From xen-devel-bounces@lists.xenproject.org Fri Aug 01 00:08:27 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 00:08:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066631.1431785 (Exim 4.92) (envelope-from ) id 1uhdJt-0000gy-Iy; Fri, 01 Aug 2025 00:08:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1066631.1431785; Fri, 01 Aug 2025 00:08:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhdJt-0000gr-FR; Fri, 01 Aug 2025 00:08:21 +0000 Received: by outflank-mailman (input) for mailman id 1066631; Fri, 01 Aug 2025 00:08:20 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhdJr-0000gl-So for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 00:08:20 +0000 Received: from tor.source.kernel.org (tor.source.kernel.org [172.105.4.254]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a041f6dc-6e6b-11f0-a320-13f23c93f187; Fri, 01 Aug 2025 02:08:18 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id B6ADF6112C; Fri, 1 Aug 2025 00:08:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BC0B3C4CEEF; Fri, 1 Aug 2025 00:08:14 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a041f6dc-6e6b-11f0-a320-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754006896; bh=lJQIBzNL1lvveTPl1/GpzzTgX4flsXoy5JpFVJH4sek=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=iqWHlRiaSt5EM0sRYeejujFmrdzm0tBI25YtuXqKpxT8qgXBrPECDHxFNP0IDOBeO bF+Ofpq4l+llH5muq6xAuPGNfOPEi4NOaKVpSYkeiFd0zQ/0BRW4Jg00p/psW1Cs5A nf1XdR5eArUZq6In7wUcXrCNmdWrUK3nnRMaZDX25gnfBZTIGlvLmUreI5eLUb0cRW zWAvmQG1EiZ2LxT4QhxftnvBuKQZG/jxddlPSrJhG8oknpkXsYYqkl8FmD8GM40rX7 oAAbx3+7mLRdwr2WxuzZ91MKIjaGXy7I4LqPfOxhV6G6VZQv9EqJ/v/HjG9w7GXyBK p3DjEBogUxZwg== Date: Thu, 31 Jul 2025 17:08:12 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: dmkhn@proton.me cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators In-Reply-To: <20250731192130.3948419-3-dmukhin@ford.com> Message-ID: References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-3-dmukhin@ford.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Thu, 31 Jul 2025, dmkhn@proton.me wrote: > From: Denis Mukhin > > Introduce a driver framework to abstract UART emulators in the hypervisor. > > That allows for architecture-independent handling of virtual UARTs in the > console driver and simplifies enabling new UART emulators. > > The framework is built under CONFIG_HAS_VUART, which will be automatically > enabled once the user enables any UART emulator. > > Current implementation supports maximum of one vUART of each kind per domain. > > Use new domain_has_vuart() in the console driver code to check whether to > forward console input to the domain using vUART. > > Note: existing vUARTs are deliberately *not* hooked to the new framework to > minimize the scope of the patch: vpl011 (i.e. SBSA) emulator and "vuart" (i.e. > minimalistic MMIO-mapped dtuart for hwdoms on Arm) are kept unmodified. > > Signed-off-by: Denis Mukhin > --- > Changes since v3: > - new patch > - original patch from ML: https://lore.kernel.org/xen-devel/20250624035443.344099-16-dmukhin@ford.com/ > --- > xen/arch/arm/xen.lds.S | 1 + > xen/arch/ppc/xen.lds.S | 1 + > xen/arch/riscv/xen.lds.S | 1 + > xen/arch/x86/xen.lds.S | 1 + > xen/common/Kconfig | 2 + > xen/common/Makefile | 1 + > xen/common/emul/Kconfig | 6 ++ > xen/common/emul/Makefile | 1 + > xen/common/emul/vuart/Kconfig | 6 ++ > xen/common/emul/vuart/Makefile | 1 + > xen/common/emul/vuart/vuart.c | 112 +++++++++++++++++++++++++++++++++ > xen/common/keyhandler.c | 3 + > xen/drivers/char/console.c | 4 ++ > xen/include/xen/vuart.h | 84 +++++++++++++++++++++++++ > xen/include/xen/xen.lds.h | 10 +++ > 15 files changed, 234 insertions(+) > create mode 100644 xen/common/emul/Kconfig > create mode 100644 xen/common/emul/Makefile > create mode 100644 xen/common/emul/vuart/Kconfig > create mode 100644 xen/common/emul/vuart/Makefile > create mode 100644 xen/common/emul/vuart/vuart.c > create mode 100644 xen/include/xen/vuart.h > > diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S > index 9f30c3a13ed1..bdba7eaa4f65 100644 > --- a/xen/arch/arm/xen.lds.S > +++ b/xen/arch/arm/xen.lds.S > @@ -58,6 +58,7 @@ SECTIONS > *(.rodata) > *(.rodata.*) > VPCI_ARRAY > + VUART_ARRAY > *(.data.rel.ro) > *(.data.rel.ro.*) > > diff --git a/xen/arch/ppc/xen.lds.S b/xen/arch/ppc/xen.lds.S > index 1de0b77fc6b9..f9d4e5b0dcd8 100644 > --- a/xen/arch/ppc/xen.lds.S > +++ b/xen/arch/ppc/xen.lds.S > @@ -52,6 +52,7 @@ SECTIONS > *(.rodata) > *(.rodata.*) > VPCI_ARRAY > + VUART_ARRAY > *(.data.rel.ro) > *(.data.rel.ro.*) > > diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S > index edcadff90bfe..59dcaa5fef9a 100644 > --- a/xen/arch/riscv/xen.lds.S > +++ b/xen/arch/riscv/xen.lds.S > @@ -47,6 +47,7 @@ SECTIONS > *(.rodata) > *(.rodata.*) > VPCI_ARRAY > + VUART_ARRAY > *(.data.rel.ro) > *(.data.rel.ro.*) > > diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S > index 8e9cac75b09e..43426df33092 100644 > --- a/xen/arch/x86/xen.lds.S > +++ b/xen/arch/x86/xen.lds.S > @@ -136,6 +136,7 @@ SECTIONS > *(.rodata) > *(.rodata.*) > VPCI_ARRAY > + VUART_ARRAY > *(.data.rel.ro) > *(.data.rel.ro.*) > > diff --git a/xen/common/Kconfig b/xen/common/Kconfig > index 16936418a6e6..4e0bd524dc43 100644 > --- a/xen/common/Kconfig > +++ b/xen/common/Kconfig > @@ -1,6 +1,8 @@ > > menu "Common Features" > > +source "common/emul/Kconfig" > + > config COMPAT > bool > help > diff --git a/xen/common/Makefile b/xen/common/Makefile > index c316957fcb36..c0734480ee4b 100644 > --- a/xen/common/Makefile > +++ b/xen/common/Makefile > @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o > obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/ > obj-$(CONFIG_IOREQ_SERVER) += dm.o > obj-y += domain.o > +obj-y += emul/ > obj-y += event_2l.o > obj-y += event_channel.o > obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o > diff --git a/xen/common/emul/Kconfig b/xen/common/emul/Kconfig > new file mode 100644 > index 000000000000..7c6764d1756b > --- /dev/null > +++ b/xen/common/emul/Kconfig > @@ -0,0 +1,6 @@ > +menu "Domain Emulation Features" > + visible if EXPERT > + > +source "common/emul/vuart/Kconfig" > + > +endmenu > diff --git a/xen/common/emul/Makefile b/xen/common/emul/Makefile > new file mode 100644 > index 000000000000..670682102c13 > --- /dev/null > +++ b/xen/common/emul/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_HAS_VUART) += vuart/ > diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kconfig > new file mode 100644 > index 000000000000..02f7dd6dc1a1 > --- /dev/null > +++ b/xen/common/emul/vuart/Kconfig > @@ -0,0 +1,6 @@ > +config HAS_VUART > + bool > + > +menu "UART Emulation" > + > +endmenu > diff --git a/xen/common/emul/vuart/Makefile b/xen/common/emul/vuart/Makefile > new file mode 100644 > index 000000000000..c6400b001e85 > --- /dev/null > +++ b/xen/common/emul/vuart/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_HAS_VUART) += vuart.o > diff --git a/xen/common/emul/vuart/vuart.c b/xen/common/emul/vuart/vuart.c > new file mode 100644 > index 000000000000..14a7f8bd8b79 > --- /dev/null > +++ b/xen/common/emul/vuart/vuart.c > @@ -0,0 +1,112 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * UART emulator framework. > + * > + * Copyright 2025 Ford Motor Company > + */ > + > +#include > +#include > +#include > + > +#define VUART_ARRAY_SIZE (__start_vuart_end - __start_vuart_array) > + > +#define for_each_vuart(vdev) \ > + for (unsigned __i = 0; \ > + __i < VUART_ARRAY_SIZE && (vdev = __start_vuart_array[__i], 1); \ > + __i++) > + > +extern const struct vuart_ops *const __start_vuart_array[]; > +extern const struct vuart_ops *const __start_vuart_end[]; > + > +int vuart_add_node(struct domain *d, const void *node) > +{ > + const struct vuart_ops *vdev; > + int rc; > + > + for_each_vuart(vdev) > + { > + if ( !vdev->add_node ) > + continue; > + > + rc = vdev->add_node(d, node); > + if ( rc ) > + return rc; > + } > + > + return 0; > +} Maybe skip this function until we needed? Without the reference implementation of vuart-ns16550.c it is hard to tell what it is supposed to do. > +int vuart_init(struct domain *d, struct vuart_params *params) > +{ > + const struct vuart_ops *vdev; > + int rc; > + > + if ( !domain_has_vuart(d) ) > + return 0; > + > + for_each_vuart(vdev) > + { > + rc = vdev->init(d, params); > + if ( rc ) > + return rc; > + } > + > + d->console.input_allowed = true; This works because there is only one emulator (NS16550) but if there were multiple possible emulators, I think we would want to only initialize the emulator enabled in the specific domain. One domain could only have NS16550 and another domain could only have PL011, while both NS16550 and PL011 might be possible. I think it is OK for now and this function can be fixed/improved when adding the second emulator. > + return 0; > +} > + > +/* > + * Release any resources taken by UART emulators. > + * > + * NB: no flags are cleared, since currently exit() is called only during > + * domain destroy. > + */ > +void vuart_deinit(struct domain *d) > +{ > + const struct vuart_ops *vdev; > + > + for_each_vuart(vdev) > + vdev->deinit(d); > +} > + > +void vuart_dump_state(const struct domain *d) > +{ > + const struct vuart_ops *vdev; > + > + for_each_vuart(vdev) > + vdev->dump_state(d); > +} > + > +/* > + * Put character to the first suitable emulated UART's FIFO. > + */ > +int vuart_put_rx(struct domain *d, char c) > +{ > + const struct vuart_ops *vdev = NULL; > + > + ASSERT(domain_has_vuart(d)); > + > + for_each_vuart(vdev) > + if ( vdev->put_rx ) > + break; > + > + return vdev ? vdev->put_rx(d, c) : -ENODEV; I don't think this would work with multiple emulators possible, maybe enable or maybe not, for the same domain. In a situation where there is both PL011 and NS16550 enable in the Xen kconfig, but only NS16550 enabled for this specific domain, for_each_vuart might find PL011 as the first emulator with a put_rx implementation, but it is not actually the one the domain can use. I think this is OK for now, but it would have to be fixed when adding a second emulator. > +} > + > +bool domain_has_vuart(const struct domain *d) > +{ > + uint32_t mask = 0; > + > + return !!(d->emulation_flags & mask); > +} > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/common/keyhandler.c b/xen/common/keyhandler.c > index eccd97c565c6..af427d25dc0d 100644 > --- a/xen/common/keyhandler.c > +++ b/xen/common/keyhandler.c > @@ -22,6 +22,7 @@ > #include > #include > #include > +#include > #include > > static unsigned char keypress_key; > @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char key) > v->periodic_period / 1000000); > } > } > + > + vuart_dump_state(d); > } > > for_each_domain ( d ) > diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c > index 963c7b043cd8..93254979817b 100644 > --- a/xen/drivers/char/console.c > +++ b/xen/drivers/char/console.c > @@ -33,6 +33,7 @@ > #include > #include > #include > +#include > > #ifdef CONFIG_X86 > #include > @@ -601,6 +602,7 @@ static void __serial_rx(char c) > /* > * Deliver input to the hardware domain buffer, unless it is > * already full. > + * NB: must be the first check: hardware domain may have emulated UART. > */ > if ( (serial_rx_prod - serial_rx_cons) != SERIAL_RX_SIZE ) > serial_rx_ring[SERIAL_RX_MASK(serial_rx_prod++)] = c; > @@ -611,6 +613,8 @@ static void __serial_rx(char c) > */ > send_global_virq(VIRQ_CONSOLE); > } > + else if ( domain_has_vuart(d) ) > + rc = vuart_put_rx(d, c); > #ifdef CONFIG_SBSA_VUART_CONSOLE > else > /* Deliver input to the emulated UART. */ > diff --git a/xen/include/xen/vuart.h b/xen/include/xen/vuart.h > new file mode 100644 > index 000000000000..e843026df4b1 > --- /dev/null > +++ b/xen/include/xen/vuart.h > @@ -0,0 +1,84 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * UART emulator framework. > + * > + * Copyright 2025 Ford Motor Company > + */ > + > +#ifndef XEN_VUART_H > +#define XEN_VUART_H > + > +#include > +#include > +#include > + > +struct vuart_params { > + domid_t console_domid; > + gfn_t gfn; > + evtchn_port_t evtchn; > +}; > + > +struct vuart_ops { > + int (*add_node)(struct domain *d, const void *node); > + int (*init)(struct domain *d, struct vuart_params *params); > + void (*deinit)(struct domain *d); > + void (*dump_state)(const struct domain *d); > + int (*put_rx)(struct domain *d, char c); > +}; > + > +#define VUART_REGISTER(name, x) \ > + static const struct vuart_ops *const __name##_entry \ > + __used_section(".data.vuart." #name) = (x); > + > +#ifdef CONFIG_HAS_VUART > + > +int vuart_add_node(struct domain *d, const void *node); > +int vuart_init(struct domain *d, struct vuart_params *params); > +void vuart_deinit(struct domain *d); > +void vuart_dump_state(const struct domain *d); > +int vuart_put_rx(struct domain *d, char c); > +bool domain_has_vuart(const struct domain *d); > + > +#else > + > +static inline int vuart_add_node(struct domain *d, const void *node) > +{ > + return 0; > +} > + > +static inline int vuart_init(struct domain *d, struct vuart_params *params) > +{ > + return 0; > +} > + > +static inline void vuart_deinit(struct domain *d) > +{ > +} > + > +static inline void vuart_dump_state(const struct domain *d) > +{ > +} > + > +static inline int vuart_put_rx(struct domain *d, char c) > +{ > + ASSERT_UNREACHABLE(); > + return -ENODEV; > +} > + > +static inline bool domain_has_vuart(const struct domain *d) > +{ > + return false; > +} > + > +#endif /* CONFIG_HAS_VUART */ > + > +#endif /* XEN_VUART_H */ > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/xen/xen.lds.h b/xen/include/xen/xen.lds.h > index b126dfe88792..c2da180948ca 100644 > --- a/xen/include/xen/xen.lds.h > +++ b/xen/include/xen/xen.lds.h > @@ -194,4 +194,14 @@ > #define VPCI_ARRAY > #endif > > +#ifdef CONFIG_HAS_VUART > +#define VUART_ARRAY \ > + . = ALIGN(POINTER_ALIGN); \ > + __start_vuart_array = .; \ > + *(SORT(.data.vuart.*)) \ > + __start_vuart_end = .; > +#else > +#define VUART_ARRAY > +#endif > + > #endif /* __XEN_LDS_H__ */ > -- > 2.34.1 > > From xen-devel-bounces@lists.xenproject.org Fri Aug 01 00:10:20 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 00:10:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066638.1431795 (Exim 4.92) (envelope-from ) id 1uhdLn-0002AL-UT; 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Fri, 1 Aug 2025 00:10:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB335C4CEF7; Fri, 1 Aug 2025 00:10:14 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e763c998-6e6b-11f0-a320-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754007016; bh=ABITAMX6yrmcnsQg+uqPo44MlCfP6dZUlwqGmgZN1s8=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=Ew2+r1fpQQ5doti1EOh678reX4CB+QcADL7/ihsqOU1OyE6us1honi+b78jOFk+H0 TF318gn8ve1qlemQ/F0Tds60pXE7HDngKYS3kUsyayHUytPBHkvppyAu9jz3CSKHAt OPjPc3dOfcs37Bx36FASfH/Ni0XLWp4t/35o9iNF3wV0U5lqwUx136CQ37objdxKHA wAv2RjlkEYXPuaALFzvh6JU1Oy+wfWU2T6tjVOUeeQ2MJRch5WbdSvq30CrTiP7fbB ugOjnRy7ltxKYnmTcAjt316g5GtX8cTvutiDb0kRtkEKe+hRLYStvamRpF9ER0xchL E2Fj18x17sI6w== Date: Thu, 31 Jul 2025 17:10:12 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: dmkhn@proton.me cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com Subject: Re: [PATCH v4 8/8] emul/vuart: introduce console forwarding enforcement via vUART In-Reply-To: <20250731192130.3948419-9-dmukhin@ford.com> Message-ID: References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-9-dmukhin@ford.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Thu, 31 Jul 2025, dmkhn@proton.me wrote: > From: Denis Mukhin > > It may be useful to enforce console forwarding over the virtual UART. E.g. > hardware domain uses PV console by default, but it may be necessary to have > console forwarded to the hardware domain via emulated UART. > > Add CONFIG_VUART_CONSOLE_FOCUS to enforce such behavior. > > Signed-off-by: Denis Mukhin I realize that hyperlaunch is not merged yet, but I think this one would be best as a hyperlaunch configuration option rather than a kconfig. But it is certainly useful for testing until Hyperlaunch is merged! > --- > Changes since v3: > - new patch > --- > xen/arch/x86/domain.c | 6 ++++++ > xen/common/emul/vuart/Kconfig | 5 +++++ > xen/drivers/char/console.c | 2 +- > 3 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c > index 39b0c0b199b9..40ff92ad6c61 100644 > --- a/xen/arch/x86/domain.c > +++ b/xen/arch/x86/domain.c > @@ -848,6 +848,12 @@ int arch_domain_create(struct domain *d, > if ( is_hardware_domain(d) && is_pv_domain(d) ) > emflags |= XEN_X86_EMU_PIT; > > + if ( IS_ENABLED(CONFIG_VUART_CONSOLE_FOCUS) && > + IS_ENABLED(CONFIG_VUART_NS16550) && > + is_hardware_domain(d) && > + is_hvm_domain(d) ) > + emflags |= XEN_X86_EMU_NS16550; > + > if ( emflags & ~XEN_X86_EMU_ALL ) > { > printk(XENLOG_G_ERR > diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kconfig > index ebefd90d913e..1069ca95f2db 100644 > --- a/xen/common/emul/vuart/Kconfig > +++ b/xen/common/emul/vuart/Kconfig > @@ -51,4 +51,9 @@ config VUART_NS16550_DEBUG > help > Enable development debugging. > > +config VUART_CONSOLE_FOCUS > + bool "Console input forwarding via UART emulator" > + help > + Enable physical console input forwarding to guest OS via emulated UART. > + > endmenu > diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c > index 93254979817b..d142f5511d61 100644 > --- a/xen/drivers/char/console.c > +++ b/xen/drivers/char/console.c > @@ -597,7 +597,7 @@ static void __serial_rx(char c) > if ( !d ) > return; > > - if ( is_hardware_domain(d) ) > + if ( !IS_ENABLED(CONFIG_VUART_CONSOLE_FOCUS) && is_hardware_domain(d) ) > { > /* > * Deliver input to the hardware domain buffer, unless it is > -- > 2.34.1 > > From xen-devel-bounces@lists.xenproject.org Fri Aug 01 00:46:57 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 00:46:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066645.1431806 (Exim 4.92) (envelope-from ) id 1uhdv4-0006Tw-F1; Fri, 01 Aug 2025 00:46:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1066645.1431806; Fri, 01 Aug 2025 00:46:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhdv4-0006Tp-CE; Fri, 01 Aug 2025 00:46:46 +0000 Received: by outflank-mailman (input) for mailman id 1066645; Fri, 01 Aug 2025 00:46:45 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhdv3-0006Tg-7Y for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 00:46:45 +0000 Received: from tor.source.kernel.org (tor.source.kernel.org [2600:3c04:e001:324:0:1991:8:25]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fdd3cfb9-6e70-11f0-a320-13f23c93f187; Fri, 01 Aug 2025 02:46:43 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 680536020E; Fri, 1 Aug 2025 00:46:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5CCDC4CEEF; Fri, 1 Aug 2025 00:46:39 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fdd3cfb9-6e70-11f0-a320-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754009201; bh=CCe2GZHM4uVATboKMdjFdbk2lwhfV2iwx9tR1JVkoiw=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=J0bp/24nPISprMc84zATF5LGaYN34pjygGGNjDi0pazLNDJGnEF2ClQKAOavx21Zo ibwirPqFttW6qFHeAlOaTck0zwL8kCCKXBGTt/ODeOmfughk7gl0HOK3IAskmb0Rm7 96+tLbUHFkWPwCLJi0nkiL+JaY6CQ5cmdhkeAhe0WE+riVTw6TorIcMj3ZggPAZsUf kEwToXiwtlGYBgSvnd9Hy0DKt02YbMV1M4fZVnY5Af1y6kwEnnUzUQx+DtQnP9LP+m IAX2XyOU8VlMKch1oisT5HDNf97aIvYWu18a4MS7KfYmjjKG2jnvCeTJUwr2SIbJm9 Zb1ZMePL2Schg== Date: Thu, 31 Jul 2025 17:46:37 -0700 (PDT) From: Stefano Stabellini X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop To: dmkhn@proton.me cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com Subject: Re: [PATCH v4 7/8] tools/xl: enable NS16550-compatible UART emulator for PVH (x86) In-Reply-To: <20250731192130.3948419-8-dmukhin@ford.com> Message-ID: References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-8-dmukhin@ford.com> User-Agent: Alpine 2.22 (DEB 394 2020-01-19) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Thu, 31 Jul 2025, dmkhn@proton.me wrote: > From: Denis Mukhin > > Enable virtual NS16550 for PVH domains in xl. > > {map,unmap}_domain_emuirq_pirq() infrastructure is modified by adding new > type of interrupt resources 'IRQ_EMU' which means 'emulated device IRQ' > (similarly to IRQ_MSI_EMU). > > This is necessary to for IOAPIC emulation code to skip IRQ->PIRQ mapping > (vioapic_hwdom_map_gsi()) when guest OS unmasks vIOAPIC pin corresponding to > virtual device's IRQ. > > Also, hvm_gsi_eoi() is modified to trigger assertion in hvm_gsi_deassert() > path for ISA IRQs. > > Signed-off-by: Denis Mukhin > --- > Changes since v3: > - new patch > --- > tools/libs/light/libxl_x86.c | 2 +- > xen/arch/x86/domain.c | 2 ++ > xen/arch/x86/hvm/vioapic.c | 10 ++++++++++ > xen/arch/x86/include/asm/irq.h | 1 + > xen/common/emul/vuart/vuart-ns16550.c | 27 +++++++++++++++++++++++++-- > xen/drivers/passthrough/x86/hvm.c | 9 ++++----- > 6 files changed, 43 insertions(+), 8 deletions(-) > > diff --git a/tools/libs/light/libxl_x86.c b/tools/libs/light/libxl_x86.c > index 0f039ca65a88..a40647c06cb9 100644 > --- a/tools/libs/light/libxl_x86.c > +++ b/tools/libs/light/libxl_x86.c > @@ -54,7 +54,7 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, > break; > case LIBXL_DOMAIN_TYPE_PVH: > config->arch.emulation_flags = XEN_X86_EMU_LAPIC; > - libxl__arch_domain_vuart_unsupported(gc, d_config, config); > + libxl__arch_domain_vuart_enable(gc, d_config, config); > break; > case LIBXL_DOMAIN_TYPE_PV: > config->arch.emulation_flags = 0; > diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c > index 6a010a509a60..39b0c0b199b9 100644 > --- a/xen/arch/x86/domain.c > +++ b/xen/arch/x86/domain.c > @@ -769,12 +769,14 @@ static bool emulation_flags_ok(const struct domain *d, uint32_t emflags) > { > .caps = CAP_HVM | CAP_HWDOM, > .min = X86_EMU_LAPIC | X86_EMU_IOAPIC | X86_EMU_VPCI, > + .opt = X86_EMU_NS16550, > }, > > /* PVH domU */ > { > .caps = CAP_HVM | CAP_DOMU, > .min = X86_EMU_LAPIC, > + .opt = X86_EMU_NS16550, > }, > > /* HVM domU */ > diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c > index 7c725f9e471f..86fe3aa4a201 100644 > --- a/xen/arch/x86/hvm/vioapic.c > +++ b/xen/arch/x86/hvm/vioapic.c > @@ -177,6 +177,16 @@ static int vioapic_hwdom_map_gsi(unsigned int gsi, unsigned int trig, > > ASSERT(is_hardware_domain(currd)); > > + /* > + * Interrupt is claimed by one of the platform virtual devices (e.g. > + * NS16550); do nothing. > + */ > + read_lock(&currd->event_lock); > + ret = domain_pirq_to_emuirq(currd, gsi); > + read_unlock(&currd->event_lock); > + if ( ret != IRQ_UNBOUND ) > + return 0; > + > /* Interrupt has been unmasked, bind it now. */ > ret = mp_register_gsi(gsi, trig, pol); > if ( ret == -EEXIST ) > diff --git a/xen/arch/x86/include/asm/irq.h b/xen/arch/x86/include/asm/irq.h > index 8c81f66434a8..731d2bbbb1b4 100644 > --- a/xen/arch/x86/include/asm/irq.h > +++ b/xen/arch/x86/include/asm/irq.h > @@ -221,6 +221,7 @@ void cleanup_domain_irq_mapping(struct domain *d); > #define IRQ_UNBOUND (-1) > #define IRQ_PT (-2) > #define IRQ_MSI_EMU (-3) > +#define IRQ_EMU (-4) > > bool cpu_has_pending_apic_eoi(void); > > diff --git a/xen/common/emul/vuart/vuart-ns16550.c b/xen/common/emul/vuart/vuart-ns16550.c > index 48bbf58264fe..9ec9aed2c594 100644 > --- a/xen/common/emul/vuart/vuart-ns16550.c > +++ b/xen/common/emul/vuart/vuart-ns16550.c > @@ -355,7 +355,9 @@ static void ns16550_irq_assert(const struct vuart_ns16550 *vdev) > struct domain *d = vdev->owner; > int vector; > > - if ( has_vpic(d) ) /* HVM */ > + if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */ > + vector = hvm_ioapic_assert(d, vdev->irq, false); > + else if ( has_vpic(d) ) /* HVM */ > vector = hvm_isa_irq_assert(d, vdev->irq, vioapic_get_vector); > else > ASSERT_UNREACHABLE(); > @@ -367,7 +369,9 @@ static void ns16550_irq_deassert(const struct vuart_ns16550 *vdev) > { > struct domain *d = vdev->owner; > > - if ( has_vpic(d) ) /* HVM */ > + if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */ > + hvm_ioapic_deassert(d, vdev->irq); > + else if ( has_vpic(d) ) /* HVM */ > hvm_isa_irq_deassert(d, vdev->irq); > else > ASSERT_UNREACHABLE(); > @@ -889,6 +893,17 @@ static int cf_check ns16550_init(struct domain *d, > return rc; > } > > + /* Claim virtual IRQ */ > + write_lock(&d->event_lock); > + rc = map_domain_emuirq_pirq(d, r->addr, IRQ_EMU); > + write_unlock(&d->event_lock); > + if ( rc ) > + { > + pr_err("%s: virtual IRQ#%"PRIu64": cannot claim: %d\n", > + desc->name, r->addr, rc); > + return rc; > + } > + > vdev->irq = r->addr; > } > else > @@ -919,12 +934,20 @@ static int cf_check ns16550_init(struct domain *d, > static void cf_check ns16550_deinit(struct domain *d) > { > struct vuart_ns16550 *vdev = d->arch.hvm.vuart; > + int rc; > > if ( !vdev ) > return; > > spin_lock(&vdev->lock); > > + rc = unmap_domain_pirq_emuirq(vdev->owner, vdev->irq); > + if ( rc ) > + { > + pr_err("%s: virtual IRQ#%d: cannot unclaim: %d\n", > + vdev->name, vdev->irq, rc); > + } write_lock(&d->event_lock); ? > ns16550_fifo_tx_flush(vdev); > > spin_unlock(&vdev->lock); > diff --git a/xen/drivers/passthrough/x86/hvm.c b/xen/drivers/passthrough/x86/hvm.c > index a2ca7e0e570c..22905cd86f95 100644 > --- a/xen/drivers/passthrough/x86/hvm.c > +++ b/xen/drivers/passthrough/x86/hvm.c > @@ -924,12 +924,11 @@ static void hvm_gsi_eoi(struct domain *d, unsigned int gsi) > { > struct pirq *pirq = pirq_info(d, gsi); > > - /* Check if GSI is actually mapped. */ > - if ( !pirq_dpci(pirq) ) > - return; > - > hvm_gsi_deassert(d, gsi); > - hvm_pirq_eoi(pirq); > + > + /* Check if GSI is actually mapped. */ > + if ( pirq_dpci(pirq) ) > + hvm_pirq_eoi(pirq); > } > > static int cf_check _hvm_dpci_isairq_eoi( > -- > 2.34.1 > > From xen-devel-bounces@lists.xenproject.org Fri Aug 01 01:51:37 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 01:51:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066685.1431816 (Exim 4.92) (envelope-from ) id 1uhevd-0005l7-1e; Fri, 01 Aug 2025 01:51:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1066685.1431816; Fri, 01 Aug 2025 01:51:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhevc-0005l0-Ue; Fri, 01 Aug 2025 01:51:24 +0000 Received: by outflank-mailman (input) for mailman id 1066685; Fri, 01 Aug 2025 01:51:23 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uheva-0005ku-Jb for xen-devel@lists.xenproject.org; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, Jul 31, 2025 at 05:10:12PM -0700, Stefano Stabellini wrote: > On Thu, 31 Jul 2025, dmkhn@proton.me wrote: > > From: Denis Mukhin > > > > It may be useful to enforce console forwarding over the virtual UART. E= .g. > > hardware domain uses PV console by default, but it may be necessary to = have > > console forwarded to the hardware domain via emulated UART. > > > > Add CONFIG_VUART_CONSOLE_FOCUS to enforce such behavior. > > > > Signed-off-by: Denis Mukhin >=20 > I realize that hyperlaunch is not merged yet, but I think this one would > be best as a hyperlaunch configuration option rather than a kconfig. But > it is certainly useful for testing until Hyperlaunch is merged! Yep, I used that to test PVH dom0 w/ emulator. re: configuration option: I agree and, initially I wanted to hook a flag to= xl / dom0 command line opton which will say that emulated UART can accept physical input. But then decided to hook such capability via Kconfig for simplicity. >=20 >=20 > > --- > > Changes since v3: > > - new patch > > --- > > xen/arch/x86/domain.c | 6 ++++++ > > xen/common/emul/vuart/Kconfig | 5 +++++ > > xen/drivers/char/console.c | 2 +- > > 3 files changed, 12 insertions(+), 1 deletion(-) > > > > diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c > > index 39b0c0b199b9..40ff92ad6c61 100644 > > --- a/xen/arch/x86/domain.c > > +++ b/xen/arch/x86/domain.c > > @@ -848,6 +848,12 @@ int arch_domain_create(struct domain *d, > > if ( is_hardware_domain(d) && is_pv_domain(d) ) > > emflags |=3D XEN_X86_EMU_PIT; > > > > + if ( IS_ENABLED(CONFIG_VUART_CONSOLE_FOCUS) && > > + IS_ENABLED(CONFIG_VUART_NS16550) && > > + is_hardware_domain(d) && > > + is_hvm_domain(d) ) > > + emflags |=3D XEN_X86_EMU_NS16550; > > + > > if ( emflags & ~XEN_X86_EMU_ALL ) > > { > > printk(XENLOG_G_ERR > > diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kcon= fig > > index ebefd90d913e..1069ca95f2db 100644 > > --- a/xen/common/emul/vuart/Kconfig > > +++ b/xen/common/emul/vuart/Kconfig > > @@ -51,4 +51,9 @@ config VUART_NS16550_DEBUG > > =09help > > =09 Enable development debugging. > > > > +config VUART_CONSOLE_FOCUS > > +=09bool "Console input forwarding via UART emulator" > > +=09help > > +=09 Enable physical console input forwarding to guest OS via emulated= UART. > > + > > endmenu > > diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c > > index 93254979817b..d142f5511d61 100644 > > --- a/xen/drivers/char/console.c > > +++ b/xen/drivers/char/console.c > > @@ -597,7 +597,7 @@ static void __serial_rx(char c) > > if ( !d ) > > return; > > > > - if ( is_hardware_domain(d) ) > > + if ( !IS_ENABLED(CONFIG_VUART_CONSOLE_FOCUS) && is_hardware_domain= (d) ) > > { > > /* > > * Deliver input to the hardware domain buffer, unless it is > > -- > > 2.34.1 > > > > From xen-devel-bounces@lists.xenproject.org Fri Aug 01 01:53:28 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 01:53:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066692.1431826 (Exim 4.92) (envelope-from ) id 1uhexb-0006Fs-BZ; Fri, 01 Aug 2025 01:53:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1066692.1431826; Fri, 01 Aug 2025 01:53:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhexb-0006Fl-8s; Fri, 01 Aug 2025 01:53:27 +0000 Received: by outflank-mailman (input) for mailman id 1066692; Fri, 01 Aug 2025 01:53:25 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhexZ-0006Fd-Bi for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 01:53:25 +0000 Received: from mail-10630.protonmail.ch (mail-10630.protonmail.ch [79.135.106.30]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 4c93842b-6e7a-11f0-b895-0df219b8e170; Fri, 01 Aug 2025 03:53:20 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4c93842b-6e7a-11f0-b895-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1754013198; x=1754272398; bh=7nYRYqyTpkgbjg/kvxtm6yMNGst/fiy6u+RTeI0aUws=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=jpDsMic2y/zW2RVS0DfcNfKXUJswslWWPT6hyUFFY+1aDO96R3d01b14LiB6Kz2m2 jzMD0l84kQEx29FbmUDG0T3UxcrbMdlGnU9Y18D9KReOxfdbtZVy5riiqvFzpfBzx2 yqW7pHQrrbVvZmeFN572mCagij61QtI8IAEkU07Cgao9hCZVITuVtTsyadLMQ3XkPX yqzbLCpNCtpWvvyfPyXmr4cgixkTgeh8Tw3r4BIRKSA4IAJGTH/GCSR9rqv3c8DxVV jZrr5QSx/XzmKdvHZxPV1oYBtfnL2MhJPUs76eUTrAr3AYT+HWIzbYZR40AmDHno4T BOmLLYJ5JmU/w== Date: Fri, 01 Aug 2025 01:53:15 +0000 To: Stefano Stabellini From: dmkhn@proton.me Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, dmukhin@ford.com Subject: Re: [PATCH v4 7/8] tools/xl: enable NS16550-compatible UART emulator for PVH (x86) Message-ID: In-Reply-To: References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-8-dmukhin@ford.com> Feedback-ID: 123220910:user:proton X-Pm-Message-ID: 8f4c468e05c200e7f27a76b99b5a5a339d6daabc MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, Jul 31, 2025 at 05:46:37PM -0700, Stefano Stabellini wrote: > On Thu, 31 Jul 2025, dmkhn@proton.me wrote: > > From: Denis Mukhin > > > > Enable virtual NS16550 for PVH domains in xl. > > > > {map,unmap}_domain_emuirq_pirq() infrastructure is modified by adding n= ew > > type of interrupt resources 'IRQ_EMU' which means 'emulated device IRQ' > > (similarly to IRQ_MSI_EMU). > > > > This is necessary to for IOAPIC emulation code to skip IRQ->PIRQ mappin= g > > (vioapic_hwdom_map_gsi()) when guest OS unmasks vIOAPIC pin correspondi= ng to > > virtual device's IRQ. > > > > Also, hvm_gsi_eoi() is modified to trigger assertion in hvm_gsi_deasser= t() > > path for ISA IRQs. > > > > Signed-off-by: Denis Mukhin > > --- > > Changes since v3: > > - new patch > > --- > > tools/libs/light/libxl_x86.c | 2 +- > > xen/arch/x86/domain.c | 2 ++ > > xen/arch/x86/hvm/vioapic.c | 10 ++++++++++ > > xen/arch/x86/include/asm/irq.h | 1 + > > xen/common/emul/vuart/vuart-ns16550.c | 27 +++++++++++++++++++++++++-- > > xen/drivers/passthrough/x86/hvm.c | 9 ++++----- > > 6 files changed, 43 insertions(+), 8 deletions(-) > > > > diff --git a/tools/libs/light/libxl_x86.c b/tools/libs/light/libxl_x86.= c > > index 0f039ca65a88..a40647c06cb9 100644 > > --- a/tools/libs/light/libxl_x86.c > > +++ b/tools/libs/light/libxl_x86.c > > @@ -54,7 +54,7 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, > > break; > > case LIBXL_DOMAIN_TYPE_PVH: > > config->arch.emulation_flags =3D XEN_X86_EMU_LAPIC; > > - libxl__arch_domain_vuart_unsupported(gc, d_config, config); > > + libxl__arch_domain_vuart_enable(gc, d_config, config); > > break; > > case LIBXL_DOMAIN_TYPE_PV: > > config->arch.emulation_flags =3D 0; > > diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c > > index 6a010a509a60..39b0c0b199b9 100644 > > --- a/xen/arch/x86/domain.c > > +++ b/xen/arch/x86/domain.c > > @@ -769,12 +769,14 @@ static bool emulation_flags_ok(const struct domai= n *d, uint32_t emflags) > > { > > .caps =3D CAP_HVM | CAP_HWDOM, > > .min =3D X86_EMU_LAPIC | X86_EMU_IOAPIC | X86_EMU_VPCI, > > + .opt =3D X86_EMU_NS16550, > > }, > > > > /* PVH domU */ > > { > > .caps =3D CAP_HVM | CAP_DOMU, > > .min =3D X86_EMU_LAPIC, > > + .opt =3D X86_EMU_NS16550, > > }, > > > > /* HVM domU */ > > diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c > > index 7c725f9e471f..86fe3aa4a201 100644 > > --- a/xen/arch/x86/hvm/vioapic.c > > +++ b/xen/arch/x86/hvm/vioapic.c > > @@ -177,6 +177,16 @@ static int vioapic_hwdom_map_gsi(unsigned int gsi,= unsigned int trig, > > > > ASSERT(is_hardware_domain(currd)); > > > > + /* > > + * Interrupt is claimed by one of the platform virtual devices (e.= g. > > + * NS16550); do nothing. > > + */ > > + read_lock(&currd->event_lock); > > + ret =3D domain_pirq_to_emuirq(currd, gsi); > > + read_unlock(&currd->event_lock); > > + if ( ret !=3D IRQ_UNBOUND ) > > + return 0; > > + > > /* Interrupt has been unmasked, bind it now. */ > > ret =3D mp_register_gsi(gsi, trig, pol); > > if ( ret =3D=3D -EEXIST ) > > diff --git a/xen/arch/x86/include/asm/irq.h b/xen/arch/x86/include/asm/= irq.h > > index 8c81f66434a8..731d2bbbb1b4 100644 > > --- a/xen/arch/x86/include/asm/irq.h > > +++ b/xen/arch/x86/include/asm/irq.h > > @@ -221,6 +221,7 @@ void cleanup_domain_irq_mapping(struct domain *d); > > #define IRQ_UNBOUND (-1) > > #define IRQ_PT (-2) > > #define IRQ_MSI_EMU (-3) > > +#define IRQ_EMU (-4) > > > > bool cpu_has_pending_apic_eoi(void); > > > > diff --git a/xen/common/emul/vuart/vuart-ns16550.c b/xen/common/emul/vu= art/vuart-ns16550.c > > index 48bbf58264fe..9ec9aed2c594 100644 > > --- a/xen/common/emul/vuart/vuart-ns16550.c > > +++ b/xen/common/emul/vuart/vuart-ns16550.c > > @@ -355,7 +355,9 @@ static void ns16550_irq_assert(const struct vuart_n= s16550 *vdev) > > struct domain *d =3D vdev->owner; > > int vector; > > > > - if ( has_vpic(d) ) /* HVM */ > > + if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */ > > + vector =3D hvm_ioapic_assert(d, vdev->irq, false); > > + else if ( has_vpic(d) ) /* HVM */ > > vector =3D hvm_isa_irq_assert(d, vdev->irq, vioapic_get_vector= ); > > else > > ASSERT_UNREACHABLE(); > > @@ -367,7 +369,9 @@ static void ns16550_irq_deassert(const struct vuart= _ns16550 *vdev) > > { > > struct domain *d =3D vdev->owner; > > > > - if ( has_vpic(d) ) /* HVM */ > > + if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */ > > + hvm_ioapic_deassert(d, vdev->irq); > > + else if ( has_vpic(d) ) /* HVM */ > > hvm_isa_irq_deassert(d, vdev->irq); > > else > > ASSERT_UNREACHABLE(); > > @@ -889,6 +893,17 @@ static int cf_check ns16550_init(struct domain *d, > > return rc; > > } > > > > + /* Claim virtual IRQ */ > > + write_lock(&d->event_lock); > > + rc =3D map_domain_emuirq_pirq(d, r->addr, IRQ_EMU); > > + write_unlock(&d->event_lock); > > + if ( rc ) > > + { > > + pr_err("%s: virtual IRQ#%"PRIu64": cannot claim: %d\n"= , > > + desc->name, r->addr, rc); > > + return rc; > > + } > > + > > vdev->irq =3D r->addr; > > } > > else > > @@ -919,12 +934,20 @@ static int cf_check ns16550_init(struct domain *d= , > > static void cf_check ns16550_deinit(struct domain *d) > > { > > struct vuart_ns16550 *vdev =3D d->arch.hvm.vuart; > > + int rc; > > > > if ( !vdev ) > > return; > > > > spin_lock(&vdev->lock); > > > > + rc =3D unmap_domain_pirq_emuirq(vdev->owner, vdev->irq); > > + if ( rc ) > > + { > > + pr_err("%s: virtual IRQ#%d: cannot unclaim: %d\n", > > + vdev->name, vdev->irq, rc); > > + } >=20 > write_lock(&d->event_lock); ? Thanks >=20 >=20 > > ns16550_fifo_tx_flush(vdev); > > > > spin_unlock(&vdev->lock); > > diff --git a/xen/drivers/passthrough/x86/hvm.c b/xen/drivers/passthroug= h/x86/hvm.c > > index a2ca7e0e570c..22905cd86f95 100644 > > --- a/xen/drivers/passthrough/x86/hvm.c > > +++ b/xen/drivers/passthrough/x86/hvm.c > > @@ -924,12 +924,11 @@ static void hvm_gsi_eoi(struct domain *d, unsigne= d int gsi) > > { > > struct pirq *pirq =3D pirq_info(d, gsi); > > > > - /* Check if GSI is actually mapped. */ > > - if ( !pirq_dpci(pirq) ) > > - return; > > - > > hvm_gsi_deassert(d, gsi); > > - hvm_pirq_eoi(pirq); > > + > > + /* Check if GSI is actually mapped. */ > > + if ( pirq_dpci(pirq) ) > > + hvm_pirq_eoi(pirq); > > } > > > > static int cf_check _hvm_dpci_isairq_eoi( > > -- > > 2.34.1 > > > > From xen-devel-bounces@lists.xenproject.org Fri Aug 01 02:55:33 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 02:55:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066714.1431837 (Exim 4.92) (envelope-from ) id 1uhfvT-0004Sc-Lb; Fri, 01 Aug 2025 02:55:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1066714.1431837; Fri, 01 Aug 2025 02:55:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhfvT-0004SR-Go; Fri, 01 Aug 2025 02:55:19 +0000 Received: by outflank-mailman (input) for mailman id 1066714; Fri, 01 Aug 2025 02:55:19 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhfvR-0004SL-MF for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 02:55:18 +0000 Received: from mail-10630.protonmail.ch (mail-10630.protonmail.ch [79.135.106.30]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id eb451092-6e82-11f0-b895-0df219b8e170; Fri, 01 Aug 2025 04:55:02 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: eb451092-6e82-11f0-b895-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1754016900; x=1754276100; bh=Napq1dcokFlHl192BT4BGuzTFYfN6exzUs9vCudnwY8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=LFEq/YdJiiofRgjY5jso45nxvBYe8QVLqUjMMhJ3uXBieJcs7OjXeDheEHNY3dD95 +h0OlBjgjJFH1SUauv0lY/l7bBoE7L8Eqe15MB9fvyuK7S+ipHYPrOOTIaA+QzV0DI fvIZbORYUmvcKI0IkeExHk4ICQRoL0k4eEhiOpDPDBRsM1nszBLNp0+CDQc4/cPBxf 3vf+MnhxN/KFTJlJ3plkvxYrvyShR+ZBn77kTlwUJbzUKS5IKQBsjVu9lD2HCM6lAW 2IUS3MsjWT7r2KijgjhQnLrCBwRh1rfVX44KDaNSW81pSTf+WX2bMwK1uzHlUvbDxe tgrCs6RVRCIFw== Date: Fri, 01 Aug 2025 02:54:55 +0000 To: Stefano Stabellini From: dmkhn@proton.me Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, dmukhin@ford.com Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators Message-ID: In-Reply-To: References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-3-dmukhin@ford.com> Feedback-ID: 123220910:user:proton X-Pm-Message-ID: 34bc334a8b66cd8bd857de2903400591bf71ecef MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, Jul 31, 2025 at 05:08:12PM -0700, Stefano Stabellini wrote: > On Thu, 31 Jul 2025, dmkhn@proton.me wrote: > > From: Denis Mukhin > > > > Introduce a driver framework to abstract UART emulators in the hypervis= or. > > > > That allows for architecture-independent handling of virtual UARTs in t= he > > console driver and simplifies enabling new UART emulators. > > > > The framework is built under CONFIG_HAS_VUART, which will be automatica= lly > > enabled once the user enables any UART emulator. > > > > Current implementation supports maximum of one vUART of each kind per d= omain. > > > > Use new domain_has_vuart() in the console driver code to check whether = to > > forward console input to the domain using vUART. > > > > Note: existing vUARTs are deliberately *not* hooked to the new framewor= k to > > minimize the scope of the patch: vpl011 (i.e. SBSA) emulator and "vuart= " (i.e. > > minimalistic MMIO-mapped dtuart for hwdoms on Arm) are kept unmodified. > > > > Signed-off-by: Denis Mukhin > > --- > > Changes since v3: > > - new patch > > - original patch from ML: https://lore.kernel.org/xen-devel/20250624035= 443.344099-16-dmukhin@ford.com/ > > --- > > xen/arch/arm/xen.lds.S | 1 + > > xen/arch/ppc/xen.lds.S | 1 + > > xen/arch/riscv/xen.lds.S | 1 + > > xen/arch/x86/xen.lds.S | 1 + > > xen/common/Kconfig | 2 + > > xen/common/Makefile | 1 + > > xen/common/emul/Kconfig | 6 ++ > > xen/common/emul/Makefile | 1 + > > xen/common/emul/vuart/Kconfig | 6 ++ > > xen/common/emul/vuart/Makefile | 1 + > > xen/common/emul/vuart/vuart.c | 112 +++++++++++++++++++++++++++++++++ > > xen/common/keyhandler.c | 3 + > > xen/drivers/char/console.c | 4 ++ > > xen/include/xen/vuart.h | 84 +++++++++++++++++++++++++ > > xen/include/xen/xen.lds.h | 10 +++ > > 15 files changed, 234 insertions(+) > > create mode 100644 xen/common/emul/Kconfig > > create mode 100644 xen/common/emul/Makefile > > create mode 100644 xen/common/emul/vuart/Kconfig > > create mode 100644 xen/common/emul/vuart/Makefile > > create mode 100644 xen/common/emul/vuart/vuart.c > > create mode 100644 xen/include/xen/vuart.h > > > > diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S > > index 9f30c3a13ed1..bdba7eaa4f65 100644 > > --- a/xen/arch/arm/xen.lds.S > > +++ b/xen/arch/arm/xen.lds.S > > @@ -58,6 +58,7 @@ SECTIONS > > *(.rodata) > > *(.rodata.*) > > VPCI_ARRAY > > + VUART_ARRAY > > *(.data.rel.ro) > > *(.data.rel.ro.*) > > > > diff --git a/xen/arch/ppc/xen.lds.S b/xen/arch/ppc/xen.lds.S > > index 1de0b77fc6b9..f9d4e5b0dcd8 100644 > > --- a/xen/arch/ppc/xen.lds.S > > +++ b/xen/arch/ppc/xen.lds.S > > @@ -52,6 +52,7 @@ SECTIONS > > *(.rodata) > > *(.rodata.*) > > VPCI_ARRAY > > + VUART_ARRAY > > *(.data.rel.ro) > > *(.data.rel.ro.*) > > > > diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S > > index edcadff90bfe..59dcaa5fef9a 100644 > > --- a/xen/arch/riscv/xen.lds.S > > +++ b/xen/arch/riscv/xen.lds.S > > @@ -47,6 +47,7 @@ SECTIONS > > *(.rodata) > > *(.rodata.*) > > VPCI_ARRAY > > + VUART_ARRAY > > *(.data.rel.ro) > > *(.data.rel.ro.*) > > > > diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S > > index 8e9cac75b09e..43426df33092 100644 > > --- a/xen/arch/x86/xen.lds.S > > +++ b/xen/arch/x86/xen.lds.S > > @@ -136,6 +136,7 @@ SECTIONS > > *(.rodata) > > *(.rodata.*) > > VPCI_ARRAY > > + VUART_ARRAY > > *(.data.rel.ro) > > *(.data.rel.ro.*) > > > > diff --git a/xen/common/Kconfig b/xen/common/Kconfig > > index 16936418a6e6..4e0bd524dc43 100644 > > --- a/xen/common/Kconfig > > +++ b/xen/common/Kconfig > > @@ -1,6 +1,8 @@ > > > > menu "Common Features" > > > > +source "common/emul/Kconfig" > > + > > config COMPAT > > =09bool > > =09help > > diff --git a/xen/common/Makefile b/xen/common/Makefile > > index c316957fcb36..c0734480ee4b 100644 > > --- a/xen/common/Makefile > > +++ b/xen/common/Makefile > > @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) +=3D d= evice.o > > obj-$(CONFIG_DEVICE_TREE_PARSE) +=3D device-tree/ > > obj-$(CONFIG_IOREQ_SERVER) +=3D dm.o > > obj-y +=3D domain.o > > +obj-y +=3D emul/ > > obj-y +=3D event_2l.o > > obj-y +=3D event_channel.o > > obj-$(CONFIG_EVTCHN_FIFO) +=3D event_fifo.o > > diff --git a/xen/common/emul/Kconfig b/xen/common/emul/Kconfig > > new file mode 100644 > > index 000000000000..7c6764d1756b > > --- /dev/null > > +++ b/xen/common/emul/Kconfig > > @@ -0,0 +1,6 @@ > > +menu "Domain Emulation Features" > > +=09visible if EXPERT > > + > > +source "common/emul/vuart/Kconfig" > > + > > +endmenu > > diff --git a/xen/common/emul/Makefile b/xen/common/emul/Makefile > > new file mode 100644 > > index 000000000000..670682102c13 > > --- /dev/null > > +++ b/xen/common/emul/Makefile > > @@ -0,0 +1 @@ > > +obj-$(CONFIG_HAS_VUART) +=3D vuart/ > > diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kcon= fig > > new file mode 100644 > > index 000000000000..02f7dd6dc1a1 > > --- /dev/null > > +++ b/xen/common/emul/vuart/Kconfig > > @@ -0,0 +1,6 @@ > > +config HAS_VUART > > +=09bool > > + > > +menu "UART Emulation" > > + > > +endmenu > > diff --git a/xen/common/emul/vuart/Makefile b/xen/common/emul/vuart/Mak= efile > > new file mode 100644 > > index 000000000000..c6400b001e85 > > --- /dev/null > > +++ b/xen/common/emul/vuart/Makefile > > @@ -0,0 +1 @@ > > +obj-$(CONFIG_HAS_VUART) +=3D vuart.o > > diff --git a/xen/common/emul/vuart/vuart.c b/xen/common/emul/vuart/vuar= t.c > > new file mode 100644 > > index 000000000000..14a7f8bd8b79 > > --- /dev/null > > +++ b/xen/common/emul/vuart/vuart.c > > @@ -0,0 +1,112 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * UART emulator framework. > > + * > > + * Copyright 2025 Ford Motor Company > > + */ > > + > > +#include > > +#include > > +#include > > + > > +#define VUART_ARRAY_SIZE (__start_vuart_end - __start_vuart_array) > > + > > +#define for_each_vuart(vdev) \ > > + for (unsigned __i =3D 0; \ > > + __i < VUART_ARRAY_SIZE && (vdev =3D __start_vuart_array[__i],= 1); \ > > + __i++) > > + > > +extern const struct vuart_ops *const __start_vuart_array[]; > > +extern const struct vuart_ops *const __start_vuart_end[]; > > + > > +int vuart_add_node(struct domain *d, const void *node) > > +{ > > + const struct vuart_ops *vdev; > > + int rc; > > + > > + for_each_vuart(vdev) > > + { > > + if ( !vdev->add_node ) > > + continue; > > + > > + rc =3D vdev->add_node(d, node); > > + if ( rc ) > > + return rc; > > + } > > + > > + return 0; > > +} >=20 > Maybe skip this function until we needed? Without the reference > implementation of vuart-ns16550.c it is hard to tell what it is supposed > to do. Ack >=20 >=20 > > +int vuart_init(struct domain *d, struct vuart_params *params) > > +{ > > + const struct vuart_ops *vdev; > > + int rc; > > + > > + if ( !domain_has_vuart(d) ) > > + return 0; > > + > > + for_each_vuart(vdev) > > + { > > + rc =3D vdev->init(d, params); > > + if ( rc ) > > + return rc; > > + } > > + > > + d->console.input_allowed =3D true; >=20 > This works because there is only one emulator (NS16550) but if there > were multiple possible emulators, I think we would want to only > initialize the emulator enabled in the specific domain. There are two emulators simultenously on Arm: "vuart", i.e. hwdom dtuart for earlycon and "vpl011", i.e. SBSA. >=20 > One domain could only have NS16550 and another domain could only have > PL011, while both NS16550 and PL011 might be possible. >=20 > I think it is OK for now and this function can be fixed/improved when > adding the second emulator. >=20 >=20 > > + return 0; > > +} > > + > > +/* > > + * Release any resources taken by UART emulators. > > + * > > + * NB: no flags are cleared, since currently exit() is called only dur= ing > > + * domain destroy. > > + */ > > +void vuart_deinit(struct domain *d) > > +{ > > + const struct vuart_ops *vdev; > > + > > + for_each_vuart(vdev) > > + vdev->deinit(d); > > +} > > + > > +void vuart_dump_state(const struct domain *d) > > +{ > > + const struct vuart_ops *vdev; > > + > > + for_each_vuart(vdev) > > + vdev->dump_state(d); > > +} > > + > > +/* > > + * Put character to the first suitable emulated UART's FIFO. > > + */ > > +int vuart_put_rx(struct domain *d, char c) > > +{ > > + const struct vuart_ops *vdev =3D NULL; > > + > > + ASSERT(domain_has_vuart(d)); > > + > > + for_each_vuart(vdev) > > + if ( vdev->put_rx ) > > + break; > > + > > + return vdev ? vdev->put_rx(d, c) : -ENODEV; >=20 > I don't think this would work with multiple emulators possible, maybe > enable or maybe not, for the same domain. >=20 > In a situation where there is both PL011 and NS16550 enable in the Xen > kconfig, but only NS16550 enabled for this specific domain, > for_each_vuart might find PL011 as the first emulator with a put_rx > implementation, but it is not actually the one the domain can use. Yes, multiple vUARTs will need more work. >=20 > I think this is OK for now, but it would have to be fixed when adding a > second emulator. >=20 >=20 > > +} > > + > > +bool domain_has_vuart(const struct domain *d) > > +{ > > + uint32_t mask =3D 0; > > + > > + return !!(d->emulation_flags & mask); > > +} > > + > > +/* > > + * Local variables: > > + * mode: C > > + * c-file-style: "BSD" > > + * c-basic-offset: 4 > > + * indent-tabs-mode: nil > > + * End: > > + */ > > diff --git a/xen/common/keyhandler.c b/xen/common/keyhandler.c > > index eccd97c565c6..af427d25dc0d 100644 > > --- a/xen/common/keyhandler.c > > +++ b/xen/common/keyhandler.c > > @@ -22,6 +22,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > static unsigned char keypress_key; > > @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char key= ) > > v->periodic_period / 1000000); > > } > > } > > + > > + vuart_dump_state(d); > > } > > > > for_each_domain ( d ) > > diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c > > index 963c7b043cd8..93254979817b 100644 > > --- a/xen/drivers/char/console.c > > +++ b/xen/drivers/char/console.c > > @@ -33,6 +33,7 @@ > > #include > > #include > > #include > > +#include > > > > #ifdef CONFIG_X86 > > #include > > @@ -601,6 +602,7 @@ static void __serial_rx(char c) > > /* > > * Deliver input to the hardware domain buffer, unless it is > > * already full. > > + * NB: must be the first check: hardware domain may have emula= ted UART. > > */ > > if ( (serial_rx_prod - serial_rx_cons) !=3D SERIAL_RX_SIZE ) > > serial_rx_ring[SERIAL_RX_MASK(serial_rx_prod++)] =3D c; > > @@ -611,6 +613,8 @@ static void __serial_rx(char c) > > */ > > send_global_virq(VIRQ_CONSOLE); > > } > > + else if ( domain_has_vuart(d) ) > > + rc =3D vuart_put_rx(d, c); > > #ifdef CONFIG_SBSA_VUART_CONSOLE > > else > > /* Deliver input to the emulated UART. */ > > diff --git a/xen/include/xen/vuart.h b/xen/include/xen/vuart.h > > new file mode 100644 > > index 000000000000..e843026df4b1 > > --- /dev/null > > +++ b/xen/include/xen/vuart.h > > @@ -0,0 +1,84 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * UART emulator framework. > > + * > > + * Copyright 2025 Ford Motor Company > > + */ > > + > > +#ifndef XEN_VUART_H > > +#define XEN_VUART_H > > + > > +#include > > +#include > > +#include > > + > > +struct vuart_params { > > + domid_t console_domid; > > + gfn_t gfn; > > + evtchn_port_t evtchn; > > +}; > > + > > +struct vuart_ops { > > + int (*add_node)(struct domain *d, const void *node); > > + int (*init)(struct domain *d, struct vuart_params *params); > > + void (*deinit)(struct domain *d); > > + void (*dump_state)(const struct domain *d); > > + int (*put_rx)(struct domain *d, char c); > > +}; > > + > > +#define VUART_REGISTER(name, x) \ > > + static const struct vuart_ops *const __name##_entry \ > > + __used_section(".data.vuart." #name) =3D (x); > > + > > +#ifdef CONFIG_HAS_VUART > > + > > +int vuart_add_node(struct domain *d, const void *node); > > +int vuart_init(struct domain *d, struct vuart_params *params); > > +void vuart_deinit(struct domain *d); > > +void vuart_dump_state(const struct domain *d); > > +int vuart_put_rx(struct domain *d, char c); > > +bool domain_has_vuart(const struct domain *d); > > + > > +#else > > + > > +static inline int vuart_add_node(struct domain *d, const void *node) > > +{ > > + return 0; > > +} > > + > > +static inline int vuart_init(struct domain *d, struct vuart_params *pa= rams) > > +{ > > + return 0; > > +} > > + > > +static inline void vuart_deinit(struct domain *d) > > +{ > > +} > > + > > +static inline void vuart_dump_state(const struct domain *d) > > +{ > > +} > > + > > +static inline int vuart_put_rx(struct domain *d, char c) > > +{ > > + ASSERT_UNREACHABLE(); > > + return -ENODEV; > > +} > > + > > +static inline bool domain_has_vuart(const struct domain *d) > > +{ > > + return false; > > +} > > + > > +#endif /* CONFIG_HAS_VUART */ > > + > > +#endif /* XEN_VUART_H */ > > + > > +/* > > + * Local variables: > > + * mode: C > > + * c-file-style: "BSD" > > + * c-basic-offset: 4 > > + * indent-tabs-mode: nil > > + * End: > > + */ > > diff --git a/xen/include/xen/xen.lds.h b/xen/include/xen/xen.lds.h > > index b126dfe88792..c2da180948ca 100644 > > --- a/xen/include/xen/xen.lds.h > > +++ b/xen/include/xen/xen.lds.h > > @@ -194,4 +194,14 @@ > > #define VPCI_ARRAY > > #endif > > > > +#ifdef CONFIG_HAS_VUART > > +#define VUART_ARRAY \ > > + . =3D ALIGN(POINTER_ALIGN); \ > > + __start_vuart_array =3D .; \ > > + *(SORT(.data.vuart.*)) \ > > + __start_vuart_end =3D .; > > +#else > > +#define VUART_ARRAY > > +#endif > > + > > #endif /* __XEN_LDS_H__ */ > > -- > > 2.34.1 > > > > From xen-devel-bounces@lists.xenproject.org Fri Aug 01 02:57:11 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 02:57:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066724.1431845 (Exim 4.92) (envelope-from ) id 1uhfxG-00050p-2S; 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a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1754017025; x=1754276225; bh=CbLxfbhmKTEJANfkftWsM0RVXlGMNTWhuSK7vBajsd8=; h=Date:To:From:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=BFeaqeQOXBhjQXAuHGIsd4jPEdD6Y7ssvCgcQZmecEk9v6Dugcdm6XIDcNz83FYu8 U0iX8MKLyBat4aPR3+JsJJSAt8lfA5OpRyb/rSAMC9O3M6uE1pT/gR0qrdYl3I5aE0 dQxxfgBjAwTF0hI4BHssYAc+O8ek6cIhfNWw3596aOSEtkLEbIyv9RXEhjPUzOXkuO ZoyUlO9TzhmfhT/u5gEZjmWoYLqkDvFEwpDivrNJ/3sD/cOFpF6HvA3C8LVe0NB7EO 5A7PP1beLvTCWUDZzu7M8To+glghjO8udlnMdlJxnNafW3fL5kWZdzexU9rBenElhh R+qIzgyQ1p5Kw== Date: Fri, 01 Aug 2025 02:57:01 +0000 To: Grygorii Strashko , xen-devel@lists.xenproject.org From: dmkhn@proton.me Subject: Re: [PATCH v4 3/8] x86/domain: allocate d->{iomem,irq}_caps before arch-specific initialization Message-ID: In-Reply-To: References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-4-dmukhin@ford.com> <6f209ee9-cf3c-473f-92d5-0c1f0fbc2e49@epam.com> Feedback-ID: 123220910:user:proton X-Pm-Message-ID: 87fbc0b7c86ebca73383c85ec2487ed2facda496 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, Jul 31, 2025 at 08:21:24PM +0000, dmkhn@proton.me wrote: > On Thu, Jul 31, 2025 at 10:52:08PM +0300, Grygorii Strashko wrote: > > Hi Denis, > > > > On 31.07.25 22:21, dmkhn@proton.me wrote: > > > From: Denis Mukhin > > > > > > Move IRQ/IOMEM rangesets allocation before arch_domain_create(). > > > > > > That guarantees that arch-specific code could access those rangesets = to > > > register traps for emulation. > > > > > > It is necessary for those emulators registering trap handlers and ens= uring > > > that emulated IRQs are not shared with the physical IRQs. > > > > > > Move dom0_setup_permissions() call right after I/O rangesets are allo= cated. > > > > > > Move pvh_setup_mmcfg() inside dom0_setup_permissions() close to the p= lace > > > where MMCFG ranges are initialized. > > > > > > Not a functional change. > > > > > > Signed-off-by: Denis Mukhin > > > --- > > > Chanhes since v3: > > > - new patch > > > --- > > > xen/arch/x86/dom0_build.c | 26 +++++++++++++++++++++++ > > > xen/arch/x86/hvm/dom0_build.c | 39 --------------------------------= --- > > > xen/arch/x86/hvm/hvm.c | 16 ++++++++++++++ > > > xen/common/domain.c | 12 +++++------ > > > 4 files changed, 48 insertions(+), 45 deletions(-) > > > > > > diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c > > > index 0b467fd4a4fc..e965f506a3c8 100644 > > > --- a/xen/arch/x86/dom0_build.c > > > +++ b/xen/arch/x86/dom0_build.c > > > @@ -471,6 +471,24 @@ static void __init process_dom0_ioports_disable(= struct domain *dom0) > > > } > > > } > > > > > > +static void __hwdom_init setup_mmcfg(struct domain *d) > > > +{ > > > + unsigned int i; > > > + int rc; > > > + > > > + for ( i =3D 0; i < pci_mmcfg_config_num; i++ ) > > > + { > > > + rc =3D register_vpci_mmcfg_handler(d, pci_mmcfg_config[i].ad= dress, > > > + pci_mmcfg_config[i].start_b= us_number, > > > + pci_mmcfg_config[i].end_bus= _number, > > > + pci_mmcfg_config[i].pci_seg= ment); > > > + if ( rc ) > > > + printk("Unable to setup MMCFG handler at %#lx for segmen= t %u\n", > > > + pci_mmcfg_config[i].address, > > > + pci_mmcfg_config[i].pci_segment); > > > + } > > > +} > > > + > > > int __init dom0_setup_permissions(struct domain *d) > > > > It could be i'm missing smth, but ^ function is __init while ... > > > > > { > > > unsigned long mfn; > > > @@ -480,6 +498,14 @@ int __init dom0_setup_permissions(struct domain = *d) > > > if ( pv_shim ) > > > return 0; > > > > > > + /* > > > + * MMCFG initialization must be performed before setting domain > > > + * permissions, as the MCFG areas must not be part of the domain= IOMEM > > > + * accessible regions. > > > + */ > > > + if ( is_hvm_domain(d) ) > > > + setup_mmcfg(d); > > > + > > > /* The hardware domain is initially permitted full I/O capabili= ties. */ > > > rc =3D ioports_permit_access(d, 0, 0xFFFF); > > > rc |=3D iomem_permit_access(d, 0UL, > > > diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_bu= ild.c > > > index 5551f9044836..6f47c9eeeaa6 100644 > > > --- a/xen/arch/x86/hvm/dom0_build.c > > > +++ b/xen/arch/x86/hvm/dom0_build.c > > > @@ -1310,24 +1310,6 @@ static int __init pvh_setup_acpi(struct domain= *d, paddr_t start_info) > > > return 0; > > > } > > > > > > -static void __hwdom_init pvh_setup_mmcfg(struct domain *d) > > > -{ > > > - unsigned int i; > > > - int rc; > > > - > > > - for ( i =3D 0; i < pci_mmcfg_config_num; i++ ) > > > - { > > > - rc =3D register_vpci_mmcfg_handler(d, pci_mmcfg_config[i].ad= dress, > > > - pci_mmcfg_config[i].start_b= us_number, > > > - pci_mmcfg_config[i].end_bus= _number, > > > - pci_mmcfg_config[i].pci_seg= ment); > > > - if ( rc ) > > > - printk("Unable to setup MMCFG handler at %#lx for segmen= t %u\n", > > > - pci_mmcfg_config[i].address, > > > - pci_mmcfg_config[i].pci_segment); > > > - } > > > -} > > > - > > > int __init dom0_construct_pvh(const struct boot_domain *bd) > > > { > > > paddr_t entry, start_info; > > > @@ -1339,27 +1321,6 @@ int __init dom0_construct_pvh(const struct boo= t_domain *bd) > > > if ( bd->kernel =3D=3D NULL ) > > > panic("Missing kernel boot module for %pd construction\n", = d); > > > > > > - if ( is_hardware_domain(d) ) > > > - { > > > - /* > > > - * MMCFG initialization must be performed before setting dom= ain > > > - * permissions, as the MCFG areas must not be part of the do= main IOMEM > > > - * accessible regions. > > > - */ > > > - pvh_setup_mmcfg(d); > > > - > > > - /* > > > - * Setup permissions early so that calls to add MMIO regions= to the > > > - * p2m as part of vPCI setup don't fail due to permission ch= ecks. > > > - */ > > > - rc =3D dom0_setup_permissions(d); > > > - if ( rc ) > > > - { > > > - printk("%pd unable to setup permissions: %d\n", d, rc); > > > - return rc; > > > - } > > > - } > > > - > > > /* > > > * Craft dom0 physical memory map and set the paging allocation= . This must > > > * be done before the iommu initializion, since iommu initializ= ation code > > > diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c > > > index cb8ecd050d41..b7edb1d6555d 100644 > > > --- a/xen/arch/x86/hvm/hvm.c > > > +++ b/xen/arch/x86/hvm/hvm.c > > > @@ -35,6 +35,7 @@ > > > #include > > > #include > > > #include > > > +#include > > > #include > > > #include > > > #include > > > @@ -651,6 +652,17 @@ int hvm_domain_initialise(struct domain *d, > > > goto fail1; > > > } > > > memset(d->arch.hvm.io_bitmap, ~0, HVM_IOBITMAP_SIZE); > > > + > > > + /* > > > + * Setup permissions early so that calls to add MMIO regions= to the > > > + * p2m as part of vPCI setup don't fail due to permission ch= ecks. > > > + */ > > > + rc =3D dom0_setup_permissions(d); > > > > ... here hvm_domain_initialise() is not __init? >=20 > No, you're right, I missed this, thanks! >=20 > Good catch! So addressing it will require some code movement, like dom0_setup_permissions() outside of arch/x86/dom0_build.c... >=20 > > > > [...] > > > > > > -- > > Best regards, > > -grygorii > > >=20 >=20 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 03:28:32 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 03:28:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066749.1431856 (Exim 4.92) (envelope-from ) id 1uhgRV-0000cl-AA; Fri, 01 Aug 2025 03:28:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1066749.1431856; Fri, 01 Aug 2025 03:28:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhgRV-0000ce-78; Fri, 01 Aug 2025 03:28:25 +0000 Received: by outflank-mailman (input) for mailman id 1066749; Fri, 01 Aug 2025 03:28:23 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhgRS-0000cY-FK for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 03:28:23 +0000 Received: from mail-10629.protonmail.ch (mail-10629.protonmail.ch [79.135.106.29]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 91f51ed7-6e87-11f0-a320-13f23c93f187; Fri, 01 Aug 2025 05:28:21 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 91f51ed7-6e87-11f0-a320-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1754018898; x=1754278098; bh=xpQcuWE2Srq1OrS6YWkW2AaQ+rh9ZESSnvzioC/47bg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=aXFlDKW6XiLn5mn5n51o9ytQjN3y+Ngyfb5XE5BxOYIX9rwQg7KdN/dBJKVx5dVDz taU9RQ1pU6exuHLZW/Z+ibs2ChhtvkQcmm1IGa6qAd0aZvDZZvHHHGddezQaNWH1TJ /1hn+P768GCaEYoGgebiBJ/HXptutyy0JBuo3fr7hkJqXppDlem0pw876g8ILhWDW3 THZQm4yUCrq7PujEVq3u4fSDZUEwrHuBlXm0lbc7Sn1jGOkppkjyEj7LzM9VP1Qfz2 W8BgohT+WN4gdFzAlllPd+mbgP679cuRTCm7jAR3qoAY5ojkE2ZMef84SaP/c8SHVZ CsXZOrIY4Mgmg== Date: Fri, 01 Aug 2025 03:28:14 +0000 To: Stefano Stabellini From: dmkhn@proton.me Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, dmukhin@ford.com Subject: Re: [PATCH v4 5/8] emul/vuart-ns16550: introduce NS16550-compatible UART emulator (x86) Message-ID: In-Reply-To: References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-6-dmukhin@ford.com> Feedback-ID: 123220910:user:proton X-Pm-Message-ID: 3e8cdafa9f9802db10a97ac9263de613a8921cb0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, Jul 31, 2025 at 04:57:00PM -0700, Stefano Stabellini wrote: > On Thu, 31 Jul 2025, dmkhn@proton.me wrote: [..] > > +/* > > + * Emulate 8-bit write access to NS16550 register. > > + */ > > +static int ns16550_io_write8( > > + struct vuart_ns16550 *vdev, uint32_t reg, uint8_t *data) > > +{ > > + uint8_t *regs =3D vdev->regs; > > + uint8_t val =3D *data; > > + int rc =3D 0; > > + > > + if ( ns16550_dlab_get(vdev) && (reg =3D=3D UART_DLL || reg =3D=3D = UART_DLM) ) > > + regs[NS16550_REGS_NUM + reg] =3D val; > > + else > > + { > > + switch ( reg ) > > + { > > + case UART_THR: > > + if ( regs[UART_MCR] & UART_MCR_LOOP ) > > + { > > + (void)ns16550_fifo_rx_putchar(vdev, val); > > + regs[UART_LSR] |=3D UART_LSR_OE; >=20 > Why is UART_LSR_OE set unconditionally here instead of checking if > ns16550_fifo_rx_putchar returned -ENOSPC? Thanks! Yes, overrun condition should be emulated once FIFO is full. [..] > > + > > + /* Calculate changes in modem status */ > > + if ( (msr_curr & UART_MSR_CTS) ^ (msr_next & UART_MSR_CTS)= ) > > + msr_delta |=3D UART_MSR_DCTS; > > + if ( (msr_curr & UART_MCR_RTS) ^ (msr_next & UART_MCR_RTS)= ) > > + msr_delta |=3D UART_MSR_DDSR; >=20 > Should we check UART_MSR_DSR instead of UART_MCR_RTS to set > UART_MSR_DDSR ? Good catch! Thanks. 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Thu, 31 Jul 2025 22:26:54 -0700 (PDT) Message-ID: <2dd66d50-0804-4c4b-b5e9-5dd8efb27da1@suse.com> Date: Fri, 1 Aug 2025 07:26:52 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] misra: fix violations in macros GVA_INFO, TRACE_TIME To: Jan Beulich , Dmytro Prokopchuk1 Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Dario Faggioli , George Dunlap , "xen-devel@lists.xenproject.org" References: <73cfc8a2d4d66042b49f44c69e672ce8ad0556ce.1753971749.git.dmytro_prokopchuk1@epam.com> <34320c56-8c79-45d4-910c-2faa5ed4ac0b@suse.com> Content-Language: en-US From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Autocrypt: addr=jgross@suse.com; keydata= xsBNBFOMcBYBCACgGjqjoGvbEouQZw/ToiBg9W98AlM2QHV+iNHsEs7kxWhKMjrioyspZKOB ycWxw3ie3j9uvg9EOB3aN4xiTv4qbnGiTr3oJhkB1gsb6ToJQZ8uxGq2kaV2KL9650I1SJve dYm8Of8Zd621lSmoKOwlNClALZNew72NjJLEzTalU1OdT7/i1TXkH09XSSI8mEQ/ouNcMvIJ NwQpd369y9bfIhWUiVXEK7MlRgUG6MvIj6Y3Am/BBLUVbDa4+gmzDC9ezlZkTZG2t14zWPvx XP3FAp2pkW0xqG7/377qptDmrk42GlSKN4z76ELnLxussxc7I2hx18NUcbP8+uty4bMxABEB AAHNH0p1ZXJnZW4gR3Jvc3MgPGpncm9zc0BzdXNlLmNvbT7CwHkEEwECACMFAlOMcK8CGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCw3p3WKL8TL8eZB/9G0juS/kDY9LhEXseh mE9U+iA1VsLhgDqVbsOtZ/S14LRFHczNd/Lqkn7souCSoyWsBs3/wO+OjPvxf7m+Ef+sMtr0 G5lCWEWa9wa0IXx5HRPW/ScL+e4AVUbL7rurYMfwCzco+7TfjhMEOkC+va5gzi1KrErgNRHH kg3PhlnRY0Udyqx++UYkAsN4TQuEhNN32MvN0Np3WlBJOgKcuXpIElmMM5f1BBzJSKBkW0Jc Wy3h2Wy912vHKpPV/Xv7ZwVJ27v7KcuZcErtptDevAljxJtE7aJG6WiBzm+v9EswyWxwMCIO RoVBYuiocc51872tRGywc03xaQydB+9R7BHPzsBNBFOMcBYBCADLMfoA44MwGOB9YT1V4KCy vAfd7E0BTfaAurbG+Olacciz3yd09QOmejFZC6AnoykydyvTFLAWYcSCdISMr88COmmCbJzn sHAogjexXiif6ANUUlHpjxlHCCcELmZUzomNDnEOTxZFeWMTFF9Rf2k2F0Tl4E5kmsNGgtSa aMO0rNZoOEiD/7UfPP3dfh8JCQ1VtUUsQtT1sxos8Eb/HmriJhnaTZ7Hp3jtgTVkV0ybpgFg w6WMaRkrBh17mV0z2ajjmabB7SJxcouSkR0hcpNl4oM74d2/VqoW4BxxxOD1FcNCObCELfIS auZx+XT6s+CE7Qi/c44ibBMR7hyjdzWbABEBAAHCwF8EGAECAAkFAlOMcBYCGwwACgkQsN6d 1ii/Ey9D+Af/WFr3q+bg/8v5tCknCtn92d5lyYTBNt7xgWzDZX8G6/pngzKyWfedArllp0Pn fgIXtMNV+3t8Li1Tg843EXkP7+2+CQ98MB8XvvPLYAfW8nNDV85TyVgWlldNcgdv7nn1Sq8g HwB2BHdIAkYce3hEoDQXt/mKlgEGsLpzJcnLKimtPXQQy9TxUaLBe9PInPd+Ohix0XOlY+Uk QFEx50Ki3rSDl2Zt2tnkNYKUCvTJq7jvOlaPd6d/W0tZqpyy7KVay+K4aMobDsodB3dvEAs6 ScCnh03dDAFgIq5nsB11j3KPKdVoPlfucX2c7kGNH+LUMbzqV6beIENfNexkOfxHfw== In-Reply-To: <34320c56-8c79-45d4-910c-2faa5ed4ac0b@suse.com> Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------dgUcIXRa1XjzNC9A0HdOtVz2" This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------dgUcIXRa1XjzNC9A0HdOtVz2 Content-Type: multipart/mixed; boundary="------------kv3oNgFE2TsryMcUjS7I9f2s"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Jan Beulich , Dmytro Prokopchuk1 Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Dario Faggioli , George Dunlap , "xen-devel@lists.xenproject.org" Message-ID: <2dd66d50-0804-4c4b-b5e9-5dd8efb27da1@suse.com> Subject: Re: [PATCH] misra: fix violations in macros GVA_INFO, TRACE_TIME References: <73cfc8a2d4d66042b49f44c69e672ce8ad0556ce.1753971749.git.dmytro_prokopchuk1@epam.com> <34320c56-8c79-45d4-910c-2faa5ed4ac0b@suse.com> In-Reply-To: <34320c56-8c79-45d4-910c-2faa5ed4ac0b@suse.com> Autocrypt-Gossip: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJ3BBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AAIQkQoDSui/t3IH4WIQQ+pJkfkcoLMCa4X6CgNK6L+3cgfgn7AJ9DmMd0SMJE ePbc7/m22D2v04iu7ACffXTdZQhNl557tJuDXZSBxDmW/tLOwU0EWTecRBAIAIK5OMKMU5R2 Lk2bbjgX7vyQuCFFyKf9rC/4itNwhYWFSlKzVj3WJBDsoi2KvPm7AI+XB6NIkNAkshL5C0kd pcNd5Xo0jRR5/WE/bT7LyrJ0OJWS/qUit5eNNvsO+SxGAk28KRa1ieVLeZi9D03NL0+HIAtZ tecfqwgl3Y72UpLUyt+r7LQhcI/XR5IUUaD4C/chB4Vq2QkDKO7Q8+2HJOrFIjiVli4lU+Sf OBp64m//Y1xys++Z4ODoKh7tkh5DxiO3QBHG7bHK0CSQsJ6XUvPVYubAuy1XfSDzSeSBl//C v78Fclb+gi9GWidSTG/4hsEzd1fY5XwCZG/XJJY9M/sAAwUH/09Ar9W2U1Qm+DwZeP2ii3Ou 14Z9VlVVPhcEmR/AFykL9dw/OV2O/7cdi52+l00reUu6Nd4Dl8s4f5n8b1YFzmkVVIyhwjvU jxtPyUgDOt6DRa+RaDlXZZmxQyWcMv2anAgYWGVszeB8Myzsw8y7xhBEVV1S+1KloCzw4V8Z DSJrcsZlyMDoiTb7FyqxwQnM0f6qHxWbmOOnbzJmBqpNpFuDcz/4xNsymJylm6oXiucHQBAP Xb/cE1YNHpuaH4SRhIxwQilCYEznWowQphNAbJtEKOmcocY7EbSt8VjXTzmYENkIfkrHRyXQ dUm5AoL51XZljkCqNwrADGkTvkwsWSvCSQQYEQIACQUCWTecRAIbDAAKCRCgNK6L+3cgfuef AJ9wlZQNQUp0KwEf8Tl37RmcxCL4bQCcC5alCSMzUBJ5DBIcR4BY+CyQFAs= --------------kv3oNgFE2TsryMcUjS7I9f2s Content-Type: multipart/mixed; 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Thu, 31 Jul 2025 22:55:20 -0700 (PDT) Message-ID: <4f12dbce-29a2-4fba-9a44-669109fed450@suse.com> Date: Fri, 1 Aug 2025 07:55:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] misra: allow discarding 'noreturn' during function pointer conversions To: Dmytro Prokopchuk1 Cc: Nicola Vetrini , Doug Goldstein , Stefano Stabellini , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , "xen-devel@lists.xenproject.org" References: <63d5d311e6502d5b957009be59e1c97599015b46.1753911912.git.dmytro_prokopchuk1@epam.com> <46e8dd16-11e4-4d96-95cb-f13b652e7317@suse.com> <0999ccba-37cf-4222-8b6e-82aa95371b75@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <0999ccba-37cf-4222-8b6e-82aa95371b75@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 18:48, Dmytro Prokopchuk1 wrote: > > > On 7/31/25 10:20, Jan Beulich wrote: >> On 30.07.2025 23:47, Dmytro Prokopchuk1 wrote: >>> --- a/docs/misra/deviations.rst >>> +++ b/docs/misra/deviations.rst >>> @@ -342,6 +342,12 @@ Deviations related to MISRA C:2012 Rules: >>> semantics that do not lead to unexpected behaviour. >>> - Tagged as `safe` for ECLAIR. >>> >>> + * - R11.1 >>> + - The conversion from 'void noreturn (*)(void *)' to 'void (*)(void *)' >>> + is safe because the semantics of the 'noreturn' attribute do not alter >>> + the calling convention or behavior of the resulting code. >>> + - Tagged as `safe` for ECLAIR. >> >> As before, imo such a deviation should be generic, i.e. here independent >> of what parameters a function takes. If that can't be easily expressed >> to Eclair, then that wants stating as a justification for the >> deviations.ecl change to not fully cover the deviation we put in place. >> Having the textual deviation generic means later possible needs can be >> easily addressed by just a deviations.ecl change, without any adjustment >> to the deviations themselves. >> >> Jan > > Hi, Jan > > Currently Eclair checks exact pointer type 'void (*)(void *)', as > described in the configuration: > > to(type(pointer(inner(return(builtin(void))&&all_param(1, > pointer(builtin(void))))))) > > Nicola wrote: "then if it needs to be extended when more cases emerge I > can do that". > > So, for clarification. > > 1. In the file "deviations.ecl" I leave exist description and config: > "The conversion from 'void noreturn (*)(void *)' to 'void (*)(void *)' > is safe because the semantics of the 'noreturn' attribute do not alter > the calling convention or behavior of the resulting code." > > 2. In the file "deviations.rst" I change the description to: > "The conversion from `void noreturn (*)(...)` to `void (*)(...)` > is safe because the semantics of the 'noreturn' attribute do not alter > the calling convention or behavior of the resulting code, parameter > handling remain consistent." > > 3. In the file "rules.rst" I change the description to: > "Conversions from 'void noreturn (*)(...)' to 'void (*)(...)' are > permitted." > > It means that only "deviations.ecl" needs to be updated if a new > deviation needs to be addressed. > > > Is it OK? Yes, with the patch description also suitably adjusted. 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Thu, 31 Jul 2025 22:59:30 -0700 (PDT) Message-ID: <69c7e79b-944a-432c-b86a-6cc73d94fc08@suse.com> Date: Fri, 1 Aug 2025 07:59:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 1/3] vmx: Rewrite vpid_sync_vcpu_gva To: Teddy Astie Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 31.07.2025 18:18, Teddy Astie wrote: > Le 31/07/2025 à 17:54, Jan Beulich a écrit : >> On 26.06.2025 16:01, Teddy Astie wrote: >>> Rewrite this function such as it doesn't rely on goto, also change the >>> type of "type" to match the __invvpid function call. >> >> While this type change is probably okay (and benign to code generation), ... >> >>> --- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h >>> +++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h >>> @@ -287,10 +287,10 @@ extern uint8_t posted_intr_vector; >>> #define cpu_has_vmx_vpid_invvpid_single_context_retaining_global \ >>> (vmx_caps.vpid & VMX_VPID_INVVPID_SINGLE_CONTEXT_RETAINING_GLOBAL) >>> >>> -#define INVVPID_INDIVIDUAL_ADDR 0 >>> -#define INVVPID_SINGLE_CONTEXT 1 >>> -#define INVVPID_ALL_CONTEXT 2 >>> -#define INVVPID_SINGLE_CONTEXT_RETAINING_GLOBAL 3 >>> +#define INVVPID_INDIVIDUAL_ADDR 0UL >>> +#define INVVPID_SINGLE_CONTEXT 1UL >>> +#define INVVPID_ALL_CONTEXT 2UL >>> +#define INVVPID_SINGLE_CONTEXT_RETAINING_GLOBAL 3UL >> >> ... I don't follow the need for these extra adjustments. Preferably with >> them dropped > > With the type change from int to unsigned long to match __invvpid() > parameter, IIUC MISRA rule 7.2 requires that integer literals that are > used for unsigned must have the proper suffix. No, it doesn't. Please re-read carefully what docs/misra/rules.rst says in this regard. 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Thu, 31 Jul 2025 23:03:06 -0700 (PDT) Message-ID: <65e288b7-d8fe-409e-a287-69b4dc29f0c2@suse.com> Date: Fri, 1 Aug 2025 08:02:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 12/16] xen/domain: introduce domain-emu.h To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, oleksii.kurochko@gmail.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250624035443.344099-1-dmukhin@ford.com> <20250624035443.344099-13-dmukhin@ford.com> <33f98fe5-9b29-43e4-a87d-19eafb30f281@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 22:55, dmkhn@proton.me wrote: > On Wed, Jul 09, 2025 at 04:57:44PM +0200, Jan Beulich wrote: >> On 24.06.2025 05:56, dmkhn@proton.me wrote: >>> @@ -458,16 +459,16 @@ struct arch_domain >>> } __cacheline_aligned; >>> >>> #ifdef CONFIG_HVM >>> -#define X86_EMU_LAPIC XEN_X86_EMU_LAPIC >>> -#define X86_EMU_HPET XEN_X86_EMU_HPET >>> -#define X86_EMU_PM XEN_X86_EMU_PM >>> -#define X86_EMU_RTC XEN_X86_EMU_RTC >>> -#define X86_EMU_IOAPIC XEN_X86_EMU_IOAPIC >>> -#define X86_EMU_PIC XEN_X86_EMU_PIC >>> -#define X86_EMU_VGA XEN_X86_EMU_VGA >>> -#define X86_EMU_IOMMU XEN_X86_EMU_IOMMU >>> -#define X86_EMU_USE_PIRQ XEN_X86_EMU_USE_PIRQ >>> -#define X86_EMU_VPCI XEN_X86_EMU_VPCI >> >> The old code deliberately used values from the public interface. > > In next version I am building, I moved all of XEN_X86_EMU_XXX definitions as > is to a new public header under include/public/xen-emu.h: > > https://gitlab.com/xen-project/people/dmukhin/xen/-/commit/9b0bc5ffa5710114df8523ae2aa7680b7c6f0942 > > That looks less invasive. > > Will that work? > > There should be a common header with emulation flags somewhere, since > there will be SBSA and hwdom vUART definitions there. Yet will there be a strict need for any constants to be identical (i.e. not only have the same name, but also the same value) across architectures? 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b=OV3zYUbJQDdaaFjN36IOWyzgHqWvV2tDr8wf4ITcmC+gggnGKgCqheUbBfXdwLjsSEF0vQyX/0wmV3BfghnRfmywWMRt0G3EWm5ySDeY9xoly+8LuD99kIzdSHLzJFJXCYFHXeIuc+Ov9e2VwmO7czF2ZhVmjOEwmotSTa8Jts4= From: Bertrand Marquis To: "xen-devel@lists.xenproject.org" CC: "jens.wiklander@linaro.org" , Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Subject: Re: [PATCH v7 3/6] xen/arm: ffa: Introduce VM to VM support Thread-Topic: [PATCH v7 3/6] xen/arm: ffa: Introduce VM to VM support Thread-Index: AQHb9xP9tgnM92Sxpk+5sdmAsJMirrRNeIKA Date: Fri, 1 Aug 2025 07:10:27 +0000 Message-ID: <83336841-32E9-498F-8D72-13F7B07A9DB3@arm.com> References: <50224eb7cca4eaef2646ad8e33f689d912704733.1752754016.git.bertrand.marquis@arm.com> In-Reply-To: <50224eb7cca4eaef2646ad8e33f689d912704733.1752754016.git.bertrand.marquis@arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3826.600.51.1.1) Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2025 07:11:00.5512 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 348d5070-5d8a-419f-ec06-08ddd0ca91ea X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A78E.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9337 Hi, A gentle ping for someone to review this :-) Thanks Bertrand > On 17 Jul 2025, at 14:11, Bertrand Marquis wro= te: >=20 > Create a CONFIG_FFA_VM_TO_VM parameter to activate FFA communication > between VMs. > When activated list VMs in the system with FF-A support in part_info_get. >=20 > When VM to VM is activated, Xen will be tainted as Insecure and a > message is displayed to the user during the boot as there is no > filtering of VMs in FF-A so any VM can communicate or see any other VM > in the system. >=20 > WARNING: There is no filtering for now and all VMs are listed !! >=20 > This patch is reorganizing the ffa_ctx structure to make clear which > lock is protecting what parts. >=20 > This patch is introducing a chain list of the ffa_ctx with a FFA Version > negociated allowing to create the partinfo results for VMs in parallel > by using rwlock which only ensure addition/removal of entries are > protected. >=20 > Signed-off-by: Bertrand Marquis > --- > Changes in v7: > - protect ffa_ctx list with a rw lock to allow several partinfo_get in > parallel but protect adding/removing entries. > Changes in v6: > - remove ACCESS_ONCE for guest_vers access and take the context lock > before modifying it > - move guest_vers in context declaration to fields protected by the > context lock and add a comment to state that lock in only needed when > modifying it > Changes in v5: > - remove invalid comment about 1.1 firmware support > - rename variables from d and dom to curr_d and dest_d (Julien) > - add a TODO in the code for potential holding for long of the CPU > (Julien) > - use an atomic global variable to store the number of VMs instead of > recomputing the value each time (Julien) > - add partinfo information in ffa_ctx (id, cpus and 64bit) and create a > chain list of ctx. Use this chain list to create the partinfo result > without holding a global lock to prevent concurrency issues. > - Move some changes in a preparation patch modifying partinfo for sps to > reduce this patch size and make the review easier > Changes in v4: > - properly handle SPMC version 1.0 header size case in partinfo_get > - switch to local counting variables instead of *pointer +=3D 1 form > - coding style issue with missing spaces in if () > Changes in v3: > - break partinfo_get in several sub functions to make the implementation > easier to understand and lock handling easier > - rework implementation to check size along the way and prevent previous > implementation limits which had to check that the number of VMs or SPs > did not change > - taint Xen as INSECURE when VM to VM is enabled > Changes in v2: > - Switch ifdef to IS_ENABLED > - dom was not switched to d as requested by Jan because there is already > a variable d pointing to the current domain and it must not be > shadowed. > --- > xen/arch/arm/tee/Kconfig | 11 +++ > xen/arch/arm/tee/ffa.c | 47 +++++++++++++ > xen/arch/arm/tee/ffa_partinfo.c | 100 ++++++++++++++++++++++++--- > xen/arch/arm/tee/ffa_private.h | 117 ++++++++++++++++++++++++++------ > 4 files changed, 245 insertions(+), 30 deletions(-) >=20 > diff --git a/xen/arch/arm/tee/Kconfig b/xen/arch/arm/tee/Kconfig > index c5b0f88d7522..88a4c4c99154 100644 > --- a/xen/arch/arm/tee/Kconfig > +++ b/xen/arch/arm/tee/Kconfig > @@ -28,5 +28,16 @@ config FFA >=20 > [1] https://developer.arm.com/documentation/den0077/latest >=20 > +config FFA_VM_TO_VM > + bool "Enable FF-A between VMs (UNSUPPORTED)" if UNSUPPORTED > + default n > + depends on FFA > + help > + This option enables to use FF-A between VMs. > + This is experimental and there is no access control so any > + guest can communicate with any other guest. > + > + If unsure, say N. > + > endmenu >=20 > diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c > index 3bbdd7168a6b..be71eda4869f 100644 > --- a/xen/arch/arm/tee/ffa.c > +++ b/xen/arch/arm/tee/ffa.c > @@ -118,6 +118,13 @@ void *ffa_tx __read_mostly; > DEFINE_SPINLOCK(ffa_rx_buffer_lock); > DEFINE_SPINLOCK(ffa_tx_buffer_lock); >=20 > +struct list_head ffa_ctx_head; > +/* RW Lock to protect addition/removal and reading in ffa_ctx_head */ > +rwlock_t ffa_ctx_list_rwlock; > + > +#ifdef CONFIG_FFA_VM_TO_VM > +atomic_t ffa_vm_count; > +#endif >=20 > /* Used to track domains that could not be torn down immediately. */ > static struct timer ffa_teardown_timer; > @@ -151,6 +158,7 @@ static void handle_version(struct cpu_user_regs *regs= ) > struct domain *d =3D current->domain; > struct ffa_ctx *ctx =3D d->arch.tee; > uint32_t vers =3D get_user_reg(regs, 1); > + uint32_t old_vers; >=20 > /* > * Guest will use the version it requested if it is our major and min= or > @@ -160,10 +168,23 @@ static void handle_version(struct cpu_user_regs *re= gs) > */ > if ( FFA_VERSION_MAJOR(vers) =3D=3D FFA_MY_VERSION_MAJOR ) > { > + spin_lock(&ctx->lock); > + old_vers =3D ctx->guest_vers; > + > if ( FFA_VERSION_MINOR(vers) > FFA_MY_VERSION_MINOR ) > ctx->guest_vers =3D FFA_MY_VERSION; > else > ctx->guest_vers =3D vers; > + spin_unlock(&ctx->lock); > + > + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !old_vers ) > + { > + /* One more VM with FF-A support available */ > + inc_ffa_vm_count(); > + write_lock(&ffa_ctx_list_rwlock); > + list_add_tail(&ctx->ctx_list, &ffa_ctx_head); > + write_unlock(&ffa_ctx_list_rwlock); > + } > } > ffa_set_regs(regs, FFA_MY_VERSION, 0, 0, 0, 0, 0, 0, 0); > } > @@ -345,6 +366,10 @@ static int ffa_domain_init(struct domain *d) > ctx->teardown_d =3D d; > INIT_LIST_HEAD(&ctx->shm_list); >=20 > + ctx->ffa_id =3D ffa_get_vm_id(d); > + ctx->num_vcpus =3D d->max_vcpus; > + ctx->is_64bit =3D is_64bit_domain(d); > + > /* > * ffa_domain_teardown() will be called if ffa_domain_init() returns = an > * error, so no need for cleanup in this function. > @@ -421,6 +446,14 @@ static int ffa_domain_teardown(struct domain *d) > if ( !ctx ) > return 0; >=20 > + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && ctx->guest_vers ) > + { > + dec_ffa_vm_count(); > + write_lock(&ffa_ctx_list_rwlock); > + list_del(&ctx->ctx_list); > + write_unlock(&ffa_ctx_list_rwlock); > + } > + > ffa_rxtx_domain_destroy(d); > ffa_notif_domain_destroy(d); >=20 > @@ -464,6 +497,18 @@ static bool ffa_probe(void) > printk(XENLOG_INFO "ARM FF-A Mediator version %u.%u\n", > FFA_MY_VERSION_MAJOR, FFA_MY_VERSION_MINOR); >=20 > + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > + { > + /* > + * When FFA VM to VM is enabled, the current implementation does= not > + * offer any way to limit which VM can communicate with which VM= using > + * FF-A. > + * Signal this in the xen console and taint the system as insecu= re. > + * TODO: Introduce a solution to limit what a VM can do through = FFA. > + */ > + printk(XENLOG_ERR "ffa: VM to VM is enabled, system is insecure = !!\n"); > + add_taint(TAINT_MACHINE_INSECURE); > + } > /* > * psci_init_smccc() updates this value with what's reported by EL-3 > * or secure world. > @@ -538,6 +583,8 @@ static bool ffa_probe(void) >=20 > ffa_notif_init(); > INIT_LIST_HEAD(&ffa_teardown_head); > + INIT_LIST_HEAD(&ffa_ctx_head); > + rwlock_init(&ffa_ctx_list_rwlock); > init_timer(&ffa_teardown_timer, ffa_teardown_timer_callback, NULL, 0)= ; >=20 > return true; > diff --git a/xen/arch/arm/tee/ffa_partinfo.c b/xen/arch/arm/tee/ffa_parti= nfo.c > index dfa0b23eaf38..fa56b1587e3b 100644 > --- a/xen/arch/arm/tee/ffa_partinfo.c > +++ b/xen/arch/arm/tee/ffa_partinfo.c > @@ -150,6 +150,73 @@ out: > return ret; > } >=20 > +static int32_t ffa_get_vm_partinfo(uint32_t *vm_count, void *dst_buf, > + void *end_buf, uint32_t dst_size) > +{ > + struct ffa_ctx *curr_ctx =3D current->domain->arch.tee; > + struct ffa_ctx *dest_ctx; > + uint32_t count =3D 0; > + int32_t ret =3D FFA_RET_OK; > + > + /* > + * There could potentially be a lot of VMs in the system and we coul= d > + * hold the CPU for long here. > + * Right now there is no solution in FF-A specification to split > + * the work in this case. > + * TODO: Check how we could delay the work or have preemption checks= . > + */ > + read_lock(&ffa_ctx_list_rwlock); > + list_for_each_entry(dest_ctx, &ffa_ctx_head, ctx_list) > + { > + /* > + * Do not include an entry for the caller VM as the spec is not > + * clearly mandating it and it is not supported by Linux. > + */ > + if ( dest_ctx !=3D curr_ctx ) > + { > + /* > + * We do not have UUID info for VMs so use > + * the 1.0 structure so that we set UUIDs to > + * zero using memset > + */ > + struct ffa_partition_info_1_0 info; > + > + if ( dst_buf > (end_buf - dst_size) ) > + { > + ret =3D FFA_RET_NO_MEMORY; > + goto out; > + } > + > + /* > + * Context might has been removed since we go it or being re= moved > + * right now so we might return information for a VM not exi= sting > + * anymore. This is acceptable as we return a view of the sy= stem > + * which could change at any time. > + */ > + info.id =3D dest_ctx->ffa_id; > + info.execution_context =3D dest_ctx->num_vcpus; > + info.partition_properties =3D FFA_PART_VM_PROP; > + if ( dest_ctx->is_64bit ) > + info.partition_properties |=3D FFA_PART_PROP_AARCH64_STA= TE; > + > + memcpy(dst_buf, &info, MIN(sizeof(info), dst_size)); > + > + if ( dst_size > sizeof(info) ) > + memset(dst_buf + sizeof(info), 0, > + dst_size - sizeof(info)); > + > + dst_buf +=3D dst_size; > + count++; > + } > + } > + *vm_count =3D count; > + > +out: > + read_unlock(&ffa_ctx_list_rwlock); > + > + return ret; > +} > + > void ffa_handle_partition_info_get(struct cpu_user_regs *regs) > { > int32_t ret =3D FFA_RET_OK; > @@ -164,7 +231,7 @@ void ffa_handle_partition_info_get(struct cpu_user_re= gs *regs) > }; > uint32_t dst_size =3D 0; > void *dst_buf, *end_buf; > - uint32_t ffa_sp_count =3D 0; > + uint32_t ffa_vm_count =3D 0, ffa_sp_count =3D 0; >=20 > /* > * If the guest is v1.0, he does not get back the entry size so we mu= st > @@ -191,15 +258,18 @@ void ffa_handle_partition_info_get(struct cpu_user_= regs *regs) > } >=20 > if ( ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) ) > + { > ret =3D ffa_get_sp_count(uuid, &ffa_sp_count); > + if ( ret ) > + goto out; > + } >=20 > - goto out; > - } > + /* > + * Do not count the caller VM as the spec is not clearly mandati= ng it > + * and it is not supported by Linux. > + */ > + ffa_vm_count =3D get_ffa_vm_count() - 1; >=20 > - if ( !ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) ) > - { > - /* Just give an empty partition list to the caller */ > - ret =3D FFA_RET_OK; > goto out; > } >=20 > @@ -224,9 +294,19 @@ void ffa_handle_partition_info_get(struct cpu_user_r= egs *regs) > goto out_rx_release; > } >=20 > - ret =3D ffa_get_sp_partinfo(uuid, &ffa_sp_count, dst_buf, end_buf, > - dst_size); > + if ( ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) ) > + { > + ret =3D ffa_get_sp_partinfo(uuid, &ffa_sp_count, dst_buf, end_bu= f, > + dst_size); > + > + if ( ret ) > + goto out_rx_release; > + > + dst_buf +=3D ffa_sp_count * dst_size; > + } >=20 > + if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > + ret =3D ffa_get_vm_partinfo(&ffa_vm_count, dst_buf, end_buf, dst= _size); >=20 > out_rx_release: > if ( ret ) > @@ -235,7 +315,7 @@ out: > if ( ret ) > ffa_set_regs_error(regs, ret); > else > - ffa_set_regs_success(regs, ffa_sp_count, dst_size); > + ffa_set_regs_success(regs, ffa_sp_count + ffa_vm_count, dst_size= ); > } >=20 > static int32_t ffa_direct_req_send_vm(uint16_t sp_id, uint16_t vm_id, > diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_privat= e.h > index 0a9c1082db28..1a1dcabcdc28 100644 > --- a/xen/arch/arm/tee/ffa_private.h > +++ b/xen/arch/arm/tee/ffa_private.h > @@ -195,6 +195,18 @@ > */ > #define FFA_PARTITION_INFO_GET_COUNT_FLAG BIT(0, U) >=20 > +/* > + * Partition properties we give for a normal world VM: > + * - can send direct message but not receive them > + * - can handle indirect messages > + * - can receive notifications > + * 32/64 bit flag is set depending on the VM > + */ > +#define FFA_PART_VM_PROP (FFA_PART_PROP_DIRECT_REQ_SEND | \ > + FFA_PART_PROP_INDIRECT_MSGS | \ > + FFA_PART_PROP_RECV_NOTIF | \ > + FFA_PART_PROP_IS_PE_ID) > + > /* Flags used in calls to FFA_NOTIFICATION_GET interface */ > #define FFA_NOTIF_FLAG_BITMAP_SP BIT(0, U) > #define FFA_NOTIF_FLAG_BITMAP_VM BIT(1, U) > @@ -297,36 +309,72 @@ struct ffa_ctx_notif { > }; >=20 > struct ffa_ctx { > - void *rx; > - const void *tx; > - struct page_info *rx_pg; > - struct page_info *tx_pg; > + /* > + * Chain list of all FF-A contexts. > + * As we might have several read from the list of context through pa= rallel > + * partinfo_get but fewer additions/removal as those happen only dur= ing a > + * version negociation or guest shutdown, access to this list is pro= tected > + * through a rwlock (addition/removal with write lock, reading throu= gh a > + * read lock). > + */ > + struct list_head ctx_list; /* chain list of all FF-A contexts */ > + > + /* > + * Data access unlocked (mainly for part_info_get in VM to VM). > + * Those should be set before the ctx is added in the list. > + */ > + /* FF-A Endpoint ID */ > + uint16_t ffa_id; > + uint16_t num_vcpus; > + bool is_64bit; > + > + /* > + * Global data accessed atomically or using ACCES_ONCE. > + */ > + struct ffa_ctx_notif notif; > + > + /* > + * Global data accessed with lock locked. > + */ > + spinlock_t lock; > + /* > + * FF-A version negociated by the guest, only modifications to > + * this field are done with the lock held as this is expected to > + * be done once at init by a guest. > + */ > + uint32_t guest_vers; > /* Number of 4kB pages in each of rx/rx_pg and tx/tx_pg */ > unsigned int page_count; > - /* FF-A version used by the guest */ > - uint32_t guest_vers; > - bool rx_is_free; > - /* Used shared memory objects, struct ffa_shm_mem */ > - struct list_head shm_list; > /* Number of allocated shared memory object */ > unsigned int shm_count; > - struct ffa_ctx_notif notif; > + /* Used shared memory objects, struct ffa_shm_mem */ > + struct list_head shm_list; > + > /* > - * tx_lock is used to serialize access to tx > - * rx_lock is used to serialize access to rx_is_free > - * lock is used for the rest in this struct > + * Rx buffer, accessed with rx_lock locked. > + * rx_is_free is used to serialize access. > */ > - spinlock_t tx_lock; > spinlock_t rx_lock; > - spinlock_t lock; > - /* Used if domain can't be torn down immediately */ > + bool rx_is_free; > + void *rx; > + struct page_info *rx_pg; > + > + /* > + * Tx buffer, access with tx_lock locked. > + */ > + spinlock_t tx_lock; > + const void *tx; > + struct page_info *tx_pg; > + > + > + /* > + * Domain teardown handling if data shared or used by other domains > + * do not allow to teardown the domain immediately. > + */ > struct domain *teardown_d; > struct list_head teardown_list; > s_time_t teardown_expire; > - /* > - * Used for ffa_domain_teardown() to keep track of which SPs should = be > - * notified that this guest is being destroyed. > - */ > + /* Keep track of SPs that should be notified of VM destruction */ > unsigned long *vm_destroy_bitmap; > }; >=20 > @@ -336,6 +384,12 @@ extern spinlock_t ffa_rx_buffer_lock; > extern spinlock_t ffa_tx_buffer_lock; > extern DECLARE_BITMAP(ffa_fw_abi_supported, FFA_ABI_BITMAP_SIZE); >=20 > +extern struct list_head ffa_ctx_head; > +extern rwlock_t ffa_ctx_list_rwlock; > +#ifdef CONFIG_FFA_VM_TO_VM > +extern atomic_t ffa_vm_count; > +#endif > + > bool ffa_shm_domain_destroy(struct domain *d); > void ffa_handle_mem_share(struct cpu_user_regs *regs); > int ffa_handle_mem_reclaim(uint64_t handle, uint32_t flags); > @@ -368,6 +422,29 @@ int ffa_handle_notification_set(struct cpu_user_regs= *regs); > void ffa_handle_msg_send_direct_req(struct cpu_user_regs *regs, uint32_t = fid); > int32_t ffa_handle_msg_send2(struct cpu_user_regs *regs); >=20 > +#ifdef CONFIG_FFA_VM_TO_VM > +static inline uint16_t get_ffa_vm_count(void) > +{ > + return atomic_read(&ffa_vm_count); > +} > + > +static inline void inc_ffa_vm_count(void) > +{ > + atomic_inc(&ffa_vm_count); > +} > + > +static inline void dec_ffa_vm_count(void) > +{ > + ASSERT(atomic_read(&ffa_vm_count) > 0); > + atomic_dec(&ffa_vm_count); > +} > +#else > +/* Only count the caller VM */ > +#define get_ffa_vm_count() ((uint16_t)1UL) > +#define inc_ffa_vm_count() do {} while(0) > +#define dec_ffa_vm_count() do {} while(0) > +#endif > + > static inline uint16_t ffa_get_vm_id(const struct domain *d) > { > /* +1 since 0 is reserved for the hypervisor in FF-A */ > --=20 > 2.47.1 >=20 >=20 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 07:11:44 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 07:11:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066875.1431917 (Exim 4.92) (envelope-from ) id 1uhjvc-0004kL-Bx; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2025 07:11:26.2712 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7b7b228-0210-48e9-cea5-08ddd0caa13e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000047.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6377 Hi, A gentle ping for someone to review this :-) Thanks Bertrand > On 17 Jul 2025, at 14:11, Bertrand Marquis wro= te: >=20 > When VM to VM support is activated and there is no suitable FF-A support > in the firmware, enable FF-A support for VMs to allow using it for VM to > VM communications. > If there is OP-TEE running in the secure world and using the non FF-A > communication system, having CONFIG_FFA_VM_TO_VM could be non functional > (if optee is probed first) or OP-TEE could be non functional (if FF-A is > probed first) so it is not recommended to activate the configuration > option for such systems. >=20 > To make buffer full notification work between VMs when there is no > firmware, rework the notification handling and modify the global flag to > only be used as check for firmware notification support instead. >=20 > Also split probe function into one for firmware and one for vm to vm to > make the implementation clearer. >=20 > Signed-off-by: Bertrand Marquis > Reviewed-by: Jens Wiklander >=20 > --- > Changes in v7: > - add Jens R-b > Changes in v6: > - split probe into fw and vm_to_vm probe > Changes in v5: > - init ctx list when there is no firmware > - rework init a bit to prevent duplicates > - Remove Jens R-b due to changes done > Changes in v4: > - Fix Optee to OP-TEE in commit message > - Add Jens R-b > Changes in v3: > - fix typos in commit message > - add spaces around << > - move notification id fix back into buffer full patch > - fix | position in if > Changes in v2: > - replace ifdef with IS_ENABLED when possible > --- > xen/arch/arm/tee/ffa.c | 93 ++++++++++++++++++------------- > xen/arch/arm/tee/ffa_notif.c | 104 ++++++++++++++++------------------- > 2 files changed, 104 insertions(+), 93 deletions(-) >=20 > diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c > index be71eda4869f..df38b4e15b36 100644 > --- a/xen/arch/arm/tee/ffa.c > +++ b/xen/arch/arm/tee/ffa.c > @@ -345,8 +345,9 @@ static int ffa_domain_init(struct domain *d) > struct ffa_ctx *ctx; > int ret; >=20 > - if ( !ffa_fw_version ) > + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !ffa_fw_version ) > return -ENODEV; > + > /* > * We are using the domain_id + 1 as the FF-A ID for VMs as FF-A ID 0= is > * reserved for the hypervisor and we only support secure endpoints u= sing > @@ -477,38 +478,12 @@ static void ffa_init_secondary(void) > ffa_notif_init_interrupt(); > } >=20 > -static bool ffa_probe(void) > +static bool ffa_probe_fw(void) > { > uint32_t vers; > unsigned int major_vers; > unsigned int minor_vers; >=20 > - /* > - * FF-A often works in units of 4K pages and currently it's assumed > - * that we can map memory using that granularity. See also the comme= nt > - * above the FFA_PAGE_SIZE define. > - * > - * It is possible to support a PAGE_SIZE larger than 4K in Xen, but > - * until that is fully handled in this code make sure that we only u= se > - * 4K page sizes. > - */ > - BUILD_BUG_ON(PAGE_SIZE !=3D FFA_PAGE_SIZE); > - > - printk(XENLOG_INFO "ARM FF-A Mediator version %u.%u\n", > - FFA_MY_VERSION_MAJOR, FFA_MY_VERSION_MINOR); > - > - if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > - { > - /* > - * When FFA VM to VM is enabled, the current implementation does= not > - * offer any way to limit which VM can communicate with which VM= using > - * FF-A. > - * Signal this in the xen console and taint the system as insecu= re. > - * TODO: Introduce a solution to limit what a VM can do through = FFA. > - */ > - printk(XENLOG_ERR "ffa: VM to VM is enabled, system is insecure = !!\n"); > - add_taint(TAINT_MACHINE_INSECURE); > - } > /* > * psci_init_smccc() updates this value with what's reported by EL-3 > * or secure world. > @@ -527,11 +502,6 @@ static bool ffa_probe(void) > goto err_no_fw; > } >=20 > - /* Some sanity check in case we update the version we support */ > - BUILD_BUG_ON(FFA_MIN_SPMC_VERSION > FFA_MY_VERSION); > - BUILD_BUG_ON(FFA_VERSION_MAJOR(FFA_MIN_SPMC_VERSION) !=3D > - FFA_MY_VERSION_MAJOR); > - > major_vers =3D FFA_VERSION_MAJOR(vers); > minor_vers =3D FFA_VERSION_MINOR(vers); >=20 > @@ -582,10 +552,6 @@ static bool ffa_probe(void) > goto err_rxtx_destroy; >=20 > ffa_notif_init(); > - INIT_LIST_HEAD(&ffa_teardown_head); > - INIT_LIST_HEAD(&ffa_ctx_head); > - rwlock_init(&ffa_ctx_list_rwlock); > - init_timer(&ffa_teardown_timer, ffa_teardown_timer_callback, NULL, 0= ); >=20 > return true; >=20 > @@ -599,6 +565,59 @@ err_no_fw: > return false; > } >=20 > +static bool ffa_probe_vm_to_vm(void) > +{ > + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > + return false; > + > + /* > + * When FFA VM to VM is enabled, the current implementation does not > + * offer any way to limit which VM can communicate with which VM usi= ng > + * FF-A. > + * Signal this in the xen console and taint the system as insecure. > + * TODO: Introduce a solution to limit what a VM can do through FFA. > + */ > + printk(XENLOG_ERR "ffa: VM to VM is enabled, system is insecure !!\n= "); > + add_taint(TAINT_MACHINE_INSECURE); > + > + return true; > +} > + > +static bool ffa_probe(void) > +{ > + /* > + * FF-A often works in units of 4K pages and currently it's assumed > + * that we can map memory using that granularity. See also the comme= nt > + * above the FFA_PAGE_SIZE define. > + * > + * It is possible to support a PAGE_SIZE larger than 4K in Xen, but > + * until that is fully handled in this code make sure that we only u= se > + * 4K page sizes. > + */ > + BUILD_BUG_ON(PAGE_SIZE !=3D FFA_PAGE_SIZE); > + > + /* Some sanity check in case we update the version we support */ > + BUILD_BUG_ON(FFA_MIN_SPMC_VERSION > FFA_MY_VERSION); > + BUILD_BUG_ON(FFA_VERSION_MAJOR(FFA_MIN_SPMC_VERSION) !=3D > + FFA_MY_VERSION_MAJOR); > + > + printk(XENLOG_INFO "ARM FF-A Mediator version %u.%u\n", > + FFA_MY_VERSION_MAJOR, FFA_MY_VERSION_MINOR); > + > + if ( !ffa_probe_fw() && !ffa_probe_vm_to_vm() ) > + return false; > + > + if ( !ffa_fw_version ) > + printk(XENLOG_INFO "ARM FF-A only available between VMs\n"); > + > + INIT_LIST_HEAD(&ffa_teardown_head); > + INIT_LIST_HEAD(&ffa_ctx_head); > + rwlock_init(&ffa_ctx_list_rwlock); > + init_timer(&ffa_teardown_timer, ffa_teardown_timer_callback, NULL, 0= ); > + > + return true; > +} > + > static const struct tee_mediator_ops ffa_ops =3D > { > .probe =3D ffa_probe, > diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c > index f6df2f15bb00..86bef6b3b2ab 100644 > --- a/xen/arch/arm/tee/ffa_notif.c > +++ b/xen/arch/arm/tee/ffa_notif.c > @@ -16,7 +16,7 @@ >=20 > #include "ffa_private.h" >=20 > -static bool __ro_after_init notif_enabled; > +static bool __ro_after_init fw_notif_enabled; > static unsigned int __ro_after_init notif_sri_irq; >=20 > int ffa_handle_notification_bind(struct cpu_user_regs *regs) > @@ -27,21 +27,17 @@ int ffa_handle_notification_bind(struct cpu_user_regs= *regs) > uint32_t bitmap_lo =3D get_user_reg(regs, 3); > uint32_t bitmap_hi =3D get_user_reg(regs, 4); >=20 > - if ( !notif_enabled ) > - return FFA_RET_NOT_SUPPORTED; > - > if ( (src_dst & 0xFFFFU) !=3D ffa_get_vm_id(d) ) > return FFA_RET_INVALID_PARAMETERS; >=20 > if ( flags ) /* Only global notifications are supported */ > return FFA_RET_DENIED; >=20 > - /* > - * We only support notifications from SP so no need to check the sen= der > - * endpoint ID, the SPMC will take care of that for us. > - */ > - return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, bitmap= _lo, > - bitmap_hi); > + if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled ) > + return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, > + bitmap_lo, bitmap_hi); > + > + return FFA_RET_NOT_SUPPORTED; > } >=20 > int ffa_handle_notification_unbind(struct cpu_user_regs *regs) > @@ -51,18 +47,14 @@ int ffa_handle_notification_unbind(struct cpu_user_re= gs *regs) > uint32_t bitmap_lo =3D get_user_reg(regs, 3); > uint32_t bitmap_hi =3D get_user_reg(regs, 4); >=20 > - if ( !notif_enabled ) > - return FFA_RET_NOT_SUPPORTED; > - > if ( (src_dst & 0xFFFFU) !=3D ffa_get_vm_id(d) ) > return FFA_RET_INVALID_PARAMETERS; >=20 > - /* > - * We only support notifications from SP so no need to check the > - * destination endpoint ID, the SPMC will take care of that for us. > - */ > - return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitmap_= lo, > - bitmap_hi); > + if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled ) > + return ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bit= map_lo, > + bitmap_hi); > + > + return FFA_RET_NOT_SUPPORTED; > } >=20 > void ffa_handle_notification_info_get(struct cpu_user_regs *regs) > @@ -71,7 +63,7 @@ void ffa_handle_notification_info_get(struct cpu_user_r= egs *regs) > struct ffa_ctx *ctx =3D d->arch.tee; > bool notif_pending; >=20 > - if ( !notif_enabled ) > + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled ) > { > ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > return; > @@ -108,7 +100,7 @@ void ffa_handle_notification_get(struct cpu_user_regs= *regs) > uint32_t w6 =3D 0; > uint32_t w7 =3D 0; >=20 > - if ( !notif_enabled ) > + if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled ) > { > ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED); > return; > @@ -120,7 +112,8 @@ void ffa_handle_notification_get(struct cpu_user_regs= *regs) > return; > } >=20 > - if ( flags & ( FFA_NOTIF_FLAG_BITMAP_SP | FFA_NOTIF_FLAG_BITMAP_SPM = ) ) > + if ( fw_notif_enabled && (flags & ( FFA_NOTIF_FLAG_BITMAP_SP | > + FFA_NOTIF_FLAG_BITMAP_SPM )) ) > { > struct arm_smccc_1_2_regs arg =3D { > .a0 =3D FFA_NOTIFICATION_GET, > @@ -177,15 +170,14 @@ int ffa_handle_notification_set(struct cpu_user_reg= s *regs) > uint32_t bitmap_lo =3D get_user_reg(regs, 3); > uint32_t bitmap_hi =3D get_user_reg(regs, 4); >=20 > - if ( !notif_enabled ) > - return FFA_RET_NOT_SUPPORTED; > - > if ( (src_dst >> 16) !=3D ffa_get_vm_id(d) ) > return FFA_RET_INVALID_PARAMETERS; >=20 > - /* Let the SPMC check the destination of the notification */ > - return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bitmap_= lo, > - bitmap_hi); > + if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled ) > + return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bit= map_lo, > + bitmap_hi); > + > + return FFA_RET_NOT_SUPPORTED; > } >=20 > #ifdef CONFIG_FFA_VM_TO_VM > @@ -371,7 +363,7 @@ void ffa_notif_init_interrupt(void) > { > int ret; >=20 > - if ( notif_enabled && notif_sri_irq < NR_GIC_SGI ) > + if ( fw_notif_enabled && notif_sri_irq < NR_GIC_SGI ) > { > /* > * An error here is unlikely since the primary CPU has already > @@ -402,41 +394,41 @@ void ffa_notif_init(void) > int ret; >=20 > /* Only enable fw notification if all ABIs we need are supported */ > - if ( !(ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_CREATE) && > - ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_DESTROY) && > - ffa_fw_supports_fid(FFA_NOTIFICATION_GET) && > - ffa_fw_supports_fid(FFA_NOTIFICATION_INFO_GET_64)) ) > - return; > - > - arm_smccc_1_2_smc(&arg, &resp); > - if ( resp.a0 !=3D FFA_SUCCESS_32 ) > - return; > - > - irq =3D resp.a2; > - notif_sri_irq =3D irq; > - if ( irq >=3D NR_GIC_SGI ) > - irq_set_type(irq, IRQ_TYPE_EDGE_RISING); > - ret =3D request_irq(irq, 0, notif_irq_handler, "FF-A notif", NULL); > - if ( ret ) > + if ( ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_CREATE) && > + ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_DESTROY) && > + ffa_fw_supports_fid(FFA_NOTIFICATION_GET) && > + ffa_fw_supports_fid(FFA_NOTIFICATION_INFO_GET_64) ) > { > - printk(XENLOG_ERR "ffa: request_irq irq %u failed: error %d\n", > - irq, ret); > - return; > - } > + arm_smccc_1_2_smc(&arg, &resp); > + if ( resp.a0 !=3D FFA_SUCCESS_32 ) > + return; >=20 > - notif_enabled =3D true; > + irq =3D resp.a2; > + notif_sri_irq =3D irq; > + if ( irq >=3D NR_GIC_SGI ) > + irq_set_type(irq, IRQ_TYPE_EDGE_RISING); > + ret =3D request_irq(irq, 0, notif_irq_handler, "FF-A notif", NUL= L); > + if ( ret ) > + { > + printk(XENLOG_ERR "ffa: request_irq irq %u failed: error %d\= n", > + irq, ret); > + return; > + } > + fw_notif_enabled =3D true; > + } > } >=20 > int ffa_notif_domain_init(struct domain *d) > { > int32_t res; >=20 > - if ( !notif_enabled ) > - return 0; > + if ( fw_notif_enabled ) > + { >=20 > - res =3D ffa_notification_bitmap_create(ffa_get_vm_id(d), d->max_vcpu= s); > - if ( res ) > - return -ENOMEM; > + res =3D ffa_notification_bitmap_create(ffa_get_vm_id(d), d->max_= vcpus); > + if ( res ) > + return -ENOMEM; > + } >=20 > return 0; > } > @@ -447,6 +439,6 @@ void ffa_notif_domain_destroy(struct domain *d) > * Call bitmap_destroy even if bitmap create failed as the SPMC will > * return a DENIED error that we will ignore. > */ > - if ( notif_enabled ) > + if ( fw_notif_enabled ) > ffa_notification_bitmap_destroy(ffa_get_vm_id(d)); > } > --=20 > 2.47.1 >=20 >=20 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 07:11:47 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 07:11:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066877.1431925 (Exim 4.92) (envelope-from ) id 1uhjvf-00050N-H5; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2025 07:11:39.6424 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 78d0bf0e-c725-4151-9f38-08ddd0caa938 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509FA.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9582 Hi, A gentle ping for someone to review this :-) Thanks Bertrand > On 17 Jul 2025, at 14:11, Bertrand Marquis wro= te: >=20 > Add support for indirect messages between VMs. > This is only enabled if CONFIG_FFA_VM_TO_VM is selected. >=20 > Signed-off-by: Bertrand Marquis > Reviewed-by: Jens Wiklander > --- > Changes in v6: > - fix code alignment (Jens) > - add Jens R-b > Changes in v5: > - Prevent potential overflow in send2 handling (Julien) > - Only use page_count with rx lock acquired > - Fix an issue where send2 between VMs was not doing the copy from the > tx buffer but from a wrong location in the stack. This bug was > introduced in v4 when switching to a local copy for the header. > Changes in v4: > - Use a local copy of the message header to prevent a TOC/TOU possible > issue when using the payload size > Changes in v3: > - Move vm to vm indirect message handling in a sub function to simplify > lock handling and make implementation easier to read > Changes in v2: > - Switch ifdef to IS_ENABLED > --- > xen/arch/arm/tee/ffa_msg.c | 117 ++++++++++++++++++++++++++++++++----- > 1 file changed, 102 insertions(+), 15 deletions(-) >=20 > diff --git a/xen/arch/arm/tee/ffa_msg.c b/xen/arch/arm/tee/ffa_msg.c > index ee594e737fc7..c20c5bec0f76 100644 > --- a/xen/arch/arm/tee/ffa_msg.c > +++ b/xen/arch/arm/tee/ffa_msg.c > @@ -88,43 +88,130 @@ out: > resp.a7 & mask); > } >=20 > +static int32_t ffa_msg_send2_vm(uint16_t dst_id, const void *src_buf, > + struct ffa_part_msg_rxtx *src_msg) > +{ > + struct domain *dst_d; > + struct ffa_ctx *dst_ctx; > + struct ffa_part_msg_rxtx *dst_msg; > + int err; > + int32_t ret; > + > + if ( dst_id =3D=3D 0 ) > + /* FF-A ID 0 is the hypervisor, this is not valid */ > + return FFA_RET_INVALID_PARAMETERS; > + > + /* This is also checking that dest is not src */ > + err =3D rcu_lock_live_remote_domain_by_id(dst_id - 1, &dst_d); > + if ( err ) > + return FFA_RET_INVALID_PARAMETERS; > + > + if ( dst_d->arch.tee =3D=3D NULL ) > + { > + ret =3D FFA_RET_INVALID_PARAMETERS; > + goto out_unlock; > + } > + > + dst_ctx =3D dst_d->arch.tee; > + if ( !dst_ctx->guest_vers ) > + { > + ret =3D FFA_RET_INVALID_PARAMETERS; > + goto out_unlock; > + } > + > + /* This also checks that destination has set a Rx buffer */ > + ret =3D ffa_rx_acquire(dst_d); > + if ( ret ) > + goto out_unlock; > + > + /* we need to have enough space in the destination buffer */ > + if ( (dst_ctx->page_count * FFA_PAGE_SIZE - > + sizeof(struct ffa_part_msg_rxtx)) < src_msg->msg_size ) > + { > + ret =3D FFA_RET_NO_MEMORY; > + ffa_rx_release(dst_d); > + goto out_unlock; > + } > + > + dst_msg =3D dst_ctx->rx; > + > + /* prepare destination header */ > + dst_msg->flags =3D 0; > + dst_msg->reserved =3D 0; > + dst_msg->msg_offset =3D sizeof(struct ffa_part_msg_rxtx); > + dst_msg->send_recv_id =3D src_msg->send_recv_id; > + dst_msg->msg_size =3D src_msg->msg_size; > + > + memcpy(dst_ctx->rx + sizeof(struct ffa_part_msg_rxtx), > + src_buf + src_msg->msg_offset, src_msg->msg_size); > + > + /* receiver rx buffer will be released by the receiver*/ > + > +out_unlock: > + rcu_unlock_domain(dst_d); > + if ( !ret ) > + ffa_raise_rx_buffer_full(dst_d); > + > + return ret; > +} > + > int32_t ffa_handle_msg_send2(struct cpu_user_regs *regs) > { > struct domain *src_d =3D current->domain; > struct ffa_ctx *src_ctx =3D src_d->arch.tee; > - const struct ffa_part_msg_rxtx *src_msg; > + struct ffa_part_msg_rxtx src_msg; > uint16_t dst_id, src_id; > int32_t ret; >=20 > - if ( !ffa_fw_supports_fid(FFA_MSG_SEND2) ) > - return FFA_RET_NOT_SUPPORTED; > + BUILD_BUG_ON(sizeof(struct ffa_part_msg_rxtx) >=3D FFA_PAGE_SIZE); >=20 > if ( !spin_trylock(&src_ctx->tx_lock) ) > return FFA_RET_BUSY; >=20 > - src_msg =3D src_ctx->tx; > - src_id =3D src_msg->send_recv_id >> 16; > - dst_id =3D src_msg->send_recv_id & GENMASK(15,0); > + /* create a copy of the message header */ > + memcpy(&src_msg, src_ctx->tx, sizeof(src_msg)); >=20 > - if ( src_id !=3D ffa_get_vm_id(src_d) || !FFA_ID_IS_SECURE(dst_id) ) > + src_id =3D src_msg.send_recv_id >> 16; > + dst_id =3D src_msg.send_recv_id & GENMASK(15,0); > + > + if ( src_id !=3D ffa_get_vm_id(src_d) ) > { > ret =3D FFA_RET_INVALID_PARAMETERS; > - goto out_unlock_tx; > + goto out; > } >=20 > /* check source message fits in buffer */ > - if ( src_ctx->page_count * FFA_PAGE_SIZE < > - src_msg->msg_offset + src_msg->msg_size || > - src_msg->msg_offset < sizeof(struct ffa_part_msg_rxtx) ) > + if ( src_msg.msg_offset < sizeof(struct ffa_part_msg_rxtx) || > + src_msg.msg_size =3D=3D 0 || > + src_msg.msg_offset > src_ctx->page_count * FFA_PAGE_SIZE || > + src_msg.msg_size > (src_ctx->page_count * FFA_PAGE_SIZE - > + src_msg.msg_offset) ) > { > ret =3D FFA_RET_INVALID_PARAMETERS; > - goto out_unlock_tx; > + goto out; > } >=20 > - ret =3D ffa_simple_call(FFA_MSG_SEND2, > - ((uint32_t)ffa_get_vm_id(src_d)) << 16, 0, 0, = 0); > + if ( FFA_ID_IS_SECURE(dst_id) ) > + { > + /* Message for a secure partition */ > + if ( !ffa_fw_supports_fid(FFA_MSG_SEND2) ) > + { > + ret =3D FFA_RET_NOT_SUPPORTED; > + goto out; > + } > + > + ret =3D ffa_simple_call(FFA_MSG_SEND2, > + ((uint32_t)ffa_get_vm_id(src_d)) << 16, 0,= 0, 0); > + } > + else if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) ) > + { > + /* Message for a VM */ > + ret =3D ffa_msg_send2_vm(dst_id, src_ctx->tx, &src_msg); > + } > + else > + ret =3D FFA_RET_INVALID_PARAMETERS; >=20 > -out_unlock_tx: > +out: > spin_unlock(&src_ctx->tx_lock); > return ret; > } > --=20 > 2.47.1 >=20 >=20 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 07:30:52 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 07:30:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066915.1431935 (Exim 4.92) (envelope-from ) id 1uhkE3-0008N4-5z; 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Fri, 01 Aug 2025 00:30:43 -0700 (PDT) Message-ID: <5fcd1c68-6c18-4a1d-8a1d-f056bdb6cde9@suse.com> Date: Fri, 1 Aug 2025 09:30:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= From: Jan Beulich Subject: [PATCH] console: make printk_ratelimit_{burst,ms} const Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Them not being altered by any means, their __read_mostly attribute is actually counter-productive: It causes the compiler to instantiate the variables, when already with just the attributes dropped the compiler can constant-propagate the values into the sole use site. Make the situation yet more explicit by adding const. Also switch the variables away from being plain int, and have the parameters of __printk_ratelimit() follow suit. While there also similarly adjust the type of "missed" and "lost", and - while touching the adjacent line - increase lost_str[] to accommodate any unsigned 32-bit number. Fixes: a8b1845a7845 ("Miscellaneous data placement adjustments") Signed-off-by: Jan Beulich --- In principle {__,}printk_ratelimit() may also want to have their return type changed to bool, but I think doing so would go too far here: This would have knock-on effects elsewhere, and it would want considering to actually flip polarity. Despite the Fixes: tag I wouldn't consider this for backport. --- a/xen/drivers/char/console.c +++ b/xen/drivers/char/console.c @@ -1268,12 +1268,12 @@ void console_end_sync(void) * This enforces a rate limit: not more than one kernel message * every printk_ratelimit_ms (millisecs). */ -int __printk_ratelimit(int ratelimit_ms, int ratelimit_burst) +int __printk_ratelimit(unsigned int ratelimit_ms, unsigned int ratelimit_burst) { static DEFINE_SPINLOCK(ratelimit_lock); static unsigned long toks = 10 * 5 * 1000; static unsigned long last_msg; - static int missed; + static unsigned int missed; unsigned long flags; unsigned long long now = NOW(); /* ns */ unsigned long ms; @@ -1288,14 +1288,16 @@ int __printk_ratelimit(int ratelimit_ms, toks = ratelimit_burst * ratelimit_ms; if ( toks >= ratelimit_ms ) { - int lost = missed; + unsigned int lost = missed; + missed = 0; toks -= ratelimit_ms; spin_unlock(&ratelimit_lock); if ( lost ) { - char lost_str[8]; - snprintf(lost_str, sizeof(lost_str), "%d", lost); + char lost_str[10]; + + snprintf(lost_str, sizeof(lost_str), "%u", lost); /* console_lock may already be acquired by printk(). */ rspin_lock(&console_lock); printk_start_of_line(CONSOLE_PREFIX); @@ -1312,11 +1314,11 @@ int __printk_ratelimit(int ratelimit_ms, return 0; } -/* minimum time in ms between messages */ -static int __read_mostly printk_ratelimit_ms = 5 * 1000; +/* Minimum time in ms between messages */ +static const unsigned int printk_ratelimit_ms = 5 * 1000; -/* number of messages we send before ratelimiting */ -static int __read_mostly printk_ratelimit_burst = 10; +/* Number of messages we send before ratelimiting */ +static const unsigned int printk_ratelimit_burst = 10; int printk_ratelimit(void) { --- a/xen/include/xen/lib.h +++ b/xen/include/xen/lib.h @@ -80,7 +80,8 @@ extern void guest_printk(const struct do __attribute__ ((format (printf, 2, 3))); extern void noreturn panic(const char *fmt, ...) __attribute__ ((format (printf, 1, 2))); -extern int __printk_ratelimit(int ratelimit_ms, int ratelimit_burst); +extern int __printk_ratelimit(unsigned int ratelimit_ms, + unsigned int ratelimit_burst); extern int printk_ratelimit(void); #define gprintk(lvl, fmt, args...) \ From xen-devel-bounces@lists.xenproject.org Fri Aug 01 07:32:17 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 07:32:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066922.1431945 (Exim 4.92) (envelope-from ) id 1uhkFU-0000Vw-Fb; Fri, 01 Aug 2025 07:32:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1066922.1431945; Fri, 01 Aug 2025 07:32:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhkFU-0000Vp-Cv; Fri, 01 Aug 2025 07:32:16 +0000 Received: by outflank-mailman (input) for mailman id 1066922; Fri, 01 Aug 2025 07:32:15 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhkFT-0000Vh-2a for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 07:32:15 +0000 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [2a00:1450:4864:20::42f]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id a44b222f-6ea9-11f0-b895-0df219b8e170; Fri, 01 Aug 2025 09:32:13 +0200 (CEST) Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3b78bca0890so1230142f8f.3 for ; Fri, 01 Aug 2025 00:32:13 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Fri, 01 Aug 2025 00:32:12 -0700 (PDT) Message-ID: Date: Fri, 1 Aug 2025 09:32:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] xen/console: remove __printk_ratelimit() To: dmkhn@proton.me Cc: Julien Grall , andrew.cooper3@citrix.com, anthony.perard@vates.tech, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250725212235.753363-1-dmukhin@ford.com> <290ae958-4fba-42d8-a64b-d44845b85491@xen.org> <4292abbe-28b1-4545-87af-b37dd4ace53e@suse.com> <528f4bd1-4a2f-4fa1-94cc-363a5f5fdbea@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 23:28, dmkhn@proton.me wrote: > On Thu, Jul 31, 2025 at 08:23:16AM +0200, Jan Beulich wrote: >> On 30.07.2025 20:06, dmkhn@proton.me wrote: >>> On Wed, Jul 30, 2025 at 07:35:04AM +0200, Jan Beulich wrote: >>>> On 30.07.2025 00:18, dmkhn@proton.me wrote: >>>>> On Mon, Jul 28, 2025 at 11:32:43AM +0200, Jan Beulich wrote: >>>>>> On 26.07.2025 11:20, Julien Grall wrote: >>>>>>> On 25/07/2025 22:24, dmkhn@proton.me wrote: >>>>>>>> From: Denis Mukhin >>>>>>>> >>>>>>>> __printk_ratelimit() is never used outside of the console driver. >>>>>>>> Remove it from the lib.h and merge with the public printk_ratelimit(). >>>>>>> >>>>>>> Is this solving any sort of violation? Asking because even if the >>>>>>> function is only used by one caller, I could see a benefit to be able to >>>>>>> use different value for the ratelimit. So I leaning towards keep the >>>>>>> code as-is. >>>>>> >>>>>> +1 >>>>>> >>>>>> In fact I'm surprised (or maybe not) that we still don't make better use >>>>>> the rate limiting functionality. >>>>> >>>>> Out of curiosity, do you have any ideas re: make better use of the rate >>>>> limiting functionality? >>>> >>>> No concrete ones; thinking about this has been way too long ago. >>>> >>>>> Build-time parameterization? >>>> >>>> That and/or command line controls. >>> >>> Got it. >>> >>> Can you please explain why exporting __printk_ratelimit() is still required >>> for implementation of build/command line settings in console.c? >> >> I didn't say console.c, did I? Whatever subsystem wanted to do proper rate > > But you also did not say anything about idea of having per-subsystem rate > limiting. > >> limiting would need to gain some way of controlling this (as said, build >> time or cmdline driven), and it'll then need that function: How would it >> effect the behavior with custom ms and/or burst values, without having >> that function to call? (It is another thing that the function, using static >> variables rather than per-caller state, may not be quite ready for that >> kind of use. Also the arbitrary and hard-coded 10 * 5 * 1000 there would >> probably also want to be customizable.) >> >> What you may want to do for Misra's sake is make the function static for >> the time being. The compiler will then fold it into its sole caller, >> until some new user appears. (At that occasion dropping one of the >> underscores may also be reasonable.) > > Do I understand it correctly that you will accept the following submission: > 1) make __printk_ratelimit() static > 2) drop one underscore from the name Yes, if you really think that's worth it. Jan > 3) keep the only call __printk_ratelimit() in a hope of there will be > per-subsystem rate limiting in the future? > > -- > Denis > >> >> Jan >> > From xen-devel-bounces@lists.xenproject.org Fri Aug 01 07:34:57 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 07:34:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1066929.1431955 (Exim 4.92) (envelope-from ) id 1uhkI3-000150-RV; Fri, 01 Aug 2025 07:34:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1066929.1431955; Fri, 01 Aug 2025 07:34:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhkI3-00014r-OR; Fri, 01 Aug 2025 07:34:55 +0000 Received: by outflank-mailman (input) for mailman id 1066929; Fri, 01 Aug 2025 07:34:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhkI2-00014g-Mr for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 07:34:54 +0000 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [2a00:1450:4864:20::436]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 035cb61d-6eaa-11f0-b895-0df219b8e170; Fri, 01 Aug 2025 09:34:53 +0200 (CEST) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3b78127c5d1so903880f8f.3 for ; Fri, 01 Aug 2025 00:34:52 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Fri, 01 Aug 2025 00:34:52 -0700 (PDT) Message-ID: Date: Fri, 1 Aug 2025 09:34:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] ns16550: ensure polling timer is disarmed To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250730031249.1613142-1-dmukhin@ford.com> <5a4dc92b-139d-4fa5-9baf-2ebc41bba758@suse.com> <78128ec6-b79f-4d4c-a298-72315b190036@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 23:42, dmkhn@proton.me wrote: > On Thu, Jul 31, 2025 at 08:54:10AM +0200, Jan Beulich wrote: >> On 30.07.2025 20:31, dmkhn@proton.me wrote: >>> On Wed, Jul 30, 2025 at 10:12:54AM +0200, Jan Beulich wrote: >>>> On 30.07.2025 05:13, dmkhn@proton.me wrote: >>>>> From: Denis Mukhin >>>>> >>>>> As it stands, polling timer is kept in the list of timers even after the >>>>> interrupts have been enabled / polling disabled on ns16550-compatible UART. >>>>> >>>>> Ensure polling timer is removed from the timer list once UART interrupts are >>>>> enabled. >>>>> >>>>> Signed-off-by: Denis Mukhin >>>> >>>> Wasn't it Andrew(?) who suggested something along these lines? That would >>>> want reflecting by a tag then. >>> >>> Yes, indeed. >>> >>>> >>>> Also, what's the real problem you want to solve here? The timer function >>>> would be run one more time after ->intr_works is set, and then the timer >>>> will be permanently inactive (up to a possible S3 resume). Is it being on >>>> an inactive list an actual problem? (IOW I'd like to understand if the >>>> change is merely cosmetic, or if there is some actual benefit.) >>> >>> My understanding is running polling timer one more time after the interrupts >>> are enabled is the issue: if there's a pending timer when it is known the >>> timer not needed, then the timer should be canceled. >> >> And the effort of canceling outweighs the one extra running of the timer? > > I think so, because intr_works will not flip at run-time once set. > If so, no need to keep the timer ready to be rearmed. Well, to me it looks like a code size increase with extremely limited benefit. Hence while likely I wouldn't outright NAK such a change, I also wouldn't ACK it. Jan From xen-devel-bounces@lists.xenproject.org Fri Aug 01 09:22:57 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 09:22:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067002.1431970 (Exim 4.92) (envelope-from ) id 1uhlyT-0006Kh-8Q; Fri, 01 Aug 2025 09:22:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067002.1431970; Fri, 01 Aug 2025 09:22:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhlyT-0006Ka-5i; Fri, 01 Aug 2025 09:22:49 +0000 Received: by outflank-mailman (input) for mailman id 1067002; Fri, 01 Aug 2025 09:22:47 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhlyR-0006KP-C0 for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 09:22:47 +0000 Received: from AM0PR83CU005.outbound.protection.outlook.com (mail-westeuropeazlp170100001.outbound.protection.outlook.com [2a01:111:f403:c201::1]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 15d0b99e-6eb9-11f0-a320-13f23c93f187; Fri, 01 Aug 2025 11:22:46 +0200 (CEST) Received: from AS2PR03MB10110.eurprd03.prod.outlook.com (2603:10a6:20b:57a::22) by VI1PR03MB6144.eurprd03.prod.outlook.com (2603:10a6:800:141::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8989.16; Fri, 1 Aug 2025 09:22:42 +0000 Received: from AS2PR03MB10110.eurprd03.prod.outlook.com ([fe80::52f0:1815:60c9:8873]) by AS2PR03MB10110.eurprd03.prod.outlook.com ([fe80::52f0:1815:60c9:8873%5]) with mapi id 15.20.8964.023; Fri, 1 Aug 2025 09:22:42 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 15d0b99e-6eb9-11f0-a320-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=wOdqgXYZkxcTQR75XTMrOwVzDYH0LzfbrJXPtnoGcdSQgv8XUFUAvsMCSDkF3o+Eb0bhZ0ECBVVu3EZ/SEUsBH+Hcrk+DnuRCcuc4Qbl1jqGr8MvqTNZ65w35pj4eMhnMHXGu+OOdadL7EDtVhBHAObHuznLLdHWHH38Wi5QO2MSm7R/UHoz2KOwhSycKJpUP7E8uwLEVOgY/0xX3SIqf/DtwoG4L2SJuqBNni1GrR9aDip5ggZMuoFQTDPGMhF0aO7140r9wR6v+BFmAJGGHrqPKcKZdnozJ03aKyUvcO8vVaTjKFVzzztyIYv/9DQcTm6ciIJ1Vd35bOHPWOrLSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Dtx8p9qHm8yinBn9Qrplu2+CNXgBCVcnXs1ePwe02dA=; b=sbwuAp64lp6E0CIFjaLPt2tRVp3b31msygZTrnyRvJRWzqFIaG9CCnkaQyGyBa6im/g9nSQ5AEJg/dJpi1HM2j78m6qtEheR9+hTRGRZ+I+xdaLx/t1sXwzaZ2UIJmsuEm0+/894vNJNdHiln7ToyHah0741tHZ+ApJHdRisKrc0Lkb1VyyEstsMQEYW8h/QKG2G0OpYApAu9n2A5uOg8ooDnX8A6qMaV/gTzx/SuMJLO3lr0SbgfA1aJ2htUvaSEn3MaJZjW0zu3KHl/BZqlqCr741YXsXDfuZkiBFYirDZ1fELgGEMWWGa05O+e6h0yPuxW7Q05rf1+FX642xD/A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=epam.com; dmarc=pass action=none header.from=epam.com; dkim=pass header.d=epam.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=epam.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Dtx8p9qHm8yinBn9Qrplu2+CNXgBCVcnXs1ePwe02dA=; b=M/SrNqRODOCuA7FkiBcf0pJu4v3b+ig1Ks6n9zlGXPT24w25ACKVeLEPmTq7B3TUY+MFYCPtekpguh42PTQroeY9saM2gGjbyFaehG/RM4ejk9APBRxoAyZjBKhPj7vZsSPaRiDJNPobFtMlNyBSVqHgsewV4sN/ddWL01Gr0SABo2aoZbTOgdcgY26HMqQ3OB5fnZU+xkj0jIySGO8U9UcfQkFWAMAKAnxc0GPA13E6wMDrLQqe8C9WrA7vXL7JEvKgxAtJhmDsuWgqhcA5O2rqI2mI++kAUtiCzPoa2rwzIHa5uCH6Qjunmz0Affxxc8z0FdDv78CJ86v0S4NTGQ== From: Mykyta Poturai To: "xen-devel@lists.xenproject.org" CC: Mykyta Poturai , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , "Daniel P. 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB10110.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5b3d8938-b0df-4bb7-367b-08ddd0dcf7ad X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 09:22:42.2747 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: UAM7G/W93dXWmXq3s6ZsczgFpXf7ZYsgxHnbixO/c6s+ZT5Rx/+d+eg7ATQdrhjZTkgAzNMcPJmnj0kpcAc2tQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR03MB6144 This series adds basic PCI device enumeration in Xen. This will allow us to= not rely on Dom0 enumeration for supported controllers, which will enable PCI passthrough for dom0less setups. Enumeration is disabled by default and can be enabled with "pci-scan" cmdli= ne option. Discovered devices are added to Xen and assigned to dom_io by defau= lt. Edward Pickup (1): arm/pci: Add pci-scan boot argument Luca Fancellu (2): xen/pci: modify pci_add_device to handle device add by Xen xen/pci: add discovered PCI device at boot docs/misc/xen-command-line.pandoc | 7 ++++ xen/arch/arm/include/asm/pci.h | 11 ++++++ xen/arch/arm/pci/pci-host-common.c | 1 + xen/arch/arm/pci/pci.c | 27 ++++++++++++- xen/arch/x86/physdev.c | 9 ++--- xen/drivers/passthrough/pci.c | 62 +++++++++++++++++++++++------- xen/drivers/pci/physdev.c | 3 +- xen/include/xen/pci.h | 4 +- 8 files changed, 102 insertions(+), 22 deletions(-) --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 09:22:57 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 09:22:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067003.1431979 (Exim 4.92) (envelope-from ) id 1uhlyV-0006Yb-KC; Fri, 01 Aug 2025 09:22:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067003.1431979; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB10110.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a3558229-a14a-40ba-93ba-08ddd0dcf80c X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 09:22:42.7687 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4tlqLzpDlpN8ckIrqlWBS98Uuij3EKWnilJDXBtf6vzIDlnesUt33hDHqoPvkSPbN7SzLMmgBkgoJnnSbKyp1w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR03MB10032 From: Edward Pickup This patch adds a Xen boot arguments that, if enabled, causes a call to existing code to scan pci devices enumerated by the firmware. This patch also makes an existing debug function viewable outside its translation unit, and uses this to dump the PCI devices found. The debug message is controlled by config DEBUG. Additionally, this patch modifies segment loading to ensure that PCI devices on other segments are properly found. This will be needed ahead of dom0less support for pci passthrough on arm. Signed-off-by: Luca Fancellu Signed-off-by: Edward Pickup Signed-off-by: Mykyta Poturai --- (cherry picked from commit bce463e1588a45e1bfdf59fc0d5f88b16604e439 from the downstream branch poc/pci-passthrough from https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git) changes since cherry-pick: * s/always_inline/inline/ * replace additional kconfig option with config DEBUG Signed-off-by: Stewart Hildebrand --- docs/misc/xen-command-line.pandoc | 7 +++++++ xen/arch/arm/include/asm/pci.h | 11 +++++++++++ xen/arch/arm/pci/pci-host-common.c | 1 + xen/arch/arm/pci/pci.c | 26 ++++++++++++++++++++++++-- xen/drivers/passthrough/pci.c | 2 +- xen/include/xen/pci.h | 1 + 6 files changed, 45 insertions(+), 3 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index 6865a61220..72c122ea32 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -2058,6 +2058,13 @@ This option can be specified more than once (up to 8= times at present). =20 Flag to enable or disable support for PCI passthrough =20 +### pci-scan (arm) +> `=3D ` + +> Default: `false` + +Flag to enable or disable Xen PCI scan at boot. + ### pcid (x86) > `=3D | xpti=3D` =20 diff --git a/xen/arch/arm/include/asm/pci.h b/xen/arch/arm/include/asm/pci.= h index 08ffcd4438..0afdc90de0 100644 --- a/xen/arch/arm/include/asm/pci.h +++ b/xen/arch/arm/include/asm/pci.h @@ -23,6 +23,7 @@ #define pci_to_dev(pcidev) (&(pcidev)->arch.dev) =20 extern bool pci_passthrough_enabled; +extern bool pci_scan_enabled; =20 struct rangeset; =20 @@ -128,6 +129,11 @@ static always_inline bool is_pci_passthrough_enabled(v= oid) return pci_passthrough_enabled; } =20 +static inline bool is_pci_scan_enabled(void) +{ + return pci_scan_enabled; +} + void arch_pci_init_pdev(struct pci_dev *pdev); =20 int pci_get_new_domain_nr(void); @@ -155,6 +161,11 @@ bool arch_pci_device_physdevop(void); =20 #else /*!CONFIG_HAS_PCI*/ =20 +static inline bool is_pci_scan_enabled(void) +{ + return false; +} + struct pci_dev; =20 static inline void arch_pci_init_pdev(struct pci_dev *pdev) {} diff --git a/xen/arch/arm/pci/pci-host-common.c b/xen/arch/arm/pci/pci-host= -common.c index 487c545f3a..d3481b05eb 100644 --- a/xen/arch/arm/pci/pci-host-common.c +++ b/xen/arch/arm/pci/pci-host-common.c @@ -284,6 +284,7 @@ pci_host_common_probe(struct dt_device_node *dev, } =20 pci_add_host_bridge(bridge); + pci_add_segment(bridge->segment); =20 return bridge; =20 diff --git a/xen/arch/arm/pci/pci.c b/xen/arch/arm/pci/pci.c index beb1f971fa..eea264db0e 100644 --- a/xen/arch/arm/pci/pci.c +++ b/xen/arch/arm/pci/pci.c @@ -91,8 +91,13 @@ bool arch_pci_device_physdevop(void) bool __read_mostly pci_passthrough_enabled; boolean_param("pci-passthrough", pci_passthrough_enabled); =20 +/* By default pci scan is disabled. */ +bool __read_mostly pci_scan_enabled; +boolean_param("pci-scan", pci_scan_enabled); + static int __init pci_init(void) { + int ret; /* * Enable PCI passthrough when has been enabled explicitly * (pci-passthrough=3Don). @@ -104,9 +109,26 @@ static int __init pci_init(void) panic("Could not initialize PCI segment 0\n"); =20 if ( acpi_disabled ) - return dt_pci_init(); + ret =3D dt_pci_init(); else - return acpi_pci_init(); + ret =3D acpi_pci_init(); + + if ( ret < 0 ) + return ret; + + if ( is_pci_scan_enabled() ) + { + ret =3D scan_pci_devices(); + + if ( ret < 0 ) + return ret; + +#ifdef DEBUG + dump_pci_devices('c'); +#endif + } + + return 0; } __initcall(pci_init); =20 diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 3edcfa8a04..fa03dafac7 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -1384,7 +1384,7 @@ static int cf_check _dump_pci_devices(struct pci_seg = *pseg, void *arg) return 0; } =20 -static void cf_check dump_pci_devices(unsigned char ch) +void cf_check dump_pci_devices(unsigned char ch) { printk("=3D=3D=3D=3D PCI devices =3D=3D=3D=3D\n"); pcidevs_lock(); diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 130c2a8c1a..5c242278b9 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -217,6 +217,7 @@ static always_inline bool pcidevs_trylock(void) bool pci_known_segment(u16 seg); bool pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func); int scan_pci_devices(void); +void dump_pci_devices(unsigned char ch); enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn); int find_upstream_bridge(u16 seg, u8 *bus, u8 *devfn, u8 *secbus); =20 --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 09:22:57 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 09:22:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067005.1432000 (Exim 4.92) (envelope-from ) id 1uhlyY-00071O-7V; Fri, 01 Aug 2025 09:22:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067005.1432000; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB10110.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 519d7477-261b-45d8-8870-08ddd0dcf8d1 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 09:22:43.6923 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: xuQ6ahSRdINkBeeN5rYgu6evqCSZbfF6OCzLGHm387PKm/GeLXSu8Quv8rcrBcp3BSzsrSd1Dmx+7sb1t5KYvg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR03MB10032 From: Luca Fancellu Create add_discovered_pci_devices function that calls pci_device_add on every PCI device discovered. The devices will be added to dom_io so that they can be assigned later to other domains. Signed-off-by: Luca Fancellu Signed-off-by: Mykyta Poturai --- (cherry picked from commit eff51e50021b75f5a50533f7de681b2ce044f5bd from the downstream branch poc/pci-passthrough from https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git) --- xen/arch/arm/pci/pci.c | 1 + xen/drivers/passthrough/pci.c | 28 ++++++++++++++++++++++++++++ xen/include/xen/pci.h | 1 + 3 files changed, 30 insertions(+) diff --git a/xen/arch/arm/pci/pci.c b/xen/arch/arm/pci/pci.c index eea264db0e..b2426878ee 100644 --- a/xen/arch/arm/pci/pci.c +++ b/xen/arch/arm/pci/pci.c @@ -123,6 +123,7 @@ static int __init pci_init(void) if ( ret < 0 ) return ret; =20 + add_discovered_pci_devices(); #ifdef DEBUG dump_pci_devices('c'); #endif diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 49a39d69db..d6f1c78701 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -1180,6 +1180,34 @@ int __init scan_pci_devices(void) return ret; } =20 +static int __init _add_discovered_pci_devices(struct pci_seg *pseg, void *= arg) +{ + struct pci_dev *pdev; + int ret =3D 0; + + list_for_each_entry ( pdev, &pseg->alldevs_list, alldevs_list ) + { + ret =3D pci_add_device(dom_io, pdev->seg, pdev->bus, pdev->devfn, = NULL, + NUMA_NO_NODE); + if ( ret < 0 ) + { + printk(XENLOG_ERR + "%pp: Failure adding the discovered pci device (Error %= d)\n", + &pdev->sbdf, ret); + break; + } + } + + return ret; +} + +void __init add_discovered_pci_devices(void) +{ + pcidevs_lock(); + pci_segments_iterate(_add_discovered_pci_devices, NULL); + pcidevs_unlock(); +} + struct setup_hwdom { struct domain *d; int (*handler)(uint8_t devfn, struct pci_dev *pdev); diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 77a44aea70..81c0c23604 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -217,6 +217,7 @@ static always_inline bool pcidevs_trylock(void) bool pci_known_segment(u16 seg); bool pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func); int scan_pci_devices(void); +void add_discovered_pci_devices(void); void dump_pci_devices(unsigned char ch); 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Smith" , Mykyta Poturai Subject: [PATCH v1 2/3] xen/pci: modify pci_add_device to handle device add by Xen Thread-Topic: [PATCH v1 2/3] xen/pci: modify pci_add_device to handle device add by Xen Thread-Index: AQHcAsXVSnyGYKO2WEup/omKSt+BHQ== Date: Fri, 1 Aug 2025 09:22:43 +0000 Message-ID: <32cf834e95664805604b13d10bcaa857897f0890.1753968306.git.mykyta_poturai@epam.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: AS2PR03MB10110:EE_|VI1PR03MB10032:EE_ x-ms-office365-filtering-correlation-id: e0adab0a-389b-49e2-2b06-08ddd0dcf887 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|38070700018; x-microsoft-antispam-message-info: =?iso-8859-1?Q?lzt0XJvpf5GNBAVYxzS8XNBUyLFEOTwfoHpQUVhxclER5ZqLkb8pu02XRl?= =?iso-8859-1?Q?L0ORC9V4g8aNPnsT8GSOYB9Wrbm4ntrzdNnzkNVjxl04l0Zgvm5xA4CK31?= =?iso-8859-1?Q?vMRWECCAtrVU7ygn+l3ZunOnzPqMhPCdYXjxozoVrJRUAE/KHjGI9YebL6?= =?iso-8859-1?Q?ciwVBvJC7Hm5q1r563gWa6XxtrYHyTVnrrvD+NN2Se0locup8YJyL2+X5n?= =?iso-8859-1?Q?Ixs+NbMTNj8HojjCrgsCLIjWjPpCJcnzp2qmxEZrSR5Jmo4HJ1L2tPX1kI?= =?iso-8859-1?Q?CdW2FQqkWCHdCH5Q2257fUx738BExELy581rJEr6tGN3zUXR+YQVCbwboL?= =?iso-8859-1?Q?S+YM7pgh/rBN7Ul2wbCn5nxZI28kv0aLXZVtkfNxn0QGK2nS7Vffevd2Ii?= =?iso-8859-1?Q?sl6PNcCagCEXUXgVpYk2OCTJgMsu8dJRbzFfH77+CcOIUnBSuIUeRlQTmp?= =?iso-8859-1?Q?wW5RCCSKbznmvPWoZSTd4FSvPPPSLkeBvlJ030MO4TRzKLKcUzOn/ieJ/S?= =?iso-8859-1?Q?HBqMzEQkEaF+MDE8fgrAQNXPVgMucyzDb3EdVeGjLmaVZwIiM5Z6Spa+FV?= =?iso-8859-1?Q?ud8MKoc1tVY9ARN4a/dMKfL8uZp3Ch39aCW2Z777hq9DrbcTmt70b65OjE?= =?iso-8859-1?Q?3v9UweWAXVuVTNnObE41cRDida4gclOmr30xKrgWWwTsV15cSH9F4PFEM2?= =?iso-8859-1?Q?wTxz+yBgIkgBBGZ94PjWIZoSB3vfKmTu8cX4JDqhCobT6SwnFvYw/hSn5T?= =?iso-8859-1?Q?0XGBnyZ1k7qQP/AM2pMCT7nKulh5PSVgOpGg6XmAecxqXO+ri6DhQEDCp2?= =?iso-8859-1?Q?f+btlxWa9XZflx25osfqWS5DR6ZAQ9zMFH1kWV1yN9h2PULHrZt7lMfyTt?= =?iso-8859-1?Q?S0+vv8c+ahSAMw03lZflQDs70w2m2bO7XPuDeDWIVj9ciKzOz52Bp2AkWQ?= =?iso-8859-1?Q?4tB38OiDE+g9uoksCG8fktljryjLtMhGZK/O4d2kIPHVUSvBLt5cCWDOxi?= =?iso-8859-1?Q?DnMhxxeandxNM+E0jXYj++VIydbL9kFzRZlzEAWxzV92G/eVhiUUyu1X7I?= =?iso-8859-1?Q?Z9wkjx9LpLA4KdZsP3ECtv9CgHzhtbv/QIjFJhLcvf0FwfNZIF0I7rqzG/?= =?iso-8859-1?Q?xdV84BJpyV8tVtc4eKmmnvYmOEcOjzXPwK7cIlT+plmjhNwy20iUsgLPPT?= =?iso-8859-1?Q?Qc0VlzDN0zLD/pgthIz9VxvGcoiY8mINiKyhsmzbGROIJBT8VuKWgh32nv?= =?iso-8859-1?Q?1z8Dr3AMw502cYiVfyx0MtyeG4fXqIVYwd73b+3cNgSNVf4Id5lf95lTrI?= =?iso-8859-1?Q?RB3/gEI5vXRiNiVKvZz1b0yu7KBYA1RGzU/aSwfejfZ73znPSMla1aIhjo?= =?iso-8859-1?Q?mV9HASUxXVPwQaJ2GIKGX1M+PnQQvcDRK4+BZmp0ICEZNRD7k2fDZ6t1pi?= =?iso-8859-1?Q?HiQ/yFr/Wp78eI9h4HY6uw39wboWYSAE1Av9EES4kBEcTtXR4VBaY58lLe?= =?iso-8859-1?Q?EFM67FuQnZXixIxWniz1Jf0n/0J0XmddAgY52sNpU/EjTD+AcXFqo7Tgtp?= =?iso-8859-1?Q?bIoqtlw=3D?= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AS2PR03MB10110.eurprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(7416014)(366016)(1800799024)(38070700018);DIR:OUT;SFP:1101; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB10110.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e0adab0a-389b-49e2-2b06-08ddd0dcf887 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 09:22:43.2717 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dbZZQK/UQt/EQAnTtI2KXvP5z4n7WFq53WAoQ49sX86/4cf0pSOOiVSrbAQ1wLrU/uuw5rMCougVGu/kt6nZiA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR03MB10032 From: Luca Fancellu Currently pci_add_device is called from hypercalls requested by Dom0 to add pci devices and when the device has no domain associated with it, it is assumed that hardware_domain is the owner. On the dom0less scenario, the enumeration is performed by the firmware and Xen at boot time might want to assign some pci devices to guests, so it has to firstly add the device and then assign it to the final guest. Modify pci_add_device to have the owner domain passed as a parameter to the function, so that when it is called from the hypercall the owner would be the hardware domain, otherwise when Xen is calling it, it would be another domain since hw domain could not be there (dom0less guests without Dom0 use case). In pci_add_device there is a call to xsm that doesn't consider the requester of the function to be Xen itself, so add a check to skip the call if the owner domain is dom_io, since it means the call is coming directly from Xen. Signed-off-by: Luca Fancellu Signed-off-by: Mykyta Poturai --- (cherry picked from commit f0c85d9043f7c9402e85b73361c8a13c683428ca from the downstream branch poc/pci-passthrough from https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git) changes since cherry-pick: * s/hardware_domain/d/ in some write_unlock calls in xen/drivers/passthroug= h/pci.c --- xen/arch/x86/physdev.c | 9 ++++----- xen/drivers/passthrough/pci.c | 32 ++++++++++++++++++++------------ xen/drivers/pci/physdev.c | 3 ++- xen/include/xen/pci.h | 2 +- 4 files changed, 27 insertions(+), 19 deletions(-) diff --git a/xen/arch/x86/physdev.c b/xen/arch/x86/physdev.c index 4dfa1c0191..9e894ce665 100644 --- a/xen/arch/x86/physdev.c +++ b/xen/arch/x86/physdev.c @@ -446,8 +446,8 @@ ret_t do_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(voi= d) arg) if ( copy_from_guest(&manage_pci, arg, 1) !=3D 0 ) break; =20 - ret =3D pci_add_device(0, manage_pci.bus, manage_pci.devfn, - NULL, NUMA_NO_NODE); + ret =3D pci_add_device(hardware_domain, 0, manage_pci.bus, + manage_pci.devfn, NULL, NUMA_NO_NODE); break; } =20 @@ -477,9 +477,8 @@ ret_t do_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(voi= d) arg) pdev_info.is_virtfn =3D manage_pci_ext.is_virtfn; pdev_info.physfn.bus =3D manage_pci_ext.physfn.bus; pdev_info.physfn.devfn =3D manage_pci_ext.physfn.devfn; - ret =3D pci_add_device(0, manage_pci_ext.bus, - manage_pci_ext.devfn, - &pdev_info, NUMA_NO_NODE); + ret =3D pci_add_device(hardware_domain, 0, manage_pci_ext.bus, + manage_pci_ext.devfn, &pdev_info, NUMA_NO_NOD= E); break; } =20 diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index fa03dafac7..49a39d69db 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -654,7 +654,7 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned= int pos, return is64bits ? 2 : 1; } =20 -int pci_add_device(u16 seg, u8 bus, u8 devfn, +int pci_add_device(struct domain *d, u16 seg, u8 bus, u8 devfn, const struct pci_dev_info *info, nodeid_t node) { struct pci_seg *pseg; @@ -672,9 +672,12 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, else type =3D "device"; =20 - ret =3D xsm_resource_plug_pci(XSM_PRIV, (seg << 16) | (bus << 8) | dev= fn); - if ( ret ) - return ret; + if ( d !=3D dom_io ) + { + ret =3D xsm_resource_plug_pci(XSM_PRIV, (seg << 16) | (bus << 8) |= devfn); + if ( ret ) + return ret; + } =20 ret =3D -ENOMEM; =20 @@ -767,9 +770,9 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, ret =3D 0; if ( !pdev->domain ) { - pdev->domain =3D hardware_domain; - write_lock(&hardware_domain->pci_lock); - list_add(&pdev->domain_list, &hardware_domain->pdev_list); + pdev->domain =3D d; + write_lock(&d->pci_lock); + list_add(&pdev->domain_list, &pdev->domain->pdev_list); =20 /* * For devices not discovered by Xen during boot, add vPCI handler= s @@ -779,25 +782,30 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn, if ( ret ) { list_del(&pdev->domain_list); - write_unlock(&hardware_domain->pci_lock); + write_unlock(&d->pci_lock); pdev->domain =3D NULL; printk(XENLOG_ERR "Setup of vPCI failed: %d\n", ret); goto out; } - write_unlock(&hardware_domain->pci_lock); + write_unlock(&d->pci_lock); ret =3D iommu_add_device(pdev); if ( ret ) { - write_lock(&hardware_domain->pci_lock); + write_lock(&d->pci_lock); vpci_deassign_device(pdev); list_del(&pdev->domain_list); - write_unlock(&hardware_domain->pci_lock); + write_unlock(&d->pci_lock); pdev->domain =3D NULL; goto out; } } - else + else if ( pdev->domain =3D=3D d ) iommu_enable_device(pdev); + else + { + ret =3D -EINVAL; + goto out; + } =20 pci_enable_acs(pdev); =20 diff --git a/xen/drivers/pci/physdev.c b/xen/drivers/pci/physdev.c index d46501b884..1b59bf1246 100644 --- a/xen/drivers/pci/physdev.c +++ b/xen/drivers/pci/physdev.c @@ -50,7 +50,8 @@ ret_t pci_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void= ) arg) } #endif =20 - ret =3D pci_add_device(add.seg, add.bus, add.devfn, &pdev_info, no= de); + ret =3D pci_add_device(hardware_domain, add.seg, add.bus, add.devf= n, + &pdev_info, node); break; } =20 diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index 5c242278b9..77a44aea70 100644 --- a/xen/include/xen/pci.h +++ b/xen/include/xen/pci.h @@ -227,7 +227,7 @@ void setup_hwdom_pci_devices(struct domain *d, int pci_release_devices(struct domain *d); int pci_add_segment(u16 seg); const unsigned long *pci_get_ro_map(u16 seg); -int pci_add_device(u16 seg, u8 bus, u8 devfn, +int pci_add_device(struct domain *d, u16 seg, u8 bus, u8 devfn, const struct pci_dev_info *info, nodeid_t node); int pci_remove_device(u16 seg, u8 bus, u8 devfn); int pci_ro_device(int seg, int bus, int devfn); --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 09:54:12 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 09:54:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067058.1432014 (Exim 4.92) (envelope-from ) id 1uhmSj-0003hK-J4; Fri, 01 Aug 2025 09:54:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067058.1432014; Fri, 01 Aug 2025 09:54:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhmSj-0003hD-G6; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Jul 31, 2025 at 4:35=E2=80=AFPM Jan Beulich wro= te: > > On 25.07.2025 17:06, Edwin T=C3=B6r=C3=B6k wrote: > > Using `aa2u` tool. > > > > Signed-off-by: Edwin T=C3=B6r=C3=B6k > > How come the use of that tool made ... > > > --- a/xen/include/public/arch-x86/pmu.h > > +++ b/xen/include/public/arch-x86/pmu.h > > @@ -75,8 +75,10 @@ DEFINE_XEN_GUEST_HANDLE(xen_pmu_regs_t); > > #define PMU_SAMPLE_PV (1<<3) /* Sample from a PV guest */ > > > > /* > > - * Architecture-specific information describing the state of the guest= at > > - * the time of a PMU interrupt. > > + * Architecture-specific information describing state of the guest at > > + * the time of PMU interrupt. > > + * Even if the interrupt arrived while inside Xen, this will always co= ntain > > + * the guest's state. > > */ > > struct xen_pmu_arch_guest { Thanks for spotting, according to my evolog this one ended up here while fixing a rebase conflict: ``` =E2=97=8B lrwoxosk hidden edwin.torok@cloud.com 2025-07-24 13:20:56 215f9e= 58 =E2=94=82 arch-x86/pmu.h: convert ascii art diagram to Unicode =E2=94=82 -- operation 073584199528 (2025-07-24 13:20:56) snapshot working= copy =E2=94=82 diff --git a/xen/include/public/arch-x86/pmu.h b/xen/include/public/arch-x86/pmu.h =E2=94=82 index 0000000000..4dc3d9a20a 100644 =E2=94=82 --- a/xen/include/public/arch-x86/pmu.h =E2=94=82 +++ b/xen/include/public/arch-x86/pmu.h =E2=94=82 @@ -75,8 +75,10 @@ =E2=94=82 #define PMU_SAMPLE_PV (1<<3) /* Sample from a PV guest */ =E2=94=82 =E2=94=82 /* =E2=94=82 - * Architecture-specific information describing the state of th= e guest at =E2=94=82 - * the time of a PMU interrupt. =E2=94=82 + * Architecture-specific information describing state of the gu= est at =E2=94=82 + * the time of PMU interrupt. =E2=94=82 + * Even if the interrupt arrived while inside Xen, this will al= ways contain =E2=94=82 + * the guest's state. =E2=94=82 */ =E2=94=82 struct xen_pmu_arch_guest { =E2=94=82 union { =E2=94=82 @@ -149,178 +151,89 @@ =E2=94=82 typedef struct xen_pmu_arch xen_pmu_arch_t; =E2=94=82 DEFINE_XEN_GUEST_HANDLE(xen_pmu_arch_t); =E2=94=82 =E2=94=82 - =E2=94=82 /* Memory layout: =E2=94=82 -<<<<<<< Conflict 1 of 1 =E2=94=82 -+++++++ Contents of side #1 ``` > > ... this comment change, or yet more interesting, ... > > > --- a/xen/include/public/pmu.h > > +++ b/xen/include/public/pmu.h > > @@ -148,7 +148,7 @@ struct xen_pmu_hv_stacktrace { > > * arrives while in Xen. > > * */ > > struct xen_pmu_arch_guest guest; > > -#define XEN_PMU_STACKTRACE_PAD 48 > > +#define XEN_PMU_STACKTRACE_PAD 56 > > uint8_t pad2[XEN_PMU_STACKTRACE_PAD]; > > }; > > ... this value in the public interface? Thanks for spotting, it doesn't belong in this commit. I would assume that this happened by squashing a commit into the wrong place, or by editing the wrong commit while rebasing. Luckily I use 'jj', and it has an evolog that stores the full history of how a commit changed over split/squash/rebase, so I don't have to guess, but can give you a precise answer. My evolog says that this change came from editing the source code while having the wrong commit checked out (I kept tweaking those values): ``` =E2=97=8B lrwoxosk hidden edwin.torok@cloud.com 2025-07-24 13:46:44 bfa295= 64 =E2=94=82 arch-x86/pmu.h: convert ascii art diagram to Unicode =E2=94=82 -- operation 3f48136a1b6a (2025-07-24 13:46:44) snapshot working= copy =E2=94=82 diff --git a/xen/include/public/pmu.h b/xen/include/public/pmu.h =E2=94=82 index 1879914ea6..6366a79169 100644 =E2=94=82 --- a/xen/include/public/pmu.h =E2=94=82 +++ b/xen/include/public/pmu.h =E2=94=82 @@ -148,7 +148,7 @@ =E2=94=82 * arrives while in Xen. =E2=94=82 * */ =E2=94=82 struct xen_pmu_arch_guest guest; =E2=94=82 -#define XEN_PMU_STACKTRACE_PAD 48 =E2=94=82 +#define XEN_PMU_STACKTRACE_PAD 56 =E2=94=82 uint8_t pad2[XEN_PMU_STACKTRACE_PAD]; =E2=94=82 }; ``` Before I submit the next version I'll check whether the other hunks ended up in the right place after all the squashing/rebasing/splitting Best regards, --Edwin > > Jan From xen-devel-bounces@lists.xenproject.org Fri Aug 01 10:09:04 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 10:09:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067065.1432024 (Exim 4.92) (envelope-from ) id 1uhmhA-0005WW-SS; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3327ac93-cfce-4ea6-aad7-08ddd0e36c0c X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 10:08:54.5086 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Hvhgm4K5C1175Q98gW95BNzz6sRDSGzqXnAVfXT1NJhy4/xa3mwMyerHRzfpr/CAeFa9Kltq4S4p7ccBVb4b/bLV9cCDCmtNN7Euf+8xfZk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR03MB6604 From: Grygorii Strashko Hence prerequisite patch was merged [1] arch specific pIRQ callback can now be dropped for arches without pIRQ support as those callback become unreach= able. [1] commit 341f271cf86f ("xen/evtchn: fully restrict concept of pIRQ for ar= ches with pIRQ support only") Grygorii Strashko (3): xen/arm: irq: drop unreachable pirq callbacks xen/ppc: irq: drop unreachable pirq callbacks xen/riscv: irq: drop unreachable pirq callbacks xen/arch/arm/irq.c | 29 ----------------------------- xen/arch/ppc/stubs.c | 20 -------------------- xen/arch/riscv/stubs.c | 20 -------------------- 3 files changed, 69 deletions(-) --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 10:09:04 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 10:09:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067066.1432030 (Exim 4.92) (envelope-from ) id 1uhmhB-0005Zi-4n; Fri, 01 Aug 2025 10:09:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067066.1432030; Fri, 01 Aug 2025 10:09:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhmhA-0005ZN-VY; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 577b1e57-9776-4cc6-8942-08ddd0e36cb0 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 10:08:54.9786 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: UqG8pTQ4VpenTvCN4bhPlAxicEiqj768lqJeb4MB3FCfevFxEKQmb5TszRrZArAJiaiXkWxops7qAJPTSe8WftnlZCXqupqFrgWDGhdKkoA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR03MB6604 From: Grygorii Strashko Hence all common pIRQ code is under CONFIG_HAS_PIRQ idefs corresponding Arm arch pIRQ callbacks become unreachable, so drop them. Signed-off-by: Grygorii Strashko --- xen/arch/arm/irq.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 03fbb90c6c43..4bbf0b0664df 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -595,35 +595,6 @@ unlock: return ret; } =20 -/* - * pirq event channels. We don't use these on ARM, instead we use the - * features of the GIC to inject virtualised normal interrupts. - */ -struct pirq *alloc_pirq_struct(struct domain *d) -{ - return NULL; -} - -/* - * These are all unreachable given an alloc_pirq_struct - * which returns NULL, all callers try to lookup struct pirq first - * which will fail. - */ -int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) -{ - BUG(); -} - -void pirq_guest_unbind(struct domain *d, struct pirq *pirq) -{ - BUG(); -} - -void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) -{ - BUG(); -} - static bool irq_validate_new_type(unsigned int curr, unsigned int new) { return (curr =3D=3D IRQ_TYPE_INVALID || curr =3D=3D new ); --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 10:09:04 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 10:09:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067068.1432049 (Exim 4.92) (envelope-from ) id 1uhmhC-00060C-MI; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 54cab3d1-c786-4819-7b75-08ddd0e36d00 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 10:08:55.6840 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: R514XdBWZSAbClVlvqXQQu42eGb3pw1aT4JIcIA3SxJJSs7H+igddqoHg64OiIuSSr5gt14pbCF0peeF/7D+MIyfTUoy1IdICajgVGCnCcM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR03MB6604 From: Grygorii Strashko Hence all common pIRQ code is under CONFIG_HAS_PIRQ idefs corresponding RISCV arch pIRQ callbacks become unreachable, so drop them. Signed-off-by: Grygorii Strashko --- xen/arch/riscv/stubs.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 8918cebf35c6..1a8c86cd8da2 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -82,26 +82,6 @@ void smp_send_call_function_mask(const cpumask_t *mask) =20 /* irq.c */ =20 -struct pirq *alloc_pirq_struct(struct domain *d) -{ - BUG_ON("unimplemented"); -} - -int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) -{ - BUG_ON("unimplemented"); -} - -void pirq_guest_unbind(struct domain *d, struct pirq *pirq) -{ - BUG_ON("unimplemented"); -} - -void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) -{ - BUG_ON("unimplemented"); -} - void irq_ack_none(struct irq_desc *desc) { BUG_ON("unimplemented"); --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 10:09:04 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 10:09:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067067.1432043 (Exim 4.92) (envelope-from ) id 1uhmhC-0005yE-D9; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 079e3fc7-c7bb-47b4-91ff-08ddd0e36cd5 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 10:08:55.3603 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WN29ZiglIWazQCgutMmdbt7H5DQQvpJXo49bYPREvmGkxAW3RWigJB5eu41c2tnTE+A+L7EZpnv/ZbsXz0kOmTLBi+0VcLq+l8IA6prngEY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR3PR03MB6604 From: Grygorii Strashko Hence all common pIRQ code is under CONFIG_HAS_PIRQ idefs corresponding PPC arch pIRQ callbacks become unreachable, so drop them. Signed-off-by: Grygorii Strashko --- xen/arch/ppc/stubs.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c index 671e71aa0a60..bdaf474c5cc0 100644 --- a/xen/arch/ppc/stubs.c +++ b/xen/arch/ppc/stubs.c @@ -103,26 +103,6 @@ void smp_send_call_function_mask(const cpumask_t *mask= ) =20 /* irq.c */ =20 -struct pirq *alloc_pirq_struct(struct domain *d) -{ - BUG_ON("unimplemented"); -} - -int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) -{ - BUG_ON("unimplemented"); -} - -void pirq_guest_unbind(struct domain *d, struct pirq *pirq) -{ - BUG_ON("unimplemented"); -} - -void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) -{ - BUG_ON("unimplemented"); -} - void irq_ack_none(struct irq_desc *desc) { BUG_ON("unimplemented"); --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 10:15:20 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 10:15:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067098.1432064 (Exim 4.92) (envelope-from ) id 1uhmnD-0000Uz-B4; Fri, 01 Aug 2025 10:15:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067098.1432064; Fri, 01 Aug 2025 10:15:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhmnD-0000Us-8I; Fri, 01 Aug 2025 10:15:15 +0000 Received: by outflank-mailman (input) for mailman id 1067098; Fri, 01 Aug 2025 10:15:13 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhmnB-0000Um-Ra for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 10:15:13 +0000 Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [2a00:1450:4864:20::332]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 694d6e7e-6ec0-11f0-a320-13f23c93f187; Fri, 01 Aug 2025 12:15:13 +0200 (CEST) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-45617887276so4269715e9.2 for ; Fri, 01 Aug 2025 03:15:13 -0700 (PDT) Received: from [192.168.1.183] (host-195-149-20-212.as13285.net. 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Fri, 01 Aug 2025 03:15:12 -0700 (PDT) Message-ID: <090231b0-6fd9-4ad5-a735-aff7a766ddff@citrix.com> Date: Fri, 1 Aug 2025 11:15:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [XEN][PATCH 0/3] xen/arch: irq: drop unreachable pirq callbacks To: Grygorii Strashko , "xen-devel@lists.xenproject.org" Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Shawn Anastasio , Alistair Francis , Bob Eshleman , Connor Davis , Oleksii Kurochko , Anthony PERARD , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <20250801100852.1260544-1-grygorii_strashko@epam.com> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: <20250801100852.1260544-1-grygorii_strashko@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 01/08/2025 11:08 am, Grygorii Strashko wrote: > From: Grygorii Strashko > > Hence prerequisite patch was merged [1] arch specific pIRQ callback can now > be dropped for arches without pIRQ support as those callback become unreachable. > > [1] commit 341f271cf86f ("xen/evtchn: fully restrict concept of pIRQ for arches with pIRQ support only") > > Grygorii Strashko (3): > xen/arm: irq: drop unreachable pirq callbacks > xen/ppc: irq: drop unreachable pirq callbacks > xen/riscv: irq: drop unreachable pirq callbacks In the individual commit messages, it would be helpful to explicitly say: Since commit 341f271cf86f ("xen/evtchn: fully restrict concept of pIRQ for arches with pIRQ support only"), the $ARCH callbacks ... Having it only in the cover letter is not great for future archaeologists. With something to that effect, Acked-by: Andrew Cooper .  It's always lovely to see diffstats like this. ~Andrew > > xen/arch/arm/irq.c | 29 ----------------------------- > xen/arch/ppc/stubs.c | 20 -------------------- > xen/arch/riscv/stubs.c | 20 -------------------- > 3 files changed, 69 deletions(-) > From xen-devel-bounces@lists.xenproject.org Fri Aug 01 10:48:38 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 10:48:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067123.1432074 (Exim 4.92) (envelope-from ) id 1uhnJJ-0004jn-Q3; Fri, 01 Aug 2025 10:48:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067123.1432074; Fri, 01 Aug 2025 10:48:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhnJJ-0004jg-NX; Fri, 01 Aug 2025 10:48:25 +0000 Received: by outflank-mailman (input) for mailman id 1067123; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV2PR03MB9572.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5f687e44-4b66-4295-36f4-08ddd0e8ee82 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 10:48:20.8648 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: iT/QshlyVvj2kjFILc8mTohm+oxMIVkjdrgKx4qp4ZjKlR+WDryfHohhPrbKke0wucrh9kPGrM512BqhdTiiYrbTb0MTxHQ1zSyElzHDC4g= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR03MB6916 The conversion from a function pointer with the 'noreturn' attribute ('void noreturn (*)(...)') to a function pointer type ('void (*)(...)' causes type incompatibility according to MISRA C Rule 11.1, which forbids conversions between incompatible function pointer types. The violation occurs at the call site: smp_call_function(halt_this_cpu, NULL, 0); where 'halt_this_cpu' with type 'void noreturn (*)(void *)' is passed to 'smp_call_function' expecting function pointer of type 'void (*)(void *)'. The 'noreturn' attribute does not change the function calling convention or parameter handling at runtime, making the conversion safe. Configure ECLAIR to treat implicit conversions that lose the "noreturn" attribute on a function 'void (*)(void*)' as safe. Signed-off-by: Dmytro Prokopchuk --- Changes in v4: - removed words "function pointer" in subject (to fit in 50 chars) - wrote deviation description more generic - adjusted commit message - adjusted of line capacity Link to v3: https://lists.xenproject.org/archives/html/xen-devel/2025-08/msg00009.html --- automation/eclair_analysis/ECLAIR/deviations.ecl | 7 +++++++ docs/misra/deviations.rst | 7 +++++++ docs/misra/rules.rst | 9 +++++---- 3 files changed, 19 insertions(+), 4 deletions(-) diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/= eclair_analysis/ECLAIR/deviations.ecl index 483507e7b9..0e04681c4c 100644 --- a/automation/eclair_analysis/ECLAIR/deviations.ecl +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl @@ -367,6 +367,13 @@ constant expressions are required.\"" } -doc_end =20 +-doc_begin=3D"The conversion from 'void noreturn (*)(void *)' to 'void (*)= (void *)' is safe +because the semantics of the 'noreturn' attribute do not alter the calling= convention or behavior of the resulting code." +-config=3DMC3A2.R11.1,casts+=3D{safe, + "kind(bitcast)&&to(type(pointer(inner(return(builtin(void))&&all_param(1= , pointer(builtin(void)))))))&&from(expr(skip(!syntactic(), + ref(property(noreturn)))))"}=20 +-doc_end + -doc_begin=3D"The conversion from a pointer to an incomplete type to unsig= ned long does not lose any information, provided that the target type has e= nough bits to store it." -config=3DMC3A2.R11.2,casts+=3D{safe, "from(type(any())) diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst index e78179fcb8..38b536dfe4 100644 --- a/docs/misra/deviations.rst +++ b/docs/misra/deviations.rst @@ -342,6 +342,13 @@ Deviations related to MISRA C:2012 Rules: semantics that do not lead to unexpected behaviour. - Tagged as `safe` for ECLAIR. =20 + * - R11.1 + - The conversion from 'void noreturn (*)(...)' to 'void (*)(...)' is = safe + because the semantics of the 'noreturn' attribute do not alter the = calling + convention or behavior of the resulting code, parameters handling r= emain + consistent. + - Tagged as `safe` for ECLAIR. + * - R11.2 - The conversion from a pointer to an incomplete type to unsigned lon= g does not lose any information, provided that the target type has en= ough diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst index 3e014a6298..2b6f30e56d 100644 --- a/docs/misra/rules.rst +++ b/docs/misra/rules.rst @@ -400,11 +400,12 @@ maintainers if you want to suggest a change. =20 * - `Rule 11.1 `_ - Required - - Conversions shall not be performed between a pointer to a - function and any other type + - Conversions shall not be performed between a pointer to a function + and any other type - All conversions to integer types are permitted if the destination - type has enough bits to hold the entire value. Conversions to - bool and void* are permitted. + type has enough bits to hold the entire value. Conversions to bool + and void* are permitted. Conversions from 'void noreturn (*)(...)' + to 'void (*)(...)' are permitted. =20 * - `Rule 11.2 `_ - Required --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 10:54:15 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 10:54:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067130.1432084 (Exim 4.92) (envelope-from ) id 1uhnOt-0006L5-D9; Fri, 01 Aug 2025 10:54:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067130.1432084; Fri, 01 Aug 2025 10:54:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhnOt-0006Ky-9y; Fri, 01 Aug 2025 10:54:11 +0000 Received: by outflank-mailman (input) for mailman id 1067130; Fri, 01 Aug 2025 10:54:09 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhnOr-0006Ks-Rd for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 10:54:09 +0000 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [2a00:1450:4864:20::436]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id d0f6045f-6ec5-11f0-b896-0df219b8e170; Fri, 01 Aug 2025 12:53:54 +0200 (CEST) Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3b792b0b829so657103f8f.3 for ; Fri, 01 Aug 2025 03:53:54 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Fri, 01 Aug 2025 03:53:53 -0700 (PDT) Message-ID: <4475f575-91df-4f9d-ad05-41a4864baa11@suse.com> Date: Fri, 1 Aug 2025 12:53:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4] misra: allow discarding 'noreturn' during conversions To: Dmytro Prokopchuk1 Cc: Nicola Vetrini , Doug Goldstein , Stefano Stabellini , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , "xen-devel@lists.xenproject.org" References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 01.08.2025 12:48, Dmytro Prokopchuk1 wrote: > The conversion from a function pointer with the 'noreturn' attribute > ('void noreturn (*)(...)') to a function pointer type ('void (*)(...)' > causes type incompatibility according to MISRA C Rule 11.1, which > forbids conversions between incompatible function pointer types. This wider deviation ... > The violation occurs at the call site: > smp_call_function(halt_this_cpu, NULL, 0); > where 'halt_this_cpu' with type 'void noreturn (*)(void *)' is passed to > 'smp_call_function' expecting function pointer of type 'void (*)(void *)'. > > The 'noreturn' attribute does not change the function calling convention > or parameter handling at runtime, making the conversion safe. > > Configure ECLAIR to treat implicit conversions that lose the "noreturn" > attribute on a function 'void (*)(void*)' as safe. ... wants connecting to this more narrow Eclair configuration. That's what I meant when I said "description also suitably adjusted". For example, the last sentence above could start "For now, configure Eclair to just treat ...". Can adjust when committing, assuming an ack for the .ecl change appears. > Signed-off-by: Dmytro Prokopchuk Acked-by: Jan Beulich # docs From xen-devel-bounces@lists.xenproject.org Fri Aug 01 10:58:48 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 10:58:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067140.1432094 (Exim 4.92) (envelope-from ) id 1uhnTL-0006xm-2A; Fri, 01 Aug 2025 10:58:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067140.1432094; Fri, 01 Aug 2025 10:58:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhnTK-0006xf-Uw; Fri, 01 Aug 2025 10:58:46 +0000 Received: by outflank-mailman (input) for mailman id 1067140; Fri, 01 Aug 2025 10:58:45 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhnTJ-0006xZ-Cy for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 10:58:45 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7b506f5b-6ec6-11f0-b896-0df219b8e170; Fri, 01 Aug 2025 12:58:40 +0200 (CEST) Received: from support.bugseng.com (support.bugseng.com [162.55.131.47]) (Authenticated sender: nicola) by support.bugseng.com (Postfix) with ESMTPA id DC3C14EE3C02; Fri, 1 Aug 2025 12:58:38 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7b506f5b-6ec6-11f0-b896-0df219b8e170 Authentication-Results: bugseng.com; arc=none smtp.remote-ip=162.55.131.47 ARC-Seal: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; cv=none; t=1754045919; b=ll4kwhdjSNCe6bybhotPTKvFBtb/tcyaQiSfiSuE6dWU3WsgIpI4gimSJGUYngaNi4dD grgOIZnR968aaUQGTSt5/7PbhPpJEh9rojoTmSiEp9880Hk+OVx56YVecgtEZEQmZXy23 W1gxxNX4qhWDVV1l0hfUlUnLxKZjF1o5hjG9aiDc4NMMopcBXv0ctmZT7ZZNpfLK3J/7t /nQILbm4+RMJdoDZ5tNyFSxjJD/JDronqsjK2Tg7mPuMdSumpamAR+DlIzpWgQVzPwMpy L2fKMQ8JgbiZJXmC4G6eU3bdGAGeDdufORJ9LDPfj3ucx2y1j6kt8oXW+mtunYoP7n4n9 3sW+gwT+RuHTk2Sv8wMZ1KiytSYt+sUjaYcr5D1lQmpMYL+0/jt8X3nyUB9cXWcptahcL 6ZHNxZCbPAlW6u4WCqwXaRHYUmh6RkgE55qfSOX2KU3Wj4G2PjwEECRFOY+MnBaTm5Yit ii0lBSMJjbCFPlH1E/bnRfiicCJF170zM8KLd2GFeOOqoKiL4wfP5dyU1eJbTbVLCPssk S/DG8cDmJr7rhh3fn83VxUnYujE0xcHIkjayqKr6pqSZzf6afjU483o5mR4NkppnIKnDm advmIgsNVXTfq7KVnDQqY0ME6ShM2sIOG13zaffPmatB5tbQuA0TpNKl3gyFVo8= ARC-Message-Signature: i=1; d=bugseng.com; s=openarc; a=rsa-sha256; c=relaxed/relaxed; t=1754045919; h=DKIM-Signature:MIME-Version:Date:From:To:Cc:Subject:In-Reply-To: References:Message-ID:X-Sender:Organization:Content-Type: Content-Transfer-Encoding; bh=l9zcpOkubj5IU7vpaTeU1fz2oeyMx4q6+I0OukzjbtU=; b=boU6akOiD27uUM/26UfM7GQbjcJFhX5swxNrxiAbp/8zeqCBcdvuz7ig0Blpt/jTVQes 6EUi+Kx0wOkGUPrV/rjQQuOnwqo2zhOCDUyH1kvcewoBqekjiZhNWzslFvL532JNG4VaQ fvtnO4w8WHUpjW+pjGs8YHYXY2xDukPtEk8L0oXqIXPqLjEF5bKc9jwDNW2up1wBKhpzw d9Gfor5s4zOWwgs0Fw/93uYZxk/1LVtVhkzrHO673aDWZt8H9gZ/tUnDpbVIjpHOlZ4GE iST+GCOGHhHaa8zwrUzWuAutLFt0AUb4Ma7Tm5Lvd3h5CZpTLWy72VTaKRzkKG/ssnT/I DC0h2X5lnzI/yd53F8EszRY6Ehb5qU5KoOOupFoQgAnUfrxoyTh57rQZTtKyNJZhowv13 gJIzLLfXfXSCzjZrXFJuJDvEGIJsmN8iDE/7XAxsbM3B3NjwvKq8pabyTEbP4n3+FeWcG ls4SESQ55zbJgSlEWznHKghqQQMJvisH380mhJTYTIMSVVLi03qOHZsImRNfqLA2K9M4X votkvruasNVDIaYLyt7ZNNSvrPc9by4Kw6oel1sIksM5KyhfzVnOiv0zxuO7F0AbZyI1Q r2rWedQtzZsYADbTDlQ2+30+uzsghOaju6qchi+jHYdf8mHa7PyCLXL28AGQmQA= ARC-Authentication-Results: i=1; bugseng.com; arc=none smtp.remote-ip=162.55.131.47 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=bugseng.com; s=mail; t=1754045919; bh=1NgS/HPFX/e6Pq8rJJ74P0lYqDY2Vje7bDk7P3Eb7LY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=rfXZF9qhunYVsgapGlwRLCXY70YEsUZ6DveYLshT/QfL+vBRvNaThaJSzj8QcNZSj cVkAMXk0UW1l9DrPIUcXtk9y+tLWsb4nnhkHtKiOe6V1LZ27yphWOMSUXvla5r7ozz EvhNAWmYOZ6YUiTyWJZQcXdteBGyx0ezAJpoJH1zhQT/vjMmleaIZbB3miWjpoGsN1 MQSWpNGvevNg1DNiOyYg7WNcz+DgTfqw1ngpFh+26HYVsIdRGjqt8CdYWk/4AjZz9n uTW1NBuEFAoHNEBH0PYpp/s7zWYKCtRvsRYkNAd6UmaHagKkZdBw7asyIIDctNl9on QCq/Cj3hRfDMw== MIME-Version: 1.0 Date: Fri, 01 Aug 2025 12:58:38 +0200 From: Nicola Vetrini To: Jan Beulich Cc: Dmytro Prokopchuk1 , Doug Goldstein , Stefano Stabellini , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org Subject: Re: [PATCH v4] misra: allow discarding 'noreturn' during conversions In-Reply-To: <4475f575-91df-4f9d-ad05-41a4864baa11@suse.com> References: <4475f575-91df-4f9d-ad05-41a4864baa11@suse.com> Message-ID: X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit On 2025-08-01 12:53, Jan Beulich wrote: > On 01.08.2025 12:48, Dmytro Prokopchuk1 wrote: >> The conversion from a function pointer with the 'noreturn' attribute >> ('void noreturn (*)(...)') to a function pointer type ('void (*)(...)' >> causes type incompatibility according to MISRA C Rule 11.1, which >> forbids conversions between incompatible function pointer types. > > This wider deviation ... > >> The violation occurs at the call site: >> smp_call_function(halt_this_cpu, NULL, 0); >> where 'halt_this_cpu' with type 'void noreturn (*)(void *)' is passed >> to >> 'smp_call_function' expecting function pointer of type 'void (*)(void >> *)'. >> >> The 'noreturn' attribute does not change the function calling >> convention >> or parameter handling at runtime, making the conversion safe. >> >> Configure ECLAIR to treat implicit conversions that lose the >> "noreturn" >> attribute on a function 'void (*)(void*)' as safe. > > ... wants connecting to this more narrow Eclair configuration. That's > what > I meant when I said "description also suitably adjusted". For example, > the > last sentence above could start "For now, configure Eclair to just > treat > ...". Can adjust when committing, assuming an ack for the .ecl change > appears. > >> Signed-off-by: Dmytro Prokopchuk > > Acked-by: Jan Beulich # docs Feels weird to review my own ecl honestly, but for the sake of the patch I verified that it is indeed what I wrote, so Reviewed-by: Nicola Vetrini # ECLAIR -- Nicola Vetrini, B.Sc. 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Fri, 01 Aug 2025 04:25:09 -0700 (PDT) Message-ID: Date: Fri, 1 Aug 2025 12:25:08 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-GB To: xen-devel From: Andrew Cooper Subject: Console vs serial Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hello, There's a long-standing irritation in Xen, whereby printk()'s which occur prior to console_init_preirq() get half-lost. They end up in the console ring, and hence are available via `xl dmesg`, but they're missing from serial console. e.g. these 4 lines don't escape     (XEN) Enabling lockdown mode because Secure Boot is enabled     (XEN) Lockdown mode is enabled     (XEN) Ignoring cmdline option 'hap_2mb' in lockdown mode     (XEN) Ignoring cmdline option 'hap_1gb' in lockdown mode      __  __            _  _    _  ___   ____      \ \/ /___ _ __   | || |  / |/ _ \ |___ \ This is from a testcase failure I've just debugged, but the issue is not specific to secureboot.  More generally, any diagnostic from cmdline parsing ends up in this state. For PVShim, we did a gross hack to assume the PV console is usable right from the outset, but all other console configurations don't start working until the cmdline has been parsed. Is anything stopping us from feeding the current contents of the console ring into serial in console_init_preirq()? ~Andrew From xen-devel-bounces@lists.xenproject.org Fri Aug 01 11:45:18 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 11:45:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067196.1432124 (Exim 4.92) (envelope-from ) id 1uhoCG-000616-PB; Fri, 01 Aug 2025 11:45:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067196.1432124; Fri, 01 Aug 2025 11:45:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhoCG-00060z-MN; Fri, 01 Aug 2025 11:45:12 +0000 Received: by outflank-mailman (input) for mailman id 1067196; Fri, 01 Aug 2025 11:45:11 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhoCF-00060t-9x for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 11:45:11 +0000 Received: from mail-oi1-x22e.google.com (mail-oi1-x22e.google.com [2607:f8b0:4864:20::22e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id f988a163-6ecc-11f0-b896-0df219b8e170; Fri, 01 Aug 2025 13:45:09 +0200 (CEST) Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-41b4ebb15e2so978854b6e.3 for ; Fri, 01 Aug 2025 04:45:09 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f988a163-6ecc-11f0-b896-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1754048708; x=1754653508; darn=lists.xenproject.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=1OlFcRTGjo+XBPKGhcZipxmDk8NlzuRt/DeJY9bvaKw=; b=lV1tGSscx/L9ad2Eb1otJGCUJjaRjpEnPqWKr5Oi6ErXWXxwQYcGE4lE4TQKLGN9/p KsGT+Bmh9P6RLFPHnt5HUoGoK4VQ9IAb+rMDX2NMLrvNEZYyIZRcI16vwguQEoMNH1/C h0tU4eSC9CuaBiUiv7EPscZfyRe/8kXQJN174= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754048708; x=1754653508; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1OlFcRTGjo+XBPKGhcZipxmDk8NlzuRt/DeJY9bvaKw=; b=UdqFLhl3vf2/dmT7z4Fqr7k4vfesI5Ux46JTzpHFk2aDMgCp8RCQBwS12Yh9VZrguC FVpMNjifNSZ2PknBhuvqL2sG93oNl9X6VMJlV4jJAcluhJcpRzwkezHPlW9VKKuqCy5j V7KVDnh0PKUvlR2YRIU3Cp3bIwzNKJqpJ3HnOmB/SvzVavyofNTlDTWyFRic4S3hy2qy YE/78SPZavl17urAMiRBe56eIV9R0V+nGyHmmQA8hmzl+/lUJplXpyoIVT6lK1EvgQ0n kuv01WqP/DsyQRy+Mowt57liCXoQNCnQwgVsYFxs9vGgEj4Px+BHGVm2u6XK9pPcBxxH 7fCg== X-Gm-Message-State: AOJu0YwukYM38CRRBmGyoDOt6xDSrOr/Qz2kEql1b5vI27rAImALDV+B Pb+OW0yLh7+KPJ+vgoAvAbw7xL5fpHjjVU56v7z4tmD7J3HcjPLIRjWRrtYO7AcMnzmqyCmY2vx 7Mrs7wC52ph+5nqKt7dXM6VfZZcYm5Mekl5D0DOzZ6Q== X-Gm-Gg: ASbGnctqXl2+CHUJW8wOcWcCebpYBp+sJuEPLqWWnm/zeUcoRCUpOrRvRRq1PmWH/Md rxlcznu5ZaOGXrn69D/cAg0ov3sDwXaTBAAwmhftPAAePoszEaZD201l9MlxQAfJ70gSRYp6EhF EeGH70LssCdkPHcH709QwAmD/kZ2Q2FrOqVj/laORgUMjstKQqhblZnT4mp3s09oQnSvoPCd8/B 2g0qx8= X-Google-Smtp-Source: AGHT+IFtF4y0tnfNuIHefeNb52zUFGW2wkiQ9ClS+SpSJ1xKaLd07vJyTMsmfLtt3DHf0+HHevJAfxPJWnNfn6tAcoY= X-Received: by 2002:a05:6808:6702:b0:406:45ae:b0 with SMTP id 5614622812f47-4319c1ef726mr7322580b6e.35.1754048707922; Fri, 01 Aug 2025 04:45:07 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Frediano Ziglio Date: Fri, 1 Aug 2025 12:44:57 +0100 X-Gm-Features: Ac12FXw4kXbLuRe8A2LolUx6iP80Z629ue7VAKmsl9g1-T6ipHV4GHC3pNTBY80 Message-ID: Subject: Re: Console vs serial To: Andrew Cooper Cc: xen-devel Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Aug 1, 2025 at 12:25=E2=80=AFPM Andrew Cooper wrote: > > Hello, > > There's a long-standing irritation in Xen, whereby printk()'s which > occur prior to console_init_preirq() get half-lost. > > They end up in the console ring, and hence are available via `xl dmesg`, > but they're missing from serial console. > > e.g. these 4 lines don't escape > > (XEN) Enabling lockdown mode because Secure Boot is enabled > (XEN) Lockdown mode is enabled > (XEN) Ignoring cmdline option 'hap_2mb' in lockdown mode > (XEN) Ignoring cmdline option 'hap_1gb' in lockdown mode > __ __ _ _ _ ___ ____ > \ \/ /___ _ __ | || | / |/ _ \ |___ \ > > > This is from a testcase failure I've just debugged, but the issue is not > specific to secureboot. More generally, any diagnostic from cmdline > parsing ends up in this state. > > For PVShim, we did a gross hack to assume the PV console is usable right > from the outset, but all other console configurations don't start > working until the cmdline has been parsed. > > Is anything stopping us from feeding the current contents of the console > ring into serial in console_init_preirq()? > > ~Andrew > I don't think there's a problem replaying the console logs into the serial once the serial is set up. It will slow down the boot maybe but beside that it should be fine. Frediano From xen-devel-bounces@lists.xenproject.org Fri Aug 01 12:55:54 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 12:55:54 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067240.1432138 (Exim 4.92) (envelope-from ) id 1uhpIU-0006Ce-RD; Fri, 01 Aug 2025 12:55:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067240.1432138; Fri, 01 Aug 2025 12:55:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhpIU-0006CX-OP; Fri, 01 Aug 2025 12:55:42 +0000 Received: by outflank-mailman (input) for mailman id 1067240; Fri, 01 Aug 2025 12:55:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhpIU-0006CR-5q for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 12:55:42 +0000 Received: from dibed.net-space.pl (dibed.net-space.pl [84.10.22.86]) by se1-gles-sth1.inumbo.com (Halon) with SMTP id d355f362-6ed6-11f0-a320-13f23c93f187; Fri, 01 Aug 2025 14:55:39 +0200 (CEST) Received: from router-fw.i.net-space.pl ([192.168.52.1]:48616 "EHLO tomti.i.net-space.pl") by router-fw-old.i.net-space.pl with ESMTP id S998191AblHAMzh (ORCPT ); Fri, 1 Aug 2025 14:55:37 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d355f362-6ed6-11f0-a320-13f23c93f187 X-Comment: RFC 2476 MSA function at dibed.net-space.pl logged sender identity as: dkiper Date: Fri, 1 Aug 2025 14:55:36 +0200 From: Daniel Kiper To: Aaron Rainbolt Cc: grub-devel@gnu.org, xen-devel@lists.xenproject.org Subject: Re: [RESEND PATCH v3 1/1] kern/xen: Add Xen command line parsing Message-ID: <20250801125536.mc2sjrdyikljzea6@tomti.i.net-space.pl> References: <20250725153012.1dd46644@kf-m2g5> <20250725153112.4ea25243@kf-m2g5> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250725153112.4ea25243@kf-m2g5> User-Agent: NeoMutt/20170113 (1.7.2) On Fri, Jul 25, 2025 at 03:31:12PM -0500, Aaron Rainbolt wrote: > Xen traditionally allows customizing guest behavior by passing arguments > to the VM kernel via the kernel command line. This is no longer possible > when using GRUB with Xen, as the kernel command line is decided by the > GRUB configuration file within the guest, not data passed to the guest > by Xen. > > To work around this limitation, enable GRUB to parse a command line > passed to it by Xen, and expose data from the command line to the GRUB > configuration as environment variables. These variables can be used in > the GRUB configuration for any desired purpose, such as extending the > kernel command line passed to the guest. The command line format is > inspired by the Linux kernel's command line format. > > To reduce the risk of misuse, abuse, or accidents in production, the > command line will only be parsed if it consists entirely of 7-bit ASCII > characters, only alphabetical characters and underscores are permitted > in variable names, and all variable names must start with the string > "xen_grub_env_". This also allows room for expanding the command line > arguments accepted by GRUB in the future, should other arguments end up > becoming desirable in the future. > > Signed-off-by: Aaron Rainbolt > --- > docs/grub.texi | 50 +++++ > grub-core/Makefile.core.def | 2 + > grub-core/kern/i386/xen/pvh.c | 14 ++ > grub-core/kern/main.c | 12 ++ > grub-core/kern/xen/cmdline.c | 343 ++++++++++++++++++++++++++++++++++ > include/grub/xen.h | 2 + > 6 files changed, 423 insertions(+) > create mode 100644 grub-core/kern/xen/cmdline.c > > diff --git a/docs/grub.texi b/docs/grub.texi > index 34b3484..ce82483 100644 > --- a/docs/grub.texi > +++ b/docs/grub.texi > @@ -3271,6 +3271,7 @@ GRUB. Others may be used freely in GRUB configuration files. > @menu > * Special environment variables:: > * Environment block:: > +* Passing environment variables through Xen:: > @end menu > > > @@ -3871,6 +3872,55 @@ using BIOS or EFI functions (no ATA, USB or IEEE1275). > @command{grub-mkconfig} uses this facility to implement > @samp{GRUB_SAVEDEFAULT} (@pxref{Simple configuration}). > > +@node Passing environment variables through Xen > +@section Passing environment variables through Xen > + > +If you are using a GRUB image as the kernel for a PV or PVH Xen virtual > +machine, you can pass environment variables from Xen's dom0 to the VM through > +the Xen-provided kernel command line. When combined with a properly configured > +guest, this can be used to customize the guest's behavior on bootup via the > +VM's Xen configuration file. > + > +GRUB will parse the kernel command line passed to it by Xen during bootup. > +The command line will be split into space-delimited words. Single and > +double quotes may be used to quote words or portions of words that contain > +spaces. Arbitrary characters may be backslash-escaped to make them a literal > +component of a word rather than being parsed as quotes or word separators. The > +command line must consist entirely of printable 7-bit ASCII characters and > +spaces. If a non-printing ASCII character is found anywhere in the command > +line, the entire command line will be ignored by GRUB. > + > +Each word should be a variable assignment in the format ``variable'' or > +``variable=value''. Variable names must contain only the characters A-Z, a-z, > +and underscore (``_''). Variable names must begin with the string > +``xen_grub_env_''. Variable values can contain arbitrary printable 7-bit > +ASCII characters and space. If any variable contains an illegal name, that > +variable will be ignored. > + > +If a variable name and value are both specified, the variable will be set to > +the specified value. If only a variable name is specified, the variable's > +value will be set to ``1''. > + > +The following is a simple example of how to use this functionality to append > +arbitrary variables to a guest's kernel command line: > + > +@example > +# In the Xen configuration file for the guest > +name = "linux_vm" > +type = "pvh" > +kernel = "/path/to/grub-i386-xen_pvh.bin" > +extra = "xen_grub_env_kernelappend='loglevel=3'" s/kernelappend/kernel_append/ or maybe even s/kernelappend/linux_append/ to make it clear it is appended to the "linux" command line... > +memory = 1024 > +disk = [ "file:/srv/vms/linux_vm.img,sda,w" ] > + > +# In the guest's GRUB configuration file > +menuentry "Linux VM with dom0-specified kernel parameters" @{ > + search --set=root --label linux_vm --hint hd0,msdos1 > + linux /boot/vmlinuz root=LABEL=linux_vm $@{xen_grub_env_kernelappend@} Ditto... > + initrd /boot/initrd.img > +@} > +@end example > + > @node Modules > @chapter Modules > > diff --git a/grub-core/Makefile.core.def b/grub-core/Makefile.core.def > index b3f7119..df0f266 100644 > --- a/grub-core/Makefile.core.def > +++ b/grub-core/Makefile.core.def > @@ -248,6 +248,7 @@ kernel = { > xen = term/xen/console.c; > xen = disk/xen/xendisk.c; > xen = commands/boot.c; > + xen = kern/xen/cmdline.c; > > i386_xen_pvh = commands/boot.c; > i386_xen_pvh = disk/xen/xendisk.c; > @@ -255,6 +256,7 @@ kernel = { > i386_xen_pvh = kern/i386/xen/tsc.c; > i386_xen_pvh = kern/i386/xen/pvh.c; > i386_xen_pvh = kern/xen/init.c; > + i386_xen_pvh = kern/xen/cmdline.c; > i386_xen_pvh = term/xen/console.c; > > ia64_efi = kern/ia64/efi/startup.S; > diff --git a/grub-core/kern/i386/xen/pvh.c b/grub-core/kern/i386/xen/pvh.c > index 91fbca8..12df2d8 100644 > --- a/grub-core/kern/i386/xen/pvh.c > +++ b/grub-core/kern/i386/xen/pvh.c > @@ -321,6 +321,8 @@ void > grub_xen_setup_pvh (void) > { > grub_addr_t par; > + const char *xen_cmdline; > + int i; > > grub_xen_cpuid_base (); > grub_xen_setup_hypercall_page (); > @@ -352,6 +354,18 @@ grub_xen_setup_pvh (void) > grub_xen_mm_init_regions (); > > grub_rsdp_addr = pvh_start_info->rsdp_paddr; > + > + xen_cmdline = (const char *) pvh_start_info->cmdline_paddr; > + for (i = 0; i < MAX_GUEST_CMDLINE; i++) Oh, MAX_GUEST_CMDLINE is a too generic. May I ask you to rename it to GRUB_XEN_MAX_GUEST_CMDLINE? This should be done in separate patch preceding this one. > + { > + if (xen_cmdline[i] == '\0') I cannot see much sense in this check. Please look below... > + { > + grub_strncpy ((char *) grub_xen_start_page_addr->cmd_line, > + (char *) pvh_start_info->cmdline_paddr, s/char */const char */ Is it always guaranteed that pvh_start_info->cmdline_paddr have MAX_GUEST_CMDLINE size? If yes then... grub_memset ((void *) pvh_start_info->cmdline_paddr, 0, MAX_GUEST_CMDLINE); grub_strncpy ((char *) grub_xen_start_page_addr->cmd_line, (const char *) pvh_start_info->cmdline_paddr, MAX_GUEST_CMDLINE - 1); ... and you are done... > + MAX_GUEST_CMDLINE); > + break; > + } > + } > } > > grub_err_t > diff --git a/grub-core/kern/main.c b/grub-core/kern/main.c > index 143a232..b4377d3 100644 > --- a/grub-core/kern/main.c > +++ b/grub-core/kern/main.c > @@ -37,6 +37,10 @@ > #include > #endif > > +#if defined (GRUB_MACHINE_XEN) || defined (GRUB_MACHINE_XEN_PVH) > +#include > +#endif > + > static bool cli_disabled = false; > static bool cli_need_auth = false; > > @@ -351,6 +355,14 @@ grub_main (void) > grub_env_export ("root"); > grub_env_export ("prefix"); > > + /* > + * Parse command line parameters from Xen and export them as environment > + * variables > + */ > +#if defined (GRUB_MACHINE_XEN) || defined (GRUB_MACHINE_XEN_PVH) > + grub_parse_xen_cmdline (); Please move this call to the grub-core/kern/xen/init.c:grub_machine_init(). > +#endif > + > /* Reclaim space used for modules. */ > reclaim_module_space (); > > diff --git a/grub-core/kern/xen/cmdline.c b/grub-core/kern/xen/cmdline.c > new file mode 100644 > index 0000000..03dd88f > --- /dev/null > +++ b/grub-core/kern/xen/cmdline.c > @@ -0,0 +1,343 @@ > +/* > + * GRUB -- GRand Unified Bootloader > + * Copyright (C) 2025 Free Software Foundation, Inc. > + * > + * GRUB is free software: you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation, either version 3 of the License, or > + * (at your option) any later version. > + * > + * GRUB is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with GRUB. If not, see . > + */ > + > +#include > +#include > +#include > +#include > + > +enum parse_flags > +{ > + PARSER_HIT_BACKSLASH = 0x1, > + PARSER_IN_SINGLE_QUOTES = 0x2, > + PARSER_IN_DOUBLE_QUOTES = 0x4, > +}; typedef parse_flags parse_flags_t; ... and use parse_flags_t instead below... And probably this should be a local variable... > + > +#define PARSER_BASE_WORD_LEN 16 This constant begs for a few words of comment... > +static grub_size_t word_list_len; > +static char **word_list; > +static grub_size_t current_word_len; > +static grub_size_t current_word_pos; > +static char *current_word; > +static char current_char; I have a feeling that most if not all of this variables should be local in a given function... > +static bool > +append_char_to_word (bool allow_null) > +{ > + /* > + * Fail if the current char is outside of the range 0x20 to 0x7E. If > + * allow_null is true, make an exception for 0x00. This is a safeguard Could you elaborate here when allow_null == true is useful? > + * against likely-invalid data. > + */ > + if ( (!(current_char >= 0x20) || !(current_char <= 0x7E) ) grub_isprint()? > + && (current_char != '\0' || allow_null == false)) I would drop redundant spaces between "(" and ")" and move "&&" to the end of first line of "if". > + return false; > + > + if (current_word_pos == current_word_len) > + { > + current_word_len *= 2; You can do this in the argument of the function below... > + current_word = grub_realloc (current_word, current_word_len); > + if (current_word == NULL) > + { > + current_word_len /= 2; > + return false; > + } > + } > + > + current_word[current_word_pos] = current_char; > + current_word_pos++; Again, you can do this operation in the "[]" above... > + return true; > +} > + > +static bool > +append_word_to_list (void) > +{ > + /* No-op on empty words. */ > + if (current_word_pos == 0) This should be probably an argument for the function... > + return true; > + > + current_char = '\0'; > + if (append_char_to_word (true) == false) > + { > + grub_error (GRUB_ERR_BUG, > + "couldn't append null terminator to word during Xen cmdline parsing"); > + grub_print_error (); > + grub_exit (); > + } > + > + current_word_len = grub_strlen (current_word) + 1; > + current_word = grub_realloc (current_word, current_word_len); > + if (current_word == NULL) > + return false; > + word_list_len++; Again this, OK ++word_list_len to be precise, can be done in a function argument below... > + word_list = grub_realloc (word_list, word_list_len * sizeof (char *)); > + if (word_list == NULL) > + return false; > + word_list[word_list_len - 1] = current_word; > + > + current_word_len = PARSER_BASE_WORD_LEN; > + current_word_pos = 0; > + current_word = grub_malloc (current_word_len); > + if (current_word == NULL) > + return false; > + > + return true; > +} > + > +static bool > +check_key_is_safe (char *key, grub_size_t len) > +{ > + grub_size_t i; > + > + for (i = 0; i < len; i++) > + { > + /* > + * Ensure only a-z, A-Z, and _ are allowed. > + */ > + if (! ( (key[i] >= 'A' && key[i] <= 'Z') > + || (key[i] >= 'a' && key[i] <= 'z') You have whole family of grub_isalpha() functions. Could not use them here and there? > + || (key[i] == '_') ) ) > + return false; > + } > + return true; > +} > + > +void > +grub_parse_xen_cmdline (void) > +{ > + const char *cmdline = (const char *) grub_xen_start_page_addr->cmd_line; > + grub_size_t cmdline_len; > + bool cmdline_valid = false; > + char **param_keys = NULL; > + char **param_vals = NULL; > + grub_size_t param_dict_len = 0; > + grub_size_t param_dict_pos = 0; > + enum parse_flags parse_flags = 0; > + grub_size_t i = 0; > + > + /* > + * The following algorithm is used to parse the Xen command line: > + * > + * - The command line is split into space-separated words. > + * - Single and double quotes may be used to suppress the splitting > + * behavior of spaces. > + * - Double quotes are appended to the current word verbatim if they > + * appear within a single-quoted string portion, and vice versa. > + * - Backslashes may be used to cause the next character to be > + * appended to the current word verbatim. This is only useful when > + * used to escape quotes, spaces, and backslashes, but for simplicity > + * we allow backslash-escaping anything. > + * - After splitting the command line into words, each word is checked to > + * see if it contains an equals sign. > + * - If it does, it is split on the equals sign into a key-value pair. The > + * key is then treated as an variable name, and the value is treated as > + * the variable's value. > + * - If it does not, the entire word is treated as a variable name. The > + * variable's value is implicitly considered to be `1`. > + * - All variables detected on the command line are checked to see if their > + * names begin with the string `xen_grub_env_`. Variables that do not pass > + * this check are discarded, variables that do pass this check are > + * exported so they are available to the GRUB configuration. I think not all from this valuable comment landed in the documentation. Please fix it... > + */ > + > + current_word_len = PARSER_BASE_WORD_LEN; > + current_word = grub_malloc (current_word_len); > + if (current_word == NULL) > + goto cleanup; > + > + for (i = 0; i < MAX_GUEST_CMDLINE; i++) > + { > + if (cmdline[i] == '\0') > + { > + cmdline_valid = true; > + break; > + } > + } > + > + if (cmdline_valid == false) > + { > + grub_error (GRUB_ERR_BAD_ARGUMENT, > + "Command line from Xen is not NUL-terminated"); GRUB errors usually start with lowercase... > + grub_print_error (); > + goto cleanup; > + } > + > + cmdline_len = grub_strlen (cmdline); > + for (i = 0; i < cmdline_len; i++) > + { > + current_char = cmdline[i]; > + > + /* > + * If the previous character was a backslash, append the current > + * character to the word verbatim > + */ > + if (parse_flags & PARSER_HIT_BACKSLASH) s/parse_flags/parser_state/ > + { > + parse_flags &= ~PARSER_HIT_BACKSLASH; > + if (append_char_to_word (false) == false) > + goto cleanup; > + continue; > + } > + > + switch (current_char) > + { > + case '\\': > + /* Backslashes escape arbitrary characters. */ > + parse_flags |= PARSER_HIT_BACKSLASH; > + continue; > + > + case '\'': > + /* > + * Single quotes suppress word splitting and double quoting until > + * the next single quote is encountered. > + */ > + if (parse_flags & PARSER_IN_DOUBLE_QUOTES) > + { > + if (append_char_to_word (false) == false) > + goto cleanup; > + continue; > + } > + > + parse_flags ^= PARSER_IN_SINGLE_QUOTES; > + continue; > + > + case '"': > + /* > + * Double quotes suppress word splitting and single quoting until > + * the next double quote is encountered. > + */ > + if (parse_flags & PARSER_IN_SINGLE_QUOTES) > + { > + if (append_char_to_word (false) == false) > + goto cleanup; > + continue; > + } > + > + parse_flags ^= PARSER_IN_DOUBLE_QUOTES; > + continue; > + > + case ' ': > + /* Spaces separate words in the command line from each other. */ > + if (parse_flags & PARSER_IN_SINGLE_QUOTES > + || parse_flags & PARSER_IN_DOUBLE_QUOTES) I prefer "||" and "&&" at the end of the lines... > + { > + if (append_char_to_word (false) == false) > + goto cleanup; > + continue; > + } > + > + if (append_word_to_list () == false) This shows nicely that the function misses arguments... > + goto cleanup; > + continue; > + } > + > + if (append_char_to_word (false) == false) Ditto... > + goto cleanup; > + } > + > + if (append_word_to_list () == false) Ditto... > + goto cleanup; > + > + param_keys = grub_malloc (word_list_len * sizeof (char *)); > + if (param_keys == NULL) > + goto cleanup; > + param_vals = grub_malloc (word_list_len * sizeof (char *)); > + if (param_vals == NULL) > + goto cleanup; > + > + for (i = 0; i < word_list_len; i++) > + { > + char *current_word_eq_ptr; > + > + current_word = word_list[i]; > + current_word_len = grub_strlen (current_word) + 1; > + current_word_eq_ptr = grub_strchr (current_word, '='); > + > + if (current_word_eq_ptr) current_word_eq_ptr != NULL > + { > + grub_size_t eq_idx = (grub_size_t)(current_word_eq_ptr - current_word); Missing space after "(grub_size_t)"... > + grub_size_t post_eq_len = current_word_len - (eq_idx); You can drop "()" from eq_idx > + > + if (check_key_is_safe (current_word, eq_idx)) check_key_is_safe() == true s/check_key_is_safe/is_key_safe/ > + { > + param_dict_pos = param_dict_len; > + param_dict_len++; > + param_keys[param_dict_pos] = grub_malloc (eq_idx + 1); > + if (param_keys == NULL) > + goto cleanup; > + param_vals[param_dict_pos] = grub_malloc (post_eq_len + 1); > + if (param_vals == NULL) > + goto cleanup; > + > + grub_strncpy (param_keys[param_dict_pos], current_word, > + eq_idx); Please do not wrap line here... > + grub_strncpy (param_vals[param_dict_pos], > + current_word + eq_idx + 1, post_eq_len); Please remember that grub_strncpy() may return non-NUL terminated strings... You should check this everywhere... > + param_keys[param_dict_pos][eq_idx] = '\0'; > + param_vals[param_dict_pos][post_eq_len] = '\0'; > + } > + } > + else > + { > + if (check_key_is_safe (current_word, current_word_len - 1)) check_key_is_safe() == true > + { > + param_dict_pos = param_dict_len; > + param_dict_len++; > + param_keys[param_dict_pos] = grub_malloc (current_word_len); > + if (param_keys == NULL) > + goto cleanup; > + param_vals[param_dict_pos] = grub_malloc (2); > + if (param_vals == NULL) > + goto cleanup; > + > + grub_strncpy (param_keys[param_dict_pos], current_word, > + current_word_len); > + grub_strcpy (param_vals[param_dict_pos], "1"); > + } > + } > + } > + > + for (i = 0; i < param_dict_len; i++) > + { > + /* > + * Find keys that start with "xen_grub_env_" and export them > + * as environment variables. > + */ > + if (grub_strncmp (param_keys[i], > + "xen_grub_env_", > + sizeof ("xen_grub_env_") - 1) != 0) > + continue; > + grub_env_set (param_keys[i], param_vals[i]); > + grub_env_export (param_keys[i]); Both functions may fail. Don't we care about that? Should not we print a warning? > + } > + > + cleanup: > + for (i = 0; i < word_list_len; i++) > + grub_free (word_list[i]); > + > + for (i = 0; i < param_dict_len; i++) > + { > + grub_free (param_keys[i]); > + grub_free (param_vals[i]); > + } > + > + grub_free (param_keys); > + grub_free (param_vals); > + grub_free (word_list); > +} Daniel From xen-devel-bounces@lists.xenproject.org Fri Aug 01 15:54:53 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 15:54:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067311.1432152 (Exim 4.92) (envelope-from ) id 1uhs5e-0001ju-TU; Fri, 01 Aug 2025 15:54:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067311.1432152; Fri, 01 Aug 2025 15:54:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhs5e-0001jn-Qf; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d792ad7c-8d91-4cc4-896b-08ddd113b3a5 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2025 15:54:30.4519 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lU8lp1iDpPGe63N7QS8S9Wt/vo8RE0H2Pb4DEJqEjjacLaefoHJhoGstyAsB+165DAtesyCwEqFJ3vN6tdKNMxazyFbOV584P32kAFr8Dv0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR03MB6256 From: Grygorii Strashko Call stack for dom0less hwdom case (1:1) memory: create_domUs |-construct_domU |-construct_hwdom() |-allocate_memory_11() And allocate_memory_11() uses "dom0_mem" as: min_low_order =3D get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); In case of dom0less boot the "dom0_mem" is not used and defaulted to 0, which causes min_low_order to get high value > order and so no allocations happens from low memory. Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" has correct memory size in both cases: regular dom0 boot and dom0less boot. Fixes: 43afe6f030244 ("xen/common: dom0less: introduce common dom0less-buil= d.c") Signed-off-by: Grygorii Strashko --- xen/arch/arm/domain_build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 801a09071a50..0a555d1ae0e5 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -278,7 +278,7 @@ static void __init allocate_memory_11(struct domain *d, struct kernel_info *kinfo) { const unsigned int min_low_order =3D - get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); + get_order_from_bytes(min_t(paddr_t, kinfo->unassigned_mem, MB(128)= )); const unsigned int min_order =3D get_order_from_bytes(MB(4)); struct membanks *mem =3D kernel_info_get_mem(kinfo); struct page_info *pg; --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 18:50:29 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 18:50:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067458.1432186 (Exim 4.92) (envelope-from ) id 1uhupc-00081w-50; Fri, 01 Aug 2025 18:50:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067458.1432186; Fri, 01 Aug 2025 18:50:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhupc-00081p-1M; Fri, 01 Aug 2025 18:50:16 +0000 Received: by outflank-mailman (input) for mailman id 1067458; Fri, 01 Aug 2025 18:50:14 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhupZ-00081j-9f for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 18:50:14 +0000 Received: from mail-24418.protonmail.ch (mail-24418.protonmail.ch [109.224.244.18]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 57f32641-6f08-11f0-b897-0df219b8e170; Fri, 01 Aug 2025 20:50:07 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 57f32641-6f08-11f0-b897-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1754074204; x=1754333404; bh=tkU2ubEKzRvgEXI9JXDaJnb41qMKQwm4UGvogAWMJn8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=DZNZBVeTNfGGez/CNz+5eEy93SqqSKGM2jLF2xaUPcZjnIsK7AZuhm0jHD87ymZRZ oqXalu8ZEVt2wqzfZEwh1OFF2dPEyQKHsW8QK/wSFJpUazM/ZwKmQSCQtOELY0y/PI laYuC4xMudhm8kAWozgCCItc27GL4DzbD/KjtRM7kIUlNWkjMcqeSjQxXexrz9prKj PcYtRSm4ySR+D/bwuyR4+NUwt5dDQHD7QYYbBtNFMrEIPK+N4AnHy/csdhx/AwX5iw yR0vp/uJR8/pgbMuHDTMLzq8Z8xlMHzaflxFQFCZo3s+uyv7KL3tMlQ16/WPpIQc35 3cVD8cmdQw8VA== Date: Fri, 01 Aug 2025 18:49:59 +0000 To: Frediano Ziglio From: dmkhn@proton.me Cc: Andrew Cooper , xen-devel Subject: Re: Console vs serial Message-ID: In-Reply-To: References: Feedback-ID: 123220910:user:proton X-Pm-Message-ID: d8d11fae8628742bb4eb795e17aac2deb94f8a3a MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Aug 01, 2025 at 12:44:57PM +0100, Frediano Ziglio wrote: > On Fri, Aug 1, 2025 at 12:25=E2=80=AFPM Andrew Cooper wrote: > > > > Hello, > > > > There's a long-standing irritation in Xen, whereby printk()'s which > > occur prior to console_init_preirq() get half-lost. > > > > They end up in the console ring, and hence are available via `xl dmesg`= , > > but they're missing from serial console. > > > > e.g. these 4 lines don't escape > > > > (XEN) Enabling lockdown mode because Secure Boot is enabled > > (XEN) Lockdown mode is enabled > > (XEN) Ignoring cmdline option 'hap_2mb' in lockdown mode > > (XEN) Ignoring cmdline option 'hap_1gb' in lockdown mode > > __ __ _ _ _ ___ ____ > > \ \/ /___ _ __ | || | / |/ _ \ |___ \ > > > > > > This is from a testcase failure I've just debugged, but the issue is no= t > > specific to secureboot. More generally, any diagnostic from cmdline > > parsing ends up in this state. > > > > For PVShim, we did a gross hack to assume the PV console is usable righ= t > > from the outset, but all other console configurations don't start > > working until the cmdline has been parsed. > > > > Is anything stopping us from feeding the current contents of the consol= e > > ring into serial in console_init_preirq()? > > > > ~Andrew > > >=20 > I don't think there's a problem replaying the console logs into the > serial once the serial is set up. > It will slow down the boot maybe but beside that it should be fine. Replaying console logs into the serial is already a case on staging branch: console_init_preirq() calls conring_flush(..), which will replay everything from conring into all available console devices. -- Denis >=20 > Frediano >=20 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 18:58:51 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 18:58:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067483.1432195 (Exim 4.92) (envelope-from ) id 1uhuxr-0000Fv-TC; Fri, 01 Aug 2025 18:58:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067483.1432195; Fri, 01 Aug 2025 18:58:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhuxr-0000Fo-QV; Fri, 01 Aug 2025 18:58:47 +0000 Received: by outflank-mailman (input) for mailman id 1067483; Fri, 01 Aug 2025 18:58:47 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhuxr-0000Fi-Bp for xen-devel@lists.xenproject.org; Fri, 01 Aug 2025 18:58:47 +0000 Received: from mail-10630.protonmail.ch (mail-10630.protonmail.ch [79.135.106.30]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 8c776738-6f09-11f0-b897-0df219b8e170; Fri, 01 Aug 2025 20:58:45 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8c776738-6f09-11f0-b897-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1754074724; x=1754333924; bh=hF3fXRRemikXKpysMLkzFHck5hyY9cjkXpdyVpV7cYI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=hj6rLPnsHphwTNFp5Dv9JNEdAZ+Dde8RuHn4Mvi5T2SJonLdWGj+pBkZzJk1+mmeY 4J3qL80DIqEXEmALoRyvuVGmh9ESEywJFrTBstKF4r1vg3RuUvP8YsIL2PP1Zy9r8x kWMn8zkCK68UjvDhuYCgxCVZmNPU8GJZF6MwbWYhxEumA8SHtSVLvrlTere0nAL6Aw 06q21q3150bziToFsY4iTgyFwk5yZIRFAuw3hQsv2Re9CqVTn2WU6Vk97A4UzOdt8u EEC2+J/V+znX48fs+MUkN/bx1iUjlJdxBIxmOZeAS6ySb8G8S0/qJ93ulniNTsjL0t d9AzdV+TbPKMA== Date: Fri, 01 Aug 2025 18:58:39 +0000 To: Jan Beulich From: dmkhn@proton.me Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , =?utf-8?Q?Roger_Pau_Monn=C3=A9?= Subject: Re: [PATCH] console: make printk_ratelimit_{burst,ms} const Message-ID: In-Reply-To: <5fcd1c68-6c18-4a1d-8a1d-f056bdb6cde9@suse.com> References: <5fcd1c68-6c18-4a1d-8a1d-f056bdb6cde9@suse.com> Feedback-ID: 123220910:user:proton X-Pm-Message-ID: ea52ee6d97e7d2fb159eae61bf75f796d4b8517f MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Aug 01, 2025 at 09:30:34AM +0200, Jan Beulich wrote: > Them not being altered by any means, their __read_mostly attribute is > actually counter-productive: It causes the compiler to instantiate the > variables, when already with just the attributes dropped the compiler > can constant-propagate the values into the sole use site. Make the > situation yet more explicit by adding const. >=20 > Also switch the variables away from being plain int, and have the > parameters of __printk_ratelimit() follow suit. While there also > similarly adjust the type of "missed" and "lost", and - while touching > the adjacent line - increase lost_str[] to accommodate any unsigned > 32-bit number. >=20 > Fixes: a8b1845a7845 ("Miscellaneous data placement adjustments") > Signed-off-by: Jan Beulich > --- > In principle {__,}printk_ratelimit() may also want to have their return > type changed to bool, but I think doing so would go too far here: This > would have knock-on effects elsewhere, and it would want considering to > actually flip polarity. >=20 > Despite the Fixes: tag I wouldn't consider this for backport. >=20 > --- a/xen/drivers/char/console.c > +++ b/xen/drivers/char/console.c > @@ -1268,12 +1268,12 @@ void console_end_sync(void) > * This enforces a rate limit: not more than one kernel message > * every printk_ratelimit_ms (millisecs). > */ > -int __printk_ratelimit(int ratelimit_ms, int ratelimit_burst) > +int __printk_ratelimit(unsigned int ratelimit_ms, unsigned int ratelimit= _burst) > { > static DEFINE_SPINLOCK(ratelimit_lock); > static unsigned long toks =3D 10 * 5 * 1000; > static unsigned long last_msg; > - static int missed; > + static unsigned int missed; > unsigned long flags; > unsigned long long now =3D NOW(); /* ns */ > unsigned long ms; > @@ -1288,14 +1288,16 @@ int __printk_ratelimit(int ratelimit_ms, > toks =3D ratelimit_burst * ratelimit_ms; > if ( toks >=3D ratelimit_ms ) > { > - int lost =3D missed; > + unsigned int lost =3D missed; > + > missed =3D 0; > toks -=3D ratelimit_ms; > spin_unlock(&ratelimit_lock); > if ( lost ) > { > - char lost_str[8]; > - snprintf(lost_str, sizeof(lost_str), "%d", lost); > + char lost_str[10]; > + > + snprintf(lost_str, sizeof(lost_str), "%u", lost); Since this code is touched, I would also simplify the entire `if ( lost )` block (I have it done in another experiment): =20 char lost_str[64]; size_t lost_len =3D snprintf(lost_str, sizeof(lost_str), "printk: %d messages suppressed.\n", lost_str); /* console_lock may already be acquired by printk(). */ rspin_lock(&console_lock); printk_start_of_line(CONSOLE_PREFIX, cflags); __putstr(lost_str, lost_len); ... What do you think? -- Denis From xen-devel-bounces@lists.xenproject.org Fri Aug 01 19:05:23 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 19:05:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067491.1432206 (Exim 4.92) (envelope-from ) id 1uhv49-0001vD-IU; Fri, 01 Aug 2025 19:05:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067491.1432206; Fri, 01 Aug 2025 19:05:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhv49-0001v6-FV; Fri, 01 Aug 2025 19:05:17 +0000 Received: by outflank-mailman (input) for mailman id 1067491; Fri, 01 Aug 2025 19:05:16 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhv48-0001ux-9a for xen-devel@lists.xenproject.org; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Aug 01, 2025 at 03:54:30PM +0000, Grygorii Strashko wrote: > From: Grygorii Strashko >=20 > Call stack for dom0less hwdom case (1:1) memory: > create_domUs > |-construct_domU > |-construct_hwdom() > |-allocate_memory_11() >=20 > And allocate_memory_11() uses "dom0_mem" as: > min_low_order =3D > get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); >=20 > In case of dom0less boot the "dom0_mem" is not used and defaulted to 0, > which causes min_low_order to get high value > order and so no allocation= s > happens from low memory. >=20 > Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" has correct > memory size in both cases: regular dom0 boot and dom0less boot. >=20 > Fixes: 43afe6f030244 ("xen/common: dom0less: introduce common dom0less-bu= ild.c") > Signed-off-by: Grygorii Strashko Reviewed-by: Denis Mukhin =20 > --- > xen/arch/arm/domain_build.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index 801a09071a50..0a555d1ae0e5 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -278,7 +278,7 @@ static void __init allocate_memory_11(struct domain *= d, > struct kernel_info *kinfo) > { > const unsigned int min_low_order =3D > - get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); > + get_order_from_bytes(min_t(paddr_t, kinfo->unassigned_mem, MB(12= 8))); > const unsigned int min_order =3D get_order_from_bytes(MB(4)); > struct membanks *mem =3D kernel_info_get_mem(kinfo); > struct page_info *pg; > -- > 2.34.1 >=20 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 19:08:23 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 19:08:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067497.1432216 (Exim 4.92) (envelope-from ) id 1uhv77-0002SM-Uw; Fri, 01 Aug 2025 19:08:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1067497.1432216; Fri, 01 Aug 2025 19:08:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhv77-0002SF-S9; Fri, 01 Aug 2025 19:08:21 +0000 Received: by outflank-mailman (input) for mailman id 1067497; Fri, 01 Aug 2025 19:08:20 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uhv76-0002S9-Em for xen-devel@lists.xenproject.org; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Aug 01, 2025 at 10:08:54AM +0000, Grygorii Strashko wrote: > From: Grygorii Strashko >=20 > Hence prerequisite patch was merged [1] arch specific pIRQ callback can n= ow > be dropped for arches without pIRQ support as those callback become unrea= chable. >=20 > [1] commit 341f271cf86f ("xen/evtchn: fully restrict concept of pIRQ for = arches with pIRQ support only") >=20 > Grygorii Strashko (3): > xen/arm: irq: drop unreachable pirq callbacks > xen/ppc: irq: drop unreachable pirq callbacks > xen/riscv: irq: drop unreachable pirq callbacks Please consider Reviewed-by: Denis Mukhin =20 for the series with or without further corrections for commit messages (there was a separate request). >=20 > xen/arch/arm/irq.c | 29 ----------------------------- > xen/arch/ppc/stubs.c | 20 -------------------- > xen/arch/riscv/stubs.c | 20 -------------------- > 3 files changed, 69 deletions(-) >=20 > -- > 2.34.1 >=20 From xen-devel-bounces@lists.xenproject.org Fri Aug 01 19:30:47 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Fri, 01 Aug 2025 19:30:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1067505.1432226 (Exim 4.92) (envelope-from ) id 1uhvSj-0006JO-KV; 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a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1754076634; x=1754335834; bh=BXrfkVJajnM8+5TEJnfsv1KbBVPEsL6OqjTqeJBMUWs=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Li3PQW1F/zQNKtNNMiAYQjnqJM6NNlPTgPIIEdvdbm+ukl0jyZVPLfR5o2AMZiifY xXtPfIcbhZxrEqRV8PzHnczF19GnrvHsk4xj9t7Cm4R37ZiAASq0nbMFsXBVKw7r1y 6opGFcZ1KTx7rfFQUnSvpaiU5NXrcFEa7V9RI7GyqXObs6aPrZEb4F8lgeCxUjWkK0 7DwbZa44ZXN7PjKChbhq+HVy4GlTT4rtzCCSIO+N5wNIL7fQAjaSl8LMOt8mwC3Iw1 YAoM4ub+HtkeMJwbHE71iuwrem2KqC1iNTOVRlSpT+tnntkAZyqlHA6TC6dw/4BQsL 5x68VK1MA1BCA== Date: Fri, 01 Aug 2025 19:30:30 +0000 To: Jan Beulich From: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, oleksii.kurochko@gmail.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org Subject: Re: [PATCH v1 12/16] xen/domain: introduce domain-emu.h Message-ID: In-Reply-To: <65e288b7-d8fe-409e-a287-69b4dc29f0c2@suse.com> References: <20250624035443.344099-1-dmukhin@ford.com> <20250624035443.344099-13-dmukhin@ford.com> <33f98fe5-9b29-43e4-a87d-19eafb30f281@suse.com> <65e288b7-d8fe-409e-a287-69b4dc29f0c2@suse.com> Feedback-ID: 123220910:user:proton X-Pm-Message-ID: e4490218c319029c70d51aa0e441fc0694d22c6b MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Fri, Aug 01, 2025 at 08:02:56AM +0200, Jan Beulich wrote: > On 31.07.2025 22:55, dmkhn@proton.me wrote: > > On Wed, Jul 09, 2025 at 04:57:44PM +0200, Jan Beulich wrote: > >> On 24.06.2025 05:56, dmkhn@proton.me wrote: > >>> @@ -458,16 +459,16 @@ struct arch_domain > >>> } __cacheline_aligned; > >>> > >>> #ifdef CONFIG_HVM > >>> -#define X86_EMU_LAPIC XEN_X86_EMU_LAPIC > >>> -#define X86_EMU_HPET XEN_X86_EMU_HPET > >>> -#define X86_EMU_PM XEN_X86_EMU_PM > >>> -#define X86_EMU_RTC XEN_X86_EMU_RTC > >>> -#define X86_EMU_IOAPIC XEN_X86_EMU_IOAPIC > >>> -#define X86_EMU_PIC XEN_X86_EMU_PIC > >>> -#define X86_EMU_VGA XEN_X86_EMU_VGA > >>> -#define X86_EMU_IOMMU XEN_X86_EMU_IOMMU > >>> -#define X86_EMU_USE_PIRQ XEN_X86_EMU_USE_PIRQ > >>> -#define X86_EMU_VPCI XEN_X86_EMU_VPCI > >> > >> The old code deliberately used values from the public interface. > > > > In next version I am building, I moved all of XEN_X86_EMU_XXX definitio= ns as > > is to a new public header under include/public/xen-emu.h: > > > > https://gitlab.com/xen-project/people/dmukhin/xen/-/commit/9b0bc5ffa5= 710114df8523ae2aa7680b7c6f0942 > > > > That looks less invasive. > > > > Will that work? > > > > There should be a common header with emulation flags somewhere, since > > there will be SBSA and hwdom vUART definitions there. >=20 > Yet will there be a strict need for any constants to be identical (i.e. > not only have the same name, but also the same value) across architecture= s? I don't think there's strict need for identical values across achitectures. But some of the constants _may_ be reused for non-x86 arches, like VPCI bit and, perhaps, IOMMU, PIRQ and future NS16550 (after adding MMIO). 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2025 20:24:22.1103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58a08fdf-99db-4fa3-35c7-08ddd139669f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8362 In vcpu_create after scheduler data is allocated, if vmtrace_alloc_buffer fails, it will jump to the wrong cleanup label resulting in a memory leak. Move sched_destroy_vcpu and destroy_waitqueue_vcpu to vcpu_teardown. Make vcpu_teardown idempotent: deal with NULL unit. Fix vcpu_runstate_get (called during XEN_SYSCTL_getdomaininfolist post vcpu_teardown) when v->sched_unit is NULL. Fixes: 217dd79ee292 ("xen/domain: Add vmtrace_size domain creation parameter") Signed-off-by: Stewart Hildebrand --- v1->v2: * move cleanup functions to vcpu_teardown * renamed, was ("xen: fix memory leak on error in vcpu_create") --- xen/common/domain.c | 14 ++++++-------- xen/common/sched/core.c | 5 ++++- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/xen/common/domain.c b/xen/common/domain.c index 5241a1629eeb..9c65c2974ea3 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -388,6 +388,8 @@ static int vmtrace_alloc_buffer(struct vcpu *v) static int vcpu_teardown(struct vcpu *v) { vmtrace_free_buffer(v); + sched_destroy_vcpu(v); + destroy_waitqueue_vcpu(v); return 0; } @@ -448,13 +450,13 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) } if ( sched_init_vcpu(v) != 0 ) - goto fail_wq; + goto fail; if ( vmtrace_alloc_buffer(v) != 0 ) - goto fail_wq; + goto fail; if ( arch_vcpu_create(v) != 0 ) - goto fail_sched; + goto fail; d->vcpu[vcpu_id] = v; if ( vcpu_id != 0 ) @@ -472,11 +474,7 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) return v; - fail_sched: - sched_destroy_vcpu(v); - fail_wq: - destroy_waitqueue_vcpu(v); - + fail: /* Must not hit a continuation in this context. */ if ( vcpu_teardown(v) ) ASSERT_UNREACHABLE(); diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c index 2ab4313517c3..fb7c99b05360 100644 --- a/xen/common/sched/core.c +++ b/xen/common/sched/core.c @@ -321,7 +321,7 @@ void vcpu_runstate_get(const struct vcpu *v, */ unit = is_idle_vcpu(v) ? get_sched_res(v->processor)->sched_unit_idle : v->sched_unit; - lock = likely(v == current) ? NULL : unit_schedule_lock_irq(unit); + lock = likely(v == current || !unit) ? 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pr=C Message-ID: <6d5545a2-bbf0-4cf9-9820-5eaf6d8530f8@amd.com> Date: Fri, 1 Aug 2025 17:06:32 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] vpci: allow queueing of mapping operations To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= CC: , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , Stefano Stabellini References: <20250723163744.13095-1-stewart.hildebrand@amd.com> <20250723163744.13095-2-stewart.hildebrand@amd.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343D:EE_|BL4PR12MB9533:EE_ X-MS-Office365-Filtering-Correlation-Id: df187537-9d65-45ac-726d-08ddd13f4b1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2025 21:06:32.9022 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df187537-9d65-45ac-726d-08ddd13f4b1d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9533 On 7/25/25 03:58, Roger Pau Monné wrote: > On Thu, Jul 24, 2025 at 06:44:32PM +0200, Roger Pau Monné wrote: >> On Wed, Jul 23, 2025 at 12:37:41PM -0400, Stewart Hildebrand wrote: >>> @@ -283,7 +297,48 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, >>> return rc; >>> } >>> >>> -static void defer_map(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) >>> +static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, >>> + uint16_t cmd, bool rom_only) >>> +{ >>> + struct vpci_map_task *task = xzalloc(struct vpci_map_task); >> >> xvzalloc() preferably. >> >> This however introduces run-time allocations as a result of guest >> actions, which is not ideal IMO. It would be preferable to do those >> allocations as part of the header initialization, and re-use them. > > I've been thinking over this, as I've realized that while commenting > on it, I didn't provide any alternatives. > > The usage of rangesets to figure out the regions to map is already not > optimal, as adding/removing from a rangeset can lead to memory > allocations. It would be good if we could create rangesets with a > pre-allocated number of ranges (iow: a pool of struct ranges), but > that's for another patchset. I think Jan already commented on this > aspect long time ago. +1 > I'm considering whether to allocate the deferred mapping structures > per-vCPU instead of per-device. That would for example mean moving > the current vpci_bar->mem rangeset so it's allocated in vpci_vcpu > struct instead. The point would be to not have the rangesets per > device (because there can be a lot of devices, specially for the > hardware domain), but instead have those per-vCPU. This should work > because a vCPU can only queue a single vPCI operation, from a single > device. > > It should then be possible to allocate the deferred mapping structures > at vCPU creation. I also ponder if we really need a linked list to > queue them; AFAIK there can only ever be an unmapping and a mapping > operation pending (so 2 operations at most). Hence we could use a > more "fixed" structure like an array. For example in struct vpci_vcpu > you could introduce a struct vpci_map_task task[2] field? > > Sorry, I know this is not a minor change to request. It shouldn't > change the overall logic much, but it would inevitably affect the > code. Let me know what you think. Thanks for the feedback and suggestion. Yeah, I'll give this a try. Here's roughly what I'm thinking so far. I'll keep playing with it. diff --git a/xen/common/domain.c b/xen/common/domain.c index 5241a1629eeb..942c9fe7d364 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -387,6 +387,16 @@ static int vmtrace_alloc_buffer(struct vcpu *v) */ static int vcpu_teardown(struct vcpu *v) { +#ifdef CONFIG_HAS_VPCI + for ( unsigned int i = 0; i < ARRAY_SIZE(v->vpci.task); i++ ) + { + struct vpci_map_task *task = &v->vpci.task[i]; + + for ( unsigned int j = 0; j < ARRAY_SIZE(task->bars); j++ ) + rangeset_destroy(task->bars[j].mem); + } +#endif + vmtrace_free_buffer(v); return 0; @@ -467,6 +477,26 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) d->vcpu[prev_id]->next_in_list = v; } +#ifdef CONFIG_HAS_VPCI + for ( unsigned int i = 0; i < ARRAY_SIZE(v->vpci.task); i++ ) + { + struct vpci_map_task *task = &v->vpci.task[i]; + + for ( unsigned int j = 0; j < ARRAY_SIZE(task->bars); j++ ) + { + struct vpci_bar_map *bar = &task->bars[j]; + char str[32]; + + snprintf(str, sizeof(str), "PCI map vcpu %u task %u BAR %u", vcpu_id, i, j); + + bar->mem = rangeset_new(v->domain, str, RANGESETF_no_print); + + if ( !bar->mem ) + goto fail_sched; + } + } +#endif + /* Must be called after making new vcpu visible to for_each_vcpu(). */ vcpu_check_shutdown(v); diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 17cfecb0aabf..afe78b00ffc9 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -116,7 +116,6 @@ struct vpci { uint64_t guest_addr; uint64_t size; uint64_t resizable_sizes; - struct rangeset *mem; enum { VPCI_BAR_EMPTY, VPCI_BAR_IO, @@ -207,14 +206,23 @@ struct vpci { #endif }; +#ifdef __XEN__ struct vpci_vcpu { /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ const struct pci_dev *pdev; - uint16_t cmd; - bool rom_only : 1; + struct domain *domain; + unsigned int nr_pending_ops; + struct vpci_map_task { + struct vpci_bar_map { + uint64_t addr; + uint64_t guest_addr; + struct rangeset *mem; + } bars[PCI_HEADER_NORMAL_NR_BARS + 1]; + uint16_t cmd; + bool rom_only : 1; + } task[2]; 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bugseng.com; arc=none smtp.remote-ip=162.55.131.47 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=bugseng.com; s=mail; t=1754161808; bh=3zW3+kMHj8v/g7CQloeTL/9yWVXx4YDrLTSLqD+dl5E=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=PkmQoVw1o9gkfry9jvShK8+OjfPMWGbUhjSJiL2N4qgSW5MYOZMiu6fBlFWe41Wsg D0r2IMTMI5lWpciiHnecEGycUM81ge50nG1DLDcWz2uXSystofF8KDToTXyI+1aVR6 MwMAud+wft6kaECtOTynchowWr72YUfLupUgWgsSf3+IYy+f8JF3JgeF65GCAUi7x7 yEdCJ6XWFEYUT+ItKlMNcRbIfdYPzzhfqWuDVneRuk6Zuqk3tx/9vXgE/dKSOk0d9u J65Wt7veR7Nr1DUNKhqOS9CNhbnlLPzFyClPHxWYgKoIuAFPuwHJcNQfK4So1V7Rvm zSDxsFdy22/EQ== MIME-Version: 1.0 Date: Sat, 02 Aug 2025 21:10:08 +0200 From: Nicola Vetrini To: Dmytro Prokopchuk1 Cc: xen-devel@lists.xenproject.org, Stefano Stabellini Subject: Re: [RFC] Next steps for MISRA C Rule 17.7 in XEN In-Reply-To: <6d622813-1617-4af3-876e-52a551518f68@epam.com> References: <6d622813-1617-4af3-876e-52a551518f68@epam.com> Message-ID: <42f485a1e32536f3d905c9564b6fdebb@bugseng.com> X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit On 2025-08-02 19:48, Dmytro Prokopchuk1 wrote: > Hello folks! > > There are a lot of MISRA C R17.7 violations in the XEN. > This rule states: "The value returned by a function having non-void > return type shall be used". > > Actually, need to decide how to deal with these violations. > Quick analyze shown that there are different cases in XEN code base. > Like, for example: > > the return value of function > `clean_and_invalidate_dcache_va_range(const > void*, unsigned long)' (unit `xen/arch/arm/alternative.c' with target > `xen/arch/arm/alternative.o') is unexpectedly ignored > This thread [1] has some discussions around the cache invalidation helpers, so it may be useful to consider the points raised there in this discussion [1] https://lore.kernel.org/xen-devel/cc6bf44701c808645c69bacaf4463295e2cb0fba.1708354388.git.nicola.vetrini@bugseng.com/ > The return value of this function > 'clean_and_invalidate_dcache_va_range' > is checked only in one place. Probably, after deeper analyze the return > value can be dropped and function prototype can be changed to > > static inline void clean_and_invalidate_dcache_va_range > (const void *p, unsigned long size); > > > Next case is vice versa: > > the return value of function `vgic_reserve_virq(struct domain*, > unsigned)' is unexpectedly ignored > > There is only one place where the return value is not checked. > Probably, in this place code may be changed to: > > (void)vgic_reserve_virq(d, irq); > > > For the case with 'memset' function: > > the return value of function `memset(void*, int, size_t)' is > unexpectedly ignored > > I guess it's better to create deviation, something like: > > "The return value of the function memset(void *, int, size_t) is > ignored > because the primary purpose of the function is to set a block of memory > to a specific value, not to use the pointer returned by the function." > > > But due to the large number of violations, it will be tricky to address > all of them. > I don't know, maybe the only right solution is to deviate all. > > > Thanks! > Dmytro. -- Nicola Vetrini, B.Sc. Software Engineer BUGSENG (https://bugseng.com) LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 01:05:13 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 01:05:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068175.1432276 (Exim 4.92) (envelope-from ) id 1uiN9l-0002cg-E4; Sun, 03 Aug 2025 01:04:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068175.1432276; Sun, 03 Aug 2025 01:04:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiN9l-0002cV-9C; Sun, 03 Aug 2025 01:04:57 +0000 Received: by outflank-mailman (input) for mailman id 1068175; Sun, 03 Aug 2025 01:04:56 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiN9j-0002cJ-UO for xen-devel@lists.xenproject.org; Sun, 03 Aug 2025 01:04:56 +0000 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id dc7965a2-7005-11f0-b897-0df219b8e170; Sun, 03 Aug 2025 03:04:52 +0200 (CEST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 395D841DE2; Sun, 3 Aug 2025 01:04:50 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: dc7965a2-7005-11f0-b897-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1754183092; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=IG2HpXzsqu+NkhilqnbEM95yf9B6n+TV1enjTn2IGB8=; b=ibJLf44Stz+KQ8z1BIhUrXB8Hx8q3mDVJsoazKdnF5cGuJvjReExXK4mcEOGy+KCLeZn/+ kiZ6ksHecS6yzjenen9Bap4+NogZvlkX8LS/fcaTLx2nCLDMs16sjfVWHO2BVoee+7W6h1 UEJQo/hhQZmslKN2uXNBIo6f/iV7i4i2ULavQeZYg9xJlgn+4UWyifl1oqRN5FdvDOipjo Anoil5WSqw3fdSJJkxGIZeUHKgePK471C7AqiXKnuTl4IJNxiRavQiZ+ZSEcB4GlH//Ny4 WFnmiHTOQORQeOxW5S5sx2Fjc6aV8soQemag6oeQvhlj/yfB9gN8N5R45YYCkg== Date: Sun, 3 Aug 2025 03:04:49 +0200 From: Alexandre Belloni To: Ard Biesheuvel Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Heinrich Schuchardt , Feng Tang , Juergen Gross , Stefano Stabellini , Oleksandr Tyshchenko , Sunil V L , Bibo Mao , linux-rtc@vger.kernel.org, linux-efi@vger.kernel.org, xen-devel@lists.xenproject.org, x86@kernel.org, linux-riscv@lists.infradead.org, loongarch@lists.linux.dev Subject: Re: [RFC PATCH 1/3] efi-rtc: Remove wakeup functionality Message-ID: <20250803010449df1f5cfb@mail.local> References: <20250714060843.4029171-5-ardb+git@google.com> <20250714060843.4029171-6-ardb+git@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250714060843.4029171-6-ardb+git@google.com> X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgddutdektdekucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuifetpfffkfdpucggtfgfnhhsuhgsshgtrhhisggvnecuuegrihhlohhuthemuceftddunecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpeffhffvvefukfhfgggtuggjsehttdertddttddvnecuhfhrohhmpeetlhgvgigrnhgurhgvuceuvghllhhonhhiuceorghlvgigrghnughrvgdrsggvlhhlohhnihessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhepgeeiudeuteehhfekgeejveefhfeiudejuefhgfeljefgjeegkeeujeeugfehgefgnecuffhomhgrihhnpegsohhothhlihhnrdgtohhmnecukfhppedvrgdtudemvgdtrgemvdgumeeifeejtdemjeekvgdtmegttdgvkeemvdektdeimeekrggtieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpedvrgdtudemvgdtrgemvdgumeeifeejtdemjeekvgdtmegttdgvkeemvdektdeimeekrggtiedphhgvlhhopehlohgtrghlhhhoshhtpdhmrghilhhfrhhomheprghlvgigrghnughrvgdrsggvlhhlohhnihessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepudejpdhrtghpthhtoheprghruggsodhgihhtsehgohhoghhlvgdrtghomhdprhgtphhtthhopehlihhnuhigqdhkvghrnhgvlhesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehli hhnuhigqdgrrhhmqdhkvghrnhgvlheslhhishhtshdrihhnfhhrrgguvggrugdrohhrghdprhgtphhtthhopegrrhgusgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtohephhgvihhnrhhitghhrdhstghhuhgthhgrrhguthestggrnhhonhhitggrlhdrtghomhdprhgtphhtthhopehfvghnghdrthgrnhhgsehlihhnuhigrdgrlhhisggrsggrrdgtohhmpdhrtghpthhtohepjhhgrhhoshhssehsuhhsvgdrtghomhdprhgtphhtthhopehsshhtrggsvghllhhinhhisehkvghrnhgvlhdrohhrgh X-GND-Sasl: alexandre.belloni@bootlin.com Hello, Apart from the topic that should be "rtc: efi:...", I'm ready to apply this patch. On 14/07/2025 08:08:45+0200, Ard Biesheuvel wrote: > From: Ard Biesheuvel > > The EFI rtc driver is used by non-x86 architectures only, and exposes > the get/set wakeup time functionality provided by the underlying > platform. This is usually broken on most platforms, and not widely used > to begin with [if at all], so let's just remove it. > > Signed-off-by: Ard Biesheuvel > --- > drivers/rtc/rtc-efi.c | 76 +------------------- > 1 file changed, 2 insertions(+), 74 deletions(-) > > diff --git a/drivers/rtc/rtc-efi.c b/drivers/rtc/rtc-efi.c > index fa8bf82df948..b4f44999ef0f 100644 > --- a/drivers/rtc/rtc-efi.c > +++ b/drivers/rtc/rtc-efi.c > @@ -112,48 +112,6 @@ convert_from_efi_time(efi_time_t *eft, struct rtc_time *wtime) > return true; > } > > -static int efi_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) > -{ > - efi_time_t eft; > - efi_status_t status; > - > - /* > - * As of EFI v1.10, this call always returns an unsupported status > - */ > - status = efi.get_wakeup_time((efi_bool_t *)&wkalrm->enabled, > - (efi_bool_t *)&wkalrm->pending, &eft); > - > - if (status != EFI_SUCCESS) > - return -EINVAL; > - > - if (!convert_from_efi_time(&eft, &wkalrm->time)) > - return -EIO; > - > - return rtc_valid_tm(&wkalrm->time); > -} > - > -static int efi_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm) > -{ > - efi_time_t eft; > - efi_status_t status; > - > - convert_to_efi_time(&wkalrm->time, &eft); > - > - /* > - * XXX Fixme: > - * As of EFI 0.92 with the firmware I have on my > - * machine this call does not seem to work quite > - * right > - * > - * As of v1.10, this call always returns an unsupported status > - */ > - status = efi.set_wakeup_time((efi_bool_t)wkalrm->enabled, &eft); > - > - dev_warn(dev, "write status is %d\n", (int)status); > - > - return status == EFI_SUCCESS ? 0 : -EINVAL; > -} > - > static int efi_read_time(struct device *dev, struct rtc_time *tm) > { > efi_status_t status; > @@ -188,17 +146,13 @@ static int efi_set_time(struct device *dev, struct rtc_time *tm) > > static int efi_procfs(struct device *dev, struct seq_file *seq) > { > - efi_time_t eft, alm; > + efi_time_t eft; > efi_time_cap_t cap; > - efi_bool_t enabled, pending; > - struct rtc_device *rtc = dev_get_drvdata(dev); > > memset(&eft, 0, sizeof(eft)); > - memset(&alm, 0, sizeof(alm)); > memset(&cap, 0, sizeof(cap)); > > efi.get_time(&eft, &cap); > - efi.get_wakeup_time(&enabled, &pending, &alm); > > seq_printf(seq, > "Time\t\t: %u:%u:%u.%09u\n" > @@ -214,26 +168,6 @@ static int efi_procfs(struct device *dev, struct seq_file *seq) > /* XXX fixme: convert to string? */ > seq_printf(seq, "Timezone\t: %u\n", eft.timezone); > > - if (test_bit(RTC_FEATURE_ALARM, rtc->features)) { > - seq_printf(seq, > - "Alarm Time\t: %u:%u:%u.%09u\n" > - "Alarm Date\t: %u-%u-%u\n" > - "Alarm Daylight\t: %u\n" > - "Enabled\t\t: %s\n" > - "Pending\t\t: %s\n", > - alm.hour, alm.minute, alm.second, alm.nanosecond, > - alm.year, alm.month, alm.day, > - alm.daylight, > - enabled == 1 ? "yes" : "no", > - pending == 1 ? "yes" : "no"); > - > - if (alm.timezone == EFI_UNSPECIFIED_TIMEZONE) > - seq_puts(seq, "Timezone\t: unspecified\n"); > - else > - /* XXX fixme: convert to string? */ > - seq_printf(seq, "Timezone\t: %u\n", alm.timezone); > - } > - > /* > * now prints the capabilities > */ > @@ -249,8 +183,6 @@ static int efi_procfs(struct device *dev, struct seq_file *seq) > static const struct rtc_class_ops efi_rtc_ops = { > .read_time = efi_read_time, > .set_time = efi_set_time, > - .read_alarm = efi_read_alarm, > - .set_alarm = efi_set_alarm, > .proc = efi_procfs, > }; > > @@ -271,11 +203,7 @@ static int __init efi_rtc_probe(struct platform_device *dev) > platform_set_drvdata(dev, rtc); > > rtc->ops = &efi_rtc_ops; > - clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->features); > - if (efi_rt_services_supported(EFI_RT_SUPPORTED_WAKEUP_SERVICES)) > - set_bit(RTC_FEATURE_ALARM_WAKEUP_ONLY, rtc->features); > - else > - clear_bit(RTC_FEATURE_ALARM, rtc->features); > + clear_bit(RTC_FEATURE_ALARM, rtc->features); > > device_init_wakeup(&dev->dev, true); > > -- > 2.50.0.727.gbf7dc18ff4-goog > -- Alexandre Belloni, co-owner and COO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com From xen-devel-bounces@lists.xenproject.org Sun Aug 03 04:25:16 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 04:25:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068234.1432285 (Exim 4.92) (envelope-from ) id 1uiQHO-000121-Ug; Sun, 03 Aug 2025 04:25:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068234.1432285; Sun, 03 Aug 2025 04:25:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiQHO-00011u-Rn; Sun, 03 Aug 2025 04:25:02 +0000 Received: by outflank-mailman (input) for mailman id 1068234; Sun, 03 Aug 2025 04:25:01 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiQHN-00011o-LG for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------1gFvVR9xjY5GAdqPj6Vym0sn" This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------1gFvVR9xjY5GAdqPj6Vym0sn Content-Type: multipart/mixed; boundary="------------tqmSlId12aASw5ET13epmu6A"; protected-headers="v1" From: Demi Marie Obenour To: Bertrand Marquis , xen-devel@lists.xenproject.org Cc: jens.wiklander@linaro.org, Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Message-ID: Subject: Re: [PATCH v7 3/6] xen/arm: ffa: Introduce VM to VM support References: <50224eb7cca4eaef2646ad8e33f689d912704733.1752754016.git.bertrand.marquis@arm.com> In-Reply-To: <50224eb7cca4eaef2646ad8e33f689d912704733.1752754016.git.bertrand.marquis@arm.com> --------------tqmSlId12aASw5ET13epmu6A Content-Type: multipart/mixed; boundary="------------bqBHrF0KlkMQcY9Dc2SWglro" --------------bqBHrF0KlkMQcY9Dc2SWglro Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 7/17/25 08:11, Bertrand Marquis wrote: > Create a CONFIG_FFA_VM_TO_VM parameter to activate FFA communication > between VMs. > When activated list VMs in the system with FF-A support in part_info_ge= t. >=20 > When VM to VM is activated, Xen will be tainted as Insecure and a > message is displayed to the user during the boot as there is no > filtering of VMs in FF-A so any VM can communicate or see any other VM > in the system. >=20 > WARNING: There is no filtering for now and all VMs are listed !! I'm pretty sure that there is already no filtering for things like grant tables and event channels, so this doesn't make things any worse. That said, FF-A is quite tricky to implement without integer overflow/wraparou= nd or denial of service bugs. In particular, code in Hafnium (Secure Partit= ion Monitor running in S-EL2) requires quadratic time because of repeated lin= ear searches. Xen is allowed to use dynamic memory allocation, so it can, sh= ould, and must do better. --=20 Sincerely, Demi Marie Obenour (she/her/hers) --------------bqBHrF0KlkMQcY9Dc2SWglro Content-Type: application/pgp-keys; name="OpenPGP_0xB288B55FFF9C22C1.asc" Content-Disposition: attachment; filename="OpenPGP_0xB288B55FFF9C22C1.asc" Content-Description: OpenPGP public key Content-Transfer-Encoding: quoted-printable -----BEGIN PGP PUBLIC KEY BLOCK----- xsFNBFp+A0oBEADffj6anl9/BHhUSxGTICeVl2tob7hPDdhHNgPR4C8xlYt5q49y B+l2nipdaq+4Gk6FZfqC825TKl7eRpUjMriwle4r3R0ydSIGcy4M6eb0IcxmuPYf bWpr/si88QKgyGSVZ7GeNW1UnzTdhYHuFlk8dBSmB1fzhEYEk0RcJqg4AKoq6/3/ UorR+FaSuVwT7rqzGrTlscnTDlPWgRzrQ3jssesI7sZLm82E3pJSgaUoCdCOlL7M MPCJwI8JpPlBedRpe9tfVyfu3euTPLPxwcV3L/cfWPGSL4PofBtB8NUU6QwYiQ9H zx4xOyn67zW73/G0Q2vPPRst8LBDqlxLjbtx/WLR6h3nBc3eyuZ+q62HS1pJ5EvU T1vjyJ1ySrqtUXWQ4XlZyoEFUfpJxJoN0A9HCxmHGVckzTRl5FMWo8TCniHynNXs BtDQbabt7aNEOaAJdE7to0AH3T/Bvwzcp0ZJtBk0EM6YeMLtotUut7h2Bkg1b//r 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xen-devel@lists.xenproject.org Content-Language: de-DE, en-US From: =?UTF-8?Q?Christoph_Gr=C3=BCninger?= Subject: Fork or replace dependency yajl? Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Dear Xen developers, you are using the dependency yajl (yet another json library, [1]) to parse JSON files. The project seems abandoned with the last commit 10 years ago, the last release over 11 years ago, and 75 open pull requests. Packaging yajl requires patches, e.g., to make it compatible with CMake 4.0. There are some forks but none has replaced the old one yet [2]. I think there are three paths forward: 1. Xen could pick a prominent fork and use it as its main dependency. 2. Xen could create a fork of its own, hopefully attracting more people interested in an maintained successor of yajl. 3. Switch to a different JSON parser library that remained healthy. Sure, you could stick to option 4., do nothing an offload the burden to fix yajl to distribution packagers. Xen is an important project and its decision can create momentum that might lead other projects. [1] https://github.com/lloyd/yajl [2] https://github.com/lloyd/yajl/issues/252 Kind regards, Christoph -- Most customers will not accept source code with compile errors in it. Dan Saks, CppCon 2016 (https://youtu.be/D7Sd8A6_fYU) From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:48:20 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:48:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068339.1432315 (Exim 4.92) (envelope-from ) id 1uiVKE-0005Ya-A7; Sun, 03 Aug 2025 09:48:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068339.1432315; Sun, 03 Aug 2025 09:48:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVKE-0005YT-7K; Sun, 03 Aug 2025 09:48:18 +0000 Received: by outflank-mailman (input) for mailman id 1068339; Sun, 03 Aug 2025 09:48:17 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVKC-0005K3-VN for xen-devel@lists.xenproject.org; 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bh=wMenH/9InGy31gRbO7Zt6kQeOlelkssdQv5WC1YzgYM=; b=29ddRivhTTAezUFe85aYMqQGxww+teKFngczXQ0ehnR/V7MOUJTIQXDkPDvXMJdV7SOWuh2bPm2kjDTyjrQPCHPF4puSKbAHV4+dCQXMDs5f050W/cu31+PQYn3SCWoner2P/72ZVX2CzahUKKcTLithPionVgErWiw7/ajbto4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: CC: , Penny Zheng , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v1 02/25] xen/x86: consolidate vram tracking support Date: Sun, 3 Aug 2025 17:47:15 +0800 Message-ID: <20250803094738.3625269-3-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231C:EE_|DS2PR12MB9823:EE_ X-MS-Office365-Filtering-Correlation-Id: e91c1bc7-7004-4748-fd97-08ddd272dbe2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:11.2327 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e91c1bc7-7004-4748-fd97-08ddd272dbe2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9823 Flag PG_log_dirty is for paging log dirty support, not vram tracking support. However data structure sh_dirty_vram{} and function paging_log_dirty_range() designed for vram tracking support, are guarded with PG_log_dirty. We release both from PG_log_dirty, and also move paging_log_dirty_range() into hap.c, to make it static. Signed-off-by: Penny Zheng --- xen/arch/x86/include/asm/paging.h | 32 +++++++++++++------------------ xen/arch/x86/mm/hap/hap.c | 32 +++++++++++++++++++++++++++++++ xen/arch/x86/mm/paging.c | 32 ------------------------------- 3 files changed, 45 insertions(+), 51 deletions(-) diff --git a/xen/arch/x86/include/asm/paging.h b/xen/arch/x86/include/asm/paging.h index 8a2a0af408..173a569610 100644 --- a/xen/arch/x86/include/asm/paging.h +++ b/xen/arch/x86/include/asm/paging.h @@ -133,13 +133,20 @@ struct paging_mode { (DIV_ROUND_UP(PADDR_BITS - PAGE_SHIFT - (PAGE_SHIFT + 3), \ PAGE_SHIFT - ilog2(sizeof(mfn_t))) + 1) -#if PG_log_dirty +#ifdef CONFIG_HVM +/* VRAM dirty tracking support */ +struct sh_dirty_vram { + unsigned long begin_pfn; + unsigned long end_pfn; +#ifdef CONFIG_SHADOW_PAGING + paddr_t *sl1ma; + uint8_t *dirty_bitmap; + s_time_t last_dirty; +#endif +}; +#endif -/* get the dirty bitmap for a specific range of pfns */ -void paging_log_dirty_range(struct domain *d, - unsigned long begin_pfn, - unsigned long nr, - uint8_t *dirty_bitmap); +#if PG_log_dirty /* log dirty initialization */ void paging_log_dirty_init(struct domain *d, const struct log_dirty_ops *ops); @@ -171,19 +178,6 @@ bool paging_mfn_is_dirty(const struct domain *d, mfn_t gmfn); #define L4_LOGDIRTY_IDX(pfn) ((pfn_x(pfn) >> (PAGE_SHIFT + 3 + PAGETABLE_ORDER * 2)) & \ (LOGDIRTY_NODE_ENTRIES-1)) -#ifdef CONFIG_HVM -/* VRAM dirty tracking support */ -struct sh_dirty_vram { - unsigned long begin_pfn; - unsigned long end_pfn; -#ifdef CONFIG_SHADOW_PAGING - paddr_t *sl1ma; - uint8_t *dirty_bitmap; - s_time_t last_dirty; -#endif -}; -#endif - #else /* !PG_log_dirty */ static inline void paging_log_dirty_init(struct domain *d, diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index ec5043a8aa..668a233923 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -36,6 +36,38 @@ /* HAP VRAM TRACKING SUPPORT */ /************************************************/ +#ifdef CONFIG_HVM +static void paging_log_dirty_range(struct domain *d, + unsigned long begin_pfn, + unsigned long nr, + uint8_t *dirty_bitmap) +{ + struct p2m_domain *p2m = p2m_get_hostp2m(d); + int i; + unsigned long pfn; + + /* + * Set l1e entries of P2M table to be read-only. + * + * On first write, it page faults, its entry is changed to read-write, + * and on retry the write succeeds. + * + * We populate dirty_bitmap by looking for entries that have been + * switched to read-write. + */ + + p2m_lock(p2m); + + for ( i = 0, pfn = begin_pfn; pfn < begin_pfn + nr; i++, pfn++ ) + if ( !p2m_change_type_one(d, pfn, p2m_ram_rw, p2m_ram_logdirty) ) + dirty_bitmap[i >> 3] |= (1 << (i & 7)); + + p2m_unlock(p2m); + + guest_flush_tlb_mask(d, d->dirty_cpumask); +} +#endif /* CONFIG_HVM */ + /* * hap_track_dirty_vram() * Create the domain's dv_dirty_vram struct on demand. diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c index c77f4c1dac..1216a181c3 100644 --- a/xen/arch/x86/mm/paging.c +++ b/xen/arch/x86/mm/paging.c @@ -583,38 +583,6 @@ static int paging_log_dirty_op(struct domain *d, return rv; } -#ifdef CONFIG_HVM -void paging_log_dirty_range(struct domain *d, - unsigned long begin_pfn, - unsigned long nr, - uint8_t *dirty_bitmap) -{ - struct p2m_domain *p2m = p2m_get_hostp2m(d); - int i; - unsigned long pfn; - - /* - * Set l1e entries of P2M table to be read-only. - * - * On first write, it page faults, its entry is changed to read-write, - * and on retry the write succeeds. - * - * We populate dirty_bitmap by looking for entries that have been - * switched to read-write. - */ - - p2m_lock(p2m); - - for ( i = 0, pfn = begin_pfn; pfn < begin_pfn + nr; i++, pfn++ ) - if ( !p2m_change_type_one(d, pfn, p2m_ram_rw, p2m_ram_logdirty) ) - dirty_bitmap[i >> 3] |= (1 << (i & 7)); - - p2m_unlock(p2m); - - guest_flush_tlb_mask(d, d->dirty_cpumask); -} -#endif - /* * Callers must supply log_dirty_ops for the log dirty code to call. This * function usually is invoked when paging is enabled. Check shadow_enable() -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:48:20 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:48:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068338.1432306 (Exim 4.92) (envelope-from ) id 1uiVK9-0005KG-3n; Sun, 03 Aug 2025 09:48:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068338.1432306; Sun, 03 Aug 2025 09:48:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVK9-0005K9-0J; Sun, 03 Aug 2025 09:48:13 +0000 Received: by outflank-mailman (input) for mailman id 1068338; Sun, 03 Aug 2025 09:48:12 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVK7-0005K3-QM for xen-devel@lists.xenproject.org; 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bh=L979/F3k7RovmtHHOlf03f4PubJLrDTXgd8cZ0e9Eqw=; b=njGnhzZpD/4LFtM53y2VKSzxAvG/e10czwTnEeeYZ00DI65H7ICw72TWiZBnxuDEbRmgFeblwSyRV8zq877UKkcwCQjc9kes6WGUsuVG/omYmWHfsSRFkpcZ2GXn6rklMH9E1PXJnqmXoMkOcbKNgGe/xfS/B0mgsFpMfN4YbFU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: , CC: , Penny Zheng , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD , Michal Orzel , "Julien Grall" , Stefano Stabellini , "Tim Deegan" , "Daniel P. Smith" , "Shawn Anastasio" , Tamas K Lengyel , Alexandru Isaila , "Petre Pircalabu" , Bertrand Marquis , Volodymyr Babchuk , Alistair Francis , Bob Eshleman , Connor Davis , "Oleksii Kurochko" , Christopher Clark , Dario Faggioli , "Juergen Gross" , George Dunlap , Nathan Studer , Stewart Hildebrand , "Meng Xu" , Rahul Singh Subject: [PATCH v1 00/25] Introduce CONFIG_DOMCTL Date: Sun, 3 Aug 2025 17:47:13 +0800 Message-ID: <20250803094738.3625269-1-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231A:EE_|SA1PR12MB7367:EE_ X-MS-Office365-Filtering-Correlation-Id: 171da079-ae70-4ada-63e3-08ddd272d6ff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013|7416014|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4YJLWg53YuXRRbHewNJp1/ay/aZTIRmTCfeBuTVt1o6jH5q/nskB3DJwHd0z?= =?us-ascii?Q?MQV6swaYV+Agd6MxNsy37pFZRd423m88CizRRFJ937NTCTJo9VhgE7PzFbAX?= =?us-ascii?Q?Jw5r+tQ5037ztVLpbRpw8TPExO4I/FGoZd3VlF5NtHmdurz6VUJBcCu6tPmV?= =?us-ascii?Q?hIHNsdEiAMdpRekc8+Bgzs7nMCg1puYNmYT/AINBGQB6DhIXvL7DLE/8qjDE?= =?us-ascii?Q?ilcJ2Tae2SCG/USDUR72Yc5jOmZchtrupucDRnG3wnxOyrelLXKWswK3aOu/?= =?us-ascii?Q?ps/YzSChlezuvA/iqDb3EaRGRa0FLG/LzSo4SvQc55mBMnbXCDq/pOk40f4V?= =?us-ascii?Q?iG5ztomHS+EP7aZGXP1I09GvFOVURiQzyA8cbotsMT2k+lNQKC+r6VfF6iHE?= =?us-ascii?Q?Zs2Ui09CKZapU1OkS74zRuU1eglt5DvyTT8Lu+od8bfVLZw5vY9we6mqTmAr?= =?us-ascii?Q?7VzmZhWQ+65a+xyHiq8FSidAeyrDPRNxvCr+7JJvTl6N3QqwOeY0CJ+KAqyv?= =?us-ascii?Q?QbzYTQunR5sX4O9pYgNJtum+TkzmZkKRn4q23vbny8fhE2BnWoxOV/1YTdo/?= =?us-ascii?Q?VL2UOuV5MLul3bnmPF4VFfurVhQmtHe0GHaowp7etP8JU0qCr9CB1qQMedPU?= =?us-ascii?Q?9aq1WGPb7Ckgkm2Ga8svlUrVupLlsat3AWUo5anLSS4YFKNyKeobWIm/Wv/U?= =?us-ascii?Q?QFgcU8MJIOIF5FZlpis/3j7KGv+fPSYaz6ADGRxN0NFNoMSQTyrnxZVxNljX?= =?us-ascii?Q?Z2+GR9pHsJnnfeyU9GYVhkAOz/lk9j5EwlXB4MiH+sbOjL0jcBaMdlYJpfa5?= =?us-ascii?Q?3P8C9Ad9jXv480h0AaF4N+0Tb7N2zeCYE04beKfsU+TAVuMZmXNX6jgaeYIT?= =?us-ascii?Q?R72NDa95ULeKsXDQ6f53FIJd3scMDpt8WwAZAE+/1k5Cuo/E4Z5GcVbiAo8g?= =?us-ascii?Q?8Rkc4w1DC1Q12ODUi4dnADtyodcwhp60gMVVUg61BipZv41QuxLooyo2h6t5?= =?us-ascii?Q?i4weDD1cI5XZ4Gah+uEW0qfZKaRI+w1ttL9qWoOmFVG6bC7IqdOgjszpxikX?= =?us-ascii?Q?5oqiTrG9qoPxalj21VUUAXvF+6PR+sVs7SUdP7XMt9wr6z4NRm7hPOVlKyfj?= =?us-ascii?Q?iPJadFAxqnHYk5DndHyTkaQuej4ct7e6wHev2F4xS6S6l5WXfUFXkWZ9ds+f?= =?us-ascii?Q?5Bax2S1O4L7d88AKGCcbeccNCrBd2EwzNTSJqzSJ5ZD9lVagqEq7uVpoQE3U?= =?us-ascii?Q?DEQnUl02UeAnhU6yLSHzpXwRnhaKdItIBsjl2XOoySk4M8NYnfQ+O4rMO7NN?= =?us-ascii?Q?LrqCWtW/MXrNPkV1wJqepaddcHzUsuXdHYNC04R6CaD7Bz2W3keQUPvq+uVk?= =?us-ascii?Q?/4fvdOSjSufpRYanMc07zUcWcsZ0M3NVd7ONeBaJvKnxsMMh/cEgaJi019Ns?= =?us-ascii?Q?Qpz9NbODRP8+AxFWZ1EynWvD+pyHl42FyKnz/T8DAT/9fkFTzEwhpdRgq4V7?= =?us-ascii?Q?da7DjE1yu6t7tEUW4vvi5zDOwve6uUClAWnS?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013)(7416014)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:03.0302 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 171da079-ae70-4ada-63e3-08ddd272d6ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7367 It can be beneficial for some dom0less systems to further reduce Xen footprint via disabling some hypercalls handling code, which may not to be used & required in such systems. Each hypercall has a separate option to keep configuration flexible. Options to disable hypercalls: - sysctl - domctl - hvm - physdev - platform This patch serie is only focusing on introducing CONFIG_DOMCTL. Different options will be covered in different patch serie. Features, like VM event, or paging log-dirty support, which fully rely on domctl op, will be wrapped with CONFIG_SYSCTL, to reduce Xen footprint as much as possible. It is derived from Stefano Stabellini's commit "xen: introduce kconfig options to disable hypercalls"( https://lore.kernel.org/xen-devel/20241219092917.3006174-1-Sergiy_Kibrik@epam.com) Penny Zheng (25): xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE xen/x86: consolidate vram tracking support xen/x86: complement PG_log_dirty wrapping xen: consolidate CONFIG_VM_EVENT xen: introduce CONFIG_DOMCTL xen/domctl: provide stub for domctl_lock_{acquire,release} xen/domctl: wrap around XEN_DOMCTL_pausedomain xen/domctl: wrap around XEN_DOMCTL_soft_reset xen/domctl: wrap around XEN_DOMCTL_destroydomain xen/domctl: wrap around XEN_DOMCTL_setnodeaffinity xen/domctl: wrap around XEN_DOMCTL_{getvcpuaffinity,setvcpuaffinity} xen/domctl: wrap around XEN_DOMCTL_scheduler_op xen/domctl: wrap around XEN_DOMCTL_getvcpucontext xen/domctl: wrap around XEN_DOMCTL_{irq_permission,iomem_permission} xen/domctl: wrap around XEN_DOMCTL_settimeoffset xen/domctl: wrap around XEN_DOMCTL_set_target xen: add stub for XEN_DOMCTL_getdomaininfo xen/domctl: wrap around XEN_DOMCTL_set_access_required xen: make CONFIG_VM_EVENT depend on DOMCTL xen/domctl: wrap around XEN_DOMCTL_set_virq_handler xen/domctl: wrap aound iommu-related domctl op xen/domctl: wrap around XEN_DOMCTL_{get,set}_paging_mempool_size xen/x86: make CONFIG_X86_PSR depend on SYSCTL || DOMCTL xen/domctl: wrap around arch-specific domctl op xen/domctl: wrap around domctl hypercall xen/arch/arm/arm32/Makefile | 2 +- xen/arch/arm/arm64/Makefile | 2 +- xen/arch/arm/domain.c | 5 ++ xen/arch/arm/include/asm/tee/tee.h | 2 + xen/arch/arm/mem_access.c | 2 + xen/arch/arm/mmu/p2m.c | 8 +++ xen/arch/arm/mpu/p2m.c | 2 + xen/arch/arm/tee/ffa.c | 4 ++ xen/arch/arm/tee/optee.c | 4 ++ xen/arch/arm/tee/tee.c | 2 + xen/arch/arm/time.c | 2 + xen/arch/ppc/stubs.c | 6 ++ xen/arch/riscv/stubs.c | 2 + xen/arch/x86/Kconfig | 1 + xen/arch/x86/Makefile | 4 +- xen/arch/x86/configs/pvshim_defconfig | 1 + xen/arch/x86/domain.c | 4 ++ xen/arch/x86/domctl.c | 4 ++ xen/arch/x86/emul-i8254.c | 2 + xen/arch/x86/gdbsx.c | 4 ++ xen/arch/x86/hvm/Makefile | 4 +- xen/arch/x86/hvm/hvm.c | 4 ++ xen/arch/x86/hvm/pmtimer.c | 2 + xen/arch/x86/hvm/save.c | 2 + xen/arch/x86/hvm/svm/svm.c | 8 +++ xen/arch/x86/hvm/vmx/vmx.c | 16 +++++ xen/arch/x86/include/asm/hvm/hvm.h | 22 +++++++ xen/arch/x86/include/asm/hvm/monitor.h | 65 ++++++++++++++++++++- xen/arch/x86/include/asm/hvm/vm_event.h | 4 ++ xen/arch/x86/include/asm/hypercall.h | 2 + xen/arch/x86/include/asm/mem_access.h | 9 +++ xen/arch/x86/include/asm/monitor.h | 15 +++++ xen/arch/x86/include/asm/p2m.h | 8 ++- xen/arch/x86/include/asm/paging.h | 34 +++++------ xen/arch/x86/mm/hap/hap.c | 38 ++++++++++++ xen/arch/x86/mm/mem_access.c | 2 + xen/arch/x86/mm/mem_paging.c | 2 + xen/arch/x86/mm/mem_sharing.c | 4 ++ xen/arch/x86/mm/p2m-pod.c | 2 + xen/arch/x86/mm/p2m.c | 2 + xen/arch/x86/mm/paging.c | 36 ++---------- xen/arch/x86/mm/shadow/common.c | 8 +++ xen/arch/x86/mm/shadow/none.c | 4 ++ xen/arch/x86/psr.c | 18 ------ xen/arch/x86/time.c | 2 + xen/common/Kconfig | 9 ++- xen/common/Makefile | 5 +- xen/common/argo.c | 2 + xen/common/device-tree/device-tree.c | 2 + xen/common/domain.c | 10 ++++ xen/common/event_channel.c | 2 + xen/common/grant_table.c | 2 + xen/common/sched/arinc653.c | 2 + xen/common/sched/core.c | 6 ++ xen/common/sched/credit.c | 4 ++ xen/common/sched/credit2.c | 4 ++ xen/common/sched/private.h | 4 ++ xen/common/sched/rt.c | 4 ++ xen/common/vm_event.c | 2 + xen/drivers/passthrough/amd/pci_amd_iommu.c | 8 +++ xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++ xen/drivers/passthrough/arm/smmu-v3.c | 4 ++ xen/drivers/passthrough/arm/smmu.c | 4 ++ xen/drivers/passthrough/device_tree.c | 6 ++ xen/drivers/passthrough/iommu.c | 2 + xen/drivers/passthrough/pci.c | 6 ++ xen/drivers/passthrough/vtd/iommu.c | 6 ++ xen/include/hypercall-defs.c | 10 +++- xen/include/xen/domain.h | 18 ++++-- xen/include/xen/mem_access.h | 36 +++++++++++- xen/include/xen/monitor.h | 8 ++- xen/include/xen/vm_event.h | 24 +++++++- xen/include/xsm/dummy.h | 2 + xen/include/xsm/xsm.h | 40 ++++++++++--- xen/lib/x86/Makefile | 2 +- xen/xsm/dummy.c | 16 ++++- xen/xsm/flask/hooks.c | 36 +++++++++--- 77 files changed, 550 insertions(+), 118 deletions(-) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:48:20 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:48:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068340.1432326 (Exim 4.92) (envelope-from ) id 1uiVKG-0005nd-Kw; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:10.5614 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 35a77a8c-7231-4743-9d25-08ddd272db7c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8182 In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and HVM=y results in hvm.c being built, but domctl.c not being built, which leaves a few functions, like domctl_lock_acquire/release() undefined, causing linking to fail. To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile /hypercall-defs section, with this adjustment, we also need to release redundant vnuma_destroy() stub definition and paging_domctl hypercall-defs from PV_SHIM_EXCLUSIVE guardian, to not break compilation Above change will leave dead code in the shim binary temporarily and will be fixed with the introduction of CONFIG_DOMCTL. Fixes: 568f806cba4c ("xen/x86: remove "depends on !PV_SHIM_EXCLUSIVE"") Reported-by: Jan Beulich Signed-off-by: Penny Zheng --- v1 -> v2: - remove paging_domctl hypercall-defs --- xen/arch/x86/Makefile | 2 +- xen/common/Makefile | 5 +---- xen/include/hypercall-defs.c | 6 +----- xen/include/xen/domain.h | 4 ---- 4 files changed, 3 insertions(+), 14 deletions(-) diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile index 5aab30a0c4..7676d7cdd8 100644 --- a/xen/arch/x86/Makefile +++ b/xen/arch/x86/Makefile @@ -28,6 +28,7 @@ obj-y += delay.o obj-y += desc.o obj-bin-y += dmi_scan.init.o obj-y += domain.o +obj-y += domctl.o obj-bin-y += dom0_build.init.o obj-y += domain_page.o obj-y += e820.o @@ -79,7 +80,6 @@ obj-y += vm_event.o obj-y += xstate.o ifneq ($(CONFIG_PV_SHIM_EXCLUSIVE),y) -obj-y += domctl.o obj-y += platform_hypercall.o obj-$(CONFIG_COMPAT) += x86_64/platform_hypercall.o endif diff --git a/xen/common/Makefile b/xen/common/Makefile index c316957fcb..756ddf52c3 100644 --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/ obj-$(CONFIG_IOREQ_SERVER) += dm.o obj-y += domain.o +obj-y += domctl.o obj-y += event_2l.o obj-y += event_channel.o obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o @@ -69,10 +70,6 @@ obj-bin-$(CONFIG_X86) += $(foreach n,decompress bunzip2 unxz unlzma lzo unlzo un obj-$(CONFIG_COMPAT) += $(addprefix compat/,domain.o memory.o multicall.o xlat.o) -ifneq ($(CONFIG_PV_SHIM_EXCLUSIVE),y) -obj-y += domctl.o -endif - extra-y := symbols-dummy.o obj-$(CONFIG_COVERAGE) += coverage/ diff --git a/xen/include/hypercall-defs.c b/xen/include/hypercall-defs.c index c1081d87a2..a2f2a7fa75 100644 --- a/xen/include/hypercall-defs.c +++ b/xen/include/hypercall-defs.c @@ -197,9 +197,9 @@ dm_op(domid_t domid, unsigned int nr_bufs, xen_dm_op_buf_t *bufs) #ifdef CONFIG_SYSCTL sysctl(xen_sysctl_t *u_sysctl) #endif -#ifndef CONFIG_PV_SHIM_EXCLUSIVE domctl(xen_domctl_t *u_domctl) paging_domctl_cont(xen_domctl_t *u_domctl) +#ifndef CONFIG_PV_SHIM_EXCLUSIVE platform_op(xen_platform_op_t *u_xenpf_op) #endif #ifdef CONFIG_HVM @@ -278,9 +278,7 @@ hvm_op do do do do do #ifdef CONFIG_SYSCTL sysctl do do do do do #endif -#ifndef CONFIG_PV_SHIM_EXCLUSIVE domctl do do do do do -#endif #ifdef CONFIG_KEXEC kexec_op compat do - - - #endif @@ -296,8 +294,6 @@ dm_op compat do compat do do hypfs_op do do do do do #endif mca do do - - - -#ifndef CONFIG_PV_SHIM_EXCLUSIVE paging_domctl_cont do do do do - -#endif #endif /* !CPPCHECK */ diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index e10baf2615..33dd90357c 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -182,11 +182,7 @@ struct vnuma_info { struct xen_vmemrange *vmemrange; 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Smith" Subject: [PATCH v1 03/25] xen/x86: complement PG_log_dirty wrapping Date: Sun, 3 Aug 2025 17:47:16 +0800 Message-ID: <20250803094738.3625269-4-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231A:EE_|CH1PPF6D0742E7B:EE_ X-MS-Office365-Filtering-Correlation-Id: 6067b92f-dc78-4a64-2d08-08ddd272dbcb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?GroV81B/IAcb3fGo5yeEWjymRA6wFRGfSON/lzd10fWY94pP8ivf4FVQNk7v?= =?us-ascii?Q?RSLxHCgeHtYYACwuWwdirdKSRBJDkhLSOgYeTJKlgw+iogTrAfI6FKzWrQ6A?= =?us-ascii?Q?jY9alHFnL9n+RgqEgniH1Q4dHDq7mWdLKKZnJEDXc+iFPdro1z5jngVboi11?= =?us-ascii?Q?gxHrRbK7YwIiqN0pFEj1wqY2xTeerBI6i2/64aHf5XtXqSx7HgfEszfCjMwl?= =?us-ascii?Q?V750CTQ1t0WN/C7PgU9qU+fiVrzMwP1N0DJ/cQHkwTF4MN9ZMXu5RYlhYtgB?= =?us-ascii?Q?4sn/X3lo5xgK94gSB5FJ4Bd9wSv4n+Qcir8IqtYx1warMPkWP+LppYJoC+ga?= =?us-ascii?Q?TZrQzzWAjQXibV9oo1uyDllNb2fBCURHmryBzl4eUri/UFJMRQ1PCEoyq640?= =?us-ascii?Q?A55Lu9NC1xL9YzPR6Ljbi7nSbVlI/Sifc8ZpvxSHW9xXxJQpPgajUEQu/3rq?= =?us-ascii?Q?QEJT8eZK/gYzoBh4SvHV0R92NlcJqbOxNJA+BbctzTe40WDRujVcB17mcTzI?= =?us-ascii?Q?zYGU6yNGhrZLPhFjI4ShOlduXctkAr1zA2n0+FbU9sIa1zYlsbzfm3nQs/P3?= =?us-ascii?Q?7Rr9YvCnrfJOIFwjORx3lZtKqwGcPb1tvrOGVV6FlPasc8k+5u/4JxKhpZPW?= =?us-ascii?Q?YY+3M4Q3VUXWzJdN8BskjX4aqtQ2di0O5YalcCfDH9nbq6YIFqCl652fZNcq?= =?us-ascii?Q?etv6Z+WDqLZXm345PwzDH46BFDCYxt9QEfGrtzzTTvbZT0UDVx7mKjg6y4Dg?= =?us-ascii?Q?y8X9uLfdIfjy1gl0RYs1SL3fUY5BFV31wzosATX9jBgCfnk5c/z+SYKYfpD4?= =?us-ascii?Q?U/cxZ8/cTJx5yplQWv9NqVbtRmTyjzkkALWAAfuMDxWGi0nhY4oDW8bFppd1?= =?us-ascii?Q?NVg7n1l85H/s+oZurMLzsVq/go6e4HFzLTlheBJQjfiXiGPaDKk/Eg4BEYn5?= =?us-ascii?Q?qcKNEAaPRxC3vGGMc6aqnBS+lV9vgMVD5eXghLgSBMqeYNHwivcv6aeiZF2g?= =?us-ascii?Q?rNwvsUa8OuKl4WbQkPOLBPQDXE4vZWuLyJFEDKpueEHGW1p/fuWXBqcJNbh0?= =?us-ascii?Q?h734kHmtKIr+4G+ML959skVAPLYQJi7DXroMeUwQu3hxFq0X7icRoosxv+zR?= =?us-ascii?Q?MqFtHmypAz0SDtHU8jaFLP5V7KiH9iH8jGhHAJYsGKhPmbrzLV4+IoLteYaH?= =?us-ascii?Q?h+6SohpXIU2oAChylHDHh6TewUlAu8afOp8E9dp0M3/3riSnZXco6tMzdnRo?= =?us-ascii?Q?ndyQK9ULtqYOHYdK/5I655RdiS/JPregkJv+IbJMcRGSF7rliCWeZJLaNoFT?= =?us-ascii?Q?6mcZn8Nq+vlPYM8t80yl2NFqx6ITBN7wIXEvT0esz6memQzNf9Ss/49vbHGG?= =?us-ascii?Q?iwKd8YRd5z6V2ZhgTS2tZ3m1arK/FkMzTQJehDBZp2Lptofy/SnGyrasIVR8?= =?us-ascii?Q?0vWLKmdJ5ypTId8ESSNNd0sMjz6pofCbczTQddcyttNK+HeJDD0NV5o4hFON?= =?us-ascii?Q?WYbXnws6s8y/XBJdBUQuaYEMCpSsPvpJJCp4?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:11.0770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6067b92f-dc78-4a64-2d08-08ddd272dbcb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF6D0742E7B We have PG_log_dirty flag to wrap codes about paging log-dirty support. The main entry is paging_domctl(), and tracking its call chain, the following functions needs wrapping too: - xsm_shadow_control - hvm_mapped_guest_frames_mark_dirty - hap_domctl - shadow_domctl - shadow_test_disable - shadow_one_bit_disable - shadow_test_enable - shadow_get_allocation - log_dirty_ops.enable - hap_enable_log_dirty - sh_enable_log_dirty - _toggle_log_dirty - log_dirty_ops.disable - hap_disable_log_dirty - sh_disable_log_dirty - log_dirty_ops.clean - hap_clean_dirty_bitmap - sh_clean_dirty_bitmap - _clean_dirty_bitmap Wrap paging_domctl hypercall-defs with PG_log_dirty and release PG_log_dirty from PV_SHIM_EXCLUSIVE, as PV_SHIM_EXCLUSIVE will be cleaned up in the future. Signed-off-by: Penny Zheng --- xen/arch/x86/domctl.c | 4 ++++ xen/arch/x86/hvm/hvm.c | 2 ++ xen/arch/x86/include/asm/hypercall.h | 2 ++ xen/arch/x86/include/asm/paging.h | 2 +- xen/arch/x86/mm/hap/hap.c | 6 ++++++ xen/arch/x86/mm/shadow/common.c | 8 ++++++++ xen/arch/x86/mm/shadow/none.c | 4 ++++ xen/include/hypercall-defs.c | 4 ++++ xen/include/xsm/xsm.h | 4 ++++ xen/xsm/dummy.c | 2 ++ xen/xsm/flask/hooks.c | 4 ++++ 11 files changed, 41 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 3044f706de..156c74e07a 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -213,10 +213,14 @@ long arch_do_domctl( { case XEN_DOMCTL_shadow_op: +#if PG_log_dirty ret = paging_domctl(d, &domctl->u.shadow_op, u_domctl, 0); if ( ret == -ERESTART ) return hypercall_create_continuation( __HYPERVISOR_paging_domctl_cont, "h", u_domctl); +#else + ret = -EOPNOTSUPP; +#endif /* PG_log_dirty */ copyback = true; break; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index cb8ecd050d..ea97815deb 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -2831,6 +2831,7 @@ void hvm_unmap_guest_frame(void *p, bool permanent) put_page(page); } +#if PG_log_dirty void hvm_mapped_guest_frames_mark_dirty(struct domain *d) { struct hvm_write_map *track; @@ -2840,6 +2841,7 @@ void hvm_mapped_guest_frames_mark_dirty(struct domain *d) paging_mark_dirty(d, page_to_mfn(track->page)); spin_unlock(&d->arch.hvm.write_map.lock); } +#endif /* PG_log_dirty */ static void *hvm_map_entry(unsigned long va, bool *writable) { diff --git a/xen/arch/x86/include/asm/hypercall.h b/xen/arch/x86/include/asm/hypercall.h index f6e9e2313b..fac93527ce 100644 --- a/xen/arch/x86/include/asm/hypercall.h +++ b/xen/arch/x86/include/asm/hypercall.h @@ -16,7 +16,9 @@ #include /* for do_mca */ #include +#if PG_log_dirty #define __HYPERVISOR_paging_domctl_cont __HYPERVISOR_arch_1 +#endif #ifdef CONFIG_PV void pv_hypercall(struct cpu_user_regs *regs); diff --git a/xen/arch/x86/include/asm/paging.h b/xen/arch/x86/include/asm/paging.h index 173a569610..956b83215c 100644 --- a/xen/arch/x86/include/asm/paging.h +++ b/xen/arch/x86/include/asm/paging.h @@ -55,7 +55,7 @@ #define PG_translate 0 #define PG_external 0 #endif -#if defined(CONFIG_HVM) || !defined(CONFIG_PV_SHIM_EXCLUSIVE) +#if defined(CONFIG_HVM) /* Enable log dirty mode */ #define PG_log_dirty (XEN_DOMCTL_SHADOW_ENABLE_LOG_DIRTY << PG_mode_shift) #else diff --git a/xen/arch/x86/mm/hap/hap.c b/xen/arch/x86/mm/hap/hap.c index 668a233923..ccbc9128dd 100644 --- a/xen/arch/x86/mm/hap/hap.c +++ b/xen/arch/x86/mm/hap/hap.c @@ -189,6 +189,7 @@ out: return rc; } +#if PG_log_dirty /************************************************/ /* HAP LOG DIRTY SUPPORT */ /************************************************/ @@ -254,6 +255,7 @@ static void cf_check hap_clean_dirty_bitmap(struct domain *d) p2m_change_entry_type_global(d, p2m_ram_rw, p2m_ram_logdirty); guest_flush_tlb_mask(d, d->dirty_cpumask); } +#endif /* PG_log_dirty */ /************************************************/ /* HAP SUPPORT FUNCTIONS */ @@ -468,9 +470,11 @@ static bool cf_check flush_tlb(const unsigned long *vcpu_bitmap); void hap_domain_init(struct domain *d) { static const struct log_dirty_ops hap_ops = { +#if PG_log_dirty .enable = hap_enable_log_dirty, .disable = hap_disable_log_dirty, .clean = hap_clean_dirty_bitmap, +#endif }; /* Use HAP logdirty mechanism. */ @@ -662,6 +666,7 @@ out: paging_unlock(d); } +#if PG_log_dirty int hap_domctl(struct domain *d, struct xen_domctl_shadow_op *sc, XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) { @@ -692,6 +697,7 @@ int hap_domctl(struct domain *d, struct xen_domctl_shadow_op *sc, return -EINVAL; } } +#endif /* PG_log_dirty */ static const struct paging_mode hap_paging_real_mode; static const struct paging_mode hap_paging_protected_mode; diff --git a/xen/arch/x86/mm/shadow/common.c b/xen/arch/x86/mm/shadow/common.c index 0176e33bc9..f678e7b149 100644 --- a/xen/arch/x86/mm/shadow/common.c +++ b/xen/arch/x86/mm/shadow/common.c @@ -69,9 +69,11 @@ const uint8_t sh_type_to_size[] = { DEFINE_PER_CPU(uint32_t,trace_shadow_path_flags); +#if PG_log_dirty static int cf_check sh_enable_log_dirty(struct domain *); static int cf_check sh_disable_log_dirty(struct domain *); static void cf_check sh_clean_dirty_bitmap(struct domain *); +#endif static void cf_check shadow_update_paging_modes(struct vcpu *); @@ -80,9 +82,11 @@ static void cf_check shadow_update_paging_modes(struct vcpu *); int shadow_domain_init(struct domain *d) { static const struct log_dirty_ops sh_ops = { +#if PG_log_dirty .enable = sh_enable_log_dirty, .disable = sh_disable_log_dirty, .clean = sh_clean_dirty_bitmap, +#endif }; INIT_PAGE_LIST_HEAD(&d->arch.paging.shadow.pinned_shadows); @@ -1414,6 +1418,7 @@ int shadow_set_allocation(struct domain *d, unsigned int pages, bool *preempted) return 0; } +#if PG_log_dirty /* Return the size of the shadow pool, rounded up to the nearest MB */ static unsigned int shadow_get_allocation(struct domain *d) { @@ -1422,6 +1427,7 @@ static unsigned int shadow_get_allocation(struct domain *d) return ((pg >> (20 - PAGE_SHIFT)) + ((pg & ((1 << (20 - PAGE_SHIFT)) - 1)) ? 1 : 0)); } +#endif /* PG_log_dirty */ /**************************************************************************/ /* Hash table for storing the guest->shadow mappings. @@ -2958,6 +2964,7 @@ static int shadow_one_bit_enable(struct domain *d, u32 mode) return 0; } +#if PG_log_dirty static int shadow_one_bit_disable(struct domain *d, u32 mode) /* Turn off a single shadow mode feature */ { @@ -3158,6 +3165,7 @@ int shadow_domctl(struct domain *d, } } +#endif /* PG_log_dirty */ /**************************************************************************/ /* Auditing shadow tables */ diff --git a/xen/arch/x86/mm/shadow/none.c b/xen/arch/x86/mm/shadow/none.c index 2a4005a795..6c6971b458 100644 --- a/xen/arch/x86/mm/shadow/none.c +++ b/xen/arch/x86/mm/shadow/none.c @@ -1,6 +1,7 @@ #include #include +#if PG_log_dirty static int cf_check _toggle_log_dirty(struct domain *d) { ASSERT(is_pv_domain(d)); @@ -11,6 +12,7 @@ static void cf_check _clean_dirty_bitmap(struct domain *d) { ASSERT(is_pv_domain(d)); } +#endif /* PG_log_dirty */ static void cf_check _update_paging_modes(struct vcpu *v) { @@ -21,9 +23,11 @@ int shadow_domain_init(struct domain *d) { /* For HVM set up pointers for safety, then fail. */ static const struct log_dirty_ops sh_none_ops = { +#if PG_log_dirty .enable = _toggle_log_dirty, .disable = _toggle_log_dirty, .clean = _clean_dirty_bitmap, +#endif }; paging_log_dirty_init(d, &sh_none_ops); diff --git a/xen/include/hypercall-defs.c b/xen/include/hypercall-defs.c index a2f2a7fa75..c70f745ac2 100644 --- a/xen/include/hypercall-defs.c +++ b/xen/include/hypercall-defs.c @@ -198,7 +198,9 @@ dm_op(domid_t domid, unsigned int nr_bufs, xen_dm_op_buf_t *bufs) sysctl(xen_sysctl_t *u_sysctl) #endif domctl(xen_domctl_t *u_domctl) +#if PG_log_dirty paging_domctl_cont(xen_domctl_t *u_domctl) +#endif #ifndef CONFIG_PV_SHIM_EXCLUSIVE platform_op(xen_platform_op_t *u_xenpf_op) #endif @@ -294,6 +296,8 @@ dm_op compat do compat do do hypfs_op do do do do do #endif mca do do - - - +#if PG_log_dirty paging_domctl_cont do do do do - +#endif #endif /* !CPPCHECK */ diff --git a/xen/include/xsm/xsm.h b/xen/include/xsm/xsm.h index 9a23d2827c..dad69905c9 100644 --- a/xen/include/xsm/xsm.h +++ b/xen/include/xsm/xsm.h @@ -173,7 +173,9 @@ struct xsm_ops { #ifdef CONFIG_X86 int (*do_mca)(void); +#if PG_log_dirty int (*shadow_control)(struct domain *d, uint32_t op); +#endif int (*mem_sharing_op)(struct domain *d, struct domain *cd, int op); int (*apic)(struct domain *d, int cmd); int (*machine_memory_map)(void); @@ -687,11 +689,13 @@ static inline int xsm_do_mca(xsm_default_t def) return alternative_call(xsm_ops.do_mca); } +#if PG_log_dirty static inline int xsm_shadow_control( xsm_default_t def, struct domain *d, uint32_t op) { return alternative_call(xsm_ops.shadow_control, d, op); } +#endif static inline int xsm_mem_sharing_op( xsm_default_t def, struct domain *d, struct domain *cd, int op) diff --git a/xen/xsm/dummy.c b/xen/xsm/dummy.c index 8b7e01b506..8a893c6eee 100644 --- a/xen/xsm/dummy.c +++ b/xen/xsm/dummy.c @@ -132,7 +132,9 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { .platform_op = xsm_platform_op, #ifdef CONFIG_X86 .do_mca = xsm_do_mca, +#if PG_log_dirty .shadow_control = xsm_shadow_control, +#endif .mem_sharing_op = xsm_mem_sharing_op, .apic = xsm_apic, .machine_memory_map = xsm_machine_memory_map, diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index b0308e1b26..0382182f94 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -1605,6 +1605,7 @@ static int cf_check flask_do_mca(void) return domain_has_xen(current->domain, XEN__MCA_OP); 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Futhermore, features about monitor_op and memory access are both based on vm event subsystem, so monitor.o/mem_access.o shall be wrapped under CONFIG_VM_EVENT. Although CONFIG_VM_EVENT is forcibly enabled on x86, we could disable it through disabling CONFIG_DOMCTL in the future. In consequence, a few functions, like the ones defined in hvm/monitor.h, needs stub to pass compilation when CONFIG_VM_EVENT=n. Remove the CONFIG_VM_EVENT wrapper for "#include ", as we need declaration there to pass compilation when CONFIG_VM_EVENT=n The following functions are developed on the basis of vm event framework, or only invoked by vm_event.c/monitor.c/mem_access.c, so they all shall be wrapped with CONFIG_VM_EVENT: - hvm_toggle_singlestep - hvm_fast_singlestep - p2m_mem_paging_drop_page - p2m_mem_paging_populate_page - p2m_mem_paging_resume - hvm_enable_msr_interception - hvm_function_table.enable_msr_interception - hvm_has_set_descriptor_access_existing - hvm_function_table.set_descriptor_access_existing - xsm_vm_event_control Signed-off-by: Penny Zheng --- xen/arch/ppc/stubs.c | 2 + xen/arch/x86/Makefile | 2 +- xen/arch/x86/hvm/Makefile | 4 +- xen/arch/x86/hvm/hvm.c | 2 + xen/arch/x86/hvm/svm/svm.c | 8 +++ xen/arch/x86/hvm/vmx/vmx.c | 10 ++++ xen/arch/x86/include/asm/hvm/hvm.h | 10 ++++ xen/arch/x86/include/asm/hvm/monitor.h | 65 ++++++++++++++++++++++++- xen/arch/x86/include/asm/hvm/vm_event.h | 4 ++ xen/arch/x86/include/asm/mem_access.h | 9 ++++ xen/arch/x86/include/asm/monitor.h | 15 ++++++ xen/arch/x86/include/asm/p2m.h | 6 +++ xen/arch/x86/mm/mem_paging.c | 2 + xen/include/xen/mem_access.h | 36 ++++++++++++-- xen/include/xen/monitor.h | 8 ++- xen/include/xen/vm_event.h | 24 ++++++++- xen/include/xsm/xsm.h | 4 +- xen/xsm/dummy.c | 2 +- xen/xsm/flask/hooks.c | 4 +- 19 files changed, 200 insertions(+), 17 deletions(-) diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c index 671e71aa0a..4679cf9360 100644 --- a/xen/arch/ppc/stubs.c +++ b/xen/arch/ppc/stubs.c @@ -60,6 +60,7 @@ void vcpu_show_execution_state(struct vcpu *v) BUG_ON("unimplemented"); } +#ifdef CONFIG_VM_EVENT /* vm_event.c */ void vm_event_fill_regs(vm_event_request_t *req) @@ -76,6 +77,7 @@ void vm_event_monitor_next_interrupt(struct vcpu *v) { /* Not supported on PPC. */ } +#endif /* CONFIG_VM_EVENT */ /* domctl.c */ void arch_get_domain_info(const struct domain *d, diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile index 7676d7cdd8..17f0e1dbc9 100644 --- a/xen/arch/x86/Makefile +++ b/xen/arch/x86/Makefile @@ -76,7 +76,7 @@ obj-y += usercopy.o obj-y += x86_emulate.o obj-$(CONFIG_TBOOT) += tboot.o obj-y += hpet.o -obj-y += vm_event.o +obj-$(CONFIG_VM_EVENT) += vm_event.o obj-y += xstate.o ifneq ($(CONFIG_PV_SHIM_EXCLUSIVE),y) diff --git a/xen/arch/x86/hvm/Makefile b/xen/arch/x86/hvm/Makefile index 6ec2c8f2db..952db00dd7 100644 --- a/xen/arch/x86/hvm/Makefile +++ b/xen/arch/x86/hvm/Makefile @@ -16,7 +16,7 @@ obj-y += io.o obj-y += ioreq.o obj-y += irq.o obj-y += mmio.o -obj-y += monitor.o +obj-$(CONFIG_VM_EVENT) += monitor.o obj-y += mtrr.o obj-y += nestedhvm.o obj-y += pmtimer.o @@ -26,7 +26,7 @@ obj-y += save.o obj-y += stdvga.o obj-y += vioapic.o obj-y += vlapic.o -obj-y += vm_event.o +obj-$(CONFIG_VM_EVENT) += vm_event.o obj-y += vmsi.o obj-y += vpic.o obj-y += vpt.o diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index ea97815deb..f464f401aa 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -5251,6 +5251,7 @@ int hvm_debug_op(struct vcpu *v, int32_t op) return rc; } +#ifdef CONFIG_VM_EVENT void hvm_toggle_singlestep(struct vcpu *v) { ASSERT(atomic_read(&v->pause_count)); @@ -5275,6 +5276,7 @@ void hvm_fast_singlestep(struct vcpu *v, uint16_t p2midx) v->arch.hvm.fast_single_step.enabled = true; v->arch.hvm.fast_single_step.p2midx = p2midx; } +#endif /* CONFIG_VM_EVENT */ /* * Segment caches in VMCB/VMCS are inconsistent about which bits are checked, diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index fce750ca1f..d71f499986 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -297,6 +297,7 @@ void svm_intercept_msr(struct vcpu *v, uint32_t msr, int flags) __clear_bit(msr * 2 + 1, msr_bit); } +#ifdef CONFIG_VM_EVENT static void cf_check svm_enable_msr_interception(struct domain *d, uint32_t msr) { struct vcpu *v; @@ -304,6 +305,7 @@ static void cf_check svm_enable_msr_interception(struct domain *d, uint32_t msr) for_each_vcpu ( d, v ) svm_intercept_msr(v, msr, MSR_INTERCEPT_WRITE); } +#endif /* CONFIG_VM_EVENT */ static void svm_save_dr(struct vcpu *v) { @@ -824,6 +826,7 @@ static void cf_check svm_set_rdtsc_exiting(struct vcpu *v, bool enable) vmcb_set_general2_intercepts(vmcb, general2_intercepts); } +#ifdef CONFIG_VM_EVENT static void cf_check svm_set_descriptor_access_exiting( struct vcpu *v, bool enable) { @@ -841,6 +844,7 @@ static void cf_check svm_set_descriptor_access_exiting( vmcb_set_general1_intercepts(vmcb, general1_intercepts); } +#endif /* CONFIG_VM_EVENT */ static unsigned int cf_check svm_get_insn_bytes(struct vcpu *v, uint8_t *buf) { @@ -2455,9 +2459,13 @@ static struct hvm_function_table __initdata_cf_clobber svm_function_table = { .fpu_dirty_intercept = svm_fpu_dirty_intercept, .msr_read_intercept = svm_msr_read_intercept, .msr_write_intercept = svm_msr_write_intercept, +#ifdef CONFIG_VM_EVENT .enable_msr_interception = svm_enable_msr_interception, +#endif .set_rdtsc_exiting = svm_set_rdtsc_exiting, +#ifdef CONFIG_VM_EVENT .set_descriptor_access_exiting = svm_set_descriptor_access_exiting, +#endif .get_insn_bytes = svm_get_insn_bytes, .nhvm_vcpu_initialise = nsvm_vcpu_initialise, diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index cb82d52ef0..9e4ad864fa 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1515,6 +1515,7 @@ static void cf_check vmx_set_rdtsc_exiting(struct vcpu *v, bool enable) vmx_vmcs_exit(v); } +#ifdef CONFIG_VM_EVENT static void cf_check vmx_set_descriptor_access_exiting( struct vcpu *v, bool enable) { @@ -1529,6 +1530,7 @@ static void cf_check vmx_set_descriptor_access_exiting( vmx_update_secondary_exec_control(v); vmx_vmcs_exit(v); } +#endif /* CONFIG_VM_EVENT */ static void cf_check vmx_init_hypercall_page(void *p) { @@ -2408,6 +2410,7 @@ static void cf_check vmx_handle_eoi(uint8_t vector, int isr) printk_once(XENLOG_WARNING "EOI for %02x but SVI=%02x\n", vector, old_svi); } +#ifdef CONFIG_VM_EVENT static void cf_check vmx_enable_msr_interception(struct domain *d, uint32_t msr) { struct vcpu *v; @@ -2415,6 +2418,7 @@ static void cf_check vmx_enable_msr_interception(struct domain *d, uint32_t msr) for_each_vcpu ( d, v ) vmx_set_msr_intercept(v, msr, VMX_MSR_W); } +#endif /* CONFIG_VM_EVENT */ static void cf_check vmx_vcpu_update_eptp(struct vcpu *v) { @@ -2862,7 +2866,9 @@ static struct hvm_function_table __initdata_cf_clobber vmx_function_table = { .nhvm_domain_relinquish_resources = nvmx_domain_relinquish_resources, .update_vlapic_mode = vmx_vlapic_msr_changed, .nhvm_hap_walk_L1_p2m = nvmx_hap_walk_L1_p2m, +#ifdef CONFIG_VM_EVENT .enable_msr_interception = vmx_enable_msr_interception, +#endif .altp2m_vcpu_update_p2m = vmx_vcpu_update_eptp, .altp2m_vcpu_update_vmfunc_ve = vmx_vcpu_update_vmfunc_ve, .altp2m_vcpu_emulate_ve = vmx_vcpu_emulate_ve, @@ -3068,9 +3074,11 @@ const struct hvm_function_table * __init start_vmx(void) vmx_function_table.caps.singlestep = cpu_has_monitor_trap_flag; +#ifdef CONFIG_VM_EVENT if ( cpu_has_vmx_dt_exiting ) vmx_function_table.set_descriptor_access_exiting = vmx_set_descriptor_access_exiting; +#endif /* * Do not enable EPT when (!cpu_has_vmx_pat), to prevent security hole @@ -3141,8 +3149,10 @@ void __init vmx_fill_funcs(void) if ( !cpu_has_xen_ibt ) return; +#ifdef CONFIG_VM_EVENT vmx_function_table.set_descriptor_access_exiting = vmx_set_descriptor_access_exiting; +#endif vmx_function_table.update_eoi_exit_bitmap = vmx_update_eoi_exit_bitmap; vmx_function_table.process_isr = vmx_process_isr; diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h index bf8bc2e100..bd53fcf155 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -191,7 +191,9 @@ struct hvm_function_table { void (*handle_cd)(struct vcpu *v, unsigned long value); void (*set_info_guest)(struct vcpu *v); void (*set_rdtsc_exiting)(struct vcpu *v, bool enable); +#ifdef CONFIG_VM_EVENT void (*set_descriptor_access_exiting)(struct vcpu *v, bool enable); +#endif /* Nested HVM */ int (*nhvm_vcpu_initialise)(struct vcpu *v); @@ -223,7 +225,9 @@ struct hvm_function_table { paddr_t *L1_gpa, unsigned int *page_order, uint8_t *p2m_acc, struct npfec npfec); +#ifdef CONFIG_VM_EVENT void (*enable_msr_interception)(struct domain *d, uint32_t msr); +#endif /* Alternate p2m */ void (*altp2m_vcpu_update_p2m)(struct vcpu *v); @@ -430,10 +434,12 @@ static inline bool using_svm(void) #define hvm_long_mode_active(v) (!!((v)->arch.hvm.guest_efer & EFER_LMA)) +#ifdef CONFIG_VM_EVENT static inline bool hvm_has_set_descriptor_access_exiting(void) { return hvm_funcs.set_descriptor_access_exiting; } +#endif /* CONFIG_VM_EVENT */ static inline void hvm_domain_creation_finished(struct domain *d) { @@ -680,10 +686,12 @@ static inline int nhvm_hap_walk_L1_p2m( v, L2_gpa, L1_gpa, page_order, p2m_acc, npfec); } +#ifdef CONFIG_VM_EVENT static inline void hvm_enable_msr_interception(struct domain *d, uint32_t msr) { alternative_vcall(hvm_funcs.enable_msr_interception, d, msr); } +#endif /* CONFIG_VM_EVENT */ static inline bool hvm_is_singlestep_supported(void) { @@ -923,10 +931,12 @@ static inline void hvm_inject_hw_exception(unsigned int vector, int errcode) ASSERT_UNREACHABLE(); } +#ifdef CONFIG_VM_EVENT static inline bool hvm_has_set_descriptor_access_exiting(void) { return false; } +#endif /* CONFIG_VM_EVENT */ static inline int hvm_vmtrace_control(struct vcpu *v, bool enable, bool reset) { diff --git a/xen/arch/x86/include/asm/hvm/monitor.h b/xen/arch/x86/include/asm/hvm/monitor.h index 02021be47b..561ca2e585 100644 --- a/xen/arch/x86/include/asm/hvm/monitor.h +++ b/xen/arch/x86/include/asm/hvm/monitor.h @@ -17,14 +17,16 @@ enum hvm_monitor_debug_type HVM_MONITOR_DEBUG_EXCEPTION, }; +#define hvm_monitor_crX(cr, new, old) \ + hvm_monitor_cr(VM_EVENT_X86_##cr, new, old) + +#ifdef CONFIG_VM_EVENT /* * Called for current VCPU on crX/MSR changes by guest. Bool return signals * whether emulation should be postponed. */ bool hvm_monitor_cr(unsigned int index, unsigned long value, unsigned long old); -#define hvm_monitor_crX(cr, new, old) \ - hvm_monitor_cr(VM_EVENT_X86_##cr, new, old) bool hvm_monitor_msr(unsigned int msr, uint64_t new_value, uint64_t old_value); void hvm_monitor_descriptor_access(uint64_t exit_info, uint64_t vmx_exit_qualification, @@ -45,6 +47,65 @@ int hvm_monitor_vmexit(unsigned long exit_reason, int hvm_monitor_io(unsigned int port, unsigned int bytes, bool in, bool str); +#else +static inline bool hvm_monitor_cr(unsigned int index, unsigned long value, + unsigned long old) +{ + return false; +} + +static inline bool hvm_monitor_msr(unsigned int msr, uint64_t new_value, + uint64_t old_value) +{ + return false; +} + +static inline void hvm_monitor_descriptor_access(uint64_t exit_info, + uint64_t vmx_exit_qualification, + uint8_t descriptor, bool is_write) {} + +static inline int hvm_monitor_debug(unsigned long rip, + enum hvm_monitor_debug_type type, + unsigned int trap_type, + unsigned int insn_length, + unsigned int pending_dbg) +{ + return -EOPNOTSUPP; +} + +static inline int hvm_monitor_cpuid(unsigned long insn_length, + unsigned int leaf, unsigned int subleaf) +{ + return -EOPNOTSUPP; +} + +static inline void hvm_monitor_interrupt(unsigned int vector, + unsigned int type, + unsigned int err, uint64_t cr2) {} + +static inline bool hvm_monitor_emul_unimplemented(void) +{ + return false; +} + +static inline bool hvm_monitor_check_p2m(unsigned long gla, gfn_t gfn, + uint32_t pfec, uint16_t kind) +{ + return false; +} + +static inline int hvm_monitor_vmexit(unsigned long exit_reason, + unsigned long exit_qualification) +{ + return -EOPNOTSUPP; +} + +static inline int hvm_monitor_io(unsigned int port, unsigned int bytes, + bool in, bool str) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_VM_EVENT */ #endif /* __ASM_X86_HVM_MONITOR_H__ */ diff --git a/xen/arch/x86/include/asm/hvm/vm_event.h b/xen/arch/x86/include/asm/hvm/vm_event.h index 506a85c774..1628230182 100644 --- a/xen/arch/x86/include/asm/hvm/vm_event.h +++ b/xen/arch/x86/include/asm/hvm/vm_event.h @@ -8,7 +8,11 @@ #ifndef __ASM_X86_HVM_VM_EVENT_H__ #define __ASM_X86_HVM_VM_EVENT_H__ +#ifdef CONFIG_VM_EVENT void hvm_vm_event_do_resume(struct vcpu *v); +#else +static inline void hvm_vm_event_do_resume(struct vcpu *v) {} +#endif /* CONFIG_VM_EVENT */ #endif /* __ASM_X86_HVM_VM_EVENT_H__ */ diff --git a/xen/arch/x86/include/asm/mem_access.h b/xen/arch/x86/include/asm/mem_access.h index 1a52a10322..c786116310 100644 --- a/xen/arch/x86/include/asm/mem_access.h +++ b/xen/arch/x86/include/asm/mem_access.h @@ -14,6 +14,7 @@ #ifndef __ASM_X86_MEM_ACCESS_H__ #define __ASM_X86_MEM_ACCESS_H__ +#ifdef CONFIG_VM_EVENT /* * Setup vm_event request based on the access (gla is -1ull if not available). * Handles the rw2rx conversion. Boolean return value indicates if event type @@ -25,6 +26,14 @@ bool p2m_mem_access_check(paddr_t gpa, unsigned long gla, struct npfec npfec, struct vm_event_st **req_ptr); +#else +static inline bool p2m_mem_access_check(paddr_t gpa, unsigned long gla, + struct npfec npfec, + struct vm_event_st **req_ptr) +{ + return false; +} +#endif /* CONFIG_VM_EVENT */ /* Check for emulation and mark vcpu for skipping one instruction * upon rescheduling if required. */ diff --git a/xen/arch/x86/include/asm/monitor.h b/xen/arch/x86/include/asm/monitor.h index 3c64d8258f..815de8fda2 100644 --- a/xen/arch/x86/include/asm/monitor.h +++ b/xen/arch/x86/include/asm/monitor.h @@ -71,6 +71,7 @@ int arch_monitor_domctl_op(struct domain *d, struct xen_domctl_monitor_op *mop) return rc; } +#ifdef CONFIG_VM_EVENT static inline uint32_t arch_monitor_get_capabilities(struct domain *d) { uint32_t capabilities = 0; @@ -102,6 +103,13 @@ static inline uint32_t arch_monitor_get_capabilities(struct domain *d) return capabilities; } +#else +static inline uint32_t arch_monitor_get_capabilities(struct domain *d) +{ + ASSERT_UNREACHABLE(); + return 0; +} +#endif /* CONFIG_VM_EVENT */ int arch_monitor_domctl_event(struct domain *d, struct xen_domctl_monitor_op *mop); @@ -123,7 +131,14 @@ static inline void arch_monitor_cleanup_domain(struct domain *d) {} #endif +#ifdef CONFIG_VM_EVENT bool monitored_msr(const struct domain *d, u32 msr); +#else +static inline bool monitored_msr(const struct domain *d, u32 msr) +{ + return false; +} +#endif bool monitored_msr_onchangeonly(const struct domain *d, u32 msr); #endif /* __ASM_X86_MONITOR_H__ */ diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h index 58b56e575e..9c92f67443 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -775,10 +775,16 @@ static inline int relinquish_p2m_mapping(struct domain *d) /* Modify p2m table for shared gfn */ int set_shared_p2m_entry(struct domain *d, unsigned long gfn, mfn_t mfn); +#ifdef CONFIG_VM_EVENT /* Tell xenpaging to drop a paged out frame */ void p2m_mem_paging_drop_page(struct domain *d, gfn_t gfn, p2m_type_t p2mt); /* Start populating a paged out frame */ void p2m_mem_paging_populate(struct domain *d, gfn_t gfn); +#else +static inline void p2m_mem_paging_drop_page(struct domain *d, gfn_t gfn, + p2m_type_t p2mt) {} +static inline void p2m_mem_paging_populate(struct domain *d, gfn_t gfn) {} +#endif /* CONFIG_VM_EVENT */ /* Resume normal operation (in case a domain was paused) */ struct vm_event_st; void p2m_mem_paging_resume(struct domain *d, struct vm_event_st *rsp); diff --git a/xen/arch/x86/mm/mem_paging.c b/xen/arch/x86/mm/mem_paging.c index ac8d34ffa0..636c0533b3 100644 --- a/xen/arch/x86/mm/mem_paging.c +++ b/xen/arch/x86/mm/mem_paging.c @@ -15,6 +15,7 @@ #include "mm-locks.h" +#ifdef CONFIG_VM_EVENT /* * p2m_mem_paging_drop_page - Tell pager to drop its reference to a paged page * @d: guest domain @@ -186,6 +187,7 @@ void p2m_mem_paging_resume(struct domain *d, vm_event_response_t *rsp) gfn_unlock(p2m, gfn, 0); } } +#endif /* CONFIG_VM_EVENT */ /* * nominate - Mark a guest page as to-be-paged-out diff --git a/xen/include/xen/mem_access.h b/xen/include/xen/mem_access.h index 4de651038d..e9aaa7b321 100644 --- a/xen/include/xen/mem_access.h +++ b/xen/include/xen/mem_access.h @@ -33,9 +33,7 @@ */ struct vm_event_st; -#ifdef CONFIG_VM_EVENT #include -#endif /* * Additional access types, which are used to further restrict @@ -73,6 +71,7 @@ typedef enum { /* NOTE: Assumed to be only 4 bits right now on x86. */ } p2m_access_t; +#ifdef CONFIG_VM_EVENT struct p2m_domain; bool xenmem_access_to_p2m_access(const struct p2m_domain *p2m, xenmem_access_t xaccess, @@ -99,10 +98,41 @@ long p2m_set_mem_access_multi(struct domain *d, int p2m_get_mem_access(struct domain *d, gfn_t gfn, xenmem_access_t *access, unsigned int altp2m_idx); -#ifdef CONFIG_VM_EVENT int mem_access_memop(unsigned long cmd, XEN_GUEST_HANDLE_PARAM(xen_mem_access_op_t) arg); #else +struct p2m_domain; +static inline bool xenmem_access_to_p2m_access(const struct p2m_domain *p2m, + xenmem_access_t xaccess, + p2m_access_t *paccess) +{ + return false; +} + +static inline long p2m_set_mem_access(struct domain *d, gfn_t gfn, uint32_t nr, + uint32_t start, uint32_t mask, + xenmem_access_t access, + unsigned int altp2m_idx) +{ + return -EOPNOTSUPP; +} + +static inline long p2m_set_mem_access_multi(struct domain *d, + const XEN_GUEST_HANDLE(const_uint64) pfn_list, + const XEN_GUEST_HANDLE(const_uint8) access_list, + uint32_t nr, uint32_t start, uint32_t mask, + unsigned int altp2m_idx) +{ + return -EOPNOTSUPP; +} + +static inline int p2m_get_mem_access(struct domain *d, gfn_t gfn, + xenmem_access_t *access, + unsigned int altp2m_idx) +{ + return -EOPNOTSUPP; +} + static inline int mem_access_memop(unsigned long cmd, XEN_GUEST_HANDLE_PARAM(xen_mem_access_op_t) arg) diff --git a/xen/include/xen/monitor.h b/xen/include/xen/monitor.h index c086c4390c..1b7984909e 100644 --- a/xen/include/xen/monitor.h +++ b/xen/include/xen/monitor.h @@ -30,6 +30,7 @@ struct xen_domctl_monitor_op; #ifdef CONFIG_VM_EVENT int monitor_domctl(struct domain *d, struct xen_domctl_monitor_op *mop); void monitor_guest_request(void); +int monitor_traps(struct vcpu *v, bool sync, vm_event_request_t *req); #else /* !CONFIG_VM_EVENT */ static inline int monitor_domctl(struct domain *d, struct xen_domctl_monitor_op *mop) @@ -37,8 +38,11 @@ static inline int monitor_domctl(struct domain *d, return -EOPNOTSUPP; } static inline void monitor_guest_request(void) {} +static inline int monitor_traps(struct vcpu *v, bool sync, + vm_event_request_t *req) +{ + return -EOPNOTSUPP; +} #endif /* !CONFIG_VM_EVENT */ -int monitor_traps(struct vcpu *v, bool sync, vm_event_request_t *req); - #endif /* __XEN_MONITOR_H__ */ diff --git a/xen/include/xen/vm_event.h b/xen/include/xen/vm_event.h index 27d0c74216..4b3d0d15ec 100644 --- a/xen/include/xen/vm_event.h +++ b/xen/include/xen/vm_event.h @@ -50,6 +50,7 @@ struct vm_event_domain unsigned int last_vcpu_wake_up; }; +#ifdef CONFIG_VM_EVENT /* Returns whether a ring has been set up */ bool vm_event_check_ring(struct vm_event_domain *ved); @@ -68,6 +69,20 @@ bool vm_event_check_ring(struct vm_event_domain *ved); */ int __vm_event_claim_slot(struct domain *d, struct vm_event_domain *ved, bool allow_sleep); +#else +static inline bool vm_event_check_ring(struct vm_event_domain *ved) +{ + return false; +} + +static inline int __vm_event_claim_slot(struct domain *d, + struct vm_event_domain *ved, + bool allow_sleep) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_VM_EVENT */ + static inline int vm_event_claim_slot(struct domain *d, struct vm_event_domain *ved) { @@ -82,23 +97,28 @@ static inline int vm_event_claim_slot_nosleep(struct domain *d, void vm_event_cancel_slot(struct domain *d, struct vm_event_domain *ved); +#ifdef CONFIG_VM_EVENT void vm_event_put_request(struct domain *d, struct vm_event_domain *ved, vm_event_request_t *req); -#ifdef CONFIG_VM_EVENT /* Clean up on domain destruction */ void vm_event_cleanup(struct domain *d); int vm_event_domctl(struct domain *d, struct xen_domctl_vm_event_op *vec); + +void vm_event_vcpu_pause(struct vcpu *v); #else /* !CONFIG_VM_EVENT */ +static inline void vm_event_put_request(struct domain *d, + struct vm_event_domain *ved, + vm_event_request_t *req) {} static inline void vm_event_cleanup(struct domain *d) {} static inline int vm_event_domctl(struct domain *d, struct xen_domctl_vm_event_op *vec) { return -EOPNOTSUPP; } +static inline void vm_event_vcpu_pause(struct vcpu *v) {}; #endif /* !CONFIG_VM_EVENT */ -void vm_event_vcpu_pause(struct vcpu *v); void vm_event_vcpu_unpause(struct vcpu *v); void vm_event_fill_regs(vm_event_request_t *req); diff --git a/xen/include/xsm/xsm.h b/xen/include/xsm/xsm.h index dad69905c9..7c61f27366 100644 --- a/xen/include/xsm/xsm.h +++ b/xen/include/xsm/xsm.h @@ -155,9 +155,9 @@ struct xsm_ops { int (*hvm_altp2mhvm_op)(struct domain *d, uint64_t mode, uint32_t op); int (*get_vnumainfo)(struct domain *d); +#ifdef CONFIG_VM_EVENT int (*vm_event_control)(struct domain *d, int mode, int op); -#ifdef CONFIG_VM_EVENT int (*mem_access)(struct domain *d); #endif @@ -651,13 +651,13 @@ static inline int xsm_get_vnumainfo(xsm_default_t def, struct domain *d) return alternative_call(xsm_ops.get_vnumainfo, d); } +#ifdef CONFIG_VM_EVENT static inline int xsm_vm_event_control( xsm_default_t def, struct domain *d, int mode, int op) { return alternative_call(xsm_ops.vm_event_control, d, mode, op); } -#ifdef CONFIG_VM_EVENT static inline int xsm_mem_access(xsm_default_t def, struct domain *d) { return alternative_call(xsm_ops.mem_access, d); diff --git a/xen/xsm/dummy.c b/xen/xsm/dummy.c index 8a893c6eee..6f8b06b45f 100644 --- a/xen/xsm/dummy.c +++ b/xen/xsm/dummy.c @@ -115,9 +115,9 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { .remove_from_physmap = xsm_remove_from_physmap, .map_gmfn_foreign = xsm_map_gmfn_foreign, +#ifdef CONFIG_VM_EVENT .vm_event_control = xsm_vm_event_control, -#ifdef CONFIG_VM_EVENT .mem_access = xsm_mem_access, #endif diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index 0382182f94..fd7aea460f 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -1365,12 +1365,12 @@ static int cf_check flask_hvm_altp2mhvm_op(struct domain *d, uint64_t mode, uint return current_has_perm(d, SECCLASS_HVM, HVM__ALTP2MHVM_OP); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:16.2300 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0720f6ed-de54-471a-7313-08ddd272dedd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002319.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9128 We introduce a new Kconfig CONFIG_DOMCTL, which shall only be disabled on some dom0less systems or PV shim on x86, to reduce Xen footprint. Making DOMCTL without prompt is transient and it will be adjusted in the final patch. And the consequence of introducing "CONFIG_DOMCTL=y" in .config file generated from pvshim_defconfig is transient too, which will also be adjusted in the final patch. Signed-off-by: Penny Zheng --- xen/common/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 16936418a6..bf1850c154 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -627,6 +627,10 @@ config SYSCTL This option shall only be disabled on some dom0less systems, or PV shim on x86, to reduce Xen footprint. +config DOMCTL + bool "Enable domctl hypercall" + def_bool y + endmenu config PM_OP -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:48:29 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:48:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068346.1432366 (Exim 4.92) (envelope-from ) id 1uiVKP-0006vx-1r; Sun, 03 Aug 2025 09:48:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068346.1432366; Sun, 03 Aug 2025 09:48:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVKO-0006vo-U0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:21.1703 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c85368e-2432-4eb3-949a-08ddd272e1cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6359 Function domain_pause_by_systemcontroller() is responsible for XEN_DOMCTL_pausedomain domctl-op, and shall be wrapped around with CONFIG_DOMCTL Signed-off-by: Penny Zheng --- xen/common/domain.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/common/domain.c b/xen/common/domain.c index 5241a1629e..e20fe2d40d 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1598,10 +1598,12 @@ static int _domain_pause_by_systemcontroller(struct domain *d, bool sync) return 0; } +#ifdef CONFIG_DOMCTL int domain_pause_by_systemcontroller(struct domain *d) { return _domain_pause_by_systemcontroller(d, true /* sync */); } +#endif /* CONFIG_DOMCTL */ int domain_pause_by_systemcontroller_nosync(struct domain *d) { -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:48:34 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:48:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068351.1432376 (Exim 4.92) (envelope-from ) id 1uiVKU-0007VB-CL; Sun, 03 Aug 2025 09:48:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068351.1432376; Sun, 03 Aug 2025 09:48:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVKU-0007V4-85; Sun, 03 Aug 2025 09:48:34 +0000 Received: by outflank-mailman (input) for mailman id 1068351; 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Smith" Subject: [PATCH v1 08/25] xen/domctl: wrap around XEN_DOMCTL_soft_reset Date: Sun, 3 Aug 2025 17:47:21 +0800 Message-ID: <20250803094738.3625269-9-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231D:EE_|SA3PR12MB8024:EE_ X-MS-Office365-Filtering-Correlation-Id: c41198b9-fa94-47c1-1fc6-08ddd272e49b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?lc86eHYoW09r0dyZphhLENMnVqVA+CisEPrttuaXqLPeO7O2mqMstB/S3PDf?= =?us-ascii?Q?JKfsofuMToHB1c0DR4bEiSgIbGWSe+Pfrr+X2Ye/RnFHKa76zT8Dnw1a0tOb?= =?us-ascii?Q?SAspPuPwQBC1KbX3Zj9Y3gZ5tD8VbuQpBQaZGD4CN0odNlAFD4Je/kgripmZ?= =?us-ascii?Q?0KWHMgH28QXXJ/b0AnaKxr6XnUzMUbtpiVzfGgqMJdTkE7G1Y931ZN1h8ka0?= =?us-ascii?Q?6xZe3Nver8QBDtpWmBW/fBikSNDo3bA1gLdUKYBw2mnL+f6l/iKhIbGlMJDF?= =?us-ascii?Q?LDh6nBeiqHefeX52+YHq/kiWrE+ORtC1DLWKhK38Xz3PEv3N8xgsdK08k7JG?= =?us-ascii?Q?82g+KzMou5+FBzuROWbeNPoSVYIDC6ZLTXTCkFRzDHt0fOCR/eDin0u1VQDZ?= =?us-ascii?Q?agEzVvtSVqFwST1kR5D+62sutCru5T9T5RmaJpcGR2WPGQqnbJEFysqQhAGe?= =?us-ascii?Q?UkImvgyRh8l3Mi/2dzQ748UUjLR6MgkSJ2Qw2Z9MDK9k8zwOHV2ZTG2XSn5W?= =?us-ascii?Q?+qiu8Z5CPbLqefxpDxwRf/qiwrPOmNeIF3yRMZnll1niamqPKoLIDopBVmRu?= =?us-ascii?Q?MgDGBbWJQbezn92uqqdU1FEqyyarm798F25mE1HQ/oxNKnkftablYV4l5Khq?= =?us-ascii?Q?sM3I1dH7ITwrOLT5q0SzJ5difjtg1HowepwXy7aEfAvAuLnYpiR/Bgg+7KmK?= =?us-ascii?Q?dH4UPjfYr+3326dv3pPvVe21nEF4d2EJgPW47VWRnCtCfAwvwr5CxvSnXgW5?= =?us-ascii?Q?GFSJC1dpZyhMeRTwsZmg6hhKHKeuMwbSxY+T07Pc2Np8Pr83jCF8Av36AKmf?= =?us-ascii?Q?gCGF9s6vQRSfGKTLwvihQZc2BmCCr3DjKI2BPX0CGm5H18yh7sQggIMHuZLO?= =?us-ascii?Q?QWhdPVhtKFefZqcPpWQBdP4WYmNBf2Pe3Oj93PTBbLunZ3zueKpl3a2fid2/?= =?us-ascii?Q?/2wgRTwvvF89GCqntaoLWSKUcLqj4Jhc7PxNonOE5D1/DMxWcPuUQp2ZKXXJ?= =?us-ascii?Q?VIVV1Er0lIQtbotcigZCk/2at+HSNTG4I+RYnOabmZvBf63WTVf0YnfeWiv+?= =?us-ascii?Q?cdSmyjE/s4QO2btcYDXtK2rpqHQEWUizkD7LikGv4geuhTv707KtlrvkY8kA?= =?us-ascii?Q?ScFaW/LUPZdy16/OHABEuy0tBl9DMGI3xOtirP4Z1cGIvRmy/3e4WflVfWGL?= =?us-ascii?Q?1s9IemuxvR9Q+wvGcoJgrGKSAaotJ4yYD5TvkfX3LjRHu5ZA3aqnBebqi6dz?= =?us-ascii?Q?9Nt+UDZ7dZ4Mqjsb3tUu40R2uwsF40R82ZxxV667UbYF8e/0Nl6z+ijTlevU?= =?us-ascii?Q?cGdLB4WF4QlQvT+t4eWc08VsIVVI0/A2jUeayyBvxH147bvtZdVAdFrc/GqS?= =?us-ascii?Q?Sib1G/BpWjGndmf4dAvh3ThfuyfRhMsP8Mw9pKVikwhN0U9sZ65EufIK9+6/?= =?us-ascii?Q?o6hzjEso9AKWnJQdLUo6ymzS9In0DNuTU8PaudJBmbcnLWyMDHPlxIrnpDUE?= =?us-ascii?Q?kh/wZwjUQOnloZXtsW9An+/fPtiZ+1OYdFFy?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:25.8604 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c41198b9-fa94-47c1-1fc6-08ddd272e49b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8024 Function domain_soft_reset() is responsible for domain soft reset, tracking its calling chain, and the following functions could also be wrapped: - grant_table_warn_active_grants() - argo_soft_reset() - arch_domain_soft_reset() - domain_resume(), another usage is in XEN_DOMCTL_resumedomain domctl-op. Signed-off-by: Penny Zheng --- xen/arch/arm/domain.c | 2 ++ xen/arch/ppc/stubs.c | 2 ++ xen/arch/riscv/stubs.c | 2 ++ xen/arch/x86/domain.c | 2 ++ xen/common/argo.c | 2 ++ xen/common/domain.c | 4 ++++ xen/common/grant_table.c | 2 ++ 7 files changed, 16 insertions(+) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 310c578909..4124d201d1 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -870,10 +870,12 @@ void arch_domain_unpause(struct domain *d) { } +#ifdef CONFIG_DOMCTL int arch_domain_soft_reset(struct domain *d) { return -ENOSYS; } +#endif /* CONFIG_DOMCTL */ void arch_domain_creation_finished(struct domain *d) { diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c index 4679cf9360..b2b97c6eb7 100644 --- a/xen/arch/ppc/stubs.c +++ b/xen/arch/ppc/stubs.c @@ -236,10 +236,12 @@ void arch_domain_unpause(struct domain *d) BUG_ON("unimplemented"); } +#ifdef CONFIG_DOMCTL int arch_domain_soft_reset(struct domain *d) { BUG_ON("unimplemented"); } +#endif /* CONFIG_DOMCTL */ void arch_domain_creation_finished(struct domain *d) { diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 8918cebf35..4f817bfe83 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -208,10 +208,12 @@ void arch_domain_unpause(struct domain *d) BUG_ON("unimplemented"); } +#ifdef CONFIG_DOMCTL int arch_domain_soft_reset(struct domain *d) { BUG_ON("unimplemented"); } +#endif /* CONFIG_DOMCTL */ void arch_domain_creation_finished(struct domain *d) { diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 56c3816187..13ccaf1c79 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1001,6 +1001,7 @@ void arch_domain_unpause(struct domain *d) viridian_time_domain_thaw(d); } +#ifdef CONFIG_DOMCTL int arch_domain_soft_reset(struct domain *d) { struct page_info *page = virt_to_page(d->shared_info), *new_page; @@ -1102,6 +1103,7 @@ int arch_domain_soft_reset(struct domain *d) return ret; } +#endif /* CONFIG_DOMCTL */ void arch_domain_creation_finished(struct domain *d) { diff --git a/xen/common/argo.c b/xen/common/argo.c index cbe8911a43..932f9fde9b 100644 --- a/xen/common/argo.c +++ b/xen/common/argo.c @@ -2351,6 +2351,7 @@ argo_destroy(struct domain *d) write_unlock(&L1_global_argo_rwlock); } +#ifdef CONFIG_DOMCTL void argo_soft_reset(struct domain *d) { @@ -2374,3 +2375,4 @@ argo_soft_reset(struct domain *d) write_unlock(&L1_global_argo_rwlock); } +#endif /* CONFIG_DOMCTL */ diff --git a/xen/common/domain.c b/xen/common/domain.c index e20fe2d40d..604217d782 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1343,6 +1343,7 @@ int domain_shutdown(struct domain *d, u8 reason) return 0; } +#ifdef CONFIG_DOMCTL void domain_resume(struct domain *d) { struct vcpu *v; @@ -1369,6 +1370,7 @@ void domain_resume(struct domain *d) domain_unpause(d); } +#endif /* CONFIG_DOMCTL */ int vcpu_start_shutdown_deferral(struct vcpu *v) { @@ -1681,6 +1683,7 @@ void domain_unpause_except_self(struct domain *d) domain_unpause(d); } +#ifdef CONFIG_DOMCTL int domain_soft_reset(struct domain *d, bool resuming) { struct vcpu *v; @@ -1718,6 +1721,7 @@ int domain_soft_reset(struct domain *d, bool resuming) return rc; } +#endif /* CONFIG_DOMCTL */ int vcpu_reset(struct vcpu *v) { diff --git a/xen/common/grant_table.c b/xen/common/grant_table.c index cf131c43a1..bfb199be7f 100644 --- a/xen/common/grant_table.c +++ b/xen/common/grant_table.c @@ -3962,6 +3962,7 @@ int gnttab_release_mappings(struct domain *d) return 0; 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wXQ8n/zXbOYYZx6IWWGU89i8B3eWN2TJh2dK9/CAeFE=; b=Xk3rjwf9HNbGvpc5j9yZT/OW+k8c3wJWhn7uBlc32SDtiqD37Mvt7/8fsOStjKzJGUOnDuStwVN39s0bYZyPEuO1NyyyrrVhxohfJerjYYPcp6oZCkEdi1TmawDxWFC5W2QAlLHqt69V+Wkh10BhzRF/5SSuHujrRD9rDv++tFU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: CC: , Penny Zheng , Dario Faggioli , Juergen Gross , George Dunlap Subject: [PATCH v1 11/25] xen/domctl: wrap around XEN_DOMCTL_{getvcpuaffinity,setvcpuaffinity} Date: Sun, 3 Aug 2025 17:47:24 +0800 Message-ID: <20250803094738.3625269-12-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231B:EE_|DM4PR12MB5964:EE_ X-MS-Office365-Filtering-Correlation-Id: 95377582-44af-4d9d-2faa-08ddd272e9ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:34.5839 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95377582-44af-4d9d-2faa-08ddd272e9ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5964 Function vcpu_affinity_domctl() is responsible for XEN_DOMCTL_{getvcpuaffinity,setvcpuaffinity} domctl-op, tracking its calling chain, the following function shall be wrapped too: - vcpu_set_soft_affinity Signed-off-by: Penny Zheng --- xen/common/sched/core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c index 2ab4313517..14f27fe70f 100644 --- a/xen/common/sched/core.c +++ b/xen/common/sched/core.c @@ -1402,10 +1402,12 @@ int vcpu_set_hard_affinity(struct vcpu *v, const cpumask_t *affinity) return vcpu_set_affinity(v, affinity, v->sched_unit->cpu_hard_affinity); } +#ifdef CONFIG_DOMCTL static int vcpu_set_soft_affinity(struct vcpu *v, const cpumask_t *affinity) { return vcpu_set_affinity(v, affinity, v->sched_unit->cpu_soft_affinity); } +#endif /* CONFIG_DOMCTL */ /* Block the currently-executing domain until a pertinent event occurs. */ void vcpu_block(void) @@ -1693,6 +1695,7 @@ int vcpuaffinity_params_invalid(const struct xen_domctl_vcpuaffinity *vcpuaff) guest_handle_is_null(vcpuaff->cpumap_soft.bitmap)); } +#ifdef CONFIG_DOMCTL int vcpu_affinity_domctl(struct domain *d, uint32_t cmd, struct xen_domctl_vcpuaffinity *vcpuaff) { @@ -1802,6 +1805,7 @@ int vcpu_affinity_domctl(struct domain *d, uint32_t cmd, return ret; } +#endif /* CONFIG_DOMCTL */ bool alloc_affinity_masks(struct affinity_masks *affinity) { -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:43 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068378.1432396 (Exim 4.92) (envelope-from ) id 1uiVMY-0002eu-CL; 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Signed-off-by: Penny Zheng --- xen/arch/arm/time.c | 2 ++ xen/arch/x86/time.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index e74d30d258..5955c7ce7a 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -365,12 +365,14 @@ void force_update_vcpu_system_time(struct vcpu *v) update_vcpu_system_time(v); } +#ifdef CONFIG_DOMCTL void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) { d->time_offset.seconds = time_offset_seconds; d->time_offset.set = true; /* XXX update guest visible wallclock time */ } +#endif /* CONFIG_DOMCTL */ static int cpu_time_callback(struct notifier_block *nfb, unsigned long action, diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c index 59129f419d..c1411be64e 100644 --- a/xen/arch/x86/time.c +++ b/xen/arch/x86/time.c @@ -1841,6 +1841,7 @@ static void update_domain_rtc(void) rcu_read_unlock(&domlist_read_lock); } +#ifdef CONFIG_DOMCTL void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) { d->time_offset.seconds = time_offset_seconds; @@ -1849,6 +1850,7 @@ void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) rtc_update_clock(d); update_domain_wallclock_time(d); } +#endif /* CONFIG_DOMCTL */ int cpu_frequency_change(u64 freq) { -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:43 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068382.1432405 (Exim 4.92) (envelope-from ) id 1uiVMZ-0002vq-KU; Sun, 03 Aug 2025 09:50:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068382.1432405; Sun, 03 Aug 2025 09:50:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVMZ-0002vh-FY; Sun, 03 Aug 2025 09:50:43 +0000 Received: by outflank-mailman (input) for mailman id 1068382; Sun, 03 Aug 2025 09:50:41 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVL5-0005hH-Qs for xen-devel@lists.xenproject.org; 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Smith" Subject: [PATCH v1 21/25] xen/domctl: wrap aound iommu-related domctl op Date: Sun, 3 Aug 2025 17:47:34 +0800 Message-ID: <20250803094738.3625269-22-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|SN7PR12MB7955:EE_ X-MS-Office365-Filtering-Correlation-Id: ac684bfe-09c0-41be-a548-08ddd272fa15 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KHceauyZxcgm2bK8ulWb2JJl9+GXas0OdWpBYnlXamuFD7iirxGYCVrB9qlz?= =?us-ascii?Q?aeaLEjomBZBRlD5OiQisKTAMiDnDymZwmfXbtvke68sn9rzIEWSrUKU/Agkz?= =?us-ascii?Q?xUPyFOb7rwD0+YB71v9f6WhQ1kXCANJGGmyqtPfPGizXkoOYU4jXFf21+ifw?= =?us-ascii?Q?b+PHkoyAS8YhSVLChX//roN23Awoz8DP2Vm77qYCx8pdR7Bd2+toItsGVTLB?= =?us-ascii?Q?n4thALLsvOJMosGS1LbwqoqvVmP5ZZHccm3md7ePhfpOE/g0Y8jhWOT/rT8U?= =?us-ascii?Q?1MxDa/cbzs2VpORA8wV6zFOKahvRJ/HH8YHrYgrCbHWfaIQvKdHmaRd/sMMz?= =?us-ascii?Q?e0mH4bA9+7VEus2fls3hqOIIADwnyCW4N8KqFWPHZyWDpvFf4CIK7G+Ro24K?= =?us-ascii?Q?lHnsp/2zwAXXB3kg/6h57ggSEiN1wiMkWx5nEQxB448YBDaWgL5tQtzuEMdy?= =?us-ascii?Q?1H+c2kQbOkeUshh6ppRoNfSMPWnjzlFI/gj5Qmo74NhTL6mw6yR1NwkQzU7T?= =?us-ascii?Q?Ygmd55jK48oDOnvHF2RQ3rqiT/3V2CVk8C3pqLgeGQUZpdMYFhLjNp7Qx+IC?= =?us-ascii?Q?MYtzJS0TGck42uyr1uzmuP10jMjRukWDT03m3MtiopXacPz5d/yTBTEEysOm?= =?us-ascii?Q?rvUF2isIspAN29ADeiujoRGVY2qUlLgzka8oDtDUlt6XrKUBqU9HxZY/pvfJ?= =?us-ascii?Q?3SJ1PtfChbDszFlFC/T5OjuqJBVtTNSU+L1qzLLaemswEHm8WcdprnqBhY1x?= =?us-ascii?Q?wb8/kursSYN+Saadgn7HsBsjbxgAgTpvQ5/lnM5xb3BG0PWNJe0wVDqbLC0R?= =?us-ascii?Q?aw5AsDOW/maGzArG7LYFIF0raiUt4v5KiK9G7gq13ikGI6V+7eu574M+DBEl?= =?us-ascii?Q?t9yO+l0KTmJ/FVu0sd5nsu456b7jJCcY0mYOgw5P52hKpdQ6L+fAQ5JpSo+9?= =?us-ascii?Q?MeNPZH95pdrM0mWiKgOnEgTWOL7J8qrvgDj3sI49NT9XiSVpkdYkp4ji/wv1?= =?us-ascii?Q?aRh9oiPt3Xm7WYH4mUKxdVR27Z5qQkwdGluCL0/uRguK90iUQZcUR5GqPIQN?= =?us-ascii?Q?uafnqJudFefq3oP1jPo2pAPt9/+IC9beB3EGIa9wOW5o88bijjzIWcOp71ER?= =?us-ascii?Q?kht4HEPTkLyxeifqAJBW/+Ce00CFwfVfusPyLzfF9dSm19wm/vnHSxJ28j08?= =?us-ascii?Q?Ju7LbFYBDiToRugx5GLG/qSe/n6qPizdAB6/04jsyNW80tSG0by21AIPgjzC?= =?us-ascii?Q?vmKbyvkFBgo33Wjr7eY+95vMRg2jzuJAZUWCSBx19yNiK4tLoOluEDzIzW/0?= =?us-ascii?Q?p9Ll1uw0o9iCqcZUXOcW7w025DzEKeIxQ4iWk4Z2FJIkUpAuXmlIAqWSkgYS?= =?us-ascii?Q?Uo2jg9N8vqva1u0mB+w9mNegKhoo5oBVIajP9rRj5ixMfMO8rkSa6WBdBhHg?= =?us-ascii?Q?6hkU1jmGCjgf9nZyDyTSHPefur0bzQoEI3JwfuOAcVoJyGZp3hJgFFVF+JHH?= =?us-ascii?Q?kQjWm67A2OYU92nbfkHTuONlwIU3aGKL3j4Z?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:49:01.8960 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac684bfe-09c0-41be-a548-08ddd272fa15 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7955 Function iommu_do_domctl() is the main entry for all iommu-related domctl-op. Tracking its calling chaining, the following functions shall all be wrapped: - iommu_do_pci_domctl - xsm_get_device_group - iommu_get_device_group - amd_iommu_group_id/intel_iommu_group_id - xsm_assign_device - device_assigned - assign_device - intel_iommu_assign_device/amd_iommu_assign_devic - xsm_deassign_device - deassign_device - reassign_device_ownership/reassign_device - iommu_do_dt_domctl - xsm_assign_dtdevice - xsm_deassign_dtdevice - iommu_deassign_dt_device - arm_smmu_reassign_dev/arm_smmu_reassign_dev - ipmmu_reassign_dev - ipmmu_deassign_dev - ipmmu_detach_dev - dt_find_node_by_gpath Signed-off-by: Penny Zheng --- xen/common/device-tree/device-tree.c | 2 ++ xen/drivers/passthrough/amd/pci_amd_iommu.c | 8 ++++++++ xen/drivers/passthrough/arm/ipmmu-vmsa.c | 6 ++++++ xen/drivers/passthrough/arm/smmu-v3.c | 4 ++++ xen/drivers/passthrough/arm/smmu.c | 4 ++++ xen/drivers/passthrough/device_tree.c | 4 ++++ xen/drivers/passthrough/iommu.c | 2 ++ xen/drivers/passthrough/pci.c | 6 +++++- xen/drivers/passthrough/vtd/iommu.c | 6 ++++++ xen/include/xsm/xsm.h | 12 ++++++------ xen/xsm/dummy.c | 4 ++-- xen/xsm/flask/hooks.c | 12 ++++++------ 12 files changed, 55 insertions(+), 15 deletions(-) diff --git a/xen/common/device-tree/device-tree.c b/xen/common/device-tree/device-tree.c index 0b5375f151..4ce6dce2ea 100644 --- a/xen/common/device-tree/device-tree.c +++ b/xen/common/device-tree/device-tree.c @@ -371,6 +371,7 @@ struct dt_device_node *dt_find_node_by_path_from(struct dt_device_node *from, return np; } +#ifdef CONFIG_DOMCTL int dt_find_node_by_gpath(XEN_GUEST_HANDLE(char) u_path, uint32_t u_plen, struct dt_device_node **node) { @@ -386,6 +387,7 @@ int dt_find_node_by_gpath(XEN_GUEST_HANDLE(char) u_path, uint32_t u_plen, return (*node == NULL) ? -ESRCH : 0; } +#endif /* CONFIG_DOMCTL */ struct dt_device_node *dt_find_node_by_alias(const char *alias) { diff --git a/xen/drivers/passthrough/amd/pci_amd_iommu.c b/xen/drivers/passthrough/amd/pci_amd_iommu.c index 3a14770855..869d2bc3a2 100644 --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c @@ -461,6 +461,7 @@ static void amd_iommu_disable_domain_device(const struct domain *domain, spin_unlock_irqrestore(&iommu->lock, flags); } +#ifdef CONFIG_DOMCTL static int cf_check reassign_device( struct domain *source, struct domain *target, u8 devfn, struct pci_dev *pdev) @@ -550,6 +551,7 @@ static int cf_check amd_iommu_assign_device( return rc; } +#endif /* CONFIG_DOMCTL */ static void cf_check amd_iommu_clear_root_pgtable(struct domain *d) { @@ -698,12 +700,14 @@ static int cf_check amd_iommu_remove_device(u8 devfn, struct pci_dev *pdev) return 0; } +#ifdef CONFIG_DOMCTL static int cf_check amd_iommu_group_id(u16 seg, u8 bus, u8 devfn) { unsigned int bdf = PCI_BDF(bus, devfn); return (bdf < ivrs_bdf_entries) ? get_dma_requestor_id(seg, bdf) : bdf; } +#endif /* CONFIG_DOMCTL */ #include @@ -772,14 +776,18 @@ static const struct iommu_ops __initconst_cf_clobber _iommu_ops = { .quarantine_init = amd_iommu_quarantine_init, .add_device = amd_iommu_add_device, .remove_device = amd_iommu_remove_device, +#ifdef CONFIG_DOMCTL .assign_device = amd_iommu_assign_device, +#endif .teardown = amd_iommu_domain_destroy, .clear_root_pgtable = amd_iommu_clear_root_pgtable, .map_page = amd_iommu_map_page, .unmap_page = amd_iommu_unmap_page, .iotlb_flush = amd_iommu_flush_iotlb_pages, +#ifdef CONFIG_DOMCTL .reassign_device = reassign_device, .get_device_group_id = amd_iommu_group_id, +#endif .enable_x2apic = iov_enable_xt, .update_ire_from_apic = amd_iommu_ioapic_update_ire, .update_ire_from_msi = amd_iommu_msi_msg_update_ire, diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index dac0dd6d46..719f0a11cc 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -726,6 +726,7 @@ static int ipmmu_attach_device(struct ipmmu_vmsa_domain *domain, return 0; } +#ifdef CONFIG_DOMCTL static void ipmmu_detach_device(struct ipmmu_vmsa_domain *domain, struct device *dev) { @@ -735,6 +736,7 @@ static void ipmmu_detach_device(struct ipmmu_vmsa_domain *domain, for ( i = 0; i < fwspec->num_ids; ++i ) ipmmu_utlb_disable(domain, fwspec->ids[i]); } +#endif /* CONFIG_DOMCTL */ static int ipmmu_init_platform_device(struct device *dev, const struct dt_phandle_args *args) @@ -1209,6 +1211,7 @@ out: return ret; } +#ifdef CONFIG_DOMCTL static int ipmmu_deassign_device(struct domain *d, struct device *dev) { struct ipmmu_vmsa_xen_domain *xen_domain = dom_iommu(d)->arch.priv; @@ -1264,6 +1267,7 @@ static int ipmmu_reassign_device(struct domain *s, struct domain *t, return 0; } +#endif /* CONFIG_DOMCTL */ static int ipmmu_dt_xlate(struct device *dev, const struct dt_phandle_args *spec) @@ -1367,7 +1371,9 @@ static const struct iommu_ops ipmmu_iommu_ops = .teardown = ipmmu_iommu_domain_teardown, .iotlb_flush = ipmmu_iotlb_flush, .assign_device = ipmmu_assign_device, +#ifdef CONFIG_DOMCTL .reassign_device = ipmmu_reassign_device, +#endif .map_page = arm_iommu_map_page, .unmap_page = arm_iommu_unmap_page, .dt_xlate = ipmmu_dt_xlate, diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index 5e9e3e048e..d3028d859e 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -2780,6 +2780,7 @@ static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, struct device return 0; } +#ifdef CONFIG_DOMCTL static int arm_smmu_reassign_dev(struct domain *s, struct domain *t, u8 devfn, struct device *dev) { @@ -2807,6 +2808,7 @@ static int arm_smmu_reassign_dev(struct domain *s, struct domain *t, return 0; } +#endif /* CONFIG_DOMCTL */ static int arm_smmu_iommu_xen_domain_init(struct domain *d) { @@ -2843,7 +2845,9 @@ static const struct iommu_ops arm_smmu_iommu_ops = { .teardown = arm_smmu_iommu_xen_domain_teardown, .iotlb_flush = arm_smmu_iotlb_flush, .assign_device = arm_smmu_assign_dev, +#ifdef CONFIG_DOMCTL .reassign_device = arm_smmu_reassign_dev, +#endif .map_page = arm_iommu_map_page, .unmap_page = arm_iommu_unmap_page, .dt_xlate = arm_smmu_dt_xlate, diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 22d306d0cb..f1d85ae91f 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -2891,6 +2891,7 @@ static int arm_smmu_deassign_dev(struct domain *d, uint8_t devfn, return 0; } +#ifdef CONFIG_DOMCTL static int arm_smmu_reassign_dev(struct domain *s, struct domain *t, u8 devfn, struct device *dev) { @@ -2918,6 +2919,7 @@ static int arm_smmu_reassign_dev(struct domain *s, struct domain *t, return 0; } +#endif /* CONFIG_DOMCTL */ static int arm_smmu_iommu_domain_init(struct domain *d) { @@ -2956,7 +2958,9 @@ static const struct iommu_ops arm_smmu_iommu_ops = { .teardown = arm_smmu_iommu_domain_teardown, .iotlb_flush = arm_smmu_iotlb_flush, .assign_device = arm_smmu_assign_dev, +#ifdef CONFIG_DOMCTL .reassign_device = arm_smmu_reassign_dev, +#endif .map_page = arm_iommu_map_page, .unmap_page = arm_iommu_unmap_page, .dt_xlate = arm_smmu_dt_xlate_generic, diff --git a/xen/drivers/passthrough/device_tree.c b/xen/drivers/passthrough/device_tree.c index 704910de3d..225aae2f29 100644 --- a/xen/drivers/passthrough/device_tree.c +++ b/xen/drivers/passthrough/device_tree.c @@ -59,6 +59,7 @@ fail: return rc; } +#ifdef CONFIG_DOMCTL int iommu_deassign_dt_device(struct domain *d, struct dt_device_node *dev) { const struct domain_iommu *hd = dom_iommu(d); @@ -86,6 +87,7 @@ fail: return rc; } +#endif /* CONFIG_DOMCTL */ static bool iommu_dt_device_is_assigned_locked(const struct dt_device_node *dev) { @@ -320,6 +322,7 @@ int iommu_add_dt_device(struct dt_device_node *np) return rc; } +#ifdef CONFIG_DOMCTL int iommu_do_dt_domctl(struct xen_domctl *domctl, struct domain *d, XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) { @@ -431,3 +434,4 @@ int iommu_do_dt_domctl(struct xen_domctl *domctl, struct domain *d, return ret; } +#endif /* CONFIG_DOMCTL */ diff --git a/xen/drivers/passthrough/iommu.c b/xen/drivers/passthrough/iommu.c index c9425d6971..5035eb6e53 100644 --- a/xen/drivers/passthrough/iommu.c +++ b/xen/drivers/passthrough/iommu.c @@ -625,6 +625,7 @@ void iommu_resume(void) iommu_vcall(iommu_get_ops(), resume); } +#ifdef CONFIG_DOMCTL int iommu_do_domctl( struct xen_domctl *domctl, struct domain *d, XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) @@ -645,6 +646,7 @@ int iommu_do_domctl( return ret; } +#endif /* CONFIG_DOMCTL */ void iommu_crash_shutdown(void) { diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c index 41638b71d6..176c7502d6 100644 --- a/xen/drivers/passthrough/pci.c +++ b/xen/drivers/passthrough/pci.c @@ -877,6 +877,7 @@ int pci_remove_device(u16 seg, u8 bus, u8 devfn) return ret; } +#ifdef CONFIG_DOMCTL /* Caller should hold the pcidevs_lock */ static int deassign_device(struct domain *d, uint16_t seg, uint8_t bus, uint8_t devfn) @@ -945,7 +946,6 @@ static int deassign_device(struct domain *d, uint16_t seg, uint8_t bus, return ret; } -#ifdef CONFIG_DOMCTL int pci_release_devices(struct domain *d) { int combined_ret; @@ -1483,6 +1483,7 @@ static int iommu_remove_device(struct pci_dev *pdev) return iommu_call(hd->platform_ops, remove_device, devfn, pci_to_dev(pdev)); } +#ifdef CONFIG_DOMCTL static int device_assigned(u16 seg, u8 bus, u8 devfn) { struct pci_dev *pdev; @@ -1646,6 +1647,7 @@ static int iommu_get_device_group( return i; } +#endif /* CONFIG_DOMCTL */ void iommu_dev_iotlb_flush_timeout(struct domain *d, struct pci_dev *pdev) { @@ -1671,6 +1673,7 @@ void iommu_dev_iotlb_flush_timeout(struct domain *d, struct pci_dev *pdev) pcidevs_unlock(); } +#ifdef CONFIG_DOMCTL int iommu_do_pci_domctl( struct xen_domctl *domctl, struct domain *d, XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) @@ -1804,6 +1807,7 @@ int iommu_do_pci_domctl( return ret; } +#endif /* CONFIG_DOMCTL */ struct segment_iter { int (*handler)(struct pci_dev *pdev, void *arg); diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index c55f02c97e..e9c074a649 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -2731,6 +2731,7 @@ static int __init cf_check vtd_setup(void) return ret; } +#ifdef CONFIG_DOMCTL static int cf_check reassign_device_ownership( struct domain *source, struct domain *target, @@ -2926,6 +2927,7 @@ static int cf_check intel_iommu_group_id(u16 seg, u8 bus, u8 devfn) return PCI_BDF(bus, devfn); } +#endif /* CONFIG_DOMCTL */ static int __must_check cf_check vtd_suspend(void) { @@ -3234,14 +3236,18 @@ static const struct iommu_ops __initconst_cf_clobber vtd_ops = { .add_device = intel_iommu_add_device, .enable_device = intel_iommu_enable_device, .remove_device = intel_iommu_remove_device, +#ifdef CONFIG_DOMCTL .assign_device = intel_iommu_assign_device, +#endif .teardown = iommu_domain_teardown, .clear_root_pgtable = iommu_clear_root_pgtable, .map_page = intel_iommu_map_page, .unmap_page = intel_iommu_unmap_page, .lookup_page = intel_iommu_lookup_page, +#ifdef CONFIG_DOMCTL .reassign_device = reassign_device_ownership, .get_device_group_id = intel_iommu_group_id, +#endif .enable_x2apic = intel_iommu_enable_eim, .disable_x2apic = intel_iommu_disable_eim, .update_ire_from_apic = io_apic_write_remap_rte, diff --git a/xen/include/xsm/xsm.h b/xen/include/xsm/xsm.h index db98496869..6bbf3df702 100644 --- a/xen/include/xsm/xsm.h +++ b/xen/include/xsm/xsm.h @@ -127,13 +127,13 @@ struct xsm_ops { int (*pci_config_permission)(struct domain *d, uint32_t machine_bdf, uint16_t start, uint16_t end, uint8_t access); -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) && defined(CONFIG_DOMCTL) int (*get_device_group)(uint32_t machine_bdf); int (*assign_device)(struct domain *d, uint32_t machine_bdf); int (*deassign_device)(struct domain *d, uint32_t machine_bdf); #endif -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) && defined(CONFIG_DOMCTL) int (*assign_dtdevice)(struct domain *d, const char *dtpath); int (*deassign_dtdevice)(struct domain *d, const char *dtpath); #endif @@ -548,7 +548,7 @@ static inline int xsm_pci_config_permission( return alternative_call(xsm_ops.pci_config_permission, d, machine_bdf, start, end, access); } -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) && defined(CONFIG_DOMCTL) static inline int xsm_get_device_group(xsm_default_t def, uint32_t machine_bdf) { return alternative_call(xsm_ops.get_device_group, machine_bdf); @@ -565,9 +565,9 @@ static inline int xsm_deassign_device( { return alternative_call(xsm_ops.deassign_device, d, machine_bdf); } -#endif /* HAS_PASSTHROUGH && HAS_PCI) */ +#endif /* HAS_PASSTHROUGH && HAS_PCI && DOMCTL */ -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) && defined(CONFIG_DOMCTL) static inline int xsm_assign_dtdevice( xsm_default_t def, struct domain *d, const char *dtpath) { @@ -580,7 +580,7 @@ static inline int xsm_deassign_dtdevice( return alternative_call(xsm_ops.deassign_dtdevice, d, dtpath); } -#endif /* HAS_PASSTHROUGH && HAS_DEVICE_TREE_DISCOVERY */ +#endif /* HAS_PASSTHROUGH && HAS_DEVICE_TREE_DISCOVERY && DOMCTL */ static inline int xsm_resource_plug_pci(xsm_default_t def, uint32_t machine_bdf) { diff --git a/xen/xsm/dummy.c b/xen/xsm/dummy.c index b7eb061e9b..b5174e610b 100644 --- a/xen/xsm/dummy.c +++ b/xen/xsm/dummy.c @@ -85,13 +85,13 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { .pci_config_permission = xsm_pci_config_permission, .get_vnumainfo = xsm_get_vnumainfo, -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) && defined(CONFIG_DOMCTL) .get_device_group = xsm_get_device_group, .assign_device = xsm_assign_device, .deassign_device = xsm_deassign_device, #endif -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) && defined(CONFIG_DOMCTL) .assign_dtdevice = xsm_assign_dtdevice, .deassign_dtdevice = xsm_deassign_dtdevice, #endif diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index 9f829aa53b..254e1323e5 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -1397,7 +1397,7 @@ static int cf_check flask_mem_sharing(struct domain *d) } #endif -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) && defined(CONFIG_DOMCTL) static int cf_check flask_get_device_group(uint32_t machine_bdf) { uint32_t rsid; @@ -1468,9 +1468,9 @@ static int cf_check flask_deassign_device( return avc_current_has_perm(rsid, SECCLASS_RESOURCE, RESOURCE__REMOVE_DEVICE, NULL); } -#endif /* HAS_PASSTHROUGH && HAS_PCI */ +#endif /* HAS_PASSTHROUGH && HAS_PCI && DOMCTL */ -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) && defined(CONFIG_DOMCTL) static int flask_test_assign_dtdevice(const char *dtpath) { uint32_t rsid; @@ -1531,7 +1531,7 @@ static int cf_check flask_deassign_dtdevice( return avc_current_has_perm(rsid, SECCLASS_RESOURCE, RESOURCE__REMOVE_DEVICE, NULL); } -#endif /* HAS_PASSTHROUGH && HAS_DEVICE_TREE_DISCOVERY */ +#endif /* HAS_PASSTHROUGH && HAS_DEVICE_TREE_DISCOVERY && DOMCTL */ static int cf_check flask_platform_op(uint32_t op) { @@ -2003,13 +2003,13 @@ static const struct xsm_ops __initconst_cf_clobber flask_ops = { .remove_from_physmap = flask_remove_from_physmap, .map_gmfn_foreign = flask_map_gmfn_foreign, -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_PCI) && defined(CONFIG_DOMCTL) .get_device_group = flask_get_device_group, .assign_device = flask_assign_device, .deassign_device = flask_deassign_device, #endif -#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) +#if defined(CONFIG_HAS_PASSTHROUGH) && defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) && defined(CONFIG_DOMCTL) .assign_dtdevice = flask_assign_dtdevice, .deassign_dtdevice = flask_deassign_dtdevice, #endif -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:44 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068393.1432412 (Exim 4.92) (envelope-from ) id 1uiVMa-00031I-57; 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Signed-off-by: Penny Zheng --- xen/arch/arm/mem_access.c | 2 ++ xen/arch/x86/mm/mem_access.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/xen/arch/arm/mem_access.c b/xen/arch/arm/mem_access.c index 2af92bb402..e205b6be8f 100644 --- a/xen/arch/arm/mem_access.c +++ b/xen/arch/arm/mem_access.c @@ -450,11 +450,13 @@ int p2m_get_mem_access(struct domain *d, gfn_t gfn, return ret; } +#ifdef CONFIG_DOMCTL void arch_p2m_set_access_required(struct domain *d, bool access_required) { ASSERT(atomic_read(&d->pause_count)); p2m_get_hostp2m(d)->access_required = access_required; } +#endif /* CONFIG_DOMCTL */ /* * Local variables: diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c index 21b5b7ecda..de694c16e9 100644 --- a/xen/arch/x86/mm/mem_access.c +++ b/xen/arch/x86/mm/mem_access.c @@ -480,6 +480,7 @@ int p2m_get_mem_access(struct domain *d, gfn_t gfn, xenmem_access_t *access, return _p2m_get_mem_access(p2m, gfn, access); } +#ifdef CONFIG_DOMCTL void arch_p2m_set_access_required(struct domain *d, bool access_required) { ASSERT(atomic_read(&d->pause_count)); @@ -498,6 +499,7 @@ void arch_p2m_set_access_required(struct domain *d, bool access_required) } } } +#endif /* CONFIG_DOMCTL */ bool p2m_mem_access_sanity_check(const struct domain *d) { -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:45 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068395.1432424 (Exim 4.92) (envelope-from ) id 1uiVMb-0003Qw-D5; Sun, 03 Aug 2025 09:50:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068395.1432424; Sun, 03 Aug 2025 09:50:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVMb-0003Pw-93; Sun, 03 Aug 2025 09:50:45 +0000 Received: by outflank-mailman (input) for mailman id 1068395; Sun, 03 Aug 2025 09:50:43 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVKg-0005hH-Av for xen-devel@lists.xenproject.org; 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Tracing its calling chain, the following functions shall be wrapped too: - xsm_domctl_scheduler_op() - sched_adjust_dom() - scheduler-specific .adjust() callback Signed-off-by: Penny Zheng --- xen/common/sched/arinc653.c | 2 ++ xen/common/sched/core.c | 2 ++ xen/common/sched/credit.c | 4 ++++ xen/common/sched/credit2.c | 4 ++++ xen/common/sched/private.h | 4 ++++ xen/common/sched/rt.c | 4 ++++ xen/include/xsm/xsm.h | 4 ++++ xen/xsm/dummy.c | 2 ++ xen/xsm/flask/hooks.c | 4 ++++ 9 files changed, 30 insertions(+) diff --git a/xen/common/sched/arinc653.c b/xen/common/sched/arinc653.c index 8a4f4259d8..e73b0256a6 100644 --- a/xen/common/sched/arinc653.c +++ b/xen/common/sched/arinc653.c @@ -735,7 +735,9 @@ static const struct scheduler sched_arinc653_def = { .switch_sched = a653_switch_sched, +#ifdef CONFIG_DOMCTL .adjust = NULL, +#endif #ifdef CONFIG_SYSCTL .adjust_global = a653sched_adjust_global, #endif diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c index 14f27fe70f..896178b32f 100644 --- a/xen/common/sched/core.c +++ b/xen/common/sched/core.c @@ -2080,6 +2080,7 @@ int scheduler_id(void) } #endif +#ifdef CONFIG_DOMCTL /* Adjust scheduling parameter for a given domain. */ long sched_adjust(struct domain *d, struct xen_domctl_scheduler_op *op) { @@ -2114,6 +2115,7 @@ long sched_adjust(struct domain *d, struct xen_domctl_scheduler_op *op) return ret; } +#endif /* CONFIG_DOMCTL */ #ifdef CONFIG_SYSCTL long sched_adjust_global(struct xen_sysctl_scheduler_op *op) diff --git a/xen/common/sched/credit.c b/xen/common/sched/credit.c index 6dcf6b2c8b..fff1af063e 100644 --- a/xen/common/sched/credit.c +++ b/xen/common/sched/credit.c @@ -1183,6 +1183,7 @@ csched_unit_yield(const struct scheduler *ops, struct sched_unit *unit) set_bit(CSCHED_FLAG_UNIT_YIELD, &svc->flags); } +#ifdef CONFIG_DOMCTL static int cf_check csched_dom_cntl( const struct scheduler *ops, @@ -1227,6 +1228,7 @@ csched_dom_cntl( return rc; } +#endif /* CONFIG_DOMCTL */ static void cf_check csched_aff_cntl(const struct scheduler *ops, struct sched_unit *unit, @@ -2288,7 +2290,9 @@ static const struct scheduler sched_credit_def = { .wake = csched_unit_wake, .yield = csched_unit_yield, +#ifdef CONFIG_DOMCTL .adjust = csched_dom_cntl, +#endif .adjust_affinity= csched_aff_cntl, #ifdef CONFIG_SYSCTL .adjust_global = csched_sys_cntl, diff --git a/xen/common/sched/credit2.c b/xen/common/sched/credit2.c index 75316d42b7..51784d9aab 100644 --- a/xen/common/sched/credit2.c +++ b/xen/common/sched/credit2.c @@ -2909,6 +2909,7 @@ static void cf_check csched2_unit_migrate( sched_set_res(unit, get_sched_res(new_cpu)); } +#ifdef CONFIG_DOMCTL static int cf_check csched2_dom_cntl( const struct scheduler *ops, @@ -3114,6 +3115,7 @@ csched2_dom_cntl( return rc; } +#endif /* CONFIG_DOMCTL */ static void cf_check csched2_aff_cntl(const struct scheduler *ops, struct sched_unit *unit, @@ -4246,7 +4248,9 @@ static const struct scheduler sched_credit2_def = { .wake = csched2_unit_wake, .yield = csched2_unit_yield, +#ifdef CONFIG_DOMCTL .adjust = csched2_dom_cntl, +#endif .adjust_affinity= csched2_aff_cntl, #ifdef CONFIG_SYSCTL .adjust_global = csched2_sys_cntl, diff --git a/xen/common/sched/private.h b/xen/common/sched/private.h index d6884550cd..b8841c9308 100644 --- a/xen/common/sched/private.h +++ b/xen/common/sched/private.h @@ -349,9 +349,11 @@ struct scheduler { void (*migrate) (const struct scheduler *ops, struct sched_unit *unit, unsigned int new_cpu); +#ifdef CONFIG_DOMCTL int (*adjust) (const struct scheduler *ops, struct domain *d, struct xen_domctl_scheduler_op *op); +#endif void (*adjust_affinity)(const struct scheduler *ops, struct sched_unit *unit, const struct cpumask *hard, @@ -506,11 +508,13 @@ static inline void sched_adjust_affinity(const struct scheduler *s, s->adjust_affinity(s, unit, hard, soft); } +#ifdef CONFIG_DOMCTL static inline int sched_adjust_dom(const struct scheduler *s, struct domain *d, struct xen_domctl_scheduler_op *op) { return s->adjust ? s->adjust(s, d, op) : 0; } +#endif #ifdef CONFIG_SYSCTL static inline int sched_adjust_cpupool(const struct scheduler *s, diff --git a/xen/common/sched/rt.c b/xen/common/sched/rt.c index 7b1f64a779..fd677b4f09 100644 --- a/xen/common/sched/rt.c +++ b/xen/common/sched/rt.c @@ -1362,6 +1362,7 @@ out: unit_schedule_unlock_irq(lock, unit); } +#ifdef CONFIG_DOMCTL /* * set/get each unit info of each domain */ @@ -1471,6 +1472,7 @@ rt_dom_cntl( return rc; } +#endif /* CONFIG_DOMCTL */ /* * The replenishment timer handler picks units @@ -1572,7 +1574,9 @@ static const struct scheduler sched_rtds_def = { .insert_unit = rt_unit_insert, .remove_unit = rt_unit_remove, +#ifdef CONFIG_DOMCTL .adjust = rt_dom_cntl, +#endif .pick_resource = rt_res_pick, .do_schedule = rt_schedule, diff --git a/xen/include/xsm/xsm.h b/xen/include/xsm/xsm.h index 7c61f27366..6444f0677b 100644 --- a/xen/include/xsm/xsm.h +++ b/xen/include/xsm/xsm.h @@ -56,7 +56,9 @@ struct xsm_ops { struct xen_domctl_getdomaininfo *info); int (*domain_create)(struct domain *d, uint32_t ssidref); int (*getdomaininfo)(struct domain *d); +#ifdef CONFIG_DOMCTL int (*domctl_scheduler_op)(struct domain *d, int op); +#endif #ifdef CONFIG_SYSCTL int (*sysctl_scheduler_op)(int op); #endif @@ -242,11 +244,13 @@ static inline int xsm_get_domain_state(xsm_default_t def, struct domain *d) return alternative_call(xsm_ops.get_domain_state, d); } +#ifdef CONFIG_DOMCTL static inline int xsm_domctl_scheduler_op( xsm_default_t def, struct domain *d, int cmd) { return alternative_call(xsm_ops.domctl_scheduler_op, d, cmd); } +#endif #ifdef CONFIG_SYSCTL static inline int xsm_sysctl_scheduler_op(xsm_default_t def, int cmd) diff --git a/xen/xsm/dummy.c b/xen/xsm/dummy.c index 6f8b06b45f..b8a9b581b7 100644 --- a/xen/xsm/dummy.c +++ b/xen/xsm/dummy.c @@ -18,7 +18,9 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { .security_domaininfo = xsm_security_domaininfo, .domain_create = xsm_domain_create, .getdomaininfo = xsm_getdomaininfo, +#ifdef CONFIG_DOMCTL .domctl_scheduler_op = xsm_domctl_scheduler_op, +#endif #ifdef CONFIG_SYSCTL .sysctl_scheduler_op = xsm_sysctl_scheduler_op, #endif diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index fd7aea460f..55da0a5ff7 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -609,6 +609,7 @@ static int cf_check flask_getdomaininfo(struct domain *d) return current_has_perm(d, SECCLASS_DOMAIN, DOMAIN__GETDOMAININFO); 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pr=C From: Penny Zheng To: CC: , Penny Zheng , "Daniel P. Smith" Subject: [PATCH v1 16/25] xen/domctl: wrap around XEN_DOMCTL_set_target Date: Sun, 3 Aug 2025 17:47:29 +0800 Message-ID: <20250803094738.3625269-17-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231E:EE_|PH8PR12MB6913:EE_ X-MS-Office365-Filtering-Correlation-Id: ea3ce413-97c8-4ce5-d3fd-08ddd272f1cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?eOhBBPQg059xJuxTN+DNL0n7YeKE1F+VhhGbuIU7mk3gnxcJvxGqooUXRa4s?= =?us-ascii?Q?enFmJBtHe1KQcerQlkVgOJ/91ztDd79Bom743/p5uhlKMIJUeNBpYfHoFUOC?= =?us-ascii?Q?ANnasmGTKQ0kBjxmEFllISZML+rKyaNOJTxwcJaw78w8yTonjvQGuWGkDRlg?= =?us-ascii?Q?r0uOo0mofUo0VbKRR/WoVSzZVw0lugjnZF7nngrSuMRHwH9pd2BSwnrkW40d?= =?us-ascii?Q?HVd311eUx7O5KCtCr910aYymU7/hIDQqxPdVQYieL9Dg4V+QwkJeePkakXpN?= =?us-ascii?Q?c2p4LR9Uqzt9HefWyeYVBKwz8Ou/BrAW6PgADaPb1ObonztibTGkMCCB2ysO?= =?us-ascii?Q?S5PFCtdQ6tnPmm+0DEqql7AvCzoIgf1+30qayOurK72j881fwXCgC8GvbNmL?= =?us-ascii?Q?6glTXYSfvyV+TNcCwE6y3kXZVpJFRrBfmJy/gc4BhajpcdStm6WLolqC6Q4N?= =?us-ascii?Q?pvkjiLMFQRujiKRMldTpkW0e8ZM8ClZsIOSWxEAO2v+S68j64ooBSynbjvqr?= =?us-ascii?Q?aSLYq/QNEu9+xFy/oTzf9YAQ4OOSN+e7u+zB2V5gcF/KcP0NcDaKFDOaPRqr?= =?us-ascii?Q?vRplaYCjCRctHFRf0LzdpbM71AXYVjmM8J1P0MR0bcEsVl+RC2SPT7nxBRay?= =?us-ascii?Q?fzztdx2olTTBZUUoq5Xgjn6G2lgdCaW4b48jOwYP+v7DXx4X0KxMmIBkWHNi?= =?us-ascii?Q?Ku/jcupdJDVwe+sx6HMuVcxvN9iUVclp5QZUnGoWb8N+Jpma1ojx56W5Akd6?= =?us-ascii?Q?27rzhGRXdd85+elizO9Zl816jHEOiFnux4xAjSka4iAMEFglrt/sJahOY0sB?= =?us-ascii?Q?7q55Y1OhI5HuRKKqoLm3++C8V8F1vcjABXVdnR3sSVYVGVQvbg9joUk2I0j5?= =?us-ascii?Q?t9R5hZzSfczQOg4+FeqsmtYAicBZL29FYKfpbu0PM9odZVABX2GGIVzByNmH?= =?us-ascii?Q?HGNWK77L9hQ6T+j3B5w6vgSv1KwhFWZ1I2A6pZJG/s+CC1y0xRfONFbMrkkY?= =?us-ascii?Q?JLsENdw4ahgV0nThLJlhNnF2lQDgDFme8wi7jt9rNfVi7PZQj1T9dsSlx/5j?= =?us-ascii?Q?crhs73ddW/rT7HZxZ1hO7WC5+YQ+gvgSCqLXxmVuWHSSfe/6IhPtKTRBZIxw?= =?us-ascii?Q?LAghgZlqM9k0nF1HDMk7SvtvR/RAn/AFR7JiyTz9MzAEVuB6BU5jIAUfDBtS?= =?us-ascii?Q?rnS67tAHWpPRZvpEDXdFwb/obP1SP0wOTnEL9/rhM+PHd+jNqHLUESjcvgi4?= =?us-ascii?Q?A0IHgnmL8hvsRqD1byQIrIY5IUPPLyS9tYmskRGqsughxehTBNKvF62dvU7K?= =?us-ascii?Q?KqWjBVZ379Qb42ltpIZJnemXeu5AZRpQetRbWOLVv8UVwQcS////AzXAQkiu?= =?us-ascii?Q?YvedyhFA14RqXZj9EBoNd5OjaLMgWPOLodxv1HqCtxY0eBr9eUxBgwVHeZoY?= =?us-ascii?Q?3ZShmlAUvD7FUeviet4a/zTq7SnTbO82EIf0Mwu5aWvbfjPy4Pxrryarkaos?= =?us-ascii?Q?Ay95k6A9Bk+5oLEEKTufWkPVmzeXNC0arX/c?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:47.9964 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea3ce413-97c8-4ce5-d3fd-08ddd272f1cc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6913 Function xsm_set_target() is only invoked under XEN_DOMCTL_set_target domctl-op, and shall be wrapped. Signed-off-by: Penny Zheng --- xen/include/xsm/xsm.h | 4 ++++ xen/xsm/dummy.c | 2 ++ xen/xsm/flask/hooks.c | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/xen/include/xsm/xsm.h b/xen/include/xsm/xsm.h index 1759d49aaa..55f8d0903e 100644 --- a/xen/include/xsm/xsm.h +++ b/xen/include/xsm/xsm.h @@ -62,7 +62,9 @@ struct xsm_ops { #ifdef CONFIG_SYSCTL int (*sysctl_scheduler_op)(int op); #endif +#ifdef CONFIG_DOMCTL int (*set_target)(struct domain *d, struct domain *e); +#endif int (*domctl)(struct domain *d, unsigned int cmd, uint32_t ssidref); int (*sysctl)(int cmd); int (*readconsole)(uint32_t clear); @@ -261,11 +263,13 @@ static inline int xsm_sysctl_scheduler_op(xsm_default_t def, int cmd) } #endif +#ifdef CONFIG_DOMCTL static inline int xsm_set_target( xsm_default_t def, struct domain *d, struct domain *e) { return alternative_call(xsm_ops.set_target, d, e); } +#endif static inline int xsm_domctl(xsm_default_t def, struct domain *d, unsigned int cmd, uint32_t ssidref) diff --git a/xen/xsm/dummy.c b/xen/xsm/dummy.c index 2798425de2..cd5358dd1e 100644 --- a/xen/xsm/dummy.c +++ b/xen/xsm/dummy.c @@ -24,7 +24,9 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { #ifdef CONFIG_SYSCTL .sysctl_scheduler_op = xsm_sysctl_scheduler_op, #endif +#ifdef CONFIG_DOMCTL .set_target = xsm_set_target, +#endif .domctl = xsm_domctl, #ifdef CONFIG_SYSCTL .sysctl = xsm_sysctl, diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index 8361cf94f9..2975d2906f 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -645,6 +645,7 @@ static int cf_check flask_sysctl_scheduler_op(int op) } #endif /* CONFIG_SYSCTL */ +#ifdef CONFIG_DOMCTL static int cf_check flask_set_target(struct domain *d, struct domain *t) { int rc; @@ -668,6 +669,7 @@ static int cf_check flask_set_target(struct domain *d, struct domain *t) &dsec->target_sid); return rc; } +#endif /* CONFIG_DOMCTL */ static int cf_check flask_domctl(struct domain *d, unsigned int cmd, uint32_t ssidref) @@ -1900,7 +1902,9 @@ static const struct xsm_ops __initconst_cf_clobber flask_ops = { #ifdef CONFIG_SYSCTL .sysctl_scheduler_op = flask_sysctl_scheduler_op, #endif +#ifdef CONFIG_DOMCTL .set_target = flask_set_target, +#endif .domctl = flask_domctl, #ifdef CONFIG_SYSCTL .sysctl = flask_sysctl, -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:46 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:46 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068397.1432436 (Exim 4.92) (envelope-from ) id 1uiVMc-0003cM-Ac; Sun, 03 Aug 2025 09:50:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068397.1432436; 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pr=C From: Penny Zheng To: CC: , Penny Zheng , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 06/25] xen/domctl: provide stub for domctl_lock_{acquire,release} Date: Sun, 3 Aug 2025 17:47:19 +0800 Message-ID: <20250803094738.3625269-7-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231D:EE_|SA0PR12MB4461:EE_ X-MS-Office365-Filtering-Correlation-Id: f8d7a918-c43e-452e-dd72-08ddd272e037 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|30052699003|82310400026|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:18.5009 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8d7a918-c43e-452e-dd72-08ddd272e037 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4461 With DOMCTL=n, we need to provide stub for domctl_lock_{acquire,release}(), as it may be invoked by hvm_set_param() in x86 PV shim mode. Although PV_SHIM_EXCLUSIVE and HVM shall not be both enabled, randconfig stands little chance to make it happen. Signed-off-by: Penny Zheng --- xen/include/xen/domain.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index 33dd90357c..b45ac91760 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -148,8 +148,17 @@ void arch_dump_domain_info(struct domain *d); int arch_vcpu_reset(struct vcpu *v); +#ifdef CONFIG_DOMCTL bool domctl_lock_acquire(void); void domctl_lock_release(void); +#else +static inline bool domctl_lock_acquire(void) +{ + return false; +} + +static inline void domctl_lock_release(void) {} +#endif /* CONFIG_DOMCTL */ /* * Continue the current hypercall via func(data) on specified cpu. -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:47 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068399.1432443 (Exim 4.92) (envelope-from ) id 1uiVMd-0003mh-1L; Sun, 03 Aug 2025 09:50:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068399.1432443; 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pr=C From: Penny Zheng To: CC: , Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Jan Beulich , "Andrew Cooper" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Tamas K Lengyel , "Daniel P. Smith" Subject: [PATCH v1 24/25] xen/domctl: wrap around arch-specific domctl op Date: Sun, 3 Aug 2025 17:47:37 +0800 Message-ID: <20250803094738.3625269-25-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|IA1PR12MB6113:EE_ X-MS-Office365-Filtering-Correlation-Id: 7740e4fc-b0a5-4c9b-f465-08ddd27300bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?vLR9Ocf/Cyx/1ZnKlLDgi6URU1motvfWrWdjfUIoZ71N/PE9Rv0ocDZuVaKA?= =?us-ascii?Q?Lx4vvZvNrppWXqFBGDwfqYOjYHPBJ0inQ7bsLMY2SUMLh7aWU1EMnEpBCdL2?= =?us-ascii?Q?MhJgS9f6KZPgJEK/A+QWVup4JJ2KHahnR0NBPWeVAwUvd87CXTTIu4M7rdUu?= =?us-ascii?Q?FxWbBNvCtyCunckLyBxLkgsLiaraFBH3WlHfR9+BMeoPU+bKhRCpuz20yBsh?= =?us-ascii?Q?Grd4xfUsKpLpjP+2LMpxlAmkxl+0ZPkTYl7BIUCCWp64IEdBQ4xntoMk/GJ1?= =?us-ascii?Q?OdgTpB4i2BasnnEeFRfwTGRsHRAHEXeCvGjiSM2aCj15NVz5hxJ7Hz47SpCQ?= =?us-ascii?Q?SOFpyDzLNc0R8+a5l974AV6brBMfHr/oqDt3urHIuH6LedX9M4GNu5CBX+iY?= =?us-ascii?Q?LG61nBM1FV/mKGdQp5ip5Z0Q5r21QXPvF1/pLLkwMnWO4MzwwMJO3iGGxA8U?= =?us-ascii?Q?Hm5NlG9LjtaDsNieeiYJ7t/8tvahpggk92wslZQTjmCqQjYCDyoUPAHMcUcf?= =?us-ascii?Q?dZZW03I5YV+UOi0VU2nbOXgNgh7i5Sf9Ez9tyRVrL6G8Zlv63G1LOThEw6mm?= =?us-ascii?Q?/RmE3IQuiF+yT/cNRp/uJD426LXRL31kT9hL+wivz5QnfD6xXmiHkYzEEKoj?= =?us-ascii?Q?xrwofK5jCfZykwf3m3CTHUaZDMmsTMb8mXCGsS65xj8LmpMkNuTqVsmydU8q?= =?us-ascii?Q?TnnnSEhCodWkRVr/ZxesyOrqeSq1YkEzrVTvCmIsJWnTtBE9zfJujLNXCXNZ?= =?us-ascii?Q?DKeg/gFR9aLrV62iORsADuPXMOLR0/i8mYq51LgCiDo3NGmxjZprrnf6fGTi?= =?us-ascii?Q?ZsmpZ+POeMFK4B9wQ9W6arvOf2lo2uOvBgLFRxK1QlNgl7fXMyk/E3LVr5Mh?= =?us-ascii?Q?GZN/72pRZ7+w8rYEV5bDeTeqZO/ajax0CiSvkZsRUWEmCYnZNTNeO1FIlqFK?= =?us-ascii?Q?PMqFMsXmQOadd++r4b3Kz4BcQ2TYw+RJcZT38lhP95wQR0aassOBZAC9w2me?= =?us-ascii?Q?b5tyjmN7Uayt6CggvOzrrSmRQMW7u12t+6Ys34xV9oQwLohllutt0DZ2LSxu?= =?us-ascii?Q?SKQS9rx95krIkk5euLBh2Mcx4g8c2PMAuxJqX8OJZknbSRqqBMyRUYx6T6Ek?= =?us-ascii?Q?oTh0Lg/uk+4tOuVpvYQsB+GPQVLQ8JalvoUXvB3vuQWvnyNbieWf1CufNflf?= =?us-ascii?Q?koaKOndGLJvM+KoLI7M8aZ9knU1fHTI0o1oY9xWK1zNIEolpC+ivvRahS3zz?= =?us-ascii?Q?JzgWSP20DhL9CvuXXh8Mj3fXWgnfuriAAY2nfIeYuASJqTLP7zipWCdgNXpJ?= =?us-ascii?Q?xo1uKDmi4/YPZRyaLMsSLXeVQa0sx882h1z6PpWg9+jL+4lUVRQTNLeApZVe?= =?us-ascii?Q?/ZKR+sNlWrZ9YLGipPVfJEOKi7rkpwyuHnaJ3aKdPkovPLMiAv6T86HnvJjC?= =?us-ascii?Q?9S3tf3mKgEyAA7J4x9dMLA6NTFkCaRgtuLlKVpGbDD4ou7Yxh7GkulsMTROi?= =?us-ascii?Q?HRDNSn2KMvHvvTmmCDJvysV2Q8K6R7wg0TXw?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:49:13.0520 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7740e4fc-b0a5-4c9b-f465-08ddd27300bb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6113 Function arch_do_domctl() is responsible for arch-specific domctl-op, and the following functions shall be wrapped: - xsm_domctl For x86: - hvm_save_one - hvm_acpi_power_button - hvm_acpi_sleep_button - xsm_{bind,unbind}_pt_irq - xsm_ioport_permission - xsm_ioport_mapping - hvm_debug_op - mem_sharing_domctl - make P2M_AUDIT depend on CONFIG_DOMCTL - make PG_log_dirty depend on CONFIG_DOMCTL - gdbsx_domctl - gdbsx_guest_meminfo - dgb_rw_guest_mem - dbg_hvm_va2mfn - dbg_pv_va2mfn - make policy.o depend on CONFIG_DOMCTL - do_vmtrace_op - hvm_vmtrace_control - hvm_funcs.vmtrace_control - hvm_vmtrace_get_option - hvm_funcs.vmtrace_get_option - hvm_vmtrace_set_option - hvm_funcs.vmtrace_set_option For ARM: - subarch_do_domctl Also, remove all #ifdef CONFIG_DOMCTL-s in arch-specific domctl.c, as we put the guardian in Makefile for the whole file. Signed-off-by: Penny Zheng --- xen/arch/arm/arm32/Makefile | 2 +- xen/arch/arm/arm64/Makefile | 2 +- xen/arch/arm/domctl.c | 2 -- xen/arch/x86/Makefile | 2 +- xen/arch/x86/domctl.c | 2 -- xen/arch/x86/gdbsx.c | 4 ++++ xen/arch/x86/hvm/hvm.c | 2 +- xen/arch/x86/hvm/pmtimer.c | 2 ++ xen/arch/x86/hvm/save.c | 2 ++ xen/arch/x86/hvm/vmx/vmx.c | 6 ++++++ xen/arch/x86/include/asm/hvm/hvm.h | 12 ++++++++++++ xen/arch/x86/include/asm/p2m.h | 2 +- xen/arch/x86/include/asm/paging.h | 2 +- xen/arch/x86/mm/mem_sharing.c | 2 ++ xen/include/xsm/xsm.h | 12 ++++++++---- xen/lib/x86/Makefile | 2 +- xen/xsm/dummy.c | 6 ++++-- xen/xsm/flask/hooks.c | 12 ++++++++---- 18 files changed, 55 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 531168f58a..384aaea398 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -4,7 +4,7 @@ obj-$(CONFIG_MPU) += mpu/ obj-y += cache.o obj-$(CONFIG_EARLY_PRINTK) += debug.o -obj-y += domctl.o +obj-$(CONFIG_DOMCTL) += domctl.o obj-y += domain.o obj-y += entry.o obj-y += head.o diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 6491c5350b..f2f547df9a 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -6,7 +6,7 @@ obj-y += cache.o obj-y += cpufeature.o obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) += bpi.o obj-$(CONFIG_EARLY_PRINTK) += debug.o -obj-y += domctl.o +obj-$(CONFIG_DOMCTL) += domctl.o obj-y += domain.o obj-y += entry.o obj-y += head.o diff --git a/xen/arch/arm/domctl.c b/xen/arch/arm/domctl.c index d508ee2880..ad914c915f 100644 --- a/xen/arch/arm/domctl.c +++ b/xen/arch/arm/domctl.c @@ -184,7 +184,6 @@ long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, } } -#ifdef CONFIG_DOMCTL void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) { struct vcpu_guest_context *ctxt = c.nat; @@ -200,7 +199,6 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) if ( !test_bit(_VPF_down, &v->pause_flags) ) ctxt->flags |= VGCF_online; } -#endif /* CONFIG_DOMCTL */ /* * Local variables: diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile index 17f0e1dbc9..c48759650c 100644 --- a/xen/arch/x86/Makefile +++ b/xen/arch/x86/Makefile @@ -28,7 +28,7 @@ obj-y += delay.o obj-y += desc.o obj-bin-y += dmi_scan.init.o obj-y += domain.o -obj-y += domctl.o +obj-$(CONFIG_DOMCTL) += domctl.o obj-bin-y += dom0_build.init.o obj-y += domain_page.o obj-y += e820.o diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 29f9db89a1..156c74e07a 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1367,7 +1367,6 @@ long arch_do_domctl( return ret; } -#ifdef CONFIG_DOMCTL #ifdef CONFIG_COMPAT #define xen_vcpu_guest_context vcpu_guest_context #define fpu_ctxt fpu_ctxt.x @@ -1526,7 +1525,6 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) c(vm_assist = d->vm_assist); #undef c } -#endif /* CONFIG_DOMCTL */ /* * Local variables: diff --git a/xen/arch/x86/gdbsx.c b/xen/arch/x86/gdbsx.c index 21442f5dff..df1a3ce9fb 100644 --- a/xen/arch/x86/gdbsx.c +++ b/xen/arch/x86/gdbsx.c @@ -23,6 +23,7 @@ #include #include +#ifdef CONFIG_DOMCTL typedef unsigned long dbgva_t; typedef unsigned char dbgbyte_t; @@ -166,6 +167,7 @@ static int gdbsx_guest_mem_io( return iop->remain ? -EFAULT : 0; } +#endif /* CONFIG_DOMCTL */ void domain_pause_for_debugger(void) { @@ -179,6 +181,7 @@ void domain_pause_for_debugger(void) send_global_virq(VIRQ_DEBUGGER); } +#ifdef CONFIG_DOMCTL int gdbsx_domctl(struct domain *d, struct xen_domctl *domctl, bool *copyback) { struct vcpu *v; @@ -245,6 +248,7 @@ int gdbsx_domctl(struct domain *d, struct xen_domctl *domctl, bool *copyback) return ret; } +#endif /* CONFIG_DOMCTL */ /* * Local variables: diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index f464f401aa..aca1e5ba69 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -5212,6 +5212,7 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE_PARAM(void) arg) return rc; } +#ifdef CONFIG_DOMCTL int hvm_debug_op(struct vcpu *v, int32_t op) { int rc = 0; @@ -5251,7 +5252,6 @@ int hvm_debug_op(struct vcpu *v, int32_t op) return rc; } -#ifdef CONFIG_VM_EVENT void hvm_toggle_singlestep(struct vcpu *v) { ASSERT(atomic_read(&v->pause_count)); diff --git a/xen/arch/x86/hvm/pmtimer.c b/xen/arch/x86/hvm/pmtimer.c index 87a7a01c9f..e4d0f001ff 100644 --- a/xen/arch/x86/hvm/pmtimer.c +++ b/xen/arch/x86/hvm/pmtimer.c @@ -56,6 +56,7 @@ static void pmt_update_sci(PMTState *s) hvm_isa_irq_deassert(s->vcpu->domain, SCI_IRQ); } +#ifdef CONFIG_DOMCTL void hvm_acpi_power_button(struct domain *d) { PMTState *s = &d->arch.hvm.pl_time->vpmt; @@ -81,6 +82,7 @@ void hvm_acpi_sleep_button(struct domain *d) pmt_update_sci(s); spin_unlock(&s->lock); } +#endif /* CONFIG_DOMCTL */ /* Set the correct value in the timer, accounting for time elapsed * since the last time we did that. */ diff --git a/xen/arch/x86/hvm/save.c b/xen/arch/x86/hvm/save.c index 8ab6405706..ffaf731ddc 100644 --- a/xen/arch/x86/hvm/save.c +++ b/xen/arch/x86/hvm/save.c @@ -121,6 +121,7 @@ size_t hvm_save_size(struct domain *d) return sz; } +#ifdef CONFIG_DOMCTL /* * Extract a single instance of a save record, by marshalling all records of * that type and copying out the one we need. @@ -195,6 +196,7 @@ int hvm_save_one(struct domain *d, unsigned int typecode, unsigned int instance, xfree(ctxt.data); return rv; } +#endif /* CONFIG_DOMCTL */ int hvm_save(struct domain *d, hvm_domain_context_t *h) { diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 9e4ad864fa..f562ab90b6 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2577,6 +2577,7 @@ static bool cf_check vmx_get_pending_event( (RTIT_STATUS_FILTER_EN | RTIT_STATUS_CONTEXT_EN | RTIT_STATUS_TRIGGER_EN | \ RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED) +#ifdef CONFIG_DOMCTL static int cf_check vmtrace_get_option( struct vcpu *v, uint64_t key, uint64_t *output) { @@ -2685,6 +2686,7 @@ static int cf_check vmtrace_control(struct vcpu *v, bool enable, bool reset) return 0; } +#endif /* CONFIG_DOMCTL */ static int cf_check vmtrace_output_position(struct vcpu *v, uint64_t *pos) { @@ -2873,10 +2875,14 @@ static struct hvm_function_table __initdata_cf_clobber vmx_function_table = { .altp2m_vcpu_update_vmfunc_ve = vmx_vcpu_update_vmfunc_ve, .altp2m_vcpu_emulate_ve = vmx_vcpu_emulate_ve, .altp2m_vcpu_emulate_vmfunc = vmx_vcpu_emulate_vmfunc, +#ifdef CONFIG_DOMCTL .vmtrace_control = vmtrace_control, +#endif .vmtrace_output_position = vmtrace_output_position, +#ifdef CONFIG_DOMCTL .vmtrace_set_option = vmtrace_set_option, .vmtrace_get_option = vmtrace_get_option, +#endif .vmtrace_reset = vmtrace_reset, .get_reg = vmx_get_reg, diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h index bd53fcf155..dd106bac42 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -236,10 +236,14 @@ struct hvm_function_table { int (*altp2m_vcpu_emulate_vmfunc)(const struct cpu_user_regs *regs); /* vmtrace */ +#ifdef CONFIG_DOMCTL int (*vmtrace_control)(struct vcpu *v, bool enable, bool reset); +#endif int (*vmtrace_output_position)(struct vcpu *v, uint64_t *pos); +#ifdef CONFIG_DOMCTL int (*vmtrace_set_option)(struct vcpu *v, uint64_t key, uint64_t value); int (*vmtrace_get_option)(struct vcpu *v, uint64_t key, uint64_t *value); +#endif int (*vmtrace_reset)(struct vcpu *v); uint64_t (*get_reg)(struct vcpu *v, unsigned int reg); @@ -740,6 +744,7 @@ static inline bool altp2m_vcpu_emulate_ve(struct vcpu *v) return false; } +#ifdef CONFIG_DOMCTL static inline int hvm_vmtrace_control(struct vcpu *v, bool enable, bool reset) { if ( hvm_funcs.vmtrace_control ) @@ -747,6 +752,7 @@ static inline int hvm_vmtrace_control(struct vcpu *v, bool enable, bool reset) return -EOPNOTSUPP; } +#endif /* Returns -errno, or a boolean of whether tracing is currently active. */ static inline int hvm_vmtrace_output_position(struct vcpu *v, uint64_t *pos) @@ -757,6 +763,7 @@ static inline int hvm_vmtrace_output_position(struct vcpu *v, uint64_t *pos) return -EOPNOTSUPP; } +#ifdef CONFIG_DOMCTL static inline int hvm_vmtrace_set_option( struct vcpu *v, uint64_t key, uint64_t value) { @@ -774,6 +781,7 @@ static inline int hvm_vmtrace_get_option( return -EOPNOTSUPP; } +#endif static inline int hvm_vmtrace_reset(struct vcpu *v) { @@ -938,16 +946,19 @@ static inline bool hvm_has_set_descriptor_access_exiting(void) } #endif /* CONFIG_VM_EVENT */ +#ifdef CONFIG_DOMCTL static inline int hvm_vmtrace_control(struct vcpu *v, bool enable, bool reset) { return -EOPNOTSUPP; } +#endif static inline int hvm_vmtrace_output_position(struct vcpu *v, uint64_t *pos) { return -EOPNOTSUPP; } +#ifdef CONFIG_DOMCTL static inline int hvm_vmtrace_set_option( struct vcpu *v, uint64_t key, uint64_t value) { @@ -959,6 +970,7 @@ static inline int hvm_vmtrace_get_option( { return -EOPNOTSUPP; } +#endif /* CONFIG_DOMCTL */ static inline uint64_t hvm_get_reg(struct vcpu *v, unsigned int reg) { diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h index 9c92f67443..e20c1a0d4a 100644 --- a/xen/arch/x86/include/asm/p2m.h +++ b/xen/arch/x86/include/asm/p2m.h @@ -20,7 +20,7 @@ #include /* for pagetable_t */ /* Debugging and auditing of the P2M code? */ -#if !defined(NDEBUG) && defined(CONFIG_HVM) +#if !defined(NDEBUG) && defined(CONFIG_HVM) && defined(CONFIG_DOMCTL) #define P2M_AUDIT 1 #else #define P2M_AUDIT 0 diff --git a/xen/arch/x86/include/asm/paging.h b/xen/arch/x86/include/asm/paging.h index 956b83215c..c35ef44fff 100644 --- a/xen/arch/x86/include/asm/paging.h +++ b/xen/arch/x86/include/asm/paging.h @@ -55,7 +55,7 @@ #define PG_translate 0 #define PG_external 0 #endif -#if defined(CONFIG_HVM) +#if defined(CONFIG_HVM) && defined(CONFIG_DOMCTL) /* Enable log dirty mode */ #define PG_log_dirty (XEN_DOMCTL_SHADOW_ENABLE_LOG_DIRTY << PG_mode_shift) #else diff --git a/xen/arch/x86/mm/mem_sharing.c b/xen/arch/x86/mm/mem_sharing.c index 7858565429..74706da2f9 100644 --- a/xen/arch/x86/mm/mem_sharing.c +++ b/xen/arch/x86/mm/mem_sharing.c @@ -2317,6 +2317,7 @@ out: return rc; } +#ifdef CONFIG_DOMCTL int mem_sharing_domctl(struct domain *d, struct xen_domctl_mem_sharing_op *mec) { int rc; @@ -2334,6 +2335,7 @@ int mem_sharing_domctl(struct domain *d, struct xen_domctl_mem_sharing_op *mec) return rc; } +#endif /* CONFIG_DOMCTL */ void arch_dump_shared_mem_info(void) { diff --git a/xen/include/xsm/xsm.h b/xen/include/xsm/xsm.h index 6bbf3df702..86a1aa5d06 100644 --- a/xen/include/xsm/xsm.h +++ b/xen/include/xsm/xsm.h @@ -64,8 +64,8 @@ struct xsm_ops { #endif #ifdef CONFIG_DOMCTL int (*set_target)(struct domain *d, struct domain *e); -#endif int (*domctl)(struct domain *d, unsigned int cmd, uint32_t ssidref); +#endif int (*sysctl)(int cmd); int (*readconsole)(uint32_t clear); @@ -115,9 +115,9 @@ struct xsm_ops { int (*map_domain_irq)(struct domain *d, int irq, const void *data); int (*unmap_domain_pirq)(struct domain *d); int (*unmap_domain_irq)(struct domain *d, int irq, const void *data); +#ifdef CONFIG_DOMCTL int (*bind_pt_irq)(struct domain *d, struct xen_domctl_bind_pt_irq *bind); int (*unbind_pt_irq)(struct domain *d, struct xen_domctl_bind_pt_irq *bind); -#ifdef CONFIG_DOMCTL int (*irq_permission)(struct domain *d, int pirq, uint8_t allow); int (*iomem_permission)(struct domain *d, uint64_t s, uint64_t e, uint8_t allow); @@ -196,10 +196,12 @@ struct xsm_ops { int (*update_va_mapping)(struct domain *d, struct domain *f, l1_pgentry_t pte); int (*priv_mapping)(struct domain *d, struct domain *t); +#ifdef CONFIG_DOMCTL int (*ioport_permission)(struct domain *d, uint32_t s, uint32_t e, uint8_t allow); int (*ioport_mapping)(struct domain *d, uint32_t s, uint32_t e, uint8_t allow); +#endif int (*pmu_op)(struct domain *d, unsigned int op); #endif int (*dm_op)(struct domain *d); @@ -273,13 +275,13 @@ static inline int xsm_set_target( { return alternative_call(xsm_ops.set_target, d, e); } -#endif static inline int xsm_domctl(xsm_default_t def, struct domain *d, unsigned int cmd, uint32_t ssidref) { return alternative_call(xsm_ops.domctl, d, cmd, ssidref); } +#endif /* CONFIG_DOMCTL */ static inline int xsm_sysctl(xsm_default_t def, int cmd) { @@ -509,6 +511,7 @@ static inline int xsm_unmap_domain_irq( return alternative_call(xsm_ops.unmap_domain_irq, d, irq, data); } +#ifdef CONFIG_DOMCTL static inline int xsm_bind_pt_irq( xsm_default_t def, struct domain *d, struct xen_domctl_bind_pt_irq *bind) { @@ -521,7 +524,6 @@ static inline int xsm_unbind_pt_irq( return alternative_call(xsm_ops.unbind_pt_irq, d, bind); } -#ifdef CONFIG_DOMCTL static inline int xsm_irq_permission( xsm_default_t def, struct domain *d, int pirq, uint8_t allow) { @@ -759,6 +761,7 @@ static inline int xsm_priv_mapping( return alternative_call(xsm_ops.priv_mapping, d, t); } +#ifdef CONFIG_DOMCTL static inline int xsm_ioport_permission( xsm_default_t def, struct domain *d, uint32_t s, uint32_t e, uint8_t allow) { @@ -770,6 +773,7 @@ static inline int xsm_ioport_mapping( { return alternative_call(xsm_ops.ioport_mapping, d, s, e, allow); } +#endif /* CONFIG_DOMCTL */ static inline int xsm_pmu_op( xsm_default_t def, struct domain *d, unsigned int op) diff --git a/xen/lib/x86/Makefile b/xen/lib/x86/Makefile index 780ea05db1..77f2831e84 100644 --- a/xen/lib/x86/Makefile +++ b/xen/lib/x86/Makefile @@ -1,3 +1,3 @@ obj-y += cpuid.o obj-y += msr.o -obj-y += policy.o +obj-$(CONFIG_DOMCTL) += policy.o diff --git a/xen/xsm/dummy.c b/xen/xsm/dummy.c index b5174e610b..04b9b4e579 100644 --- a/xen/xsm/dummy.c +++ b/xen/xsm/dummy.c @@ -26,8 +26,8 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { #endif #ifdef CONFIG_DOMCTL .set_target = xsm_set_target, -#endif .domctl = xsm_domctl, +#endif #ifdef CONFIG_SYSCTL .sysctl = xsm_sysctl, .readconsole = xsm_readconsole, @@ -75,9 +75,9 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { .map_domain_irq = xsm_map_domain_irq, .unmap_domain_pirq = xsm_unmap_domain_pirq, .unmap_domain_irq = xsm_unmap_domain_irq, +#ifdef CONFIG_DOMCTL .bind_pt_irq = xsm_bind_pt_irq, .unbind_pt_irq = xsm_unbind_pt_irq, -#ifdef CONFIG_DOMCTL .irq_permission = xsm_irq_permission, .iomem_permission = xsm_iomem_permission, #endif @@ -149,8 +149,10 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { .mmuext_op = xsm_mmuext_op, .update_va_mapping = xsm_update_va_mapping, .priv_mapping = xsm_priv_mapping, +#ifdef CONFIG_DOMCTL .ioport_permission = xsm_ioport_permission, .ioport_mapping = xsm_ioport_mapping, +#endif .pmu_op = xsm_pmu_op, #endif .dm_op = xsm_dm_op, diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index 254e1323e5..00c4ac94e6 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -669,7 +669,6 @@ static int cf_check flask_set_target(struct domain *d, struct domain *t) &dsec->target_sid); return rc; } -#endif /* CONFIG_DOMCTL */ static int cf_check flask_domctl(struct domain *d, unsigned int cmd, uint32_t ssidref) @@ -861,6 +860,7 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd, return avc_unknown_permission("domctl", cmd); } } +#endif /* CONFIG_DOMCTL */ #ifdef CONFIG_SYSCTL static int cf_check flask_sysctl(int cmd) @@ -1082,6 +1082,7 @@ static int cf_check flask_unmap_domain_irq( return rc; } +#ifdef CONFIG_DOMCTL static int cf_check flask_bind_pt_irq( struct domain *d, struct xen_domctl_bind_pt_irq *bind) { @@ -1115,7 +1116,6 @@ static int cf_check flask_unbind_pt_irq( return current_has_perm(d, SECCLASS_RESOURCE, RESOURCE__REMOVE); } -#ifdef CONFIG_DOMCTL static int cf_check flask_irq_permission( struct domain *d, int pirq, uint8_t access) { @@ -1640,6 +1640,7 @@ static int cf_check flask_shadow_control(struct domain *d, uint32_t op) } #endif /* PG_log_dirty */ +#ifdef CONFIG_DOMCTL struct ioport_has_perm_data { uint32_t ssid; uint32_t dsid; @@ -1695,6 +1696,7 @@ static int cf_check flask_ioport_mapping( { return flask_ioport_permission(d, start, end, access); } +#endif /* CONFIG_DOMCTL */ static int cf_check flask_mem_sharing_op( struct domain *d, struct domain *cd, int op) @@ -1904,8 +1906,8 @@ static const struct xsm_ops __initconst_cf_clobber flask_ops = { #endif #ifdef CONFIG_DOMCTL .set_target = flask_set_target, -#endif .domctl = flask_domctl, +#endif #ifdef CONFIG_SYSCTL .sysctl = flask_sysctl, .readconsole = flask_readconsole, @@ -1953,9 +1955,9 @@ static const struct xsm_ops __initconst_cf_clobber flask_ops = { .map_domain_irq = flask_map_domain_irq, .unmap_domain_pirq = flask_unmap_domain_pirq, .unmap_domain_irq = flask_unmap_domain_irq, +#ifdef CONFIG_DOMCTL .bind_pt_irq = flask_bind_pt_irq, .unbind_pt_irq = flask_unbind_pt_irq, -#ifdef CONFIG_DOMCTL .irq_permission = flask_irq_permission, .iomem_permission = flask_iomem_permission, #endif @@ -2028,8 +2030,10 @@ static const struct xsm_ops __initconst_cf_clobber flask_ops = { .mmuext_op = flask_mmuext_op, .update_va_mapping = flask_update_va_mapping, .priv_mapping = flask_priv_mapping, +#ifdef CONFIG_DOMCTL .ioport_permission = flask_ioport_permission, .ioport_mapping = flask_ioport_mapping, +#endif .pmu_op = flask_pmu_op, #endif .dm_op = flask_dm_op, -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:47 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068400.1432451 (Exim 4.92) (envelope-from ) id 1uiVMd-0003uU-Lg; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:29.8808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c5869eb-f513-4f26-8017-08ddd272e700 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7903 Function domain_kill() is responsible for killing domain and relinquish domain-held resources. Tracking its calling chain, the following functions shall also be wrapped: - domain_relinquish_resource - pci_release_device - relinquish_shared_pages - paging_teardown - p2m_pod_empty_cache - relinquish_memory - pit_deinit - iommu_release_dt_devices - tee_relinquish_resources - ffa_relinquish_resources/optee_relinquish_resources - relinquish_p2m_mapping - p2m_clear_root_pages - vm_event_cleanup Signed-off-by: Penny Zheng --- xen/arch/arm/domain.c | 3 +++ xen/arch/arm/include/asm/tee/tee.h | 2 ++ xen/arch/arm/mmu/p2m.c | 4 ++++ xen/arch/arm/mpu/p2m.c | 2 ++ xen/arch/arm/tee/ffa.c | 4 ++++ xen/arch/arm/tee/optee.c | 4 ++++ xen/arch/arm/tee/tee.c | 2 ++ xen/arch/ppc/stubs.c | 2 ++ xen/arch/x86/domain.c | 2 ++ xen/arch/x86/emul-i8254.c | 2 ++ xen/arch/x86/mm/mem_sharing.c | 2 ++ xen/arch/x86/mm/p2m-pod.c | 2 ++ xen/arch/x86/mm/p2m.c | 2 ++ xen/arch/x86/mm/paging.c | 2 ++ xen/common/domain.c | 2 ++ xen/common/vm_event.c | 2 ++ xen/drivers/passthrough/device_tree.c | 2 ++ xen/drivers/passthrough/pci.c | 2 ++ 18 files changed, 43 insertions(+) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 4124d201d1..e55ff966d2 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -990,6 +990,7 @@ int arch_vcpu_reset(struct vcpu *v) return 0; } +#ifdef CONFIG_DOMCTL static int relinquish_memory(struct domain *d, struct page_list_head *list) { struct page_info *page, *tmp; @@ -1135,6 +1136,8 @@ int domain_relinquish_resources(struct domain *d) #undef PROGRESS +#endif /* CONFIG_DOMCTL */ + void arch_dump_domain_info(struct domain *d) { p2m_dump_info(d); diff --git a/xen/arch/arm/include/asm/tee/tee.h b/xen/arch/arm/include/asm/tee/tee.h index 0169fd746b..dc08e7e0ba 100644 --- a/xen/arch/arm/include/asm/tee/tee.h +++ b/xen/arch/arm/include/asm/tee/tee.h @@ -40,12 +40,14 @@ struct tee_mediator_ops { int (*domain_teardown)(struct domain *d); void (*free_domain_ctx)(struct domain *d); +#ifdef CONFIG_DOMCTL /* * Called during domain destruction to relinquish resources used * by mediator itself. This function can return -ERESTART to indicate * that it does not finished work and should be called again. */ int (*relinquish_resources)(struct domain *d); +#endif /* Handle SMCCC call for current domain. */ bool (*handle_call)(struct cpu_user_regs *regs); diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 51abf3504f..4b13867fa2 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1243,6 +1243,7 @@ static void p2m_invalidate_table(struct p2m_domain *p2m, mfn_t mfn) p2m->need_flush = true; } +#ifdef CONFIG_DOMCTL /* * The domain will not be scheduled anymore, so in theory we should * not need to flush the TLBs. Do it for safety purpose. @@ -1262,6 +1263,7 @@ void p2m_clear_root_pages(struct p2m_domain *p2m) p2m_write_unlock(p2m); } +#endif /* CONFIG_DOMCTL */ /* * Invalidate all entries in the root page-tables. This is @@ -1556,6 +1558,7 @@ int p2m_init(struct domain *d) return 0; } +#ifdef CONFIG_DOMCTL /* * The function will go through the p2m and remove page reference when it * is required. The mapping will be removed from the p2m. @@ -1626,6 +1629,7 @@ int relinquish_p2m_mapping(struct domain *d) return rc; } +#endif /* CONFIG_DOMCTL */ /* * Clean & invalidate RAM associated to the guest vCPU. diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index f7fb58ab6a..e8c5665ab9 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -57,10 +57,12 @@ bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) void p2m_flush_vm(struct vcpu *v) {} +#ifdef CONFIG_DOMCTL int relinquish_p2m_mapping(struct domain *d) { return 0; } +#endif /* CONFIG_DOMCTL */ void p2m_domain_creation_finished(struct domain *d) {} diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c index 3bbdd7168a..bb9b50932c 100644 --- a/xen/arch/arm/tee/ffa.c +++ b/xen/arch/arm/tee/ffa.c @@ -434,10 +434,12 @@ static void ffa_free_domain_ctx(struct domain *d) XFREE(d->arch.tee); } +#ifdef CONFIG_DOMCTL static int ffa_relinquish_resources(struct domain *d) { return 0; } +#endif /* CONFIG_DOMCTL */ static void ffa_init_secondary(void) { @@ -559,7 +561,9 @@ static const struct tee_mediator_ops ffa_ops = .domain_init = ffa_domain_init, .domain_teardown = ffa_domain_teardown, .free_domain_ctx = ffa_free_domain_ctx, +#ifdef CONFIG_DOMCTL .relinquish_resources = ffa_relinquish_resources, +#endif .handle_call = ffa_handle_call, }; diff --git a/xen/arch/arm/tee/optee.c b/xen/arch/arm/tee/optee.c index 5151bd90ed..8d91df4e23 100644 --- a/xen/arch/arm/tee/optee.c +++ b/xen/arch/arm/tee/optee.c @@ -632,6 +632,7 @@ static void free_optee_shm_buf_pg_list(struct optee_domain *ctx, cookie); } +#ifdef CONFIG_DOMCTL static int optee_relinquish_resources(struct domain *d) { struct arm_smccc_res resp; @@ -693,6 +694,7 @@ static int optee_relinquish_resources(struct domain *d) return 0; } +#endif /* CONFIG_DOMCTL */ #define PAGELIST_ENTRIES_PER_PAGE \ ((OPTEE_MSG_NONCONTIG_PAGE_SIZE / sizeof(u64)) - 1) @@ -1727,7 +1729,9 @@ static const struct tee_mediator_ops optee_ops = .probe = optee_probe, .domain_init = optee_domain_init, .domain_teardown = optee_domain_teardown, +#ifdef CONFIG_DOMCTL .relinquish_resources = optee_relinquish_resources, +#endif .handle_call = optee_handle_call, }; diff --git a/xen/arch/arm/tee/tee.c b/xen/arch/arm/tee/tee.c index 3f65e45a78..c97b19cd6f 100644 --- a/xen/arch/arm/tee/tee.c +++ b/xen/arch/arm/tee/tee.c @@ -60,6 +60,7 @@ int tee_domain_teardown(struct domain *d) return cur_mediator->ops->domain_teardown(d); } +#ifdef CONFIG_DOMCTL int tee_relinquish_resources(struct domain *d) { if ( !cur_mediator ) @@ -67,6 +68,7 @@ int tee_relinquish_resources(struct domain *d) return cur_mediator->ops->relinquish_resources(d); } +#endif /* CONFIG_DOMCTL */ uint16_t tee_get_type(void) { diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c index b2b97c6eb7..0d8563f11f 100644 --- a/xen/arch/ppc/stubs.c +++ b/xen/arch/ppc/stubs.c @@ -263,10 +263,12 @@ int arch_vcpu_reset(struct vcpu *v) BUG_ON("unimplemented"); } +#ifdef CONFIG_DOMCTL int domain_relinquish_resources(struct domain *d) { BUG_ON("unimplemented"); } +#endif /* CONFIG_DOMCTL */ void arch_dump_domain_info(struct domain *d) { diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 13ccaf1c79..a0d650cb86 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -2235,6 +2235,7 @@ void sync_vcpu_execstate(struct vcpu *v) read_atomic(&v->dirty_cpu) != dirty_cpu); } +#ifdef CONFIG_DOMCTL static int relinquish_memory( struct domain *d, struct page_list_head *list, unsigned long type) { @@ -2559,6 +2560,7 @@ int domain_relinquish_resources(struct domain *d) return 0; } +#endif /* CONFIG_DOMCTL */ void arch_dump_domain_info(struct domain *d) { diff --git a/xen/arch/x86/emul-i8254.c b/xen/arch/x86/emul-i8254.c index 144aa168a3..bb9718bb97 100644 --- a/xen/arch/x86/emul-i8254.c +++ b/xen/arch/x86/emul-i8254.c @@ -651,6 +651,7 @@ void pit_init(struct domain *d) pit_reset(d); } +#ifdef CONFIG_DOMCTL void pit_deinit(struct domain *d) { PITState *pit = domain_vpit(d); @@ -664,6 +665,7 @@ void pit_deinit(struct domain *d) destroy_periodic_time(&pit->pt0); } } +#endif /* CONFIG_DOMCTL */ /* * Local variables: diff --git a/xen/arch/x86/mm/mem_sharing.c b/xen/arch/x86/mm/mem_sharing.c index da28266ef0..7858565429 100644 --- a/xen/arch/x86/mm/mem_sharing.c +++ b/xen/arch/x86/mm/mem_sharing.c @@ -1391,6 +1391,7 @@ int __mem_sharing_unshare_page(struct domain *d, return rc; } +#ifdef CONFIG_DOMCTL int relinquish_shared_pages(struct domain *d) { int rc = 0; @@ -1447,6 +1448,7 @@ int relinquish_shared_pages(struct domain *d) p2m_unlock(p2m); return rc; } +#endif /* CONFIG_DOMCTL */ static int range_share(struct domain *d, struct domain *cd, struct mem_sharing_op_range *range) diff --git a/xen/arch/x86/mm/p2m-pod.c b/xen/arch/x86/mm/p2m-pod.c index 05633fe2ac..98a846bb55 100644 --- a/xen/arch/x86/mm/p2m-pod.c +++ b/xen/arch/x86/mm/p2m-pod.c @@ -366,6 +366,7 @@ void p2m_pod_get_mem_target(const struct domain *d, xen_pod_target_t *target) pod_unlock(p2m); } +#ifdef CONFIG_DOMCTL int p2m_pod_empty_cache(struct domain *d) { struct p2m_domain *p2m = p2m_get_hostp2m(d); @@ -409,6 +410,7 @@ int p2m_pod_empty_cache(struct domain *d) unlock_page_alloc(p2m); return p2m->pod.count ? -ERESTART : 0; } +#endif /* CONFIG_DOMCTL */ int p2m_pod_offline_or_broken_hit(struct page_info *p) diff --git a/xen/arch/x86/mm/p2m.c b/xen/arch/x86/mm/p2m.c index b9a7c2dc53..c2840131ad 100644 --- a/xen/arch/x86/mm/p2m.c +++ b/xen/arch/x86/mm/p2m.c @@ -2088,6 +2088,7 @@ int xenmem_add_to_physmap_one( return rc; } +#ifdef CONFIG_DOMCTL /* * Remove foreign mappings from the p2m, as that drops the page reference taken * when mapped. @@ -2151,6 +2152,7 @@ int relinquish_p2m_mapping(struct domain *d) return rc; } +#endif /* CONFIG_DOMCTL */ /* * Local variables: diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c index 1216a181c3..3da99ad371 100644 --- a/xen/arch/x86/mm/paging.c +++ b/xen/arch/x86/mm/paging.c @@ -768,6 +768,7 @@ void paging_vcpu_teardown(struct vcpu *v) shadow_vcpu_teardown(v); } +#ifdef CONFIG_DOMCTL /* Call when destroying a domain */ int paging_teardown(struct domain *d) { @@ -794,6 +795,7 @@ int paging_teardown(struct domain *d) return rc; } +#endif /* CONFIG_DOMCTL */ /* Call once all of the references to the domain have gone away */ void paging_final_teardown(struct domain *d) diff --git a/xen/common/domain.c b/xen/common/domain.c index 604217d782..be722c9f09 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1222,6 +1222,7 @@ int rcu_lock_live_remote_domain_by_id(domid_t dom, struct domain **d) return 0; } +#ifdef CONFIG_DOMCTL int domain_kill(struct domain *d) { int rc = 0; @@ -1272,6 +1273,7 @@ int domain_kill(struct domain *d) return rc; } +#endif /* CONFIG_DOMCTL */ void __domain_crash(struct domain *d) diff --git a/xen/common/vm_event.c b/xen/common/vm_event.c index 1666ff615f..102745117e 100644 --- a/xen/common/vm_event.c +++ b/xen/common/vm_event.c @@ -559,6 +559,7 @@ static void cf_check mem_sharing_notification(struct vcpu *v, unsigned int port) } #endif +#ifdef CONFIG_DOMCTL /* Clean up on domain destruction */ void vm_event_cleanup(struct domain *d) { @@ -589,6 +590,7 @@ void vm_event_cleanup(struct domain *d) } #endif } +#endif /* CONFIG_DOMCTL */ int vm_event_domctl(struct domain *d, struct xen_domctl_vm_event_op *vec) { diff --git a/xen/drivers/passthrough/device_tree.c b/xen/drivers/passthrough/device_tree.c index f5850a2607..704910de3d 100644 --- a/xen/drivers/passthrough/device_tree.c +++ b/xen/drivers/passthrough/device_tree.c @@ -108,6 +108,7 @@ int iommu_dt_domain_init(struct domain *d) return 0; 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pr=C From: Penny Zheng To: CC: , Penny Zheng , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , "Julien Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , "Daniel P. Smith" Subject: [PATCH v1 17/25] xen: add stub for XEN_DOMCTL_getdomaininfo Date: Sun, 3 Aug 2025 17:47:30 +0800 Message-ID: <20250803094738.3625269-18-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231E:EE_|DM6PR12MB4450:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f44547e-348b-4287-c7b3-08ddd272f2e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?hH3cN1bSLziJoOeZlSoapnFhBCJAAfYoBmsa75u+PvFVvPIwWfHwWrY0Fx6a?= =?us-ascii?Q?0Gt3+cjJrLgUKo6PzGKuwOoT0vv1+lXvWLc22vDenJY0wWryV4Sa8+PHZzZT?= =?us-ascii?Q?m+XvEf42FB/u2sV6lQ90asbNHu3YKHVb2R1jtqb3wmUgZPK+URRu52S32Cpg?= =?us-ascii?Q?SmLK8iYHQf1nelhQJaAC68QqrnvHvQ9/gj+yz+EsmhIUGXQfS1okIHTwjjxi?= =?us-ascii?Q?64+fhf1gjdtmPgsgu4z0jbpbk0N+Fd5l5csAg2EhgcOnifX0DTrJp5PqQxTM?= =?us-ascii?Q?St9IscFq9TEjR/sj8vmdSJCzkJcxF26ntV2q8aSSmaBhu/d17NppclvMO9Gl?= =?us-ascii?Q?AiYa4h78GRu4LHcSbKb24kSsfK6db7tHksgfmIeihrSNtcnpk4T1BZgk36X9?= =?us-ascii?Q?YHbevkd2fsZ4KlglRJhcjraxExJoyP7PYu1cQGexP7PHJza/RzFw6O8op4Xk?= =?us-ascii?Q?t2nuAY/PosjH5Loi1RgjJld/avD2TVMhnNEtWZ4UpS7nMXXAmZ76LOLGHbGP?= =?us-ascii?Q?tJ3mOPDjTOiUAsKPuWsCdEecx3MqzaIJvsFm1TeHCxktfqAhwJ7OmwimK8NU?= =?us-ascii?Q?3iBvwc2/WF8mhgnTJ3tqf+jpYW05X/MVP5ff+R9ffR3Hh1iBd1boybZ8RrzS?= =?us-ascii?Q?BXQj3mKPpD1bRTA5xkiGfWMlnw1giHDn99fI8O17yDAo8w1LUtdbT2H2TUxT?= =?us-ascii?Q?L5mzK+nlRyHtVcctwdGOGHW9nOQLEsi1vvQzWPn63MKFRPj5cgl4ximP6Iwe?= =?us-ascii?Q?s4aG6GDNAw11qf8/JjUZ+vGwC5K85Tf0P5TgJH4XCCiH6zFuiBjbew/6ERez?= =?us-ascii?Q?2JjEzsQKRGF/w0Oquhjl+dmQpJm2NiMfBh7miCozwv5rmvb4oHQL8lD5fOnS?= =?us-ascii?Q?9tGpUFlgRdoV6MlO4BjQBf22wBcqk7sl0SlYN5/IL/FPkUuSxfL2nprTOgmL?= =?us-ascii?Q?UajJcdl0dUX3A4UejA6D5tRtP4/zjj7cr+BdoL8g27rt1jAmvvaZa187zu8T?= =?us-ascii?Q?NoTDQbkMEus0yw2HokfDU4gq4/AlmFztxK939tKiUeYwWXIL45qmy9QGrK6V?= =?us-ascii?Q?x5BbS8LkABPQm6iXLbBe5YKNKf4LISNlX1jRpmtW/vWcyo/U3Imc8g1TnVcC?= =?us-ascii?Q?iuX4chB1dk8a1eQe4V1HWNHKIplI+UQteRUpinz/kRYCbaBiB7hS2Lwjto3f?= =?us-ascii?Q?jeIkLpyi9SA1kRzC6uspxhIPlmuifnaQci1aYWrvIBCWOSCf/JKUcKRky3w/?= =?us-ascii?Q?gF3mZBIv7IAdlKi2Ts8Nh/SwQLUxV/XkVbGCErkLZvRvJ2ZAXnyUJxAS11me?= =?us-ascii?Q?/muW+O3rWJyJQks0lGYs8suJkXD9jTxO9LiarGx9d/arxTxtvyCsFWLuNH82?= =?us-ascii?Q?I7nE4UeIXOY+799lWyUNsJ2sk5ENU8nXTu4fY96RO4udcbLMdIwDVmh4lQqZ?= =?us-ascii?Q?sK5yOuXurK/g1iqPv5gaXcvF9Prtfm98P+eV0vC/d1JU2KFlb0RooSGj8Aql?= =?us-ascii?Q?mbKnkLyGzqwgZZbH1r/lQzNHyfNPSNzwO1Ls?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:49.8566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f44547e-348b-4287-c7b3-08ddd272f2e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4450 Function getdomaininfo() is designed for XEN_DOMCTL_getdomaininfo domctl-op to get per-domain info in userspace, so it shall be guarded with CONFIG_DOMCTL. We need to provide stub for getdomaininfo(), as it still could be invoked by XEN_SYSCTL_getdomaininfolist sysctl-op when CONFIG_DOMCTL=n. The same logic goes for xsm_getdomaininfo() too. Signed-off-by: Penny Zheng --- xen/include/xen/domain.h | 5 +++++ xen/include/xsm/xsm.h | 6 +++++- xen/xsm/dummy.c | 2 +- xen/xsm/flask/hooks.c | 4 ++-- 4 files changed, 13 insertions(+), 4 deletions(-) diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h index b45ac91760..55befdb256 100644 --- a/xen/include/xen/domain.h +++ b/xen/include/xen/domain.h @@ -31,8 +31,13 @@ int vcpu_up(struct vcpu *v); void setup_system_domains(void); +#ifdef CONFIG_DOMCTL struct xen_domctl_getdomaininfo; void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info); +#else +static inline void getdomaininfo(struct domain *d, + struct xen_domctl_getdomaininfo *info) {} +#endif /* CONFIG_DOMCTL */ void arch_get_domain_info(const struct domain *d, struct xen_domctl_getdomaininfo *info); diff --git a/xen/include/xsm/xsm.h b/xen/include/xsm/xsm.h index 55f8d0903e..db98496869 100644 --- a/xen/include/xsm/xsm.h +++ b/xen/include/xsm/xsm.h @@ -55,8 +55,8 @@ struct xsm_ops { void (*security_domaininfo)(struct domain *d, struct xen_domctl_getdomaininfo *info); int (*domain_create)(struct domain *d, uint32_t ssidref); - int (*getdomaininfo)(struct domain *d); #ifdef CONFIG_DOMCTL + int (*getdomaininfo)(struct domain *d); int (*domctl_scheduler_op)(struct domain *d, int op); #endif #ifdef CONFIG_SYSCTL @@ -240,7 +240,11 @@ static inline int xsm_domain_create( static inline int xsm_getdomaininfo(xsm_default_t def, struct domain *d) { +#ifdef CONFIG_DOMCTL return alternative_call(xsm_ops.getdomaininfo, d); +#else + return -EOPNOTSUPP; +#endif } static inline int xsm_get_domain_state(xsm_default_t def, struct domain *d) diff --git a/xen/xsm/dummy.c b/xen/xsm/dummy.c index cd5358dd1e..b7eb061e9b 100644 --- a/xen/xsm/dummy.c +++ b/xen/xsm/dummy.c @@ -17,8 +17,8 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { .set_system_active = xsm_set_system_active, .security_domaininfo = xsm_security_domaininfo, .domain_create = xsm_domain_create, - .getdomaininfo = xsm_getdomaininfo, #ifdef CONFIG_DOMCTL + .getdomaininfo = xsm_getdomaininfo, .domctl_scheduler_op = xsm_domctl_scheduler_op, #endif #ifdef CONFIG_SYSCTL diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index 2975d2906f..9f829aa53b 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -604,12 +604,12 @@ static int cf_check flask_domain_create(struct domain *d, uint32_t ssidref) return rc; } +#ifdef CONFIG_DOMCTL static int cf_check flask_getdomaininfo(struct domain *d) { return current_has_perm(d, SECCLASS_DOMAIN, DOMAIN__GETDOMAININFO); } -#ifdef CONFIG_DOMCTL static int cf_check flask_domctl_scheduler_op(struct domain *d, int op) { switch ( op ) @@ -1895,8 +1895,8 @@ static const struct xsm_ops __initconst_cf_clobber flask_ops = { .set_system_active = flask_set_system_active, .security_domaininfo = flask_security_domaininfo, .domain_create = flask_domain_create, - .getdomaininfo = flask_getdomaininfo, #ifdef CONFIG_DOMCTL + .getdomaininfo = flask_getdomaininfo, .domctl_scheduler_op = flask_domctl_scheduler_op, #endif #ifdef CONFIG_SYSCTL -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:51 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068407.1432480 (Exim 4.92) (envelope-from ) id 1uiVMh-0004rS-4p; Sun, 03 Aug 2025 09:50:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068407.1432480; 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pr=C From: Penny Zheng To: CC: , Penny Zheng , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD , Michal Orzel , "Julien Grall" , Stefano Stabellini Subject: [PATCH v1 25/25] xen/domctl: wrap around domctl hypercall Date: Sun, 3 Aug 2025 17:47:38 +0800 Message-ID: <20250803094738.3625269-26-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|MW6PR12MB8960:EE_ X-MS-Office365-Filtering-Correlation-Id: e210ab8b-0961-47d4-0682-08ddd2730189 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:49:14.3958 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e210ab8b-0961-47d4-0682-08ddd2730189 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8960 Wrap domctl hypercall def and domctl.o with CONFIG_DOMCTL We need to make DOMCTL with prompt back, add help info and set default value as y. We shall at least provide "# CONFIG_DOMCTL is not set" in preset configs for PV shim on x86. Signed-off-by: Penny Zheng --- xen/arch/x86/configs/pvshim_defconfig | 1 + xen/common/Kconfig | 5 ++++- xen/common/Makefile | 2 +- xen/include/hypercall-defs.c | 4 ++++ 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/configs/pvshim_defconfig b/xen/arch/x86/configs/pvshim_defconfig index c58c29adb0..c100b84fa8 100644 --- a/xen/arch/x86/configs/pvshim_defconfig +++ b/xen/arch/x86/configs/pvshim_defconfig @@ -25,3 +25,4 @@ CONFIG_EXPERT=y # CONFIG_DEBUG is not set # CONFIG_GDBSX is not set # CONFIG_SYSCTL is not set +# CONFIG_DOMCTL is not set diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 24a7b83af9..31db3d448b 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -629,7 +629,10 @@ config SYSCTL config DOMCTL bool "Enable domctl hypercall" - def_bool y + default y + help + This option shall only be disabled on some dom0less systems, or + PV shim on x86, to reduce Xen footprint. endmenu diff --git a/xen/common/Makefile b/xen/common/Makefile index 756ddf52c3..fc83a45b60 100644 --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -11,7 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/ obj-$(CONFIG_IOREQ_SERVER) += dm.o obj-y += domain.o -obj-y += domctl.o +obj-$(CONFIG_DOMCTL) += domctl.o obj-y += event_2l.o obj-y += event_channel.o obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o diff --git a/xen/include/hypercall-defs.c b/xen/include/hypercall-defs.c index c70f745ac2..ccc38e5e22 100644 --- a/xen/include/hypercall-defs.c +++ b/xen/include/hypercall-defs.c @@ -197,7 +197,9 @@ dm_op(domid_t domid, unsigned int nr_bufs, xen_dm_op_buf_t *bufs) #ifdef CONFIG_SYSCTL sysctl(xen_sysctl_t *u_sysctl) #endif +#ifdef CONFIG_DOMCTL domctl(xen_domctl_t *u_domctl) +#endif #if PG_log_dirty paging_domctl_cont(xen_domctl_t *u_domctl) #endif @@ -280,7 +282,9 @@ hvm_op do do do do do #ifdef CONFIG_SYSCTL sysctl do do do do do #endif +#ifdef CONFIG_DOMCTL domctl do do do do do +#endif #ifdef CONFIG_KEXEC kexec_op compat do - - - #endif -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:53 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068410.1432490 (Exim 4.92) (envelope-from ) id 1uiVMi-0005Jg-Py; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:55.7797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ab5d1a9-e408-48c8-61e3-08ddd272f670 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6144 VM event could only be enabled/disabled via vm_event domctl-op, so CONFIG_VM_EVENT shall depend on CONFIG_DOMCTL Signed-off-by: Penny Zheng --- xen/common/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/common/Kconfig b/xen/common/Kconfig index bf1850c154..24a7b83af9 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -145,7 +145,7 @@ config MEM_ACCESS_ALWAYS_ON config VM_EVENT def_bool MEM_ACCESS_ALWAYS_ON prompt "Memory Access and VM events" if !MEM_ACCESS_ALWAYS_ON - depends on HVM + depends on HVM && DOMCTL help Framework to configure memory access types for guests and receive -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:55 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068419.1432503 (Exim 4.92) (envelope-from ) id 1uiVMl-0005oR-G6; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:58.5301 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c46e3e9-4a44-4a30-1aa0-08ddd272f814 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9703 Function set_global_virq_handler() is reponsible for XEN_DOMCTL_set_virq_handler domctl-op, and shall be wrapped. Signed-off-by: Penny Zheng --- xen/common/event_channel.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c index 67700b050a..e11b677cac 100644 --- a/xen/common/event_channel.c +++ b/xen/common/event_channel.c @@ -1006,6 +1006,7 @@ void send_global_virq(uint32_t virq) send_guest_domain_virq(get_global_virq_handler(virq), virq); } +#ifdef CONFIG_DOMCTL int set_global_virq_handler(struct domain *d, uint32_t virq) { struct domain *old, *hdl; @@ -1068,6 +1069,7 @@ int set_global_virq_handler(struct domain *d, uint32_t virq) return rc; } +#endif /* CONFIG_DOMCTL */ static void clear_global_virq_handlers(struct domain *d) { -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:50:57 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:50:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068425.1432512 (Exim 4.92) (envelope-from ) id 1uiVMn-0006G9-IH; Sun, 03 Aug 2025 09:50:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068425.1432512; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:32.6151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fae9d576-6f7b-4258-ad12-08ddd272e8a1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5772 Function domain_set_node_affinity() is responsible for XEN_DOMCTL_setnodeaffinity domctl-op, and shall be wrapped with CONFIG_DOMCTL Signed-off-by: Penny Zheng --- xen/common/domain.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/common/domain.c b/xen/common/domain.c index be722c9f09..22313d761b 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1097,6 +1097,7 @@ void __init setup_system_domains(void) #endif } +#ifdef CONFIG_DOMCTL int domain_set_node_affinity(struct domain *d, const nodemask_t *affinity) { /* Being disjoint with the system is just wrong. */ @@ -1125,6 +1126,7 @@ out: return 0; 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Smith" Subject: [PATCH v1 14/25] xen/domctl: wrap around XEN_DOMCTL_{irq_permission,iomem_permission} Date: Sun, 3 Aug 2025 17:47:27 +0800 Message-ID: <20250803094738.3625269-15-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231E:EE_|PH7PR12MB5593:EE_ X-MS-Office365-Filtering-Correlation-Id: 0277a6d2-5527-4af7-c3be-08ddd272ef43 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?1iQTy6VvR/y7RXjnJfwO2WuEP+LdunD4EjYM5LWl9zb0RahEQxerjs3DPBZG?= =?us-ascii?Q?egXc0O5jsm5nQVrFrJfOvKdXIfSrkPU/kGmurtqQNTyA8MG9ElahEd+H+lli?= =?us-ascii?Q?aZ94Feadl4pDB9eskl1pvID9wkqlR//SWEt9fQa5sGWSvH5BE6viGAadR7T6?= =?us-ascii?Q?vxzIgSL5fU71py2u91ijesTjKU8k5+vQpwn7ti0R0YFoW/vSz049wO2Oqpe1?= =?us-ascii?Q?Q11bmbxUceoLjHg1C1mi2uyOpoGsvZqLIHYRYwWNew0WHt+ub9V8VKrcNGoE?= =?us-ascii?Q?HcyZdy3mt6tmiWU3EoEmHN16/gM5H6PYt6II8Y1ISYgRmd03M1/Yu6zqUqnd?= =?us-ascii?Q?QQZnaJoQD9PW3Iij7cfaT2tKEUv71UIiA3L3Klz50UTL9bCfEze1AiXv33Ph?= =?us-ascii?Q?bbGqwVEM0vY2NoIsWkAJrM18x163Pz2dv69o5+I1gLja/tV97LKLRg/rMq0C?= =?us-ascii?Q?6phC7/ETc/0UjpL1H9fS9Z+VDC+XuaLJRtO3eNznxuUaLGHm15vUnXv/RoOl?= =?us-ascii?Q?Iz/s2eVhJJ+opZct2XREx4nV+vAraeEBsHMZlbjCikFQGk4jyQSymQMP8ZX9?= =?us-ascii?Q?M9kynGiBzDkfnVH1ZwMX2ns4zz69+ChZGwwY6G2D7TOkCZYf0zQ36up9PmYF?= =?us-ascii?Q?71B969F+HJe6hX2N5eWuOmOp5QBh+q32jIQ0ZnEH2YZ7SJtezyUrQQ/xGB3S?= =?us-ascii?Q?Skwh3L0XlnfAymBP2ReCnxXKFbocTtz8NBmW16yHO9Tx3HO+VbxT7mm7kty2?= =?us-ascii?Q?65Q3C9q//mnAETdUs5V10lc2+2VMWsAQVgx8SUqmZBahB+6Y0O8FwmmaRkxs?= =?us-ascii?Q?dHRNw1HqWfZ5cMpCH+9edx+rKIigfyIsRjbCtTfYOEov9HZPlO9u9ajOVU2k?= =?us-ascii?Q?ssE8jpCTHJuPn+oGdlkxJouZ/ZcrYHFFF2TqBEXljdwyCI/87+GWSgyKKyF4?= =?us-ascii?Q?aG1+Rog0fKeJYD7xdCgf91inrBtaQsD1lYL3jgZO7EZehXDd86mTRGMC1YLx?= =?us-ascii?Q?QOCOMNXw8YUrmT8vbyrj1YakQL2gEm+b5xcI2C8+SAccSeexic0KXYE446SN?= =?us-ascii?Q?zM1t+FBMyfAu1MFyyq43o9G5/16/XsSV+m9inl9tbSFgfIhvhCsI8YcbxWna?= =?us-ascii?Q?DhetPcVdwkWRO1z9/Q2+JwA9lkojiV2PCK4s9lnkygKawY4broMo1nADe8E+?= =?us-ascii?Q?v/XWLBkZJEHSFwbuC8Ms7HWVVbzt2mpLuNUg0pHW3ZEIhcKEjxDOsdSXEX05?= =?us-ascii?Q?O/q+NJN1bu9DoRIhygT2HPMW2FCFiWFesUoooE1erkFgKR6ScMz1Rk0o/AWl?= =?us-ascii?Q?eXFci63hWUci0ryQNd+foFEslRv5PG7x2rHRjK8PPvrNX625SJ5QAK6m9ieL?= =?us-ascii?Q?FGiM4sTKN6sr4s5YIGKBVjvW0NkMLwxurni7fqK+teCE1oBIp12EIxcaEwSW?= =?us-ascii?Q?p6IphNQ1HgIvmIQ8BqmOzE29hOBYTQes43UWWqjpT2vk9+oadUkZrpud2Ez/?= =?us-ascii?Q?qDLIFVuJcT9xgEsntRlULZ8WDU7UrE5NzBWn?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:43.7436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0277a6d2-5527-4af7-c3be-08ddd272ef43 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5593 The following functions are invoked only under XEN_DOMCTL_{irq_permission,iomem_permission} domctl-op, and shall be wrapped: - xsm_irq_permission - xsm_iomem_permission Signed-off-by: Penny Zheng --- xen/include/xsm/dummy.h | 2 ++ xen/include/xsm/xsm.h | 4 ++++ xen/xsm/dummy.c | 2 ++ xen/xsm/flask/hooks.c | 4 ++++ 4 files changed, 12 insertions(+) diff --git a/xen/include/xsm/dummy.h b/xen/include/xsm/dummy.h index 12792c3a43..55521c012b 100644 --- a/xen/include/xsm/dummy.h +++ b/xen/include/xsm/dummy.h @@ -556,6 +556,7 @@ static XSM_INLINE int cf_check xsm_unmap_domain_irq( return xsm_default_action(action, current->domain, d); } +#ifdef CONFIG_DOMCTL static XSM_INLINE int cf_check xsm_irq_permission( XSM_DEFAULT_ARG struct domain *d, int pirq, uint8_t allow) { @@ -569,6 +570,7 @@ static XSM_INLINE int cf_check xsm_iomem_permission( XSM_ASSERT_ACTION(XSM_HOOK); return xsm_default_action(action, current->domain, d); } +#endif /* CONFIG_DOMCTL */ static XSM_INLINE int cf_check xsm_iomem_mapping( XSM_DEFAULT_ARG struct domain *d, uint64_t s, uint64_t e, uint8_t allow) diff --git a/xen/include/xsm/xsm.h b/xen/include/xsm/xsm.h index 6444f0677b..1759d49aaa 100644 --- a/xen/include/xsm/xsm.h +++ b/xen/include/xsm/xsm.h @@ -115,9 +115,11 @@ struct xsm_ops { int (*unmap_domain_irq)(struct domain *d, int irq, const void *data); int (*bind_pt_irq)(struct domain *d, struct xen_domctl_bind_pt_irq *bind); int (*unbind_pt_irq)(struct domain *d, struct xen_domctl_bind_pt_irq *bind); +#ifdef CONFIG_DOMCTL int (*irq_permission)(struct domain *d, int pirq, uint8_t allow); int (*iomem_permission)(struct domain *d, uint64_t s, uint64_t e, uint8_t allow); +#endif int (*iomem_mapping)(struct domain *d, uint64_t s, uint64_t e, uint8_t allow); int (*pci_config_permission)(struct domain *d, uint32_t machine_bdf, @@ -511,6 +513,7 @@ static inline int xsm_unbind_pt_irq( return alternative_call(xsm_ops.unbind_pt_irq, d, bind); } +#ifdef CONFIG_DOMCTL static inline int xsm_irq_permission( xsm_default_t def, struct domain *d, int pirq, uint8_t allow) { @@ -522,6 +525,7 @@ static inline int xsm_iomem_permission( { return alternative_call(xsm_ops.iomem_permission, d, s, e, allow); } +#endif /* CONFIG_DOMCTL */ static inline int xsm_iomem_mapping( xsm_default_t def, struct domain *d, uint64_t s, uint64_t e, uint8_t allow) diff --git a/xen/xsm/dummy.c b/xen/xsm/dummy.c index b8a9b581b7..2798425de2 100644 --- a/xen/xsm/dummy.c +++ b/xen/xsm/dummy.c @@ -75,8 +75,10 @@ static const struct xsm_ops __initconst_cf_clobber dummy_ops = { .unmap_domain_irq = xsm_unmap_domain_irq, .bind_pt_irq = xsm_bind_pt_irq, .unbind_pt_irq = xsm_unbind_pt_irq, +#ifdef CONFIG_DOMCTL .irq_permission = xsm_irq_permission, .iomem_permission = xsm_iomem_permission, +#endif .iomem_mapping = xsm_iomem_mapping, .pci_config_permission = xsm_pci_config_permission, .get_vnumainfo = xsm_get_vnumainfo, diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index 55da0a5ff7..8361cf94f9 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -1113,12 +1113,14 @@ static int cf_check flask_unbind_pt_irq( return current_has_perm(d, SECCLASS_RESOURCE, RESOURCE__REMOVE); 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pr=C From: Penny Zheng To: CC: , Penny Zheng , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v1 23/25] xen/x86: make CONFIG_X86_PSR depend on SYSCTL || DOMCTL Date: Sun, 3 Aug 2025 17:47:36 +0800 Message-ID: <20250803094738.3625269-24-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|LV3PR12MB9235:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e769449-15ed-4713-b2eb-08ddd2730044 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?VNBEZloTWHPaMddamAsaZ6dbCCUJAbwZmx234at7iBkWjw9bEvTpKHAqntj/?= =?us-ascii?Q?zi8mUyJbT7K42NQK2mPHvi4e05eWXrRkIWDWQp+8Mx9LRBYt3g2i/ZoXt3Oj?= =?us-ascii?Q?2NF/QV/dBlD05v44nYsHDgRVDzy4JAfuaAQZZI56zEM9jFeP9jK6NaddoxPw?= =?us-ascii?Q?n8Anc5m0tpMZBGJP49eMDowKl7iIzTPSCIBXqThzh/MXCof3OJRITW/sDADe?= =?us-ascii?Q?xxZupG6N2arFUmRAwGJz9UQSw8fHtyQDgvVO8SBREiDlv5QHYDTjYhXb0iO1?= =?us-ascii?Q?f1s0I/iOzH0Xa35sNeUk6ZJPU7QHbixpJcrKXh4ARuIHwQI4N6xS0/l5jJBb?= =?us-ascii?Q?mIXdHG+m40UeFDGGRBC7r6TEk/m8b6j+yamO2eTyhxAMw14C8jwaNeVLAGRt?= =?us-ascii?Q?HHdEG0TPWmLaDuT13D/1gMPSx9dOZFRueQih7AFonf8hpi61XuR/Om0nGim+?= =?us-ascii?Q?TErVTOyJ/bzjBtl0S2ZUmH/D6u4DexLL1pBNkjtEe4hMuyMUX+OLuZnpZdeH?= =?us-ascii?Q?XImULo4de5BAul345/w/m2bCiwB3/sFrzqYt33n9esX/BEp1Sty2mI4fRjoe?= =?us-ascii?Q?0n5R29mkIC7Ys/rR0VCg675tVS6cuC9kjfSglRR/Sgcb0LFLcCeZC3nl4+w5?= =?us-ascii?Q?PZPT0b2ZMisoYPCN0YKtWsWRnAJAA8s/eSfgFolNYx1PiBMlNibamwHBAagD?= =?us-ascii?Q?4DP2NTuScTAnut27hHRB4/+3pRCqJvcMMJwxAVHd2wzS9dhq2wxxWfmo7L1F?= =?us-ascii?Q?BCX1Lu7q7ESltQBOMxOjssGp51SP8lsYA9IJb5lF1KbqtIvUZZVmuKpR32GU?= =?us-ascii?Q?O32/6+Po30fTx620iREb0npk+Vwp6J27Sp2fquO/P5H4yOH/g4RnhYs5vkUA?= =?us-ascii?Q?53svRRaomZwDqe8tl6TTFfEjZ+hfx2386788ZhTrmmZ3ZnR8co2HP4fR3M1e?= =?us-ascii?Q?J0pI1e0HWDpQgfHrRwlVWGMepuUl4uB5pq1CwJTbad3JfCM1Co+2gNf8plOE?= =?us-ascii?Q?AJKYQTGWyKiqe1PMcozllnsa78XMWvBC9Vcl4o/4DkOcU2EYABdRrJmJcg3Q?= =?us-ascii?Q?+VAjhTBSoWlXeQXAeo4L8p/AeZs42L8w8s7BA7OPScEND4DwmjW/QaePx4aK?= =?us-ascii?Q?QrpE8OjwICv9PTyPeUf9svKDRZ+EJ6OcUDzGd2TEgjzYVUW0dpH6osmBWgZo?= =?us-ascii?Q?HtISAAPbCh1E3hMOnDGbvbNBQ8WnRPyKAdWUeMAy9mmDLM/ICfcnwKQIQ3ox?= =?us-ascii?Q?b6wVSe/AiIynvf1PQ7jJRdX67C3Jlc/wI5AKjNakcUry7/EKt0jgaflILaXb?= =?us-ascii?Q?fqLwS0u4K2RmJkDsS/7ylRDgH2qq7+jdadmDYlGzzxIXYP0xJ2ZO9PZ22rWw?= =?us-ascii?Q?B2QHyLQbTMyZtLQki1mHgIfu/dx3Ty/iotMEzJdmJzweBGu+JmbrSn+U22pl?= =?us-ascii?Q?+GywXgiju1Hwo7kKQONo1KkfWiRlMP9Go9V4PuNm+nquMDHVrerZRJDq0Tq6?= =?us-ascii?Q?tx9f9wvtmWzshzSPTrDRUIqtofWLNrFg47Ov?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:49:12.2707 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e769449-15ed-4713-b2eb-08ddd2730044 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9235 Users control/monitor Intel Platform Shared Resource (PSR) through related domctl-op or sysctl-op, so CONFIG_X86_PSR can be put under SYSCTL or DOMCTL. with this change, we could remove SYSCTL-wrapping in psr.c Signed-off-by: Penny Zheng --- xen/arch/x86/Kconfig | 1 + xen/arch/x86/psr.c | 18 ------------------ 2 files changed, 1 insertion(+), 18 deletions(-) diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig index a45ce106e2..691edf8926 100644 --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -187,6 +187,7 @@ config TBOOT config X86_PSR bool "Platform Shared Resource support" if EXPERT default INTEL + depends on SYSCTL || DOMCTL help Support of Platform Shared Resource technology, which is basis for monitoring and control of resources like cache and memory bandwidth. diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c index 499d320e61..5815a35335 100644 --- a/xen/arch/x86/psr.c +++ b/xen/arch/x86/psr.c @@ -133,11 +133,9 @@ static const struct feat_props { */ enum psr_type alt_type; -#ifdef CONFIG_SYSCTL /* get_feat_info is used to return feature HW info through sysctl. */ bool (*get_feat_info)(const struct feat_node *feat, uint32_t data[], unsigned int array_len); -#endif /* write_msr is used to write out feature MSR register. */ void (*write_msr)(unsigned int cos, uint32_t val, enum psr_type type); @@ -420,7 +418,6 @@ static bool mba_init_feature(const struct cpuid_leaf *regs, return true; } -#ifdef CONFIG_SYSCTL static bool cf_check cat_get_feat_info( const struct feat_node *feat, uint32_t data[], unsigned int array_len) { @@ -433,7 +430,6 @@ static bool cf_check cat_get_feat_info( return true; } -#endif /* CONFIG_SYSCTL */ /* L3 CAT props */ static void cf_check l3_cat_write_msr( @@ -446,14 +442,11 @@ static const struct feat_props l3_cat_props = { .cos_num = 1, .type[0] = PSR_TYPE_L3_CBM, .alt_type = PSR_TYPE_UNKNOWN, -#ifdef CONFIG_SYSCTL .get_feat_info = cat_get_feat_info, -#endif .write_msr = l3_cat_write_msr, .sanitize = cat_check_cbm, }; -#ifdef CONFIG_SYSCTL /* L3 CDP props */ static bool cf_check l3_cdp_get_feat_info( const struct feat_node *feat, uint32_t data[], uint32_t array_len) @@ -465,7 +458,6 @@ static bool cf_check l3_cdp_get_feat_info( return true; } -#endif /* CONFIG_SYSCTL */ static void cf_check l3_cdp_write_msr( unsigned int cos, uint32_t val, enum psr_type type) @@ -481,9 +473,7 @@ static const struct feat_props l3_cdp_props = { .type[0] = PSR_TYPE_L3_DATA, .type[1] = PSR_TYPE_L3_CODE, .alt_type = PSR_TYPE_L3_CBM, -#ifdef CONFIG_SYSCTL .get_feat_info = l3_cdp_get_feat_info, -#endif .write_msr = l3_cdp_write_msr, .sanitize = cat_check_cbm, }; @@ -499,14 +489,11 @@ static const struct feat_props l2_cat_props = { .cos_num = 1, .type[0] = PSR_TYPE_L2_CBM, .alt_type = PSR_TYPE_UNKNOWN, -#ifdef CONFIG_SYSCTL .get_feat_info = cat_get_feat_info, -#endif .write_msr = l2_cat_write_msr, .sanitize = cat_check_cbm, }; -#ifdef CONFIG_SYSCTL /* MBA props */ static bool cf_check mba_get_feat_info( const struct feat_node *feat, uint32_t data[], unsigned int array_len) @@ -521,7 +508,6 @@ static bool cf_check mba_get_feat_info( return true; } -#endif /* CONFIG_SYSCTL */ static void cf_check mba_write_msr( unsigned int cos, uint32_t val, enum psr_type type) @@ -559,9 +545,7 @@ static const struct feat_props mba_props = { .cos_num = 1, .type[0] = PSR_TYPE_MBA_THRTL, .alt_type = PSR_TYPE_UNKNOWN, -#ifdef CONFIG_SYSCTL .get_feat_info = mba_get_feat_info, -#endif .write_msr = mba_write_msr, .sanitize = mba_sanitize_thrtl, }; @@ -824,7 +808,6 @@ static struct psr_socket_info *get_socket_info(unsigned int socket) return socket_info + socket; } -#ifdef CONFIG_SYSCTL int psr_get_info(unsigned int socket, enum psr_type type, uint32_t data[], unsigned int array_len) { @@ -856,7 +839,6 @@ int psr_get_info(unsigned int socket, enum psr_type type, return -EINVAL; } -#endif /* CONFIG_SYSCTL */ int psr_get_val(struct domain *d, unsigned int socket, uint32_t *val, enum psr_type type) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:51:04 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:51:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068440.1432541 (Exim 4.92) (envelope-from ) id 1uiVMu-0007pZ-JJ; Sun, 03 Aug 2025 09:51:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068440.1432541; Sun, 03 Aug 2025 09:51:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiVMt-0007kw-RM; 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=s8bVld26wdPkUEIzQ96R8Mizbjv7EQdlxJtjjv8jsMk=; b=CzxL+Hyj1tuNC2w7ws3LTk0MU58q1iMnGGtjVmF7FbPmt8KrR6Rey2Gf9LX3rxidbhlA8IsFLETxhzSFv0IQY/fQ36uZNevI5n+VuyAhc6pW6z82+BE9yBElBI7sEmF4JCTYE0Em+bfoSDTHZ2LGvHxVXYS7EIt8pIvFUUOH6Ic= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Penny Zheng To: CC: , Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" , Jan Beulich , "Andrew Cooper" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v1 22/25] xen/domctl: wrap around XEN_DOMCTL_{get,set}_paging_mempool_size Date: Sun, 3 Aug 2025 17:47:35 +0800 Message-ID: <20250803094738.3625269-23-Penny.Zheng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> References: <20250803094738.3625269-1-Penny.Zheng@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231F:EE_|IA0PR12MB7749:EE_ X-MS-Office365-Filtering-Correlation-Id: 798d91a7-c7bf-4e64-8798-08ddd273002a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:49:12.0966 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 798d91a7-c7bf-4e64-8798-08ddd273002a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7749 Arch-specific arch_{get,set}_paging_mempool_size() is responsible for XEN_DOMCTL_{get,set}_paging_mempool_size domctl-op, and shall be wrapped. Signed-off-by: Penny Zheng --- xen/arch/arm/mmu/p2m.c | 4 ++++ xen/arch/x86/mm/paging.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 4b13867fa2..878ce205e2 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -58,12 +58,14 @@ static void p2m_free_page(struct domain *d, struct page_info *pg) } } +#ifdef CONFIG_DOMCTL /* Return the size of the pool, in bytes. */ int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) { *size = (uint64_t)ACCESS_ONCE(d->arch.paging.p2m_total_pages) << PAGE_SHIFT; return 0; } +#endif /* CONFIG_DOMCTL */ /* * Set the pool of pages to the required number of pages. @@ -122,6 +124,7 @@ int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted) return 0; } +#ifdef CONFIG_DOMCTL int arch_set_paging_mempool_size(struct domain *d, uint64_t size) { unsigned long pages = size >> PAGE_SHIFT; @@ -140,6 +143,7 @@ int arch_set_paging_mempool_size(struct domain *d, uint64_t size) return rc; } +#endif /* CONFIG_DOMCTL */ int p2m_teardown_allocation(struct domain *d) { diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c index 3da99ad371..e6eff60df1 100644 --- a/xen/arch/x86/mm/paging.c +++ b/xen/arch/x86/mm/paging.c @@ -955,6 +955,7 @@ int __init paging_set_allocation(struct domain *d, unsigned int pages, } #endif +#ifdef CONFIG_DOMCTL int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) { unsigned long pages; @@ -997,6 +998,7 @@ int arch_set_paging_mempool_size(struct domain *d, uint64_t size) return preempted ? -ERESTART : rc; } +#endif /* CONFIG_DOMCTL */ /* * Local variables: -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 09:51:06 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 09:51:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068446.1432547 (Exim 4.92) (envelope-from ) id 1uiVMw-0008Aa-2G; Sun, 03 Aug 2025 09:51:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068446.1432547; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2025 09:48:42.5032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1539411b-88c7-470b-73ce-08ddd272ee86 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7369 Arch-specific function arch_get_info_guest() is responsible for XEN_DOMCTL_getvcpucontext domctl-op, and shall be wrapped Signed-off-by: Penny Zheng --- xen/arch/arm/domctl.c | 2 ++ xen/arch/x86/domctl.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/xen/arch/arm/domctl.c b/xen/arch/arm/domctl.c index ad914c915f..d508ee2880 100644 --- a/xen/arch/arm/domctl.c +++ b/xen/arch/arm/domctl.c @@ -184,6 +184,7 @@ long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, } } +#ifdef CONFIG_DOMCTL void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) { struct vcpu_guest_context *ctxt = c.nat; @@ -199,6 +200,7 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) if ( !test_bit(_VPF_down, &v->pause_flags) ) ctxt->flags |= VGCF_online; } +#endif /* CONFIG_DOMCTL */ /* * Local variables: diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 156c74e07a..29f9db89a1 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1367,6 +1367,7 @@ long arch_do_domctl( return ret; } +#ifdef CONFIG_DOMCTL #ifdef CONFIG_COMPAT #define xen_vcpu_guest_context vcpu_guest_context #define fpu_ctxt fpu_ctxt.x @@ -1525,6 +1526,7 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) c(vm_assist = d->vm_assist); #undef c } +#endif /* CONFIG_DOMCTL */ /* * Local variables: -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Sun Aug 03 10:02:16 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 10:02:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068533.1432566 (Exim 4.92) (envelope-from ) id 1uiVXf-0005Yc-33; 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Sun, 03 Aug 2025 06:19:16 -0700 (PDT) Message-ID: Date: Sun, 3 Aug 2025 14:19:14 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create To: Stewart Hildebrand , xen-devel@lists.xenproject.org Cc: Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Dario Faggioli , Juergen Gross , George Dunlap References: <20250801202418.38977-1-stewart.hildebrand@amd.com> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: <20250801202418.38977-1-stewart.hildebrand@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 01/08/2025 9:24 pm, Stewart Hildebrand wrote: > In vcpu_create after scheduler data is allocated, if > vmtrace_alloc_buffer fails, it will jump to the wrong cleanup label > resulting in a memory leak. > > Move sched_destroy_vcpu and destroy_waitqueue_vcpu to vcpu_teardown. > Make vcpu_teardown idempotent: deal with NULL unit. > > Fix vcpu_runstate_get (called during XEN_SYSCTL_getdomaininfolist post > vcpu_teardown) when v->sched_unit is NULL. This is unfortunate.  It feels wrong to be updating stats on a domain that's in the process of being destroyed, especially as a side effect of a get call. But, I wonder if we've uncovered an object lifecycle problem here.  Previously any vCPU which was addressable in the system (i.e. domid was addressable, a d->vcpu[x] was not NULL) had a unit. > > Fixes: 217dd79ee292 ("xen/domain: Add vmtrace_size domain creation parameter") > Signed-off-by: Stewart Hildebrand > --- > v1->v2: > * move cleanup functions to vcpu_teardown > * renamed, was ("xen: fix memory leak on error in vcpu_create") > --- > xen/common/domain.c | 14 ++++++-------- > xen/common/sched/core.c | 5 ++++- > 2 files changed, 10 insertions(+), 9 deletions(-) > > diff --git a/xen/common/domain.c b/xen/common/domain.c > index 5241a1629eeb..9c65c2974ea3 100644 > --- a/xen/common/domain.c > +++ b/xen/common/domain.c > @@ -388,6 +388,8 @@ static int vmtrace_alloc_buffer(struct vcpu *v) > static int vcpu_teardown(struct vcpu *v) > { > vmtrace_free_buffer(v); > + sched_destroy_vcpu(v); > + destroy_waitqueue_vcpu(v); > > return 0; > } Along with this, you want a matching: diff --git a/xen/common/domain.c b/xen/common/domain.c index 5241a1629eeb..3fd75a6d6784 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1412,8 +1412,6 @@ static void cf_check complete_domain_destroy(struct rcu_head *head)              continue;          tasklet_kill(&v->continue_hypercall_tasklet);          arch_vcpu_destroy(v); -        sched_destroy_vcpu(v); -        destroy_waitqueue_vcpu(v);      }        grant_table_destroy(d); > @@ -448,13 +450,13 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) > } > > if ( sched_init_vcpu(v) != 0 ) > - goto fail_wq; > + goto fail; > > if ( vmtrace_alloc_buffer(v) != 0 ) > - goto fail_wq; > + goto fail; > > if ( arch_vcpu_create(v) != 0 ) > - goto fail_sched; > + goto fail; > > d->vcpu[vcpu_id] = v; > if ( vcpu_id != 0 ) > @@ -472,11 +474,7 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) > > return v; > > - fail_sched: > - sched_destroy_vcpu(v); > - fail_wq: > - destroy_waitqueue_vcpu(v); > - > + fail: > /* Must not hit a continuation in this context. */ > if ( vcpu_teardown(v) ) > ASSERT_UNREACHABLE(); > diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c > index 2ab4313517c3..fb7c99b05360 100644 > --- a/xen/common/sched/core.c > +++ b/xen/common/sched/core.c > @@ -321,7 +321,7 @@ void vcpu_runstate_get(const struct vcpu *v, > */ > unit = is_idle_vcpu(v) ? get_sched_res(v->processor)->sched_unit_idle > : v->sched_unit; > - lock = likely(v == current) ? NULL : unit_schedule_lock_irq(unit); > + lock = likely(v == current || !unit) ? NULL : unit_schedule_lock_irq(unit); This is obfuscation for obfuscations sake.  The normal way of writing it would be:     if ( v != current && unit )         lock = unit_schedule_lock_irq(unit); and that is precisely what the compiler emits. Moreover it also matches the pattern for how the lock is released, later in the function. ~Andrew From xen-devel-bounces@lists.xenproject.org Sun Aug 03 13:36:50 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 13:36:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068614.1432587 (Exim 4.92) (envelope-from ) id 1uiYtJ-0007eO-QZ; Sun, 03 Aug 2025 13:36:45 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068614.1432587; Sun, 03 Aug 2025 13:36:45 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiYtJ-0007eH-MS; Sun, 03 Aug 2025 13:36:45 +0000 Received: by outflank-mailman (input) for mailman id 1068614; Sun, 03 Aug 2025 13:36:44 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiYtI-0007eB-Gb for xen-devel@lists.xenproject.org; Sun, 03 Aug 2025 13:36:44 +0000 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [2a00:1450:4864:20::443]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e4b5bce4-706e-11f0-a321-13f23c93f187; Sun, 03 Aug 2025 15:36:43 +0200 (CEST) Received: by mail-wr1-x443.google.com with SMTP id ffacd0b85a97d-3b786421e36so2050659f8f.3 for ; Sun, 03 Aug 2025 06:36:43 -0700 (PDT) Received: from [192.168.1.183] (host-195-149-20-212.as13285.net. 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To: =?UTF-8?Q?Christoph_Gr=C3=BCninger?= , xen-devel@lists.xenproject.org References: Content-Language: en-GB Cc: Anthony PERARD , Juergen Gross From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 03/08/2025 9:52 am, Christoph Grüninger wrote: > Dear Xen developers, > > you are using the dependency yajl (yet another json library, [1]) to > parse JSON files. The project seems abandoned with the last commit 10 > years ago, the last release over 11 years ago, and 75 open pull > requests. Packaging yajl requires patches, e.g., to make it compatible > with CMake 4.0. > There are some forks but none has replaced the old one yet [2]. > > I think there are three paths forward: > 1. Xen could pick a prominent fork and use it as its main dependency. > 2. Xen could create a fork of its own, hopefully attracting more > people interested in an maintained successor of yajl. > 3. Switch to a different JSON parser library that remained healthy. > > Sure, you could stick to option 4., do nothing an offload the burden > to fix yajl to distribution packagers. > > Xen is an important project and its decision can create momentum that > might lead other projects. > > [1] https://github.com/lloyd/yajl > [2] https://github.com/lloyd/yajl/issues/252 CCing the libxl maintainers. ~Andrew From xen-devel-bounces@lists.xenproject.org Sun Aug 03 15:57:30 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 15:57:30 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068638.1432595 (Exim 4.92) (envelope-from ) id 1uib5K-0007Vr-B8; Sun, 03 Aug 2025 15:57:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068638.1432595; Sun, 03 Aug 2025 15:57:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uib5K-0007Vk-8Z; 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AJvYcCXZCQ/wK9I4VzAxyi4N1blNV7fE5yxQeGfHzxZgnGdLfPjCZnK1wzt1gf0zqqKt+k5aNXvJpj+4j0E=@lists.xenproject.org X-Gm-Message-State: AOJu0YwoLRcVnhEUR4vuo9P1HJVhVWaQVAhLbF/FEotTnMxWHinp4/Xj 7HySpKhLXnrO1LB22xnu2fP0WA6rDG/iFVI3c79Gk4/YguNSqZvjPtBs X-Gm-Gg: ASbGncvoqmDYINxjVAk4DFZJJjYsRbK9UhPp94EAxcpEnejO+wUKZksMdo8taIz4uO3 IYvCRmfNaVbNSfOiFv6wwbkAXjYqBkIN8I9iZ7Vx3/ZcpPWLGMVRno+RKbKOxRprSlqxiPnG54g tniOq/Rw4meo52ki8DjcpJ9Gp+K2s3oC7W9hnpTd6WRWzsTnbD+yP32CtX6h2H9ezXSlTi43ypQ gAaZMrtS9fQQ9FFbIuch/TuY1bzOUv1FVlyHTU6nfAkHWwcaZls6GETkHlvcGgInNUaSFZkYVnV SWBDoBMOQIaL3Qseg1Nb9LelxQPFSs69LW9WTY2vGg3uJZfzi27rArFn42q86IYUv0qq7lppOch veKHamrSgq0QaITfQKTSBVD/4jyeq86Q= X-Google-Smtp-Source: AGHT+IFJkV/yhq6un/u65EgeHZIBGmVmdR/00A7B/jnsQgh/uwuP5x1U2c5Dil2c+VJKwuRXqWhcJQ== X-Received: by 2002:a05:6e02:370e:b0:3e2:a082:7e4b with SMTP id e9e14a558f8ab-3e4161beca5mr32236065ab.4.1754236632239; Sun, 03 Aug 2025 08:57:12 -0700 (PDT) Date: Sun, 3 Aug 2025 10:57:03 -0500 From: Aaron Rainbolt To: Daniel Kiper Cc: grub-devel@gnu.org, xen-devel@lists.xenproject.org Subject: Re: [RESEND PATCH v3 1/1] kern/xen: Add Xen command line parsing Message-ID: <20250803105703.5c83d4b2@kf-m2g5> In-Reply-To: <20250801125536.mc2sjrdyikljzea6@tomti.i.net-space.pl> References: <20250725153012.1dd46644@kf-m2g5> <20250725153112.4ea25243@kf-m2g5> <20250801125536.mc2sjrdyikljzea6@tomti.i.net-space.pl> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.41; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; boundary="Sig_/cDaFj_5U54ghyioulxMOsfG"; protocol="application/pgp-signature"; micalg=pgp-sha512 --Sig_/cDaFj_5U54ghyioulxMOsfG Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Fri, 1 Aug 2025 14:55:36 +0200 Daniel Kiper wrote: > On Fri, Jul 25, 2025 at 03:31:12PM -0500, Aaron Rainbolt wrote: > > Xen traditionally allows customizing guest behavior by passing > > arguments to the VM kernel via the kernel command line. This is no > > longer possible when using GRUB with Xen, as the kernel command > > line is decided by the GRUB configuration file within the guest, > > not data passed to the guest by Xen. > > > > To work around this limitation, enable GRUB to parse a command line > > passed to it by Xen, and expose data from the command line to the > > GRUB configuration as environment variables. These variables can be > > used in the GRUB configuration for any desired purpose, such as > > extending the kernel command line passed to the guest. The command > > line format is inspired by the Linux kernel's command line format. > > > > To reduce the risk of misuse, abuse, or accidents in production, the > > command line will only be parsed if it consists entirely of 7-bit > > ASCII characters, only alphabetical characters and underscores are > > permitted in variable names, and all variable names must start with > > the string "xen_grub_env_". This also allows room for expanding the > > command line arguments accepted by GRUB in the future, should other > > arguments end up becoming desirable in the future. > > > > Signed-off-by: Aaron Rainbolt > > --- > > docs/grub.texi | 50 +++++ > > grub-core/Makefile.core.def | 2 + > > grub-core/kern/i386/xen/pvh.c | 14 ++ > > grub-core/kern/main.c | 12 ++ > > grub-core/kern/xen/cmdline.c | 343 > > ++++++++++++++++++++++++++++++++++ include/grub/xen.h | > > 2 + 6 files changed, 423 insertions(+) > > create mode 100644 grub-core/kern/xen/cmdline.c > > > > diff --git a/docs/grub.texi b/docs/grub.texi > > index 34b3484..ce82483 100644 > > --- a/docs/grub.texi > > +++ b/docs/grub.texi > > @@ -3271,6 +3271,7 @@ GRUB. Others may be used freely in GRUB > > configuration files. @menu > > * Special environment variables:: > > * Environment block:: > > +* Passing environment variables through Xen:: > > @end menu > > > > > > @@ -3871,6 +3872,55 @@ using BIOS or EFI functions (no ATA, USB or > > IEEE1275). @command{grub-mkconfig} uses this facility to implement > > @samp{GRUB_SAVEDEFAULT} (@pxref{Simple configuration}). > > > > +@node Passing environment variables through Xen > > +@section Passing environment variables through Xen > > + > > +If you are using a GRUB image as the kernel for a PV or PVH Xen > > virtual +machine, you can pass environment variables from Xen's > > dom0 to the VM through +the Xen-provided kernel command line. When > > combined with a properly configured +guest, this can be used to > > customize the guest's behavior on bootup via the +VM's Xen > > configuration file. + > > +GRUB will parse the kernel command line passed to it by Xen during > > bootup. +The command line will be split into space-delimited words. > > Single and +double quotes may be used to quote words or portions of > > words that contain +spaces. Arbitrary characters may be > > backslash-escaped to make them a literal +component of a word > > rather than being parsed as quotes or word separators. The +command > > line must consist entirely of printable 7-bit ASCII characters and > > +spaces. If a non-printing ASCII character is found anywhere in the > > command +line, the entire command line will be ignored by GRUB. + > > +Each word should be a variable assignment in the format > > ``variable'' or +``variable=3Dvalue''. Variable names must contain > > only the characters A-Z, a-z, +and underscore (``_''). Variable > > names must begin with the string +``xen_grub_env_''. Variable > > values can contain arbitrary printable 7-bit +ASCII characters and > > space. If any variable contains an illegal name, that +variable > > will be ignored. + > > +If a variable name and value are both specified, the variable will > > be set to +the specified value. If only a variable name is > > specified, the variable's +value will be set to ``1''. > > + > > +The following is a simple example of how to use this functionality > > to append +arbitrary variables to a guest's kernel command line: > > + > > +@example > > +# In the Xen configuration file for the guest > > +name =3D "linux_vm" > > +type =3D "pvh" > > +kernel =3D "/path/to/grub-i386-xen_pvh.bin" > > +extra =3D "xen_grub_env_kernelappend=3D'loglevel=3D3'" =20 >=20 > s/kernelappend/kernel_append/ >=20 > or maybe even >=20 > s/kernelappend/linux_append/ >=20 > to make it clear it is appended to the "linux" command line... Will do. > > +memory =3D 1024 > > +disk =3D [ "file:/srv/vms/linux_vm.img,sda,w" ] > > + > > +# In the guest's GRUB configuration file > > +menuentry "Linux VM with dom0-specified kernel parameters" @{ > > + search --set=3Droot --label linux_vm --hint hd0,msdos1 > > + linux /boot/vmlinuz root=3DLABEL=3Dlinux_vm > > $@{xen_grub_env_kernelappend@} =20 >=20 > Ditto... Will do. > > + initrd /boot/initrd.img > > +@} > > +@end example > > + > > @node Modules > > @chapter Modules > > > > diff --git a/grub-core/Makefile.core.def > > b/grub-core/Makefile.core.def index b3f7119..df0f266 100644 > > --- a/grub-core/Makefile.core.def > > +++ b/grub-core/Makefile.core.def > > @@ -248,6 +248,7 @@ kernel =3D { > > xen =3D term/xen/console.c; > > xen =3D disk/xen/xendisk.c; > > xen =3D commands/boot.c; > > + xen =3D kern/xen/cmdline.c; > > > > i386_xen_pvh =3D commands/boot.c; > > i386_xen_pvh =3D disk/xen/xendisk.c; > > @@ -255,6 +256,7 @@ kernel =3D { > > i386_xen_pvh =3D kern/i386/xen/tsc.c; > > i386_xen_pvh =3D kern/i386/xen/pvh.c; > > i386_xen_pvh =3D kern/xen/init.c; > > + i386_xen_pvh =3D kern/xen/cmdline.c; > > i386_xen_pvh =3D term/xen/console.c; > > > > ia64_efi =3D kern/ia64/efi/startup.S; > > diff --git a/grub-core/kern/i386/xen/pvh.c > > b/grub-core/kern/i386/xen/pvh.c index 91fbca8..12df2d8 100644 > > --- a/grub-core/kern/i386/xen/pvh.c > > +++ b/grub-core/kern/i386/xen/pvh.c > > @@ -321,6 +321,8 @@ void > > grub_xen_setup_pvh (void) > > { > > grub_addr_t par; > > + const char *xen_cmdline; > > + int i; > > > > grub_xen_cpuid_base (); > > grub_xen_setup_hypercall_page (); > > @@ -352,6 +354,18 @@ grub_xen_setup_pvh (void) > > grub_xen_mm_init_regions (); > > > > grub_rsdp_addr =3D pvh_start_info->rsdp_paddr; > > + > > + xen_cmdline =3D (const char *) pvh_start_info->cmdline_paddr; > > + for (i =3D 0; i < MAX_GUEST_CMDLINE; i++) =20 >=20 > Oh, MAX_GUEST_CMDLINE is a too generic. May I ask you to rename it to > GRUB_XEN_MAX_GUEST_CMDLINE? This should be done in separate patch > preceding this one. Sure. > > + { > > + if (xen_cmdline[i] =3D=3D '\0') =20 >=20 > I cannot see much sense in this check. Please look below... >=20 > > + { > > + grub_strncpy ((char *) > > grub_xen_start_page_addr->cmd_line, > > + (char *) pvh_start_info->cmdline_paddr, =20 >=20 > s/char */const char */ >=20 > Is it always guaranteed that pvh_start_info->cmdline_paddr have > MAX_GUEST_CMDLINE size? If yes then... It is not guaranteed. I tested this under Qubes OS, and it is unfortunately very possible to pass a guest command line longer than MAX_GUEST_CMDLINE via pvh_start_info->cmdline_paddr. I do not know of any documentation specifying what the "real" maximum length is in this instance (if any), but in any event the string ultimately has to be crammed into an array that is only MAX_GUEST_CMDLINE long. Originally I wrote this to truncate the command line in this situation, but later decided that discarding the command line would be safer than truncation. (When booting a VM in PV mode, Xen does guarantee the command line will not be longer than MAX_GUEST_CMDLINE and will simply return a truncated command line. There is no way to detect this condition to my awareness, so in PV mode, we simply live with the truncation since we aren't given another option.) > grub_memset ((void *) pvh_start_info->cmdline_paddr, 0, > MAX_GUEST_CMDLINE); grub_strncpy ((char *) > grub_xen_start_page_addr->cmd_line, (const char *) > pvh_start_info->cmdline_paddr, MAX_GUEST_CMDLINE - 1); >=20 > ... and you are done... This would truncate the command line rather than discarding it. If the goal is consistency with Xen's PV mode, then I can switch to this, but I don't like the idea of booting a guest with corrupted data inserted randomly into the grub.cfg file. (Like mentioned above, there isn't any other option when using PV mode, but just because PV mode does things dangerously doesn't mean we have to when running in PVH mode.) > > + MAX_GUEST_CMDLINE); > > + break; > > + } > > + } > > } > > > > grub_err_t > > diff --git a/grub-core/kern/main.c b/grub-core/kern/main.c > > index 143a232..b4377d3 100644 > > --- a/grub-core/kern/main.c > > +++ b/grub-core/kern/main.c > > @@ -37,6 +37,10 @@ > > #include > > #endif > > > > +#if defined (GRUB_MACHINE_XEN) || defined (GRUB_MACHINE_XEN_PVH) > > +#include > > +#endif > > + > > static bool cli_disabled =3D false; > > static bool cli_need_auth =3D false; > > > > @@ -351,6 +355,14 @@ grub_main (void) > > grub_env_export ("root"); > > grub_env_export ("prefix"); > > > > + /* > > + * Parse command line parameters from Xen and export them as > > environment > > + * variables > > + */ > > +#if defined (GRUB_MACHINE_XEN) || defined (GRUB_MACHINE_XEN_PVH) > > + grub_parse_xen_cmdline (); =20 >=20 > Please move this call to the > grub-core/kern/xen/init.c:grub_machine_init(). Will do. > > +#endif > > + > > /* Reclaim space used for modules. */ > > reclaim_module_space (); > > > > diff --git a/grub-core/kern/xen/cmdline.c > > b/grub-core/kern/xen/cmdline.c new file mode 100644 > > index 0000000..03dd88f > > --- /dev/null > > +++ b/grub-core/kern/xen/cmdline.c > > @@ -0,0 +1,343 @@ > > +/* > > + * GRUB -- GRand Unified Bootloader > > + * Copyright (C) 2025 Free Software Foundation, Inc. > > + * > > + * GRUB is free software: you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License as > > published by > > + * the Free Software Foundation, either version 3 of the License, > > or > > + * (at your option) any later version. > > + * > > + * GRUB is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public > > License > > + * along with GRUB. If not, see . > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +enum parse_flags > > +{ > > + PARSER_HIT_BACKSLASH =3D 0x1, > > + PARSER_IN_SINGLE_QUOTES =3D 0x2, > > + PARSER_IN_DOUBLE_QUOTES =3D 0x4, > > +}; =20 > typedef parse_flags parse_flags_t; >=20 > ... and use parse_flags_t instead below... Will do. > And probably this should be a local variable... See below for comments on globals in the parser. > > + > > +#define PARSER_BASE_WORD_LEN 16 =20 >=20 > This constant begs for a few words of comment... Will add. This is just the initial length of the dynamically allocated buffer for storing each "word" of the command line, but it is confusing as written. Perhaps it should be renamed to PARSER_WORD_BUF_START_LEN or similar, to make it clear this isn't a string length, but a buffer length? > > +static grub_size_t word_list_len; > > +static char **word_list; > > +static grub_size_t current_word_len; > > +static grub_size_t current_word_pos; > > +static char *current_word; > > +static char current_char; =20 >=20 > I have a feeling that most if not all of this variables should be > local in a given function... I made them globals because making them local would have required an awful lot of parameter "shuttling" that I believed made the code less readable. For instance, the `append_word_to_list` function right now has no parameters and can be called very simply by the parser whenever it is needed. If all variables used were local, the function would have to have a signature akin to: static bool append_word_to_list(grub_size_t *current_word_pos_ref, grub_size_t *current_word_len_ref, char *current_word, grub_size_t *word_list_len_ref, char **word_list) IMO this is difficult to read and frustrating to call (possibly even error-prone). Ultimately the variables are "local" to the parser, and the functions are just there to split up the parser's algorithm to avoid repetition. They all ultimately operate on the same state, so having the state variables static but global within the file fits the current parser design well. > > +static bool > > +append_char_to_word (bool allow_null) > > +{ > > + /* > > + * Fail if the current char is outside of the range 0x20 to > > 0x7E. If > > + * allow_null is true, make an exception for 0x00. This is a > > safeguard =20 >=20 > Could you elaborate here when allow_null =3D=3D true is useful? Usually when appending characters to a word, you aren't going to be appending null characters, thus `append_char_to_word` usually rejects those so as to make it harder to mess things up. However, the string does need to be null-terminated, and thus once a command line word is fully loaded into current_word, it is necessary to add the null terminator on the end. In this instance the parser sets `current_char` to '\0' and then calls the `append_char_to_word` function with `allow_null` set to true, so that the function knows that the addition of a null is intentional here. (In retrospect, if allow_null is set to true, the only thing `append_char_to_word` should append is a null character, it should reject anything else in that instance. Otherwise someone could accidentally append something other than a null when they meant to append a null.) > > + * against likely-invalid data. > > + */ > > + if ( (!(current_char >=3D 0x20) || !(current_char <=3D 0x7E) ) =20 >=20 > grub_isprint()? That would work, I wasn't aware that existed. Maybe a mention of some valuable GRUB internal API functions that are likely to remain stable could be added to the GRUB development manual? (Or just a reference to header files where useful things like this are defined.) > > + && (current_char !=3D '\0' || allow_null =3D=3D false)) =20 >=20 > I would drop redundant spaces between "(" and ")" and move "&&" to the > end of first line of "if". Will do, though I'm likely to rewrite this conditional anyway so that anything other than '\0' will be rejected when `allow_null =3D=3D true`. > > + return false; > > + > > + if (current_word_pos =3D=3D current_word_len) > > + { > > + current_word_len *=3D 2; =20 >=20 > You can do this in the argument of the function below... I mean, yes, technically I can, but that's a lot less readable to me. I can't find anywhere else in GRUB that uses that style (using `grep -ri '\*=3D'` to search), and can find a few spots that use a style similar to the one I've used here: * `util/grub-install.c` in function `device_map_check_duplicates` * `grub-core/osdep/windows/platform.c` in function `get_efi_variable` * `grub-core/osdep/unix/platform.c` in function `get_ofpathname` > > + current_word =3D grub_realloc (current_word, current_word_len); > > + if (current_word =3D=3D NULL) > > + { > > + current_word_len /=3D 2; > > + return false; > > + } > > + } > > + > > + current_word[current_word_pos] =3D current_char; > > + current_word_pos++; =20 >=20 > Again, you can do this operation in the "[]" above... Will do. (This does seem to be a much more common way to write things in GRUB than what I've done.) > > + return true; > > +} > > + > > +static bool > > +append_word_to_list (void) > > +{ > > + /* No-op on empty words. */ > > + if (current_word_pos =3D=3D 0) =20 >=20 > This should be probably an argument for the function... See above for parser state and global variables rationale. > > + return true; > > + > > + current_char =3D '\0'; > > + if (append_char_to_word (true) =3D=3D false) > > + { > > + grub_error (GRUB_ERR_BUG, > > + "couldn't append null terminator to word during > > Xen cmdline parsing"); > > + grub_print_error (); > > + grub_exit (); > > + } > > + > > + current_word_len =3D grub_strlen (current_word) + 1; > > + current_word =3D grub_realloc (current_word, current_word_len); > > + if (current_word =3D=3D NULL) > > + return false; > > + word_list_len++; =20 >=20 > Again this, OK ++word_list_len to be precise, can be done in a > function argument below... `grep -ri 'alloc.*++'` doesn't show me any instance of this style anywhere else in the GRUB codebase, and I find it much more difficult to read since now I have to think about incrementing `word_list_len`'s value and returning it and multiplying the returned value all at the same time. `grub-core/osdep/unix/platform.c` uses the style I've used here. > > + word_list =3D grub_realloc (word_list, word_list_len * sizeof > > (char *)); > > + if (word_list =3D=3D NULL) > > + return false; > > + word_list[word_list_len - 1] =3D current_word; > > + > > + current_word_len =3D PARSER_BASE_WORD_LEN; > > + current_word_pos =3D 0; > > + current_word =3D grub_malloc (current_word_len); > > + if (current_word =3D=3D NULL) > > + return false; > > + > > + return true; > > +} > > + > > +static bool > > +check_key_is_safe (char *key, grub_size_t len) > > +{ > > + grub_size_t i; > > + > > + for (i =3D 0; i < len; i++) > > + { > > + /* > > + * Ensure only a-z, A-Z, and _ are allowed. > > + */ > > + if (! ( (key[i] >=3D 'A' && key[i] <=3D 'Z') > > + || (key[i] >=3D 'a' && key[i] <=3D 'z') =20 >=20 > You have whole family of grub_isalpha() functions. Could not use them > here and there? Those would almost certainly work here, I'll switch to using those where possible (including here).=20 > > + || (key[i] =3D=3D '_') ) ) > > + return false; > > + } > > + return true; > > +} > > + > > +void > > +grub_parse_xen_cmdline (void) > > +{ > > + const char *cmdline =3D (const char *) > > grub_xen_start_page_addr->cmd_line; > > + grub_size_t cmdline_len; > > + bool cmdline_valid =3D false; > > + char **param_keys =3D NULL; > > + char **param_vals =3D NULL; > > + grub_size_t param_dict_len =3D 0; > > + grub_size_t param_dict_pos =3D 0; > > + enum parse_flags parse_flags =3D 0; > > + grub_size_t i =3D 0; > > + > > + /* > > + * The following algorithm is used to parse the Xen command line: > > + * > > + * - The command line is split into space-separated words. > > + * - Single and double quotes may be used to suppress the > > splitting > > + * behavior of spaces. > > + * - Double quotes are appended to the current word verbatim > > if they > > + * appear within a single-quoted string portion, and vice > > versa. > > + * - Backslashes may be used to cause the next character to be > > + * appended to the current word verbatim. This is only > > useful when > > + * used to escape quotes, spaces, and backslashes, but for > > simplicity > > + * we allow backslash-escaping anything. > > + * - After splitting the command line into words, each word is > > checked to > > + * see if it contains an equals sign. > > + * - If it does, it is split on the equals sign into a > > key-value pair. The > > + * key is then treated as an variable name, and the value is > > treated as > > + * the variable's value. > > + * - If it does not, the entire word is treated as a variable > > name. The > > + * variable's value is implicitly considered to be `1`. > > + * - All variables detected on the command line are checked to > > see if their > > + * names begin with the string `xen_grub_env_`. Variables that > > do not pass > > + * this check are discarded, variables that do pass this check > > are > > + * exported so they are available to the GRUB configuration. =20 >=20 > I think not all from this valuable comment landed in the > documentation. Please fix it... Comparing the two side-by-side: +----------------------------------+----------------------------------+ | Documentation | Comment | +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ | The command line will be split | The command line is split into | | into space-delimited words. | space-separated words. Single | | Single and double quotes may be | and double quotes may be used to | | used to quote words or portions | suppress the splitting behavior | | of words that contain spaces. | of spaces. | +----------------------------------+----------------------------------+ | (Self-evident, any other | Double quotes are appended to | | behavior involving quotes would | the current word verbatim if | | be extremely unexpected.) | they appear within a single- | | | quoted string, and vice versa. | +----------------------------------+----------------------------------+ | Arbitrary characters may be | Backslashes may be used to cause | | backslash-escaped to make them a | the next character to be | | literal component of a word | appended to the current word | | rather than being parsed as | verbatim. This is only useful | | quotes or word separators. | when used to escape quotes, | | | spaces, and backslashes, but for | | | simplicity we allow backslash- | | | escaping anything. | +----------------------------------+----------------------------------+ | Each word should be a variable | After splitting the command line | | assignment in the format | into words, each word is checked | | ``variable'' or | to see if it contains an equals | | ``variable=3Dvalue''. | sign. | +----------------------------------+----------------------------------+ | If a variable name and value are | If it does, it is split on the | | both specified, the variable | equals sign into a key-value | | will be set to the specified | pair. The key is then treated as | | value. | a variable name, and the value | | | treated as the variable's value. | +----------------------------------+----------------------------------+ | If only a variable name is | If it does not, the entire word | | specified, the variable's value | is treated as a variable name. | | will be set to ``1''. | The variable's value is | | | implicitly considered to be '1'. | +----------------------------------+----------------------------------+ | Variable names must begin with | All variables detected on the | | the string ``xen_grub_env_''... | command line are checked to see | | If any variable contains an | if their names begin with the | | illegal name, that variable will | string `xen_grub_env_`. | | be ignored. | Variables that do not pass this | | | check are discarded, | +----------------------------------+----------------------------------+ | ...you can pass environment | variables that do pass this | | variables from Xen's dom0 to the | check are exported so they are | | VM through the Xen-provided | available to the GRUB | | kernel command line. | configuration. | +----------------------------------+----------------------------------+ The only missing detail I see is that single quotes are legal in double-quoted strings and vice versa, though I guess I can make it more explicit that the variables passed on the command line are exported before getting to the example that shows this. Is there anything else you see that's missing? > > + */ > > + > > + current_word_len =3D PARSER_BASE_WORD_LEN; > > + current_word =3D grub_malloc (current_word_len); > > + if (current_word =3D=3D NULL) > > + goto cleanup; > > + > > + for (i =3D 0; i < MAX_GUEST_CMDLINE; i++) > > + { > > + if (cmdline[i] =3D=3D '\0') > > + { > > + cmdline_valid =3D true; > > + break; > > + } > > + } > > + > > + if (cmdline_valid =3D=3D false) > > + { > > + grub_error (GRUB_ERR_BAD_ARGUMENT, > > + "Command line from Xen is not NUL-terminated"); =20 >=20 > GRUB errors usually start with lowercase... Will fix. > > + grub_print_error (); > > + goto cleanup; > > + } > > + > > + cmdline_len =3D grub_strlen (cmdline); > > + for (i =3D 0; i < cmdline_len; i++) > > + { > > + current_char =3D cmdline[i]; > > + > > + /* > > + * If the previous character was a backslash, append the > > current > > + * character to the word verbatim > > + */ > > + if (parse_flags & PARSER_HIT_BACKSLASH) =20 >=20 > s/parse_flags/parser_state/ Hmm, I don't like 'parser_state' as a name because the parser's "state" is the global variables in `grub-core/kern/xen/cmdline.`. Maybe 'splitter_state' instead, since this is just the bit of state that the word splitter is concerned with? > > + { > > + parse_flags &=3D ~PARSER_HIT_BACKSLASH; > > + if (append_char_to_word (false) =3D=3D false) > > + goto cleanup; > > + continue; > > + } > > + > > + switch (current_char) > > + { > > + case '\\': > > + /* Backslashes escape arbitrary characters. */ > > + parse_flags |=3D PARSER_HIT_BACKSLASH; > > + continue; > > + > > + case '\'': > > + /* > > + * Single quotes suppress word splitting and double > > quoting until > > + * the next single quote is encountered. > > + */ > > + if (parse_flags & PARSER_IN_DOUBLE_QUOTES) > > + { > > + if (append_char_to_word (false) =3D=3D false) > > + goto cleanup; > > + continue; > > + } > > + > > + parse_flags ^=3D PARSER_IN_SINGLE_QUOTES; > > + continue; > > + > > + case '"': > > + /* > > + * Double quotes suppress word splitting and single > > quoting until > > + * the next double quote is encountered. > > + */ > > + if (parse_flags & PARSER_IN_SINGLE_QUOTES) > > + { > > + if (append_char_to_word (false) =3D=3D false) > > + goto cleanup; > > + continue; > > + } > > + > > + parse_flags ^=3D PARSER_IN_DOUBLE_QUOTES; > > + continue; > > + > > + case ' ': > > + /* Spaces separate words in the command line from each > > other. */ > > + if (parse_flags & PARSER_IN_SINGLE_QUOTES > > + || parse_flags & PARSER_IN_DOUBLE_QUOTES) =20 >=20 > I prefer "||" and "&&" at the end of the lines... Will fix. This is another thing that might be good to put in the GRUB coding style docs. (My boss insists that I always put && and || at the beginning of lines, so I've been instinctively doing that.) >=20 > > + { > > + if (append_char_to_word (false) =3D=3D false) > > + goto cleanup; > > + continue; > > + } > > + > > + if (append_word_to_list () =3D=3D false) =20 >=20 > This shows nicely that the function misses arguments... Will fix, and will also check my compiler warnings more closely (I assume this generated a warning that I missed). > > + goto cleanup; > > + continue; > > + } > > + > > + if (append_char_to_word (false) =3D=3D false) =20 >=20 > Ditto... >=20 > > + goto cleanup; > > + } > > + > > + if (append_word_to_list () =3D=3D false) =20 >=20 > Ditto... >=20 > > + goto cleanup; > > + > > + param_keys =3D grub_malloc (word_list_len * sizeof (char *)); > > + if (param_keys =3D=3D NULL) > > + goto cleanup; > > + param_vals =3D grub_malloc (word_list_len * sizeof (char *)); > > + if (param_vals =3D=3D NULL) > > + goto cleanup; > > + > > + for (i =3D 0; i < word_list_len; i++) > > + { > > + char *current_word_eq_ptr; > > + > > + current_word =3D word_list[i]; > > + current_word_len =3D grub_strlen (current_word) + 1; > > + current_word_eq_ptr =3D grub_strchr (current_word, '=3D'); > > + > > + if (current_word_eq_ptr) =20 >=20 > current_word_eq_ptr !=3D NULL Will change. > > + { > > + grub_size_t eq_idx =3D (grub_size_t)(current_word_eq_ptr - > > current_word); =20 >=20 > Missing space after "(grub_size_t)"... Will fix.=20 > > + grub_size_t post_eq_len =3D current_word_len - (eq_idx); =20 >=20 > You can drop "()" from eq_idx Will fix. > > + > > + if (check_key_is_safe (current_word, eq_idx)) =20 >=20 > check_key_is_safe() =3D=3D true >=20 > s/check_key_is_safe/is_key_safe/ Will fix and rename. > > + { > > + param_dict_pos =3D param_dict_len; > > + param_dict_len++; > > + param_keys[param_dict_pos] =3D grub_malloc (eq_idx + > > 1); > > + if (param_keys =3D=3D NULL) > > + goto cleanup; > > + param_vals[param_dict_pos] =3D grub_malloc > > (post_eq_len + 1); > > + if (param_vals =3D=3D NULL) > > + goto cleanup; > > + > > + grub_strncpy (param_keys[param_dict_pos], > > current_word, > > + eq_idx); =20 >=20 > Please do not wrap line here... Will fix. > > + grub_strncpy (param_vals[param_dict_pos], > > + current_word + eq_idx + 1, > > post_eq_len); =20 >=20 > Please remember that grub_strncpy() may return non-NUL terminated > strings... You should check this everywhere... The next two lines of the patch append the null terminators here. > > + param_keys[param_dict_pos][eq_idx] =3D '\0'; > > + param_vals[param_dict_pos][post_eq_len] =3D '\0'; Making a note for myself here, I believe I'm unintentionally double-null-terminating `param_vals[param_dict_pos]`, since `post_eq_len` is the length of everything after the equals sign including the null terminator. Thus post_eq_len - 2 is the index of the last character of the string, post_eq_len - 1 is the index of the null terminator, and then this is a second null terminator. I should skip appending the null here and also should allocate a buffer one character smaller for `param_vals[param_dict_pos]`. This will need comments to explain. > > + } > > + } > > + else > > + { > > + if (check_key_is_safe (current_word, current_word_len - > > 1)) =20 >=20 > check_key_is_safe() =3D=3D true Will fix (and also rename as requested earlier). > > + { > > + param_dict_pos =3D param_dict_len; > > + param_dict_len++; > > + param_keys[param_dict_pos] =3D grub_malloc > > (current_word_len); > > + if (param_keys =3D=3D NULL) > > + goto cleanup; > > + param_vals[param_dict_pos] =3D grub_malloc (2); > > + if (param_vals =3D=3D NULL) > > + goto cleanup; > > + > > + grub_strncpy (param_keys[param_dict_pos], > > current_word, > > + current_word_len); > > + grub_strcpy (param_vals[param_dict_pos], "1"); > > + } > > + } > > + } > > + > > + for (i =3D 0; i < param_dict_len; i++) > > + { > > + /* > > + * Find keys that start with "xen_grub_env_" and export them > > + * as environment variables. > > + */ > > + if (grub_strncmp (param_keys[i], > > + "xen_grub_env_", > > + sizeof ("xen_grub_env_") - 1) !=3D 0) > > + continue; > > + grub_env_set (param_keys[i], param_vals[i]); > > + grub_env_export (param_keys[i]); =20 >=20 > Both functions may fail. Don't we care about that? Should not we > print a warning? No other places in this file do so, but I'm happy to add warnings here anyway. -- Aaron > > + } > > + > > + cleanup: > > + for (i =3D 0; i < word_list_len; i++) > > + grub_free (word_list[i]); > > + > > + for (i =3D 0; i < param_dict_len; i++) > > + { > > + grub_free (param_keys[i]); > > + grub_free (param_vals[i]); > > + } > > + > > + grub_free (param_keys); > > + grub_free (param_vals); > > + grub_free (word_list); > > +} =20 >=20 > Daniel --Sig_/cDaFj_5U54ghyioulxMOsfG Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEEudh48PFXwyPDa0wGpwkWDXPHkQkFAmiPhs8ACgkQpwkWDXPH kQld6w//SUjwYMNqcIthXBnOq70qi7vPIFhZ/ZE90Ea1M0zgJXtnWmdbHSOYuT82 /NbhXiZO1y1Sm9BZsGBOWVKEPbzeJIze9W3leBI7vDrvXzofkPbp7Ibe4e5nO6U6 PeF5+ybrV65ydt5UpEYuXRJkWDNyTYvOUawyPhfA0Jr2gxc8QHMHsAMntaGn7oZv GoRuFd3NzzKl3r/BV5JCHdvtPOFfsI3EgPx+O6TXBjzIOsXruLkAMBXj3AchKB7o Ub3uPcvY9JCBqyr/4loyHl5qPmmMf/k2gHQ2CE1he/Nja9YnL5DsrlQPTdMr5ROW kDkuaC22XuLDOWGkpePpACfmeJosfOdqpLAn+bINkVHhbUnggCK9aj4uFUc4X9/e Fdb4BFAxXS4AhW4Tc5agWQDX61e4An7is4FDUqk9/K80+Ckv+XkigHg//M+A6NL/ C9UxYI/Z6LOq/EtStY5OKgAxVGNmw5kPY6UvxgK1aywhniOn80aJ5rrp/Ph3BkXD 4PlVZ2AuG3MUF8rrs1jYbXiwHa5TGHu55G4QNfhaC3dHTYP6eTMhWcrFd4J2AmGd g1pKDLg2Y1RApNvoznr+yjYNEyfWgnC+GKpMmtrTqYpc/z5YgptHWKFYLmuGNa+9 q0nZ7bvAJyQpBtr8BS4WgOAPxUDriU8puUtL0YEA5kIFbbgErmU= =gHpn -----END PGP SIGNATURE----- --Sig_/cDaFj_5U54ghyioulxMOsfG-- From xen-devel-bounces@lists.xenproject.org Sun Aug 03 20:16:41 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Sun, 03 Aug 2025 20:16:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068687.1432606 (Exim 4.92) (envelope-from ) id 1uif83-0004FA-V7; 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Sun, 03 Aug 2025 20:16:19 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b7ee7e72-70a6-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1754252179; x=1754856979; d=contentwise.tech; s=rsa1; h=content-type:subject:reply-to:cc:from:to:message-id:mime-version:date: in-reply-to:from; bh=yaDO2zkeiZRQmNdej1F7o4pvt5aFjEGieQX3PkdBhME=; b=M3ioqw6iQT4GlZ/XkfcOX0RAJ2+EY2WUuzD4hDDhl3bV0rgknO14Z26XY8IbUy9YjY+8DHtBsyNBJ CD4aQEpDKVpMKWqvWCAyn6nHSX+sKpQ0nvUhlSLkJ0F1Db5xmx6/ecBwTpa0/ZRZNavT9D7PINcamD NPQFPTpk9Io20ROEbyUYqzfizXsMbxC05lc0arS4/UKGjng8Z6c6/Ts8DmG/p2QHEwgq/I8N406jIr cUaU6Ki++tSdCmqLGd9AH/JdaNy2COhWuU5cju6DOEdipkVyjvOCx0qH3UqMBsooMPDwP4oKaN0/Gl VkxgT81n5xBZd9XxGEZEyC2aihU/fvQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; t=1754252179; x=1754856979; d=contentwise.tech; s=ed1; h=content-type:subject:reply-to:cc:from:to:message-id:mime-version:date: in-reply-to:from; bh=yaDO2zkeiZRQmNdej1F7o4pvt5aFjEGieQX3PkdBhME=; b=nMyy8RwnvQDEXSF1YI07fZ5XjTp5de7eOF9KQjHfYOdrrr09PxdD5wPZ/W2K7KVpqDRWa/JV7JLFS F+ZSi48Bw== X-HalOne-ID: b75d3b88-70a6-11f0-9572-e90f2b8e16ca X-Originating-IP: 5.180.182.5 User-Agent: One.com webmail 49.1.9 In-Reply-To: <2d218180-4be4-4c3f-ab65-04a112141b0f@xen.org> Date: Sun, 03 Aug 2025 23:16:18 +0300 MIME-Version: 1.0 Message-ID: <1754252178882.7.40484@webmail-backend-production-957f95bc8-4zxxx> To: "Julien Grall" From: "Evgeny Beysembaev" Cc: , "Stefano Stabellini" , "Bertrand Marquis" , "Volodymyr Babchuk" , Reply-To: Subject: Re: [PATCH] BCM2711 reboot fix Content-Type: multipart/alternative; boundary="----------40482-1754252178882-1" This is a multipart message in MIME format. ------------40482-1754252178882-1 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 According to the commit b334c1afad17 ("ARM: dts: bcm2711: Use proper compat= ible in PM/Watchdog node") in Linux kernel, the `compatible` string for the watchdog peripheral in the= DTS has been modified from `brcm,bcm2835-pm` to `brcm,bcm2711-pm`, which caused `rpi4_map_watchdog()` = function to fail, leading to inability to reboot the system under Xen hypervisor. Signed-off-by: Evgeny Beysembaev <> --- xen/arch/arm/platforms/brcm-raspberry-pi.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/platforms/brcm-raspberry-pi.c b/xen/arch/arm/plat= forms/brcm-raspberry-pi.c index 811b40b1a6..74fca7ecc5 100644 --- a/xen/arch/arm/platforms/brcm-raspberry-pi.c +++ b/xen/arch/arm/platforms/brcm-raspberry-pi.c @@ -60,9 +60,12 @@ static void __iomem *rpi4_map_watchdog(void) paddr_t start, len; int ret; - node =3D dt_find_compatible_node(NULL, NULL, "brcm,bcm2835-pm"); - if ( !node ) - return NULL; + node =3D dt_find_compatible_node(NULL, NULL, "brcm,bcm2711-pm"); + if ( !node ) { + node =3D dt_find_compatible_node(NULL, NULL, "brcm,bcm2835-pm"); + if ( !node ) + return NULL; + } ret =3D dt_device_get_address(node, 0, &start, &len); if ( ret ) --=20 2.47.2 On Friday, May 30, 2025 at 11:40:23 pm +03:00, Julien Grall wrote: > Hi Evgeny, >=20 > Thank you for the patch. Let me start with the process, > patches are submitted inline rather than in attachment. >=20 > git-send-email commmand can do that for you. >=20 > Now regarding the patch. I understand that newer kernel > will use the new compatible. But I would assume there is > still some device-tree out using the old property. So I > think Xen needs to check both compatible. >=20 > Lastly, for the future,when mentioning we commit, we tend to use a smalle= r > hash (12 digits) followed by the commit title. In your case, > it would be: >=20 > b334c1afad17 ("ARM: dts: bcm2711: Use proper compatible in PM/Watchdog no= de"). > > Cheers, > > -- > Julien Grall > ------------40482-1754252178882-1 Content-Type: multipart/related; boundary="----------40482-1754252178882-2" ------------40482-1754252178882-2 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=UTF-8
According to the commit b334c1afad= 17 ("ARM: dts: bcm2711: Use proper compatible in PM/Watchdog node")<= /span> <= br><= span class=3D"colour" style=3D"color: rgb(224, 226, 234);">in Linux kernel,= the `compatible` string for the watchdog peripheral in the DTS has been mo= dified from
`brcm,bcm2835-pm` to `brcm,bcm2711-pm`, which caused `rpi4_map_watchdog(= )` function to fail,
leading to inability to reboot the system under Xen hypervisor.= =

Sig= ned-off-by: Evgeny Beysembaev <evgeny@contentwise.tech>
---
xen/arch/arm/platforms/brcm-raspberry-pi.c | 9 ++++++---<= /span> <= /span>
1 file c= hanged, 6 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/platforms/brc= m-raspberry-pi.c b/xen/arch/arm/platforms/brcm-raspberry-pi.c= <= span class=3D"colour" style=3D"color: rgb(0, 0, 0);">
index 811b40b1a6..74fc= a7ecc5 100644
--- a/xen/arch/arm/platforms/brcm-raspberry-pi.c
+++ b/xen/arch/arm/platforms/b= rcm-raspberry-pi.c
@@ -60,9 +60,12 @@ static void __iomem *rpi4_map_watchdog(= void)
= =C2=A0=C2=A0=C2=A0=C2=A0paddr_t start, len;
=C2=A0=C2=A0=C2=A0=C2=A0int ret;
- =C2=A0=C2= =A0=C2=A0node =3D dt_find_compatible_node(NULL, NULL, "brcm,bcm2835-pm");
- =C2=A0=C2= =A0=C2=A0if ( !node )
- =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return NULL; + =C2=A0=C2=A0= =C2=A0node =3D dt_find_compatible_node(NULL, NULL, "brcm,bcm2711-pm");<= /span> <= br><= span class=3D"colour" style=3D"color: rgb(179, 246, 192);">+ =C2=A0=C2=A0= =C2=A0if ( !node ) {
+ =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0node =3D dt_find_compa= tible_node(NULL, NULL, "brcm,bcm2835-pm");
+ =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0if ( !node )
+ =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0return NULL;
+ =C2=A0=C2=A0=C2=A0}

=C2=A0=C2=A0=C2=A0=C2=A0ret =3D dt_device_get_addres= s(node, 0, &start, &len);
=C2=A0=C2=A0=C2=A0=C2=A0if ( ret )
-- =C2=A0
2.47.2
<= div>


On Friday, May 30, 2025 at= 11:40:23 pm +03:00, Julien Grall <julien@xen.org> wrote:
=
Hi Evgeny,

Thank you for the patch. Let m= e start with the process,
patches are submitted inline rather= than in attachment.

git-send-email commmand c= an do that for you.

Now regarding the patch. I= understand that newer kernel
will use the new compatible. Bu= t I would assume there is
still some device-tree out using th= e old property. So I
think Xen needs to check both compatible= .

Lastly, for the future,when mentioning we co= mmit, we tend to use a smaller
hash (12 digits) followed by t= he commit title. In your case,
it would be:
b334c1afad17 ("ARM: dts: bcm2711: Use proper compatible in PM/W= atchdog node").

Cheers,

--
Julien Grall

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Mon, 04 Aug 2025 00:10:32 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 09:10:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] console: make printk_ratelimit_{burst,ms} const To: dmkhn@proton.me Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= References: <5fcd1c68-6c18-4a1d-8a1d-f056bdb6cde9@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 01.08.2025 20:58, dmkhn@proton.me wrote: > On Fri, Aug 01, 2025 at 09:30:34AM +0200, Jan Beulich wrote: >> Them not being altered by any means, their __read_mostly attribute is >> actually counter-productive: It causes the compiler to instantiate the >> variables, when already with just the attributes dropped the compiler >> can constant-propagate the values into the sole use site. Make the >> situation yet more explicit by adding const. >> >> Also switch the variables away from being plain int, and have the >> parameters of __printk_ratelimit() follow suit. While there also >> similarly adjust the type of "missed" and "lost", and - while touching >> the adjacent line - increase lost_str[] to accommodate any unsigned >> 32-bit number. >> >> Fixes: a8b1845a7845 ("Miscellaneous data placement adjustments") >> Signed-off-by: Jan Beulich >> --- >> In principle {__,}printk_ratelimit() may also want to have their return >> type changed to bool, but I think doing so would go too far here: This >> would have knock-on effects elsewhere, and it would want considering to >> actually flip polarity. >> >> Despite the Fixes: tag I wouldn't consider this for backport. >> >> --- a/xen/drivers/char/console.c >> +++ b/xen/drivers/char/console.c >> @@ -1268,12 +1268,12 @@ void console_end_sync(void) >> * This enforces a rate limit: not more than one kernel message >> * every printk_ratelimit_ms (millisecs). >> */ >> -int __printk_ratelimit(int ratelimit_ms, int ratelimit_burst) >> +int __printk_ratelimit(unsigned int ratelimit_ms, unsigned int ratelimit_burst) >> { >> static DEFINE_SPINLOCK(ratelimit_lock); >> static unsigned long toks = 10 * 5 * 1000; >> static unsigned long last_msg; >> - static int missed; >> + static unsigned int missed; >> unsigned long flags; >> unsigned long long now = NOW(); /* ns */ >> unsigned long ms; >> @@ -1288,14 +1288,16 @@ int __printk_ratelimit(int ratelimit_ms, >> toks = ratelimit_burst * ratelimit_ms; >> if ( toks >= ratelimit_ms ) >> { >> - int lost = missed; >> + unsigned int lost = missed; >> + >> missed = 0; >> toks -= ratelimit_ms; >> spin_unlock(&ratelimit_lock); >> if ( lost ) >> { >> - char lost_str[8]; >> - snprintf(lost_str, sizeof(lost_str), "%d", lost); >> + char lost_str[10]; >> + >> + snprintf(lost_str, sizeof(lost_str), "%u", lost); > > Since this code is touched, I would also simplify the entire `if ( lost )` > block (I have it done in another experiment): > > char lost_str[64]; > size_t lost_len = snprintf(lost_str, sizeof(lost_str), > "printk: %d messages suppressed.\n", > lost_str); > > /* console_lock may already be acquired by printk(). */ > rspin_lock(&console_lock); > printk_start_of_line(CONSOLE_PREFIX, cflags); > __putstr(lost_str, lost_len); > ... > > What do you think? Maybe, but definitely not right in this patch. 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Mon, 04 Aug 2025 00:13:06 -0700 (PDT) Message-ID: <61efc085-a787-4ca9-82e4-032408532ba6@suse.com> Date: Mon, 4 Aug 2025 09:13:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 12/16] xen/domain: introduce domain-emu.h To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, oleksii.kurochko@gmail.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250624035443.344099-1-dmukhin@ford.com> <20250624035443.344099-13-dmukhin@ford.com> <33f98fe5-9b29-43e4-a87d-19eafb30f281@suse.com> <65e288b7-d8fe-409e-a287-69b4dc29f0c2@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 01.08.2025 21:30, dmkhn@proton.me wrote: > On Fri, Aug 01, 2025 at 08:02:56AM +0200, Jan Beulich wrote: >> On 31.07.2025 22:55, dmkhn@proton.me wrote: >>> On Wed, Jul 09, 2025 at 04:57:44PM +0200, Jan Beulich wrote: >>>> On 24.06.2025 05:56, dmkhn@proton.me wrote: >>>>> @@ -458,16 +459,16 @@ struct arch_domain >>>>> } __cacheline_aligned; >>>>> >>>>> #ifdef CONFIG_HVM >>>>> -#define X86_EMU_LAPIC XEN_X86_EMU_LAPIC >>>>> -#define X86_EMU_HPET XEN_X86_EMU_HPET >>>>> -#define X86_EMU_PM XEN_X86_EMU_PM >>>>> -#define X86_EMU_RTC XEN_X86_EMU_RTC >>>>> -#define X86_EMU_IOAPIC XEN_X86_EMU_IOAPIC >>>>> -#define X86_EMU_PIC XEN_X86_EMU_PIC >>>>> -#define X86_EMU_VGA XEN_X86_EMU_VGA >>>>> -#define X86_EMU_IOMMU XEN_X86_EMU_IOMMU >>>>> -#define X86_EMU_USE_PIRQ XEN_X86_EMU_USE_PIRQ >>>>> -#define X86_EMU_VPCI XEN_X86_EMU_VPCI >>>> >>>> The old code deliberately used values from the public interface. >>> >>> In next version I am building, I moved all of XEN_X86_EMU_XXX definitions as >>> is to a new public header under include/public/xen-emu.h: >>> >>> https://gitlab.com/xen-project/people/dmukhin/xen/-/commit/9b0bc5ffa5710114df8523ae2aa7680b7c6f0942 >>> >>> That looks less invasive. >>> >>> Will that work? >>> >>> There should be a common header with emulation flags somewhere, since >>> there will be SBSA and hwdom vUART definitions there. >> >> Yet will there be a strict need for any constants to be identical (i.e. >> not only have the same name, but also the same value) across architectures? > > I don't think there's strict need for identical values across achitectures. That's what I was expecting. > But some of the constants _may_ be reused for non-x86 arches, like VPCI bit > and, perhaps, IOMMU, PIRQ and future NS16550 (after adding MMIO). Right, but as you say - they want to use the same name, but they could easily have a different value there. I hope you understand that what I'm questioning is the introduction of a single header covering all architectures. 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Mon, 04 Aug 2025 00:17:24 -0700 (PDT) Message-ID: <9688eba1-d6f3-4d7b-8d4a-21f28ab152b1@suse.com> Date: Mon, 4 Aug 2025 09:17:26 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 05/19] xen/cpufreq: refactor cmdline "cpufreq=xxx" To: "Penny, Zheng" Cc: "Huang, Ray" , "xen-devel@lists.xenproject.org" References: <20250711035106.2540522-1-Penny.Zheng@amd.com> <20250711035106.2540522-6-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 04.08.2025 08:04, Penny, Zheng wrote: >> -----Original Message----- >> From: Jan Beulich >> Sent: Wednesday, July 16, 2025 11:01 PM >> >> On 11.07.2025 05:50, Penny Zheng wrote: >>> --- a/xen/drivers/cpufreq/cpufreq.c >>> +++ b/xen/drivers/cpufreq/cpufreq.c >>> @@ -64,12 +64,53 @@ LIST_HEAD_READ_MOSTLY(cpufreq_governor_list); >>> /* set xen as default cpufreq */ >>> enum cpufreq_controller cpufreq_controller = FREQCTL_xen; >>> >>> -enum cpufreq_xen_opt __initdata cpufreq_xen_opts[2] = { CPUFREQ_xen, >>> - CPUFREQ_none }; >>> +enum cpufreq_xen_opt __initdata cpufreq_xen_opts[NR_CPUFREQ_OPTS] = { >>> + CPUFREQ_xen, >>> + CPUFREQ_none >>> +}; >>> unsigned int __initdata cpufreq_xen_cnt = 1; >> >> Given this, isn't the array index 1 initializer quite pointless above? Or else, if you >> really mean to explicitly fill all slots with CPUFREQ_none (despite that deliberately >> having numeric value 0), why not >> "[1 ... NR_CPUFREQ_OPTS - 1] = CPUFREQ_none" (or using ARRAY_SIZE(), as >> per below)? >> >>> static int __init cpufreq_cmdline_parse(const char *s, const char >>> *e); >>> >>> +static bool __init cpufreq_opts_contain(enum cpufreq_xen_opt option) >>> +{ >>> + unsigned int count = cpufreq_xen_cnt; >>> + >>> + while ( count-- ) >>> + { >>> + if ( cpufreq_xen_opts[count] == option ) >>> + return true; >>> + } >>> + >>> + return false; >>> +} >>> + >>> +static int __init handle_cpufreq_cmdline(enum cpufreq_xen_opt option) >>> +{ >>> + int ret = 0; >>> + >>> + if ( cpufreq_opts_contain(option) ) >>> + return 0; >>> + >>> + cpufreq_controller = FREQCTL_xen; >>> + ASSERT(cpufreq_xen_cnt < NR_CPUFREQ_OPTS); >> >> This would better use ARRAY_SIZE(), at which point NR_CPUFREQ_OPTS can go >> away again. What's worse, though, is that on release builds ... > > I found that we already have array index check in setup_cpufreq_option(), before calling handle_cpufreq_cmdline() > Then maybe there is no need to do it again here Well, you will still need to deal with the release build aspect, as per your earlier reply. At which point you can easily place an ASSERT_UNREACHABLE() there as well. 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Mon, 04 Aug 2025 00:19:44 -0700 (PDT) Message-ID: <5ddd405b-b999-4dcc-8ba3-3d0db5f727bb@suse.com> Date: Mon, 4 Aug 2025 09:19:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 05/19] xen/cpufreq: refactor cmdline "cpufreq=xxx" To: "Penny, Zheng" Cc: "Huang, Ray" , "xen-devel@lists.xenproject.org" References: <20250711035106.2540522-1-Penny.Zheng@amd.com> <20250711035106.2540522-6-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 04.08.2025 07:47, Penny, Zheng wrote: >> -----Original Message----- >> From: Jan Beulich >> Sent: Wednesday, July 16, 2025 11:01 PM >> >> On 11.07.2025 05:50, Penny Zheng wrote: >>> --- a/xen/drivers/cpufreq/cpufreq.c >>> +++ b/xen/drivers/cpufreq/cpufreq.c >>> @@ -64,12 +64,53 @@ LIST_HEAD_READ_MOSTLY(cpufreq_governor_list); >>> /* set xen as default cpufreq */ >>> enum cpufreq_controller cpufreq_controller = FREQCTL_xen; >>> >>> -enum cpufreq_xen_opt __initdata cpufreq_xen_opts[2] = { CPUFREQ_xen, >>> - CPUFREQ_none }; >>> +enum cpufreq_xen_opt __initdata cpufreq_xen_opts[NR_CPUFREQ_OPTS] = { >>> + CPUFREQ_xen, >>> + CPUFREQ_none >>> +}; >>> unsigned int __initdata cpufreq_xen_cnt = 1; >> >> Given this, isn't the array index 1 initializer quite pointless above? Or else, if you >> really mean to explicitly fill all slots with CPUFREQ_none (despite that deliberately >> having numeric value 0), why not >> "[1 ... NR_CPUFREQ_OPTS - 1] = CPUFREQ_none" (or using ARRAY_SIZE(), as >> per below)? >> > > The cpufreq_xen_cnt initialized as 1 is to have default CPUFREQ_xen value when there is no "cpufreq=xxx" cmdline option > I suppose you are pointing out that the macro NR_CPUFREQ_OPTS is pointless, as we could use ARRAY_SIZE(). That I'm suggesting further down, yes. But here I'm questioning the array initializer: As said, I think only slot 0 needs explicit initializing. Or else the initializer would need touching again when the array size is grown. Which would be nice to avoid, providing doing so is correct. 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Mon, 04 Aug 2025 00:25:53 -0700 (PDT) Message-ID: <5f6f16b9-3aea-4407-8938-2ce4cc6edcfd@suse.com> Date: Mon, 4 Aug 2025 09:25:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 10/19] xen/cpufreq: introduce new sub-hypercall to propagate CPPC data To: "Penny, Zheng" Cc: "Huang, Ray" , Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Anthony PERARD , "Orzel, Michal" , Julien Grall , Stefano Stabellini , "xen-devel@lists.xenproject.org" References: <20250711035106.2540522-1-Penny.Zheng@amd.com> <20250711035106.2540522-11-Penny.Zheng@amd.com> <916162aa-01fa-42a3-82c6-42a2c635f082@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 04.08.2025 08:47, Penny, Zheng wrote: > [Public] > >> -----Original Message----- >> From: Jan Beulich >> Sent: Wednesday, July 16, 2025 11:39 PM >> To: Penny, Zheng >> Cc: Huang, Ray ; Andrew Cooper >> ; Roger Pau Monné ; >> Anthony PERARD ; Orzel, Michal >> ; Julien Grall ; Stefano Stabellini >> ; xen-devel@lists.xenproject.org >> Subject: Re: [PATCH v6 10/19] xen/cpufreq: introduce new sub-hypercall to >> propagate CPPC data >> >> On 11.07.2025 05:50, Penny Zheng wrote: >>> + cppc_data->cpc.nominal_perf > cppc_data->cpc.highest_perf ) >>> + /* >>> + * Right now, Xen doesn't actually use highest_perf/nominal_perf/ >>> + * lowest_nonlinear_perf/lowest_perf values read from ACPI _CPC >>> + * table. Xen reads CPPC capability MSR to get these four values. >>> + * So warning is enough. >>> + */ >>> + printk_once(XENLOG_WARNING >>> + "Broken CPPC perf values: lowest(%u), nonlinear_lowest(%u), >> nominal(%u), highest(%u)\n", >>> + cppc_data->cpc.lowest_perf, >>> + cppc_data->cpc.lowest_nonlinear_perf, >>> + cppc_data->cpc.nominal_perf, >>> + cppc_data->cpc.highest_perf); >>> + >>> + /* lowest_mhz and nominal_mhz are optional value */ >>> + if ( cppc_data->cpc.lowest_mhz > cppc_data->cpc.nominal_mhz ) >> >> If they're optional, what if lowest_mhz is provided but nominal_mhz isn't? >> Wouldn't the warning needlessly trigger in that case? >> > > Yes, only both are provided, this check is meaningful > + if ( cppc_data->cpc.nominal_mhz && > + cppc_data->cpc.lowest_mhz > cppc_data->cpc.nominal_mhz ) > >>> --- a/xen/include/public/platform.h >>> +++ b/xen/include/public/platform.h >>> @@ -363,6 +363,7 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t); >>> #define XEN_PM_PX 1 >>> #define XEN_PM_TX 2 >>> #define XEN_PM_PDC 3 >>> +#define XEN_PM_CPPC 4 >>> >>> /* Px sub info type */ >>> #define XEN_PX_PCT 1 >>> @@ -370,6 +371,10 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t); >>> #define XEN_PX_PPC 4 >>> #define XEN_PX_PSD 8 >>> >>> +/* CPPC sub info type */ >>> +#define XEN_CPPC_PSD 1 >>> +#define XEN_CPPC_CPC 2 >> >> As per this, ... >> >>> @@ -457,6 +462,26 @@ struct xen_processor_performance { typedef >>> struct xen_processor_performance xen_processor_performance_t; >>> DEFINE_XEN_GUEST_HANDLE(xen_processor_performance_t); >>> >>> +struct xen_processor_cppc { >>> + uint8_t flags; /* IN: XEN_CPPC_xxx */ >> >> ... it's a type that's living here, not a collection of flags. Any reason the field isn't >> named "type"? > > It is a collection of flags. Only when both XEN_CPPC_PSD and XEN_CPPC_CPC are set, we could run cpufreq_cpu_init() to initialize cpufreq core. Hmm, right. The next legitimate XEN_CPPC_* value to use would be 4, not 3. That's not visible from how things are defined, though. May I suggest that you use /* CPPC sub info type */ #define XEN_CPPC_PSD (1U << 0) #define XEN_CPPC_CPC (1U << 1) instead then? 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b=JYvBWJOCpyoVU3eObYbRIFwt+nsfd8l61Cg7jAmhEMKByxEXtGDtWMeG0cFeFH+i4XY4BXg2GVXl3qJB2vA0St96yCJPjCb2Xcpd+Q7rBElQV+KtXwe4al+p1LaCr3fpTMFDJxsocSRByueWzI/lao8Skjw7ji4YfUR/+g/yuFU= From: Bertrand Marquis To: Demi Marie Obenour CC: "xen-devel@lists.xenproject.org" , "jens.wiklander@linaro.org" , Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Michal Orzel Subject: Re: [PATCH v7 3/6] xen/arm: ffa: Introduce VM to VM support Thread-Topic: [PATCH v7 3/6] xen/arm: ffa: Introduce VM to VM support Thread-Index: AQHb9xP9tgnM92Sxpk+5sdmAsJMirrRQbvOAgAHDiYA= Date: Mon, 4 Aug 2025 07:21:07 +0000 Message-ID: References: <50224eb7cca4eaef2646ad8e33f689d912704733.1752754016.git.bertrand.marquis@arm.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3826.600.51.1.1) Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; x-ms-traffictypediagnostic: DB9PR08MB6588:EE_|DB9PR08MB8699:EE_|AM4PEPF00027A61:EE_|DU0PR08MB9558:EE_ X-MS-Office365-Filtering-Correlation-Id: 3172c775-100c-4297-f8f7-08ddd3278eab x-checkrecipientrouted: true nodisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230040|1800799024|366016|376014|10070799003|38070700018; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 07:21:40.6177 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3172c775-100c-4297-f8f7-08ddd3278eab X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A61.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB9558 Hi Demi, > On 3 Aug 2025, at 06:24, Demi Marie Obenour wrote= : >=20 > On 7/17/25 08:11, Bertrand Marquis wrote: >> Create a CONFIG_FFA_VM_TO_VM parameter to activate FFA communication >> between VMs. >> When activated list VMs in the system with FF-A support in part_info_get= . >>=20 >> When VM to VM is activated, Xen will be tainted as Insecure and a >> message is displayed to the user during the boot as there is no >> filtering of VMs in FF-A so any VM can communicate or see any other VM >> in the system. >>=20 >> WARNING: There is no filtering for now and all VMs are listed !! > I'm pretty sure that there is already no filtering for things like grant > tables and event channels, so this doesn't make things any worse. That > said, FF-A is quite tricky to implement without integer overflow/wraparou= nd > or denial of service bugs. In particular, code in Hafnium (Secure Partit= ion > Monitor running in S-EL2) requires quadratic time because of repeated lin= ear > searches. Xen is allowed to use dynamic memory allocation, so it can, sh= ould, > and must do better. I do agree but we still have tricky cases where we could end up in unbounde= d loops. Some are handled by adding some limits. Dynamic allocation being available in Xen is helping a lot on some cases bu= t for now I try to prevent it when possible but we might have to review this later if= we want to increase some capacities (for example the number of shared memories). I plan to do a presentation at the Xen Summit and a design session to discu= ss how we could define a way to define by configuration or at runtime what secure = endpoints or VMs can be contacted by a VM with FF-A enabled. Regards Bertrand > --=20 > Sincerely, > Demi Marie Obenour (she/her/hers) From xen-devel-bounces@lists.xenproject.org Mon Aug 04 07:40:57 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 07:40:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068848.1432705 (Exim 4.92) (envelope-from ) id 1uipoS-0002u1-Q7; Mon, 04 Aug 2025 07:40:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068848.1432705; Mon, 04 Aug 2025 07:40:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uipoS-0002tu-Mc; Mon, 04 Aug 2025 07:40:52 +0000 Received: by outflank-mailman (input) for mailman id 1068848; Mon, 04 Aug 2025 07:40:51 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uipoR-0002sG-Bt for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 07:40:51 +0000 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [2a00:1450:4864:20::530]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 579b0470-7106-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 09:40:50 +0200 (CEST) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-61571192ba5so6016069a12.2 for ; Mon, 04 Aug 2025 00:40:50 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Mon, 04 Aug 2025 00:40:49 -0700 (PDT) Message-ID: <770f41e5-5d02-4358-8f91-e577f762cf58@suse.com> Date: Mon, 4 Aug 2025 09:40:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 05/25] xen: introduce CONFIG_DOMCTL To: Penny Zheng Cc: ray.huang@amd.com, Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <20250803094738.3625269-1-Penny.Zheng@amd.com> <20250803094738.3625269-6-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250803094738.3625269-6-Penny.Zheng@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 03.08.2025 11:47, Penny Zheng wrote: > --- a/xen/common/Kconfig > +++ b/xen/common/Kconfig > @@ -627,6 +627,10 @@ config SYSCTL > This option shall only be disabled on some dom0less systems, or > PV shim on x86, to reduce Xen footprint. > > +config DOMCTL > + bool "Enable domctl hypercall" > + def_bool y > + Just to re-iterate - we don't think we want things to be this fine-grained. (As an aside, nit: "bool" and "def_bool" are partly redundant with one another.) Jan From xen-devel-bounces@lists.xenproject.org Mon Aug 04 07:42:49 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 07:42:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1068858.1432716 (Exim 4.92) (envelope-from ) id 1uipqK-0003bW-7p; Mon, 04 Aug 2025 07:42:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1068858.1432716; Mon, 04 Aug 2025 07:42:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uipqK-0003bP-4W; Mon, 04 Aug 2025 07:42:48 +0000 Received: by outflank-mailman (input) for mailman id 1068858; Mon, 04 Aug 2025 07:42:46 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uipqI-0003bH-U9 for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 07:42:46 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9c8834b1-7106-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 09:42:46 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-adfb562266cso658753866b.0 for ; Mon, 04 Aug 2025 00:42:46 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Mon, 04 Aug 2025 00:42:45 -0700 (PDT) Message-ID: <371bc812-acdb-41ef-950b-3c9e5feea48e@suse.com> Date: Mon, 4 Aug 2025 09:42:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 01/25] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE To: Penny Zheng Cc: ray.huang@amd.com, Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , xen-devel@lists.xenproject.org References: <20250803094738.3625269-1-Penny.Zheng@amd.com> <20250803094738.3625269-2-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250803094738.3625269-2-Penny.Zheng@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 03.08.2025 11:47, Penny Zheng wrote: > In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and > HVM=y results in hvm.c being built, but domctl.c not being built, which leaves > a few functions, like domctl_lock_acquire/release() undefined, causing linking > to fail. > To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile > /hypercall-defs section, with this adjustment, we also need to release > redundant vnuma_destroy() stub definition and paging_domctl hypercall-defs > from PV_SHIM_EXCLUSIVE guardian, to not break compilation > Above change will leave dead code in the shim binary temporarily and will be > fixed with the introduction of CONFIG_DOMCTL. > > Fixes: 568f806cba4c ("xen/x86: remove "depends on !PV_SHIM_EXCLUSIVE"") > Reported-by: Jan Beulich > Signed-off-by: Penny Zheng > --- > v1 -> v2: > - remove paging_domctl hypercall-defs And you've run this through a full round of testing this time, in isolation? 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Smith" , Shawn Anastasio , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu , Bertrand Marquis , Volodymyr Babchuk , Alistair Francis , Bob Eshleman , Connor Davis , Oleksii Kurochko , Christopher Clark , Dario Faggioli , Juergen Gross , George Dunlap , Nathan Studer , Stewart Hildebrand , Meng Xu , Rahul Singh , xen-devel@lists.xenproject.org, xen-devel@dornerworks.com References: <20250803094738.3625269-1-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250803094738.3625269-1-Penny.Zheng@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 03.08.2025 11:47, Penny Zheng wrote: > It can be beneficial for some dom0less systems to further reduce Xen footprint > via disabling some hypercalls handling code, which may not to be used & > required in such systems. Each hypercall has a separate option to keep > configuration flexible. > > Options to disable hypercalls: > - sysctl > - domctl > - hvm > - physdev > - platform > > This patch serie is only focusing on introducing CONFIG_DOMCTL. Different > options will be covered in different patch serie. > > Features, like VM event, or paging log-dirty support, which fully rely on > domctl op, will be wrapped with CONFIG_SYSCTL, to reduce Xen footprint as > much as possible. > > It is derived from Stefano Stabellini's commit "xen: introduce kconfig options to > disable hypercalls"( > https://lore.kernel.org/xen-devel/20241219092917.3006174-1-Sergiy_Kibrik@epam.com) > > Penny Zheng (25): > xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE > xen/x86: consolidate vram tracking support > xen/x86: complement PG_log_dirty wrapping > xen: consolidate CONFIG_VM_EVENT > xen: introduce CONFIG_DOMCTL > xen/domctl: provide stub for domctl_lock_{acquire,release} > xen/domctl: wrap around XEN_DOMCTL_pausedomain > xen/domctl: wrap around XEN_DOMCTL_soft_reset > xen/domctl: wrap around XEN_DOMCTL_destroydomain > xen/domctl: wrap around XEN_DOMCTL_setnodeaffinity > xen/domctl: wrap around XEN_DOMCTL_{getvcpuaffinity,setvcpuaffinity} > xen/domctl: wrap around XEN_DOMCTL_scheduler_op > xen/domctl: wrap around XEN_DOMCTL_getvcpucontext > xen/domctl: wrap around XEN_DOMCTL_{irq_permission,iomem_permission} > xen/domctl: wrap around XEN_DOMCTL_settimeoffset > xen/domctl: wrap around XEN_DOMCTL_set_target > xen: add stub for XEN_DOMCTL_getdomaininfo > xen/domctl: wrap around XEN_DOMCTL_set_access_required > xen: make CONFIG_VM_EVENT depend on DOMCTL > xen/domctl: wrap around XEN_DOMCTL_set_virq_handler > xen/domctl: wrap aound iommu-related domctl op > xen/domctl: wrap around XEN_DOMCTL_{get,set}_paging_mempool_size > xen/x86: make CONFIG_X86_PSR depend on SYSCTL || DOMCTL > xen/domctl: wrap around arch-specific domctl op > xen/domctl: wrap around domctl hypercall Hmm, I should have remembered to Cc you on this [1] reply of mine to Jiqian. It applies here as well. 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Mon, 04 Aug 2025 00:57:37 -0700 (PDT) Message-ID: <52ea4f10-26b4-447b-8753-0e4287a03408@suse.com> Date: Mon, 4 Aug 2025 09:57:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create To: Stewart Hildebrand Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Dario Faggioli , Juergen Gross , George Dunlap , xen-devel@lists.xenproject.org References: <20250801202418.38977-1-stewart.hildebrand@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250801202418.38977-1-stewart.hildebrand@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 01.08.2025 22:24, Stewart Hildebrand wrote: > @@ -839,6 +839,9 @@ void sched_destroy_vcpu(struct vcpu *v) > { > struct sched_unit *unit = v->sched_unit; > > + if ( !unit ) > + return; > + > kill_timer(&v->periodic_timer); > kill_timer(&v->singleshot_timer); > kill_timer(&v->poll_timer); What if it's the 2nd error path in sched_init_vcpu() that is taken? Then we might take this path (just out of context here) if ( unit->vcpu_list == v ) { rcu_read_lock(&sched_res_rculock); sched_remove_unit(vcpu_scheduler(v), unit); sched_free_udata(vcpu_scheduler(v), unit->priv); and at least Credit1's hook doesn't look to be safe against being passed NULL. (Not to speak of the risk of unit->priv being used elsewhere while cleaning up.) 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Mon, 04 Aug 2025 01:02:03 -0700 (PDT) Message-ID: <9d71cc11-884d-4924-9de9-e3396801158a@suse.com> Date: Mon, 4 Aug 2025 10:02:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC] Next steps for MISRA C Rule 17.7 in XEN To: Dmytro Prokopchuk1 , Stefano Stabellini Cc: Nicola Vetrini , "xen-devel@lists.xenproject.org" References: <6d622813-1617-4af3-876e-52a551518f68@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6d622813-1617-4af3-876e-52a551518f68@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 02.08.2025 19:48, Dmytro Prokopchuk1 wrote: > There are a lot of MISRA C R17.7 violations in the XEN. > This rule states: "The value returned by a function having non-void > return type shall be used". > > Actually, need to decide how to deal with these violations. > Quick analyze shown that there are different cases in XEN code base. Long ago, when we discussed the rules in a mainly abstract way, there already was quite a bit of discussion around this. Stefano - I wonder if you had taken (and have kept) notes back at the time? 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Mon, 04 Aug 2025 01:10:51 -0700 (PDT) Message-ID: <2464e97d-e950-4645-9aa9-5c2cddab72b2@suse.com> Date: Mon, 4 Aug 2025 10:10:52 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/3] arm/pci: Add pci-scan boot argument To: Mykyta Poturai Cc: Edward Pickup , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Bertrand Marquis , Volodymyr Babchuk , Luca Fancellu , Stewart Hildebrand , "xen-devel@lists.xenproject.org" References: <98c8889e07d6c82067309d8458e15dd52145b467.1753968306.git.mykyta_poturai@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <98c8889e07d6c82067309d8458e15dd52145b467.1753968306.git.mykyta_poturai@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 01.08.2025 11:22, Mykyta Poturai wrote: > From: Edward Pickup > > This patch adds a Xen boot arguments that, if enabled, causes a call to > existing code to scan pci devices enumerated by the firmware. > > This patch also makes an existing debug function viewable outside its > translation unit, and uses this to dump the PCI devices found. > The debug message is controlled by config DEBUG. > > Additionally, this patch modifies segment loading to ensure that PCI > devices on other segments are properly found. > > This will be needed ahead of dom0less support for pci passthrough on > arm. > > Signed-off-by: Luca Fancellu > Signed-off-by: Edward Pickup Considering the From: above and this order of S-o-b: Who is it really that was the original author here? > --- a/xen/arch/arm/include/asm/pci.h > +++ b/xen/arch/arm/include/asm/pci.h > @@ -23,6 +23,7 @@ > #define pci_to_dev(pcidev) (&(pcidev)->arch.dev) > > extern bool pci_passthrough_enabled; > +extern bool pci_scan_enabled; With the variable non-static, ... > @@ -128,6 +129,11 @@ static always_inline bool is_pci_passthrough_enabled(void) > return pci_passthrough_enabled; > } > > +static inline bool is_pci_scan_enabled(void) > +{ > + return pci_scan_enabled; > +} > + > void arch_pci_init_pdev(struct pci_dev *pdev); > > int pci_get_new_domain_nr(void); > @@ -155,6 +161,11 @@ bool arch_pci_device_physdevop(void); > > #else /*!CONFIG_HAS_PCI*/ > > +static inline bool is_pci_scan_enabled(void) > +{ > + return false; > +} ... what's the point of the wrappers? Constrain the variable as such to HAS_PCI=y, and use "#define pci_scan_enabled false" in the opposite case. Just like we do elsewhere in a number of cases. > --- a/xen/arch/arm/pci/pci.c > +++ b/xen/arch/arm/pci/pci.c > @@ -91,8 +91,13 @@ bool arch_pci_device_physdevop(void) > bool __read_mostly pci_passthrough_enabled; > boolean_param("pci-passthrough", pci_passthrough_enabled); > > +/* By default pci scan is disabled. */ > +bool __read_mostly pci_scan_enabled; __ro_after_init? > +boolean_param("pci-scan", pci_scan_enabled); > + > static int __init pci_init(void) > { > + int ret; > /* Nit: Blank line please between declaration(s) and statement(s). > @@ -104,9 +109,26 @@ static int __init pci_init(void) > panic("Could not initialize PCI segment 0\n"); > > if ( acpi_disabled ) > - return dt_pci_init(); > + ret = dt_pci_init(); > else > - return acpi_pci_init(); > + ret = acpi_pci_init(); > + > + if ( ret < 0 ) > + return ret; > + > + if ( is_pci_scan_enabled() ) > + { > + ret = scan_pci_devices(); > + > + if ( ret < 0 ) > + return ret; > + > +#ifdef DEBUG > + dump_pci_devices('c'); > +#endif If I was a maintainer of this code, I would request such to be dropped. Or if there was a good reason to have such, I think it would want to be arch-independent. > --- a/xen/drivers/passthrough/pci.c > +++ b/xen/drivers/passthrough/pci.c > @@ -1384,7 +1384,7 @@ static int cf_check _dump_pci_devices(struct pci_seg *pseg, void *arg) > return 0; > } > > -static void cf_check dump_pci_devices(unsigned char ch) > +void cf_check dump_pci_devices(unsigned char ch) Note the cf_check here. It, for some reason, ... > --- a/xen/include/xen/pci.h > +++ b/xen/include/xen/pci.h > @@ -217,6 +217,7 @@ static always_inline bool pcidevs_trylock(void) > bool pci_known_segment(u16 seg); > bool pci_device_detect(u16 seg, u8 bus, u8 dev, u8 func); > int scan_pci_devices(void); > +void dump_pci_devices(unsigned char ch); ... needs reproducing on the declaration. What about x86 though? It'll end up as a non-static function with no caller outside of the defining CU, hence violating some Misra rule. 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Smith" , "xen-devel@lists.xenproject.org" References: <32cf834e95664805604b13d10bcaa857897f0890.1753968306.git.mykyta_poturai@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <32cf834e95664805604b13d10bcaa857897f0890.1753968306.git.mykyta_poturai@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 01.08.2025 11:22, Mykyta Poturai wrote: > From: Luca Fancellu > > Currently pci_add_device is called from hypercalls requested by Dom0 > to add pci devices and when the device has no domain associated with > it, it is assumed that hardware_domain is the owner. > > On the dom0less scenario, the enumeration is performed by the > firmware and Xen at boot time might want to assign some pci devices > to guests, so it has to firstly add the device and then assign it to > the final guest. > > Modify pci_add_device to have the owner domain passed as a parameter > to the function, so that when it is called from the hypercall the > owner would be the hardware domain, otherwise when Xen is calling it, > it would be another domain since hw domain could not be there > (dom0less guests without Dom0 use case). > > In pci_add_device there is a call to xsm that doesn't consider the > requester of the function to be Xen itself, so add a check to skip > the call if the owner domain is dom_io, since it means the call is > coming directly from Xen. I don't understand this particular aspect: All call sites pass hardware_domain. Checking against dom_io therefore looks unnecessary, or at least premature. In Misra's terms it is "dead code" that you add. > --- a/xen/drivers/passthrough/pci.c > +++ b/xen/drivers/passthrough/pci.c > @@ -654,7 +654,7 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned int pos, > return is64bits ? 2 : 1; > } > > -int pci_add_device(u16 seg, u8 bus, u8 devfn, > +int pci_add_device(struct domain *d, u16 seg, u8 bus, u8 devfn, > const struct pci_dev_info *info, nodeid_t node) For a pci_*() function I don't think it's appropriate to have a domain (not a PCI domain, aka segment, which would be fine) as first parameter. While you touch this it might also be nice if you switched u to uint_t. > --- a/xen/drivers/pci/physdev.c > +++ b/xen/drivers/pci/physdev.c > @@ -50,7 +50,8 @@ ret_t pci_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg) > } > #endif > > - ret = pci_add_device(add.seg, add.bus, add.devfn, &pdev_info, node); > + ret = pci_add_device(hardware_domain, add.seg, add.bus, add.devfn, > + &pdev_info, node); Here as well as in the x86-specific counterparts: Why hardware_domain, i.e. why not current->domain? Yes, what you do is in line with how the code has behaved so far, but now that you want to change it, it needs to be sorted what it is that's really wanted. This btw also plays into the XSM aspect that you're fiddling with. Also, what if you end up passing NULL here in the dom0less case? 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Mon, 04 Aug 2025 01:35:37 -0700 (PDT) Message-ID: <123626b4-3234-40e5-b1cf-bd5c2b19cbc8@suse.com> Date: Mon, 4 Aug 2025 10:35:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/3] xen/pci: add discovered PCI device at boot To: Mykyta Poturai Cc: Luca Fancellu , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , "xen-devel@lists.xenproject.org" References: <5097b76acf0a5c64cc78522f6af6233370c948e6.1753968306.git.mykyta_poturai@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5097b76acf0a5c64cc78522f6af6233370c948e6.1753968306.git.mykyta_poturai@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 01.08.2025 11:22, Mykyta Poturai wrote: > Create add_discovered_pci_devices function that calls pci_device_add > on every PCI device discovered. > The devices will be added to dom_io so that they can be assigned > later to other domains. And why's the intermediate step necessary? IOW can't they be assigned to their target domains right away, and only whatever's left would go to DOM_IO? > --- a/xen/drivers/passthrough/pci.c > +++ b/xen/drivers/passthrough/pci.c > @@ -1180,6 +1180,34 @@ int __init scan_pci_devices(void) > return ret; > } > > +static int __init _add_discovered_pci_devices(struct pci_seg *pseg, void *arg) > +{ > + struct pci_dev *pdev; > + int ret = 0; > + > + list_for_each_entry ( pdev, &pseg->alldevs_list, alldevs_list ) > + { > + ret = pci_add_device(dom_io, pdev->seg, pdev->bus, pdev->devfn, NULL, > + NUMA_NO_NODE); > + if ( ret < 0 ) > + { > + printk(XENLOG_ERR > + "%pp: Failure adding the discovered pci device (Error %d)\n", > + &pdev->sbdf, ret); > + break; > + } > + } > + > + return ret; > +} > + > +void __init add_discovered_pci_devices(void) > +{ > + pcidevs_lock(); > + pci_segments_iterate(_add_discovered_pci_devices, NULL); > + pcidevs_unlock(); > +} This looks to merely be a specialized form of what ... > struct setup_hwdom { > struct domain *d; > int (*handler)(uint8_t devfn, struct pci_dev *pdev); ... follows below here. By generalizing what we have (perhaps from the top, i.e. iommu_hwdom_init()), you'd also avoid violating Misra rule 2.1 on x86, as you add unreachable code there. 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Mon, 04 Aug 2025 01:38:21 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 10:38:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 05/25] xen: introduce CONFIG_DOMCTL To: "Penny, Zheng" Cc: "Huang, Ray" , Andrew Cooper , Anthony PERARD , "Orzel, Michal" , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , "xen-devel@lists.xenproject.org" References: <20250803094738.3625269-1-Penny.Zheng@amd.com> <20250803094738.3625269-6-Penny.Zheng@amd.com> <770f41e5-5d02-4358-8f91-e577f762cf58@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 04.08.2025 10:29, Penny, Zheng wrote: > [Public] > >> -----Original Message----- >> From: Jan Beulich >> Sent: Monday, August 4, 2025 3:41 PM >> To: Penny, Zheng >> Cc: Huang, Ray ; Andrew Cooper >> ; Anthony PERARD ; >> Orzel, Michal ; Julien Grall ; Roger Pau >> Monné ; Stefano Stabellini ; xen- >> devel@lists.xenproject.org >> Subject: Re: [PATCH v1 05/25] xen: introduce CONFIG_DOMCTL >> >> On 03.08.2025 11:47, Penny Zheng wrote: >>> --- a/xen/common/Kconfig >>> +++ b/xen/common/Kconfig >>> @@ -627,6 +627,10 @@ config SYSCTL >>> This option shall only be disabled on some dom0less systems, or >>> PV shim on x86, to reduce Xen footprint. >>> >>> +config DOMCTL >>> + bool "Enable domctl hypercall" >>> + def_bool y >>> + >> >> Just to re-iterate - we don't think we want things to be this fine-grained. >> (As an aside, nit: "bool" and "def_bool" are partly redundant with one >> another.) >> > > Are we suggesting to use one Kconfig, maybe like CONFIG_XENCTL(not a good choice, just popping in my head...), to wrap all scenarios, including sysctl-op, domctl-op, jiqian's platform-op, etc ? Yes, that's the thought that was circulated, and that I had hoped Stefano would have conveyed. > In which case, maybe we still submit commits(or features) serie by serie, more easy to review, but only when all is completed, we make this Kconfig as an selectable option ? Likely the best route, but that may then mean stepping back a little on SYSCTL, before trying to deal with SYSCTL and maybe PLATFORM_OP (albeit I raised further reservations there). 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Mon, 04 Aug 2025 01:48:27 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 10:48:29 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 11/19] xen/x86: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc driver To: "Penny, Zheng" Cc: "Huang, Ray" , Andrew Cooper , Anthony PERARD , "Orzel, Michal" , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , "xen-devel@lists.xenproject.org" References: <20250711035106.2540522-1-Penny.Zheng@amd.com> <20250711035106.2540522-12-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 04.08.2025 10:09, Penny, Zheng wrote: > [Public] > >> -----Original Message----- >> From: Jan Beulich >> Sent: Thursday, July 17, 2025 12:00 AM >> To: Penny, Zheng >> Cc: Huang, Ray ; Andrew Cooper >> ; Anthony PERARD ; >> Orzel, Michal ; Julien Grall ; Roger Pau >> Monné ; Stefano Stabellini ; xen- >> devel@lists.xenproject.org >> Subject: Re: [PATCH v6 11/19] xen/x86: introduce "cpufreq=amd-cppc" xen cmdline >> and amd-cppc driver >> >> On 11.07.2025 05:50, Penny Zheng wrote: >>> --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c >>> +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c >>> @@ -128,12 +128,14 @@ static int __init cf_check >>> cpufreq_driver_init(void) >>> >>> if ( cpufreq_controller == FREQCTL_xen ) >>> { >>> + unsigned int i = 0; >> >> Pointless initializer; both for() loops set i to 0. But also see further down. >> >>> @@ -157,9 +164,70 @@ static int __init cf_check >>> cpufreq_driver_init(void) >>> >>> case X86_VENDOR_AMD: >>> case X86_VENDOR_HYGON: >>> - ret = IS_ENABLED(CONFIG_AMD) ? powernow_register_driver() : - >> ENODEV; >>> + if ( !IS_ENABLED(CONFIG_AMD) ) >>> + { >>> + ret = -ENODEV; >>> + break; >>> + } >>> + ret = -ENOENT; >> >> The code structure is sufficiently different from the Intel counterpart for this to >> perhaps better move ... >> >>> + for ( i = 0; i < cpufreq_xen_cnt; i++ ) >>> + { >>> + switch ( cpufreq_xen_opts[i] ) >>> + { >>> + case CPUFREQ_xen: >>> + ret = powernow_register_driver(); >>> + break; >>> + >>> + case CPUFREQ_amd_cppc: >>> + ret = amd_cppc_register_driver(); >>> + break; >>> + >>> + case CPUFREQ_none: >>> + ret = 0; >>> + break; >>> + >>> + default: >>> + printk(XENLOG_WARNING >>> + "Unsupported cpufreq driver for vendor AMD or Hygon\n"); >>> + break; >> >> ... here. >> > > Are we suggesting moving > " > if ( !IS_ENABLED(CONFIG_AMD) ) > { > ret = -ENODEV; > break; > } > " here? In which case, When CONFIG_AMD=n and users doesn't provide "cpufreq=xxx", we will have cpufreq_xen_cnt initialized as 1 and cpufreq_xen_opts[0] = CPUFREQ_xen. powernow_register_driver() hence gets invoked. The thing is that we don't have stub for it and it is compiled under CONFIG_AMD > I suggest to change to use #ifdef CONFIG_AMD code wrapping > >>> + } >>> + >>> + if ( !ret || ret == -EBUSY ) >>> + break; >>> + } >>> + >>> break; >>> } >>> + >>> + /* >>> + * After successful cpufreq driver registeration, >> XEN_PROCESSOR_PM_CPPC >>> + * and XEN_PROCESSOR_PM_PX shall become exclusive flags. >>> + */ >>> + if ( !ret ) >>> + { >>> + ASSERT(i < cpufreq_xen_cnt); >>> + switch ( cpufreq_xen_opts[i] ) >> >> Hmm, this is using the the initializer of i that I commented on. I think there's >> another default: case missing, where you simply "return 0" (to retain prior behavior). >> But again see also yet further down. >> >> >>> + /* >>> + * No cpufreq driver gets registered, clear both >>> + * XEN_PROCESSOR_PM_CPPC and XEN_PROCESSOR_PM_PX >>> + */ >>> + xen_processor_pmbits &= ~(XEN_PROCESSOR_PM_CPPC | >>> + XEN_PROCESSOR_PM_PX); >> >> Yet more hmm - this path you want to get through for the case mentioned above. >> But only this code; specifically not the "switch ( cpufreq_xen_opts[i] )", which really >> is "switch ( cpufreq_xen_opts[0] )" in that case, and that's pretty clearly wrong to >> evaluate in then. > > Correct me if I understand you wrongly: > The above "case missing" , are we talking about is entering "case CPUFREQ_none" ? > IMO, it may never be entered. If users doesn't provide "cpufreq=xxx", we will have cpufreq_xen_cnt initialized as 1 and cpufreq_xen_opts[0] = CPUFREQ_xen. That is, we will have px states as default driver. Even if we have failed px-driver initialization, with cpufreq_xen_cnt limited to 1, we will not enter CPUFREQ_none. > CPUFREQ_none only could be set when users explicitly set "cpufreq=disabled/none/0", but in which case, cpufreq_controller will be set with FREQCTL_none. And the whole cpufreq_driver_init() is under " cpufreq_controller == FREQCTL_xen " condition > Or "case missing" is referring entering default case? In which case, we will have -ENOENT errno. As we have ret=-ENOENT in the very beginning Sorry, this is hard to follow. Plus I think I made the main requirement quite clear: You want to "retain prior behavior" for all cases you don't deliberately change to accommodate the new driver. Plus you want to watch out for pre- existing incorrect behavior: Rather than proliferating any, such would want adjusting. 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Mon, 04 Aug 2025 01:48:48 -0700 (PDT) Message-ID: <4df7c533-8d6e-4cf6-9ab2-90a00a31ebbb@suse.com> Date: Mon, 4 Aug 2025 10:48:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 11/19] xen/x86: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc driver To: "Penny, Zheng" Cc: "Huang, Ray" , Andrew Cooper , Anthony PERARD , "Orzel, Michal" , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , "xen-devel@lists.xenproject.org" References: <20250711035106.2540522-1-Penny.Zheng@amd.com> <20250711035106.2540522-12-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 04.08.2025 10:09, Penny, Zheng wrote: > [Public] > >> -----Original Message----- >> From: Jan Beulich >> Sent: Thursday, July 17, 2025 12:00 AM >> To: Penny, Zheng >> Cc: Huang, Ray ; Andrew Cooper >> ; Anthony PERARD ; >> Orzel, Michal ; Julien Grall ; Roger Pau >> Monné ; Stefano Stabellini ; xen- >> devel@lists.xenproject.org >> Subject: Re: [PATCH v6 11/19] xen/x86: introduce "cpufreq=amd-cppc" xen cmdline >> and amd-cppc driver >> >> On 11.07.2025 05:50, Penny Zheng wrote: >>> --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c >>> +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c >>> @@ -128,12 +128,14 @@ static int __init cf_check >>> cpufreq_driver_init(void) >>> >>> if ( cpufreq_controller == FREQCTL_xen ) >>> { >>> + unsigned int i = 0; >> >> Pointless initializer; both for() loops set i to 0. But also see further down. >> >>> @@ -157,9 +164,70 @@ static int __init cf_check >>> cpufreq_driver_init(void) >>> >>> case X86_VENDOR_AMD: >>> case X86_VENDOR_HYGON: >>> - ret = IS_ENABLED(CONFIG_AMD) ? powernow_register_driver() : - >> ENODEV; >>> + if ( !IS_ENABLED(CONFIG_AMD) ) >>> + { >>> + ret = -ENODEV; >>> + break; >>> + } >>> + ret = -ENOENT; >> >> The code structure is sufficiently different from the Intel counterpart for this to >> perhaps better move ... >> >>> + for ( i = 0; i < cpufreq_xen_cnt; i++ ) >>> + { >>> + switch ( cpufreq_xen_opts[i] ) >>> + { >>> + case CPUFREQ_xen: >>> + ret = powernow_register_driver(); >>> + break; >>> + >>> + case CPUFREQ_amd_cppc: >>> + ret = amd_cppc_register_driver(); >>> + break; >>> + >>> + case CPUFREQ_none: >>> + ret = 0; >>> + break; >>> + >>> + default: >>> + printk(XENLOG_WARNING >>> + "Unsupported cpufreq driver for vendor AMD or Hygon\n"); >>> + break; >> >> ... here. >> > > Are we suggesting moving > " > if ( !IS_ENABLED(CONFIG_AMD) ) > { > ret = -ENODEV; > break; > } > " here? That's what I said, didn't I? > In which case, When CONFIG_AMD=n and users doesn't provide "cpufreq=xxx", we will have cpufreq_xen_cnt initialized as 1 and cpufreq_xen_opts[0] = CPUFREQ_xen. powernow_register_driver() hence gets invoked. The thing is that we don't have stub for it and it is compiled under CONFIG_AMD > I suggest to change to use #ifdef CONFIG_AMD code wrapping Perhaps necessary, yes. As you know, we generally prefer IS_ENABLED() where possible, but when not possible, #ifdef is certainly okay to use. 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Mon, 04 Aug 2025 02:34:31 -0700 (PDT) Message-ID: <4ceb64fa-d7cb-4c77-8a60-1526046c037c@suse.com> Date: Mon, 4 Aug 2025 11:34:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen/x86: fix xen.efi boot crash from some bootloaders To: Yann Sionneau Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , xen-devel@lists.xenproject.org References: <20250724140731.1502774-1-yann.sionneau@vates.tech> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250724140731.1502774-1-yann.sionneau@vates.tech> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 24.07.2025 16:07, Yann Sionneau wrote: > xen.efi PE does not boot when loaded from shim or some patched > downstream grub2. > > What happens is the bootloader would honour the MEM_DISCARDABLE > flag of the .reloc section meaning it would not load its content > into memory. > > But Xen is parsing the .reloc section content twice at boot: > * https://elixir.bootlin.com/xen/v4.20.1/source/xen/common/efi/boot.c#L1362 > * https://elixir.bootlin.com/xen/v4.20.1/source/xen/arch/x86/efi/efi-boot.h#L237 > > Therefore it would crash with the following message: > "Unsupported relocation type" as reported there: > > * https://github.com/QubesOS/qubes-issues/issues/8206#issuecomment-2619048838 > * https://lore.kernel.org/xen-devel/7e039262-1f54-46e1-8f70-ac3f03607d5a@suse.com/T/#me122b9e6c27cd98db917da2c9f67e74a2c6ad7a5 > > This commit adds a small C host tool named keeprelocs > that is called after xen.efi is produced by the build system > in order to remove this bit from its .reloc section header. > > Signed-off-by: Yann Sionneau So I found a way to deal with this at the linker side, without any new command line options. Behavior is solely driven by the attributes of any incoming .reloc sections (of which there would be none by default, retaining original behavior). The important patch is [1], but at least the first patch of the series [2] would in most cases also be wanted/needed (patch 04 is obviously a mechanical prereq for the main patch). Need for other of the prereqs there depends on the scope and purpose of one's binutils build(s). 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Mon, 04 Aug 2025 02:46:34 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 11:46:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/8] xen/domain: introduce common emulation flags To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-2-dmukhin@ford.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250731192130.3948419-2-dmukhin@ford.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 21:21, dmkhn@proton.me wrote: > --- a/xen/include/xen/sched.h > +++ b/xen/include/xen/sched.h > @@ -652,6 +652,8 @@ struct domain > unsigned int *llc_colors; > #endif > > + uint32_t emulation_flags; Just one further remark: The field probably never should have been of this type; unsigned int will do, and imo will want switching to while the field is being moved. (Before giving an x86 ack, I want to convince myself though that this is moving us in the right direction.) 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Mon, 04 Aug 2025 03:11:01 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 12:11:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-3-dmukhin@ford.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250731192130.3948419-3-dmukhin@ford.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 21:21, dmkhn@proton.me wrote: > From: Denis Mukhin > > Introduce a driver framework to abstract UART emulators in the hypervisor. > > That allows for architecture-independent handling of virtual UARTs in the > console driver and simplifies enabling new UART emulators. > > The framework is built under CONFIG_HAS_VUART, which will be automatically > enabled once the user enables any UART emulator. Yet then still - why "HAS"? Call it just VUART or VUART_FRAMEWORK or some such. > --- a/xen/common/Kconfig > +++ b/xen/common/Kconfig > @@ -1,6 +1,8 @@ > > menu "Common Features" > > +source "common/emul/Kconfig" > + > config COMPAT Why at the very top? > --- a/xen/common/Makefile > +++ b/xen/common/Makefile > @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o > obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/ > obj-$(CONFIG_IOREQ_SERVER) += dm.o > obj-y += domain.o > +obj-y += emul/ > obj-y += event_2l.o > obj-y += event_channel.o > obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o > diff --git a/xen/common/emul/Kconfig b/xen/common/emul/Kconfig > new file mode 100644 > index 000000000000..7c6764d1756b > --- /dev/null > +++ b/xen/common/emul/Kconfig > @@ -0,0 +1,6 @@ > +menu "Domain Emulation Features" > + visible if EXPERT > + > +source "common/emul/vuart/Kconfig" > + > +endmenu > diff --git a/xen/common/emul/Makefile b/xen/common/emul/Makefile > new file mode 100644 > index 000000000000..670682102c13 > --- /dev/null > +++ b/xen/common/emul/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_HAS_VUART) += vuart/ With this you can ... > --- /dev/null > +++ b/xen/common/emul/vuart/Makefile > @@ -0,0 +1 @@ > +obj-$(CONFIG_HAS_VUART) += vuart.o ... use the simpler obj-y here. > --- /dev/null > +++ b/xen/common/emul/vuart/vuart.c > @@ -0,0 +1,112 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * UART emulator framework. > + * > + * Copyright 2025 Ford Motor Company > + */ > + > +#include > +#include > +#include > + > +#define VUART_ARRAY_SIZE (__start_vuart_end - __start_vuart_array) > + > +#define for_each_vuart(vdev) \ > + for (unsigned __i = 0; \ > + __i < VUART_ARRAY_SIZE && (vdev = __start_vuart_array[__i], 1); \ > + __i++) Nit: Xen style please. Any preferably no leading underscores; in no case two of them. > +extern const struct vuart_ops *const __start_vuart_array[]; > +extern const struct vuart_ops *const __start_vuart_end[]; Is there an actual need for this extra level of indirection? It is in the process of being done away with for vPCI. > +int vuart_add_node(struct domain *d, const void *node) > +{ > + const struct vuart_ops *vdev; > + int rc; > + > + for_each_vuart(vdev) > + { > + if ( !vdev->add_node ) > + continue; > + > + rc = vdev->add_node(d, node); Here and below - shouldn't you call hooks only when the kind of driver is actually enabled for the domkain in question? > + if ( rc ) > + return rc; > + } > + > + return 0; > +} > + > +int vuart_init(struct domain *d, struct vuart_params *params) > +{ > + const struct vuart_ops *vdev; > + int rc; > + > + if ( !domain_has_vuart(d) ) > + return 0; > + > + for_each_vuart(vdev) > + { > + rc = vdev->init(d, params); > + if ( rc ) > + return rc; > + } > + > + d->console.input_allowed = true; Unconditionally? > +void vuart_deinit(struct domain *d) > +{ > + const struct vuart_ops *vdev; > + > + for_each_vuart(vdev) > + vdev->deinit(d); > +} I can perhaps see why this hook wants to uniformly be set, but ... > +void vuart_dump_state(const struct domain *d) > +{ > + const struct vuart_ops *vdev; > + > + for_each_vuart(vdev) > + vdev->dump_state(d); > +} ... state dumping pretty surely wants to be optional? > +/* > + * Put character to the first suitable emulated UART's FIFO. > + */ What's "suitable"? Along the lines of the earlier remark, what if the domain has vUART kind A configured, ... > +int vuart_put_rx(struct domain *d, char c) > +{ > + const struct vuart_ops *vdev = NULL; > + > + ASSERT(domain_has_vuart(d)); > + > + for_each_vuart(vdev) > + if ( vdev->put_rx ) ... but only kind B offers this hook? > + break; > + > + return vdev ? vdev->put_rx(d, c) : -ENODEV; The check for NULL helps for the "no vUART drivers" case, but it won't help if you exhausted the array without finding a driver with the wanted hook. > +} > + > +bool domain_has_vuart(const struct domain *d) > +{ > + uint32_t mask = 0; unsigned int? > --- a/xen/common/keyhandler.c > +++ b/xen/common/keyhandler.c > @@ -22,6 +22,7 @@ > #include > #include > #include > +#include > #include > > static unsigned char keypress_key; > @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char key) > v->periodic_period / 1000000); > } > } > + > + vuart_dump_state(d); How verbose is this going to get? > --- /dev/null > +++ b/xen/include/xen/vuart.h > @@ -0,0 +1,84 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * UART emulator framework. > + * > + * Copyright 2025 Ford Motor Company > + */ > + > +#ifndef XEN_VUART_H > +#define XEN_VUART_H > + > +#include > +#include > +#include The order is wrong - types must be available before public headers are included. > +struct vuart_params { > + domid_t console_domid; > + gfn_t gfn; > + evtchn_port_t evtchn; > +}; > + > +struct vuart_ops { > + int (*add_node)(struct domain *d, const void *node); > + int (*init)(struct domain *d, struct vuart_params *params); > + void (*deinit)(struct domain *d); > + void (*dump_state)(const struct domain *d); > + int (*put_rx)(struct domain *d, char c); > +}; > + > +#define VUART_REGISTER(name, x) \ > + static const struct vuart_ops *const __name##_entry \ > + __used_section(".data.vuart." #name) = (x); > + > +#ifdef CONFIG_HAS_VUART > + > +int vuart_add_node(struct domain *d, const void *node); > +int vuart_init(struct domain *d, struct vuart_params *params); > +void vuart_deinit(struct domain *d); > +void vuart_dump_state(const struct domain *d); > +int vuart_put_rx(struct domain *d, char c); > +bool domain_has_vuart(const struct domain *d); > + > +#else > + > +static inline int vuart_add_node(struct domain *d, const void *node) > +{ > + return 0; > +} > + > +static inline int vuart_init(struct domain *d, struct vuart_params *params) > +{ > + return 0; > +} > + > +static inline void vuart_deinit(struct domain *d) > +{ > +} > + > +static inline void vuart_dump_state(const struct domain *d) > +{ > +} > + > +static inline int vuart_put_rx(struct domain *d, char c) > +{ > + ASSERT_UNREACHABLE(); > + return -ENODEV; > +} > + > +static inline bool domain_has_vuart(const struct domain *d) > +{ > + return false; > +} With this, some of the other stubs should not be necessary. Declarations will suffice, e.g. for vuart_put_rx(). > --- a/xen/include/xen/xen.lds.h > +++ b/xen/include/xen/xen.lds.h > @@ -194,4 +194,14 @@ > #define VPCI_ARRAY > #endif > > +#ifdef CONFIG_HAS_VUART > +#define VUART_ARRAY \ > + . = ALIGN(POINTER_ALIGN); \ > + __start_vuart_array = .; \ > + *(SORT(.data.vuart.*)) \ This is r/o data afaict, so would want naming .rodata.vuart.*. Which in turn means the uses of the macros need to move up in the linker scripts. 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Mon, 04 Aug 2025 03:20:10 -0700 (PDT) Message-ID: <032daad1-29a0-48ca-9f50-5234d42a3ea1@suse.com> Date: Mon, 4 Aug 2025 12:20:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/8] x86/domain: allocate d->{iomem,irq}_caps before arch-specific initialization To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-4-dmukhin@ford.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250731192130.3948419-4-dmukhin@ford.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 21:21, dmkhn@proton.me wrote: > From: Denis Mukhin > > Move IRQ/IOMEM rangesets allocation before arch_domain_create(). > > That guarantees that arch-specific code could access those rangesets to > register traps for emulation. > > It is necessary for those emulators registering trap handlers and ensuring > that emulated IRQs are not shared with the physical IRQs. > > Move dom0_setup_permissions() call right after I/O rangesets are allocated. > > Move pvh_setup_mmcfg() inside dom0_setup_permissions() close to the place > where MMCFG ranges are initialized. And this is just because you like doing so? I ask because first and foremost I can't make the connection between this and the purpose of this patch. > --- a/xen/arch/x86/dom0_build.c > +++ b/xen/arch/x86/dom0_build.c > @@ -471,6 +471,24 @@ static void __init process_dom0_ioports_disable(struct domain *dom0) > } > } > > +static void __hwdom_init setup_mmcfg(struct domain *d) Why __hwdom_init when ... > @@ -480,6 +498,14 @@ int __init dom0_setup_permissions(struct domain *d) > if ( pv_shim ) > return 0; > > + /* > + * MMCFG initialization must be performed before setting domain > + * permissions, as the MCFG areas must not be part of the domain IOMEM > + * accessible regions. > + */ > + if ( is_hvm_domain(d) ) > + setup_mmcfg(d); ... the sole caller is __init? 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Mon, 04 Aug 2025 03:23:33 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 12:23:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/8] xen/8250-uart: update definitions To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-5-dmukhin@ford.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250731192130.3948419-5-dmukhin@ford.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 21:22, dmkhn@proton.me wrote: > From: Denis Mukhin > > Added missing definitions needed for NS16550 UART emulator. > > Newly introduced MSR definitions re-used in the existing ns16550 driver. > > Also, corrected FCR DMA definition bit#3 (0x08) as per: > https://www.ti.com/lit/ds/symlink/tl16c550c.pdf > See "7.7.2 FIFO Control Register (FCR)". > > Signed-off-by: Denis Mukhin > --- > Changes since v3: > - feedback addressed > - made use of new UART_MCR_XXX bits in ns16550 driver > - Link to v3: https://lore.kernel.org/xen-devel/20250103-vuart-ns8250-v3-v1-19-c5d36b31d66c@ford.com/ > --- > xen/drivers/char/ns16550.c | 6 ++--- > xen/include/xen/8250-uart.h | 50 ++++++++++++++++++++++++++++++------- > 2 files changed, 44 insertions(+), 12 deletions(-) > > diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c > index df7fff7f81df..a899711e2a8b 100644 > --- a/xen/drivers/char/ns16550.c > +++ b/xen/drivers/char/ns16550.c > @@ -739,9 +739,9 @@ static int __init check_existence(struct ns16550 *uart) > * Check to see if a UART is really there. > * Use loopback test mode. > */ > - ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | 0x0A); > - status = ns_read_reg(uart, UART_MSR) & 0xF0; > - return (status == 0x90); > + ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | UART_MCR_RTS | UART_MCR_OUT2); > + status = ns_read_reg(uart, UART_MSR) & UART_MSR_STATUS; > + return (status == (UART_MSR_CTS | UART_MSR_DCD)); > } > > #ifdef CONFIG_HAS_PCI > diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h > index d13352940c13..bc11cdc376c9 100644 > --- a/xen/include/xen/8250-uart.h > +++ b/xen/include/xen/8250-uart.h > @@ -32,6 +32,7 @@ > #define UART_MCR 0x04 /* Modem control */ > #define UART_LSR 0x05 /* line status */ > #define UART_MSR 0x06 /* Modem status */ > +#define UART_SCR 0x07 /* Scratch pad */ > #define UART_USR 0x1f /* Status register (DW) */ > #define UART_DLL 0x00 /* divisor latch (ls) (DLAB=1) */ > #define UART_DLM 0x01 /* divisor latch (ms) (DLAB=1) */ > @@ -42,6 +43,8 @@ > #define UART_IER_ETHREI 0x02 /* tx reg. empty */ > #define UART_IER_ELSI 0x04 /* rx line status */ > #define UART_IER_EMSI 0x08 /* MODEM status */ > +#define UART_IER_MASK \ > + (UART_IER_ERDAI | UART_IER_ETHREI | UART_IER_ELSI | UART_IER_EMSI) At the example of this: It having no users here, how are we to know it'll gain some (and hence be useful)? Adding missing base definitions is imo fine without immediate users, but for derived ones it's less clear. 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Sure, I wasn't aware of this functionality. Thanks, Roger. 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Mon, 04 Aug 2025 03:53:35 -0700 (PDT) Message-ID: <5c0589a2-91fe-484d-bded-5a68a1626355@suse.com> Date: Mon, 4 Aug 2025 12:53:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/8] emul/vuart-ns16550: introduce NS16550-compatible UART emulator (x86) To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-6-dmukhin@ford.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250731192130.3948419-6-dmukhin@ford.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 21:22, dmkhn@proton.me wrote: > From: Denis Mukhin > > Add initial in-hypervisor emulator for NS8250/NS16x50-compatible UARTs under > CONFIG_VUART_NS16550 for x86 port of Xen. > > x86 port of Xen lacks vUART facility similar to Arm's SBSA emulator to support > x86 guest OS bring up in the embedded setups. > > In parallel domain creation scenario (hyperlaunch), NS16550 emulator helps > early guest firmware and/or OS bringup debugging, because it eliminates > dependency on the external emulator (qemu) being operational by the time > domains are created. > > The emulator also allows to forward the physical console input to the x86 > domain which is useful when a system has only one physical UART for early > debugging and this UART is owned by Xen. Such functionality is limited to dom0 > use currently. > > By default, CONFIG_VUART_NS16550 enables emulation of NS16550 at I/O port > 0x3f8, IRQ#4 in guest OS (legacy COM1). > > Legacy COM resources can be selected at built-time and cannot be configured > per-domain via .cfg or DT yet. > > Introduce new emulation flag for virtual UART on x86 and plumb it through > domain creation code so NS16550 emulator can be instantiated properly. > > Please refer to the NS16550 emulator code for full list of limitations. > > Signed-off-by: Denis Mukhin > --- > Changes since v3: > - feedback addressed > - adjusted to new vUART framework APIs > - Link to v3: https://lore.kernel.org/xen-devel/20250103-vuart-ns8250-v3-v1-21-c5d36b31d66c@ford.com/ > --- > xen/arch/x86/hvm/hvm.c | 9 + > xen/arch/x86/include/asm/domain.h | 4 +- > xen/arch/x86/include/asm/hvm/domain.h | 4 + > xen/common/emul/vuart/Kconfig | 48 ++ > xen/common/emul/vuart/Makefile | 1 + > xen/common/emul/vuart/vuart-ns16550.c | 1009 +++++++++++++++++++++++++ > xen/common/emul/vuart/vuart.c | 4 + > xen/include/public/arch-x86/xen.h | 4 +- > xen/include/xen/resource.h | 3 + > 9 files changed, 1084 insertions(+), 2 deletions(-) > create mode 100644 xen/common/emul/vuart/vuart-ns16550.c Overall I think this patch is too large to sensibly review. Surely base structure and then (incrementally) fleshing out of the hooks can be separated from one another? > --- a/xen/arch/x86/hvm/hvm.c > +++ b/xen/arch/x86/hvm/hvm.c > @@ -31,6 +31,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -702,6 +703,10 @@ int hvm_domain_initialise(struct domain *d, > if ( rc != 0 ) > goto fail1; > > + rc = vuart_init(d, NULL); > + if ( rc != 0 ) > + goto out_vioapic_deinit; > + > stdvga_init(d); > > rtc_init(d); > @@ -725,6 +730,8 @@ int hvm_domain_initialise(struct domain *d, > return 0; > > fail2: > + vuart_deinit(d); > + out_vioapic_deinit: > vioapic_deinit(d); > fail1: > if ( is_hardware_domain(d) ) Would be better if vuart_deinit() was idempotent, and hence could be called unconditionally here. > @@ -787,6 +794,8 @@ void hvm_domain_destroy(struct domain *d) > if ( hvm_funcs.domain_destroy ) > alternative_vcall(hvm_funcs.domain_destroy, d); > > + vuart_deinit(d); You require a fair level of idempotency already anyway, as a domain may not have any vUART, so this call already needs to be "capabale" of doing nothing. > --- a/xen/arch/x86/include/asm/hvm/domain.h > +++ b/xen/arch/x86/include/asm/hvm/domain.h > @@ -149,6 +149,10 @@ struct hvm_domain { > #ifdef CONFIG_MEM_SHARING > struct mem_sharing_domain mem_sharing; > #endif > + > +#ifdef CONFIG_VUART_NS16550 > + void *vuart; /* Virtual UART handle. */ > +#endif > }; With your framework you allow for multiple vUART drivers. Either the field looks misnamed or the CONFIG_* option checked is the wrong one. Also, why's this x86-specific? NS16550s can exist anywhere, can't they? (The present, but presumably temporary tying to x86 looks to be the use of I/O ports.) > --- a/xen/common/emul/vuart/Kconfig > +++ b/xen/common/emul/vuart/Kconfig > @@ -3,4 +3,52 @@ config HAS_VUART > > menu "UART Emulation" > > +config VUART_NS16550 > + bool "NS16550-compatible UART Emulation" if EXPERT > + depends on X86 && HVM > + select HAS_VUART > + help > + In-hypervisor NS16550/NS16x50 UART emulation. > + > + Only legacy PC I/O ports are emulated. > + > + This is strictly for testing purposes (such as early HVM guest console), > + and not appropriate for use in production. > + > +choice VUART_NS16550_PC > + prompt "IBM PC COM resources" > + depends on VUART_NS16550 > + default VUART_NS16550_PC_COM1 > + help > + Default emulated NS16550 resources. > + > +config VUART_NS16550_PC_COM1 > + bool "COM1 (I/O port 0x3f8, IRQ#4)" > + > +config VUART_NS16550_PC_COM2 > + bool "COM2 (I/O port 0x2f8, IRQ#3)" > + > +config VUART_NS16550_PC_COM3 > + bool "COM3 (I/O port 0x3e8, IRQ#4)" > + > +config VUART_NS16550_PC_COM4 > + bool "COM4 (I/O port 0x2e8, IRQ#3)" > + > +endchoice > + > +config VUART_NS16550_LOG_LEVEL > + int "UART emulator verbosity level" > + range 0 3 > + default "1" > + depends on VUART_NS16550 > + help > + Set the default log level of UART emulator. > + See include/xen/config.h for more details. For someone merely running kconfig but not otherwise knowing the sources, this isn't an overly helful pointer. But I question the need for such a control anyway, and I think I did say so already before. > +config VUART_NS16550_DEBUG > + bool "UART emulator development debugging" > + depends on VUART_NS16550 && DEBUG ? > --- a/xen/common/emul/vuart/Makefile > +++ b/xen/common/emul/vuart/Makefile > @@ -1 +1,2 @@ > obj-$(CONFIG_HAS_VUART) += vuart.o > +obj-$(CONFIG_VUART_NS16550) += vuart-ns16550.o I don't think files in this directory need a vuart- name prefix. > --- /dev/null > +++ b/xen/common/emul/vuart/vuart-ns16550.c > @@ -0,0 +1,1009 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * NS16550-compatible UART Emulator. > + * > + * See: > + * - Serial and UART Tutorial: > + * https://download.freebsd.org/doc/en/articles/serial-uart/serial-uart_en.pdf > + * - UART w/ 16 byte FIFO: > + * https://www.ti.com/lit/ds/symlink/tl16c550c.pdf > + * - UART w/ 64 byte FIFO: > + * https://www.ti.com/lit/ds/symlink/tl16c750.pdf > + * > + * Limitations: > + * - Only x86; > + * - Only HVM domains support (build-time), PVH domains are not supported yet; > + * - Only legacy COM{1,2,3,4} resources via Kconfig, custom I/O ports/IRQs > + * are not supported; > + * - Only Xen console as a backend, no inter-domain communication (similar to > + * vpl011 on Arm); > + * - Only 8n1 emulation (8-bit data, no parity, 1 stop bit); > + * - No toolstack integration; > + * - No baud rate emulation (reports 115200 baud to the guest OS); > + * - No FIFO-less mode emulation; > + * - No RX FIFO interrupt moderation (FCR) emulation; > + * - No integration w/ VM snapshotting (HVM_REGISTER_SAVE_RESTORE() and > + * friends); > + * - No ISA IRQ sharing allowed; > + * - No MMIO-based UART emulation. > + */ > + > +#define pr_prefix "ns16550" > +#define pr_fmt(fmt) pr_prefix ": " fmt > +#define pr_log_level CONFIG_VUART_NS16550_LOG_LEVEL > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include Except for cases where Xen itself runs as a guest, I don't think any of these headers should be used in Xen sources. If I'm not mistaken, ... > +/* > + * Virtual NS16550 device state. > + */ > +struct vuart_ns16550 { > + struct xencons_interface cons; /* Emulated RX/TX FIFOs */ ... this also isn't to communicate with some remote, but merely to use some of the fields conveniently. > + uint8_t regs[NS16550_EMU_REGS_NUM]; /* Emulated registers */ > + unsigned int irq; /* Emulated IRQ# */ > + uint64_t io_addr; /* Emulated I/O region base address */ > + uint64_t io_size; /* Emulated I/O region size */ These are huge; for the size that's true even if considering future MMIO- based emulation. > + const char *name; /* Device name */ > + struct domain *owner; /* Owner domain */ > + spinlock_t lock; /* Protection */ > +}; > + > +/* > + * Virtual device description. > + */ > +struct virtdev_desc { > + const char *name; > + const struct resource *res; > +}; > + > +/* > + * Legacy IBM PC NS16550 resources. > + * There are only 4 I/O port ranges, hardcoding all of them here. > + */ > +static const struct virtdev_desc x86_pc_uarts[4] = { > + [0] = { > + .name = "COM1", > + .res = (const struct resource[]){ > + { .type = IORESOURCE_IO, .addr = 0x3f8, .size = NS16550_REGS_NUM }, > + { .type = IORESOURCE_IRQ, .addr = 4, .size = 1 }, > + { .type = IORESOURCE_UNKNOWN }, > + }, > + }, > + [1] = { > + .name = "COM2", > + .res = (const struct resource[]){ > + { .type = IORESOURCE_IO, .addr = 0x2f8, .size = NS16550_REGS_NUM }, > + { .type = IORESOURCE_IRQ, .addr = 3, .size = 1 }, > + { .type = IORESOURCE_UNKNOWN }, > + }, > + }, > + [2] = { > + .name = "COM3", > + .res = (const struct resource[]){ > + { .type = IORESOURCE_IO, .addr = 0x3e8, .size = NS16550_REGS_NUM }, > + { .type = IORESOURCE_IRQ, .addr = 4, .size = 1 }, > + { .type = IORESOURCE_UNKNOWN }, > + }, > + }, > + [3] = { > + .name = "COM4", > + .res = (const struct resource[]){ > + { .type = IORESOURCE_IO, .addr = 0x2e8, .size = NS16550_REGS_NUM }, > + { .type = IORESOURCE_IRQ, .addr = 3, .size = 1 }, > + { .type = IORESOURCE_UNKNOWN }, > + }, > + }, > +}; The choice of COMn is at build time. Why do we need all four configurations resident not only in the binary, but even at (post-init) runtime? Also, the way you do initialization of .res, I think adding __initconst to the main array wouldn't have the effect of pulling all those inti .init.* as well. For the time being I simply don't see the need for the extra level of indirection: All instances have two entries (plus the then likely not necessary sentinel). > +static bool cf_check ns16550_iir_check_lsi(const struct vuart_ns16550 *vdev) > +{ > + return !!(vdev->regs[UART_LSR] & UART_LSR_MASK); No need for !! (also elsewhere). > --- a/xen/include/xen/resource.h > +++ b/xen/include/xen/resource.h > @@ -31,4 +31,7 @@ struct resource { > > #define resource_size(res) ((res)->size) > > +#define for_each_resource(res) \ > + for ( ; (res) && (res)->type != IORESOURCE_UNKNOWN; (res)++ ) I'm not sure this is a good generic #define; imo it wants keeping local to the one file that uses it. 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Mon, 04 Aug 2025 03:54:25 -0700 (PDT) Message-ID: <9564486c-19ff-427b-9d65-13ee4c8e429b@suse.com> Date: Mon, 4 Aug 2025 12:54:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 6/8] tools/xl: enable NS16550-compatible UART emulator for HVM (x86) To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-7-dmukhin@ford.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250731192130.3948419-7-dmukhin@ford.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 21:22, dmkhn@proton.me wrote: > --- a/xen/arch/x86/domain.c > +++ b/xen/arch/x86/domain.c > @@ -780,9 +780,10 @@ static bool emulation_flags_ok(const struct domain *d, uint32_t emflags) > /* HVM domU */ > { > .caps = CAP_HVM | CAP_DOMU, > - .min = X86_EMU_ALL & ~(X86_EMU_VPCI | X86_EMU_USE_PIRQ), > + .min = X86_EMU_ALL & ~(X86_EMU_VPCI | X86_EMU_USE_PIRQ | > + X86_EMU_NS16550), > /* HVM PIRQ feature is user-selectable. */ > - .opt = X86_EMU_USE_PIRQ, > + .opt = X86_EMU_USE_PIRQ | X86_EMU_NS16550, Rendering the comment partly stale. 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Mon, 04 Aug 2025 04:00:52 -0700 (PDT) Message-ID: <0f4abbb4-aa7f-4c09-8652-bc9041a25a56@citrix.com> Date: Mon, 4 Aug 2025 12:00:51 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen/x86: fix xen.efi boot crash from some bootloaders To: Jan Beulich , Yann Sionneau Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , xen-devel@lists.xenproject.org References: <20250724140731.1502774-1-yann.sionneau@vates.tech> <4ceb64fa-d7cb-4c77-8a60-1526046c037c@suse.com> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: <4ceb64fa-d7cb-4c77-8a60-1526046c037c@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 04/08/2025 10:34 am, Jan Beulich wrote: > On 24.07.2025 16:07, Yann Sionneau wrote: >> xen.efi PE does not boot when loaded from shim or some patched >> downstream grub2. >> >> What happens is the bootloader would honour the MEM_DISCARDABLE >> flag of the .reloc section meaning it would not load its content >> into memory. >> >> But Xen is parsing the .reloc section content twice at boot: >> * https://elixir.bootlin.com/xen/v4.20.1/source/xen/common/efi/boot.c#L1362 >> * https://elixir.bootlin.com/xen/v4.20.1/source/xen/arch/x86/efi/efi-boot.h#L237 >> >> Therefore it would crash with the following message: >> "Unsupported relocation type" as reported there: >> >> * https://github.com/QubesOS/qubes-issues/issues/8206#issuecomment-2619048838 >> * https://lore.kernel.org/xen-devel/7e039262-1f54-46e1-8f70-ac3f03607d5a@suse.com/T/#me122b9e6c27cd98db917da2c9f67e74a2c6ad7a5 >> >> This commit adds a small C host tool named keeprelocs >> that is called after xen.efi is produced by the build system >> in order to remove this bit from its .reloc section header. >> >> Signed-off-by: Yann Sionneau > So I found a way to deal with this at the linker side, without any new command > line options. Behavior is solely driven by the attributes of any incoming .reloc > sections (of which there would be none by default, retaining original behavior). > The important patch is [1], but at least the first patch of the series [2] would > in most cases also be wanted/needed (patch 04 is obviously a mechanical prereq > for the main patch). Need for other of the prereqs there depends on the scope > and purpose of one's binutils build(s). > > Jan > > [1] https://sourceware.org/pipermail/binutils/2025-August/143153.html > [2] https://sourceware.org/pipermail/binutils/2025-August/143141.html That's good to see.  Do we need any matching changes in Xen? ~Andrew From xen-devel-bounces@lists.xenproject.org Mon Aug 04 11:06:40 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 11:06:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069099.1432936 (Exim 4.92) (envelope-from ) id 1uit1X-0000bD-Gq; Mon, 04 Aug 2025 11:06:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069099.1432936; Mon, 04 Aug 2025 11:06:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uit1X-0000b6-E4; Mon, 04 Aug 2025 11:06:35 +0000 Received: by outflank-mailman (input) for mailman id 1069099; Mon, 04 Aug 2025 11:06:33 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uit1V-0000b0-OP for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 11:06:33 +0000 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [2a00:1450:4864:20::532]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 13860420-7123-11f0-b898-0df219b8e170; Mon, 04 Aug 2025 13:06:31 +0200 (CEST) Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-60bfcada295so5133936a12.1 for ; Mon, 04 Aug 2025 04:06:31 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Mon, 04 Aug 2025 04:06:30 -0700 (PDT) Message-ID: <549bde88-38a3-4920-9309-f898b48d3bda@suse.com> Date: Mon, 4 Aug 2025 13:06:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 7/8] tools/xl: enable NS16550-compatible UART emulator for PVH (x86) To: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-8-dmukhin@ford.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250731192130.3948419-8-dmukhin@ford.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 21:22, dmkhn@proton.me wrote: > From: Denis Mukhin > > Enable virtual NS16550 for PVH domains in xl. > > {map,unmap}_domain_emuirq_pirq() infrastructure is modified by adding new > type of interrupt resources 'IRQ_EMU' which means 'emulated device IRQ' > (similarly to IRQ_MSI_EMU). > > This is necessary to for IOAPIC emulation code to skip IRQ->PIRQ mapping > (vioapic_hwdom_map_gsi()) when guest OS unmasks vIOAPIC pin corresponding to > virtual device's IRQ. > > Also, hvm_gsi_eoi() is modified to trigger assertion in hvm_gsi_deassert() > path for ISA IRQs. > > Signed-off-by: Denis Mukhin > --- > Changes since v3: > - new patch > --- > tools/libs/light/libxl_x86.c | 2 +- > xen/arch/x86/domain.c | 2 ++ > xen/arch/x86/hvm/vioapic.c | 10 ++++++++++ > xen/arch/x86/include/asm/irq.h | 1 + > xen/common/emul/vuart/vuart-ns16550.c | 27 +++++++++++++++++++++++++-- > xen/drivers/passthrough/x86/hvm.c | 9 ++++----- > 6 files changed, 43 insertions(+), 8 deletions(-) Given this diffstat, how come the patch prefix is "tools/xl:"? You don't even touch xl ... > --- a/xen/common/emul/vuart/vuart-ns16550.c > +++ b/xen/common/emul/vuart/vuart-ns16550.c > @@ -355,7 +355,9 @@ static void ns16550_irq_assert(const struct vuart_ns16550 *vdev) > struct domain *d = vdev->owner; > int vector; > > - if ( has_vpic(d) ) /* HVM */ > + if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */ > + vector = hvm_ioapic_assert(d, vdev->irq, false); > + else if ( has_vpic(d) ) /* HVM */ > vector = hvm_isa_irq_assert(d, vdev->irq, vioapic_get_vector); Why not if ( has_vpic(d) ) /* HVM */ vector = hvm_isa_irq_assert(d, vdev->irq, vioapic_get_vector); else if ( has_vioapic(d) ) /* PVH */ vector = hvm_ioapic_assert(d, vdev->irq, false); Less code churn and maybe even less generated code. > @@ -367,7 +369,9 @@ static void ns16550_irq_deassert(const struct vuart_ns16550 *vdev) > { > struct domain *d = vdev->owner; > > - if ( has_vpic(d) ) /* HVM */ > + if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */ > + hvm_ioapic_deassert(d, vdev->irq); > + else if ( has_vpic(d) ) /* HVM */ > hvm_isa_irq_deassert(d, vdev->irq); Same here then. > --- a/xen/drivers/passthrough/x86/hvm.c > +++ b/xen/drivers/passthrough/x86/hvm.c > @@ -924,12 +924,11 @@ static void hvm_gsi_eoi(struct domain *d, unsigned int gsi) > { > struct pirq *pirq = pirq_info(d, gsi); > > - /* Check if GSI is actually mapped. */ > - if ( !pirq_dpci(pirq) ) > - return; > - > hvm_gsi_deassert(d, gsi); > - hvm_pirq_eoi(pirq); > + > + /* Check if GSI is actually mapped. */ > + if ( pirq_dpci(pirq) ) > + hvm_pirq_eoi(pirq); > } The correctness of this change (in particular hvm_gsi_deassert() now always running) wants reasoning about in the description. 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Mon, 04 Aug 2025 04:23:23 -0700 (PDT) Message-ID: <1e83ed1c-6fa6-4295-9072-d4277f95f2a1@suse.com> Date: Mon, 4 Aug 2025 13:23:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen/x86: fix xen.efi boot crash from some bootloaders To: Andrew Cooper Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , xen-devel@lists.xenproject.org, Yann Sionneau References: <20250724140731.1502774-1-yann.sionneau@vates.tech> <4ceb64fa-d7cb-4c77-8a60-1526046c037c@suse.com> <0f4abbb4-aa7f-4c09-8652-bc9041a25a56@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <0f4abbb4-aa7f-4c09-8652-bc9041a25a56@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 04.08.2025 13:00, Andrew Cooper wrote: > On 04/08/2025 10:34 am, Jan Beulich wrote: >> On 24.07.2025 16:07, Yann Sionneau wrote: >>> xen.efi PE does not boot when loaded from shim or some patched >>> downstream grub2. >>> >>> What happens is the bootloader would honour the MEM_DISCARDABLE >>> flag of the .reloc section meaning it would not load its content >>> into memory. >>> >>> But Xen is parsing the .reloc section content twice at boot: >>> * https://elixir.bootlin.com/xen/v4.20.1/source/xen/common/efi/boot.c#L1362 >>> * https://elixir.bootlin.com/xen/v4.20.1/source/xen/arch/x86/efi/efi-boot.h#L237 >>> >>> Therefore it would crash with the following message: >>> "Unsupported relocation type" as reported there: >>> >>> * https://github.com/QubesOS/qubes-issues/issues/8206#issuecomment-2619048838 >>> * https://lore.kernel.org/xen-devel/7e039262-1f54-46e1-8f70-ac3f03607d5a@suse.com/T/#me122b9e6c27cd98db917da2c9f67e74a2c6ad7a5 >>> >>> This commit adds a small C host tool named keeprelocs >>> that is called after xen.efi is produced by the build system >>> in order to remove this bit from its .reloc section header. >>> >>> Signed-off-by: Yann Sionneau >> So I found a way to deal with this at the linker side, without any new command >> line options. Behavior is solely driven by the attributes of any incoming .reloc >> sections (of which there would be none by default, retaining original behavior). >> The important patch is [1], but at least the first patch of the series [2] would >> in most cases also be wanted/needed (patch 04 is obviously a mechanical prereq >> for the main patch). Need for other of the prereqs there depends on the scope >> and purpose of one's binutils build(s). >> >> [1] https://sourceware.org/pipermail/binutils/2025-August/143153.html >> [2] https://sourceware.org/pipermail/binutils/2025-August/143141.html > > That's good to see.  Do we need any matching changes in Xen? Well, we'll need some (zero-size) contribution to .reloc then. For my testing I hacked this into the linking rule (which is a mess already anyway), but I hope / expect to find a cleaner solution for upstreaming. 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That's because cleared_caps[] are only applied after the ->c_init() hooks ran, i.e. cpu_has() still returns true in init_amd(). Fixes: 93401e28a84b ("x86: clear RDRAND CPUID bit on AMD family 15h/16h") Signed-off-by: Jan Beulich --- TBD: It's not clear whether doing it this way is actually a good idea; it may need to be two of the three call sites to be amended by a new is_cleared_cpu_cap(). Also relevant to "x86/AMD: disable RDSEED on Fam17 model 47 stepping 0". --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -108,7 +108,7 @@ void __init setup_force_cpu_cap(unsigned bool __init is_forced_cpu_cap(unsigned int cap) { - return test_bit(cap, forced_caps); + return test_bit(cap, forced_caps) || test_bit(cap, cleared_caps); } static void cf_check default_init(struct cpuinfo_x86 * c) From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:20:23 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:20:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069140.1432967 (Exim 4.92) (envelope-from ) id 1uiuAk-0003A3-97; Mon, 04 Aug 2025 12:20:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069140.1432967; Mon, 04 Aug 2025 12:20:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuAk-00039w-5D; Mon, 04 Aug 2025 12:20:10 +0000 Received: by outflank-mailman (input) for mailman id 1069140; Mon, 04 Aug 2025 12:20:09 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuAj-00039q-4T for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:20:09 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 5bc47152-712d-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 14:20:07 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-af949bdf36cso330991766b.0 for ; Mon, 04 Aug 2025 05:20:07 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Mon, 04 Aug 2025 05:20:06 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 14:20:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 02/25] xen/x86: consolidate vram tracking support To: Penny Zheng Cc: ray.huang@amd.com, Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org References: <20250803094738.3625269-1-Penny.Zheng@amd.com> <20250803094738.3625269-3-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250803094738.3625269-3-Penny.Zheng@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 03.08.2025 11:47, Penny Zheng wrote: > Flag PG_log_dirty is for paging log dirty support, not vram tracking support. > However data structure sh_dirty_vram{} and function paging_log_dirty_range() > designed for vram tracking support, are guarded with PG_log_dirty. The struct decl is guarded by both, which is fine, merely a bit redundant. I'm okay with moving it if that helps elsewhere. > We release both from PG_log_dirty, and also move paging_log_dirty_range() into > hap.c, to make it static. This, I think, wants doing separately. paging.c isn't quite a correct home for it, yes, but neither is hap/hap.c. This is noticeable first and foremost from ... > --- a/xen/arch/x86/mm/hap/hap.c > +++ b/xen/arch/x86/mm/hap/hap.c > @@ -36,6 +36,38 @@ > /* HAP VRAM TRACKING SUPPORT */ > /************************************************/ > > +#ifdef CONFIG_HVM > +static void paging_log_dirty_range(struct domain *d, > + unsigned long begin_pfn, > + unsigned long nr, > + uint8_t *dirty_bitmap) > +{ > + struct p2m_domain *p2m = p2m_get_hostp2m(d); > + int i; > + unsigned long pfn; > + > + /* > + * Set l1e entries of P2M table to be read-only. > + * > + * On first write, it page faults, its entry is changed to read-write, > + * and on retry the write succeeds. > + * > + * We populate dirty_bitmap by looking for entries that have been > + * switched to read-write. > + */ > + > + p2m_lock(p2m); ... the lock it uses. This function really wants to move to p2m.c imo, and be suitably renamed (s/paging_/p2m_/). While there please also consider switching i to unsigned int. > + for ( i = 0, pfn = begin_pfn; pfn < begin_pfn + nr; i++, pfn++ ) > + if ( !p2m_change_type_one(d, pfn, p2m_ram_rw, p2m_ram_logdirty) ) > + dirty_bitmap[i >> 3] |= (1 << (i & 7)); > + > + p2m_unlock(p2m); > + > + guest_flush_tlb_mask(d, d->dirty_cpumask); > +} > +#endif /* CONFIG_HVM */ This #ifdef / #endif isn't needed. Neither when it lives in hap/hap.c (the parent dir's Makefile has obj-$(CONFIG_HVM) += hap/ ) nor when in p2m.c. The function then still not being non-static is acceptable; it living where it logically belongs is more important imo. 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Smith" , xen-devel@lists.xenproject.org References: <20250803094738.3625269-1-Penny.Zheng@amd.com> <20250803094738.3625269-4-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250803094738.3625269-4-Penny.Zheng@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 03.08.2025 11:47, Penny Zheng wrote: > We have PG_log_dirty flag to wrap codes about paging log-dirty support. > The main entry is paging_domctl(), Yet paging_domctl() serves other paging modes, too. In fact for the shim PG_SH_forced is actually a mode that could plausibly come into use (even if not by way of a toolstack requesting it). It was previously indicated that it was wrong for SHADOW_PAGING to be forced off in shim-exclusive mode. No patch ever surfaced, but that may want sorting before any new boundaries are to be drawn. In fact, ... > --- a/xen/arch/x86/include/asm/paging.h > +++ b/xen/arch/x86/include/asm/paging.h > @@ -55,7 +55,7 @@ > #define PG_translate 0 > #define PG_external 0 > #endif > -#if defined(CONFIG_HVM) || !defined(CONFIG_PV_SHIM_EXCLUSIVE) > +#if defined(CONFIG_HVM) > /* Enable log dirty mode */ > #define PG_log_dirty (XEN_DOMCTL_SHADOW_ENABLE_LOG_DIRTY << PG_mode_shift) ... the conditional here likely wants to become #if defined(CONFIG_HVM) || defined(CONFIG_SHADOW_PAGING) instead. This might actually be a far more isolated change then, still moving you in the direction that you want (I think). > --- a/xen/arch/x86/mm/hap/hap.c > +++ b/xen/arch/x86/mm/hap/hap.c > @@ -189,6 +189,7 @@ out: > return rc; > } > > +#if PG_log_dirty > /************************************************/ > /* HAP LOG DIRTY SUPPORT */ > /************************************************/ > @@ -254,6 +255,7 @@ static void cf_check hap_clean_dirty_bitmap(struct domain *d) > p2m_change_entry_type_global(d, p2m_ram_rw, p2m_ram_logdirty); > guest_flush_tlb_mask(d, d->dirty_cpumask); > } > +#endif /* PG_log_dirty */ Please also don't go overboard with #ifdef-ary: Files built for HVM=y only don't need these, as HVM=y implies non-zero PG_log_dirty. But maybe, with the other change that I outlined, you won't even need all of this anymore. Jan From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:43:26 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:43:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069163.1432995 (Exim 4.92) (envelope-from ) id 1uiuXD-0006iu-CN; Mon, 04 Aug 2025 12:43:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069163.1432995; Mon, 04 Aug 2025 12:43:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXD-0006in-9h; Mon, 04 Aug 2025 12:43:23 +0000 Received: by outflank-mailman (input) for mailman id 1069163; Mon, 04 Aug 2025 12:43:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXB-0006VD-NW for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:43:21 +0000 Received: from sea.source.kernel.org (sea.source.kernel.org [2600:3c0a:e001:78e:0:1991:8:25]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 99425443-7130-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 14:43:20 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 56FE04423C; Mon, 4 Aug 2025 12:43:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B783C4CEF0; Mon, 4 Aug 2025 12:43:17 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 99425443-7130-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311398; bh=rlkoLHmieI8GnOBig0uhL3NMd0vvRWDvv2oEih0mzFM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QrFIfUaOpq0zgYoSf2B1eOFHhzxa8uJ9rI7ao3LQ15JdOAmXwx/vS3c+eYH6QTWOC CZmPIb28BNkyQUhEkXmvY3ou31ivX2Y6W+QyRQ5lEcadqA118EYMjd4CMO32TmndIt q9x/mE/Grc0mkPr/feAp0D8366SSjD6FCJuMLM/iEpxRFuKKQJHqb6OZAv8QT4n2gA l8UYQWJxtJiMLDORYH+k0vFOc3W5LIKBdC/UjGKILIXxW7YyF57t2tVDzjmI4Hs2SY Y6Y7brOxqet5SSMB18NQiaM/FfQfmONk81U59gW5ymq8VCTWf5/3zTUjdvPe68z/B6 YFqU3TERLKLDQ== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 02/16] iommu/dma: handle MMIO path in dma_iova_link Date: Mon, 4 Aug 2025 15:42:36 +0300 Message-ID: <52e39cd31d8f30e54a27afac84ea35f45ae4e422.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Make sure that CPU is not synced if MMIO path is taken. Signed-off-by: Leon Romanovsky --- drivers/iommu/dma-iommu.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index ea2ef53bd4fef..399838c17b705 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -1837,13 +1837,20 @@ static int __dma_iova_link(struct device *dev, dma_addr_t addr, phys_addr_t phys, size_t size, enum dma_data_direction dir, unsigned long attrs) { - bool coherent = dev_is_dma_coherent(dev); + int prot; - if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) - arch_sync_dma_for_device(phys, size, dir); + if (attrs & DMA_ATTR_MMIO) + prot = dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO; + else { + bool coherent = dev_is_dma_coherent(dev); + + if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) + arch_sync_dma_for_device(phys, size, dir); + prot = dma_info_to_prot(dir, coherent, attrs); + } return iommu_map_nosync(iommu_get_dma_domain(dev), addr, phys, size, - dma_info_to_prot(dir, coherent, attrs), GFP_ATOMIC); + prot, GFP_ATOMIC); } static int iommu_dma_iova_bounce_and_link(struct device *dev, dma_addr_t addr, @@ -1949,9 +1956,13 @@ int dma_iova_link(struct device *dev, struct dma_iova_state *state, return -EIO; if (dev_use_swiotlb(dev, size, dir) && - iova_unaligned(iovad, phys, size)) + iova_unaligned(iovad, phys, size)) { + if (attrs & DMA_ATTR_MMIO) + return -EPERM; + return iommu_dma_iova_link_swiotlb(dev, state, phys, offset, size, dir, attrs); + } return __dma_iova_link(dev, state->addr + offset - iova_start_pad, phys - iova_start_pad, -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:43:26 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:43:26 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069162.1432986 (Exim 4.92) (envelope-from ) id 1uiuXC-0006VQ-6h; Mon, 04 Aug 2025 12:43:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069162.1432986; Mon, 04 Aug 2025 12:43:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXC-0006VJ-3A; Mon, 04 Aug 2025 12:43:22 +0000 Received: by outflank-mailman (input) for mailman id 1069162; Mon, 04 Aug 2025 12:43:20 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXA-0006V7-Qe for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:43:20 +0000 Received: from nyc.source.kernel.org (nyc.source.kernel.org [147.75.193.91]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 969ae083-7130-11f0-b898-0df219b8e170; Mon, 04 Aug 2025 14:43:15 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 030FAA55811; Mon, 4 Aug 2025 12:43:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73ED3C4CEE7; Mon, 4 Aug 2025 12:43:12 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 969ae083-7130-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311393; bh=5JNlmVmGVDRpHLFMyx/IqEG6PVqYnGg8cLXnDHx1P9k=; h=From:To:Cc:Subject:Date:From; b=Ea6NngjAGEvyrXvmgnjdDyM3mXPSC8QQfT+nOKbotr6HcSnhW9BlM6zfns9p9k3kL aHN1p5RrLF18qj2RnxxdzX8nS9REiqaWtNTzVJNCM1ShLOSb5FfV99ZaNORp06pQRf K3R1pWS9saoxzj1xXJAIiMxruqRredF2Zi+OmY/oC+bQ4mzzuhWorXTUyup4qpTeuv RrIC3bsvwJsKhiLKd060hGDOvjUq+dNjvySky2bOV6npAhY9wBNf0nitks6Cij982L fFaJuAYxFYDUX0NP4XT5/rJMF9kRy2ZpZIT9BlCY9GVEvgTb44GAyAGaBkqZ5aGmE4 Sus5Is+qyLnxQ== From: Leon Romanovsky To: Marek Szyprowski Cc: Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 00/16] dma-mapping: migrate to physical address-based API Date: Mon, 4 Aug 2025 15:42:34 +0300 Message-ID: X-Mailer: git-send-email 2.50.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Changelog: v1: * Added new DMA_ATTR_MMIO attribute to indicate PCI_P2PDMA_MAP_THRU_HOST_BRIDGE path. * Rewrote dma_map_* functions to use thus new attribute v0: https://lore.kernel.org/all/cover.1750854543.git.leon@kernel.org/ ------------------------------------------------------------------------ This series refactors the DMA mapping to use physical addresses as the primary interface instead of page+offset parameters. This change aligns the DMA API with the underlying hardware reality where DMA operations work with physical addresses, not page structures. The series maintains export symbol backward compatibility by keeping the old page-based API as wrapper functions around the new physical address-based implementations. Thanks Leon Romanovsky (16): dma-mapping: introduce new DMA attribute to indicate MMIO memory iommu/dma: handle MMIO path in dma_iova_link dma-debug: refactor to use physical addresses for page mapping dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory dma-mapping: convert dma_direct_*map_page to be phys_addr_t based kmsan: convert kmsan_handle_dma to use physical addresses dma-mapping: handle MMIO flow in dma_map|unmap_page xen: swiotlb: Open code map_resource callback dma-mapping: export new dma_*map_phys() interface mm/hmm: migrate to physical address-based DMA mapping API mm/hmm: properly take MMIO path block-dma: migrate to dma_map_phys instead of map_page block-dma: properly take MMIO path nvme-pci: unmap MMIO pages with appropriate interface Documentation/core-api/dma-api.rst | 4 +- Documentation/core-api/dma-attributes.rst | 7 ++ arch/powerpc/kernel/dma-iommu.c | 4 +- block/blk-mq-dma.c | 15 ++- drivers/iommu/dma-iommu.c | 69 +++++++------ drivers/nvme/host/pci.c | 18 +++- drivers/virtio/virtio_ring.c | 4 +- drivers/xen/swiotlb-xen.c | 21 +++- include/linux/blk-mq-dma.h | 6 +- include/linux/blk_types.h | 2 + include/linux/dma-direct.h | 2 - include/linux/dma-map-ops.h | 8 +- include/linux/dma-mapping.h | 27 +++++ include/linux/iommu-dma.h | 11 +-- include/linux/kmsan.h | 12 ++- include/trace/events/dma.h | 9 +- kernel/dma/debug.c | 71 ++++--------- kernel/dma/debug.h | 37 ++----- kernel/dma/direct.c | 22 +---- kernel/dma/direct.h | 50 ++++++---- kernel/dma/mapping.c | 115 +++++++++++++--------- kernel/dma/ops_helpers.c | 6 +- mm/hmm.c | 19 ++-- mm/kmsan/hooks.c | 36 +++++-- rust/kernel/dma.rs | 3 + tools/virtio/linux/kmsan.h | 2 +- 26 files changed, 320 insertions(+), 260 deletions(-) -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:43:28 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:43:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069164.1433006 (Exim 4.92) (envelope-from ) id 1uiuXI-0006zd-Ka; Mon, 04 Aug 2025 12:43:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069164.1433006; Mon, 04 Aug 2025 12:43:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXI-0006zW-Gf; Mon, 04 Aug 2025 12:43:28 +0000 Received: by outflank-mailman (input) for mailman id 1069164; Mon, 04 Aug 2025 12:43:26 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXG-0006V7-Rb for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:43:26 +0000 Received: from sea.source.kernel.org (sea.source.kernel.org [172.234.252.31]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9bc209eb-7130-11f0-b898-0df219b8e170; Mon, 04 Aug 2025 14:43:24 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 2379744938; Mon, 4 Aug 2025 12:43:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E414EC4CEE7; Mon, 4 Aug 2025 12:43:21 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9bc209eb-7130-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311403; bh=G8yxKVCRAfrQOyuBUvZbEVDf24fip2a2X5oNwMglhAg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FLzGyKpimqZsvNAMkhEPYN2tkYm9wQ3h3UDHZHmuFev7Kdqx8jKIWoT3U85iOoM1k aCTeOR/y2YoJkjQmGkC8nd0XlPwXp9ABDdnY25JZZV+pjTwrGx1BPI6jkGtfuWH3lH cNTOlfe37YMJ7EbolofEK6cSqjVoJzRKIgDX9Rw/r/pSkJ6tgXx0mQMDPbB50Eo/tY bSHgA0aJulzKtznrvuSvmEPJIYl7Z15YnjALIGKQEd37p0dEVK+inYE3ISZhcfRZD9 duEz6OdVIUPZ2RcrkaozjegB0lDsbcAcuJNUcsrkRMd4xE8ofRwae99SaFKf8HjV7j 9ur3CJw3QLkfA== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 03/16] dma-debug: refactor to use physical addresses for page mapping Date: Mon, 4 Aug 2025 15:42:37 +0300 Message-ID: <9ba84c387ce67389cd80f374408eebb58326c448.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Convert the DMA debug infrastructure from page-based to physical address-based mapping as a preparation to rely on physical address for DMA mapping routines. The refactoring renames debug_dma_map_page() to debug_dma_map_phys() and changes its signature to accept a phys_addr_t parameter instead of struct page and offset. Similarly, debug_dma_unmap_page() becomes debug_dma_unmap_phys(). A new dma_debug_phy type is introduced to distinguish physical address mappings from other debug entry types. All callers throughout the codebase are updated to pass physical addresses directly, eliminating the need for page-to-physical conversion in the debug layer. This refactoring eliminates the need to convert between page pointers and physical addresses in the debug layer, making the code more efficient and consistent with the DMA mapping API's physical address focus. Signed-off-by: Leon Romanovsky --- Documentation/core-api/dma-api.rst | 4 ++-- kernel/dma/debug.c | 28 +++++++++++++++++----------- kernel/dma/debug.h | 16 +++++++--------- kernel/dma/mapping.c | 15 ++++++++------- 4 files changed, 34 insertions(+), 29 deletions(-) diff --git a/Documentation/core-api/dma-api.rst b/Documentation/core-api/dma-api.rst index 3087bea715ed2..ca75b35416792 100644 --- a/Documentation/core-api/dma-api.rst +++ b/Documentation/core-api/dma-api.rst @@ -761,7 +761,7 @@ example warning message may look like this:: [] find_busiest_group+0x207/0x8a0 [] _spin_lock_irqsave+0x1f/0x50 [] check_unmap+0x203/0x490 - [] debug_dma_unmap_page+0x49/0x50 + [] debug_dma_unmap_phys+0x49/0x50 [] nv_tx_done_optimized+0xc6/0x2c0 [] nv_nic_irq_optimized+0x73/0x2b0 [] handle_IRQ_event+0x34/0x70 @@ -855,7 +855,7 @@ that a driver may be leaking mappings. dma-debug interface debug_dma_mapping_error() to debug drivers that fail to check DMA mapping errors on addresses returned by dma_map_single() and dma_map_page() interfaces. This interface clears a flag set by -debug_dma_map_page() to indicate that dma_mapping_error() has been called by +debug_dma_map_phys() to indicate that dma_mapping_error() has been called by the driver. When driver does unmap, debug_dma_unmap() checks the flag and if this flag is still set, prints warning message that includes call trace that leads up to the unmap. This interface can be called from dma_mapping_error() diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c index e43c6de2bce4e..da6734e3a4ce9 100644 --- a/kernel/dma/debug.c +++ b/kernel/dma/debug.c @@ -39,6 +39,7 @@ enum { dma_debug_sg, dma_debug_coherent, dma_debug_resource, + dma_debug_phy, }; enum map_err_types { @@ -141,6 +142,7 @@ static const char *type2name[] = { [dma_debug_sg] = "scatter-gather", [dma_debug_coherent] = "coherent", [dma_debug_resource] = "resource", + [dma_debug_phy] = "phy", }; static const char *dir2name[] = { @@ -1201,9 +1203,8 @@ void debug_dma_map_single(struct device *dev, const void *addr, } EXPORT_SYMBOL(debug_dma_map_single); -void debug_dma_map_page(struct device *dev, struct page *page, size_t offset, - size_t size, int direction, dma_addr_t dma_addr, - unsigned long attrs) +void debug_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, + int direction, dma_addr_t dma_addr, unsigned long attrs) { struct dma_debug_entry *entry; @@ -1218,19 +1219,24 @@ void debug_dma_map_page(struct device *dev, struct page *page, size_t offset, return; entry->dev = dev; - entry->type = dma_debug_single; - entry->paddr = page_to_phys(page) + offset; + entry->type = dma_debug_phy; + entry->paddr = phys; entry->dev_addr = dma_addr; entry->size = size; entry->direction = direction; entry->map_err_type = MAP_ERR_NOT_CHECKED; - check_for_stack(dev, page, offset); + if (!(attrs & DMA_ATTR_MMIO)) { + struct page *page = phys_to_page(phys); + size_t offset = offset_in_page(page); - if (!PageHighMem(page)) { - void *addr = page_address(page) + offset; + check_for_stack(dev, page, offset); - check_for_illegal_area(dev, addr, size); + if (!PageHighMem(page)) { + void *addr = page_address(page) + offset; + + check_for_illegal_area(dev, addr, size); + } } add_dma_entry(entry, attrs); @@ -1274,11 +1280,11 @@ void debug_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) } EXPORT_SYMBOL(debug_dma_mapping_error); -void debug_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, +void debug_dma_unmap_phys(struct device *dev, dma_addr_t dma_addr, size_t size, int direction) { struct dma_debug_entry ref = { - .type = dma_debug_single, + .type = dma_debug_phy, .dev = dev, .dev_addr = dma_addr, .size = size, diff --git a/kernel/dma/debug.h b/kernel/dma/debug.h index f525197d3cae6..76adb42bffd5f 100644 --- a/kernel/dma/debug.h +++ b/kernel/dma/debug.h @@ -9,12 +9,11 @@ #define _KERNEL_DMA_DEBUG_H #ifdef CONFIG_DMA_API_DEBUG -extern void debug_dma_map_page(struct device *dev, struct page *page, - size_t offset, size_t size, - int direction, dma_addr_t dma_addr, +extern void debug_dma_map_phys(struct device *dev, phys_addr_t phys, + size_t size, int direction, dma_addr_t dma_addr, unsigned long attrs); -extern void debug_dma_unmap_page(struct device *dev, dma_addr_t addr, +extern void debug_dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size, int direction); extern void debug_dma_map_sg(struct device *dev, struct scatterlist *sg, @@ -55,14 +54,13 @@ extern void debug_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, int direction); #else /* CONFIG_DMA_API_DEBUG */ -static inline void debug_dma_map_page(struct device *dev, struct page *page, - size_t offset, size_t size, - int direction, dma_addr_t dma_addr, - unsigned long attrs) +static inline void debug_dma_map_phys(struct device *dev, phys_addr_t phys, + size_t size, int direction, + dma_addr_t dma_addr, unsigned long attrs) { } -static inline void debug_dma_unmap_page(struct device *dev, dma_addr_t addr, +static inline void debug_dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size, int direction) { } diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index 107e4a4d251df..4c1dfbabb8ae5 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -157,6 +157,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, unsigned long attrs) { const struct dma_map_ops *ops = get_dma_ops(dev); + phys_addr_t phys = page_to_phys(page) + offset; dma_addr_t addr; BUG_ON(!valid_dma_direction(dir)); @@ -165,16 +166,15 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, return DMA_MAPPING_ERROR; if (dma_map_direct(dev, ops) || - arch_dma_map_page_direct(dev, page_to_phys(page) + offset + size)) + arch_dma_map_page_direct(dev, phys + size)) addr = dma_direct_map_page(dev, page, offset, size, dir, attrs); else if (use_dma_iommu(dev)) addr = iommu_dma_map_page(dev, page, offset, size, dir, attrs); else addr = ops->map_page(dev, page, offset, size, dir, attrs); kmsan_handle_dma(page, offset, size, dir); - trace_dma_map_page(dev, page_to_phys(page) + offset, addr, size, dir, - attrs); - debug_dma_map_page(dev, page, offset, size, dir, addr, attrs); + trace_dma_map_page(dev, phys, addr, size, dir, attrs); + debug_dma_map_phys(dev, phys, size, dir, addr, attrs); return addr; } @@ -194,7 +194,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, else ops->unmap_page(dev, addr, size, dir, attrs); trace_dma_unmap_page(dev, addr, size, dir, attrs); - debug_dma_unmap_page(dev, addr, size, dir); + debug_dma_unmap_phys(dev, addr, size, dir); } EXPORT_SYMBOL(dma_unmap_page_attrs); @@ -712,7 +712,8 @@ struct page *dma_alloc_pages(struct device *dev, size_t size, if (page) { trace_dma_alloc_pages(dev, page_to_virt(page), *dma_handle, size, dir, gfp, 0); - debug_dma_map_page(dev, page, 0, size, dir, *dma_handle, 0); + debug_dma_map_phys(dev, page_to_phys(page), size, dir, + *dma_handle, 0); } else { trace_dma_alloc_pages(dev, NULL, 0, size, dir, gfp, 0); } @@ -738,7 +739,7 @@ void dma_free_pages(struct device *dev, size_t size, struct page *page, dma_addr_t dma_handle, enum dma_data_direction dir) { trace_dma_free_pages(dev, page_to_virt(page), dma_handle, size, dir, 0); - debug_dma_unmap_page(dev, dma_handle, size, dir); + debug_dma_unmap_phys(dev, dma_handle, size, dir); __dma_free_pages(dev, size, page, dma_handle, dir); } EXPORT_SYMBOL_GPL(dma_free_pages); -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:43:32 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:43:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069166.1433015 (Exim 4.92) (envelope-from ) id 1uiuXM-0007IJ-10; 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Mon, 4 Aug 2025 12:43:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 96668C4CEF8; Mon, 4 Aug 2025 12:43:27 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9f577fea-7130-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311409; bh=B6ggJVOQfTYMCOE/nJsgZM614saTj7Qtn55LwfqKBMA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mACwCJwnciJCEbZnCrkOPhfxhxsK8nNGbFRTcuF/UprHjNhigkEBz4Qjo6q3nOYnE NNEuUiRwpxiJJ+5+lJPFbBh1pz1NHdaolrAAyyFd/BDEth7WPdBMjVzrlmdIaxA3Qb 2RsWBm5LtpycB6Eoe6pJbVmXbTVoQjyF0BJrKzZPE5F7UARnqwUUZNfC3023xQAdCk GMv+SVJ7lY8MSINtMTSQNgemwlQgadSRLsUt+7E2s6eroO/rhcn1uAVTTMaXvcyAt7 AFjFAFTQV2Ju8uDUJFNXpQWgxbDaQrFpkFb9ltCXITe4mMxj1t62jvARy38KRhJWAk x4Lll22SY+E5Q== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 01/16] dma-mapping: introduce new DMA attribute to indicate MMIO memory Date: Mon, 4 Aug 2025 15:42:35 +0300 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky This patch introduces the DMA_ATTR_MMIO attribute to mark DMA buffers that reside in memory-mapped I/O (MMIO) regions, such as device BARs exposed through the host bridge, which are accessible for peer-to-peer (P2P) DMA. This attribute is especially useful for exporting device memory to other devices for DMA without CPU involvement, and avoids unnecessary or potentially detrimental CPU cache maintenance calls. Signed-off-by: Leon Romanovsky --- Documentation/core-api/dma-attributes.rst | 7 +++++++ include/linux/dma-mapping.h | 14 ++++++++++++++ include/trace/events/dma.h | 3 ++- rust/kernel/dma.rs | 3 +++ 4 files changed, 26 insertions(+), 1 deletion(-) diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst index 1887d92e8e926..91acd2684e506 100644 --- a/Documentation/core-api/dma-attributes.rst +++ b/Documentation/core-api/dma-attributes.rst @@ -130,3 +130,10 @@ accesses to DMA buffers in both privileged "supervisor" and unprivileged subsystem that the buffer is fully accessible at the elevated privilege level (and ideally inaccessible or at least read-only at the lesser-privileged levels). + +DMA_ATTR_MMIO +------------- + +This attribute is especially useful for exporting device memory to other +devices for DMA without CPU involvement, and avoids unnecessary or +potentially detrimental CPU cache maintenance calls. diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index 55c03e5fe8cb3..afc89835c7457 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -58,6 +58,20 @@ */ #define DMA_ATTR_PRIVILEGED (1UL << 9) +/* + * DMA_ATTR_MMIO - Indicates memory-mapped I/O (MMIO) region for DMA mapping + * + * This attribute is used for MMIO memory regions that are exposed through + * the host bridge and are accessible for peer-to-peer (P2P) DMA. Memory + * marked with this attribute is not system RAM and may represent device + * BAR windows or peer-exposed memory. + * + * Typical usage is for mapping hardware memory BARs or exporting device + * memory to other devices for DMA without involving main system RAM. + * The attribute guarantees no CPU cache maintenance calls will be made. + */ +#define DMA_ATTR_MMIO (1UL << 10) + /* * A dma_addr_t can hold any valid DMA or bus address for the platform. It can * be given to a device to use as a DMA source or target. It is specific to a diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h index d8ddc27b6a7c8..ee90d6f1dcf35 100644 --- a/include/trace/events/dma.h +++ b/include/trace/events/dma.h @@ -31,7 +31,8 @@ TRACE_DEFINE_ENUM(DMA_NONE); { DMA_ATTR_FORCE_CONTIGUOUS, "FORCE_CONTIGUOUS" }, \ { DMA_ATTR_ALLOC_SINGLE_PAGES, "ALLOC_SINGLE_PAGES" }, \ { DMA_ATTR_NO_WARN, "NO_WARN" }, \ - { DMA_ATTR_PRIVILEGED, "PRIVILEGED" }) + { DMA_ATTR_PRIVILEGED, "PRIVILEGED" }, \ + { DMA_ATTR_MMIO, "MMIO" }) DECLARE_EVENT_CLASS(dma_map, TP_PROTO(struct device *dev, phys_addr_t phys_addr, dma_addr_t dma_addr, diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs index 2bc8ab51ec280..61d9eed7a786e 100644 --- a/rust/kernel/dma.rs +++ b/rust/kernel/dma.rs @@ -242,6 +242,9 @@ pub mod attrs { /// Indicates that the buffer is fully accessible at an elevated privilege level (and /// ideally inaccessible or at least read-only at lesser-privileged levels). pub const DMA_ATTR_PRIVILEGED: Attrs = Attrs(bindings::DMA_ATTR_PRIVILEGED); + + /// Indicates that the buffer is MMIO memory. + pub const DMA_ATTR_MMIO: Attrs = Attrs(bindings::DMA_ATTR_MMIO); } /// An abstraction of the `dma_alloc_coherent` API. -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:43:39 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:43:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069168.1433026 (Exim 4.92) (envelope-from ) id 1uiuXT-0007il-Aj; Mon, 04 Aug 2025 12:43:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069168.1433026; Mon, 04 Aug 2025 12:43:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXT-0007ie-6s; Mon, 04 Aug 2025 12:43:39 +0000 Received: by outflank-mailman (input) for mailman id 1069168; Mon, 04 Aug 2025 12:43:37 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXR-0006V7-Nh for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:43:37 +0000 Received: from nyc.source.kernel.org (nyc.source.kernel.org [147.75.193.91]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id a3062ad6-7130-11f0-b898-0df219b8e170; Mon, 04 Aug 2025 14:43:36 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 46869A55826; Mon, 4 Aug 2025 12:43:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7673FC4CEE7; Mon, 4 Aug 2025 12:43:33 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a3062ad6-7130-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311414; bh=gXQfTddyrmH8Ixen8MMOQFcSDtf75ytBbFmEnbpkIK0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WRgsvRlFW0e77jc7NIsyBW2keN26coVZrkVCiSkqs4aw+XPWcg7vc+V1XlKoIcE88 IOIbPQelgEDLheM/qg7mVhJZzAqXm7CUjMAMKNzC+umg0g7DwYC9YBLyHXL0I66FCh IFbMO71xVEUgxdJl2+IupUgaBpdkpCp+VfiDgWnzz0MMd73xSf4ctXSScspzbf7J4C MQm70SnKxDBQEq6Qi5EQDhrkAfT+WwzTZQfsthVUSLn1pLEnK9pcRGmBAGcQOXI3DR pSMdvMXvMDulNitg5dtAwYyxJ7hDxcGMKpGt6kEpCAlccx1SJGPya+SDEHg8s11i4i u8QgrR2e/DTYQ== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 04/16] dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys Date: Mon, 4 Aug 2025 15:42:38 +0300 Message-ID: <7e10dcba2f3108efc6af13bfdbe8f09073835838.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky As a preparation for following map_page -> map_phys API conversion, let's rename trace_dma_*map_page() to be trace_dma_*map_phys(). Signed-off-by: Leon Romanovsky --- include/trace/events/dma.h | 4 ++-- kernel/dma/mapping.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h index ee90d6f1dcf35..84416c7d6bfaa 100644 --- a/include/trace/events/dma.h +++ b/include/trace/events/dma.h @@ -72,7 +72,7 @@ DEFINE_EVENT(dma_map, name, \ size_t size, enum dma_data_direction dir, unsigned long attrs), \ TP_ARGS(dev, phys_addr, dma_addr, size, dir, attrs)) -DEFINE_MAP_EVENT(dma_map_page); +DEFINE_MAP_EVENT(dma_map_phys); DEFINE_MAP_EVENT(dma_map_resource); DECLARE_EVENT_CLASS(dma_unmap, @@ -110,7 +110,7 @@ DEFINE_EVENT(dma_unmap, name, \ enum dma_data_direction dir, unsigned long attrs), \ TP_ARGS(dev, addr, size, dir, attrs)) -DEFINE_UNMAP_EVENT(dma_unmap_page); +DEFINE_UNMAP_EVENT(dma_unmap_phys); DEFINE_UNMAP_EVENT(dma_unmap_resource); DECLARE_EVENT_CLASS(dma_alloc_class, diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index 4c1dfbabb8ae5..fe1f0da6dc507 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -173,7 +173,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, else addr = ops->map_page(dev, page, offset, size, dir, attrs); kmsan_handle_dma(page, offset, size, dir); - trace_dma_map_page(dev, phys, addr, size, dir, attrs); + trace_dma_map_phys(dev, phys, addr, size, dir, attrs); debug_dma_map_phys(dev, phys, size, dir, addr, attrs); return addr; @@ -193,7 +193,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, iommu_dma_unmap_page(dev, addr, size, dir, attrs); else ops->unmap_page(dev, addr, size, dir, attrs); - trace_dma_unmap_page(dev, addr, size, dir, attrs); + trace_dma_unmap_phys(dev, addr, size, dir, attrs); debug_dma_unmap_phys(dev, addr, size, dir); } EXPORT_SYMBOL(dma_unmap_page_attrs); -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:43:44 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:43:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069175.1433036 (Exim 4.92) (envelope-from ) id 1uiuXY-0008FI-Ix; Mon, 04 Aug 2025 12:43:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069175.1433036; Mon, 04 Aug 2025 12:43:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXY-0008F0-EX; Mon, 04 Aug 2025 12:43:44 +0000 Received: by outflank-mailman (input) for mailman id 1069175; Mon, 04 Aug 2025 12:43:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXW-0006VD-Il for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:43:42 +0000 Received: from sea.source.kernel.org (sea.source.kernel.org [172.234.252.31]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a60fbd40-7130-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 14:43:41 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id 5EDCF4423C; Mon, 4 Aug 2025 12:43:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D6868C4CEF0; Mon, 4 Aug 2025 12:43:38 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a60fbd40-7130-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311420; bh=KuB85oQ1zEvHewxjvaa7TgR+vPeGP91gwiah2Yizc2c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hwpc/2Lt2D3anuuHX/CywReJ+JevkzY6FynhQNLZcPcidH3a8z4Y3cZmYKqJx40aB HuWBeZEysO6t3oSzFklaWg8fzR58b4rw4vPFNALiUc9A9irWH9TDeW0nOLlTcNMjg5 8y75jvY8oofTniAsxP4pz8Mu3KaSfgmilMiaTliZ/mjlKSNBhY+c10mFYtQHZ4AR/7 Xmk6xDyL82OWzMQWw/B3tiObakK+I7qRBS7g9Wgz6viepi3WB5CZHiWKKRcEEGPKzI Kj0BbJnhOLGzRPSZ09k5YVjeQRC0y6mBjsRtkaL/iwYbfSRrLhH2F4a0OA4eEyJn4C wZIRnvkij7dkA== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 06/16] iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory Date: Mon, 4 Aug 2025 15:42:40 +0300 Message-ID: <09c04e0428f422c1b13d2b054af16e719de318a3.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Combine iommu_dma_*map_phys with iommu_dma_*map_resource interfaces in order to allow single phys_addr_t flow. Signed-off-by: Leon Romanovsky --- drivers/iommu/dma-iommu.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 11c5d5f8c0981..0a19ce50938b3 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -1193,12 +1193,17 @@ static inline size_t iova_unaligned(struct iova_domain *iovad, phys_addr_t phys, dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, enum dma_data_direction dir, unsigned long attrs) { - bool coherent = dev_is_dma_coherent(dev); - int prot = dma_info_to_prot(dir, coherent, attrs); struct iommu_domain *domain = iommu_get_dma_domain(dev); struct iommu_dma_cookie *cookie = domain->iova_cookie; struct iova_domain *iovad = &cookie->iovad; dma_addr_t iova, dma_mask = dma_get_mask(dev); + bool coherent; + int prot; + + if (attrs & DMA_ATTR_MMIO) + return __iommu_dma_map(dev, phys, size, + dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO, + dma_get_mask(dev)); /* * If both the physical buffer start address and size are page aligned, @@ -1211,6 +1216,9 @@ dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, return DMA_MAPPING_ERROR; } + coherent = dev_is_dma_coherent(dev); + prot = dma_info_to_prot(dir, coherent, attrs); + if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) arch_sync_dma_for_device(phys, size, dir); @@ -1223,10 +1231,14 @@ dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir, unsigned long attrs) { - struct iommu_domain *domain = iommu_get_dma_domain(dev); phys_addr_t phys; - phys = iommu_iova_to_phys(domain, dma_handle); + if (attrs & DMA_ATTR_MMIO) { + __iommu_dma_unmap(dev, dma_handle, size); + return; + } + + phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle); if (WARN_ON(!phys)) return; -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:43:48 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:43:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069181.1433046 (Exim 4.92) (envelope-from ) id 1uiuXc-0000DM-QL; Mon, 04 Aug 2025 12:43:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069181.1433046; Mon, 04 Aug 2025 12:43:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXc-0000DC-Lh; Mon, 04 Aug 2025 12:43:48 +0000 Received: by outflank-mailman (input) for mailman id 1069181; Mon, 04 Aug 2025 12:43:47 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXb-0006VD-5w for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:43:47 +0000 Received: from tor.source.kernel.org (tor.source.kernel.org [2600:3c04:e001:324:0:1991:8:25]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a9037b29-7130-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 14:43:46 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id AE031601FD; Mon, 4 Aug 2025 12:43:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9423FC4CEE7; Mon, 4 Aug 2025 12:43:43 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: a9037b29-7130-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311424; bh=974P2mquMC7dLPtwo4RbF3aKdnRgjXusEE0OKr9VEPo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sRzNIswyOXbP49BscDBQ+94sPL3uQydFVa6yD3MLC4jh0WkntDIM+qnsOlQuXDIVr wxnQwyeKJFQGPd7H59/m+DRXV9WGkkfngBQYFQnV2Vx5zdbDTmlp3SKPzzugttJ5wK Y94WaLaho7OI9fqCDv7wnjA4LbMPxMu1m7XNoFz9vxQttjkrfNEZgFRlKOgE5FUG9O 9S+EDseCadKtr6Zd8jY55mBnPek99fWQfl0LLIwkcioEL+wWEh9akcqBS/aNmw3uOI i2gfa9Kf8zAEiD7yipdlK7kOpCvN+05lo1g4pMkP27RWr31YBzoQ7Nv4fuU8IiE/Yw SuLv6jnr2CKZg== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 07/16] dma-mapping: convert dma_direct_*map_page to be phys_addr_t based Date: Mon, 4 Aug 2025 15:42:41 +0300 Message-ID: <882499bb37bf4af3dece27d9f791a8982ca4c6a7.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Convert the DMA direct mapping functions to accept physical addresses directly instead of page+offset parameters. The functions were already operating on physical addresses internally, so this change eliminates the redundant page-to-physical conversion at the API boundary. The functions dma_direct_map_page() and dma_direct_unmap_page() are renamed to dma_direct_map_phys() and dma_direct_unmap_phys() respectively, with their calling convention changed from (struct page *page, unsigned long offset) to (phys_addr_t phys). Architecture-specific functions arch_dma_map_page_direct() and arch_dma_unmap_page_direct() are similarly renamed to arch_dma_map_phys_direct() and arch_dma_unmap_phys_direct(). The is_pci_p2pdma_page() checks are replaced with DMA_ATTR_MMIO checks to allow integration with dma_direct_map_resource and dma_direct_map_phys() is extended to support MMIO path either. Signed-off-by: Leon Romanovsky --- arch/powerpc/kernel/dma-iommu.c | 4 +-- include/linux/dma-map-ops.h | 8 +++--- kernel/dma/direct.c | 6 ++-- kernel/dma/direct.h | 50 ++++++++++++++++++++------------- kernel/dma/mapping.c | 8 +++--- 5 files changed, 44 insertions(+), 32 deletions(-) diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c index 4d64a5db50f38..0359ab72cd3ba 100644 --- a/arch/powerpc/kernel/dma-iommu.c +++ b/arch/powerpc/kernel/dma-iommu.c @@ -14,7 +14,7 @@ #define can_map_direct(dev, addr) \ ((dev)->bus_dma_limit >= phys_to_dma((dev), (addr))) -bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr) +bool arch_dma_map_phys_direct(struct device *dev, phys_addr_t addr) { if (likely(!dev->bus_dma_limit)) return false; @@ -24,7 +24,7 @@ bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr) #define is_direct_handle(dev, h) ((h) >= (dev)->archdata.dma_offset) -bool arch_dma_unmap_page_direct(struct device *dev, dma_addr_t dma_handle) +bool arch_dma_unmap_phys_direct(struct device *dev, dma_addr_t dma_handle) { if (likely(!dev->bus_dma_limit)) return false; diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h index f48e5fb88bd5d..71f5b30254159 100644 --- a/include/linux/dma-map-ops.h +++ b/include/linux/dma-map-ops.h @@ -392,15 +392,15 @@ void *arch_dma_set_uncached(void *addr, size_t size); void arch_dma_clear_uncached(void *addr, size_t size); #ifdef CONFIG_ARCH_HAS_DMA_MAP_DIRECT -bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr); -bool arch_dma_unmap_page_direct(struct device *dev, dma_addr_t dma_handle); +bool arch_dma_map_phys_direct(struct device *dev, phys_addr_t addr); +bool arch_dma_unmap_phys_direct(struct device *dev, dma_addr_t dma_handle); bool arch_dma_map_sg_direct(struct device *dev, struct scatterlist *sg, int nents); bool arch_dma_unmap_sg_direct(struct device *dev, struct scatterlist *sg, int nents); #else -#define arch_dma_map_page_direct(d, a) (false) -#define arch_dma_unmap_page_direct(d, a) (false) +#define arch_dma_map_phys_direct(d, a) (false) +#define arch_dma_unmap_phys_direct(d, a) (false) #define arch_dma_map_sg_direct(d, s, n) (false) #define arch_dma_unmap_sg_direct(d, s, n) (false) #endif diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c index 24c359d9c8799..fa75e30700730 100644 --- a/kernel/dma/direct.c +++ b/kernel/dma/direct.c @@ -453,7 +453,7 @@ void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl, if (sg_dma_is_bus_address(sg)) sg_dma_unmark_bus_address(sg); else - dma_direct_unmap_page(dev, sg->dma_address, + dma_direct_unmap_phys(dev, sg->dma_address, sg_dma_len(sg), dir, attrs); } } @@ -476,8 +476,8 @@ int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents, */ break; case PCI_P2PDMA_MAP_NONE: - sg->dma_address = dma_direct_map_page(dev, sg_page(sg), - sg->offset, sg->length, dir, attrs); + sg->dma_address = dma_direct_map_phys(dev, sg_phys(sg), + sg->length, dir, attrs); if (sg->dma_address == DMA_MAPPING_ERROR) { ret = -EIO; goto out_unmap; diff --git a/kernel/dma/direct.h b/kernel/dma/direct.h index d2c0b7e632fc0..2b442efc9b5a7 100644 --- a/kernel/dma/direct.h +++ b/kernel/dma/direct.h @@ -80,42 +80,54 @@ static inline void dma_direct_sync_single_for_cpu(struct device *dev, arch_dma_mark_clean(paddr, size); } -static inline dma_addr_t dma_direct_map_page(struct device *dev, - struct page *page, unsigned long offset, size_t size, - enum dma_data_direction dir, unsigned long attrs) +static inline dma_addr_t dma_direct_map_phys(struct device *dev, + phys_addr_t phys, size_t size, enum dma_data_direction dir, + unsigned long attrs) { - phys_addr_t phys = page_to_phys(page) + offset; - dma_addr_t dma_addr = phys_to_dma(dev, phys); + bool is_mmio = attrs & DMA_ATTR_MMIO; + dma_addr_t dma_addr; + bool capable; + + dma_addr = (is_mmio) ? phys : phys_to_dma(dev, phys); + capable = dma_capable(dev, dma_addr, size, is_mmio); + if (is_mmio) { + if (unlikely(!capable)) + goto err_overflow; + return dma_addr; + } - if (is_swiotlb_force_bounce(dev)) { - if (is_pci_p2pdma_page(page)) - return DMA_MAPPING_ERROR; + if (is_swiotlb_force_bounce(dev)) return swiotlb_map(dev, phys, size, dir, attrs); - } - if (unlikely(!dma_capable(dev, dma_addr, size, true)) || - dma_kmalloc_needs_bounce(dev, size, dir)) { - if (is_pci_p2pdma_page(page)) - return DMA_MAPPING_ERROR; + if (unlikely(!capable) || dma_kmalloc_needs_bounce(dev, size, dir)) { if (is_swiotlb_active(dev)) return swiotlb_map(dev, phys, size, dir, attrs); - dev_WARN_ONCE(dev, 1, - "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", - &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); - return DMA_MAPPING_ERROR; + goto err_overflow; } if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) arch_sync_dma_for_device(phys, size, dir); return dma_addr; + +err_overflow: + dev_WARN_ONCE( + dev, 1, + "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", + &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); + return DMA_MAPPING_ERROR; } -static inline void dma_direct_unmap_page(struct device *dev, dma_addr_t addr, +static inline void dma_direct_unmap_phys(struct device *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir, unsigned long attrs) { - phys_addr_t phys = dma_to_phys(dev, addr); + phys_addr_t phys; + + if (attrs & DMA_ATTR_MMIO) + /* nothing to do: uncached and no swiotlb */ + return; + phys = dma_to_phys(dev, addr); if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) dma_direct_sync_single_for_cpu(dev, addr, size, dir); diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index 58482536db9bb..80481a873340a 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -166,8 +166,8 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, return DMA_MAPPING_ERROR; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 12:45:39.1542 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9618c8da-d0e0-465e-b9ed-08ddd354d0f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5776 Hi Hari, On 30/07/2025 09:45, Hari Limaye wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > From: Luca Fancellu > > Implement the MPU variant of `setup_frametable_mappings`. This function > will be called by `setup_mm` when an implementation for MPU systems is > added in a follow up commit. > > Signed-off-by: Luca Fancellu > Signed-off-by: Hari Limaye Reviewed-by: Ayan Kumarb Halder Tested-by: Ayan Kumarb Halder (On R82 and R52 with some additional patches) - Ayan From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:51:09 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:51:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069208.1433066 (Exim 4.92) (envelope-from ) id 1uiuee-0003Nv-SG; Mon, 04 Aug 2025 12:51:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069208.1433066; Mon, 04 Aug 2025 12:51:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuee-0003No-P6; Mon, 04 Aug 2025 12:51:04 +0000 Received: by outflank-mailman (input) for mailman id 1069208; Mon, 04 Aug 2025 12:51:03 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuY5-0006V7-E5 for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:44:17 +0000 Received: from nyc.source.kernel.org (nyc.source.kernel.org [147.75.193.91]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id baab2ecc-7130-11f0-b898-0df219b8e170; Mon, 04 Aug 2025 14:44:15 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 0920DA55826; Mon, 4 Aug 2025 12:44:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 58081C4CEF0; Mon, 4 Aug 2025 12:44:13 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: baab2ecc-7130-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311454; bh=qnVGWPERMw1BTa2/gk85Rr9nCLsamOSAPU4HKvyJS1c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OtgAnXB9G/hO4kHiG6lUbx1lGdhplK8QSnQvERbDkZeJ2rBPi5BohP2fOcU1EY1H0 LWK7JmM6eYjvDV85Iv2oqAeUvxpoecgv6pnhGevxoOAJjwoIKIBVlnyhDtWl6iMFdx RkkwEUkNj1PK4RIEa7lvhblH+3HASR9LDXUdd9ooPuLmkTQNLafsqp7vExm+lHX79L xgsW9Dlqtb1H+ROfUItFyQuMNgUa0HHgvJ+5cBoMm5E0OKANto/+eCMPooaSWD2S6k W4Hqu5Itep2BtJPMCEt1CECg7NNUHsl45+R6007i0eogZT7o+A+uJhsGr5xPHo73g0 Vn+VRBXex4Xsg== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 10/16] xen: swiotlb: Open code map_resource callback Date: Mon, 4 Aug 2025 15:42:44 +0300 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky General dma_direct_map_resource() is going to be removed in next patch, so simply open-code it in xen driver. Signed-off-by: Leon Romanovsky --- drivers/xen/swiotlb-xen.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c index da1a7d3d377cf..dd7747a2de879 100644 --- a/drivers/xen/swiotlb-xen.c +++ b/drivers/xen/swiotlb-xen.c @@ -392,6 +392,25 @@ xen_swiotlb_sync_sg_for_device(struct device *dev, struct scatterlist *sgl, } } +static dma_addr_t xen_swiotlb_direct_map_resource(struct device *dev, + phys_addr_t paddr, + size_t size, + enum dma_data_direction dir, + unsigned long attrs) +{ + dma_addr_t dma_addr = paddr; + + if (unlikely(!dma_capable(dev, dma_addr, size, false))) { + dev_err_once(dev, + "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", + &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); + WARN_ON_ONCE(1); + return DMA_MAPPING_ERROR; + } + + return dma_addr; +} + /* * Return whether the given device DMA address mask can be supported * properly. For example, if your device can only drive the low 24-bits @@ -426,5 +445,5 @@ const struct dma_map_ops xen_swiotlb_dma_ops = { .alloc_pages_op = dma_common_alloc_pages, .free_pages = dma_common_free_pages, .max_mapping_size = swiotlb_max_mapping_size, - .map_resource = dma_direct_map_resource, + .map_resource = xen_swiotlb_direct_map_resource, }; -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:51:17 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:51:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069213.1433076 (Exim 4.92) (envelope-from ) id 1uiuer-0003kg-49; Mon, 04 Aug 2025 12:51:17 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069213.1433076; Mon, 04 Aug 2025 12:51:17 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuer-0003kZ-0f; Mon, 04 Aug 2025 12:51:17 +0000 Received: by outflank-mailman (input) for mailman id 1069213; Mon, 04 Aug 2025 12:51:15 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuYE-0006V7-OZ for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:44:26 +0000 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id bfe031d2-7130-11f0-b898-0df219b8e170; Mon, 04 Aug 2025 14:44:24 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 91E5C5C5F4C; Mon, 4 Aug 2025 12:44:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D115C4CEE7; Mon, 4 Aug 2025 12:44:22 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bfe031d2-7130-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311463; bh=vHoVz+WsFzZyOWz8hKi3gaHzcDQnMM6K5YlppZB3S5Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CEWxy3DQJEv8tmWrU60JGu2vy2JC6Vy5gQ7dkMLe3WhDD80GhgtaPSi2T4O+uh/qX dzCLBAG639t4BdY7iOVuiz/s1KjNeAuSDkQxAswKoB8Dlog8b4SWYXyCwMpjyJfJs/ N598nGgARAwbbzCyY7NB50l2J7JGzBArXzyzEB0gXQ+Arna+DrOW+E2PsAsdgJv7Pa Xqf4bgAaoc0j7DzDpKnhtwqRE6JormvtT5/kXa44BjUbPKvgizXbhqf9ZKiiePFStu qAJ3Rs9QlPzNZq5SwsxLYx3N0dkWN+PMHiDWxME92RHKujqBYmsalcvoVTj85/jbJK SRTlNuuOgXchw== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 14/16] block-dma: migrate to dma_map_phys instead of map_page Date: Mon, 4 Aug 2025 15:42:48 +0300 Message-ID: <9b8454a8a24ace186a22242e218e4f4fed103fdd.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky After introduction of dma_map_phys(), there is no need to convert from physical address to struct page in order to map page. So let's use it directly. Signed-off-by: Leon Romanovsky --- block/blk-mq-dma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/block/blk-mq-dma.c b/block/blk-mq-dma.c index ad283017caef2..37e2142be4f7d 100644 --- a/block/blk-mq-dma.c +++ b/block/blk-mq-dma.c @@ -87,8 +87,8 @@ static bool blk_dma_map_bus(struct blk_dma_iter *iter, struct phys_vec *vec) static bool blk_dma_map_direct(struct request *req, struct device *dma_dev, struct blk_dma_iter *iter, struct phys_vec *vec) { - iter->addr = dma_map_page(dma_dev, phys_to_page(vec->paddr), - offset_in_page(vec->paddr), vec->len, rq_dma_dir(req)); + iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len, + rq_dma_dir(req), 0); if (dma_mapping_error(dma_dev, iter->addr)) { iter->status = BLK_STS_RESOURCE; return false; -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:51:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:51:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069217.1433086 (Exim 4.92) (envelope-from ) id 1uiuez-000491-Aq; Mon, 04 Aug 2025 12:51:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069217.1433086; Mon, 04 Aug 2025 12:51:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuez-00048s-7A; Mon, 04 Aug 2025 12:51:25 +0000 Received: by outflank-mailman (input) for mailman id 1069217; Mon, 04 Aug 2025 12:51:23 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXu-0006VD-UT for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:44:07 +0000 Received: from nyc.source.kernel.org (nyc.source.kernel.org [147.75.193.91]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id b4ec8bc0-7130-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 14:44:06 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 53524A55807; Mon, 4 Aug 2025 12:44:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53748C4CEE7; Mon, 4 Aug 2025 12:44:03 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b4ec8bc0-7130-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311445; bh=nQ8mJNz8JUVPh4M/Ljj9VN6K2zPf9ZLUUVJWTFyBl+A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GansV4O33RE7bTiUe/oNxZ1/j8JluPHS14/eOky1Kgw46PimC/h6BaSBUDGRq12+X OkJSrxybJq/HteOgaIzllB8AsL+b7hRdM8DPNeLMHm+vZ/fR/LPNhiUazudBa3ty/O EJ1x4V+MsfVg7VBwvSqZsZVLaRQf9qyLSmRUN2c8y+lw9M06rQodqLnlnf5jTmNx18 LT/LEEm6hKNG2HPfx5SHtIWCLoi1qnrPS19m9ncban08q3hx8pnsDFQqSQLhEQmP8F DMTVJ/Ihc0ToY72sMUBykGK97puqzsvoLrLzWHM0oQIzdVjJNfPXuovmP6lgZeX5pc fRToWSP6g+OEA== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 11/16] dma-mapping: export new dma_*map_phys() interface Date: Mon, 4 Aug 2025 15:42:45 +0300 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Introduce new DMA mapping functions dma_map_phys() and dma_unmap_phys() that operate directly on physical addresses instead of page+offset parameters. This provides a more efficient interface for drivers that already have physical addresses available. The new functions are implemented as the primary mapping layer, with the existing dma_map_page_attrs() and dma_unmap_page_attrs() functions converted to simple wrappers around the phys-based implementations. The old page-based API is preserved in mapping.c to ensure that existing code won't be affected by changing EXPORT_SYMBOL to EXPORT_SYMBOL_GPL variant for dma_*map_phys(). Signed-off-by: Leon Romanovsky --- drivers/iommu/dma-iommu.c | 14 -------- include/linux/dma-direct.h | 2 -- include/linux/dma-mapping.h | 13 +++++++ include/linux/iommu-dma.h | 4 --- include/trace/events/dma.h | 2 -- kernel/dma/debug.c | 43 ----------------------- kernel/dma/debug.h | 21 ------------ kernel/dma/direct.c | 16 --------- kernel/dma/mapping.c | 68 ++++++++++++++++++++----------------- 9 files changed, 49 insertions(+), 134 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 0a19ce50938b3..69f85209be7ab 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -1556,20 +1556,6 @@ void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, __iommu_dma_unmap(dev, start, end - start); } -dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys, - size_t size, enum dma_data_direction dir, unsigned long attrs) -{ - return __iommu_dma_map(dev, phys, size, - dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO, - dma_get_mask(dev)); -} - -void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, - size_t size, enum dma_data_direction dir, unsigned long attrs) -{ - __iommu_dma_unmap(dev, handle, size); -} - static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr) { size_t alloc_size = PAGE_ALIGN(size); diff --git a/include/linux/dma-direct.h b/include/linux/dma-direct.h index f3bc0bcd70980..c249912456f96 100644 --- a/include/linux/dma-direct.h +++ b/include/linux/dma-direct.h @@ -149,7 +149,5 @@ void dma_direct_free_pages(struct device *dev, size_t size, struct page *page, dma_addr_t dma_addr, enum dma_data_direction dir); int dma_direct_supported(struct device *dev, u64 mask); -dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr, - size_t size, enum dma_data_direction dir, unsigned long attrs); #endif /* _LINUX_DMA_DIRECT_H */ diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index afc89835c7457..2aa43a6bed92b 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -132,6 +132,10 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, unsigned long attrs); void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir, unsigned long attrs); +dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, + enum dma_data_direction dir, unsigned long attrs); +void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size, + enum dma_data_direction dir, unsigned long attrs); unsigned int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction dir, unsigned long attrs); void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, @@ -186,6 +190,15 @@ static inline void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir, unsigned long attrs) { } +static inline dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, + size_t size, enum dma_data_direction dir, unsigned long attrs) +{ + return DMA_MAPPING_ERROR; +} +static inline void dma_unmap_phys(struct device *dev, dma_addr_t addr, + size_t size, enum dma_data_direction dir, unsigned long attrs) +{ +} static inline unsigned int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction dir, unsigned long attrs) diff --git a/include/linux/iommu-dma.h b/include/linux/iommu-dma.h index 485bdffed9888..a92b3ff9b9343 100644 --- a/include/linux/iommu-dma.h +++ b/include/linux/iommu-dma.h @@ -42,10 +42,6 @@ size_t iommu_dma_opt_mapping_size(void); size_t iommu_dma_max_mapping_size(struct device *dev); void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle, unsigned long attrs); -dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys, - size_t size, enum dma_data_direction dir, unsigned long attrs); -void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, - size_t size, enum dma_data_direction dir, unsigned long attrs); struct sg_table *iommu_dma_alloc_noncontiguous(struct device *dev, size_t size, enum dma_data_direction dir, gfp_t gfp, unsigned long attrs); void iommu_dma_free_noncontiguous(struct device *dev, size_t size, diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h index 84416c7d6bfaa..5da59fd8121db 100644 --- a/include/trace/events/dma.h +++ b/include/trace/events/dma.h @@ -73,7 +73,6 @@ DEFINE_EVENT(dma_map, name, \ TP_ARGS(dev, phys_addr, dma_addr, size, dir, attrs)) DEFINE_MAP_EVENT(dma_map_phys); -DEFINE_MAP_EVENT(dma_map_resource); DECLARE_EVENT_CLASS(dma_unmap, TP_PROTO(struct device *dev, dma_addr_t addr, size_t size, @@ -111,7 +110,6 @@ DEFINE_EVENT(dma_unmap, name, \ TP_ARGS(dev, addr, size, dir, attrs)) DEFINE_UNMAP_EVENT(dma_unmap_phys); -DEFINE_UNMAP_EVENT(dma_unmap_resource); DECLARE_EVENT_CLASS(dma_alloc_class, TP_PROTO(struct device *dev, void *virt_addr, dma_addr_t dma_addr, diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c index da6734e3a4ce9..06e31fd216e38 100644 --- a/kernel/dma/debug.c +++ b/kernel/dma/debug.c @@ -38,7 +38,6 @@ enum { dma_debug_single, dma_debug_sg, dma_debug_coherent, - dma_debug_resource, dma_debug_phy, }; @@ -141,7 +140,6 @@ static const char *type2name[] = { [dma_debug_single] = "single", [dma_debug_sg] = "scatter-gather", [dma_debug_coherent] = "coherent", - [dma_debug_resource] = "resource", [dma_debug_phy] = "phy", }; @@ -1448,47 +1446,6 @@ void debug_dma_free_coherent(struct device *dev, size_t size, check_unmap(&ref); } -void debug_dma_map_resource(struct device *dev, phys_addr_t addr, size_t size, - int direction, dma_addr_t dma_addr, - unsigned long attrs) -{ - struct dma_debug_entry *entry; - - if (unlikely(dma_debug_disabled())) - return; - - entry = dma_entry_alloc(); - if (!entry) - return; - - entry->type = dma_debug_resource; - entry->dev = dev; - entry->paddr = addr; - entry->size = size; - entry->dev_addr = dma_addr; - entry->direction = direction; - entry->map_err_type = MAP_ERR_NOT_CHECKED; - - add_dma_entry(entry, attrs); -} - -void debug_dma_unmap_resource(struct device *dev, dma_addr_t dma_addr, - size_t size, int direction) -{ - struct dma_debug_entry ref = { - .type = dma_debug_resource, - .dev = dev, - .dev_addr = dma_addr, - .size = size, - .direction = direction, - }; - - if (unlikely(dma_debug_disabled())) - return; - - check_unmap(&ref); -} - void debug_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, int direction) { diff --git a/kernel/dma/debug.h b/kernel/dma/debug.h index 76adb42bffd5f..424b8f912aded 100644 --- a/kernel/dma/debug.h +++ b/kernel/dma/debug.h @@ -30,14 +30,6 @@ extern void debug_dma_alloc_coherent(struct device *dev, size_t size, extern void debug_dma_free_coherent(struct device *dev, size_t size, void *virt, dma_addr_t addr); -extern void debug_dma_map_resource(struct device *dev, phys_addr_t addr, - size_t size, int direction, - dma_addr_t dma_addr, - unsigned long attrs); - -extern void debug_dma_unmap_resource(struct device *dev, dma_addr_t dma_addr, - size_t size, int direction); - extern void debug_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, int direction); @@ -88,19 +80,6 @@ static inline void debug_dma_free_coherent(struct device *dev, size_t size, { } -static inline void debug_dma_map_resource(struct device *dev, phys_addr_t addr, - size_t size, int direction, - dma_addr_t dma_addr, - unsigned long attrs) -{ -} - -static inline void debug_dma_unmap_resource(struct device *dev, - dma_addr_t dma_addr, size_t size, - int direction) -{ -} - static inline void debug_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, int direction) diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c index fa75e30700730..1062caac47e7b 100644 --- a/kernel/dma/direct.c +++ b/kernel/dma/direct.c @@ -502,22 +502,6 @@ int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents, return ret; } -dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr, - size_t size, enum dma_data_direction dir, unsigned long attrs) -{ - dma_addr_t dma_addr = paddr; - - if (unlikely(!dma_capable(dev, dma_addr, size, false))) { - dev_err_once(dev, - "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n", - &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit); - WARN_ON_ONCE(1); - return DMA_MAPPING_ERROR; - } - - return dma_addr; -} - int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt, void *cpu_addr, dma_addr_t dma_addr, size_t size, unsigned long attrs) diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index f5f051737e556..b747794448130 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -152,12 +152,10 @@ static inline bool dma_map_direct(struct device *dev, return dma_go_direct(dev, *dev->dma_mask, ops); } -dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, - size_t offset, size_t size, enum dma_data_direction dir, - unsigned long attrs) +dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, + enum dma_data_direction dir, unsigned long attrs) { const struct dma_map_ops *ops = get_dma_ops(dev); - phys_addr_t phys = page_to_phys(page) + offset; bool is_mmio = attrs & DMA_ATTR_MMIO; dma_addr_t addr; @@ -177,6 +175,9 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, addr = ops->map_resource(dev, phys, size, dir, attrs); } else { + struct page *page = phys_to_page(phys); + size_t offset = offset_in_page(phys); + /* * All platforms which implement .map_page() don't support * non-struct page backed addresses. @@ -190,9 +191,25 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, return addr; } +EXPORT_SYMBOL_GPL(dma_map_phys); + +dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, + size_t offset, size_t size, enum dma_data_direction dir, + unsigned long attrs) +{ + phys_addr_t phys = page_to_phys(page) + offset; + + if (unlikely(attrs & DMA_ATTR_MMIO)) + return DMA_MAPPING_ERROR; + + if (IS_ENABLED(CONFIG_DMA_API_DEBUG)) + WARN_ON_ONCE(!pfn_valid(PHYS_PFN(phys))); + + return dma_map_phys(dev, phys, size, dir, attrs); +} EXPORT_SYMBOL(dma_map_page_attrs); -void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, +void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir, unsigned long attrs) { const struct dma_map_ops *ops = get_dma_ops(dev); @@ -212,6 +229,16 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, trace_dma_unmap_phys(dev, addr, size, dir, attrs); debug_dma_unmap_phys(dev, addr, size, dir); } +EXPORT_SYMBOL_GPL(dma_unmap_phys); + +void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, + enum dma_data_direction dir, unsigned long attrs) +{ + if (unlikely(attrs & DMA_ATTR_MMIO)) + return; + + dma_unmap_phys(dev, addr, size, dir, attrs); +} EXPORT_SYMBOL(dma_unmap_page_attrs); static int __dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, @@ -337,41 +364,18 @@ EXPORT_SYMBOL(dma_unmap_sg_attrs); dma_addr_t dma_map_resource(struct device *dev, phys_addr_t phys_addr, size_t size, enum dma_data_direction dir, unsigned long attrs) { - const struct dma_map_ops *ops = get_dma_ops(dev); - dma_addr_t addr = DMA_MAPPING_ERROR; - - BUG_ON(!valid_dma_direction(dir)); - - if (WARN_ON_ONCE(!dev->dma_mask)) + if (IS_ENABLED(CONFIG_DMA_API_DEBUG) && + WARN_ON_ONCE(pfn_valid(PHYS_PFN(phys_addr)))) return DMA_MAPPING_ERROR; - if (dma_map_direct(dev, ops)) - addr = dma_direct_map_resource(dev, phys_addr, size, dir, attrs); - else if (use_dma_iommu(dev)) - addr = iommu_dma_map_resource(dev, phys_addr, size, dir, attrs); - else if (ops->map_resource) - addr = ops->map_resource(dev, phys_addr, size, dir, attrs); - - trace_dma_map_resource(dev, phys_addr, addr, size, dir, attrs); - debug_dma_map_resource(dev, phys_addr, size, dir, addr, attrs); - return addr; + return dma_map_phys(dev, phys_addr, size, dir, attrs | DMA_ATTR_MMIO); } EXPORT_SYMBOL(dma_map_resource); void dma_unmap_resource(struct device *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir, unsigned long attrs) { - const struct dma_map_ops *ops = get_dma_ops(dev); - - BUG_ON(!valid_dma_direction(dir)); - if (dma_map_direct(dev, ops)) - ; /* nothing to do: uncached and no swiotlb */ - else if (use_dma_iommu(dev)) - iommu_dma_unmap_resource(dev, addr, size, dir, attrs); - else if (ops->unmap_resource) - ops->unmap_resource(dev, addr, size, dir, attrs); - trace_dma_unmap_resource(dev, addr, size, dir, attrs); - debug_dma_unmap_resource(dev, addr, size, dir); + dma_unmap_phys(dev, addr, size, dir, attrs | DMA_ATTR_MMIO); } EXPORT_SYMBOL(dma_unmap_resource); -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:51:28 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:51:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069219.1433096 (Exim 4.92) (envelope-from ) id 1uiuf2-0004SQ-P9; Mon, 04 Aug 2025 12:51:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069219.1433096; Mon, 04 Aug 2025 12:51:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuf2-0004SH-KP; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311435; bh=j/IXC/mk0CucPDkDZSOLBQ/UHxOlDcVl+SoZNP0e+X0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ihw3Mu90j8p2iuP5oqZQ0qRYRAR/2eX9T50SB8VLM/IpeY+W5wW61GhW3av4wc29C 5rQPXs1M+s6jjy1+nIw6SWxZuIavX26CaEl38gSuxVMHKz9Ozga++BdX/JbT+AreaD thi1puaSRP5nUcta2FCkabbmnkHrUDPmtBsN8oUFKF0vUAnM1ZHd3jM+br9WjySLQ8 NTL3Vo53fSv59+EK2VgBP0cZFK4osZ7IM6oRQqchl8AnWygksQAVNXy453HYzPo2QW I3SOs53kRy1kdIAph2yeNZ5VK6beeqdsIxQeMAXinFMWTJElchVQzM+2upe9a5Me8M xXtsI8WERuQcg== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 09/16] dma-mapping: handle MMIO flow in dma_map|unmap_page Date: Mon, 4 Aug 2025 15:42:43 +0300 Message-ID: <152745932ce4200e4baaedcc59ef45c230e47896.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Extend base DMA page API to handle MMIO flow. Signed-off-by: Leon Romanovsky --- kernel/dma/mapping.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index 709405d46b2b4..f5f051737e556 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -158,6 +158,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, { const struct dma_map_ops *ops = get_dma_ops(dev); phys_addr_t phys = page_to_phys(page) + offset; + bool is_mmio = attrs & DMA_ATTR_MMIO; dma_addr_t addr; BUG_ON(!valid_dma_direction(dir)); @@ -166,12 +167,23 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, return DMA_MAPPING_ERROR; if (dma_map_direct(dev, ops) || - arch_dma_map_phys_direct(dev, phys + size)) + (!is_mmio && arch_dma_map_phys_direct(dev, phys + size))) addr = dma_direct_map_phys(dev, phys, size, dir, attrs); else if (use_dma_iommu(dev)) addr = iommu_dma_map_phys(dev, phys, size, dir, attrs); - else + else if (is_mmio) { + if (!ops->map_resource) + return DMA_MAPPING_ERROR; + + addr = ops->map_resource(dev, phys, size, dir, attrs); + } else { + /* + * All platforms which implement .map_page() don't support + * non-struct page backed addresses. + */ addr = ops->map_page(dev, page, offset, size, dir, attrs); + } + kmsan_handle_dma(phys, size, dir); trace_dma_map_phys(dev, phys, addr, size, dir, attrs); debug_dma_map_phys(dev, phys, size, dir, addr, attrs); @@ -184,14 +196,18 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, enum dma_data_direction dir, unsigned long attrs) { const struct dma_map_ops *ops = get_dma_ops(dev); + bool is_mmio = attrs & DMA_ATTR_MMIO; BUG_ON(!valid_dma_direction(dir)); if (dma_map_direct(dev, ops) || - arch_dma_unmap_phys_direct(dev, addr + size)) + (!is_mmio && arch_dma_unmap_phys_direct(dev, addr + size))) dma_direct_unmap_phys(dev, addr, size, dir, attrs); else if (use_dma_iommu(dev)) iommu_dma_unmap_phys(dev, addr, size, dir, attrs); - else + else if (is_mmio) { + if (ops->unmap_resource) + ops->unmap_resource(dev, addr, size, dir, attrs); + } else ops->unmap_page(dev, addr, size, dir, attrs); trace_dma_unmap_phys(dev, addr, size, dir, attrs); debug_dma_unmap_phys(dev, addr, size, dir); -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:51:29 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:51:29 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069221.1433100 (Exim 4.92) (envelope-from ) id 1uiuf3-0004Vc-3A; Mon, 04 Aug 2025 12:51:29 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069221.1433100; Mon, 04 Aug 2025 12:51:29 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuf2-0004VC-T9; Mon, 04 Aug 2025 12:51:28 +0000 Received: by outflank-mailman (input) for mailman id 1069221; Mon, 04 Aug 2025 12:51:27 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXg-0006VD-7A for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:43:52 +0000 Received: from nyc.source.kernel.org (nyc.source.kernel.org [147.75.193.91]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id abad2c6e-7130-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 14:43:50 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id DB03EA55869; Mon, 4 Aug 2025 12:43:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77632C4CEF8; Mon, 4 Aug 2025 12:43:48 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: abad2c6e-7130-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311429; bh=fV/HgrK+DFqDLLsHNIEfHPO7ePKynetLmNvxMPUxMvM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Aa0MuxNBbcIy902+5pajDqLKZSF1w44g4nO478lMbvVmelIgJo9/XEVtOJdLolm32 q7aXDo/HichuVD7Pb+Aa/K/QU+jft9TqQt6qSowqpu9o7oVK33kF7h87bAMiCEuh7J GTG4UxRiY9ThlFKl1TYW6avleePvBUl4DfH/vEF1Kr9msK2hTjqPSEBQo2CPPDN9XL cmvQ+Y6RsY/GLJU2K2UCJxW/9snuDBWIgUSq51tLUxcQc4tM8wxjYyQbIJau+bNm5z oI+I/YZiPTOQKrn1/OVrXurN2c10xr6JyOZLXzeR/bxU8ANAxJ8GIadB+SKB840EpC wLychapzdplKg== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 05/16] iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys Date: Mon, 4 Aug 2025 15:42:39 +0300 Message-ID: <9186ccefda5ea97b56ec006900127650f9e324b5.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Rename the IOMMU DMA mapping functions to better reflect their actual calling convention. The functions iommu_dma_map_page() and iommu_dma_unmap_page() are renamed to iommu_dma_map_phys() and iommu_dma_unmap_phys() respectively, as they already operate on physical addresses rather than page structures. The calling convention changes from accepting (struct page *page, unsigned long offset) to (phys_addr_t phys), which eliminates the need for page-to-physical address conversion within the functions. This renaming prepares for the broader DMA API conversion from page-based to physical address-based mapping throughout the kernel. All callers are updated to pass physical addresses directly, including dma_map_page_attrs(), scatterlist mapping functions, and DMA page allocation helpers. The change simplifies the code by removing the page_to_phys() + offset calculation that was previously done inside the IOMMU functions. Signed-off-by: Leon Romanovsky --- drivers/iommu/dma-iommu.c | 14 ++++++-------- include/linux/iommu-dma.h | 7 +++---- kernel/dma/mapping.c | 4 ++-- kernel/dma/ops_helpers.c | 6 +++--- 4 files changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 399838c17b705..11c5d5f8c0981 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -1190,11 +1190,9 @@ static inline size_t iova_unaligned(struct iova_domain *iovad, phys_addr_t phys, return iova_offset(iovad, phys | size); } -dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, enum dma_data_direction dir, - unsigned long attrs) +dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, + enum dma_data_direction dir, unsigned long attrs) { - phys_addr_t phys = page_to_phys(page) + offset; bool coherent = dev_is_dma_coherent(dev); int prot = dma_info_to_prot(dir, coherent, attrs); struct iommu_domain *domain = iommu_get_dma_domain(dev); @@ -1222,7 +1220,7 @@ dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page, return iova; } -void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle, +void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir, unsigned long attrs) { struct iommu_domain *domain = iommu_get_dma_domain(dev); @@ -1341,7 +1339,7 @@ static void iommu_dma_unmap_sg_swiotlb(struct device *dev, struct scatterlist *s int i; for_each_sg(sg, s, nents, i) - iommu_dma_unmap_page(dev, sg_dma_address(s), + iommu_dma_unmap_phys(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); } @@ -1354,8 +1352,8 @@ static int iommu_dma_map_sg_swiotlb(struct device *dev, struct scatterlist *sg, sg_dma_mark_swiotlb(sg); for_each_sg(sg, s, nents, i) { - sg_dma_address(s) = iommu_dma_map_page(dev, sg_page(s), - s->offset, s->length, dir, attrs); + sg_dma_address(s) = iommu_dma_map_phys(dev, sg_phys(s), + s->length, dir, attrs); if (sg_dma_address(s) == DMA_MAPPING_ERROR) goto out_unmap; sg_dma_len(s) = s->length; diff --git a/include/linux/iommu-dma.h b/include/linux/iommu-dma.h index 508beaa44c39e..485bdffed9888 100644 --- a/include/linux/iommu-dma.h +++ b/include/linux/iommu-dma.h @@ -21,10 +21,9 @@ static inline bool use_dma_iommu(struct device *dev) } #endif /* CONFIG_IOMMU_DMA */ -dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page, - unsigned long offset, size_t size, enum dma_data_direction dir, - unsigned long attrs); -void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle, +dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size, + enum dma_data_direction dir, unsigned long attrs); +void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction dir, unsigned long attrs); int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction dir, unsigned long attrs); diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index fe1f0da6dc507..58482536db9bb 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -169,7 +169,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, arch_dma_map_page_direct(dev, phys + size)) addr = dma_direct_map_page(dev, page, offset, size, dir, attrs); else if (use_dma_iommu(dev)) - addr = iommu_dma_map_page(dev, page, offset, size, dir, attrs); + addr = iommu_dma_map_phys(dev, phys, size, dir, attrs); else addr = ops->map_page(dev, page, offset, size, dir, attrs); kmsan_handle_dma(page, offset, size, dir); @@ -190,7 +190,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size, arch_dma_unmap_page_direct(dev, addr + size)) dma_direct_unmap_page(dev, addr, size, dir, attrs); else if (use_dma_iommu(dev)) - iommu_dma_unmap_page(dev, addr, size, dir, attrs); + iommu_dma_unmap_phys(dev, addr, size, dir, attrs); else ops->unmap_page(dev, addr, size, dir, attrs); trace_dma_unmap_phys(dev, addr, size, dir, attrs); diff --git a/kernel/dma/ops_helpers.c b/kernel/dma/ops_helpers.c index 9afd569eadb96..6f9d604d9d406 100644 --- a/kernel/dma/ops_helpers.c +++ b/kernel/dma/ops_helpers.c @@ -72,8 +72,8 @@ struct page *dma_common_alloc_pages(struct device *dev, size_t size, return NULL; if (use_dma_iommu(dev)) - *dma_handle = iommu_dma_map_page(dev, page, 0, size, dir, - DMA_ATTR_SKIP_CPU_SYNC); + *dma_handle = iommu_dma_map_phys(dev, page_to_phys(page), size, + dir, DMA_ATTR_SKIP_CPU_SYNC); else *dma_handle = ops->map_page(dev, page, 0, size, dir, DMA_ATTR_SKIP_CPU_SYNC); @@ -92,7 +92,7 @@ void dma_common_free_pages(struct device *dev, size_t size, struct page *page, const struct dma_map_ops *ops = get_dma_ops(dev); if (use_dma_iommu(dev)) - iommu_dma_unmap_page(dev, dma_handle, size, dir, + iommu_dma_unmap_phys(dev, dma_handle, size, dir, DMA_ATTR_SKIP_CPU_SYNC); else if (ops->unmap_page) ops->unmap_page(dev, dma_handle, size, dir, -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:51:33 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:51:33 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069224.1433115 (Exim 4.92) (envelope-from ) id 1uiuf7-00056V-AZ; Mon, 04 Aug 2025 12:51:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069224.1433115; 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Mon, 4 Aug 2025 12:44:08 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b7812cf0-7130-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311449; bh=71zLK4izXOep/KpMivpRm0s6UWtEl8Sf4NUkNJ/aIsU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jbu+qcbqIUowFpCDDbVzU+O+oDab7hCwuZ0M/xHzIA/m0ruu3KAVq7ylLBINY55If bo9Tk+feiAbmQkF4YUkUgIp0MAGQcmiQI/Mcg1NkiXwovDTkgHpeGsJGSuvqbW4nNb 6fzLtf+WmA+A9sS3/Z9a3whJQW3+eizW1avVzK6HdjeWo/DTN9Zhf652jC0OiVqnIx daQ4NzeFJg9jNTgGGI/AIUyWbdPkZPaelF6ZKtGOEKFXm1v4YI2nWf6GfMuCj7zPG3 LWho0rhThFQGEnh+1T8yylTXAtdwgRYiF8Q52vne/vV6b0+WWqLNv/LW3uBlxR2xc1 8NgN+JwChrndA== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 12/16] mm/hmm: migrate to physical address-based DMA mapping API Date: Mon, 4 Aug 2025 15:42:46 +0300 Message-ID: <6d5896c3c1eb4d481b7d49f1eb661f61353bcfdb.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Convert HMM DMA operations from the legacy page-based API to the new physical address-based dma_map_phys() and dma_unmap_phys() functions. This demonstrates the preferred approach for new code that should use physical addresses directly rather than page+offset parameters. The change replaces dma_map_page() and dma_unmap_page() calls with dma_map_phys() and dma_unmap_phys() respectively, using the physical address that was already available in the code. This eliminates the redundant page-to-physical address conversion and aligns with the DMA subsystem's move toward physical address-centric interfaces. This serves as an example of how new code should be written to leverage the more efficient physical address API, which provides cleaner interfaces for drivers that already have access to physical addresses. Signed-off-by: Leon Romanovsky --- mm/hmm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/mm/hmm.c b/mm/hmm.c index d545e24949949..015ab243f0813 100644 --- a/mm/hmm.c +++ b/mm/hmm.c @@ -775,8 +775,8 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map, if (WARN_ON_ONCE(dma_need_unmap(dev) && !dma_addrs)) goto error; - dma_addr = dma_map_page(dev, page, 0, map->dma_entry_size, - DMA_BIDIRECTIONAL); + dma_addr = dma_map_phys(dev, paddr, map->dma_entry_size, + DMA_BIDIRECTIONAL, 0); if (dma_mapping_error(dev, dma_addr)) goto error; @@ -819,8 +819,8 @@ bool hmm_dma_unmap_pfn(struct device *dev, struct hmm_dma_map *map, size_t idx) dma_iova_unlink(dev, state, idx * map->dma_entry_size, map->dma_entry_size, DMA_BIDIRECTIONAL, attrs); } else if (dma_need_unmap(dev)) - dma_unmap_page(dev, dma_addrs[idx], map->dma_entry_size, - DMA_BIDIRECTIONAL); + dma_unmap_phys(dev, dma_addrs[idx], map->dma_entry_size, + DMA_BIDIRECTIONAL, 0); pfns[idx] &= ~(HMM_PFN_DMA_MAPPED | HMM_PFN_P2PDMA | HMM_PFN_P2PDMA_BUS); -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:51:49 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:51:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069246.1433126 (Exim 4.92) (envelope-from ) id 1uiufN-00069a-KQ; Mon, 04 Aug 2025 12:51:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069246.1433126; Mon, 04 Aug 2025 12:51:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiufN-00068j-Gl; Mon, 04 Aug 2025 12:51:49 +0000 Received: by outflank-mailman (input) for mailman id 1069246; Mon, 04 Aug 2025 12:51:48 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuY9-0006VD-Og for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:44:21 +0000 Received: from dfw.source.kernel.org (dfw.source.kernel.org [2604:1380:4641:c500::1]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id bd6de160-7130-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 14:44:20 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 1404A5C5F2E; Mon, 4 Aug 2025 12:44:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D4569C4CEE7; Mon, 4 Aug 2025 12:44:17 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bd6de160-7130-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311458; bh=dqwhbGWVl/oipogVPAPlJyJScmypxjmriuJlNMDqMFM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=twziXknBPqQkaMb4B7FpNHJ9HEUx7/M836/B/HOkWAaI0xU18AOGgranE1UPO3Z2A qByqLoklhRYu6bnu+x5ETVJIc+P+0Ju1mUTlWesgsxm9Uw2nnAUHgWFFcvipLZWsPr /X/Xgc0MrjwXWJE2eE8R2nPmVwtK2NoWOETrJzuVA7cF2pqqQw7TPbh3FX3McEN3on SLv84u5z+pYu1j0JRSH5twhBbzvn9nXehFR206rnivCVd5lTNcN4IpS/pX3K4gEYJR R30yvtOo8vlSCBPCeQNV8Tbj18sYkV187LjgCJFMSIphAwqv5UYBAvrh/Sqr87dLeL XA2ufQWKM0AXg== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 13/16] mm/hmm: properly take MMIO path Date: Mon, 4 Aug 2025 15:42:47 +0300 Message-ID: <79cf36301cc05d6dd1c88e9c3812ac5c3f57e32b.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky In case peer-to-peer transaction traverses through host bridge, the IOMMU needs to have IOMMU_MMIO flag, together with skip of CPU sync. The latter was handled by provided DMA_ATTR_SKIP_CPU_SYNC flag, but IOMMU flag was missed, due to assumption that such memory can be treated as regular one. Reuse newly introduced DMA attribute to properly take MMIO path. Signed-off-by: Leon Romanovsky --- mm/hmm.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/mm/hmm.c b/mm/hmm.c index 015ab243f0813..6556c0e074ba8 100644 --- a/mm/hmm.c +++ b/mm/hmm.c @@ -746,7 +746,7 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map, case PCI_P2PDMA_MAP_NONE: break; case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE: - attrs |= DMA_ATTR_SKIP_CPU_SYNC; + attrs |= DMA_ATTR_MMIO; pfns[idx] |= HMM_PFN_P2PDMA; break; case PCI_P2PDMA_MAP_BUS_ADDR: @@ -776,7 +776,7 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map, goto error; dma_addr = dma_map_phys(dev, paddr, map->dma_entry_size, - DMA_BIDIRECTIONAL, 0); + DMA_BIDIRECTIONAL, attrs); if (dma_mapping_error(dev, dma_addr)) goto error; @@ -811,16 +811,17 @@ bool hmm_dma_unmap_pfn(struct device *dev, struct hmm_dma_map *map, size_t idx) if ((pfns[idx] & valid_dma) != valid_dma) return false; + if (pfns[idx] & HMM_PFN_P2PDMA) + attrs |= DMA_ATTR_MMIO; + if (pfns[idx] & HMM_PFN_P2PDMA_BUS) ; /* no need to unmap bus address P2P mappings */ - else if (dma_use_iova(state)) { - if (pfns[idx] & HMM_PFN_P2PDMA) - attrs |= DMA_ATTR_SKIP_CPU_SYNC; + else if (dma_use_iova(state)) dma_iova_unlink(dev, state, idx * map->dma_entry_size, map->dma_entry_size, DMA_BIDIRECTIONAL, attrs); - } else if (dma_need_unmap(dev)) + else if (dma_need_unmap(dev)) dma_unmap_phys(dev, dma_addrs[idx], map->dma_entry_size, - DMA_BIDIRECTIONAL, 0); + DMA_BIDIRECTIONAL, attrs); pfns[idx] &= ~(HMM_PFN_DMA_MAPPED | HMM_PFN_P2PDMA | HMM_PFN_P2PDMA_BUS); -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:51:52 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:51:52 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069256.1433136 (Exim 4.92) (envelope-from ) id 1uiufQ-0006Zj-TH; Mon, 04 Aug 2025 12:51:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069256.1433136; Mon, 04 Aug 2025 12:51:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiufQ-0006ZZ-PR; Mon, 04 Aug 2025 12:51:52 +0000 Received: by outflank-mailman (input) for mailman id 1069256; Mon, 04 Aug 2025 12:51:51 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuXt-0006V7-PH for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:44:05 +0000 Received: from sea.source.kernel.org (sea.source.kernel.org [172.234.252.31]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id b19df0c1-7130-11f0-b898-0df219b8e170; Mon, 04 Aug 2025 14:44:01 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id BB55A43C23; Mon, 4 Aug 2025 12:43:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 82117C4CEF8; Mon, 4 Aug 2025 12:43:58 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b19df0c1-7130-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311439; bh=KD5XpS99kfAtzNwNr0G2cKeknKa6uIV3HkFwkgt52Og=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=REzkJIVPP9gFnq006IpzWA33deEBq3gq/L07hYxS4b9Co9lY/j51ovFGlZKxGO1e5 4+8sYBN0i9v9K0mgKzmZ/QHCuA9Q46V87wtCzHKFC0ANzBr9PuysZxQhOrNozb4Qyk VihVy8omfI8O2IRdV4Tyl6d0KjHEM3acEvXoNbj8+O8OXRRPHQMKadb9piVN0E1Wap K/UpRFgSWAcvtvvkCiTXu1nv84wDzdAsa9r8/C/wTH34YjDjAVJPlKm4jsTlVi+zRC U+eUEQKpw0KzkD87pD1mxwxAbEEaEpX1KJV4/DAHcK3vw7alfBmL84qIH19KHyRx/5 kND7FSCrGya4g== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 08/16] kmsan: convert kmsan_handle_dma to use physical addresses Date: Mon, 4 Aug 2025 15:42:42 +0300 Message-ID: <5b40377b621e49ff4107fa10646c828ccc94e53e.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Convert the KMSAN DMA handling function from page-based to physical address-based interface. The refactoring renames kmsan_handle_dma() parameters from accepting (struct page *page, size_t offset, size_t size) to (phys_addr_t phys, size_t size). A PFN_VALID check is added to prevent KMSAN operations on non-page memory, preventing from non struct page backed address, As part of this change, support for highmem addresses is implemented using kmap_local_page() to handle both lowmem and highmem regions properly. All callers throughout the codebase are updated to use the new phys_addr_t based interface. Signed-off-by: Leon Romanovsky --- drivers/virtio/virtio_ring.c | 4 ++-- include/linux/kmsan.h | 12 +++++++----- kernel/dma/mapping.c | 2 +- mm/kmsan/hooks.c | 36 +++++++++++++++++++++++++++++------- tools/virtio/linux/kmsan.h | 2 +- 5 files changed, 40 insertions(+), 16 deletions(-) diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index f5062061c4084..c147145a65930 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -378,7 +378,7 @@ static int vring_map_one_sg(const struct vring_virtqueue *vq, struct scatterlist * is initialized by the hardware. Explicitly check/unpoison it * depending on the direction. */ - kmsan_handle_dma(sg_page(sg), sg->offset, sg->length, direction); + kmsan_handle_dma(sg_phys(sg), sg->length, direction); *addr = (dma_addr_t)sg_phys(sg); return 0; } @@ -3157,7 +3157,7 @@ dma_addr_t virtqueue_dma_map_single_attrs(struct virtqueue *_vq, void *ptr, struct vring_virtqueue *vq = to_vvq(_vq); if (!vq->use_dma_api) { - kmsan_handle_dma(virt_to_page(ptr), offset_in_page(ptr), size, dir); + kmsan_handle_dma(virt_to_phys(ptr), size, dir); return (dma_addr_t)virt_to_phys(ptr); } diff --git a/include/linux/kmsan.h b/include/linux/kmsan.h index 2b1432cc16d59..6f27b9824ef77 100644 --- a/include/linux/kmsan.h +++ b/include/linux/kmsan.h @@ -182,8 +182,7 @@ void kmsan_iounmap_page_range(unsigned long start, unsigned long end); /** * kmsan_handle_dma() - Handle a DMA data transfer. - * @page: first page of the buffer. - * @offset: offset of the buffer within the first page. + * @phys: physical address of the buffer. * @size: buffer size. * @dir: one of possible dma_data_direction values. * @@ -191,8 +190,11 @@ void kmsan_iounmap_page_range(unsigned long start, unsigned long end); * * checks the buffer, if it is copied to device; * * initializes the buffer, if it is copied from device; * * does both, if this is a DMA_BIDIRECTIONAL transfer. + * + * The function handles page lookup internally and supports both lowmem + * and highmem addresses. */ -void kmsan_handle_dma(struct page *page, size_t offset, size_t size, +void kmsan_handle_dma(phys_addr_t phys, size_t size, enum dma_data_direction dir); /** @@ -372,8 +374,8 @@ static inline void kmsan_iounmap_page_range(unsigned long start, { } -static inline void kmsan_handle_dma(struct page *page, size_t offset, - size_t size, enum dma_data_direction dir) +static inline void kmsan_handle_dma(phys_addr_t phys, size_t size, + enum dma_data_direction dir) { } diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index 80481a873340a..709405d46b2b4 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -172,7 +172,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page, addr = iommu_dma_map_phys(dev, phys, size, dir, attrs); else addr = ops->map_page(dev, page, offset, size, dir, attrs); - kmsan_handle_dma(page, offset, size, dir); + kmsan_handle_dma(phys, size, dir); trace_dma_map_phys(dev, phys, addr, size, dir, attrs); debug_dma_map_phys(dev, phys, size, dir, addr, attrs); diff --git a/mm/kmsan/hooks.c b/mm/kmsan/hooks.c index 97de3d6194f07..eab7912a3bf05 100644 --- a/mm/kmsan/hooks.c +++ b/mm/kmsan/hooks.c @@ -336,25 +336,48 @@ static void kmsan_handle_dma_page(const void *addr, size_t size, } /* Helper function to handle DMA data transfers. */ -void kmsan_handle_dma(struct page *page, size_t offset, size_t size, +void kmsan_handle_dma(phys_addr_t phys, size_t size, enum dma_data_direction dir) { u64 page_offset, to_go, addr; + struct page *page; + void *kaddr; - if (PageHighMem(page)) + if (!pfn_valid(PHYS_PFN(phys))) return; - addr = (u64)page_address(page) + offset; + + page = phys_to_page(phys); + page_offset = offset_in_page(phys); + /* * The kernel may occasionally give us adjacent DMA pages not belonging * to the same allocation. Process them separately to avoid triggering * internal KMSAN checks. */ while (size > 0) { - page_offset = offset_in_page(addr); to_go = min(PAGE_SIZE - page_offset, (u64)size); + + if (PageHighMem(page)) + /* Handle highmem pages using kmap */ + kaddr = kmap_local_page(page); + else + /* Lowmem pages can be accessed directly */ + kaddr = page_address(page); + + addr = (u64)kaddr + page_offset; kmsan_handle_dma_page((void *)addr, to_go, dir); - addr += to_go; + + if (PageHighMem(page)) + kunmap_local(page); + + phys += to_go; size -= to_go; + + /* Move to next page if needed */ + if (size > 0) { + page = phys_to_page(phys); + page_offset = offset_in_page(phys); + } } } EXPORT_SYMBOL_GPL(kmsan_handle_dma); @@ -366,8 +389,7 @@ void kmsan_handle_dma_sg(struct scatterlist *sg, int nents, int i; for_each_sg(sg, item, nents, i) - kmsan_handle_dma(sg_page(item), item->offset, item->length, - dir); + kmsan_handle_dma(sg_phys(item), item->length, dir); } /* Functions from kmsan-checks.h follow. */ diff --git a/tools/virtio/linux/kmsan.h b/tools/virtio/linux/kmsan.h index 272b5aa285d5a..6cd2e3efd03dc 100644 --- a/tools/virtio/linux/kmsan.h +++ b/tools/virtio/linux/kmsan.h @@ -4,7 +4,7 @@ #include -inline void kmsan_handle_dma(struct page *page, size_t offset, size_t size, +inline void kmsan_handle_dma(phys_addr_t phys, size_t size, enum dma_data_direction dir) { } -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:52:45 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:52:45 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069273.1433145 (Exim 4.92) (envelope-from ) id 1uiugG-00080F-AU; Mon, 04 Aug 2025 12:52:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069273.1433145; Mon, 04 Aug 2025 12:52:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiugG-000808-7V; Mon, 04 Aug 2025 12:52:44 +0000 Received: by outflank-mailman (input) for mailman id 1069273; Mon, 04 Aug 2025 12:52:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuYM-0006VD-En for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:44:34 +0000 Received: from nyc.source.kernel.org (nyc.source.kernel.org [147.75.193.91]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id c5682827-7130-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 14:44:33 +0200 (CEST) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 10CE7A5586C; Mon, 4 Aug 2025 12:44:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DBBA4C4CEE7; Mon, 4 Aug 2025 12:44:31 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c5682827-7130-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311472; bh=Aje2MY5jLtJJ+XC6L21HodqK1MreNzlcX3KM+Qptt24=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D+O9BFW9G3EUN02UNr+9W1wRCdRDfRkf0x3nKVoSKF3qgFSYQkjSJdutDyO+/GaXc LGLcj33SDyJqVULCEM37MXdFVYsGALxSAZY0nHbzSQZTnFerxjcv8C6TboBXWH4naX 6ZVZnkDzbfO3eKo22J8zcBZLzmo4T9kxSkmi7f07Z+UGaRwrQIMopajJOg4vYfLx6+ jnSQUAfHfWhVCjNaPp3bPAtogKMoVHj2Hvn4dfigZthAzfffhOXJp1Yoe3nvVjUnC/ ShnNJR9ewOfC+QlOtWiwtM5Xx2GVbLWurX258r+SmOzIeAJTmd4uYs98RHNcdlwqdj Y4q80UzvzmD6g== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 15/16] block-dma: properly take MMIO path Date: Mon, 4 Aug 2025 15:42:49 +0300 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Make sure that CPU is not synced and IOMMU is configured to take MMIO path by providing newly introduced DMA_ATTR_MMIO attribute. Signed-off-by: Leon Romanovsky --- block/blk-mq-dma.c | 13 +++++++++++-- include/linux/blk-mq-dma.h | 6 +++++- include/linux/blk_types.h | 2 ++ 3 files changed, 18 insertions(+), 3 deletions(-) diff --git a/block/blk-mq-dma.c b/block/blk-mq-dma.c index 37e2142be4f7d..d415088ed9fd2 100644 --- a/block/blk-mq-dma.c +++ b/block/blk-mq-dma.c @@ -87,8 +87,13 @@ static bool blk_dma_map_bus(struct blk_dma_iter *iter, struct phys_vec *vec) static bool blk_dma_map_direct(struct request *req, struct device *dma_dev, struct blk_dma_iter *iter, struct phys_vec *vec) { + unsigned int attrs = 0; + + if (req->cmd_flags & REQ_MMIO) + attrs = DMA_ATTR_MMIO; + iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len, - rq_dma_dir(req), 0); + rq_dma_dir(req), attrs); if (dma_mapping_error(dma_dev, iter->addr)) { iter->status = BLK_STS_RESOURCE; return false; @@ -103,14 +108,17 @@ static bool blk_rq_dma_map_iova(struct request *req, struct device *dma_dev, { enum dma_data_direction dir = rq_dma_dir(req); unsigned int mapped = 0; + unsigned int attrs = 0; int error; iter->addr = state->addr; iter->len = dma_iova_size(state); + if (req->cmd_flags & REQ_MMIO) + attrs = DMA_ATTR_MMIO; do { error = dma_iova_link(dma_dev, state, vec->paddr, mapped, - vec->len, dir, 0); + vec->len, dir, attrs); if (error) break; mapped += vec->len; @@ -176,6 +184,7 @@ bool blk_rq_dma_map_iter_start(struct request *req, struct device *dma_dev, * same as non-P2P transfers below and during unmap. */ req->cmd_flags &= ~REQ_P2PDMA; + req->cmd_flags |= REQ_MMIO; break; default: iter->status = BLK_STS_INVAL; diff --git a/include/linux/blk-mq-dma.h b/include/linux/blk-mq-dma.h index c26a01aeae006..6c55f5e585116 100644 --- a/include/linux/blk-mq-dma.h +++ b/include/linux/blk-mq-dma.h @@ -48,12 +48,16 @@ static inline bool blk_rq_dma_map_coalesce(struct dma_iova_state *state) static inline bool blk_rq_dma_unmap(struct request *req, struct device *dma_dev, struct dma_iova_state *state, size_t mapped_len) { + unsigned int attrs = 0; + if (req->cmd_flags & REQ_P2PDMA) return true; if (dma_use_iova(state)) { + if (req->cmd_flags & REQ_MMIO) + attrs = DMA_ATTR_MMIO; dma_iova_destroy(dma_dev, state, mapped_len, rq_dma_dir(req), - 0); + attrs); return true; } diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h index 09b99d52fd365..283058bcb5b14 100644 --- a/include/linux/blk_types.h +++ b/include/linux/blk_types.h @@ -387,6 +387,7 @@ enum req_flag_bits { __REQ_FS_PRIVATE, /* for file system (submitter) use */ __REQ_ATOMIC, /* for atomic write operations */ __REQ_P2PDMA, /* contains P2P DMA pages */ + __REQ_MMIO, /* contains MMIO memory */ /* * Command specific flags, keep last: */ @@ -420,6 +421,7 @@ enum req_flag_bits { #define REQ_FS_PRIVATE (__force blk_opf_t)(1ULL << __REQ_FS_PRIVATE) #define REQ_ATOMIC (__force blk_opf_t)(1ULL << __REQ_ATOMIC) #define REQ_P2PDMA (__force blk_opf_t)(1ULL << __REQ_P2PDMA) +#define REQ_MMIO (__force blk_opf_t)(1ULL << __REQ_MMIO) #define REQ_NOUNMAP (__force blk_opf_t)(1ULL << __REQ_NOUNMAP) -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:53:00 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:53:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069277.1433156 (Exim 4.92) (envelope-from ) id 1uiugW-0008U7-JI; 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Mon, 4 Aug 2025 12:44:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 16A0CC4CEE7; Mon, 4 Aug 2025 12:44:27 +0000 (UTC) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c2bd95cf-7130-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754311468; bh=6qGcHzBt0dZoqM7CuRvm64zWhofh7owUAL+fgH12bgM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QrNeSbr2ETjZG5USk2ip6Q5L+o73xniNPTNqJfZmeQ0KuyCuSNG0LJiusWyclzjKr cFFoKUr822PG8QqKCLTd5BeFqtuT5Wy83EgwLas9lgxaOVGp8D6uZ1DZl2tq1dbKx/ L+omTL0ofNOzbXoE9fyZGuqE2CSvotiwsuOKLhXV08+L7k2MaQEDPsb6OddrmQRn4z PSjtn3F5+SFZ4HUEL0cLcskl4nbzTgDtlLNFq79lO3atdeVNqKCn/0JzVgj9R/u+Y+ m0zCkfJHRbZiqlPJoau9al8Hd9lK5yTnnQg10fAI/hDh0sKrsDMMIbG+18uzswU+JQ 8ketKVA4tFFWQ== From: Leon Romanovsky To: Marek Szyprowski Cc: Leon Romanovsky , Jason Gunthorpe , Abdiel Janulgue , Alexander Potapenko , Alex Gaynor , Andrew Morton , Christoph Hellwig , Danilo Krummrich , iommu@lists.linux.dev, Jason Wang , Jens Axboe , Joerg Roedel , Jonathan Corbet , Juergen Gross , kasan-dev@googlegroups.com, Keith Busch , linux-block@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan , Masami Hiramatsu , Michael Ellerman , "Michael S. Tsirkin" , Miguel Ojeda , Robin Murphy , rust-for-linux@vger.kernel.org, Sagi Grimberg , Stefano Stabellini , Steven Rostedt , virtualization@lists.linux.dev, Will Deacon , xen-devel@lists.xenproject.org Subject: [PATCH v1 16/16] nvme-pci: unmap MMIO pages with appropriate interface Date: Mon, 4 Aug 2025 15:42:50 +0300 Message-ID: <5b0131f82a3d14acaa85f0d1dd608d2913af84e2.1754292567.git.leon@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Leon Romanovsky Block layer maps MMIO memory through dma_map_phys() interface with help of DMA_ATTR_MMIO attribute. There is a need to unmap that memory with the appropriate unmap function. Signed-off-by: Leon Romanovsky --- drivers/nvme/host/pci.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index 071efec25346f..0b624247948c5 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -682,11 +682,15 @@ static void nvme_free_prps(struct request *req) { struct nvme_iod *iod = blk_mq_rq_to_pdu(req); struct nvme_queue *nvmeq = req->mq_hctx->driver_data; + unsigned int attrs = 0; unsigned int i; + if (req->cmd_flags & REQ_MMIO) + attrs = DMA_ATTR_MMIO; + for (i = 0; i < iod->nr_dma_vecs; i++) - dma_unmap_page(nvmeq->dev->dev, iod->dma_vecs[i].addr, - iod->dma_vecs[i].len, rq_dma_dir(req)); + dma_unmap_phys(nvmeq->dev->dev, iod->dma_vecs[i].addr, + iod->dma_vecs[i].len, rq_dma_dir(req), attrs); mempool_free(iod->dma_vecs, nvmeq->dev->dmavec_mempool); } @@ -699,15 +703,19 @@ static void nvme_free_sgls(struct request *req) unsigned int sqe_dma_len = le32_to_cpu(iod->cmd.common.dptr.sgl.length); struct nvme_sgl_desc *sg_list = iod->descriptors[0]; enum dma_data_direction dir = rq_dma_dir(req); + unsigned int attrs = 0; + + if (req->cmd_flags & REQ_MMIO) + attrs = DMA_ATTR_MMIO; if (iod->nr_descriptors) { unsigned int nr_entries = sqe_dma_len / sizeof(*sg_list), i; for (i = 0; i < nr_entries; i++) - dma_unmap_page(dma_dev, le64_to_cpu(sg_list[i].addr), - le32_to_cpu(sg_list[i].length), dir); + dma_unmap_phys(dma_dev, le64_to_cpu(sg_list[i].addr), + le32_to_cpu(sg_list[i].length), dir, attrs); } else { - dma_unmap_page(dma_dev, sqe_dma_addr, sqe_dma_len, dir); + dma_unmap_phys(dma_dev, sqe_dma_addr, sqe_dma_len, dir, attrs); } } -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:56:47 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:56:47 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069289.1433165 (Exim 4.92) (envelope-from ) id 1uiuk7-0000qY-2d; Mon, 04 Aug 2025 12:56:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069289.1433165; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 12:56:34.1386 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ada36b5d-2fae-4ef3-51b3-08ddd356574d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9515 Hi Hari, On 30/07/2025 09:45, Hari Limaye wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > From: Luca Fancellu > > Add a scheme to distinguish transient MPU regions, to identify MPU > regions which will be mapped for a short period of time. > > Signed-off-by: Luca Fancellu > Signed-off-by: Hari Limaye Reviewed-by: Ayan Kumar Halder Tested-by: Ayan Kumar Halder (On R82 and R52 with some additional patches) - Ayan From xen-devel-bounces@lists.xenproject.org Mon Aug 04 12:59:59 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 12:59:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069297.1433176 (Exim 4.92) (envelope-from ) id 1uiunG-0001PC-Gs; Mon, 04 Aug 2025 12:59:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069297.1433176; Mon, 04 Aug 2025 12:59:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiunG-0001P5-Dy; Mon, 04 Aug 2025 12:59:58 +0000 Received: by outflank-mailman (input) for mailman id 1069297; Mon, 04 Aug 2025 12:59:57 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiunF-0001Oz-Dh for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 12:59:57 +0000 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [2a00:1450:4864:20::634]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id eb478c6c-7132-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 14:59:55 +0200 (CEST) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-af967835d0aso158910766b.0 for ; Mon, 04 Aug 2025 05:59:55 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Smith" , xen-devel@lists.xenproject.org References: <20250803094738.3625269-1-Penny.Zheng@amd.com> <20250803094738.3625269-5-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250803094738.3625269-5-Penny.Zheng@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 03.08.2025 11:47, Penny Zheng wrote: > File hvm/vm_event.c and x86/vm_event.c are the extend to vm_event handling > routines, and its compilation shall be guarded by CONFIG_VM_EVENT too. > Futhermore, features about monitor_op and memory access are both based on > vm event subsystem, so monitor.o/mem_access.o shall be wrapped under > CONFIG_VM_EVENT. > > Although CONFIG_VM_EVENT is forcibly enabled on x86, we could disable it > through disabling CONFIG_DOMCTL in the future. > In consequence, a few functions, like the ones defined in hvm/monitor.h, > needs stub to pass compilation when CONFIG_VM_EVENT=n. > Remove the CONFIG_VM_EVENT wrapper for "#include ", as > we need declaration there to pass compilation when CONFIG_VM_EVENT=n > > The following functions are developed on the basis of vm event framework, or > only invoked by vm_event.c/monitor.c/mem_access.c, so they all shall be > wrapped with CONFIG_VM_EVENT: > - hvm_toggle_singlestep > - hvm_fast_singlestep > - p2m_mem_paging_drop_page > - p2m_mem_paging_populate_page > - p2m_mem_paging_resume > - hvm_enable_msr_interception > - hvm_function_table.enable_msr_interception > - hvm_has_set_descriptor_access_existing > - hvm_function_table.set_descriptor_access_existing > - xsm_vm_event_control > > Signed-off-by: Penny Zheng > --- > xen/arch/ppc/stubs.c | 2 + > xen/arch/x86/Makefile | 2 +- > xen/arch/x86/hvm/Makefile | 4 +- > xen/arch/x86/hvm/hvm.c | 2 + > xen/arch/x86/hvm/svm/svm.c | 8 +++ > xen/arch/x86/hvm/vmx/vmx.c | 10 ++++ > xen/arch/x86/include/asm/hvm/hvm.h | 10 ++++ > xen/arch/x86/include/asm/hvm/monitor.h | 65 ++++++++++++++++++++++++- > xen/arch/x86/include/asm/hvm/vm_event.h | 4 ++ > xen/arch/x86/include/asm/mem_access.h | 9 ++++ > xen/arch/x86/include/asm/monitor.h | 15 ++++++ > xen/arch/x86/include/asm/p2m.h | 6 +++ > xen/arch/x86/mm/mem_paging.c | 2 + > xen/include/xen/mem_access.h | 36 ++++++++++++-- > xen/include/xen/monitor.h | 8 ++- > xen/include/xen/vm_event.h | 24 ++++++++- > xen/include/xsm/xsm.h | 4 +- > xen/xsm/dummy.c | 2 +- > xen/xsm/flask/hooks.c | 4 +- > 19 files changed, 200 insertions(+), 17 deletions(-) Overall it looks like the patch could be split some. E.g. the XSM changes look as if they could go separately. > --- a/xen/arch/ppc/stubs.c > +++ b/xen/arch/ppc/stubs.c > @@ -60,6 +60,7 @@ void vcpu_show_execution_state(struct vcpu *v) > BUG_ON("unimplemented"); > } > > +#ifdef CONFIG_VM_EVENT > /* vm_event.c */ > > void vm_event_fill_regs(vm_event_request_t *req) > @@ -76,6 +77,7 @@ void vm_event_monitor_next_interrupt(struct vcpu *v) > { > /* Not supported on PPC. */ > } > +#endif /* CONFIG_VM_EVENT */ Is this really needed? I wouldn't bother editing stubs.c files unless really necessary. > --- a/xen/arch/x86/include/asm/monitor.h > +++ b/xen/arch/x86/include/asm/monitor.h > @@ -71,6 +71,7 @@ int arch_monitor_domctl_op(struct domain *d, struct xen_domctl_monitor_op *mop) > return rc; > } > > +#ifdef CONFIG_VM_EVENT > static inline uint32_t arch_monitor_get_capabilities(struct domain *d) > { > uint32_t capabilities = 0; > @@ -102,6 +103,13 @@ static inline uint32_t arch_monitor_get_capabilities(struct domain *d) > > return capabilities; > } > +#else > +static inline uint32_t arch_monitor_get_capabilities(struct domain *d) > +{ > + ASSERT_UNREACHABLE(); > + return 0; > +} Instead of this, a mere declaration (with no definition) would make a possible problem known at build time, rather than only at runtime. > --- a/xen/arch/x86/include/asm/p2m.h > +++ b/xen/arch/x86/include/asm/p2m.h > @@ -775,10 +775,16 @@ static inline int relinquish_p2m_mapping(struct domain *d) > /* Modify p2m table for shared gfn */ > int set_shared_p2m_entry(struct domain *d, unsigned long gfn, mfn_t mfn); > > +#ifdef CONFIG_VM_EVENT > /* Tell xenpaging to drop a paged out frame */ > void p2m_mem_paging_drop_page(struct domain *d, gfn_t gfn, p2m_type_t p2mt); > /* Start populating a paged out frame */ > void p2m_mem_paging_populate(struct domain *d, gfn_t gfn); > +#else > +static inline void p2m_mem_paging_drop_page(struct domain *d, gfn_t gfn, > + p2m_type_t p2mt) {} This, I think, isn't needed. p2m_is_paging() is already short-circuited into 0 / false when MEM_PAGING=n (implying VM_EVENT=n in your supposed future configuration, so the call site is being DCE-ed, and hence the declaration that was already there will suffice. > --- a/xen/arch/x86/mm/mem_paging.c > +++ b/xen/arch/x86/mm/mem_paging.c > @@ -15,6 +15,7 @@ > > #include "mm-locks.h" > > +#ifdef CONFIG_VM_EVENT > /* > * p2m_mem_paging_drop_page - Tell pager to drop its reference to a paged page > * @d: guest domain > @@ -186,6 +187,7 @@ void p2m_mem_paging_resume(struct domain *d, vm_event_response_t *rsp) > gfn_unlock(p2m, gfn, 0); > } > } > +#endif /* CONFIG_VM_EVENT */ As per the previous remark: Why would this be needed? We already have obj-$(CONFIG_MEM_PAGING) += mem_paging.o in the corresponding Makefile. > --- a/xen/include/xen/mem_access.h > +++ b/xen/include/xen/mem_access.h > @@ -33,9 +33,7 @@ > */ > struct vm_event_st; > > -#ifdef CONFIG_VM_EVENT > #include > -#endif Why? > @@ -73,6 +71,7 @@ typedef enum { > /* NOTE: Assumed to be only 4 bits right now on x86. */ > } p2m_access_t; > > +#ifdef CONFIG_VM_EVENT > struct p2m_domain; > bool xenmem_access_to_p2m_access(const struct p2m_domain *p2m, > xenmem_access_t xaccess, > @@ -99,10 +98,41 @@ long p2m_set_mem_access_multi(struct domain *d, > int p2m_get_mem_access(struct domain *d, gfn_t gfn, xenmem_access_t *access, > unsigned int altp2m_idx); > > -#ifdef CONFIG_VM_EVENT > int mem_access_memop(unsigned long cmd, > XEN_GUEST_HANDLE_PARAM(xen_mem_access_op_t) arg); > #else > +struct p2m_domain; No point in duplicating this; just move it ahead of the #ifdef. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 12:52:19.5834 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97cd5dcf-0003-4eeb-6d1c-08ddd355bfa1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8648 Hi Hari, On 30/07/2025 09:45, Hari Limaye wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > From: Luca Fancellu > > Implement `setup_mm` for MPU systems. This variant doesn't need to set > up the direct map. > > Signed-off-by: Luca Fancellu > Signed-off-by: Hari Limaye Reviewed-by: Ayan Kumarb Halder Tested-by: Ayan Kumarb Halder (On R82 and R52 with some additional patches) - Ayan From xen-devel-bounces@lists.xenproject.org Mon Aug 04 13:04:03 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 13:04:03 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069323.1433196 (Exim 4.92) (envelope-from ) id 1uiur9-0003nA-BF; Mon, 04 Aug 2025 13:03:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069323.1433196; Mon, 04 Aug 2025 13:03:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiur9-0003n3-8Y; Mon, 04 Aug 2025 13:03:59 +0000 Received: by outflank-mailman (input) for mailman id 1069323; Mon, 04 Aug 2025 13:03:58 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiur8-0003mx-6J for xen-devel@lists.xenproject.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 13:03:51.0068 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7281cb1-e082-4af2-534e-08ddd3575bc0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8714 Hi Hari, On 30/07/2025 09:45, Hari Limaye wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > From: Luca Fancellu > > Introduce helpers (un)map_mm_range() in order to allow the temporary > mapping of a range of memory, and use these to implement the function > `ioremap_attr` for MPU systems. > > Signed-off-by: Luca Fancellu > Signed-off-by: Hari Limaye Reviewed-by: Ayan Kumar Halder Tested-by: Ayan Kumar Halder (On R82 and R52 with some additional patches) - Ayan From xen-devel-bounces@lists.xenproject.org Mon Aug 04 13:05:28 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 13:05:28 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069335.1433205 (Exim 4.92) (envelope-from ) id 1uiusZ-0004Xk-KG; Mon, 04 Aug 2025 13:05:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069335.1433205; Mon, 04 Aug 2025 13:05:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiusZ-0004Xd-HY; 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pr=C Message-ID: <4335b725-08fa-4a22-b79b-fb1e22aaa594@amd.com> Date: Mon, 4 Aug 2025 14:05:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] xen/arm: map static memory on demand Content-Language: en-GB To: Hari Limaye , CC: , Penny Zheng , "Stefano Stabellini" , Julien Grall , "Bertrand Marquis" , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , "Jan Beulich" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Wei Chen References: From: Ayan Kumar Halder In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB04.amd.com: ayankuma@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4B:EE_|DM6PR12MB4204:EE_ X-MS-Office365-Filtering-Correlation-Id: 58273b03-883f-4f68-2211-08ddd357909a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|7416014|82310400026|7053199007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 13:05:19.7676 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58273b03-883f-4f68-2211-08ddd357909a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4204 Hi Hari, On 30/07/2025 09:45, Hari Limaye wrote: > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email. > > > From: Penny Zheng > > In the function `init_staticmem_pages` we need to have mapped static > memory banks for initialization. Unlike on an MMU system, we cannot map > the entire RAM on an MPU system as we have a limited number of MPU > memory regions. To solve this, transiently map the static memory banks > for initialization. > > Signed-off-by: Penny Zheng > Signed-off-by: Wei Chen > Signed-off-by: Luca Fancellu > Signed-off-by: Hari Limaye Reviewed-by: Ayan Kumar Halder Tested-by: Ayan Kumar Halder (On R82 and R52 with some additional patches) From xen-devel-bounces@lists.xenproject.org Mon Aug 04 13:06:56 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 13:06:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069354.1433215 (Exim 4.92) (envelope-from ) id 1uiutz-0005PG-0A; Mon, 04 Aug 2025 13:06:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069354.1433215; Mon, 04 Aug 2025 13:06:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuty-0005P9-TU; Mon, 04 Aug 2025 13:06:54 +0000 Received: by outflank-mailman (input) for mailman id 1069354; Mon, 04 Aug 2025 13:06:53 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiutx-0005P3-Hr for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 13:06:53 +0000 Received: from rein-hpcbdc09 (unknown [1.6.89.6]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e180481f-7133-11f0-a321-13f23c93f187; Mon, 04 Aug 2025 15:06:50 +0200 (CEST) Received: by rein-hpcbdc09 (Postfix, from userid 1000) id 6AF1380C0979; Mon, 4 Aug 2025 18:36:46 +0530 (IST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e180481f-7133-11f0-a321-13f23c93f187 From: Jahan Murudi To: xen-devel@lists.xenproject.org Cc: Jahan Murudi , Anthony PERARD Subject: [RFC PATCH v3] tools/xentop: Add physical CPU statistics support Date: Mon, 4 Aug 2025 18:36:43 +0530 Message-Id: <20250804130643.1046157-1-jahan.murudi.zg@renesas.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce a new '-p/--pcpus' flag to display physical CPU utilization metrics using xc_interface. This provides hypervisor-level CPU usage insights alongside existing domain statistics. This helps correlate VM resource usage with host CPU load patterns. Changes: - Add pcpu.c/pcpu.h for PCPU stat collection logic - Link against libxenctrl for xc_handle access - Extend CLI with '-p' flag and output formatting - Forward declare xenstat_handle to access xc_handle - Include cleanup for PCPU resources in exit handler Example usage: xentop -p # Shows physical CPU stats xentop -bp # Batch mode xentop -d 1 -p # With different delays Example output with '-p': NAME STATE CPU(%) MEM(%) VCPUS ... Domain-0 -----r 17.0 6.3 8 DomD -----r 767.0 38.1 8 Physical CPU Usage: ┌───────┬────────┠│ Core │ Usage │ ├───────┼────────┤ │ 0 │ 98.1% │ │ ... │ ... │ │ 7 │ 97.3% │ └───────┴────────┘ Signed-off-by: Jahan Murudi --- tools/xentop/Makefile | 5 +- tools/xentop/pcpu.c | 152 ++++++++++++++++++++++++++++++++++++++++++ tools/xentop/pcpu.h | 15 +++++ tools/xentop/xentop.c | 57 ++++++++++------ 4 files changed, 207 insertions(+), 22 deletions(-) create mode 100644 tools/xentop/pcpu.c create mode 100644 tools/xentop/pcpu.h diff --git a/tools/xentop/Makefile b/tools/xentop/Makefile index 70cc2211c5..f514a6f7a8 100644 --- a/tools/xentop/Makefile +++ b/tools/xentop/Makefile @@ -15,6 +15,7 @@ include $(XEN_ROOT)/tools/Rules.mk CFLAGS += -DGCC_PRINTF $(CFLAGS_libxenstat) LDLIBS += $(LDLIBS_libxenstat) $(CURSES_LIBS) $(TINFO_LIBS) $(SOCKET_LIBS) -lm +LDLIBS += $(LDLIBS_libxenctrl) CFLAGS += -DHOST_$(XEN_OS) # Include configure output (config.h) @@ -25,8 +26,8 @@ TARGETS := xentop .PHONY: all all: $(TARGETS) -xentop: xentop.o - $(CC) $(LDFLAGS) -o $@ $< $(LDLIBS) $(APPEND_LDFLAGS) +xentop: xentop.o pcpu.o + $(CC) $(LDFLAGS) -o $@ $^ $(LDLIBS) $(APPEND_LDFLAGS) .PHONY: install install: all diff --git a/tools/xentop/pcpu.c b/tools/xentop/pcpu.c new file mode 100644 index 0000000000..53d6b9c30c --- /dev/null +++ b/tools/xentop/pcpu.c @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include +#include "pcpu.h" + +#define MAX_PCPUS 128 + +typedef struct { + float usage_pct; +} pcpu_stat_t; + +static pcpu_stat_t *pcpu_stats = NULL; +static uint64_t *prev_idle = NULL; +static uint64_t *prev_time = NULL; +static int allocated_pcpus = 0; +static xc_interface *xc_handle = NULL; + +static void report_pcpu_error(const char *context) +{ + fprintf(stderr, "PCPU error: %s (%s)\n", context, strerror(errno)); +} + +int update_pcpu_stats(const struct timeval *now, unsigned int delay_sec) +{ + struct xen_sysctl_cpuinfo info[MAX_PCPUS]; + int detected_cpus = 0; + int ret, i; + uint64_t current_time = (uint64_t)now->tv_sec * 1000000ULL + now->tv_usec; + + if (!xc_handle) { + xc_handle = xc_interface_open(NULL, NULL, 0); + if (!xc_handle) { + report_pcpu_error("xc_interface_open failed"); + return -1; + } + } + + ret = xc_getcpuinfo(xc_handle, MAX_PCPUS, info, &detected_cpus); + if (ret < 0) { + report_pcpu_error("xc_getcpuinfo failed"); + return -1; + } + + /* Allocate/reallocate memory if needed */ + if (!pcpu_stats || detected_cpus > allocated_pcpus) { + pcpu_stat_t *new_stats = realloc(pcpu_stats, + detected_cpus * sizeof(*pcpu_stats)); + if (!new_stats) goto alloc_error; + + uint64_t *new_prev_idle = realloc(prev_idle, + detected_cpus * sizeof(*prev_idle)); + if (!new_prev_idle) { + free(new_stats); + goto alloc_error; + } + + uint64_t *new_prev_time = realloc(prev_time, + detected_cpus * sizeof(*prev_time)); + if (!new_prev_time) { + free(new_stats); + free(new_prev_idle); + goto alloc_error; + } + + pcpu_stats = new_stats; + prev_idle = new_prev_idle; + prev_time = new_prev_time; + allocated_pcpus = detected_cpus; + + /* Initialize new entries */ + for (i = 0; i < detected_cpus; i++) { + prev_idle[i] = info[i].idletime / 1000; /* ns->us */ + prev_time[i] = current_time; + pcpu_stats[i].usage_pct = 0.0; + } + return 0; + } + + /* Calculate CPU usage with delay normalization */ + for (i = 0; i < detected_cpus; i++) { + uint64_t current_idle = info[i].idletime / 1000; + uint64_t idle_diff = current_idle - prev_idle[i]; + uint64_t time_diff = current_time - prev_time[i]; + + /* Use configured delay when actual interval is too small */ + if (time_diff < 100000) { + time_diff = delay_sec * 1000000ULL; + } + + if (time_diff > 0) { + double usage = 100.0 * (1.0 - ((double)idle_diff / time_diff)); + /* Clamp between 0-100% */ + pcpu_stats[i].usage_pct = (usage < 0) ? 0.0 : + (usage > 100) ? 100.0 : usage; + } else { + pcpu_stats[i].usage_pct = 0.0; + } + + prev_idle[i] = current_idle; + prev_time[i] = current_time; + } + + return 0; + +alloc_error: + free_pcpu_stats(); + errno = ENOMEM; + report_pcpu_error("memory allocation failed"); + return -1; +} + +void print_pcpu_stats(void) +{ + if (!pcpu_stats || allocated_pcpus == 0) { + printf("\r\nNo PCPU data available\r\n"); + return; + } + + printf("\r\nPhysical CPU Usage:\r\n"); + printf("+-------+--------+\r\n"); + printf("| Core | Usage |\r\n"); + printf("+-------+--------+\r\n"); + + for (int i = 0; i < allocated_pcpus; i++) { + printf("| %-5d | %5.1f%% |\r\n", i, pcpu_stats[i].usage_pct); + } + + printf("+-------+--------+\r\n"); +} + +void free_pcpu_stats(void) +{ + if (xc_handle) { + xc_interface_close(xc_handle); + xc_handle = NULL; + } + free(pcpu_stats); + free(prev_idle); + free(prev_time); + pcpu_stats = NULL; + prev_idle = NULL; + prev_time = NULL; + allocated_pcpus = 0; +} diff --git a/tools/xentop/pcpu.h b/tools/xentop/pcpu.h new file mode 100644 index 0000000000..2ce86292a6 --- /dev/null +++ b/tools/xentop/pcpu.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Renesas Electronics Corporation + */ + +#ifndef __XENTOP_PCPU_H__ +#define __XENTOP_PCPU_H__ + +#include + +int update_pcpu_stats(const struct timeval *now, unsigned int delay); +void print_pcpu_stats(void); +void free_pcpu_stats(void); + +#endif /* __XENTOP_PCPU_H__ */ diff --git a/tools/xentop/xentop.c b/tools/xentop/xentop.c index f5d6c19cf9..dcf2f69b59 100644 --- a/tools/xentop/xentop.c +++ b/tools/xentop/xentop.c @@ -37,6 +37,7 @@ #endif #include +#include "pcpu.h" #define XENTOP_VERSION "1.0" @@ -205,6 +206,7 @@ field_id sort_field = FIELD_DOMID; unsigned int first_domain_index = 0; unsigned int delay = 3; unsigned int batch = 0; +static unsigned int show_pcpus = 0; unsigned int loop = 1; unsigned int iterations = 0; int show_vcpus = 0; @@ -230,22 +232,23 @@ static WINDOW *cwin; /* Print usage message, using given program name */ static void usage(const char *program) { - printf("Usage: %s [OPTION]\n" - "Displays ongoing information about xen vm resources \n\n" - "-h, --help display this help and exit\n" - "-V, --version output version information and exit\n" - "-d, --delay=SECONDS seconds between updates (default 3)\n" - "-n, --networks output vif network data\n" - "-x, --vbds output vbd block device data\n" - "-r, --repeat-header repeat table header before each domain\n" - "-v, --vcpus output vcpu data\n" - "-b, --batch output in batch mode, no user input accepted\n" - "-i, --iterations number of iterations before exiting\n" - "-f, --full-name output the full domain name (not truncated)\n" - "-z, --dom0-first display dom0 first (ignore sorting)\n" - "\n" XENTOP_BUGSTO, - program); - return; + printf("Usage: %s [OPTION]\n" + "Displays ongoing information about xen vm resources \n\n" + "-h, --help display this help and exit\n" + "-V, --version output version information and exit\n" + "-d, --delay=SECONDS seconds between updates (default 3)\n" + "-n, --networks output vif network data\n" + "-x, --vbds output vbd block device data\n" + "-r, --repeat-header repeat table header before each domain\n" + "-v, --vcpus output vcpu data\n" + "-b, --batch output in batch mode, no user input accepted\n" + "-p, --pcpus show physical CPU stats\n" + "-i, --iterations number of iterations before exiting\n" + "-f, --full-name output the full domain name (not truncated)\n" + "-z, --dom0-first display dom0 first (ignore sorting)\n" + "\n" XENTOP_BUGSTO, + program); + return; } /* Print program version information */ @@ -267,6 +270,8 @@ static void cleanup(void) xenstat_free_node(cur_node); if(xhandle != NULL) xenstat_uninit(xhandle); + + free_pcpu_stats(); } /* Display the given message and gracefully exit */ @@ -1189,7 +1194,7 @@ static void top(void) fail("Failed to retrieve statistics from libxenstat\n"); /* dump summary top information */ - if (!batch) + if (!batch && !show_pcpus) do_summary(); /* Count the number of domains for which to report data */ @@ -1245,9 +1250,17 @@ static void top(void) do_vbd(domains[i]); } - if (!batch) + if (!batch && !show_pcpus) do_bottom_line(); + if (show_pcpus) { + if (update_pcpu_stats(&curtime, delay) == 0) { + print_pcpu_stats(); + } else { + fail("Error getting PCPU stats\n"); + } + } + free(domains); } @@ -1271,13 +1284,14 @@ int main(int argc, char **argv) { "repeat-header", no_argument, NULL, 'r' }, { "vcpus", no_argument, NULL, 'v' }, { "delay", required_argument, NULL, 'd' }, - { "batch", no_argument, NULL, 'b' }, + { "batch", no_argument, NULL, 'b' }, + { "pcpus", no_argument, NULL, 'p' }, { "iterations", required_argument, NULL, 'i' }, { "full-name", no_argument, NULL, 'f' }, { "dom0-first", no_argument, NULL, 'z' }, { 0, 0, 0, 0 }, }; - const char *sopts = "hVnxrvd:bi:fz"; + const char *sopts = "hVnxrvd:bpi:fz"; if (atexit(cleanup) != 0) fail("Failed to install cleanup handler.\n"); @@ -1312,6 +1326,9 @@ int main(int argc, char **argv) case 'b': batch = 1; break; + case 'p': + show_pcpus = 1; + break; case 'i': iterations = atoi(optarg); loop = 0; -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 13:08:55 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 13:08:55 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069368.1433225 (Exim 4.92) (envelope-from ) id 1uiuvu-0006JN-C8; Mon, 04 Aug 2025 13:08:54 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069368.1433225; Mon, 04 Aug 2025 13:08:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuvu-0006JG-9C; Mon, 04 Aug 2025 13:08:54 +0000 Received: by outflank-mailman (input) for mailman id 1069368; Mon, 04 Aug 2025 13:08:53 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiuvt-0006J9-KU for xen-devel@lists.xenproject.org; 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Must be > > @@ -40,6 +41,12 @@ bool __mfn_valid(unsigned long mfn) > > > > #ifdef CONFIG_PDX_MASK_COMPRESSION > > invalid |= mfn & pfn_hole_mask; > > +#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) > > +{ > > + unsigned long base = pfn_bases[PFN_TBL_IDX(mfn)]; > > + > > + invalid |= mfn < base || mfn >= base + pdx_region_size; > > Leveraging wrapping, this could be simplified to > > invalid |= mfn - base >= pdx_region_size; > > I think. Considering it's a frequently used path, doing so may be worthwhile. I don't think that would work for all cases, take the following example: PFN compression using lookup table shift 18 and region size 0x40000 range 0 [0000000280000, 00000002bffff] PFN IDX 10 : 0000000280000 If you pass mfn 0 to mfn_valid() with your proposed adjustment, the result of the subtraction would be: 0 - ~0UL == 1 Which wouldn't satisfy the >= condition, and hence pfn 0 would be reported as a valid mfn. I think we need to keep both sides of the check. > > @@ -75,6 +82,13 @@ void set_pdx_range(unsigned long smfn, unsigned long emfn) > > # error "Missing architecture maximum number of RAM ranges" > > #endif > > > > +/* Some functions should be init when not using PDX mask compression. */ > > +#ifndef CONFIG_PDX_MASK_COMPRESSION > > +# define __init_or_pdx_mask __init > > +#else > > +# define __init_or_pdx_mask > > +#endif > > Considering this is local to the CU, "pdx" in the name isn't very meaningful. > Instead it being a compression type may be, so how about __init_or_mask_compr > or some such? (If we gain further compression types, this may be getting > unwieldy anyway.) I'm fine with your proposal. The current naming was derived from the CONFIG_ define. > > +static void __init cf_check swp_node(void *a, void *b, size_t size) > > +{ > > + SWAP(a, b); > > This doesn't look right - you swap a and b, not what they point to. > > > +static bool __init pfn_offset_sanitize_ranges(void) > > +{ > > + unsigned int i = 0; > > + > > + if ( nr_ranges == 1 ) > > + { > > + ASSERT(PFN_TBL_IDX(ranges[0].base) == > > + PFN_TBL_IDX(ranges[0].base + ranges[0].size - 1)); > > I think this points out a naming issue in patch 2: "base" and "size" look > as if these were address / byte count, when they're PFN / page count. > Which caught my eye because of the values being passed to something that > actually wants a PFN (and hence looked wrong at the first glance). The struct name is pfn_range, I could rename the fields to base_pfn and pages or similar, but my impression was that the struct name was enough of a pointer that those are PFN ranges. Do you have any alternative proposal about how to name those? > > + return true; > > + } > > + > > + while ( i + 1 < nr_ranges ) > > + { > > + /* > > + * Ensure ranges [start, end] use the same offset table index. Should > > + * be guaranteed by the logic that calculates the pfn shift. > > + */ > > + if ( PFN_TBL_IDX(ranges[i].base) != > > + PFN_TBL_IDX(ranges[i].base + ranges[i].size - 1) || > > + PFN_TBL_IDX(ranges[i + 1].base) != > > + PFN_TBL_IDX(ranges[i + 1].base + ranges[i + 1].size - 1) ) > > It feels a little odd to re-do the 2nd half of the checking here on the next > iteration, when the table wouldn't have changed when ... > > > + { > > + ASSERT_UNREACHABLE(); > > + return false; > > + } > > + > > + if ( PFN_TBL_IDX(ranges[i].base) != PFN_TBL_IDX(ranges[i + 1].base) ) > > + { > > + i++; > > + continue; > > ... taking this path. Could I talk you into moving the latter half ... > > > + } > > ... here? If that's needed at all, as ... > > > + /* Merge ranges with the same table index. */ > > + ranges[i].size = ranges[i + 1].base + ranges[i + 1].size - > > + ranges[i].base; > > ... the new range should also fulfill the requirement. Just that the last > such range then wouldn't be checked, unless ... > > > + memmove(&ranges[i + 1], &ranges[i + 2], > > + (nr_ranges - (i + 2)) * sizeof(ranges[0])); > > + nr_ranges--; > > + } > > ... that checking was put past the loop. Which then would allow to remove > the special casing of nr_ranges == 1 at the top of the function: You'd > uniformly check the ranges[nr_ranges - 1] here. What about doing it like: static bool __init pfn_offset_sanitize_ranges(void) { unsigned int i = 0; if ( PFN_TBL_IDX(ranges[0].base) != PFN_TBL_IDX(ranges[0].base + ranges[0].size - 1) ) { ASSERT_UNREACHABLE(); return false; } while ( i + 1 < nr_ranges ) { /* * Ensure ranges [start, end] use the same offset table index. Should * be guaranteed by the logic that calculates the pfn shift. */ if ( PFN_TBL_IDX(ranges[i + 1].base) != PFN_TBL_IDX(ranges[i + 1].base + ranges[i + 1].size - 1) ) { ASSERT_UNREACHABLE(); return false; } if ( PFN_TBL_IDX(ranges[i].base) != PFN_TBL_IDX(ranges[i + 1].base) ) { i++; continue; } /* Merge ranges with the same table index. */ ranges[i].size = ranges[i + 1].base + ranges[i + 1].size - ranges[i].base; memmove(&ranges[i + 1], &ranges[i + 2], (nr_ranges - (i + 2)) * sizeof(ranges[0])); nr_ranges--; } return true; } I've pulled the index 0 check ahead of the loop, which then covers for the case where nr_ranges == 1. There's also no duplicate checking of the ranges, since the range at i + 1 will always be a non-checked one; either because the array has been shifted as a result of a range merging, or the index has been advanced. > > + ranges[i].size = start + ranges[i].size - ranges[i].base; > > + > > + /* > > + * Only merge overlapped regions now, leave adjacent regions separated. > > + * They would be merged later if both use the same index into the > > + * lookup table. > > + */ > > + if ( !i || ranges[i].base >= (ranges[i - 1].base + ranges[i - 1].size) ) > > + { > > + /* > > + * We might parse the region at position 0 more than once, as for > > + * index 0 we don't attempt to merge to keep this simple. > > + */ > > + mask |= pdx_region_mask(ranges[i].base, ranges[i].size); > > + continue; > > In how far is it relevant here that slot 0 may be looked at more than once? Not really, just that someone might wonder about the possibly inefficiency of this. I will remove the comment then. > > + } > > + > > + ranges[i - 1].size = ranges[i].base + ranges[i].size - > > + ranges[i - 1].base; > > + > > + if ( i + 1 < nr_ranges ) > > + memmove(&ranges[i], &ranges[i + 1], > > + (nr_ranges - (i + 1)) * sizeof(ranges[0])); > > + else /* last range */ > > + mask |= pdx_region_mask(ranges[i].base, ranges[i].size); > > + nr_ranges--; > > + i--; > > + } > > + > > + /* > > + * Populate a mask with the non-equal bits of the different ranges, do this > > + * to calculate the maximum PFN shift to use as the lookup table index. > > + */ > > + for ( i = 0; i < nr_ranges; i++ ) > > + for ( unsigned int j = 0; j < nr_ranges; j++ ) > > + idx_mask |= (ranges[i].base & ~mask) ^ (ranges[j].base & ~mask); > > + > > + if ( !idx_mask ) > > + /* Single region case. */ > > + pfn_index_shift = flsl(mask); > > + else if ( flsl(idx_mask) - ffsl(idx_mask) < CONFIG_PDX_OFFSET_TBL_ORDER ) > > + /* The changed mask fits in the table index width. */ > > + pfn_index_shift = ffsl(idx_mask) - 1; > > + else > > + /* Changed mask is wider than array size, use most significant bits. */ > > + pfn_index_shift = flsl(idx_mask) - CONFIG_PDX_OFFSET_TBL_ORDER; > > Perhaps emit a log message here to indicate that bigger PDX_OFFSET_TBL_ORDER > may yield better results? What about: printk(XENLOG_DEBUG "PFN compression table index truncated, requires order %u\n", flsl(idx_mask) - ffsl(idx_mask) + 1); > > + /* > > + * Ensure correctness of the calculated values, plus merge ranges if they > > + * use the same lookup table index. > > + */ > > + if ( !pfn_offset_sanitize_ranges() ) > > + { > > + printk(XENLOG_DEBUG "PFN compression is invalid, disabling\n"); > > + pfn_pdx_compression_reset(); > > + return false; > > + } > > + > > + /* > > + * Find the maximum PFN range size after having merged ranges with same > > + * index. The rounded up region size will be the base for the PDX region > > + * size and shift. > > + */ > > + for ( i = 0; i < nr_ranges; i++ ) > > + size = max(size, ranges[i].size); > > + > > + /* pdx_init_mask() already takes MAX_ORDER into account. */ > > + mask = PFN_DOWN(pdx_init_mask(size << PAGE_SHIFT)); > > We're in arch-neutral code here, so I think you need to cast size to paddr_t > before shifting. Indeed, size is unsigned long here. Thanks, Roger. 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Mon, 04 Aug 2025 06:40:57 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 15:40:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 7/8] pdx: introduce a new compression algorithm based on region offsets To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: Oleksii Kurochko , Community Manager , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , xen-devel@lists.xenproject.org References: <20250724110416.2081-1-roger.pau@citrix.com> <20250724110416.2081-8-roger.pau@citrix.com> <87c1a72d-62cf-475a-8320-70e1954cd0f5@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 04.08.2025 15:08, Roger Pau Monné wrote: > On Tue, Jul 29, 2025 at 04:16:15PM +0200, Jan Beulich wrote: >> On 24.07.2025 13:04, Roger Pau Monne wrote: >>> --- a/xen/common/pdx.c >>> +++ b/xen/common/pdx.c >>> @@ -24,6 +24,7 @@ >>> #include >>> #include >>> #include >>> +#include >>> >>> /** >>> * Maximum (non-inclusive) usable pdx. Must be >>> @@ -40,6 +41,12 @@ bool __mfn_valid(unsigned long mfn) >>> >>> #ifdef CONFIG_PDX_MASK_COMPRESSION >>> invalid |= mfn & pfn_hole_mask; >>> +#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) >>> +{ >>> + unsigned long base = pfn_bases[PFN_TBL_IDX(mfn)]; >>> + >>> + invalid |= mfn < base || mfn >= base + pdx_region_size; >> >> Leveraging wrapping, this could be simplified to >> >> invalid |= mfn - base >= pdx_region_size; >> >> I think. Considering it's a frequently used path, doing so may be worthwhile. > > I don't think that would work for all cases, take the following > example: > > PFN compression using lookup table shift 18 and region size 0x40000 > range 0 [0000000280000, 00000002bffff] PFN IDX 10 : 0000000280000 > > If you pass mfn 0 to mfn_valid() with your proposed adjustment, the > result of the subtraction would be: > > 0 - ~0UL == 1 > > Which wouldn't satisfy the >= condition, and hence pfn 0 would be > reported as a valid mfn. I think we need to keep both sides of the > check. Hmm, right - I keep forgetting that the start of a pfn_bases[x] isn't necessarily a valid page itself. >>> +static void __init cf_check swp_node(void *a, void *b, size_t size) >>> +{ >>> + SWAP(a, b); >> >> This doesn't look right - you swap a and b, not what they point to. >> >>> +static bool __init pfn_offset_sanitize_ranges(void) >>> +{ >>> + unsigned int i = 0; >>> + >>> + if ( nr_ranges == 1 ) >>> + { >>> + ASSERT(PFN_TBL_IDX(ranges[0].base) == >>> + PFN_TBL_IDX(ranges[0].base + ranges[0].size - 1)); >> >> I think this points out a naming issue in patch 2: "base" and "size" look >> as if these were address / byte count, when they're PFN / page count. >> Which caught my eye because of the values being passed to something that >> actually wants a PFN (and hence looked wrong at the first glance). > > The struct name is pfn_range, I could rename the fields to base_pfn > and pages or similar, but my impression was that the struct name was > enough of a pointer that those are PFN ranges. Problem being that the struct name isn't anywhere in sight here. > Do you have any > alternative proposal about how to name those? Your suggested new naming looks good to me. >>> + return true; >>> + } >>> + >>> + while ( i + 1 < nr_ranges ) >>> + { >>> + /* >>> + * Ensure ranges [start, end] use the same offset table index. Should >>> + * be guaranteed by the logic that calculates the pfn shift. >>> + */ >>> + if ( PFN_TBL_IDX(ranges[i].base) != >>> + PFN_TBL_IDX(ranges[i].base + ranges[i].size - 1) || >>> + PFN_TBL_IDX(ranges[i + 1].base) != >>> + PFN_TBL_IDX(ranges[i + 1].base + ranges[i + 1].size - 1) ) >> >> It feels a little odd to re-do the 2nd half of the checking here on the next >> iteration, when the table wouldn't have changed when ... >> >>> + { >>> + ASSERT_UNREACHABLE(); >>> + return false; >>> + } >>> + >>> + if ( PFN_TBL_IDX(ranges[i].base) != PFN_TBL_IDX(ranges[i + 1].base) ) >>> + { >>> + i++; >>> + continue; >> >> ... taking this path. Could I talk you into moving the latter half ... >> >>> + } >> >> ... here? If that's needed at all, as ... >> >>> + /* Merge ranges with the same table index. */ >>> + ranges[i].size = ranges[i + 1].base + ranges[i + 1].size - >>> + ranges[i].base; >> >> ... the new range should also fulfill the requirement. Just that the last >> such range then wouldn't be checked, unless ... >> >>> + memmove(&ranges[i + 1], &ranges[i + 2], >>> + (nr_ranges - (i + 2)) * sizeof(ranges[0])); >>> + nr_ranges--; >>> + } >> >> ... that checking was put past the loop. Which then would allow to remove >> the special casing of nr_ranges == 1 at the top of the function: You'd >> uniformly check the ranges[nr_ranges - 1] here. > > What about doing it like: > > static bool __init pfn_offset_sanitize_ranges(void) > { > unsigned int i = 0; > > if ( PFN_TBL_IDX(ranges[0].base) != > PFN_TBL_IDX(ranges[0].base + ranges[0].size - 1) ) > { > ASSERT_UNREACHABLE(); > return false; > } > > while ( i + 1 < nr_ranges ) > { > /* > * Ensure ranges [start, end] use the same offset table index. Should > * be guaranteed by the logic that calculates the pfn shift. > */ > if ( PFN_TBL_IDX(ranges[i + 1].base) != > PFN_TBL_IDX(ranges[i + 1].base + ranges[i + 1].size - 1) ) > { > ASSERT_UNREACHABLE(); > return false; > } > > if ( PFN_TBL_IDX(ranges[i].base) != PFN_TBL_IDX(ranges[i + 1].base) ) > { > i++; > continue; > } > > /* Merge ranges with the same table index. */ > ranges[i].size = ranges[i + 1].base + ranges[i + 1].size - > ranges[i].base; > memmove(&ranges[i + 1], &ranges[i + 2], > (nr_ranges - (i + 2)) * sizeof(ranges[0])); > nr_ranges--; > } > > return true; > } > > I've pulled the index 0 check ahead of the loop, which then covers for > the case where nr_ranges == 1. There's also no duplicate checking of > the ranges, since the range at i + 1 will always be a non-checked one; > either because the array has been shifted as a result of a range > merging, or the index has been advanced. Looks good, thanks. >>> + ranges[i].size = start + ranges[i].size - ranges[i].base; >>> + ranges[i - 1].size = ranges[i].base + ranges[i].size - >>> + ranges[i - 1].base; >>> + >>> + if ( i + 1 < nr_ranges ) >>> + memmove(&ranges[i], &ranges[i + 1], >>> + (nr_ranges - (i + 1)) * sizeof(ranges[0])); >>> + else /* last range */ >>> + mask |= pdx_region_mask(ranges[i].base, ranges[i].size); >>> + nr_ranges--; >>> + i--; >>> + } >>> + >>> + /* >>> + * Populate a mask with the non-equal bits of the different ranges, do this >>> + * to calculate the maximum PFN shift to use as the lookup table index. >>> + */ >>> + for ( i = 0; i < nr_ranges; i++ ) >>> + for ( unsigned int j = 0; j < nr_ranges; j++ ) >>> + idx_mask |= (ranges[i].base & ~mask) ^ (ranges[j].base & ~mask); >>> + >>> + if ( !idx_mask ) >>> + /* Single region case. */ >>> + pfn_index_shift = flsl(mask); >>> + else if ( flsl(idx_mask) - ffsl(idx_mask) < CONFIG_PDX_OFFSET_TBL_ORDER ) >>> + /* The changed mask fits in the table index width. */ >>> + pfn_index_shift = ffsl(idx_mask) - 1; >>> + else >>> + /* Changed mask is wider than array size, use most significant bits. */ >>> + pfn_index_shift = flsl(idx_mask) - CONFIG_PDX_OFFSET_TBL_ORDER; >> >> Perhaps emit a log message here to indicate that bigger PDX_OFFSET_TBL_ORDER >> may yield better results? > > What about: > > printk(XENLOG_DEBUG > "PFN compression table index truncated, requires order %u\n", > flsl(idx_mask) - ffsl(idx_mask) + 1); Again, fine with me. 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Mon, 04 Aug 2025 06:52:19 -0700 (PDT) Message-ID: <829f9477-2b18-47f0-8fb3-57bffa8d133d@suse.com> Date: Mon, 4 Aug 2025 15:52:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 01/20] xen/riscv: implement sbi_remote_hfence_gvma() To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > Instruct the remote harts to execute one or more HFENCE.GVMA instructions, > covering the range of guest physical addresses between start_addr and > start_addr + size for all VMIDs. > > The remote fence operation applies to the entire address space if either: > - start_addr and size are both 0, or > - size is equal to 2^XLEN-1. > > Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich However, ... > --- a/xen/arch/riscv/include/asm/sbi.h > +++ b/xen/arch/riscv/include/asm/sbi.h > @@ -89,6 +89,25 @@ bool sbi_has_rfence(void); > int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, > size_t size); > > +/* > + * Instructs the remote harts to execute one or more HFENCE.GVMA > + * instructions, covering the range of guest physical addresses > + * between start_addr and start_addr + size for all VMIDs. ... I'd like to ask that you avoid fuzzy terminology like this one. Afaict you mean [start, start + size). Help yourself and future readers by then also saying it exactly like this. (Happy to make a respective edit while committing.) > + * Returns 0 if IPI was sent to all the targeted harts successfully > + * or negative value if start_addr or size is not valid. This similarly is ambiguous: The union of the success case stated and the error case stated isn't obviously all possible states. The success statement in particular alludes to the possibility of an IPI not actually reaching its target. > + * The remote fence operation applies to the entire address space if either: > + * - start_addr and size are both 0, or > + * - size is equal to 2^XLEN-1. Whose XLEN is this? The guest's? The host's? (I assume the latter, but it's not unambiguous, unless there's specific terminology that I'm unaware of, yet which would make this unambiguous.) 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Mon, 04 Aug 2025 06:55:47 -0700 (PDT) Message-ID: <164e0f8e-3986-4c9a-8201-14ea006405c7@suse.com> Date: Mon, 4 Aug 2025 15:55:46 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 02/20] xen/riscv: introduce sbi_remote_hfence_gvma_vmid() To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > It instructs the remote harts to execute one or more HFENCE.GVMA instructions > by making an SBI call, covering the range of guest physical addresses between > start_addr and start_addr + size only for the given VMID. > > The remote fence operation applies to the entire address space if either: > - start_addr and size are both 0, or > - size is equal to 2^XLEN-1. > > Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich with perhaps a similar on-commit edit as suggested for patch 1. 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It would be preferable to do those > >> allocations as part of the header initialization, and re-use them. > > > > I've been thinking over this, as I've realized that while commenting > > on it, I didn't provide any alternatives. > > > > The usage of rangesets to figure out the regions to map is already not > > optimal, as adding/removing from a rangeset can lead to memory > > allocations. It would be good if we could create rangesets with a > > pre-allocated number of ranges (iow: a pool of struct ranges), but > > that's for another patchset. I think Jan already commented on this > > aspect long time ago. > > +1 > > > I'm considering whether to allocate the deferred mapping structures > > per-vCPU instead of per-device. That would for example mean moving > > the current vpci_bar->mem rangeset so it's allocated in vpci_vcpu > > struct instead. The point would be to not have the rangesets per > > device (because there can be a lot of devices, specially for the > > hardware domain), but instead have those per-vCPU. This should work > > because a vCPU can only queue a single vPCI operation, from a single > > device. > > > > It should then be possible to allocate the deferred mapping structures > > at vCPU creation. I also ponder if we really need a linked list to > > queue them; AFAIK there can only ever be an unmapping and a mapping > > operation pending (so 2 operations at most). Hence we could use a > > more "fixed" structure like an array. For example in struct vpci_vcpu > > you could introduce a struct vpci_map_task task[2] field? > > > > Sorry, I know this is not a minor change to request. It shouldn't > > change the overall logic much, but it would inevitably affect the > > code. Let me know what you think. > > Thanks for the feedback and suggestion. Yeah, I'll give this a try. > Here's roughly what I'm thinking so far. I'll keep playing with it. > > diff --git a/xen/common/domain.c b/xen/common/domain.c > index 5241a1629eeb..942c9fe7d364 100644 > --- a/xen/common/domain.c > +++ b/xen/common/domain.c > @@ -387,6 +387,16 @@ static int vmtrace_alloc_buffer(struct vcpu *v) > */ > static int vcpu_teardown(struct vcpu *v) > { > +#ifdef CONFIG_HAS_VPCI > + for ( unsigned int i = 0; i < ARRAY_SIZE(v->vpci.task); i++ ) > + { > + struct vpci_map_task *task = &v->vpci.task[i]; > + > + for ( unsigned int j = 0; j < ARRAY_SIZE(task->bars); j++ ) > + rangeset_destroy(task->bars[j].mem); You might want to additionally do: task->bars[j].mem = NULL; > + } > +#endif > + > vmtrace_free_buffer(v); > > return 0; > @@ -467,6 +477,26 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) > d->vcpu[prev_id]->next_in_list = v; > } > > +#ifdef CONFIG_HAS_VPCI > + for ( unsigned int i = 0; i < ARRAY_SIZE(v->vpci.task); i++ ) > + { > + struct vpci_map_task *task = &v->vpci.task[i]; > + > + for ( unsigned int j = 0; j < ARRAY_SIZE(task->bars); j++ ) > + { > + struct vpci_bar_map *bar = &task->bars[j]; > + char str[32]; > + > + snprintf(str, sizeof(str), "PCI map vcpu %u task %u BAR %u", vcpu_id, i, j); > + > + bar->mem = rangeset_new(v->domain, str, RANGESETF_no_print); Not sure there's much point in naming those with that much detail - those are scratch space for mapping calculations. You already pass RANGESETF_no_print, which means the contents of the rangeset won't be dumped, and hence the name is kind of meaningless. I shouldn't have named those either when allocated in bar_add_rangeset(). > + > + if ( !bar->mem ) > + goto fail_sched; > + } > + } > +#endif > + > /* Must be called after making new vcpu visible to for_each_vcpu(). */ > vcpu_check_shutdown(v); > > diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h > index 17cfecb0aabf..afe78b00ffc9 100644 > --- a/xen/include/xen/vpci.h > +++ b/xen/include/xen/vpci.h > @@ -116,7 +116,6 @@ struct vpci { > uint64_t guest_addr; > uint64_t size; > uint64_t resizable_sizes; > - struct rangeset *mem; > enum { > VPCI_BAR_EMPTY, > VPCI_BAR_IO, > @@ -207,14 +206,23 @@ struct vpci { > #endif > }; > > +#ifdef __XEN__ > struct vpci_vcpu { > /* Per-vcpu structure to store state while {un}mapping of PCI BARs. */ > const struct pci_dev *pdev; > - uint16_t cmd; > - bool rom_only : 1; > + struct domain *domain; > + unsigned int nr_pending_ops; Not sure you really need a pending ops counter? Hard to tell without seeing the code that makes use of it. > + struct vpci_map_task { > + struct vpci_bar_map { > + uint64_t addr; > + uint64_t guest_addr; > + struct rangeset *mem; > + } bars[PCI_HEADER_NORMAL_NR_BARS + 1]; > + uint16_t cmd; > + bool rom_only : 1; > + } task[2]; Don't you need a way to differentiate between map/unmap operations? Do you plan to use slot 0 as unmap and slot 1 as map? Or would you rather introduce a boolean field to signal it in struct vpci_map_task? Overall seems OK, but obviously it all needs to fit together with the current code :). Thanks, Roger. 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Mon, 04 Aug 2025 06:57:25 -0700 (PDT) Message-ID: <6b8a8631-14c5-4e57-91f9-22acdf7efa07@suse.com> Date: Mon, 4 Aug 2025 15:57:24 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] vpci: allow queueing of mapping operations To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , Stewart Hildebrand References: <20250723163744.13095-1-stewart.hildebrand@amd.com> <20250723163744.13095-2-stewart.hildebrand@amd.com> <6d5545a2-bbf0-4cf9-9820-5eaf6d8530f8@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 04.08.2025 15:55, Roger Pau Monné wrote: > On Fri, Aug 01, 2025 at 05:06:32PM -0400, Stewart Hildebrand wrote: >> On 7/25/25 03:58, Roger Pau Monné wrote: >>> On Thu, Jul 24, 2025 at 06:44:32PM +0200, Roger Pau Monné wrote: >>>> On Wed, Jul 23, 2025 at 12:37:41PM -0400, Stewart Hildebrand wrote: >>>>> @@ -283,7 +297,48 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, >>>>> return rc; >>>>> } >>>>> >>>>> -static void defer_map(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) >>>>> +static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, >>>>> + uint16_t cmd, bool rom_only) >>>>> +{ >>>>> + struct vpci_map_task *task = xzalloc(struct vpci_map_task); >>>> >>>> xvzalloc() preferably. >>>> >>>> This however introduces run-time allocations as a result of guest >>>> actions, which is not ideal IMO. It would be preferable to do those >>>> allocations as part of the header initialization, and re-use them. >>> >>> I've been thinking over this, as I've realized that while commenting >>> on it, I didn't provide any alternatives. >>> >>> The usage of rangesets to figure out the regions to map is already not >>> optimal, as adding/removing from a rangeset can lead to memory >>> allocations. It would be good if we could create rangesets with a >>> pre-allocated number of ranges (iow: a pool of struct ranges), but >>> that's for another patchset. I think Jan already commented on this >>> aspect long time ago. >> >> +1 >> >>> I'm considering whether to allocate the deferred mapping structures >>> per-vCPU instead of per-device. That would for example mean moving >>> the current vpci_bar->mem rangeset so it's allocated in vpci_vcpu >>> struct instead. The point would be to not have the rangesets per >>> device (because there can be a lot of devices, specially for the >>> hardware domain), but instead have those per-vCPU. This should work >>> because a vCPU can only queue a single vPCI operation, from a single >>> device. >>> >>> It should then be possible to allocate the deferred mapping structures >>> at vCPU creation. I also ponder if we really need a linked list to >>> queue them; AFAIK there can only ever be an unmapping and a mapping >>> operation pending (so 2 operations at most). Hence we could use a >>> more "fixed" structure like an array. For example in struct vpci_vcpu >>> you could introduce a struct vpci_map_task task[2] field? >>> >>> Sorry, I know this is not a minor change to request. It shouldn't >>> change the overall logic much, but it would inevitably affect the >>> code. Let me know what you think. >> >> Thanks for the feedback and suggestion. Yeah, I'll give this a try. >> Here's roughly what I'm thinking so far. I'll keep playing with it. >> >> diff --git a/xen/common/domain.c b/xen/common/domain.c >> index 5241a1629eeb..942c9fe7d364 100644 >> --- a/xen/common/domain.c >> +++ b/xen/common/domain.c >> @@ -387,6 +387,16 @@ static int vmtrace_alloc_buffer(struct vcpu *v) >> */ >> static int vcpu_teardown(struct vcpu *v) >> { >> +#ifdef CONFIG_HAS_VPCI >> + for ( unsigned int i = 0; i < ARRAY_SIZE(v->vpci.task); i++ ) >> + { >> + struct vpci_map_task *task = &v->vpci.task[i]; >> + >> + for ( unsigned int j = 0; j < ARRAY_SIZE(task->bars); j++ ) >> + rangeset_destroy(task->bars[j].mem); > > You might want to additionally do: > > task->bars[j].mem = NULL; Should we perhaps introduce RANGESET_DESTROY() along the lines of XFREE() et al? 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Mon, 04 Aug 2025 07:11:13 -0700 (PDT) Message-ID: <01442213-1bcb-465c-9e0d-252864ba88c8@suse.com> Date: Mon, 4 Aug 2025 16:11:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/20] xen/dom0less: abstract Arm-specific p2m type name for device MMIO mappings To: Oleksii Kurochko Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > Rename `p2m_mmio_direct_dev` to a more architecture-neutral alias > `p2m_mmio_direct` to avoid leaking Arm-specific naming into common Xen code, > such as dom0less passthrough property handling. > > This helps reduce platform-specific terminology in shared logic and > improves clarity for future non-Arm ports (e.g. RISC-V or PowerPC). > > No functional changes — the definition is preserved via a macro alias > for Arm. > > Suggested-by: Jan Beulich I'm sorry, but no, ... > --- a/xen/arch/arm/include/asm/p2m.h > +++ b/xen/arch/arm/include/asm/p2m.h > @@ -137,6 +137,8 @@ typedef enum { > p2m_max_real_type, /* Types after this won't be store in the p2m */ > } p2m_type_t; > > +#define p2m_mmio_direct p2m_mmio_direct_dev ... this isn't what I suggested. When Arm has three p2m_mmio_direct_*, randomly aliasing one to p2m_mmio_direct is imo more likely to create confusion than to help things. Imo you want to introduce ... > --- a/xen/common/device-tree/dom0less-build.c > +++ b/xen/common/device-tree/dom0less-build.c > @@ -185,7 +185,7 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo, > gaddr_to_gfn(gstart), > PFN_DOWN(size), > maddr_to_mfn(mstart), > - p2m_mmio_direct_dev); > + p2m_mmio_direct); ... a per-arch inline function which returns the type to use here. The name of the function would want to properly reflect the purpose; my limited DT knowledge may make arch_dt_passthrough_p2m_type() an entirely wrong suggestion. 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Mon, 04 Aug 2025 07:16:23 -0700 (PDT) Message-ID: <48dcca92-4dd8-4d6e-a4cb-c10a7ee80f19@suse.com> Date: Mon, 4 Aug 2025 16:16:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 08/20] xen/riscv: add new p2m types and helper macros for type classification To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <3d35b6f4bb79048647020ed4e7b222585ca3a9a3.1753973161.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <3d35b6f4bb79048647020ed4e7b222585ca3a9a3.1753973161.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > - Extended p2m_type_t with additional types: p2m_mmio_direct, > p2m_grant_map_{rw,ro}. > - Added macros to classify memory types: P2M_RAM_TYPES, P2M_GRANT_TYPES. > - Introduced helper predicates: p2m_is_ram(), p2m_is_any_ram(). > - Define p2m_mmio_direct to tell handle_passthrough_prop() from common > code how to map device memory. > > Signed-off-by: Oleksii Kurochko Almost ready to be acked, except for ... > --- a/xen/arch/riscv/include/asm/p2m.h > +++ b/xen/arch/riscv/include/asm/p2m.h > @@ -62,8 +62,30 @@ struct p2m_domain { > typedef enum { > p2m_invalid = 0, /* Nothing mapped here */ > p2m_ram_rw, /* Normal read/write domain RAM */ > + p2m_mmio_direct_io, /* Read/write mapping of genuine Device MMIO area, > + PTE_PBMT_IO will be used for such mappings */ > + p2m_ext_storage, /* Following types'll be stored outsude PTE bits: */ > + p2m_grant_map_rw, /* Read/write grant mapping */ > + p2m_grant_map_ro, /* Read-only grant mapping */ > } p2m_type_t; > > +#define p2m_mmio_direct p2m_mmio_direct_io ... this (see reply to patch 09). > +/* We use bitmaps and mask to handle groups of types */ > +#define p2m_to_mask(t_) BIT(t_, UL) I notice that you moved the underscore to the back of the parameters, compared to how Arm has it. I wonder though: What use are these underscores in the first place, here and below? (There are macros where conflicts could arise, but the ones here don't fall in that group, afaict.) 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[92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b79c47b10asm15546318f8f.60.2025.08.04.08.02.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Aug 2025 08:02:14 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 01ecb330-7144-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754319735; x=1754924535; darn=lists.xenproject.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=Ra+2KvMwL1gIIILY0e8xcHmgCZ5EEzejiGz4ScwUAWY=; b=RdqC5eIXpM1TKFRLb5OsjgsDMveAHgEkxnaevmqWUi+FiCLhWqdOdsLPenlWAqerPC /0TirF8HzF6k3ScQVipw0FX7dLx2V9PnTm8fcK6yRKMG6q9dj1dTQEtBBvWDBECWEoOv dug9R9Z1IfabVEIX6K5gLGdcH5rKaqrluudJM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754319735; x=1754924535; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Ra+2KvMwL1gIIILY0e8xcHmgCZ5EEzejiGz4ScwUAWY=; b=pK2vazwyeyYSyTH+RUgcvanzzPJl6gQTB1UKLBTIOP5HT5tzRMHST06vAksRDV6qX/ MtGEfechBqDXTbShzcxgXCtH/0ya4ZfEeM/QIhKv+/JyMYdDQAzoIKh8ZDVV/r6Mgu78 vU97Jncj34HHlDxjfn1izN+yVErCWx2PJFm5+NSqo+RvE9JTRkt6pZq+aOjgS1D9ttFr 7lMRnOR7jRic6qAxUe1Z0il/XHk/yu42hxPVbIj6XT2AdqMRB1W1FS2t9HYN/PwCUGXt 8RWE4tgJ7wvb8HWIU/7q63w+X+QpCuExgabKw46KpRIv0ESzKnlkiFI32rt2o/ojxZwG InfA== X-Gm-Message-State: AOJu0YyETYlB0rVf5vig41vLGqz34DwcXhohcUpGesg6FCF7I5XBkQ3J fj+Ft3NpeCvFdT7rrHO1sGMLquaroGGq9GjYqosSJKdNvnPh9Yx9Yb5Xb4ikXuZJ35U= X-Gm-Gg: ASbGncu3N7botJgt5MC4DxuZ1jZ0A8RNQNXy7dAnXjSBwGWo3zXQre7yc9KIQXuiDm4 3Imx/JT+vKRIaOlQqzQxhj2hhG9UXdxFAlXsb+Js4BvkNLqPpa7uyMv6sBGFEGfRkQgi3PzLQZp C28qpZ2N+Nx6hBpHxcitpQK2yptPNrnC3l2gaJ1f4GN28awPqFl0ufqL/1egQY7JIAAnI9jrM6M bykwJoc/LQ11ulfz1RIvvUoR2pgShr+Qqq0ZbMUhcTbeCYJ60LM/cBr75JAQdpyrG7LFp63Q8e4 oOTo5IDXCKMPrx8PhW4ytp1VukuHeFTFWsZ6eg1KB+YLYbxSjPb6ys4hE59hBYrJuzxxXGeDclh /b+eKfcFGifF1tClZ7YHDuZDp/TJSkp+aEhyfiVxlMJjcRaC/XK+Hh9kv6UUUyMr65g== X-Google-Smtp-Source: AGHT+IF9Wwue/lSscaS6cVbgXxpWhyb6gs3+Hf4VDUamXB3dfd7reHIb8wT9ex2THYMkYIJXut5P+g== X-Received: by 2002:a05:600c:3b93:b0:459:94a7:220f with SMTP id 5b1f17b1804b1-45994a72576mr49153515e9.26.1754319734525; Mon, 04 Aug 2025 08:02:14 -0700 (PDT) Date: Mon, 4 Aug 2025 17:02:13 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Jan Beulich Cc: xen-devel@lists.xenproject.org, Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , Stewart Hildebrand Subject: Re: [PATCH v2 1/3] vpci: allow queueing of mapping operations Message-ID: References: <20250723163744.13095-1-stewart.hildebrand@amd.com> <20250723163744.13095-2-stewart.hildebrand@amd.com> <6d5545a2-bbf0-4cf9-9820-5eaf6d8530f8@amd.com> <6b8a8631-14c5-4e57-91f9-22acdf7efa07@suse.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <6b8a8631-14c5-4e57-91f9-22acdf7efa07@suse.com> On Mon, Aug 04, 2025 at 03:57:24PM +0200, Jan Beulich wrote: > On 04.08.2025 15:55, Roger Pau Monné wrote: > > On Fri, Aug 01, 2025 at 05:06:32PM -0400, Stewart Hildebrand wrote: > >> On 7/25/25 03:58, Roger Pau Monné wrote: > >>> On Thu, Jul 24, 2025 at 06:44:32PM +0200, Roger Pau Monné wrote: > >>>> On Wed, Jul 23, 2025 at 12:37:41PM -0400, Stewart Hildebrand wrote: > >>>>> @@ -283,7 +297,48 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev, > >>>>> return rc; > >>>>> } > >>>>> > >>>>> -static void defer_map(const struct pci_dev *pdev, uint16_t cmd, bool rom_only) > >>>>> +static struct vpci_map_task *alloc_map_task(const struct pci_dev *pdev, > >>>>> + uint16_t cmd, bool rom_only) > >>>>> +{ > >>>>> + struct vpci_map_task *task = xzalloc(struct vpci_map_task); > >>>> > >>>> xvzalloc() preferably. > >>>> > >>>> This however introduces run-time allocations as a result of guest > >>>> actions, which is not ideal IMO. It would be preferable to do those > >>>> allocations as part of the header initialization, and re-use them. > >>> > >>> I've been thinking over this, as I've realized that while commenting > >>> on it, I didn't provide any alternatives. > >>> > >>> The usage of rangesets to figure out the regions to map is already not > >>> optimal, as adding/removing from a rangeset can lead to memory > >>> allocations. It would be good if we could create rangesets with a > >>> pre-allocated number of ranges (iow: a pool of struct ranges), but > >>> that's for another patchset. I think Jan already commented on this > >>> aspect long time ago. > >> > >> +1 > >> > >>> I'm considering whether to allocate the deferred mapping structures > >>> per-vCPU instead of per-device. That would for example mean moving > >>> the current vpci_bar->mem rangeset so it's allocated in vpci_vcpu > >>> struct instead. The point would be to not have the rangesets per > >>> device (because there can be a lot of devices, specially for the > >>> hardware domain), but instead have those per-vCPU. This should work > >>> because a vCPU can only queue a single vPCI operation, from a single > >>> device. > >>> > >>> It should then be possible to allocate the deferred mapping structures > >>> at vCPU creation. I also ponder if we really need a linked list to > >>> queue them; AFAIK there can only ever be an unmapping and a mapping > >>> operation pending (so 2 operations at most). Hence we could use a > >>> more "fixed" structure like an array. For example in struct vpci_vcpu > >>> you could introduce a struct vpci_map_task task[2] field? > >>> > >>> Sorry, I know this is not a minor change to request. It shouldn't > >>> change the overall logic much, but it would inevitably affect the > >>> code. Let me know what you think. > >> > >> Thanks for the feedback and suggestion. Yeah, I'll give this a try. > >> Here's roughly what I'm thinking so far. I'll keep playing with it. > >> > >> diff --git a/xen/common/domain.c b/xen/common/domain.c > >> index 5241a1629eeb..942c9fe7d364 100644 > >> --- a/xen/common/domain.c > >> +++ b/xen/common/domain.c > >> @@ -387,6 +387,16 @@ static int vmtrace_alloc_buffer(struct vcpu *v) > >> */ > >> static int vcpu_teardown(struct vcpu *v) > >> { > >> +#ifdef CONFIG_HAS_VPCI > >> + for ( unsigned int i = 0; i < ARRAY_SIZE(v->vpci.task); i++ ) > >> + { > >> + struct vpci_map_task *task = &v->vpci.task[i]; > >> + > >> + for ( unsigned int j = 0; j < ARRAY_SIZE(task->bars); j++ ) > >> + rangeset_destroy(task->bars[j].mem); > > > > You might want to additionally do: > > > > task->bars[j].mem = NULL; > > Should we perhaps introduce RANGESET_DESTROY() along the lines of XFREE() et al? Yes, I was wondering whether to recommend it here, but didn't want to add noise, so was planning on adding this to my queue. But yes, if you can/will please do it Stewart. Thanks, Roger. From xen-devel-bounces@lists.xenproject.org Mon Aug 04 15:18:05 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 15:18:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069509.1433361 (Exim 4.92) (envelope-from ) id 1uiwwn-0007tN-Nt; Mon, 04 Aug 2025 15:17:57 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069509.1433361; Mon, 04 Aug 2025 15:17:57 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiwwn-0007tG-Js; Mon, 04 Aug 2025 15:17:57 +0000 Received: by outflank-mailman (input) for mailman id 1069509; Mon, 04 Aug 2025 15:17:55 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiwwl-0007tA-Mk for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 15:17:55 +0000 Received: from dibed.net-space.pl (dibed.net-space.pl [84.10.22.86]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2dd7547a-7146-11f0-b898-0df219b8e170; Mon, 04 Aug 2025 17:17:48 +0200 (CEST) Received: from router-fw.i.net-space.pl ([192.168.52.1]:41720 "EHLO tomti.i.net-space.pl") by router-fw-old.i.net-space.pl with ESMTP id S2271495AblHDPRq (ORCPT ); Mon, 4 Aug 2025 17:17:46 +0200 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2dd7547a-7146-11f0-b898-0df219b8e170 X-Comment: RFC 2476 MSA function at dibed.net-space.pl logged sender identity as: dkiper Date: Mon, 4 Aug 2025 17:17:43 +0200 From: Daniel Kiper To: Aaron Rainbolt Cc: grub-devel@gnu.org, xen-devel@lists.xenproject.org Subject: Re: [RESEND PATCH v3 1/1] kern/xen: Add Xen command line parsing Message-ID: <20250804151743.cjngftaseqesmht3@tomti.i.net-space.pl> References: <20250725153012.1dd46644@kf-m2g5> <20250725153112.4ea25243@kf-m2g5> <20250801125536.mc2sjrdyikljzea6@tomti.i.net-space.pl> <20250803105703.5c83d4b2@kf-m2g5> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250803105703.5c83d4b2@kf-m2g5> User-Agent: NeoMutt/20170113 (1.7.2) On Sun, Aug 03, 2025 at 10:57:03AM -0500, Aaron Rainbolt wrote: > On Fri, 1 Aug 2025 14:55:36 +0200 Daniel Kiper wrote: > > On Fri, Jul 25, 2025 at 03:31:12PM -0500, Aaron Rainbolt wrote: > > > Xen traditionally allows customizing guest behavior by passing > > > arguments to the VM kernel via the kernel command line. This is no > > > longer possible when using GRUB with Xen, as the kernel command > > > line is decided by the GRUB configuration file within the guest, > > > not data passed to the guest by Xen. > > > > > > To work around this limitation, enable GRUB to parse a command line > > > passed to it by Xen, and expose data from the command line to the > > > GRUB configuration as environment variables. These variables can be > > > used in the GRUB configuration for any desired purpose, such as > > > extending the kernel command line passed to the guest. The command > > > line format is inspired by the Linux kernel's command line format. > > > > > > To reduce the risk of misuse, abuse, or accidents in production, the > > > command line will only be parsed if it consists entirely of 7-bit > > > ASCII characters, only alphabetical characters and underscores are > > > permitted in variable names, and all variable names must start with > > > the string "xen_grub_env_". This also allows room for expanding the > > > command line arguments accepted by GRUB in the future, should other > > > arguments end up becoming desirable in the future. > > > > > > Signed-off-by: Aaron Rainbolt > > > --- > > > docs/grub.texi | 50 +++++ > > > grub-core/Makefile.core.def | 2 + > > > grub-core/kern/i386/xen/pvh.c | 14 ++ > > > grub-core/kern/main.c | 12 ++ > > > grub-core/kern/xen/cmdline.c | 343 > > > ++++++++++++++++++++++++++++++++++ include/grub/xen.h | > > > 2 + 6 files changed, 423 insertions(+) > > > create mode 100644 grub-core/kern/xen/cmdline.c > > > > > > diff --git a/docs/grub.texi b/docs/grub.texi > > > index 34b3484..ce82483 100644 > > > --- a/docs/grub.texi > > > +++ b/docs/grub.texi > > > @@ -3271,6 +3271,7 @@ GRUB. Others may be used freely in GRUB > > > configuration files. @menu > > > * Special environment variables:: > > > * Environment block:: > > > +* Passing environment variables through Xen:: > > > @end menu > > > > > > > > > @@ -3871,6 +3872,55 @@ using BIOS or EFI functions (no ATA, USB or > > > IEEE1275). @command{grub-mkconfig} uses this facility to implement > > > @samp{GRUB_SAVEDEFAULT} (@pxref{Simple configuration}). > > > > > > +@node Passing environment variables through Xen > > > +@section Passing environment variables through Xen > > > + > > > +If you are using a GRUB image as the kernel for a PV or PVH Xen > > > virtual +machine, you can pass environment variables from Xen's > > > dom0 to the VM through +the Xen-provided kernel command line. When > > > combined with a properly configured +guest, this can be used to > > > customize the guest's behavior on bootup via the +VM's Xen > > > configuration file. + > > > +GRUB will parse the kernel command line passed to it by Xen during > > > bootup. +The command line will be split into space-delimited words. > > > Single and +double quotes may be used to quote words or portions of > > > words that contain +spaces. Arbitrary characters may be > > > backslash-escaped to make them a literal +component of a word > > > rather than being parsed as quotes or word separators. The +command > > > line must consist entirely of printable 7-bit ASCII characters and > > > +spaces. If a non-printing ASCII character is found anywhere in the > > > command +line, the entire command line will be ignored by GRUB. + > > > +Each word should be a variable assignment in the format > > > ``variable'' or +``variable=value''. Variable names must contain > > > only the characters A-Z, a-z, +and underscore (``_''). Variable > > > names must begin with the string +``xen_grub_env_''. Variable > > > values can contain arbitrary printable 7-bit +ASCII characters and > > > space. If any variable contains an illegal name, that +variable > > > will be ignored. + > > > +If a variable name and value are both specified, the variable will > > > be set to +the specified value. If only a variable name is > > > specified, the variable's +value will be set to ``1''. > > > + > > > +The following is a simple example of how to use this functionality > > > to append +arbitrary variables to a guest's kernel command line: > > > + > > > +@example > > > +# In the Xen configuration file for the guest > > > +name = "linux_vm" > > > +type = "pvh" > > > +kernel = "/path/to/grub-i386-xen_pvh.bin" > > > +extra = "xen_grub_env_kernelappend='loglevel=3'" > > > > s/kernelappend/kernel_append/ > > > > or maybe even > > > > s/kernelappend/linux_append/ > > > > to make it clear it is appended to the "linux" command line... > > Will do. > > > > +memory = 1024 > > > +disk = [ "file:/srv/vms/linux_vm.img,sda,w" ] > > > + > > > +# In the guest's GRUB configuration file > > > +menuentry "Linux VM with dom0-specified kernel parameters" @{ > > > + search --set=root --label linux_vm --hint hd0,msdos1 > > > + linux /boot/vmlinuz root=LABEL=linux_vm > > > $@{xen_grub_env_kernelappend@} > > > > Ditto... > > Will do. > > > > + initrd /boot/initrd.img > > > +@} > > > +@end example > > > + > > > @node Modules > > > @chapter Modules > > > > > > diff --git a/grub-core/Makefile.core.def > > > b/grub-core/Makefile.core.def index b3f7119..df0f266 100644 > > > --- a/grub-core/Makefile.core.def > > > +++ b/grub-core/Makefile.core.def > > > @@ -248,6 +248,7 @@ kernel = { > > > xen = term/xen/console.c; > > > xen = disk/xen/xendisk.c; > > > xen = commands/boot.c; > > > + xen = kern/xen/cmdline.c; > > > > > > i386_xen_pvh = commands/boot.c; > > > i386_xen_pvh = disk/xen/xendisk.c; > > > @@ -255,6 +256,7 @@ kernel = { > > > i386_xen_pvh = kern/i386/xen/tsc.c; > > > i386_xen_pvh = kern/i386/xen/pvh.c; > > > i386_xen_pvh = kern/xen/init.c; > > > + i386_xen_pvh = kern/xen/cmdline.c; > > > i386_xen_pvh = term/xen/console.c; > > > > > > ia64_efi = kern/ia64/efi/startup.S; > > > diff --git a/grub-core/kern/i386/xen/pvh.c > > > b/grub-core/kern/i386/xen/pvh.c index 91fbca8..12df2d8 100644 > > > --- a/grub-core/kern/i386/xen/pvh.c > > > +++ b/grub-core/kern/i386/xen/pvh.c > > > @@ -321,6 +321,8 @@ void > > > grub_xen_setup_pvh (void) > > > { > > > grub_addr_t par; > > > + const char *xen_cmdline; > > > + int i; > > > > > > grub_xen_cpuid_base (); > > > grub_xen_setup_hypercall_page (); > > > @@ -352,6 +354,18 @@ grub_xen_setup_pvh (void) > > > grub_xen_mm_init_regions (); > > > > > > grub_rsdp_addr = pvh_start_info->rsdp_paddr; > > > + > > > + xen_cmdline = (const char *) pvh_start_info->cmdline_paddr; > > > + for (i = 0; i < MAX_GUEST_CMDLINE; i++) > > > > Oh, MAX_GUEST_CMDLINE is a too generic. May I ask you to rename it to > > GRUB_XEN_MAX_GUEST_CMDLINE? This should be done in separate patch > > preceding this one. > > Sure. > > > > + { > > > + if (xen_cmdline[i] == '\0') > > > > I cannot see much sense in this check. Please look below... > > > > > + { > > > + grub_strncpy ((char *) > > > grub_xen_start_page_addr->cmd_line, > > > + (char *) pvh_start_info->cmdline_paddr, > > > > s/char */const char */ > > > > Is it always guaranteed that pvh_start_info->cmdline_paddr have > > MAX_GUEST_CMDLINE size? If yes then... > > It is not guaranteed. I tested this under Qubes OS, and it is > unfortunately very possible to pass a guest command line longer than > MAX_GUEST_CMDLINE via pvh_start_info->cmdline_paddr. I do not know of > any documentation specifying what the "real" maximum length is in this > instance (if any), but in any event the string ultimately has to be > crammed into an array that is only MAX_GUEST_CMDLINE long. Originally I > wrote this to truncate the command line in this situation, but later > decided that discarding the command line would be safer than truncation. I think you are confusing source, grub_xen_start_page_addr->cmd_line, and destination, pvh_start_info->cmdline_paddr. I am asking about the destination... > (When booting a VM in PV mode, Xen does guarantee the command line will > not be longer than MAX_GUEST_CMDLINE and will simply return a truncated > command line. There is no way to detect this condition to my awareness, > so in PV mode, we simply live with the truncation since we aren't given > another option.) OK... > > grub_memset ((void *) pvh_start_info->cmdline_paddr, 0, > > MAX_GUEST_CMDLINE); grub_strncpy ((char *) > > grub_xen_start_page_addr->cmd_line, (const char *) > > pvh_start_info->cmdline_paddr, MAX_GUEST_CMDLINE - 1); > > > > ... and you are done... > > This would truncate the command line rather than discarding it. If the > goal is consistency with Xen's PV mode, then I can switch to this, but > I don't like the idea of booting a guest with corrupted data inserted > randomly into the grub.cfg file. (Like mentioned above, there isn't any > other option when using PV mode, but just because PV mode does things > dangerously doesn't mean we have to when running in PVH mode.) OK, but please remember you have to ensure the string is NUL-terminated after grub_strncpy(). Potentially you could also use grub_strlen() to make a check and add NUL in proper place... > > > + MAX_GUEST_CMDLINE); > > > + break; > > > + } > > > + } > > > } > > > > > > grub_err_t > > > diff --git a/grub-core/kern/main.c b/grub-core/kern/main.c > > > index 143a232..b4377d3 100644 > > > --- a/grub-core/kern/main.c > > > +++ b/grub-core/kern/main.c > > > @@ -37,6 +37,10 @@ > > > #include > > > #endif > > > > > > +#if defined (GRUB_MACHINE_XEN) || defined (GRUB_MACHINE_XEN_PVH) > > > +#include > > > +#endif > > > + > > > static bool cli_disabled = false; > > > static bool cli_need_auth = false; > > > > > > @@ -351,6 +355,14 @@ grub_main (void) > > > grub_env_export ("root"); > > > grub_env_export ("prefix"); > > > > > > + /* > > > + * Parse command line parameters from Xen and export them as > > > environment > > > + * variables > > > + */ > > > +#if defined (GRUB_MACHINE_XEN) || defined (GRUB_MACHINE_XEN_PVH) > > > + grub_parse_xen_cmdline (); > > > > Please move this call to the > > grub-core/kern/xen/init.c:grub_machine_init(). > > Will do. > > > > +#endif > > > + > > > /* Reclaim space used for modules. */ > > > reclaim_module_space (); > > > > > > diff --git a/grub-core/kern/xen/cmdline.c > > > b/grub-core/kern/xen/cmdline.c new file mode 100644 > > > index 0000000..03dd88f > > > --- /dev/null > > > +++ b/grub-core/kern/xen/cmdline.c > > > @@ -0,0 +1,343 @@ > > > +/* > > > + * GRUB -- GRand Unified Bootloader > > > + * Copyright (C) 2025 Free Software Foundation, Inc. > > > + * > > > + * GRUB is free software: you can redistribute it and/or modify > > > + * it under the terms of the GNU General Public License as > > > published by > > > + * the Free Software Foundation, either version 3 of the License, > > > or > > > + * (at your option) any later version. > > > + * > > > + * GRUB is distributed in the hope that it will be useful, > > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > > + * GNU General Public License for more details. > > > + * > > > + * You should have received a copy of the GNU General Public > > > License > > > + * along with GRUB. If not, see . > > > + */ > > > + > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +enum parse_flags > > > +{ > > > + PARSER_HIT_BACKSLASH = 0x1, > > > + PARSER_IN_SINGLE_QUOTES = 0x2, > > > + PARSER_IN_DOUBLE_QUOTES = 0x4, > > > +}; > > typedef parse_flags parse_flags_t; > > > > ... and use parse_flags_t instead below... > > Will do. > > > And probably this should be a local variable... > > See below for comments on globals in the parser. > > > > + > > > +#define PARSER_BASE_WORD_LEN 16 > > > > This constant begs for a few words of comment... > > Will add. This is just the initial length of the dynamically allocated > buffer for storing each "word" of the command line, but it is confusing > as written. Perhaps it should be renamed to PARSER_WORD_BUF_START_LEN > or similar, to make it clear this isn't a string length, but a buffer > length? s/length/size/ then... However, then why 16 not, e.g., 32? > > > +static grub_size_t word_list_len; > > > +static char **word_list; > > > +static grub_size_t current_word_len; > > > +static grub_size_t current_word_pos; > > > +static char *current_word; > > > +static char current_char; > > > > I have a feeling that most if not all of this variables should be > > local in a given function... > > I made them globals because making them local would have required an > awful lot of parameter "shuttling" that I believed made the code less > readable. For instance, the `append_word_to_list` function right now > has no parameters and can be called very simply by the parser whenever > it is needed. If all variables used were local, the function would have > to have a signature akin to: > > static bool append_word_to_list(grub_size_t *current_word_pos_ref, > grub_size_t *current_word_len_ref, char *current_word, > grub_size_t *word_list_len_ref, char **word_list) > > IMO this is difficult to read and frustrating to call (possibly even > error-prone). Ultimately the variables are "local" to the parser, and > the functions are just there to split up the parser's algorithm to > avoid repetition. They all ultimately operate on the same state, so > having the state variables static but global within the file fits the > current parser design well. First of all, think about the design. If you are sure it is optimal then please use struct and a pointer to pass as many argument as you need... > > > +static bool > > > +append_char_to_word (bool allow_null) > > > +{ > > > + /* > > > + * Fail if the current char is outside of the range 0x20 to > > > 0x7E. If > > > + * allow_null is true, make an exception for 0x00. This is a > > > safeguard > > > > Could you elaborate here when allow_null == true is useful? > > Usually when appending characters to a word, you aren't going to be > appending null characters, thus `append_char_to_word` usually rejects s/null/NUL/... > those so as to make it harder to mess things up. However, the string > does need to be null-terminated, and thus once a command line word is Ditto... In general, even it is correct, I prefer to use NUL instead of null/NULL to avoid confusion... > fully loaded into current_word, it is necessary to add the null > terminator on the end. In this instance the parser sets `current_char` > to '\0' and then calls the `append_char_to_word` function with > `allow_null` set to true, so that the function knows that the addition > of a null is intentional here. > > (In retrospect, if allow_null is set to true, the only thing > `append_char_to_word` should append is a null character, it should > reject anything else in that instance. Otherwise someone could > accidentally append something other than a null when they meant to > append a null.) Is not it simpler to open code this instead of complicating this function? > > > + * against likely-invalid data. > > > + */ > > > + if ( (!(current_char >= 0x20) || !(current_char <= 0x7E) ) > > > > grub_isprint()? > > That would work, I wasn't aware that existed. Maybe a mention of some > valuable GRUB internal API functions that are likely to remain stable > could be added to the GRUB development manual? (Or just a reference to > header files where useful things like this are defined.) Certainly it is a good idea. In general you can assume the GRUB has a lot of POSIX compatible functions which names are prefixed with "grub_". > > > + && (current_char != '\0' || allow_null == false)) > > > > I would drop redundant spaces between "(" and ")" and move "&&" to the > > end of first line of "if". > > Will do, though I'm likely to rewrite this conditional anyway so that > anything other than '\0' will be rejected when `allow_null == true`. > > > > + return false; > > > + > > > + if (current_word_pos == current_word_len) > > > + { > > > + current_word_len *= 2; > > > > You can do this in the argument of the function below... > > I mean, yes, technically I can, but that's a lot less readable to me. I > can't find anywhere else in GRUB that uses that style (using > `grep -ri '\*='` to search), and can find a few spots that use a style > similar to the one I've used here: > > * `util/grub-install.c` in function `device_map_check_duplicates` > * `grub-core/osdep/windows/platform.c` in function `get_efi_variable` > * `grub-core/osdep/unix/platform.c` in function `get_ofpathname` > > > > + current_word = grub_realloc (current_word, current_word_len); > > > + if (current_word == NULL) > > > + { > > > + current_word_len /= 2; > > > + return false; > > > + } > > > + } > > > + > > > + current_word[current_word_pos] = current_char; > > > + current_word_pos++; > > > > Again, you can do this operation in the "[]" above... > > Will do. (This does seem to be a much more common way to write things > in GRUB than what I've done.) > > > > + return true; > > > +} > > > + > > > +static bool > > > +append_word_to_list (void) > > > +{ > > > + /* No-op on empty words. */ > > > + if (current_word_pos == 0) > > > > This should be probably an argument for the function... > > See above for parser state and global variables rationale. > > > > + return true; > > > + > > > + current_char = '\0'; > > > + if (append_char_to_word (true) == false) > > > + { > > > + grub_error (GRUB_ERR_BUG, > > > + "couldn't append null terminator to word during > > > Xen cmdline parsing"); > > > + grub_print_error (); > > > + grub_exit (); > > > + } > > > + > > > + current_word_len = grub_strlen (current_word) + 1; > > > + current_word = grub_realloc (current_word, current_word_len); > > > + if (current_word == NULL) > > > + return false; > > > + word_list_len++; > > > > Again this, OK ++word_list_len to be precise, can be done in a > > function argument below... > > `grep -ri 'alloc.*++'` doesn't show me any instance of this style > anywhere else in the GRUB codebase, and I find it much more difficult > to read since now I have to think about incrementing `word_list_len`'s > value and returning it and multiplying the returned value all at the > same time. `grub-core/osdep/unix/platform.c` uses the style I've used > here. > > > > + word_list = grub_realloc (word_list, word_list_len * sizeof > > > (char *)); word_list = grub_realloc (word_list, ++word_list_len * sizeof (char *a)); Is it really difficult to read? I do not think so... [...] > > > +void > > > +grub_parse_xen_cmdline (void) > > > +{ > > > + const char *cmdline = (const char *) > > > grub_xen_start_page_addr->cmd_line; > > > + grub_size_t cmdline_len; > > > + bool cmdline_valid = false; > > > + char **param_keys = NULL; > > > + char **param_vals = NULL; > > > + grub_size_t param_dict_len = 0; > > > + grub_size_t param_dict_pos = 0; > > > + enum parse_flags parse_flags = 0; > > > + grub_size_t i = 0; > > > + > > > + /* > > > + * The following algorithm is used to parse the Xen command line: > > > + * > > > + * - The command line is split into space-separated words. > > > + * - Single and double quotes may be used to suppress the > > > splitting > > > + * behavior of spaces. > > > + * - Double quotes are appended to the current word verbatim > > > if they > > > + * appear within a single-quoted string portion, and vice > > > versa. > > > + * - Backslashes may be used to cause the next character to be > > > + * appended to the current word verbatim. This is only > > > useful when > > > + * used to escape quotes, spaces, and backslashes, but for > > > simplicity > > > + * we allow backslash-escaping anything. > > > + * - After splitting the command line into words, each word is > > > checked to > > > + * see if it contains an equals sign. > > > + * - If it does, it is split on the equals sign into a > > > key-value pair. The > > > + * key is then treated as an variable name, and the value is > > > treated as > > > + * the variable's value. > > > + * - If it does not, the entire word is treated as a variable > > > name. The > > > + * variable's value is implicitly considered to be `1`. > > > + * - All variables detected on the command line are checked to > > > see if their > > > + * names begin with the string `xen_grub_env_`. Variables that > > > do not pass > > > + * this check are discarded, variables that do pass this check > > > are > > > + * exported so they are available to the GRUB configuration. > > > > I think not all from this valuable comment landed in the > > documentation. Please fix it... > > Comparing the two side-by-side: > > +----------------------------------+----------------------------------+ > | Documentation | Comment | > +==================================+==================================+ > | The command line will be split | The command line is split into | > | into space-delimited words. | space-separated words. Single | > | Single and double quotes may be | and double quotes may be used to | > | used to quote words or portions | suppress the splitting behavior | > | of words that contain spaces. | of spaces. | > +----------------------------------+----------------------------------+ > | (Self-evident, any other | Double quotes are appended to | > | behavior involving quotes would | the current word verbatim if | > | be extremely unexpected.) | they appear within a single- | > | | quoted string, and vice versa. | > +----------------------------------+----------------------------------+ > | Arbitrary characters may be | Backslashes may be used to cause | > | backslash-escaped to make them a | the next character to be | > | literal component of a word | appended to the current word | > | rather than being parsed as | verbatim. This is only useful | > | quotes or word separators. | when used to escape quotes, | > | | spaces, and backslashes, but for | > | | simplicity we allow backslash- | > | | escaping anything. | > +----------------------------------+----------------------------------+ > | Each word should be a variable | After splitting the command line | > | assignment in the format | into words, each word is checked | > | ``variable'' or | to see if it contains an equals | > | ``variable=value''. | sign. | > +----------------------------------+----------------------------------+ > | If a variable name and value are | If it does, it is split on the | > | both specified, the variable | equals sign into a key-value | > | will be set to the specified | pair. The key is then treated as | > | value. | a variable name, and the value | > | | treated as the variable's value. | > +----------------------------------+----------------------------------+ > | If only a variable name is | If it does not, the entire word | > | specified, the variable's value | is treated as a variable name. | > | will be set to ``1''. | The variable's value is | > | | implicitly considered to be '1'. | > +----------------------------------+----------------------------------+ > | Variable names must begin with | All variables detected on the | > | the string ``xen_grub_env_''... | command line are checked to see | > | If any variable contains an | if their names begin with the | > | illegal name, that variable will | string `xen_grub_env_`. | > | be ignored. | Variables that do not pass this | > | | check are discarded, | > +----------------------------------+----------------------------------+ > | ...you can pass environment | variables that do pass this | > | variables from Xen's dom0 to the | check are exported so they are | > | VM through the Xen-provided | available to the GRUB | > | kernel command line. | configuration. | > +----------------------------------+----------------------------------+ > > The only missing detail I see is that single quotes are legal in > double-quoted strings and vice versa, though I guess I can make it more > explicit that the variables passed on the command line are exported > before getting to the example that shows this. Is there anything else > you see that's missing? Exactly, I was thing about single/double quotes here. If other stuff is in the documentation then OK... > > > + */ > > > + > > > + current_word_len = PARSER_BASE_WORD_LEN; > > > + current_word = grub_malloc (current_word_len); > > > + if (current_word == NULL) > > > + goto cleanup; > > > + > > > + for (i = 0; i < MAX_GUEST_CMDLINE; i++) > > > + { > > > + if (cmdline[i] == '\0') > > > + { > > > + cmdline_valid = true; > > > + break; > > > + } > > > + } > > > + > > > + if (cmdline_valid == false) > > > + { > > > + grub_error (GRUB_ERR_BAD_ARGUMENT, > > > + "Command line from Xen is not NUL-terminated"); > > > > GRUB errors usually start with lowercase... > > Will fix. > > > > + grub_print_error (); > > > + goto cleanup; > > > + } > > > + > > > + cmdline_len = grub_strlen (cmdline); > > > + for (i = 0; i < cmdline_len; i++) > > > + { > > > + current_char = cmdline[i]; > > > + > > > + /* > > > + * If the previous character was a backslash, append the > > > current > > > + * character to the word verbatim > > > + */ > > > + if (parse_flags & PARSER_HIT_BACKSLASH) > > > > s/parse_flags/parser_state/ > > Hmm, I don't like 'parser_state' as a name because the parser's "state" > is the global variables in `grub-core/kern/xen/cmdline.`. Maybe > 'splitter_state' instead, since this is just the bit of state that the > word splitter is concerned with? I am OK with both... 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Mon, 04 Aug 2025 08:19:38 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 17:19:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 03/20] xen/riscv: introduce VMID allocation and manegement To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > Current implementation is based on x86's way to allocate VMIDs: > VMIDs partition the physical TLB. In the current implementation VMIDs are > introduced to reduce the number of TLB flushes. Each time the guest's > virtual address space changes, virtual? > instead of flushing the TLB, a new VMID is > assigned. This reduces the number of TLB flushes to at most 1/#VMIDs. > The biggest advantage is that hot parts of the hypervisor's code and data > retain in the TLB. > > VMIDs are a hart-local resource. As preemption of VMIDs is not possible, > VMIDs are assigned in a round-robin scheme. To minimize the overhead of > VMID invalidation, at the time of a TLB flush, VMIDs are tagged with a > 64-bit generation. Only on a generation overflow the code needs to > invalidate all VMID information stored at the VCPUs with are run on the > specific physical processor. This overflow appears after about 2^80 > host processor cycles, Where's this number coming from? (If you provide numbers, I think they will want to be "reproducible" by the reader. Which I fear isn't the case here.) > @@ -148,6 +149,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, > > console_init_postirq(); > > + vmid_init(); This lives here only temporarily, I assume? Every hart will need to execute it, and hence (like we have it on x86) this may want to be a central place elsewhere. > --- /dev/null > +++ b/xen/arch/riscv/vmid.c > @@ -0,0 +1,165 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +/* Xen command-line option to enable VMIDs */ > +static bool __read_mostly opt_vmid_enabled = true; __ro_after_init ? > +boolean_param("vmid", opt_vmid_enabled); > + > +/* > + * VMIDs partition the physical TLB. In the current implementation VMIDs are > + * introduced to reduce the number of TLB flushes. Each time the guest's > + * virtual address space changes, instead of flushing the TLB, a new VMID is The same odd "virtual" again? All the code here is about guest-physical, isn't it? > + * assigned. This reduces the number of TLB flushes to at most 1/#VMIDs. > + * The biggest advantage is that hot parts of the hypervisor's code and data > + * retain in the TLB. > + * > + * Sketch of the Implementation: > + * > + * VMIDs are a hart-local resource. As preemption of VMIDs is not possible, > + * VMIDs are assigned in a round-robin scheme. To minimize the overhead of > + * VMID invalidation, at the time of a TLB flush, VMIDs are tagged with a > + * 64-bit generation. Only on a generation overflow the code needs to > + * invalidate all VMID information stored at the VCPUs with are run on the > + * specific physical processor. This overflow appears after about 2^80 And the same interesting number again. > + * host processor cycles, so we do not optimize this case, but simply disable > + * VMID useage to retain correctness. > + */ > + > +/* Per-Hart VMID management. */ > +struct vmid_data { > + uint64_t hart_vmid_generation; Any reason not to simply use "generation"? > + uint16_t next_vmid; > + uint16_t max_vmid; > + bool disabled; > +}; > + > +static DEFINE_PER_CPU(struct vmid_data, vmid_data); > + > +static unsigned long vmidlen_detect(void) __init ? Or wait, are you (deliberately) permitting different VMIDLEN across harts? > +{ > + unsigned long vmid_bits; Why "long" (also for the function return type)? > + unsigned long old; > + > + /* Figure-out number of VMID bits in HW */ > + old = csr_read(CSR_HGATP); > + > + csr_write(CSR_HGATP, old | HGATP_VMID_MASK); > + vmid_bits = csr_read(CSR_HGATP); > + vmid_bits = MASK_EXTR(vmid_bits, HGATP_VMID_MASK); Nit: Stray blank. > + vmid_bits = flsl(vmid_bits); > + csr_write(CSR_HGATP, old); > + > + /* > + * We polluted local TLB so flush all guest TLB as > + * a speculative access can happen at any time. > + */ > + local_hfence_gvma_all(); There's no guest running. If you wrote hgat.MODE as zero, as per my understanding now new TLB entries could even purely theoretically appear. In fact, with no guest running (yet) I'm having a hard time seeing why you shouldn't be able to simply write the register with just HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable whether "old" needs restoring; writing plain zero afterwards ought to suffice. You're in charcge of the register, after all. > + return vmid_bits; > +} > + > +void vmid_init(void) > +{ > + static bool g_disabled = false; > + unsigned long vmid_len = vmidlen_detect(); > + struct vmid_data *data = &this_cpu(vmid_data); > + unsigned long max_availalbe_bits = sizeof(data->max_vmid) << 3; Nit: Typo in "available". Also now that we have it, better use BITS_PER_BYTE here? > + if ( vmid_len > max_availalbe_bits ) > + panic("%s: VMIDLEN is bigger then a type which represent VMID: %lu(%lu)\n", > + __func__, vmid_len, max_availalbe_bits); This shouldn't be a runtime check imo. What you want to check (at build time) is that the bits set in HGATP_VMID_MASK can be held in ->max_vmid. > + data->max_vmid = BIT(vmid_len, U) - 1; > + data->disabled = !opt_vmid_enabled || (vmid_len <= 1); Actually, what exactly does it mean that "VMIDs are disabled"? There's no enable bit that I could find anywhere. Isn't it rather that in this case you need to arrange to flush always on VM entry (or always after a P2M change, depending how the TLB is split between guest and host use)? If you look at vmx_vmenter_helper(), its flipping of SECONDARY_EXEC_ENABLE_VPID tweaks CPU behavior, such that the flush would be implicit (when the bit is off). I don't expect RISC-V has any such "implicit" flushing behavior? > + if ( g_disabled != data->disabled ) > + { > + printk("%s: VMIDs %sabled.\n", __func__, > + data->disabled ? "dis" : "en"); > + if ( !g_disabled ) > + g_disabled = data->disabled; This doesn't match x86 code. g_disabled is a tristate there, which only the boot CPU would ever write to. A clear shortcoming of the x86 code (that you copied) is that the log message doesn't identify the CPU in question. A sequence of "disabled" and "enabled" could thus result, without the last one (or in fact any one) making clear what the overall state is. I think you want to avoid this from the beginning. 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Mon, 04 Aug 2025 08:24:07 -0700 (PDT) Content-Type: multipart/alternative; boundary="------------0o3XCAYF34QNn0CFpsFhcHsn" Message-ID: <4c317d98-a17f-471e-9111-f28bc78924af@gmail.com> Date: Mon, 4 Aug 2025 17:24:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [XEN][PATCH 3/3] xen/riscv: irq: drop unreachable pirq callbacks To: Grygorii Strashko , "xen-devel@lists.xenproject.org" Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini References: <20250801100852.1260544-1-grygorii_strashko@epam.com> <20250801100852.1260544-4-grygorii_strashko@epam.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <20250801100852.1260544-4-grygorii_strashko@epam.com> This is a multi-part message in MIME format. --------------0o3XCAYF34QNn0CFpsFhcHsn Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/1/25 12:08 PM, Grygorii Strashko wrote: > From: Grygorii Strashko > > Hence all common pIRQ code is under CONFIG_HAS_PIRQ idefs corresponding > RISCV arch pIRQ callbacks become unreachable, so drop them. > > Signed-off-by: Grygorii Strashko > --- > xen/arch/riscv/stubs.c | 20 -------------------- > 1 file changed, 20 deletions(-) > > diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c > index 8918cebf35c6..1a8c86cd8da2 100644 > --- a/xen/arch/riscv/stubs.c > +++ b/xen/arch/riscv/stubs.c > @@ -82,26 +82,6 @@ void smp_send_call_function_mask(const cpumask_t *mask) > > /* irq.c */ > > -struct pirq *alloc_pirq_struct(struct domain *d) > -{ > - BUG_ON("unimplemented"); > -} > - > -int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) > -{ > - BUG_ON("unimplemented"); > -} > - > -void pirq_guest_unbind(struct domain *d, struct pirq *pirq) > -{ > - BUG_ON("unimplemented"); > -} > - > -void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) > -{ > - BUG_ON("unimplemented"); > -} > - > void irq_ack_none(struct irq_desc *desc) > { > BUG_ON("unimplemented"); LGTM: Reviewed-by: Oleksii Kurochko ~ Oleksii --------------0o3XCAYF34QNn0CFpsFhcHsn Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit


On 8/1/25 12:08 PM, Grygorii Strashko wrote:
From: Grygorii Strashko <grygorii_strashko@epam.com>

Hence all common pIRQ code is under CONFIG_HAS_PIRQ idefs corresponding
RISCV arch pIRQ callbacks become unreachable, so drop them.

Signed-off-by: Grygorii Strashko <grygorii_strashko@epam.com>
---
 xen/arch/riscv/stubs.c | 20 --------------------
 1 file changed, 20 deletions(-)

diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c
index 8918cebf35c6..1a8c86cd8da2 100644
--- a/xen/arch/riscv/stubs.c
+++ b/xen/arch/riscv/stubs.c
@@ -82,26 +82,6 @@ void smp_send_call_function_mask(const cpumask_t *mask)
 
 /* irq.c */
 
-struct pirq *alloc_pirq_struct(struct domain *d)
-{
-    BUG_ON("unimplemented");
-}
-
-int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share)
-{
-    BUG_ON("unimplemented");
-}
-
-void pirq_guest_unbind(struct domain *d, struct pirq *pirq)
-{
-    BUG_ON("unimplemented");
-}
-
-void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask)
-{
-    BUG_ON("unimplemented");
-}
-
 void irq_ack_none(struct irq_desc *desc)
 {
     BUG_ON("unimplemented");

LGTM: Reviewed-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

~ Oleksii
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Mon, 04 Aug 2025 08:31:03 -0700 (PDT) Date: Mon, 4 Aug 2025 17:31:02 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: "Chen, Jiqian" Cc: Andrew Cooper , "xen-devel@lists.xenproject.org" , "Huang, Ray" , Anthony PERARD Subject: Re: [PATCH v9 5/8] vpci: Refactor vpci_remove_register to remove matched registers Message-ID: References: <20250728050401.329510-1-Jiqian.Chen@amd.com> <20250728050401.329510-6-Jiqian.Chen@amd.com> <89058017-141e-4837-a547-10b41b5d041b@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Thu, Jul 31, 2025 at 06:28:14AM +0000, Chen, Jiqian wrote: > On 2025/7/30 19:23, Andrew Cooper wrote: > > On 28/07/2025 6:03 am, Jiqian Chen wrote: > >> vpci_remove_register() only supports removing a register in a time, > >> but the follow-on changes need to remove all registers within a range. > >> So, refactor it to support removing all registers in a given region. > >> > >> And it is no issue to remove a non exist register, so remove the > >> __must_check prefix. > >> > >> Signed-off-by: Jiqian Chen > >> Reviewed-by: Roger Pau Monné > > > > Bisection says this causes an assertion failure in the unit test. > > > > Running /usr/lib/xen/tests/test_vpci > > Assertion failed: vpci_remove_registers(test_pdev.vpci, 16, 2) (main.c: > > main: 407) > > FAILED: /usr/lib/xen/tests/test_vpci > Thanks Andrew. > This is because new function vpci_remove_registers() removes all registers inside (offset, offset + size) and returns failure when overlap happens. > For tools/tests/vpci/main.c, there are layout: > * > * 32 24 16 8 0 > * +------+------+------+------+ > * | r0 | 0 > * +------+------+------+------+ > * | r7 | r6 | r5 |//////| 4 > * +------+------+------+------| > * |///////////////////////////| 8 > * +-------------+-------------+ > * |/////////////| r12 | 12 > * +------+------+------+------+ > * |r16[3]|r16[2]|r16[1]|r16[0]| 16 > * +------+------+------+------+ > * | r20[1] | r20[0] | 20 > * +-------------+-------------| > * | r24 | 24 > * +------+------+------+------+ > * |//////| r30 |//////| r28 | 28 > * +------+------+------+------+ > * |rsvdz |rsvdp | rw1c | ro | 32 > * +------+------+------+------+ > * > As for the last three test cases: > VPCI_REMOVE_INVALID_REG(20, 1); > This can success as this overlap with r20[0] > VPCI_REMOVE_INVALID_REG(16, 2); > VPCI_REMOVE_INVALID_REG(30, 2); > These two fail as there are r16[0], r16[1] and r30 inside them, so remove success and test cases fail. Yes, given that vpci_remove_registers() can now remove multiple handlers in one call those two tests are simply not correct given the new behavior of the function. > So, I think we need to change these two test cases to match the new function's logic, like: > VPCI_REMOVE_INVALID_REG(0, 2); > VPCI_REMOVE_INVALID_REG(2, 2); Those two test exactly the same as the (20, 1) call, so I think they don't add value to the testing. I would convert them into valid test cases, so: VPCI_REMOVE_REG(16, 2); VPCI_REMOVE_REG(30, 2); Because they now test the new functionality of removing multiple handlers with a single call (or removing a handler while dealing with padding on the sides). Thanks, Roger. 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Split the BSP action from the AP one, indicating the odd CPU in the AP log message, thus avoiding the impression that global state would have changed. While there also - move g_disabled into .data.ro_after_init; only the BSP will ever write to it, - make the function's parameter unsigned; no negative values may be passed in. Also reflect this in svm_asid_init(). Signed-off-by: Jan Beulich --- a/xen/arch/x86/hvm/asid.c +++ b/xen/arch/x86/hvm/asid.c @@ -48,20 +48,22 @@ struct hvm_asid_data { static DEFINE_PER_CPU(struct hvm_asid_data, hvm_asid_data); -void hvm_asid_init(int nasids) +void hvm_asid_init(unsigned int nasids) { - static int8_t g_disabled = -1; + static int8_t __ro_after_init g_disabled = -1; struct hvm_asid_data *data = &this_cpu(hvm_asid_data); data->max_asid = nasids - 1; data->disabled = !opt_asid_enabled || (nasids <= 1); - if ( g_disabled != data->disabled ) + if ( g_disabled < 0 ) { - printk("HVM: ASIDs %sabled.\n", data->disabled ? "dis" : "en"); - if ( g_disabled < 0 ) - g_disabled = data->disabled; + g_disabled = data->disabled; + printk("HVM: ASIDs %sabled\n", data->disabled ? "dis" : "en"); } + else if ( g_disabled != data->disabled ) + printk("HVM: CPU%u: ASIDs %sabled\n", smp_processor_id(), + data->disabled ? "dis" : "en"); /* Zero indicates 'invalid generation', so we start the count at one. */ data->core_asid_generation = 1; --- a/xen/arch/x86/hvm/svm/asid.c +++ b/xen/arch/x86/hvm/svm/asid.c @@ -12,7 +12,7 @@ void svm_asid_init(const struct cpuinfo_x86 *c) { - int nasids = 0; + unsigned int nasids = 0; /* Check for erratum #170, and leave ASIDs disabled if it's present. */ if ( !cpu_has_amd_erratum(c, AMD_ERRATUM_170) ) --- a/xen/arch/x86/include/asm/hvm/asid.h +++ b/xen/arch/x86/include/asm/hvm/asid.h @@ -13,7 +13,7 @@ struct vcpu; struct hvm_vcpu_asid; /* Initialise ASID management for the current physical CPU. */ -void hvm_asid_init(int nasids); +void hvm_asid_init(unsigned int nasids); /* Invalidate a particular ASID allocation: forces re-allocation. */ void hvm_asid_flush_vcpu_asid(struct hvm_vcpu_asid *asid); From xen-devel-bounces@lists.xenproject.org Mon Aug 04 15:53:12 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 15:53:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069702.1433467 (Exim 4.92) (envelope-from ) id 1uixUq-00048d-1p; Mon, 04 Aug 2025 15:53:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069702.1433467; Mon, 04 Aug 2025 15:53:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uixUp-00048W-TX; Mon, 04 Aug 2025 15:53:07 +0000 Received: by outflank-mailman (input) for mailman id 1069702; Mon, 04 Aug 2025 15:53:07 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uixUp-00047I-4a for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 15:53:07 +0000 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [2a00:1450:4864:20::530]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 1bb42055-714b-11f0-b898-0df219b8e170; Mon, 04 Aug 2025 17:53:05 +0200 (CEST) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-615c29fc31eso7059956a12.0 for ; Mon, 04 Aug 2025 08:53:05 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Mon, 04 Aug 2025 08:53:04 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 17:53:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 04/20] xen/riscv: introduce things necessary for p2m initialization To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/include/asm/p2m.h > +++ b/xen/arch/riscv/include/asm/p2m.h > @@ -3,11 +3,45 @@ > #define ASM__RISCV__P2M_H > > #include > +#include > +#include > +#include > > #include > > #define paddr_bits PADDR_BITS > > +/* Get host p2m table */ > +#define p2m_get_hostp2m(d) (&(d)->arch.p2m) > + > +/* Per-p2m-table state */ > +struct p2m_domain { > + /* > + * Lock that protects updates to the p2m. > + */ > + rwlock_t lock; > + > + /* Pages used to construct the p2m */ > + struct page_list_head pages; > + > + /* Indicate if it is required to clean the cache when writing an entry */ > + bool clean_pte; I'm a little puzzled by this field still being here, despite the extensive revlog commentary. If you really feel you need to keep it, please ... > + /* Back pointer to domain */ > + struct domain *domain; > + > + /* > + * P2M updates may required TLBs to be flushed (invalidated). > + * > + * Flushes may be deferred by setting 'need_flush' and then flushing > + * when the p2m write lock is released. > + * > + * If an immediate flush is required (e.g, if a super page is > + * shattered), call p2m_tlb_flush_sync(). > + */ > + bool need_flush; ... group booleans together, for better packing. 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Mon, 04 Aug 2025 08:58:55 -0700 (PDT) Message-ID: Date: Mon, 4 Aug 2025 17:58:54 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 05/20] xen/riscv: construct the P2M pages pool for guests To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <4e7de8ffc929c1bdfa28b40fdd31b814acef103c.1753973161.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4e7de8ffc929c1bdfa28b40fdd31b814acef103c.1753973161.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > Implement p2m_set_allocation() to construct p2m pages pool for guests > based on required number of pages. > > This is implemented by: > - Adding a `struct paging_domain` which contains a freelist, a > counter variable and a spinlock to `struct arch_domain` to > indicate the free p2m pages and the number of p2m total pages in > the p2m pages pool. > - Adding a helper `p2m_set_allocation` to set the p2m pages pool > size. This helper should be called before allocating memory for > a guest and is called from domain_p2m_set_allocation(), the latter > is a part of common dom0less code. > - Adding paging_freelist_init() to struct paging_domain. > > Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich From xen-devel-bounces@lists.xenproject.org Mon Aug 04 16:58:27 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 16:58:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069732.1433486 (Exim 4.92) (envelope-from ) id 1uiyVs-0002f8-NV; Mon, 04 Aug 2025 16:58:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069732.1433486; Mon, 04 Aug 2025 16:58:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uiyVs-0002f1-Kf; Mon, 04 Aug 2025 16:58:16 +0000 Received: by outflank-mailman (input) for mailman id 1069732; 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pr=C Message-ID: Date: Mon, 4 Aug 2025 12:57:57 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create To: Jan Beulich CC: Andrew Cooper , Anthony PERARD , Michal Orzel , "Julien Grall" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , "Dario Faggioli" , Juergen Gross , George Dunlap , References: <20250801202418.38977-1-stewart.hildebrand@amd.com> <52ea4f10-26b4-447b-8753-0e4287a03408@suse.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: <52ea4f10-26b4-447b-8753-0e4287a03408@suse.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003448:EE_|CY5PR12MB9054:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cf2b97f-30dc-4400-dfa8-08ddd378150e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|36860700013|376014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 16:58:05.8490 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cf2b97f-30dc-4400-dfa8-08ddd378150e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003448.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB9054 On 8/4/25 03:57, Jan Beulich wrote: > On 01.08.2025 22:24, Stewart Hildebrand wrote: >> @@ -839,6 +839,9 @@ void sched_destroy_vcpu(struct vcpu *v) >> { >> struct sched_unit *unit = v->sched_unit; >> >> + if ( !unit ) >> + return; >> + >> kill_timer(&v->periodic_timer); >> kill_timer(&v->singleshot_timer); >> kill_timer(&v->poll_timer); > > What if it's the 2nd error path in sched_init_vcpu() that is taken? Then we > might take this path (just out of context here) > > if ( unit->vcpu_list == v ) > { > rcu_read_lock(&sched_res_rculock); > > sched_remove_unit(vcpu_scheduler(v), unit); > sched_free_udata(vcpu_scheduler(v), unit->priv); > > and at least Credit1's hook doesn't look to be safe against being passed NULL. > (Not to speak of the risk of unit->priv being used elsewhere while cleaning > up.) > > Jan Are you referring to this error path in sched_init_vcpu? unit->priv = sched_alloc_udata(dom_scheduler(d), unit, d->sched_priv); if ( unit->priv == NULL ) { sched_free_unit(unit, v); rcu_read_unlock(&sched_res_rculock); return 1; } If so, my understanding is that sched_free_unit sets v->sched_unit = NULL, so sched_destroy_vcpu (with this patch applied) would return before reaching that just-out-of-context condition. Albeit I have not yet tested this with any sort of non-default scheduling granularity, so I could have missed something... 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV2PR03MB9572.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d9f165e6-0890-4e41-3275-08ddd37d01df X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Aug 2025 17:33:21.1837 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vQRBnUNWtXaRPWEhBlwkcETJto30R3olD9Y09FJ7fm/EiCG+m2KPdt3WNsHYxeAVvL9rIbsrvxTZCHxv4yBN5I2f2wbEzVTpx5cRoVwzWYM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR03MB9510 MISRA Rule 16.4: Every switch statement shall have a default label. The default clause must contain either a statement or a comment prior to its terminating break statement. However, there is a documented deviation for this rule in Xen: 'docs/misra/deviations.rst': * - R16.4 - A switch statement with a single clause and no default label may replace an equivalent if statement to improve readability. - Tagged as `deliberate` for ECLAIR. This change removes empty default cases in single-clause switches to avoid violations of the rule where the `default` clause lacks a suitable comment or statement. Signed-off-by: Dmytro Prokopchuk --- Test CI pipeline: https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1965255558 --- xen/arch/arm/cpuerrata.c | 2 -- xen/arch/arm/gic.c | 2 -- xen/arch/arm/mmu/p2m.c | 2 -- xen/arch/arm/time.c | 2 -- xen/common/kexec.c | 2 -- 5 files changed, 10 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 17cf134f1b..4e84bc66fc 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -734,8 +734,6 @@ static int cpu_errata_callback(struct notifier_block *n= fb, ASSERT(system_state !=3D SYS_STATE_boot); rc =3D enable_nonboot_cpu_caps(arm_errata); break; - default: - break; } =20 return notifier_from_errno(rc); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index e80fe0ca24..4f06ab9f0f 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -435,8 +435,6 @@ static int cpu_gic_callback(struct notifier_block *nfb, /* This is reverting the work done in init_maintenance_interrupt *= / release_irq(gic_hw_ops->info->maintenance_irq, NULL); break; - default: - break; } =20 return NOTIFY_DONE; diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c index 51abf3504f..f53b93847a 100644 --- a/xen/arch/arm/mmu/p2m.c +++ b/xen/arch/arm/mmu/p2m.c @@ -1827,8 +1827,6 @@ static int cpu_virt_paging_callback(struct notifier_b= lock *nfb, ASSERT(system_state !=3D SYS_STATE_boot); setup_virt_paging_one(NULL); break; - default: - break; } =20 return NOTIFY_DONE; diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index e74d30d258..0ccfd3b12d 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -381,8 +381,6 @@ static int cpu_time_callback(struct notifier_block *nfb= , case CPU_DYING: deinit_timer_interrupt(); break; - default: - break; } =20 return NOTIFY_DONE; diff --git a/xen/common/kexec.c b/xen/common/kexec.c index 84fe8c3597..bb669da833 100644 --- a/xen/common/kexec.c +++ b/xen/common/kexec.c @@ -548,8 +548,6 @@ static int cf_check cpu_callback( * fail the CPU_UP_PREPARE */ kexec_init_cpu_notes(cpu); break; - default: - break; } return NOTIFY_DONE; } --=20 2.43.0 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 20:31:53 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 20:31:53 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069825.1433522 (Exim 4.92) (envelope-from ) id 1uj1qJ-0007yZ-Ko; Mon, 04 Aug 2025 20:31:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069825.1433522; Mon, 04 Aug 2025 20:31:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj1qJ-0007yS-H7; Mon, 04 Aug 2025 20:31:35 +0000 Received: by outflank-mailman (input) for mailman id 1069825; Mon, 04 Aug 2025 20:31:34 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj1qI-0007yM-GG for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 20:31:34 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1uj1qI-001D41-0r for xen-devel@lists.xenproject.org; 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We=E2=80=99d love for you to jo= in. Feel free to participate or just observe. This call is a great opportunity to see what the community is working on, align our various efforts, and share updates. Everyone is welcome! *Preparation:* - Add any proposed agenda items or missing action items: https://cryptpad.fr/pad/#/2/pad/edit/ELpO7rzIdKPuQrSmizBUUf4L/ - If any action items have been resolved or are no longer relevant, feel free to remove them from the doc. *Call Details:* - *Date:* Thursday, 7 August 2025 - *Time:* 15:00 UTC (agenda begins at 15:05 UTC) - Find your local timezone here - *Link to Join the Call:* https://meet.jit.si/XenProjectCommunityCall We plan to open the meeting room at 15:00 UTC, but to allow time for switching between meetings and handling any technical issues, we=E2=80=99ll officially start discussing the agenda at 15:05 UTC. *Want to be CC=E2=80=99d on future calls?* Add or remove yourself from our Sign-up Sheet . See you on thursday! Cody Zuschlag Xen Project - Community Manager --0000000000005502cd063b8ffe41 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi everyone,

We=E2=80= =99re getting ready for August's Xen Project=C2=A0Community Call=C2=A0on=C2=A0Thursday, 7 August 2025=C2=A0= at=C2=A015:00 UTC=C2=A0(4 pm UK time). We=E2=80=99d love for you to = join. Feel free to participate or just observe. This=C2=A0call=C2=A0is a great opportunity to see what the=C2=A0community=C2=A0is working on, align our various e= fforts, and share updates. Everyone is welcome!

Preparation= :

Call=C2=A0Details:

We plan to open the meeting room at 15:00 UTC, but to all= ow time for switching between meetings and handling any technical issues, w= e=E2=80=99ll officially start discussing the agenda at 15:05 UTC.

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x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; boundary="Sig_/c21vzwXoh5w2G7dTvpTKCZK"; protocol="application/pgp-signature"; micalg=pgp-sha512 --Sig_/c21vzwXoh5w2G7dTvpTKCZK Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Mon, 4 Aug 2025 17:17:43 +0200 Daniel Kiper wrote: > On Sun, Aug 03, 2025 at 10:57:03AM -0500, Aaron Rainbolt wrote: > > On Fri, 1 Aug 2025 14:55:36 +0200 Daniel Kiper > > wrote: =20 > > > On Fri, Jul 25, 2025 at 03:31:12PM -0500, Aaron Rainbolt wrote: =20 > > > > Xen traditionally allows customizing guest behavior by passing > > > > arguments to the VM kernel via the kernel command line. This is > > > > no longer possible when using GRUB with Xen, as the kernel > > > > command line is decided by the GRUB configuration file within > > > > the guest, not data passed to the guest by Xen. > > > > > > > > To work around this limitation, enable GRUB to parse a command > > > > line passed to it by Xen, and expose data from the command line > > > > to the GRUB configuration as environment variables. These > > > > variables can be used in the GRUB configuration for any desired > > > > purpose, such as extending the kernel command line passed to > > > > the guest. The command line format is inspired by the Linux > > > > kernel's command line format. > > > > > > > > To reduce the risk of misuse, abuse, or accidents in > > > > production, the command line will only be parsed if it consists > > > > entirely of 7-bit ASCII characters, only alphabetical > > > > characters and underscores are permitted in variable names, and > > > > all variable names must start with the string "xen_grub_env_". > > > > This also allows room for expanding the command line arguments > > > > accepted by GRUB in the future, should other arguments end up > > > > becoming desirable in the future. > > > > > > > > Signed-off-by: Aaron Rainbolt > > > > --- > > > > docs/grub.texi | 50 +++++ > > > > grub-core/Makefile.core.def | 2 + > > > > grub-core/kern/i386/xen/pvh.c | 14 ++ > > > > grub-core/kern/main.c | 12 ++ > > > > grub-core/kern/xen/cmdline.c | 343 > > > > ++++++++++++++++++++++++++++++++++ include/grub/xen.h > > > > | 2 + 6 files changed, 423 insertions(+) > > > > create mode 100644 grub-core/kern/xen/cmdline.c > > > > > > > > diff --git a/docs/grub.texi b/docs/grub.texi > > > > index 34b3484..ce82483 100644 > > > > --- a/docs/grub.texi > > > > +++ b/docs/grub.texi > > > > @@ -3271,6 +3271,7 @@ GRUB. Others may be used freely in GRUB > > > > configuration files. @menu > > > > * Special environment variables:: > > > > * Environment block:: > > > > +* Passing environment variables through Xen:: > > > > @end menu > > > > > > > > > > > > @@ -3871,6 +3872,55 @@ using BIOS or EFI functions (no ATA, USB > > > > or IEEE1275). @command{grub-mkconfig} uses this facility to > > > > implement @samp{GRUB_SAVEDEFAULT} (@pxref{Simple > > > > configuration}). > > > > > > > > +@node Passing environment variables through Xen > > > > +@section Passing environment variables through Xen > > > > + > > > > +If you are using a GRUB image as the kernel for a PV or PVH Xen > > > > virtual +machine, you can pass environment variables from Xen's > > > > dom0 to the VM through +the Xen-provided kernel command line. > > > > When combined with a properly configured +guest, this can be > > > > used to customize the guest's behavior on bootup via the +VM's > > > > Xen configuration file. + > > > > +GRUB will parse the kernel command line passed to it by Xen > > > > during bootup. +The command line will be split into > > > > space-delimited words. Single and +double quotes may be used to > > > > quote words or portions of words that contain +spaces. > > > > Arbitrary characters may be backslash-escaped to make them a > > > > literal +component of a word rather than being parsed as quotes > > > > or word separators. The +command line must consist entirely of > > > > printable 7-bit ASCII characters and +spaces. If a non-printing > > > > ASCII character is found anywhere in the command +line, the > > > > entire command line will be ignored by GRUB. + +Each word > > > > should be a variable assignment in the format ``variable'' or > > > > +``variable=3Dvalue''. Variable names must contain only the > > > > characters A-Z, a-z, +and underscore (``_''). Variable names > > > > must begin with the string +``xen_grub_env_''. Variable values > > > > can contain arbitrary printable 7-bit +ASCII characters and > > > > space. If any variable contains an illegal name, that +variable > > > > will be ignored. + +If a variable name and value are both > > > > specified, the variable will be set to +the specified value. If > > > > only a variable name is specified, the variable's +value will > > > > be set to ``1''. + > > > > +The following is a simple example of how to use this > > > > functionality to append +arbitrary variables to a guest's > > > > kernel command line: + > > > > +@example > > > > +# In the Xen configuration file for the guest > > > > +name =3D "linux_vm" > > > > +type =3D "pvh" > > > > +kernel =3D "/path/to/grub-i386-xen_pvh.bin" > > > > +extra =3D "xen_grub_env_kernelappend=3D'loglevel=3D3'" =20 > > > > > > s/kernelappend/kernel_append/ > > > > > > or maybe even > > > > > > s/kernelappend/linux_append/ > > > > > > to make it clear it is appended to the "linux" command line... =20 > > > > Will do. > > =20 > > > > +memory =3D 1024 > > > > +disk =3D [ "file:/srv/vms/linux_vm.img,sda,w" ] > > > > + > > > > +# In the guest's GRUB configuration file > > > > +menuentry "Linux VM with dom0-specified kernel parameters" @{ > > > > + search --set=3Droot --label linux_vm --hint hd0,msdos1 > > > > + linux /boot/vmlinuz root=3DLABEL=3Dlinux_vm > > > > $@{xen_grub_env_kernelappend@} =20 > > > > > > Ditto... =20 > > > > Will do. > > =20 > > > > + initrd /boot/initrd.img > > > > +@} > > > > +@end example > > > > + > > > > @node Modules > > > > @chapter Modules > > > > > > > > diff --git a/grub-core/Makefile.core.def > > > > b/grub-core/Makefile.core.def index b3f7119..df0f266 100644 > > > > --- a/grub-core/Makefile.core.def > > > > +++ b/grub-core/Makefile.core.def > > > > @@ -248,6 +248,7 @@ kernel =3D { > > > > xen =3D term/xen/console.c; > > > > xen =3D disk/xen/xendisk.c; > > > > xen =3D commands/boot.c; > > > > + xen =3D kern/xen/cmdline.c; > > > > > > > > i386_xen_pvh =3D commands/boot.c; > > > > i386_xen_pvh =3D disk/xen/xendisk.c; > > > > @@ -255,6 +256,7 @@ kernel =3D { > > > > i386_xen_pvh =3D kern/i386/xen/tsc.c; > > > > i386_xen_pvh =3D kern/i386/xen/pvh.c; > > > > i386_xen_pvh =3D kern/xen/init.c; > > > > + i386_xen_pvh =3D kern/xen/cmdline.c; > > > > i386_xen_pvh =3D term/xen/console.c; > > > > > > > > ia64_efi =3D kern/ia64/efi/startup.S; > > > > diff --git a/grub-core/kern/i386/xen/pvh.c > > > > b/grub-core/kern/i386/xen/pvh.c index 91fbca8..12df2d8 100644 > > > > --- a/grub-core/kern/i386/xen/pvh.c > > > > +++ b/grub-core/kern/i386/xen/pvh.c > > > > @@ -321,6 +321,8 @@ void > > > > grub_xen_setup_pvh (void) > > > > { > > > > grub_addr_t par; > > > > + const char *xen_cmdline; > > > > + int i; > > > > > > > > grub_xen_cpuid_base (); > > > > grub_xen_setup_hypercall_page (); > > > > @@ -352,6 +354,18 @@ grub_xen_setup_pvh (void) > > > > grub_xen_mm_init_regions (); > > > > > > > > grub_rsdp_addr =3D pvh_start_info->rsdp_paddr; > > > > + > > > > + xen_cmdline =3D (const char *) pvh_start_info->cmdline_paddr; > > > > + for (i =3D 0; i < MAX_GUEST_CMDLINE; i++) =20 > > > > > > Oh, MAX_GUEST_CMDLINE is a too generic. May I ask you to rename > > > it to GRUB_XEN_MAX_GUEST_CMDLINE? This should be done in separate > > > patch preceding this one. =20 > > > > Sure. > > =20 > > > > + { > > > > + if (xen_cmdline[i] =3D=3D '\0') =20 > > > > > > I cannot see much sense in this check. Please look below... > > > =20 > > > > + { > > > > + grub_strncpy ((char *) > > > > grub_xen_start_page_addr->cmd_line, > > > > + (char *) > > > > pvh_start_info->cmdline_paddr, =20 > > > > > > s/char */const char */ > > > > > > Is it always guaranteed that pvh_start_info->cmdline_paddr have > > > MAX_GUEST_CMDLINE size? If yes then... =20 > > > > It is not guaranteed. I tested this under Qubes OS, and it is > > unfortunately very possible to pass a guest command line longer than > > MAX_GUEST_CMDLINE via pvh_start_info->cmdline_paddr. I do not know > > of any documentation specifying what the "real" maximum length is > > in this instance (if any), but in any event the string ultimately > > has to be crammed into an array that is only MAX_GUEST_CMDLINE > > long. Originally I wrote this to truncate the command line in this > > situation, but later decided that discarding the command line would > > be safer than truncation. =20 >=20 > I think you are confusing source, grub_xen_start_page_addr->cmd_line, > and destination, pvh_start_info->cmdline_paddr. I am asking about the > destination... The destination is grub_xen_start_page_addr->cmd_line. pvh_start_info->cmdline_paddr is the *source*, not the destination. grub_xen_start_page_addr->cmd_line is a MAX_GUEST_CMDLINE-long int8_t array, so yes, the destination is guaranteed to always have MAX_GUEST_CMDLINE size. > > (When booting a VM in PV mode, Xen does guarantee the command line > > will not be longer than MAX_GUEST_CMDLINE and will simply return a > > truncated command line. There is no way to detect this condition to > > my awareness, so in PV mode, we simply live with the truncation > > since we aren't given another option.) =20 >=20 > OK... >=20 > > > grub_memset ((void *) pvh_start_info->cmdline_paddr, 0, > > > MAX_GUEST_CMDLINE); grub_strncpy ((char *) > > > grub_xen_start_page_addr->cmd_line, (const char *) > > > pvh_start_info->cmdline_paddr, MAX_GUEST_CMDLINE - 1); > > > > > > ... and you are done... =20 > > > > This would truncate the command line rather than discarding it. If > > the goal is consistency with Xen's PV mode, then I can switch to > > this, but I don't like the idea of booting a guest with corrupted > > data inserted randomly into the grub.cfg file. (Like mentioned > > above, there isn't any other option when using PV mode, but just > > because PV mode does things dangerously doesn't mean we have to > > when running in PVH mode.) =20 >=20 > OK, but please remember you have to ensure the string is > NUL-terminated after grub_strncpy(). Potentially you could also use > grub_strlen() to make a check and add NUL in proper place... The code does ensure the string is NUL-terminated I believe, unless grub_strncpy doesn't behave like POSIX strncpy. If a '\0' is found anywhere in pvh_start_info->cmdline_paddr (the source), then we grub_strncpy the string to grub_xen_start_page_addr->cmd_line, specifying the size of the destination buffer as MAX_GUEST_CMDLINE. strncpy pads the rest of the buffer with NUL bytes. In the worst case scenario, the source is exactly MAX_GUEST_CMDLINE-1 bytes long plus a NUL at the end, in which case strncpy will copy MAX_GUEST_CMDLINE-1 bytes and then add one byte of NUL padding. If the sources consists of MAX_GUEST_CMDLINE non-NUL bytes, the copy won't happen at all because a NUL will never be found in the first MAX_GUEST_CMDLINE bytes of the source. Using grub_strlen as a sanity check sounds good. If after the copy, `grub_strlen((char *) grub_xen_start_page_addr->cmd_line) !=3D (i - 1)`, then we know something is wrong and can halt the system. > > > > + MAX_GUEST_CMDLINE); > > > > + break; > > > > + } > > > > + } > > > > } > > > > > > > > grub_err_t > > > > diff --git a/grub-core/kern/main.c b/grub-core/kern/main.c > > > > index 143a232..b4377d3 100644 > > > > --- a/grub-core/kern/main.c > > > > +++ b/grub-core/kern/main.c > > > > @@ -37,6 +37,10 @@ > > > > #include > > > > #endif > > > > > > > > +#if defined (GRUB_MACHINE_XEN) || defined > > > > (GRUB_MACHINE_XEN_PVH) +#include > > > > +#endif > > > > + > > > > static bool cli_disabled =3D false; > > > > static bool cli_need_auth =3D false; > > > > > > > > @@ -351,6 +355,14 @@ grub_main (void) > > > > grub_env_export ("root"); > > > > grub_env_export ("prefix"); > > > > > > > > + /* > > > > + * Parse command line parameters from Xen and export them as > > > > environment > > > > + * variables > > > > + */ > > > > +#if defined (GRUB_MACHINE_XEN) || defined > > > > (GRUB_MACHINE_XEN_PVH) > > > > + grub_parse_xen_cmdline (); =20 > > > > > > Please move this call to the > > > grub-core/kern/xen/init.c:grub_machine_init(). =20 > > > > Will do. > > =20 > > > > +#endif > > > > + > > > > /* Reclaim space used for modules. */ > > > > reclaim_module_space (); > > > > > > > > diff --git a/grub-core/kern/xen/cmdline.c > > > > b/grub-core/kern/xen/cmdline.c new file mode 100644 > > > > index 0000000..03dd88f > > > > --- /dev/null > > > > +++ b/grub-core/kern/xen/cmdline.c > > > > @@ -0,0 +1,343 @@ > > > > +/* > > > > + * GRUB -- GRand Unified Bootloader > > > > + * Copyright (C) 2025 Free Software Foundation, Inc. > > > > + * > > > > + * GRUB is free software: you can redistribute it and/or > > > > modify > > > > + * it under the terms of the GNU General Public License as > > > > published by > > > > + * the Free Software Foundation, either version 3 of the > > > > License, or > > > > + * (at your option) any later version. > > > > + * > > > > + * GRUB is distributed in the hope that it will be useful, > > > > + * but WITHOUT ANY WARRANTY; without even the implied > > > > warranty of > > > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See > > > > the > > > > + * GNU General Public License for more details. > > > > + * > > > > + * You should have received a copy of the GNU General Public > > > > License > > > > + * along with GRUB. If not, see > > > > . > > > > + */ > > > > + > > > > +#include > > > > +#include > > > > +#include > > > > +#include > > > > + > > > > +enum parse_flags > > > > +{ > > > > + PARSER_HIT_BACKSLASH =3D 0x1, > > > > + PARSER_IN_SINGLE_QUOTES =3D 0x2, > > > > + PARSER_IN_DOUBLE_QUOTES =3D 0x4, > > > > +}; =20 > > > typedef parse_flags parse_flags_t; > > > > > > ... and use parse_flags_t instead below... =20 > > > > Will do. > > =20 > > > And probably this should be a local variable... =20 > > > > See below for comments on globals in the parser. > > =20 > > > > + > > > > +#define PARSER_BASE_WORD_LEN 16 =20 > > > > > > This constant begs for a few words of comment... =20 > > > > Will add. This is just the initial length of the dynamically > > allocated buffer for storing each "word" of the command line, but > > it is confusing as written. Perhaps it should be renamed to > > PARSER_WORD_BUF_START_LEN or similar, to make it clear this isn't a > > string length, but a buffer length? =20 >=20 > s/length/size/ then... However, then why 16 not, e.g., 32? My original iteration of the patch didn't require `xen_grub_env_` at the beginning of every variable name, so 16 was a reasonable estimate of how long most "words" would end up, and I wanted to use the smallest reasonable value here. That being said, `xen_grub_env_` is required now, which is already 13 bytes long, so maybe 32 is a more reasonable value. (Or, depending on where GRUB's allocator aligns things, maybe this should be a large number like MAX_GUEST_CMDLINE, so that we don't ever have to reallocate?) > > > > +static grub_size_t word_list_len; > > > > +static char **word_list; > > > > +static grub_size_t current_word_len; > > > > +static grub_size_t current_word_pos; > > > > +static char *current_word; > > > > +static char current_char; =20 > > > > > > I have a feeling that most if not all of this variables should be > > > local in a given function... =20 > > > > I made them globals because making them local would have required an > > awful lot of parameter "shuttling" that I believed made the code > > less readable. For instance, the `append_word_to_list` function > > right now has no parameters and can be called very simply by the > > parser whenever it is needed. If all variables used were local, the > > function would have to have a signature akin to: > > > > static bool append_word_to_list(grub_size_t *current_word_pos_ref, > > grub_size_t *current_word_len_ref, char *current_word, > > grub_size_t *word_list_len_ref, char **word_list) > > > > IMO this is difficult to read and frustrating to call (possibly even > > error-prone). Ultimately the variables are "local" to the parser, > > and the functions are just there to split up the parser's algorithm > > to avoid repetition. They all ultimately operate on the same state, > > so having the state variables static but global within the file > > fits the current parser design well. =20 >=20 > First of all, think about the design. If you are sure it is optimal > then please use struct and a pointer to pass as many argument as you > need... Will do. > > > > +static bool > > > > +append_char_to_word (bool allow_null) > > > > +{ > > > > + /* > > > > + * Fail if the current char is outside of the range 0x20 to > > > > 0x7E. If > > > > + * allow_null is true, make an exception for 0x00. This is a > > > > safeguard =20 > > > > > > Could you elaborate here when allow_null =3D=3D true is useful? =20 > > > > Usually when appending characters to a word, you aren't going to be > > appending null characters, thus `append_char_to_word` usually > > rejects =20 >=20 > s/null/NUL/... Will switch terminology from now on. > > those so as to make it harder to mess things up. However, the string > > does need to be null-terminated, and thus once a command line word > > is =20 >=20 > Ditto... In general, even it is correct, I prefer to use NUL instead > of null/NULL to avoid confusion... >=20 > > fully loaded into current_word, it is necessary to add the null > > terminator on the end. In this instance the parser sets > > `current_char` to '\0' and then calls the `append_char_to_word` > > function with `allow_null` set to true, so that the function knows > > that the addition of a null is intentional here. > > > > (In retrospect, if allow_null is set to true, the only thing > > `append_char_to_word` should append is a null character, it should > > reject anything else in that instance. Otherwise someone could > > accidentally append something other than a null when they meant to > > append a null.) =20 >=20 > Is not it simpler to open code this instead of complicating this > function? Due to the possibility of having to reallocate the buffer, I don't think so. If however we switch to using a buffer than doesn't need reallocation, then it would be simpler to do that. I'll experiment with it before sending the next patch version. > > > > + * against likely-invalid data. > > > > + */ > > > > + if ( (!(current_char >=3D 0x20) || !(current_char <=3D 0x7E) ) = =20 > > > > > > grub_isprint()? =20 > > > > That would work, I wasn't aware that existed. Maybe a mention of > > some valuable GRUB internal API functions that are likely to remain > > stable could be added to the GRUB development manual? (Or just a > > reference to header files where useful things like this are > > defined.) =20 >=20 > Certainly it is a good idea. In general you can assume the GRUB has a > lot of POSIX compatible functions which names are prefixed with > "grub_". Nice, good to know. > > > > + && (current_char !=3D '\0' || allow_null =3D=3D false)) =20 > > > > > > I would drop redundant spaces between "(" and ")" and move "&&" > > > to the end of first line of "if". =20 > > > > Will do, though I'm likely to rewrite this conditional anyway so > > that anything other than '\0' will be rejected when `allow_null =3D=3D > > true`.=20 > > > > + return false; > > > > + > > > > + if (current_word_pos =3D=3D current_word_len) > > > > + { > > > > + current_word_len *=3D 2; =20 > > > > > > You can do this in the argument of the function below... =20 > > > > I mean, yes, technically I can, but that's a lot less readable to > > me. I can't find anywhere else in GRUB that uses that style (using > > `grep -ri '\*=3D'` to search), and can find a few spots that use a > > style similar to the one I've used here: > > > > * `util/grub-install.c` in function `device_map_check_duplicates` > > * `grub-core/osdep/windows/platform.c` in function > > `get_efi_variable` > > * `grub-core/osdep/unix/platform.c` in function `get_ofpathname` > > =20 > > > > + current_word =3D grub_realloc (current_word, > > > > current_word_len); > > > > + if (current_word =3D=3D NULL) > > > > + { > > > > + current_word_len /=3D 2; > > > > + return false; > > > > + } > > > > + } > > > > + > > > > + current_word[current_word_pos] =3D current_char; > > > > + current_word_pos++; =20 > > > > > > Again, you can do this operation in the "[]" above... =20 > > > > Will do. (This does seem to be a much more common way to write > > things in GRUB than what I've done.) > > =20 > > > > + return true; > > > > +} > > > > + > > > > +static bool > > > > +append_word_to_list (void) > > > > +{ > > > > + /* No-op on empty words. */ > > > > + if (current_word_pos =3D=3D 0) =20 > > > > > > This should be probably an argument for the function... =20 > > > > See above for parser state and global variables rationale. > > =20 > > > > + return true; > > > > + > > > > + current_char =3D '\0'; > > > > + if (append_char_to_word (true) =3D=3D false) > > > > + { > > > > + grub_error (GRUB_ERR_BUG, > > > > + "couldn't append null terminator to word > > > > during Xen cmdline parsing"); > > > > + grub_print_error (); > > > > + grub_exit (); > > > > + } > > > > + > > > > + current_word_len =3D grub_strlen (current_word) + 1; > > > > + current_word =3D grub_realloc (current_word, current_word_len); > > > > + if (current_word =3D=3D NULL) > > > > + return false; > > > > + word_list_len++; =20 > > > > > > Again this, OK ++word_list_len to be precise, can be done in a > > > function argument below... =20 > > > > `grep -ri 'alloc.*++'` doesn't show me any instance of this style > > anywhere else in the GRUB codebase, and I find it much more > > difficult to read since now I have to think about incrementing > > `word_list_len`'s value and returning it and multiplying the > > returned value all at the same time. > > `grub-core/osdep/unix/platform.c` uses the style I've used here. > > =20 > > > > + word_list =3D grub_realloc (word_list, word_list_len * sizeof > > > > (char *)); =20 >=20 > word_list =3D grub_realloc (word_list, ++word_list_len * sizeof (char > *a)); >=20 > Is it really difficult to read? I do not think so... I find it harder to read personally, but I'm fine with switching to it if you'd prefer. > [...] >=20 > > > > +void > > > > +grub_parse_xen_cmdline (void) > > > > +{ > > > > + const char *cmdline =3D (const char *) > > > > grub_xen_start_page_addr->cmd_line; > > > > + grub_size_t cmdline_len; > > > > + bool cmdline_valid =3D false; > > > > + char **param_keys =3D NULL; > > > > + char **param_vals =3D NULL; > > > > + grub_size_t param_dict_len =3D 0; > > > > + grub_size_t param_dict_pos =3D 0; > > > > + enum parse_flags parse_flags =3D 0; > > > > + grub_size_t i =3D 0; > > > > + > > > > + /* > > > > + * The following algorithm is used to parse the Xen command > > > > line: > > > > + * > > > > + * - The command line is split into space-separated words. > > > > + * - Single and double quotes may be used to suppress the > > > > splitting > > > > + * behavior of spaces. > > > > + * - Double quotes are appended to the current word > > > > verbatim if they > > > > + * appear within a single-quoted string portion, and vice > > > > versa. > > > > + * - Backslashes may be used to cause the next character > > > > to be > > > > + * appended to the current word verbatim. This is only > > > > useful when > > > > + * used to escape quotes, spaces, and backslashes, but > > > > for simplicity > > > > + * we allow backslash-escaping anything. > > > > + * - After splitting the command line into words, each word > > > > is checked to > > > > + * see if it contains an equals sign. > > > > + * - If it does, it is split on the equals sign into a > > > > key-value pair. The > > > > + * key is then treated as an variable name, and the > > > > value is treated as > > > > + * the variable's value. > > > > + * - If it does not, the entire word is treated as a > > > > variable name. The > > > > + * variable's value is implicitly considered to be `1`. > > > > + * - All variables detected on the command line are checked > > > > to see if their > > > > + * names begin with the string `xen_grub_env_`. Variables > > > > that do not pass > > > > + * this check are discarded, variables that do pass this > > > > check are > > > > + * exported so they are available to the GRUB > > > > configuration. =20 > > > > > > I think not all from this valuable comment landed in the > > > documentation. Please fix it... =20 > > > > Comparing the two side-by-side: > > > > +----------------------------------+----------------------------------+ > > | Documentation | Comment > > | > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ > > | The command line will be split | The command line is split into > > | | into space-delimited words. | space-separated words. > > Single | | Single and double quotes may be | and double quotes > > may be used to | | used to quote words or portions | suppress the > > splitting behavior | | of words that contain spaces. | of > > spaces. | > > +----------------------------------+----------------------------------+ > > | (Self-evident, any other | Double quotes are appended to > > | | behavior involving quotes would | the current word verbatim > > if | | be extremely unexpected.) | they appear within a > > single- | | | quoted string, > > and vice versa. | > > +----------------------------------+----------------------------------+ > > | Arbitrary characters may be | Backslashes may be used to > > cause | | backslash-escaped to make them a | the next character to > > be | | literal component of a word | appended to the > > current word | | rather than being parsed as | verbatim. > > This is only useful | | quotes or word separators. | when > > used to escape quotes, | | | > > spaces, and backslashes, but for | | > > | simplicity we allow backslash- | | > > | escaping anything. | > > +----------------------------------+----------------------------------+ > > | Each word should be a variable | After splitting the command > > line | | assignment in the format | into words, each word > > is checked | | ``variable'' or | to see if it > > contains an equals | | ``variable=3Dvalue''. | sign. > > | > > +----------------------------------+----------------------------------+ > > | If a variable name and value are | If it does, it is split on the > > | | both specified, the variable | equals sign into a > > key-value | | will be set to the specified | pair. The key > > is then treated as | | value. | a > > variable name, and the value | | > > | treated as the variable's value. | > > +----------------------------------+----------------------------------+ > > | If only a variable name is | If it does not, the entire > > word | | specified, the variable's value | is treated as a > > variable name. | | will be set to ``1''. | The > > variable's value is | | | > > implicitly considered to be '1'. | > > +----------------------------------+----------------------------------+ > > | Variable names must begin with | All variables detected on the > > | | the string ``xen_grub_env_''... | command line are checked > > to see | | If any variable contains an | if their names begin > > with the | | illegal name, that variable will | string > > `xen_grub_env_`. | | be ignored. | > > Variables that do not pass this | | > > | check are discarded, | > > +----------------------------------+----------------------------------+ > > | ...you can pass environment | variables that do pass this > > | | variables from Xen's dom0 to the | check are exported so they > > are | | VM through the Xen-provided | available to the GRUB > > | | kernel command line. | configuration. > > | > > +----------------------------------+----------------------------------+ > > > > The only missing detail I see is that single quotes are legal in > > double-quoted strings and vice versa, though I guess I can make it > > more explicit that the variables passed on the command line are > > exported before getting to the example that shows this. Is there > > anything else you see that's missing? =20 >=20 > Exactly, I was thing about single/double quotes here. If other stuff > is in the documentation then OK... Will add. -- Aaron > > > > + */ > > > > + > > > > + current_word_len =3D PARSER_BASE_WORD_LEN; > > > > + current_word =3D grub_malloc (current_word_len); > > > > + if (current_word =3D=3D NULL) > > > > + goto cleanup; > > > > + > > > > + for (i =3D 0; i < MAX_GUEST_CMDLINE; i++) > > > > + { > > > > + if (cmdline[i] =3D=3D '\0') > > > > + { > > > > + cmdline_valid =3D true; > > > > + break; > > > > + } > > > > + } > > > > + > > > > + if (cmdline_valid =3D=3D false) > > > > + { > > > > + grub_error (GRUB_ERR_BAD_ARGUMENT, > > > > + "Command line from Xen is not > > > > NUL-terminated"); =20 > > > > > > GRUB errors usually start with lowercase... =20 > > > > Will fix. > > =20 > > > > + grub_print_error (); > > > > + goto cleanup; > > > > + } > > > > + > > > > + cmdline_len =3D grub_strlen (cmdline); > > > > + for (i =3D 0; i < cmdline_len; i++) > > > > + { > > > > + current_char =3D cmdline[i]; > > > > + > > > > + /* > > > > + * If the previous character was a backslash, append the > > > > current > > > > + * character to the word verbatim > > > > + */ > > > > + if (parse_flags & PARSER_HIT_BACKSLASH) =20 > > > > > > s/parse_flags/parser_state/ =20 > > > > Hmm, I don't like 'parser_state' as a name because the parser's > > "state" is the global variables in `grub-core/kern/xen/cmdline.`. > > Maybe 'splitter_state' instead, since this is just the bit of state > > that the word splitter is concerned with? =20 >=20 > I am OK with both... > > Daniel --Sig_/c21vzwXoh5w2G7dTvpTKCZK Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEEudh48PFXwyPDa0wGpwkWDXPHkQkFAmiRNkAACgkQpwkWDXPH kQkPSQ/9Frq2XLp0/YQsiM2+4usjCt0ms5BtnSXFaEMAk2CDAcyjgJ0Ui3IFZqPe 3kVCrb1tabXNC7BWRpV/bFwPk+mEHF3Uh0o79UqGrp7SY8x7X1tiD51fesAOjCVA gy3USyqR4mxIeJA3qWuAODlzwl6rnNFACC81mxeYpFGP4XFP67Av+UKL6XeVF6vN oWwVZx3rQ6jG6Bz6LbLnBTFsKclEeelVIzy5xLSAzdFY71ETr3bCCNNE4SFVvikp 8TA6ve21suqiIW/geyUAPoNwgvhJgJwHVRSRptxl+mUCeSwclWy6y1we2Z9J//5A 7g++IBadn9ZWFs6qpjKM/JNcyLECceWzhxFLutTupnjnHfR9BqjjpkRZKcbqDY1J VqC4K1vMR9K8K4unKvL6iv8nc5jP3DM1waVqAq06zqrOq/KIjmbqOsSQK+fdLH+X UrdQ8Ayy47nNH4FfeS+7FkTIw9ljI6l+EPfpGrlCLxgVpOHc+QNVRF2Vw08/GfOf pMyC/rXCn51AkmLNwtjSOKNCIim6a1F9MhYzmabWJIYusjWCHHgCowBBm3ncy7gH EO/H1avLBCRcnsQ77OpEohT721UdbzdKLFqXAW2TvTucSsS0mOGSd/qCcADqcBIw MJjIZAlde5Lcs4reuwE+RsH44N1wWI8TrsFLM6WaMA0pRZn2Z90= =2Iiy -----END PGP SIGNATURE----- --Sig_/c21vzwXoh5w2G7dTvpTKCZK-- From xen-devel-bounces@lists.xenproject.org Mon Aug 04 23:27:50 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 23:27:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069860.1433545 (Exim 4.92) (envelope-from ) id 1uj4am-0002hX-1Z; Mon, 04 Aug 2025 23:27:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069860.1433545; Mon, 04 Aug 2025 23:27:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj4al-0002gz-V4; Mon, 04 Aug 2025 23:27:43 +0000 Received: by outflank-mailman (input) for mailman id 1069860; Mon, 04 Aug 2025 23:27:43 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj4ak-0002gt-Dm for xen-devel@lists.xenproject.org; Mon, 04 Aug 2025 23:27:43 +0000 Received: from mail-24417.protonmail.ch (mail-24417.protonmail.ch [109.224.244.17]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 9ce51638-718a-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 01:27:40 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9ce51638-718a-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1754350058; x=1754609258; bh=w3znrRy3Q3UPwv8hAmfKpkieJIJwL4RGvd+2kM8Zvcc=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=hSrh4bGIoU0Fm/DnvyOIX+RaAkZg4PKbfPLqcqwjKuEDOmSsGtIdPgM83E5WhXO7p UkXdlqsEtT0Vgmvz2DoWMbPp6F7oxTITGYMX1ArS6KCPKCUZ4hyQKCfkzXRCDMHT+v S78Hfyys0VLwSfsG3PJ4Ulz/C+QZJGc5D9L1GP8RmfCFG6Pa/PlmnUOsWcyMFpEfN9 0FipfxmaPttk4fKWPayLazKFVpeug9qg1R8Pvb3tJkdnHbxl4oJR5s6dkfGYu4itjl 3w8m5L53izPxZk4gI8Cz46wOD8lb3Z8+xYh2W7h4Zor/NRLgsALknQvLIrbZQ8ii4U DMe4b9PSlYBTg== Date: Mon, 04 Aug 2025 23:27:34 +0000 To: Jan Beulich From: dmkhn@proton.me Cc: "xen-devel@lists.xenproject.org" , Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , =?utf-8?Q?Roger_Pau_Monn=C3=A9?= Subject: Re: [PATCH] console: make printk_ratelimit_{burst,ms} const Message-ID: In-Reply-To: References: <5fcd1c68-6c18-4a1d-8a1d-f056bdb6cde9@suse.com> Feedback-ID: 123220910:user:proton X-Pm-Message-ID: 112008fd4bf757c4e1ff6d9d07ff165ed9ddada8 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Mon, Aug 04, 2025 at 09:10:34AM +0200, Jan Beulich wrote: > On 01.08.2025 20:58, dmkhn@proton.me wrote: > > On Fri, Aug 01, 2025 at 09:30:34AM +0200, Jan Beulich wrote: > >> Them not being altered by any means, their __read_mostly attribute is > >> actually counter-productive: It causes the compiler to instantiate the > >> variables, when already with just the attributes dropped the compiler > >> can constant-propagate the values into the sole use site. Make the > >> situation yet more explicit by adding const. > >> > >> Also switch the variables away from being plain int, and have the > >> parameters of __printk_ratelimit() follow suit. While there also > >> similarly adjust the type of "missed" and "lost", and - while touching > >> the adjacent line - increase lost_str[] to accommodate any unsigned > >> 32-bit number. > >> > >> Fixes: a8b1845a7845 ("Miscellaneous data placement adjustments") > >> Signed-off-by: Jan Beulich > >> --- > >> In principle {__,}printk_ratelimit() may also want to have their retur= n > >> type changed to bool, but I think doing so would go too far here: This > >> would have knock-on effects elsewhere, and it would want considering t= o > >> actually flip polarity. > >> > >> Despite the Fixes: tag I wouldn't consider this for backport. > >> > >> --- a/xen/drivers/char/console.c > >> +++ b/xen/drivers/char/console.c > >> @@ -1268,12 +1268,12 @@ void console_end_sync(void) > >> * This enforces a rate limit: not more than one kernel message > >> * every printk_ratelimit_ms (millisecs). > >> */ > >> -int __printk_ratelimit(int ratelimit_ms, int ratelimit_burst) > >> +int __printk_ratelimit(unsigned int ratelimit_ms, unsigned int rateli= mit_burst) > >> { > >> static DEFINE_SPINLOCK(ratelimit_lock); > >> static unsigned long toks =3D 10 * 5 * 1000; > >> static unsigned long last_msg; > >> - static int missed; > >> + static unsigned int missed; > >> unsigned long flags; > >> unsigned long long now =3D NOW(); /* ns */ > >> unsigned long ms; > >> @@ -1288,14 +1288,16 @@ int __printk_ratelimit(int ratelimit_ms, > >> toks =3D ratelimit_burst * ratelimit_ms; > >> if ( toks >=3D ratelimit_ms ) > >> { > >> - int lost =3D missed; > >> + unsigned int lost =3D missed; > >> + > >> missed =3D 0; > >> toks -=3D ratelimit_ms; > >> spin_unlock(&ratelimit_lock); > >> if ( lost ) > >> { > >> - char lost_str[8]; > >> - snprintf(lost_str, sizeof(lost_str), "%d", lost); > >> + char lost_str[10]; > >> + > >> + snprintf(lost_str, sizeof(lost_str), "%u", lost); > > > > Since this code is touched, I would also simplify the entire `if ( lost= )` > > block (I have it done in another experiment): > > > > char lost_str[64]; > > size_t lost_len =3D snprintf(lost_str, sizeof(lost_str), > > "printk: %d messages suppressed.= \n", > > lost_str); > > > > /* console_lock may already be acquired by printk(). */ > > rspin_lock(&console_lock); > > printk_start_of_line(CONSOLE_PREFIX, cflags); > > __putstr(lost_str, lost_len); > > ... > > > > What do you think? >=20 > Maybe, but definitely not right in this patch. Sure, please consider Reviewed-by: Denis Mukhin =20 From xen-devel-bounces@lists.xenproject.org Mon Aug 04 23:36:44 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Mon, 04 Aug 2025 23:36:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069868.1433556 (Exim 4.92) (envelope-from ) id 1uj4jP-0004LS-TS; Mon, 04 Aug 2025 23:36:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069868.1433556; Mon, 04 Aug 2025 23:36:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj4jP-0004LL-PK; Mon, 04 Aug 2025 23:36:39 +0000 Received: by outflank-mailman (input) for mailman id 1069868; Mon, 04 Aug 2025 23:36:39 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj4jO-0004LF-TS for xen-devel@lists.xenproject.org; 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pr=C Message-ID: <4f5009e6-3099-4f6d-af45-dc7c418f483c@amd.com> Date: Mon, 4 Aug 2025 19:36:24 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create To: Andrew Cooper , CC: Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Dario Faggioli , Juergen Gross , George Dunlap References: <20250801202418.38977-1-stewart.hildebrand@amd.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013B:EE_|SJ5PPF6D27E3EA3:EE_ X-MS-Office365-Filtering-Correlation-Id: d9286db3-61a3-43c9-4663-08ddd3afbb5f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Aug 2025 23:36:27.2250 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9286db3-61a3-43c9-4663-08ddd3afbb5f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPF6D27E3EA3 On 8/3/25 09:19, Andrew Cooper wrote: > On 01/08/2025 9:24 pm, Stewart Hildebrand wrote: >> In vcpu_create after scheduler data is allocated, if >> vmtrace_alloc_buffer fails, it will jump to the wrong cleanup label >> resulting in a memory leak. >> >> Move sched_destroy_vcpu and destroy_waitqueue_vcpu to vcpu_teardown. >> Make vcpu_teardown idempotent: deal with NULL unit. >> >> Fix vcpu_runstate_get (called during XEN_SYSCTL_getdomaininfolist post >> vcpu_teardown) when v->sched_unit is NULL. > > This is unfortunate.  It feels wrong to be updating stats on a domain > that's in the process of being destroyed, especially as a side effect of > a get call. > > But, I wonder if we've uncovered an object lifecycle problem here.  > Previously any vCPU which was addressable in the system (i.e. domid was > addressable, a d->vcpu[x] was not NULL) had a unit. Hm. My understanding is that domain destruction happens in roughly two parts. The first part finishes right away, e.g. before "xl destroy" returns. The 2nd part may be deferred and happens in complete_domain_destroy. There may pass a non-negligible amount of time before complete_domain_destroy runs, giving opportunity for an admin to invoke all sorts of hypercalls from dom0 in the meantime when half-destroyed domains still exist. E.g. see 54fe207f29f8 ("sched/null: avoid another crash after failed domU creation"). Currently, sched_destroy_vcpu happens in complete_domain_destroy (i.e. it's deferred), so half-destroyed domains still have their vcpu data. The present patch moves sched_destroy_vcpu to the first stage of domain destruction, not deferred. A consequence of doing so is that it would open up a non-negligible window for an admin to invoke all sorts of hypercalls while there exists half-destroyed domains with freed vcpus. This is getting to be a bit complex, and it appears there's potential for more fallout. While I'd be happy to make the changes to address your comments below, I wonder if we should consider taking v1 of the patch for now. >> >> Fixes: 217dd79ee292 ("xen/domain: Add vmtrace_size domain creation parameter") >> Signed-off-by: Stewart Hildebrand >> --- >> v1->v2: >> * move cleanup functions to vcpu_teardown >> * renamed, was ("xen: fix memory leak on error in vcpu_create") >> --- >> xen/common/domain.c | 14 ++++++-------- >> xen/common/sched/core.c | 5 ++++- >> 2 files changed, 10 insertions(+), 9 deletions(-) >> >> diff --git a/xen/common/domain.c b/xen/common/domain.c >> index 5241a1629eeb..9c65c2974ea3 100644 >> --- a/xen/common/domain.c >> +++ b/xen/common/domain.c >> @@ -388,6 +388,8 @@ static int vmtrace_alloc_buffer(struct vcpu *v) >> static int vcpu_teardown(struct vcpu *v) >> { >> vmtrace_free_buffer(v); >> + sched_destroy_vcpu(v); >> + destroy_waitqueue_vcpu(v); >> >> return 0; >> } > > Along with this, you want a matching: > > diff --git a/xen/common/domain.c b/xen/common/domain.c > index 5241a1629eeb..3fd75a6d6784 100644 > --- a/xen/common/domain.c > +++ b/xen/common/domain.c > @@ -1412,8 +1412,6 @@ static void cf_check complete_domain_destroy(struct rcu_head *head) >              continue; >          tasklet_kill(&v->continue_hypercall_tasklet); >          arch_vcpu_destroy(v); > -        sched_destroy_vcpu(v); > -        destroy_waitqueue_vcpu(v); >      } >   >      grant_table_destroy(d); > > OK >> @@ -448,13 +450,13 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) >> } >> >> if ( sched_init_vcpu(v) != 0 ) >> - goto fail_wq; >> + goto fail; >> >> if ( vmtrace_alloc_buffer(v) != 0 ) >> - goto fail_wq; >> + goto fail; >> >> if ( arch_vcpu_create(v) != 0 ) >> - goto fail_sched; >> + goto fail; >> >> d->vcpu[vcpu_id] = v; >> if ( vcpu_id != 0 ) >> @@ -472,11 +474,7 @@ struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id) >> >> return v; >> >> - fail_sched: >> - sched_destroy_vcpu(v); >> - fail_wq: >> - destroy_waitqueue_vcpu(v); >> - >> + fail: >> /* Must not hit a continuation in this context. */ >> if ( vcpu_teardown(v) ) >> ASSERT_UNREACHABLE(); >> diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c >> index 2ab4313517c3..fb7c99b05360 100644 >> --- a/xen/common/sched/core.c >> +++ b/xen/common/sched/core.c >> @@ -321,7 +321,7 @@ void vcpu_runstate_get(const struct vcpu *v, >> */ >> unit = is_idle_vcpu(v) ? get_sched_res(v->processor)->sched_unit_idle >> : v->sched_unit; >> - lock = likely(v == current) ? NULL : unit_schedule_lock_irq(unit); >> + lock = likely(v == current || !unit) ? NULL : unit_schedule_lock_irq(unit); > > This is obfuscation for obfuscations sake.  The normal way of writing it > would be: > >     if ( v != current && unit ) >         lock = unit_schedule_lock_irq(unit); > > and that is precisely what the compiler emits. > > Moreover it also matches the pattern for how the lock is released, later > in the function. OK, but I'd need to initialize lock to NULL (or add "else lock = NULL;") to avoid error: 'lock' may be used uninitialized in this function. Also, would we want the condition enclosed in unlikely(...) ? if ( unlikely(v != current && unit) ) lock = unit_schedule_lock_irq(unit); else lock = NULL; From xen-devel-bounces@lists.xenproject.org Tue Aug 05 00:25:01 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 00:25:01 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069881.1433566 (Exim 4.92) (envelope-from ) id 1uj5U1-0002io-7E; Tue, 05 Aug 2025 00:24:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069881.1433566; Tue, 05 Aug 2025 00:24:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj5U1-0002ih-4N; Tue, 05 Aug 2025 00:24:49 +0000 Received: by outflank-mailman (input) for mailman id 1069881; Tue, 05 Aug 2025 00:24:47 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj5Ty-0002iU-80 for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 00:24:47 +0000 Received: from mail-24416.protonmail.ch (mail-24416.protonmail.ch [109.224.244.16]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 9535d9a8-7192-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 02:24:43 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 9535d9a8-7192-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=protonmail; t=1754353482; x=1754612682; bh=jmSlZ+nH0HTo+SfNQ5zHTS2TQ6CtRkTRjHZXyfnPl1g=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Eyr1sesiqKxrBIG0RmqBFotQDjHzhHIhP7/gGixA5EfSvHeX+Y3cYnBdLr4/0aVdd BxLxf9pZQxWusjeG3K/4CkwYvEcFHXbOHwFT/wt7UNnVTP90M2dqISf2uMZfooTedY yd2QqaQW2tCU8PLGF74gh5tXm/C4payDCoOcnfAzaDTT7CKXbkLbNqwb7mLeugEAQm GFv1xf567xzDaQQ4OaJyfanU4ewTmzDp6S2juh1zBlOnSHkFZyZNr7r/AcVsyeTsbB Rrd0pmc8ciq9TKOqXOHK/IG9USOUNc2AJ1YFH+IMya4U34ibzbru6E33HpLfyDbL4f UUxrMEMgnt5xQ== Date: Tue, 05 Aug 2025 00:24:38 +0000 To: Jan Beulich From: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, oleksii.kurochko@gmail.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org Subject: Re: [PATCH v1 12/16] xen/domain: introduce domain-emu.h Message-ID: In-Reply-To: <61efc085-a787-4ca9-82e4-032408532ba6@suse.com> References: <20250624035443.344099-1-dmukhin@ford.com> <20250624035443.344099-13-dmukhin@ford.com> <33f98fe5-9b29-43e4-a87d-19eafb30f281@suse.com> <65e288b7-d8fe-409e-a287-69b4dc29f0c2@suse.com> <61efc085-a787-4ca9-82e4-032408532ba6@suse.com> Feedback-ID: 123220910:user:proton X-Pm-Message-ID: f08b396511e3536fd51ca897b7d45d1beacc3ab8 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Mon, Aug 04, 2025 at 09:13:07AM +0200, Jan Beulich wrote: > On 01.08.2025 21:30, dmkhn@proton.me wrote: > > On Fri, Aug 01, 2025 at 08:02:56AM +0200, Jan Beulich wrote: > >> On 31.07.2025 22:55, dmkhn@proton.me wrote: > >>> On Wed, Jul 09, 2025 at 04:57:44PM +0200, Jan Beulich wrote: > >>>> On 24.06.2025 05:56, dmkhn@proton.me wrote: > >>>>> @@ -458,16 +459,16 @@ struct arch_domain > >>>>> } __cacheline_aligned; > >>>>> > >>>>> #ifdef CONFIG_HVM > >>>>> -#define X86_EMU_LAPIC XEN_X86_EMU_LAPIC > >>>>> -#define X86_EMU_HPET XEN_X86_EMU_HPET > >>>>> -#define X86_EMU_PM XEN_X86_EMU_PM > >>>>> -#define X86_EMU_RTC XEN_X86_EMU_RTC > >>>>> -#define X86_EMU_IOAPIC XEN_X86_EMU_IOAPIC > >>>>> -#define X86_EMU_PIC XEN_X86_EMU_PIC > >>>>> -#define X86_EMU_VGA XEN_X86_EMU_VGA > >>>>> -#define X86_EMU_IOMMU XEN_X86_EMU_IOMMU > >>>>> -#define X86_EMU_USE_PIRQ XEN_X86_EMU_USE_PIRQ > >>>>> -#define X86_EMU_VPCI XEN_X86_EMU_VPCI > >>>> > >>>> The old code deliberately used values from the public interface. > >>> > >>> In next version I am building, I moved all of XEN_X86_EMU_XXX definit= ions as > >>> is to a new public header under include/public/xen-emu.h: > >>> > >>> https://gitlab.com/xen-project/people/dmukhin/xen/-/commit/9b0bc5ff= a5710114df8523ae2aa7680b7c6f0942 > >>> > >>> That looks less invasive. > >>> > >>> Will that work? > >>> > >>> There should be a common header with emulation flags somewhere, since > >>> there will be SBSA and hwdom vUART definitions there. > >> > >> Yet will there be a strict need for any constants to be identical (i.e= . > >> not only have the same name, but also the same value) across architect= ures? > > > > I don't think there's strict need for identical values across achitectu= res. >=20 > That's what I was expecting. >=20 > > But some of the constants _may_ be reused for non-x86 arches, like VPCI= bit > > and, perhaps, IOMMU, PIRQ and future NS16550 (after adding MMIO). >=20 > Right, but as you say - they want to use the same name, but they could ea= sily > have a different value there. I hope you understand that what I'm questio= ning > is the introduction of a single header covering all architectures. Yes, I understand your point wrt common header and identical values in emulation flags. I think I can add missing per-vUART fields to per-arch xen_arch_domainconfi= g, populate them by the toolstack and be done for now, i.e. I can drop that patch. -- Denis From xen-devel-bounces@lists.xenproject.org Tue Aug 05 00:54:56 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 00:54:56 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069894.1433577 (Exim 4.92) (envelope-from ) id 1uj5x3-0006ZM-Au; Tue, 05 Aug 2025 00:54:49 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069894.1433577; Tue, 05 Aug 2025 00:54:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj5x3-0006ZF-6h; Tue, 05 Aug 2025 00:54:49 +0000 Received: by outflank-mailman (input) for mailman id 1069894; Tue, 05 Aug 2025 00:54:48 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj5x1-0006Z2-FA for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 00:54:48 +0000 Received: from mail-10630.protonmail.ch (mail-10630.protonmail.ch [79.135.106.30]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id c38920fd-7196-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 02:54:39 +0200 (CEST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c38920fd-7196-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=proton.me; s=nlfzmj5cnbgtrfqinrkr57pfqy.protonmail; t=1754355277; x=1754614477; bh=Gf/gUMS/DL3VWa3qxDAViy/wKvJEWViUk/wKkn4k5IA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=K+BLDedy8E0FJazuT6YimuDDqtiFPQoXEmFF7Z1wAUhdKTYT0vvIRtLWNLZ9jRwKK L4hvxajIu/WDptnzN7eT4u/kOYySNl/4X7hRsyWBz3B/O4amx3Ut1//lgOhNCkL+e4 V4ivQ4FvriizDIFVwgJSSVRVOn1V8FoMXh39cTKbe89ffwNEQltfUyom3FzxQ9P/nh dqvM+xrjRROnK2r5I40dl2SvrjyNgoVqNTGKSnq7wd4fDdu505GAW6yLPmT+mjW36h b1YS21+2BQzu1k88S1GJSspaY2Lkuz8DThJig2fRmqp5DH3i0LY/5gDoS95OtiYLFP Ld3jKlHdAiA7g== Date: Tue, 05 Aug 2025 00:54:31 +0000 To: Jan Beulich From: dmkhn@proton.me Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, oleksii.kurochko@gmail.com, dmukhin@ford.com, xen-devel@lists.xenproject.org Subject: Re: [PATCH v4 1/8] xen/domain: introduce common emulation flags Message-ID: In-Reply-To: References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-2-dmukhin@ford.com> Feedback-ID: 123220910:user:proton X-Pm-Message-ID: 832fb489d638f87ab26acd733321aad8886c7034 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable + Cc: Oleskii On Mon, Aug 04, 2025 at 11:46:36AM +0200, Jan Beulich wrote: > On 31.07.2025 21:21, dmkhn@proton.me wrote: > > --- a/xen/include/xen/sched.h > > +++ b/xen/include/xen/sched.h > > @@ -652,6 +652,8 @@ struct domain > > unsigned int *llc_colors; > > #endif > > > > + uint32_t emulation_flags; >=20 > Just one further remark: The field probably never should have been of thi= s > type; unsigned int will do, and imo will want switching to while the fiel= d > is being moved. (Before giving an x86 ack, I want to convince myself thou= gh > that this is moving us in the right direction.) Hi Jan, I can definitely use different mechanism for virt ns16550: add a new field = in xen_arch_domainconfig. That will also simplify some of the emulation_flags checks on x86 and will be more flexible wrt emulator configuration (e.g. I = can allow passing I/O ports ranges). Hi Arm/RISC-V maintainers, Do you foresee any need in bubbling up emulation_flags to the common `struc= t domain`? -- Denis From xen-devel-bounces@lists.xenproject.org Tue Aug 05 03:39:07 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 03:39:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069914.1433586 (Exim 4.92) (envelope-from ) id 1uj8Vr-0007RL-MH; Tue, 05 Aug 2025 03:38:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069914.1433586; Tue, 05 Aug 2025 03:38:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj8Vr-0007RE-JX; Tue, 05 Aug 2025 03:38:55 +0000 Received: by outflank-mailman (input) for mailman id 1069914; Tue, 05 Aug 2025 03:38:54 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj8Vq-0007R8-AM for xen-devel@lists.xenproject.org; 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pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD Subject: [PATCH v10 0/4] Support hiding capability when its initialization fails Date: Tue, 5 Aug 2025 11:49:02 +0800 Message-ID: <20250805034906.1014212-1-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A346:EE_|IA1PR12MB6018:EE_ X-MS-Office365-Filtering-Correlation-Id: f920b90c-d8d0-4480-f61d-08ddd3d31059 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?Rk10ZUlTK1dUZUNVYkxDYlBrT0swaWN0WG5ydWd1eVBPSXhxN0JUd2Y3clFB?= =?utf-8?B?UDVIc2EyUTdyaERIN1ZlRGNFd09WVEtIRUw1WURBekpINHpmdnBUUXJHclF3?= =?utf-8?B?ZVY4WDkzcVMzS0YvM0psaVdOTWZJMHZCU2JKQW1PYm4waElvZmx1em1OOXNk?= =?utf-8?B?UnJqY2hVT3ZVMUd2VWtibUl3aG56OWowK0RiY0FlMjdQVU1mZ2QyaGZUV1Vz?= =?utf-8?B?a0ZBYjZJWmowM1NJVTkzME9ieFVQUnl0TmMrQWlqeEpTcUF1SGs2QVdzVjdp?= =?utf-8?B?RitXNzFQNUljM1VtWTRoOW5CSjNGMkhvMHVEZjhWTHBqZzMxWmJlODdwTjVm?= =?utf-8?B?QVZIZXl0ZWMxMGlBK2lja0RCNkhHNnFzaHk5R003VmdwZlV6bVVEOEpOamN2?= =?utf-8?B?U3RaSHRjb0R1N0hoQVVIS3AwZVBWV3Z6ajA1K1B6UHhCMXFoRmR4UGt3emJF?= =?utf-8?B?Q2k2U2FLTGJZK0c2eVljTHNTRzJiRzhsV3pjTFJMSkFEUXNvTEVEZWw2S0Nt?= =?utf-8?B?Z1RVenFBVE5RcllJMHlsU1IvSjV4ajdzbGpINHVlVHFSeDM1QXprcEdMT3lm?= =?utf-8?B?a2FEbnUrV3JRTnFnVENhN2FyR21uYWtrQ0diNllaOWdBdUNVRXlyU1pZd3Ba?= =?utf-8?B?SjRBdC9yOGpmcEVJRUUyU3U1U0xJd2w1TGpRa1NoVGVDZXdyb3Ewc0NoMHR2?= =?utf-8?B?WmVQV0hSdDAvb3p3UTdwNjRvSEIrdFJud2tUMURFVzBycnVlR2VkREx0VWs0?= =?utf-8?B?OFhCMjcvMFNwRUk4eHVpVXk2QVNWUVJhcHhGa2M0TTh5MWNMZ0Q3SHNVRUJ1?= =?utf-8?B?cEtCM1RXa2ZPT3JxVCtZYVVFQ252czZhcDNZak0wNFFSbDFjU0hRZzYxZWRN?= =?utf-8?B?MHRFL0Y2ZXpwNXJmenBBWG51bkhoVE9NTWlWVTlnS0o1cVh6My9DUnVmQlY1?= =?utf-8?B?TWplQnJ3ZTMvckFtVmtvZ251dmloZXByOG1LdnhKM0c1b3EyUFdUSzVIQ0FP?= =?utf-8?B?NzFiSngwMEpOSnRRQ0NUUmtEZW5NbnVLaEtqVWpoN0U0aGZUNEplTzBRNE9x?= =?utf-8?B?TVBrc1B0Z3IwL2QxdmtNY2krcGhZMGhVMGVNWnlCeXRkY1k1ZFhEMEVhSXFp?= =?utf-8?B?aHptKzdDeEhvSG5YbkZ1azdLeUNmUUoxc1JjVWU2NTNkYmVtN2hkb0hCaE9s?= =?utf-8?B?c0JYaTlPRHhiQktqRGFpS1U4MVJUVm1XSUF5c29yN1BHSUVVNmpWVzdYR3BO?= =?utf-8?B?SnpWOUNIVmZQOTRjYUxkbjFsK2xtdkRLQW11V2RMRTU1RkgzUEE0clBCVTVZ?= =?utf-8?B?T01vVVlVNkx6Zyt2a3JNRDZqZnF1d3NRQlpHemUzeW9kR2w5cWpTQk5ycjJ4?= =?utf-8?B?U1B5aExZQjZpT1FvVHZ3MFl6Sk1XVVltcHFpd29RNGFKNCtHdGRySEgrZjRU?= =?utf-8?B?YUJnc2FZR3JtZmR3Z2VPUEJjWmlMNkdSU1FaR3o1dE9RdlpnWmhSajVZVGxn?= =?utf-8?B?Z29VKzh4WVFLTjZBUjNGaDk2UXBuSDQwUWE4VEV0ZlhscjRKTnl0SnZjUG4z?= =?utf-8?B?TFF5WTVDUzhJMVc0bE9CTTk4clVRK0s2RmgwVmJtaVhiWFYwR3dRUlUrSkM2?= =?utf-8?B?bXZoZVliNjVRQnQ4Z0xUQkI5L3hsMGgveERuK1lLcmc3MFJVR254a0RmZjNU?= =?utf-8?B?cUtvR1h6QkpOR05QY29qdUkvZ0xxblVKZkJFK3VhL25lejBkSmY2VXhIalIv?= =?utf-8?B?YzAzTExCbmQ5WEUxQkRSR1dSSmtGVVU0a2szemxpL2pvUnUwaTVTYk92UU1L?= =?utf-8?B?bWxzaHdaYWhtUVIyV3NLdDdNZGgyVDMwQWkyRVNvZzhmVXN6aW1aNjYrV1Nw?= =?utf-8?B?SExoaTBHRks4YnlOY0g0RXpGV1FZa1RBaEszK2xWN1lUdUhDUFBkOTZGMUdw?= =?utf-8?B?TEMybzRxbHViRTNocTlDNFZtcFhYTUFxendQKzlHcWFoQUZEaTNsK3BKUUIz?= =?utf-8?B?MWRxbUdaMVErUHJPSDFvUmxqQnNTRngvWkVhejNvcEduUXAxZS9oMHlFUW5u?= =?utf-8?Q?BmnJsX?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 03:49:22.1825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f920b90c-d8d0-4480-f61d-08ddd3d31059 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A346.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6018 Hi, This series is to emulate extended capability list for dom0; hide legacy and extended capability when its initialization fails; above two parts had been merged. remove all related registers and other resources when initializing capability fails, including patch #1, #2, #3, #4. Best regards, Jiqian Chen. --- cc: "Roger Pau Monné" cc: Anthony PERARD --- Jiqian Chen (4): vpci: Refactor vpci_remove_register to remove matched registers vpci/rebar: Free Rebar resources when init_rebar() fails vpci/msi: Free MSI resources when init_msi() fails vpci/msix: Free MSIX resources when init_msix() fails tools/tests/vpci/main.c | 8 ++--- xen/drivers/vpci/msi.c | 46 ++++++++++++++++++++++++++- xen/drivers/vpci/msix.c | 44 +++++++++++++++++++++++++- xen/drivers/vpci/rebar.c | 41 +++++++++++++++++------- xen/drivers/vpci/vpci.c | 68 ++++++++++++++++++++++++---------------- xen/include/xen/vpci.h | 4 +-- 6 files changed, 165 insertions(+), 46 deletions(-) -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 03:49:34 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 03:49:34 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069924.1433606 (Exim 4.92) (envelope-from ) id 1uj8g6-0000vS-Q6; Tue, 05 Aug 2025 03:49:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069924.1433606; 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pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD Subject: [PATCH v10 1/4] vpci: Refactor vpci_remove_register to remove matched registers Date: Tue, 5 Aug 2025 11:49:03 +0800 Message-ID: <20250805034906.1014212-2-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250805034906.1014212-1-Jiqian.Chen@amd.com> References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A346:EE_|DM4PR12MB7648:EE_ X-MS-Office365-Filtering-Correlation-Id: 0368f18e-81ba-4a50-a6dd-08ddd3d31159 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 03:49:23.8583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0368f18e-81ba-4a50-a6dd-08ddd3d31159 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A346.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7648 vpci_remove_register() only supports removing a register in a time, but the follow-on changes need to remove all registers within a range. So, refactor it to support removing all registers in a given region. And it is no issue to remove a non exist register, so remove the __must_check prefix. Note: two test cases don't math the new logic of vpci_remove_registers(), then modify them. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monné" cc: Anthony PERARD --- v9->v10 changes: * Since logic change of vpci_remove_registers() affect the test cases of tools/tests/vpci/main.c, change them to match the new function logic. * Remove Roger's Reviewed-by since patch changed. v8->v9 changes: v7->v8 changes: v6->v7 changes: No. v5->v6 changes: * Modify commit message. * Add Roger's Reviewed-by. v4->v5 changes: No. v3->v4 changes: * Use list_for_each_entry_safe instead of list_for_each_entry. * Return ERANGE if overlap. v2->v3 changes: * Add new check to return error if registers overlap but not inside range. v1->v2 changes: new patch Best regards, Jiqian Chen. --- tools/tests/vpci/main.c | 8 ++++---- xen/drivers/vpci/vpci.c | 38 ++++++++++++++++++++------------------ xen/include/xen/vpci.h | 4 ++-- 3 files changed, 26 insertions(+), 24 deletions(-) diff --git a/tools/tests/vpci/main.c b/tools/tests/vpci/main.c index 33223db3eb77..2ef8d4e03f1d 100644 --- a/tools/tests/vpci/main.c +++ b/tools/tests/vpci/main.c @@ -132,10 +132,10 @@ static void vpci_write32_mask(const struct pci_dev *pdev, unsigned int reg, rsvdz_mask)) #define VPCI_REMOVE_REG(off, size) \ - assert(!vpci_remove_register(test_pdev.vpci, off, size)) + assert(!vpci_remove_registers(test_pdev.vpci, off, size)) #define VPCI_REMOVE_INVALID_REG(off, size) \ - assert(vpci_remove_register(test_pdev.vpci, off, size)) + assert(vpci_remove_registers(test_pdev.vpci, off, size)) /* Read a 32b register using all possible sizes. */ void multiread4_check(unsigned int reg, uint32_t val) @@ -402,10 +402,10 @@ main(int argc, char **argv) VPCI_REMOVE_REG(28, 1); VPCI_REMOVE_REG(24, 4); VPCI_REMOVE_REG(12, 2); + VPCI_REMOVE_REG(16, 2); + VPCI_REMOVE_REG(30, 2); VPCI_REMOVE_INVALID_REG(20, 1); - VPCI_REMOVE_INVALID_REG(16, 2); - VPCI_REMOVE_INVALID_REG(30, 2); return 0; } diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index fd02718b47ea..91d40be5bc4c 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -152,7 +152,7 @@ static int vpci_capability_hide(const struct pci_dev *pdev, unsigned int cap) prev_r->private = next_r->private; /* - * Not calling vpci_remove_register() here is to avoid redoing + * Not calling vpci_remove_registers() here is to avoid redoing * the register search. */ list_del(&next_r->node); @@ -160,7 +160,7 @@ static int vpci_capability_hide(const struct pci_dev *pdev, unsigned int cap) xfree(next_r); if ( !is_hardware_domain(pdev->domain) ) - return vpci_remove_register(vpci, offset + PCI_CAP_LIST_ID, 1); + return vpci_remove_registers(vpci, offset + PCI_CAP_LIST_ID, 1); return 0; } @@ -549,34 +549,36 @@ int vpci_add_register_mask(struct vpci *vpci, vpci_read_t *read_handler, return 0; } -int vpci_remove_register(struct vpci *vpci, unsigned int offset, - unsigned int size) +int vpci_remove_registers(struct vpci *vpci, unsigned int start, + unsigned int size) { - const struct vpci_register r = { .offset = offset, .size = size }; - struct vpci_register *rm; + struct vpci_register *rm, *tmp; + unsigned int end = start + size; spin_lock(&vpci->lock); - list_for_each_entry ( rm, &vpci->handlers, node ) + list_for_each_entry_safe ( rm, tmp, &vpci->handlers, node ) { - int cmp = vpci_register_cmp(&r, rm); - - /* - * NB: do not use a switch so that we can use break to - * get out of the list loop earlier if required. - */ - if ( !cmp && rm->offset == offset && rm->size == size ) + /* Remove rm if rm is inside the range. */ + if ( rm->offset >= start && rm->offset + rm->size <= end ) { list_del(&rm->node); - spin_unlock(&vpci->lock); xfree(rm); - return 0; + continue; } - if ( cmp <= 0 ) + + /* Return error if registers overlap but not inside. */ + if ( rm->offset + rm->size > start && rm->offset < end ) + { + spin_unlock(&vpci->lock); + return -ERANGE; + } + + if ( start < rm->offset ) break; } spin_unlock(&vpci->lock); - return -ENOENT; + return 0; } /* Wrappers for performing reads/writes to the underlying hardware. */ diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h index 17cfecb0aabf..514a0ce39133 100644 --- a/xen/include/xen/vpci.h +++ b/xen/include/xen/vpci.h @@ -70,8 +70,8 @@ static inline int __must_check vpci_add_register(struct vpci *vpci, size, data, 0, 0, 0, 0); } -int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offset, - unsigned int size); +int vpci_remove_registers(struct vpci *vpci, unsigned int start, + unsigned int size); /* Generic read/write handlers for the PCI config space. */ uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size); -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 03:49:38 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 03:49:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069925.1433616 (Exim 4.92) (envelope-from ) id 1uj8gE-0001Dt-5C; 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pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v10 2/4] vpci/rebar: Free Rebar resources when init_rebar() fails Date: Tue, 5 Aug 2025 11:49:04 +0800 Message-ID: <20250805034906.1014212-3-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250805034906.1014212-1-Jiqian.Chen@amd.com> References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34C:EE_|SJ2PR12MB9137:EE_ X-MS-Office365-Filtering-Correlation-Id: cf8f8bd5-ea21-46b8-729f-08ddd3d31249 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?eXU2aXlSQitCWDAwd08vL2dBZkFVTU1SdmFCYmYvajJKZkpSemkvSTBGL0JP?= =?utf-8?B?SXNMR1JhUUFqVm9wSEdoYlJKVG44Mm52WnBHd0RIQjcxWVFOMlNCNnNndWFS?= =?utf-8?B?U05pZVBaQzRRdEZhTllsR2luZEhVTTRqVDN3Ri9DMlZiVHFUL2NLYm5uOXhr?= =?utf-8?B?SDVvUTJBWUlSbDM1UUU3UTV1R2QvOC8vMHdaaG9PM0hmMkFxWnpia2VWWUxm?= =?utf-8?B?aldONFdBQmdSTFBFMVo0QTl6R014NFdpQ0pUQWpuNzRWb0dLR2JLa21VUzhj?= =?utf-8?B?T0Q0Wlo4ZWFUaEFucVJYc284OGhmMkkyaGdMQkpMaW1kZVpjcXY4aENYRTVP?= =?utf-8?B?bTRuanVhZ1ptaWY3OXpSRDZvTWh2WHV4UExZRS9GVmV0WTVCU2h3Y1lLYWZa?= =?utf-8?B?Y0lFL3lBS1dHazJ2MklNNm53MmsxSWM5RmJtVElZejZOYWFjNnZ4bGlGeVh2?= =?utf-8?B?VFRrRzhXMFovM1k4K3NEeCs1Q3VLa2ZuZnFVd0w4eEdCbnZUMW5KNWdTVk9l?= =?utf-8?B?YndsRjRxV0pnRWphMlo3ODQ1dTRnU0toR213WWNtbU5SVlBJQ3UzUDVqOW9m?= =?utf-8?B?UGN0eCs4ZDNRVFRiME9MVitFbkZsOE8ySUdxNnNudTdzQ3FPME5kUzZTbnJB?= =?utf-8?B?Um1TQytkMHVNK1k2SU1wQ1J4cDViTUJ0TkZkNlkrU0tJaGlmNUpLdlgvaTFJ?= =?utf-8?B?Y080MXg3K0Y3U3lrVnlyZVlqeis4YXZkT0E4S3p5aU5CRVBKdFY1Vmd6THBK?= =?utf-8?B?NU9XVnhvMHlUNHphQTIvM2hWWG4wZE5tV2poNUE1cE52MlJvN2Y0ZnBYcGE3?= =?utf-8?B?ajUvN0tYN1NFMGNGUDhMd3BIZVMwdXluUWZSWFFwRG5lR1lQemUwSUk2VlQv?= =?utf-8?B?VzdNK2JUYTFQbmppQlV1elN6TCtDSWRMbGhYR0JVdmt0U3RHTWFZVFhRYVBP?= =?utf-8?B?ejBFUXJGSzFyTk5YU0c2TjB2a3lFdkk3V1Vwc0lrOU9TZ3pRQzlCN2Q1QWNa?= =?utf-8?B?Mmc5MlB5MTRFZTZab3VpakIxVHdFVlhLcEVZNWUrYXp6dk40YVRZWXJ5VXlS?= =?utf-8?B?bHBMQi9ydHNJSjVXQjlLTXAyQ1pyZlU5Yi9mSDJtZlY3ME8yOGVkSENGcXo2?= =?utf-8?B?dENFbmRoZ2pKY0IrcnJYSnR5bTUvQitHNWpYbVNLUjVrUGk2SDdGOHdvS0da?= =?utf-8?B?T1FsNldENVRxblk4N2FXZWxjYjkzYUlUVU1EVDVmOU03T2w3cDFTaGJOMkE5?= =?utf-8?B?VUVkcDhFWFh1NDZiL0ZJWkZyVEg2TVF0TVBuTEFLWlJ4OGNmcThnaWF1ZjQx?= =?utf-8?B?djJGSFY3eFJIRUovNFdlMElRcGpTYW80MG5FaHYvQmY0YUhmTDQvNTAvMy9Y?= =?utf-8?B?MnlIczVNOG1TalVNSERseDRDcUlRbndNR3d6WlJyNnpTRHZQUTRyN3FubFh4?= =?utf-8?B?anlTOEllZ3dIblhmc01KSGxGNHpHTHYxWG5PMUI1dUVEOUNjeU8xcGY3WjND?= =?utf-8?B?VC9hQ3lXLy9RMTUwblk1ZElBTXAxN21LMnF0bGV3OTRlN3NNaDRxVzExbll1?= =?utf-8?B?N2FFYklmRGtCUVlhS09uMEdkTlhxME9VdUdlbnFaTWM2RCt1MW9vRC85MmdW?= =?utf-8?B?NFlnMVBLTGcxR2MzNHBWWDNwV3lJc29XWkZLNjdUWVkzT2crN0tIWVdWYXUy?= =?utf-8?B?cmE5RlM5bG1TL1ZFWXJwZVFQZ2FpTmpvZVhlT2pVSFVKbER0aXoyTW5CRG45?= =?utf-8?B?V2NYL0ZHYm1qQ2l4Vm1HaW12OEs1aHFzK0g3VXRNcTdweDRUNTVqdE9lbXkv?= =?utf-8?B?TmJYNi9RaHF4UDNFOXZNdGVXUGtkNk5UMG44UUVSeDZFYjlvUlpLbXY0enBl?= =?utf-8?B?WmxJeUtGTkJIVHFKU2pxWTVDM1JTa3BwWnlmRTAyQm4yNVc5NlFWTW5raWVq?= =?utf-8?B?RTlMTUJlNS9pWGM0UmRja2ZIbE1Sd0R1V2l1bmRZR3JqM3dPdG91VmFZWGxt?= =?utf-8?B?YThEN1RIN2I4a0xnYW5Yb1ZCS0t3MlBiRkNJaHpTSmxWUit1Y3h2VDh5Ty9F?= =?utf-8?Q?KOYLew?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 03:49:25.4279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf8f8bd5-ea21-46b8-729f-08ddd3d31249 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9137 When init_rebar() fails, current logic return fail and free Rebar-related resources in vpci_deassign_device(). But the previous new changes will hide Rebar capability and return success, it can't reach vpci_deassign_device() to remove resources if hiding success, so those resources must be removed in cleanup function of Rebar. To do that, implement cleanup function for Rebar. Signed-off-by: Jiqian Chen Reviewed-by: Roger Pau Monné --- cc: "Roger Pau Monné" --- v9->v10 changes: v8->v9 changes: No. v7->v8 changes: * Add Roger's Reviewed-by. v6->v7 changes: * Change the pointer parameter of cleanup_rebar() to be const. * Print error when vpci_remove_registers() fail in cleanup_rebar(). v5->v6 changes: No. v4->v5 changes: * Change definition "static void cleanup_rebar" to "static int cf_check cleanup_rebar" since cleanup hook is changed to be int. v3->v4 changes: * Change function name from fini_rebar() to cleanup_rebar(). * Change the error number to be E2BIG and ENXIO in init_rebar(). v2->v3 changes: * Use fini_rebar() to remove all register instead of in the failure path of init_rebar(); v1->v2 changes: * Called vpci_remove_registers() to remove all possible registered registers instead of using a array to record all registered register. Best regards, Jiqian Chen. --- xen/drivers/vpci/rebar.c | 41 +++++++++++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/xen/drivers/vpci/rebar.c b/xen/drivers/vpci/rebar.c index 3c18792d9bcd..39ab9c2eb7d9 100644 --- a/xen/drivers/vpci/rebar.c +++ b/xen/drivers/vpci/rebar.c @@ -49,6 +49,32 @@ static void cf_check rebar_ctrl_write(const struct pci_dev *pdev, bar->guest_addr = bar->addr; } +static int cf_check cleanup_rebar(const struct pci_dev *pdev) +{ + int rc; + uint32_t ctrl; + unsigned int nbars; + unsigned int rebar_offset = pci_find_ext_capability(pdev->sbdf, + PCI_EXT_CAP_ID_REBAR); + + if ( !rebar_offset || !is_hardware_domain(pdev->domain) ) + { + ASSERT_UNREACHABLE(); + return 0; + } + + ctrl = pci_conf_read32(pdev->sbdf, rebar_offset + PCI_REBAR_CTRL(0)); + nbars = MASK_EXTR(ctrl, PCI_REBAR_CTRL_NBAR_MASK); + + rc = vpci_remove_registers(pdev->vpci, rebar_offset + PCI_REBAR_CAP(0), + PCI_REBAR_CTRL(nbars - 1)); + if ( rc ) + printk(XENLOG_ERR "%pd %pp: fail to remove Rebar handlers rc=%d\n", + pdev->domain, &pdev->sbdf, rc); + + return rc; +} + static int cf_check init_rebar(struct pci_dev *pdev) { uint32_t ctrl; @@ -80,7 +106,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) { printk(XENLOG_ERR "%pd %pp: too big BAR number %u in REBAR_CTRL\n", pdev->domain, &pdev->sbdf, index); - continue; + return -E2BIG; } bar = &pdev->vpci->header.bars[index]; @@ -88,7 +114,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) { printk(XENLOG_ERR "%pd %pp: BAR%u is not in memory space\n", pdev->domain, &pdev->sbdf, index); - continue; + return -ENXIO; } rc = vpci_add_register(pdev->vpci, vpci_hw_read32, rebar_ctrl_write, @@ -97,14 +123,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) { printk(XENLOG_ERR "%pd %pp: BAR%u fail to add reg of REBAR_CTRL rc=%d\n", pdev->domain, &pdev->sbdf, index, rc); - /* - * Ideally we would hide the ReBar capability on error, but code - * for doing so still needs to be written. Use continue instead - * to keep any already setup register hooks, as returning an - * error will cause the hardware domain to get unmediated access - * to all device registers. - */ - continue; + return rc; } bar->resizable_sizes = @@ -118,7 +137,7 @@ static int cf_check init_rebar(struct pci_dev *pdev) return 0; } -REGISTER_VPCI_EXTCAP(REBAR, init_rebar, NULL); +REGISTER_VPCI_EXTCAP(REBAR, init_rebar, cleanup_rebar); /* * Local variables: -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 03:49:39 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 03:49:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069926.1433626 (Exim 4.92) (envelope-from ) id 1uj8gF-0001Sz-Dl; Tue, 05 Aug 2025 03:49:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069926.1433626; Tue, 05 Aug 2025 03:49:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1uj8gF-0001Sq-9I; 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h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OEirtSDxahjpcMVfzlTj78FWKW2/EKvB4YH6q/kyPkk=; b=mRitk0BEau4Qm8BE5ALP2o2vdOOI4zG8YfZi4iWp92Oyn0QpjDfXZe6NOQXbuQqyIfENyLYhUVNLh6q2iSkdNCOG647m7zuuhu7cTue0P/xNpH5h2YfrEO6zDSH901vB67j6e1m6DV0fk3io6NGrSAIA36qbzKRexB38yuzQ30U= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v10 3/4] vpci/msi: Free MSI resources when init_msi() fails Date: Tue, 5 Aug 2025 11:49:05 +0800 Message-ID: <20250805034906.1014212-4-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250805034906.1014212-1-Jiqian.Chen@amd.com> References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 03:49:27.5447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa4f2d3b-4709-4791-56f5-08ddd3d3138c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8344 When init_msi() fails, current logic return fail and free MSI-related resources in vpci_deassign_device(). But the previous new changes will hide MSI capability and return success, it can't reach vpci_deassign_device() to remove resources if hiding success, so those resources must be removed in cleanup function of MSI. To do that, implement cleanup function for MSI. Signed-off-by: Jiqian Chen Reviewed-by: Roger Pau Monné --- cc: "Roger Pau Monné" --- v9->v10 changes: No. v8->v9 changes: * Add Roger's Reviewed-by. v7->v8 changes: * Add a comment to describe why "-2" in cleanup_msi(). * Given the code in vpci_remove_registers() an error in the removal of registers would likely imply memory corruption, at which point it's best to fully disable the device. So, Rollback the last two modifications of v7. v6->v7 changes: * Change the pointer parameter of cleanup_msi() to be const. * When vpci_remove_registers() in cleanup_msi() fails, not to return directly, instead try to free msi and re-add ctrl handler. * Pass pdev->vpci into vpci_add_register() instead of pdev->vpci->msi in init_msi() since we need that every handler realize that msi is NULL when msi is free but handlers are still in there. v5->v6 changes: No. v4->v5 changes: * Change definition "static void cleanup_msi" to "static int cf_check cleanup_msi" since cleanup hook is changed to be int. * Add a read-only register for MSI Control Register in the end of cleanup_msi. v3->v4 changes: * Change function name from fini_msi() to cleanup_msi(). * Remove unnecessary comment. * Change to use XFREE to free vpci->msi. v2->v3 changes: * Remove all fail path, and use fini_msi() hook instead. * Change the method to calculating the size of msi registers. v1->v2 changes: * Added a new function fini_msi to free all MSI resources instead of using an array to record registered registers. Best regards, Jiqian Chen. --- xen/drivers/vpci/msi.c | 46 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c index c3eba4e14870..ad5138c4cb5e 100644 --- a/xen/drivers/vpci/msi.c +++ b/xen/drivers/vpci/msi.c @@ -193,6 +193,50 @@ static void cf_check mask_write( msi->mask = val; } +static int cf_check cleanup_msi(const struct pci_dev *pdev) +{ + int rc; + unsigned int end; + struct vpci *vpci = pdev->vpci; + const unsigned int msi_pos = pdev->msi_pos; + const unsigned int ctrl = msi_control_reg(msi_pos); + + if ( !msi_pos || !vpci->msi ) + return 0; + + if ( vpci->msi->masking ) + end = msi_pending_bits_reg(msi_pos, vpci->msi->address64); + else + /* + * "-2" here is to cut the reserved 2 bytes of Message Data when + * there is no masking support. + */ + end = msi_mask_bits_reg(msi_pos, vpci->msi->address64) - 2; + + rc = vpci_remove_registers(vpci, ctrl, end - ctrl); + if ( rc ) + { + printk(XENLOG_ERR "%pd %pp: fail to remove MSI handlers rc=%d\n", + pdev->domain, &pdev->sbdf, rc); + ASSERT_UNREACHABLE(); + return rc; + } + + XFREE(vpci->msi); + + /* + * The driver may not traverse the capability list and think device + * supports MSI by default. So here let the control register of MSI + * be Read-Only is to ensure MSI disabled. + */ + rc = vpci_add_register(vpci, vpci_hw_read16, NULL, ctrl, 2, NULL); + if ( rc ) + printk(XENLOG_ERR "%pd %pp: fail to add MSI ctrl handler rc=%d\n", + pdev->domain, &pdev->sbdf, rc); + + return rc; +} + static int cf_check init_msi(struct pci_dev *pdev) { unsigned int pos = pdev->msi_pos; @@ -270,7 +314,7 @@ static int cf_check init_msi(struct pci_dev *pdev) return 0; } -REGISTER_VPCI_CAP(MSI, init_msi, NULL); +REGISTER_VPCI_CAP(MSI, init_msi, cleanup_msi); void vpci_dump_msi(void) { -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 03:49:40 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 03:49:40 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069927.1433636 (Exim 4.92) (envelope-from ) id 1uj8gG-0001iZ-LQ; Tue, 05 Aug 2025 03:49:40 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069927.1433636; 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pr=C From: Jiqian Chen To: CC: Huang Rui , Jiqian Chen , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v10 4/4] vpci/msix: Free MSIX resources when init_msix() fails Date: Tue, 5 Aug 2025 11:49:06 +0800 Message-ID: <20250805034906.1014212-5-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250805034906.1014212-1-Jiqian.Chen@amd.com> References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|IA1PR12MB6652:EE_ X-MS-Office365-Filtering-Correlation-Id: ddcd4363-4ae3-4df1-a19c-08ddd3d314e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?MDJtdm5ETDk1NHNnK25XdkVHZmx2cmdIeUNDamxoNmVhMU1xdHR2VHdQQThJ?= =?utf-8?B?TmZXam85RU90ZmlKTWh5Q2p1dEhpU1BqKzdicXBlTzd0Rm5nYkxVYXlFU3Rh?= =?utf-8?B?R1ZXQ2FVVVRlY2d2UkxGaU9PK1RrNVlXdWFpcmdweWtmaTZac05YWFNJMVFY?= =?utf-8?B?OGFtTFhXUFFGM051VG1zVUVBNmo1ZnJWd0ZVYVFNajdIN3FDb3M1ZWR6NEpS?= =?utf-8?B?aExqa1pTalltVDI2NEJuaE1xVTN5c1BFNGFhblVVWHpZUDl6NnpsN3hjWllI?= =?utf-8?B?ekdDRFIxM1dnbVJTaVlVbXluajVCZ2Vmc1ZIWTQ4SGtTVjVSSlZqOW9vdDlY?= =?utf-8?B?MlJFZUFWZHN1NndRbTVKV2NaVFdtaDhtVXlHZWMyY0htQ212VmdMWko4Nmc4?= =?utf-8?B?REFCRjBhTHZ5dkhrMHlYd3VPcXVkYzNic05SVUN1MzFwSkpOVE5nZDRQeWQ4?= =?utf-8?B?c3VVNGtGdEhUNm56emRxMW0vNFpRalE5T1JaemRWenV2RDBpTXJlR2lhdXRm?= =?utf-8?B?WHMrY0JkRmx5NiszQktGSlpUc0E5QW5IN0s5eXk0cERMclVNbC9xaHJsclZn?= =?utf-8?B?U1BPNExXdXVkSjNWZ3VjeTZVb09pVGFwTmFud0g1OWpXSHd3bFJ2bXJpZlVZ?= =?utf-8?B?YlNRSEpBR2N5ZU5HcGtrUitzaUUxeGdZcnlnRFVFczNFNjdiRUY1MC9Kd0Yx?= =?utf-8?B?UHNqVS9Oc0pBRkFDelNGNVF0SkduSWpVc1cyNDR0Ni8rdXkyUlVkdHRuVEho?= =?utf-8?B?RWpOaHJEOWxpYWZCNnpFdnk4OG14bFBtSkpuMFE2TzZDbGlCY2d6dmc2anlQ?= =?utf-8?B?NTNEeXF0K1dlSVRiYUQxa1FNVTc5SnJSWE5oTnBEZU5ZbGJSZ1VBV0I0Mmd0?= =?utf-8?B?ZTB4cW1UR1orTE5RTFFVVGpHd1NJWWZNdTJFOGk2S1ZNaXhEemE2eWl2c2lM?= =?utf-8?B?dm1nNm1tSWtGM3FtOHp6TjJGZC9IRTlHdnpneStWWkhSTVZsK1NsSFZhNlI0?= =?utf-8?B?MWdTZkp3UHErT0FzOWpwcHhjWjZ3ZmV6VWNTaEZkVXlhOWpkaGhYeEh6eWVP?= =?utf-8?B?ODlWczd0aTRqbXRQZEFOMDlOVlkwNFlUbFhpNDdQUllpeUUyUVh3Z29QOVNm?= =?utf-8?B?bVM0R3ZoTzdFUSt4WHRvSmo4Q0Z0a1VsS0w5eG4zYUF3OGhwTFUwVmk5OVRJ?= =?utf-8?B?WXo1b2lzQ0Nmd0p0bHBkU1g2ajJocjVJUFdkcC8yd1lMOVZaL3MvNkhZUC9z?= =?utf-8?B?SW1vQ25qQk51eXJzUjg3dk1NN216WjMyUGhoc254SGlUUEszNU1CQ0xva1lW?= =?utf-8?B?eWU2UHpIaVhZWStBV29JbHI5MVo5YkpOeDRnNi8xTlZzOHFqRFhoU09hRmNp?= =?utf-8?B?ZW94VktadSswbHdqUW9yRFV0RkVtYlR1eTBEOVpnMGRDNTQ5ZU0xU2VPOHpC?= =?utf-8?B?Njh0UG9mTVl0eWYyUUk5cXdOZlF6RUZmOTlFZFlOa2ZXRXVQaENya1owQXhU?= =?utf-8?B?ZlQ4MVU5MTA2dmJYNGtWSGY4RE4zS0NEQlRIYzBDMXJtamJ4aTgrdlNRTVoz?= =?utf-8?B?L21jM2tNQU5RN1ZEZlpXdTdkWG5xS0szZ2Q1SWtROHpRZnlNLzc2dlBwdVVG?= =?utf-8?B?RU5TMVFRdXUzRmN5YzBuY0ZQZjlqT2RYMEpxTGFnSTJNUTRiRnBLOTJzazA0?= =?utf-8?B?RkRQVm5BRVdPL0pxWFA1dkxvMUsyMHowZmJIUnI2MlZEMUI2SUIrNm9IcS92?= =?utf-8?B?ckRtVjlFYXRyWEdEaHlDa2lQTFB4Z29HT2FkS1BSZld0VjNIY0hWWjk2K2R1?= =?utf-8?B?SU9UL2dhc0JJeHVjcnZWd2ZzRVJFRXF3ZmVwbExBT1VjZjBTQzRJdHUxNlpZ?= =?utf-8?B?eGdITWtoaDVwWHBLNWZ1TnYzNWFOVlhQazc1bW8zMUp5cDJzZVJUVDA4WmZq?= =?utf-8?B?MGsrcU9YZWFHVnVaT3pIRjhibEdicGpxTENVcWNjRDNoOUdRRURYOTNhN3dK?= =?utf-8?B?YnZSd2I0N0h2MW1lTjJxMzEzeW10N3pvaWpXajdXL200ZUNTWjEwdG5MZDdv?= =?utf-8?Q?nV6dyS?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 03:49:29.8274 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ddcd4363-4ae3-4df1-a19c-08ddd3d314e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6652 When MSI-X initialization fails vPCI will hide the capability, but remove of handlers and data won't be performed until the device is deassigned. Introduce a MSI-X cleanup hook that will be called when initialization fails to cleanup MSI-X related hooks and free it's associated data. As all supported capabilities have been switched to use the cleanup hooks call those from vpci_deassign_device() instead of open-code the capability specific cleanup in there. Signed-off-by: Jiqian Chen --- cc: "Roger Pau Monné" --- v9->v10 changes: * Call all cleanup hook in vpci_deassign_device() instead of cleanup_msix(). v8->v9 changes: * Modify commit message. * Call cleanup_msix() in vpci_deassign_device() to remove the open-code to cleanup msix datas. * In cleanup_msix(), move "list_del(&vpci->msix->next);" above for loop of iounmap msix tables. v7->v8 changes: * Given the code in vpci_remove_registers() an error in the removal of registers would likely imply memory corruption, at which point it's best to fully disable the device. So, Rollback the last two modifications of v7. v6->v7 changes: * Change the pointer parameter of cleanup_msix() to be const. * When vpci_remove_registers() in cleanup_msix() fails, not to return directly, instead try to free msix and re-add ctrl handler. * Pass pdev->vpci into vpci_add_register() instead of pdev->vpci->msix in init_msix() since we need that every handler realize that msix is NULL when msix is freed but handlers are still in there. v5->v6 changes: * Change the logic to add dummy handler when !vpci->msix in cleanup_msix(). v4->v5 changes: * Change definition "static void cleanup_msix" to "static int cf_check cleanup_msix" since cleanup hook is changed to be int. * Add a read-only register for MSIX Control Register in the end of cleanup_msix(). v3->v4 changes: * Change function name from fini_msix() to cleanup_msix(). * Change to use XFREE to free vpci->msix. * In cleanup function, change the sequence of check and remove action according to init_msix(). v2->v3 changes: * Remove unnecessary clean operations in fini_msix(). v1->v2 changes: new patch. Best regards, Jiqian Chen. --- xen/drivers/vpci/msix.c | 44 ++++++++++++++++++++++++++++++++++++++++- xen/drivers/vpci/vpci.c | 30 +++++++++++++++++++--------- 2 files changed, 64 insertions(+), 10 deletions(-) diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c index 54a5070733aa..3aa271445d12 100644 --- a/xen/drivers/vpci/msix.c +++ b/xen/drivers/vpci/msix.c @@ -655,6 +655,48 @@ int vpci_make_msix_hole(const struct pci_dev *pdev) return 0; } +static int cf_check cleanup_msix(const struct pci_dev *pdev) +{ + int rc; + struct vpci *vpci = pdev->vpci; + const unsigned int msix_pos = pdev->msix_pos; + + if ( !msix_pos ) + return 0; + + rc = vpci_remove_registers(vpci, msix_control_reg(msix_pos), 2); + if ( rc ) + { + printk(XENLOG_ERR "%pd %pp: fail to remove MSIX handlers rc=%d\n", + pdev->domain, &pdev->sbdf, rc); + ASSERT_UNREACHABLE(); + return rc; + } + + if ( vpci->msix ) + { + list_del(&vpci->msix->next); + for ( unsigned int i = 0; i < ARRAY_SIZE(vpci->msix->table); i++ ) + if ( vpci->msix->table[i] ) + iounmap(vpci->msix->table[i]); + + XFREE(vpci->msix); + } + + /* + * The driver may not traverse the capability list and think device + * supports MSIX by default. So here let the control register of MSIX + * be Read-Only is to ensure MSIX disabled. + */ + rc = vpci_add_register(vpci, vpci_hw_read16, NULL, + msix_control_reg(msix_pos), 2, NULL); + if ( rc ) + printk(XENLOG_ERR "%pd %pp: fail to add MSIX ctrl handler rc=%d\n", + pdev->domain, &pdev->sbdf, rc); + + return rc; +} + static int cf_check init_msix(struct pci_dev *pdev) { struct domain *d = pdev->domain; @@ -710,7 +752,7 @@ static int cf_check init_msix(struct pci_dev *pdev) */ return vpci_make_msix_hole(pdev); } -REGISTER_VPCI_CAP(MSIX, init_msix, NULL); +REGISTER_VPCI_CAP(MSIX, init_msix, cleanup_msix); /* * Local variables: diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c index 91d40be5bc4c..ebc4fdcd2600 100644 --- a/xen/drivers/vpci/vpci.c +++ b/xen/drivers/vpci/vpci.c @@ -321,6 +321,27 @@ void vpci_deassign_device(struct pci_dev *pdev) &pdev->domain->vpci_dev_assigned_map); #endif + for ( i = 0; i < NUM_VPCI_INIT; i++ ) + { + const vpci_capability_t *capability = &__start_vpci_array[i]; + const unsigned int cap = capability->id; + unsigned int pos = 0; + + if ( !capability->is_ext ) + pos = pci_find_cap_offset(pdev->sbdf, cap); + else if ( is_hardware_domain(pdev->domain) ) + pos = pci_find_ext_capability(pdev->sbdf, cap); + + if ( pos && capability->cleanup ) + { + int rc = capability->cleanup(pdev); + if ( rc ) + printk(XENLOG_ERR "%pd %pp: clean %s cap %u fail rc=%d\n", + pdev->domain, &pdev->sbdf, + capability->is_ext ? "extended" : "legacy", cap, rc); + } + } + spin_lock(&pdev->vpci->lock); while ( !list_empty(&pdev->vpci->handlers) ) { @@ -332,19 +353,10 @@ void vpci_deassign_device(struct pci_dev *pdev) xfree(r); } spin_unlock(&pdev->vpci->lock); - if ( pdev->vpci->msix ) - { - list_del(&pdev->vpci->msix->next); - for ( i = 0; i < ARRAY_SIZE(pdev->vpci->msix->table); i++ ) - if ( pdev->vpci->msix->table[i] ) - iounmap(pdev->vpci->msix->table[i]); - } for ( i = 0; i < ARRAY_SIZE(pdev->vpci->header.bars); i++ ) rangeset_destroy(pdev->vpci->header.bars[i].mem); - xfree(pdev->vpci->msix); - xfree(pdev->vpci->msi); xfree(pdev->vpci); pdev->vpci = NULL; } -- 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 04:48:43 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 04:48:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069979.1433645 (Exim 4.92) (envelope-from ) id 1uj9bE-0002DD-0T; Tue, 05 Aug 2025 04:48:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1069979.1433645; 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Mon, 04 Aug 2025 21:48:28 -0700 (PDT) Date: Mon, 4 Aug 2025 23:48:16 -0500 From: Aaron Rainbolt To: grub-devel@gnu.org, xen-devel@lists.xenproject.org Subject: [PATCH v4 0/2] kern/xen: Add Xen command line parsing Message-ID: <20250804234816.3d14f53f@kf-m2g5> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.41; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; boundary="Sig_/xScQGjvbhehxfi4Rs=kQNRS"; protocol="application/pgp-signature"; micalg=pgp-sha512 --Sig_/xScQGjvbhehxfi4Rs=kQNRS Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable The purpose of this patch is to allow the Xen hypervisor to pass extra data to GRUB in the form of a kernel command line, allowing the host to customize the boot process of the guest. The command line from Xen is parsed, and any variables within that start with the string `xen_grub_env_` are exposed as environment variables. The grub.cfg script can then use those environment variables as it sees fit. The main reason for doing this is to allow implementing boot modes in Qubes OS while also using in-VM kernels. For more context on Qubes boot modes, see [1]. In order for this to work with in-VM kernels, it is necessary for dom0 to pass kernel parameters to the guest without modifying the guest's grub.cfg manually. This patch allows this to be done, by allowing dom0 to pass kernel parameters to GRUB, which then provides them to grub.cfg as an environment variable. The grub.cfg script within the VM can then append those variables to the kernel command line. All of the changes from version 3 of the patch are simply refinements after a review from Daniel Kiper (coding style cleanups, avoiding global variables, double-checking NUL-termination after using grub_strncpy, etc.). The patch's functionality is unchanged. Since there are substantial changes since version 3, I've re-run the entire battery of tests that were used against the v3 patch, plus an extra test to ensure an escaped control character won't be accepted in variable values. The test results can be seen at [2]. As previously, the tests were done by booting a patched GRUB in Xen with various different parameters passed to it via the Xen-provided kernel command line. The effects of these parameters on the bootloader's environment were then tested, and then an Arch Linux image was booted to ensure that boot still worked. [1] https://github.com/QubesOS/qubes-linux-pvgrub2/pull/16 [2] https://bpa.st/3SBQ Aaron Rainbolt (2): include/xen: Rename MAX_GUEST_CMDLINE to GRUB_XEN_MAX_GUEST_CMDLINE kern/xen: Add Xen command line parsing docs/grub.texi | 51 +++++ grub-core/Makefile.core.def | 2 + grub-core/kern/i386/xen/pvh.c | 23 +++ grub-core/kern/xen/cmdline.c | 376 ++++++++++++++++++++++++++++++++++ grub-core/kern/xen/init.c | 2 + include/grub/xen.h | 2 + include/xen/xen.h | 4 +- 7 files changed, 458 insertions(+), 2 deletions(-) create mode 100644 grub-core/kern/xen/cmdline.c --=20 2.50.1 --Sig_/xScQGjvbhehxfi4Rs=kQNRS Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEEudh48PFXwyPDa0wGpwkWDXPHkQkFAmiRjRAACgkQpwkWDXPH kQmUcQ/+IK73jDnnYdHxMHW5n0qqZPpSkOK1mYaH7o9lzLGngg9ias2SqAML8aw+ Fyi+QQhVd7XRmPjZHe85yyVgEY3NM4WK7+T2PY4LfSAWq5xRKHVtm4mnhSMmXp95 /DPqL4k8Dyj8oVuu861gdSxGk3L8Bq8bW1ttMIxTn9j1A3lKZ7h3//z6aXu+fTgQ MJuACkFJRGVjMnRXT40AKlRCM36KFktCC+C1r+a8Lh7rHhSzLWf6TbF+0A9Nt8vZ foLAvqAGlYfLtyi5nCMPdC88VeOcVc2PjymhzCd2MdTc7Wumxhw/xUFsJcoggaZK Al//2ekOjTjRP/Cirx6KBCe6eId3vk6YOC5HWKrHcFyCdYG3D+4MGXFPL9wQMEyN c1QLWdIPtBtFXXHLjppX1gsd0Wi9Jt47K1Xr1glzLHs7b++Zhlz+/qtoguPHU74i ilvAe8E4XRaCDZyFlxQofrfUVpa2OJOLHsoubS35X7DFpcNc+nHMYesDw4L6Bk0P McjaJ1CAbsxfELJ82ReQajhjTLB10C26EUd+JolR3g6+6fU2L4Aiy+IwQw348Rmc KKV429earA8F8Pu6UkgKEG8JQJlkbTts0wMs94+5pOslM5rqFqrbi/IDNJXV9e/2 fsU01RHTu4HKB6j8ryDi0Mgo5sPqfkJJJplfxQeaiRpeeo7Txj8= =k+GH -----END PGP SIGNATURE----- --Sig_/xScQGjvbhehxfi4Rs=kQNRS-- From xen-devel-bounces@lists.xenproject.org Tue Aug 05 04:49:18 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 04:49:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069988.1433656 (Exim 4.92) (envelope-from ) id 1uj9by-0002g6-9N; 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Mon, 04 Aug 2025 21:49:14 -0700 (PDT) Date: Mon, 4 Aug 2025 23:49:11 -0500 From: Aaron Rainbolt To: grub-devel@gnu.org, xen-devel@lists.xenproject.org Subject: [PATCH v4 1/2] include/xen: Rename MAX_GUEST_CMDLINE to GRUB_XEN_MAX_GUEST_CMDLINE Message-ID: <20250804234911.3cc3997c@kf-m2g5> In-Reply-To: <20250804234816.3d14f53f@kf-m2g5> References: <20250804234816.3d14f53f@kf-m2g5> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.41; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; boundary="Sig_/cayLqM02C/AJXMYF4q/w2jR"; protocol="application/pgp-signature"; micalg=pgp-sha512 --Sig_/cayLqM02C/AJXMYF4q/w2jR Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable The xen.h header was using an overly generic name to refer to the maximum length of the command line passed from Xen to a guest. Rename it to avoid confusion or conflicts in the future. Signed-off-by: Aaron Rainbolt --- include/xen/xen.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/xen/xen.h b/include/xen/xen.h index 692f97a..fdf0fc4 100644 --- a/include/xen/xen.h +++ b/include/xen/xen.h @@ -823,8 +823,8 @@ struct start_info { /* (PFN of pre-loaded module if = */ /* SIF_MOD_START_PFN set in flags). = */ unsigned long mod_len; /* Size (bytes) of pre-loaded module. = */ -#define MAX_GUEST_CMDLINE 1024 - int8_t cmd_line[MAX_GUEST_CMDLINE]; +#define GRUB_XEN_MAX_GUEST_CMDLINE 1024 + int8_t cmd_line[GRUB_XEN_MAX_GUEST_CMDLINE]; /* The pfn range here covers both page table and p->m table frames. = */ unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. = */ unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. = */ --=20 2.50.1 --Sig_/cayLqM02C/AJXMYF4q/w2jR Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEEudh48PFXwyPDa0wGpwkWDXPHkQkFAmiRjUcACgkQpwkWDXPH kQnPRhAAwD0BnZnH/WypxaZfvHSRWFj2A1vN+TZL4GAj8foEiE9r6ia/uPRVDR60 uayYCi0NQ35VfGYYA8Ok/ses+8kpCtFcNQaGOwu8DwzQu2+4gaTp5EKAz4cl189e JsRds5jE8nLReqFxKhNbVMTMMlz91THrPM9vMlt3SJLnDveNhZgTCZl+JqQPV0wZ FxBxb08f8fcA3k6MPZfZkY1su2ncLszFJUidDSjyA+8PHzxiT2n8PNCUJX06a60O xPNnr9bfb9P13H4hk57gSazsc03iVnbw14njhssBYr2Aw/1J+gGWWRBXTyqFBFiu JLsZPdFkEKo0CAsuNNW4teNXurCjLMjad/mVvfOUOw65NQUM9bpPAcm+SdgviVG/ Xj1m/fIKVRBoPwfDHXgcDVPIE8YtcP6kN3+YKeJrmHdT7sUPv9Rcbp+jNeRa6BC+ rzIVnkIPXYP95dV0Ycou0lYTBuFSTYAS7wPOotV/HxPp/Z1trRnYXmeWJieF6Iis z6Ih4dywciqSfy5Q+xanxKC8vq17KZW49QQc/aWC9hJt45KnkcAFJeUFEbZfBWXV FW/e59JWreNSNQ7IZ87j7Wk8zbBXShNAJ7uONiox00W3cJrglSBbOkI4DZ1zMt/Q mI0uzhOJ4uAOrRZ3qFS+oei+C8jaz69jgG9PjtJ+HV/hxlzmBpQ= =xDlH -----END PGP SIGNATURE----- --Sig_/cayLqM02C/AJXMYF4q/w2jR-- From xen-devel-bounces@lists.xenproject.org Tue Aug 05 04:50:22 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 04:50:22 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1069995.1433666 (Exim 4.92) (envelope-from ) id 1uj9cz-0004AM-J6; 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Mon, 04 Aug 2025 21:50:12 -0700 (PDT) Date: Mon, 4 Aug 2025 23:50:09 -0500 From: Aaron Rainbolt To: grub-devel@gnu.org, xen-devel@lists.xenproject.org Subject: [PATCH v4 2/2] kern/xen: Add Xen command line parsing Message-ID: <20250804235009.30e39bd9@kf-m2g5> In-Reply-To: <20250804234911.3cc3997c@kf-m2g5> References: <20250804234816.3d14f53f@kf-m2g5> <20250804234911.3cc3997c@kf-m2g5> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.41; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; boundary="Sig_/ZnIhcNgyGpUwofXD.=Muf+N"; protocol="application/pgp-signature"; micalg=pgp-sha512 --Sig_/ZnIhcNgyGpUwofXD.=Muf+N Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Xen traditionally allows customizing guest behavior by passing arguments to the VM kernel via the kernel command line. This is no longer possible when using GRUB with Xen, as the kernel command line is decided by the GRUB configuration file within the guest, not data passed to the guest by Xen. To work around this limitation, enable GRUB to parse a command line passed to it by Xen, and expose data from the command line to the GRUB configuration as environment variables. These variables can be used in the GRUB configuration for any desired purpose, such as extending the kernel command line passed to the guest. The command line format is inspired by the Linux kernel's command line format. To reduce the risk of misuse, abuse, or accidents in production, the command line will only be parsed if it consists entirely of 7-bit ASCII characters, only alphabetical characters and underscores are permitted in variable names, and all variable names must start with the string "xen_grub_env_". This also allows room for expanding the command line arguments accepted by GRUB in the future, should other arguments end up becoming desirable in the future. Signed-off-by: Aaron Rainbolt --- docs/grub.texi | 51 +++++ grub-core/Makefile.core.def | 2 + grub-core/kern/i386/xen/pvh.c | 23 +++ grub-core/kern/xen/cmdline.c | 376 ++++++++++++++++++++++++++++++++++ grub-core/kern/xen/init.c | 2 + include/grub/xen.h | 2 + 6 files changed, 456 insertions(+) create mode 100644 grub-core/kern/xen/cmdline.c diff --git a/docs/grub.texi b/docs/grub.texi index 34b3484..b58cf98 100644 --- a/docs/grub.texi +++ b/docs/grub.texi @@ -3271,6 +3271,7 @@ GRUB. Others may be used freely in GRUB configuratio= n files. @menu * Special environment variables:: * Environment block:: +* Passing environment variables through Xen:: @end menu =20 =20 @@ -3871,6 +3872,56 @@ using BIOS or EFI functions (no ATA, USB or IEEE1275= ). @command{grub-mkconfig} uses this facility to implement @samp{GRUB_SAVEDEFAULT} (@pxref{Simple configuration}). =20 +@node Passing environment variables through Xen +@section Passing environment variables through Xen + +If you are using a GRUB image as the kernel for a PV or PVH Xen virtual +machine, you can pass environment variables from Xen's dom0 to the VM thro= ugh +the Xen-provided kernel command line. When combined with a properly config= ured +guest, this can be used to customize the guest's behavior on bootup via the +VM's Xen configuration file. + +GRUB will parse the kernel command line passed to it by Xen during bootup. +The command line will be split into space-delimited words. Single and +double quotes may be used to quote words or portions of words that contain +spaces. Single quotes will be considered part of a word if inside double +quotes, and vice versa. Arbitrary characters may be backslash-escaped to m= ake +them a literal component of a word rather than being parsed as quotes or w= ord +separators. The command line must consist entirely of printable 7-bit ASCII +characters and spaces. If a non-printing ASCII character is found anywhere= in +the command line, the entire command line will be ignored by GRUB. + +Each word should be a variable assignment in the format ``variable'' or +``variable=3Dvalue''. Variable names must contain only the characters A-Z,= a-z, +and underscore (``_''). Variable names must begin with the string +``xen_grub_env_''. Variable values can contain arbitrary printable 7-bit +ASCII characters and space. If any variable contains an illegal name, that +variable will be ignored. + +If a variable name and value are both specified, the variable will be set = to +the specified value. If only a variable name is specified, the variable's +value will be set to ``1''. + +The following is a simple example of how to use this functionality to appe= nd +arbitrary variables to a guest's kernel command line: + +@example +# In the Xen configuration file for the guest +name =3D "linux_vm" +type =3D "pvh" +kernel =3D "/path/to/grub-i386-xen_pvh.bin" +extra =3D "xen_grub_env_linux_append=3D'loglevel=3D3'" +memory =3D 1024 +disk =3D [ "file:/srv/vms/linux_vm.img,sda,w" ] + +# In the guest's GRUB configuration file +menuentry "Linux VM with dom0-specified kernel parameters" @{ + search --set=3Droot --label linux_vm --hint hd0,msdos1 + linux /boot/vmlinuz root=3DLABEL=3Dlinux_vm $@{xen_grub_env_linux_appe= nd@} + initrd /boot/initrd.img +@} +@end example + @node Modules @chapter Modules =20 diff --git a/grub-core/Makefile.core.def b/grub-core/Makefile.core.def index b3f7119..df0f266 100644 --- a/grub-core/Makefile.core.def +++ b/grub-core/Makefile.core.def @@ -248,6 +248,7 @@ kernel =3D { xen =3D term/xen/console.c; xen =3D disk/xen/xendisk.c; xen =3D commands/boot.c; + xen =3D kern/xen/cmdline.c; =20 i386_xen_pvh =3D commands/boot.c; i386_xen_pvh =3D disk/xen/xendisk.c; @@ -255,6 +256,7 @@ kernel =3D { i386_xen_pvh =3D kern/i386/xen/tsc.c; i386_xen_pvh =3D kern/i386/xen/pvh.c; i386_xen_pvh =3D kern/xen/init.c; + i386_xen_pvh =3D kern/xen/cmdline.c; i386_xen_pvh =3D term/xen/console.c; =20 ia64_efi =3D kern/ia64/efi/startup.S; diff --git a/grub-core/kern/i386/xen/pvh.c b/grub-core/kern/i386/xen/pvh.c index 91fbca8..a8988d2 100644 --- a/grub-core/kern/i386/xen/pvh.c +++ b/grub-core/kern/i386/xen/pvh.c @@ -321,6 +321,8 @@ void grub_xen_setup_pvh (void) { grub_addr_t par; + const char *xen_cmdline; + int i; =20 grub_xen_cpuid_base (); grub_xen_setup_hypercall_page (); @@ -352,6 +354,27 @@ grub_xen_setup_pvh (void) grub_xen_mm_init_regions (); =20 grub_rsdp_addr =3D pvh_start_info->rsdp_paddr; + + xen_cmdline =3D (const char *) pvh_start_info->cmdline_paddr; + for (i =3D 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++) + { + if (xen_cmdline[i] =3D=3D '\0') + { + grub_strncpy ((char *) grub_xen_start_page_addr->cmd_line, + (char *) pvh_start_info->cmdline_paddr, + GRUB_XEN_MAX_GUEST_CMDLINE); + + if (grub_xen_start_page_addr->cmd_line[GRUB_XEN_MAX_GUEST_CMDLIN= E - 1] !=3D '\0') + { + grub_error (GRUB_ERR_BUG, + "Xen command line is not NUL-terminated"); + grub_print_error (); + grub_exit (); + } + + break; + } + } } =20 grub_err_t diff --git a/grub-core/kern/xen/cmdline.c b/grub-core/kern/xen/cmdline.c new file mode 100644 index 0000000..46a9998 --- /dev/null +++ b/grub-core/kern/xen/cmdline.c @@ -0,0 +1,376 @@ +/* + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2025 Free Software Foundation, Inc. + * + * GRUB is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * GRUB is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GRUB. If not, see . + */ + +#include +#include +#include +#include + +enum splitter_state +{ + SPLITTER_HIT_BACKSLASH =3D 0x1, + SPLITTER_IN_SINGLE_QUOTES =3D 0x2, + SPLITTER_IN_DOUBLE_QUOTES =3D 0x4, +}; +typedef enum splitter_state splitter_state_t; + +/* + * The initial size of the current_word buffer. The buffer may be resized = as + * needed. + */ +#define PARSER_BASE_WORD_SIZE 32 + +struct parser_state +{ + grub_size_t word_list_len; + char **word_list; + grub_size_t current_word_len; + grub_size_t current_word_pos; + char *current_word; +}; +typedef struct parser_state parser_state_t; + +static bool +append_char_to_word (parser_state_t *s, char c, bool allow_null) +{ + /* + * We ban any chars that are not in the ASCII printable range. If + * allow_null =3D=3D true, we make an exception for NUL. (This is needed= so that + * append_word_to_list can add a NUL terminator to the word). + */ + if (grub_isprint (c) =3D=3D false && allow_null =3D=3D false) + return false; + else if (allow_null =3D=3D true && c !=3D '\0') + return false; + + if (s->current_word_pos =3D=3D s->current_word_len) + { + s->current_word =3D grub_realloc (s->current_word, s->current_word_l= en *=3D 2); + if (s->current_word =3D=3D NULL) + { + s->current_word_len /=3D 2; + return false; + } + } + + s->current_word[s->current_word_pos++] =3D c; + return true; +} + +static bool +append_word_to_list (parser_state_t *s) +{ + /* No-op on empty words. */ + if (s->current_word_pos =3D=3D 0) + return true; + + if (append_char_to_word (s, '\0', true) =3D=3D false) + { + grub_error (GRUB_ERR_BUG, + "couldn't append NUL terminator to word during Xen cmdline parsing"); + grub_print_error (); + grub_exit (); + } + + s->current_word_len =3D grub_strlen (s->current_word) + 1; + s->current_word =3D grub_realloc (s->current_word, s->current_word_len); + if (s->current_word =3D=3D NULL) + return false; + s->word_list =3D grub_realloc (s->word_list, ++s->word_list_len * sizeof= (char *)); + if (s->word_list =3D=3D NULL) + return false; + s->word_list[s->word_list_len - 1] =3D s->current_word; + + s->current_word_len =3D PARSER_BASE_WORD_SIZE; + s->current_word_pos =3D 0; + s->current_word =3D grub_malloc (s->current_word_len); + if (s->current_word =3D=3D NULL) + return false; + + return true; +} + +static bool +is_key_safe (char *key, grub_size_t len) +{ + grub_size_t i; + + for (i =3D 0; i < len; i++) + { + if (! (grub_isalpha (key[i]) || key[i] =3D=3D '_')) + return false; + } + + return true; +} + +void +grub_parse_xen_cmdline (void) +{ + parser_state_t *s =3D NULL; + + const char *cmdline =3D (const char *) grub_xen_start_page_addr->cmd_lin= e; + grub_size_t cmdline_len; + bool cmdline_valid =3D false; + char **param_keys =3D NULL; + char **param_vals =3D NULL; + grub_size_t param_dict_len =3D 0; + grub_size_t param_dict_pos =3D 0; + splitter_state_t splitter_state =3D 0; + char current_char =3D '\0'; + grub_size_t i =3D 0; + + s =3D grub_malloc (sizeof (parser_state_t)); + if (s =3D=3D NULL) + goto cleanup_final; + + /* + * The following algorithm is used to parse the Xen command line: + * + * - The command line is split into space-separated words. + * - Single and double quotes may be used to suppress the splitting + * behavior of spaces. + * - Double quotes are appended to the current word verbatim if they + * appear within a single-quoted string portion, and vice versa. + * - Backslashes may be used to cause the next character to be + * appended to the current word verbatim. This is only useful when + * used to escape quotes, spaces, and backslashes, but for simplicity + * we allow backslash-escaping anything. + * - After splitting the command line into words, each word is checked to + * see if it contains an equals sign. + * - If it does, it is split on the equals sign into a key-value pair.= The + * key is then treated as an variable name, and the value is treated= as + * the variable's value. + * - If it does not, the entire word is treated as a variable name. The + * variable's value is implicitly considered to be `1`. + * - All variables detected on the command line are checked to see if th= eir + * names begin with the string `xen_grub_env_`. Variables that do not = pass + * this check are discarded, variables that do pass this check are + * exported so they are available to the GRUB configuration. + */ + + s->current_word_len =3D PARSER_BASE_WORD_SIZE; + s->current_word =3D grub_malloc (s->current_word_len); + if (s->current_word =3D=3D NULL) + goto cleanup_main; + + for (i =3D 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++) + { + if (cmdline[i] =3D=3D '\0') + { + cmdline_valid =3D true; + break; + } + } + + if (cmdline_valid =3D=3D false) + { + grub_error (GRUB_ERR_BAD_ARGUMENT, + "command line from Xen is not NUL-terminated"); + grub_print_error (); + goto cleanup_main; + } + + cmdline_len =3D grub_strlen (cmdline); + for (i =3D 0; i < cmdline_len; i++) + { + current_char =3D cmdline[i]; + + /* + * If the previous character was a backslash, append the current + * character to the word verbatim + */ + if (splitter_state & SPLITTER_HIT_BACKSLASH) + { + splitter_state &=3D ~SPLITTER_HIT_BACKSLASH; + if (append_char_to_word (s, current_char, false) =3D=3D false) + goto cleanup_main; + continue; + } + + switch (current_char) + { + case '\\': + /* Backslashes escape arbitrary characters. */ + splitter_state |=3D SPLITTER_HIT_BACKSLASH; + continue; + + case '\'': + /* + * Single quotes suppress word splitting and double quoting until + * the next single quote is encountered. + */ + if (splitter_state & SPLITTER_IN_DOUBLE_QUOTES) + { + if (append_char_to_word (s, current_char, false) =3D=3D fals= e) + goto cleanup_main; + continue; + } + + splitter_state ^=3D SPLITTER_IN_SINGLE_QUOTES; + continue; + + case '"': + /* + * Double quotes suppress word splitting and single quoting until + * the next double quote is encountered. + */ + if (splitter_state & SPLITTER_IN_SINGLE_QUOTES) + { + if (append_char_to_word (s, current_char, false) =3D=3D fals= e) + goto cleanup_main; + continue; + } + + splitter_state ^=3D SPLITTER_IN_DOUBLE_QUOTES; + continue; + + case ' ': + /* Spaces separate words in the command line from each other. */ + if (splitter_state & SPLITTER_IN_SINGLE_QUOTES || + splitter_state & SPLITTER_IN_DOUBLE_QUOTES) + { + if (append_char_to_word (s, current_char, false) =3D=3D fals= e) + goto cleanup_main; + continue; + } + + if (append_word_to_list (s) =3D=3D false) + goto cleanup_main; + continue; + } + + if (append_char_to_word (s, current_char, false) =3D=3D false) + goto cleanup_main; + } + + if (append_word_to_list (s) =3D=3D false) + goto cleanup_main; + + param_keys =3D grub_malloc (s->word_list_len * sizeof (char *)); + if (param_keys =3D=3D NULL) + goto cleanup_main; + param_vals =3D grub_malloc (s->word_list_len * sizeof (char *)); + if (param_vals =3D=3D NULL) + goto cleanup_main; + + for (i =3D 0; i < s->word_list_len; i++) + { + char *current_word_eq_ptr; + + s->current_word =3D s->word_list[i]; + s->current_word_len =3D grub_strlen (s->current_word) + 1; + current_word_eq_ptr =3D grub_strchr (s->current_word, '=3D'); + + if (current_word_eq_ptr !=3D NULL) + { + /* + * Both pre_eq_len and post_eq_len represent substring lengths + * without a NUL terminator. + */ + grub_size_t pre_eq_len =3D (grub_size_t) (current_word_eq_ptr - = s->current_word); + /* + * s->current_word_len includes the NUL terminator, so we subtra= ct + * one to get rid of the terminator, and one more to get rid of = the + * equals sign. + */ + grub_size_t post_eq_len =3D (s->current_word_len - 2) - pre_eq_l= en; + + if (is_key_safe (s->current_word, pre_eq_len) =3D=3D true) + { + param_dict_pos =3D param_dict_len++; + param_keys[param_dict_pos] =3D grub_malloc (pre_eq_len + 1); + if (param_keys =3D=3D NULL) + goto cleanup_main; + param_vals[param_dict_pos] =3D grub_malloc (post_eq_len + 1); + if (param_vals =3D=3D NULL) + goto cleanup_main; + + grub_strncpy (param_keys[param_dict_pos], s->current_word, p= re_eq_len); + grub_strncpy (param_vals[param_dict_pos], + s->current_word + pre_eq_len + 1, post_eq_len); + param_keys[param_dict_pos][pre_eq_len] =3D '\0'; + param_vals[param_dict_pos][post_eq_len] =3D '\0'; + } + } + else + { + if (is_key_safe (s->current_word, s->current_word_len - 1) =3D= =3D true) + { + param_dict_pos =3D param_dict_len++; + param_keys[param_dict_pos] =3D grub_malloc (s->current_word_= len); + if (param_keys =3D=3D NULL) + goto cleanup_main; + param_vals[param_dict_pos] =3D grub_malloc (2); + if (param_vals =3D=3D NULL) + goto cleanup_main; + + grub_strncpy (param_keys[param_dict_pos], s->current_word, + s->current_word_len); + if (param_keys[param_dict_pos][s->current_word_len - 1] !=3D= '\0' ) + { + grub_error (GRUB_ERR_BUG, + "NUL terminator missing from key during Xen cmdline parsing"); + grub_print_error (); + grub_exit (); + } + grub_strcpy (param_vals[param_dict_pos], "1"); + } + } + } + + for (i =3D 0; i < param_dict_len; i++) + { + /* + * Find keys that start with "xen_grub_env_" and export them + * as environment variables. + */ + if (grub_strncmp (param_keys[i], + "xen_grub_env_", + sizeof ("xen_grub_env_") - 1) !=3D 0) + continue; + + if (grub_env_set (param_keys[i], param_vals[i]) !=3D GRUB_ERR_NONE) + { + grub_printf ("warning: could not set environment variable `%s' t= o value `%s'\n", + param_keys[i], param_vals[i]); + continue; + } + + if (grub_env_export (param_keys[i]) !=3D GRUB_ERR_NONE) + grub_printf ("warning: could not export environment variable `%s'", + param_keys[i]); + } + + cleanup_main: + for (i =3D 0; i < s->word_list_len; i++) + grub_free (s->word_list[i]); + + for (i =3D 0; i < param_dict_len; i++) + { + grub_free (param_keys[i]); + grub_free (param_vals[i]); + } + + grub_free (param_keys); + grub_free (param_vals); + grub_free (s->word_list); + + cleanup_final: + grub_free (s); +} diff --git a/grub-core/kern/xen/init.c b/grub-core/kern/xen/init.c index 782ca72..69cf59f 100644 --- a/grub-core/kern/xen/init.c +++ b/grub-core/kern/xen/init.c @@ -581,6 +581,8 @@ grub_machine_init (void) grub_xendisk_init (); =20 grub_boot_init (); + + grub_parse_xen_cmdline (); } =20 void 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(Mailchimp) with ESMTP id 4bx3hP3S8yzNCd9N3 for ; Tue, 5 Aug 2025 06:40:21 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id 35fa034925814b74bbe826b3e4cc14e1; Tue, 05 Aug 2025 06:40:21 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0f6c5301-71c7-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1754376021; x=1754646021; bh=qCzkPd8313LLSTfHiY3PPprP7+lFyqmaCrjYFGWt89U=; h=From:Subject:Message-Id:To:Cc:References:In-Reply-To:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=E1dQH8sgePmZg9I40VxyEGZYheaFCMNARcM516aD/oA3jYcbGWCEdLnRqXkadTwrB kwCYflObQCbQesWQiAJRLXnwNUZ6DFHpr6C0DxeFWjkBENwwixZcnrZoxbqgF7tadr 9uHRPuvMQOYP2Yr0WsCN2QQftMXCTgKVhpLmWppWOY3IqUy6mcmNvZZEUv7+Ll6D5n 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4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1754376019184 Message-Id: <1e6c430a-0932-4742-b31e-c362e922d406@vates.tech> To: "=?utf-8?Q?Edwin=20T=C3=B6r=C3=B6k?=" , xen-devel@lists.xenproject.org Cc: "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "Stefano Stabellini" , "Bertrand Marquis" , "Volodymyr Babchuk" , boris.ostrovsky@oracle.com References: <49cbbacdc5f4fec624ae164a01eaa574aa771854.1753372928.git.edwin.torok@cloud.com> In-Reply-To: <49cbbacdc5f4fec624ae164a01eaa574aa771854.1753372928.git.edwin.torok@cloud.com> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.35fa034925814b74bbe826b3e4cc14e1?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20250805:md Date: Tue, 05 Aug 2025 06:40:21 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On 7/25/25 5:07 PM, Edwin T=C3=B6r=C3=B6k wrote: > diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c > index a6117dfebf..024d0c1eb7 100644 > --- a/xen/arch/x86/cpu/vpmu_amd.c > +++ b/xen/arch/x86/cpu/vpmu_amd.c > @@ -543,7 +543,7 @@ static const struct arch_vpmu_ops *__init common_init= (void) > } > > if ( sizeof(struct xen_pmu_data) + > - 2 * sizeof(uint64_t) * num_counters > PAGE_SIZE ) > + 2 * sizeof(uint64_t) * num_counters > MAX_XEN_PMU_DATA_SIZE) > { > printk(XENLOG_WARNING > "VPMU: Register bank does not fit into VPMU shared page\= n"); You've lost a space before the end of the parenthesis here > diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.= c > index 7ce98ee42e..9c8b5c1907 100644 > --- a/xen/arch/x86/cpu/vpmu_intel.c > +++ b/xen/arch/x86/cpu/vpmu_intel.c > @@ -967,7 +967,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(vo= id) > pmc_quirk =3D current_cpu_data.x86 =3D=3D 6; > > if ( sizeof(struct xen_pmu_data) + sizeof(uint64_t) * fixed_pmc_cnt= + > - sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt > PAGE_SIZE ) > + sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt > MAX_XEN_PMU_D= ATA_SIZE) > { > printk(XENLOG_WARNING > "VPMU: Register bank does not fit into VPMU share page\n= "); and here > diff --git a/xen/include/public/arch-x86/pmu.h b/xen/include/public/arch-= x86/pmu.h > index 5bd0aa6f77..bdc8218cbe 100644 > --- a/xen/include/public/arch-x86/pmu.h > +++ b/xen/include/public/arch-x86/pmu.h > @@ -129,67 +146,86 @@ struct xen_pmu_arch { > typedef struct xen_pmu_arch xen_pmu_arch_t; > DEFINE_XEN_GUEST_HANDLE(xen_pmu_arch_t); > > + > /* Memory layout: > -* =E2=95=AD=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=95= =AE > -* =E2=94=82 struct xen_pmu_data =E2=94=82 > -* =E2=95=92=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A7= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A7=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=95 =E2=97=81=E2=95=AE > -* =E2=94=82 vcpu_id = =E2=94=82 =E2=94=82 > -* =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4 =E2=94=82 > -* =E2=94=82 pcpu_id = =E2=94=82 =E2=94=82 > -* =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4 =E2=94=82 > -* =E2=94=82 domain_id = =E2=94=82 =E2=94=82 > -* =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4 =E2=94=82 > -* =E2=94=82=E2=96=88=E2=96=88pad=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=94=82 =E2=94=82 > -* =E2=95=9E=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90=E2=95= =A4=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1 =E2=94=82 > -* =E2=94=82 pmu=E2=94=82 =E2=94=82 r =E2=94=82 regs =E2=94= =82=E2=96=88=E2=96=88pad=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=95=AF =E2=94=9C=E2=94= =80=E2=94=80=E2=94=80=E2=95=AF (xen or guest) =E2=94=82=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=95=9E=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=A7=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1 =E2=94= =82 > -* =E2=94=82 =E2=94=82 pmu_flags = =E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=95=9E=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1 =E2=94= =82 > -* =E2=94=82 =E2=94=82 l =E2=94=82 lapic_lvtpc =E2=94=82=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=95=AF =E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=94=82=E2=96=88=E2=96=88pad=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=95=9E=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90= =E2=95=A4=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=A4=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=AA=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A4= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1 =E2=94= =82 > -* =E2=94=82 =E2=94=82 c =E2=94=82 =E2=94=82 =E2=94=82 amd =E2= =94=82 =E2=94=82 =E2=94=82 intel =E2=94=82 =E2=94=82=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94=82= =E2=95=B0=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=95=AF = =E2=94=82 =E2=95=B0=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=95=AF =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 counter =E2=94=82 fixe= d_counters =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=BC=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 ctrls =E2=94=82 arch= _counters =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=95=9E=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=A4=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90=E2=95=90=E2=95=90=E2=94=9C=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 regs[] =E2=94=82 = =E2=94=86=E2=94=82 global_ctrl =E2=94=82=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=95=AF =E2=94=86= =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82struct =E2=94=86=E2=94= =82 global_ovf_ctrl =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82xen_pmu_cntr_pair=E2=94=86=E2=94= =9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82[counters] =E2=94=86=E2=94= =82 global_status =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2=94= =9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2=94= =82 fixed_ctrl =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2=94= =9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2=94= =82 ds_area =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2=94= =9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2=94= =82 pebs_enable =E2=94=82=E2=96=88pad=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2=94= =9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 =E2=96=BD=E2=94= =82 debugctl =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=94=82 =E2=94=82 it looks like there is a stray space character here breaking up the vertical lines > -* =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= 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=E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 uint64_t= =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 [fixed_c= ounters] =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 = =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 = =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 = =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 struct = =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 xen_pmu_= cntr_pair=E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=95=98=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1 [arch_co= unters] =E2=94=86 =E2=95=9E=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=A1 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=86 =E2=94=82 =E2=94=82 =E2=94=82 > -* =E2=94=82 =E2=94=82 =E2=94=82 = =E2=96=BD =E2=94=82 =E2=94=82 =E2=94=82 same here > -* =E2=94=82 =E2=94=82 =E2=95=98=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= 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=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A7=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=95 =E2=97=81=E2=95=AE > + * =E2=94=82 vcpu_id = =E2=94=82 =E2=94=82 > + * =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4 =E2=94=82 > + * =E2=94=82 pcpu_id = =E2=94=82 =E2=94=82 > + * =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4 =E2=94=82 > + * =E2=94=82 domain_id = =E2=94=82 =E2=94=82 > + * =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= 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=90=E2=95=90=E2=95=90=E2=95=AA=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A4= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1 =E2=94= =82 > + * =E2=94=82 =E2=94=82 c =E2=94=82 =E2=94=82 =E2=94=82 amd = =E2=94=82 =E2=94=82 =E2=94=82 intel =E2=94=82 =E2=94=82=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=98 =E2=94= =82 =E2=95=B0=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=95=AF = =E2=94=82 =E2=95=B0=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=95=AF =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 counter =E2=94=82 fix= ed_counters =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=BC=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 ctrls =E2=94=82 arc= h_counters =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=95=9E=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=A4=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90=E2=95=90=E2=95=90=E2=94=9C=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=82 regs[] =E2=94=82= =E2=94=86=E2=94=82 global_ctrl =E2=94=82=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=94=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=95=AF =E2=94= =86=E2=94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82struct =E2=94=86=E2= =94=82 global_ovf_ctrl =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82xen_pmu_cntr_pair=E2=94=86=E2= =94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82[counters] =E2=94=86=E2= =94=82 global_status =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2= =94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2= =94=82 fixed_ctrl =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2= =94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2= =94=82 ds_area =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2= =94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2= =94=82 pebs_enable =E2=94=82=E2=96=88pad=E2=96=88=E2=94=82 =E2=94= =82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=94=86=E2= =94=9C=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=A4=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 =E2=96=BD=E2= =94=82 debugctl =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=94=82 =E2=94=82 and here > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=95=9E=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A4=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 = =E2=94=82 regs[] =E2=94=82 =E2=94=86[0]=E2=94=82=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 = =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=95=AF =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 uint64_t= =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 [fixed_c= ounters] =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 = =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 = =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2= =94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 = =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 struct = =E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 xen_pmu_= cntr_pair=E2=94=86 =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=95=98=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1 [arch_co= unters] =E2=94=86 =E2=95=9E=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=A1 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 = =E2=94=86 =E2=94=82 =E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=94=82 =E2=94=82 = =E2=96=BD =E2=94=82 =E2=94=82 =E2=94=82 and here > + * =E2=94=82 =E2=94=82 =E2=95=98=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=9B =E2=94=82 =E2=94=82 > + * =E2=94=82 =E2=95=98=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1 =E2=94= =82 > + * =E2=95=9E=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90= =E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2= =95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95=90=E2=95= =90=E2=95=90=E2=95=90=E2=95=90=E2=95=A1 =E2=94=82 > + * =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * =E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94= =86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86= =E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2= =94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94= =86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86= =E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2= =94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94= =86=E2=94=86=E2=94=86=E2=94=86=E2=94=86 =E2=94=86 > + * =E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94= =86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86= =E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2= =94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94= =86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86= =E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2= =94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94=86=E2=94= =86=E2=94=86=E2=94=86=E2=94=86=E2=94=86 =E2=94=86 > + * =E2=94=82=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88= =E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2= =96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96=88=E2=96= =88=E2=96=88=E2=96=88=E2=96=88=E2=94=82 =E2=94=82 > + * |############################################################| | > + * |##########.------------------------------.##################| | > + * |##########| struct xen_pmu_hv_stacktrace |##################| | > + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ | > + * | ^ [stacktrace_nr-1] | | > + * | : | | > + * | stacktrace[stacktrace_nr] : [0] | | > + * +------------------------------------------------------------+ | > + * | stacktrace_nr | | > + * +------------------------------------------------------------+ | > + * | guest_domain_id | | > + * +------------------------------------------------------------+ | > + * |##pad#######################################################| | > + * +=3D=3D=3D=3D=3D=3D=3D+=3D+=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ | > + * | guest | | r | regs |##pad######################| | > + * +-------. +---. (xen or guest) |###########################| | > + * | +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ | > + * | |##pad2############################################| | PAG= E_SIZE > + * +=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ <. > */ > > #endif /* __XEN_PUBLIC_ARCH_X86_PMU_H__ */ Andriy Sultanov | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From xen-devel-bounces@lists.xenproject.org Tue Aug 05 07:39:11 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 07:39:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070048.1433695 (Exim 4.92) (envelope-from ) id 1ujCGB-0000O9-Sr; Tue, 05 Aug 2025 07:38:59 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070048.1433695; Tue, 05 Aug 2025 07:38:59 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujCGB-0000O2-Q5; Tue, 05 Aug 2025 07:38:59 +0000 Received: by outflank-mailman (input) for mailman id 1070048; Tue, 05 Aug 2025 07:38:58 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujCGA-0000Nw-7c for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 07:38:58 +0000 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [2a00:1450:4864:20::635]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 3c2cc588-71cf-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 09:38:53 +0200 (CEST) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-ae3b336e936so845509366b.3 for ; Tue, 05 Aug 2025 00:38:53 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 05 Aug 2025 00:38:52 -0700 (PDT) Message-ID: <3e20688c-c125-4aa4-bc06-1fe634550f70@suse.com> Date: Tue, 5 Aug 2025 09:38:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 01/25] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE To: "Penny, Zheng" Cc: "Huang, Ray" , Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Anthony PERARD , "Orzel, Michal" , Julien Grall , Stefano Stabellini , "xen-devel@lists.xenproject.org" References: <20250803094738.3625269-1-Penny.Zheng@amd.com> <20250803094738.3625269-2-Penny.Zheng@amd.com> <371bc812-acdb-41ef-950b-3c9e5feea48e@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05.08.2025 05:38, Penny, Zheng wrote: > [Public] > >> -----Original Message----- >> From: Jan Beulich >> Sent: Monday, August 4, 2025 3:43 PM >> To: Penny, Zheng >> Cc: Huang, Ray ; Andrew Cooper >> ; Roger Pau Monné ; >> Anthony PERARD ; Orzel, Michal >> ; Julien Grall ; Stefano Stabellini >> ; xen-devel@lists.xenproject.org >> Subject: Re: [PATCH v1 01/25] xen/x86: move domctl.o out of >> PV_SHIM_EXCLUSIVE >> >> On 03.08.2025 11:47, Penny Zheng wrote: >>> In order to fix CI error of a randconfig picking both >>> PV_SHIM_EXCLUSIVE=y and HVM=y results in hvm.c being built, but >>> domctl.c not being built, which leaves a few functions, like >>> domctl_lock_acquire/release() undefined, causing linking to fail. >>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE >>> Makefile /hypercall-defs section, with this adjustment, we also need >>> to release redundant vnuma_destroy() stub definition and paging_domctl >>> hypercall-defs from PV_SHIM_EXCLUSIVE guardian, to not break >>> compilation Above change will leave dead code in the shim binary >>> temporarily and will be fixed with the introduction of CONFIG_DOMCTL. >>> >>> Fixes: 568f806cba4c ("xen/x86: remove "depends on >>> !PV_SHIM_EXCLUSIVE"") >>> Reported-by: Jan Beulich >>> Signed-off-by: Penny Zheng >>> --- >>> v1 -> v2: >>> - remove paging_domctl hypercall-defs >> >> And you've run this through a full round of testing this time, in isolation? > > This commit shall be committed together with "xen/x86: complement PG_log_dirty wrapping", (I've added in change log, idk why it didn't get delivered in the mail list in the last). And "committed together" still means the two at least build okay independently (i.e. allowing the build-each-commit job to succeed)? As to the missing indication thereof in the submission: Patch 01 has a revlog, so if anything was missing there you must have added it some other way. But the cover letter is lacking that information as well. (As indicated earlier, to increase the chance of such a remark actually being noticed, it's best put in both places.) > As PG_log_dirty is disabled on PV mode, paging_domctl() will still have "undefined reference" on PV mode, which gets fixed in "xen/x86: complement PG_log_dirty wrapping". I thought it better sits there. > If it doesn't comply with the commit policy, I'll move according fix here. Let me post a pair of patches dealing with part of the problem, in an imo (longer term) more desirable way. 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Tue, 05 Aug 2025 00:42:36 -0700 (PDT) Message-ID: <00eb26b1-de5f-4ca7-a7de-026ee33d594f@suse.com> Date: Tue, 5 Aug 2025 09:42:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 11/19] xen/x86: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc driver To: "Penny, Zheng" Cc: "Huang, Ray" , Andrew Cooper , Anthony PERARD , "Orzel, Michal" , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , "xen-devel@lists.xenproject.org" References: <20250711035106.2540522-1-Penny.Zheng@amd.com> <20250711035106.2540522-12-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05.08.2025 08:31, Penny, Zheng wrote: > [Public] > >> -----Original Message----- >> From: Jan Beulich >> Sent: Monday, August 4, 2025 4:48 PM >> To: Penny, Zheng >> Cc: Huang, Ray ; Andrew Cooper >> ; Anthony PERARD ; >> Orzel, Michal ; Julien Grall ; Roger Pau >> Monné ; Stefano Stabellini ; xen- >> devel@lists.xenproject.org >> Subject: Re: [PATCH v6 11/19] xen/x86: introduce "cpufreq=amd-cppc" xen cmdline >> and amd-cppc driver >> >> On 04.08.2025 10:09, Penny, Zheng wrote: >>> [Public] >>> >>>> -----Original Message----- >>>> From: Jan Beulich >>>> Sent: Thursday, July 17, 2025 12:00 AM >>>> To: Penny, Zheng >>>> Cc: Huang, Ray ; Andrew Cooper >>>> ; Anthony PERARD >>>> ; Orzel, Michal ; >>>> Julien Grall ; Roger Pau Monné >>>> ; Stefano Stabellini ; >>>> xen- devel@lists.xenproject.org >>>> Subject: Re: [PATCH v6 11/19] xen/x86: introduce "cpufreq=amd-cppc" >>>> xen cmdline and amd-cppc driver >>>> >>>> On 11.07.2025 05:50, Penny Zheng wrote: >>>>> --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c >>>>> +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c >>>>> @@ -128,12 +128,14 @@ static int __init cf_check >>>>> cpufreq_driver_init(void) >>>>> >>>>> if ( cpufreq_controller == FREQCTL_xen ) >>>>> { >>>>> + unsigned int i = 0; >>>> >>>> Pointless initializer; both for() loops set i to 0. But also see further down. >>>> >>>>> @@ -157,9 +164,70 @@ static int __init cf_check >>>>> cpufreq_driver_init(void) >>>>> >>>>> case X86_VENDOR_AMD: >>>>> case X86_VENDOR_HYGON: >>>>> - ret = IS_ENABLED(CONFIG_AMD) ? powernow_register_driver() : - >>>> ENODEV; >>>>> + if ( !IS_ENABLED(CONFIG_AMD) ) >>>>> + { >>>>> + ret = -ENODEV; >>>>> + break; >>>>> + } >>>>> + ret = -ENOENT; >>>> >>>> The code structure is sufficiently different from the Intel >>>> counterpart for this to perhaps better move ... >>>> >>>>> + for ( i = 0; i < cpufreq_xen_cnt; i++ ) >>>>> + { >>>>> + switch ( cpufreq_xen_opts[i] ) >>>>> + { >>>>> + case CPUFREQ_xen: >>>>> + ret = powernow_register_driver(); >>>>> + break; >>>>> + >>>>> + case CPUFREQ_amd_cppc: >>>>> + ret = amd_cppc_register_driver(); >>>>> + break; >>>>> + >>>>> + case CPUFREQ_none: >>>>> + ret = 0; >>>>> + break; >>>>> + >>>>> + default: >>>>> + printk(XENLOG_WARNING >>>>> + "Unsupported cpufreq driver for vendor AMD or Hygon\n"); >>>>> + break; >>>> >>>> ... here. >>>> >>> >>> Are we suggesting moving >>> " >>> if ( !IS_ENABLED(CONFIG_AMD) ) >>> { >>> ret = -ENODEV; >>> break; >>> } >>> " here? In which case, When CONFIG_AMD=n and users doesn't provide >>> "cpufreq=xxx", we will have cpufreq_xen_cnt initialized as 1 and >>> cpufreq_xen_opts[0] = CPUFREQ_xen. powernow_register_driver() hence >>> gets invoked. The thing is that we don't have stub for it and it is >>> compiled under CONFIG_AMD I suggest to change to use #ifdef CONFIG_AMD >>> code wrapping >>> >>>>> + } >>>>> + >>>>> + if ( !ret || ret == -EBUSY ) >>>>> + break; >>>>> + } >>>>> + >>>>> break; >>>>> } >>>>> + >>>>> + /* >>>>> + * After successful cpufreq driver registeration, >>>> XEN_PROCESSOR_PM_CPPC >>>>> + * and XEN_PROCESSOR_PM_PX shall become exclusive flags. >>>>> + */ >>>>> + if ( !ret ) >>>>> + { >>>>> + ASSERT(i < cpufreq_xen_cnt); >>>>> + switch ( cpufreq_xen_opts[i] ) >>>> >>>> Hmm, this is using the the initializer of i that I commented on. I >>>> think there's another default: case missing, where you simply "return 0" (to >> retain prior behavior). >>>> But again see also yet further down. >>>> >>>> >>>>> + /* >>>>> + * No cpufreq driver gets registered, clear both >>>>> + * XEN_PROCESSOR_PM_CPPC and XEN_PROCESSOR_PM_PX >>>>> + */ >>>>> + xen_processor_pmbits &= ~(XEN_PROCESSOR_PM_CPPC | >>>>> + XEN_PROCESSOR_PM_PX); >>>> >>>> Yet more hmm - this path you want to get through for the case mentioned above. >>>> But only this code; specifically not the "switch ( >>>> cpufreq_xen_opts[i] )", which really is "switch ( cpufreq_xen_opts[0] >>>> )" in that case, and that's pretty clearly wrong to evaluate in then. >>> >>> Correct me if I understand you wrongly: >>> The above "case missing" , are we talking about is entering "case >> CPUFREQ_none" ? >>> IMO, it may never be entered. If users doesn't provide "cpufreq=xxx", we will >> have cpufreq_xen_cnt initialized as 1 and cpufreq_xen_opts[0] = CPUFREQ_xen. >> That is, we will have px states as default driver. Even if we have failed px-driver >> initialization, with cpufreq_xen_cnt limited to 1, we will not enter CPUFREQ_none. >>> CPUFREQ_none only could be set when users explicitly set >>> "cpufreq=disabled/none/0", but in which case, cpufreq_controller will >>> be set with FREQCTL_none. And the whole cpufreq_driver_init() is under >>> " cpufreq_controller == FREQCTL_xen " condition Or "case missing" is >>> referring entering default case? In which case, we will have -ENOENT >>> errno. As we have ret=-ENOENT in the very beginning >> >> Sorry, this is hard to follow. Plus I think I made the main requirement quite >> clear: You want to "retain prior behavior" for all cases you don't deliberately change >> to accommodate the new driver. Plus you want to watch out for pre- existing >> incorrect behavior: Rather than proliferating any, such would want adjusting. >> > > I was trying to follow "there's another default: case missing, where you simply "return 0" (to retain prior behavior ) ", > The missing "default :" is referring the one for "switch ( boot_cpu_data.x86_vendor )"? (I thought it referred " switch ( cpufreq_xen_opts[i] ) " ....) > It is a pre- existing incorrect behavior which I shall create a new commit to fix it firstly > I'll add an -ENOENTRY initializer for ret at the very beginning , and complement the missing default: entry with "Unsupported vendor..." error log Yes, I was referring to pre-existing code which I think wants adjusting in order to then accommodate your changes there. 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Tue, 05 Aug 2025 00:44:59 -0700 (PDT) Message-ID: <795cf4c1-07be-47a5-b807-074b165650c4@suse.com> Date: Tue, 5 Aug 2025 09:44:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create To: Stewart Hildebrand Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Dario Faggioli , Juergen Gross , George Dunlap , xen-devel@lists.xenproject.org References: <20250801202418.38977-1-stewart.hildebrand@amd.com> <52ea4f10-26b4-447b-8753-0e4287a03408@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 04.08.2025 18:57, Stewart Hildebrand wrote: > On 8/4/25 03:57, Jan Beulich wrote: >> On 01.08.2025 22:24, Stewart Hildebrand wrote: >>> @@ -839,6 +839,9 @@ void sched_destroy_vcpu(struct vcpu *v) >>> { >>> struct sched_unit *unit = v->sched_unit; >>> >>> + if ( !unit ) >>> + return; >>> + >>> kill_timer(&v->periodic_timer); >>> kill_timer(&v->singleshot_timer); >>> kill_timer(&v->poll_timer); >> >> What if it's the 2nd error path in sched_init_vcpu() that is taken? Then we >> might take this path (just out of context here) >> >> if ( unit->vcpu_list == v ) >> { >> rcu_read_lock(&sched_res_rculock); >> >> sched_remove_unit(vcpu_scheduler(v), unit); >> sched_free_udata(vcpu_scheduler(v), unit->priv); >> >> and at least Credit1's hook doesn't look to be safe against being passed NULL. >> (Not to speak of the risk of unit->priv being used elsewhere while cleaning >> up.) > > > Are you referring to this error path in sched_init_vcpu? No, given the context I thought it was clear that I was referring to static void cf_check csched_free_udata(const struct scheduler *ops, void *priv) { struct csched_unit *svc = priv; BUG_ON( !list_empty(&svc->runq_elem) ); (i.e. particularly this BUG_ON()). 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Tue, 05 Aug 2025 00:57:29 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 09:57:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Penny Zheng From: Jan Beulich Subject: [PATCH 0/2] x86/mm: paging build adjustments Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit This is in the hope that it'll lead to a better overall result than plainly taking [1] and [2] (or whichever re-work thereof). 1: drop paging_get_mode() 2: correct PG_log_dirty definition Jan [1] https://lists.xen.org/archives/html/xen-devel/2025-08/msg00050.html [2] https://lists.xen.org/archives/html/xen-devel/2025-08/msg00051.html From xen-devel-bounces@lists.xenproject.org Tue Aug 05 07:58:31 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 07:58:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070083.1433736 (Exim 4.92) (envelope-from ) id 1ujCZ5-0004u6-6H; Tue, 05 Aug 2025 07:58:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070083.1433736; Tue, 05 Aug 2025 07:58:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujCZ5-0004tz-2l; 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Thus it has always been violating Misra rule 2.1 (unreachable code). Fixes: dd6de3ab9985 ("Implement Nested-on-Nested") Signed-off-by: Jan Beulich --- a/xen/arch/x86/include/asm/paging.h +++ b/xen/arch/x86/include/asm/paging.h @@ -225,7 +225,6 @@ int paging_enable(struct domain *d, u32 #define paging_get_hostmode(v) ((v)->arch.paging.mode) #define paging_get_nestedmode(v) ((v)->arch.paging.nestedmode) -const struct paging_mode *paging_get_mode(struct vcpu *v); void paging_update_nestedmode(struct vcpu *v); /* Page fault handler --- unstable.orig/xen/arch/x86/mm/paging.c 2025-08-05 08:59:15.512131147 +0200 +++ unstable/xen/arch/x86/mm/paging.c 2025-08-05 09:00:24.160657794 +0200 @@ -946,14 +946,6 @@ void paging_dump_vcpu_info(struct vcpu * } } -const struct paging_mode *paging_get_mode(struct vcpu *v) -{ - if (!nestedhvm_is_n2(v)) - return paging_get_hostmode(v); - - return paging_get_nestedmode(v); -} - #ifdef CONFIG_HVM void paging_update_nestedmode(struct vcpu *v) { From xen-devel-bounces@lists.xenproject.org Tue Aug 05 07:59:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 07:59:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070092.1433745 (Exim 4.92) (envelope-from ) id 1ujCZw-0005Rs-DX; Tue, 05 Aug 2025 07:59:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070092.1433745; Tue, 05 Aug 2025 07:59:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujCZw-0005Rl-Aw; Tue, 05 Aug 2025 07:59:24 +0000 Received: by outflank-mailman (input) for mailman id 1070092; Tue, 05 Aug 2025 07:59:22 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujCZu-0005FK-Qs for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 07:59:22 +0000 Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [2a00:1450:4864:20::531]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 1836bb6f-71d2-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 09:59:21 +0200 (CEST) Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-61553a028dfso5261368a12.0 for ; Tue, 05 Aug 2025 00:59:21 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 05 Aug 2025 00:59:20 -0700 (PDT) Message-ID: <65e27b35-9256-4ab0-966a-c50a18900ba5@suse.com> Date: Tue, 5 Aug 2025 09:59:19 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 2/2] x86/mm: correct PG_log_dirty definition From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Julien Grall , Stefano Stabellini , Anthony PERARD , Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Penny Zheng References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit While it is correct that in shim-exclusive mode log-dirty handling is all unreachable code, the present conditional still isn't correct: In a HVM=n and SHADOW_PAGING=n configuration log-dirty code also is all unreachable (and hence violating Misra rule 2.1). As we're aiming at moving away from special casing PV_SHIM_EXCLUSIVE=y, don't retain that part of the conditional. Because of hypercall-defs.c we need to carry out the dependency by introducing a new auxiliary PAGING control. Since compiling out mm/paging.c altogether would entail further changes, merely conditionalize the one function in there (paging_enable()) which would otherwise remain unreachable (Misra rule 2.1 again) when PAGING=n. Fixes: 23d4e0d17b76 ("x86/shim: fix build with PV_SHIM_EXCLUSIVE and SHADOW_PAGING") Signed-off-by: Jan Beulich --- Of course PAGING is at risk of being confused with MEM_PAGING. It not having a prompt, I hope that's tolerable, as I can't really think of a better name. Other PG_log_dirty pre-processor conditionals then likely also want replacing. mm/paging.c and mm/p2m-basic.c could also be compiled out altogether when PAGING=n, at the expense of introducing a few more stubs. FTAOD, the Fixes: tag being referenced does not mean this patch corrects the far more recently introduced build issue with the combination of the two features. That's still work that I expect Penny to carry out (with there still being the option of reverting the final part of the earlier series). --- a/xen/arch/x86/Kconfig +++ b/xen/arch/x86/Kconfig @@ -162,6 +162,9 @@ config SHADOW_PAGING If unsure, say Y. +config PAGING + def_bool HVM || SHADOW_PAGING + config BIGMEM bool "big memory support" default n --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -213,11 +213,15 @@ long arch_do_domctl( { case XEN_DOMCTL_shadow_op: +#ifdef CONFIG_PAGING ret = paging_domctl(d, &domctl->u.shadow_op, u_domctl, 0); if ( ret == -ERESTART ) return hypercall_create_continuation( __HYPERVISOR_paging_domctl_cont, "h", u_domctl); copyback = true; +#else + ret = -EOPNOTSUPP; +#endif break; case XEN_DOMCTL_ioport_permission: --- a/xen/arch/x86/include/asm/paging.h +++ b/xen/arch/x86/include/asm/paging.h @@ -55,7 +55,7 @@ #define PG_translate 0 #define PG_external 0 #endif -#if defined(CONFIG_HVM) || !defined(CONFIG_PV_SHIM_EXCLUSIVE) +#ifdef CONFIG_PAGING /* Enable log dirty mode */ #define PG_log_dirty (XEN_DOMCTL_SHADOW_ENABLE_LOG_DIRTY << PG_mode_shift) #else --- a/xen/arch/x86/mm/paging.c +++ b/xen/arch/x86/mm/paging.c @@ -864,6 +864,7 @@ void paging_final_teardown(struct domain p2m_final_teardown(d); } +#ifdef CONFIG_PAGING /* Enable an arbitrary paging-assistance mode. Call once at domain * creation. */ int paging_enable(struct domain *d, u32 mode) @@ -889,6 +890,7 @@ int paging_enable(struct domain *d, u32 else return shadow_enable(d, mode); } +#endif #ifdef CONFIG_HVM /* Called from the guest to indicate that a process is being torn down --- a/xen/include/hypercall-defs.c +++ b/xen/include/hypercall-defs.c @@ -197,9 +197,11 @@ dm_op(domid_t domid, unsigned int nr_buf #ifdef CONFIG_SYSCTL sysctl(xen_sysctl_t *u_sysctl) #endif +#if defined(CONFIG_X86) && defined(CONFIG_PAGING) +paging_domctl_cont(xen_domctl_t *u_domctl) +#endif #ifndef CONFIG_PV_SHIM_EXCLUSIVE domctl(xen_domctl_t *u_domctl) -paging_domctl_cont(xen_domctl_t *u_domctl) platform_op(xen_platform_op_t *u_xenpf_op) #endif #ifdef CONFIG_HVM @@ -296,7 +298,7 @@ dm_op compa hypfs_op do do do do do #endif mca do do - - - -#ifndef CONFIG_PV_SHIM_EXCLUSIVE +#if defined(CONFIG_X86) && defined(CONFIG_PAGING) paging_domctl_cont do do do do - #endif From xen-devel-bounces@lists.xenproject.org Tue Aug 05 08:02:09 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 08:02:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070105.1433755 (Exim 4.92) (envelope-from ) id 1ujCcZ-0007i7-W7; Tue, 05 Aug 2025 08:02:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070105.1433755; Tue, 05 Aug 2025 08:02:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujCcZ-0007i0-Se; Tue, 05 Aug 2025 08:02:07 +0000 Received: by outflank-mailman (input) for mailman id 1070105; Tue, 05 Aug 2025 08:02:06 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujCcY-0007hu-R7 for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 08:02:06 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 79b5efc5-71d2-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 10:02:04 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-af95b919093so350600566b.2 for ; Tue, 05 Aug 2025 01:02:04 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 05 Aug 2025 01:02:04 -0700 (PDT) Message-ID: <450982f5-4032-4b63-9635-40dbc10f6779@suse.com> Date: Tue, 5 Aug 2025 10:02:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/HVM: polish hvm_asid_init() a little From: Jan Beulich To: Oleksii Kurochko Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , "xen-devel@lists.xenproject.org" References: Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 04.08.2025 17:41, Jan Beulich wrote: > While the logic there covers asymmetric cases, the resulting log > messages would likely raise more confusion than clarify anything. Split > the BSP action from the AP one, indicating the odd CPU in the AP log > message, thus avoiding the impression that global state would have > changed. > > While there also > - move g_disabled into .data.ro_after_init; only the BSP will ever write > to it, > - make the function's parameter unsigned; no negative values may be > passed in. Also reflect this in svm_asid_init(). > > Signed-off-by: Jan Beulich Sorry, I meant to Cc: you on the submission, as it was the reviewing of your copied code which made me spot the shortcomings (which, as indicated, I think it would be nice if you avoided from the very start). Jan > --- a/xen/arch/x86/hvm/asid.c > +++ b/xen/arch/x86/hvm/asid.c > @@ -48,20 +48,22 @@ struct hvm_asid_data { > > static DEFINE_PER_CPU(struct hvm_asid_data, hvm_asid_data); > > -void hvm_asid_init(int nasids) > +void hvm_asid_init(unsigned int nasids) > { > - static int8_t g_disabled = -1; > + static int8_t __ro_after_init g_disabled = -1; > struct hvm_asid_data *data = &this_cpu(hvm_asid_data); > > data->max_asid = nasids - 1; > data->disabled = !opt_asid_enabled || (nasids <= 1); > > - if ( g_disabled != data->disabled ) > + if ( g_disabled < 0 ) > { > - printk("HVM: ASIDs %sabled.\n", data->disabled ? "dis" : "en"); > - if ( g_disabled < 0 ) > - g_disabled = data->disabled; > + g_disabled = data->disabled; > + printk("HVM: ASIDs %sabled\n", data->disabled ? "dis" : "en"); > } > + else if ( g_disabled != data->disabled ) > + printk("HVM: CPU%u: ASIDs %sabled\n", smp_processor_id(), > + data->disabled ? "dis" : "en"); > > /* Zero indicates 'invalid generation', so we start the count at one. */ > data->core_asid_generation = 1; > --- a/xen/arch/x86/hvm/svm/asid.c > +++ b/xen/arch/x86/hvm/svm/asid.c > @@ -12,7 +12,7 @@ > > void svm_asid_init(const struct cpuinfo_x86 *c) > { > - int nasids = 0; > + unsigned int nasids = 0; > > /* Check for erratum #170, and leave ASIDs disabled if it's present. */ > if ( !cpu_has_amd_erratum(c, AMD_ERRATUM_170) ) > --- a/xen/arch/x86/include/asm/hvm/asid.h > +++ b/xen/arch/x86/include/asm/hvm/asid.h > @@ -13,7 +13,7 @@ struct vcpu; > struct hvm_vcpu_asid; > > /* Initialise ASID management for the current physical CPU. */ > -void hvm_asid_init(int nasids); > +void hvm_asid_init(unsigned int nasids); > > /* Invalidate a particular ASID allocation: forces re-allocation. */ > void hvm_asid_flush_vcpu_asid(struct hvm_vcpu_asid *asid); From xen-devel-bounces@lists.xenproject.org Tue Aug 05 08:11:05 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 08:11:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070118.1433767 (Exim 4.92) (envelope-from ) id 1ujClA-00014B-UQ; Tue, 05 Aug 2025 08:11:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070118.1433767; Tue, 05 Aug 2025 08:11:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujClA-000144-Qc; Tue, 05 Aug 2025 08:11:00 +0000 Received: by outflank-mailman (input) for mailman id 1070118; Tue, 05 Aug 2025 08:10:59 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujCl9-00012l-7G for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 08:10:59 +0000 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [2a00:1450:4864:20::52e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id b6fb73af-71d3-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 10:10:57 +0200 (CEST) Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-615d1865b2dso6353499a12.0 for ; Tue, 05 Aug 2025 01:10:57 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 05 Aug 2025 01:10:56 -0700 (PDT) Message-ID: <889e32d2-b50f-4d61-b04b-6c73472abf23@suse.com> Date: Tue, 5 Aug 2025 10:10:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 4/4] vpci/msix: Free MSIX resources when init_msix() fails To: Jiqian Chen Cc: Huang Rui , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> <20250805034906.1014212-5-Jiqian.Chen@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250805034906.1014212-5-Jiqian.Chen@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05.08.2025 05:49, Jiqian Chen wrote: > When MSI-X initialization fails vPCI will hide the capability, but > remove of handlers and data won't be performed until the device is > deassigned. Introduce a MSI-X cleanup hook that will be called when > initialization fails to cleanup MSI-X related hooks and free it's > associated data. > > As all supported capabilities have been switched to use the cleanup > hooks call those from vpci_deassign_device() instead of open-code the > capability specific cleanup in there. > > Signed-off-by: Jiqian Chen > --- > cc: "Roger Pau Monné" > --- > v9->v10 changes: > * Call all cleanup hook in vpci_deassign_device() instead of cleanup_msix(). Isn't this rather an omission in an earlier change, and hence may want to come separately and with a Fixes: tag? > --- a/xen/drivers/vpci/vpci.c > +++ b/xen/drivers/vpci/vpci.c > @@ -321,6 +321,27 @@ void vpci_deassign_device(struct pci_dev *pdev) > &pdev->domain->vpci_dev_assigned_map); > #endif > > + for ( i = 0; i < NUM_VPCI_INIT; i++ ) > + { > + const vpci_capability_t *capability = &__start_vpci_array[i]; > + const unsigned int cap = capability->id; > + unsigned int pos = 0; > + > + if ( !capability->is_ext ) > + pos = pci_find_cap_offset(pdev->sbdf, cap); > + else if ( is_hardware_domain(pdev->domain) ) > + pos = pci_find_ext_capability(pdev->sbdf, cap); What's the point of doing this when ... > + if ( pos && capability->cleanup ) ... ->cleanup is NULL? Don't you want to have if ( !capability->cleanup ) continue; earlier on? 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Tue, 05 Aug 2025 01:15:56 -0700 (PDT) Message-ID: <321d07ea-1688-4036-a031-37c46dab5c15@suse.com> Date: Tue, 5 Aug 2025 10:15:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] misra: remove default case in single-clause switch To: Dmytro Prokopchuk1 Cc: Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , "xen-devel@lists.xenproject.org" References: <725ec86ac1aa883c35fb30b8f226c95cbe0934e9.1754322299.git.dmytro_prokopchuk1@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <725ec86ac1aa883c35fb30b8f226c95cbe0934e9.1754322299.git.dmytro_prokopchuk1@epam.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 04.08.2025 19:33, Dmytro Prokopchuk1 wrote: > MISRA Rule 16.4: Every switch statement shall have a default label. > The default clause must contain either a statement or a comment > prior to its terminating break statement. > > However, there is a documented deviation for this rule in Xen: > 'docs/misra/deviations.rst': > * - R16.4 > - A switch statement with a single clause and no default label > may replace an equivalent if statement to improve readability. > - Tagged as `deliberate` for ECLAIR. > > This change removes empty default cases in single-clause switches > to avoid violations of the rule where the `default` clause lacks > a suitable comment or statement. > > Signed-off-by: Dmytro Prokopchuk It's all CPU notifiers that you alter, and iirc the outcome of earlier discussion was that particularly for those we _want_ to add commentary, clarifying why only the given subset of notification need handling in the particular case. It may also well be that the (at least) one case of the possibly missing handling of some other notification still is unaddressed (and might hence be wrongly hidden by the adjustment done here, if it's in one of the function that are being altered). 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Tue, 05 Aug 2025 01:40:01 -0700 (PDT) Message-ID: <0c8458ea-9977-4ba9-8668-b09a65cf9172@suse.com> Date: Tue, 5 Aug 2025 10:40:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 4/4] vpci/msix: Free MSIX resources when init_msix() fails To: "Chen, Jiqian" Cc: "Huang, Ray" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , "xen-devel@lists.xenproject.org" References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> <20250805034906.1014212-5-Jiqian.Chen@amd.com> <889e32d2-b50f-4d61-b04b-6c73472abf23@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05.08.2025 10:27, Chen, Jiqian wrote: > On 2025/8/5 16:10, Jan Beulich wrote: >> On 05.08.2025 05:49, Jiqian Chen wrote: >>> When MSI-X initialization fails vPCI will hide the capability, but >>> remove of handlers and data won't be performed until the device is >>> deassigned. Introduce a MSI-X cleanup hook that will be called when >>> initialization fails to cleanup MSI-X related hooks and free it's >>> associated data. >>> >>> As all supported capabilities have been switched to use the cleanup >>> hooks call those from vpci_deassign_device() instead of open-code the >>> capability specific cleanup in there. >>> >>> Signed-off-by: Jiqian Chen >>> --- >>> cc: "Roger Pau Monné" >>> --- >>> v9->v10 changes: >>> * Call all cleanup hook in vpci_deassign_device() instead of cleanup_msix(). >> >> Isn't this rather an omission in an earlier change, and hence may want to >> come separately and with a Fixes: tag? > This is not really an omission, after all, all the cleanup hooks were implemented at the end of this series. > And judging from the commit message(which was written by Roger in v8), Roger also agreed to add them in this patch. I disagree. Of the two xfree()-s you remove here from vpci_deassign_device(), one should have been removed by patch 3 already. Which would require the part of the patch here to be put in place earlier on. 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Tue, 05 Aug 2025 01:43:10 -0700 (PDT) Message-ID: <775a45bd-61df-4cab-948e-bdc79dfd89ef@suse.com> Date: Tue, 5 Aug 2025 10:43:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 4/4] vpci/msix: Free MSIX resources when init_msix() fails To: Jiqian Chen Cc: Huang Rui , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> <20250805034906.1014212-5-Jiqian.Chen@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250805034906.1014212-5-Jiqian.Chen@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05.08.2025 05:49, Jiqian Chen wrote: > --- a/xen/drivers/vpci/msix.c > +++ b/xen/drivers/vpci/msix.c > @@ -655,6 +655,48 @@ int vpci_make_msix_hole(const struct pci_dev *pdev) > return 0; > } > > +static int cf_check cleanup_msix(const struct pci_dev *pdev) > +{ > + int rc; > + struct vpci *vpci = pdev->vpci; > + const unsigned int msix_pos = pdev->msix_pos; > + > + if ( !msix_pos ) > + return 0; > + > + rc = vpci_remove_registers(vpci, msix_control_reg(msix_pos), 2); > + if ( rc ) > + { > + printk(XENLOG_ERR "%pd %pp: fail to remove MSIX handlers rc=%d\n", > + pdev->domain, &pdev->sbdf, rc); > + ASSERT_UNREACHABLE(); > + return rc; > + } > + > + if ( vpci->msix ) > + { > + list_del(&vpci->msix->next); > + for ( unsigned int i = 0; i < ARRAY_SIZE(vpci->msix->table); i++ ) > + if ( vpci->msix->table[i] ) > + iounmap(vpci->msix->table[i]); > + > + XFREE(vpci->msix); > + } > + > + /* > + * The driver may not traverse the capability list and think device > + * supports MSIX by default. So here let the control register of MSIX > + * be Read-Only is to ensure MSIX disabled. > + */ > + rc = vpci_add_register(vpci, vpci_hw_read16, NULL, > + msix_control_reg(msix_pos), 2, NULL); > + if ( rc ) > + printk(XENLOG_ERR "%pd %pp: fail to add MSIX ctrl handler rc=%d\n", > + pdev->domain, &pdev->sbdf, rc); Here as well as for MSI: Wouldn't this better be limited to the init-failure case? No point in adding a register hook (and possibly emitting a misleading log message) when we're tearing down anyway. IOW I think the ->cleanup() hook needs a boolean parameter, unless the distinction of the two cases can be (reliably) inferred from some other property. > --- a/xen/drivers/vpci/vpci.c > +++ b/xen/drivers/vpci/vpci.c > @@ -321,6 +321,27 @@ void vpci_deassign_device(struct pci_dev *pdev) > &pdev->domain->vpci_dev_assigned_map); > #endif > > + for ( i = 0; i < NUM_VPCI_INIT; i++ ) > + { > + const vpci_capability_t *capability = &__start_vpci_array[i]; > + const unsigned int cap = capability->id; > + unsigned int pos = 0; > + > + if ( !capability->is_ext ) > + pos = pci_find_cap_offset(pdev->sbdf, cap); > + else if ( is_hardware_domain(pdev->domain) ) > + pos = pci_find_ext_capability(pdev->sbdf, cap); > + > + if ( pos && capability->cleanup ) > + { > + int rc = capability->cleanup(pdev); > + if ( rc ) > + printk(XENLOG_ERR "%pd %pp: clean %s cap %u fail rc=%d\n", > + pdev->domain, &pdev->sbdf, > + capability->is_ext ? "extended" : "legacy", cap, rc); > + } > + } With this imo the patch subject is now wrong, too. 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Tue, 05 Aug 2025 01:48:23 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 10:48:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 2/4] vpci/rebar: Free Rebar resources when init_rebar() fails To: Jiqian Chen Cc: Huang Rui , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , xen-devel@lists.xenproject.org References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> <20250805034906.1014212-3-Jiqian.Chen@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250805034906.1014212-3-Jiqian.Chen@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05.08.2025 05:49, Jiqian Chen wrote: > --- a/xen/drivers/vpci/rebar.c > +++ b/xen/drivers/vpci/rebar.c > @@ -49,6 +49,32 @@ static void cf_check rebar_ctrl_write(const struct pci_dev *pdev, > bar->guest_addr = bar->addr; > } > > +static int cf_check cleanup_rebar(const struct pci_dev *pdev) > +{ > + int rc; > + uint32_t ctrl; > + unsigned int nbars; > + unsigned int rebar_offset = pci_find_ext_capability(pdev->sbdf, > + PCI_EXT_CAP_ID_REBAR); > + > + if ( !rebar_offset || !is_hardware_domain(pdev->domain) ) > + { > + ASSERT_UNREACHABLE(); > + return 0; > + } > + > + ctrl = pci_conf_read32(pdev->sbdf, rebar_offset + PCI_REBAR_CTRL(0)); > + nbars = MASK_EXTR(ctrl, PCI_REBAR_CTRL_NBAR_MASK); > + > + rc = vpci_remove_registers(pdev->vpci, rebar_offset + PCI_REBAR_CAP(0), > + PCI_REBAR_CTRL(nbars - 1)); > + if ( rc ) > + printk(XENLOG_ERR "%pd %pp: fail to remove Rebar handlers rc=%d\n", > + pdev->domain, &pdev->sbdf, rc); MSI and MSI-X (now) have ASSERT_UNREACHABLE() on their respective paths. Is there a reason this shouldn't be done here as well? MSI and MSI-X further have another add-register below here, to ensure the control register cannot be written. Again - is there a reason the same shouldn't be done here? (If so, I think this may want putting in a comment.) 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pr=C Message-ID: <07c5f672-034a-46f0-a563-081a0d4ad0d5@amd.com> Date: Tue, 5 Aug 2025 05:06:30 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create To: Jan Beulich CC: Andrew Cooper , Anthony PERARD , Michal Orzel , "Julien Grall" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , "Dario Faggioli" , Juergen Gross , "George Dunlap" , References: <20250801202418.38977-1-stewart.hildebrand@amd.com> <52ea4f10-26b4-447b-8753-0e4287a03408@suse.com> <795cf4c1-07be-47a5-b807-074b165650c4@suse.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: <795cf4c1-07be-47a5-b807-074b165650c4@suse.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F68:EE_|SA5PPF5EA4322E1:EE_ X-MS-Office365-Filtering-Correlation-Id: e0ef121d-69c8-48a8-bbc9-08ddd3ff6221 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 09:06:37.2431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0ef121d-69c8-48a8-bbc9-08ddd3ff6221 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F68.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF5EA4322E1 On 8/5/25 03:44, Jan Beulich wrote: > On 04.08.2025 18:57, Stewart Hildebrand wrote: >> On 8/4/25 03:57, Jan Beulich wrote: >>> On 01.08.2025 22:24, Stewart Hildebrand wrote: >>>> @@ -839,6 +839,9 @@ void sched_destroy_vcpu(struct vcpu *v) >>>> { >>>> struct sched_unit *unit = v->sched_unit; >>>> >>>> + if ( !unit ) >>>> + return; >>>> + >>>> kill_timer(&v->periodic_timer); >>>> kill_timer(&v->singleshot_timer); >>>> kill_timer(&v->poll_timer); >>> >>> What if it's the 2nd error path in sched_init_vcpu() that is taken? ^^ This ^^ is what I'm confused about >>> Then we >>> might take this path (just out of context here) >>> >>> if ( unit->vcpu_list == v ) >>> { >>> rcu_read_lock(&sched_res_rculock); >>> >>> sched_remove_unit(vcpu_scheduler(v), unit); >>> sched_free_udata(vcpu_scheduler(v), unit->priv); >>> >>> and at least Credit1's hook doesn't look to be safe against being passed NULL. >>> (Not to speak of the risk of unit->priv being used elsewhere while cleaning >>> up.) >> >> >> Are you referring to this error path in sched_init_vcpu? > > No, given the context I thought it was clear that I was referring to > > static void cf_check > csched_free_udata(const struct scheduler *ops, void *priv) > { > struct csched_unit *svc = priv; > > BUG_ON( !list_empty(&svc->runq_elem) ); > > (i.e. particularly this BUG_ON()). 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Tue, 05 Aug 2025 02:17:27 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 11:17:26 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create To: Stewart Hildebrand Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Dario Faggioli , Juergen Gross , George Dunlap , xen-devel@lists.xenproject.org References: <20250801202418.38977-1-stewart.hildebrand@amd.com> <52ea4f10-26b4-447b-8753-0e4287a03408@suse.com> <795cf4c1-07be-47a5-b807-074b165650c4@suse.com> <07c5f672-034a-46f0-a563-081a0d4ad0d5@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <07c5f672-034a-46f0-a563-081a0d4ad0d5@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05.08.2025 11:06, Stewart Hildebrand wrote: > On 8/5/25 03:44, Jan Beulich wrote: >> On 04.08.2025 18:57, Stewart Hildebrand wrote: >>> On 8/4/25 03:57, Jan Beulich wrote: >>>> On 01.08.2025 22:24, Stewart Hildebrand wrote: >>>>> @@ -839,6 +839,9 @@ void sched_destroy_vcpu(struct vcpu *v) >>>>> { >>>>> struct sched_unit *unit = v->sched_unit; >>>>> >>>>> + if ( !unit ) >>>>> + return; >>>>> + >>>>> kill_timer(&v->periodic_timer); >>>>> kill_timer(&v->singleshot_timer); >>>>> kill_timer(&v->poll_timer); >>>> >>>> What if it's the 2nd error path in sched_init_vcpu() that is taken? > > ^^ This ^^ is what I'm confused about If sched_init_vcpu() took the indicated path, the if() you add here won't help, and ... >>>> Then we >>>> might take this path (just out of context here) >>>> >>>> if ( unit->vcpu_list == v ) >>>> { >>>> rcu_read_lock(&sched_res_rculock); >>>> >>>> sched_remove_unit(vcpu_scheduler(v), unit); >>>> sched_free_udata(vcpu_scheduler(v), unit->priv); >>>> >>>> and at least Credit1's hook doesn't look to be safe against being passed NULL. >>>> (Not to speak of the risk of unit->priv being used elsewhere while cleaning >>>> up.) >>> >>> >>> Are you referring to this error path in sched_init_vcpu? >> >> No, given the context I thought it was clear that I was referring to >> >> static void cf_check >> csched_free_udata(const struct scheduler *ops, void *priv) >> { >> struct csched_unit *svc = priv; >> >> BUG_ON( !list_empty(&svc->runq_elem) ); ... we'd make it here (afaict). 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pr=C Message-ID: Date: Tue, 5 Aug 2025 05:33:20 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create To: Jan Beulich CC: Andrew Cooper , Anthony PERARD , Michal Orzel , "Julien Grall" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , "Dario Faggioli" , Juergen Gross , "George Dunlap" , References: <20250801202418.38977-1-stewart.hildebrand@amd.com> <52ea4f10-26b4-447b-8753-0e4287a03408@suse.com> <795cf4c1-07be-47a5-b807-074b165650c4@suse.com> <07c5f672-034a-46f0-a563-081a0d4ad0d5@amd.com> Content-Language: en-US From: Stewart Hildebrand In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EB:EE_|PH8PR12MB8607:EE_ X-MS-Office365-Filtering-Correlation-Id: e2f23baf-63ee-42d7-de04-08ddd4031f28 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 09:33:22.7900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2f23baf-63ee-42d7-de04-08ddd4031f28 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8607 On 8/5/25 05:17, Jan Beulich wrote: > On 05.08.2025 11:06, Stewart Hildebrand wrote: >> On 8/5/25 03:44, Jan Beulich wrote: >>> On 04.08.2025 18:57, Stewart Hildebrand wrote: >>>> On 8/4/25 03:57, Jan Beulich wrote: >>>>> On 01.08.2025 22:24, Stewart Hildebrand wrote: >>>>>> @@ -839,6 +839,9 @@ void sched_destroy_vcpu(struct vcpu *v) >>>>>> { >>>>>> struct sched_unit *unit = v->sched_unit; >>>>>> >>>>>> + if ( !unit ) >>>>>> + return; >>>>>> + >>>>>> kill_timer(&v->periodic_timer); >>>>>> kill_timer(&v->singleshot_timer); >>>>>> kill_timer(&v->poll_timer); >>>>> >>>>> What if it's the 2nd error path in sched_init_vcpu() that is taken? >> >> ^^ This ^^ is what I'm confused about > > If sched_init_vcpu() took the indicated path, What path? In the one I'm looking at, sched_free_unit() gets called, setting v->sched_unit = NULL, and in that case ... > the if() you add here won't > help, and ... ... the condition is true, and ... >>>>> Then we >>>>> might take this path (just out of context here) >>>>> >>>>> if ( unit->vcpu_list == v ) >>>>> { >>>>> rcu_read_lock(&sched_res_rculock); >>>>> >>>>> sched_remove_unit(vcpu_scheduler(v), unit); >>>>> sched_free_udata(vcpu_scheduler(v), unit->priv); >>>>> >>>>> and at least Credit1's hook doesn't look to be safe against being passed NULL. >>>>> (Not to speak of the risk of unit->priv being used elsewhere while cleaning >>>>> up.) >>>> >>>> >>>> Are you referring to this error path in sched_init_vcpu? >>> >>> No, given the context I thought it was clear that I was referring to >>> >>> static void cf_check >>> csched_free_udata(const struct scheduler *ops, void *priv) >>> { >>> struct csched_unit *svc = priv; >>> >>> BUG_ON( !list_empty(&svc->runq_elem) ); > > ... we'd make it here (afaict). ... we'd not make it here. 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Tue, 05 Aug 2025 02:49:06 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 11:49:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create To: Stewart Hildebrand Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Dario Faggioli , Juergen Gross , George Dunlap , xen-devel@lists.xenproject.org References: <20250801202418.38977-1-stewart.hildebrand@amd.com> <52ea4f10-26b4-447b-8753-0e4287a03408@suse.com> <795cf4c1-07be-47a5-b807-074b165650c4@suse.com> <07c5f672-034a-46f0-a563-081a0d4ad0d5@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05.08.2025 11:33, Stewart Hildebrand wrote: > On 8/5/25 05:17, Jan Beulich wrote: >> On 05.08.2025 11:06, Stewart Hildebrand wrote: >>> On 8/5/25 03:44, Jan Beulich wrote: >>>> On 04.08.2025 18:57, Stewart Hildebrand wrote: >>>>> On 8/4/25 03:57, Jan Beulich wrote: >>>>>> On 01.08.2025 22:24, Stewart Hildebrand wrote: >>>>>>> @@ -839,6 +839,9 @@ void sched_destroy_vcpu(struct vcpu *v) >>>>>>> { >>>>>>> struct sched_unit *unit = v->sched_unit; >>>>>>> >>>>>>> + if ( !unit ) >>>>>>> + return; >>>>>>> + >>>>>>> kill_timer(&v->periodic_timer); >>>>>>> kill_timer(&v->singleshot_timer); >>>>>>> kill_timer(&v->poll_timer); >>>>>> >>>>>> What if it's the 2nd error path in sched_init_vcpu() that is taken? >>> >>> ^^ This ^^ is what I'm confused about >> >> If sched_init_vcpu() took the indicated path, > > What path? In the one I'm looking at, sched_free_unit() gets called, Oh, I see - that wasn't quite obvious, though. Yet of course ... > setting v->sched_unit = NULL, and in that case ... > >> the if() you add here won't >> help, and ... > > ... the condition is true, and ... > >>>>>> Then we >>>>>> might take this path (just out of context here) >>>>>> >>>>>> if ( unit->vcpu_list == v ) >>>>>> { >>>>>> rcu_read_lock(&sched_res_rculock); >>>>>> >>>>>> sched_remove_unit(vcpu_scheduler(v), unit); >>>>>> sched_free_udata(vcpu_scheduler(v), unit->priv); >>>>>> >>>>>> and at least Credit1's hook doesn't look to be safe against being passed NULL. >>>>>> (Not to speak of the risk of unit->priv being used elsewhere while cleaning >>>>>> up.) ... this latter part of my remark still applies. IOW I continue to think that discussing the correctness of this change needs to be extended. Unless of course a scheduler maintainer wants to ack it as is. Jan From xen-devel-bounces@lists.xenproject.org Tue Aug 05 09:53:14 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 09:53:14 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070223.1433866 (Exim 4.92) (envelope-from ) id 1ujEM5-0001yw-1D; Tue, 05 Aug 2025 09:53:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070223.1433866; Tue, 05 Aug 2025 09:53:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM4-0001yp-Tr; Tue, 05 Aug 2025 09:53:12 +0000 Received: by outflank-mailman (input) for mailman id 1070223; Tue, 05 Aug 2025 09:53:11 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM3-0001yh-AA for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 09:53:11 +0000 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [2a00:1450:4864:20::334]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fecbcb16-71e1-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 11:53:10 +0200 (CEST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-459e20ec1d9so4312975e9.3 for ; Tue, 05 Aug 2025 02:53:10 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. 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Patches 1 to 6 prepare the existing code to make it easier to introduce a new PDX compression, including generalizing the initialization and setup functions and adding a unit test for PDX compression. Patch 7 introduce the new compression. The new compression is only enabled by default on x86, other architectures are left with their previous defaults. Finally patch 8 optimizes one x86 loop that was iterating over pfn ranges to instead use pdx values. Thanks, Roger. Roger Pau Monne (8): kconfig: turn PDX compression into a choice pdx: provide a unified set of unit functions pdx: introduce command line compression toggle pdx: allow per-arch optimization of PDX conversion helpers test/pdx: add PDX compression unit tests pdx: move some helpers in preparation for new compression pdx: introduce a new compression algorithm based on region offsets x86/mm: adjust loop in arch_init_memory() to iterate over the PDX space CHANGELOG.md | 3 + docs/misc/xen-command-line.pandoc | 9 + tools/tests/Makefile | 1 + tools/tests/pdx/.gitignore | 3 + tools/tests/pdx/Makefile | 50 +++ tools/tests/pdx/harness.h | 98 ++++++ tools/tests/pdx/test-pdx.c | 271 ++++++++++++++++ xen/arch/arm/setup.c | 36 +-- xen/arch/x86/include/asm/cpufeatures.h | 1 + xen/arch/x86/include/asm/pdx.h | 71 ++++ xen/arch/x86/mm.c | 17 +- xen/arch/x86/srat.c | 30 +- xen/common/Kconfig | 37 ++- xen/common/pdx.c | 432 +++++++++++++++++++++++-- xen/include/xen/pdx.h | 213 ++++++++---- 15 files changed, 1139 insertions(+), 133 deletions(-) create mode 100644 tools/tests/pdx/.gitignore create mode 100644 tools/tests/pdx/Makefile create mode 100644 tools/tests/pdx/harness.h create mode 100644 tools/tests/pdx/test-pdx.c create mode 100644 xen/arch/x86/include/asm/pdx.h -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 09:53:15 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 09:53:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070224.1433876 (Exim 4.92) (envelope-from ) id 1ujEM7-0002Dq-BW; Tue, 05 Aug 2025 09:53:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070224.1433876; Tue, 05 Aug 2025 09:53:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM7-0002Dj-8U; Tue, 05 Aug 2025 09:53:15 +0000 Received: by outflank-mailman (input) for mailman id 1070224; Tue, 05 Aug 2025 09:53:13 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM5-00026G-NW for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 09:53:13 +0000 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [2a00:1450:4864:20::430]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id ff884533-71e1-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 11:53:11 +0200 (CEST) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3b78a034f17so3680053f8f.2 for ; Tue, 05 Aug 2025 02:53:11 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. [92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b79c4a2848sm18386766f8f.71.2025.08.05.02.53.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 02:53:10 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ff884533-71e1-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754387591; x=1754992391; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YlJ4EVtQhQPCSTEsURZWjPcV24GHkW+OWqt8tBVq6Ws=; b=Bqb0zdIl5Ehg6S4t4fbcZePweha19gznJngnQBceOvschwUHsqRaHKur5R+hsJYkFc SVfUK/NILHjcZfDbGu/mS35UforuNBcGGiphku7UZPdA0vNxx+vyDfALeqwdyFkcuzOP WX5YONmJuPBuA4K7ZKJpSt7XM5D0UJDfcNWB8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754387591; x=1754992391; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YlJ4EVtQhQPCSTEsURZWjPcV24GHkW+OWqt8tBVq6Ws=; b=MjDfJ0Mnykz83zQhrrob+juCkCf07zEf4sJibNtEHco41uMLvePFvo2boQ9jBiTk43 cTOt96d40Eca0sNXawul4Op6yUgGorOgA2fEl2gX1pBtSVK2gW/7jDY6s3EQpxcZCbcA r6tvnj9s01ywkftVFgmOJNY5ngWzqw/MqCgMQDSqfSVm1P6FPnWDKFq1aGqIDuzRCqDO dfRq+jDVtOGM0S9/mL9vyOhR2tTpMzxaLXeLO3o1N0uiK74lUpCWQpKbOMGWOe52BMug 20MTPQeHBK1Xa/rTHZdVF5wXgeByhd89LsdgHuvyMIYbc1Ql19NkkCZgSEkMElmVXu17 IKng== X-Gm-Message-State: AOJu0Yzo+mxDvc1YaFbXwPKSgjz/nbtG6Zc5YqNqr5DZKJ9zE/mM3QKP pvQhXs7B13Rq35dp4MmDWj4iuIoDOQIQFrKBi3NomokOatZjxLrOm+4/2RjoI5p7ia5bXESYBuc vYBkj X-Gm-Gg: ASbGnct+uaUa2jTRRQLmco4RKtM1sX80+ZUlfKjv5g53Ob3zKOkDbeHHSpSOvYSFchY Wwyrj5dEaFqfra0ArO8+vrtfmoRalBP72pmGTcEc77Yt+mjpYTGG/ZHdqBjibjNkF+vkBOha8GP 2j8G0Ic+zaoTkQzkHsux5dptJq1aXQmNBYBQwVn1KlLUwmkXSm+DBeZhONu1iaKUlniAocaepol tsQWiTdoP4JHnjqXfpC2+w5K4CHn3k3zn3RhYHkGlv+pM0GQAcYUAIlpZX3ZpWU0+YuHq/gOR1F Q5M3wwGvsG6nAkKE8rjzKNCL7n2JUwFC+jVijDkW/LgzVlQaDsaD62naunooALvGlxneudOvkgs eV6VxjpWhZL8HKtp6PK2b/EplT2Q2riJd3DK1Wn8f0p6/HAqPyEn4aK68wZjt1NtfrLwXyBcJcM /E X-Google-Smtp-Source: AGHT+IFwRXAghNgrt0pR2SwJ3D/h7HW/dZTVNoThRWg/S/KXqaZhSjs7CWT+IBx1cibnmwzVpiCsHg== X-Received: by 2002:a05:6000:220b:b0:3b7:792c:e8be with SMTP id ffacd0b85a97d-3b8d946c468mr8387219f8f.8.1754387590874; Tue, 05 Aug 2025 02:53:10 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich Subject: [PATCH v4 1/8] kconfig: turn PDX compression into a choice Date: Tue, 5 Aug 2025 11:52:50 +0200 Message-ID: <20250805095257.74975-2-roger.pau@citrix.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250805095257.74975-1-roger.pau@citrix.com> References: <20250805095257.74975-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename the current CONFIG_PDX_COMPRESSION to CONFIG_PDX_MASK_COMPRESSION, and make it part of the PDX compression choice block, in preparation for adding further PDX compression algorithms. The PDX compression defaults should still be the same for all architectures, however the choice block cannot be protected under EXPERT and still have a default choice being unconditionally selected. As a result, the new "PDX (Page inDeX) compression" item will be unconditionally visible in Kconfig, even on architectures like x86 that previously had no way to enable PDX compression. As part of this preparation work to introduce new PDX compressions, adjust some of the comments on pdx.h to note they apply to a specific PDX compression. Also shuffle function prototypes and dummy implementations around to make it easier to introduce a new PDX compression. Note all PDX compression implementations are expected to provide a pdx_is_region_compressible() that takes the same set of arguments. Signed-off-by: Roger Pau Monné Acked-by: Jan Beulich --- xen/arch/arm/setup.c | 2 +- xen/common/Kconfig | 18 +++++++++++++++--- xen/common/pdx.c | 4 ++-- xen/include/xen/pdx.h | 32 +++++++++++++++++++------------- 4 files changed, 37 insertions(+), 19 deletions(-) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index bb35afe56cec..a77b31071ed8 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -258,7 +258,7 @@ void __init init_pdx(void) paddr_t bank_start, bank_size, bank_end, ram_end = 0; int bank; -#ifdef CONFIG_PDX_COMPRESSION +#ifndef CONFIG_PDX_NONE /* * Arm does not have any restrictions on the bits to compress. Pass 0 to * let the common code further restrict the mask. diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 16936418a6e6..8dad0c923a9d 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -57,9 +57,10 @@ config EVTCHN_FIFO If unsure, say Y. -config PDX_COMPRESSION - bool "PDX (Page inDeX) compression" if EXPERT && !X86 && !RISCV - default ARM || PPC +choice + prompt "PDX (Page inDeX) compression" + default PDX_MASK_COMPRESSION if !X86 && !RISCV + default PDX_NONE help PDX compression is a technique designed to reduce the memory overhead of physical memory management on platforms with sparse RAM @@ -72,6 +73,17 @@ config PDX_COMPRESSION If your platform does not have sparse RAM banks, do not enable PDX compression. +config PDX_MASK_COMPRESSION + bool "Mask compression" + help + Compression relying on all RAM addresses sharing a zeroed bit region. + +config PDX_NONE + bool "None" + help + No compression +endchoice + config ALTERNATIVE_CALL bool diff --git a/xen/common/pdx.c b/xen/common/pdx.c index b8384e6189df..00aa7e43006d 100644 --- a/xen/common/pdx.c +++ b/xen/common/pdx.c @@ -34,7 +34,7 @@ bool __mfn_valid(unsigned long mfn) { bool invalid = mfn >= max_page; -#ifdef CONFIG_PDX_COMPRESSION +#ifdef CONFIG_PDX_MASK_COMPRESSION invalid |= mfn & pfn_hole_mask; #endif @@ -55,7 +55,7 @@ void set_pdx_range(unsigned long smfn, unsigned long emfn) __set_bit(idx, pdx_group_valid); } -#ifdef CONFIG_PDX_COMPRESSION +#ifdef CONFIG_PDX_MASK_COMPRESSION /* * Diagram to make sense of the following variables. The masks and shifts diff --git a/xen/include/xen/pdx.h b/xen/include/xen/pdx.h index c1423d64a95b..8e373cac8b87 100644 --- a/xen/include/xen/pdx.h +++ b/xen/include/xen/pdx.h @@ -25,7 +25,7 @@ * this by keeping a bitmap of the ranges in the frame table containing * invalid entries and not allocating backing memory for them. * - * ## PDX compression + * ## PDX mask compression * * This is a technique to avoid wasting memory on machines known to have * split their machine address space in several big discontinuous and highly @@ -101,22 +101,13 @@ bool __mfn_valid(unsigned long mfn); #define paddr_to_pdx(pa) pfn_to_pdx(paddr_to_pfn(pa)) #define pdx_to_paddr(px) pfn_to_paddr(pdx_to_pfn(px)) -#ifdef CONFIG_PDX_COMPRESSION +#ifdef CONFIG_PDX_MASK_COMPRESSION extern unsigned long pfn_pdx_bottom_mask, ma_va_bottom_mask; extern unsigned int pfn_pdx_hole_shift; extern unsigned long pfn_hole_mask; extern unsigned long pfn_top_mask, ma_top_mask; -/** - * Validate a region's compatibility with the current compression runtime - * - * @param base Base address of the region - * @param npages Number of PAGE_SIZE-sized pages in the region - * @return True iff the region can be used with the current compression - */ -bool pdx_is_region_compressible(paddr_t base, unsigned long npages); - /** * Calculates a mask covering "moving" bits of all addresses of a region * @@ -209,7 +200,9 @@ static inline paddr_t directmapoff_to_maddr(unsigned long offset) */ void pfn_pdx_hole_setup(unsigned long mask); -#else /* !CONFIG_PDX_COMPRESSION */ +#endif /* CONFIG_PDX_MASK_COMPRESSION */ + +#ifdef CONFIG_PDX_NONE /* Without PDX compression we can skip some computations */ @@ -241,7 +234,20 @@ static inline void pfn_pdx_hole_setup(unsigned long mask) { } -#endif /* CONFIG_PDX_COMPRESSION */ +#else /* !CONFIG_PDX_NONE */ + +/* Shared functions implemented by all PDX compressions. */ + +/** + * Validate a region's compatibility with the current compression runtime + * + * @param base Base address of the region + * @param npages Number of PAGE_SIZE-sized pages in the region + * @return True iff the region can be used with the current compression + */ +bool pdx_is_region_compressible(paddr_t base, unsigned long npages); + +#endif /* !CONFIG_PDX_NONE */ #endif /* __XEN_PDX_H__ */ /* -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 09:53:15 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 09:53:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070225.1433880 (Exim 4.92) (envelope-from ) id 1ujEM7-0002GL-Kh; Tue, 05 Aug 2025 09:53:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070225.1433880; Tue, 05 Aug 2025 09:53:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM7-0002Fc-Gq; Tue, 05 Aug 2025 09:53:15 +0000 Received: by outflank-mailman (input) for mailman id 1070225; Tue, 05 Aug 2025 09:53:14 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM6-0001yh-UM for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 09:53:14 +0000 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [2a00:1450:4864:20::42c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 012038fb-71e2-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 11:53:14 +0200 (CEST) Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-3b78127c5d1so3045203f8f.3 for ; Tue, 05 Aug 2025 02:53:14 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. 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The disabling is done by turning pfn_pdx_add_region() into a no-op, so when attempting to initialize the selected compression algorithm the array of ranges to compress is empty. Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich --- Changes since v1: - New in this version. --- docs/misc/xen-command-line.pandoc | 9 +++++++++ xen/common/pdx.c | 14 +++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc index 6865a61220ca..5dd2ab82b7aa 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -2072,6 +2072,15 @@ for all of them (`true`), only for those subject to XPTI (`xpti`) or for those not subject to XPTI (`no-xpti`). The feature is used only in case INVPCID is supported and not disabled via `invpcid=false`. +### pdx-compress +> `= ` + +> Default: `true` if CONFIG_PDX_NONE is unset + +Only relevant when the hypervisor is build with PFN PDX compression. Controls +whether Xen will engage in PFN compression. The algorithm used for PFN +compression is selected at build time from Kconfig. + ### ple_gap > `= ` diff --git a/xen/common/pdx.c b/xen/common/pdx.c index c5ea58873c0e..f4a3dcf6cb60 100644 --- a/xen/common/pdx.c +++ b/xen/common/pdx.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -76,9 +77,13 @@ static struct pfn_range { } ranges[MAX_PFN_RANGES] __initdata; static unsigned int __initdata nr_ranges; +static bool __initdata pdx_compress = true; +boolean_param("pdx-compress", pdx_compress); + void __init pfn_pdx_add_region(paddr_t base, paddr_t size) { - if ( !size ) + /* Without ranges there's no PFN compression. */ + if ( !size || !pdx_compress ) return; if ( nr_ranges >= ARRAY_SIZE(ranges) ) @@ -215,6 +220,13 @@ void __init pfn_pdx_compression_setup(paddr_t base) unsigned int i, j, bottom_shift = 0, hole_shift = 0; unsigned long mask = pdx_init_mask(base) >> PAGE_SHIFT; + if ( !nr_ranges ) + { + printk(XENLOG_DEBUG "PFN compression disabled%s\n", + pdx_compress ? ": no ranges provided" : ""); + return; + } + if ( nr_ranges > ARRAY_SIZE(ranges) ) { printk(XENLOG_WARNING -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 09:53:17 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 09:53:17 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070226.1433897 (Exim 4.92) (envelope-from ) id 1ujEM8-0002gx-TV; Tue, 05 Aug 2025 09:53:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070226.1433897; Tue, 05 Aug 2025 09:53:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM8-0002g8-Nu; Tue, 05 Aug 2025 09:53:16 +0000 Received: by outflank-mailman (input) for mailman id 1070226; Tue, 05 Aug 2025 09:53:15 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM7-00026G-61 for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 09:53:15 +0000 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [2a00:1450:4864:20::32c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 00800a5b-71e2-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 11:53:13 +0200 (CEST) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-459e39ee7ccso2003675e9.2 for ; Tue, 05 Aug 2025 02:53:13 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. [92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-458f713eb44sm104033275e9.14.2025.08.05.02.53.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 02:53:11 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 00800a5b-71e2-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754387592; x=1754992392; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vsHoH88Bq1GawZ6maquU1VqYJOWUKfDJ8Tpkog2WGL4=; b=mzdWx2O/lD84MrDcO+0WpXXyTYnJxi12qxaNuB5dYjjD+JrarMO3EE6ZdCA56hXEcH aftY6E+50Q333rRBfvUeLXMyPBdigtvAxvUocEOA4NYTeelMPNAb7DUTk7zJa9V/xGgh u1JTcmIOTxuEaid2ViYUYleRH+O020abq2mrg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754387592; x=1754992392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vsHoH88Bq1GawZ6maquU1VqYJOWUKfDJ8Tpkog2WGL4=; b=i37j8RcRSskP8JM7XmYuG2qYXdpg0Eyt2vNXuVx7KHy+6SWiHWbKvX8p11FA6wg1Ws li8pV9NXEXeklzeIKpa/nN8P/qhOq/qjfWlSTeOpq4uj1P5tmQKFdZvaSbvSaPloAh3c 8JPQXd2yCmSYYT5JsfQ6NYVU/iztcrQFpBYL4gOjZPq+pVnZD/JQIf3wJeTdVWYbW5wu 0v6MlWXmdndDEs7LZjSG/Rf0w/0z2KHKd9Dc0ZjIVeiwii437YgaRUEq3LhDfxNd+OSB UsUOBpkiSShVPZpXm+KjxnEzPMuIUdt7Jq8aYCusIQhrWTksvVaR9YkWNIj8h0KNC4ah ZLWQ== X-Gm-Message-State: AOJu0YzPjG5JfQOgMlJux5SI30qbWt8DjPRaaSzOYPjZQEGb0QjLiBal zsnrxRgIzehUXS8zYPT49wx1/R+KTpt+T2EdeotFJzWSHpQ0mRFwo1CUsNtviMdfzNj4V/XWR/l 3uvZX X-Gm-Gg: ASbGnctL2SaReDRMbduPIYC6IDOxTRs0xskvd+lrAAJDSxn6OJsk7Yb2YuHSsHUnei5 10ilmxrDFwragg9I+Vxi2Hu7JwuzntjVegHQiwuYIxuZSCdQDEJhz+yZVt9C6CZDTXV190NpGJG y6EJ7ZpTNxnWbut/tpDzu+60cQBLNT1wV5CXjlvf6PHhdpaGBCDfaMxHJY5ihQUIweXM2mAtnva ZrftDBtfV8sXjNisQpJ02O9ECFV32BrqK59rFhzaScS2k2mKEfERwrl56kM798xhyH7/v3U2fv3 4vCt/7qWE+3e7HQ8KUs44d39UOdmBRuvA0arIDpgv46DxInjEeKi1zyx2/IGQxBM5RSrepdddBr l8LPVINqzY5QhKI3wW+gI2p1Jrrd2o3LJ+xvAXuj5ca7ZeSif68w7oWkfzxf/e5wMaA== X-Google-Smtp-Source: AGHT+IFxvIar0IThaZT++liEgv3hQugAJuhVSOQvcs5FezgqdkMBUhbPoarb4rJsxvS11/W+diaoFA== X-Received: by 2002:a05:600c:3b9c:b0:459:d3d0:650e with SMTP id 5b1f17b1804b1-459d3d065f9mr68179545e9.13.1754387592065; Tue, 05 Aug 2025 02:53:12 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich Subject: [PATCH v4 2/8] pdx: provide a unified set of unit functions Date: Tue, 5 Aug 2025 11:52:51 +0200 Message-ID: <20250805095257.74975-3-roger.pau@citrix.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250805095257.74975-1-roger.pau@citrix.com> References: <20250805095257.74975-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current setup (pdx_init_mask() and pdx_region_mask()) and init (pfn_pdx_hole_setup()) PDX compression functions are tailored to the existing PDX compression algorithm. In preparation for introducing a new compression algorithm convert the setup and init functions to more generic interfaces that aren't tied to the compression in-use. To accomplish this introduce a function that registers all the PFN RAM ranges, plus an init function. This has the downside of requiring a static array to store such ranges ahead of being processed by the setup function, however it's the only way to pass all the possible information to the different compression setup functions without using per-compression specific setup functions. Per-arch compression setup also need to be adjusted to use the new interface. There's a slight ordering adjustment, in that after PDX compression setup the caller will check whether all the RAM regions are properly covered by the newly setup compression, otherwise compression is disabled by resetting to the initial values. No functional change intended in the resulting PDX compression values. Signed-off-by: Roger Pau Monné Acked-by: Jan Beulich --- Changes since v3: - Rename base to base_pfn and size to pages. Changes since v2: - Fix indentation. Changes since v1: - s/nr/nr_ranges/ --- xen/arch/arm/setup.c | 34 ++++++------ xen/arch/x86/srat.c | 28 ++++++---- xen/common/pdx.c | 122 ++++++++++++++++++++++++++++++++++++------ xen/include/xen/pdx.h | 73 +++++++++---------------- 4 files changed, 166 insertions(+), 91 deletions(-) diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index a77b31071ed8..ba35bf1fe3bb 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -256,9 +256,11 @@ void __init init_pdx(void) { const struct membanks *mem = bootinfo_get_mem(); paddr_t bank_start, bank_size, bank_end, ram_end = 0; - int bank; + unsigned int bank; #ifndef CONFIG_PDX_NONE + for ( bank = 0 ; bank < mem->nr_banks; bank++ ) + pfn_pdx_add_region(mem->bank[bank].start, mem->bank[bank].size); /* * Arm does not have any restrictions on the bits to compress. Pass 0 to * let the common code further restrict the mask. @@ -266,26 +268,24 @@ void __init init_pdx(void) * If the logic changes in pfn_pdx_hole_setup we might have to * update this function too. */ - uint64_t mask = pdx_init_mask(0x0); - - for ( bank = 0 ; bank < mem->nr_banks; bank++ ) - { - bank_start = mem->bank[bank].start; - bank_size = mem->bank[bank].size; - - mask |= bank_start | pdx_region_mask(bank_start, bank_size); - } + pfn_pdx_compression_setup(0); for ( bank = 0 ; bank < mem->nr_banks; bank++ ) { - bank_start = mem->bank[bank].start; - bank_size = mem->bank[bank].size; - - if (~mask & pdx_region_mask(bank_start, bank_size)) - mask = 0; + if ( !pdx_is_region_compressible( + mem->bank[bank].start, + PFN_UP(mem->bank[bank].start + mem->bank[bank].size) - + PFN_DOWN(mem->bank[bank].start)) ) + { + pfn_pdx_compression_reset(); + printk(XENLOG_WARNING + "PFN compression disabled, RAM region [%#" PRIpaddr ", %#" + PRIpaddr "] not covered\n", + mem->bank[bank].start, + mem->bank[bank].start + mem->bank[bank].size - 1); + break; + } } - - pfn_pdx_hole_setup(mask >> PAGE_SHIFT); #endif for ( bank = 0 ; bank < mem->nr_banks; bank++ ) diff --git a/xen/arch/x86/srat.c b/xen/arch/x86/srat.c index 688f410287d4..747607439fb4 100644 --- a/xen/arch/x86/srat.c +++ b/xen/arch/x86/srat.c @@ -261,8 +261,6 @@ acpi_numa_memory_affinity_init(const struct acpi_srat_mem_affinity *ma) void __init acpi_numa_arch_fixup(void) {} -static uint64_t __initdata srat_region_mask; - static int __init cf_check srat_parse_region( struct acpi_subtable_header *header, const unsigned long end) { @@ -282,15 +280,13 @@ static int __init cf_check srat_parse_region( printk(KERN_INFO "SRAT: %013"PRIx64"-%013"PRIx64"\n", ma->base_address, ma->base_address + ma->length - 1); - srat_region_mask |= ma->base_address | - pdx_region_mask(ma->base_address, ma->length); + pfn_pdx_add_region(ma->base_address, ma->length); return 0; } void __init srat_parse_regions(paddr_t addr) { - u64 mask; unsigned int i; if (acpi_disabled || acpi_numa < 0 || @@ -299,19 +295,29 @@ void __init srat_parse_regions(paddr_t addr) /* Set "PXM" as early as feasible. */ numa_fw_nid_name = "PXM"; - srat_region_mask = pdx_init_mask(addr); acpi_table_parse_srat(ACPI_SRAT_TYPE_MEMORY_AFFINITY, srat_parse_region, 0); - for (mask = srat_region_mask, i = 0; mask && i < e820.nr_map; i++) { + pfn_pdx_compression_setup(addr); + + /* Ensure all RAM ranges in the e820 are covered. */ + for (i = 0; i < e820.nr_map; i++) { if (e820.map[i].type != E820_RAM) continue; - if (~mask & pdx_region_mask(e820.map[i].addr, e820.map[i].size)) - mask = 0; + if (!pdx_is_region_compressible( + e820.map[i].addr, + PFN_UP(e820.map[i].addr + e820.map[i].size) - + PFN_DOWN(e820.map[i].addr))) { + pfn_pdx_compression_reset(); + printk(XENLOG_WARNING + "PFN compression disabled, RAM region [%#" PRIx64 + ", %#" PRIx64 "] not covered\n", + e820.map[i].addr, + e820.map[i].addr + e820.map[i].size - 1); + return; + } } - - pfn_pdx_hole_setup(mask >> PAGE_SHIFT); } unsigned int numa_node_to_arch_nid(nodeid_t n) diff --git a/xen/common/pdx.c b/xen/common/pdx.c index 00aa7e43006d..c5ea58873c0e 100644 --- a/xen/common/pdx.c +++ b/xen/common/pdx.c @@ -19,6 +19,7 @@ #include #include #include +#include #include /** @@ -55,6 +56,44 @@ void set_pdx_range(unsigned long smfn, unsigned long emfn) __set_bit(idx, pdx_group_valid); } +#ifndef CONFIG_PDX_NONE + +#ifdef CONFIG_X86 +# include +# define MAX_PFN_RANGES E820MAX +#elif defined(CONFIG_HAS_DEVICE_TREE_DISCOVERY) +# include +# define MAX_PFN_RANGES NR_MEM_BANKS +#endif + +#ifndef MAX_PFN_RANGES +# error "Missing architecture maximum number of RAM ranges" +#endif + +/* Generic PFN compression helpers. */ +static struct pfn_range { + unsigned long base_pfn, pages; +} ranges[MAX_PFN_RANGES] __initdata; +static unsigned int __initdata nr_ranges; + +void __init pfn_pdx_add_region(paddr_t base, paddr_t size) +{ + if ( !size ) + return; + + if ( nr_ranges >= ARRAY_SIZE(ranges) ) + { + ASSERT((nr_ranges + 1) > nr_ranges); + nr_ranges++; + return; + } + + ranges[nr_ranges].base_pfn = PFN_DOWN(base); + ranges[nr_ranges++].pages = PFN_UP(base + size) - PFN_DOWN(base); +} + +#endif /* !CONFIG_PDX_NONE */ + #ifdef CONFIG_PDX_MASK_COMPRESSION /* @@ -115,20 +154,25 @@ static uint64_t fill_mask(uint64_t mask) return mask; } -bool pdx_is_region_compressible(paddr_t base, unsigned long npages) -{ - return !(paddr_to_pfn(base) & pfn_hole_mask) && - !(pdx_region_mask(base, npages * PAGE_SIZE) & ~ma_va_bottom_mask); -} - -/* We don't want to compress the low MAX_ORDER bits of the addresses. */ -uint64_t __init pdx_init_mask(uint64_t base_addr) -{ - return fill_mask(max(base_addr, - (uint64_t)1 << (MAX_ORDER + PAGE_SHIFT)) - 1); -} - -uint64_t pdx_region_mask(uint64_t base, uint64_t len) +/** + * Calculates a mask covering "moving" bits of all addresses of a region + * + * The i-th bit of the mask must be set if there's 2 different addresses + * in the region that have different j-th bits. where j >= i. + * + * e.g: + * base=0x1B00000000 + * len+base=0x1B00042000 + * + * ought to return 0x000007FFFF, which implies that every bit position + * with a zero in the mask remains unchanged in every address of the + * region. + * + * @param base Base address of the region + * @param len Size in octets of the region + * @return Mask of moving bits at the bottom of all the region addresses + */ +static uint64_t pdx_region_mask(uint64_t base, uint64_t len) { /* * We say a bit "moves" in a range if there exist 2 addresses in that @@ -143,9 +187,45 @@ uint64_t pdx_region_mask(uint64_t base, uint64_t len) return fill_mask(base ^ (base + len - 1)); } -void __init pfn_pdx_hole_setup(unsigned long mask) +bool pdx_is_region_compressible(paddr_t base, unsigned long npages) +{ + return !(paddr_to_pfn(base) & pfn_hole_mask) && + !(pdx_region_mask(base, npages * PAGE_SIZE) & ~ma_va_bottom_mask); +} + +/** + * Creates the mask to start from when calculating non-compressible bits + * + * This function is intimately related to pdx_region_mask(), and together + * they are meant to calculate the mask of non-compressible bits given the + * current memory map. + * + * @param base_addr Address of the first maddr in the system + * @return An integer of the form 2^n - 1 + */ +static uint64_t __init pdx_init_mask(uint64_t base_addr) +{ + return fill_mask(max(base_addr, + /* Don't compress the low MAX_ORDER bits. */ + (uint64_t)1 << (MAX_ORDER + PAGE_SHIFT)) - 1); +} + +void __init pfn_pdx_compression_setup(paddr_t base) { unsigned int i, j, bottom_shift = 0, hole_shift = 0; + unsigned long mask = pdx_init_mask(base) >> PAGE_SHIFT; + + if ( nr_ranges > ARRAY_SIZE(ranges) ) + { + printk(XENLOG_WARNING + "Too many PFN ranges (%u > %zu), not attempting PFN compression\n", + nr_ranges, ARRAY_SIZE(ranges)); + return; + } + + for ( i = 0; i < nr_ranges; i++ ) + mask |= ranges[i].base_pfn | + pdx_region_mask(ranges[i].base_pfn, ranges[i].pages); /* * We skip the first MAX_ORDER bits, as we never want to compress them. @@ -184,6 +264,18 @@ void __init pfn_pdx_hole_setup(unsigned long mask) ma_top_mask = pfn_top_mask << PAGE_SHIFT; } +void __init pfn_pdx_compression_reset(void) +{ + pfn_pdx_bottom_mask = ~0UL; + ma_va_bottom_mask = ~0UL; + pfn_top_mask = 0; + ma_top_mask = 0; + pfn_hole_mask = 0; + pfn_pdx_hole_shift = 0; + + nr_ranges = 0; +} + #endif /* CONFIG_PDX_COMPRESSION */ /* diff --git a/xen/include/xen/pdx.h b/xen/include/xen/pdx.h index 8e373cac8b87..10153da98bf1 100644 --- a/xen/include/xen/pdx.h +++ b/xen/include/xen/pdx.h @@ -108,38 +108,6 @@ extern unsigned int pfn_pdx_hole_shift; extern unsigned long pfn_hole_mask; extern unsigned long pfn_top_mask, ma_top_mask; -/** - * Calculates a mask covering "moving" bits of all addresses of a region - * - * The i-th bit of the mask must be set if there's 2 different addresses - * in the region that have different j-th bits. where j >= i. - * - * e.g: - * base=0x1B00000000 - * len+base=0x1B00042000 - * - * ought to return 0x000007FFFF, which implies that every bit position - * with a zero in the mask remains unchanged in every address of the - * region. - * - * @param base Base address of the region - * @param len Size in octets of the region - * @return Mask of moving bits at the bottom of all the region addresses - */ -uint64_t pdx_region_mask(uint64_t base, uint64_t len); - -/** - * Creates the mask to start from when calculating non-compressible bits - * - * This function is intimately related to pdx_region_mask(), and together - * they are meant to calculate the mask of non-compressible bits given the - * current memory map. - * - * @param base_addr Address of the first maddr in the system - * @return An integer of the form 2^n - 1 - */ -uint64_t pdx_init_mask(uint64_t base_addr); - /** * Map pfn to its corresponding pdx * @@ -189,17 +157,6 @@ static inline paddr_t directmapoff_to_maddr(unsigned long offset) (offset & ma_va_bottom_mask)); } -/** - * Initializes global variables with information about the compressible - * range of the current memory regions. - * - * @param mask This mask is the biggest pdx_mask of every region in the - * system ORed with all base addresses of every region in the - * system. This results in a mask where every zero in a bit - * position marks a potentially compressible bit. - */ -void pfn_pdx_hole_setup(unsigned long mask); - #endif /* CONFIG_PDX_MASK_COMPRESSION */ #ifdef CONFIG_PDX_NONE @@ -220,17 +177,15 @@ static inline bool pdx_is_region_compressible(paddr_t base, return true; } -static inline uint64_t pdx_init_mask(uint64_t base_addr) +static inline void pfn_pdx_add_region(paddr_t base, paddr_t size) { - return 0; } -static inline uint64_t pdx_region_mask(uint64_t base, uint64_t len) +static inline void pfn_pdx_compression_setup(paddr_t base) { - return 0; } -static inline void pfn_pdx_hole_setup(unsigned long mask) +static inline void pfn_pdx_compression_reset(void) { } @@ -247,6 +202,28 @@ static inline void pfn_pdx_hole_setup(unsigned long mask) */ bool pdx_is_region_compressible(paddr_t base, unsigned long npages); +/** + * Register a RAM region with the PFN compression logic. + * + * @param base Start of the region in bytes. + * @param size Length of the region in bytes. + */ +void pfn_pdx_add_region(paddr_t base, paddr_t size); + +/** + * Initializes global variables with information about the compressible + * range of the current memory regions. + * + * @param base address to start compression from. + */ +void pfn_pdx_compression_setup(paddr_t base); + +/** + * Reset the global variables to it's default values, thus disabling PFN + * compression. + */ +void pfn_pdx_compression_reset(void); + #endif /* !CONFIG_PDX_NONE */ #endif /* __XEN_PDX_H__ */ -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 09:53:19 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 09:53:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070227.1433906 (Exim 4.92) (envelope-from ) id 1ujEMB-0002zW-8x; Tue, 05 Aug 2025 09:53:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070227.1433906; Tue, 05 Aug 2025 09:53:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEMB-0002zG-52; Tue, 05 Aug 2025 09:53:19 +0000 Received: by outflank-mailman (input) for mailman id 1070227; Tue, 05 Aug 2025 09:53:17 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM9-0001yh-Bl for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 09:53:17 +0000 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [2a00:1450:4864:20::329]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 028c75f3-71e2-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 11:53:16 +0200 (CEST) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-458bc3ce3beso17623665e9.1 for ; Tue, 05 Aug 2025 02:53:16 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. [92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b79c3ac115sm18611197f8f.12.2025.08.05.02.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 02:53:15 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 028c75f3-71e2-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754387596; x=1754992396; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GhNVb0ZBMkEpsnDvzYh3YmEGHHdUK0KvBkXDeBZiN3g=; b=akO85gkBD+r0K5/Y7o4s68DoH8pGUy5Tze4ruo/N6qqTfZhD+f7BjUpNpQhZ56Y05V ZJxUwTp7Bq4NsYjiQN12GmXFL99TajTUEcNzzOKJ3pgxU9huIers7PzzMAkVO3WGBrOW W/r4vADg35aUrjZYBBiAtqhiIc2wgecAckStY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754387596; x=1754992396; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GhNVb0ZBMkEpsnDvzYh3YmEGHHdUK0KvBkXDeBZiN3g=; b=EGfW684fxW0M5OpvKlH3l+yzZK51BCkD+b9iUl55qvu10e1Yfhf3Ndv/VOlXXyQAj1 nLoaqhrJh49qe4GV9khvG6JzDKo+FC+seHz7gshZ9vNjg1ET0zQvUB8y59cASjSWJLM8 x/QCVVNA21f7yos3ntPr88LxYIHsY6eT7KKHCPQtfNjjanMvJbzA+n8lUEJvtHgW3W2t 3k3Xh7vWjq/myEqIoecw8XhUFev9IijmfNGeZWmmK/UFyOnO0UlWwqUmR0y8XNtwWL7o d9OWCiD6O7Kkgy6OlvypXnsTN7jLPDWE2K8iDyoYoKmbX0oUaaZT8W6Y0r+tRv7JNHsO OKFQ== X-Gm-Message-State: AOJu0YxJ+r+/+AQhRTN7b3ngXZ175xiSSSIUh90y+PRq4+CW2bq7d4Kg YqpNQSc/ZdO1gR+2ij/Hgp0xAMeAxEbisY5p8G35QLqavXjAJz4mQ3ai5fhv7MiCikmR05ugfdy Ou91M X-Gm-Gg: ASbGncsd7g8Sj61aEk9+o5PiqRI7aoiW2znZGTjpS1GA6qaTQGT7/xSYMVxrHsM8WrR oh3lamArNWax1+8TTlxPdLkvBSG41x0v8qQX0Iff6+Qo9e1BZOW8fl+W+i7ymI5S0eEiR3pu5wW Net4dMJZkxVrd0m/7S7Ct5NRE+HYnDmQZqTZBPzSJBumcvk7OvJzUaZ1qu7/npfgFHzlVsMb+WM d0vXcHSzcoSv/l09RbtYp2gv6n8UHmMGlEknFibJwzOMCXdZig8+eVKDnlH7iORTjPBHc/gJbQ7 8ygFeZ4V02RsYLx2DXyH1w/sATmpx7S8E84rHVYPOuMT64WKSRHIedIiS2NNAJvjximoKdsMCKb oGHV0RNHtikr7uLR2ljX8h5UG80YM5NnIzb1poKylVHNZOFjbgU+d6ko/Txu1GMDjXA== X-Google-Smtp-Source: AGHT+IF8Hlz1NANF27jwxjR7WhHDaJIu9qeg8DsnUouM8UGa3gJLwXNf3/SypT85GbgbUedpf/x+lw== X-Received: by 2002:a05:600c:4752:b0:456:25aa:e9c0 with SMTP id 5b1f17b1804b1-458b69e3710mr115207405e9.14.1754387595822; Tue, 05 Aug 2025 02:53:15 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Anthony PERARD , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v4 5/8] test/pdx: add PDX compression unit tests Date: Tue, 5 Aug 2025 11:52:54 +0200 Message-ID: <20250805095257.74975-6-roger.pau@citrix.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250805095257.74975-1-roger.pau@citrix.com> References: <20250805095257.74975-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce a set of unit tests for PDX compression. The unit tests contains both real and crafted memory maps that are then compressed using the selected PDX algorithm. Note the build system for the unit tests has been done in a way to support adding new compression algorithms easily. That requires generating a new test-pdx- executable that's build with the selected PDX compression enabled. Currently the only generated executable is test-pdx-mask that tests PDX mask compression. Signed-off-by: Roger Pau Monné --- Changes since v2: - Use set -e when running the tests. - Drop stray removal of pdx.c. - Use * instead of ? for header blank space capture. - Add some more memory maps. Changes since v1: - New in this version (partially pulled out from a different patch). --- tools/tests/Makefile | 1 + tools/tests/pdx/.gitignore | 2 + tools/tests/pdx/Makefile | 49 +++++++ tools/tests/pdx/harness.h | 84 ++++++++++++ tools/tests/pdx/test-pdx.c | 267 +++++++++++++++++++++++++++++++++++++ xen/common/pdx.c | 4 + 6 files changed, 407 insertions(+) create mode 100644 tools/tests/pdx/.gitignore create mode 100644 tools/tests/pdx/Makefile create mode 100644 tools/tests/pdx/harness.h create mode 100644 tools/tests/pdx/test-pdx.c diff --git a/tools/tests/Makefile b/tools/tests/Makefile index 36928676a666..97ba2a13894d 100644 --- a/tools/tests/Makefile +++ b/tools/tests/Makefile @@ -9,6 +9,7 @@ ifneq ($(clang),y) SUBDIRS-$(CONFIG_X86) += x86_emulator endif SUBDIRS-y += xenstore +SUBDIRS-y += pdx SUBDIRS-y += rangeset SUBDIRS-y += vpci SUBDIRS-y += paging-mempool diff --git a/tools/tests/pdx/.gitignore b/tools/tests/pdx/.gitignore new file mode 100644 index 000000000000..a32c7db4de79 --- /dev/null +++ b/tools/tests/pdx/.gitignore @@ -0,0 +1,2 @@ +/pdx.h +/test-pdx-mask diff --git a/tools/tests/pdx/Makefile b/tools/tests/pdx/Makefile new file mode 100644 index 000000000000..b3734afde686 --- /dev/null +++ b/tools/tests/pdx/Makefile @@ -0,0 +1,49 @@ +XEN_ROOT=$(CURDIR)/../../.. +include $(XEN_ROOT)/tools/Rules.mk + +TARGETS := test-pdx-mask + +.PHONY: all +all: $(TARGETS) + +.PHONY: run +run: $(TARGETS) +ifeq ($(CC),$(HOSTCC)) + set -e; \ + for test in $? ; do \ + ./$$test ; \ + done +else + $(warning HOSTCC != CC, will not run test) +endif + +.PHONY: clean +clean: + $(RM) -- *.o $(TARGETS) $(DEPS_RM) pdx.h + +.PHONY: distclean +distclean: clean + $(RM) -- *~ + +.PHONY: install +install: all + $(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests + $(INSTALL_PROG) $(TARGETS) $(DESTDIR)$(LIBEXEC)/tests + +.PHONY: uninstall +uninstall: + $(RM) -- $(patsubst %,$(DESTDIR)$(LIBEXEC)/tests/%,$(TARGETS)) + +pdx.h: $(XEN_ROOT)/xen/include/xen/pdx.h + sed -E -e '/^#[[:space:]]*include/d' <$< >$@ + +CFLAGS += -D__XEN_TOOLS__ +CFLAGS += $(APPEND_CFLAGS) +CFLAGS += $(CFLAGS_xeninclude) + +test-pdx-mask: CFLAGS += -DCONFIG_PDX_MASK_COMPRESSION + +test-pdx-%: test-pdx.c pdx.h + $(CC) $(CPPFLAGS) $(CFLAGS) $(CFLAGS_$*.o) -o $@ $< $(APPEND_CFLAGS) + +-include $(DEPS_INCLUDE) diff --git a/tools/tests/pdx/harness.h b/tools/tests/pdx/harness.h new file mode 100644 index 000000000000..5bef7df650d2 --- /dev/null +++ b/tools/tests/pdx/harness.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Unit tests for PDX compression. + * + * Copyright (C) 2025 Cloud Software Group + */ + +#ifndef _TEST_HARNESS_ +#define _TEST_HARNESS_ + +#include +#include +#include +#include +#include +#include + +#include + +#define __init +#define __initdata +#define __ro_after_init +#define cf_check + +#define printk printf +#define XENLOG_INFO +#define XENLOG_DEBUG +#define XENLOG_WARNING +#define KERN_INFO + +#define BITS_PER_LONG (unsigned int)(sizeof(unsigned long) * 8) + +#define PAGE_SHIFT 12 +/* Some libcs define PAGE_SIZE in limits.h. */ +#undef PAGE_SIZE +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define MAX_ORDER 18 /* 2 * PAGETABLE_ORDER (9) */ + +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) +#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) + +#define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) +#define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) + +#define MAX_RANGES 16 +#define MAX_PFN_RANGES MAX_RANGES + +#define ASSERT assert + +#define CONFIG_DEBUG + +static inline unsigned int find_next( + const unsigned long *addr, unsigned int size, unsigned int off, bool value) +{ + unsigned int i; + + ASSERT(size <= BITS_PER_LONG); + + for ( i = off; i < size; i++ ) + if ( !!(*addr & (1UL << i)) == value ) + return i; + + return size; +} + +#define find_next_zero_bit(a, s, o) find_next(a, s, o, false) +#define find_next_bit(a, s, o) find_next(a, s, o, true) + +#define boolean_param(name, func) + +typedef uint64_t paddr_t; + +#include "pdx.h" + +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/tools/tests/pdx/test-pdx.c b/tools/tests/pdx/test-pdx.c new file mode 100644 index 000000000000..0798ccee359b --- /dev/null +++ b/tools/tests/pdx/test-pdx.c @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Unit tests for PDX compression. + * + * Copyright (C) 2025 Cloud Software Group + */ + +#include "harness.h" + +#include "../../xen/common/pdx.c" + +struct range { + /* Ranges are defined as [start, end). */ + unsigned long start, end; +}; + +static void print_ranges(const struct range *r) +{ + unsigned int i; + + printf("Ranges:\n"); + + for ( i = 0; i < MAX_RANGES; i++ ) + { + if ( !r[i].start && !r[i].end ) + break; + + printf(" %013lx-%013lx\n", r[i].start, r[i].end); + } +} + +int main(int argc, char **argv) +{ + static const struct { + struct range ranges[MAX_RANGES]; + bool compress; + } tests[] = { +#ifdef __LP64__ + /* + * Only for targets where unsigned long is 64bits, otherwise compiler + * will complain about truncation from 'long long' -> 'long' conversion. + * + * Real memory map from a 4s Intel GNR. Not compressible using PDX + * mask compression. + */ + { + .ranges = { + { .start = 0, .end = 0x80000UL }, + { .start = 0x0100000UL, .end = 0x8080000UL }, + { .start = 0x63e80000UL, .end = 0x6be80000UL }, + { .start = 0xc7e80000UL, .end = 0xcfe80000UL }, + { .start = 0x12be80000UL, .end = 0x133e80000UL }, + }, + .compress = false, + }, + /* Simple hole. */ + { + .ranges = { + { .start = 0, + .end = (1UL << MAX_ORDER) * 1 }, + { .start = (1UL << (MAX_ORDER * 2)) | 0, + .end = (1UL << (MAX_ORDER * 2)) | (1UL << MAX_ORDER) * 1 }, + }, + .compress = true, + }, + /* Simple hole, unsorted ranges. */ + { + .ranges = { + { .start = (1UL << (MAX_ORDER * 2)) | 0, + .end = (1UL << (MAX_ORDER * 2)) | (1UL << MAX_ORDER) * 1 }, + { .start = 0, + .end = (1UL << MAX_ORDER) * 1 }, + }, + .compress = true, + }, + /* PDX compression, 2 ranges covered by the lower mask. */ + { + .ranges = { + { .start = 0, + .end = (1 << MAX_ORDER) * 1 }, + { .start = (1 << MAX_ORDER) * 2, + .end = (1 << MAX_ORDER) * 3 }, + { .start = (1 << MAX_ORDER) * 20, + .end = (1 << MAX_ORDER) * 22 }, + }, + .compress = true, + }, + /* Single range not starting at 0. */ + { + .ranges = { + { .start = (1 << MAX_ORDER) * 10, + .end = (1 << MAX_ORDER) * 11 }, + }, + .compress = true, + }, + /* Resulting PDX region size leads to no compression. */ + { + .ranges = { + { .start = 0, + .end = (1 << MAX_ORDER) * 1 }, + { .start = (1 << MAX_ORDER) * 2, + .end = (1 << MAX_ORDER) * 3 }, + { .start = (1 << MAX_ORDER) * 4, + .end = (1 << MAX_ORDER) * 7 }, + { .start = (1 << MAX_ORDER) * 8, + .end = (1 << MAX_ORDER) * 12 }, + }, + .compress = false, + }, + /* AMD Versal Gen 2 ARM board. */ + { + .ranges = { + { .start = 0, .end = 0x80000UL }, + { .start = 0x800000UL, .end = 0x880000UL }, + { .start = 0x50000000UL, .end = 0x50080000UL }, + { .start = 0x60000000UL, .end = 0x60080000UL }, + { .start = 0x70000000UL, .end = 0x70080000UL }, + }, + .compress = true, + }, + /* Unsorted ranges, lower one not starting at 0. */ + { + .ranges = { + { .start = (1UL << (35 - PAGE_SHIFT)) + (1 << MAX_ORDER) * 2, + .end = (1UL << (35 - PAGE_SHIFT)) + (1 << MAX_ORDER) * 3 }, + { .start = (1 << MAX_ORDER) * 2, + .end = (1 << MAX_ORDER) * 3 }, + }, + .compress = true, + }, + /* Two ranges with the same high bit set. */ + { + .ranges = { + { .start = (1UL << (51 - PAGE_SHIFT)) + (1 << MAX_ORDER) * 0, + .end = (1UL << (51 - PAGE_SHIFT)) + (1 << MAX_ORDER) * 1 }, + { .start = (1UL << (51 - PAGE_SHIFT)) + (1 << MAX_ORDER) * 3, + .end = (1UL << (51 - PAGE_SHIFT)) + (1 << MAX_ORDER) * 4 }, + }, + .compress = true, + }, +#endif + /* AMD Naples Epyc 7281 2 sockets, 8 NUMA nodes. */ + { + .ranges = { + { .start = 0, .end = 0xa0UL }, + { .start = 0x100UL, .end = 0xb0000UL }, + { .start = 0x100000UL, .end = 0x430000UL }, + { .start = 0x430000UL, .end = 0x830000UL }, + { .start = 0x830000UL, .end = 0xc30000UL }, + { .start = 0xc30000UL, .end = 0x1030000UL }, + { .start = 0x1030000UL, .end = 0x1430000UL }, + { .start = 0x1430000UL, .end = 0x1830000UL }, + { .start = 0x1830000UL, .end = 0x1c30000UL }, + { .start = 0x1c30000UL, .end = 0x2030000UL }, + }, + .compress = false, + }, + /* 2-node 2GB per-node QEMU layout. */ + { + .ranges = { + { .start = 0, .end = 0x80000UL }, + { .start = 0x100000UL, .end = 0x180000UL }, + }, + .compress = true, + }, + /* Not compressible, smaller than MAX_ORDER. */ + { + .ranges = { + { .start = 0, .end = 1 }, + { .start = 0x100UL, .end = 0x101UL }, + }, + .compress = false, + }, + /* Compressible, requires adjusting size to (1 << MAX_ORDER). */ + { + .ranges = { + { .start = 0, .end = 1 }, + { .start = 0x100000UL, .end = 0x100001UL }, + }, + .compress = true, + }, + /* 2s Intel CLX with contiguous ranges, no compression. */ + { + .ranges = { + { .start = 0 , .end = 0x180000UL }, + { .start = 0x180000UL, .end = 0x3040000UL }, + }, + .compress = false, + }, + }; + int ret_code = EXIT_SUCCESS; + + for ( unsigned int i = 0 ; i < ARRAY_SIZE(tests); i++ ) + { + unsigned int j; + + pfn_pdx_compression_reset(); + + for ( j = 0; j < ARRAY_SIZE(tests[i].ranges); j++ ) + { + unsigned long size = tests[i].ranges[j].end - + tests[i].ranges[j].start; + + if ( !tests[i].ranges[j].start && !tests[i].ranges[j].end ) + break; + + pfn_pdx_add_region(tests[i].ranges[j].start << PAGE_SHIFT, + size << PAGE_SHIFT); + } + + if ( pfn_pdx_compression_setup(0) != tests[i].compress ) + { + printf("PFN compression diverge, expected %scompressible\n", + tests[i].compress ? "" : "un"); + print_ranges(tests[i].ranges); + + ret_code = EXIT_FAILURE; + continue; + } + + if ( !tests[i].compress ) + continue; + + for ( j = 0; j < ARRAY_SIZE(tests[i].ranges); j++ ) + { + unsigned long start = tests[i].ranges[j].start; + unsigned long end = tests[i].ranges[j].end; + + if ( !start && !end ) + break; + + if ( !pdx_is_region_compressible(start << PAGE_SHIFT, 1) || + !pdx_is_region_compressible((end - 1) << PAGE_SHIFT, 1) ) + { + printf( + "PFN compression invalid, pages %#lx and %#lx should be compressible\n", + start, end - 1); + print_ranges(tests[i].ranges); + ret_code = EXIT_FAILURE; + } + + if ( start != pdx_to_pfn(pfn_to_pdx(start)) || + end - 1 != pdx_to_pfn(pfn_to_pdx(end - 1)) ) + { + printf("Compression is not bi-directional:\n"); + printf(" PFN %#lx -> PDX %#lx -> PFN %#lx\n", + start, pfn_to_pdx(start), pdx_to_pfn(pfn_to_pdx(start))); + printf(" PFN %#lx -> PDX %#lx -> PFN %#lx\n", + end - 1, pfn_to_pdx(end - 1), + pdx_to_pfn(pfn_to_pdx(end - 1))); + print_ranges(tests[i].ranges); + ret_code = EXIT_FAILURE; + } + } + } + + return ret_code; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/common/pdx.c b/xen/common/pdx.c index c9ec86729151..cd8a9e75a836 100644 --- a/xen/common/pdx.c +++ b/xen/common/pdx.c @@ -15,6 +15,8 @@ * along with this program; If not, see . */ +/* Trim content when built for the test harness. */ +#ifdef __XEN__ #include #include #include @@ -57,6 +59,8 @@ void set_pdx_range(unsigned long smfn, unsigned long emfn) __set_bit(idx, pdx_group_valid); } +#endif /* __XEN__ */ + #ifndef CONFIG_PDX_NONE #ifdef CONFIG_X86 -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 09:53:19 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 09:53:19 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070228.1433910 (Exim 4.92) (envelope-from ) id 1ujEMB-000323-IN; Tue, 05 Aug 2025 09:53:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070228.1433910; Tue, 05 Aug 2025 09:53:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEMB-00031U-DS; Tue, 05 Aug 2025 09:53:19 +0000 Received: by outflank-mailman (input) for mailman id 1070228; Tue, 05 Aug 2025 09:53:17 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEM9-00026G-RI for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 09:53:17 +0000 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [2a00:1450:4864:20::42d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 02297962-71e2-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 11:53:16 +0200 (CEST) Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3b7886bee77so4477966f8f.0 for ; Tue, 05 Aug 2025 02:53:16 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. [92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b79c3b95f4sm18447847f8f.23.2025.08.05.02.53.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 02:53:14 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 02297962-71e2-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754387595; x=1754992395; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f1xBFAQp2tU3X5eYxoTRxXwfOAwjqwHWw59TnMhPZ9E=; b=c7MBeCHiCF/1qUpO+iiwYHbrHY9wcB+QuR2xazxnaFp4qjTLqPTR2LtDv1utuNCBgH mLqLd13md5+PXbvXvf5bT98cPORVCM3tjny5EmoK7y9f5IzxPWFN8J+NOpjGRt48AAWZ DZOJZltmaspumcZLHnl0fAzNrQTVbm/IDn6cQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754387595; x=1754992395; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f1xBFAQp2tU3X5eYxoTRxXwfOAwjqwHWw59TnMhPZ9E=; b=GLtiPxzGsu4E6tKIYRXwTdjyD5BpFILq3EvgkcOKkYbldps8Dr4O7AtanZ63rFjK1E EKnoV+X2kCLy3UIOwma26MjqkJgomBEpcJct1OpG2ic85e005oc+1Cb/6BJO1vH2dcYn IDmPvDXFZ1UsAFQTFrLzNJE4ZNTAwn8nkKe23cu8CVvtG4lscqQT4fGrgRKGZ53HA38A TCTAEVEaUQX8ofqL+aX5KRDEelW8NVvdgfmOY3bl1ycKHNlRNPDtF/8Qqxj8HxkgMG9v xy+O7z5ctFbyaO1ZPZ0hqo56XyyZVHCJvGatEz6uCoJoGKVdd9LRiEU3il4+EbE1af+F mcKg== X-Gm-Message-State: AOJu0YzdMR7yG4bRWb5amUVeQOkD7ISxBhBgMTC6gEYD2JdSebsEUj08 3c1EzmdvAau7dEurca9jkEAViWDtpu7yx6eIyGLvrPc4YC2j9zprL9a4jJ3JKpz0pPGXs6N9UjC 8nzNq X-Gm-Gg: ASbGncvzxsNC7HZPe1VJkJ5G1Ny1JYdVfnePHfFmxd9HEr0XETfY/v33Y4swDQtErJp OBca8ZsUaCYKRWbEJAbt1rZTjI/WUOTJlR6uxjsQO4fc7aejhN5Z/DqJcXCpsbW2sXHl/lCf5FB qiUxjVYqRmuDCvYcLJz3oGu52LlleCE0xz9AN+/ZTWJnXrw5hX9DotlOlV9n6aEmI1v/Cj1NIF+ rOjVJtwwiFM8ntV9uVi26C3IEcrcX8yxXrUiG6QMK9rFwRk74hsuCYrpYq+RWun27H5gl/GIDoi nySQEaSo4ic+EDZj4XDnsblvuQnQz1azqu9HS8OUZgLdBt2BeBRSZtGHzvRKI7kGVPboLmlbk99 zxUFQLSZVvPeO1P/JezYC5sO5805y6/cVl+UhZ2em1l5iN0qTskJHcOwnEIWHlT5idg== X-Google-Smtp-Source: AGHT+IFHLgGTaQ6E5u7Plz8Q4Qef8ivTkL1ylGSdq7BstwwYvvUspsHFDN/BNElPxIzFK+sVHrumXg== X-Received: by 2002:a5d:588a:0:b0:3b7:e3c3:fbb6 with SMTP id ffacd0b85a97d-3b8d94ba9aemr9316236f8f.31.1754387594710; Tue, 05 Aug 2025 02:53:14 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Jan Beulich , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini Subject: [PATCH v4 4/8] pdx: allow per-arch optimization of PDX conversion helpers Date: Tue, 5 Aug 2025 11:52:53 +0200 Message-ID: <20250805095257.74975-5-roger.pau@citrix.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250805095257.74975-1-roger.pau@citrix.com> References: <20250805095257.74975-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are four performance critical PDX conversion helpers that do the PFN to/from PDX and the physical addresses to/from directmap offsets translations. In the absence of an active PDX compression, those functions would still do the calculations needed, just to return the same input value as no translation is in place and hence PFN and PDX spaces are identity mapped. To reduce the overhead of having to do the pointless calculations allow architectures to implement the translation helpers in a per-arch header. Rename the existing conversion functions to add a trailing _xlate suffix, so that the per-arch headers can define the non suffixed versions. Currently only x86 implements meaningful custom handlers to short circuit the translation when not active, using asm goto. Other architectures use generic macros that map the non-xlate to the xlate variants to keep the previous behavior. Signed-off-by: Roger Pau Monné --- Changes since v3: - Use has_include. Changes since v2: - Consume the skip label as parameter in the PDX optimize macro. Changes since v1: - Pull return out of OPTIMIZE_PDX macro. - undef OPTIMIZE_PDX. --- Would it make sense to move the x86 implementation to the common pdx.h header and let architectures define PDX_ASM_GOTO_SKIP instead? --- xen/arch/x86/include/asm/cpufeatures.h | 1 + xen/arch/x86/include/asm/pdx.h | 71 ++++++++++++++++++++++++++ xen/arch/x86/srat.c | 6 ++- xen/common/pdx.c | 10 ++-- xen/include/xen/pdx.h | 29 ++++++++--- 5 files changed, 106 insertions(+), 11 deletions(-) create mode 100644 xen/arch/x86/include/asm/pdx.h diff --git a/xen/arch/x86/include/asm/cpufeatures.h b/xen/arch/x86/include/asm/cpufeatures.h index bc108c3819e8..71308d9dafc8 100644 --- a/xen/arch/x86/include/asm/cpufeatures.h +++ b/xen/arch/x86/include/asm/cpufeatures.h @@ -42,6 +42,7 @@ XEN_CPUFEATURE(XEN_IBT, X86_SYNTH(27)) /* Xen uses CET Indirect Branch XEN_CPUFEATURE(IBPB_ENTRY_PV, X86_SYNTH(28)) /* MSR_PRED_CMD used by Xen for PV */ XEN_CPUFEATURE(IBPB_ENTRY_HVM, X86_SYNTH(29)) /* MSR_PRED_CMD used by Xen for HVM */ XEN_CPUFEATURE(USE_VMCALL, X86_SYNTH(30)) /* Use VMCALL instead of VMMCALL */ +XEN_CPUFEATURE(PDX_COMPRESSION, X86_SYNTH(31)) /* PDX compression */ /* Bug words follow the synthetic words. */ #define X86_NR_BUG 1 diff --git a/xen/arch/x86/include/asm/pdx.h b/xen/arch/x86/include/asm/pdx.h new file mode 100644 index 000000000000..6be7e1185eb1 --- /dev/null +++ b/xen/arch/x86/include/asm/pdx.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef X86_PDX_H +#define X86_PDX_H + +#include + +/* + * Introduce a macro to avoid repeating the same asm goto block in each helper. + * Note the macro is strictly tied to the code in the helpers. + */ +#define PDX_ASM_GOTO(label) \ + asm_inline goto ( \ + ALTERNATIVE( \ + "", \ + "jmp %l0", \ + ALT_NOT(X86_FEATURE_PDX_COMPRESSION)) \ + : : : : label ) + +static inline unsigned long pfn_to_pdx(unsigned long pfn) +{ + PDX_ASM_GOTO(skip); + + return pfn_to_pdx_xlate(pfn); + + skip: + return pfn; +} + +static inline unsigned long pdx_to_pfn(unsigned long pdx) +{ + PDX_ASM_GOTO(skip); + + return pdx_to_pfn_xlate(pdx); + + skip: + return pdx; +} + +static inline unsigned long maddr_to_directmapoff(paddr_t ma) +{ + PDX_ASM_GOTO(skip); + + return maddr_to_directmapoff_xlate(ma); + + skip: + return ma; +} + +static inline paddr_t directmapoff_to_maddr(unsigned long offset) +{ + PDX_ASM_GOTO(skip); + + return directmapoff_to_maddr_xlate(offset); + + skip: + return offset; +} + +#undef PDX_ASM_GOTO_SKIP + +#endif /* X86_PDX_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/x86/srat.c b/xen/arch/x86/srat.c index 747607439fb4..42ccb0c0f3ae 100644 --- a/xen/arch/x86/srat.c +++ b/xen/arch/x86/srat.c @@ -298,7 +298,8 @@ void __init srat_parse_regions(paddr_t addr) acpi_table_parse_srat(ACPI_SRAT_TYPE_MEMORY_AFFINITY, srat_parse_region, 0); - pfn_pdx_compression_setup(addr); + if (!pfn_pdx_compression_setup(addr)) + return; /* Ensure all RAM ranges in the e820 are covered. */ for (i = 0; i < e820.nr_map; i++) { @@ -318,6 +319,9 @@ void __init srat_parse_regions(paddr_t addr) return; } } + + /* If we got this far compression is working as expected. */ + setup_force_cpu_cap(X86_FEATURE_PDX_COMPRESSION); } unsigned int numa_node_to_arch_nid(nodeid_t n) diff --git a/xen/common/pdx.c b/xen/common/pdx.c index f4a3dcf6cb60..c9ec86729151 100644 --- a/xen/common/pdx.c +++ b/xen/common/pdx.c @@ -215,7 +215,7 @@ static uint64_t __init pdx_init_mask(uint64_t base_addr) (uint64_t)1 << (MAX_ORDER + PAGE_SHIFT)) - 1); } -void __init pfn_pdx_compression_setup(paddr_t base) +bool __init pfn_pdx_compression_setup(paddr_t base) { unsigned int i, j, bottom_shift = 0, hole_shift = 0; unsigned long mask = pdx_init_mask(base) >> PAGE_SHIFT; @@ -224,7 +224,7 @@ void __init pfn_pdx_compression_setup(paddr_t base) { printk(XENLOG_DEBUG "PFN compression disabled%s\n", pdx_compress ? ": no ranges provided" : ""); - return; + return false; } if ( nr_ranges > ARRAY_SIZE(ranges) ) @@ -232,7 +232,7 @@ void __init pfn_pdx_compression_setup(paddr_t base) printk(XENLOG_WARNING "Too many PFN ranges (%u > %zu), not attempting PFN compression\n", nr_ranges, ARRAY_SIZE(ranges)); - return; + return false; } for ( i = 0; i < nr_ranges; i++ ) @@ -263,7 +263,7 @@ void __init pfn_pdx_compression_setup(paddr_t base) } } if ( !hole_shift ) - return; + return false; printk(KERN_INFO "PFN compression on bits %u...%u\n", bottom_shift, bottom_shift + hole_shift - 1); @@ -274,6 +274,8 @@ void __init pfn_pdx_compression_setup(paddr_t base) pfn_hole_mask = ((1UL << hole_shift) - 1) << bottom_shift; pfn_top_mask = ~(pfn_pdx_bottom_mask | pfn_hole_mask); ma_top_mask = pfn_top_mask << PAGE_SHIFT; + + return true; } void __init pfn_pdx_compression_reset(void) diff --git a/xen/include/xen/pdx.h b/xen/include/xen/pdx.h index 10153da98bf1..425d45e9f08e 100644 --- a/xen/include/xen/pdx.h +++ b/xen/include/xen/pdx.h @@ -114,7 +114,7 @@ extern unsigned long pfn_top_mask, ma_top_mask; * @param pfn Frame number * @return Obtained pdx after compressing the pfn */ -static inline unsigned long pfn_to_pdx(unsigned long pfn) +static inline unsigned long pfn_to_pdx_xlate(unsigned long pfn) { return (pfn & pfn_pdx_bottom_mask) | ((pfn & pfn_top_mask) >> pfn_pdx_hole_shift); @@ -126,7 +126,7 @@ static inline unsigned long pfn_to_pdx(unsigned long pfn) * @param pdx Page index * @return Obtained pfn after decompressing the pdx */ -static inline unsigned long pdx_to_pfn(unsigned long pdx) +static inline unsigned long pdx_to_pfn_xlate(unsigned long pdx) { return (pdx & pfn_pdx_bottom_mask) | ((pdx << pfn_pdx_hole_shift) & pfn_top_mask); @@ -139,7 +139,7 @@ static inline unsigned long pdx_to_pfn(unsigned long pdx) * @return Offset on the direct map where that * machine address can be accessed */ -static inline unsigned long maddr_to_directmapoff(paddr_t ma) +static inline unsigned long maddr_to_directmapoff_xlate(paddr_t ma) { return (((ma & ma_top_mask) >> pfn_pdx_hole_shift) | (ma & ma_va_bottom_mask)); @@ -151,7 +151,7 @@ static inline unsigned long maddr_to_directmapoff(paddr_t ma) * @param offset Offset into the direct map * @return Corresponding machine address of that virtual location */ -static inline paddr_t directmapoff_to_maddr(unsigned long offset) +static inline paddr_t directmapoff_to_maddr_xlate(unsigned long offset) { return ((((paddr_t)offset << pfn_pdx_hole_shift) & ma_top_mask) | (offset & ma_va_bottom_mask)); @@ -181,8 +181,9 @@ static inline void pfn_pdx_add_region(paddr_t base, paddr_t size) { } -static inline void pfn_pdx_compression_setup(paddr_t base) +static inline bool pfn_pdx_compression_setup(paddr_t base) { + return false; } static inline void pfn_pdx_compression_reset(void) @@ -191,6 +192,21 @@ static inline void pfn_pdx_compression_reset(void) #else /* !CONFIG_PDX_NONE */ +/* + * Allow each architecture to define its (possibly optimized) versions of the + * translation functions. + * + * Do not use _xlate suffixed functions, always use the non _xlate variants. + */ +#if __has_include() +# include +#else +# define pdx_to_pfn pdx_to_pfn_xlate +# define pfn_to_pdx pfn_to_pdx_xlate +# define maddr_to_directmapoff maddr_to_directmapoff_xlate +# define directmapoff_to_maddr directmapoff_to_maddr_xlate +#endif + /* Shared functions implemented by all PDX compressions. */ /** @@ -215,8 +231,9 @@ void pfn_pdx_add_region(paddr_t base, paddr_t size); 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No functional change intended. Signed-off-by: Roger Pau Monné Acked-by: Jan Beulich --- git is not very helpful when generating the diff here, and it ends up moving everything around the functions instead of the functions themselves. --- xen/common/pdx.c | 118 +++++++++++++++++++++++------------------------ 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/xen/common/pdx.c b/xen/common/pdx.c index cd8a9e75a836..9e6b36086fbd 100644 --- a/xen/common/pdx.c +++ b/xen/common/pdx.c @@ -101,59 +101,6 @@ void __init pfn_pdx_add_region(paddr_t base, paddr_t size) ranges[nr_ranges++].pages = PFN_UP(base + size) - PFN_DOWN(base); } -#endif /* !CONFIG_PDX_NONE */ - -#ifdef CONFIG_PDX_MASK_COMPRESSION - -/* - * Diagram to make sense of the following variables. The masks and shifts - * are done on mfn values in order to convert to/from pdx: - * - * pfn_hole_mask - * pfn_pdx_hole_shift (mask bitsize) - * | - * |---------| - * | | - * V V - * -------------------------- - * |HHHHHHH|000000000|LLLLLL| <--- mfn - * -------------------------- - * ^ ^ ^ ^ - * | | |------| - * | | | - * | | pfn_pdx_bottom_mask - * | | - * |-------| - * | - * pfn_top_mask - * - * ma_{top,va_bottom}_mask is simply a shifted pfn_{top,pdx_bottom}_mask, - * where ma_top_mask has zeroes shifted in while ma_va_bottom_mask has - * ones. - */ - -/** Mask for the lower non-compressible bits of an mfn */ -unsigned long __ro_after_init pfn_pdx_bottom_mask = ~0UL; - -/** Mask for the lower non-compressible bits of an maddr or vaddr */ -unsigned long __ro_after_init ma_va_bottom_mask = ~0UL; - -/** Mask for the higher non-compressible bits of an mfn */ -unsigned long __ro_after_init pfn_top_mask = 0; - -/** Mask for the higher non-compressible bits of an maddr or vaddr */ -unsigned long __ro_after_init ma_top_mask = 0; - -/** - * Mask for a pdx compression bit slice. - * - * Invariant: valid(mfn) implies (mfn & pfn_hole_mask) == 0 - */ -unsigned long __ro_after_init pfn_hole_mask = 0; - -/** Number of bits of the "compressible" bit slice of an mfn */ -unsigned int __ro_after_init pfn_pdx_hole_shift = 0; - /* Sets all bits from the most-significant 1-bit down to the LSB */ static uint64_t fill_mask(uint64_t mask) { @@ -196,12 +143,6 @@ static uint64_t pdx_region_mask(uint64_t base, uint64_t len) return fill_mask(base ^ (base + len - 1)); } -bool pdx_is_region_compressible(paddr_t base, unsigned long npages) -{ - return !(paddr_to_pfn(base) & pfn_hole_mask) && - !(pdx_region_mask(base, npages * PAGE_SIZE) & ~ma_va_bottom_mask); -} - /** * Creates the mask to start from when calculating non-compressible bits * @@ -219,6 +160,65 @@ static uint64_t __init pdx_init_mask(uint64_t base_addr) (uint64_t)1 << (MAX_ORDER + PAGE_SHIFT)) - 1); } +#endif /* !CONFIG_PDX_NONE */ + +#ifdef CONFIG_PDX_MASK_COMPRESSION + +/* + * Diagram to make sense of the following variables. The masks and shifts + * are done on mfn values in order to convert to/from pdx: + * + * pfn_hole_mask + * pfn_pdx_hole_shift (mask bitsize) + * | + * |---------| + * | | + * V V + * -------------------------- + * |HHHHHHH|000000000|LLLLLL| <--- mfn + * -------------------------- + * ^ ^ ^ ^ + * | | |------| + * | | | + * | | pfn_pdx_bottom_mask + * | | + * |-------| + * | + * pfn_top_mask + * + * ma_{top,va_bottom}_mask is simply a shifted pfn_{top,pdx_bottom}_mask, + * where ma_top_mask has zeroes shifted in while ma_va_bottom_mask has + * ones. + */ + +/** Mask for the lower non-compressible bits of an mfn */ +unsigned long __ro_after_init pfn_pdx_bottom_mask = ~0UL; + +/** Mask for the lower non-compressible bits of an maddr or vaddr */ +unsigned long __ro_after_init ma_va_bottom_mask = ~0UL; + +/** Mask for the higher non-compressible bits of an mfn */ +unsigned long __ro_after_init pfn_top_mask = 0; + +/** Mask for the higher non-compressible bits of an maddr or vaddr */ +unsigned long __ro_after_init ma_top_mask = 0; + +/** + * Mask for a pdx compression bit slice. + * + * Invariant: valid(mfn) implies (mfn & pfn_hole_mask) == 0 + */ +unsigned long __ro_after_init pfn_hole_mask = 0; + +/** Number of bits of the "compressible" bit slice of an mfn */ +unsigned int __ro_after_init pfn_pdx_hole_shift = 0; + +bool pdx_is_region_compressible(paddr_t base, unsigned long npages) +{ + return !(paddr_to_pfn(base) & pfn_hole_mask) && + !(pdx_region_mask(base, npages * PAGE_SIZE) & ~ma_va_bottom_mask); +} + bool __init pfn_pdx_compression_setup(paddr_t base) { unsigned int i, j, bottom_shift = 0, hole_shift = 0; -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 09:53:23 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 09:53:23 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070232.1433936 (Exim 4.92) (envelope-from ) id 1ujEMF-0003rF-Ia; Tue, 05 Aug 2025 09:53:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070232.1433936; Tue, 05 Aug 2025 09:53:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEMF-0003qd-E4; Tue, 05 Aug 2025 09:53:23 +0000 Received: by outflank-mailman (input) for mailman id 1070232; Tue, 05 Aug 2025 09:53:21 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEMD-00026G-Gp for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 09:53:21 +0000 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [2a00:1450:4864:20::435]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 0434faa8-71e2-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 11:53:19 +0200 (CEST) Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3b7825e2775so4558658f8f.2 for ; Tue, 05 Aug 2025 02:53:19 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. [92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b79c3c4d02sm18194279f8f.33.2025.08.05.02.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 02:53:18 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0434faa8-71e2-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754387599; x=1754992399; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dkHB+363YxhGHGsW0WbfTknTo2Qh5BFaLJhNwQ63/RY=; b=e2GS6ptta+XjgaIwe0WSAhoZfF4F33zaRzFnROFi2PGW6DwqJXHDn9LTvqYR8PYlj4 Jg+6gl8sg6kHaMpjrF4Fs+pGOV9HivGy20k4t7ig+LlJ0gJ1loiFKDiduhVBmMnfGlnu N6h6qrGQSR9kbKSa2UGQqlscifSuxWrEUcbPE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754387599; x=1754992399; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dkHB+363YxhGHGsW0WbfTknTo2Qh5BFaLJhNwQ63/RY=; b=k9QNHk9nhkIrGdrWja2myzeBtJ+ob0QFUNHwvTgjYs5Ux1kD2FFFDG9a6PCL1vZmYX UTnR+2+/CxZEohPKSe9cpNQxrzE6zeZ5napyiafkJknNoPdFSITF7G76wu4oY7vYK0Rc g/q6t1StZW/Cixvs9fKjB01ZpfcRrdVqKnM1xjajWwdq5H8Xf0RVPb6mzZ7y4BCvRvvq rUtExtKBfnYvcrTeCVy3X0+YGAQKAgtiQxUpmLVeJLLPcm1uhSPkGibCPAUtsjvI4l0b 53lIfflluLktFLE9DrToCapIALDtMqpgYitfp3YWqLs2RKUvs+M7KvKljJ4AF8Q3nZrC PIUA== X-Gm-Message-State: AOJu0Yy3sxYmfIYilSuHUQgOERvjN25PKTygW4EnI2i1THNhYOUXNBts G9b4G5OSUWWlWA6Q/76IAN4WJpCDGWYDgP41EN51qGsiRyFW3Ra5+iM/ADISd9cwfWEpm9iY+AM h30pA X-Gm-Gg: ASbGncvmnxlUvVWK0dKfIKQTk7V5NR/bnxYtSQctgZZs9yRHmpVWbZ67hNdXLvsLdCB LCfT+bZ6CAFZxk5U/b3GidGMk4/7SQmam7oUa4qMb4KLM6UD5Y7Z7au0cOVok7QHSmm0CfaZad5 CtIT1KwT9ADE193i/gyPVPTAj7HYl3cv6iB4nU6eFDAA76L2gFoEXyqgvnRXq/qBHExQTfTacAo lod4vDBSufxV6KvhXEwFiY4escPnUj7WEGvtwdhGeE/K+W53uVb4ENyXzCBbDPz+/v7jm2FGANR Rcm3Vn4nwVHOgCctoiZPbCwzbIRtlYdGEeKwsIze0HT0g3pL5TsM96oSvQhEmRq6ek7PqFfNPBb c5CuyV3OB4b+mNQnxkWU0/V0Ng0TkdBblOT39yP/OdhJ0o8gT1D5SXevnwMvi4vNJUw== X-Google-Smtp-Source: AGHT+IErhUju3M5UYg5smm6FdBrFeXFJHpWvobhJlu/JUk/uNlqrhtdZJmPqgM3IR95GIBDLPmU7Lg== X-Received: by 2002:a05:6000:2007:b0:3b7:8b64:3107 with SMTP id ffacd0b85a97d-3b8d948647fmr9664503f8f.26.1754387598519; Tue, 05 Aug 2025 02:53:18 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Oleksii Kurochko , Community Manager , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v4 7/8] pdx: introduce a new compression algorithm based on region offsets Date: Tue, 5 Aug 2025 11:52:56 +0200 Message-ID: <20250805095257.74975-8-roger.pau@citrix.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250805095257.74975-1-roger.pau@citrix.com> References: <20250805095257.74975-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the appearance of Intel Sierra Forest and Granite Rapids it's now possible to get a production x86 host with the following memory map: SRAT: Node 0 PXM 0 [0000000000000000, 000000007fffffff] SRAT: Node 0 PXM 0 [0000000100000000, 000000807fffffff] SRAT: Node 1 PXM 1 [0000063e80000000, 000006be7fffffff] SRAT: Node 2 PXM 2 [00000c7e80000000, 00000cfe7fffffff] SRAT: Node 3 PXM 3 [000012be80000000, 0000133e7fffffff] This is from a four socket Granite Rapids system, with each node having 512GB of memory. The total amount of RAM on the system is 2TB, but without enabling CONFIG_BIGMEM the last range is not accessible, as it's above the 16TB boundary covered by the frame table. Sierra Forest and Granite Rapids are socket compatible, however Sierra Forest only supports 2 socket configurations, while Granite Rapids can go up to 8 sockets. Note that while the memory map is very sparse, it couldn't be compressed using the current PDX_MASK compression algorithm, which relies on all ranges having a shared zeroed region of bits that can be removed. The memory map presented above has the property of all regions being similarly spaced between each other, and all having also a similar size. Use a lookup table to store the offsets to translate from/to PFN and PDX spaces. Such table is indexed based on the input PFN or PDX to translated. The example PFN layout about would get compressed using the following: PFN compression using PFN lookup table shift 29 and PDX region size 0x10000000 range 0 [0000000000000, 0x0000807ffff] PFN IDX 0 : 0000000000000 range 1 [0x00063e80000, 0x0006be7ffff] PFN IDX 3 : 0x00053e80000 range 2 [0x000c7e80000, 0x000cfe7ffff] PFN IDX 6 : 0x000a7e80000 range 3 [0x0012be80000, 0x00133e7ffff] PFN IDX 9 : 0x000fbe80000 Note how the tow ranges belonging to node 0 get merged into a single PDX region by the compression algorithm. The default size of lookup tables currently set in Kconfig is 64 entries, and the example memory map consumes 10 entries. Such memory map is from a 4 socket Granite Rapids host, which in theory supports up to 8 sockets according to Intel documentation. Assuming the layout of a 8 socket system is similar to the 4 socket one, it would require 21 lookup table entries to support it, way below the current default of 64 entries. The valid range of lookup table size is currently restricted from 1 to 512 elements in Kconfig. An extra array is used to keep track of the base PFN for each translated range. Non used slots are set to ~0UL, so that in mfn_valid() the mfn < base check always fails, thus reporting the mfn as invalid. Introduce __init_or_pdx_mask and use it on some shared functions between PDX mask and offset compression, as otherwise some code becomes unreachable after boot if PDX offset compression is used. Mark the code as __init in that case, so it's pruned after boot. Signed-off-by: Roger Pau Monné --- Changes since v3: - Rename __init_or_pdx_mask. - Reorder logic in pfn_offset_sanitize_ranges() to reduce code. - Print a message if the table index is truncated from what would be required to represent all input ranges independently. - Cast size to paddr_t for pdx_init_mask() call. Changes since v2: - s/PDX_OFFSET_TLB_ORDER/PDX_OFFSET_TBL_ORDER/. - Fix changelog mention of Sapphire Rapids. - Misc fixes in the test harness. - Use SWAP() macro. - Introduce an extra table to keep the bases of the valid ranges. Changes since v1: - Use a lookup table with the offsets. - Split the adding of the test to a pre-patch. - Amend diagram to also show possible padding after compression. --- CHANGELOG.md | 3 + tools/tests/pdx/.gitignore | 1 + tools/tests/pdx/Makefile | 3 +- tools/tests/pdx/harness.h | 14 ++ tools/tests/pdx/test-pdx.c | 4 + xen/common/Kconfig | 21 ++- xen/common/pdx.c | 258 ++++++++++++++++++++++++++++++++++++- xen/include/xen/pdx.h | 87 ++++++++++++- 8 files changed, 385 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5f31ca08fe3f..f9ef893f4851 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -20,6 +20,9 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) grant table or foreign memory. ### Added + - Introduce new PDX compression algorithm to cope with Intel Sierra Forest and + Granite Rapids having sparse memory maps. + - On x86: - Option to attempt to fixup p2m page-faults on PVH dom0. - Resizable BARs is supported for PVH dom0. diff --git a/tools/tests/pdx/.gitignore b/tools/tests/pdx/.gitignore index a32c7db4de79..1202a531a7fd 100644 --- a/tools/tests/pdx/.gitignore +++ b/tools/tests/pdx/.gitignore @@ -1,2 +1,3 @@ /pdx.h /test-pdx-mask +/test-pdx-offset diff --git a/tools/tests/pdx/Makefile b/tools/tests/pdx/Makefile index b3734afde686..10b354f0cefd 100644 --- a/tools/tests/pdx/Makefile +++ b/tools/tests/pdx/Makefile @@ -1,7 +1,7 @@ XEN_ROOT=$(CURDIR)/../../.. include $(XEN_ROOT)/tools/Rules.mk -TARGETS := test-pdx-mask +TARGETS := test-pdx-mask test-pdx-offset .PHONY: all all: $(TARGETS) @@ -42,6 +42,7 @@ CFLAGS += $(APPEND_CFLAGS) CFLAGS += $(CFLAGS_xeninclude) test-pdx-mask: CFLAGS += -DCONFIG_PDX_MASK_COMPRESSION +test-pdx-offset: CFLAGS += -DCONFIG_PDX_OFFSET_COMPRESSION test-pdx-%: test-pdx.c pdx.h $(CC) $(CPPFLAGS) $(CFLAGS) $(CFLAGS_$*.o) -o $@ $< $(APPEND_CFLAGS) diff --git a/tools/tests/pdx/harness.h b/tools/tests/pdx/harness.h index 5bef7df650d2..7c1c5a246868 100644 --- a/tools/tests/pdx/harness.h +++ b/tools/tests/pdx/harness.h @@ -44,8 +44,10 @@ #define MAX_RANGES 16 #define MAX_PFN_RANGES MAX_RANGES +#define CONFIG_PDX_OFFSET_TBL_ORDER 6 #define ASSERT assert +#define ASSERT_UNREACHABLE() assert(0) #define CONFIG_DEBUG @@ -66,10 +68,22 @@ static inline unsigned int find_next( #define find_next_zero_bit(a, s, o) find_next(a, s, o, false) #define find_next_bit(a, s, o) find_next(a, s, o, true) +#define flsl(x) ((x) ? BITS_PER_LONG - __builtin_clzl(x) : 0) +#define ffsl(x) __builtin_ffsl(x) + #define boolean_param(name, func) typedef uint64_t paddr_t; +#define SWAP(a, b) \ + do { typeof(a) t_ = (a); (a) = (b); (b) = t_; } while ( 0 ) + +#define sort(elem, nr, size, cmp, swp) ({ \ + /* Consume swp() so compiler doesn't complain it's unused. */ \ + (void)swp; \ + qsort(elem, nr, size, cmp); \ +}) + #include "pdx.h" #endif diff --git a/tools/tests/pdx/test-pdx.c b/tools/tests/pdx/test-pdx.c index 0798ccee359b..eefd54c76815 100644 --- a/tools/tests/pdx/test-pdx.c +++ b/tools/tests/pdx/test-pdx.c @@ -51,7 +51,11 @@ int main(int argc, char **argv) { .start = 0xc7e80000UL, .end = 0xcfe80000UL }, { .start = 0x12be80000UL, .end = 0x133e80000UL }, }, +#ifdef CONFIG_PDX_OFFSET_COMPRESSION + .compress = true, +#else .compress = false, +#endif }, /* Simple hole. */ { diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 8dad0c923a9d..76f9ce705f7a 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -59,7 +59,8 @@ config EVTCHN_FIFO choice prompt "PDX (Page inDeX) compression" - default PDX_MASK_COMPRESSION if !X86 && !RISCV + default PDX_OFFSET_COMPRESSION if X86 + default PDX_MASK_COMPRESSION if !RISCV default PDX_NONE help PDX compression is a technique designed to reduce the memory @@ -78,12 +79,30 @@ config PDX_MASK_COMPRESSION help Compression relying on all RAM addresses sharing a zeroed bit region. +config PDX_OFFSET_COMPRESSION + bool "Offset compression" + help + Compression relying on size and distance between RAM regions being + compressible using an offset lookup table. + config PDX_NONE bool "None" help No compression endchoice +config PDX_OFFSET_TBL_ORDER + int "PDX offset compression lookup table order" if EXPERT + depends on PDX_OFFSET_COMPRESSION + default 6 + range 0 9 + help + Order of the PFN to PDX and PDX to PFN translation lookup tables. + Number of table entries is calculated as 2^N. + + Size of the tables can be adjusted from 1 entry (order 0) to 512 + entries (order 9). + config ALTERNATIVE_CALL bool diff --git a/xen/common/pdx.c b/xen/common/pdx.c index 9e6b36086fbd..d29582234bfd 100644 --- a/xen/common/pdx.c +++ b/xen/common/pdx.c @@ -24,6 +24,7 @@ #include #include #include +#include /** * Maximum (non-inclusive) usable pdx. Must be @@ -40,6 +41,12 @@ bool __mfn_valid(unsigned long mfn) #ifdef CONFIG_PDX_MASK_COMPRESSION invalid |= mfn & pfn_hole_mask; +#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) +{ + unsigned long base = pfn_bases[PFN_TBL_IDX(mfn)]; + + invalid |= mfn < base || mfn >= base + pdx_region_size; +} #endif if ( unlikely(evaluate_nospec(invalid)) ) @@ -75,6 +82,13 @@ void set_pdx_range(unsigned long smfn, unsigned long emfn) # error "Missing architecture maximum number of RAM ranges" #endif +/* Some functions should be init when not using PDX mask compression. */ +#ifndef CONFIG_PDX_MASK_COMPRESSION +# define __init_or_mask_compr __init +#else +# define __init_or_mask_compr +#endif + /* Generic PFN compression helpers. */ static struct pfn_range { unsigned long base_pfn, pages; @@ -102,7 +116,7 @@ void __init pfn_pdx_add_region(paddr_t base, paddr_t size) } /* Sets all bits from the most-significant 1-bit down to the LSB */ -static uint64_t fill_mask(uint64_t mask) +static uint64_t __init_or_mask_compr fill_mask(uint64_t mask) { while (mask & (mask + 1)) mask |= mask + 1; @@ -128,7 +142,7 @@ static uint64_t fill_mask(uint64_t mask) * @param len Size in octets of the region * @return Mask of moving bits at the bottom of all the region addresses */ -static uint64_t pdx_region_mask(uint64_t base, uint64_t len) +static uint64_t __init_or_mask_compr pdx_region_mask(uint64_t base, uint64_t len) { /* * We say a bit "moves" in a range if there exist 2 addresses in that @@ -294,7 +308,245 @@ void __init pfn_pdx_compression_reset(void) nr_ranges = 0; } -#endif /* CONFIG_PDX_COMPRESSION */ +#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) /* CONFIG_PDX_MASK_COMPRESSION */ + +unsigned int __ro_after_init pfn_index_shift; +unsigned int __ro_after_init pdx_index_shift; + +unsigned long __ro_after_init pfn_pdx_lookup[CONFIG_PDX_NR_LOOKUP]; +unsigned long __ro_after_init pdx_pfn_lookup[CONFIG_PDX_NR_LOOKUP]; +unsigned long __ro_after_init pfn_bases[CONFIG_PDX_NR_LOOKUP]; +unsigned long __ro_after_init pdx_region_size = ~0UL; + +bool pdx_is_region_compressible(paddr_t base, unsigned long npages) +{ + unsigned long pfn = PFN_DOWN(base); + unsigned long pfn_base = pfn_bases[PFN_TBL_IDX(pfn)]; + + return pfn >= pfn_base && + pfn + npages <= pfn_base + pdx_region_size; +} + +static int __init cf_check cmp_node(const void *a, const void *b) +{ + const struct pfn_range *l = a; + const struct pfn_range *r = b; + + if ( l->base_pfn > r->base_pfn ) + return 1; + if ( l->base_pfn < r->base_pfn ) + return -1; + + return 0; +} + +static void __init cf_check swp_node(void *a, void *b) +{ + SWAP(a, b); +} + +static bool __init pfn_offset_sanitize_ranges(void) +{ + unsigned int i = 0; + + if ( PFN_TBL_IDX(ranges[0].base_pfn) != + PFN_TBL_IDX(ranges[0].base_pfn + ranges[0].pages - 1) ) + { + ASSERT_UNREACHABLE(); + return false; + } + + while ( i + 1 < nr_ranges ) + { + /* + * Ensure ranges [start, end] use the same offset table index. Should + * be guaranteed by the logic that calculates the pfn shift. + */ + if ( PFN_TBL_IDX(ranges[i + 1].base_pfn) != + PFN_TBL_IDX(ranges[i + 1].base_pfn + ranges[i + 1].pages - 1) ) + { + ASSERT_UNREACHABLE(); + return false; + } + + if ( PFN_TBL_IDX(ranges[i].base_pfn) != + PFN_TBL_IDX(ranges[i + 1].base_pfn) ) + { + i++; + continue; + } + + /* Merge ranges with the same table index. */ + ranges[i].pages = ranges[i + 1].base_pfn + ranges[i + 1].pages - + ranges[i].base_pfn; + memmove(&ranges[i + 1], &ranges[i + 2], + (nr_ranges - (i + 2)) * sizeof(ranges[0])); + nr_ranges--; + } + + return true; +} + +bool __init pfn_pdx_compression_setup(paddr_t base) +{ + unsigned long mask = PFN_DOWN(pdx_init_mask(base)), idx_mask = 0; + unsigned long pages = 0; + unsigned int i; + + if ( !nr_ranges ) + { + printk(XENLOG_DEBUG "PFN compression disabled%s\n", + pdx_compress ? ": no ranges provided" : ""); + return false; + } + + if ( nr_ranges > ARRAY_SIZE(ranges) ) + { + printk(XENLOG_WARNING + "Too many PFN ranges (%u > %zu), not attempting PFN compression\n", + nr_ranges, ARRAY_SIZE(ranges)); + return false; + } + + /* Sort ranges by start address. */ + sort(ranges, nr_ranges, sizeof(*ranges), cmp_node, swp_node); + + for ( i = 0; i < nr_ranges; i++ ) + { + unsigned long start = ranges[i].base_pfn; + + /* + * Align range base to MAX_ORDER. This is required so the PDX offset + * for the bits below MAX_ORDER matches the MFN offset, and pages + * greater than the minimal order can be used to populate the + * directmap. + */ + ranges[i].base_pfn = start & ~((1UL << MAX_ORDER) - 1); + ranges[i].pages = start + ranges[i].pages - ranges[i].base_pfn; + + /* + * Only merge overlapped regions now, leave adjacent regions separated. + * They would be merged later if both use the same index into the + * lookup table. + */ + if ( !i || + ranges[i].base_pfn >= + (ranges[i - 1].base_pfn + ranges[i - 1].pages) ) + { + mask |= pdx_region_mask(ranges[i].base_pfn, ranges[i].pages); + continue; + } + + ranges[i - 1].pages = ranges[i].base_pfn + ranges[i].pages - + ranges[i - 1].base_pfn; + + if ( i + 1 < nr_ranges ) + memmove(&ranges[i], &ranges[i + 1], + (nr_ranges - (i + 1)) * sizeof(ranges[0])); + else /* last range */ + mask |= pdx_region_mask(ranges[i].base_pfn, ranges[i].pages); + nr_ranges--; + i--; + } + + /* + * Populate a mask with the non-equal bits of the different ranges, do this + * to calculate the maximum PFN shift to use as the lookup table index. + */ + for ( i = 0; i < nr_ranges; i++ ) + for ( unsigned int j = 0; j < nr_ranges; j++ ) + idx_mask |= (ranges[i].base_pfn & ~mask) ^ + (ranges[j].base_pfn & ~mask); + + if ( !idx_mask ) + /* Single region case. */ + pfn_index_shift = flsl(mask); + else if ( flsl(idx_mask) - ffsl(idx_mask) < CONFIG_PDX_OFFSET_TBL_ORDER ) + /* The changed mask fits in the table index width. */ + pfn_index_shift = ffsl(idx_mask) - 1; + else + { + /* Changed mask is wider than array size, use most significant bits. */ + pfn_index_shift = flsl(idx_mask) - CONFIG_PDX_OFFSET_TBL_ORDER; + printk(XENLOG_DEBUG + "PFN compression table index truncated, requires order %u\n", + flsl(idx_mask) - ffsl(idx_mask) + 1); + } + + /* + * Ensure correctness of the calculated values, plus merge ranges if they + * use the same lookup table index. + */ + if ( !pfn_offset_sanitize_ranges() ) + { + printk(XENLOG_DEBUG "PFN compression is invalid, disabling\n"); + pfn_pdx_compression_reset(); + return false; + } + + /* + * Find the maximum PFN range size after having merged ranges with same + * index. The rounded up region size will be the base for the PDX region + * size and shift. + */ + for ( i = 0; i < nr_ranges; i++ ) + pages = max(pages, ranges[i].pages); + + /* pdx_init_mask() already takes MAX_ORDER into account. */ + mask = PFN_DOWN(pdx_init_mask((paddr_t)pages << PAGE_SHIFT)); + pdx_index_shift = flsl(mask); + + /* Avoid compression if there's no gain. */ + if ( (mask + 1) * (nr_ranges - 1) >= ranges[nr_ranges - 1].base_pfn ) + { + printk(XENLOG_DEBUG + "PFN compression yields no space gain, disabling\n"); + pfn_pdx_compression_reset(); + return false; + } + + /* + * Set all entries in the bases table to ~0 to force both mfn_valid() and + * pdx_is_region_compressible() to return false for non-handled pfns. + */ + memset(pfn_bases, ~0, sizeof(pfn_bases)); + + pdx_region_size = mask + 1; + + printk(XENLOG_INFO + "PFN compression using lookup table shift %u and region size %#lx\n", + pfn_index_shift, pdx_region_size); + + for ( i = 0; i < nr_ranges; i++ ) + { + unsigned int idx = PFN_TBL_IDX(ranges[i].base_pfn); + + pfn_pdx_lookup[idx] = ranges[i].base_pfn - (mask + 1) * i; + pdx_pfn_lookup[i] = pfn_pdx_lookup[idx]; + pfn_bases[idx] = ranges[i].base_pfn; + + printk(XENLOG_DEBUG + " range %3u [%013lx, %013lx] PFN IDX %3u : %013lx\n", + i, ranges[i].base_pfn, ranges[i].base_pfn + ranges[i].pages - 1, + idx, pfn_pdx_lookup[idx]); + } + + return true; +} + +void __init pfn_pdx_compression_reset(void) +{ + memset(pfn_pdx_lookup, 0, sizeof(pfn_pdx_lookup)); + memset(pdx_pfn_lookup, 0, sizeof(pfn_pdx_lookup)); + memset(pfn_bases, 0, sizeof(pfn_bases)); + pfn_index_shift = 0; + pdx_index_shift = 0; + pdx_region_size = ~0UL; + + nr_ranges = 0; +} + +#endif /* CONFIG_PDX_OFFSET_COMPRESSION */ /* * Local variables: diff --git a/xen/include/xen/pdx.h b/xen/include/xen/pdx.h index 425d45e9f08e..a5693b956b25 100644 --- a/xen/include/xen/pdx.h +++ b/xen/include/xen/pdx.h @@ -65,6 +65,46 @@ * This scheme also holds for multiple regions, where HHHHHHH acts as * the region identifier and LLLLLL fully contains the span of every * region involved. + * + * ## PDX offset compression + * + * Alternative compression mechanism that relies on RAM ranges having a similar + * size and offset between them: + * + * PFN address space: + * ┌────────┬──────────┬────────┬──────────┠┌────────┬──────────┠+ * │ RAM 0 │ │ RAM 1 │ │...│ RAM N │ │ + * ├────────┼──────────┼────────┴──────────┘ └────────┴──────────┘ + * │<------>│ │ + * │ size │ + * │<----------------->│ + * offset + * + * The compression reduces the holes between RAM regions: + * + * PDX address space: + * ┌────────┬───┬────────┬───┠┌─┬────────┠+ * │ RAM 0 │ │ RAM 1 │ │...│ │ RAM N │ + * ├────────┴───┼────────┴───┘ └─┴────────┘ + * │<---------->│ + * pdx region size + * + * The offsets to convert from PFN to PDX and from PDX to PFN are stored in a + * pair of lookup tables, and the index into those tables to find the offset + * for each PFN or PDX is obtained by shifting the to be translated address by + * a specific value calculated at boot: + * + * pdx = pfn - pfn_lookup_table[pfn >> pfn_shift] + * pfn = pdx + pdx_lookup_table[pdx >> pdx_shift] + * + * Note the indexes into the lookup tables are masked to avoid out of bounds + * accesses. + * + * This compression requires the PFN ranges to contain a non-equal most + * significant part that's smaller than the lookup table size, so that a valid + * shift value can be found to differentiate between PFN regions. The setup + * algorithm might merge otherwise separate PFN ranges to use the same lookup + * table entry. */ extern unsigned long max_pdx; @@ -157,7 +197,52 @@ static inline paddr_t directmapoff_to_maddr_xlate(unsigned long offset) (offset & ma_va_bottom_mask)); } -#endif /* CONFIG_PDX_MASK_COMPRESSION */ +#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) /* CONFIG_PDX_MASK_COMPRESSION */ + +#include + +#define CONFIG_PDX_NR_LOOKUP (1UL << CONFIG_PDX_OFFSET_TBL_ORDER) +#define PDX_TBL_MASK (CONFIG_PDX_NR_LOOKUP - 1) + +#define PFN_TBL_IDX(pfn) \ + (((pfn) >> pfn_index_shift) & PDX_TBL_MASK) +#define PDX_TBL_IDX(pdx) \ + (((pdx) >> pdx_index_shift) & PDX_TBL_MASK) +#define MADDR_TBL_IDX(ma) \ + (((ma) >> (pfn_index_shift + PAGE_SHIFT)) & PDX_TBL_MASK) +#define DMAPOFF_TBL_IDX(off) \ + (((off) >> (pdx_index_shift + PAGE_SHIFT)) & PDX_TBL_MASK) + +extern unsigned int pfn_index_shift; +extern unsigned int pdx_index_shift; + +extern unsigned long pfn_pdx_lookup[]; +extern unsigned long pdx_pfn_lookup[]; +extern unsigned long pfn_bases[]; +extern unsigned long pdx_region_size; + +static inline unsigned long pfn_to_pdx_xlate(unsigned long pfn) +{ + return pfn - pfn_pdx_lookup[PFN_TBL_IDX(pfn)]; +} + +static inline unsigned long pdx_to_pfn_xlate(unsigned long pdx) +{ + return pdx + pdx_pfn_lookup[PDX_TBL_IDX(pdx)]; +} + +static inline unsigned long maddr_to_directmapoff_xlate(paddr_t ma) +{ + return ma - ((paddr_t)pfn_pdx_lookup[MADDR_TBL_IDX(ma)] << PAGE_SHIFT); +} + +static inline paddr_t directmapoff_to_maddr_xlate(unsigned long offset) +{ + return offset + ((paddr_t)pdx_pfn_lookup[DMAPOFF_TBL_IDX(offset)] << + PAGE_SHIFT); +} + +#endif /* CONFIG_PDX_OFFSET_COMPRESSION */ #ifdef CONFIG_PDX_NONE -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 09:53:24 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 09:53:24 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070233.1433942 (Exim 4.92) (envelope-from ) id 1ujEMG-0003vq-4t; Tue, 05 Aug 2025 09:53:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070233.1433942; Tue, 05 Aug 2025 09:53:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEMF-0003vb-RK; Tue, 05 Aug 2025 09:53:23 +0000 Received: by outflank-mailman (input) for mailman id 1070233; Tue, 05 Aug 2025 09:53:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujEMD-0001yh-RQ for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 09:53:21 +0000 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [2a00:1450:4864:20::42d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 04c6e06f-71e2-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 11:53:20 +0200 (CEST) Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3b79bddd604so3581404f8f.0 for ; Tue, 05 Aug 2025 02:53:20 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. [92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-458b73868a4sm128606745e9.11.2025.08.05.02.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 02:53:19 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 04c6e06f-71e2-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754387600; x=1754992400; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lLIn3FF6zwDcWQpb5QcmoMzmzTKK4Qs20CfUmv+TlvU=; b=pryDO7v4wpFvoa4dmDMvxdpOKkRxHpN7dF6Okli9zEBoyuEdbvVNgrGmx3UqXUa/Kd yRBJppAOglSfAL1iPUmjcDB0c4RWIPfDY+Gn4yoUjFIGlnbDqfdR8rPM7R/WFMOQBVCn UTCSQAkvxVI608jbJ3MRArKTS4HGkFBgrF774= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754387600; x=1754992400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lLIn3FF6zwDcWQpb5QcmoMzmzTKK4Qs20CfUmv+TlvU=; b=emBCJ0WJbH/KaxcUKZ9q1mLdaCE8jKSGFnIWRDPSHM617T9sHCs40d2jcxwO2O/R1v xAy1t1EC3bCWu0tRrdVcuIn9yC+1WYEuGXeG5PlhWjn3kKGG54HpyQi0pL+ssM9dLV46 NUTnbdJr62iO1IAWT0nELhoUs865thF2DW8HKyYXfvgsWem9pGBo9gFFtRusFMhkLxhz fJlOGU9sBPca+uoTtF5vd8Ljr0BSGzhhwWktKtZWW8rwFvv9nxmzLRoD+NVBUqP+mbZW 2veCoF7hnwR7RNO62i/wIJ8hrDstQDV7j7wQi2Tbfam5oEFRaG2B1O5dNiqB8lfwyJC6 s1qw== X-Gm-Message-State: AOJu0YwFEkOdL6QiAW6AnVVOrXC0CmtFOhud2dITX1a58/SZ3DeuUeJl k1NV673DKCk2nfTf/oAwjicvDa1XlX5shU5wdPuZePr//66TZv1/07uBeYCK+falle3N4+BpKyr febNQ X-Gm-Gg: ASbGncvCMp52xD6gXqOYFWeFJkEORdbC5ZtzntVtstJHmhFgeNpg2GaYuJQyylj3IGB ZE0OW0nqAz4P7fSn0R8LeZ4/iWX1P7m3FH103Jb90WJ7ihe43LdU/ZN9SobNiWxkyPiwPm9wmHT b74b1LkT/UC80/NVbZSMdsyWioO48jikk0YCMSP3vXx+IClj5uTpoVAF7yItkPbiggTVrGA2vso zGLsO1RHhixjWaWcSASusmu+VkcliN2dGZIsSv2voWHMMTZe9ZOIsaHzpBowTascrCyos3gu5B9 HaxzaD6aKv/TTgQFeelLM4Gq0O3urIqER8DFMBQHHkp8n/yiW5vVswACRo5lM1y+PB7PIofYhIU uy8aMZXNQ/d2/M4GcmMcioVlg2RK4SkMZrAJ9sLekxBZStfzma2sOVJP63IiVD41lTzIkNIzf1s Bc X-Google-Smtp-Source: AGHT+IF1tlMb6KZwDcyrJwRY0DLZ3X9YMOMVZzsA08b0rnKgAvFdrqoP72cSYcW9kqUAOHbX8Xfvpg== X-Received: by 2002:a5d:5d0e:0:b0:3b7:9564:29be with SMTP id ffacd0b85a97d-3b8d94c1febmr8669986f8f.49.1754387599726; Tue, 05 Aug 2025 02:53:19 -0700 (PDT) From: Roger Pau Monne To: xen-devel@lists.xenproject.org Cc: Roger Pau Monne , Jan Beulich , Andrew Cooper Subject: [PATCH v4 8/8] x86/mm: adjust loop in arch_init_memory() to iterate over the PDX space Date: Tue, 5 Aug 2025 11:52:57 +0200 Message-ID: <20250805095257.74975-9-roger.pau@citrix.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250805095257.74975-1-roger.pau@citrix.com> References: <20250805095257.74975-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's a loop in arch_init_memory() that iterates over holes and non-RAM regions to possibly mark any page_info structures matching those addresses as IO. The looping there is done over the PFN space. PFNs not covered by the PDX space will always fail the mfn_valid() check, hence re-write the loop to iterate over the PDX space and avoid checking any holes that are not covered by the PDX translation. On a system with a ~6TiB hole this change together with using PDX compression reduces boot time in approximately 20 seconds. Xen boot time without the change is ~50s, with the change it's ~30s. Signed-off-by: Roger Pau Monné --- Changes since v3: - Ensure parameter to pfn_to_pdx() is always RAM. Changes since v2: - New in this version. --- xen/arch/x86/mm.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c index e7fd56c7ce90..e27dc28cfdd6 100644 --- a/xen/arch/x86/mm.c +++ b/xen/arch/x86/mm.c @@ -275,7 +275,7 @@ static void __init assign_io_page(struct page_info *page) void __init arch_init_memory(void) { - unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn; + unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn, pdx; /* * Basic guest-accessible flags: @@ -328,9 +328,20 @@ void __init arch_init_memory(void) destroy_xen_mappings((unsigned long)mfn_to_virt(iostart_pfn), (unsigned long)mfn_to_virt(ioend_pfn)); - /* Mark as I/O up to next RAM region. */ - for ( ; pfn < rstart_pfn; pfn++ ) + /* + * Mark as I/O up to next RAM region. Iterate over the PDX space to + * skip holes which would always fail the mfn_valid() check. + * + * pfn_to_pdx() requires a valid (iow: RAM) PFN to convert to PDX, + * hence provide pfn - 1, which is the tailing PFN from the last RAM + * range, or pdx 0 if the input pfn is 0. + */ + for ( pdx = pfn ? pfn_to_pdx(pfn - 1) + 1 : 0; + pdx < pfn_to_pdx(rstart_pfn); + pdx++ ) { + pfn = pdx_to_pfn(pdx); + if ( !mfn_valid(_mfn(pfn)) ) continue; -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 09:58:38 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 09:58:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070253.1433956 (Exim 4.92) (envelope-from ) id 1ujERG-0006nh-Uf; Tue, 05 Aug 2025 09:58:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070253.1433956; Tue, 05 Aug 2025 09:58:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujERG-0006na-Qz; Tue, 05 Aug 2025 09:58:34 +0000 Received: by outflank-mailman (input) for mailman id 1070253; Tue, 05 Aug 2025 09:58:33 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujERF-0006nU-7d for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 09:58:33 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id be8d30a9-71e2-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 11:58:32 +0200 (CEST) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-af934d7c932so582164166b.3 for ; Tue, 05 Aug 2025 02:58:32 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Smith" , xen-devel@lists.xenproject.org References: <20250803094738.3625269-1-Penny.Zheng@amd.com> <20250803094738.3625269-4-Penny.Zheng@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250803094738.3625269-4-Penny.Zheng@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 03.08.2025 11:47, Penny Zheng wrote: > --- a/xen/include/hypercall-defs.c > +++ b/xen/include/hypercall-defs.c > @@ -198,7 +198,9 @@ dm_op(domid_t domid, unsigned int nr_bufs, xen_dm_op_buf_t *bufs) > sysctl(xen_sysctl_t *u_sysctl) > #endif > domctl(xen_domctl_t *u_domctl) > +#if PG_log_dirty > paging_domctl_cont(xen_domctl_t *u_domctl) > +#endif > #ifndef CONFIG_PV_SHIM_EXCLUSIVE > platform_op(xen_platform_op_t *u_xenpf_op) > #endif > @@ -294,6 +296,8 @@ dm_op compat do compat do do > hypfs_op do do do do do > #endif > mca do do - - - > +#if PG_log_dirty > paging_domctl_cont do do do do - > +#endif While putting together my pair of patches, I figured that using PG_log_dirty here is wrong. asm/paging.h isn't (and cannot easily be) included, and hence the compiler will consider PG_log_dirty uniformly 0, no matter what .config holds. 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Tue, 05 Aug 2025 03:37:15 -0700 (PDT) Message-ID: <3c02593f-deae-4109-9334-0ac4376a9a9e@suse.com> Date: Tue, 5 Aug 2025 12:37:14 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 06/20] xen/riscv: add root page table allocation To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > Introduce support for allocating and initializing the root page table > required for RISC-V stage-2 address translation. > > To implement root page table allocation the following is introduced: > - p2m_get_clean_page() and p2m_alloc_root_table(), p2m_allocate_root() > helpers to allocate and zero a 16 KiB root page table, as mandated > by the RISC-V privileged specification for Sv32x4/Sv39x4/Sv48x4/Sv57x4 > modes. > - Update p2m_init() to inititialize p2m_root_order. > - Add maddr_to_page() and page_to_maddr() macros for easier address > manipulation. > - Introduce paging_ret_pages_to_domheap() to return some pages before > allocate 16 KiB pages for root page table. > - Allocate root p2m table after p2m pool is initialized. > - Add construct_hgatp() to construct the hgatp register value based on > p2m->root, p2m->hgatp_mode and VMID. Imo for this to be complete, freeing of the root table also wants taking care of. Much like imo p2m_init() would better immediately be accompanied by the respective teardown function. Once you start using them, you want to use them in pairs, after all. > --- a/xen/arch/riscv/include/asm/riscv_encoding.h > +++ b/xen/arch/riscv/include/asm/riscv_encoding.h > @@ -133,11 +133,13 @@ > #define HGATP_MODE_SV48X4 _UL(9) > > #define HGATP32_MODE_SHIFT 31 > +#define HGATP32_MODE_MASK _UL(0x80000000) > #define HGATP32_VMID_SHIFT 22 > #define HGATP32_VMID_MASK _UL(0x1FC00000) > #define HGATP32_PPN _UL(0x003FFFFF) > > #define HGATP64_MODE_SHIFT 60 > +#define HGATP64_MODE_MASK _ULL(0xF000000000000000) > #define HGATP64_VMID_SHIFT 44 > #define HGATP64_VMID_MASK _ULL(0x03FFF00000000000) > #define HGATP64_PPN _ULL(0x00000FFFFFFFFFFF) > @@ -170,6 +172,7 @@ > #define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT > #define HGATP_VMID_MASK HGATP64_VMID_MASK > #define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT > +#define HGATP_MODE_MASK HGATP64_MODE_MASK > #else > #define MSTATUS_SD MSTATUS32_SD > #define SSTATUS_SD SSTATUS32_SD > @@ -181,8 +184,11 @@ > #define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT > #define HGATP_VMID_MASK HGATP32_VMID_MASK > #define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT > +#define HGATP_MODE_MASK HGATP32_MODE_MASK > #endif > > +#define GUEST_ROOT_PAGE_TABLE_SIZE KB(16) In another context I already mentioned that imo you want to be careful with the use of "guest" in identifiers. It's not the guest page tables which have an order-2 root table, but the P2M (Xen terminology) or G-stage / second stage (RISC-V spec terminology) ones. As long as you're only doing P2M work, this may not look significant. But once you actually start dealing with guest page tables, it easily can end up confusing. > --- a/xen/arch/riscv/p2m.c > +++ b/xen/arch/riscv/p2m.c > @@ -1,8 +1,86 @@ > +#include > #include > #include > #include > > #include > +#include > +#include > + > +unsigned int __read_mostly p2m_root_order; If this is to be a variable at all, it ought to be __ro_after_init, and hence it shouldn't be written every time p2m_init() is run. If you want to to remain as a variable, what's wrong with const unsigned int p2m_root_order = ilog2(GUEST_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT; or some such? But of course equally well you could have #define P2M_ROOT_ORDER (ilog2(GUEST_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT) > +static void clear_and_clean_page(struct page_info *page) > +{ > + clear_domain_page(page_to_mfn(page)); > + > + /* > + * If the IOMMU doesn't support coherent walks and the p2m tables are > + * shared between the CPU and IOMMU, it is necessary to clean the > + * d-cache. > + */ That is, ... > + clean_dcache_va_range(page, PAGE_SIZE); ... this call really wants to be conditional? > +} > + > +static struct page_info *p2m_allocate_root(struct domain *d) With there also being p2m_alloc_root_table() and with that being the sole caller of the function here, I wonder: Is having this in a separate function really outweighing the possible confusion of which of the two functions to use? > +{ > + struct page_info *page; > + > + /* > + * As mentioned in the Priviliged Architecture Spec (version 20240411) > + * in Section 18.5.1, for the paged virtual-memory schemes (Sv32x4, > + * Sv39x4, Sv48x4, and Sv57x4), the root page table is 16 KiB and must > + * be aligned to a 16-KiB boundary. > + */ > + page = alloc_domheap_pages(d, P2M_ROOT_ORDER, MEMF_no_owner); > + if ( !page ) > + return NULL; > + > + for ( unsigned int i = 0; i < P2M_ROOT_PAGES; i++ ) > + clear_and_clean_page(page + i); > + > + return page; > +} > + > +unsigned long construct_hgatp(struct p2m_domain *p2m, uint16_t vmid) > +{ > + unsigned long ppn; > + > + ppn = PFN_DOWN(page_to_maddr(p2m->root)) & HGATP_PPN; Why not page_to_pfn() or mfn_x(page_to_mfn())? I.e. why mix different groups of accessors? As to "& HGATP_PPN" - that's making an assumption that you could avoid by using ... > + /* TODO: add detection of hgatp_mode instead of hard-coding it. */ > +#if RV_STAGE1_MODE == SATP_MODE_SV39 > + p2m->hgatp_mode = HGATP_MODE_SV39X4; > +#elif RV_STAGE1_MODE == SATP_MODE_SV48 > + p2m->hgatp_mode = HGATP_MODE_SV48X4; > +#else > +# error "add HGATP_MODE" > +#endif > + > + return ppn | MASK_INSR(p2m->hgatp_mode, HGATP_MODE_MASK) | > + MASK_INSR(vmid, HGATP_VMID_MASK); ... MASK_INSR() also on "ppn". As to the writing of p2m->hgatp_mode - you don't want to do this here, when this is the function to calculate the value to put into hgatp. This field needs calculating only once, perhaps in p2m_init(). > +static int p2m_alloc_root_table(struct p2m_domain *p2m) > +{ > + struct domain *d = p2m->domain; > + struct page_info *page; > + const unsigned int nr_root_pages = P2M_ROOT_PAGES; Is this local variable really of any use? > + /* > + * Return back nr_root_pages to assure the root table memory is also > + * accounted against the P2M pool of the domain. > + */ > + if ( !paging_ret_pages_to_domheap(d, nr_root_pages) ) > + return -ENOMEM; > + > + page = p2m_allocate_root(d); > + if ( !page ) > + return -ENOMEM; Hmm, and the pool is then left shrunk by 4 pages? > --- a/xen/arch/riscv/paging.c > +++ b/xen/arch/riscv/paging.c > @@ -54,6 +54,36 @@ int paging_freelist_init(struct domain *d, unsigned long pages, > > return 0; > } > + > +bool paging_ret_pages_to_domheap(struct domain *d, unsigned int nr_pages) > +{ > + struct page_info *page; > + > + ASSERT(spin_is_locked(&d->arch.paging.lock)); > + > + if ( ACCESS_ONCE(d->arch.paging.total_pages) < nr_pages ) > + return false; > + > + for ( unsigned int i = 0; i < nr_pages; i++ ) > + { > + /* Return memory to domheap. */ > + page = page_list_remove_head(&d->arch.paging.freelist); > + if( page ) > + { > + ACCESS_ONCE(d->arch.paging.total_pages)--; > + free_domheap_page(page); > + } > + else > + { > + printk(XENLOG_ERR > + "Failed to free P2M pages, P2M freelist is empty.\n"); > + return false; Looks pretty redundant with half of paging_freelist_init(), including the stray full stop in the log message. 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Tue, 05 Aug 2025 03:40:50 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 12:40:48 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 05/20] xen/riscv: construct the P2M pages pool for guests To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <4e7de8ffc929c1bdfa28b40fdd31b814acef103c.1753973161.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4e7de8ffc929c1bdfa28b40fdd31b814acef103c.1753973161.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > @@ -30,3 +34,18 @@ int p2m_init(struct domain *d) > > return 0; > } > + > +/* > + * Set the pool of pages to the required number of pages. > + * Returns 0 for success, non-zero for failure. > + * Call with d->arch.paging.lock held. > + */ > +int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted) Noticed only when looking at the subsequent patch: With this being ... > +{ > + int rc; > + > + if ( (rc = paging_freelist_init(d, pages, preempted)) ) ... a caller of this function, the "init" in the name feels wrong. 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Tue, 05 Aug 2025 03:43:07 -0700 (PDT) Message-ID: <7491c934-f847-4fe2-9d9b-a500f0888198@suse.com> Date: Tue, 5 Aug 2025 12:43:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 06/20] xen/riscv: add root page table allocation To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > +static int p2m_alloc_root_table(struct p2m_domain *p2m) > +{ > + struct domain *d = p2m->domain; > + struct page_info *page; > + const unsigned int nr_root_pages = P2M_ROOT_PAGES; > + > + /* > + * Return back nr_root_pages to assure the root table memory is also > + * accounted against the P2M pool of the domain. > + */ > + if ( !paging_ret_pages_to_domheap(d, nr_root_pages) ) > + return -ENOMEM; > + > + page = p2m_allocate_root(d); > + if ( !page ) > + return -ENOMEM; > + > + p2m->root = page; > + > + return 0; > +} In the success case, shouldn't you bump the paging pool's total_pages by P2M_ROOT_PAGES? (As the freeing side is missing so far, it's not easy to tell whether there's [going to be] a balancing problem in the long run. In the short run there certainly is.) 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[92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b79c3c33fesm19083698f8f.29.2025.08.05.04.22.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 04:22:25 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 777e563b-71ee-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754392946; x=1754997746; darn=lists.xenproject.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=vb12vK4YDW6kaP7yHCW2OjLcwlaEqIPC8aHdGQ+Wcuc=; b=KdZR/AYylKQivBr0wqN9wAvyt/XNEP6NdMkgkUS534tMVDiNqrrjlf+EScitBbgiAN vihgkuQPxJJnwqZESs477d/fi+BsqGS7cEiSuEQ1eDkfq6m18FFV/2DY5ppqToiEROum +p7aXZbpR4+ZGxEahMHjP9OVhWrxqZpeTE4sY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754392946; x=1754997746; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=vb12vK4YDW6kaP7yHCW2OjLcwlaEqIPC8aHdGQ+Wcuc=; b=MQEQpVyx1YbwFN//0AsKmvmxCMpqyLXz4pO4Fn0nDXvnPvf/2QKgQi1DYI1dSsxtCx zy363S90iKxkdqwmnZvFLA5oZN7+zv+Py2COK4ML2NrZUeOmeQXz7faouuZP44/l3un7 KIGY20c8fMW15Q9k0tcoI1ZpPYlp5Ckf3R+uACIGiKeHiDRuqb76vymtbdz+GhanJNog SYfUK+NB32jvv5W92/vQHvEKJFt39D2LX/5GzRrPYdtiIsE+qR7V6Lzvb3/3Ht+Y5biQ vIqtgYkx4AcNzs8YCJBBKgu+yPSXioAk9rMIs3wSTsLAkJN06agpkgzHIESPuiqQEXlr VhPg== X-Gm-Message-State: AOJu0YzmmOTTyjVKNaDFekI3uEs8Tm5SFjtaxJ29OxZsAUmpbPnF5U7Z Heu/ANTCt9hkXBDZ1R3TwebtHbNFJEwjYAY3IB6SPPLkiZdbiEtoVvuGuoOnQSOqWaU= X-Gm-Gg: ASbGncvz1SHXVkUaYXnJFF16dXSDEuSupMh0UVDB4r1I14ni/06IoB1IPs4KFX7XIO9 +TPAZUKr0y3Q5C001HkJbLXfTKSxK2fGbuu1/266ccTlZBsP//+mtJ6TdGsOvDYGdK/VvUALISr iTqotq5uawMsM/1swYQyJmWXQ+XhsZD3DfHF9BiCHwaZsfh0mfbBtXfVStxSIH9y++ZecRvOrFX OnBOyZc0U8clkKzPUB+o6Dkm10Qw0bQDHUvsSbMMXFwsll/r4ljCeGjXY7wxISIfNMEKyCYRGMl urfByvhWuKMKqQZc57yfRXDtQpzflKZZQEsIUkKbCsC5mzS+5GELDxouyUlaOFfKQohjB5X5mEq V0QtYOP4ZxZIxpQg2VxgOfWSufPeFO0GpydBwvXLBs4LuA3cVgDUqgt5X9yy/0RI3jmP1RsRYGG Mm X-Google-Smtp-Source: AGHT+IEFKgjtnVjHMthObN55/fEtKtyZ6Lt2uHRrtFggXnXt569vwoQY1lMtONYvBgupTDiGb8XM5A== X-Received: by 2002:a5d:64ec:0:b0:3ab:27f9:e51 with SMTP id ffacd0b85a97d-3b8d94bbb3amr9646808f8f.31.1754392946288; Tue, 05 Aug 2025 04:22:26 -0700 (PDT) Date: Tue, 5 Aug 2025 13:22:25 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: dmkhn@proton.me Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, sstabellini@kernel.org, teddy.astie@vates.tech, dmukhin@ford.com Subject: Re: [PATCH v10] xen/console: introduce domain_console struct Message-ID: References: <20250725210525.736706-1-dmukhin@ford.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250725210525.736706-1-dmukhin@ford.com> On Fri, Jul 25, 2025 at 09:08:02PM +0000, dmkhn@proton.me wrote: > From: Denis Mukhin > > Introduce domain_console for grouping data structures used for integrating > domain's diagnostic console with Xen's console driver. > > Group all pbuf-related data structures under domain_console. Rename the moved > fields to plain .buf, .idx and .lock names, since all uses of the fields are > touched. > > Ensure accesses to domain_console pointer are valid in console_switch_input(). > > Bump the domain console buffer allocation size to 256. No extra symbol for the > value since it is used only once during data structure declaration. All size > checks use ARRAY_SIZE(). > > Allocate domain_console from the heap so that the parent domain struct size > stays below PAGE_SIZE boundary to account for more console-related fields > added in the future. > > Finally, update the domain_console allocation and initialization code. > > Not a functional change. > > Signed-off-by: Denis Mukhin Just one request about the allocation of the domain_console in domain_create(). > --- > Changes since v9: > - kept cd as is in hvm_print_line() as requested > - dropped domain lock in hvm_print_line() > > Link to v9: https://lore.kernel.org/xen-devel/20250723001116.186009-1-dmukhin@ford.com/ > --- > xen/arch/arm/vpl011.c | 2 +- > xen/arch/x86/hvm/hvm.c | 16 +++++++++------- > xen/arch/x86/pv/shim.c | 2 +- > xen/common/domain.c | 19 +++++++++---------- > xen/drivers/char/console.c | 28 ++++++++++++++++------------ > xen/include/xen/sched.h | 24 +++++++++++++----------- > 6 files changed, 49 insertions(+), 42 deletions(-) > > diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c > index 480fc664fc62..d0d17c76b72c 100644 > --- a/xen/arch/arm/vpl011.c > +++ b/xen/arch/arm/vpl011.c > @@ -713,7 +713,7 @@ int domain_vpl011_init(struct domain *d, struct vpl011_init_info *info) > } > else > { > - d->console.input_allowed = true; > + d->console->input_allowed = true; > vpl011->backend_in_domain = false; > > vpl011->backend.xen = xzalloc(struct vpl011_xen_backend); > diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c > index 56c7de39778b..37af507a8d90 100644 > --- a/xen/arch/x86/hvm/hvm.c > +++ b/xen/arch/x86/hvm/hvm.c > @@ -560,6 +560,7 @@ static int cf_check hvm_print_line( > int dir, unsigned int port, unsigned int bytes, uint32_t *val) > { > struct domain *cd = current->domain; > + struct domain_console *cons = cd->console; > char c = *val; > > ASSERT(bytes == 1 && port == XEN_HVM_DEBUGCONS_IOPORT); > @@ -571,16 +572,17 @@ static int cf_check hvm_print_line( > if ( !is_console_printable(c) ) > return X86EMUL_OKAY; > > - spin_lock(&cd->pbuf_lock); > + spin_lock(&cons->lock); > + ASSERT(cons->idx < ARRAY_SIZE(cons->buf)); > if ( c != '\n' ) > - cd->pbuf[cd->pbuf_idx++] = c; > - if ( (cd->pbuf_idx == (DOMAIN_PBUF_SIZE - 1)) || (c == '\n') ) > + cons->buf[cons->idx++] = c; > + if ( (cons->idx == (ARRAY_SIZE(cons->buf) - 1)) || (c == '\n') ) > { > - cd->pbuf[cd->pbuf_idx] = '\0'; > - guest_printk(cd, XENLOG_G_DEBUG "%s\n", cd->pbuf); > - cd->pbuf_idx = 0; > + cons->buf[cons->idx] = '\0'; > + guest_printk(cd, XENLOG_G_DEBUG "%s\n", cons->buf); > + cons->idx = 0; > } > - spin_unlock(&cd->pbuf_lock); > + spin_unlock(&cons->lock); > > return X86EMUL_OKAY; > } > diff --git a/xen/arch/x86/pv/shim.c b/xen/arch/x86/pv/shim.c > index bc2a7dd5fae5..bd29c53a2d34 100644 > --- a/xen/arch/x86/pv/shim.c > +++ b/xen/arch/x86/pv/shim.c > @@ -239,7 +239,7 @@ void __init pv_shim_setup_dom(struct domain *d, l4_pgentry_t *l4start, > */ > d->max_pages = domain_tot_pages(d); > > - d->console.input_allowed = true; > + d->console->input_allowed = true; > } > > static void write_start_info(struct domain *d) > diff --git a/xen/common/domain.c b/xen/common/domain.c > index 303c338ef293..caef4cc8d649 100644 > --- a/xen/common/domain.c > +++ b/xen/common/domain.c > @@ -669,7 +669,7 @@ static void _domain_destroy(struct domain *d) > BUG_ON(!d->is_dying); > BUG_ON(atomic_read(&d->refcnt) != DOMAIN_DESTROYED); > > - xfree(d->pbuf); > + xvfree(d->console); Nit: even if the struct if being freed just a couple of lines below, I would use XVFREE() here. > > argo_destroy(d); > > @@ -835,8 +835,6 @@ struct domain *domain_create(domid_t domid, > flags |= CDF_hardware; > if ( old_hwdom ) > old_hwdom->cdf &= ~CDF_hardware; > - > - d->console.input_allowed = true; > } > > /* Holding CDF_* internal flags. */ > @@ -866,8 +864,6 @@ struct domain *domain_create(domid_t domid, > spin_lock_init(&d->shutdown_lock); > d->shutdown_code = SHUTDOWN_CODE_INVALID; > > - spin_lock_init(&d->pbuf_lock); > - > rwlock_init(&d->vnuma_rwlock); > > #ifdef CONFIG_HAS_PCI > @@ -877,6 +873,14 @@ struct domain *domain_create(domid_t domid, > > /* All error paths can depend on the above setup. */ > > + err = -ENOMEM; > + d->console = xvzalloc(typeof(*d->console)); > + if ( !d->console ) > + goto fail; > + > + spin_lock_init(&d->console->lock); > + d->console->input_allowed = is_hardware_domain(d); That's too early to do the allocation of the console buffer AFAICT. It needs to be done after the: if ( is_system_domain(d) ) return d; check, as allocating a console buffer for system domains is pointless. > + > /* > * Allocate d->vcpu[] and set ->max_vcpus up early. Various per-domain > * resources want to be sized based on max_vcpus. > @@ -959,11 +963,6 @@ struct domain *domain_create(domid_t domid, > if ( (err = argo_init(d)) != 0 ) > goto fail; > > - err = -ENOMEM; > - d->pbuf = xzalloc_array(char, DOMAIN_PBUF_SIZE); > - if ( !d->pbuf ) > - goto fail; > - > if ( (err = sched_init_domain(d, config->cpupool_id)) != 0 ) > goto fail; > > diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c > index 963c7b043cd8..75fa033ce74d 100644 > --- a/xen/drivers/char/console.c > +++ b/xen/drivers/char/console.c > @@ -526,7 +526,7 @@ struct domain *console_get_domain(void) > if ( !d ) > return NULL; > > - if ( d->console.input_allowed ) > + if ( d->console->input_allowed ) > return d; > > rcu_unlock_domain(d); > @@ -567,10 +567,13 @@ static void console_switch_input(void) > d = rcu_lock_domain_by_id(domid); > if ( d ) > { > - rcu_unlock_domain(d); > - > - if ( !d->console.input_allowed ) > + if ( !d->console->input_allowed ) > + { > + rcu_unlock_domain(d); > continue; > + } > + > + rcu_unlock_domain(d); > > console_rx = next_rx; > printk("*** Serial input to DOM%u", domid); > @@ -749,6 +752,7 @@ static long guest_console_write(XEN_GUEST_HANDLE_PARAM(char) buffer, > else > { > char *kin = kbuf, *kout = kbuf, c; > + struct domain_console *cons = cd->console; > > /* Strip non-printable characters */ > do > @@ -761,22 +765,22 @@ static long guest_console_write(XEN_GUEST_HANDLE_PARAM(char) buffer, > } while ( --kcount > 0 ); > > *kout = '\0'; > - spin_lock(&cd->pbuf_lock); > + spin_lock(&cons->lock); > kcount = kin - kbuf; > if ( c != '\n' && > - (cd->pbuf_idx + (kout - kbuf) < (DOMAIN_PBUF_SIZE - 1)) ) > + (cons->idx + (kout - kbuf) < (ARRAY_SIZE(cons->buf) - 1)) ) > { > /* buffer the output until a newline */ > - memcpy(cd->pbuf + cd->pbuf_idx, kbuf, kout - kbuf); > - cd->pbuf_idx += (kout - kbuf); > + memcpy(cons->buf + cons->idx, kbuf, kout - kbuf); > + cons->idx += kout - kbuf; > } > else > { > - cd->pbuf[cd->pbuf_idx] = '\0'; > - guest_printk(cd, XENLOG_G_DEBUG "%s%s\n", cd->pbuf, kbuf); > - cd->pbuf_idx = 0; > + cons->buf[cons->idx] = '\0'; > + guest_printk(cd, XENLOG_G_DEBUG "%s%s\n", cons->buf, kbuf); > + cons->idx = 0; > } > - spin_unlock(&cd->pbuf_lock); > + spin_unlock(&cons->lock); > } > > guest_handle_add_offset(buffer, kcount); > diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h > index fe53d4fab7ba..c828d5626dea 100644 > --- a/xen/include/xen/sched.h > +++ b/xen/include/xen/sched.h > @@ -371,6 +371,17 @@ struct evtchn_port_ops; > > #define MAX_NR_IOREQ_SERVERS 8 > > +/* Domain console settings. */ > +struct domain_console { > + /* Permission to take ownership of the physical console input. */ > + bool input_allowed; > + > + /* hvm_print_line() and guest_console_write() logging. */ > + unsigned int idx; > + spinlock_t lock; > + char buf[256]; > +}; > + > struct domain > { > domid_t domain_id; > @@ -562,12 +573,6 @@ struct domain > /* Control-plane tools handle for this domain. */ > xen_domain_handle_t handle; > > - /* hvm_print_line() and guest_console_write() logging. */ > -#define DOMAIN_PBUF_SIZE 200 > - char *pbuf; > - unsigned int pbuf_idx; > - spinlock_t pbuf_lock; > - > /* OProfile support. */ > struct xenoprof *xenoprof; > > @@ -652,11 +657,8 @@ struct domain > const unsigned int *llc_colors; > #endif > > - /* Console settings. */ > - struct { > - /* Permission to take ownership of the physical console input. */ > - bool input_allowed; > - } console; > + /* Pointer to console settings; NULL for system Xen domains. */ Nit: I would drop Xen from the sentence above, "system domains" is a well known entity in this context. Thanks, Roger. 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Xen 4.19.3 is available from its git repository http://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=refs/heads/stable-4.19 (tag RELEASE-4.19.3) or (eventually) from the XenProject download page https://xenproject.org/resources/downloads/. We recommend all users of the 4.19 stable series to update to this latest point release. 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Tue, 05 Aug 2025 05:11:23 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 14:11:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/8] pdx: allow per-arch optimization of PDX conversion helpers To: Roger Pau Monne Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , xen-devel@lists.xenproject.org References: <20250805095257.74975-1-roger.pau@citrix.com> <20250805095257.74975-5-roger.pau@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250805095257.74975-5-roger.pau@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05.08.2025 11:52, Roger Pau Monne wrote: > There are four performance critical PDX conversion helpers that do the PFN > to/from PDX and the physical addresses to/from directmap offsets > translations. > > In the absence of an active PDX compression, those functions would still do > the calculations needed, just to return the same input value as no > translation is in place and hence PFN and PDX spaces are identity mapped. > > To reduce the overhead of having to do the pointless calculations allow > architectures to implement the translation helpers in a per-arch header. > Rename the existing conversion functions to add a trailing _xlate suffix, > so that the per-arch headers can define the non suffixed versions. > > Currently only x86 implements meaningful custom handlers to short circuit > the translation when not active, using asm goto. Other architectures use > generic macros that map the non-xlate to the xlate variants to keep the > previous behavior. > > Signed-off-by: Roger Pau Monné Once again: Reviewed-by: Jan Beulich Jan From xen-devel-bounces@lists.xenproject.org Tue Aug 05 12:28:39 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 12:28:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070440.1434057 (Exim 4.92) (envelope-from ) id 1ujGmJ-0006yO-Cz; Tue, 05 Aug 2025 12:28:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070440.1434057; Tue, 05 Aug 2025 12:28:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujGmJ-0006yH-AO; Tue, 05 Aug 2025 12:28:27 +0000 Received: by outflank-mailman (input) for mailman id 1070440; Tue, 05 Aug 2025 12:28:26 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujGmI-0006yB-3W for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 12:28:26 +0000 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [2a00:1450:4864:20::62e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id ae76525e-71f7-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 14:28:24 +0200 (CEST) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-af8fd1b80e5so935171266b.2 for ; Tue, 05 Aug 2025 05:28:24 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 05 Aug 2025 05:28:24 -0700 (PDT) Message-ID: <50aa7098-3777-43b2-8217-0b836a3c8879@suse.com> Date: Tue, 5 Aug 2025 14:28:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 7/8] pdx: introduce a new compression algorithm based on region offsets To: Roger Pau Monne Cc: Oleksii Kurochko , Community Manager , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , xen-devel@lists.xenproject.org References: <20250805095257.74975-1-roger.pau@citrix.com> <20250805095257.74975-8-roger.pau@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250805095257.74975-8-roger.pau@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05.08.2025 11:52, Roger Pau Monne wrote: > --- a/xen/common/pdx.c > +++ b/xen/common/pdx.c > @@ -24,6 +24,7 @@ > #include > #include > #include > +#include > > /** > * Maximum (non-inclusive) usable pdx. Must be > @@ -40,6 +41,12 @@ bool __mfn_valid(unsigned long mfn) > > #ifdef CONFIG_PDX_MASK_COMPRESSION > invalid |= mfn & pfn_hole_mask; > +#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) > +{ > + unsigned long base = pfn_bases[PFN_TBL_IDX(mfn)]; > + > + invalid |= mfn < base || mfn >= base + pdx_region_size; > +} > #endif Hmm, didn't notice this earlier on: Brace placement looks odd here. I think they want to be indented by one level, as they aren't starting a function body. > @@ -294,7 +308,245 @@ void __init pfn_pdx_compression_reset(void) > nr_ranges = 0; > } > > -#endif /* CONFIG_PDX_COMPRESSION */ > +#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) /* CONFIG_PDX_MASK_COMPRESSION */ > + > +unsigned int __ro_after_init pfn_index_shift; > +unsigned int __ro_after_init pdx_index_shift; > + > +unsigned long __ro_after_init pfn_pdx_lookup[CONFIG_PDX_NR_LOOKUP]; > +unsigned long __ro_after_init pdx_pfn_lookup[CONFIG_PDX_NR_LOOKUP]; > +unsigned long __ro_after_init pfn_bases[CONFIG_PDX_NR_LOOKUP]; > +unsigned long __ro_after_init pdx_region_size = ~0UL; For cache locality, might this last one better also move ahead of the arrays? > +bool pdx_is_region_compressible(paddr_t base, unsigned long npages) > +{ > + unsigned long pfn = PFN_DOWN(base); > + unsigned long pfn_base = pfn_bases[PFN_TBL_IDX(pfn)]; > + > + return pfn >= pfn_base && > + pfn + npages <= pfn_base + pdx_region_size; > +} > + > +static int __init cf_check cmp_node(const void *a, const void *b) > +{ > + const struct pfn_range *l = a; > + const struct pfn_range *r = b; > + > + if ( l->base_pfn > r->base_pfn ) > + return 1; > + if ( l->base_pfn < r->base_pfn ) > + return -1; > + > + return 0; > +} > + > +static void __init cf_check swp_node(void *a, void *b) > +{ > + SWAP(a, b); > +} This hasn't changed from v3, and still looks wrong to me. > +bool __init pfn_pdx_compression_setup(paddr_t base) > +{ > + unsigned long mask = PFN_DOWN(pdx_init_mask(base)), idx_mask = 0; > + unsigned long pages = 0; > + unsigned int i; > + > + if ( !nr_ranges ) > + { > + printk(XENLOG_DEBUG "PFN compression disabled%s\n", > + pdx_compress ? ": no ranges provided" : ""); > + return false; > + } > + > + if ( nr_ranges > ARRAY_SIZE(ranges) ) > + { > + printk(XENLOG_WARNING > + "Too many PFN ranges (%u > %zu), not attempting PFN compression\n", > + nr_ranges, ARRAY_SIZE(ranges)); > + return false; > + } > + > + /* Sort ranges by start address. */ > + sort(ranges, nr_ranges, sizeof(*ranges), cmp_node, swp_node); > + > + for ( i = 0; i < nr_ranges; i++ ) > + { > + unsigned long start = ranges[i].base_pfn; > + > + /* > + * Align range base to MAX_ORDER. This is required so the PDX offset > + * for the bits below MAX_ORDER matches the MFN offset, and pages > + * greater than the minimal order can be used to populate the > + * directmap. > + */ > + ranges[i].base_pfn = start & ~((1UL << MAX_ORDER) - 1); > + ranges[i].pages = start + ranges[i].pages - ranges[i].base_pfn; > + > + /* > + * Only merge overlapped regions now, leave adjacent regions separated. > + * They would be merged later if both use the same index into the > + * lookup table. > + */ > + if ( !i || > + ranges[i].base_pfn >= > + (ranges[i - 1].base_pfn + ranges[i - 1].pages) ) > + { > + mask |= pdx_region_mask(ranges[i].base_pfn, ranges[i].pages); > + continue; > + } > + > + ranges[i - 1].pages = ranges[i].base_pfn + ranges[i].pages - > + ranges[i - 1].base_pfn; > + > + if ( i + 1 < nr_ranges ) > + memmove(&ranges[i], &ranges[i + 1], > + (nr_ranges - (i + 1)) * sizeof(ranges[0])); > + else /* last range */ > + mask |= pdx_region_mask(ranges[i].base_pfn, ranges[i].pages); > + nr_ranges--; > + i--; > + } > + > + /* > + * Populate a mask with the non-equal bits of the different ranges, do this > + * to calculate the maximum PFN shift to use as the lookup table index. > + */ > + for ( i = 0; i < nr_ranges; i++ ) > + for ( unsigned int j = 0; j < nr_ranges; j++ ) > + idx_mask |= (ranges[i].base_pfn & ~mask) ^ > + (ranges[j].base_pfn & ~mask); "mask" is loop invariant - can't the AND-ing be pulled out, after the loop? Further, isn't it sufficient for the inner loop to start from i + 1? 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Tue, 05 Aug 2025 05:38:39 -0700 (PDT) Message-ID: <31691bf7-94bf-4f73-b04c-a32f86bb0e37@suse.com> Date: Tue, 5 Aug 2025 14:38:38 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 8/8] x86/mm: adjust loop in arch_init_memory() to iterate over the PDX space To: Roger Pau Monne Cc: Andrew Cooper , xen-devel@lists.xenproject.org References: <20250805095257.74975-1-roger.pau@citrix.com> <20250805095257.74975-9-roger.pau@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250805095257.74975-9-roger.pau@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05.08.2025 11:52, Roger Pau Monne wrote: > --- a/xen/arch/x86/mm.c > +++ b/xen/arch/x86/mm.c > @@ -275,7 +275,7 @@ static void __init assign_io_page(struct page_info *page) > > void __init arch_init_memory(void) > { > - unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn; > + unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn, pdx; > > /* > * Basic guest-accessible flags: > @@ -328,9 +328,20 @@ void __init arch_init_memory(void) > destroy_xen_mappings((unsigned long)mfn_to_virt(iostart_pfn), > (unsigned long)mfn_to_virt(ioend_pfn)); > > - /* Mark as I/O up to next RAM region. */ > - for ( ; pfn < rstart_pfn; pfn++ ) > + /* > + * Mark as I/O up to next RAM region. Iterate over the PDX space to > + * skip holes which would always fail the mfn_valid() check. > + * > + * pfn_to_pdx() requires a valid (iow: RAM) PFN to convert to PDX, > + * hence provide pfn - 1, which is the tailing PFN from the last RAM > + * range, or pdx 0 if the input pfn is 0. > + */ > + for ( pdx = pfn ? pfn_to_pdx(pfn - 1) + 1 : 0; > + pdx < pfn_to_pdx(rstart_pfn); > + pdx++ ) > { > + pfn = pdx_to_pfn(pdx); > + > if ( !mfn_valid(_mfn(pfn)) ) > continue; > As much as I would have liked to ack this, I fear there's another caveat here: At the top of the loop we check not only for RAM, but also for UNUSABLE. The latter, like RAM, shouldn't be marked I/O, but we also can't use PFN <-> PDX transformations on any such page. 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bugseng.com; arc=none smtp.remote-ip=162.55.131.47 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=bugseng.com; s=mail; t=1754400143; bh=fLlSmMB8OttCWI618y1+A1e6c9DZsadgQRWTgiALugA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Z9XSomEccalJz+RpSSbEQEIzOjRWdQ1wAMg1Cq/qUq5+FDb3xkplB+YlgzCLZArB9 9Ut0LhrA0+wT3hqvg+IPk6wnsrzchdfNVEMkyFTT1nV+hSNkbREKEb2MiVnkSgYrUJ 56LXRN2+yX4uxnh9bjKwo/U+qX9G1yQxIvB1l/TeV7VQr+I//MlI6q8DPKMGqTKF10 WO/F2fbkapeOttMufpft+96tYl9O+jjWuSg2IxuGX/e4PViRR85u+8Z1e2yDTxlCq4 EyS0j1NGgxHlF3qqrZskMZQQpj73nKesn/oP5n+bWyv2JZtfmD0QuWJZz5ERkBxv9f YJP715kbXHnaA== MIME-Version: 1.0 Date: Tue, 05 Aug 2025 15:22:23 +0200 From: Nicola Vetrini To: Dmytro Prokopchuk1 Cc: Andrew Cooper , Jan Beulich , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Dario Faggioli , Juergen Gross , George Dunlap , xen-devel@lists.xenproject.org Subject: Re: [PATCH] misra: fix violations in macros GVA_INFO, TRACE_TIME In-Reply-To: <91d2a8ec-8a8e-404a-85ac-1038317e937b@epam.com> References: <73cfc8a2d4d66042b49f44c69e672ce8ad0556ce.1753971749.git.dmytro_prokopchuk1@epam.com> <470a04e6-f8c1-4937-8478-0f80107d562d@citrix.com> <898e1c2a-7684-489b-84cd-254b2ee53e5d@suse.com> <9952fc5c-b95a-4879-a442-12e491438e08@citrix.com> <689178480a418f04158d623e3cedd4bd@bugseng.com> <91d2a8ec-8a8e-404a-85ac-1038317e937b@epam.com> Message-ID: <1a59e6d831fd7119df1e2bd0cdbe262b@bugseng.com> X-Sender: nicola.vetrini@bugseng.com Organization: BUGSENG s.r.l. Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2025-08-05 13:49, Dmytro Prokopchuk1 wrote: > On 7/31/25 19:09, Nicola Vetrini wrote: >> On 2025-07-31 18:05, Andrew Cooper wrote: >>> On 31/07/2025 4:58 pm, Jan Beulich wrote: >>>> On 31.07.2025 17:37, Andrew Cooper wrote: >>>>> On 31/07/2025 4:16 pm, Dmytro Prokopchuk1 wrote: >>>>>> MISRA Rule 13.1: Initializer lists shall not contain persistent >>>>>> side >>>>>> effects. >>>>>> >>>>>> The violations occur because both the `GVA_INFO` and `TRACE_TIME` >>>>>> macro >>>>>> expansions include expressions with persistent side effects >>>>>> introduced >>>>>> via inline assembly. >>>>>> >>>>>> In the case of `GVA_INFO`, the issue stems from the initializer >>>>>> list >>>>>> containing a direct call to `current`, which evaluates to >>>>>> `this_cpu(curr_vcpu)` and involves persistent side effects via the >>>>>> `asm` statement. To resolve this, the side-effect-producing >>>>>> expression >>>>>> is computed in a separate statement prior to the macro >>>>>> initialization: >>>>>> >>>>>>     struct vcpu *current_vcpu = current; >>>>>> >>>>>> The computed value is passed into the `GVA_INFO(current_vcpu)` >>>>>> macro, >>>>>> ensuring that the initializer is clean and free of such side >>>>>> effects. >>>>>> >>>>>> Similarly, the `TRACE_TIME` macro violates this rule when >>>>>> accessing >>>>>> expressions like `current->vcpu_id` and >>>>>> `current->domain->domain_id`, >>>>>> which also depend on `current` and inline assembly. To fix this, >>>>>> the >>>>>> value of `current` is assigned to a temporary variable: >>>>>> >>>>>>     struct vcpu *v = current; >>>>>> >>>>>> This temporary variable is then used to access `domain_id` and >>>>>> `vcpu_id`. >>>>>> This ensures that the arguments passed to the `TRACE_TIME` macro >>>>>> are >>>>>> simple expressions free of persistent side effects. >>>>>> >>>>>> Signed-off-by: Dmytro Prokopchuk >>>>> The macro `current` specifically does not (and must not) have side >>>>> effects.  It is expected to behave like a plain `struct vcpu >>>>> *current;` >>>>> variable, and what Eclair is noticing is the thread-local machinery >>>>> under this_cpu() (or in x86's case, get_current()). >>>>> >>>>> In ARM's case, it's literally reading the hardware thread pointer >>>>> register.  Can anything be done to tell Eclair that `this_cpu()` >>>>> specifically does not have side effects? >>>>> >>>>> The only reason that GVA_INFO() and TRACE_TIME() are picked out is >>>>> because they both contain embedded structure initialisation, and >>>>> this is >>>>> is actually an example where trying to comply with MISRA interferes >>>>> with >>>>> what is otherwise a standard pattern in Xen. >>>> Irrespective of what you say, some of the changes here were >>>> eliminating >>>> multiple adjacent uses of current, which - iirc - often the compiler >>>> can't fold via CSE. >>> >>> Where we have mixed usage, sure.  (I'm sure I've got a branch >>> somewhere >>> trying to add some more pure/const around to try and help out here, >>> but >>> I can't find it, and don't recall it being a major improvement >>> either.) >>> >>> The real problem here is that there are a *very few* number of >>> contexts >>> where Eclair refuses to tolerate the use of `current` citing side >>> effects, despite there being no side effects. >>> >>> That is the thing that breaks the principle of least surprise, and we >>> ought to fix it by making Eclair happy with `current` everywhere, >>> rather >>> than force people to learn that 2 macros can't have a `current` in >>> their >>> parameter list. >>> >> >> I'll take a look. Likely yes, by adding a handful of properties. There >> are subtleties, though. >> > > Hi, Nicola. > > Did you have a chance to try configure Eclair to ignore this macro > `this_cpu()`? > Hi Dmytro, I'm on it, I needed to handle other tasks first. > Thanks. > Dmytro -- Nicola Vetrini, B.Sc. Software Engineer BUGSENG (https://bugseng.com) LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 13:38:58 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 13:38:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070488.1434088 (Exim 4.92) (envelope-from ) id 1ujHsM-00004z-R2; Tue, 05 Aug 2025 13:38:46 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070488.1434088; Tue, 05 Aug 2025 13:38:46 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujHsM-00004q-Na; Tue, 05 Aug 2025 13:38:46 +0000 Received: by outflank-mailman (input) for mailman id 1070488; Tue, 05 Aug 2025 13:38:45 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujHsL-0008WQ-4T for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 13:38:45 +0000 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [2a00:1450:4864:20::42a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 7e70e7e5-7201-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 15:38:39 +0200 (CEST) Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3b790dbb112so3080327f8f.3 for ; Tue, 05 Aug 2025 06:38:39 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. [92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id ffacd0b85a97d-3b79c3b9eddsm19252765f8f.22.2025.08.05.06.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 06:38:37 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7e70e7e5-7201-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754401118; x=1755005918; darn=lists.xenproject.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=1ICPZPpXze7J7LRr91S6QodYf4qNrYblEf+QBJDXMUo=; b=hdRsLhvVixPtaXS191GtLoGkV+NqQQ5AUCtIhHOwAaTb9XZX63wWkk98ciliVevEuW Mj0Sf2mrnlT2LsSRglFbG0p2oGXoDIUzK5RctVGGcyaKamHgNRPwWpKbcapOKq6DQ66d YIJcZAWtvbOhh6Yjz6ZV/TondEqNgxWTsePMA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754401118; x=1755005918; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=1ICPZPpXze7J7LRr91S6QodYf4qNrYblEf+QBJDXMUo=; b=uXEpPoswRe+l267n0u4kqJCr2ImQ6tfGWii2AOSYFdnn4JfC8z5T8ArAm676/T/sJ4 LbnVKGjBdCfrT82W8Lddykty2soU8ANPs8SdbMfEoJSMbpb2940FydhTs+4hhr3frIDu 8bVQmRQO2K5zFOThSRjmzZYwrj8DRfGzpSWtd82A5KqBIAGoyaX4XBkEY3SlywPK7vns /AFTcndIOWh5+VyCPky4Rh3S6loURU+2briqLXTuMVAIS9qpJasfjHLBnnFMgFGUa5Xv SbsHfEXThO0Q5dMBwpE7nyz/WesLsU0mWQN9Z5Y14w+VSpz4N4phFgvc2mQdEfwBKr6M zlag== X-Gm-Message-State: AOJu0YzYu6OSNFznht1xMQMCgStlsA/nztjF+6AEEdMDQi2la8f6j682 oh9fdUzVR1FApDHN2GvzJLJ0FrtA4nsTQ//W8Nh3QqVbfqC8pdzFtUNv+Vd2GynGm6o= X-Gm-Gg: ASbGncv/NlZztU6unqv5vXD6+ffdynrYpQd8rjO0YJ7H3LkdXpVameu0wKUZzM/qrNd XBvTAaD5b+iMr5g6UOoLa7ulxb/f+zSoKuh45EVk8WaxHbY3cPyCcow7Za+RVbOHJySthg1DUZV dGj5TpImFB4iwzGE8cslaLzKI5gUMOmpmiXguyGejfbyIniF7ZN0b5t/wy+xKBki+hfNpq6ppCx t+jPAHv7YNndLfF/ffD5hq2n7Gp01RB5AXVsC8ECgn8pVXqvt097QSnGhM/qKwWbsMBHk41Ns9m 7K/JkdABangnNT0e549ueBU3X6UYkpdV4e1Z0I0zIkSIIpgHdqpjSCe7+3oSsgxtEcsJPY9ekev zbrKPwqmf4EDAjcqWtxM6F6go6C6PPKSIFAGF/eHsQLkH9CwfqVPqLY3dcUbb6VCiUohyEkVmoX Ts X-Google-Smtp-Source: AGHT+IFDEV4GGxybwIMaWwcQebpxjNel+VuoJ9aMQQ4jDghvQGo1aF4/C/MSeSv6FuOupAgAzSFzxQ== X-Received: by 2002:a05:6000:18af:b0:3a4:dc2a:924e with SMTP id ffacd0b85a97d-3b8d94684e8mr9949850f8f.6.1754401118403; Tue, 05 Aug 2025 06:38:38 -0700 (PDT) Date: Tue, 5 Aug 2025 15:38:37 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: dmkhn@proton.me Cc: xen-devel@lists.xenproject.org, alejandro.garciavallejo@amd.com, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com Subject: Re: [PATCH v13 1/3] xen/domain: unify domain ID allocation Message-ID: References: <20250730174042.1632011-1-dmukhin@ford.com> <20250730174042.1632011-2-dmukhin@ford.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250730174042.1632011-2-dmukhin@ford.com> On Wed, Jul 30, 2025 at 05:40:54PM +0000, dmkhn@proton.me wrote: > From: Denis Mukhin > > Currently, there are two different domain ID allocation implementations: > > 1) Sequential IDs allocation in dom0less Arm code based on max_init_domid; > > 2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use > max_init_domid (both Arm and x86). > > The domain ID allocation covers dom0 or late hwdom, predefined domains, > post-boot domains, excluding Xen system domains (domid >= > DOMID_FIRST_RESERVED). > > It makes sense to have a common helper code for such task across architectures > (Arm and x86) and between dom0less / toolstack domU allocation. > > Note, fixing dependency on max_init_domid is out of scope of this patch. > > Wrap the domain ID allocation as an arch-independent function domid_alloc() in > new common/domid.c based on the bitmap. > > Allocation algorithm: > - If an explicit domain ID is provided, verify its availability and use it if > ID is not used; > - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1], > starting from the last used ID. > Implementation guarantees that two consecutive calls will never return the > same ID. ID#0 is reserved for the first boot domain (currently, dom0) and > excluded from the allocation range. > > Remove is_free_domid() helper as it is not needed now. > > No functional change intended. > > Signed-off-by: Denis Mukhin > Reviewed-by: Alejandro Vallejo > --- > Changes since v12: > - updated comment for domid_alloc() and commit message > - added Alejandro's R-b > --- > xen/arch/arm/domain_build.c | 7 +- > xen/arch/x86/setup.c | 7 +- > xen/common/Makefile | 1 + > xen/common/device-tree/dom0less-build.c | 15 ++-- > xen/common/domain.c | 2 + > xen/common/domctl.c | 42 ++--------- > xen/common/domid.c | 94 +++++++++++++++++++++++++ > xen/include/xen/domain.h | 3 + > 8 files changed, 124 insertions(+), 47 deletions(-) > create mode 100644 xen/common/domid.c > > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index 463ae4474d30..789f2b9d3ce7 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -2050,6 +2050,7 @@ void __init create_dom0(void) > .grant_opts = XEN_DOMCTL_GRANT_version(opt_gnttab_max_version), > }; > unsigned int flags = CDF_privileged | CDF_hardware; > + domid_t domid; > int rc; > > /* The vGIC for DOM0 is exactly emulating the hardware GIC */ > @@ -2074,7 +2075,11 @@ void __init create_dom0(void) > if ( !llc_coloring_enabled ) > flags |= CDF_directmap; > > - dom0 = domain_create(0, &dom0_cfg, flags); > + domid = domid_alloc(0); > + if ( domid == DOMID_INVALID ) > + panic("Error allocating domain ID 0\n"); > + > + dom0 = domain_create(domid, &dom0_cfg, flags); > if ( IS_ERR(dom0) ) > panic("Error creating domain 0 (rc = %ld)\n", PTR_ERR(dom0)); > > diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c > index 1543dd251cc6..2ff7c28c277b 100644 > --- a/xen/arch/x86/setup.c > +++ b/xen/arch/x86/setup.c > @@ -1047,8 +1047,11 @@ static struct domain *__init create_dom0(struct boot_info *bi) > if ( iommu_enabled ) > dom0_cfg.flags |= XEN_DOMCTL_CDF_iommu; > > - /* Create initial domain. Not d0 for pvshim. */ > - bd->domid = get_initial_domain_id(); > + /* Allocate initial domain ID. Not d0 for pvshim. */ > + bd->domid = domid_alloc(get_initial_domain_id()); > + if ( bd->domid == DOMID_INVALID ) > + panic("Error allocating domain ID %d\n", get_initial_domain_id()); Nit: in other error messages in the same function we handle the domid as an unsigned integer, so %u probably wants using here. Unless you have an explicit intention to print IDs >= DOMID_FIRST_RESERVED as negative integers? > + > d = domain_create(bd->domid, &dom0_cfg, > pv_shim ? 0 : CDF_privileged | CDF_hardware); > if ( IS_ERR(d) ) > diff --git a/xen/common/Makefile b/xen/common/Makefile > index c316957fcb36..0c7d0f5d46e1 100644 > --- a/xen/common/Makefile > +++ b/xen/common/Makefile > @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o > obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/ > obj-$(CONFIG_IOREQ_SERVER) += dm.o > obj-y += domain.o > +obj-y += domid.o > obj-y += event_2l.o > obj-y += event_channel.o > obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o > diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c > index 6bb038111de9..f4b6b515d2d2 100644 > --- a/xen/common/device-tree/dom0less-build.c > +++ b/xen/common/device-tree/dom0less-build.c > @@ -833,6 +833,7 @@ void __init create_domUs(void) > { > struct kernel_info ki = KERNEL_INFO_INIT; > int rc = parse_dom0less_node(node, &ki.bd); > + domid_t domid; > > if ( rc == -ENOENT ) > continue; > @@ -842,13 +843,13 @@ void __init create_domUs(void) > if ( (max_init_domid + 1) >= DOMID_FIRST_RESERVED ) > panic("No more domain IDs available\n"); > > - /* > - * The variable max_init_domid is initialized with zero, so here it's > - * very important to use the pre-increment operator to call > - * domain_create() with a domid > 0. (domid == 0 is reserved for Dom0) > - */ > - ki.bd.d = domain_create(++max_init_domid, > - &ki.bd.create_cfg, ki.bd.create_flags); > + domid = domid_alloc(DOMID_INVALID); > + if ( domid == DOMID_INVALID ) > + panic("Error allocating ID for domain %s\n", dt_node_name(node)); > + > + max_init_domid = max(max_init_domid, domid); > + > + ki.bd.d = domain_create(domid, &ki.bd.create_cfg, ki.bd.create_flags); > if ( IS_ERR(ki.bd.d) ) > panic("Error creating domain %s (rc = %ld)\n", > dt_node_name(node), PTR_ERR(ki.bd.d)); > diff --git a/xen/common/domain.c b/xen/common/domain.c > index 5241a1629eeb..12fbab01cd8e 100644 > --- a/xen/common/domain.c > +++ b/xen/common/domain.c > @@ -1473,6 +1473,8 @@ void domain_destroy(struct domain *d) > /* Remove from the domlist/hash. */ > domlist_remove(d); > > + domid_free(d->domain_id); The domlist removal above still allows current users to continue "operating" on the domain until the next RCU. Should for safety the freeing of the domid be deferred to _domain_destroy(), which is executed in RCU context, and thus ensures there are no current users of the removed domain? I cannot think of a specific scenario where this could be dangerous right now, but deferring to RCU context together with the final cleanup seems safer overall. > + > /* Schedule RCU asynchronous completion of domain destroy. */ > call_rcu(&d->rcu, complete_domain_destroy); > } > diff --git a/xen/common/domctl.c b/xen/common/domctl.c > index f2a7caaf853c..5509998aa139 100644 > --- a/xen/common/domctl.c > +++ b/xen/common/domctl.c > @@ -51,20 +51,6 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nodemask, > MAX_NUMNODES); > } > > -static inline int is_free_domid(domid_t dom) > -{ > - struct domain *d; > - > - if ( dom >= DOMID_FIRST_RESERVED ) > - return 0; > - > - if ( (d = rcu_lock_domain_by_id(dom)) == NULL ) > - return 1; > - > - rcu_unlock_domain(d); > - return 0; > -} > - > void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info) > { > struct vcpu *v; > @@ -423,36 +409,18 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) > > case XEN_DOMCTL_createdomain: > { > - domid_t dom; > - static domid_t rover = 0; > + domid_t domid = domid_alloc(op->domain); > > - dom = op->domain; > - if ( (dom > 0) && (dom < DOMID_FIRST_RESERVED) ) > + if ( domid == DOMID_INVALID ) This is a change in behavior AFAICT, as you now allow XEN_DOMCTL_createdomain to possibly create a domain with domid 0 (if it's available). Currently op->domain == 0 is handled as op->domain == DOMID_FIRST_RESERVED. You either need to adjust the code here, so that you do: domid_t domid = domid_alloc(op->domain ?: DOMID_FIRST_RESERVED); Or domid_alloc() needs to be adjusted to handle an input domid == 0 as it handles DOMID_FIRST_RESERVED. > { > ret = -EEXIST; > - if ( !is_free_domid(dom) ) > - break; > - } > - else > - { > - for ( dom = rover + 1; dom != rover; dom++ ) > - { > - if ( dom == DOMID_FIRST_RESERVED ) > - dom = 1; > - if ( is_free_domid(dom) ) > - break; > - } > - > - ret = -ENOMEM; > - if ( dom == rover ) > - break; > - > - rover = dom; > + break; > } > > - d = domain_create(dom, &op->u.createdomain, false); > + d = domain_create(domid, &op->u.createdomain, false); > if ( IS_ERR(d) ) > { > + domid_free(domid); > ret = PTR_ERR(d); > d = NULL; > break; > diff --git a/xen/common/domid.c b/xen/common/domid.c > new file mode 100644 > index 000000000000..e727dcaf0793 > --- /dev/null > +++ b/xen/common/domid.c > @@ -0,0 +1,94 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Domain ID allocator. > + * > + * Covers dom0 or late hwdom, predefined domains, post-boot domains. > + * Excludes Xen system domains (ID >= DOMID_FIRST_RESERVED). > + * > + * Copyright 2025 Ford Motor Company > + */ > + > +#include > + > +static DEFINE_SPINLOCK(domid_lock); > +static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED); > + > +/* > + * Allocate domain ID. > + * > + * @param domid Domain ID hint: > + * - If an explicit domain ID is provided, verify its availability and use it > + * if ID is not used; > + * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] range, > + * starting from the last used ID. Implementation guarantees that two > + * consecutive calls will never return the same ID. ID#0 is reserved for > + * the first boot domain (currently, dom0) and excluded from the allocation > + * range. > + * @return Valid domain ID in case of successful allocation, > + * DOMID_INVALID - otherwise. > + */ > +domid_t domid_alloc(domid_t domid) > +{ > + static domid_t domid_last; > + > + spin_lock(&domid_lock); > + > + /* Exact match. */ > + if ( domid < DOMID_FIRST_RESERVED ) > + { > + if ( __test_and_set_bit(domid, domid_bitmap) ) > + domid = DOMID_INVALID; > + } > + /* > + * Exhaustive search. > + * > + * Domain ID#0 is reserved for the first boot domain (e.g. control domain) > + * and excluded from allocation. > + */ > + else > + { > + domid = find_next_zero_bit(domid_bitmap, > + DOMID_FIRST_RESERVED, > + domid_last + 1); > + if ( domid == DOMID_FIRST_RESERVED ) Nit: you could further gate this second search to domid_last != 0, as otherwise the first search has already scanned the whole bitmap. > + domid = find_next_zero_bit(domid_bitmap, > + DOMID_FIRST_RESERVED, > + 1); Nit: you could possibly limit this second search to (domid_last + 1) size, as you have already searched from [domid_last + 1, DOMID_FIRST_RESERVED], and the bitmap couldn't have changed as the lock is being held. Thanks, Roger. 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Tue, 05 Aug 2025 07:11:33 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 16:11:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 10/20] xen/riscv: introduce page_{get,set}_xenheap_gfn() To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <5aa3beb7fc0b7fc7f4d6d07ae25f37d44fc38858.1753973161.git.oleksii.kurochko@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <5aa3beb7fc0b7fc7f4d6d07ae25f37d44fc38858.1753973161.git.oleksii.kurochko@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > --- a/xen/arch/riscv/include/asm/mm.h > +++ b/xen/arch/riscv/include/asm/mm.h > @@ -12,6 +12,7 @@ > #include > #include > > +#include > #include > #include > > @@ -247,9 +248,17 @@ static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long nr) > #define PGT_writable_page PG_mask(1, 1) /* has writable mappings? */ > #define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. */ > > -/* Count of uses of this frame as its current type. */ > -#define PGT_count_width PG_shift(2) > -#define PGT_count_mask ((1UL << PGT_count_width) - 1) > + /* 9-bit count of uses of this frame as its current type. */ Nit: Stray blank at start of line. > +#define PGT_count_mask PG_mask(0x3FF, 10) A 9-bit count corresponds to a mask of 0x1ff, doesn't it? With 0x3ff the count can spill over the type. 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Tue, 05 Aug 2025 07:15:29 -0700 (PDT) Date: Tue, 5 Aug 2025 16:15:28 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: dmkhn@proton.me Cc: xen-devel@lists.xenproject.org, alejandro.garciavallejo@amd.com, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com Subject: Re: [PATCH v13 2/3] tools/tests: introduce unit tests for domain ID allocator Message-ID: References: <20250730174042.1632011-1-dmukhin@ford.com> <20250730174042.1632011-3-dmukhin@ford.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250730174042.1632011-3-dmukhin@ford.com> On Wed, Jul 30, 2025 at 05:41:00PM +0000, dmkhn@proton.me wrote: > From: Denis Mukhin > > Introduce some basic infrastructure for doing domain ID allocation unit tests, > and add a few tests that ensure correctness of the domain ID allocator. > > Signed-off-by: Denis Mukhin > --- > Changes since v12: > - fixed Makefile > - dropped unused symbols/includes from the test harness header > - s/printk/printf/g in the test code > --- > tools/tests/Makefile | 2 +- > tools/tests/domid/.gitignore | 2 + > tools/tests/domid/Makefile | 48 ++++++++++ > tools/tests/domid/include/xen/domain.h | 126 +++++++++++++++++++++++++ > tools/tests/domid/test-domid.c | 78 +++++++++++++++ > 5 files changed, 255 insertions(+), 1 deletion(-) > create mode 100644 tools/tests/domid/.gitignore > create mode 100644 tools/tests/domid/Makefile > create mode 100644 tools/tests/domid/include/xen/domain.h > create mode 100644 tools/tests/domid/test-domid.c > > diff --git a/tools/tests/Makefile b/tools/tests/Makefile > index 36928676a666..ff1666425436 100644 > --- a/tools/tests/Makefile > +++ b/tools/tests/Makefile > @@ -1,7 +1,7 @@ > XEN_ROOT = $(CURDIR)/../.. > include $(XEN_ROOT)/tools/Rules.mk > > -SUBDIRS-y := > +SUBDIRS-y := domid > SUBDIRS-y += resource > SUBDIRS-$(CONFIG_X86) += cpu-policy > SUBDIRS-$(CONFIG_X86) += tsx > diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignore > new file mode 100644 > index 000000000000..70e306b3c074 > --- /dev/null > +++ b/tools/tests/domid/.gitignore > @@ -0,0 +1,2 @@ > +*.o > +test-domid > diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile > new file mode 100644 > index 000000000000..08fbad096aec > --- /dev/null > +++ b/tools/tests/domid/Makefile > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# > +# Unit tests for domain ID allocator. > +# > +# Copyright 2025 Ford Motor Company > + > +XEN_ROOT=$(CURDIR)/../../.. > +include $(XEN_ROOT)/tools/Rules.mk > + > +TESTS := test-domid > + > +vpath domid.c $(XEN_ROOT)/xen/common/ > + > +.PHONY: all > +all: $(TESTS) > + > +.PHONY: run > +run: $(TESTS) > + $(foreach t,$(TESTS),./$(t);) > + > +.PHONY: clean > +clean: > + $(RM) -- *.o $(TESTS) $(DEPS_RM) > + > +.PHONY: distclean > +distclean: clean > + $(RM) -- *~ > + > +.PHONY: install > +install: all > + $(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests > + $(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests > + > +.PHONY: uninstall > +uninstall: > + $(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid > + > +CFLAGS += -D__XEN_TOOLS__ > +CFLAGS += $(APPEND_CFLAGS) > +CFLAGS += $(CFLAGS_xeninclude) > +CFLAGS += -I./include/ > + > +LDFLAGS += $(APPEND_LDFLAGS) > + > +test-domid: domid.o test-domid.o > + $(CC) $^ -o $@ $(LDFLAGS) > + > +-include $(DEPS_INCLUDE) > diff --git a/tools/tests/domid/include/xen/domain.h b/tools/tests/domid/include/xen/domain.h > new file mode 100644 > index 000000000000..e5db0235445e > --- /dev/null > +++ b/tools/tests/domid/include/xen/domain.h > @@ -0,0 +1,126 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Unit test harness for domain ID allocator. > + * > + * Copyright 2025 Ford Motor Company > + */ > + > +#ifndef _TEST_HARNESS_ > +#define _TEST_HARNESS_ > + > +#include > +#include > +#include > +#include > + > +#include > + > +#define BUG_ON(x) assert(!(x)) > +#define ASSERT(x) assert(x) > + > +#define DOMID_FIRST_RESERVED (10) > +#define DOMID_INVALID (11) > + > +#define DEFINE_SPINLOCK(x) unsigned long *(x) I think this shouldn't be a pointer? As you otherwise trigger a NULL pointer dereference in the increases and decreases done below? > +#define spin_lock(x) ((*(x))++) > +#define spin_unlock(x) ((*(x))--) FWIW, I would use a plain bool: #define DEFINE_SPINLOCK(l) bool l #define spin_lock(l) (*(l) = true) #define spin_unlock(l) (*(l) = false) As you don't expect concurrency tests, you could even assert the lock is in the expected state before taking/releasing it. > + > +#define printk printf > + > +#define BITS_PER_LONG sizeof(unsigned long) That's BYTES_PER_LONG, BITS_PER_LONG would be (sizeof(unsigned long) * 8). > +#define BITS_PER_WORD (8U * BITS_PER_LONG) > +#define BITS_TO_LONGS(bits) \ > + (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG) > +#define DECLARE_BITMAP(name, bits) \ > + unsigned long name[BITS_TO_LONGS(bits)] > + > +static inline int __test_and_set_bit(unsigned int nr, unsigned long *addr) > +{ > + unsigned long mask = 1UL << (nr % BITS_PER_WORD); > + unsigned long *p = addr + (nr / BITS_PER_WORD); > + int old = (*p & mask) != 0; > + > + *p |= mask; > + > + return old; > +} > + > +static inline int __test_and_clear_bit(unsigned int nr, unsigned long *addr) > +{ > + unsigned long mask = 1UL << (nr % BITS_PER_WORD); > + unsigned long *p = addr + (nr / BITS_PER_WORD); > + int old = (*p & mask) != 0; > + > + *p &= ~mask; > + > + return old; > +} Could you somehow use the generic__test_and_set_bit() and generic__test_and_clear_bit() implementations in bitops.h? > + > +static inline void __set_bit(unsigned int nr, volatile unsigned long *addr) > +{ > + unsigned long mask = 1UL << (nr % BITS_PER_WORD); > + unsigned long *p = (unsigned long *)addr + (nr / BITS_PER_WORD); Why do you need the cast to drop the volatile here? > + > + *p |= mask; > +} I think you could possibly simplify to a single line: ((unsigned int *)addr)[nr >> 5] |= (1u << (nr & 31)); That's the implementation of constant_set_bit() in x86. > + > +static inline void __clear_bit(unsigned int nr, volatile unsigned long *addr) > +{ > + unsigned long mask = 1UL << (nr % BITS_PER_WORD); > + unsigned long *p = (unsigned long *)addr + (nr / BITS_PER_WORD); > + > + *p &= ~mask; > +} I don't think you need __clear_bit()? It's not used by domid.c AFAICT. > + > +static inline unsigned long find_next_zero_bit(const unsigned long *addr, > + unsigned long size, > + unsigned long offset) > +{ > + unsigned long idx = offset / BITS_PER_WORD; > + unsigned long bit = offset % BITS_PER_WORD; > + > + if (offset >= size) > + return size; > + > + while (offset < size) > + { > + unsigned long val = addr[idx] | (~0UL >> (BITS_PER_WORD - bit)); > + > + if (~val) > + { > + unsigned long pos = __builtin_ffsl(~val); > + > + if (pos > 0) > + { > + unsigned long rc = idx * BITS_PER_WORD + (pos - 1); > + > + if (rc < size) > + return rc; > + } > + } > + > + offset = (idx + 1) * BITS_PER_WORD; > + idx++; > + bit = 0; > + } > + > + return size; > +} Hm, you need a full find_next_zero_bit() implementation here because addr can be arbitrarily long. Could you somehow include xen/lib/find-next-bit.c and set the right defines so only the implementation of find_next_bit() is included? > + > +typedef bool spinlock_t; You want to put this ahead, so that DEFINE_SPINLOCK can be: #define DEFINE_SPINLOCK(l) spinlock_t l > +typedef uint16_t domid_t; > + > +/* See include/xen/domain.h */ > +extern domid_t domid_alloc(domid_t domid); > +extern void domid_free(domid_t domid); > + > +#endif /* _TEST_HARNESS_ */ > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-domid.c > new file mode 100644 > index 000000000000..d52eaf5f1f55 > --- /dev/null > +++ b/tools/tests/domid/test-domid.c > @@ -0,0 +1,78 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Unit tests for domain ID allocator. > + * > + * Copyright 2025 Ford Motor Company > + */ > + > +/* Local test include replicating hypervisor includes. */ > +#include I think this is a difficult to maintain position. Right now domid.c only includes xen/domain.h, so you can easily replace this in user-space. However if/when domid.c starts including more headers, replicating this in user-space will be cumbersome IMO. I would just guard the includes in domid.c with #ifdef __XEN__ for the preprocessor to remove them when domid.c is compiled as part of the unit-tests harness. I usually include a harness.h that contains the glue to make the imported code build (much like what you have placed in the test harness xen/domain.h header. > + > +int main(int argc, char **argv) > +{ > + domid_t expected, allocated; > + > + printf("DOMID_FIRST_RESERVED=%u DOMID_INVALID=%u\n", > + DOMID_FIRST_RESERVED, DOMID_INVALID); > + > + /* Test ID#0 cannot be allocated twice. */ > + allocated = domid_alloc(0); > + printf("TEST 1: expected %u allocated %u\n", 0, allocated); > + ASSERT(allocated == 0); > + allocated = domid_alloc(0); > + printf("TEST 1: expected %u allocated %u\n", DOMID_INVALID, allocated); > + ASSERT(allocated == DOMID_INVALID); > + > + /* Ensure ID is not allocated. */ > + domid_free(0); > + > + /* > + * Test that that two consecutive calls of domid_alloc(DOMID_INVALID) > + * will never return the same ID. > + * NB: ID#0 is reserved and shall not be allocated by > + * domid_alloc(DOMID_INVALID). > + */ > + for ( expected = 1; expected < DOMID_FIRST_RESERVED; expected++ ) > + { > + allocated = domid_alloc(DOMID_INVALID); > + printf("TEST 2: expected %u allocated %u\n", expected, allocated); > + ASSERT(allocated == expected); > + } > + for ( expected = 1; expected < DOMID_FIRST_RESERVED; expected++ ) > + { > + allocated = domid_alloc(DOMID_INVALID); > + printf("TEST 3: expected %u allocated %u\n", DOMID_INVALID, allocated); > + ASSERT(allocated == DOMID_INVALID); > + } > + > + /* Re-allocate first ID from [1..DOMID_FIRST_RESERVED - 1]. */ > + expected = 1; > + domid_free(1); > + allocated = domid_alloc(DOMID_INVALID); > + printf("TEST 4: expected %u allocated %u\n", expected, allocated); > + ASSERT(allocated == expected); > + > + /* Re-allocate last ID from [1..DOMID_FIRST_RESERVED - 1]. */ > + expected = DOMID_FIRST_RESERVED - 1; > + domid_free(DOMID_FIRST_RESERVED - 1); > + allocated = domid_alloc(DOMID_INVALID); > + printf("TEST 5: expected %u allocated %u\n", expected, allocated); > + ASSERT(allocated == expected); > + > + /* Allocate an invalid ID. */ > + expected = DOMID_INVALID; > + allocated = domid_alloc(DOMID_FIRST_RESERVED); > + printf("TEST 6: expected %u allocated %u\n", expected, allocated); > + ASSERT(allocated == expected); I would make this a bit less chatty maybe? I think you only need to print on errors, and you probably don't want to ASSERT() on failure, and rather try to finish all the tests in order to report multiple failures in a single run. Thanks, Roger. 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Other architectures use > > generic macros that map the non-xlate to the xlate variants to keep the > > previous behavior. > > > > Signed-off-by: Roger Pau Monné > > Once again: > Reviewed-by: Jan Beulich Thanks, I didn't carry your RB due to the changes requested by Andrew, that was a bit too much to carry a RB after those. Roger. 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Must be > > @@ -40,6 +41,12 @@ bool __mfn_valid(unsigned long mfn) > > > > #ifdef CONFIG_PDX_MASK_COMPRESSION > > invalid |= mfn & pfn_hole_mask; > > +#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) > > +{ > > + unsigned long base = pfn_bases[PFN_TBL_IDX(mfn)]; > > + > > + invalid |= mfn < base || mfn >= base + pdx_region_size; > > +} > > #endif > > Hmm, didn't notice this earlier on: Brace placement looks odd here. I think > they want to be indented by one level, as they aren't starting a function > body. Right, I can adjust. Since they are inside of the ifdef block it did look kind of OK to me, and avoided having to indent the content one extra level. > > @@ -294,7 +308,245 @@ void __init pfn_pdx_compression_reset(void) > > nr_ranges = 0; > > } > > > > -#endif /* CONFIG_PDX_COMPRESSION */ > > +#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) /* CONFIG_PDX_MASK_COMPRESSION */ > > + > > +unsigned int __ro_after_init pfn_index_shift; > > +unsigned int __ro_after_init pdx_index_shift; > > + > > +unsigned long __ro_after_init pfn_pdx_lookup[CONFIG_PDX_NR_LOOKUP]; > > +unsigned long __ro_after_init pdx_pfn_lookup[CONFIG_PDX_NR_LOOKUP]; > > +unsigned long __ro_after_init pfn_bases[CONFIG_PDX_NR_LOOKUP]; > > +unsigned long __ro_after_init pdx_region_size = ~0UL; > > For cache locality, might this last one better also move ahead of the arrays? Oh, yes, this was a late addition and I clearly didn't place enough attention when adding it. > > +bool pdx_is_region_compressible(paddr_t base, unsigned long npages) > > +{ > > + unsigned long pfn = PFN_DOWN(base); > > + unsigned long pfn_base = pfn_bases[PFN_TBL_IDX(pfn)]; > > + > > + return pfn >= pfn_base && > > + pfn + npages <= pfn_base + pdx_region_size; > > +} > > + > > +static int __init cf_check cmp_node(const void *a, const void *b) > > +{ > > + const struct pfn_range *l = a; > > + const struct pfn_range *r = b; > > + > > + if ( l->base_pfn > r->base_pfn ) > > + return 1; > > + if ( l->base_pfn < r->base_pfn ) > > + return -1; > > + > > + return 0; > > +} > > + > > +static void __init cf_check swp_node(void *a, void *b) > > +{ > > + SWAP(a, b); > > +} > > This hasn't changed from v3, and still looks wrong to me. Oh, I did recall a comment to that regard, but somehow forgot to apply it, I'm sorry, I've now fixed it. > > +bool __init pfn_pdx_compression_setup(paddr_t base) > > +{ > > + unsigned long mask = PFN_DOWN(pdx_init_mask(base)), idx_mask = 0; > > + unsigned long pages = 0; > > + unsigned int i; > > + > > + if ( !nr_ranges ) > > + { > > + printk(XENLOG_DEBUG "PFN compression disabled%s\n", > > + pdx_compress ? ": no ranges provided" : ""); > > + return false; > > + } > > + > > + if ( nr_ranges > ARRAY_SIZE(ranges) ) > > + { > > + printk(XENLOG_WARNING > > + "Too many PFN ranges (%u > %zu), not attempting PFN compression\n", > > + nr_ranges, ARRAY_SIZE(ranges)); > > + return false; > > + } > > + > > + /* Sort ranges by start address. */ > > + sort(ranges, nr_ranges, sizeof(*ranges), cmp_node, swp_node); > > + > > + for ( i = 0; i < nr_ranges; i++ ) > > + { > > + unsigned long start = ranges[i].base_pfn; > > + > > + /* > > + * Align range base to MAX_ORDER. This is required so the PDX offset > > + * for the bits below MAX_ORDER matches the MFN offset, and pages > > + * greater than the minimal order can be used to populate the > > + * directmap. > > + */ > > + ranges[i].base_pfn = start & ~((1UL << MAX_ORDER) - 1); > > + ranges[i].pages = start + ranges[i].pages - ranges[i].base_pfn; > > + > > + /* > > + * Only merge overlapped regions now, leave adjacent regions separated. > > + * They would be merged later if both use the same index into the > > + * lookup table. > > + */ > > + if ( !i || > > + ranges[i].base_pfn >= > > + (ranges[i - 1].base_pfn + ranges[i - 1].pages) ) > > + { > > + mask |= pdx_region_mask(ranges[i].base_pfn, ranges[i].pages); > > + continue; > > + } > > + > > + ranges[i - 1].pages = ranges[i].base_pfn + ranges[i].pages - > > + ranges[i - 1].base_pfn; > > + > > + if ( i + 1 < nr_ranges ) > > + memmove(&ranges[i], &ranges[i + 1], > > + (nr_ranges - (i + 1)) * sizeof(ranges[0])); > > + else /* last range */ > > + mask |= pdx_region_mask(ranges[i].base_pfn, ranges[i].pages); > > + nr_ranges--; > > + i--; > > + } > > + > > + /* > > + * Populate a mask with the non-equal bits of the different ranges, do this > > + * to calculate the maximum PFN shift to use as the lookup table index. > > + */ > > + for ( i = 0; i < nr_ranges; i++ ) > > + for ( unsigned int j = 0; j < nr_ranges; j++ ) > > + idx_mask |= (ranges[i].base_pfn & ~mask) ^ > > + (ranges[j].base_pfn & ~mask); > > "mask" is loop invariant - can't the AND-ing be pulled out, after the loop? I've applied both of the above, thanks for the help. Regards, Roger. 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I'd like to ask that you avoid fuzzy terminology like this one. Afaict > you mean [start, start + size). Help yourself and future readers by then > also saying it exactly like this. (Happy to make a respective edit while > committing.) I just tried the following wording in SBI spec. I agree that using [start, start+size) is clearer as each time I'm going to check SBI code to verify if 'start+size' is included or not. It would be happy if you could update this part of commit message during commit. > >> + * Returns 0 if IPI was sent to all the targeted harts successfully >> + * or negative value if start_addr or size is not valid. > This similarly is ambiguous: The union of the success case stated and the > error case stated isn't obviously all possible states. The success > statement in particular alludes to the possibility of an IPI not actually > reaching its target. The same as above this is what SBI spec. tells. I've not checked SBI code deeply, but it seems like the code is waiting while IPI will be reached as looking at the code: /** * As this this function only handlers scalar values of hart mask, it must be * set to all online harts if the intention is to send IPIs to all the harts. * If hmask is zero, no IPIs will be sent. */ int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data) { ... /* Send IPIs */ do { retry_needed = false; sbi_hartmask_for_each_hart(i, &target_mask) { rc = sbi_ipi_send(scratch, i, event, data); if (rc == SBI_IPI_UPDATE_RETRY) retry_needed = true; else sbi_hartmask_clear_hart(i, &target_mask); } } while (retry_needed); /* Sync IPIs */ sbi_ipi_sync(scratch, event); return 0; } and static int sbi_ipi_sync(struct sbi_scratch *scratch, u32 event) { const struct sbi_ipi_event_ops *ipi_ops; if ((SBI_IPI_EVENT_MAX <= event) || !ipi_ops_array[event]) return SBI_EINVAL; ipi_ops = ipi_ops_array[event]; if (ipi_ops->sync) ipi_ops->sync(scratch); return 0; } which calls: static void tlb_sync(struct sbi_scratch *scratch) { atomic_t *tlb_sync = sbi_scratch_offset_ptr(scratch, tlb_sync_off); while (atomic_read(tlb_sync) > 0) { /* * While we are waiting for remote hart to set the sync, * consume fifo requests to avoid deadlock. */ tlb_process_once(scratch); } return; } > >> + * The remote fence operation applies to the entire address space if either: >> + * - start_addr and size are both 0, or >> + * - size is equal to 2^XLEN-1. > Whose XLEN is this? The guest's? The host's? (I assume the latter, but it's > not unambiguous, unless there's specific terminology that I'm unaware of, > yet which would make this unambiguous.) RISC-V spec quite mixes the terminology (3.1.6.2. Base ISA Control in mstatus Register) around XLEN: For RV64 harts, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. The encoding of these fields is the same as the MXL field of misa, shown in Table 9. The effective XLEN in S-mode and U-mode are termed SXLEN and UXLEN, respectively Basically, RISC-V privileged architecture defines different XLEN values for various privilege modes:  - MXLEN for Machine mode - SXLEN for Supervisor mode.  - HSXLEN for Hypervisor-Supervisor mode.  - VSXLEN for Virtual Supervisor mode. Considering that SBI is an API that is provided for S-mode I expect that XLEN = SXLEN in this case, but SBI spec. is using just XLEN. ~ Oleksii --------------kdt00xxFjWrjsxUeIoZikbxX Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit


    On 8/4/25 3:52 PM, Jan Beulich wrote:
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    Instruct the remote harts to execute one or more HFENCE.GVMA instructions,
covering the range of guest physical addresses between start_addr and
start_addr + size for all VMIDs.

The remote fence operation applies to the entire address space if either:
 - start_addr and size are both 0, or
 - size is equal to 2^XLEN-1.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

    Acked-by: Jan Beulich <jbeulich@suse.com>

However, ...


    --- a/xen/arch/riscv/include/asm/sbi.h
+++ b/xen/arch/riscv/include/asm/sbi.h
@@ -89,6 +89,25 @@ bool sbi_has_rfence(void);
 int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start,
                           size_t size);
 
+/*
+ * Instructs the remote harts to execute one or more HFENCE.GVMA
+ * instructions, covering the range of guest physical addresses
+ * between start_addr and start_addr + size for all VMIDs.

    ... I'd like to ask that you avoid fuzzy terminology like this one. Afaict
you mean [start, start + size). Help yourself and future readers by then
also saying it exactly like this. (Happy to make a respective edit while
committing.)
    I just tried the following wording in SBI spec.

I agree that using [start, start+size) is clearer as each time I'm going
to check SBI code to verify if 'start+size' is included or not.

It would be happy if you could update this part of commit message during
commit.


    

    + * Returns 0 if IPI was sent to all the targeted harts successfully
+ * or negative value if start_addr or size is not valid.

    This similarly is ambiguous: The union of the success case stated and the
error case stated isn't obviously all possible states. The success
statement in particular alludes to the possibility of an IPI not actually
reaching its target.
    The same as above this is what SBI spec. tells.

I've not checked SBI code deeply, but it seems like the code is waiting while
IPI will be reached as looking at the code:
	/**
	 * As this this function only handlers scalar values of hart mask, it must be
	 * set to all online harts if the intention is to send IPIs to all the harts.
	 * If hmask is zero, no IPIs will be sent.
	 */
	int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data)
	{
                ...
	
		/* Send IPIs */
		do {
			retry_needed = false;
			sbi_hartmask_for_each_hart(i, &target_mask) {
				rc = sbi_ipi_send(scratch, i, event, data);
				if (rc == SBI_IPI_UPDATE_RETRY)
					retry_needed = true;
				else
					sbi_hartmask_clear_hart(i, &target_mask);
			}
		} while (retry_needed);
	
		/* Sync IPIs */
		sbi_ipi_sync(scratch, event);
	
		return 0;
	}
and
	static int sbi_ipi_sync(struct sbi_scratch *scratch, u32 event)
	{
		const struct sbi_ipi_event_ops *ipi_ops;
	
		if ((SBI_IPI_EVENT_MAX <= event) ||
		    !ipi_ops_array[event])
			return SBI_EINVAL;
		ipi_ops = ipi_ops_array[event];
	
		if (ipi_ops->sync)
			ipi_ops->sync(scratch);
	
		return 0;
	}
which calls:
	static void tlb_sync(struct sbi_scratch *scratch)
	{
		atomic_t *tlb_sync =
				sbi_scratch_offset_ptr(scratch, tlb_sync_off);
	
		while (atomic_read(tlb_sync) > 0) {
			/*
			 * While we are waiting for remote hart to set the sync,
			 * consume fifo requests to avoid deadlock.
			 */
			tlb_process_once(scratch);
		}
	
		return;
	}


    

    + * The remote fence operation applies to the entire address space if either:
+ *  - start_addr and size are both 0, or
+ *  - size is equal to 2^XLEN-1.

    Whose XLEN is this? The guest's? The host's? (I assume the latter, but it's
not unambiguous, unless there's specific terminology that I'm unaware of,
yet which would make this unambiguous.)
    RISC-V spec quite mixes the terminology (3.1.6.2. Base ISA Control in mstatus Register)
around XLEN:
  For RV64 harts, the SXL and UXL fields are WARL fields that control the value
  of XLEN for S-mode and U-mode, respectively. The encoding of these fields is
  the same as the MXL field of misa, shown in Table 9. The effective XLEN in
  S-mode and U-mode are termed SXLEN and UXLEN, respectively

Basically, RISC-V privileged architecture defines different XLEN values for
various privilege modes:
 - MXLEN for Machine mode
 - SXLEN for Supervisor mode.
 - HSXLEN for Hypervisor-Supervisor mode.
 - VSXLEN for Virtual Supervisor mode.

Considering that SBI is an API that is provided for S-mode I expect that XLEN = SXLEN
in this case, but SBI spec. is using just XLEN.

~ Oleksii
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I would happy if you could do that during merge. Thanks. ~ Oleksii --------------Tw0jcxWjp0ZzjXU7Gtfn0Rly Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit


    On 8/4/25 3:55 PM, Jan Beulich wrote:
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    It instructs the remote harts to execute one or more HFENCE.GVMA instructions
by making an SBI call, covering the range of guest physical addresses between
start_addr and start_addr + size only for the given VMID.

The remote fence operation applies to the entire address space if either:
  - start_addr and size are both 0, or
  - size is equal to 2^XLEN-1.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

    Acked-by: Jan Beulich <jbeulich@suse.com>
with perhaps a similar on-commit edit as suggested for patch 1.
    I would happy if you could do that during merge. Thanks.

~ Oleksii
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Tue, 05 Aug 2025 08:01:33 -0700 (PDT) Message-ID: <55a08131-169d-49b3-a499-d7057e7affac@suse.com> Date: Tue, 5 Aug 2025 17:01:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 01/20] xen/riscv: implement sbi_remote_hfence_gvma() To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: <829f9477-2b18-47f0-8fb3-57bffa8d133d@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05.08.2025 16:45, Oleksii Kurochko wrote: > On 8/4/25 3:52 PM, Jan Beulich wrote: >> On 31.07.2025 17:58, Oleksii Kurochko wrote: >>> + * Returns 0 if IPI was sent to all the targeted harts successfully >>> + * or negative value if start_addr or size is not valid. >> This similarly is ambiguous: The union of the success case stated and the >> error case stated isn't obviously all possible states. The success >> statement in particular alludes to the possibility of an IPI not actually >> reaching its target. > > The same as above this is what SBI spec. tells. > > I've not checked SBI code deeply, but it seems like the code is waiting while > IPI will be reached as looking at the code: > /** > * As this this function only handlers scalar values of hart mask, it must be > * set to all online harts if the intention is to send IPIs to all the harts. > * If hmask is zero, no IPIs will be sent. > */ > int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data) > { > ... > > /* Send IPIs */ > do { > retry_needed = false; > sbi_hartmask_for_each_hart(i, &target_mask) { > rc = sbi_ipi_send(scratch, i, event, data); > if (rc == SBI_IPI_UPDATE_RETRY) > retry_needed = true; > else > sbi_hartmask_clear_hart(i, &target_mask); > } > } while (retry_needed); > > /* Sync IPIs */ > sbi_ipi_sync(scratch, event); > > return 0; > } > and > static int sbi_ipi_sync(struct sbi_scratch *scratch, u32 event) > { > const struct sbi_ipi_event_ops *ipi_ops; > > if ((SBI_IPI_EVENT_MAX <= event) || > !ipi_ops_array[event]) > return SBI_EINVAL; > ipi_ops = ipi_ops_array[event]; > > if (ipi_ops->sync) > ipi_ops->sync(scratch); > > return 0; > } > which calls: > static void tlb_sync(struct sbi_scratch *scratch) > { > atomic_t *tlb_sync = > sbi_scratch_offset_ptr(scratch, tlb_sync_off); > > while (atomic_read(tlb_sync) > 0) { > /* > * While we are waiting for remote hart to set the sync, > * consume fifo requests to avoid deadlock. > */ > tlb_process_once(scratch); > } > > return; > } I'll leave that comment as-is then, even if I'm not really happy with it. >>> + * The remote fence operation applies to the entire address space if either: >>> + * - start_addr and size are both 0, or >>> + * - size is equal to 2^XLEN-1. >> Whose XLEN is this? The guest's? The host's? (I assume the latter, but it's >> not unambiguous, unless there's specific terminology that I'm unaware of, >> yet which would make this unambiguous.) > > RISC-V spec quite mixes the terminology (3.1.6.2. Base ISA Control in mstatus Register) > around XLEN: > For RV64 harts, the SXL and UXL fields are WARL fields that control the value > of XLEN for S-mode and U-mode, respectively. The encoding of these fields is > the same as the MXL field of misa, shown in Table 9. The effective XLEN in > S-mode and U-mode are termed SXLEN and UXLEN, respectively > > Basically, RISC-V privileged architecture defines different XLEN values for > various privilege modes: >  - MXLEN for Machine mode > - SXLEN for Supervisor mode. >  - HSXLEN for Hypervisor-Supervisor mode. >  - VSXLEN for Virtual Supervisor mode. > > Considering that SBI is an API that is provided for S-mode I expect that XLEN = SXLEN > in this case, but SBI spec. is using just XLEN. Very helpful. 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Tue, 05 Aug 2025 08:02:45 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 17:02:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/8] pdx: allow per-arch optimization of PDX conversion helpers To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , Stefano Stabellini , xen-devel@lists.xenproject.org References: <20250805095257.74975-1-roger.pau@citrix.com> <20250805095257.74975-5-roger.pau@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05.08.2025 16:20, Roger Pau Monné wrote: > On Tue, Aug 05, 2025 at 02:11:22PM +0200, Jan Beulich wrote: >> On 05.08.2025 11:52, Roger Pau Monne wrote: >>> There are four performance critical PDX conversion helpers that do the PFN >>> to/from PDX and the physical addresses to/from directmap offsets >>> translations. >>> >>> In the absence of an active PDX compression, those functions would still do >>> the calculations needed, just to return the same input value as no >>> translation is in place and hence PFN and PDX spaces are identity mapped. >>> >>> To reduce the overhead of having to do the pointless calculations allow >>> architectures to implement the translation helpers in a per-arch header. >>> Rename the existing conversion functions to add a trailing _xlate suffix, >>> so that the per-arch headers can define the non suffixed versions. >>> >>> Currently only x86 implements meaningful custom handlers to short circuit >>> the translation when not active, using asm goto. Other architectures use >>> generic macros that map the non-xlate to the xlate variants to keep the >>> previous behavior. >>> >>> Signed-off-by: Roger Pau Monné >> >> Once again: >> Reviewed-by: Jan Beulich > > Thanks, I didn't carry your RB due to the changes requested by Andrew, > that was a bit too much to carry a RB after those. Of course, and I didn't mean to suggest you should have kept it. All I wanted to indicate is that I'm as okay withe change as I was before. Jan From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:20:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:20:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070597.1434223 (Exim 4.92) (envelope-from ) id 1ujJSh-0001gG-OC; Tue, 05 Aug 2025 15:20:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070597.1434223; Tue, 05 Aug 2025 15:20:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSh-0001eN-Eu; Tue, 05 Aug 2025 15:20:23 +0000 Received: by outflank-mailman (input) for mailman id 1070597; Tue, 05 Aug 2025 15:07:22 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJG6-0007M7-QP for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 15:07:22 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-flk1.inumbo.com (Halon) with ESMTP id e25cef63-720d-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 17:07:20 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2ABA12BCE; Tue, 5 Aug 2025 08:07:12 -0700 (PDT) Received: from [10.1.29.177] (e137867.arm.com [10.1.29.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E03633F673; Tue, 5 Aug 2025 08:07:15 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e25cef63-720d-11f0-b898-0df219b8e170 Message-ID: Date: Tue, 5 Aug 2025 16:07:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH -next v7 6/7] arm64: entry: Move arm64_preempt_schedule_irq() into __exit_to_kernel_mode() To: Jinjie Ruan References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-7-ruanjinjie@huawei.com> From: Ada Couprie Diaz Cc: mbenes@suse.cz, xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, leitao@debian.org, ardb@kernel.org, liaochang1@huawei.com, kristina.martsenko@arm.com, anshuman.khandual@arm.com, chenl311@chinatelecom.cn, akpm@linux-foundation.org, ryan.roberts@arm.com, broonie@kernel.org, puranjay@kernel.org, mark.rutland@arm.com, sstabellini@kernel.org, oleg@redhat.com, will@kernel.org, catalin.marinas@arm.com, Ada Couprie Diaz Content-Language: en-US Organization: Arm Ltd. In-Reply-To: <20250729015456.3411143-7-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 29/07/2025 02:54, Jinjie Ruan wrote: > The arm64 entry code only preempts a kernel context upon a return from > a regular IRQ exception. The generic entry code may preempt a kernel > context for any exception return where irqentry_exit() is used, and so > may preempt other exceptions such as faults. > > In preparation for moving arm64 over to the generic entry code, align > arm64 with the generic behaviour by calling > arm64_preempt_schedule_irq() from exit_to_kernel_mode(). To make this > possible, arm64_preempt_schedule_irq() > and dynamic/raw_irqentry_exit_cond_resched() are moved earlier in > the file, with no changes. > > As Mark pointed out, this change will have the following 2 key impact: > > - " We'll preempt even without taking a "real" interrupt. That > shouldn't result in preemption that wasn't possible before, > but it does change the probability of preempting at certain points, > and might have a performance impact, so probably warrants a > benchmark." > > - " We will not preempt when taking interrupts from a region of kernel > code where IRQs are enabled but RCU is not watching, matching the > behaviour of the generic entry code. > > This has the potential to introduce livelock if we can ever have a > screaming interrupt in such a region, so we'll need to go figure out > whether that's actually a problem. > > Having this as a separate patch will make it easier to test/bisect > for that specifically." > > Suggested-by: Mark Rutland > Signed-off-by: Jinjie Ruan > --- Reviewed-by: Ada Couprie Diaz From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:20:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:20:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070587.1434189 (Exim 4.92) (envelope-from ) id 1ujJSg-0001CL-5a; Tue, 05 Aug 2025 15:20:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070587.1434189; Tue, 05 Aug 2025 15:20:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSg-0001CE-2y; Tue, 05 Aug 2025 15:20:22 +0000 Received: by outflank-mailman (input) for mailman id 1070587; Tue, 05 Aug 2025 15:05:59 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJEl-0007Ir-Dk for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 15:05:59 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id b060329f-720d-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 17:05:57 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4C11B1424; Tue, 5 Aug 2025 08:05:48 -0700 (PDT) Received: from [10.1.29.177] (e137867.arm.com [10.1.29.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D55FA3F673; Tue, 5 Aug 2025 08:05:51 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b060329f-720d-11f0-a321-13f23c93f187 Message-ID: Date: Tue, 5 Aug 2025 16:05:45 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH -next v7 1/7] arm64: ptrace: Replace interrupts_enabled() with regs_irqs_disabled() To: Jinjie Ruan References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-2-ruanjinjie@huawei.com> From: Ada Couprie Diaz Cc: Ada Couprie Diaz , catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com, sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com, akpm@linux-foundation.org, chenl311@chinatelecom.cn, anshuman.khandual@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Content-Language: en-US Organization: Arm Ltd. In-Reply-To: <20250729015456.3411143-2-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 29/07/2025 02:54, Jinjie Ruan wrote: > The generic entry code expects architecture code to provide > regs_irqs_disabled(regs) function, but arm64 does not have this and > provides inerrupts_enabled(regs), which has the opposite polarity. Nit: "interrupts_enabled(regs)" > In preparation for moving arm64 over to the generic entry code, > relace arm64's interrupts_enabled() with regs_irqs_disabled() and > update its callers under arch/arm64. > > For the moment, a definition of interrupts_enabled() is provided for > the GICv3 driver. Once arch/arm implement regs_irqs_disabled(), this > can be removed. > > Delete the fast_interrupts_enabled() macro as it is unused and we > don't want any new users to show up. > > No functional changes. > > Acked-by: Mark Rutland > Suggested-by: Mark Rutland > Signed-off-by: Jinjie Ruan > --- Otherwise looks good to me ! Reviewed-by: Ada Couprie Diaz From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:20:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:20:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070599.1434235 (Exim 4.92) (envelope-from ) id 1ujJSi-0001uY-Cw; Tue, 05 Aug 2025 15:20:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070599.1434235; Tue, 05 Aug 2025 15:20:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSh-0001sy-V4; Tue, 05 Aug 2025 15:20:23 +0000 Received: by outflank-mailman (input) for mailman id 1070599; Tue, 05 Aug 2025 15:07:49 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJGX-0007Mk-5a for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 15:07:49 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id f26ea8ea-720d-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 17:07:47 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 18C202BF2; Tue, 5 Aug 2025 08:07:39 -0700 (PDT) Received: from [10.1.29.177] (e137867.arm.com [10.1.29.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BAE723F673; Tue, 5 Aug 2025 08:07:42 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f26ea8ea-720d-11f0-a321-13f23c93f187 Message-ID: Date: Tue, 5 Aug 2025 16:07:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH -next v7 7/7] arm64: entry: Switch to generic IRQ entry To: Jinjie Ruan References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-8-ruanjinjie@huawei.com> From: Ada Couprie Diaz Cc: Ada Couprie Diaz , catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com, sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com, akpm@linux-foundation.org, chenl311@chinatelecom.cn, anshuman.khandual@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Content-Language: en-US Organization: Arm Ltd. In-Reply-To: <20250729015456.3411143-8-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Jinjie, The code changes look good to me, just a small missing clean up I believe. On 29/07/2025 02:54, Jinjie Ruan wrote: > Currently, x86, Riscv, Loongarch use the generic entry. Convert arm64 > to use the generic entry infrastructure from kernel/entry/*. > The generic entry makes maintainers' work easier and codes > more elegant. > > Switch arm64 to generic IRQ entry first, which removed duplicate 100+ > LOC. The next patch serise will switch to generic entry completely later. > Switch to generic entry in two steps according to Mark's suggestion > will make it easier to review. I think the commit message could be clearer, especially since now this series only moves arm64 to generic IRQ entry and not the complete generic entry. What do you think of something like below ? It repeats a bit less and I think it helps understanding what is going on in this specific commit, as you already have details on the larger plans in the cover. Currently, x86, Riscv and Loongarch use the generic entry code, which makes maintainer's work easier and code more elegant. Start converting arm64 to use the generic entry infrastructure from kernel/entry/* by switching it to generic IRQ entry, which removes 100+ lines of duplicate code. arm64 will completely switch to generic entry in a later series. > The changes are below: > - Remove *enter_from/exit_to_kernel_mode(), and wrap with generic > irqentry_enter/exit(). Also remove *enter_from/exit_to_user_mode(), > and wrap with generic enter_from/exit_to_user_mode() because they > are exactly the same so far. Nit : "so far" can be removed > - Remove arm64_enter/exit_nmi() and use generic irqentry_nmi_enter/exit() > because they're exactly the same, so the temporary arm64 version > irqentry_state can also be removed. > > - Remove PREEMPT_DYNAMIC code, as generic entry do the same thing > if arm64 implement arch_irqentry_exit_need_resched(). This feels unrelated, given that the part that needs `arch_irqentry_exit_need_resched()` is called whether or not PREEMPT_DYNAMIC is enabled ? Given my comments on patch 5, I feel that the commit message should mention explicitly the implementation of `arch_irqentry_exit_need_resched()` and why, even though it was already mentioned in patch 5. (This is what I was referencing in patch 5 : as I feel it's useful to mention again the reasons when implementing it, it doesn't feel too out of place to introduce the generic part at the same time. But again, I might be wrong here.) Then you can have another point explaining that `raw_irqentry_exit_cond_resched()` and the PREEMPT_DYNAMIC code is removed because they are identical to the generic entry code, similarly to your other points. > Tested ok with following test cases on Qemu virt platform: > - Perf tests. > - Different `dynamic preempt` mode switch. > - Pseudo NMI tests. > - Stress-ng CPU stress test. > - MTE test case in Documentation/arch/arm64/memory-tagging-extension.rst > and all test cases in tools/testing/selftests/arm64/mte/*. Nit : I'm not sure if the commit message is the best place for this, given you already gave some details in the cover ? But I don't have much experience here, so I'll leave it up to you and others ! > Suggested-by: Mark Rutland > Signed-off-by: Jinjie Ruan > --- > [...] > diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c > index db3f972f8cd9..1110eeb21f57 100644 > --- a/arch/arm64/kernel/signal.c > +++ b/arch/arm64/kernel/signal.c > @@ -9,6 +9,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -1576,7 +1577,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) > * the kernel can handle, and then we build all the user-level signal handling > * stack-frames in one go after that. > */ > -void do_signal(struct pt_regs *regs) > +void arch_do_signal_or_restart(struct pt_regs *regs) Given that `do_signal(struct pt_regs *regs)` is defined in `arch/arm64/include/asm/exception.h`, and that there remains no users of `do_signal()`, I think it should be removed there. Thanks, Ada From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:20:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:20:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070595.1434215 (Exim 4.92) (envelope-from ) id 1ujJSh-0001bP-CC; Tue, 05 Aug 2025 15:20:23 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070595.1434215; Tue, 05 Aug 2025 15:20:23 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSh-0001ZB-4O; Tue, 05 Aug 2025 15:20:23 +0000 Received: by outflank-mailman (input) for mailman id 1070595; Tue, 05 Aug 2025 15:07:06 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJFq-0007Kl-4q for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 15:07:06 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id d9080db7-720d-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 17:07:05 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 77E4C2BCE; Tue, 5 Aug 2025 08:06:56 -0700 (PDT) Received: from [10.1.29.177] (e137867.arm.com [10.1.29.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 423853F673; Tue, 5 Aug 2025 08:07:00 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d9080db7-720d-11f0-a321-13f23c93f187 Message-ID: <44fd646c-4e31-4ca6-9e22-f715ad19e0d7@arm.com> Date: Tue, 5 Aug 2025 16:06:58 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH -next v7 5/7] arm64: entry: Refactor preempt_schedule_irq() check code To: Jinjie Ruan References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-6-ruanjinjie@huawei.com> From: Ada Couprie Diaz Cc: Ada Couprie Diaz , catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com, sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com, akpm@linux-foundation.org, chenl311@chinatelecom.cn, anshuman.khandual@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Content-Language: en-US Organization: Arm Ltd. In-Reply-To: <20250729015456.3411143-6-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Jinjie, On 29/07/2025 02:54, Jinjie Ruan wrote: > ARM64 requires an additional check whether to reschedule on return > from interrupt. So add arch_irqentry_exit_need_resched() as the default > NOP implementation and hook it up into the need_resched() condition in > raw_irqentry_exit_cond_resched(). This allows ARM64 to implement > the architecture specific version for switching over to > the generic entry code. I was a bit confused by this, as I didn't see the link with the generic entry given you implement `raw_irqentry_exit_cond_resched()` in arch/arm64 as well in this patch : I expected the arm64 implementation to be added. I share more thoughts below. What do you think about something along those lines ? Compared to the generic entry code, arm64 does additional checks when deciding to reschedule on return from an interrupt. Introduce arch_irqentry_exit_need_resched() in the need_resched() condition of the generic raw_irqentry_exit_cond_resched(), with a NOP default. This will allow arm64 to implement its architecture specific checks when switching over to the generic entry code. > [...] > diff --git a/kernel/entry/common.c b/kernel/entry/common.c > index b82032777310..4aa9656fa1b4 100644 > --- a/kernel/entry/common.c > +++ b/kernel/entry/common.c > @@ -142,6 +142,20 @@ noinstr irqentry_state_t irqentry_enter(struct pt_regs *regs) > return ret; > } > > +/** > + * arch_irqentry_exit_need_resched - Architecture specific need resched function > + * > + * Invoked from raw_irqentry_exit_cond_resched() to check if need resched. Very nit : "to check if resched is needed." ? > + * Defaults return true. > + * > + * The main purpose is to permit arch to skip preempt a task from an IRQ. If feel that "to avoid preemption of a task" instead of "to skip preempt a task" would make this much clearer, what do you think ? > + */ > +static inline bool arch_irqentry_exit_need_resched(void); > + > +#ifndef arch_irqentry_exit_need_resched > +static inline bool arch_irqentry_exit_need_resched(void) { return true; } > +#endif > + I've had some trouble reviewing this patch : on the one hand because I didn't notice `arch_irqentry_exit_need_resched()` was added in the common entry code, which is on me ! On the other hand, I felt that the patch itself was a bit disconnected : we add `arch_irqentry_exit_need_resched()` in the common entry code, with a default NOP, but in the same function we add to arm64, while mentioning that this is for arm64's additional checks, which we only implement in patch 7. Would it make sense to move the `arch_irqentry_exit_need_resched()` part of the patch to patch 7, so that the introduction and arch-specific implementation appear together ? To me it seems easier to wrap my head around, as it would look like "Move arm64 to generic entry, but it does additional checks : add a new arch-specific function controlling re-scheduling, defaulting to true, and implement it for arm64". I feel it could help making patch 7's commit message clearer as well. From what I gathered on the archive `arch_irqentry_exit_need_resched()` being added here was suggested previously, so others might not have the same opinion. Maybe improving the commit message and comment for this would be enough as well, as per my suggestions above. Otherwise the changes make sense and I don't see any functional issues ! Thanks, Ada From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:20:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:20:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070601.1434242 (Exim 4.92) (envelope-from ) id 1ujJSi-000236-Mo; Tue, 05 Aug 2025 15:20:24 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070601.1434242; Tue, 05 Aug 2025 15:20:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSi-000212-Dt; Tue, 05 Aug 2025 15:20:24 +0000 Received: by outflank-mailman (input) for mailman id 1070601; Tue, 05 Aug 2025 15:08:34 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJHG-0007Nd-3a for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 15:08:34 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-flk1.inumbo.com (Halon) with ESMTP id 0cd5b606-720e-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 17:08:32 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6C1652BCE; Tue, 5 Aug 2025 08:08:23 -0700 (PDT) Received: from [10.1.29.177] (e137867.arm.com [10.1.29.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A5AA3F673; Tue, 5 Aug 2025 08:08:26 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0cd5b606-720e-11f0-b898-0df219b8e170 Message-ID: <6bd09b5b-9830-42b4-ad9e-9ad1e153e564@arm.com> Date: Tue, 5 Aug 2025 16:08:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH -next v7 0/7] arm64: entry: Convert to generic irq entry To: Jinjie Ruan References: <20250729015456.3411143-1-ruanjinjie@huawei.com> From: Ada Couprie Diaz Cc: Ada Couprie Diaz , catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com, sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com, akpm@linux-foundation.org, chenl311@chinatelecom.cn, anshuman.khandual@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Content-Language: en-US Organization: Arm Ltd. In-Reply-To: <20250729015456.3411143-1-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Jinjie, On 29/07/2025 02:54, Jinjie Ruan wrote: > Since commit a70e9f647f50 ("entry: Split generic entry into generic > exception and syscall entry") split the generic entry into generic irq > entry and generic syscall entry, it is time to convert arm64 to use > the generic irq entry. And ARM64 will be completely converted to generic > entry in the upcoming patch series. Note : I had to manually cherry-pick a70e9f647f50 when pulling the series on top of the Linux Arm Kernel for-next/core branch, but there might be something I'm missing here. > > The main convert steps are as follows: > - Split generic entry into generic irq entry and generic syscall to > make the single patch more concentrated in switching to one thing. > - Make arm64 easier to use irqentry_enter/exit(). > - Make arm64 closer to the PREEMPT_DYNAMIC code of generic entry. > - Switch to generic irq entry. I reviewed the whole series and as expected it looks good ! Just a few nits here and there and some clarifications that I think could be useful. I'm not sure about the generic implementation of `arch_irqentry_exit_need_resched()` in patch 5, I would be tempted to move it to patch 7. I detail my thoughts more on the relevant patches, but I might be wrong and that feels like details : I don't think the code itself has issues. > It was tested ok with following test cases on QEMU virt platform: > - Perf tests. > - Different `dynamic preempt` mode switch. > - Pseudo NMI tests. > - Stress-ng CPU stress test. > - MTE test case in Documentation/arch/arm64/memory-tagging-extension.rst > and all test cases in tools/testing/selftests/arm64/mte/*. > > The test QEMU configuration is as follows: > > qemu-system-aarch64 \ > -M virt,gic-version=3,virtualization=on,mte=on \ > -cpu max,pauth-impdef=on \ > -kernel Image \ > -smp 8,sockets=1,cores=4,threads=2 \ > -m 512m \ > -nographic \ > -no-reboot \ > -device virtio-rng-pci \ > -append "root=/dev/vda rw console=ttyAMA0 kgdboc=ttyAMA0,115200 \ > earlycon preempt=voluntary irqchip.gicv3_pseudo_nmi=1" \ > -drive if=none,file=images/rootfs.ext4,format=raw,id=hd0 \ > -device virtio-blk-device,drive=hd0 \ > I'll spend some time testing the series now, specifically given patch 6's changes, but other than that everything I saw made sense and didn't look like it would be of concern to me. Thanks, Ada From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:20:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:20:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070591.1434201 (Exim 4.92) (envelope-from ) id 1ujJSg-0001He-MV; Tue, 05 Aug 2025 15:20:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070591.1434201; Tue, 05 Aug 2025 15:20:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSg-0001GJ-Fb; Tue, 05 Aug 2025 15:20:22 +0000 Received: by outflank-mailman (input) for mailman id 1070591; Tue, 05 Aug 2025 15:06:31 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJFH-0007Ji-SI for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 15:06:31 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-flk1.inumbo.com (Halon) with ESMTP id c42e6e49-720d-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 17:06:30 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 74E5E2BCC; Tue, 5 Aug 2025 08:06:21 -0700 (PDT) Received: from [10.1.29.177] (e137867.arm.com [10.1.29.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CBD3F3F673; Tue, 5 Aug 2025 08:06:25 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c42e6e49-720d-11f0-b898-0df219b8e170 Message-ID: Date: Tue, 5 Aug 2025 16:06:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH -next v7 3/7] arm64: entry: Rework arm64_preempt_schedule_irq() To: Jinjie Ruan References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-4-ruanjinjie@huawei.com> From: Ada Couprie Diaz Cc: Ada Couprie Diaz , catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com, sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com, akpm@linux-foundation.org, chenl311@chinatelecom.cn, anshuman.khandual@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Content-Language: en-US Organization: Arm Ltd. In-Reply-To: <20250729015456.3411143-4-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 29/07/2025 02:54, Jinjie Ruan wrote: > The generic entry code has the form: > > | raw_irqentry_exit_cond_resched() > | { > | if (!preempt_count()) { > | ... > | if (need_resched()) > | preempt_schedule_irq(); > | } > | } > > In preparation for moving arm64 over to the generic entry code, align > the structure of the arm64 code with raw_irqentry_exit_cond_resched() from > the generic entry code. > > Signed-off-by: Jinjie Ruan > --- Reviewed-by: Ada Couprie Diaz From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:20:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:20:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070593.1434206 (Exim 4.92) (envelope-from ) id 1ujJSg-0001Qk-U0; Tue, 05 Aug 2025 15:20:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070593.1434206; Tue, 05 Aug 2025 15:20:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSg-0001Q3-P6; Tue, 05 Aug 2025 15:20:22 +0000 Received: by outflank-mailman (input) for mailman id 1070593; Tue, 05 Aug 2025 15:06:48 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJFY-0007Kl-DX for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 15:06:48 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-sth1.inumbo.com (Halon) with ESMTP id ce744366-720d-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 17:06:47 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A7B542BCD; Tue, 5 Aug 2025 08:06:38 -0700 (PDT) Received: from [10.1.29.177] (e137867.arm.com [10.1.29.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7233B3F673; Tue, 5 Aug 2025 08:06:42 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ce744366-720d-11f0-a321-13f23c93f187 Message-ID: <3fd74c08-2950-46a9-a191-a635f379a8f7@arm.com> Date: Tue, 5 Aug 2025 16:06:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH -next v7 4/7] arm64: entry: Use preempt_count() and need_resched() helper To: Jinjie Ruan References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-5-ruanjinjie@huawei.com> From: Ada Couprie Diaz Content-Language: en-US Cc: Ada Couprie Diaz , will@kernel.org, oleg@redhat.com, sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com, akpm@linux-foundation.org, chenl311@chinatelecom.cn, anshuman.khandual@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, catalin.marinas@arm.com Organization: Arm Ltd. In-Reply-To: <20250729015456.3411143-5-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 29/07/2025 02:54, Jinjie Ruan wrote: > The generic entry code uses preempt_count() and need_resched() helpers to > check if it should do preempt_schedule_irq(). Currently, arm64 use its own > check logic, that is "READ_ONCE(current_thread_info()->preempt_count == 0", > which is equivalent to "preempt_count() == 0 && need_resched()". > > In preparation for moving arm64 over to the generic entry code, use > these helpers to replace arm64's own code and move it ahead. > > No functional changes. > > Signed-off-by: Jinjie Ruan > --- Reviewed-by: Ada Couprie Diaz From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:20:25 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:20:25 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070589.1434196 (Exim 4.92) (envelope-from ) id 1ujJSg-0001FT-Em; Tue, 05 Aug 2025 15:20:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070589.1434196; Tue, 05 Aug 2025 15:20:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSg-0001ET-8o; Tue, 05 Aug 2025 15:20:22 +0000 Received: by outflank-mailman (input) for mailman id 1070589; Tue, 05 Aug 2025 15:06:22 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJF8-0007Ji-DN for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 15:06:22 +0000 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by se1-gles-flk1.inumbo.com (Halon) with ESMTP id bc4bc230-720d-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 17:06:17 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 42E052BC2; Tue, 5 Aug 2025 08:06:08 -0700 (PDT) Received: from [10.1.29.177] (e137867.arm.com [10.1.29.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 226143F673; Tue, 5 Aug 2025 08:06:11 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bc4bc230-720d-11f0-b898-0df219b8e170 Message-ID: Date: Tue, 5 Aug 2025 16:06:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH -next v7 2/7] arm64: entry: Refactor the entry and exit for exceptions from EL1 To: Jinjie Ruan References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-3-ruanjinjie@huawei.com> From: Ada Couprie Diaz Cc: Ada Couprie Diaz , catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com, sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com, akpm@linux-foundation.org, chenl311@chinatelecom.cn, anshuman.khandual@arm.com, kristina.martsenko@arm.com, liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org Content-Language: en-US Organization: Arm Ltd. In-Reply-To: <20250729015456.3411143-3-ruanjinjie@huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, On 29/07/2025 02:54, Jinjie Ruan wrote: > The generic entry code uses irqentry_state_t to track lockdep and RCU > state across exception entry and return. For historical reasons, arm64 > embeds similar fields within its pt_regs structure. > > In preparation for moving arm64 over to the generic entry code, pull > these fields out of arm64's pt_regs, and use a separate structure, > matching the style of the generic entry code. > > No functional changes. As far as I understand and checked, we used the two fields in an exclusive fashion, so there is indeed no functional change. > Suggested-by: Mark Rutland > Signed-off-by: Jinjie Ruan > --- > [...] > diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c > index 8e798f46ad28..97e0741abde1 100644 > --- a/arch/arm64/kernel/entry-common.c > +++ b/arch/arm64/kernel/entry-common.c > [...] > @@ -475,73 +497,81 @@ UNHANDLED(el1t, 64, error) > static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr) > { > unsigned long far = read_sysreg(far_el1); > + arm64_irqentry_state_t state; > > - enter_from_kernel_mode(regs); > + state = enter_from_kernel_mode(regs); Nit: There is some inconsistencies with some functions splitting state's definition and declaration (like el1_abort here), while some others do it on the same line (el1_undef() below for example). In some cases it is welcome as the entry function is called after some other work, but here for example it doesn't seem to be beneficial ? > local_daif_inherit(regs); > do_mem_abort(far, esr, regs); > local_daif_mask(); > - exit_to_kernel_mode(regs); > + exit_to_kernel_mode(regs, state); > } > > static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr) > { > unsigned long far = read_sysreg(far_el1); > + arm64_irqentry_state_t state; > > - enter_from_kernel_mode(regs); > + state = enter_from_kernel_mode(regs); > local_daif_inherit(regs); > do_sp_pc_abort(far, esr, regs); > local_daif_mask(); > - exit_to_kernel_mode(regs); > + exit_to_kernel_mode(regs, state); > } > > static void noinstr el1_undef(struct pt_regs *regs, unsigned long esr) > { > - enter_from_kernel_mode(regs); > + arm64_irqentry_state_t state = enter_from_kernel_mode(regs); > + > local_daif_inherit(regs); > do_el1_undef(regs, esr); > local_daif_mask(); > - exit_to_kernel_mode(regs); > + exit_to_kernel_mode(regs, state); > } > > [...] Other than the small nit: Reviewed-by: Ada Couprie Diaz From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:20:27 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:20:27 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070603.1434271 (Exim 4.92) (envelope-from ) id 1ujJSl-000316-6r; Tue, 05 Aug 2025 15:20:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070603.1434271; Tue, 05 Aug 2025 15:20:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSk-00030R-VD; Tue, 05 Aug 2025 15:20:26 +0000 Received: by outflank-mailman (input) for mailman id 1070603; Tue, 05 Aug 2025 15:20:25 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJSj-0002Ma-IM for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 15:20:25 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id b2cff0fb-720f-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 17:20:20 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-af93381a1d2so662415266b.3 for ; Tue, 05 Aug 2025 08:20:20 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 05 Aug 2025 08:20:19 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 17:20:17 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 11/20] xen/riscv: implement function to map memory in guest p2m To: Oleksii Kurochko , Andrew Cooper Cc: Alistair Francis , Bob Eshleman , Connor Davis , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > Implement map_regions_p2mt() to map a region in the guest p2m with > a specific p2m type. The memory attributes will be derived from the > p2m type. This function is going to be called from dom0less common > code. s/is going to be/is/ ? Such a call exists already, after all. > --- a/xen/arch/riscv/include/asm/p2m.h > +++ b/xen/arch/riscv/include/asm/p2m.h > @@ -121,21 +121,22 @@ static inline int guest_physmap_mark_populate_on_demand(struct domain *d, > return -EOPNOTSUPP; > } > > -static inline int guest_physmap_add_entry(struct domain *d, > - gfn_t gfn, mfn_t mfn, > - unsigned long page_order, > - p2m_type_t t) > -{ > - BUG_ON("unimplemented"); > - return -EINVAL; > -} > +/* > + * Map a region in the guest p2m with a specific p2m type. What is "the guest p2m"? In your answer, please consider the possible (and at some point likely necessary) existence of altp2m and nestedp2m. In patch 04 you introduce p2m_get_hostp2m(), and I expect it's that what you mean here. > --- a/xen/arch/riscv/p2m.c > +++ b/xen/arch/riscv/p2m.c > @@ -9,6 +9,41 @@ > > unsigned int __read_mostly p2m_root_order; > > +/* > + * Force a synchronous P2M TLB flush. > + * > + * Must be called with the p2m lock held. > + */ > +static void p2m_force_tlb_flush_sync(struct p2m_domain *p2m) > +{ > + struct domain *d = p2m->domain; Pointer-to-const please. Personally, given the implementation of this function (and also ... > + ASSERT(p2m_is_write_locked(p2m)); > + > + sbi_remote_hfence_gvma(d->dirty_cpumask, 0, 0); > + > + p2m->need_flush = false; > +} > + > +void p2m_tlb_flush_sync(struct p2m_domain *p2m) > +{ > + if ( p2m->need_flush ) > + p2m_force_tlb_flush_sync(p2m); > +} ... this one) I'd further ask for the function parameters to also be pointer-to-const, but Andrew may object to that. Andrew - it continues to be unclear to me under what conditions you agree with adding const, and under what conditions you would object to me asking for such. Please can you take the time to clarify this? > +/* Unlock the flush and do a P2M TLB flush if necessary */ > +void p2m_write_unlock(struct p2m_domain *p2m) > +{ > + /* > + * The final flush is done with the P2M write lock taken to avoid > + * someone else modifying the P2M wbefore the TLB invalidation has Nit: Stray 'w'. > + * completed. > + */ > + p2m_tlb_flush_sync(p2m); Wasn't the plan to have this be conditional? > @@ -139,3 +174,33 @@ int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted) > > return 0; > } > + > +static int p2m_set_range(struct p2m_domain *p2m, > + gfn_t sgfn, > + unsigned long nr, > + mfn_t smfn, > + p2m_type_t t) > +{ > + return -EOPNOTSUPP; > +} > + > +static int p2m_insert_mapping(struct p2m_domain *p2m, gfn_t start_gfn, > + unsigned long nr, mfn_t mfn, p2m_type_t t) > +{ > + int rc; > + > + p2m_write_lock(p2m); > + rc = p2m_set_range(p2m, start_gfn, nr, mfn, t); > + p2m_write_unlock(p2m); > + > + return rc; > +} > + > +int map_regions_p2mt(struct domain *d, > + gfn_t gfn, > + unsigned long nr, > + mfn_t mfn, > + p2m_type_t p2mt) > +{ > + return p2m_insert_mapping(p2m_get_hostp2m(d), gfn, nr, mfn, p2mt); > +} And eventually both helper functions will gain further callers? Otherwise it's a little hard to see why they would both need to be separate functions. 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[92.178.7.112]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-458953cfeaesm271894195e9.16.2025.08.05.08.27.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 08:27:40 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b9d50e61-7210-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754407661; x=1755012461; darn=lists.xenproject.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=KpQ6JVuYGsB2GRKbtOPMGOVowMsWszSsXYpd1hQT2Fk=; b=XVdegpZ/xoX2OtCzvNHU/QkMTjIdsNXB4WaX1nCfzFfDCFhiggAbps6LdGXv+L/qFo QlqlU3Xx2ifCk9eezCSHCQTriU8P+f3f2OZoi12jGIO20XdE8KLfj/9p0hHVUuoTvpOX Utoacl0yz1HEVu6mb+++72/eP/B6+gBDKQKTI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754407661; x=1755012461; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=KpQ6JVuYGsB2GRKbtOPMGOVowMsWszSsXYpd1hQT2Fk=; b=eon5f90kqTIY4ZUl0QWPlPh7s4wE6Wfi9K8YNqIdHKaPW28bKWqyxT+uUnWyHFZqOR RRxxidzhQJtqeJ3cr4eKMwZX91HAJQXaaIRQz99QYcRBJl/qK/UfU5+jHDYUaRLVd6sj +JxbO44ZfmDT+OuWF2KMQOUBAlMnnzp27ri3vB98ea60ziWCCTxPTQK2sc07vSKK00XK B/C1u0ku3I/MeTs2Pt3AITwM4iVRZFHhws9Ka9i6N3GwBRlgzQxmQyr35HF74v0Y1E5a mV0YMOKPeeynb7v4DM9DNQuYMNwkOxuEFkyQWeIYMZ6dR6oWC9Hyjk5A1RibsQvkfFz3 NdZg== X-Forwarded-Encrypted: i=1; AJvYcCXMA7+9AlbXWDpCHXg0AniwaQ8XoSdgC3iTvHccr7g0ZtNPlALJBCBCfP6CGFOO66TuKEQwiIyyS/A=@lists.xenproject.org X-Gm-Message-State: AOJu0YyJPieIP91WEqhUgSlYemsKEODz9ozk4KImusISIxQhWbOVbJJZ s8NWGgrKPOkybMAS0wIJNbTlfIoYjrcHB1/v4mA+l5J2sMPNlHo05OnH7EVgxH3W3mekqg9bYP+ AltwU X-Gm-Gg: ASbGncvm2uqXa1lXi1wOxddAkjlL9SUX7ysYD3lg9OrFdzAvlUGazBRhxhsK6WhS5XT Jtd3Gt1MPYsY2cUofiebySCh/cCTdQpceCycch/P7QqL1Gdt2D+83WdBA1J/+/aVbZE/WkBscS6 /u5fV80Ty6KH1Cr2oK/HQPGwLXq7YTpx+0WtyrBAJi63XYLSlhuYlcpDtWVwQvNoyVcBt9ivK7J 1XbGGBLxmc5+nAPw4zahaB3BTKXHDoVu+OLzfM1CDLmV4R2e0dQj16iBiywNL/dsbR47wqcCxl1 sDYdsqf8w1boVhvliv9sL71T1ZExGWbnOI3A+E0Sa287R4VRz17QLTAfxA4iw3oNfSu7uDzr2To GluGjrJvqnW7I3BH461dqQXB+EY2+XVRaPtnFlDhKi6xwcfqrQQNZIPnbe841/1mie95tmcRZVg 4x X-Google-Smtp-Source: AGHT+IFyOv2Xc+fp5Zcq7Qrz3t1lTUDHVhOZr2Rpw/TGq+7T7Eht6R6qm8rCdqbdSc/wZswRgGTEpg== X-Received: by 2002:a05:600c:4ed0:b0:459:e466:1bec with SMTP id 5b1f17b1804b1-459e4661e0bmr17456935e9.2.1754407660595; Tue, 05 Aug 2025 08:27:40 -0700 (PDT) Date: Tue, 5 Aug 2025 17:27:39 +0200 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Jan Beulich Cc: Andrew Cooper , xen-devel@lists.xenproject.org Subject: Re: [PATCH v4 8/8] x86/mm: adjust loop in arch_init_memory() to iterate over the PDX space Message-ID: References: <20250805095257.74975-1-roger.pau@citrix.com> <20250805095257.74975-9-roger.pau@citrix.com> <31691bf7-94bf-4f73-b04c-a32f86bb0e37@suse.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <31691bf7-94bf-4f73-b04c-a32f86bb0e37@suse.com> On Tue, Aug 05, 2025 at 02:38:38PM +0200, Jan Beulich wrote: > On 05.08.2025 11:52, Roger Pau Monne wrote: > > --- a/xen/arch/x86/mm.c > > +++ b/xen/arch/x86/mm.c > > @@ -275,7 +275,7 @@ static void __init assign_io_page(struct page_info *page) > > > > void __init arch_init_memory(void) > > { > > - unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn; > > + unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn, pdx; > > > > /* > > * Basic guest-accessible flags: > > @@ -328,9 +328,20 @@ void __init arch_init_memory(void) > > destroy_xen_mappings((unsigned long)mfn_to_virt(iostart_pfn), > > (unsigned long)mfn_to_virt(ioend_pfn)); > > > > - /* Mark as I/O up to next RAM region. */ > > - for ( ; pfn < rstart_pfn; pfn++ ) > > + /* > > + * Mark as I/O up to next RAM region. Iterate over the PDX space to > > + * skip holes which would always fail the mfn_valid() check. > > + * > > + * pfn_to_pdx() requires a valid (iow: RAM) PFN to convert to PDX, > > + * hence provide pfn - 1, which is the tailing PFN from the last RAM > > + * range, or pdx 0 if the input pfn is 0. > > + */ > > + for ( pdx = pfn ? pfn_to_pdx(pfn - 1) + 1 : 0; > > + pdx < pfn_to_pdx(rstart_pfn); > > + pdx++ ) > > { > > + pfn = pdx_to_pfn(pdx); > > + > > if ( !mfn_valid(_mfn(pfn)) ) > > continue; > > > > As much as I would have liked to ack this, I fear there's another caveat here: > At the top of the loop we check not only for RAM, but also for UNUSABLE. The > latter, like RAM, shouldn't be marked I/O, but we also can't use PFN <-> PDX > transformations on any such page. Right you are. I'm not sure however why we do this - won't we want the mappings of UNUSABLE regions also be removed from the Xen page-tables? (but not marked as IO) I could do something like: /* Mark as I/O up to next RAM or UNUSABLE region. */ if ( (!pfn || pdx_is_region_compressible(pfn_to_paddr(pfn - 1), 1)) && pdx_is_region_compressible(pfn_to_paddr(rstart_pfn), 1) ) { /* * Iterate over the PDX space to skip holes which would always fail * the mfn_valid() check. * * pfn_to_pdx() requires a valid (iow: RAM) PFN to convert to PDX, * hence provide pfn - 1, which is the tailing PFN from the last * RAM range, or pdx 0 if the input pfn is 0. */ for ( pdx = pfn ? pfn_to_pdx(pfn - 1) + 1 : 0; pdx < pfn_to_pdx(rstart_pfn); pdx++ ) { pfn = pdx_to_pfn(pdx); if ( !mfn_valid(_mfn(pfn)) ) continue; assign_io_page(mfn_to_page(_mfn(pfn))); } } else { /* Slow path, iterate over the PFN space. */ for ( ; pfn < rstart_pfn; pfn++ ) { if ( !mfn_valid(_mfn(pfn)) ) continue; assign_io_page(mfn_to_page(_mfn(pfn))); } } But I find it a bit ugly - I might send v5 without this final patch while I see if I can find a better alternative. Thanks, Roger. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 15:31:03.9422 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cf19268-9360-47b3-413e-08ddd43516f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF0D2C72F0D On 2025-08-04 11:41, Jan Beulich wrote: > While the logic there covers asymmetric cases, the resulting log > messages would likely raise more confusion than clarify anything. Split > the BSP action from the AP one, indicating the odd CPU in the AP log > message, thus avoiding the impression that global state would have > changed. > > While there also > - move g_disabled into .data.ro_after_init; only the BSP will ever write > to it, > - make the function's parameter unsigned; no negative values may be > passed in. Also reflect this in svm_asid_init(). > > Signed-off-by: Jan Beulich Reviewed-by: Jason Andryuk From xen-devel-bounces@lists.xenproject.org Tue Aug 05 15:53:07 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 15:53:07 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070695.1434311 (Exim 4.92) (envelope-from ) id 1ujJyC-00030t-BM; Tue, 05 Aug 2025 15:52:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070695.1434311; Tue, 05 Aug 2025 15:52:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJyC-00030m-8b; Tue, 05 Aug 2025 15:52:56 +0000 Received: by outflank-mailman (input) for mailman id 1070695; Tue, 05 Aug 2025 15:52:55 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujJyB-00030f-Rg for xen-devel@lists.xenproject.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 15:52:51.1617 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47fac8f0-c65e-431c-1476-08ddd438221d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4140 On 2025-08-01 03:30, Jan Beulich wrote: > Them not being altered by any means, their __read_mostly attribute is > actually counter-productive: It causes the compiler to instantiate the > variables, when already with just the attributes dropped the compiler > can constant-propagate the values into the sole use site. Make the > situation yet more explicit by adding const. > > Also switch the variables away from being plain int, and have the > parameters of __printk_ratelimit() follow suit. While there also > similarly adjust the type of "missed" and "lost", and - while touching > the adjacent line - increase lost_str[] to accommodate any unsigned > 32-bit number. > > Fixes: a8b1845a7845 ("Miscellaneous data placement adjustments") > Signed-off-by: Jan Beulich Reviewed-by: Jason Andryuk From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:04:00 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:04:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070703.1434321 (Exim 4.92) (envelope-from ) id 1ujK8p-0005Kh-9g; Tue, 05 Aug 2025 16:03:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070703.1434321; Tue, 05 Aug 2025 16:03:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujK8p-0005Ka-76; Tue, 05 Aug 2025 16:03:55 +0000 Received: by outflank-mailman (input) for mailman id 1070703; Tue, 05 Aug 2025 16:03:54 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujK8o-0005KP-6F for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 16:03:54 +0000 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [2a00:1450:4864:20::433]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id c8a103b3-7215-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 18:03:53 +0200 (CEST) Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3b79bd3b1f7so3214536f8f.1 for ; Tue, 05 Aug 2025 09:03:53 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. 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Fix this by doing the local APIC EOI strictly after the window with interrupt enabled, as that prevents the recursion, and would only allow for interrupts with higher priority to be serviced. Use the generic ack_nonmaskable_msi_irq() and end_nonmaskable_irq() functions, removing the need for hpet_msi_ack(). Reported-by: Andrew Cooper Fixes: 3ba523ff957c ('CPUIDLE: enable MSI capable HPET for timer broadcast') Signed-off-by: Roger Pau Monné --- xen/arch/x86/hpet.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/hpet.c b/xen/arch/x86/hpet.c index 192de433cfd1..d05b5eb1361f 100644 --- a/xen/arch/x86/hpet.c +++ b/xen/arch/x86/hpet.c @@ -303,13 +303,6 @@ static unsigned int cf_check hpet_msi_startup(struct irq_desc *desc) #define hpet_msi_shutdown hpet_msi_mask -static void cf_check hpet_msi_ack(struct irq_desc *desc) -{ - irq_complete_move(desc); - move_native_irq(desc); - ack_APIC_irq(); -} - static void cf_check hpet_msi_set_affinity( struct irq_desc *desc, const cpumask_t *mask) { @@ -337,7 +330,8 @@ static hw_irq_controller hpet_msi_type = { .shutdown = hpet_msi_shutdown, .enable = hpet_msi_unmask, .disable = hpet_msi_mask, - .ack = hpet_msi_ack, + .ack = ack_nonmaskable_msi_irq, + .end = end_nonmaskable_irq, .set_affinity = hpet_msi_set_affinity, }; -- 2.49.0 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:05:05 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:05:05 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070714.1434332 (Exim 4.92) (envelope-from ) id 1ujK9w-00060B-N4; Tue, 05 Aug 2025 16:05:04 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070714.1434332; Tue, 05 Aug 2025 16:05:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujK9w-000604-JR; Tue, 05 Aug 2025 16:05:04 +0000 Received: by outflank-mailman (input) for mailman id 1070714; Tue, 05 Aug 2025 16:05:02 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujK9u-0005KP-PA for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 16:05:02 +0000 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [2a00:1450:4864:20::535]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id f119556d-7215-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 18:05:01 +0200 (CEST) Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-615398dc162so10087224a12.3 for ; Tue, 05 Aug 2025 09:05:01 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 05 Aug 2025 09:05:00 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 18:04:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 12/20] xen/riscv: implement p2m_set_range() To: Oleksii Kurochko Cc: Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , xen-devel@lists.xenproject.org References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 31.07.2025 17:58, Oleksii Kurochko wrote: > This patch introduces p2m_set_range() and its core helper p2m_set_entry() for Nit: This patch doesn't introduce p2m_set_range(); it merely fleshes it out. > --- a/xen/arch/riscv/include/asm/p2m.h > +++ b/xen/arch/riscv/include/asm/p2m.h > @@ -7,11 +7,13 @@ > #include > #include > > +#include > #include > > extern unsigned int p2m_root_order; > #define P2M_ROOT_ORDER p2m_root_order > #define P2M_ROOT_PAGES BIT(P2M_ROOT_ORDER, U) > +#define P2M_ROOT_LEVEL HYP_PT_ROOT_LEVEL I think I commented on this before, and I would have hoped for at least a remark in the description to appear (perhaps even a comment here): It's okay(ish) to tie these together for now, but in the longer run I don't expect this is going to be wanted. If e.g. we ran Xen in Sv57 mode, there would be no reason at all to force all P2Ms to use 5 levels of page tables. > @@ -175,13 +179,257 @@ int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted) > return 0; > } > > +/* > + * Find and map the root page table. The caller is responsible for > + * unmapping the table. > + * > + * The function will return NULL if the offset into the root table is > + * invalid. > + */ > +static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn) > +{ > + unsigned long root_table_indx; > + > + root_table_indx = gfn_x(gfn) >> XEN_PT_LEVEL_ORDER(P2M_ROOT_LEVEL); Right now page table layouts / arrangements are indeed similar enough to share accessor constructs. Nevertheless I find it problematic (doc-wise at the very least) that a Xen page table construct is used to access a P2M page table. If and when these needed to be decoupled, it would likely help of the distinction was already made, by - for now - simply introducing aliases (here e.g. P2M_LEVEL_ORDER(), expanding to XEN_PT_LEVEL_ORDER() for the time being). > + if ( root_table_indx >= P2M_ROOT_PAGES ) > + return NULL; > + > + return __map_domain_page(p2m->root + root_table_indx); > +} > + > +static inline void p2m_write_pte(pte_t *p, pte_t pte, bool clean_pte) > +{ > + write_pte(p, pte); > + if ( clean_pte ) > + clean_dcache_va_range(p, sizeof(*p)); Not necessarily for right away, but if multiple adjacent PTEs are written without releasing the lock, this then redundant cache flushing can be a performance issue. > +} > + > +static inline void p2m_clean_pte(pte_t *p, bool clean_pte) > +{ > + pte_t pte; > + > + memset(&pte, 0, sizeof(pte)); Why memset()? Why not simply give the variable an appropriate initializer? Or use ... > + p2m_write_pte(p, pte, clean_pte); ... a compound literal here, like you do ... > +} > + > +static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t) > +{ > + panic("%s: hasn't been implemented yet\n", __func__); > + > + return (pte_t) { .pte = 0 }; ... here? (Just {} would also do, if I'm not mistaken.) > +} > + > +#define P2M_TABLE_MAP_NONE 0 > +#define P2M_TABLE_MAP_NOMEM 1 > +#define P2M_TABLE_SUPER_PAGE 2 > +#define P2M_TABLE_NORMAL 3 > + > +/* > + * Take the currently mapped table, find the corresponding the entry > + * corresponding to the GFN, and map the next table, if available. Nit: Double "corresponding". > + * The previous table will be unmapped if the next level was mapped > + * (e.g P2M_TABLE_NORMAL returned). > + * > + * `alloc_tbl` parameter indicates whether intermediate tables should > + * be allocated when not present. > + * > + * Return values: > + * P2M_TABLE_MAP_NONE: a table allocation isn't permitted. > + * P2M_TABLE_MAP_NOMEM: allocating a new page failed. > + * P2M_TABLE_SUPER_PAGE: next level or leaf mapped normally. > + * P2M_TABLE_NORMAL: The next entry points to a superpage. > + */ > +static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl, > + unsigned int level, pte_t **table, > + unsigned int offset) > +{ > + panic("%s: hasn't been implemented yet\n", __func__); > + > + return P2M_TABLE_MAP_NONE; > +} > + > +/* Free pte sub-tree behind an entry */ > +static void p2m_free_subtree(struct p2m_domain *p2m, > + pte_t entry, unsigned int level) > +{ > + panic("%s: hasn't been implemented yet\n", __func__); > +} > + > +/* > + * Insert an entry in the p2m. This should be called with a mapping > + * equal to a page/superpage. > + */ > +static int p2m_set_entry(struct p2m_domain *p2m, > + gfn_t gfn, > + unsigned long page_order, > + mfn_t mfn, > + p2m_type_t t) > +{ > + unsigned int level; > + unsigned int target = page_order / PAGETABLE_ORDER; > + pte_t *entry, *table, orig_pte; > + int rc; > + /* A mapping is removed if the MFN is invalid. */ > + bool removing_mapping = mfn_eq(mfn, INVALID_MFN); Comment and code don't fit together. Many MFNs are invalid (any for which mfn_valid() returns false), yet you only check for INVALID_MFN here. > + DECLARE_OFFSETS(offsets, gfn_to_gaddr(gfn)); > + > + ASSERT(p2m_is_write_locked(p2m)); > + > + /* > + * Check if the level target is valid: we only support > + * 4K - 2M - 1G mapping. > + */ > + ASSERT((target <= 2) && !(page_order % PAGETABLE_ORDER)); If you think you need to check this, don't you also want to check that GFN and MFN (the latter if it isn't INVALID_MFN) fit the requested order? > + table = p2m_get_root_pointer(p2m, gfn); > + if ( !table ) > + return -EINVAL; > + > + for ( level = P2M_ROOT_LEVEL; level > target; level-- ) > + { > + /* > + * Don't try to allocate intermediate page table if the mapping > + * is about to be removed. > + */ > + rc = p2m_next_level(p2m, !removing_mapping, > + level, &table, offsets[level]); > + if ( (rc == P2M_TABLE_MAP_NONE) || (rc == P2M_TABLE_MAP_NOMEM) ) > + { > + rc = (rc == P2M_TABLE_MAP_NONE) ? -ENOENT : -ENOMEM; > + /* > + * We are here because p2m_next_level has failed to map > + * the intermediate page table (e.g the table does not exist > + * and they p2m tree is read-only). It is a valid case > + * when removing a mapping as it may not exist in the > + * page table. In this case, just ignore it. > + */ > + rc = removing_mapping ? 0 : rc; Nit: Stray blank. > + goto out; > + } > + > + if ( rc != P2M_TABLE_NORMAL ) > + break; > + } > + > + entry = table + offsets[level]; > + > + /* > + * If we are here with level > target, we must be at a leaf node, > + * and we need to break up the superpage. > + */ > + if ( level > target ) > + { > + panic("Shattering isn't implemented\n"); > + } > + > + /* > + * We should always be there with the correct level because all the > + * intermediate tables have been installed if necessary. > + */ > + ASSERT(level == target); > + > + orig_pte = *entry; > + > + if ( removing_mapping ) > + p2m_clean_pte(entry, p2m->clean_pte); > + else > + { > + pte_t pte = p2m_pte_from_mfn(mfn, t); > + > + p2m_write_pte(entry, pte, p2m->clean_pte); > + > + p2m->max_mapped_gfn = gfn_max(p2m->max_mapped_gfn, > + gfn_add(gfn, BIT(page_order, UL) - 1)); > + p2m->lowest_mapped_gfn = gfn_min(p2m->lowest_mapped_gfn, gfn); > + } > + > + p2m->need_flush = true; > + > + /* > + * Currently, the infrastructure required to enable CONFIG_HAS_PASSTHROUGH > + * is not ready for RISC-V support. > + * > + * When CONFIG_HAS_PASSTHROUGH=y, iommu_iotlb_flush() should be done > + * here. > + */ > +#ifdef CONFIG_HAS_PASSTHROUGH > +# error "add code to flush IOMMU TLB" > +#endif > + > + rc = 0; > + > + /* > + * Free the entry only if the original pte was valid and the base > + * is different (to avoid freeing when permission is changed). > + */ > + if ( pte_is_valid(orig_pte) && > + !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) ) I'm puzzled by this 2nd check: A permission change would - I expect - only occur to a leaf entry. If the new entry is a super-page one and the old wasn't, don't you still need to free the sub-tree, no matter whether the MFNs are the same? Plus consider the special case of MFN 0: If you clear an entry using MFN 0, you will find old and new PTEs' both having the same MFN. > static int p2m_set_range(struct p2m_domain *p2m, > gfn_t sgfn, > unsigned long nr, > mfn_t smfn, > p2m_type_t t) > { > - return -EOPNOTSUPP; > + int rc = 0; > + unsigned long left = nr; > + > + /* > + * Any reference taken by the P2M mappings (e.g. foreign mapping) will > + * be dropped in relinquish_p2m_mapping(). As the P2M will still > + * be accessible after, we need to prevent mapping to be added when the > + * domain is dying. > + */ > + if ( unlikely(p2m->domain->is_dying) ) > + return -EACCES; > + > + while ( left ) > + { > + unsigned long order = p2m_mapping_order(sgfn, smfn, left); > + > + rc = p2m_set_entry(p2m, sgfn, order, smfn, t); > + if ( rc ) > + break; > + > + sgfn = gfn_add(sgfn, BIT(order, UL)); > + if ( !mfn_eq(smfn, INVALID_MFN) ) > + smfn = mfn_add(smfn, BIT(order, UL)); > + > + left -= BIT(order, UL); > + } > + > + return !left ? 0 : left == nr ? rc : (nr - left); The function returning "int", you may be truncating the return value here. In the worst case indicating success (0) or an error (negative) when some of the upper bits were set. Also looks like you could get away with a single conditional operator here: return !left || left == nr ? rc : (nr - left); Jan From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:05:44 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:05:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070718.1434342 (Exim 4.92) (envelope-from ) id 1ujKAZ-0006Sn-Ua; Tue, 05 Aug 2025 16:05:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070718.1434342; Tue, 05 Aug 2025 16:05:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKAZ-0006Sg-RI; Tue, 05 Aug 2025 16:05:43 +0000 Received: by outflank-mailman (input) for mailman id 1070718; Tue, 05 Aug 2025 16:05:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKAY-0006SK-QM for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 16:05:42 +0000 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [2a00:1450:4864:20::331]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 06d65ecf-7216-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 18:05:37 +0200 (CEST) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-458ba079338so185255e9.1 for ; Tue, 05 Aug 2025 09:05:37 -0700 (PDT) Received: from [192.168.1.183] (host-195-149-20-212.as13285.net. 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Tue, 05 Aug 2025 09:05:37 -0700 (PDT) Message-ID: <641a944b-ed71-49f3-aa3e-e92f4ee06508@citrix.com> Date: Tue, 5 Aug 2025 17:05:35 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86/hpet: do local APIC EOI after interrupt processing To: Roger Pau Monne , xen-devel@lists.xenproject.org Cc: Jan Beulich References: <20250805160326.78837-1-roger.pau@citrix.com> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: <20250805160326.78837-1-roger.pau@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05/08/2025 5:03 pm, Roger Pau Monne wrote: > The current logic in the HPET interrupt ->ack() hook will perform a local > APIC EOI ahead of enabling interrupts, possibly leading to recursion in the > interrupt handler. > > Fix this by doing the local APIC EOI strictly after the window with > interrupt enabled, as that prevents the recursion, and would only allow for > interrupts with higher priority to be serviced. > > Use the generic ack_nonmaskable_msi_irq() and end_nonmaskable_irq() > functions, removing the need for hpet_msi_ack(). > > Reported-by: Andrew Cooper > Fixes: 3ba523ff957c ('CPUIDLE: enable MSI capable HPET for timer broadcast') > Signed-off-by: Roger Pau Monné Reviewed-by: Andrew Cooper Good riddance to the mess in our patchqueue cased by this. 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Tue, 05 Aug 2025 09:30:28 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 17:30:27 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] systemd: Add hooks to stop/start xen-watchdog on suspend/resume To: Mykola Kvach , xen-devel@lists.xenproject.org Cc: Mykola Kvach , Anthony PERARD References: Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 17/07/2025 9:16 pm, Mykola Kvach wrote: > config/Tools.mk.in | 1 + > m4/systemd.m4 | 14 ++++++++ > tools/hotplug/Linux/systemd/Makefile | 8 ++++- > .../Linux/systemd/xen-watchdog-sleep.sh | 34 +++++++++++++++++++ This has been committed, but it drops the file:   /usr/lib/systemd/system-sleep/xen-watchdog-sleep.sh into a directory which more normally contains: $ file /usr/lib/systemd/system-sleep/* /usr/lib/systemd/system-sleep/hdparm:              POSIX shell script, ASCII text executable /usr/lib/systemd/system-sleep/nvidia:              POSIX shell script, ASCII text executable /usr/lib/systemd/system-sleep/sysstat.sleep:       POSIX shell script, ASCII text executable /usr/lib/systemd/system-sleep/tlp:                 POSIX shell script, ASCII text executable /usr/lib/systemd/system-sleep/unattended-upgrades: POSIX shell script, ASCII text executable I'd suggest renaming it to xen-watchdog (or perhaps xen-watchdog.sleep). ~Andrew From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:32:11 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:32:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070744.1434362 (Exim 4.92) (envelope-from ) id 1ujKaA-0002hk-AL; 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Tue, 05 Aug 2025 09:32:08 -0700 (PDT) From: Ross Lagerwall To: Xen-devel , xen-devel@lists.xenproject.org Cc: Ross Lagerwall , "Daniel P. Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Jan Beulich Subject: [PATCH 0/2] Misc EFI boot fixes Date: Tue, 5 Aug 2025 17:32:02 +0100 Message-ID: <20250805163204.3631483-1-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.50.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Fixes for a couple of annoyances when booting Xen using the native EFI entry point. Ross Lagerwall (2): efi: Call FreePages only if needed efi: Stop using StdErr xen/common/efi/boot.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:32:11 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:32:11 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070745.1434373 (Exim 4.92) (envelope-from ) id 1ujKaB-0002vr-HR; Tue, 05 Aug 2025 16:32:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070745.1434373; Tue, 05 Aug 2025 16:32:11 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKaB-0002vi-D5; Tue, 05 Aug 2025 16:32:11 +0000 Received: by outflank-mailman (input) for mailman id 1070745; Tue, 05 Aug 2025 16:32:10 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKaA-0002gS-KN for xen-devel@lists.xen.org; Tue, 05 Aug 2025 16:32:10 +0000 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [2a00:1450:4864:20::62b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id bb473bf1-7219-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 18:32:09 +0200 (CEST) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-af93c3bac8fso638381066b.2 for ; Tue, 05 Aug 2025 09:32:09 -0700 (PDT) Received: from rossla-pc.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af928c84154sm842980766b.84.2025.08.05.09.32.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 09:32:07 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bb473bf1-7219-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754411528; x=1755016328; darn=lists.xen.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Cw+fp9ijqB07ybQ00T6Z+NAfGs8NSWdqqpiXyp8ErM4=; b=jWc64krrPGfNBbHLeiIe0zQ1vzurQmzf3HzVTUzjc6/7j39jL6U/2sgsVhyEyInCrT Gz67skHR5FWLLKKKAK68ttbdPKzd9v5OcrzkxBjKzDqopWxzMyfXb0VAP5etY51XFCO6 lNOfsAJdSiOC1bOBqSGW+EHwhqEIgUl3n6kik= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754411528; x=1755016328; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Cw+fp9ijqB07ybQ00T6Z+NAfGs8NSWdqqpiXyp8ErM4=; b=KlYpVqs/Gf+RQ+XhL3kGG7Ahz0y2FQLfDuRdqXLWHbiif1DDB5usAZSn4nb8prcWzc 6ST652g8HvY/PIqOYvHk6DPJ4uWhkExg4ryusjnyP/j/xfljE7ckIpOa+sOH736hUCeD kdewYLhW/C88kCUWsnXaYpQ0LmbUYV8Pt/JkpbBg9TohikuIsGiRj7P06w07A4VteXQ7 y8bWPcjtG6wZnGfffqn+NIg664txGIe5lW+XEKEipKGsG3kj44roKmiVNCqC4RQrN0s7 dYOjafgaKwNatbb5Pd6loINED9wuaS/z0kzIiVb/n3fN0dQgIpsfaL54ALDAe12K6kOp MXkg== X-Gm-Message-State: AOJu0YyPmxWNj90JnK8Cd5vyQLMdO/7RrKHcIi8RproC/k7fjVzVpAKR fkW6thlTe6IJAU+hUQFSrG2rk5kzeS3QljoC/nby1J8b4NGJa0QafQzYRpuXCkgZNFRjTrexzBb Uf0U= X-Gm-Gg: ASbGncty9d0n+3bkEvpxubZGcfdxeMg+y3H4bHdmFz1UeRgAX9T5Gny12BYdI69/R9E eac536jLF2DKtqs18Htj/OxuzWaHwZDJy4+Qoz8gOU3KHd2kLlTTsqFlvfbNQWsBb+KLvi6OMYe n2avkD1xnTu+f20bJPn8i923t6zdk9sU21DIp6KmY+5dCUpVh6viWgG7zH0G1piJDxW0YsUATxE zRJhBiqWgTmj8pNWShIrhbCeArAAyKG/aC+cpM7D6TtAeeWT6sED3YeVPA1aB4H3j8Hs+dKbmmE YGcVmb0PvyObPl+7sXhIQHZpOLjyMPwxhDdG+nu+9T0PEVmZfnlWw8K3h50QMIQMerPNdDYBoeE KnGpoabyRBRbjBb+yTirD/uWKE1NskeX/hV+QPOdDu3OXFQ== X-Google-Smtp-Source: AGHT+IGa4GFLCDHDfvOak3r6zeET09jfJFrVEa7qKNQ3LiINiAKvfcR4Wn8Z3ypOhRbpZd4sqlkjAA== X-Received: by 2002:a17:907:7fa8:b0:ae0:d798:2ebd with SMTP id a640c23a62f3a-af94017fa9amr1402524766b.35.1754411528077; Tue, 05 Aug 2025 09:32:08 -0700 (PDT) From: Ross Lagerwall To: Xen-devel , xen-devel@lists.xenproject.org Cc: Ross Lagerwall , "Daniel P. Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Jan Beulich Subject: [PATCH 0/2] Misc EFI boot fixes Date: Tue, 5 Aug 2025 17:32:02 +0100 Message-ID: <20250805163204.3631483-1-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.50.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Fixes for a couple of annoyances when booting Xen using the native EFI entry point. Ross Lagerwall (2): efi: Call FreePages only if needed efi: Stop using StdErr xen/common/efi/boot.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:32:13 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:32:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070746.1434381 (Exim 4.92) (envelope-from ) id 1ujKaD-0003B3-NG; Tue, 05 Aug 2025 16:32:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070746.1434381; Tue, 05 Aug 2025 16:32:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKaD-0003Au-Kc; Tue, 05 Aug 2025 16:32:13 +0000 Received: by outflank-mailman (input) for mailman id 1070746; Tue, 05 Aug 2025 16:32:11 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKaB-0002Yg-SJ for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 16:32:11 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id bca38bbb-7219-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 18:32:11 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-af91a6b7a06so1026243466b.2 for ; Tue, 05 Aug 2025 09:32:11 -0700 (PDT) Received: from rossla-pc.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af928c84154sm842980766b.84.2025.08.05.09.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 09:32:10 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bca38bbb-7219-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754411531; x=1755016331; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HyChThRw6GVKg1romDTn5fzN51ukPoZgESaAn7xK/ic=; b=aNVpRU6C4xg2zlyZdIPP2L46YxQHMoGZUh19fkSorhraw2jWccc/q1mSbSDtEPazU0 4F7k7t4374HowTm8y7/3wHZGh5xQ5iaZv+GCxDOvGrFedQR9i33sqCbbVU1alXtB1fnN 1Afkw21KgYEI/oI/BZRjGmvhO49OW+MEoKbfY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754411531; x=1755016331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HyChThRw6GVKg1romDTn5fzN51ukPoZgESaAn7xK/ic=; b=dLDkT7vTrF19oMiA5tcgpJYxO0LqnW7d2ChOnycMGrMnIBGhSVVZLEuIg3m994Y11I a2YeP5cGQt/xGeke3LuAtSRuLsTX79Phd69QA4UPhJwPTRqUwSYFBf+xNn+XwjtZRJ++ i6SU5HgiaoH9c1dJmF06skXM7YwhSf5D2bpRihH55V0j/if6k95IcSkpDuE6d6DfRRTe OXkFFfmzQPAIVtKtH0EmNhoxZCkcO8uXzAYBw+idiXf/P7c9jRWwQDh3NSPVpxQjZsRu ltrzk3xcQcxX/exUeM4nd358JVZJ4FGtwX4Huats9xueVGppgzEfnAbDlMV+xiwCfCf6 PNAQ== X-Forwarded-Encrypted: i=1; AJvYcCUX/pb1XDciA1x4Ikly3yikgvF5pgNGwJ+O2TCXdSwZ767/hU8r6KP6IQ+yTEn2MkPtFUlm1ff3Grw=@lists.xenproject.org X-Gm-Message-State: AOJu0YzkzKHrjLhQmkRFGWx3rjP7QoUWuLJikl46enes8Q6WnERGR1TW L/sXIT0Q1dr+dfYugHh53Ur5Rimjtg0UTr5QjkWkRH99+BIMxXC9JQ+8pVNyJfBc8eWhrnilhmQ tWMA= X-Gm-Gg: ASbGncs1ZxaaOFfyK6WZITiNddlmSDJaJty71/h33HJtHAwUSvjfrUYtza8RXT+3eMN KRKBEKA8WDkXUtkhSP55ZdwKadW4PS3GKbjjavIZc6GfJdJiK6UQOSCk92N2y9+oiv7JBPp7lD4 QLLgUw5EQqBIpwvsqUGoMoJH5ogUxT+JKzteqNncZBi14NXqDa17d1/Bv/H3vezjm1i1chWrjTy dE+7eMdj99wo13lqdqdV4YDCKGn8meBibvLmvnW7YxeIA5L7WhM74R2DqsgF1glaOx4XsSQFbrE P4PCI7pBnJ134ZaSWInO5d+4o/ef8HVSeHnM/u693hMZ6Zj6GioEUf5nzZatvDDsJzVICnDZMQ8 GZxSD4ouPNr7Vx+OLXDOL0EnyBt6a6U4Ptyz2xxR2G6av8w== X-Google-Smtp-Source: AGHT+IHfJbaJv57Bho8r5sfyd+qAP9P2dr44hKcu2gIKy6YgKG5c4omoNyMg3Ahg2Rn7mVRnYL6UEg== X-Received: by 2002:a17:907:2d2c:b0:add:ede0:b9d4 with SMTP id a640c23a62f3a-af93fd76ffamr1568967066b.0.1754411530898; Tue, 05 Aug 2025 09:32:10 -0700 (PDT) From: Ross Lagerwall To: Xen-devel , xen-devel@lists.xenproject.org Cc: Ross Lagerwall , "Daniel P. Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Jan Beulich Subject: [PATCH 1/2] efi: Call FreePages only if needed Date: Tue, 5 Aug 2025 17:32:03 +0100 Message-ID: <20250805163204.3631483-2-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805163204.3631483-1-ross.lagerwall@citrix.com> References: <20250805163204.3631483-1-ross.lagerwall@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit If the config file is builtin, cfg.addr will be zero but Xen unconditionally calls FreePages() on the address. Xen may also call FreePages() with a zero address if blexit() is called after this point since cfg.need_to_free is not set to false. The UEFI specification does not say whether calling FreePages() with a zero address is allowed so let's be cautious and use cfg.need_to_free properly. Signed-off-by: Ross Lagerwall --- xen/common/efi/boot.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c index 778a39cc48e6..50ff1d1bd225 100644 --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -1534,8 +1534,11 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE ImageHandle, efi_arch_cfg_file_late(loaded_image, dir_handle, section.s); - efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size)); - cfg.addr = 0; + if ( cfg.need_to_free ) + { + efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size)); + cfg.need_to_free = false; + } if ( dir_handle ) dir_handle->Close(dir_handle); -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:32:15 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:32:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070747.1434393 (Exim 4.92) (envelope-from ) id 1ujKaF-0003Q7-29; Tue, 05 Aug 2025 16:32:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070747.1434393; Tue, 05 Aug 2025 16:32:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKaE-0003Q0-Rt; Tue, 05 Aug 2025 16:32:14 +0000 Received: by outflank-mailman (input) for mailman id 1070747; Tue, 05 Aug 2025 16:32:13 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKaD-0002gS-GK for xen-devel@lists.xen.org; Tue, 05 Aug 2025 16:32:13 +0000 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [2a00:1450:4864:20::629]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id bcf8c4fa-7219-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 18:32:12 +0200 (CEST) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-af967835d0aso402887866b.0 for ; Tue, 05 Aug 2025 09:32:12 -0700 (PDT) Received: from rossla-pc.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af928c84154sm842980766b.84.2025.08.05.09.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 09:32:10 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bcf8c4fa-7219-11f0-b898-0df219b8e170 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754411531; x=1755016331; darn=lists.xen.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HyChThRw6GVKg1romDTn5fzN51ukPoZgESaAn7xK/ic=; b=RjULSuQGaRH2h2sfIspmByy/vWktiO82zs8pqNmjM14Iy/56Vun4ihCiMzzcwGhEZP shDlH6SH1uoUFQ8TuHES6hZLIHQGiM1cGnYxYFB2aQUSz9HVJE2hW36xoXyxJkmyle6E +g/7os73Lmsfs8aK0vzDs+F3pjUr+VuEsj+Qw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754411531; x=1755016331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HyChThRw6GVKg1romDTn5fzN51ukPoZgESaAn7xK/ic=; b=j+i+kJo+7AwLwK92Wcy0AYQARJmBmEeoAq/bNDNDYpUxfIOhgmAQvBbea44AFxiZM0 JJNt0Gga6lt7sQFyV0ry9nLQNei2W3Vvll2p1oBLBydWP8rB9vJvsP2wA9lM/E1IvyOm F1KmGgocyoRbN+32FBrsCiLc6wBNH1oxEc83urKl4FjYRZaWMfDhtdeSuJ5syWlDKgo1 85jEGHiLFhf22OKJuA63InAp7kaLKMC4ReK88I8VIueJvi6oIGcIy09MdqTSaDoZ3UP4 Edmr9cBnXEBtujlK4PCogOOqMij39/wM7P1ULFRnV9NXso+prQRDtD1xs5usrV6BX1dD 6j5g== X-Gm-Message-State: AOJu0YwLirlRqq4SF734kR4hkU1yGcreq2PUunE00a3u+zIHMv6Zn497 bfDpEUHAybnI3iD7VMsa1nKEIgtQ6vXv3M2dFIdY4yK05YRMVt7M2cCVTpjpjK6zBnIcyUAt3R2 efS8= X-Gm-Gg: ASbGncvIV0J8S1QdT8rf7BsAOj8PPKv/8lp19zQuqlLEg1nUZgaWfZnuLaqjECj7TBT 1vwIGiYk0jgj5R79ycv0aYBJdZyaZnCkQwP5xsQQj8TvQeCMIdRRIHBh94/3rTN+SlEGykCkZtf uzi1QmkFIfeXVRbpBKM2AQXH98BHLHg0+FvTXbFa2QnNZqOK4vGzlAVhscDdV7dNcjvHj8gpT3z tlPy8d/JRhJeneFD1ew6kSbE5aOiuJQEMuaZxu7IzPoWw+kjqBLgR5EhHeBmg0wvcaNP7Joer2g T6uKp4PD0t3X9SzctLHvpfEo3w0R5xuy41Ljg1Ty84rd74o7EkA+iLMCJQkXF7UcI1+r4N5Gesh c0v9RoHEoTTaA28M3cO/Jwda2inq6MTyTXVoKQXEiqsfr3g== X-Google-Smtp-Source: AGHT+IHfJbaJv57Bho8r5sfyd+qAP9P2dr44hKcu2gIKy6YgKG5c4omoNyMg3Ahg2Rn7mVRnYL6UEg== X-Received: by 2002:a17:907:2d2c:b0:add:ede0:b9d4 with SMTP id a640c23a62f3a-af93fd76ffamr1568967066b.0.1754411530898; Tue, 05 Aug 2025 09:32:10 -0700 (PDT) From: Ross Lagerwall To: Xen-devel , xen-devel@lists.xenproject.org Cc: Ross Lagerwall , "Daniel P. Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Jan Beulich Subject: [PATCH 1/2] efi: Call FreePages only if needed Date: Tue, 5 Aug 2025 17:32:03 +0100 Message-ID: <20250805163204.3631483-2-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805163204.3631483-1-ross.lagerwall@citrix.com> References: <20250805163204.3631483-1-ross.lagerwall@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit If the config file is builtin, cfg.addr will be zero but Xen unconditionally calls FreePages() on the address. Xen may also call FreePages() with a zero address if blexit() is called after this point since cfg.need_to_free is not set to false. The UEFI specification does not say whether calling FreePages() with a zero address is allowed so let's be cautious and use cfg.need_to_free properly. Signed-off-by: Ross Lagerwall --- xen/common/efi/boot.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c index 778a39cc48e6..50ff1d1bd225 100644 --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -1534,8 +1534,11 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE ImageHandle, efi_arch_cfg_file_late(loaded_image, dir_handle, section.s); - efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size)); - cfg.addr = 0; + if ( cfg.need_to_free ) + { + efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size)); + cfg.need_to_free = false; + } if ( dir_handle ) dir_handle->Close(dir_handle); -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:32:16 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:32:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070748.1434402 (Exim 4.92) (envelope-from ) id 1ujKaG-0003gd-6d; Tue, 05 Aug 2025 16:32:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070748.1434402; Tue, 05 Aug 2025 16:32:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKaG-0003gP-3C; Tue, 05 Aug 2025 16:32:16 +0000 Received: by outflank-mailman (input) for mailman id 1070748; Tue, 05 Aug 2025 16:32:14 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKaE-0002Yg-4b for xen-devel@lists.xen.org; Tue, 05 Aug 2025 16:32:14 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id bdf1b194-7219-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 18:32:13 +0200 (CEST) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-af922ab4849so851607166b.3 for ; Tue, 05 Aug 2025 09:32:13 -0700 (PDT) Received: from rossla-pc.eng.citrite.net ([185.25.67.249]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af928c84154sm842980766b.84.2025.08.05.09.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 09:32:12 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bdf1b194-7219-11f0-a321-13f23c93f187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1754411533; x=1755016333; darn=lists.xen.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L1QqT35WPMNEdKVxqmbRQUpDF5jhPdPInhgcu4VmEpk=; b=kMtTWE3TMx3uIJAUZSpBpug1sxlsYJZN0NYrZIoUIIeclFVqzTVD3n+n+LEoa/pzdy 3aMbAMsX0T9M0iLo30S79bY3OBz39FFrdGDI0eYF3NkBxYoVuAQEBrnL06VMXFIkQiuE G1WG/ZmQD29jHiraDdZA2ZbeXQvHTBBLB3WU8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1754411533; x=1755016333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L1QqT35WPMNEdKVxqmbRQUpDF5jhPdPInhgcu4VmEpk=; b=QKONrDVfD8vVsCqXLJChkUTdgPu6DWZ2HditHpZ6pqUNTtf5IPZjLNSkpqMsE0HyCU ZUQur7NFmBLdvm7BHvpFUAku9AbTyOdav/9eEQMi/YD7+MAPem7xBX39zJMYHrafF27/ gTl8sVQZSDv7b6tVp9+S8vG8TdW1QahSYaSahV+eDNpf7EDat6KZ/+feeJJK12m4anC4 bpwZMKOKdvPHjeB6nLJDWXMX0vHoWH13mRxyijAKbUt7362JzC1oXKpq98ZQOF4DTjGG eGWB8hkkMTnjRlRKUecX1UjHhJHCq9yCVrxa8ml+vSP9zRrWaErdD89Jy6tLnl+e9ybf 5zqg== X-Gm-Message-State: AOJu0YwHXDQGG8rKCdMK/kYvQixnUvPOmsb+uFoqOhznoZjI4F+zJxlU 2leMbS16CegDJqGMOSjvsGLC9vG8cAd/DLUrQZdoyM/6qb7JBMxxMPZEsyqwaQPs06BvwBXSFIL yitQ= X-Gm-Gg: ASbGnctgyfEKiOc4EfnU84m3qZJwP26gPOghuTX5zyvFHLKDI3uxgQADNHlzZ9XBkpl mxdxRAB1fQ8BAjoYFwEwLdhAWmhlVCTFDAh9Krp5eCp2/beO6Uu0NHQCyssmbAXU+Ltqtw1ClTS 5y/DPDR25l38AxB7Z2G5rCV40oSpxZxYqfhdyiCyIBXfoBfDwEV8a7WMt9OYb5FMpRDbpiZwHSv gj1k+TW2NLLOVswgGcbOzSnJE3HHP5V9/JGcisixFVVgC4f416vd4YMNdAt7mo+zo5A0/R3c99O Uq0XO5EvQ1B8exXCJHh26zxzCP8AU0kAog/rJdjfUL9ASw3rzHCAOhy2oZI0/9e/n0i8PDSE3no 6SOi9OdLiMdNL1aERfCNTJqhPMT1ssuGIab+9K3hH2UldNw== X-Google-Smtp-Source: AGHT+IHMLaIm8aahuPreV60FOOmrmpQocxqFSXDfnpp2XbU/+KZwakIBweYK+7LfGmsvOPVCS/FpIw== X-Received: by 2002:a17:907:1b1d:b0:af9:3116:e110 with SMTP id a640c23a62f3a-af940277761mr1288991366b.58.1754411532702; Tue, 05 Aug 2025 09:32:12 -0700 (PDT) From: Ross Lagerwall To: Xen-devel , xen-devel@lists.xenproject.org Cc: Ross Lagerwall , "Daniel P. Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Jan Beulich Subject: [PATCH 2/2] efi: Stop using StdErr Date: Tue, 5 Aug 2025 17:32:04 +0100 Message-ID: <20250805163204.3631483-3-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805163204.3631483-1-ross.lagerwall@citrix.com> References: <20250805163204.3631483-1-ross.lagerwall@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Xen's use of StdErr is inconsistent. Some boot errors are reported using PrintErr() which uses StdErr and some are reported using blexit() which uses StdOut. On my test system using OVMF, StdErr is not displayed on the emulated screen. Looking at other EFI applications, StdErr is just used for debug messages if at all. Therefore, switch all boot output to use StdOut. Signed-off-by: Ross Lagerwall --- xen/common/efi/boot.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c index 50ff1d1bd225..6ba486943466 100644 --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -153,7 +153,6 @@ static UINT32 __initdata efi_bs_revision; static EFI_HANDLE __initdata efi_ih; static SIMPLE_TEXT_OUTPUT_INTERFACE *__initdata StdOut; -static SIMPLE_TEXT_OUTPUT_INTERFACE *__initdata StdErr; static UINT32 __initdata mdesc_ver; static bool __initdata map_bs; @@ -168,11 +167,7 @@ static void __init PrintStr(const CHAR16 *s) { StdOut->OutputString(StdOut, (CHAR16 *)s ); } - -static void __init PrintErr(const CHAR16 *s) -{ - StdErr->OutputString(StdErr, (CHAR16 *)s ); -} +#define PrintErr PrintStr static CHAR16 *__init FormatDec(UINT64 Val, CHAR16 *Buffer) { @@ -287,7 +282,6 @@ static bool __init match_guid(const EFI_GUID *guid1, const EFI_GUID *guid2) /* generic routine for printing error messages */ static void __init noreturn PrintErrMesg(const CHAR16 *mesg, EFI_STATUS ErrCode) { - StdOut = StdErr; PrintErr(mesg); PrintErr(L": "); @@ -914,7 +908,6 @@ static void __init efi_init(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTabl efi_fw_revision = SystemTable->FirmwareRevision; StdOut = SystemTable->ConOut; - StdErr = SystemTable->StdErr ?: StdOut; } static void __init efi_console_set_mode(void) -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:32:16 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:32:16 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070749.1434408 (Exim 4.92) (envelope-from ) id 1ujKaG-0003kf-In; Tue, 05 Aug 2025 16:32:16 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070749.1434408; Tue, 05 Aug 2025 16:32:16 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKaG-0003kP-Cz; Tue, 05 Aug 2025 16:32:16 +0000 Received: by outflank-mailman (input) for mailman id 1070749; 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Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Jan Beulich Subject: [PATCH 2/2] efi: Stop using StdErr Date: Tue, 5 Aug 2025 17:32:04 +0100 Message-ID: <20250805163204.3631483-3-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250805163204.3631483-1-ross.lagerwall@citrix.com> References: <20250805163204.3631483-1-ross.lagerwall@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Xen's use of StdErr is inconsistent. Some boot errors are reported using PrintErr() which uses StdErr and some are reported using blexit() which uses StdOut. On my test system using OVMF, StdErr is not displayed on the emulated screen. Looking at other EFI applications, StdErr is just used for debug messages if at all. Therefore, switch all boot output to use StdOut. Signed-off-by: Ross Lagerwall --- xen/common/efi/boot.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c index 50ff1d1bd225..6ba486943466 100644 --- a/xen/common/efi/boot.c +++ b/xen/common/efi/boot.c @@ -153,7 +153,6 @@ static UINT32 __initdata efi_bs_revision; static EFI_HANDLE __initdata efi_ih; static SIMPLE_TEXT_OUTPUT_INTERFACE *__initdata StdOut; -static SIMPLE_TEXT_OUTPUT_INTERFACE *__initdata StdErr; static UINT32 __initdata mdesc_ver; static bool __initdata map_bs; @@ -168,11 +167,7 @@ static void __init PrintStr(const CHAR16 *s) { StdOut->OutputString(StdOut, (CHAR16 *)s ); } - -static void __init PrintErr(const CHAR16 *s) -{ - StdErr->OutputString(StdErr, (CHAR16 *)s ); -} +#define PrintErr PrintStr static CHAR16 *__init FormatDec(UINT64 Val, CHAR16 *Buffer) { @@ -287,7 +282,6 @@ static bool __init match_guid(const EFI_GUID *guid1, const EFI_GUID *guid2) /* generic routine for printing error messages */ static void __init noreturn PrintErrMesg(const CHAR16 *mesg, EFI_STATUS ErrCode) { - StdOut = StdErr; PrintErr(mesg); PrintErr(L": "); @@ -914,7 +908,6 @@ static void __init efi_init(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTabl efi_fw_revision = SystemTable->FirmwareRevision; StdOut = SystemTable->ConOut; - StdErr = SystemTable->StdErr ?: StdOut; } static void __init efi_console_set_mode(void) -- 2.50.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:37:38 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:37:38 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070765.1434432 (Exim 4.92) (envelope-from ) id 1ujKfP-0006LV-Io; Tue, 05 Aug 2025 16:37:35 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070765.1434432; Tue, 05 Aug 2025 16:37:35 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKfP-0006LM-G3; Tue, 05 Aug 2025 16:37:35 +0000 Received: by outflank-mailman (input) for mailman id 1070765; Tue, 05 Aug 2025 16:37:33 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujKfN-00067g-TP for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 16:37:33 +0000 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [2a00:1450:4864:20::32d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7b9a7d7d-721a-11f0-b898-0df219b8e170; Tue, 05 Aug 2025 18:37:31 +0200 (CEST) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-459d7726ee6so17417505e9.2 for ; Tue, 05 Aug 2025 09:37:31 -0700 (PDT) Received: from [192.168.1.183] (host-195-149-20-212.as13285.net. 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Smith" , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Jan Beulich References: <20250805163204.3631483-1-ross.lagerwall@citrix.com> <20250805163204.3631483-2-ross.lagerwall@citrix.com> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: <20250805163204.3631483-2-ross.lagerwall@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05/08/2025 5:32 pm, Ross Lagerwall wrote: > If the config file is builtin, cfg.addr will be zero but Xen > unconditionally calls FreePages() on the address. > > Xen may also call FreePages() with a zero address if blexit() is called > after this point since cfg.need_to_free is not set to false. > > The UEFI specification does not say whether calling FreePages() with a > zero address is allowed so let's be cautious and use cfg.need_to_free > properly. > > Signed-off-by: Ross Lagerwall Acked-by: Andrew Cooper From xen-devel-bounces@lists.xenproject.org Tue Aug 05 16:37:39 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 16:37:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070764.1434422 (Exim 4.92) (envelope-from ) id 1ujKfO-00067t-DF; Tue, 05 Aug 2025 16:37:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070764.1434422; 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Smith" , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , Jan Beulich References: <20250805163204.3631483-1-ross.lagerwall@citrix.com> <20250805163204.3631483-2-ross.lagerwall@citrix.com> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: <20250805163204.3631483-2-ross.lagerwall@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05/08/2025 5:32 pm, Ross Lagerwall wrote: > If the config file is builtin, cfg.addr will be zero but Xen > unconditionally calls FreePages() on the address. > > Xen may also call FreePages() with a zero address if blexit() is called > after this point since cfg.need_to_free is not set to false. > > The UEFI specification does not say whether calling FreePages() with a > zero address is allowed so let's be cautious and use cfg.need_to_free > properly. > > Signed-off-by: Ross Lagerwall Acked-by: Andrew Cooper From xen-devel-bounces@lists.xenproject.org Tue Aug 05 17:22:13 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 17:22:13 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070819.1434441 (Exim 4.92) (envelope-from ) id 1ujLMP-0006rg-Ro; Tue, 05 Aug 2025 17:22:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070819.1434441; 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pr=C Message-ID: <7c867f77-3846-4b2a-a028-4dfb248a4fc2@amd.com> Date: Tue, 5 Aug 2025 13:21:50 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [XEN][PATCH] xen/dom0less: arm: fix hwdom 1:1 low memory allocation To: Grygorii Strashko , "xen-devel@lists.xenproject.org" CC: Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" References: <20250801155429.1402395-1-grygorii_strashko@epam.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <20250801155429.1402395-1-grygorii_strashko@epam.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB03.amd.com: jason.andryuk@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|SJ2PR12MB9115:EE_ X-MS-Office365-Filtering-Correlation-Id: 57d41a7d-89d2-4d69-26c4-08ddd4448fb0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026|7053199007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 17:21:48.9382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57d41a7d-89d2-4d69-26c4-08ddd4448fb0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9115 On 2025-08-01 11:54, Grygorii Strashko wrote: > From: Grygorii Strashko > > Call stack for dom0less hwdom case (1:1) memory: > create_domUs > |-construct_domU > |-construct_hwdom() > |-allocate_memory_11() > > And allocate_memory_11() uses "dom0_mem" as: > min_low_order = > get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); > > In case of dom0less boot the "dom0_mem" is not used and defaulted to 0, > which causes min_low_order to get high value > order and so no allocations > happens from low memory. > > Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" has correct > memory size in both cases: regular dom0 boot and dom0less boot. > > Fixes: 43afe6f030244 ("xen/common: dom0less: introduce common dom0less-build.c") I think I introduced this bug with the dom0less hwdom support, and the correct fixes is: Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction") > Signed-off-by: Grygorii Strashko dom0_mem is also mentioned in the comment on line 252. With that changed as well: Reviewed-by: Jason Andryuk Thanks, Jason From xen-devel-bounces@lists.xenproject.org Tue Aug 05 18:19:57 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 18:19:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070840.1434452 (Exim 4.92) (envelope-from ) id 1ujMGN-0006rh-SE; Tue, 05 Aug 2025 18:19:51 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070840.1434452; Tue, 05 Aug 2025 18:19:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujMGN-0006ra-NK; Tue, 05 Aug 2025 18:19:51 +0000 Received: by outflank-mailman (input) for mailman id 1070840; Tue, 05 Aug 2025 18:19:50 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujMGM-0006rU-9U for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 18:19:50 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id c5852ff0-7228-11f0-a321-13f23c93f187; Tue, 05 Aug 2025 20:19:49 +0200 (CEST) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-af9180a11bcso42802266b.0 for ; Tue, 05 Aug 2025 11:19:48 -0700 (PDT) Received: from [192.168.1.5] (user-109-243-64-38.play-internet.pl. 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Smith" , Grygorii Strashko , Alejandro Vallejo , "committers@xenproject.org" , Community Manager From: Oleksii Kurochko Subject: Xen 4.21 Development Update [June-July] Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hello everyone, This email only tracks big items for xen.git tree. Please reply for items you would like to see in 4.21 so that people have an idea what is going on and prioritise accordingly. You're welcome to provide description and use cases of the feature you're working on. = Timeline = The current release schedule could be found here:   https://wiki.xenproject.org/wiki/Xen_Project_X.YY_Release_Notes And as a reminder I would like to remind at the of this week we will have Last posting date (Fri Aug 08, 2025). = Updates = The following items ( the links for them could be found int the list below ) were moved to completed:   [since Jun2 - Aug5]:    Added some tags: [4.21], [next-rel(s)] to the list "Full list of items"    below.    * x86:     - kexec: add kexec support to Mini-OS.     - x86: memcpy() / memset() (non-)ERMS flavors plus fallout    * Arm:     - SMMU handling for PCIe Passthrough on ARM.     - Add support for R-Car Gen4 PCI host controller.     - First chunk for Arm R82 and MPU support.     - Enable R52 support for the first chunk of MPU support     - ARM split hardware and control domains.    * RISC-V:     - Introduce basic UART support and interrupts for hypervisor mode.   [since May 6 - Jun2]:     * Hypervisor:       - tools: remove qemu-traditional     * Arm:       - PCI devices passthrough on Arm, part 3     * x86:       - xen: cache control improvements   [since 4.20 relese - May 6]:     * Hypervisor:       - Move parts of Arm's Dom0less to common code       - remove libxenctrl usage from xenstored     * Arm:       - Enable early bootup of Armv8-R AArch32 systems     * x86:       - x86/HVM: emulation (MMIO) improvements     * RISC-V:       - RISC-V some preinit calls.       - Fixes for UBSAN & GCOV support for RISC-V. Some new items added:  [since May]     * x86:      - Allow x86 to unflatten DTs      - hyperlaunch: move remaining pvh dom0 construction      - x86/hyperlaunch: introduce concept of core domains      - Confidential computing and AMD SEV support     * Arm:      - SMMU handling for PCIe Passthrough on ARM      - xen/arm: scmi: introduce SCI SCMI SMC multi-agent support      - Add initial Xen Suspend-to-RAM support on ARM64     * RISC-V:      - introduce p2m functionality  [since 4.20 release]     * Hypervisor:       - tools: remove qemu-traditional       - Physical address hypercall ABI ("HVMv2")       - xen: Untangle mm.h       - xen: introduce CONFIG_SYSCTL       - Add support for exact-node memory claims       - Several CI cleanups and improvements, plus yet another new runner     * x86:       - x86/EFI: prevent write-execute sections       - x86: Trenchboot Secure Launch DRTM (Xen)       - Hyperlaunch device tree for dom0 (v6)       - amd-cppc CPU Performance Scaling Driver (v4)       - Hyperlaunch domain builder       - kexec: add kexec support to Mini-OS       - xen: cache control improvements (should be moved to "Hypervisor"?)       - x86: generate xen.efi image with no write-execute sections       - x86/asm: cleanups after toolchain baseline upgrade     * Arm:       - Add support for R-Car Gen4 PCI host controller (v4)       - FF-A VM to VM support (v5)       - First chunk for Arm R82 and MPU support (v4)       - ARM split hardware and control domains (v5)       - MPU mm subsistem skeleton     * RISC-V:       - introduce basic UART support and interrupts for hypervisor mode * Full list of items : * = Projects = == Hypervisor == * [4.21] xen/console: cleanup console input switch logic (v5)   - Denis Mukhin   - https://lore.kernel.org/xen-devel/20250530231841.73386-1-dmukhin@ford.com/ * [4.21] xen: introduce CONFIG_SYSCTL (v4 -> v8)   -  Penny Zheng   - https://lore.kernel.org/xen-devel/20250711043158.2566880-1-Penny.Zheng@amd.com/ * [4.21] Several CI cleanups and improvements, plus yet another new runner   - Marek Marczykowski-Górecki   - https://lore.kernel.org/xen-devel/cover.7da1777882774486a13e6f39ff4a2096f6b7901e.1744028549.git-series.marmarek@invisiblethingslab.com/   - https://patchew.org/Xen/cover.7da1777882774486a13e6f39ff4a2096f6b7901e.1744028549.git-series.marmarek@invisiblethingslab.com/ * [4.21] automation: Refresh the remaining Debian containers (v2)   -  Javi Merino   - https://lore.kernel.org/xen-devel/cover.1730743077.git.javi.merino@cloud.com/T/#m5d9acb7cf5db3c2be3d6527de14b69b07812314e * [4.21] MSI-X support with qemu in stubdomain, and other related changes (v8)   -  Marek Marczykowski-Górecki   - https://lore.kernel.org/xen-devel/cover.33fb4385b7dd6c53bda4acf0a9e91748b3d7b1f7.1715313192.git-series.marmarek@invisiblethingslab.com/   -  Only automation patch left to be reviewed/merged. * [next-rel(s)] Physical address hypercall ABI ("HVMv2")   - Teddy Astie   - https://lore.kernel.org/xen-devel/cover.1744981654.git.teddy.astie@vates.tech/ * [next-rel(s)] xen: Untangle mm.h   -  Andrew Cooper   - https://lore.kernel.org/xen-devel/20250312174513.4075066-1-andrew.cooper3@citrix.com/   - https://patchew.org/Xen/20250312174513.4075066-1-andrew.cooper3@citrix.com/ * [next-rel(s)] Add support for exact-node memory claims   -  Alejandro Vallejo   - https://lore.kernel.org/xen-devel/20250314172502.53498-1-alejandro.vallejo@cloud.com/   - https://patchew.org/Xen/20250314172502.53498-1-alejandro.vallejo@cloud.com/ * [next-rel(s)] Remove the directmap (v5)   -  Alejandro Vallejo   - https://lore.kernel.org/xen-devel/20250108151822.16030-1-alejandro.vallejo@cloud.com/   - https://patchew.org/Xen/20250108151822.16030-1-alejandro.vallejo@cloud.com/ * [next-rel(s)] GRUB: Supporting Secure Boot of xen.gz (v1)   -  Ross Lagerwall   - https://patchew.org/Xen/20240313150748.791236-1-ross.lagerwall@citrix.com/ * [next-rel(s)] Introduce xenbindgen to autogen hypercall structs (v1)   -  Alejandro Vallejo   - https://patchew.org/Xen/20241115115200.2824-1-alejandro.vallejo@cloud.com/ * [next-rel(s)] Introduce NS8250 UART emulator (v2)   -  Denis Mukhin   - https://patchew.org/Xen/20241205-vuart-ns8250-v1-0-e9aa923127eb@ford.com/ * [next-rel(s)] xen: framework for UART emulators   - Denis Mukhin   - https://lore.kernel.org/xen-devel/20250624035443.344099-1-dmukhin@ford.com/ === x86 === * [4.21] x86/asm: cleanups after toolchain baseline upgrade (v1 -> v2)   - Denis Mukhin   - https://lore.kernel.org/xen-devel/20250403182250.3329498-1-dmukhin@ford.com/   - https://patchew.org/Xen/20250403182250.3329498-1-dmukhin@ford.com/ * [4.21?] x86/efi: Fix booting when NX is disabled (v1 -> v2)   - Andrew Cooper   - https://patchew.org/Xen/20240722101838.3946983-1-andrew.cooper3@citrix.com/   - https://lore.kernel.org/xen-devel/20240722101838.3946983-1-andrew.cooper3@citrix.com/ * [4.21?] Hyperlaunch device tree for dom0 (v6)   - Alejandro Vallejo   - https://patchew.org/Xen/20250429123629.20839-1-agarciav@amd.com/   - https://lore.kernel.org/xen-devel/20250429123629.20839-1-agarciav@amd.com/ *  [4.21?] Boot modules for Hyperlaunch (v9)   -  Daniel P. Smith   - https://lore.kernel.org/xen-devel/20241115131204.32135-1-dpsmith@apertussolutions.com/   - https://patchew.org/Xen/20241115131204.32135-1-dpsmith@apertussolutions.com/ *  [4.21?] Address Space Isolation FPU preparations (v2->v3)   -  Alejandro Vallejo   - https://patchew.org/Xen/20250110132823.24348-1-alejandro.vallejo@cloud.com/ * [next-rel(s)] Hyperlaunch domain builder   - Daniel P. Smith   - https://lore.kernel.org/xen-devel/20250515131744.3843-1-dpsmith@apertussolutions.com/ * [next-rel(s)] Confidential computing and AMD SEV support   - Teddy Astie   - https://patchew.org/Xen/cover.1747312394.git.teddy.astie@vates.tech/   - https://lore.kernel.org/xen-devel/cover.1747312394.git.teddy.astie@vates.tech/ * [next-rel(s)] amd-cppc CPU Performance Scaling Driver (v5 -> v6)   - Penny Zheng   - https://lore.kernel.org/xen-devel/20250711035106.2540522-1-Penny.Zheng@amd.com/ * [next-rel(s)] x86: Trenchboot Secure Launch DRTM (Xen) (v1 -> v3)   - Sergii Dmytruk   - https://patchew.org/Xen/cover.1745172094.git.sergii.dmytruk@3mdeb.com/   - https://lore.kernel.org/xen-devel/cover.1748611041.git.sergii.dmytruk@3mdeb.com/ * [next-rel(s)] x86/EFI: prevent write-execute sections   - Roger Pau Monne   - https://lore.kernel.org/xen-devel/20250401130840.72119-1-roger.pau@citrix.com/ * [next-rel(s)] x86: generate xen.efi image with no write-execute sections   - Roger Pau Monne   - https://lore.kernel.org/xen-devel/20250318173547.59475-1-roger.pau@citrix.com/ *  [next-rel(s)] Expose consistent topology to guests (v7)   -  Alejandro Vallejo   - https://patchew.org/Xen/20241021154600.11745-1-alejandro.vallejo@cloud.com/ *  [next-rel(s)] x86/alternatives: Adjust all insn-relative fields (v2)   -  Andrew Cooper   - https://lore.kernel.org/xen-devel/20241002152725.1841575-1-andrew.cooper3@citrix.com/T/#mac2deaea7e02a343210d61887486433d946ad129 *  [next-rel(s)] x86emul: misc additions (v7)   -  Jan Beulich   - https://patchew.org/Xen/3a25cd59-e1cb-4bfc-b868-fb11599d22f5@suse.com/ *  [next-rel(s)] x86: support AVX10 (v3)   -  Jan Beulich   - https://lore.kernel.org/xen-devel/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@suse.com/   - https://patchew.org/Xen/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@suse.com/ *  [next-rel(s)] VT-d: SATC handling; ATS: tidying (v2)   -  Jan Beulich   - https://patchew.org/Xen/64b028be-2197-4951-ae5b-32f9eabfa84a@suse.com/ *  [next-rel(s)] x86: parallelize AP bring-up during boot (v1)   -  Krystian Hebel   - https://lore.kernel.org/xen-devel/cover.1699982111.git.krystian.hebel@3mdeb.com/ *  [next-rel(s)] x86/spec-ctrl: IBPB improvements (v4)   -  Jan Beulich   - https://patchew.org/Xen/06591b64-2f05-a4cc-a2f3-a74c3c4a76d6@suse.com/ *  [next-rel(s)] Move some boot code from assembly to C (v2)   -  Frediano Ziglio   - https://lore.kernel.org/xen-devel/20241122093358.478774-1-frediano.ziglio@cloud.com/   - https://patchew.org/Xen/20241122093358.478774-1-frediano.ziglio@cloud.com/ *  [next-rel(s)]amd-pstate CPU Performance Scaling Driver (v1)   -  Penny Zheng   - https://patchew.org/Xen/20241203081111.463400-1-Penny.Zheng@amd.com/   - https://lore.kernel.org/xen-devel/593baee2-9bf1-4db4-86e8-015cae48dc1a@suse.com/ * [next-rel(s)] x86: adventures in Address Space Isolation   - Roger Pau Monne   - https://lore.kernel.org/xen-devel/20250108142659.99490-1-roger.pau@citrix.com/ === ARM === * [4.21?] MPU mm subsistem skeleton   - Luca Fancellu   - https://lore.kernel.org/xen-devel/20250312135258.1815706-1-luca.fancellu@arm.com/   - https://patchew.org/Xen/20250312135258.1815706-1-luca.fancellu@arm.com/ * [4.21?] Add initial Xen Suspend-to-RAM support on ARM64 (v4)   - Mykola Kvach   - https://lore.kernel.org/xen-devel/cover.1748848482.git.mykola_kvach@epam.com/ * [4.21?] xen/arm: scmi: introduce SCI SCMI SMC multi-agent support (->v4)   - Oleksii Moisieiev   - https://lore.kernel.org/xen-devel/cover.1753184487.git.oleksii_moisieiev@epam.com/ * [next-rel(s)] FF-A VM to VM support (v6)   - Bertrand Marquis   - https://lore.kernel.org/xen-devel/cover.1747925287.git.bertrand.marquis@arm.com/   - https://patchew.org/Xen/cover.1747925287.git.bertrand.marquis@arm.com/ *  [next-rel(s)] Add Virtio-PCI for dom0less on ARM (v1)   -  Edgar E. Iglesias   - https://lore.kernel.org/xen-devel/20240924162359.1390487-1-edgar.iglesias@gmail.com/T/#mfa148991b9408f223a079d4cef610244d5b04c2b   - https://patchew.org/Xen/20240924162359.1390487-1-edgar.iglesias@gmail.com/ *  [next-rel(s)] DOMCTL-based guest magic region allocation for 11 domUs (v4)   -  Henry Wang   - https://patchew.org/Xen/20240409045357.236802-1-xin.wang2@amd.com/ === RISCV === * [4.21] xen/riscv: introduce p2m functionality (v1->v3)   - Oleksii Kurochko   - https://lore.kernel.org/xen-devel/cover.1753973161.git.oleksii.kurochko@gmail.com/T/#t === PPC === *  Early Boot Allocation on Power (v5)   -  Shawn Anastasio   - https://lore.kernel.org/xen-devel/cover.1727388925.git.sanastasio@raptorengineering.com/T/#m8cac91a93b56a359fa2d5f08596c4be61dca290d   - https://patchew.org/Xen/cover.1727388925.git.sanastasio@raptorengineering.com/ == Completed == === Hypervisor === * tools: remove qemu-traditional   - Juergen Gross   - https://lore.kernel.org/xen-devel/20250527132035.985-1-jgross@suse.com/ *  remove libxenctrl usage from xenstored (v8)   -  Juergen Gross   - https://lore.kernel.org/xen-devel/20250204113407.16839-1-jgross@suse.com/ * xen/config.h: Move BITS_PER_* definitions from asm/config.h to xen/config.h   - Oleksii Kurochko   - https://lore.kernel.org/xen-devel/6b21fb046cf1c8ca760f5ad72fa3cc13b59c4069.1743092485.git.oleksii.kurochko@gmail.com/ * Move parts of Arm's Dom0less to common code   - Oleksii Kurochko   - https://patchew.org/Xen/cover.1746468003.git.oleksii.kurochko@gmail.com/   - https://lore.kernel.org/xen-devel/cover.1746468003.git.oleksii.kurochko@gmail.com/T/#t === x86 === *  x86: memcpy() / memset() (non-)ERMS flavors plus fallout (v4 -> v5)   -  Jan Beulich   - https://patchew.org/Xen/14b65231-b83b-43fb-bbcf-dec5c07d285b@suse.com/ * kexec: add kexec support to Mini-OS (v1 -> v2)   - Juergen Gross   - https://lore.kernel.org/xen-devel/20250616084619.11112-1-jgross@suse.com/ * [4.21] Allow x86 to unflatten DTs (v8)   - Alejandro Vallejo   - https://lore.kernel.org/xen-devel/20250722000525.7247-1-alejandro.garciavallejo@amd.com/#t * xen: cache control improvements   - Roger Pau Monne   - https://lore.kernel.org/xen-devel/20250506083148.34963-1-roger.pau@citrix.com/ *  x86/HVM: emulation (MMIO) improvements (v3)   -  Jan Beulich   - https://patchew.org/Xen/729f7896-55b7-4b5b-a7e9-6eb0420e0b14@suse.com/ === ARM === * Enable R52 support for the first chunk of MPU support  -  Ayan Kumar Halder  - https://lore.kernel.org/xen-devel/20250619113152.2723066-1-ayan.kumar.halder@amd.com/ * ARM split hardware and control domains (v5)   - Jason Andryuk   - https://lore.kernel.org/xen-devel/20250416212911.410946-1-jason.andryuk@amd.com/   - https://patchew.org/Xen/20250416212911.410946-1-jason.andryuk@amd.com/ * First chunk for Arm R82 and MPU support (v4 -> v6)   - Luca Fancellu   - https://lore.kernel.org/xen-devel/20250523065406.3795420-1-luca.fancellu@arm.com/   - https://patchew.org/Xen/20250523065406.3795420-1-luca.fancellu@arm.com/ * Add support for R-Car Gen4 PCI host controller (v4 -> v5)   - Mykyta Poturai   - https://lore.kernel.org/xen-devel/cover.1747820844.git.mykyta_poturai@epam.com/   - https://patchew.org/Xen/cover.1747820844.git.mykyta._5Fpoturai@epam.com/ * SMMU handling for PCIe Passthrough on ARM (v11 -> v12)   - Mykyta Poturai   - https://lore.kernel.org/xen-devel/cover.1751439885.git.mykyta_poturai@epam.com/ *  PCI devices passthrough on Arm, part 3 (v16->v20->v21)   -  Stewart Hildebrand   - https://patchew.org/Xen/20250508104608.531079-1-stewart.hildebrand@amd.com/   - https://lore.kernel.org/xen-devel/20250508104608.531079-1-stewart.hildebrand@amd.com/ * Enable early bootup of Armv8-R AArch32 systems   - Ayan Kumar Halder   - https://lore.kernel.org/xen-devel/20250414164514.588373-1-ayan.kumar.halder@amd.com/   - https://patchew.org/Xen/20250414164514.588373-1-ayan.kumar.halder@amd.com/ === RISC-V === * riscv: introduce basic UART support and interrupts for hypervisor mode (v2 -> v3)   -  Oleksii Kurochko   - https://lore.kernel.org/xen-devel/cover.1747843009.git.oleksii.kurochko@gmail.com/   - https://patchew.org/Xen/cover.1747843009.git.oleksii.kurochko@gmail.com/ * RISC-V some preinit calls:   -  Oleksii Kurochko   - https://lore.kernel.org/xen-devel/4ddde60347edf6740fbc69b5739d099616f5b5ff.1743165791.git.oleksii.kurochko@gmail.com/ * Fixes for UBSAN & GCOV support for RISC-V:   -  Oleksii Kurochko   - https://lore.kernel.org/xen-devel/9fbb5e1389b84bed2e95f99e4c383d0215c7a524.1744889185.git.oleksii.kurochko@gmail.com/ Have a good week! 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>> >> In case of dom0less boot the "dom0_mem" is not used and defaulted to 0, >> which causes min_low_order to get high value > order and so no allocations >> happens from low memory. >> >> Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" has correct >> memory size in both cases: regular dom0 boot and dom0less boot. >> >> Fixes: 43afe6f030244 ("xen/common: dom0less: introduce common dom0less-build.c") > > I think I introduced this bug with the dom0less hwdom support, and the correct fixes is: > > Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction") > >> Signed-off-by: Grygorii Strashko > > dom0_mem is also mentioned in the comment on line 252.  With that changed as well: > > Reviewed-by: Jason Andryuk Will smth like below be ok? * We first allocate the largest allocation we can as low as we * can. This then becomes the first bank. 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pr=C Message-ID: Date: Tue, 5 Aug 2025 14:39:55 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [XEN][PATCH] xen/dom0less: arm: fix hwdom 1:1 low memory allocation To: Grygorii Strashko , "xen-devel@lists.xenproject.org" CC: Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" References: <20250801155429.1402395-1-grygorii_strashko@epam.com> <7c867f77-3846-4b2a-a028-4dfb248a4fc2@amd.com> <47e51e6d-ea3a-464e-9442-fa5f4329eabc@epam.com> Content-Language: en-US From: Jason Andryuk In-Reply-To: <47e51e6d-ea3a-464e-9442-fa5f4329eabc@epam.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: None (SATLEXMB05.amd.com: jason.andryuk@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF0000020A:EE_|IA1PR12MB6306:EE_ X-MS-Office365-Filtering-Correlation-Id: cd788429-93a5-4df9-b6ef-08ddd44f7b7c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026|7053199007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2025 18:39:59.4412 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd788429-93a5-4df9-b6ef-08ddd44f7b7c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF0000020A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6306 On 2025-08-05 14:38, Grygorii Strashko wrote: > Hi Jason, > > On 05.08.25 20:21, Jason Andryuk wrote: >> On 2025-08-01 11:54, Grygorii Strashko wrote: >>> From: Grygorii Strashko >>> >>> Call stack for dom0less hwdom case (1:1) memory: >>> create_domUs >>> |-construct_domU >>>    |-construct_hwdom() >>>      |-allocate_memory_11() >>> >>> And allocate_memory_11() uses "dom0_mem" as: >>> min_low_order = >>>    get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); >>> >>> In case of dom0less boot the "dom0_mem" is not used and defaulted to 0, >>> which causes min_low_order to get high value > order and so no >>> allocations >>> happens from low memory. >>> >>> Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" has correct >>> memory size in both cases: regular dom0 boot and dom0less boot. >>> >>> Fixes: 43afe6f030244 ("xen/common: dom0less: introduce common >>> dom0less-build.c") >> >> I think I introduced this bug with the dom0less hwdom support, and the >> correct fixes is: >> >> Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction") >> >>> Signed-off-by: Grygorii Strashko >> >> dom0_mem is also mentioned in the comment on line 252.  With that >> changed as well: >> >> Reviewed-by: Jason Andryuk > > > Will smth like below be ok? > >   * We first allocate the largest allocation we can as low as we >   * can. This then becomes the first bank. This bank must be at least > - * 128MB (or dom0_mem if that is smaller). > + * 128MB (or memory size requested for domain if that is smaller). LGTM - Thank you. -Jason From xen-devel-bounces@lists.xenproject.org Tue Aug 05 18:41:02 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 18:41:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070872.1434483 (Exim 4.92) (envelope-from ) id 1ujMas-0003ft-1f; Tue, 05 Aug 2025 18:41:02 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070872.1434483; Tue, 05 Aug 2025 18:41:02 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujMar-0003f1-Sp; Tue, 05 Aug 2025 18:41:01 +0000 Received: by outflank-mailman (input) for mailman id 1070872; Tue, 05 Aug 2025 18:41:00 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujMaq-0003e3-CZ for xen-devel@lists.xenproject.org; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d71c8bb4-a00d-4f7e-d3b4-08ddd44f880d X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Aug 2025 18:40:20.5985 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vLepVwL+sFduqI5NySNLPQfGSavwbB7VxVeZwb2VUsJHQlPfjUAO6nmI3GApBN4VN/Y/7ZOXICoSFlQB5g3jL7/sQfXa4vkYIZNjiIXK52s= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR03MB9719 From: Grygorii Strashko Since commit 341f271cf86f ("xen/evtchn: fully restrict concept of pIRQ for arches with pIRQ support only"), the corresponding Arm arch pIRQ callbacks become unreachable, so drop them. Signed-off-by: Grygorii Strashko Acked-by: Andrew Cooper Reviewed-by: Denis Mukhin --- xen/arch/arm/irq.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 03fbb90c6c43..4bbf0b0664df 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -595,35 +595,6 @@ unlock: return ret; } =20 -/* - * pirq event channels. We don't use these on ARM, instead we use the - * features of the GIC to inject virtualised normal interrupts. - */ -struct pirq *alloc_pirq_struct(struct domain *d) -{ - return NULL; -} - -/* - * These are all unreachable given an alloc_pirq_struct - * which returns NULL, all callers try to lookup struct pirq first - * which will fail. - */ -int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) -{ - BUG(); -} - -void pirq_guest_unbind(struct domain *d, struct pirq *pirq) -{ - BUG(); -} - -void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) -{ - BUG(); -} - static bool irq_validate_new_type(unsigned int curr, unsigned int new) { return (curr =3D=3D IRQ_TYPE_INVALID || curr =3D=3D new ); --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 18:41:02 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 18:41:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070873.1434486 (Exim 4.92) (envelope-from ) id 1ujMas-0003n7-Cu; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6d8b61c2-a3c5-4535-6ad8-08ddd44f88ba X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Aug 2025 18:40:21.0006 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GzTWbXlh1uecGRtza6qgW/tLmAJyk/GqJpXVJRB8vvZRvzSzunk4IAYl4XG6yuMqHPMMtH+ApL7qnT0gy+youoKrkEZKiUZ27PgbHJQajM8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR03MB9719 From: Grygorii Strashko Since commit 341f271cf86f ("xen/evtchn: fully restrict concept of pIRQ for arches with pIRQ support only"), the corresponding PPC arch pIRQ callbacks become unreachable, so drop them. Signed-off-by: Grygorii Strashko Acked-by: Andrew Cooper Reviewed-by: Denis Mukhin --- xen/arch/ppc/stubs.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c index 671e71aa0a60..bdaf474c5cc0 100644 --- a/xen/arch/ppc/stubs.c +++ b/xen/arch/ppc/stubs.c @@ -103,26 +103,6 @@ void smp_send_call_function_mask(const cpumask_t *mask= ) =20 /* irq.c */ =20 -struct pirq *alloc_pirq_struct(struct domain *d) -{ - BUG_ON("unimplemented"); -} - -int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) -{ - BUG_ON("unimplemented"); -} - -void pirq_guest_unbind(struct domain *d, struct pirq *pirq) -{ - BUG_ON("unimplemented"); -} - -void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) -{ - BUG_ON("unimplemented"); -} - void irq_ack_none(struct irq_desc *desc) { BUG_ON("unimplemented"); --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 18:41:04 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 18:41:04 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070874.1434502 (Exim 4.92) (envelope-from ) id 1ujMau-0004AS-LV; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0cc8db13-9a66-4fa1-9cfc-08ddd44f88ee X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Aug 2025 18:40:21.2865 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /c4annAsyGcyrfBdgHYHfh7OUPSahH6894Ke9kUaNM1Sk7LoyKgrXDjd8UG+Mq7i/ZHuXdG1oCKQH3bN7iSeBrBd7BfMMgr77Qe4f6tyyWU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR03MB9719 From: Grygorii Strashko Since commit 341f271cf86f ("xen/evtchn: fully restrict concept of pIRQ for arches with pIRQ support only"), the corresponding RISCV arch pIRQ callbacks become unreachable, so drop them. Signed-off-by: Grygorii Strashko Reviewed-by: Oleksii Kurochko Acked-by: Andrew Cooper Reviewed-by: Denis Mukhin --- xen/arch/riscv/stubs.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 8918cebf35c6..1a8c86cd8da2 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -82,26 +82,6 @@ void smp_send_call_function_mask(const cpumask_t *mask) =20 /* irq.c */ =20 -struct pirq *alloc_pirq_struct(struct domain *d) -{ - BUG_ON("unimplemented"); -} - -int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) -{ - BUG_ON("unimplemented"); -} - -void pirq_guest_unbind(struct domain *d, struct pirq *pirq) -{ - BUG_ON("unimplemented"); -} - -void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) -{ - BUG_ON("unimplemented"); -} - void irq_ack_none(struct irq_desc *desc) { BUG_ON("unimplemented"); --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 18:47:06 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 18:47:06 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070891.1434512 (Exim 4.92) (envelope-from ) id 1ujMgg-0005Sl-8h; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fc36a8cd-bb93-4127-af40-08ddd44f87c1 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Aug 2025 18:40:20.0964 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JRareoB5rwAerrtb19xvx7rcpIHbA2cqIxJe1bZv7phBjgMfD/29Wwwksd4OIZirk2vOXt4B1MVwFmkI0Nu2UTwuDzU+vq5MW1/4IIfmH1E= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR03MB9719 From: Grygorii Strashko Hence prerequisite patch was merged [1] arch specific pIRQ callback can now be dropped for arches without pIRQ support as those callback become unreach= able. [1] commit 341f271cf86f ("xen/evtchn: fully restrict concept of pIRQ for ar= ches with pIRQ support only") Changes in v2: - reworded commit messages as requested - added reviewer's tags Grygorii Strashko (3): xen/arm: irq: drop unreachable pirq callbacks xen/ppc: irq: drop unreachable pirq callbacks xen/riscv: irq: drop unreachable pirq callbacks xen/arch/arm/irq.c | 29 ----------------------------- xen/arch/ppc/stubs.c | 20 -------------------- xen/arch/riscv/stubs.c | 20 -------------------- 3 files changed, 69 deletions(-) --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 19:00:35 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 19:00:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070914.1434522 (Exim 4.92) (envelope-from ) id 1ujMtg-0000AQ-FK; Tue, 05 Aug 2025 19:00:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070914.1434522; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 305bffee-1589-4ed8-fddf-08ddd452526a X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Aug 2025 19:00:19.1440 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: CyVVqVq5KQ4ZT3LNHqr2YXWmAM7HHYh1QC+ifzquvfgkYjYSZOpF7OJvY3K0evi3UASIDO4E4CcHf3NLMgn35kurTkBqFnMSDtrFUVzjSCw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR03MB9345 From: Grygorii Strashko Call stack for dom0less hwdom case (1:1) memory: create_domUs |-construct_domU |-construct_hwdom() |-allocate_memory_11() And allocate_memory_11() uses "dom0_mem" as: min_low_order =3D get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); In case of dom0less boot the "dom0_mem" is not used and defaulted to 0, which causes min_low_order to get high value > order and so no allocations happens from low memory. Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" has correct memory size in both cases: regular dom0 boot and dom0less boot. Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction") Signed-off-by: Grygorii Strashko Reviewed-by: Denis Mukhin Reviewed-by: Jason Andryuk --- Changes in v2: - changed 'fixes' tag - fixed comment for allocate_memory_11() - added reviewer's tags xen/arch/arm/domain_build.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 463ae4474d30..a9e4153e3cf9 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -249,7 +249,7 @@ fail: * * We first allocate the largest allocation we can as low as we * can. This then becomes the first bank. This bank must be at least - * 128MB (or dom0_mem if that is smaller). + * 128MB (or memory size requested for domain if that is smaller). * * Then we start allocating more memory, trying to allocate the * largest possible size and trying smaller sizes until we @@ -278,7 +278,7 @@ static void __init allocate_memory_11(struct domain *d, struct kernel_info *kinfo) { const unsigned int min_low_order =3D - get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); + get_order_from_bytes(min_t(paddr_t, kinfo->unassigned_mem, MB(128)= )); const unsigned int min_order =3D get_order_from_bytes(MB(4)); struct membanks *mem =3D kernel_info_get_mem(kinfo); struct page_info *pg; --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Tue Aug 05 20:13:44 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 20:13:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070941.1434532 (Exim 4.92) (envelope-from ) id 1ujO2N-0001Oe-50; Tue, 05 Aug 2025 20:13:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070941.1434532; Tue, 05 Aug 2025 20:13:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujO2N-0001OX-25; Tue, 05 Aug 2025 20:13:31 +0000 Received: by outflank-mailman (input) for mailman id 1070941; Tue, 05 Aug 2025 20:13:29 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujO2L-0001OR-OI for xen-devel@lists.xenproject.org; Tue, 05 Aug 2025 20:13:29 +0000 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [2a00:1450:4864:20::334]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id a6824bd6-7238-11f0-a322-13f23c93f187; Tue, 05 Aug 2025 22:13:28 +0200 (CEST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4561ed868b5so39743185e9.0 for ; Tue, 05 Aug 2025 13:13:28 -0700 (PDT) Received: from [192.168.1.183] (host-195-149-20-212.as13285.net. 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Tue, 05 Aug 2025 13:13:28 -0700 (PDT) Message-ID: Date: Tue, 5 Aug 2025 21:13:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] x86/mm: drop paging_get_mode() To: Jan Beulich , "xen-devel@lists.xenproject.org" Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Penny Zheng References: <0c75ef27-7584-4e56-9ead-6bb0274ce3eb@suse.com> Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: <0c75ef27-7584-4e56-9ead-6bb0274ce3eb@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05/08/2025 8:58 am, Jan Beulich wrote: > The function was introduced without any caller, and never gained any. > Thus it has always been violating Misra rule 2.1 (unreachable code). > > Fixes: dd6de3ab9985 ("Implement Nested-on-Nested") > Signed-off-by: Jan Beulich Acked-by: Andrew Cooper I'm still not certain how this will shake out in nested-virt, but I'm reasonably sure it wont end up like this. ~Andrew From xen-devel-bounces@lists.xenproject.org Tue Aug 05 20:24:58 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 20:24:58 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070949.1434542 (Exim 4.92) (envelope-from ) id 1ujODN-00034w-4a; Tue, 05 Aug 2025 20:24:53 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070949.1434542; Tue, 05 Aug 2025 20:24:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujODN-00034p-1J; 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Tue, 05 Aug 2025 20:57:39 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=o5t2772qYlHXuqpkP22SCJqrItlXUcR8aQnEFbjnkDE=; b=VqDfVeL9NJ8HprYj1Lx1h5HaDo SCz71mMjx0dxc+P/KsF1r8ybAwU4G/lHBe9dAEHpRIHFeMuf3rC2IT6ESng+0tFeQ2XHd20q9ffcN xuVbTQcPn/tw5iUagGEc837K+nzxvj/XBJauVk394jZxvJfukCEx+L5l3vH4ek/i6V/Y=; Message-ID: <7ca43ebb-5944-4542-89d4-9f826997d2a5@xen.org> Date: Tue, 5 Aug 2025 21:57:37 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] xen/arm: irq: drop unreachable pirq callbacks Content-Language: en-GB To: Grygorii Strashko , "xen-devel@lists.xenproject.org" Cc: Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Denis Mukhin References: <20250805184003.202839-1-grygorii_strashko@epam.com> <20250805184003.202839-2-grygorii_strashko@epam.com> From: Julien Grall In-Reply-To: <20250805184003.202839-2-grygorii_strashko@epam.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, On 05/08/2025 19:40, Grygorii Strashko wrote: > From: Grygorii Strashko > > Since commit 341f271cf86f ("xen/evtchn: fully restrict concept of pIRQ for > arches with pIRQ support only"), the corresponding Arm arch pIRQ callbacks > become unreachable, so drop them. > > Signed-off-by: Grygorii Strashko > Acked-by: Andrew Cooper > Reviewed-by: Denis Mukhin Acked-by: Julien Grall Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Tue Aug 05 21:07:37 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Tue, 05 Aug 2025 21:07:37 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1070982.1434561 (Exim 4.92) (envelope-from ) id 1ujOsf-0000Vd-Fu; Tue, 05 Aug 2025 21:07:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1070982.1434561; Tue, 05 Aug 2025 21:07:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujOsf-0000VW-DL; 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c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=SlCOk/8WqC6UuveQSRLxilIMD74FmsC3e2Z9QycD6FE=; b=QvhKoaXmSJOlTAEV4bjqQ5ipSs xK4QGRcyG51qF6A4CMubsBNVS1IcaDVIR6RgsoXUSg9dZuK24plPVX1BKE9IbnDdAw0OOe5HEHJSM O5EMIYMK6Lua4Bh06xFWYl04Ks7GhIhTJIUBBItqnHD6k5e8D6+sADytqz6zzziXAC1g=; Message-ID: <5807ed03-7db2-4ce6-9acf-c4d515fbd293@xen.org> Date: Tue, 5 Aug 2025 22:07:28 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen/dom0less: arm: fix hwdom 1:1 low memory allocation Content-Language: en-GB To: Grygorii Strashko , "xen-devel@lists.xenproject.org" Cc: Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Denis Mukhin , Jason Andryuk References: <20250805190017.209711-1-grygorii_strashko@epam.com> From: Julien Grall In-Reply-To: <20250805190017.209711-1-grygorii_strashko@epam.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Grygorii, On 05/08/2025 20:00, Grygorii Strashko wrote: > From: Grygorii Strashko > > Call stack for dom0less hwdom case (1:1) memory: > create_domUs > |-construct_domU > |-construct_hwdom() > |-allocate_memory_11() > > And allocate_memory_11() uses "dom0_mem" as: > min_low_order = > get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); > > In case of dom0less boot the "dom0_mem" is not used and defaulted to 0, From docs/mics/xen-command-linux.pandoc: --- ### dom0_mem (ARM) > `= ` Set the amount of memory for the initial domain (dom0). It must be greater than zero. This parameter is required. --- If dom0_mem is effectively optional, then shouldn't the doc be updated? > which causes min_low_order to get high value > order and so no allocations > happens from low memory. > > Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" has correct > memory size in both cases: regular dom0 boot and dom0less boot. > > Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction") > Signed-off-by: Grygorii Strashko > Reviewed-by: Denis Mukhin > Reviewed-by: Jason Andryuk Acked-by: Julien Grall Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Wed Aug 06 02:32:20 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 02:32:20 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071073.1434612 (Exim 4.92) (envelope-from ) id 1ujTwh-0006Ib-Jq; Wed, 06 Aug 2025 02:32:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071073.1434612; Wed, 06 Aug 2025 02:32:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujTwh-0006IT-EK; Wed, 06 Aug 2025 02:32:03 +0000 Received: by outflank-mailman (input) for mailman id 1071073; Wed, 06 Aug 2025 02:32:02 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujTwg-0006IN-UW for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 02:32:02 +0000 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 84796c7e-726d-11f0-a322-13f23c93f187; Wed, 06 Aug 2025 04:32:00 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.88.194]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4bxZ3V1z9wz13N1Z; Wed, 6 Aug 2025 10:28:38 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 0C3F3140146; Wed, 6 Aug 2025 10:31:53 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 6 Aug 2025 10:31:51 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 84796c7e-726d-11f0-a322-13f23c93f187 Message-ID: <36bd2bb2-31c8-e38f-e420-407742ccc3cc@huawei.com> Date: Wed, 6 Aug 2025 10:31:34 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH -next v7 1/7] arm64: ptrace: Replace interrupts_enabled() with regs_irqs_disabled() Content-Language: en-US To: Ada Couprie Diaz CC: , , , , , , , , , , , , , , , , , , References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-2-ruanjinjie@huawei.com> From: Jinjie Ruan In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.109.254] X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To dggpemf500011.china.huawei.com (7.185.36.131) On 2025/8/5 23:05, Ada Couprie Diaz wrote: > On 29/07/2025 02:54, Jinjie Ruan wrote: > >> The generic entry code expects architecture code to provide >> regs_irqs_disabled(regs) function, but arm64 does not have this and >> provides inerrupts_enabled(regs), which has the opposite polarity. > Nit: "interrupts_enabled(regs)" Good catch! thank you for the review. >> In preparation for moving arm64 over to the generic entry code, >> relace arm64's interrupts_enabled() with regs_irqs_disabled() and >> update its callers under arch/arm64. >> >> For the moment, a definition of interrupts_enabled() is provided for >> the GICv3 driver. Once arch/arm implement regs_irqs_disabled(), this >> can be removed. >> >> Delete the fast_interrupts_enabled() macro as it is unused and we >> don't want any new users to show up. >> >> No functional changes. >> >> Acked-by: Mark Rutland >> Suggested-by: Mark Rutland >> Signed-off-by: Jinjie Ruan >> --- > Otherwise looks good to me ! > Reviewed-by: Ada Couprie Diaz > From xen-devel-bounces@lists.xenproject.org Wed Aug 06 02:49:44 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 02:49:44 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071082.1434622 (Exim 4.92) (envelope-from ) id 1ujUDj-00086p-U8; Wed, 06 Aug 2025 02:49:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071082.1434622; Wed, 06 Aug 2025 02:49:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujUDj-00086i-QS; Wed, 06 Aug 2025 02:49:39 +0000 Received: by outflank-mailman (input) for mailman id 1071082; Wed, 06 Aug 2025 02:49:39 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujUDj-00086c-6I for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 02:49:39 +0000 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id f74b368c-726f-11f0-b898-0df219b8e170; Wed, 06 Aug 2025 04:49:32 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.163.252]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4bxZQV4lLmz14MLW; Wed, 6 Aug 2025 10:45:06 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 3E366180B54; Wed, 6 Aug 2025 10:49:23 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 6 Aug 2025 10:49:21 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f74b368c-726f-11f0-b898-0df219b8e170 Message-ID: <6825c4c4-2c48-db3b-55e2-97922f25897f@huawei.com> Date: Wed, 6 Aug 2025 10:49:21 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH -next v7 2/7] arm64: entry: Refactor the entry and exit for exceptions from EL1 Content-Language: en-US To: Ada Couprie Diaz CC: , , , , , , , , , , , , , , , , , , References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-3-ruanjinjie@huawei.com> From: Jinjie Ruan In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.109.254] X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To dggpemf500011.china.huawei.com (7.185.36.131) On 2025/8/5 23:06, Ada Couprie Diaz wrote: > Hi, > > On 29/07/2025 02:54, Jinjie Ruan wrote: > >> The generic entry code uses irqentry_state_t to track lockdep and RCU >> state across exception entry and return. For historical reasons, arm64 >> embeds similar fields within its pt_regs structure. >> >> In preparation for moving arm64 over to the generic entry code, pull >> these fields out of arm64's pt_regs, and use a separate structure, >> matching the style of the generic entry code. >> >> No functional changes. > As far as I understand and checked, we used the two fields > in an exclusive fashion, so there is indeed no functional change. >> Suggested-by: Mark Rutland >> Signed-off-by: Jinjie Ruan >> --- >> [...] >> diff --git a/arch/arm64/kernel/entry-common.c >> b/arch/arm64/kernel/entry-common.c >> index 8e798f46ad28..97e0741abde1 100644 >> --- a/arch/arm64/kernel/entry-common.c >> +++ b/arch/arm64/kernel/entry-common.c >> [...] >> @@ -475,73 +497,81 @@ UNHANDLED(el1t, 64, error) >>   static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr) >>   { >>       unsigned long far = read_sysreg(far_el1); >> +    arm64_irqentry_state_t state; >>   -    enter_from_kernel_mode(regs); >> +    state = enter_from_kernel_mode(regs); > Nit: There is some inconsistencies with some functions splitting state's > definition > and declaration (like el1_abort here), while some others do it on the > same line > (el1_undef() below for example). > In some cases it is welcome as the entry function is called after some > other work, > but here for example it doesn't seem to be beneficial ? Both methods can keep the modifications to `enter_from_kernel_mode()` on the same line as the original code, which will facilitate code review. I think it is also fine to do it on the same line here, which can reduce one line code, which method is better may be a matter of personal opinion. >>       local_daif_inherit(regs); >>       do_mem_abort(far, esr, regs); >>       local_daif_mask(); >> -    exit_to_kernel_mode(regs); >> +    exit_to_kernel_mode(regs, state); >>   } >>     static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr) >>   { >>       unsigned long far = read_sysreg(far_el1); >> +    arm64_irqentry_state_t state; >>   -    enter_from_kernel_mode(regs); >> +    state = enter_from_kernel_mode(regs); >>       local_daif_inherit(regs); >>       do_sp_pc_abort(far, esr, regs); >>       local_daif_mask(); >> -    exit_to_kernel_mode(regs); >> +    exit_to_kernel_mode(regs, state); >>   } >>     static void noinstr el1_undef(struct pt_regs *regs, unsigned long >> esr) >>   { >> -    enter_from_kernel_mode(regs); >> +    arm64_irqentry_state_t state = enter_from_kernel_mode(regs); >> + >>       local_daif_inherit(regs); >>       do_el1_undef(regs, esr); >>       local_daif_mask(); >> -    exit_to_kernel_mode(regs); >> +    exit_to_kernel_mode(regs, state); >>   } >> >> [...] > Other than the small nit: > Reviewed-by: Ada Couprie Diaz > > From xen-devel-bounces@lists.xenproject.org Wed Aug 06 03:35:39 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 03:35:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071092.1434632 (Exim 4.92) (envelope-from ) id 1ujUw4-0005sX-7s; Wed, 06 Aug 2025 03:35:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071092.1434632; Wed, 06 Aug 2025 03:35:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujUw4-0005sQ-4S; Wed, 06 Aug 2025 03:35:28 +0000 Received: by outflank-mailman (input) for mailman id 1071092; Wed, 06 Aug 2025 03:35:26 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujUw2-0005s4-E5 for xen-devel@lists.xenproject.org; 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charset="iso-8859-1" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL1PR12MB5849.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 655af769-e08f-47cd-2f2f-08ddd49a4182 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2025 03:35:14.5233 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WS3PprTymW1ED2hs3vPczWtDSbDeXtlw9fxhW30K5eQUj3RdeggS9q/c2fOTBZCCg60m+g0ji288gfrInoxhbw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ5PPFE4FC9FAB3 On 2025/8/5 16:43, Jan Beulich wrote: > On 05.08.2025 05:49, Jiqian Chen wrote: >> --- a/xen/drivers/vpci/msix.c >> +++ b/xen/drivers/vpci/msix.c >> @@ -655,6 +655,48 @@ int vpci_make_msix_hole(const struct pci_dev *pdev) >> return 0; >> } >> =20 >> +static int cf_check cleanup_msix(const struct pci_dev *pdev) >> +{ >> + int rc; >> + struct vpci *vpci =3D pdev->vpci; >> + const unsigned int msix_pos =3D pdev->msix_pos; >> + >> + if ( !msix_pos ) >> + return 0; >> + >> + rc =3D vpci_remove_registers(vpci, msix_control_reg(msix_pos), 2); >> + if ( rc ) >> + { >> + printk(XENLOG_ERR "%pd %pp: fail to remove MSIX handlers rc=3D%= d\n", >> + pdev->domain, &pdev->sbdf, rc); >> + ASSERT_UNREACHABLE(); >> + return rc; >> + } >> + >> + if ( vpci->msix ) >> + { >> + list_del(&vpci->msix->next); >> + for ( unsigned int i =3D 0; i < ARRAY_SIZE(vpci->msix->table); = i++ ) >> + if ( vpci->msix->table[i] ) >> + iounmap(vpci->msix->table[i]); >> + >> + XFREE(vpci->msix); >> + } >> + >> + /* >> + * The driver may not traverse the capability list and think device >> + * supports MSIX by default. So here let the control register of MS= IX >> + * be Read-Only is to ensure MSIX disabled. >> + */ >> + rc =3D vpci_add_register(vpci, vpci_hw_read16, NULL, >> + msix_control_reg(msix_pos), 2, NULL); >> + if ( rc ) >> + printk(XENLOG_ERR "%pd %pp: fail to add MSIX ctrl handler rc=3D= %d\n", >> + pdev->domain, &pdev->sbdf, rc); >=20 > Here as well as for MSI: Wouldn't this better be limited to the init-fail= ure > case? No point in adding a register hook (and possibly emitting a mislead= ing > log message) when we're tearing down anyway. IOW I think the ->cleanup() > hook needs a boolean parameter, unless the distinction of the two cases c= an > be (reliably) inferred from some other property. To make these changes, can I add a new patch as the last patch of this seri= es? And the new patch will do: 1. add a boolean parameter for cleanup hook to separate whose calls cleanup= (during initialization or during deassign device). 2. call all cleanup hooks in vpci_deassign_device(). 3. remove the MSI/MSIX specific free actions in vpci_deassign_device(). >=20 >> --- a/xen/drivers/vpci/vpci.c >> +++ b/xen/drivers/vpci/vpci.c >> @@ -321,6 +321,27 @@ void vpci_deassign_device(struct pci_dev *pdev) >> &pdev->domain->vpci_dev_assigned_map); >> #endif >> =20 >> + for ( i =3D 0; i < NUM_VPCI_INIT; i++ ) >> + { >> + const vpci_capability_t *capability =3D &__start_vpci_array[i]; >> + const unsigned int cap =3D capability->id; >> + unsigned int pos =3D 0; >> + >> + if ( !capability->is_ext ) >> + pos =3D pci_find_cap_offset(pdev->sbdf, cap); >> + else if ( is_hardware_domain(pdev->domain) ) >> + pos =3D pci_find_ext_capability(pdev->sbdf, cap); >> + >> + if ( pos && capability->cleanup ) >> + { >> + int rc =3D capability->cleanup(pdev); >> + if ( rc ) >> + printk(XENLOG_ERR "%pd %pp: clean %s cap %u fail rc=3D%= d\n", >> + pdev->domain, &pdev->sbdf, >> + capability->is_ext ? "extended" : "legacy", cap,= rc); >> + } >> + } >=20 > With this imo the patch subject is now wrong, too. >=20 > Jan --=20 Best regards, Jiqian Chen. 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Wed, 6 Aug 2025 00:30:59 -0400 (EDT) (envelope-from ehem@m5p.com) Received: (from ehem@localhost) by m5p.com (8.18.1/8.15.2/Submit) id 5764Up9t006239; Tue, 5 Aug 2025 21:30:51 -0700 (PDT) (envelope-from ehem) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 35b26d50-727e-11f0-a322-13f23c93f187 Date: Tue, 5 Aug 2025 21:30:51 -0700 From: Elliott Mitchell To: Paul Leiber Cc: xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org, Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: Consider changing CONFIG_ACPI default on ARM? (was: Re: Xen bootup: issue with Raspberry Pi 5?) Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=0.4 required=10.0 tests=KHOP_HELO_FCRDNS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on mattapan.m5p.com Sigh, resending as I lost some of the intended Cc targets when originally creating the message. Sorry about the duplication for people who have already seen, but I thought this might be worthy of wider discussion. I would like to draw the attention of a few people on xen-devel to the thread which occured on xen-users recently and quoted below: https://lists.xenproject.org/archives/html/xen-users/2025-07/msg00001.html On Tue, Jul 01, 2025 at 10:01:13PM +0200, Paul Leiber wrote: > > Unfortunately, I don't have a direct answer to the question (as is so often > the case, due to my limited knowledge and experience). However, I am > successfully running Xen on a RPi 4 (mostly, except for some VLAN related > networking issues). > > I used instructions in [1] to install vanilla Debian on the RPi, including > UEFI boot and grub. I then compiled Xen with expert options and ACPI > enabled. > > I don't know if there are better solutions. For example, I suffer from the > fact that I2C doesn't work when using UEFI boot on a RPi. Nowadays, Debian > provides their own vanilla Debian images for RPi and with working I2C, but > these images are using a different boot method that I didn't know how to use > with Xen. So far, the procedure described above seems to be the easiest > solution for me. > [1] https://forums.raspberrypi.com/viewtopic.php?t=282839 > > Am 30.06.2025 um 12:35 schrieb Sumit Semwal: > > > > I've just begun to experiment with the Raspberry Pi 5, trying to run a > > simple xen + Dom0 setup, using uBoot, and the bookworm based Rpi > > distro. > > > > I've tried combinations of the following setup: > > > > 1. prebuilt Rpi5 kernel + dtbs, and have also tried to build them from > > source [1] > > 2. Xen from upstream [2] and xen-troops [3] > > 3. upstream uBoot from [4] > > > > but with the same result: [short log below; I can provide a fuller log > > if needed] > > > > (XEN) DT: ** translation for device /axi/msi-controller@1000130000 ** > > (XEN) DT: bus is default (na=2, ns=2) on /axi > > (XEN) DT: translating address:<3> 000000ff<3> fffff000<3> > > (XEN) DT: parent bus is default (na=2, ns=1) on / > > (XEN) DT: walking ranges... > > (XEN) DT: default map, cp=0, s=1000000000, da=fffffff000 > > (XEN) DT: default map, cp=1000000000, s=100000000, da=fffffff000 > > (XEN) DT: default map, cp=1400000000, s=400000000, da=fffffff000 > > (XEN) DT: default map, cp=1800000000, s=400000000, da=fffffff000 > > (XEN) DT: default map, cp=1c00000000, s=400000000, da=fffffff000 > > (XEN) DT: not found ! > > (XEN) Unable to retrieve address 1 for /axi/msi-controller@1000130000 > > (XEN) Device tree generation failed (-22). > > (XEN) debugtrace_dump() global buffer starting > > 1 cpupool_create(pool=0,sched=6) > > 2 Created cpupool 0 with scheduler SMP Credit Scheduler rev2 (credit2) > > 3 cpupool_add_domain(dom=0,pool=0) n_dom 1 rc 0 > > (XEN) wrap: 0 > > (XEN) debugtrace_dump() global buffer finished > > (XEN) > > (XEN) **************************************** > > (XEN) Panic on CPU 0: > > (XEN) Could not set up DOM0 guest OS (rc = -22) > > (XEN) **************************************** > > > > > > I'm certain I'm missing something, but before I delve deeper, I just > > wanted to ask if this is a known issue, and if so, are there any > > workarounds or solutions available for this? > > > > Any help about this is highly appreciated! > > > > Thanks and Best regards, > > Sumit. > > > > [1]: https://github.com/raspberrypi/linux rpi-6.12.y branch > > [2]: git://xenbits.xen.org/xen.git - main branch > > [3] xen-troops https://github.com/xen-troops/xen - rpi5_dev branch > > [4]: https://github.com/u-boot/u-boot.git master branch Ultimately Debian is choosing to leave most defaults alone. So far the Xen developers have left CONFIG_ACPI defaulting to off on ARM*. The Debian project doesn't have paid people to support Raspberry PI hardware, despite being rather common. As a result there aren't any official Raspberry PI images, but people associated with Tianocore have gotten generic images to boot on Raspberry PI hardware. I'm unsure of the likelihood of getting the Debian maintainers to override the default. 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Smith" , Grygorii Strashko , Alejandro Vallejo , "committers@xenproject.org" , Community Manager , Xen-devel References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05.08.2025 20:19, Oleksii Kurochko wrote: > * Full list of items : * > > = Projects = > > == Hypervisor == > > * [4.21] xen/console: cleanup console input switch logic (v5) >   - Denis Mukhin >   - > https://lore.kernel.org/xen-devel/20250530231841.73386-1-dmukhin@ford.com/ > > * [4.21] xen: introduce CONFIG_SYSCTL (v4 -> v8) >   -  Penny Zheng >   - > https://lore.kernel.org/xen-devel/20250711043158.2566880-1-Penny.Zheng@amd.com/ > > * [4.21] Several CI cleanups and improvements, plus yet another new runner >   - Marek Marczykowski-Górecki >   - > https://lore.kernel.org/xen-devel/cover.7da1777882774486a13e6f39ff4a2096f6b7901e.1744028549.git-series.marmarek@invisiblethingslab.com/ >   - > https://patchew.org/Xen/cover.7da1777882774486a13e6f39ff4a2096f6b7901e.1744028549.git-series.marmarek@invisiblethingslab.com/ > > * [4.21] automation: Refresh the remaining Debian containers (v2) >   -  Javi Merino >   - > https://lore.kernel.org/xen-devel/cover.1730743077.git.javi.merino@cloud.com/T/#m5d9acb7cf5db3c2be3d6527de14b69b07812314e > > * [4.21] MSI-X support with qemu in stubdomain, and other related > changes (v8) >   -  Marek Marczykowski-Górecki >   - > https://lore.kernel.org/xen-devel/cover.33fb4385b7dd6c53bda4acf0a9e91748b3d7b1f7.1715313192.git-series.marmarek@invisiblethingslab.com/ >   -  Only automation patch left to be reviewed/merged. > > * [next-rel(s)] Physical address hypercall ABI ("HVMv2") >   - Teddy Astie >   - > https://lore.kernel.org/xen-devel/cover.1744981654.git.teddy.astie@vates.tech/ > > * [next-rel(s)] xen: Untangle mm.h >   -  Andrew Cooper >   - > https://lore.kernel.org/xen-devel/20250312174513.4075066-1-andrew.cooper3@citrix.com/ >   - > https://patchew.org/Xen/20250312174513.4075066-1-andrew.cooper3@citrix.com/ > > * [next-rel(s)] Add support for exact-node memory claims >   -  Alejandro Vallejo >   - > https://lore.kernel.org/xen-devel/20250314172502.53498-1-alejandro.vallejo@cloud.com/ >   - > https://patchew.org/Xen/20250314172502.53498-1-alejandro.vallejo@cloud.com/ > > * [next-rel(s)] Remove the directmap (v5) >   -  Alejandro Vallejo >   - > https://lore.kernel.org/xen-devel/20250108151822.16030-1-alejandro.vallejo@cloud.com/ >   - > https://patchew.org/Xen/20250108151822.16030-1-alejandro.vallejo@cloud.com/ > > * [next-rel(s)] GRUB: Supporting Secure Boot of xen.gz (v1) >   -  Ross Lagerwall >   - > https://patchew.org/Xen/20240313150748.791236-1-ross.lagerwall@citrix.com/ > > * [next-rel(s)] Introduce xenbindgen to autogen hypercall structs (v1) >   -  Alejandro Vallejo >   - > https://patchew.org/Xen/20241115115200.2824-1-alejandro.vallejo@cloud.com/ > > * [next-rel(s)] Introduce NS8250 UART emulator (v2) >   -  Denis Mukhin >   - > https://patchew.org/Xen/20241205-vuart-ns8250-v1-0-e9aa923127eb@ford.com/ > > * [next-rel(s)] xen: framework for UART emulators >   - Denis Mukhin >   - > https://lore.kernel.org/xen-devel/20250624035443.344099-1-dmukhin@ford.com/ > > === x86 === > * [4.21] x86/asm: cleanups after toolchain baseline upgrade (v1 -> v2) >   - Denis Mukhin >   - > https://lore.kernel.org/xen-devel/20250403182250.3329498-1-dmukhin@ford.com/ >   - https://patchew.org/Xen/20250403182250.3329498-1-dmukhin@ford.com/ > > * [4.21?] x86/efi: Fix booting when NX is disabled (v1 -> v2) >   - Andrew Cooper >   - > https://patchew.org/Xen/20240722101838.3946983-1-andrew.cooper3@citrix.com/ >   - > https://lore.kernel.org/xen-devel/20240722101838.3946983-1-andrew.cooper3@citrix.com/ > > * [4.21?] Hyperlaunch device tree for dom0 (v6) >   - Alejandro Vallejo >   - https://patchew.org/Xen/20250429123629.20839-1-agarciav@amd.com/ >   - > https://lore.kernel.org/xen-devel/20250429123629.20839-1-agarciav@amd.com/ > > *  [4.21?] Boot modules for Hyperlaunch (v9) >   -  Daniel P. Smith >   - > https://lore.kernel.org/xen-devel/20241115131204.32135-1-dpsmith@apertussolutions.com/ >   - > https://patchew.org/Xen/20241115131204.32135-1-dpsmith@apertussolutions.com/ > > *  [4.21?] Address Space Isolation FPU preparations (v2->v3) >   -  Alejandro Vallejo >   - > https://patchew.org/Xen/20250110132823.24348-1-alejandro.vallejo@cloud.com/ > > * [next-rel(s)] Hyperlaunch domain builder >   - Daniel P. Smith >   - > https://lore.kernel.org/xen-devel/20250515131744.3843-1-dpsmith@apertussolutions.com/ > > * [next-rel(s)] Confidential computing and AMD SEV support >   - Teddy Astie >   - https://patchew.org/Xen/cover.1747312394.git.teddy.astie@vates.tech/ >   - > https://lore.kernel.org/xen-devel/cover.1747312394.git.teddy.astie@vates.tech/ > > * [next-rel(s)] amd-cppc CPU Performance Scaling Driver (v5 -> v6) >   - Penny Zheng >   - > https://lore.kernel.org/xen-devel/20250711035106.2540522-1-Penny.Zheng@amd.com/ > > * [next-rel(s)] x86: Trenchboot Secure Launch DRTM (Xen) (v1 -> v3) >   - Sergii Dmytruk >   - https://patchew.org/Xen/cover.1745172094.git.sergii.dmytruk@3mdeb.com/ >   - > https://lore.kernel.org/xen-devel/cover.1748611041.git.sergii.dmytruk@3mdeb.com/ > > * [next-rel(s)] x86/EFI: prevent write-execute sections >   - Roger Pau Monne >   - > https://lore.kernel.org/xen-devel/20250401130840.72119-1-roger.pau@citrix.com/ > > * [next-rel(s)] x86: generate xen.efi image with no write-execute sections >   - Roger Pau Monne >   - > https://lore.kernel.org/xen-devel/20250318173547.59475-1-roger.pau@citrix.com/ > > *  [next-rel(s)] Expose consistent topology to guests (v7) >   -  Alejandro Vallejo >   - > https://patchew.org/Xen/20241021154600.11745-1-alejandro.vallejo@cloud.com/ > > *  [next-rel(s)] x86/alternatives: Adjust all insn-relative fields (v2) >   -  Andrew Cooper >   - > https://lore.kernel.org/xen-devel/20241002152725.1841575-1-andrew.cooper3@citrix.com/T/#mac2deaea7e02a343210d61887486433d946ad129 > > *  [next-rel(s)] x86emul: misc additions (v7) >   -  Jan Beulich >   - https://patchew.org/Xen/3a25cd59-e1cb-4bfc-b868-fb11599d22f5@suse.com/ > > *  [next-rel(s)] x86: support AVX10 (v3) >   -  Jan Beulich >   - > https://lore.kernel.org/xen-devel/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@suse.com/ >   - https://patchew.org/Xen/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@suse.com/ While it is correct that AVX10 is now to go first, AMX was lost as an item, and APX (which I see no reason in posting as long as AVX10 doesn't make any progress) was agreed to go after AVX10, before AMX. (KeyLocker was also lost, but that happens to be correct, as with Intel abandoning the feature we apparently have no plans anymore to make an attempt at supporting it.) FRED (being worked on by Andrew) is also entirely missing. Overall: There are very many items on this list, and it seems entirely clear to me that not all of them will make it. I think it would be quite helpful to strip down the set for 4.21 to some realistic subset. Maybe something to discuss on the community call later today? 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Smith" , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , xen-devel@lists.xenproject.org References: <20250805163204.3631483-1-ross.lagerwall@citrix.com> <20250805163204.3631483-2-ross.lagerwall@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250805163204.3631483-2-ross.lagerwall@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05.08.2025 18:32, Ross Lagerwall wrote: > If the config file is builtin, cfg.addr will be zero but Xen > unconditionally calls FreePages() on the address. > > Xen may also call FreePages() with a zero address if blexit() is called > after this point since cfg.need_to_free is not set to false. > > The UEFI specification does not say whether calling FreePages() with a > zero address is allowed so let's be cautious and use cfg.need_to_free > properly. Well, no, this paragraph makes no sense. Of course this is allowed, but not as no-op behavior (like free(NULL) would be), but to free memory starting at 0. > Signed-off-by: Ross Lagerwall This pretty clearly wants a Fixes: tag, or maybe it even needs to be two. I've checked the original code in 4.2, and things were consistent there, afaics. So breakage was introduced perhaps in one or two of the many re-works. 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Smith" , Grygorii Strashko , Alejandro Vallejo , "committers@xenproject.org" , Community Manager References: Content-Language: en-US From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= Autocrypt: addr=jgross@suse.com; keydata= xsBNBFOMcBYBCACgGjqjoGvbEouQZw/ToiBg9W98AlM2QHV+iNHsEs7kxWhKMjrioyspZKOB ycWxw3ie3j9uvg9EOB3aN4xiTv4qbnGiTr3oJhkB1gsb6ToJQZ8uxGq2kaV2KL9650I1SJve dYm8Of8Zd621lSmoKOwlNClALZNew72NjJLEzTalU1OdT7/i1TXkH09XSSI8mEQ/ouNcMvIJ NwQpd369y9bfIhWUiVXEK7MlRgUG6MvIj6Y3Am/BBLUVbDa4+gmzDC9ezlZkTZG2t14zWPvx XP3FAp2pkW0xqG7/377qptDmrk42GlSKN4z76ELnLxussxc7I2hx18NUcbP8+uty4bMxABEB AAHNH0p1ZXJnZW4gR3Jvc3MgPGpncm9zc0BzdXNlLmNvbT7CwHkEEwECACMFAlOMcK8CGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRCw3p3WKL8TL8eZB/9G0juS/kDY9LhEXseh mE9U+iA1VsLhgDqVbsOtZ/S14LRFHczNd/Lqkn7souCSoyWsBs3/wO+OjPvxf7m+Ef+sMtr0 G5lCWEWa9wa0IXx5HRPW/ScL+e4AVUbL7rurYMfwCzco+7TfjhMEOkC+va5gzi1KrErgNRHH kg3PhlnRY0Udyqx++UYkAsN4TQuEhNN32MvN0Np3WlBJOgKcuXpIElmMM5f1BBzJSKBkW0Jc Wy3h2Wy912vHKpPV/Xv7ZwVJ27v7KcuZcErtptDevAljxJtE7aJG6WiBzm+v9EswyWxwMCIO RoVBYuiocc51872tRGywc03xaQydB+9R7BHPzsBNBFOMcBYBCADLMfoA44MwGOB9YT1V4KCy vAfd7E0BTfaAurbG+Olacciz3yd09QOmejFZC6AnoykydyvTFLAWYcSCdISMr88COmmCbJzn sHAogjexXiif6ANUUlHpjxlHCCcELmZUzomNDnEOTxZFeWMTFF9Rf2k2F0Tl4E5kmsNGgtSa aMO0rNZoOEiD/7UfPP3dfh8JCQ1VtUUsQtT1sxos8Eb/HmriJhnaTZ7Hp3jtgTVkV0ybpgFg w6WMaRkrBh17mV0z2ajjmabB7SJxcouSkR0hcpNl4oM74d2/VqoW4BxxxOD1FcNCObCELfIS auZx+XT6s+CE7Qi/c44ibBMR7hyjdzWbABEBAAHCwF8EGAECAAkFAlOMcBYCGwwACgkQsN6d 1ii/Ey9D+Af/WFr3q+bg/8v5tCknCtn92d5lyYTBNt7xgWzDZX8G6/pngzKyWfedArllp0Pn fgIXtMNV+3t8Li1Tg843EXkP7+2+CQ98MB8XvvPLYAfW8nNDV85TyVgWlldNcgdv7nn1Sq8g HwB2BHdIAkYce3hEoDQXt/mKlgEGsLpzJcnLKimtPXQQy9TxUaLBe9PInPd+Ohix0XOlY+Uk QFEx50Ki3rSDl2Zt2tnkNYKUCvTJq7jvOlaPd6d/W0tZqpyy7KVay+K4aMobDsodB3dvEAs6 ScCnh03dDAFgIq5nsB11j3KPKdVoPlfucX2c7kGNH+LUMbzqV6beIENfNexkOfxHfw== In-Reply-To: Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="------------Bha8zBvQP4eh14IxMIwCC8YT" This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --------------Bha8zBvQP4eh14IxMIwCC8YT Content-Type: multipart/mixed; boundary="------------y4XDt7UpE0rgiID9Ta9FSqkU"; protected-headers="v1" From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= To: Oleksii Kurochko , Xen-devel Cc: Oleksii Moisieiev , Ayan Kumar Halder , Mykyta Poturai , Teddy Astie , Bertrand Marquis , Luca Fancellu , "Jason Andryuk," , Alejandro Vallejo , Sergii Dmytruk , "Penny Zheng," , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki=2C?= , Roger Pau Monne , Andrew Cooper , dmkhn@proton.me, Mykola Kvach , "Daniel P. Smith" , Grygorii Strashko , Alejandro Vallejo , "committers@xenproject.org" , Community Manager Message-ID: <8b18a14c-6436-4266-9a50-20a9b85c12ae@suse.com> Subject: Re: Xen 4.21 Development Update [June-July] References: In-Reply-To: --------------y4XDt7UpE0rgiID9Ta9FSqkU Content-Type: multipart/mixed; boundary="------------SppeSxdwE2m0ImLmFQPGKzTi" --------------SppeSxdwE2m0ImLmFQPGKzTi Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: base64 T24gMDUuMDguMjUgMjA6MTksIE9sZWtzaWkgS3Vyb2Noa28gd3JvdGU6DQo+IEhlbGxvIGV2 ZXJ5b25lLA0KPiANCj4gVGhpcyBlbWFpbCBvbmx5IHRyYWNrcyBiaWcgaXRlbXMgZm9yIHhl bi5naXQgdHJlZS4gUGxlYXNlIHJlcGx5IGZvciBpdGVtcyB5b3UNCj4gd291bGQgbGlrZSB0 byBzZWUgaW4gNC4yMSBzbyB0aGF0IHBlb3BsZSBoYXZlIGFuIGlkZWEgd2hhdCBpcyBnb2lu ZyBvbiBhbmQNCj4gcHJpb3JpdGlzZSBhY2NvcmRpbmdseS4NCj4gDQo+IFlvdSdyZSB3ZWxj b21lIHRvIHByb3ZpZGUgZGVzY3JpcHRpb24gYW5kIHVzZSBjYXNlcyBvZiB0aGUgZmVhdHVy ZSB5b3UncmUNCj4gd29ya2luZyBvbi4NCj4gDQo+ID0gVGltZWxpbmUgPQ0KPiANCj4gVGhl IGN1cnJlbnQgcmVsZWFzZSBzY2hlZHVsZSBjb3VsZCBiZSBmb3VuZCBoZXJlOg0KPiAgwqAg aHR0cHM6Ly93aWtpLnhlbnByb2plY3Qub3JnL3dpa2kvWGVuX1Byb2plY3RfWC5ZWV9SZWxl YXNlX05vdGVzDQo+IA0KPiBBbmQgYXMgYSByZW1pbmRlciBJIHdvdWxkIGxpa2UgdG8gcmVt aW5kIGF0IHRoZSBvZiB0aGlzIHdlZWsgd2Ugd2lsbCBoYXZlDQo+IExhc3QgcG9zdGluZyBk YXRlIChGcmkgQXVnIDA4LCAyMDI1KS4NCj4gDQo+ID0gVXBkYXRlcyA9DQo+IA0KPiBUaGUg Zm9sbG93aW5nIGl0ZW1zICggdGhlIGxpbmtzIGZvciB0aGVtIGNvdWxkIGJlIGZvdW5kIGlu dCB0aGUgbGlzdCBiZWxvdyApDQo+IHdlcmUgbW92ZWQgdG8gY29tcGxldGVkOg0KPiAgwqAg W3NpbmNlIEp1bjIgLSBBdWc1XToNCj4gIMKgwqAgQWRkZWQgc29tZSB0YWdzOiBbNC4yMV0s IFtuZXh0LXJlbChzKV0gdG8gdGhlIGxpc3QgIkZ1bGwgbGlzdCBvZiBpdGVtcyINCj4gIMKg wqAgYmVsb3cuDQo+ICDCoMKgICogeDg2Og0KPiAgwqDCoMKgIC0ga2V4ZWM6IGFkZCBrZXhl YyBzdXBwb3J0IHRvIE1pbmktT1MuDQoNCkFuZCB3aXRoIHRoYXQ6DQoNCi0gUFZIIHhlbnN0 b3JlLXN0dWJkb20gbGl2ZSB1cGRhdGUNCg0KPiAgwqDCoMKgIC0geDg2OiBtZW1jcHkoKSAv IG1lbXNldCgpIChub24tKUVSTVMgZmxhdm9ycyBwbHVzIGZhbGxvdXQNCj4gIMKgwqAgKiBB cm06DQo+ICDCoMKgwqAgLSBTTU1VIGhhbmRsaW5nIGZvciBQQ0llIFBhc3N0aHJvdWdoIG9u IEFSTS4NCj4gIMKgwqDCoCAtIEFkZCBzdXBwb3J0IGZvciBSLUNhciBHZW40IFBDSSBob3N0 IGNvbnRyb2xsZXIuDQo+ICDCoMKgwqAgLSBGaXJzdCBjaHVuayBmb3IgQXJtIFI4MiBhbmQg TVBVIHN1cHBvcnQuDQo+ICDCoMKgwqAgLSBFbmFibGUgUjUyIHN1cHBvcnQgZm9yIHRoZSBm aXJzdCBjaHVuayBvZiBNUFUgc3VwcG9ydA0KPiAgwqDCoMKgIC0gQVJNIHNwbGl0IGhhcmR3 YXJlIGFuZCBjb250cm9sIGRvbWFpbnMuDQo+ICDCoMKgICogUklTQy1WOg0KPiAgwqDCoMKg IC0gSW50cm9kdWNlIGJhc2ljIFVBUlQgc3VwcG9ydCBhbmQgaW50ZXJydXB0cyBmb3IgaHlw ZXJ2aXNvciBtb2RlLg0KDQoqIEh5cGVydmlzb3I6DQogICAtIHRvb2xzOiBzdXBwb3J0IGZv ciBwZXItZG9tYWluIFhlbnN0b3JlIGZlYXR1cmVzDQoNCg0KSnVlcmdlbg0K --------------SppeSxdwE2m0ImLmFQPGKzTi Content-Type: application/pgp-keys; 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name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wsB5BAABCAAjFiEEhRJncuj2BJSl0Jf3sN6d1ii/Ey8FAmiS80QFAwAAAAAACgkQsN6d1ii/Ey+4 iggAm7vuT0ExEDfNVmXxNT6ufz9JkVKvlevFUUI8sk8LaPJQewZ+ggErkgVZSbqje5tsIo8gR9k5 q0xLHNVgUrNh5CSULrX1XataS6m4Blw4ayCTGaQsMVy+EK9RrqIctpnczaCE2zdny3WEJkGfsoDS Glh5VZ2WngLs1Yrl3jzk+Ec9cNwNPY9Xdvr3EV0u0RsYrtNPAYD0E8YIWv0xwpalhxQqdUYAwAvd lzWVe/Ql+nJBLwubFKsGiGdaO5yuy6O5F5I8SKrl6QYcW87opRyWfKeMkrhHu4pICnA2CxY+fBBn TZwSp7pGGFBqZ7GLdXYDjnMRVvZ3yQAKJQF/mzHnug== =b3X8 -----END PGP SIGNATURE----- --------------Bha8zBvQP4eh14IxMIwCC8YT-- From xen-devel-bounces@lists.xenproject.org Wed Aug 06 06:26:49 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 06:26:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071212.1434707 (Exim 4.92) (envelope-from ) id 1ujXbo-00052x-9o; Wed, 06 Aug 2025 06:26:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071212.1434707; Wed, 06 Aug 2025 06:26:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujXbo-00052q-70; Wed, 06 Aug 2025 06:26:44 +0000 Received: by outflank-mailman (input) for mailman id 1071212; Wed, 06 Aug 2025 06:26:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujXbm-00052k-Kb for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 06:26:42 +0000 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 4e0b7ae6-728e-11f0-a322-13f23c93f187; Wed, 06 Aug 2025 08:26:39 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.163.48]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4bxgDK4p7yz14MKj; Wed, 6 Aug 2025 14:21:37 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id D56AE1800B1; Wed, 6 Aug 2025 14:26:33 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 6 Aug 2025 14:26:32 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4e0b7ae6-728e-11f0-a322-13f23c93f187 Message-ID: <5d81d30f-8dd4-d74c-7c8a-0714dafc09fe@huawei.com> Date: Wed, 6 Aug 2025 14:26:31 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH -next v7 5/7] arm64: entry: Refactor preempt_schedule_irq() check code Content-Language: en-US To: Ada Couprie Diaz CC: , , , , , , , , , , , , , , , , , , References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-6-ruanjinjie@huawei.com> <44fd646c-4e31-4ca6-9e22-f715ad19e0d7@arm.com> From: Jinjie Ruan In-Reply-To: <44fd646c-4e31-4ca6-9e22-f715ad19e0d7@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.109.254] X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500011.china.huawei.com (7.185.36.131) On 2025/8/5 23:06, Ada Couprie Diaz wrote: > Hi Jinjie, > > On 29/07/2025 02:54, Jinjie Ruan wrote: >> ARM64 requires an additional check whether to reschedule on return >> from interrupt. So add arch_irqentry_exit_need_resched() as the default >> NOP implementation and hook it up into the need_resched() condition in >> raw_irqentry_exit_cond_resched(). This allows ARM64 to implement >> the architecture specific version for switching over to >> the generic entry code. > I was a bit confused by this, as I didn't see the link with the generic > entry > given you implement `raw_irqentry_exit_cond_resched()` in arch/arm64 > as well in this patch : I expected the arm64 implementation to be added. > I share more thoughts below. > > What do you think about something along those lines ? > >     Compared to the generic entry code, arm64 does additional checks >     when deciding to reschedule on return from an interrupt. >     Introduce arch_irqentry_exit_need_resched() in the need_resched() > condition >     of the generic raw_irqentry_exit_cond_resched(), with a NOP default. >     This will allow arm64 to implement its architecture specific checks > when >     switching over to the generic entry code. This revision makes it easier for people to understand. > >> [...] >> diff --git a/kernel/entry/common.c b/kernel/entry/common.c >> index b82032777310..4aa9656fa1b4 100644 >> --- a/kernel/entry/common.c >> +++ b/kernel/entry/common.c >> @@ -142,6 +142,20 @@ noinstr irqentry_state_t irqentry_enter(struct >> pt_regs *regs) >>       return ret; >>   } >>   +/** >> + * arch_irqentry_exit_need_resched - Architecture specific need >> resched function >> + * >> + * Invoked from raw_irqentry_exit_cond_resched() to check if need >> resched. > Very nit : "to check if resched is needed." ? This is good. >> + * Defaults return true. >> + * >> + * The main purpose is to permit arch to skip preempt a task from an >> IRQ. > If feel that "to avoid preemption of a task" instead of "to skip preempt > a task" > would make this much clearer, what do you think ? Yes, this is more clearer. >> + */ >> +static inline bool arch_irqentry_exit_need_resched(void); >> + >> +#ifndef arch_irqentry_exit_need_resched >> +static inline bool arch_irqentry_exit_need_resched(void) { return >> true; } >> +#endif >> + > > I've had some trouble reviewing this patch : on the one hand because > I didn't notice `arch_irqentry_exit_need_resched()` was added in > the common entry code, which is on me ! > On the other hand, I felt that the patch itself was a bit disconnected : > we add `arch_irqentry_exit_need_resched()` in the common entry code, > with a default NOP, but in the same function we add to arm64, > while mentioning that this is for arm64's additional checks, > which we only implement in patch 7. > > Would it make sense to move the `arch_irqentry_exit_need_resched()` > part of the patch to patch 7, so that the introduction and > arch-specific implementation appear together ? > To me it seems easier to wrap my head around, as it would look like > "Move arm64 to generic entry, but it does additional checks : add a new > arch-specific function controlling re-scheduling, defaulting to true, > and implement it for arm64". I feel it could help making patch 7's > commit message clearer as well. > > From what I gathered on the archive `arch_irqentry_exit_need_resched()` > being added here was suggested previously, so others might not have the > same opinion. > > Maybe improving the commit message and comment for this would be enough > as well, as per my suggestions above. > > > Otherwise the changes make sense and I don't see any functional issues ! > > Thanks, > Ada > > From xen-devel-bounces@lists.xenproject.org Wed Aug 06 06:33:00 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 06:33:00 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071220.1434718 (Exim 4.92) (envelope-from ) id 1ujXho-0006eb-2k; Wed, 06 Aug 2025 06:32:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071220.1434718; Wed, 06 Aug 2025 06:32:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujXhn-0006eU-Vk; Wed, 06 Aug 2025 06:32:55 +0000 Received: by outflank-mailman (input) for mailman id 1071220; Wed, 06 Aug 2025 06:32:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujXhm-0006eO-Pn for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 06:32:54 +0000 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [2a00:1450:4864:20::636]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2e0e87f1-728f-11f0-b898-0df219b8e170; Wed, 06 Aug 2025 08:32:52 +0200 (CEST) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-af95b919093so527894666b.2 for ; Tue, 05 Aug 2025 23:32:52 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Smith" , =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= , xen-devel@lists.xenproject.org References: <20250805163204.3631483-1-ross.lagerwall@citrix.com> <20250805163204.3631483-3-ross.lagerwall@citrix.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <20250805163204.3631483-3-ross.lagerwall@citrix.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 05.08.2025 18:32, Ross Lagerwall wrote: > Xen's use of StdErr is inconsistent. Some boot errors are reported using > PrintErr() which uses StdErr and some are reported using blexit() which > uses StdOut. ... with PrintErrMesg() having StdOut = StdErr; apparently to address at least some of the inconsistencies. Perhaps blexit(), when not passed NULL, should similarly override StdOut. > On my test system using OVMF, StdErr is not displayed on the emulated > screen. Looking at other EFI applications, StdErr is just used for debug > messages if at all. That's hardly how StdErr was meant to be used. And at the risk of being flamed for saying so, looking at other EFI applications (without saying of what prominence or origin they are) can hardly serve as a justification. If OVMF doesn't set up StdErr correctly (despite being configured / set up correctly), and if that can't be fixed there, imo what you want as a workaround is a command line option to override StdErr by StdOut even when SystemTable->StdErr is non-NULL. Along the lines of the comment further up, inconsistencies in the use of StdErr vs StdOut may want addressing (separately). But of course, not being EFI maintainer anymore, all of what I said above may be deemed entirely meaningless by the new maintainers. Jan From xen-devel-bounces@lists.xenproject.org Wed Aug 06 06:39:57 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 06:39:57 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071236.1434728 (Exim 4.92) (envelope-from ) id 1ujXoW-0007QI-OY; Wed, 06 Aug 2025 06:39:52 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071236.1434728; Wed, 06 Aug 2025 06:39:52 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujXoW-0007QB-Kt; Wed, 06 Aug 2025 06:39:52 +0000 Received: by outflank-mailman (input) for mailman id 1071236; Wed, 06 Aug 2025 06:39:51 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujXoV-0007Q5-TT for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 06:39:51 +0000 Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 224797ed-7290-11f0-b898-0df219b8e170; Wed, 06 Aug 2025 08:39:48 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.88.234]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4bxgfJ29swz27g4j; Wed, 6 Aug 2025 14:40:40 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 8B11A140119; Wed, 6 Aug 2025 14:39:37 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 6 Aug 2025 14:39:36 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 224797ed-7290-11f0-b898-0df219b8e170 Message-ID: Date: Wed, 6 Aug 2025 14:39:35 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH -next v7 5/7] arm64: entry: Refactor preempt_schedule_irq() check code Content-Language: en-US To: Ada Couprie Diaz CC: , , , , , , , , , , , , , , , , , , References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-6-ruanjinjie@huawei.com> <44fd646c-4e31-4ca6-9e22-f715ad19e0d7@arm.com> From: Jinjie Ruan In-Reply-To: <44fd646c-4e31-4ca6-9e22-f715ad19e0d7@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.109.254] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) On 2025/8/5 23:06, Ada Couprie Diaz wrote: > Hi Jinjie, > > On 29/07/2025 02:54, Jinjie Ruan wrote: >> ARM64 requires an additional check whether to reschedule on return >> from interrupt. So add arch_irqentry_exit_need_resched() as the default >> NOP implementation and hook it up into the need_resched() condition in >> raw_irqentry_exit_cond_resched(). This allows ARM64 to implement >> the architecture specific version for switching over to >> the generic entry code. > I was a bit confused by this, as I didn't see the link with the generic > entry > given you implement `raw_irqentry_exit_cond_resched()` in arch/arm64 > as well in this patch : I expected the arm64 implementation to be added. > I share more thoughts below. > > What do you think about something along those lines ? > >     Compared to the generic entry code, arm64 does additional checks >     when deciding to reschedule on return from an interrupt. >     Introduce arch_irqentry_exit_need_resched() in the need_resched() > condition >     of the generic raw_irqentry_exit_cond_resched(), with a NOP default. >     This will allow arm64 to implement its architecture specific checks > when >     switching over to the generic entry code. > >> [...] >> diff --git a/kernel/entry/common.c b/kernel/entry/common.c >> index b82032777310..4aa9656fa1b4 100644 >> --- a/kernel/entry/common.c >> +++ b/kernel/entry/common.c >> @@ -142,6 +142,20 @@ noinstr irqentry_state_t irqentry_enter(struct >> pt_regs *regs) >>       return ret; >>   } >>   +/** >> + * arch_irqentry_exit_need_resched - Architecture specific need >> resched function >> + * >> + * Invoked from raw_irqentry_exit_cond_resched() to check if need >> resched. > Very nit : "to check if resched is needed." ? >> + * Defaults return true. >> + * >> + * The main purpose is to permit arch to skip preempt a task from an >> IRQ. > If feel that "to avoid preemption of a task" instead of "to skip preempt > a task" > would make this much clearer, what do you think ? >> + */ >> +static inline bool arch_irqentry_exit_need_resched(void); >> + >> +#ifndef arch_irqentry_exit_need_resched >> +static inline bool arch_irqentry_exit_need_resched(void) { return >> true; } >> +#endif >> + > > I've had some trouble reviewing this patch : on the one hand because > I didn't notice `arch_irqentry_exit_need_resched()` was added in > the common entry code, which is on me ! > On the other hand, I felt that the patch itself was a bit disconnected : > we add `arch_irqentry_exit_need_resched()` in the common entry code, > with a default NOP, but in the same function we add to arm64, > while mentioning that this is for arm64's additional checks, > which we only implement in patch 7. Yes, it does. > > Would it make sense to move the `arch_irqentry_exit_need_resched()` > part of the patch to patch 7, so that the introduction and > arch-specific implementation appear together ? > To me it seems easier to wrap my head around, as it would look like > "Move arm64 to generic entry, but it does additional checks : add a new > arch-specific function controlling re-scheduling, defaulting to true, > and implement it for arm64". I feel it could help making patch 7's > commit message clearer as well. > > From what I gathered on the archive `arch_irqentry_exit_need_resched()` > being added here was suggested previously, so others might not have the > same opinion. Yes, introduce `arch_irqentry_exit_need_resched()` here may help understand the patch's refactoring purpose. > > Maybe improving the commit message and comment for this would be enough > as well, as per my suggestions above. Thank you! I'll improve the commit message and comment. > > > Otherwise the changes make sense and I don't see any functional issues ! > > Thanks, > Ada > > From xen-devel-bounces@lists.xenproject.org Wed Aug 06 06:53:39 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 06:53:39 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071245.1434738 (Exim 4.92) (envelope-from ) id 1ujY1l-0001vg-Qn; Wed, 06 Aug 2025 06:53:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071245.1434738; Wed, 06 Aug 2025 06:53:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujY1l-0001vZ-Nq; Wed, 06 Aug 2025 06:53:33 +0000 Received: by outflank-mailman (input) for mailman id 1071245; Wed, 06 Aug 2025 06:53:32 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujY1k-0001vT-94 for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 06:53:32 +0000 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [2a00:1450:4864:20::52a]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 0f9cf1f6-7292-11f0-b898-0df219b8e170; Wed, 06 Aug 2025 08:53:30 +0200 (CEST) Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-61571192c3aso6765803a12.2 for ; Tue, 05 Aug 2025 23:53:30 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 05 Aug 2025 23:53:29 -0700 (PDT) Message-ID: <40f3719b-e6b2-4ea5-9c9c-89b17b973ef3@suse.com> Date: Wed, 6 Aug 2025 08:53:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 2/4] vpci/rebar: Free Rebar resources when init_rebar() fails To: "Chen, Jiqian" Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , "xen-devel@lists.xenproject.org" , "Huang, Ray" References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> <20250805034906.1014212-3-Jiqian.Chen@amd.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 06.08.2025 05:39, Chen, Jiqian wrote: > On 2025/8/5 16:48, Jan Beulich wrote: >> On 05.08.2025 05:49, Jiqian Chen wrote: >>> --- a/xen/drivers/vpci/rebar.c >>> +++ b/xen/drivers/vpci/rebar.c >>> @@ -49,6 +49,32 @@ static void cf_check rebar_ctrl_write(const struct pci_dev *pdev, >>> bar->guest_addr = bar->addr; >>> } >>> >>> +static int cf_check cleanup_rebar(const struct pci_dev *pdev) >>> +{ >>> + int rc; >>> + uint32_t ctrl; >>> + unsigned int nbars; >>> + unsigned int rebar_offset = pci_find_ext_capability(pdev->sbdf, >>> + PCI_EXT_CAP_ID_REBAR); >>> + >>> + if ( !rebar_offset || !is_hardware_domain(pdev->domain) ) >>> + { >>> + ASSERT_UNREACHABLE(); >>> + return 0; >>> + } >>> + >>> + ctrl = pci_conf_read32(pdev->sbdf, rebar_offset + PCI_REBAR_CTRL(0)); >>> + nbars = MASK_EXTR(ctrl, PCI_REBAR_CTRL_NBAR_MASK); >>> + >>> + rc = vpci_remove_registers(pdev->vpci, rebar_offset + PCI_REBAR_CAP(0), >>> + PCI_REBAR_CTRL(nbars - 1)); >>> + if ( rc ) >>> + printk(XENLOG_ERR "%pd %pp: fail to remove Rebar handlers rc=%d\n", >>> + pdev->domain, &pdev->sbdf, rc); >> >> MSI and MSI-X (now) have ASSERT_UNREACHABLE() on their respective paths. Is >> there a reason this shouldn't be done here as well? > Will add. > >> >> MSI and MSI-X further have another add-register below here, to ensure the >> control register cannot be written. Again - is there a reason the same >> shouldn't be done here? (If so, I think this may want putting in a comment.) > Since extended capabilities are only exposed to dom0, and dom0 has no limitations to access devices. > It since there is not much point in adding such a handler for rebar. While the effect is different from MSI / MSI-X, isn't it still a problem if Dom0 changed BAR sizes entirely behind Xen's back? Which could be prevented by similarly discarding writes to the control register, as is done for the other two? Jan From xen-devel-bounces@lists.xenproject.org Wed Aug 06 06:56:59 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 06:56:59 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071257.1434748 (Exim 4.92) (envelope-from ) id 1ujY54-0002UH-8w; Wed, 06 Aug 2025 06:56:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071257.1434748; Wed, 06 Aug 2025 06:56:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujY54-0002UA-50; Wed, 06 Aug 2025 06:56:58 +0000 Received: by outflank-mailman (input) for mailman id 1071257; Wed, 06 Aug 2025 06:56:56 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujY52-0002U4-IA for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 06:56:56 +0000 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [2a00:1450:4864:20::629]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 8a0ae281-7292-11f0-a322-13f23c93f187; Wed, 06 Aug 2025 08:56:55 +0200 (CEST) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-af910372ab3so106603466b.1 for ; Tue, 05 Aug 2025 23:56:55 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Tue, 05 Aug 2025 23:56:55 -0700 (PDT) Message-ID: <4c02de43-e51e-4f34-9144-a37819889daf@suse.com> Date: Wed, 6 Aug 2025 08:56:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 4/4] vpci/msix: Free MSIX resources when init_msix() fails To: "Chen, Jiqian" Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , "xen-devel@lists.xenproject.org" , "Huang, Ray" References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> <20250805034906.1014212-5-Jiqian.Chen@amd.com> <775a45bd-61df-4cab-948e-bdc79dfd89ef@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 06.08.2025 05:35, Chen, Jiqian wrote: > On 2025/8/5 16:43, Jan Beulich wrote: >> On 05.08.2025 05:49, Jiqian Chen wrote: >>> --- a/xen/drivers/vpci/msix.c >>> +++ b/xen/drivers/vpci/msix.c >>> @@ -655,6 +655,48 @@ int vpci_make_msix_hole(const struct pci_dev *pdev) >>> return 0; >>> } >>> >>> +static int cf_check cleanup_msix(const struct pci_dev *pdev) >>> +{ >>> + int rc; >>> + struct vpci *vpci = pdev->vpci; >>> + const unsigned int msix_pos = pdev->msix_pos; >>> + >>> + if ( !msix_pos ) >>> + return 0; >>> + >>> + rc = vpci_remove_registers(vpci, msix_control_reg(msix_pos), 2); >>> + if ( rc ) >>> + { >>> + printk(XENLOG_ERR "%pd %pp: fail to remove MSIX handlers rc=%d\n", >>> + pdev->domain, &pdev->sbdf, rc); >>> + ASSERT_UNREACHABLE(); >>> + return rc; >>> + } >>> + >>> + if ( vpci->msix ) >>> + { >>> + list_del(&vpci->msix->next); >>> + for ( unsigned int i = 0; i < ARRAY_SIZE(vpci->msix->table); i++ ) >>> + if ( vpci->msix->table[i] ) >>> + iounmap(vpci->msix->table[i]); >>> + >>> + XFREE(vpci->msix); >>> + } >>> + >>> + /* >>> + * The driver may not traverse the capability list and think device >>> + * supports MSIX by default. So here let the control register of MSIX >>> + * be Read-Only is to ensure MSIX disabled. >>> + */ >>> + rc = vpci_add_register(vpci, vpci_hw_read16, NULL, >>> + msix_control_reg(msix_pos), 2, NULL); >>> + if ( rc ) >>> + printk(XENLOG_ERR "%pd %pp: fail to add MSIX ctrl handler rc=%d\n", >>> + pdev->domain, &pdev->sbdf, rc); >> >> Here as well as for MSI: Wouldn't this better be limited to the init-failure >> case? No point in adding a register hook (and possibly emitting a misleading >> log message) when we're tearing down anyway. IOW I think the ->cleanup() >> hook needs a boolean parameter, unless the distinction of the two cases can >> be (reliably) inferred from some other property. > To make these changes, can I add a new patch as the last patch of this series? > And the new patch will do: > 1. add a boolean parameter for cleanup hook to separate whose calls cleanup(during initialization or during deassign device). > 2. call all cleanup hooks in vpci_deassign_device(). > 3. remove the MSI/MSIX specific free actions in vpci_deassign_device(). The outline looks okay, but imo it shouldn't be last in the series. Instead I think it wants to come ahead of the last three patches; whether it's patch 1 or patch 2 doesn't really matter. Then (3) would be taken care of incrementally, as ->cleanup hooks are added. Jan From xen-devel-bounces@lists.xenproject.org Wed Aug 06 06:59:18 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 06:59:18 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071267.1434757 (Exim 4.92) (envelope-from ) id 1ujY7F-00034X-Nx; Wed, 06 Aug 2025 06:59:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071267.1434757; Wed, 06 Aug 2025 06:59:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujY7F-00034Q-LL; Wed, 06 Aug 2025 06:59:13 +0000 Received: by outflank-mailman (input) for mailman id 1071267; Wed, 06 Aug 2025 06:59:13 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujY7F-00034K-AV for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 06:59:13 +0000 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d7c34c79-7292-11f0-a322-13f23c93f187; Wed, 06 Aug 2025 08:59:08 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4bxgxp47LNz14MD9; Wed, 6 Aug 2025 14:54:06 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id C2CAE140155; Wed, 6 Aug 2025 14:59:02 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 6 Aug 2025 14:59:01 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d7c34c79-7292-11f0-a322-13f23c93f187 Message-ID: <8972d8b9-ced3-f207-9c00-91b544d8ecc8@huawei.com> Date: Wed, 6 Aug 2025 14:59:00 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH -next v7 7/7] arm64: entry: Switch to generic IRQ entry Content-Language: en-US To: Ada Couprie Diaz CC: , , , , , , , , , , , , , , , , , , References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <20250729015456.3411143-8-ruanjinjie@huawei.com> From: Jinjie Ruan In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.67.109.254] X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To dggpemf500011.china.huawei.com (7.185.36.131) On 2025/8/5 23:07, Ada Couprie Diaz wrote: > Hi Jinjie, > > The code changes look good to me, just a small missing clean up I believe. > > On 29/07/2025 02:54, Jinjie Ruan wrote: > >> Currently, x86, Riscv, Loongarch use the generic entry. Convert arm64 >> to use the generic entry infrastructure from kernel/entry/*. >> The generic entry makes maintainers' work easier and codes >> more elegant. >> >> Switch arm64 to generic IRQ entry first, which removed duplicate 100+ >> LOC. The next patch serise will switch to generic entry completely later. >> Switch to generic entry in two steps according to Mark's suggestion >> will make it easier to review. > > I think the commit message could be clearer, especially since now this > series > only moves arm64 to generic IRQ entry and not the complete generic entry. > > What do you think of something like below ? It repeats a bit less and I > think > it helps understanding what is going on in this specific commit, as you > already > have details on the larger plans in the cover. > >     Currently, x86, Riscv and Loongarch use the generic entry code, > which makes >     maintainer's work easier and code more elegant. >     Start converting arm64 to use the generic entry infrastructure >     from kernel/entry/* by switching it to generic IRQ entry, which > removes 100+ >     lines of duplicate code. >     arm64 will completely switch to generic entry in a later series. > Yes, this is more concise and accurate, and make the motivation more clearer. >> The changes are below: >>   - Remove *enter_from/exit_to_kernel_mode(), and wrap with generic >>     irqentry_enter/exit(). Also remove *enter_from/exit_to_user_mode(), >>     and wrap with generic enter_from/exit_to_user_mode() because they >>     are exactly the same so far. > Nit : "so far" can be removed >>   - Remove arm64_enter/exit_nmi() and use generic >> irqentry_nmi_enter/exit() >>     because they're exactly the same, so the temporary arm64 version >>     irqentry_state can also be removed. >> >>   - Remove PREEMPT_DYNAMIC code, as generic entry do the same thing >>     if arm64 implement arch_irqentry_exit_need_resched(). > This feels unrelated, given that the part that needs > `arch_irqentry_exit_need_resched()` > is called whether or not PREEMPT_DYNAMIC is enabled ? Yes, the language here needs to be reorganized in conjunction with your comments from the fifth patch. > > Given my comments on patch 5, I feel that the commit message should mention > explicitly the implementation of `arch_irqentry_exit_need_resched()` and > why, > even though it was already mentioned in patch 5. > (This is what I was referencing in patch 5 : as I feel it's useful to > mention again > the reasons when implementing it, it doesn't feel too out of place to > introduce > the generic part at the same time. But again, I might be wrong here.) > > Then you can have another point explaining that > `raw_irqentry_exit_cond_resched()` > and the PREEMPT_DYNAMIC code is removed because they are identical to the > generic entry code, similarly to your other points. >> Tested ok with following test cases on Qemu virt platform: >>   - Perf tests. >>   - Different `dynamic preempt` mode switch. >>   - Pseudo NMI tests. >>   - Stress-ng CPU stress test. >>   - MTE test case in >> Documentation/arch/arm64/memory-tagging-extension.rst >>     and all test cases in tools/testing/selftests/arm64/mte/*. > Nit : I'm not sure if the commit message is the best place for this, > given you > already gave some details in the cover ? > But I don't have much experience here, so I'll leave it up to you and > others ! Yes, this can be removed as the cover letter already has it. >> Suggested-by: Mark Rutland >> Signed-off-by: Jinjie Ruan >> --- >> [...] >> diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c >> index db3f972f8cd9..1110eeb21f57 100644 >> --- a/arch/arm64/kernel/signal.c >> +++ b/arch/arm64/kernel/signal.c >> @@ -9,6 +9,7 @@ >>   #include >>   #include >>   #include >> +#include >>   #include >>   #include >>   #include >> @@ -1576,7 +1577,7 @@ static void handle_signal(struct ksignal *ksig, >> struct pt_regs *regs) >>    * the kernel can handle, and then we build all the user-level >> signal handling >>    * stack-frames in one go after that. >>    */ >> -void do_signal(struct pt_regs *regs) >> +void arch_do_signal_or_restart(struct pt_regs *regs) > Given that `do_signal(struct pt_regs *regs)` is defined in > `arch/arm64/include/asm/exception.h`, > and that there remains no users of `do_signal()`, I think it should be > removed there. Good catch! I'll remove it. > > Thanks, > Ada > From xen-devel-bounces@lists.xenproject.org Wed Aug 06 07:11:35 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 07:11:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071273.1434768 (Exim 4.92) (envelope-from ) id 1ujYJ0-0006CR-PM; Wed, 06 Aug 2025 07:11:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071273.1434768; Wed, 06 Aug 2025 07:11:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujYJ0-0006CK-ME; Wed, 06 Aug 2025 07:11:22 +0000 Received: by outflank-mailman (input) for mailman id 1071273; Wed, 06 Aug 2025 07:11:21 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujYIz-0006CE-Pm for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 07:11:21 +0000 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [2a00:1450:4864:20::330]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 8d77d6f8-7294-11f0-a322-13f23c93f187; Wed, 06 Aug 2025 09:11:20 +0200 (CEST) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-458b49c98a7so30184995e9.1 for ; Wed, 06 Aug 2025 00:11:20 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. 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Split > > the BSP action from the AP one, indicating the odd CPU in the AP log > > message, thus avoiding the impression that global state would have > > changed. > > > > While there also > > - move g_disabled into .data.ro_after_init; only the BSP will ever write > > to it, > > - make the function's parameter unsigned; no negative values may be > > passed in. Also reflect this in svm_asid_init(). > > > > Signed-off-by: Jan Beulich > > Reviewed-by: Jason Andryuk Acked-by: Roger Pau Monné Thanks. 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Smith" , Grygorii Strashko , Alejandro Vallejo , "committers@xenproject.org" , Community Manager , Xen-devel References: <242a93cf-20f7-4fcd-8eef-6945af5d864c@suse.com> Content-Language: en-US From: Oleksii Kurochko In-Reply-To: <242a93cf-20f7-4fcd-8eef-6945af5d864c@suse.com> This is a multi-part message in MIME format. --------------kZF3O5gOHXMsO4gSSGZUUrHA Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 8/6/25 8:05 AM, Jan Beulich wrote: > On 05.08.2025 20:19, Oleksii Kurochko wrote: >> * Full list of items : * >> >> = Projects = >> >> == Hypervisor == >> >> * [4.21] xen/console: cleanup console input switch logic (v5) >>   - Denis Mukhin >>   - >> https://lore.kernel.org/xen-devel/20250530231841.73386-1-dmukhin@ford.com/ >> >> * [4.21] xen: introduce CONFIG_SYSCTL (v4 -> v8) >>   -  Penny Zheng >>   - >> https://lore.kernel.org/xen-devel/20250711043158.2566880-1-Penny.Zheng@amd.com/ >> >> * [4.21] Several CI cleanups and improvements, plus yet another new runner >>   - Marek Marczykowski-Górecki >>   - >> https://lore.kernel.org/xen-devel/cover.7da1777882774486a13e6f39ff4a2096f6b7901e.1744028549.git-series.marmarek@invisiblethingslab.com/ >>   - >> https://patchew.org/Xen/cover.7da1777882774486a13e6f39ff4a2096f6b7901e.1744028549.git-series.marmarek@invisiblethingslab.com/ >> >> * [4.21] automation: Refresh the remaining Debian containers (v2) >>   -  Javi Merino >>   - >> https://lore.kernel.org/xen-devel/cover.1730743077.git.javi.merino@cloud.com/T/#m5d9acb7cf5db3c2be3d6527de14b69b07812314e >> >> * [4.21] MSI-X support with qemu in stubdomain, and other related >> changes (v8) >>   -  Marek Marczykowski-Górecki >>   - >> https://lore.kernel.org/xen-devel/cover.33fb4385b7dd6c53bda4acf0a9e91748b3d7b1f7.1715313192.git-series.marmarek@invisiblethingslab.com/ >>   -  Only automation patch left to be reviewed/merged. >> >> * [next-rel(s)] Physical address hypercall ABI ("HVMv2") >>   - Teddy Astie >>   - >> https://lore.kernel.org/xen-devel/cover.1744981654.git.teddy.astie@vates.tech/ >> >> * [next-rel(s)] xen: Untangle mm.h >>   -  Andrew Cooper >>   - >> https://lore.kernel.org/xen-devel/20250312174513.4075066-1-andrew.cooper3@citrix.com/ >>   - >> https://patchew.org/Xen/20250312174513.4075066-1-andrew.cooper3@citrix.com/ >> >> * [next-rel(s)] Add support for exact-node memory claims >>   -  Alejandro Vallejo >>   - >> https://lore.kernel.org/xen-devel/20250314172502.53498-1-alejandro.vallejo@cloud.com/ >>   - >> https://patchew.org/Xen/20250314172502.53498-1-alejandro.vallejo@cloud.com/ >> >> * [next-rel(s)] Remove the directmap (v5) >>   -  Alejandro Vallejo >>   - >> https://lore.kernel.org/xen-devel/20250108151822.16030-1-alejandro.vallejo@cloud.com/ >>   - >> https://patchew.org/Xen/20250108151822.16030-1-alejandro.vallejo@cloud.com/ >> >> * [next-rel(s)] GRUB: Supporting Secure Boot of xen.gz (v1) >>   -  Ross Lagerwall >>   - >> https://patchew.org/Xen/20240313150748.791236-1-ross.lagerwall@citrix.com/ >> >> * [next-rel(s)] Introduce xenbindgen to autogen hypercall structs (v1) >>   -  Alejandro Vallejo >>   - >> https://patchew.org/Xen/20241115115200.2824-1-alejandro.vallejo@cloud.com/ >> >> * [next-rel(s)] Introduce NS8250 UART emulator (v2) >>   -  Denis Mukhin >>   - >> https://patchew.org/Xen/20241205-vuart-ns8250-v1-0-e9aa923127eb@ford.com/ >> >> * [next-rel(s)] xen: framework for UART emulators >>   - Denis Mukhin >>   - >> https://lore.kernel.org/xen-devel/20250624035443.344099-1-dmukhin@ford.com/ >> >> === x86 === >> * [4.21] x86/asm: cleanups after toolchain baseline upgrade (v1 -> v2) >>   - Denis Mukhin >>   - >> https://lore.kernel.org/xen-devel/20250403182250.3329498-1-dmukhin@ford.com/ >>   -https://patchew.org/Xen/20250403182250.3329498-1-dmukhin@ford.com/ >> >> * [4.21?] x86/efi: Fix booting when NX is disabled (v1 -> v2) >>   - Andrew Cooper >>   - >> https://patchew.org/Xen/20240722101838.3946983-1-andrew.cooper3@citrix.com/ >>   - >> https://lore.kernel.org/xen-devel/20240722101838.3946983-1-andrew.cooper3@citrix.com/ >> >> * [4.21?] Hyperlaunch device tree for dom0 (v6) >>   - Alejandro Vallejo >>   -https://patchew.org/Xen/20250429123629.20839-1-agarciav@amd.com/ >>   - >> https://lore.kernel.org/xen-devel/20250429123629.20839-1-agarciav@amd.com/ >> >> *  [4.21?] Boot modules for Hyperlaunch (v9) >>   -  Daniel P. Smith >>   - >> https://lore.kernel.org/xen-devel/20241115131204.32135-1-dpsmith@apertussolutions.com/ >>   - >> https://patchew.org/Xen/20241115131204.32135-1-dpsmith@apertussolutions.com/ >> >> *  [4.21?] Address Space Isolation FPU preparations (v2->v3) >>   -  Alejandro Vallejo >>   - >> https://patchew.org/Xen/20250110132823.24348-1-alejandro.vallejo@cloud.com/ >> >> * [next-rel(s)] Hyperlaunch domain builder >>   - Daniel P. Smith >>   - >> https://lore.kernel.org/xen-devel/20250515131744.3843-1-dpsmith@apertussolutions.com/ >> >> * [next-rel(s)] Confidential computing and AMD SEV support >>   - Teddy Astie >>   -https://patchew.org/Xen/cover.1747312394.git.teddy.astie@vates.tech/ >>   - >> https://lore.kernel.org/xen-devel/cover.1747312394.git.teddy.astie@vates.tech/ >> >> * [next-rel(s)] amd-cppc CPU Performance Scaling Driver (v5 -> v6) >>   - Penny Zheng >>   - >> https://lore.kernel.org/xen-devel/20250711035106.2540522-1-Penny.Zheng@amd.com/ >> >> * [next-rel(s)] x86: Trenchboot Secure Launch DRTM (Xen) (v1 -> v3) >>   - Sergii Dmytruk >>   -https://patchew.org/Xen/cover.1745172094.git.sergii.dmytruk@3mdeb.com/ >>   - >> https://lore.kernel.org/xen-devel/cover.1748611041.git.sergii.dmytruk@3mdeb.com/ >> >> * [next-rel(s)] x86/EFI: prevent write-execute sections >>   - Roger Pau Monne >>   - >> https://lore.kernel.org/xen-devel/20250401130840.72119-1-roger.pau@citrix.com/ >> >> * [next-rel(s)] x86: generate xen.efi image with no write-execute sections >>   - Roger Pau Monne >>   - >> https://lore.kernel.org/xen-devel/20250318173547.59475-1-roger.pau@citrix.com/ >> >> *  [next-rel(s)] Expose consistent topology to guests (v7) >>   -  Alejandro Vallejo >>   - >> https://patchew.org/Xen/20241021154600.11745-1-alejandro.vallejo@cloud.com/ >> >> *  [next-rel(s)] x86/alternatives: Adjust all insn-relative fields (v2) >>   -  Andrew Cooper >>   - >> https://lore.kernel.org/xen-devel/20241002152725.1841575-1-andrew.cooper3@citrix.com/T/#mac2deaea7e02a343210d61887486433d946ad129 >> >> *  [next-rel(s)] x86emul: misc additions (v7) >>   -  Jan Beulich >>   -https://patchew.org/Xen/3a25cd59-e1cb-4bfc-b868-fb11599d22f5@suse.com/ >> >> *  [next-rel(s)] x86: support AVX10 (v3) >>   -  Jan Beulich >>   - >> https://lore.kernel.org/xen-devel/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@suse.com/ >>   -https://patchew.org/Xen/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@suse.com/ > While it is correct that AVX10 is now to go first, AMX was lost as an item, and > APX (which I see no reason in posting as long as AVX10 doesn't make any progress) > was agreed to go after AVX10, before AMX. (KeyLocker was also lost, but that > happens to be correct, as with Intel abandoning the feature we apparently have no > plans anymore to make an attempt at supporting it.) > > FRED (being worked on by Andrew) is also entirely missing. > > Overall: There are very many items on this list, and it seems entirely clear to > me that not all of them will make it. I think it would be quite helpful to strip > down the set for 4.21 to some realistic subset. Maybe something to discuss on > the community call later today? Good point, lets discuss that tomorrow during the community call. ~ Oleksii --------------kZF3O5gOHXMsO4gSSGZUUrHA Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit


    On 8/6/25 8:05 AM, Jan Beulich wrote:
    On 05.08.2025 20:19, Oleksii Kurochko wrote:

    * Full list of items : *

= Projects =

== Hypervisor ==

* [4.21] xen/console: cleanup console input switch logic (v5)
   - Denis Mukhin
   - 
https://lore.kernel.org/xen-devel/20250530231841.73386-1-dmukhin@ford.com/

* [4.21] xen: introduce CONFIG_SYSCTL (v4 -> v8)
   -  Penny Zheng
   - 
https://lore.kernel.org/xen-devel/20250711043158.2566880-1-Penny.Zheng@amd.com/

* [4.21] Several CI cleanups and improvements, plus yet another new runner
   - Marek Marczykowski-Górecki
   - 
https://lore.kernel.org/xen-devel/cover.7da1777882774486a13e6f39ff4a2096f6b7901e.1744028549.git-series.marmarek@invisiblethingslab.com/
   - 
https://patchew.org/Xen/cover.7da1777882774486a13e6f39ff4a2096f6b7901e.1744028549.git-series.marmarek@invisiblethingslab.com/

* [4.21] automation: Refresh the remaining Debian containers (v2)
   -  Javi Merino
   - 
https://lore.kernel.org/xen-devel/cover.1730743077.git.javi.merino@cloud.com/T/#m5d9acb7cf5db3c2be3d6527de14b69b07812314e

* [4.21] MSI-X support with qemu in stubdomain, and other related 
changes (v8)
   -  Marek Marczykowski-Górecki
   - 
https://lore.kernel.org/xen-devel/cover.33fb4385b7dd6c53bda4acf0a9e91748b3d7b1f7.1715313192.git-series.marmarek@invisiblethingslab.com/
   -  Only automation patch left to be reviewed/merged.

* [next-rel(s)] Physical address hypercall ABI ("HVMv2")
   - Teddy Astie
   - 
https://lore.kernel.org/xen-devel/cover.1744981654.git.teddy.astie@vates.tech/

* [next-rel(s)] xen: Untangle mm.h
   -  Andrew Cooper
   - 
https://lore.kernel.org/xen-devel/20250312174513.4075066-1-andrew.cooper3@citrix.com/
   - 
https://patchew.org/Xen/20250312174513.4075066-1-andrew.cooper3@citrix.com/

* [next-rel(s)] Add support for exact-node memory claims
   -  Alejandro Vallejo
   - 
https://lore.kernel.org/xen-devel/20250314172502.53498-1-alejandro.vallejo@cloud.com/
   - 
https://patchew.org/Xen/20250314172502.53498-1-alejandro.vallejo@cloud.com/

* [next-rel(s)] Remove the directmap (v5)
   -  Alejandro Vallejo
   - 
https://lore.kernel.org/xen-devel/20250108151822.16030-1-alejandro.vallejo@cloud.com/
   - 
https://patchew.org/Xen/20250108151822.16030-1-alejandro.vallejo@cloud.com/

* [next-rel(s)] GRUB: Supporting Secure Boot of xen.gz (v1)
   -  Ross Lagerwall
   - 
https://patchew.org/Xen/20240313150748.791236-1-ross.lagerwall@citrix.com/

* [next-rel(s)] Introduce xenbindgen to autogen hypercall structs (v1)
   -  Alejandro Vallejo
   - 
https://patchew.org/Xen/20241115115200.2824-1-alejandro.vallejo@cloud.com/

* [next-rel(s)] Introduce NS8250 UART emulator (v2)
   -  Denis Mukhin
   - 
https://patchew.org/Xen/20241205-vuart-ns8250-v1-0-e9aa923127eb@ford.com/

* [next-rel(s)] xen: framework for UART emulators
   - Denis Mukhin
   - 
https://lore.kernel.org/xen-devel/20250624035443.344099-1-dmukhin@ford.com/

=== x86 ===
* [4.21] x86/asm: cleanups after toolchain baseline upgrade (v1 -> v2)
   - Denis Mukhin
   - 
https://lore.kernel.org/xen-devel/20250403182250.3329498-1-dmukhin@ford.com/
   - https://patchew.org/Xen/20250403182250.3329498-1-dmukhin@ford.com/

* [4.21?] x86/efi: Fix booting when NX is disabled (v1 -> v2)
   - Andrew Cooper
   - 
https://patchew.org/Xen/20240722101838.3946983-1-andrew.cooper3@citrix.com/
   - 
https://lore.kernel.org/xen-devel/20240722101838.3946983-1-andrew.cooper3@citrix.com/

* [4.21?] Hyperlaunch device tree for dom0 (v6)
   - Alejandro Vallejo
   - https://patchew.org/Xen/20250429123629.20839-1-agarciav@amd.com/
   - 
https://lore.kernel.org/xen-devel/20250429123629.20839-1-agarciav@amd.com/

*  [4.21?] Boot modules for Hyperlaunch (v9)
   -  Daniel P. Smith
   - 
https://lore.kernel.org/xen-devel/20241115131204.32135-1-dpsmith@apertussolutions.com/
   - 
https://patchew.org/Xen/20241115131204.32135-1-dpsmith@apertussolutions.com/

*  [4.21?] Address Space Isolation FPU preparations (v2->v3)
   -  Alejandro Vallejo
   - 
https://patchew.org/Xen/20250110132823.24348-1-alejandro.vallejo@cloud.com/

* [next-rel(s)] Hyperlaunch domain builder
   - Daniel P. Smith
   - 
https://lore.kernel.org/xen-devel/20250515131744.3843-1-dpsmith@apertussolutions.com/

* [next-rel(s)] Confidential computing and AMD SEV support
   - Teddy Astie
   - https://patchew.org/Xen/cover.1747312394.git.teddy.astie@vates.tech/
   - 
https://lore.kernel.org/xen-devel/cover.1747312394.git.teddy.astie@vates.tech/

* [next-rel(s)] amd-cppc CPU Performance Scaling Driver (v5 -> v6)
   - Penny Zheng
   - 
https://lore.kernel.org/xen-devel/20250711035106.2540522-1-Penny.Zheng@amd.com/

* [next-rel(s)] x86: Trenchboot Secure Launch DRTM (Xen) (v1 -> v3)
   - Sergii Dmytruk
   - https://patchew.org/Xen/cover.1745172094.git.sergii.dmytruk@3mdeb.com/
   - 
https://lore.kernel.org/xen-devel/cover.1748611041.git.sergii.dmytruk@3mdeb.com/

* [next-rel(s)] x86/EFI: prevent write-execute sections
   - Roger Pau Monne <roger.pau@citrix.com>
   - 
https://lore.kernel.org/xen-devel/20250401130840.72119-1-roger.pau@citrix.com/

* [next-rel(s)] x86: generate xen.efi image with no write-execute sections
   - Roger Pau Monne
   - 
https://lore.kernel.org/xen-devel/20250318173547.59475-1-roger.pau@citrix.com/

*  [next-rel(s)] Expose consistent topology to guests (v7)
   -  Alejandro Vallejo
   - 
https://patchew.org/Xen/20241021154600.11745-1-alejandro.vallejo@cloud.com/

*  [next-rel(s)] x86/alternatives: Adjust all insn-relative fields (v2)
   -  Andrew Cooper
   - 
https://lore.kernel.org/xen-devel/20241002152725.1841575-1-andrew.cooper3@citrix.com/T/#mac2deaea7e02a343210d61887486433d946ad129

*  [next-rel(s)] x86emul: misc additions (v7)
   -  Jan Beulich
   - https://patchew.org/Xen/3a25cd59-e1cb-4bfc-b868-fb11599d22f5@suse.com/

*  [next-rel(s)] x86: support AVX10 (v3)
   -  Jan Beulich
   - 
https://lore.kernel.org/xen-devel/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@suse.com/
   - https://patchew.org/Xen/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@suse.com/

    While it is correct that AVX10 is now to go first, AMX was lost as an item, and
APX (which I see no reason in posting as long as AVX10 doesn't make any progress)
was agreed to go after AVX10, before AMX. (KeyLocker was also lost, but that
happens to be correct, as with Intel abandoning the feature we apparently have no
plans anymore to make an attempt at supporting it.)

FRED (being worked on by Andrew) is also entirely missing.

Overall: There are very many items on this list, and it seems entirely clear to
me that not all of them will make it. I think it would be quite helpful to strip
down the set for 4.21 to some realistic subset. Maybe something to discuss on
the community call later today?
    Good point, lets discuss that tomorrow during the community call.

~ Oleksii
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Introduce a MSI-X cleanup hook that will be called when > >>> initialization fails to cleanup MSI-X related hooks and free it's > >>> associated data. > >>> > >>> As all supported capabilities have been switched to use the cleanup > >>> hooks call those from vpci_deassign_device() instead of open-code the > >>> capability specific cleanup in there. > >>> > >>> Signed-off-by: Jiqian Chen > >>> --- > >>> cc: "Roger Pau Monné" > >>> --- > >>> v9->v10 changes: > >>> * Call all cleanup hook in vpci_deassign_device() instead of cleanup_msix(). > >> > >> Isn't this rather an omission in an earlier change, and hence may want to > >> come separately and with a Fixes: tag? > > This is not really an omission, after all, all the cleanup hooks were implemented at the end of this series. > > And judging from the commit message(which was written by Roger in v8), Roger also agreed to add them in this patch. > > I disagree. Of the two xfree()-s you remove here from vpci_deassign_device(), > one should have been removed by patch 3 already. Which would require the > part of the patch here to be put in place earlier on. I don't think a Fixes tag is strictly required - the previous functionality will not lead to malfunction, albeit it's best to use the cleanup hooks introduced here. Up until the hooks are executed as part of vpci_deassign_device() the xfree() calls need to remain in place. Conceptually it would have been better to add the calls to the ->cleanup() hooks in vpci_deassign_device() in the same patch that added the vpci_init_capabilities() ->init() and ->cleanup() logic. It was my bad for noting this only when reviewing patch 8, and then not asking for it to be placed in the right patch. Thanks, Roger. From xen-devel-bounces@lists.xenproject.org Wed Aug 06 08:11:41 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 08:11:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071353.1434814 (Exim 4.92) (envelope-from ) id 1ujZFF-0007e7-Rp; Wed, 06 Aug 2025 08:11:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071353.1434814; Wed, 06 Aug 2025 08:11:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZFF-0007e0-Ob; Wed, 06 Aug 2025 08:11:33 +0000 Received: by outflank-mailman (input) for mailman id 1071353; Wed, 06 Aug 2025 08:11:32 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZFE-0007cc-Ig for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 08:11:32 +0000 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id f0a9d23e-729c-11f0-a322-13f23c93f187; Wed, 06 Aug 2025 10:11:27 +0200 (CEST) Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4bxjYD0qPnz14ML1; Wed, 6 Aug 2025 16:06:24 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 55C9114022F; Wed, 6 Aug 2025 16:11:20 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 6 Aug 2025 16:11:19 +0800 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f0a9d23e-729c-11f0-a322-13f23c93f187 Message-ID: <94757d00-5a8e-ac6b-f832-030f33ccf771@huawei.com> Date: Wed, 6 Aug 2025 16:11:18 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH -next v7 0/7] arm64: entry: Convert to generic irq entry Content-Language: en-US To: Ada Couprie Diaz CC: , , , , , , , , , , , , , , , , , , References: <20250729015456.3411143-1-ruanjinjie@huawei.com> <6bd09b5b-9830-42b4-ad9e-9ad1e153e564@arm.com> From: Jinjie Ruan In-Reply-To: <6bd09b5b-9830-42b4-ad9e-9ad1e153e564@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.67.109.254] X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To dggpemf500011.china.huawei.com (7.185.36.131) On 2025/8/5 23:08, Ada Couprie Diaz wrote: > Hi Jinjie, > > On 29/07/2025 02:54, Jinjie Ruan wrote: > >> Since commit a70e9f647f50 ("entry: Split generic entry into generic >> exception and syscall entry") split the generic entry into generic irq >> entry and generic syscall entry, it is time to convert arm64 to use >> the generic irq entry. And ARM64 will be completely converted to generic >> entry in the upcoming patch series. > Note : I had to manually cherry-pick a70e9f647f50 when pulling the series > on top of the Linux Arm Kernel for-next/core branch, but there might be > something I'm missing here. >> It seems that it is now in mainline v6.16-rc1 and linux-next but not Linux Arm Kernel for-next/core branch. [...] > I'll spend some time testing the series now, specifically given patch 6's > changes, but other than that everything I saw made sense and didn't look > like it would be of concern to me. Thank you for the test and review. > > Thanks, > Ada > From xen-devel-bounces@lists.xenproject.org Wed Aug 06 08:11:41 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 08:11:41 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071354.1434824 (Exim 4.92) (envelope-from ) id 1ujZFN-0007tf-2e; Wed, 06 Aug 2025 08:11:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071354.1434824; Wed, 06 Aug 2025 08:11:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZFM-0007tY-Ve; Wed, 06 Aug 2025 08:11:40 +0000 Received: by outflank-mailman (input) for mailman id 1071354; Wed, 06 Aug 2025 08:11:39 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZFL-0007Yx-K8 for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 08:11:39 +0000 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [2a00:1450:4864:20::52c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id f9b18d0d-729c-11f0-b898-0df219b8e170; Wed, 06 Aug 2025 10:11:37 +0200 (CEST) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-615378b42ecso9306705a12.0 for ; Wed, 06 Aug 2025 01:11:37 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 06 Aug 2025 01:11:37 -0700 (PDT) Message-ID: <68da529e-7fd7-4ca5-b6ef-4c1f95423246@suse.com> Date: Wed, 6 Aug 2025 10:11:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 8/8] x86/mm: adjust loop in arch_init_memory() to iterate over the PDX space To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: Andrew Cooper , xen-devel@lists.xenproject.org References: <20250805095257.74975-1-roger.pau@citrix.com> <20250805095257.74975-9-roger.pau@citrix.com> <31691bf7-94bf-4f73-b04c-a32f86bb0e37@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05.08.2025 17:27, Roger Pau Monné wrote: > On Tue, Aug 05, 2025 at 02:38:38PM +0200, Jan Beulich wrote: >> On 05.08.2025 11:52, Roger Pau Monne wrote: >>> --- a/xen/arch/x86/mm.c >>> +++ b/xen/arch/x86/mm.c >>> @@ -275,7 +275,7 @@ static void __init assign_io_page(struct page_info *page) >>> >>> void __init arch_init_memory(void) >>> { >>> - unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn; >>> + unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn, pdx; >>> >>> /* >>> * Basic guest-accessible flags: >>> @@ -328,9 +328,20 @@ void __init arch_init_memory(void) >>> destroy_xen_mappings((unsigned long)mfn_to_virt(iostart_pfn), >>> (unsigned long)mfn_to_virt(ioend_pfn)); >>> >>> - /* Mark as I/O up to next RAM region. */ >>> - for ( ; pfn < rstart_pfn; pfn++ ) >>> + /* >>> + * Mark as I/O up to next RAM region. Iterate over the PDX space to >>> + * skip holes which would always fail the mfn_valid() check. >>> + * >>> + * pfn_to_pdx() requires a valid (iow: RAM) PFN to convert to PDX, >>> + * hence provide pfn - 1, which is the tailing PFN from the last RAM >>> + * range, or pdx 0 if the input pfn is 0. >>> + */ >>> + for ( pdx = pfn ? pfn_to_pdx(pfn - 1) + 1 : 0; >>> + pdx < pfn_to_pdx(rstart_pfn); >>> + pdx++ ) >>> { >>> + pfn = pdx_to_pfn(pdx); >>> + >>> if ( !mfn_valid(_mfn(pfn)) ) >>> continue; >>> >> >> As much as I would have liked to ack this, I fear there's another caveat here: >> At the top of the loop we check not only for RAM, but also for UNUSABLE. The >> latter, like RAM, shouldn't be marked I/O, but we also can't use PFN <-> PDX >> transformations on any such page. > > Right you are. I'm not sure however why we do this - won't we want > the mappings of UNUSABLE regions also be removed from the Xen > page-tables? (but not marked as IO) Yes, I think this is a flaw in current code. Perhaps it was (wrongly) assumed that no UNUSABLE regions would ever exist this low in a memory map? Imo we want to deal with this in two steps - first sort the UNUSABLE issue, then improve the dealing with what is passed to assign_io_page(). While there we may also want to find a way to tie together the 16Mb boundary checks - the 16UL isn't properly connected to the BOOTSTRAP_MAP_BASE definition in setup.c. Yet then: Am I overlooking something, or is the 16Mb boundary not really special anymore? I.e. could e.g. BOOTSTRAP_MAP_BASE perhaps be moved (at least in principle), either almost arbitrarily up (within the low 4Gb), or down as much as to the 2Mb boundary? The relevant aspect here would be that the comment saying "the statically-initialised 1-16MB mapping area" looks to be stale, as of 7cd7f2f5e116 ("x86/boot: Remove the preconstructed low 16M superpage mappings"). If there are excess mappings to worry about, those may nowadays well live above the 16Mb boundary (because of it being 2Mb mappings that head.S inserts into l2_directmap[]). If I was to sensibly make changes to that code, I guess I first ought to find a system which actually surfaces any (ideally "interesting") UNUSABLE ranges. In any event, I think the cleanest thing we can do is split the loop in two, one to deal with the removal of mappings between RAM regions up to the 4Gb boundary, and the other to invoke assign_io_page() for holes between RAM || UNUSABLE ones. The latter would then be subject to your optimization. The former could ignore the PDX aspect due to being limited to the low 4Gb, where we never compress. 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Smith" , Grygorii Strashko , Alejandro Vallejo , "committers@xenproject.org" , Community Manager , Xen-devel References: <242a93cf-20f7-4fcd-8eef-6945af5d864c@suse.com> <03a1d0b8-facd-4c02-97c6-45fa694da0b6@gmail.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <03a1d0b8-facd-4c02-97c6-45fa694da0b6@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 06.08.2025 09:45, Oleksii Kurochko wrote: > On 8/6/25 8:05 AM, Jan Beulich wrote: >> Overall: There are very many items on this list, and it seems entirely clear to >> me that not all of them will make it. I think it would be quite helpful to strip >> down the set for 4.21 to some realistic subset. Maybe something to discuss on >> the community call later today? > > Good point, lets discuss that tomorrow during the community call. Oh, right, it's only Wednesday today. Jan From xen-devel-bounces@lists.xenproject.org Wed Aug 06 08:16:32 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 08:16:32 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071394.1434856 (Exim 4.92) (envelope-from ) id 1ujZK0-00010A-Ux; Wed, 06 Aug 2025 08:16:28 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071394.1434856; Wed, 06 Aug 2025 08:16:28 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZK0-000103-Rz; Wed, 06 Aug 2025 08:16:28 +0000 Received: by outflank-mailman (input) for mailman id 1071394; Wed, 06 Aug 2025 08:16:27 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZJz-0000zX-6T for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 08:16:27 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1ujZJy-004MLN-2F; Wed, 06 Aug 2025 08:16:26 +0000 Received: from [2a01:cb15:80df:da00:780b:80d6:89ae:cd4d] (helo=l14) by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1ujZJy-006fUE-16; Wed, 06 Aug 2025 08:16:26 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xenproject.org; s=20200302mail; h=In-Reply-To:Content-Transfer-Encoding: Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=DunmOPknlULrykY12F/SXCDD6v08oltn7onGcW3sDM0=; b=PiyAYAUTKbZl0PmrHmvsmXfbpb sbOditSKN3dVU14e6MM5x7sJFF56tAjRBXZiRcC56s/pxkJ5nwu4LxDlW7PvGuOnbZ+cDpPt4aGzl +v8mKhhfLzncaDOfO828suM3LF+6J0mjcR4ytLAxSF73lp0oMLmBVH4X15DMZ2iJ4+qs=; Date: Wed, 6 Aug 2025 10:16:24 +0200 From: Anthony PERARD To: Roger Pau Monne Cc: xen-devel@lists.xenproject.org, Anthony PERARD , Andrew Cooper , Michal Orzel , Jan Beulich , Julien Grall , Stefano Stabellini Subject: Re: [PATCH v4 5/8] test/pdx: add PDX compression unit tests Message-ID: References: <20250805095257.74975-1-roger.pau@citrix.com> <20250805095257.74975-6-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250805095257.74975-6-roger.pau@citrix.com> On Tue, Aug 05, 2025 at 11:52:54AM +0200, Roger Pau Monne wrote: > Introduce a set of unit tests for PDX compression. The unit tests contains > both real and crafted memory maps that are then compressed using the > selected PDX algorithm. Note the build system for the unit tests has been > done in a way to support adding new compression algorithms easily. That > requires generating a new test-pdx- executable that's build with > the selected PDX compression enabled. > > Currently the only generated executable is test-pdx-mask that tests PDX > mask compression. > > Signed-off-by: Roger Pau Monné Reviewed-by: Anthony PERARD Thanks, -- Anthony PERARD From xen-devel-bounces@lists.xenproject.org Wed Aug 06 08:19:12 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 08:19:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071412.1434865 (Exim 4.92) (envelope-from ) id 1ujZMc-0001b6-Gd; Wed, 06 Aug 2025 08:19:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071412.1434865; Wed, 06 Aug 2025 08:19:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZMc-0001az-E2; Wed, 06 Aug 2025 08:19:10 +0000 Received: by outflank-mailman (input) for mailman id 1071412; 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>> >> In case of dom0less boot the "dom0_mem" is not used and defaulted to 0, > > From docs/mics/xen-command-linux.pandoc: > > --- > > ### dom0_mem (ARM) > > `= ` > > Set the amount of memory for the initial domain (dom0). It must be > greater than zero. This parameter is required. > > --- > > If dom0_mem is effectively optional, then shouldn't the doc be updated? No. I think doc is correct because when regular Dom0(hwdom)(initial domain) is created code goes through regular Dom0 path and "dom0_mem" is accounted for. create_dom0()->construct_dom0() kinfo.unassigned_mem = dom0_mem; construct_hwdom()->allocate_memory_11() The issue happens in dom0less mode when hwdom is created and domain's configuration parameters are obtained from DT. > >> which causes min_low_order to get high value > order and so no allocations >> happens from low memory. > > > Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" has correct Right, it should be "which has" >> memory size in both cases: regular dom0 boot and dom0less boot. >> >> Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction") >> Signed-off-by: Grygorii Strashko >> Reviewed-by: Denis Mukhin >> Reviewed-by: Jason Andryuk > > Acked-by: Julien Grall > > Cheers, > -- Best regards, -grygorii From xen-devel-bounces@lists.xenproject.org Wed Aug 06 08:22:12 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 08:22:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071424.1434876 (Exim 4.92) (envelope-from ) id 1ujZPU-0003KU-UY; Wed, 06 Aug 2025 08:22:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071424.1434876; Wed, 06 Aug 2025 08:22:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZPU-0003KN-Qo; Wed, 06 Aug 2025 08:22:08 +0000 Received: by outflank-mailman (input) for mailman id 1071424; Wed, 06 Aug 2025 08:22:07 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZPT-0003KH-O9 for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 08:22:07 +0000 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [2a00:1450:4864:20::336]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 709a9d19-729e-11f0-a322-13f23c93f187; Wed, 06 Aug 2025 10:22:07 +0200 (CEST) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-459eb4ae596so391525e9.1 for ; Wed, 06 Aug 2025 01:22:07 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. 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So here let the control register of MSIX > > + * be Read-Only is to ensure MSIX disabled. > > + */ > > + rc = vpci_add_register(vpci, vpci_hw_read16, NULL, > > + msix_control_reg(msix_pos), 2, NULL); > > + if ( rc ) > > + printk(XENLOG_ERR "%pd %pp: fail to add MSIX ctrl handler rc=%d\n", > > + pdev->domain, &pdev->sbdf, rc); > > Here as well as for MSI: Wouldn't this better be limited to the init-failure > case? No point in adding a register hook (and possibly emitting a misleading > log message) when we're tearing down anyway. IOW I think the ->cleanup() > hook needs a boolean parameter, unless the distinction of the two cases can > be (reliably) inferred from some other property. I don't think we have any signal in pci_dev itself that notices whether the device is being deassigned, in which case it does need an extra boolean parameter to notice whether to add the r/o handler. I'm also wondering whether we want to limit this hiding to the hardware domain only, and for domUs fail the operation instead, and fail to assign the device. That can be adjusted in a later patch though. Thanks, Roger. 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Wed, 06 Aug 2025 01:30:54 -0700 (PDT) Message-ID: <20990797-0523-429d-a920-a8e2ba92d18b@suse.com> Date: Wed, 6 Aug 2025 10:30:53 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 4/4] vpci/msix: Free MSIX resources when init_msix() fails To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: Jiqian Chen , Huang Rui , xen-devel@lists.xenproject.org References: <20250805034906.1014212-1-Jiqian.Chen@amd.com> <20250805034906.1014212-5-Jiqian.Chen@amd.com> <775a45bd-61df-4cab-948e-bdc79dfd89ef@suse.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 06.08.2025 10:22, Roger Pau Monné wrote: > On Tue, Aug 05, 2025 at 10:43:09AM +0200, Jan Beulich wrote: >> On 05.08.2025 05:49, Jiqian Chen wrote: >>> --- a/xen/drivers/vpci/msix.c >>> +++ b/xen/drivers/vpci/msix.c >>> @@ -655,6 +655,48 @@ int vpci_make_msix_hole(const struct pci_dev *pdev) >>> return 0; >>> } >>> >>> +static int cf_check cleanup_msix(const struct pci_dev *pdev) >>> +{ >>> + int rc; >>> + struct vpci *vpci = pdev->vpci; >>> + const unsigned int msix_pos = pdev->msix_pos; >>> + >>> + if ( !msix_pos ) >>> + return 0; >>> + >>> + rc = vpci_remove_registers(vpci, msix_control_reg(msix_pos), 2); >>> + if ( rc ) >>> + { >>> + printk(XENLOG_ERR "%pd %pp: fail to remove MSIX handlers rc=%d\n", >>> + pdev->domain, &pdev->sbdf, rc); >>> + ASSERT_UNREACHABLE(); >>> + return rc; >>> + } >>> + >>> + if ( vpci->msix ) >>> + { >>> + list_del(&vpci->msix->next); >>> + for ( unsigned int i = 0; i < ARRAY_SIZE(vpci->msix->table); i++ ) >>> + if ( vpci->msix->table[i] ) >>> + iounmap(vpci->msix->table[i]); >>> + >>> + XFREE(vpci->msix); >>> + } >>> + >>> + /* >>> + * The driver may not traverse the capability list and think device >>> + * supports MSIX by default. So here let the control register of MSIX >>> + * be Read-Only is to ensure MSIX disabled. >>> + */ >>> + rc = vpci_add_register(vpci, vpci_hw_read16, NULL, >>> + msix_control_reg(msix_pos), 2, NULL); >>> + if ( rc ) >>> + printk(XENLOG_ERR "%pd %pp: fail to add MSIX ctrl handler rc=%d\n", >>> + pdev->domain, &pdev->sbdf, rc); >> >> Here as well as for MSI: Wouldn't this better be limited to the init-failure >> case? No point in adding a register hook (and possibly emitting a misleading >> log message) when we're tearing down anyway. IOW I think the ->cleanup() >> hook needs a boolean parameter, unless the distinction of the two cases can >> be (reliably) inferred from some other property. > > I don't think we have any signal in pci_dev itself that notices > whether the device is being deassigned, in which case it does need an > extra boolean parameter to notice whether to add the r/o handler. > > I'm also wondering whether we want to limit this hiding to the > hardware domain only, and for domUs fail the operation instead, and > fail to assign the device. That can be adjusted in a later patch > though. Yes, DomU wants handling as you say. Iirc there are other open issues with DomU support, though. Hence yes, "later" ought to suffice here. Perhaps worth annotating with a fixme, though, to be able to easily spot all the places that require adjustment. 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So here let the control register of MSIX > >>> + * be Read-Only is to ensure MSIX disabled. > >>> + */ > >>> + rc = vpci_add_register(vpci, vpci_hw_read16, NULL, > >>> + msix_control_reg(msix_pos), 2, NULL); > >>> + if ( rc ) > >>> + printk(XENLOG_ERR "%pd %pp: fail to add MSIX ctrl handler rc=%d\n", > >>> + pdev->domain, &pdev->sbdf, rc); > >> > >> Here as well as for MSI: Wouldn't this better be limited to the init-failure > >> case? No point in adding a register hook (and possibly emitting a misleading > >> log message) when we're tearing down anyway. IOW I think the ->cleanup() > >> hook needs a boolean parameter, unless the distinction of the two cases can > >> be (reliably) inferred from some other property. > > > > I don't think we have any signal in pci_dev itself that notices > > whether the device is being deassigned, in which case it does need an > > extra boolean parameter to notice whether to add the r/o handler. > > > > I'm also wondering whether we want to limit this hiding to the > > hardware domain only, and for domUs fail the operation instead, and > > fail to assign the device. That can be adjusted in a later patch > > though. > > Yes, DomU wants handling as you say. Iirc there are other open issues with > DomU support, though. Hence yes, "later" ought to suffice here. Perhaps > worth annotating with a fixme, though, to be able to easily spot all the > places that require adjustment. Sometimes I don't take into account that vPCI is also supposed to be used by domUs in the long run and forget about that aspect when reviewing patches Roger. From xen-devel-bounces@lists.xenproject.org Wed Aug 06 08:48:12 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 08:48:12 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071467.1434905 (Exim 4.92) (envelope-from ) id 1ujZoc-0007eT-CV; Wed, 06 Aug 2025 08:48:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071467.1434905; Wed, 06 Aug 2025 08:48:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZoc-0007eM-9x; Wed, 06 Aug 2025 08:48:06 +0000 Received: by outflank-mailman (input) for mailman id 1071467; Wed, 06 Aug 2025 08:48:05 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujZob-0007eG-Cb for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 08:48:05 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.96) (envelope-from ) id 1ujZoa-004N02-24; Wed, 06 Aug 2025 08:48:04 +0000 Received: from [15.248.3.95] (helo=[10.24.67.219]) by xenbits.xenproject.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.96) (envelope-from ) id 1ujZoa-006h07-1L; Wed, 06 Aug 2025 08:48:04 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=M6PvuqvXz/6ABB1gSm81kTqZeDu/E6K5yov6LNNWdME=; b=1x46Tfw+krHgLK9d4I11eMKoLY l0GiBSEcK2Ff6rkzEugAjWLIoXGBTvFN53y/i7UM1JzJQsY0C7QTK/1rZWKmFkWP58mGBuyJjxCr4 dYpLuwJNey7t9sbLV+N7bwB5kwhIM6siovyaIvzYOV29X1xfFnwgDelEXu+UuV3PYVss=; Message-ID: <72f0d4bd-65b6-4904-8fd6-b714058923b2@xen.org> Date: Wed, 6 Aug 2025 09:48:02 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] xen/dom0less: arm: fix hwdom 1:1 low memory allocation Content-Language: en-GB To: Grygorii Strashko , "xen-devel@lists.xenproject.org" Cc: Stefano Stabellini , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Denis Mukhin , Jason Andryuk References: <20250805190017.209711-1-grygorii_strashko@epam.com> <5807ed03-7db2-4ce6-9acf-c4d515fbd293@xen.org> <5a33ddf2-716e-4fca-8764-760dec9944ce@epam.com> From: Julien Grall In-Reply-To: <5a33ddf2-716e-4fca-8764-760dec9944ce@epam.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Grygorii, On 06/08/2025 09:19, Grygorii Strashko wrote: > Hi Julien, > > On 06.08.25 00:07, Julien Grall wrote: >> Hi Grygorii, >> >> On 05/08/2025 20:00, Grygorii Strashko wrote: >>> From: Grygorii Strashko >>> >>> Call stack for dom0less hwdom case (1:1) memory: >>> create_domUs >>> |-construct_domU >>>    |-construct_hwdom() >>>      |-allocate_memory_11() >>> >>> And allocate_memory_11() uses "dom0_mem" as: >>> min_low_order = >>>    get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128))); >>> >>> In case of dom0less boot the "dom0_mem" is not used and defaulted to 0, >> >>  From docs/mics/xen-command-linux.pandoc: >> >> --- >> >> ### dom0_mem (ARM) >>  > `= ` >> >> Set the amount of memory for the initial domain (dom0). It must be >> greater than zero. This parameter is required. >> >> --- >> >> If dom0_mem is effectively optional, then shouldn't the doc be updated? > > No. I think doc is correct because when regular Dom0(hwdom)(initial domain) > is created code goes through regular Dom0 path and "dom0_mem" is > accounted for. I understand this is used when dom0 is not described in the device tree. The crucial part in your sentence is "when", to me this indicates a condition. Whereas the current wording in xen-command-linux is using "required" with no condition. So a reader can rightfully think the parameter is also used in dom0less and have to be specified. So I think the wording needs to be tweaked to something like "This parameter is required (and only used) when the initial domain is not described in the Device-Tree." Although, "required" might still be too strict because it looks like we would provide a configuration for dom0_mem if it is not set. Cheers, -- Julien Grall From xen-devel-bounces@lists.xenproject.org Wed Aug 06 09:27:31 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 09:27:31 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071484.1434915 (Exim 4.92) (envelope-from ) id 1ujaQa-0004t4-9O; Wed, 06 Aug 2025 09:27:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071484.1434915; Wed, 06 Aug 2025 09:27:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujaQa-0004sx-6p; Wed, 06 Aug 2025 09:27:20 +0000 Received: by outflank-mailman (input) for mailman id 1071484; Wed, 06 Aug 2025 09:27:19 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujaQY-0004sp-JF for xen-devel@lists.xenproject.org; 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Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2025-08-05 15:22, Nicola Vetrini wrote: > On 2025-08-05 13:49, Dmytro Prokopchuk1 wrote: >> On 7/31/25 19:09, Nicola Vetrini wrote: >>> On 2025-07-31 18:05, Andrew Cooper wrote: >>>> On 31/07/2025 4:58 pm, Jan Beulich wrote: >>>>> On 31.07.2025 17:37, Andrew Cooper wrote: >>>>>> On 31/07/2025 4:16 pm, Dmytro Prokopchuk1 wrote: >>>>>>> MISRA Rule 13.1: Initializer lists shall not contain persistent >>>>>>> side >>>>>>> effects. >>>>>>> >>>>>>> The violations occur because both the `GVA_INFO` and `TRACE_TIME` >>>>>>> macro >>>>>>> expansions include expressions with persistent side effects >>>>>>> introduced >>>>>>> via inline assembly. >>>>>>> >>>>>>> In the case of `GVA_INFO`, the issue stems from the initializer >>>>>>> list >>>>>>> containing a direct call to `current`, which evaluates to >>>>>>> `this_cpu(curr_vcpu)` and involves persistent side effects via >>>>>>> the >>>>>>> `asm` statement. To resolve this, the side-effect-producing >>>>>>> expression >>>>>>> is computed in a separate statement prior to the macro >>>>>>> initialization: >>>>>>> >>>>>>>     struct vcpu *current_vcpu = current; >>>>>>> >>>>>>> The computed value is passed into the `GVA_INFO(current_vcpu)` >>>>>>> macro, >>>>>>> ensuring that the initializer is clean and free of such side >>>>>>> effects. >>>>>>> >>>>>>> Similarly, the `TRACE_TIME` macro violates this rule when >>>>>>> accessing >>>>>>> expressions like `current->vcpu_id` and >>>>>>> `current->domain->domain_id`, >>>>>>> which also depend on `current` and inline assembly. To fix this, >>>>>>> the >>>>>>> value of `current` is assigned to a temporary variable: >>>>>>> >>>>>>>     struct vcpu *v = current; >>>>>>> >>>>>>> This temporary variable is then used to access `domain_id` and >>>>>>> `vcpu_id`. >>>>>>> This ensures that the arguments passed to the `TRACE_TIME` macro >>>>>>> are >>>>>>> simple expressions free of persistent side effects. >>>>>>> >>>>>>> Signed-off-by: Dmytro Prokopchuk >>>>>> The macro `current` specifically does not (and must not) have side >>>>>> effects.  It is expected to behave like a plain `struct vcpu >>>>>> *current;` >>>>>> variable, and what Eclair is noticing is the thread-local >>>>>> machinery >>>>>> under this_cpu() (or in x86's case, get_current()). >>>>>> >>>>>> In ARM's case, it's literally reading the hardware thread pointer >>>>>> register.  Can anything be done to tell Eclair that `this_cpu()` >>>>>> specifically does not have side effects? >>>>>> >>>>>> The only reason that GVA_INFO() and TRACE_TIME() are picked out is >>>>>> because they both contain embedded structure initialisation, and >>>>>> this is >>>>>> is actually an example where trying to comply with MISRA >>>>>> interferes >>>>>> with >>>>>> what is otherwise a standard pattern in Xen. >>>>> Irrespective of what you say, some of the changes here were >>>>> eliminating >>>>> multiple adjacent uses of current, which - iirc - often the >>>>> compiler >>>>> can't fold via CSE. >>>> >>>> Where we have mixed usage, sure.  (I'm sure I've got a branch >>>> somewhere >>>> trying to add some more pure/const around to try and help out here, >>>> but >>>> I can't find it, and don't recall it being a major improvement >>>> either.) >>>> >>>> The real problem here is that there are a *very few* number of >>>> contexts >>>> where Eclair refuses to tolerate the use of `current` citing side >>>> effects, despite there being no side effects. >>>> >>>> That is the thing that breaks the principle of least surprise, and >>>> we >>>> ought to fix it by making Eclair happy with `current` everywhere, >>>> rather >>>> than force people to learn that 2 macros can't have a `current` in >>>> their >>>> parameter list. >>>> >>> >>> I'll take a look. Likely yes, by adding a handful of properties. >>> There >>> are subtleties, though. >>> >> >> Hi, Nicola. >> >> Did you have a chance to try configure Eclair to ignore this macro >> `this_cpu()`? >> > > Hi Dmytro, > > I'm on it, I needed to handle other tasks first. > A solution has been devised by extending ECLAIR. The runner will be updated with the latest ECLAIR version, and as a result a couple of other patches will be submitted to adapt for it. >> Thanks. >> Dmytro -- Nicola Vetrini, B.Sc. Software Engineer BUGSENG (https://bugseng.com) LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253 From xen-devel-bounces@lists.xenproject.org Wed Aug 06 09:45:35 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 09:45:35 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071495.1434928 (Exim 4.92) (envelope-from ) id 1ujaiA-0007st-Jt; Wed, 06 Aug 2025 09:45:30 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071495.1434928; Wed, 06 Aug 2025 09:45:30 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujaiA-0007sm-HD; Wed, 06 Aug 2025 09:45:30 +0000 Received: by outflank-mailman (input) for mailman id 1071495; Wed, 06 Aug 2025 09:45:29 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujai9-0007sg-CH for xen-devel@lists.xenproject.org; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ae3fde9e-f313-43b8-e666-08ddd4ce90d9 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2025 09:49:41.4406 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 26c0S55bxFXW4hCuYd/JjRi1g2doeJSMTNBB0x/uJj+qEFl7cFCFS4PQgdxP3mHIPjndyHoPzm2k3VOTX/SabAndQuWUwrtS3Qz8hHHHL2c= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR03MB8421 From: Grygorii Strashko Hi, During review of v1 [1] of this series Julien Grall raised concern that=20 "If the desire is to make 32-bit domain optional on Arm64.=20 Then I think it would be better to pass the domain type when the domain is created (IOW add an extra flags to XEN_DOMCTL_createdomain)." for which I've sent patches attempting to start solving the problem [2] and try to probe guest kernels before creating domains. While proposed changes [2] is under review and hence there are definitely more work is required I'd appreciated if current series can be considered as it's Arm specific only and working (and tested) with current Xen in its current state. Now Arm64 AArch32 guest support is always enabled and built-in while not all Arm64 platforms supports AArch32 (for exmaple on Armv9A) or this support might not be needed (Arm64 AArch32 is used quite rarely in embedded systems). More over, when focusing on safety certification, AArch32 related code in Xen leaves a gap in terms of coverage that cannot really be justified in words. This leaves two options: either support it (lots of additional testing, requirements and documents would be needed) or compile it out. Patches 1-2 Prerequisite patches Patch 3 - allows to make aarch32 support optional by introducing Kconfig op= tion CONFIG_ARM64_AARCH32 Patch 4 - enables build-time optimization of AArch32 specific code by redef= ining some is_32/64bit_domain() macro as constants Tested (CONFIG_ARM64_AARCH32=3Dy/n): - dom0 with AArch32/64 kernel - toolstack create domain with AArch32/64 kernel - dom0less domains with AArch32/64 kernel - creating domain with AArch64 kernel and AArch32 EL0 rootfs Changes in v2: - dropped patches - (licensing issue) "xen/arm: move vcpu_switch_to_aarch64_mode() in arch_= vcpu_create()" - (problematic change) "xen/arm: move vcpu_switch_to_aarch64_mode() in ar= m64" - constifying is_32/64bit_domain() macro gives most of results in terms o= f coverage, drop regs changes for now (can be added latter): "xen/arm: regs.h split subarch definitions between arm64/arm32" "xen/arm64: constify regs_mode_is_32bit macro for CONFIG_ARM64_AARCH32= =3Dn" - use Arm64 "cpu_has_el1_32" in all places to check if HW has AArch32 suppo= rt - rework Arm64 XEN_DOMCTL_set_address_size hypercall handling to work with = any initial domain type set (32bit or 64 bit) - fix comments related to macro parameters evaluation issues - do not expose EL1 AArch32 support to guest in ID_AA64PFR0_EL1 reg if AArch32 is disabled Link on v1: [1] https://lore.kernel.org/xen-devel/20250723075835.3993182-1-grygorii_str= ashko@epam.com/ [2] https://patchwork.kernel.org/project/xen-devel/cover/20250731094234.996= 684-1-grygorii_strashko@epam.com/ Grygorii Strashko (4): xen/arm: split set_domain_type() between arm64/arm32 xen/arm: split is_32bit/64bit_domain() between arm64/arm32 xen/arm64: allow to make aarch32 support optional xen/arm64: constify is_32/64bit_domain() macro for CONFIG_ARM64_AARCH32=3Dn xen/arch/arm/Kconfig | 7 +++ xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/domain-build.c | 22 +++++++++ xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/domain-build.c | 66 +++++++++++++++++++++++++ xen/arch/arm/arm64/domctl.c | 16 +++--- xen/arch/arm/arm64/vsysreg.c | 9 ++++ xen/arch/arm/dom0less-build.c | 14 ------ xen/arch/arm/domain.c | 9 ++++ xen/arch/arm/domain_build.c | 21 ++------ xen/arch/arm/include/asm/arm32/domain.h | 32 ++++++++++++ xen/arch/arm/include/asm/arm64/domain.h | 54 ++++++++++++++++++++ xen/arch/arm/include/asm/domain.h | 7 ++- xen/arch/arm/setup.c | 2 +- xen/include/xen/dom0less-build.h | 8 +++ 15 files changed, 227 insertions(+), 42 deletions(-) create mode 100644 xen/arch/arm/arm32/domain-build.c create mode 100644 xen/arch/arm/arm64/domain-build.c create mode 100644 xen/arch/arm/include/asm/arm32/domain.h create mode 100644 xen/arch/arm/include/asm/arm64/domain.h --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Aug 06 09:49:49 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 09:49:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071505.1434952 (Exim 4.92) (envelope-from ) id 1ujamK-0000DM-QR; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f019145d-935e-446f-2356-08ddd4ce9230 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2025 09:49:42.6498 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Tms3Q2PwycUcYmsiQC23Gay6DWCqfl/ZjqL/hgyVrLqg2e3lrYCzWsk2zgpqpLplDuhUxguEc7Cq/Nm7XYgwNxgUs0EuOOsObr2Q+pqENCw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR03MB10887 From: Grygorii Strashko Split is_32bit/64bit_domain() macro implementations between arm64/arm32. Signed-off-by: Grygorii Strashko --- v2: - fix comments related to macro parameters evaluation issues xen/arch/arm/include/asm/arm32/domain.h | 20 +++++++++++++++++ xen/arch/arm/include/asm/arm64/domain.h | 29 +++++++++++++++++++++++++ xen/arch/arm/include/asm/domain.h | 7 +++--- 3 files changed, 52 insertions(+), 4 deletions(-) create mode 100644 xen/arch/arm/include/asm/arm32/domain.h create mode 100644 xen/arch/arm/include/asm/arm64/domain.h diff --git a/xen/arch/arm/include/asm/arm32/domain.h b/xen/arch/arm/include= /asm/arm32/domain.h new file mode 100644 index 000000000000..1bd0735c9194 --- /dev/null +++ b/xen/arch/arm/include/asm/arm32/domain.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ARM_ARM32_DOMAIN_H +#define ARM_ARM32_DOMAIN_H + +/* Arm32 always runs guests in AArch32 mode */ + +#define is_32bit_domain(d) ((void)(d), 1) +#define is_64bit_domain(d) ((void)(d), 0) + +#endif /* ARM_ARM32_DOMAIN_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/arm64/domain.h b/xen/arch/arm/include= /asm/arm64/domain.h new file mode 100644 index 000000000000..1a2d73950bf0 --- /dev/null +++ b/xen/arch/arm/include/asm/arm64/domain.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ARM_ARM64_DOMAIN_H +#define ARM_ARM64_DOMAIN_H + +/* + * Returns true if guest execution state is AArch32 + * + * @d: pointer to the domain structure + */ +#define is_32bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_32BIT) + +/* + * Returns true if guest execution state is AArch64 + * + * @d: pointer to the domain structure + */ +#define is_64bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_64BIT) + +#endif /* ARM_ARM64_DOMAIN_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index a3487ca71303..dde48178b857 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -22,11 +22,10 @@ enum domain_type { DOMAIN_32BIT, DOMAIN_64BIT, }; -#define is_32bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_32BIT) -#define is_64bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_64BIT) + +# include #else -#define is_32bit_domain(d) (1) -#define is_64bit_domain(d) (0) +# include #endif =20 /* --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Aug 06 09:49:49 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 09:49:49 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071504.1434944 (Exim 4.92) (envelope-from ) id 1ujamK-0008Vv-BH; Wed, 06 Aug 2025 09:49:48 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071504.1434944; Wed, 06 Aug 2025 09:49:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujamK-0008Uz-79; Wed, 06 Aug 2025 09:49:48 +0000 Received: by outflank-mailman (input) for mailman id 1071504; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fbadd1ef-f5f1-47a7-4e77-08ddd4ce914c X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2025 09:49:42.1969 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: MGnwP5F88CBAS6Z972ZECAd0wwzPAYVtJJk03tW0FozdTxCOcFkSOyo2HoU1sYehytsJOZVJBrkCpNri65Vl4ldYCSJd5X0vaHixnyh2FXk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR03MB10887 From: Grygorii Strashko Split set_domain_type() between Arm64/Arm32 sub-arches as set_domain_type() implementation is going to be extended for Arm64. Signed-off-by: Grygorii Strashko --- v2: - no changes, rebase xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/domain-build.c | 22 ++++++++++++++++++++++ xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/arm64/domain-build.c | 24 ++++++++++++++++++++++++ xen/arch/arm/dom0less-build.c | 14 -------------- xen/include/xen/dom0less-build.h | 8 ++++++++ 6 files changed, 56 insertions(+), 14 deletions(-) create mode 100644 xen/arch/arm/arm32/domain-build.c create mode 100644 xen/arch/arm/arm64/domain-build.c diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 531168f58a0a..0fd3f5272361 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -6,6 +6,7 @@ obj-y +=3D cache.o obj-$(CONFIG_EARLY_PRINTK) +=3D debug.o obj-y +=3D domctl.o obj-y +=3D domain.o +obj-y +=3D domain-build.o obj-y +=3D entry.o obj-y +=3D head.o obj-y +=3D insn.o diff --git a/xen/arch/arm/arm32/domain-build.c b/xen/arch/arm/arm32/domain-= build.c new file mode 100644 index 000000000000..e34261e4a2ad --- /dev/null +++ b/xen/arch/arm/arm32/domain-build.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +#ifdef CONFIG_DOM0LESS_BOOT +void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) +{ + /* Nothing to do */ +} +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 6491c5350b2e..3272fe7e4ca2 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) +=3D bpi.o obj-$(CONFIG_EARLY_PRINTK) +=3D debug.o obj-y +=3D domctl.o obj-y +=3D domain.o +obj-y +=3D domain-build.o obj-y +=3D entry.o obj-y +=3D head.o obj-y +=3D insn.o diff --git a/xen/arch/arm/arm64/domain-build.c b/xen/arch/arm/arm64/domain-= build.c new file mode 100644 index 000000000000..3a89ee46b8c6 --- /dev/null +++ b/xen/arch/arm/arm64/domain-build.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include + +#ifdef CONFIG_DOM0LESS_BOOT +/* TODO: make arch.type generic ? */ +void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) +{ + /* type must be set before allocate memory */ + d->arch.type =3D kinfo->arch.type; +} +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index c8d07213e247..58f77628df1f 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -236,20 +236,6 @@ int __init make_arch_nodes(struct kernel_info *kinfo) return 0; } =20 -/* TODO: make arch.type generic ? */ -#ifdef CONFIG_ARM_64 -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* type must be set before allocate memory */ - d->arch.type =3D kinfo->arch.type; -} -#else -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) -{ - /* Nothing to do */ -} -#endif - int __init init_vuart(struct domain *d, struct kernel_info *kinfo, const struct dt_device_node *node) { diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-bu= ild.h index 408859e3255a..3e81d8ba3a47 100644 --- a/xen/include/xen/dom0less-build.h +++ b/xen/include/xen/dom0less-build.h @@ -57,6 +57,14 @@ int init_vuart(struct domain *d, struct kernel_info *kin= fo, int make_intc_domU_node(struct kernel_info *kinfo); int make_arch_nodes(struct kernel_info *kinfo); =20 +/* + * Set domain type from struct kernel_info which defines guest Execution + * State 32-bit/64-bit (for Arm AArch32/AArch64). + * The domain type must be set before allocate_memory. + * + * @d: pointer to the domain structure. + * @kinfo: pointer to the kinfo structure. + */ void set_domain_type(struct domain *d, struct kernel_info *kinfo); =20 int init_intc_phandle(struct kernel_info *kinfo, const char *name, --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Aug 06 09:49:50 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 09:49:50 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071506.1434969 (Exim 4.92) (envelope-from ) id 1ujamM-0000fe-2H; Wed, 06 Aug 2025 09:49:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071506.1434969; Wed, 06 Aug 2025 09:49:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujamL-0000ew-Sl; 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Wed, 6 Aug 2025 09:49:44 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: afbf7411-72aa-11f0-a322-13f23c93f187 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=QFJY5SHTBQrN+rtdTMaTx7BnzPu4p3f96yxlw3fIPu4f11d+QeSdyUSOrn1lHXE1B3dv15v5uYBuLGt2ASwdTSpCZZQpybFVReqgnfpZHjp08ciMXow9crQ0WbN5UuINTOiEbNyTy7ROrKpxN3chSuZwmsUR4uyku7//l8etTudiJAqVD6wfzlGpwgfaPS3LTnRSLQqtdMZnTf3zUaDJ4AEtjq1pwg8R4FRX/tJgMAMu8bKbDYUx/cDpJ3OOFImG6Pk0MZmKq1/3af+NNN9EQalxgQpqMagssYuVFOcfGDFRoLStV0UlMp9qhbxOm6XfA13C4I/trauC/Y5fQexJ2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 91ebd3b0-afcf-4152-5a11-08ddd4ce925c X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2025 09:49:43.0249 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: YOlMbvS2ph2cE4aai3wRyOfLpAdt2fkoBV4m+aoR7VojMcnqw69q/JWYYHfNxbV+ZHWK2fjAe5R9ncha2MuZIOt73jdVUDKvDVAMwsuS3uU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR03MB10887 From: Grygorii Strashko Now Arm64 AArch32 guest support is always enabled and built-in while not all Arm64 platforms supports AArch32 (for exmaple on Armv9A) or this support might not be needed (Arm64 AArch32 is used quite rarely in embedded systems). More over, when focusing on safety certification, AArch32 related code in Xen leaves a gap in terms of coverage that cannot really be justified in words. This leaves two options: either support it (lots of additional testing, requirements and documents would be needed) or compile it out. Hence, this patch introduces basic support to allow make Arm64 AArch32 guest support optional. The following changes are introduced: - Introduce Kconfig option CONFIG_ARM64_AARCH32 to allow enable/disable Arm64 AArch32 guest support (default y) - Introduce is_aarch32_enabled() helper which accounts Arm64 HW capability and CONFIG_ARM64_AARCH32 setting - Introduce arm64_set_domain_type() to configure Arm64 domain type in unified way instead of open coding (d)->arch.type, and account CONFIG_ARM64_AARCH32 configuration. - toolstack: do not advertise "xen-3.0-armv7l " capability if AArch32 is disabled. - do not expose EL1 AArch32 support to guest in ID_AA64PFR0_EL1 reg if AArch32 is disabled. - Set Arm64 domain type to DOMAIN_64BIT by default. - the Arm Xen boot code is handling this case properly already; - for toolstack case the XEN_DOMCTL_set_address_size hypercall handling updated to forcibly configure domain type regardless of current domain type configuration, so toolstack behavior is unchanged. With CONFIG_ARM64_AARCH32=3Dn the Xen will reject AArch32 guests (kernels) = if configured by user in the following way: - Xen boot will fail with panic during dom0 or dom0less domains creation - toolstack domain creation will be rejected due to xc_dom_compat_check() failure. Making Arm64 AArch32 guest support open further possibilities for build optimizations of Arm64 AArch32 guest support code. Signed-off-by: Grygorii Strashko --- changes in v2: - use Arm64 "cpu_has_el1_32" in all places to check if HW has AArch32 suppo= rt - rework Arm64 XEN_DOMCTL_set_address_size hypercall handling to work with = any initial domain type set (32bit or 64 bit) - fix comments related to macro parameters evaluation issues - do not expose EL1 AArch32 support to guest in ID_AA64PFR0_EL1 reg if AArch32 is disabled xen/arch/arm/Kconfig | 7 ++++ xen/arch/arm/arm64/domain-build.c | 46 +++++++++++++++++++++++-- xen/arch/arm/arm64/domctl.c | 16 +++++---- xen/arch/arm/arm64/vsysreg.c | 9 +++++ xen/arch/arm/domain.c | 9 +++++ xen/arch/arm/domain_build.c | 21 +++-------- xen/arch/arm/include/asm/arm32/domain.h | 12 +++++++ xen/arch/arm/include/asm/arm64/domain.h | 23 +++++++++++++ xen/arch/arm/setup.c | 2 +- 9 files changed, 119 insertions(+), 26 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index a0c816047427..bf6dd73caf73 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -266,6 +266,13 @@ config PCI_PASSTHROUGH help This option enables PCI device passthrough =20 +config ARM64_AARCH32 + bool "AArch32 Guests support on on ARM64 (UNSUPPORTED)" if UNSUPPORTED + depends on ARM_64 + default y + help + This option enables AArch32 Guests on ARM64. + endmenu =20 menu "ARM errata workaround via the alternative framework" diff --git a/xen/arch/arm/arm64/domain-build.c b/xen/arch/arm/arm64/domain-= build.c index 3a89ee46b8c6..5951f002e3af 100644 --- a/xen/arch/arm/arm64/domain-build.c +++ b/xen/arch/arm/arm64/domain-build.c @@ -4,13 +4,55 @@ #include =20 #include +#include + +int __init arm64_set_domain_type(struct kernel_info *kinfo) +{ + struct domain *d =3D kinfo->bd.d; + enum domain_type type; + + ASSERT(d); + ASSERT(kinfo); + + type =3D kinfo->arch.type; + + if ( !is_aarch32_enabled() ) + { + ASSERT(d->arch.type =3D=3D DOMAIN_64BIT); + + if ( type =3D=3D DOMAIN_32BIT ) + { + const char *str =3D "not available"; + + if ( !IS_ENABLED(CONFIG_ARM64_AARCH32) ) + str =3D "disabled"; + printk("aarch32 guests support is %s\n", str); + return -EINVAL; + } + + return 0; + } + + if ( is_sve_domain(d) && type =3D=3D DOMAIN_32BIT ) + { + printk("SVE is not available for 32-bit domain\n"); + return -EINVAL; + } + + d->arch.type =3D type; + + return 0; +} =20 #ifdef CONFIG_DOM0LESS_BOOT /* TODO: make arch.type generic ? */ void __init set_domain_type(struct domain *d, struct kernel_info *kinfo) { - /* type must be set before allocate memory */ - d->arch.type =3D kinfo->arch.type; + int rc; + + rc =3D arm64_set_domain_type(kinfo); + if ( rc < 0 ) + panic("Unsupported guest type\n"); } #endif =20 diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c index 8720d126c97d..4f0f143daef8 100644 --- a/xen/arch/arm/arm64/domctl.c +++ b/xen/arch/arm/arm64/domctl.c @@ -13,6 +13,11 @@ #include #include =20 +static void vcpu_switch_to_aarch32_mode(struct vcpu *v) +{ + v->arch.hcr_el2 &=3D ~HCR_RW; +} + static long switch_mode(struct domain *d, enum domain_type type) { struct vcpu *v; @@ -21,14 +26,14 @@ static long switch_mode(struct domain *d, enum domain_t= ype type) return -EINVAL; if ( domain_tot_pages(d) !=3D 0 ) return -EBUSY; - if ( d->arch.type =3D=3D type ) - return 0; =20 d->arch.type =3D type; =20 - if ( is_64bit_domain(d) ) - for_each_vcpu(d, v) + for_each_vcpu(d, v) + if ( is_64bit_domain(d) ) vcpu_switch_to_aarch64_mode(v); + else + vcpu_switch_to_aarch32_mode(v); =20 return 0; } @@ -38,7 +43,7 @@ static long set_address_size(struct domain *d, uint32_t a= ddress_size) switch ( address_size ) { case 32: - if ( !cpu_has_el1_32 ) + if ( !is_aarch32_enabled() ) return -EINVAL; /* SVE is not supported for 32 bit domain */ if ( is_sve_domain(d) ) @@ -58,7 +63,6 @@ long subarch_do_domctl(struct xen_domctl *domctl, struct = domain *d, { case XEN_DOMCTL_set_address_size: return set_address_size(d, domctl->u.address_size.size); - default: return -ENOSYS; } diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index d14258290ff0..9f7e735c9b74 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -330,6 +330,15 @@ void do_sysreg(struct cpu_user_regs *regs, { register_t guest_reg_value =3D domain_cpuinfo.pfr64.bits[0]; =20 + if ( !is_aarch32_enabled() ) + { + /* do not expose EL1 AArch32 support if disabled */ + register_t mask =3D GENMASK(ID_AA64PFR0_EL1_SHIFT + 4 - 1, + ID_AA64PFR0_EL1_SHIFT); + guest_reg_value &=3D ~mask; + guest_reg_value |=3D (1 << ID_AA64PFR0_EL1_SHIFT) & mask; + } + if ( is_sve_domain(v->domain) ) { /* 4 is the SVE field width in id_aa64pfr0_el1 */ diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 310c5789096d..544d1422a793 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -791,6 +791,15 @@ int arch_domain_create(struct domain *d, d->arch.sve_vl =3D config->arch.sve_vl; #endif =20 +#ifdef CONFIG_ARM_64 + /* + * Set default Execution State to AArch64 (64bit) + * - Xen will reconfigure it properly at boot time + * - toolstack will reconfigure it properly by XEN_DOMCTL_set_address_= size + */ + d->arch.type =3D DOMAIN_64BIT; +#endif + return 0; =20 fail: diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 47ba920fc6b0..c616127e8da5 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1873,19 +1873,6 @@ int __init construct_domain(struct domain *d, struct= kernel_info *kinfo) BUG_ON(v->is_initialised); =20 #ifdef CONFIG_ARM_64 - /* if aarch32 mode is not supported at EL1 do not allow 32-bit domain = */ - if ( !(cpu_has_el1_32) && kinfo->arch.type =3D=3D DOMAIN_32BIT ) - { - printk("Platform does not support 32-bit domain\n"); - return -EINVAL; - } - - if ( is_sve_domain(d) && (kinfo->arch.type =3D=3D DOMAIN_32BIT) ) - { - printk("SVE is not available for 32-bit domain\n"); - return -EINVAL; - } - if ( is_64bit_domain(d) ) vcpu_switch_to_aarch64_mode(v); =20 @@ -1983,6 +1970,10 @@ static int __init construct_dom0(struct domain *d) if ( rc < 0 ) return rc; =20 + rc =3D arm64_set_domain_type(&kinfo); + if ( rc < 0 ) + return rc; + return construct_hwdom(&kinfo, NULL); } =20 @@ -1994,10 +1985,6 @@ int __init construct_hwdom(struct kernel_info *kinfo= , =20 iommu_hwdom_init(d); =20 -#ifdef CONFIG_ARM_64 - /* type must be set before allocate_memory */ - d->arch.type =3D kinfo->arch.type; -#endif find_gnttab_region(d, kinfo); if ( is_domain_direct_mapped(d) ) allocate_memory_11(d, kinfo); diff --git a/xen/arch/arm/include/asm/arm32/domain.h b/xen/arch/arm/include= /asm/arm32/domain.h index 1bd0735c9194..30e8818ff2ae 100644 --- a/xen/arch/arm/include/asm/arm32/domain.h +++ b/xen/arch/arm/include/asm/arm32/domain.h @@ -3,11 +3,23 @@ #ifndef ARM_ARM32_DOMAIN_H #define ARM_ARM32_DOMAIN_H =20 +struct kernel_info; + /* Arm32 always runs guests in AArch32 mode */ =20 #define is_32bit_domain(d) ((void)(d), 1) #define is_64bit_domain(d) ((void)(d), 0) =20 +static inline bool is_aarch32_enabled(void) +{ + return true; +} + +static inline int arm64_set_domain_type(struct kernel_info *kinfo) +{ + return 0; +} + #endif /* ARM_ARM32_DOMAIN_H */ =20 /* diff --git a/xen/arch/arm/include/asm/arm64/domain.h b/xen/arch/arm/include= /asm/arm64/domain.h index 1a2d73950bf0..bebcbc582f97 100644 --- a/xen/arch/arm/include/asm/arm64/domain.h +++ b/xen/arch/arm/include/asm/arm64/domain.h @@ -3,6 +3,10 @@ #ifndef ARM_ARM64_DOMAIN_H #define ARM_ARM64_DOMAIN_H =20 +#include + +struct kernel_info; + /* * Returns true if guest execution state is AArch32 * @@ -17,6 +21,25 @@ */ #define is_64bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_64BIT) =20 +/* + * Arm64 declares AArch32 (32bit) Execution State support in the + * Processor Feature Registers (PFR0), but also can be disabled manually. + */ +static inline bool is_aarch32_enabled(void) +{ + return IS_ENABLED(CONFIG_ARM64_AARCH32) && cpu_has_el1_32; +} + +/* + * Set domain type from struct kernel_info which defines guest Execution + * State AArch32/AArch64 during regular dom0 or predefined (dom0less) + * domains creation . + * Type must be set before allocate_memory or create vcpus. + * + * @kinfo: pointer to the kinfo structure. + */ +int arm64_set_domain_type(struct kernel_info *kinfo); + #endif /* ARM_ARM64_DOMAIN_H */ =20 /* diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index bb35afe56cec..c29573f0ffec 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -530,7 +530,7 @@ static int __init init_xen_cap_info(void) #ifdef CONFIG_ARM_64 safe_strcat(xen_cap_info, "xen-3.0-aarch64 "); #endif - if ( cpu_has_aarch32 ) + if ( is_aarch32_enabled() ) safe_strcat(xen_cap_info, "xen-3.0-armv7l "); =20 return 0; --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Aug 06 09:49:51 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 09:49:51 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071507.1434979 (Exim 4.92) (envelope-from ) id 1ujamN-0000y0-Ei; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: epam.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AS2PR03MB8907.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: af9560bb-b8c0-42cd-379f-08ddd4ce928d X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2025 09:49:43.3659 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b41b72d0-4e9f-4c26-8a69-f949f367c91d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: iQYCecNOL7gKww2YDeHXnPElgz/ZFMitLExzchWKDuEfVrqJck8bq0cn7UOWKN99hgktIbvCTWxb0wkC+8c5r9Ot25LlGH4AXg1erKBwe70= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4PR03MB10887 From: Grygorii Strashko Constify is_32/64bit_domain() macro for the case CONFIG_ARM64_AARCH32=3Dn a= nd so allow compiler to opt out Aarch32 specific code. Before (CONFIG_ARM64_AARCH32=3Dy): text data bss dec hex filename 859212 322404 270880 1452496 1629d0 xen-syms-before After (CONFIG_ARM64_AARCH32=3Dn): text data bss dec hex filename 851256 322404 270880 1444540 160abc xen-syms-after Signed-off-by: Grygorii Strashko --- v2: - use IS_ENABLED(CONFIG_ARM64_AARCH32) instead of ifdefs xen/arch/arm/include/asm/arm64/domain.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/include/asm/arm64/domain.h b/xen/arch/arm/include= /asm/arm64/domain.h index bebcbc582f97..70dfbeac7443 100644 --- a/xen/arch/arm/include/asm/arm64/domain.h +++ b/xen/arch/arm/include/asm/arm64/domain.h @@ -12,14 +12,16 @@ struct kernel_info; * * @d: pointer to the domain structure */ -#define is_32bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_32BIT) +#define is_32bit_domain(d) = \ + (IS_ENABLED(CONFIG_ARM64_AARCH32) && (d)->arch.type =3D=3D DOMAIN_= 32BIT) =20 /* * Returns true if guest execution state is AArch64 * * @d: pointer to the domain structure */ -#define is_64bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_64BIT) +#define is_64bit_domain(d) = \ + (!IS_ENABLED(CONFIG_ARM64_AARCH32) || (d)->arch.type =3D=3D DOMAIN= _64BIT) =20 /* * Arm64 declares AArch32 (32bit) Execution State support in the --=20 2.34.1 From xen-devel-bounces@lists.xenproject.org Wed Aug 06 10:24:09 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 10:24:09 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071564.1434988 (Exim 4.92) (envelope-from ) id 1ujbJT-0008Q9-VY; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="COT8wTur3wgaNPW/" Content-Disposition: inline --COT8wTur3wgaNPW/ Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 6 Aug 2025 12:23:56 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: xen-devel Cc: Andrew Cooper Subject: S3 regression related to XSA-471 patches Hi, We've got several reports that S3 reliability recently regressed. We identified it's definitely related to XSA-471 patches, and bisection points at "x86/idle: Remove broken MWAIT implementation". I don't have reliable reproduction steps, so I'm not 100% sure if it's really this patch, or maybe an earlier one - but it's definitely already broken at this point in the series. Most reports are about Xen 4.17 (as that's what stable Qubes OS version currently use), but I think I've seen somebody reporting the issue on 4.19 too (but I don't have clear evidence, especially if it's the same issue). The problem manifests in system freezing on S3 resume. Sometimes it manages to show the screenlocker password prompt, and sometimes one can interact with it for a second or two. But then it freezes, mouse stops moving etc (but no reboot). One time I managed to get pass the screenlocker and interact with dom0 for a few minutes before it frozen. Resuming domUs didn't happen (the qubes-specific script doing so resume hanged), and also no logs persisted on the disk from this case (on disk it looked like it never resumed). Generally it looked like some CPUs were stuck. It appears to be more likely to hit the issue if some domUs are active at the suspend/resume time. While Qubes OS does suspend (not just pause) them for the host S3 time, some activity before/after does appear to matter. My test case that has ~30-40% reproduction rate involves several firefox instances playing youtube videos. I've talked with Andrew about it a bit, with not much conclusions. Initial reports mentioned only MTL and RPL systems, so we focused on something related to weird topology. But just today I've got a report of the same happening on KBL too... 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Wed, 06 Aug 2025 03:25:52 -0700 (PDT) Message-ID: <18c28180-c0ff-4b54-a964-e8ab753014ea@suse.com> Date: Wed, 6 Aug 2025 12:25:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 8/8] x86/mm: adjust loop in arch_init_memory() to iterate over the PDX space From: Jan Beulich To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= Cc: Andrew Cooper , xen-devel@lists.xenproject.org References: <20250805095257.74975-1-roger.pau@citrix.com> <20250805095257.74975-9-roger.pau@citrix.com> <31691bf7-94bf-4f73-b04c-a32f86bb0e37@suse.com> <68da529e-7fd7-4ca5-b6ef-4c1f95423246@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <68da529e-7fd7-4ca5-b6ef-4c1f95423246@suse.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 06.08.2025 10:11, Jan Beulich wrote: > On 05.08.2025 17:27, Roger Pau Monné wrote: >> On Tue, Aug 05, 2025 at 02:38:38PM +0200, Jan Beulich wrote: >>> On 05.08.2025 11:52, Roger Pau Monne wrote: >>>> --- a/xen/arch/x86/mm.c >>>> +++ b/xen/arch/x86/mm.c >>>> @@ -275,7 +275,7 @@ static void __init assign_io_page(struct page_info *page) >>>> >>>> void __init arch_init_memory(void) >>>> { >>>> - unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn; >>>> + unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn, pdx; >>>> >>>> /* >>>> * Basic guest-accessible flags: >>>> @@ -328,9 +328,20 @@ void __init arch_init_memory(void) >>>> destroy_xen_mappings((unsigned long)mfn_to_virt(iostart_pfn), >>>> (unsigned long)mfn_to_virt(ioend_pfn)); >>>> >>>> - /* Mark as I/O up to next RAM region. */ >>>> - for ( ; pfn < rstart_pfn; pfn++ ) >>>> + /* >>>> + * Mark as I/O up to next RAM region. Iterate over the PDX space to >>>> + * skip holes which would always fail the mfn_valid() check. >>>> + * >>>> + * pfn_to_pdx() requires a valid (iow: RAM) PFN to convert to PDX, >>>> + * hence provide pfn - 1, which is the tailing PFN from the last RAM >>>> + * range, or pdx 0 if the input pfn is 0. >>>> + */ >>>> + for ( pdx = pfn ? pfn_to_pdx(pfn - 1) + 1 : 0; >>>> + pdx < pfn_to_pdx(rstart_pfn); >>>> + pdx++ ) >>>> { >>>> + pfn = pdx_to_pfn(pdx); >>>> + >>>> if ( !mfn_valid(_mfn(pfn)) ) >>>> continue; >>>> >>> >>> As much as I would have liked to ack this, I fear there's another caveat here: >>> At the top of the loop we check not only for RAM, but also for UNUSABLE. The >>> latter, like RAM, shouldn't be marked I/O, but we also can't use PFN <-> PDX >>> transformations on any such page. >> >> Right you are. I'm not sure however why we do this - won't we want >> the mappings of UNUSABLE regions also be removed from the Xen >> page-tables? (but not marked as IO) > > Yes, I think this is a flaw in current code. Perhaps it was (wrongly) assumed > that no UNUSABLE regions would ever exist this low in a memory map? Imo we want > to deal with this in two steps - first sort the UNUSABLE issue, then improve > the dealing with what is passed to assign_io_page(). > > While there we may also want to find a way to tie together the 16Mb boundary > checks - the 16UL isn't properly connected to the BOOTSTRAP_MAP_BASE definition > in setup.c. Yet then: Am I overlooking something, or is the 16Mb boundary not > really special anymore? I.e. could e.g. BOOTSTRAP_MAP_BASE perhaps be moved (at > least in principle), either almost arbitrarily up (within the low 4Gb), or down > as much as to the 2Mb boundary? The relevant aspect here would be that the > comment saying "the statically-initialised 1-16MB mapping area" looks to be > stale, as of 7cd7f2f5e116 ("x86/boot: Remove the preconstructed low 16M > superpage mappings"). If there are excess mappings to worry about, those may > nowadays well live above the 16Mb boundary (because of it being 2Mb mappings > that head.S inserts into l2_directmap[]). Hmm, extending this to beyond 16M collides with mappings done by acpi_dmar_init(), erst_init(), and acpi_hest_init(). Luckily efi_init_memory() runs only afterwards. While I guess I could limit this to the space 2M mappings were done for in head.S, theoretically there could still be a collision afterwards. So I think we need to either somehow exclude such mappings (might end up fragile), or stop (ab)using the directmap there. Thoughts? Jan From xen-devel-bounces@lists.xenproject.org Wed Aug 06 10:37:15 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 10:37:15 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071582.1435008 (Exim 4.92) (envelope-from ) id 1ujbW3-0002NI-9c; Wed, 06 Aug 2025 10:37:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071582.1435008; Wed, 06 Aug 2025 10:37:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujbW3-0002NB-6T; Wed, 06 Aug 2025 10:37:03 +0000 Received: by outflank-mailman (input) for mailman id 1071582; Wed, 06 Aug 2025 10:37:02 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujbW2-0002N5-8n for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 10:37:02 +0000 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [2a00:1450:4864:20::530]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 47669c7a-72b1-11f0-b898-0df219b8e170; Wed, 06 Aug 2025 12:36:58 +0200 (CEST) Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-61592ff5df8so8465758a12.1 for ; Wed, 06 Aug 2025 03:36:58 -0700 (PDT) Received: from [10.156.60.236] (ip-037-024-206-209.um08.pools.vodafone-ip.de. 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Wed, 06 Aug 2025 03:36:57 -0700 (PDT) Message-ID: Date: Wed, 6 Aug 2025 12:36:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: S3 regression related to XSA-471 patches To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= Cc: Andrew Cooper , xen-devel References: Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 06.08.2025 12:23, Marek Marczykowski-Górecki wrote: > We've got several reports that S3 reliability recently regressed. We > identified it's definitely related to XSA-471 patches, and bisection > points at "x86/idle: Remove broken MWAIT implementation". I don't have > reliable reproduction steps, so I'm not 100% sure if it's really this > patch, or maybe an earlier one - but it's definitely already broken at > this point in the series. Most reports are about Xen 4.17 (as that's > what stable Qubes OS version currently use), but I think I've seen > somebody reporting the issue on 4.19 too (but I don't have clear > evidence, especially if it's the same issue). At the time we've been discussing the explicit raising of TIMER_SOFTIRQ in mwait_idle_with_hints() a lot. If it was now truly missing, that imo shouldn't cause problems only after resume, but then it may have covered for some omission during resume. As a far-fetched experiment, could you try putting that back (including the calculation of the "expires" local variable)? Jan From xen-devel-bounces@lists.xenproject.org Wed Aug 06 10:46:48 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 10:46:48 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071599.1435019 (Exim 4.92) (envelope-from ) id 1ujbfQ-0004EM-5b; Wed, 06 Aug 2025 10:46:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071599.1435019; Wed, 06 Aug 2025 10:46:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujbfQ-0004EF-1K; Wed, 06 Aug 2025 10:46:44 +0000 Received: by outflank-mailman (input) for mailman id 1071599; Wed, 06 Aug 2025 10:46:43 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujbfP-0004E9-3v for xen-devel@lists.xenproject.org; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="napIOcvaMj7fpBqC" Content-Disposition: inline In-Reply-To: --napIOcvaMj7fpBqC Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Wed, 6 Aug 2025 12:46:36 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Jan Beulich Cc: Andrew Cooper , xen-devel Subject: Re: S3 regression related to XSA-471 patches On Wed, Aug 06, 2025 at 12:36:56PM +0200, Jan Beulich wrote: > On 06.08.2025 12:23, Marek Marczykowski-G=C3=B3recki wrote: > > We've got several reports that S3 reliability recently regressed. We > > identified it's definitely related to XSA-471 patches, and bisection > > points at "x86/idle: Remove broken MWAIT implementation". I don't have > > reliable reproduction steps, so I'm not 100% sure if it's really this > > patch, or maybe an earlier one - but it's definitely already broken at > > this point in the series. Most reports are about Xen 4.17 (as that's > > what stable Qubes OS version currently use), but I think I've seen > > somebody reporting the issue on 4.19 too (but I don't have clear > > evidence, especially if it's the same issue). >=20 > At the time we've been discussing the explicit raising of TIMER_SOFTIRQ > in mwait_idle_with_hints() a lot. If it was now truly missing, that imo > shouldn't cause problems only after resume, but then it may have covered > for some omission during resume. As a far-fetched experiment, could you > try putting that back (including the calculation of the "expires" local > variable)? Sure, I'll try. --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --napIOcvaMj7fpBqC Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmiTMowACgkQ24/THMrX 1yyz/gf/TAjjh3F2m+hJHergkwX4ZwPtXu33CoPXWPENb6t2wXDgEVOP4K6tN4j9 5/hwE0lDaFiHFTYr/lWGY2dcV8Z60lJCYv+Pg1NYu25VhE5yyByanBEnftmwiJs1 nDJ711I9gG82uqdzDlMh6jzx4C5EtgEyYJISLwQ9B5hsKgmfQ2zCsMF3jaqna5QJ zJTx0tbR4JWkkNvlj0R0a6LPFUYrPiIBlnC3c0MBYs27ZAu8X7ZXZk0mkLoBd+W1 Z0FOqKvgCorTkdgigbfLab7NgY3W3r2ORuXbD+adim964UzkH3CFlm9c6GvYifla RblTFxvVKcL3KHB7zmO6mYHgwyWVeg== =sbTY -----END PGP SIGNATURE----- --napIOcvaMj7fpBqC-- From xen-devel-bounces@lists.xenproject.org Wed Aug 06 10:48:02 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 10:48:02 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071606.1435029 (Exim 4.92) (envelope-from ) id 1ujbge-0004iU-D9; Wed, 06 Aug 2025 10:48:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071606.1435029; Wed, 06 Aug 2025 10:48:00 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujbge-0004iN-AY; Wed, 06 Aug 2025 10:48:00 +0000 Received: by outflank-mailman (input) for mailman id 1071606; Wed, 06 Aug 2025 10:47:59 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujbgc-0004iF-VI for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 10:47:58 +0000 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [2a00:1450:4864:20::330]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d07636c4-72b2-11f0-a322-13f23c93f187; Wed, 06 Aug 2025 12:47:57 +0200 (CEST) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-458b49c98a7so31729745e9.1 for ; Wed, 06 Aug 2025 03:47:58 -0700 (PDT) Received: from localhost (112.pool92-178-7.dynamic.orange.es. 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(that's from _ns16550_resume()). Thanks, Roger. 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That would > >>>> want reflecting by a tag then. > >>> > >>> Yes, indeed. > >>> > >>>> > >>>> Also, what's the real problem you want to solve here? The timer function > >>>> would be run one more time after ->intr_works is set, and then the timer > >>>> will be permanently inactive (up to a possible S3 resume). Is it being on > >>>> an inactive list an actual problem? (IOW I'd like to understand if the > >>>> change is merely cosmetic, or if there is some actual benefit.) > >>> > >>> My understanding is running polling timer one more time after the interrupts > >>> are enabled is the issue: if there's a pending timer when it is known the > >>> timer not needed, then the timer should be canceled. > >> > >> And the effort of canceling outweighs the one extra running of the timer? > > > > I think so, because intr_works will not flip at run-time once set. > > If so, no need to keep the timer ready to be rearmed. > > Well, to me it looks like a code size increase with extremely limited benefit. > Hence while likely I wouldn't outright NAK such a change, I also wouldn't ACK > it. Hm, indeed the net win of this is dubious, as the extra polling interrupt would only happen once. Using stop_timer() would be less heavyweight than kill_timer(). Overall I think it needs justification in the commit message, as the timer cannot be removed from the list of timers, otherwise it's usage on resume from suspension will trigger an ASSERT, so part of the commit message is stale. Thanks, Roger. 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It's unclear whether we would like to dynamically change those values in the future. Given the current usage they would better be const. > + > /* > * printk rate limiting, lifted from Linux. > * > * This enforces a rate limit: not more than one kernel message > * every printk_ratelimit_ms (millisecs). > */ > -int __printk_ratelimit(int ratelimit_ms, int ratelimit_burst) > +int printk_ratelimit(void) As suggested by Jan, I would just make this static and remove the prototype from lib.h. That results in less changes, and allows to more easily export the fine grained function in the future if we had a need to. Thanks, Roger. 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boundary="_000_FR6P281MB3484EDA4C66DFB8C1F9A26FEB82DAFR6P281MB3484DEUP_" MIME-Version: 1.0 X-OriginatorOrg: daimlertruck.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: FR6P281MB3484.DEUP281.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: aec31e4a-8a57-434d-f8af-08ddd4dbde68 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2025 11:24:55.0687 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 505cca53-5750-4134-9501-8d52d5df3cd1 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Bpvai/yfG22N3ITY2Jl45BZ8HGy4qMCeTlG9dBoSVZ44Ru8lLkFhiKBqjTbphGxO9K6isNSXNUGcBnWsc2UN1g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BEXP281MB0213 --_000_FR6P281MB3484EDA4C66DFB8C1F9A26FEB82DAFR6P281MB3484DEUP_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Volodymyr, I'm currently working with the R-Car H3e board and exploring Xen virtualiza= tion on this platform. While I've found resources related to dom0 and domU = configurations, I'm specifically looking for guidance on building and launc= hing a full-fledged Linux VM on Xen-beyond the domd setup. Are there any official or community-maintained guides or examples tailored = for ARM-based platforms like the R-Car H3e that walk through setting up a s= tandalone Linux VM with full capabilities (networking, storage, graphical i= nterface, etc.)? Any help or direction would be greatly appreciated. Best regards, John Preetham If you are not the addressee, please inform us immediately that you have re= ceived this e-mail by mistake, and delete it. We thank you for your support= . --_000_FR6P281MB3484EDA4C66DFB8C1F9A26FEB82DAFR6P281MB3484DEUP_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

    Hi Volodymyr,

     

    I’m currently working with the R-Car H3e board= and exploring Xen virtualization on this platform. While I’ve found = resources related to dom0 and domU configurations, I’m specifically l= ooking for guidance on building and launching a full-fledged Linux VM on Xen—beyond the domd setup.

     

    Are there any official or community-maintained guide= s or examples tailored for ARM-based platforms like the R-Car H3e that walk= through setting up a standalone Linux VM with full capabilities (networkin= g, storage, graphical interface, etc.)?

     

    Any help or direction would be greatly appreciated.<= o:p>

     

    Best regards, 

    John Preetham

     

    <= br> If you are not the addressee, please inform us immediately that you have re= ceived this e-mail by mistake, and delete it. We thank you for your support= .

    --_000_FR6P281MB3484EDA4C66DFB8C1F9A26FEB82DAFR6P281MB3484DEUP_-- From xen-devel-bounces@lists.xenproject.org Wed Aug 06 11:33:43 2025 Return-path: Envelope-to: archives@lists.xen.org Delivery-date: Wed, 06 Aug 2025 11:33:43 +0000 Received: from list by lists.xenproject.org with outflank-mailman.1071651.1435069 (Exim 4.92) (envelope-from ) id 1ujcOo-0004yN-F9; Wed, 06 Aug 2025 11:33:38 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 1071651.1435069; Wed, 06 Aug 2025 11:33:38 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujcOo-0004yG-CE; Wed, 06 Aug 2025 11:33:38 +0000 Received: by outflank-mailman (input) for mailman id 1071651; Wed, 06 Aug 2025 11:33:37 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1ujcOm-0004y9-MI for xen-devel@lists.xenproject.org; Wed, 06 Aug 2025 11:33:36 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 2faf35e9-72b9-11f0-b898-0df219b8e170; Wed, 06 Aug 2025 13:33:34 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-af925cbd73aso1104812466b.1 for ; Wed, 06 Aug 2025 04:33:34 -0700 (PDT) Received: from [192.168.1.5] (user-109-243-64-38.play-internet.pl. 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In the current implementation VMIDs are >> introduced to reduce the number of TLB flushes. Each time the guest's >> virtual address space changes, > virtual? I assumed that originally it meant that from Xen point of view it could be called guest's virtual as guest doesn't really work with real physical address, but it seems like it would be more clear to use guest-physical as you suggested below. >> instead of flushing the TLB, a new VMID is >> assigned. This reduces the number of TLB flushes to at most 1/#VMIDs. >> The biggest advantage is that hot parts of the hypervisor's code and data >> retain in the TLB. >> >> VMIDs are a hart-local resource. As preemption of VMIDs is not possible, >> VMIDs are assigned in a round-robin scheme. To minimize the overhead of >> VMID invalidation, at the time of a TLB flush, VMIDs are tagged with a >> 64-bit generation. Only on a generation overflow the code needs to >> invalidate all VMID information stored at the VCPUs with are run on the >> specific physical processor. This overflow appears after about 2^80 >> host processor cycles, > Where's this number coming from? (If you provide numbers, I think they will > want to be "reproducible" by the reader. Which I fear isn't the case here.) The 2^80 cycles (based on x86-related numbers) result from: 1. And VM-Entry/-Exit cycle takes at least 1800 cycles (approximated by 2^10) 2. We have 64 ASIDs (2^6) 3. 2^64 generations. I removed this part of the comment earlier because I assumed that the first item is quite CPU-dependent, even for x86, let alone for other architectures, which may have a different number (?). However, this part of the comment was reintroduced during one of the merges. >> @@ -148,6 +149,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, >> >> console_init_postirq(); >> >> + vmid_init(); > This lives here only temporarily, I assume? Every hart will need to execute > it, and hence (like we have it on x86) this may want to be a central place > elsewhere. I haven’t checked how it is done on x86; I probably should. I planned to call it for each hart separately during secondary hart bring-up, since accessing the|hgatp| register of a hart is required to detect|VMIDLEN|. Therefore,|vmid_init()| should be called for secondary harts when their initialization code starts executing. >> --- /dev/null >> +++ b/xen/arch/riscv/vmid.c >> @@ -0,0 +1,165 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include >> +#include >> +#include >> + >> +/* Xen command-line option to enable VMIDs */ >> +static bool __read_mostly opt_vmid_enabled = true; > __ro_after_init ? Agree, __ro_afer_init would be better. >> +boolean_param("vmid", opt_vmid_enabled); >> + >> +/* >> + * VMIDs partition the physical TLB. In the current implementation VMIDs are >> + * introduced to reduce the number of TLB flushes. Each time the guest's >> + * virtual address space changes, instead of flushing the TLB, a new VMID is > The same odd "virtual" again? All the code here is about guest-physical, isn't > it? Answered above. >> + * assigned. This reduces the number of TLB flushes to at most 1/#VMIDs. >> + * The biggest advantage is that hot parts of the hypervisor's code and data >> + * retain in the TLB. >> + * >> + * Sketch of the Implementation: >> + * >> + * VMIDs are a hart-local resource. As preemption of VMIDs is not possible, >> + * VMIDs are assigned in a round-robin scheme. To minimize the overhead of >> + * VMID invalidation, at the time of a TLB flush, VMIDs are tagged with a >> + * 64-bit generation. Only on a generation overflow the code needs to >> + * invalidate all VMID information stored at the VCPUs with are run on the >> + * specific physical processor. This overflow appears after about 2^80 > And the same interesting number again. Answered above. >> + * host processor cycles, so we do not optimize this case, but simply disable >> + * VMID useage to retain correctness. >> + */ >> + >> +/* Per-Hart VMID management. */ >> +struct vmid_data { >> + uint64_t hart_vmid_generation; > Any reason not to simply use "generation"? No specific reason for that, it could be renamed to "generation". >> + uint16_t next_vmid; >> + uint16_t max_vmid; >> + bool disabled; >> +}; >> + >> +static DEFINE_PER_CPU(struct vmid_data, vmid_data); >> + >> +static unsigned long vmidlen_detect(void) > __init ? Or wait, are you (deliberately) permitting different VMIDLEN > across harts? All what I was able in RISC-V spec is that: The number of VMID bits is UNSPECIFIED and may be zero. The number of implemented VMID bits, termed VMIDLEN, may be determined by writing one to every bit position in the VMID field, then reading back the value in hgatp to see which bit positions in the VMID field hold a one. The least- significant bits of VMID are implemented first: that is, if VMIDLEN > 0, VMID[VMIDLEN-1:0] is writable. The maximal value of VMIDLEN, termed VMIDMAX, is 7 for Sv32x4 or 14 for Sv39x4, Sv48x4, and Sv57x4.. And I couldn't find explicitly that VMIDLEN will be the same across harts. Therefore, IMO, while the specification doesn't guarantee VMID will be different, the "unspecified" nature and the per-hart discovery mechanism of VMIDLEN in the hgatp CSR allows for VMIDLEN to be different on different harts in an implementation without violating the RISC-V privileged specification. > >> +{ >> + unsigned long vmid_bits; > Why "long" (also for the function return type)? Because csr_read() returns unsigned long as HGATP register has 'unsigned long' length. But it could be done in this way: csr_write(CSR_HGATP, old | HGATP_VMID_MASK); vmid_bits = MASK_EXTR(csr_read(CSR_HGATP), HGATP_VMID_MASK); vmid_bits = ffs_g(vmid_bits); csr_write(CSR_HGATP, old); And then use uint16_t for vmid_bits and use uin16_t as a return type. > >> + unsigned long old; >> + >> + /* Figure-out number of VMID bits in HW */ >> + old = csr_read(CSR_HGATP); >> + >> + csr_write(CSR_HGATP, old | HGATP_VMID_MASK); >> + vmid_bits = csr_read(CSR_HGATP); >> + vmid_bits = MASK_EXTR(vmid_bits, HGATP_VMID_MASK); > Nit: Stray blank. > >> + vmid_bits = flsl(vmid_bits); >> + csr_write(CSR_HGATP, old); >> + >> + /* >> + * We polluted local TLB so flush all guest TLB as >> + * a speculative access can happen at any time. >> + */ >> + local_hfence_gvma_all(); > There's no guest running. If you wrote hgat.MODE as zero, as per my > understanding now new TLB entries could even purely theoretically appear. It could be an issue (or, at least, it is recommended) when hgatp.MODE is changed: If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0 (and rs2 set to either x0 or the VMID) must be executed to order subsequent guest translations with the MODE change—even if the old MODE or new MODE is Bare. On other hand it is guaranteed that, at least, on Reset (and so I assume for power on) that: If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE fields are reset to 0. So it seems like if no guest is ran then there is no need even to write hgatp.MODE as zero, but it might be sense to do that explicitly just to be sure. I thought it was possible to have a running guest and perform a CPU hotplug. In that case, I expect that during the hotplug,|vmidlen_detect()| will be called and return the|vmid_bits| value, which is used as the active VMID. At that moment, the local TLB could be speculatively polluted, I think. Likely, it makes sense to call vmidlen_detect() only once for each hart during initial bringup. > In fact, with no guest running (yet) I'm having a hard time seeing why > you shouldn't be able to simply write the register with just > HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable > whether "old" needs restoring; writing plain zero afterwards ought to > suffice. You're in charcge of the register, after all. It make sense (but I don't know if it is a possible case) to be sure that HGATP.MODE remains the same, so there is no need to have TLB flush. If HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned above. If we agreed to keep local_hfence_gvma_all() then I think it isn't really any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK. Generally if 'old' is guaranteed to be zero (and, probably, it makes sense to check that in vmidlen_detect() and panic if it isn't zero) and if vmidlen_detect() function will be called before any guest domain(s) will be ran then I could agree that we don't need local_hfence_gvma_all() here. As an option we can do local_hfence_gvma_all() only if 'old' value wasn't set to zero. Does it make sense? > >> + return vmid_bits; >> +} >> + >> +void vmid_init(void) >> +{ >> + static bool g_disabled = false; >> + unsigned long vmid_len = vmidlen_detect(); >> + struct vmid_data *data = &this_cpu(vmid_data); >> + unsigned long max_availalbe_bits = sizeof(data->max_vmid) << 3; > Nit: Typo in "available". Also now that we have it, better use > BITS_PER_BYTE here? Sure, I will use BITS_PER_BYTE. > >> + if ( vmid_len > max_availalbe_bits ) >> + panic("%s: VMIDLEN is bigger then a type which represent VMID: %lu(%lu)\n", >> + __func__, vmid_len, max_availalbe_bits); > This shouldn't be a runtime check imo. What you want to check (at build > time) is that the bits set in HGATP_VMID_MASK can be held in ->max_vmid. Oh, I just noticed that this check isn't even really correct because of data->max_vmid is inited after this check. Anyway, build time check would be better. > >> + data->max_vmid = BIT(vmid_len, U) - 1; >> + data->disabled = !opt_vmid_enabled || (vmid_len <= 1); > Actually, what exactly does it mean that "VMIDs are disabled"? There's > no enable bit that I could find anywhere. Isn't it rather that in this > case you need to arrange to flush always on VM entry (or always after a > P2M change, depending how the TLB is split between guest and host use)? "VMIDs are disabled" here means that TLB flush will happen each time p2m is changed. > If you look at vmx_vmenter_helper(), its flipping of > SECONDARY_EXEC_ENABLE_VPID tweaks CPU behavior, such that the flush > would be implicit (when the bit is off). I don't expect RISC-V has any > such "implicit" flushing behavior? RISC-V relies on explicit software-managed fence instructions for TLB flushing. It seems like vmid_handle_vmenter() should be updated then to return true if VMIDs are disabled: bool vmid_handle_vmenter(struct vcpu_vmid *vmid) { struct vmid_data *data = &this_cpu(vmid_data); ... /* * When we assign VMID 1, flush all TLB entries as we are starting a new * generation, and all old VMID allocations are now stale. */ return (vmid->vmid == 1); disabled: vmid->vmid = 0; - return 0; + return true; } > >> + if ( g_disabled != data->disabled ) >> + { >> + printk("%s: VMIDs %sabled.\n", __func__, >> + data->disabled ? "dis" : "en"); >> + if ( !g_disabled ) >> + g_disabled = data->disabled; > This doesn't match x86 code. g_disabled is a tristate there, which only > the boot CPU would ever write to. Why g_disabled is written only by boot CPU? Does x86 have only two options or VMIDs are enabled for all CPUs or it is disabled for all of them? For RISC-V as I mentioned above it is needed to check all harts as the spec. doesn't explicitly mention that VMIDLEN is equal for all harts... > > A clear shortcoming of the x86 code (that you copied) is that the log > message doesn't identify the CPU in question. A sequence of "disabled" > and "enabled" could thus result, without the last one (or in fact any > one) making clear what the overall state is. I think you want to avoid > this from the beginning. ... Thereby it seems like declaration of g_disabled should be moved outside vmid_init() function and add a new function which will return g_disabled value (or just make g_disabled not static and rename to something like g_vmids_disabled). And the print message once after all harts will be initialized, somewhere in setup.c in start_xen() after: for_each_present_cpu ( i ) { if( (num_online_cpus()< nr_cpu_ids)&& !cpu_online(i)) { intret = cpu_up(i); if( ret != 0) printk("Failed to bring up CPU %u (error %d)\n", i, ret); } } (RISC-V doesn't have such code at the moment) ~ Oleksii --------------AK7SuHGjOpmcvQDZfEVxjVSd Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit


    On 8/4/25 5:19 PM, Jan Beulich wrote:
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    Current implementation is based on x86's way to allocate VMIDs:
  VMIDs partition the physical TLB. In the current implementation VMIDs are
  introduced to reduce the number of TLB flushes.  Each time the guest's
  virtual address space changes,

    virtual?
    I assumed that originally it meant that from Xen point of view it could be
called guest's virtual as guest doesn't really work with real physical address,
but it seems like it would be more clear to use guest-physical as you suggested
below.

    instead of flushing the TLB, a new VMID is
  assigned.  This reduces the number of TLB flushes to at most 1/#VMIDs.
  The biggest advantage is that hot parts of the hypervisor's code and data
  retain in the TLB.

  VMIDs are a hart-local resource.  As preemption of VMIDs is not possible,
  VMIDs are assigned in a round-robin scheme.  To minimize the overhead of
  VMID invalidation, at the time of a TLB flush, VMIDs are tagged with a
  64-bit generation. Only on a generation overflow the code needs to
  invalidate all VMID information stored at the VCPUs with are run on the
  specific physical processor.  This overflow appears after about 2^80
  host processor cycles,

    Where's this number coming from? (If you provide numbers, I think they will
want to be "reproducible" by the reader. Which I fear isn't the case here.)
    The 2^80 cycles (based on x86-related numbers) result from:
  1. And VM-Entry/-Exit cycle takes at least 1800 cycles (approximated by 2^10)
  2. We have 64 ASIDs (2^6)
  3. 2^64 generations.
I removed this part of the comment earlier because I assumed that the first
item is quite CPU-dependent, even for x86, let alone for other architectures,
which may have a different number (?).
However, this part of the comment was reintroduced during one of the merges.


    @@ -148,6 +149,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id,
 
     console_init_postirq();
 
+    vmid_init();

    This lives here only temporarily, I assume? Every hart will need to execute
it, and hence (like we have it on x86) this may want to be a central place
elsewhere.
    I haven’t checked how it is done on x86; I probably should.
    I planned to call it for each hart separately during secondary hart bring-up,
since accessing the hgatp register of a hart is required to detect VMIDLEN.
Therefore, vmid_init() should be called for secondary harts when their
initialization code starts executing.


    --- /dev/null
+++ b/xen/arch/riscv/vmid.c
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <xen/domain.h>
+#include <xen/init.h>
+#include <xen/sections.h>
+#include <xen/lib.h>
+#include <xen/param.h>
+#include <xen/percpu.h>
+
+#include <asm/atomic.h>
+#include <asm/csr.h>
+#include <asm/flushtlb.h>
+
+/* Xen command-line option to enable VMIDs */
+static bool __read_mostly opt_vmid_enabled = true;

    __ro_after_init ?
    Agree, __ro_afer_init would be better.

    +boolean_param("vmid", opt_vmid_enabled);
+
+/*
+ * VMIDs partition the physical TLB. In the current implementation VMIDs are
+ * introduced to reduce the number of TLB flushes.  Each time the guest's
+ * virtual address space changes, instead of flushing the TLB, a new VMID is

    The same odd "virtual" again? All the code here is about guest-physical, isn't
it?
    Answered above.
    + * assigned. This reduces the number of TLB flushes to at most 1/#VMIDs.
+ * The biggest advantage is that hot parts of the hypervisor's code and data
+ * retain in the TLB.
+ *
+ * Sketch of the Implementation:
+ *
+ * VMIDs are a hart-local resource.  As preemption of VMIDs is not possible,
+ * VMIDs are assigned in a round-robin scheme.  To minimize the overhead of
+ * VMID invalidation, at the time of a TLB flush, VMIDs are tagged with a
+ * 64-bit generation. Only on a generation overflow the code needs to
+ * invalidate all VMID information stored at the VCPUs with are run on the
+ * specific physical processor.  This overflow appears after about 2^80

    And the same interesting number again.
    Answered above.

    + * host processor cycles, so we do not optimize this case, but simply disable
+ * VMID useage to retain correctness.
+ */
+
+/* Per-Hart VMID management. */
+struct vmid_data {
+   uint64_t hart_vmid_generation;

    Any reason not to simply use "generation"?
    No specific reason for that, it could be renamed to "generation".


    +   uint16_t next_vmid;
+   uint16_t max_vmid;
+   bool disabled;
+};
+
+static DEFINE_PER_CPU(struct vmid_data, vmid_data);
+
+static unsigned long vmidlen_detect(void)

    __init ? Or wait, are you (deliberately) permitting different VMIDLEN
across harts?
    All what I was able in RISC-V spec is that:
  The number of VMID bits is UNSPECIFIED and may be zero. The number of
  implemented VMID bits, termed VMIDLEN, may be determined by writing one
  to every bit position in the VMID field, then reading back the value in
  hgatp to see which bit positions in the VMID field hold a one. The least-
  significant bits of VMID are implemented first: that is, if VMIDLEN > 0,
  VMID[VMIDLEN-1:0] is writable. The maximal value of VMIDLEN, termed
  VMIDMAX, is 7 for Sv32x4 or 14 for Sv39x4, Sv48x4, and Sv57x4..
And I couldn't find explicitly that VMIDLEN will be the same across harts.

Therefore, IMO, while the specification doesn't guarantee VMID will be
different, the "unspecified" nature and the per-hart discovery mechanism
of VMIDLEN in the hgatp CSR allows for VMIDLEN to be different on
different harts in an implementation without violating the
RISC-V privileged specification.




    

    +{
+    unsigned long vmid_bits;

    Why "long" (also for the function return type)?
    Because csr_read() returns unsigned long as HGATP register has
'unsigned long' length.

But it could be done in this way:
    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
    vmid_bits =  MASK_EXTR(csr_read(CSR_HGATP), HGATP_VMID_MASK);
    vmid_bits = ffs_g(vmid_bits);
    csr_write(CSR_HGATP, old);
And then use uint16_t for vmid_bits and use uin16_t as a return type.


    

    +    unsigned long old;
+
+    /* Figure-out number of VMID bits in HW */
+    old = csr_read(CSR_HGATP);
+
+    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
+    vmid_bits = csr_read(CSR_HGATP);
+    vmid_bits =  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);

    Nit: Stray blank.


    +    vmid_bits = flsl(vmid_bits);
+    csr_write(CSR_HGATP, old);
+
+    /*
+     * We polluted local TLB so flush all guest TLB as
+     * a speculative access can happen at any time.
+     */
+    local_hfence_gvma_all();

    There's no guest running. If you wrote hgat.MODE as zero, as per my
understanding now new TLB entries could even purely theoretically appear.
    It could be an issue (or, at least, it is recommended) when hgatp.MODE is
changed:
 If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0
 (and rs2 set to either x0 or the VMID) must be executed to order subsequent
 guest translations with the MODE change—even if the old MODE or new MODE
 is Bare.
On other hand it is guaranteed that, at least, on Reset (and so I assume
for power on) that:
 If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE
 fields are reset to 0.

So it seems like if no guest is ran then there is no need even to write
hgatp.MODE as zero, but it might be sense to do that explicitly just to
be sure.

I thought it was possible to have a running guest and perform a CPU hotplug.
In that case, I expect that during the hotplug, vmidlen_detect() will be
called and return the vmid_bits value, which is used as the active VMID.
At that moment, the local TLB could be speculatively polluted, I think.
Likely, it makes sense to call vmidlen_detect() only once for each hart
during initial bringup.



    In fact, with no guest running (yet) I'm having a hard time seeing why
you shouldn't be able to simply write the register with just
HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable
whether "old" needs restoring; writing plain zero afterwards ought to
suffice. You're in charcge of the register, after all.
    It make sense (but I don't know if it is a possible case) to be sure that
HGATP.MODE remains the same, so there is no need to have TLB flush. If
HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned
above.

If we agreed to keep local_hfence_gvma_all() then I think it isn't really
any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.

Generally if 'old' is guaranteed to be zero (and, probably, it makes sense
to check that in vmidlen_detect() and panic if it isn't zero) and if
vmidlen_detect() function will be called before any guest domain(s) will
be ran then I could agree that we don't need local_hfence_gvma_all() here.

As an option we can do local_hfence_gvma_all() only if 'old' value wasn't
set to zero.

Does it make sense?

    

    +    return vmid_bits;
+}
+
+void vmid_init(void)
+{
+    static bool g_disabled = false;

    
      
    
        
    +    unsigned long vmid_len = vmidlen_detect();
+    struct vmid_data *data = &this_cpu(vmid_data);
+    unsigned long max_availalbe_bits = sizeof(data->max_vmid) << 3;

    
      
    
      
    Nit: Typo in "available". Also now that we have it, better use
BITS_PER_BYTE here?
    
    
    
    
    Sure, I will use BITS_PER_BYTE.


    
    
    
      
    

    
      
    
        
    +    if ( vmid_len > max_availalbe_bits )
+        panic("%s: VMIDLEN is bigger then a type which represent VMID: %lu(%lu)\n",
+              __func__, vmid_len, max_availalbe_bits);

    
      
    
      
    This shouldn't be a runtime check imo. What you want to check (at build
time) is that the bits set in HGATP_VMID_MASK can be held in ->max_vmid.
    
    
    
    
    Oh, I just noticed that this check isn't even really correct because of
data->max_vmid is inited after this check.

Anyway, build time check would be better.


    
    
    
      
    

    
      
    
        
    +    data->max_vmid = BIT(vmid_len, U) - 1;
+    data->disabled = !opt_vmid_enabled || (vmid_len <= 1);

    
      
    
      
    Actually, what exactly does it mean that "VMIDs are disabled"? There's
no enable bit that I could find anywhere. Isn't it rather that in this
case you need to arrange to flush always on VM entry (or always after a
P2M change, depending how the TLB is split between guest and host use)?
    
    
    
    
    "VMIDs are disabled" here means that TLB flush will happen each time p2m
is changed.

    
    
    
      
    If you look at vmx_vmenter_helper(), its flipping of
SECONDARY_EXEC_ENABLE_VPID tweaks CPU behavior, such that the flush
would be implicit (when the bit is off). I don't expect RISC-V has any
such "implicit" flushing behavior?
    
    
    
    
    RISC-V relies on explicit software-managed fence instructions for TLB
flushing.

It seems like vmid_handle_vmenter() should be updated then to return
true if VMIDs are disabled:
  bool vmid_handle_vmenter(struct vcpu_vmid *vmid)
  {
      struct vmid_data *data = &this_cpu(vmid_data);
  
  ...
  
      /*
       * When we assign VMID 1, flush all TLB entries as we are starting a new
       * generation, and all old VMID allocations are now stale.
       */
      return (vmid->vmid == 1);
  
   disabled:
      vmid->vmid = 0;
-      return 0;
+      return true;
  }


    
    
    
      
    

    
      
    
        
    +    if ( g_disabled != data->disabled )
+    {
+        printk("%s: VMIDs %sabled.\n", __func__,
+               data->disabled ? "dis" : "en");
+        if ( !g_disabled )
+            g_disabled = data->disabled;

    
      
    
      
    This doesn't match x86 code. g_disabled is a tristate there, which only
the boot CPU would ever write to.
    
    
    
    
    Why g_disabled is written only by boot CPU? Does x86 have only two options
or VMIDs are enabled for all CPUs or it is disabled for all of them?

For RISC-V as I mentioned above it is needed to check all harts as the spec.
doesn't explicitly mention that VMIDLEN is equal for all harts...


    
    
    
      
    
A clear shortcoming of the x86 code (that you copied) is that the log
message doesn't identify the CPU in question. A sequence of "disabled"
and "enabled" could thus result, without the last one (or in fact any
one) making clear what the overall state is. I think you want to avoid
this from the beginning.
    
    
    
    
    ... Thereby it seems like declaration of g_disabled should be moved outside
vmid_init() function and add a new function which will return g_disabled
value (or just make g_disabled not static and rename to something like
g_vmids_disabled).

And the print message once after all harts will be initialized, somewhere
in setup.c in start_xen() after:
 
    for_each_present_cpu ( i )
    {
        if ( (num_online_cpus() < nr_cpu_ids) && !cpu_online(i) )
        {
            int ret = cpu_up(i);
            if ( ret != 0 )
                printk("Failed to bring up CPU %u (error %d)\n", i, ret);
        }
    }
(RISC-V doesn't have such code at the moment)

~ Oleksii
    
  


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Subject: Re: [PATCH v3 04/20] xen/riscv: introduce things necessary for p2m
 initialization
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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From: Oleksii Kurochko 
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On 8/4/25 5:53 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> --- a/xen/arch/riscv/include/asm/p2m.h
>> +++ b/xen/arch/riscv/include/asm/p2m.h
>> @@ -3,11 +3,45 @@
>>   #define ASM__RISCV__P2M_H
>>   
>>   #include 
>> +#include 
>> +#include 
>> +#include 
>>   
>>   #include 
>>   
>>   #define paddr_bits PADDR_BITS
>>   
>> +/* Get host p2m table */
>> +#define p2m_get_hostp2m(d) (&(d)->arch.p2m)
>> +
>> +/* Per-p2m-table state */
>> +struct p2m_domain {
>> +    /*
>> +     * Lock that protects updates to the p2m.
>> +     */
>> +    rwlock_t lock;
>> +
>> +    /* Pages used to construct the p2m */
>> +    struct page_list_head pages;
>> +
>> +    /* Indicate if it is required to clean the cache when writing an entry */
>> +    bool clean_pte;
> I'm a little puzzled by this field still being here, despite the extensive
> revlog commentary. If you really feel you need to keep it, please ...

I think still it could be useful to have clean_pte, but likely not in this patch.
I will move an introduction of it to one of the next patch where it is started
really to be used.

>
>> +    /* Back pointer to domain */
>> +    struct domain *domain;
>> +
>> +    /*
>> +     * P2M updates may required TLBs to be flushed (invalidated).
>> +     *
>> +     * Flushes may be deferred by setting 'need_flush' and then flushing
>> +     * when the p2m write lock is released.
>> +     *
>> +     * If an immediate flush is required (e.g, if a super page is
>> +     * shattered), call p2m_tlb_flush_sync().
>> +     */
>> +    bool need_flush;
> ... group booleans together, for better packing.

I will take that into account. Thanks.

~ Oleksii

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    On 8/4/25 5:53 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    --- a/xen/arch/riscv/include/asm/p2m.h
+++ b/xen/arch/riscv/include/asm/p2m.h
@@ -3,11 +3,45 @@
 #define ASM__RISCV__P2M_H
 
 #include <xen/errno.h>
+#include <xen/mm.h>
+#include <xen/rwlock.h>
+#include <xen/types.h>
 
 #include <asm/page-bits.h>
 
 #define paddr_bits PADDR_BITS
 
+/* Get host p2m table */
+#define p2m_get_hostp2m(d) (&(d)->arch.p2m)
+
+/* Per-p2m-table state */
+struct p2m_domain {
+    /*
+     * Lock that protects updates to the p2m.
+     */
+    rwlock_t lock;
+
+    /* Pages used to construct the p2m */
+    struct page_list_head pages;
+
+    /* Indicate if it is required to clean the cache when writing an entry */
+    bool clean_pte;

    
      
    
      
    I'm a little puzzled by this field still being here, despite the extensive
revlog commentary. If you really feel you need to keep it, please ...
    
    
    
    
    I think still it could be useful to have clean_pte, but likely not in this patch.
I will move an introduction of it to one of the next patch where it is started
really to be used.


    
    
    
      
    

    
      
    
        
    +    /* Back pointer to domain */
+    struct domain *domain;
+
+    /*
+     * P2M updates may required TLBs to be flushed (invalidated).
+     *
+     * Flushes may be deferred by setting 'need_flush' and then flushing
+     * when the p2m write lock is released.
+     *
+     * If an immediate flush is required (e.g, if a super page is
+     * shattered), call p2m_tlb_flush_sync().
+     */
+    bool need_flush;

    
      
    
      
    ... group booleans together, for better packing.
    
    
    
    
    I will take that into account. Thanks.

~ Oleksii

    
  


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Subject: Re: [PATCH] ns16550: ensure polling timer is disarmed
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On 06.08.2025 12:53, Roger Pau Monné wrote:
> On Fri, Aug 01, 2025 at 09:34:42AM +0200, Jan Beulich wrote:
>> On 31.07.2025 23:42, dmkhn@proton.me wrote:
>>> On Thu, Jul 31, 2025 at 08:54:10AM +0200, Jan Beulich wrote:
>>>> On 30.07.2025 20:31, dmkhn@proton.me wrote:
>>>>> On Wed, Jul 30, 2025 at 10:12:54AM +0200, Jan Beulich wrote:
>>>>>> On 30.07.2025 05:13, dmkhn@proton.me wrote:
>>>>>>> From: Denis Mukhin 
>>>>>>>
>>>>>>> As it stands, polling timer is kept in the list of timers even after the
>>>>>>> interrupts have been enabled / polling disabled on ns16550-compatible UART.
>>>>>>>
>>>>>>> Ensure polling timer is removed from the timer list once UART interrupts are
>>>>>>> enabled.
>>>>>>>
>>>>>>> Signed-off-by: Denis Mukhin 
>>>>>>
>>>>>> Wasn't it Andrew(?) who suggested something along these lines? That would
>>>>>> want reflecting by a tag then.
>>>>>
>>>>> Yes, indeed.
>>>>>
>>>>>>
>>>>>> Also, what's the real problem you want to solve here? The timer function
>>>>>> would be run one more time after ->intr_works is set, and then the timer
>>>>>> will be permanently inactive (up to a possible S3 resume). Is it being on
>>>>>> an inactive list an actual problem? (IOW I'd like to understand if the
>>>>>> change is merely cosmetic, or if there is some actual benefit.)
>>>>>
>>>>> My understanding is running polling timer one more time after the interrupts
>>>>> are enabled is the issue: if there's a pending timer when it is known the
>>>>> timer not needed, then the timer should be canceled.
>>>>
>>>> And the effort of canceling outweighs the one extra running of the timer?
>>>
>>> I think so, because intr_works will not flip at run-time once set.
>>> If so, no need to keep the timer ready to be rearmed.
>>
>> Well, to me it looks like a code size increase with extremely limited benefit.
>> Hence while likely I wouldn't outright NAK such a change, I also wouldn't ACK
>> it.
> 
> Hm, indeed the net win of this is dubious, as the extra polling
> interrupt would only happen once.  Using stop_timer() would be less
> heavyweight than kill_timer().
> 
> Overall I think it needs justification in the commit message, as the
> timer cannot be removed from the list of timers, otherwise it's usage
> on resume from suspension will trigger an ASSERT, so part of the
> commit message is stale.

That could be compensated by another init_timer(), though. (In fact when
originally looking at the patch, I [wrongly] thought that path was taken
on resume, so didn't comment on that aspect.)

Jan


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Subject: Re: [PATCH v3 05/20] xen/riscv: construct the P2M pages pool for
 guests
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 8/5/25 12:40 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> @@ -30,3 +34,18 @@ int p2m_init(struct domain *d)
>>   
>>       return 0;
>>   }
>> +
>> +/*
>> + * Set the pool of pages to the required number of pages.
>> + * Returns 0 for success, non-zero for failure.
>> + * Call with d->arch.paging.lock held.
>> + */
>> +int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted)
> Noticed only when looking at the subsequent patch: With this being ...
>
>> +{
>> +    int rc;
>> +
>> +    if ( (rc = paging_freelist_init(d, pages, preempted)) )
> ... a caller of this function, the "init" in the name feels wrong.

I thought about paging_freelist_alloc(), but it feels wrong too as it sounds like
freelist is being allocated inside this functions, but what really happens that
pages are allocated and just added/removed to/from freelist.

Maybe something like paging_freelist_resize() or *_adjust() would be better?

~ Oleksii

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    On 8/5/25 12:40 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    @@ -30,3 +34,18 @@ int p2m_init(struct domain *d)
 
     return 0;
 }
+
+/*
+ * Set the pool of pages to the required number of pages.
+ * Returns 0 for success, non-zero for failure.
+ * Call with d->arch.paging.lock held.
+ */
+int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted)

    
      
    
      
    Noticed only when looking at the subsequent patch: With this being ...


    
      
    
        
    +{
+    int rc;
+
+    if ( (rc = paging_freelist_init(d, pages, preempted)) )

    
      
    
      
    ... a caller of this function, the "init" in the name feels wrong.
    
    
    
    
    I thought about paging_freelist_alloc(), but it feels wrong too as it sounds like
freelist is being allocated inside this functions, but what really happens that
pages are allocated and just added/removed to/from freelist.

Maybe something like paging_freelist_resize() or *_adjust() would be better?

~ Oleksii

    
  


--------------H6KpCsd5d2afR9BLfiirc8TZ--


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On 06.08.2025 13:33, Oleksii Kurochko wrote:
> On 8/4/25 5:19 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> @@ -148,6 +149,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id,
>>>   
>>>       console_init_postirq();
>>>   
>>> +    vmid_init();
>> This lives here only temporarily, I assume? Every hart will need to execute
>> it, and hence (like we have it on x86) this may want to be a central place
>> elsewhere.
> 
> I haven’t checked how it is done on x86; I probably should.
> 
> I planned to call it for each hart separately during secondary hart bring-up,
> since accessing the|hgatp| register of a hart is required to detect|VMIDLEN|.
> Therefore,|vmid_init()| should be called for secondary harts when their
> initialization code starts executing.

But is this going to be the only per-hart thing that will need doing? Otherwise
the same larger "container" function may want calling instead.

>>> +static unsigned long vmidlen_detect(void)
>> __init ? Or wait, are you (deliberately) permitting different VMIDLEN
>> across harts?
> 
> All what I was able in RISC-V spec is that:
>    The number of VMID bits is UNSPECIFIED and may be zero. The number of
>    implemented VMID bits, termed VMIDLEN, may be determined by writing one
>    to every bit position in the VMID field, then reading back the value in
>    hgatp to see which bit positions in the VMID field hold a one. The least-
>    significant bits of VMID are implemented first: that is, if VMIDLEN > 0,
>    VMID[VMIDLEN-1:0] is writable. The maximal value of VMIDLEN, termed
>    VMIDMAX, is 7 for Sv32x4 or 14 for Sv39x4, Sv48x4, and Sv57x4..
> And I couldn't find explicitly that VMIDLEN will be the same across harts.
> 
> Therefore, IMO, while the specification doesn't guarantee VMID will be
> different, the "unspecified" nature and the per-hart discovery mechanism
> of VMIDLEN in the hgatp CSR allows for VMIDLEN to be different on
> different harts in an implementation without violating the
> RISC-V privileged specification.

Okay, since that's easily feasible with the present implementation, why not
keep it like that then.

>>> +{
>>> +    unsigned long vmid_bits;
>> Why "long" (also for the function return type)?
> 
> Because csr_read() returns unsigned long as HGATP register has
> 'unsigned long' length.

Oh, right, I should have commented on the function return type only.
Yet then I also can't resist stating that this kind of use of a variable,
which initially is assigned a value that doesn't really fit its name, is
easily misleading towards giving such comments.

> But it could be done in this way:
>      csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>      vmid_bits =  MASK_EXTR(csr_read(CSR_HGATP), HGATP_VMID_MASK);
>      vmid_bits = ffs_g(vmid_bits);
>      csr_write(CSR_HGATP, old);
> And then use uint16_t for vmid_bits and use uin16_t as a return type.

Please check ./CODING_STYLE again as to the use of fixed-width types.

>>> +    unsigned long old;
>>> +
>>> +    /* Figure-out number of VMID bits in HW */
>>> +    old = csr_read(CSR_HGATP);
>>> +
>>> +    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>> +    vmid_bits = csr_read(CSR_HGATP);
>>> +    vmid_bits =  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);
>> Nit: Stray blank.
>>
>>> +    vmid_bits = flsl(vmid_bits);
>>> +    csr_write(CSR_HGATP, old);
>>> +
>>> +    /*
>>> +     * We polluted local TLB so flush all guest TLB as
>>> +     * a speculative access can happen at any time.
>>> +     */
>>> +    local_hfence_gvma_all();
>> There's no guest running. If you wrote hgat.MODE as zero, as per my
>> understanding now new TLB entries could even purely theoretically appear.
> 
> It could be an issue (or, at least, it is recommended) when hgatp.MODE is
> changed:
>   If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0
>   (and rs2 set to either x0 or the VMID) must be executed to order subsequent
>   guest translations with the MODE change—even if the old MODE or new MODE
>   is Bare.
> On other hand it is guaranteed that, at least, on Reset (and so I assume
> for power on) that:
>   If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE
>   fields are reset to 0.
> 
> So it seems like if no guest is ran then there is no need even to write
> hgatp.MODE as zero, but it might be sense to do that explicitly just to
> be sure.
> 
> I thought it was possible to have a running guest and perform a CPU hotplug.

But that guest will run on another hart.

> In that case, I expect that during the hotplug,|vmidlen_detect()| will be
> called and return the|vmid_bits| value, which is used as the active VMID.
> At that moment, the local TLB could be speculatively polluted, I think.
> Likely, it makes sense to call vmidlen_detect() only once for each hart
> during initial bringup.

That may bring you more problems than it solves. You'd need to stash away
the value originally read somewhere. And that somewhere isn't per-CPU data.

>> In fact, with no guest running (yet) I'm having a hard time seeing why
>> you shouldn't be able to simply write the register with just
>> HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable
>> whether "old" needs restoring; writing plain zero afterwards ought to
>> suffice. You're in charcge of the register, after all.
> 
> It make sense (but I don't know if it is a possible case) to be sure that
> HGATP.MODE remains the same, so there is no need to have TLB flush. If
> HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned
> above.
> 
> If we agreed to keep local_hfence_gvma_all() then I think it isn't really
> any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.
> 
> Generally if 'old' is guaranteed to be zero (and, probably, it makes sense
> to check that in vmidlen_detect() and panic if it isn't zero) and if
> vmidlen_detect() function will be called before any guest domain(s) will
> be ran then I could agree that we don't need local_hfence_gvma_all() here.
> 
> As an option we can do local_hfence_gvma_all() only if 'old' value wasn't
> set to zero.
> 
> Does it make sense?

Well - I'd like the pre-conditions to be understood better. For example, can
a hart really speculate into guest mode, when the hart is only in the
process of being brought up?

>>> +    data->max_vmid = BIT(vmid_len, U) - 1;
>>> +    data->disabled = !opt_vmid_enabled || (vmid_len <= 1);
>> Actually, what exactly does it mean that "VMIDs are disabled"? There's
>> no enable bit that I could find anywhere. Isn't it rather that in this
>> case you need to arrange to flush always on VM entry (or always after a
>> P2M change, depending how the TLB is split between guest and host use)?
> 
> "VMIDs are disabled" here means that TLB flush will happen each time p2m
> is changed.

That's better described as "VMIDs aren't used" then?

>>> +    if ( g_disabled != data->disabled )
>>> +    {
>>> +        printk("%s: VMIDs %sabled.\n", __func__,
>>> +               data->disabled ? "dis" : "en");
>>> +        if ( !g_disabled )
>>> +            g_disabled = data->disabled;
>> This doesn't match x86 code. g_disabled is a tristate there, which only
>> the boot CPU would ever write to.
> 
> Why g_disabled is written only by boot CPU? Does x86 have only two options
> or VMIDs are enabled for all CPUs or it is disabled for all of them?

Did you look at the x86 code again, or the patch that I sent for it?

> For RISC-V as I mentioned above it is needed to check all harts as the spec.
> doesn't explicitly mention that VMIDLEN is equal for all harts...

Even if in practice x86 systems are symmetric in this regard, you will
have seen that we support varying values there as well. Up to and
including ASIDs being in use on some CPUs, but not on others. So that
code can serve as a reference for you, I think.

>> A clear shortcoming of the x86 code (that you copied) is that the log
>> message doesn't identify the CPU in question. A sequence of "disabled"
>> and "enabled" could thus result, without the last one (or in fact any
>> one) making clear what the overall state is. I think you want to avoid
>> this from the beginning.
> 
> ... Thereby it seems like declaration of g_disabled should be moved outside
> vmid_init() function and add a new function which will return g_disabled
> value (or just make g_disabled not static and rename to something like
> g_vmids_disabled).

No, why? While I didn't Cc you on my patch submission, I specifically
replied to it with you (alone) on the To: list, just so you can look
there first before suggesting (sorry) odd things.

Jan


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Subject: Re: [PATCH v3 05/20] xen/riscv: construct the P2M pages pool for
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To: Oleksii Kurochko 
Cc: Alistair Francis ,
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On 06.08.2025 14:01, Oleksii Kurochko wrote:
> 
> On 8/5/25 12:40 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> @@ -30,3 +34,18 @@ int p2m_init(struct domain *d)
>>>   
>>>       return 0;
>>>   }
>>> +
>>> +/*
>>> + * Set the pool of pages to the required number of pages.
>>> + * Returns 0 for success, non-zero for failure.
>>> + * Call with d->arch.paging.lock held.
>>> + */
>>> +int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted)
>> Noticed only when looking at the subsequent patch: With this being ...
>>
>>> +{
>>> +    int rc;
>>> +
>>> +    if ( (rc = paging_freelist_init(d, pages, preempted)) )
>> ... a caller of this function, the "init" in the name feels wrong.
> 
> I thought about paging_freelist_alloc(), but it feels wrong too as it sounds like
> freelist is being allocated inside this functions, but what really happens that
> pages are allocated and just added/removed to/from freelist.
> 
> Maybe something like paging_freelist_resize() or *_adjust() would be better?

Yes; whichever of the two you like better.

Jan


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From: Ayan Kumar Halder 
To: 
CC: , , Ayan Kumar Halder
	
Subject: [ImageBuilder] Add config option to use separate load commands for Xen, DOM0 and DOMU binaries
Date: Wed, 6 Aug 2025 13:33:52 +0100
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Introduce the following options :-
1. XEN_LOAD - This specifies command to load xen hypervisor binary and device
tree.
2. DOM0_LOAD - This specifies command to load Dom0 binaries.
3. DOMU_LOAD[] - This specifies command to load DomU binaries.

There can be situations where Xen, Dom0 and DomU binaries are stored in
different partitions. Thus, imagebuilder should provide a way the binaries
using different commands.

If any of the above options are not specified, LOAD_CMD is used by default.

Signed-off-by: Ayan Kumar Halder 
---
 README.md                | 14 ++++++++++++++
 scripts/uboot-script-gen | 32 +++++++++++++++++++++++---------
 2 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/README.md b/README.md
index b7be268..4be6efb 100644
--- a/README.md
+++ b/README.md
@@ -33,10 +33,12 @@ BOOT_CMD="booti"
 
 DEVICE_TREE="mpsoc.dtb"
 XEN="xen"
+XEN_LOAD="ext4load mmc 0:1"
 XEN_CMD="console=dtuart dtuart=serial0 dom0_mem=1G dom0_max_vcpus=1 bootscrub=0 vwfi=native sched=null"
 PASSTHROUGH_DTS_REPO="git@github.com:Xilinx/xen-passthrough-device-trees.git device-trees-2021.2/zcu102"
 DOM0_KERNEL="Image-dom0"
 DOM0_CMD="console=hvc0 earlycon=xen earlyprintk=xen clk_ignore_unused"
+DOM0_LOAD="ext4load mmc 2:1"
 DOM0_RAMDISK="dom0-ramdisk.cpio"
 DOM0_MEM=1024
 DOM0_VCPUS=1
@@ -46,11 +48,13 @@ DT_OVERLAY[0]="host_dt_overlay.dtbo"
 
 NUM_DOMUS=2
 DOMU_KERNEL[0]="zynqmp-dom1/Image-domU"
+DOMU_LOAD[0]="ext4load mmc 4:1"
 DOMU_PASSTHROUGH_PATHS[0]="/axi/ethernet@ff0e0000 /axi/serial@ff000000"
 DOMU_CMD[0]="console=ttyPS0 earlycon console=ttyPS0,115200 clk_ignore_unused rdinit=/sbin/init root=/dev/ram0 init=/bin/sh"
 DOMU_RAMDISK[0]="zynqmp-dom1/domU-ramdisk.cpio"
 DOMU_COLORS[0]="6-14"
 DOMU_KERNEL[1]="zynqmp-dom2/Image-domU"
+DOMU_LOAD[1]="ext4load mmc 5:1"
 DOMU_CMD[1]="console=ttyAMA0 clk_ignore_unused rdinit=/sbin/init root=/dev/ram0 init=/bin/sh"
 DOMU_RAMDISK[1]="zynqmp-dom2/domU-ramdisk.cpio"
 DOMU_MEM[1]=512
@@ -99,6 +103,9 @@ Where:
 - XEN_CMD specifies the command line arguments used for Xen.  If not
   set, the default one will be used.
 
+- XEN_LOAD specifies the command to load XEN and DEVICE_TREE. If not set,
+  LOAD_CMD will be used.
+
 - XEN_STATIC_HEAP="baseaddr1 size1 ... baseaddrN sizeN"
   if specified, indicates the host physical address regions
   [baseaddr, baseaddr + size) to be reserved as Xen static heap.
@@ -109,6 +116,9 @@ Where:
   uboot-script-gen will compile the partial device trees which have
   been specified in DOMU_PASSTHROUGH_PATHS[number].
 
+- DOM0_LOAD specifies the command to load DOM0_KERNEL and DOM0_RAMDISK. If not
+  set, LOAD_CMD will be used.
+
 - DOM0_KERNEL specifies the Dom0 kernel file to load.
   For dom0less configurations, the parameter is optional.
 
@@ -159,6 +169,10 @@ Where:
   kernel. If not set and DOMU_VPL011[number] is not set to 0, then
   "console=ttyAMA0" is used.
 
+- DOMU_LOAD[number] specifies the command to load DOMU_KERNEL[number],
+  DOMU_RAMDISK[number] and DOMU_PASSTHROUGH_DTB[number]. If not set, then
+  LOAD_CMD is used.
+
 - DOMU_RAMDISK[number] specifies the DomU ramdisk to use.
 
 - DOMU_PASSTHROUGH_PATHS[number] specifies the passthrough devices (
diff --git a/scripts/uboot-script-gen b/scripts/uboot-script-gen
index b81e614..fed53aa 100755
--- a/scripts/uboot-script-gen
+++ b/scripts/uboot-script-gen
@@ -737,6 +737,7 @@ function load_file()
 {
     local filename=$1
     local fit_scr_name=$2
+    local load_cmd=$3
 
     local absolute_path="$(realpath --no-symlinks $filename)"
     local base="$(realpath $PWD)"/
@@ -748,10 +749,10 @@ function load_file()
         add_size_from_file $filename
     else
         if test "$CALC"; then
-            echo "$LOAD_CMD \${memaddr} ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
+            echo "$load_cmd \${memaddr} ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
             add_size_calculate $fit_scr_name
         else
-            echo "$LOAD_CMD $memaddr ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
+            echo "$load_cmd $memaddr ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
             add_size_from_file $filename
         fi
     fi
@@ -1003,11 +1004,15 @@ generate_uboot_images()
 
 xen_file_loading()
 {
+    if test -z "$DOM0_LOAD"
+    then
+        DOM0_LOAD="$LOAD_CMD"
+    fi
     if test "$DOM0_KERNEL"
     then
         check_compressed_file_type $DOM0_KERNEL "executable\|uImage"
         dom0_kernel_addr=$memaddr
-        load_file $DOM0_KERNEL "dom0_linux"
+        load_file $DOM0_KERNEL "dom0_linux" "$DOM0_LOAD"
         dom0_kernel_size=$filesize
     fi
     if test "$DOM0_RAMDISK"
@@ -1015,7 +1020,7 @@ xen_file_loading()
         check_compressed_file_type $DOM0_RAMDISK "cpio archive"
         ramdisk_addr=$memaddr
         ramdisk_path=$DOM0_RAMDISK
-        load_file "$DOM0_RAMDISK" "dom0_ramdisk"
+        load_file "$DOM0_RAMDISK" "dom0_ramdisk" "$DOM0_LOAD"
         ramdisk_size=$filesize
     else
         ramdisk_addr="-"
@@ -1024,6 +1029,10 @@ xen_file_loading()
     i=0
     while test $i -lt $NUM_DOMUS
     do
+        if test -z "${DOMU_LOAD[$i]}"
+        then
+            DOMU_LOAD[$i]="$LOAD_CMD"
+        fi
         if test "${DOMU_ROOTFS[$i]}" || test "${DOMU_NOBOOT[$i]}"
         then
             if test -z "${DOMU_NOBOOT[$i]}"
@@ -1042,20 +1051,20 @@ xen_file_loading()
 
         check_compressed_file_type ${DOMU_KERNEL[$i]} "executable\|uImage"
         domU_kernel_addr[$i]=$memaddr
-        load_file ${DOMU_KERNEL[$i]} "domU${i}_kernel"
+        load_file ${DOMU_KERNEL[$i]} "domU${i}_kernel" "${DOMU_LOAD[$i]}"
         domU_kernel_size[$i]=$filesize
         if test "${DOMU_RAMDISK[$i]}"
         then
             check_compressed_file_type ${DOMU_RAMDISK[$i]} "cpio archive"
             domU_ramdisk_addr[$i]=$memaddr
-            load_file ${DOMU_RAMDISK[$i]} "domU${i}_ramdisk"
+            load_file ${DOMU_RAMDISK[$i]} "domU${i}_ramdisk" "${DOMU_LOAD[$i]}"
             domU_ramdisk_size[$i]=$filesize
         fi
         if test "${DOMU_PASSTHROUGH_DTB[$i]}"
         then
             check_compressed_file_type ${DOMU_PASSTHROUGH_DTB[$i]} "Device Tree Blob"
             domU_passthrough_dtb_addr[$i]=$memaddr
-            load_file ${DOMU_PASSTHROUGH_DTB[$i]} "domU${i}_fdt"
+            load_file ${DOMU_PASSTHROUGH_DTB[$i]} "domU${i}_fdt" "${DOMU_LOAD[$i]}"
             domU_passthrough_dtb_size[$i]=$filesize
         fi
         i=$(( $i + 1 ))
@@ -1070,9 +1079,14 @@ xen_file_loading()
         generate_uboot_images
     fi
 
+    if test -z "${XEN_LOAD}"
+    then
+        XEN_LOAD="$LOAD_CMD"
+    fi
+
     kernel_addr=$memaddr
     kernel_path=$XEN
-    load_file "$XEN" "host_kernel"
+    load_file "$XEN" "host_kernel" "$XEN_LOAD"
 
     xen_policy_addr="-"
     if test -n "$XEN_POLICY"
@@ -1691,7 +1705,7 @@ fi
 
 check_file_type $DEVICE_TREE "Device Tree Blob"
 device_tree_addr=$memaddr
-load_file $DEVICE_TREE "host_fdt"
+load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
 bitstream_load_and_config  # bitstream is loaded last but used first
 device_tree_editing $device_tree_addr
 
-- 
2.25.1



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Date: Wed, 6 Aug 2025 15:48:36 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 0/8] x86: introduce NS16550-compatible UART emulator
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
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On Thu, Jul 31, 2025 at 07:21:37PM +0000, dmkhn@proton.me wrote:
> x86 port of Xen lacks vUART facility similar to Arm's vpl011 to support x86
> guest OS bring up in the embedded setups.
> 
> This patch series introduces initial in-hypervisor emulator for
> NS8250/NS16x50-compatible UARTs under CONFIG_VUART_NS16550.
> 
> In parallel domain creation scenario (hyperlaunch), NS16550 emulator helps
> early guest firmware and OS bringup debugging, because it eliminates
> dependency on the external emulator (qemu) being operational by the time
> domains are created.
> 
> The emulator also allows to forward the physical console input to the x86
> domain which is useful when a system has only one physical UART for early
> debugging and this UART is owned by Xen.
> 
> By default, CONFIG_VUART_NS16550 enables emulation of NS16550 at I/O port
> 0x3f8, IRQ#4 in guest OS (legacy COM1). But all legacy COM resources can be
> selected at built-time (no per-domain configuration yet).
> 
> The NS16550 emulator is disabled in default x86 configuration and goes under
> CONFIG_EXPERT in menuconfig.
> 
> Limitations
> ===========
> - Only x86;
> - Only HVM domains support (build-time), PVH domains are not supported yet;

I'm confused by the above statement, HVM domains always have an
emulated serial provided by QEMU if needed, so I think you got this
backwards, and it should instead be:

- Only PVH domains supported, PV and HVM domains are not supported yet.

?

Thanks, Roger.


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Date: Wed, 6 Aug 2025 15:56:42 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: dmkhn@proton.me
Cc: Jan Beulich , andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com,
	sstabellini@kernel.org, oleksii.kurochko@gmail.com,
	dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 1/8] xen/domain: introduce common emulation flags
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-2-dmukhin@ford.com>
 
 
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On Tue, Aug 05, 2025 at 12:54:31AM +0000, dmkhn@proton.me wrote:
> + Cc: Oleskii
> 
> On Mon, Aug 04, 2025 at 11:46:36AM +0200, Jan Beulich wrote:
> > On 31.07.2025 21:21, dmkhn@proton.me wrote:
> > > --- a/xen/include/xen/sched.h
> > > +++ b/xen/include/xen/sched.h
> > > @@ -652,6 +652,8 @@ struct domain
> > >      unsigned int *llc_colors;
> > >  #endif
> > >
> > > +    uint32_t emulation_flags;
> > 
> > Just one further remark: The field probably never should have been of this
> > type; unsigned int will do, and imo will want switching to while the field
> > is being moved. (Before giving an x86 ack, I want to convince myself though
> > that this is moving us in the right direction.)
> 
> Hi Jan,
> 
> I can definitely use different mechanism for virt ns16550: add a new field in
> xen_arch_domainconfig. That will also simplify some of the emulation_flags
> checks on x86 and will be more flexible wrt emulator configuration (e.g. I can
> allow passing I/O ports ranges).

For the time being, I would leave emulation_flags in
xen_arch_domainconfig.  The set of emulated devices is
architecture-specific, and pulling it to the generic struct is IMO not
specially helpful, as you then have the definition of the flags
decoupled from the field definition.

For the emulated UART, I don't think you need a new field in
xen_arch_domainconfig, just a new bit in emulation_flags? IOW:

#define _XEN_X86_EMU_VUART          11
#define XEN_X86_EMU_VUART           (1U << _XEN_X86_EMU_VUART)

Thanks, Roger.


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On 7/26/25 05:23, Julien Grall wrote:
> Hi,
> 
> On 25/07/2025 15:01, Stewart Hildebrand wrote:
>> From: Stefano Stabellini 
>>
>> Up until f9f6b22abf1d "xen/arm: Map ITS doorbell register to IOMMU page
>> tables" the only caller of iommu_map on ARM was grant_table.c which has
>> a specific usage model and restrictions as described by the in-code
>> comment in arm_iommu_map_page.
>>
>> f9f6b22abf1d introduced a second caller to iommu_map on ARM:
>> vgic_v3_its_init_virtual. This specific statement in the
>> f9f6b22abf1d commit message is partially wrong:
>>
>> "Note that the 1:1 check in arm_iommu_map_page remains for now, as
>> virtual ITSes are currently only created for hwdom where the doorbell
>> mapping is always 1:1."
>>
>> Leading to crashes any time the hardware domain is not direct-mapped
>> (e.g. cache coloring and non-Dom0 hardware domain):
>>
>> (XEN) Xen BUG at drivers/passthrough/arm/iommu_helpers.c:47
>> [...]
>> (XEN) Xen call trace:
>> (XEN)    [<00000a000024c758>] arm_iommu_map_page+0x80/0x90 (PC)
>> (XEN)    [<00000a000024c750>] arm_iommu_map_page+0x78/0x90 (LR)
>> (XEN)    [<00000a0000250884>] iommu_map+0xcc/0x29c
>> (XEN)    [<00000a0000288024>] vgic_v3_its_init_domain+0x18c/0x1e8
>> (XEN)    [<00000a0000285228>] vgic-v3.c#vgic_v3_domain_init+0x168/0x21c
>> (XEN)    [<00000a0000281dcc>] domain_vgic_init+0x14c/0x210
>> (XEN)    [<00000a00002705a4>] arch_domain_create+0x150/0x1f0
>> (XEN)    [<00000a00002055e8>] domain_create+0x47c/0x6c0
>> (XEN)    [<00000a00002cf090>] create_domUs+0x7f8/0x8cc
>> (XEN)    [<00000a00002eb588>] start_xen+0x8f4/0x998
>> (XEN)    [<00000a000020018c>] head.o#primary_switched+0x4/0x10
>>
>> Specifically, non-1:1 hardware domain exists with cache coloring
>> enabled. For that, is_domain_direct_mapped(d) is false but
>> domain_use_host_layout(d) is true.
>>
>> Change the is_domain_direct_mapped(d) checks in arm_iommu_map_page and
>> arm_iommu_unmap_page into domain_use_host_layout(d) checks.
>>
>> Drop stale in-code comment specific to grant table mappings.
>>
>> Fixes: f9f6b22abf1d ("xen/arm: Map ITS doorbell register to IOMMU page tables")
>> Signed-off-by: Stefano Stabellini 
>> Signed-off-by: Stewart Hildebrand 
> 
> Reviewed-by: Julien Grall 

Thanks for the review! Is this ready to be committed?


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Date: Wed, 6 Aug 2025 17:02:40 +0300
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Subject: Re: [PATCH v2] xen/dom0less: arm: fix hwdom 1:1 low memory allocation
To: Julien Grall ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Denis Mukhin , Jason Andryuk 
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On 06.08.25 11:48, Julien Grall wrote:
> Hi Grygorii,
> 
> On 06/08/2025 09:19, Grygorii Strashko wrote:
>> Hi Julien,
>>
>> On 06.08.25 00:07, Julien Grall wrote:
>>> Hi Grygorii,
>>>
>>> On 05/08/2025 20:00, Grygorii Strashko wrote:
>>>> From: Grygorii Strashko 
>>>>
>>>> Call stack for dom0less hwdom case (1:1) memory:
>>>> create_domUs
>>>> |-construct_domU
>>>>    |-construct_hwdom()
>>>>      |-allocate_memory_11()
>>>>
>>>> And allocate_memory_11() uses "dom0_mem" as:
>>>> min_low_order =
>>>>    get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128)));
>>>>
>>>> In case of dom0less boot the "dom0_mem" is not used and defaulted to 0,
>>>
>>>  From docs/mics/xen-command-linux.pandoc:
>>>
>>> ---
>>>
>>> ### dom0_mem (ARM)
>>>  > `= `
>>>
>>> Set the amount of memory for the initial domain (dom0). It must be
>>> greater than zero. This parameter is required.
>>>
>>> ---
>>>
>>> If dom0_mem is effectively optional, then shouldn't the doc be updated?
>>
>> No. I think doc is correct because when regular Dom0(hwdom)(initial domain)
>> is created code goes through regular Dom0 path and "dom0_mem" is accounted for.
> 
> I understand this is used when dom0 is not described in the device tree.
> The crucial part in your sentence is "when", to me this indicates a condition. Whereas the current wording in xen-command-linux is using "required" with no condition. So a reader can rightfully think the parameter is also used in dom0less and have to be specified.
> 
> So I think the wording needs to be tweaked to something like "This parameter is required (and only used) when the initial domain is not described in the Device-Tree."

Got it.

> 
> Although, "required" might still be too strict because it looks like we would provide a configuration for dom0_mem if it is not set.

Correct - it will be defaulted to MB(512) if not configured + log notification "PLEASE SPECIFY dom0_mem PARAMETER - USING 512M FOR NOW\n"

Thank you.

-- 
Best regards,
-grygorii



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Date: Wed, 6 Aug 2025 17:20:51 +0300
User-Agent: Mozilla Thunderbird
Subject: Re: Consider changing CONFIG_ACPI default on ARM?
To: Elliott Mitchell , Paul Leiber 
Cc: xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 
 
Content-Language: en-US
From: Grygorii Strashko 
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On 06.08.25 07:30, Elliott Mitchell wrote:
> Sigh, resending as I lost some of the intended Cc targets when originally
> creating the message.  Sorry about the duplication for people who have
> already seen, but I thought this might be worthy of wider discussion.
> 
> 
> 
> I would like to draw the attention of a few people on xen-devel to the
> thread which occured on xen-users recently and quoted below:
> 
> https://lists.xenproject.org/archives/html/xen-users/2025-07/msg00001.html
> 
> On Tue, Jul 01, 2025 at 10:01:13PM +0200, Paul Leiber wrote:
>>
>> Unfortunately, I don't have a direct answer to the question (as is so often
>> the case, due to my limited knowledge and experience). However, I am
>> successfully running Xen on a RPi 4 (mostly, except for some VLAN related
>> networking issues).
>>
>> I used instructions in [1] to install vanilla Debian on the RPi, including
>> UEFI boot and grub. I then compiled Xen with expert options and ACPI
>> enabled.
>>
>> I don't know if there are better solutions. For example, I suffer from the
>> fact that I2C doesn't work when using UEFI boot on a RPi. Nowadays, Debian
>> provides their own vanilla Debian images for RPi and with working I2C, but
>> these images are using a different boot method that I didn't know how to use
>> with Xen.  So far, the procedure described above seems to be the easiest
>> solution for me.
> 
> 
>> [1] https://forums.raspberrypi.com/viewtopic.php?t=282839
>>
>> Am 30.06.2025 um 12:35 schrieb Sumit Semwal:
>>>
>>> I've just begun to experiment with the Raspberry Pi 5, trying to run a
>>> simple xen + Dom0 setup, using uBoot, and the bookworm based Rpi
>>> distro.
>>>
>>> I've tried combinations of the following setup:
>>>
>>> 1. prebuilt Rpi5 kernel + dtbs, and have also tried to build them from
>>> source [1]
>>> 2. Xen from upstream [2] and xen-troops [3]
>>> 3. upstream uBoot from [4]
>>>
>>> but with the same result: [short log below; I can provide a fuller log
>>> if needed]
>>>
>>> (XEN) DT: ** translation for device /axi/msi-controller@1000130000 **
>>> (XEN) DT: bus is default (na=2, ns=2) on /axi
>>> (XEN) DT: translating address:<3> 000000ff<3> fffff000<3>
>>> (XEN) DT: parent bus is default (na=2, ns=1) on /
>>> (XEN) DT: walking ranges...
>>> (XEN) DT: default map, cp=0, s=1000000000, da=fffffff000
>>> (XEN) DT: default map, cp=1000000000, s=100000000, da=fffffff000
>>> (XEN) DT: default map, cp=1400000000, s=400000000, da=fffffff000
>>> (XEN) DT: default map, cp=1800000000, s=400000000, da=fffffff000
>>> (XEN) DT: default map, cp=1c00000000, s=400000000, da=fffffff000
>>> (XEN) DT: not found !
>>> (XEN) Unable to retrieve address 1 for /axi/msi-controller@1000130000
>>> (XEN) Device tree generation failed (-22).
>>> (XEN) debugtrace_dump() global buffer starting
>>> 1 cpupool_create(pool=0,sched=6)
>>> 2 Created cpupool 0 with scheduler SMP Credit Scheduler rev2 (credit2)
>>> 3 cpupool_add_domain(dom=0,pool=0) n_dom 1 rc 0
>>> (XEN) wrap: 0
>>> (XEN) debugtrace_dump() global buffer finished
>>> (XEN)
>>> (XEN) ****************************************
>>> (XEN) Panic on CPU 0:
>>> (XEN) Could not set up DOM0 guest OS (rc = -22)
>>> (XEN) ****************************************
>>>
>>>
>>> I'm certain I'm missing something, but before I delve deeper, I just
>>> wanted to ask if this is a known issue, and if so, are there any
>>> workarounds or solutions available for this?
>>>
>>> Any help about this is highly appreciated!
>>>
>>> Thanks and Best regards,
>>> Sumit.
>>>
>>> [1]:  https://github.com/raspberrypi/linux rpi-6.12.y branch
>>> [2]: git://xenbits.xen.org/xen.git - main branch
>>> [3] xen-troops https://github.com/xen-troops/xen - rpi5_dev branch
>>> [4]: https://github.com/u-boot/u-boot.git master branch
> 
> Ultimately Debian is choosing to leave most defaults alone.  So far the
> Xen developers have left CONFIG_ACPI defaulting to off on ARM*.  The
> Debian project doesn't have paid people to support Raspberry PI hardware,
> despite being rather common.  As a result there aren't any official
> Raspberry PI images, but people associated with Tianocore have gotten
> generic images to boot on Raspberry PI hardware.
> 
> I'm unsure of the likelihood of getting the Debian maintainers to
> override the default.  Yet due being by far the simplest way to install
> Debian and Xen on a very common ARM64 platform, perhaps the Xen
> developers should consider changing?

Information about our experiments with RPI5 can be found in [1]
and demonstration project [2].

Seen no issues (except no IOMMU as platform is closed and no docs/support).

[1] https://github.com/xen-troops/meta-xt-rpi5/wiki
[2] https://github.com/xen-troops/meta-xt-prod-devel-rpi5

-- 
Best regards,
-grygorii



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Date: Wed, 6 Aug 2025 16:24:52 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-3-dmukhin@ford.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
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In-Reply-To: <20250731192130.3948419-3-dmukhin@ford.com>

On Thu, Jul 31, 2025 at 07:21:49PM +0000, dmkhn@proton.me wrote:
> From: Denis Mukhin  
> 
> Introduce a driver framework to abstract UART emulators in the hypervisor.
> 
> That allows for architecture-independent handling of virtual UARTs in the
> console driver and simplifies enabling new UART emulators.
> 
> The framework is built under CONFIG_HAS_VUART, which will be automatically
> enabled once the user enables any UART emulator.
> 
> Current implementation supports maximum of one vUART of each kind per domain.
> 
> Use new domain_has_vuart() in the console driver code to check whether to
> forward console input to the domain using vUART.
> 
> Note: existing vUARTs are deliberately *not* hooked to the new framework to
> minimize the scope of the patch: vpl011 (i.e. SBSA) emulator and "vuart" (i.e.
> minimalistic MMIO-mapped dtuart for hwdoms on Arm) are kept unmodified.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v3:
> - new patch
> - original patch from ML: https://lore.kernel.org/xen-devel/20250624035443.344099-16-dmukhin@ford.com/
> ---
>  xen/arch/arm/xen.lds.S         |   1 +
>  xen/arch/ppc/xen.lds.S         |   1 +
>  xen/arch/riscv/xen.lds.S       |   1 +
>  xen/arch/x86/xen.lds.S         |   1 +
>  xen/common/Kconfig             |   2 +
>  xen/common/Makefile            |   1 +
>  xen/common/emul/Kconfig        |   6 ++
>  xen/common/emul/Makefile       |   1 +
>  xen/common/emul/vuart/Kconfig  |   6 ++
>  xen/common/emul/vuart/Makefile |   1 +
>  xen/common/emul/vuart/vuart.c  | 112 +++++++++++++++++++++++++++++++++
>  xen/common/keyhandler.c        |   3 +
>  xen/drivers/char/console.c     |   4 ++
>  xen/include/xen/vuart.h        |  84 +++++++++++++++++++++++++
>  xen/include/xen/xen.lds.h      |  10 +++
>  15 files changed, 234 insertions(+)
>  create mode 100644 xen/common/emul/Kconfig
>  create mode 100644 xen/common/emul/Makefile
>  create mode 100644 xen/common/emul/vuart/Kconfig
>  create mode 100644 xen/common/emul/vuart/Makefile
>  create mode 100644 xen/common/emul/vuart/vuart.c
>  create mode 100644 xen/include/xen/vuart.h
> 
> diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S
> index 9f30c3a13ed1..bdba7eaa4f65 100644
> --- a/xen/arch/arm/xen.lds.S
> +++ b/xen/arch/arm/xen.lds.S
> @@ -58,6 +58,7 @@ SECTIONS
>         *(.rodata)
>         *(.rodata.*)
>         VPCI_ARRAY
> +       VUART_ARRAY
>         *(.data.rel.ro)
>         *(.data.rel.ro.*)
>  
> diff --git a/xen/arch/ppc/xen.lds.S b/xen/arch/ppc/xen.lds.S
> index 1de0b77fc6b9..f9d4e5b0dcd8 100644
> --- a/xen/arch/ppc/xen.lds.S
> +++ b/xen/arch/ppc/xen.lds.S
> @@ -52,6 +52,7 @@ SECTIONS
>          *(.rodata)
>          *(.rodata.*)
>          VPCI_ARRAY
> +        VUART_ARRAY
>          *(.data.rel.ro)
>          *(.data.rel.ro.*)
>  
> diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S
> index edcadff90bfe..59dcaa5fef9a 100644
> --- a/xen/arch/riscv/xen.lds.S
> +++ b/xen/arch/riscv/xen.lds.S
> @@ -47,6 +47,7 @@ SECTIONS
>          *(.rodata)
>          *(.rodata.*)
>          VPCI_ARRAY
> +        VUART_ARRAY
>          *(.data.rel.ro)
>          *(.data.rel.ro.*)
>  
> diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S
> index 8e9cac75b09e..43426df33092 100644
> --- a/xen/arch/x86/xen.lds.S
> +++ b/xen/arch/x86/xen.lds.S
> @@ -136,6 +136,7 @@ SECTIONS
>         *(.rodata)
>         *(.rodata.*)
>         VPCI_ARRAY
> +       VUART_ARRAY
>         *(.data.rel.ro)
>         *(.data.rel.ro.*)
>  
> diff --git a/xen/common/Kconfig b/xen/common/Kconfig
> index 16936418a6e6..4e0bd524dc43 100644
> --- a/xen/common/Kconfig
> +++ b/xen/common/Kconfig
> @@ -1,6 +1,8 @@
>  
>  menu "Common Features"
>  
> +source "common/emul/Kconfig"
> +
>  config COMPAT
>  	bool
>  	help
> diff --git a/xen/common/Makefile b/xen/common/Makefile
> index c316957fcb36..c0734480ee4b 100644
> --- a/xen/common/Makefile
> +++ b/xen/common/Makefile
> @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o
>  obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/
>  obj-$(CONFIG_IOREQ_SERVER) += dm.o
>  obj-y += domain.o
> +obj-y += emul/
>  obj-y += event_2l.o
>  obj-y += event_channel.o
>  obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o
> diff --git a/xen/common/emul/Kconfig b/xen/common/emul/Kconfig
> new file mode 100644
> index 000000000000..7c6764d1756b
> --- /dev/null
> +++ b/xen/common/emul/Kconfig
> @@ -0,0 +1,6 @@
> +menu "Domain Emulation Features"
> +	visible if EXPERT
> +
> +source "common/emul/vuart/Kconfig"
> +
> +endmenu
> diff --git a/xen/common/emul/Makefile b/xen/common/emul/Makefile
> new file mode 100644
> index 000000000000..670682102c13
> --- /dev/null
> +++ b/xen/common/emul/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_HAS_VUART) += vuart/
> diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kconfig
> new file mode 100644
> index 000000000000..02f7dd6dc1a1
> --- /dev/null
> +++ b/xen/common/emul/vuart/Kconfig
> @@ -0,0 +1,6 @@
> +config HAS_VUART
> +	bool
> +
> +menu "UART Emulation"
> +
> +endmenu
> diff --git a/xen/common/emul/vuart/Makefile b/xen/common/emul/vuart/Makefile
> new file mode 100644
> index 000000000000..c6400b001e85
> --- /dev/null
> +++ b/xen/common/emul/vuart/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_HAS_VUART) += vuart.o
> diff --git a/xen/common/emul/vuart/vuart.c b/xen/common/emul/vuart/vuart.c
> new file mode 100644
> index 000000000000..14a7f8bd8b79
> --- /dev/null
> +++ b/xen/common/emul/vuart/vuart.c
> @@ -0,0 +1,112 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UART emulator framework.
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +#define VUART_ARRAY_SIZE    (__start_vuart_end - __start_vuart_array)
> +
> +#define for_each_vuart(vdev) \
> +    for (unsigned __i = 0; \
> +         __i < VUART_ARRAY_SIZE && (vdev = __start_vuart_array[__i], 1); \
> +         __i++)

Could you possibly do:

#define for_each_vuart(vdev) \
    for ( vdev = __start_vuart_array; vdev < __start_vuart_end: vdev++ )

To avoid the extra __i variable in the inner scope?

> +
> +extern const struct vuart_ops *const __start_vuart_array[];
> +extern const struct vuart_ops *const __start_vuart_end[];

Naming here looks weird, why not __vuart_{start,end}?  Or
__{start,end}_vuart_array.

> +
> +int vuart_add_node(struct domain *d, const void *node)

What's the purpose of this function?  There's no comment here or in
the declaration to figure out what's the purpose.  It's also not being
called, which makes it unreachable code.  MISRA will likely complain
about it?

> +{
> +    const struct vuart_ops *vdev;
> +    int rc;
> +
> +    for_each_vuart(vdev)
> +    {
> +        if ( !vdev->add_node )
> +            continue;
> +
> +        rc = vdev->add_node(d, node);
> +        if ( rc )
> +            return rc;
> +    }
> +
> +    return 0;
> +}
> +
> +int vuart_init(struct domain *d, struct vuart_params *params)
> +{
> +    const struct vuart_ops *vdev;
> +    int rc;
> +
> +    if ( !domain_has_vuart(d) )
> +        return 0;

Don't you need the domain_has_vuart() checks in all the handlers?
Otherwise you are pointlessly iterating and calling handlers that
won't do anything?

> +
> +    for_each_vuart(vdev)
> +    {
> +        rc = vdev->init(d, params);
> +        if ( rc )
> +            return rc;
> +    }
> +
> +    d->console.input_allowed = true;
> +
> +    return 0;
> +}
> +
> +/*
> + * Release any resources taken by UART emulators.
> + *
> + * NB: no flags are cleared, since currently exit() is called only during
> + * domain destroy.
> + */
> +void vuart_deinit(struct domain *d)
> +{
> +    const struct vuart_ops *vdev;
> +
> +    for_each_vuart(vdev)
> +        vdev->deinit(d);
> +}
> +
> +void vuart_dump_state(const struct domain *d)
> +{
> +    const struct vuart_ops *vdev;
> +
> +    for_each_vuart(vdev)
> +        vdev->dump_state(d);
> +}
> +
> +/*
> + * Put character to the first suitable emulated UART's FIFO.
> + */
> +int vuart_put_rx(struct domain *d, char c)
> +{
> +    const struct vuart_ops *vdev = NULL;
> +
> +    ASSERT(domain_has_vuart(d));
> +
> +    for_each_vuart(vdev)
> +        if ( vdev->put_rx )
> +            break;
> +
> +    return vdev ? vdev->put_rx(d, c) : -ENODEV;

The above functions seems to be designed to deal with multiple vUARTs
in-use by the same domain, while the put_rx code gives up as soon as
it finds an implementation that has the ->put_rx() hook set.

> +}
> +
> +bool domain_has_vuart(const struct domain *d)
> +{
> +    uint32_t mask = 0;
> +
> +    return !!(d->emulation_flags & mask);
> +}
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/common/keyhandler.c b/xen/common/keyhandler.c
> index eccd97c565c6..af427d25dc0d 100644
> --- a/xen/common/keyhandler.c
> +++ b/xen/common/keyhandler.c
> @@ -22,6 +22,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  static unsigned char keypress_key;
> @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char key)
>                             v->periodic_period / 1000000);
>              }
>          }
> +
> +        vuart_dump_state(d);
>      }
>  
>      for_each_domain ( d )
> diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c
> index 963c7b043cd8..93254979817b 100644
> --- a/xen/drivers/char/console.c
> +++ b/xen/drivers/char/console.c
> @@ -33,6 +33,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #ifdef CONFIG_X86
>  #include 
> @@ -601,6 +602,7 @@ static void __serial_rx(char c)
>          /*
>           * Deliver input to the hardware domain buffer, unless it is
>           * already full.
> +         * NB: must be the first check: hardware domain may have emulated UART.
>           */
>          if ( (serial_rx_prod - serial_rx_cons) != SERIAL_RX_SIZE )
>              serial_rx_ring[SERIAL_RX_MASK(serial_rx_prod++)] = c;
> @@ -611,6 +613,8 @@ static void __serial_rx(char c)
>           */
>          send_global_virq(VIRQ_CONSOLE);
>      }
> +    else if ( domain_has_vuart(d) )
> +        rc = vuart_put_rx(d, c);
>  #ifdef CONFIG_SBSA_VUART_CONSOLE
>      else
>          /* Deliver input to the emulated UART. */
> diff --git a/xen/include/xen/vuart.h b/xen/include/xen/vuart.h
> new file mode 100644
> index 000000000000..e843026df4b1
> --- /dev/null
> +++ b/xen/include/xen/vuart.h
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UART emulator framework.
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#ifndef XEN_VUART_H
> +#define XEN_VUART_H
> +
> +#include 
> +#include 
> +#include 
> +
> +struct vuart_params {
> +    domid_t console_domid;
> +    gfn_t gfn;
> +    evtchn_port_t evtchn;

I think this should be empty initially, as there's no implementation
that uses the hooks it's completely opaque to me what should be placed
in vuart_params.

> +};
> +
> +struct vuart_ops {
> +    int (*add_node)(struct domain *d, const void *node);
> +    int (*init)(struct domain *d, struct vuart_params *params);
> +    void (*deinit)(struct domain *d);
> +    void (*dump_state)(const struct domain *d);
> +    int (*put_rx)(struct domain *d, char c);

We haven't been very good at this, but ideally hooks should be
documented as to which task they are expected to perform, so that
future implementations have some initial help in understanding how
this is supposed to work.

> +};
> +
> +#define VUART_REGISTER(name, x) \
> +    static const struct vuart_ops *const __name##_entry \
> +        __used_section(".data.vuart." #name) = (x);

For vPCI we are moving this to a different section, I think you want
to use ".data.rel.ro.vuart" here.

Thanks, Roger.


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On 2025-08-06 09:58, Stewart Hildebrand wrote:
> On 7/26/25 05:23, Julien Grall wrote:
>> Hi,
>>
>> On 25/07/2025 15:01, Stewart Hildebrand wrote:
>>> From: Stefano Stabellini 
>>>
>>> Up until f9f6b22abf1d "xen/arm: Map ITS doorbell register to IOMMU page
>>> tables" the only caller of iommu_map on ARM was grant_table.c which has
>>> a specific usage model and restrictions as described by the in-code
>>> comment in arm_iommu_map_page.
>>>
>>> f9f6b22abf1d introduced a second caller to iommu_map on ARM:
>>> vgic_v3_its_init_virtual. This specific statement in the
>>> f9f6b22abf1d commit message is partially wrong:
>>>
>>> "Note that the 1:1 check in arm_iommu_map_page remains for now, as
>>> virtual ITSes are currently only created for hwdom where the doorbell
>>> mapping is always 1:1."
>>>
>>> Leading to crashes any time the hardware domain is not direct-mapped
>>> (e.g. cache coloring and non-Dom0 hardware domain):
>>>
>>> (XEN) Xen BUG at drivers/passthrough/arm/iommu_helpers.c:47
>>> [...]
>>> (XEN) Xen call trace:
>>> (XEN)    [<00000a000024c758>] arm_iommu_map_page+0x80/0x90 (PC)
>>> (XEN)    [<00000a000024c750>] arm_iommu_map_page+0x78/0x90 (LR)
>>> (XEN)    [<00000a0000250884>] iommu_map+0xcc/0x29c
>>> (XEN)    [<00000a0000288024>] vgic_v3_its_init_domain+0x18c/0x1e8
>>> (XEN)    [<00000a0000285228>] vgic-v3.c#vgic_v3_domain_init+0x168/0x21c
>>> (XEN)    [<00000a0000281dcc>] domain_vgic_init+0x14c/0x210
>>> (XEN)    [<00000a00002705a4>] arch_domain_create+0x150/0x1f0
>>> (XEN)    [<00000a00002055e8>] domain_create+0x47c/0x6c0
>>> (XEN)    [<00000a00002cf090>] create_domUs+0x7f8/0x8cc
>>> (XEN)    [<00000a00002eb588>] start_xen+0x8f4/0x998
>>> (XEN)    [<00000a000020018c>] head.o#primary_switched+0x4/0x10
>>>
>>> Specifically, non-1:1 hardware domain exists with cache coloring
>>> enabled. For that, is_domain_direct_mapped(d) is false but
>>> domain_use_host_layout(d) is true.
>>>
>>> Change the is_domain_direct_mapped(d) checks in arm_iommu_map_page and
>>> arm_iommu_unmap_page into domain_use_host_layout(d) checks.
>>>
>>> Drop stale in-code comment specific to grant table mappings.
>>>
>>> Fixes: f9f6b22abf1d ("xen/arm: Map ITS doorbell register to IOMMU page tables")
>>> Signed-off-by: Stefano Stabellini 
>>> Signed-off-by: Stewart Hildebrand 
>>
>> Reviewed-by: Julien Grall 
> 
> Thanks for the review! Is this ready to be committed?

Tested-by: Jason Andryuk 

Thanks,
Jason


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Date: Wed, 6 Aug 2025 10:31:20 -0400
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Subject: Re: [PATCH v5 2/2] xen/arm: allow translated iommu mappings
To: Julien Grall , Stewart Hildebrand
	, 
CC: Stefano Stabellini , Stefano Stabellini
	, Bertrand Marquis ,
	"Michal Orzel" , Volodymyr Babchuk
	
References: <20250725140130.4008-1-stewart.hildebrand@amd.com>
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On 2025-07-26 05:23, Julien Grall wrote:
> Hi,
> 
> On 25/07/2025 15:01, Stewart Hildebrand wrote:
>> From: Stefano Stabellini 
>>
>> In preparation of exposing vITS to domUs, generalize arm_iommu_map_page
>> and arm_iommu_unmap_page to allow ITS doorbell mappings with dfn != mfn.
>>
>> The mfn does not need to be passed to guest_physmap_remove_page since
>> there is no mfn checking on the p2m_iommu_map_{rw,ro} p2m types during
>> unmap. Pass INVALID_MFN to guest_physmap_remove_page.
>>
>> Signed-off-by: Stefano Stabellini 
>> Signed-off-by: Stewart Hildebrand 
> 
> Reviewed-by: Julien Grall 

Tested-by: Jason Andryuk 

Thanks,
Jason


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Date: Wed, 6 Aug 2025 16:37:23 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 3/8] x86/domain: allocate d->{iomem,irq}_caps before
 arch-specific initialization
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-4-dmukhin@ford.com>
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In-Reply-To: <20250731192130.3948419-4-dmukhin@ford.com>

On Thu, Jul 31, 2025 at 07:21:54PM +0000, dmkhn@proton.me wrote:
> From: Denis Mukhin  
> 
> Move IRQ/IOMEM rangesets allocation before arch_domain_create().
> 
> That guarantees that arch-specific code could access those rangesets to
> register traps for emulation.
> 
> It is necessary for those emulators registering trap handlers and ensuring
> that emulated IRQs are not shared with the physical IRQs.
> 
> Move dom0_setup_permissions() call right after I/O rangesets are allocated.
> 
> Move pvh_setup_mmcfg() inside dom0_setup_permissions() close to the place
> where MMCFG ranges are initialized.

I'm a bit puzzled by this, you don't need I/O permission to setup
traps.  You can setup traps everywhere, the I/O rangesets control
whether a domain can access the physical resource, not whether
accesses can be emulated.

The dependency between MMCFG registration (pvh_setup_mmcfg()) and
calling dom0_setup_permissions() is because the later consumes the
MMCFG ranges added by the former to mark them as not accessible by
a PVH dom0.

I think you don't need this for vUARTS, as the ports are know at build
time, and hence you can block access to them without requiring the
actual vUART to be initialized.

Thanks, Roger.


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According to the Arm SMMUv3 spec (ARM IHI 0070), a system may have
SMMU(s) that is/are non-coherent to the PE (processing element). In such
cases, memory accesses from the PE should be either non-cached or be
augmented with manual cache maintenance. SMMU cache coherency is reported
by bit 4 (COHACC) of the SMMU_IDR0 register and is already present in the
Xen driver. However, the current implementation is not aware of cache
maintenance for memory that is shared between the PE and non-coherent
SMMUs. It contains dmam_alloc_coherent() function, that is added during
Linux driver porting. But it is actually a wrapper for _xzalloc(), that
returns normal writeback memory (which is OK for coherent SMMUs).

During Xen bring-up on a system with non-coherent SMMUs, the driver did
not work properly - the SMMU was not functional and halted initialization
at the very beginning due to a timeout while waiting for CMD_SYNC
completion:

  (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
  (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout

To properly handle such scenarios, add the non_coherent flag to the
arm_smmu_queue struct. It is initialized using features reported by the
SMMU HW and will be used for triggering cache clean/invalidate operations.
This flag is not queue-specific (it is applicable to the whole SMMU), but
adding it to arm_smmu_queue allows us to not change function signatures
and simplify the patch (smmu->features, which contains the required flag,
are not available in code parts that require cache maintenance).

Signed-off-by: Dmytro Firsov 
---
 xen/drivers/passthrough/arm/smmu-v3.c | 27 +++++++++++++++++++++++----
 xen/drivers/passthrough/arm/smmu-v3.h |  7 +++++++
 2 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug=
h/arm/smmu-v3.c
index 5e9e3e048e..bf153227db 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.c
+++ b/xen/drivers/passthrough/arm/smmu-v3.c
@@ -346,10 +346,14 @@ static void queue_write(__le64 *dst, u64 *src, size_t=
 n_dwords)
=20
 static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent)
 {
+	__le64 *q_addr =3D Q_ENT(q, q->llq.prod);
+
 	if (queue_full(&q->llq))
 		return -ENOSPC;
=20
-	queue_write(Q_ENT(q, q->llq.prod), ent, q->ent_dwords);
+	queue_write(q_addr, ent, q->ent_dwords);
+	if (q->non_coherent)
+		clean_dcache_va_range(q_addr, q->ent_dwords * sizeof(*q_addr));
 	queue_inc_prod(&q->llq);
 	queue_sync_prod_out(q);
 	return 0;
@@ -365,10 +369,15 @@ static void queue_read(u64 *dst, __le64 *src, size_t =
n_dwords)
=20
 static int queue_remove_raw(struct arm_smmu_queue *q, u64 *ent)
 {
+	__le64 *q_addr =3D Q_ENT(q, q->llq.cons);
+
 	if (queue_empty(&q->llq))
 		return -EAGAIN;
=20
-	queue_read(ent, Q_ENT(q, q->llq.cons), q->ent_dwords);
+	if (q->non_coherent)
+		invalidate_dcache_va_range(q_addr, q->ent_dwords * sizeof(*q_addr));
+
+	queue_read(ent, q_addr, q->ent_dwords);
 	queue_inc_cons(&q->llq);
 	queue_sync_cons_out(q);
 	return 0;
@@ -463,6 +472,7 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_devi=
ce *smmu)
 	struct arm_smmu_queue *q =3D &smmu->cmdq.q;
 	u32 cons =3D readl_relaxed(q->cons_reg);
 	u32 idx =3D FIELD_GET(CMDQ_CONS_ERR, cons);
+	__le64 *q_addr =3D Q_ENT(q, cons);
 	struct arm_smmu_cmdq_ent cmd_sync =3D {
 		.opcode =3D CMDQ_OP_CMD_SYNC,
 	};
@@ -489,11 +499,14 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_de=
vice *smmu)
 		break;
 	}
=20
+	if (q->non_coherent)
+		invalidate_dcache_va_range(q_addr, q->ent_dwords * sizeof(*q_addr));
+
 	/*
 	 * We may have concurrent producers, so we need to be careful
 	 * not to touch any of the shadow cmdq state.
 	 */
-	queue_read(cmd, Q_ENT(q, cons), q->ent_dwords);
+	queue_read(cmd, q_addr, q->ent_dwords);
 	dev_err(smmu->dev, "skipping command in error state:\n");
 	for (i =3D 0; i < ARRAY_SIZE(cmd); ++i)
 		dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]);
@@ -504,7 +517,10 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_dev=
ice *smmu)
 		return;
 	}
=20
-	queue_write(Q_ENT(q, cons), cmd, q->ent_dwords);
+	queue_write(q_addr, cmd, q->ent_dwords);
+
+	if (q->non_coherent)
+		clean_dcache_va_range(q_addr, q->ent_dwords * sizeof(*q_addr));
 }
=20
 static void arm_smmu_cmdq_insert_cmd(struct arm_smmu_device *smmu, u64 *cm=
d)
@@ -1634,6 +1650,9 @@ static int __init arm_smmu_init_one_queue(struct arm_=
smmu_device *smmu,
 	q->q_base |=3D FIELD_PREP(Q_BASE_LOG2SIZE, q->llq.max_n_shift);
=20
 	q->llq.prod =3D q->llq.cons =3D 0;
+
+	q->non_coherent =3D !(smmu->features & ARM_SMMU_FEAT_COHERENCY);
+
 	return 0;
 }
=20
diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug=
h/arm/smmu-v3.h
index f09048812c..db936b9bd4 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.h
+++ b/xen/drivers/passthrough/arm/smmu-v3.h
@@ -522,6 +522,13 @@ struct arm_smmu_queue {
=20
 	u32 __iomem			*prod_reg;
 	u32 __iomem			*cons_reg;
+
+	/*
+	 * According to SMMU spec section 3.16, some systems may have
+	 * SMMUs, that are non-coherent to PE (processing elements).
+	 * In such case manual cache management is needed.
+	 */
+	bool				non_coherent;
 };
=20
 struct arm_smmu_cmdq {
--=20
2.50.1


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Date: Wed, 6 Aug 2025 17:06:24 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 5/8] emul/vuart-ns16550: introduce NS16550-compatible
 UART emulator (x86)
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-6-dmukhin@ford.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Disposition: inline
In-Reply-To: <20250731192130.3948419-6-dmukhin@ford.com>

On Thu, Jul 31, 2025 at 07:22:06PM +0000, dmkhn@proton.me wrote:
> From: Denis Mukhin  
> 
> Add initial in-hypervisor emulator for NS8250/NS16x50-compatible UARTs under
> CONFIG_VUART_NS16550 for x86 port of Xen.
> 
> x86 port of Xen lacks vUART facility similar to Arm's SBSA emulator to support
> x86 guest OS bring up in the embedded setups.
> 
> In parallel domain creation scenario (hyperlaunch), NS16550 emulator helps
> early guest firmware and/or OS bringup debugging, because it eliminates
> dependency on the external emulator (qemu) being operational by the time
> domains are created.
> 
> The emulator also allows to forward the physical console input to the x86
> domain which is useful when a system has only one physical UART for early
> debugging and this UART is owned by Xen. Such functionality is limited to dom0
> use currently.
> 
> By default, CONFIG_VUART_NS16550 enables emulation of NS16550 at I/O port
> 0x3f8, IRQ#4 in guest OS (legacy COM1).
> 
> Legacy COM resources can be selected at built-time and cannot be configured
> per-domain via .cfg or DT yet.
> 
> Introduce new emulation flag for virtual UART on x86 and plumb it through
> domain creation code so NS16550 emulator can be instantiated properly.
> 
> Please refer to the NS16550 emulator code for full list of limitations.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v3:
> - feedback addressed
> - adjusted to new vUART framework APIs
> - Link to v3: https://lore.kernel.org/xen-devel/20250103-vuart-ns8250-v3-v1-21-c5d36b31d66c@ford.com/
> ---
>  xen/arch/x86/hvm/hvm.c                |    9 +
>  xen/arch/x86/include/asm/domain.h     |    4 +-
>  xen/arch/x86/include/asm/hvm/domain.h |    4 +
>  xen/common/emul/vuart/Kconfig         |   48 ++
>  xen/common/emul/vuart/Makefile        |    1 +
>  xen/common/emul/vuart/vuart-ns16550.c | 1009 +++++++++++++++++++++++++
>  xen/common/emul/vuart/vuart.c         |    4 +
>  xen/include/public/arch-x86/xen.h     |    4 +-
>  xen/include/xen/resource.h            |    3 +
>  9 files changed, 1084 insertions(+), 2 deletions(-)
>  create mode 100644 xen/common/emul/vuart/vuart-ns16550.c
> 
> diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
> index b7edb1d6555d..1156e7ebcc4c 100644
> --- a/xen/arch/x86/hvm/hvm.c
> +++ b/xen/arch/x86/hvm/hvm.c
> @@ -31,6 +31,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -702,6 +703,10 @@ int hvm_domain_initialise(struct domain *d,
>      if ( rc != 0 )
>          goto fail1;
>  
> +    rc = vuart_init(d, NULL);
> +    if ( rc != 0 )
> +        goto out_vioapic_deinit;
> +
>      stdvga_init(d);
>  
>      rtc_init(d);
> @@ -725,6 +730,8 @@ int hvm_domain_initialise(struct domain *d,
>      return 0;
>  
>   fail2:
> +    vuart_deinit(d);
> + out_vioapic_deinit:
>      vioapic_deinit(d);
>   fail1:
>      if ( is_hardware_domain(d) )
> @@ -787,6 +794,8 @@ void hvm_domain_destroy(struct domain *d)
>      if ( hvm_funcs.domain_destroy )
>          alternative_vcall(hvm_funcs.domain_destroy, d);
>  
> +    vuart_deinit(d);
> +
>      vioapic_deinit(d);
>  
>      XFREE(d->arch.hvm.pl_time);
> diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h
> index eafd5cfc903d..1ecc7c2cae32 100644
> --- a/xen/arch/x86/include/asm/domain.h
> +++ b/xen/arch/x86/include/asm/domain.h
> @@ -468,6 +468,7 @@ struct arch_domain
>  #define X86_EMU_IOMMU    XEN_X86_EMU_IOMMU
>  #define X86_EMU_USE_PIRQ XEN_X86_EMU_USE_PIRQ
>  #define X86_EMU_VPCI     XEN_X86_EMU_VPCI
> +#define X86_EMU_NS16550  XEN_X86_EMU_NS16550
>  #else
>  #define X86_EMU_LAPIC    0
>  #define X86_EMU_HPET     0
> @@ -479,6 +480,7 @@ struct arch_domain
>  #define X86_EMU_IOMMU    0
>  #define X86_EMU_USE_PIRQ 0
>  #define X86_EMU_VPCI     0
> +#define X86_EMU_NS16550  0
>  #endif
>  
>  #define X86_EMU_PIT     XEN_X86_EMU_PIT
> @@ -489,7 +491,7 @@ struct arch_domain
>                                   X86_EMU_IOAPIC | X86_EMU_PIC |         \
>                                   X86_EMU_VGA | X86_EMU_IOMMU |          \
>                                   X86_EMU_PIT | X86_EMU_USE_PIRQ |       \
> -                                 X86_EMU_VPCI)
> +                                 X86_EMU_VPCI | X86_EMU_NS16550)
>  
>  #define has_vlapic(d)      (!!((d)->emulation_flags & X86_EMU_LAPIC))
>  #define has_vhpet(d)       (!!((d)->emulation_flags & X86_EMU_HPET))
> diff --git a/xen/arch/x86/include/asm/hvm/domain.h b/xen/arch/x86/include/asm/hvm/domain.h
> index 333501d5f2ac..9945b16d1a6e 100644
> --- a/xen/arch/x86/include/asm/hvm/domain.h
> +++ b/xen/arch/x86/include/asm/hvm/domain.h
> @@ -149,6 +149,10 @@ struct hvm_domain {
>  #ifdef CONFIG_MEM_SHARING
>      struct mem_sharing_domain mem_sharing;
>  #endif
> +
> +#ifdef CONFIG_VUART_NS16550
> +    void *vuart; /* Virtual UART handle. */
> +#endif
>  };
>  
>  #endif /* __ASM_X86_HVM_DOMAIN_H__ */
> diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kconfig
> index 02f7dd6dc1a1..ebefd90d913e 100644
> --- a/xen/common/emul/vuart/Kconfig
> +++ b/xen/common/emul/vuart/Kconfig
> @@ -3,4 +3,52 @@ config HAS_VUART
>  
>  menu "UART Emulation"
>  
> +config VUART_NS16550
> +	bool "NS16550-compatible UART Emulation" if EXPERT
> +	depends on X86 && HVM
> +	select HAS_VUART
> +	help
> +	  In-hypervisor NS16550/NS16x50 UART emulation.
> +
> +	  Only legacy PC I/O ports are emulated.
> +
> +	  This is strictly for testing purposes (such as early HVM guest console),
> +	  and not appropriate for use in production.
> +
> +choice VUART_NS16550_PC
> +	prompt "IBM PC COM resources"
> +	depends on VUART_NS16550
> +	default VUART_NS16550_PC_COM1
> +	help
> +	  Default emulated NS16550 resources.
> +
> +config VUART_NS16550_PC_COM1
> +	bool "COM1 (I/O port 0x3f8, IRQ#4)"
> +
> +config VUART_NS16550_PC_COM2
> +	bool "COM2 (I/O port 0x2f8, IRQ#3)"
> +
> +config VUART_NS16550_PC_COM3
> +	bool "COM3 (I/O port 0x3e8, IRQ#4)"
> +
> +config VUART_NS16550_PC_COM4
> +	bool "COM4 (I/O port 0x2e8, IRQ#3)"
> +
> +endchoice

You can turn this into an index define here in Kconfig, using:

config VUART_NS16550_PC_IDX
	depends on VUART_NS16550
	int
	default 3 if VUART_NS16550_PC_COM4
	default 2 if VUART_NS16550_PC_COM3
	default 1 if VUART_NS16550_PC_COM2
	default 0

Or similar, seeing what you do with X86_PC_UART_IDX below.

> +
> +config VUART_NS16550_LOG_LEVEL
> +	int "UART emulator verbosity level"
> +	range 0 3
> +	default "1"
> +	depends on VUART_NS16550
> +	help
> +	  Set the default log level of UART emulator.
> +	  See include/xen/config.h for more details.
> +
> +config VUART_NS16550_DEBUG
> +	bool "UART emulator development debugging"
> +	depends on VUART_NS16550
> +	help
> +	  Enable development debugging.
> +
>  endmenu
> diff --git a/xen/common/emul/vuart/Makefile b/xen/common/emul/vuart/Makefile
> index c6400b001e85..85650ca5d8ce 100644
> --- a/xen/common/emul/vuart/Makefile
> +++ b/xen/common/emul/vuart/Makefile
> @@ -1 +1,2 @@
>  obj-$(CONFIG_HAS_VUART) += vuart.o
> +obj-$(CONFIG_VUART_NS16550) += vuart-ns16550.o
> diff --git a/xen/common/emul/vuart/vuart-ns16550.c b/xen/common/emul/vuart/vuart-ns16550.c
> new file mode 100644
> index 000000000000..48bbf58264fe
> --- /dev/null
> +++ b/xen/common/emul/vuart/vuart-ns16550.c
> @@ -0,0 +1,1009 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * NS16550-compatible UART Emulator.
> + *
> + * See:
> + * - Serial and UART Tutorial:
> + *     https://download.freebsd.org/doc/en/articles/serial-uart/serial-uart_en.pdf
> + * - UART w/ 16 byte FIFO:
> + *     https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
> + * - UART w/ 64 byte FIFO:
> + *     https://www.ti.com/lit/ds/symlink/tl16c750.pdf
> + *
> + * Limitations:
> + * - Only x86;
> + * - Only HVM domains support (build-time), PVH domains are not supported yet;
> + * - Only legacy COM{1,2,3,4} resources via Kconfig, custom I/O ports/IRQs
> + *   are not supported;
> + * - Only Xen console as a backend, no inter-domain communication (similar to
> + *   vpl011 on Arm);
> + * - Only 8n1 emulation (8-bit data, no parity, 1 stop bit);
> + * - No toolstack integration;
> + * - No baud rate emulation (reports 115200 baud to the guest OS);
> + * - No FIFO-less mode emulation;
> + * - No RX FIFO interrupt moderation (FCR) emulation;
> + * - No integration w/ VM snapshotting (HVM_REGISTER_SAVE_RESTORE() and
> + *   friends);
> + * - No ISA IRQ sharing allowed;
> + * - No MMIO-based UART emulation.

Listing the limitations here might not be the beast approach, this is
likely to get out of sync as it's too far away from the code
implementation.

If anything those comments want to be closer together to where the
feature would otherwise be implemented.

> + */
> +
> +#define pr_prefix               "ns16550"
> +#define pr_fmt(fmt)             pr_prefix ": " fmt
> +#define pr_log_level            CONFIG_VUART_NS16550_LOG_LEVEL
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#define pr_err(fmt, args...) do { \
> +    gprintk(KERN_ERR, pr_fmt(fmt), ## args); \
> +} while (0)
> +
> +#define pr_warn(fmt, args...) do { \
> +    if ( pr_log_level >= 1) \
> +        gprintk(KERN_WARNING, pr_fmt(fmt), ## args); \
> +} while (0)
> +
> +#define pr_info(fmt, args...) do { \
> +    if ( pr_log_level >= 2 ) \
> +        gprintk(KERN_INFO, pr_fmt(fmt), ## args); \
> +} while (0)
> +
> +#define pr_debug(fmt, args...) do { \
> +    if ( pr_log_level >= 3 ) \
> +        gprintk(KERN_DEBUG, pr_fmt(fmt), ## args); \
> +} while (0)

We would use the pr_* set of logging functions for code imported from
Linux, but for Xen code we would directly use the gprintk() functions
rather than wrap them as you do.

> +
> +#if defined(CONFIG_VUART_NS16550_PC_COM1)
> +#define X86_PC_UART_IDX         0
> +#elif defined(CONFIG_VUART_NS16550_PC_COM2)
> +#define X86_PC_UART_IDX         1
> +#elif defined(CONFIG_VUART_NS16550_PC_COM3)
> +#define X86_PC_UART_IDX         2
> +#elif defined(CONFIG_VUART_NS16550_PC_COM4)
> +#define X86_PC_UART_IDX         3
> +#else
> +#error "Unsupported I/O port"
> +#endif
> +
> +#ifdef CONFIG_VUART_NS16550_DEBUG
> +#define guest_prefix            "FROM GUEST "
> +#else
> +#define guest_prefix            ""
> +#endif
> +
> +/*
> + * Number of supported registers in the UART.
> + */
> +#define NS16550_REGS_NUM        ( UART_SCR + 1 )

Extra spaces around parentheses? (here and below)

> +
> +/*
> + * Number of emulated registers.
> + *
> + * - Emulated registers [0..NS16550_REGS_NUM] are R/W registers for DLAB=0.
> + * - DLAB=1, R/W, DLL            = NS16550_REGS_NUM + 0
> + * - DLAB=1, R/W, DLM            = NS16550_REGS_NUM + 1
> + * -         R/O, IIR (IIR_THR)  = NS16550_REGS_NUM + 2
> + */
> +#define NS16550_EMU_REGS_NUM    ( NS16550_REGS_NUM + 3 )
> +
> +/*
> + * Virtual NS16550 device state.
> + */
> +struct vuart_ns16550 {
> +    struct xencons_interface cons;      /* Emulated RX/TX FIFOs */
> +    uint8_t regs[NS16550_EMU_REGS_NUM]; /* Emulated registers */
> +    unsigned int irq;                   /* Emulated IRQ# */
> +    uint64_t io_addr;                   /* Emulated I/O region base address */
> +    uint64_t io_size;                   /* Emulated I/O region size */
> +    const char *name;                   /* Device name */
> +    struct domain *owner;               /* Owner domain */
> +    spinlock_t lock;                    /* Protection */
> +};
> +
> +/*
> + * Virtual device description.
> + */
> +struct virtdev_desc {
> +    const char *name;
> +    const struct resource *res;
> +};
> +
> +/*
> + * Legacy IBM PC NS16550 resources.
> + * There are only 4 I/O port ranges, hardcoding all of them here.
> + */
> +static const struct virtdev_desc x86_pc_uarts[4] = {
> +    [0] = {

You don't need the explicit array indexes?

> +        .name = "COM1",
> +        .res = (const struct resource[]){
> +            { .type = IORESOURCE_IO,  .addr = 0x3f8, .size = NS16550_REGS_NUM },
> +            { .type = IORESOURCE_IRQ, .addr = 4,     .size = 1 },
> +            { .type = IORESOURCE_UNKNOWN },
> +        },
> +    },
> +    [1] = {
> +        .name = "COM2",
> +        .res = (const struct resource[]){
> +            { .type = IORESOURCE_IO,  .addr = 0x2f8, .size = NS16550_REGS_NUM },
> +            { .type = IORESOURCE_IRQ, .addr = 3,     .size = 1 },
> +            { .type = IORESOURCE_UNKNOWN },
> +        },
> +    },
> +    [2] = {
> +        .name = "COM3",
> +        .res = (const struct resource[]){
> +            { .type = IORESOURCE_IO,  .addr = 0x3e8, .size = NS16550_REGS_NUM },
> +            { .type = IORESOURCE_IRQ, .addr = 4,     .size = 1 },
> +            { .type = IORESOURCE_UNKNOWN },
> +        },
> +    },
> +    [3] = {
> +        .name = "COM4",
> +        .res = (const struct resource[]){
> +            { .type = IORESOURCE_IO,  .addr = 0x2e8, .size = NS16550_REGS_NUM },
> +            { .type = IORESOURCE_IRQ, .addr = 3,     .size = 1 },
> +            { .type = IORESOURCE_UNKNOWN },
> +        },
> +    },
> +};
> +
> +static bool ns16550_fifo_rx_empty(const struct vuart_ns16550 *vdev)
> +{
> +    const struct xencons_interface *cons = &vdev->cons;
> +
> +    return cons->in_prod == cons->in_cons;
> +}
> +
> +static bool ns16550_fifo_rx_full(const struct vuart_ns16550 *vdev)
> +{
> +    const struct xencons_interface *cons = &vdev->cons;
> +
> +    return cons->in_prod - cons->in_cons == ARRAY_SIZE(cons->in);
> +}
> +
> +static void ns16550_fifo_rx_reset(struct vuart_ns16550 *vdev)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +
> +    cons->in_cons = cons->in_prod;
> +}
> +
> +static int ns16550_fifo_rx_getchar(struct vuart_ns16550 *vdev)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +    int rc;
> +
> +    if ( ns16550_fifo_rx_empty(vdev) )
> +    {
> +        pr_debug("%s: RX FIFO empty\n", vdev->name);
> +        rc = -ENODATA;
> +    }
> +    else
> +    {
> +        rc = cons->in[MASK_XENCONS_IDX(cons->in_cons, cons->in)];
> +        cons->in_cons++;
> +    }
> +
> +    return rc;
> +}
> +
> +static int ns16550_fifo_rx_putchar(struct vuart_ns16550 *vdev, char c)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +    int rc;
> +
> +    /*
> +     * FIFO-less 8250/16450 UARTs: newly arrived word overwrites the contents
> +     * of the THR.
> +     */
> +    if ( ns16550_fifo_rx_full(vdev) )
> +    {
> +        pr_debug("%s: RX FIFO full; resetting\n", vdev->name);
> +        ns16550_fifo_rx_reset(vdev);
> +        rc = -ENOSPC;
> +    }
> +    else
> +        rc = 0;
> +
> +    cons->in[MASK_XENCONS_IDX(cons->in_prod, cons->in)] = c;
> +    cons->in_prod++;
> +
> +    return rc;
> +}
> +
> +static bool ns16550_fifo_tx_empty(const struct vuart_ns16550 *vdev)
> +{
> +    const struct xencons_interface *cons = &vdev->cons;
> +
> +    return cons->out_prod == cons->out_cons;
> +}
> +
> +static void ns16550_fifo_tx_reset(struct vuart_ns16550 *vdev)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +
> +    cons->out_prod = 0;
> +    ASSERT(cons->out_cons == cons->out_prod);
> +}
> +
> +/*
> + * Flush cached output to Xen console.
> + */
> +static void ns16550_fifo_tx_flush(struct vuart_ns16550 *vdev)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +
> +    if ( ns16550_fifo_tx_empty(vdev) )
> +        return;
> +
> +    ASSERT(cons->out_prod < ARRAY_SIZE(cons->out));
> +    cons->out[cons->out_prod] = '\0';
> +    cons->out_prod++;
> +
> +    guest_printk(vdev->owner, guest_prefix "%s", cons->out);
> +
> +    ns16550_fifo_tx_reset(vdev);
> +}
> +
> +/*
> + * Accumulate guest OS output before sending to Xen console.
> + */
> +static void ns16550_fifo_tx_putchar(struct vuart_ns16550 *vdev, char ch)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +
> +    if ( !is_console_printable(ch) )
> +        return;
> +
> +    if ( ch != '\0' )
> +    {
> +        cons->out[cons->out_prod] = ch;
> +        cons->out_prod++;
> +    }
> +
> +    if ( cons->out_prod == ARRAY_SIZE(cons->out) - 1 ||
> +         ch == '\n' || ch == '\0' )
> +        ns16550_fifo_tx_flush(vdev);
> +}
> +
> +static inline uint8_t cf_check ns16550_dlab_get(const struct vuart_ns16550 *vdev)
> +{
> +    return vdev->regs[UART_LCR] & UART_LCR_DLAB ? 1 : 0;
> +}
> +
> +static bool cf_check ns16550_iir_check_lsi(const struct vuart_ns16550 *vdev)
> +{
> +    return !!(vdev->regs[UART_LSR] & UART_LSR_MASK);
> +}
> +
> +static bool cf_check ns16550_iir_check_rda(const struct vuart_ns16550 *vdev)
> +{
> +    return !ns16550_fifo_rx_empty(vdev);
> +}
> +
> +static bool cf_check ns16550_iir_check_thr(const struct vuart_ns16550 *vdev)
> +{
> +    return !!(vdev->regs[NS16550_REGS_NUM + UART_IIR] & UART_IIR_THR);
> +}
> +
> +static bool cf_check ns16550_iir_check_msi(const struct vuart_ns16550 *vdev)
> +{
> +    return !!(vdev->regs[UART_MSR] & UART_MSR_CHANGE);
> +}
> +
> +/*
> + * Get the interrupt identity reason.
> + *
> + * IIR is re-calculated once called, because NS16550 always reports high
> + * priority events first.
> + * regs[NS16550_REGS_NUM + UART_IIR] is used to store THR reason only.
> + */
> +static uint8_t ns16550_iir_get(const struct vuart_ns16550 *vdev)
> +{
> +    /*
> +     * Interrupt identity reasons by priority.
> +     * NB: high priority are at lower indexes below.
> +     */
> +    static const struct {
> +        bool (*check)(const struct vuart_ns16550 *vdev);
> +        uint8_t ier;
> +        uint8_t iir;
> +    } iir_by_prio[] = {
> +        [0] = { ns16550_iir_check_lsi, UART_IER_ELSI,   UART_IIR_LSI },
> +        [1] = { ns16550_iir_check_rda, UART_IER_ERDAI,  UART_IIR_RDA },
> +        [2] = { ns16550_iir_check_thr, UART_IER_ETHREI, UART_IIR_THR },
> +        [3] = { ns16550_iir_check_msi, UART_IER_EMSI,   UART_IIR_MSI },
> +    };
> +    const uint8_t *regs = vdev->regs;
> +    uint8_t iir = 0;
> +    unsigned int i;
> +
> +    /*
> +     * NB: every interaction w/ NS16550 registers (except DLAB=1) goes
> +     * through that call.
> +     */
> +    ASSERT(spin_is_locked(&vdev->lock));
> +
> +    for ( i = 0; i < ARRAY_SIZE(iir_by_prio); i++ )
> +    {
> +        if ( (regs[UART_IER] & iir_by_prio[i].ier) &&
> +             iir_by_prio[i].check(vdev) )
> +            break;
> +
> +    }
> +    if ( i == ARRAY_SIZE(iir_by_prio) )
> +        iir |= UART_IIR_NOINT;
> +    else
> +        iir |= iir_by_prio[i].iir;
> +
> +    if ( regs[UART_FCR] & UART_FCR_ENABLE )
> +        iir |= UART_IIR_FE;
> +
> +    return iir;
> +}
> +
> +static void ns16550_irq_assert(const struct vuart_ns16550 *vdev)
> +{
> +    struct domain *d = vdev->owner;
> +    int vector;
> +
> +    if ( has_vpic(d) ) /* HVM */
> +        vector = hvm_isa_irq_assert(d, vdev->irq, vioapic_get_vector);
> +    else
> +        ASSERT_UNREACHABLE();
> +
> +    pr_debug("%s: IRQ#%d vector %d assert\n", vdev->name, vdev->irq, vector);
> +}
> +
> +static void ns16550_irq_deassert(const struct vuart_ns16550 *vdev)
> +{
> +    struct domain *d = vdev->owner;
> +
> +    if ( has_vpic(d) ) /* HVM */
> +        hvm_isa_irq_deassert(d, vdev->irq);
> +    else
> +        ASSERT_UNREACHABLE();
> +
> +    pr_debug("%s: IRQ#%d deassert\n", vdev->name, vdev->irq);
> +}
> +
> +/*
> + * Assert/deassert virtual NS16550 interrupt line.
> + */
> +static void ns16550_irq_check(const struct vuart_ns16550 *vdev)
> +{
> +    uint8_t iir = ns16550_iir_get(vdev);
> +
> +    if ( iir & UART_IIR_NOINT )
> +        ns16550_irq_assert(vdev);
> +    else
> +        ns16550_irq_deassert(vdev);
> +
> +    pr_debug("%s: IRQ#%d IIR 0x%02x %s\n", vdev->name, vdev->irq, iir,
> +             (iir & UART_IIR_NOINT) ? "deassert" : "assert");
> +}
> +
> +/*
> + * Emulate 8-bit write access to NS16550 register.
> + */
> +static int ns16550_io_write8(
> +    struct vuart_ns16550 *vdev, uint32_t reg, uint8_t *data)
> +{
> +    uint8_t *regs = vdev->regs;
> +    uint8_t val = *data;
> +    int rc = 0;
> +
> +    if ( ns16550_dlab_get(vdev) && (reg == UART_DLL || reg == UART_DLM) )
> +        regs[NS16550_REGS_NUM + reg] = val;
> +    else
> +    {
> +        switch ( reg )
> +        {
> +        case UART_THR:
> +            if ( regs[UART_MCR] & UART_MCR_LOOP )
> +            {
> +                (void)ns16550_fifo_rx_putchar(vdev, val);
> +                regs[UART_LSR] |= UART_LSR_OE;
> +            }
> +            else
> +                ns16550_fifo_tx_putchar(vdev, val);
> +
> +            regs[NS16550_REGS_NUM + UART_IIR] |= UART_IIR_THR;
> +
> +            break;
> +
> +        case UART_IER:
> +            /*
> +             * NB: Make sure THR interrupt is re-triggered once guest OS
> +             * re-enabled ETHREI in EIR.
> +             */
> +            if ( val & regs[UART_IER] & UART_IER_ETHREI )
> +                regs[NS16550_REGS_NUM + UART_IIR] |= UART_IIR_THR;
> +
> +            regs[UART_IER] = val & UART_IER_MASK;
> +
> +            break;
> +
> +        case UART_FCR: /* WO */
> +            if ( val & UART_FCR_RESERVED0 )
> +                pr_warn("%s: FCR: attempt to set reserved bit: %x\n",
> +                        vdev->name, UART_FCR_RESERVED0);
> +
> +            if ( val & UART_FCR_RESERVED1 )
> +                pr_warn("%s: FCR: attempt to set reserved bit: %x\n",
> +                        vdev->name, UART_FCR_RESERVED1);
> +
> +            if ( val & UART_FCR_CLRX )
> +                ns16550_fifo_rx_reset(vdev);
> +
> +            if ( val & UART_FCR_CLTX )
> +                ns16550_fifo_tx_flush(vdev);
> +
> +            if ( val & UART_FCR_ENABLE )
> +                val &= UART_FCR_ENABLE | UART_FCR_DMA | UART_FCR_TRG_MASK;
> +            else
> +                val = 0;
> +
> +            regs[UART_FCR] = val;
> +
> +            break;
> +
> +        case UART_LCR:
> +            regs[UART_LCR] = val;
> +            break;
> +
> +        case UART_MCR: {
> +            uint8_t msr_curr, msr_next, msr_delta;
> +
> +            msr_curr = regs[UART_MSR];
> +            msr_next = 0;
> +            msr_delta = 0;
> +
> +            if ( val & UART_MCR_RESERVED0 )
> +                pr_warn("%s: MCR: attempt to set reserved bit: %x\n",
> +                        vdev->name, UART_MCR_RESERVED0);
> +
> +            if ( val & UART_MCR_TCRTLR )
> +                pr_warn("%s: MCR: not supported: %x\n",
> +                        vdev->name, UART_MCR_TCRTLR);
> +
> +            if ( val & UART_MCR_RESERVED1 )
> +                pr_warn("%s: MCR: attempt to set reserved bit: %x\n",
> +                        vdev->name, UART_MCR_RESERVED1);
> +
> +            /* Set modem status */
> +            if ( val & UART_MCR_LOOP )
> +            {
> +                if ( val & UART_MCR_DTR )
> +                    msr_next |= UART_MSR_DSR;
> +                if ( val & UART_MCR_RTS )
> +                    msr_next |= UART_MSR_CTS;
> +                if ( val & UART_MCR_OUT1 )
> +                    msr_next |= UART_MSR_RI;
> +                if ( val & UART_MCR_OUT2 )
> +                    msr_next |= UART_MSR_DCD;
> +            }
> +            else
> +                msr_next |= UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
> +
> +            /* Calculate changes in modem status */
> +            if ( (msr_curr & UART_MSR_CTS) ^ (msr_next & UART_MSR_CTS) )
> +                msr_delta |= UART_MSR_DCTS;
> +            if ( (msr_curr & UART_MCR_RTS) ^ (msr_next & UART_MCR_RTS) )
> +                msr_delta |= UART_MSR_DDSR;
> +            if ( (msr_curr & UART_MSR_RI)  & (msr_next & UART_MSR_RI) )
> +                msr_delta |= UART_MSR_TERI;
> +            if ( (msr_curr & UART_MSR_DCD) ^ (msr_next & UART_MSR_DCD) )
> +                msr_delta |= UART_MSR_DDCD;
> +
> +            regs[UART_MCR] = val & UART_MCR_MASK;
> +            regs[UART_MSR] = msr_next | msr_delta;
> +
> +            break;
> +        }
> +
> +        /* NB: Firmware (e.g. OVMF) may rely on SCR presence. */
> +        case UART_SCR:
> +            regs[UART_SCR] = val;
> +            break;
> +
> +        case UART_LSR: /* RO */
> +        case UART_MSR: /* RO */
> +        default:
> +            rc = -EINVAL;
> +            break;
> +        }
> +
> +        ns16550_irq_check(vdev);
> +    }
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate 16-bit write access to NS16550 register.
> + * NB: some guest OSes use outw() to access UART_DLL.
> + */
> +static int ns16550_io_write16(
> +    struct vuart_ns16550 *vdev, uint32_t reg, uint16_t *data)
> +{
> +    uint16_t val = *data;
> +    int rc;
> +
> +    if ( ns16550_dlab_get(vdev) && reg == UART_DLL )
> +    {
> +        vdev->regs[NS16550_REGS_NUM + UART_DLL] = val & 0xff;
> +        vdev->regs[NS16550_REGS_NUM + UART_DLM] = (val >> 8) & 0xff;
> +        rc = 0;
> +    }
> +    else
> +        rc = -EINVAL;
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate write access to NS16550 register.
> + */
> +static int ns16550_io_write(
> +    struct vuart_ns16550 *vdev, uint8_t reg, uint32_t size, uint32_t *data)
> +{
> +    int rc;
> +
> +    switch ( size )
> +    {
> +    case 1:
> +        rc = ns16550_io_write8(vdev, reg, (uint8_t *)data);
> +        break;
> +
> +    case 2:
> +        rc = ns16550_io_write16(vdev, reg, (uint16_t *)data);
> +        break;
> +
> +    default:
> +        rc = -EINVAL;
> +        break;
> +    }
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate 8-bit read access to NS16550 register.
> + */
> +static int ns16550_io_read8(
> +    struct vuart_ns16550 *vdev, uint32_t reg, uint8_t *data)
> +{
> +    uint8_t *regs = vdev->regs;
> +    uint8_t val = 0xff;
> +    int rc = 0;
> +
> +    if ( ns16550_dlab_get(vdev) && (reg == UART_DLL || reg == UART_DLM) )
> +        val = regs[NS16550_REGS_NUM + reg];
> +    else {
> +        switch ( reg )
> +        {
> +        case UART_RBR:
> +            /* NB: do not forget to clear overrun condition */
> +            regs[UART_LSR] &= ~UART_LSR_OE;
> +
> +            rc = ns16550_fifo_rx_getchar(vdev);
> +            if ( rc >= 0 )
> +                val = (uint8_t)rc;
> +
> +            rc = 0;
> +            break;
> +
> +        case UART_IER:
> +            val = regs[UART_IER];
> +            break;
> +
> +        case UART_IIR: /* RO */
> +            val = ns16550_iir_get(vdev);
> +
> +            /* NB: clear IIR scratch location */
> +            if ( val & UART_IIR_THR )
> +                regs[NS16550_REGS_NUM + UART_IIR] &= ~UART_IIR_THR;
> +
> +            break;
> +
> +        case UART_LCR:
> +            val = regs[UART_LCR];
> +            break;
> +
> +        case UART_MCR:
> +            val = regs[UART_MCR];
> +            break;
> +
> +        case UART_LSR:
> +            val = regs[UART_LSR] | UART_LSR_THRE | UART_LSR_TEMT;
> +            if ( ns16550_fifo_rx_empty(vdev) )
> +                val &= ~UART_LSR_DR;
> +            else
> +                val |= UART_LSR_DR;
> +
> +            regs[UART_LSR] = val & ~UART_LSR_MASK;
> +
> +            break;
> +
> +        case UART_MSR:
> +            val = regs[UART_MSR];
> +            regs[UART_MSR] &= ~UART_MSR_CHANGE;
> +            break;
> +
> +        case UART_SCR:
> +            val = regs[UART_SCR];
> +            break;
> +
> +        default:
> +            rc = -EINVAL;
> +            break;
> +        }
> +
> +        ns16550_irq_check(vdev);
> +    }
> +
> +    *data = val;
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate 16-bit read access to NS16550 register.
> + */
> +static int ns16550_io_read16(
> +    struct vuart_ns16550 *vdev, uint32_t reg, uint16_t *data)
> +{
> +    uint16_t val = 0xffff;
> +    int rc = -EINVAL;
> +
> +    if ( ns16550_dlab_get(vdev) && reg == UART_DLL )
> +    {
> +        val = vdev->regs[NS16550_REGS_NUM + UART_DLM] << 8 |
> +              vdev->regs[NS16550_REGS_NUM + UART_DLL];
> +        rc = 0;
> +    }
> +
> +    *data = val;
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate read access to NS16550 register.
> + */
> +static int ns16550_io_read(
> +    struct vuart_ns16550 *vdev, uint8_t reg, uint32_t size, uint32_t *data)
> +{
> +    int rc;
> +
> +    switch ( size )
> +    {
> +    case 1:
> +        rc = ns16550_io_read8(vdev, reg, (uint8_t *)data);
> +        break;
> +
> +    case 2:
> +        rc = ns16550_io_read16(vdev, reg, (uint16_t *)data);
> +        break;
> +
> +    default:
> +        *data = 0xffffffff;
> +        rc = -EINVAL;
> +        break;
> +    }
> +
> +    return rc;
> +}
> +
> +static void cf_check ns16550_dump_state(const struct domain *d)
> +{
> +    struct vuart_ns16550 *vdev = d->arch.hvm.vuart;
> +    const struct xencons_interface *cons;
> +    const uint8_t *regs;
> +
> +    if ( !vdev )
> +        return;
> +
> +    /* Allow printing state in case of a deadlock. */
> +    if ( !spin_trylock(&vdev->lock) )
> +        return;
> +
> +    cons = &vdev->cons;
> +    regs = &vdev->regs[0];
> +
> +    printk("Virtual " pr_prefix " (%s) I/O port 0x%04"PRIx64" IRQ#%d owner %pd\n",
> +            vdev->name, vdev->io_addr, vdev->irq, vdev->owner);
> +
> +    printk("  RX FIFO size %ld in_prod %d in_cons %d used %d\n",
> +            ARRAY_SIZE(cons->in), cons->in_prod, cons->in_cons,
> +            cons->in_prod - cons->in_cons);
> +
> +    printk("  TX FIFO size %ld out_prod %d out_cons %d used %d\n",
> +            ARRAY_SIZE(cons->out), cons->out_prod, cons->out_cons,
> +            cons->out_prod - cons->out_cons);
> +
> +    printk("  %02"PRIx8" RBR %02"PRIx8" THR %02"PRIx8" DLL %02"PRIx8" DLM %02"PRIx8"\n",
> +            UART_RBR,
> +            cons->in[MASK_XENCONS_IDX(cons->in_prod, cons)],
> +            cons->out[MASK_XENCONS_IDX(cons->out_prod, cons)],
> +            regs[NS16550_REGS_NUM + UART_DLL],
> +            regs[NS16550_REGS_NUM + UART_DLM]);
> +
> +    printk("  %02"PRIx8" IER %02"PRIx8"\n", UART_IER, regs[UART_IER]);
> +
> +    printk("  %02"PRIx8" FCR %02"PRIx8" IIR %02"PRIx8"\n",
> +            UART_FCR, regs[UART_FCR], ns16550_iir_get(vdev));
> +
> +    printk("  %02"PRIx8" LCR %02"PRIx8"\n", UART_LCR, regs[UART_LCR]);
> +    printk("  %02"PRIx8" MCR %02"PRIx8"\n", UART_MCR, regs[UART_MCR]);
> +    printk("  %02"PRIx8" LSR %02"PRIx8"\n", UART_LSR, regs[UART_LSR]);
> +    printk("  %02"PRIx8" MSR %02"PRIx8"\n", UART_MSR, regs[UART_MSR]);
> +    printk("  %02"PRIx8" SCR %02"PRIx8"\n", UART_SCR, regs[UART_SCR]);
> +
> +    spin_unlock(&vdev->lock);
> +}
> +
> +/*
> + * Emulate I/O access to NS16550 register.
> + * Note, emulation always returns X86EMUL_OKAY, once I/O port trap is enabled.
> + */
> +static int cf_check ns16550_io_handle(
> +    int dir, unsigned int addr, unsigned int size, uint32_t *data)
> +{
> +#define op(dir)     (((dir) == IOREQ_WRITE) ? 'W' : 'R')
> +    struct domain *d = rcu_lock_current_domain();
> +    struct vuart_ns16550 *vdev = d->arch.hvm.vuart;
> +    uint32_t reg;
> +    unsigned dlab;
> +    int rc;
> +
> +    if ( !vdev )
> +    {
> +        pr_err("%s: %c io 0x%04x %d: not initialized\n",
> +                vdev->name, op(dir), addr, size);
> +
> +        ASSERT_UNREACHABLE();
> +        goto out;
> +    }
> +
> +    if ( d != vdev->owner )
> +    {
> +        pr_err("%s: %c io 0x%04x %d: does not match current domain %pv\n",
> +                vdev->name, op(dir), addr, size, d);
> +
> +        ASSERT_UNREACHABLE();
> +        goto out;
> +    }
> +
> +    reg = addr - vdev->io_addr;
> +    if ( !IS_ALIGNED(reg, size) )
> +    {
> +        pr_err("%s: %c 0x%04x %d: unaligned access\n",
> +                vdev->name, op(dir), addr, size);
> +        goto out;
> +    }
> +
> +    dlab = ns16550_dlab_get(vdev);
> +    if ( reg >= NS16550_REGS_NUM )
> +    {
> +        pr_err("%s: %c io 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32": not implemented\n",
> +                vdev->name, op(dir), addr, size,
> +                dlab, reg, *data);
> +        goto out;
> +    }
> +
> +    spin_lock(&vdev->lock);
> +
> +    if ( dir == IOREQ_WRITE )
> +    {
> +        pr_debug("%s: %c 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32"\n",
> +                 vdev->name, op(dir), addr, size,
> +                 dlab, reg, *data);
> +        rc = ns16550_io_write(vdev, reg, size, data);
> +    }
> +    else
> +    {
> +        rc = ns16550_io_read(vdev, reg, size, data);
> +        pr_debug("%s: %c 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32"\n",
> +                 vdev->name, op(dir), addr, size,
> +                 dlab, reg, *data);
> +    }
> +    if ( rc < 0 )
> +        pr_err("%s: %c 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32": unsupported access\n",
> +               vdev->name, op(dir), addr, size,
> +               dlab, reg, *data);
> +
> +    spin_unlock(&vdev->lock);
> +#ifdef CONFIG_VUART_NS16550_DEBUG
> +    ns16550_dump_state(d);
> +#endif
> +
> +out:
> +    rcu_unlock_domain(d);
> +
> +    return X86EMUL_OKAY;
> +#undef op
> +}
> +
> +static int cf_check ns16550_init(struct domain *d,
> +                                 struct vuart_params *params)
> +{
> +    const struct virtdev_desc *desc = &x86_pc_uarts[X86_PC_UART_IDX];
> +    const struct resource *r = desc->res;
> +    const uint16_t divisor = (UART_CLOCK_HZ / 115200) >> 4;
> +    struct vuart_ns16550 *vdev;
> +    int rc;
> +
> +    BUG_ON(d->arch.hvm.vuart);
> +
> +    if ( !is_hvm_domain(d) )
> +    {
> +        pr_err("%s: not an HVM domain\n", desc->name);
> +        return -ENOSYS;
> +    }
> +
> +    vdev = xvzalloc(typeof(*vdev));
> +    if ( !vdev )
> +    {
> +        pr_err("%s: failed to allocate memory\n", desc->name);
> +        return -ENOMEM;
> +    }
> +
> +    for_each_resource(r)
> +    {
> +        if ( r->type & IORESOURCE_IO )
> +        {
> +            /* Disallow sharing physical I/O port */
> +            rc = ioports_deny_access(d, r->addr, r->addr + r->size - 1);
> +            if ( rc )
> +            {
> +                pr_err("%s: virtual I/O port range [0x%04x"PRIx64"..0x%04x"PRIx64"]: conflict w/ physical range\n",
> +                        desc->name,
> +                        (unsigned int)r->addr,
> +                        (unsigned int)(r->addr + r->size - 1));
> +                return rc;
> +            }
> +
> +            register_portio_handler(d, r->addr, r->size, ns16550_io_handle);
> +
> +            vdev->io_addr = r->addr;
> +            vdev->io_size = r->size;
> +        }
> +        else if ( r->type & IORESOURCE_IRQ )
> +        {
> +            /* Disallow sharing physical IRQ */
> +            rc = irq_deny_access(d, r->addr);
> +            if ( rc )
> +            {
> +                pr_err("%s: virtual IRQ#%"PRIu64": conflict w/ physical IRQ: %d\n",
> +                        desc->name, r->addr, rc);
> +                return rc;
> +            }
> +
> +            vdev->irq = r->addr;
> +        }
> +        else
> +            ASSERT_UNREACHABLE();
> +    }
> +
> +    spin_lock_init(&vdev->lock);
> +
> +    vdev->owner = d;
> +    vdev->name = desc->name;
> +
> +    /* NB: report 115200 baud rate */
> +    vdev->regs[NS16550_REGS_NUM + UART_DLL] = divisor & 0xff;
> +    vdev->regs[NS16550_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
> +
> +    /* NS16550 shall assert UART_IIR_THR whenever transmitter is empty. */
> +    vdev->regs[NS16550_REGS_NUM + UART_IIR] = UART_IIR_THR;
> +
> +    d->arch.hvm.vuart = vdev;
> +
> +    spin_lock(&vdev->lock);
> +    ns16550_irq_check(vdev);
> +    spin_unlock(&vdev->lock);
> +
> +    return 0;
> +}
> +
> +static void cf_check ns16550_deinit(struct domain *d)
> +{
> +    struct vuart_ns16550 *vdev = d->arch.hvm.vuart;
> +
> +    if ( !vdev )
> +        return;
> +
> +    spin_lock(&vdev->lock);
> +
> +    ns16550_fifo_tx_flush(vdev);
> +
> +    spin_unlock(&vdev->lock);
> +
> +    XVFREE(d->arch.hvm.vuart);
> +}
> +
> +static int cf_check ns16550_put_rx(struct domain *d, char ch)
> +{
> +    struct vuart_ns16550 *vdev = d->arch.hvm.vuart;
> +    uint8_t *regs;
> +    uint8_t dlab;
> +    int rc;
> +
> +    ASSERT(d == vdev->owner);
> +    if ( !vdev )
> +        return -ENODEV;
> +
> +    spin_lock(&vdev->lock);
> +
> +    dlab = ns16550_dlab_get(vdev);
> +    regs = vdev->regs;
> +
> +    if ( dlab )
> +    {
> +        pr_debug("%s: THR/RBR access disabled: DLAB=1\n", vdev->name);
> +        rc = -EBUSY;
> +    }
> +    else if ( regs[UART_MCR] & UART_MCR_LOOP )
> +    {
> +        pr_debug("%s: THR/RBR access disabled: loopback mode\n", vdev->name);
> +        rc = -EBUSY;
> +    }
> +    else
> +    {
> +        uint8_t val = 0;
> +
> +        rc = ns16550_fifo_rx_putchar(vdev, ch);
> +        if ( rc == -ENOSPC )
> +            val |= UART_LSR_OE;
> +
> +        /* NB: UART_LSR_DR is also set when UART_LSR is accessed. */
> +        regs[UART_LSR] |= UART_LSR_DR | val;
> +
> +        /*
> +         * Echo the user input on Xen console iff Xen console input is owned
> +         * by NS16550 domain.
> +         * NB: use 'console_timestamps=none' to disable Xen timestamps.
> +         */
> +        if ( is_console_printable(ch) )
> +            guest_printk(d, "%c", ch);
> +
> +        /* FIXME: check FCR when to fire an interrupt */
> +        ns16550_irq_check(vdev);
> +    }
> +
> +    spin_unlock(&vdev->lock);
> +#ifdef CONFIG_VUART_NS16550_DEBUG
> +    ns16550_dump_state(d);
> +#endif
> +
> +    return rc;
> +}
> +
> +static const struct vuart_ops ns16550_ops = {
> +    .add_node   = NULL,
> +    .init       = ns16550_init,
> +    .deinit     = ns16550_deinit,
> +    .dump_state = ns16550_dump_state,
> +    .put_rx     = ns16550_put_rx,
> +};
> +
> +VUART_REGISTER(ns16550, &ns16550_ops);
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/common/emul/vuart/vuart.c b/xen/common/emul/vuart/vuart.c
> index 14a7f8bd8b79..7971813a723d 100644
> --- a/xen/common/emul/vuart/vuart.c
> +++ b/xen/common/emul/vuart/vuart.c
> @@ -99,6 +99,10 @@ bool domain_has_vuart(const struct domain *d)
>  {
>      uint32_t mask = 0;
>  
> +#ifdef CONFIG_VUART_NS16550
> +    mask |= XEN_X86_EMU_NS16550;
> +#endif
> +
>      return !!(d->emulation_flags & mask);
>  }
>  
> diff --git a/xen/include/public/arch-x86/xen.h b/xen/include/public/arch-x86/xen.h
> index fc2487986642..f905e1252c70 100644
> --- a/xen/include/public/arch-x86/xen.h
> +++ b/xen/include/public/arch-x86/xen.h
> @@ -283,13 +283,15 @@ struct xen_arch_domainconfig {
>  #define XEN_X86_EMU_USE_PIRQ        (1U<<_XEN_X86_EMU_USE_PIRQ)
>  #define _XEN_X86_EMU_VPCI           10
>  #define XEN_X86_EMU_VPCI            (1U<<_XEN_X86_EMU_VPCI)
> +#define _XEN_X86_EMU_NS16550        11
> +#define XEN_X86_EMU_NS16550         (1U<<_XEN_X86_EMU_NS16550)
>  
>  #define XEN_X86_EMU_ALL             (XEN_X86_EMU_LAPIC | XEN_X86_EMU_HPET |  \
>                                       XEN_X86_EMU_PM | XEN_X86_EMU_RTC |      \
>                                       XEN_X86_EMU_IOAPIC | XEN_X86_EMU_PIC |  \
>                                       XEN_X86_EMU_VGA | XEN_X86_EMU_IOMMU |   \
>                                       XEN_X86_EMU_PIT | XEN_X86_EMU_USE_PIRQ |\
> -                                     XEN_X86_EMU_VPCI)
> +                                     XEN_X86_EMU_VPCI | XEN_X86_EMU_NS16550)

libxl also consumes XEN_X86_EMU_ALL, and with the proposed change here
it will create all HVM domains with XEN_X86_EMU_NS16550, which I don't
think it's indented?

Overall I agree for Jan it would be better if this patch could be
split into somehow smaller units.  Is this something feasible?  We
don't want a patch for each register handle, but maybe you cna somehow
grup those into functional sections, so that patches can be < 250
lines?

Maybe you have already considered this approach and it wasn't
feasible?

Thanks, Roger.


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        Wed, 06 Aug 2025 08:21:07 -0700 (PDT)
Date: Wed, 6 Aug 2025 17:21:06 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 6/8] tools/xl: enable NS16550-compatible UART emulator
 for HVM (x86)
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-7-dmukhin@ford.com>
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In-Reply-To: <20250731192130.3948419-7-dmukhin@ford.com>

On Thu, Jul 31, 2025 at 07:22:12PM +0000, dmkhn@proton.me wrote:
> From: Denis Mukhin  
> 
> Enable UART emulator to be individually configured per HVM-domain.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v3:
> - new patch
> ---
>  docs/man/xl.cfg.5.pod.in             |  9 ++++--
>  tools/golang/xenlight/helpers.gen.go |  4 +--
>  tools/golang/xenlight/types.gen.go   |  3 +-
>  tools/libs/light/libxl_arm.c         | 26 ++++++++++++-----
>  tools/libs/light/libxl_create.c      |  2 +-
>  tools/libs/light/libxl_types.idl     |  3 +-
>  tools/libs/light/libxl_x86.c         | 42 ++++++++++++++++++++++++++++
>  tools/ocaml/libs/xc/xenctrl.ml       |  1 +
>  tools/ocaml/libs/xc/xenctrl.mli      |  1 +
>  tools/xl/xl_parse.c                  |  2 +-
>  xen/arch/x86/domain.c                |  5 ++--
>  11 files changed, 80 insertions(+), 18 deletions(-)
> 
> diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
> index 5362fb0e9a6f..e1d012274eaf 100644
> --- a/docs/man/xl.cfg.5.pod.in
> +++ b/docs/man/xl.cfg.5.pod.in
> @@ -3032,14 +3032,17 @@ the domain was created.
>  This requires hardware compatibility with the requested version, either
>  natively or via hardware backwards compatibility support.
>  
> -=item B
> +=item B
>  
>  To enable vuart console, user must specify the following option in the
> -VM config file:
> +VM config file, e.g:
>  
> +```
>  vuart = "sbsa_uart"
> +```
>  
> -Currently, only the "sbsa_uart" model is supported for ARM.
> +Currently, "sbsa_uart" (ARM) and "ns16550" (x86) are the only supported
> +UART models.
>  
>  =back
>  
> diff --git a/tools/golang/xenlight/helpers.gen.go b/tools/golang/xenlight/helpers.gen.go
> index b43aad7d0064..e56af8a8a8c5 100644
> --- a/tools/golang/xenlight/helpers.gen.go
> +++ b/tools/golang/xenlight/helpers.gen.go
> @@ -1160,7 +1160,6 @@ x.TypeUnion = &typePvh
>  default:
>  return fmt.Errorf("invalid union key '%v'", x.Type)}
>  x.ArchArm.GicVersion = GicVersion(xc.arch_arm.gic_version)
> -x.ArchArm.Vuart = VuartType(xc.arch_arm.vuart)
>  x.ArchArm.SveVl = SveType(xc.arch_arm.sve_vl)
>  x.ArchArm.NrSpis = uint32(xc.arch_arm.nr_spis)
>  if err := x.ArchX86.MsrRelaxed.fromC(&xc.arch_x86.msr_relaxed);err != nil {
> @@ -1169,6 +1168,7 @@ return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err)
>  x.Altp2M = Altp2MMode(xc.altp2m)
>  x.Altp2MCount = uint32(xc.altp2m_count)
>  x.VmtraceBufKb = int(xc.vmtrace_buf_kb)
> +x.Vuart = VuartType(xc.vuart)
>  if err := x.Vpmu.fromC(&xc.vpmu);err != nil {
>  return fmt.Errorf("converting field Vpmu: %v", err)
>  }
> @@ -1695,7 +1695,6 @@ break
>  default:
>  return fmt.Errorf("invalid union key '%v'", x.Type)}
>  xc.arch_arm.gic_version = C.libxl_gic_version(x.ArchArm.GicVersion)
> -xc.arch_arm.vuart = C.libxl_vuart_type(x.ArchArm.Vuart)
>  xc.arch_arm.sve_vl = C.libxl_sve_type(x.ArchArm.SveVl)
>  xc.arch_arm.nr_spis = C.uint32_t(x.ArchArm.NrSpis)
>  if err := x.ArchX86.MsrRelaxed.toC(&xc.arch_x86.msr_relaxed); err != nil {
> @@ -1704,6 +1703,7 @@ return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err)
>  xc.altp2m = C.libxl_altp2m_mode(x.Altp2M)
>  xc.altp2m_count = C.uint32_t(x.Altp2MCount)
>  xc.vmtrace_buf_kb = C.int(x.VmtraceBufKb)
> +xc.vuart = C.libxl_vuart_type(x.Vuart)
>  if err := x.Vpmu.toC(&xc.vpmu); err != nil {
>  return fmt.Errorf("converting field Vpmu: %v", err)
>  }
> diff --git a/tools/golang/xenlight/types.gen.go b/tools/golang/xenlight/types.gen.go
> index 4777f528b52c..2f4153d2510b 100644
> --- a/tools/golang/xenlight/types.gen.go
> +++ b/tools/golang/xenlight/types.gen.go
> @@ -253,6 +253,7 @@ type VuartType int
>  const(
>  VuartTypeUnknown VuartType = 0
>  VuartTypeSbsaUart VuartType = 1
> +VuartTypeNs16550 VuartType = 2
>  )
>  
>  type VkbBackend int
> @@ -596,7 +597,6 @@ Type DomainType
>  TypeUnion DomainBuildInfoTypeUnion
>  ArchArm struct {
>  GicVersion GicVersion
> -Vuart VuartType
>  SveVl SveType
>  NrSpis uint32
>  }
> @@ -608,6 +608,7 @@ Altp2MCount uint32
>  VmtraceBufKb int
>  Vpmu Defbool
>  TrapUnmappedAccesses Defbool
> +Vuart VuartType
>  }
>  
>  type DomainBuildInfoTypeUnion interface {
> diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c
> index 4a19a8d22bdf..f4721b24763c 100644
> --- a/tools/libs/light/libxl_arm.c
> +++ b/tools/libs/light/libxl_arm.c
> @@ -92,14 +92,26 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
>      uint32_t virtio_mmio_irq = GUEST_VIRTIO_MMIO_SPI_FIRST;
>      int rc;
>  
> -    /*
> -     * If pl011 vuart is enabled then increment the nr_spis to allow allocation
> -     * of SPI VIRQ for pl011.
> -     */
> -    if (d_config->b_info.arch_arm.vuart == LIBXL_VUART_TYPE_SBSA_UART) {
> +    switch ( d_config->b_info.vuart )
> +    {
> +    case LIBXL_VUART_TYPE_SBSA_UART:
> +        /*
> +         * If pl011 vuart is enabled then increment the nr_spis to allow
> +         * allocation of SPI VIRQ for pl011.
> +         */
>          nr_spis += (GUEST_VPL011_SPI - 32) + 1;
>          vuart_irq = GUEST_VPL011_SPI;
>          vuart_enabled = true;
> +        break;
> +
> +    case LIBXL_VUART_TYPE_NS16550:
> +        LOG(ERROR, "unsupported UART emulator %d\n", d_config->b_info.vuart);
> +        abort();
> +        break;
> +
> +    case LIBXL_VUART_TYPE_UNKNOWN:
> +    default:
> +        break;
>      }
>  
>      for (i = 0; i < d_config->num_disks; i++) {
> @@ -1372,7 +1384,7 @@ next_resize:
>          FDT( make_timer_node(gc, fdt, ainfo, state->clock_frequency) );
>          FDT( make_hypervisor_node(gc, fdt, vers) );
>  
> -        if (info->arch_arm.vuart == LIBXL_VUART_TYPE_SBSA_UART)
> +        if (info->vuart == LIBXL_VUART_TYPE_SBSA_UART)
>              FDT( make_vpl011_uart_node(gc, fdt, ainfo, dom) );
>  
>          if (info->tee == LIBXL_TEE_TYPE_OPTEE)
> @@ -1725,7 +1737,7 @@ int libxl__arch_build_dom_finish(libxl__gc *gc,
>  {
>      int rc = 0, ret;
>  
> -    if (info->arch_arm.vuart != LIBXL_VUART_TYPE_SBSA_UART) {
> +    if (info->vuart != LIBXL_VUART_TYPE_SBSA_UART) {
>          rc = 0;
>          goto out;
>      }
> diff --git a/tools/libs/light/libxl_create.c b/tools/libs/light/libxl_create.c
> index 4042ae1a8957..cfd7e827867a 100644
> --- a/tools/libs/light/libxl_create.c
> +++ b/tools/libs/light/libxl_create.c
> @@ -1815,7 +1815,7 @@ static void domcreate_launch_dm(libxl__egc *egc, libxl__multidev *multidev,
>                                &d_config->vfbs[i]);
>          }
>  
> -        if (d_config->b_info.arch_arm.vuart == LIBXL_VUART_TYPE_SBSA_UART) {
> +        if (d_config->b_info.vuart == LIBXL_VUART_TYPE_SBSA_UART) {
>              init_console_info(gc, &vuart, 0);
>              vuart.backend_domid = state->console_domid;
>              libxl__device_vuart_add(gc, domid, &vuart, state);
> diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl
> index fe251649f346..fd60c2b26764 100644
> --- a/tools/libs/light/libxl_types.idl
> +++ b/tools/libs/light/libxl_types.idl
> @@ -276,6 +276,7 @@ libxl_checkpointed_stream = Enumeration("checkpointed_stream", [
>  libxl_vuart_type = Enumeration("vuart_type", [
>      (0, "unknown"),
>      (1, "sbsa_uart"),
> +    (2, "ns16550"),
>      ])
>  
>  libxl_vkb_backend = Enumeration("vkb_backend", [
> @@ -722,7 +723,6 @@ libxl_domain_build_info = Struct("domain_build_info",[
>  
>  
>      ("arch_arm", Struct(None, [("gic_version", libxl_gic_version),
> -                               ("vuart", libxl_vuart_type),
>                                 ("sve_vl", libxl_sve_type),
>                                 ("nr_spis", uint32, {'init_val': 'LIBXL_NR_SPIS_DEFAULT'}),
>                                ])),
> @@ -739,6 +739,7 @@ libxl_domain_build_info = Struct("domain_build_info",[
>  
>      ("vpmu", libxl_defbool),
>      ("trap_unmapped_accesses", libxl_defbool),
> +    ("vuart", libxl_vuart_type),
>  
>      ], dir=DIR_IN,
>         copy_deprecated_fn="libxl__domain_build_info_copy_deprecated",
> diff --git a/tools/libs/light/libxl_x86.c b/tools/libs/light/libxl_x86.c
> index 60d4e8661c93..0f039ca65a88 100644
> --- a/tools/libs/light/libxl_x86.c
> +++ b/tools/libs/light/libxl_x86.c
> @@ -2,6 +2,45 @@
>  #include "libxl_arch.h"
>  #include 
>  
> +static void libxl__arch_domain_vuart_assert(
> +    libxl__gc *gc,
> +    libxl_domain_config *d_config,
> +    struct xen_domctl_createdomain *config)
> +{
> +    LOG(ERROR, "unsupported UART emulator %d\n", d_config->b_info.vuart);
> +    abort();
> +}
> +
> +static void libxl__arch_domain_vuart_unsupported(
> +    libxl__gc *gc,
> +    libxl_domain_config *d_config,
> +    struct xen_domctl_createdomain *config)
> +{
> +    if ( d_config->b_info.vuart != LIBXL_VUART_TYPE_UNKNOWN )
> +        libxl__arch_domain_vuart_assert(gc, d_config, config);
> +}
> +
> +static void libxl__arch_domain_vuart_enable(
> +    libxl__gc *gc,
> +    libxl_domain_config *d_config,
> +    struct xen_domctl_createdomain *config)
> +{
> +    switch ( d_config->b_info.vuart )
> +    {
> +    case LIBXL_VUART_TYPE_SBSA_UART:
> +        libxl__arch_domain_vuart_assert(gc, d_config, config);
> +        break;
> +
> +    case LIBXL_VUART_TYPE_NS16550:
> +        config->arch.emulation_flags |= XEN_X86_EMU_NS16550;
> +        break;
> +
> +    case LIBXL_VUART_TYPE_UNKNOWN:
> +    default:
> +        break;
> +    }
> +}
> +
>  int libxl__arch_domain_prepare_config(libxl__gc *gc,
>                                        libxl_domain_config *d_config,
>                                        struct xen_domctl_createdomain *config)
> @@ -9,14 +48,17 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
>      switch(d_config->c_info.type) {
>      case LIBXL_DOMAIN_TYPE_HVM:
>          config->arch.emulation_flags = (XEN_X86_EMU_ALL & ~XEN_X86_EMU_VPCI);
> +        libxl__arch_domain_vuart_enable(gc, d_config, config);

As mentioned in the previous commit, I don't think this works as
expected.  You have added XEN_X86_EMU_NS16550 to XEN_X86_EMU_ALL, and
hence you need to subtract it from the mask as it's done with VPCI.

>          if (!libxl_defbool_val(d_config->b_info.u.hvm.pirq))
>              config->arch.emulation_flags &= ~XEN_X86_EMU_USE_PIRQ;
>          break;
>      case LIBXL_DOMAIN_TYPE_PVH:
>          config->arch.emulation_flags = XEN_X86_EMU_LAPIC;
> +        libxl__arch_domain_vuart_unsupported(gc, d_config, config);
>          break;
>      case LIBXL_DOMAIN_TYPE_PV:
>          config->arch.emulation_flags = 0;
> +        libxl__arch_domain_vuart_unsupported(gc, d_config, config);
>          break;
>      default:
>          abort();
> diff --git a/tools/ocaml/libs/xc/xenctrl.ml b/tools/ocaml/libs/xc/xenctrl.ml
> index 7e1aabad6cba..4539e78bb283 100644
> --- a/tools/ocaml/libs/xc/xenctrl.ml
> +++ b/tools/ocaml/libs/xc/xenctrl.ml
> @@ -47,6 +47,7 @@ type x86_arch_emulation_flags =
>    | X86_EMU_PIT
>    | X86_EMU_USE_PIRQ
>    | X86_EMU_VPCI
> +  | X86_EMU_NS16550
>  
>  type x86_arch_misc_flags =
>    | X86_MSR_RELAXED
> diff --git a/tools/ocaml/libs/xc/xenctrl.mli b/tools/ocaml/libs/xc/xenctrl.mli
> index f44dba61aeab..66a98180d99b 100644
> --- a/tools/ocaml/libs/xc/xenctrl.mli
> +++ b/tools/ocaml/libs/xc/xenctrl.mli
> @@ -41,6 +41,7 @@ type x86_arch_emulation_flags =
>    | X86_EMU_PIT
>    | X86_EMU_USE_PIRQ
>    | X86_EMU_VPCI
> +  | X86_EMU_NS16550
>  
>  type x86_arch_misc_flags =
>    | X86_MSR_RELAXED
> diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
> index 28cdbf07c213..b0d266b5bf63 100644
> --- a/tools/xl/xl_parse.c
> +++ b/tools/xl/xl_parse.c
> @@ -1498,7 +1498,7 @@ void parse_config_data(const char *config_source,
>          b_info->max_vcpus = l;
>  
>      if (!xlu_cfg_get_string(config, "vuart", &buf, 0)) {
> -        if (libxl_vuart_type_from_string(buf, &b_info->arch_arm.vuart)) {
> +        if (libxl_vuart_type_from_string(buf, &b_info->vuart)) {
>              fprintf(stderr, "ERROR: invalid value \"%s\" for \"vuart\"\n",
>                      buf);
>              exit(1);
> diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
> index 7fd4f7a831dc..6a010a509a60 100644
> --- a/xen/arch/x86/domain.c
> +++ b/xen/arch/x86/domain.c
> @@ -780,9 +780,10 @@ static bool emulation_flags_ok(const struct domain *d, uint32_t emflags)
>          /* HVM domU */
>          {
>              .caps   = CAP_HVM | CAP_DOMU,
> -            .min    = X86_EMU_ALL & ~(X86_EMU_VPCI | X86_EMU_USE_PIRQ),
> +            .min    = X86_EMU_ALL & ~(X86_EMU_VPCI | X86_EMU_USE_PIRQ |
> +                                      X86_EMU_NS16550),
>              /* HVM PIRQ feature is user-selectable. */
> -            .opt    = X86_EMU_USE_PIRQ,
> +            .opt    = X86_EMU_USE_PIRQ | X86_EMU_NS16550,

Does this need to be part of the patch that adds X86_EMU_NS16550 into
X86_EMU_ALL, as to not break domain creation in the interim?

Thanks, Roger.


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Date: Wed, 6 Aug 2025 17:55:07 +0200
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Subject: Re: [PATCH v3 13/20] xen/riscv: Implement p2m_free_subtree() and
 related helpers
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <41845723a7b0e3efd09095d13e57aace6f7747ef.1753973161.git.oleksii.kurochko@gmail.com>
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From: Jan Beulich 
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In-Reply-To: <41845723a7b0e3efd09095d13e57aace6f7747ef.1753973161.git.oleksii.kurochko@gmail.com>
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On 31.07.2025 17:58, Oleksii Kurochko wrote:
> --- a/xen/arch/riscv/include/asm/p2m.h
> +++ b/xen/arch/riscv/include/asm/p2m.h
> @@ -79,10 +79,20 @@ typedef enum {
>      p2m_ext_storage,    /* Following types'll be stored outsude PTE bits: */
>      p2m_grant_map_rw,   /* Read/write grant mapping */
>      p2m_grant_map_ro,   /* Read-only grant mapping */
> +    p2m_map_foreign_rw, /* Read/write RAM pages from foreign domain */
> +    p2m_map_foreign_ro, /* Read-only RAM pages from foreign domain */
>  } p2m_type_t;
>  
>  #define p2m_mmio_direct p2m_mmio_direct_io
>  
> +/*
> + * Bits 8 and 9 are reserved for use by supervisor software;
> + * the implementation shall ignore this field.
> + * We are going to use to save in these bits frequently used types to avoid
> + * get/set of a type from radix tree.
> + */
> +#define P2M_TYPE_PTE_BITS_MASK  0x300
> +
>  /* We use bitmaps and mask to handle groups of types */
>  #define p2m_to_mask(t_) BIT(t_, UL)
>  
> @@ -93,10 +103,16 @@ typedef enum {
>  #define P2M_GRANT_TYPES (p2m_to_mask(p2m_grant_map_rw) | \
>                           p2m_to_mask(p2m_grant_map_ro))
>  
> +                            /* Foreign mappings types */

Nit: Why so far to the right?

> --- a/xen/arch/riscv/p2m.c
> +++ b/xen/arch/riscv/p2m.c
> @@ -197,6 +197,16 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
>      return __map_domain_page(p2m->root + root_table_indx);
>  }
>  
> +static p2m_type_t p2m_get_type(const pte_t pte)
> +{
> +    p2m_type_t type = MASK_EXTR(pte.pte, P2M_TYPE_PTE_BITS_MASK);
> +
> +    if ( type == p2m_ext_storage )
> +        panic("unimplemented\n");

That is, as per p2m.h additions you pretend to add support for foreign types
here, but then you don't?

> @@ -248,11 +258,136 @@ static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl,
>      return P2M_TABLE_MAP_NONE;
>  }
>  
> +static void p2m_put_foreign_page(struct page_info *pg)
> +{
> +    /*
> +     * It’s safe to call put_page() here because arch_flush_tlb_mask()
> +     * will be invoked if the page is reallocated before the end of
> +     * this loop, which will trigger a flush of the guest TLBs.
> +     */
> +    put_page(pg);
> +}

How can one know the comment is true? arch_flush_tlb_mask() still lives in
stubs.c, and hence what it is eventually going to do (something like Arm's
vs more like x86'es) is entirely unknown right now.

> +/* Put any references on the single 4K page referenced by mfn. */
> +static void p2m_put_4k_page(mfn_t mfn, p2m_type_t type)
> +{
> +    /* TODO: Handle other p2m types */
> +
> +    if ( p2m_is_foreign(type) )
> +    {
> +        ASSERT(mfn_valid(mfn));
> +        p2m_put_foreign_page(mfn_to_page(mfn));
> +    }
> +
> +    /*
> +     * Detect the xenheap page and mark the stored GFN as invalid.
> +     * We don't free the underlying page until the guest requested to do so.
> +     * So we only need to tell the page is not mapped anymore in the P2M by
> +     * marking the stored GFN as invalid.
> +     */
> +    if ( p2m_is_ram(type) && is_xen_heap_mfn(mfn) )
> +        page_set_xenheap_gfn(mfn_to_page(mfn), INVALID_GFN);

Isn't this for grants? p2m_is_ram() doesn't cover p2m_grant_map_*.

> +}
> +
> +/* Put any references on the superpage referenced by mfn. */
> +static void p2m_put_2m_superpage(mfn_t mfn, p2m_type_t type)
> +{
> +    struct page_info *pg;
> +    unsigned int i;
> +
> +    ASSERT(mfn_valid(mfn));
> +
> +    pg = mfn_to_page(mfn);
> +
> +    for ( i = 0; i < XEN_PT_ENTRIES; i++, pg++ )
> +        p2m_put_foreign_page(pg);
> +}

In p2m_put_4k_page() you check the type, whereas here you don't.

> +/* Put any references on the page referenced by pte. */
> +static void p2m_put_page(const pte_t pte, unsigned int level)
> +{
> +    mfn_t mfn = pte_get_mfn(pte);
> +    p2m_type_t p2m_type = p2m_get_type(pte);
> +
> +    ASSERT(pte_is_valid(pte));
> +
> +    /*
> +     * TODO: Currently we don't handle level 2 super-page, Xen is not
> +     * preemptible and therefore some work is needed to handle such
> +     * superpages, for which at some point Xen might end up freeing memory
> +     * and therefore for such a big mapping it could end up in a very long
> +     * operation.
> +     */
> +    switch ( level )
> +    {
> +    case 1:
> +        return p2m_put_2m_superpage(mfn, p2m_type);
> +
> +    case 0:
> +        return p2m_put_4k_page(mfn, p2m_type);
> +    }

Yet despite the comment not even an assertion for level 2 and up?

>  /* Free pte sub-tree behind an entry */
>  static void p2m_free_subtree(struct p2m_domain *p2m,
>                               pte_t entry, unsigned int level)
>  {
> -    panic("%s: hasn't been implemented yet\n", __func__);
> +    unsigned int i;
> +    pte_t *table;
> +    mfn_t mfn;
> +    struct page_info *pg;
> +
> +    /* Nothing to do if the entry is invalid. */
> +    if ( !pte_is_valid(entry) )
> +        return;
> +
> +    if ( pte_is_superpage(entry, level) || (level == 0) )

Perhaps swap the two conditions around?

> +    {
> +#ifdef CONFIG_IOREQ_SERVER
> +        /*
> +         * If this gets called then either the entry was replaced by an entry
> +         * with a different base (valid case) or the shattering of a superpage
> +         * has failed (error case).
> +         * So, at worst, the spurious mapcache invalidation might be sent.
> +         */
> +        if ( p2m_is_ram(p2m_get_type(p2m, entry)) &&
> +             domain_has_ioreq_server(p2m->domain) )
> +            ioreq_request_mapcache_invalidate(p2m->domain);
> +#endif
> +
> +        p2m_put_page(entry, level);
> +
> +        return;
> +    }
> +
> +    table = map_domain_page(pte_get_mfn(entry));
> +    for ( i = 0; i < XEN_PT_ENTRIES; i++ )
> +        p2m_free_subtree(p2m, table[i], level - 1);

In p2m_put_page() you comment towards concerns for level >= 2; no similar
concerns for the resulting recursion here?

> +    unmap_domain_page(table);
> +
> +    /*
> +     * Make sure all the references in the TLB have been removed before
> +     * freing the intermediate page table.
> +     * XXX: Should we defer the free of the page table to avoid the
> +     * flush?
> +     */
> +    p2m_tlb_flush_sync(p2m);
> +
> +    mfn = pte_get_mfn(entry);
> +    ASSERT(mfn_valid(mfn));
> +
> +    pg = mfn_to_page(mfn);
> +
> +    page_list_del(pg, &p2m->pages);
> +    p2m_free_page(p2m, pg);

Once again I wonder whether this code path was actually tested: p2m_free_page()
also invokes page_list_del(), and double deletions typically won't end very
well.

Jan


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Subject: Re: [PATCH v3 03/20] xen/riscv: introduce VMID allocation and
 manegement
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 
 
 
 <6ddee574-6fe2-4de7-b000-a3af0b2c9d12@suse.com>
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From: Oleksii Kurochko 
In-Reply-To: <6ddee574-6fe2-4de7-b000-a3af0b2c9d12@suse.com>

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On 8/6/25 2:05 PM, Jan Beulich wrote:
> On 06.08.2025 13:33, Oleksii Kurochko wrote:
>> On 8/4/25 5:19 PM, Jan Beulich wrote:
>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>> @@ -148,6 +149,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id,
>>>>    
>>>>        console_init_postirq();
>>>>    
>>>> +    vmid_init();
>>> This lives here only temporarily, I assume? Every hart will need to execute
>>> it, and hence (like we have it on x86) this may want to be a central place
>>> elsewhere.
>> I haven’t checked how it is done on x86; I probably should.
>>
>> I planned to call it for each hart separately during secondary hart bring-up,
>> since accessing the|hgatp| register of a hart is required to detect|VMIDLEN|.
>> Therefore,|vmid_init()| should be called for secondary harts when their
>> initialization code starts executing.
> But is this going to be the only per-hart thing that will need doing? Otherwise
> the same larger "container" function may want calling instead.

Yes, it is going to be the only per-hart operation.

There is|__cpu_up()| (not yet upstreamed [1]), which calls
|sbi_hsm_hart_start(hartid, boot_addr, hsm_data)| to start a hart, and I planned
to place|vmid_init()| somewhere in the code executed at|boot_addr|.

[1]https://gitlab.com/xen-project/people/olkur/xen/-/blob/latest/xen/arch/riscv/smpboot.c#L40

>>>> +{
>>>> +    unsigned long vmid_bits;
>>> Why "long" (also for the function return type)?
>> Because csr_read() returns unsigned long as HGATP register has
>> 'unsigned long' length.
> Oh, right, I should have commented on the function return type only.
> Yet then I also can't resist stating that this kind of use of a variable,
> which initially is assigned a value that doesn't really fit its name, is
> easily misleading towards giving such comments.
>
>> But it could be done in this way:
>>       csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>       vmid_bits =  MASK_EXTR(csr_read(CSR_HGATP), HGATP_VMID_MASK);
>>       vmid_bits = ffs_g(vmid_bits);
>>       csr_write(CSR_HGATP, old);
>> And then use uint16_t for vmid_bits and use uin16_t as a return type.
> Please check ./CODING_STYLE again as to the use of fixed-width types.

I meant unsigned short, uint16_t was just short to write. I'll try to be
more specific.

>
>>>> +    unsigned long old;
>>>> +
>>>> +    /* Figure-out number of VMID bits in HW */
>>>> +    old = csr_read(CSR_HGATP);
>>>> +
>>>> +    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>>> +    vmid_bits = csr_read(CSR_HGATP);
>>>> +    vmid_bits =  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);
>>> Nit: Stray blank.
>>>
>>>> +    vmid_bits = flsl(vmid_bits);
>>>> +    csr_write(CSR_HGATP, old);
>>>> +
>>>> +    /*
>>>> +     * We polluted local TLB so flush all guest TLB as
>>>> +     * a speculative access can happen at any time.
>>>> +     */
>>>> +    local_hfence_gvma_all();
>>> There's no guest running. If you wrote hgat.MODE as zero, as per my
>>> understanding now new TLB entries could even purely theoretically appear.
>> It could be an issue (or, at least, it is recommended) when hgatp.MODE is
>> changed:
>>    If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0
>>    (and rs2 set to either x0 or the VMID) must be executed to order subsequent
>>    guest translations with the MODE change—even if the old MODE or new MODE
>>    is Bare.
>> On other hand it is guaranteed that, at least, on Reset (and so I assume
>> for power on) that:
>>    If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE
>>    fields are reset to 0.
>>
>> So it seems like if no guest is ran then there is no need even to write
>> hgatp.MODE as zero, but it might be sense to do that explicitly just to
>> be sure.
>>
>> I thought it was possible to have a running guest and perform a CPU hotplug.
> But that guest will run on another hart.
>
>> In that case, I expect that during the hotplug,|vmidlen_detect()| will be
>> called and return the|vmid_bits| value, which is used as the active VMID.
>> At that moment, the local TLB could be speculatively polluted, I think.
>> Likely, it makes sense to call vmidlen_detect() only once for each hart
>> during initial bringup.
> That may bring you more problems than it solves. You'd need to stash away
> the value originally read somewhere. And that somewhere isn't per-CPU data.
>
>>> In fact, with no guest running (yet) I'm having a hard time seeing why
>>> you shouldn't be able to simply write the register with just
>>> HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable
>>> whether "old" needs restoring; writing plain zero afterwards ought to
>>> suffice. You're in charcge of the register, after all.
>> It make sense (but I don't know if it is a possible case) to be sure that
>> HGATP.MODE remains the same, so there is no need to have TLB flush. If
>> HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned
>> above.
>>
>> If we agreed to keep local_hfence_gvma_all() then I think it isn't really
>> any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.
>>
>> Generally if 'old' is guaranteed to be zero (and, probably, it makes sense
>> to check that in vmidlen_detect() and panic if it isn't zero) and if
>> vmidlen_detect() function will be called before any guest domain(s) will
>> be ran then I could agree that we don't need local_hfence_gvma_all() here.
>>
>> As an option we can do local_hfence_gvma_all() only if 'old' value wasn't
>> set to zero.
>>
>> Does it make sense?
> Well - I'd like the pre-conditions to be understood better. For example, can
> a hart really speculate into guest mode, when the hart is only in the
> process of being brought up?

I couldn't explicit words that a hart can't speculate into guest mode
either on bring up or during its work.

But there are some moments in the spec which tells:
   Implementations with virtual memory are permitted to perform address
   translations speculatively and earlier than required by an explicit
   memory access, and are permitted to cache them in address translation
   cache structures—including possibly caching the identity mappings from
   effective address to physical address used in Bare translation modes and
   M-mode.
And here:
   Implementations may also execute the address-translation algorithm
   speculatively at any time, for any virtual address, as long as satp is
   active (as defined in Section 10.1.11). Such speculative executions have
   the effect of pre-populating the address-translation cache.
Where it is explicitly mentioned that speculation can happen in *any time*.
And at the same time:
   Speculative executions of the address-translation algorithm behave as
   non-speculative executions of the algorithm do, except that they must
   not set the dirty bit for a PTE, they must not trigger an exception,
   and they must not create address-translation cache entries if those
   entries would have been invalidated by any SFENCE.VMA instruction
   executed by the hart since the speculative execution of the algorithm began.
What I read as if TLB was empty before it will stay empty.

Also, despite of the fact here it is mentioned that when V=0 two-stage address
translation is inactivated:
   The current virtualization mode, denoted V, indicates whether the hart is
   currently executing in a guest. When V=1, the hart is either in virtual
   S-mode (VS-mode), or in virtual U-mode (VU-mode) atop a guest OS running
   in VS-mode. When V=0, the hart is either in M-mode, in HS-mode, or in
   U-mode atop an OS running in HS-mode. The virtualization mode also
   indicates whether two-stage address translation is active (V=1) or
   inactive (V=0).
But on the same side, writing to hgatp register activates it:
   The hgatp register is considered active for the purposes of
   the address-translation algorithm unless the effective privilege mode
   is U and hstatus.HU=0.
And if so + considering that speculation could happen at any time, and
we are in HS-mode, not it U mode then I would say that it could really
speculate into guest mode.


>
>>>> +    data->max_vmid = BIT(vmid_len, U) - 1;
>>>> +    data->disabled = !opt_vmid_enabled || (vmid_len <= 1);
>>> Actually, what exactly does it mean that "VMIDs are disabled"? There's
>>> no enable bit that I could find anywhere. Isn't it rather that in this
>>> case you need to arrange to flush always on VM entry (or always after a
>>> P2M change, depending how the TLB is split between guest and host use)?
>> "VMIDs are disabled" here means that TLB flush will happen each time p2m
>> is changed.
> That's better described as "VMIDs aren't used" then?

It sounds a little bit just like an opposite to "disabled" (i.e. means
basically the same), but I am okay to use "used" instead.

>
>>>> +    if ( g_disabled != data->disabled )
>>>> +    {
>>>> +        printk("%s: VMIDs %sabled.\n", __func__,
>>>> +               data->disabled ? "dis" : "en");
>>>> +        if ( !g_disabled )
>>>> +            g_disabled = data->disabled;
>>> This doesn't match x86 code. g_disabled is a tristate there, which only
>>> the boot CPU would ever write to.
>> Why g_disabled is written only by boot CPU? Does x86 have only two options
>> or VMIDs are enabled for all CPUs or it is disabled for all of them?
> Did you look at the x86 code again, or the patch that I sent for it?
>
>> For RISC-V as I mentioned above it is needed to check all harts as the spec.
>> doesn't explicitly mention that VMIDLEN is equal for all harts...
> Even if in practice x86 systems are symmetric in this regard, you will
> have seen that we support varying values there as well. Up to and
> including ASIDs being in use on some CPUs, but not on others. So that
> code can serve as a reference for you, I think.
>
>>> A clear shortcoming of the x86 code (that you copied) is that the log
>>> message doesn't identify the CPU in question. A sequence of "disabled"
>>> and "enabled" could thus result, without the last one (or in fact any
>>> one) making clear what the overall state is. I think you want to avoid
>>> this from the beginning.
>> ... Thereby it seems like declaration of g_disabled should be moved outside
>> vmid_init() function and add a new function which will return g_disabled
>> value (or just make g_disabled not static and rename to something like
>> g_vmids_disabled).
> No, why? While I didn't Cc you on my patch submission, I specifically
> replied to it with you (alone) on the To: list, just so you can look
> there first before suggesting (sorry) odd things.

I haven't received this e-mail, but I was able to find it on lore.kernel.org.
Thanks.

~ Oleksii


--------------iqbAeYP49t7P0mDsFTqvVc3X
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 8bit



  
    
  
  
    

    
    
    
    
    On 8/6/25 2:05 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 06.08.2025 13:33, Oleksii Kurochko wrote:

    
      
    
        
    On 8/4/25 5:19 PM, Jan Beulich wrote:

    
        
    
          
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
          
    
            
    @@ -148,6 +149,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id,
  
      console_init_postirq();
  
+    vmid_init();

    
          
    
          
    This lives here only temporarily, I assume? Every hart will need to execute
it, and hence (like we have it on x86) this may want to be a central place
elsewhere.

    
        
    
        
    I haven’t checked how it is done on x86; I probably should.

I planned to call it for each hart separately during secondary hart bring-up,
since accessing the|hgatp| register of a hart is required to detect|VMIDLEN|.
Therefore,|vmid_init()| should be called for secondary harts when their
initialization code starts executing.

    
      
    
      
    But is this going to be the only per-hart thing that will need doing? Otherwise
the same larger "container" function may want calling instead.
    
    
    
    
    Yes, it is going to be the only per-hart operation.


    
    
    There is __cpu_up() (not yet upstreamed [1]), which calls
sbi_hsm_hart_start(hartid, boot_addr, hsm_data) to start a hart, and I planned
to place vmid_init() somewhere in the code executed at boot_addr.

[1] https://gitlab.com/xen-project/people/olkur/xen/-/blob/latest/xen/arch/riscv/smpboot.c#L40

    
    
    
    
    
      
    
      
    
        
    
          
    
            
    +{
+    unsigned long vmid_bits;

    
          
    
          
    Why "long" (also for the function return type)?

    
        
    
        
    Because csr_read() returns unsigned long as HGATP register has
'unsigned long' length.

    
      
    
      
    Oh, right, I should have commented on the function return type only.
Yet then I also can't resist stating that this kind of use of a variable,
which initially is assigned a value that doesn't really fit its name, is
easily misleading towards giving such comments.


    
      
    
        
    But it could be done in this way:
     csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
     vmid_bits =  MASK_EXTR(csr_read(CSR_HGATP), HGATP_VMID_MASK);
     vmid_bits = ffs_g(vmid_bits);
     csr_write(CSR_HGATP, old);
And then use uint16_t for vmid_bits and use uin16_t as a return type.

    
      
    
      
    Please check ./CODING_STYLE again as to the use of fixed-width types.
    
    
    
    
    I meant unsigned short, uint16_t was just short to write. I'll try to be
more specific.


    
    
    
      
    

    
      
    
        
    
          
    
            
    +    unsigned long old;
+
+    /* Figure-out number of VMID bits in HW */
+    old = csr_read(CSR_HGATP);
+
+    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
+    vmid_bits = csr_read(CSR_HGATP);
+    vmid_bits =  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);

    
          
    
          
    Nit: Stray blank.


    
          
    
            
    +    vmid_bits = flsl(vmid_bits);
+    csr_write(CSR_HGATP, old);
+
+    /*
+     * We polluted local TLB so flush all guest TLB as
+     * a speculative access can happen at any time.
+     */
+    local_hfence_gvma_all();

    
          
    
          
    There's no guest running. If you wrote hgat.MODE as zero, as per my
understanding now new TLB entries could even purely theoretically appear.

    
        
    
        
    It could be an issue (or, at least, it is recommended) when hgatp.MODE is
changed:
  If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0
  (and rs2 set to either x0 or the VMID) must be executed to order subsequent
  guest translations with the MODE change—even if the old MODE or new MODE
  is Bare.
On other hand it is guaranteed that, at least, on Reset (and so I assume
for power on) that:
  If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE
  fields are reset to 0.

So it seems like if no guest is ran then there is no need even to write
hgatp.MODE as zero, but it might be sense to do that explicitly just to
be sure.

I thought it was possible to have a running guest and perform a CPU hotplug.

    
      
    
      
    But that guest will run on another hart.


    
      
    
        
    In that case, I expect that during the hotplug,|vmidlen_detect()| will be
called and return the|vmid_bits| value, which is used as the active VMID.
At that moment, the local TLB could be speculatively polluted, I think.
Likely, it makes sense to call vmidlen_detect() only once for each hart
during initial bringup.

    
      
    
      
    That may bring you more problems than it solves. You'd need to stash away
the value originally read somewhere. And that somewhere isn't per-CPU data.


    
      
    
        
    
          
    In fact, with no guest running (yet) I'm having a hard time seeing why
you shouldn't be able to simply write the register with just
HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable
whether "old" needs restoring; writing plain zero afterwards ought to
suffice. You're in charcge of the register, after all.

    
        
    
        
    It make sense (but I don't know if it is a possible case) to be sure that
HGATP.MODE remains the same, so there is no need to have TLB flush. If
HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned
above.

If we agreed to keep local_hfence_gvma_all() then I think it isn't really
any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.

Generally if 'old' is guaranteed to be zero (and, probably, it makes sense
to check that in vmidlen_detect() and panic if it isn't zero) and if
vmidlen_detect() function will be called before any guest domain(s) will
be ran then I could agree that we don't need local_hfence_gvma_all() here.

As an option we can do local_hfence_gvma_all() only if 'old' value wasn't
set to zero.

Does it make sense?

    
      
    
      
    Well - I'd like the pre-conditions to be understood better. For example, can
a hart really speculate into guest mode, when the hart is only in the
process of being brought up?
    
    
    
    
    I couldn't explicit words that a hart can't speculate into guest mode
either on bring up or during its work.

But there are some moments in the spec which tells:
  Implementations with virtual memory are permitted to perform address
  translations speculatively and earlier than required by an explicit
  memory access, and are permitted to cache them in address translation
  cache structures—including possibly caching the identity mappings from
  effective address to physical address used in Bare translation modes and
  M-mode.
And here:
  Implementations may also execute the address-translation algorithm
  speculatively at any time, for any virtual address, as long as satp is
  active (as defined in Section 10.1.11). Such speculative executions have
  the effect of pre-populating the address-translation cache.
Where it is explicitly mentioned that speculation can happen in *any time*.
And at the same time:
  Speculative executions of the address-translation algorithm behave as
  non-speculative executions of the algorithm do, except that they must
  not set the dirty bit for a PTE, they must not trigger an exception,
  and they must not create address-translation cache entries if those
  entries would have been invalidated by any SFENCE.VMA instruction
  executed by the hart since the speculative execution of the algorithm began.
What I read as if TLB was empty before it will stay empty.

Also, despite of the fact here it is mentioned that when V=0 two-stage address
translation is inactivated:
  The current virtualization mode, denoted V, indicates whether the hart is
  currently executing in a guest. When V=1, the hart is either in virtual
  S-mode (VS-mode), or in virtual U-mode (VU-mode) atop a guest OS running
  in VS-mode. When V=0, the hart is either in M-mode, in HS-mode, or in
  U-mode atop an OS running in HS-mode. The virtualization mode also
  indicates whether two-stage address translation is active (V=1) or
  inactive (V=0).
But on the same side, writing to hgatp register activates it:
  The hgatp register is considered active for the purposes of
  the address-translation algorithm unless the effective privilege mode
  is U and hstatus.HU=0.
And if so + considering that speculation could happen at any time, and
we are in HS-mode, not it U mode then I would say that it could really
speculate into guest mode.

    
    

    
    
    
    
    
      
    

    
      
    
        
    
          
    
            
    +    data->max_vmid = BIT(vmid_len, U) - 1;
+    data->disabled = !opt_vmid_enabled || (vmid_len <= 1);

    
          
    
          
    Actually, what exactly does it mean that "VMIDs are disabled"? There's
no enable bit that I could find anywhere. Isn't it rather that in this
case you need to arrange to flush always on VM entry (or always after a
P2M change, depending how the TLB is split between guest and host use)?

    
        
    
        
    "VMIDs are disabled" here means that TLB flush will happen each time p2m
is changed.

    
      
    
      
    That's better described as "VMIDs aren't used" then?
    
    
    
    
    It sounds a little bit just like an opposite to "disabled" (i.e. means
basically the same), but I am okay to use "used" instead.


    
    
    
      
    

    
      
    
        
    
          
    
            
    +    if ( g_disabled != data->disabled )
+    {
+        printk("%s: VMIDs %sabled.\n", __func__,
+               data->disabled ? "dis" : "en");
+        if ( !g_disabled )
+            g_disabled = data->disabled;

    
          
    
          
    This doesn't match x86 code. g_disabled is a tristate there, which only
the boot CPU would ever write to.

    
        
    
        
    Why g_disabled is written only by boot CPU? Does x86 have only two options
or VMIDs are enabled for all CPUs or it is disabled for all of them?

    
      
    
      
    Did you look at the x86 code again, or the patch that I sent for it?


    
      
    
        
    For RISC-V as I mentioned above it is needed to check all harts as the spec.
doesn't explicitly mention that VMIDLEN is equal for all harts...

    
      
    
      
    Even if in practice x86 systems are symmetric in this regard, you will
have seen that we support varying values there as well. Up to and
including ASIDs being in use on some CPUs, but not on others. So that
code can serve as a reference for you, I think.


    
      
    
        
    
          
    A clear shortcoming of the x86 code (that you copied) is that the log
message doesn't identify the CPU in question. A sequence of "disabled"
and "enabled" could thus result, without the last one (or in fact any
one) making clear what the overall state is. I think you want to avoid
this from the beginning.

    
        
    
        
    ... Thereby it seems like declaration of g_disabled should be moved outside
vmid_init() function and add a new function which will return g_disabled
value (or just make g_disabled not static and rename to something like
g_vmids_disabled).

    
      
    
      
    No, why? While I didn't Cc you on my patch submission, I specifically
replied to it with you (alone) on the To: list, just so you can look
there first before suggesting (sorry) odd things.
    
    
    
    
    I haven't received this e-mail, but I was able to find it on lore.kernel.org.
Thanks.

~ Oleksii
    
    
    
  


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Message-ID: <14e1c224-c648-41bb-97c6-ec63596bd38b@gmail.com>
Date: Wed, 6 Aug 2025 12:50:02 -0400
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Subject: Re: [PATCH v3 03/20] xen/riscv: introduce VMID allocation and
 manegement
To: Oleksii Kurochko ,
 Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 
 
 
 <6ddee574-6fe2-4de7-b000-a3af0b2c9d12@suse.com>
 
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From: Demi Marie Obenour 
To: Oleksii Kurochko ,
 Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
Message-ID: <14e1c224-c648-41bb-97c6-ec63596bd38b@gmail.com>
Subject: Re: [PATCH v3 03/20] xen/riscv: introduce VMID allocation and
 manegement
References: 
 
 
 
 <6ddee574-6fe2-4de7-b000-a3af0b2c9d12@suse.com>
 
In-Reply-To: 

--------------UCSiGg9IZeyNJvXl8IjE07zq
Content-Type: multipart/mixed; boundary="------------UAOgisYUERiBA07qRNHzbgMk"

--------------UAOgisYUERiBA07qRNHzbgMk
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On 8/6/25 12:24, Oleksii Kurochko wrote:
>=20
> On 8/6/25 2:05 PM, Jan Beulich wrote:
>> On 06.08.2025 13:33, Oleksii Kurochko wrote:
>>> On 8/4/25 5:19 PM, Jan Beulich wrote:
>>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>>> @@ -148,6 +149,8 @@ void __init noreturn start_xen(unsigned long bo=
otcpu_id,
>>>>>   =20
>>>>>        console_init_postirq();
>>>>>   =20
>>>>> +    vmid_init();
>>>> This lives here only temporarily, I assume? Every hart will need to =
execute
>>>> it, and hence (like we have it on x86) this may want to be a central=
 place
>>>> elsewhere.
>>> I haven=E2=80=99t checked how it is done on x86; I probably should.
>>>
>>> I planned to call it for each hart separately during secondary hart b=
ring-up,
>>> since accessing the|hgatp| register of a hart is required to detect|V=
MIDLEN|.
>>> Therefore,|vmid_init()| should be called for secondary harts when the=
ir
>>> initialization code starts executing.
>> But is this going to be the only per-hart thing that will need doing? =
Otherwise
>> the same larger "container" function may want calling instead.
>=20
> Yes, it is going to be the only per-hart operation.
>=20
> There is|__cpu_up()| (not yet upstreamed [1]), which calls
> |sbi_hsm_hart_start(hartid, boot_addr, hsm_data)| to start a hart, and =
I planned
> to place|vmid_init()| somewhere in the code executed at|boot_addr|.
>=20
> [1]https://gitlab.com/xen-project/people/olkur/xen/-/blob/latest/xen/ar=
ch/riscv/smpboot.c#L40
>=20
>>>>> +{
>>>>> +    unsigned long vmid_bits;
>>>> Why "long" (also for the function return type)?
>>> Because csr_read() returns unsigned long as HGATP register has
>>> 'unsigned long' length.
>> Oh, right, I should have commented on the function return type only.
>> Yet then I also can't resist stating that this kind of use of a variab=
le,
>> which initially is assigned a value that doesn't really fit its name, =
is
>> easily misleading towards giving such comments.
>>
>>> But it could be done in this way:
>>>       csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>>       vmid_bits =3D  MASK_EXTR(csr_read(CSR_HGATP), HGATP_VMID_MASK);=

>>>       vmid_bits =3D ffs_g(vmid_bits);
>>>       csr_write(CSR_HGATP, old);
>>> And then use uint16_t for vmid_bits and use uin16_t as a return type.=

>> Please check ./CODING_STYLE again as to the use of fixed-width types.
>=20
> I meant unsigned short, uint16_t was just short to write. I'll try to b=
e
> more specific.
>=20
>>
>>>>> +    unsigned long old;
>>>>> +
>>>>> +    /* Figure-out number of VMID bits in HW */
>>>>> +    old =3D csr_read(CSR_HGATP);
>>>>> +
>>>>> +    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>>>> +    vmid_bits =3D csr_read(CSR_HGATP);
>>>>> +    vmid_bits =3D  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);
>>>> Nit: Stray blank.
>>>>
>>>>> +    vmid_bits =3D flsl(vmid_bits);
>>>>> +    csr_write(CSR_HGATP, old);
>>>>> +
>>>>> +    /*
>>>>> +     * We polluted local TLB so flush all guest TLB as
>>>>> +     * a speculative access can happen at any time.
>>>>> +     */
>>>>> +    local_hfence_gvma_all();
>>>> There's no guest running. If you wrote hgat.MODE as zero, as per my
>>>> understanding now new TLB entries could even purely theoretically ap=
pear.
>>> It could be an issue (or, at least, it is recommended) when hgatp.MOD=
E is
>>> changed:
>>>    If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=
=3Dx0
>>>    (and rs2 set to either x0 or the VMID) must be executed to order s=
ubsequent
>>>    guest translations with the MODE change=E2=80=94even if the old MO=
DE or new MODE
>>>    is Bare.
>>> On other hand it is guaranteed that, at least, on Reset (and so I ass=
ume
>>> for power on) that:
>>>    If the hypervisor extension is implemented, the hgatp.MODE and vsa=
tp.MODE
>>>    fields are reset to 0.
>>>
>>> So it seems like if no guest is ran then there is no need even to wri=
te
>>> hgatp.MODE as zero, but it might be sense to do that explicitly just =
to
>>> be sure.
>>>
>>> I thought it was possible to have a running guest and perform a CPU h=
otplug.
>> But that guest will run on another hart.
>>
>>> In that case, I expect that during the hotplug,|vmidlen_detect()| wil=
l be
>>> called and return the|vmid_bits| value, which is used as the active V=
MID.
>>> At that moment, the local TLB could be speculatively polluted, I thin=
k.
>>> Likely, it makes sense to call vmidlen_detect() only once for each ha=
rt
>>> during initial bringup.
>> That may bring you more problems than it solves. You'd need to stash a=
way
>> the value originally read somewhere. And that somewhere isn't per-CPU =
data.
>>
>>>> In fact, with no guest running (yet) I'm having a hard time seeing w=
hy
>>>> you shouldn't be able to simply write the register with just
>>>> HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionabl=
e
>>>> whether "old" needs restoring; writing plain zero afterwards ought t=
o
>>>> suffice. You're in charcge of the register, after all.
>>> It make sense (but I don't know if it is a possible case) to be sure =
that
>>> HGATP.MODE remains the same, so there is no need to have TLB flush. I=
f
>>> HGATP.MODE is changed then it will be needed to do TLB flush as I men=
tioned
>>> above.
>>>
>>> If we agreed to keep local_hfence_gvma_all() then I think it isn't re=
ally
>>> any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.
>>>
>>> Generally if 'old' is guaranteed to be zero (and, probably, it makes =
sense
>>> to check that in vmidlen_detect() and panic if it isn't zero) and if
>>> vmidlen_detect() function will be called before any guest domain(s) w=
ill
>>> be ran then I could agree that we don't need local_hfence_gvma_all() =
here.
>>>
>>> As an option we can do local_hfence_gvma_all() only if 'old' value wa=
sn't
>>> set to zero.
>>>
>>> Does it make sense?
>> Well - I'd like the pre-conditions to be understood better. For exampl=
e, can
>> a hart really speculate into guest mode, when the hart is only in the
>> process of being brought up?
>=20
> I couldn't explicit words that a hart can't speculate into guest mode
> either on bring up or during its work.
>=20
> But there are some moments in the spec which tells:
>    Implementations with virtual memory are permitted to perform address=

>    translations speculatively and earlier than required by an explicit
>    memory access, and are permitted to cache them in address translatio=
n
>    cache structures=E2=80=94including possibly caching the identity map=
pings from
>    effective address to physical address used in Bare translation modes=
 and
>    M-mode.
> And here:
>    Implementations may also execute the address-translation algorithm
>    speculatively at any time, for any virtual address, as long as satp =
is
>    active (as defined in Section 10.1.11). Such speculative executions =
have
>    the effect of pre-populating the address-translation cache.
> Where it is explicitly mentioned that speculation can happen in *any ti=
me*.
> And at the same time:
>    Speculative executions of the address-translation algorithm behave a=
s
>    non-speculative executions of the algorithm do, except that they mus=
t
>    not set the dirty bit for a PTE, they must not trigger an exception,=

>    and they must not create address-translation cache entries if those
>    entries would have been invalidated by any SFENCE.VMA instruction
>    executed by the hart since the speculative execution of the algorith=
m began.
> What I read as if TLB was empty before it will stay empty.

I read that as "flushing the TLB invalidates entries created by speculati=
ve
execution before the TLB flush".  That is the bare minimum needed for TLB=

flushing to work.  You have to do the TLB flush *after* changing the PTEs=
,
not before.

This is true on at least x86 but I expect it to hold in general.
--=20
Sincerely,
Demi Marie Obenour (she/her/hers)
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From: Jens Wiklander 
Date: Wed, 6 Aug 2025 17:54:59 +0100
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Subject: Re: [PATCH v7 3/6] xen/arm: ffa: Introduce VM to VM support
To: Bertrand Marquis 
Cc: xen-devel@lists.xenproject.org, 
	Volodymyr Babchuk , Stefano Stabellini , 
	Julien Grall , Michal Orzel 
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Hi Bertrand,

On Thu, Jul 17, 2025 at 1:11=E2=80=AFPM Bertrand Marquis
 wrote:
>
> Create a CONFIG_FFA_VM_TO_VM parameter to activate FFA communication
> between VMs.
> When activated list VMs in the system with FF-A support in part_info_get.
>
> When VM to VM is activated, Xen will be tainted as Insecure and a
> message is displayed to the user during the boot as there is no
> filtering of VMs in FF-A so any VM can communicate or see any other VM
> in the system.
>
> WARNING: There is no filtering for now and all VMs are listed !!
>
> This patch is reorganizing the ffa_ctx structure to make clear which
> lock is protecting what parts.
>
> This patch is introducing a chain list of the ffa_ctx with a FFA Version
> negociated allowing to create the partinfo results for VMs in parallel

negotiated

> by using rwlock which only ensure addition/removal of entries are
> protected.
>
> Signed-off-by: Bertrand Marquis 
> ---
> Changes in v7:
> - protect ffa_ctx list with a rw lock to allow several partinfo_get in
>   parallel but protect adding/removing entries.
> Changes in v6:
> - remove ACCESS_ONCE for guest_vers access and take the context lock
>   before modifying it
> - move guest_vers in context declaration to fields protected by the
>   context lock and add a comment to state that lock in only needed when
>   modifying it
> Changes in v5:
> - remove invalid comment about 1.1 firmware support
> - rename variables from d and dom to curr_d and dest_d (Julien)
> - add a TODO in the code for potential holding for long of the CPU
>   (Julien)
> - use an atomic global variable to store the number of VMs instead of
>   recomputing the value each time (Julien)
> - add partinfo information in ffa_ctx (id, cpus and 64bit) and create a
>   chain list of ctx. Use this chain list to create the partinfo result
>   without holding a global lock to prevent concurrency issues.
> - Move some changes in a preparation patch modifying partinfo for sps to
>   reduce this patch size and make the review easier
> Changes in v4:
> - properly handle SPMC version 1.0 header size case in partinfo_get
> - switch to local counting variables instead of *pointer +=3D 1 form
> - coding style issue with missing spaces in if ()
> Changes in v3:
> - break partinfo_get in several sub functions to make the implementation
>   easier to understand and lock handling easier
> - rework implementation to check size along the way and prevent previous
>   implementation limits which had to check that the number of VMs or SPs
>   did not change
> - taint Xen as INSECURE when VM to VM is enabled
> Changes in v2:
> - Switch ifdef to IS_ENABLED
> - dom was not switched to d as requested by Jan because there is already
>   a variable d pointing to the current domain and it must not be
>   shadowed.
> ---
>  xen/arch/arm/tee/Kconfig        |  11 +++
>  xen/arch/arm/tee/ffa.c          |  47 +++++++++++++
>  xen/arch/arm/tee/ffa_partinfo.c | 100 ++++++++++++++++++++++++---
>  xen/arch/arm/tee/ffa_private.h  | 117 ++++++++++++++++++++++++++------
>  4 files changed, 245 insertions(+), 30 deletions(-)
>
> diff --git a/xen/arch/arm/tee/Kconfig b/xen/arch/arm/tee/Kconfig
> index c5b0f88d7522..88a4c4c99154 100644
> --- a/xen/arch/arm/tee/Kconfig
> +++ b/xen/arch/arm/tee/Kconfig
> @@ -28,5 +28,16 @@ config FFA
>
>           [1] https://developer.arm.com/documentation/den0077/latest
>
> +config FFA_VM_TO_VM
> +    bool "Enable FF-A between VMs (UNSUPPORTED)" if UNSUPPORTED
> +    default n
> +    depends on FFA
> +    help
> +      This option enables to use FF-A between VMs.
> +      This is experimental and there is no access control so any
> +      guest can communicate with any other guest.
> +
> +      If unsure, say N.
> +
>  endmenu
>
> diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c
> index 3bbdd7168a6b..be71eda4869f 100644
> --- a/xen/arch/arm/tee/ffa.c
> +++ b/xen/arch/arm/tee/ffa.c
> @@ -118,6 +118,13 @@ void *ffa_tx __read_mostly;
>  DEFINE_SPINLOCK(ffa_rx_buffer_lock);
>  DEFINE_SPINLOCK(ffa_tx_buffer_lock);
>
> +struct list_head ffa_ctx_head;
> +/* RW Lock to protect addition/removal and reading in ffa_ctx_head */
> +rwlock_t ffa_ctx_list_rwlock;
> +
> +#ifdef CONFIG_FFA_VM_TO_VM
> +atomic_t ffa_vm_count;
> +#endif
>
>  /* Used to track domains that could not be torn down immediately. */
>  static struct timer ffa_teardown_timer;
> @@ -151,6 +158,7 @@ static void handle_version(struct cpu_user_regs *regs=
)
>      struct domain *d =3D current->domain;
>      struct ffa_ctx *ctx =3D d->arch.tee;
>      uint32_t vers =3D get_user_reg(regs, 1);
> +    uint32_t old_vers;
>
>      /*
>       * Guest will use the version it requested if it is our major and mi=
nor
> @@ -160,10 +168,23 @@ static void handle_version(struct cpu_user_regs *re=
gs)
>       */
>      if ( FFA_VERSION_MAJOR(vers) =3D=3D FFA_MY_VERSION_MAJOR )
>      {
> +        spin_lock(&ctx->lock);
> +        old_vers =3D ctx->guest_vers;
> +
>          if ( FFA_VERSION_MINOR(vers) > FFA_MY_VERSION_MINOR )
>              ctx->guest_vers =3D FFA_MY_VERSION;
>          else
>              ctx->guest_vers =3D vers;
> +        spin_unlock(&ctx->lock);
> +
> +        if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !old_vers )
> +        {
> +            /* One more VM with FF-A support available */
> +            inc_ffa_vm_count();
> +            write_lock(&ffa_ctx_list_rwlock);
> +            list_add_tail(&ctx->ctx_list, &ffa_ctx_head);
> +            write_unlock(&ffa_ctx_list_rwlock);
> +        }
>      }
>      ffa_set_regs(regs, FFA_MY_VERSION, 0, 0, 0, 0, 0, 0, 0);
>  }
> @@ -345,6 +366,10 @@ static int ffa_domain_init(struct domain *d)
>      ctx->teardown_d =3D d;
>      INIT_LIST_HEAD(&ctx->shm_list);
>
> +    ctx->ffa_id =3D ffa_get_vm_id(d);
> +    ctx->num_vcpus =3D d->max_vcpus;
> +    ctx->is_64bit =3D is_64bit_domain(d);
> +
>      /*
>       * ffa_domain_teardown() will be called if ffa_domain_init() returns=
 an
>       * error, so no need for cleanup in this function.
> @@ -421,6 +446,14 @@ static int ffa_domain_teardown(struct domain *d)
>      if ( !ctx )
>          return 0;
>
> +    if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && ctx->guest_vers )
> +    {
> +        dec_ffa_vm_count();
> +        write_lock(&ffa_ctx_list_rwlock);
> +        list_del(&ctx->ctx_list);
> +        write_unlock(&ffa_ctx_list_rwlock);
> +    }
> +
>      ffa_rxtx_domain_destroy(d);
>      ffa_notif_domain_destroy(d);
>
> @@ -464,6 +497,18 @@ static bool ffa_probe(void)
>      printk(XENLOG_INFO "ARM FF-A Mediator version %u.%u\n",
>             FFA_MY_VERSION_MAJOR, FFA_MY_VERSION_MINOR);
>
> +    if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) )
> +    {
> +        /*
> +         * When FFA VM to VM is enabled, the current implementation does=
 not
> +         * offer any way to limit which VM can communicate with which VM=
 using
> +         * FF-A.
> +         * Signal this in the xen console and taint the system as insecu=
re.
> +         * TODO: Introduce a solution to limit what a VM can do through =
FFA.
> +         */
> +        printk(XENLOG_ERR "ffa: VM to VM is enabled, system is insecure =
!!\n");
> +        add_taint(TAINT_MACHINE_INSECURE);
> +    }
>      /*
>       * psci_init_smccc() updates this value with what's reported by EL-3
>       * or secure world.
> @@ -538,6 +583,8 @@ static bool ffa_probe(void)
>
>      ffa_notif_init();
>      INIT_LIST_HEAD(&ffa_teardown_head);
> +    INIT_LIST_HEAD(&ffa_ctx_head);
> +    rwlock_init(&ffa_ctx_list_rwlock);
>      init_timer(&ffa_teardown_timer, ffa_teardown_timer_callback, NULL, 0=
);
>
>      return true;
> diff --git a/xen/arch/arm/tee/ffa_partinfo.c b/xen/arch/arm/tee/ffa_parti=
nfo.c
> index dfa0b23eaf38..fa56b1587e3b 100644
> --- a/xen/arch/arm/tee/ffa_partinfo.c
> +++ b/xen/arch/arm/tee/ffa_partinfo.c
> @@ -150,6 +150,73 @@ out:
>      return ret;
>  }
>
> +static int32_t ffa_get_vm_partinfo(uint32_t *vm_count, void *dst_buf,
> +                                   void *end_buf, uint32_t dst_size)
> +{
> +    struct ffa_ctx *curr_ctx =3D current->domain->arch.tee;
> +    struct ffa_ctx *dest_ctx;
> +    uint32_t count =3D 0;
> +    int32_t ret =3D FFA_RET_OK;
> +
> +    /*
> +     * There could potentially be a lot of VMs in the system and we coul=
d
> +     * hold the CPU for long here.
> +     * Right now there is no solution in FF-A specification to split
> +     * the work in this case.
> +     * TODO: Check how we could delay the work or have preemption checks=
.
> +     */
> +    read_lock(&ffa_ctx_list_rwlock);
> +    list_for_each_entry(dest_ctx, &ffa_ctx_head, ctx_list)
> +    {
> +        /*
> +         * Do not include an entry for the caller VM as the spec is not
> +         * clearly mandating it and it is not supported by Linux.
> +         */
> +        if ( dest_ctx !=3D curr_ctx )
> +        {
> +            /*
> +             * We do not have UUID info for VMs so use
> +             * the 1.0 structure so that we set UUIDs to
> +             * zero using memset
> +             */
> +            struct ffa_partition_info_1_0 info;
> +
> +            if  ( dst_buf > (end_buf - dst_size) )
> +            {
> +                ret =3D FFA_RET_NO_MEMORY;
> +                goto out;
> +            }
> +
> +            /*
> +             * Context might has been removed since we go it or being re=
moved
> +             * right now so we might return information for a VM not exi=
sting
> +             * anymore. This is acceptable as we return a view of the sy=
stem
> +             * which could change at any time.
> +             */
> +            info.id =3D dest_ctx->ffa_id;
> +            info.execution_context =3D dest_ctx->num_vcpus;
> +            info.partition_properties =3D FFA_PART_VM_PROP;
> +            if ( dest_ctx->is_64bit )
> +                info.partition_properties |=3D FFA_PART_PROP_AARCH64_STA=
TE;
> +
> +            memcpy(dst_buf, &info, MIN(sizeof(info), dst_size));
> +
> +            if ( dst_size > sizeof(info) )
> +                memset(dst_buf + sizeof(info), 0,
> +                       dst_size - sizeof(info));
> +
> +            dst_buf +=3D dst_size;
> +            count++;
> +        }
> +    }
> +    *vm_count =3D count;
> +
> +out:
> +    read_unlock(&ffa_ctx_list_rwlock);
> +
> +    return ret;
> +}
> +
>  void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
>  {
>      int32_t ret =3D FFA_RET_OK;
> @@ -164,7 +231,7 @@ void ffa_handle_partition_info_get(struct cpu_user_re=
gs *regs)
>      };
>      uint32_t dst_size =3D 0;
>      void *dst_buf, *end_buf;
> -    uint32_t ffa_sp_count =3D 0;
> +    uint32_t ffa_vm_count =3D 0, ffa_sp_count =3D 0;
>
>      /*
>       * If the guest is v1.0, he does not get back the entry size so we m=
ust
> @@ -191,15 +258,18 @@ void ffa_handle_partition_info_get(struct cpu_user_=
regs *regs)
>          }
>
>          if ( ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) )
> +        {
>              ret =3D ffa_get_sp_count(uuid, &ffa_sp_count);
> +            if ( ret )
> +                goto out;
> +        }
>
> -        goto out;
> -    }
> +        /*
> +         * Do not count the caller VM as the spec is not clearly mandati=
ng it
> +         * and it is not supported by Linux.
> +         */
> +        ffa_vm_count =3D get_ffa_vm_count() - 1;
>
> -    if ( !ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) )
> -    {
> -        /* Just give an empty partition list to the caller */
> -        ret =3D FFA_RET_OK;
>          goto out;
>      }
>
> @@ -224,9 +294,19 @@ void ffa_handle_partition_info_get(struct cpu_user_r=
egs *regs)
>          goto out_rx_release;
>      }
>
> -    ret =3D ffa_get_sp_partinfo(uuid, &ffa_sp_count, dst_buf, end_buf,
> -                              dst_size);
> +    if ( ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) )
> +    {
> +        ret =3D ffa_get_sp_partinfo(uuid, &ffa_sp_count, dst_buf, end_bu=
f,
> +                                  dst_size);
> +
> +        if ( ret )
> +            goto out_rx_release;
> +
> +        dst_buf +=3D ffa_sp_count * dst_size;
> +    }
>
> +    if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) )
> +        ret =3D ffa_get_vm_partinfo(&ffa_vm_count, dst_buf, end_buf, dst=
_size);
>
>  out_rx_release:
>      if ( ret )
> @@ -235,7 +315,7 @@ out:
>      if ( ret )
>          ffa_set_regs_error(regs, ret);
>      else
> -        ffa_set_regs_success(regs, ffa_sp_count, dst_size);
> +        ffa_set_regs_success(regs, ffa_sp_count + ffa_vm_count, dst_size=
);
>  }
>
>  static int32_t ffa_direct_req_send_vm(uint16_t sp_id, uint16_t vm_id,
> diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_privat=
e.h
> index 0a9c1082db28..1a1dcabcdc28 100644
> --- a/xen/arch/arm/tee/ffa_private.h
> +++ b/xen/arch/arm/tee/ffa_private.h
> @@ -195,6 +195,18 @@
>   */
>  #define FFA_PARTITION_INFO_GET_COUNT_FLAG BIT(0, U)
>
> +/*
> + * Partition properties we give for a normal world VM:
> + * - can send direct message but not receive them
> + * - can handle indirect messages
> + * - can receive notifications
> + * 32/64 bit flag is set depending on the VM
> + */
> +#define FFA_PART_VM_PROP    (FFA_PART_PROP_DIRECT_REQ_SEND | \
> +                             FFA_PART_PROP_INDIRECT_MSGS | \
> +                             FFA_PART_PROP_RECV_NOTIF | \
> +                             FFA_PART_PROP_IS_PE_ID)
> +
>  /* Flags used in calls to FFA_NOTIFICATION_GET interface  */
>  #define FFA_NOTIF_FLAG_BITMAP_SP        BIT(0, U)
>  #define FFA_NOTIF_FLAG_BITMAP_VM        BIT(1, U)
> @@ -297,36 +309,72 @@ struct ffa_ctx_notif {
>  };
>
>  struct ffa_ctx {
> -    void *rx;
> -    const void *tx;
> -    struct page_info *rx_pg;
> -    struct page_info *tx_pg;
> +    /*
> +     * Chain list of all FF-A contexts.
> +     * As we might have several read from the list of context through pa=
rallel
> +     * partinfo_get but fewer additions/removal as those happen only dur=
ing a
> +     * version negociation or guest shutdown, access to this list is pro=
tected

negotiation

With these two typos fixed, please apply:
Reviewed-by: Jens Wiklander 

Cheers,
Jens

> +     * through a rwlock (addition/removal with write lock, reading throu=
gh a
> +     * read lock).
> +     */
> +    struct list_head ctx_list; /* chain list of all FF-A contexts */
> +
> +    /*
> +     * Data access unlocked (mainly for part_info_get in VM to VM).
> +     * Those should be set before the ctx is added in the list.
> +     */
> +    /* FF-A Endpoint ID */
> +    uint16_t ffa_id;
> +    uint16_t num_vcpus;
> +    bool is_64bit;
> +
> +    /*
> +     * Global data accessed atomically or using ACCES_ONCE.
> +     */
> +    struct ffa_ctx_notif notif;
> +
> +    /*
> +     * Global data accessed with lock locked.
> +     */
> +    spinlock_t lock;
> +    /*
> +     * FF-A version negociated by the guest, only modifications to
> +     * this field are done with the lock held as this is expected to
> +     * be done once at init by a guest.
> +     */
> +    uint32_t guest_vers;
>      /* Number of 4kB pages in each of rx/rx_pg and tx/tx_pg */
>      unsigned int page_count;
> -    /* FF-A version used by the guest */
> -    uint32_t guest_vers;
> -    bool rx_is_free;
> -    /* Used shared memory objects, struct ffa_shm_mem */
> -    struct list_head shm_list;
>      /* Number of allocated shared memory object */
>      unsigned int shm_count;
> -    struct ffa_ctx_notif notif;
> +    /* Used shared memory objects, struct ffa_shm_mem */
> +    struct list_head shm_list;
> +
>      /*
> -     * tx_lock is used to serialize access to tx
> -     * rx_lock is used to serialize access to rx_is_free
> -     * lock is used for the rest in this struct
> +     * Rx buffer, accessed with rx_lock locked.
> +     * rx_is_free is used to serialize access.
>       */
> -    spinlock_t tx_lock;
>      spinlock_t rx_lock;
> -    spinlock_t lock;
> -    /* Used if domain can't be torn down immediately */
> +    bool rx_is_free;
> +    void *rx;
> +    struct page_info *rx_pg;
> +
> +    /*
> +     * Tx buffer, access with tx_lock locked.
> +     */
> +    spinlock_t tx_lock;
> +    const void *tx;
> +    struct page_info *tx_pg;
> +
> +
> +    /*
> +     * Domain teardown handling if data shared or used by other domains
> +     * do not allow to teardown the domain immediately.
> +     */
>      struct domain *teardown_d;
>      struct list_head teardown_list;
>      s_time_t teardown_expire;
> -    /*
> -     * Used for ffa_domain_teardown() to keep track of which SPs should =
be
> -     * notified that this guest is being destroyed.
> -     */
> +    /* Keep track of SPs that should be notified of VM destruction */
>      unsigned long *vm_destroy_bitmap;
>  };
>
> @@ -336,6 +384,12 @@ extern spinlock_t ffa_rx_buffer_lock;
>  extern spinlock_t ffa_tx_buffer_lock;
>  extern DECLARE_BITMAP(ffa_fw_abi_supported, FFA_ABI_BITMAP_SIZE);
>
> +extern struct list_head ffa_ctx_head;
> +extern rwlock_t ffa_ctx_list_rwlock;
> +#ifdef CONFIG_FFA_VM_TO_VM
> +extern atomic_t ffa_vm_count;
> +#endif
> +
>  bool ffa_shm_domain_destroy(struct domain *d);
>  void ffa_handle_mem_share(struct cpu_user_regs *regs);
>  int ffa_handle_mem_reclaim(uint64_t handle, uint32_t flags);
> @@ -368,6 +422,29 @@ int ffa_handle_notification_set(struct cpu_user_regs=
 *regs);
>  void ffa_handle_msg_send_direct_req(struct cpu_user_regs *regs, uint32_t=
 fid);
>  int32_t ffa_handle_msg_send2(struct cpu_user_regs *regs);
>
> +#ifdef CONFIG_FFA_VM_TO_VM
> +static inline uint16_t get_ffa_vm_count(void)
> +{
> +    return atomic_read(&ffa_vm_count);
> +}
> +
> +static inline void inc_ffa_vm_count(void)
> +{
> +    atomic_inc(&ffa_vm_count);
> +}
> +
> +static inline void dec_ffa_vm_count(void)
> +{
> +    ASSERT(atomic_read(&ffa_vm_count) > 0);
> +    atomic_dec(&ffa_vm_count);
> +}
> +#else
> +/* Only count the caller VM */
> +#define get_ffa_vm_count()  ((uint16_t)1UL)
> +#define inc_ffa_vm_count()  do {} while(0)
> +#define dec_ffa_vm_count()  do {} while(0)
> +#endif
> +
>  static inline uint16_t ffa_get_vm_id(const struct domain *d)
>  {
>      /* +1 since 0 is reserved for the hypervisor in FF-A */
> --
> 2.47.1
>


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        Wed, 06 Aug 2025 09:55:45 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Frediano Ziglio ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Ross Lagerwall 
Subject: [PATCH] x86/domctl: Reject XEN_DOMCTL_hypercall_init against oneself
Date: Wed,  6 Aug 2025 17:55:43 +0100
Message-Id: <20250806165543.169140-1-andrew.cooper3@citrix.com>
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A toolstack is expected to use XEN_DOMCTL_hypercall_init where applicable to
construct a new guest, but is absolutely not expected to use it against
itself.  Kernels have a stable ABI for accessing the same functionality, via
MSR 0x40000000.

Found when auditing hypercalls for Host UEFI-SecureBoot safety.

Reported-by: Frediano Ziglio 
Signed-off-by: Andrew Cooper 
---
CC: Anthony PERARD 
CC: Michal Orzel 
CC: Jan Beulich 
CC: Julien Grall 
CC: Roger Pau Monné 
CC: Stefano Stabellini 
CC: Ross Lagerwall 
CC: Frediano Ziglio 
---
 xen/arch/x86/domctl.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 3044f706de1c..bf1ee4ed51a0 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -372,6 +372,14 @@ long arch_do_domctl(
         struct page_info *page;
         void *hypercall_page;
 
+        /*
+         * Kernels should use the MSR method to get a hypercall page.  The
+         * toolstack should not be using the DOMCTL on itself.
+         */
+        ret = -EINVAL;
+        if ( d == currd )
+            break;
+
         page = get_page_from_gfn(d, gmfn, NULL, P2M_ALLOC);
 
         if ( !page || !get_page_type(page, PGT_writable_page) )

base-commit: 68797a710f4e91cc09fe5650ee14478316010f88
-- 
2.39.5



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Date: Wed, 6 Aug 2025 18:18:56 +0100
MIME-Version: 1.0
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Subject: Re: [PATCH] x86/domctl: Reject XEN_DOMCTL_hypercall_init against
 oneself
To: Xen-devel 
Cc: Frediano Ziglio ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 Ross Lagerwall ,
 Daniel Smith ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= 
References: <20250806165543.169140-1-andrew.cooper3@citrix.com>
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From: Andrew Cooper 
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In-Reply-To: <20250806165543.169140-1-andrew.cooper3@citrix.com>
Content-Type: text/plain; charset=UTF-8
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On 06/08/2025 5:55 pm, Andrew Cooper wrote:
> A toolstack is expected to use XEN_DOMCTL_hypercall_init where applicable to
> construct a new guest, but is absolutely not expected to use it against
> itself.  Kernels have a stable ABI for accessing the same functionality, via
> MSR 0x40000000.
>
> Found when auditing hypercalls for Host UEFI-SecureBoot safety.
>
> Reported-by: Frediano Ziglio 
> Signed-off-by: Andrew Cooper 
> ---
> CC: Anthony PERARD 
> CC: Michal Orzel 
> CC: Jan Beulich 
> CC: Julien Grall 
> CC: Roger Pau Monné 
> CC: Stefano Stabellini 
> CC: Ross Lagerwall 
> CC: Frediano Ziglio 

It's worth nothing that the observations which lead to this mean it's
impossible to support multiple TCB domains without Flask.

Imagine that we did have two control domains and they could operate on
each other.  It's inappropriate for the domain's kernel to be auditing
which domid's are which privilege.

Flask can let Xen express that level of control, and in practice the
system would need configuring with a privilege hierarchy. 
Equally-powerful domains which can operate on each other simply doesn't
make sense from a system point of view.

But, as Flask is not supported yet in Xen, the Host UEFI-SB security
policy is going to have to be limited to a single all-power dom0 in the
short term.

~Andrew


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From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 5/8] emul/vuart-ns16550: introduce NS16550-compatible
 UART emulator (x86)
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-6-dmukhin@ford.com>
 
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On Wed, Aug 06, 2025 at 05:06:24PM +0200, Roger Pau Monné wrote:
> On Thu, Jul 31, 2025 at 07:22:06PM +0000, dmkhn@proton.me wrote:
> > From: Denis Mukhin  
> Overall I agree for Jan it would be better if this patch could be
> split into somehow smaller units.  Is this something feasible?  We
> don't want a patch for each register handle, but maybe you cna somehow
> grup those into functional sections, so that patches can be < 250
> lines?

I've been thinking about this, would it be feasible to have a first
patch that introduces all the boilerplate, like adding the domain
create option, wire the libxl bits, but doesn't actually add any
emulation at all.  Then further patches could fill in the emulation
slowly, starting with a patch to register the IO port handlers
(initially would be empty functions), and progressing from the basic
parts (uart initialization maybe?) towards the end implementation that
you have here.

Thanks, Roger.


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Date: Wed, 6 Aug 2025 14:31:32 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 01/16] dma-mapping: introduce new DMA attribute to
 indicate MMIO memory
Message-ID: <20250806173132.GA184255@nvidia.com>
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On Mon, Aug 04, 2025 at 03:42:35PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> This patch introduces the DMA_ATTR_MMIO attribute to mark DMA buffers
> that reside in memory-mapped I/O (MMIO) regions, such as device BARs
> exposed through the host bridge, which are accessible for peer-to-peer
> (P2P) DMA.
> 
> This attribute is especially useful for exporting device memory to other
> devices for DMA without CPU involvement, and avoids unnecessary or
> potentially detrimental CPU cache maintenance calls.

It is worth mentioning here that dma_map_resource() and DMA_ATTR_MMIO
are intended to be the same thing.

> --- a/Documentation/core-api/dma-attributes.rst
> +++ b/Documentation/core-api/dma-attributes.rst
> @@ -130,3 +130,10 @@ accesses to DMA buffers in both privileged "supervisor" and unprivileged
>  subsystem that the buffer is fully accessible at the elevated privilege
>  level (and ideally inaccessible or at least read-only at the
>  lesser-privileged levels).
> +
> +DMA_ATTR_MMIO
> +-------------
> +
> +This attribute is especially useful for exporting device memory to other
> +devices for DMA without CPU involvement, and avoids unnecessary or
> +potentially detrimental CPU cache maintenance calls.

How about

This attribute indicates the physical address is not normal system
memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page()
functions, it may not be cachable, and access using CPU load/store
instructions may not be allowed.

Usually this will be used to describe MMIO addresses, or other non
cachable register addresses. When DMA mapping this sort of address we
call the operation Peer to Peer as a one device is DMA'ing to another
device. For PCI devices the p2pdma APIs must be used to determine if
DMA_ATTR_MMIO is appropriate.

For architectures that require cache flushing for DMA coherence
DMA_ATTR_MMIO will not perform any cache flushing. The address
provided must never be mapped cachable into the CPU.

> +/*
> + * DMA_ATTR_MMIO - Indicates memory-mapped I/O (MMIO) region for DMA mapping
> + *
> + * This attribute is used for MMIO memory regions that are exposed through
> + * the host bridge and are accessible for peer-to-peer (P2P) DMA. Memory
> + * marked with this attribute is not system RAM and may represent device
> + * BAR windows or peer-exposed memory.
> + *
> + * Typical usage is for mapping hardware memory BARs or exporting device
> + * memory to other devices for DMA without involving main system RAM.
> + * The attribute guarantees no CPU cache maintenance calls will be made.
> + */

I'd copy the Documentation/ text

Jason


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Date: Wed, 6 Aug 2025 15:10:41 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 02/16] iommu/dma: handle MMIO path in dma_iova_link
Message-ID: <20250806181041.GB184255@nvidia.com>
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 <52e39cd31d8f30e54a27afac84ea35f45ae4e422.1754292567.git.leon@kernel.org>
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On Mon, Aug 04, 2025 at 03:42:36PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Make sure that CPU is not synced if MMIO path is taken.

Let's elaborate..

Implement DMA_ATTR_MMIO for dma_iova_link().

This will replace the hacky use of DMA_ATTR_SKIP_CPU_SYNC to avoid
touching the possibly non-KVA MMIO memory.

Also correct the incorrect caching attribute for the IOMMU, MMIO
memory should not be cachable inside the IOMMU mapping or it can
possibly create system problems. Set IOMMU_MMIO for DMA_ATTR_MMIO.

> diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
> index ea2ef53bd4fef..399838c17b705 100644
> --- a/drivers/iommu/dma-iommu.c
> +++ b/drivers/iommu/dma-iommu.c
> @@ -1837,13 +1837,20 @@ static int __dma_iova_link(struct device *dev, dma_addr_t addr,
>  		phys_addr_t phys, size_t size, enum dma_data_direction dir,
>  		unsigned long attrs)
>  {
> -	bool coherent = dev_is_dma_coherent(dev);
> +	int prot;
>  
> -	if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
> -		arch_sync_dma_for_device(phys, size, dir);
> +	if (attrs & DMA_ATTR_MMIO)
> +		prot = dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO;

Yeah, exactly, we need the IOPTE on ARM to have the right cachability
or some systems might go wrong.


> +	else {
> +		bool coherent = dev_is_dma_coherent(dev);
> +
> +		if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
> +			arch_sync_dma_for_device(phys, size, dir);
> +		prot = dma_info_to_prot(dir, coherent, attrs);
> +	}
>  
>  	return iommu_map_nosync(iommu_get_dma_domain(dev), addr, phys, size,
> -			dma_info_to_prot(dir, coherent, attrs), GFP_ATOMIC);
> +			prot, GFP_ATOMIC);
>  }

Hmm, I missed this in prior series, ideally the GFP_ATOMIC should be
passed in as a gfp_t here so we can use GFP_KERNEL in callers that are
able.

Reviewed-by: Jason Gunthorpe 

Jason


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Date: Wed, 6 Aug 2025 15:26:30 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 03/16] dma-debug: refactor to use physical addresses
 for page mapping
Message-ID: <20250806182630.GC184255@nvidia.com>
References: 
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On Mon, Aug 04, 2025 at 03:42:37PM +0300, Leon Romanovsky wrote:
> +void debug_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
> +		int direction, dma_addr_t dma_addr, unsigned long attrs)
>  {
>  	struct dma_debug_entry *entry;

Should this patch should also absorb debug_dma_map_resource() into
here as well and we can have the caller of dma_dma_map_resource() call
debug_dma_map_page with ATTR_MMIO?

If not, this looks OK

Reviewed-by: Jason Gunthorpe 

Jason


From xen-devel-bounces@lists.xenproject.org Wed Aug 06 18:38:46 2025
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Date: Wed, 6 Aug 2025 21:38:31 +0300
From: Leon Romanovsky 
To: Jason Gunthorpe 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 03/16] dma-debug: refactor to use physical addresses
 for page mapping
Message-ID: <20250806183831.GW402218@unreal>
References: 
 <9ba84c387ce67389cd80f374408eebb58326c448.1754292567.git.leon@kernel.org>
 <20250806182630.GC184255@nvidia.com>
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On Wed, Aug 06, 2025 at 03:26:30PM -0300, Jason Gunthorpe wrote:
> On Mon, Aug 04, 2025 at 03:42:37PM +0300, Leon Romanovsky wrote:
> > +void debug_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
> > +		int direction, dma_addr_t dma_addr, unsigned long attrs)
> >  {
> >  	struct dma_debug_entry *entry;
> 
> Should this patch should also absorb debug_dma_map_resource() into
> here as well and we can have the caller of dma_dma_map_resource() call
> debug_dma_map_page with ATTR_MMIO?

It is done in "[PATCH v1 11/16] dma-mapping: export new dma_*map_phys() interface".

Thanks

> 
> If not, this looks OK
> 
> Reviewed-by: Jason Gunthorpe 
> 
> Jason
> 


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Date: Wed, 6 Aug 2025 15:44:43 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 05/16] iommu/dma: rename iommu_dma_*map_page to
 iommu_dma_*map_phys
Message-ID: <20250806184443.GD184255@nvidia.com>
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 <9186ccefda5ea97b56ec006900127650f9e324b5.1754292567.git.leon@kernel.org>
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On Mon, Aug 04, 2025 at 03:42:39PM +0300, Leon Romanovsky wrote:
> diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
> index 399838c17b705..11c5d5f8c0981 100644
> --- a/drivers/iommu/dma-iommu.c
> +++ b/drivers/iommu/dma-iommu.c
> @@ -1190,11 +1190,9 @@ static inline size_t iova_unaligned(struct iova_domain *iovad, phys_addr_t phys,
>  	return iova_offset(iovad, phys | size);
>  }
>  
> -dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
> -	      unsigned long offset, size_t size, enum dma_data_direction dir,
> -	      unsigned long attrs)
> +dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
> +		enum dma_data_direction dir, unsigned long attrs)
>  {
> -	phys_addr_t phys = page_to_phys(page) + offset;
>  	bool coherent = dev_is_dma_coherent(dev);
>  	int prot = dma_info_to_prot(dir, coherent, attrs);
>  	struct iommu_domain *domain = iommu_get_dma_domain(dev);

No issue with pushing the page_to_phys to the looks like two callers..

It is worth pointing though that today if the page * was a
MEMORY_DEVICE_PCI_P2PDMA page then it is illegal to call the swiotlb
functions a few lines below this:

                phys = iommu_dma_map_swiotlb(dev, phys, size, dir, attrs);

ie struct page alone as a type is not sufficient to make this function
safe for a long time now.

So I would add some explanation in the commit message how this will be
situated in the final call chains, and maybe leave behind a comment
that attrs may not have ATTR_MMIO in this function.

I think the answer is iommu_dma_map_phys() is only called for
!ATTR_MMIO addresses, and that iommu_dma_map_resource() will be called
for ATTR_MMIO?

Jason


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Date: Wed, 6 Aug 2025 17:24:05 -0400
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Subject: Re: [PATCH 2/2] x86/mm: correct PG_log_dirty definition
To: Jan Beulich , "xen-devel@lists.xenproject.org"
	
CC: Andrew Cooper , Julien Grall ,
	Stefano Stabellini , Anthony PERARD
	, Michal Orzel ,
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Penny Zheng
	
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 <65e27b35-9256-4ab0-966a-c50a18900ba5@suse.com>
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On 2025-08-05 03:59, Jan Beulich wrote:
> While it is correct that in shim-exclusive mode log-dirty handling is
> all unreachable code, the present conditional still isn't correct: In a
> HVM=n and SHADOW_PAGING=n configuration log-dirty code also is all
> unreachable (and hence violating Misra rule 2.1).
> 
> As we're aiming at moving away from special casing PV_SHIM_EXCLUSIVE=y,
> don't retain that part of the conditional.
> 
> Because of hypercall-defs.c we need to carry out the dependency by
> introducing a new auxiliary PAGING control.
> 
> Since compiling out mm/paging.c altogether would entail further changes,
> merely conditionalize the one function in there (paging_enable()) which
> would otherwise remain unreachable (Misra rule 2.1 again) when PAGING=n.
> 
> Fixes: 23d4e0d17b76 ("x86/shim: fix build with PV_SHIM_EXCLUSIVE and SHADOW_PAGING")
> Signed-off-by: Jan Beulich 
> ---
> Of course PAGING is at risk of being confused with MEM_PAGING. It not
> having a prompt, I hope that's tolerable, as I can't really think of a
> better name.
> 
> Other PG_log_dirty pre-processor conditionals then likely also want
> replacing. mm/paging.c and mm/p2m-basic.c could also be compiled out
> altogether when PAGING=n, at the expense of introducing a few more
> stubs.
> 
> FTAOD, the Fixes: tag being referenced does not mean this patch corrects
> the far more recently introduced build issue with the combination of the
> two features. That's still work that I expect Penny to carry out (with
> there still being the option of reverting the final part of the earlier
> series).
> 

> --- a/xen/arch/x86/mm/paging.c
> +++ b/xen/arch/x86/mm/paging.c
> @@ -864,6 +864,7 @@ void paging_final_teardown(struct domain
>       p2m_final_teardown(d);
>   }
>   
> +#ifdef CONFIG_PAGING

The file already has a lot of uses of #if PG_log_dirty with similar 
meaning, if I am not mistaken, so using that would make it more 
consistent.  But CONFIG_PAGING is directly tied to the Kconfig, so maybe 
it is better?  Just something I noticed.

Reviewed-by: Jason Andryuk 

Regards,
Jason

>   /* Enable an arbitrary paging-assistance mode.  Call once at domain
>    * creation. */
>   int paging_enable(struct domain *d, u32 mode)
> @@ -889,6 +890,7 @@ int paging_enable(struct domain *d, u32
>       else
>           return shadow_enable(d, mode);
>   }
> +#endif
>   
>   #ifdef CONFIG_HVM
>   /* Called from the guest to indicate that a process is being torn down


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Date: Thu, 7 Aug 2025 02:05:45 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: xen-devel@lists.xenproject.org
Cc: Andrew Cooper ,
	Stefano Stabellini ,
	Roger Pau =?utf-8?B?TW9ubsOp?= 
Subject: Re: [PATCH test-artifacts] Add debian rootfs artifact
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To: xen-devel@lists.xenproject.org
Cc: Andrew Cooper ,
	Stefano Stabellini ,
	Roger Pau =?utf-8?B?TW9ubsOp?= 
Subject: Re: [PATCH test-artifacts] Add debian rootfs artifact

On Thu, Aug 07, 2025 at 02:03:07AM +0200, Marek Marczykowski-G=C3=B3recki w=
rote:
> Will be used as dom0/domU in some tests.
>=20
> Install OpenRC and setup it to start /etc/local.d/ scripts so tests
> don't need different cases for Alpine and Debian.

Looks like this one did not reached the list:
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I just hope people explicitly included in cc did got it...

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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From: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
To: xen-devel@lists.xenproject.org
Cc: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: [PATCH v1 1/2] CI: Add driver domains tests
Date: Thu,  7 Aug 2025 02:06:49 +0200
Message-ID: <4595a5aaa66e8d26ff9851496624ceb9c734ee4c.1754525202.git-series.marmarek@invisiblethingslab.com>
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Setup a simple two domU system. One with network backend, running
xendriverdomain service, and one with frontend, trying to ping the
backend.

Contrary to other similar tests, use disk image instead of initrd, to
allow bigger rootfs without adding more RAM (for both dom0 and domU).
But keep using pxelinux as a bootloader as it's easier to setup than
installing grub on the disk. Theoretically, it could be started via direct
kernel boot in QEMU, but pxelinux is slightly closer to real-world
deployment.

Signed-off-by: Marek Marczykowski-Górecki 
---
 automation/gitlab-ci/test.yaml                  |   8 +-
 automation/scripts/qemu-driverdomains-x86_64.sh | 116 +++++++++++++++++-
 2 files changed, 124 insertions(+)
 create mode 100755 automation/scripts/qemu-driverdomains-x86_64.sh

diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
index 1f0b27b2378a..5c4b2dc304b4 100644
--- a/automation/gitlab-ci/test.yaml
+++ b/automation/gitlab-ci/test.yaml
@@ -656,6 +656,14 @@ qemu-alpine-x86_64-gcc:
     - *x86-64-test-needs
     - alpine-3.18-gcc
 
+qemu-alpine-driverdomains-x86_64-gcc:
+  extends: .qemu-x86-64
+  script:
+    - ./automation/scripts/qemu-driverdomains-x86_64.sh 2>&1 | tee ${LOGFILE}
+  needs:
+    - *x86-64-test-needs
+    - alpine-3.18-gcc
+
 qemu-smoke-x86-64-gcc:
   extends: .qemu-smoke-x86-64
   script:
diff --git a/automation/scripts/qemu-driverdomains-x86_64.sh b/automation/scripts/qemu-driverdomains-x86_64.sh
new file mode 100755
index 000000000000..1caaede7722e
--- /dev/null
+++ b/automation/scripts/qemu-driverdomains-x86_64.sh
@@ -0,0 +1,116 @@
+#!/bin/bash
+
+set -ex -o pipefail
+
+dom0_rootfs_extra_comp=()
+dom0_rootfs_extra_uncomp=()
+
+cd binaries
+
+# DomU rootfs
+
+mkdir -p rootfs
+cd rootfs
+mkdir -p etc/local.d
+passed="ping test passed"
+echo "#!/bin/bash
+
+set -x
+
+if grep -q test=backend /proc/cmdline; then
+    brctl addbr xenbr0
+    ip link set xenbr0 up
+    ip addr add 192.168.0.1/24 dev xenbr0
+    bash /etc/init.d/xendriverdomain start
+    # log backend-related logs to the console
+    tail -F /var/log/xen/xldevd.log /var/log/xen/xen-hotplug.log >>/dev/console 2>/dev/null &
+else
+    ip link set eth0 up
+    ip addr add 192.168.0.2/24 dev eth0
+    until ping -c 10 192.168.0.1; do
+        sleep 1
+    done
+    echo \"${passed}\"
+fi
+
+" > etc/local.d/xen.start
+chmod +x etc/local.d/xen.start
+zcat ../rootfs.cpio.gz | cpio -imd
+zcat ../xen-tools.cpio.gz | cpio -imd
+mkfs.ext4 -d . ../domU-rootfs.img 1024M
+cd ..
+rm -rf rootfs
+
+# Dom0 rootfs
+mkdir -p rootfs
+cd rootfs
+zcat ../rootfs.cpio.gz | cpio -imd
+zcat ../xen-tools.cpio.gz | cpio -imd
+mkdir -p root etc/local.d
+echo "name=\"backend\"
+memory=512
+vcpus=1
+kernel=\"/root/bzImage\"
+extra=\"console=hvc0 root=/dev/xvda net.ifnames=0 test=backend\"
+disk=[ '/root/domU-rootfs-b.img,raw,xvda,rw' ]
+" > root/backend.cfg
+echo "name=\"frontend\"
+memory=512
+vcpus=1
+kernel=\"/root/bzImage\"
+extra=\"console=hvc0 root=/dev/xvda net.ifnames=0 test=frontend\"
+disk=[ '/root/domU-rootfs-f.img,raw,xvda,rw' ]
+vif=[ 'bridge=xenbr0,backend=backend' ]
+" > root/frontend.cfg
+echo "#!/bin/bash
+
+set -x
+
+bash /etc/init.d/xencommons start
+
+xl list
+
+tail -F /var/log/xen/console/guest-backend.log 2>/dev/null | sed -e \"s/^/(backend) /\" &
+tail -F /var/log/xen/console/guest-frontend.log 2>/dev/null | sed -e \"s/^/(frontend) /\" &
+xl -vvv create /root/backend.cfg
+xl -vvv create /root/frontend.cfg
+" > etc/local.d/xen.start
+chmod +x etc/local.d/xen.start
+
+cp ../domU-rootfs.img ./root/domU-rootfs-b.img
+cp ../domU-rootfs.img ./root/domU-rootfs-f.img
+cp ../bzImage ./root/
+mkdir -p etc/default
+echo 'XENCONSOLED_TRACE=all' >> etc/default/xencommons
+mkdir -p var/log/xen/console
+mkfs.ext4 -d . ../dom0-rootfs.img 2048M
+cd ..
+rm -rf rootfs
+
+cd ..
+
+cat >> binaries/pxelinux.0 << EOF
+#!ipxe
+
+kernel xen console=com1 console_timestamps=boot
+module bzImage console=hvc0 root=/dev/sda net.ifnames=0
+boot
+EOF
+
+# Run the test
+rm -f smoke.serial
+export TEST_CMD="qemu-system-x86_64 \
+    -cpu qemu64,+svm \
+    -m 2G -smp 2 \
+    -monitor none -serial stdio \
+    -nographic \
+    -device virtio-net-pci,netdev=n0 \
+    -netdev user,id=n0,tftp=binaries,bootfile=/pxelinux.0 \
+    -drive file=binaries/dom0-rootfs.img,format=raw"
+
+export TEST_LOG="smoke.serial"
+export BOOT_MSG="Latest ChangeSet: "
+export LOG_MSG="Domain-0"
+export PASSED="$passed"
+
+./automation/scripts/console.exp | sed 's/\r\+$//'
-- 
git-series 0.9.1


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From: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
To: xen-devel@lists.xenproject.org
Cc: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
Subject: [PATCH v1 0/2] Add driver domains test
Date: Thu,  7 Aug 2025 02:06:48 +0200
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This is intended to detect issues like recent xl devd crash in domU.

Pipeline:
https://gitlab.com/xen-project/people/marmarek/xen/-/pipelines/1970971528

I did checked that indeed it fails with the fix reverted - that's why the
second patch - Alpine version did not detected that regression.

Requires debian in test-artifacts repo - patch sent separately.

Marek Marczykowski-Górecki (2):
  CI: Add driver domains tests
  CI: Run driver domains test on Debian too

 automation/gitlab-ci/test.yaml                  |  27 ++++-
 automation/scripts/qemu-driverdomains-x86_64.sh | 116 +++++++++++++++++-
 2 files changed, 143 insertions(+)
 create mode 100755 automation/scripts/qemu-driverdomains-x86_64.sh

base-commit: dbcbbed4e9dc25faa211d359c2f04a9c70f087c9
-- 
git-series 0.9.1


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Feedback-ID: i1568416f:Fastmail
From: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
To: xen-devel@lists.xenproject.org
Cc: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: [PATCH v1 2/2] CI: Run driver domains test on Debian too
Date: Thu,  7 Aug 2025 02:06:50 +0200
Message-ID: 
X-Mailer: git-send-email 2.49.0
In-Reply-To: 
References: 
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The recent failure affected only glibc-based systems, so do the test on
Debian too.

Signed-off-by: Marek Marczykowski-Górecki 
---
 automation/gitlab-ci/test.yaml | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
index 5c4b2dc304b4..a5ae03b0eee9 100644
--- a/automation/gitlab-ci/test.yaml
+++ b/automation/gitlab-ci/test.yaml
@@ -30,6 +30,17 @@
     job: microcode-x86
     ref: master
 
+.debian-x86-64-test-needs: &debian-x86-64-test-needs
+  - project: xen-project/hardware/test-artifacts
+    job: linux-6.6.56-x86_64
+    ref: master
+  - project: xen-project/hardware/test-artifacts
+    job: debian-12-x86_64-rootfs
+    ref: master
+  - project: xen-project/hardware/test-artifacts
+    job: microcode-x86
+    ref: master
+
 .qemu-arm64:
   extends: .test-jobs-common
   variables:
@@ -664,6 +675,14 @@ qemu-alpine-driverdomains-x86_64-gcc:
     - *x86-64-test-needs
     - alpine-3.18-gcc
 
+qemu-debian-12-driverdomains-x86_64-gcc:
+  extends: .qemu-x86-64
+  script:
+    - ./automation/scripts/qemu-driverdomains-x86_64.sh 2>&1 | tee ${LOGFILE}
+  needs:
+    - *debian-x86-64-test-needs
+    - debian-12-x86_64-gcc-debug
+
 qemu-smoke-x86-64-gcc:
   extends: .qemu-smoke-x86-64
   script:
-- 
git-series 0.9.1


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Date: Thu, 07 Aug 2025 00:56:56 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v11] xen/console: introduce domain_console struct
Message-ID: <20250807005649.551704-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Introduce domain_console for grouping data structures used for integrating
domain's diagnostic console with Xen's console driver.

Group all pbuf-related data structures under domain_console. Rename the mov=
ed
fields to plain .buf, .idx and .lock names, since all uses of the fields ar=
e
touched.

Ensure accesses to domain_console pointer are valid in console_switch_input=
().

Bump the domain console buffer allocation size to 256. No extra symbol for =
the
value since it is used only once during data structure declaration. All siz=
e
checks use ARRAY_SIZE().

Allocate domain_console from the heap so that the parent domain struct size
stays below PAGE_SIZE boundary to account for more console-related fields
added in the future.

Finally, update the domain_console allocation and initialization code. Make
sure domain_console is not allocated for system domains.

No functional change.

Signed-off-by: Denis Mukhin 
---
Changes since v10:
- use XVFREE()
- ensured that domain_console is not allocated for system domains
- corrected comment in sched.h
- Link to v10: https://lore.kernel.org/xen-devel/20250725210525.736706-1-dm=
ukhin@ford.com/
---
 xen/arch/arm/vpl011.c      |  2 +-
 xen/arch/x86/hvm/hvm.c     | 16 +++++++++-------
 xen/arch/x86/pv/shim.c     |  2 +-
 xen/common/domain.c        | 19 +++++++++----------
 xen/drivers/char/console.c | 28 ++++++++++++++++------------
 xen/include/xen/sched.h    | 24 +++++++++++++-----------
 6 files changed, 49 insertions(+), 42 deletions(-)

diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c
index 480fc664fc62..d0d17c76b72c 100644
--- a/xen/arch/arm/vpl011.c
+++ b/xen/arch/arm/vpl011.c
@@ -713,7 +713,7 @@ int domain_vpl011_init(struct domain *d, struct vpl011_=
init_info *info)
     }
     else
     {
-        d->console.input_allowed =3D true;
+        d->console->input_allowed =3D true;
         vpl011->backend_in_domain =3D false;
=20
         vpl011->backend.xen =3D xzalloc(struct vpl011_xen_backend);
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index cb8ecd050d41..c0673325143d 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -560,6 +560,7 @@ static int cf_check hvm_print_line(
     int dir, unsigned int port, unsigned int bytes, uint32_t *val)
 {
     struct domain *cd =3D current->domain;
+    struct domain_console *cons =3D cd->console;
     char c =3D *val;
=20
     ASSERT(bytes =3D=3D 1 && port =3D=3D XEN_HVM_DEBUGCONS_IOPORT);
@@ -571,16 +572,17 @@ static int cf_check hvm_print_line(
     if ( !is_console_printable(c) )
         return X86EMUL_OKAY;
=20
-    spin_lock(&cd->pbuf_lock);
+    spin_lock(&cons->lock);
+    ASSERT(cons->idx < ARRAY_SIZE(cons->buf));
     if ( c !=3D '\n' )
-        cd->pbuf[cd->pbuf_idx++] =3D c;
-    if ( (cd->pbuf_idx =3D=3D (DOMAIN_PBUF_SIZE - 1)) || (c =3D=3D '\n') )
+        cons->buf[cons->idx++] =3D c;
+    if ( (cons->idx =3D=3D (ARRAY_SIZE(cons->buf) - 1)) || (c =3D=3D '\n')=
 )
     {
-        cd->pbuf[cd->pbuf_idx] =3D '\0';
-        guest_printk(cd, XENLOG_G_DEBUG "%s\n", cd->pbuf);
-        cd->pbuf_idx =3D 0;
+        cons->buf[cons->idx] =3D '\0';
+        guest_printk(cd, XENLOG_G_DEBUG "%s\n", cons->buf);
+        cons->idx =3D 0;
     }
-    spin_unlock(&cd->pbuf_lock);
+    spin_unlock(&cons->lock);
=20
     return X86EMUL_OKAY;
 }
diff --git a/xen/arch/x86/pv/shim.c b/xen/arch/x86/pv/shim.c
index bc2a7dd5fae5..bd29c53a2d34 100644
--- a/xen/arch/x86/pv/shim.c
+++ b/xen/arch/x86/pv/shim.c
@@ -239,7 +239,7 @@ void __init pv_shim_setup_dom(struct domain *d, l4_pgen=
try_t *l4start,
      */
     d->max_pages =3D domain_tot_pages(d);
=20
-    d->console.input_allowed =3D true;
+    d->console->input_allowed =3D true;
 }
=20
 static void write_start_info(struct domain *d)
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 5241a1629eeb..8b20daa57d62 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -680,7 +680,7 @@ static void _domain_destroy(struct domain *d)
     BUG_ON(!d->is_dying);
     BUG_ON(atomic_read(&d->refcnt) !=3D DOMAIN_DESTROYED);
=20
-    xfree(d->pbuf);
+    XVFREE(d->console);
=20
     argo_destroy(d);
=20
@@ -846,8 +846,6 @@ struct domain *domain_create(domid_t domid,
         flags |=3D CDF_hardware;
         if ( old_hwdom )
             old_hwdom->cdf &=3D ~CDF_hardware;
-
-        d->console.input_allowed =3D true;
     }
=20
     /* Holding CDF_* internal flags. */
@@ -877,8 +875,6 @@ struct domain *domain_create(domid_t domid,
     spin_lock_init(&d->shutdown_lock);
     d->shutdown_code =3D SHUTDOWN_CODE_INVALID;
=20
-    spin_lock_init(&d->pbuf_lock);
-
     rwlock_init(&d->vnuma_rwlock);
=20
 #ifdef CONFIG_HAS_PCI
@@ -924,6 +920,14 @@ struct domain *domain_create(domid_t domid,
     if ( is_system_domain(d) )
         return d;
=20
+    err =3D -ENOMEM;
+    d->console =3D xvzalloc(typeof(*d->console));
+    if ( !d->console )
+        goto fail;
+
+    spin_lock_init(&d->console->lock);
+    d->console->input_allowed =3D is_hardware_domain(d);
+
     /*
      * This assertion helps static analysis tools infer that config cannot=
 be
      * NULL in this branch, which in turn means that it can be safely
@@ -976,11 +980,6 @@ struct domain *domain_create(domid_t domid,
     if ( (err =3D argo_init(d)) !=3D 0 )
         goto fail;
=20
-    err =3D -ENOMEM;
-    d->pbuf =3D xzalloc_array(char, DOMAIN_PBUF_SIZE);
-    if ( !d->pbuf )
-        goto fail;
-
     if ( (err =3D sched_init_domain(d, config->cpupool_id)) !=3D 0 )
         goto fail;
=20
diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c
index 9bd5b4825da6..a99605103552 100644
--- a/xen/drivers/char/console.c
+++ b/xen/drivers/char/console.c
@@ -526,7 +526,7 @@ struct domain *console_get_domain(void)
     if ( !d )
         return NULL;
=20
-    if ( d->console.input_allowed )
+    if ( d->console->input_allowed )
         return d;
=20
     rcu_unlock_domain(d);
@@ -567,10 +567,13 @@ static void console_switch_input(void)
         d =3D rcu_lock_domain_by_id(domid);
         if ( d )
         {
-            rcu_unlock_domain(d);
-
-            if ( !d->console.input_allowed )
+            if ( !d->console->input_allowed )
+            {
+                rcu_unlock_domain(d);
                 continue;
+            }
+
+            rcu_unlock_domain(d);
=20
             console_rx =3D next_rx;
             printk("*** Serial input to DOM%u", domid);
@@ -749,6 +752,7 @@ static long guest_console_write(XEN_GUEST_HANDLE_PARAM(=
char) buffer,
         else
         {
             char *kin =3D kbuf, *kout =3D kbuf, c;
+            struct domain_console *cons =3D cd->console;
=20
             /* Strip non-printable characters */
             do
@@ -761,22 +765,22 @@ static long guest_console_write(XEN_GUEST_HANDLE_PARA=
M(char) buffer,
             } while ( --kcount > 0 );
=20
             *kout =3D '\0';
-            spin_lock(&cd->pbuf_lock);
+            spin_lock(&cons->lock);
             kcount =3D kin - kbuf;
             if ( c !=3D '\n' &&
-                 (cd->pbuf_idx + (kout - kbuf) < (DOMAIN_PBUF_SIZE - 1)) )
+                 (cons->idx + (kout - kbuf) < (ARRAY_SIZE(cons->buf) - 1))=
 )
             {
                 /* buffer the output until a newline */
-                memcpy(cd->pbuf + cd->pbuf_idx, kbuf, kout - kbuf);
-                cd->pbuf_idx +=3D (kout - kbuf);
+                memcpy(cons->buf + cons->idx, kbuf, kout - kbuf);
+                cons->idx +=3D kout - kbuf;
             }
             else
             {
-                cd->pbuf[cd->pbuf_idx] =3D '\0';
-                guest_printk(cd, XENLOG_G_DEBUG "%s%s\n", cd->pbuf, kbuf);
-                cd->pbuf_idx =3D 0;
+                cons->buf[cons->idx] =3D '\0';
+                guest_printk(cd, XENLOG_G_DEBUG "%s%s\n", cons->buf, kbuf)=
;
+                cons->idx =3D 0;
             }
-            spin_unlock(&cd->pbuf_lock);
+            spin_unlock(&cons->lock);
         }
=20
         guest_handle_add_offset(buffer, kcount);
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index fd5c9f933373..dab3fe59263e 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -371,6 +371,17 @@ struct evtchn_port_ops;
=20
 #define MAX_NR_IOREQ_SERVERS 8
=20
+/* Domain console settings. */
+struct domain_console {
+    /* Permission to take ownership of the physical console input. */
+    bool input_allowed;
+
+    /* hvm_print_line() and guest_console_write() logging. */
+    unsigned int idx;
+    spinlock_t lock;
+    char buf[256];
+};
+
 struct domain
 {
     domid_t          domain_id;
@@ -562,12 +573,6 @@ struct domain
     /* Control-plane tools handle for this domain. */
     xen_domain_handle_t handle;
=20
-    /* hvm_print_line() and guest_console_write() logging. */
-#define DOMAIN_PBUF_SIZE 200
-    char       *pbuf;
-    unsigned int pbuf_idx;
-    spinlock_t  pbuf_lock;
-
     /* OProfile support. */
     struct xenoprof *xenoprof;
=20
@@ -652,11 +657,8 @@ struct domain
     unsigned int *llc_colors;
 #endif
=20
-    /* Console settings. */
-    struct {
-        /* Permission to take ownership of the physical console input. */
-        bool input_allowed;
-    } console;
+    /* Pointer to console settings; NULL for system domains. */
+    struct domain_console *console;
 } __aligned(PAGE_SIZE);
=20
 static inline struct page_list_head *page_to_list(
--=20
2.34.1




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To: =?utf-8?Q?Roger_Pau_Monn=C3=A9?= 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, alejandro.garciavallejo@amd.com, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v13 1/3] xen/domain: unify domain ID allocation
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References: <20250730174042.1632011-1-dmukhin@ford.com> <20250730174042.1632011-2-dmukhin@ford.com> 
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On Tue, Aug 05, 2025 at 03:38:37PM +0200, Roger Pau Monn=C3=A9 wrote:
> On Wed, Jul 30, 2025 at 05:40:54PM +0000, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Currently, there are two different domain ID allocation implementations=
:
> >
> >   1) Sequential IDs allocation in dom0less Arm code based on max_init_d=
omid;
> >
> >   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
> >      max_init_domid (both Arm and x86).
> >
> > The domain ID allocation covers dom0 or late hwdom, predefined domains,
> > post-boot domains, excluding Xen system domains (domid >=3D
> > DOMID_FIRST_RESERVED).
> >
> > It makes sense to have a common helper code for such task across archit=
ectures
> > (Arm and x86) and between dom0less / toolstack domU allocation.
> >
> > Note, fixing dependency on max_init_domid is out of scope of this patch=
.
> >
> > Wrap the domain ID allocation as an arch-independent function domid_all=
oc() in
> > new common/domid.c based on the bitmap.
> >
> > Allocation algorithm:
> > - If an explicit domain ID is provided, verify its availability and use=
 it if
> >   ID is not used;
> > - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERV=
ED-1],
> >   starting from the last used ID.
> >   Implementation guarantees that two consecutive calls will never retur=
n the
> >   same ID. ID#0 is reserved for the first boot domain (currently, dom0)=
 and
> >   excluded from the allocation range.
> >
> > Remove is_free_domid() helper as it is not needed now.
> >
> > No functional change intended.
> >
> > Signed-off-by: Denis Mukhin 
> > Reviewed-by: Alejandro Vallejo 
> > ---
> > Changes since v12:
> > - updated comment for domid_alloc() and commit message
> > - added Alejandro's R-b
> > ---
> >  xen/arch/arm/domain_build.c             |  7 +-
> >  xen/arch/x86/setup.c                    |  7 +-
> >  xen/common/Makefile                     |  1 +
> >  xen/common/device-tree/dom0less-build.c | 15 ++--
> >  xen/common/domain.c                     |  2 +
> >  xen/common/domctl.c                     | 42 ++---------
> >  xen/common/domid.c                      | 94 +++++++++++++++++++++++++
> >  xen/include/xen/domain.h                |  3 +
> >  8 files changed, 124 insertions(+), 47 deletions(-)
> >  create mode 100644 xen/common/domid.c
> >
> > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> > index 463ae4474d30..789f2b9d3ce7 100644
> > --- a/xen/arch/arm/domain_build.c
> > +++ b/xen/arch/arm/domain_build.c
> > @@ -2050,6 +2050,7 @@ void __init create_dom0(void)
> >          .grant_opts =3D XEN_DOMCTL_GRANT_version(opt_gnttab_max_versio=
n),
> >      };
> >      unsigned int flags =3D CDF_privileged | CDF_hardware;
> > +    domid_t domid;
> >      int rc;
> >
> >      /* The vGIC for DOM0 is exactly emulating the hardware GIC */
> > @@ -2074,7 +2075,11 @@ void __init create_dom0(void)
> >      if ( !llc_coloring_enabled )
> >          flags |=3D CDF_directmap;
> >
> > -    dom0 =3D domain_create(0, &dom0_cfg, flags);
> > +    domid =3D domid_alloc(0);
> > +    if ( domid =3D=3D DOMID_INVALID )
> > +        panic("Error allocating domain ID 0\n");
> > +
> > +    dom0 =3D domain_create(domid, &dom0_cfg, flags);
> >      if ( IS_ERR(dom0) )
> >          panic("Error creating domain 0 (rc =3D %ld)\n", PTR_ERR(dom0))=
;
> >
> > diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
> > index 1543dd251cc6..2ff7c28c277b 100644
> > --- a/xen/arch/x86/setup.c
> > +++ b/xen/arch/x86/setup.c
> > @@ -1047,8 +1047,11 @@ static struct domain *__init create_dom0(struct =
boot_info *bi)
> >      if ( iommu_enabled )
> >          dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu;
> >
> > -    /* Create initial domain.  Not d0 for pvshim. */
> > -    bd->domid =3D get_initial_domain_id();
> > +    /* Allocate initial domain ID.  Not d0 for pvshim. */
> > +    bd->domid =3D domid_alloc(get_initial_domain_id());
> > +    if ( bd->domid =3D=3D DOMID_INVALID )
> > +        panic("Error allocating domain ID %d\n", get_initial_domain_id=
());
>=20
> Nit: in other error messages in the same function we handle the domid
> as an unsigned integer, so %u probably wants using here.  Unless you
> have an explicit intention to print IDs >=3D DOMID_FIRST_RESERVED as
> negative integers?

No negative integers, that should be %u
Thanks!

>=20
> > +
> >      d =3D domain_create(bd->domid, &dom0_cfg,
> >                        pv_shim ? 0 : CDF_privileged | CDF_hardware);
> >      if ( IS_ERR(d) )
> > diff --git a/xen/common/Makefile b/xen/common/Makefile
> > index c316957fcb36..0c7d0f5d46e1 100644
> > --- a/xen/common/Makefile
> > +++ b/xen/common/Makefile
> > @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) +=3D d=
evice.o
> >  obj-$(CONFIG_DEVICE_TREE_PARSE) +=3D device-tree/
> >  obj-$(CONFIG_IOREQ_SERVER) +=3D dm.o
> >  obj-y +=3D domain.o
> > +obj-y +=3D domid.o
> >  obj-y +=3D event_2l.o
> >  obj-y +=3D event_channel.o
> >  obj-$(CONFIG_EVTCHN_FIFO) +=3D event_fifo.o
> > diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/devic=
e-tree/dom0less-build.c
> > index 6bb038111de9..f4b6b515d2d2 100644
> > --- a/xen/common/device-tree/dom0less-build.c
> > +++ b/xen/common/device-tree/dom0less-build.c
> > @@ -833,6 +833,7 @@ void __init create_domUs(void)
> >      {
> >          struct kernel_info ki =3D KERNEL_INFO_INIT;
> >          int rc =3D parse_dom0less_node(node, &ki.bd);
> > +        domid_t domid;
> >
> >          if ( rc =3D=3D -ENOENT )
> >              continue;
> > @@ -842,13 +843,13 @@ void __init create_domUs(void)
> >          if ( (max_init_domid + 1) >=3D DOMID_FIRST_RESERVED )
> >              panic("No more domain IDs available\n");
> >
> > -        /*
> > -         * The variable max_init_domid is initialized with zero, so he=
re it's
> > -         * very important to use the pre-increment operator to call
> > -         * domain_create() with a domid > 0. (domid =3D=3D 0 is reserv=
ed for Dom0)
> > -         */
> > -        ki.bd.d =3D domain_create(++max_init_domid,
> > -                                &ki.bd.create_cfg, ki.bd.create_flags)=
;
> > +        domid =3D domid_alloc(DOMID_INVALID);
> > +        if ( domid =3D=3D DOMID_INVALID )
> > +            panic("Error allocating ID for domain %s\n", dt_node_name(=
node));
> > +
> > +        max_init_domid =3D max(max_init_domid, domid);
> > +
> > +        ki.bd.d =3D domain_create(domid, &ki.bd.create_cfg, ki.bd.crea=
te_flags);
> >          if ( IS_ERR(ki.bd.d) )
> >              panic("Error creating domain %s (rc =3D %ld)\n",
> >                    dt_node_name(node), PTR_ERR(ki.bd.d));
> > diff --git a/xen/common/domain.c b/xen/common/domain.c
> > index 5241a1629eeb..12fbab01cd8e 100644
> > --- a/xen/common/domain.c
> > +++ b/xen/common/domain.c
> > @@ -1473,6 +1473,8 @@ void domain_destroy(struct domain *d)
> >      /* Remove from the domlist/hash. */
> >      domlist_remove(d);
> >
> > +    domid_free(d->domain_id);
>=20
> The domlist removal above still allows current users to continue
> "operating" on the domain until the next RCU.  Should for safety the
> freeing of the domid be deferred to _domain_destroy(), which is
> executed in RCU context, and thus ensures there are no current users
> of the removed domain?
>=20
> I cannot think of a specific scenario where this could be dangerous
> right now, but deferring to RCU context together with the final
> cleanup seems safer overall.

I agree, _domain_destroy() is the place for domid_free().

>=20
> > +
> >      /* Schedule RCU asynchronous completion of domain destroy. */
> >      call_rcu(&d->rcu, complete_domain_destroy);
> >  }
> > diff --git a/xen/common/domctl.c b/xen/common/domctl.c
> > index f2a7caaf853c..5509998aa139 100644
> > --- a/xen/common/domctl.c
> > +++ b/xen/common/domctl.c
> > @@ -51,20 +51,6 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nod=
emask,
> >                                     MAX_NUMNODES);
> >  }
> >
> > -static inline int is_free_domid(domid_t dom)
> > -{
> > -    struct domain *d;
> > -
> > -    if ( dom >=3D DOMID_FIRST_RESERVED )
> > -        return 0;
> > -
> > -    if ( (d =3D rcu_lock_domain_by_id(dom)) =3D=3D NULL )
> > -        return 1;
> > -
> > -    rcu_unlock_domain(d);
> > -    return 0;
> > -}
> > -
> >  void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *=
info)
> >  {
> >      struct vcpu *v;
> > @@ -423,36 +409,18 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_=
t) u_domctl)
> >
> >      case XEN_DOMCTL_createdomain:
> >      {
> > -        domid_t        dom;
> > -        static domid_t rover =3D 0;
> > +        domid_t domid =3D domid_alloc(op->domain);
> >
> > -        dom =3D op->domain;
> > -        if ( (dom > 0) && (dom < DOMID_FIRST_RESERVED) )
> > +        if ( domid =3D=3D DOMID_INVALID )
>=20
> This is a change in behavior AFAICT, as you now allow
> XEN_DOMCTL_createdomain to possibly create a domain with domid 0 (if
> it's available).  Currently op->domain =3D=3D 0 is handled as op->domain
> =3D=3D DOMID_FIRST_RESERVED. You either need to adjust the code here, so
> that you do:
>=20
> domid_t domid =3D domid_alloc(op->domain ?: DOMID_FIRST_RESERVED);
>=20
> Or domid_alloc() needs to be adjusted to handle an input domid =3D=3D 0 a=
s
> it handles DOMID_FIRST_RESERVED.

Thanks!
I will adjust code in do_domctl().

>=20
> >          {
> >              ret =3D -EEXIST;
> > -            if ( !is_free_domid(dom) )
> > -                break;
> > -        }
> > -        else
> > -        {
> > -            for ( dom =3D rover + 1; dom !=3D rover; dom++ )
> > -            {
> > -                if ( dom =3D=3D DOMID_FIRST_RESERVED )
> > -                    dom =3D 1;
> > -                if ( is_free_domid(dom) )
> > -                    break;
> > -            }
> > -
> > -            ret =3D -ENOMEM;
> > -            if ( dom =3D=3D rover )
> > -                break;
> > -
> > -            rover =3D dom;
> > +            break;
> >          }
> >
> > -        d =3D domain_create(dom, &op->u.createdomain, false);
> > +        d =3D domain_create(domid, &op->u.createdomain, false);
> >          if ( IS_ERR(d) )
> >          {
> > +            domid_free(domid);
> >              ret =3D PTR_ERR(d);
> >              d =3D NULL;
> >              break;
> > diff --git a/xen/common/domid.c b/xen/common/domid.c
> > new file mode 100644
> > index 000000000000..e727dcaf0793
> > --- /dev/null
> > +++ b/xen/common/domid.c
> > @@ -0,0 +1,94 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Domain ID allocator.
> > + *
> > + * Covers dom0 or late hwdom, predefined domains, post-boot domains.
> > + * Excludes Xen system domains (ID >=3D DOMID_FIRST_RESERVED).
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#include 
> > +
> > +static DEFINE_SPINLOCK(domid_lock);
> > +static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED);
> > +
> > +/*
> > + * Allocate domain ID.
> > + *
> > + * @param domid Domain ID hint:
> > + * - If an explicit domain ID is provided, verify its availability and=
 use it
> > + *   if ID is not used;
> > + * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] =
range,
> > + *   starting from the last used ID. Implementation guarantees that tw=
o
> > + *   consecutive calls will never return the same ID. ID#0 is reserved=
 for
> > + *   the first boot domain (currently, dom0) and excluded from the all=
ocation
> > + *   range.
> > + * @return Valid domain ID in case of successful allocation,
> > + *         DOMID_INVALID - otherwise.
> > + */
> > +domid_t domid_alloc(domid_t domid)
> > +{
> > +    static domid_t domid_last;
> > +
> > +    spin_lock(&domid_lock);
> > +
> > +    /* Exact match. */
> > +    if ( domid < DOMID_FIRST_RESERVED )
> > +    {
> > +        if ( __test_and_set_bit(domid, domid_bitmap) )
> > +            domid =3D DOMID_INVALID;
> > +    }
> > +    /*
> > +     * Exhaustive search.
> > +     *
> > +     * Domain ID#0 is reserved for the first boot domain (e.g. control=
 domain)
> > +     * and excluded from allocation.
> > +     */
> > +    else
> > +    {
> > +        domid =3D find_next_zero_bit(domid_bitmap,
> > +                                   DOMID_FIRST_RESERVED,
> > +                                   domid_last + 1);
> > +        if ( domid =3D=3D DOMID_FIRST_RESERVED )
>=20
> Nit: you could further gate this second search to domid_last !=3D 0, as
> otherwise the first search has already scanned the whole bitmap.

Ack.

>=20
> > +            domid =3D find_next_zero_bit(domid_bitmap,
> > +                                       DOMID_FIRST_RESERVED,
> > +                                       1);
>=20
> Nit: you could possibly limit this second search to (domid_last + 1)
> size, as you have already searched from [domid_last + 1,
> DOMID_FIRST_RESERVED], and the bitmap couldn't have changed as the
> lock is being held.

Ack.

>=20
> Thanks, Roger.



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Anthony PERARD
	, Juergen Gross 
Subject: [PATCH v1] xenconsole: Add connected flag
Date: Wed, 6 Aug 2025 21:56:06 -0400
Message-ID: <20250807015606.4427-1-jason.andryuk@amd.com>
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With hyperlaunch, a domU can start before its console ring is connected
by xenconsoled.  With nothing emptying the ring, it can quickly fill
during boot.  In domU_write_console(), __write_console() returns 0 when
the ring is full.  This loops spins until xenconsoled starts emptying
the ring:

        while (len) {
                ssize_t sent = __write_console(cons, data, len);

                if (sent < 0)
                        return sent;

                data += sent;
                len -= sent;

                if (unlikely(len))
                        HYPERVISOR_sched_op(SCHEDOP_yield, NULL);
        }

The goal of this patch is to add a way for the frontend to know when a
console is connected.  This patch adds a new flag to the end of the
console ring structure.  It is used for the backend to indicate that it
has connected and started servicing the page.

The two values are
XENCONSOLE_DISCONNECTED 1
XENCONSOLE_CONNECTED    0

XENCONSOLE_DISCONNECTED indicates to the guest that ring is
disconnected, so it will not be serviced.  The guest can avoid writing
into it in that case.  A domU can use console hypercalls and only
transition to the ring when it is connected and won't fill and block.

Once the backend (xenconsoled) maps and starts servicing the
console, the flag will be set to XENCONSOLE_CONNECTED (0) to indicate
the backend state to the frontend.

The connected value as 0 will be match the default of a zero-ed console
page.  Hyperlaunch can set the flag to XENCONSOLE_DISCONNECTED and let
xenconsoled set to XENCONSOLE_CONNECTED.

Old domU hvc_xen drivers won't check the flag.
New domU hvc_xen running on a new xen/xenconsoled will work properly.
New domU hvc_xen on old xen/xenconsoled should only see a 0 for the flag
and behave as if connected.

Signed-off-by: Jason Andryuk 
---
v1:
Remove evtchn notify call
Set connected later when there is no error

RFC v3:
Flip flag values so 0 is connected.

The other option would be to add:
uint32_t features
uint32_t connected

New domUs would check features for a magic value and/or flag to know
they can rely on connected transitioning.

I think making XENCONSOLE_CONNECTED == 0 side steps the need for
an additional features field.  As long as assuming zero-ed memory is
acceptable.  However, this only matters for a hyperlaunched guest -
xenconsoled will normally readily connect the console and set the value.

This assumes that existing frontends are not using the flag space for
some other use.

Removed idea:
Send an event channel notification to let the domU know that xenconsoled
is connected.  Xenstored does similar, but for xenstore, the xenstore
driver owns the event channel/irq and can rebind it.  For hvc_xen, the
hvc subsystem owns the irq, so it isn't readily available for rebinding.
This is not implemented.

I had the idea for the kernel to use a static key and switch writing
from the hypercall to the PV ring once connected.  It didn't actually
work in my short attempt - I think changing the static key from within
an interupt was wrong.  I fell back to just checking the flag directly
without an optimization.  That would work and would make the event
channel notification unnecessary.
---
 tools/console/daemon/io.c       |  4 ++++
 xen/include/public/io/console.h | 13 +++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/tools/console/daemon/io.c b/tools/console/daemon/io.c
index bb739bdb8c..c278752ff1 100644
--- a/tools/console/daemon/io.c
+++ b/tools/console/daemon/io.c
@@ -781,6 +781,10 @@ static int console_create_ring(struct console *con)
 		con->log_fd = create_console_log(con);
 
  out:
+	/* Mark the console connected. */
+	if (!err && con->interface)
+		con->interface->flag = XENCONSOLE_CONNECTED;
+
 	return err;
 }
 
diff --git a/xen/include/public/io/console.h b/xen/include/public/io/console.h
index 4509b4b689..c16ef42ef4 100644
--- a/xen/include/public/io/console.h
+++ b/xen/include/public/io/console.h
@@ -19,6 +19,19 @@ struct xencons_interface {
     char out[2048];
     XENCONS_RING_IDX in_cons, in_prod;
     XENCONS_RING_IDX out_cons, out_prod;
+/*
+ * Flag values signaling from backend to frontend whether the console is
+ * connected.  i.e. Whether it will be serviced and emptied.
+ *
+ * The flag starts as disconnected.
+ */
+#define XENCONSOLE_DISCONNECTED 1
+/*
+ * The flag is set to connected when the backend connects and the console
+ * will be serviced.
+ */
+#define XENCONSOLE_CONNECTED    0
+    uint32_t flag;
 };
 
 #ifdef XEN_WANT_FLEX_CONSOLE_RING
-- 
2.50.1



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Date: Thu, 07 Aug 2025 02:12:10 +0000
To: =?utf-8?Q?Roger_Pau_Monn=C3=A9?= 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, alejandro.garciavallejo@amd.com, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v13 2/3] tools/tests: introduce unit tests for domain ID allocator
Message-ID: 
In-Reply-To: 
References: <20250730174042.1632011-1-dmukhin@ford.com> <20250730174042.1632011-3-dmukhin@ford.com> 
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On Tue, Aug 05, 2025 at 04:15:28PM +0200, Roger Pau Monn=C3=A9 wrote:
> On Wed, Jul 30, 2025 at 05:41:00PM +0000, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Introduce some basic infrastructure for doing domain ID allocation unit=
 tests,
> > and add a few tests that ensure correctness of the domain ID allocator.
> >
> > Signed-off-by: Denis Mukhin 
> > ---
> > Changes since v12:
> > - fixed Makefile
> > - dropped unused symbols/includes from the test harness header
> > - s/printk/printf/g in the test code
> > ---
> >  tools/tests/Makefile                   |   2 +-
> >  tools/tests/domid/.gitignore           |   2 +
> >  tools/tests/domid/Makefile             |  48 ++++++++++
> >  tools/tests/domid/include/xen/domain.h | 126 +++++++++++++++++++++++++
> >  tools/tests/domid/test-domid.c         |  78 +++++++++++++++
> >  5 files changed, 255 insertions(+), 1 deletion(-)
> >  create mode 100644 tools/tests/domid/.gitignore
> >  create mode 100644 tools/tests/domid/Makefile
> >  create mode 100644 tools/tests/domid/include/xen/domain.h
> >  create mode 100644 tools/tests/domid/test-domid.c
> >
> > diff --git a/tools/tests/Makefile b/tools/tests/Makefile
> > index 36928676a666..ff1666425436 100644
> > --- a/tools/tests/Makefile
> > +++ b/tools/tests/Makefile
> > @@ -1,7 +1,7 @@
> >  XEN_ROOT =3D $(CURDIR)/../..
> >  include $(XEN_ROOT)/tools/Rules.mk
> >
> > -SUBDIRS-y :=3D
> > +SUBDIRS-y :=3D domid
> >  SUBDIRS-y +=3D resource
> >  SUBDIRS-$(CONFIG_X86) +=3D cpu-policy
> >  SUBDIRS-$(CONFIG_X86) +=3D tsx
> > diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignor=
e
> > new file mode 100644
> > index 000000000000..70e306b3c074
> > --- /dev/null
> > +++ b/tools/tests/domid/.gitignore
> > @@ -0,0 +1,2 @@
> > +*.o
> > +test-domid
> > diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile
> > new file mode 100644
> > index 000000000000..08fbad096aec
> > --- /dev/null
> > +++ b/tools/tests/domid/Makefile
> > @@ -0,0 +1,48 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +#
> > +# Unit tests for domain ID allocator.
> > +#
> > +# Copyright 2025 Ford Motor Company
> > +
> > +XEN_ROOT=3D$(CURDIR)/../../..
> > +include $(XEN_ROOT)/tools/Rules.mk
> > +
> > +TESTS :=3D test-domid
> > +
> > +vpath domid.c $(XEN_ROOT)/xen/common/
> > +
> > +.PHONY: all
> > +all: $(TESTS)
> > +
> > +.PHONY: run
> > +run: $(TESTS)
> > +=09$(foreach t,$(TESTS),./$(t);)
> > +
> > +.PHONY: clean
> > +clean:
> > +=09$(RM) -- *.o $(TESTS) $(DEPS_RM)
> > +
> > +.PHONY: distclean
> > +distclean: clean
> > +=09$(RM) -- *~
> > +
> > +.PHONY: install
> > +install: all
> > +=09$(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests
> > +=09$(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests
> > +
> > +.PHONY: uninstall
> > +uninstall:
> > +=09$(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid
> > +
> > +CFLAGS +=3D -D__XEN_TOOLS__
> > +CFLAGS +=3D $(APPEND_CFLAGS)
> > +CFLAGS +=3D $(CFLAGS_xeninclude)
> > +CFLAGS +=3D -I./include/
> > +
> > +LDFLAGS +=3D $(APPEND_LDFLAGS)
> > +
> > +test-domid: domid.o test-domid.o
> > +=09$(CC) $^ -o $@ $(LDFLAGS)
> > +
> > +-include $(DEPS_INCLUDE)
> > diff --git a/tools/tests/domid/include/xen/domain.h b/tools/tests/domid=
/include/xen/domain.h
> > new file mode 100644
> > index 000000000000..e5db0235445e
> > --- /dev/null
> > +++ b/tools/tests/domid/include/xen/domain.h
> > @@ -0,0 +1,126 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Unit test harness for domain ID allocator.
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#ifndef _TEST_HARNESS_
> > +#define _TEST_HARNESS_
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +
> > +#define BUG_ON(x)               assert(!(x))
> > +#define ASSERT(x)               assert(x)
> > +
> > +#define DOMID_FIRST_RESERVED    (10)
> > +#define DOMID_INVALID           (11)
> > +
> > +#define DEFINE_SPINLOCK(x)      unsigned long *(x)
>=20
> I think this shouldn't be a pointer?  As you otherwise trigger a NULL
> pointer dereference in the increases and decreases done below?

Sorry, this bitops integration is very raw.

Thanks for all your suggestions, I reworked it.

>=20
> > +#define spin_lock(x)            ((*(x))++)
> > +#define spin_unlock(x)          ((*(x))--)
>=20
> FWIW, I would use a plain bool:
>=20
> #define DEFINE_SPINLOCK(l)      bool l
> #define spin_lock(l)            (*(l) =3D true)
> #define spin_unlock(l)          (*(l) =3D false)
>=20
> As you don't expect concurrency tests, you could even assert the lock
> is in the expected state before taking/releasing it.
>=20
> > +
> > +#define printk printf
> > +
> > +#define BITS_PER_LONG           sizeof(unsigned long)
>=20
> That's BYTES_PER_LONG, BITS_PER_LONG would be (sizeof(unsigned long) * 8)=
.
>=20
> > +#define BITS_PER_WORD           (8U * BITS_PER_LONG)
> > +#define BITS_TO_LONGS(bits) \
> > +    (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
> > +#define DECLARE_BITMAP(name, bits) \
> > +    unsigned long name[BITS_TO_LONGS(bits)]
> > +
> > +static inline int __test_and_set_bit(unsigned int nr, unsigned long *a=
ddr)
> > +{
> > +    unsigned long mask =3D 1UL << (nr % BITS_PER_WORD);
> > +    unsigned long *p =3D addr + (nr / BITS_PER_WORD);
> > +    int old =3D (*p & mask) !=3D 0;
> > +
> > +    *p |=3D mask;
> > +
> > +    return old;
> > +}
> > +
> > +static inline int __test_and_clear_bit(unsigned int nr, unsigned long =
*addr)
> > +{
> > +    unsigned long mask =3D 1UL << (nr % BITS_PER_WORD);
> > +    unsigned long *p =3D addr + (nr / BITS_PER_WORD);
> > +    int old =3D (*p & mask) !=3D 0;
> > +
> > +    *p &=3D ~mask;
> > +
> > +    return old;
> > +}
>=20
> Could you somehow use the generic__test_and_set_bit() and
> generic__test_and_clear_bit() implementations in bitops.h?

I tried that originally, and it pulls a lot of dependencies from xen/bitops=
.h;
that will be a mini project to compile xen/bitops.h for the host, which I
think I can skip doing for the purpose of this test.

I followed another approach as discussed offline in matrix: re-purpose
tools/libs/ctrl/xc_bitops.h which seems to be working nice!

>=20
> > +
> > +static inline void __set_bit(unsigned int nr, volatile unsigned long *=
addr)
> > +{
> > +    unsigned long mask =3D 1UL << (nr % BITS_PER_WORD);
> > +    unsigned long *p =3D (unsigned long *)addr + (nr / BITS_PER_WORD);
>=20
> Why do you need the cast to drop the volatile here?
>=20
> > +
> > +    *p |=3D mask;
> > +}
>=20
> I think you could possibly simplify to a single line:
>=20
>     ((unsigned int *)addr)[nr >> 5] |=3D (1u << (nr & 31));
>=20
> That's the implementation of constant_set_bit() in x86.
>=20
> > +
> > +static inline void __clear_bit(unsigned int nr, volatile unsigned long=
 *addr)
> > +{
> > +    unsigned long mask =3D 1UL << (nr % BITS_PER_WORD);
> > +    unsigned long *p =3D (unsigned long *)addr + (nr / BITS_PER_WORD);
> > +
> > +    *p &=3D ~mask;
> > +}
>=20
> I don't think you need __clear_bit()?  It's not used by domid.c AFAICT.

Overlooked, thanks.

>=20
> > +
> > +static inline unsigned long find_next_zero_bit(const unsigned long *ad=
dr,
> > +                                               unsigned long size,
> > +                                               unsigned long offset)
> > +{
> > +    unsigned long idx =3D offset / BITS_PER_WORD;
> > +    unsigned long bit =3D offset % BITS_PER_WORD;
> > +
> > +    if (offset >=3D size)
> > +        return size;
> > +
> > +    while (offset < size)
> > +    {
> > +        unsigned long val =3D addr[idx] | (~0UL >> (BITS_PER_WORD - bi=
t));
> > +
> > +        if (~val)
> > +        {
> > +            unsigned long pos =3D __builtin_ffsl(~val);
> > +
> > +            if (pos > 0)
> > +            {
> > +                unsigned long rc =3D idx * BITS_PER_WORD + (pos - 1);
> > +
> > +                if (rc < size)
> > +                    return rc;
> > +            }
> > +        }
> > +
> > +        offset =3D (idx + 1) * BITS_PER_WORD;
> > +        idx++;
> > +        bit =3D 0;
> > +    }
> > +
> > +    return size;
> > +}
>=20
> Hm, you need a full find_next_zero_bit() implementation here because
> addr can be arbitrarily long.  Could you somehow include
> xen/lib/find-next-bit.c and set the right defines so only the
> implementation of find_next_bit() is included?

That's a good idea!

xen/lib/find-next-bit.c seems to be integrating pretty simple.

Thanks for the hint!

>=20
> > +
> > +typedef bool spinlock_t;
>=20
> You want to put this ahead, so that DEFINE_SPINLOCK can be:
>=20
> #define DEFINE_SPINLOCK(l)      spinlock_t l
>=20
> > +typedef uint16_t domid_t;
> > +
> > +/* See include/xen/domain.h */
> > +extern domid_t domid_alloc(domid_t domid);
> > +extern void domid_free(domid_t domid);
> > +
> > +#endif /* _TEST_HARNESS_ */
> > +
> > +/*
> > + * Local variables:
> > + * mode: C
> > + * c-file-style: "BSD"
> > + * c-basic-offset: 4
> > + * indent-tabs-mode: nil
> > + * End:
> > + */
> > diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-do=
mid.c
> > new file mode 100644
> > index 000000000000..d52eaf5f1f55
> > --- /dev/null
> > +++ b/tools/tests/domid/test-domid.c
> > @@ -0,0 +1,78 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Unit tests for domain ID allocator.
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +/* Local test include replicating hypervisor includes. */
> > +#include 
>=20
> I think this is a difficult to maintain position.  Right now domid.c
> only includes xen/domain.h, so you can easily replace this in
> user-space.  However if/when domid.c starts including more headers,
> replicating this in user-space will be cumbersome IMO.
>=20
> I would just guard the includes in domid.c with #ifdef __XEN__ for the
> preprocessor to remove them when domid.c is compiled as part of the
> unit-tests harness.
>=20
> I usually include a harness.h that contains the glue to make the
> imported code build (much like what you have placed in the test
> harness xen/domain.h header.

I like that there's no need to modify the tested code.

I reworked this slightly differently: local include/xen/domain.h is a symli=
nk
to local harness.h, and all future dependendent files will be symlinks to
harness.h as well.

>=20
> > +
> > +int main(int argc, char **argv)
> > +{
> > +    domid_t expected, allocated;
> > +
> > +    printf("DOMID_FIRST_RESERVED=3D%u DOMID_INVALID=3D%u\n",
> > +            DOMID_FIRST_RESERVED, DOMID_INVALID);
> > +
> > +    /* Test ID#0 cannot be allocated twice. */
> > +    allocated =3D domid_alloc(0);
> > +    printf("TEST 1: expected %u allocated %u\n", 0, allocated);
> > +    ASSERT(allocated =3D=3D 0);
> > +    allocated =3D domid_alloc(0);
> > +    printf("TEST 1: expected %u allocated %u\n", DOMID_INVALID, alloca=
ted);
> > +    ASSERT(allocated =3D=3D DOMID_INVALID);
> > +
> > +    /* Ensure ID is not allocated. */
> > +    domid_free(0);
> > +
> > +    /*
> > +     * Test that that two consecutive calls of domid_alloc(DOMID_INVAL=
ID)
> > +     * will never return the same ID.
> > +     * NB: ID#0 is reserved and shall not be allocated by
> > +     * domid_alloc(DOMID_INVALID).
> > +     */
> > +    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED; expected++ =
)
> > +    {
> > +        allocated =3D domid_alloc(DOMID_INVALID);
> > +        printf("TEST 2: expected %u allocated %u\n", expected, allocat=
ed);
> > +        ASSERT(allocated =3D=3D expected);
> > +    }
> > +    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED; expected++ =
)
> > +    {
> > +        allocated =3D domid_alloc(DOMID_INVALID);
> > +        printf("TEST 3: expected %u allocated %u\n", DOMID_INVALID, al=
located);
> > +        ASSERT(allocated =3D=3D DOMID_INVALID);
> > +    }
> > +
> > +    /* Re-allocate first ID from [1..DOMID_FIRST_RESERVED - 1]. */
> > +    expected =3D 1;
> > +    domid_free(1);
> > +    allocated =3D domid_alloc(DOMID_INVALID);
> > +    printf("TEST 4: expected %u allocated %u\n", expected, allocated);
> > +    ASSERT(allocated =3D=3D expected);
> > +
> > +    /* Re-allocate last ID from [1..DOMID_FIRST_RESERVED - 1]. */
> > +    expected =3D DOMID_FIRST_RESERVED - 1;
> > +    domid_free(DOMID_FIRST_RESERVED - 1);
> > +    allocated =3D domid_alloc(DOMID_INVALID);
> > +    printf("TEST 5: expected %u allocated %u\n", expected, allocated);
> > +    ASSERT(allocated =3D=3D expected);
> > +
> > +    /* Allocate an invalid ID. */
> > +    expected =3D DOMID_INVALID;
> > +    allocated =3D domid_alloc(DOMID_FIRST_RESERVED);
> > +    printf("TEST 6: expected %u allocated %u\n", expected, allocated);
> > +    ASSERT(allocated =3D=3D expected);
>=20
> I would make this a bit less chatty maybe?

Ack.

>=20
> I think you only need to print on errors, and you probably don't want
> to ASSERT() on failure, and rather try to finish all the tests in
> order to report multiple failures in a single run.

I thought about it originally, but my "tests" depend on each other, so I'll
keep failing on the first error as is, if there's no strong objection.

>=20
> Thanks, Roger.



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Volodymyr Babchuk ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Oleksandr Andrushchenko ,
	Mykola Kvach 
Subject: [PATCH v5] xen/char: implement suspend/resume calls for SCIF driver
Date: Thu,  7 Aug 2025 08:16:52 +0300
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From: Volodymyr Babchuk 

Implement suspend and resume callbacks for the SCIF UART driver,
enabled when CONFIG_SYSTEM_SUSPEND is set. This allows proper
handling of UART state across system suspend/resume cycles.

Tested on Renesas R-Car H3 Starter Kit.

Signed-off-by: Volodymyr Babchuk 
Signed-off-by: Oleksandr Andrushchenko 
Signed-off-by: Mykola Kvach 
---
In patch v5, there are no changes at all;
it was done just to trigger a review.

In patch v4, enhance commit message, no functional changes

In patch v2, I just added a CONFIG_SYSTEM_SUSPEND check around
the suspend/resume functions in the SCIF driver.
---
 xen/drivers/char/scif-uart.c | 40 ++++++++++++++++++++++++++++++++++--
 1 file changed, 38 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c
index 757793ca45..888821a3b8 100644
--- a/xen/drivers/char/scif-uart.c
+++ b/xen/drivers/char/scif-uart.c
@@ -139,9 +139,8 @@ static void scif_uart_interrupt(int irq, void *data)
     }
 }
 
-static void __init scif_uart_init_preirq(struct serial_port *port)
+static void scif_uart_disable(struct scif_uart *uart)
 {
-    struct scif_uart *uart = port->uart;
     const struct port_params *params = uart->params;
 
     /*
@@ -155,6 +154,14 @@ static void __init scif_uart_init_preirq(struct serial_port *port)
 
     /* Reset TX/RX FIFOs */
     scif_writew(uart, SCIF_SCFCR, SCFCR_RFRST | SCFCR_TFRST);
+}
+
+static void scif_uart_init_preirq(struct serial_port *port)
+{
+    struct scif_uart *uart = port->uart;
+    const struct port_params *params = uart->params;
+
+    scif_uart_disable(uart);
 
     /* Clear all errors and flags */
     scif_readw(uart, params->status_reg);
@@ -271,6 +278,31 @@ static void scif_uart_stop_tx(struct serial_port *port)
     scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) & ~SCSCR_TIE);
 }
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+
+static void scif_uart_suspend(struct serial_port *port)
+{
+    struct scif_uart *uart = port->uart;
+
+    scif_uart_stop_tx(port);
+    scif_uart_disable(uart);
+}
+
+static void scif_uart_resume(struct serial_port *port)
+{
+    struct scif_uart *uart = port->uart;
+    const struct port_params *params = uart->params;
+    uint16_t ctrl;
+
+    scif_uart_init_preirq(port);
+
+    /* Enable TX/RX and Error Interrupts  */
+    ctrl = scif_readw(uart, SCIF_SCSCR);
+    scif_writew(uart, SCIF_SCSCR, ctrl | params->irq_flags);
+}
+
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
 static struct uart_driver __read_mostly scif_uart_driver = {
     .init_preirq  = scif_uart_init_preirq,
     .init_postirq = scif_uart_init_postirq,
@@ -281,6 +313,10 @@ static struct uart_driver __read_mostly scif_uart_driver = {
     .start_tx     = scif_uart_start_tx,
     .stop_tx      = scif_uart_stop_tx,
     .vuart_info   = scif_vuart_info,
+#ifdef CONFIG_SYSTEM_SUSPEND
+    .suspend      = scif_uart_suspend,
+    .resume       = scif_uart_resume,
+#endif
 };
 
 static const struct dt_device_match scif_uart_dt_match[] __initconst =
-- 
2.48.1



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From: Mykola Kvach 
Date: Thu, 7 Aug 2025 08:47:54 +0300
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Subject: Re: [PATCH] xen/domctl: add domain_lock in XEN_DOMCTL_setvcpucontext
To: Jan Beulich 
Cc: Mykola Kvach , Andrew Cooper , 
	Anthony PERARD , Michal Orzel , 
	Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Stefano Stabellini , xen-devel@lists.xenproject.org
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Hi Jan,

On Tue, Jul 29, 2025 at 10:56=E2=80=AFAM Jan Beulich  wr=
ote:
>
> On 28.07.2025 20:40, Mykola Kvach wrote:
> > From: Mykola Kvach 
> >
> > Add domain_{lock,unlock} in the XEN_DOMCTL_setvcpucontext operation
> > for protecting arch_set_info_guest.
> >
> > This aligns with the locking pattern used by other operations that
> > modify vCPU state.
> >
> > Signed-off-by: Mykola Kvach 
>
> I think this requires more of a description / justification. May I in
> particular turn your attention to this comment that we have in x86'es
> handling of HVM_PARAM_IDENT_PT (disregard the 1st sentence for the
> purpose here):
>
>         /*
>          * Update GUEST_CR3 in each VMCS to point at identity map.
>          * All foreign updates to guest state must synchronise on
>          * the domctl_lock.
>          */
>         rc =3D -ERESTART;
>         if ( !domctl_lock_acquire(d) )
>             break;
>
> IOW in particular I'd expect you to explain why holding the domctl
> lock isn't sufficient here, and hence what (theoretical?) race it is
> you're concerned about. That may in turn clarify whether a Fixes: tag
> would actually be appropriate here.

For example, on ARM systems, we bring up vCPUs via PSCI. At the same time,
from another domain, XEN_DOMCTL_setvcpucontext may be called. In the PSCI
path, access is protected by domain_lock, but domain_pause alone is not
sufficient to prevent races during modification of the vCPU context from
XEN_DOMCTL_setvcpucontext.

>
> Jan
>
> > --- a/xen/common/domctl.c
> > +++ b/xen/common/domctl.c
> > @@ -392,7 +392,9 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t)=
 u_domctl)
> >          if ( ret =3D=3D 0 )
> >          {
> >              domain_pause(d);
> > +            domain_lock(d);
> >              ret =3D arch_set_info_guest(v, c);
> > +            domain_unlock(d);
> >              domain_unpause(d);
> >
> >              if ( ret =3D=3D -ERESTART )
>

Best regards,
Mykola


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MIME-Version: 1.0
Date: Thu, 07 Aug 2025 09:33:19 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, Doug Goldstein ,
 Stefano Stabellini , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Jan Beulich , Julien
 Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
Subject: Re: [PATCH v4] misra: add deviations of MISRA C Rule 5.5
In-Reply-To: 
References: 
Message-ID: <874c914eafd42020afc2087eccf4d7a3@bugseng.com>
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On 2025-07-31 22:43, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 5.5 states: "Identifiers shall be distinct from macro 
> names".
> 
> Update ECLAIR configuration to deviate clashes: specify the macros that
> should be ignored. Update deviations.rst and rules.rst accordingly.
> 
> Signed-off-by: Dmytro Prokopchuk 

Reviewed-by: Nicola Vetrini 

> ---
> Changes in v4:
> - fixed formatting (aligned length chars per line)
> - set 'ignored_macros' as a regex expression
> - set a deviation restriction on xen/common/grant_table.c
> - s/ensures/to ensure/
> - fixed grammar errors
> 
> Link to v3:
> https://patchew.org/Xen/e681e0c083d945f48e6d0add1aee32af16be224e.1753911247.git.dmytro._5Fprokopchuk1@epam.com/
> 
> Test CI pipeline:
> https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1960066579
> ---
>  .../eclair_analysis/ECLAIR/deviations.ecl     | 10 +++++++++
>  docs/misra/deviations.rst                     | 22 +++++++++++++++++++
>  docs/misra/rules.rst                          | 17 ++++++++++++++
>  3 files changed, 49 insertions(+)
> 
> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl 
> b/automation/eclair_analysis/ECLAIR/deviations.ecl
> index 483507e7b9..ab3400fc89 100644
> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -117,6 +117,16 @@ it defines would (in the common case) be already 
> defined. Peer reviewed by the c
>  -config=MC3A2.R5.5,reports+={deliberate, 
> "any_area(decl(kind(function))||any_loc(macro(name(memcpy||memset||memmove))))&&any_area(any_loc(file(^xen/common/libelf/libelf-private\\.h$)))"}
>  -doc_end
> 
> +-doc_begin="Clashes between bitops functions and macro names are 
> deliberate.
> +These macros are needed for input validation and error handling."
> +-config=MC3A2.R5.5,ignored_macros+="^(__)?(test|set|clear|change|test_and_(set|clear|change))_bit$"
> +-doc_end
> +
> +-doc_begin="Clashes between grant table functions and macro names in 
> 'xen/common/grant_table.c' are deliberate.
> +These macros address differences in argument count during 
> compile-time, effectively discarding unused parameters to avoid 
> warnings or errors related to them."
> +-config=MC3A2.R5.5,ignored_macros+="name(update_gnttab_par||parse_gnttab_limit)&&loc(file(^xen/common/grant_table\\.c$))"
> +-doc_end
> +
>  -doc_begin="The type \"ret_t\" is deliberately defined multiple times,
>  depending on the guest."
>  
> -config=MC3A2.R5.6,reports+={deliberate,"any_area(any_loc(text(^.*ret_t.*$)))"}
> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
> index e78179fcb8..4c64a8be62 100644
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -142,6 +142,28 @@ Deviations related to MISRA C:2012 Rules:
>         memmove.
>       - Tagged as `deliberate` for ECLAIR.
> 
> +   * - R5.5
> +     - Clashes between bitops ('__test_and_set_bit', 
> '__test_and_clear_bit',
> +       '__test_and_change_bit', 'test_bit', 'set_bit', 'clear_bit', 
> 'change_bit',
> +       'test_and_set_bit', 'test_and_clear_bit', 
> 'test_and_change_bit')
> +       functions and macro names are intentional. These are necessary 
> for error
> +       handling and input validation to ensure that the size of the 
> object being
> +       referenced by the memory address (passed as an argument to the 
> macro)
> +       meets the minimum requirements for the bit operation. This 
> prevents unsafe
> +       operations on improperly sized data types that could lead to 
> undefined
> +       behavior or memory corruption. The macros encapsulate this 
> conditional
> +       logic into a single, reusable form, simplifying the code and 
> avoiding
> +       function call overhead. Also this bit operations API was 
> inherited from
> +       Linux and should be kept for familiarity.
> +     - ECLAIR has been configured to ignore these macros.
> +
> +   * - R5.5
> +     - Clashes between grant table ('update_gnttab_par', 
> 'parse_gnttab_limit')
> +       functions and macro names are intentional. These macros address
> +       differences in argument count during compile-time, effectively 
> discarding
> +       unused 2nd and 3rd parameters to avoid warnings or errors 
> related to them.
> +     - ECLAIR has been configured to ignore these macros.
> +
>     * - R5.6
>       - The type ret_t is deliberately defined multiple times depending 
> on the
>         type of guest to service.
> diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
> index 3e014a6298..cba15933fe 100644
> --- a/docs/misra/rules.rst
> +++ b/docs/misra/rules.rst
> @@ -196,6 +196,23 @@ maintainers if you want to suggest a change.
>             #define f(x, y) f(x, y)
>             void f(int x, int y);
> 
> +       Clashes between bitops functions and macro names are allowed
> +       because they are used for input validation and error handling.
> +       Example::
> +
> +           static inline void set_bit(int nr, volatile void *addr)
> +           {
> +               asm volatile ( "lock btsl %1,%0"
> +                              : "+m" (ADDR) : "Ir" (nr) : "memory");
> +           }
> +           #define set_bit(nr, addr) ({                            \
> +               if ( bitop_bad_size(addr) ) __bitop_bad_size();     \
> +               set_bit(nr, addr);                                  \
> +           })
> +
> +       Clashes between grant table functions and macro names are 
> allowed
> +       because they are used for discarding unused parameters.
> +
>     * - `Rule 5.6 
> `_
>       - Required
>       - A typedef name shall be a unique identifier

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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From: Mykola Kvach 
Date: Thu, 7 Aug 2025 10:38:46 +0300
X-Gm-Features: Ac12FXzENTIOvUC_-kobFDIHWBUHMvWuVpSCa-16IyJxIrWtUNP4OgitmvWAiJQ
Message-ID: 
Subject: Re: [PATCH v7 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Jan Beulich 
Cc: Mykola Kvach , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Andrew Cooper , Anthony PERARD , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	xen-devel@lists.xenproject.org
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Hi Jan,

On Tue, Jul 29, 2025 at 12:11=E2=80=AFPM Jan Beulich  wr=
ote:
>
> On 29.07.2025 10:52, Mykola Kvach wrote:
> > --- a/xen/common/domain.c
> > +++ b/xen/common/domain.c
> > @@ -1334,16 +1334,15 @@ int domain_shutdown(struct domain *d, u8 reason=
)
> >      return 0;
> >  }
> >
> > -void domain_resume(struct domain *d)
> > +#ifdef CONFIG_ARM
> > +void domain_resume_nopause(struct domain *d)
> > +#else
> > +static void domain_resume_nopause(struct domain *d)
> > +#endif
>
> #ifndef CONFIG_ARM
> static
> #endif
> void domain_resume_nopause(struct domain *d)
>
> to have as little redundancy as possible.

Okay, I=E2=80=99ll change it.

>
> >  {
> >      struct vcpu *v;
> >
> > -    /*
> > -     * Some code paths assume that shutdown status does not get reset =
under
> > -     * their feet (e.g., some assertions make this assumption).
> > -     */
> > -    domain_pause(d);
> > -
> > +    domain_lock(d);
>
> This addition of locking affects domain_resume() as well. Neither need no=
r
> correctness are discussed in the description. If the locking was really
> needed for domain_resume() as well, I suppose adding that would better be
> a separate change anyway.

Thanks for the review.

The locking was added to avoid potential races involving _VPF_suspended and
the suspend/resume logic.

Consider the case where domain_lock() is not used inside domain_resume():

Domain 1 initiates suspend via PSCI SYSTEM_SUSPEND. At the same time,
Domain 0 invokes resume for Domain 1.

Domain 0 calls xl resume, which leads to domain_resume(). Domain 1 acquires
domain_lock() as part of the suspend path. Then it acquires the shutdown
lock in domain_shutdown(). Domain 0 is blocked waiting for the shutdown
lock. When Domain 1 releases the shutdown lock, it sets _VPF_suspended and
modifies the VCPU context. Then Domain 0 clears _VPF_suspended.

At this point, ctxt_switch_from() might be called with _VPF_suspended
already cleared, and the VCPU context partially updated. For example, the
guest PC is set to the resume entry point, but some registers like TTBR or
SCTLR_EL1 are saved from the current hardware context by
ctxt_switch_from.

However, after reviewing the flow again, I think this kind of race could
still happen even with the lock in place. Imagine Domain 1 sets the flag
via SYSTEM_SUSPEND, and then Domain 0 clears it by resuming the domain
before the first context switch. This could still result in a partially
updated context with inconsistent state.

So it might be better to update the VCPU context at the point of resume
instead of doing it during suspend. I'll look into that further and also
check for other possible races if the update is moved.

>
> The addition of this locking is particularly interesting considering that
> ...
>
> >      spin_lock(&d->shutdown_lock);
>
> ... is what follows right after.
>
> > --- a/xen/include/xen/sched.h
> > +++ b/xen/include/xen/sched.h
> > @@ -814,6 +814,9 @@ void domain_destroy(struct domain *d);
> >  int domain_kill(struct domain *d);
> >  int domain_shutdown(struct domain *d, u8 reason);
> >  void domain_resume(struct domain *d);
> > +#ifdef CONFIG_ARM
> > +void domain_resume_nopause(struct domain *d);
> > +#endif
> >
> >  int domain_soft_reset(struct domain *d, bool resuming);
> >
> > @@ -1010,6 +1013,10 @@ static inline struct domain *next_domain_in_cpup=
ool(
> >  /* VCPU is parked. */
> >  #define _VPF_parked          8
> >  #define VPF_parked           (1UL<<_VPF_parked)
> > +/* VCPU is suspended. */
> > +#define _VPF_suspended       9
> > +#define VPF_suspended        (1UL<<_VPF_suspended)
>
> Irrespective of the style violations in pre-existing code, can you please
> not add further violations, by inserting the missing blanks?

Okay

>
> > +
> >
>
> Please also don't introduce double blank lines.

I'll remove it.

>
> Jan

Best regards,
Mykola


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To: =?utf-8?Q?Marek_Marczykowski-G=C3=B3recki?= 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, Doug Goldstein , Stefano Stabellini 
Subject: Re: [PATCH v1 1/2] CI: Add driver domains tests
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On Thu, Aug 07, 2025 at 02:06:49AM +0200, Marek Marczykowski-G=C3=B3recki w=
rote:
> Setup a simple two domU system. One with network backend, running
> xendriverdomain service, and one with frontend, trying to ping the
> backend.
>=20
> Contrary to other similar tests, use disk image instead of initrd, to
> allow bigger rootfs without adding more RAM (for both dom0 and domU).
> But keep using pxelinux as a bootloader as it's easier to setup than
> installing grub on the disk. Theoretically, it could be started via direc=
t
> kernel boot in QEMU, but pxelinux is slightly closer to real-world
> deployment.
>=20
> Signed-off-by: Marek Marczykowski-G=C3=B3recki 
> ---
>  automation/gitlab-ci/test.yaml                  |   8 +-
>  automation/scripts/qemu-driverdomains-x86_64.sh | 116 +++++++++++++++++-
>  2 files changed, 124 insertions(+)
>  create mode 100755 automation/scripts/qemu-driverdomains-x86_64.sh
>=20
> diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.y=
aml
> index 1f0b27b2378a..5c4b2dc304b4 100644
> --- a/automation/gitlab-ci/test.yaml
> +++ b/automation/gitlab-ci/test.yaml
> @@ -656,6 +656,14 @@ qemu-alpine-x86_64-gcc:
>      - *x86-64-test-needs
>      - alpine-3.18-gcc
>=20
> +qemu-alpine-driverdomains-x86_64-gcc:
> +  extends: .qemu-x86-64
> +  script:
> +    - ./automation/scripts/qemu-driverdomains-x86_64.sh 2>&1 | tee ${LOG=
FILE}
> +  needs:
> +    - *x86-64-test-needs
> +    - alpine-3.18-gcc
> +
>  qemu-smoke-x86-64-gcc:
>    extends: .qemu-smoke-x86-64
>    script:
> diff --git a/automation/scripts/qemu-driverdomains-x86_64.sh b/automation=
/scripts/qemu-driverdomains-x86_64.sh
> new file mode 100755
> index 000000000000..1caaede7722e
> --- /dev/null
> +++ b/automation/scripts/qemu-driverdomains-x86_64.sh
> @@ -0,0 +1,116 @@
> +#!/bin/bash
> +
> +set -ex -o pipefail
> +
> +dom0_rootfs_extra_comp=3D()
> +dom0_rootfs_extra_uncomp=3D()
> +
> +cd binaries
> +
> +# DomU rootfs
> +
> +mkdir -p rootfs
> +cd rootfs
> +mkdir -p etc/local.d
> +passed=3D"ping test passed"
> +echo "#!/bin/bash
> +
> +set -x
> +
> +if grep -q test=3Dbackend /proc/cmdline; then
> +    brctl addbr xenbr0
> +    ip link set xenbr0 up
> +    ip addr add 192.168.0.1/24 dev xenbr0
> +    bash /etc/init.d/xendriverdomain start
> +    # log backend-related logs to the console
> +    tail -F /var/log/xen/xldevd.log /var/log/xen/xen-hotplug.log >>/dev/=
console 2>/dev/null &
> +else
> +    ip link set eth0 up
> +    ip addr add 192.168.0.2/24 dev eth0
> +    until ping -c 10 192.168.0.1; do

I would limit the number of iterations (60?), otherwise in the worst case t=
he
test will execute intil the test job timeout, which AFAIU is undesired if
anything goes wrong.

> +        sleep 1
> +    done
> +    echo \"${passed}\"
> +fi
> +
> +" > etc/local.d/xen.start

For the block generating xen.start: suggest switching to heredoc like for
pxelinux.0 config below, this way escaping will not be needed.

> +chmod +x etc/local.d/xen.start
> +zcat ../rootfs.cpio.gz | cpio -imd
> +zcat ../xen-tools.cpio.gz | cpio -imd
> +mkfs.ext4 -d . ../domU-rootfs.img 1024M
> +cd ..
> +rm -rf rootfs
> +
> +# Dom0 rootfs
> +mkdir -p rootfs
> +cd rootfs
> +zcat ../rootfs.cpio.gz | cpio -imd
> +zcat ../xen-tools.cpio.gz | cpio -imd
> +mkdir -p root etc/local.d
> +echo "name=3D\"backend\"
> +memory=3D512
> +vcpus=3D1
> +kernel=3D\"/root/bzImage\"
> +extra=3D\"console=3Dhvc0 root=3D/dev/xvda net.ifnames=3D0 test=3Dbackend=
\"
> +disk=3D[ '/root/domU-rootfs-b.img,raw,xvda,rw' ]
> +" > root/backend.cfg
> +echo "name=3D\"frontend\"
> +memory=3D512
> +vcpus=3D1
> +kernel=3D\"/root/bzImage\"
> +extra=3D\"console=3Dhvc0 root=3D/dev/xvda net.ifnames=3D0 test=3Dfronten=
d\"
> +disk=3D[ '/root/domU-rootfs-f.img,raw,xvda,rw' ]
> +vif=3D[ 'bridge=3Dxenbr0,backend=3Dbackend' ]
> +" > root/frontend.cfg

.. and heredoc here ^^ ?

> +echo "#!/bin/bash
> +
> +set -x
> +
> +bash /etc/init.d/xencommons start
> +
> +xl list
> +
> +tail -F /var/log/xen/console/guest-backend.log 2>/dev/null | sed -e \"s/=
^/(backend) /\" &
> +tail -F /var/log/xen/console/guest-frontend.log 2>/dev/null | sed -e \"s=
/^/(frontend) /\" &
> +xl -vvv create /root/backend.cfg
> +xl -vvv create /root/frontend.cfg
> +" > etc/local.d/xen.start

.. and heredoc here ^^ ?

> +chmod +x etc/local.d/xen.start
> +
> +cp ../domU-rootfs.img ./root/domU-rootfs-b.img
> +cp ../domU-rootfs.img ./root/domU-rootfs-f.img
                                            ^
Perhaps use "backend" and "frontend" suffixes for clarify?

> +cp ../bzImage ./root/
> +mkdir -p etc/default
> +echo 'XENCONSOLED_TRACE=3Dall' >> etc/default/xencommons
> +mkdir -p var/log/xen/console
> +mkfs.ext4 -d . ../dom0-rootfs.img 2048M
> +cd ..
> +rm -rf rootfs
> +
> +cd ..
> +
> +cat >> binaries/pxelinux.0 << EOF
> +#!ipxe
> +
> +kernel xen console=3Dcom1 console_timestamps=3Dboot
> +module bzImage console=3Dhvc0 root=3D/dev/sda net.ifnames=3D0
> +boot
> +EOF
> +
> +# Run the test
> +rm -f smoke.serial
> +export TEST_CMD=3D"qemu-system-x86_64 \
> +    -cpu qemu64,+svm \
> +    -m 2G -smp 2 \
> +    -monitor none -serial stdio \
> +    -nographic \
> +    -device virtio-net-pci,netdev=3Dn0 \
> +    -netdev user,id=3Dn0,tftp=3Dbinaries,bootfile=3D/pxelinux.0 \
> +    -drive file=3Dbinaries/dom0-rootfs.img,format=3Draw"
> +
> +export TEST_LOG=3D"smoke.serial"
> +export BOOT_MSG=3D"Latest ChangeSet: "
> +export LOG_MSG=3D"Domain-0"
> +export PASSED=3D"$passed"
> +
> +./automation/scripts/console.exp | sed 's/\r\+$//'
> --
> git-series 0.9.1
>=20



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Date: Thu, 7 Aug 2025 08:55:56 +0100
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Subject: Re: [PATCH test-artifacts] Add debian rootfs artifact
To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , xen-devel@lists.xenproject.org
Cc: Stefano Stabellini ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
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On 07/08/2025 1:03 am, Marek Marczykowski-Górecki wrote:
> Will be used as dom0/domU in some tests.
>
> Install OpenRC and setup it to start /etc/local.d/ scripts so tests
> don't need different cases for Alpine and Debian.

(Yeah, I got this via CC.)

I was just thinking that we needed some non-Alpine testing too, but for
a different reason.

We have systemd configuration in Xen, and changes to it, yet no CI of
what is the most common init system in Linux these days.

What would need to be different in tests to avoid OpenRC?  If it's only
the script to start the test running, can't we just declare a name, and
arrange for both init systems to run it?

~Andrew


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From: Mykola Kvach 
Date: Thu, 7 Aug 2025 11:27:26 +0300
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Subject: Re: [PATCH] xen/domctl: add domain_lock in XEN_DOMCTL_setvcpucontext
To: Jan Beulich 
Cc: Mykola Kvach , Andrew Cooper , 
	Anthony PERARD , Michal Orzel , 
	Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Stefano Stabellini , xen-devel@lists.xenproject.org
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On Thu, Aug 7, 2025 at 8:47=E2=80=AFAM Mykola Kvach  wrote:
>
> Hi Jan,
>
> On Tue, Jul 29, 2025 at 10:56=E2=80=AFAM Jan Beulich  =
wrote:
> >
> > On 28.07.2025 20:40, Mykola Kvach wrote:
> > > From: Mykola Kvach 
> > >
> > > Add domain_{lock,unlock} in the XEN_DOMCTL_setvcpucontext operation
> > > for protecting arch_set_info_guest.
> > >
> > > This aligns with the locking pattern used by other operations that
> > > modify vCPU state.
> > >
> > > Signed-off-by: Mykola Kvach 
> >
> > I think this requires more of a description / justification. May I in
> > particular turn your attention to this comment that we have in x86'es
> > handling of HVM_PARAM_IDENT_PT (disregard the 1st sentence for the
> > purpose here):
> >
> >         /*
> >          * Update GUEST_CR3 in each VMCS to point at identity map.
> >          * All foreign updates to guest state must synchronise on
> >          * the domctl_lock.
> >          */
> >         rc =3D -ERESTART;
> >         if ( !domctl_lock_acquire(d) )
> >             break;
> >
> > IOW in particular I'd expect you to explain why holding the domctl
> > lock isn't sufficient here, and hence what (theoretical?) race it is
> > you're concerned about. That may in turn clarify whether a Fixes: tag
> > would actually be appropriate here.
>
> For example, on ARM systems, we bring up vCPUs via PSCI. At the same time=
,
> from another domain, XEN_DOMCTL_setvcpucontext may be called. In the PSCI
> path, access is protected by domain_lock, but domain_pause alone is not
> sufficient to prevent races during modification of the vCPU context from
> XEN_DOMCTL_setvcpucontext.

Sorry, we don't need any extra locking here, because domain_pause
performs vCPU blocking synchronously. It waits until the vCPU becomes
non-runnable, and only after that the context is updated.

So this patch isn't needed.

>
> >
> > Jan
> >
> > > --- a/xen/common/domctl.c
> > > +++ b/xen/common/domctl.c
> > > @@ -392,7 +392,9 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_=
t) u_domctl)
> > >          if ( ret =3D=3D 0 )
> > >          {
> > >              domain_pause(d);
> > > +            domain_lock(d);
> > >              ret =3D arch_set_info_guest(v, c);
> > > +            domain_unlock(d);
> > >              domain_unpause(d);
> > >
> > >              if ( ret =3D=3D -ERESTART )
> >
>
> Best regards,
> Mykola


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Subject: Re: [PATCH v3 03/20] xen/riscv: introduce VMID allocation and
 manegement
To: Demi Marie Obenour ,
 Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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On 8/6/25 6:50 PM, Demi Marie Obenour wrote:
> On 8/6/25 12:24, Oleksii Kurochko wrote:
>> On 8/6/25 2:05 PM, Jan Beulich wrote:
>>> On 06.08.2025 13:33, Oleksii Kurochko wrote:
>>>> On 8/4/25 5:19 PM, Jan Beulich wrote:
>>>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>>>> @@ -148,6 +149,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id,
>>>>>>     
>>>>>>         console_init_postirq();
>>>>>>     
>>>>>> +    vmid_init();
>>>>> This lives here only temporarily, I assume? Every hart will need to execute
>>>>> it, and hence (like we have it on x86) this may want to be a central place
>>>>> elsewhere.
>>>> I haven’t checked how it is done on x86; I probably should.
>>>>
>>>> I planned to call it for each hart separately during secondary hart bring-up,
>>>> since accessing the|hgatp| register of a hart is required to detect|VMIDLEN|.
>>>> Therefore,|vmid_init()| should be called for secondary harts when their
>>>> initialization code starts executing.
>>> But is this going to be the only per-hart thing that will need doing? Otherwise
>>> the same larger "container" function may want calling instead.
>> Yes, it is going to be the only per-hart operation.
>>
>> There is|__cpu_up()| (not yet upstreamed [1]), which calls
>> |sbi_hsm_hart_start(hartid, boot_addr, hsm_data)| to start a hart, and I planned
>> to place|vmid_init()| somewhere in the code executed at|boot_addr|.
>>
>> [1]https://gitlab.com/xen-project/people/olkur/xen/-/blob/latest/xen/arch/riscv/smpboot.c#L40
>>
>>>>>> +{
>>>>>> +    unsigned long vmid_bits;
>>>>> Why "long" (also for the function return type)?
>>>> Because csr_read() returns unsigned long as HGATP register has
>>>> 'unsigned long' length.
>>> Oh, right, I should have commented on the function return type only.
>>> Yet then I also can't resist stating that this kind of use of a variable,
>>> which initially is assigned a value that doesn't really fit its name, is
>>> easily misleading towards giving such comments.
>>>
>>>> But it could be done in this way:
>>>>        csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>>>        vmid_bits =  MASK_EXTR(csr_read(CSR_HGATP), HGATP_VMID_MASK);
>>>>        vmid_bits = ffs_g(vmid_bits);
>>>>        csr_write(CSR_HGATP, old);
>>>> And then use uint16_t for vmid_bits and use uin16_t as a return type.
>>> Please check ./CODING_STYLE again as to the use of fixed-width types.
>> I meant unsigned short, uint16_t was just short to write. I'll try to be
>> more specific.
>>
>>>>>> +    unsigned long old;
>>>>>> +
>>>>>> +    /* Figure-out number of VMID bits in HW */
>>>>>> +    old = csr_read(CSR_HGATP);
>>>>>> +
>>>>>> +    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>>>>> +    vmid_bits = csr_read(CSR_HGATP);
>>>>>> +    vmid_bits =  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);
>>>>> Nit: Stray blank.
>>>>>
>>>>>> +    vmid_bits = flsl(vmid_bits);
>>>>>> +    csr_write(CSR_HGATP, old);
>>>>>> +
>>>>>> +    /*
>>>>>> +     * We polluted local TLB so flush all guest TLB as
>>>>>> +     * a speculative access can happen at any time.
>>>>>> +     */
>>>>>> +    local_hfence_gvma_all();
>>>>> There's no guest running. If you wrote hgat.MODE as zero, as per my
>>>>> understanding now new TLB entries could even purely theoretically appear.
>>>> It could be an issue (or, at least, it is recommended) when hgatp.MODE is
>>>> changed:
>>>>     If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0
>>>>     (and rs2 set to either x0 or the VMID) must be executed to order subsequent
>>>>     guest translations with the MODE change—even if the old MODE or new MODE
>>>>     is Bare.
>>>> On other hand it is guaranteed that, at least, on Reset (and so I assume
>>>> for power on) that:
>>>>     If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE
>>>>     fields are reset to 0.
>>>>
>>>> So it seems like if no guest is ran then there is no need even to write
>>>> hgatp.MODE as zero, but it might be sense to do that explicitly just to
>>>> be sure.
>>>>
>>>> I thought it was possible to have a running guest and perform a CPU hotplug.
>>> But that guest will run on another hart.
>>>
>>>> In that case, I expect that during the hotplug,|vmidlen_detect()| will be
>>>> called and return the|vmid_bits| value, which is used as the active VMID.
>>>> At that moment, the local TLB could be speculatively polluted, I think.
>>>> Likely, it makes sense to call vmidlen_detect() only once for each hart
>>>> during initial bringup.
>>> That may bring you more problems than it solves. You'd need to stash away
>>> the value originally read somewhere. And that somewhere isn't per-CPU data.
>>>
>>>>> In fact, with no guest running (yet) I'm having a hard time seeing why
>>>>> you shouldn't be able to simply write the register with just
>>>>> HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable
>>>>> whether "old" needs restoring; writing plain zero afterwards ought to
>>>>> suffice. You're in charcge of the register, after all.
>>>> It make sense (but I don't know if it is a possible case) to be sure that
>>>> HGATP.MODE remains the same, so there is no need to have TLB flush. If
>>>> HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned
>>>> above.
>>>>
>>>> If we agreed to keep local_hfence_gvma_all() then I think it isn't really
>>>> any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.
>>>>
>>>> Generally if 'old' is guaranteed to be zero (and, probably, it makes sense
>>>> to check that in vmidlen_detect() and panic if it isn't zero) and if
>>>> vmidlen_detect() function will be called before any guest domain(s) will
>>>> be ran then I could agree that we don't need local_hfence_gvma_all() here.
>>>>
>>>> As an option we can do local_hfence_gvma_all() only if 'old' value wasn't
>>>> set to zero.
>>>>
>>>> Does it make sense?
>>> Well - I'd like the pre-conditions to be understood better. For example, can
>>> a hart really speculate into guest mode, when the hart is only in the
>>> process of being brought up?
>> I couldn't explicit words that a hart can't speculate into guest mode
>> either on bring up or during its work.
>>
>> But there are some moments in the spec which tells:
>>     Implementations with virtual memory are permitted to perform address
>>     translations speculatively and earlier than required by an explicit
>>     memory access, and are permitted to cache them in address translation
>>     cache structures—including possibly caching the identity mappings from
>>     effective address to physical address used in Bare translation modes and
>>     M-mode.
>> And here:
>>     Implementations may also execute the address-translation algorithm
>>     speculatively at any time, for any virtual address, as long as satp is
>>     active (as defined in Section 10.1.11). Such speculative executions have
>>     the effect of pre-populating the address-translation cache.
>> Where it is explicitly mentioned that speculation can happen in *any time*.
>> And at the same time:
>>     Speculative executions of the address-translation algorithm behave as
>>     non-speculative executions of the algorithm do, except that they must
>>     not set the dirty bit for a PTE, they must not trigger an exception,
>>     and they must not create address-translation cache entries if those
>>     entries would have been invalidated by any SFENCE.VMA instruction
>>     executed by the hart since the speculative execution of the algorithm began.
>> What I read as if TLB was empty before it will stay empty.
> I read that as "flushing the TLB invalidates entries created by speculative
> execution before the TLB flush".

But this part:
   they must not create address-translation cache entries if those entries
   would have been invalidated by any SFENCE.VMA instruction

Doesn't it mean that entries which was invalidated by SFENCE.VMA can't be
inserted into the TLB during speculative execution?

So, if the speculative page walk started before|SFENCE.VMA|,|SFENCE.VMA|
indicates: “All previous TLB entries might be invalid". Therefore, any
speculative TLB entry/that started before/ must*not* be inserted into the
TLB afterward.

So, hardware tracks if a|SFENCE.VMA| occurred/after/ speculation started.
If so, any speculative address translations must be*discarded* or
*not committed*.

>    That is the bare minimum needed for TLB
> flushing to work.  You have to do the TLB flush *after* changing the PTEs,
> not before.
>
> This is true on at least x86 but I expect it to hold in general.

Agree with that.

~ Oleksii

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    On 8/6/25 6:50 PM, Demi Marie Obenour
      wrote:
    
    
    
    
    
      
    On 8/6/25 12:24, Oleksii Kurochko wrote:

    
      
    
        
    On 8/6/25 2:05 PM, Jan Beulich wrote:

    
        
    
          
    On 06.08.2025 13:33, Oleksii Kurochko wrote:

    
          
    
            
    On 8/4/25 5:19 PM, Jan Beulich wrote:

    
            
    
              
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
              
    
                
    @@ -148,6 +149,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id,
   
       console_init_postirq();
   
+    vmid_init();

    
              
    
              
    This lives here only temporarily, I assume? Every hart will need to execute
it, and hence (like we have it on x86) this may want to be a central place
elsewhere.

    
            
    
            
    I haven’t checked how it is done on x86; I probably should.

I planned to call it for each hart separately during secondary hart bring-up,
since accessing the|hgatp| register of a hart is required to detect|VMIDLEN|.
Therefore,|vmid_init()| should be called for secondary harts when their
initialization code starts executing.

    
          
    
          
    But is this going to be the only per-hart thing that will need doing? Otherwise
the same larger "container" function may want calling instead.

    
        
    
        
    Yes, it is going to be the only per-hart operation.

There is|__cpu_up()| (not yet upstreamed [1]), which calls
|sbi_hsm_hart_start(hartid, boot_addr, hsm_data)| to start a hart, and I planned
to place|vmid_init()| somewhere in the code executed at|boot_addr|.

[1]https://gitlab.com/xen-project/people/olkur/xen/-/blob/latest/xen/arch/riscv/smpboot.c#L40


    
        
    
          
    
            
    
              
    
                
    +{
+    unsigned long vmid_bits;

    
              
    
              
    Why "long" (also for the function return type)?

    
            
    
            
    Because csr_read() returns unsigned long as HGATP register has
'unsigned long' length.

    
          
    
          
    Oh, right, I should have commented on the function return type only.
Yet then I also can't resist stating that this kind of use of a variable,
which initially is assigned a value that doesn't really fit its name, is
easily misleading towards giving such comments.


    
          
    
            
    But it could be done in this way:
      csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
      vmid_bits =  MASK_EXTR(csr_read(CSR_HGATP), HGATP_VMID_MASK);
      vmid_bits = ffs_g(vmid_bits);
      csr_write(CSR_HGATP, old);
And then use uint16_t for vmid_bits and use uin16_t as a return type.

    
          
    
          
    Please check ./CODING_STYLE again as to the use of fixed-width types.

    
        
    
        
    I meant unsigned short, uint16_t was just short to write. I'll try to be
more specific.


    
        
    
          
    
          
    
            
    
              
    
                
    +    unsigned long old;
+
+    /* Figure-out number of VMID bits in HW */
+    old = csr_read(CSR_HGATP);
+
+    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
+    vmid_bits = csr_read(CSR_HGATP);
+    vmid_bits =  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);

    
              
    
              
    Nit: Stray blank.


    
              
    
                
    +    vmid_bits = flsl(vmid_bits);
+    csr_write(CSR_HGATP, old);
+
+    /*
+     * We polluted local TLB so flush all guest TLB as
+     * a speculative access can happen at any time.
+     */
+    local_hfence_gvma_all();

    
              
    
              
    There's no guest running. If you wrote hgat.MODE as zero, as per my
understanding now new TLB entries could even purely theoretically appear.

    
            
    
            
    It could be an issue (or, at least, it is recommended) when hgatp.MODE is
changed:
   If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0
   (and rs2 set to either x0 or the VMID) must be executed to order subsequent
   guest translations with the MODE change—even if the old MODE or new MODE
   is Bare.
On other hand it is guaranteed that, at least, on Reset (and so I assume
for power on) that:
   If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE
   fields are reset to 0.

So it seems like if no guest is ran then there is no need even to write
hgatp.MODE as zero, but it might be sense to do that explicitly just to
be sure.

I thought it was possible to have a running guest and perform a CPU hotplug.

    
          
    
          
    But that guest will run on another hart.


    
          
    
            
    In that case, I expect that during the hotplug,|vmidlen_detect()| will be
called and return the|vmid_bits| value, which is used as the active VMID.
At that moment, the local TLB could be speculatively polluted, I think.
Likely, it makes sense to call vmidlen_detect() only once for each hart
during initial bringup.

    
          
    
          
    That may bring you more problems than it solves. You'd need to stash away
the value originally read somewhere. And that somewhere isn't per-CPU data.


    
          
    
            
    
              
    In fact, with no guest running (yet) I'm having a hard time seeing why
you shouldn't be able to simply write the register with just
HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable
whether "old" needs restoring; writing plain zero afterwards ought to
suffice. You're in charcge of the register, after all.

    
            
    
            
    It make sense (but I don't know if it is a possible case) to be sure that
HGATP.MODE remains the same, so there is no need to have TLB flush. If
HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned
above.

If we agreed to keep local_hfence_gvma_all() then I think it isn't really
any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.

Generally if 'old' is guaranteed to be zero (and, probably, it makes sense
to check that in vmidlen_detect() and panic if it isn't zero) and if
vmidlen_detect() function will be called before any guest domain(s) will
be ran then I could agree that we don't need local_hfence_gvma_all() here.

As an option we can do local_hfence_gvma_all() only if 'old' value wasn't
set to zero.

Does it make sense?

    
          
    
          
    Well - I'd like the pre-conditions to be understood better. For example, can
a hart really speculate into guest mode, when the hart is only in the
process of being brought up?

    
        
    
        
    I couldn't explicit words that a hart can't speculate into guest mode
either on bring up or during its work.

But there are some moments in the spec which tells:
   Implementations with virtual memory are permitted to perform address
   translations speculatively and earlier than required by an explicit
   memory access, and are permitted to cache them in address translation
   cache structures—including possibly caching the identity mappings from
   effective address to physical address used in Bare translation modes and
   M-mode.
And here:
   Implementations may also execute the address-translation algorithm
   speculatively at any time, for any virtual address, as long as satp is
   active (as defined in Section 10.1.11). Such speculative executions have
   the effect of pre-populating the address-translation cache.
Where it is explicitly mentioned that speculation can happen in *any time*.
And at the same time:
   Speculative executions of the address-translation algorithm behave as
   non-speculative executions of the algorithm do, except that they must
   not set the dirty bit for a PTE, they must not trigger an exception,
   and they must not create address-translation cache entries if those
   entries would have been invalidated by any SFENCE.VMA instruction
   executed by the hart since the speculative execution of the algorithm began.
What I read as if TLB was empty before it will stay empty.

    
      
    
      
    I read that as "flushing the TLB invalidates entries created by speculative
execution before the TLB flush".
    
    
    
    
    But this part:
  they must not create address-translation cache entries if those entries
  would have been invalidated by any SFENCE.VMA instruction

Doesn't it mean that entries which was invalidated by SFENCE.VMA can't be
inserted into the TLB during speculative execution?

So, if the speculative page walk started before SFENCE.VMA, SFENCE.VMA
indicates: “All previous TLB entries might be invalid". Therefore, any
speculative TLB entry that started before must not be inserted into the
TLB afterward.

So, hardware tracks if a SFENCE.VMA occurred after speculation started.
If so, any speculative address translations must be discarded or
not committed.
    
    
    
    
    
      
      That is the bare minimum needed for TLB
flushing to work.  You have to do the TLB flush *after* changing the PTEs,
not before.

This is true on at least x86 but I expect it to hold in general.
    
    
    
    
    Agree with that.

~ Oleksii
    
  


--------------fD8N5IalILLFp4Wq7DTsS7xq--


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Subject: Re: [PATCH 2/2] x86/mm: correct PG_log_dirty definition
To: Jason Andryuk 
Cc: Andrew Cooper , Julien Grall ,
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 Anthony PERARD ,
 Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
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On 06.08.2025 23:24, Jason Andryuk wrote:
> On 2025-08-05 03:59, Jan Beulich wrote:
>> While it is correct that in shim-exclusive mode log-dirty handling is
>> all unreachable code, the present conditional still isn't correct: In a
>> HVM=n and SHADOW_PAGING=n configuration log-dirty code also is all
>> unreachable (and hence violating Misra rule 2.1).
>>
>> As we're aiming at moving away from special casing PV_SHIM_EXCLUSIVE=y,
>> don't retain that part of the conditional.
>>
>> Because of hypercall-defs.c we need to carry out the dependency by
>> introducing a new auxiliary PAGING control.
>>
>> Since compiling out mm/paging.c altogether would entail further changes,
>> merely conditionalize the one function in there (paging_enable()) which
>> would otherwise remain unreachable (Misra rule 2.1 again) when PAGING=n.
>>
>> Fixes: 23d4e0d17b76 ("x86/shim: fix build with PV_SHIM_EXCLUSIVE and SHADOW_PAGING")
>> Signed-off-by: Jan Beulich 
>> ---
>> Of course PAGING is at risk of being confused with MEM_PAGING. It not
>> having a prompt, I hope that's tolerable, as I can't really think of a
>> better name.
>>
>> Other PG_log_dirty pre-processor conditionals then likely also want
>> replacing.

Isn't this remark of mine ...

>> mm/paging.c and mm/p2m-basic.c could also be compiled out
>> altogether when PAGING=n, at the expense of introducing a few more
>> stubs.
>>
>> FTAOD, the Fixes: tag being referenced does not mean this patch corrects
>> the far more recently introduced build issue with the combination of the
>> two features. That's still work that I expect Penny to carry out (with
>> there still being the option of reverting the final part of the earlier
>> series).
>>
> 
>> --- a/xen/arch/x86/mm/paging.c
>> +++ b/xen/arch/x86/mm/paging.c
>> @@ -864,6 +864,7 @@ void paging_final_teardown(struct domain
>>       p2m_final_teardown(d);
>>   }
>>   
>> +#ifdef CONFIG_PAGING
> 
> The file already has a lot of uses of #if PG_log_dirty with similar 
> meaning, if I am not mistaken, so using that would make it more 
> consistent.  But CONFIG_PAGING is directly tied to the Kconfig, so maybe 
> it is better?  Just something I noticed.

... precisely matching your observation? If we want to accept the extra churn,
we certainly can go this route in a follow-on patch.

> Reviewed-by: Jason Andryuk 

Thanks.

Jan


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Date: Thu, 7 Aug 2025 10:57:26 +0200
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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v4] misra: add deviations of MISRA C Rule 5.5
To: Dmytro Prokopchuk1 
Cc: "xen-devel@lists.xenproject.org" ,
 Doug Goldstein ,
 Stefano Stabellini ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Nicola Vetrini 
References: 
 
 <148c16be-03c0-43cd-a394-2b37088f4383@epam.com>
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From: Jan Beulich 
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On 06.08.2025 18:56, Dmytro Prokopchuk1 wrote:
> On 8/1/25 01:32, Nicola Vetrini wrote:
>> On 2025-07-31 22:43, Dmytro Prokopchuk1 wrote:
>>> MISRA C Rule 5.5 states: "Identifiers shall be distinct from macro 
>>> names".
>>>
>>> Update ECLAIR configuration to deviate clashes: specify the macros that
>>> should be ignored. Update deviations.rst and rules.rst accordingly.
>>>
>>> Signed-off-by: Dmytro Prokopchuk 
>>
>> Reviewed-by: Nicola Vetrini  # ECLAIR
>>
>>> ---
>>> Changes in v4:
>>> - fixed formatting (aligned length chars per line)
>>> - set 'ignored_macros' as a regex expression
>>> - set a deviation restriction on xen/common/grant_table.c
>>> - s/ensures/to ensure/
>>> - fixed grammar errors
>>>
>>> Link to v3:
>>> https://eur01.safelinks.protection.outlook.com/? 
>>> url=https%3A%2F%2Fpatchew.org%2FXen%2Fe681e0c083d945f48e6d0add1aee32af16be224e.1753911247.git.dmytro._5Fprokopchuk1%40epam.com%2F&data=05%7C02%7Cdmytro_prokopchuk1%40epam.com%7Ce9d60ddeef764dfa381208ddd0823178%7Cb41b72d04e9f4c268a69f949f367c91d%7C1%7C0%7C638895979778846477%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=n0QPvqr8O8gos%2BYMpZ%2BMOG0spC46A7T56Vpz44wutlw%3D&reserved=0
>>>
>>> Test CI pipeline:
>>> https://eur01.safelinks.protection.outlook.com/? 
>>> url=https%3A%2F%2Fgitlab.com%2Fxen- 
>>> project%2Fpeople%2Fdimaprkp4k%2Fxen%2F- 
>>> %2Fpipelines%2F1960066579&data=05%7C02%7Cdmytro_prokopchuk1%40epam.com%7Ce9d60ddeef764dfa381208ddd0823178%7Cb41b72d04e9f4c268a69f949f367c91d%7C1%7C0%7C638895979778869002%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=z8DtrlxxN8nyrMNRXXW8IktFaru4f3f8N99iirhnbw0%3D&reserved=0
>>> ---
>>>  .../eclair_analysis/ECLAIR/deviations.ecl     | 10 +++++++++
>>>  docs/misra/deviations.rst                     | 22 +++++++++++++++++++
>>>  docs/misra/rules.rst                          | 17 ++++++++++++++
>>>  3 files changed, 49 insertions(+)
>>>
>>> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/ 
>>> automation/eclair_analysis/ECLAIR/deviations.ecl
>>> index 483507e7b9..ab3400fc89 100644
>>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>>> @@ -117,6 +117,16 @@ it defines would (in the common case) be already 
>>> defined. Peer reviewed by the c
>>>  -config=MC3A2.R5.5,reports+={deliberate, 
>>> "any_area(decl(kind(function))||any_loc(macro(name(memcpy||memset|| 
>>> memmove))))&&any_area(any_loc(file(^xen/common/libelf/libelf-private\ 
>>> \.h$)))"}
>>>  -doc_end
>>>
>>> +-doc_begin="Clashes between bitops functions and macro names are 
>>> deliberate.
>>> +These macros are needed for input validation and error handling."
>>> +-config=MC3A2.R5.5,ignored_macros+="^(__)?(test|set|clear|change| 
>>> test_and_(set|clear|change))_bit$"
>>> +-doc_end
>>> +
>>> +-doc_begin="Clashes between grant table functions and macro names in 
>>> 'xen/common/grant_table.c' are deliberate.
>>> +These macros address differences in argument count during compile- 
>>> time, effectively discarding unused parameters to avoid warnings or 
>>> errors related to them."
>>> +-config=MC3A2.R5.5,ignored_macros+="name(update_gnttab_par|| 
>>> parse_gnttab_limit)&&loc(file(^xen/common/grant_table\\.c$))"
>>> +-doc_end
>>> +
>>>  -doc_begin="The type \"ret_t\" is deliberately defined multiple times,
>>>  depending on the guest."
>>>
>>> - 
>>> config=MC3A2.R5.6,reports+={deliberate,"any_area(any_loc(text(^.*ret_t.*$)))"}
>>> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
>>> index e78179fcb8..4c64a8be62 100644
>>> --- a/docs/misra/deviations.rst
>>> +++ b/docs/misra/deviations.rst
>>> @@ -142,6 +142,28 @@ Deviations related to MISRA C:2012 Rules:
>>>         memmove.
>>>       - Tagged as `deliberate` for ECLAIR.
>>>
>>> +   * - R5.5
>>> +     - Clashes between bitops ('__test_and_set_bit', 
>>> '__test_and_clear_bit',
>>> +       '__test_and_change_bit', 'test_bit', 'set_bit', 'clear_bit', 
>>> 'change_bit',
>>> +       'test_and_set_bit', 'test_and_clear_bit', 'test_and_change_bit')
>>> +       functions and macro names are intentional. These are necessary 
>>> for error
>>> +       handling and input validation to ensure that the size of the 
>>> object being
>>> +       referenced by the memory address (passed as an argument to the 
>>> macro)
>>> +       meets the minimum requirements for the bit operation. This 
>>> prevents unsafe
>>> +       operations on improperly sized data types that could lead to 
>>> undefined
>>> +       behavior or memory corruption. The macros encapsulate this 
>>> conditional
>>> +       logic into a single, reusable form, simplifying the code and 
>>> avoiding
>>> +       function call overhead. Also this bit operations API was 
>>> inherited from
>>> +       Linux and should be kept for familiarity.
>>> +     - ECLAIR has been configured to ignore these macros.
>>> +
>>> +   * - R5.5
>>> +     - Clashes between grant table ('update_gnttab_par', 
>>> 'parse_gnttab_limit')
>>> +       functions and macro names are intentional. These macros address
>>> +       differences in argument count during compile-time, effectively 
>>> discarding
>>> +       unused 2nd and 3rd parameters to avoid warnings or errors 
>>> related to them.
>>> +     - ECLAIR has been configured to ignore these macros.
>>> +
>>>     * - R5.6
>>>       - The type ret_t is deliberately defined multiple times 
>>> depending on the
>>>         type of guest to service.
>>> diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
>>> index 3e014a6298..cba15933fe 100644
>>> --- a/docs/misra/rules.rst
>>> +++ b/docs/misra/rules.rst
>>> @@ -196,6 +196,23 @@ maintainers if you want to suggest a change.
>>>             #define f(x, y) f(x, y)
>>>             void f(int x, int y);
>>>
>>> +       Clashes between bitops functions and macro names are allowed
>>> +       because they are used for input validation and error handling.
>>> +       Example::
>>> +
>>> +           static inline void set_bit(int nr, volatile void *addr)
>>> +           {
>>> +               asm volatile ( "lock btsl %1,%0"
>>> +                              : "+m" (ADDR) : "Ir" (nr) : "memory");
>>> +           }
>>> +           #define set_bit(nr, addr) ({                            \
>>> +               if ( bitop_bad_size(addr) ) __bitop_bad_size();     \
>>> +               set_bit(nr, addr);                                  \
>>> +           })
>>> +
>>> +       Clashes between grant table functions and macro names are allowed
>>> +       because they are used for discarding unused parameters.
>>> +
>>>     * - `Rule 5.6 >> url=https%3A%2F%2Fgitlab.com%2FMISRA%2FMISRA-C%2FMISRA- 
>>> C-2012%2FExample-Suite%2F- 
>>> %2Fblob%2Fmaster%2FR_05_06.c&data=05%7C02%7Cdmytro_prokopchuk1%40epam.com%7Ce9d60ddeef764dfa381208ddd0823178%7Cb41b72d04e9f4c268a69f949f367c91d%7C1%7C0%7C638895979778883822%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=crVYwr4A0vyXcUXfQ2%2FJ5EObWfr0XGLgaQ0%2FLH9pMnM%3D&reserved=0>`_
>>>       - Required
>>>       - A typedef name shall be a unique identifier
> 
> Hello Jan, Nicola.
> 
> Do you have any comments regarding this patch?
> Does it require updates/fixes?

Hmm, you have Nicola's R-b, so it's not clear to me what else you need from
him. In its present shape I'm okay for the patch to go in with somebody
else's ack (after all it's not just me who can legitimately ack it); I'm not
happy enough with the patch to give an ack myself, even if I can't offer a
good suggestion towards improvements.

Sorry, Jan


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From: Mykola Kvach 
Date: Thu, 7 Aug 2025 12:15:19 +0300
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Message-ID: 
Subject: Re: [PATCH v7 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Jan Beulich 
Cc: Mykola Kvach , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Andrew Cooper , Anthony PERARD , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	xen-devel@lists.xenproject.org
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On Thu, Aug 7, 2025 at 10:38=E2=80=AFAM Mykola Kvach  wrote:
>
> Hi Jan,
>
> On Tue, Jul 29, 2025 at 12:11=E2=80=AFPM Jan Beulich  =
wrote:
> >
> > On 29.07.2025 10:52, Mykola Kvach wrote:
> > > --- a/xen/common/domain.c
> > > +++ b/xen/common/domain.c
> > > @@ -1334,16 +1334,15 @@ int domain_shutdown(struct domain *d, u8 reas=
on)
> > >      return 0;
> > >  }
> > >
> > > -void domain_resume(struct domain *d)
> > > +#ifdef CONFIG_ARM
> > > +void domain_resume_nopause(struct domain *d)
> > > +#else
> > > +static void domain_resume_nopause(struct domain *d)
> > > +#endif
> >
> > #ifndef CONFIG_ARM
> > static
> > #endif
> > void domain_resume_nopause(struct domain *d)
> >
> > to have as little redundancy as possible.
>
> Okay, I=E2=80=99ll change it.
>
> >
> > >  {
> > >      struct vcpu *v;
> > >
> > > -    /*
> > > -     * Some code paths assume that shutdown status does not get rese=
t under
> > > -     * their feet (e.g., some assertions make this assumption).
> > > -     */
> > > -    domain_pause(d);
> > > -
> > > +    domain_lock(d);
> >
> > This addition of locking affects domain_resume() as well. Neither need =
nor
> > correctness are discussed in the description. If the locking was really
> > needed for domain_resume() as well, I suppose adding that would better =
be
> > a separate change anyway.
>
> Thanks for the review.
>
> The locking was added to avoid potential races involving _VPF_suspended a=
nd
> the suspend/resume logic.
>
> Consider the case where domain_lock() is not used inside domain_resume():
>
> Domain 1 initiates suspend via PSCI SYSTEM_SUSPEND. At the same time,
> Domain 0 invokes resume for Domain 1.
>
> Domain 0 calls xl resume, which leads to domain_resume(). Domain 1 acquir=
es
> domain_lock() as part of the suspend path. Then it acquires the shutdown
> lock in domain_shutdown(). Domain 0 is blocked waiting for the shutdown
> lock. When Domain 1 releases the shutdown lock, it sets _VPF_suspended an=
d
> modifies the VCPU context. Then Domain 0 clears _VPF_suspended.
>
> At this point, ctxt_switch_from() might be called with _VPF_suspended
> already cleared, and the VCPU context partially updated. For example, the
> guest PC is set to the resume entry point, but some registers like TTBR o=
r
> SCTLR_EL1 are saved from the current hardware context by
> ctxt_switch_from.
>
> However, after reviewing the flow again, I think this kind of race could
> still happen even with the lock in place. Imagine Domain 1 sets the flag
> via SYSTEM_SUSPEND, and then Domain 0 clears it by resuming the domain
> before the first context switch. This could still result in a partially
> updated context with inconsistent state.

There are no synchronization issues here -- domain_pause inside domain_resu=
me
prevents them by design.

The only situation where issues might arise is during a SYSTEM_SUSPEND requ=
est
for a guest that has multiple vCPUs online (buggy OS), while another
vCPU performs
a CPU_ON request.

Therefore, it seems we only need to protect the loop that checks if other v=
CPUs
are offline during the SYSTEM_SUSPEND vPSCI call using the domain lock.

>
> So it might be better to update the VCPU context at the point of resume
> instead of doing it during suspend. I'll look into that further and also
> check for other possible races if the update is moved.
>
> >
> > The addition of this locking is particularly interesting considering th=
at
> > ...
> >
> > >      spin_lock(&d->shutdown_lock);
> >
> > ... is what follows right after.
> >
> > > --- a/xen/include/xen/sched.h
> > > +++ b/xen/include/xen/sched.h
> > > @@ -814,6 +814,9 @@ void domain_destroy(struct domain *d);
> > >  int domain_kill(struct domain *d);
> > >  int domain_shutdown(struct domain *d, u8 reason);
> > >  void domain_resume(struct domain *d);
> > > +#ifdef CONFIG_ARM
> > > +void domain_resume_nopause(struct domain *d);
> > > +#endif
> > >
> > >  int domain_soft_reset(struct domain *d, bool resuming);
> > >
> > > @@ -1010,6 +1013,10 @@ static inline struct domain *next_domain_in_cp=
upool(
> > >  /* VCPU is parked. */
> > >  #define _VPF_parked          8
> > >  #define VPF_parked           (1UL<<_VPF_parked)
> > > +/* VCPU is suspended. */
> > > +#define _VPF_suspended       9
> > > +#define VPF_suspended        (1UL<<_VPF_suspended)
> >
> > Irrespective of the style violations in pre-existing code, can you plea=
se
> > not add further violations, by inserting the missing blanks?
>
> Okay
>
> >
> > > +
> > >
> >
> > Please also don't introduce double blank lines.
>
> I'll remove it.
>
> >
> > Jan
>
> Best regards,
> Mykola


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Date: Thu, 7 Aug 2025 11:19:04 +0200
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Subject: Re: [PATCH v1] xenconsole: Add connected flag
To: Jason Andryuk 
Cc: Anthony PERARD ,
 Juergen Gross , xen-devel@lists.xenproject.org
References: <20250807015606.4427-1-jason.andryuk@amd.com>
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From: Jan Beulich 
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On 07.08.2025 03:56, Jason Andryuk wrote:
> --- a/xen/include/public/io/console.h
> +++ b/xen/include/public/io/console.h
> @@ -19,6 +19,19 @@ struct xencons_interface {
>      char out[2048];
>      XENCONS_RING_IDX in_cons, in_prod;
>      XENCONS_RING_IDX out_cons, out_prod;
> +/*
> + * Flag values signaling from backend to frontend whether the console is
> + * connected.  i.e. Whether it will be serviced and emptied.
> + *
> + * The flag starts as disconnected.
> + */
> +#define XENCONSOLE_DISCONNECTED 1
> +/*
> + * The flag is set to connected when the backend connects and the console
> + * will be serviced.
> + */
> +#define XENCONSOLE_CONNECTED    0
> +    uint32_t flag;
>  };

Even if the field name is singular, there's the possible reading of everything
together as the connected state merely taking one bit, with other bits available
for future use. IOW I think the field wants giving a less generic name, and
perhaps also shrinking to unsigned char (or uint8_t, but char is being used in
the structure already anyway).

Jan


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Subject: Re: [PATCH] x86/domctl: Reject XEN_DOMCTL_hypercall_init against
 oneself
To: Andrew Cooper 
Cc: Frediano Ziglio ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Ross Lagerwall ,
 Xen-devel 
References: <20250806165543.169140-1-andrew.cooper3@citrix.com>
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From: Jan Beulich 
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On 06.08.2025 18:55, Andrew Cooper wrote:
> --- a/xen/arch/x86/domctl.c
> +++ b/xen/arch/x86/domctl.c
> @@ -372,6 +372,14 @@ long arch_do_domctl(
>          struct page_info *page;
>          void *hypercall_page;
>  
> +        /*
> +         * Kernels should use the MSR method to get a hypercall page.  The
> +         * toolstack should not be using the DOMCTL on itself.
> +         */
> +        ret = -EINVAL;
> +        if ( d == currd )
> +            break;

Isn't what the comment says more generally true? To act on themselves, most
domctl-s are inappropriate to use, I think. There are a few exceptions, where
alternatives simply don't exist (and where, if a kernel wanted to use a domctl
[or sysctl], it would need to go through hoops to deal with the interface
versioning). Yet there's still the question of whether we shouldn't apply this
restriction in a broader fashion.

Jan


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To: "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
From: Jan Beulich 
Subject: [PATCH RFC] x86/mm: split unmapping and marking-as-I/O in
 arch_init_memory()
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The unmapping part also wants to cover UNUSABLE regions, and it will now
be necessary for space outside the low 16Mb (wherever Xen is placed).

While there, limit the scopes of involved variables.

Fixes: e4dd91ea85a3 ("x86: Ensure RAM holes really are not mapped in Xen's ongoing 1:1 physmap")
Fixes: 7cd7f2f5e116 ("x86/boot: Remove the preconstructed low 16M superpage mappings")
Signed-off-by: Jan Beulich 
---
Originally I had the unmap cover the entire range up to 4Gb, which made
this ACPI mapping issue more pronounced: Mappings done by
acpi_dmar_init(), erst_init(), and acpi_hest_init() may wrongly be
undone this way. Having limited things to the initial mapping range, the
risk of an overlap with some area which needs to remain mapped is lower,
but it's not gone.

As the excess mappings could, at least in principle, also cause other
issues (like mapping a range WB which must strictly be non-cachable), I
wonder whether we can actually get away with those excess mappings,
despite properly tearing them down in arch_init_memory() (directmap) and
__start_xen() (Xen image space). Options would appear to be to move
_end[] to a 2Mb aligned boundary (or at least extend the PT_LOAD segment
to end at the next 2Mb boundary), or to use 4k mappings for the tail
part of .bss. That would then also eliminate the remaining concern here.

Extending the PT_LOAD segment (in mkelf32) would apparently allow to do
away with the hackery introduced by 773ded42218d ("Move cpu0_stack out
of Xen text section and into BSS"), to "work around" a supposed linker
bug (which really was a bug in the linker script imo). The extra command
line argument then wouldn't be needed anymore.

--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -275,8 +275,6 @@ static void __init assign_io_page(struct
 
 void __init arch_init_memory(void)
 {
-    unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn;
-
     /*
      * Basic guest-accessible flags:
      *   PRESENT, R/W, USER, A/D, AVAIL[0,1,2], AVAIL_HIGH, NX (if available).
@@ -292,12 +290,55 @@ void __init arch_init_memory(void)
      * case the low 1MB.
      */
     BUG_ON(pvh_boot && trampoline_phys != 0x1000);
-    for ( i = 0; i < 0x100; i++ )
+    for ( unsigned int i = 0; i < MB(1) >> PAGE_SHIFT; i++ )
         assign_io_page(mfn_to_page(_mfn(i)));
 
-    /* Any areas not specified as RAM by the e820 map are considered I/O. */
-    for ( i = 0, pfn = 0; pfn < max_page; i++ )
+    /*
+     * Any areas not specified as RAM by the e820 map want to have no mappings.
+     * We may have established some by mapping more than necessary in head.S,
+     * due to the use of super-pages there.
+     */
+    for ( unsigned long i = 0, pfn = 0,
+                        rlimit_pfn = PFN_DOWN(PAGE_ALIGN_2M(__pa(_end)));
+          pfn < rlimit_pfn; i++ )
     {
+        unsigned long rstart_pfn, rend_pfn, start_pfn;
+
+        while ( i < e820.nr_map &&
+                e820.map[i].type != E820_RAM )
+            i++;
+
+        if ( i >= e820.nr_map )
+        {
+            /* No more RAM regions: Unmap right to upper boundary. */
+            rstart_pfn = rend_pfn = rlimit_pfn;
+        }
+        else
+        {
+            /* Unmap just up as far as next RAM region. */
+            rstart_pfn = min(rlimit_pfn, PFN_UP(e820.map[i].addr));
+            rend_pfn   = max(rstart_pfn,
+                             PFN_DOWN(e820.map[i].addr + e820.map[i].size));
+        }
+
+        /* NB: _start is already 2Mb-aligned. */
+        start_pfn = max(pfn, PFN_DOWN(__pa(_start)));
+        if ( start_pfn < rstart_pfn )
+            destroy_xen_mappings((unsigned long)mfn_to_virt(start_pfn),
+                                 (unsigned long)mfn_to_virt(rstart_pfn));
+
+        /* Skip the RAM region. */
+        pfn = rend_pfn;
+    }
+
+    /*
+     * Any areas not specified as RAM or UNUSABLE by the e820 map are
+     * considered I/O.
+     */
+    for ( unsigned long i = 0, pfn = 0; pfn < max_page; i++ )
+    {
+        unsigned long rstart_pfn, rend_pfn;
+
         while ( (i < e820.nr_map) &&
                 (e820.map[i].type != E820_RAM) &&
                 (e820.map[i].type != E820_UNUSABLE) )
@@ -317,17 +358,6 @@ void __init arch_init_memory(void)
                                PFN_DOWN(e820.map[i].addr + e820.map[i].size));
         }
 
-        /*
-         * Make sure any Xen mappings of RAM holes above 1MB are blown away.
-         * In particular this ensures that RAM holes are respected even in
-         * the statically-initialised 1-16MB mapping area.
-         */
-        iostart_pfn = max_t(unsigned long, pfn, 1UL << (20 - PAGE_SHIFT));
-        ioend_pfn = min(rstart_pfn, 16UL << (20 - PAGE_SHIFT));
-        if ( iostart_pfn < ioend_pfn )
-            destroy_xen_mappings((unsigned long)mfn_to_virt(iostart_pfn),
-                                 (unsigned long)mfn_to_virt(ioend_pfn));
-
         /* Mark as I/O up to next RAM region. */
         for ( ; pfn < rstart_pfn; pfn++ )
         {
@@ -365,6 +395,7 @@ void __init arch_init_memory(void)
                     const l3_pgentry_t *l3idle = map_l3t_from_l4e(
                             idle_pg_table[l4_table_offset(split_va)]);
                     l3_pgentry_t *l3tab = map_domain_page(l3mfn);
+                    unsigned int i;
 
                     for ( i = 0; i < l3_table_offset(split_va); ++i )
                         l3tab[i] = l3idle[i];


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Subject: Re: [PATCH RFC] x86/mm: split unmapping and marking-as-I/O in
 arch_init_memory()
From: Jan Beulich 
To: "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
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On 07.08.2025 11:37, Jan Beulich wrote:
> The unmapping part also wants to cover UNUSABLE regions, and it will now
> be necessary for space outside the low 16Mb (wherever Xen is placed).
> 
> While there, limit the scopes of involved variables.
> 
> Fixes: e4dd91ea85a3 ("x86: Ensure RAM holes really are not mapped in Xen's ongoing 1:1 physmap")
> Fixes: 7cd7f2f5e116 ("x86/boot: Remove the preconstructed low 16M superpage mappings")
> Signed-off-by: Jan Beulich 
> ---
> Originally I had the unmap cover the entire range up to 4Gb, which made
> this ACPI mapping issue more pronounced: Mappings done by
> acpi_dmar_init(), erst_init(), and acpi_hest_init() may wrongly be
> undone this way. Having limited things to the initial mapping range, the
> risk of an overlap with some area which needs to remain mapped is lower,
> but it's not gone.
> 
> As the excess mappings could, at least in principle, also cause other
> issues (like mapping a range WB which must strictly be non-cachable), I
> wonder whether we can actually get away with those excess mappings,
> despite properly tearing them down in arch_init_memory() (directmap) and
> __start_xen() (Xen image space). Options would appear to be to move
> _end[] to a 2Mb aligned boundary (or at least extend the PT_LOAD segment
> to end at the next 2Mb boundary), or to use 4k mappings for the tail
> part of .bss. That would then also eliminate the remaining concern here.
> 
> Extending the PT_LOAD segment (in mkelf32) would apparently allow to do
> away with the hackery introduced by 773ded42218d ("Move cpu0_stack out
> of Xen text section and into BSS"), to "work around" a supposed linker
> bug (which really was a bug in the linker script imo). The extra command
> line argument then wouldn't be needed anymore.

Thinking about it, this would then also simplify ...

> --- a/xen/arch/x86/mm.c
> +++ b/xen/arch/x86/mm.c
> @@ -275,8 +275,6 @@ static void __init assign_io_page(struct
>  
>  void __init arch_init_memory(void)
>  {
> -    unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn;
> -
>      /*
>       * Basic guest-accessible flags:
>       *   PRESENT, R/W, USER, A/D, AVAIL[0,1,2], AVAIL_HIGH, NX (if available).
> @@ -292,12 +290,55 @@ void __init arch_init_memory(void)
>       * case the low 1MB.
>       */
>      BUG_ON(pvh_boot && trampoline_phys != 0x1000);
> -    for ( i = 0; i < 0x100; i++ )
> +    for ( unsigned int i = 0; i < MB(1) >> PAGE_SHIFT; i++ )
>          assign_io_page(mfn_to_page(_mfn(i)));
>  
> -    /* Any areas not specified as RAM by the e820 map are considered I/O. */
> -    for ( i = 0, pfn = 0; pfn < max_page; i++ )
> +    /*
> +     * Any areas not specified as RAM by the e820 map want to have no mappings.
> +     * We may have established some by mapping more than necessary in head.S,
> +     * due to the use of super-pages there.
> +     */
> +    for ( unsigned long i = 0, pfn = 0,
> +                        rlimit_pfn = PFN_DOWN(PAGE_ALIGN_2M(__pa(_end)));
> +          pfn < rlimit_pfn; i++ )
>      {
> +        unsigned long rstart_pfn, rend_pfn, start_pfn;
> +
> +        while ( i < e820.nr_map &&
> +                e820.map[i].type != E820_RAM )
> +            i++;
> +
> +        if ( i >= e820.nr_map )
> +        {
> +            /* No more RAM regions: Unmap right to upper boundary. */
> +            rstart_pfn = rend_pfn = rlimit_pfn;
> +        }
> +        else
> +        {
> +            /* Unmap just up as far as next RAM region. */
> +            rstart_pfn = min(rlimit_pfn, PFN_UP(e820.map[i].addr));
> +            rend_pfn   = max(rstart_pfn,
> +                             PFN_DOWN(e820.map[i].addr + e820.map[i].size));
> +        }
> +
> +        /* NB: _start is already 2Mb-aligned. */
> +        start_pfn = max(pfn, PFN_DOWN(__pa(_start)));
> +        if ( start_pfn < rstart_pfn )
> +            destroy_xen_mappings((unsigned long)mfn_to_virt(start_pfn),
> +                                 (unsigned long)mfn_to_virt(rstart_pfn));
> +
> +        /* Skip the RAM region. */
> +        pfn = rend_pfn;
> +    }

... this: If we're loaded in an area that's a multiple of 2Mb in size (and
2Mb aligned), we wouldn't need to walk the E820 map anymore. The boot loader
(or whatever else) must have placed the entire image inside a RAM region.
Hence we could simply unmap [PAGE_ALIGN_4K(_end), PAGE_ALIGN_2M(_end)),
outside of any loop.

Jan


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Date: Thu, 7 Aug 2025 12:01:32 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Andrew Cooper 
Cc: xen-devel@lists.xenproject.org,
	Stefano Stabellini ,
	Roger Pau =?utf-8?B?TW9ubsOp?= 
Subject: Re: [PATCH test-artifacts] Add debian rootfs artifact
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Date: Thu, 7 Aug 2025 12:01:32 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Andrew Cooper 
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	Stefano Stabellini ,
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Subject: Re: [PATCH test-artifacts] Add debian rootfs artifact

On Thu, Aug 07, 2025 at 08:55:56AM +0100, Andrew Cooper wrote:
> On 07/08/2025 1:03 am, Marek Marczykowski-G=C3=B3recki wrote:
> > Will be used as dom0/domU in some tests.
> >
> > Install OpenRC and setup it to start /etc/local.d/ scripts so tests
> > don't need different cases for Alpine and Debian.
>=20
> (Yeah, I got this via CC.)
>=20
> I was just thinking that we needed some non-Alpine testing too, but for
> a different reason.
>=20
> We have systemd configuration in Xen, and changes to it, yet no CI of
> what is the most common init system in Linux these days.
>=20
> What would need to be different in tests to avoid OpenRC?=C2=A0 If it's o=
nly
> the script to start the test running, can't we just declare a name, and
> arrange for both init systems to run it?

In this particular test, probably just that. And convincing
systemd/journald to dump logs to the console. But some other tests (if
we'd want to reuse this artifact) wait for "Welcome to Alpine Linux"
text, or start other services via /etc/init.d (mostly xencommons...).

And also - installing openrc takes 3MB, installing (just) systemd takes
30MB. And I haven't tried yet if any auxiliary package isn't needed
too...
But I can see what it takes to make the test use systemd.

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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From: Grygorii Strashko 
To: "xen-devel@lists.xenproject.org" 
CC: Grygorii Strashko , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini , Bertrand
 Marquis , Volodymyr Babchuk
	, Denis Mukhin , Jason Andryuk
	, Julien Grall 
Subject: [PATCH v3] xen/dom0less: arm: fix hwdom 1:1 low memory allocation
Thread-Topic: [PATCH v3] xen/dom0less: arm: fix hwdom 1:1 low memory
 allocation
Thread-Index: AQHcB4KDC2FxELT99UexPqqnlkcdng==
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From: Grygorii Strashko 

Call stack for dom0less hwdom case (1:1) memory:
create_domUs
|-construct_domU
  |-construct_hwdom()
    |-allocate_memory_11()

And allocate_memory_11() uses "dom0_mem" as:
min_low_order =3D
  get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128)));

In case of dom0less boot the "dom0_mem" is not used and defaulted to 0,
which causes min_low_order to get high value > order and so no allocations
happens from low memory.

Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" which has
correct memory size in both cases: regular dom0 boot and dom0less boot.

Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction")
Signed-off-by: Grygorii Strashko 
Reviewed-by: Denis Mukhin 
Reviewed-by: Jason Andryuk 
Acked-by: Julien Grall 
---
Changes in v3:
- updated "dom0_mem" doc in xen-command-line.pandoc
- add tag from Julien Grall

Changes in v2:
- changed 'fixes' tag
- fixed comment for allocate_memory_11()
- added reviewer's tags

 docs/misc/xen-command-line.pandoc | 3 ++-
 xen/arch/arm/domain_build.c       | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line=
.pandoc
index 6865a61220ca..1f33b7a11eba 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -1035,7 +1035,8 @@ For example, with `dom0_max_vcpus=3D4-8`:
 > `=3D `
=20
 Set the amount of memory for the initial domain (dom0). It must be
-greater than zero. This parameter is required.
+greater than zero. This parameter is required (and only used) when the ini=
tial
+domain is not described in the Device-Tree.
=20
 ### dom0_mem (x86)
 > `=3D List of ( min: | max: |  )`
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 463ae4474d30..a9e4153e3cf9 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -249,7 +249,7 @@ fail:
  *
  * We first allocate the largest allocation we can as low as we
  * can. This then becomes the first bank. This bank must be at least
- * 128MB (or dom0_mem if that is smaller).
+ * 128MB (or memory size requested for domain if that is smaller).
  *
  * Then we start allocating more memory, trying to allocate the
  * largest possible size and trying smaller sizes until we
@@ -278,7 +278,7 @@ static void __init allocate_memory_11(struct domain *d,
                                       struct kernel_info *kinfo)
 {
     const unsigned int min_low_order =3D
-        get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128)));
+        get_order_from_bytes(min_t(paddr_t, kinfo->unassigned_mem, MB(128)=
));
     const unsigned int min_order =3D get_order_from_bytes(MB(4));
     struct membanks *mem =3D kernel_info_get_mem(kinfo);
     struct page_info *pg;
--=20
2.34.1


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Date: Thu, 7 Aug 2025 12:11:48 +0200
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Subject: Re: [PATCH v3 03/20] xen/riscv: introduce VMID allocation and
 manegement
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 
 
 
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On 06.08.2025 18:24, Oleksii Kurochko wrote:
> On 8/6/25 2:05 PM, Jan Beulich wrote:
>> On 06.08.2025 13:33, Oleksii Kurochko wrote:
>>> On 8/4/25 5:19 PM, Jan Beulich wrote:
>>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>>> +{
>>>>> +    unsigned long vmid_bits;
>>>> Why "long" (also for the function return type)?
>>> Because csr_read() returns unsigned long as HGATP register has
>>> 'unsigned long' length.
>> Oh, right, I should have commented on the function return type only.
>> Yet then I also can't resist stating that this kind of use of a variable,
>> which initially is assigned a value that doesn't really fit its name, is
>> easily misleading towards giving such comments.
>>
>>> But it could be done in this way:
>>>       csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>>       vmid_bits =  MASK_EXTR(csr_read(CSR_HGATP), HGATP_VMID_MASK);
>>>       vmid_bits = ffs_g(vmid_bits);
>>>       csr_write(CSR_HGATP, old);
>>> And then use uint16_t for vmid_bits and use uin16_t as a return type.
>> Please check ./CODING_STYLE again as to the use of fixed-width types.
> 
> I meant unsigned short, uint16_t was just short to write. I'll try to be
> more specific.

I'd also recommend against unsigned short when there are no space concerns.
unsigned int is what wants using in the general case.

>>>>> +    unsigned long old;
>>>>> +
>>>>> +    /* Figure-out number of VMID bits in HW */
>>>>> +    old = csr_read(CSR_HGATP);
>>>>> +
>>>>> +    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>>>> +    vmid_bits = csr_read(CSR_HGATP);
>>>>> +    vmid_bits =  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);
>>>> Nit: Stray blank.
>>>>
>>>>> +    vmid_bits = flsl(vmid_bits);
>>>>> +    csr_write(CSR_HGATP, old);
>>>>> +
>>>>> +    /*
>>>>> +     * We polluted local TLB so flush all guest TLB as
>>>>> +     * a speculative access can happen at any time.
>>>>> +     */
>>>>> +    local_hfence_gvma_all();
>>>> There's no guest running. If you wrote hgat.MODE as zero, as per my
>>>> understanding now new TLB entries could even purely theoretically appear.
>>> It could be an issue (or, at least, it is recommended) when hgatp.MODE is
>>> changed:
>>>    If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0
>>>    (and rs2 set to either x0 or the VMID) must be executed to order subsequent
>>>    guest translations with the MODE change—even if the old MODE or new MODE
>>>    is Bare.
>>> On other hand it is guaranteed that, at least, on Reset (and so I assume
>>> for power on) that:
>>>    If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE
>>>    fields are reset to 0.
>>>
>>> So it seems like if no guest is ran then there is no need even to write
>>> hgatp.MODE as zero, but it might be sense to do that explicitly just to
>>> be sure.
>>>
>>> I thought it was possible to have a running guest and perform a CPU hotplug.
>> But that guest will run on another hart.
>>
>>> In that case, I expect that during the hotplug,|vmidlen_detect()| will be
>>> called and return the|vmid_bits| value, which is used as the active VMID.
>>> At that moment, the local TLB could be speculatively polluted, I think.
>>> Likely, it makes sense to call vmidlen_detect() only once for each hart
>>> during initial bringup.
>> That may bring you more problems than it solves. You'd need to stash away
>> the value originally read somewhere. And that somewhere isn't per-CPU data.
>>
>>>> In fact, with no guest running (yet) I'm having a hard time seeing why
>>>> you shouldn't be able to simply write the register with just
>>>> HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable
>>>> whether "old" needs restoring; writing plain zero afterwards ought to
>>>> suffice. You're in charcge of the register, after all.
>>> It make sense (but I don't know if it is a possible case) to be sure that
>>> HGATP.MODE remains the same, so there is no need to have TLB flush. If
>>> HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned
>>> above.
>>>
>>> If we agreed to keep local_hfence_gvma_all() then I think it isn't really
>>> any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.
>>>
>>> Generally if 'old' is guaranteed to be zero (and, probably, it makes sense
>>> to check that in vmidlen_detect() and panic if it isn't zero) and if
>>> vmidlen_detect() function will be called before any guest domain(s) will
>>> be ran then I could agree that we don't need local_hfence_gvma_all() here.
>>>
>>> As an option we can do local_hfence_gvma_all() only if 'old' value wasn't
>>> set to zero.
>>>
>>> Does it make sense?
>> Well - I'd like the pre-conditions to be understood better. For example, can
>> a hart really speculate into guest mode, when the hart is only in the
>> process of being brought up?
> 
> I couldn't explicit words that a hart can't speculate into guest mode
> either on bring up or during its work.
> 
> But there are some moments in the spec which tells:
>    Implementations with virtual memory are permitted to perform address
>    translations speculatively and earlier than required by an explicit
>    memory access, and are permitted to cache them in address translation
>    cache structures—including possibly caching the identity mappings from
>    effective address to physical address used in Bare translation modes and
>    M-mode.
> And here:
>    Implementations may also execute the address-translation algorithm
>    speculatively at any time, for any virtual address, as long as satp is
>    active (as defined in Section 10.1.11). Such speculative executions have
>    the effect of pre-populating the address-translation cache.

That's satp though, not hgatp.

> Where it is explicitly mentioned that speculation can happen in *any time*.
> And at the same time:
>    Speculative executions of the address-translation algorithm behave as
>    non-speculative executions of the algorithm do, except that they must
>    not set the dirty bit for a PTE, they must not trigger an exception,
>    and they must not create address-translation cache entries if those
>    entries would have been invalidated by any SFENCE.VMA instruction
>    executed by the hart since the speculative execution of the algorithm began.
> What I read as if TLB was empty before it will stay empty.
> 
> Also, despite of the fact here it is mentioned that when V=0 two-stage address
> translation is inactivated:
>    The current virtualization mode, denoted V, indicates whether the hart is
>    currently executing in a guest. When V=1, the hart is either in virtual
>    S-mode (VS-mode), or in virtual U-mode (VU-mode) atop a guest OS running
>    in VS-mode. When V=0, the hart is either in M-mode, in HS-mode, or in
>    U-mode atop an OS running in HS-mode. The virtualization mode also
>    indicates whether two-stage address translation is active (V=1) or
>    inactive (V=0).
> But on the same side, writing to hgatp register activates it:
>    The hgatp register is considered active for the purposes of
>    the address-translation algorithm unless the effective privilege mode
>    is U and hstatus.HU=0.
> And if so + considering that speculation could happen at any time, and
> we are in HS-mode, not it U mode then I would say that it could really
> speculate into guest mode.

Hmm, that leaves some things to be desired. What I'm particularly puzzled
by is that there's nothing said either way towards speculation through SRET.
That's the important aspect here aiui, because without that the hart can't
speculate into guest mode.

But yes, in the absence of any clear indication to the contrary, I think
you want to keep the local_hfence_gvma_all() (with a suitable comment).

>>>>> +    data->max_vmid = BIT(vmid_len, U) - 1;
>>>>> +    data->disabled = !opt_vmid_enabled || (vmid_len <= 1);
>>>> Actually, what exactly does it mean that "VMIDs are disabled"? There's
>>>> no enable bit that I could find anywhere. Isn't it rather that in this
>>>> case you need to arrange to flush always on VM entry (or always after a
>>>> P2M change, depending how the TLB is split between guest and host use)?
>>> "VMIDs are disabled" here means that TLB flush will happen each time p2m
>>> is changed.
>> That's better described as "VMIDs aren't used" then?
> 
> It sounds a little bit just like an opposite to "disabled" (i.e. means
> basically the same), but I am okay to use "used" instead.

If you want to stick to using "disabled", then how about "VMID use is
disabled"? (You probably meanwhile understood that what I'm after is it
becoming clear that this is a software decision, not something you can
enforce in hardware.)

Jan


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Subject: Re: [PATCH] x86/domctl: Reject XEN_DOMCTL_hypercall_init against
 oneself
To: Jan Beulich 
Cc: Frediano Ziglio ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
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On 07/08/2025 10:30 am, Jan Beulich wrote:
> On 06.08.2025 18:55, Andrew Cooper wrote:
>> --- a/xen/arch/x86/domctl.c
>> +++ b/xen/arch/x86/domctl.c
>> @@ -372,6 +372,14 @@ long arch_do_domctl(
>>          struct page_info *page;
>>          void *hypercall_page;
>>  
>> +        /*
>> +         * Kernels should use the MSR method to get a hypercall page.  The
>> +         * toolstack should not be using the DOMCTL on itself.
>> +         */
>> +        ret = -EINVAL;
>> +        if ( d == currd )
>> +            break;
> Isn't what the comment says more generally true? To act on themselves, most
> domctl-s are inappropriate to use, I think. There are a few exceptions, where
> alternatives simply don't exist (and where, if a kernel wanted to use a domctl
> [or sysctl], it would need to go through hoops to deal with the interface
> versioning). Yet there's still the question of whether we shouldn't apply this
> restriction in a broader fashion.

I'd go so far as to say that domctls ought to be restricted against
oneself, but it's not quite that easy.  The majority of them already are
restricted because of domain/vcpu_pause(), but this is all ad-hoc.

In principle, the control domain ought to be able to issue some of the
getter's on itself, but even that's inconsistent.  get_dominfo is
permitted, but paging ops are not.

This is still a TBD for the stable tools interfaces.  One option I am
considering was to split the opcode space by whether it was logically a
getter or setter, but I expect this does not work nicely if we also want
to retain backwards compatibility.

~Andrew


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Subject: Re: [PATCH] x86/domctl: Reject XEN_DOMCTL_hypercall_init against
 oneself
To: Andrew Cooper 
Cc: Frediano Ziglio ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Ross Lagerwall ,
 Xen-devel 
References: <20250806165543.169140-1-andrew.cooper3@citrix.com>
 
 <848c5da3-5aa8-4f0e-a9ed-cd41a5fac0b0@citrix.com>
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On 07.08.2025 12:17, Andrew Cooper wrote:
> On 07/08/2025 10:30 am, Jan Beulich wrote:
>> On 06.08.2025 18:55, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/domctl.c
>>> +++ b/xen/arch/x86/domctl.c
>>> @@ -372,6 +372,14 @@ long arch_do_domctl(
>>>          struct page_info *page;
>>>          void *hypercall_page;
>>>  
>>> +        /*
>>> +         * Kernels should use the MSR method to get a hypercall page.  The
>>> +         * toolstack should not be using the DOMCTL on itself.
>>> +         */
>>> +        ret = -EINVAL;
>>> +        if ( d == currd )
>>> +            break;
>> Isn't what the comment says more generally true? To act on themselves, most
>> domctl-s are inappropriate to use, I think. There are a few exceptions, where
>> alternatives simply don't exist (and where, if a kernel wanted to use a domctl
>> [or sysctl], it would need to go through hoops to deal with the interface
>> versioning). Yet there's still the question of whether we shouldn't apply this
>> restriction in a broader fashion.
> 
> I'd go so far as to say that domctls ought to be restricted against
> oneself, but it's not quite that easy.  The majority of them already are
> restricted because of domain/vcpu_pause(), but this is all ad-hoc.
> 
> In principle, the control domain ought to be able to issue some of the
> getter's on itself, but even that's inconsistent.  get_dominfo is
> permitted, but paging ops are not.

Hmm, right. And as said, there are a few which simply can't be done a non-
domctl way. For the patch here:
Reviewed-by: Jan Beulich 

> This is still a TBD for the stable tools interfaces.  One option I am
> considering was to split the opcode space by whether it was logically a
> getter or setter, but I expect this does not work nicely if we also want
> to retain backwards compatibility.

I didn't expect we'd strive for (binary) backwards compatibility there.
Source compatibility (i.e. merely requiring a re-compile) may be a goal,
yet even there I wouldn't be certain.

Jan


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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 4/4] x86: Drop the vm86 segments selectors from struct cpu_user_regs
Date: Thu,  7 Aug 2025 12:16:57 +0100
Message-Id: <20250807111657.201849-5-andrew.cooper3@citrix.com>
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The data segment registers are part of the on-stack IRET frame when
interrupting Virtual 8086 mode, but this ceased being relevant for Xen in
commit 5d1181a5ea5e ("xen: Remove x86_32 build target.") in 2012.

With all other cleanup in place, delete the fields so we can introduce FRED
support which uses this space for different data.

Everywhere which used the es field as an offset in cpu_user_regs needs
adjusting.  However, they'll change again for FRED, so no cleanup is performed
at this juncture.

This also undoes the OoB Read workaround in show_registers(), which can now
switch back to being simple structure copy.

No functional change, but a lot of rearranging of stack and struct layout
under the hood.

Signed-off-by: Andrew Cooper 
Reviewed-by: Jan Beulich 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/cpu/common.c                | 2 +-
 xen/arch/x86/include/asm/cpu-user-regs.h | 5 -----
 xen/arch/x86/include/asm/current.h       | 8 ++++----
 xen/arch/x86/include/asm/hvm/hvm.h       | 4 ----
 xen/arch/x86/include/asm/regs.h          | 3 +--
 xen/arch/x86/traps.c                     | 2 +-
 xen/arch/x86/x86_64/asm-offsets.c        | 2 +-
 xen/arch/x86/x86_64/traps.c              | 8 +-------
 8 files changed, 9 insertions(+), 25 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index e063fe790a97..97bdda1d4a25 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -959,7 +959,7 @@ void load_system_tables(void)
 	 * Defer checks until exception support is sufficiently set up.
 	 */
 	BUILD_BUG_ON((sizeof(struct cpu_info) -
-		      offsetof(struct cpu_info, guest_cpu_user_regs.es)) & 0xf);
+		      sizeof(struct cpu_user_regs)) & 0xf);
 	BUG_ON(system_state != SYS_STATE_early_boot && (stack_bottom & 0xf));
 }
 
diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/include/asm/cpu-user-regs.h
index 0e78e38ed00d..d700a3ef3447 100644
--- a/xen/arch/x86/include/asm/cpu-user-regs.h
+++ b/xen/arch/x86/include/asm/cpu-user-regs.h
@@ -53,11 +53,6 @@ struct cpu_user_regs
      * For IDT delivery, tss->rsp0 points to this boundary as embedded within
      * struct cpu_info.  It must be 16-byte aligned.
      */
-
-    uint16_t es, _pad3[3];
-    uint16_t ds, _pad4[3];
-    uint16_t fs, _pad5[3];
-    uint16_t gs, _pad6[3];
 };
 
 #endif /* X86_CPU_USER_REGS_H */
diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index 243d17ef79fd..a7c9473428b2 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -106,12 +106,12 @@ static inline struct cpu_info *get_cpu_info(void)
 #define get_per_cpu_offset()  (get_cpu_info()->per_cpu_offset)
 
 /*
- * Get the bottom-of-stack, as stored in the per-CPU TSS. This actually points
- * into the middle of cpu_info.guest_cpu_user_regs, at the section that
- * precisely corresponds to a CPU trap frame.
+ * Get the bottom-of-stack, as stored in the per-CPU TSS. This points at the
+ * end of cpu_info.guest_cpu_user_regs, at the section that precisely
+ * corresponds to a CPU trap frame.
  */
 #define get_stack_bottom()                      \
-    ((unsigned long)&get_cpu_info()->guest_cpu_user_regs.es)
+    ((unsigned long)(&get_cpu_info()->guest_cpu_user_regs + 1))
 
 /*
  * Get the reasonable stack bounds for stack traces and stack dumps.  Stack
diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h
index bf8bc2e100bd..18e40910ff71 100644
--- a/xen/arch/x86/include/asm/hvm/hvm.h
+++ b/xen/arch/x86/include/asm/hvm/hvm.h
@@ -624,10 +624,6 @@ static inline void hvm_sanitize_regs_fields(struct cpu_user_regs *regs,
     regs->saved_upcall_mask = 0xbf;
     regs->cs = 0xbeef;
     regs->ss = 0xbeef;
-    regs->ds = 0xbeef;
-    regs->es = 0xbeef;
-    regs->fs = 0xbeef;
-    regs->gs = 0xbeef;
 #endif
 }
 
diff --git a/xen/arch/x86/include/asm/regs.h b/xen/arch/x86/include/asm/regs.h
index ce9b028276a1..72595110e2d5 100644
--- a/xen/arch/x86/include/asm/regs.h
+++ b/xen/arch/x86/include/asm/regs.h
@@ -23,8 +23,7 @@
     (!is_pv_32bit_vcpu(v) ? ((tb)->eip == 0) : (((tb)->cs & ~3) == 0))
 
 /* Number of bytes of on-stack execution state to be context-switched. */
-/* NB. Segment registers and bases are not saved/restored on x86/64 stack. */
-#define CTXT_SWITCH_STACK_BYTES (offsetof(struct cpu_user_regs, es))
+#define CTXT_SWITCH_STACK_BYTES sizeof(struct cpu_user_regs)
 
 #define guest_mode(r)                                                         \
 ({                                                                            \
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 34dc077cad34..238d923dd188 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -387,7 +387,7 @@ unsigned long get_stack_trace_bottom(unsigned long sp)
     {
     case 1 ... 4:
         return ROUNDUP(sp, PAGE_SIZE) -
-            offsetof(struct cpu_user_regs, es) - sizeof(unsigned long);
+            sizeof(struct cpu_user_regs) - sizeof(unsigned long);
 
     case 6 ... 7:
         return ROUNDUP(sp, STACK_SIZE) -
diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-offsets.c
index 630bdc39451d..2258b4ce1b95 100644
--- a/xen/arch/x86/x86_64/asm-offsets.c
+++ b/xen/arch/x86/x86_64/asm-offsets.c
@@ -52,7 +52,7 @@ void __dummy__(void)
     OFFSET(UREGS_eflags, struct cpu_user_regs, rflags);
     OFFSET(UREGS_rsp, struct cpu_user_regs, rsp);
     OFFSET(UREGS_ss, struct cpu_user_regs, ss);
-    OFFSET(UREGS_kernel_sizeof, struct cpu_user_regs, es);
+    DEFINE(UREGS_kernel_sizeof, sizeof(struct cpu_user_regs));
     BLANK();
 
     /*
diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c
index 29ac5a14ca3f..34adf55e48df 100644
--- a/xen/arch/x86/x86_64/traps.c
+++ b/xen/arch/x86/x86_64/traps.c
@@ -135,17 +135,11 @@ static void _show_registers(
 
 void show_registers(const struct cpu_user_regs *regs)
 {
-    struct cpu_user_regs fault_regs;
+    struct cpu_user_regs fault_regs = *regs;
     struct extra_state fault_state;
     enum context context;
     struct vcpu *v = system_state >= SYS_STATE_smp_boot ? current : NULL;
 
-    /*
-     * Don't read beyond the end of the hardware frame.  It is out of bounds
-     * for WARN()/etc.
-     */
-    memcpy(&fault_regs, regs, offsetof(struct cpu_user_regs, es));
-
     if ( guest_mode(regs) && is_hvm_vcpu(v) )
     {
         get_hvm_registers(v, &fault_regs, &fault_state);
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper 
Subject: [PATCH v2 0/4] x86: Drop the vm86 segments selectors from struct cpu_user_regs
Date: Thu,  7 Aug 2025 12:16:53 +0100
Message-Id: <20250807111657.201849-1-andrew.cooper3@citrix.com>
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This is the next chunk of work in order to support FRED.  Half of v1 is
already committed.

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1972002392

Andrew Cooper (4):
  x86/domctl: Stop using XLAT_cpu_user_regs()
  x86/pv: Store the data segment selectors outside of cpu_user_regs
  x86/public: Split the struct cpu_user_regs type
  x86: Drop the vm86 segments selectors from struct cpu_user_regs

 xen/arch/x86/cpu/common.c                |  2 +-
 xen/arch/x86/domain.c                    | 92 ++++++++++++++++--------
 xen/arch/x86/domctl.c                    | 38 +++++++++-
 xen/arch/x86/include/asm/cpu-user-regs.h | 58 +++++++++++++++
 xen/arch/x86/include/asm/current.h       | 11 +--
 xen/arch/x86/include/asm/domain.h        |  2 +
 xen/arch/x86/include/asm/hvm/hvm.h       |  4 --
 xen/arch/x86/include/asm/regs.h          | 11 +--
 xen/arch/x86/pv/dom0_build.c             |  6 +-
 xen/arch/x86/traps.c                     |  2 +-
 xen/arch/x86/x86_64/asm-offsets.c        |  2 +-
 xen/arch/x86/x86_64/traps.c              | 16 ++---
 xen/arch/x86/x86_emulate/private.h       |  1 +
 xen/include/public/arch-x86/xen-x86_32.h |  9 +++
 xen/include/public/arch-x86/xen-x86_64.h |  9 +++
 xen/include/public/arch-x86/xen.h        | 11 +++
 xen/include/xlat.lst                     |  2 -
 17 files changed, 208 insertions(+), 68 deletions(-)
 create mode 100644 xen/arch/x86/include/asm/cpu-user-regs.h

-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Jan Beulich 
Subject: [PATCH v2 3/4] x86/public: Split the struct cpu_user_regs type
Date: Thu,  7 Aug 2025 12:16:56 +0100
Message-Id: <20250807111657.201849-4-andrew.cooper3@citrix.com>
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In order to support FRED, we're going to have to remove the {ds..gs} fields
from struct cpu_user_regs, meaning that it is going to have to become a
different type to the structure embedded in vcpu_guest_context_u.

struct cpu_user_regs is a name used in common Xen code (i.e. needs to stay
using this name), so renaming the public struct to be guest_user_regs in Xen's
view only.

Introduce a brand hew cpu-user-regs.h, currently containing a duplicate
structure.

Notably, this removes the need to include pubic/xen.h in ~every translation
unit in Xen (via current.h), and highlights one case where the emulator was
picking up cpu_user_regs transitively.

Include comments describing how hardware interacts with this structure under
IDT delivery, as it's quite magic to start with.  FRED is going make things
more complicated.

No functional change.

Signed-off-by: Andrew Cooper 
Reviewed-by: Jan Beulich 
Acked-by: Roger Pau Monné 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Remove the macros from cpu-user-regs.h and write the struct longhand
 * Exclude the guest handles in Xen context
---
 xen/arch/x86/include/asm/cpu-user-regs.h | 63 ++++++++++++++++++++++++
 xen/arch/x86/include/asm/current.h       |  3 +-
 xen/arch/x86/x86_emulate/private.h       |  1 +
 xen/include/public/arch-x86/xen-x86_32.h |  9 ++++
 xen/include/public/arch-x86/xen-x86_64.h |  9 ++++
 xen/include/public/arch-x86/xen.h        | 11 +++++
 6 files changed, 95 insertions(+), 1 deletion(-)
 create mode 100644 xen/arch/x86/include/asm/cpu-user-regs.h

diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/include/asm/cpu-user-regs.h
new file mode 100644
index 000000000000..0e78e38ed00d
--- /dev/null
+++ b/xen/arch/x86/include/asm/cpu-user-regs.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef X86_CPU_USER_REGS_H
+#define X86_CPU_USER_REGS_H
+
+#include 
+
+/*
+ * cpu_user_regs represents the interrupted GPR state at the point of an
+ * interrupt, exception or syscall.  The layout is dictated by the hardware
+ * format for the event frame, with software filling in the rest.
+ */
+struct cpu_user_regs
+{
+    union { uint64_t r15;    uint32_t r15d;   uint16_t r15w;  uint8_t r15b; };
+    union { uint64_t r14;    uint32_t r14d;   uint16_t r14w;  uint8_t r14b; };
+    union { uint64_t r13;    uint32_t r13d;   uint16_t r13w;  uint8_t r13b; };
+    union { uint64_t r12;    uint32_t r12d;   uint16_t r12w;  uint8_t r12b; };
+    union { uint64_t rbp;    uint32_t ebp;    uint16_t bp;    uint8_t bpl;  };
+    union { uint64_t rbx;    uint32_t ebx;    uint16_t bx;    struct { uint8_t bl, bh; }; };
+    union { uint64_t r11;    uint32_t r11d;   uint16_t r11w;  uint8_t r11b; };
+    union { uint64_t r10;    uint32_t r10d;   uint16_t r10w;  uint8_t r10b; };
+    union { uint64_t r9;     uint32_t r9d;    uint16_t r9w;   uint8_t r9b;  };
+    union { uint64_t r8;     uint32_t r8d;    uint16_t r8w;   uint8_t r8b;  };
+    union { uint64_t rax;    uint32_t eax;    uint16_t ax;    struct { uint8_t al, ah; }; };
+    union { uint64_t rcx;    uint32_t ecx;    uint16_t cx;    struct { uint8_t cl, ch; }; };
+    union { uint64_t rdx;    uint32_t edx;    uint16_t dx;    struct { uint8_t dl, dh; }; };
+    union { uint64_t rsi;    uint32_t esi;    uint16_t si;    uint8_t sil;  };
+    union { uint64_t rdi;    uint32_t edi;    uint16_t di;    uint8_t dil;  };
+
+    /*
+     * During IDT delivery for exceptions with an error code, hardware pushes
+     * to this point.  Entry_vector is filled in by software.
+     */
+
+    uint32_t error_code;
+    uint32_t entry_vector;
+
+    /*
+     * During IDT delivery for interrupts or exceptions without an error code,
+     * hardware pushes to this point.  Both error_code and entry_vector are
+     * filled in by software.
+     */
+
+    union { uint64_t rip;    uint32_t eip;    uint16_t ip; };
+    uint16_t cs, _pad0[1];
+    uint8_t  saved_upcall_mask; /* PV (v)rflags.IF == !saved_upcall_mask */
+    uint8_t  _pad1[3];
+    union { uint64_t rflags; uint32_t eflags; uint16_t flags; };
+    union { uint64_t rsp;    uint32_t esp;    uint16_t sp;    uint8_t spl; };
+    uint16_t ss, _pad2[3];
+
+    /*
+     * For IDT delivery, tss->rsp0 points to this boundary as embedded within
+     * struct cpu_info.  It must be 16-byte aligned.
+     */
+
+    uint16_t es, _pad3[3];
+    uint16_t ds, _pad4[3];
+    uint16_t fs, _pad5[3];
+    uint16_t gs, _pad6[3];
+};
+
+#endif /* X86_CPU_USER_REGS_H */
diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index bcec328c9875..243d17ef79fd 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -9,7 +9,8 @@
 
 #include 
 #include 
-#include 
+
+#include 
 
 /*
  * Xen's cpu stacks are 8 pages (8-page aligned), arranged as:
diff --git a/xen/arch/x86/x86_emulate/private.h b/xen/arch/x86/x86_emulate/private.h
index 940087987011..24c79c4e8fac 100644
--- a/xen/arch/x86/x86_emulate/private.h
+++ b/xen/arch/x86/x86_emulate/private.h
@@ -14,6 +14,7 @@
 # include 
 # include 
 
+# include 
 # include 
 # include 
 # include 
diff --git a/xen/include/public/arch-x86/xen-x86_32.h b/xen/include/public/arch-x86/xen-x86_32.h
index 9e3bf06b121e..25cc44728838 100644
--- a/xen/include/public/arch-x86/xen-x86_32.h
+++ b/xen/include/public/arch-x86/xen-x86_32.h
@@ -114,6 +114,10 @@
 #define __DECL_REG_LO16(name) uint32_t e ## name
 #endif
 
+#ifdef __XEN__
+#define cpu_user_regs guest_user_regs
+#endif
+
 struct cpu_user_regs {
     __DECL_REG_LO8(b);
     __DECL_REG_LO8(c);
@@ -136,8 +140,13 @@ struct cpu_user_regs {
     uint16_t fs, _pad4;
     uint16_t gs, _pad5;
 };
+
+#ifdef __XEN__
+#undef cpu_user_regs
+#else
 typedef struct cpu_user_regs cpu_user_regs_t;
 DEFINE_XEN_GUEST_HANDLE(cpu_user_regs_t);
+#endif
 
 #undef __DECL_REG_LO8
 #undef __DECL_REG_LO16
diff --git a/xen/include/public/arch-x86/xen-x86_64.h b/xen/include/public/arch-x86/xen-x86_64.h
index 43f6e3d22001..ea6b56aa3bd8 100644
--- a/xen/include/public/arch-x86/xen-x86_64.h
+++ b/xen/include/public/arch-x86/xen-x86_64.h
@@ -159,6 +159,10 @@ struct iret_context {
 #define __DECL_REG_HI(num)    uint64_t r ## num
 #endif
 
+#ifdef __XEN__
+#define cpu_user_regs guest_user_regs
+#endif
+
 struct cpu_user_regs {
     __DECL_REG_HI(15);
     __DECL_REG_HI(14);
@@ -189,8 +193,13 @@ struct cpu_user_regs {
     uint16_t fs, _pad5[3];
     uint16_t gs, _pad6[3];
 };
+
+#ifdef __XEN__
+#undef cpu_user_regs
+#else
 typedef struct cpu_user_regs cpu_user_regs_t;
 DEFINE_XEN_GUEST_HANDLE(cpu_user_regs_t);
+#endif
 
 #undef __DECL_REG
 #undef __DECL_REG_LOHI
diff --git a/xen/include/public/arch-x86/xen.h b/xen/include/public/arch-x86/xen.h
index fc2487986642..b99a691706f8 100644
--- a/xen/include/public/arch-x86/xen.h
+++ b/xen/include/public/arch-x86/xen.h
@@ -173,7 +173,18 @@ struct vcpu_guest_context {
 #define _VGCF_online                   5
 #define VGCF_online                    (1<<_VGCF_online)
     unsigned long flags;                    /* VGCF_* flags                 */
+
+    /*
+     * Outside of Xen, regs type stays named cpu_user_regs for backwards
+     * compatibility.  Inside Xen, the type called cpu_user_regs is different,
+     * and the public API type is renamed to guest_user_regs.
+     */
+#ifdef __XEN__
+    struct guest_user_regs user_regs;       /* User-level CPU registers     */
+#else
     struct cpu_user_regs user_regs;         /* User-level CPU registers     */
+#endif
+
     struct trap_info trap_ctxt[256];        /* Virtual IDT                  */
     unsigned long ldt_base, ldt_ents;       /* LDT (linear address, # ents) */
     unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 1/4] x86/domctl: Stop using XLAT_cpu_user_regs()
Date: Thu,  7 Aug 2025 12:16:54 +0100
Message-Id: <20250807111657.201849-2-andrew.cooper3@citrix.com>
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In order to support FRED, we're going to have to remove the {ds..gs} fields
from struct cpu_user_regs, meaning that it is going to have to become a
different type to the structure embedded in vcpu_guest_context_u.

In both arch_{get,set}_info_guest(), expand the memcpy()/XLAT_cpu_user_regs()
to copy the fields individually.  This will allow us to eventually make them
different types.

This does cause some minor changes in behaviour for the hypercalls.

It is specifically not the case that a toolstack could set_info(); get_info();
and get an identical bit pattern back.  Amongst other things, the
architectural sticky bits in registers are applied during setting.

Previously, XLAT_cpu_user_regs() omitted the _pad fields in the compat case
whereas the non-compat case included them owing to the single memcpy().

Omit the _pad fields in the non-compat case too; for all but the oldest of
CPUs, the segment selectors are zero-extended by hardware when pushed onto the
stack, so non-zero values here get lost naturally.  Furthermore, FRED reuses
the space above cs and ss for extra state, and a PV guest for now at least
must not be able to write the control state.

Omit the error_code and entry_vector fields too.  They're already identified
as private fields in the public API, and are stale outside of Xen's
interrupt/exception/syscall handler.  They're also a very minor information
leak of which event caused the last deschedule of a vCPU.

Finally, omit saved_upcall_mask.  Xen doesn't consume this, and only produces
it in {compat_,}create_bounce_frame(), based on the vcpu_info page and
settings about the event being injected.  Similar to error_code/entry_vector,
it is stale outside of the guest's event handler.

No change that toolstacks or guests are expected to notice or care about.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Zero memory before a partial copy, or note that it already is.
 * Omit error_code/entry_vector/saved_upcall_mask too.

I can't see why saved_upcall_mask exists in the first place, given that it is
also reflected in (v)rflags.IF.  None of MiniOS, Linux or NetBSD use it at
all.  I suspect the reflecting in IF was a slightly later addition dicovered
when running non-toy PV guests, and saved_upcall_mask got left behind as a
wart in the ABI.
---
 xen/arch/x86/domain.c | 38 ++++++++++++++++++++++++++++++++++++--
 xen/arch/x86/domctl.c | 38 ++++++++++++++++++++++++++++++++++++--
 xen/include/xlat.lst  |  2 --
 3 files changed, 72 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 56c381618712..56111eac3d94 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1233,7 +1233,24 @@ int arch_set_info_guest(
 
     if ( !compat )
     {
-        memcpy(&v->arch.user_regs, &c.nat->user_regs, sizeof(c.nat->user_regs));
+        memset(&v->arch.user_regs, 0, sizeof(v->arch.user_regs));
+        v->arch.user_regs.rbx               = c.nat->user_regs.rbx;
+        v->arch.user_regs.rcx               = c.nat->user_regs.rcx;
+        v->arch.user_regs.rdx               = c.nat->user_regs.rdx;
+        v->arch.user_regs.rsi               = c.nat->user_regs.rsi;
+        v->arch.user_regs.rdi               = c.nat->user_regs.rdi;
+        v->arch.user_regs.rbp               = c.nat->user_regs.rbp;
+        v->arch.user_regs.rax               = c.nat->user_regs.rax;
+        v->arch.user_regs.rip               = c.nat->user_regs.rip;
+        v->arch.user_regs.cs                = c.nat->user_regs.cs;
+        v->arch.user_regs.rflags            = c.nat->user_regs.rflags;
+        v->arch.user_regs.rsp               = c.nat->user_regs.rsp;
+        v->arch.user_regs.ss                = c.nat->user_regs.ss;
+        v->arch.user_regs.es                = c.nat->user_regs.es;
+        v->arch.user_regs.ds                = c.nat->user_regs.ds;
+        v->arch.user_regs.fs                = c.nat->user_regs.fs;
+        v->arch.user_regs.gs                = c.nat->user_regs.gs;
+
         if ( is_pv_domain(d) )
             memcpy(v->arch.pv.trap_ctxt, c.nat->trap_ctxt,
                    sizeof(c.nat->trap_ctxt));
@@ -1241,7 +1258,24 @@ int arch_set_info_guest(
 #ifdef CONFIG_COMPAT
     else
     {
-        XLAT_cpu_user_regs(&v->arch.user_regs, &c.cmp->user_regs);
+        memset(&v->arch.user_regs, 0, sizeof(v->arch.user_regs));
+        v->arch.user_regs.ebx               = c.cmp->user_regs.ebx;
+        v->arch.user_regs.ecx               = c.cmp->user_regs.ecx;
+        v->arch.user_regs.edx               = c.cmp->user_regs.edx;
+        v->arch.user_regs.esi               = c.cmp->user_regs.esi;
+        v->arch.user_regs.edi               = c.cmp->user_regs.edi;
+        v->arch.user_regs.ebp               = c.cmp->user_regs.ebp;
+        v->arch.user_regs.eax               = c.cmp->user_regs.eax;
+        v->arch.user_regs.eip               = c.cmp->user_regs.eip;
+        v->arch.user_regs.cs                = c.cmp->user_regs.cs;
+        v->arch.user_regs.eflags            = c.cmp->user_regs.eflags;
+        v->arch.user_regs.esp               = c.cmp->user_regs.esp;
+        v->arch.user_regs.ss                = c.cmp->user_regs.ss;
+        v->arch.user_regs.es                = c.cmp->user_regs.es;
+        v->arch.user_regs.ds                = c.cmp->user_regs.ds;
+        v->arch.user_regs.fs                = c.cmp->user_regs.fs;
+        v->arch.user_regs.gs                = c.cmp->user_regs.gs;
+
         if ( is_pv_domain(d) )
         {
             for ( i = 0; i < ARRAY_SIZE(c.cmp->trap_ctxt); ++i )
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 3044f706de1c..28fec0e12dbb 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1399,7 +1399,24 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c)
         c(flags |= VGCF_online);
     if ( !compat )
     {
-        memcpy(&c.nat->user_regs, &v->arch.user_regs, sizeof(c.nat->user_regs));
+        /* Backing memory is pre-zeroed. */
+        c.nat->user_regs.rbx               = v->arch.user_regs.rbx;
+        c.nat->user_regs.rcx               = v->arch.user_regs.rcx;
+        c.nat->user_regs.rdx               = v->arch.user_regs.rdx;
+        c.nat->user_regs.rsi               = v->arch.user_regs.rsi;
+        c.nat->user_regs.rdi               = v->arch.user_regs.rdi;
+        c.nat->user_regs.rbp               = v->arch.user_regs.rbp;
+        c.nat->user_regs.rax               = v->arch.user_regs.rax;
+        c.nat->user_regs.rip               = v->arch.user_regs.rip;
+        c.nat->user_regs.cs                = v->arch.user_regs.cs;
+        c.nat->user_regs.rflags            = v->arch.user_regs.rflags;
+        c.nat->user_regs.rsp               = v->arch.user_regs.rsp;
+        c.nat->user_regs.ss                = v->arch.user_regs.ss;
+        c.nat->user_regs.es                = v->arch.user_regs.es;
+        c.nat->user_regs.ds                = v->arch.user_regs.ds;
+        c.nat->user_regs.fs                = v->arch.user_regs.fs;
+        c.nat->user_regs.gs                = v->arch.user_regs.gs;
+
         if ( is_pv_domain(d) )
             memcpy(c.nat->trap_ctxt, v->arch.pv.trap_ctxt,
                    sizeof(c.nat->trap_ctxt));
@@ -1407,7 +1424,24 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c)
 #ifdef CONFIG_COMPAT
     else
     {
-        XLAT_cpu_user_regs(&c.cmp->user_regs, &v->arch.user_regs);
+        /* Backing memory is pre-zeroed. */
+        c.cmp->user_regs.ebx               = v->arch.user_regs.ebx;
+        c.cmp->user_regs.ecx               = v->arch.user_regs.ecx;
+        c.cmp->user_regs.edx               = v->arch.user_regs.edx;
+        c.cmp->user_regs.esi               = v->arch.user_regs.esi;
+        c.cmp->user_regs.edi               = v->arch.user_regs.edi;
+        c.cmp->user_regs.ebp               = v->arch.user_regs.ebp;
+        c.cmp->user_regs.eax               = v->arch.user_regs.eax;
+        c.cmp->user_regs.eip               = v->arch.user_regs.eip;
+        c.cmp->user_regs.cs                = v->arch.user_regs.cs;
+        c.cmp->user_regs.eflags            = v->arch.user_regs.eflags;
+        c.cmp->user_regs.esp               = v->arch.user_regs.esp;
+        c.cmp->user_regs.ss                = v->arch.user_regs.ss;
+        c.cmp->user_regs.es                = v->arch.user_regs.es;
+        c.cmp->user_regs.ds                = v->arch.user_regs.ds;
+        c.cmp->user_regs.fs                = v->arch.user_regs.fs;
+        c.cmp->user_regs.gs                = v->arch.user_regs.gs;
+
         if ( is_pv_domain(d) )
         {
             for ( i = 0; i < ARRAY_SIZE(c.cmp->trap_ctxt); ++i )
diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst
index 3c7b6c6830a9..6d6c6cfab251 100644
--- a/xen/include/xlat.lst
+++ b/xen/include/xlat.lst
@@ -34,8 +34,6 @@
 ?	pmu_intel_ctxt			arch-x86/pmu.h
 ?	pmu_regs			arch-x86/pmu.h
 
-!	cpu_user_regs			arch-x86/xen-@arch@.h
-
 ?	cpu_offline_action		arch-x86/xen-mca.h
 ?	mc				arch-x86/xen-mca.h
 !	mc_fetch			arch-x86/xen-mca.h
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 2/4] x86/pv: Store the data segment selectors outside of cpu_user_regs
Date: Thu,  7 Aug 2025 12:16:55 +0100
Message-Id: <20250807111657.201849-3-andrew.cooper3@citrix.com>
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In order to support FRED, we're going to have to remove the {ds..gs} fields
from struct cpu_user_regs.  This will impact v->arch.user_regs.

These fields are unused for HVM guests, but for PV hold the selector values
when the vCPU is scheduled out.

Introduce new fields for the selectors in struct pv_vcpu, and update:

 * {save,load}_segments(), context switching
 * arch_{set,set}_info_guest(), hypercalls
 * vcpu_show_registers(), diagnostics
 * dom0_construct(), PV dom0

to use the new storage.  This removes the final user of read_sregs() so drop
it too.

Signed-off-by: Andrew Cooper 
Reviewed-by: Jan Beulich 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/domain.c             | 70 +++++++++++++++----------------
 xen/arch/x86/domctl.c             | 16 +++----
 xen/arch/x86/include/asm/domain.h |  2 +
 xen/arch/x86/include/asm/regs.h   |  8 ----
 xen/arch/x86/pv/dom0_build.c      |  6 ++-
 xen/arch/x86/x86_64/traps.c       |  8 ++--
 6 files changed, 53 insertions(+), 57 deletions(-)

diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 56111eac3d94..a4ee8ff6ef0e 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1246,10 +1246,10 @@ int arch_set_info_guest(
         v->arch.user_regs.rflags            = c.nat->user_regs.rflags;
         v->arch.user_regs.rsp               = c.nat->user_regs.rsp;
         v->arch.user_regs.ss                = c.nat->user_regs.ss;
-        v->arch.user_regs.es                = c.nat->user_regs.es;
-        v->arch.user_regs.ds                = c.nat->user_regs.ds;
-        v->arch.user_regs.fs                = c.nat->user_regs.fs;
-        v->arch.user_regs.gs                = c.nat->user_regs.gs;
+        v->arch.pv.es                       = c.nat->user_regs.es;
+        v->arch.pv.ds                       = c.nat->user_regs.ds;
+        v->arch.pv.fs                       = c.nat->user_regs.fs;
+        v->arch.pv.gs                       = c.nat->user_regs.gs;
 
         if ( is_pv_domain(d) )
             memcpy(v->arch.pv.trap_ctxt, c.nat->trap_ctxt,
@@ -1271,10 +1271,10 @@ int arch_set_info_guest(
         v->arch.user_regs.eflags            = c.cmp->user_regs.eflags;
         v->arch.user_regs.esp               = c.cmp->user_regs.esp;
         v->arch.user_regs.ss                = c.cmp->user_regs.ss;
-        v->arch.user_regs.es                = c.cmp->user_regs.es;
-        v->arch.user_regs.ds                = c.cmp->user_regs.ds;
-        v->arch.user_regs.fs                = c.cmp->user_regs.fs;
-        v->arch.user_regs.gs                = c.cmp->user_regs.gs;
+        v->arch.pv.es                       = c.cmp->user_regs.es;
+        v->arch.pv.ds                       = c.cmp->user_regs.ds;
+        v->arch.pv.fs                       = c.cmp->user_regs.fs;
+        v->arch.pv.gs                       = c.cmp->user_regs.gs;
 
         if ( is_pv_domain(d) )
         {
@@ -1762,7 +1762,6 @@ long do_vcpu_op(int cmd, unsigned int vcpuid, XEN_GUEST_HANDLE_PARAM(void) arg)
  */
 static void load_segments(struct vcpu *n)
 {
-    struct cpu_user_regs *uregs = &n->arch.user_regs;
     unsigned long gsb = 0, gss = 0;
     bool compat = is_pv_32bit_vcpu(n);
     bool all_segs_okay = true, fs_gs_done = false;
@@ -1796,7 +1795,7 @@ static void load_segments(struct vcpu *n)
         if ( !(n->arch.flags & TF_kernel_mode) )
             SWAP(gsb, gss);
 
-        if ( using_svm() && (uregs->fs | uregs->gs) <= 3 )
+        if ( using_svm() && (n->arch.pv.fs | n->arch.pv.gs) <= 3 )
             fs_gs_done = svm_load_segs(n->arch.pv.ldt_ents, LDT_VIRT_START(n),
                                        n->arch.pv.fs_base, gsb, gss);
     }
@@ -1805,12 +1804,12 @@ static void load_segments(struct vcpu *n)
     {
         load_LDT(n);
 
-        TRY_LOAD_SEG(fs, uregs->fs);
-        TRY_LOAD_SEG(gs, uregs->gs);
+        TRY_LOAD_SEG(fs, n->arch.pv.fs);
+        TRY_LOAD_SEG(gs, n->arch.pv.gs);
     }
 
-    TRY_LOAD_SEG(ds, uregs->ds);
-    TRY_LOAD_SEG(es, uregs->es);
+    TRY_LOAD_SEG(ds, n->arch.pv.ds);
+    TRY_LOAD_SEG(es, n->arch.pv.es);
 
     if ( !fs_gs_done && !compat )
     {
@@ -1863,13 +1862,13 @@ static void load_segments(struct vcpu *n)
             }
 
             if ( ret |
-                 put_guest(rflags,      esp - 1) |
-                 put_guest(cs_and_mask, esp - 2) |
-                 put_guest(regs->eip,   esp - 3) |
-                 put_guest(uregs->gs,   esp - 4) |
-                 put_guest(uregs->fs,   esp - 5) |
-                 put_guest(uregs->es,   esp - 6) |
-                 put_guest(uregs->ds,   esp - 7) )
+                 put_guest(rflags,        esp - 1) |
+                 put_guest(cs_and_mask,   esp - 2) |
+                 put_guest(regs->eip,     esp - 3) |
+                 put_guest(n->arch.pv.gs, esp - 4) |
+                 put_guest(n->arch.pv.fs, esp - 5) |
+                 put_guest(n->arch.pv.es, esp - 6) |
+                 put_guest(n->arch.pv.ds, esp - 7) )
                 domain_crash(n->domain,
                              "Error creating compat failsafe callback frame\n");
 
@@ -1895,17 +1894,17 @@ static void load_segments(struct vcpu *n)
         cs_and_mask = (unsigned long)regs->cs |
             ((unsigned long)vcpu_info(n, evtchn_upcall_mask) << 32);
 
-        if ( put_guest(regs->ss,    rsp -  1) |
-             put_guest(regs->rsp,   rsp -  2) |
-             put_guest(rflags,      rsp -  3) |
-             put_guest(cs_and_mask, rsp -  4) |
-             put_guest(regs->rip,   rsp -  5) |
-             put_guest(uregs->gs,   rsp -  6) |
-             put_guest(uregs->fs,   rsp -  7) |
-             put_guest(uregs->es,   rsp -  8) |
-             put_guest(uregs->ds,   rsp -  9) |
-             put_guest(regs->r11,   rsp - 10) |
-             put_guest(regs->rcx,   rsp - 11) )
+        if ( put_guest(regs->ss,      rsp -  1) |
+             put_guest(regs->rsp,     rsp -  2) |
+             put_guest(rflags,        rsp -  3) |
+             put_guest(cs_and_mask,   rsp -  4) |
+             put_guest(regs->rip,     rsp -  5) |
+             put_guest(n->arch.pv.gs, rsp -  6) |
+             put_guest(n->arch.pv.fs, rsp -  7) |
+             put_guest(n->arch.pv.es, rsp -  8) |
+             put_guest(n->arch.pv.ds, rsp -  9) |
+             put_guest(regs->r11,     rsp - 10) |
+             put_guest(regs->rcx,     rsp - 11) )
             domain_crash(n->domain,
                          "Error creating failsafe callback frame\n");
 
@@ -1934,9 +1933,10 @@ static void load_segments(struct vcpu *n)
  */
 static void save_segments(struct vcpu *v)
 {
-    struct cpu_user_regs *regs = &v->arch.user_regs;
-
-    read_sregs(regs);
+    asm ( "mov %%ds, %0" : "=m" (v->arch.pv.ds) );
+    asm ( "mov %%es, %0" : "=m" (v->arch.pv.es) );
+    asm ( "mov %%fs, %0" : "=m" (v->arch.pv.fs) );
+    asm ( "mov %%gs, %0" : "=m" (v->arch.pv.gs) );
 
     if ( !is_pv_32bit_vcpu(v) )
     {
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 28fec0e12dbb..3e94af51a795 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1412,10 +1412,10 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c)
         c.nat->user_regs.rflags            = v->arch.user_regs.rflags;
         c.nat->user_regs.rsp               = v->arch.user_regs.rsp;
         c.nat->user_regs.ss                = v->arch.user_regs.ss;
-        c.nat->user_regs.es                = v->arch.user_regs.es;
-        c.nat->user_regs.ds                = v->arch.user_regs.ds;
-        c.nat->user_regs.fs                = v->arch.user_regs.fs;
-        c.nat->user_regs.gs                = v->arch.user_regs.gs;
+        c.nat->user_regs.es                = v->arch.pv.es;
+        c.nat->user_regs.ds                = v->arch.pv.ds;
+        c.nat->user_regs.fs                = v->arch.pv.fs;
+        c.nat->user_regs.gs                = v->arch.pv.gs;
 
         if ( is_pv_domain(d) )
             memcpy(c.nat->trap_ctxt, v->arch.pv.trap_ctxt,
@@ -1437,10 +1437,10 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c)
         c.cmp->user_regs.eflags            = v->arch.user_regs.eflags;
         c.cmp->user_regs.esp               = v->arch.user_regs.esp;
         c.cmp->user_regs.ss                = v->arch.user_regs.ss;
-        c.cmp->user_regs.es                = v->arch.user_regs.es;
-        c.cmp->user_regs.ds                = v->arch.user_regs.ds;
-        c.cmp->user_regs.fs                = v->arch.user_regs.fs;
-        c.cmp->user_regs.gs                = v->arch.user_regs.gs;
+        c.cmp->user_regs.es                = v->arch.pv.es;
+        c.cmp->user_regs.ds                = v->arch.pv.ds;
+        c.cmp->user_regs.fs                = v->arch.pv.fs;
+        c.cmp->user_regs.gs                = v->arch.pv.gs;
 
         if ( is_pv_domain(d) )
         {
diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h
index 8c0dea12a526..c31e74c6fa9b 100644
--- a/xen/arch/x86/include/asm/domain.h
+++ b/xen/arch/x86/include/asm/domain.h
@@ -546,6 +546,8 @@ struct pv_vcpu
     bool syscall32_disables_events;
     bool sysenter_disables_events;
 
+    uint16_t ds, es, fs, gs;
+
     /*
      * 64bit segment bases.
      *
diff --git a/xen/arch/x86/include/asm/regs.h b/xen/arch/x86/include/asm/regs.h
index 60b0d7b8735b..ce9b028276a1 100644
--- a/xen/arch/x86/include/asm/regs.h
+++ b/xen/arch/x86/include/asm/regs.h
@@ -44,12 +44,4 @@
     __sel;                                           \
 })
 
-static inline void read_sregs(struct cpu_user_regs *regs)
-{
-    asm ( "mov %%ds, %0" : "=m" (regs->ds) );
-    asm ( "mov %%es, %0" : "=m" (regs->es) );
-    asm ( "mov %%fs, %0" : "=m" (regs->fs) );
-    asm ( "mov %%gs, %0" : "=m" (regs->gs) );
-}
-
 #endif /* __X86_REGS_H__ */
diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c
index c37bea945431..21158ce1812e 100644
--- a/xen/arch/x86/pv/dom0_build.c
+++ b/xen/arch/x86/pv/dom0_build.c
@@ -1012,8 +1012,10 @@ static int __init dom0_construct(const struct boot_domain *bd)
      *  [rAX,rBX,rCX,rDX,rDI,rBP,R8-R15 are zero]
      */
     regs = &v->arch.user_regs;
-    regs->ds = regs->es = regs->fs = regs->gs =
-               (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS);
+    v->arch.pv.ds = (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS);
+    v->arch.pv.es = (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS);
+    v->arch.pv.fs = (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS);
+    v->arch.pv.gs = (compat ? FLAT_COMPAT_KERNEL_DS : FLAT_KERNEL_DS);
     regs->ss = (compat ? FLAT_COMPAT_KERNEL_SS : FLAT_KERNEL_SS);
     regs->cs = (compat ? FLAT_COMPAT_KERNEL_CS : FLAT_KERNEL_CS);
     regs->rip = parms.virt_entry;
diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c
index 8460a4a1ae59..29ac5a14ca3f 100644
--- a/xen/arch/x86/x86_64/traps.c
+++ b/xen/arch/x86/x86_64/traps.c
@@ -220,10 +220,10 @@ void vcpu_show_registers(struct vcpu *v)
         state.gsb = gsb;
         state.gss = gss;
 
-        state.ds = v->arch.user_regs.ds;
-        state.es = v->arch.user_regs.es;
-        state.fs = v->arch.user_regs.fs;
-        state.gs = v->arch.user_regs.gs;
+        state.ds = v->arch.pv.ds;
+        state.es = v->arch.pv.es;
+        state.fs = v->arch.pv.fs;
+        state.gs = v->arch.pv.gs;
 
         context = CTXT_pv_guest;
     }
-- 
2.39.5



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Date: Thu, 7 Aug 2025 14:00:25 +0200
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Subject: Re: [PATCH v3 06/20] xen/riscv: add root page table allocation
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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References: 
 <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com>
 <3c02593f-deae-4109-9334-0ac4376a9a9e@suse.com>
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On 8/5/25 12:37 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> Introduce support for allocating and initializing the root page table
>> required for RISC-V stage-2 address translation.
>>
>> To implement root page table allocation the following is introduced:
>> - p2m_get_clean_page() and p2m_alloc_root_table(), p2m_allocate_root()
>>    helpers to allocate and zero a 16 KiB root page table, as mandated
>>    by the RISC-V privileged specification for Sv32x4/Sv39x4/Sv48x4/Sv57x4
>>    modes.
>> - Update p2m_init() to inititialize p2m_root_order.
>> - Add maddr_to_page() and page_to_maddr() macros for easier address
>>    manipulation.
>> - Introduce paging_ret_pages_to_domheap() to return some pages before
>>    allocate 16 KiB pages for root page table.
>> - Allocate root p2m table after p2m pool is initialized.
>> - Add construct_hgatp() to construct the hgatp register value based on
>>    p2m->root, p2m->hgatp_mode and VMID.
> Imo for this to be complete, freeing of the root table also wants taking
> care of. Much like imo p2m_init() would better immediately be accompanied
> by the respective teardown function. Once you start using them, you want
> to use them in pairs, after all.

I decided to ignore freeing of the root table and tearing down p2m mapping
as it is going to be used during a domain destroy, which isn't supported
at the moment, and thereby an implementation of them could be delayed when
they really will be used.

>
>> --- a/xen/arch/riscv/include/asm/riscv_encoding.h
>> +++ b/xen/arch/riscv/include/asm/riscv_encoding.h
>> @@ -133,11 +133,13 @@
>>   #define HGATP_MODE_SV48X4		_UL(9)
>>   
>>   #define HGATP32_MODE_SHIFT		31
>> +#define HGATP32_MODE_MASK		_UL(0x80000000)
>>   #define HGATP32_VMID_SHIFT		22
>>   #define HGATP32_VMID_MASK		_UL(0x1FC00000)
>>   #define HGATP32_PPN			_UL(0x003FFFFF)
>>   
>>   #define HGATP64_MODE_SHIFT		60
>> +#define HGATP64_MODE_MASK		_ULL(0xF000000000000000)
>>   #define HGATP64_VMID_SHIFT		44
>>   #define HGATP64_VMID_MASK		_ULL(0x03FFF00000000000)
>>   #define HGATP64_PPN			_ULL(0x00000FFFFFFFFFFF)
>> @@ -170,6 +172,7 @@
>>   #define HGATP_VMID_SHIFT		HGATP64_VMID_SHIFT
>>   #define HGATP_VMID_MASK			HGATP64_VMID_MASK
>>   #define HGATP_MODE_SHIFT		HGATP64_MODE_SHIFT
>> +#define HGATP_MODE_MASK			HGATP64_MODE_MASK
>>   #else
>>   #define MSTATUS_SD			MSTATUS32_SD
>>   #define SSTATUS_SD			SSTATUS32_SD
>> @@ -181,8 +184,11 @@
>>   #define HGATP_VMID_SHIFT		HGATP32_VMID_SHIFT
>>   #define HGATP_VMID_MASK			HGATP32_VMID_MASK
>>   #define HGATP_MODE_SHIFT		HGATP32_MODE_SHIFT
>> +#define HGATP_MODE_MASK			HGATP32_MODE_MASK
>>   #endif
>>   
>> +#define GUEST_ROOT_PAGE_TABLE_SIZE	KB(16)
> In another context I already mentioned that imo you want to be careful with
> the use of "guest" in identifiers. It's not the guest page tables which have
> an order-2 root table, but the P2M (Xen terminology) or G-stage / second
> stage (RISC-V spec terminology) ones. As long as you're only doing P2M
> work, this may not look significant. But once you actually start dealing
> with guest page tables, it easily can end up confusing.

I thought that GUEST_ROOT_PAGE_TABLE is equal to G-stage root page table.
But it is confusing even now, then I'll use GSTAGE_ROOT_PAGE_TABLE_SIZE
instead.

>
>> --- a/xen/arch/riscv/p2m.c
>> +++ b/xen/arch/riscv/p2m.c
>> @@ -1,8 +1,86 @@
>> +#include 
>>   #include 
>>   #include 
>>   #include 
>>   
>>   #include 
>> +#include 
>> +#include 
>> +
>> +unsigned int __read_mostly p2m_root_order;
> If this is to be a variable at all, it ought to be __ro_after_init, and
> hence it shouldn't be written every time p2m_init() is run. If you want
> to to remain as a variable, what's wrong with
>
> const unsigned int p2m_root_order = ilog2(GUEST_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT;
>
> or some such? But of course equally well you could have
>
> #define P2M_ROOT_ORDER  (ilog2(GUEST_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT)

The only one reason p2m_root_order was introduced as variable it was that
I had a compilation issue when define P2M_ROOT_ORDER in such way:
   #define P2M_ROOT_ORDER  get_order_from_bytes(GUEST_ROOT_PAGE_TABLE_SIZE)
But I can't reproduce it anymore.

Anyway, your option is better as it should be faster.

>
>> +static void clear_and_clean_page(struct page_info *page)
>> +{
>> +    clear_domain_page(page_to_mfn(page));
>> +
>> +    /*
>> +     * If the IOMMU doesn't support coherent walks and the p2m tables are
>> +     * shared between the CPU and IOMMU, it is necessary to clean the
>> +     * d-cache.
>> +     */
> That is, ...
>
>> +    clean_dcache_va_range(page, PAGE_SIZE);
> ... this call really wants to be conditional?

It makes sense. I will add "if ( p2m->clean_pte )" and update clear_and_clean_page()
declaration.

>
>> +}
>> +
>> +static struct page_info *p2m_allocate_root(struct domain *d)
> With there also being p2m_alloc_root_table() and with that being the sole
> caller of the function here, I wonder: Is having this in a separate
> function really outweighing the possible confusion of which of the two
> functions to use?

p2m_allocate_root() will be also used in further patches to allocate
root's metadata page(s), but, also, in the same function p2m_alloc_root_table().

Probably, to avoid confusion it makes sense to rename p2m_allocate_root() to
p2m_allocate_root_page().


>
>> +{
>> +    struct page_info *page;
>> +
>> +    /*
>> +     * As mentioned in the Priviliged Architecture Spec (version 20240411)
>> +     * in Section 18.5.1, for the paged virtual-memory schemes  (Sv32x4,
>> +     * Sv39x4, Sv48x4, and Sv57x4), the root page table is 16 KiB and must
>> +     * be aligned to a 16-KiB boundary.
>> +     */
>> +    page = alloc_domheap_pages(d, P2M_ROOT_ORDER, MEMF_no_owner);
>> +    if ( !page )
>> +        return NULL;
>> +
>> +    for ( unsigned int i = 0; i < P2M_ROOT_PAGES; i++ )
>> +        clear_and_clean_page(page + i);
>> +
>> +    return page;
>> +}
>> +
>> +unsigned long construct_hgatp(struct p2m_domain *p2m, uint16_t vmid)
>> +{
>> +    unsigned long ppn;
>> +
>> +    ppn = PFN_DOWN(page_to_maddr(p2m->root)) & HGATP_PPN;
> Why not page_to_pfn() or mfn_x(page_to_mfn())? I.e. why mix different groups
> of accessors?

No specific reason, just missed such option.

>
> As to "& HGATP_PPN" - that's making an assumption that you could avoid by
> using ...
>
>> +    /* TODO: add detection of hgatp_mode instead of hard-coding it. */
>> +#if RV_STAGE1_MODE == SATP_MODE_SV39
>> +    p2m->hgatp_mode = HGATP_MODE_SV39X4;
>> +#elif RV_STAGE1_MODE == SATP_MODE_SV48
>> +    p2m->hgatp_mode = HGATP_MODE_SV48X4;
>> +#else
>> +#   error "add HGATP_MODE"
>> +#endif
>> +
>> +    return ppn | MASK_INSR(p2m->hgatp_mode, HGATP_MODE_MASK) |
>> +                 MASK_INSR(vmid, HGATP_VMID_MASK);
> ... MASK_INSR() also on "ppn".
>
> As to the writing of p2m->hgatp_mode - you don't want to do this here, when
> this is the function to calculate the value to put into hgatp. This field
> needs calculating only once, perhaps in p2m_init().

Agree, it makes sense to move hgatp_mode detection to p2m_init().

>
>> +static int p2m_alloc_root_table(struct p2m_domain *p2m)
>> +{
>> +    struct domain *d = p2m->domain;
>> +    struct page_info *page;
>> +    const unsigned int nr_root_pages = P2M_ROOT_PAGES;
> Is this local variable really of any use?

It will be needed for one of the next patches and to have less change in
further patch, I've decided to introduce it here.

>
>> +    /*
>> +     * Return back nr_root_pages to assure the root table memory is also
>> +     * accounted against the P2M pool of the domain.
>> +     */
>> +    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
>> +        return -ENOMEM;
>> +
>> +    page = p2m_allocate_root(d);
>> +    if ( !page )
>> +        return -ENOMEM;
> Hmm, and the pool is then left shrunk by 4 pages?

Yes until they are used for root table it shouldn't be in p2m pool (freelist),
when root table will be freed then it makes sense to return them back.
Am I missing something?

Probably, you meant that it is needed to update p2m->pages?

>
>> --- a/xen/arch/riscv/paging.c
>> +++ b/xen/arch/riscv/paging.c
>> @@ -54,6 +54,36 @@ int paging_freelist_init(struct domain *d, unsigned long pages,
>>   
>>       return 0;
>>   }
>> +
>> +bool paging_ret_pages_to_domheap(struct domain *d, unsigned int nr_pages)
>> +{
>> +    struct page_info *page;
>> +
>> +    ASSERT(spin_is_locked(&d->arch.paging.lock));
>> +
>> +    if ( ACCESS_ONCE(d->arch.paging.total_pages) < nr_pages )
>> +        return false;
>> +
>> +    for ( unsigned int i = 0; i < nr_pages; i++ )
>> +    {
>> +        /* Return memory to domheap. */
>> +        page = page_list_remove_head(&d->arch.paging.freelist);
>> +        if( page )
>> +        {
>> +            ACCESS_ONCE(d->arch.paging.total_pages)--;
>> +            free_domheap_page(page);
>> +        }
>> +        else
>> +        {
>> +            printk(XENLOG_ERR
>> +                   "Failed to free P2M pages, P2M freelist is empty.\n");
>> +            return false;
> Looks pretty redundant with half of paging_freelist_init(), including the
> stray full stop in the log message.

I will introduce then a separate function (for a code, which is inside
for-loop) and use it here and in paging_freelist_init().

Thanks.

~ Oleksii

--------------WQs5Vkl5Q3M7mmCKOOUD9V9K
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 7bit



  
    
  
  
    

    
    
    
    
    On 8/5/25 12:37 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    Introduce support for allocating and initializing the root page table
required for RISC-V stage-2 address translation.

To implement root page table allocation the following is introduced:
- p2m_get_clean_page() and p2m_alloc_root_table(), p2m_allocate_root()
  helpers to allocate and zero a 16 KiB root page table, as mandated
  by the RISC-V privileged specification for Sv32x4/Sv39x4/Sv48x4/Sv57x4
  modes.
- Update p2m_init() to inititialize p2m_root_order.
- Add maddr_to_page() and page_to_maddr() macros for easier address
  manipulation.
- Introduce paging_ret_pages_to_domheap() to return some pages before
  allocate 16 KiB pages for root page table.
- Allocate root p2m table after p2m pool is initialized.
- Add construct_hgatp() to construct the hgatp register value based on
  p2m->root, p2m->hgatp_mode and VMID.

    
      
    
      
    Imo for this to be complete, freeing of the root table also wants taking
care of. Much like imo p2m_init() would better immediately be accompanied
by the respective teardown function. Once you start using them, you want
to use them in pairs, after all.
    
    
    
    
    I decided to ignore freeing of the root table and tearing down p2m mapping
as it is going to be used during a domain destroy, which isn't supported
at the moment, and thereby an implementation of them could be delayed when
they really will be used.


    
    
    
      
    

    
      
    
        
    --- a/xen/arch/riscv/include/asm/riscv_encoding.h
+++ b/xen/arch/riscv/include/asm/riscv_encoding.h
@@ -133,11 +133,13 @@
 #define HGATP_MODE_SV48X4		_UL(9)
 
 #define HGATP32_MODE_SHIFT		31
+#define HGATP32_MODE_MASK		_UL(0x80000000)
 #define HGATP32_VMID_SHIFT		22
 #define HGATP32_VMID_MASK		_UL(0x1FC00000)
 #define HGATP32_PPN			_UL(0x003FFFFF)
 
 #define HGATP64_MODE_SHIFT		60
+#define HGATP64_MODE_MASK		_ULL(0xF000000000000000)
 #define HGATP64_VMID_SHIFT		44
 #define HGATP64_VMID_MASK		_ULL(0x03FFF00000000000)
 #define HGATP64_PPN			_ULL(0x00000FFFFFFFFFFF)
@@ -170,6 +172,7 @@
 #define HGATP_VMID_SHIFT		HGATP64_VMID_SHIFT
 #define HGATP_VMID_MASK			HGATP64_VMID_MASK
 #define HGATP_MODE_SHIFT		HGATP64_MODE_SHIFT
+#define HGATP_MODE_MASK			HGATP64_MODE_MASK
 #else
 #define MSTATUS_SD			MSTATUS32_SD
 #define SSTATUS_SD			SSTATUS32_SD
@@ -181,8 +184,11 @@
 #define HGATP_VMID_SHIFT		HGATP32_VMID_SHIFT
 #define HGATP_VMID_MASK			HGATP32_VMID_MASK
 #define HGATP_MODE_SHIFT		HGATP32_MODE_SHIFT
+#define HGATP_MODE_MASK			HGATP32_MODE_MASK
 #endif
 
+#define GUEST_ROOT_PAGE_TABLE_SIZE	KB(16)

    
      
    
      
    In another context I already mentioned that imo you want to be careful with
the use of "guest" in identifiers. It's not the guest page tables which have
an order-2 root table, but the P2M (Xen terminology) or G-stage / second
stage (RISC-V spec terminology) ones. As long as you're only doing P2M
work, this may not look significant. But once you actually start dealing
with guest page tables, it easily can end up confusing.
    
    
    
    
    I thought that GUEST_ROOT_PAGE_TABLE is equal to G-stage root page table.
But it is confusing even now, then I'll use GSTAGE_ROOT_PAGE_TABLE_SIZE
instead.


    
    
    
      
    

    
      
    
        
    --- a/xen/arch/riscv/p2m.c
+++ b/xen/arch/riscv/p2m.c
@@ -1,8 +1,86 @@
+#include <xen/domain_page.h>
 #include <xen/mm.h>
 #include <xen/rwlock.h>
 #include <xen/sched.h>
 
 #include <asm/paging.h>
+#include <asm/p2m.h>
+#include <asm/riscv_encoding.h>
+
+unsigned int __read_mostly p2m_root_order;

    
      
    
      
    If this is to be a variable at all, it ought to be __ro_after_init, and
hence it shouldn't be written every time p2m_init() is run. If you want
to to remain as a variable, what's wrong with

const unsigned int p2m_root_order = ilog2(GUEST_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT;

or some such? But of course equally well you could have

#define P2M_ROOT_ORDER  (ilog2(GUEST_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT)
    
    
    
    
    The only one reason p2m_root_order was introduced as variable it was that
I had a compilation issue when define P2M_ROOT_ORDER in such way:
  #define P2M_ROOT_ORDER  get_order_from_bytes(GUEST_ROOT_PAGE_TABLE_SIZE)
But I can't reproduce it anymore.

Anyway, your option is better as it should be faster.


    
    
    
      
    

    
      
    
        
    +static void clear_and_clean_page(struct page_info *page)
+{
+    clear_domain_page(page_to_mfn(page));
+
+    /*
+     * If the IOMMU doesn't support coherent walks and the p2m tables are
+     * shared between the CPU and IOMMU, it is necessary to clean the
+     * d-cache.
+     */

    
      
    
      
    That is, ...


    
      
    
        
    +    clean_dcache_va_range(page, PAGE_SIZE);

    
      
    
      
    ... this call really wants to be conditional?
    
    
    
    
    It makes sense. I will add "if ( p2m->clean_pte )" and update clear_and_clean_page()
declaration.


    
    
    
      
    

    
      
    
        
    +}
+
+static struct page_info *p2m_allocate_root(struct domain *d)

    
      
    
      
    With there also being p2m_alloc_root_table() and with that being the sole
caller of the function here, I wonder: Is having this in a separate
function really outweighing the possible confusion of which of the two
functions to use?
    
    
    
    
    p2m_allocate_root() will be also used in further patches to allocate
root's metadata page(s), but, also, in the same function p2m_alloc_root_table().

Probably, to avoid confusion it makes sense to rename p2m_allocate_root() to
p2m_allocate_root_page().



    
    
    
      
    

    
      
    
        
    +{
+    struct page_info *page;
+
+    /*
+     * As mentioned in the Priviliged Architecture Spec (version 20240411)
+     * in Section 18.5.1, for the paged virtual-memory schemes  (Sv32x4,
+     * Sv39x4, Sv48x4, and Sv57x4), the root page table is 16 KiB and must
+     * be aligned to a 16-KiB boundary.
+     */
+    page = alloc_domheap_pages(d, P2M_ROOT_ORDER, MEMF_no_owner);
+    if ( !page )
+        return NULL;
+
+    for ( unsigned int i = 0; i < P2M_ROOT_PAGES; i++ )
+        clear_and_clean_page(page + i);
+
+    return page;
+}
+
+unsigned long construct_hgatp(struct p2m_domain *p2m, uint16_t vmid)
+{
+    unsigned long ppn;
+
+    ppn = PFN_DOWN(page_to_maddr(p2m->root)) & HGATP_PPN;

    
      
    
      
    Why not page_to_pfn() or mfn_x(page_to_mfn())? I.e. why mix different groups
of accessors?
    
    
    
    
    No specific reason, just missed such option.


    
    
    
      
    
As to "& HGATP_PPN" - that's making an assumption that you could avoid by
using ...


    
      
    
        
    +    /* TODO: add detection of hgatp_mode instead of hard-coding it. */
+#if RV_STAGE1_MODE == SATP_MODE_SV39
+    p2m->hgatp_mode = HGATP_MODE_SV39X4;
+#elif RV_STAGE1_MODE == SATP_MODE_SV48
+    p2m->hgatp_mode = HGATP_MODE_SV48X4;
+#else
+#   error "add HGATP_MODE"
+#endif
+
+    return ppn | MASK_INSR(p2m->hgatp_mode, HGATP_MODE_MASK) |
+                 MASK_INSR(vmid, HGATP_VMID_MASK);

    
      
    
      
    ... MASK_INSR() also on "ppn".

As to the writing of p2m->hgatp_mode - you don't want to do this here, when
this is the function to calculate the value to put into hgatp. This field
needs calculating only once, perhaps in p2m_init().
    
    
    
    
    Agree, it makes sense to move hgatp_mode detection to p2m_init().


    
    
    
      
    

    
      
    
        
    +static int p2m_alloc_root_table(struct p2m_domain *p2m)
+{
+    struct domain *d = p2m->domain;
+    struct page_info *page;
+    const unsigned int nr_root_pages = P2M_ROOT_PAGES;

    
      
    
      
    Is this local variable really of any use?
    
    
    
    
    It will be needed for one of the next patches and to have less change in
further patch, I've decided to introduce it here.

    
    
    
      
    

    
      
    
        
    +    /*
+     * Return back nr_root_pages to assure the root table memory is also
+     * accounted against the P2M pool of the domain.
+     */
+    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
+        return -ENOMEM;
+
+    page = p2m_allocate_root(d);
+    if ( !page )
+        return -ENOMEM;

    
      
    
      
    Hmm, and the pool is then left shrunk by 4 pages?
    
    
    
    
    Yes until they are used for root table it shouldn't be in p2m pool (freelist),
when root table will be freed then it makes sense to return them back.
Am I missing something?

Probably, you meant that it is needed to update p2m->pages?


    
    
    
      
    

    
      
    
        
    --- a/xen/arch/riscv/paging.c
+++ b/xen/arch/riscv/paging.c
@@ -54,6 +54,36 @@ int paging_freelist_init(struct domain *d, unsigned long pages,
 
     return 0;
 }
+
+bool paging_ret_pages_to_domheap(struct domain *d, unsigned int nr_pages)
+{
+    struct page_info *page;
+
+    ASSERT(spin_is_locked(&d->arch.paging.lock));
+
+    if ( ACCESS_ONCE(d->arch.paging.total_pages) < nr_pages )
+        return false;
+
+    for ( unsigned int i = 0; i < nr_pages; i++ )
+    {
+        /* Return memory to domheap. */
+        page = page_list_remove_head(&d->arch.paging.freelist);
+        if( page )
+        {
+            ACCESS_ONCE(d->arch.paging.total_pages)--;
+            free_domheap_page(page);
+        }
+        else
+        {
+            printk(XENLOG_ERR
+                   "Failed to free P2M pages, P2M freelist is empty.\n");
+            return false;

    
      
    
      
    Looks pretty redundant with half of paging_freelist_init(), including the
stray full stop in the log message.
    
    
    
    
    I will introduce then a separate function (for a code, which is inside
for-loop) and use it here and in paging_freelist_init().

Thanks.

~ Oleksii
    
  


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Date: Thu, 7 Aug 2025 09:07:15 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 06/16] iommu/dma: extend iommu_dma_*map_phys API to
 handle MMIO memory
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On Mon, Aug 04, 2025 at 03:42:40PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Combine iommu_dma_*map_phys with iommu_dma_*map_resource interfaces in
> order to allow single phys_addr_t flow.

Some later patch deletes iommu_dma_map_resource() ? Mention that plan here?

> --- a/drivers/iommu/dma-iommu.c
> +++ b/drivers/iommu/dma-iommu.c
> @@ -1193,12 +1193,17 @@ static inline size_t iova_unaligned(struct iova_domain *iovad, phys_addr_t phys,
>  dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
>  		enum dma_data_direction dir, unsigned long attrs)
>  {
> -	bool coherent = dev_is_dma_coherent(dev);
> -	int prot = dma_info_to_prot(dir, coherent, attrs);
>  	struct iommu_domain *domain = iommu_get_dma_domain(dev);
>  	struct iommu_dma_cookie *cookie = domain->iova_cookie;
>  	struct iova_domain *iovad = &cookie->iovad;
>  	dma_addr_t iova, dma_mask = dma_get_mask(dev);
> +	bool coherent;
> +	int prot;
> +
> +	if (attrs & DMA_ATTR_MMIO)
> +		return __iommu_dma_map(dev, phys, size,
> +				dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO,
> +				dma_get_mask(dev));

I realize that iommu_dma_map_resource() doesn't today, but shouldn't
this be checking for swiotlb:

	if (dev_use_swiotlb(dev, size, dir) &&
	    iova_unaligned(iovad, phys, size)) {

Except we have to fail for ATTR_MMIO?

Now that we have ATTR_MMIO, should dma_info_to_prot() just handle it
directly instead of open coding the | IOMMU_MMIO and messing with the
coherent attribute?

Jason


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Date: Thu, 7 Aug 2025 09:13:27 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 07/16] dma-mapping: convert dma_direct_*map_page to be
 phys_addr_t based
Message-ID: <20250807121327.GG184255@nvidia.com>
References: 
 <882499bb37bf4af3dece27d9f791a8982ca4c6a7.1754292567.git.leon@kernel.org>
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On Mon, Aug 04, 2025 at 03:42:41PM +0300, Leon Romanovsky wrote:
> --- a/kernel/dma/direct.h
> +++ b/kernel/dma/direct.h
> @@ -80,42 +80,54 @@ static inline void dma_direct_sync_single_for_cpu(struct device *dev,
>  		arch_dma_mark_clean(paddr, size);
>  }
>  
> -static inline dma_addr_t dma_direct_map_page(struct device *dev,
> -		struct page *page, unsigned long offset, size_t size,
> -		enum dma_data_direction dir, unsigned long attrs)
> +static inline dma_addr_t dma_direct_map_phys(struct device *dev,
> +		phys_addr_t phys, size_t size, enum dma_data_direction dir,
> +		unsigned long attrs)
>  {
> -	phys_addr_t phys = page_to_phys(page) + offset;
> -	dma_addr_t dma_addr = phys_to_dma(dev, phys);
> +	bool is_mmio = attrs & DMA_ATTR_MMIO;
> +	dma_addr_t dma_addr;
> +	bool capable;
> +
> +	dma_addr = (is_mmio) ? phys : phys_to_dma(dev, phys);
> +	capable = dma_capable(dev, dma_addr, size, is_mmio);
> +	if (is_mmio) {
> +	       if (unlikely(!capable))
> +		       goto err_overflow;
> +	       return dma_addr;

Similar remark here, shouldn't we be checking swiotlb things for
ATTR_MMIO and failing if swiotlb is needed?

> -	if (is_swiotlb_force_bounce(dev)) {
> -		if (is_pci_p2pdma_page(page))
> -			return DMA_MAPPING_ERROR;

This

> -	if (unlikely(!dma_capable(dev, dma_addr, size, true)) ||
> -	    dma_kmalloc_needs_bounce(dev, size, dir)) {
> -		if (is_pci_p2pdma_page(page))
> -			return DMA_MAPPING_ERROR;

And this

Jason


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Date: Thu, 7 Aug 2025 09:21:15 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 08/16] kmsan: convert kmsan_handle_dma to use physical
 addresses
Message-ID: <20250807122115.GH184255@nvidia.com>
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On Mon, Aug 04, 2025 at 03:42:42PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Convert the KMSAN DMA handling function from page-based to physical
> address-based interface.
> 
> The refactoring renames kmsan_handle_dma() parameters from accepting
> (struct page *page, size_t offset, size_t size) to (phys_addr_t phys,
> size_t size). A PFN_VALID check is added to prevent KMSAN operations
> on non-page memory, preventing from non struct page backed address,
> 
> As part of this change, support for highmem addresses is implemented
> using kmap_local_page() to handle both lowmem and highmem regions
> properly. All callers throughout the codebase are updated to use the
> new phys_addr_t based interface.

Use the function Matthew pointed at kmap_local_pfn()

Maybe introduce the kmap_local_phys() he suggested too.

>  /* Helper function to handle DMA data transfers. */
> -void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
> +void kmsan_handle_dma(phys_addr_t phys, size_t size,
>  		      enum dma_data_direction dir)
>  {
>  	u64 page_offset, to_go, addr;
> +	struct page *page;
> +	void *kaddr;
>  
> -	if (PageHighMem(page))
> +	if (!pfn_valid(PHYS_PFN(phys)))
>  		return;

Not needed, the caller must pass in a phys that is kmap
compatible. Maybe just leave a comment. FWIW today this is also not
checking for P2P or DEVICE non-kmap struct pages either, so it should
be fine without checks.

> -	addr = (u64)page_address(page) + offset;
> +
> +	page = phys_to_page(phys);
> +	page_offset = offset_in_page(phys);
> +
>  	/*
>  	 * The kernel may occasionally give us adjacent DMA pages not belonging
>  	 * to the same allocation. Process them separately to avoid triggering
>  	 * internal KMSAN checks.
>  	 */
>  	while (size > 0) {
> -		page_offset = offset_in_page(addr);
>  		to_go = min(PAGE_SIZE - page_offset, (u64)size);
> +
> +		if (PageHighMem(page))
> +			/* Handle highmem pages using kmap */
> +			kaddr = kmap_local_page(page);

No need for the PageHighMem() - just always call kmap_local_pfn().

I'd also propose that any debug/sanitizer checks that the passed phys
is valid for kmap (eg pfn valid, not zone_device, etc) should be
inside the kmap code.

Jason


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC addresses for
 common operations
Thread-Topic: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC
 addresses for common operations
Thread-Index: AQHcB5d7cCAQRdJCgUKSzBGsZt4ytQ==
Date: Thu, 7 Aug 2025 12:33:30 +0000
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Currently, many common functions perform the same operations to calculate
GIC register addresses. This patch consolidates the similar code into
a separate helper function to improve maintainability and reduce duplicatio=
n.
This refactoring also simplifies the implementation of eSPI support in futu=
re
changes.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- no changes
---
 xen/arch/arm/gic-v3.c          | 99 ++++++++++++++++++++++------------
 xen/arch/arm/include/asm/irq.h |  1 +
 2 files changed, 67 insertions(+), 33 deletions(-)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index cd3e1acf79..8fd78aba44 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -445,17 +445,62 @@ static void gicv3_dump_state(const struct vcpu *v)
     }
 }
=20
+static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
+{
+    switch ( irqd->irq )
+    {
+    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+        case GICD_ICENABLER:
+        case GICD_ISPENDR:
+        case GICD_ICPENDR:
+        case GICD_ISACTIVER:
+        case GICD_ICACTIVER:
+            return (GICD_RDIST_SGI_BASE + offset);
+        case GICD_ICFGR:
+            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
+        case GICD_IPRIORITYR:
+            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
+        default:
+            break;
+        }
+    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+        case GICD_ICENABLER:
+        case GICD_ISPENDR:
+        case GICD_ICPENDR:
+        case GICD_ISACTIVER:
+        case GICD_ICACTIVER:
+            return (GICD + offset + (irqd->irq / 32) * 4);
+        case GICD_ICFGR:
+            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
+        case GICD_IROUTER:
+            return (GICD + GICD_IROUTER + irqd->irq * 8);
+        case GICD_IPRIORITYR:
+            return (GICD + GICD_IPRIORITYR + irqd->irq);
+        default:
+            break;
+        }
+    default:
+        break;
+    }
+
+    /* Something went wrong, we shouldn't be able to reach here */
+    panic("Invalid offset 0x%x for IRQ#%d", offset, irqd->irq);
+
+    return NULL;
+}
+
 static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_fo=
r_rwp)
 {
     u32 mask =3D 1U << (irqd->irq % 32);
-    void __iomem *base;
-
-    if ( irqd->irq < NR_GIC_LOCAL_IRQS )
-        base =3D GICD_RDIST_SGI_BASE;
-    else
-        base =3D GICD;
+    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
=20
-    writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
+    writel_relaxed(mask, addr);
=20
     if ( wait_for_rwp )
         gicv3_wait_for_rwp(irqd->irq);
@@ -463,15 +508,9 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u32 =
offset, bool wait_for_rwp)
=20
 static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset)
 {
-    void __iomem *base;
-    unsigned int irq =3D irqd->irq;
-
-    if ( irq >=3D NR_GIC_LOCAL_IRQS)
-        base =3D GICD + (irq / 32) * 4;
-    else
-        base =3D GICD_RDIST_SGI_BASE;
+    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
=20
-    return !!(readl(base + offset) & (1U << (irq % 32)));
+    return !!(readl(addr) & (1U << (irqd->irq % 32)));
 }
=20
 static void gicv3_unmask_irq(struct irq_desc *irqd)
@@ -558,30 +597,26 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cp=
u)
 static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type)
 {
     uint32_t cfg, actual, edgebit;
-    void __iomem *base;
-    unsigned int irq =3D desc->irq;
+    void __iomem *addr;
=20
     /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
-    ASSERT(irq >=3D NR_GIC_SGI);
+    ASSERT(desc->irq >=3D NR_GIC_SGI);
=20
     spin_lock(&gicv3.lock);
=20
-    if ( irq >=3D NR_GIC_LOCAL_IRQS)
-        base =3D GICD + GICD_ICFGR + (irq / 16) * 4;
-    else
-        base =3D GICD_RDIST_SGI_BASE + GICR_ICFGR1;
+    addr =3D get_addr_by_offset(desc, GICD_ICFGR);
=20
-    cfg =3D readl_relaxed(base);
+    cfg =3D readl_relaxed(addr);
=20
-    edgebit =3D 2u << (2 * (irq % 16));
+    edgebit =3D 2u << (2 * (desc->irq % 16));
     if ( type & IRQ_TYPE_LEVEL_MASK )
         cfg &=3D ~edgebit;
     else if ( type & IRQ_TYPE_EDGE_BOTH )
         cfg |=3D edgebit;
=20
-    writel_relaxed(cfg, base);
+    writel_relaxed(cfg, addr);
=20
-    actual =3D readl_relaxed(base);
+    actual =3D readl_relaxed(addr);
     if ( ( cfg & edgebit ) ^ ( actual & edgebit ) )
     {
         printk(XENLOG_WARNING "GICv3: WARNING: "
@@ -600,15 +635,12 @@ static void gicv3_set_irq_type(struct irq_desc *desc,=
 unsigned int type)
 static void gicv3_set_irq_priority(struct irq_desc *desc,
                                    unsigned int priority)
 {
-    unsigned int irq =3D desc->irq;
+    void __iomem *addr;
=20
     spin_lock(&gicv3.lock);
=20
-    /* Set priority */
-    if ( irq < NR_GIC_LOCAL_IRQS )
-        writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + =
irq);
-    else
-        writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
+    addr =3D get_addr_by_offset(desc, GICD_IPRIORITYR);
+    writeb_relaxed(priority, addr);
=20
     spin_unlock(&gicv3.lock);
 }
@@ -1273,6 +1305,7 @@ static void gicv3_irq_set_affinity(struct irq_desc *d=
esc, const cpumask_t *mask)
 {
     unsigned int cpu;
     uint64_t affinity;
+    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IROUTER);
=20
     ASSERT(!cpumask_empty(mask));
=20
@@ -1284,7 +1317,7 @@ static void gicv3_irq_set_affinity(struct irq_desc *d=
esc, const cpumask_t *mask)
     affinity &=3D ~GICD_IROUTER_SPI_MODE_ANY;
=20
     if ( desc->irq >=3D NR_GIC_LOCAL_IRQS )
-        writeq_relaxed_non_atomic(affinity, (GICD + GICD_IROUTER + desc->i=
rq * 8));
+        writeq_relaxed_non_atomic(affinity, addr);
=20
     spin_unlock(&gicv3.lock);
 }
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.=
h
index fce7e42a33..5bc6475eb4 100644
--- a/xen/arch/arm/include/asm/irq.h
+++ b/xen/arch/arm/include/asm/irq.h
@@ -29,6 +29,7 @@ struct arch_irq_desc {
  */
 #define NR_IRQS		1024
=20
+#define SPI_MAX_INTID   1019
 #define LPI_OFFSET      8192
=20
 /* LPIs are always numbered starting at 8192, so 0 is a good invalid case.=
 */
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for virq
 checks
Thread-Topic: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Index: AQHcB5d76MRh/Swq2EGu624C+G/Fbw==
Date: Thu, 7 Aug 2025 12:33:30 +0000
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Introduced two new helper functions for vGIC: vgic_is_valid_irq and
vgic_is_shared_irq. The functions are similar to the newly introduced
gic_is_valid_irq and gic_is_shared_irq, but they verify whether a vIRQ
is available for a specific domain, while GIC-specific functions
validate INTIDs for the real GIC hardware. For example, the GIC may
support all 992 SPI lines, but the domain may use only some part of them
(e.g., 640), depending on the highest IRQ number defined in the domain
configuration. Therefore, for vGIC-related code and checks, the
appropriate functions should be used. Also, updated the appropriate
checks to use these new helper functions.

The purpose of introducing new helper functions for vGIC is essentially
the same as for GIC: to avoid potential confusion with GIC-related
checks and to consolidate similar code into separate functions, which
can be more easily extended by additional conditions, e.g., when
implementing extended SPI interrupts.

Only the validation change in vgic_inject_irq may affect existing
functionality, as it currently checks whether the vIRQ is less than or
equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
first SPI), the check should behave consistently with similar logic in
other places and should check if the vIRQ number is less than
vgic_num_irqs. The remaining changes, which replace open-coded checks
with the use of these new helper functions, do not introduce any
functional changes, as the helper functions follow the current vIRQ
index verification logic.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- introduced this patch
---
 xen/arch/arm/gic.c              |  3 +--
 xen/arch/arm/include/asm/vgic.h |  7 +++++++
 xen/arch/arm/irq.c              |  4 ++--
 xen/arch/arm/vgic.c             | 10 ++++++++--
 4 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index eb0346a898..47fccf21d8 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -133,8 +133,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned i=
nt virq,
=20
     ASSERT(spin_is_locked(&desc->lock));
     /* Caller has already checked that the IRQ is an SPI */
-    ASSERT(virq >=3D 32);
-    ASSERT(virq < vgic_num_irqs(d));
+    ASSERT(vgic_is_shared_irq(d, virq));
     ASSERT(!is_lpi(virq));
=20
     ret =3D vgic_connect_hw_irq(d, NULL, virq, desc, true);
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 35c0c6a8b0..45201f4ca5 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -335,6 +335,13 @@ extern void vgic_check_inflight_irqs_pending(struct vc=
pu *v,
 /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
 #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
=20
+extern bool vgic_is_valid_irq(struct domain *d, unsigned int virq);
+
+static inline bool vgic_is_shared_irq(struct domain *d, unsigned int virq)
+{
+    return (virq >=3D NR_LOCAL_IRQS && vgic_is_valid_irq(d, virq));
+}
+
 /*
  * Allocate a guest VIRQ
  *  - spi =3D=3D 0 =3D> allocate a PPI. It will be the same on every vCPU
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 12c70d02cc..50e57aaea7 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -442,7 +442,7 @@ int route_irq_to_guest(struct domain *d, unsigned int v=
irq,
     unsigned long flags;
     int retval =3D 0;
=20
-    if ( virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_valid_irq(d, virq) )
     {
         printk(XENLOG_G_ERR
                "the vIRQ number %u is too high for domain %u (max =3D %u)\=
n",
@@ -560,7 +560,7 @@ int release_guest_irq(struct domain *d, unsigned int vi=
rq)
     int ret;
=20
     /* Only SPIs are supported */
-    if ( virq < NR_LOCAL_IRQS || virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_shared_irq(d, virq) )
         return -EINVAL;
=20
     desc =3D vgic_get_hw_irq_desc(d, NULL, virq);
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index c563ba93af..48fbaf56fb 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -24,6 +24,12 @@
 #include 
 #include 
=20
+
+bool vgic_is_valid_irq(struct domain *d, unsigned int virq)
+{
+    return virq < vgic_num_irqs(d);
+}
+
 static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
                                                   unsigned int rank)
 {
@@ -582,7 +588,7 @@ void vgic_inject_irq(struct domain *d, struct vcpu *v, =
unsigned int virq,
     if ( !v )
     {
         /* The IRQ needs to be an SPI if no vCPU is specified. */
-        ASSERT(virq >=3D 32 && virq <=3D vgic_num_irqs(d));
+        ASSERT(vgic_is_shared_irq(d, virq));
=20
         v =3D vgic_get_target_vcpu(d->vcpu[0], virq);
     };
@@ -659,7 +665,7 @@ bool vgic_emulate(struct cpu_user_regs *regs, union hsr=
 hsr)
=20
 bool vgic_reserve_virq(struct domain *d, unsigned int virq)
 {
-    if ( virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_valid_irq(d, virq) )
         return false;
=20
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI range
Thread-Topic: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcB5d7kgaRrTB4eUK2JDUmO9y7Hw==
Date: Thu, 7 Aug 2025 12:33:31 +0000
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Currently, Xen does not support eSPI interrupts, leading
to a data abort when such interrupts are defined in the DTS.

This patch introduces a separate array to initialize up to
1024 interrupt descriptors in the eSPI range and adds the
necessary defines and helper function. These changes lay the
groundwork for future implementation of full eSPI interrupt
support. As this GICv3.1 feature is not required by all vendors,
all changes are guarded by ifdefs, depending on the corresponding
Kconfig option.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
- remove unnecessary comment for nr_irqs initialization
---
 xen/arch/arm/Kconfig           |  9 +++++++++
 xen/arch/arm/include/asm/irq.h | 25 +++++++++++++++++++++++++
 xen/arch/arm/irq.c             | 26 ++++++++++++++++++++++++++
 3 files changed, 60 insertions(+)

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 17df147b25..08073ece1f 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -135,6 +135,15 @@ config GICV3
 	  Driver for the ARM Generic Interrupt Controller v3.
 	  If unsure, use the default setting.
=20
+config GICV3_ESPI
+	bool "Extended SPI range support"
+	depends on GICV3 && !NEW_VGIC
+	default y
+	help
+	  Allow Xen and domains to use interrupt numbers from the extended SPI
+	  range, from 4096 to 5119. This feature is introduced in GICv3.1
+	  architecture.
+
 config HAS_ITS
         bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORT=
ED
         depends on GICV3 && !NEW_VGIC && !ARM_32
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.=
h
index 5bc6475eb4..acebc3d42f 100644
--- a/xen/arch/arm/include/asm/irq.h
+++ b/xen/arch/arm/include/asm/irq.h
@@ -32,6 +32,14 @@ struct arch_irq_desc {
 #define SPI_MAX_INTID   1019
 #define LPI_OFFSET      8192
=20
+#ifdef CONFIG_GICV3_ESPI
+#define ESPI_BASE_INTID 4096
+#define ESPI_MAX_INTID  5119
+
+#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
+#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
+#endif
+
 /* LPIs are always numbered starting at 8192, so 0 is a good invalid case.=
 */
 #define INVALID_LPI     0
=20
@@ -39,7 +47,15 @@ struct arch_irq_desc {
 #define INVALID_IRQ     1023
=20
 extern const unsigned int nr_irqs;
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * This will also cover the eSPI range, as some critical devices
+ * for booting Xen (e.g., serial) may use this type of interrupts.
+ */
+#define nr_static_irqs (ESPI_MAX_INTID + 1)
+#else
 #define nr_static_irqs NR_IRQS
+#endif
=20
 struct irq_desc;
 struct irqaction;
@@ -55,6 +71,15 @@ static inline bool is_lpi(unsigned int irq)
     return irq >=3D LPI_OFFSET;
 }
=20
+static inline bool is_espi(unsigned int irq)
+{
+#ifdef CONFIG_GICV3_ESPI
+    return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID);
+#else
+    return false;
+#endif
+}
+
 #define domain_pirq_to_irq(d, pirq) (pirq)
=20
 bool is_assignable_irq(unsigned int irq);
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 50e57aaea7..9bc72fbbc9 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -19,7 +19,11 @@
 #include 
 #include 
=20
+#ifdef CONFIG_GICV3_ESPI
+const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1;
+#else
 const unsigned int nr_irqs =3D NR_IRQS;
+#endif
=20
 static unsigned int local_irqs_type[NR_LOCAL_IRQS];
 static DEFINE_SPINLOCK(local_irqs_type_lock);
@@ -46,6 +50,9 @@ void irq_end_none(struct irq_desc *irq)
 }
=20
 static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
+#ifdef CONFIG_GICV3_ESPI
+static irq_desc_t espi_desc[NR_IRQS];
+#endif
 static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc);
=20
 struct irq_desc *__irq_to_desc(unsigned int irq)
@@ -53,6 +60,11 @@ struct irq_desc *__irq_to_desc(unsigned int irq)
     if ( irq < NR_LOCAL_IRQS )
         return &this_cpu(local_irq_desc)[irq];
=20
+#ifdef CONFIG_GICV3_ESPI
+    if ( is_espi(irq) )
+        return &espi_desc[ESPI_INTID2IDX(irq)];
+#endif
+
     return &irq_desc[irq-NR_LOCAL_IRQS];
 }
=20
@@ -79,6 +91,20 @@ static int __init init_irq_data(void)
         desc->action  =3D NULL;
     }
=20
+#ifdef CONFIG_GICV3_ESPI
+    for ( irq =3D ESPI_BASE_INTID; irq <=3D ESPI_MAX_INTID; irq++ )
+    {
+        struct irq_desc *desc =3D irq_to_desc(irq);
+        int rc =3D init_one_irq_desc(desc);
+
+        if ( rc )
+            return rc;
+
+        desc->irq =3D irq;
+        desc->action  =3D NULL;
+    }
+#endif
+
     return 0;
 }
=20
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Andrew Cooper
	, Anthony PERARD , Jan
 Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: [PATCH v2 00/10] Introduce eSPI support
Thread-Topic: [PATCH v2 00/10] Introduce eSPI support
Thread-Index: AQHcB5d6CNAyJbck6EKQNoQgtljZhg==
Date: Thu, 7 Aug 2025 12:33:29 +0000
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Hello everyone!

### Background
Unlike the Linux kernel, which has supported extended shared peripheral
interrupts (eSPIs) since 2019 [1], Xen currently lacks support for this
interrupt range. For SoCs with GICv3.1+, this feature may be essential
because critical devices, such as consoles required for booting Xen
itself, may rely on eSPIs. Additionally, these platforms require eSPI
support for fully functional domains, as any device using eSPIs cannot
currently be used with Xen setups. Without eSPI support, Xen cannot run
properly on these platforms, significantly limiting its usability on
modern ARM hardware.

This patch series adds support for the extended shared peripheral
interrupt (eSPI) range (INTIDs 4096-5119 [2](ranges of INTIDs)) for Xen
and guest domains. The implementation uses a generic approach to handle
eSPIs, similar to regular SPIs, while maintaining compatibility with the
existing SPI range. Functionality remains unchanged for setups that do
not require eSPIs.

The series includes:
1) General refactoring of common IRQ operations with GIC registers to
improve code readability, simplify further maintenance and prepare the
key functions for eSPI implementation.
2) Introducing a new Kconfig option (default y) to enable or disable
eSPI support. Disabling this option prevents unnecessary resource
allocation for setups that do not require eSPIs.
3) Adding additional resources to store required information and operate
with up to 1024 interrupts from eSPI range.
4) Adjusting assertions and checks to pass verification for INTIDs in
the eSPI range.
5) Configuration of eSPI-specific registers during GIC initialization
for systems with GICv3.1+ hardware.
6) Enables eSPI MMIO emulation for vGIC, allowing guest domains to
access and operate within the eSPI's INTIDs.

[1] https://github.com/torvalds/linux/commit/211bddd210a6746e4fdfa9b6cdfbdb=
15026530a7
[2] https://developer.arm.com/documentation/198123/0302/Arm-GIC-fundamental=
s?lang=3Den

Changes in V2:
- added 2 more patches to implement helper
  functions for gic/vgic:
  xen/arm: gic: implement helper functions for INTID checks
  xen/arm: vgic: implement helper functions for virq checks
- removed 2 patches:
  xen/arm/irq: allow assignment/releasing of eSPI interrupts
  xen/arm: gic/irq: permit routing of eSPI interrupts to Xen and domains
  since their functionality can be moved to appropriate patches after
  introducing patches with helper functions
- individual changes in patches

Link on V1:
- https://lists.xenproject.org/archives/html/xen-devel/2025-07/msg01809.htm=
l

Leonid Komarianskyi (10):
  xen/arm: gicv3: refactor obtaining GIC addresses for common operations
  xen/arm: gic: implement helper functions for INTID checks
  xen/arm: vgic: implement helper functions for virq checks
  xen/arm/irq: add handling for IRQs in the eSPI range
  xen/arm: gicv3: implement handling of GICv3.1 eSPI
  xen/arm/irq: allow eSPI processing in the do_IRQ function
  xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow eSPI processing
  xen/arm: vgic: add resource management for extended SPIs
  xen/arm: domain_build: adjust Dom0 IRQ handling to support eSPIs
  xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers

 xen/arch/arm/Kconfig                   |   9 +
 xen/arch/arm/domain_build.c            |  10 +
 xen/arch/arm/gic-v3.c                  | 172 +++++++++++++----
 xen/arch/arm/gic.c                     |   7 +-
 xen/arch/arm/include/asm/gic.h         |  26 +++
 xen/arch/arm/include/asm/gic_v3_defs.h |  35 +++-
 xen/arch/arm/include/asm/irq.h         |  26 +++
 xen/arch/arm/include/asm/vgic.h        |  36 ++++
 xen/arch/arm/irq.c                     |  34 +++-
 xen/arch/arm/vgic-v3.c                 | 248 ++++++++++++++++++++++++-
 xen/arch/arm/vgic.c                    | 155 +++++++++++++++-
 11 files changed, 711 insertions(+), 47 deletions(-)

--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 02/10] xen/arm: gic: implement helper functions for INTID
 checks
Thread-Topic: [PATCH v2 02/10] xen/arm: gic: implement helper functions for
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Introduced two new helper functions: gic_is_valid_irq and
gic_is_shared_irq. The first function helps determine whether an IRQ
number is less than the number of lines supported by hardware. The
second function additionally checks if the IRQ number falls within the
SPI range. Also, updated the appropriate checks to use these new helper
functions.

The current checks for the real GIC are very similar to those for the
vGIC but serve a different purpose. For GIC-related code, the interrupt
numbers should be validated based on whether the hardware can operate
with such interrupts. On the other hand, for the vGIC, the indexes must
also be verified to ensure they are available for a specific domain. The
first reason for introducing these helper functions is to avoid
potential confusion with vGIC-related checks. The second reason is to
consolidate similar code into separate functions, which can be more
easily extended by additional conditions, e.g., when implementing
extended SPI interrupts.

The changes, which replace open-coded checks with the use of the new
helper functions, do not introduce any functional changes, as the helper
functions follow the current IRQ index verification logic.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- introduced this patch
---
 xen/arch/arm/gic.c             | 2 +-
 xen/arch/arm/include/asm/gic.h | 9 +++++++++
 xen/arch/arm/irq.c             | 2 +-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index e80fe0ca24..eb0346a898 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -111,7 +111,7 @@ static void gic_set_irq_priority(struct irq_desc *desc,=
 unsigned int priority)
 void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority)
 {
     ASSERT(priority <=3D 0xff);     /* Only 8 bits of priority */
-    ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that =
don't exist */
+    ASSERT(gic_is_valid_irq(desc->irq));/* Can't route interrupts that don=
't exist */
     ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
     ASSERT(spin_is_locked(&desc->lock));
=20
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.=
h
index 541f0eeb80..ac0b7b783e 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -306,6 +306,15 @@ extern void gic_dump_vgic_info(struct vcpu *v);
=20
 /* Number of interrupt lines */
 extern unsigned int gic_number_lines(void);
+static inline bool gic_is_valid_irq(unsigned int irq)
+{
+    return irq < gic_number_lines();
+}
+
+static inline bool gic_is_shared_irq(unsigned int irq)
+{
+    return (irq >=3D NR_LOCAL_IRQS && gic_is_valid_irq(irq));
+}
=20
 /* IRQ translation function for the device tree */
 int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 03fbb90c6c..12c70d02cc 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -415,7 +415,7 @@ err:
 bool is_assignable_irq(unsigned int irq)
 {
     /* For now, we can only route SPIs to the guest */
-    return (irq >=3D NR_LOCAL_IRQS) && (irq < gic_number_lines());
+    return gic_is_shared_irq(irq);
 }
=20
 /*
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 05/10] xen/arm: gicv3: implement handling of GICv3.1 eSPI
Thread-Topic: [PATCH v2 05/10] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
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Date: Thu, 7 Aug 2025 12:33:31 +0000
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Introduced appropriate register definitions, helper macros,
and initialization of required GICv3.1 distributor registers
to support eSPI. This type of interrupt is handled in the
same way as regular SPI interrupts, with the following
differences:

1) eSPIs can have up to 1024 interrupts, starting from the
beginning of the range, whereas regular SPIs use INTIDs from
32 to 1019, totaling 988 interrupts;
2) eSPIs start at INTID 4096, necessitating additional interrupt
index conversion during register operations.

In case if appropriate config is disabled, or GIC HW doesn't
support eSPI, the existing functionality will remain the same.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- move gic_number_espis function from
  [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
  to use it in the newly introduced gic_is_valid_espi
- add gic_is_valid_espi which checks if IRQ number is in supported
  by HW eSPI range
- update gic_is_valid_irq conditions to allow operations with eSPIs
---
 xen/arch/arm/gic-v3.c                  | 73 ++++++++++++++++++++++++++
 xen/arch/arm/include/asm/gic.h         | 17 ++++++
 xen/arch/arm/include/asm/gic_v3_defs.h | 33 ++++++++++++
 3 files changed, 123 insertions(+)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 8fd78aba44..a0e8ee1a1e 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_des=
c *irqd, u32 offset)
         default:
             break;
         }
+#ifdef CONFIG_GICV3_ESPI
+    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
+    {
+        u32 irq_index =3D ESPI_INTID2IDX(irqd->irq);
+
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
+        case GICD_ICENABLER:
+            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
+        case GICD_ISPENDR:
+            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
+        case GICD_ICPENDR:
+            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
+        case GICD_ISACTIVER:
+            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
+        case GICD_ICACTIVER:
+            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
+        case GICD_ICFGR:
+            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
+        case GICD_IROUTER:
+            return (GICD + GICD_IROUTERnE + irq_index * 8);
+        case GICD_IPRIORITYR:
+            return (GICD + GICD_IPRIORITYRnE + irq_index);
+        default:
+            break;
+        }
+    }
+#endif
     default:
         break;
     }
@@ -645,6 +675,40 @@ static void gicv3_set_irq_priority(struct irq_desc *de=
sc,
     spin_unlock(&gicv3.lock);
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+unsigned int gic_number_espis(void)
+{
+    return gic_hw_ops->info->nr_espi;
+}
+
+static void gicv3_dist_espi_common_init(uint32_t type)
+{
+    unsigned int espi_nr;
+    int i;
+
+    espi_nr =3D min(1024U, GICD_TYPER_ESPIS_NUM(type));
+    gicv3_info.nr_espi =3D espi_nr;
+    /* The GIC HW doesn't support eSPI, so we can leave from here */
+    if ( gicv3_info.nr_espi =3D=3D 0 )
+        return;
+
+    for ( i =3D 0; i < espi_nr; i +=3D 16 )
+        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
+
+    for ( i =3D 0; i < espi_nr; i +=3D 4 )
+        writel_relaxed(GIC_PRI_IRQ_ALL, GICD + GICD_IPRIORITYRnE + (i / 4)=
 * 4);
+
+    for ( i =3D 0; i < espi_nr; i +=3D 32 )
+    {
+        writel_relaxed(0xffffffffU, GICD + GICD_ICENABLERnE + (i / 32) * 4=
);
+        writel_relaxed(0xffffffffU, GICD + GICD_ICACTIVERnE + (i / 32) * 4=
);
+    }
+
+    for ( i =3D 0; i < espi_nr; i +=3D 32 )
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) * =
4);
+}
+#endif
+
 static void __init gicv3_dist_init(void)
 {
     uint32_t type;
@@ -690,6 +754,10 @@ static void __init gicv3_dist_init(void)
     for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i +=3D 32 )
         writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4)=
;
=20
+#ifdef CONFIG_GICV3_ESPI
+    gicv3_dist_espi_common_init(type);
+#endif
+
     gicv3_dist_wait_for_rwp();
=20
     /* Turn on the distributor */
@@ -703,6 +771,11 @@ static void __init gicv3_dist_init(void)
=20
     for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
         writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8);
+
+#ifdef CONFIG_GICV3_ESPI
+    for ( i =3D 0; i < gicv3_info.nr_espi; i++ )
+        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * 8)=
;
+#endif
 }
=20
 static int gicv3_enable_redist(void)
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.=
h
index ac0b7b783e..2f570abf70 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -306,8 +306,21 @@ extern void gic_dump_vgic_info(struct vcpu *v);
=20
 /* Number of interrupt lines */
 extern unsigned int gic_number_lines(void);
+#ifdef CONFIG_GICV3_ESPI
+extern unsigned int gic_number_espis(void);
+
+static inline bool gic_is_valid_espi(unsigned int irq)
+{
+    return (irq >=3D ESPI_BASE_INTID && irq < ESPI_IDX2INTID(gic_number_es=
pis()));
+}
+#endif
+
 static inline bool gic_is_valid_irq(unsigned int irq)
 {
+#ifdef CONFIG_GICV3_ESPI
+    if ( gic_is_valid_espi(irq) )
+        return true;
+#endif
     return irq < gic_number_lines();
 }
=20
@@ -325,6 +338,10 @@ struct gic_info {
     enum gic_version hw_version;
     /* Number of GIC lines supported */
     unsigned int nr_lines;
+#ifdef CONFIG_GICV3_ESPI
+    /* Number of GIC eSPI supported */
+    unsigned int nr_espi;
+#endif
     /* Number of LR registers */
     uint8_t nr_lrs;
     /* Maintenance irq number */
diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/=
asm/gic_v3_defs.h
index 2af093e774..7f769b38e3 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -37,6 +37,39 @@
 #define GICD_IROUTER1019             (0x7FD8)
 #define GICD_PIDR2                   (0xFFE8)
=20
+#ifdef CONFIG_GICV3_ESPI
+/* Additional registers for GICv3.1 */
+#define GICD_IGROUPRnE               (0x1000)
+#define GICD_IGROUPRnEN              (0x107C)
+#define GICD_ISENABLERnE             (0x1200)
+#define GICD_ISENABLERnEN            (0x127C)
+#define GICD_ICENABLERnE             (0x1400)
+#define GICD_ICENABLERnEN            (0x147C)
+#define GICD_ISPENDRnE               (0x1600)
+#define GICD_ISPENDRnEN              (0x167C)
+#define GICD_ICPENDRnE               (0x1800)
+#define GICD_ICPENDRnEN              (0x187C)
+#define GICD_ISACTIVERnE             (0x1A00)
+#define GICD_ISACTIVERnEN            (0x1A7C)
+#define GICD_ICACTIVERnE             (0x1C00)
+#define GICD_ICACTIVERnEN            (0x1C7C)
+#define GICD_IPRIORITYRnE            (0x2000)
+#define GICD_IPRIORITYRnEN           (0x23FC)
+#define GICD_ICFGRnE                 (0x3000)
+#define GICD_ICFGRnEN                (0x30FC)
+#define GICD_IROUTERnE               (0x8000)
+#define GICD_IROUTERnEN              (0x9FFC)
+
+#define GICD_TYPER_ESPI_SHIFT        8
+#define GICD_TYPER_ESPI_RANGE_SHIFT  27
+#define GICD_TYPER_ESPI_RANGE_MASK   (0x1F)
+#define GICD_TYPER_ESPI              (1U << GICD_TYPER_ESPI_SHIFT)
+#define GICD_TYPER_ESPI_RANGE(typer) ((((typer) & GICD_TYPER_ESPI_RANGE_MA=
SK) + 1) * 32)
+#define GICD_TYPER_ESPIS_NUM(typer)    \
+        (((typer) & GICD_TYPER_ESPI) ? \
+        GICD_TYPER_ESPI_RANGE((typer) >> GICD_TYPER_ESPI_RANGE_SHIFT) : 0)
+#endif
+
 /* Common between GICD_PIDR2 and GICR_PIDR2 */
 #define GIC_PIDR2_ARCH_MASK         (0xf0)
 #define GIC_PIDR2_ARCH_GICv3        (0x30)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 07/10] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow
 eSPI processing
Thread-Topic: [PATCH v2 07/10] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
 allow eSPI processing
Thread-Index: AQHcB5d8lU0HcDjyxEOVNNx+lAhf9w==
Date: Thu, 7 Aug 2025 12:33:32 +0000
Message-ID:
 
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To properly deactivate guest interrupts and allow them to be retriggered
after the initial trigger, the LR needs to be updated. The current
implementation ignores interrupts outside the range specified by the mask
0x3FF, which only covers IRQ numbers up to 1023. To enable processing of
eSPI interrupts, this patch updates the mask to 0x13FF.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- remove unnecessary CONFIG_GICV3_ESPI ifdef guard
---
 xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/=
asm/gic_v3_defs.h
index 7f769b38e3..4f27708a70 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -206,7 +206,7 @@
 #define ICH_LR_VIRTUAL_SHIFT         0
 #define ICH_LR_CPUID_MASK            0x7
 #define ICH_LR_CPUID_SHIFT           10
-#define ICH_LR_PHYSICAL_MASK         0x3ff
+#define ICH_LR_PHYSICAL_MASK         0x13ff
 #define ICH_LR_PHYSICAL_SHIFT        32
 #define ICH_LR_STATE_MASK            0x3
 #define ICH_LR_STATE_SHIFT           62
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 06/10] xen/arm/irq: allow eSPI processing in the do_IRQ
 function
Thread-Topic: [PATCH v2 06/10] xen/arm/irq: allow eSPI processing in the
 do_IRQ function
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Date: Thu, 7 Aug 2025 12:33:32 +0000
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The do_IRQ() function is the main handler for processing IRQs.
Currently, due to restrictive checks, it does not process interrupt
numbers greater than 1024. This patch updates the condition to allow
the handling of interrupts from the eSPI range.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- no changes
---
 xen/arch/arm/gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 47fccf21d8..7186c3d40a 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -341,7 +341,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_f=
iq)
         /* Reading IRQ will ACK it */
         irq =3D gic_hw_ops->read_irq();
=20
-        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) )
+        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) || is_espi(=
irq) )
         {
             isb();
             do_IRQ(regs, irq, is_fiq);
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling to
 support eSPIs
Thread-Topic: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
 to support eSPIs
Thread-Index: AQHcB5d9D2bB2ytT+0KvuTkMlpIiHw==
Date: Thu, 7 Aug 2025 12:33:34 +0000
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The Dom0 configuration logic in create_dom0() has been updated
to account for extended SPIs when supported by the hardware and
enabled with CONFIG_GICV3_ESPI. These changes ensure the proper
calculation of the maximum number of SPIs and eSPIs available for Dom0.

When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is
enabled, the maximum number of eSPI interrupts is calculated using
the ESPI_BASE_INTID offset (4096) and limited at 1024, with 32 IRQs
subtracted. To ensure compatibility with non-Dom0 domains, this
adjustment is applied by the toolstack during domain creation, while
for Dom0 it is handled directly during VGIC initialization. If eSPIs
are not supported, the calculation defaults to using the standard SPI
range, with a maximum value of 992 interrupt lines as it works now.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- no changes
---
 xen/arch/arm/domain_build.c     | 10 ++++++++++
 xen/arch/arm/include/asm/vgic.h | 11 +++++++++++
 2 files changed, 21 insertions(+)

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index d91a71acfd..fa5abf2dfb 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2055,6 +2055,16 @@ void __init create_dom0(void)
     /* The vGIC for DOM0 is exactly emulating the hardware GIC */
     dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
     dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS;
+#ifdef CONFIG_GICV3_ESPI
+    /*
+     * Check if the hardware supports extended SPIs (even if the appropria=
te config is set).
+     * If not, the common SPI range will be used. Otherwise overwrite the =
nr_spis with the
+     * maximum available INTID from eSPI range. In that case, the number o=
f regular SPIs will
+     * be adjusted to the maximum value during vGIC initialization.
+     */
+    if ( gic_number_espis() > 0 )
+        dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_ESPIS;
+#endif
     dom0_cfg.arch.tee_type =3D tee_get_type();
     dom0_cfg.max_vcpus =3D dom0_max_vcpus();
=20
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 9fa4523018..117b3aa92c 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -353,6 +353,17 @@ extern void vgic_check_inflight_irqs_pending(struct vc=
pu *v,
 /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
 #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
=20
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * Returns the maximum eSPI INTID subtracted by 32. For non-Dom0 domains, =
the
+ * toolstack applies the same adjustment to cover local IRQs. We will add =
back
+ * this value during VGIC initialization. This ensures consistent handling=
 for Dom0
+ * and other domains. For the regular SPI range interrupts in this case, t=
he maximum
+ * value of VGIC_DEF_NR_SPIS will be used.
+ */
+#define VGIC_DEF_NR_ESPIS (ESPI_BASE_INTID + min(gic_number_espis(), 1024U=
) - 32)
+#endif
+
 extern bool vgic_is_valid_irq(struct domain *d, unsigned int virq);
=20
 static inline bool vgic_is_shared_irq(struct domain *d, unsigned int virq)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
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Date: Thu, 7 Aug 2025 12:33:34 +0000
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Implemented support for GICv3.1 extended SPI registers for vGICv3,
allowing the emulation of eSPI-specific behavior for guest domains.
The implementation includes read and write emulation for eSPI-related
registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
following a similar approach to the handling of regular SPIs.

The eSPI registers, previously located in reserved address ranges,
are now adjusted to support MMIO read and write operations correctly
when CONFIG_GICV3_ESPI is enabled.

The availability of eSPIs and the number of emulated extended SPIs
for guest domains is reported by setting the appropriate bits in the
GICD_TYPER register, based on the number of eSPIs requested by the
domain and supported by the hardware. In cases where the configuration
option is disabled, the hardware does not support eSPIs, or the domain
does not request such interrupts, the functionality remains unchanged.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- add missing rank index conversion for pending and inflight irqs
---
 xen/arch/arm/vgic-v3.c | 248 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 245 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 4369c55177..1cacbb6e43 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -111,7 +111,7 @@ static uint64_t vgic_fetch_irouter(struct vgic_irq_rank=
 *rank,
  * Note the offset will be aligned to the appropriate boundary.
  */
 static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *ran=
k,
-                               unsigned int offset, uint64_t irouter)
+                               unsigned int offset, uint64_t irouter, bool=
 espi)
 {
     struct vcpu *new_vcpu, *old_vcpu;
     unsigned int virq;
@@ -123,7 +123,8 @@ static void vgic_store_irouter(struct domain *d, struct=
 vgic_irq_rank *rank,
      * The IROUTER0-31, used for SGIs/PPIs, are reserved and should
      * never call this function.
      */
-    ASSERT(virq >=3D 32);
+    if ( !espi )
+        ASSERT(virq >=3D 32);
=20
     /* Get the index in the rank */
     offset =3D virq & INTERRUPT_RANK_MASK;
@@ -146,6 +147,11 @@ static void vgic_store_irouter(struct domain *d, struc=
t vgic_irq_rank *rank,
     /* Only migrate the IRQ if the target vCPU has changed */
     if ( new_vcpu !=3D old_vcpu )
     {
+#ifdef CONFIG_GICV3_ESPI
+        /* Convert virq index to eSPI range */
+        if ( espi )
+            virq =3D ESPI_IDX2INTID(virq);
+#endif
         if ( vgic_migrate_irq(old_vcpu, new_vcpu, virq) )
             write_atomic(&rank->vcpu[offset], new_vcpu->vcpu_id);
     }
@@ -685,6 +691,9 @@ static int __vgic_v3_distr_common_mmio_read(const char =
*name, struct vcpu *v,
     {
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+#endif
         /* We do not implement security extensions for guests, read zero *=
/
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
         goto read_as_zero;
@@ -710,11 +719,19 @@ static int __vgic_v3_distr_common_mmio_read(const cha=
r *name, struct vcpu *v,
     /* Read the pending status of an IRQ via GICD/GICR is not supported */
     case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
     case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+#endif
         goto read_as_zero;
=20
     /* Read the active status of an IRQ via GICD/GICR is not supported */
     case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
     case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+#endif
         goto read_as_zero;
=20
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
@@ -752,6 +769,61 @@ static int __vgic_v3_distr_common_mmio_read(const char=
 *name, struct vcpu *v,
         return 1;
     }
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL ) goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        *r =3D vreg_reg32_extract(rank->ienable, info);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL ) goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        *r =3D vreg_reg32_extract(rank->ienable, info);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    {
+        uint32_t ipriorityr;
+        uint8_t rank_index;
+
+        if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD ) goto b=
ad_width;
+        rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DABT_=
WORD);
+        if ( rank =3D=3D NULL ) goto read_as_zero;
+        rank_index =3D REG_RANK_INDEX(8, reg - GICD_IPRIORITYRnE, DABT_WOR=
D);
+
+        vgic_lock_rank(v, rank, flags);
+        ipriorityr =3D ACCESS_ONCE(rank->ipriorityr[rank_index]);
+        vgic_unlock_rank(v, rank, flags);
+
+        *r =3D vreg_reg32_extract(ipriorityr, info);
+
+        return 1;
+    }
+
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+    {
+        uint32_t icfgr;
+
+        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WORD)=
;
+        if ( rank =3D=3D NULL ) goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        icfgr =3D rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE, DABT_WO=
RD)];
+        vgic_unlock_rank(v, rank, flags);
+
+        *r =3D vreg_reg32_extract(icfgr, info);
+
+        return 1;
+    }
+#endif
+
     default:
         printk(XENLOG_G_ERR
                "%pv: %s: unhandled read r%d offset %#08x\n",
@@ -782,6 +854,9 @@ static int __vgic_v3_distr_common_mmio_write(const char=
 *name, struct vcpu *v,
     {
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+#endif
         /* We do not implement security extensions for guests, write ignor=
e */
         goto write_ignore_32;
=20
@@ -871,6 +946,87 @@ static int __vgic_v3_distr_common_mmio_write(const cha=
r *name, struct vcpu *v,
         vgic_unlock_rank(v, rank, flags);
         return 1;
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL ) goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        tr =3D rank->ienable;
+        vreg_reg32_setbits(&rank->ienable, r, info);
+        vgic_enable_irqs(v, (rank->ienable) & (~tr), EXT_RANK_IDX2NUM(rank=
->index));
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL ) goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        tr =3D rank->ienable;
+        vreg_reg32_clearbits(&rank->ienable, r, info);
+        vgic_disable_irqs(v, (~rank->ienable) & tr, EXT_RANK_IDX2NUM(rank-=
>index));
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISPENDRnE, DABT_WOR=
D);
+        if ( rank =3D=3D NULL ) goto write_ignore;
+
+        vgic_set_irqs_pending(v, r, EXT_RANK_IDX2NUM(rank->index));
+
+        return 1;
+
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICPENDRnE, DABT_WOR=
D);
+        if ( rank =3D=3D NULL ) goto write_ignore;
+
+        vgic_check_inflight_irqs_pending(v, EXT_RANK_IDX2NUM(rank->index),=
 r);
+
+        goto write_ignore;
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
+        printk(XENLOG_G_ERR
+               "%pv: %s: unhandled word write %#"PRIregister" to ISACTIVER=
%d\n",
+               v, name, r, reg - GICD_ISACTIVERnE);
+        return 0;
+
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+        printk(XENLOG_G_ERR
+               "%pv: %s: unhandled word write %#"PRIregister" to ICACTIVER=
%d\n",
+               v, name, r, reg - GICD_ICACTIVER);
+        goto write_ignore_32;
+
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    {
+        uint32_t *ipriorityr, priority;
+
+        if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD ) goto b=
ad_width;
+        rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DABT_=
WORD);
+        if ( rank =3D=3D NULL ) goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        ipriorityr =3D &rank->ipriorityr[REG_RANK_INDEX(8, reg - GICD_IPRI=
ORITYRnE,
+                                                      DABT_WORD)];
+        priority =3D ACCESS_ONCE(*ipriorityr);
+        vreg_reg32_update(&priority, r, info);
+        ACCESS_ONCE(*ipriorityr) =3D priority;
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+    }
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WORD)=
;
+        if ( rank =3D=3D NULL ) goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE=
,
+                                                     DABT_WORD)],
+                          r, info);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+#endif
+
     default:
         printk(XENLOG_G_ERR
                "%pv: %s: unhandled write r%d=3D%"PRIregister" offset %#08x=
\n",
@@ -1129,6 +1285,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
             typer |=3D GICD_TYPE_LPIS;
=20
         typer |=3D (v->domain->arch.vgic.intid_bits - 1) << GICD_TYPE_ID_B=
ITS_SHIFT;
+#ifdef CONFIG_GICV3_ESPI
+        if ( v->domain->arch.vgic.nr_espis > 0 )
+        {
+            /* Set eSPI support bit for the domain */
+            typer |=3D GICD_TYPER_ESPI;
+            /* Set ESPI range bits */
+            typer |=3D (DIV_ROUND_UP(v->domain->arch.vgic.nr_espis, 32) - =
1)
+                       << GICD_TYPER_ESPI_RANGE_SHIFT;
+        }
+#endif
=20
         *r =3D vreg_reg32_extract(typer, info);
=20
@@ -1194,6 +1360,18 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
     case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+#endif
         /*
          * Above all register are common with GICR and GICD
          * Manage in common
@@ -1216,7 +1394,11 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
         /* Replaced with GICR_ISPENDR0. So ignore write */
         goto read_as_zero_32;
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(0x3100, 0x60FC):
+#else
     case VRANGE32(0x0F30, 0x60FC):
+#endif
         goto read_reserved;
=20
     case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
@@ -1235,8 +1417,30 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
=20
         return 1;
     }
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
+    {
+        uint64_t irouter;
+
+        if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 64, gicd_reg - GICD_IROUTERnE,
+                                DABT_DOUBLE_WORD);
+        if ( rank =3D=3D NULL ) goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTERnE);
+        vgic_unlock_rank(v, rank, flags);
+
+        *r =3D vreg_reg64_extract(irouter, info);
+
+        return 1;
+    }
+#endif
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(0xA004, 0xBFFC):
+#else
     case VRANGE32(0x7FE0, 0xBFFC):
+#endif
         goto read_reserved;
=20
     case VRANGE32(0xC000, 0xFFCC):
@@ -1382,6 +1586,18 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, =
mmio_info_t *info,
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
     case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+#endif
         /* Above registers are common with GICR and GICD
          * Manage in common */
         return __vgic_v3_distr_common_mmio_write("vGICD", v, info,
@@ -1405,7 +1621,11 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, =
mmio_info_t *info,
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
         return 0;
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(0x3100, 0x60FC):
+#else
     case VRANGE32(0x0F30, 0x60FC):
+#endif
         goto write_reserved;
=20
     case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
@@ -1419,12 +1639,34 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v,=
 mmio_info_t *info,
         vgic_lock_rank(v, rank, flags);
         irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTER);
         vreg_reg64_update(&irouter, r, info);
-        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTER, irout=
er);
+        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTER, irout=
er, false);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+    }
+
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
+    {
+        uint64_t irouter;
+
+        if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 64, gicd_reg - GICD_IROUTERnE,
+                                DABT_DOUBLE_WORD);
+        if ( rank =3D=3D NULL ) goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTERnE);
+        vreg_reg64_update(&irouter, r, info);
+        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTERnE, iro=
uter, true);
         vgic_unlock_rank(v, rank, flags);
         return 1;
     }
+#endif
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(0xA004, 0xBFFC):
+#else
     case VRANGE32(0x7FE0, 0xBFFC):
+#endif
         goto write_reserved;
=20
     case VRANGE32(0xC000, 0xFFCC):
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: Leonid Komarianskyi , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v2 08/10] xen/arm: vgic: add resource management for extended
 SPIs
Thread-Topic: [PATCH v2 08/10] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcB5d8BuZ0dq8rx0Owht+h5hVtIg==
Date: Thu, 7 Aug 2025 12:33:33 +0000
Message-ID:
 
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This change introduces resource management in the VGIC to handle
extended SPIs introduced in GICv3.1. The pending_irqs and
allocated_irqs arrays are resized to support the required
number of eSPIs, based on what is supported by the hardware and
requested by the guest. A new field, ext_shared_irqs, is added
to the VGIC structure to store information about eSPIs, similar
to how shared_irqs is used for regular SPIs.

Since the eSPI range starts at INTID 4096 and INTIDs between 1025
and 4095 are reserved, helper macros are introduced to simplify the
transformation of indices and to enable easier access to eSPI-specific
resources. These changes prepare the VGIC for processing eSPIs as
required by future functionality.

The initialization and deinitialization paths for vgic have been updated
to allocate and free these resources appropriately. Additionally,
updated handling of INTIDs greater than 1024, passed from the toolstack
during domain creation, and verification logic ensures only valid SPI or
eSPI INTIDs are used.

The existing SPI behavior remains unaffected when guests do not request
eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
option is disabled.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- change is_espi_rank to is_valid_espi_rank to verify whether the array
  element ext_shared_irqs exists. The previous version, is_espi_rank,
  only checked if the rank index was less than the maximum possible eSPI
  rank index, but this could potentially result in accessing a
  non-existing array element. To address this, is_valid_espi_rank was
  introduced, which ensures that the required eSPI rank exists
- move gic_number_espis to
  xen/arm: gicv3: implement handling of GICv3.1 eSPI
- update vgic_is_valid_irq checks to allow operating with eSPIs
- remove redundant newline in vgic_allocate_virq
---
 xen/arch/arm/include/asm/vgic.h |  18 ++++
 xen/arch/arm/vgic.c             | 145 ++++++++++++++++++++++++++++++++
 2 files changed, 163 insertions(+)

diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 45201f4ca5..9fa4523018 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -146,6 +146,10 @@ struct vgic_dist {
     int nr_spis; /* Number of SPIs */
     unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
     struct vgic_irq_rank *shared_irqs;
+#ifdef CONFIG_GICV3_ESPI
+    struct vgic_irq_rank *ext_shared_irqs;
+    int nr_espis; /* Number of extended SPIs */
+#endif
     /*
      * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
      * struct arch_vcpu.
@@ -243,6 +247,14 @@ struct vgic_ops {
 /* Number of ranks of interrupt registers for a domain */
 #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
=20
+#ifdef CONFIG_GICV3_ESPI
+#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
+#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
+#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
+#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
+#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
+#endif
+
 #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
 #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
=20
@@ -302,6 +314,12 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct v=
cpu *v,
                                               unsigned int b,
                                               unsigned int n,
                                               unsigned int s);
+#ifdef CONFIG_GICV3_ESPI
+extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
+                                                  unsigned int b,
+                                                  unsigned int n,
+                                                  unsigned int s);
+#endif
 extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int ir=
q);
 extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
 extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 48fbaf56fb..1a6c765af9 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -27,9 +27,26 @@
=20
 bool vgic_is_valid_irq(struct domain *d, unsigned int virq)
 {
+#ifdef CONFIG_GICV3_ESPI
+    if ( virq >=3D ESPI_BASE_INTID && virq < ESPI_IDX2INTID(d->arch.vgic.n=
r_espis) )
+        return true;
+#endif
+
     return virq < vgic_num_irqs(d);
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * Since eSPI indexes start from 4096 and numbers from 1024 to
+ * 4095 are forbidden, we need to check both lower and upper
+ * limits for ranks.
+ */
+static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
+{
+    return ( rank >=3D EXT_RANK_MIN && EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_=
EXT_RANKS(d) );
+}
+#endif
+
 static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
                                                   unsigned int rank)
 {
@@ -37,6 +54,10 @@ static inline struct vgic_irq_rank *vgic_get_rank(struct=
 vcpu *v,
         return v->arch.vgic.private_irqs;
     else if ( rank <=3D DOMAIN_NR_RANKS(v->domain) )
         return &v->domain->arch.vgic.shared_irqs[rank - 1];
+#ifdef CONFIG_GICV3_ESPI
+    else if ( is_valid_espi_rank(v->domain, rank) )
+        return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank=
)];
+#endif
     else
         return NULL;
 }
@@ -53,6 +74,16 @@ struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, u=
nsigned int b,
     return vgic_get_rank(v, rank);
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int b,
+                                           unsigned int n, unsigned int s)
+{
+    unsigned int rank =3D REG_RANK_NR(b, (n >> s));
+
+    return vgic_get_rank(v, rank + EXT_RANK_MIN);
+}
+#endif
+
 struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq)
 {
     unsigned int rank =3D irq / 32;
@@ -117,6 +148,29 @@ int domain_vgic_register(struct domain *d, unsigned in=
t *mmio_count)
     return 0;
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+static int init_vgic_espi(struct domain *d)
+{
+    int i;
+
+    if ( d->arch.vgic.nr_espis =3D=3D 0 )
+        return 0;
+
+    d->arch.vgic.ext_shared_irqs =3D
+        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
+    if ( d->arch.vgic.ext_shared_irqs =3D=3D NULL )
+        return -ENOMEM;
+
+    for ( i =3D 0; i < d->arch.vgic.nr_espis; i++ )
+        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i + d->arch.vgic.=
nr_spis], ESPI_IDX2INTID(i));
+
+    for ( i =3D 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
+        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
+
+    return 0;
+}
+#endif
+
 int domain_vgic_init(struct domain *d, unsigned int nr_spis)
 {
     int i;
@@ -131,6 +185,30 @@ int domain_vgic_init(struct domain *d, unsigned int nr=
_spis)
      */
     nr_spis =3D ROUNDUP(nr_spis, 32);
=20
+#ifdef CONFIG_GICV3_ESPI
+    if ( nr_spis > ESPI_MAX_INTID )
+        return -EINVAL;
+
+    if ( is_espi(nr_spis) )
+    {
+        /*
+         * During domain creation, the toolstack specifies the maximum INT=
ID,
+         * which is defined in the domain config subtracted by 32. To comp=
ute the
+         * actual number of eSPI that will be usable for, add back 32.
+         */
+        d->arch.vgic.nr_espis =3D min(nr_spis - ESPI_BASE_INTID + 32, 1024=
U);
+        /* Verify if GIC HW can handle provided INTID */
+        if ( d->arch.vgic.nr_espis > gic_number_espis() )
+            return -EINVAL;
+        /* Set the maximum available number for defult SPI to pass the nex=
t check */
+        nr_spis =3D VGIC_DEF_NR_SPIS;
+    } else
+    {
+        /* Domain will use the regular SPI range */
+        d->arch.vgic.nr_espis =3D 0;
+    }
+#endif
+
     /* Limit the number of virtual SPIs supported to (1020 - 32) =3D 988  =
*/
     if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
         return -EINVAL;
@@ -145,7 +223,12 @@ int domain_vgic_init(struct domain *d, unsigned int nr=
_spis)
         return -ENOMEM;
=20
     d->arch.vgic.pending_irqs =3D
+#ifdef CONFIG_GICV3_ESPI
+        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis +
+                      d->arch.vgic.nr_espis);
+#else
         xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
+#endif
     if ( d->arch.vgic.pending_irqs =3D=3D NULL )
         return -ENOMEM;
=20
@@ -156,12 +239,23 @@ int domain_vgic_init(struct domain *d, unsigned int n=
r_spis)
     for ( i =3D 0; i < DOMAIN_NR_RANKS(d); i++ )
         vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
=20
+#ifdef CONFIG_GICV3_ESPI
+    ret =3D init_vgic_espi(d);
+    if ( ret )
+        return ret;
+#endif
+
     ret =3D d->arch.vgic.handler->domain_init(d);
     if ( ret )
         return ret;
=20
     d->arch.vgic.allocated_irqs =3D
+#ifdef CONFIG_GICV3_ESPI
+        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d) +
+                      d->arch.vgic.nr_espis));
+#else
         xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
+#endif
     if ( !d->arch.vgic.allocated_irqs )
         return -ENOMEM;
=20
@@ -195,9 +289,27 @@ void domain_vgic_free(struct domain *d)
         }
     }
=20
+#ifdef CONFIG_GICV3_ESPI
+    for ( i =3D 0; i < (d->arch.vgic.nr_espis); i++ )
+    {
+        struct pending_irq *p =3D spi_to_pending(d, ESPI_IDX2INTID(i));
+
+        if ( p->desc )
+        {
+            ret =3D release_guest_irq(d, p->irq);
+            if ( ret )
+                dprintk(XENLOG_G_WARNING, "d%u: Failed to release virq %u =
ret =3D %d\n",
+                        d->domain_id, p->irq, ret);
+        }
+    }
+#endif
+
     if ( d->arch.vgic.handler )
         d->arch.vgic.handler->domain_free(d);
     xfree(d->arch.vgic.shared_irqs);
+#ifdef CONFIG_GICV3_ESPI
+    xfree(d->arch.vgic.ext_shared_irqs);
+#endif
     xfree(d->arch.vgic.pending_irqs);
     xfree(d->arch.vgic.allocated_irqs);
 }
@@ -331,6 +443,17 @@ void arch_move_irqs(struct vcpu *v)
         if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->s=
tatus) )
             irq_set_affinity(p->desc, cpu_mask);
     }
+
+#ifdef CONFIG_GICV3_ESPI
+    for ( i =3D ESPI_BASE_INTID; i < (d)->arch.vgic.nr_espis; i++ )
+    {
+        v_target =3D vgic_get_target_vcpu(v, i);
+        p =3D irq_to_pending(v_target, i);
+
+        if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->s=
tatus) )
+            irq_set_affinity(p->desc, cpu_mask);
+    }
+#endif
 }
=20
 void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
@@ -538,6 +661,10 @@ struct pending_irq *irq_to_pending(struct vcpu *v, uns=
igned int irq)
         n =3D &v->arch.vgic.pending_irqs[irq];
     else if ( is_lpi(irq) )
         n =3D v->domain->arch.vgic.handler->lpi_to_pending(v->domain, irq)=
;
+#ifdef CONFIG_GICV3_ESPI
+    else if ( is_espi(irq) )
+        n =3D &v->domain->arch.vgic.pending_irqs[ESPI_INTID2IDX(irq) + v->=
domain->arch.vgic.nr_spis];
+#endif
     else
         n =3D &v->domain->arch.vgic.pending_irqs[irq - 32];
     return n;
@@ -547,6 +674,14 @@ struct pending_irq *spi_to_pending(struct domain *d, u=
nsigned int irq)
 {
     ASSERT(irq >=3D NR_LOCAL_IRQS);
=20
+#ifdef CONFIG_GICV3_ESPI
+    if ( is_espi(irq) )
+    {
+        irq =3D ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
+        return &d->arch.vgic.pending_irqs[irq];
+    }
+#endif
+
     return &d->arch.vgic.pending_irqs[irq - 32];
 }
=20
@@ -668,6 +803,11 @@ bool vgic_reserve_virq(struct domain *d, unsigned int =
virq)
     if ( !vgic_is_valid_irq(d, virq) )
         return false;
=20
+#ifdef CONFIG_GICV3_ESPI
+    if ( is_espi(virq) )
+        return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d), =
d->arch.vgic.allocated_irqs);
+#endif
+
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
 }
=20
@@ -686,6 +826,11 @@ int vgic_allocate_virq(struct domain *d, bool spi)
     {
         first =3D 32;
         end =3D vgic_num_irqs(d);
+#ifdef CONFIG_GICV3_ESPI
+        /* Take into account extended SPI range */
+        end +=3D d->arch.vgic.nr_espis;
+#endif
+
     }
=20
     /*
--=20
2.34.1


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Date: Thu, 7 Aug 2025 15:50:42 +0300
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Message-ID: 
Subject: Re: Xen 4.21 Development Update [June-July]
To: Oleksii Kurochko 
Cc: Xen-devel , 
	Oleksii Moisieiev , 
	", Ayan Kumar Halder" , Mykyta Poturai , 
	Juergen Gross , Teddy Astie , 
	Bertrand Marquis , Luca Fancellu , 
	"Jason Andryuk," , Alejandro Vallejo , 
	Sergii Dmytruk , "Penny Zheng," , 
	=?UTF-8?Q?Marek_Marczykowski=2DG=C3=B3recki=2C?= , 
	Roger Pau Monne , Andrew Cooper , dmkhn@proton.me, 
	"Daniel P. Smith" , Grygorii Strashko , 
	Alejandro Vallejo , "committers@xenproject.org" , 
	Community Manager 
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

Hi Oleksii,

On Tue, Aug 5, 2025 at 9:19=E2=80=AFPM Oleksii Kurochko
 wrote:
>
> Hello everyone,
>
> This email only tracks big items for xen.git tree. Please reply for
> items you
> would like to see in 4.21 so that people have an idea what is going on an=
d
> prioritise accordingly.
>
> You're welcome to provide description and use cases of the feature you're
> working on.
>
> =3D Timeline =3D
>
> The current release schedule could be found here:
>    https://wiki.xenproject.org/wiki/Xen_Project_X.YY_Release_Notes
>
> And as a reminder I would like to remind at the of this week we will have
> Last posting date (Fri Aug 08, 2025).
>
> =3D Updates =3D
>
> The following items ( the links for them could be found int the list belo=
w )
> were moved to completed:
>    [since Jun2 - Aug5]:
>     Added some tags: [4.21], [next-rel(s)] to the list "Full list of item=
s"
>     below.
>     * x86:
>      - kexec: add kexec support to Mini-OS.
>      - x86: memcpy() / memset() (non-)ERMS flavors plus fallout
>     * Arm:
>      - SMMU handling for PCIe Passthrough on ARM.
>      - Add support for R-Car Gen4 PCI host controller.
>      - First chunk for Arm R82 and MPU support.
>      - Enable R52 support for the first chunk of MPU support
>      - ARM split hardware and control domains.
>     * RISC-V:
>      - Introduce basic UART support and interrupts for hypervisor mode.
>
>    [since May 6 - Jun2]:
>      * Hypervisor:
>        - tools: remove qemu-traditional
>      * Arm:
>        - PCI devices passthrough on Arm, part 3
>      * x86:
>        - xen: cache control improvements
>    [since 4.20 relese - May 6]:
>      * Hypervisor:
>        - Move parts of Arm's Dom0less to common code
>        - remove libxenctrl usage from xenstored
>      * Arm:
>        - Enable early bootup of Armv8-R AArch32 systems
>      * x86:
>        - x86/HVM: emulation (MMIO) improvements
>      * RISC-V:
>        - RISC-V some preinit calls.
>        - Fixes for UBSAN & GCOV support for RISC-V.
>
> Some new items added:
>   [since May]
>      * x86:
>       - Allow x86 to unflatten DTs
>       - hyperlaunch: move remaining pvh dom0 construction
>       - x86/hyperlaunch: introduce concept of core domains
>       - Confidential computing and AMD SEV support
>      * Arm:
>       - SMMU handling for PCIe Passthrough on ARM
>       - xen/arm: scmi: introduce SCI SCMI SMC multi-agent support
>       - Add initial Xen Suspend-to-RAM support on ARM64
>      * RISC-V:
>       - introduce p2m functionality
>   [since 4.20 release]
>      * Hypervisor:
>        - tools: remove qemu-traditional
>        - Physical address hypercall ABI ("HVMv2")
>        - xen: Untangle mm.h
>        - xen: introduce CONFIG_SYSCTL
>        - Add support for exact-node memory claims
>        - Several CI cleanups and improvements, plus yet another new runne=
r
>      * x86:
>        - x86/EFI: prevent write-execute sections
>        - x86: Trenchboot Secure Launch DRTM (Xen)
>        - Hyperlaunch device tree for dom0 (v6)
>        - amd-cppc CPU Performance Scaling Driver (v4)
>        - Hyperlaunch domain builder
>        - kexec: add kexec support to Mini-OS
>        - xen: cache control improvements (should be moved to "Hypervisor"=
?)
>        - x86: generate xen.efi image with no write-execute sections
>        - x86/asm: cleanups after toolchain baseline upgrade
>      * Arm:
>        - Add support for R-Car Gen4 PCI host controller (v4)
>        - FF-A VM to VM support (v5)
>        - First chunk for Arm R82 and MPU support (v4)
>        - ARM split hardware and control domains (v5)
>        - MPU mm subsistem skeleton
>      * RISC-V:
>        - introduce basic UART support and interrupts for hypervisor mode
>
> * Full list of items : *
>
> =3D Projects =3D
>
> =3D=3D Hypervisor =3D=3D
>
> * [4.21] xen/console: cleanup console input switch logic (v5)
>    - Denis Mukhin
>    -
> https://lore.kernel.org/xen-devel/20250530231841.73386-1-dmukhin@ford.com=
/
>
> * [4.21] xen: introduce CONFIG_SYSCTL (v4 -> v8)
>    -  Penny Zheng
>    -
> https://lore.kernel.org/xen-devel/20250711043158.2566880-1-Penny.Zheng@am=
d.com/
>
> * [4.21] Several CI cleanups and improvements, plus yet another new runne=
r
>    - Marek Marczykowski-G=C3=B3recki
>    -
> https://lore.kernel.org/xen-devel/cover.7da1777882774486a13e6f39ff4a2096f=
6b7901e.1744028549.git-series.marmarek@invisiblethingslab.com/
>    -
> https://patchew.org/Xen/cover.7da1777882774486a13e6f39ff4a2096f6b7901e.17=
44028549.git-series.marmarek@invisiblethingslab.com/
>
> * [4.21] automation: Refresh the remaining Debian containers (v2)
>    -  Javi Merino
>    -
> https://lore.kernel.org/xen-devel/cover.1730743077.git.javi.merino@cloud.=
com/T/#m5d9acb7cf5db3c2be3d6527de14b69b07812314e
>
> * [4.21] MSI-X support with qemu in stubdomain, and other related
> changes (v8)
>    -  Marek Marczykowski-G=C3=B3recki
>    -
> https://lore.kernel.org/xen-devel/cover.33fb4385b7dd6c53bda4acf0a9e91748b=
3d7b1f7.1715313192.git-series.marmarek@invisiblethingslab.com/
>    -  Only automation patch left to be reviewed/merged.
>
> * [next-rel(s)] Physical address hypercall ABI ("HVMv2")
>    - Teddy Astie
>    -
> https://lore.kernel.org/xen-devel/cover.1744981654.git.teddy.astie@vates.=
tech/
>
> * [next-rel(s)] xen: Untangle mm.h
>    -  Andrew Cooper
>    -
> https://lore.kernel.org/xen-devel/20250312174513.4075066-1-andrew.cooper3=
@citrix.com/
>    -
> https://patchew.org/Xen/20250312174513.4075066-1-andrew.cooper3@citrix.co=
m/
>
> * [next-rel(s)] Add support for exact-node memory claims
>    -  Alejandro Vallejo
>    -
> https://lore.kernel.org/xen-devel/20250314172502.53498-1-alejandro.vallej=
o@cloud.com/
>    -
> https://patchew.org/Xen/20250314172502.53498-1-alejandro.vallejo@cloud.co=
m/
>
> * [next-rel(s)] Remove the directmap (v5)
>    -  Alejandro Vallejo
>    -
> https://lore.kernel.org/xen-devel/20250108151822.16030-1-alejandro.vallej=
o@cloud.com/
>    -
> https://patchew.org/Xen/20250108151822.16030-1-alejandro.vallejo@cloud.co=
m/
>
> * [next-rel(s)] GRUB: Supporting Secure Boot of xen.gz (v1)
>    -  Ross Lagerwall
>    -
> https://patchew.org/Xen/20240313150748.791236-1-ross.lagerwall@citrix.com=
/
>
> * [next-rel(s)] Introduce xenbindgen to autogen hypercall structs (v1)
>    -  Alejandro Vallejo
>    -
> https://patchew.org/Xen/20241115115200.2824-1-alejandro.vallejo@cloud.com=
/
>
> * [next-rel(s)] Introduce NS8250 UART emulator (v2)
>    -  Denis Mukhin
>    -
> https://patchew.org/Xen/20241205-vuart-ns8250-v1-0-e9aa923127eb@ford.com/
>
> * [next-rel(s)] xen: framework for UART emulators
>    - Denis Mukhin
>    -
> https://lore.kernel.org/xen-devel/20250624035443.344099-1-dmukhin@ford.co=
m/
>
> =3D=3D=3D x86 =3D=3D=3D
> * [4.21] x86/asm: cleanups after toolchain baseline upgrade (v1 -> v2)
>    - Denis Mukhin
>    -
> https://lore.kernel.org/xen-devel/20250403182250.3329498-1-dmukhin@ford.c=
om/
>    - https://patchew.org/Xen/20250403182250.3329498-1-dmukhin@ford.com/
>
> * [4.21?] x86/efi: Fix booting when NX is disabled (v1 -> v2)
>    - Andrew Cooper
>    -
> https://patchew.org/Xen/20240722101838.3946983-1-andrew.cooper3@citrix.co=
m/
>    -
> https://lore.kernel.org/xen-devel/20240722101838.3946983-1-andrew.cooper3=
@citrix.com/
>
> * [4.21?] Hyperlaunch device tree for dom0 (v6)
>    - Alejandro Vallejo
>    - https://patchew.org/Xen/20250429123629.20839-1-agarciav@amd.com/
>    -
> https://lore.kernel.org/xen-devel/20250429123629.20839-1-agarciav@amd.com=
/
>
> *  [4.21?] Boot modules for Hyperlaunch (v9)
>    -  Daniel P. Smith
>    -
> https://lore.kernel.org/xen-devel/20241115131204.32135-1-dpsmith@apertuss=
olutions.com/
>    -
> https://patchew.org/Xen/20241115131204.32135-1-dpsmith@apertussolutions.c=
om/
>
> *  [4.21?] Address Space Isolation FPU preparations (v2->v3)
>    -  Alejandro Vallejo
>    -
> https://patchew.org/Xen/20250110132823.24348-1-alejandro.vallejo@cloud.co=
m/
>
> * [next-rel(s)] Hyperlaunch domain builder
>    - Daniel P. Smith
>    -
> https://lore.kernel.org/xen-devel/20250515131744.3843-1-dpsmith@apertusso=
lutions.com/
>
> * [next-rel(s)] Confidential computing and AMD SEV support
>    - Teddy Astie
>    - https://patchew.org/Xen/cover.1747312394.git.teddy.astie@vates.tech/
>    -
> https://lore.kernel.org/xen-devel/cover.1747312394.git.teddy.astie@vates.=
tech/
>
> * [next-rel(s)] amd-cppc CPU Performance Scaling Driver (v5 -> v6)
>    - Penny Zheng
>    -
> https://lore.kernel.org/xen-devel/20250711035106.2540522-1-Penny.Zheng@am=
d.com/
>
> * [next-rel(s)] x86: Trenchboot Secure Launch DRTM (Xen) (v1 -> v3)
>    - Sergii Dmytruk
>    - https://patchew.org/Xen/cover.1745172094.git.sergii.dmytruk@3mdeb.co=
m/
>    -
> https://lore.kernel.org/xen-devel/cover.1748611041.git.sergii.dmytruk@3md=
eb.com/
>
> * [next-rel(s)] x86/EFI: prevent write-execute sections
>    - Roger Pau Monne 
>    -
> https://lore.kernel.org/xen-devel/20250401130840.72119-1-roger.pau@citrix=
.com/
>
> * [next-rel(s)] x86: generate xen.efi image with no write-execute section=
s
>    - Roger Pau Monne
>    -
> https://lore.kernel.org/xen-devel/20250318173547.59475-1-roger.pau@citrix=
.com/
>
> *  [next-rel(s)] Expose consistent topology to guests (v7)
>    -  Alejandro Vallejo
>    -
> https://patchew.org/Xen/20241021154600.11745-1-alejandro.vallejo@cloud.co=
m/
>
> *  [next-rel(s)] x86/alternatives: Adjust all insn-relative fields (v2)
>    -  Andrew Cooper
>    -
> https://lore.kernel.org/xen-devel/20241002152725.1841575-1-andrew.cooper3=
@citrix.com/T/#mac2deaea7e02a343210d61887486433d946ad129
>
> *  [next-rel(s)] x86emul: misc additions (v7)
>    -  Jan Beulich
>    - https://patchew.org/Xen/3a25cd59-e1cb-4bfc-b868-fb11599d22f5@suse.co=
m/
>
> *  [next-rel(s)] x86: support AVX10 (v3)
>    -  Jan Beulich
>    -
> https://lore.kernel.org/xen-devel/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@su=
se.com/
>    - https://patchew.org/Xen/516b7f9a-048e-409d-8a4e-89aeb8ffacc4@suse.co=
m/
>
> *  [next-rel(s)] VT-d: SATC handling; ATS: tidying (v2)
>    -  Jan Beulich
>    - https://patchew.org/Xen/64b028be-2197-4951-ae5b-32f9eabfa84a@suse.co=
m/
>
> *  [next-rel(s)] x86: parallelize AP bring-up during boot (v1)
>    -  Krystian Hebel
>    -
> https://lore.kernel.org/xen-devel/cover.1699982111.git.krystian.hebel@3md=
eb.com/
>
> *  [next-rel(s)] x86/spec-ctrl: IBPB improvements (v4)
>    -  Jan Beulich
>    - https://patchew.org/Xen/06591b64-2f05-a4cc-a2f3-a74c3c4a76d6@suse.co=
m/
>
> *  [next-rel(s)] Move some boot code from assembly to C (v2)
>    -  Frediano Ziglio
>    -
> https://lore.kernel.org/xen-devel/20241122093358.478774-1-frediano.ziglio=
@cloud.com/
>    -
> https://patchew.org/Xen/20241122093358.478774-1-frediano.ziglio@cloud.com=
/
>
> *  [next-rel(s)]amd-pstate CPU Performance Scaling Driver (v1)
>    -  Penny Zheng
>    - https://patchew.org/Xen/20241203081111.463400-1-Penny.Zheng@amd.com/
>    -
> https://lore.kernel.org/xen-devel/593baee2-9bf1-4db4-86e8-015cae48dc1a@su=
se.com/
>
> * [next-rel(s)] x86: adventures in Address Space Isolation
>    - Roger Pau Monne 
>    -
> https://lore.kernel.org/xen-devel/20250108142659.99490-1-roger.pau@citrix=
.com/
>
> =3D=3D=3D ARM =3D=3D=3D
>
> * [4.21?] MPU mm subsistem skeleton
>    - Luca Fancellu
>    -
> https://lore.kernel.org/xen-devel/20250312135258.1815706-1-luca.fancellu@=
arm.com/
>    - https://patchew.org/Xen/20250312135258.1815706-1-luca.fancellu@arm.c=
om/
>
> * [4.21?] Add initial Xen Suspend-to-RAM support on ARM64 (v4)
>    - Mykola Kvach
>    -
> https://lore.kernel.org/xen-devel/cover.1748848482.git.mykola_kvach@epam.=
com/

Our team expects to see this feature included in the 4.21 release.

Additional related patches for this feature:
https://lore.kernel.org/xen-devel/cover.1753778926.git.mykola_kvach@epam.co=
m/
https://lore.kernel.org/xen-devel/e57133182b9bcecb519911c8b3f0d871955d6fef.=
1754540991.git.mykola_kvach@epam.com/

>
> * [4.21?] xen/arm: scmi: introduce SCI SCMI SMC multi-agent support (->v4=
)
>    - Oleksii Moisieiev
>    -
> https://lore.kernel.org/xen-devel/cover.1753184487.git.oleksii_moisieiev@=
epam.com/
>
> * [next-rel(s)] FF-A VM to VM support (v6)
>    - Bertrand Marquis 
>    -
> https://lore.kernel.org/xen-devel/cover.1747925287.git.bertrand.marquis@a=
rm.com/
>    - https://patchew.org/Xen/cover.1747925287.git.bertrand.marquis@arm.co=
m/
>
> *  [next-rel(s)] Add Virtio-PCI for dom0less on ARM (v1)
>    -  Edgar E. Iglesias
>    -
> https://lore.kernel.org/xen-devel/20240924162359.1390487-1-edgar.iglesias=
@gmail.com/T/#mfa148991b9408f223a079d4cef610244d5b04c2b
>    -
> https://patchew.org/Xen/20240924162359.1390487-1-edgar.iglesias@gmail.com=
/
>
> *  [next-rel(s)] DOMCTL-based guest magic region allocation for 11 domUs
> (v4)
>    -  Henry Wang
>    - https://patchew.org/Xen/20240409045357.236802-1-xin.wang2@amd.com/
>
> =3D=3D=3D RISCV =3D=3D=3D
>
> * [4.21] xen/riscv: introduce p2m functionality (v1->v3)
>    - Oleksii Kurochko
>    -
> https://lore.kernel.org/xen-devel/cover.1753973161.git.oleksii.kurochko@g=
mail.com/T/#t
>
> =3D=3D=3D PPC =3D=3D=3D
>
> *  Early Boot Allocation on Power (v5)
>    -  Shawn Anastasio
>    -
> https://lore.kernel.org/xen-devel/cover.1727388925.git.sanastasio@raptore=
ngineering.com/T/#m8cac91a93b56a359fa2d5f08596c4be61dca290d
>    -
> https://patchew.org/Xen/cover.1727388925.git.sanastasio@raptorengineering=
.com/
>
> =3D=3D Completed =3D=3D
>
> =3D=3D=3D Hypervisor =3D=3D=3D
>
> * tools: remove qemu-traditional
>    - Juergen Gross 
>    - https://lore.kernel.org/xen-devel/20250527132035.985-1-jgross@suse.c=
om/
>
> *  remove libxenctrl usage from xenstored (v8)
>    -  Juergen Gross
>    -
> https://lore.kernel.org/xen-devel/20250204113407.16839-1-jgross@suse.com/
>
> * xen/config.h: Move BITS_PER_* definitions from asm/config.h to
> xen/config.h
>    - Oleksii Kurochko
>    -
> https://lore.kernel.org/xen-devel/6b21fb046cf1c8ca760f5ad72fa3cc13b59c406=
9.1743092485.git.oleksii.kurochko@gmail.com/
>
> * Move parts of Arm's Dom0less to common code
>    - Oleksii Kurochko
>    -
> https://patchew.org/Xen/cover.1746468003.git.oleksii.kurochko@gmail.com/
>    -
> https://lore.kernel.org/xen-devel/cover.1746468003.git.oleksii.kurochko@g=
mail.com/T/#t
>
> =3D=3D=3D x86 =3D=3D=3D
>
> *  x86: memcpy() / memset() (non-)ERMS flavors plus fallout (v4 -> v5)
>    -  Jan Beulich
>    - https://patchew.org/Xen/14b65231-b83b-43fb-bbcf-dec5c07d285b@suse.co=
m/
>
> * kexec: add kexec support to Mini-OS (v1 -> v2)
>    - Juergen Gross 
>    -
> https://lore.kernel.org/xen-devel/20250616084619.11112-1-jgross@suse.com/
>
> * [4.21] Allow x86 to unflatten DTs (v8)
>    - Alejandro Vallejo
>    -
> https://lore.kernel.org/xen-devel/20250722000525.7247-1-alejandro.garciav=
allejo@amd.com/#t
>
> * xen: cache control improvements
>    - Roger Pau Monne
>    -
> https://lore.kernel.org/xen-devel/20250506083148.34963-1-roger.pau@citrix=
.com/
>
> *  x86/HVM: emulation (MMIO) improvements (v3)
>    -  Jan Beulich
>    - https://patchew.org/Xen/729f7896-55b7-4b5b-a7e9-6eb0420e0b14@suse.co=
m/
>
> =3D=3D=3D ARM =3D=3D=3D
>
> * Enable R52 support for the first chunk of MPU support
>   -  Ayan Kumar Halder
>   -
> https://lore.kernel.org/xen-devel/20250619113152.2723066-1-ayan.kumar.hal=
der@amd.com/
>
> * ARM split hardware and control domains (v5)
>    - Jason Andryuk
>    -
> https://lore.kernel.org/xen-devel/20250416212911.410946-1-jason.andryuk@a=
md.com/
>    - https://patchew.org/Xen/20250416212911.410946-1-jason.andryuk@amd.co=
m/
>
> * First chunk for Arm R82 and MPU support (v4 -> v6)
>    - Luca Fancellu
>    -
> https://lore.kernel.org/xen-devel/20250523065406.3795420-1-luca.fancellu@=
arm.com/
>    - https://patchew.org/Xen/20250523065406.3795420-1-luca.fancellu@arm.c=
om/
>
> * Add support for R-Car Gen4 PCI host controller (v4 -> v5)
>    - Mykyta Poturai
>    -
> https://lore.kernel.org/xen-devel/cover.1747820844.git.mykyta_poturai@epa=
m.com/
>    -
> https://patchew.org/Xen/cover.1747820844.git.mykyta._5Fpoturai@epam.com/
>
> * SMMU handling for PCIe Passthrough on ARM (v11 -> v12)
>    - Mykyta Poturai
>    -
> https://lore.kernel.org/xen-devel/cover.1751439885.git.mykyta_poturai@epa=
m.com/
>
> *  PCI devices passthrough on Arm, part 3 (v16->v20->v21)
>    -  Stewart Hildebrand
>    -
> https://patchew.org/Xen/20250508104608.531079-1-stewart.hildebrand@amd.co=
m/
>    -
> https://lore.kernel.org/xen-devel/20250508104608.531079-1-stewart.hildebr=
and@amd.com/
>
> * Enable early bootup of Armv8-R AArch32 systems
>    - Ayan Kumar Halder
>    -
> https://lore.kernel.org/xen-devel/20250414164514.588373-1-ayan.kumar.hald=
er@amd.com/
>    -
> https://patchew.org/Xen/20250414164514.588373-1-ayan.kumar.halder@amd.com=
/
>
> =3D=3D=3D RISC-V =3D=3D=3D
>
> * riscv: introduce basic UART support and interrupts for hypervisor mode
> (v2 -> v3)
>    -  Oleksii Kurochko
>    -
> https://lore.kernel.org/xen-devel/cover.1747843009.git.oleksii.kurochko@g=
mail.com/
>    -
> https://patchew.org/Xen/cover.1747843009.git.oleksii.kurochko@gmail.com/
>
> * RISC-V some preinit calls:
>    -  Oleksii Kurochko
>    -
> https://lore.kernel.org/xen-devel/4ddde60347edf6740fbc69b5739d099616f5b5f=
f.1743165791.git.oleksii.kurochko@gmail.com/
>
> * Fixes for UBSAN & GCOV support for RISC-V:
>    -  Oleksii Kurochko
>    -
> https://lore.kernel.org/xen-devel/9fbb5e1389b84bed2e95f99e4c383d0215c7a52=
4.1744889185.git.oleksii.kurochko@gmail.com/
>
> Have a good week!
>
> Best regards,
>   Oleksi

Best regards,
Mykola


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Date: Thu, 7 Aug 2025 10:08:11 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 09/16] dma-mapping: handle MMIO flow in
 dma_map|unmap_page
Message-ID: <20250807130811.GI184255@nvidia.com>
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On Mon, Aug 04, 2025 at 03:42:43PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Extend base DMA page API to handle MMIO flow.

I would mention here this follows the long ago agreement that we don't
need to enable P2P in the legacy dma_ops area. Simply failing when
getting an ATTR_MMIO is OK.

> --- a/kernel/dma/mapping.c
> +++ b/kernel/dma/mapping.c
> @@ -158,6 +158,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
>  {
>  	const struct dma_map_ops *ops = get_dma_ops(dev);
>  	phys_addr_t phys = page_to_phys(page) + offset;
> +	bool is_mmio = attrs & DMA_ATTR_MMIO;
>  	dma_addr_t addr;
>  
>  	BUG_ON(!valid_dma_direction(dir));
> @@ -166,12 +167,23 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
>  		return DMA_MAPPING_ERROR;
>  
>  	if (dma_map_direct(dev, ops) ||
> -	    arch_dma_map_phys_direct(dev, phys + size))
> +	    (!is_mmio && arch_dma_map_phys_direct(dev, phys + size)))
>  		addr = dma_direct_map_phys(dev, phys, size, dir, attrs);

I don't know this area, maybe explain a bit in the commit message how
you see ATTR_MMIO interacts with arch_dma_map_phys_direct ?

>  	else if (use_dma_iommu(dev))
>  		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
> -	else
> +	else if (is_mmio) {
> +		if (!ops->map_resource)
> +			return DMA_MAPPING_ERROR;
> +
> +		addr = ops->map_resource(dev, phys, size, dir, attrs);
> +	} else {
> +		/*
> +		 * All platforms which implement .map_page() don't support
> +		 * non-struct page backed addresses.
> +		 */
>  		addr = ops->map_page(dev, page, offset, size, dir, attrs);

Comment could be clearer maybe just:

 The dma_ops API contract for ops->map_page() requires kmappable memory, while
 ops->map_resource() does not.

But this approach looks good to me, it prevents non-kmappable phys
from going down to the legacy dma_ops map_page where it cannot work.

>From here you could do what Marek and Christoph asked to flush the
struct page out of the ops->map_page() and replace it with
kmap_local_phys().

Jason


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Date: Thu, 7 Aug 2025 10:14:18 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 13/16] mm/hmm: properly take MMIO path
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On Mon, Aug 04, 2025 at 03:42:47PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> In case peer-to-peer transaction traverses through host bridge,
> the IOMMU needs to have IOMMU_MMIO flag, together with skip of
> CPU sync.
> 
> The latter was handled by provided DMA_ATTR_SKIP_CPU_SYNC flag,
> but IOMMU flag was missed, due to assumption that such memory
> can be treated as regular one.
> 
> Reuse newly introduced DMA attribute to properly take MMIO path.
> 
> Signed-off-by: Leon Romanovsky 
> ---
>  mm/hmm.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/mm/hmm.c b/mm/hmm.c
> index 015ab243f0813..6556c0e074ba8 100644
> --- a/mm/hmm.c
> +++ b/mm/hmm.c
> @@ -746,7 +746,7 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
>  	case PCI_P2PDMA_MAP_NONE:
>  		break;
>  	case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
> -		attrs |= DMA_ATTR_SKIP_CPU_SYNC;
> +		attrs |= DMA_ATTR_MMIO;
>  		pfns[idx] |= HMM_PFN_P2PDMA;
>  		break;

Yeah, this is a lot cleaner

Reviewed-by: Jason Gunthorpe 

Jason


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Date: Thu, 7 Aug 2025 10:14:58 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 12/16] mm/hmm: migrate to physical address-based DMA
 mapping API
Message-ID: <20250807131458.GK184255@nvidia.com>
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On Mon, Aug 04, 2025 at 03:42:46PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Convert HMM DMA operations from the legacy page-based API to the new
> physical address-based dma_map_phys() and dma_unmap_phys() functions.
> This demonstrates the preferred approach for new code that should use
> physical addresses directly rather than page+offset parameters.
> 
> The change replaces dma_map_page() and dma_unmap_page() calls with
> dma_map_phys() and dma_unmap_phys() respectively, using the physical
> address that was already available in the code. This eliminates the
> redundant page-to-physical address conversion and aligns with the
> DMA subsystem's move toward physical address-centric interfaces.
> 
> This serves as an example of how new code should be written to leverage
> the more efficient physical address API, which provides cleaner interfaces
> for drivers that already have access to physical addresses.
> 
> Signed-off-by: Leon Romanovsky 
> ---
>  mm/hmm.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

Reviewed-by: Jason Gunthorpe 

Maybe the next patch should be squished into here too if it is going
to be a full example

Jason


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Date: Thu, 7 Aug 2025 15:35:28 +0200
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Subject: Re: [PATCH v3 06/20] xen/riscv: add root page table allocation
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com>
 <7491c934-f847-4fe2-9d9b-a500f0888198@suse.com>
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From: Oleksii Kurochko 
In-Reply-To: <7491c934-f847-4fe2-9d9b-a500f0888198@suse.com>

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On 8/5/25 12:43 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> +static int p2m_alloc_root_table(struct p2m_domain *p2m)
>> +{
>> +    struct domain *d = p2m->domain;
>> +    struct page_info *page;
>> +    const unsigned int nr_root_pages = P2M_ROOT_PAGES;
>> +
>> +    /*
>> +     * Return back nr_root_pages to assure the root table memory is also
>> +     * accounted against the P2M pool of the domain.
>> +     */
>> +    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
>> +        return -ENOMEM;
>> +
>> +    page = p2m_allocate_root(d);
>> +    if ( !page )
>> +        return -ENOMEM;
>> +
>> +    p2m->root = page;
>> +
>> +    return 0;
>> +}
> In the success case, shouldn't you bump the paging pool's total_pages by
> P2M_ROOT_PAGES? (As the freeing side is missing so far, it's not easy to
> tell whether there's [going to be] a balancing problem in the long run.
> In the short run there certainly is.)

I think that total_pages should be updated only in case when page is added
to freelist.
In the case of p2m root table, we just returning some pages to domheap and
durint that decreasing an amount of total_pages as freelist has lesser pages,
and then just allocate pages from domheap without adding them to freelist.

~ Oleksii

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    On 8/5/25 12:43 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    +static int p2m_alloc_root_table(struct p2m_domain *p2m)
+{
+    struct domain *d = p2m->domain;
+    struct page_info *page;
+    const unsigned int nr_root_pages = P2M_ROOT_PAGES;
+
+    /*
+     * Return back nr_root_pages to assure the root table memory is also
+     * accounted against the P2M pool of the domain.
+     */
+    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
+        return -ENOMEM;
+
+    page = p2m_allocate_root(d);
+    if ( !page )
+        return -ENOMEM;
+
+    p2m->root = page;
+
+    return 0;
+}

    
      
    
      
    In the success case, shouldn't you bump the paging pool's total_pages by
P2M_ROOT_PAGES? (As the freeing side is missing so far, it's not easy to
tell whether there's [going to be] a balancing problem in the long run.
In the short run there certainly is.)
    
    
    
    
    I think that total_pages should be updated only in case when page is added
to freelist.
In the case of p2m root table, we just returning some pages to domheap and
durint that decreasing an amount of total_pages as freelist has lesser pages,
and then just allocate pages from domheap without adding them to freelist.

~ Oleksii

    
  


--------------Ai0G5NcisNLRIKxItrFcJzkT--


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Date: Thu, 7 Aug 2025 10:38:48 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
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	kasan-dev@googlegroups.com, Keith Busch ,
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	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
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	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 11/16] dma-mapping: export new dma_*map_phys()
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On Mon, Aug 04, 2025 at 03:42:45PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Introduce new DMA mapping functions dma_map_phys() and dma_unmap_phys()
> that operate directly on physical addresses instead of page+offset
> parameters. This provides a more efficient interface for drivers that
> already have physical addresses available.
> 
> The new functions are implemented as the primary mapping layer, with
> the existing dma_map_page_attrs() and dma_unmap_page_attrs() functions
> converted to simple wrappers around the phys-based implementations.

Briefly explain how the existing functions are remapped into wrappers
calling the phys functions.

> +dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
> +		size_t offset, size_t size, enum dma_data_direction dir,
> +		unsigned long attrs)
> +{
> +	phys_addr_t phys = page_to_phys(page) + offset;
> +
> +	if (unlikely(attrs & DMA_ATTR_MMIO))
> +		return DMA_MAPPING_ERROR;
> +
> +	if (IS_ENABLED(CONFIG_DMA_API_DEBUG))
> +		WARN_ON_ONCE(!pfn_valid(PHYS_PFN(phys)));

This is not useful, if we have a struct page and did page_to_phys then
pfn_valid is always true.

Instead this should check for any ZONE_DEVICE page and reject that.
And handle the error:

  if (WARN_ON_ONCE()) return DMA_MAPPING_ERROR;

I'd add another debug check inside dma_map_phys that if !ATTR_MMIO
then pfn_valid, and not zone_device

> @@ -337,41 +364,18 @@ EXPORT_SYMBOL(dma_unmap_sg_attrs);
>  dma_addr_t dma_map_resource(struct device *dev, phys_addr_t phys_addr,
>  		size_t size, enum dma_data_direction dir, unsigned long attrs)
>  {

> -	const struct dma_map_ops *ops = get_dma_ops(dev);
> -	dma_addr_t addr = DMA_MAPPING_ERROR;
> -
> -	BUG_ON(!valid_dma_direction(dir));
> -
> -	if (WARN_ON_ONCE(!dev->dma_mask))
> +	if (IS_ENABLED(CONFIG_DMA_API_DEBUG) &&
> +	    WARN_ON_ONCE(pfn_valid(PHYS_PFN(phys_addr))))
>  		return DMA_MAPPING_ERROR;
>  
> -	if (dma_map_direct(dev, ops))
> -		addr = dma_direct_map_resource(dev, phys_addr, size, dir, attrs);
> -	else if (use_dma_iommu(dev))
> -		addr = iommu_dma_map_resource(dev, phys_addr, size, dir, attrs);
> -	else if (ops->map_resource)
> -		addr = ops->map_resource(dev, phys_addr, size, dir, attrs);
> -
> -	trace_dma_map_resource(dev, phys_addr, addr, size, dir, attrs);
> -	debug_dma_map_resource(dev, phys_addr, size, dir, addr, attrs);
> -	return addr;
> +	return dma_map_phys(dev, phys_addr, size, dir, attrs | DMA_ATTR_MMIO);
>  }
>  EXPORT_SYMBOL(dma_map_resource);

I think this makes alot of sense at least.

Jason


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Date: Thu, 7 Aug 2025 10:45:33 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 16/16] nvme-pci: unmap MMIO pages with appropriate
 interface
Message-ID: <20250807134533.GM184255@nvidia.com>
References: 
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On Mon, Aug 04, 2025 at 03:42:50PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Block layer maps MMIO memory through dma_map_phys() interface
> with help of DMA_ATTR_MMIO attribute. There is a need to unmap
> that memory with the appropriate unmap function.

Be specific, AFIACT the issue is that on dma_ops platforms the map
will call ops->map_resource for ATTR_MMIO so we must have the unmap
call ops->unmap_resournce

Maybe these patches should be swapped then, as adding ATTR_MMIO seems
like it created this issue?

Jason


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The function returning zero is an error indication; we shouldn't try to
map MFN 0 and then treat that page as a context table.

Signed-off-by: Jan Beulich 
---
Whether to really have the ASSERT_UNREACHABLE() on the unmap path I'm
not quite sure about: According to my checking, the early bailing from
intel_iommu_remove_device() is what covers the case where an earlier
mapping attempt may have failed; in all other cases a mapping was
previously established. IOW while it should indeed be impossible to
hit that path, there's not really a problem if it was taken: It would
then be no different from finding a non-present context entry.

--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -1499,6 +1499,11 @@ int domain_context_mapping_one(
     ASSERT(pcidevs_locked());
     spin_lock(&iommu->lock);
     maddr = bus_to_context_maddr(iommu, bus);
+    if ( !maddr )
+    {
+        spin_unlock(&iommu->lock);
+        return -ENOMEM;
+    }
     context_entries = (struct context_entry *)map_vtd_domain_page(maddr);
     context = &context_entries[devfn];
     old = (lctxt = *context).full;
@@ -1853,6 +1858,12 @@ int domain_context_unmap_one(
     spin_lock(&iommu->lock);
 
     maddr = bus_to_context_maddr(iommu, bus);
+    if ( !maddr )
+    {
+        ASSERT_UNREACHABLE();
+        spin_unlock(&iommu->lock);
+        return 0;
+    }
     context_entries = (struct context_entry *)map_vtd_domain_page(maddr);
     context = &context_entries[devfn];
 


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Date: Thu, 7 Aug 2025 11:19:29 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 00/16] dma-mapping: migrate to physical address-based
 API
Message-ID: <20250807141929.GN184255@nvidia.com>
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On Mon, Aug 04, 2025 at 03:42:34PM +0300, Leon Romanovsky wrote:
> Changelog:
> v1:
>  * Added new DMA_ATTR_MMIO attribute to indicate
>    PCI_P2PDMA_MAP_THRU_HOST_BRIDGE path.
>  * Rewrote dma_map_* functions to use thus new attribute
> v0: https://lore.kernel.org/all/cover.1750854543.git.leon@kernel.org/
> ------------------------------------------------------------------------
> 
> This series refactors the DMA mapping to use physical addresses
> as the primary interface instead of page+offset parameters. This
> change aligns the DMA API with the underlying hardware reality where
> DMA operations work with physical addresses, not page structures.

Lets elaborate this as Robin asked:

This series refactors the DMA mapping API to provide a phys_addr_t
based, and struct-page free, external API that can handle all the
mapping cases we want in modern systems:

 - struct page based cachable DRAM
 - struct page MEMORY_DEVICE_PCI_P2PDMA PCI peer to peer non-cachable MMIO
 - struct page-less PCI peer to peer non-cachable MMIO
 - struct page-less "resource" MMIO

Overall this gets much closer to Matthew's long term wish for
struct-pageless IO to cachable DRAM. The remaining primary work would
be in the mm side to allow kmap_local_pfn()/phys_to_virt() to work on
phys_addr_t without a struct page.

The general design is to remove struct page usage entirely from the
DMA API inner layers. For flows that need to have a KVA for the
physical address they can use kmap_local_pfn() or phys_to_virt(). This
isolates the struct page requirements to MM code only. Long term all
removals of struct page usage are supporting Matthew's memdesc
project which seeks to substantially transform how struct page works.

Instead make the DMA API internals work on phys_addr_t. Internally
there are still dedicated 'page' and 'resource' flows, except they are
now distinguished by a new DMA_ATTR_MMIO instead of by callchain. Both
flows use the same phys_addr_t.

When DMA_ATTR_MMIO is specified things work similar to the existing
'resource' flow. kmap_local_pfn(), phys_to_virt(), phys_to_page(),
pfn_valid(), etc are never called on the phys_addr_t. This requires
rejecting any configuration that would need swiotlb. CPU cache
flushing is not required, and avoided, as ATTR_MMIO also indicates the
address have no cachable mappings. This effectively removes any
DMA API side requirement to have struct page when DMA_ATTR_MMIO is
used.

In the !DMA_ATTR_MMIO mode things work similarly to the 'page' flow,
except on the common path of no cache flush, no swiotlb it never
touches a struct page. When cache flushing or swiotlb copying
kmap_local_pfn()/phys_to_virt() are used to get a KVA for CPU
usage. This was already the case on the unmap side, now the map side
is symmetric.

Callers are adjusted to set DMA_ATTR_MMIO. Existing 'resource' users
must set it. The existing struct page based MEMORY_DEVICE_PCI_P2PDMA
path must also set it. This corrects some existing bugs where iommu
mappings for P2P MMIO were improperly marked IOMMU_CACHE.

Since ATTR_MMIO is made to work with all the existing DMA map entry
points, particularly dma_iova_link(), this finally allows a way to use
the new DMA API to map PCI P2P MMIO without creating struct page. The
VFIO DMABUF series demonstrates how this works. This is intended to
replace the incorrect driver use of dma_map_resource() on PCI BAR
addresses.

This series does the core code and modern flows. A followup series
will give the same treatement to the legacy dma_ops implementation.

Jason


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Date: Thu, 7 Aug 2025 16:28:20 +0200
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Subject: Re: [PATCH v4 1/8] xen/domain: introduce common emulation flags
To: dmkhn@proton.me, Jan Beulich 
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org,
 michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
 dmukhin@ford.com, xen-devel@lists.xenproject.org
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-2-dmukhin@ford.com>
  
Content-Language: en-US
From: Oleksii Kurochko 
In-Reply-To: 

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On 8/5/25 2:54 AM, dmkhn@proton.me wrote:
> + Cc: Oleskii
>
> On Mon, Aug 04, 2025 at 11:46:36AM +0200, Jan Beulich wrote:
>> On 31.07.2025 21:21,dmkhn@proton.me wrote:
>>> --- a/xen/include/xen/sched.h
>>> +++ b/xen/include/xen/sched.h
>>> @@ -652,6 +652,8 @@ struct domain
>>>       unsigned int *llc_colors;
>>>   #endif
>>>
>>> +    uint32_t emulation_flags;
>> Just one further remark: The field probably never should have been of this
>> type; unsigned int will do, and imo will want switching to while the field
>> is being moved. (Before giving an x86 ack, I want to convince myself though
>> that this is moving us in the right direction.)
> Hi Jan,
>
> I can definitely use different mechanism for virt ns16550: add a new field in
> xen_arch_domainconfig. That will also simplify some of the emulation_flags
> checks on x86 and will be more flexible wrt emulator configuration (e.g. I can
> allow passing I/O ports ranges).
>
> Hi Arm/RISC-V maintainers,
>
> Do you foresee any need in bubbling up emulation_flags to the common `struct
> domain`?

At the moment, in RISC-V's downstream branches emulation_flags isn't used. And,
for now, I am not really sure that it's going to be used in the nearest future.

~ Oleksii

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    On 8/5/25 2:54 AM, dmkhn@proton.me
      wrote:
    
    
    
    
    
      
    + Cc: Oleskii

On Mon, Aug 04, 2025 at 11:46:36AM +0200, Jan Beulich wrote:

    
      
    
        
    On 31.07.2025 21:21, dmkhn@proton.me wrote:

    
        
    
          
    --- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -652,6 +652,8 @@ struct domain
     unsigned int *llc_colors;
 #endif

+    uint32_t emulation_flags;

    
        
    
        
    Just one further remark: The field probably never should have been of this
type; unsigned int will do, and imo will want switching to while the field
is being moved. (Before giving an x86 ack, I want to convince myself though
that this is moving us in the right direction.)

    
      
    
      
    Hi Jan,

I can definitely use different mechanism for virt ns16550: add a new field in
xen_arch_domainconfig. That will also simplify some of the emulation_flags
checks on x86 and will be more flexible wrt emulator configuration (e.g. I can
allow passing I/O ports ranges).

Hi Arm/RISC-V maintainers,

Do you foresee any need in bubbling up emulation_flags to the common `struct
domain`?

    
    
    
    
    At the moment, in RISC-V's downstream branches emulation_flags isn't used. And,
for now, I am not really sure that it's going to be used in the nearest future.

~ Oleksii
    
  


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Subject: Re: Xen 4.21 Development Update [June-July]
To: Mykola Kvach 
Cc: Xen-devel ,
 Oleksii Moisieiev ,
 Ayan Kumar Halder ,
 Mykyta Poturai , Juergen Gross ,
 Teddy Astie ,
 Bertrand Marquis ,
 Luca Fancellu , "Jason Andryuk,"
 , Alejandro Vallejo ,
 Sergii Dmytruk , "Penny Zheng,"
 ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki=2C?=
 , Roger Pau Monne ,
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 "Daniel P. Smith" ,
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 "committers@xenproject.org" ,
 Community Manager 
References: 
 
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From: Oleksii Kurochko 
In-Reply-To: 

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On 8/7/25 2:50 PM, Mykola Kvach wrote:
> Hi Oleksii,

Hello Mykola,

>
> === ARM ===
>
> * [4.21?] MPU mm subsistem skeleton
>     - Luca Fancellu
>     -
> https://lore.kernel.org/xen-devel/20250312135258.1815706-1-luca.fancellu@arm.com/
>     -https://patchew.org/Xen/20250312135258.1815706-1-luca.fancellu@arm.com/
>
> * [4.21?] Add initial Xen Suspend-to-RAM support on ARM64 (v4)
>     - Mykola Kvach
>     -
> https://lore.kernel.org/xen-devel/cover.1748848482.git.mykola_kvach@epam.com/
> Our team expects to see this feature included in the 4.21 release.
>
> Additional related patches for this feature:
> https://lore.kernel.org/xen-devel/cover.1753778926.git.mykola_kvach@epam.com/
> https://lore.kernel.org/xen-devel/e57133182b9bcecb519911c8b3f0d871955d6fef.1754540991.git.mykola_kvach@epam.com/

Thanks for your comment and info about additional patches.

~ Oleksii


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    On 8/7/25 2:50 PM, Mykola Kvach wrote:
    
    
    
    
    
      
    Hi Oleksii,

    
    
    
    
    Hello Mykola,


    
    
    
      
    
=== ARM ===

* [4.21?] MPU mm subsistem skeleton
   - Luca Fancellu
   -
https://lore.kernel.org/xen-devel/20250312135258.1815706-1-luca.fancellu@arm.com/
   - https://patchew.org/Xen/20250312135258.1815706-1-luca.fancellu@arm.com/

* [4.21?] Add initial Xen Suspend-to-RAM support on ARM64 (v4)
   - Mykola Kvach
   -
https://lore.kernel.org/xen-devel/cover.1748848482.git.mykola_kvach@epam.com/

    
      
    Our team expects to see this feature included in the 4.21 release.

Additional related patches for this feature:
https://lore.kernel.org/xen-devel/cover.1753778926.git.mykola_kvach@epam.com/
https://lore.kernel.org/xen-devel/e57133182b9bcecb519911c8b3f0d871955d6fef.1754540991.git.mykola_kvach@epam.com/
    
    
    
    
    Thanks for your comment and info about additional patches.

~ Oleksii
    
    
    
  


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Subject: Re: [PATCH v1 10/16] xen: swiotlb: Open code map_resource callback
To: Leon Romanovsky ,
 Marek Szyprowski 
Cc: Leon Romanovsky , Jason Gunthorpe ,
 Abdiel Janulgue ,
 Alexander Potapenko , Alex Gaynor
 , Andrew Morton ,
 Christoph Hellwig , Danilo Krummrich ,
 iommu@lists.linux.dev, Jason Wang ,
 Jens Axboe , Joerg Roedel ,
 Jonathan Corbet , kasan-dev@googlegroups.com,
 Keith Busch , linux-block@vger.kernel.org,
 linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org,
 linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
 linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan
 , Masami Hiramatsu ,
 Michael Ellerman , "Michael S. Tsirkin"
 , Miguel Ojeda ,
 Robin Murphy , rust-for-linux@vger.kernel.org,
 Sagi Grimberg , Stefano Stabellini
 , Steven Rostedt ,
 virtualization@lists.linux.dev, Will Deacon ,
 xen-devel@lists.xenproject.org
References: 
 
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From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= 
To: Leon Romanovsky ,
 Marek Szyprowski 
Cc: Leon Romanovsky , Jason Gunthorpe ,
 Abdiel Janulgue ,
 Alexander Potapenko , Alex Gaynor
 , Andrew Morton ,
 Christoph Hellwig , Danilo Krummrich ,
 iommu@lists.linux.dev, Jason Wang ,
 Jens Axboe , Joerg Roedel ,
 Jonathan Corbet , kasan-dev@googlegroups.com,
 Keith Busch , linux-block@vger.kernel.org,
 linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org,
 linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
 linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan
 , Masami Hiramatsu ,
 Michael Ellerman , "Michael S. Tsirkin"
 , Miguel Ojeda ,
 Robin Murphy , rust-for-linux@vger.kernel.org,
 Sagi Grimberg , Stefano Stabellini
 , Steven Rostedt ,
 virtualization@lists.linux.dev, Will Deacon ,
 xen-devel@lists.xenproject.org
Message-ID: 
Subject: Re: [PATCH v1 10/16] xen: swiotlb: Open code map_resource callback
References: 
 
In-Reply-To: 

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Date: Thu, 7 Aug 2025 16:45:37 +0200
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Subject: Re: [PATCH v3 03/20] xen/riscv: introduce VMID allocation and
 manegement
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 
 
 
 <6ddee574-6fe2-4de7-b000-a3af0b2c9d12@suse.com>
 
 
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From: Oleksii Kurochko 
In-Reply-To: 

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On 8/7/25 12:11 PM, Jan Beulich wrote:
>>>>>> +    unsigned long old;
>>>>>> +
>>>>>> +    /* Figure-out number of VMID bits in HW */
>>>>>> +    old = csr_read(CSR_HGATP);
>>>>>> +
>>>>>> +    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
>>>>>> +    vmid_bits = csr_read(CSR_HGATP);
>>>>>> +    vmid_bits =  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);
>>>>> Nit: Stray blank.
>>>>>
>>>>>> +    vmid_bits = flsl(vmid_bits);
>>>>>> +    csr_write(CSR_HGATP, old);
>>>>>> +
>>>>>> +    /*
>>>>>> +     * We polluted local TLB so flush all guest TLB as
>>>>>> +     * a speculative access can happen at any time.
>>>>>> +     */
>>>>>> +    local_hfence_gvma_all();
>>>>> There's no guest running. If you wrote hgat.MODE as zero, as per my
>>>>> understanding now new TLB entries could even purely theoretically appear.
>>>> It could be an issue (or, at least, it is recommended) when hgatp.MODE is
>>>> changed:
>>>>     If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0
>>>>     (and rs2 set to either x0 or the VMID) must be executed to order subsequent
>>>>     guest translations with the MODE change—even if the old MODE or new MODE
>>>>     is Bare.
>>>> On other hand it is guaranteed that, at least, on Reset (and so I assume
>>>> for power on) that:
>>>>     If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE
>>>>     fields are reset to 0.
>>>>
>>>> So it seems like if no guest is ran then there is no need even to write
>>>> hgatp.MODE as zero, but it might be sense to do that explicitly just to
>>>> be sure.
>>>>
>>>> I thought it was possible to have a running guest and perform a CPU hotplug.
>>> But that guest will run on another hart.
>>>
>>>> In that case, I expect that during the hotplug,|vmidlen_detect()| will be
>>>> called and return the|vmid_bits| value, which is used as the active VMID.
>>>> At that moment, the local TLB could be speculatively polluted, I think.
>>>> Likely, it makes sense to call vmidlen_detect() only once for each hart
>>>> during initial bringup.
>>> That may bring you more problems than it solves. You'd need to stash away
>>> the value originally read somewhere. And that somewhere isn't per-CPU data.
>>>
>>>>> In fact, with no guest running (yet) I'm having a hard time seeing why
>>>>> you shouldn't be able to simply write the register with just
>>>>> HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable
>>>>> whether "old" needs restoring; writing plain zero afterwards ought to
>>>>> suffice. You're in charcge of the register, after all.
>>>> It make sense (but I don't know if it is a possible case) to be sure that
>>>> HGATP.MODE remains the same, so there is no need to have TLB flush. If
>>>> HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned
>>>> above.
>>>>
>>>> If we agreed to keep local_hfence_gvma_all() then I think it isn't really
>>>> any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.
>>>>
>>>> Generally if 'old' is guaranteed to be zero (and, probably, it makes sense
>>>> to check that in vmidlen_detect() and panic if it isn't zero) and if
>>>> vmidlen_detect() function will be called before any guest domain(s) will
>>>> be ran then I could agree that we don't need local_hfence_gvma_all() here.
>>>>
>>>> As an option we can do local_hfence_gvma_all() only if 'old' value wasn't
>>>> set to zero.
>>>>
>>>> Does it make sense?
>>> Well - I'd like the pre-conditions to be understood better. For example, can
>>> a hart really speculate into guest mode, when the hart is only in the
>>> process of being brought up?
>> I couldn't explicit words that a hart can't speculate into guest mode
>> either on bring up or during its work.
>>
>> But there are some moments in the spec which tells:
>>     Implementations with virtual memory are permitted to perform address
>>     translations speculatively and earlier than required by an explicit
>>     memory access, and are permitted to cache them in address translation
>>     cache structures—including possibly caching the identity mappings from
>>     effective address to physical address used in Bare translation modes and
>>     M-mode.
>> And here:
>>     Implementations may also execute the address-translation algorithm
>>     speculatively at any time, for any virtual address, as long as satp is
>>     active (as defined in Section 10.1.11). Such speculative executions have
>>     the effect of pre-populating the address-translation cache.
> That's satp though, not hgatp.
>
>> Where it is explicitly mentioned that speculation can happen in*any time*.
>> And at the same time:
>>     Speculative executions of the address-translation algorithm behave as
>>     non-speculative executions of the algorithm do, except that they must
>>     not set the dirty bit for a PTE, they must not trigger an exception,
>>     and they must not create address-translation cache entries if those
>>     entries would have been invalidated by any SFENCE.VMA instruction
>>     executed by the hart since the speculative execution of the algorithm began.
>> What I read as if TLB was empty before it will stay empty.
>>
>> Also, despite of the fact here it is mentioned that when V=0 two-stage address
>> translation is inactivated:
>>     The current virtualization mode, denoted V, indicates whether the hart is
>>     currently executing in a guest. When V=1, the hart is either in virtual
>>     S-mode (VS-mode), or in virtual U-mode (VU-mode) atop a guest OS running
>>     in VS-mode. When V=0, the hart is either in M-mode, in HS-mode, or in
>>     U-mode atop an OS running in HS-mode. The virtualization mode also
>>     indicates whether two-stage address translation is active (V=1) or
>>     inactive (V=0).
>> But on the same side, writing to hgatp register activates it:
>>     The hgatp register is considered active for the purposes of
>>     the address-translation algorithm unless the effective privilege mode
>>     is U and hstatus.HU=0.
>> And if so + considering that speculation could happen at any time, and
>> we are in HS-mode, not it U mode then I would say that it could really
>> speculate into guest mode.
> Hmm, that leaves some things to be desired. What I'm particularly puzzled
> by is that there's nothing said either way towards speculation through SRET.
> That's the important aspect here aiui, because without that the hart can't
> speculate into guest mode.
>
> But yes, in the absence of any clear indication to the contrary, I think
> you want to keep the local_hfence_gvma_all() (with a suitable comment).

Interesting that for VS-stage translation is explicitly mention that it is
possible to stop speculation:
   No mechanism is provided to atomically change vsatp and hgatp together.
   Hence, to prevent speculative execution causing one guest’s VS-stage
   translations to be cached under another guest’s VMID, world-switch code
   should zero vsatp, then swap hgatp, then finally write the new vsatp value.
   Similarly, if henvcfg.PBMTE need be world-switched, it should be switched
   after zeroing vsatp but before writing the new vsatp value, obviating
   the need to execute an HFENCE.VVMA instruction.
So if VSATP is 0 then there is no speculation as there is no need to execute
HFENCE.VVMA.

>
>>>>>> +    data->max_vmid = BIT(vmid_len, U) - 1;
>>>>>> +    data->disabled = !opt_vmid_enabled || (vmid_len <= 1);
>>>>> Actually, what exactly does it mean that "VMIDs are disabled"? There's
>>>>> no enable bit that I could find anywhere. Isn't it rather that in this
>>>>> case you need to arrange to flush always on VM entry (or always after a
>>>>> P2M change, depending how the TLB is split between guest and host use)?
>>>> "VMIDs are disabled" here means that TLB flush will happen each time p2m
>>>> is changed.
>>> That's better described as "VMIDs aren't used" then?
>> It sounds a little bit just like an opposite to "disabled" (i.e. means
>> basically the same), but I am okay to use "used" instead.
> If you want to stick to using "disabled", then how about "VMID use is
> disabled"? (You probably meanwhile understood that what I'm after is it
> becoming clear that this is a software decision, not something you can
> enforce in hardware.)

"VMID use is disabled" really sounds more clear. Thanks.

~ Oleksii

--------------34lT01JwO04vhqMxTRkKLy9A
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 8bit



  
    
  
  
    

    
    
    
    
    On 8/7/25 12:11 PM, Jan Beulich wrote:
    
    
    
    
    
      
    +    unsigned long old;
+
+    /* Figure-out number of VMID bits in HW */
+    old = csr_read(CSR_HGATP);
+
+    csr_write(CSR_HGATP, old | HGATP_VMID_MASK);
+    vmid_bits = csr_read(CSR_HGATP);
+    vmid_bits =  MASK_EXTR(vmid_bits, HGATP_VMID_MASK);

    Nit: Stray blank.


    +    vmid_bits = flsl(vmid_bits);
+    csr_write(CSR_HGATP, old);
+
+    /*
+     * We polluted local TLB so flush all guest TLB as
+     * a speculative access can happen at any time.
+     */
+    local_hfence_gvma_all();

    There's no guest running. If you wrote hgat.MODE as zero, as per my
understanding now new TLB entries could even purely theoretically appear.

    It could be an issue (or, at least, it is recommended) when hgatp.MODE is
changed:
   If hgatp.MODE is changed for a given VMID, an HFENCE.GVMA with rs1=x0
   (and rs2 set to either x0 or the VMID) must be executed to order subsequent
   guest translations with the MODE change—even if the old MODE or new MODE
   is Bare.
On other hand it is guaranteed that, at least, on Reset (and so I assume
for power on) that:
   If the hypervisor extension is implemented, the hgatp.MODE and vsatp.MODE
   fields are reset to 0.

So it seems like if no guest is ran then there is no need even to write
hgatp.MODE as zero, but it might be sense to do that explicitly just to
be sure.

I thought it was possible to have a running guest and perform a CPU hotplug.

    But that guest will run on another hart.


    In that case, I expect that during the hotplug,|vmidlen_detect()| will be
called and return the|vmid_bits| value, which is used as the active VMID.
At that moment, the local TLB could be speculatively polluted, I think.
Likely, it makes sense to call vmidlen_detect() only once for each hart
during initial bringup.

    That may bring you more problems than it solves. You'd need to stash away
the value originally read somewhere. And that somewhere isn't per-CPU data.


    In fact, with no guest running (yet) I'm having a hard time seeing why
you shouldn't be able to simply write the register with just
HGATP_VMID_MASK, i.e. without OR-ing in "old". It's even questionable
whether "old" needs restoring; writing plain zero afterwards ought to
suffice. You're in charcge of the register, after all.

    It make sense (but I don't know if it is a possible case) to be sure that
HGATP.MODE remains the same, so there is no need to have TLB flush. If
HGATP.MODE is changed then it will be needed to do TLB flush as I mentioned
above.

If we agreed to keep local_hfence_gvma_all() then I think it isn't really
any sense to restore 'old' or OR-ing it with HGATP_VMID_MASK.

Generally if 'old' is guaranteed to be zero (and, probably, it makes sense
to check that in vmidlen_detect() and panic if it isn't zero) and if
vmidlen_detect() function will be called before any guest domain(s) will
be ran then I could agree that we don't need local_hfence_gvma_all() here.

As an option we can do local_hfence_gvma_all() only if 'old' value wasn't
set to zero.

Does it make sense?

    Well - I'd like the pre-conditions to be understood better. For example, can
a hart really speculate into guest mode, when the hart is only in the
process of being brought up?

    I couldn't explicit words that a hart can't speculate into guest mode
either on bring up or during its work.

But there are some moments in the spec which tells:
   Implementations with virtual memory are permitted to perform address
   translations speculatively and earlier than required by an explicit
   memory access, and are permitted to cache them in address translation
   cache structures—including possibly caching the identity mappings from
   effective address to physical address used in Bare translation modes and
   M-mode.
And here:
   Implementations may also execute the address-translation algorithm
   speculatively at any time, for any virtual address, as long as satp is
   active (as defined in Section 10.1.11). Such speculative executions have
   the effect of pre-populating the address-translation cache.

    That's satp though, not hgatp.


    Where it is explicitly mentioned that speculation can happen in *any time*.
And at the same time:
   Speculative executions of the address-translation algorithm behave as
   non-speculative executions of the algorithm do, except that they must
   not set the dirty bit for a PTE, they must not trigger an exception,
   and they must not create address-translation cache entries if those
   entries would have been invalidated by any SFENCE.VMA instruction
   executed by the hart since the speculative execution of the algorithm began.
What I read as if TLB was empty before it will stay empty.

Also, despite of the fact here it is mentioned that when V=0 two-stage address
translation is inactivated:
   The current virtualization mode, denoted V, indicates whether the hart is
   currently executing in a guest. When V=1, the hart is either in virtual
   S-mode (VS-mode), or in virtual U-mode (VU-mode) atop a guest OS running
   in VS-mode. When V=0, the hart is either in M-mode, in HS-mode, or in
   U-mode atop an OS running in HS-mode. The virtualization mode also
   indicates whether two-stage address translation is active (V=1) or
   inactive (V=0).
But on the same side, writing to hgatp register activates it:
   The hgatp register is considered active for the purposes of
   the address-translation algorithm unless the effective privilege mode
   is U and hstatus.HU=0.
And if so + considering that speculation could happen at any time, and
we are in HS-mode, not it U mode then I would say that it could really
speculate into guest mode.

    Hmm, that leaves some things to be desired. What I'm particularly puzzled
by is that there's nothing said either way towards speculation through SRET.
That's the important aspect here aiui, because without that the hart can't
speculate into guest mode.

But yes, in the absence of any clear indication to the contrary, I think
you want to keep the local_hfence_gvma_all() (with a suitable comment).
    
    
    
    
    Interesting that for VS-stage translation is explicitly mention that it is
possible to stop speculation:
  No mechanism is provided to atomically change vsatp and hgatp together.
  Hence, to prevent speculative execution causing one guest’s VS-stage
  translations to be cached under another guest’s VMID, world-switch code
  should zero vsatp, then swap hgatp, then finally write the new vsatp value.
  Similarly, if henvcfg.PBMTE need be world-switched, it should be switched
  after zeroing vsatp but before writing the new vsatp value, obviating
  the need to execute an HFENCE.VVMA instruction.
So if VSATP is 0 then there is no speculation as there is no need to execute
HFENCE.VVMA.

    
    
    
      
    

    +    data->max_vmid = BIT(vmid_len, U) - 1;
+    data->disabled = !opt_vmid_enabled || (vmid_len <= 1);

    Actually, what exactly does it mean that "VMIDs are disabled"? There's
no enable bit that I could find anywhere. Isn't it rather that in this
case you need to arrange to flush always on VM entry (or always after a
P2M change, depending how the TLB is split between guest and host use)?

    "VMIDs are disabled" here means that TLB flush will happen each time p2m
is changed.

    That's better described as "VMIDs aren't used" then?

    It sounds a little bit just like an opposite to "disabled" (i.e. means
basically the same), but I am okay to use "used" instead.

    If you want to stick to using "disabled", then how about "VMID use is
disabled"? (You probably meanwhile understood that what I'm after is it
becoming clear that this is a software decision, not something you can
enforce in hardware.)
    
    
    
    
    "VMID use is disabled" really sounds more clear. Thanks.

~ Oleksii

    
  


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From: Oleksii Moisieiev 
To: Oleksii Kurochko , Xen-devel
	
CC: ", Ayan Kumar Halder" , Mykyta Poturai
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	, Community Manager
	
Subject: Re: Xen 4.21 Development Update [June-July]
Thread-Topic: Xen 4.21 Development Update [June-July]
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Subject: Re: [PATCH v3 09/20] xen/dom0less: abstract Arm-specific p2m type
 name for device MMIO mappings
To: Jan Beulich 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 xen-devel@lists.xenproject.org
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 <01442213-1bcb-465c-9e0d-252864ba88c8@suse.com>
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From: Oleksii Kurochko 
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On 8/4/25 4:11 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> Rename `p2m_mmio_direct_dev` to a more architecture-neutral alias
>> `p2m_mmio_direct` to avoid leaking Arm-specific naming into common Xen code,
>> such as dom0less passthrough property handling.
>>
>> This helps reduce platform-specific terminology in shared logic and
>> improves clarity for future non-Arm ports (e.g. RISC-V or PowerPC).
>>
>> No functional changes — the definition is preserved via a macro alias
>> for Arm.
>>
>> Suggested-by: Jan Beulich
> I'm sorry, but no, ...
>
>> --- a/xen/arch/arm/include/asm/p2m.h
>> +++ b/xen/arch/arm/include/asm/p2m.h
>> @@ -137,6 +137,8 @@ typedef enum {
>>       p2m_max_real_type,  /* Types after this won't be store in the p2m */
>>   } p2m_type_t;
>>   
>> +#define p2m_mmio_direct p2m_mmio_direct_dev
> ... this isn't what I suggested. When Arm has three p2m_mmio_direct_*,
> randomly aliasing one to p2m_mmio_direct is imo more likely to create
> confusion than to help things. Imo you want to introduce ...

This is not randomly, this what Arm uses for device's node(s), which is going
to be passthroughed...

>
>> --- a/xen/common/device-tree/dom0less-build.c
>> +++ b/xen/common/device-tree/dom0less-build.c
>> @@ -185,7 +185,7 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo,
>>                                  gaddr_to_gfn(gstart),
>>                                  PFN_DOWN(size),
>>                                  maddr_to_mfn(mstart),
>> -                               p2m_mmio_direct_dev);
>> +                               p2m_mmio_direct);
> ... a per-arch inline function which returns the type to use here.
> The name of the function would want to properly reflect the purpose;
> my limited DT knowledge may make arch_dt_passthrough_p2m_type() an
> entirely wrong suggestion.

... But make it even more generic by providing an inline function which
just return p2m_type_t would be really better.

~ Oleksii

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    On 8/4/25 4:11 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    Rename `p2m_mmio_direct_dev` to a more architecture-neutral alias
`p2m_mmio_direct` to avoid leaking Arm-specific naming into common Xen code,
such as dom0less passthrough property handling.

This helps reduce platform-specific terminology in shared logic and
improves clarity for future non-Arm ports (e.g. RISC-V or PowerPC).

No functional changes — the definition is preserved via a macro alias
for Arm.

Suggested-by: Jan Beulich <jbeulich@suse.com>

    
      
    
      
    I'm sorry, but no, ...


    
      
    
        
    --- a/xen/arch/arm/include/asm/p2m.h
+++ b/xen/arch/arm/include/asm/p2m.h
@@ -137,6 +137,8 @@ typedef enum {
     p2m_max_real_type,  /* Types after this won't be store in the p2m */
 } p2m_type_t;
 
+#define p2m_mmio_direct p2m_mmio_direct_dev

    
      
    
      
    ... this isn't what I suggested. When Arm has three p2m_mmio_direct_*,
randomly aliasing one to p2m_mmio_direct is imo more likely to create
confusion than to help things. Imo you want to introduce ...
    
    
    
    
    This is not randomly, this what Arm uses for device's node(s), which is going
to be passthroughed...
    
    
    
      
    

    
      
    
        
    --- a/xen/common/device-tree/dom0less-build.c
+++ b/xen/common/device-tree/dom0less-build.c
@@ -185,7 +185,7 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo,
                                gaddr_to_gfn(gstart),
                                PFN_DOWN(size),
                                maddr_to_mfn(mstart),
-                               p2m_mmio_direct_dev);
+                               p2m_mmio_direct);

    
      
    
      
    ... a per-arch inline function which returns the type to use here.
The name of the function would want to properly reflect the purpose;
my limited DT knowledge may make arch_dt_passthrough_p2m_type() an
entirely wrong suggestion.
    
    
    
    
    ... But make it even more generic by providing an inline function which
just return p2m_type_t would be really better.

    
    
    ~ Oleksii

    
  


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Subject: Re: [PATCH v3 06/20] xen/riscv: add root page table allocation
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com>
 <3c02593f-deae-4109-9334-0ac4376a9a9e@suse.com>
 
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On 07.08.2025 14:00, Oleksii Kurochko wrote:
> On 8/5/25 12:37 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> +    /*
>>> +     * Return back nr_root_pages to assure the root table memory is also
>>> +     * accounted against the P2M pool of the domain.
>>> +     */
>>> +    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
>>> +        return -ENOMEM;
>>> +
>>> +    page = p2m_allocate_root(d);
>>> +    if ( !page )
>>> +        return -ENOMEM;
>> Hmm, and the pool is then left shrunk by 4 pages?
> 
> Yes until they are used for root table it shouldn't be in p2m pool (freelist),
> when root table will be freed then it makes sense to return them back.
> Am I missing something?

I'm commenting specifically on the error path here.

> Probably, you meant that it is needed to update p2m->pages?

That (I think) I commented on elsewhere, yes.

Jan


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Subject: Re: [PATCH v3 08/20] xen/riscv: add new p2m types and helper macros
 for type classification
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <3d35b6f4bb79048647020ed4e7b222585ca3a9a3.1753973161.git.oleksii.kurochko@gmail.com>
 <48dcca92-4dd8-4d6e-a4cb-c10a7ee80f19@suse.com>
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From: Oleksii Kurochko 
In-Reply-To: <48dcca92-4dd8-4d6e-a4cb-c10a7ee80f19@suse.com>

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On 8/4/25 4:16 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> - Extended p2m_type_t with additional types: p2m_mmio_direct,
>>    p2m_grant_map_{rw,ro}.
>> - Added macros to classify memory types: P2M_RAM_TYPES, P2M_GRANT_TYPES.
>> - Introduced helper predicates: p2m_is_ram(), p2m_is_any_ram().
>> - Define p2m_mmio_direct to tell handle_passthrough_prop() from common
>>    code how to map device memory.
>>
>> Signed-off-by: Oleksii Kurochko
> Almost ready to be acked, except for ...
>
>> --- a/xen/arch/riscv/include/asm/p2m.h
>> +++ b/xen/arch/riscv/include/asm/p2m.h
>> @@ -62,8 +62,30 @@ struct p2m_domain {
>>   typedef enum {
>>       p2m_invalid = 0,    /* Nothing mapped here */
>>       p2m_ram_rw,         /* Normal read/write domain RAM */
>> +    p2m_mmio_direct_io, /* Read/write mapping of genuine Device MMIO area,
>> +                           PTE_PBMT_IO will be used for such mappings */
>> +    p2m_ext_storage,    /* Following types'll be stored outsude PTE bits: */
>> +    p2m_grant_map_rw,   /* Read/write grant mapping */
>> +    p2m_grant_map_ro,   /* Read-only grant mapping */
>>   } p2m_type_t;
>>   
>> +#define p2m_mmio_direct p2m_mmio_direct_io
> ... this (see reply to patch 09).
>
>> +/* We use bitmaps and mask to handle groups of types */
>> +#define p2m_to_mask(t_) BIT(t_, UL)
> I notice that you moved the underscore to the back of the parameters,
> compared to how Arm has it. I wonder though: What use are these
> underscores in the first place, here and below? (There are macros where
> conflicts could arise, but the ones here don't fall in that group,
> afaict.)

Good point, there is really no name conflicts here, so underscore could
be just dropped.

~ Oleksii

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    On 8/4/25 4:16 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    - Extended p2m_type_t with additional types: p2m_mmio_direct,
  p2m_grant_map_{rw,ro}.
- Added macros to classify memory types: P2M_RAM_TYPES, P2M_GRANT_TYPES.
- Introduced helper predicates: p2m_is_ram(), p2m_is_any_ram().
- Define p2m_mmio_direct to tell handle_passthrough_prop() from common
  code how to map device memory.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

    
      
    
      
    Almost ready to be acked, except for ...


    
      
    
        
    --- a/xen/arch/riscv/include/asm/p2m.h
+++ b/xen/arch/riscv/include/asm/p2m.h
@@ -62,8 +62,30 @@ struct p2m_domain {
 typedef enum {
     p2m_invalid = 0,    /* Nothing mapped here */
     p2m_ram_rw,         /* Normal read/write domain RAM */
+    p2m_mmio_direct_io, /* Read/write mapping of genuine Device MMIO area,
+                           PTE_PBMT_IO will be used for such mappings */
+    p2m_ext_storage,    /* Following types'll be stored outsude PTE bits: */
+    p2m_grant_map_rw,   /* Read/write grant mapping */
+    p2m_grant_map_ro,   /* Read-only grant mapping */
 } p2m_type_t;
 
+#define p2m_mmio_direct p2m_mmio_direct_io

    
      
    
      
    ... this (see reply to patch 09).


    
      
    
        
    +/* We use bitmaps and mask to handle groups of types */
+#define p2m_to_mask(t_) BIT(t_, UL)

    
      
    
      
    I notice that you moved the underscore to the back of the parameters,
compared to how Arm has it. I wonder though: What use are these
underscores in the first place, here and below? (There are macros where
conflicts could arise, but the ones here don't fall in that group,
afaict.)
    
    
    
    
    Good point, there is really no name conflicts here, so underscore could
be just dropped.

~ Oleksii

    
  


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From: Ayan Kumar Halder 
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Subject: [ImageBuilder] Make DEVICE_TREE optional parameter
Date: Thu, 7 Aug 2025 16:46:14 +0100
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There are systems where device tree binary is passed by the U-Boot as
$fdtcontroladdr. In such cases, no external device tree binary is provided
during uboot script generation.

This is an enhancement on top of the following commit:-
uboot-script-gen: Dynamically compute addr and size when loading bina…

When DEVICE_TREE is not present, $CALC is set as the addresses and sizes should
be computed dynamically from U-Boot.

Signed-off-by: Ayan Kumar Halder 
---
 README.md                |  3 ++-
 scripts/uboot-script-gen | 26 +++++++++++++++++++-------
 2 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/README.md b/README.md
index 4be6efb..d80bdc9 100644
--- a/README.md
+++ b/README.md
@@ -90,7 +90,8 @@ Where:
   DTB are stored in 'host_kernel_addr' and 'host_fdt_addr' u-boot
   env variables respectively, to be used manually when booting.
 
-- DEVICE_TREE specifies the DTB file to load.
+- DEVICE_TREE specifies the DTB file to load. If not set, then $fdtcontroladdr
+  is used as the address of the DTB loaded by u-boot.
 
 - XEN specifies the Xen hypervisor binary to load. Note that it has to
   be a regular Xen binary, not a u-boot binary.
diff --git a/scripts/uboot-script-gen b/scripts/uboot-script-gen
index fed53aa..9fe4a55 100755
--- a/scripts/uboot-script-gen
+++ b/scripts/uboot-script-gen
@@ -560,7 +560,7 @@ function device_tree_editing()
     if test $UBOOT_SOURCE
     then
         if test "$CALC"; then
-            echo "fdt addr \${host_fdt_addr}" >> $UBOOT_SOURCE
+            echo "fdt addr \${fdtcontroladdr}" >> $UBOOT_SOURCE
         else
             echo "fdt addr $device_tree_addr" >> $UBOOT_SOURCE
         fi
@@ -591,7 +591,7 @@ function device_tree_editing()
 
 function fill_reserved_spaces_from_dtb()
 {
-    if [ ! -f $DEVICE_TREE ]
+    if test ! -f $DEVICE_TREE || test -z ${DEVICE_TREE+x}
     then
         if test "$CALC"; then
             return
@@ -1502,6 +1502,11 @@ check_depends
 declare -A DOMU_VCPU_HARD_AFFINITY
 source "$cfg_file"
 
+if test -z ${DEVICE_TREE+x}
+then
+    CALC=y
+fi
+
 SCRIPT_PATH=$(dirname "$0")
 source "$SCRIPT_PATH/common"
 source "$SCRIPT_PATH/xen_dt_domu"
@@ -1703,9 +1708,13 @@ then
     done
 fi
 
-check_file_type $DEVICE_TREE "Device Tree Blob"
-device_tree_addr=$memaddr
-load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
+if test ${DEVICE_TREE+x}
+then
+    check_file_type $DEVICE_TREE "Device Tree Blob"
+    device_tree_addr=$memaddr
+    load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
+fi
+
 bitstream_load_and_config  # bitstream is loaded last but used first
 device_tree_editing $device_tree_addr
 
@@ -1727,14 +1736,17 @@ fi
 if [ "$BOOT_CMD" != "none" ]
 then
     if test "$CALC"; then
-        echo "$BOOT_CMD \${host_kernel_addr} $([ "$BOOT_CMD" = "bootefi" ] || echo '-') \${host_fdt_addr}" >> $UBOOT_SOURCE
+        echo "$BOOT_CMD \${host_kernel_addr} $([ "$BOOT_CMD" = "bootefi" ] || echo '-') \${fdtcontroladdr}" >> $UBOOT_SOURCE
     else
         echo "$BOOT_CMD $kernel_addr $([ "$BOOT_CMD" = "bootefi" ] || echo '-') $device_tree_addr" >> $UBOOT_SOURCE
     fi
 else
     # skip boot command but store load addresses to be used later
     echo "setenv host_kernel_addr $kernel_addr" >> $UBOOT_SOURCE
-    echo "setenv host_fdt_addr $device_tree_addr" >> $UBOOT_SOURCE
+    if test ${DEVICE_TREE+x}
+    then
+        echo "setenv host_fdt_addr $device_tree_addr" >> $UBOOT_SOURCE
+    fi
 fi
 
 if test "$FIT"
-- 
2.25.1



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On 07.08.2025 15:35, Oleksii Kurochko wrote:
> 
> On 8/5/25 12:43 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> +static int p2m_alloc_root_table(struct p2m_domain *p2m)
>>> +{
>>> +    struct domain *d = p2m->domain;
>>> +    struct page_info *page;
>>> +    const unsigned int nr_root_pages = P2M_ROOT_PAGES;
>>> +
>>> +    /*
>>> +     * Return back nr_root_pages to assure the root table memory is also
>>> +     * accounted against the P2M pool of the domain.
>>> +     */
>>> +    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
>>> +        return -ENOMEM;
>>> +
>>> +    page = p2m_allocate_root(d);
>>> +    if ( !page )
>>> +        return -ENOMEM;
>>> +
>>> +    p2m->root = page;
>>> +
>>> +    return 0;
>>> +}
>> In the success case, shouldn't you bump the paging pool's total_pages by
>> P2M_ROOT_PAGES? (As the freeing side is missing so far, it's not easy to
>> tell whether there's [going to be] a balancing problem in the long run.
>> In the short run there certainly is.)
> 
> I think that total_pages should be updated only in case when page is added
> to freelist.
> In the case of p2m root table, we just returning some pages to domheap and
> durint that decreasing an amount of total_pages as freelist has lesser pages,
> and then just allocate pages from domheap without adding them to freelist.

But how's freeing of a root table going to look like? Logically that group
of 4 pages would be put back into the pool. And from that the pool's
total_pages should reflect that right after successful allocation.

Jan


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Date: Thu, 7 Aug 2025 17:59:22 +0200
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Subject: Re: [PATCH v3 06/20] xen/riscv: add root page table allocation
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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References: 
 <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com>
 <3c02593f-deae-4109-9334-0ac4376a9a9e@suse.com>
 
 
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On 8/7/25 5:30 PM, Jan Beulich wrote:
> On 07.08.2025 14:00, Oleksii Kurochko wrote:
>> On 8/5/25 12:37 PM, Jan Beulich wrote:
>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>> +    /*
>>>> +     * Return back nr_root_pages to assure the root table memory is also
>>>> +     * accounted against the P2M pool of the domain.
>>>> +     */
>>>> +    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
>>>> +        return -ENOMEM;
>>>> +
>>>> +    page = p2m_allocate_root(d);
>>>> +    if ( !page )
>>>> +        return -ENOMEM;
>>> Hmm, and the pool is then left shrunk by 4 pages?
>> Yes until they are used for root table it shouldn't be in p2m pool (freelist),
>> when root table will be freed then it makes sense to return them back.
>> Am I missing something?
> I'm commenting specifically on the error path here.

Ohh, got it.

In this case, should we really care about this 4 pages as a domain can't be ran
without allocated page root table and a panic() will be occured anyway according
to the create_domUs() common code (construct_domU() -> domain_p2m_set_allocation()
-> p2m_set_allocation() -> p2m_alloc_root_table()):
...
         rc = construct_domU(&ki, node);
         if ( rc )
             panic("Could not set up domain %s (rc = %d)\n",
                   dt_node_name(node), rc);
...
(Note: I missed to return a value returned by p2m_alloc_root_table() in p2m_set_allocation()
so it isn't really propagated, at the moment, but I will fix that in the next patch
version) ...

>> Probably, you meant that it is needed to update p2m->pages?
> That (I think) I commented on elsewhere, yes.
...

if it is needed really to update p2m->pages when a page is allocated, I think
it will be better to in p2m_allocate_root() immediately after alloc_domheap_pages()
is called in p2m_allocate_root().

~ Oleksii


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    On 8/7/25 5:30 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 07.08.2025 14:00, Oleksii Kurochko wrote:

    
      
    
        
    On 8/5/25 12:37 PM, Jan Beulich wrote:

    
        
    
          
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
          
    
            
    +    /*
+     * Return back nr_root_pages to assure the root table memory is also
+     * accounted against the P2M pool of the domain.
+     */
+    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
+        return -ENOMEM;
+
+    page = p2m_allocate_root(d);
+    if ( !page )
+        return -ENOMEM;

    
          
    
          
    Hmm, and the pool is then left shrunk by 4 pages?

    
        
    
        
    Yes until they are used for root table it shouldn't be in p2m pool (freelist),
when root table will be freed then it makes sense to return them back.
Am I missing something?

    
      
    
      
    I'm commenting specifically on the error path here.
    
    
    
    
    Ohh, got it.

In this case, should we really care about this 4 pages as a domain can't be ran
without allocated page root table and a panic() will be occured anyway according
to the create_domUs() common code (construct_domU() -> domain_p2m_set_allocation()
-> p2m_set_allocation() -> p2m_alloc_root_table()):
...
        rc = construct_domU(&ki, node);
        if ( rc )
            panic("Could not set up domain %s (rc = %d)\n",
                  dt_node_name(node), rc);
...
(Note: I missed to return a value returned by p2m_alloc_root_table() in p2m_set_allocation()
so it isn't really propagated, at the moment, but I will fix that in the next patch
version) ...


    
    
    
      
    
      
    
        
    Probably, you meant that it is needed to update p2m->pages?

    
      
    
      
    That (I think) I commented on elsewhere, yes.
    
    
    
    ... 
    
    
    if it is needed really to update p2m->pages when a page is allocated, I think
it will be better to in p2m_allocate_root() immediately after alloc_domheap_pages()
is called in p2m_allocate_root().


    
    
    ~ Oleksii

    
    
    
  


--------------5KcyPkjop0awM4nKFAFs0bwU--


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Subject: Re: [PATCH v3 06/20] xen/riscv: add root page table allocation
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com>
 <3c02593f-deae-4109-9334-0ac4376a9a9e@suse.com>
 
 
 <9fec023f-3b93-49a4-8ee2-ab2194951b19@gmail.com>
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From: Jan Beulich 
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On 07.08.2025 17:59, Oleksii Kurochko wrote:
> On 8/7/25 5:30 PM, Jan Beulich wrote:
>> On 07.08.2025 14:00, Oleksii Kurochko wrote:
>>> On 8/5/25 12:37 PM, Jan Beulich wrote:
>>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>>> +    /*
>>>>> +     * Return back nr_root_pages to assure the root table memory is also
>>>>> +     * accounted against the P2M pool of the domain.
>>>>> +     */
>>>>> +    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
>>>>> +        return -ENOMEM;
>>>>> +
>>>>> +    page = p2m_allocate_root(d);
>>>>> +    if ( !page )
>>>>> +        return -ENOMEM;
>>>> Hmm, and the pool is then left shrunk by 4 pages?
>>> Yes until they are used for root table it shouldn't be in p2m pool (freelist),
>>> when root table will be freed then it makes sense to return them back.
>>> Am I missing something?
>> I'm commenting specifically on the error path here.
> 
> Ohh, got it.
> 
> In this case, should we really care about this 4 pages as a domain can't be ran
> without allocated page root table and a panic() will be occured anyway according
> to the create_domUs() common code (construct_domU() -> domain_p2m_set_allocation()
> -> p2m_set_allocation() -> p2m_alloc_root_table()):
> ...
>          rc = construct_domU(&ki, node);
>          if ( rc )
>              panic("Could not set up domain %s (rc = %d)\n",
>                    dt_node_name(node), rc);

Well, that's for dom0less. Even for tool-stack created VMs there would be
no problem. But root tables required on demand (altp2m, nested) would be
different. So what you do here may be good enough for now, but likely will
want improving later on. (Such temporary restrictions may want putting
down somewhere.)

Jan


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From: Leonid Komarianskyi 
To: Oleksii Kurochko , Xen-devel
	
CC: Oleksii Moisieiev , Ayan Kumar Halder
	, Mykyta Poturai ,
	Juergen Gross , Teddy Astie ,
	Bertrand Marquis , Luca Fancellu
	, "Jason Andryuk," , Alejandro
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	, Mykola Kvach , "Daniel P. Smith"
	, Grygorii Strashko ,
	Alejandro Vallejo , "committers@xenproject.org"
	, Community Manager
	
Subject: Re: Xen 4.21 Development Update [June-July]
Thread-Topic: Xen 4.21 Development Update [June-July]
Thread-Index: AQHcB7VdyMkZhhqGnEisplRAacP5HQ==
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From: Bertrand Marquis 
To: Oleksii Kurochko 
CC: Xen-devel , Oleksii Moisieiev
	, ", Ayan Kumar Halder"
	, Mykyta Poturai ,
	Juergen Gross , Teddy Astie , Luca
 Fancellu , "Jason Andryuk," ,
	Alejandro Vallejo , Sergii Dmytruk
	, "Penny Zheng," ,
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	, Roger Pau Monne ,
	Andrew Cooper , "dmkhn@proton.me"
	, Mykola Kvach , "Daniel P. Smith"
	, Grygorii Strashko ,
	Alejandro Vallejo , "committers@xenproject.org"
	, Community Manager
	
Subject: Re: Xen 4.21 Development Update [June-July]
Thread-Topic: Xen 4.21 Development Update [June-July]
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Date: Thu, 7 Aug 2025 18:20:58 +0200
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Subject: Re: Xen 4.21 Development Update [June-July]
To: Jan Beulich , Andrew Cooper
 ,
 "committers@xenproject.org" 
Cc: Oleksii Moisieiev ,
 Ayan Kumar Halder ,
 Mykyta Poturai , Juergen Gross ,
 Teddy Astie ,
 Bertrand Marquis ,
 Luca Fancellu , "Jason Andryuk,"
 , Sergii Dmytruk ,
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 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki=2C?=
 , Roger Pau Monne ,
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From: Oleksii Kurochko 
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On 8/6/25 10:12 AM, Jan Beulich wrote:
> On 06.08.2025 09:45, Oleksii Kurochko wrote:
>> On 8/6/25 8:05 AM, Jan Beulich wrote:
>>> Overall: There are very many items on this list, and it seems entirely clear to
>>> me that not all of them will make it. I think it would be quite helpful to strip
>>> down the set for 4.21 to some realistic subset. Maybe something to discuss on
>>> the community call later today?
>> Good point, lets discuss that tomorrow during the community call.
> Oh, right, it's only Wednesday today.

I had the Xen Community Call marked at 6 PM in my calendar, so I missed it as
it actually took place at 15:00... I'm not sure if a recording is available
somewhere, but based on the notes:
     Call for major work items for 4.21 or 4.22
         Please make yourself known if you are intending to work on major items
         PDX compression.
         FRED, AVX10, APX, and AMX support (x86)
         Host UEFI Secure Boot
         FF-A 1.2 Support (Arm)

I completely agree with the first point — it would be great to receive feedback
from the authors of major patch series, similar to how the team at EPAM does.

As for the other items, I assume this is a list of major work items that are
likely to slip to 4.22, correct? From the looks of it, PDX compression and
FRED-related work might still make it into 4.21.

I also wanted to ask this during the call, but since I missed it,
I’ll ask here instead:
What should be the criteria for continuing to track a patch series?
It seems that the best approach would be to rely on feedback from the series'
author. However, obtaining that feedback can be challenging. So perhaps the
only practical solution is to keep tracking major items throughout the current
release cycle and drop them at the start of the next cycle if no activity has
taken place.

P.S.: Andrew, could you please provide a list for FRED connected patch series,
I am tracking some of them, but wanted to be sure that I'm tracking all of them.
Thanks in advance.

~ Oleksii

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    On 8/6/25 10:12 AM, Jan Beulich wrote:
    
    
    
    
    
      
    On 06.08.2025 09:45, Oleksii Kurochko wrote:

    
      
    
        
    On 8/6/25 8:05 AM, Jan Beulich wrote:

    
        
    
          
    Overall: There are very many items on this list, and it seems entirely clear to
me that not all of them will make it. I think it would be quite helpful to strip
down the set for 4.21 to some realistic subset. Maybe something to discuss on
the community call later today?

    
        
    
        
    Good point, lets discuss that tomorrow during the community call.

    
      
    
      
    Oh, right, it's only Wednesday today.
    
    
    
    
    I had the Xen Community Call marked at 6 PM in my calendar, so I missed it as
it actually took place at 15:00... I'm not sure if a recording is available
somewhere, but based on the notes:
    Call for major work items for 4.21 or 4.22
        Please make yourself known if you are intending to work on major items
        PDX compression.
        FRED, AVX10, APX, and AMX support (x86)
        Host UEFI Secure Boot
        FF-A 1.2 Support (Arm)

I completely agree with the first point — it would be great to receive feedback
from the authors of major patch series, similar to how the team at EPAM does.

As for the other items, I assume this is a list of major work items that are
likely to slip to 4.22, correct? From the looks of it, PDX compression and
FRED-related work might still make it into 4.21.

I also wanted to ask this during the call, but since I missed it,
I’ll ask here instead:
What should be the criteria for continuing to track a patch series?
It seems that the best approach would be to rely on feedback from the series'
author. However, obtaining that feedback can be challenging. So perhaps the
only practical solution is to keep tracking major items throughout the current
release cycle and drop them at the start of the next cycle if no activity has
taken place.

P.S.: Andrew, could you please provide a list for FRED connected patch series,
I am tracking some of them, but wanted to be sure that I'm tracking all of them.
Thanks in advance.

~ Oleksii
    
  


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Date: Thu, 7 Aug 2025 18:11:16 +0100
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Subject: Re: [PATCH 2/2] x86/mm: correct PG_log_dirty definition
To: Jan Beulich ,
 "xen-devel@lists.xenproject.org" 
Cc: Julien Grall , Stefano Stabellini
 , Anthony PERARD ,
 Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Penny Zheng 
References: 
 <65e27b35-9256-4ab0-966a-c50a18900ba5@suse.com>
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From: Andrew Cooper 
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On 05/08/2025 8:59 am, Jan Beulich wrote:
> While it is correct that in shim-exclusive mode log-dirty handling is
> all unreachable code, the present conditional still isn't correct: In a
> HVM=n and SHADOW_PAGING=n configuration log-dirty code also is all
> unreachable (and hence violating Misra rule 2.1).
>
> As we're aiming at moving away from special casing PV_SHIM_EXCLUSIVE=y,
> don't retain that part of the conditional.
>
> Because of hypercall-defs.c we need to carry out the dependency by
> introducing a new auxiliary PAGING control.
>
> Since compiling out mm/paging.c altogether would entail further changes,
> merely conditionalize the one function in there (paging_enable()) which
> would otherwise remain unreachable (Misra rule 2.1 again) when PAGING=n.
>
> Fixes: 23d4e0d17b76 ("x86/shim: fix build with PV_SHIM_EXCLUSIVE and SHADOW_PAGING")
> Signed-off-by: Jan Beulich 

Acked-by: Andrew Cooper 

> ---
> Of course PAGING is at risk of being confused with MEM_PAGING. It not
> having a prompt, I hope that's tolerable, as I can't really think of a
> better name.

Honestly, PAGING is a bad name start with.  While it is to do with the
handling of pages, it is specifically not what people think of when
using the term paging.

Hence why we've got MEM_PAGING too, which is referring to what most
people think of when told the name paging.

I don't have a better suggestion, given the current codebase, but I'm
open to suggestions.

~Andrew


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Date: Thu, 7 Aug 2025 19:29:57 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Jan Beulich 
Cc: Andrew Cooper ,
	xen-devel 
Subject: Re: S3 regression related to XSA-471 patches
Message-ID: 
References: 
 
 
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Date: Thu, 7 Aug 2025 19:29:57 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Jan Beulich 
Cc: Andrew Cooper ,
	xen-devel 
Subject: Re: S3 regression related to XSA-471 patches

On Wed, Aug 06, 2025 at 12:46:36PM +0200, Marek Marczykowski-G=C3=B3recki w=
rote:
> On Wed, Aug 06, 2025 at 12:36:56PM +0200, Jan Beulich wrote:
> > On 06.08.2025 12:23, Marek Marczykowski-G=C3=B3recki wrote:
> > > We've got several reports that S3 reliability recently regressed. We
> > > identified it's definitely related to XSA-471 patches, and bisection
> > > points at "x86/idle: Remove broken MWAIT implementation". I don't have
> > > reliable reproduction steps, so I'm not 100% sure if it's really this
> > > patch, or maybe an earlier one - but it's definitely already broken at
> > > this point in the series. Most reports are about Xen 4.17 (as that's
> > > what stable Qubes OS version currently use), but I think I've seen
> > > somebody reporting the issue on 4.19 too (but I don't have clear
> > > evidence, especially if it's the same issue).
> >=20
> > At the time we've been discussing the explicit raising of TIMER_SOFTIRQ
> > in mwait_idle_with_hints() a lot. If it was now truly missing, that imo
> > shouldn't cause problems only after resume, but then it may have covered
> > for some omission during resume. As a far-fetched experiment, could you
> > try putting that back (including the calculation of the "expires" local
> > variable)?
>=20
> Sure, I'll try.

It appears this fixes the issue, at least in ~10 attempts so far
(usually I could reproduce the issue after 2-3 attempts).

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Date: Thu, 07 Aug 2025 17:43:57 +0000
To: Oleksii Kurochko 
From: dmkhn@proton.me
Cc: Jan Beulich , andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 1/8] xen/domain: introduce common emulation flags
Message-ID: 
In-Reply-To: <5b604ac0-c832-496f-85b4-6261cbe06fcd@gmail.com>
References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-2-dmukhin@ford.com>   <5b604ac0-c832-496f-85b4-6261cbe06fcd@gmail.com>
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On Thu, Aug 07, 2025 at 04:28:20PM +0200, Oleksii Kurochko wrote:
[..]
> Hi Arm/RISC-V maintainers,
>=20
> Do you foresee any need in bubbling up emulation_flags to the common `str=
uct
> domain`?
> 
>     
>     
    At the moment, in RISC-V's downstream branches emulation_flags i=
sn't used. And,
> for now, I am not really sure that it's going to be used in the nearest f=
uture.

Thank you, I'll drop that patch.



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From: Ayan Kumar Halder 
To: 
CC: Ayan Kumar Halder , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , "Volodymyr
 Babchuk" 
Subject: [PATCH v1 0/2] R52 MPU support (for "Third series for R82 MPU")
Date: Thu, 7 Aug 2025 18:45:27 +0100
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Hi all,

This series is related to
"[PATCH 0/5] Third series for R82 MPU support". There is no build dependency
between the two series.

At the end of these 2 series, R82 and R52 boot till the same point
(approximately).

Kind regards,
Ayan

Ayan Kumar Halder (2):
  arm/mpu: Enable is_xen_heap_page and co for ARM_32
  arm/mpu: Disable map_domain_page for MPU

 xen/arch/arm/Kconfig              |  2 +-
 xen/arch/arm/include/asm/mm.h     |  2 --
 xen/arch/arm/include/asm/mpu/mm.h |  5 ----
 xen/arch/arm/mpu/domain-page.c    | 45 -------------------------------
 4 files changed, 1 insertion(+), 53 deletions(-)
 delete mode 100644 xen/arch/arm/mpu/domain-page.c

-- 
2.25.1



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	, Michal Orzel , "Volodymyr
 Babchuk" 
Subject: [PATCH v1 1/2] arm/mpu: Enable is_xen_heap_page and co for ARM_32
Date: Thu, 7 Aug 2025 18:45:28 +0100
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In case of ARM_32, all of the RAM will be covered by a permanent contiguous
mapping (where VA == PA) and there will be a single heap. Thus, the memory
allocated from Xen heap uses PGC_xen_heap.
This is similar to the scenario described for
"CONFIG_SEPARATE_XENHEAP=n W/ DIRECT MAP OF ALL RAM" in common/page_alloc.c.

Signed-off-by: Ayan Kumar Halder 
---
 xen/arch/arm/include/asm/mm.h     | 2 --
 xen/arch/arm/include/asm/mpu/mm.h | 5 -----
 2 files changed, 7 deletions(-)

diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h
index fb79aeb088..4eaa81d5e8 100644
--- a/xen/arch/arm/include/asm/mm.h
+++ b/xen/arch/arm/include/asm/mm.h
@@ -170,11 +170,9 @@ struct page_info
 #define _PGC_need_scrub   _PGC_allocated
 #define PGC_need_scrub    PGC_allocated
 
-#ifdef CONFIG_ARM_64
 #define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap)
 #define is_xen_heap_mfn(mfn) \
     (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn)))
-#endif
 
 #define is_xen_fixed_mfn(mfn)                                   \
     ((mfn_to_maddr(mfn) >= virt_to_maddr(&_start)) &&           \
diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
index c32fac8905..e1ded6521d 100644
--- a/xen/arch/arm/include/asm/mpu/mm.h
+++ b/xen/arch/arm/include/asm/mpu/mm.h
@@ -27,11 +27,6 @@ extern pr_t xen_mpumap[MAX_MPU_REGION_NR];
 
 #define virt_to_maddr(va) ((paddr_t)((vaddr_t)(va) & PADDR_MASK))
 
-#ifdef CONFIG_ARM_32
-#define is_xen_heap_page(page) ({ BUG_ON("unimplemented"); false; })
-#define is_xen_heap_mfn(mfn) ({ BUG_ON("unimplemented"); false; })
-#endif
-
 /* On MPU systems there is no translation, ma == va. */
 static inline void *maddr_to_virt(paddr_t ma)
 {
-- 
2.25.1



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From: Ayan Kumar Halder 
To: 
CC: Ayan Kumar Halder , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , "Volodymyr
 Babchuk" 
Subject: [PATCH v1 2/2] arm/mpu: Disable map_domain_page for MPU
Date: Thu, 7 Aug 2025 18:45:29 +0100
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There is no domheap for ARM_32. All of the RAM is mapped and VA == PA.

Signed-off-by: Ayan Kumar Halder 
---
 xen/arch/arm/Kconfig           |  2 +-
 xen/arch/arm/mpu/domain-page.c | 45 ----------------------------------
 2 files changed, 1 insertion(+), 46 deletions(-)
 delete mode 100644 xen/arch/arm/mpu/domain-page.c

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index a0c8160474..5355534f3d 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -1,7 +1,7 @@
 config ARM_32
 	def_bool y
 	depends on "$(ARCH)" = "arm32"
-	select ARCH_MAP_DOMAIN_PAGE
+	select ARCH_MAP_DOMAIN_PAGE if MMU
 
 config ARM_64
 	def_bool y
diff --git a/xen/arch/arm/mpu/domain-page.c b/xen/arch/arm/mpu/domain-page.c
deleted file mode 100644
index df5e06b6db..0000000000
--- a/xen/arch/arm/mpu/domain-page.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include 
-#include 
-#include 
-#include 
-
-void *map_domain_page_global(mfn_t mfn)
-{
-    BUG_ON("unimplemented");
-    return NULL;
-}
-
-/* Map a page of domheap memory */
-void *map_domain_page(mfn_t mfn)
-{
-    BUG_ON("unimplemented");
-    return NULL;
-}
-
-/* Release a mapping taken with map_domain_page() */
-void unmap_domain_page(const void *ptr)
-{
-    BUG_ON("unimplemented");
-}
-
-mfn_t domain_page_map_to_mfn(const void *ptr)
-{
-    BUG_ON("unimplemented");
-    return INVALID_MFN;
-}
-
-void unmap_domain_page_global(const void *va)
-{
-    BUG_ON("unimplemented");
-}
-
-/*
- * Local variables:
- * mode: C
- * c-file-style: "BSD"
- * c-basic-offset: 4
- * indent-tabs-mode: nil
- * End:
- */
-- 
2.25.1



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Date: Thu, 07 Aug 2025 17:54:01 +0000
To: =?utf-8?Q?Roger_Pau_Monn=C3=A9?= 
From: dmkhn@proton.me
Cc: Jan Beulich , andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, sstabellini@kernel.org, oleksii.kurochko@gmail.com, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 1/8] xen/domain: introduce common emulation flags
Message-ID: 
In-Reply-To: 
References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-2-dmukhin@ford.com>   
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On Wed, Aug 06, 2025 at 03:56:42PM +0200, Roger Pau Monn=C3=A9 wrote:
> On Tue, Aug 05, 2025 at 12:54:31AM +0000, dmkhn@proton.me wrote:
> > + Cc: Oleskii
> >
> > On Mon, Aug 04, 2025 at 11:46:36AM +0200, Jan Beulich wrote:
> > > On 31.07.2025 21:21, dmkhn@proton.me wrote:
> > > > --- a/xen/include/xen/sched.h
> > > > +++ b/xen/include/xen/sched.h
> > > > @@ -652,6 +652,8 @@ struct domain
> > > >      unsigned int *llc_colors;
> > > >  #endif
> > > >
> > > > +    uint32_t emulation_flags;
> > >
> > > Just one further remark: The field probably never should have been of=
 this
> > > type; unsigned int will do, and imo will want switching to while the =
field
> > > is being moved. (Before giving an x86 ack, I want to convince myself =
though
> > > that this is moving us in the right direction.)
> >
> > Hi Jan,
> >
> > I can definitely use different mechanism for virt ns16550: add a new fi=
eld in
> > xen_arch_domainconfig. That will also simplify some of the emulation_fl=
ags
> > checks on x86 and will be more flexible wrt emulator configuration (e.g=
. I can
> > allow passing I/O ports ranges).
>=20
> For the time being, I would leave emulation_flags in
> xen_arch_domainconfig.

Ack; agreed.

>  The set of emulated devices is
> architecture-specific, and pulling it to the generic struct is IMO not
> specially helpful, as you then have the definition of the flags
> decoupled from the field definition.

NS16550 is not an arch-specific device though.
But yes, current implementation _is_ arch-specific.

>=20
> For the emulated UART, I don't think you need a new field in
> xen_arch_domainconfig, just a new bit in emulation_flags? IOW:

I think new field is needed, since there are four legacy PC UART resource
sets selectable by the user. I'm dropping COM port build-time selection
and reworking it to be xl-configurable. That will be more flexible and
there will be less in-hypervisor changes.

>=20
> #define _XEN_X86_EMU_VUART          11
> #define XEN_X86_EMU_VUART           (1U << _XEN_X86_EMU_VUART)
>=20
> Thanks, Roger.



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Message-ID: 
Subject: Re: [PATCH 00/20] Add SMMUv3 Stage 1 Support for XEN guests
To: Milan Djokic 
Cc: "xen-devel@lists.xenproject.org" , 
	Bertrand Marquis , Rahul Singh , 
	Stefano Stabellini , Michal Orzel , 
	Volodymyr Babchuk , Jan Beulich , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Anthony PERARD , Nick Rosbrook , 
	George Dunlap , Juergen Gross , 
	Andrew Cooper 
Content-Type: multipart/alternative; boundary="0000000000006b36ce063bca3518"

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Hi Milan,

On Thu, 7 Aug 2025 at 17:55, Milan Djokic  wrote:

> This patch series represents a rebase of an older patch series implemente=
d
> and
> sumbitted by Rahul Singh as an RFC:
> https://patchwork.kernel.org/project/xen-devel/cover/cover.1669888522.git=
.rahul.singh@arm.com/
> .
> Original patch series content is aligned with the latest xen structure in
> terms of common/arch-specific code structuring.
> Some minor bugfixes are also applied:
> - Sanity checks / error handling
> - Non-pci devices support for emulated iommu


>
> Overall description of stage-1 support is available in the original
> patch series cover letter. Original commits structure with detailed
> explanation for each commit
> functionality is maintained.


I am a bit surprised not much has changed. Last time we asked a document to
explain the overall design of the vSMMU including some details on the
security posture. I can=E2=80=99t remember if this was ever posted.

If not, then you need to start with that. Otherwise, if is going to be
pretty difficult to review this series.

Cheers,


>
> Patch series testing is performed in qemu arm environment. Additionally,
> stage-1 translation for non-pci devices is verified on a Renesas platform=
.
>
> Jean-Philippe Brucker (1):
>   xen/arm: smmuv3: Maintain a SID->device structure
>
> Rahul Singh (19):
>   xen/arm: smmuv3: Add support for stage-1 and nested stage translation
>   xen/arm: smmuv3: Alloc io_domain for each device
>   xen/arm: vIOMMU: add generic vIOMMU framework
>   xen/arm: vsmmuv3: Add dummy support for virtual SMMUv3 for guests
>   xen/domctl: Add XEN_DOMCTL_CONFIG_VIOMMU_* and viommu config param
>   xen/arm: vIOMMU: Add cmdline boot option "viommu =3D "
>   xen/arm: vsmmuv3: Add support for registers emulation
>   xen/arm: vsmmuv3: Add support for cmdqueue handling
>   xen/arm: vsmmuv3: Add support for command CMD_CFGI_STE
>   xen/arm: vsmmuv3: Attach Stage-1 configuration to SMMUv3 hardware
>   xen/arm: vsmmuv3: Add support for event queue and global error
>   xen/arm: vsmmuv3: Add "iommus" property node for dom0 devices
>   xen/arm: vIOMMU: IOMMU device tree node for dom0
>   xen/arm: vsmmuv3: Emulated SMMUv3 device tree node for dom0less
>   arm/libxl: vsmmuv3: Emulated SMMUv3 device tree node in libxl
>   xen/arm: vsmmuv3: Alloc virq for virtual SMMUv3
>   xen/arm: vsmmuv3: Add support to send stage-1 event to guest
>   libxl/arm: vIOMMU: Modify the partial device tree for iommus
>   xen/arm: vIOMMU: Modify the partial device tree for dom0less
>
>  docs/man/xl.cfg.5.pod.in                |  13 +
>  docs/misc/xen-command-line.pandoc       |   7 +
>  tools/golang/xenlight/helpers.gen.go    |   2 +
>  tools/golang/xenlight/types.gen.go      |   1 +
>  tools/include/libxl.h                   |   5 +
>  tools/libs/light/libxl_arm.c            | 123 +++-
>  tools/libs/light/libxl_types.idl        |   6 +
>  tools/xl/xl_parse.c                     |  10 +
>  xen/arch/arm/dom0less-build.c           |  72 ++
>  xen/arch/arm/domain.c                   |  26 +
>  xen/arch/arm/domain_build.c             | 103 ++-
>  xen/arch/arm/include/asm/domain.h       |   4 +
>  xen/arch/arm/include/asm/viommu.h       | 102 +++
>  xen/common/device-tree/dom0less-build.c |  31 +-
>  xen/drivers/passthrough/Kconfig         |  14 +
>  xen/drivers/passthrough/arm/Makefile    |   2 +
>  xen/drivers/passthrough/arm/smmu-v3.c   | 369 +++++++++-
>  xen/drivers/passthrough/arm/smmu-v3.h   |  49 +-
>  xen/drivers/passthrough/arm/viommu.c    |  87 +++
>  xen/drivers/passthrough/arm/vsmmu-v3.c  | 895 ++++++++++++++++++++++++
>  xen/drivers/passthrough/arm/vsmmu-v3.h  |  32 +
>  xen/include/public/arch-arm.h           |  14 +-
>  xen/include/public/device_tree_defs.h   |   1 +
>  xen/include/xen/iommu.h                 |  14 +
>  24 files changed, 1935 insertions(+), 47 deletions(-)
>  create mode 100644 xen/arch/arm/include/asm/viommu.h
>  create mode 100644 xen/drivers/passthrough/arm/viommu.c
>  create mode 100644 xen/drivers/passthrough/arm/vsmmu-v3.c
>  create mode 100644 xen/drivers/passthrough/arm/vsmmu-v3.h
>
> --
> 2.43.0
>

--0000000000006b36ce063bca3518
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable


    Hi Milan,

    <=
/div>
    On Thu, 7 Aug 2=
025 at 17:55, Milan Djokic <milan_djokic@epam.com> wrote:
    This patch series represents a rebase of an older patch se=
ries implemented and
    
sumbitted by Rahul Singh as an RFC: https://patchwork.kernel.org/project/xen-deve=
l/cover/cover.1669888522.git.rahul.singh@arm.com/.
    
Original patch series content is aligned with the latest xen structure in t=
erms of common/arch-specific code structuring. 
    
Some minor bugfixes are also applied:
    
- Sanity checks / error handling
    
- Non-pci devices support for emulated iommu

    

    
Overall description of stage-1 support is available in the original
    
patch series cover letter. Original commits structure with detailed explana=
tion for each commit
    
functionality is maintained.

    =

    I am a bit surprised not much has changed. Last time=
 we asked a document to explain the overall design of the vSMMU=C2=A0including some details on th=
e security posture. I can=E2=80=99t remember if this was ever posted.

    If not, then you need to start with that. Otherwise, if is =
going to be pretty difficult to review this series.

    Cheers,

    

    
Patch series testing is performed in qemu arm environment. Additionally,
stage-1 translation for non-pci devices is verified on a Renesas platform.<=
br>

    
Jean-Philippe Brucker (1):
    
=C2=A0 xen/arm: smmuv3: Maintain a SID->device structure
    

    
Rahul Singh (19):
    
=C2=A0 xen/arm: smmuv3: Add support for stage-1 and nested stage translatio=
n
    
=C2=A0 xen/arm: smmuv3: Alloc io_domain for each device
    
=C2=A0 xen/arm: vIOMMU: add generic vIOMMU framework
    
=C2=A0 xen/arm: vsmmuv3: Add dummy support for virtual SMMUv3 for guests
=C2=A0 xen/domctl: Add XEN_DOMCTL_CONFIG_VIOMMU_* and viommu config param
=C2=A0 xen/arm: vIOMMU: Add cmdline boot option "viommu =3D <boolea=
n>"
    
=C2=A0 xen/arm: vsmmuv3: Add support for registers emulation
    
=C2=A0 xen/arm: vsmmuv3: Add support for cmdqueue handling
    
=C2=A0 xen/arm: vsmmuv3: Add support for command CMD_CFGI_STE
    
=C2=A0 xen/arm: vsmmuv3: Attach Stage-1 configuration to SMMUv3 hardware
=C2=A0 xen/arm: vsmmuv3: Add support for event queue and global error
    
=C2=A0 xen/arm: vsmmuv3: Add "iommus" property node for dom0 devi=
ces
    
=C2=A0 xen/arm: vIOMMU: IOMMU device tree node for dom0
    
=C2=A0 xen/arm: vsmmuv3: Emulated SMMUv3 device tree node for dom0less
    
=C2=A0 arm/libxl: vsmmuv3: Emulated SMMUv3 device tree node in libxl
    
=C2=A0 xen/arm: vsmmuv3: Alloc virq for virtual SMMUv3
    
=C2=A0 xen/arm: vsmmuv3: Add support to send stage-1 event to guest
    
=C2=A0 libxl/arm: vIOMMU: Modify the partial device tree for iommus
    
=C2=A0 xen/arm: vIOMMU: Modify the partial device tree for dom0less
    

    
=C2=A0docs/man/xl.cfg.5.pod.in=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 |=C2=A0 13 +
    
=C2=A0docs/misc/xen-command-line.pandoc=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =
=C2=A07 +
    
=C2=A0tools/golang/xenlight/helpers.gen.go=C2=A0 =C2=A0 |=C2=A0 =C2=A02 +
=C2=A0tools/golang/xenlight/types.gen.go=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0=
1 +
    
=C2=A0tools/include/libxl.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A05 +
    
=C2=A0tools/libs/light/libxl_arm.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 | 123 +++-
    
=C2=A0tools/libs/light/libxl_types.idl=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =
=C2=A06 +
    
=C2=A0tools/xl/xl_parse.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 10 +
    
=C2=A0xen/arch/arm/dom0less-build.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0|=C2=A0 72 ++
    
=C2=A0xen/arch/arm/domain.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 =C2=A0 =C2=A0 =C2=A0|=C2=A0 26 +
    
=C2=A0xen/arch/arm/domain_build.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0| 103 ++-
    
=C2=A0xen/arch/arm/include/asm/domain.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =
=C2=A04 +
    
=C2=A0xen/arch/arm/include/asm/viommu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0| 102 +++=

    
=C2=A0xen/common/device-tree/dom0less-build.c |=C2=A0 31 +-
    
=C2=A0xen/drivers/passthrough/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=
=A0 14 +
    
=C2=A0xen/drivers/passthrough/arm/Makefile=C2=A0 =C2=A0 |=C2=A0 =C2=A02 +
=C2=A0xen/drivers/passthrough/arm/smmu-v3.c=C2=A0 =C2=A0| 369 +++++++++-
=C2=A0xen/drivers/passthrough/arm/smmu-v3.h=C2=A0 =C2=A0|=C2=A0 49 +-
    
=C2=A0xen/drivers/passthrough/arm/viommu.c=C2=A0 =C2=A0 |=C2=A0 87 +++
    
=C2=A0xen/drivers/passthrough/arm/vsmmu-v3.c=C2=A0 | 895 ++++++++++++++++++=
++++++
    
=C2=A0xen/drivers/passthrough/arm/vsmmu-v3.h=C2=A0 |=C2=A0 32 +
    
=C2=A0xen/include/public/arch-arm.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0|=C2=A0 14 +-
    
=C2=A0xen/include/public/device_tree_defs.h=C2=A0 =C2=A0|=C2=A0 =C2=A01 +
=C2=A0xen/include/xen/iommu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0|=C2=A0 14 +
    
=C2=A024 files changed, 1935 insertions(+), 47 deletions(-)
    
=C2=A0create mode 100644 xen/arch/arm/include/asm/viommu.h
    
=C2=A0create mode 100644 xen/drivers/passthrough/arm/viommu.c
    
=C2=A0create mode 100644 xen/drivers/passthrough/arm/vsmmu-v3.c
    
=C2=A0create mode 100644 xen/drivers/passthrough/arm/vsmmu-v3.h
    

    
-- 
    
2.43.0
    

    

    

--0000000000006b36ce063bca3518--


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Milan Djokic , Bertrand Marquis
	, Rahul Singh , Stefano
 Stabellini , Julien Grall , Michal
 Orzel , Volodymyr Babchuk ,
	Jan Beulich , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Anthony PERARD , Nick
 Rosbrook , George Dunlap , Juergen
 Gross , Andrew Cooper 
Subject: [PATCH 00/20] Add SMMUv3 Stage 1 Support for XEN guests
Thread-Topic: [PATCH 00/20] Add SMMUv3 Stage 1 Support for XEN guests
Thread-Index: AQHcB7wdmg15F24Gc0ClRsxpCVedRA==
Date: Thu, 7 Aug 2025 16:55:44 +0000
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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Milan Djokic 
Subject: [PATCH 13/20] xen/arm: vsmmuv3: Add "iommus" property node for dom0
 devices
Thread-Topic: [PATCH 13/20] xen/arm: vsmmuv3: Add "iommus" property node for
 dom0 devices
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From: Rahul Singh 

"iommus" property will be added for dom0 devices to virtual
IOMMU node to enable the dom0 linux kernel to configure the IOMMU

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/arch/arm/domain_build.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 50e4f5fee4..9d2b0ea928 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -537,9 +537,12 @@ static int __init write_properties(struct domain *d, s=
truct kernel_info *kinfo,
             continue;
         }
=20
-        if ( iommu_node )
+        /*
+         * Expose IOMMU specific properties to hwdom when vIOMMU is
+         * enabled.
+         */
+        if ( iommu_node && !is_viommu_enabled() )
         {
-            /* Don't expose IOMMU specific properties to hwdom */
             if ( dt_property_name_is_equal(prop, "iommus") )
                 continue;
=20
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini , Bertrand
 Marquis , Volodymyr Babchuk
	, Milan Djokic 
Subject: [PATCH 07/20] xen/arm: vIOMMU: Add cmdline boot option "viommu =
 "
Thread-Topic: [PATCH 07/20] xen/arm: vIOMMU: Add cmdline boot option "viommu =
 "
Thread-Index: AQHcB7yfTy1RKYdeLkuvW3i0Y8QAyQ==
Date: Thu, 7 Aug 2025 16:59:22 +0000
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From: Rahul Singh 

Add cmdline boot option "viommu =3D " to enable or disable the
virtual iommu support for guests on ARM.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 docs/misc/xen-command-line.pandoc      |  7 +++++++
 xen/arch/arm/include/asm/viommu.h      | 11 +++++++++++
 xen/drivers/passthrough/arm/viommu.c   |  9 +++++++++
 xen/drivers/passthrough/arm/vsmmu-v3.c |  3 +++
 4 files changed, 30 insertions(+)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line=
.pandoc
index 6865a61220..d6a2a6fbdd 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2058,6 +2058,13 @@ This option can be specified more than once (up to 8=
 times at present).
=20
 Flag to enable or disable support for PCI passthrough
=20
+### viommu (arm)
+> `=3D `
+
+> Default: `false`
+
+Flag to enable or disable support for Virtual IOMMU for guests.
+
 ### pcid (x86)
 > `=3D  | xpti=3D`
=20
diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/v=
iommu.h
index 4785877e2a..4de4cceeda 100644
--- a/xen/arch/arm/include/asm/viommu.h
+++ b/xen/arch/arm/include/asm/viommu.h
@@ -10,6 +10,7 @@
 #include 
=20
 extern struct list_head host_iommu_list;
+extern bool viommu_enabled;
=20
 /* data structure for each hardware IOMMU */
 struct host_iommu {
@@ -50,6 +51,11 @@ uint16_t viommu_get_type(void);
 void add_to_host_iommu_list(paddr_t addr, paddr_t size,
                             const struct dt_device_node *node);
=20
+static always_inline bool is_viommu_enabled(void)
+{
+    return viommu_enabled;
+}
+
 #else
=20
 static inline uint8_t viommu_get_type(void)
@@ -76,6 +82,11 @@ static inline void add_to_host_iommu_list(paddr_t addr, =
paddr_t size,
     return;
 }
=20
+static always_inline bool is_viommu_enabled(void)
+{
+    return false;
+}
+
 #endif /* CONFIG_VIRTUAL_IOMMU */
=20
 #endif /* __ARCH_ARM_VIOMMU_H__ */
diff --git a/xen/drivers/passthrough/arm/viommu.c b/xen/drivers/passthrough=
/arm/viommu.c
index 53ae46349a..a1d6a04ba9 100644
--- a/xen/drivers/passthrough/arm/viommu.c
+++ b/xen/drivers/passthrough/arm/viommu.c
@@ -3,6 +3,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
=20
 #include 
@@ -38,8 +39,16 @@ void add_to_host_iommu_list(paddr_t addr, paddr_t size,
     list_add_tail(&iommu_data->entry, &host_iommu_list);
 }
=20
+/* By default viommu is disabled. */
+bool __read_mostly viommu_enabled;
+boolean_param("viommu", viommu_enabled);
+
 int domain_viommu_init(struct domain *d, uint16_t viommu_type)
 {
+    /* Enable viommu when it has been enabled explicitly (viommu=3Don). */
+    if ( !viommu_enabled )
+        return 0;
+
     if ( viommu_type =3D=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE )
         return 0;
=20
diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou=
gh/arm/vsmmu-v3.c
index 6b4009e5ef..e36f200ba5 100644
--- a/xen/drivers/passthrough/arm/vsmmu-v3.c
+++ b/xen/drivers/passthrough/arm/vsmmu-v3.c
@@ -105,6 +105,9 @@ void __init vsmmuv3_set_type(void)
 {
     const struct viommu_desc *desc =3D &vsmmuv3_desc;
=20
+    if ( !is_viommu_enabled() )
+        return;
+
     if ( cur_viommu && (cur_viommu !=3D desc) )
     {
         printk("WARNING: Cannot set vIOMMU, already set to a different val=
ue\n");
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Milan Djokic 
Subject: [PATCH 08/20] xen/arm: vsmmuv3: Add support for registers emulation
Thread-Topic: [PATCH 08/20] xen/arm: vsmmuv3: Add support for registers
 emulation
Thread-Index: AQHcB7yf5fp8wcYRf0iby3/TDRcqpw==
Date: Thu, 7 Aug 2025 16:59:23 +0000
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 <77d962e8a344f3fd3f7afcd71ad35c12a604b372.1754580688.git.milan_djokic@epam.com>
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From: Rahul Singh 

Add initial support for various emulated registers for virtual SMMUv3
for guests and also add support for virtual cmdq and eventq.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/drivers/passthrough/arm/smmu-v3.h  |   6 +
 xen/drivers/passthrough/arm/vsmmu-v3.c | 286 +++++++++++++++++++++++++
 2 files changed, 292 insertions(+)

diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug=
h/arm/smmu-v3.h
index 3411edc47f..d54f0a79f2 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.h
+++ b/xen/drivers/passthrough/arm/smmu-v3.h
@@ -60,6 +60,12 @@
 #define IDR5_VAX			GENMASK(11, 10)
 #define IDR5_VAX_52_BIT			1
=20
+#define ARM_SMMU_IIDR			0x18
+#define IIDR_PRODUCTID			GENMASK(31, 20)
+#define IIDR_VARIANT			GENMASK(19, 16)
+#define IIDR_REVISION			GENMASK(15, 12)
+#define IIDR_IMPLEMENTER		GENMASK(11, 0)
+
 #define ARM_SMMU_CR0			0x20
 #define CR0_ATSCHK			(1 << 4)
 #define CR0_CMDQEN			(1 << 3)
diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou=
gh/arm/vsmmu-v3.c
index e36f200ba5..3ae1e62a50 100644
--- a/xen/drivers/passthrough/arm/vsmmu-v3.c
+++ b/xen/drivers/passthrough/arm/vsmmu-v3.c
@@ -3,25 +3,307 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
+
+#include "smmu-v3.h"
+
+/* Register Definition */
+#define ARM_SMMU_IDR2       0x8
+#define ARM_SMMU_IDR3       0xc
+#define ARM_SMMU_IDR4       0x10
+#define IDR0_TERM_MODEL     (1 << 26)
+#define IDR3_RIL            (1 << 10)
+#define CR0_RESERVED        0xFFFFFC20
+#define SMMU_IDR1_SIDSIZE   16
+#define SMMU_CMDQS          19
+#define SMMU_EVTQS          19
+#define DWORDS_BYTES        8
+#define ARM_SMMU_IIDR_VAL   0x12
=20
 /* Struct to hold the vIOMMU ops and vIOMMU type */
 extern const struct viommu_desc __read_mostly *cur_viommu;
=20
+/* virtual smmu queue */
+struct arm_vsmmu_queue {
+    uint64_t    q_base; /* base register */
+    uint32_t    prod;
+    uint32_t    cons;
+    uint8_t     ent_size;
+    uint8_t     max_n_shift;
+};
+
 struct virt_smmu {
     struct      domain *d;
     struct      list_head viommu_list;
+    uint8_t     sid_split;
+    uint32_t    features;
+    uint32_t    cr[3];
+    uint32_t    cr0ack;
+    uint32_t    gerror;
+    uint32_t    gerrorn;
+    uint32_t    strtab_base_cfg;
+    uint64_t    strtab_base;
+    uint32_t    irq_ctrl;
+    uint64_t    gerror_irq_cfg0;
+    uint64_t    evtq_irq_cfg0;
+    struct      arm_vsmmu_queue evtq, cmdq;
 };
=20
 static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info,
                               register_t r, void *priv)
 {
+    struct virt_smmu *smmu =3D priv;
+    uint64_t reg;
+    uint32_t reg32;
+
+    switch ( info->gpa & 0xffff )
+    {
+    case VREG32(ARM_SMMU_CR0):
+        reg32 =3D smmu->cr[0];
+        vreg_reg32_update(®32, r, info);
+        smmu->cr[0] =3D reg32;
+        smmu->cr0ack =3D reg32 & ~CR0_RESERVED;
+        break;
+
+    case VREG32(ARM_SMMU_CR1):
+        reg32 =3D smmu->cr[1];
+        vreg_reg32_update(®32, r, info);
+        smmu->cr[1] =3D reg32;
+        break;
+
+    case VREG32(ARM_SMMU_CR2):
+        reg32 =3D smmu->cr[2];
+        vreg_reg32_update(®32, r, info);
+        smmu->cr[2] =3D reg32;
+        break;
+
+    case VREG64(ARM_SMMU_STRTAB_BASE):
+        reg =3D smmu->strtab_base;
+        vreg_reg64_update(®, r, info);
+        smmu->strtab_base =3D reg;
+        break;
+
+    case VREG32(ARM_SMMU_STRTAB_BASE_CFG):
+        reg32 =3D smmu->strtab_base_cfg;
+        vreg_reg32_update(®32, r, info);
+        smmu->strtab_base_cfg =3D reg32;
+
+        smmu->sid_split =3D FIELD_GET(STRTAB_BASE_CFG_SPLIT, reg32);
+        smmu->features |=3D STRTAB_BASE_CFG_FMT_2LVL;
+        break;
+
+    case VREG32(ARM_SMMU_CMDQ_BASE):
+        reg =3D smmu->cmdq.q_base;
+        vreg_reg64_update(®, r, info);
+        smmu->cmdq.q_base =3D reg;
+        smmu->cmdq.max_n_shift =3D FIELD_GET(Q_BASE_LOG2SIZE, smmu->cmdq.q=
_base);
+        if ( smmu->cmdq.max_n_shift > SMMU_CMDQS )
+            smmu->cmdq.max_n_shift =3D SMMU_CMDQS;
+        break;
+
+    case VREG32(ARM_SMMU_CMDQ_PROD):
+        reg32 =3D smmu->cmdq.prod;
+        vreg_reg32_update(®32, r, info);
+        smmu->cmdq.prod =3D reg32;
+        break;
+
+    case VREG32(ARM_SMMU_CMDQ_CONS):
+        reg32 =3D smmu->cmdq.cons;
+        vreg_reg32_update(®32, r, info);
+        smmu->cmdq.cons =3D reg32;
+        break;
+
+    case VREG32(ARM_SMMU_EVTQ_BASE):
+        reg =3D smmu->evtq.q_base;
+        vreg_reg64_update(®, r, info);
+        smmu->evtq.q_base =3D reg;
+        smmu->evtq.max_n_shift =3D FIELD_GET(Q_BASE_LOG2SIZE, smmu->evtq.q=
_base);
+        if ( smmu->cmdq.max_n_shift > SMMU_EVTQS )
+            smmu->cmdq.max_n_shift =3D SMMU_EVTQS;
+        break;
+
+    case VREG32(ARM_SMMU_EVTQ_PROD):
+        reg32 =3D smmu->evtq.prod;
+        vreg_reg32_update(®32, r, info);
+        smmu->evtq.prod =3D reg32;
+        break;
+
+    case VREG32(ARM_SMMU_EVTQ_CONS):
+        reg32 =3D smmu->evtq.cons;
+        vreg_reg32_update(®32, r, info);
+        smmu->evtq.cons =3D reg32;
+        break;
+
+    case VREG32(ARM_SMMU_IRQ_CTRL):
+        reg32 =3D smmu->irq_ctrl;
+        vreg_reg32_update(®32, r, info);
+        smmu->irq_ctrl =3D reg32;
+        break;
+
+    case VREG64(ARM_SMMU_GERROR_IRQ_CFG0):
+        reg =3D smmu->gerror_irq_cfg0;
+        vreg_reg64_update(®, r, info);
+        smmu->gerror_irq_cfg0 =3D reg;
+        break;
+
+    case VREG64(ARM_SMMU_EVTQ_IRQ_CFG0):
+        reg =3D smmu->evtq_irq_cfg0;
+        vreg_reg64_update(®, r, info);
+        smmu->evtq_irq_cfg0 =3D reg;
+        break;
+
+    case VREG32(ARM_SMMU_GERRORN):
+        reg =3D smmu->gerrorn;
+        vreg_reg64_update(®, r, info);
+        smmu->gerrorn =3D reg;
+        break;
+
+    default:
+        printk(XENLOG_G_ERR
+               "%pv: vSMMUv3: unhandled write r%d offset %"PRIpaddr"\n",
+               v, info->dabt.reg, (unsigned long)info->gpa & 0xffff);
+        return IO_ABORT;
+    }
+
     return IO_HANDLED;
 }
=20
 static int vsmmuv3_mmio_read(struct vcpu *v, mmio_info_t *info,
                              register_t *r, void *priv)
 {
+    struct virt_smmu *smmu =3D priv;
+    uint64_t reg;
+
+    switch ( info->gpa & 0xffff )
+    {
+    case VREG32(ARM_SMMU_IDR0):
+        reg  =3D FIELD_PREP(IDR0_S1P, 1) | FIELD_PREP(IDR0_TTF, 2) |
+            FIELD_PREP(IDR0_COHACC, 0) | FIELD_PREP(IDR0_ASID16, 1) |
+            FIELD_PREP(IDR0_TTENDIAN, 0) | FIELD_PREP(IDR0_STALL_MODEL, 1)=
 |
+            FIELD_PREP(IDR0_ST_LVL, 1) | FIELD_PREP(IDR0_TERM_MODEL, 1);
+        *r =3D vreg_reg32_extract(reg, info);
+        break;
+
+    case VREG32(ARM_SMMU_IDR1):
+        reg  =3D FIELD_PREP(IDR1_SIDSIZE, SMMU_IDR1_SIDSIZE) |
+            FIELD_PREP(IDR1_CMDQS, SMMU_CMDQS) |
+            FIELD_PREP(IDR1_EVTQS, SMMU_EVTQS);
+        *r =3D vreg_reg32_extract(reg, info);
+        break;
+
+    case VREG32(ARM_SMMU_IDR2):
+        goto read_reserved;
+
+    case VREG32(ARM_SMMU_IDR3):
+        reg  =3D FIELD_PREP(IDR3_RIL, 0);
+        *r =3D vreg_reg32_extract(reg, info);
+        break;
+
+    case VREG32(ARM_SMMU_IDR4):
+        goto read_impl_defined;
+
+    case VREG32(ARM_SMMU_IDR5):
+        reg  =3D FIELD_PREP(IDR5_GRAN4K, 1) | FIELD_PREP(IDR5_GRAN16K, 1) =
|
+            FIELD_PREP(IDR5_GRAN64K, 1) | FIELD_PREP(IDR5_OAS, IDR5_OAS_48=
_BIT);
+        *r =3D vreg_reg32_extract(reg, info);
+        break;
+
+    case VREG32(ARM_SMMU_IIDR):
+        *r =3D vreg_reg32_extract(ARM_SMMU_IIDR_VAL, info);
+        break;
+
+    case VREG32(ARM_SMMU_CR0):
+        *r =3D vreg_reg32_extract(smmu->cr[0], info);
+        break;
+
+    case VREG32(ARM_SMMU_CR0ACK):
+        *r =3D vreg_reg32_extract(smmu->cr0ack, info);
+        break;
+
+    case VREG32(ARM_SMMU_CR1):
+        *r =3D vreg_reg32_extract(smmu->cr[1], info);
+        break;
+
+    case VREG32(ARM_SMMU_CR2):
+        *r =3D vreg_reg32_extract(smmu->cr[2], info);
+        break;
+
+    case VREG32(ARM_SMMU_STRTAB_BASE):
+        *r =3D vreg_reg64_extract(smmu->strtab_base, info);
+        break;
+
+    case VREG32(ARM_SMMU_STRTAB_BASE_CFG):
+        *r =3D vreg_reg32_extract(smmu->strtab_base_cfg, info);
+        break;
+
+    case VREG32(ARM_SMMU_CMDQ_BASE):
+        *r =3D vreg_reg64_extract(smmu->cmdq.q_base, info);
+        break;
+
+    case VREG32(ARM_SMMU_CMDQ_PROD):
+        *r =3D vreg_reg32_extract(smmu->cmdq.prod, info);
+        break;
+
+    case VREG32(ARM_SMMU_CMDQ_CONS):
+        *r =3D vreg_reg32_extract(smmu->cmdq.cons, info);
+        break;
+
+    case VREG32(ARM_SMMU_EVTQ_BASE):
+        *r =3D vreg_reg64_extract(smmu->evtq.q_base, info);
+        break;
+
+    case VREG32(ARM_SMMU_EVTQ_PROD):
+        *r =3D vreg_reg32_extract(smmu->evtq.prod, info);
+        break;
+
+    case VREG32(ARM_SMMU_EVTQ_CONS):
+        *r =3D vreg_reg32_extract(smmu->evtq.cons, info);
+        break;
+
+    case VREG32(ARM_SMMU_IRQ_CTRL):
+    case VREG32(ARM_SMMU_IRQ_CTRLACK):
+        *r =3D vreg_reg32_extract(smmu->irq_ctrl, info);
+        break;
+
+    case VREG64(ARM_SMMU_GERROR_IRQ_CFG0):
+        *r =3D vreg_reg64_extract(smmu->gerror_irq_cfg0, info);
+        break;
+
+    case VREG64(ARM_SMMU_EVTQ_IRQ_CFG0):
+        *r =3D vreg_reg64_extract(smmu->evtq_irq_cfg0, info);
+        break;
+
+    case VREG32(ARM_SMMU_GERROR):
+        *r =3D vreg_reg64_extract(smmu->gerror, info);
+        break;
+
+    case VREG32(ARM_SMMU_GERRORN):
+        *r =3D vreg_reg64_extract(smmu->gerrorn, info);
+        break;
+
+    default:
+        printk(XENLOG_G_ERR
+               "%pv: vSMMUv3: unhandled read r%d offset %"PRIpaddr"\n",
+               v, info->dabt.reg, (unsigned long)info->gpa & 0xffff);
+        return IO_ABORT;
+    }
+
+    return IO_HANDLED;
+
+ read_impl_defined:
+    printk(XENLOG_G_DEBUG
+           "%pv: vSMMUv3: RAZ on implementation defined register offset %"=
PRIpaddr"\n",
+           v, info->gpa & 0xffff);
+    *r =3D 0;
+    return IO_HANDLED;
+
+ read_reserved:
+    printk(XENLOG_G_DEBUG
+           "%pv: vSMMUv3: RAZ on reserved register offset %"PRIpaddr"\n",
+           v, info->gpa & 0xffff);
+    *r =3D 0;
     return IO_HANDLED;
 }
=20
@@ -39,6 +321,10 @@ static int vsmmuv3_init_single(struct domain *d, paddr_=
t addr, paddr_t size)
         return -ENOMEM;
=20
     smmu->d =3D d;
+    smmu->cmdq.q_base =3D FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_CMDQS);
+    smmu->cmdq.ent_size =3D CMDQ_ENT_DWORDS * DWORDS_BYTES;
+    smmu->evtq.q_base =3D FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_EVTQS);
+    smmu->evtq.ent_size =3D EVTQ_ENT_DWORDS * DWORDS_BYTES;
=20
     register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu);
=20
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Jan Beulich ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Milan Djokic
	
Subject: [PATCH 05/20] xen/arm: vsmmuv3: Add dummy support for virtual SMMUv3
 for guests
Thread-Topic: [PATCH 05/20] xen/arm: vsmmuv3: Add dummy support for virtual
 SMMUv3 for guests
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Date: Thu, 7 Aug 2025 16:59:20 +0000
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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Bertrand Marquis
	, Stefano Stabellini ,
	Julien Grall , Michal Orzel , Volodymyr
 Babchuk , Milan Djokic 
Subject: [PATCH 02/20] xen/arm: smmuv3: Add support for stage-1 and nested
 stage translation
Thread-Topic: [PATCH 02/20] xen/arm: smmuv3: Add support for stage-1 and
 nested stage translation
Thread-Index: AQHcB7ya52I2vrwap0uCF6HUjZseiA==
Date: Thu, 7 Aug 2025 16:59:13 +0000
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From: Rahul Singh 

Xen SMMUv3 driver only supports stage-2 translation. Add support for
Stage-1 translation that is required to support nested stage
translation.

In true nested mode, both s1_cfg and s2_cfg will coexist.
Let's remove the union. When nested stage translation is setup, both
s1_cfg and s2_cfg are valid.

We introduce a new smmu_domain abort field that will be set
upon guest stage-1 configuration passing. If no guest stage-1
config has been attached, it is ignored when writing the STE.

arm_smmu_write_strtab_ent() is modified to write both stage
fields in the STE and deal with the abort field.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/drivers/passthrough/arm/smmu-v3.c | 93 +++++++++++++++++++++++----
 xen/drivers/passthrough/arm/smmu-v3.h |  9 +++
 2 files changed, 91 insertions(+), 11 deletions(-)

diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug=
h/arm/smmu-v3.c
index 307057ad8a..5c96e8ec7c 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.c
+++ b/xen/drivers/passthrough/arm/smmu-v3.c
@@ -667,8 +667,10 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_=
master *master, u32 sid,
 	 * 3. Update Config, sync
 	 */
 	u64 val =3D le64_to_cpu(dst[0]);
-	bool ste_live =3D false;
+	bool s1_live =3D false, s2_live =3D false, ste_live =3D false;
+	bool abort, translate =3D false;
 	struct arm_smmu_device *smmu =3D NULL;
+	struct arm_smmu_s1_cfg *s1_cfg =3D NULL;
 	struct arm_smmu_s2_cfg *s2_cfg =3D NULL;
 	struct arm_smmu_domain *smmu_domain =3D NULL;
 	struct arm_smmu_cmdq_ent prefetch_cmd =3D {
@@ -683,30 +685,54 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu=
_master *master, u32 sid,
 		smmu =3D master->smmu;
 	}
=20
-	if (smmu_domain)
-		s2_cfg =3D &smmu_domain->s2_cfg;
+	if (smmu_domain) {
+		switch (smmu_domain->stage) {
+		case ARM_SMMU_DOMAIN_NESTED:
+			s1_cfg =3D &smmu_domain->s1_cfg;
+			fallthrough;
+		case ARM_SMMU_DOMAIN_S2:
+			s2_cfg =3D &smmu_domain->s2_cfg;
+			break;
+		default:
+			break;
+		}
+		translate =3D !!s1_cfg || !!s2_cfg;
+	}
=20
 	if (val & STRTAB_STE_0_V) {
 		switch (FIELD_GET(STRTAB_STE_0_CFG, val)) {
 		case STRTAB_STE_0_CFG_BYPASS:
 			break;
+		case STRTAB_STE_0_CFG_S1_TRANS:
+			s1_live =3D true;
+			break;
 		case STRTAB_STE_0_CFG_S2_TRANS:
-			ste_live =3D true;
+			s2_live =3D true;
+			break;
+		case STRTAB_STE_0_CFG_NESTED:
+			s1_live =3D true;
+			s2_live =3D true;
 			break;
 		case STRTAB_STE_0_CFG_ABORT:
-			BUG_ON(!disable_bypass);
 			break;
 		default:
 			BUG(); /* STE corruption */
 		}
 	}
=20
+	ste_live =3D s1_live || s2_live;
+
 	/* Nuke the existing STE_0 value, as we're going to rewrite it */
 	val =3D STRTAB_STE_0_V;
=20
 	/* Bypass/fault */
-	if (!smmu_domain || !(s2_cfg)) {
-		if (!smmu_domain && disable_bypass)
+	if (!smmu_domain)
+		abort =3D disable_bypass;
+	else
+		abort =3D smmu_domain->abort;
+
+	if (abort || !translate) {
+		if (abort)
 			val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
 		else
 			val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
@@ -724,7 +750,33 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_=
master *master, u32 sid,
 		return;
 	}
=20
+	if (ste_live) {
+		/* First invalidate the live STE */
+		dst[0] =3D cpu_to_le64(STRTAB_STE_0_CFG_ABORT);
+		arm_smmu_sync_ste_for_sid(smmu, sid);
+	}
+
+	if (s1_cfg) {
+		BUG_ON(s1_live);
+		dst[1] =3D cpu_to_le64(
+			 FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) |
+			 FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) |
+			 FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) |
+			 FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) |
+			 FIELD_PREP(STRTAB_STE_1_STRW, STRTAB_STE_1_STRW_NSEL1));
+
+		if (smmu->features & ARM_SMMU_FEAT_STALLS &&
+		   !(smmu->features & ARM_SMMU_FEAT_STALL_FORCE))
+			dst[1] |=3D cpu_to_le64(STRTAB_STE_1_S1STALLD);
+
+		val |=3D (s1_cfg->s1ctxptr & STRTAB_STE_0_S1CTXPTR_MASK) |
+			FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) |
+			FIELD_PREP(STRTAB_STE_0_S1CDMAX, s1_cfg->s1cdmax) |
+			FIELD_PREP(STRTAB_STE_0_S1FMT, s1_cfg->s1fmt);
+	}
+
 	if (s2_cfg) {
+		u64 vttbr =3D s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK;
 		u64 strtab =3D
 			 FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) |
 			 FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) |
@@ -734,12 +786,19 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu=
_master *master, u32 sid,
 			 STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 |
 			 STRTAB_STE_2_S2R;
=20
-		BUG_ON(ste_live);
+		if (s2_live) {
+			u64 s2ttb =3D le64_to_cpu(dst[3]) & STRTAB_STE_3_S2TTB_MASK;
+			BUG_ON(s2ttb !=3D vttbr);
+		}
+
 		dst[2] =3D cpu_to_le64(strtab);
=20
-		dst[3] =3D cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK);
+		dst[3] =3D cpu_to_le64(vttbr);
=20
 		val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS);
+	} else {
+		dst[2] =3D 0;
+		dst[3] =3D 0;
 	}
=20
 	if (master->ats_enabled)
@@ -1238,6 +1297,15 @@ static int arm_smmu_domain_finalise(struct iommu_dom=
ain *domain,
 {
 	int ret;
 	struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain);
+	struct arm_smmu_device *smmu =3D smmu_domain->smmu;
+
+	if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_NESTED &&
+		(!(smmu->features & ARM_SMMU_FEAT_TRANS_S1) ||
+		 !(smmu->features & ARM_SMMU_FEAT_TRANS_S2))) {
+			dev_info(smmu_domain->smmu->dev,
+					"does not implement two stages\n");
+			return -EINVAL;
+	}
=20
 	/* Restrict the stage to what we can actually support */
 	smmu_domain->stage =3D ARM_SMMU_DOMAIN_S2;
@@ -2334,11 +2402,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu=
_device *smmu)
 		break;
 	}
=20
+	if (reg & IDR0_S1P)
+		smmu->features |=3D ARM_SMMU_FEAT_TRANS_S1;
+
 	if (reg & IDR0_S2P)
 		smmu->features |=3D ARM_SMMU_FEAT_TRANS_S2;
=20
-	if (!(reg & IDR0_S2P)) {
-		dev_err(smmu->dev, "no stage-2 translation support!\n");
+	if (!(reg & (IDR0_S1P | IDR0_S2P))) {
+		dev_err(smmu->dev, "no translation support!\n");
 		return -ENXIO;
 	}
=20
diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug=
h/arm/smmu-v3.h
index fe651ca5a7..3411edc47f 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.h
+++ b/xen/drivers/passthrough/arm/smmu-v3.h
@@ -197,6 +197,7 @@
 #define STRTAB_STE_0_CFG_BYPASS		4
 #define STRTAB_STE_0_CFG_S1_TRANS	5
 #define STRTAB_STE_0_CFG_S2_TRANS	6
+#define STRTAB_STE_0_CFG_NESTED		7
=20
 #define STRTAB_STE_0_S1FMT		GENMASK_ULL(5, 4)
 #define STRTAB_STE_0_S1FMT_LINEAR	0
@@ -546,6 +547,12 @@ struct arm_smmu_strtab_l1_desc {
 	dma_addr_t			l2ptr_dma;
 };
=20
+struct arm_smmu_s1_cfg {
+	u64				s1ctxptr;
+	u8				s1fmt;
+	u8				s1cdmax;
+};
+
 struct arm_smmu_s2_cfg {
 	u16				vmid;
 	u64				vttbr;
@@ -666,7 +673,9 @@ struct arm_smmu_domain {
 	atomic_t			nr_ats_masters;
=20
 	enum arm_smmu_domain_stage	stage;
+	struct arm_smmu_s1_cfg	s1_cfg;
 	struct arm_smmu_s2_cfg	s2_cfg;
+	bool			abort;
=20
 	/* Xen domain associated with this SMMU domain */
 	struct domain		*d;
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Bertrand Marquis
	, Stefano Stabellini ,
	Julien Grall , Michal Orzel , Volodymyr
 Babchuk , Jan Beulich ,
	=?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Milan Djokic
	
Subject: [PATCH 11/20] xen/arm: vsmmuv3: Attach Stage-1 configuration to
 SMMUv3 hardware
Thread-Topic: [PATCH 11/20] xen/arm: vsmmuv3: Attach Stage-1 configuration to
 SMMUv3 hardware
Thread-Index: AQHcB7yha1klxs18OESsoLM4R9ywNQ==
Date: Thu, 7 Aug 2025 16:59:26 +0000
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From: Rahul Singh 

Attach the Stage-1 configuration to device STE to support nested
translation for the guests.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/drivers/passthrough/arm/smmu-v3.c  | 79 ++++++++++++++++++++++++++
 xen/drivers/passthrough/arm/smmu-v3.h  |  1 +
 xen/drivers/passthrough/arm/vsmmu-v3.c | 18 ++++++
 xen/include/xen/iommu.h                | 14 +++++
 4 files changed, 112 insertions(+)

diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug=
h/arm/smmu-v3.c
index 193c892fcd..91bf72d420 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.c
+++ b/xen/drivers/passthrough/arm/smmu-v3.c
@@ -2791,6 +2791,37 @@ static struct arm_smmu_device *arm_smmu_get_by_dev(c=
onst struct device *dev)
 	return NULL;
 }
=20
+static struct iommu_domain *arm_smmu_get_domain_by_sid(struct domain *d,
+				u32 sid)
+{
+	int i;
+	unsigned long flags;
+	struct iommu_domain *io_domain;
+	struct arm_smmu_domain *smmu_domain;
+	struct arm_smmu_master *master;
+	struct arm_smmu_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv;
+
+	/*
+	 * Loop through the &xen_domain->contexts to locate a context
+	 * assigned to this SMMU
+	 */
+	list_for_each_entry(io_domain, &xen_domain->contexts, list) {
+		smmu_domain =3D to_smmu_domain(io_domain);
+
+		spin_lock_irqsave(&smmu_domain->devices_lock, flags);
+		list_for_each_entry(master, &smmu_domain->devices, domain_head) {
+			for (i =3D 0; i < master->num_streams; i++) {
+				if (sid !=3D master->streams[i].id)
+					continue;
+				spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
+				return io_domain;
+			}
+		}
+		spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
+	}
+	return NULL;
+}
+
 static struct iommu_domain *arm_smmu_get_domain(struct domain *d,
 				struct device *dev)
 {
@@ -3003,6 +3034,53 @@ static void arm_smmu_iommu_xen_domain_teardown(struc=
t domain *d)
 	xfree(xen_domain);
 }
=20
+static int arm_smmu_attach_guest_config(struct domain *d, u32 sid,
+		struct iommu_guest_config *cfg)
+{
+	int ret =3D -EINVAL;
+	unsigned long flags;
+	struct arm_smmu_master *master;
+	struct arm_smmu_domain *smmu_domain;
+	struct arm_smmu_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv;
+	struct iommu_domain *io_domain =3D arm_smmu_get_domain_by_sid(d, sid);
+
+	if (!io_domain)
+		return -ENODEV;
+
+	smmu_domain =3D to_smmu_domain(io_domain);
+
+	spin_lock(&xen_domain->lock);
+
+	switch (cfg->config) {
+	case ARM_SMMU_DOMAIN_ABORT:
+		smmu_domain->abort =3D true;
+		break;
+	case ARM_SMMU_DOMAIN_BYPASS:
+		smmu_domain->abort =3D false;
+		break;
+	case ARM_SMMU_DOMAIN_NESTED:
+		/* Enable Nested stage translation. */
+		smmu_domain->stage =3D ARM_SMMU_DOMAIN_NESTED;
+		smmu_domain->s1_cfg.s1ctxptr =3D cfg->s1ctxptr;
+		smmu_domain->s1_cfg.s1fmt =3D cfg->s1fmt;
+		smmu_domain->s1_cfg.s1cdmax =3D cfg->s1cdmax;
+		smmu_domain->abort =3D false;
+		break;
+	default:
+		goto out;
+	}
+
+	spin_lock_irqsave(&smmu_domain->devices_lock, flags);
+	list_for_each_entry(master, &smmu_domain->devices, domain_head)
+		arm_smmu_install_ste_for_dev(master);
+	spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
+
+	ret =3D 0;
+out:
+	spin_unlock(&xen_domain->lock);
+	return ret;
+}
+
 static const struct iommu_ops arm_smmu_iommu_ops =3D {
 	.page_sizes		=3D PAGE_SIZE_4K,
 	.init			=3D arm_smmu_iommu_xen_domain_init,
@@ -3015,6 +3093,7 @@ static const struct iommu_ops arm_smmu_iommu_ops =3D =
{
 	.unmap_page		=3D arm_iommu_unmap_page,
 	.dt_xlate		=3D arm_smmu_dt_xlate,
 	.add_device		=3D arm_smmu_add_device,
+	.attach_guest_config =3D arm_smmu_attach_guest_config
 };
=20
 static __init int arm_smmu_dt_init(struct dt_device_node *dev,
diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug=
h/arm/smmu-v3.h
index d54f0a79f2..3e3a6cd080 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.h
+++ b/xen/drivers/passthrough/arm/smmu-v3.h
@@ -398,6 +398,7 @@ enum arm_smmu_domain_stage {
 	ARM_SMMU_DOMAIN_S2,
 	ARM_SMMU_DOMAIN_NESTED,
 	ARM_SMMU_DOMAIN_BYPASS,
+	ARM_SMMU_DOMAIN_ABORT,
 };
=20
 /* Xen specific code. */
diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou=
gh/arm/vsmmu-v3.c
index 3ecbe4861b..3b073b9dac 100644
--- a/xen/drivers/passthrough/arm/vsmmu-v3.c
+++ b/xen/drivers/passthrough/arm/vsmmu-v3.c
@@ -224,8 +224,11 @@ static int arm_vsmmu_handle_cfgi_ste(struct virt_smmu =
*smmu, uint64_t *cmdptr)
 {
     int ret;
     uint64_t ste[STRTAB_STE_DWORDS];
+    struct domain *d =3D smmu->d;
+    struct domain_iommu *hd =3D dom_iommu(d);
     struct arm_vsmmu_s1_trans_cfg s1_cfg =3D {0};
     uint32_t sid =3D smmu_cmd_get_sid(cmdptr[0]);
+    struct iommu_guest_config guest_cfg =3D {0};
=20
     ret =3D arm_vsmmu_find_ste(smmu, sid, ste);
     if ( ret )
@@ -235,6 +238,21 @@ static int arm_vsmmu_handle_cfgi_ste(struct virt_smmu =
*smmu, uint64_t *cmdptr)
     if ( ret )
         return (ret =3D=3D -EAGAIN ) ? 0 : ret;
=20
+    guest_cfg.s1ctxptr =3D s1_cfg.s1ctxptr;
+    guest_cfg.s1fmt =3D s1_cfg.s1fmt;
+    guest_cfg.s1cdmax =3D s1_cfg.s1cdmax;
+
+    if ( s1_cfg.bypassed )
+        guest_cfg.config =3D ARM_SMMU_DOMAIN_BYPASS;
+    else if ( s1_cfg.aborted )
+        guest_cfg.config =3D ARM_SMMU_DOMAIN_ABORT;
+    else
+        guest_cfg.config =3D ARM_SMMU_DOMAIN_NESTED;
+
+    ret =3D hd->platform_ops->attach_guest_config(d, sid, &guest_cfg);
+    if ( ret )
+        return ret;
+
     return 0;
 }
=20
diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h
index 37c4a1dc82..21f905d44f 100644
--- a/xen/include/xen/iommu.h
+++ b/xen/include/xen/iommu.h
@@ -311,6 +311,15 @@ static inline int iommu_add_dt_pci_sideband_ids(struct=
 pci_dev *pdev)
=20
 #endif /* HAS_DEVICE_TREE_DISCOVERY */
=20
+#ifdef CONFIG_ARM
+struct iommu_guest_config {
+    paddr_t     s1ctxptr;
+    uint8_t     config;
+    uint8_t     s1fmt;
+    uint8_t     s1cdmax;
+};
+#endif /* CONFIG_ARM */
+
 struct page_info;
=20
 /*
@@ -387,6 +396,11 @@ struct iommu_ops {
 #endif
     /* Inhibit all interrupt generation, to be used at shutdown. */
     void (*quiesce)(void);
+
+#ifdef CONFIG_ARM
+    int (*attach_guest_config)(struct domain *d, u32 sid,
+                               struct iommu_guest_config *cfg);
+#endif
 };
=20
 /*
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Bertrand Marquis
	, Stefano Stabellini ,
	Julien Grall , Michal Orzel , Volodymyr
 Babchuk , Milan Djokic 
Subject: [PATCH 03/20] xen/arm: smmuv3: Alloc io_domain for each device
Thread-Topic: [PATCH 03/20] xen/arm: smmuv3: Alloc io_domain for each device
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From: Rahul Singh 

In current implementation io_domain is allocated once for each xen
domain as Stage2 translation is common for all devices in same xen
domain.

Nested stage supports S1 and S2 configuration at the same time. Stage1
translation will be different for each device as linux kernel will
allocate page-table for each device.

Alloc io_domain for each device so that each device can have different
Stage-1 and Stage-2 configuration structure.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/drivers/passthrough/arm/smmu-v3.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug=
h/arm/smmu-v3.c
index 5c96e8ec7c..15ff703458 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.c
+++ b/xen/drivers/passthrough/arm/smmu-v3.c
@@ -2790,11 +2790,13 @@ static struct arm_smmu_device *arm_smmu_get_by_dev(=
const struct device *dev)
 static struct iommu_domain *arm_smmu_get_domain(struct domain *d,
 				struct device *dev)
 {
+	unsigned long flags;
 	struct iommu_domain *io_domain;
 	struct arm_smmu_domain *smmu_domain;
 	struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev);
 	struct arm_smmu_xen_domain *xen_domain =3D dom_iommu(d)->arch.priv;
 	struct arm_smmu_device *smmu =3D arm_smmu_get_by_dev(fwspec->iommu_dev);
+	struct arm_smmu_master *master;
=20
 	if (!smmu)
 		return NULL;
@@ -2805,8 +2807,15 @@ static struct iommu_domain *arm_smmu_get_domain(stru=
ct domain *d,
 	 */
 	list_for_each_entry(io_domain, &xen_domain->contexts, list) {
 		smmu_domain =3D to_smmu_domain(io_domain);
-		if (smmu_domain->smmu =3D=3D smmu)
-			return io_domain;
+
+		spin_lock_irqsave(&smmu_domain->devices_lock, flags);
+		list_for_each_entry(master, &smmu_domain->devices, domain_head) {
+			if (master->dev =3D=3D dev) {
+				spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
+				return io_domain;
+			}
+		}
+		spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
 	}
 	return NULL;
 }
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Milan Djokic 
Subject: [PATCH 09/20] xen/arm: vsmmuv3: Add support for cmdqueue handling
Thread-Topic: [PATCH 09/20] xen/arm: vsmmuv3: Add support for cmdqueue
 handling
Thread-Index: AQHcB7ygaIRJk82f2U2cK2snO9G44g==
Date: Thu, 7 Aug 2025 16:59:24 +0000
Message-ID:
 <61dbd27ea536b80b6d0de1bf3ad0b4bab38e83a7.1754580688.git.milan_djokic@epam.com>
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From: Rahul Singh 

Add support for virtual cmdqueue handling for guests

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/drivers/passthrough/arm/vsmmu-v3.c | 101 +++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou=
gh/arm/vsmmu-v3.c
index 3ae1e62a50..84bd1f7327 100644
--- a/xen/drivers/passthrough/arm/vsmmu-v3.c
+++ b/xen/drivers/passthrough/arm/vsmmu-v3.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
=20
+#include 
 #include 
 #include 
 #include 
@@ -25,6 +26,26 @@
 /* Struct to hold the vIOMMU ops and vIOMMU type */
 extern const struct viommu_desc __read_mostly *cur_viommu;
=20
+/* SMMUv3 command definitions */
+#define CMDQ_OP_PREFETCH_CFG    0x1
+#define CMDQ_OP_CFGI_STE        0x3
+#define CMDQ_OP_CFGI_ALL        0x4
+#define CMDQ_OP_CFGI_CD         0x5
+#define CMDQ_OP_CFGI_CD_ALL     0x6
+#define CMDQ_OP_TLBI_NH_ASID    0x11
+#define CMDQ_OP_TLBI_NH_VA      0x12
+#define CMDQ_OP_TLBI_NSNH_ALL   0x30
+#define CMDQ_OP_CMD_SYNC        0x46
+
+/* Queue Handling */
+#define Q_BASE(q)       ((q)->q_base & Q_BASE_ADDR_MASK)
+#define Q_CONS_ENT(q)   (Q_BASE(q) + Q_IDX(q, (q)->cons) * (q)->ent_size)
+#define Q_PROD_ENT(q)   (Q_BASE(q) + Q_IDX(q, (q)->prod) * (q)->ent_size)
+
+/* Helper Macros */
+#define smmu_get_cmdq_enabled(x)    FIELD_GET(CR0_CMDQEN, x)
+#define smmu_cmd_get_command(x)     FIELD_GET(CMDQ_0_OP, x)
+
 /* virtual smmu queue */
 struct arm_vsmmu_queue {
     uint64_t    q_base; /* base register */
@@ -49,8 +70,80 @@ struct virt_smmu {
     uint64_t    gerror_irq_cfg0;
     uint64_t    evtq_irq_cfg0;
     struct      arm_vsmmu_queue evtq, cmdq;
+    spinlock_t  cmd_queue_lock;
 };
=20
+/* Queue manipulation functions */
+static bool queue_empty(struct arm_vsmmu_queue *q)
+{
+    return Q_IDX(q, q->prod) =3D=3D Q_IDX(q, q->cons) &&
+           Q_WRP(q, q->prod) =3D=3D Q_WRP(q, q->cons);
+}
+
+static void queue_inc_cons(struct arm_vsmmu_queue *q)
+{
+    uint32_t cons =3D (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1;
+    q->cons =3D Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons);
+}
+
+static void dump_smmu_command(uint64_t *command)
+{
+    gdprintk(XENLOG_ERR, "cmd 0x%02llx: %016lx %016lx\n",
+             smmu_cmd_get_command(command[0]), command[0], command[1]);
+}
+static int arm_vsmmu_handle_cmds(struct virt_smmu *smmu)
+{
+    struct arm_vsmmu_queue *q =3D &smmu->cmdq;
+    struct domain *d =3D smmu->d;
+    uint64_t command[CMDQ_ENT_DWORDS];
+    paddr_t addr;
+
+    if ( !smmu_get_cmdq_enabled(smmu->cr[0]) )
+        return 0;
+
+    while ( !queue_empty(q) )
+    {
+        int ret;
+
+        addr =3D Q_CONS_ENT(q);
+        ret =3D access_guest_memory_by_ipa(d, addr, command,
+                                         sizeof(command), false);
+        if ( ret )
+            return ret;
+
+        switch ( smmu_cmd_get_command(command[0]) )
+        {
+        case CMDQ_OP_CFGI_STE:
+            break;
+        case CMDQ_OP_PREFETCH_CFG:
+        case CMDQ_OP_CFGI_CD:
+        case CMDQ_OP_CFGI_CD_ALL:
+        case CMDQ_OP_CFGI_ALL:
+        case CMDQ_OP_CMD_SYNC:
+            break;
+        case CMDQ_OP_TLBI_NH_ASID:
+        case CMDQ_OP_TLBI_NSNH_ALL:
+        case CMDQ_OP_TLBI_NH_VA:
+            if ( !iommu_iotlb_flush_all(smmu->d, 1) )
+                break;
+        default:
+            gdprintk(XENLOG_ERR, "vSMMUv3: unhandled command\n");
+            dump_smmu_command(command);
+            break;
+        }
+
+        if ( ret )
+        {
+            gdprintk(XENLOG_ERR,
+                     "vSMMUv3: command error %d while handling command\n",
+                     ret);
+            dump_smmu_command(command);
+        }
+        queue_inc_cons(q);
+    }
+    return 0;
+}
+
 static int vsmmuv3_mmio_write(struct vcpu *v, mmio_info_t *info,
                               register_t r, void *priv)
 {
@@ -104,9 +197,15 @@ static int vsmmuv3_mmio_write(struct vcpu *v, mmio_inf=
o_t *info,
         break;
=20
     case VREG32(ARM_SMMU_CMDQ_PROD):
+        spin_lock(&smmu->cmd_queue_lock);
         reg32 =3D smmu->cmdq.prod;
         vreg_reg32_update(®32, r, info);
         smmu->cmdq.prod =3D reg32;
+
+        if ( arm_vsmmu_handle_cmds(smmu) )
+            gdprintk(XENLOG_ERR, "error handling vSMMUv3 commands\n");
+
+        spin_unlock(&smmu->cmd_queue_lock);
         break;
=20
     case VREG32(ARM_SMMU_CMDQ_CONS):
@@ -326,6 +425,8 @@ static int vsmmuv3_init_single(struct domain *d, paddr_=
t addr, paddr_t size)
     smmu->evtq.q_base =3D FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_EVTQS);
     smmu->evtq.ent_size =3D EVTQ_ENT_DWORDS * DWORDS_BYTES;
=20
+    spin_lock_init(&smmu->cmd_queue_lock);
+
     register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu);
=20
     /* Register the vIOMMU to be able to clean it up later. */
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Anthony PERARD
	, Nick Rosbrook , George Dunlap
	, Juergen Gross , Milan Djokic
	
Subject: [PATCH 06/20] xen/domctl: Add XEN_DOMCTL_CONFIG_VIOMMU_* and viommu
 config param
Thread-Topic: [PATCH 06/20] xen/domctl: Add XEN_DOMCTL_CONFIG_VIOMMU_* and
 viommu config param
Thread-Index: AQHcB7yeWtqOMnUc4US5ATSpbJFzIQ==
Date: Thu, 7 Aug 2025 16:59:21 +0000
Message-ID:
 <76c461a4af7c824bc9a3d0958733ddb12ee724b7.1754580688.git.milan_djokic@epam.com>
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From: Rahul Singh 

Add new viommu_type field and field values XEN_DOMCTL_CONFIG_VIOMMU_NONE
XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3 in xen_arch_domainconfig to
enable/disable vIOMMU support for domains.

Also add viommu=3D"N" parameter to xl domain configuration to enable the
vIOMMU for the domains. Currently, only the "smmuv3" type is supported
for ARM.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 docs/man/xl.cfg.5.pod.in             | 13 +++++++++++++
 tools/golang/xenlight/helpers.gen.go |  2 ++
 tools/golang/xenlight/types.gen.go   |  1 +
 tools/include/libxl.h                |  5 +++++
 tools/libs/light/libxl_arm.c         | 13 +++++++++++++
 tools/libs/light/libxl_types.idl     |  6 ++++++
 tools/xl/xl_parse.c                  | 10 ++++++++++
 7 files changed, 50 insertions(+)

diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
index f0c920b39d..25e9be073c 100644
--- a/docs/man/xl.cfg.5.pod.in
+++ b/docs/man/xl.cfg.5.pod.in
@@ -3125,6 +3125,19 @@ This option is only implemented for Arm where the de=
fault is enabled.
=20
 =3Dback
=20
+=3Dover 4
+
+=3Ditem B
+
+To enable viommu, user must specify the following option in the VM
+config file:
+
+viommu =3D "smmuv3"
+
+Currently, only the "smmuv3" type is supported for ARM.
+
+=3Dback
+
 =3Dhead3 x86
=20
 =3Dover 4
diff --git a/tools/golang/xenlight/helpers.gen.go b/tools/golang/xenlight/h=
elpers.gen.go
index 667030cbd7..23635afefe 100644
--- a/tools/golang/xenlight/helpers.gen.go
+++ b/tools/golang/xenlight/helpers.gen.go
@@ -1163,6 +1163,7 @@ x.ArchArm.GicVersion =3D GicVersion(xc.arch_arm.gic_v=
ersion)
 x.ArchArm.Vuart =3D VuartType(xc.arch_arm.vuart)
 x.ArchArm.SveVl =3D SveType(xc.arch_arm.sve_vl)
 x.ArchArm.NrSpis =3D uint32(xc.arch_arm.nr_spis)
+x.ArchArm.Viommu =3D ViommuType(xc.arch_arm.viommu)
 if err :=3D x.ArchX86.MsrRelaxed.fromC(&xc.arch_x86.msr_relaxed);err !=3D =
nil {
 return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err)
 }
@@ -1699,6 +1700,7 @@ xc.arch_arm.gic_version =3D C.libxl_gic_version(x.Arc=
hArm.GicVersion)
 xc.arch_arm.vuart =3D C.libxl_vuart_type(x.ArchArm.Vuart)
 xc.arch_arm.sve_vl =3D C.libxl_sve_type(x.ArchArm.SveVl)
 xc.arch_arm.nr_spis =3D C.uint32_t(x.ArchArm.NrSpis)
+xc.arch_arm.viommu =3D C.libxl_viommu_type(x.ArchArm.Viommu)
 if err :=3D x.ArchX86.MsrRelaxed.toC(&xc.arch_x86.msr_relaxed); err !=3D n=
il {
 return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err)
 }
diff --git a/tools/golang/xenlight/types.gen.go b/tools/golang/xenlight/typ=
es.gen.go
index e26b3cdfc7..23f5a300e0 100644
--- a/tools/golang/xenlight/types.gen.go
+++ b/tools/golang/xenlight/types.gen.go
@@ -599,6 +599,7 @@ GicVersion GicVersion
 Vuart VuartType
 SveVl SveType
 NrSpis uint32
+Viommu ViommuType
 }
 ArchX86 struct {
 MsrRelaxed Defbool
diff --git a/tools/include/libxl.h b/tools/include/libxl.h
index 185f74d8a8..f985426ae1 100644
--- a/tools/include/libxl.h
+++ b/tools/include/libxl.h
@@ -313,6 +313,11 @@
  */
 #define LIBXL_HAVE_BUILDINFO_ARCH_NR_SPIS 1
=20
+/*
+ * libxl_domain_build_info has the arch_arm.viommu_type field.
+ */
+#define LIBXL_HAVE_BUILDINFO_ARM_VIOMMU 1
+
 /*
  * LIBXL_HAVE_SOFT_RESET indicates that libxl supports performing
  * 'soft reset' for domains and there is 'soft_reset' shutdown reason
diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c
index 4a19a8d22b..44b7bcd672 100644
--- a/tools/libs/light/libxl_arm.c
+++ b/tools/libs/light/libxl_arm.c
@@ -233,6 +233,19 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
         config->arch.sve_vl =3D d_config->b_info.arch_arm.sve_vl / 128U;
     }
=20
+    switch (d_config->b_info.arch_arm.viommu_type) {
+    case LIBXL_VIOMMU_TYPE_NONE:
+        config->arch.viommu_type =3D XEN_DOMCTL_CONFIG_VIOMMU_NONE;
+        break;
+    case LIBXL_VIOMMU_TYPE_SMMUV3:
+        config->arch.viommu_type =3D XEN_DOMCTL_CONFIG_VIOMMU_SMMUV3;
+        break;
+    default:
+        LOG(ERROR, "Unknown vIOMMU type %d",
+            d_config->b_info.arch_arm.viommu_type);
+        return ERROR_FAIL;
+    }
+
     return 0;
 }
=20
diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_type=
s.idl
index a6030a2dbd..0c8d2c7156 100644
--- a/tools/libs/light/libxl_types.idl
+++ b/tools/libs/light/libxl_types.idl
@@ -551,6 +551,11 @@ libxl_sve_type =3D Enumeration("sve_type", [
     (2048, "2048")
     ], init_val =3D "LIBXL_SVE_TYPE_DISABLED")
=20
+libxl_viommu_type =3D Enumeration("viommu_type", [
+    (0, "none"),
+    (1, "smmuv3")
+    ], init_val =3D "LIBXL_VIOMMU_TYPE_NONE")
+
 libxl_rdm_reserve =3D Struct("rdm_reserve", [
     ("strategy",    libxl_rdm_reserve_strategy),
     ("policy",      libxl_rdm_reserve_policy),
@@ -725,6 +730,7 @@ libxl_domain_build_info =3D Struct("domain_build_info",=
[
                                ("vuart", libxl_vuart_type),
                                ("sve_vl", libxl_sve_type),
                                ("nr_spis", uint32, {'init_val': 'LIBXL_NR_=
SPIS_DEFAULT'}),
+                               ("viommu_type", libxl_viommu_type),
                               ])),
     ("arch_x86", Struct(None, [("msr_relaxed", libxl_defbool),
                               ])),
diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
index 90c9386f5b..32236f7e5f 100644
--- a/tools/xl/xl_parse.c
+++ b/tools/xl/xl_parse.c
@@ -2989,6 +2989,16 @@ skip_usbdev:
     xlu_cfg_get_defbool(config, "trap_unmapped_accesses",
                         &b_info->trap_unmapped_accesses, 0);
=20
+
+    if (!xlu_cfg_get_string (config, "viommu", &buf, 1)) {
+        e =3D libxl_viommu_type_from_string(buf, &b_info->arch_arm.viommu_=
type);
+        if (e) {
+            fprintf(stderr,
+                    "Unknown vIOMMU type \"%s\" specified\n", buf);
+            exit(-ERROR_FAIL);
+        }
+    }
+
     parse_vkb_list(config, d_config);
=20
     d_config->virtios =3D NULL;
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Milan Djokic 
Subject: [PATCH 10/20] xen/arm: vsmmuv3: Add support for command CMD_CFGI_STE
Thread-Topic: [PATCH 10/20] xen/arm: vsmmuv3: Add support for command
 CMD_CFGI_STE
Thread-Index: AQHcB7yhsDZE5DA1DUCoBRmJXjwGPQ==
Date: Thu, 7 Aug 2025 16:59:25 +0000
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From: Rahul Singh 

CMD_CFGI_STE is used to invalidate/validate the STE. Emulated vSMMUv3
driver in XEN will read the STE from the guest memory space and capture
the Stage-1 configuration required to support nested translation.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/drivers/passthrough/arm/vsmmu-v3.c | 148 +++++++++++++++++++++++++
 1 file changed, 148 insertions(+)

diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou=
gh/arm/vsmmu-v3.c
index 84bd1f7327..3ecbe4861b 100644
--- a/xen/drivers/passthrough/arm/vsmmu-v3.c
+++ b/xen/drivers/passthrough/arm/vsmmu-v3.c
@@ -45,6 +45,21 @@ extern const struct viommu_desc __read_mostly *cur_viomm=
u;
 /* Helper Macros */
 #define smmu_get_cmdq_enabled(x)    FIELD_GET(CR0_CMDQEN, x)
 #define smmu_cmd_get_command(x)     FIELD_GET(CMDQ_0_OP, x)
+#define smmu_cmd_get_sid(x)         FIELD_GET(CMDQ_PREFETCH_0_SID, x)
+#define smmu_get_ste_s1cdmax(x)     FIELD_GET(STRTAB_STE_0_S1CDMAX, x)
+#define smmu_get_ste_s1fmt(x)       FIELD_GET(STRTAB_STE_0_S1FMT, x)
+#define smmu_get_ste_s1stalld(x)    FIELD_GET(STRTAB_STE_1_S1STALLD, x)
+#define smmu_get_ste_s1ctxptr(x)    FIELD_PREP(STRTAB_STE_0_S1CTXPTR_MASK,=
 \
+                                    FIELD_GET(STRTAB_STE_0_S1CTXPTR_MASK, =
x))
+
+/* stage-1 translation configuration */
+struct arm_vsmmu_s1_trans_cfg {
+    paddr_t s1ctxptr;
+    uint8_t s1fmt;
+    uint8_t s1cdmax;
+    bool    bypassed;             /* translation is bypassed */
+    bool    aborted;              /* translation is aborted */
+};
=20
 /* virtual smmu queue */
 struct arm_vsmmu_queue {
@@ -91,6 +106,138 @@ static void dump_smmu_command(uint64_t *command)
     gdprintk(XENLOG_ERR, "cmd 0x%02llx: %016lx %016lx\n",
              smmu_cmd_get_command(command[0]), command[0], command[1]);
 }
+static int arm_vsmmu_find_ste(struct virt_smmu *smmu, uint32_t sid,
+                              uint64_t *ste)
+{
+    paddr_t addr, strtab_base;
+    struct domain *d =3D smmu->d;
+    uint32_t log2size;
+    int strtab_size_shift;
+    int ret;
+
+    log2size =3D FIELD_GET(STRTAB_BASE_CFG_LOG2SIZE, smmu->strtab_base_cfg=
);
+
+    if ( sid >=3D (1 << MIN(log2size, SMMU_IDR1_SIDSIZE)) )
+        return -EINVAL;
+
+    if ( smmu->features & STRTAB_BASE_CFG_FMT_2LVL )
+    {
+        int idx, max_l2_ste, span;
+        paddr_t l1ptr, l2ptr;
+        uint64_t l1std;
+
+        strtab_size_shift =3D MAX(5, (int)log2size - smmu->sid_split - 1 +=
 3);
+        strtab_base =3D smmu->strtab_base & STRTAB_BASE_ADDR_MASK &
+                        ~GENMASK_ULL(strtab_size_shift, 0);
+        idx =3D (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS;
+        l1ptr =3D (paddr_t)(strtab_base + idx * sizeof(l1std));
+
+        ret =3D access_guest_memory_by_ipa(d, l1ptr, &l1std,
+                                         sizeof(l1std), false);
+        if ( ret )
+        {
+            gdprintk(XENLOG_ERR,
+                     "Could not read L1PTR at 0X%"PRIx64"\n", l1ptr);
+            return ret;
+        }
+
+        span =3D FIELD_GET(STRTAB_L1_DESC_SPAN, l1std);
+        if ( !span )
+        {
+            gdprintk(XENLOG_ERR, "Bad StreamID span\n");
+            return -EINVAL;
+        }
+
+        max_l2_ste =3D (1 << span) - 1;
+        l2ptr =3D FIELD_PREP(STRTAB_L1_DESC_L2PTR_MASK,
+                    FIELD_GET(STRTAB_L1_DESC_L2PTR_MASK, l1std));
+        idx =3D sid & ((1 << smmu->sid_split) - 1);
+        if ( idx > max_l2_ste )
+        {
+            gdprintk(XENLOG_ERR, "idx=3D%d > max_l2_ste=3D%d\n",
+                     idx, max_l2_ste);
+            return -EINVAL;
+        }
+        addr =3D l2ptr + idx * sizeof(*ste) * STRTAB_STE_DWORDS;
+    }
+    else
+    {
+        strtab_size_shift =3D log2size + 5;
+        strtab_base =3D smmu->strtab_base & STRTAB_BASE_ADDR_MASK &
+                      ~GENMASK_ULL(strtab_size_shift, 0);
+        addr =3D strtab_base + sid * sizeof(*ste) * STRTAB_STE_DWORDS;
+    }
+    ret =3D access_guest_memory_by_ipa(d, addr, ste, sizeof(*ste), false);
+    if ( ret )
+    {
+        gdprintk(XENLOG_ERR,
+                "Cannot fetch pte at address=3D0x%"PRIx64"\n", addr);
+        return -EINVAL;
+    }
+
+    return 0;
+}
+
+static int arm_vsmmu_decode_ste(struct virt_smmu *smmu, uint32_t sid,
+                                struct arm_vsmmu_s1_trans_cfg *cfg,
+                                uint64_t *ste)
+{
+    uint64_t val =3D ste[0];
+
+    if ( !(val & STRTAB_STE_0_V) )
+        return -EAGAIN;
+
+    switch ( FIELD_GET(STRTAB_STE_0_CFG, val) )
+    {
+    case STRTAB_STE_0_CFG_BYPASS:
+        cfg->bypassed =3D true;
+        return 0;
+    case STRTAB_STE_0_CFG_ABORT:
+        cfg->aborted =3D true;
+        return 0;
+    case STRTAB_STE_0_CFG_S1_TRANS:
+        break;
+    case STRTAB_STE_0_CFG_S2_TRANS:
+        gdprintk(XENLOG_ERR, "vSMMUv3 does not support stage 2 yet\n");
+        goto bad_ste;
+    default:
+        BUG(); /* STE corruption */
+    }
+
+    cfg->s1ctxptr =3D smmu_get_ste_s1ctxptr(val);
+    cfg->s1fmt =3D smmu_get_ste_s1fmt(val);
+    cfg->s1cdmax =3D smmu_get_ste_s1cdmax(val);
+    if ( cfg->s1cdmax !=3D 0 )
+    {
+        gdprintk(XENLOG_ERR,
+                 "vSMMUv3 does not support multiple context descriptors\n"=
);
+        goto bad_ste;
+    }
+
+    return 0;
+
+bad_ste:
+    return -EINVAL;
+}
+
+static int arm_vsmmu_handle_cfgi_ste(struct virt_smmu *smmu, uint64_t *cmd=
ptr)
+{
+    int ret;
+    uint64_t ste[STRTAB_STE_DWORDS];
+    struct arm_vsmmu_s1_trans_cfg s1_cfg =3D {0};
+    uint32_t sid =3D smmu_cmd_get_sid(cmdptr[0]);
+
+    ret =3D arm_vsmmu_find_ste(smmu, sid, ste);
+    if ( ret )
+        return ret;
+
+    ret =3D arm_vsmmu_decode_ste(smmu, sid, &s1_cfg, ste);
+    if ( ret )
+        return (ret =3D=3D -EAGAIN ) ? 0 : ret;
+
+    return 0;
+}
+
 static int arm_vsmmu_handle_cmds(struct virt_smmu *smmu)
 {
     struct arm_vsmmu_queue *q =3D &smmu->cmdq;
@@ -114,6 +261,7 @@ static int arm_vsmmu_handle_cmds(struct virt_smmu *smmu=
)
         switch ( smmu_cmd_get_command(command[0]) )
         {
         case CMDQ_OP_CFGI_STE:
+            ret =3D arm_vsmmu_handle_cfgi_ste(smmu, command);
             break;
         case CMDQ_OP_PREFETCH_CFG:
         case CMDQ_OP_CFGI_CD:
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Milan Djokic 
Subject: [PATCH 12/20] xen/arm: vsmmuv3: Add support for event queue and
 global error
Thread-Topic: [PATCH 12/20] xen/arm: vsmmuv3: Add support for event queue and
 global error
Thread-Index: AQHcB7yi7AssCwTYaUG/iDk08I6dEw==
Date: Thu, 7 Aug 2025 16:59:27 +0000
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From: Rahul Singh 

Event queue is used to send the events to guest when there is an events/
faults. Add support for event queue to send events to guest.

Global error in SMMUv3 hw will be updated in smmu_gerror and
smmu_gerrorn register. Add support for global error registers to send
global error to guest.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/drivers/passthrough/arm/smmu-v3.h  |  20 +++
 xen/drivers/passthrough/arm/vsmmu-v3.c | 169 ++++++++++++++++++++++++-
 xen/include/public/arch-arm.h          |   5 +-
 3 files changed, 186 insertions(+), 8 deletions(-)

diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug=
h/arm/smmu-v3.h
index 3e3a6cd080..820271a413 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.h
+++ b/xen/drivers/passthrough/arm/smmu-v3.h
@@ -354,6 +354,26 @@
=20
 #define EVTQ_0_ID			GENMASK_ULL(7, 0)
=20
+#define EVT_ID_BAD_STREAMID		0x02
+#define EVT_ID_BAD_STE		    	0x04
+#define EVT_ID_TRANSLATION_FAULT	0x10
+#define EVT_ID_ADDR_SIZE_FAULT		0x11
+#define EVT_ID_ACCESS_FAULT		0x12
+#define EVT_ID_PERMISSION_FAULT		0x13
+
+#define EVTQ_0_SSV			(1UL << 11)
+#define EVTQ_0_SSID			GENMASK_ULL(31, 12)
+#define EVTQ_0_SID			GENMASK_ULL(63, 32)
+#define EVTQ_1_STAG			GENMASK_ULL(15, 0)
+#define EVTQ_1_STALL			(1UL << 31)
+#define EVTQ_1_PnU			(1UL << 33)
+#define EVTQ_1_InD			(1UL << 34)
+#define EVTQ_1_RnW			(1UL << 35)
+#define EVTQ_1_S2			(1UL << 39)
+#define EVTQ_1_CLASS			GENMASK_ULL(41, 40)
+#define EVTQ_1_TT_READ			(1UL << 44)
+#define EVTQ_2_ADDR			GENMASK_ULL(63, 0)
+#define EVTQ_3_IPA			GENMASK_ULL(51, 12)
 /* PRI queue */
 #define PRIQ_ENT_SZ_SHIFT		4
 #define PRIQ_ENT_DWORDS			((1 << PRIQ_ENT_SZ_SHIFT) >> 3)
diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou=
gh/arm/vsmmu-v3.c
index 3b073b9dac..7a6c18df53 100644
--- a/xen/drivers/passthrough/arm/vsmmu-v3.c
+++ b/xen/drivers/passthrough/arm/vsmmu-v3.c
@@ -44,6 +44,7 @@ extern const struct viommu_desc __read_mostly *cur_viommu=
;
=20
 /* Helper Macros */
 #define smmu_get_cmdq_enabled(x)    FIELD_GET(CR0_CMDQEN, x)
+#define smmu_get_evtq_enabled(x)    FIELD_GET(CR0_EVTQEN, x)
 #define smmu_cmd_get_command(x)     FIELD_GET(CMDQ_0_OP, x)
 #define smmu_cmd_get_sid(x)         FIELD_GET(CMDQ_PREFETCH_0_SID, x)
 #define smmu_get_ste_s1cdmax(x)     FIELD_GET(STRTAB_STE_0_S1CDMAX, x)
@@ -52,6 +53,35 @@ extern const struct viommu_desc __read_mostly *cur_viomm=
u;
 #define smmu_get_ste_s1ctxptr(x)    FIELD_PREP(STRTAB_STE_0_S1CTXPTR_MASK,=
 \
                                     FIELD_GET(STRTAB_STE_0_S1CTXPTR_MASK, =
x))
=20
+/* event queue entry */
+struct arm_smmu_evtq_ent {
+    /* Common fields */
+    uint8_t     opcode;
+    uint32_t    sid;
+
+    /* Event-specific fields */
+    union {
+        struct {
+            uint32_t ssid;
+            bool ssv;
+        } c_bad_ste_streamid;
+
+        struct {
+            bool stall;
+            uint16_t stag;
+            uint32_t ssid;
+            bool ssv;
+            bool s2;
+            uint64_t addr;
+            bool rnw;
+            bool pnu;
+            bool ind;
+            uint8_t class;
+            uint64_t addr2;
+        } f_translation;
+    };
+};
+
 /* stage-1 translation configuration */
 struct arm_vsmmu_s1_trans_cfg {
     paddr_t s1ctxptr;
@@ -82,6 +112,7 @@ struct virt_smmu {
     uint32_t    strtab_base_cfg;
     uint64_t    strtab_base;
     uint32_t    irq_ctrl;
+    uint32_t    virq;
     uint64_t    gerror_irq_cfg0;
     uint64_t    evtq_irq_cfg0;
     struct      arm_vsmmu_queue evtq, cmdq;
@@ -89,6 +120,12 @@ struct virt_smmu {
 };
=20
 /* Queue manipulation functions */
+static bool queue_full(struct arm_vsmmu_queue *q)
+{
+    return Q_IDX(q, q->prod) =3D=3D Q_IDX(q, q->cons) &&
+           Q_WRP(q, q->prod) !=3D Q_WRP(q, q->cons);
+}
+
 static bool queue_empty(struct arm_vsmmu_queue *q)
 {
     return Q_IDX(q, q->prod) =3D=3D Q_IDX(q, q->cons) &&
@@ -101,11 +138,105 @@ static void queue_inc_cons(struct arm_vsmmu_queue *q=
)
     q->cons =3D Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons);
 }
=20
+static void queue_inc_prod(struct arm_vsmmu_queue *q)
+{
+    u32 prod =3D (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + 1;
+    q->prod =3D Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod);
+}
+
 static void dump_smmu_command(uint64_t *command)
 {
     gdprintk(XENLOG_ERR, "cmd 0x%02llx: %016lx %016lx\n",
              smmu_cmd_get_command(command[0]), command[0], command[1]);
 }
+
+static void arm_vsmmu_inject_irq(struct virt_smmu *smmu, bool is_gerror,
+                                uint32_t gerror_err)
+{
+    uint32_t new_gerrors, pending;
+
+    if ( is_gerror )
+    {
+        /* trigger global error irq to guest */
+        pending =3D smmu->gerror ^ smmu->gerrorn;
+        new_gerrors =3D ~pending & gerror_err;
+
+        /* only toggle non pending errors */
+        if (!new_gerrors)
+            return;
+
+        smmu->gerror ^=3D new_gerrors;
+    }
+
+    vgic_inject_irq(smmu->d, NULL, smmu->virq, true);
+}
+
+static int arm_vsmmu_write_evtq(struct virt_smmu *smmu, uint64_t *evt)
+{
+    struct arm_vsmmu_queue *q =3D &smmu->evtq;
+    struct domain *d =3D smmu->d;
+    paddr_t addr;
+    int ret;
+
+    if ( !smmu_get_evtq_enabled(smmu->cr[0]) )
+        return -EINVAL;
+
+    if ( queue_full(q) )
+        return -EINVAL;
+
+    addr =3D Q_PROD_ENT(q);
+    ret =3D access_guest_memory_by_gpa(d, addr, evt,
+                                     sizeof(*evt) * EVTQ_ENT_DWORDS, true)=
;
+    if ( ret )
+        return ret;
+
+    queue_inc_prod(q);
+
+    /* trigger eventq irq to guest */
+    if ( !queue_empty(q) )
+        arm_vsmmu_inject_irq(smmu, false, 0);
+
+    return 0;
+}
+
+void arm_vsmmu_send_event(struct virt_smmu *smmu,
+                          struct arm_smmu_evtq_ent *ent)
+{
+    uint64_t evt[EVTQ_ENT_DWORDS];
+    int ret;
+
+    memset(evt, 0, 1 << EVTQ_ENT_SZ_SHIFT);
+
+    if ( !smmu_get_evtq_enabled(smmu->cr[0]) )
+        return;
+
+    evt[0] |=3D FIELD_PREP(EVTQ_0_ID, ent->opcode);
+    evt[0] |=3D FIELD_PREP(EVTQ_0_SID, ent->sid);
+
+    switch (ent->opcode)
+    {
+    case EVT_ID_BAD_STREAMID:
+    case EVT_ID_BAD_STE:
+        evt[0] |=3D FIELD_PREP(EVTQ_0_SSID, ent->c_bad_ste_streamid.ssid);
+        evt[0] |=3D FIELD_PREP(EVTQ_0_SSV, ent->c_bad_ste_streamid.ssv);
+        break;
+    case EVT_ID_TRANSLATION_FAULT:
+    case EVT_ID_ADDR_SIZE_FAULT:
+    case EVT_ID_ACCESS_FAULT:
+    case EVT_ID_PERMISSION_FAULT:
+        break;
+    default:
+        gdprintk(XENLOG_WARNING, "vSMMUv3: event opcode is bad\n");
+        break;
+    }
+
+    ret =3D arm_vsmmu_write_evtq(smmu, evt);
+    if ( ret )
+        arm_vsmmu_inject_irq(smmu, true, GERROR_EVTQ_ABT_ERR);
+
+    return;
+}
+
 static int arm_vsmmu_find_ste(struct virt_smmu *smmu, uint32_t sid,
                               uint64_t *ste)
 {
@@ -114,11 +245,22 @@ static int arm_vsmmu_find_ste(struct virt_smmu *smmu,=
 uint32_t sid,
     uint32_t log2size;
     int strtab_size_shift;
     int ret;
+    struct arm_smmu_evtq_ent ent =3D {
+        .sid =3D sid,
+        .c_bad_ste_streamid =3D {
+            .ssid =3D 0,
+            .ssv =3D false,
+        },
+    };
=20
     log2size =3D FIELD_GET(STRTAB_BASE_CFG_LOG2SIZE, smmu->strtab_base_cfg=
);
=20
     if ( sid >=3D (1 << MIN(log2size, SMMU_IDR1_SIDSIZE)) )
+    {
+        ent.opcode =3D EVT_ID_BAD_STE;
+        arm_vsmmu_send_event(smmu, &ent);
         return -EINVAL;
+    }
=20
     if ( smmu->features & STRTAB_BASE_CFG_FMT_2LVL )
     {
@@ -132,7 +274,7 @@ static int arm_vsmmu_find_ste(struct virt_smmu *smmu, u=
int32_t sid,
         idx =3D (sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS;
         l1ptr =3D (paddr_t)(strtab_base + idx * sizeof(l1std));
=20
-        ret =3D access_guest_memory_by_ipa(d, l1ptr, &l1std,
+        ret =3D access_guest_memory_by_gpa(d, l1ptr, &l1std,
                                          sizeof(l1std), false);
         if ( ret )
         {
@@ -156,6 +298,8 @@ static int arm_vsmmu_find_ste(struct virt_smmu *smmu, u=
int32_t sid,
         {
             gdprintk(XENLOG_ERR, "idx=3D%d > max_l2_ste=3D%d\n",
                      idx, max_l2_ste);
+            ent.opcode =3D EVT_ID_BAD_STREAMID;
+            arm_vsmmu_send_event(smmu, &ent);
             return -EINVAL;
         }
         addr =3D l2ptr + idx * sizeof(*ste) * STRTAB_STE_DWORDS;
@@ -167,7 +311,7 @@ static int arm_vsmmu_find_ste(struct virt_smmu *smmu, u=
int32_t sid,
                       ~GENMASK_ULL(strtab_size_shift, 0);
         addr =3D strtab_base + sid * sizeof(*ste) * STRTAB_STE_DWORDS;
     }
-    ret =3D access_guest_memory_by_ipa(d, addr, ste, sizeof(*ste), false);
+    ret =3D access_guest_memory_by_gpa(d, addr, ste, sizeof(*ste), false);
     if ( ret )
     {
         gdprintk(XENLOG_ERR,
@@ -183,6 +327,14 @@ static int arm_vsmmu_decode_ste(struct virt_smmu *smmu=
, uint32_t sid,
                                 uint64_t *ste)
 {
     uint64_t val =3D ste[0];
+    struct arm_smmu_evtq_ent ent =3D {
+        .opcode =3D EVT_ID_BAD_STE,
+        .sid =3D sid,
+        .c_bad_ste_streamid =3D {
+            .ssid =3D 0,
+            .ssv =3D false,
+        },
+    };
=20
     if ( !(val & STRTAB_STE_0_V) )
         return -EAGAIN;
@@ -217,6 +369,7 @@ static int arm_vsmmu_decode_ste(struct virt_smmu *smmu,=
 uint32_t sid,
     return 0;
=20
 bad_ste:
+    arm_vsmmu_send_event(smmu, &ent);
     return -EINVAL;
 }
=20
@@ -271,7 +424,7 @@ static int arm_vsmmu_handle_cmds(struct virt_smmu *smmu=
)
         int ret;
=20
         addr =3D Q_CONS_ENT(q);
-        ret =3D access_guest_memory_by_ipa(d, addr, command,
+        ret =3D access_guest_memory_by_gpa(d, addr, command,
                                          sizeof(command), false);
         if ( ret )
             return ret;
@@ -577,7 +730,8 @@ static const struct mmio_handler_ops vsmmuv3_mmio_handl=
er =3D {
     .write =3D vsmmuv3_mmio_write,
 };
=20
-static int vsmmuv3_init_single(struct domain *d, paddr_t addr, paddr_t siz=
e)
+static int vsmmuv3_init_single(struct domain *d, paddr_t addr,
+                               paddr_t size, uint32_t virq)
 {
     struct virt_smmu *smmu;
=20
@@ -586,6 +740,7 @@ static int vsmmuv3_init_single(struct domain *d, paddr_=
t addr, paddr_t size)
         return -ENOMEM;
=20
     smmu->d =3D d;
+    smmu->virq =3D virq;
     smmu->cmdq.q_base =3D FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_CMDQS);
     smmu->cmdq.ent_size =3D CMDQ_ENT_DWORDS * DWORDS_BYTES;
     smmu->evtq.q_base =3D FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_EVTQS);
@@ -612,14 +767,16 @@ int domain_vsmmuv3_init(struct domain *d)
=20
         list_for_each_entry(hw_iommu, &host_iommu_list, entry)
         {
-            ret =3D vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->size)=
;
+            ret =3D vsmmuv3_init_single(d, hw_iommu->addr, hw_iommu->size,
+                                      hw_iommu->irq);
             if ( ret )
                 return ret;
         }
     }
     else
     {
-        ret =3D vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_S=
IZE);
+        ret =3D vsmmuv3_init_single(d, GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_S=
IZE,
+                                  GUEST_VSMMU_SPI);
         if ( ret )
             return ret;
     }
diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index d6201df06a..1b03222b77 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -521,9 +521,10 @@ typedef uint64_t xen_callback_t;
 #define GUEST_EVTCHN_PPI        31
=20
 #define GUEST_VPL011_SPI        32
+#define GUEST_VSMMU_SPI         33
=20
-#define GUEST_VIRTIO_MMIO_SPI_FIRST   33
-#define GUEST_VIRTIO_MMIO_SPI_LAST    43
+#define GUEST_VIRTIO_MMIO_SPI_FIRST   34
+#define GUEST_VIRTIO_MMIO_SPI_LAST    44
=20
 /*
  * SGI is the preferred delivery mechanism of FF-A pending notifications o=
r
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Jean-Philippe Brucker , Bertrand Marquis
	, Rahul Singh , Stefano
 Stabellini , Julien Grall , Michal
 Orzel , Volodymyr Babchuk ,
	Jonathan Cameron , Eric Auger
	, Keqian Zhu , Will Deacon
	, Joerg Roedel 
Subject: [PATCH 01/20] xen/arm: smmuv3: Maintain a SID->device structure
Thread-Topic: [PATCH 01/20] xen/arm: smmuv3: Maintain a SID->device structure
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Date: Thu, 7 Aug 2025 16:57:18 +0000
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From: Jean-Philippe Brucker 

Backport Linux commit cdf315f907d4. This is the clean backport without
any changes.

When handling faults from the event or PRI queue, we need to find the
struct device associated with a SID. Add a rb_tree to keep track of
SIDs.

Acked-by: Jonathan Cameron 
Reviewed-by: Eric Auger 
Reviewed-by: Keqian Zhu 
Signed-off-by: Jean-Philippe Brucker 
Acked-by: Will Deacon 
Link: https://lore.kernel.org/r/20210401154718.307519-8-jean-philippe@linar=
o.org
Signed-off-by: Joerg Roedel 
Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git cd=
f315f907d4
Signed-off-by: Rahul Singh 
---
 xen/drivers/passthrough/arm/smmu-v3.c | 131 +++++++++++++++++++++-----
 xen/drivers/passthrough/arm/smmu-v3.h |  13 ++-
 2 files changed, 118 insertions(+), 26 deletions(-)

diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug=
h/arm/smmu-v3.c
index 5e9e3e048e..307057ad8a 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.c
+++ b/xen/drivers/passthrough/arm/smmu-v3.c
@@ -793,6 +793,27 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_dev=
ice *smmu, u32 sid)
 	return 0;
 }
=20
+__maybe_unused
+static struct arm_smmu_master *
+arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid)
+{
+	struct rb_node *node;
+	struct arm_smmu_stream *stream;
+
+	node =3D smmu->streams.rb_node;
+	while (node) {
+		stream =3D rb_entry(node, struct arm_smmu_stream, node);
+		if (stream->id < sid)
+			node =3D node->rb_right;
+		else if (stream->id > sid)
+			node =3D node->rb_left;
+		else
+			return stream->master;
+	}
+
+	return NULL;
+}
+
 /* IRQ and event handlers */
 static void arm_smmu_evtq_tasklet(void *dev)
 {
@@ -1026,8 +1047,8 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_ma=
ster *master,
 	if (!master->ats_enabled)
 		return 0;
=20
-	for (i =3D 0; i < master->num_sids; i++) {
-		cmd->atc.sid =3D master->sids[i];
+	for (i =3D 0; i < master->num_streams; i++) {
+		cmd->atc.sid =3D master->streams[i].id;
 		arm_smmu_cmdq_issue_cmd(master->smmu, cmd);
 	}
=20
@@ -1255,13 +1276,13 @@ static void arm_smmu_install_ste_for_dev(struct arm=
_smmu_master *master)
 	int i, j;
 	struct arm_smmu_device *smmu =3D master->smmu;
=20
-	for (i =3D 0; i < master->num_sids; ++i) {
-		u32 sid =3D master->sids[i];
+    for (i =3D 0; i < master->num_streams; ++i) {
+		u32 sid =3D master->streams[i].id;
 		__le64 *step =3D arm_smmu_get_step_for_sid(smmu, sid);
=20
 		/* Bridged PCI devices may end up with duplicated IDs */
 		for (j =3D 0; j < i; j++)
-			if (master->sids[j] =3D=3D sid)
+			if (master->streams[j].id =3D=3D sid)
 				break;
 		if (j < i)
 			continue;
@@ -1470,6 +1491,80 @@ static bool arm_smmu_sid_in_range(struct arm_smmu_de=
vice *smmu, u32 sid)
=20
 	return sid < limit;
 }
+
+static int arm_smmu_insert_master(struct arm_smmu_device *smmu,
+				  struct arm_smmu_master *master)
+{
+	int i;
+	int ret =3D 0;
+	struct arm_smmu_stream *new_stream, *cur_stream;
+	struct rb_node **new_node, *parent_node =3D NULL;
+	struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(master->dev);
+
+	master->streams =3D _xzalloc_array(sizeof(*master->streams), sizeof(void =
*),
+					fwspec->num_ids);
+	if (!master->streams)
+		return -ENOMEM;
+	master->num_streams =3D fwspec->num_ids;
+
+	mutex_lock(&smmu->streams_mutex);
+	for (i =3D 0; i < fwspec->num_ids; i++) {
+		u32 sid =3D fwspec->ids[i];
+
+		new_stream =3D &master->streams[i];
+		new_stream->id =3D sid;
+		new_stream->master =3D master;
+
+		/*
+		 * Check the SIDs are in range of the SMMU and our stream table
+		 */
+		if (!arm_smmu_sid_in_range(smmu, sid)) {
+			ret =3D -ERANGE;
+			break;
+		}
+
+		/* Ensure l2 strtab is initialised */
+		if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
+			ret =3D arm_smmu_init_l2_strtab(smmu, sid);
+			if (ret)
+				break;
+		}
+
+		/* Insert into SID tree */
+		new_node =3D &(smmu->streams.rb_node);
+		while (*new_node) {
+			cur_stream =3D rb_entry(*new_node, struct arm_smmu_stream,
+					      node);
+			parent_node =3D *new_node;
+			if (cur_stream->id > new_stream->id) {
+				new_node =3D &((*new_node)->rb_left);
+			} else if (cur_stream->id < new_stream->id) {
+				new_node =3D &((*new_node)->rb_right);
+			} else {
+				dev_warn(master->dev,
+					 "stream %u already in tree\n",
+					 cur_stream->id);
+				ret =3D -EINVAL;
+				break;
+			}
+		}
+		if (ret)
+			break;
+
+		rb_link_node(&new_stream->node, parent_node, new_node);
+		rb_insert_color(&new_stream->node, &smmu->streams);
+	}
+
+	if (ret) {
+		for (i--; i >=3D 0; i--)
+			rb_erase(&master->streams[i].node, &smmu->streams);
+		xfree(master->streams);
+	}
+	mutex_unlock(&smmu->streams_mutex);
+
+	return ret;
+}
+
 /* Forward declaration */
 static struct arm_smmu_device *arm_smmu_get_by_dev(const struct device *de=
v);
 static int arm_smmu_assign_dev(struct domain *d, u8 devfn, struct device *=
dev,
@@ -1479,7 +1574,7 @@ static int arm_smmu_deassign_dev(struct domain *d, ui=
nt8_t devfn,
=20
 static int arm_smmu_add_device(u8 devfn, struct device *dev)
 {
-	int i, ret;
+	int ret;
 	struct arm_smmu_device *smmu;
 	struct arm_smmu_master *master;
 	struct iommu_fwspec *fwspec;
@@ -1516,26 +1611,11 @@ static int arm_smmu_add_device(u8 devfn, struct dev=
ice *dev)
=20
 	master->dev =3D dev;
 	master->smmu =3D smmu;
-	master->sids =3D fwspec->ids;
-	master->num_sids =3D fwspec->num_ids;
 	dev_iommu_priv_set(dev, master);
=20
-	/* Check the SIDs are in range of the SMMU and our stream table */
-	for (i =3D 0; i < master->num_sids; i++) {
-		u32 sid =3D master->sids[i];
-
-		if (!arm_smmu_sid_in_range(smmu, sid)) {
-			ret =3D -ERANGE;
-			goto err_free_master;
-		}
-
-		/* Ensure l2 strtab is initialised */
-		if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) {
-			ret =3D arm_smmu_init_l2_strtab(smmu, sid);
-			if (ret)
-				goto err_free_master;
-		}
-	}
+	ret =3D arm_smmu_insert_master(smmu, master);
+	if (ret)
+		goto err_free_master;
=20
 	/*
 	 * Note that PASID must be enabled before, and disabled after ATS:
@@ -1777,6 +1857,9 @@ static int __init arm_smmu_init_structures(struct arm=
_smmu_device *smmu)
 {
 	int ret;
=20
+	mutex_init(&smmu->streams_mutex);
+	smmu->streams =3D RB_ROOT;
+
 	ret =3D arm_smmu_init_queues(smmu);
 	if (ret)
 		return ret;
diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthroug=
h/arm/smmu-v3.h
index f09048812c..fe651ca5a7 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.h
+++ b/xen/drivers/passthrough/arm/smmu-v3.h
@@ -636,6 +636,15 @@ struct arm_smmu_device {
 	struct tasklet		evtq_irq_tasklet;
 	struct tasklet		priq_irq_tasklet;
 	struct tasklet		combined_irq_tasklet;
+
+	struct rb_root		streams;
+	struct mutex		streams_mutex;
+};
+
+struct arm_smmu_stream {
+	u32							id;
+	struct arm_smmu_master		*master;
+	struct rb_node				node;
 };
=20
 /* SMMU private data for each master */
@@ -644,8 +653,8 @@ struct arm_smmu_master {
 	struct device			*dev;
 	struct arm_smmu_domain		*domain;
 	struct list_head		domain_head;
-	u32				*sids;
-	unsigned int			num_sids;
+	struct arm_smmu_stream		*streams;
+	unsigned int				num_streams;
 	bool				ats_enabled;
 };
=20
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Jan Beulich ,
	=?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Milan Djokic
	
Subject: [PATCH 04/20] xen/arm: vIOMMU: add generic vIOMMU framework
Thread-Topic: [PATCH 04/20] xen/arm: vIOMMU: add generic vIOMMU framework
Thread-Index: AQHcB7yc6FJdcKq17UOgpZ88dk+WBw==
Date: Thu, 7 Aug 2025 16:59:18 +0000
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 <87b001cfc0555192435967b32190f75783ffa746.1754580688.git.milan_djokic@epam.com>
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From: Rahul Singh 

This patch adds basic framework for vIOMMU.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/arch/arm/dom0less-build.c        |  2 +
 xen/arch/arm/domain.c                | 25 ++++++++++
 xen/arch/arm/domain_build.c          |  2 +
 xen/arch/arm/include/asm/viommu.h    | 70 ++++++++++++++++++++++++++++
 xen/drivers/passthrough/Kconfig      |  6 +++
 xen/drivers/passthrough/arm/Makefile |  1 +
 xen/drivers/passthrough/arm/viommu.c | 48 +++++++++++++++++++
 xen/include/public/arch-arm.h        |  4 ++
 8 files changed, 158 insertions(+)
 create mode 100644 xen/arch/arm/include/asm/viommu.h
 create mode 100644 xen/drivers/passthrough/arm/viommu.c

diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index c8d07213e2..1fa6df214b 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -22,6 +22,7 @@
=20
 #include 
 #include 
+#include 
 #include 
 #include 
=20
@@ -280,6 +281,7 @@ int __init arch_parse_dom0less_node(struct dt_device_no=
de *node,
     uint32_t val;
=20
     d_cfg->arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
+    d_cfg->arch.viommu_type =3D viommu_get_type();
     d_cfg->flags |=3D XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap;
=20
     if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) )
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 310c578909..a66f71da17 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
=20
 #include "vpci.h"
@@ -699,6 +700,21 @@ int arch_sanitise_domain_config(struct xen_domctl_crea=
tedomain *config)
         return -EINVAL;
     }
=20
+    if ( !(config->flags & XEN_DOMCTL_CDF_iommu) &&
+         config->arch.viommu_type !=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE )
+    {
+        dprintk(XENLOG_INFO,
+                "vIOMMU requested while iommu not enabled for domain\n");
+        return -EINVAL;
+    }
+
+    if ( config->arch.viommu_type !=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE )
+    {
+        dprintk(XENLOG_INFO,
+                "vIOMMU type requested not supported by the platform or Xe=
n\n");
+        return -EINVAL;
+    }
+
     return 0;
 }
=20
@@ -791,6 +807,9 @@ int arch_domain_create(struct domain *d,
     d->arch.sve_vl =3D config->arch.sve_vl;
 #endif
=20
+    if ( (rc =3D domain_viommu_init(d, config->arch.viommu_type)) !=3D 0 )
+        goto fail;
+
     return 0;
=20
 fail:
@@ -1038,6 +1057,7 @@ static int relinquish_memory(struct domain *d, struct=
 page_list_head *list)
 enum {
     PROG_pci =3D 1,
     PROG_tee,
+    PROG_viommu,
     PROG_xen,
     PROG_page,
     PROG_mapping,
@@ -1089,6 +1109,11 @@ int domain_relinquish_resources(struct domain *d)
         if (ret )
             return ret;
=20
+    PROGRESS(viommu):
+        ret =3D viommu_relinquish_resources(d);
+        if (ret )
+            return ret;
+
     PROGRESS(xen):
         ret =3D relinquish_memory(d, &d->xenpage_list);
         if ( ret )
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 463ae4474d..50e4f5fee4 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -34,6 +34,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
=20
 #include 
@@ -2057,6 +2058,7 @@ void __init create_dom0(void)
     dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS;
     dom0_cfg.arch.tee_type =3D tee_get_type();
     dom0_cfg.max_vcpus =3D dom0_max_vcpus();
+    dom0_cfg.arch.viommu_type =3D viommu_get_type();
=20
     if ( iommu_enabled )
         dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu;
diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/v=
iommu.h
new file mode 100644
index 0000000000..7cd3818a12
--- /dev/null
+++ b/xen/arch/arm/include/asm/viommu.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
+#ifndef __ARCH_ARM_VIOMMU_H__
+#define __ARCH_ARM_VIOMMU_H__
+
+#ifdef CONFIG_VIRTUAL_IOMMU
+
+#include 
+#include 
+#include 
+
+struct viommu_ops {
+    /*
+     * Called during domain construction if toolstack requests to enable
+     * vIOMMU support.
+     */
+    int (*domain_init)(struct domain *d);
+
+    /*
+     * Called during domain destruction to free resources used by vIOMMU.
+     */
+    int (*relinquish_resources)(struct domain *d);
+};
+
+struct viommu_desc {
+    /* vIOMMU domains init/free operations described above. */
+    const struct viommu_ops *ops;
+
+    /*
+     * ID of vIOMMU. Corresponds to xen_arch_domainconfig.viommu_type.
+     * Should be one of XEN_DOMCTL_CONFIG_VIOMMU_xxx
+     */
+    uint16_t viommu_type;
+};
+
+int domain_viommu_init(struct domain *d, uint16_t viommu_type);
+int viommu_relinquish_resources(struct domain *d);
+uint16_t viommu_get_type(void);
+
+#else
+
+static inline uint8_t viommu_get_type(void)
+{
+    return XEN_DOMCTL_CONFIG_VIOMMU_NONE;
+}
+
+static inline int domain_viommu_init(struct domain *d, uint16_t viommu_typ=
e)
+{
+    if ( likely(viommu_type =3D=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE) )
+        return 0;
+
+    return -ENODEV;
+}
+
+static inline int viommu_relinquish_resources(struct domain *d)
+{
+    return 0;
+}
+
+#endif /* CONFIG_VIRTUAL_IOMMU */
+
+#endif /* __ARCH_ARM_VIOMMU_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/drivers/passthrough/Kconfig b/xen/drivers/passthrough/Kcon=
fig
index b413c33a4c..fbd56eb990 100644
--- a/xen/drivers/passthrough/Kconfig
+++ b/xen/drivers/passthrough/Kconfig
@@ -35,6 +35,12 @@ config IPMMU_VMSA
 	  (H3 ES3.0, M3-W+, etc) or Gen4 SoCs which IPMMU hardware supports stage=
 2
 	  translation table format and is able to use CPU's P2M table as is.
=20
+config VIRTUAL_IOMMU
+	bool "Virtual IOMMU Support (UNSUPPORTED)" if UNSUPPORTED
+	default n
+	help
+	 Support virtual IOMMU infrastructure to implement vIOMMU.
+
 endif
=20
 config AMD_IOMMU
diff --git a/xen/drivers/passthrough/arm/Makefile b/xen/drivers/passthrough=
/arm/Makefile
index c5fb3b58a5..4cc54f3f4d 100644
--- a/xen/drivers/passthrough/arm/Makefile
+++ b/xen/drivers/passthrough/arm/Makefile
@@ -2,3 +2,4 @@ obj-y +=3D iommu.o iommu_helpers.o iommu_fwspec.o
 obj-$(CONFIG_ARM_SMMU) +=3D smmu.o
 obj-$(CONFIG_IPMMU_VMSA) +=3D ipmmu-vmsa.o
 obj-$(CONFIG_ARM_SMMU_V3) +=3D smmu-v3.o
+obj-$(CONFIG_VIRTUAL_IOMMU) +=3D viommu.o
diff --git a/xen/drivers/passthrough/arm/viommu.c b/xen/drivers/passthrough=
/arm/viommu.c
new file mode 100644
index 0000000000..7ab6061e34
--- /dev/null
+++ b/xen/drivers/passthrough/arm/viommu.c
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
+
+#include 
+#include 
+#include 
+
+#include 
+
+const struct viommu_desc __read_mostly *cur_viommu;
+
+int domain_viommu_init(struct domain *d, uint16_t viommu_type)
+{
+    if ( viommu_type =3D=3D XEN_DOMCTL_CONFIG_VIOMMU_NONE )
+        return 0;
+
+    if ( !cur_viommu )
+        return -ENODEV;
+
+    if ( cur_viommu->viommu_type !=3D viommu_type )
+        return -EINVAL;
+
+    return cur_viommu->ops->domain_init(d);
+}
+
+int viommu_relinquish_resources(struct domain *d)
+{
+    if ( !cur_viommu )
+        return 0;
+
+    return cur_viommu->ops->relinquish_resources(d);
+}
+
+uint16_t viommu_get_type(void)
+{
+    if ( !cur_viommu )
+        return XEN_DOMCTL_CONFIG_VIOMMU_NONE;
+
+    return cur_viommu->viommu_type;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index e2412a1747..0a155fe615 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -327,12 +327,16 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
 #define XEN_DOMCTL_CONFIG_TEE_OPTEE     1
 #define XEN_DOMCTL_CONFIG_TEE_FFA       2
=20
+#define XEN_DOMCTL_CONFIG_VIOMMU_NONE   0
+
 struct xen_arch_domainconfig {
     /* IN/OUT */
     uint8_t gic_version;
     /* IN - Contains SVE vector length divided by 128 */
     uint8_t sve_vl;
     /* IN */
+    uint8_t viommu_type;
+    /* IN */
     uint16_t tee_type;
     /* IN */
     uint32_t nr_spis;
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Milan Djokic 
Subject: [PATCH 14/20] xen/arm: vIOMMU: IOMMU device tree node for dom0
Thread-Topic: [PATCH 14/20] xen/arm: vIOMMU: IOMMU device tree node for dom0
Thread-Index: AQHcB7yjVZWSIfKg2EWj5KqbQYkZRQ==
Date: Thu, 7 Aug 2025 16:59:29 +0000
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From: Rahul Singh 

XEN will create an IOMMU device tree node in the device tree
to enable the dom0 to discover the virtual SMMUv3 during dom0 boot.
IOMMU device tree node will only be created when cmdline option viommu
is enabled.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/arch/arm/domain_build.c       | 94 +++++++++++++++++++++++++++++++
 xen/arch/arm/include/asm/viommu.h |  1 +
 2 files changed, 95 insertions(+)

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 9d2b0ea928..aa2b3bdfcc 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -1559,6 +1559,95 @@ int __init make_chosen_node(const struct kernel_info=
 *kinfo)
     return res;
 }
=20
+#ifdef CONFIG_VIRTUAL_IOMMU
+static int make_hwdom_viommu_node(const struct kernel_info *kinfo)
+{
+    uint32_t len;
+    int res;
+    char buf[24];
+    void *fdt =3D kinfo->fdt;
+    const void *prop =3D NULL;
+    const struct dt_device_node *iommu =3D NULL;
+    struct host_iommu *iommu_data;
+    gic_interrupt_t intr;
+
+    if ( list_empty(&host_iommu_list) )
+        return 0;
+
+    list_for_each_entry( iommu_data, &host_iommu_list, entry )
+    {
+        if ( iommu_data->hwdom_node_created )
+            return 0;
+
+        iommu =3D iommu_data->dt_node;
+
+        snprintf(buf, sizeof(buf), "iommu@%"PRIx64, iommu_data->addr);
+
+        res =3D fdt_begin_node(fdt, buf);
+        if ( res )
+            return res;
+
+        prop =3D dt_get_property(iommu, "compatible", &len);
+        if ( !prop )
+        {
+            res =3D -FDT_ERR_XEN(ENOENT);
+            return res;
+        }
+
+        res =3D fdt_property(fdt, "compatible", prop, len);
+        if ( res )
+            return res;
+
+        if ( iommu->phandle )
+        {
+            res =3D fdt_property_cell(fdt, "phandle", iommu->phandle);
+            if ( res )
+                return res;
+        }
+
+        /* Use the same reg regions as the IOMMU node in host DTB. */
+        prop =3D dt_get_property(iommu, "reg", &len);
+        if ( !prop )
+        {
+            printk(XENLOG_ERR "vIOMMU: Can't find IOMMU reg property.\n");
+            res =3D -FDT_ERR_XEN(ENOENT);
+            return res;
+        }
+
+        res =3D fdt_property(fdt, "reg", prop, len);
+        if ( res )
+            return res;
+
+        prop =3D dt_get_property(iommu, "#iommu-cells", &len);
+        if ( !prop )
+        {
+            res =3D -FDT_ERR_XEN(ENOENT);
+            return res;
+        }
+
+        res =3D fdt_property(fdt, "#iommu-cells", prop, len);
+        if ( res )
+            return res;
+
+        res =3D fdt_property_string(fdt, "interrupt-names", "combined");
+        if ( res )
+            return res;
+
+        set_interrupt(intr, iommu_data->irq, 0xf, DT_IRQ_TYPE_LEVEL_HIGH);
+
+        res =3D fdt_property_interrupts(kinfo, &intr, 1);
+        if ( res )
+            return res;
+
+        iommu_data->hwdom_node_created =3D true;
+
+        fdt_end_node(fdt);
+    }
+
+    return res;
+}
+#endif
+
 static int __init handle_node(struct domain *d, struct kernel_info *kinfo,
                               struct dt_device_node *node,
                               p2m_type_t p2mt)
@@ -1627,6 +1716,11 @@ static int __init handle_node(struct domain *d, stru=
ct kernel_info *kinfo,
     if ( dt_match_node(timer_matches, node) )
         return make_timer_node(kinfo);
=20
+#ifdef CONFIG_VIRTUAL_IOMMU
+    if ( device_get_class(node) =3D=3D DEVICE_IOMMU && is_viommu_enabled()=
 )
+        return make_hwdom_viommu_node(kinfo);
+#endif
+
     /* Skip nodes used by Xen */
     if ( dt_device_used_by(node) =3D=3D DOMID_XEN )
     {
diff --git a/xen/arch/arm/include/asm/viommu.h b/xen/arch/arm/include/asm/v=
iommu.h
index 4de4cceeda..e6018f435b 100644
--- a/xen/arch/arm/include/asm/viommu.h
+++ b/xen/arch/arm/include/asm/viommu.h
@@ -19,6 +19,7 @@ struct host_iommu {
     paddr_t addr;
     paddr_t size;
     uint32_t irq;
+    bool hwdom_node_created;
 };
=20
 struct viommu_ops {
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Andrew Cooper
	, Anthony PERARD , Jan
 Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Milan Djokic 
Subject: [PATCH 15/20] xen/arm: vsmmuv3: Emulated SMMUv3 device tree node for
 dom0less
Thread-Topic: [PATCH 15/20] xen/arm: vsmmuv3: Emulated SMMUv3 device tree node
 for dom0less
Thread-Index: AQHcB7ykWuFnTntxcE+YZDhqvaBxqA==
Date: Thu, 7 Aug 2025 16:59:30 +0000
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 <0be8cd7abe1c3b2fde6cd4a0004e443f14f99d92.1754580688.git.milan_djokic@epam.com>
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From: Rahul Singh 

XEN will create an Emulated SMMUv3 device tree node in the device tree
to enable the dom0less domains to discover the virtual SMMUv3 during
boot. Emulated SMMUv3 device tree node will only be created when cmdline
option vsmmuv3 is enabled.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/arch/arm/dom0less-build.c         | 53 +++++++++++++++++++++++++++
 xen/include/public/device_tree_defs.h |  1 +
 2 files changed, 54 insertions(+)

diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 1fa6df214b..1e526c10de 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -217,10 +217,63 @@ static int __init make_vpl011_uart_node(struct kernel=
_info *kinfo)
 }
 #endif
=20
+#ifdef CONFIG_VIRTUAL_ARM_SMMU_V3
+static int __init make_vsmmuv3_node(const struct kernel_info *kinfo)
+{
+    int res;
+    char buf[24];
+    __be32 reg[GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS];
+    __be32 *cells;
+    void *fdt =3D kinfo->fdt;
+
+    snprintf(buf, sizeof(buf), "iommu@%llx", GUEST_VSMMUV3_BASE);
+
+    res =3D fdt_begin_node(fdt, buf);
+    if ( res )
+        return res;
+
+    res =3D fdt_property_string(fdt, "compatible", "arm,smmu-v3");
+    if ( res )
+        return res;
+
+    /* Create reg property */
+    cells =3D ®[0];
+    dt_child_set_range(&cells, GUEST_ROOT_ADDRESS_CELLS, GUEST_ROOT_SIZE_C=
ELLS,
+                       GUEST_VSMMUV3_BASE, GUEST_VSMMUV3_SIZE);
+    res =3D fdt_property(fdt, "reg", reg,
+                       (GUEST_ROOT_ADDRESS_CELLS +
+                       GUEST_ROOT_SIZE_CELLS) * sizeof(*reg));
+    if ( res )
+        return res;
+
+    res =3D fdt_property_cell(fdt, "phandle", GUEST_PHANDLE_VSMMUV3);
+    if ( res )
+        return res;
+
+    res =3D fdt_property_cell(fdt, "#iommu-cells", 1);
+    if ( res )
+        return res;
+
+    res =3D fdt_end_node(fdt);
+
+    return res;
+}
+#endif
+
 int __init make_arch_nodes(struct kernel_info *kinfo)
 {
     int ret;
=20
+
+#ifdef CONFIG_VIRTUAL_ARM_SMMU_V3
+    if ( is_viommu_enabled() )
+    {
+        ret =3D make_vsmmuv3_node(kinfo);
+        if ( ret )
+            return -EINVAL;
+    }
+#endif
+
     ret =3D make_psci_node(kinfo->fdt);
     if ( ret )
         return -EINVAL;
diff --git a/xen/include/public/device_tree_defs.h b/xen/include/public/dev=
ice_tree_defs.h
index 9e80d0499d..7846a0425c 100644
--- a/xen/include/public/device_tree_defs.h
+++ b/xen/include/public/device_tree_defs.h
@@ -14,6 +14,7 @@
  */
 #define GUEST_PHANDLE_GIC (65000)
 #define GUEST_PHANDLE_IOMMU (GUEST_PHANDLE_GIC + 1)
+#define GUEST_PHANDLE_VSMMUV3 (GUEST_PHANDLE_IOMMU + 1)
=20
 #define GUEST_ROOT_ADDRESS_CELLS 2
 #define GUEST_ROOT_SIZE_CELLS 2
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Bertrand Marquis
	, Stefano Stabellini ,
	Julien Grall , Michal Orzel , Volodymyr
 Babchuk , Milan Djokic 
Subject: [PATCH 18/20] xen/arm: vsmmuv3: Add support to send stage-1 event to
 guest
Thread-Topic: [PATCH 18/20] xen/arm: vsmmuv3: Add support to send stage-1
 event to guest
Thread-Index: AQHcB7ylYt7xb8ek2UKgm42MUihrsg==
Date: Thu, 7 Aug 2025 16:59:33 +0000
Message-ID:
 <0ca83cfb5d360d80813fc4ebbd3b038a3195cdd1.1754580688.git.milan_djokic@epam.com>
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From: Rahul Singh 

Stage-1 translation is handled by guest, therefore stage-1 fault has to
be forwarded to guest.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/drivers/passthrough/arm/smmu-v3.c  | 48 ++++++++++++++++++++++++--
 xen/drivers/passthrough/arm/vsmmu-v3.c | 45 ++++++++++++++++++++++++
 xen/drivers/passthrough/arm/vsmmu-v3.h | 12 +++++++
 3 files changed, 103 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthroug=
h/arm/smmu-v3.c
index 91bf72d420..4ea3e90c11 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.c
+++ b/xen/drivers/passthrough/arm/smmu-v3.c
@@ -853,7 +853,6 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_devi=
ce *smmu, u32 sid)
 	return 0;
 }
=20
-__maybe_unused
 static struct arm_smmu_master *
 arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid)
 {
@@ -874,10 +873,51 @@ arm_smmu_find_master(struct arm_smmu_device *smmu, u3=
2 sid)
 	return NULL;
 }
=20
+static int arm_smmu_handle_evt(struct arm_smmu_device *smmu, u64 *evt)
+{
+	int ret;
+	struct arm_smmu_master *master;
+	u32 sid =3D FIELD_GET(EVTQ_0_SID, evt[0]);
+
+	switch (FIELD_GET(EVTQ_0_ID, evt[0])) {
+	case EVT_ID_TRANSLATION_FAULT:
+		break;
+	case EVT_ID_ADDR_SIZE_FAULT:
+		break;
+	case EVT_ID_ACCESS_FAULT:
+		break;
+	case EVT_ID_PERMISSION_FAULT:
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	/* Stage-2 event */
+	if (evt[1] & EVTQ_1_S2)
+		return -EFAULT;
+
+	mutex_lock(&smmu->streams_mutex);
+	master =3D arm_smmu_find_master(smmu, sid);
+	if (!master) {
+		ret =3D -EINVAL;
+		goto out_unlock;
+	}
+
+	ret =3D arm_vsmmu_handle_evt(master->domain->d, smmu->dev, evt);
+	if (ret) {
+		ret =3D -EINVAL;
+		goto out_unlock;
+	}
+
+out_unlock:
+	mutex_unlock(&smmu->streams_mutex);
+	return ret;
+}
+
 /* IRQ and event handlers */
 static void arm_smmu_evtq_tasklet(void *dev)
 {
-	int i;
+	int i, ret;
 	struct arm_smmu_device *smmu =3D dev;
 	struct arm_smmu_queue *q =3D &smmu->evtq.q;
 	struct arm_smmu_ll_queue *llq =3D &q->llq;
@@ -887,6 +927,10 @@ static void arm_smmu_evtq_tasklet(void *dev)
 		while (!queue_remove_raw(q, evt)) {
 			u8 id =3D FIELD_GET(EVTQ_0_ID, evt[0]);
=20
+			ret =3D arm_smmu_handle_evt(smmu, evt);
+			if (!ret)
+				continue;
+
 			dev_info(smmu->dev, "event 0x%02x received:\n", id);
 			for (i =3D 0; i < ARRAY_SIZE(evt); ++i)
 				dev_info(smmu->dev, "\t0x%016llx\n",
diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou=
gh/arm/vsmmu-v3.c
index a5b9700369..5d0dabd2b2 100644
--- a/xen/drivers/passthrough/arm/vsmmu-v3.c
+++ b/xen/drivers/passthrough/arm/vsmmu-v3.c
@@ -103,6 +103,7 @@ struct arm_vsmmu_queue {
 struct virt_smmu {
     struct      domain *d;
     struct      list_head viommu_list;
+    paddr_t     addr;
     uint8_t     sid_split;
     uint32_t    features;
     uint32_t    cr[3];
@@ -237,6 +238,49 @@ void arm_vsmmu_send_event(struct virt_smmu *smmu,
     return;
 }
=20
+static struct virt_smmu *vsmmuv3_find_by_addr(struct domain *d, paddr_t pa=
ddr)
+{
+    struct virt_smmu *smmu;
+
+    list_for_each_entry( smmu, &d->arch.viommu_list, viommu_list )
+    {
+        if ( smmu->addr =3D=3D paddr )
+            return smmu;
+    }
+
+    return NULL;
+}
+
+int arm_vsmmu_handle_evt(struct domain *d, struct device *dev, uint64_t *e=
vt)
+{
+    int ret;
+    struct virt_smmu *smmu;
+
+    if ( is_hardware_domain(d) )
+    {
+        paddr_t paddr;
+        /* Base address */
+        ret =3D dt_device_get_address(dev_to_dt(dev), 0, &paddr, NULL);
+        if ( ret )
+            return -EINVAL;
+
+        smmu =3D vsmmuv3_find_by_addr(d, paddr);
+        if ( !smmu )
+            return -ENODEV;
+    }
+    else
+    {
+        smmu =3D list_entry(d->arch.viommu_list.next,
+                          struct virt_smmu, viommu_list);
+    }
+
+    ret =3D arm_vsmmu_write_evtq(smmu, evt);
+    if ( ret )
+        arm_vsmmu_inject_irq(smmu, true, GERROR_EVTQ_ABT_ERR);
+
+    return 0;
+}
+
 static int arm_vsmmu_find_ste(struct virt_smmu *smmu, uint32_t sid,
                               uint64_t *ste)
 {
@@ -742,6 +786,7 @@ static int vsmmuv3_init_single(struct domain *d, paddr_=
t addr,
=20
     smmu->d =3D d;
     smmu->virq =3D virq;
+    smmu->addr =3D addr;
     smmu->cmdq.q_base =3D FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_CMDQS);
     smmu->cmdq.ent_size =3D CMDQ_ENT_DWORDS * DWORDS_BYTES;
     smmu->evtq.q_base =3D FIELD_PREP(Q_BASE_LOG2SIZE, SMMU_EVTQS);
diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.h b/xen/drivers/passthrou=
gh/arm/vsmmu-v3.h
index e11f85b431..c7bfd3fb59 100644
--- a/xen/drivers/passthrough/arm/vsmmu-v3.h
+++ b/xen/drivers/passthrough/arm/vsmmu-v3.h
@@ -8,6 +8,12 @@
=20
 void vsmmuv3_set_type(void);
=20
+static inline int arm_vsmmu_handle_evt(struct domain *d,
+                                       struct device *dev, uint64_t *evt)
+{
+    return -EINVAL;
+}
+
 #else
=20
 static inline void vsmmuv3_set_type(void)
@@ -15,6 +21,12 @@ static inline void vsmmuv3_set_type(void)
     return;
 }
=20
+static inline int arm_vsmmu_handle_evt(struct domain *d,
+                                       struct device *dev, uint64_t *evt)
+{
+    return -EINVAL;
+}
+
 #endif /* CONFIG_VIRTUAL_ARM_SMMU_V3 */
=20
 #endif /* __ARCH_ARM_VSMMU_V3_H__ */
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Anthony PERARD
	, Juergen Gross , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel ,
	Volodymyr Babchuk , Milan Djokic
	
Subject: [PATCH 17/20] xen/arm: vsmmuv3: Alloc virq for virtual SMMUv3
Thread-Topic: [PATCH 17/20] xen/arm: vsmmuv3: Alloc virq for virtual SMMUv3
Thread-Index: AQHcB7yl9f0v0YO6DkW2QyqxB5OyfA==
Date: Thu, 7 Aug 2025 16:59:32 +0000
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From: Rahul Singh 

Alloc and reserve virq for event queue and global error to send event to
guests. Also Modify the libxl to accomadate the new define virq.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 tools/libs/light/libxl_arm.c           | 28 ++++++++++++++++++++++++--
 xen/arch/arm/dom0less-build.c          | 17 ++++++++++++++++
 xen/drivers/passthrough/arm/vsmmu-v3.c | 13 ++++++++++++
 3 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c
index c8255d8d4f..55beda8c0e 100644
--- a/tools/libs/light/libxl_arm.c
+++ b/tools/libs/light/libxl_arm.c
@@ -86,8 +86,8 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
 {
     uint32_t nr_spis =3D 0, cfg_nr_spis =3D d_config->b_info.arch_arm.nr_s=
pis;
     unsigned int i;
-    uint32_t vuart_irq, virtio_irq =3D 0;
-    bool vuart_enabled =3D false, virtio_enabled =3D false;
+    uint32_t vuart_irq, virtio_irq =3D 0, vsmmu_irq =3D 0;
+    bool vuart_enabled =3D false, virtio_enabled =3D false, vsmmu_enabled =
=3D false;
     uint64_t virtio_mmio_base =3D GUEST_VIRTIO_MMIO_BASE;
     uint32_t virtio_mmio_irq =3D GUEST_VIRTIO_MMIO_SPI_FIRST;
     int rc;
@@ -102,6 +102,16 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
         vuart_enabled =3D true;
     }
=20
+    /*
+     * If smmuv3 viommu is enabled then increment the nr_spis to allow all=
ocation
+     * of SPI VIRQ for VSMMU.
+     */
+    if (d_config->b_info.arch_arm.viommu_type =3D=3D LIBXL_VIOMMU_TYPE_SMM=
UV3) {
+        nr_spis +=3D (GUEST_VSMMU_SPI - 32) + 1;
+        vsmmu_irq =3D GUEST_VSMMU_SPI;
+        vsmmu_enabled =3D true;
+    }
+
     for (i =3D 0; i < d_config->num_disks; i++) {
         libxl_device_disk *disk =3D &d_config->disks[i];
=20
@@ -170,6 +180,11 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
             return ERROR_FAIL;
         }
=20
+        if (vsmmu_enabled && irq =3D=3D vsmmu_irq) {
+            LOG(ERROR, "Physical IRQ %u conflicting with vSMMUv3 SPI\n", i=
rq);
+            return ERROR_FAIL;
+        }
+
         if (irq < 32)
             continue;
=20
@@ -893,6 +908,7 @@ static int make_vsmmuv3_node(libxl__gc *gc, void *fdt,
 {
     int res;
     const char *name =3D GCSPRINTF("iommu@%llx", GUEST_VSMMUV3_BASE);
+    gic_interrupt intr;
=20
     res =3D fdt_begin_node(fdt, name);
     if (res) return res;
@@ -911,6 +927,14 @@ static int make_vsmmuv3_node(libxl__gc *gc, void *fdt,
     res =3D fdt_property_cell(fdt, "#iommu-cells", 1);
     if (res) return res;
=20
+    res =3D fdt_property_string(fdt, "interrupt-names", "combined");
+    if (res) return res;
+
+    set_interrupt(intr, GUEST_VSMMU_SPI, 0xf, DT_IRQ_TYPE_LEVEL_HIGH);
+
+    res =3D fdt_property_interrupts(gc, fdt, &intr, 1);
+    if (res) return res;
+
     res =3D fdt_end_node(fdt);
     if (res) return res;
=20
diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 1e526c10de..66ef3dfa1f 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -224,6 +224,7 @@ static int __init make_vsmmuv3_node(const struct kernel=
_info *kinfo)
     char buf[24];
     __be32 reg[GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS];
     __be32 *cells;
+    gic_interrupt_t intr;
     void *fdt =3D kinfo->fdt;
=20
     snprintf(buf, sizeof(buf), "iommu@%llx", GUEST_VSMMUV3_BASE);
@@ -254,6 +255,22 @@ static int __init make_vsmmuv3_node(const struct kerne=
l_info *kinfo)
     if ( res )
         return res;
=20
+    res =3D fdt_property_string(fdt, "interrupt-names", "combined");
+    if ( res )
+        return res;
+
+    set_interrupt(intr, GUEST_VSMMU_SPI, 0xf, DT_IRQ_TYPE_LEVEL_HIGH);
+
+    res =3D fdt_property(kinfo->fdt, "interrupts",
+                       intr, sizeof(intr));
+    if ( res )
+        return res;
+
+    res =3D fdt_property_cell(kinfo->fdt, "interrupt-parent",
+                            kinfo->phandle_intc);
+    if ( res )
+        return res;
+
     res =3D fdt_end_node(fdt);
=20
     return res;
diff --git a/xen/drivers/passthrough/arm/vsmmu-v3.c b/xen/drivers/passthrou=
gh/arm/vsmmu-v3.c
index 7a6c18df53..a5b9700369 100644
--- a/xen/drivers/passthrough/arm/vsmmu-v3.c
+++ b/xen/drivers/passthrough/arm/vsmmu-v3.c
@@ -733,6 +733,7 @@ static const struct mmio_handler_ops vsmmuv3_mmio_handl=
er =3D {
 static int vsmmuv3_init_single(struct domain *d, paddr_t addr,
                                paddr_t size, uint32_t virq)
 {
+    int ret;
     struct virt_smmu *smmu;
=20
     smmu =3D xzalloc(struct virt_smmu);
@@ -748,12 +749,24 @@ static int vsmmuv3_init_single(struct domain *d, padd=
r_t addr,
=20
     spin_lock_init(&smmu->cmd_queue_lock);
=20
+    ret =3D vgic_reserve_virq(d, virq);
+    if ( !ret )
+    {
+        ret =3D -EINVAL;
+        goto out;
+    }
+
     register_mmio_handler(d, &vsmmuv3_mmio_handler, addr, size, smmu);
=20
     /* Register the vIOMMU to be able to clean it up later. */
     list_add_tail(&smmu->viommu_list, &d->arch.viommu_list);
=20
     return 0;
+
+out:
+    xfree(smmu);
+    vgic_free_virq(d, virq);
+    return ret;
 }
=20
 int domain_vsmmuv3_init(struct domain *d)
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Anthony PERARD
	, Juergen Gross , Milan Djokic
	
Subject: [PATCH 16/20] arm/libxl: vsmmuv3: Emulated SMMUv3 device tree node in
 libxl
Thread-Topic: [PATCH 16/20] arm/libxl: vsmmuv3: Emulated SMMUv3 device tree
 node in libxl
Thread-Index: AQHcB7yktmBVQsC5I0iGGX/Mv/uKhg==
Date: Thu, 7 Aug 2025 16:59:31 +0000
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From: Rahul Singh 

libxl will create an Emulated SMMUv3 device tree node in the device
tree to enable the guest OS to discover the virtual SMMUv3 during guest
boot.

Emulated SMMUv3 device tree node will only be created when
"viommu=3Dsmmuv3" is set in xl domain configuration.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 tools/libs/light/libxl_arm.c | 37 ++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c
index 44b7bcd672..c8255d8d4f 100644
--- a/tools/libs/light/libxl_arm.c
+++ b/tools/libs/light/libxl_arm.c
@@ -887,6 +887,36 @@ static int make_vpl011_uart_node(libxl__gc *gc, void *=
fdt,
     return 0;
 }
=20
+static int make_vsmmuv3_node(libxl__gc *gc, void *fdt,
+                             const struct arch_info *ainfo,
+                             struct xc_dom_image *dom)
+{
+    int res;
+    const char *name =3D GCSPRINTF("iommu@%llx", GUEST_VSMMUV3_BASE);
+
+    res =3D fdt_begin_node(fdt, name);
+    if (res) return res;
+
+    res =3D fdt_property_compat(gc, fdt, 1, "arm,smmu-v3");
+    if (res) return res;
+
+    res =3D fdt_property_regs(gc, fdt, GUEST_ROOT_ADDRESS_CELLS,
+                            GUEST_ROOT_SIZE_CELLS, 1, GUEST_VSMMUV3_BASE,
+                            GUEST_VSMMUV3_SIZE);
+    if (res) return res;
+
+    res =3D fdt_property_cell(fdt, "phandle", GUEST_PHANDLE_VSMMUV3);
+    if (res) return res;
+
+    res =3D fdt_property_cell(fdt, "#iommu-cells", 1);
+    if (res) return res;
+
+    res =3D fdt_end_node(fdt);
+    if (res) return res;
+
+    return 0;
+}
+
 static int make_vpci_node(libxl__gc *gc, void *fdt,
                           const struct arch_info *ainfo,
                           struct xc_dom_image *dom)
@@ -928,6 +958,10 @@ static int make_vpci_node(libxl__gc *gc, void *fdt,
         GUEST_VPCI_PREFETCH_MEM_SIZE);
     if (res) return res;
=20
+    res =3D fdt_property_values(gc, fdt, "iommu-map", 4, 0,
+                              GUEST_PHANDLE_VSMMUV3, 0, 0x10000);
+    if (res) return res;
+
     res =3D fdt_end_node(fdt);
     if (res) return res;
=20
@@ -1394,6 +1428,9 @@ next_resize:
         if (d_config->num_pcidevs)
             FDT( make_vpci_node(gc, fdt, ainfo, dom) );
=20
+        if (info->arch_arm.viommu_type =3D=3D LIBXL_VIOMMU_TYPE_SMMUV3)
+            FDT( make_vsmmuv3_node(gc, fdt, ainfo, dom) );
+
         for (i =3D 0; i < d_config->num_disks; i++) {
             libxl_device_disk *disk =3D &d_config->disks[i];
=20
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Anthony PERARD
	, Juergen Gross , Milan Djokic
	
Subject: [PATCH 19/20] libxl/arm: vIOMMU: Modify the partial device tree for
 iommus
Thread-Topic: [PATCH 19/20] libxl/arm: vIOMMU: Modify the partial device tree
 for iommus
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Date: Thu, 7 Aug 2025 16:59:34 +0000
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From: Rahul Singh 

To configure IOMMU in guest for passthrough devices, user will need to
copy the unmodified "iommus" property from host device tree to partial
device tree. To enable the dom0 linux kernel to confiure the IOMMU
correctly replace the phandle in partial device tree with virtual
IOMMU phandle when "iommus" property is set.

Signed-off-by: Rahul Singh 
Singed-off-by: Milan Djokic 
---
 tools/libs/light/libxl_arm.c | 47 +++++++++++++++++++++++++++++++++++-
 1 file changed, 46 insertions(+), 1 deletion(-)

diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c
index 55beda8c0e..d99f49b831 100644
--- a/tools/libs/light/libxl_arm.c
+++ b/tools/libs/light/libxl_arm.c
@@ -1312,6 +1312,41 @@ static int copy_partial_fdt(libxl__gc *gc, void *fdt=
, void *pfdt)
     return 0;
 }
=20
+static int modify_partial_fdt(libxl__gc *gc, void *pfdt)
+{
+    int nodeoff, proplen, i, r;
+    const fdt32_t *prop;
+    fdt32_t *prop_c;
+
+    nodeoff =3D fdt_path_offset(pfdt, "/passthrough");
+    if (nodeoff < 0)
+        return nodeoff;
+
+    for (nodeoff =3D fdt_first_subnode(pfdt, nodeoff);
+         nodeoff >=3D 0;
+         nodeoff =3D fdt_next_subnode(pfdt, nodeoff)) {
+
+        prop =3D fdt_getprop(pfdt, nodeoff, "iommus", &proplen);
+        if (!prop)
+            continue;
+
+        prop_c =3D libxl__zalloc(gc, proplen);
+
+        for (i =3D 0; i < proplen / 8; ++i) {
+            prop_c[i * 2] =3D cpu_to_fdt32(GUEST_PHANDLE_VSMMUV3);
+            prop_c[i * 2 + 1] =3D prop[i * 2 + 1];
+        }
+
+        r =3D fdt_setprop(pfdt, nodeoff, "iommus", prop_c, proplen);
+        if (r) {
+            LOG(ERROR, "Can't set the iommus property in partial FDT");
+            return r;
+        }
+    }
+
+    return 0;
+}
+
 #else
=20
 static int check_partial_fdt(libxl__gc *gc, void *fdt, size_t size)
@@ -1330,6 +1365,13 @@ static int copy_partial_fdt(libxl__gc *gc, void *fdt=
, void *pfdt)
     return -FDT_ERR_INTERNAL;
 }
=20
+static int modify_partial_fdt(libxl__gc *gc, void *pfdt)
+{
+    LOG(ERROR, "partial device tree not supported");
+
+    return ERROR_FAIL;
+}
+
 #endif /* ENABLE_PARTIAL_DEVICE_TREE */
=20
 #define FDT_MAX_SIZE (1<<20)
@@ -1452,8 +1494,11 @@ next_resize:
         if (d_config->num_pcidevs)
             FDT( make_vpci_node(gc, fdt, ainfo, dom) );
=20
-        if (info->arch_arm.viommu_type =3D=3D LIBXL_VIOMMU_TYPE_SMMUV3)
+        if (info->arch_arm.viommu_type =3D=3D LIBXL_VIOMMU_TYPE_SMMUV3) {
             FDT( make_vsmmuv3_node(gc, fdt, ainfo, dom) );
+            if (pfdt)
+                FDT( modify_partial_fdt(gc, pfdt) );
+        }
=20
         for (i =3D 0; i < d_config->num_disks; i++) {
             libxl_device_disk *disk =3D &d_config->disks[i];
--=20
2.43.0


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From: Milan Djokic 
To: "xen-devel@lists.xenproject.org" 
CC: Rahul Singh , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Milan Djokic
	
Subject: [PATCH 20/20] xen/arm: vIOMMU: Modify the partial device tree for
 dom0less
Thread-Topic: [PATCH 20/20] xen/arm: vIOMMU: Modify the partial device tree
 for dom0less
Thread-Index: AQHcB7ynr3/KXhUzEkK9AiVwODSe+g==
Date: Thu, 7 Aug 2025 16:59:35 +0000
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From: Rahul Singh 

To configure IOMMU in guest for passthrough devices, user will need to
copy the unmodified "iommus" property from host device tree to partial
device tree. To enable the dom0 linux kernel to confiure the IOMMU
correctly replace the phandle in partial device tree with virtual
IOMMU phandle when "iommus" property is set.

Signed-off-by: Rahul Singh 
Signed-off-by: Milan Djokic 
---
 xen/common/device-tree/dom0less-build.c | 31 ++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tr=
ee/dom0less-build.c
index 6bb038111d..3cfffa6581 100644
--- a/xen/common/device-tree/dom0less-build.c
+++ b/xen/common/device-tree/dom0less-build.c
@@ -314,7 +314,35 @@ static int __init handle_prop_pfdt(struct kernel_info =
*kinfo,
     return ( propoff !=3D -FDT_ERR_NOTFOUND ) ? propoff : 0;
 }
=20
-static int __init scan_pfdt_node(struct kernel_info *kinfo, const void *pf=
dt,
+static void modify_pfdt_node(void *pfdt, int nodeoff)
+{
+    int proplen, i, rc;
+    const fdt32_t *prop;
+    fdt32_t *prop_c;
+
+    prop =3D fdt_getprop(pfdt, nodeoff, "iommus", &proplen);
+    if ( !prop )
+        return;
+
+    prop_c =3D xzalloc_bytes(proplen);
+
+    for ( i =3D 0; i < proplen / 8; ++i )
+    {
+        prop_c[i * 2] =3D cpu_to_fdt32(GUEST_PHANDLE_VSMMUV3);
+        prop_c[i * 2 + 1] =3D prop[i * 2 + 1];
+    }
+
+    rc =3D fdt_setprop(pfdt, nodeoff, "iommus", prop_c, proplen);
+    if ( rc )
+    {
+        dprintk(XENLOG_ERR, "Can't set the iommus property in partial FDT"=
);
+        return;
+    }
+
+    return;
+}
+
+static int __init scan_pfdt_node(struct kernel_info *kinfo, void *pfdt,
                                  int nodeoff,
                                  uint32_t address_cells, uint32_t size_cel=
ls,
                                  bool scan_passthrough_prop)
@@ -340,6 +368,7 @@ static int __init scan_pfdt_node(struct kernel_info *ki=
nfo, const void *pfdt,
     node_next =3D fdt_first_subnode(pfdt, nodeoff);
     while ( node_next > 0 )
     {
+        modify_pfdt_node(pfdt, node_next);
         rc =3D scan_pfdt_node(kinfo, pfdt, node_next, address_cells, size_=
cells,
                             scan_passthrough_prop);
         if ( rc )
--=20
2.43.0


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Date: Thu, 07 Aug 2025 18:49:28 +0000
To: =?utf-8?Q?Roger_Pau_Monn=C3=A9?= 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 5/8] emul/vuart-ns16550: introduce NS16550-compatible UART emulator (x86)
Message-ID: 
In-Reply-To: 
References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-6-dmukhin@ford.com> 
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On Wed, Aug 06, 2025 at 05:06:24PM +0200, Roger Pau Monn=C3=A9 wrote:
[..]
> > @@ -0,0 +1,1009 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * NS16550-compatible UART Emulator.
> > + *
> > + * See:
> > + * - Serial and UART Tutorial:
> > + *     https://download.freebsd.org/doc/en/articles/serial-uart/serial=
-uart_en.pdf
> > + * - UART w/ 16 byte FIFO:
> > + *     https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
> > + * - UART w/ 64 byte FIFO:
> > + *     https://www.ti.com/lit/ds/symlink/tl16c750.pdf
> > + *
> > + * Limitations:
> > + * - Only x86;
> > + * - Only HVM domains support (build-time), PVH domains are not suppor=
ted yet;
> > + * - Only legacy COM{1,2,3,4} resources via Kconfig, custom I/O ports/=
IRQs
> > + *   are not supported;
> > + * - Only Xen console as a backend, no inter-domain communication (sim=
ilar to
> > + *   vpl011 on Arm);
> > + * - Only 8n1 emulation (8-bit data, no parity, 1 stop bit);
> > + * - No toolstack integration;
> > + * - No baud rate emulation (reports 115200 baud to the guest OS);
> > + * - No FIFO-less mode emulation;
> > + * - No RX FIFO interrupt moderation (FCR) emulation;
> > + * - No integration w/ VM snapshotting (HVM_REGISTER_SAVE_RESTORE() an=
d
> > + *   friends);
> > + * - No ISA IRQ sharing allowed;
> > + * - No MMIO-based UART emulation.
>=20
> Listing the limitations here might not be the beast approach, this is
> likely to get out of sync as it's too far away from the code
> implementation.
>=20
> If anything those comments want to be closer together to where the
> feature would otherwise be implemented.

I wanted to have some rough overview of the emulation capabilities in one
place so it is easy to get a grasp of how emulator can be used.

But I agree that can get out of hand if not maintained; I plan to maintain
that code.

>=20
> > + */
> > +
> > +#define pr_prefix               "ns16550"
> > +#define pr_fmt(fmt)             pr_prefix ": " fmt
> > +#define pr_log_level            CONFIG_VUART_NS16550_LOG_LEVEL
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +
> > +#define pr_err(fmt, args...) do { \
> > +    gprintk(KERN_ERR, pr_fmt(fmt), ## args); \
> > +} while (0)
> > +
> > +#define pr_warn(fmt, args...) do { \
> > +    if ( pr_log_level >=3D 1) \
> > +        gprintk(KERN_WARNING, pr_fmt(fmt), ## args); \
> > +} while (0)
> > +
> > +#define pr_info(fmt, args...) do { \
> > +    if ( pr_log_level >=3D 2 ) \
> > +        gprintk(KERN_INFO, pr_fmt(fmt), ## args); \
> > +} while (0)
> > +
> > +#define pr_debug(fmt, args...) do { \
> > +    if ( pr_log_level >=3D 3 ) \
> > +        gprintk(KERN_DEBUG, pr_fmt(fmt), ## args); \
> > +} while (0)
>=20
> We would use the pr_* set of logging functions for code imported from
> Linux, but for Xen code we would directly use the gprintk() functions
> rather than wrap them as you do.

Oh, I see, pr_ is a "reserved namespace".

I will rename these to ns16550_ since those are extremely helpful for
debugging.

>=20
> > +
> > +#if defined(CONFIG_VUART_NS16550_PC_COM1)
> > +#define X86_PC_UART_IDX         0
> > +#elif defined(CONFIG_VUART_NS16550_PC_COM2)
> > +#define X86_PC_UART_IDX         1
> > +#elif defined(CONFIG_VUART_NS16550_PC_COM3)
> > +#define X86_PC_UART_IDX         2
> > +#elif defined(CONFIG_VUART_NS16550_PC_COM4)
> > +#define X86_PC_UART_IDX         3
> > +#else
> > +#error "Unsupported I/O port"
> > +#endif
> > +
> > +#ifdef CONFIG_VUART_NS16550_DEBUG
> > +#define guest_prefix            "FROM GUEST "
> > +#else
> > +#define guest_prefix            ""
> > +#endif
> > +
> > +/*
> > + * Number of supported registers in the UART.
> > + */
> > +#define NS16550_REGS_NUM        ( UART_SCR + 1 )
>=20
> Extra spaces around parentheses? (here and below)

Ack.

>=20
> > +
> > +/*
> > + * Number of emulated registers.
> > + *
> > + * - Emulated registers [0..NS16550_REGS_NUM] are R/W registers for DL=
AB=3D0.
> > + * - DLAB=3D1, R/W, DLL            =3D NS16550_REGS_NUM + 0
> > + * - DLAB=3D1, R/W, DLM            =3D NS16550_REGS_NUM + 1
> > + * -         R/O, IIR (IIR_THR)  =3D NS16550_REGS_NUM + 2
> > + */
> > +#define NS16550_EMU_REGS_NUM    ( NS16550_REGS_NUM + 3 )
> > +
> > +/*
> > + * Virtual NS16550 device state.
> > + */
> > +struct vuart_ns16550 {
> > +    struct xencons_interface cons;      /* Emulated RX/TX FIFOs */
> > +    uint8_t regs[NS16550_EMU_REGS_NUM]; /* Emulated registers */
> > +    unsigned int irq;                   /* Emulated IRQ# */
> > +    uint64_t io_addr;                   /* Emulated I/O region base ad=
dress */
> > +    uint64_t io_size;                   /* Emulated I/O region size */
> > +    const char *name;                   /* Device name */
> > +    struct domain *owner;               /* Owner domain */
> > +    spinlock_t lock;                    /* Protection */
> > +};
> > +
> > +/*
> > + * Virtual device description.
> > + */
> > +struct virtdev_desc {
> > +    const char *name;
> > +    const struct resource *res;
> > +};
> > +
> > +/*
> > + * Legacy IBM PC NS16550 resources.
> > + * There are only 4 I/O port ranges, hardcoding all of them here.
> > + */
> > +static const struct virtdev_desc x86_pc_uarts[4] =3D {
> > +    [0] =3D {
>=20
> You don't need the explicit array indexes?

Muscle memory; I will nuke that huge static array in v5.

>=20
> > +        .name =3D "COM1",
> > +        .res =3D (const struct resource[]){
> > +            { .type =3D IORESOURCE_IO,  .addr =3D 0x3f8, .size =3D NS1=
6550_REGS_NUM },
> > +            { .type =3D IORESOURCE_IRQ, .addr =3D 4,     .size =3D 1 }=
,
> > +            { .type =3D IORESOURCE_UNKNOWN },
> > +        },
> > +    },
> > +    [1] =3D {
> > +        .name =3D "COM2",
> > +        .res =3D (const struct resource[]){
> > +            { .type =3D IORESOURCE_IO,  .addr =3D 0x2f8, .size =3D NS1=
6550_REGS_NUM },
> > +            { .type =3D IORESOURCE_IRQ, .addr =3D 3,     .size =3D 1 }=
,
> > +            { .type =3D IORESOURCE_UNKNOWN },
> > +        },
> > +    },
> > +    [2] =3D {
> > +        .name =3D "COM3",
> > +        .res =3D (const struct resource[]){
> > +            { .type =3D IORESOURCE_IO,  .addr =3D 0x3e8, .size =3D NS1=
6550_REGS_NUM },
> > +            { .type =3D IORESOURCE_IRQ, .addr =3D 4,     .size =3D 1 }=
,
> > +            { .type =3D IORESOURCE_UNKNOWN },
> > +        },
> > +    },
> > +    [3] =3D {
> > +        .name =3D "COM4",
> > +        .res =3D (const struct resource[]){
> > +            { .type =3D IORESOURCE_IO,  .addr =3D 0x2e8, .size =3D NS1=
6550_REGS_NUM },
> > +            { .type =3D IORESOURCE_IRQ, .addr =3D 3,     .size =3D 1 }=
,
> > +            { .type =3D IORESOURCE_UNKNOWN },
> > +        },
> > +    },
> > +};
[..]
> > diff --git a/xen/include/public/arch-x86/xen.h b/xen/include/public/arc=
h-x86/xen.h
> > index fc2487986642..f905e1252c70 100644
> > --- a/xen/include/public/arch-x86/xen.h
> > +++ b/xen/include/public/arch-x86/xen.h
> > @@ -283,13 +283,15 @@ struct xen_arch_domainconfig {
> >  #define XEN_X86_EMU_USE_PIRQ        (1U<<_XEN_X86_EMU_USE_PIRQ)
> >  #define _XEN_X86_EMU_VPCI           10
> >  #define XEN_X86_EMU_VPCI            (1U<<_XEN_X86_EMU_VPCI)
> > +#define _XEN_X86_EMU_NS16550        11
> > +#define XEN_X86_EMU_NS16550         (1U<<_XEN_X86_EMU_NS16550)
> >
> >  #define XEN_X86_EMU_ALL             (XEN_X86_EMU_LAPIC | XEN_X86_EMU_H=
PET |  \
> >                                       XEN_X86_EMU_PM | XEN_X86_EMU_RTC =
|      \
> >                                       XEN_X86_EMU_IOAPIC | XEN_X86_EMU_=
PIC |  \
> >                                       XEN_X86_EMU_VGA | XEN_X86_EMU_IOM=
MU |   \
> >                                       XEN_X86_EMU_PIT | XEN_X86_EMU_USE=
_PIRQ |\
> > -                                     XEN_X86_EMU_VPCI)
> > +                                     XEN_X86_EMU_VPCI | XEN_X86_EMU_NS=
16550)
>=20
> libxl also consumes XEN_X86_EMU_ALL, and with the proposed change here
> it will create all HVM domains with XEN_X86_EMU_NS16550, which I don't
> think it's indented?
>=20
> Overall I agree for Jan it would be better if this patch could be
> split into somehow smaller units.  Is this something feasible?  We
> don't want a patch for each register handle, but maybe you cna somehow
> grup those into functional sections, so that patches can be < 250
> lines?
>=20
> Maybe you have already considered this approach and it wasn't
> feasible?

There __were__ pretty comprehensive reviews of this very emulator code
in the past without raising such concern (and this is v4).

Just in case, the most comprehensive review was this one (thanks Roger!):
  https://lore.kernel.org/xen-devel/Z1wd4iAmVzv1ISPZ@macbook.local/



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Date: Thu, 07 Aug 2025 18:57:23 +0000
To: =?utf-8?Q?Roger_Pau_Monn=C3=A9?= 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 3/8] x86/domain: allocate d->{iomem,irq}_caps before arch-specific initialization
Message-ID: 
In-Reply-To: 
References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-4-dmukhin@ford.com> 
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On Wed, Aug 06, 2025 at 04:37:23PM +0200, Roger Pau Monn=C3=A9 wrote:
> On Thu, Jul 31, 2025 at 07:21:54PM +0000, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Move IRQ/IOMEM rangesets allocation before arch_domain_create().
> >
> > That guarantees that arch-specific code could access those rangesets to
> > register traps for emulation.
> >
> > It is necessary for those emulators registering trap handlers and ensur=
ing
> > that emulated IRQs are not shared with the physical IRQs.
> >
> > Move dom0_setup_permissions() call right after I/O rangesets are alloca=
ted.
> >
> > Move pvh_setup_mmcfg() inside dom0_setup_permissions() close to the pla=
ce
> > where MMCFG ranges are initialized.
>=20
> I'm a bit puzzled by this, you don't need I/O permission to setup
> traps.  You can setup traps everywhere, the I/O rangesets control
> whether a domain can access the physical resource, not whether
> accesses can be emulated.

I do not want to setup traps if there's physical I/O range owned by the sam=
e
domain already. Emulator will report a misconfiguration in this case.

>=20
> The dependency between MMCFG registration (pvh_setup_mmcfg()) and
> calling dom0_setup_permissions() is because the later consumes the
> MMCFG ranges added by the former to mark them as not accessible by
> a PVH dom0.
>=20
> I think you don't need this for vUARTS, as the ports are know at build
> time, and hence you can block access to them without requiring the
> actual vUART to be initialized.

Oh, I see now why I have it: that spilled from MMIO-based UART.

What I need is I/O ports and IRQs rangesets allocation before emulator
initialization.

>=20
> Thanks, Roger.



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Date: Thu, 07 Aug 2025 18:59:17 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 3/8] x86/domain: allocate d->{iomem,irq}_caps before arch-specific initialization
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On Mon, Aug 04, 2025 at 12:20:11PM +0200, Jan Beulich wrote:
> On 31.07.2025 21:21, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Move IRQ/IOMEM rangesets allocation before arch_domain_create().
> >
> > That guarantees that arch-specific code could access those rangesets to
> > register traps for emulation.
> >
> > It is necessary for those emulators registering trap handlers and ensur=
ing
> > that emulated IRQs are not shared with the physical IRQs.
> >
> > Move dom0_setup_permissions() call right after I/O rangesets are alloca=
ted.
> >
> > Move pvh_setup_mmcfg() inside dom0_setup_permissions() close to the pla=
ce
> > where MMCFG ranges are initialized.
>=20
> And this is just because you like doing so? I ask because first and forem=
ost
> I can't make the connection between this and the purpose of this patch.

No, that is a bad leftover from the MMIO-based emulator.

>=20
> > --- a/xen/arch/x86/dom0_build.c
> > +++ b/xen/arch/x86/dom0_build.c
> > @@ -471,6 +471,24 @@ static void __init process_dom0_ioports_disable(st=
ruct domain *dom0)
> >      }
> >  }
> >
> > +static void __hwdom_init setup_mmcfg(struct domain *d)
>=20
> Why __hwdom_init when ...
>=20
> > @@ -480,6 +498,14 @@ int __init dom0_setup_permissions(struct domain *d=
)
> >      if ( pv_shim )
> >          return 0;
> >
> > +    /*
> > +     * MMCFG initialization must be performed before setting domain
> > +     * permissions, as the MCFG areas must not be part of the domain I=
OMEM
> > +     * accessible regions.
> > +     */
> > +    if ( is_hvm_domain(d) )
> > +        setup_mmcfg(d);
>=20
> ... the sole caller is __init?
>=20
> Jan



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Subject: [regression] Re: [PATCH v2] x86/vpci: fix handling of BAR overlaps
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To: Roger Pau Monne , xen-devel@lists.xenproject.org
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
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In-Reply-To: <20250516083159.61945-1-roger.pau@citrix.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On 16/05/2025 9:31 am, Roger Pau Monne wrote:
> diff --git a/xen/arch/x86/pci.c b/xen/arch/x86/pci.c
> index 97b792e578f1..afaf9fe1c053 100644
> --- a/xen/arch/x86/pci.c
> +++ b/xen/arch/x86/pci.c
> @@ -98,3 +98,53 @@ int pci_conf_write_intercept(unsigned int seg, unsigned int bdf,
>  
>      return rc;
>  }
> +
> +bool pci_check_bar(const struct pci_dev *pdev, mfn_t start, mfn_t end)
> +{
> +    /*
> +     * Check if BAR is not overlapping with any memory region defined
> +     * in the memory map.
> +     */
> +    if ( !is_memory_hole(start, end) )
> +        gdprintk(XENLOG_WARNING,
> +                 "%pp: BAR at [%"PRI_mfn", %"PRI_mfn"] not in memory map hole\n",
> +                 &pdev->sbdf, mfn_x(start), mfn_x(end));


This is causing substantial logspam now.  From adl-* in CI,

(XEN) [    4.131847] PCI add device 0000:00:14.0
[    0.227775] pci 0000:00:14.2: [8086:7aa7] type 00 class 0x050000
(XEN) [    4.131987] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.131996] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132013] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132015] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132062] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132070] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132084] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132086] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
[    0.227942] pci 0000:00:14.2: reg 0x10: [mem 0x00000000-0x00003fff 64bit]
(XEN) [    4.132130] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132138] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132153] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132155] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132202] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132210] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132224] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132226] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
[    0.228082] pci 0000:00:14.2: reg 0x18: [mem 0x00000000-0x00000fff 64bit]
(XEN) [    4.132270] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132277] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132291] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132294] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132322] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132330] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132343] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132346] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132360] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132368] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132382] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132384] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132412] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132420] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132433] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132436] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132451] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132458] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132474] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132476] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132528] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132536] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132550] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00003] not in memory map hole
(XEN) [    4.132552] arch/x86/pci.c:109:d0v0 0000:00:14.2: BAR at [00000, 00000] not in memory map hole
(XEN) [    4.132729] PCI add device 0000:00:14.2

It really needs to become less verbose.

~Andrew



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Date: Thu, 07 Aug 2025 19:12:04 +0000
To: =?utf-8?Q?Roger_Pau_Monn=C3=A9?= 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators
Message-ID: 
In-Reply-To: 
References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-3-dmukhin@ford.com> 
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On Wed, Aug 06, 2025 at 04:24:52PM +0200, Roger Pau Monn=C3=A9 wrote:
> On Thu, Jul 31, 2025 at 07:21:49PM +0000, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Introduce a driver framework to abstract UART emulators in the hypervis=
or.
> >
> > That allows for architecture-independent handling of virtual UARTs in t=
he
> > console driver and simplifies enabling new UART emulators.
> >
> > The framework is built under CONFIG_HAS_VUART, which will be automatica=
lly
> > enabled once the user enables any UART emulator.
> >
> > Current implementation supports maximum of one vUART of each kind per d=
omain.
> >
> > Use new domain_has_vuart() in the console driver code to check whether =
to
> > forward console input to the domain using vUART.
> >
> > Note: existing vUARTs are deliberately *not* hooked to the new framewor=
k to
> > minimize the scope of the patch: vpl011 (i.e. SBSA) emulator and "vuart=
" (i.e.
> > minimalistic MMIO-mapped dtuart for hwdoms on Arm) are kept unmodified.
> >
> > Signed-off-by: Denis Mukhin 
> > ---
> > Changes since v3:
> > - new patch
> > - original patch from ML: https://lore.kernel.org/xen-devel/20250624035=
443.344099-16-dmukhin@ford.com/
> > ---
> >  xen/arch/arm/xen.lds.S         |   1 +
> >  xen/arch/ppc/xen.lds.S         |   1 +
> >  xen/arch/riscv/xen.lds.S       |   1 +
> >  xen/arch/x86/xen.lds.S         |   1 +
> >  xen/common/Kconfig             |   2 +
> >  xen/common/Makefile            |   1 +
> >  xen/common/emul/Kconfig        |   6 ++
> >  xen/common/emul/Makefile       |   1 +
> >  xen/common/emul/vuart/Kconfig  |   6 ++
> >  xen/common/emul/vuart/Makefile |   1 +
> >  xen/common/emul/vuart/vuart.c  | 112 +++++++++++++++++++++++++++++++++
> >  xen/common/keyhandler.c        |   3 +
> >  xen/drivers/char/console.c     |   4 ++
> >  xen/include/xen/vuart.h        |  84 +++++++++++++++++++++++++
> >  xen/include/xen/xen.lds.h      |  10 +++
> >  15 files changed, 234 insertions(+)
> >  create mode 100644 xen/common/emul/Kconfig
> >  create mode 100644 xen/common/emul/Makefile
> >  create mode 100644 xen/common/emul/vuart/Kconfig
> >  create mode 100644 xen/common/emul/vuart/Makefile
> >  create mode 100644 xen/common/emul/vuart/vuart.c
> >  create mode 100644 xen/include/xen/vuart.h
> >
> > diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S
> > index 9f30c3a13ed1..bdba7eaa4f65 100644
> > --- a/xen/arch/arm/xen.lds.S
> > +++ b/xen/arch/arm/xen.lds.S
> > @@ -58,6 +58,7 @@ SECTIONS
> >         *(.rodata)
> >         *(.rodata.*)
> >         VPCI_ARRAY
> > +       VUART_ARRAY
> >         *(.data.rel.ro)
> >         *(.data.rel.ro.*)
> >
> > diff --git a/xen/arch/ppc/xen.lds.S b/xen/arch/ppc/xen.lds.S
> > index 1de0b77fc6b9..f9d4e5b0dcd8 100644
> > --- a/xen/arch/ppc/xen.lds.S
> > +++ b/xen/arch/ppc/xen.lds.S
> > @@ -52,6 +52,7 @@ SECTIONS
> >          *(.rodata)
> >          *(.rodata.*)
> >          VPCI_ARRAY
> > +        VUART_ARRAY
> >          *(.data.rel.ro)
> >          *(.data.rel.ro.*)
> >
> > diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S
> > index edcadff90bfe..59dcaa5fef9a 100644
> > --- a/xen/arch/riscv/xen.lds.S
> > +++ b/xen/arch/riscv/xen.lds.S
> > @@ -47,6 +47,7 @@ SECTIONS
> >          *(.rodata)
> >          *(.rodata.*)
> >          VPCI_ARRAY
> > +        VUART_ARRAY
> >          *(.data.rel.ro)
> >          *(.data.rel.ro.*)
> >
> > diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S
> > index 8e9cac75b09e..43426df33092 100644
> > --- a/xen/arch/x86/xen.lds.S
> > +++ b/xen/arch/x86/xen.lds.S
> > @@ -136,6 +136,7 @@ SECTIONS
> >         *(.rodata)
> >         *(.rodata.*)
> >         VPCI_ARRAY
> > +       VUART_ARRAY
> >         *(.data.rel.ro)
> >         *(.data.rel.ro.*)
> >
> > diff --git a/xen/common/Kconfig b/xen/common/Kconfig
> > index 16936418a6e6..4e0bd524dc43 100644
> > --- a/xen/common/Kconfig
> > +++ b/xen/common/Kconfig
> > @@ -1,6 +1,8 @@
> >
> >  menu "Common Features"
> >
> > +source "common/emul/Kconfig"
> > +
> >  config COMPAT
> >  =09bool
> >  =09help
> > diff --git a/xen/common/Makefile b/xen/common/Makefile
> > index c316957fcb36..c0734480ee4b 100644
> > --- a/xen/common/Makefile
> > +++ b/xen/common/Makefile
> > @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) +=3D d=
evice.o
> >  obj-$(CONFIG_DEVICE_TREE_PARSE) +=3D device-tree/
> >  obj-$(CONFIG_IOREQ_SERVER) +=3D dm.o
> >  obj-y +=3D domain.o
> > +obj-y +=3D emul/
> >  obj-y +=3D event_2l.o
> >  obj-y +=3D event_channel.o
> >  obj-$(CONFIG_EVTCHN_FIFO) +=3D event_fifo.o
> > diff --git a/xen/common/emul/Kconfig b/xen/common/emul/Kconfig
> > new file mode 100644
> > index 000000000000..7c6764d1756b
> > --- /dev/null
> > +++ b/xen/common/emul/Kconfig
> > @@ -0,0 +1,6 @@
> > +menu "Domain Emulation Features"
> > +=09visible if EXPERT
> > +
> > +source "common/emul/vuart/Kconfig"
> > +
> > +endmenu
> > diff --git a/xen/common/emul/Makefile b/xen/common/emul/Makefile
> > new file mode 100644
> > index 000000000000..670682102c13
> > --- /dev/null
> > +++ b/xen/common/emul/Makefile
> > @@ -0,0 +1 @@
> > +obj-$(CONFIG_HAS_VUART) +=3D vuart/
> > diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kcon=
fig
> > new file mode 100644
> > index 000000000000..02f7dd6dc1a1
> > --- /dev/null
> > +++ b/xen/common/emul/vuart/Kconfig
> > @@ -0,0 +1,6 @@
> > +config HAS_VUART
> > +=09bool
> > +
> > +menu "UART Emulation"
> > +
> > +endmenu
> > diff --git a/xen/common/emul/vuart/Makefile b/xen/common/emul/vuart/Mak=
efile
> > new file mode 100644
> > index 000000000000..c6400b001e85
> > --- /dev/null
> > +++ b/xen/common/emul/vuart/Makefile
> > @@ -0,0 +1 @@
> > +obj-$(CONFIG_HAS_VUART) +=3D vuart.o
> > diff --git a/xen/common/emul/vuart/vuart.c b/xen/common/emul/vuart/vuar=
t.c
> > new file mode 100644
> > index 000000000000..14a7f8bd8b79
> > --- /dev/null
> > +++ b/xen/common/emul/vuart/vuart.c
> > @@ -0,0 +1,112 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * UART emulator framework.
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define VUART_ARRAY_SIZE    (__start_vuart_end - __start_vuart_array)
> > +
> > +#define for_each_vuart(vdev) \
> > +    for (unsigned __i =3D 0; \
> > +         __i < VUART_ARRAY_SIZE && (vdev =3D __start_vuart_array[__i],=
 1); \
> > +         __i++)
>=20
> Could you possibly do:
>=20
> #define for_each_vuart(vdev) \
>     for ( vdev =3D __start_vuart_array; vdev < __start_vuart_end: vdev++ =
)
>=20
> To avoid the extra __i variable in the inner scope?
>=20
> > +
> > +extern const struct vuart_ops *const __start_vuart_array[];
> > +extern const struct vuart_ops *const __start_vuart_end[];
>=20
> Naming here looks weird, why not __vuart_{start,end}?  Or
> __{start,end}_vuart_array.

I overlooked that, thanks.

>=20
> > +
> > +int vuart_add_node(struct domain *d, const void *node)
>=20
> What's the purpose of this function?  There's no comment here or in
> the declaration to figure out what's the purpose.  It's also not being
> called, which makes it unreachable code.  MISRA will likely complain
> about it?

That supposed to ge a hook to generate virtual firmware description for the
guest OS. On Arm/RISC-V that would be DT, on x86 that would be DSDT record =
in
guest's ACPI.

Stefano already asked to drop that until it is actually used, like for Arm'=
s
vUARTs.

Will remove in v5.

>=20
> > +{
> > +    const struct vuart_ops *vdev;
> > +    int rc;
> > +
> > +    for_each_vuart(vdev)
> > +    {
> > +        if ( !vdev->add_node )
> > +            continue;
> > +
> > +        rc =3D vdev->add_node(d, node);
> > +        if ( rc )
> > +            return rc;
> > +    }
> > +
> > +    return 0;
> > +}
> > +
> > +int vuart_init(struct domain *d, struct vuart_params *params)
> > +{
> > +    const struct vuart_ops *vdev;
> > +    int rc;
> > +
> > +    if ( !domain_has_vuart(d) )
> > +        return 0;
>=20
> Don't you need the domain_has_vuart() checks in all the handlers?
> Otherwise you are pointlessly iterating and calling handlers that
> won't do anything?

All handlers should check for vuart handler (per-vUART data structure)
not being NULL. Will update that code in v5.

>=20
> > +
> > +    for_each_vuart(vdev)
> > +    {
> > +        rc =3D vdev->init(d, params);
> > +        if ( rc )
> > +            return rc;
> > +    }
> > +
> > +    d->console.input_allowed =3D true;
> > +
> > +    return 0;
> > +}
> > +
> > +/*
> > + * Release any resources taken by UART emulators.
> > + *
> > + * NB: no flags are cleared, since currently exit() is called only dur=
ing
> > + * domain destroy.
> > + */
> > +void vuart_deinit(struct domain *d)
> > +{
> > +    const struct vuart_ops *vdev;
> > +
> > +    for_each_vuart(vdev)
> > +        vdev->deinit(d);
> > +}
> > +
> > +void vuart_dump_state(const struct domain *d)
> > +{
> > +    const struct vuart_ops *vdev;
> > +
> > +    for_each_vuart(vdev)
> > +        vdev->dump_state(d);
> > +}
> > +
> > +/*
> > + * Put character to the first suitable emulated UART's FIFO.
> > + */
> > +int vuart_put_rx(struct domain *d, char c)
> > +{
> > +    const struct vuart_ops *vdev =3D NULL;
> > +
> > +    ASSERT(domain_has_vuart(d));
> > +
> > +    for_each_vuart(vdev)
> > +        if ( vdev->put_rx )
> > +            break;
> > +
> > +    return vdev ? vdev->put_rx(d, c) : -ENODEV;
>=20
> The above functions seems to be designed to deal with multiple vUARTs
> in-use by the same domain, while the put_rx code gives up as soon as
> it finds an implementation that has the ->put_rx() hook set.

Correct, that is to account for hwdom vUART (or just "vuart" on Arm) which =
by
design has no RX buffer/register emulation.

>=20
> > +}
> > +
> > +bool domain_has_vuart(const struct domain *d)
> > +{
> > +    uint32_t mask =3D 0;
> > +
> > +    return !!(d->emulation_flags & mask);
> > +}
> > +
> > +/*
> > + * Local variables:
> > + * mode: C
> > + * c-file-style: "BSD"
> > + * c-basic-offset: 4
> > + * indent-tabs-mode: nil
> > + * End:
> > + */
> > diff --git a/xen/common/keyhandler.c b/xen/common/keyhandler.c
> > index eccd97c565c6..af427d25dc0d 100644
> > --- a/xen/common/keyhandler.c
> > +++ b/xen/common/keyhandler.c
> > @@ -22,6 +22,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >
> >  static unsigned char keypress_key;
> > @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char key=
)
> >                             v->periodic_period / 1000000);
> >              }
> >          }
> > +
> > +        vuart_dump_state(d);
> >      }
> >
> >      for_each_domain ( d )
> > diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c
> > index 963c7b043cd8..93254979817b 100644
> > --- a/xen/drivers/char/console.c
> > +++ b/xen/drivers/char/console.c
> > @@ -33,6 +33,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  #ifdef CONFIG_X86
> >  #include 
> > @@ -601,6 +602,7 @@ static void __serial_rx(char c)
> >          /*
> >           * Deliver input to the hardware domain buffer, unless it is
> >           * already full.
> > +         * NB: must be the first check: hardware domain may have emula=
ted UART.
> >           */
> >          if ( (serial_rx_prod - serial_rx_cons) !=3D SERIAL_RX_SIZE )
> >              serial_rx_ring[SERIAL_RX_MASK(serial_rx_prod++)] =3D c;
> > @@ -611,6 +613,8 @@ static void __serial_rx(char c)
> >           */
> >          send_global_virq(VIRQ_CONSOLE);
> >      }
> > +    else if ( domain_has_vuart(d) )
> > +        rc =3D vuart_put_rx(d, c);
> >  #ifdef CONFIG_SBSA_VUART_CONSOLE
> >      else
> >          /* Deliver input to the emulated UART. */
> > diff --git a/xen/include/xen/vuart.h b/xen/include/xen/vuart.h
> > new file mode 100644
> > index 000000000000..e843026df4b1
> > --- /dev/null
> > +++ b/xen/include/xen/vuart.h
> > @@ -0,0 +1,84 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * UART emulator framework.
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#ifndef XEN_VUART_H
> > +#define XEN_VUART_H
> > +
> > +#include 
> > +#include 
> > +#include 
> > +
> > +struct vuart_params {
> > +    domid_t console_domid;
> > +    gfn_t gfn;
> > +    evtchn_port_t evtchn;
>=20
> I think this should be empty initially, as there's no implementation
> that uses the hooks it's completely opaque to me what should be placed
> in vuart_params.

Good point, will do.

>=20
> > +};
> > +
> > +struct vuart_ops {
> > +    int (*add_node)(struct domain *d, const void *node);
> > +    int (*init)(struct domain *d, struct vuart_params *params);
> > +    void (*deinit)(struct domain *d);
> > +    void (*dump_state)(const struct domain *d);
> > +    int (*put_rx)(struct domain *d, char c);
>=20
> We haven't been very good at this, but ideally hooks should be
> documented as to which task they are expected to perform, so that
> future implementations have some initial help in understanding how
> this is supposed to work.

Agreed.

>=20
> > +};
> > +
> > +#define VUART_REGISTER(name, x) \
> > +    static const struct vuart_ops *const __name##_entry \
> > +        __used_section(".data.vuart." #name) =3D (x);
>=20
> For vPCI we are moving this to a different section, I think you want
> to use ".data.rel.ro.vuart" here.

Ack.

>=20
> Thanks, Roger.



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Date: Thu, 07 Aug 2025 19:38:40 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 7/8] tools/xl: enable NS16550-compatible UART emulator for PVH (x86)
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References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-8-dmukhin@ford.com> <549bde88-38a3-4920-9309-f898b48d3bda@suse.com>
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On Mon, Aug 04, 2025 at 01:06:32PM +0200, Jan Beulich wrote:
> On 31.07.2025 21:22, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Enable virtual NS16550 for PVH domains in xl.
> >
> > {map,unmap}_domain_emuirq_pirq() infrastructure is modified by adding n=
ew
> > type of interrupt resources 'IRQ_EMU' which means 'emulated device IRQ'
> > (similarly to IRQ_MSI_EMU).
> >
> > This is necessary to for IOAPIC emulation code to skip IRQ->PIRQ mappin=
g
> > (vioapic_hwdom_map_gsi()) when guest OS unmasks vIOAPIC pin correspondi=
ng to
> > virtual device's IRQ.
> >
> > Also, hvm_gsi_eoi() is modified to trigger assertion in hvm_gsi_deasser=
t()
> > path for ISA IRQs.
> >
> > Signed-off-by: Denis Mukhin 
> > ---
> > Changes since v3:
> > - new patch
> > ---
> >  tools/libs/light/libxl_x86.c          |  2 +-
> >  xen/arch/x86/domain.c                 |  2 ++
> >  xen/arch/x86/hvm/vioapic.c            | 10 ++++++++++
> >  xen/arch/x86/include/asm/irq.h        |  1 +
> >  xen/common/emul/vuart/vuart-ns16550.c | 27 +++++++++++++++++++++++++--
> >  xen/drivers/passthrough/x86/hvm.c     |  9 ++++-----
> >  6 files changed, 43 insertions(+), 8 deletions(-)
>=20
> Given this diffstat, how come the patch prefix is "tools/xl:"? You don't =
even
> touch xl ...

Yeah, my bad, that should have been saying something like
"enable IRQ emulation via vIOAPIC"

Will update.

>=20
> > --- a/xen/common/emul/vuart/vuart-ns16550.c
> > +++ b/xen/common/emul/vuart/vuart-ns16550.c
> > @@ -355,7 +355,9 @@ static void ns16550_irq_assert(const struct vuart_n=
s16550 *vdev)
> >      struct domain *d =3D vdev->owner;
> >      int vector;
> >
> > -    if ( has_vpic(d) ) /* HVM */
> > +    if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */
> > +        vector =3D hvm_ioapic_assert(d, vdev->irq, false);
> > +    else if ( has_vpic(d) ) /* HVM */
> >          vector =3D hvm_isa_irq_assert(d, vdev->irq, vioapic_get_vector=
);
>=20
> Why not
>=20
>     if ( has_vpic(d) ) /* HVM */
>          vector =3D hvm_isa_irq_assert(d, vdev->irq, vioapic_get_vector);
>     else if ( has_vioapic(d) ) /* PVH */
>         vector =3D hvm_ioapic_assert(d, vdev->irq, false);
>=20
> Less code churn and maybe even less generated code.
>=20
> > @@ -367,7 +369,9 @@ static void ns16550_irq_deassert(const struct vuart=
_ns16550 *vdev)
> >  {
> >      struct domain *d =3D vdev->owner;
> >
> > -    if ( has_vpic(d) ) /* HVM */
> > +    if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */
> > +        hvm_ioapic_deassert(d, vdev->irq);
> > +    else if ( has_vpic(d) ) /* HVM */
> >          hvm_isa_irq_deassert(d, vdev->irq);
>=20
> Same here then.
>=20
> > --- a/xen/drivers/passthrough/x86/hvm.c
> > +++ b/xen/drivers/passthrough/x86/hvm.c
> > @@ -924,12 +924,11 @@ static void hvm_gsi_eoi(struct domain *d, unsigne=
d int gsi)
> >  {
> >      struct pirq *pirq =3D pirq_info(d, gsi);
> >
> > -    /* Check if GSI is actually mapped. */
> > -    if ( !pirq_dpci(pirq) )
> > -        return;
> > -
> >      hvm_gsi_deassert(d, gsi);
> > -    hvm_pirq_eoi(pirq);
> > +
> > +    /* Check if GSI is actually mapped. */
> > +    if ( pirq_dpci(pirq) )
> > +        hvm_pirq_eoi(pirq);
> >  }
>=20
> The correctness of this change (in particular hvm_gsi_deassert() now alwa=
ys
> running) wants reasoning about in the description.
>=20
> Jan
>=20



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Juergen Gross ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v8 0/4] Enable guest suspend/resume support on ARM via vPSCI
Date: Thu,  7 Aug 2025 22:39:24 +0300
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From: Mykola Kvach 

This patch series introduces the initial support for guest suspend
and resume on ARM platforms using the PSCI SYSTEM_SUSPEND interface. The main
goal is to allow ARM guests to request suspension using PSCI and be resumed
by the control domain (e.g., via "xl resume").

### Background

The PSCI SYSTEM_SUSPEND call is part of the PSCI v1.0+ specification and is
used by guests to enter the deepest possible power state. On Xen/ARM, we
emulate this interface in the virtual PSCI (vPSCI) layer for guests.

This series includes:

1. A new vPSCI implementation of the PSCI SYSTEM_SUSPEND function for guests
2. Documentation updates to SUPPORT.md to reflect PSCI and vPSCI support status
3. Enabling "xl resume" command compilation for ARM, which was previously disabled

### Usage

For Linux-based guests:
  - Suspend can be triggered using: "echo mem > /sys/power/state" or "systemctl suspend"
  - Resume can be performed from control domain using: "xl resume "

For more information, refer to the official Linux kernel documentation on power management.

Note that currently, SYSTEM_SUSPEND is supported only for guest domains (not for
the hardware domain).
---

TODO: enable "xl suspend" for ARM
---

This is the first part of previous patch series and originally consist only
with necessary changes needed for guest domain suspend.

Changes in V8:
- GIC and virtual timer context saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Main changes in V6:
- Skip execution of ctxt_switch_from for VCPUs in paused domains.
- Implement domain_resume_nopause
- Add a helper to determine if a VCPU is in suspended domain.
- Ignore upper 32 bits of arguments for 64-bit domains calling SMC32 SYSTEM_SUSPEND.
- Macro renamed from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND for clarity.
- Documentation now focuses only on the SYSTEM_SUSPEND function, with improved wording and structure.
- Changelog and commit messages refined for clarity and to remove redundant explanations.

Main change in V5:
  - Reverted the logic related to suspending domains. Instead of the standby
    mode introduced in v4, domains now resume execution at the point provided
    during suspend

The rest of the minor changes are described in the changelog of each commit.

Previous versions of this patch series:
  V1: https://lists.xenproject.org/archives/html/xen-devel/2018-11/msg01093.html
  V2: https://marc.info/?l=xen-devel&m=166514782207736&w=2
  V3: https://lists.xenproject.org/archives/html/xen-devel/2025-03/msg00168.html

Mykola Kvach (4):
  xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
  tools/xl: Allow compilation of 'xl resume' command on Arm
  SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
  CHANGELOG: Document guest suspend/resume to RAM support on Arm

 CHANGELOG.md                          |   2 +
 SUPPORT.md                            |   5 +-
 tools/include/libxl.h                 |   1 -
 tools/xl/xl.h                         |   4 +-
 tools/xl/xl_cmdtable.c                |   4 +-
 tools/xl/xl_migrate.c                 |   2 +-
 tools/xl/xl_saverestore.c             |   2 +-
 tools/xl/xl_vmcontrol.c               |  12 +--
 xen/arch/arm/domain.c                 |  17 +++--
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   2 +-
 xen/arch/arm/vpsci.c                  | 101 ++++++++++++++++++++++----
 xen/common/domain.c                   |  22 ++++--
 xen/include/xen/sched.h               |   6 ++
 15 files changed, 139 insertions(+), 44 deletions(-)

-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v8 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
Date: Thu,  7 Aug 2025 22:39:25 +0300
Message-ID: <64cbfa58af7935c47141a2b1c0560e8d63e3d712.1754595198.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPSCI
(virtual PSCI) interface, allowing guests to request suspend via the PSCI
v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).

The implementation:
- Adds SYSTEM_SUSPEND function IDs to PSCI definitions
- Implements trapping and handling of SYSTEM_SUSPEND in vPSCI
- Allows only non-hardware domains to invoke SYSTEM_SUSPEND; for the
  hardware domain, PSCI_NOT_SUPPORTED is returned to avoid halting the
  system in hwdom_shutdown() called from domain_shutdown
- Ensures all secondary VCPUs of the calling domain are offline before
  allowing suspend due to PSCI spec

GIC and virtual timer context must be saved when the domain suspends.
This is done by moving the respective code in ctxt_switch_from
before the return that happens if the domain suspended.

Usage:

For Linux-based guests, suspend can be initiated with:
    echo mem > /sys/power/state
or via:
    systemctl suspend

Resuming the guest is performed from control domain using:
      xl resume 

Signed-off-by: Mykola Kvach 
---
Changes in V8:
- GIC and virtual timer context must be saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Changes in V6:
- skip execution of ctxt_switch_from for vcpu that is in paused domain
- add implementation of domain_resume without domain_pause
- add helper function to determine if vcpu is suspended or not
- ignore upper 32 bits of argument values when the domain is 64-bit
  and calls the SMC32 SYSTEM_SUSPEND function
- cosmetic changes after review

Changes in V5:
- don't use standby mode, restore execution in a provided by guest point
- move checking that all CPUs, except current one, are offline to after
  pausing the vCPUs
- provide ret status from arch_domain_shutdown and handle it in
  domain_shutdown
- adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI functions

Changes in V4:
Dropped all changes related to watchdog, domain is marked as shutting
down in domain_shutdown and watchdog timeout handler won't trigger
because of it.

Previous versions included code to manage Xen watchdog timers during suspend,
but this was removed. When a guest OS starts the Xen watchdog (either via the
kernel driver or xenwatchdogd), it is responsible for managing that state
across suspend/resume. On Linux, the Xen kernel driver properly stops the
watchdog during suspend. However, when xenwatchdogd is used instead, suspend
handling is incomplete, potentially leading to watchdog-triggered resets on
resume. Xen leaves watchdog handling to the guest OS and its services.

Dropped all changes related to VCPU context, because instead domain_shutdown
is used, so we don't need any extra changes for suspending domain.

Changes in V3:
Dropped all domain flags and related code (which touched common functions like
vcpu_unblock), keeping only the necessary changes for Xen suspend/resume, i.e.
suspend/resume is now fully supported only for the hardware domain.
Proper support for domU suspend/resume will be added in a future patch.
This patch does not yet include VCPU context reset or domain context
restoration in VCPU.
---
 xen/arch/arm/domain.c                 |  17 +++--
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   2 +-
 xen/arch/arm/vpsci.c                  | 101 ++++++++++++++++++++++----
 xen/common/domain.c                   |  22 ++++--
 xen/include/xen/sched.h               |   6 ++
 7 files changed, 122 insertions(+), 29 deletions(-)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 310c578909..9e9649c4e2 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -90,6 +90,16 @@ static void ctxt_switch_from(struct vcpu *p)
     if ( is_idle_vcpu(p) )
         return;
 
+    /* Arch timer */
+    p->arch.cntkctl = READ_SYSREG(CNTKCTL_EL1);
+    virt_timer_save(p);
+
+    /* VGIC */
+    gic_save_state(p);
+
+    if ( test_bit(_VPF_suspended, &p->pause_flags) )
+        return;
+
     p2m_save_state(p);
 
     /* CP 15 */
@@ -106,10 +116,6 @@ static void ctxt_switch_from(struct vcpu *p)
     p->arch.tpidrro_el0 = READ_SYSREG(TPIDRRO_EL0);
     p->arch.tpidr_el1 = READ_SYSREG(TPIDR_EL1);
 
-    /* Arch timer */
-    p->arch.cntkctl = READ_SYSREG(CNTKCTL_EL1);
-    virt_timer_save(p);
-
     if ( is_32bit_domain(p->domain) && cpu_has_thumbee )
     {
         p->arch.teecr = READ_SYSREG(TEECR32_EL1);
@@ -158,9 +164,6 @@ static void ctxt_switch_from(struct vcpu *p)
 
     /* XXX MPU */
 
-    /* VGIC */
-    gic_save_state(p);
-
     isb();
 }
 
diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/include/asm/perfc_defn.h
index effd25b69e..8dfcac7e3b 100644
--- a/xen/arch/arm/include/asm/perfc_defn.h
+++ b/xen/arch/arm/include/asm/perfc_defn.h
@@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system_reset")
 PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
 PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
 PERFCOUNTER(vpsci_features,            "vpsci: features")
+PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
 
 PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
 
diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/psci.h
index 4780972621..48a93e6b79 100644
--- a/xen/arch/arm/include/asm/psci.h
+++ b/xen/arch/arm/include/asm/psci.h
@@ -47,10 +47,12 @@ void call_psci_system_reset(void);
 #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
 #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
 #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
+#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
 
 #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
 #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
 #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
+#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
 
 /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
 #define PSCI_0_2_AFFINITY_LEVEL_ON      0
diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/asm/vpsci.h
index 0cca5e6830..69d40f9d7f 100644
--- a/xen/arch/arm/include/asm/vpsci.h
+++ b/xen/arch/arm/include/asm/vpsci.h
@@ -23,7 +23,7 @@
 #include 
 
 /* Number of function implemented by virtual PSCI (only 0.2 or later) */
-#define VPSCI_NR_FUNCS  12
+#define VPSCI_NR_FUNCS  14
 
 /* Functions handle PSCI calls from the guests */
 bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index 7ba9ccd94b..67d369a8a2 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -10,28 +10,18 @@
 
 #include 
 
-static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
-                            register_t context_id)
+static int do_setup_vcpu_ctx(struct vcpu *v, register_t entry_point,
+                      register_t context_id)
 {
-    struct vcpu *v;
     struct domain *d = current->domain;
     struct vcpu_guest_context *ctxt;
     int rc;
     bool is_thumb = entry_point & 1;
-    register_t vcpuid;
-
-    vcpuid = vaffinity_to_vcpuid(target_cpu);
-
-    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
-        return PSCI_INVALID_PARAMETERS;
 
     /* THUMB set is not allowed with 64-bit domain */
     if ( is_64bit_domain(d) && is_thumb )
         return PSCI_INVALID_ADDRESS;
 
-    if ( !test_bit(_VPF_down, &v->pause_flags) )
-        return PSCI_ALREADY_ON;
-
     if ( (ctxt = alloc_vcpu_guest_context()) == NULL )
         return PSCI_DENIED;
 
@@ -78,11 +68,32 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
     if ( rc < 0 )
         return PSCI_DENIED;
 
-    vcpu_wake(v);
-
     return PSCI_SUCCESS;
 }
 
+static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
+                            register_t context_id)
+{
+    int rc;
+    struct vcpu *v;
+    struct domain *d = current->domain;
+    register_t vcpuid;
+
+    vcpuid = vaffinity_to_vcpuid(target_cpu);
+
+    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
+        return PSCI_INVALID_PARAMETERS;
+
+    if ( !test_bit(_VPF_down, &v->pause_flags) )
+        return PSCI_ALREADY_ON;
+
+    rc = do_setup_vcpu_ctx(v, entry_point, context_id);
+    if ( rc == PSCI_SUCCESS )
+        vcpu_wake(v);
+
+    return rc;
+}
+
 static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
 {
     int32_t ret;
@@ -197,6 +208,48 @@ static void do_psci_0_2_system_reset(void)
     domain_shutdown(d,SHUTDOWN_reboot);
 }
 
+static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid)
+{
+    int32_t rc;
+    struct vcpu *v;
+    struct domain *d = current->domain;
+
+    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
+    if ( is_hardware_domain(d) )
+        return PSCI_NOT_SUPPORTED;
+
+    /* Ensure that all CPUs other than the calling one are offline */
+    domain_lock(d);
+    for_each_vcpu ( d, v )
+    {
+        if ( v != current && is_vcpu_online(v) )
+        {
+            domain_unlock(d);
+            return PSCI_DENIED;
+        }
+    }
+    domain_unlock(d);
+
+    rc = domain_shutdown(d, SHUTDOWN_suspend);
+    if ( rc )
+        return PSCI_DENIED;
+
+    rc = do_setup_vcpu_ctx(current, epoint, cid);
+    if ( rc != PSCI_SUCCESS )
+    {
+        domain_resume_nopause(d);
+        return rc;
+    }
+
+    set_bit(_VPF_suspended, ¤t->pause_flags);
+
+    dprintk(XENLOG_DEBUG,
+            "Dom %u: SYSTEM_SUSPEND requested, epoint=%#lx, cid=%#lx\n",
+            d->domain_id, epoint, cid);
+
+    return rc;
+}
+
 static int32_t do_psci_1_0_features(uint32_t psci_func_id)
 {
     /* /!\ Ordered by function ID and not name */
@@ -214,6 +267,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id)
     case PSCI_0_2_FN32_SYSTEM_OFF:
     case PSCI_0_2_FN32_SYSTEM_RESET:
     case PSCI_1_0_FN32_PSCI_FEATURES:
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
     case ARM_SMCCC_VERSION_FID:
         return 0;
     default:
@@ -344,6 +399,24 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
         return true;
     }
 
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
+    {
+        register_t epoint = PSCI_ARG(regs, 1);
+        register_t cid = PSCI_ARG(regs, 2);
+
+        if ( is_64bit_domain(current->domain) &&
+             fid == PSCI_1_0_FN32_SYSTEM_SUSPEND )
+        {
+            epoint &= GENMASK(31, 0);
+            cid &= GENMASK(31, 0);
+        }
+
+        perfc_incr(vpsci_system_suspend);
+        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
+        return true;
+    }
+
     default:
         return false;
     }
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 5241a1629e..c3609b0cb0 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -1343,16 +1343,13 @@ int domain_shutdown(struct domain *d, u8 reason)
     return 0;
 }
 
-void domain_resume(struct domain *d)
+#ifndef CONFIG_ARM
+static
+#endif
+void domain_resume_nopause(struct domain *d)
 {
     struct vcpu *v;
 
-    /*
-     * Some code paths assume that shutdown status does not get reset under
-     * their feet (e.g., some assertions make this assumption).
-     */
-    domain_pause(d);
-
     spin_lock(&d->shutdown_lock);
 
     d->is_shutting_down = d->is_shut_down = 0;
@@ -1360,13 +1357,24 @@ void domain_resume(struct domain *d)
 
     for_each_vcpu ( d, v )
     {
+        clear_bit(_VPF_suspended, &v->pause_flags);
+
         if ( v->paused_for_shutdown )
             vcpu_unpause(v);
         v->paused_for_shutdown = 0;
     }
 
     spin_unlock(&d->shutdown_lock);
+}
 
+void domain_resume(struct domain *d)
+{
+    /*
+     * Some code paths assume that shutdown status does not get reset under
+     * their feet (e.g., some assertions make this assumption).
+     */
+    domain_pause(d);
+    domain_resume_nopause(d);
     domain_unpause(d);
 }
 
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index fd5c9f9333..4050b5dc6a 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -814,6 +814,9 @@ void domain_destroy(struct domain *d);
 int domain_kill(struct domain *d);
 int domain_shutdown(struct domain *d, u8 reason);
 void domain_resume(struct domain *d);
+#ifdef CONFIG_ARM
+void domain_resume_nopause(struct domain *d);
+#endif
 
 int domain_soft_reset(struct domain *d, bool resuming);
 
@@ -1010,6 +1013,9 @@ static inline struct domain *next_domain_in_cpupool(
 /* VCPU is parked. */
 #define _VPF_parked          8
 #define VPF_parked           (1UL<<_VPF_parked)
+/* VCPU is suspended. */
+#define _VPF_suspended 9
+#define VPF_suspended (1UL<<_VPF_suspended)
 
 static inline bool vcpu_runnable(const struct vcpu *v)
 {
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Anthony PERARD ,
	Juergen Gross 
Subject: [PATCH v8 2/4] tools/xl: Allow compilation of 'xl resume' command on Arm
Date: Thu,  7 Aug 2025 22:39:26 +0300
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From: Mykola Kvach 

The "xl resume" command was previously excluded from Arm builds because
system suspend/resume (e.g., SYSTEM_SUSPEND via vPSCI) was not
implemented. On x86, this command is used for resume.

This change enables compilation of `xl resume` on Arm regardless of the
underlying implementation status, making the tool available for testing
and future feature support. The relevant libxl infrastructure and handler
functions are already present and usable.

Note: This does not imply full system suspend/resume support on Arm.
      The `xl suspend` command still does not work on Arm platforms.

Signed-off-by: Mykola Kvach 
Acked-by: Anthony PERARD 
---
Changes in v7:
- dropped renaming of LIBXL_HAVE_NO_SUSPEND_RESUME macro

Changes in v6:
- Renamed macro from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND
  to better reflect the scope of this change
- Applied cosmetic changes based on review feedback
---
 tools/include/libxl.h     |  1 -
 tools/xl/xl.h             |  4 ++--
 tools/xl/xl_cmdtable.c    |  4 ++--
 tools/xl/xl_migrate.c     |  2 +-
 tools/xl/xl_saverestore.c |  2 +-
 tools/xl/xl_vmcontrol.c   | 12 ++++++------
 6 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/tools/include/libxl.h b/tools/include/libxl.h
index 185f74d8a8..b204fc5e2e 100644
--- a/tools/include/libxl.h
+++ b/tools/include/libxl.h
@@ -1140,7 +1140,6 @@ typedef struct libxl__ctx libxl_ctx;
  * restoring or migrating a domain. In this case the related functions
  * should be expected to return failure. That is:
  *  - libxl_domain_suspend
- *  - libxl_domain_resume
  *  - libxl_domain_remus_start
  */
 #if defined(__arm__) || defined(__aarch64__)
diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index 45745f0dbb..9233b73f85 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -65,7 +65,7 @@ static const char migrate_permission_to_go[]=
     "domain is yours, you are cleared to unpause";
 static const char migrate_report[]=
     "my copy unpause results are as follows";
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
   /* followed by one byte:
    *     0: everything went well, domain is running
@@ -130,8 +130,8 @@ int main_migrate_receive(int argc, char **argv);
 int main_save(int argc, char **argv);
 int main_migrate(int argc, char **argv);
 int main_suspend(int argc, char **argv);
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 int main_resume(int argc, char **argv);
-#endif
 int main_dump_core(int argc, char **argv);
 int main_pause(int argc, char **argv);
 int main_unpause(int argc, char **argv);
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 06a0039718..bcb2d233cc 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -198,12 +198,12 @@ const struct cmd_spec cmd_table[] = {
       "Suspend a domain to RAM",
       "",
     },
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "resume",
       &main_resume, 0, 1,
       "Resume a domain from RAM",
       "",
     },
-#endif
     { "dump-core",
       &main_dump_core, 0, 1,
       "Core dump a domain",
@@ -548,7 +548,7 @@ const struct cmd_spec cmd_table[] = {
       "                        checkpoint must be disabled.\n"
       "-p                      Use COLO userspace proxy."
     },
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "devd",
       &main_devd, 0, 1,
       "Daemon that listens for devices and launches backends",
diff --git a/tools/xl/xl_migrate.c b/tools/xl/xl_migrate.c
index b8594f44a5..4b4a379aa1 100644
--- a/tools/xl/xl_migrate.c
+++ b/tools/xl/xl_migrate.c
@@ -767,7 +767,7 @@ int main_remus(int argc, char **argv)
     close(send_fd);
     return EXIT_FAILURE;
 }
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 /*
diff --git a/tools/xl/xl_saverestore.c b/tools/xl/xl_saverestore.c
index 953d791d1a..747094ec7b 100644
--- a/tools/xl/xl_saverestore.c
+++ b/tools/xl/xl_saverestore.c
@@ -270,7 +270,7 @@ int main_save(int argc, char **argv)
     return EXIT_SUCCESS;
 }
 
-#endif /* LIBXL_HAVE_NO_SUSPEND_RESUME */
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 
diff --git a/tools/xl/xl_vmcontrol.c b/tools/xl/xl_vmcontrol.c
index c813732838..93766f631b 100644
--- a/tools/xl/xl_vmcontrol.c
+++ b/tools/xl/xl_vmcontrol.c
@@ -38,11 +38,6 @@ static void suspend_domain(uint32_t domid)
     libxl_domain_suspend_only(ctx, domid, NULL);
 }
 
-static void resume_domain(uint32_t domid)
-{
-    libxl_domain_resume(ctx, domid, 1, NULL);
-}
-
 int main_suspend(int argc, char **argv)
 {
     int opt;
@@ -55,6 +50,12 @@ int main_suspend(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
+
+static void resume_domain(uint32_t domid)
+{
+    libxl_domain_resume(ctx, domid, 1, NULL);
+}
 
 int main_resume(int argc, char **argv)
 {
@@ -68,7 +69,6 @@ int main_resume(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
-#endif
 
 static void pause_domain(uint32_t domid)
 {
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini 
Subject: [PATCH v8 3/4] SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
Date: Thu,  7 Aug 2025 22:39:27 +0300
Message-ID: <60902266c3817ed221a45f6acf265438bc7ff322.1754595198.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

Add a new entry under the "Virtual Hardware, QEMU" section documenting
support for the optional PSCI SYSTEM_SUSPEND function exposed to guests.

This function is available via the virtual PSCI (vPSCI) interface and
allows guest domains (domUs) to initiate system suspend operations.

The feature is currently marked as Experimental.

Signed-off-by: Mykola Kvach 
---
Changes in v6:
- Dropped the generic guest PSCI support entry (merged in a separate patch)
- This patch now documents only the SYSTEM_SUSPEND optional function
- Reworded commit message to match the final form after rebase

Changes in v5:
- Dropped ARM/PSCI entry: this refers to internal use of PSCI SMC calls,
  which is not relevant for SUPPORT.md
- Added a dedicated entry for PSCI SYSTEM_SUSPEND instead of generic guest
  PSCI info; guest PSCI support was documented in a separate patch
---
 SUPPORT.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/SUPPORT.md b/SUPPORT.md
index 6a82a92189..b5ab049b52 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -962,8 +962,9 @@ Emulated PSCI interface exposed to guests. We support all mandatory
 functions of PSCI 1.1. See below for the list of optional PSCI call
 implemented and their status.
 
-   Status, Mandatory: Supported
-   Status, MIGRATE_INFO_TYPE: Supported
+    Status, Mandatory: Supported
+    Status, MIGRATE_INFO_TYPE: Supported
+    Status, SYSTEM_SUSPEND: Experimental
 
 ## Virtual Hardware, QEMU
 
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v8 4/4] CHANGELOG: Document guest suspend/resume to RAM support on Arm
Date: Thu,  7 Aug 2025 22:39:28 +0300
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From: Mykola Kvach 

Mention the newly added support for guest suspend and resume to/from
RAM via vPSCI on Arm platforms.

This support is limited to non-hardware domain guests.

Signed-off-by: Mykola Kvach 
Acked-by: Oleksii Kurochko 
---
Chnages in v6:
- removed reduntand explanation that thi support added for
  both arm32 and arm64.

Changes in v5:
- adjustments to the commit title and message
- expanded the changelog entry to include more context about
  suspend/resume support introduced in this patch series
---
 CHANGELOG.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe..7e42ca9b59 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -29,6 +29,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 
  - On Arm:
     - Ability to enable stack protector
+    - Support for guest suspend and resume to/from RAM via vPSCI.
+      Applies only to non-hardware domain guests.
 
 ### Removed
  - On x86:
-- 
2.48.1



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Date: Thu, 07 Aug 2025 19:41:09 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 4/8] xen/8250-uart: update definitions
Message-ID: 
In-Reply-To: 
References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-5-dmukhin@ford.com> 
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On Mon, Aug 04, 2025 at 12:23:34PM +0200, Jan Beulich wrote:
> On 31.07.2025 21:22, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Added missing definitions needed for NS16550 UART emulator.
> >
> > Newly introduced MSR definitions re-used in the existing ns16550 driver=
.
> >
> > Also, corrected FCR DMA definition bit#3 (0x08) as per:
> >   https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
> > See "7.7.2 FIFO Control Register (FCR)".
> >
> > Signed-off-by: Denis Mukhin 
> > ---
> > Changes since v3:
> > - feedback addressed
> > - made use of new UART_MCR_XXX bits in ns16550 driver
> > - Link to v3: https://lore.kernel.org/xen-devel/20250103-vuart-ns8250-v=
3-v1-19-c5d36b31d66c@ford.com/
> > ---
> >  xen/drivers/char/ns16550.c  |  6 ++---
> >  xen/include/xen/8250-uart.h | 50 ++++++++++++++++++++++++++++++-------
> >  2 files changed, 44 insertions(+), 12 deletions(-)
> >
> > diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
> > index df7fff7f81df..a899711e2a8b 100644
> > --- a/xen/drivers/char/ns16550.c
> > +++ b/xen/drivers/char/ns16550.c
> > @@ -739,9 +739,9 @@ static int __init check_existence(struct ns16550 *u=
art)
> >       * Check to see if a UART is really there.
> >       * Use loopback test mode.
> >       */
> > -    ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | 0x0A);
> > -    status =3D ns_read_reg(uart, UART_MSR) & 0xF0;
> > -    return (status =3D=3D 0x90);
> > +    ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | UART_MCR_RTS | UART_M=
CR_OUT2);
> > +    status =3D ns_read_reg(uart, UART_MSR) & UART_MSR_STATUS;
> > +    return (status =3D=3D (UART_MSR_CTS | UART_MSR_DCD));
> >  }
> >
> >  #ifdef CONFIG_HAS_PCI
> > diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h
> > index d13352940c13..bc11cdc376c9 100644
> > --- a/xen/include/xen/8250-uart.h
> > +++ b/xen/include/xen/8250-uart.h
> > @@ -32,6 +32,7 @@
> >  #define UART_MCR          0x04    /* Modem control        */
> >  #define UART_LSR          0x05    /* line status          */
> >  #define UART_MSR          0x06    /* Modem status         */
> > +#define UART_SCR          0x07    /* Scratch pad          */
> >  #define UART_USR          0x1f    /* Status register (DW) */
> >  #define UART_DLL          0x00    /* divisor latch (ls) (DLAB=3D1) */
> >  #define UART_DLM          0x01    /* divisor latch (ms) (DLAB=3D1) */
> > @@ -42,6 +43,8 @@
> >  #define UART_IER_ETHREI   0x02    /* tx reg. empty        */
> >  #define UART_IER_ELSI     0x04    /* rx line status       */
> >  #define UART_IER_EMSI     0x08    /* MODEM status         */
> > +#define UART_IER_MASK \
> > +    (UART_IER_ERDAI | UART_IER_ETHREI | UART_IER_ELSI | UART_IER_EMSI)
>=20
> At the example of this: It having no users here, how are we to know it'll
> gain some (and hence be useful)? Adding missing base definitions is imo
> fine without immediate users, but for derived ones it's less clear.

There're UART_IIR and UART_IER bits which could be re-used.
Will update ns16550 driver.
Thanks.



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From: Nicola Vetrini 
To: xen-devel@lists.xenproject.org
Cc: sstabellini@kernel.org,
	michal.orzel@amd.com,
	xenia.ragiadakou@amd.com,
	ayan.kumar.halder@amd.com,
	consulting@bugseng.com,
	Nicola Vetrini ,
	Doug Goldstein ,
	Andrew Cooper 
Subject: [XEN PATCH] automation/eclair: restrict clean target to xen
Date: Thu,  7 Aug 2025 23:53:56 +0200
Message-ID: 
X-Mailer: git-send-email 2.43.0
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

The clean target also clears files outside the xen directory,
which is not needed for the purposes of running an analysis.

No functional change.

Reported-by: Andrew Cooper 
Signed-off-by: Nicola Vetrini 
---
 automation/eclair_analysis/prepare.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/automation/eclair_analysis/prepare.sh b/automation/eclair_analysis/prepare.sh
index 4285ff26de54..e941e6edc4f3 100755
--- a/automation/eclair_analysis/prepare.sh
+++ b/automation/eclair_analysis/prepare.sh
@@ -39,12 +39,12 @@ fi
     fi
 
     ./configure
-    make clean
+    make -C xen clean
     find . -type f -name "*.safparse" -print -delete
     "${script_dir}/build.sh" "$1"
     # Generate additional configuration files
     "${script_dir}/ECLAIR/generate_ecl.sh"
-    make clean
+    make -C xen clean
     cd xen
     make -f "${script_dir}/Makefile.prepare" prepare
     # Translate the /* SAF-n-safe */ comments into ECLAIR CBTs
-- 
2.43.0



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On 2025-08-07 03:00, Jürgen Groß wrote:
> On 07.08.25 03:56, Jason Andryuk wrote:
>> With hyperlaunch, a domU can start before its console ring is connected
>> by xenconsoled.  With nothing emptying the ring, it can quickly fill
>> during boot.  In domU_write_console(), __write_console() returns 0 when
>> the ring is full.  This loops spins until xenconsoled starts emptying
>> the ring:
>>
>>          while (len) {
>>                  ssize_t sent = __write_console(cons, data, len);
>>
>>                  if (sent < 0)
>>                          return sent;
>>
>>                  data += sent;
>>                  len -= sent;
>>
>>                  if (unlikely(len))
>>                          HYPERVISOR_sched_op(SCHEDOP_yield, NULL);
>>          }
>>
>> The goal of this patch is to add a way for the frontend to know when a
>> console is connected.  This patch adds a new flag to the end of the
>> console ring structure.  It is used for the backend to indicate that it
>> has connected and started servicing the page.
>>
>> The two values are
>> XENCONSOLE_DISCONNECTED 1
>> XENCONSOLE_CONNECTED    0
>>
>> XENCONSOLE_DISCONNECTED indicates to the guest that ring is
>> disconnected, so it will not be serviced.  The guest can avoid writing
>> into it in that case.  A domU can use console hypercalls and only
>> transition to the ring when it is connected and won't fill and block.
>>
>> Once the backend (xenconsoled) maps and starts servicing the
>> console, the flag will be set to XENCONSOLE_CONNECTED (0) to indicate
>> the backend state to the frontend.
>>
>> The connected value as 0 will be match the default of a zero-ed console
>> page.  Hyperlaunch can set the flag to XENCONSOLE_DISCONNECTED and let
>> xenconsoled set to XENCONSOLE_CONNECTED.
> 
> I think libxenguest should set XENCONSOLE_DISCONNECTED as well (see below).
> 
>>
>> Old domU hvc_xen drivers won't check the flag.
>> New domU hvc_xen running on a new xen/xenconsoled will work properly.
>> New domU hvc_xen on old xen/xenconsoled should only see a 0 for the flag
>> and behave as if connected.
>>
>> Signed-off-by: Jason Andryuk 
> 
> Adapt the title of the patch?

With Jan's naming suggestion, it'll be "xenconsole: Add connection field"

>> ---
>> v1:
>> Remove evtchn notify call
>> Set connected later when there is no error
>>
>> RFC v3:
>> Flip flag values so 0 is connected.
>>
>> The other option would be to add:
>> uint32_t features
>> uint32_t connected
>>
>> New domUs would check features for a magic value and/or flag to know
>> they can rely on connected transitioning.
>>
>> I think making XENCONSOLE_CONNECTED == 0 side steps the need for
>> an additional features field.  As long as assuming zero-ed memory is
>> acceptable.  However, this only matters for a hyperlaunched guest -
>> xenconsoled will normally readily connect the console and set the value.
> 
> I'd like to consider other cases as well, e.g. a console driver domain.
> So any instance creating a domain with a console ring page should set the
> flag initially to "disconnected".

Sure, that makes sense.

I don't have immediate plans for this, but I had the additional thought 
of placing the event channel inside the page like we do for xenstore. 
Today xenconsoled uses xenstore for the ring-ref and event channel, 
thought it tries the reserved console grant first.  With the reserved 
grant, and the event channel inside, that dependency would be removed. 
Xenconsoled still needs some way to know when domains come and go, and 
it depends on xenstore's @introduceDomain/@releaseDomain for that.  So 
it couldn't be completely decoupled without some other mechanism.

>> This assumes that existing frontends are not using the flag space for
>> some other use.
>>
>> Removed idea:
>> Send an event channel notification to let the domU know that xenconsoled
>> is connected.  Xenstored does similar, but for xenstore, the xenstore
>> driver owns the event channel/irq and can rebind it.  For hvc_xen, the
>> hvc subsystem owns the irq, so it isn't readily available for rebinding.
>> This is not implemented.
>>
>> I had the idea for the kernel to use a static key and switch writing
>> from the hypercall to the PV ring once connected.  It didn't actually
>> work in my short attempt - I think changing the static key from within
>> an interupt was wrong.  I fell back to just checking the flag directly
> 
> You'd need to do the static key changing from a worker thread instead.

Thanks.  I'll investigate.

Regards,
Jason


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Subject: Re: [PATCH v1] xenconsole: Add connected flag
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On 2025-08-07 05:19, Jan Beulich wrote:
> On 07.08.2025 03:56, Jason Andryuk wrote:
>> --- a/xen/include/public/io/console.h
>> +++ b/xen/include/public/io/console.h
>> @@ -19,6 +19,19 @@ struct xencons_interface {
>>       char out[2048];
>>       XENCONS_RING_IDX in_cons, in_prod;
>>       XENCONS_RING_IDX out_cons, out_prod;
>> +/*
>> + * Flag values signaling from backend to frontend whether the console is
>> + * connected.  i.e. Whether it will be serviced and emptied.
>> + *
>> + * The flag starts as disconnected.
>> + */
>> +#define XENCONSOLE_DISCONNECTED 1
>> +/*
>> + * The flag is set to connected when the backend connects and the console
>> + * will be serviced.
>> + */
>> +#define XENCONSOLE_CONNECTED    0
>> +    uint32_t flag;
>>   };
> 
> Even if the field name is singular, there's the possible reading of everything
> together as the connected state merely taking one bit, with other bits available
> for future use. IOW I think the field wants giving a less generic name, and
> perhaps also shrinking to unsigned char (or uint8_t, but char is being used in
> the structure already anyway).

It could become a bit in a multi-flag field, dut the structure has a 
good bit of space to the end of the page,  A named field, "connection", 
sounds good.

Thanks,
Jason


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On Thu, Aug 07, 2025 at 11:53:56PM +0200, Nicola Vetrini wrote:
> The clean target also clears files outside the xen directory,
> which is not needed for the purposes of running an analysis.
>=20
> No functional change.
>=20
> Reported-by: Andrew Cooper 
> Signed-off-by: Nicola Vetrini 

Reviewed-by: Denis Mukhin =20

> ---
>  automation/eclair_analysis/prepare.sh | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>=20
> diff --git a/automation/eclair_analysis/prepare.sh b/automation/eclair_an=
alysis/prepare.sh
> index 4285ff26de54..e941e6edc4f3 100755
> --- a/automation/eclair_analysis/prepare.sh
> +++ b/automation/eclair_analysis/prepare.sh
> @@ -39,12 +39,12 @@ fi
>      fi
>=20
>      ./configure
> -    make clean
> +    make -C xen clean
>      find . -type f -name "*.safparse" -print -delete
>      "${script_dir}/build.sh" "$1"
>      # Generate additional configuration files
>      "${script_dir}/ECLAIR/generate_ecl.sh"
> -    make clean
> +    make -C xen clean
>      cd xen
>      make -f "${script_dir}/Makefile.prepare" prepare
>      # Translate the /* SAF-n-safe */ comments into ECLAIR CBTs
> --
> 2.43.0
>=20
>=20



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Date: Fri, 08 Aug 2025 02:19:56 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v14 1/4] xen/domain: unify domain ID allocation
Message-ID: <20250808021938.669855-2-dmukhin@ford.com>
In-Reply-To: <20250808021938.669855-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Currently, there are two different domain ID allocation implementations:

  1) Sequential IDs allocation in dom0less Arm code based on max_init_domid=
;

  2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
     max_init_domid (both Arm and x86).

The domain ID allocation covers dom0 or late hwdom, predefined domains,
post-boot domains, excluding Xen system domains (domid >=3D
DOMID_FIRST_RESERVED).

It makes sense to have a common helper code for such task across architectu=
res
(Arm and x86) and between dom0less / toolstack domU allocation.

Note, fixing dependency on max_init_domid is out of scope of this patch.

Wrap the domain ID allocation as an arch-independent function domid_alloc()=
 in
new common/domid.c based on the bitmap.

Allocation algorithm:
- If an explicit domain ID is provided, verify its availability and use it =
if
  ID is not used;
- If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1=
],
  starting from the last used ID.
  Implementation guarantees that two consecutive calls will never return th=
e
  same ID. ID#0 is reserved for the first boot domain (currently, dom0) and
  excluded from the allocation range.

Remove is_free_domid() helper as it is not needed now.

No functional change intended.

Signed-off-by: Denis Mukhin 
---
Changes since v13:
- fixed panic() formatting in x86's create_dom0()
- fixed login in do_domctl()
- optimizations in domid_alloc()
---
 xen/arch/arm/domain_build.c             |  7 +-
 xen/arch/x86/setup.c                    |  7 +-
 xen/common/Makefile                     |  1 +
 xen/common/device-tree/dom0less-build.c | 15 ++--
 xen/common/domain.c                     |  2 +
 xen/common/domctl.c                     | 43 ++---------
 xen/common/domid.c                      | 95 +++++++++++++++++++++++++
 xen/include/xen/domain.h                |  3 +
 8 files changed, 126 insertions(+), 47 deletions(-)
 create mode 100644 xen/common/domid.c

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 463ae4474d30..789f2b9d3ce7 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2050,6 +2050,7 @@ void __init create_dom0(void)
         .grant_opts =3D XEN_DOMCTL_GRANT_version(opt_gnttab_max_version),
     };
     unsigned int flags =3D CDF_privileged | CDF_hardware;
+    domid_t domid;
     int rc;
=20
     /* The vGIC for DOM0 is exactly emulating the hardware GIC */
@@ -2074,7 +2075,11 @@ void __init create_dom0(void)
     if ( !llc_coloring_enabled )
         flags |=3D CDF_directmap;
=20
-    dom0 =3D domain_create(0, &dom0_cfg, flags);
+    domid =3D domid_alloc(0);
+    if ( domid =3D=3D DOMID_INVALID )
+        panic("Error allocating domain ID 0\n");
+
+    dom0 =3D domain_create(domid, &dom0_cfg, flags);
     if ( IS_ERR(dom0) )
         panic("Error creating domain 0 (rc =3D %ld)\n", PTR_ERR(dom0));
=20
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 1543dd251cc6..398da734c0c5 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1047,8 +1047,11 @@ static struct domain *__init create_dom0(struct boot=
_info *bi)
     if ( iommu_enabled )
         dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu;
=20
-    /* Create initial domain.  Not d0 for pvshim. */
-    bd->domid =3D get_initial_domain_id();
+    /* Allocate initial domain ID.  Not d0 for pvshim. */
+    bd->domid =3D domid_alloc(get_initial_domain_id());
+    if ( bd->domid =3D=3D DOMID_INVALID )
+        panic("Error allocating domain ID %u\n", get_initial_domain_id());
+
     d =3D domain_create(bd->domid, &dom0_cfg,
                       pv_shim ? 0 : CDF_privileged | CDF_hardware);
     if ( IS_ERR(d) )
diff --git a/xen/common/Makefile b/xen/common/Makefile
index c316957fcb36..0c7d0f5d46e1 100644
--- a/xen/common/Makefile
+++ b/xen/common/Makefile
@@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) +=3D devic=
e.o
 obj-$(CONFIG_DEVICE_TREE_PARSE) +=3D device-tree/
 obj-$(CONFIG_IOREQ_SERVER) +=3D dm.o
 obj-y +=3D domain.o
+obj-y +=3D domid.o
 obj-y +=3D event_2l.o
 obj-y +=3D event_channel.o
 obj-$(CONFIG_EVTCHN_FIFO) +=3D event_fifo.o
diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tr=
ee/dom0less-build.c
index 6bb038111de9..f4b6b515d2d2 100644
--- a/xen/common/device-tree/dom0less-build.c
+++ b/xen/common/device-tree/dom0less-build.c
@@ -833,6 +833,7 @@ void __init create_domUs(void)
     {
         struct kernel_info ki =3D KERNEL_INFO_INIT;
         int rc =3D parse_dom0less_node(node, &ki.bd);
+        domid_t domid;
=20
         if ( rc =3D=3D -ENOENT )
             continue;
@@ -842,13 +843,13 @@ void __init create_domUs(void)
         if ( (max_init_domid + 1) >=3D DOMID_FIRST_RESERVED )
             panic("No more domain IDs available\n");
=20
-        /*
-         * The variable max_init_domid is initialized with zero, so here i=
t's
-         * very important to use the pre-increment operator to call
-         * domain_create() with a domid > 0. (domid =3D=3D 0 is reserved f=
or Dom0)
-         */
-        ki.bd.d =3D domain_create(++max_init_domid,
-                                &ki.bd.create_cfg, ki.bd.create_flags);
+        domid =3D domid_alloc(DOMID_INVALID);
+        if ( domid =3D=3D DOMID_INVALID )
+            panic("Error allocating ID for domain %s\n", dt_node_name(node=
));
+
+        max_init_domid =3D max(max_init_domid, domid);
+
+        ki.bd.d =3D domain_create(domid, &ki.bd.create_cfg, ki.bd.create_f=
lags);
         if ( IS_ERR(ki.bd.d) )
             panic("Error creating domain %s (rc =3D %ld)\n",
                   dt_node_name(node), PTR_ERR(ki.bd.d));
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 5241a1629eeb..a7e303253d1a 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -692,6 +692,8 @@ static void _domain_destroy(struct domain *d)
=20
     lock_profile_deregister_struct(LOCKPROF_TYPE_PERDOM, d);
=20
+    domid_free(d->domain_id);
+
     free_domain_struct(d);
 }
=20
diff --git a/xen/common/domctl.c b/xen/common/domctl.c
index f2a7caaf853c..71e712c1f316 100644
--- a/xen/common/domctl.c
+++ b/xen/common/domctl.c
@@ -51,20 +51,6 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nodemas=
k,
                                    MAX_NUMNODES);
 }
=20
-static inline int is_free_domid(domid_t dom)
-{
-    struct domain *d;
-
-    if ( dom >=3D DOMID_FIRST_RESERVED )
-        return 0;
-
-    if ( (d =3D rcu_lock_domain_by_id(dom)) =3D=3D NULL )
-        return 1;
-
-    rcu_unlock_domain(d);
-    return 0;
-}
-
 void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info=
)
 {
     struct vcpu *v;
@@ -423,36 +409,19 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u=
_domctl)
=20
     case XEN_DOMCTL_createdomain:
     {
-        domid_t        dom;
-        static domid_t rover =3D 0;
+        /* NB: ID#0 is reserved, find the first suitable ID instead. */
+        domid_t domid =3D domid_alloc(op->domain ?: DOMID_INVALID);
=20
-        dom =3D op->domain;
-        if ( (dom > 0) && (dom < DOMID_FIRST_RESERVED) )
+        if ( domid =3D=3D DOMID_INVALID )
         {
             ret =3D -EEXIST;
-            if ( !is_free_domid(dom) )
-                break;
-        }
-        else
-        {
-            for ( dom =3D rover + 1; dom !=3D rover; dom++ )
-            {
-                if ( dom =3D=3D DOMID_FIRST_RESERVED )
-                    dom =3D 1;
-                if ( is_free_domid(dom) )
-                    break;
-            }
-
-            ret =3D -ENOMEM;
-            if ( dom =3D=3D rover )
-                break;
-
-            rover =3D dom;
+            break;
         }
=20
-        d =3D domain_create(dom, &op->u.createdomain, false);
+        d =3D domain_create(domid, &op->u.createdomain, false);
         if ( IS_ERR(d) )
         {
+            domid_free(domid);
             ret =3D PTR_ERR(d);
             d =3D NULL;
             break;
diff --git a/xen/common/domid.c b/xen/common/domid.c
new file mode 100644
index 000000000000..7839a2885810
--- /dev/null
+++ b/xen/common/domid.c
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Domain ID allocator.
+ *
+ * Covers dom0 or late hwdom, predefined domains, post-boot domains.
+ * Excludes system domains (ID >=3D DOMID_FIRST_RESERVED).
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include 
+
+static DEFINE_SPINLOCK(domid_lock);
+static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED);
+
+/*
+ * Allocate domain ID.
+ *
+ * @param domid Domain ID hint:
+ * - If an explicit domain ID is provided, verify its availability and use=
 it
+ *   if ID is not used;
+ * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] rang=
e,
+ *   starting from the last used ID. Implementation guarantees that two
+ *   consecutive calls will never return the same ID. ID#0 is reserved for
+ *   the first boot domain (currently, dom0) and excluded from the allocat=
ion
+ *   range.
+ * @return Valid domain ID in case of successful allocation,
+ *         DOMID_INVALID - otherwise.
+ */
+domid_t domid_alloc(domid_t domid)
+{
+    static domid_t domid_last;
+
+    spin_lock(&domid_lock);
+
+    /* Exact match. */
+    if ( domid < DOMID_FIRST_RESERVED )
+    {
+        if ( __test_and_set_bit(domid, domid_bitmap) )
+            domid =3D DOMID_INVALID;
+    }
+    /*
+     * Exhaustive search.
+     *
+     * Domain ID#0 is reserved for the first boot domain (e.g. control dom=
ain)
+     * and excluded from allocation.
+     */
+    else
+    {
+        domid_t num =3D DOMID_FIRST_RESERVED;
+
+        domid =3D find_next_zero_bit(domid_bitmap, num, domid_last + 1);
+        if ( domid =3D=3D num && domid_last !=3D 0 )
+        {
+            num =3D domid_last + 1;
+            domid =3D find_next_zero_bit(domid_bitmap, num, 1);
+        }
+
+        ASSERT(domid <=3D DOMID_FIRST_RESERVED);
+        if ( domid < num )
+        {
+            __set_bit(domid, domid_bitmap);
+            domid_last =3D domid;
+        }
+        else
+            domid =3D DOMID_INVALID;
+    }
+
+    spin_unlock(&domid_lock);
+
+    return domid;
+}
+
+void domid_free(domid_t domid)
+{
+    int rc;
+
+    ASSERT(domid <=3D DOMID_FIRST_RESERVED);
+
+    spin_lock(&domid_lock);
+    rc =3D __test_and_clear_bit(domid, domid_bitmap);
+    spin_unlock(&domid_lock);
+
+    ASSERT(rc);
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615fd..8aab05ae93c8 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -38,6 +38,9 @@ void arch_get_domain_info(const struct domain *d,
=20
 domid_t get_initial_domain_id(void);
=20
+domid_t domid_alloc(domid_t domid);
+void domid_free(domid_t domid);
+
 /* CDF_* constant. Internal flags for domain creation. */
 /* Is this a privileged domain? */
 #define CDF_privileged           (1U << 0)
--=20
2.34.1




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Date: Fri, 08 Aug 2025 02:19:49 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v14 0/4] xen/domain: domain ID allocation
Message-ID: <20250808021938.669855-1-dmukhin@ford.com>
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Patch 1 introduces new domid_{alloc,free} calls.
Patch 2 is a prep change for domain ID allocator test.
Patch 3 introduces some basic testing for domain ID allocator.
Patch 4 adjusts create_dom0() messages (use %pd).

Link to v13: https://lore.kernel.org/xen-devel/20250730174042.1632011-1-dmu=
khin@ford.com/
Link to CI: https://gitlab.com/xen-project/people/dmukhin/xen/-/pipelines/1=
973569163

Denis Mukhin (4):
  xen/domain: unify domain ID allocation
  tools/include: move xc_bitops.h to xen-tools/bitops.h
  tools/tests: introduce unit tests for domain ID allocator
  xen/domain: update create_dom0() messages

 .../xen-tools/bitops.h}                       | 16 +++-
 tools/libs/ctrl/xc_misc.c                     | 13 +--
 tools/libs/guest/xg_dom_elfloader.c           |  3 +-
 tools/libs/guest/xg_dom_hvmloader.c           |  3 +-
 tools/libs/guest/xg_private.h                 |  2 +-
 tools/libs/guest/xg_sr_common.h               |  3 +-
 tools/tests/Makefile                          |  2 +-
 tools/tests/domid/.gitignore                  |  2 +
 tools/tests/domid/Makefile                    | 56 +++++++++++
 tools/tests/domid/harness.h                   | 54 +++++++++++
 tools/tests/domid/include/xen/domain.h        |  1 +
 tools/tests/domid/test-domid.c                | 86 +++++++++++++++++
 xen/arch/arm/domain_build.c                   | 13 ++-
 xen/arch/x86/setup.c                          | 11 ++-
 xen/common/Makefile                           |  1 +
 xen/common/device-tree/dom0less-build.c       | 15 +--
 xen/common/domain.c                           |  2 +
 xen/common/domctl.c                           | 43 ++-------
 xen/common/domid.c                            | 95 +++++++++++++++++++
 xen/include/xen/domain.h                      |  3 +
 xen/lib/find-next-bit.c                       |  5 +
 21 files changed, 362 insertions(+), 67 deletions(-)
 rename tools/{libs/ctrl/xc_bitops.h =3D> include/xen-tools/bitops.h} (84%)
 create mode 100644 tools/tests/domid/.gitignore
 create mode 100644 tools/tests/domid/Makefile
 create mode 100644 tools/tests/domid/harness.h
 create mode 120000 tools/tests/domid/include/xen/domain.h
 create mode 100644 tools/tests/domid/test-domid.c
 create mode 100644 xen/common/domid.c

--=20
2.34.1




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Date: Fri, 08 Aug 2025 02:20:01 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v14 2/4] tools/include: move xc_bitops.h to xen-tools/bitops.h
Message-ID: <20250808021938.669855-3-dmukhin@ford.com>
In-Reply-To: <20250808021938.669855-1-dmukhin@ford.com>
References: <20250808021938.669855-1-dmukhin@ford.com>
Feedback-ID: 123220910:user:proton
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From: Denis Mukhin =20

Move xc_bitops.h to common tools location to be shared between
the toolstack and unit test code.

Adjust the guard in xen-tools/bitops.h

Correct the #include directives and comments referring to the old
xc_bitops.h in the toolstack code.

Signed-off-by: Denis Mukhin 
---
Changes since v13:
- new patch
---
 .../ctrl/xc_bitops.h =3D> include/xen-tools/bitops.h} |  6 +++---
 tools/libs/ctrl/xc_misc.c                           | 13 +++++++------
 tools/libs/guest/xg_dom_elfloader.c                 |  3 ++-
 tools/libs/guest/xg_dom_hvmloader.c                 |  3 ++-
 tools/libs/guest/xg_private.h                       |  2 +-
 tools/libs/guest/xg_sr_common.h                     |  3 +--
 6 files changed, 16 insertions(+), 14 deletions(-)
 rename tools/{libs/ctrl/xc_bitops.h =3D> include/xen-tools/bitops.h} (95%)

diff --git a/tools/libs/ctrl/xc_bitops.h b/tools/include/xen-tools/bitops.h
similarity index 95%
rename from tools/libs/ctrl/xc_bitops.h
rename to tools/include/xen-tools/bitops.h
index 4a776dc3a57f..681482f6759f 100644
--- a/tools/libs/ctrl/xc_bitops.h
+++ b/tools/include/xen-tools/bitops.h
@@ -1,5 +1,5 @@
-#ifndef XC_BITOPS_H
-#define XC_BITOPS_H 1
+#ifndef __XEN_TOOLS_BITOPS_H__
+#define __XEN_TOOLS_BITOPS_H__
=20
 /* bitmap operations for single threaded access */
=20
@@ -81,4 +81,4 @@ static inline void bitmap_or(void *_dst, const void *_oth=
er,
         dst[i] |=3D other[i];
 }
=20
-#endif  /* XC_BITOPS_H */
+#endif  /* __XEN_TOOLS_BITOPS_H__ */
diff --git a/tools/libs/ctrl/xc_misc.c b/tools/libs/ctrl/xc_misc.c
index 33e87bac2868..10ddf85667a9 100644
--- a/tools/libs/ctrl/xc_misc.c
+++ b/tools/libs/ctrl/xc_misc.c
@@ -17,8 +17,8 @@
  * License along with this library; If not, see .
  */
=20
-#include "xc_bitops.h"
 #include "xc_private.h"
+#include 
 #include 
=20
 int xc_get_max_cpus(xc_interface *xch)
@@ -94,11 +94,12 @@ xc_cpumap_t xc_cpumap_alloc(xc_interface *xch)
 }
=20
 /*
- * xc_bitops.h has macros that do this as well - however they assume that
- * the bitmask is word aligned but xc_cpumap_t is only guaranteed to be
- * byte aligned and so we need byte versions for architectures which do
- * not support misaligned accesses (which is basically everyone
- * but x86, although even on x86 it can be inefficient).
+ *  has macros that do this as well - however they
+ * assume that the bitmask is word aligned but xc_cpumap_t is only
+ * guaranteed to be byte aligned and so we need byte versions for
+ * architectures which do not support misaligned accesses (which is
+ * basically everyone but x86, although even on x86 it can be
+ * inefficient).
  *
  * NOTE: The xc_bitops macros now use byte alignment.
  * TODO: Clean up the users of this interface.
diff --git a/tools/libs/guest/xg_dom_elfloader.c b/tools/libs/guest/xg_dom_=
elfloader.c
index f17930d98bf7..8531e90f8e21 100644
--- a/tools/libs/guest/xg_dom_elfloader.c
+++ b/tools/libs/guest/xg_dom_elfloader.c
@@ -25,8 +25,9 @@
 #include 
 #include 
=20
+#include 
+
 #include "xg_private.h"
-#include "xc_bitops.h"
=20
 #define XEN_VER "xen-3.0"
=20
diff --git a/tools/libs/guest/xg_dom_hvmloader.c b/tools/libs/guest/xg_dom_=
hvmloader.c
index 39e1e5f579a7..0f569c20c522 100644
--- a/tools/libs/guest/xg_dom_hvmloader.c
+++ b/tools/libs/guest/xg_dom_hvmloader.c
@@ -24,8 +24,9 @@
 #include 
 #include 
=20
+#include 
+
 #include "xg_private.h"
-#include "xc_bitops.h"
=20
 /* -----------------------------------------------------------------------=
- */
 /* parse elf binary                                                       =
  */
diff --git a/tools/libs/guest/xg_private.h b/tools/libs/guest/xg_private.h
index d73947094f2e..285229cf82a3 100644
--- a/tools/libs/guest/xg_private.h
+++ b/tools/libs/guest/xg_private.h
@@ -28,9 +28,9 @@
 #include 
=20
 #include "xc_private.h"
-#include "xc_bitops.h"
 #include "xenguest.h"
=20
+#include 
 #include 
 #include 
 #include 
diff --git a/tools/libs/guest/xg_sr_common.h b/tools/libs/guest/xg_sr_commo=
n.h
index 2f058ee3a6ff..2e583f2eac72 100644
--- a/tools/libs/guest/xg_sr_common.h
+++ b/tools/libs/guest/xg_sr_common.h
@@ -2,11 +2,10 @@
 #define __COMMON__H
=20
 #include 
+#include 
=20
 #include "xg_private.h"
 #include "xg_save_restore.h"
-#include "xc_bitops.h"
-
 #include "xg_sr_stream_format.h"
=20
 /* String representation of Domain Header types. */
--=20
2.34.1




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Date: Fri, 08 Aug 2025 02:20:06 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v14 3/4] tools/tests: introduce unit tests for domain ID allocator
Message-ID: <20250808021938.669855-4-dmukhin@ford.com>
In-Reply-To: <20250808021938.669855-1-dmukhin@ford.com>
References: <20250808021938.669855-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Introduce some basic infrastructure for doing domain ID allocation unit tes=
ts,
and add a few tests that ensure correctness of the domain ID allocator.

Use  and xen/lib/find-next-bit.c in test hardness code.

Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.

Signed-off-by: Denis Mukhin 
---
Changes since v13:
- reworked bitops integration
- hooked xen/lib/find-next-bit.c
- cleaned up harness.h code
- made test to use more IDs
---
 tools/include/xen-tools/bitops.h       | 10 +++
 tools/tests/Makefile                   |  2 +-
 tools/tests/domid/.gitignore           |  2 +
 tools/tests/domid/Makefile             | 56 +++++++++++++++++
 tools/tests/domid/harness.h            | 54 ++++++++++++++++
 tools/tests/domid/include/xen/domain.h |  1 +
 tools/tests/domid/test-domid.c         | 86 ++++++++++++++++++++++++++
 xen/lib/find-next-bit.c                |  5 ++
 8 files changed, 215 insertions(+), 1 deletion(-)
 create mode 100644 tools/tests/domid/.gitignore
 create mode 100644 tools/tests/domid/Makefile
 create mode 100644 tools/tests/domid/harness.h
 create mode 120000 tools/tests/domid/include/xen/domain.h
 create mode 100644 tools/tests/domid/test-domid.c

diff --git a/tools/include/xen-tools/bitops.h b/tools/include/xen-tools/bit=
ops.h
index 681482f6759f..3b98fba6d74c 100644
--- a/tools/include/xen-tools/bitops.h
+++ b/tools/include/xen-tools/bitops.h
@@ -12,6 +12,16 @@
 #define BITS_PER_LONG 32
 #endif
=20
+#define ffsl(x)       __builtin_ffsl(x)
+
+#define BIT_WORD(nr)  ((nr) / BITS_PER_LONG)
+
+#define BITS_TO_LONGS(bits) \
+    (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
+
+#define DECLARE_BITMAP(name, bits) \
+    unsigned long name[BITS_TO_LONGS(bits)]
+
 #define BITMAP_ENTRY(_nr,_bmap) ((_bmap))[(_nr) / 8]
 #define BITMAP_SHIFT(_nr) ((_nr) % 8)
=20
diff --git a/tools/tests/Makefile b/tools/tests/Makefile
index 36928676a666..ff1666425436 100644
--- a/tools/tests/Makefile
+++ b/tools/tests/Makefile
@@ -1,7 +1,7 @@
 XEN_ROOT =3D $(CURDIR)/../..
 include $(XEN_ROOT)/tools/Rules.mk
=20
-SUBDIRS-y :=3D
+SUBDIRS-y :=3D domid
 SUBDIRS-y +=3D resource
 SUBDIRS-$(CONFIG_X86) +=3D cpu-policy
 SUBDIRS-$(CONFIG_X86) +=3D tsx
diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignore
new file mode 100644
index 000000000000..70e306b3c074
--- /dev/null
+++ b/tools/tests/domid/.gitignore
@@ -0,0 +1,2 @@
+*.o
+test-domid
diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile
new file mode 100644
index 000000000000..d96ceca6d954
--- /dev/null
+++ b/tools/tests/domid/Makefile
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Unit tests for domain ID allocator.
+#
+# Copyright 2025 Ford Motor Company
+
+XEN_ROOT=3D$(CURDIR)/../../..
+include $(XEN_ROOT)/tools/Rules.mk
+
+TESTS :=3D test-domid
+
+vpath domid.c $(XEN_ROOT)/xen/common/
+vpath find-next-bit.c $(XEN_ROOT)/xen/lib/
+
+.PHONY: all
+all: $(TESTS)
+
+.PHONY: run
+run: $(TESTS)
+=09$(foreach t,$(TESTS),./$(t);)
+
+.PHONY: clean
+clean:
+=09$(RM) -- *.o $(TESTS) $(DEPS_RM)
+
+.PHONY: distclean
+distclean: clean
+=09$(RM) -- *~
+
+.PHONY: install
+install: all
+=09$(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests
+=09$(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests
+
+.PHONY: uninstall
+uninstall:
+=09$(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid
+
+CFLAGS +=3D -D__XEN_TOOLS__
+# find-next-bit.c
+CFLAGS +=3D '-DEXPORT_SYMBOL(x)=3D' \
+          -Dfind_first_bit \
+          -Dfind_first_zero_bit \
+          -Dfind_next_bit \
+          -Dfind_next_bit_le \
+          -Dfind_next_zero_bit_le
+CFLAGS +=3D $(APPEND_CFLAGS)
+CFLAGS +=3D $(CFLAGS_xeninclude)
+CFLAGS +=3D -I./include/
+
+LDFLAGS +=3D $(APPEND_LDFLAGS)
+
+test-domid: domid.o find-next-bit.o test-domid.o
+=09$(CC) $^ -o $@ $(LDFLAGS)
+
+-include $(DEPS_INCLUDE)
diff --git a/tools/tests/domid/harness.h b/tools/tests/domid/harness.h
new file mode 100644
index 000000000000..b043519dcb35
--- /dev/null
+++ b/tools/tests/domid/harness.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Unit test harness for domain ID allocator.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#ifndef _TEST_HARNESS_
+#define _TEST_HARNESS_
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+typedef bool spinlock_t;
+typedef uint16_t domid_t;
+
+extern domid_t domid_alloc(domid_t domid);
+extern void domid_free(domid_t domid);
+
+extern unsigned long find_next_zero_bit(const unsigned long *addr,
+                                        unsigned long size,
+                                        unsigned long offset);
+
+#define __test_and_set_bit(nr, addr)    test_and_set_bit(nr, addr)
+#define __test_and_clear_bit(nr, addr)  test_and_clear_bit(nr, addr)
+#define __set_bit(nr, addr)             set_bit(nr, addr)
+
+#define BUG_ON(x)                       assert(!(x))
+#define ASSERT(x)                       assert(x)
+
+#define DEFINE_SPINLOCK(l)              spinlock_t l
+#define spin_lock(l)                    (*(l) =3D true)
+#define spin_unlock(l)                  (*(l) =3D false)
+
+#define printk                          printf
+
+#define DOMID_FIRST_RESERVED            (100)
+#define DOMID_INVALID                   (101)
+
+#endif /* _TEST_HARNESS_ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tools/tests/domid/include/xen/domain.h b/tools/tests/domid/inc=
lude/xen/domain.h
new file mode 120000
index 000000000000..2eda9aed088e
--- /dev/null
+++ b/tools/tests/domid/include/xen/domain.h
@@ -0,0 +1 @@
+../../harness.h
\ No newline at end of file
diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-domid.=
c
new file mode 100644
index 000000000000..7b6fb5ee2a7b
--- /dev/null
+++ b/tools/tests/domid/test-domid.c
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Unit tests for domain ID allocator.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include "harness.h"
+
+#define verify(exp, fmt, args...) do { \
+    if ( !(exp) ) \
+        printf(fmt, ## args); \
+    assert(exp); \
+} while (0);
+
+/*
+ * Fail on the first error, since tests are dependent on each other.
+ */
+int main(int argc, char **argv)
+{
+    domid_t expected, allocated;
+
+    /* Test ID#0 cannot be allocated twice. */
+    allocated =3D domid_alloc(0);
+    verify(allocated =3D=3D 0,
+           "TEST 1: expected %u allocated %u\n", 0, allocated);
+    allocated =3D domid_alloc(0);
+    verify(allocated =3D=3D DOMID_INVALID,
+           "TEST 1: expected %u allocated %u\n", DOMID_INVALID, allocated)=
;
+
+    /* Ensure ID is not allocated. */
+    domid_free(0);
+
+    /*
+     * Test that that two consecutive calls of domid_alloc(DOMID_INVALID)
+     * will never return the same ID.
+     * NB: ID#0 is reserved and shall not be allocated by
+     * domid_alloc(DOMID_INVALID).
+     */
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(DOMID_INVALID);
+        verify(allocated =3D=3D expected,
+               "TEST 2: expected %u allocated %u\n", expected, allocated);
+    }
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(DOMID_INVALID);
+        verify(allocated =3D=3D DOMID_INVALID,
+               "TEST 3: expected %u allocated %u\n", DOMID_INVALID, alloca=
ted);
+    }
+
+    /* Re-allocate first ID from [1..DOMID_FIRST_RESERVED/2]. */
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED / 2; expected++ =
)
+        domid_free(expected);
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED / 2; expected++ =
)
+    {
+        allocated =3D domid_alloc(DOMID_INVALID);
+        verify(allocated =3D=3D expected,
+               "TEST 4: expected %u allocated %u\n", expected, allocated);
+    }
+
+    /* Re-allocate last ID from [1..DOMID_FIRST_RESERVED - 1]. */
+    expected =3D DOMID_FIRST_RESERVED - 1;
+    domid_free(DOMID_FIRST_RESERVED - 1);
+    allocated =3D domid_alloc(DOMID_INVALID);
+    verify(allocated =3D=3D expected,
+           "TEST 5: expected %u allocated %u\n", expected, allocated);
+
+    /* Allocate an invalid ID. */
+    expected =3D DOMID_INVALID;
+    allocated =3D domid_alloc(DOMID_FIRST_RESERVED);
+    verify(allocated =3D=3D expected,
+           "TEST 6: expected %u allocated %u\n", expected, allocated);
+
+    return 0;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/lib/find-next-bit.c b/xen/lib/find-next-bit.c
index 9b8d7814f20c..539c7f2022b0 100644
--- a/xen/lib/find-next-bit.c
+++ b/xen/lib/find-next-bit.c
@@ -8,8 +8,13 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
+
+#ifdef __XEN_TOOLS__
+#include 
+#else
 #include 
 #include 
+#endif
=20
 #define __ffs(x) (ffsl(x) - 1)
 #define ffz(x) __ffs(~(x))
--=20
2.34.1




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Date: Fri, 08 Aug 2025 02:20:10 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Alejandro Vallejo 
Subject: [PATCH v14 4/4] xen/domain: update create_dom0() messages
Message-ID: <20250808021938.669855-5-dmukhin@ford.com>
In-Reply-To: <20250808021938.669855-1-dmukhin@ford.com>
References: <20250808021938.669855-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Use %pd for domain identification in error/panic messages in create_dom0().

No functional change.

Signed-off-by: Denis Mukhin 
Reviewed-by: Alejandro Vallejo 
Acked-by: Jan Beulich 
---
Changes since v13:
- n/a
---
 xen/arch/arm/domain_build.c | 6 +++---
 xen/arch/x86/setup.c        | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 789f2b9d3ce7..02a15d160962 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2084,14 +2084,14 @@ void __init create_dom0(void)
         panic("Error creating domain 0 (rc =3D %ld)\n", PTR_ERR(dom0));
=20
     if ( llc_coloring_enabled && (rc =3D dom0_set_llc_colors(dom0)) )
-        panic("Error initializing LLC coloring for domain 0 (rc =3D %d)\n"=
, rc);
+        panic("Error initializing LLC coloring for %pd (rc =3D %d)\n", dom=
0, rc);
=20
     if ( vcpu_create(dom0, 0) =3D=3D NULL )
-        panic("Error creating domain 0 vcpu0\n");
+        panic("Error creating %pdv0\n", dom0);
=20
     rc =3D construct_dom0(dom0);
     if ( rc )
-        panic("Could not set up DOM0 guest OS (rc =3D %d)\n", rc);
+        panic("Could not set up %pd guest OS (rc =3D %d)\n", dom0, rc);
=20
     set_xs_domain(dom0);
 }
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 398da734c0c5..bf21c55f7193 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1084,7 +1084,7 @@ static struct domain *__init create_dom0(struct boot_=
info *bi)
=20
         if ( (strlen(acpi_param) =3D=3D 0) && acpi_disabled )
         {
-            printk("ACPI is disabled, notifying Domain 0 (acpi=3Doff)\n");
+            printk("ACPI is disabled, notifying %pd (acpi=3Doff)\n", d);
             safe_strcpy(acpi_param, "off");
         }
=20
@@ -1099,7 +1099,7 @@ static struct domain *__init create_dom0(struct boot_=
info *bi)
=20
     bd->d =3D d;
     if ( construct_dom0(bd) !=3D 0 )
-        panic("Could not construct domain 0\n");
+        panic("Could not construct %pd\n", d);
=20
     bd->cmdline =3D NULL;
     xfree(cmdline);
--=20
2.34.1




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Date: Thu, 7 Aug 2025 22:33:12 -0500
From: Aaron Rainbolt 
To: grub-devel@gnu.org, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 2/2] kern/xen: Add Xen command line parsing
Message-ID: <20250807223312.100a8ab4@kf-m2g5>
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On Mon, 4 Aug 2025 23:50:09 -0500
Aaron Rainbolt  wrote:

> Xen traditionally allows customizing guest behavior by passing
> arguments to the VM kernel via the kernel command line. This is no
> longer possible when using GRUB with Xen, as the kernel command line
> is decided by the GRUB configuration file within the guest, not data
> passed to the guest by Xen.
>=20
> To work around this limitation, enable GRUB to parse a command line
> passed to it by Xen, and expose data from the command line to the GRUB
> configuration as environment variables. These variables can be used in
> the GRUB configuration for any desired purpose, such as extending the
> kernel command line passed to the guest. The command line format is
> inspired by the Linux kernel's command line format.
>=20
> To reduce the risk of misuse, abuse, or accidents in production, the
> command line will only be parsed if it consists entirely of 7-bit
> ASCII characters, only alphabetical characters and underscores are
> permitted in variable names, and all variable names must start with
> the string "xen_grub_env_". This also allows room for expanding the
> command line arguments accepted by GRUB in the future, should other
> arguments end up becoming desirable in the future.

Darn. I sent this patch as a reply to the previous patch in the stack,
not as a reply to the cover letter. That's probably not the right way
to do things.

I should just set up git-send-email and stop trying to make Claws Mail
barely work for this kind of thing... Will resend the patch soon-ish,
this time formatted right (unless that would just cause needless noise).

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Date: Fri, 8 Aug 2025 08:04:10 +0200
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Subject: Re: Xen 4.21 Development Update [June-July]
To: Oleksii Kurochko 
Cc: Oleksii Moisieiev ,
 Ayan Kumar Halder ,
 Mykyta Poturai , Juergen Gross ,
 Teddy Astie ,
 Bertrand Marquis ,
 Luca Fancellu , "Jason Andryuk,"
 , Sergii Dmytruk ,
 "Penny Zheng," ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki=2C?=
 , Roger Pau Monne ,
 dmkhn@proton.me, Mykola Kvach ,
 "Daniel P. Smith" ,
 Grygorii Strashko ,
 Alejandro Vallejo ,
 Community Manager ,
 Xen-devel ,
 Andrew Cooper ,
 "committers@xenproject.org" 
References: 
 <242a93cf-20f7-4fcd-8eef-6945af5d864c@suse.com>
 <03a1d0b8-facd-4c02-97c6-45fa694da0b6@gmail.com>
 
 
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From: Jan Beulich 
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On 07.08.2025 18:20, Oleksii Kurochko wrote:
> 
> On 8/6/25 10:12 AM, Jan Beulich wrote:
>> On 06.08.2025 09:45, Oleksii Kurochko wrote:
>>> On 8/6/25 8:05 AM, Jan Beulich wrote:
>>>> Overall: There are very many items on this list, and it seems entirely clear to
>>>> me that not all of them will make it. I think it would be quite helpful to strip
>>>> down the set for 4.21 to some realistic subset. Maybe something to discuss on
>>>> the community call later today?
>>> Good point, lets discuss that tomorrow during the community call.
>> Oh, right, it's only Wednesday today.
> 
> I had the Xen Community Call marked at 6 PM in my calendar, so I missed it as
> it actually took place at 15:00... I'm not sure if a recording is available
> somewhere, but based on the notes:
>      Call for major work items for 4.21 or 4.22
>          Please make yourself known if you are intending to work on major items
>          PDX compression.
>          FRED, AVX10, APX, and AMX support (x86)
>          Host UEFI Secure Boot
>          FF-A 1.2 Support (Arm)
> 
> I completely agree with the first point — it would be great to receive feedback
> from the authors of major patch series, similar to how the team at EPAM does.
> 
> As for the other items, I assume this is a list of major work items that are
> likely to slip to 4.22, correct? From the looks of it, PDX compression and
> FRED-related work might still make it into 4.21.
> 
> I also wanted to ask this during the call, but since I missed it,
> I’ll ask here instead:
> What should be the criteria for continuing to track a patch series?
> It seems that the best approach would be to rely on feedback from the series'
> author. However, obtaining that feedback can be challenging. So perhaps the
> only practical solution is to keep tracking major items throughout the current
> release cycle and drop them at the start of the next cycle if no activity has
> taken place.
> 
> P.S.: Andrew, could you please provide a list for FRED connected patch series,
> I am tracking some of them, but wanted to be sure that I'm tracking all of them.

This is possibly one of the problems: The tracking is too fine-grained. I don't
think every little piece needs tracking throughout the entire dev cycle. Close
to relevant milestones, adding certain things (like bugfixes) that definitely
want to go in for the release may make sense. But prior to that I think it would
help if things were more coarse grained, and less focused on individual patches
or patch series. (Connecting the individual items with their series would of
course be a plus, but to allow having an overview the two aspects may want
separating.)

Jan


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Date: Fri, 8 Aug 2025 08:16:41 +0200
MIME-Version: 1.0
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Subject: Re: [PATCH 04/20] xen/arm: vIOMMU: add generic vIOMMU framework
To: Milan Djokic 
Cc: Rahul Singh ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "xen-devel@lists.xenproject.org" 
References: 
 <87b001cfc0555192435967b32190f75783ffa746.1754580688.git.milan_djokic@epam.com>
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On 07.08.2025 18:59, Milan Djokic wrote:
> --- a/xen/drivers/passthrough/Kconfig
> +++ b/xen/drivers/passthrough/Kconfig
> @@ -35,6 +35,12 @@ config IPMMU_VMSA
>  	  (H3 ES3.0, M3-W+, etc) or Gen4 SoCs which IPMMU hardware supports stage 2
>  	  translation table format and is able to use CPU's P2M table as is.
>  
> +config VIRTUAL_IOMMU
> +	bool "Virtual IOMMU Support (UNSUPPORTED)" if UNSUPPORTED
> +	default n

Nit: Please omit this redundant line.

Jan


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Subject: Re: [PATCH 07/20] xen/arm: vIOMMU: Add cmdline boot option "viommu =
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To: Milan Djokic 
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 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 07.08.2025 18:59, Milan Djokic wrote:
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -2058,6 +2058,13 @@ This option can be specified more than once (up to 8 times at present).
>  
>  Flag to enable or disable support for PCI passthrough
>  
> +### viommu (arm)
> +> `= `
> +
> +> Default: `false`
> +
> +Flag to enable or disable support for Virtual IOMMU for guests.

Isn't this too coarse-grained? IOW don't you want to specify the kind of IOMMU
to use, even if right now only one is being implemented? Also - why on the
command line? Isn't this rather a per-guest setting?

>  ### pcid (x86)
>  > `=  | xpti=`

Also, seeing this adjacent entry, you're inserting in the wrong place. The
options are supposed to be alphabetically sorted.

Jan


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 Bertrand Marquis ,
 Stefano Stabellini , Julien Grall ,
 Michal Orzel ,
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 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 07.08.2025 18:59, Milan Djokic wrote:
> --- a/xen/include/xen/iommu.h
> +++ b/xen/include/xen/iommu.h
> @@ -311,6 +311,15 @@ static inline int iommu_add_dt_pci_sideband_ids(struct pci_dev *pdev)
>  
>  #endif /* HAS_DEVICE_TREE_DISCOVERY */
>  
> +#ifdef CONFIG_ARM
> +struct iommu_guest_config {
> +    paddr_t     s1ctxptr;
> +    uint8_t     config;
> +    uint8_t     s1fmt;
> +    uint8_t     s1cdmax;
> +};
> +#endif /* CONFIG_ARM */

This looks like it should rather go into Arm's asm/iommu.h.

Jan


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Date: Fri, 8 Aug 2025 08:33:36 +0200
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Subject: Re: [PATCH v8 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
To: Mykola Kvach 
Cc: Mykola Kvach ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 xen-devel@lists.xenproject.org
References: 
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On 07.08.2025 21:39, Mykola Kvach wrote:
> From: Mykola Kvach 
> 
> This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPSCI
> (virtual PSCI) interface, allowing guests to request suspend via the PSCI
> v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).
> 
> The implementation:
> - Adds SYSTEM_SUSPEND function IDs to PSCI definitions
> - Implements trapping and handling of SYSTEM_SUSPEND in vPSCI
> - Allows only non-hardware domains to invoke SYSTEM_SUSPEND; for the
>   hardware domain, PSCI_NOT_SUPPORTED is returned to avoid halting the
>   system in hwdom_shutdown() called from domain_shutdown
> - Ensures all secondary VCPUs of the calling domain are offline before
>   allowing suspend due to PSCI spec
> 
> GIC and virtual timer context must be saved when the domain suspends.
> This is done by moving the respective code in ctxt_switch_from
> before the return that happens if the domain suspended.
> 
> Usage:
> 
> For Linux-based guests, suspend can be initiated with:
>     echo mem > /sys/power/state
> or via:
>     systemctl suspend
> 
> Resuming the guest is performed from control domain using:
>       xl resume 
> 
> Signed-off-by: Mykola Kvach 

Nothing is being said on why domain_resume_nopause() would be needed. While this
may be entirely obvious to Arm people, the change is done in common code.

> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -1343,16 +1343,13 @@ int domain_shutdown(struct domain *d, u8 reason)
>      return 0;
>  }
>  
> -void domain_resume(struct domain *d)
> +#ifndef CONFIG_ARM
> +static
> +#endif
> +void domain_resume_nopause(struct domain *d)
>  {
>      struct vcpu *v;
>  
> -    /*
> -     * Some code paths assume that shutdown status does not get reset under
> -     * their feet (e.g., some assertions make this assumption).
> -     */
> -    domain_pause(d);
> -
>      spin_lock(&d->shutdown_lock);
>  
>      d->is_shutting_down = d->is_shut_down = 0;
> @@ -1360,13 +1357,24 @@ void domain_resume(struct domain *d)
>  
>      for_each_vcpu ( d, v )
>      {
> +        clear_bit(_VPF_suspended, &v->pause_flags);

Similarly it's not becoming clear why unconditionally doing this here would
be correct (now and going forward). There are other calls to this function,
after all.

> --- a/xen/include/xen/sched.h
> +++ b/xen/include/xen/sched.h
> @@ -814,6 +814,9 @@ void domain_destroy(struct domain *d);
>  int domain_kill(struct domain *d);
>  int domain_shutdown(struct domain *d, u8 reason);
>  void domain_resume(struct domain *d);
> +#ifdef CONFIG_ARM
> +void domain_resume_nopause(struct domain *d);
> +#endif
>  
>  int domain_soft_reset(struct domain *d, bool resuming);
>  
> @@ -1010,6 +1013,9 @@ static inline struct domain *next_domain_in_cpupool(
>  /* VCPU is parked. */
>  #define _VPF_parked          8
>  #define VPF_parked           (1UL<<_VPF_parked)
> +/* VCPU is suspended. */
> +#define _VPF_suspended 9
> +#define VPF_suspended (1UL<<_VPF_suspended)

And then, even if it's "only" style: With how adjacent code is formatted,
how come there's no suitable blank padding here? If anything wants (and
really needs) doing differently from pre-existing code, then to have
blanks around the << as well.

Jan


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From: Jiqian Chen 
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	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v11 1/5] vpci: Use cleanup to free capability resource during deassign
Date: Fri, 8 Aug 2025 16:03:33 +0800
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As cleanup hook of all supported capabilities will be implemented in
follow-on changes, so to pre-call hook in vpci_deassign_device(), and
the capability specific clean open-code in there will be removed by
follow-on corresponding capability changes.

Since vpci_deassign_device() and vpci_init_capabilities() require
different cleanup actions, add a boolean parameter to cleanup hook
to distinguish them.

Signed-off-by: Jiqian Chen 
---
cc: "Roger Pau Monné" 
---
v10->v11 changes:
new patch.
---
 xen/drivers/vpci/vpci.c | 25 ++++++++++++++++++++++++-
 xen/include/xen/vpci.h  |  2 +-
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c
index fd02718b47ea..120a919f08e3 100644
--- a/xen/drivers/vpci/vpci.c
+++ b/xen/drivers/vpci/vpci.c
@@ -280,7 +280,7 @@ static int vpci_init_capabilities(struct pci_dev *pdev)
 
             if ( capability->cleanup )
             {
-                rc = capability->cleanup(pdev);
+                rc = capability->cleanup(pdev, true);
                 if ( rc )
                 {
                     printk(XENLOG_ERR "%pd %pp: clean %s cap %u fail rc=%d\n",
@@ -321,6 +321,29 @@ void vpci_deassign_device(struct pci_dev *pdev)
                     &pdev->domain->vpci_dev_assigned_map);
 #endif
 
+    for ( i = 0; i < NUM_VPCI_INIT; i++ )
+    {
+        const vpci_capability_t *capability = &__start_vpci_array[i];
+        const unsigned int cap = capability->id;
+        unsigned int pos = 0;
+
+        if ( !capability->cleanup )
+            continue;
+
+        if ( !capability->is_ext )
+            pos = pci_find_cap_offset(pdev->sbdf, cap);
+        else if ( is_hardware_domain(pdev->domain) )
+            pos = pci_find_ext_capability(pdev->sbdf, cap);
+        if ( pos )
+        {
+            int rc = capability->cleanup(pdev, false);
+            if ( rc )
+                printk(XENLOG_ERR "%pd %pp: clean %s cap %u fail rc=%d\n",
+                       pdev->domain, &pdev->sbdf,
+                       capability->is_ext ? "extended" : "legacy", cap, rc);
+        }
+    }
+
     spin_lock(&pdev->vpci->lock);
     while ( !list_empty(&pdev->vpci->handlers) )
     {
diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h
index 17cfecb0aabf..4b7b9298c4e8 100644
--- a/xen/include/xen/vpci.h
+++ b/xen/include/xen/vpci.h
@@ -17,7 +17,7 @@ typedef struct {
     unsigned int id;
     bool is_ext;
     int (* init)(struct pci_dev *pdev);
-    int (* cleanup)(const struct pci_dev *pdev);
+    int (* cleanup)(const struct pci_dev *pdev, bool hide);
 } vpci_capability_t;
 
 #define VPCI_ECAM_BDF(addr)     (((addr) & 0x0ffff000) >> 12)
-- 
2.34.1



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From: Jiqian Chen 
To: 
CC: Huang Rui , Jiqian Chen ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v11 3/5] vpci/rebar: Implement cleanup function for Rebar
Date: Fri, 8 Aug 2025 16:03:35 +0800
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When Rebar initialization fails, vPCI hides the capability, but
removing handlers and datas won't be performed until the device is
deassigned. So, implement Rebar cleanup hook that will be called to
cleanup Rebar related handlers and free it's associated data when
initialization fails.

Signed-off-by: Jiqian Chen 
---
cc: "Roger Pau Monné" 
---
v10->v11 changes:
* Add ASSERT_UNREACHABLE() when vpci_remove_registers() fails
* When hide == true, add handlers to let Rebar ctrl be RO.
* Remove Roger's Reviewed-by since patch change.

v9->v10 changes:
v8->v9 changes:
No.

v7->v8 changes:
* Add Roger's Reviewed-by.

v6->v7 changes:
* Change the pointer parameter of cleanup_rebar() to be const.
* Print error when vpci_remove_registers() fail in cleanup_rebar().

v5->v6 changes:
No.

v4->v5 changes:
* Change definition "static void cleanup_rebar" to "static int cf_check cleanup_rebar" since cleanup hook is changed to be int.

v3->v4 changes:
* Change function name from fini_rebar() to cleanup_rebar().
* Change the error number to be E2BIG and ENXIO in init_rebar().

v2->v3 changes:
* Use fini_rebar() to remove all register instead of in the failure path of init_rebar();

v1->v2 changes:
* Called vpci_remove_registers() to remove all possible registered registers instead of using a array to record all registered register.

Best regards,
Jiqian Chen.
---
 xen/drivers/vpci/rebar.c | 66 +++++++++++++++++++++++++++++++++-------
 1 file changed, 55 insertions(+), 11 deletions(-)

diff --git a/xen/drivers/vpci/rebar.c b/xen/drivers/vpci/rebar.c
index 3c18792d9bcd..91d5369d75e2 100644
--- a/xen/drivers/vpci/rebar.c
+++ b/xen/drivers/vpci/rebar.c
@@ -49,6 +49,57 @@ static void cf_check rebar_ctrl_write(const struct pci_dev *pdev,
     bar->guest_addr = bar->addr;
 }
 
+static int cf_check cleanup_rebar(const struct pci_dev *pdev, bool hide)
+{
+    int rc;
+    uint32_t ctrl;
+    unsigned int nbars;
+    unsigned int rebar_offset = pci_find_ext_capability(pdev->sbdf,
+                                                        PCI_EXT_CAP_ID_REBAR);
+
+    if ( !rebar_offset || !is_hardware_domain(pdev->domain) )
+    {
+        ASSERT_UNREACHABLE();
+        return 0;
+    }
+
+    ctrl = pci_conf_read32(pdev->sbdf, rebar_offset + PCI_REBAR_CTRL(0));
+    nbars = MASK_EXTR(ctrl, PCI_REBAR_CTRL_NBAR_MASK);
+
+    rc = vpci_remove_registers(pdev->vpci, rebar_offset + PCI_REBAR_CAP(0),
+                               PCI_REBAR_CTRL(nbars - 1));
+    if ( rc )
+    {
+        printk(XENLOG_ERR "%pd %pp: fail to remove Rebar handlers rc=%d\n",
+               pdev->domain, &pdev->sbdf, rc);
+        ASSERT_UNREACHABLE();
+        return rc;
+    }
+
+    if ( !hide )
+        return 0;
+
+    /*
+     * The driver may not traverse the capability list and think device
+     * supports Rebar by default. So here let the control register of Rebar
+     * be Read-Only is to ensure Rebar disabled.
+     */
+    for ( unsigned int i = 0; i < nbars; i++ )
+    {
+        rc = vpci_add_register(pdev->vpci, vpci_hw_read32, NULL,
+                               rebar_offset + PCI_REBAR_CTRL(i), 4, NULL);
+        if ( rc )
+        {
+            printk(XENLOG_ERR
+                   "%pd %pp: fail to add Rebar ctrl handler rc=%d\n",
+                   pdev->domain, &pdev->sbdf, rc);
+            return rc;
+        }
+    }
+
+    return 0;
+}
+
 static int cf_check init_rebar(struct pci_dev *pdev)
 {
     uint32_t ctrl;
@@ -80,7 +131,7 @@ static int cf_check init_rebar(struct pci_dev *pdev)
         {
             printk(XENLOG_ERR "%pd %pp: too big BAR number %u in REBAR_CTRL\n",
                    pdev->domain, &pdev->sbdf, index);
-            continue;
+            return -E2BIG;
         }
 
         bar = &pdev->vpci->header.bars[index];
@@ -88,7 +139,7 @@ static int cf_check init_rebar(struct pci_dev *pdev)
         {
             printk(XENLOG_ERR "%pd %pp: BAR%u is not in memory space\n",
                    pdev->domain, &pdev->sbdf, index);
-            continue;
+            return -ENXIO;
         }
 
         rc = vpci_add_register(pdev->vpci, vpci_hw_read32, rebar_ctrl_write,
@@ -97,14 +148,7 @@ static int cf_check init_rebar(struct pci_dev *pdev)
         {
             printk(XENLOG_ERR "%pd %pp: BAR%u fail to add reg of REBAR_CTRL rc=%d\n",
                    pdev->domain, &pdev->sbdf, index, rc);
-            /*
-             * Ideally we would hide the ReBar capability on error, but code
-             * for doing so still needs to be written. Use continue instead
-             * to keep any already setup register hooks, as returning an
-             * error will cause the hardware domain to get unmediated access
-             * to all device registers.
-             */
-            continue;
+            return rc;
         }
 
         bar->resizable_sizes =
@@ -118,7 +162,7 @@ static int cf_check init_rebar(struct pci_dev *pdev)
 
     return 0;
 }
-REGISTER_VPCI_EXTCAP(REBAR, init_rebar, NULL);
+REGISTER_VPCI_EXTCAP(REBAR, init_rebar, cleanup_rebar);
 
 /*
  * Local variables:
-- 
2.34.1



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From: Jiqian Chen 
To: 
CC: Huang Rui , Jiqian Chen ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD
	
Subject: [PATCH v11 0/5] Support hiding capability when its initialization fails
Date: Fri, 8 Aug 2025 16:03:32 +0800
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Hi,

This series is to
emulate extended capability list for dom0;
hide legacy and extended capability when its initialization fails;
above two parts had been merged.
remove all related registers and other resources when initializing capability fails, including patch #1, #2, #3, #4, #5.

Best regards,
Jiqian Chen.
---
cc: "Roger Pau Monné" 
cc: Anthony PERARD 
---
Jiqian Chen (5):
  vpci: Use cleanup to free capability resource during deassign
  vpci: Refactor vpci_remove_register to remove matched registers
  vpci/rebar: Implement cleanup function for Rebar
  vpci/msi: Implement cleanup function for MSI
  vpci/msix: Implement cleanup function for MSI-X

 tools/tests/vpci/main.c  |  8 ++---
 xen/drivers/vpci/msi.c   | 49 ++++++++++++++++++++++++++-
 xen/drivers/vpci/msix.c  | 47 +++++++++++++++++++++++++-
 xen/drivers/vpci/rebar.c | 66 ++++++++++++++++++++++++++++++------
 xen/drivers/vpci/vpci.c  | 72 ++++++++++++++++++++++++----------------
 xen/include/xen/vpci.h   |  6 ++--
 6 files changed, 200 insertions(+), 48 deletions(-)

-- 
2.34.1



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From: Jiqian Chen 
To: 
CC: Huang Rui , Jiqian Chen ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v11 4/5] vpci/msi: Implement cleanup function for MSI
Date: Fri, 8 Aug 2025 16:03:36 +0800
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When MSI initialization fails, vPCI hides the capability, but
removing handlers and datas won't be performed until the device is
deassigned. So, implement MSI cleanup hook that will be called to
cleanup MSI related handlers and free it's associated data when
initialization fails.

Since cleanup function of MSI is implemented, delete the open-code
in vpci_deassign_device().

Signed-off-by: Jiqian Chen 
---
cc: "Roger Pau Monné" 
---
v10->v11 changes:
* Add hide paratemer to cleanup_msi().
* Check hide, if false return directly instead of letting ctrl RO.
* Delete xfree(pdev->vpci->msi); in vpci_deassign_device().
* Remove Roger's Reviewed-by since patch change.

v9->v10 changes:
No.

v8->v9 changes:
* Add Roger's Reviewed-by.

v7->v8 changes:
* Add a comment to describe why "-2" in cleanup_msi().
* Given the code in vpci_remove_registers() an error in the removal of
  registers would likely imply memory corruption, at which point it's
  best to fully disable the device. So, Rollback the last two modifications of v7.

v6->v7 changes:
* Change the pointer parameter of cleanup_msi() to be const.
* When vpci_remove_registers() in cleanup_msi() fails, not to return
  directly, instead try to free msi and re-add ctrl handler.
* Pass pdev->vpci into vpci_add_register() instead of pdev->vpci->msi in
  init_msi() since we need that every handler realize that msi is NULL
  when msi is free but handlers are still in there.

v5->v6 changes:
No.

v4->v5 changes:
* Change definition "static void cleanup_msi" to "static int cf_check cleanup_msi"
  since cleanup hook is changed to be int.
* Add a read-only register for MSI Control Register in the end of cleanup_msi.

v3->v4 changes:
* Change function name from fini_msi() to cleanup_msi().
* Remove unnecessary comment.
* Change to use XFREE to free vpci->msi.

v2->v3 changes:
* Remove all fail path, and use fini_msi() hook instead.
* Change the method to calculating the size of msi registers.

v1->v2 changes:
* Added a new function fini_msi to free all MSI resources instead of using an array
  to record registered registers.

Best regards,
Jiqian Chen.
---
 xen/drivers/vpci/msi.c  | 49 ++++++++++++++++++++++++++++++++++++++++-
 xen/drivers/vpci/vpci.c |  1 -
 2 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c
index c3eba4e14870..6ab45b9ba655 100644
--- a/xen/drivers/vpci/msi.c
+++ b/xen/drivers/vpci/msi.c
@@ -193,6 +193,53 @@ static void cf_check mask_write(
     msi->mask = val;
 }
 
+static int cf_check cleanup_msi(const struct pci_dev *pdev, bool hide)
+{
+    int rc;
+    unsigned int end;
+    struct vpci *vpci = pdev->vpci;
+    const unsigned int msi_pos = pdev->msi_pos;
+    const unsigned int ctrl = msi_control_reg(msi_pos);
+
+    if ( !msi_pos || !vpci->msi )
+        return 0;
+
+    if ( vpci->msi->masking )
+        end = msi_pending_bits_reg(msi_pos, vpci->msi->address64);
+    else
+        /*
+         * "-2" here is to cut the reserved 2 bytes of Message Data when
+         * there is no masking support.
+         */
+        end = msi_mask_bits_reg(msi_pos, vpci->msi->address64) - 2;
+
+    rc = vpci_remove_registers(vpci, ctrl, end - ctrl);
+    if ( rc )
+    {
+        printk(XENLOG_ERR "%pd %pp: fail to remove MSI handlers rc=%d\n",
+               pdev->domain, &pdev->sbdf, rc);
+        ASSERT_UNREACHABLE();
+        return rc;
+    }
+
+    XFREE(vpci->msi);
+
+    if ( !hide )
+        return 0;
+
+    /*
+     * The driver may not traverse the capability list and think device
+     * supports MSI by default. So here let the control register of MSI
+     * be Read-Only is to ensure MSI disabled.
+     */
+    rc = vpci_add_register(vpci, vpci_hw_read16, NULL, ctrl, 2, NULL);
+    if ( rc )
+        printk(XENLOG_ERR "%pd %pp: fail to add MSI ctrl handler rc=%d\n",
+               pdev->domain, &pdev->sbdf, rc);
+
+    return rc;
+}
+
 static int cf_check init_msi(struct pci_dev *pdev)
 {
     unsigned int pos = pdev->msi_pos;
@@ -270,7 +317,7 @@ static int cf_check init_msi(struct pci_dev *pdev)
 
     return 0;
 }
-REGISTER_VPCI_CAP(MSI, init_msi, NULL);
+REGISTER_VPCI_CAP(MSI, init_msi, cleanup_msi);
 
 void vpci_dump_msi(void)
 {
diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c
index 6ecb70052b93..3122847524d2 100644
--- a/xen/drivers/vpci/vpci.c
+++ b/xen/drivers/vpci/vpci.c
@@ -367,7 +367,6 @@ void vpci_deassign_device(struct pci_dev *pdev)
         rangeset_destroy(pdev->vpci->header.bars[i].mem);
 
     xfree(pdev->vpci->msix);
-    xfree(pdev->vpci->msi);
     xfree(pdev->vpci);
     pdev->vpci = NULL;
 }
-- 
2.34.1



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From: Jiqian Chen 
To: 
CC: Huang Rui , Jiqian Chen ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD
	
Subject: [PATCH v11 2/5] vpci: Refactor vpci_remove_register to remove matched registers
Date: Fri, 8 Aug 2025 16:03:34 +0800
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vpci_remove_register() only supports removing a register in a time,
but the follow-on changes need to remove all registers within a range.
So, refactor it to support removing all registers in a given region.

And it is no issue to remove a non exist register, so remove the
__must_check prefix.

Note: two test cases don't math the new logic of
vpci_remove_registers(), then modify them.

Signed-off-by: Jiqian Chen 
---
cc: "Roger Pau Monné" 
cc: Anthony PERARD 
---
v10->v11 changes:
No.

v9->v10 changes:
* Since logic change of vpci_remove_registers() affect the test cases of
  tools/tests/vpci/main.c, change them to match the new function logic.
* Remove Roger's Reviewed-by since patch changed.

v8->v9 changes:
v7->v8 changes:
v6->v7 changes:
No.

v5->v6 changes:
* Modify commit message.
* Add Roger's Reviewed-by.

v4->v5 changes:
No.

v3->v4 changes:
* Use list_for_each_entry_safe instead of list_for_each_entry.
* Return ERANGE if overlap.

v2->v3 changes:
* Add new check to return error if registers overlap but not inside range.

v1->v2 changes:
new patch

Best regards,
Jiqian Chen.
---
 tools/tests/vpci/main.c |  8 ++++----
 xen/drivers/vpci/vpci.c | 38 ++++++++++++++++++++------------------
 xen/include/xen/vpci.h  |  4 ++--
 3 files changed, 26 insertions(+), 24 deletions(-)

diff --git a/tools/tests/vpci/main.c b/tools/tests/vpci/main.c
index 33223db3eb77..2ef8d4e03f1d 100644
--- a/tools/tests/vpci/main.c
+++ b/tools/tests/vpci/main.c
@@ -132,10 +132,10 @@ static void vpci_write32_mask(const struct pci_dev *pdev, unsigned int reg,
                                   rsvdz_mask))
 
 #define VPCI_REMOVE_REG(off, size)                                          \
-    assert(!vpci_remove_register(test_pdev.vpci, off, size))
+    assert(!vpci_remove_registers(test_pdev.vpci, off, size))
 
 #define VPCI_REMOVE_INVALID_REG(off, size)                                  \
-    assert(vpci_remove_register(test_pdev.vpci, off, size))
+    assert(vpci_remove_registers(test_pdev.vpci, off, size))
 
 /* Read a 32b register using all possible sizes. */
 void multiread4_check(unsigned int reg, uint32_t val)
@@ -402,10 +402,10 @@ main(int argc, char **argv)
     VPCI_REMOVE_REG(28, 1);
     VPCI_REMOVE_REG(24, 4);
     VPCI_REMOVE_REG(12, 2);
+    VPCI_REMOVE_REG(16, 2);
+    VPCI_REMOVE_REG(30, 2);
 
     VPCI_REMOVE_INVALID_REG(20, 1);
-    VPCI_REMOVE_INVALID_REG(16, 2);
-    VPCI_REMOVE_INVALID_REG(30, 2);
 
     return 0;
 }
diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c
index 120a919f08e3..6ecb70052b93 100644
--- a/xen/drivers/vpci/vpci.c
+++ b/xen/drivers/vpci/vpci.c
@@ -152,7 +152,7 @@ static int vpci_capability_hide(const struct pci_dev *pdev, unsigned int cap)
 
     prev_r->private = next_r->private;
     /*
-     * Not calling vpci_remove_register() here is to avoid redoing
+     * Not calling vpci_remove_registers() here is to avoid redoing
      * the register search.
      */
     list_del(&next_r->node);
@@ -160,7 +160,7 @@ static int vpci_capability_hide(const struct pci_dev *pdev, unsigned int cap)
     xfree(next_r);
 
     if ( !is_hardware_domain(pdev->domain) )
-        return vpci_remove_register(vpci, offset + PCI_CAP_LIST_ID, 1);
+        return vpci_remove_registers(vpci, offset + PCI_CAP_LIST_ID, 1);
 
     return 0;
 }
@@ -572,34 +572,36 @@ int vpci_add_register_mask(struct vpci *vpci, vpci_read_t *read_handler,
     return 0;
 }
 
-int vpci_remove_register(struct vpci *vpci, unsigned int offset,
-                         unsigned int size)
+int vpci_remove_registers(struct vpci *vpci, unsigned int start,
+                          unsigned int size)
 {
-    const struct vpci_register r = { .offset = offset, .size = size };
-    struct vpci_register *rm;
+    struct vpci_register *rm, *tmp;
+    unsigned int end = start + size;
 
     spin_lock(&vpci->lock);
-    list_for_each_entry ( rm, &vpci->handlers, node )
+    list_for_each_entry_safe ( rm, tmp, &vpci->handlers, node )
     {
-        int cmp = vpci_register_cmp(&r, rm);
-
-        /*
-         * NB: do not use a switch so that we can use break to
-         * get out of the list loop earlier if required.
-         */
-        if ( !cmp && rm->offset == offset && rm->size == size )
+        /* Remove rm if rm is inside the range. */
+        if ( rm->offset >= start && rm->offset + rm->size <= end )
         {
             list_del(&rm->node);
-            spin_unlock(&vpci->lock);
             xfree(rm);
-            return 0;
+            continue;
         }
-        if ( cmp <= 0 )
+
+        /* Return error if registers overlap but not inside. */
+        if ( rm->offset + rm->size > start && rm->offset < end )
+        {
+            spin_unlock(&vpci->lock);
+            return -ERANGE;
+        }
+
+        if ( start < rm->offset )
             break;
     }
     spin_unlock(&vpci->lock);
 
-    return -ENOENT;
+    return 0;
 }
 
 /* Wrappers for performing reads/writes to the underlying hardware. */
diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h
index 4b7b9298c4e8..9ae75d946af4 100644
--- a/xen/include/xen/vpci.h
+++ b/xen/include/xen/vpci.h
@@ -70,8 +70,8 @@ static inline int __must_check vpci_add_register(struct vpci *vpci,
                                   size, data, 0, 0, 0, 0);
 }
 
-int __must_check vpci_remove_register(struct vpci *vpci, unsigned int offset,
-                                      unsigned int size);
+int vpci_remove_registers(struct vpci *vpci, unsigned int start,
+                          unsigned int size);
 
 /* Generic read/write handlers for the PCI config space. */
 uint32_t vpci_read(pci_sbdf_t sbdf, unsigned int reg, unsigned int size);
-- 
2.34.1



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From: Jiqian Chen 
To: 
CC: Huang Rui , Jiqian Chen ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v11 5/5] vpci/msix: Implement cleanup function for MSI-X
Date: Fri, 8 Aug 2025 16:03:37 +0800
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When MSI-X initialization fails, vPCI hides the capability, but
removing handlers and datas won't be performed until the device is
deassigned. So, implement MSI-X cleanup hook that will be called
to cleanup MSI-X related handlers and free it's associated data when
initialization fails.

Since cleanup function of MSI-X is implemented, delete the open-code
in vpci_deassign_device().

Signed-off-by: Jiqian Chen 
---
cc: "Roger Pau Monné" 
---
v10->v11 changes:
* Move calling all cleanup hook in vpci_deassign_device() out of this patch.
* Add hide parameter to cleanup_msix().
* Check hide, if it is false, return directly instead of letting ctrl RO.

v9->v10 changes:
* Call all cleanup hook in vpci_deassign_device() instead of cleanup_msix().

v8->v9 changes:
* Modify commit message.
* Call cleanup_msix() in vpci_deassign_device() to remove the open-code to cleanup msix datas.
* In cleanup_msix(), move "list_del(&vpci->msix->next);" above for loop of iounmap msix tables.

v7->v8 changes:
* Given the code in vpci_remove_registers() an error in the removal of
  registers would likely imply memory corruption, at which point it's
  best to fully disable the device. So, Rollback the last two modifications of v7.

v6->v7 changes:
* Change the pointer parameter of cleanup_msix() to be const.
* When vpci_remove_registers() in cleanup_msix() fails, not to return
  directly, instead try to free msix and re-add ctrl handler.
* Pass pdev->vpci into vpci_add_register() instead of pdev->vpci->msix in
  init_msix() since we need that every handler realize that msix is NULL
  when msix is freed but handlers are still in there.

v5->v6 changes:
* Change the logic to add dummy handler when !vpci->msix in cleanup_msix().

v4->v5 changes:
* Change definition "static void cleanup_msix" to "static int cf_check cleanup_msix"
  since cleanup hook is changed to be int.
* Add a read-only register for MSIX Control Register in the end of cleanup_msix().

v3->v4 changes:
* Change function name from fini_msix() to cleanup_msix().
* Change to use XFREE to free vpci->msix.
* In cleanup function, change the sequence of check and remove action according to
  init_msix().

v2->v3 changes:
* Remove unnecessary clean operations in fini_msix().

v1->v2 changes:
new patch.

Best regards,
Jiqian Chen.
---
 xen/drivers/vpci/msix.c | 47 ++++++++++++++++++++++++++++++++++++++++-
 xen/drivers/vpci/vpci.c |  8 -------
 2 files changed, 46 insertions(+), 9 deletions(-)

diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c
index 54a5070733aa..287aafda9157 100644
--- a/xen/drivers/vpci/msix.c
+++ b/xen/drivers/vpci/msix.c
@@ -655,6 +655,51 @@ int vpci_make_msix_hole(const struct pci_dev *pdev)
     return 0;
 }
 
+static int cf_check cleanup_msix(const struct pci_dev *pdev, bool hide)
+{
+    int rc;
+    struct vpci *vpci = pdev->vpci;
+    const unsigned int msix_pos = pdev->msix_pos;
+
+    if ( !msix_pos )
+        return 0;
+
+    rc = vpci_remove_registers(vpci, msix_control_reg(msix_pos), 2);
+    if ( rc )
+    {
+        printk(XENLOG_ERR "%pd %pp: fail to remove MSIX handlers rc=%d\n",
+               pdev->domain, &pdev->sbdf, rc);
+        ASSERT_UNREACHABLE();
+        return rc;
+    }
+
+    if ( vpci->msix )
+    {
+        list_del(&vpci->msix->next);
+        for ( unsigned int i = 0; i < ARRAY_SIZE(vpci->msix->table); i++ )
+            if ( vpci->msix->table[i] )
+                iounmap(vpci->msix->table[i]);
+
+        XFREE(vpci->msix);
+    }
+
+    if ( !hide )
+        return 0;
+
+    /*
+     * The driver may not traverse the capability list and think device
+     * supports MSIX by default. So here let the control register of MSIX
+     * be Read-Only is to ensure MSIX disabled.
+     */
+    rc = vpci_add_register(vpci, vpci_hw_read16, NULL,
+                           msix_control_reg(msix_pos), 2, NULL);
+    if ( rc )
+        printk(XENLOG_ERR "%pd %pp: fail to add MSIX ctrl handler rc=%d\n",
+               pdev->domain, &pdev->sbdf, rc);
+
+    return rc;
+}
+
 static int cf_check init_msix(struct pci_dev *pdev)
 {
     struct domain *d = pdev->domain;
@@ -710,7 +755,7 @@ static int cf_check init_msix(struct pci_dev *pdev)
      */
     return vpci_make_msix_hole(pdev);
 }
-REGISTER_VPCI_CAP(MSIX, init_msix, NULL);
+REGISTER_VPCI_CAP(MSIX, init_msix, cleanup_msix);
 
 /*
  * Local variables:
diff --git a/xen/drivers/vpci/vpci.c b/xen/drivers/vpci/vpci.c
index 3122847524d2..394d75490db9 100644
--- a/xen/drivers/vpci/vpci.c
+++ b/xen/drivers/vpci/vpci.c
@@ -355,18 +355,10 @@ void vpci_deassign_device(struct pci_dev *pdev)
         xfree(r);
     }
     spin_unlock(&pdev->vpci->lock);
-    if ( pdev->vpci->msix )
-    {
-        list_del(&pdev->vpci->msix->next);
-        for ( i = 0; i < ARRAY_SIZE(pdev->vpci->msix->table); i++ )
-            if ( pdev->vpci->msix->table[i] )
-                iounmap(pdev->vpci->msix->table[i]);
-    }
 
     for ( i = 0; i < ARRAY_SIZE(pdev->vpci->header.bars); i++ )
         rangeset_destroy(pdev->vpci->header.bars[i].mem);
 
-    xfree(pdev->vpci->msix);
     xfree(pdev->vpci);
     pdev->vpci = NULL;
 }
-- 
2.34.1



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Subject: Re: [PATCH v11 1/5] vpci: Use cleanup to free capability resource
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To: Jiqian Chen 
Cc: Huang Rui , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , xen-devel@lists.xenproject.org
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On 08.08.2025 10:03, Jiqian Chen wrote:
> @@ -321,6 +321,29 @@ void vpci_deassign_device(struct pci_dev *pdev)
>                      &pdev->domain->vpci_dev_assigned_map);
>  #endif
>  
> +    for ( i = 0; i < NUM_VPCI_INIT; i++ )
> +    {
> +        const vpci_capability_t *capability = &__start_vpci_array[i];
> +        const unsigned int cap = capability->id;
> +        unsigned int pos = 0;
> +
> +        if ( !capability->cleanup )
> +            continue;
> +
> +        if ( !capability->is_ext )
> +            pos = pci_find_cap_offset(pdev->sbdf, cap);
> +        else if ( is_hardware_domain(pdev->domain) )
> +            pos = pci_find_ext_capability(pdev->sbdf, cap);
> +        if ( pos )
> +        {
> +            int rc = capability->cleanup(pdev, false);
> +            if ( rc )

Nit: Blank line between declaration(s) and statement(s) please. (Likely
easy enough to adjust while committing, if no other need for a v12
arises.)

Jan


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Subject: Re: [PATCH v3 06/20] xen/riscv: add root page table allocation
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <23c79f07221dee7eb782ebb160442f3a796a41b2.1753973161.git.oleksii.kurochko@gmail.com>
 <7491c934-f847-4fe2-9d9b-a500f0888198@suse.com>
 
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From: Oleksii Kurochko 
In-Reply-To: <2aa2135f-e422-417f-a509-74f61c3b19de@suse.com>

This is a multi-part message in MIME format.
--------------t95ZBYk0mol7q0a0O8M8qfXE
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On 8/7/25 5:57 PM, Jan Beulich wrote:
> On 07.08.2025 15:35, Oleksii Kurochko wrote:
>> On 8/5/25 12:43 PM, Jan Beulich wrote:
>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>> +static int p2m_alloc_root_table(struct p2m_domain *p2m)
>>>> +{
>>>> +    struct domain *d = p2m->domain;
>>>> +    struct page_info *page;
>>>> +    const unsigned int nr_root_pages = P2M_ROOT_PAGES;
>>>> +
>>>> +    /*
>>>> +     * Return back nr_root_pages to assure the root table memory is also
>>>> +     * accounted against the P2M pool of the domain.
>>>> +     */
>>>> +    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
>>>> +        return -ENOMEM;
>>>> +
>>>> +    page = p2m_allocate_root(d);
>>>> +    if ( !page )
>>>> +        return -ENOMEM;
>>>> +
>>>> +    p2m->root = page;
>>>> +
>>>> +    return 0;
>>>> +}
>>> In the success case, shouldn't you bump the paging pool's total_pages by
>>> P2M_ROOT_PAGES? (As the freeing side is missing so far, it's not easy to
>>> tell whether there's [going to be] a balancing problem in the long run.
>>> In the short run there certainly is.)
>> I think that total_pages should be updated only in case when page is added
>> to freelist.
>> In the case of p2m root table, we just returning some pages to domheap and
>> durint that decreasing an amount of total_pages as freelist has lesser pages,
>> and then just allocate pages from domheap without adding them to freelist.
> But how's freeing of a root table going to look like?

We have saved pointer to first page of P2M_ROOT_PAGES allocated for root page
table which is stored in p2m->root. Then when a domain is going to be destroyed,
then do something like:
     for ( i = 0; i < P2M_ROOT_PAGES; i++ )
         clear_and_clean_page(p2m->root + i);
...


> Logically that group
> of 4 pages would be put back into the pool. And from that the pool's
> total_pages should reflect that right after successful allocation.

... I think instead of having the loop mentioned above we could add root table
pages to p2m->pages (as you suggested) in p2m_allocate_root() and then a domain
is being destroyed just do the following:
   while ( (pg = page_list_remove_head(&p2m->pages)) )
   {
       p2m_free_page(p2m->domain, pg);
And it will be a job of internals of p2m_free_page() -> paging_free_page() to
adjust freelist's total_pages and return back page(s) allocated for root table
to the freelist. (Note: the current implementation of paging_free_page() just
add a page to freelist without updating of freelist's total_pages what looks
incorrect. And it will be enough as total_pages is present only for freelist
and there is not separate total_pages (or something similar) for p2m->pages).

~ Oleksii

--------------t95ZBYk0mol7q0a0O8M8qfXE
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    On 8/7/25 5:57 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 07.08.2025 15:35, Oleksii Kurochko wrote:

    
      
    
        
    On 8/5/25 12:43 PM, Jan Beulich wrote:

    
        
    
          
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
          
    
            
    +static int p2m_alloc_root_table(struct p2m_domain *p2m)
+{
+    struct domain *d = p2m->domain;
+    struct page_info *page;
+    const unsigned int nr_root_pages = P2M_ROOT_PAGES;
+
+    /*
+     * Return back nr_root_pages to assure the root table memory is also
+     * accounted against the P2M pool of the domain.
+     */
+    if ( !paging_ret_pages_to_domheap(d, nr_root_pages) )
+        return -ENOMEM;
+
+    page = p2m_allocate_root(d);
+    if ( !page )
+        return -ENOMEM;
+
+    p2m->root = page;
+
+    return 0;
+}

    
          
    
          
    In the success case, shouldn't you bump the paging pool's total_pages by
P2M_ROOT_PAGES? (As the freeing side is missing so far, it's not easy to
tell whether there's [going to be] a balancing problem in the long run.
In the short run there certainly is.)

    
        
    
        
    I think that total_pages should be updated only in case when page is added
to freelist.
In the case of p2m root table, we just returning some pages to domheap and
durint that decreasing an amount of total_pages as freelist has lesser pages,
and then just allocate pages from domheap without adding them to freelist.

    
      
    
      
    But how's freeing of a root table going to look like? 
    
    
    
    
    We have saved pointer to first page of P2M_ROOT_PAGES allocated for root page
table which is stored in p2m->root. Then when a domain is going to be destroyed,
then do something like:
    for ( i = 0; i < P2M_ROOT_PAGES; i++ )
        clear_and_clean_page(p2m->root + i);
...

    
    

    
    
    
    
    
      
    Logically that group
of 4 pages would be put back into the pool. And from that the pool's
total_pages should reflect that right after successful allocation.
    
    
    
    
    ... I think instead of having the loop mentioned above we could add root table
pages to p2m->pages (as you suggested) in p2m_allocate_root() and then a domain
is being destroyed just do the following:
  while ( (pg = page_list_remove_head(&p2m->pages)) )
  {
      p2m_free_page(p2m->domain, pg);
And it will be a job of internals of p2m_free_page() -> paging_free_page() to
adjust freelist's total_pages and return back page(s) allocated for root table
to the freelist. (Note: the current implementation of paging_free_page() just
add a page to freelist without updating of freelist's total_pages what looks
incorrect. And it will be enough as total_pages is present only for freelist
and there is not separate total_pages (or something similar) for p2m->pages).

~ Oleksii
    
  


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Date: Fri, 8 Aug 2025 11:16:56 +0200
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Subject: Re: [PATCH v3 10/20] xen/riscv: introduce
 page_{get,set}_xenheap_gfn()
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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From: Oleksii Kurochko 
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On 8/5/25 4:11 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> --- a/xen/arch/riscv/include/asm/mm.h
>> +++ b/xen/arch/riscv/include/asm/mm.h
>> @@ -12,6 +12,7 @@
>>   #include 
>>   #include 
>>   
>> +#include 
>>   #include 
>>   #include 
>>   
>> @@ -247,9 +248,17 @@ static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long nr)
>>   #define PGT_writable_page PG_mask(1, 1)  /* has writable mappings?         */
>>   #define PGT_type_mask     PG_mask(1, 1)  /* Bits 31 or 63.                 */
>>   
>> -/* Count of uses of this frame as its current type. */
>> -#define PGT_count_width   PG_shift(2)
>> -#define PGT_count_mask    ((1UL << PGT_count_width) - 1)
>> + /* 9-bit count of uses of this frame as its current type. */
> Nit: Stray blank at start of line.
>
>> +#define PGT_count_mask    PG_mask(0x3FF, 10)
> A 9-bit count corresponds to a mask of 0x1ff, doesn't it? With 0x3ff the count
> can spill over the type.

It should be really 0x1ff, thanks.

~ Oleksii

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    On 8/5/25 4:11 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    --- a/xen/arch/riscv/include/asm/mm.h
+++ b/xen/arch/riscv/include/asm/mm.h
@@ -12,6 +12,7 @@
 #include <xen/sections.h>
 #include <xen/types.h>
 
+#include <asm/cmpxchg.h>
 #include <asm/page.h>
 #include <asm/page-bits.h>
 
@@ -247,9 +248,17 @@ static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long nr)
 #define PGT_writable_page PG_mask(1, 1)  /* has writable mappings?         */
 #define PGT_type_mask     PG_mask(1, 1)  /* Bits 31 or 63.                 */
 
-/* Count of uses of this frame as its current type. */
-#define PGT_count_width   PG_shift(2)
-#define PGT_count_mask    ((1UL << PGT_count_width) - 1)
+ /* 9-bit count of uses of this frame as its current type. */

    
      
    
      
    Nit: Stray blank at start of line.


    
      
    
        
    +#define PGT_count_mask    PG_mask(0x3FF, 10)

    
      
    
      
    A 9-bit count corresponds to a mask of 0x1ff, doesn't it? With 0x3ff the count
can spill over the type.
    
    
    
    
    It should be really 0x1ff, thanks.

~ Oleksii
    
  


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Subject: Re: [PATCH v2 1/4] x86/domctl: Stop using XLAT_cpu_user_regs()
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250807111657.201849-1-andrew.cooper3@citrix.com>
 <20250807111657.201849-2-andrew.cooper3@citrix.com>
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On 07.08.2025 13:16, Andrew Cooper wrote:
> In order to support FRED, we're going to have to remove the {ds..gs} fields
> from struct cpu_user_regs, meaning that it is going to have to become a
> different type to the structure embedded in vcpu_guest_context_u.
> 
> In both arch_{get,set}_info_guest(), expand the memcpy()/XLAT_cpu_user_regs()
> to copy the fields individually.  This will allow us to eventually make them
> different types.
> 
> This does cause some minor changes in behaviour for the hypercalls.
> 
> It is specifically not the case that a toolstack could set_info(); get_info();
> and get an identical bit pattern back.  Amongst other things, the
> architectural sticky bits in registers are applied during setting.
> 
> Previously, XLAT_cpu_user_regs() omitted the _pad fields in the compat case
> whereas the non-compat case included them owing to the single memcpy().
> 
> Omit the _pad fields in the non-compat case too; for all but the oldest of
> CPUs, the segment selectors are zero-extended by hardware when pushed onto the
> stack, so non-zero values here get lost naturally.  Furthermore, FRED reuses
> the space above cs and ss for extra state, and a PV guest for now at least
> must not be able to write the control state.
> 
> Omit the error_code and entry_vector fields too.  They're already identified
> as private fields in the public API, and are stale outside of Xen's
> interrupt/exception/syscall handler.  They're also a very minor information
> leak of which event caused the last deschedule of a vCPU.

I think my prior remark towards tools like xenctx wasn't really addressed.
Then again that particular tool doesn't use the fields now, so apparently
no-one ever saw a need.

> --- a/xen/arch/x86/domain.c
> +++ b/xen/arch/x86/domain.c
> @@ -1233,7 +1233,24 @@ int arch_set_info_guest(
>  
>      if ( !compat )
>      {
> -        memcpy(&v->arch.user_regs, &c.nat->user_regs, sizeof(c.nat->user_regs));
> +        memset(&v->arch.user_regs, 0, sizeof(v->arch.user_regs));

Any reason to have this and ...

> +        v->arch.user_regs.rbx               = c.nat->user_regs.rbx;
> +        v->arch.user_regs.rcx               = c.nat->user_regs.rcx;
> +        v->arch.user_regs.rdx               = c.nat->user_regs.rdx;
> +        v->arch.user_regs.rsi               = c.nat->user_regs.rsi;
> +        v->arch.user_regs.rdi               = c.nat->user_regs.rdi;
> +        v->arch.user_regs.rbp               = c.nat->user_regs.rbp;
> +        v->arch.user_regs.rax               = c.nat->user_regs.rax;
> +        v->arch.user_regs.rip               = c.nat->user_regs.rip;
> +        v->arch.user_regs.cs                = c.nat->user_regs.cs;
> +        v->arch.user_regs.rflags            = c.nat->user_regs.rflags;
> +        v->arch.user_regs.rsp               = c.nat->user_regs.rsp;
> +        v->arch.user_regs.ss                = c.nat->user_regs.ss;
> +        v->arch.user_regs.es                = c.nat->user_regs.es;
> +        v->arch.user_regs.ds                = c.nat->user_regs.ds;
> +        v->arch.user_regs.fs                = c.nat->user_regs.fs;
> +        v->arch.user_regs.gs                = c.nat->user_regs.gs;
> +
>          if ( is_pv_domain(d) )
>              memcpy(v->arch.pv.trap_ctxt, c.nat->trap_ctxt,
>                     sizeof(c.nat->trap_ctxt));
> @@ -1241,7 +1258,24 @@ int arch_set_info_guest(
>  #ifdef CONFIG_COMPAT
>      else
>      {
> -        XLAT_cpu_user_regs(&v->arch.user_regs, &c.cmp->user_regs);
> +        memset(&v->arch.user_regs, 0, sizeof(v->arch.user_regs));

... this separate, rather than putting just one ahead of the if()?

Preferably with that adjustment:
Reviewed-by: Jan Beulich 

Jan


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From: Ross Lagerwall 
Date: Fri, 8 Aug 2025 11:13:36 +0100
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Subject: Re: [PATCH 2/2] efi: Stop using StdErr
To: Jan Beulich 
Cc: "Daniel P. Smith" , 
	=?UTF-8?Q?Marek_Marczykowski=2DG=C3=B3recki?= , 
	xen-devel@lists.xenproject.org
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On Wed, Aug 6, 2025 at 7:32=E2=80=AFAM Jan Beulich  wrot=
e:
>
> On 05.08.2025 18:32, Ross Lagerwall wrote:
> > Xen's use of StdErr is inconsistent. Some boot errors are reported usin=
g
> > PrintErr() which uses StdErr and some are reported using blexit() which
> > uses StdOut.
>
> ... with PrintErrMesg() having
>
>     StdOut =3D StdErr;
>
> apparently to address at least some of the inconsistencies. Perhaps
> blexit(), when not passed NULL, should similarly override StdOut.
>
> > On my test system using OVMF, StdErr is not displayed on the emulated
> > screen. Looking at other EFI applications, StdErr is just used for debu=
g
> > messages if at all.
>
> That's hardly how StdErr was meant to be used. And at the risk of being
> flamed for saying so, looking at other EFI applications (without saying
> of what prominence or origin they are) can hardly serve as a justificatio=
n.
> If OVMF doesn't set up StdErr correctly (despite being configured / set u=
p
> correctly), and if that can't be fixed there, imo what you want as a
> workaround is a command line option to override StdErr by StdOut even whe=
n
> SystemTable->StdErr is non-NULL.
>
> Along the lines of the comment further up, inconsistencies in the use of
> StdErr vs StdOut may want addressing (separately).
>

I tried to reproduce this on a few physical hosts and was unable to so
for now I'll chalk it up as an OVMF bug / configuration issue and
retract this patch. And yes, the StdErr vs StdOut issue should probably
be addressed separately.

Thanks,
Ross


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From: Ross Lagerwall 
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Subject: Re: [PATCH 1/2] efi: Call FreePages only if needed
To: Jan Beulich 
Cc: "Daniel P. Smith" , 
	=?UTF-8?Q?Marek_Marczykowski=2DG=C3=B3recki?= , 
	xen-devel@lists.xenproject.org
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On Wed, Aug 6, 2025 at 7:16=E2=80=AFAM Jan Beulich  wrot=
e:
>
> On 05.08.2025 18:32, Ross Lagerwall wrote:
> > If the config file is builtin, cfg.addr will be zero but Xen
> > unconditionally calls FreePages() on the address.
> >
> > Xen may also call FreePages() with a zero address if blexit() is called
> > after this point since cfg.need_to_free is not set to false.
> >
> > The UEFI specification does not say whether calling FreePages() with a
> > zero address is allowed so let's be cautious and use cfg.need_to_free
> > properly.
>
> Well, no, this paragraph makes no sense. Of course this is allowed, but
> not as no-op behavior (like free(NULL) would be), but to free memory
> starting at 0.

Fair enough. This paragraph could simply be dropped then.

>
> > Signed-off-by: Ross Lagerwall 
>
> This pretty clearly wants a Fixes: tag, or maybe it even needs to be two.
> I've checked the original code in 4.2, and things were consistent there,
> afaics. So breakage was introduced perhaps in one or two of the many
> re-works.
>

Fixes: 8a71d50ed40b ("efi: Enable booting unified
hypervisor/kernel/initrd images")
Fixes: 04be2c3a0678 ("efi/boot.c: add file.need_to_free")

Do you want an updated patch or can these tweaks be done while committing?

Thanks,
Ross


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Subject: Re: [PATCH 1/2] efi: Call FreePages only if needed
To: Ross Lagerwall 
Cc: "Daniel P. Smith" ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , xen-devel@lists.xenproject.org
References: <20250805163204.3631483-1-ross.lagerwall@citrix.com>
 <20250805163204.3631483-2-ross.lagerwall@citrix.com>
 
 
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On 08.08.2025 12:14, Ross Lagerwall wrote:
> On Wed, Aug 6, 2025 at 7:16 AM Jan Beulich  wrote:
>>
>> On 05.08.2025 18:32, Ross Lagerwall wrote:
>>> If the config file is builtin, cfg.addr will be zero but Xen
>>> unconditionally calls FreePages() on the address.
>>>
>>> Xen may also call FreePages() with a zero address if blexit() is called
>>> after this point since cfg.need_to_free is not set to false.
>>>
>>> The UEFI specification does not say whether calling FreePages() with a
>>> zero address is allowed so let's be cautious and use cfg.need_to_free
>>> properly.
>>
>> Well, no, this paragraph makes no sense. Of course this is allowed, but
>> not as no-op behavior (like free(NULL) would be), but to free memory
>> starting at 0.
> 
> Fair enough. This paragraph could simply be dropped then.
> 
>>
>>> Signed-off-by: Ross Lagerwall 
>>
>> This pretty clearly wants a Fixes: tag, or maybe it even needs to be two.
>> I've checked the original code in 4.2, and things were consistent there,
>> afaics. So breakage was introduced perhaps in one or two of the many
>> re-works.
>>
> 
> Fixes: 8a71d50ed40b ("efi: Enable booting unified
> hypervisor/kernel/initrd images")
> Fixes: 04be2c3a0678 ("efi/boot.c: add file.need_to_free")
> 
> Do you want an updated patch or can these tweaks be done while committing?

If the maintainers have no other requests that require a v2, I'm sure this
can be done while committing.

Jan


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Subject: Re: [PATCH v5 02/25] drm/dumb-buffers: Provide helper to set pitch
 and size
To: Thomas Zimmermann 
Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org,
 freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
 imx@lists.linux.dev, linux-samsung-soc@vger.kernel.org,
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 intel-xe@lists.freedesktop.org, xen-devel@lists.xenproject.org,
 simona@ffwll.ch, airlied@gmail.com, mripard@kernel.org,
 maarten.lankhorst@linux.intel.com, geert@linux-m68k.org
References: <20250613090431.127087-1-tzimmermann@suse.de>
 <20250613090431.127087-3-tzimmermann@suse.de>
Content-Language: en-US
From: Tomi Valkeinen 
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In-Reply-To: <20250613090431.127087-3-tzimmermann@suse.de>
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Hi,

On 13/06/2025 12:00, Thomas Zimmermann wrote:
> Add drm_modes_size_dumb(), a helper to calculate the dumb-buffer
> scanline pitch and allocation size. Implementations of struct
> drm_driver.dumb_create can call the new helper for their size
> computations.
> 
> There is currently quite a bit of code duplication among DRM's
> memory managers. Each calculates scanline pitch and buffer size
> from the given arguments, but the implementations are inconsistent
> in how they treat alignment and format support. Later patches will
> unify this code on top of drm_mode_size_dumb() as much as possible.
> 
> drm_mode_size_dumb() uses existing 4CC format helpers to interpret
> the given color mode. This makes the dumb-buffer interface behave
> similar the kernel's video= parameter. Current per-driver implementations
> again likely have subtle differences or bugs in how they support color
> modes.
> 
> The dumb-buffer UAPI is only specified for known color modes. These
> values describe linear, single-plane RGB color formats or legacy index
> formats. Other values should not be specified. But some user space
> still does. So for unknown color modes, there are a number of known
> exceptions for which drm_mode_size_dumb() calculates the pitch from
> the bpp value, as before. All other values work the same but print
> an error.
> 
> v5:
> - check for overflows with check_mul_overflow() (Tomi)
> v4:
> - use %u conversion specifier (Geert)
> - list DRM_FORMAT_Dn in UAPI docs (Geert)
> - avoid dmesg spamming with drm_warn_once() (Sima)
> - add more information about bpp special case (Sima)
> - clarify parameters for hardware alignment
> - add a TODO item for DUMB_CREATE2
> v3:
> - document the UAPI semantics
> - compute scanline pitch from for unknown color modes (Andy, Tomi)
> 
> Signed-off-by: Thomas Zimmermann 
> Reviewed-by: Tomi Valkeinen 
> ---
>  Documentation/gpu/todo.rst         |  27 ++++++
>  drivers/gpu/drm/drm_dumb_buffers.c | 130 +++++++++++++++++++++++++++++
>  include/drm/drm_dumb_buffers.h     |  14 ++++
>  include/uapi/drm/drm_mode.h        |  50 ++++++++++-
>  4 files changed, 220 insertions(+), 1 deletion(-)
>  create mode 100644 include/drm/drm_dumb_buffers.h
> 
> diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
> index be8637da3fe9..f7312afa87b5 100644
> --- a/Documentation/gpu/todo.rst
> +++ b/Documentation/gpu/todo.rst
> @@ -648,6 +648,33 @@ Contact: Thomas Zimmermann , Simona Vetter
>  
>  Level: Advanced
>  
> +Implement a new DUMB_CREATE2 ioctl
> +----------------------------------
> +
> +The current DUMB_CREATE ioctl is not well defined. Instead of a pixel and
> +framebuffer format, it only accepts a color mode of vague semantics. Assuming
> +a linear framebuffer, the color mode gives and idea of the supported pixel

"an" idea.

> +format. But userspace effectively has to guess the correct values. It really
> +only works reliable with framebuffers in XRGB8888. Userspace has begun to

"reliably"

> +workaround these limitations by computing arbitrary format's buffer sizes and
> +calculating their sizes in terms of XRGB8888 pixels.
> +
> +One possible solution is a new ioctl DUMB_CREATE2. It should accept a DRM
> +format and a format modifier to resolve the color mode's ambiguity. As
> +framebuffers can be multi-planar, the new ioctl has to return the buffer size,
> +pitch and GEM handle for each individual color plane.
> +
> +In the first step, the new ioctl can be limited to the current features of
> +the existing DUMB_CREATE. Individual drivers can then be extended to support
> +multi-planar formats. Rockchip might require this and would be a good candidate.
> +
> +In addition to the kernel implementation, there must be user-space support
> +for the new ioctl. There's code in Mesa that might be able to use the new
> +call.

I think it would be important to allow non-alloc use of DUMB_CREATE2, or
have another ioctl for it. In other words, you could ask the driver what
the buffers for pixel format XYZ have to look like, and then you could
allocate the actual memory buffers from somewhere else.

Reviewed-by: Tomi Valkeinen 

 Tomi

> +Contact: Thomas Zimmermann 
> +
> +Level: Advanced
>  
>  Better Testing
>  ==============
> diff --git a/drivers/gpu/drm/drm_dumb_buffers.c b/drivers/gpu/drm/drm_dumb_buffers.c
> index 9916aaf5b3f2..e9eed9a5b760 100644
> --- a/drivers/gpu/drm/drm_dumb_buffers.c
> +++ b/drivers/gpu/drm/drm_dumb_buffers.c
> @@ -25,6 +25,8 @@
>  
>  #include 
>  #include 
> +#include 
> +#include 
>  #include 
>  #include 
>  
> @@ -57,6 +59,134 @@
>   * a hardware-specific ioctl to allocate suitable buffer objects.
>   */
>  
> +static int drm_mode_align_dumb(struct drm_mode_create_dumb *args,
> +			       unsigned long hw_pitch_align,
> +			       unsigned long hw_size_align)
> +{
> +	u32 pitch = args->pitch;
> +	u32 size;
> +
> +	if (!pitch)
> +		return -EINVAL;
> +
> +	if (hw_pitch_align)
> +		pitch = roundup(pitch, hw_pitch_align);
> +
> +	if (!hw_size_align)
> +		hw_size_align = PAGE_SIZE;
> +	else if (!IS_ALIGNED(hw_size_align, PAGE_SIZE))
> +		return -EINVAL; /* TODO: handle this if necessary */
> +
> +	if (check_mul_overflow(args->height, pitch, &size))
> +		return -EINVAL;
> +	size = ALIGN(size, hw_size_align);
> +	if (!size)
> +		return -EINVAL;
> +
> +	args->pitch = pitch;
> +	args->size = size;
> +
> +	return 0;
> +}
> +
> +/**
> + * drm_mode_size_dumb - Calculates the scanline and buffer sizes for dumb buffers
> + * @dev: DRM device
> + * @args: Parameters for the dumb buffer
> + * @hw_pitch_align: Hardware scanline alignment in bytes
> + * @hw_size_align: Hardware buffer-size alignment in bytes
> + *
> + * The helper drm_mode_size_dumb() calculates the size of the buffer
> + * allocation and the scanline size for a dumb buffer. Callers have to
> + * set the buffers width, height and color mode in the argument @arg.
> + * The helper validates the correctness of the input and tests for
> + * possible overflows. If successful, it returns the dumb buffer's
> + * required scanline pitch and size in &args.
> + *
> + * The parameter @hw_pitch_align allows the driver to specifies an
> + * alignment for the scanline pitch, if the hardware requires any. The
> + * calculated pitch will be a multiple of the alignment. The parameter
> + * @hw_size_align allows to specify an alignment for buffer sizes. The
> + * provided alignment should represent requirements of the graphics
> + * hardware. drm_mode_size_dumb() handles GEM-related constraints
> + * automatically across all drivers and hardware. For example, the
> + * returned buffer size is always a multiple of PAGE_SIZE, which is
> + * required by mmap().
> + *
> + * Returns:
> + * Zero on success, or a negative error code otherwise.
> + */
> +int drm_mode_size_dumb(struct drm_device *dev,
> +		       struct drm_mode_create_dumb *args,
> +		       unsigned long hw_pitch_align,
> +		       unsigned long hw_size_align)
> +{
> +	u64 pitch = 0;
> +	u32 fourcc;
> +
> +	/*
> +	 * The scanline pitch depends on the buffer width and the color
> +	 * format. The latter is specified as a color-mode constant for
> +	 * which we first have to find the corresponding color format.
> +	 *
> +	 * Different color formats can have the same color-mode constant.
> +	 * For example XRGB8888 and BGRX8888 both have a color mode of 32.
> +	 * It is possible to use different formats for dumb-buffer allocation
> +	 * and rendering as long as all involved formats share the same
> +	 * color-mode constant.
> +	 */
> +	fourcc = drm_driver_color_mode_format(dev, args->bpp);
> +	if (fourcc != DRM_FORMAT_INVALID) {
> +		const struct drm_format_info *info = drm_format_info(fourcc);
> +
> +		if (!info)
> +			return -EINVAL;
> +		pitch = drm_format_info_min_pitch(info, 0, args->width);
> +	} else if (args->bpp) {
> +		/*
> +		 * Some userspace throws in arbitrary values for bpp and
> +		 * relies on the kernel to figure it out. In this case we
> +		 * fall back to the old method of using bpp directly. The
> +		 * over-commitment of memory from the rounding is acceptable
> +		 * for compatibility with legacy userspace. We have a number
> +		 * of deprecated legacy values that are explicitly supported.
> +		 */
> +		switch (args->bpp) {
> +		default:
> +			drm_warn_once(dev,
> +				      "Unknown color mode %u; guessing buffer size.\n",
> +				      args->bpp);
> +			fallthrough;
> +		/*
> +		 * These constants represent various YUV formats supported by
> +		 * drm_gem_afbc_get_bpp().
> +		 */
> +		case 12: // DRM_FORMAT_YUV420_8BIT
> +		case 15: // DRM_FORMAT_YUV420_10BIT
> +		case 30: // DRM_FORMAT_VUY101010
> +			fallthrough;
> +		/*
> +		 * Used by Mesa and Gstreamer to allocate NV formats and others
> +		 * as RGB buffers. Technically, XRGB16161616F formats are RGB,
> +		 * but the dumb buffers are not supposed to be used for anything
> +		 * beyond 32 bits per pixels.
> +		 */
> +		case 10: // DRM_FORMAT_NV{15,20,30}, DRM_FORMAT_P010
> +		case 64: // DRM_FORMAT_{XRGB,XBGR,ARGB,ABGR}16161616F
> +			pitch = args->width * DIV_ROUND_UP(args->bpp, SZ_8);
> +			break;
> +		}
> +	}
> +
> +	if (!pitch || pitch > U32_MAX)
> +		return -EINVAL;
> +
> +	args->pitch = pitch;
> +
> +	return drm_mode_align_dumb(args, hw_pitch_align, hw_size_align);
> +}
> +EXPORT_SYMBOL(drm_mode_size_dumb);
> +
>  int drm_mode_create_dumb(struct drm_device *dev,
>  			 struct drm_mode_create_dumb *args,
>  			 struct drm_file *file_priv)
> diff --git a/include/drm/drm_dumb_buffers.h b/include/drm/drm_dumb_buffers.h
> new file mode 100644
> index 000000000000..1f3a8236fb3d
> --- /dev/null
> +++ b/include/drm/drm_dumb_buffers.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +
> +#ifndef __DRM_DUMB_BUFFERS_H__
> +#define __DRM_DUMB_BUFFERS_H__
> +
> +struct drm_device;
> +struct drm_mode_create_dumb;
> +
> +int drm_mode_size_dumb(struct drm_device *dev,
> +		       struct drm_mode_create_dumb *args,
> +		       unsigned long hw_pitch_align,
> +		       unsigned long hw_size_align);
> +
> +#endif
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index c082810c08a8..efe8f5ad35ee 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -1058,7 +1058,7 @@ struct drm_mode_crtc_page_flip_target {
>   * struct drm_mode_create_dumb - Create a KMS dumb buffer for scanout.
>   * @height: buffer height in pixels
>   * @width: buffer width in pixels
> - * @bpp: bits per pixel
> + * @bpp: color mode
>   * @flags: must be zero
>   * @handle: buffer object handle
>   * @pitch: number of bytes between two consecutive lines
> @@ -1066,6 +1066,54 @@ struct drm_mode_crtc_page_flip_target {
>   *
>   * User-space fills @height, @width, @bpp and @flags. If the IOCTL succeeds,
>   * the kernel fills @handle, @pitch and @size.
> + *
> + * The value of @bpp is a color-mode number describing a specific format
> + * or a variant thereof. The value often corresponds to the number of bits
> + * per pixel for most modes, although there are exceptions. Each color mode
> + * maps to a DRM format plus a number of modes with similar pixel layout.
> + * Framebuffer layout is always linear.
> + *
> + * Support for all modes and formats is optional. Even if dumb-buffer
> + * creation with a certain color mode succeeds, it is not guaranteed that
> + * the DRM driver supports any of the related formats. Most drivers support
> + * a color mode of 32 with a format of DRM_FORMAT_XRGB8888 on their primary
> + * plane.
> + *
> + * +------------+------------------------+------------------------+
> + * | Color mode | Framebuffer format     | Compatible formats     |
> + * +============+========================+========================+
> + * |     32     |  * DRM_FORMAT_XRGB8888 |  * DRM_FORMAT_BGRX8888 |
> + * |            |                        |  * DRM_FORMAT_RGBX8888 |
> + * |            |                        |  * DRM_FORMAT_XBGR8888 |
> + * +------------+------------------------+------------------------+
> + * |     24     |  * DRM_FORMAT_RGB888   |  * DRM_FORMAT_BGR888   |
> + * +------------+------------------------+------------------------+
> + * |     16     |  * DRM_FORMAT_RGB565   |  * DRM_FORMAT_BGR565   |
> + * +------------+------------------------+------------------------+
> + * |     15     |  * DRM_FORMAT_XRGB1555 |  * DRM_FORMAT_BGRX1555 |
> + * |            |                        |  * DRM_FORMAT_RGBX1555 |
> + * |            |                        |  * DRM_FORMAT_XBGR1555 |
> + * +------------+------------------------+------------------------+
> + * |      8     |  * DRM_FORMAT_C8       |  * DRM_FORMAT_D8       |
> + * |            |                        |  * DRM_FORMAT_R8       |
> + * +------------+------------------------+------------------------+
> + * |      4     |  * DRM_FORMAT_C4       |  * DRM_FORMAT_D4       |
> + * |            |                        |  * DRM_FORMAT_R4       |
> + * +------------+------------------------+------------------------+
> + * |      2     |  * DRM_FORMAT_C2       |  * DRM_FORMAT_D2       |
> + * |            |                        |  * DRM_FORMAT_R2       |
> + * +------------+------------------------+------------------------+
> + * |      1     |  * DRM_FORMAT_C1       |  * DRM_FORMAT_D1       |
> + * |            |                        |  * DRM_FORMAT_R1       |
> + * +------------+------------------------+------------------------+
> + *
> + * Color modes of 10, 12, 15, 30 and 64 are only supported for use by
> + * legacy user space. Please don't use them in new code. Other modes
> + * are not support.
> + *
> + * Do not attempt to allocate anything but linear framebuffer memory
> + * with single-plane RGB data. Allocation of other framebuffer
> + * layouts requires dedicated ioctls in the respective DRM driver.
>   */
>  struct drm_mode_create_dumb {
>  	__u32 height;



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Date: Fri, 8 Aug 2025 11:42:58 +0100
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Subject: Re: [PATCH v2 1/4] x86/domctl: Stop using XLAT_cpu_user_regs()
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250807111657.201849-1-andrew.cooper3@citrix.com>
 <20250807111657.201849-2-andrew.cooper3@citrix.com>
 
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On 08/08/2025 11:09 am, Jan Beulich wrote:
> On 07.08.2025 13:16, Andrew Cooper wrote:
>> In order to support FRED, we're going to have to remove the {ds..gs} fields
>> from struct cpu_user_regs, meaning that it is going to have to become a
>> different type to the structure embedded in vcpu_guest_context_u.
>>
>> In both arch_{get,set}_info_guest(), expand the memcpy()/XLAT_cpu_user_regs()
>> to copy the fields individually.  This will allow us to eventually make them
>> different types.
>>
>> This does cause some minor changes in behaviour for the hypercalls.
>>
>> It is specifically not the case that a toolstack could set_info(); get_info();
>> and get an identical bit pattern back.  Amongst other things, the
>> architectural sticky bits in registers are applied during setting.
>>
>> Previously, XLAT_cpu_user_regs() omitted the _pad fields in the compat case
>> whereas the non-compat case included them owing to the single memcpy().
>>
>> Omit the _pad fields in the non-compat case too; for all but the oldest of
>> CPUs, the segment selectors are zero-extended by hardware when pushed onto the
>> stack, so non-zero values here get lost naturally.  Furthermore, FRED reuses
>> the space above cs and ss for extra state, and a PV guest for now at least
>> must not be able to write the control state.
>>
>> Omit the error_code and entry_vector fields too.  They're already identified
>> as private fields in the public API, and are stale outside of Xen's
>> interrupt/exception/syscall handler.  They're also a very minor information
>> leak of which event caused the last deschedule of a vCPU.
> I think my prior remark towards tools like xenctx wasn't really addressed.
> Then again that particular tool doesn't use the fields now, so apparently
> no-one ever saw a need.

Oh, sorry.  I did specifically look (everywhere in tools, not just
xenctx), and they're not used at all.

Xenalyze uses an error_code, but that's a field name from the EPT/NPT
fault trace record, not from cpu_user_regs.

Finally, the observation about the information leak.  The information
present is often the timer interrupt (end of time-slice), or the event
check IPI (from vcpu_pause()).

gdbsx is the only utility that stands a chance of reliably using
->entry_vector, and even it doesn't because that's not how GDB works.

Overall, I'd say people have been pretty good at following the /*
Private */ note in the public ABI.


>
>> --- a/xen/arch/x86/domain.c
>> +++ b/xen/arch/x86/domain.c
>> @@ -1233,7 +1233,24 @@ int arch_set_info_guest(
>>  
>>      if ( !compat )
>>      {
>> -        memcpy(&v->arch.user_regs, &c.nat->user_regs, sizeof(c.nat->user_regs));
>> +        memset(&v->arch.user_regs, 0, sizeof(v->arch.user_regs));
> Any reason to have this and ...
>
>> +        v->arch.user_regs.rbx               = c.nat->user_regs.rbx;
>> +        v->arch.user_regs.rcx               = c.nat->user_regs.rcx;
>> +        v->arch.user_regs.rdx               = c.nat->user_regs.rdx;
>> +        v->arch.user_regs.rsi               = c.nat->user_regs.rsi;
>> +        v->arch.user_regs.rdi               = c.nat->user_regs.rdi;
>> +        v->arch.user_regs.rbp               = c.nat->user_regs.rbp;
>> +        v->arch.user_regs.rax               = c.nat->user_regs.rax;
>> +        v->arch.user_regs.rip               = c.nat->user_regs.rip;
>> +        v->arch.user_regs.cs                = c.nat->user_regs.cs;
>> +        v->arch.user_regs.rflags            = c.nat->user_regs.rflags;
>> +        v->arch.user_regs.rsp               = c.nat->user_regs.rsp;
>> +        v->arch.user_regs.ss                = c.nat->user_regs.ss;
>> +        v->arch.user_regs.es                = c.nat->user_regs.es;
>> +        v->arch.user_regs.ds                = c.nat->user_regs.ds;
>> +        v->arch.user_regs.fs                = c.nat->user_regs.fs;
>> +        v->arch.user_regs.gs                = c.nat->user_regs.gs;
>> +
>>          if ( is_pv_domain(d) )
>>              memcpy(v->arch.pv.trap_ctxt, c.nat->trap_ctxt,
>>                     sizeof(c.nat->trap_ctxt));
>> @@ -1241,7 +1258,24 @@ int arch_set_info_guest(
>>  #ifdef CONFIG_COMPAT
>>      else
>>      {
>> -        XLAT_cpu_user_regs(&v->arch.user_regs, &c.cmp->user_regs);
>> +        memset(&v->arch.user_regs, 0, sizeof(v->arch.user_regs));
> ... this separate, rather than putting just one ahead of the if()?

Code generation.  If you hoist the memset(), it can't be merged with the
assignments.

Although I see now it's not even attempting the mere (it was in the
past), and I don't care enough to argue, so I'll change it.

> Preferably with that adjustment:
> Reviewed-by: Jan Beulich 

Thanks.

~Andrew


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Date: Fri, 8 Aug 2025 13:43:27 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v5 03/25] drm/gem-dma: Compute dumb-buffer sizes with
 drm_mode_size_dumb()
To: Thomas Zimmermann 
Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org,
 freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
 imx@lists.linux.dev, linux-samsung-soc@vger.kernel.org,
 nouveau@lists.freedesktop.org, virtualization@lists.linux.dev,
 spice-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org,
 linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org,
 intel-xe@lists.freedesktop.org, xen-devel@lists.xenproject.org,
 simona@ffwll.ch, airlied@gmail.com, mripard@kernel.org,
 maarten.lankhorst@linux.intel.com, geert@linux-m68k.org
References: <20250613090431.127087-1-tzimmermann@suse.de>
 <20250613090431.127087-4-tzimmermann@suse.de>
Content-Language: en-US
From: Tomi Valkeinen 
Autocrypt: addr=tomi.valkeinen@ideasonboard.com; keydata=
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In-Reply-To: <20250613090431.127087-4-tzimmermann@suse.de>
Content-Type: text/plain; charset=UTF-8
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On 13/06/2025 12:00, Thomas Zimmermann wrote:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
> buffer size. Align the pitch to a multiple of 8.
> 
> Push the current calculation into the only direct caller imx. Imx's
> hardware requires the framebuffer width to be aligned to 8. The
> driver's current approach is actually incorrect, as it only guarantees
> this implicitly and requires bpp to be a multiple of 8 already. A
> later commit will fix this problem by aligning the scanline pitch
> such that an aligned width still fits into each scanline's memory.
> 
> A number of other drivers are build on top of gem-dma helpers and
> implement their own dumb-buffer allocation. These drivers invoke
> drm_gem_dma_dumb_create_internal(), which is not affected by this
> commit.
> 
> v5:
> - avoid reset of arguments (Tomi)
> 
> Signed-off-by: Thomas Zimmermann 
> ---
>  drivers/gpu/drm/drm_gem_dma_helper.c     | 7 +++++--
>  drivers/gpu/drm/imx/ipuv3/imx-drm-core.c | 4 +++-
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_gem_dma_helper.c b/drivers/gpu/drm/drm_gem_dma_helper.c
> index b7f033d4352a..49be9b033610 100644
> --- a/drivers/gpu/drm/drm_gem_dma_helper.c
> +++ b/drivers/gpu/drm/drm_gem_dma_helper.c
> @@ -20,6 +20,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  
> @@ -304,9 +305,11 @@ int drm_gem_dma_dumb_create(struct drm_file *file_priv,
>  			    struct drm_mode_create_dumb *args)
>  {
>  	struct drm_gem_dma_object *dma_obj;
> +	int ret;
>  
> -	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
> -	args->size = args->pitch * args->height;
> +	ret = drm_mode_size_dumb(drm, args, SZ_8, 0);
> +	if (ret)
> +		return ret;
>  
>  	dma_obj = drm_gem_dma_create_with_handle(file_priv, drm, args->size,
>  						 &args->handle);
> diff --git a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
> index ec5fd9a01f1e..af4a30311e18 100644
> --- a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
> +++ b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
> @@ -145,8 +145,10 @@ static int imx_drm_dumb_create(struct drm_file *file_priv,
>  	int ret;
>  
>  	args->width = ALIGN(width, 8);
> +	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
> +	args->size = args->pitch * args->height;
>  
> -	ret = drm_gem_dma_dumb_create(file_priv, drm, args);
> +	ret = drm_gem_dma_dumb_create_internal(file_priv, drm, args);
>  	if (ret)
>  		return ret;
>  

Reviewed-by: Tomi Valkeinen 

 Tomi



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        Fri, 08 Aug 2025 03:44:09 -0700 (PDT)
From: Kevin Lampis 
To: xen-devel@lists.xenproject.org
Cc: jbeulich@suse.com,
	andrew.cooper3@citrix.com,
	roger.pau@citrix.com,
	Kevin Lampis 
Subject: [PATCH] x86: Remove x86 prefixed names from cpuinfo
Date: Fri,  8 Aug 2025 11:43:49 +0100
Message-ID: <20250808104349.635091-1-kevin.lampis@cloud.com>
X-Mailer: git-send-email 2.50.1
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

struct cpuinfo_x86
  .x86        => .family
  .x86_vendor => .vendor
  .x86_model  => .model
  .x86_mask   => .stepping

No functional change.

Signed-off-by: Kevin Lampis 
---
 xen/arch/x86/acpi/cpu_idle.c             | 20 +++---
 xen/arch/x86/acpi/cpufreq/acpi.c         |  2 +-
 xen/arch/x86/acpi/cpufreq/cpufreq.c      |  4 +-
 xen/arch/x86/acpi/cpufreq/powernow.c     |  4 +-
 xen/arch/x86/alternative.c               |  8 +--
 xen/arch/x86/apic.c                      |  8 +--
 xen/arch/x86/cpu/amd.c                   | 84 ++++++++++++------------
 xen/arch/x86/cpu/centaur.c               |  4 +-
 xen/arch/x86/cpu/common.c                | 38 +++++------
 xen/arch/x86/cpu/hygon.c                 |  4 +-
 xen/arch/x86/cpu/intel.c                 | 30 ++++-----
 xen/arch/x86/cpu/intel_cacheinfo.c       |  6 +-
 xen/arch/x86/cpu/mcheck/amd_nonfatal.c   |  2 +-
 xen/arch/x86/cpu/mcheck/mcaction.c       |  2 +-
 xen/arch/x86/cpu/mcheck/mce.c            | 30 ++++-----
 xen/arch/x86/cpu/mcheck/mce.h            |  2 +-
 xen/arch/x86/cpu/mcheck/mce_amd.c        | 16 ++---
 xen/arch/x86/cpu/mcheck/mce_intel.c      |  5 +-
 xen/arch/x86/cpu/mcheck/non-fatal.c      |  2 +-
 xen/arch/x86/cpu/mcheck/vmce.c           |  8 +--
 xen/arch/x86/cpu/mtrr/generic.c          |  6 +-
 xen/arch/x86/cpu/mwait-idle.c            |  4 +-
 xen/arch/x86/cpu/vpmu.c                  |  4 +-
 xen/arch/x86/cpu/vpmu_amd.c              |  6 +-
 xen/arch/x86/cpu/vpmu_intel.c            |  4 +-
 xen/arch/x86/cpuid.c                     |  2 +-
 xen/arch/x86/dom0_build.c                |  4 +-
 xen/arch/x86/domain.c                    | 12 ++--
 xen/arch/x86/e820.c                      |  2 +-
 xen/arch/x86/hvm/hvm.c                   |  2 +-
 xen/arch/x86/hvm/svm/svm.c               |  6 +-
 xen/arch/x86/hvm/vmx/vmcs.c              |  4 +-
 xen/arch/x86/hvm/vmx/vmx.c               | 28 ++++----
 xen/arch/x86/i8259.c                     |  2 +-
 xen/arch/x86/include/asm/cpufeature.h    | 21 ++----
 xen/arch/x86/include/asm/intel-family.h  |  4 ++
 xen/arch/x86/io_apic.c                   |  2 +-
 xen/arch/x86/irq.c                       |  4 +-
 xen/arch/x86/mpparse.c                   |  8 +--
 xen/arch/x86/msr.c                       |  4 +-
 xen/arch/x86/nmi.c                       | 12 ++--
 xen/arch/x86/platform_hypercall.c        |  6 +-
 xen/arch/x86/pv/domain.c                 |  2 +-
 xen/arch/x86/pv/emul-priv-op.c           | 30 ++++-----
 xen/arch/x86/setup.c                     |  6 +-
 xen/arch/x86/traps-setup.c               |  4 +-
 xen/arch/x86/tsx.c                       |  4 +-
 xen/drivers/passthrough/amd/iommu_init.c |  6 +-
 48 files changed, 234 insertions(+), 244 deletions(-)

diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index d60a07bfd5..95a626f49c 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -178,10 +178,10 @@ static void cf_check do_get_hw_residencies(void *arg)
     struct cpuinfo_x86 *c = ¤t_cpu_data;
     struct hw_residencies *hw_res = arg;
 
-    if ( c->x86_vendor != X86_VENDOR_INTEL || c->x86 != 6 )
+    if ( c->vendor != X86_VENDOR_INTEL || c->family != 6 )
         return;
 
-    switch ( c->x86_model )
+    switch ( c->model )
     {
     /* 4th generation Intel Core (Haswell) */
     case 0x45:
@@ -915,7 +915,7 @@ void cf_check acpi_dead_idle(void)
             mwait(cx->address, 0);
         }
     }
-    else if ( (current_cpu_data.x86_vendor &
+    else if ( (current_cpu_data.vendor &
                (X86_VENDOR_AMD | X86_VENDOR_HYGON)) &&
               cx->entry_method == ACPI_CSTATE_EM_SYSIO )
     {
@@ -1042,8 +1042,8 @@ static void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flag
     flags->bm_check = 0;
     if ( num_online_cpus() == 1 )
         flags->bm_check = 1;
-    else if ( (c->x86_vendor == X86_VENDOR_INTEL) ||
-              ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 0x15)) )
+    else if ( (c->vendor == X86_VENDOR_INTEL) ||
+              ((c->vendor == X86_VENDOR_AMD) && (c->family == 0x15)) )
     {
         /*
          * Today all MP CPUs that support C3 share cache.
@@ -1059,8 +1059,8 @@ static void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flag
      * is not required while entering C3 type state on
      * P4, Core and beyond CPUs
      */
-    if ( c->x86_vendor == X86_VENDOR_INTEL &&
-        (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14)) )
+    if ( c->vendor == X86_VENDOR_INTEL &&
+        (c->family > 0x6 || (c->family == 6 && c->model >= 14)) )
             flags->bm_control = 0;
 }
 
@@ -1416,12 +1416,12 @@ static void amd_cpuidle_init(struct acpi_processor_power *power)
     if ( vendor_override < 0 )
         return;
 
-    switch ( c->x86 )
+    switch ( c->model )
     {
     case 0x1a:
     case 0x19:
     case 0x18:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_HYGON )
+        if ( boot_cpu_data.vendor != X86_VENDOR_HYGON )
         {
     default:
             vendor_override = -1;
@@ -1648,7 +1648,7 @@ static int cf_check cpu_callback(
         break;
 
     case CPU_ONLINE:
-        if ( (boot_cpu_data.x86_vendor &
+        if ( (boot_cpu_data.vendor &
               (X86_VENDOR_AMD | X86_VENDOR_HYGON)) &&
              processor_powers[cpu] )
             amd_cpuidle_init(processor_powers[cpu]);
diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/acpi.c
index 0c25376406..8a102baff3 100644
--- a/xen/arch/x86/acpi/cpufreq/acpi.c
+++ b/xen/arch/x86/acpi/cpufreq/acpi.c
@@ -468,7 +468,7 @@ static int cf_check acpi_cpufreq_cpu_init(struct cpufreq_policy *policy)
 
     /* Check for APERF/MPERF support in hardware
      * also check for boost support */
-    if (c->x86_vendor == X86_VENDOR_INTEL && c->cpuid_level >= 6)
+    if ( c->vendor == X86_VENDOR_INTEL && c->cpuid_level >= 6 )
         on_selected_cpus(cpumask_of(cpu), feature_detect, policy, 1);
 
     /*
diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c
index 45f301f354..abb19573a7 100644
--- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
+++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
@@ -128,7 +128,7 @@ static int __init cf_check cpufreq_driver_init(void)
 
     if ( cpufreq_controller == FREQCTL_xen )
     {
-        switch ( boot_cpu_data.x86_vendor )
+        switch ( boot_cpu_data.vendor )
         {
         case X86_VENDOR_INTEL:
             ret = -ENOENT;
@@ -182,7 +182,7 @@ __initcall(cpufreq_driver_late_init);
 int cpufreq_cpu_init(unsigned int cpu)
 {
     /* Currently we only handle Intel, AMD and Hygon processor */
-    if ( boot_cpu_data.x86_vendor &
+    if ( boot_cpu_data.vendor &
          (X86_VENDOR_INTEL | X86_VENDOR_AMD | X86_VENDOR_HYGON) )
         return cpufreq_add_cpu(cpu);
 
diff --git a/xen/arch/x86/acpi/cpufreq/powernow.c b/xen/arch/x86/acpi/cpufreq/powernow.c
index 12fca45b45..4c04dd242f 100644
--- a/xen/arch/x86/acpi/cpufreq/powernow.c
+++ b/xen/arch/x86/acpi/cpufreq/powernow.c
@@ -144,7 +144,7 @@ static void amd_fixup_frequency(struct xen_processor_px *px)
     int index = px->control & 0x00000007;
     const struct cpuinfo_x86 *c = ¤t_cpu_data;
 
-    if ((c->x86 != 0x10 || c->x86_model >= 10) && c->x86 != 0x11)
+    if ((c->family != 0x10 || c->model >= 10) && c->family != 0x11)
         return;
 
     rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi);
@@ -157,7 +157,7 @@ static void amd_fixup_frequency(struct xen_processor_px *px)
 
     fid = lo & 0x3f;
     did = (lo >> 6) & 7;
-    if (c->x86 == 0x10)
+    if (c->family == 0x10)
         px->core_frequency = (100 * (fid + 16)) >> did;
     else
         px->core_frequency = (100 * (fid + 8)) >> did;
diff --git a/xen/arch/x86/alternative.c b/xen/arch/x86/alternative.c
index 9f844241bc..5ed0c26725 100644
--- a/xen/arch/x86/alternative.c
+++ b/xen/arch/x86/alternative.c
@@ -89,7 +89,7 @@ static bool init_or_livepatch_read_mostly toolchain_nops_are_ideal;
 
 static void __init arch_init_ideal_nops(void)
 {
-    switch ( boot_cpu_data.x86_vendor )
+    switch ( boot_cpu_data.vendor )
     {
     case X86_VENDOR_INTEL:
         /*
@@ -97,10 +97,10 @@ static void __init arch_init_ideal_nops(void)
          * actually perform better with the "k8_nops" than with the SDM-
          * recommended NOPs.
          */
-        if ( boot_cpu_data.x86 != 6 )
+        if ( boot_cpu_data.family != 6 )
             break;
 
-        switch ( boot_cpu_data.x86_model )
+        switch ( boot_cpu_data.model )
         {
         case 0x0f ... 0x1b:
         case 0x1d ... 0x25:
@@ -111,7 +111,7 @@ static void __init arch_init_ideal_nops(void)
         break;
 
     case X86_VENDOR_AMD:
-        if ( boot_cpu_data.x86 <= 0xf )
+        if ( boot_cpu_data.family <= 0xf )
             ideal_nops = k8_nops;
         break;
     }
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 0fd8bdba70..5cd9d8c47d 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -96,12 +96,12 @@ static int modern_apic(void)
 {
     unsigned int lvr, version;
     /* AMD systems use old APIC versions, so check the CPU */
-    if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-        boot_cpu_data.x86 >= 0xf)
+    if (boot_cpu_data.vendor == X86_VENDOR_AMD &&
+        boot_cpu_data.family >= 0xf)
         return 1;
 
     /* Hygon systems use modern APIC */
-    if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
+    if (boot_cpu_data.vendor == X86_VENDOR_HYGON)
         return 1;
 
     lvr = apic_read(APIC_LVR);
@@ -447,7 +447,7 @@ void __init init_bsp_APIC(void)
     value |= APIC_SPIV_APIC_ENABLED;
     
     /* This bit is reserved on P4/Xeon and should be cleared */
-    if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
+    if ((boot_cpu_data.vendor == X86_VENDOR_INTEL) && (boot_cpu_data.family == 15))
         value &= ~APIC_SPIV_FOCUS_DISABLED;
     else
         value |= APIC_SPIV_FOCUS_DISABLED;
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index eb428f284e..2062d8779c 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -190,7 +190,7 @@ static void __init noinline probe_masking_msrs(void)
 	 */
 
 	/* Fam11 doesn't support masking at all. */
-	if (c->x86 == 0x11)
+	if (c->family == 0x11)
 		return;
 
 	cpuidmask_defaults._1cd =
@@ -202,7 +202,7 @@ static void __init noinline probe_masking_msrs(void)
 		cpuidmask_defaults._7ab0 =
 			_probe_mask_msr(MSR_AMD_L7S0_FEATURE_MASK, LCAP_7ab0);
 
-	if (c->x86 == 0x15 && c->cpuid_level >= 6 && cpuid_ecx(6))
+	if (c->family == 0x15 && c->cpuid_level >= 6 && cpuid_ecx(6))
 		cpuidmask_defaults._6c =
 			_probe_mask_msr(MSR_AMD_THRM_FEATURE_MASK, LCAP_6c);
 
@@ -219,7 +219,7 @@ static void __init noinline probe_masking_msrs(void)
 	       expected_levelling_cap, levelling_caps,
 	       (expected_levelling_cap ^ levelling_caps) & levelling_caps);
 	printk(XENLOG_WARNING "Fam %#x, model %#x level %#x\n",
-	       c->x86, c->x86_model, c->cpuid_level);
+	       c->family, c->model, c->cpuid_level);
 	printk(XENLOG_WARNING
 	       "If not running virtualised, please report a bug\n");
 }
@@ -428,7 +428,7 @@ int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, int osvw_id, ...)
 	u32 range;
 	u32 ms;
 	
-	if (cpu->x86_vendor != X86_VENDOR_AMD)
+	if (cpu->vendor != X86_VENDOR_AMD)
 		return 0;
 
 	if (osvw_id >= 0 && cpu_has(cpu, X86_FEATURE_OSVW)) {
@@ -449,9 +449,9 @@ int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, int osvw_id, ...)
 	/* OSVW unavailable or ID unknown, match family-model-stepping range */
 	va_start(ap, osvw_id);
 
-	ms = (cpu->x86_model << 4) | cpu->x86_mask;
+	ms = (cpu->model << 4) | cpu->stepping;
 	while ((range = va_arg(ap, int))) {
-		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
+		if ((cpu->family == AMD_MODEL_RANGE_FAMILY(range)) &&
 		    (ms >= AMD_MODEL_RANGE_START(range)) &&
 		    (ms <= AMD_MODEL_RANGE_END(range))) {
 			va_end(ap);
@@ -519,8 +519,8 @@ static void check_syscfg_dram_mod_en(void)
 {
 	uint64_t syscfg;
 
-	if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
-		(boot_cpu_data.x86 >= 0x0f)))
+	if (!((boot_cpu_data.vendor == X86_VENDOR_AMD) &&
+		(boot_cpu_data.family >= 0x0f)))
 		return;
 
 	rdmsrl(MSR_K8_SYSCFG, syscfg);
@@ -563,7 +563,7 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
                 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
                 c->x86_num_siblings = ((ebx >> 8) & 0xff) + 1;
 
-                if (c->x86 < 0x17)
+                if (c->family < 0x17)
                         c->compute_unit_id = ebx & 0xFF;
                 else {
                         c->cpu_core_id = ebx & 0xFF;
@@ -621,10 +621,10 @@ static void amd_process_freq(const struct cpuinfo_x86 *c,
 	unsigned int idx = 0, h;
 	uint64_t hi, lo, val;
 
-	if (c->x86 < 0x10 || c->x86 > 0x1A)
+	if (c->family < 0x10 || c->family > 0x1A)
 		return;
 
-	if (c->x86 < 0x17) {
+	if (c->family < 0x17) {
 		unsigned int node = 0;
 		uint64_t nbcfg;
 
@@ -674,7 +674,7 @@ static void amd_process_freq(const struct cpuinfo_x86 *c,
 				 * accounted for in order to correctly fetch the
 				 * nominal frequency of the processor.
 				 */
-				switch (c->x86) {
+				switch (c->family) {
 				case 0x10: idx = 1; break;
 				case 0x12: idx = 7; break;
 				case 0x14: idx = 7; break;
@@ -694,7 +694,7 @@ static void amd_process_freq(const struct cpuinfo_x86 *c,
 	}
 
 	lo = 0; /* gcc may not recognize the loop having at least 5 iterations */
-	for (h = c->x86 == 0x10 ? 5 : 8; h--; )
+	for (h = c->family == 0x10 ? 5 : 8; h--; )
 		if (!rdmsr_safe(0xC0010064 + h, lo) && (lo >> 63))
 			break;
 	if (!(lo >> 63))
@@ -704,18 +704,18 @@ static void amd_process_freq(const struct cpuinfo_x86 *c,
 	    !rdmsr_safe(0xC0010064 + idx, val) && (val >> 63) &&
 	    !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) {
 		if (nom_mhz)
-			*nom_mhz = amd_parse_freq(c->x86, val);
+			*nom_mhz = amd_parse_freq(c->family, val);
 		if (low_mhz)
-			*low_mhz = amd_parse_freq(c->x86, lo);
+			*low_mhz = amd_parse_freq(c->family, lo);
 		if (hi_mhz)
-			*hi_mhz = amd_parse_freq(c->x86, hi);
+			*hi_mhz = amd_parse_freq(c->family, hi);
 	} else if (h && !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) {
 		if (low_mhz)
-			*low_mhz = amd_parse_freq(c->x86, lo);
+			*low_mhz = amd_parse_freq(c->family, lo);
 		if (hi_mhz)
-			*hi_mhz = amd_parse_freq(c->x86, hi);
+			*hi_mhz = amd_parse_freq(c->family, hi);
 	} else if (low_mhz)
-		*low_mhz = amd_parse_freq(c->x86, lo);
+		*low_mhz = amd_parse_freq(c->family, lo);
 }
 
 void cf_check early_init_amd(struct cpuinfo_x86 *c)
@@ -794,7 +794,7 @@ static bool set_legacy_ssbd(const struct cpuinfo_x86 *c, bool enable)
 {
 	int bit = -1;
 
-	switch (c->x86) {
+	switch (c->family) {
 	case 0x15: bit = 54; break;
 	case 0x16: bit = 33; break;
 	case 0x17:
@@ -856,7 +856,7 @@ bool __init amd_setup_legacy_ssbd(void)
 {
 	unsigned int i;
 
-	if ((boot_cpu_data.x86 != 0x17 && boot_cpu_data.x86 != 0x18) ||
+	if ((boot_cpu_data.family != 0x17 && boot_cpu_data.family != 0x18) ||
 	    boot_cpu_data.x86_num_siblings <= 1 || opt_ssbd)
 		return true;
 
@@ -903,7 +903,7 @@ static void core_set_legacy_ssbd(bool enable)
 
 	BUG_ON(this_cpu(legacy_ssbd) == enable);
 
-	if ((c->x86 != 0x17 && c->x86 != 0x18) || c->x86_num_siblings <= 1) {
+	if ((c->family != 0x17 && c->family != 0x18) || c->x86_num_siblings <= 1) {
 		BUG_ON(!set_legacy_ssbd(c, enable));
 		return;
 	}
@@ -994,10 +994,10 @@ void amd_check_zenbleed(void)
 	 * position to care either way.  An admin doesn't want to be disabling
 	 * AVX as a mitigation on any build of Xen with this logic present.
 	 */
-	if (cpu_has_hypervisor || boot_cpu_data.x86 != 0x17)
+	if (cpu_has_hypervisor || boot_cpu_data.family != 0x17)
 		return;
 
-	switch (boot_cpu_data.x86_model) {
+	switch (boot_cpu_data.model) {
 	case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
 	case 0x60 ... 0x67: good_rev = 0x0860010b; break;
 	case 0x68 ... 0x6f: good_rev = 0x08608105; break;
@@ -1082,7 +1082,7 @@ static void amd_check_bp_cfg(void)
 	/*
 	 * AMD Erratum #1485.  Set bit 5, as instructed.
 	 */
-	if (!cpu_has_hypervisor && boot_cpu_data.x86 == 0x19 && is_zen4_uarch())
+	if (!cpu_has_hypervisor && boot_cpu_data.family == 0x19 && is_zen4_uarch())
 		new |= (1 << 5);
 
 	/*
@@ -1125,7 +1125,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	 * Errata 63 for SH-B3 steppings
 	 * Errata 122 for all steppings (F+ have it disabled by default)
 	 */
-	if (c->x86 == 15) {
+	if (c->family == 15) {
 		rdmsrl(MSR_K8_HWCR, value);
 		value |= 1 << 6;
 		wrmsrl(MSR_K8_HWCR, value);
@@ -1138,7 +1138,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	 */
 	__clear_bit(X86_FEATURE_PBE, c->x86_capability);
 	
-	if (c->x86 == 0xf && c->x86_model < 0x14
+	if (c->family == 0xf && c->model < 0x14
 	    && cpu_has(c, X86_FEATURE_LAHF_LM)) {
 		/*
 		 * Some BIOSes incorrectly force this feature, but only K8
@@ -1157,7 +1157,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	if (c == &boot_cpu_data && !cpu_has(c, X86_FEATURE_RSTR_FP_ERR_PTRS))
 		setup_force_cpu_cap(X86_BUG_FPU_PTRS);
 
-	if (c->x86 == 0x0f || c->x86 == 0x11)
+	if (c->family == 0x0f || c->family == 0x11)
 		/* Always dispatch serialising on this hardare. */
 		__set_bit(X86_FEATURE_LFENCE_DISPATCH, c->x86_capability);
 	else /* Implicily "== 0x10 || >= 0x12" by being 64bit. */
@@ -1165,12 +1165,12 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 
 	amd_init_ssbd(c);
 
-	if (c->x86 == 0x17)
+	if (c->family == 0x17)
 		amd_init_spectral_chicken();
 
 	/* Probe for NSCB on Zen2 CPUs when not virtualised */
 	if (!cpu_has_hypervisor && !cpu_has_nscb && c == &boot_cpu_data &&
-	    c->x86 == 0x17)
+	    c->family == 0x17)
 		detect_zen2_null_seg_behaviour();
 
 	/*
@@ -1192,7 +1192,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	if (c == &boot_cpu_data && !cpu_has_clflushopt)
 		setup_force_cpu_cap(X86_BUG_CLFLUSH_MFENCE);
 
-	switch(c->x86)
+	switch(c->family)
 	{
 	case 0xf ... 0x11:
 		disable_c1e(NULL);
@@ -1241,15 +1241,15 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		if (cpu_has(c, X86_FEATURE_ITSC)) {
 			__set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
 			__set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
-			if (c->x86 != 0x11)
+			if (c->family != 0x11)
 				__set_bit(X86_FEATURE_TSC_RELIABLE,
 					  c->x86_capability);
 		}
 	}
 
 	/* re-enable TopologyExtensions if switched off by BIOS */
-	if ((c->x86 == 0x15) &&
-	    (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
+	if ((c->family == 0x15) &&
+	    (c->model >= 0x10) && (c->model <= 0x1f) &&
 	    !cpu_has(c, X86_FEATURE_TOPOEXT) &&
 	    !rdmsr_safe(MSR_K8_EXT_FEATURE_MASK, value)) {
 		value |= 1ULL << 54;
@@ -1266,14 +1266,14 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	 * The way access filter has a performance penalty on some workloads.
 	 * Disable it on the affected CPUs.
 	 */
-	if (c->x86 == 0x15 && c->x86_model >= 0x02 && c->x86_model < 0x20 &&
+	if (c->family == 0x15 && c->model >= 0x02 && c->model < 0x20 &&
 	    !rdmsr_safe(MSR_AMD64_IC_CFG, value) && (value & 0x1e) != 0x1e)
 		wrmsr_safe(MSR_AMD64_IC_CFG, value | 0x1e);
 
         amd_get_topology(c);
 
 	/* Pointless to use MWAIT on Family10 as it does not deep sleep. */
-	if (c->x86 == 0x10)
+	if (c->family == 0x10)
 		__clear_bit(X86_FEATURE_MONITOR, c->x86_capability);
 
 	if (!cpu_has_amd_erratum(c, AMD_ERRATUM_121))
@@ -1290,7 +1290,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 		       "*** Pass \"allow_unsafe\" if you're trusting"
 		       " all your (PV) guest kernels. ***\n");
 
-	if (c->x86 == 0x16 && c->x86_model <= 0xf) {
+	if (c->family == 0x16 && c->model <= 0xf) {
 		if (c == &boot_cpu_data) {
 			l = pci_conf_read32(PCI_SBDF(0, 0, 0x18, 3), 0x58);
 			h = pci_conf_read32(PCI_SBDF(0, 0, 0x18, 3), 0x5c);
@@ -1318,7 +1318,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 					    smp_processor_id());
 			wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15));
 		}
-	} else if (c->x86 == 0x12) {
+	} else if (c->family == 0x12) {
 		rdmsrl(MSR_AMD64_DE_CFG, value);
 		if (!(value & (1U << 31))) {
 			if (c == &boot_cpu_data || opt_cpu_info)
@@ -1332,7 +1332,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	/* AMD CPUs do not support SYSENTER outside of legacy mode. */
 	__clear_bit(X86_FEATURE_SEP, c->x86_capability);
 
-	if (c->x86 == 0x10) {
+	if (c->family == 0x10) {
 		/* do this for boot cpu */
 		if (c == &boot_cpu_data)
 			check_enable_amd_mmconf_dmi();
@@ -1355,14 +1355,14 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	 * Family 0x12 and above processors have APIC timer
 	 * running in deep C states.
 	 */
-	if ( opt_arat && c->x86 > 0x11 )
+	if ( opt_arat && c->family > 0x11 )
 		__set_bit(X86_FEATURE_ARAT, c->x86_capability);
 
 	/*
 	 * Prior to Family 0x14, perf counters are not reset during warm reboot.
 	 * We have to reset them manually.
 	 */
-	if (nmi_watchdog != NMI_LOCAL_APIC && c->x86 < 0x14) {
+	if (nmi_watchdog != NMI_LOCAL_APIC && c->family < 0x14) {
 		wrmsrl(MSR_K7_PERFCTR0, 0);
 		wrmsrl(MSR_K7_PERFCTR1, 0);
 		wrmsrl(MSR_K7_PERFCTR2, 0);
@@ -1404,7 +1404,7 @@ static int __init cf_check amd_check_erratum_1474(void)
 	s_time_t delta;
 
 	if (cpu_has_hypervisor ||
-	    (boot_cpu_data.x86 != 0x17 && boot_cpu_data.x86 != 0x18))
+	    (boot_cpu_data.family != 0x17 && boot_cpu_data.family != 0x18))
 		return 0;
 
 	/*
diff --git a/xen/arch/x86/cpu/centaur.c b/xen/arch/x86/cpu/centaur.c
index 750168d1e8..d0e10cafc7 100644
--- a/xen/arch/x86/cpu/centaur.c
+++ b/xen/arch/x86/cpu/centaur.c
@@ -39,7 +39,7 @@ static void init_c3(struct cpuinfo_x86 *c)
 		}
 	}
 
-	if (c->x86 == 0x6 && c->x86_model >= 0xf) {
+	if (c->family == 0x6 && c->model >= 0xf) {
 		c->x86_cache_alignment = c->x86_clflush_size * 2;
 		__set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
 	}
@@ -50,7 +50,7 @@ static void init_c3(struct cpuinfo_x86 *c)
 
 static void cf_check init_centaur(struct cpuinfo_x86 *c)
 {
-	if (c->x86 == 6)
+	if (c->family == 6)
 		init_c3(c);
 }
 
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index e063fe790a..3738109a99 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -338,8 +338,8 @@ void __init early_cpu_init(bool verbose)
 	*(u32 *)&c->x86_vendor_id[8] = ecx;
 	*(u32 *)&c->x86_vendor_id[4] = edx;
 
-	c->x86_vendor = x86_cpuid_lookup_vendor(ebx, ecx, edx);
-	switch (c->x86_vendor) {
+	c->vendor = x86_cpuid_lookup_vendor(ebx, ecx, edx);
+	switch (c->vendor) {
 	case X86_VENDOR_INTEL:    intel_unlock_cpuid_leaves(c);
 				  actual_cpu = intel_cpu_dev;    break;
 	case X86_VENDOR_AMD:      actual_cpu = amd_cpu_dev;      break;
@@ -356,7 +356,7 @@ void __init early_cpu_init(bool verbose)
 	}
 
 	cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
-	c->x86 = get_cpu_family(eax, &c->x86_model, &c->x86_mask);
+	c->family = get_cpu_family(eax, &c->model, &c->stepping);
 
 	edx &= ~cleared_caps[FEATURESET_1d];
 	ecx &= ~cleared_caps[FEATURESET_1c];
@@ -400,8 +400,8 @@ void __init early_cpu_init(bool verbose)
 		printk(XENLOG_INFO
 		       "CPU Vendor: %s, Family %u (%#x), "
 		       "Model %u (%#x), Stepping %u (raw %08x)\n",
-		       x86_cpuid_vendor_to_str(c->x86_vendor), c->x86,
-		       c->x86, c->x86_model, c->x86_model, c->x86_mask,
+		       x86_cpuid_vendor_to_str(c->vendor), c->family,
+		       c->family, c->model, c->model, c->stepping,
 		       eax);
 
 	if (c->cpuid_level >= 7) {
@@ -442,7 +442,7 @@ void __init early_cpu_init(bool verbose)
 		paddr_bits -= (ebx >> 6) & 0x3f;
 	}
 
-	if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)))
+	if (!(c->vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)))
 		park_offline_cpus = opt_mce;
 
 	initialize_cpu_data(0);
@@ -452,10 +452,10 @@ void reset_cpuinfo(struct cpuinfo_x86 *c, bool keep_basic)
 {
     if ( !keep_basic )
     {
-        c->x86_vendor = 0;
-        c->x86 = 0;
-        c->x86_model = 0;
-        c->x86_mask = 0;
+        c->vendor = 0;
+        c->family = 0;
+        c->model = 0;
+        c->stepping = 0;
         memset(&c->x86_capability, 0, sizeof(c->x86_capability));
         memset(&c->x86_vendor_id, 0, sizeof(c->x86_vendor_id));
         memset(&c->x86_model_id, 0, sizeof(c->x86_model_id));
@@ -474,18 +474,18 @@ static void generic_identify(struct cpuinfo_x86 *c)
 	*(u32 *)&c->x86_vendor_id[8] = ecx;
 	*(u32 *)&c->x86_vendor_id[4] = edx;
 
-	c->x86_vendor = x86_cpuid_lookup_vendor(ebx, ecx, edx);
-	if (boot_cpu_data.x86_vendor != c->x86_vendor)
+	c->vendor = x86_cpuid_lookup_vendor(ebx, ecx, edx);
+	if (boot_cpu_data.vendor != c->vendor)
 		printk(XENLOG_ERR "CPU%u vendor %u mismatch against BSP %u\n",
-		       smp_processor_id(), c->x86_vendor,
-		       boot_cpu_data.x86_vendor);
+		       smp_processor_id(), c->vendor,
+		       boot_cpu_data.vendor);
 
 	/* Initialize the standard set of capabilities */
 	/* Note that the vendor-specific code below might override */
 
 	/* Model and family information. */
 	cpuid(1, &eax, &ebx, &ecx, &edx);
-	c->x86 = get_cpu_family(eax, &c->x86_model, &c->x86_mask);
+	c->family = get_cpu_family(eax, &c->model, &c->stepping);
 	c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
 	c->phys_proc_id = c->apicid;
 
@@ -610,7 +610,7 @@ void identify_cpu(struct cpuinfo_x86 *c)
 	if ( !c->x86_model_id[0] ) {
 		/* Last resort... */
 		snprintf(c->x86_model_id, sizeof(c->x86_model_id),
-			"%02x/%02x", c->x86_vendor, c->x86_model);
+			"%02x/%02x", c->vendor, c->model);
 	}
 
 	/* Now the feature flags better reflect actual CPU features! */
@@ -829,16 +829,16 @@ void print_cpu_info(unsigned int cpu)
 
 	printk("CPU%u: ", cpu);
 
-	vendor = x86_cpuid_vendor_to_str(c->x86_vendor);
+	vendor = x86_cpuid_vendor_to_str(c->vendor);
 	if (strncmp(c->x86_model_id, vendor, strlen(vendor)))
 		printk("%s ", vendor);
 
 	if (!c->x86_model_id[0])
-		printk("%d86", c->x86);
+		printk("%d86", c->family);
 	else
 		printk("%s", c->x86_model_id);
 
-	printk(" stepping %02x\n", c->x86_mask);
+	printk(" stepping %02x\n", c->stepping);
 }
 
 static cpumask_t cpu_initialized;
diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c
index f7508cc8fc..f454fbef33 100644
--- a/xen/arch/x86/cpu/hygon.c
+++ b/xen/arch/x86/cpu/hygon.c
@@ -36,12 +36,12 @@ static void cf_check init_hygon(struct cpuinfo_x86 *c)
 
 	/* Probe for NSCB on Zen2 CPUs when not virtualised */
 	if (!cpu_has_hypervisor && !cpu_has_nscb && c == &boot_cpu_data &&
-	    c->x86 == 0x18)
+	    c->family == 0x18)
 		detect_zen2_null_seg_behaviour();
 
 	/*
 	 * TODO: Check heuristic safety with Hygon first
-	if (c->x86 == 0x18)
+	if (c->family == 0x18)
 		amd_init_spectral_chicken();
 	 */
 
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 29144ffe37..60bb1a5ae7 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -86,7 +86,7 @@ static void __init check_memory_type_self_snoop_errata(void)
 	if (!boot_cpu_has(X86_FEATURE_SS))
 		return;
 
-	switch (boot_cpu_data.x86_model) {
+	switch (boot_cpu_data.model) {
 	case 0x0f: /* Merom */
 	case 0x16: /* Merom L */
 	case 0x17: /* Penryn */
@@ -137,10 +137,10 @@ static void __init probe_masking_msrs(void)
 	unsigned int exp_msr_basic, exp_msr_ext, exp_msr_xsave;
 
 	/* Only family 6 supports this feature. */
-	if (c->x86 != 6)
+	if (c->family != 6)
 		return;
 
-	switch (c->x86_model) {
+	switch (c->model) {
 	case 0x17: /* Yorkfield, Wolfdale, Penryn, Harpertown(DP) */
 	case 0x1d: /* Dunnington(MP) */
 		msr_basic = MSR_INTEL_MASK_V1_CPUID1;
@@ -191,7 +191,7 @@ static void __init probe_masking_msrs(void)
 	       expected_levelling_cap, levelling_caps,
 	       (expected_levelling_cap ^ levelling_caps) & levelling_caps);
 	printk(XENLOG_WARNING "Fam %#x, model %#x expected (%#x/%#x/%#x), "
-	       "got (%#x/%#x/%#x)\n", c->x86, c->x86_model,
+	       "got (%#x/%#x/%#x)\n", c->family, c->model,
 	       exp_msr_basic, exp_msr_ext, exp_msr_xsave,
 	       msr_basic, msr_ext, msr_xsave);
 	printk(XENLOG_WARNING
@@ -265,7 +265,7 @@ static void __init noinline intel_init_levelling(void)
 	 * so skip it altogether. In the case where Xen is virtualized these
 	 * MSRs may be emulated though, so we allow it in that case.
 	 */
-	if ((boot_cpu_data.x86 != 0xf || cpu_has_hypervisor) &&
+	if ((boot_cpu_data.family != 0xf || cpu_has_hypervisor) &&
 	    probe_cpuid_faulting()) {
 		expected_levelling_cap |= LCAP_faulting;
 		levelling_caps |= LCAP_faulting;
@@ -348,7 +348,7 @@ void intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c)
 static void cf_check early_init_intel(struct cpuinfo_x86 *c)
 {
 	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
-	if (c->x86 == 15 && c->x86_cache_alignment == 64)
+	if (c->family == 15 && c->x86_cache_alignment == 64)
 		c->x86_cache_alignment = 128;
 
 	if (c == &boot_cpu_data &&
@@ -358,8 +358,8 @@ static void cf_check early_init_intel(struct cpuinfo_x86 *c)
 	intel_unlock_cpuid_leaves(c);
 
 	/* CPUID workaround for Intel 0F33/0F34 CPU */
-	if (boot_cpu_data.x86 == 0xF && boot_cpu_data.x86_model == 3 &&
-	    (boot_cpu_data.x86_mask == 3 || boot_cpu_data.x86_mask == 4))
+	if (boot_cpu_data.vfm == INTEL_P4_PRESCOTT &&
+	    (boot_cpu_data.stepping == 3 || boot_cpu_data.stepping == 4))
 		paddr_bits = 36;
 
 	if (c == &boot_cpu_data) {
@@ -458,7 +458,7 @@ static void Intel_errata_workarounds(struct cpuinfo_x86 *c)
 {
 	unsigned long lo, hi;
 
-	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
+	if ( c->vfm == INTEL_P4_WILLAMETTE && c->stepping == 1 ) {
 		rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
 		if ((lo & (1<<9)) == 0) {
 			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
@@ -468,8 +468,8 @@ static void Intel_errata_workarounds(struct cpuinfo_x86 *c)
 		}
 	}
 
-	if (c->x86 == 6 && cpu_has_clflush &&
-	    (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
+	if (c->family == 6 && cpu_has_clflush &&
+	    (c->model == 29 || c->model == 46 || c->model == 47))
 		setup_force_cpu_cap(X86_BUG_CLFLUSH_MONITOR);
 
 	probe_c3_errata(c);
@@ -540,7 +540,7 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
         }
     }
 
-    switch ( c->x86 )
+    switch ( c->family )
     {
         static const unsigned short core_factors[] =
             { 26667, 13333, 20000, 16667, 33333, 10000, 40000 };
@@ -553,7 +553,7 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
         if ( !max_ratio )
             return;
 
-        switch ( c->x86_model )
+        switch ( c->model )
         {
         case 0x0e: /* Core */
         case 0x0f: case 0x16: case 0x17: case 0x1d: /* Core2 */
@@ -657,8 +657,8 @@ static void cf_check init_intel(struct cpuinfo_x86 *c)
 	/* Work around errata */
 	Intel_errata_workarounds(c);
 
-	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
-		(c->x86 == 0x6 && c->x86_model >= 0x0e))
+	if ((c->family == 0xf && c->model >= 0x03) ||
+		(c->family == 0x6 && c->model >= 0x0e))
 		__set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
 	if (cpu_has(c, X86_FEATURE_ITSC)) {
 		__set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c b/xen/arch/x86/cpu/intel_cacheinfo.c
index e88faa7545..a81d0764fb 100644
--- a/xen/arch/x86/cpu/intel_cacheinfo.c
+++ b/xen/arch/x86/cpu/intel_cacheinfo.c
@@ -168,15 +168,15 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c)
 	 * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
 	 * trace cache
 	 */
-	if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1 &&
-	    c->x86_vendor != X86_VENDOR_SHANGHAI)
+	if ((num_cache_leaves == 0 || c->family == 15) && c->cpuid_level > 1 &&
+	    c->vendor != X86_VENDOR_SHANGHAI)
 	{
 		/* supports eax=2  call */
 		unsigned int i, j, n, regs[4];
 		unsigned char *dp = (unsigned char *)regs;
 		int only_trace = 0;
 
-		if (num_cache_leaves != 0 && c->x86 == 15)
+		if (num_cache_leaves != 0 && c->family == 15)
 			only_trace = 1;
 
 		/* Number of times to iterate */
diff --git a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
index 7d48c9ab5f..fb52639e13 100644
--- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
+++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c
@@ -191,7 +191,7 @@ static void cf_check mce_amd_work_fn(void *data)
 
 void __init amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c)
 {
-	if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)))
+	if (!(c->vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)))
 		return;
 
 	/* Assume we are on K8 or newer AMD or Hygon CPU here */
diff --git a/xen/arch/x86/cpu/mcheck/mcaction.c b/xen/arch/x86/cpu/mcheck/mcaction.c
index bf7a0de965..236424569a 100644
--- a/xen/arch/x86/cpu/mcheck/mcaction.c
+++ b/xen/arch/x86/cpu/mcheck/mcaction.c
@@ -101,7 +101,7 @@ mc_memerr_dhandler(struct mca_binfo *binfo,
                       * not always precise. In that case, fallback to broadcast.
                       */
                      global->mc_domid != bank->mc_domid ||
-                     (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+                     (boot_cpu_data.vendor == X86_VENDOR_INTEL &&
                       (!(global->mc_gstatus & MCG_STATUS_LMCE) ||
                        !(d->vcpu[mc_vcpuid]->arch.vmce.mcg_ext_ctl &
                          MCG_EXT_CTL_LMCE_EN))) )
diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index bbc0d24732..8ebaae242e 100644
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -334,7 +334,7 @@ mcheck_mca_logout(enum mca_source who, struct mca_banks *bankmask,
                 mca_init_global(mc_flags, mig);
                 /* A hook here to get global extended msrs */
                 if ( IS_ENABLED(CONFIG_INTEL) &&
-                     boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+                     boot_cpu_data.vendor == X86_VENDOR_INTEL )
                     intel_get_extended_msrs(mig, mci);
             }
         }
@@ -564,8 +564,8 @@ bool mce_available(const struct cpuinfo_x86 *c)
  */
 unsigned int mce_firstbank(struct cpuinfo_x86 *c)
 {
-    return c->x86 == 6 &&
-           c->x86_vendor == X86_VENDOR_INTEL && c->x86_model < 0x1a;
+    return c->family == 6 &&
+           c->vendor == X86_VENDOR_INTEL && c->model < 0x1a;
 }
 
 static int show_mca_info(int inited, struct cpuinfo_x86 *c)
@@ -596,7 +596,7 @@ static int show_mca_info(int inited, struct cpuinfo_x86 *c)
         case mcheck_amd_famXX:
         case mcheck_hygon:
             printk("%s%s Fam%xh machine check reporting enabled\n",
-                   prefix, type_str[inited], c->x86);
+                   prefix, type_str[inited], c->family);
             break;
 
         case mcheck_none:
@@ -766,7 +766,7 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp)
     else if ( cpu_bank_alloc(cpu) )
         panic("Insufficient memory for MCE bank allocations\n");
 
-    switch ( c->x86_vendor )
+    switch ( c->vendor )
     {
 #ifdef CONFIG_AMD
     case X86_VENDOR_AMD:
@@ -777,7 +777,7 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp)
 
 #ifdef CONFIG_INTEL
     case X86_VENDOR_INTEL:
-        switch ( c->x86 )
+        switch ( c->family )
         {
         case 6:
         case 15:
@@ -866,7 +866,7 @@ static void x86_mcinfo_apei_save(
     memset(&m, 0, sizeof(struct mce));
 
     m.cpu = mc_global->mc_coreid;
-    m.cpuvendor = boot_cpu_data.x86_vendor;
+    m.cpuvendor = boot_cpu_data.vendor;
     m.cpuid = cpuid_eax(1);
     m.socketid = mc_global->mc_socketid;
     m.apicid = mc_global->mc_apicid;
@@ -967,10 +967,10 @@ static void cf_check __maybe_unused do_mc_get_cpu_info(void *v)
                         &xcp->mc_apicid, &xcp->mc_ncores,
                         &xcp->mc_ncores_active, &xcp->mc_nthreads);
     xcp->mc_cpuid_level = c->cpuid_level;
-    xcp->mc_family = c->x86;
-    xcp->mc_vendor = c->x86_vendor;
-    xcp->mc_model = c->x86_model;
-    xcp->mc_step = c->x86_mask;
+    xcp->mc_family = c->family;
+    xcp->mc_vendor = c->vendor;
+    xcp->mc_model = c->model;
+    xcp->mc_step = c->stepping;
     xcp->mc_cache_size = c->x86_cache_size;
     xcp->mc_cache_alignment = c->x86_cache_alignment;
     memcpy(xcp->mc_vendorid, c->x86_vendor_id, sizeof xcp->mc_vendorid);
@@ -1126,7 +1126,7 @@ static bool __maybe_unused x86_mc_msrinject_verify(struct xen_mc_msrinject *mci)
 
         if ( IS_MCA_BANKREG(reg, mci->mcinj_cpunr) )
         {
-            if ( c->x86_vendor == X86_VENDOR_AMD )
+            if ( c->vendor == X86_VENDOR_AMD )
             {
                 /*
                  * On AMD we can set MCi_STATUS_WREN in the
@@ -1161,15 +1161,15 @@ static bool __maybe_unused x86_mc_msrinject_verify(struct xen_mc_msrinject *mci)
             case MSR_F10_MC4_MISC1:
             case MSR_F10_MC4_MISC2:
             case MSR_F10_MC4_MISC3:
-                if ( c->x86_vendor != X86_VENDOR_AMD )
+                if ( c->vendor != X86_VENDOR_AMD )
                     reason = "only supported on AMD";
-                else if ( c->x86 < 0x10 )
+                else if ( c->family < 0x10 )
                     reason = "only supported on AMD Fam10h+";
                 break;
 
             /* MSRs that the HV will take care of */
             case MSR_K8_HWCR:
-                if ( c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
+                if ( c->vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
                     reason = "HV will operate HWCR";
                 else
                     reason = "only supported on AMD or Hygon";
diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h
index eba4b536c7..5c50453cb5 100644
--- a/xen/arch/x86/cpu/mcheck/mce.h
+++ b/xen/arch/x86/cpu/mcheck/mce.h
@@ -136,7 +136,7 @@ void x86_mcinfo_dump(struct mc_info *mi);
 
 static inline int mce_vendor_bank_msr(const struct vcpu *v, uint32_t msr)
 {
-    switch (boot_cpu_data.x86_vendor) {
+    switch (boot_cpu_data.vendor) {
     case X86_VENDOR_INTEL:
         if (msr >= MSR_IA32_MC0_CTL2 &&
             msr < MSR_IA32_MCx_CTL2(v->arch.vmce.mcg_cap & MCG_CAP_COUNT) )
diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mce_amd.c
index 4f06a3153b..690c72c455 100644
--- a/xen/arch/x86/cpu/mcheck/mce_amd.c
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -160,17 +160,17 @@ mcequirk_lookup_amd_quirkdata(const struct cpuinfo_x86 *c)
 {
     unsigned int i;
 
-    BUG_ON(c->x86_vendor != X86_VENDOR_AMD);
+    BUG_ON(c->vendor != X86_VENDOR_AMD);
 
     for ( i = 0; i < ARRAY_SIZE(mce_amd_quirks); i++ )
     {
-        if ( c->x86 != mce_amd_quirks[i].cpu_family )
+        if ( c->family != mce_amd_quirks[i].cpu_family )
             continue;
         if ( (mce_amd_quirks[i].cpu_model != ANY) &&
-             (mce_amd_quirks[i].cpu_model != c->x86_model) )
+             (mce_amd_quirks[i].cpu_model != c->model) )
             continue;
         if ( (mce_amd_quirks[i].cpu_stepping != ANY) &&
-             (mce_amd_quirks[i].cpu_stepping != c->x86_mask) )
+             (mce_amd_quirks[i].cpu_stepping != c->stepping) )
                 continue;
         return mce_amd_quirks[i].quirk;
     }
@@ -291,13 +291,13 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp)
     uint32_t i;
     enum mcequirk_amd_flags quirkflag = 0;
 
-    if ( c->x86_vendor != X86_VENDOR_HYGON )
+    if ( c->vendor != X86_VENDOR_HYGON )
         quirkflag = mcequirk_lookup_amd_quirkdata(c);
 
     /* Assume that machine check support is available.
      * The minimum provided support is at least the K8. */
     if ( bsp )
-        mce_handler_init(c->x86 == 0xf ? &k8_callbacks : &k10_callbacks);
+        mce_handler_init(c->family == 0xf ? &k8_callbacks : &k10_callbacks);
 
     for ( i = 0; i < this_cpu(nr_mce_banks); i++ )
     {
@@ -311,7 +311,7 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp)
         }
     }
 
-    if ( c->x86 == 0xf )
+    if ( c->family == 0xf )
         return mcheck_amd_k8;
 
     if ( quirkflag == MCEQUIRK_F10_GART )
@@ -337,6 +337,6 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp)
             ppin_msr = MSR_AMD_PPIN;
     }
 
-    return c->x86_vendor == X86_VENDOR_HYGON ?
+    return c->vendor == X86_VENDOR_HYGON ?
             mcheck_hygon : mcheck_amd_famXX;
 }
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 1e52b1ac25..c266c4e3b9 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -709,8 +709,7 @@ static bool mce_is_broadcast(struct cpuinfo_x86 *c)
      * DisplayFamily_DisplayModel encoding of 06H_EH and above,
      * a MCA signal is broadcast to all logical processors in the system
      */
-    if ( c->x86_vendor == X86_VENDOR_INTEL && c->x86 == 6 &&
-         c->x86_model >= 0xe )
+    if ( c->vendor == X86_VENDOR_INTEL && c->family == 6 && c->model >= 0xe )
         return true;
     return false;
 }
@@ -858,7 +857,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
      * other purposes.  Despite the late addition of a CPUID bit (rendering
      * the MSR architectural), keep using the same detection logic there.
      */
-    switch ( c->x86_model )
+    switch ( c->model )
     {
         uint64_t val;
 
diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c
index a9ee9bb94f..4e7c64abef 100644
--- a/xen/arch/x86/cpu/mcheck/non-fatal.c
+++ b/xen/arch/x86/cpu/mcheck/non-fatal.c
@@ -23,7 +23,7 @@ static int __init cf_check init_nonfatal_mce_checker(void)
 	/*
 	 * Check for non-fatal errors every MCE_RATE s
 	 */
-	switch (c->x86_vendor) {
+	switch (c->vendor) {
 #ifdef CONFIG_AMD
 	case X86_VENDOR_AMD:
 	case X86_VENDOR_HYGON:
diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index 5abdf4cb5f..bef4eedb31 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -45,7 +45,7 @@ void vmce_init_vcpu(struct vcpu *v)
     int i;
 
     /* global MCA MSRs init */
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+    if ( boot_cpu_data.vendor == X86_VENDOR_INTEL )
         v->arch.vmce.mcg_cap = INTEL_GUEST_MCG_CAP;
     else
         v->arch.vmce.mcg_cap = AMD_GUEST_MCG_CAP;
@@ -63,7 +63,7 @@ int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt)
 {
     unsigned long guest_mcg_cap;
 
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+    if ( boot_cpu_data.vendor == X86_VENDOR_INTEL )
         guest_mcg_cap = INTEL_GUEST_MCG_CAP | MCG_LMCE_P;
     else
         guest_mcg_cap = AMD_GUEST_MCG_CAP;
@@ -136,7 +136,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
         break;
 
     default:
-        switch ( boot_cpu_data.x86_vendor )
+        switch ( boot_cpu_data.vendor )
         {
 #ifdef CONFIG_INTEL
         case X86_VENDOR_CENTAUR:
@@ -273,7 +273,7 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
         break;
 
     default:
-        switch ( boot_cpu_data.x86_vendor )
+        switch ( boot_cpu_data.vendor )
         {
 #ifdef CONFIG_INTEL
         case X86_VENDOR_INTEL:
diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generic.c
index c587e9140e..190be7f1b4 100644
--- a/xen/arch/x86/cpu/mtrr/generic.c
+++ b/xen/arch/x86/cpu/mtrr/generic.c
@@ -218,9 +218,9 @@ static void __init print_mtrr_state(const char *level)
 			printk("%s  %u disabled\n", level, i);
 	}
 
-	if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-	     boot_cpu_data.x86 >= 0xf) ||
-	     boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
+	if ((boot_cpu_data.vendor == X86_VENDOR_AMD &&
+	     boot_cpu_data.family >= 0xf) ||
+	     boot_cpu_data.vendor == X86_VENDOR_HYGON) {
 		uint64_t syscfg, tom2;
 
 		rdmsrl(MSR_K8_SYSCFG, syscfg);
diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index f47fdfb569..37322c46c0 100644
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -1637,7 +1637,7 @@ static int __init mwait_idle_probe(void)
 		lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 
 	pr_debug(PREFIX "v" MWAIT_IDLE_VERSION " model %#x\n",
-		 boot_cpu_data.x86_model);
+		 boot_cpu_data.model);
 
 	pr_debug(PREFIX "lapic_timer_reliable_states %#x\n",
 		 lapic_timer_reliable_states);
@@ -1816,7 +1816,7 @@ bool __init mwait_pc10_supported(void)
 {
 	unsigned int ecx, edx, dummy;
 
-	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
+	if (boot_cpu_data.vendor != X86_VENDOR_INTEL ||
 	    !cpu_has_monitor ||
 	    boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 		return false;
diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c
index c28192ea26..64328bdf3f 100644
--- a/xen/arch/x86/cpu/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu.c
@@ -398,7 +398,7 @@ int vpmu_load(struct vcpu *v, bool from_guest)
 static int vpmu_arch_initialise(struct vcpu *v)
 {
     struct vpmu_struct *vpmu = vcpu_vpmu(v);
-    uint8_t vendor = current_cpu_data.x86_vendor;
+    uint8_t vendor = current_cpu_data.vendor;
     int ret;
 
     BUILD_BUG_ON(sizeof(struct xen_pmu_intel_ctxt) > XENPMU_CTXT_PAD_SZ);
@@ -815,7 +815,7 @@ static struct notifier_block cpu_nfb = {
 
 static int __init cf_check vpmu_init(void)
 {
-    int vendor = current_cpu_data.x86_vendor;
+    int vendor = current_cpu_data.vendor;
     const struct arch_vpmu_ops *ops = NULL;
 
     if ( !opt_vpmu_enabled )
diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
index a6117dfebf..16d8d8cef3 100644
--- a/xen/arch/x86/cpu/vpmu_amd.c
+++ b/xen/arch/x86/cpu/vpmu_amd.c
@@ -538,7 +538,7 @@ static const struct arch_vpmu_ops *__init common_init(void)
     if ( !num_counters )
     {
         printk(XENLOG_WARNING "VPMU: Unsupported CPU family %#x\n",
-               current_cpu_data.x86);
+               current_cpu_data.family);
         return ERR_PTR(-EINVAL);
     }
 
@@ -563,7 +563,7 @@ static const struct arch_vpmu_ops *__init common_init(void)
 
 const struct arch_vpmu_ops *__init amd_vpmu_init(void)
 {
-    switch ( current_cpu_data.x86 )
+    switch ( current_cpu_data.family )
     {
     case 0x15:
     case 0x17:
@@ -591,7 +591,7 @@ const struct arch_vpmu_ops *__init amd_vpmu_init(void)
 
 const struct arch_vpmu_ops *__init hygon_vpmu_init(void)
 {
-    switch ( current_cpu_data.x86 )
+    switch ( current_cpu_data.family )
     {
     case 0x18:
         num_counters = F15H_NUM_COUNTERS;
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index 7ce98ee42e..bc9d871056 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -923,7 +923,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void)
         return ERR_PTR(-EINVAL);
     }
 
-    if ( current_cpu_data.x86 != 6 )
+    if ( current_cpu_data.family != 6 )
     {
         printk(XENLOG_WARNING "VPMU: only family 6 is supported\n");
         return ERR_PTR(-EINVAL);
@@ -964,7 +964,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void)
               sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt;
 
     /* TODO: It's clearly incorrect for this to quirk all Intel Fam6 CPUs. */
-    pmc_quirk = current_cpu_data.x86 == 6;
+    pmc_quirk = current_cpu_data.family == 6;
 
     if ( sizeof(struct xen_pmu_data) + sizeof(uint64_t) * fixed_pmc_cnt +
          sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt > PAGE_SIZE )
diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 8dc68945f7..cd7df0f117 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -434,7 +434,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
 
     case 0xa:
         /* TODO: Rework vPMU control in terms of toolstack choices. */
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
+        if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
              !vpmu_available(v) )
             *res = EMPTY_LEAF;
         else
diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c
index 0b467fd4a4..864dd9e53e 100644
--- a/xen/arch/x86/dom0_build.c
+++ b/xen/arch/x86/dom0_build.c
@@ -572,10 +572,10 @@ int __init dom0_setup_permissions(struct domain *d)
             rc |= iomem_deny_access(d, mfn, mfn);
     }
     /* HyperTransport range. */
-    if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
+    if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
     {
         mfn = paddr_to_pfn(1UL <<
-                           (boot_cpu_data.x86 < 0x17 ? 40 : paddr_bits));
+                           (boot_cpu_data.family < 0x17 ? 40 : paddr_bits));
         rc |= iomem_deny_access(d, mfn - paddr_to_pfn(3UL << 32), mfn - 1);
     }
 
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 56c3816187..234e828bb3 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -317,7 +317,7 @@ void domain_cpu_policy_changed(struct domain *d)
             if ( cpu_has_htt )
                 edx |= cpufeat_mask(X86_FEATURE_HTT);
 
-            switch ( boot_cpu_data.x86_vendor )
+            switch ( boot_cpu_data.vendor )
             {
             case X86_VENDOR_INTEL:
                 /*
@@ -370,7 +370,7 @@ void domain_cpu_policy_changed(struct domain *d)
         {
             uint64_t mask = cpuidmask_defaults._6c;
 
-            if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+            if ( boot_cpu_data.vendor == X86_VENDOR_AMD )
                 mask &= (~0ULL << 32) | p->basic.raw[6].c;
 
             d->arch.pv.cpuidmasks->_6c = mask;
@@ -385,7 +385,7 @@ void domain_cpu_policy_changed(struct domain *d)
              * wholesale from the policy, but clamp the features in 7[0].ebx
              * per usual.
              */
-            if ( boot_cpu_data.x86_vendor &
+            if ( boot_cpu_data.vendor &
                  (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
                 mask = (((uint64_t)p->feat.max_subleaf << 32) |
                         ((uint32_t)mask & p->feat._7b0));
@@ -398,7 +398,7 @@ void domain_cpu_policy_changed(struct domain *d)
             uint64_t mask = cpuidmask_defaults.Da1;
             uint32_t eax = p->xstate.Da1;
 
-            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+            if ( boot_cpu_data.vendor == X86_VENDOR_INTEL )
                 mask &= (~0ULL << 32) | eax;
 
             d->arch.pv.cpuidmasks->Da1 = mask;
@@ -425,7 +425,7 @@ void domain_cpu_policy_changed(struct domain *d)
             if ( !(p->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
                 edx &= ~CPUID_COMMON_1D_FEATURES;
 
-            switch ( boot_cpu_data.x86_vendor )
+            switch ( boot_cpu_data.vendor )
             {
             case X86_VENDOR_INTEL:
                 mask &= ((uint64_t)edx << 32) | ecx;
@@ -455,7 +455,7 @@ void domain_cpu_policy_changed(struct domain *d)
         cpu_policy_updated(v);
 
         /* If PMU version is zero then the guest doesn't have VPMU */
-        if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+        if ( boot_cpu_data.vendor == X86_VENDOR_INTEL &&
              p->basic.pmu_version == 0 )
             vpmu_destroy(v);
     }
diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c
index ca577c0bde..872208ab37 100644
--- a/xen/arch/x86/e820.c
+++ b/xen/arch/x86/e820.c
@@ -426,7 +426,7 @@ static uint64_t __init mtrr_top_of_ram(void)
 
     /* By default we check only Intel systems. */
     if ( e820_mtrr_clip == -1 )
-        e820_mtrr_clip = boot_cpu_data.x86_vendor == X86_VENDOR_INTEL;
+        e820_mtrr_clip = boot_cpu_data.vendor == X86_VENDOR_INTEL;
 
     if ( !e820_mtrr_clip )
         return 0;
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index cb8ecd050d..2459b43d32 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3881,7 +3881,7 @@ void hvm_ud_intercept(struct cpu_user_regs *regs)
 {
     struct vcpu *cur = current;
     bool should_emulate =
-        cur->domain->arch.cpuid->x86_vendor != boot_cpu_data.x86_vendor;
+        cur->domain->arch.cpuid->x86_vendor != boot_cpu_data.vendor;
     struct hvm_emulate_ctxt ctxt;
 
     hvm_emulate_init_once(&ctxt, opt_hvm_fep ? NULL : is_cross_vendor, regs);
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index fce750ca1f..c79822787d 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -588,7 +588,7 @@ static void cf_check svm_cpuid_policy_changed(struct vcpu *v)
     u32 bitmap = vmcb_get_exception_intercepts(vmcb);
 
     if ( opt_hvm_fep ||
-         (v->domain->arch.cpuid->x86_vendor != boot_cpu_data.x86_vendor) )
+         (v->domain->arch.cpuid->x86_vendor != boot_cpu_data.vendor) )
         bitmap |= (1U << X86_EXC_UD);
     else
         bitmap &= ~(1U << X86_EXC_UD);
@@ -1053,7 +1053,7 @@ static void svm_guest_osvw_init(struct domain *d)
      * be conservative here and therefore we tell the guest that erratum 298
      * is present (because we really don't know).
      */
-    if ( osvw_length == 0 && boot_cpu_data.x86 == 0x10 )
+    if ( osvw_length == 0 && boot_cpu_data.family == 0x10 )
         svm->osvw.status |= 1;
 
     spin_unlock(&osvw_lock);
@@ -1788,7 +1788,7 @@ static int cf_check svm_msr_read_intercept(
         if ( !rdmsr_safe(msr, *msr_content) )
             break;
 
-        if ( boot_cpu_data.x86 == 0xf )
+        if ( boot_cpu_data.family == 0xf )
         {
             /*
              * Win2k8 x64 reads this MSR on revF chips, where it wasn't
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index ab8b1c87ec..a5eef5970c 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -2145,8 +2145,8 @@ int __init vmx_vmcs_init(void)
 
     if ( opt_ept_ad < 0 )
         /* Work around Erratum AVR41 on Avoton processors. */
-        opt_ept_ad = !(boot_cpu_data.x86 == 6 &&
-                       boot_cpu_data.x86_model == 0x4d);
+        opt_ept_ad = !(boot_cpu_data.family == 6 &&
+                       boot_cpu_data.model == 0x4d);
 
     ret = _vmx_cpu_up(true);
 
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index cb82d52ef0..f441e41531 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -497,10 +497,10 @@ static const struct lbr_info *__ro_after_init model_specific_lbr;
 
 static const struct lbr_info *__init get_model_specific_lbr(void)
 {
-    switch ( boot_cpu_data.x86 )
+    switch ( boot_cpu_data.family )
     {
     case 6:
-        switch ( boot_cpu_data.x86_model )
+        switch ( boot_cpu_data.model )
         {
         /* Core2 Duo */
         case 0x0f:
@@ -556,7 +556,7 @@ static const struct lbr_info *__init get_model_specific_lbr(void)
         break;
 
     case 15:
-        switch ( boot_cpu_data.x86_model )
+        switch ( boot_cpu_data.model )
         {
         /* Pentium4/Xeon with em64t */
         case 3: case 4: case 6:
@@ -792,7 +792,7 @@ static void cf_check vmx_cpuid_policy_changed(struct vcpu *v)
     int rc = 0;
 
     if ( opt_hvm_fep ||
-         (v->domain->arch.cpuid->x86_vendor != boot_cpu_data.x86_vendor) )
+         (v->domain->arch.cpuid->x86_vendor != boot_cpu_data.vendor) )
         v->arch.hvm.vmx.exception_bitmap |= (1U << X86_EXC_UD);
     else
         v->arch.hvm.vmx.exception_bitmap &= ~(1U << X86_EXC_UD);
@@ -2984,11 +2984,11 @@ static bool __init has_if_pschange_mc(void)
      * IF_PSCHANGE_MC is only known to affect Intel Family 6 processors at
      * this time.
      */
-    if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
-         boot_cpu_data.x86 != 6 )
+    if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
+         boot_cpu_data.family != 6 )
         return false;
 
-    switch ( boot_cpu_data.x86_model )
+    switch ( boot_cpu_data.model )
     {
         /*
          * Core processors since at least Nehalem are vulnerable.
@@ -3047,7 +3047,7 @@ static bool __init has_if_pschange_mc(void)
 
     default:
         printk("Unrecognised CPU model %#x - assuming vulnerable to IF_PSCHANGE_MC\n",
-               boot_cpu_data.x86_model);
+               boot_cpu_data.model);
         return true;
     }
 }
@@ -3336,11 +3336,11 @@ static void __init lbr_tsx_fixup_check(void)
      * fixed up as well.
      */
     if ( cpu_has_hle || cpu_has_rtm ||
-         boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
-         boot_cpu_data.x86 != 6 )
+         boot_cpu_data.vendor != X86_VENDOR_INTEL ||
+         boot_cpu_data.family != 6 )
         return;
 
-    switch ( boot_cpu_data.x86_model )
+    switch ( boot_cpu_data.model )
     {
     case 0x3c: /* HSM182, HSD172 - 4th gen Core */
     case 0x3f: /* HSE117 - Xeon E5 v3 */
@@ -3381,11 +3381,11 @@ static void __init ler_to_fixup_check(void)
      * that are not equal to bit[47].  Attempting to context switch this value
      * may cause a #GP.  Software should sign extend the MSR.
      */
-    if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
-         boot_cpu_data.x86 != 6 )
+    if ( boot_cpu_data.vendor != X86_VENDOR_INTEL ||
+         boot_cpu_data.family != 6 )
         return;
 
-    switch ( boot_cpu_data.x86_model )
+    switch ( boot_cpu_data.model )
     {
     case 0x3d: /* BDM131 - 5th gen Core */
     case 0x47: /* BDD??? - 5th gen Core (H-Processor line)
diff --git a/xen/arch/x86/i8259.c b/xen/arch/x86/i8259.c
index 5c7e21a751..d2a08661f8 100644
--- a/xen/arch/x86/i8259.c
+++ b/xen/arch/x86/i8259.c
@@ -419,7 +419,7 @@ void __init init_IRQ(void)
          * the interrupt.
          */
         cpumask_copy(desc->arch.cpu_mask,
-                     (boot_cpu_data.x86_vendor &
+                     (boot_cpu_data.vendor &
                       (X86_VENDOR_AMD | X86_VENDOR_HYGON) ? &cpumask_all
                                                           : cpumask_of(cpu)));
         desc->arch.vector = LEGACY_VECTOR(irq);
diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h
index 441a7ecc49..0fefb4acb1 100644
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -37,29 +37,16 @@
 #ifndef __ASSEMBLY__
 
 struct cpuinfo_x86 {
-    /* TODO: Phase out the x86 prefixed names. */
     union {
         struct {
-            union {
-                uint8_t x86_model;
-                uint8_t model;
-            };
-            union {
-                uint8_t x86;
-                uint8_t family;
-            };
-            union {
-                uint8_t x86_vendor;
-                uint8_t vendor;
-            };
+            uint8_t model;
+            uint8_t family;
+            uint8_t vendor;
             uint8_t _rsvd;             /* Use of this needs coordinating with VFM_MAKE() */
         };
         uint32_t vfm;                  /* Vendor Family Model */
     };
-    union {
-        uint8_t x86_mask;
-        uint8_t stepping;
-    };
+    uint8_t stepping;
 
     unsigned int cpuid_level;          /* Maximum supported CPUID level */
     unsigned int extended_cpuid_level; /* Maximum supported CPUID extended level */
diff --git a/xen/arch/x86/include/asm/intel-family.h b/xen/arch/x86/include/asm/intel-family.h
index d8c0bcc406..c71e744731 100644
--- a/xen/arch/x86/include/asm/intel-family.h
+++ b/xen/arch/x86/include/asm/intel-family.h
@@ -179,6 +179,10 @@
 #define INTEL_XEON_PHI_KNL		IFM(6, 0x57) /* Knights Landing */
 #define INTEL_XEON_PHI_KNM		IFM(6, 0x85) /* Knights Mill */
 
+/* Family 15 - NetBurst */
+#define INTEL_P4_WILLAMETTE		IFM(15, 0x01) /* Also Xeon Foster */
+#define INTEL_P4_PRESCOTT		IFM(15, 0x03)
+
 /* Family 5 */
 #define INTEL_FAM5_QUARK_X1000		0x09 /* Quark X1000 SoC */
 #define INTEL_QUARK_X1000		IFM(5, 0x09) /* Quark X1000 SoC */
diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index 1816e1c0b9..15d6b855cb 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -1480,7 +1480,7 @@ static void __init setup_ioapic_ids_from_mpc(void)
      * Don't check I/O APIC IDs for xAPIC systems. They have
      * no meaning without the serial APIC bus.
      */
-    if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+    if (!(boot_cpu_data.vendor == X86_VENDOR_INTEL)
         || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
         return;
 
diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c
index 556134f85a..c1d60395ed 100644
--- a/xen/arch/x86/irq.c
+++ b/xen/arch/x86/irq.c
@@ -1984,8 +1984,8 @@ void do_IRQ(struct cpu_user_regs *regs)
                      * interrupts have been delivered to CPUs
                      * different than the BSP.
                      */
-                    (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD |
-                                                 X86_VENDOR_HYGON))) &&
+                    (boot_cpu_data.vendor & (X86_VENDOR_AMD |
+                                             X86_VENDOR_HYGON))) &&
                    bogus_8259A_irq(vector - FIRST_LEGACY_VECTOR)) )
             {
                 printk("CPU%u: No irq handler for vector %02x (IRQ %d%s)\n",
diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c
index e74a714f50..38ba90d1cb 100644
--- a/xen/arch/x86/mpparse.c
+++ b/xen/arch/x86/mpparse.c
@@ -511,9 +511,9 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
 	/* Either an integrated APIC or a discrete 82489DX. */
 	processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
 	processor.mpc_cpuflag = CPU_ENABLED;
-	processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
-				   (boot_cpu_data.x86_model << 4) |
-				   boot_cpu_data.x86_mask;
+	processor.mpc_cpufeature = (boot_cpu_data.family << 8) |
+				   (boot_cpu_data.model << 4) |
+				   boot_cpu_data.stepping;
 	processor.mpc_featureflag =
             boot_cpu_data.x86_capability[FEATURESET_1d];
 	processor.mpc_reserved[0] = 0;
@@ -891,7 +891,7 @@ void __init mp_register_ioapic (
 	mp_ioapics[idx].mpc_apicaddr = address;
 
 	set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
-	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+	if ((boot_cpu_data.vendor == X86_VENDOR_INTEL)
 		&& !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
 		tmpid = io_apic_get_unique_id(idx, id);
 	else
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 2cd46b6c8a..ffee35daed 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -169,7 +169,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
 
     case MSR_IA32_PLATFORM_ID:
         if ( !(cp->x86_vendor & X86_VENDOR_INTEL) ||
-             !(boot_cpu_data.x86_vendor & X86_VENDOR_INTEL) )
+             !(boot_cpu_data.vendor & X86_VENDOR_INTEL) )
             goto gp_fault;
         rdmsrl(MSR_IA32_PLATFORM_ID, *val);
         break;
@@ -189,7 +189,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
          * the guest.
          */
         if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) ||
-             !(boot_cpu_data.x86_vendor &
+             !(boot_cpu_data.vendor &
                (X86_VENDOR_INTEL | X86_VENDOR_AMD)) ||
              rdmsr_safe(MSR_AMD_PATCHLEVEL, *val) )
             goto gp_fault;
diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c
index 9793fa2316..c61167fab8 100644
--- a/xen/arch/x86/nmi.c
+++ b/xen/arch/x86/nmi.c
@@ -216,12 +216,12 @@ void disable_lapic_nmi_watchdog(void)
 {
     if (nmi_active <= 0)
         return;
-    switch (boot_cpu_data.x86_vendor) {
+    switch (boot_cpu_data.vendor) {
     case X86_VENDOR_AMD:
         wrmsr(MSR_K7_EVNTSEL0, 0, 0);
         break;
     case X86_VENDOR_INTEL:
-        switch (boot_cpu_data.x86) {
+        switch (boot_cpu_data.family) {
         case 6:
             wrmsr(MSR_P6_EVNTSEL(0), 0, 0);
             break;
@@ -362,7 +362,7 @@ static void setup_p4_watchdog(void)
         clear_msr_range(0x3F1, 2);
     /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
        docs doesn't fully define it, so leave it alone for now. */
-    if (boot_cpu_data.x86_model >= 0x3) {
+    if (boot_cpu_data.model >= 0x3) {
         /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */
         clear_msr_range(0x3A0, 26);
         clear_msr_range(0x3BC, 3);
@@ -387,16 +387,16 @@ void setup_apic_nmi_watchdog(void)
     if ( nmi_watchdog == NMI_NONE )
         return;
 
-    switch ( boot_cpu_data.x86_vendor )
+    switch ( boot_cpu_data.vendor )
     {
     case X86_VENDOR_AMD:
         setup_k7_watchdog();
         break;
 
     case X86_VENDOR_INTEL:
-        switch (boot_cpu_data.x86) {
+        switch (boot_cpu_data.family) {
         case 6:
-            setup_p6_watchdog((boot_cpu_data.x86_model < 14) 
+            setup_p6_watchdog((boot_cpu_data.model < 14)
                               ? P6_EVENT_CPU_CLOCKS_NOT_HALTED
                               : CORE_EVENT_CPU_CLOCKS_NOT_HALTED);
             break;
diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c
index 3eba791889..65faf2b6f9 100644
--- a/xen/arch/x86/platform_hypercall.c
+++ b/xen/arch/x86/platform_hypercall.c
@@ -640,9 +640,9 @@ ret_t do_platform_op(
             const struct cpuinfo_x86 *c = &cpu_data[ver->xen_cpuid];
 
             memcpy(ver->vendor_id, c->x86_vendor_id, sizeof(ver->vendor_id));
-            ver->family = c->x86;
-            ver->model = c->x86_model;
-            ver->stepping = c->x86_mask;
+            ver->family = c->family;
+            ver->model = c->model;
+            ver->stepping = c->stepping;
         }
 
         ver->max_present = cpumask_last(&cpu_present_map);
diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c
index 9334da1dab..b089a1e348 100644
--- a/xen/arch/x86/pv/domain.c
+++ b/xen/arch/x86/pv/domain.c
@@ -173,7 +173,7 @@ static int __init cf_check pge_init(void)
 {
     if ( opt_global_pages == -1 )
         opt_global_pages = !cpu_has_hypervisor ||
-                           !(boot_cpu_data.x86_vendor &
+                           !(boot_cpu_data.vendor &
                              (X86_VENDOR_AMD | X86_VENDOR_HYGON));
 
     return 0;
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index f3f012f8fb..e64ebad938 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -243,8 +243,8 @@ static bool pci_cfg_ok(struct domain *currd, unsigned int start,
     start |= CF8_ADDR_LO(currd->arch.pci_cf8);
     /* AMD extended configuration space access? */
     if ( CF8_ADDR_HI(currd->arch.pci_cf8) &&
-         boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-         boot_cpu_data.x86 >= 0x10 && boot_cpu_data.x86 < 0x17 )
+         boot_cpu_data.vendor == X86_VENDOR_AMD &&
+         boot_cpu_data.family >= 0x10 && boot_cpu_data.family < 0x17 )
     {
         uint64_t msr_val;
 
@@ -867,7 +867,7 @@ static uint64_t guest_efer(const struct domain *d)
      */
     if ( is_pv_32bit_domain(d) )
         val &= ~(EFER_LME | EFER_LMA |
-                 (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL
+                 (boot_cpu_data.vendor == X86_VENDOR_INTEL
                   ? EFER_SCE : 0));
     return val;
 }
@@ -942,7 +942,7 @@ static int cf_check read_msr(
     case MSR_K8_PSTATE5:
     case MSR_K8_PSTATE6:
     case MSR_K8_PSTATE7:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD )
+        if ( boot_cpu_data.vendor != X86_VENDOR_AMD )
             break;
         if ( unlikely(is_cpufreq_controller(currd)) )
             goto normal;
@@ -950,8 +950,8 @@ static int cf_check read_msr(
         return X86EMUL_OKAY;
 
     case MSR_FAM10H_MMIO_CONF_BASE:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >= 0x17 )
+        if ( boot_cpu_data.vendor != X86_VENDOR_AMD ||
+             boot_cpu_data.family < 0x10 || boot_cpu_data.family >= 0x17 )
             break;
         /* fall through */
     case MSR_AMD64_NB_CFG:
@@ -975,13 +975,13 @@ static int cf_check read_msr(
     case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3):
     case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2:
     case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
-        if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+        if ( boot_cpu_data.vendor == X86_VENDOR_INTEL )
         {
             vpmu_msr = true;
             /* fall through */
     case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
     case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
-            if ( vpmu_msr || (boot_cpu_data.x86_vendor &
+            if ( vpmu_msr || (boot_cpu_data.vendor &
                               (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
             {
                 if ( vpmu_do_rdmsr(reg, val) )
@@ -1084,7 +1084,7 @@ static int cf_check write_msr(
     case MSR_K8_PSTATE6:
     case MSR_K8_PSTATE7:
     case MSR_K8_HWCR:
-        if ( !(boot_cpu_data.x86_vendor &
+        if ( !(boot_cpu_data.vendor &
                (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
             break;
         if ( likely(!is_cpufreq_controller(currd)) ||
@@ -1103,8 +1103,8 @@ static int cf_check write_msr(
         break;
 
     case MSR_FAM10H_MMIO_CONF_BASE:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-             boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >= 0x17 )
+        if ( boot_cpu_data.vendor != X86_VENDOR_AMD ||
+             boot_cpu_data.family < 0x10 || boot_cpu_data.family >= 0x17 )
             break;
         if ( !is_hwdom_pinned_vcpu(curr) )
             return X86EMUL_OKAY;
@@ -1132,7 +1132,7 @@ static int cf_check write_msr(
 
     case MSR_IA32_MPERF:
     case MSR_IA32_APERF:
-        if ( !(boot_cpu_data.x86_vendor &
+        if ( !(boot_cpu_data.vendor &
                (X86_VENDOR_INTEL | X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
             break;
         if ( likely(!is_cpufreq_controller(currd)) ||
@@ -1142,7 +1142,7 @@ static int cf_check write_msr(
 
     case MSR_IA32_THERM_CONTROL:
     case MSR_IA32_ENERGY_PERF_BIAS:
-        if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
+        if ( boot_cpu_data.vendor != X86_VENDOR_INTEL )
             break;
         if ( !is_hwdom_pinned_vcpu(curr) || wrmsr_safe(reg, val) == 0 )
             return X86EMUL_OKAY;
@@ -1152,12 +1152,12 @@ static int cf_check write_msr(
     case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3):
     case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2:
     case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
-        if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+        if ( boot_cpu_data.vendor == X86_VENDOR_INTEL )
         {
             vpmu_msr = true;
     case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5:
     case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3:
-            if ( vpmu_msr || (boot_cpu_data.x86_vendor &
+            if ( vpmu_msr || (boot_cpu_data.vendor &
                               (X86_VENDOR_AMD | X86_VENDOR_HYGON)) )
             {
                 if ( (vpmu_mode & XENPMU_MODE_ALL) &&
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 1543dd251c..94e914201c 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1392,7 +1392,7 @@ void asmlinkage __init noreturn __start_xen(void)
          * supervisor shadow stacks are now safe to use.
          */
         bool cpu_has_bug_shstk_fracture =
-            boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
+            boot_cpu_data.vendor == X86_VENDOR_INTEL &&
             !boot_cpu_has(X86_FEATURE_CET_SSS);
 
         /*
@@ -2024,10 +2024,10 @@ void asmlinkage __init noreturn __start_xen(void)
 
     /* Do not enable SMEP/SMAP in PV shim on AMD and Hygon by default */
     if ( opt_smep == -1 )
-        opt_smep = !pv_shim || !(boot_cpu_data.x86_vendor &
+        opt_smep = !pv_shim || !(boot_cpu_data.vendor &
                                  (X86_VENDOR_AMD | X86_VENDOR_HYGON));
     if ( opt_smap == -1 )
-        opt_smap = !pv_shim || !(boot_cpu_data.x86_vendor &
+        opt_smap = !pv_shim || !(boot_cpu_data.vendor &
                                  (X86_VENDOR_AMD | X86_VENDOR_HYGON));
 
     if ( !opt_smep )
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index a8385b26ae..06ab71171c 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -30,10 +30,10 @@ static void __init init_ler(void)
      * Intel Pentium 4 is the only known CPU to not use the architectural MSR
      * indicies.
      */
-    switch ( boot_cpu_data.x86_vendor )
+    switch ( boot_cpu_data.vendor )
     {
     case X86_VENDOR_INTEL:
-        if ( boot_cpu_data.x86 == 0xf )
+        if ( boot_cpu_data.family == 0xf )
         {
             msr = MSR_P4_LER_FROM_LIP;
             break;
diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c
index fbdd05971c..52636462d9 100644
--- a/xen/arch/x86/tsx.c
+++ b/xen/arch/x86/tsx.c
@@ -148,8 +148,8 @@ void tsx_init(void)
             {
                 printk(XENLOG_ERR
                        "FIRMWARE BUG: CPU %02x-%02x-%02x, ucode 0x%08x: RTM_ALWAYS_ABORT vs RTM mismatch\n",
-                       boot_cpu_data.x86, boot_cpu_data.x86_model,
-                       boot_cpu_data.x86_mask, this_cpu(cpu_sig).rev);
+                       boot_cpu_data.family, boot_cpu_data.model,
+                       boot_cpu_data.stepping, this_cpu(cpu_sig).rev);
 
                 setup_clear_cpu_cap(X86_FEATURE_RTM_ALWAYS_ABORT);
                 setup_clear_cpu_cap(X86_FEATURE_TSX_FORCE_ABORT);
diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthrough/amd/iommu_init.c
index 3f6d2f5db5..476d569e81 100644
--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -835,9 +835,9 @@ static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
 {
     u32 value;
 
-    if ( (boot_cpu_data.x86 != 0x15) ||
-         (boot_cpu_data.x86_model < 0x10) ||
-         (boot_cpu_data.x86_model > 0x1f) )
+    if ( (boot_cpu_data.family != 0x15) ||
+         (boot_cpu_data.model < 0x10) ||
+         (boot_cpu_data.model > 0x1f) )
         return;
 
     pci_conf_write32(iommu->sbdf, 0xf0, 0x90);
-- 
2.50.1



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Subject: Re: [PATCH v5 25/25] drm/xlnx: Compute dumb-buffer sizes with
 drm_mode_size_dumb()
To: Thomas Zimmermann 
Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org,
 freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
 imx@lists.linux.dev, linux-samsung-soc@vger.kernel.org,
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 linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org,
 intel-xe@lists.freedesktop.org, xen-devel@lists.xenproject.org,
 Laurent Pinchart , simona@ffwll.ch,
 airlied@gmail.com, mripard@kernel.org, maarten.lankhorst@linux.intel.com,
 geert@linux-m68k.org
References: <20250613090431.127087-1-tzimmermann@suse.de>
 <20250613090431.127087-26-tzimmermann@suse.de>
Content-Language: en-US
From: Tomi Valkeinen 
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In-Reply-To: <20250613090431.127087-26-tzimmermann@suse.de>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit

On 13/06/2025 12:00, Thomas Zimmermann wrote:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
> buffer size. Align the pitch according to hardware requirements.
> 
> Signed-off-by: Thomas Zimmermann 
> Cc: Laurent Pinchart 
> Cc: Tomi Valkeinen 
> ---
>  drivers/gpu/drm/xlnx/zynqmp_kms.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c b/drivers/gpu/drm/xlnx/zynqmp_kms.c
> index b47463473472..7ea0cd4f71d3 100644
> --- a/drivers/gpu/drm/xlnx/zynqmp_kms.c
> +++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c
> @@ -19,6 +19,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -363,10 +364,12 @@ static int zynqmp_dpsub_dumb_create(struct drm_file *file_priv,
>  				    struct drm_mode_create_dumb *args)
>  {
>  	struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(drm);
> -	unsigned int pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
> +	int ret;
>  
>  	/* Enforce the alignment constraints of the DMA engine. */
> -	args->pitch = ALIGN(pitch, dpsub->dma_align);
> +	ret = drm_mode_size_dumb(drm, args, dpsub->dma_align, 0);
> +	if (ret)
> +		return ret;
>  
>  	return drm_gem_dma_dumb_create_internal(file_priv, drm, args);
>  }

Reviewed-by: Tomi Valkeinen 

 Tomi



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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v5 04/25] drm/gem-shmem: Compute dumb-buffer sizes with
 drm_mode_size_dumb()
To: Thomas Zimmermann 
Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org,
 freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
 imx@lists.linux.dev, linux-samsung-soc@vger.kernel.org,
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 linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org,
 intel-xe@lists.freedesktop.org, xen-devel@lists.xenproject.org,
 simona@ffwll.ch, airlied@gmail.com, mripard@kernel.org,
 maarten.lankhorst@linux.intel.com, geert@linux-m68k.org
References: <20250613090431.127087-1-tzimmermann@suse.de>
 <20250613090431.127087-5-tzimmermann@suse.de>
Content-Language: en-US
From: Tomi Valkeinen 
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On 13/06/2025 12:00, Thomas Zimmermann wrote:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
> buffer size. Align the pitch to a multiple of 8.
> 
> Signed-off-by: Thomas Zimmermann 
> ---
>  drivers/gpu/drm/drm_gem_shmem_helper.c | 16 +++++-----------
>  1 file changed, 5 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c
> index 8ac0b1fa5287..0fc09484dfa6 100644
> --- a/drivers/gpu/drm/drm_gem_shmem_helper.c
> +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
> @@ -18,6 +18,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -518,18 +519,11 @@ EXPORT_SYMBOL_GPL(drm_gem_shmem_purge_locked);
>  int drm_gem_shmem_dumb_create(struct drm_file *file, struct drm_device *dev,
>  			      struct drm_mode_create_dumb *args)
>  {
> -	u32 min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
> +	int ret;
>  
> -	if (!args->pitch || !args->size) {
> -		args->pitch = min_pitch;
> -		args->size = PAGE_ALIGN(args->pitch * args->height);
> -	} else {
> -		/* ensure sane minimum values */
> -		if (args->pitch < min_pitch)
> -			args->pitch = min_pitch;
> -		if (args->size < args->pitch * args->height)
> -			args->size = PAGE_ALIGN(args->pitch * args->height);
> -	}
> +	ret = drm_mode_size_dumb(dev, args, SZ_8, 0);
> +	if (ret)
> +		return ret;
>  
>  	return drm_gem_shmem_create_with_handle(file, dev, args->size, &args->handle);
>  }

Reviewed-by: Tomi Valkeinen 

 Tomi



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Subject: Re: [PATCH] x86: Remove x86 prefixed names from cpuinfo
To: Kevin Lampis 
Cc: andrew.cooper3@citrix.com, roger.pau@citrix.com,
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On 08.08.2025 12:43, Kevin Lampis wrote:
> struct cpuinfo_x86
>   .x86        => .family
>   .x86_vendor => .vendor
>   .x86_model  => .model
>   .x86_mask   => .stepping
> 
> No functional change.
> 
> Signed-off-by: Kevin Lampis 
> ---
>  xen/arch/x86/acpi/cpu_idle.c             | 20 +++---
>  xen/arch/x86/acpi/cpufreq/acpi.c         |  2 +-
>  xen/arch/x86/acpi/cpufreq/cpufreq.c      |  4 +-
>  xen/arch/x86/acpi/cpufreq/powernow.c     |  4 +-
>  xen/arch/x86/alternative.c               |  8 +--
>  xen/arch/x86/apic.c                      |  8 +--
>  xen/arch/x86/cpu/amd.c                   | 84 ++++++++++++------------
>  xen/arch/x86/cpu/centaur.c               |  4 +-
>  xen/arch/x86/cpu/common.c                | 38 +++++------
>  xen/arch/x86/cpu/hygon.c                 |  4 +-
>  xen/arch/x86/cpu/intel.c                 | 30 ++++-----
>  xen/arch/x86/cpu/intel_cacheinfo.c       |  6 +-
>  xen/arch/x86/cpu/mcheck/amd_nonfatal.c   |  2 +-
>  xen/arch/x86/cpu/mcheck/mcaction.c       |  2 +-
>  xen/arch/x86/cpu/mcheck/mce.c            | 30 ++++-----
>  xen/arch/x86/cpu/mcheck/mce.h            |  2 +-
>  xen/arch/x86/cpu/mcheck/mce_amd.c        | 16 ++---
>  xen/arch/x86/cpu/mcheck/mce_intel.c      |  5 +-
>  xen/arch/x86/cpu/mcheck/non-fatal.c      |  2 +-
>  xen/arch/x86/cpu/mcheck/vmce.c           |  8 +--
>  xen/arch/x86/cpu/mtrr/generic.c          |  6 +-
>  xen/arch/x86/cpu/mwait-idle.c            |  4 +-
>  xen/arch/x86/cpu/vpmu.c                  |  4 +-
>  xen/arch/x86/cpu/vpmu_amd.c              |  6 +-
>  xen/arch/x86/cpu/vpmu_intel.c            |  4 +-
>  xen/arch/x86/cpuid.c                     |  2 +-
>  xen/arch/x86/dom0_build.c                |  4 +-
>  xen/arch/x86/domain.c                    | 12 ++--
>  xen/arch/x86/e820.c                      |  2 +-
>  xen/arch/x86/hvm/hvm.c                   |  2 +-
>  xen/arch/x86/hvm/svm/svm.c               |  6 +-
>  xen/arch/x86/hvm/vmx/vmcs.c              |  4 +-
>  xen/arch/x86/hvm/vmx/vmx.c               | 28 ++++----
>  xen/arch/x86/i8259.c                     |  2 +-
>  xen/arch/x86/include/asm/cpufeature.h    | 21 ++----
>  xen/arch/x86/include/asm/intel-family.h  |  4 ++
>  xen/arch/x86/io_apic.c                   |  2 +-
>  xen/arch/x86/irq.c                       |  4 +-
>  xen/arch/x86/mpparse.c                   |  8 +--
>  xen/arch/x86/msr.c                       |  4 +-
>  xen/arch/x86/nmi.c                       | 12 ++--
>  xen/arch/x86/platform_hypercall.c        |  6 +-
>  xen/arch/x86/pv/domain.c                 |  2 +-
>  xen/arch/x86/pv/emul-priv-op.c           | 30 ++++-----
>  xen/arch/x86/setup.c                     |  6 +-
>  xen/arch/x86/traps-setup.c               |  4 +-
>  xen/arch/x86/tsx.c                       |  4 +-
>  xen/drivers/passthrough/amd/iommu_init.c |  6 +-
>  48 files changed, 234 insertions(+), 244 deletions(-)

Can you perhaps get this broken up some? The bigger such a patch, the easier it
is that one unintended change slips through.

When doing the conversion wholesale, backporting considerations also come into
play: More adjustments may then need making all in one go when crossing the
4.21 / 4.20 boundary.

Jan


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Date: Fri, 8 Aug 2025 12:05:33 +0100
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Subject: Re: [PATCH] x86: Remove x86 prefixed names from cpuinfo
To: Kevin Lampis , xen-devel@lists.xenproject.org
Cc: jbeulich@suse.com, roger.pau@citrix.com
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On 08/08/2025 11:43 am, Kevin Lampis wrote:
> diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
> index d60a07bfd5..95a626f49c 100644
> --- a/xen/arch/x86/acpi/cpu_idle.c
> +++ b/xen/arch/x86/acpi/cpu_idle.c
> @@ -1059,8 +1059,8 @@ static void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flag
>       * is not required while entering C3 type state on
>       * P4, Core and beyond CPUs
>       */
> -    if ( c->x86_vendor == X86_VENDOR_INTEL &&
> -        (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14)) )
> +    if ( c->vendor == X86_VENDOR_INTEL &&
> +        (c->family > 0x6 || (c->family == 6 && c->model >= 14)) )
>              flags->bm_control = 0;
>  }

One of the purposes of the name change was to audit every use of these
fields for safety.

This is an example which needs reworking.  It is technically safe with
Family 18/19, because of the way the relation works, but


> @@ -468,8 +468,8 @@ static void Intel_errata_workarounds(struct
> cpuinfo_x86 *c) } } - if (c->x86 == 6 && cpu_has_clflush && -
> (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) + if
> (c->family == 6 && cpu_has_clflush && + (c->model == 29 || c->model ==
> 46 || c->model == 47)) setup_force_cpu_cap(X86_BUG_CLFLUSH_MONITOR);
> probe_c3_errata(c);

This is one which wants converting to using real CPU names.

Also, this really cannot be one giant patch.  It's unreviewable by shear
volume of change (and isn't a mechanical change that can be trivially
confirmed).

Perhaps start by doing a patch covering mcheck (but even then you've got
one conversion to a real CPU name I can see), and one covering vPMU. 
They're both not oneliners, and about the right order of magnitude for a
change like this.

~Andrew




From xen-devel-bounces@lists.xenproject.org Fri Aug 08 11:40:38 2025
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Date: Fri, 8 Aug 2025 13:45:54 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v5 17/25] drm/renesas/rcar-du: Compute dumb-buffer sizes
 with drm_mode_size_dumb()
To: Thomas Zimmermann 
Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org,
 freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org,
 imx@lists.linux.dev, linux-samsung-soc@vger.kernel.org,
 nouveau@lists.freedesktop.org, virtualization@lists.linux.dev,
 spice-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org,
 linux-rockchip@lists.infradead.org, linux-tegra@vger.kernel.org,
 intel-xe@lists.freedesktop.org, xen-devel@lists.xenproject.org,
 Laurent Pinchart ,
 Kieran Bingham , simona@ffwll.ch,
 airlied@gmail.com, mripard@kernel.org, maarten.lankhorst@linux.intel.com,
 geert@linux-m68k.org
References: <20250613090431.127087-1-tzimmermann@suse.de>
 <20250613090431.127087-18-tzimmermann@suse.de>
Content-Language: en-US
From: Tomi Valkeinen 
In-Reply-To: <20250613090431.127087-18-tzimmermann@suse.de>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit

On 13/06/2025 12:00, Thomas Zimmermann wrote:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
> buffer size. Align the pitch according to hardware requirements.
> 
> Signed-off-by: Thomas Zimmermann 
> Cc: Laurent Pinchart 
> Cc: Kieran Bingham 
> ---
>  drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c
> index 4c8fe83dd610..dd353fb858ef 100644
> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c
> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c
> @@ -11,6 +11,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -407,8 +408,8 @@ int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
>  			struct drm_mode_create_dumb *args)
>  {
>  	struct rcar_du_device *rcdu = to_rcar_du_device(dev);
> -	unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
>  	unsigned int align;
> +	int ret;
>  
>  	/*
>  	 * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
> @@ -419,7 +420,9 @@ int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
>  	else
>  		align = 16 * args->bpp / 8;
>  
> -	args->pitch = roundup(min_pitch, align);
> +	ret = drm_mode_size_dumb(dev, args, align, 0);
> +	if (ret)
> +		return ret;
>  
>  	return drm_gem_dma_dumb_create_internal(file, dev, args);
>  }

Reviewed-by: Tomi Valkeinen 

 Tomi



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Message-ID: <31c75a64-8b69-47ac-9e08-6010fa6cfb9c@gmail.com>
Date: Fri, 8 Aug 2025 15:46:39 +0200
MIME-Version: 1.0
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Subject: Re: [PATCH v3 11/20] xen/riscv: implement function to map memory in
 guest p2m
To: Jan Beulich , Andrew Cooper 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 
 
Content-Language: en-US
From: Oleksii Kurochko 
In-Reply-To: 

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On 8/5/25 5:20 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> Implement map_regions_p2mt() to map a region in the guest p2m with
>> a specific p2m type. The memory attributes will be derived from the
>> p2m type. This function is going to be called from dom0less common
>> code.
> s/is going to be/is/ ? Such a call exists already, after all.
>
>> --- a/xen/arch/riscv/include/asm/p2m.h
>> +++ b/xen/arch/riscv/include/asm/p2m.h
>> @@ -121,21 +121,22 @@ static inline int guest_physmap_mark_populate_on_demand(struct domain *d,
>>       return -EOPNOTSUPP;
>>   }
>>   
>> -static inline int guest_physmap_add_entry(struct domain *d,
>> -                                          gfn_t gfn, mfn_t mfn,
>> -                                          unsigned long page_order,
>> -                                          p2m_type_t t)
>> -{
>> -    BUG_ON("unimplemented");
>> -    return -EINVAL;
>> -}
>> +/*
>> + * Map a region in the guest p2m with a specific p2m type.
> What is "the guest p2m"? In your answer, please consider the possible
> (and at some point likely necessary) existence of altp2m and nestedp2m.
> In patch 04 you introduce p2m_get_hostp2m(), and I expect it's that
> what you mean here.

In the current one context it is host p2m. I can update the comment with:
"guest's hostp2m".

>
>> --- a/xen/arch/riscv/p2m.c
>> +++ b/xen/arch/riscv/p2m.c
>> @@ -9,6 +9,41 @@
>>   
>>   unsigned int __read_mostly p2m_root_order;
>>   
>> +/*
>> + * Force a synchronous P2M TLB flush.
>> + *
>> + * Must be called with the p2m lock held.
>> + */
>> +static void p2m_force_tlb_flush_sync(struct p2m_domain *p2m)
>> +{
>> +    struct domain *d = p2m->domain;
> Pointer-to-const please. Personally, given the implementation of this
> function (and also ...
>
>> +    ASSERT(p2m_is_write_locked(p2m));
>> +
>> +    sbi_remote_hfence_gvma(d->dirty_cpumask, 0, 0);
>> +
>> +    p2m->need_flush = false;
>> +}
>> +
>> +void p2m_tlb_flush_sync(struct p2m_domain *p2m)
>> +{
>> +    if ( p2m->need_flush )
>> +        p2m_force_tlb_flush_sync(p2m);
>> +}
> ... this one) I'd further ask for the function parameters to also be
> pointer-to-const, but Andrew may object to that. Andrew - it continues to
> be unclear to me under what conditions you agree with adding const, and
> under what conditions you would object to me asking for such. Please can
> you take the time to clarify this?
>
>> +/* Unlock the flush and do a P2M TLB flush if necessary */
>> +void p2m_write_unlock(struct p2m_domain *p2m)
>> +{
>> +    /*
>> +     * The final flush is done with the P2M write lock taken to avoid
>> +     * someone else modifying the P2M wbefore the TLB invalidation has
> Nit: Stray 'w'.
>
>> +     * completed.
>> +     */
>> +    p2m_tlb_flush_sync(p2m);
> Wasn't the plan to have this be conditional?

Not really, probably, I misunderstood you before.

Previously, I only had|p2m_force_tlb_flush_sync()| here, instead of
|p2m_tlb_flush_sync()|, and the latter includes a condition check on
|p2m->need_flush|.

>
>> @@ -139,3 +174,33 @@ int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted)
>>   
>>       return 0;
>>   }
>> +
>> +static int p2m_set_range(struct p2m_domain *p2m,
>> +                         gfn_t sgfn,
>> +                         unsigned long nr,
>> +                         mfn_t smfn,
>> +                         p2m_type_t t)
>> +{
>> +    return -EOPNOTSUPP;
>> +}
>> +
>> +static int p2m_insert_mapping(struct p2m_domain *p2m, gfn_t start_gfn,
>> +                              unsigned long nr, mfn_t mfn, p2m_type_t t)
>> +{
>> +    int rc;
>> +
>> +    p2m_write_lock(p2m);
>> +    rc = p2m_set_range(p2m, start_gfn, nr, mfn, t);
>> +    p2m_write_unlock(p2m);
>> +
>> +    return rc;
>> +}
>> +
>> +int map_regions_p2mt(struct domain *d,
>> +                     gfn_t gfn,
>> +                     unsigned long nr,
>> +                     mfn_t mfn,
>> +                     p2m_type_t p2mt)
>> +{
>> +    return p2m_insert_mapping(p2m_get_hostp2m(d), gfn, nr, mfn, p2mt);
>> +}
> And eventually both helper functions will gain further callers? Otherwise
> it's a little hard to see why they would both need to be separate functions.

Good point.
Actually, I think that it is enough to have map_regions_p2mt() as it is used
for dom0less common code, and re-use it every where potentially p2m_insert_mapping()
will be needed.

~ Oleksii

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    On 8/5/25 5:20 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    Implement map_regions_p2mt() to map a region in the guest p2m with
a specific p2m type. The memory attributes will be derived from the
p2m type. This function is going to be called from dom0less common
code.

    
      
    
      
    s/is going to be/is/ ? Such a call exists already, after all.


    
      
    
        
    --- a/xen/arch/riscv/include/asm/p2m.h
+++ b/xen/arch/riscv/include/asm/p2m.h
@@ -121,21 +121,22 @@ static inline int guest_physmap_mark_populate_on_demand(struct domain *d,
     return -EOPNOTSUPP;
 }
 
-static inline int guest_physmap_add_entry(struct domain *d,
-                                          gfn_t gfn, mfn_t mfn,
-                                          unsigned long page_order,
-                                          p2m_type_t t)
-{
-    BUG_ON("unimplemented");
-    return -EINVAL;
-}
+/*
+ * Map a region in the guest p2m with a specific p2m type.

    
      
    
      
    What is "the guest p2m"? In your answer, please consider the possible
(and at some point likely necessary) existence of altp2m and nestedp2m.
In patch 04 you introduce p2m_get_hostp2m(), and I expect it's that
what you mean here.
    
    
    
    
    In the current one context it is host p2m. I can update the comment with:
"guest's hostp2m".


    
    
    
      
    

    
      
    
        
    --- a/xen/arch/riscv/p2m.c
+++ b/xen/arch/riscv/p2m.c
@@ -9,6 +9,41 @@
 
 unsigned int __read_mostly p2m_root_order;
 
+/*
+ * Force a synchronous P2M TLB flush.
+ *
+ * Must be called with the p2m lock held.
+ */
+static void p2m_force_tlb_flush_sync(struct p2m_domain *p2m)
+{
+    struct domain *d = p2m->domain;

    
      
    
      
    Pointer-to-const please. Personally, given the implementation of this
function (and also ...


    
      
    
        
    +    ASSERT(p2m_is_write_locked(p2m));
+
+    sbi_remote_hfence_gvma(d->dirty_cpumask, 0, 0);
+
+    p2m->need_flush = false;
+}
+
+void p2m_tlb_flush_sync(struct p2m_domain *p2m)
+{
+    if ( p2m->need_flush )
+        p2m_force_tlb_flush_sync(p2m);
+}

    
      
    
      
    ... this one) I'd further ask for the function parameters to also be
pointer-to-const, but Andrew may object to that. Andrew - it continues to
be unclear to me under what conditions you agree with adding const, and
under what conditions you would object to me asking for such. Please can
you take the time to clarify this?


    
      
    
        
    +/* Unlock the flush and do a P2M TLB flush if necessary */
+void p2m_write_unlock(struct p2m_domain *p2m)
+{
+    /*
+     * The final flush is done with the P2M write lock taken to avoid
+     * someone else modifying the P2M wbefore the TLB invalidation has

    
      
    
      
    Nit: Stray 'w'.


    
      
    
        
    +     * completed.
+     */
+    p2m_tlb_flush_sync(p2m);

    
      
    
      
    Wasn't the plan to have this be conditional?
    
    
    
    
    Not really, probably, I misunderstood you before.

Previously, I only had p2m_force_tlb_flush_sync() here, instead of
p2m_tlb_flush_sync(), and the latter includes a condition check on
p2m->need_flush.


    
    
    
      
    

    
      
    
        
    @@ -139,3 +174,33 @@ int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted)
 
     return 0;
 }
+
+static int p2m_set_range(struct p2m_domain *p2m,
+                         gfn_t sgfn,
+                         unsigned long nr,
+                         mfn_t smfn,
+                         p2m_type_t t)
+{
+    return -EOPNOTSUPP;
+}
+
+static int p2m_insert_mapping(struct p2m_domain *p2m, gfn_t start_gfn,
+                              unsigned long nr, mfn_t mfn, p2m_type_t t)
+{
+    int rc;
+
+    p2m_write_lock(p2m);
+    rc = p2m_set_range(p2m, start_gfn, nr, mfn, t);
+    p2m_write_unlock(p2m);
+
+    return rc;
+}
+
+int map_regions_p2mt(struct domain *d,
+                     gfn_t gfn,
+                     unsigned long nr,
+                     mfn_t mfn,
+                     p2m_type_t p2mt)
+{
+    return p2m_insert_mapping(p2m_get_hostp2m(d), gfn, nr, mfn, p2mt);
+}

    
      
    
      
    And eventually both helper functions will gain further callers? Otherwise
it's a little hard to see why they would both need to be separate functions.
    
    
    
    
    Good point.
Actually, I think that it is enough to have map_regions_p2mt() as it is used
for dom0less common code, and re-use it every where potentially p2m_insert_mapping()
will be needed.

    
    
    ~ Oleksii

    
  


--------------UeLToCNY0qfZGDEeATW01CXA--


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From: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
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Cc: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: [PATCH v2 1/3] CI: Add driver domains tests
Date: Fri,  8 Aug 2025 16:32:41 +0200
Message-ID: <0243d946ec451ddf18a620dbcaaa45eba861810a.1754663560.git-series.marmarek@invisiblethingslab.com>
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Setup a simple two domU system. One with network backend, running
xendriverdomain service, and one with frontend, trying to ping the
backend.

Contrary to other similar tests, use disk image instead of initrd, to
allow bigger rootfs without adding more RAM (for both dom0 and domU).
But keep using pxelinux as a bootloader as it's easier to setup than
installing grub on the disk. Theoretically, it could be started via direct
kernel boot in QEMU, but pxelinux is slightly closer to real-world
deployment.

Signed-off-by: Marek Marczykowski-Górecki 
---
Changes in v2:
- use heredoc
- limit ping loop iterations
- use full "backend" / "frontend" in disk image names
- print domU consoles directly to /dev/console, to avoid systemd-added
  messages prefix
- terminate test on failure, don't wait for timeout
---
 automation/gitlab-ci/test.yaml                  |   8 +-
 automation/scripts/qemu-driverdomains-x86_64.sh | 130 +++++++++++++++++-
 2 files changed, 138 insertions(+)
 create mode 100755 automation/scripts/qemu-driverdomains-x86_64.sh

diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
index 1f0b27b2378a..5c4b2dc304b4 100644
--- a/automation/gitlab-ci/test.yaml
+++ b/automation/gitlab-ci/test.yaml
@@ -656,6 +656,14 @@ qemu-alpine-x86_64-gcc:
     - *x86-64-test-needs
     - alpine-3.18-gcc
 
+qemu-alpine-driverdomains-x86_64-gcc:
+  extends: .qemu-x86-64
+  script:
+    - ./automation/scripts/qemu-driverdomains-x86_64.sh 2>&1 | tee ${LOGFILE}
+  needs:
+    - *x86-64-test-needs
+    - alpine-3.18-gcc
+
 qemu-smoke-x86-64-gcc:
   extends: .qemu-smoke-x86-64
   script:
diff --git a/automation/scripts/qemu-driverdomains-x86_64.sh b/automation/scripts/qemu-driverdomains-x86_64.sh
new file mode 100755
index 000000000000..a8e2ceb33527
--- /dev/null
+++ b/automation/scripts/qemu-driverdomains-x86_64.sh
@@ -0,0 +1,130 @@
+#!/bin/bash
+
+set -ex -o pipefail
+
+dom0_rootfs_extra_comp=()
+dom0_rootfs_extra_uncomp=()
+
+cd binaries
+
+# DomU rootfs
+
+mkdir -p rootfs
+cd rootfs
+mkdir -p etc/local.d
+passed="ping test passed"
+failed="TEST FAILED"
+cat > etc/local.d/xen.start << EOF
+#!/bin/bash
+
+set -x
+
+if grep -q test=backend /proc/cmdline; then
+    brctl addbr xenbr0
+    ip link set xenbr0 up
+    ip addr add 192.168.0.1/24 dev xenbr0
+    bash /etc/init.d/xendriverdomain start
+    # log backend-related logs to the console
+    tail -F /var/log/xen/xldevd.log /var/log/xen/xen-hotplug.log >>/dev/console 2>/dev/null &
+else
+    ip link set eth0 up
+    ip addr add 192.168.0.2/24 dev eth0
+    timeout=6 # 6*10s
+    until ping -c 10 192.168.0.1; do
+        sleep 1
+        if [ \$timeout -le 0 ]; then
+            echo "${failed}"
+            exit 1
+        fi
+        ((timeout--))
+    done
+    echo "${passed}"
+fi
+EOF
+chmod +x etc/local.d/xen.start
+zcat ../rootfs.cpio.gz | cpio -imd
+zcat ../xen-tools.cpio.gz | cpio -imd
+mkfs.ext4 -d . ../domU-rootfs.img 1024M
+cd ..
+rm -rf rootfs
+
+# Dom0 rootfs
+mkdir -p rootfs
+cd rootfs
+zcat ../rootfs.cpio.gz | cpio -imd
+zcat ../xen-tools.cpio.gz | cpio -imd
+mkdir -p root etc/local.d
+cat > root/backend.cfg << EOF
+name="backend"
+memory=512
+vcpus=1
+kernel="/root/bzImage"
+extra="console=hvc0 root=/dev/xvda net.ifnames=0 test=backend"
+disk=[ '/root/domU-rootfs-backend.img,raw,xvda,rw' ]
+EOF
+cat > root/frontend.cfg << EOF
+name="frontend"
+memory=512
+vcpus=1
+kernel="/root/bzImage"
+extra="console=hvc0 root=/dev/xvda net.ifnames=0 test=frontend"
+disk=[ '/root/domU-rootfs-frontend.img,raw,xvda,rw' ]
+vif=[ 'bridge=xenbr0,backend=backend' ]
+EOF
+
+cat > etc/local.d/xen.start << EOF
+#!/bin/bash
+
+set -x
+
+bash /etc/init.d/xencommons start
+
+xl list
+
+tail -F /var/log/xen/console/guest-backend.log 2>/dev/null | sed -e "s/^/(backend) /" >>/dev/console &
+tail -F /var/log/xen/console/guest-frontend.log 2>/dev/null | sed -e "s/^/(frontend) /" >>/dev/console &
+xl -vvv create /root/backend.cfg
+xl -vvv create /root/frontend.cfg
+EOF
+chmod +x etc/local.d/xen.start
+
+cp ../domU-rootfs.img ./root/domU-rootfs-backend.img
+cp ../domU-rootfs.img ./root/domU-rootfs-frontend.img
+cp ../bzImage ./root/
+mkdir -p etc/default
+echo 'XENCONSOLED_TRACE=all' >> etc/default/xencommons
+mkdir -p var/log/xen/console
+mkfs.ext4 -d . ../dom0-rootfs.img 2048M
+cd ..
+rm -rf rootfs
+
+cd ..
+
+cat >> binaries/pxelinux.0 << EOF
+#!ipxe
+
+kernel xen console=com1 console_timestamps=boot
+module bzImage console=hvc0 root=/dev/sda net.ifnames=0
+boot
+EOF
+
+# Run the test
+rm -f smoke.serial
+export TEST_CMD="qemu-system-x86_64 \
+    -cpu qemu64,+svm \
+    -m 2G -smp 2 \
+    -monitor none -serial stdio \
+    -nographic \
+    -device virtio-net-pci,netdev=n0 \
+    -netdev user,id=n0,tftp=binaries,bootfile=/pxelinux.0 \
+    -drive file=binaries/dom0-rootfs.img,format=raw"
+
+export TEST_LOG="smoke.serial"
+export BOOT_MSG="Latest ChangeSet: "
+export LOG_MSG="Domain-0"
+# exit early on test failure too, check if it was success below
+export PASSED="$passed|$failed"
+
+./automation/scripts/console.exp | sed 's/\r\+$//'
+
+grep "$passed" smoke.serial
-- 
git-series 0.9.1


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Cc: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
Subject: [PATCH v2 0/3] Add driver domains test
Date: Fri,  8 Aug 2025 16:32:40 +0200
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This is intended to detect issues like recent xl devd crash in domU.

Pipeline:
https://gitlab.com/xen-project/people/marmarek/xen/-/pipelines/1974548454

I did checked that indeed it fails with the fix reverted - that's why the
second patch - Alpine version did not detected that regression.

Requires debian in test-artifacts repo - patch sent separately.

Marek Marczykowski-Górecki (3):
  CI: Add driver domains tests
  CI: Add configure --enable-systemd for full build
  CI: Run driver domains test on Debian too

 automation/build/debian/12-x86_64.dockerfile    |   1 +-
 automation/gitlab-ci/test.yaml                  |  27 +++-
 automation/scripts/build                        |   3 +-
 automation/scripts/qemu-driverdomains-x86_64.sh | 144 +++++++++++++++++-
 4 files changed, 175 insertions(+)
 create mode 100755 automation/scripts/qemu-driverdomains-x86_64.sh

base-commit: dbcbbed4e9dc25faa211d359c2f04a9c70f087c9
-- 
git-series 0.9.1


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From: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
To: xen-devel@lists.xenproject.org
Cc: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: [PATCH v2 3/3] CI: Run driver domains test on Debian too
Date: Fri,  8 Aug 2025 16:32:43 +0200
Message-ID: <3f4e22c2424e8b534fe743aad1e1ee4934f9444c.1754663560.git-series.marmarek@invisiblethingslab.com>
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The recent failure affected only glibc-based systems, so do the test on
Debian too.

Signed-off-by: Marek Marczykowski-Górecki 
---
Changes in v2:
- use systemd in Debian

I once got the following timeout:

    (backend) ==> /var/log/xen/xldevd.log <==
    (backend) libxl: error: libxl_aoutils.c:539:async_exec_timeout: killing execution of /etc/xen/scripts/vif-bridge online because of timeout

https://gitlab.com/xen-project/people/marmarek/xen/-/jobs/10961394681
(docker-bobcat runner)

Could be related to having systemd in domU (and being on QEMU TCG, not
even KVM). I never hit this case on Alpine nor Debian with OpenRC. If
that will repeat, may need some adjustments - more CPUs in QEMU? limit
to more powerful runners? setup KVM on the runners?
---
 automation/gitlab-ci/test.yaml                  | 19 ++++++++++++++++++-
 automation/scripts/qemu-driverdomains-x86_64.sh | 18 +++++++++++++++--
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
index 5c4b2dc304b4..a5ae03b0eee9 100644
--- a/automation/gitlab-ci/test.yaml
+++ b/automation/gitlab-ci/test.yaml
@@ -30,6 +30,17 @@
     job: microcode-x86
     ref: master
 
+.debian-x86-64-test-needs: &debian-x86-64-test-needs
+  - project: xen-project/hardware/test-artifacts
+    job: linux-6.6.56-x86_64
+    ref: master
+  - project: xen-project/hardware/test-artifacts
+    job: debian-12-x86_64-rootfs
+    ref: master
+  - project: xen-project/hardware/test-artifacts
+    job: microcode-x86
+    ref: master
+
 .qemu-arm64:
   extends: .test-jobs-common
   variables:
@@ -664,6 +675,14 @@ qemu-alpine-driverdomains-x86_64-gcc:
     - *x86-64-test-needs
     - alpine-3.18-gcc
 
+qemu-debian-12-driverdomains-x86_64-gcc:
+  extends: .qemu-x86-64
+  script:
+    - ./automation/scripts/qemu-driverdomains-x86_64.sh 2>&1 | tee ${LOGFILE}
+  needs:
+    - *debian-x86-64-test-needs
+    - debian-12-x86_64-gcc-debug
+
 qemu-smoke-x86-64-gcc:
   extends: .qemu-smoke-x86-64
   script:
diff --git a/automation/scripts/qemu-driverdomains-x86_64.sh b/automation/scripts/qemu-driverdomains-x86_64.sh
index a8e2ceb33527..e5765ba5dbd6 100755
--- a/automation/scripts/qemu-driverdomains-x86_64.sh
+++ b/automation/scripts/qemu-driverdomains-x86_64.sh
@@ -23,7 +23,11 @@ if grep -q test=backend /proc/cmdline; then
     brctl addbr xenbr0
     ip link set xenbr0 up
     ip addr add 192.168.0.1/24 dev xenbr0
-    bash /etc/init.d/xendriverdomain start
+    if [ -d /run/systemd ]; then
+        systemctl start xendriverdomain
+    else
+        bash /etc/init.d/xendriverdomain start
+    fi
     # log backend-related logs to the console
     tail -F /var/log/xen/xldevd.log /var/log/xen/xen-hotplug.log >>/dev/console 2>/dev/null &
 else
@@ -77,7 +81,11 @@ cat > etc/local.d/xen.start << EOF
 
 set -x
 
-bash /etc/init.d/xencommons start
+if [ -d /run/systemd ]; then
+    systemctl start xen-init-dom0.service
+else
+    bash /etc/init.d/xencommons start
+fi
 
 xl list
 
@@ -94,6 +102,12 @@ cp ../bzImage ./root/
 mkdir -p etc/default
 echo 'XENCONSOLED_TRACE=all' >> etc/default/xencommons
 mkdir -p var/log/xen/console
+if [ -e etc/systemd/system.conf ]; then
+    chroot . systemctl enable proc-xen.mount \
+        xenstored.service \
+        xenconsoled.service \
+        xen-init-dom0.service
+fi
 mkfs.ext4 -d . ../dom0-rootfs.img 2048M
 cd ..
 rm -rf rootfs
-- 
git-series 0.9.1


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From: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
To: xen-devel@lists.xenproject.org
Cc: =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: [PATCH v2 2/3] CI: Add configure --enable-systemd for full build
Date: Fri,  8 Aug 2025 16:32:42 +0200
Message-ID: <526d26a85bd1f164dd8a421dfcc1e765c3ff5590.1754663560.git-series.marmarek@invisiblethingslab.com>
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This doesn't exclude sysvinit scripts, but allows testing systemd too.

Signed-off-by: Marek Marczykowski-Górecki 
--
New in v2.

Requires containers rebuild
---
 automation/build/debian/12-x86_64.dockerfile | 1 +
 automation/scripts/build                     | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/automation/build/debian/12-x86_64.dockerfile b/automation/build/debian/12-x86_64.dockerfile
index e26a19079e38..3a53d92ddf6d 100644
--- a/automation/build/debian/12-x86_64.dockerfile
+++ b/automation/build/debian/12-x86_64.dockerfile
@@ -24,6 +24,7 @@ RUN <
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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Juergen Gross 
Subject: [XEN PATCH 05/11] libxl: Convert libxl__json_parse() to use json-c
Date: Fri,  8 Aug 2025 16:55:56 +0200
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From: Anthony PERARD 

This reuse the "json_callback_*" implemented for the yajl parser as
they don't really need to be changed. It's just awkward to have to
cast between `unsigned char` and `char.`

Replace few strncpy() by memcpy() to let the compiler know we want to
copy the string without the terminating nul, as we are adding it just
after.

Also, it should be possible to keep using YAJL parser when json-c
library isn't available.

Signed-off-by: Anthony PERARD 
---
 tools/include/libxl_json.h    |   4 ++
 tools/libs/light/libxl_json.c | 120 ++++++++++++++++++++++++++++++++--
 2 files changed, 120 insertions(+), 4 deletions(-)

diff --git a/tools/include/libxl_json.h b/tools/include/libxl_json.h
index 3f97267eae..f0b4871e0e 100644
--- a/tools/include/libxl_json.h
+++ b/tools/include/libxl_json.h
@@ -42,6 +42,7 @@ yajl_gen_status libxl_ms_vm_genid_gen_json(yajl_gen hand, libxl_ms_vm_genid *p);
 #  define HAVE_YAJL_V2 1
 #endif
 
+#ifdef HAVE_LIBYAJL
 #ifdef HAVE_YAJL_V2
 
 typedef size_t libxl_yajl_length;
@@ -89,5 +90,8 @@ static inline yajl_gen libxl_yajl_gen_alloc(const yajl_alloc_funcs *allocFuncs)
 }
 
 #endif /* !HAVE_YAJL_V2 */
+#else
+typedef size_t libxl_yajl_length;
+#endif /* !HAVE_LIBYAJL */
 
 #endif /* LIBXL_JSON_H */
diff --git a/tools/libs/light/libxl_json.c b/tools/libs/light/libxl_json.c
index 9b8ef2cab9..44ee6e213f 100644
--- a/tools/libs/light/libxl_json.c
+++ b/tools/libs/light/libxl_json.c
@@ -16,7 +16,25 @@
 
 #include 
 
+#ifdef HAVE_LIBJSONC
+#include 
+#define USE_LIBJSONC_PARSER
+#endif
+
+#ifdef HAVE_LIBYAJL
+#  ifndef USE_LIBJSONC_PARSER
+#    define USE_LIBYAJL_PARSER
+#  endif
+#endif
+
+
+#ifdef USE_LIBJSONC_PARSER
+#include 
+#endif
+
+#ifdef USE_LIBYAJL_PARSER
 #include 
+#endif
 #include 
 
 #include "libxl_internal.h"
@@ -25,7 +43,9 @@
 
 typedef struct libxl__yajl_ctx {
     libxl__gc *gc;
+#ifdef USE_LIBYAJL_PARSER
     yajl_handle hand;
+#endif
     libxl__json_object *head;
     libxl__json_object *current;
 #ifdef DEBUG_ANSWER
@@ -33,7 +53,7 @@ typedef struct libxl__yajl_ctx {
 #endif
 } libxl__yajl_ctx;
 
-#ifdef DEBUG_ANSWER
+#if defined(DEBUG_ANSWER) && defined(USE_LIBYAJL_PARSER)
 #if YAJL_VERSION < 20000
 #  define DEBUG_GEN_ALLOC(ctx)                  \
     if ((ctx)->g == NULL) {                     \
@@ -759,7 +779,7 @@ static int json_callback_number(void *opaque, const char *s, libxl_yajl_length l
     obj = libxl__json_object_alloc(ctx->gc, JSON_NUMBER);
 
     t = libxl__zalloc(ctx->gc, len + 1);
-    strncpy(t, s, len);
+    memcpy(t, s, len);
     t[len] = 0;
 
     obj->u.string = t;
@@ -806,7 +826,7 @@ static int json_callback_map_key(void *opaque, const unsigned char *str,
 
     DEBUG_GEN_STRING(ctx, str, len);
 
-    strncpy(t, (const char *) str, len);
+    memcpy(t, (const char *) str, len);
     t[len] = 0;
 
     if (libxl__json_object_is_map(obj)) {
@@ -890,6 +910,7 @@ static int json_callback_end_array(void *opaque)
     return 1;
 }
 
+#ifdef USE_LIBYAJL_PARSER
 static yajl_callbacks callbacks = {
     json_callback_null,
     json_callback_boolean,
@@ -903,28 +924,111 @@ static yajl_callbacks callbacks = {
     json_callback_start_array,
     json_callback_end_array
 };
+#endif
 
 static void yajl_ctx_free(libxl__yajl_ctx *yajl_ctx)
 {
+#ifdef USE_LIBYAJL_PARSER
     if (yajl_ctx->hand) {
         yajl_free(yajl_ctx->hand);
         yajl_ctx->hand = NULL;
     }
+#endif
     DEBUG_GEN_FREE(yajl_ctx);
 }
 
+#ifdef USE_LIBJSONC_PARSER
+static int jso_visiter(json_object *jso,
+                       int flags,
+                       json_object *parent_jso,
+                       const char *jso_key,
+                       size_t *jso_index,
+                       void *userarg)
+{
+    enum json_type type;
+    int r;
+
+    if (jso_key && flags != JSON_C_VISIT_SECOND) {
+        json_callback_map_key(userarg, (const unsigned char*)jso_key, strlen(jso_key));
+    }
+    type = json_object_get_type(jso);
+    switch (type) {
+    case json_type_null:
+        r = json_callback_null(userarg);
+        break;
+    case json_type_boolean:
+        r = json_callback_boolean(userarg, json_object_get_boolean(jso));
+        break;
+    case json_type_int:
+    case json_type_double: {
+        // it might be better to use on of
+        // json_object_get_{int,int64,uint64,double} instead.
+        // but would need to replace json_callback_number().
+        const char *s = json_object_get_string(jso);
+        r = json_callback_number(userarg, s, strlen(s));
+        break;
+    }
+    case json_type_object:
+        if (flags != JSON_C_VISIT_SECOND) {
+            r = json_callback_start_map(userarg);
+        } else {
+            r = json_callback_end_map(userarg);
+        }
+        break;
+    case json_type_array:
+        if (flags != JSON_C_VISIT_SECOND) {
+            r = json_callback_start_array(userarg);
+        } else {
+            r = json_callback_end_array(userarg);
+        }
+        break;
+    case json_type_string: {
+        const char *s = json_object_get_string(jso);
+        const int len = json_object_get_string_len(jso);
+        r = json_callback_string(userarg, (const unsigned char*)s, len);
+        break;
+    }
+    default:
+        /* error */
+        r = 0;
+    }
+    if (r == 0)
+        return JSON_C_VISIT_RETURN_ERROR;
+    return JSON_C_VISIT_RETURN_CONTINUE;
+}
+#endif
+
 libxl__json_object *libxl__json_parse(libxl__gc *gc, const char *s)
 {
+#ifdef USE_LIBYAJL_PARSER
     yajl_status status;
+    unsigned char *str = NULL;
+#endif
     libxl__yajl_ctx yajl_ctx;
     libxl__json_object *o = NULL;
-    unsigned char *str = NULL;
+#ifdef USE_LIBJSONC_PARSER
+    json_object *jso;
+    enum json_tokener_error error;
+
+    jso = json_tokener_parse_verbose(s, &error);
+    if (!jso) {
+        LOG(ERROR, "json-c parse error: %s", json_tokener_error_desc(error));
+        goto out;
+    }
+#endif
 
     memset(&yajl_ctx, 0, sizeof (yajl_ctx));
     yajl_ctx.gc = gc;
 
     DEBUG_GEN_ALLOC(&yajl_ctx);
 
+#ifdef USE_LIBJSONC_PARSER
+    int r = json_c_visit(jso, 0, jso_visiter, &yajl_ctx);
+    if (r < 0) {
+        LOG(ERROR, "json_c_visit failed");
+        goto out;
+    }
+#elif defined(USE_LIBYAJL_PARSER)
     if (yajl_ctx.hand == NULL) {
         yajl_ctx.hand = libxl__yajl_alloc(&callbacks, NULL, &yajl_ctx);
     }
@@ -935,6 +1039,7 @@ libxl__json_object *libxl__json_parse(libxl__gc *gc, const char *s)
     status = yajl_complete_parse(yajl_ctx.hand);
     if (status != yajl_status_ok)
         goto out;
+#endif
 
     o = yajl_ctx.head;
 
@@ -943,13 +1048,20 @@ libxl__json_object *libxl__json_parse(libxl__gc *gc, const char *s)
     yajl_ctx.head = NULL;
 
     yajl_ctx_free(&yajl_ctx);
+#ifdef USE_LIBJSONC_PARSER
+    json_object_put(jso);
+#endif
     return o;
 
 out:
+#ifdef USE_LIBJSONC_PARSER
+    json_object_put(jso);
+#elif defined(USE_LIBYAJL_PARSER)
     str = yajl_get_error(yajl_ctx.hand, 1, (const unsigned char*)s, strlen(s));
 
     LIBXL__LOG(libxl__gc_owner(gc), LIBXL__LOG_ERROR, "yajl error: %s", str);
     yajl_free_error(yajl_ctx.hand, str);
+#endif
     yajl_ctx_free(&yajl_ctx);
     return NULL;
 }
-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD 
Subject: [XEN PATCH 01/11] xl: move printf_info prototype to an header
Date: Fri,  8 Aug 2025 16:55:52 +0200
Message-Id: <20250808145602.41716-2-anthony@xenproject.org>
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From: Anthony PERARD 

In a single place.

Signed-off-by: Anthony PERARD 
---
 tools/xl/xl.h      | 3 +++
 tools/xl/xl_info.c | 3 ---
 tools/xl/xl_misc.c | 3 ---
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index 45745f0dbb..9000df00de 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -310,6 +310,9 @@ extern void printf_info_sexp(int domid, libxl_domain_config *d_config, FILE *fh)
 extern void apply_global_affinity_masks(libxl_domain_type type,
                                         libxl_bitmap *vcpu_affinity_array,
                                         unsigned int size);
+void printf_info(enum output_format output_format,
+                 int domid,
+                 libxl_domain_config *d_config, FILE *fh);
 
 #define XL_GLOBAL_CONFIG XEN_CONFIG_DIR "/xl.conf"
 #define XL_LOCK_FILE XEN_LOCK_DIR "/xl"
diff --git a/tools/xl/xl_info.c b/tools/xl/xl_info.c
index eb019e3ee9..3fbc0698b7 100644
--- a/tools/xl/xl_info.c
+++ b/tools/xl/xl_info.c
@@ -96,9 +96,6 @@ static yajl_gen_status printf_info_one_json(yajl_gen hand, int domid,
     return s;
 }
 
-void printf_info(enum output_format output_format,
-                 int domid,
-                 libxl_domain_config *d_config, FILE *fh);
 void printf_info(enum output_format output_format,
                  int domid,
                  libxl_domain_config *d_config, FILE *fh)
diff --git a/tools/xl/xl_misc.c b/tools/xl/xl_misc.c
index 08f0fb6dc9..f0167e1603 100644
--- a/tools/xl/xl_misc.c
+++ b/tools/xl/xl_misc.c
@@ -256,9 +256,6 @@ int main_dump_core(int argc, char **argv)
     return EXIT_SUCCESS;
 }
 
-extern void printf_info(enum output_format output_format,
-                        int domid,
-                        libxl_domain_config *d_config, FILE *fh);
 int main_config_update(int argc, char **argv)
 {
     uint32_t domid;
-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Juergen Gross ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Andrew Cooper ,
	Jan Beulich ,
	Community Manager ,
	Stefano Stabellini ,
	Julien Grall ,
	Michal Orzel ,
	Oleksii Kurochko 
Subject: [XEN PATCH 00/11] Allow to build libxl and other tools with json-c instead of yajl
Date: Fri,  8 Aug 2025 16:55:51 +0200
Message-Id: <20250808145602.41716-1-anthony@xenproject.org>
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From: Anthony PERARD 

Patch series available in this git branch:
https://xenbits.xenproject.org/git-http/people/aperard/xen-unstable.git br.libxl-libjsonc-v1

Hi,

The library YAJL has been unmaintained for several years, without an obvious
fork to pick.

On the other and the library json-c is been maintained and use by several other
project, it's probably already installed on your machine. So this patch series
intend to allow to build the Xen toolstack again json-c, and forgo yajl.

Just in case, YAJL is can still be used.

There's bit of libxl API that exposes YAJL, mainly so it can be used by `xl` to
call libxl_domain_config_gen_json(). It was exposed via the "libxl_json.h"
headers. This functions and others won't be available when libxl is build
against json-c.

Cheers,

Anthony PERARD (11):
  xl: move printf_info prototype to an header
  libxl: Remove duplicate libxl_domain_config_gen_json prototype
  libxl: remove duplicated libxl__yajl_gen_asciiz() prototype
  tools/configure: Introduce deps on json-c lib for libxl
  libxl: Convert libxl__json_parse() to use json-c
  libxl: convert libxl__json_object_to_yajl_gen to
    libxl__json_object_to_libjsonc_object
  libxl: libxl__object_to_json() to json-c
  libxl: convert libxl__json_object_to_json() to json_object
  tools/libxenstat: Use json-c when available
  configure: Use json-c by default, fallback to yajl
  Update CHANGELOG and README with dependency on json-c

 CHANGELOG.md                              |   2 +
 README                                    |   2 +-
 config/Tools.mk.in                        |   2 +
 tools/config.h.in                         |   3 +
 tools/configure                           | 136 +++++-
 tools/configure.ac                        |  10 +-
 tools/include/libxl_json.h                |  30 +-
 tools/libs/light/Makefile                 |   7 +-
 tools/libs/light/gentypes.py              | 160 ++++++-
 tools/libs/light/idl.py                   |   7 +-
 tools/libs/light/libxl_cpuid.c            | 119 +++++
 tools/libs/light/libxl_internal.h         |  25 +-
 tools/libs/light/libxl_json.c             | 557 +++++++++++++++++++++-
 tools/libs/light/libxl_qmp.c              |  53 ++
 tools/libs/light/libxl_types.idl          |   7 +-
 tools/libs/light/libxl_types_internal.idl |   3 +-
 tools/libs/stat/Makefile                  |   3 +-
 tools/libs/stat/xenstat_qmp.c             | 126 ++++-
 tools/xl/Makefile                         |   2 +-
 tools/xl/xl.h                             |   3 +
 tools/xl/xl_info.c                        | 105 +++-
 tools/xl/xl_misc.c                        |   3 -
 22 files changed, 1313 insertions(+), 52 deletions(-)

-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Juergen Gross 
Subject: [XEN PATCH 06/11] libxl: convert libxl__json_object_to_yajl_gen to libxl__json_object_to_libjsonc_object
Date: Fri,  8 Aug 2025 16:55:57 +0200
Message-Id: <20250808145602.41716-7-anthony@xenproject.org>
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From: Anthony PERARD 

Convert yajl_gen to json_object from lib json-c.

And make use of it in qmp_prepare_cmd(), which can be compiled with
either lib.

Signed-off-by: Anthony PERARD 
---
 tools/include/libxl_json.h        |  6 ++
 tools/libs/light/libxl_internal.h |  7 +++
 tools/libs/light/libxl_json.c     | 95 +++++++++++++++++++++++++++++++
 tools/libs/light/libxl_qmp.c      | 53 +++++++++++++++++
 4 files changed, 161 insertions(+)

diff --git a/tools/include/libxl_json.h b/tools/include/libxl_json.h
index f0b4871e0e..e2ef8151f0 100644
--- a/tools/include/libxl_json.h
+++ b/tools/include/libxl_json.h
@@ -15,12 +15,18 @@
 #ifndef LIBXL_JSON_H
 #define LIBXL_JSON_H
 
+#ifdef HAVE_LIBJSONC
+#include 
+#endif
+
+#ifdef HAVE_LIBYAJL
 #include 
 #include 
 
 #ifdef HAVE_YAJL_YAJL_VERSION_H
 #  include 
 #endif
+#endif
 
 yajl_gen_status libxl__uint64_gen_json(yajl_gen hand, uint64_t val);
 yajl_gen_status libxl_defbool_gen_json(yajl_gen hand, libxl_defbool *p);
diff --git a/tools/libs/light/libxl_internal.h b/tools/libs/light/libxl_internal.h
index 4b6587a27a..b66aaa779d 100644
--- a/tools/libs/light/libxl_internal.h
+++ b/tools/libs/light/libxl_internal.h
@@ -2234,9 +2234,16 @@ _hidden const libxl__json_object *libxl__json_map_get(const char *key,
  */
 _hidden libxl__json_object *libxl__json_object_alloc(libxl__gc *gc_opt,
                                                      libxl__json_node_type type);
+#ifdef HAVE_LIBJSONC
+_hidden int libxl__json_object_to_json_object(libxl__gc *gc,
+                                              json_object **jso_out,
+                                              const libxl__json_object *obj);
+#endif
+#ifdef HAVE_LIBYAJL
 _hidden yajl_status libxl__json_object_to_yajl_gen(libxl__gc *gc_opt,
                                                    yajl_gen hand,
                                                    const libxl__json_object *param);
+#endif
 _hidden void libxl__json_object_free(libxl__gc *gc_opt,
                                      libxl__json_object *obj);
 
diff --git a/tools/libs/light/libxl_json.c b/tools/libs/light/libxl_json.c
index 44ee6e213f..b26ac901d6 100644
--- a/tools/libs/light/libxl_json.c
+++ b/tools/libs/light/libxl_json.c
@@ -631,6 +631,100 @@ const libxl__json_object *libxl__json_map_get(const char *key,
     return NULL;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl__json_object_to_json_object(libxl__gc *gc,
+                                      json_object **jso_out,
+                                      const libxl__json_object *obj)
+{
+    int idx = 0;
+    int rc, r;
+
+    switch (obj->type) {
+    case JSON_NULL:
+        *jso_out = json_object_new_null();
+        return 0;
+    case JSON_BOOL:
+        *jso_out = json_object_new_boolean(obj->u.b);
+        if (!*jso_out)
+            return ERROR_NOMEM;
+        return 0;
+    case JSON_INTEGER:
+        *jso_out = json_object_new_int64(obj->u.i);
+        if (!*jso_out)
+            return ERROR_NOMEM;
+        return 0;
+    case JSON_DOUBLE:
+        *jso_out = json_object_new_double(obj->u.d);
+        if (!*jso_out)
+            return ERROR_NOMEM;
+        return 0;
+    case JSON_NUMBER:
+        *jso_out = json_object_new_string(obj->u.string);
+        if (!*jso_out)
+            return ERROR_NOMEM;
+        return 0;
+    case JSON_STRING:
+        *jso_out = json_object_new_string(obj->u.string);
+        if (!*jso_out)
+            return ERROR_NOMEM;
+        return 0;
+    case JSON_MAP: {
+        libxl__json_map_node *node = NULL;
+        json_object *map_root = json_object_new_object();
+        json_object *node_value;
+
+        for (idx = 0; idx < obj->u.map->count; idx++) {
+            if (flexarray_get(obj->u.map, idx, (void**)&node) != 0)
+                break;
+
+            rc = libxl__json_object_to_json_object(gc, &node_value, node->obj);
+            if (rc) {
+                json_object_put(map_root);
+                return rc;
+            }
+
+            r = json_object_object_add(map_root, node->map_key, node_value);
+            if (r < 0) {
+                json_object_put(node_value);
+                json_object_put(map_root);
+                return ERROR_FAIL;
+            }
+        }
+        *jso_out = map_root;
+        return 0;
+    }
+    case JSON_ARRAY: {
+        libxl__json_object *node = NULL;
+        json_object *array_root = json_object_new_array_ext(obj->u.array->count);
+        json_object *node_value;
+
+        for (idx = 0; idx < obj->u.array->count; idx++) {
+            if (flexarray_get(obj->u.array, idx, (void**)&node) != 0)
+                break;
+
+            rc = libxl__json_object_to_json_object(gc, &node_value, node);
+            if (rc) {
+                json_object_put(array_root);
+                return rc;
+            }
+            r = json_object_array_add(array_root, node_value);
+            if (r < 0) {
+                json_object_put(node_value);
+                json_object_put(array_root);
+                return ERROR_FAIL;
+            }
+        }
+        *jso_out = array_root;
+        return 0;
+    }
+    case JSON_ANY:
+    default:
+        /* JSON_ANY is not a valid value for obj->type. */
+        return ERROR_FAIL;
+    }
+}
+#endif
+#ifdef HAVE_LIBYAJL
 yajl_status libxl__json_object_to_yajl_gen(libxl__gc *gc,
                                            yajl_gen hand,
                                            const libxl__json_object *obj)
@@ -698,6 +792,7 @@ yajl_status libxl__json_object_to_yajl_gen(libxl__gc *gc,
     abort();
 #undef CONVERT_YAJL_GEN_TO_STATUS
 }
+#endif
 
 
 /*
diff --git a/tools/libs/light/libxl_qmp.c b/tools/libs/light/libxl_qmp.c
index 84740bd4b3..94b6fdb559 100644
--- a/tools/libs/light/libxl_qmp.c
+++ b/tools/libs/light/libxl_qmp.c
@@ -61,7 +61,11 @@
 
 #include 
 
+#ifdef HAVE_LIBJSONC
+#include 
+#elif defined(HAVE_LIBYAJL)
 #include 
+#endif
 
 #include "xen_list.h"
 #include "libxl_internal.h"
@@ -481,13 +485,56 @@ static char *qmp_prepare_cmd(libxl__gc *gc, const char *cmd,
                              const libxl__json_object *args,
                              int id)
 {
+#ifdef HAVE_LIBJSONC
+    json_object *jso = NULL;
+    json_object *jso_value = NULL;
+    /* memory for 'buf' is owned by 'jso' */
+    const char *buf;
+    int rc, r;
+#elif defined(HAVE_LIBYAJL)
     yajl_gen hand = NULL;
     /* memory for 'buf' is owned by 'hand' */
     const unsigned char *buf;
     libxl_yajl_length len;
     yajl_gen_status s;
+#else
+#  error Missing JSON library
+#endif
     char *ret = NULL;
 
+#ifdef HAVE_LIBJSONC
+    jso = json_object_new_object();
+    if (!jso)
+        goto out;
+
+    jso_value = json_object_new_string(cmd);
+    if (!jso_value)
+        goto out;
+    r = json_object_object_add(jso, "execute", jso_value);
+    if (r < 0)
+        goto out;
+    jso_value = json_object_new_int(id);
+    if (!jso_value)
+        goto out;
+    r = json_object_object_add(jso, "id", jso_value);
+    if (r < 0)
+        goto out;
+    /* `jso_value` now part of `jso`, shouldn't free it anymore */
+    jso_value = NULL;
+    if (args) {
+        rc = libxl__json_object_to_json_object(gc, &jso_value, args);
+        if (rc)
+            goto out;
+        r = json_object_object_add(jso, "arguments", jso_value);
+        if (r < 0)
+            goto out;
+        jso_value = NULL;
+    }
+
+    buf = json_object_to_json_string_ext(jso, JSON_C_TO_STRING_PLAIN);
+    ret = libxl__sprintf(gc, "%s\r\n", buf);
+
+#elif defined(HAVE_LIBYAJL)
     hand = libxl_yajl_gen_alloc(NULL);
 
     if (!hand) {
@@ -516,9 +563,15 @@ static char *qmp_prepare_cmd(libxl__gc *gc, const char *cmd,
         goto out;
 
     ret = libxl__sprintf(gc, "%*.*s\r\n", (int)len, (int)len, buf);
+#endif
 
 out:
+#ifdef HAVE_LIBJSONC
+    json_object_put(jso_value);
+    json_object_put(jso);
+#elif defined(HAVE_LIBYAJL)
     yajl_gen_free(hand);
+#endif
     return ret;
 }
 
-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Juergen Gross 
Subject: [XEN PATCH 04/11] tools/configure: Introduce deps on json-c lib for libxl
Date: Fri,  8 Aug 2025 16:55:55 +0200
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From: Anthony PERARD 

To replace yajl.

Introduce YAJL_LIBS variable, to be able to remove "-lyajl" later.

Signed-off-by: Anthony PERARD 
---
 config/Tools.mk.in        |   2 +
 tools/config.h.in         |   3 ++
 tools/configure           | 107 +++++++++++++++++++++++++++++++++++++-
 tools/configure.ac        |   6 ++-
 tools/libs/light/Makefile |   5 +-
 tools/xl/Makefile         |   2 +-
 6 files changed, 119 insertions(+), 6 deletions(-)

diff --git a/config/Tools.mk.in b/config/Tools.mk.in
index e47ac23d11..c2201021d1 100644
--- a/config/Tools.mk.in
+++ b/config/Tools.mk.in
@@ -65,6 +65,8 @@ EXTFS_LIBS          := @EXTFS_LIBS@
 CURSES_LIBS         := @CURSES_LIBS@
 TINFO_LIBS          := @TINFO_LIBS@
 ARGP_LDFLAGS        := @argp_ldflags@
+LIBJSONC_LIBS       := @libjsonc_LIBS@
+YAJL_LIBS           := @YAJL_LIBS@
 
 FILE_OFFSET_BITS    := @FILE_OFFSET_BITS@
 
diff --git a/tools/config.h.in b/tools/config.h.in
index fe2a94cfc4..ed0042018d 100644
--- a/tools/config.h.in
+++ b/tools/config.h.in
@@ -27,6 +27,9 @@
 /* Define to 1 if you have the `fdt' library (-lfdt). */
 #undef HAVE_LIBFDT
 
+/* Use library json-c */
+#undef HAVE_LIBJSONC
+
 /* Define to 1 if you have the `lzma' library (-llzma). */
 #undef HAVE_LIBLZMA
 
diff --git a/tools/configure b/tools/configure
index 5abd44e21e..edd1701b2d 100755
--- a/tools/configure
+++ b/tools/configure
@@ -660,6 +660,9 @@ libnl
 LIBNL3_LIBS
 LIBNL3_CFLAGS
 argp_ldflags
+YAJL_LIBS
+libjsonc_LIBS
+libjsonc_CFLAGS
 PTHREAD_LIBS
 PTHREAD_LDFLAGS
 PTHREAD_CFLAGS
@@ -882,6 +885,8 @@ pixman_CFLAGS
 pixman_LIBS
 libzstd_CFLAGS
 libzstd_LIBS
+libjsonc_CFLAGS
+libjsonc_LIBS
 LIBNL3_CFLAGS
 LIBNL3_LIBS
 SYSTEMD_SLEEP_DIR'
@@ -1633,6 +1638,10 @@ Some influential environment variables:
               C compiler flags for libzstd, overriding pkg-config
   libzstd_LIBS
               linker flags for libzstd, overriding pkg-config
+  libjsonc_CFLAGS
+              C compiler flags for libjsonc, overriding pkg-config
+  libjsonc_LIBS
+              linker flags for libjsonc, overriding pkg-config
   LIBNL3_CFLAGS
               C compiler flags for LIBNL3, overriding pkg-config
   LIBNL3_LIBS linker flags for LIBNL3, overriding pkg-config
@@ -9624,6 +9633,99 @@ printf "%s\n" "$ax_cv_pthread_flags" >&6; }
 
 
 
+
+pkg_failed=no
+{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for libjsonc" >&5
+printf %s "checking for libjsonc... " >&6; }
+
+if test -n "$libjsonc_CFLAGS"; then
+    pkg_cv_libjsonc_CFLAGS="$libjsonc_CFLAGS"
+ elif test -n "$PKG_CONFIG"; then
+    if test -n "$PKG_CONFIG" && \
+    { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"json-c\""; } >&5
+  ($PKG_CONFIG --exists --print-errors "json-c") 2>&5
+  ac_status=$?
+  printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; then
+  pkg_cv_libjsonc_CFLAGS=`$PKG_CONFIG --cflags "json-c" 2>/dev/null`
+		      test "x$?" != "x0" && pkg_failed=yes
+else
+  pkg_failed=yes
+fi
+ else
+    pkg_failed=untried
+fi
+if test -n "$libjsonc_LIBS"; then
+    pkg_cv_libjsonc_LIBS="$libjsonc_LIBS"
+ elif test -n "$PKG_CONFIG"; then
+    if test -n "$PKG_CONFIG" && \
+    { { printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"json-c\""; } >&5
+  ($PKG_CONFIG --exists --print-errors "json-c") 2>&5
+  ac_status=$?
+  printf "%s\n" "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; then
+  pkg_cv_libjsonc_LIBS=`$PKG_CONFIG --libs "json-c" 2>/dev/null`
+		      test "x$?" != "x0" && pkg_failed=yes
+else
+  pkg_failed=yes
+fi
+ else
+    pkg_failed=untried
+fi
+
+
+
+if test $pkg_failed = yes; then
+   	{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5
+printf "%s\n" "no" >&6; }
+
+if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then
+        _pkg_short_errors_supported=yes
+else
+        _pkg_short_errors_supported=no
+fi
+        if test $_pkg_short_errors_supported = yes; then
+	        libjsonc_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "json-c" 2>&1`
+        else
+	        libjsonc_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "json-c" 2>&1`
+        fi
+	# Put the nasty error message in config.log where it belongs
+	echo "$libjsonc_PKG_ERRORS" >&5
+
+	as_fn_error $? "Package requirements (json-c) were not met:
+
+$libjsonc_PKG_ERRORS
+
+Consider adjusting the PKG_CONFIG_PATH environment variable if you
+installed software in a non-standard prefix.
+
+Alternatively, you may set the environment variables libjsonc_CFLAGS
+and libjsonc_LIBS to avoid the need to call pkg-config.
+See the pkg-config man page for more details." "$LINENO" 5
+elif test $pkg_failed = untried; then
+     	{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5
+printf "%s\n" "no" >&6; }
+	{ { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "The pkg-config script could not be found or is too old.  Make sure it
+is in your PATH or set the PKG_CONFIG environment variable to the full
+path to pkg-config.
+
+Alternatively, you may set the environment variables libjsonc_CFLAGS
+and libjsonc_LIBS to avoid the need to call pkg-config.
+See the pkg-config man page for more details.
+
+To get pkg-config, see .
+See \`config.log' for more details" "$LINENO" 5; }
+else
+	libjsonc_CFLAGS=$pkg_cv_libjsonc_CFLAGS
+	libjsonc_LIBS=$pkg_cv_libjsonc_LIBS
+        { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+printf "%s\n" "yes" >&6; }
+
+printf "%s\n" "#define HAVE_LIBJSONC 1" >>confdefs.h
+
+fi
 { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for yajl_alloc in -lyajl" >&5
 printf %s "checking for yajl_alloc in -lyajl... " >&6; }
 if test ${ac_cv_lib_yajl_yajl_alloc+y}
@@ -9661,9 +9763,10 @@ fi
 printf "%s\n" "$ac_cv_lib_yajl_yajl_alloc" >&6; }
 if test "x$ac_cv_lib_yajl_yajl_alloc" = xyes
 then :
-  printf "%s\n" "#define HAVE_LIBYAJL 1" >>confdefs.h
+  YAJL_LIBS=-lyajl
 
-  LIBS="-lyajl $LIBS"
+
+printf "%s\n" "#define HAVE_LIBYAJL 1" >>confdefs.h
 
 else $as_nop
   as_fn_error $? "Could not find yajl" "$LINENO" 5
diff --git a/tools/configure.ac b/tools/configure.ac
index dada1c3b15..bb40b5b3f0 100644
--- a/tools/configure.ac
+++ b/tools/configure.ac
@@ -424,7 +424,11 @@ AC_SUBST([ZLIB_CFLAGS])
 AC_SUBST([ZLIB_LIBS])
 AX_CHECK_EXTFS
 AX_CHECK_PTHREAD
-AC_CHECK_LIB([yajl], [yajl_alloc], [],
+PKG_CHECK_MODULES([libjsonc], [json-c],
+    [AC_DEFINE([HAVE_LIBJSONC], [1], [Use library json-c])])
+AC_CHECK_LIB([yajl], [yajl_alloc],
+   [AC_SUBST([YAJL_LIBS],[-lyajl])
+    AC_DEFINE([HAVE_LIBYAJL],[1],[Define to 1 if you have the `yajl' library (-lyajl).])],
     [AC_MSG_ERROR([Could not find yajl])])
 AC_CHECK_LIB([z], [deflateCopy], [], [AC_MSG_ERROR([Could not find zlib])])
 AC_CHECK_HEADER([argp.h], [
diff --git a/tools/libs/light/Makefile b/tools/libs/light/Makefile
index b690d92159..fa2a338c2b 100644
--- a/tools/libs/light/Makefile
+++ b/tools/libs/light/Makefile
@@ -166,7 +166,8 @@ LDLIBS-$(CONFIG_Linux) += -luuid
 LDLIBS-$(CONFIG_Linux) += -lrt
 LDLIBS-$(CONFIG_ARM) += -lfdt
 LDLIBS-y += $(PTHREAD_LIBS)
-LDLIBS-y += -lyajl
+LDLIBS-y += $(YAJL_LIBS)
+LDLIBS-y += $(LIBJSONC_LIBS)
 LDLIBS += $(LDLIBS-y)
 
 $(OBJS-y) $(PIC_OBJS) $(LIBXL_TEST_OBJS): CFLAGS += $(CFLAGS_LIBXL) -include $(XEN_ROOT)/tools/config.h
@@ -246,7 +247,7 @@ libxenlight_test.so: $(PIC_OBJS) $(LIBXL_TEST_OBJS)
 	$(CC) $(LDFLAGS) -Wl,$(SONAME_LDFLAG) -Wl,libxenlight.so.$(MAJOR) $(SHLIB_LDFLAGS) -o $@ $^ $(LDLIBS) $(APPEND_LDFLAGS)
 
 test_%: test_%.o test_common.o libxenlight_test.so
-	$(CC) $(LDFLAGS) -o $@ $^ $(filter-out %libxenlight.so, $(LDLIBS_libxenlight)) $(LDLIBS_libxentoollog) $(LDLIBS_libxentoolcore) -lyajl $(APPEND_LDFLAGS)
+	$(CC) $(LDFLAGS) -o $@ $^ $(filter-out %libxenlight.so, $(LDLIBS_libxenlight)) $(LDLIBS_libxentoollog) $(LDLIBS_libxentoolcore) $(YAJL_LIBS) $(LIBJSONC_LIBS) $(APPEND_LDFLAGS)
 
 libxl-save-helper: $(SAVE_HELPER_OBJS) libxenlight.so
 	$(CC) $(LDFLAGS) -o $@ $(SAVE_HELPER_OBJS) $(LDLIBS_libxentoollog) $(LDLIBS_libxenctrl) $(LDLIBS_libxenguest) $(LDLIBS_libxentoolcore) $(APPEND_LDFLAGS)
diff --git a/tools/xl/Makefile b/tools/xl/Makefile
index ad577cdd70..ff7a5aee94 100644
--- a/tools/xl/Makefile
+++ b/tools/xl/Makefile
@@ -33,7 +33,7 @@ $(XL_OBJS): CFLAGS += -include $(XEN_ROOT)/tools/config.h # libxl_json.h needs i
 all: xl
 
 xl: $(XL_OBJS)
-	$(CC) $(LDFLAGS) -o $@ $(XL_OBJS) $(LDLIBS_libxenutil) $(LDLIBS_libxenlight) $(LDLIBS_libxentoollog) $(LDLIBS_libxenstore) -lyajl $(APPEND_LDFLAGS)
+	$(CC) $(LDFLAGS) -o $@ $(XL_OBJS) $(LDLIBS_libxenutil) $(LDLIBS_libxenlight) $(LDLIBS_libxentoollog) $(LDLIBS_libxenstore) $(YAJL_LIBS) $(LIBJSONC_LIBS) $(APPEND_LDFLAGS)
 
 .PHONY: install
 install: all
-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Juergen Gross 
Subject: [XEN PATCH 07/11] libxl: libxl__object_to_json() to json-c
Date: Fri,  8 Aug 2025 16:55:58 +0200
Message-Id: <20250808145602.41716-8-anthony@xenproject.org>
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From: Anthony PERARD 

- libxl changes:

While doing so, we rename all "*_gen_json" function to "*_gen_jso" as
they have different prototype. All the function pointer are been cast
to (libxl__gen_json_callback) by "gentypes.py" when generating
"*_to_json()" functions.

We also introduce a few more "*_gen_jso" functions for "int" and
"bool" because we can't use json_object_*() functions from json-c
directly like it's done with yajl.

To make the generation of _libxl_types*json.[ch] with both YAJL and
json-c we add "--libjsonc" to gentypes.py so it can generate
functions/types for both.

Also introducing "jsonc_json_gen_fn" in the IDL, to be able to point
to a different function when using json-c.

Also, don't export any of the new *_gen_jso() function, at the cost of
having "_hidden" macro in semi-public headers.

- xl changes:

Also, rework the implementation of printf_info() in `xl` to avoid
using libxl_domain_config_gen_json() which isn't available without
YAJL. The implementation using "json_object" call
libxl_domain_config_to_json() which generate a plain string of JSON,
which we parse to add it to our own json; this avoid a dependency on
the json library used by libxl.

Signed-off-by: Anthony PERARD 
---
 tools/include/libxl_json.h                |  17 ++
 tools/libs/light/Makefile                 |   2 +-
 tools/libs/light/gentypes.py              | 160 ++++++++++-
 tools/libs/light/idl.py                   |   7 +-
 tools/libs/light/libxl_cpuid.c            | 119 ++++++++
 tools/libs/light/libxl_internal.h         |  16 +-
 tools/libs/light/libxl_json.c             | 316 ++++++++++++++++++++++
 tools/libs/light/libxl_types.idl          |   7 +-
 tools/libs/light/libxl_types_internal.idl |   3 +-
 tools/xl/xl_info.c                        | 102 ++++++-
 10 files changed, 729 insertions(+), 20 deletions(-)

diff --git a/tools/include/libxl_json.h b/tools/include/libxl_json.h
index e2ef8151f0..c130e88a5e 100644
--- a/tools/include/libxl_json.h
+++ b/tools/include/libxl_json.h
@@ -28,6 +28,22 @@
 #endif
 #endif
 
+#ifdef HAVE_LIBJSONC
+#ifndef _hidden
+#define _hidden
+#endif
+_hidden int libxl__uint64_gen_jso(json_object **jso_r, uint64_t val);
+_hidden int libxl_defbool_gen_jso(json_object **jso_r, libxl_defbool *p);
+_hidden int libxl_uuid_gen_jso(json_object **jso_r, libxl_uuid *p);
+_hidden int libxl_mac_gen_jso(json_object **jso_r, libxl_mac *p);
+_hidden int libxl_bitmap_gen_jso(json_object **jso_r, libxl_bitmap *p);
+_hidden int libxl_cpuid_policy_list_gen_jso(json_object **jso_r,libxl_cpuid_policy_list *p);
+_hidden int libxl_string_list_gen_jso(json_object **jso_r,libxl_string_list *p);
+_hidden int libxl_key_value_list_gen_jso(json_object **jso_r, libxl_key_value_list *p);
+_hidden int libxl_hwcap_gen_jso(json_object **jso_r, libxl_hwcap *p);
+_hidden int libxl_ms_vm_genid_gen_jso(json_object **jso_r, libxl_ms_vm_genid *p);
+#endif
+#if defined(HAVE_LIBYAJL)
 yajl_gen_status libxl__uint64_gen_json(yajl_gen hand, uint64_t val);
 yajl_gen_status libxl_defbool_gen_json(yajl_gen hand, libxl_defbool *p);
 yajl_gen_status libxl_uuid_gen_json(yajl_gen hand, libxl_uuid *p);
@@ -40,6 +56,7 @@ yajl_gen_status libxl_key_value_list_gen_json(yajl_gen hand,
                                               libxl_key_value_list *p);
 yajl_gen_status libxl_hwcap_gen_json(yajl_gen hand, libxl_hwcap *p);
 yajl_gen_status libxl_ms_vm_genid_gen_json(yajl_gen hand, libxl_ms_vm_genid *p);
+#endif
 
 #include <_libxl_types_json.h>
 
diff --git a/tools/libs/light/Makefile b/tools/libs/light/Makefile
index fa2a338c2b..c59c2cf198 100644
--- a/tools/libs/light/Makefile
+++ b/tools/libs/light/Makefile
@@ -227,7 +227,7 @@ testidl.o: $(XEN_INCLUDE)/libxl.h
 # This exploits the 'multi-target pattern rule' trick.
 # gentypes.py should be executed only once to make all the targets.
 _libxl_type%.h _libxl_type%_json.h _libxl_type%_private.h _libxl_type%.c: libxl_type%.idl gentypes.py idl.py
-	$(PYTHON) gentypes.py libxl_type$(*F).idl __libxl_type$(*F).h __libxl_type$(*F)_private.h \
+	$(PYTHON) gentypes.py $(if $(LIBJSONC_LIBS),--libjsonc) libxl_type$(*F).idl __libxl_type$(*F).h __libxl_type$(*F)_private.h \
 		__libxl_type$(*F)_json.h  __libxl_type$(*F).c
 	$(call move-if-changed,__libxl_type$(*F).h,_libxl_type$(*F).h)
 	$(call move-if-changed,__libxl_type$(*F)_private.h,_libxl_type$(*F)_private.h)
diff --git a/tools/libs/light/gentypes.py b/tools/libs/light/gentypes.py
index 3fe3873242..006bea170a 100644
--- a/tools/libs/light/gentypes.py
+++ b/tools/libs/light/gentypes.py
@@ -256,6 +256,30 @@ def libxl_C_type_member_init(ty, field):
     s += "\n"
     return s
 
+# For json-c gen_jso functions
+def libxl_C_type_gen_jso_map_key(f, parent, indent, scope_object, sub_scope_object):
+    s = ""
+    if isinstance(f.type, idl.KeyedUnion):
+        s += "switch (%s) {\n" % (parent + f.type.keyvar.name)
+        for x in f.type.fields:
+            v = f.type.keyvar.name + "." + x.name
+            s += "case %s:\n" % x.enumname
+            s += "    if (json_object_object_add(%s, \"%s\", %s)) {\n" % (scope_object, v, sub_scope_object)
+            s += "        json_object_put(%s);\n" % (sub_scope_object)
+            s += "        goto out;\n"
+            s += "    }\n"
+            s += "    break;\n"
+        s += "}\n"
+    else:
+        s += "if (json_object_object_add(%s, \"%s\", %s)) {\n" % (scope_object, f.name, sub_scope_object)
+        s += "    json_object_put(%s);\n" % (sub_scope_object)
+        s += "    goto out;\n"
+        s += "}\n"
+    if s != "":
+        s = indent + s
+    return s.replace("\n", "\n%s" % indent).rstrip(indent)
+
+# For YAJL gen_json functions
 def libxl_C_type_gen_map_key(f, parent, indent = ""):
     s = ""
     if isinstance(f.type, idl.KeyedUnion):
@@ -352,6 +376,86 @@ def get_default_expr(f, nparent, fexpr):
 
     return "%s" % fexpr
 
+# For json-c gen_json functions
+def libxl_C_type_gen_jso(ty, v, indent = "    ", parent = None, scope_object = "jso"):
+    s = ""
+    if parent is None:
+        s += "json_object *jso;\n"
+        s += "int rc;\n"
+        sub_scope_object = "jso_sub_1"
+    else:
+        sub_scope_object = "jso_sub_%d" % (1+int(scope_object.removeprefix("jso_sub_")))
+
+    if isinstance(ty, idl.Array):
+        if parent is None:
+            raise Exception("Array type must have a parent")
+        s += "{\n"
+        s += "    int i;\n"
+        s += "    %s = json_object_new_array_ext(%s);\n" % (scope_object, parent + ty.lenvar.name)
+        s += "    if (!%s)\n" % (scope_object)
+        s += "        goto out;\n"
+        s += "    for (i=0; i<%s; i++) {\n" % (parent + ty.lenvar.name)
+        s += "        json_object *%s;\n" % (sub_scope_object)
+        # remove some indent, it's over indented at least in one case libxl_vcpu_sched_params_gen_json
+        s += libxl_C_type_gen_jso(ty.elem_type, v+"[i]",
+                                   indent + "    ", parent, sub_scope_object)
+        s += "        if (json_object_array_add(%s, %s)) {\n" % (scope_object, sub_scope_object)
+        s += "            json_object_put(%s);\n" % (sub_scope_object)
+        s += "            goto out;\n"
+        s += "        }\n"
+        s += "    }\n"
+        s += "}\n"
+    elif isinstance(ty, idl.Enumeration):
+        s += "rc = libxl__enum_gen_jso(&%s, %s_to_string(%s));\n" % (scope_object, ty.typename, ty.pass_arg(v, parent is None))
+        s += "if (rc)\n"
+        s += "    goto out;\n"
+    elif isinstance(ty, idl.KeyedUnion):
+        if parent is None:
+            raise Exception("KeyedUnion type must have a parent")
+        s += "switch (%s) {\n" % (parent + ty.keyvar.name)
+        for f in ty.fields:
+            (nparent,fexpr) = ty.member(v, f, parent is None)
+            s += "case %s:\n" % f.enumname
+            if f.type is not None:
+                s += libxl_C_type_gen_jso(f.type, fexpr, indent + "    ", nparent, scope_object)
+            else:
+                s += "    %s = json_object_new_object();\n" % (scope_object)
+                s += "    if (!%s)\n" % (scope_object)
+                s += "        goto out;\n"
+            s += "    break;\n"
+        s += "}\n"
+    elif isinstance(ty, idl.Struct) and (parent is None or ty.json_gen_fn is None):
+        s += "%s = json_object_new_object();\n" % (scope_object)
+        s += "if (!%s)\n" % (scope_object)
+        s += "    goto out;\n"
+        for f in [f for f in ty.fields if not f.const and not f.type.private]:
+            (nparent,fexpr) = ty.member(v, f, parent is None)
+            default_expr = get_default_expr(f, nparent, fexpr)
+            s += "if (%s) {\n" % default_expr
+            s += "    json_object *%s = NULL;\n" % (sub_scope_object)
+            s += libxl_C_type_gen_jso(f.type, fexpr, "    ", nparent, sub_scope_object)
+            s += libxl_C_type_gen_jso_map_key(f, nparent, "    ", scope_object, sub_scope_object)
+
+            s += "}\n"
+
+    else:
+        if ty.json_gen_fn is not None:
+            s += "rc = %s(&%s, %s);\n" % (ty.json_gen_fn, scope_object, ty.pass_arg(v, parent is None))
+            s += "if (rc)\n"
+            s += "    goto out;\n"
+
+    if parent is None:
+        s += "*jso_r = jso;\n"
+        s += "return 0;\n"
+        s += "out:\n"
+        s += "json_object_put(jso);\n"
+        s += "return ERROR_FAIL;\n"
+
+    if s != "":
+        s = indent + s
+    return s.replace("\n", "\n%s" % indent).rstrip(indent)
+
+# For YAJL gen_json functions
 def libxl_C_type_gen_json(ty, v, indent = "    ", parent = None):
     s = ""
     if parent is None:
@@ -426,9 +530,9 @@ def libxl_C_type_gen_json(ty, v, indent = "    ", parent = None):
         s = indent + s
     return s.replace("\n", "\n%s" % indent).rstrip(indent)
 
-def libxl_C_type_to_json(ty, v, indent = "    "):
+def libxl_C_type_to_json(ty, v, indent = "    ", fn_ptr_type="libxl__gen_json_callback", fn_suffix="_gen_json"):
     s = ""
-    gen = "(libxl__gen_json_callback)&%s_gen_json" % ty.typename
+    gen = "(%s)&%s%s" % (fn_ptr_type, ty.typename, fn_suffix)
     s += "return libxl__object_to_json(ctx, \"%s\", %s, (void *)%s);\n" % (ty.typename, gen, ty.pass_arg(v, passby=idl.PASS_BY_REFERENCE))
 
     if s != "":
@@ -589,14 +693,38 @@ def clean_header_define(header_path):
 
 
 if __name__ == '__main__':
+    opt_libjsonc = False
+    if len(sys.argv) == 7:
+        if sys.argv.pop(1) == "--libjsonc":
+            opt_libjsonc = True
     if len(sys.argv) != 6:
         print("Usage: gentypes.py  
       ", file=sys.stderr)
         sys.exit(1)
 
     (_, idlname, header, header_private, header_json, impl) = sys.argv
 
+    # Overwrite `json_gen_fn` for standard types
+    if opt_libjsonc:
+        idl.bool.json_gen_fn = "libxl__boolean_gen_jso"
+        idl.size_t.json_gen_fn = "libxl__int_gen_jso"
+        idl.integer .json_gen_fn = "libxl__int_gen_jso"
+        idl.uint8.json_gen_fn = "libxl__int_gen_jso"
+        idl.uint16.json_gen_fn = "libxl__int_gen_jso"
+        idl.uint32.json_gen_fn = "libxl__int_gen_jso"
+        idl.uint64.json_gen_fn = "libxl__uint64_gen_jso"
+        idl.string.json_gen_fn = "libxl__string_gen_jso"
+
     (builtins,types) = idl.parse(idlname)
 
+    # Overwrite `json_gen_fn` with `jsonc_json_gen_fn` for types from the IDL
+    if opt_libjsonc:
+        for t in builtins:
+            if t.jsonc_json_gen_fn is not None:
+                t.json_gen_fn = t.jsonc_json_gen_fn
+        for t in types:
+            if t.jsonc_json_gen_fn is not None:
+                t.json_gen_fn = t.jsonc_json_gen_fn
+
     print("outputting libxl type definitions to %s" % header)
 
     f = open(header, "w")
@@ -665,7 +793,11 @@ if __name__ == '__main__':
 """ % (header_json_define, header_json_define, " ".join(sys.argv)))
 
     for ty in [ty for ty in types if ty.json_gen_fn is not None]:
-        f.write("%syajl_gen_status %s_gen_json(yajl_gen hand, %s);\n" % (ty.hidden(), ty.typename, ty.make_arg("p", passby=idl.PASS_BY_REFERENCE)))
+        if opt_libjsonc:
+            # Always hide JSON generators base on json-c
+            f.write("%sint %s_gen_jso(json_object **jso_r, %s);\n" % ("_hidden ", ty.typename, ty.make_arg("p", passby=idl.PASS_BY_REFERENCE)))
+        else:
+            f.write("%syajl_gen_status %s_gen_json(yajl_gen hand, %s);\n" % (ty.hidden(), ty.typename, ty.make_arg("p", passby=idl.PASS_BY_REFERENCE)))
 
     f.write("\n")
     f.write("""#endif /* %s */\n""" % header_json_define)
@@ -769,15 +901,25 @@ if __name__ == '__main__':
         f.write("\n")
 
     for ty in [t for t in types if t.json_gen_fn is not None]:
-        f.write("yajl_gen_status %s_gen_json(yajl_gen hand, %s)\n" % (ty.typename, ty.make_arg("p", passby=idl.PASS_BY_REFERENCE)))
-        f.write("{\n")
-        f.write(libxl_C_type_gen_json(ty, "p"))
-        f.write("}\n")
-        f.write("\n")
+        if opt_libjsonc:
+            f.write("int %s_gen_jso(json_object **jso_r, %s)\n" % (ty.typename, ty.make_arg("p", passby=idl.PASS_BY_REFERENCE)))
+            f.write("{\n")
+            f.write(libxl_C_type_gen_jso(ty, "p"))
+            f.write("}\n")
+            f.write("\n")
+        else:
+            f.write("yajl_gen_status %s_gen_json(yajl_gen hand, %s)\n" % (ty.typename, ty.make_arg("p", passby=idl.PASS_BY_REFERENCE)))
+            f.write("{\n")
+            f.write(libxl_C_type_gen_json(ty, "p"))
+            f.write("}\n")
+            f.write("\n")
 
         f.write("char *%s_to_json(libxl_ctx *ctx, %s)\n" % (ty.typename, ty.make_arg("p")))
         f.write("{\n")
-        f.write(libxl_C_type_to_json(ty, "p"))
+        if opt_libjsonc:
+            f.write(libxl_C_type_to_json(ty, "p", fn_ptr_type="libxl__gen_json_callback", fn_suffix="_gen_jso"))
+        else:
+            f.write(libxl_C_type_to_json(ty, "p", fn_ptr_type="libxl__gen_json_callback", fn_suffix="_gen_json"))
         f.write("}\n")
         f.write("\n")
 
diff --git a/tools/libs/light/idl.py b/tools/libs/light/idl.py
index d7367503b4..61c8e14004 100644
--- a/tools/libs/light/idl.py
+++ b/tools/libs/light/idl.py
@@ -79,6 +79,7 @@ class Type(object):
 
         if self.typename is not None and not self.private:
             self.json_gen_fn = kwargs.setdefault('json_gen_fn', self.typename + "_gen_json")
+            self.jsonc_json_gen_fn = kwargs.setdefault('jsonc_json_gen_fn', self.typename + "_gen_jso")
             self.json_parse_type = kwargs.setdefault('json_parse_type', "JSON_ANY")
             if self.namespace is not None:
                 self.json_parse_fn = kwargs.setdefault('json_parse_fn',
@@ -88,6 +89,7 @@ class Type(object):
                                                        self.typename + "_parse_json")
         else:
             self.json_gen_fn = kwargs.setdefault('json_gen_fn', None)
+            self.jsonc_json_gen_fn = kwargs.setdefault('jsonc_json_gen_fn', None)
             self.json_parse_type = kwargs.setdefault('json_parse_type', None)
             self.json_parse_fn = kwargs.setdefault('json_parse_fn', None)
 
@@ -142,6 +144,7 @@ class Number(Builtin):
         kwargs.setdefault('copy_fn', None)
         kwargs.setdefault('signed', False)
         kwargs.setdefault('json_gen_fn', "yajl_gen_integer")
+        kwargs.setdefault('jsonc_json_gen_fn', "libxl__int_gen_jso")
         kwargs.setdefault('json_parse_type', "JSON_INTEGER")
         # json_parse_fn might be overriden on specific type
         kwargs.setdefault('json_parse_fn', "libxl__int_parse_json")
@@ -290,6 +293,7 @@ void = Builtin("void *", namespace = None)
 bool = Builtin("bool", namespace = None,
                copy_fn=None,
                json_gen_fn = "yajl_gen_bool",
+               jsonc_json_gen_fn = "libxl__boolean_gen_jso",
                json_parse_type = "JSON_BOOL",
                json_parse_fn = "libxl__bool_parse_json",
                autogenerate_json = False)
@@ -301,10 +305,11 @@ integer = Number("int", namespace = None, signed = True)
 uint8 = UInt(8)
 uint16 = UInt(16)
 uint32 = UInt(32)
-uint64 = UInt(64, json_gen_fn = "libxl__uint64_gen_json")
+uint64 = UInt(64, json_gen_fn = "libxl__uint64_gen_json", jsonc_json_gen_fn = "libxl__uint64_gen_jso")
 
 string = Builtin("char *", namespace = None, copy_fn = "libxl_string_copy", dispose_fn = "free",
                  json_gen_fn = "libxl__string_gen_json",
+                 jsonc_json_gen_fn = "libxl__string_gen_jso",
                  json_parse_type = "JSON_STRING | JSON_NULL",
                  json_parse_fn = "libxl__string_parse_json",
                  autogenerate_json = False,
diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c
index f738e17b19..8420b2465f 100644
--- a/tools/libs/light/libxl_cpuid.c
+++ b/tools/libs/light/libxl_cpuid.c
@@ -545,6 +545,124 @@ static const char *policy_names[4] = { "eax", "ebx", "ecx", "edx" };
  * }
  */
 
+#ifdef HAVE_LIBJSONC
+int libxl_cpuid_policy_list_gen_jso(json_object **jso_r, libxl_cpuid_policy_list *pl)
+{
+    libxl_cpuid_policy_list policy = *pl;
+    struct xc_xend_cpuid *cpuid;
+    const struct xc_msr *msr;
+    json_object *jso_outer;
+    json_object *jso_array;
+    int i, j;
+    int r;
+    int rc = ERROR_FAIL;
+
+    jso_outer = json_object_new_object();
+    if (!jso_outer) goto out;
+
+    jso_array = json_object_new_array();
+    if (!jso_array) goto out;
+
+    r = json_object_object_add(jso_outer, "cpuid", jso_array);
+    if (r < 0) {
+        json_object_put(jso_array);
+        goto out;
+    }
+
+    if (policy == NULL || policy->cpuid == NULL) goto empty;
+    cpuid = policy->cpuid;
+
+    for (i = 0; cpuid[i].input[0] != XEN_CPUID_INPUT_UNUSED; i++) {
+        json_object *jso_inner;
+        jso_inner = json_object_new_object();
+        if (!jso_inner) goto out;
+
+        r = json_object_array_add(jso_array, jso_inner);
+        if (r < 0) {
+            json_object_put(jso_inner);
+            goto out;
+        }
+
+        for (j = 0; j < 2; j++) {
+            if (cpuid[i].input[j] != XEN_CPUID_INPUT_UNUSED) {
+                json_object *jso_value = json_object_new_int(cpuid[i].input[j]);
+                if (!jso_value) goto out;
+                r = json_object_object_add(jso_inner, input_names[j], jso_value);
+                if (r < 0) {
+                    json_object_put(jso_value);
+                    goto out;
+                }
+            }
+        }
+
+        for (j = 0; j < 4; j++) {
+            if (cpuid[i].policy[j] != NULL) {
+                json_object *jso_value = json_object_new_string_len(cpuid[i].policy[j], 32);
+                if (!jso_value) goto out;
+                r = json_object_object_add(jso_inner, policy_names[j], jso_value);
+                if (r < 0) {
+                    json_object_put(jso_value);
+                    goto out;
+                }
+            }
+        }
+    }
+
+empty:
+
+    jso_array = json_object_new_array();
+    if (!jso_array) goto out;
+
+    r = json_object_object_add(jso_outer, "msr", jso_array);
+    if (r < 0) {
+        json_object_put(jso_array);
+        goto out;
+    }
+
+    if (!policy || !policy->msr) goto done;
+    msr = policy->msr;
+
+    for (i = 0; msr[i].index != XC_MSR_INPUT_UNUSED; i++) {
+        json_object *jso_inner;
+        json_object *jso_value;
+
+        jso_inner = json_object_new_object();
+        if (!jso_inner) goto out;
+
+        r = json_object_array_add(jso_array, jso_inner);
+        if (r < 0) {
+            json_object_put(jso_inner);
+            goto out;
+        }
+
+        jso_value = json_object_new_int(msr[i].index);
+        if (!jso_value) goto out;
+        r = json_object_object_add(jso_inner, "index", jso_value);
+        if (r < 0) {
+            json_object_put(jso_value);
+            goto out;
+        }
+
+        jso_value = json_object_new_string_len(msr[i].policy, 64);
+        if (!jso_value) goto out;
+        r = json_object_object_add(jso_inner, "policy", jso_value);
+        if (r < 0) {
+            json_object_put(jso_value);
+            goto out;
+        }
+    }
+
+done:
+    *jso_r = jso_outer;
+    jso_outer = NULL;
+    rc = 0;
+out:
+    json_object_put(jso_outer);
+    return rc;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl_cpuid_policy_list_gen_json(yajl_gen hand,
                                 libxl_cpuid_policy_list *pl)
 {
@@ -630,6 +748,7 @@ yajl_gen_status libxl_cpuid_policy_list_gen_json(yajl_gen hand,
 out:
     return s;
 }
+#endif
 
 int libxl__cpuid_policy_list_parse_json(libxl__gc *gc,
                                         const libxl__json_object *o,
diff --git a/tools/libs/light/libxl_internal.h b/tools/libs/light/libxl_internal.h
index b66aaa779d..0f707e4204 100644
--- a/tools/libs/light/libxl_internal.h
+++ b/tools/libs/light/libxl_internal.h
@@ -1993,9 +1993,11 @@ _hidden char *libxl__cpupoolid_to_name(libxl__gc *gc, uint32_t poolid);
 _hidden int libxl__enum_from_string(const libxl_enum_string_table *t,
                                     const char *s, int *e) NN(2);
 
-_hidden yajl_gen_status libxl__string_gen_json(yajl_gen hand, const char *p);
-
+#ifdef HAVE_LIBJSONC
+typedef int (*libxl__gen_json_callback)(json_object **jso_r, void *);
+#elif defined(HAVE_LIBYAJL)
 typedef yajl_gen_status (*libxl__gen_json_callback)(yajl_gen hand, void *);
+#endif
 _hidden char *libxl__object_to_json(libxl_ctx *ctx, const char *type,
                                     libxl__gen_json_callback gen, void *p);
 
@@ -2084,11 +2086,21 @@ int libxl__recvmsg_fds(libxl__gc *gc, int carrier,
                        void *databuf, size_t datalen,
                        int nfds, int fds[], const char *what);
 
+#ifdef HAVE_LIBJSONC
+_hidden int libxl__enum_gen_jso(json_object **jso_r, const char *str);
+_hidden int libxl__int_gen_jso(json_object **jso_r, int i);
+_hidden int libxl__boolean_gen_jso(json_object **jso_r, bool b);
+_hidden int libxl__string_gen_jso(json_object **jso_r, const char *p);
+#endif
+
+#ifdef HAVE_LIBYAJL
 /* from libxl_json */
 #include 
 
 _hidden yajl_gen_status libxl__yajl_gen_asciiz(yajl_gen hand, const char *str);
 _hidden yajl_gen_status libxl__yajl_gen_enum(yajl_gen hand, const char *str);
+_hidden yajl_gen_status libxl__string_gen_json(yajl_gen hand, const char *p);
+#endif
 
 typedef enum {
     JSON_NULL    = (1 << 0),
diff --git a/tools/libs/light/libxl_json.c b/tools/libs/light/libxl_json.c
index b26ac901d6..01944ef94d 100644
--- a/tools/libs/light/libxl_json.c
+++ b/tools/libs/light/libxl_json.c
@@ -19,12 +19,16 @@
 #ifdef HAVE_LIBJSONC
 #include 
 #define USE_LIBJSONC_PARSER
+#define USE_LIBJSONC_GEN
 #endif
 
 #ifdef HAVE_LIBYAJL
 #  ifndef USE_LIBJSONC_PARSER
 #    define USE_LIBYAJL_PARSER
 #  endif
+#  ifndef USE_LIBJSONC_GEN
+#    define USE_LIBYAJL_GEN
+#  endif
 #endif
 
 
@@ -35,7 +39,9 @@
 #ifdef USE_LIBYAJL_PARSER
 #include 
 #endif
+#ifdef USE_LIBYAJL_GEN
 #include 
+#endif
 
 #include "libxl_internal.h"
 
@@ -103,6 +109,21 @@ yajl_gen_status libxl__yajl_gen_asciiz(yajl_gen hand, const char *str)
     return yajl_gen_string(hand, (const unsigned char *)str, strlen(str));
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl__enum_gen_jso(json_object **jso_r, const char *str)
+{
+    if (str) {
+        *jso_r = json_object_new_string(str);
+        if (!*jso_r)
+            return ERROR_FAIL;
+    } else {
+        *jso_r = json_object_new_null();
+    }
+    return 0;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl__yajl_gen_enum(yajl_gen hand, const char *str)
 {
     if (str)
@@ -110,15 +131,28 @@ yajl_gen_status libxl__yajl_gen_enum(yajl_gen hand, const char *str)
     else
         return yajl_gen_null(hand);
 }
+#endif
 
 /*
  * YAJL generators for builtin libxl types.
  */
+#ifdef HAVE_LIBJSONC
+int libxl_defbool_gen_jso(json_object **jso_r, libxl_defbool *db)
+{
+    *jso_r = json_object_new_string(libxl_defbool_to_string(*db));
+    if (!*jso_r)
+        return ERROR_FAIL;
+    return 0;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl_defbool_gen_json(yajl_gen hand,
                                        libxl_defbool *db)
 {
     return libxl__yajl_gen_asciiz(hand, libxl_defbool_to_string(*db));
 }
+#endif
 
 int libxl__defbool_parse_json(libxl__gc *gc, const libxl__json_object *o,
                               libxl_defbool *p)
@@ -145,6 +179,16 @@ int libxl__defbool_parse_json(libxl__gc *gc, const libxl__json_object *o,
     return 0;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl__boolean_gen_jso(json_object **jso_r, bool b)
+{
+    *jso_r = json_object_new_boolean(b);
+    if (!*jso_r)
+        return ERROR_FAIL;
+    return 0;
+}
+#endif
+
 int libxl__bool_parse_json(libxl__gc *gc, const libxl__json_object *o,
                            bool *p)
 {
@@ -156,6 +200,19 @@ int libxl__bool_parse_json(libxl__gc *gc, const libxl__json_object *o,
     return 0;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl_uuid_gen_jso(json_object **jso_r, libxl_uuid *uuid)
+{
+    char buf[LIBXL_UUID_FMTLEN+1];
+    snprintf(buf, sizeof(buf), LIBXL_UUID_FMT, LIBXL_UUID_BYTES((*uuid)));
+    *jso_r = json_object_new_string_len(buf, LIBXL_UUID_FMTLEN);
+    if (!*jso_r)
+        return ERROR_FAIL;
+    return 0;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl_uuid_gen_json(yajl_gen hand,
                                     libxl_uuid *uuid)
 {
@@ -163,6 +220,7 @@ yajl_gen_status libxl_uuid_gen_json(yajl_gen hand,
     snprintf(buf, sizeof(buf), LIBXL_UUID_FMT, LIBXL_UUID_BYTES((*uuid)));
     return yajl_gen_string(hand, (const unsigned char *)buf, LIBXL_UUID_FMTLEN);
 }
+#endif
 
 int libxl__uuid_parse_json(libxl__gc *gc, const libxl__json_object *o,
                            libxl_uuid *p)
@@ -173,6 +231,39 @@ int libxl__uuid_parse_json(libxl__gc *gc, const libxl__json_object *o,
     return libxl_uuid_from_string(p, o->u.string);
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl_bitmap_gen_jso(json_object **jso_r, libxl_bitmap *bitmap)
+{
+    json_object *jso;
+    int i;
+    int r;
+    int rc = ERROR_FAIL;
+
+    jso = json_object_new_array();
+    if (!jso) goto out;
+
+    libxl_for_each_bit(i, *bitmap) {
+        if (libxl_bitmap_test(bitmap, i)) {
+            json_object *jso_value = json_object_new_int(i);
+            if (!jso_value) goto out;
+            r = json_object_array_add(jso, jso_value);
+            if (r) {
+                json_object_put(jso_value);
+                goto out;
+            }
+        }
+    }
+
+    *jso_r = jso;
+    jso = NULL;
+    rc = 0;
+out:
+    json_object_put(jso);
+    return rc;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl_bitmap_gen_json(yajl_gen hand,
                                       libxl_bitmap *bitmap)
 {
@@ -192,6 +283,7 @@ yajl_gen_status libxl_bitmap_gen_json(yajl_gen hand,
 out:
     return s;
 }
+#endif
 
 int libxl__bitmap_parse_json(libxl__gc *gc, const libxl__json_object *o,
                             libxl_bitmap *p)
@@ -227,6 +319,42 @@ int libxl__bitmap_parse_json(libxl__gc *gc, const libxl__json_object *o,
     return 0;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl_key_value_list_gen_jso(json_object **jso_r, libxl_key_value_list *pkvl)
+{
+    libxl_key_value_list kvl = *pkvl;
+    json_object *jso;
+    int i;
+
+    jso = json_object_new_object();
+    if (!jso) goto out;
+
+    if (!kvl) goto empty;
+
+    for (i = 0; kvl[i] != NULL; i += 2) {
+        json_object *jso_value;
+        if (kvl[i + 1]) {
+            jso_value = json_object_new_string(kvl[i+1]);
+            if (!jso_value) goto out;
+        } else {
+            jso_value = json_object_new_null();
+        }
+        int r = json_object_object_add(jso, kvl[i], jso_value);
+        if (r) {
+            json_object_put(jso_value);
+            goto out;
+        }
+    }
+empty:
+    *jso_r = jso;
+    return 0;
+out:
+    json_object_put(jso);
+    return ERROR_FAIL;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl_key_value_list_gen_json(yajl_gen hand,
                                               libxl_key_value_list *pkvl)
 {
@@ -253,6 +381,7 @@ yajl_gen_status libxl_key_value_list_gen_json(yajl_gen hand,
 out:
     return s;
 }
+#endif
 
 int libxl__key_value_list_parse_json(libxl__gc *gc, const libxl__json_object *o,
                                      libxl_key_value_list *p)
@@ -289,6 +418,39 @@ int libxl__key_value_list_parse_json(libxl__gc *gc, const libxl__json_object *o,
     return 0;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl_string_list_gen_jso(json_object **jso_r, libxl_string_list *pl)
+{
+    libxl_string_list l = *pl;
+    json_object *jso;
+    int i;
+    int rc = ERROR_FAIL;
+
+    jso = json_object_new_array();
+    if (!jso) goto out;
+
+    if (!l) goto empty;
+
+    for (i = 0; l[i] != NULL; i++) {
+        json_object *jso_value = json_object_new_string(l[i]);
+        if (!jso_value) goto out;
+        int r = json_object_array_add(jso, jso_value);
+        if (r) {
+            json_object_put(jso_value);
+            goto out;
+        }
+    }
+empty:
+    *jso_r = jso;
+    jso = NULL;
+    rc = 0;
+out:
+    json_object_put(jso);
+    return rc;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl_string_list_gen_json(yajl_gen hand, libxl_string_list *pl)
 {
     libxl_string_list l = *pl;
@@ -309,6 +471,7 @@ yajl_gen_status libxl_string_list_gen_json(yajl_gen hand, libxl_string_list *pl)
 out:
     return s;
 }
+#endif
 
 int libxl__string_list_parse_json(libxl__gc *gc, const libxl__json_object *o,
                                   libxl_string_list *p)
@@ -342,12 +505,26 @@ int libxl__string_list_parse_json(libxl__gc *gc, const libxl__json_object *o,
     return 0;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl_mac_gen_jso(json_object **jso_r, libxl_mac *mac)
+{
+    char buf[LIBXL_MAC_FMTLEN+1];
+    snprintf(buf, sizeof(buf), LIBXL_MAC_FMT, LIBXL_MAC_BYTES((*mac)));
+    *jso_r = json_object_new_string_len(buf, LIBXL_MAC_FMTLEN);
+    if (!*jso_r)
+        return ERROR_FAIL;
+    return 0;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl_mac_gen_json(yajl_gen hand, libxl_mac *mac)
 {
     char buf[LIBXL_MAC_FMTLEN+1];
     snprintf(buf, sizeof(buf), LIBXL_MAC_FMT, LIBXL_MAC_BYTES((*mac)));
     return yajl_gen_string(hand, (const unsigned char *)buf, LIBXL_MAC_FMTLEN);
 }
+#endif
 
 int libxl__mac_parse_json(libxl__gc *gc, const libxl__json_object *o,
                           libxl_mac *p)
@@ -358,6 +535,36 @@ int libxl__mac_parse_json(libxl__gc *gc, const libxl__json_object *o,
     return libxl__parse_mac(libxl__json_object_get_string(o), *p);
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl_hwcap_gen_jso(json_object **jso_r, libxl_hwcap *p)
+{
+    json_object *jso;
+    int i;
+    int rc = ERROR_FAIL;
+
+    jso = json_object_new_array();
+    if (!jso) goto out;
+
+    for(i=0; i<4; i++) {
+        json_object *jso_value = json_object_new_int((*p)[i]);
+        if (!jso_value)
+            goto out;
+        int r = json_object_array_add(jso, jso_value);
+        if (r) {
+            json_object_put(jso_value);
+            goto out;
+        }
+    }
+    *jso_r = jso;
+    jso = NULL;
+    rc = 0;
+out:
+    json_object_put(jso);
+    return rc;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl_hwcap_gen_json(yajl_gen hand,
                                      libxl_hwcap *p)
 {
@@ -375,6 +582,7 @@ yajl_gen_status libxl_hwcap_gen_json(yajl_gen hand,
 out:
     return s;
 }
+#endif
 
 int libxl__hwcap_parse_json(libxl__gc *gc, const libxl__json_object *o,
                             libxl_hwcap *p)
@@ -397,6 +605,37 @@ int libxl__hwcap_parse_json(libxl__gc *gc, const libxl__json_object *o,
     return 0;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl_ms_vm_genid_gen_jso(json_object **jso_r, libxl_ms_vm_genid *p)
+{
+    json_object *jso;
+    int i;
+    int rc = ERROR_FAIL;
+
+    jso = json_object_new_array_ext(LIBXL_MS_VM_GENID_LEN);
+    if (!jso) goto out;
+
+    for (i = 0; i < LIBXL_MS_VM_GENID_LEN; i++) {
+        json_object *jso_value = json_object_new_int(p->bytes[i]);
+        if (!jso_value)
+            goto out;
+        int r = json_object_array_add(jso, jso_value);
+        if (r) {
+            json_object_put(jso_value);
+            goto out;
+        }
+    }
+
+    *jso_r = jso;
+    jso = NULL;
+    rc = 0;
+out:
+    json_object_put(jso);
+    return rc;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl_ms_vm_genid_gen_json(yajl_gen hand, libxl_ms_vm_genid *p)
 {
     yajl_gen_status s;
@@ -414,6 +653,7 @@ yajl_gen_status libxl_ms_vm_genid_gen_json(yajl_gen hand, libxl_ms_vm_genid *p)
 
     return yajl_gen_array_close(hand);
 }
+#endif
 
 int libxl__ms_vm_genid_parse_json(libxl__gc *gc, const libxl__json_object *o,
                                   libxl_ms_vm_genid *p)
@@ -436,6 +676,21 @@ int libxl__ms_vm_genid_parse_json(libxl__gc *gc, const libxl__json_object *o,
     return 0;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl__string_gen_jso(json_object **jso_r, const char *p)
+{
+    if (p) {
+        *jso_r = json_object_new_string(p);
+        if (!*jso_r)
+            return ERROR_FAIL;
+    } else {
+        *jso_r = json_object_new_null();
+    }
+    return 0;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl__string_gen_json(yajl_gen hand,
                                        const char *p)
 {
@@ -444,6 +699,7 @@ yajl_gen_status libxl__string_gen_json(yajl_gen hand,
     else
         return yajl_gen_null(hand);
 }
+#endif
 
 int libxl__string_parse_json(libxl__gc *gc, const libxl__json_object *o,
                              char **p)
@@ -1161,6 +1417,7 @@ libxl__json_object *libxl__json_parse(libxl__gc *gc, const char *s)
     return NULL;
 }
 
+#ifdef USE_LIBYAJL_GEN
 static const char *yajl_gen_status_to_string(yajl_gen_status s)
 {
         switch (s) {
@@ -1185,7 +1442,43 @@ static const char *yajl_gen_status_to_string(yajl_gen_status s)
             return "unknown error";
         }
 }
+#endif
 
+#ifdef USE_LIBJSONC_GEN
+char *libxl__object_to_json(libxl_ctx *ctx, const char *type,
+                            libxl__gen_json_callback gen, void *p)
+{
+    const char *buf;
+    char *ret = NULL;
+    json_object *jso = NULL;
+    int rc;
+
+    rc = gen(&jso, p);
+    if (rc)
+        goto out;
+
+    buf = json_object_to_json_string_ext(jso, JSON_C_TO_STRING_PRETTY);
+    if (!buf)
+        goto out;
+    ret = strdup((const char *)buf);
+
+out:
+    json_object_put(jso);
+
+    if (rc) {
+        LIBXL__LOG(ctx, LIBXL__LOG_ERROR,
+                   "unable to convert %s to JSON representation. ",
+                   type);
+    } else if (!ret) {
+        LIBXL__LOG(ctx, LIBXL__LOG_ERROR,
+                   "unable to allocate space for to JSON representation of %s",
+                   type);
+    }
+
+    return ret;
+}
+
+#elif defined(USE_LIBYAJL_GEN)
 char *libxl__object_to_json(libxl_ctx *ctx, const char *type,
                             libxl__gen_json_callback gen, void *p)
 {
@@ -1224,6 +1517,7 @@ char *libxl__object_to_json(libxl_ctx *ctx, const char *type,
 
     return ret;
 }
+#endif
 
 char *libxl__json_object_to_json(libxl__gc *gc,
                                  const libxl__json_object *args)
@@ -1257,6 +1551,17 @@ char *libxl__json_object_to_json(libxl__gc *gc,
     return ret;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl__uint64_gen_jso(json_object **jso_r, uint64_t val)
+{
+    *jso_r = json_object_new_uint64(val);
+    if (!*jso_r)
+        return ERROR_FAIL;
+    return 0;
+}
+#endif
+
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl__uint64_gen_json(yajl_gen hand, uint64_t val)
 {
     char *num;
@@ -1277,6 +1582,7 @@ yajl_gen_status libxl__uint64_gen_json(yajl_gen hand, uint64_t val)
 out:
     return s;
 }
+#endif
 
 int libxl__object_from_json(libxl_ctx *ctx, const char *type,
                             libxl__json_parse_callback parse,
@@ -1308,6 +1614,16 @@ int libxl__object_from_json(libxl_ctx *ctx, const char *type,
     return rc;
 }
 
+#ifdef HAVE_LIBJSONC
+int libxl__int_gen_jso(json_object **jso_r, int i)
+{
+    *jso_r = json_object_new_int(i);
+    if (!*jso_r)
+        return ERROR_FAIL;
+    return 0;
+}
+#endif
+
 int libxl__int_parse_json(libxl__gc *gc, const libxl__json_object *o,
                           void *p)
 {
diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl
index a6030a2dbd..caeddbcdc0 100644
--- a/tools/libs/light/libxl_types.idl
+++ b/tools/libs/light/libxl_types.idl
@@ -7,9 +7,9 @@ namespace("libxl_")
 
 libxl_defbool = Builtin("defbool", json_parse_type="JSON_STRING", passby=PASS_BY_REFERENCE, copy_fn=None,
                         check_default_fn="libxl__defbool_is_default")
-libxl_domid = Builtin("domid", json_gen_fn = "yajl_gen_integer", json_parse_fn = "libxl__uint32_parse_json",
+libxl_domid = Builtin("domid", json_gen_fn = "yajl_gen_integer", jsonc_json_gen_fn = "libxl__uint64_gen_jso", json_parse_fn = "libxl__uint32_parse_json",
                       json_parse_type = "JSON_INTEGER", autogenerate_json = False, copy_fn=None)
-libxl_devid = Builtin("devid", json_gen_fn = "yajl_gen_integer", json_parse_fn = "libxl__int_parse_json",
+libxl_devid = Builtin("devid", json_gen_fn = "yajl_gen_integer", jsonc_json_gen_fn = "libxl__int_gen_jso", json_parse_fn = "libxl__int_parse_json",
                       json_parse_type = "JSON_INTEGER", autogenerate_json = False, signed = True, init_val="-1",
                       copy_fn=None)
 libxl_uuid = Builtin("uuid", json_parse_type="JSON_STRING", passby=PASS_BY_REFERENCE, check_default_fn="libxl_uuid_is_nil",
@@ -37,7 +37,8 @@ libxl_ms_vm_genid = Builtin("ms_vm_genid", passby=PASS_BY_REFERENCE, check_defau
 # Specific integer types
 #
 
-MemKB = UInt(64, init_val = "LIBXL_MEMKB_DEFAULT", json_gen_fn = "libxl__uint64_gen_json")
+MemKB = UInt(64, init_val = "LIBXL_MEMKB_DEFAULT",
+             json_gen_fn = "libxl__uint64_gen_json", jsonc_json_gen_fn = "libxl__uint64_gen_jso")
 
 #
 # Constants / Enumerations
diff --git a/tools/libs/light/libxl_types_internal.idl b/tools/libs/light/libxl_types_internal.idl
index 0425e9b6b0..ab4ee92870 100644
--- a/tools/libs/light/libxl_types_internal.idl
+++ b/tools/libs/light/libxl_types_internal.idl
@@ -1,7 +1,8 @@
 namespace("libxl__")
 hidden(True)
 
-libxl_domid = Builtin("domid", namespace="libxl_", json_gen_fn = "yajl_gen_integer",
+libxl_domid = Builtin("domid", namespace="libxl_",
+                      json_gen_fn = "yajl_gen_integer", jsonc_json_gen_fn = "libxl__uint64_gen_jso",
 		      json_parse_fn = "libxl__uint32_parse_json", json_parse_type = "JSON_INTEGER",
 		      autogenerate_json = False, copy_fn = None)
 
diff --git a/tools/xl/xl_info.c b/tools/xl/xl_info.c
index 3fbc0698b7..18cfd3c217 100644
--- a/tools/xl/xl_info.c
+++ b/tools/xl/xl_info.c
@@ -60,6 +60,48 @@ static int maybe_printf(const char *fmt, ...)
     return count;
 }
 
+
+#ifdef HAVE_LIBJSONC
+static int printf_info_one_json(json_object **jso_r, int domid,
+                                libxl_domain_config *d_config)
+{
+    json_object *jso = NULL;
+    json_object *jso_config = NULL;
+    enum json_tokener_error error;
+    char *s = NULL;
+    int r = EXIT_FAILURE;
+
+    s = libxl_domain_config_to_json(ctx, d_config);
+    jso_config = json_tokener_parse_verbose(s, &error);
+    if (!jso_config) {
+        fprintf(stderr, "fail to parse JSON from libxl_domain_config_to_json(): %s\n",
+                json_tokener_error_desc(error));
+        goto out;
+    }
+
+    jso = json_object_new_object();
+    if (domid != -1)
+        json_object_object_add(jso, "domid", json_object_new_int(domid));
+    else
+        json_object_object_add(jso, "domid", json_object_new_null());
+
+
+    json_object_object_add(jso, "config", jso_config);
+    jso_config = NULL;
+
+    *jso_r = jso;
+    jso = NULL;
+    r = EXIT_SUCCESS;
+
+out:
+    free(s);
+    json_object_put(jso);
+    json_object_put(jso_config);
+    return r;
+}
+
+#elif defined(HAVE_LIBYAJL)
+
 static yajl_gen_status printf_info_one_json(yajl_gen hand, int domid,
                                             libxl_domain_config *d_config)
 {
@@ -95,6 +137,7 @@ static yajl_gen_status printf_info_one_json(yajl_gen hand, int domid,
 out:
     return s;
 }
+#endif
 
 void printf_info(enum output_format output_format,
                  int domid,
@@ -103,6 +146,27 @@ void printf_info(enum output_format output_format,
     if (output_format == OUTPUT_FORMAT_SXP)
         return printf_info_sexp(domid, d_config, fh);
 
+#ifdef HAVE_LIBJSONC
+    int r;
+    const char *buf;
+    json_object *jso;
+
+    r = printf_info_one_json(&jso, domid, d_config);
+    if (r)
+        goto out;
+
+    buf = json_object_to_json_string_ext(jso, JSON_C_TO_STRING_PRETTY);
+    if (!buf)
+        goto out;
+
+    fputs(buf, fh);
+
+out:
+    json_object_put(jso);
+    flush_stream(fh);
+    return;
+
+#elif defined(HAVE_LIBYAJL)
     const char *buf;
     libxl_yajl_length len = 0;
     yajl_gen_status s;
@@ -132,6 +196,7 @@ void printf_info(enum output_format output_format,
                 "unable to format domain config as JSON (YAJL:%d)\n", s);
 
     flush_stream(fh);
+#endif
 }
 
 static void output_xeninfo(void)
@@ -475,11 +540,20 @@ static void list_domains_details(const libxl_dominfo *info, int nb_domain)
 
     int i, rc;
 
+    const char *buf;
+#ifdef HAVE_LIBJSONC
+    json_object *jso = NULL;
+#elif defined(HAVE_LIBYAJL)
     yajl_gen hand = NULL;
     yajl_gen_status s;
-    const char *buf;
     libxl_yajl_length yajl_len = 0;
+#endif
 
+#ifdef HAVE_LIBJSONC
+    if (default_output_format == OUTPUT_FORMAT_JSON) {
+        jso = json_object_new_array();
+    }
+#elif defined(HAVE_LIBYAJL)
     if (default_output_format == OUTPUT_FORMAT_JSON) {
         hand = libxl_yajl_gen_alloc(NULL);
         if (!hand) {
@@ -492,6 +566,7 @@ static void list_domains_details(const libxl_dominfo *info, int nb_domain)
             goto out;
     } else
         s = yajl_gen_status_ok;
+#endif
 
     for (i = 0; i < nb_domain; i++) {
         libxl_domain_config_init(&d_config);
@@ -499,16 +574,32 @@ static void list_domains_details(const libxl_dominfo *info, int nb_domain)
                                                  &d_config, NULL);
         if (rc)
             continue;
-        if (default_output_format == OUTPUT_FORMAT_JSON)
+        if (default_output_format == OUTPUT_FORMAT_JSON) {
+#ifdef HAVE_LIBJSONC
+            json_object *jso_value;
+            rc = printf_info_one_json(&jso_value, info[i].domid, &d_config);
+            json_object_array_add(jso, jso_value);
+#elif defined(HAVE_LIBYAJL)
             s = printf_info_one_json(hand, info[i].domid, &d_config);
-        else
+#endif
+        } else
             printf_info_sexp(info[i].domid, &d_config, stdout);
         libxl_domain_config_dispose(&d_config);
+#ifdef HAVE_LIBJSONC
+        if (rc)
+            goto out;
+#elif defined(HAVE_LIBYAJL)
         if (s != yajl_gen_status_ok)
             goto out;
+#endif
     }
 
     if (default_output_format == OUTPUT_FORMAT_JSON) {
+#ifdef HAVE_LIBJSONC
+        buf = json_object_to_json_string_ext(jso, JSON_C_TO_STRING_PRETTY);
+        if (!buf)
+            goto out;
+#elif defined(HAVE_LIBYAJL)
         s = yajl_gen_array_close(hand);
         if (s != yajl_gen_status_ok)
             goto out;
@@ -516,16 +607,21 @@ static void list_domains_details(const libxl_dominfo *info, int nb_domain)
         s = yajl_gen_get_buf(hand, (const unsigned char **)&buf, &yajl_len);
         if (s != yajl_gen_status_ok)
             goto out;
+#endif
 
         puts(buf);
     }
 
 out:
     if (default_output_format == OUTPUT_FORMAT_JSON) {
+#ifdef HAVE_LIBJSONC
+        json_object_put(jso);
+#elif defined(HAVE_LIBYAJL)
         yajl_gen_free(hand);
         if (s != yajl_gen_status_ok)
             fprintf(stderr,
                     "unable to format domain config as JSON (YAJL:%d)\n", s);
+#endif
     }
 }
 
-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Juergen Gross 
Subject: [XEN PATCH 03/11] libxl: remove duplicated libxl__yajl_gen_asciiz() prototype
Date: Fri,  8 Aug 2025 16:55:54 +0200
Message-Id: <20250808145602.41716-4-anthony@xenproject.org>
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From: Anthony PERARD 

Signed-off-by: Anthony PERARD 
---
 tools/libs/light/libxl_internal.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/tools/libs/light/libxl_internal.h b/tools/libs/light/libxl_internal.h
index 2a5b233caa..4b6587a27a 100644
--- a/tools/libs/light/libxl_internal.h
+++ b/tools/libs/light/libxl_internal.h
@@ -1993,8 +1993,6 @@ _hidden char *libxl__cpupoolid_to_name(libxl__gc *gc, uint32_t poolid);
 _hidden int libxl__enum_from_string(const libxl_enum_string_table *t,
                                     const char *s, int *e) NN(2);
 
-_hidden yajl_gen_status libxl__yajl_gen_asciiz(yajl_gen hand, const char *str);
-
 _hidden yajl_gen_status libxl__string_gen_json(yajl_gen hand, const char *p);
 
 typedef yajl_gen_status (*libxl__gen_json_callback)(yajl_gen hand, void *);
-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Juergen Gross 
Subject: [XEN PATCH 09/11] tools/libxenstat: Use json-c when available
Date: Fri,  8 Aug 2025 16:56:00 +0200
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From: Anthony PERARD 

This is mainly a copy of the existing code in yajl and use json-c
instead.

Signed-off-by: Anthony PERARD 
---
 tools/libs/stat/Makefile      |   3 +-
 tools/libs/stat/xenstat_qmp.c | 126 ++++++++++++++++++++++++++++++++--
 2 files changed, 121 insertions(+), 8 deletions(-)

diff --git a/tools/libs/stat/Makefile b/tools/libs/stat/Makefile
index a968eaff48..3f13cf07be 100644
--- a/tools/libs/stat/Makefile
+++ b/tools/libs/stat/Makefile
@@ -24,7 +24,8 @@ OBJS-$(CONFIG_SunOS) += xenstat_solaris.o
 OBJS-$(CONFIG_NetBSD) += xenstat_netbsd.o
 OBJS-$(CONFIG_FreeBSD) += xenstat_freebsd.o
 
-LDLIBS-y += -lyajl
+LDLIBS-y += $(YAJL_LIBS)
+LDLIBS-y += $(LIBJSONC_LIBS)
 LDLIBS-$(CONFIG_SunOS) += -lkstat
 LDLIBS += $(LDLIBS-y)
 
diff --git a/tools/libs/stat/xenstat_qmp.c b/tools/libs/stat/xenstat_qmp.c
index 9909b9727e..21e321fffa 100644
--- a/tools/libs/stat/xenstat_qmp.c
+++ b/tools/libs/stat/xenstat_qmp.c
@@ -24,6 +24,10 @@
 
 #include "xenstat_priv.h"
 
+#ifdef HAVE_LIBJSONC
+#include 
+
+#elif defined(HAVE_LIBYAJL)
 #ifdef HAVE_YAJL_YAJL_VERSION_H
 #  include 
 #endif
@@ -32,11 +36,13 @@
 #if defined(YAJL_MAJOR) && (YAJL_MAJOR > 1)
 #  define HAVE_YAJL_V2 1
 #endif
+#endif
 
 #ifdef HAVE_YAJL_V2
-
 #include 
+#endif
 
+#if defined(HAVE_LIBJSONC) || defined(HAVE_YAJL_V2)
 static unsigned char *qmp_query(int, const char *);
 
 enum query_blockstats {
@@ -76,9 +82,10 @@ enum query_block {
             "type": 'str'
           }]}
 */
-static char *qmp_get_block_image(xenstat_node *node, char *qmp_devname, int qfd)
+static char *qmp_get_block_image(xenstat_node *node, const char *qmp_devname, int qfd)
 {
-	char *tmp, *file = NULL;
+	const char *tmp;
+	char *file = NULL;
 	const char *query_block_cmd = "{ \"execute\": \"query-block\" }";
 	static const char *const qblock[] = {
 		[ QMP_BLOCK_RETURN  ] = "return",
@@ -88,13 +95,56 @@ static char *qmp_get_block_image(xenstat_node *node, char *qmp_devname, int qfd)
 	};
 	const char *ptr[] = {0, 0};
 	unsigned char *qmp_stats;
-	yajl_val info, ret_obj, dev_obj, n;
 	int i;
 
 	if ((qmp_stats = qmp_query(qfd, query_block_cmd)) == NULL)
 		return NULL;
 
+#ifdef HAVE_LIBJSONC
+	json_object *jso;
+	enum json_tokener_error error;
+	jso = json_tokener_parse_verbose((const char *)qmp_stats, &error);
+	free(qmp_stats);
+	if (jso == NULL)
+		return NULL;
+
+	ptr[0] = qblock[QMP_BLOCK_RETURN]; /* "return" */
+	json_object *ret_jso = json_object_object_get(jso, ptr[0]);
+	if (ret_jso == NULL)
+		goto done;
+
+	for (i=0; i
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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Juergen Gross 
Subject: [XEN PATCH 08/11] libxl: convert libxl__json_object_to_json() to json_object
Date: Fri,  8 Aug 2025 16:55:59 +0200
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From: Anthony PERARD 

But keep the implementation done for YAJL.

Signed-off-by: Anthony PERARD 
---
 tools/libs/light/libxl_json.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/tools/libs/light/libxl_json.c b/tools/libs/light/libxl_json.c
index 01944ef94d..cffda158d2 100644
--- a/tools/libs/light/libxl_json.c
+++ b/tools/libs/light/libxl_json.c
@@ -104,10 +104,12 @@ typedef struct libxl__yajl_ctx {
  * YAJL Helper
  */
 
+#ifdef HAVE_LIBYAJL
 yajl_gen_status libxl__yajl_gen_asciiz(yajl_gen hand, const char *str)
 {
     return yajl_gen_string(hand, (const unsigned char *)str, strlen(str));
 }
+#endif
 
 #ifdef HAVE_LIBJSONC
 int libxl__enum_gen_jso(json_object **jso_r, const char *str)
@@ -1522,6 +1524,29 @@ char *libxl__object_to_json(libxl_ctx *ctx, const char *type,
 char *libxl__json_object_to_json(libxl__gc *gc,
                                  const libxl__json_object *args)
 {
+#ifdef HAVE_LIBJSONC
+    const char *buf;
+    json_object *root;
+    char *ret = NULL;
+    int rc;
+
+    if (!args)
+        return NULL;
+
+    rc = libxl__json_object_to_json_object(gc, &root, args);
+    if (rc)
+        goto out;
+
+    buf = json_object_to_json_string_ext(root, JSON_C_TO_STRING_PRETTY);
+    if (!buf)
+        goto out;
+
+    ret = libxl__strdup(gc, buf);
+
+out:
+    json_object_put(root);
+    return ret;
+#elif defined(HAVE_LIBYAJL)
     const unsigned char *buf;
     libxl_yajl_length len;
     yajl_gen_status s;
@@ -1549,6 +1574,7 @@ char *libxl__json_object_to_json(libxl__gc *gc,
 out:
     yajl_gen_free(hand);
     return ret;
+#endif
 }
 
 #ifdef HAVE_LIBJSONC
-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Juergen Gross 
Subject: [XEN PATCH 02/11] libxl: Remove duplicate libxl_domain_config_gen_json prototype
Date: Fri,  8 Aug 2025 16:55:53 +0200
Message-Id: <20250808145602.41716-3-anthony@xenproject.org>
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From: Anthony PERARD 

Since f9e681d3d1b8, the prototype of libxl_domain_config_gen_json is
generated from IDL in _libxl_types_json.h.

Fixes: f9e681d3d1b8 ("libxl: move definition of libxl_domain_config into the IDL")
Signed-off-by: Anthony PERARD 
---
 tools/include/libxl_json.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/tools/include/libxl_json.h b/tools/include/libxl_json.h
index 260783bfde..3f97267eae 100644
--- a/tools/include/libxl_json.h
+++ b/tools/include/libxl_json.h
@@ -90,7 +90,4 @@ static inline yajl_gen libxl_yajl_gen_alloc(const yajl_alloc_funcs *allocFuncs)
 
 #endif /* !HAVE_YAJL_V2 */
 
-yajl_gen_status libxl_domain_config_gen_json(yajl_gen hand,
-                                             libxl_domain_config *p);
-
 #endif /* LIBXL_JSON_H */
-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD 
Subject: [XEN PATCH 10/11] configure: Use json-c by default, fallback to yajl
Date: Fri,  8 Aug 2025 16:56:01 +0200
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From: Anthony PERARD 

Signed-off-by: Anthony PERARD 
---
 tools/configure    | 97 +++++++++++++++++++++++++++++-----------------
 tools/configure.ac | 12 +++---
 2 files changed, 69 insertions(+), 40 deletions(-)

diff --git a/tools/configure b/tools/configure
index edd1701b2d..0eb7a0ab6a 100755
--- a/tools/configure
+++ b/tools/configure
@@ -9692,41 +9692,7 @@ fi
 	# Put the nasty error message in config.log where it belongs
 	echo "$libjsonc_PKG_ERRORS" >&5
 
-	as_fn_error $? "Package requirements (json-c) were not met:
-
-$libjsonc_PKG_ERRORS
-
-Consider adjusting the PKG_CONFIG_PATH environment variable if you
-installed software in a non-standard prefix.
-
-Alternatively, you may set the environment variables libjsonc_CFLAGS
-and libjsonc_LIBS to avoid the need to call pkg-config.
-See the pkg-config man page for more details." "$LINENO" 5
-elif test $pkg_failed = untried; then
-     	{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5
-printf "%s\n" "no" >&6; }
-	{ { printf "%s\n" "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
-printf "%s\n" "$as_me: error: in \`$ac_pwd':" >&2;}
-as_fn_error $? "The pkg-config script could not be found or is too old.  Make sure it
-is in your PATH or set the PKG_CONFIG environment variable to the full
-path to pkg-config.
-
-Alternatively, you may set the environment variables libjsonc_CFLAGS
-and libjsonc_LIBS to avoid the need to call pkg-config.
-See the pkg-config man page for more details.
-
-To get pkg-config, see .
-See \`config.log' for more details" "$LINENO" 5; }
-else
-	libjsonc_CFLAGS=$pkg_cv_libjsonc_CFLAGS
-	libjsonc_LIBS=$pkg_cv_libjsonc_LIBS
-        { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: yes" >&5
-printf "%s\n" "yes" >&6; }
-
-printf "%s\n" "#define HAVE_LIBJSONC 1" >>confdefs.h
-
-fi
-{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for yajl_alloc in -lyajl" >&5
+	{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for yajl_alloc in -lyajl" >&5
 printf %s "checking for yajl_alloc in -lyajl... " >&6; }
 if test ${ac_cv_lib_yajl_yajl_alloc+y}
 then :
@@ -9772,6 +9738,67 @@ else $as_nop
   as_fn_error $? "Could not find yajl" "$LINENO" 5
 fi
 
+
+elif test $pkg_failed = untried; then
+     	{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: no" >&5
+printf "%s\n" "no" >&6; }
+	{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for yajl_alloc in -lyajl" >&5
+printf %s "checking for yajl_alloc in -lyajl... " >&6; }
+if test ${ac_cv_lib_yajl_yajl_alloc+y}
+then :
+  printf %s "(cached) " >&6
+else $as_nop
+  ac_check_lib_save_LIBS=$LIBS
+LIBS="-lyajl  $LIBS"
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+/* Override any GCC internal prototype to avoid an error.
+   Use char because int might match the return type of a GCC
+   builtin and then its argument prototype would still apply.  */
+char yajl_alloc ();
+int
+main (void)
+{
+return yajl_alloc ();
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"
+then :
+  ac_cv_lib_yajl_yajl_alloc=yes
+else $as_nop
+  ac_cv_lib_yajl_yajl_alloc=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.beam \
+    conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+{ printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_yajl_yajl_alloc" >&5
+printf "%s\n" "$ac_cv_lib_yajl_yajl_alloc" >&6; }
+if test "x$ac_cv_lib_yajl_yajl_alloc" = xyes
+then :
+  YAJL_LIBS=-lyajl
+
+
+printf "%s\n" "#define HAVE_LIBYAJL 1" >>confdefs.h
+
+else $as_nop
+  as_fn_error $? "Could not find yajl" "$LINENO" 5
+fi
+
+
+else
+	libjsonc_CFLAGS=$pkg_cv_libjsonc_CFLAGS
+	libjsonc_LIBS=$pkg_cv_libjsonc_LIBS
+        { printf "%s\n" "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+printf "%s\n" "yes" >&6; }
+
+printf "%s\n" "#define HAVE_LIBJSONC 1" >>confdefs.h
+
+fi
+
 { printf "%s\n" "$as_me:${as_lineno-$LINENO}: checking for deflateCopy in -lz" >&5
 printf %s "checking for deflateCopy in -lz... " >&6; }
 if test ${ac_cv_lib_z_deflateCopy+y}
diff --git a/tools/configure.ac b/tools/configure.ac
index bb40b5b3f0..7267d02a04 100644
--- a/tools/configure.ac
+++ b/tools/configure.ac
@@ -425,11 +425,13 @@ AC_SUBST([ZLIB_LIBS])
 AX_CHECK_EXTFS
 AX_CHECK_PTHREAD
 PKG_CHECK_MODULES([libjsonc], [json-c],
-    [AC_DEFINE([HAVE_LIBJSONC], [1], [Use library json-c])])
-AC_CHECK_LIB([yajl], [yajl_alloc],
-   [AC_SUBST([YAJL_LIBS],[-lyajl])
-    AC_DEFINE([HAVE_LIBYAJL],[1],[Define to 1 if you have the `yajl' library (-lyajl).])],
-    [AC_MSG_ERROR([Could not find yajl])])
+    [AC_DEFINE([HAVE_LIBJSONC], [1], [Use library json-c])],
+    [AC_CHECK_LIB([yajl], [yajl_alloc],
+        [AC_SUBST([YAJL_LIBS],[-lyajl])
+         AC_DEFINE([HAVE_LIBYAJL],[1],[Define to 1 if you have the `yajl' library (-lyajl).])],
+        [AC_MSG_ERROR([Could not find yajl])])
+])
+
 AC_CHECK_LIB([z], [deflateCopy], [], [AC_MSG_ERROR([Could not find zlib])])
 AC_CHECK_HEADER([argp.h], [
 AC_CHECK_LIB([argp], [argp_usage], [argp_ldflags="-largp"])
-- 
Anthony PERARD



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From: Anthony PERARD 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
	Oleksii Kurochko ,
	Community Manager ,
	Andrew Cooper ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini 
Subject: [XEN PATCH 11/11] Update CHANGELOG and README with dependency on json-c
Date: Fri,  8 Aug 2025 16:56:02 +0200
Message-Id: <20250808145602.41716-12-anthony@xenproject.org>
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From: Anthony PERARD 

Signed-off-by: Anthony PERARD 
---
 CHANGELOG.md | 2 ++
 README       | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe..83195e2dae 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - For x86, GCC 5.1 and Binutils 2.25, or Clang/LLVM 11
    - For ARM32 and ARM64, GCC 5.1 and Binutils 2.25
  - Linux based device model stubdomains are now fully supported.
+ - New dependency on library json-c, the toolstack will prefer it to `YAJL`
+   when available.
 
  - On x86:
    - Restrict the cache flushing done as a result of guest physical memory map
diff --git a/README b/README
index 6ee58f7b35..9329f30e13 100644
--- a/README
+++ b/README
@@ -53,7 +53,7 @@ provided by your OS distributor:
     * Development install of Python 2.7 or later (e.g., python-dev)
     * Development install of curses (e.g., libncurses-dev)
     * Development install of uuid (e.g. uuid-dev)
-    * Development install of yajl (e.g. libyajl-dev)
+    * Development install of json-c (e.g. libjson-c-dev) or yajl (e.g. libyajl-dev)
     * Development install of libaio (e.g. libaio-dev) version 0.3.107 or
       greater.
     * Development install of GLib v2.0 (e.g. libglib2.0-dev)
-- 
Anthony PERARD



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Subject: Re: [XEN PATCH 00/11] Allow to build libxl and other tools with
 json-c instead of yajl
To: Anthony PERARD , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Juergen Gross , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Jan Beulich ,
 Community Manager ,
 Stefano Stabellini , Julien Grall ,
 Michal Orzel ,
 Oleksii Kurochko 
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On 08/08/2025 3:55 pm, Anthony PERARD wrote:
> From: Anthony PERARD 
>
> Patch series available in this git branch:
> https://xenbits.xenproject.org/git-http/people/aperard/xen-unstable.git br.libxl-libjsonc-v1
>
> Hi,
>
> The library YAJL has been unmaintained for several years, without an obvious
> fork to pick.
>
> On the other and the library json-c is been maintained and use by several other
> project, it's probably already installed on your machine. So this patch series
> intend to allow to build the Xen toolstack again json-c, and forgo yajl.
>
> Just in case, YAJL is can still be used.
>
> There's bit of libxl API that exposes YAJL, mainly so it can be used by `xl` to
> call libxl_domain_config_gen_json(). It was exposed via the "libxl_json.h"
> headers. This functions and others won't be available when libxl is build
> against json-c.
>
> Cheers,
>
> Anthony PERARD (11):
>   xl: move printf_info prototype to an header
>   libxl: Remove duplicate libxl_domain_config_gen_json prototype
>   libxl: remove duplicated libxl__yajl_gen_asciiz() prototype

First three, trivially Acked-by: Andrew Cooper 

I'll look at the rest when I've got a bit more time.


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Subject: Re: Fork or replace dependency yajl?
From: Andrew Cooper 
To: =?UTF-8?Q?Christoph_Gr=C3=BCninger?= ,
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Cc: Anthony PERARD ,
 Juergen Gross 
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On 03/08/2025 2:36 pm, Andrew Cooper wrote:
> On 03/08/2025 9:52 am, Christoph Grüninger wrote:
>> Dear Xen developers,
>>
>> you are using the dependency yajl (yet another json library, [1]) to
>> parse JSON files. The project seems abandoned with the last commit 10
>> years ago, the last release over 11 years ago, and 75 open pull
>> requests. Packaging yajl requires patches, e.g., to make it compatible
>> with CMake 4.0.
>> There are some forks but none has replaced the old one yet [2].
>>
>> I think there are three paths forward:
>> 1. Xen could pick a prominent fork and use it as its main dependency.
>> 2. Xen could create a fork of its own, hopefully attracting more
>> people interested in an maintained successor of yajl.
>> 3. Switch to a different JSON parser library that remained healthy.
>>
>> Sure, you could stick to option 4., do nothing an offload the burden
>> to fix yajl to distribution packagers.
>>
>> Xen is an important project and its decision can create momentum that
>> might lead other projects.
>>
>> [1] https://github.com/lloyd/yajl
>> [2] https://github.com/lloyd/yajl/issues/252
> CCing the libxl maintainers.

To follow up here, please try
https://lore.kernel.org/xen-devel/20250808145602.41716-1-anthony@xenproject.org/T/#u
which should make libxl use json-c by preference.

~Andrew


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Date: Fri, 8 Aug 2025 16:28:45 +0100
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Subject: Re: [XEN PATCH] automation/eclair: restrict clean target to xen
To: Nicola Vetrini ,
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Cc: sstabellini@kernel.org, michal.orzel@amd.com, xenia.ragiadakou@amd.com,
 ayan.kumar.halder@amd.com, consulting@bugseng.com,
 Doug Goldstein 
References: 
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From: Andrew Cooper 
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On 07/08/2025 10:53 pm, Nicola Vetrini wrote:
> The clean target also clears files outside the xen directory,
> which is not needed for the purposes of running an analysis.
>
> No functional change.
>
> Reported-by: Andrew Cooper 
> Signed-off-by: Nicola Vetrini 

Acked-by: Andrew Cooper 


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Date: Fri, 8 Aug 2025 17:53:24 +0100
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Subject: Re: [PATCH v7 3/6] xen/arm: ffa: Introduce VM to VM support
To: Bertrand Marquis ,
 xen-devel@lists.xenproject.org
Cc: jens.wiklander@linaro.org, Volodymyr Babchuk
 , Stefano Stabellini ,
 Michal Orzel 
References: 
 <50224eb7cca4eaef2646ad8e33f689d912704733.1752754016.git.bertrand.marquis@arm.com>
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From: Julien Grall 
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Hi Bertrand,

On 17/07/2025 13:11, Bertrand Marquis wrote:
> Create a CONFIG_FFA_VM_TO_VM parameter to activate FFA communication
> between VMs.
> When activated list VMs in the system with FF-A support in part_info_get.
> 
> When VM to VM is activated, Xen will be tainted as Insecure and a
> message is displayed to the user during the boot as there is no
> filtering of VMs in FF-A so any VM can communicate or see any other VM
> in the system.
> 
> WARNING: There is no filtering for now and all VMs are listed !!
> 
> This patch is reorganizing the ffa_ctx structure to make clear which
> lock is protecting what parts.
> 
> This patch is introducing a chain list of the ffa_ctx with a FFA Version
> negociated allowing to create the partinfo results for VMs in parallel
> by using rwlock which only ensure addition/removal of entries are
> protected.
> 
> Signed-off-by: Bertrand Marquis 

With two remarks below:

Acked-by: Julien Grall 

> ---
> Changes in v7:
> - protect ffa_ctx list with a rw lock to allow several partinfo_get in
>    parallel but protect adding/removing entries.
> Changes in v6:
> - remove ACCESS_ONCE for guest_vers access and take the context lock
>    before modifying it
> - move guest_vers in context declaration to fields protected by the
>    context lock and add a comment to state that lock in only needed when
>    modifying it
> Changes in v5:
> - remove invalid comment about 1.1 firmware support
> - rename variables from d and dom to curr_d and dest_d (Julien)
> - add a TODO in the code for potential holding for long of the CPU
>    (Julien)
> - use an atomic global variable to store the number of VMs instead of
>    recomputing the value each time (Julien)
> - add partinfo information in ffa_ctx (id, cpus and 64bit) and create a
>    chain list of ctx. Use this chain list to create the partinfo result
>    without holding a global lock to prevent concurrency issues.
> - Move some changes in a preparation patch modifying partinfo for sps to
>    reduce this patch size and make the review easier
> Changes in v4:
> - properly handle SPMC version 1.0 header size case in partinfo_get
> - switch to local counting variables instead of *pointer += 1 form
> - coding style issue with missing spaces in if ()
> Changes in v3:
> - break partinfo_get in several sub functions to make the implementation
>    easier to understand and lock handling easier
> - rework implementation to check size along the way and prevent previous
>    implementation limits which had to check that the number of VMs or SPs
>    did not change
> - taint Xen as INSECURE when VM to VM is enabled
> Changes in v2:
> - Switch ifdef to IS_ENABLED
> - dom was not switched to d as requested by Jan because there is already
>    a variable d pointing to the current domain and it must not be
>    shadowed.
> ---
>   xen/arch/arm/tee/Kconfig        |  11 +++
>   xen/arch/arm/tee/ffa.c          |  47 +++++++++++++
>   xen/arch/arm/tee/ffa_partinfo.c | 100 ++++++++++++++++++++++++---
>   xen/arch/arm/tee/ffa_private.h  | 117 ++++++++++++++++++++++++++------
>   4 files changed, 245 insertions(+), 30 deletions(-)
> 
> diff --git a/xen/arch/arm/tee/Kconfig b/xen/arch/arm/tee/Kconfig
> index c5b0f88d7522..88a4c4c99154 100644
> --- a/xen/arch/arm/tee/Kconfig
> +++ b/xen/arch/arm/tee/Kconfig
> @@ -28,5 +28,16 @@ config FFA
>   
>   	  [1] https://developer.arm.com/documentation/den0077/latest
>   
> +config FFA_VM_TO_VM
> +    bool "Enable FF-A between VMs (UNSUPPORTED)" if UNSUPPORTED
> +    default n
> +    depends on FFA
> +    help
> +      This option enables to use FF-A between VMs.
> +      This is experimental and there is no access control so any
> +      guest can communicate with any other guest.
> +
> +      If unsure, say N.
> +
>   endmenu
>   
> diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c
> index 3bbdd7168a6b..be71eda4869f 100644
> --- a/xen/arch/arm/tee/ffa.c
> +++ b/xen/arch/arm/tee/ffa.c
> @@ -118,6 +118,13 @@ void *ffa_tx __read_mostly;
>   DEFINE_SPINLOCK(ffa_rx_buffer_lock);
>   DEFINE_SPINLOCK(ffa_tx_buffer_lock);
>   
> +struct list_head ffa_ctx_head;

A more common pattern is to use LIST_HEAD(ffa_ctx_head) and ...

> +/* RW Lock to protect addition/removal and reading in ffa_ctx_head */
> +rwlock_t ffa_ctx_list_rwlock;

... DEFINE_RWLOCK(ffa_ctx_list_rwlock) which will also initialize 
list/rwlock for you. So no need for extra code further down and less 
risk if the variables are used before they are initialized.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v7 5/6] xen/arm: ffa: Add indirect message between VM
Content-Language: en-GB
To: Bertrand Marquis ,
 xen-devel@lists.xenproject.org
Cc: jens.wiklander@linaro.org, Volodymyr Babchuk
 , Stefano Stabellini ,
 Michal Orzel 
References: 
 <1a5ef965eca870918a120221667e2f26c7604afc.1752754016.git.bertrand.marquis@arm.com>
From: Julien Grall 
In-Reply-To: <1a5ef965eca870918a120221667e2f26c7604afc.1752754016.git.bertrand.marquis@arm.com>
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Hi Bertrand,

On 17/07/2025 13:11, Bertrand Marquis wrote:
> Add support for indirect messages between VMs.
> This is only enabled if CONFIG_FFA_VM_TO_VM is selected.
> 
> Signed-off-by: Bertrand Marquis 
> Reviewed-by: Jens Wiklander 

Acked-by: Julien Grall 

Cheers,

-- 
Julien Grall



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To: =?utf-8?Q?Marek_Marczykowski-G=C3=B3recki?= 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, Doug Goldstein , Stefano Stabellini 
Subject: Re: [PATCH v2 1/3] CI: Add driver domains tests
Message-ID: 
In-Reply-To: <0243d946ec451ddf18a620dbcaaa45eba861810a.1754663560.git-series.marmarek@invisiblethingslab.com>
References:  <0243d946ec451ddf18a620dbcaaa45eba861810a.1754663560.git-series.marmarek@invisiblethingslab.com>
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On Fri, Aug 08, 2025 at 04:32:41PM +0200, Marek Marczykowski-G=C3=B3recki w=
rote:
> Setup a simple two domU system. One with network backend, running
> xendriverdomain service, and one with frontend, trying to ping the
> backend.
>=20
> Contrary to other similar tests, use disk image instead of initrd, to
> allow bigger rootfs without adding more RAM (for both dom0 and domU).
> But keep using pxelinux as a bootloader as it's easier to setup than
> installing grub on the disk. Theoretically, it could be started via direc=
t
> kernel boot in QEMU, but pxelinux is slightly closer to real-world
> deployment.
>=20
> Signed-off-by: Marek Marczykowski-G=C3=B3recki 

Reviewed-by: Denis Mukhin =20

> ---
> Changes in v2:
> - use heredoc
> - limit ping loop iterations
> - use full "backend" / "frontend" in disk image names
> - print domU consoles directly to /dev/console, to avoid systemd-added
>   messages prefix
> - terminate test on failure, don't wait for timeout
> ---
>  automation/gitlab-ci/test.yaml                  |   8 +-
>  automation/scripts/qemu-driverdomains-x86_64.sh | 130 +++++++++++++++++-
>  2 files changed, 138 insertions(+)
>  create mode 100755 automation/scripts/qemu-driverdomains-x86_64.sh
>=20
> diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.y=
aml
> index 1f0b27b2378a..5c4b2dc304b4 100644
> --- a/automation/gitlab-ci/test.yaml
> +++ b/automation/gitlab-ci/test.yaml
> @@ -656,6 +656,14 @@ qemu-alpine-x86_64-gcc:
>      - *x86-64-test-needs
>      - alpine-3.18-gcc
>=20
> +qemu-alpine-driverdomains-x86_64-gcc:
> +  extends: .qemu-x86-64
> +  script:
> +    - ./automation/scripts/qemu-driverdomains-x86_64.sh 2>&1 | tee ${LOG=
FILE}
> +  needs:
> +    - *x86-64-test-needs
> +    - alpine-3.18-gcc
> +
>  qemu-smoke-x86-64-gcc:
>    extends: .qemu-smoke-x86-64
>    script:
> diff --git a/automation/scripts/qemu-driverdomains-x86_64.sh b/automation=
/scripts/qemu-driverdomains-x86_64.sh
> new file mode 100755
> index 000000000000..a8e2ceb33527
> --- /dev/null
> +++ b/automation/scripts/qemu-driverdomains-x86_64.sh
> @@ -0,0 +1,130 @@
> +#!/bin/bash
> +
> +set -ex -o pipefail
> +
> +dom0_rootfs_extra_comp=3D()
> +dom0_rootfs_extra_uncomp=3D()
> +
> +cd binaries
> +
> +# DomU rootfs
> +
> +mkdir -p rootfs
> +cd rootfs
> +mkdir -p etc/local.d
> +passed=3D"ping test passed"
> +failed=3D"TEST FAILED"
> +cat > etc/local.d/xen.start << EOF
> +#!/bin/bash
> +
> +set -x
> +
> +if grep -q test=3Dbackend /proc/cmdline; then
> +    brctl addbr xenbr0
> +    ip link set xenbr0 up
> +    ip addr add 192.168.0.1/24 dev xenbr0
> +    bash /etc/init.d/xendriverdomain start
> +    # log backend-related logs to the console
> +    tail -F /var/log/xen/xldevd.log /var/log/xen/xen-hotplug.log >>/dev/=
console 2>/dev/null &
> +else
> +    ip link set eth0 up
> +    ip addr add 192.168.0.2/24 dev eth0
> +    timeout=3D6 # 6*10s
> +    until ping -c 10 192.168.0.1; do
> +        sleep 1
> +        if [ \$timeout -le 0 ]; then
> +            echo "${failed}"
> +            exit 1
> +        fi
> +        ((timeout--))
> +    done
> +    echo "${passed}"
> +fi
> +EOF
> +chmod +x etc/local.d/xen.start
> +zcat ../rootfs.cpio.gz | cpio -imd
> +zcat ../xen-tools.cpio.gz | cpio -imd
> +mkfs.ext4 -d . ../domU-rootfs.img 1024M
> +cd ..
> +rm -rf rootfs
> +
> +# Dom0 rootfs
> +mkdir -p rootfs
> +cd rootfs
> +zcat ../rootfs.cpio.gz | cpio -imd
> +zcat ../xen-tools.cpio.gz | cpio -imd
> +mkdir -p root etc/local.d
> +cat > root/backend.cfg << EOF
> +name=3D"backend"
> +memory=3D512
> +vcpus=3D1
> +kernel=3D"/root/bzImage"
> +extra=3D"console=3Dhvc0 root=3D/dev/xvda net.ifnames=3D0 test=3Dbackend"
> +disk=3D[ '/root/domU-rootfs-backend.img,raw,xvda,rw' ]
> +EOF
> +cat > root/frontend.cfg << EOF
> +name=3D"frontend"
> +memory=3D512
> +vcpus=3D1
> +kernel=3D"/root/bzImage"
> +extra=3D"console=3Dhvc0 root=3D/dev/xvda net.ifnames=3D0 test=3Dfrontend=
"
> +disk=3D[ '/root/domU-rootfs-frontend.img,raw,xvda,rw' ]
> +vif=3D[ 'bridge=3Dxenbr0,backend=3Dbackend' ]
> +EOF
> +
> +cat > etc/local.d/xen.start << EOF
> +#!/bin/bash
> +
> +set -x
> +
> +bash /etc/init.d/xencommons start
> +
> +xl list
> +
> +tail -F /var/log/xen/console/guest-backend.log 2>/dev/null | sed -e "s/^=
/(backend) /" >>/dev/console &
> +tail -F /var/log/xen/console/guest-frontend.log 2>/dev/null | sed -e "s/=
^/(frontend) /" >>/dev/console &
> +xl -vvv create /root/backend.cfg
> +xl -vvv create /root/frontend.cfg
> +EOF
> +chmod +x etc/local.d/xen.start
> +
> +cp ../domU-rootfs.img ./root/domU-rootfs-backend.img
> +cp ../domU-rootfs.img ./root/domU-rootfs-frontend.img
> +cp ../bzImage ./root/
> +mkdir -p etc/default
> +echo 'XENCONSOLED_TRACE=3Dall' >> etc/default/xencommons
> +mkdir -p var/log/xen/console
> +mkfs.ext4 -d . ../dom0-rootfs.img 2048M
> +cd ..
> +rm -rf rootfs
> +
> +cd ..
> +
> +cat >> binaries/pxelinux.0 << EOF
> +#!ipxe
> +
> +kernel xen console=3Dcom1 console_timestamps=3Dboot
> +module bzImage console=3Dhvc0 root=3D/dev/sda net.ifnames=3D0
> +boot
> +EOF
> +
> +# Run the test
> +rm -f smoke.serial
> +export TEST_CMD=3D"qemu-system-x86_64 \
> +    -cpu qemu64,+svm \
> +    -m 2G -smp 2 \
> +    -monitor none -serial stdio \
> +    -nographic \
> +    -device virtio-net-pci,netdev=3Dn0 \
> +    -netdev user,id=3Dn0,tftp=3Dbinaries,bootfile=3D/pxelinux.0 \
> +    -drive file=3Dbinaries/dom0-rootfs.img,format=3Draw"
> +
> +export TEST_LOG=3D"smoke.serial"
> +export BOOT_MSG=3D"Latest ChangeSet: "
> +export LOG_MSG=3D"Domain-0"
> +# exit early on test failure too, check if it was success below
> +export PASSED=3D"$passed|$failed"
> +
> +./automation/scripts/console.exp | sed 's/\r\+$//'
> +
> +grep "$passed" smoke.serial
> --
> git-series 0.9.1
>=20



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To: =?utf-8?Q?Marek_Marczykowski-G=C3=B3recki?= 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, Doug Goldstein , Stefano Stabellini 
Subject: Re: [PATCH v2 2/3] CI: Add configure --enable-systemd for full build
Message-ID: 
In-Reply-To: <526d26a85bd1f164dd8a421dfcc1e765c3ff5590.1754663560.git-series.marmarek@invisiblethingslab.com>
References:  <526d26a85bd1f164dd8a421dfcc1e765c3ff5590.1754663560.git-series.marmarek@invisiblethingslab.com>
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On Fri, Aug 08, 2025 at 04:32:42PM +0200, Marek Marczykowski-G=C3=B3recki w=
rote:
> This doesn't exclude sysvinit scripts, but allows testing systemd too.
>=20
> Signed-off-by: Marek Marczykowski-G=C3=B3recki 

Reviewed-by: Denis Mukhin =20

> --
> New in v2.
>=20
> Requires containers rebuild
> ---
>  automation/build/debian/12-x86_64.dockerfile | 1 +
>  automation/scripts/build                     | 3 +++
>  2 files changed, 4 insertions(+)
>=20
> diff --git a/automation/build/debian/12-x86_64.dockerfile b/automation/bu=
ild/debian/12-x86_64.dockerfile
> index e26a19079e38..3a53d92ddf6d 100644
> --- a/automation/build/debian/12-x86_64.dockerfile
> +++ b/automation/build/debian/12-x86_64.dockerfile
> @@ -24,6 +24,7 @@ RUN <          git-core
>          pkg-config
>          wget
> +        systemd
>          # libxenguest dombuilder
>          libbz2-dev
>          liblzma-dev
> diff --git a/automation/scripts/build b/automation/scripts/build
> index 0e7494ff6d87..4ad42889c78c 100755
> --- a/automation/scripts/build
> +++ b/automation/scripts/build
> @@ -69,6 +69,9 @@ else
>      # Full build.  Figure out our ./configure options
>      cfgargs=3D("--prefix=3D/usr")
>      cfgargs+=3D("--enable-docs")
> +    if pkg-config systemd; then
> +        cfgargs+=3D("--enable-systemd")
> +    fi
>=20
>      # booleans for which compiler is in use
>      cc_is_gcc=3D"$($cc --version | grep -q gcc && echo "y" || :)"
> --
> git-series 0.9.1
>=20



From xen-devel-bounces@lists.xenproject.org Fri Aug 08 17:04:34 2025
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Subject: Re: [PATCH v7 6/6] xen/arm: ffa: Enable VM to VM without firmware
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To: Bertrand Marquis ,
 xen-devel@lists.xenproject.org
Cc: jens.wiklander@linaro.org, Volodymyr Babchuk
 , Stefano Stabellini ,
 Michal Orzel 
References: 
 <9ed199ef3be4b6dc665f19f96ba4063c61ccbf00.1752754016.git.bertrand.marquis@arm.com>
From: Julien Grall 
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Hi Bertrand,

On 17/07/2025 13:11, Bertrand Marquis wrote:
> When VM to VM support is activated and there is no suitable FF-A support
> in the firmware, enable FF-A support for VMs to allow using it for VM to
> VM communications.
> If there is OP-TEE running in the secure world and using the non FF-A
> communication system, having CONFIG_FFA_VM_TO_VM could be non functional
> (if optee is probed first) or OP-TEE could be non functional (if FF-A is
> probed first) so it is not recommended to activate the configuration
> option for such systems.
> 
> To make buffer full notification work between VMs when there is no
> firmware, rework the notification handling and modify the global flag to
> only be used as check for firmware notification support instead.
> 
> Also split probe function into one for firmware and one for vm to vm to
> make the implementation clearer.
> 
> Signed-off-by: Bertrand Marquis 
> Reviewed-by: Jens Wiklander 

Acked-by: Julien Grall 

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v4 1/8] kconfig: turn PDX compression into a choice
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To: Roger Pau Monne , xen-devel@lists.xenproject.org
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich 
References: <20250805095257.74975-1-roger.pau@citrix.com>
 <20250805095257.74975-2-roger.pau@citrix.com>
From: Julien Grall 
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Hi Roger,

On 05/08/2025 10:52, Roger Pau Monne wrote:
> Rename the current CONFIG_PDX_COMPRESSION to CONFIG_PDX_MASK_COMPRESSION,
> and make it part of the PDX compression choice block, in preparation for
> adding further PDX compression algorithms.
> 
> The PDX compression defaults should still be the same for all
> architectures, however the choice block cannot be protected under EXPERT
> and still have a default choice being unconditionally selected.  As a
> result, the new "PDX (Page inDeX) compression" item will be unconditionally
> visible in Kconfig, even on architectures like x86 that previously had no
> way to enable PDX compression.
> 
> As part of this preparation work to introduce new PDX compressions, adjust
> some of the comments on pdx.h to note they apply to a specific PDX
> compression.  Also shuffle function prototypes and dummy implementations
> around to make it easier to introduce a new PDX compression.  Note all
> PDX compression implementations are expected to provide a
> pdx_is_region_compressible() that takes the same set of arguments.
> 
> Signed-off-by: Roger Pau Monné 
> Acked-by: Jan Beulich 

Acked-by: Julien Grall 

Cheers,

-- 
Julien Grall



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Date: Fri, 8 Aug 2025 18:21:29 +0100
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Subject: Re: [PATCH v4 2/8] pdx: provide a unified set of unit functions
Content-Language: en-GB
To: Roger Pau Monne , xen-devel@lists.xenproject.org
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich 
References: <20250805095257.74975-1-roger.pau@citrix.com>
 <20250805095257.74975-3-roger.pau@citrix.com>
From: Julien Grall 
In-Reply-To: <20250805095257.74975-3-roger.pau@citrix.com>
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Hi Roger,

On 05/08/2025 10:52, Roger Pau Monne wrote:
> diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
> index a77b31071ed8..ba35bf1fe3bb 100644
> --- a/xen/arch/arm/setup.c
> +++ b/xen/arch/arm/setup.c
> @@ -256,9 +256,11 @@ void __init init_pdx(void)
>   {
>       const struct membanks *mem = bootinfo_get_mem();
>       paddr_t bank_start, bank_size, bank_end, ram_end = 0;
> -    int bank;
> +    unsigned int bank;
>   
>   #ifndef CONFIG_PDX_NONE
> +    for ( bank = 0 ; bank < mem->nr_banks; bank++ )
> +        pfn_pdx_add_region(mem->bank[bank].start, mem->bank[bank].size);
>       /*
>        * Arm does not have any restrictions on the bits to compress. Pass 0 to
>        * let the common code further restrict the mask.
> @@ -266,26 +268,24 @@ void __init init_pdx(void)
>        * If the logic changes in pfn_pdx_hole_setup we might have to
>        * update this function too.
>        */
> -    uint64_t mask = pdx_init_mask(0x0);
> -
> -    for ( bank = 0 ; bank < mem->nr_banks; bank++ )
> -    {
> -        bank_start = mem->bank[bank].start;
> -        bank_size = mem->bank[bank].size;
> -
> -        mask |= bank_start | pdx_region_mask(bank_start, bank_size);
> -    }
> +    pfn_pdx_compression_setup(0);
>   
>       for ( bank = 0 ; bank < mem->nr_banks; bank++ )
>       {
> -        bank_start = mem->bank[bank].start;
> -        bank_size = mem->bank[bank].size;
> -
> -        if (~mask & pdx_region_mask(bank_start, bank_size))
> -            mask = 0;
> +        if ( !pdx_is_region_compressible(
> +                  mem->bank[bank].start,
> +                  PFN_UP(mem->bank[bank].start + mem->bank[bank].size) -
> +                  PFN_DOWN(mem->bank[bank].start)) )

This code is a bit too verbose. Can we at least introduce "bank = 
&mem->bank[bank]" to reduce a bit the verbosity?

The rest of the logic looks fine. So:

Acked-by: Julien Grall  # ARM

Cheers,

-- 
Julien Grall



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To: =?utf-8?Q?Marek_Marczykowski-G=C3=B3recki?= 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, Doug Goldstein , Stefano Stabellini 
Subject: Re: [PATCH v2 3/3] CI: Run driver domains test on Debian too
Message-ID: 
In-Reply-To: <3f4e22c2424e8b534fe743aad1e1ee4934f9444c.1754663560.git-series.marmarek@invisiblethingslab.com>
References:  <3f4e22c2424e8b534fe743aad1e1ee4934f9444c.1754663560.git-series.marmarek@invisiblethingslab.com>
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On Fri, Aug 08, 2025 at 04:32:43PM +0200, Marek Marczykowski-G=C3=B3recki w=
rote:
> The recent failure affected only glibc-based systems, so do the test on
> Debian too.
>=20
> Signed-off-by: Marek Marczykowski-G=C3=B3recki 

Just one tiny comment below, otherwise looks good to me!

With or without addressing it:

Reviewed-by: Denis Mukhin =20

> ---
> Changes in v2:
> - use systemd in Debian
>=20
> I once got the following timeout:
>=20
>     (backend) =3D=3D> /var/log/xen/xldevd.log <=3D=3D
>     (backend) libxl: error: libxl_aoutils.c:539:async_exec_timeout: killi=
ng execution of /etc/xen/scripts/vif-bridge online because of timeout
>=20
> https://gitlab.com/xen-project/people/marmarek/xen/-/jobs/10961394681
> (docker-bobcat runner)
>=20
> Could be related to having systemd in domU (and being on QEMU TCG, not
> even KVM). I never hit this case on Alpine nor Debian with OpenRC. If
> that will repeat, may need some adjustments - more CPUs in QEMU? limit
> to more powerful runners? setup KVM on the runners?
> ---
>  automation/gitlab-ci/test.yaml                  | 19 ++++++++++++++++++-
>  automation/scripts/qemu-driverdomains-x86_64.sh | 18 +++++++++++++++--
>  2 files changed, 35 insertions(+), 2 deletions(-)
>=20
> diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.y=
aml
> index 5c4b2dc304b4..a5ae03b0eee9 100644
> --- a/automation/gitlab-ci/test.yaml
> +++ b/automation/gitlab-ci/test.yaml
> @@ -30,6 +30,17 @@
>      job: microcode-x86
>      ref: master
>=20
> +.debian-x86-64-test-needs: &debian-x86-64-test-needs
> +  - project: xen-project/hardware/test-artifacts
> +    job: linux-6.6.56-x86_64
> +    ref: master
> +  - project: xen-project/hardware/test-artifacts
> +    job: debian-12-x86_64-rootfs
> +    ref: master
> +  - project: xen-project/hardware/test-artifacts
> +    job: microcode-x86
> +    ref: master
> +
>  .qemu-arm64:
>    extends: .test-jobs-common
>    variables:
> @@ -664,6 +675,14 @@ qemu-alpine-driverdomains-x86_64-gcc:
>      - *x86-64-test-needs
>      - alpine-3.18-gcc
>=20
> +qemu-debian-12-driverdomains-x86_64-gcc:
> +  extends: .qemu-x86-64
> +  script:
> +    - ./automation/scripts/qemu-driverdomains-x86_64.sh 2>&1 | tee ${LOG=
FILE}
> +  needs:
> +    - *debian-x86-64-test-needs
> +    - debian-12-x86_64-gcc-debug
> +
>  qemu-smoke-x86-64-gcc:
>    extends: .qemu-smoke-x86-64
>    script:
> diff --git a/automation/scripts/qemu-driverdomains-x86_64.sh b/automation=
/scripts/qemu-driverdomains-x86_64.sh
> index a8e2ceb33527..e5765ba5dbd6 100755
> --- a/automation/scripts/qemu-driverdomains-x86_64.sh
> +++ b/automation/scripts/qemu-driverdomains-x86_64.sh
> @@ -23,7 +23,11 @@ if grep -q test=3Dbackend /proc/cmdline; then
>      brctl addbr xenbr0
>      ip link set xenbr0 up
>      ip addr add 192.168.0.1/24 dev xenbr0
> -    bash /etc/init.d/xendriverdomain start
> +    if [ -d /run/systemd ]; then
> +        systemctl start xendriverdomain
> +    else
> +        bash /etc/init.d/xendriverdomain start
> +    fi
>      # log backend-related logs to the console
>      tail -F /var/log/xen/xldevd.log /var/log/xen/xen-hotplug.log >>/dev/=
console 2>/dev/null &
>  else
> @@ -77,7 +81,11 @@ cat > etc/local.d/xen.start << EOF
>=20
>  set -x
>=20
> -bash /etc/init.d/xencommons start
> +if [ -d /run/systemd ]; then
> +    systemctl start xen-init-dom0.service
> +else
> +    bash /etc/init.d/xencommons start
> +fi
>=20
>  xl list
>=20
> @@ -94,6 +102,12 @@ cp ../bzImage ./root/
>  mkdir -p etc/default
>  echo 'XENCONSOLED_TRACE=3Dall' >> etc/default/xencommons
>  mkdir -p var/log/xen/console
> +if [ -e etc/systemd/system.conf ]; then
> +    chroot . systemctl enable proc-xen.mount \
> +        xenstored.service \
> +        xenconsoled.service \
> +        xen-init-dom0.service

I would keep the list of files sorted; that may help with future merges, if
any.

> +fi
>  mkfs.ext4 -d . ../dom0-rootfs.img 2048M
>  cd ..
>  rm -rf rootfs
> --
> git-series 0.9.1
>=20



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Subject: Re: [PATCH v14 1/4] xen/domain: unify domain ID allocation
Content-Language: en-GB
To: dmkhn@proton.me, xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com,
 michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
 dmukhin@ford.com
References: <20250808021938.669855-1-dmukhin@ford.com>
 <20250808021938.669855-2-dmukhin@ford.com>
From: Julien Grall 
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Hi Denis,

On 08/08/2025 03:19, dmkhn@proton.me wrote:
> From: Denis Mukhin 
> 
> Currently, there are two different domain ID allocation implementations:
> 
>    1) Sequential IDs allocation in dom0less Arm code based on max_init_domid;
> 
>    2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
>       max_init_domid (both Arm and x86).
> 
> The domain ID allocation covers dom0 or late hwdom, predefined domains,
> post-boot domains, excluding Xen system domains (domid >=
> DOMID_FIRST_RESERVED).
> 
> It makes sense to have a common helper code for such task across architectures
> (Arm and x86) and between dom0less / toolstack domU allocation.
> 
> Note, fixing dependency on max_init_domid is out of scope of this patch.
> 
> Wrap the domain ID allocation as an arch-independent function domid_alloc() in
> new common/domid.c based on the bitmap.
> 
> Allocation algorithm:
> - If an explicit domain ID is provided, verify its availability and use it if
>    ID is not used;
> - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1],
>    starting from the last used ID.
>    Implementation guarantees that two consecutive calls will never return the
>    same ID. ID#0 is reserved for the first boot domain (currently, dom0) and
>    excluded from the allocation range.
> 
> Remove is_free_domid() helper as it is not needed now.
> 
> No functional change intended.
> 
> Signed-off-by: Denis Mukhin 

Reviewed-by: Julien Grall 

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v14 3/4] tools/tests: introduce unit tests for domain ID
 allocator
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To: dmkhn@proton.me, xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com,
 michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
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References: <20250808021938.669855-1-dmukhin@ford.com>
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From: Julien Grall 
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Hi Denis,

On 08/08/2025 03:20, dmkhn@proton.me wrote:
> From: Denis Mukhin 
> 
> Introduce some basic infrastructure for doing domain ID allocation unit tests,
> and add a few tests that ensure correctness of the domain ID allocator.

I am quite happy to see more unit tests for Xen :).

> 
> Use  and xen/lib/find-next-bit.c in test hardness code.
> 
> Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.
> 
> Signed-off-by: Denis Mukhin 

With a couple of remarks below:

Acked-by: Julien Grall 

> ---
> Changes since v13:
> - reworked bitops integration
> - hooked xen/lib/find-next-bit.c
> - cleaned up harness.h code
> - made test to use more IDs
> ---
>   tools/include/xen-tools/bitops.h       | 10 +++
>   tools/tests/Makefile                   |  2 +-
>   tools/tests/domid/.gitignore           |  2 +
>   tools/tests/domid/Makefile             | 56 +++++++++++++++++
>   tools/tests/domid/harness.h            | 54 ++++++++++++++++
>   tools/tests/domid/include/xen/domain.h |  1 +
>   tools/tests/domid/test-domid.c         | 86 ++++++++++++++++++++++++++
>   xen/lib/find-next-bit.c                |  5 ++
>   8 files changed, 215 insertions(+), 1 deletion(-)
>   create mode 100644 tools/tests/domid/.gitignore
>   create mode 100644 tools/tests/domid/Makefile
>   create mode 100644 tools/tests/domid/harness.h
>   create mode 120000 tools/tests/domid/include/xen/domain.h
>   create mode 100644 tools/tests/domid/test-domid.c
> 
> diff --git a/tools/include/xen-tools/bitops.h b/tools/include/xen-tools/bitops.h
> index 681482f6759f..3b98fba6d74c 100644
> --- a/tools/include/xen-tools/bitops.h
> +++ b/tools/include/xen-tools/bitops.h
> @@ -12,6 +12,16 @@
>   #define BITS_PER_LONG 32
>   #endif
>   
> +#define ffsl(x)       __builtin_ffsl(x)
> +
> +#define BIT_WORD(nr)  ((nr) / BITS_PER_LONG)
> +
> +#define BITS_TO_LONGS(bits) \
> +    (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
> +
> +#define DECLARE_BITMAP(name, bits) \
> +    unsigned long name[BITS_TO_LONGS(bits)]
> +
>   #define BITMAP_ENTRY(_nr,_bmap) ((_bmap))[(_nr) / 8]
>   #define BITMAP_SHIFT(_nr) ((_nr) % 8)
>   
> diff --git a/tools/tests/Makefile b/tools/tests/Makefile
> index 36928676a666..ff1666425436 100644
> --- a/tools/tests/Makefile
> +++ b/tools/tests/Makefile
> @@ -1,7 +1,7 @@
>   XEN_ROOT = $(CURDIR)/../..
>   include $(XEN_ROOT)/tools/Rules.mk
>   
> -SUBDIRS-y :=
> +SUBDIRS-y := domid

I would prefer if we keep SUBDIRST-y := as it is and add a new line 
SUBDIRS-y +=. This is mostly to reduce the chance that someone will add 
a new directory "abc" and forgot to update the line containing "domid".

>   SUBDIRS-y += resource
>   SUBDIRS-$(CONFIG_X86) += cpu-policy
>   SUBDIRS-$(CONFIG_X86) += tsx
> diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignore
> new file mode 100644
> index 000000000000..70e306b3c074
> --- /dev/null
> +++ b/tools/tests/domid/.gitignore
> @@ -0,0 +1,2 @@
> +*.o
> +test-domid
> diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile
> new file mode 100644
> index 000000000000..d96ceca6d954
> --- /dev/null
> +++ b/tools/tests/domid/Makefile
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# Unit tests for domain ID allocator.
> +#
> +# Copyright 2025 Ford Motor Company
> +
> +XEN_ROOT=$(CURDIR)/../../..
> +include $(XEN_ROOT)/tools/Rules.mk
> +
> +TESTS := test-domid
> +
> +vpath domid.c $(XEN_ROOT)/xen/common/
> +vpath find-next-bit.c $(XEN_ROOT)/xen/lib/
> +
> +.PHONY: all
> +all: $(TESTS)
> +
> +.PHONY: run
> +run: $(TESTS)
> +	$(foreach t,$(TESTS),./$(t);)
> +
> +.PHONY: clean
> +clean:
> +	$(RM) -- *.o $(TESTS) $(DEPS_RM)
> +
> +.PHONY: distclean
> +distclean: clean
> +	$(RM) -- *~
> +
> +.PHONY: install
> +install: all
> +	$(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests
> +	$(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests
> +
> +.PHONY: uninstall
> +uninstall:
> +	$(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid
> +
> +CFLAGS += -D__XEN_TOOLS__
> +# find-next-bit.c
> +CFLAGS += '-DEXPORT_SYMBOL(x)=' \
> +          -Dfind_first_bit \
> +          -Dfind_first_zero_bit \
> +          -Dfind_next_bit \
> +          -Dfind_next_bit_le \
> +          -Dfind_next_zero_bit_le
> +CFLAGS += $(APPEND_CFLAGS)
> +CFLAGS += $(CFLAGS_xeninclude)
> +CFLAGS += -I./include/
> +
> +LDFLAGS += $(APPEND_LDFLAGS)
> +
> +test-domid: domid.o find-next-bit.o test-domid.o
> +	$(CC) $^ -o $@ $(LDFLAGS)
> +
> +-include $(DEPS_INCLUDE)
> diff --git a/tools/tests/domid/harness.h b/tools/tests/domid/harness.h
> new file mode 100644
> index 000000000000..b043519dcb35
> --- /dev/null
> +++ b/tools/tests/domid/harness.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Unit test harness for domain ID allocator.
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#ifndef _TEST_HARNESS_
> +#define _TEST_HARNESS_
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +typedef bool spinlock_t;
> +typedef uint16_t domid_t;
> +
> +extern domid_t domid_alloc(domid_t domid);
> +extern void domid_free(domid_t domid);
> +
> +extern unsigned long find_next_zero_bit(const unsigned long *addr,
> +                                        unsigned long size,
> +                                        unsigned long offset);
> +
> +#define __test_and_set_bit(nr, addr)    test_and_set_bit(nr, addr)
> +#define __test_and_clear_bit(nr, addr)  test_and_clear_bit(nr, addr)
> +#define __set_bit(nr, addr)             set_bit(nr, addr)
> +
> +#define BUG_ON(x)                       assert(!(x))
> +#define ASSERT(x)                       assert(x)
> +
> +#define DEFINE_SPINLOCK(l)              spinlock_t l
> +#define spin_lock(l)                    (*(l) = true)
> +#define spin_unlock(l)                  (*(l) = false)

NIT: For hardening purpose, I wonder whether we should also assert that 
"l" is "false" for spin_lock() and "true" for spin_unlock(). This would 
help catching any bug in the locking.

> +
> +#define printk                          printf
> +
> +#define DOMID_FIRST_RESERVED            (100)
> +#define DOMID_INVALID                   (101)
> +
> +#endif /* _TEST_HARNESS_ */
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/tools/tests/domid/include/xen/domain.h b/tools/tests/domid/include/xen/domain.h
> new file mode 120000
> index 000000000000..2eda9aed088e
> --- /dev/null
> +++ b/tools/tests/domid/include/xen/domain.h
> @@ -0,0 +1 @@
> +../../harness.h
> \ No newline at end of file
> diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-domid.c
> new file mode 100644
> index 000000000000..7b6fb5ee2a7b
> --- /dev/null
> +++ b/tools/tests/domid/test-domid.c
> @@ -0,0 +1,86 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Unit tests for domain ID allocator.
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#include "harness.h"
> +
> +#define verify(exp, fmt, args...) do { \
> +    if ( !(exp) ) \
> +        printf(fmt, ## args); \
> +    assert(exp); \
> +} while (0);
> +
> +/*
> + * Fail on the first error, since tests are dependent on each other.
> + */
> +int main(int argc, char **argv)
> +{
> +    domid_t expected, allocated;
> +
> +    /* Test ID#0 cannot be allocated twice. */

For future improvement, we could check that for any domid [0; 
DOMID_FIRST_RESERVED[, we can allocate domid_alloc().

This would also confirm that domid_alloc() *only* allocates *one* ID.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v14 3/4] tools/tests: introduce unit tests for domain ID
 allocator
Content-Language: en-GB
From: Julien Grall 
To: dmkhn@proton.me, xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com,
 michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
 dmukhin@ford.com
References: <20250808021938.669855-1-dmukhin@ford.com>
 <20250808021938.669855-4-dmukhin@ford.com>
 <230593d5-f3a2-4be8-973a-530c2debcb08@xen.org>
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On 08/08/2025 18:56, Julien Grall wrote:
> Hi Denis,
> 
> On 08/08/2025 03:20, dmkhn@proton.me wrote:
>> From: Denis Mukhin 
>>
>> Introduce some basic infrastructure for doing domain ID allocation 
>> unit tests,
>> and add a few tests that ensure correctness of the domain ID allocator.
> 
> I am quite happy to see more unit tests for Xen :).
> 
>>
>> Use  and xen/lib/find-next-bit.c in test hardness 
>> code.
>>
>> Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.
>>
>> Signed-off-by: Denis Mukhin 
> 
> With a couple of remarks below:
> 
> Acked-by: Julien Grall 

Actually, this should have been a Reviewed-by tag. Sorry.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v14 4/4] xen/domain: update create_dom0() messages
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To: dmkhn@proton.me, xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com,
 michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
 dmukhin@ford.com, Alejandro Vallejo 
References: <20250808021938.669855-1-dmukhin@ford.com>
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Hi Denis,

On 08/08/2025 03:20, dmkhn@proton.me wrote:
> From: Denis Mukhin 
> 
> Use %pd for domain identification in error/panic messages in create_dom0().
> 
> No functional change.
> 
> Signed-off-by: Denis Mukhin 
> Reviewed-by: Alejandro Vallejo 
> Acked-by: Jan Beulich 

Acked-by: Julien Grall 

Cheers,

-- 
Julien Grall



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On 07.08.2025 16:19, Jason Gunthorpe wrote:
> On Mon, Aug 04, 2025 at 03:42:34PM +0300, Leon Romanovsky wrote:
>> Changelog:
>> v1:
>>   * Added new DMA_ATTR_MMIO attribute to indicate
>>     PCI_P2PDMA_MAP_THRU_HOST_BRIDGE path.
>>   * Rewrote dma_map_* functions to use thus new attribute
>> v0: https://lore.kernel.org/all/cover.1750854543.git.leon@kernel.org/
>> ------------------------------------------------------------------------
>>
>> This series refactors the DMA mapping to use physical addresses
>> as the primary interface instead of page+offset parameters. This
>> change aligns the DMA API with the underlying hardware reality where
>> DMA operations work with physical addresses, not page structures.
> Lets elaborate this as Robin asked:
>
> This series refactors the DMA mapping API to provide a phys_addr_t
> based, and struct-page free, external API that can handle all the
> mapping cases we want in modern systems:
>
>   - struct page based cachable DRAM
>   - struct page MEMORY_DEVICE_PCI_P2PDMA PCI peer to peer non-cachable MMIO
>   - struct page-less PCI peer to peer non-cachable MMIO
>   - struct page-less "resource" MMIO
>
> Overall this gets much closer to Matthew's long term wish for
> struct-pageless IO to cachable DRAM. The remaining primary work would
> be in the mm side to allow kmap_local_pfn()/phys_to_virt() to work on
> phys_addr_t without a struct page.
>
> The general design is to remove struct page usage entirely from the
> DMA API inner layers. For flows that need to have a KVA for the
> physical address they can use kmap_local_pfn() or phys_to_virt(). This
> isolates the struct page requirements to MM code only. Long term all
> removals of struct page usage are supporting Matthew's memdesc
> project which seeks to substantially transform how struct page works.
>
> Instead make the DMA API internals work on phys_addr_t. Internally
> there are still dedicated 'page' and 'resource' flows, except they are
> now distinguished by a new DMA_ATTR_MMIO instead of by callchain. Both
> flows use the same phys_addr_t.
>
> When DMA_ATTR_MMIO is specified things work similar to the existing
> 'resource' flow. kmap_local_pfn(), phys_to_virt(), phys_to_page(),
> pfn_valid(), etc are never called on the phys_addr_t. This requires
> rejecting any configuration that would need swiotlb. CPU cache
> flushing is not required, and avoided, as ATTR_MMIO also indicates the
> address have no cachable mappings. This effectively removes any
> DMA API side requirement to have struct page when DMA_ATTR_MMIO is
> used.
>
> In the !DMA_ATTR_MMIO mode things work similarly to the 'page' flow,
> except on the common path of no cache flush, no swiotlb it never
> touches a struct page. When cache flushing or swiotlb copying
> kmap_local_pfn()/phys_to_virt() are used to get a KVA for CPU
> usage. This was already the case on the unmap side, now the map side
> is symmetric.
>
> Callers are adjusted to set DMA_ATTR_MMIO. Existing 'resource' users
> must set it. The existing struct page based MEMORY_DEVICE_PCI_P2PDMA
> path must also set it. This corrects some existing bugs where iommu
> mappings for P2P MMIO were improperly marked IOMMU_CACHE.
>
> Since ATTR_MMIO is made to work with all the existing DMA map entry
> points, particularly dma_iova_link(), this finally allows a way to use
> the new DMA API to map PCI P2P MMIO without creating struct page. The
> VFIO DMABUF series demonstrates how this works. This is intended to
> replace the incorrect driver use of dma_map_resource() on PCI BAR
> addresses.
>
> This series does the core code and modern flows. A followup series
> will give the same treatement to the legacy dma_ops implementation.

Thanks for the elaborate description, that's something that was missing 
in the previous attempt. I read again all the previous discussion and 
this explanation and there are still two things that imho needs more 
clarification.


First - basing the API on the phys_addr_t.

Page based API had the advantage that it was really hard to abuse it and 
call for something that is not 'a normal RAM'. I initially though that 
phys_addr_t based API will somehow simplify arch specific 
implementation, as some of them indeed rely on phys_addr_t internally, 
but I missed other things pointed by Robin. Do we have here any 
alternative?


Second - making dma_map_phys() a single API to handle all cases.

Do we really need such single function to handle all cases? To handle 
P2P case, the caller already must pass DMA_ATTR_MMIO, so it must somehow 
keep such information internally. Cannot it just call existing 
dma_map_resource(), so there will be clear distinction between these 2 
cases (DMA to RAM and P2P DMA)? Do we need additional check for 
DMA_ATTR_MMIO for every typical DMA user? I know that branching is 
cheap, but this will probably increase code size for most of the typical 
users for no reason.


Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 09/22] x86/traps: Move load_system_tables() into traps-setup.c
Date: Fri,  8 Aug 2025 21:23:01 +0100
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Switch it to Xen coding style and fix MISRA violations.  Make it static as
there are no external caller now.

Since commit a35816b5cae8 ("x86/traps: Introduce early_traps_init() and
simplify setup"), load_system_tables() is called later on the BSP, so the
SYS_STATE_early_boot check can be dropped from the safety BUG_ON().

Move the BUILD_BUG_ON() into build_assertions(), and introduce an
endof_field() helper to make the expression clearer.

Swap wrmsrl(MSR_ISST, ...) for wrmsrns().  No serialisation is needed at this
point.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/cpu/common.c         | 118 --------------------------
 xen/arch/x86/include/asm/system.h |   1 -
 xen/arch/x86/traps-setup.c        | 132 ++++++++++++++++++++++++++++++
 xen/include/xen/macros.h          |   2 +
 4 files changed, 134 insertions(+), 119 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index cdc41248d4e9..da05015578aa 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -843,124 +843,6 @@ void print_cpu_info(unsigned int cpu)
 
 static cpumask_t cpu_initialized;
 
-/*
- * Sets up system tables and descriptors.
- *
- * - Sets up TSS with stack pointers, including ISTs
- * - Inserts TSS selector into regular and compat GDTs
- * - Loads GDT, IDT, TR then null LDT
- * - Sets up IST references in the IDT
- */
-void load_system_tables(void)
-{
-	unsigned int i, cpu = smp_processor_id();
-	unsigned long stack_bottom = get_stack_bottom(),
-		stack_top = stack_bottom & ~(STACK_SIZE - 1);
-	/*
-	 * NB: define tss_page as a local variable because clang 3.5 doesn't
-	 * support using ARRAY_SIZE against per-cpu variables.
-	 */
-	struct tss_page *tss_page = &this_cpu(tss_page);
-	idt_entry_t *idt = this_cpu(idt);
-
-	/* The TSS may be live.	 Disuade any clever optimisations. */
-	volatile struct tss64 *tss = &tss_page->tss;
-	seg_desc_t *gdt =
-		this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY;
-
-	const struct desc_ptr gdtr = {
-		.base = (unsigned long)gdt,
-		.limit = LAST_RESERVED_GDT_BYTE,
-	};
-	const struct desc_ptr idtr = {
-		.base = (unsigned long)idt,
-		.limit = sizeof(bsp_idt) - 1,
-	};
-
-	/*
-	 * Set up the TSS.  Warning - may be live, and the NMI/#MC must remain
-	 * valid on every instruction boundary.  (Note: these are all
-	 * semantically ACCESS_ONCE() due to tss's volatile qualifier.)
-	 *
-	 * rsp0 refers to the primary stack.  #MC, NMI, #DB and #DF handlers
-	 * each get their own stacks.  No IO Bitmap.
-	 */
-	tss->rsp0 = stack_bottom;
-	tss->ist[IST_MCE - 1] = stack_top + (1 + IST_MCE) * PAGE_SIZE;
-	tss->ist[IST_NMI - 1] = stack_top + (1 + IST_NMI) * PAGE_SIZE;
-	tss->ist[IST_DB  - 1] = stack_top + (1 + IST_DB)  * PAGE_SIZE;
-	tss->ist[IST_DF  - 1] = stack_top + (1 + IST_DF)  * PAGE_SIZE;
-	tss->bitmap = IOBMP_INVALID_OFFSET;
-
-	/* All other stack pointers poisioned. */
-	for ( i = IST_MAX; i < ARRAY_SIZE(tss->ist); ++i )
-		tss->ist[i] = 0x8600111111111111ul;
-	tss->rsp1 = 0x8600111111111111ul;
-	tss->rsp2 = 0x8600111111111111ul;
-
-	/*
-	 * Set up the shadow stack IST.  Used entries must point at the
-	 * supervisor stack token.  Unused entries are poisoned.
-	 *
-	 * This IST Table may be live, and the NMI/#MC entries must
-	 * remain valid on every instruction boundary, hence the
-	 * volatile qualifier.
-	 */
-	if (cpu_has_xen_shstk) {
-		volatile uint64_t *ist_ssp = tss_page->ist_ssp;
-		unsigned long
-			mce_ssp = stack_top + (IST_MCE * IST_SHSTK_SIZE) - 8,
-			nmi_ssp = stack_top + (IST_NMI * IST_SHSTK_SIZE) - 8,
-			db_ssp  = stack_top + (IST_DB  * IST_SHSTK_SIZE) - 8,
-			df_ssp  = stack_top + (IST_DF  * IST_SHSTK_SIZE) - 8;
-
-		ist_ssp[0] = 0x8600111111111111ul;
-		ist_ssp[IST_MCE] = mce_ssp;
-		ist_ssp[IST_NMI] = nmi_ssp;
-		ist_ssp[IST_DB]	 = db_ssp;
-		ist_ssp[IST_DF]	 = df_ssp;
-		for ( i = IST_DF + 1; i < ARRAY_SIZE(tss_page->ist_ssp); ++i )
-			ist_ssp[i] = 0x8600111111111111ul;
-
-		if (IS_ENABLED(CONFIG_XEN_SHSTK) && rdssp() != SSP_NO_SHSTK) {
-			/*
-			 * Rewrite supervisor tokens when shadow stacks are
-			 * active.  This resets any busy bits left across S3.
-			 */
-			wrss(mce_ssp, _p(mce_ssp));
-			wrss(nmi_ssp, _p(nmi_ssp));
-			wrss(db_ssp,  _p(db_ssp));
-			wrss(df_ssp,  _p(df_ssp));
-		}
-
-		wrmsrl(MSR_ISST, (unsigned long)ist_ssp);
-	}
-
-	_set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
-			 sizeof(*tss) - 1, SYS_DESC_tss_avail);
-	if ( IS_ENABLED(CONFIG_PV32) )
-		_set_tssldt_desc(
-			this_cpu(compat_gdt) - FIRST_RESERVED_GDT_ENTRY + TSS_ENTRY,
-			(unsigned long)tss, sizeof(*tss) - 1, SYS_DESC_tss_busy);
-
-	per_cpu(full_gdt_loaded, cpu) = false;
-	lgdt(&gdtr);
-	lidt(&idtr);
-	ltr(TSS_SELECTOR);
-	lldt(0);
-
-	enable_each_ist(idt);
-
-	/*
-	 * Bottom-of-stack must be 16-byte aligned!
-	 *
-	 * Defer checks until exception support is sufficiently set up.
-	 */
-	BUILD_BUG_ON((sizeof(struct cpu_info) -
-		      sizeof(struct cpu_user_regs)) & 0xf);
-	BUG_ON(system_state != SYS_STATE_early_boot && (stack_bottom & 0xf));
-}
-
 static void skinit_enable_intr(void)
 {
 	uint64_t val;
diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
index 57446c5b465c..3cdc56e4ba6d 100644
--- a/xen/arch/x86/include/asm/system.h
+++ b/xen/arch/x86/include/asm/system.h
@@ -256,7 +256,6 @@ static inline int local_irq_is_enabled(void)
 #define BROKEN_ACPI_Sx          0x0001
 #define BROKEN_INIT_AFTER_S1    0x0002
 
-void load_system_tables(void);
 void subarch_percpu_traps_init(void);
 
 #endif
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index 8ca379c9e4cb..13b8fcf0ba51 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -7,6 +7,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -19,6 +20,124 @@ boolean_param("ler", opt_ler);
 
 void nocall entry_PF(void);
 
+/*
+ * Sets up system tables and descriptors for IDT devliery.
+ *
+ * - Sets up TSS with stack pointers, including ISTs
+ * - Inserts TSS selector into regular and compat GDTs
+ * - Loads GDT, IDT, TR then null LDT
+ * - Sets up IST references in the IDT
+ */
+static void load_system_tables(void)
+{
+    unsigned int i, cpu = smp_processor_id();
+    unsigned long stack_bottom = get_stack_bottom(),
+        stack_top = stack_bottom & ~(STACK_SIZE - 1);
+    /*
+     * NB: define tss_page as a local variable because clang 3.5 doesn't
+     * support using ARRAY_SIZE against per-cpu variables.
+     */
+    struct tss_page *tss_page = &this_cpu(tss_page);
+    idt_entry_t *idt = this_cpu(idt);
+
+    /* The TSS may be live.  Disuade any clever optimisations. */
+    volatile struct tss64 *tss = &tss_page->tss;
+    seg_desc_t *gdt =
+        this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY;
+
+    const struct desc_ptr gdtr = {
+        .base = (unsigned long)gdt,
+        .limit = LAST_RESERVED_GDT_BYTE,
+    };
+    const struct desc_ptr idtr = {
+        .base = (unsigned long)idt,
+        .limit = sizeof(bsp_idt) - 1,
+    };
+
+    /*
+     * Set up the TSS.  Warning - may be live, and the NMI/#MC must remain
+     * valid on every instruction boundary.  (Note: these are all
+     * semantically ACCESS_ONCE() due to tss's volatile qualifier.)
+     *
+     * rsp0 refers to the primary stack.  #MC, NMI, #DB and #DF handlers
+     * each get their own stacks.  No IO Bitmap.
+     */
+    tss->rsp0 = stack_bottom;
+    tss->ist[IST_MCE - 1] = stack_top + (1 + IST_MCE) * PAGE_SIZE;
+    tss->ist[IST_NMI - 1] = stack_top + (1 + IST_NMI) * PAGE_SIZE;
+    tss->ist[IST_DB  - 1] = stack_top + (1 + IST_DB)  * PAGE_SIZE;
+    tss->ist[IST_DF  - 1] = stack_top + (1 + IST_DF)  * PAGE_SIZE;
+    tss->bitmap = IOBMP_INVALID_OFFSET;
+
+    /* All other stack pointers poisioned. */
+    for ( i = IST_MAX; i < ARRAY_SIZE(tss->ist); ++i )
+        tss->ist[i] = 0x8600111111111111UL;
+    tss->rsp1 = 0x8600111111111111UL;
+    tss->rsp2 = 0x8600111111111111UL;
+
+    /*
+     * Set up the shadow stack IST.  Used entries must point at the
+     * supervisor stack token.  Unused entries are poisoned.
+     *
+     * This IST Table may be live, and the NMI/#MC entries must
+     * remain valid on every instruction boundary, hence the
+     * volatile qualifier.
+     */
+    if ( cpu_has_xen_shstk )
+    {
+        volatile uint64_t *ist_ssp = tss_page->ist_ssp;
+        unsigned long
+            mce_ssp = stack_top + (IST_MCE * IST_SHSTK_SIZE) - 8,
+            nmi_ssp = stack_top + (IST_NMI * IST_SHSTK_SIZE) - 8,
+            db_ssp  = stack_top + (IST_DB  * IST_SHSTK_SIZE) - 8,
+            df_ssp  = stack_top + (IST_DF  * IST_SHSTK_SIZE) - 8;
+
+        ist_ssp[0] = 0x8600111111111111UL;
+        ist_ssp[IST_MCE] = mce_ssp;
+        ist_ssp[IST_NMI] = nmi_ssp;
+        ist_ssp[IST_DB]  = db_ssp;
+        ist_ssp[IST_DF]  = df_ssp;
+        for ( i = IST_DF + 1; i < ARRAY_SIZE(tss_page->ist_ssp); ++i )
+            ist_ssp[i] = 0x8600111111111111UL;
+
+        if ( IS_ENABLED(CONFIG_XEN_SHSTK) && rdssp() != SSP_NO_SHSTK )
+        {
+            /*
+             * Rewrite supervisor tokens when shadow stacks are
+             * active.  This resets any busy bits left across S3.
+             */
+            wrss(mce_ssp, _p(mce_ssp));
+            wrss(nmi_ssp, _p(nmi_ssp));
+            wrss(db_ssp,  _p(db_ssp));
+            wrss(df_ssp,  _p(df_ssp));
+        }
+
+        wrmsrns(MSR_ISST, (unsigned long)ist_ssp);
+    }
+
+    _set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
+                     sizeof(*tss) - 1, SYS_DESC_tss_avail);
+    if ( IS_ENABLED(CONFIG_PV32) )
+        _set_tssldt_desc(
+            this_cpu(compat_gdt) - FIRST_RESERVED_GDT_ENTRY + TSS_ENTRY,
+            (unsigned long)tss, sizeof(*tss) - 1, SYS_DESC_tss_busy);
+
+    per_cpu(full_gdt_loaded, cpu) = false;
+    lgdt(&gdtr);
+    lidt(&idtr);
+    ltr(TSS_SELECTOR);
+    lldt(0);
+
+    enable_each_ist(idt);
+
+    /*
+     * tss->rsp0 must be 16-byte aligned.
+     *
+     * Defer checks until exception support is sufficiently set up.
+     */
+    BUG_ON(stack_bottom & 15);
+}
+
 static void __init init_ler(void)
 {
     unsigned int msr = 0;
@@ -139,3 +258,16 @@ void asmlinkage ap_early_traps_init(void)
 {
     load_system_tables();
 }
+
+static void __init __maybe_unused build_assertions(void)
+{
+    /*
+     * This is best-effort (it doesn't cover some padding corner cases), but
+     * is preforable to hitting the check at boot time.
+     *
+     * tss->rsp0, pointing at the end of cpu_info.guest_cpu_user_regs, must be
+     * 16-byte aligned.
+     */
+    BUILD_BUG_ON((sizeof(struct cpu_info) -
+                  endof_field(struct cpu_info, guest_cpu_user_regs)) & 15);
+}
diff --git a/xen/include/xen/macros.h b/xen/include/xen/macros.h
index cd528fbdb127..726ba221e0d8 100644
--- a/xen/include/xen/macros.h
+++ b/xen/include/xen/macros.h
@@ -102,6 +102,8 @@
  */
 #define sizeof_field(type, member) sizeof(((type *)NULL)->member)
 
+#define endof_field(type, member) (offsetof(type, member) + sizeof_field(type, member))
+
 /* Cast an arbitrary integer to a pointer. */
 #define _p(x) ((void *)(unsigned long)(x))
 
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 07/22] x86/spec-ctrl: Rework init_shadow_spec_ctrl_state() to take an info pointer
Date: Fri,  8 Aug 2025 21:22:59 +0100
Message-Id: <20250808202314.1045968-8-andrew.cooper3@citrix.com>
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We're going to want to reuse it for a remote stack shortly.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/spec_ctrl.h | 4 +---
 xen/arch/x86/setup.c                 | 2 +-
 xen/arch/x86/smpboot.c               | 2 +-
 xen/arch/x86/spec_ctrl.c             | 2 +-
 4 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/asm/spec_ctrl.h
index 6724d3812029..3d92928f9439 100644
--- a/xen/arch/x86/include/asm/spec_ctrl.h
+++ b/xen/arch/x86/include/asm/spec_ctrl.h
@@ -99,10 +99,8 @@ extern bool opt_bp_spec_reduce;
  */
 extern paddr_t l1tf_addr_mask, l1tf_safe_maddr;
 
-static inline void init_shadow_spec_ctrl_state(void)
+static inline void init_shadow_spec_ctrl_state(struct cpu_info *info)
 {
-    struct cpu_info *info = get_cpu_info();
-
     info->shadow_spec_ctrl = 0;
     info->xen_spec_ctrl = default_xen_spec_ctrl;
     info->scf = default_scf;
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index c8c408e02436..6fb42c5a5f95 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1126,7 +1126,7 @@ void asmlinkage __init noreturn __start_xen(void)
 
     /* Critical region without exception handling.  Any fault is deadly! */
 
-    init_shadow_spec_ctrl_state();
+    init_shadow_spec_ctrl_state(info);
 
     percpu_init_areas();
 
diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index 302be4341bf3..ce4862dde5a7 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -332,7 +332,7 @@ void asmlinkage start_secondary(void)
     set_current(idle_vcpu[cpu]);
     this_cpu(curr_vcpu) = idle_vcpu[cpu];
     rdmsrl(MSR_EFER, this_cpu(efer));
-    init_shadow_spec_ctrl_state();
+    init_shadow_spec_ctrl_state(info);
 
     /*
      * Just as during early bootstrap, it is convenient here to disable
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index feae0d710f8e..1ff3d6835d9d 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -2226,7 +2226,7 @@ void __init init_speculation_mitigations(void)
         opt_eager_fpu = should_use_eager_fpu();
 
     /* (Re)init BSP state now that default_scf has been calculated. */
-    init_shadow_spec_ctrl_state();
+    init_shadow_spec_ctrl_state(get_cpu_info());
 
     /*
      * For microcoded IBRS only (i.e. Intel, pre eIBRS), it is recommended to
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 08/22] x86/traps: Introduce ap_early_traps_init() and set up exception handling earlier
Date: Fri,  8 Aug 2025 21:23:00 +0100
Message-Id: <20250808202314.1045968-9-andrew.cooper3@citrix.com>
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As things stand, we set up AP/S3 exception handling marginally after the
fragile activity of setting up shadow stacks.  Shadow stack setup is going to
get more complicated under FRED.

Introduce ap_early_traps_init() and call it ahead of setting up shadow stacks.
To start with, call load_system_tables() which is sufficient to set up full
exception handling.

In order to handle exceptions, current and the speculation controls needs to
work.  cpu_smpboot_alloc() already constructs some of the AP's top-of-stack
block, so have it set up a little more.

This gets us complete exception coverage of setting up shadow stacks, rather
than dying with a triple fault.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/acpi/wakeup_prot.S |  5 +++--
 xen/arch/x86/boot/x86_64.S      |  5 ++++-
 xen/arch/x86/smpboot.c          | 17 ++++-------------
 xen/arch/x86/traps-setup.c      | 12 ++++++++++++
 4 files changed, 23 insertions(+), 16 deletions(-)

diff --git a/xen/arch/x86/acpi/wakeup_prot.S b/xen/arch/x86/acpi/wakeup_prot.S
index 92af6230b31f..60eca4010042 100644
--- a/xen/arch/x86/acpi/wakeup_prot.S
+++ b/xen/arch/x86/acpi/wakeup_prot.S
@@ -63,6 +63,9 @@ LABEL(s3_resume)
         pushq   %rax
         lretq
 1:
+        /* Set up early exceptions and CET before entering C properly. */
+        call    ap_early_traps_init
+
 #if defined(CONFIG_XEN_SHSTK) || defined(CONFIG_XEN_IBT)
         call    xen_msr_s_cet_value
         test    %eax, %eax
@@ -117,8 +120,6 @@ LABEL(s3_resume)
 .L_cet_done:
 #endif /* CONFIG_XEN_SHSTK || CONFIG_XEN_IBT */
 
-        call    load_system_tables
-
         /* Restore CR4 from the cpuinfo block. */
         GET_STACK_END(bx)
         mov     STACK_CPUINFO_FIELD(cr4)(%rbx), %rax
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 95a6b6cf63bd..0dfcc8a88a40 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -30,7 +30,10 @@ ENTRY(__high_start)
         test    %ebx,%ebx
         jz      .L_bsp
 
-        /* APs.  Set up CET before entering C properly. */
+        /* APs.  Set up early exceptions and CET before entering C properly. */
+
+        call    ap_early_traps_init
+
 #if defined(CONFIG_XEN_SHSTK) || defined(CONFIG_XEN_IBT)
         call    xen_msr_s_cet_value
         test    %eax, %eax
diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index ce4862dde5a7..8af6556999d7 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -327,12 +327,7 @@ void asmlinkage start_secondary(void)
     struct cpu_info *info = get_cpu_info();
     unsigned int cpu = smp_processor_id();
 
-    /* Critical region without IDT or TSS.  Any fault is deadly! */
-
-    set_current(idle_vcpu[cpu]);
-    this_cpu(curr_vcpu) = idle_vcpu[cpu];
     rdmsrl(MSR_EFER, this_cpu(efer));
-    init_shadow_spec_ctrl_state(info);
 
     /*
      * Just as during early bootstrap, it is convenient here to disable
@@ -352,14 +347,6 @@ void asmlinkage start_secondary(void)
      */
     spin_debug_disable();
 
-    get_cpu_info()->use_pv_cr3 = false;
-    get_cpu_info()->xen_cr3 = 0;
-    get_cpu_info()->pv_cr3 = 0;
-
-    load_system_tables();
-
-    /* Full exception support from here on in. */
-
     if ( cpu_has_pks )
         wrpkrs_and_cache(0); /* Must be before setting CR4.PKS */
 
@@ -1064,8 +1051,12 @@ static int cpu_smpboot_alloc(unsigned int cpu)
             goto out;
 
     info = get_cpu_info_from_stack((unsigned long)stack_base[cpu]);
+    memset(info, 0, sizeof(*info));
+    init_shadow_spec_ctrl_state(info);
     info->processor_id = cpu;
     info->per_cpu_offset = __per_cpu_offset[cpu];
+    info->current_vcpu = idle_vcpu[cpu];
+    per_cpu(curr_vcpu, cpu) = idle_vcpu[cpu];
 
     gdt = per_cpu(gdt, cpu) ?: alloc_xenheap_pages(0, memflags);
     if ( gdt == NULL )
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index 370f4d5f7b60..8ca379c9e4cb 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -127,3 +127,15 @@ void percpu_traps_init(void)
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
 }
+
+/*
+ * Configure exception handling on APs and S3.  Called before entering C
+ * properly, and before shadow stacks are activated.
+ *
+ * boot_gdt is currently loaded, and we must switch to our local GDT.  The
+ * local IDT has unknown IST-ness.
+ */
+void asmlinkage ap_early_traps_init(void)
+{
+    load_system_tables();
+}
-- 
2.39.5



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        Fri, 08 Aug 2025 13:23:21 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 02/22] x86/msr: Rename wrmsr_ns() to wrmsrns(), and take 64bit value
Date: Fri,  8 Aug 2025 21:22:54 +0100
Message-Id: <20250808202314.1045968-3-andrew.cooper3@citrix.com>
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In hindsight, having the wrapper name not be the instruction mnemonic was a
poor choice.  Also, PKS turns out to be quite rare in wanting a split value.

Switch to using a single 64bit value in preparation for new users.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/msr.h      | 4 ++--
 xen/arch/x86/include/asm/prot-key.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 4c4f18b3a54d..b6b85b04c3fd 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -39,7 +39,7 @@ static inline void wrmsrl(unsigned int msr, uint64_t val)
 }
 
 /* Non-serialising WRMSR, when available.  Falls back to a serialising WRMSR. */
-static inline void wrmsr_ns(uint32_t msr, uint32_t lo, uint32_t hi)
+static inline void wrmsrns(uint32_t msr, uint64_t val)
 {
     /*
      * WRMSR is 2 bytes.  WRMSRNS is 3 bytes.  Pad WRMSR with a redundant CS
@@ -47,7 +47,7 @@ static inline void wrmsr_ns(uint32_t msr, uint32_t lo, uint32_t hi)
      */
     alternative_input(".byte 0x2e; wrmsr",
                       ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
-                      "c" (msr), "a" (lo), "d" (hi));
+                      "c" (msr), "a" (val), "d" (val >> 32));
 }
 
 /* rdmsr with exception handling */
diff --git a/xen/arch/x86/include/asm/prot-key.h b/xen/arch/x86/include/asm/prot-key.h
index 0cbecc2df401..3e9c2eaef415 100644
--- a/xen/arch/x86/include/asm/prot-key.h
+++ b/xen/arch/x86/include/asm/prot-key.h
@@ -72,14 +72,14 @@ static inline void wrpkrs(uint32_t pkrs)
     {
         *this_pkrs = pkrs;
 
-        wrmsr_ns(MSR_PKRS, pkrs, 0);
+        wrmsrns(MSR_PKRS, pkrs);
     }
 }
 
 static inline void wrpkrs_and_cache(uint32_t pkrs)
 {
     this_cpu(pkrs) = pkrs;
-    wrmsr_ns(MSR_PKRS, pkrs, 0);
+    wrmsrns(MSR_PKRS, pkrs);
 }
 
 #endif /* ASM_PROT_KEY_H */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 12/22] x86/traps: Unexport show_code() and show_stack_overflow()
Date: Fri,  8 Aug 2025 21:23:04 +0100
Message-Id: <20250808202314.1045968-13-andrew.cooper3@citrix.com>
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These can become static now the two traps.c have been merged.

No fucntional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/processor.h | 2 --
 xen/arch/x86/traps.c                 | 4 ++--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/include/asm/processor.h b/xen/arch/x86/include/asm/processor.h
index 2799d59e385a..1342241742ac 100644
--- a/xen/arch/x86/include/asm/processor.h
+++ b/xen/arch/x86/include/asm/processor.h
@@ -333,8 +333,6 @@ extern void write_ptbase(struct vcpu *v);
 /* PAUSE (encoding: REP NOP) is a good thing to insert into busy-wait loops. */
 #define cpu_relax() asm volatile ( "pause" ::: "memory" )
 
-void show_code(const struct cpu_user_regs *regs);
-void show_stack_overflow(unsigned int cpu, const struct cpu_user_regs *regs);
 void show_registers(const struct cpu_user_regs *regs);
 #define dump_execution_state() run_in_exception_handler(show_execution_state)
 void show_page_walk(unsigned long addr);
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index ab8ff36acfe6..270b93ed623e 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -354,7 +354,7 @@ void show_page_walk(unsigned long addr)
            l1_table_offset(addr), l1e_get_intpte(l1e), pfn);
 }
 
-void show_code(const struct cpu_user_regs *regs)
+static void show_code(const struct cpu_user_regs *regs)
 {
     unsigned char insns_before[8] = {}, insns_after[16] = {};
     unsigned int i, tmp, missing_before, missing_after;
@@ -838,7 +838,7 @@ static void show_stack(const struct cpu_user_regs *regs)
     show_trace(regs);
 }
 
-void show_stack_overflow(unsigned int cpu, const struct cpu_user_regs *regs)
+static void show_stack_overflow(unsigned int cpu, const struct cpu_user_regs *regs)
 {
     unsigned long esp = regs->rsp;
     unsigned long curr_stack_base = esp & ~(STACK_SIZE - 1);
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 06/22] x86/traps: Introduce bsp_traps_reinit()
Date: Fri,  8 Aug 2025 21:22:58 +0100
Message-Id: <20250808202314.1045968-7-andrew.cooper3@citrix.com>
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... to abstract away updating the refereces to the old BSP stack.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/traps.h | 1 +
 xen/arch/x86/setup.c             | 6 +-----
 xen/arch/x86/traps-setup.c       | 9 +++++++++
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/include/asm/traps.h b/xen/arch/x86/include/asm/traps.h
index 7414420e57d8..6ae451d3fc70 100644
--- a/xen/arch/x86/include/asm/traps.h
+++ b/xen/arch/x86/include/asm/traps.h
@@ -9,6 +9,7 @@
 
 void bsp_early_traps_init(void);
 void traps_init(void);
+void bsp_traps_reinit(void);
 void percpu_traps_init(void);
 
 extern unsigned int ler_msr;
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 64f02699e1aa..c8c408e02436 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -902,11 +902,7 @@ static void __init noreturn reinit_bsp_stack(void)
     unsigned long *stack = (void*)(get_stack_bottom() & ~(STACK_SIZE - 1));
     int rc;
 
-    /* Update TSS and ISTs */
-    load_system_tables();
-
-    /* Update SYSCALL trampolines */
-    percpu_traps_init();
+    bsp_traps_reinit();
 
     stack_base[0] = stack;
 
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index 7713f427d344..370f4d5f7b60 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -107,6 +107,15 @@ void __init traps_init(void)
     percpu_traps_init();
 }
 
+/*
+ * Re-initialise all state referencing the early-boot stack.
+ */
+void bsp_traps_reinit(void)
+{
+    load_system_tables();
+    percpu_traps_init();
+}
+
 /*
  * Set up per-CPU linkage registers for exception, interrupt and syscall
  * handling.
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 10/22] x86/traps: Move subarch_percpu_traps_init() into traps-setup.c
Date: Fri,  8 Aug 2025 21:23:02 +0100
Message-Id: <20250808202314.1045968-11-andrew.cooper3@citrix.com>
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... along with the supporting functions.  Switch to Xen coding style, and make
static as there are no external callers.

Rename to legacy_syscall_init() as a more accurate name.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/system.h |  2 -
 xen/arch/x86/traps-setup.c        | 97 ++++++++++++++++++++++++++++++-
 xen/arch/x86/x86_64/traps.c       | 92 -----------------------------
 3 files changed, 95 insertions(+), 96 deletions(-)

diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
index 3cdc56e4ba6d..6c2800d8158d 100644
--- a/xen/arch/x86/include/asm/system.h
+++ b/xen/arch/x86/include/asm/system.h
@@ -256,6 +256,4 @@ static inline int local_irq_is_enabled(void)
 #define BROKEN_ACPI_Sx          0x0001
 #define BROKEN_INIT_AFTER_S1    0x0002
 
-void subarch_percpu_traps_init(void);
-
 #endif
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index 13b8fcf0ba51..fbae7072c292 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -2,13 +2,15 @@
 /*
  * Configuration of event handling for all CPUs.
  */
+#include 
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 
 DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt);
@@ -19,6 +21,8 @@ static bool __initdata opt_ler;
 boolean_param("ler", opt_ler);
 
 void nocall entry_PF(void);
+void nocall lstar_enter(void);
+void nocall cstar_enter(void);
 
 /*
  * Sets up system tables and descriptors for IDT devliery.
@@ -138,6 +142,95 @@ static void load_system_tables(void)
     BUG_ON(stack_bottom & 15);
 }
 
+static unsigned int write_stub_trampoline(
+    unsigned char *stub, unsigned long stub_va,
+    unsigned long stack_bottom, unsigned long target_va)
+{
+    unsigned char *p = stub;
+
+    if ( cpu_has_xen_ibt )
+    {
+        place_endbr64(p);
+        p += 4;
+    }
+
+    /* Store guest %rax into %ss slot */
+    /* movabsq %rax, stack_bottom - 8 */
+    *p++ = 0x48;
+    *p++ = 0xa3;
+    *(uint64_t *)p = stack_bottom - 8;
+    p += 8;
+
+    /* Store guest %rsp in %rax */
+    /* movq %rsp, %rax */
+    *p++ = 0x48;
+    *p++ = 0x89;
+    *p++ = 0xe0;
+
+    /* Switch to Xen stack */
+    /* movabsq $stack_bottom - 8, %rsp */
+    *p++ = 0x48;
+    *p++ = 0xbc;
+    *(uint64_t *)p = stack_bottom - 8;
+    p += 8;
+
+    /* jmp target_va */
+    *p++ = 0xe9;
+    *(int32_t *)p = target_va - (stub_va + (p - stub) + 4);
+    p += 4;
+
+    /* Round up to a multiple of 16 bytes. */
+    return ROUNDUP(p - stub, 16);
+}
+
+static void legacy_syscall_init(void)
+{
+    unsigned long stack_bottom = get_stack_bottom();
+    unsigned long stub_va = this_cpu(stubs.addr);
+    unsigned char *stub_page;
+    unsigned int offset;
+
+    /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
+    if ( !IS_ENABLED(CONFIG_PV) )
+        return;
+
+    stub_page = map_domain_page(_mfn(this_cpu(stubs.mfn)));
+
+    /*
+     * Trampoline for SYSCALL entry from 64-bit mode.  The VT-x HVM vcpu
+     * context switch logic relies on the SYSCALL trampoline being at the
+     * start of the stubs.
+     */
+    wrmsrl(MSR_LSTAR, stub_va);
+    offset = write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
+                                   stub_va, stack_bottom,
+                                   (unsigned long)lstar_enter);
+    stub_va += offset;
+
+    if ( cpu_has_sep )
+    {
+        /* SYSENTER entry. */
+        wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
+        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
+        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
+    }
+
+    /* Trampoline for SYSCALL entry from compatibility mode. */
+    wrmsrl(MSR_CSTAR, stub_va);
+    offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
+                                    stub_va, stack_bottom,
+                                    (unsigned long)cstar_enter);
+
+    /* Don't consume more than half of the stub space here. */
+    ASSERT(offset <= STUB_BUF_SIZE / 2);
+
+    unmap_domain_page(stub_page);
+
+    /* Common SYSCALL parameters. */
+    wrmsrl(MSR_STAR, XEN_MSR_STAR);
+    wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
+}
+
 static void __init init_ler(void)
 {
     unsigned int msr = 0;
@@ -241,7 +334,7 @@ void bsp_traps_reinit(void)
  */
 void percpu_traps_init(void)
 {
-    subarch_percpu_traps_init();
+    legacy_syscall_init();
 
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c
index 34adf55e48df..81e64466e47e 100644
--- a/xen/arch/x86/x86_64/traps.c
+++ b/xen/arch/x86/x86_64/traps.c
@@ -311,98 +311,6 @@ void asmlinkage noreturn do_double_fault(struct cpu_user_regs *regs)
     panic("DOUBLE FAULT -- system shutdown\n");
 }
 
-static unsigned int write_stub_trampoline(
-    unsigned char *stub, unsigned long stub_va,
-    unsigned long stack_bottom, unsigned long target_va)
-{
-    unsigned char *p = stub;
-
-    if ( cpu_has_xen_ibt )
-    {
-        place_endbr64(p);
-        p += 4;
-    }
-
-    /* Store guest %rax into %ss slot */
-    /* movabsq %rax, stack_bottom - 8 */
-    *p++ = 0x48;
-    *p++ = 0xa3;
-    *(uint64_t *)p = stack_bottom - 8;
-    p += 8;
-
-    /* Store guest %rsp in %rax */
-    /* movq %rsp, %rax */
-    *p++ = 0x48;
-    *p++ = 0x89;
-    *p++ = 0xe0;
-
-    /* Switch to Xen stack */
-    /* movabsq $stack_bottom - 8, %rsp */
-    *p++ = 0x48;
-    *p++ = 0xbc;
-    *(uint64_t *)p = stack_bottom - 8;
-    p += 8;
-
-    /* jmp target_va */
-    *p++ = 0xe9;
-    *(int32_t *)p = target_va - (stub_va + (p - stub) + 4);
-    p += 4;
-
-    /* Round up to a multiple of 16 bytes. */
-    return ROUNDUP(p - stub, 16);
-}
-
-void nocall lstar_enter(void);
-void nocall cstar_enter(void);
-
-void subarch_percpu_traps_init(void)
-{
-    unsigned long stack_bottom = get_stack_bottom();
-    unsigned long stub_va = this_cpu(stubs.addr);
-    unsigned char *stub_page;
-    unsigned int offset;
-
-    /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
-    if ( !IS_ENABLED(CONFIG_PV) )
-        return;
-
-    stub_page = map_domain_page(_mfn(this_cpu(stubs.mfn)));
-
-    /*
-     * Trampoline for SYSCALL entry from 64-bit mode.  The VT-x HVM vcpu
-     * context switch logic relies on the SYSCALL trampoline being at the
-     * start of the stubs.
-     */
-    wrmsrl(MSR_LSTAR, stub_va);
-    offset = write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
-                                   stub_va, stack_bottom,
-                                   (unsigned long)lstar_enter);
-    stub_va += offset;
-
-    if ( cpu_has_sep )
-    {
-        /* SYSENTER entry. */
-        wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
-        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
-        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
-    }
-
-    /* Trampoline for SYSCALL entry from compatibility mode. */
-    wrmsrl(MSR_CSTAR, stub_va);
-    offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
-                                    stub_va, stack_bottom,
-                                    (unsigned long)cstar_enter);
-
-    /* Don't consume more than half of the stub space here. */
-    ASSERT(offset <= STUB_BUF_SIZE / 2);
-
-    unmap_domain_page(stub_page);
-
-    /* Common SYSCALL parameters. */
-    wrmsrl(MSR_STAR, XEN_MSR_STAR);
-    wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
-}
-
 /*
  * Local variables:
  * mode: C
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 05/22] x86/traps: Rename early_traps_init() to bsp_early_traps_init()
Date: Fri,  8 Aug 2025 21:22:57 +0100
Message-Id: <20250808202314.1045968-6-andrew.cooper3@citrix.com>
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We're going to want to introduce an AP version shortly.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/traps.h | 2 +-
 xen/arch/x86/setup.c             | 2 +-
 xen/arch/x86/traps-setup.c       | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/include/asm/traps.h b/xen/arch/x86/include/asm/traps.h
index 72c33a33e283..7414420e57d8 100644
--- a/xen/arch/x86/include/asm/traps.h
+++ b/xen/arch/x86/include/asm/traps.h
@@ -7,7 +7,7 @@
 #ifndef ASM_TRAP_H
 #define ASM_TRAP_H
 
-void early_traps_init(void);
+void bsp_early_traps_init(void);
 void traps_init(void);
 void percpu_traps_init(void);
 
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 1543dd251cc6..64f02699e1aa 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1134,7 +1134,7 @@ void asmlinkage __init noreturn __start_xen(void)
 
     percpu_init_areas();
 
-    early_traps_init();
+    bsp_early_traps_init();
 
     smp_prepare_boot_cpu();
     sort_exception_tables();
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index a8385b26ae9b..7713f427d344 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -62,7 +62,7 @@ static void __init init_ler(void)
  * boot_gdt is already loaded, and bsp_idt[] is constructed without IST
  * settings, so we don't need a TSS configured yet.
  */
-void __init early_traps_init(void)
+void __init bsp_early_traps_init(void)
 {
     const struct desc_ptr idtr = {
         .base = (unsigned long)bsp_idt,
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 03/22] x86/traps: Drop incorrect BUILD_BUG_ON() and comment in load_system_tables()
Date: Fri,  8 Aug 2025 21:22:55 +0100
Message-Id: <20250808202314.1045968-4-andrew.cooper3@citrix.com>
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This was added erroneously by me.

Hardware task switching does demand a TSS of at least 0x67 bytes, but that's
not relevant in 64bit, and not relevant for Xen since commit
5d1181a5ea5e ("xen: Remove x86_32 build target.") in 2012.

We already load a 0-length TSS in early_traps_init() demonstrating that it's
possible.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/cpu/common.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index f6ec5c9df522..cdc41248d4e9 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -936,8 +936,6 @@ void load_system_tables(void)
 		wrmsrl(MSR_ISST, (unsigned long)ist_ssp);
 	}
 
-	BUILD_BUG_ON(sizeof(*tss) <= 0x67); /* Mandated by the architecture. */
-
 	_set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
 			 sizeof(*tss) - 1, SYS_DESC_tss_avail);
 	if ( IS_ENABLED(CONFIG_PV32) )
-- 
2.39.5



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	Hi
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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 01/22] x86/msr: Rename MSR_INTERRUPT_SSP_TABLE to MSR_ISST
Date: Fri,  8 Aug 2025 21:22:53 +0100
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The name AMD chose is rather more concise.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/cpu/common.c            | 2 +-
 xen/arch/x86/include/asm/msr-index.h | 2 +-
 xen/arch/x86/msr.c                   | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 97bdda1d4a25..f6ec5c9df522 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -933,7 +933,7 @@ void load_system_tables(void)
 			wrss(df_ssp,  _p(df_ssp));
 		}
 
-		wrmsrl(MSR_INTERRUPT_SSP_TABLE, (unsigned long)ist_ssp);
+		wrmsrl(MSR_ISST, (unsigned long)ist_ssp);
 	}
 
 	BUILD_BUG_ON(sizeof(*tss) <= 0x67); /* Mandated by the architecture. */
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 2e7e2aff9a33..428d993ee89b 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -157,7 +157,7 @@
 #define MSR_PL1_SSP                         0x000006a5
 #define MSR_PL2_SSP                         0x000006a6
 #define MSR_PL3_SSP                         0x000006a7
-#define MSR_INTERRUPT_SSP_TABLE             0x000006a8
+#define MSR_ISST                            0x000006a8
 
 #define MSR_PKRS                            0x000006e1
 
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 2cd46b6c8afa..1bf117cbd80f 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -138,7 +138,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
     case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7):
     case MSR_U_CET:
     case MSR_S_CET:
-    case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE:
+    case MSR_PL0_SSP ... MSR_ISST:
     case MSR_AMD64_LWP_CFG:
     case MSR_AMD64_LWP_CBADDR:
     case MSR_PPIN_CTL:
@@ -442,7 +442,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
     case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7):
     case MSR_U_CET:
     case MSR_S_CET:
-    case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE:
+    case MSR_PL0_SSP ... MSR_ISST:
     case MSR_AMD64_LWP_CFG:
     case MSR_AMD64_LWP_CBADDR:
     case MSR_PPIN_CTL:
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 04/22] x86/idt: Minor improvements to _update_gate_addr_lower()
Date: Fri,  8 Aug 2025 21:22:56 +0100
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After some experimentation, using .a/.b makes far better logic than using the
named fields, as both Clang and GCC spill idte to the stack when named fields
are used.

GCC seems to do something very daft for the addr1 field.  It takes addr,
shifts it by 32, then ANDs with 0xffff0000000000000UL, which requires
manifesting a MOVABS.

Clang follows the C, whereby it ANDs with $imm32, then shifts, avoiding the
MOVABS entirely.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

I'm disappointed about how poor the code generation is when assigning to named
fields, but I suppose it is a harder problem for the compiler to figure out.

add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-24 (-24)
Function                                     old     new   delta
machine_kexec                                356     348      -8
traps_init                                   434     418     -16
---
 xen/arch/x86/include/asm/idt.h | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/include/asm/idt.h b/xen/arch/x86/include/asm/idt.h
index f613d5693e0e..b5e570a77fae 100644
--- a/xen/arch/x86/include/asm/idt.h
+++ b/xen/arch/x86/include/asm/idt.h
@@ -92,15 +92,16 @@ static inline void _set_gate_lower(idt_entry_t *gate, unsigned long type,
  * Update the lower half handler of an IDT entry, without changing any other
  * configuration.
  */
-static inline void _update_gate_addr_lower(idt_entry_t *gate, void *addr)
+static inline void _update_gate_addr_lower(idt_entry_t *gate, void *_addr)
 {
+    unsigned long addr = (unsigned long)_addr;
+    unsigned int addr1 = addr & 0xffff0000U; /* GCC force better codegen. */
     idt_entry_t idte;
-    idte.a = gate->a;
 
-    idte.b = ((unsigned long)(addr) >> 32);
-    idte.a &= 0x0000FFFFFFFF0000ULL;
-    idte.a |= (((unsigned long)(addr) & 0xFFFF0000UL) << 32) |
-        ((unsigned long)(addr) & 0xFFFFUL);
+    idte.b = addr >> 32;
+    idte.a = gate->a & 0x0000ffffffff0000UL;
+    idte.a |= (unsigned long)addr1 << 32;
+    idte.a |= addr & 0xffff;
 
     _write_gate_lower(gate, &idte);
 }
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper 
Subject: [PATCH 00/22] x86: FRED support, part 1 (stacks and exceptions)
Date: Fri,  8 Aug 2025 21:22:52 +0100
Message-Id: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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Patches 1-12 are cleanup and rearrangement in order to fit FRED in more
nicely.

Patches 13-22 are the start of FRED support, setting up the stacks and
exception handling.

By the end of this series, Xen can run a PVH dom0 (if NMIs aren't in use -
VT-x has a really nasty corner case here), or can get to the point of
launching a PV dom0.  Running a PV dom0 is going to take a similar quantity of
work.

All deveopment work has been done with Intel SIMICS.  I don't yet have real
hardware to test on.

The Gitlab CI AlderLake box, sporting both Shadow Stacks and S3 has been
working overtime checking that S3 works on every relevant patch boundary.

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1974989391


Andrew Cooper (22):
  x86/msr: Rename MSR_INTERRUPT_SSP_TABLE to MSR_ISST
  x86/msr: Rename wrmsr_ns() to wrmsrns(), and take 64bit value
  x86/traps: Drop incorrect BUILD_BUG_ON() and comment in load_system_tables()
  x86/idt: Minor improvements to _update_gate_addr_lower()
  x86/traps: Rename early_traps_init() to bsp_early_traps_init()
  x86/traps: Introduce bsp_traps_reinit()
  x86/spec-ctrl: Rework init_shadow_spec_ctrl_state() to take an info pointer
  x86/traps: Introduce ap_early_traps_init() and set up exception handling earlier
  x86/traps: Move load_system_tables() into traps-setup.c
  x86/traps: Move subarch_percpu_traps_init() into traps-setup.c
  x86/traps: Fold x86_64/traps.c into traps.c
  x86/traps: Unexport show_code() and show_stack_overflow()
  x86: FRED enumerations
  x86/traps: Extend struct cpu_user_regs/cpu_info with FRED fields
  x86/traps: Introduce opt_fred
  x86/boot: Adjust CR4 handling around ap_early_traps_init()
  x86/S3: Switch to using RSTORSSP to recover SSP on resume
  x86/traps: Set MSR_PL0_SSP in load_system_tables()
  x86/boot: Use RSTORSSP to establish SSP
  x86/traps: Alter switch_stack_and_jump() for FRED mode
  x86/traps: Introduce FRED entrypoints
  x86/traps: Enable FRED when requested

 docs/misc/xen-command-line.pandoc           |  10 +
 xen/arch/x86/Kconfig                        |   4 +
 xen/arch/x86/acpi/wakeup_prot.S             |  57 +--
 xen/arch/x86/boot/x86_64.S                  |  53 ++-
 xen/arch/x86/cpu/common.c                   | 120 ------
 xen/arch/x86/include/asm/asm-defns.h        |   9 +
 xen/arch/x86/include/asm/asm_defns.h        |  65 +++
 xen/arch/x86/include/asm/cpu-user-regs.h    |  71 +++-
 xen/arch/x86/include/asm/cpufeature.h       |   3 +
 xen/arch/x86/include/asm/current.h          |  14 +-
 xen/arch/x86/include/asm/idt.h              |  13 +-
 xen/arch/x86/include/asm/msr-index.h        |  13 +-
 xen/arch/x86/include/asm/msr.h              |  12 +-
 xen/arch/x86/include/asm/processor.h        |   2 -
 xen/arch/x86/include/asm/prot-key.h         |   4 +-
 xen/arch/x86/include/asm/spec_ctrl.h        |   4 +-
 xen/arch/x86/include/asm/system.h           |   3 -
 xen/arch/x86/include/asm/traps.h            |   7 +-
 xen/arch/x86/include/asm/x86-defns.h        |   1 +
 xen/arch/x86/msr.c                          |   4 +-
 xen/arch/x86/setup.c                        |  37 +-
 xen/arch/x86/smpboot.c                      |  17 +-
 xen/arch/x86/spec_ctrl.c                    |   2 +-
 xen/arch/x86/traps-setup.c                  | 358 +++++++++++++++-
 xen/arch/x86/traps.c                        | 448 +++++++++++++++++++-
 xen/arch/x86/x86_64/Makefile                |   2 +-
 xen/arch/x86/x86_64/entry-fred.S            |  35 ++
 xen/arch/x86/x86_64/traps.c                 | 414 ------------------
 xen/include/public/arch-x86/cpufeatureset.h |   3 +
 xen/include/xen/macros.h                    |   2 +
 30 files changed, 1142 insertions(+), 645 deletions(-)
 create mode 100644 xen/arch/x86/x86_64/entry-fred.S
 delete mode 100644 xen/arch/x86/x86_64/traps.c

-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 11/22] x86/traps: Fold x86_64/traps.c into traps.c
Date: Fri,  8 Aug 2025 21:23:03 +0100
Message-Id: <20250808202314.1045968-12-andrew.cooper3@citrix.com>
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It's now just the double fault handler and various state dumping functions.

Swap u64 for uint64_t, and fix a few other minor style issues.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/traps.c         | 291 +++++++++++++++++++++++++++++++
 xen/arch/x86/x86_64/Makefile |   1 -
 xen/arch/x86/x86_64/traps.c  | 322 -----------------------------------
 3 files changed, 291 insertions(+), 323 deletions(-)
 delete mode 100644 xen/arch/x86/x86_64/traps.c

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 238d923dd188..ab8ff36acfe6 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -87,6 +88,272 @@ const unsigned int nmi_cpu;
 #define stack_words_per_line 4
 #define ESP_BEFORE_EXCEPTION(regs) ((unsigned long *)(regs)->rsp)
 
+struct extra_state
+{
+    unsigned long cr0, cr2, cr3, cr4;
+    unsigned long fsb, gsb, gss;
+    uint16_t ds, es, fs, gs;
+};
+
+static void print_xen_info(void)
+{
+    char taint_str[TAINT_STRING_MAX_LEN];
+
+    printk("----[ Xen-%d.%d%s  x86_64  %s  %s ]----\n",
+           xen_major_version(), xen_minor_version(), xen_extra_version(),
+           xen_build_info(), print_tainted(taint_str));
+}
+
+enum context {
+    CTXT_hypervisor,
+    CTXT_pv_guest,
+    CTXT_hvm_guest,
+};
+
+static void read_registers(struct extra_state *state)
+{
+    state->cr0 = read_cr0();
+    state->cr2 = read_cr2();
+    state->cr3 = read_cr3();
+    state->cr4 = read_cr4();
+
+    state->fsb = read_fs_base();
+    state->gsb = read_gs_base();
+    state->gss = read_gs_shadow();
+
+    asm ( "mov %%ds, %0" : "=m" (state->ds) );
+    asm ( "mov %%es, %0" : "=m" (state->es) );
+    asm ( "mov %%fs, %0" : "=m" (state->fs) );
+    asm ( "mov %%gs, %0" : "=m" (state->gs) );
+}
+
+static void get_hvm_registers(struct vcpu *v, struct cpu_user_regs *regs,
+                              struct extra_state *state)
+{
+    struct segment_register sreg;
+
+    state->cr0 = v->arch.hvm.guest_cr[0];
+    state->cr2 = v->arch.hvm.guest_cr[2];
+    state->cr3 = v->arch.hvm.guest_cr[3];
+    state->cr4 = v->arch.hvm.guest_cr[4];
+
+    hvm_get_segment_register(v, x86_seg_cs, &sreg);
+    regs->cs = sreg.sel;
+
+    hvm_get_segment_register(v, x86_seg_ds, &sreg);
+    state->ds = sreg.sel;
+
+    hvm_get_segment_register(v, x86_seg_es, &sreg);
+    state->es = sreg.sel;
+
+    hvm_get_segment_register(v, x86_seg_fs, &sreg);
+    state->fs = sreg.sel;
+    state->fsb = sreg.base;
+
+    hvm_get_segment_register(v, x86_seg_gs, &sreg);
+    state->gs = sreg.sel;
+    state->gsb = sreg.base;
+
+    hvm_get_segment_register(v, x86_seg_ss, &sreg);
+    regs->ss = sreg.sel;
+
+    state->gss = hvm_get_reg(v, MSR_SHADOW_GS_BASE);
+}
+
+static void _show_registers(
+    const struct cpu_user_regs *regs, const struct extra_state *state,
+    enum context context, const struct vcpu *v)
+{
+    static const char *const context_names[] = {
+        [CTXT_hypervisor] = "hypervisor",
+        [CTXT_pv_guest]   = "pv guest",
+        [CTXT_hvm_guest]  = "hvm guest",
+    };
+
+    printk("RIP:    %04x:[<%016lx>]", regs->cs, regs->rip);
+    if ( context == CTXT_hypervisor )
+        printk(" %pS", _p(regs->rip));
+    printk("\nRFLAGS: %016lx   ", regs->rflags);
+    if ( (context == CTXT_pv_guest) && v && v->vcpu_info_area.map )
+        printk("EM: %d   ", !!vcpu_info(v, evtchn_upcall_mask));
+    printk("CONTEXT: %s", context_names[context]);
+    if ( v && !is_idle_vcpu(v) )
+        printk(" (%pv)", v);
+
+    printk("\nrax: %016lx   rbx: %016lx   rcx: %016lx\n",
+           regs->rax, regs->rbx, regs->rcx);
+    printk("rdx: %016lx   rsi: %016lx   rdi: %016lx\n",
+           regs->rdx, regs->rsi, regs->rdi);
+    printk("rbp: %016lx   rsp: %016lx   r8:  %016lx\n",
+           regs->rbp, regs->rsp, regs->r8);
+    printk("r9:  %016lx   r10: %016lx   r11: %016lx\n",
+           regs->r9,  regs->r10, regs->r11);
+    printk("r12: %016lx   r13: %016lx   r14: %016lx\n",
+           regs->r12, regs->r13, regs->r14);
+    printk("r15: %016lx   cr0: %016lx   cr4: %016lx\n",
+           regs->r15, state->cr0, state->cr4);
+    printk("cr3: %016lx   cr2: %016lx\n", state->cr3, state->cr2);
+    printk("fsb: %016lx   gsb: %016lx   gss: %016lx\n",
+           state->fsb, state->gsb, state->gss);
+    printk("ds: %04x   es: %04x   fs: %04x   gs: %04x   ss: %04x   cs: %04x\n",
+           state->ds, state->es, state->fs,
+           state->gs, regs->ss, regs->cs);
+}
+
+void show_registers(const struct cpu_user_regs *regs)
+{
+    struct cpu_user_regs fault_regs = *regs;
+    struct extra_state fault_state;
+    enum context context;
+    struct vcpu *v = system_state >= SYS_STATE_smp_boot ? current : NULL;
+
+    if ( guest_mode(regs) && is_hvm_vcpu(v) )
+    {
+        get_hvm_registers(v, &fault_regs, &fault_state);
+        context = CTXT_hvm_guest;
+    }
+    else
+    {
+        read_registers(&fault_state);
+
+        if ( guest_mode(regs) )
+        {
+            context = CTXT_pv_guest;
+            fault_state.cr2 = arch_get_cr2(v);
+        }
+        else
+        {
+            context = CTXT_hypervisor;
+        }
+    }
+
+    print_xen_info();
+    printk("CPU:    %d\n", smp_processor_id());
+    _show_registers(&fault_regs, &fault_state, context, v);
+
+    if ( ler_msr && !guest_mode(regs) )
+    {
+        uint64_t from, to;
+
+        rdmsrl(ler_msr, from);
+        rdmsrl(ler_msr + 1, to);
+
+        /* Upper bits may store metadata.  Re-canonicalise for printing. */
+        printk("ler: from %016"PRIx64" [%ps]\n",
+               from, _p(canonicalise_addr(from)));
+        printk("       to %016"PRIx64" [%ps]\n",
+               to, _p(canonicalise_addr(to)));
+    }
+}
+
+void vcpu_show_registers(struct vcpu *v)
+{
+    const struct cpu_user_regs *regs = &v->arch.user_regs;
+    struct cpu_user_regs aux_regs;
+    struct extra_state state;
+    enum context context;
+
+    if ( is_hvm_vcpu(v) )
+    {
+        aux_regs = *regs;
+        get_hvm_registers(v, &aux_regs, &state);
+        regs = &aux_regs;
+        context = CTXT_hvm_guest;
+    }
+    else
+    {
+        bool kernel = guest_kernel_mode(v, regs);
+        unsigned long gsb, gss;
+
+        state.cr0 = v->arch.pv.ctrlreg[0];
+        state.cr2 = arch_get_cr2(v);
+        state.cr3 = pagetable_get_paddr(kernel
+                                        ? v->arch.guest_table
+                                        : v->arch.guest_table_user);
+        state.cr4 = v->arch.pv.ctrlreg[4];
+
+        gsb = v->arch.pv.gs_base_user;
+        gss = v->arch.pv.gs_base_kernel;
+        if ( kernel )
+            SWAP(gsb, gss);
+
+        state.fsb = v->arch.pv.fs_base;
+        state.gsb = gsb;
+        state.gss = gss;
+
+        state.ds = v->arch.pv.ds;
+        state.es = v->arch.pv.es;
+        state.fs = v->arch.pv.fs;
+        state.gs = v->arch.pv.gs;
+
+        context = CTXT_pv_guest;
+    }
+
+    _show_registers(regs, &state, context, v);
+}
+
+void show_page_walk(unsigned long addr)
+{
+    unsigned long pfn, mfn = read_cr3() >> PAGE_SHIFT;
+    l4_pgentry_t l4e, *l4t;
+    l3_pgentry_t l3e, *l3t;
+    l2_pgentry_t l2e, *l2t;
+    l1_pgentry_t l1e, *l1t;
+
+    printk("Pagetable walk from %016lx:\n", addr);
+    if ( !is_canonical_address(addr) )
+        return;
+
+    l4t = map_domain_page(_mfn(mfn));
+    l4e = l4t[l4_table_offset(addr)];
+    unmap_domain_page(l4t);
+    mfn = l4e_get_pfn(l4e);
+    pfn = mfn_valid(_mfn(mfn)) && machine_to_phys_mapping_valid ?
+          get_gpfn_from_mfn(mfn) : INVALID_M2P_ENTRY;
+    printk(" L4[0x%03lx] = %"PRIpte" %016lx\n",
+           l4_table_offset(addr), l4e_get_intpte(l4e), pfn);
+    if ( !(l4e_get_flags(l4e) & _PAGE_PRESENT) ||
+         !mfn_valid(_mfn(mfn)) )
+        return;
+
+    l3t = map_domain_page(_mfn(mfn));
+    l3e = l3t[l3_table_offset(addr)];
+    unmap_domain_page(l3t);
+    mfn = l3e_get_pfn(l3e);
+    pfn = mfn_valid(_mfn(mfn)) && machine_to_phys_mapping_valid ?
+          get_gpfn_from_mfn(mfn) : INVALID_M2P_ENTRY;
+    printk(" L3[0x%03lx] = %"PRIpte" %016lx%s\n",
+           l3_table_offset(addr), l3e_get_intpte(l3e), pfn,
+           (l3e_get_flags(l3e) & _PAGE_PSE) ? " (PSE)" : "");
+    if ( !(l3e_get_flags(l3e) & _PAGE_PRESENT) ||
+         (l3e_get_flags(l3e) & _PAGE_PSE) ||
+         !mfn_valid(_mfn(mfn)) )
+        return;
+
+    l2t = map_domain_page(_mfn(mfn));
+    l2e = l2t[l2_table_offset(addr)];
+    unmap_domain_page(l2t);
+    mfn = l2e_get_pfn(l2e);
+    pfn = mfn_valid(_mfn(mfn)) && machine_to_phys_mapping_valid ?
+          get_gpfn_from_mfn(mfn) : INVALID_M2P_ENTRY;
+    printk(" L2[0x%03lx] = %"PRIpte" %016lx%s\n",
+           l2_table_offset(addr), l2e_get_intpte(l2e), pfn,
+           (l2e_get_flags(l2e) & _PAGE_PSE) ? " (PSE)" : "");
+    if ( !(l2e_get_flags(l2e) & _PAGE_PRESENT) ||
+         (l2e_get_flags(l2e) & _PAGE_PSE) ||
+         !mfn_valid(_mfn(mfn)) )
+        return;
+
+    l1t = map_domain_page(_mfn(mfn));
+    l1e = l1t[l1_table_offset(addr)];
+    unmap_domain_page(l1t);
+    mfn = l1e_get_pfn(l1e);
+    pfn = mfn_valid(_mfn(mfn)) && machine_to_phys_mapping_valid ?
+          get_gpfn_from_mfn(mfn) : INVALID_M2P_ENTRY;
+    printk(" L1[0x%03lx] = %"PRIpte" %016lx\n",
+           l1_table_offset(addr), l1e_get_intpte(l1e), pfn);
+}
+
 void show_code(const struct cpu_user_regs *regs)
 {
     unsigned char insns_before[8] = {}, insns_after[16] = {};
@@ -762,6 +1029,30 @@ const char *vector_name(unsigned int vec)
     return (vec < ARRAY_SIZE(names) && names[vec][0]) ? names[vec] : "???";
 }
 
+void asmlinkage do_double_fault(struct cpu_user_regs *regs)
+{
+    unsigned int cpu;
+    struct extra_state state;
+
+    console_force_unlock();
+
+    asm ( "lsll %[sel], %[limit]" : [limit] "=r" (cpu)
+                                  : [sel] "r" (PER_CPU_SELECTOR) );
+
+    /* Find information saved during fault and dump it to the console. */
+    printk("*** DOUBLE FAULT ***\n");
+    print_xen_info();
+
+    read_registers(&state);
+
+    printk("CPU:    %d\n", cpu);
+    _show_registers(regs, &state, CTXT_hypervisor, NULL);
+    show_code(regs);
+    show_stack_overflow(cpu, regs);
+
+    panic("DOUBLE FAULT -- system shutdown\n");
+}
+
 /*
  * This is called for faults at very unexpected times (e.g., when interrupts
  * are disabled). In such situations we can't do much that is safe. We try to
diff --git a/xen/arch/x86/x86_64/Makefile b/xen/arch/x86/x86_64/Makefile
index 472b2bab523d..f20763088740 100644
--- a/xen/arch/x86/x86_64/Makefile
+++ b/xen/arch/x86/x86_64/Makefile
@@ -1,7 +1,6 @@
 obj-$(CONFIG_PV32) += compat/
 
 obj-bin-y += entry.o
-obj-y += traps.o
 obj-$(CONFIG_KEXEC) += machine_kexec.o
 obj-y += pci.o
 obj-y += acpi_mmcfg.o
diff --git a/xen/arch/x86/x86_64/traps.c b/xen/arch/x86/x86_64/traps.c
deleted file mode 100644
index 81e64466e47e..000000000000
--- a/xen/arch/x86/x86_64/traps.c
+++ /dev/null
@@ -1,322 +0,0 @@
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-struct extra_state
-{
-    unsigned long cr0, cr2, cr3, cr4;
-    unsigned long fsb, gsb, gss;
-    uint16_t ds, es, fs, gs;
-};
-
-static void print_xen_info(void)
-{
-    char taint_str[TAINT_STRING_MAX_LEN];
-
-    printk("----[ Xen-%d.%d%s  x86_64  %s  %s ]----\n",
-           xen_major_version(), xen_minor_version(), xen_extra_version(),
-           xen_build_info(), print_tainted(taint_str));
-}
-
-enum context { CTXT_hypervisor, CTXT_pv_guest, CTXT_hvm_guest };
-
-static void read_registers(struct extra_state *state)
-{
-    state->cr0 = read_cr0();
-    state->cr2 = read_cr2();
-    state->cr3 = read_cr3();
-    state->cr4 = read_cr4();
-
-    state->fsb = read_fs_base();
-    state->gsb = read_gs_base();
-    state->gss = read_gs_shadow();
-
-    asm ( "mov %%ds, %0" : "=m" (state->ds) );
-    asm ( "mov %%es, %0" : "=m" (state->es) );
-    asm ( "mov %%fs, %0" : "=m" (state->fs) );
-    asm ( "mov %%gs, %0" : "=m" (state->gs) );
-}
-
-static void get_hvm_registers(struct vcpu *v, struct cpu_user_regs *regs,
-                              struct extra_state *state)
-{
-    struct segment_register sreg;
-
-    state->cr0 = v->arch.hvm.guest_cr[0];
-    state->cr2 = v->arch.hvm.guest_cr[2];
-    state->cr3 = v->arch.hvm.guest_cr[3];
-    state->cr4 = v->arch.hvm.guest_cr[4];
-
-    hvm_get_segment_register(v, x86_seg_cs, &sreg);
-    regs->cs = sreg.sel;
-
-    hvm_get_segment_register(v, x86_seg_ds, &sreg);
-    state->ds = sreg.sel;
-
-    hvm_get_segment_register(v, x86_seg_es, &sreg);
-    state->es = sreg.sel;
-
-    hvm_get_segment_register(v, x86_seg_fs, &sreg);
-    state->fs = sreg.sel;
-    state->fsb = sreg.base;
-
-    hvm_get_segment_register(v, x86_seg_gs, &sreg);
-    state->gs = sreg.sel;
-    state->gsb = sreg.base;
-
-    hvm_get_segment_register(v, x86_seg_ss, &sreg);
-    regs->ss = sreg.sel;
-
-    state->gss = hvm_get_reg(v, MSR_SHADOW_GS_BASE);
-}
-
-static void _show_registers(
-    const struct cpu_user_regs *regs, const struct extra_state *state,
-    enum context context, const struct vcpu *v)
-{
-    static const char *const context_names[] = {
-        [CTXT_hypervisor] = "hypervisor",
-        [CTXT_pv_guest]   = "pv guest",
-        [CTXT_hvm_guest]  = "hvm guest"
-    };
-
-    printk("RIP:    %04x:[<%016lx>]", regs->cs, regs->rip);
-    if ( context == CTXT_hypervisor )
-        printk(" %pS", _p(regs->rip));
-    printk("\nRFLAGS: %016lx   ", regs->rflags);
-    if ( (context == CTXT_pv_guest) && v && v->vcpu_info_area.map )
-        printk("EM: %d   ", !!vcpu_info(v, evtchn_upcall_mask));
-    printk("CONTEXT: %s", context_names[context]);
-    if ( v && !is_idle_vcpu(v) )
-        printk(" (%pv)", v);
-
-    printk("\nrax: %016lx   rbx: %016lx   rcx: %016lx\n",
-           regs->rax, regs->rbx, regs->rcx);
-    printk("rdx: %016lx   rsi: %016lx   rdi: %016lx\n",
-           regs->rdx, regs->rsi, regs->rdi);
-    printk("rbp: %016lx   rsp: %016lx   r8:  %016lx\n",
-           regs->rbp, regs->rsp, regs->r8);
-    printk("r9:  %016lx   r10: %016lx   r11: %016lx\n",
-           regs->r9,  regs->r10, regs->r11);
-    printk("r12: %016lx   r13: %016lx   r14: %016lx\n",
-           regs->r12, regs->r13, regs->r14);
-    printk("r15: %016lx   cr0: %016lx   cr4: %016lx\n",
-           regs->r15, state->cr0, state->cr4);
-    printk("cr3: %016lx   cr2: %016lx\n", state->cr3, state->cr2);
-    printk("fsb: %016lx   gsb: %016lx   gss: %016lx\n",
-           state->fsb, state->gsb, state->gss);
-    printk("ds: %04x   es: %04x   fs: %04x   gs: %04x   "
-           "ss: %04x   cs: %04x\n",
-           state->ds, state->es, state->fs,
-           state->gs, regs->ss, regs->cs);
-}
-
-void show_registers(const struct cpu_user_regs *regs)
-{
-    struct cpu_user_regs fault_regs = *regs;
-    struct extra_state fault_state;
-    enum context context;
-    struct vcpu *v = system_state >= SYS_STATE_smp_boot ? current : NULL;
-
-    if ( guest_mode(regs) && is_hvm_vcpu(v) )
-    {
-        get_hvm_registers(v, &fault_regs, &fault_state);
-        context = CTXT_hvm_guest;
-    }
-    else
-    {
-        read_registers(&fault_state);
-
-        if ( guest_mode(regs) )
-        {
-            context = CTXT_pv_guest;
-            fault_state.cr2 = arch_get_cr2(v);
-        }
-        else
-        {
-            context = CTXT_hypervisor;
-        }
-    }
-
-    print_xen_info();
-    printk("CPU:    %d\n", smp_processor_id());
-    _show_registers(&fault_regs, &fault_state, context, v);
-
-    if ( ler_msr && !guest_mode(regs) )
-    {
-        u64 from, to;
-
-        rdmsrl(ler_msr, from);
-        rdmsrl(ler_msr + 1, to);
-
-        /* Upper bits may store metadata.  Re-canonicalise for printing. */
-        printk("ler: from %016"PRIx64" [%ps]\n",
-               from, _p(canonicalise_addr(from)));
-        printk("       to %016"PRIx64" [%ps]\n",
-               to, _p(canonicalise_addr(to)));
-    }
-}
-
-void vcpu_show_registers(struct vcpu *v)
-{
-    const struct cpu_user_regs *regs = &v->arch.user_regs;
-    struct cpu_user_regs aux_regs;
-    struct extra_state state;
-    enum context context;
-
-    if ( is_hvm_vcpu(v) )
-    {
-        aux_regs = *regs;
-        get_hvm_registers(v, &aux_regs, &state);
-        regs = &aux_regs;
-        context = CTXT_hvm_guest;
-    }
-    else
-    {
-        bool kernel = guest_kernel_mode(v, regs);
-        unsigned long gsb, gss;
-
-        state.cr0 = v->arch.pv.ctrlreg[0];
-        state.cr2 = arch_get_cr2(v);
-        state.cr3 = pagetable_get_paddr(kernel
-                                        ? v->arch.guest_table
-                                        : v->arch.guest_table_user);
-        state.cr4 = v->arch.pv.ctrlreg[4];
-
-        gsb = v->arch.pv.gs_base_user;
-        gss = v->arch.pv.gs_base_kernel;
-        if ( kernel )
-            SWAP(gsb, gss);
-
-        state.fsb = v->arch.pv.fs_base;
-        state.gsb = gsb;
-        state.gss = gss;
-
-        state.ds = v->arch.pv.ds;
-        state.es = v->arch.pv.es;
-        state.fs = v->arch.pv.fs;
-        state.gs = v->arch.pv.gs;
-
-        context = CTXT_pv_guest;
-    }
-
-    _show_registers(regs, &state, context, v);
-}
-
-void show_page_walk(unsigned long addr)
-{
-    unsigned long pfn, mfn = read_cr3() >> PAGE_SHIFT;
-    l4_pgentry_t l4e, *l4t;
-    l3_pgentry_t l3e, *l3t;
-    l2_pgentry_t l2e, *l2t;
-    l1_pgentry_t l1e, *l1t;
-
-    printk("Pagetable walk from %016lx:\n", addr);
-    if ( !is_canonical_address(addr) )
-        return;
-
-    l4t = map_domain_page(_mfn(mfn));
-    l4e = l4t[l4_table_offset(addr)];
-    unmap_domain_page(l4t);
-    mfn = l4e_get_pfn(l4e);
-    pfn = mfn_valid(_mfn(mfn)) && machine_to_phys_mapping_valid ?
-          get_gpfn_from_mfn(mfn) : INVALID_M2P_ENTRY;
-    printk(" L4[0x%03lx] = %"PRIpte" %016lx\n",
-           l4_table_offset(addr), l4e_get_intpte(l4e), pfn);
-    if ( !(l4e_get_flags(l4e) & _PAGE_PRESENT) ||
-         !mfn_valid(_mfn(mfn)) )
-        return;
-
-    l3t = map_domain_page(_mfn(mfn));
-    l3e = l3t[l3_table_offset(addr)];
-    unmap_domain_page(l3t);
-    mfn = l3e_get_pfn(l3e);
-    pfn = mfn_valid(_mfn(mfn)) && machine_to_phys_mapping_valid ?
-          get_gpfn_from_mfn(mfn) : INVALID_M2P_ENTRY;
-    printk(" L3[0x%03lx] = %"PRIpte" %016lx%s\n",
-           l3_table_offset(addr), l3e_get_intpte(l3e), pfn,
-           (l3e_get_flags(l3e) & _PAGE_PSE) ? " (PSE)" : "");
-    if ( !(l3e_get_flags(l3e) & _PAGE_PRESENT) ||
-         (l3e_get_flags(l3e) & _PAGE_PSE) ||
-         !mfn_valid(_mfn(mfn)) )
-        return;
-
-    l2t = map_domain_page(_mfn(mfn));
-    l2e = l2t[l2_table_offset(addr)];
-    unmap_domain_page(l2t);
-    mfn = l2e_get_pfn(l2e);
-    pfn = mfn_valid(_mfn(mfn)) && machine_to_phys_mapping_valid ?
-          get_gpfn_from_mfn(mfn) : INVALID_M2P_ENTRY;
-    printk(" L2[0x%03lx] = %"PRIpte" %016lx%s\n",
-           l2_table_offset(addr), l2e_get_intpte(l2e), pfn,
-           (l2e_get_flags(l2e) & _PAGE_PSE) ? " (PSE)" : "");
-    if ( !(l2e_get_flags(l2e) & _PAGE_PRESENT) ||
-         (l2e_get_flags(l2e) & _PAGE_PSE) ||
-         !mfn_valid(_mfn(mfn)) )
-        return;
-
-    l1t = map_domain_page(_mfn(mfn));
-    l1e = l1t[l1_table_offset(addr)];
-    unmap_domain_page(l1t);
-    mfn = l1e_get_pfn(l1e);
-    pfn = mfn_valid(_mfn(mfn)) && machine_to_phys_mapping_valid ?
-          get_gpfn_from_mfn(mfn) : INVALID_M2P_ENTRY;
-    printk(" L1[0x%03lx] = %"PRIpte" %016lx\n",
-           l1_table_offset(addr), l1e_get_intpte(l1e), pfn);
-}
-
-void asmlinkage noreturn do_double_fault(struct cpu_user_regs *regs)
-{
-    unsigned int cpu;
-    struct extra_state state;
-
-    console_force_unlock();
-
-    asm ( "lsll %[sel], %[limit]" : [limit] "=r" (cpu)
-                                  : [sel] "r" (PER_CPU_SELECTOR) );
-
-    /* Find information saved during fault and dump it to the console. */
-    printk("*** DOUBLE FAULT ***\n");
-    print_xen_info();
-
-    read_registers(&state);
-
-    printk("CPU:    %d\n", cpu);
-    _show_registers(regs, &state, CTXT_hypervisor, NULL);
-    show_code(regs);
-    show_stack_overflow(cpu, regs);
-
-    panic("DOUBLE FAULT -- system shutdown\n");
-}
-
-/*
- * Local variables:
- * mode: C
- * c-file-style: "BSD"
- * c-basic-offset: 4
- * tab-width: 4
- * indent-tabs-mode: nil
- * End:
- */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 14/22] x86/traps: Extend struct cpu_user_regs/cpu_info with FRED fields
Date: Fri,  8 Aug 2025 21:23:06 +0100
Message-Id: <20250808202314.1045968-15-andrew.cooper3@citrix.com>
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The FRED on-stack format is larger than the IDT format, but is by and large
compatible.  FRED reuses space above cs and ss for extra metadata, some of
which is purely informational, and some of which causes additional effects in
ERET{U,S}.

Follow Linux's choice of naming for fred_{c,s}s structures, to make it very
clear at the point of use that it's dependent on FRED.

There is also the event data field and reserved fields, but we cannot include
these in struct cpu_user_regs without reintroducing OoB structure accesses in
the non-FRED case.  See commit 6065a05adf15 ("x86/traps: 'Fix' safety of
read_registers() in #DF path"). for more details.

Instead, use a new struct fred_info and position it suitably in struct
cpu_info.  This boundary will be loaded into MSR_FRED_RSP_SL0, and must be
64-byte aligned.

This does add 16 bytes back into struct cpu_info, undoing the saving we made
by dropping the vm86 data segment selectors.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/cpu-user-regs.h | 71 ++++++++++++++++++++++--
 xen/arch/x86/include/asm/current.h       |  2 +
 xen/arch/x86/traps-setup.c               |  5 ++
 3 files changed, 74 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/include/asm/cpu-user-regs.h
index d700a3ef3447..06d9cbfbe6ba 100644
--- a/xen/arch/x86/include/asm/cpu-user-regs.h
+++ b/xen/arch/x86/include/asm/cpu-user-regs.h
@@ -30,6 +30,10 @@ struct cpu_user_regs
     /*
      * During IDT delivery for exceptions with an error code, hardware pushes
      * to this point.  Entry_vector is filled in by software.
+     *
+     * During FRED delivery, hardware always pushes to this point.  Software
+     * copies fred_ss.vector into entry_vector so most interrupt/exception
+     * handling can be FRED-agnostic.
      */
 
     uint32_t error_code;
@@ -42,17 +46,76 @@ struct cpu_user_regs
      */
 
     union { uint64_t rip;    uint32_t eip;    uint16_t ip; };
-    uint16_t cs, _pad0[1];
-    uint8_t  saved_upcall_mask; /* PV (v)rflags.IF == !saved_upcall_mask */
-    uint8_t  _pad1[3];
+    union {
+        struct {
+            uint16_t      cs;
+            unsigned long :16;
+            uint8_t       saved_upcall_mask; /* PV (v)rflags.IF == !saved_upcall_mask */
+        };
+        unsigned long     csx;
+        struct {
+            /*
+             * Bits 0 thru 31 control ERET{U,S} behaviour, and is state of the
+             * interrupted context.
+             */
+            uint16_t      cs;
+            unsigned int  sl:2;      /* Stack Level */
+            bool          wfe:1;     /* Wait-for-ENDBRANCH state */
+        } fred_cs;
+    };
     union { uint64_t rflags; uint32_t eflags; uint16_t flags; };
     union { uint64_t rsp;    uint32_t esp;    uint16_t sp;    uint8_t spl; };
-    uint16_t ss, _pad2[3];
+    union {
+        uint16_t          ss;
+        unsigned long     ssx;
+        struct {
+            /*
+             * Bits 0 thru 31 control ERET{U,S} behaviour, and is state about
+             * the event which occured.
+             */
+            uint16_t      ss;
+            bool          sti:1;     /* Was blocked-by-STI, and not cancelled */
+            bool          swint:1;   /* Was a SYSCALL/SYSENTER/INT $N */
+            bool          nmi:1;     /* Was an NMI. */
+            unsigned long :13;
+
+            /*
+             * Bits 32 thru 63 are ignored by ERET{U,S} and are informative
+             * only.
+             */
+            uint8_t       vector;
+            unsigned long :8;
+            unsigned int  type:4;    /* X86_ET_* */
+            unsigned long :4;
+            bool          enclave:1; /* Event taken in SGX mode */
+            bool          lm:1;      /* Was in Long Mode */
+            bool          nested:1;  /* Exception during event delivery, clear for #DF */
+            unsigned long :1;
+            unsigned int  insnlen:4; /* .type >= SW_INT */
+        } fred_ss;
+    };
 
     /*
      * For IDT delivery, tss->rsp0 points to this boundary as embedded within
      * struct cpu_info.  It must be 16-byte aligned.
      */
 };
+struct fred_info
+{
+    /*
+     * Event Data.  For:
+     *   #DB: PENDING_DBG (%dr6 with positive polarity)
+     *   NMI: NMI-Source Bitmap (on capable hardware)
+     *   #PF: %cr2
+     *   #NM: MSR_XFD_ERR (only XFD-induced #NMs)
+     */
+    uint64_t edata;
+    uint64_t _rsvd;
+
+    /*
+     * For FRED delivery, MSR_FRED_RSP_SL0 points to this boundary as embedded
+     * within struct cpu_info.  It must be 64-byte aligned.
+     */
+};
 
 #endif /* X86_CPU_USER_REGS_H */
diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index a7c9473428b2..962eb76a82b3 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -38,6 +38,8 @@ struct vcpu;
 
 struct cpu_info {
     struct cpu_user_regs guest_cpu_user_regs;
+    struct fred_info _fred; /* Only used when FRED is active. */
+
     unsigned int processor_id;
     unsigned int verw_sel;
     struct vcpu *current_vcpu;
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index fbae7072c292..37202c17fcea 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -360,7 +360,12 @@ static void __init __maybe_unused build_assertions(void)
      *
      * tss->rsp0, pointing at the end of cpu_info.guest_cpu_user_regs, must be
      * 16-byte aligned.
+     *
+     * MSR_FRED_RSP_SL0, pointing to the end of cpu_info._fred must be 64-byte
+     * aligned.
      */
     BUILD_BUG_ON((sizeof(struct cpu_info) -
                   endof_field(struct cpu_info, guest_cpu_user_regs)) & 15);
+    BUILD_BUG_ON((sizeof(struct cpu_info) -
+                  endof_field(struct cpu_info, _fred)) & 63);
 }
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 16/22] x86/boot: Adjust CR4 handling around ap_early_traps_init()
Date: Fri,  8 Aug 2025 21:23:08 +0100
Message-Id: <20250808202314.1045968-17-andrew.cooper3@citrix.com>
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ap_early_traps_init() will shortly be setting CR4.FRED.  This requires that
cpu_info->cr4 is already set up, and that the enablement of CET doesn't
truncate FRED back out because of it's 32bit logic.

For __high_start(), defer re-loading XEN_MINIMAL_CR4 until after %rsp is set
up and we can store the result in the cr4 field too.

For s3_resume(), explicitly re-load XEN_MINIMAL_CR4.  Later when loading all
features, use the mmu_cr4_features variable which is how the rest of Xen
performs this operation.

No functional change, yet.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/acpi/wakeup_prot.S | 18 ++++++++++++++----
 xen/arch/x86/boot/x86_64.S      | 15 ++++++++++-----
 2 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/xen/arch/x86/acpi/wakeup_prot.S b/xen/arch/x86/acpi/wakeup_prot.S
index 60eca4010042..dfc8c6ac6e8c 100644
--- a/xen/arch/x86/acpi/wakeup_prot.S
+++ b/xen/arch/x86/acpi/wakeup_prot.S
@@ -63,6 +63,14 @@ LABEL(s3_resume)
         pushq   %rax
         lretq
 1:
+
+        GET_STACK_END(15)
+
+        /* Enable minimal CR4 features. */
+        mov     $XEN_MINIMAL_CR4, %eax
+        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
+        mov     %rax, %cr4
+
         /* Set up early exceptions and CET before entering C properly. */
         call    ap_early_traps_init
 
@@ -77,7 +85,9 @@ LABEL(s3_resume)
         wrmsr
 
         /* Enable CR4.CET. */
-        mov     $XEN_MINIMAL_CR4 | X86_CR4_CET, %ecx
+        mov     $X86_CR4_CET, %ecx
+        or      STACK_CPUINFO_FIELD(cr4)(%r15), %rcx
+        mov     %rcx, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rcx, %cr4
 
         /* WARNING! call/ret now fatal (iff SHSTK) until SETSSBSY loads SSP */
@@ -120,9 +130,9 @@ LABEL(s3_resume)
 .L_cet_done:
 #endif /* CONFIG_XEN_SHSTK || CONFIG_XEN_IBT */
 
-        /* Restore CR4 from the cpuinfo block. */
-        GET_STACK_END(bx)
-        mov     STACK_CPUINFO_FIELD(cr4)(%rbx), %rax
+        /* Load all CR4 settings. */
+        mov     mmu_cr4_features(%rip), %rax
+        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rax, %cr4
 
         call    mtrr_bp_restore
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 0dfcc8a88a40..631ea2f8236e 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -11,16 +11,19 @@ ENTRY(__high_start)
         mov     %ecx,%gs
         mov     %ecx,%ss
 
-        /* Enable minimal CR4 features. */
-        mov     $XEN_MINIMAL_CR4,%rcx
-        mov     %rcx,%cr4
-
         mov     stack_start(%rip),%rsp
 
         /* Reset EFLAGS (subsumes CLI and CLD). */
         pushq   $0
         popf
 
+        GET_STACK_END(15)
+
+        /* Enable minimal CR4 features. */
+        mov     $XEN_MINIMAL_CR4, %eax
+        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
+        mov     %rax, %cr4
+
         /* Reload code selector. */
         pushq   $__HYPERVISOR_CS
         leaq    1f(%rip),%rax
@@ -45,7 +48,9 @@ ENTRY(__high_start)
         wrmsr
 
         /* Enable CR4.CET. */
-        mov     $XEN_MINIMAL_CR4 | X86_CR4_CET, %ecx
+        mov     $X86_CR4_CET, %ecx
+        or      STACK_CPUINFO_FIELD(cr4)(%r15), %rcx
+        mov     %rcx, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rcx, %cr4
 
         /* WARNING! call/ret now fatal (iff SHSTK) until SETSSBSY loads SSP */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 13/22] x86: FRED enumerations
Date: Fri,  8 Aug 2025 21:23:05 +0100
Message-Id: <20250808202314.1045968-14-andrew.cooper3@citrix.com>
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Of note, CR4.FRED is bit 32 and cannot enabled outside of 64bit mode.

Most supported toolchains don't understand the FRED instructions yet.  ERETU
and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC), while LKGS is
more complicated and deferred for now.

I have intentionally named the FRED MSRs differently to the spec.  In the
spec, the stack pointer names alias the TSS fields of the same name, despite
very different semantics.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/Kconfig                        |  4 ++++
 xen/arch/x86/include/asm/asm-defns.h        |  9 +++++++++
 xen/arch/x86/include/asm/cpufeature.h       |  3 +++
 xen/arch/x86/include/asm/msr-index.h        | 11 +++++++++++
 xen/arch/x86/include/asm/x86-defns.h        |  1 +
 xen/include/public/arch-x86/cpufeatureset.h |  3 +++
 6 files changed, 31 insertions(+)

diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig
index a45ce106e210..90cbad13a7c7 100644
--- a/xen/arch/x86/Kconfig
+++ b/xen/arch/x86/Kconfig
@@ -57,6 +57,10 @@ config HAS_CC_CET_IBT
 	# Retpoline check to work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654
 	def_bool $(cc-option,-fcf-protection=branch -mmanual-endbr -mindirect-branch=thunk-extern) && $(as-instr,endbr64)
 
+config HAS_AS_FRED
+	# binutils >= 2.41 or LLVM >= 19
+	def_bool $(as-instr,eretu;lkgs %ax)
+
 menu "Architecture Features"
 
 source "arch/x86/Kconfig.cpu"
diff --git a/xen/arch/x86/include/asm/asm-defns.h b/xen/arch/x86/include/asm/asm-defns.h
index 61a5faf90446..2e5200b94b82 100644
--- a/xen/arch/x86/include/asm/asm-defns.h
+++ b/xen/arch/x86/include/asm/asm-defns.h
@@ -4,6 +4,15 @@
     .byte 0x0f, 0x01, 0xfc
 .endm
 
+#ifndef CONFIG_HAS_AS_FRED
+.macro eretu
+    .byte 0xf3, 0x0f, 0x01, 0xca
+.endm
+.macro erets
+    .byte 0xf2, 0x0f, 0x01, 0xca
+.endm
+#endif
+
 /*
  * Call a noreturn function.  This could be JMP, but CALL results in a more
  * helpful backtrace.  BUG is to catch functions which do decide to return...
diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h
index 441a7ecc494b..b6cf0c8dfc7c 100644
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -246,6 +246,9 @@ static inline bool boot_cpu_has(unsigned int feat)
 #define cpu_has_avx_vnni        boot_cpu_has(X86_FEATURE_AVX_VNNI)
 #define cpu_has_avx512_bf16     boot_cpu_has(X86_FEATURE_AVX512_BF16)
 #define cpu_has_cmpccxadd       boot_cpu_has(X86_FEATURE_CMPCCXADD)
+#define cpu_has_fred            boot_cpu_has(X86_FEATURE_FRED)
+#define cpu_has_lkgs            boot_cpu_has(X86_FEATURE_LKGS)
+#define cpu_has_nmi_src         boot_cpu_has(X86_FEATURE_NMI_SRC)
 #define cpu_has_avx_ifma        boot_cpu_has(X86_FEATURE_AVX_IFMA)
 
 /* CPUID level 0x80000021.eax */
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 428d993ee89b..bb48d16f0c6d 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -115,6 +115,17 @@
 #define  MCU_OPT_CTRL_GDS_MIT_DIS           (_AC(1, ULL) <<  4)
 #define  MCU_OPT_CTRL_GDS_MIT_LOCK          (_AC(1, ULL) <<  5)
 
+#define MSR_FRED_RSP_SL0                    0x000001cc
+#define MSR_FRED_RSP_SL1                    0x000001cd
+#define MSR_FRED_RSP_SL2                    0x000001ce
+#define MSR_FRED_RSP_SL3                    0x000001cf
+#define MSR_FRED_STK_LVLS                   0x000001d0
+#define MSR_FRED_SSP_SL0                    MSR_PL0_SSP
+#define MSR_FRED_SSP_SL1                    0x000001d1
+#define MSR_FRED_SSP_SL2                    0x000001d2
+#define MSR_FRED_SSP_SL3                    0x000001d3
+#define MSR_FRED_CONFIG                     0x000001d4
+
 #define MSR_RTIT_OUTPUT_BASE                0x00000560
 #define MSR_RTIT_OUTPUT_MASK                0x00000561
 #define MSR_RTIT_CTL                        0x00000570
diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h
index 23579c471f4a..513f18b3be4e 100644
--- a/xen/arch/x86/include/asm/x86-defns.h
+++ b/xen/arch/x86/include/asm/x86-defns.h
@@ -75,6 +75,7 @@
 #define X86_CR4_PKE        0x00400000 /* enable PKE */
 #define X86_CR4_CET        0x00800000 /* Control-flow Enforcement Technology */
 #define X86_CR4_PKS        0x01000000 /* Protection Key Supervisor */
+#define X86_CR4_FRED      0x100000000 /* Fast Return and Event Delivery */
 
 #define X86_CR8_VALID_MASK 0xf
 
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index f7312e0b04e7..9cd778586f10 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -310,7 +310,10 @@ XEN_CPUFEATURE(ARCH_PERF_MON, 10*32+8) /*   Architectural Perfmon */
 XEN_CPUFEATURE(FZRM,         10*32+10) /*A  Fast Zero-length REP MOVSB */
 XEN_CPUFEATURE(FSRS,         10*32+11) /*A  Fast Short REP STOSB */
 XEN_CPUFEATURE(FSRCS,        10*32+12) /*A  Fast Short REP CMPSB/SCASB */
+XEN_CPUFEATURE(FRED,         10*32+17) /*   Fast Return and Event Delivery */
+XEN_CPUFEATURE(LKGS,         10*32+18) /*   Load Kernel GS instruction */
 XEN_CPUFEATURE(WRMSRNS,      10*32+19) /*S  WRMSR Non-Serialising */
+XEN_CPUFEATURE(NMI_SRC,      10*32+20) /*   NMI-Source Reporting */
 XEN_CPUFEATURE(AMX_FP16,     10*32+21) /*   AMX FP16 instruction */
 XEN_CPUFEATURE(AVX_IFMA,     10*32+23) /*A  AVX-IFMA Instructions */
 XEN_CPUFEATURE(LAM,          10*32+26) /*   Linear Address Masking */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper 
Subject: [PATCH 15/22] x86/traps: Introduce opt_fred
Date: Fri,  8 Aug 2025 21:23:07 +0100
Message-Id: <20250808202314.1045968-16-andrew.cooper3@citrix.com>
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... disabled by default.  There is a lot of work before FRED can be enabled by
default.

One part of FRED, the LKGS (Load Kernel GS) instruction, is enumerated
separately but is mandatory as FRED disallows the SWAPGS instruction.
Therefore, both CPUID bits must be checked.

FRED formally removes the use of Ring1 and Ring2, meaning we cannot run 32bit
PV guests.  Therefore, don't enable FRED by default in shim mode.  OTOH, if
FRED is active, then PV32 needs disabling like with CET.

No functional change.

Signed-off-by: Andrew Cooper 
---
 docs/misc/xen-command-line.pandoc | 10 ++++++++++
 xen/arch/x86/include/asm/traps.h  |  4 ++++
 xen/arch/x86/traps-setup.c        | 31 +++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 6865a61220ca..f293d973a8e8 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -1283,6 +1283,16 @@ requirement can be relaxed.  This option is particularly useful for nested
 virtualization, to allow the L1 hypervisor to use EPT even if the L0 hypervisor
 does not provide `VM_ENTRY_LOAD_GUEST_PAT`.
 
+### fred (x86)
+> `= `
+
+> Default: `false`
+
+Flexible Return and Event Delivery is an overhaul of interrupt, exception and
+system call handling, fixing many corner cases in the x86 architecture, and
+expected in hardware from 2025.  Support in Xen is a work in progress and
+disabled by default.
+
 ### gnttab
 > `= List of [ max-ver:, transitive=, transfer= ]`
 
diff --git a/xen/arch/x86/include/asm/traps.h b/xen/arch/x86/include/asm/traps.h
index 6ae451d3fc70..73097e957d05 100644
--- a/xen/arch/x86/include/asm/traps.h
+++ b/xen/arch/x86/include/asm/traps.h
@@ -7,6 +7,10 @@
 #ifndef ASM_TRAP_H
 #define ASM_TRAP_H
 
+#include 
+
+extern int8_t opt_fred;
+
 void bsp_early_traps_init(void);
 void traps_init(void);
 void bsp_traps_reinit(void);
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index 37202c17fcea..3b5e4969a375 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -9,6 +9,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -20,6 +22,9 @@ unsigned int __ro_after_init ler_msr;
 static bool __initdata opt_ler;
 boolean_param("ler", opt_ler);
 
+int8_t __ro_after_init opt_fred = 0; /* -1 when supported. */
+boolean_param("fred", opt_fred);
+
 void nocall entry_PF(void);
 void nocall lstar_enter(void);
 void nocall cstar_enter(void);
@@ -305,6 +310,32 @@ void __init traps_init(void)
     /* Replace early pagefault with real pagefault handler. */
     _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF);
 
+    if ( !cpu_has_fred || !cpu_has_lkgs )
+    {
+        if ( opt_fred )
+            printk(XENLOG_WARNING "FRED not available, ignoring\n");
+        opt_fred = false;
+    }
+
+    if ( opt_fred == -1 )
+        opt_fred = !pv_shim;
+
+    if ( opt_fred )
+    {
+#ifdef CONFIG_PV32
+        if ( opt_pv32 )
+        {
+            opt_pv32 = 0;
+            printk(XENLOG_INFO "Disabling PV32 due to FRED\n");
+        }
+#endif
+        printk("Using FRED event delivery\n");
+    }
+    else
+    {
+        printk("Using IDT event delivery\n");
+    }
+
     load_system_tables();
 
     init_ler();
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 18/22] x86/traps: Set MSR_PL0_SSP in load_system_tables()
Date: Fri,  8 Aug 2025 21:23:10 +0100
Message-Id: <20250808202314.1045968-19-andrew.cooper3@citrix.com>
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FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
means that the value they load into MSR_PL0_SSP differs by 8.

s3_resume() in particular has logic which is otherwise invariant of FRED mode,
and must not clobber a FRED MSR_PL0_SSP with an IDT one.

This also simplifies the AP path too.  Updating reinit_bsp_stack() is deferred
until later.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/acpi/wakeup_prot.S |  9 ---------
 xen/arch/x86/boot/x86_64.S      | 12 +++---------
 xen/arch/x86/traps-setup.c      |  2 ++
 3 files changed, 5 insertions(+), 18 deletions(-)

diff --git a/xen/arch/x86/acpi/wakeup_prot.S b/xen/arch/x86/acpi/wakeup_prot.S
index 6ddc4011d8b6..c800cd28a7c9 100644
--- a/xen/arch/x86/acpi/wakeup_prot.S
+++ b/xen/arch/x86/acpi/wakeup_prot.S
@@ -104,15 +104,6 @@ LABEL(s3_resume)
          */
         mov     saved_ssp(%rip), %rdi
 
-        /* Calculate MSR_PL0_SSP from SSP. */
-        mov     $MSR_PL0_SSP, %ecx
-        mov     %rdi, %rdx
-        shr     $32, %rdx
-        mov     %edi, %eax
-        and     $~(STACK_SIZE - 1), %eax
-        or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %eax
-        wrmsr
-
         /*
          * A Restore Token's value is &token + 8 + 64BIT (bit 0).
          * We want to put this on the shstk at SSP - 8.
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 631ea2f8236e..ebb91d5e3f60 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -65,17 +65,11 @@ ENTRY(__high_start)
         or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %rdx
 
         /*
-         * Write a new supervisor token.  Doesn't matter on boot, but for S3
-         * resume this clears the busy bit.
+         * Write a new Supervisor Token.  It doesn't matter the first time a
+         * CPU boots, but for S3 resume or CPU hot re-add, this clears the
+         * busy bit.
          */
         wrssq   %rdx, (%rdx)
-
-        /* Point MSR_PL0_SSP at the token. */
-        mov     $MSR_PL0_SSP, %ecx
-        mov     %edx, %eax
-        shr     $32, %rdx
-        wrmsr
-
         setssbsy
 
 #endif /* CONFIG_XEN_SHSTK */
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index 3b5e4969a375..c4825fc1b11a 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -96,6 +96,7 @@ static void load_system_tables(void)
     {
         volatile uint64_t *ist_ssp = tss_page->ist_ssp;
         unsigned long
+            ssp = stack_top + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8,
             mce_ssp = stack_top + (IST_MCE * IST_SHSTK_SIZE) - 8,
             nmi_ssp = stack_top + (IST_NMI * IST_SHSTK_SIZE) - 8,
             db_ssp  = stack_top + (IST_DB  * IST_SHSTK_SIZE) - 8,
@@ -122,6 +123,7 @@ static void load_system_tables(void)
         }
 
         wrmsrns(MSR_ISST, (unsigned long)ist_ssp);
+        wrmsrns(MSR_PL0_SSP, (unsigned long)ssp);
     }
 
     _set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 21/22] x86/traps: Introduce FRED entrypoints
Date: Fri,  8 Aug 2025 21:23:13 +0100
Message-Id: <20250808202314.1045968-22-andrew.cooper3@citrix.com>
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Under FRED, there's one entrypoint from Ring 3, and one from Ring 0.

FRED gives us a good stack (even for SYSCALL/SYSENTER), and a unified event
frame on the stack, meaing that all software needs to do is spill the GPRs
with a line of PUSHes.  Introduce PUSH_AND_CLEAR_GPRS and POP_GPRS for this
purpose.

Introduce entry_FRED_R0() which to a first appoximation is complete for all
event handling within Xen.

entry_FRED_R0() needs deriving from entry_FRED_R3(), so introduce a basic
handler.  There is more work required to make the return-to-guest path work
under FRED, so leave a BUG clearly in place.

Also introduce entry_from_{xen,pv}() to be the C level handlers.  By simply
copying regs->fred_ss.vector into regs->entry_vector, we can reuse all the
existing fault handlers.

Extend fatal_trap() to render the event type, including by name, when FRED is
active.  This is slightly complicated, because X86_ET_OTHER must not use
vector_name() or SYSCALL and SYSENTER get rendered as #BP and #DB.  Also,
{read,write}_gs_shadow() needs modifying to avoid the SWAPGS instruction,
which is disallowed in FRED mode.

This is sufficient to handle all interrupts and exceptions encountered during
development, including plenty of Double Faults.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

SIMICS hasn't been updated to the FRED v9, and still wants ENDBR instructions
at the entrypoints.
---
 xen/arch/x86/include/asm/asm_defns.h |  65 ++++++++++++
 xen/arch/x86/include/asm/msr.h       |   8 +-
 xen/arch/x86/traps.c                 | 153 ++++++++++++++++++++++++++-
 xen/arch/x86/x86_64/Makefile         |   1 +
 xen/arch/x86/x86_64/entry-fred.S     |  35 ++++++
 5 files changed, 256 insertions(+), 6 deletions(-)
 create mode 100644 xen/arch/x86/x86_64/entry-fred.S

diff --git a/xen/arch/x86/include/asm/asm_defns.h b/xen/arch/x86/include/asm/asm_defns.h
index 72a0082d319d..a81a4043d0f1 100644
--- a/xen/arch/x86/include/asm/asm_defns.h
+++ b/xen/arch/x86/include/asm/asm_defns.h
@@ -315,6 +315,71 @@ static always_inline void stac(void)
         subq  $-(UREGS_error_code-UREGS_r15+\adj), %rsp
 .endm
 
+/*
+ * Push and clear GPRs
+ */
+.macro PUSH_AND_CLEAR_GPRS
+        push  %rdi
+        xor   %edi, %edi
+        push  %rsi
+        xor   %esi, %esi
+        push  %rdx
+        xor   %edx, %edx
+        push  %rcx
+        xor   %ecx, %ecx
+        push  %rax
+        xor   %eax, %eax
+        push  %r8
+        xor   %r8d, %r8d
+        push  %r9
+        xor   %r9d, %r9d
+        push  %r10
+        xor   %r10d, %r10d
+        push  %r11
+        xor   %r11d, %r11d
+        push  %rbx
+        xor   %ebx, %ebx
+        push  %rbp
+#ifdef CONFIG_FRAME_POINTER
+/* Indicate special exception stack frame by inverting the frame pointer. */
+        mov   %rsp, %rbp
+        notq  %rbp
+#else
+        xor   %ebp, %ebp
+#endif
+        push  %r12
+        xor   %r12d, %r12d
+        push  %r13
+        xor   %r13d, %r13d
+        push  %r14
+        xor   %r14d, %r14d
+        push  %r15
+        xor   %r15d, %r15d
+.endm
+
+/*
+ * POP GPRs from a UREGS_* frame on the stack.  Does not modify flags.
+ *
+ * @rax: Alternative destination for the %rax value on the stack.
+ */
+.macro POP_GPRS rax=%rax
+        pop   %r15
+        pop   %r14
+        pop   %r13
+        pop   %r12
+        pop   %rbp
+        pop   %rbx
+        pop   %r11
+        pop   %r10
+        pop   %r9
+        pop   %r8
+        pop   \rax
+        pop   %rcx
+        pop   %rdx
+        pop   %rsi
+        pop   %rdi
+.endm
+
 #ifdef CONFIG_PV32
 #define CR4_PV32_RESTORE                               \
     ALTERNATIVE_2 "",                                  \
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index b6b85b04c3fd..01f510315ffe 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -202,9 +202,9 @@ static inline unsigned long read_gs_base(void)
 
 static inline unsigned long read_gs_shadow(void)
 {
-    unsigned long base;
+    unsigned long base, cr4 = read_cr4();
 
-    if ( read_cr4() & X86_CR4_FSGSBASE )
+    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
     {
         asm volatile ( "swapgs" );
         base = __rdgsbase();
@@ -234,7 +234,9 @@ static inline void write_gs_base(unsigned long base)
 
 static inline void write_gs_shadow(unsigned long base)
 {
-    if ( read_cr4() & X86_CR4_FSGSBASE )
+    unsigned long cr4 = read_cr4();
+
+    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
     {
         asm volatile ( "swapgs\n\t"
                        "wrgsbase %0\n\t"
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 270b93ed623e..e67a428e4362 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1013,6 +1013,32 @@ void show_execution_state_nmi(const cpumask_t *mask, bool show_all)
         printk("Non-responding CPUs: {%*pbl}\n", CPUMASK_PR(&show_state_mask));
 }
 
+static const char *x86_et_name(unsigned int type)
+{
+    static const char *const names[] = {
+        [X86_ET_EXT_INTR]    = "EXT_INTR",
+        [X86_ET_NMI]         = "NMI",
+        [X86_ET_HW_EXC]      = "HW_EXC",
+        [X86_ET_SW_INT]      = "SW_INT",
+        [X86_ET_PRIV_SW_EXC] = "PRIV_SW_EXEC",
+        [X86_ET_SW_EXC]      = "SW_EXEC",
+        [X86_ET_OTHER]       = "OTHER",
+    };
+
+    return (type < ARRAY_SIZE(names) && names[type]) ? names[type] : "???";
+}
+
+static const char *x86_et_other_name(unsigned int vec)
+{
+    static const char *const names[] = {
+        [0] = "MTF",
+        [1] = "SYSCALL",
+        [2] = "SYSENTER",
+    };
+
+    return (vec < ARRAY_SIZE(names) && names[vec][0]) ? names[vec] : "???";
+}
+
 const char *vector_name(unsigned int vec)
 {
     static const char names[][4] = {
@@ -1091,9 +1117,42 @@ void fatal_trap(const struct cpu_user_regs *regs, bool show_remote)
         }
     }
 
-    panic("FATAL TRAP: vec %u, %s[%04x]%s\n",
-          trapnr, vector_name(trapnr), regs->error_code,
-          (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
+    if ( read_cr4() & X86_CR4_FRED )
+    {
+        bool render_ec = false;
+        const char *vec_name = NULL;
+
+        switch ( regs->fred_ss.type )
+        {
+        case X86_ET_HW_EXC:
+        case X86_ET_SW_INT:
+        case X86_ET_PRIV_SW_EXC:
+        case X86_ET_SW_EXC:
+            render_ec = true;
+            vec_name = vector_name(regs->fred_ss.vector);
+            break;
+
+        case X86_ET_OTHER:
+            vec_name = x86_et_other_name(regs->fred_ss.vector);
+            break;
+        }
+
+        if ( render_ec )
+            panic("Fatal TRAP: type %u, %s, vec %u, %s[%04x]%s\n",
+                  regs->fred_ss.type, x86_et_name(regs->fred_ss.type),
+                  regs->fred_ss.vector, vec_name ?: "",
+                  regs->error_code,
+                  (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
+        else
+            panic("Fatal TRAP: type %u, %s, vec %u, %s%s\n",
+                  regs->fred_ss.type, x86_et_name(regs->fred_ss.type),
+                  regs->fred_ss.vector, vec_name ?: "",
+                  (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
+    }
+    else
+        panic("FATAL TRAP: vec %u, %s[%04x]%s\n",
+              trapnr, vector_name(trapnr), regs->error_code,
+              (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
 }
 
 void asmlinkage noreturn do_unhandled_trap(struct cpu_user_regs *regs)
@@ -2181,6 +2240,94 @@ void asmlinkage check_ist_exit(const struct cpu_user_regs *regs, bool ist_exit)
 }
 #endif
 
+void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
+{
+    /* Copy fred_ss.vector into entry_vector as IDT delivery would have done. */
+    regs->entry_vector = regs->fred_ss.vector;
+
+    switch ( regs->fred_ss.type )
+    {
+    case X86_ET_EXT_INTR:
+        do_IRQ(regs);
+        break;
+
+    case X86_ET_NMI:
+        do_nmi(regs);
+        break;
+
+    case X86_ET_HW_EXC:
+    case X86_ET_SW_INT:
+    case X86_ET_PRIV_SW_EXC:
+    case X86_ET_SW_EXC:
+        goto fatal;
+
+    default:
+        goto fatal;
+    }
+
+    return;
+
+ fatal:
+    fatal_trap(regs, false);
+}
+
+void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
+{
+    /* Copy fred_ss.vector into entry_vector as IDT delivery would have done. */
+    regs->entry_vector = regs->fred_ss.vector;
+
+    switch ( regs->fred_ss.type )
+    {
+    case X86_ET_EXT_INTR:
+        do_IRQ(regs);
+        break;
+
+    case X86_ET_NMI:
+        do_nmi(regs);
+        break;
+
+    case X86_ET_HW_EXC:
+    case X86_ET_SW_INT:
+    case X86_ET_PRIV_SW_EXC:
+    case X86_ET_SW_EXC:
+        switch ( regs->fred_ss.vector )
+        {
+        case X86_EXC_PF:  do_page_fault(regs); break;
+        case X86_EXC_GP:  do_general_protection(regs); break;
+        case X86_EXC_UD:  do_invalid_op(regs); break;
+        case X86_EXC_NM:  do_device_not_available(regs); break;
+        case X86_EXC_BP:  do_int3(regs); break;
+        case X86_EXC_DB:  do_debug(regs); break;
+        case X86_EXC_DF:  do_double_fault(regs); break;
+
+        case X86_EXC_DE:
+        case X86_EXC_OF:
+        case X86_EXC_BR:
+        case X86_EXC_NP:
+        case X86_EXC_SS:
+        case X86_EXC_MF:
+        case X86_EXC_AC:
+        case X86_EXC_XM:
+            do_trap(regs);
+            break;
+
+        case X86_EXC_CP:  do_entry_CP(regs); break;
+
+        default:
+            goto fatal;
+        }
+        break;
+
+    default:
+        goto fatal;
+    }
+
+    return;
+
+ fatal:
+    fatal_trap(regs, false);
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/xen/arch/x86/x86_64/Makefile b/xen/arch/x86/x86_64/Makefile
index f20763088740..5ec933539adb 100644
--- a/xen/arch/x86/x86_64/Makefile
+++ b/xen/arch/x86/x86_64/Makefile
@@ -1,6 +1,7 @@
 obj-$(CONFIG_PV32) += compat/
 
 obj-bin-y += entry.o
+obj-bin-y += entry-fred.o
 obj-$(CONFIG_KEXEC) += machine_kexec.o
 obj-y += pci.o
 obj-y += acpi_mmcfg.o
diff --git a/xen/arch/x86/x86_64/entry-fred.S b/xen/arch/x86/x86_64/entry-fred.S
new file mode 100644
index 000000000000..88d262b91f92
--- /dev/null
+++ b/xen/arch/x86/x86_64/entry-fred.S
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+        .file "x86_64/entry-fred.S"
+
+#include 
+#include 
+
+        .section .text.entry, "ax", @progbits
+
+        /* The Ring3 entry point is required to be 4k aligned. */
+
+FUNC(entry_FRED_R3, 4096)
+        PUSH_AND_CLEAR_GPRS
+
+        mov     %rsp, %rdi
+        call    entry_from_pv
+
+        BUG     /* TODO - return to guest path */
+
+        POP_GPRS
+        eretu
+END(entry_FRED_R3)
+
+        /* The Ring0 entrypoint is at Ring3 + 256. */
+        .org entry_FRED_R3 + 256, 0xcc
+
+FUNC_LOCAL(entry_FRED_R0, 0)
+        PUSH_AND_CLEAR_GPRS
+
+        mov     %rsp, %rdi
+        call    entry_from_xen
+
+        POP_GPRS
+        erets
+END(entry_FRED_R0)
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 22/22] x86/traps: Enable FRED when requested
Date: Fri,  8 Aug 2025 21:23:14 +0100
Message-Id: <20250808202314.1045968-23-andrew.cooper3@citrix.com>
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With the shadow stack and exception handling adjustements in place, we can now
activate FRED when appropriate.  Note that opt_fred is still disabled by
default.

Introduce init_fred() to set up all the MSRs relevant for FRED.  FRED uses
MSR_STAR (entries from Ring3 only), and MSR_FRED_SSP_SL0 aliases MSR_PL0_SSP
when CET-SS is active.  Otherwise, they're all new MSRs.

With init_fred() existing, load_system_tables() and legacy_syscall_init()
should only be used when setting up IDT delivery.  Insert ASSERT()s to this
effect, and adjust the various *_init() functions to make this property true.

Per the documentation, ap_early_traps_init() is responsible for switching off
the boot GDT, which needs doing even in FRED mode.

Finally, set CR4.FRED in {bsp,ap}_early_traps_init().

Xen can now boot in FRED mode up until starting a PV guest, where it faults
because IRET is not permitted to change privilege.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

In principle we can stop allocating the IDT and TSS for CPUs now, although I
want to get shutdown and kexec working before making this optimisation, in
case there's something I've overlooked.
---
 xen/arch/x86/include/asm/current.h |  3 ++
 xen/arch/x86/traps-setup.c         | 78 +++++++++++++++++++++++++++---
 2 files changed, 75 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index 24d7d906a8c6..046740447db0 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -24,6 +24,9 @@
  * 2 - NMI IST stack
  * 1 - #MC IST stack
  * 0 - IST Shadow Stacks (4x 1k, read-only)
+ *
+ * In FRED mode, #DB and NMI do not need special stacks, so their stacks are
+ * unused.
  */
 
 /*
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index c4825fc1b11a..fdcfc7f5777d 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -26,6 +26,7 @@ int8_t __ro_after_init opt_fred = 0; /* -1 when supported. */
 boolean_param("fred", opt_fred);
 
 void nocall entry_PF(void);
+void nocall entry_FRED_R3(void);
 void nocall lstar_enter(void);
 void nocall cstar_enter(void);
 
@@ -63,6 +64,8 @@ static void load_system_tables(void)
         .limit = sizeof(bsp_idt) - 1,
     };
 
+    ASSERT(opt_fred == 0);
+
     /*
      * Set up the TSS.  Warning - may be live, and the NMI/#MC must remain
      * valid on every instruction boundary.  (Note: these are all
@@ -197,6 +200,8 @@ static void legacy_syscall_init(void)
     unsigned char *stub_page;
     unsigned int offset;
 
+    ASSERT(opt_fred == 0);
+
     /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
     if ( !IS_ENABLED(CONFIG_PV) )
         return;
@@ -274,6 +279,44 @@ static void __init init_ler(void)
     setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
 }
 
+/*
+ * Set up all MSRs relevant for FRED event delivery.
+ *
+ * Xen does not use any of the optional config in MSR_FRED_CONFIG, so all that
+ * is needed is the entrypoint.
+ *
+ * Because FRED always provides a good stack, NMI and #DB do not need any
+ * special treatment.  Only #DF needs another stack level, and #MC for the
+ * offchance that Xen's main stack suffers an uncorrectable error.
+ *
+ * FRED reuses MSR_STAR to provide the segment selector values to load on
+ * entry from Ring3.  Entry from Ring0 leave %cs and %ss unmodified.
+ */
+static void init_fred(void)
+{
+    unsigned long stack_top = get_stack_bottom() & ~(STACK_SIZE - 1);
+
+    ASSERT(opt_fred == 1);
+
+    wrmsrns(MSR_STAR, XEN_MSR_STAR);
+    wrmsrns(MSR_FRED_CONFIG, (unsigned long)entry_FRED_R3);
+
+    wrmsrns(MSR_FRED_RSP_SL0, (unsigned long)(&get_cpu_info()->_fred + 1));
+    wrmsrns(MSR_FRED_RSP_SL1, 0);
+    wrmsrns(MSR_FRED_RSP_SL2, stack_top + (1 + IST_MCE)  * PAGE_SIZE);
+    wrmsrns(MSR_FRED_RSP_SL3, stack_top + (1 + IST_DF)   * PAGE_SIZE);
+    wrmsrns(MSR_FRED_STK_LVLS, ((2UL << (X86_EXC_MC * 2)) |
+                                (3UL << (X86_EXC_DF * 2))));
+
+    if ( cpu_has_xen_shstk )
+    {
+        wrmsrns(MSR_FRED_SSP_SL0, stack_top + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE);
+        wrmsrns(MSR_FRED_SSP_SL1, 0);
+        wrmsrns(MSR_FRED_SSP_SL2, stack_top + (IST_MCE * IST_SHSTK_SIZE));
+        wrmsrns(MSR_FRED_SSP_SL3, stack_top + (IST_DF  * IST_SHSTK_SIZE));
+    }
+}
+
 /*
  * Configure basic exception handling.  This is prior to parsing the command
  * line or configuring a console, and needs to be as simple as possible.
@@ -331,15 +374,18 @@ void __init traps_init(void)
             printk(XENLOG_INFO "Disabling PV32 due to FRED\n");
         }
 #endif
+        init_fred();
+        set_in_cr4(X86_CR4_FRED);
+
         printk("Using FRED event delivery\n");
     }
     else
     {
+        load_system_tables();
+
         printk("Using IDT event delivery\n");
     }
 
-    load_system_tables();
-
     init_ler();
 
     /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
@@ -357,8 +403,13 @@ void __init traps_init(void)
  */
 void bsp_traps_reinit(void)
 {
-    load_system_tables();
-    percpu_traps_init();
+    if ( opt_fred )
+        init_fred();
+    else
+    {
+        load_system_tables();
+        percpu_traps_init();
+    }
 }
 
 /*
@@ -367,7 +418,8 @@ void bsp_traps_reinit(void)
  */
 void percpu_traps_init(void)
 {
-    legacy_syscall_init();
+    if ( !opt_fred )
+        legacy_syscall_init();
 
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
@@ -382,7 +434,21 @@ void percpu_traps_init(void)
  */
 void asmlinkage ap_early_traps_init(void)
 {
-    load_system_tables();
+    if ( opt_fred )
+    {
+        const seg_desc_t *gdt = this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY;
+        const struct desc_ptr gdtr = {
+            .base = (unsigned long)gdt,
+            .limit = LAST_RESERVED_GDT_BYTE,
+        };
+
+        lgdt(&gdtr);
+
+        init_fred();
+        write_cr4(read_cr4() | X86_CR4_FRED);
+    }
+    else
+        load_system_tables();
 }
 
 static void __init __maybe_unused build_assertions(void)
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 20/22] x86/traps: Alter switch_stack_and_jump() for FRED mode
Date: Fri,  8 Aug 2025 21:23:12 +0100
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FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
means that switch_stack_and_jump() needs to discard one extra word when FRED
is active.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

RFC.  I don't like this, but it does work.

This emits opt_fred logic outside of CONFIG_XEN_SHSTK.  But frankly, the
construct is already too unweildly, and all options I can think of make it
moreso.
---
 xen/arch/x86/include/asm/current.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index 962eb76a82b3..24d7d906a8c6 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -11,6 +11,7 @@
 #include 
 
 #include 
+#include 
 
 /*
  * Xen's cpu stacks are 8 pages (8-page aligned), arranged as:
@@ -154,7 +155,6 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
     "rdsspd %[ssp];"                                            \
     "cmp $1, %[ssp];"                                           \
     "je .L_shstk_done.%=;" /* CET not active?  Skip. */         \
-    "mov $%c[skstk_base], %[val];"                              \
     "and $%c[stack_mask], %[ssp];"                              \
     "sub %[ssp], %[val];"                                       \
     "shr $3, %[val];"                                           \
@@ -177,6 +177,8 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
 
 #define switch_stack_and_jump(fn, instr, constr)                        \
     ({                                                                  \
+        unsigned int token_offset =                                     \
+            (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - (opt_fred ? 0 : 8);  \
         unsigned int tmp;                                               \
         BUILD_BUG_ON(!ssaj_has_attr_noreturn(fn));                      \
         __asm__ __volatile__ (                                          \
@@ -184,12 +186,11 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
             "mov %[stk], %%rsp;"                                        \
             CHECK_FOR_LIVEPATCH_WORK                                    \
             instr "[fun]"                                               \
-            : [val] "=&r" (tmp),                                        \
+            : [val] "=r" (tmp),                                         \
               [ssp] "=&r" (tmp)                                         \
             : [stk] "r" (guest_cpu_user_regs()),                        \
               [fun] constr (fn),                                        \
-              [skstk_base] "i"                                          \
-              ((PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8),               \
+              "[val]" (token_offset),                                   \
               [stack_mask] "i" (STACK_SIZE - 1),                        \
               _ASM_BUGFRAME_INFO(BUGFRAME_bug, __LINE__,                \
                                  __FILE__, NULL)                        \
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 17/22] x86/S3: Switch to using RSTORSSP to recover SSP on resume
Date: Fri,  8 Aug 2025 21:23:09 +0100
Message-Id: <20250808202314.1045968-18-andrew.cooper3@citrix.com>
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Under FRED, SETSSBSY is unavailable, and we want to be setting up FRED prior
to setting up shadow stacks.  Luckily, RSTORSSP will also work in this case.

This involves a new type of shadow stack token, the Restore Token, which is
distinguished from the Supervisor Token by pointing to the adjacent slot on
the shadow stack rather than pointing at itself.

In the short term, this logic still needs to load MSR_PL0_SSP.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/acpi/wakeup_prot.S | 31 +++++++++++++++----------------
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/xen/arch/x86/acpi/wakeup_prot.S b/xen/arch/x86/acpi/wakeup_prot.S
index dfc8c6ac6e8c..6ddc4011d8b6 100644
--- a/xen/arch/x86/acpi/wakeup_prot.S
+++ b/xen/arch/x86/acpi/wakeup_prot.S
@@ -90,7 +90,7 @@ LABEL(s3_resume)
         mov     %rcx, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rcx, %cr4
 
-        /* WARNING! call/ret now fatal (iff SHSTK) until SETSSBSY loads SSP */
+        /* WARNING! CALL/RET now fatal (iff SHSTK) until RSTORSSP loads SSP */
 
 #if defined(CONFIG_XEN_SHSTK)
         test    $CET_SHSTK_EN, %al
@@ -98,32 +98,31 @@ LABEL(s3_resume)
 
         /*
          * Restoring SSP is a little complicated, because we are intercepting
-         * an in-use shadow stack.  Write a temporary token under the stack,
-         * so SETSSBSY will successfully load a value useful for us, then
-         * reset MSR_PL0_SSP to its usual value and pop the temporary token.
+         * an in-use shadow stack.  Write a Restore Token under the stack, and
+         * use RSTORSSP to load it.  RSTORSSP converts the token to a
+         * Previous-SSP Token, which we discard.
          */
         mov     saved_ssp(%rip), %rdi
 
-        /* Construct the temporary supervisor token under SSP. */
-        sub     $8, %rdi
-
-        /* Load it into MSR_PL0_SSP. */
+        /* Calculate MSR_PL0_SSP from SSP. */
         mov     $MSR_PL0_SSP, %ecx
         mov     %rdi, %rdx
         shr     $32, %rdx
         mov     %edi, %eax
-        wrmsr
-
-        /* Write the temporary token onto the shadow stack, and activate it. */
-        wrssq   %rdi, (%rdi)
-        setssbsy
-
-        /* Reset MSR_PL0_SSP back to its normal value. */
         and     $~(STACK_SIZE - 1), %eax
         or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %eax
         wrmsr
 
-        /* Pop the temporary token off the stack. */
+        /*
+         * A Restore Token's value is &token + 8 + 64BIT (bit 0).
+         * We want to put this on the shstk at SSP - 8.
+         */
+        lea     1(%rdi), %rax
+        sub     $8, %rdi
+        wrssq   %rax, (%rdi)
+        rstorssp (%rdi)
+
+        /* Discard the Previous-SSP Token from the shstk. */
         mov     $2, %eax
         incsspd %eax
 #endif /* CONFIG_XEN_SHSTK */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 19/22] x86/boot: Use RSTORSSP to establish SSP
Date: Fri,  8 Aug 2025 21:23:11 +0100
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Under FRED, SETSSBSY is unavailable, and we want to be setting up FRED prior
to setting up shadow stacks.  As we still need Supervisor Tokens in IDT mode,
we need mode-specific logic to establish SSP.

In FRED mode, write a Restore Token, RSTORSSP it, and discard the resulting
Previous-SSP token.

No change outside of FRED mode.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/boot/x86_64.S | 23 +++++++++++++++++++++--
 xen/arch/x86/setup.c       | 27 ++++++++++++++++++++++++---
 2 files changed, 45 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index ebb91d5e3f60..138501f52158 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -53,17 +53,21 @@ ENTRY(__high_start)
         mov     %rcx, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rcx, %cr4
 
-        /* WARNING! call/ret now fatal (iff SHSTK) until SETSSBSY loads SSP */
+        /* WARNING! CALL/RET now fatal (iff SHSTK) until SETSSBSY/RSTORSSP loads SSP */
 
 #if defined(CONFIG_XEN_SHSTK)
         test    $CET_SHSTK_EN, %al
         jz      .L_ap_cet_done
 
-        /* Derive the supervisor token address from %rsp. */
+        /* Derive the token address from %rsp. */
         mov     %rsp, %rdx
         and     $~(STACK_SIZE - 1), %rdx
         or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %rdx
 
+        /* Establishing SSP depends on whether we're using FRED or IDT mode. */
+        bt      $32 /* ilog2(X86_CR4_FRED) */, %rcx
+        jc      .L_fred_shstk
+
         /*
          * Write a new Supervisor Token.  It doesn't matter the first time a
          * CPU boots, but for S3 resume or CPU hot re-add, this clears the
@@ -71,6 +75,21 @@ ENTRY(__high_start)
          */
         wrssq   %rdx, (%rdx)
         setssbsy
+        jmp     .L_ap_cet_done
+
+.L_fred_shstk:
+
+        /*
+         * Write a Restore Token, value: &token + 8 + * 64BIT (bit 0) at the
+         * base of the shstk (which isn't in use yet).
+         */
+        lea     9(%rdx), %rdi
+        wrssq   %rdi, (%rdx)
+        rstorssp (%rdx)
+
+        /* Discard the Previous-SSP Token from the shstk. */
+        mov     $2, %edx
+        incsspd %edx
 
 #endif /* CONFIG_XEN_SHSTK */
 .L_ap_cet_done:
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 6fb42c5a5f95..c5dd2051dffe 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -53,6 +53,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -912,10 +913,30 @@ static void __init noreturn reinit_bsp_stack(void)
 
     if ( cpu_has_xen_shstk )
     {
-        wrmsrl(MSR_PL0_SSP,
-               (unsigned long)stack + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8);
         wrmsrl(MSR_S_CET, xen_msr_s_cet_value());
-        asm volatile ("setssbsy" ::: "memory");
+
+        /*
+         * IDT and FRED differ by a Supervisor Token on the shadow stack, and
+         * therefore by the value in MSR_PL0_SSP.
+         *
+         * In IDT mode, we use SETSSBSY to mark the Supervisor Token as busy.
+         * In FRED mode, there is no token, so we need a transient Restore
+         * Token to establish SSP.
+         */
+        if ( opt_fred )
+        {
+            unsigned long *token =
+                (void *)stack + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8;
+
+            wrss((unsigned long)token + 9, token);
+            asm volatile ( "rstorssp %0" : "+m" (*token) );
+            /*
+             * We need to discard the resulting Previous-SSP Token, but
+             * reset_stack_and_jump() will do that for us.
+             */
+        }
+        else
+            asm volatile ( "setssbsy" ::: "memory" );
     }
 
     reset_stack_and_jump(init_done);
-- 
2.39.5



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From: Nicola Vetrini 
To: xen-devel@lists.xenproject.org
Cc: sstabellini@kernel.org,
	consulting@bugseng.com,
	dmytro_prokopchuk1@epam.com,
	andrew.cooper3@citrix.com,
	jbeulich@suse.com,
	Nicola Vetrini ,
	Doug Goldstein 
Subject: [XEN PATCH 2/2] Address violation of MISRA C Rule 13.1 involving asm side effects.
Date: Fri,  8 Aug 2025 23:40:47 +0200
Message-ID: 
X-Mailer: git-send-email 2.43.0
In-Reply-To: <1283be3b76d76814af244bbca544f6a3b74a04de.1754689062.git.nicola.vetrini@bugseng.com>
References: <1283be3b76d76814af244bbca544f6a3b74a04de.1754689062.git.nicola.vetrini@bugseng.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

The rule states: "Initializer lists shall not contain persistent side effects".
The specific way in which the 'mrs' instruction is used does not lead to
visible side effects for the surrounding code.

Signed-off-by: Nicola Vetrini 
---
Not yet tested on the Xen ECLAIR runner, as the syntax used in the deviation
is only supported after updating the runner.

What the tool is reporting is that due to the '=r' constraint and the
semantics of the instruction, there is the side effect of writing to '_r',
but this is not observable outside the stmt expr. The deviation ends up being
a bit too general for my taste, but the restriction on the actual istruction
should be enough to limit applicability to cases that are arguably safe in
practice.

An alternative approach would be represented by stating that side effects in
'READ_SYSREG64' are safe, but this is not true in general.
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/eclair_analysis/ECLAIR/deviations.ecl
index ec0cac797e5f..6b492e38505d 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -437,6 +437,10 @@ write or not"
 # Series 13
 #
 
+-doc_begin="Consider the asm instruction to read an Arm system register to have no side effects."
+-asm_properties+={"asm(any())&&child(text, ast_field(value,^mrs\\s+%0.*$))", {no_side_effect}}
+-doc_end
+
 -doc_begin="All developers and reviewers can be safely assumed to be well aware
 of the short-circuit evaluation strategy of such logical operators."
 -config=MC3A2.R13.5,reports+={disapplied,"any()"}
-- 
2.43.0



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From: Nicola Vetrini 
To: xen-devel@lists.xenproject.org
Cc: sstabellini@kernel.org,
	consulting@bugseng.com,
	dmytro_prokopchuk1@epam.com,
	andrew.cooper3@citrix.com,
	jbeulich@suse.com,
	Nicola Vetrini ,
	Doug Goldstein 
Subject: [XEN PATCH 1/2] automation/eclair: ECLAIR configuration changes due to GitLab runner update
Date: Fri,  8 Aug 2025 23:40:46 +0200
Message-ID: <1283be3b76d76814af244bbca544f6a3b74a04de.1754689062.git.nicola.vetrini@bugseng.com>
X-Mailer: git-send-email 2.43.0
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Update configurations to adapt to the new syntax used by the newer
version of the tool in the GitLab runner.

No functional changes.

Signed-off-by: Nicola Vetrini 
---
This will of course need coordination with me to update the runners
just before committing the patches, as any analysis done in between will
fail due to syntax errors in the tool configuration files.
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/eclair_analysis/ECLAIR/deviations.ecl
index ebce1ceab912..ec0cac797e5f 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -536,8 +536,8 @@ safe."
 -config=MC3A2.R16.3,reports+={safe, "any_area(end_loc(any_exp(text(^(?s).*/\\* [fF]all ?through\\.? \\*/.*$,0..2))))"}
 -doc_end
 
--doc_begin="Switch statements having a controlling expression of enum type deliberately do not have a default case: gcc -Wall enables -Wswitch which warns (and breaks the build as we use -Werror) if one of the enum labels is missing from the switch."
--config=MC3A2.R16.4,reports+={deliberate,'any_area(kind(context)&&^.* has no `default.*$&&stmt(node(switch_stmt)&&child(cond,skip(__non_syntactic_paren_stmts,type(canonical(enum_underlying_type(any())))))))'}
+-doc_begin="Switch statements having a controlling expression of enum type deliberately do not have a default case: gcc -Wall enables -Wswitch which warns (and breaks the build as -Werror is used) if one of the enumeration values is missing from the switch."
+-config=MC3A2.R16.4,reports+={deliberate,"any_area(kind(context)&&^.* has no `default.*$&&stmt(node(switch_stmt)&&child(cond,skip(__non_syntactic_paren_stmts,ref(enum_underlying_type(any()))))))"}
 -doc_end
 
 -doc_begin="A switch statement with a single switch clause and no default label may be used in place of an equivalent if statement if it is considered to improve readability."
@@ -596,10 +596,10 @@ in assignments; (5) as initializers, possibly designated, in initalizer lists;
 -config=MC3A2.R20.7,expansion_context=
 {safe, "context(__call_expr_arg_contexts)"},
 {safe, "left_right(^[(,\\[]$,^[),\\]]$)"},
-{safe, "context(skip_to(__expr_non_syntactic_contexts, stmt_child(node(array_subscript_expr), subscript)))"},
-{safe, "context(skip_to(__expr_non_syntactic_contexts, stmt_child(operator(assign), lhs)))"},
-{safe, "context(skip_to(__expr_non_syntactic_contexts, stmt_child(node(init_list_expr||designated_init_expr), init)))"},
-{safe, "context(skip_to(__expr_non_syntactic_contexts, stmt_child(node(case_stmt), lower||upper)))"}
+{safe, "context(skip(__expr_non_syntactic_contexts, is(subscript)&&node(array_subscript_expr)))"},
+{safe, "context(skip(__expr_non_syntactic_contexts, is(lhs)&&stmt(operator(assign))))"},
+{safe, "context(skip(__expr_non_syntactic_contexts, is(init)&&node(init_list_expr||designated_init_expr)))"},
+{safe, "context(skip(__expr_non_syntactic_contexts, is(lower||upper)&&node(case_stmt)))"}
 -doc_end
 
 -doc_begin="Violations involving the __config_enabled macros cannot be fixed without
-- 
2.43.0



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Date: Fri, 8 Aug 2025 22:43:46 +0100
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Subject: Re: [XEN PATCH 1/2] automation/eclair: ECLAIR configuration changes
 due to GitLab runner update
To: Nicola Vetrini ,
 xen-devel@lists.xenproject.org
Cc: sstabellini@kernel.org, consulting@bugseng.com,
 dmytro_prokopchuk1@epam.com, jbeulich@suse.com,
 Doug Goldstein 
References: <1283be3b76d76814af244bbca544f6a3b74a04de.1754689062.git.nicola.vetrini@bugseng.com>
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In-Reply-To: <1283be3b76d76814af244bbca544f6a3b74a04de.1754689062.git.nicola.vetrini@bugseng.com>
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On 08/08/2025 10:40 pm, Nicola Vetrini wrote:
> Update configurations to adapt to the new syntax used by the newer
> version of the tool in the GitLab runner.
>
> No functional changes.
>
> Signed-off-by: Nicola Vetrini 
> ---
> This will of course need coordination with me to update the runners
> just before committing the patches, as any analysis done in between will
> fail due to syntax errors in the tool configuration files.

Acked-by: Andrew Cooper 


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Date: Fri, 08 Aug 2025 23:48:11 +0200
From: Nicola Vetrini 
To: xen-devel@lists.xenproject.org
Cc: sstabellini@kernel.org, consulting@bugseng.com,
 dmytro_prokopchuk1@epam.com, andrew.cooper3@citrix.com, jbeulich@suse.com,
 Doug Goldstein 
Subject: Re: [XEN PATCH 1/2] automation/eclair: ECLAIR configuration changes
 due to GitLab runner update
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On 2025-08-08 23:40, Nicola Vetrini wrote:
> Update configurations to adapt to the new syntax used by the newer
> version of the tool in the GitLab runner.
> 

Sorry, forgot to include the cover letter. See below.

 From c4da2554d94c3f7bd4b1e460dcaa27db382ece2f Mon Sep 17 00:00:00 2001
Message-ID: 
 From: Nicola Vetrini 
Date: Fri, 8 Aug 2025 23:43:08 +0200
Subject: [XEN PATCH 0/2] Update ECLAIR runner and address MISRA 
violations

The first patch of the series contains the necessary updates to the
ECLAIR syntax needed to run the updated runners. The change was
motivated by usage of the new syntax in a deviation that is part of the
second patch.

As a result, the runners should be updated either just before or just
after committing the patches.

These have not been properly tested yet on an ECLAIR analysis of Xen, 
but
I sent the patches to get some feedback first and then coordinate with
maintainers to take the needed action once agreed on the approach.

Nicola Vetrini (2):
   automation/eclair: ECLAIR configuration changes due to GitLab runner
     update
   Address violation of MISRA C Rule 13.1 involving asm side effects.

  automation/eclair_analysis/ECLAIR/deviations.ecl | 16 ++++++++++------
  1 file changed, 10 insertions(+), 6 deletions(-)

-- 
2.43.0


> No functional changes.
> 
> Signed-off-by: Nicola Vetrini 
> ---
> This will of course need coordination with me to update the runners
> just before committing the patches, as any analysis done in between 
> will
> fail due to syntax errors in the tool configuration files.
> ---
>  automation/eclair_analysis/ECLAIR/deviations.ecl | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl 
> b/automation/eclair_analysis/ECLAIR/deviations.ecl
> index ebce1ceab912..ec0cac797e5f 100644
> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -536,8 +536,8 @@ safe."
>  -config=MC3A2.R16.3,reports+={safe, 
> "any_area(end_loc(any_exp(text(^(?s).*/\\* [fF]all ?through\\.? 
> \\*/.*$,0..2))))"}
>  -doc_end
> 
> --doc_begin="Switch statements having a controlling expression of enum 
> type deliberately do not have a default case: gcc -Wall enables 
> -Wswitch which warns (and breaks the build as we use -Werror) if one of 
> the enum labels is missing from the switch."
> --config=MC3A2.R16.4,reports+={deliberate,'any_area(kind(context)&&^.* 
> has no 
> `default.*$&&stmt(node(switch_stmt)&&child(cond,skip(__non_syntactic_paren_stmts,type(canonical(enum_underlying_type(any())))))))'}
> +-doc_begin="Switch statements having a controlling expression of enum 
> type deliberately do not have a default case: gcc -Wall enables 
> -Wswitch which warns (and breaks the build as -Werror is used) if one 
> of the enumeration values is missing from the switch."
> +-config=MC3A2.R16.4,reports+={deliberate,"any_area(kind(context)&&^.* 
> has no 
> `default.*$&&stmt(node(switch_stmt)&&child(cond,skip(__non_syntactic_paren_stmts,ref(enum_underlying_type(any()))))))"}
>  -doc_end
> 
>  -doc_begin="A switch statement with a single switch clause and no 
> default label may be used in place of an equivalent if statement if it 
> is considered to improve readability."
> @@ -596,10 +596,10 @@ in assignments; (5) as initializers, possibly 
> designated, in initalizer lists;
>  -config=MC3A2.R20.7,expansion_context=
>  {safe, "context(__call_expr_arg_contexts)"},
>  {safe, "left_right(^[(,\\[]$,^[),\\]]$)"},
> -{safe, "context(skip_to(__expr_non_syntactic_contexts, 
> stmt_child(node(array_subscript_expr), subscript)))"},
> -{safe, "context(skip_to(__expr_non_syntactic_contexts, 
> stmt_child(operator(assign), lhs)))"},
> -{safe, "context(skip_to(__expr_non_syntactic_contexts, 
> stmt_child(node(init_list_expr||designated_init_expr), init)))"},
> -{safe, "context(skip_to(__expr_non_syntactic_contexts, 
> stmt_child(node(case_stmt), lower||upper)))"}
> +{safe, "context(skip(__expr_non_syntactic_contexts, 
> is(subscript)&&node(array_subscript_expr)))"},
> +{safe, "context(skip(__expr_non_syntactic_contexts, 
> is(lhs)&&stmt(operator(assign))))"},
> +{safe, "context(skip(__expr_non_syntactic_contexts, 
> is(init)&&node(init_list_expr||designated_init_expr)))"},
> +{safe, "context(skip(__expr_non_syntactic_contexts, 
> is(lower||upper)&&node(case_stmt)))"}
>  -doc_end
> 
>  -doc_begin="Violations involving the __config_enabled macros cannot be 
> fixed without

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH] RFC x86/msr: Use WRMSRNS $imm when available
Date: Fri,  8 Aug 2025 23:20:13 +0100
Message-Id: <20250808222013.1071291-1-andrew.cooper3@citrix.com>
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Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

This is on top of the FRED series for the wrmsrns() cleanup, but otherwise
unrelated.

The code generation isn't entirely ideal

  Function                                     old     new   delta
  init_fred                                    255     274     +19
  vmx_set_reg                                  248     256      +8
  enter_state_helper.cold                     1014    1018      +4
  __start_xen                                 8893    8897      +4

but made worse by the the prior codegen for wrmsrns(MSR_STAR, ...) being mad:

  mov    $0xc0000081,%ecx
  mov    $0xe023e008,%edx
  movabs $0xe023e00800000000,%rax
  cs wrmsr

The two sources of code expansion come from the compiler not being able to
construct %eax and %edx separately, and not being able propagate constants.

Loading 0 is possibly common enough to warrant another specialisation where we
can use "a" (0), "d" (0) and forgo the MOV+SHR.

I'm probably overthinking things.  The addition will be in the noise in
practice, and Intel are sure the advantage of MSR_IMM will not be.
---
 xen/arch/x86/include/asm/alternative.h      |  7 ++++
 xen/arch/x86/include/asm/msr.h              | 39 ++++++++++++++++++++-
 xen/include/public/arch-x86/cpufeatureset.h |  1 +
 3 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/include/asm/alternative.h b/xen/arch/x86/include/asm/alternative.h
index 0482bbf7cbf1..fe87b15ec72c 100644
--- a/xen/arch/x86/include/asm/alternative.h
+++ b/xen/arch/x86/include/asm/alternative.h
@@ -151,6 +151,13 @@ extern void alternative_instructions(void);
         ALTERNATIVE(oldinstr, newinstr, feature)                        \
         :: input )
 
+#define alternative_input_2(oldinstr, newinstr1, feature1,              \
+                            newinstr2, feature2, input...)              \
+    asm_inline volatile (                                               \
+        ALTERNATIVE_2(oldinstr, newinstr1, feature1,                    \
+                      newinstr2, feature2)                              \
+        :: input )
+
 /* Like alternative_input, but with a single output argument */
 #define alternative_io(oldinstr, newinstr, feature, output, input...)   \
     asm_inline volatile (                                               \
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 01f510315ffe..434fcac854e1 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -38,9 +38,46 @@ static inline void wrmsrl(unsigned int msr, uint64_t val)
         wrmsr(msr, lo, hi);
 }
 
+/*
+ * Non-serialising WRMSR with a compile-time constant index, when available.
+ * Falls back to plain WRMSRNS, or to a serialising WRMSR.
+ */
+static always_inline void __wrmsrns_imm(uint32_t msr, uint64_t val)
+{
+    /*
+     * For best performance, WRMSRNS %r64, $msr is recommended.  For
+     * compatibility, we need to fall back to plain WRMSRNS, or to WRMSR.
+     *
+     * The combined ABI is awkward, because WRMSRNS $imm takes a single r64,
+     * whereas WRMSR{,NS} takes a split edx:eax pair.
+     *
+     * Always use WRMSRNS %rax, $imm, because it has the most in common with
+     * the legacy forms.  When MSR_IMM isn't available, emit setup logic for
+     * %ecx and %edx too.
+     */
+    alternative_input_2(
+        "mov $%c[msr], %%ecx\n\t"
+        "mov %%rax, %%rdx\n\t"
+        "shr $32, %%rdx\n\t"
+        ".byte 0x2e; wrmsr",
+
+        /* WRMSRNS %rax, $msr */
+        ".byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
+
+        "mov $%c[msr], %%ecx\n\t"
+        "mov %%rax, %%rdx\n\t"
+        "shr $32, %%rdx\n\t"
+        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
+
+        [msr] "i" (msr), "a" (val) : "rcx", "rdx");
+}
+
 /* Non-serialising WRMSR, when available.  Falls back to a serialising WRMSR. */
-static inline void wrmsrns(uint32_t msr, uint64_t val)
+static always_inline void wrmsrns(uint32_t msr, uint64_t val)
 {
+    if ( __builtin_constant_p(msr) )
+        return __wrmsrns_imm(msr, val);
+
     /*
      * WRMSR is 2 bytes.  WRMSRNS is 3 bytes.  Pad WRMSR with a redundant CS
      * prefix to avoid a trailing NOP.
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 9cd778586f10..af69cf3822eb 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -352,6 +352,7 @@ XEN_CPUFEATURE(MCDT_NO,            13*32+ 5) /*A  MCDT_NO */
 XEN_CPUFEATURE(UC_LOCK_DIS,        13*32+ 6) /*   UC-lock disable */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
+XEN_CPUFEATURE(MSR_IMM,            14*32+ 5) /*   {RD,WR}MSR $imm32 */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */
 XEN_CPUFEATURE(AVX_VNNI_INT8,      15*32+ 4) /*A  AVX-VNNI-INT8 Instructions */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 23/22] x86/vmx: Adjust NMI handling for FRED
Date: Sat,  9 Aug 2025 00:49:20 +0100
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Handling NMIs in VT-x is awkward.  It turns out that using INT $2 happens to
be correct for IDT delivery, and can be made to be correct under FRED too.

Xen can now boot in FRED mode and run PVH dom0 even with the watchdog enabled.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/hvm/vmx/vmx.c | 14 ++++++++++++--
 xen/arch/x86/traps.c       | 16 +++++++++++++++-
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index cb82d52ef035..577a5e2d59c6 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -4209,8 +4209,18 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_regs *regs)
              ((intr_info & INTR_INFO_INTR_TYPE_MASK) ==
               MASK_INSR(X86_ET_NMI, INTR_INFO_INTR_TYPE_MASK)) )
         {
-            do_nmi(regs);
-            enable_nmis();
+            /*
+             * If we exited because of an NMI, NMIs are blocked in hardware,
+             * but software is expected to invoke the handler.
+             *
+             * Use INT $2.  Combined with the current state, it is the correct
+             * architectural state for the NMI handler, and the IRET on the
+             * way back out will unblock NMIs.
+             *
+             * In FRED mode, we can spot this trick and cause the ERETS to
+             * unblock NMIs too.
+             */
+            asm ("int $2");
         }
         break;
     case EXIT_REASON_MCE_DURING_VMENTRY:
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index f58e6dcf13b7..16dd335cadb2 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2285,8 +2285,22 @@ void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
         do_nmi(regs);
         break;
 
-    case X86_ET_HW_EXC:
     case X86_ET_SW_INT:
+        if ( regs->fred_ss.vector == 2 )
+        {
+            /*
+             * Explicit request from the the VMExit handler.  Rewrite the FRED
+             * frame to look like it was a real NMI, and go around again.
+             */
+            regs->fred_ss.swint = false;
+            regs->fred_ss.nmi = true;
+            regs->fred_ss.type = X86_ET_NMI;
+            regs->fred_ss.insnlen = 0;
+
+            return entry_from_xen(regs);
+        }
+        fallthrough;
+    case X86_ET_HW_EXC:
     case X86_ET_PRIV_SW_EXC:
     case X86_ET_SW_EXC:
         switch ( regs->fred_ss.vector )
-- 
2.39.5



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Date: Sat, 9 Aug 2025 10:34:54 -0300
From: Jason Gunthorpe 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 00/16] dma-mapping: migrate to physical address-based
 API
Message-ID: <20250809133454.GP184255@nvidia.com>
References: 
 
 <20250807141929.GN184255@nvidia.com>
 
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On Fri, Aug 08, 2025 at 08:51:08PM +0200, Marek Szyprowski wrote:
> First - basing the API on the phys_addr_t.
> 
> Page based API had the advantage that it was really hard to abuse it and 
> call for something that is not 'a normal RAM'. 

This is not true anymore. Today we have ZONE_DEVICE as a struct page
type with a whole bunch of non-dram sub-types:

enum memory_type {
	/* 0 is reserved to catch uninitialized type fields */
	MEMORY_DEVICE_PRIVATE = 1,
	MEMORY_DEVICE_COHERENT,
	MEMORY_DEVICE_FS_DAX,
	MEMORY_DEVICE_GENERIC,
	MEMORY_DEVICE_PCI_P2PDMA,
};

Few of which are kmappable/page_to_virtable() in a way that is useful
for the DMA API.

DMA API sort of ignores all of this and relies on the caller to not
pass in an incorrect struct page. eg we rely on things like the block
stack to do the right stuff when a MEMORY_DEVICE_PCI_P2PDMA is present
in a bio_vec.

Which is not really fundamentally different from just using
phys_addr_t in the first place.

Sure, this was a stronger argument when this stuff was originally
written, before ZONE_DEVICE was invented.

> I initially though that phys_addr_t based API will somehow simplify
> arch specific implementation, as some of them indeed rely on
> phys_addr_t internally, but I missed other things pointed by
> Robin. Do we have here any alternative?

I think it is less of a code simplification, more as a reduction in
conceptual load. When we can say directly there is no struct page type
anyhwere in the DMA API layers then we only have to reason about
kmap/phys_to_virt compatibly.

This is also a weaker overall requirement than needing an actual
struct page which allows optimizing other parts of the kernel. Like we
aren't forced to create MEMORY_DEVICE_PCI_P2PDMA stuct pages just to
use the dma api.

Again, any place in the kernel we can get rid of struct page the
smoother the road will be for the MM side struct page restructuring.

For example one of the bigger eventual goes here is to make a bio_vec
store phys_addr_t, not struct page pointers.

DMA API is not alone here, we have been de-struct-paging the kernel
for a long time now:

netdev: https://lore.kernel.org/linux-mm/20250609043225.77229-1-byungchul@sk.com/
slab: https://lore.kernel.org/linux-mm/20211201181510.18784-1-vbabka@suse.cz/
iommmu: https://lore.kernel.org/all/0-v4-c8663abbb606+3f7-iommu_pages_jgg@nvidia.com/
page tables: https://lore.kernel.org/linux-mm/20230731170332.69404-1-vishal.moola@gmail.com/
zswap: https://lore.kernel.org/all/20241216150450.1228021-1-42.hyeyoo@gmail.com/

With a long term goal that struct page only exists for legacy code,
and is maybe entirely compiled out of modern server kernels.

> Second - making dma_map_phys() a single API to handle all cases.
> 
> Do we really need such single function to handle all cases? 

If we accept the direction to remove struct page then it makes little
sense to have a dma_map_ram(phys_addr) and dma_map_resource(phys_addr)
and force key callers (like block) to have more ifs - especially if
the conditional could become "free" inside the dma API (see below).

Plus if we keep the callchain split then adding a
"dma_link_resource"/etc are now needed as well.

> DMA_ATTR_MMIO for every typical DMA user? I know that branching is 
> cheap, but this will probably increase code size for most of the typical 
> users for no reason.

Well, having two call chains will increase the code size much more,
and 'resource' can't be compiled out. Arguably this unification should
reduce the .text size since many of the resource only functions go
away.

There are some branches, and I think the push toward re-using
DMA_ATTR_SKIP_CPU_SYNC was directly to try to reduce that branch
cost.

However, I think we should be looking for a design here that is "free"
on the fast no-swiotlb and non-cache-flush path. I think this can be
achieved by checking ATTR_MMIO only after seeing swiotlb is needed
(like today's is p2p check). And we can probably freely fold it into
the existing sync check:

	if ((attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)) == 0)

I saw Leon hasn't done these micro optimizations, but it seems like it
could work out.

Regards,
Jason


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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH] xen/arm: irq: add missing spin_unlock() in init_local_irq_data() error path
Date: Sat,  9 Aug 2025 17:32:41 +0300
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From: Mykola Kvach 

If init_one_irq_desc() fails, init_local_irq_data() returns without
releasing local_irqs_type_lock, leading to a possible deadlock.

Release the lock before returning to ensure proper cleanup.

Signed-off-by: Mykola Kvach 
---
 xen/arch/arm/irq.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 4bbf0b0664..02ca82c089 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -94,7 +94,10 @@ static int init_local_irq_data(unsigned int cpu)
         int rc = init_one_irq_desc(desc);
 
         if ( rc )
+        {
+            spin_unlock(&local_irqs_type_lock);
             return rc;
+        }
 
         desc->irq = irq;
         desc->action  = NULL;
-- 
2.48.1



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Date: Sat, 9 Aug 2025 18:22:33 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Anthony PERARD 
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH v2 1/3] CI: Rework run-tools-test exit path
Message-ID: 
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 <20250730152602.45436-2-anthony@xenproject.org>
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--aMZBcusYaCrcvdhH
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Date: Sat, 9 Aug 2025 18:22:33 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Anthony PERARD 
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH v2 1/3] CI: Rework run-tools-test exit path

On Wed, Jul 30, 2025 at 05:26:00PM +0200, Anthony PERARD wrote:
> From: Anthony PERARD 
>=20
> The main script expect to find the string "$passed" or it just timeout
> and doesn't try to download the junit file in this case. So we ignore
> the return value of run-tools-test to always print "$passed" and
> instead look for failure in the generated junit file. If the junit
> report is incomplete, this will also result in a failure of the job.
>=20
> Signed-off-by: Anthony PERARD 
> ---
>=20
> Notes:
>     Changes in v2:
>     - This squash both patch "CI: Ignore run-tools-test return value" and
>       "CI: Have the gitlab job fail on tools/tests failure"
>     - grep for ''
>=20
>  automation/scripts/qubes-x86-64.sh | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>=20
> diff --git a/automation/scripts/qubes-x86-64.sh b/automation/scripts/qube=
s-x86-64.sh
> index 2750d24eba..21dcd9b063 100755
> --- a/automation/scripts/qubes-x86-64.sh
> +++ b/automation/scripts/qubes-x86-64.sh
> @@ -135,10 +135,11 @@ done
>      ### tests: tools-tests-pv, tools-tests-pvh
>      "tools-tests-pv"|"tools-tests-pvh")
>          retrieve_xml=3D1
> -        passed=3D"test passed"
> +        passed=3D"run-tools-test over"
>          domU_check=3D""
>          dom0_check=3D"
> -/root/run-tools-tests /usr/lib/xen/tests /tmp/tests-junit.xml && echo \"=
${passed}\"
> +/root/run-tools-tests /usr/lib/xen/tests /tmp/tests-junit.xml ||:
> +echo \"${passed}\"
>  nc -l -p 8080 < /tmp/tests-junit.xml >/dev/null &
>  "
>          if [ "${test_variant}" =3D "tools-tests-pvh" ]; then
> @@ -297,6 +298,14 @@ TEST_RESULT=3D$?
> =20
>  if [ -n "$retrieve_xml" ]; then
>      nc -w 10 "$SUT_ADDR" 8080 > tests-junit.xml  +    # Findout if one of the test failed
> +    if ! grep -q '' tests-junit.xml; then
> +        echo "ERROR: tests-junit.xml is incomplete or missing."
> +        TEST_RESULT=3D1
> +    # Only match "type=3Dfailure" to allow to "tolerable" for example.
> +    elif grep -q ' +        TEST_RESULT=3D1
> +    fi
>  fi
> =20
>  exit "$TEST_RESULT"
> --=20
> Anthony PERARD
>=20

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Date: Sat, 9 Aug 2025 18:23:39 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Anthony PERARD 
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH v2 2/3] CI: Upload junit result as artefact
Message-ID: 
References: <20250730152602.45436-1-anthony@xenproject.org>
 <20250730152602.45436-3-anthony@xenproject.org>
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Date: Sat, 9 Aug 2025 18:23:39 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Anthony PERARD 
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH v2 2/3] CI: Upload junit result as artefact

On Wed, Jul 30, 2025 at 05:26:01PM +0200, Anthony PERARD wrote:
> From: Anthony PERARD 
>=20
> This allows to investigate the junit file in cases of parse error.
>=20
> Signed-off-by: Anthony PERARD 

Reviewed-by: Marek Marczykowski-G=C3=B3recki 
> ---
>=20
> Notes:
>     Changes in v2:
>     - more concise patch description.
>=20
>  automation/gitlab-ci/test.yaml | 1 +
>  1 file changed, 1 insertion(+)
>=20
> diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.y=
aml
> index 1f0b27b237..feb03cc7ed 100644
> --- a/automation/gitlab-ci/test.yaml
> +++ b/automation/gitlab-ci/test.yaml
> @@ -155,6 +155,7 @@
>      paths:
>        - smoke.serial
>        - '*.log'
> +      - tests-junit.xml
>      when: always
>    rules:
>      - if: $SELECTED_JOBS_ONLY && $CI_JOB_NAME =3D~ $SELECTED_JOBS_ONLY
> --=20
> Anthony PERARD
>=20

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Date: Sat, 9 Aug 2025 18:25:28 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Anthony PERARD 
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH v2 3/3] CI: Workaround extra content in junit
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 <20250730152602.45436-4-anthony@xenproject.org>
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Date: Sat, 9 Aug 2025 18:25:28 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Anthony PERARD 
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH v2 3/3] CI: Workaround extra content in junit

On Wed, Jul 30, 2025 at 05:26:02PM +0200, Anthony PERARD wrote:
> From: Anthony PERARD 
>=20
> Signed-off-by: Anthony PERARD 

Is it still an issue? AFAIR similar issue was fixed together with fixing
xml upload hanging.

> ---
>  automation/scripts/qubes-x86-64.sh | 6 ++++++
>  1 file changed, 6 insertions(+)
>=20
> diff --git a/automation/scripts/qubes-x86-64.sh b/automation/scripts/qube=
s-x86-64.sh
> index 21dcd9b063..f1b7e02e63 100755
> --- a/automation/scripts/qubes-x86-64.sh
> +++ b/automation/scripts/qubes-x86-64.sh
> @@ -298,6 +298,12 @@ TEST_RESULT=3D$?
> =20
>  if [ -n "$retrieve_xml" ]; then
>      nc -w 10 "$SUT_ADDR" 8080 > tests-junit.xml  +    # Workaround duplicated data been received
> +    sed -i.old '/^<\/testsuites>/q' tests-junit.xml > /dev/null
> +    extra_line_in_junit=3D$(($(wc -l < tests-junit.xml.old) - $(wc -l < =
tests-junit.xml)))
> +    if [ $extra_line_in_junit -gt 0 ]; then
> +        echo "WARNING: Found $extra_line_in_junit too many lines in juni=
t."
> +    fi
>      # Findout if one of the test failed
>      if ! grep -q '' tests-junit.xml; then
>          echo "ERROR: tests-junit.xml is incomplete or missing."
> --=20
> Anthony PERARD
>=20

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Date: Sat, 9 Aug 2025 12:53:09 -0400
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Subject: Re: [PATCH v1 00/16] dma-mapping: migrate to physical address-based
 API
To: Jason Gunthorpe ,
 Marek Szyprowski 
Cc: Leon Romanovsky ,
 Abdiel Janulgue ,
 Alexander Potapenko , Alex Gaynor
 , Andrew Morton ,
 Christoph Hellwig , Danilo Krummrich ,
 iommu@lists.linux.dev, Jason Wang ,
 Jens Axboe , Joerg Roedel ,
 Jonathan Corbet , Juergen Gross ,
 kasan-dev@googlegroups.com, Keith Busch ,
 linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-mm@kvack.org,
 linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
 linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan
 , Masami Hiramatsu ,
 Michael Ellerman , "Michael S. Tsirkin"
 , Miguel Ojeda ,
 Robin Murphy , rust-for-linux@vger.kernel.org,
 Sagi Grimberg , Stefano Stabellini
 , Steven Rostedt ,
 virtualization@lists.linux.dev, Will Deacon ,
 xen-devel@lists.xenproject.org
References: 
 
 <20250807141929.GN184255@nvidia.com>
 
 <20250809133454.GP184255@nvidia.com>
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In-Reply-To: <20250809133454.GP184255@nvidia.com>
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 protected-headers="v1"
From: Demi Marie Obenour 
To: Jason Gunthorpe ,
 Marek Szyprowski 
Cc: Leon Romanovsky ,
 Abdiel Janulgue ,
 Alexander Potapenko , Alex Gaynor
 , Andrew Morton ,
 Christoph Hellwig , Danilo Krummrich ,
 iommu@lists.linux.dev, Jason Wang ,
 Jens Axboe , Joerg Roedel ,
 Jonathan Corbet , Juergen Gross ,
 kasan-dev@googlegroups.com, Keith Busch ,
 linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-mm@kvack.org,
 linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
 linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan
 , Masami Hiramatsu ,
 Michael Ellerman , "Michael S. Tsirkin"
 , Miguel Ojeda ,
 Robin Murphy , rust-for-linux@vger.kernel.org,
 Sagi Grimberg , Stefano Stabellini
 , Steven Rostedt ,
 virtualization@lists.linux.dev, Will Deacon ,
 xen-devel@lists.xenproject.org
Message-ID: <6cbaa3a3-694e-4951-abb3-b88e6c9d6638@gmail.com>
Subject: Re: [PATCH v1 00/16] dma-mapping: migrate to physical address-based
 API
References: 
 
 <20250807141929.GN184255@nvidia.com>
 
 <20250809133454.GP184255@nvidia.com>
In-Reply-To: <20250809133454.GP184255@nvidia.com>
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On 8/9/25 09:34, Jason Gunthorpe wrote:
> On Fri, Aug 08, 2025 at 08:51:08PM +0200, Marek Szyprowski wrote:
>> First - basing the=C2=A0API on the phys_addr_t.
>>
>> Page based API had the advantage that it was really hard to abuse it a=
nd=20
>> call for something that is not 'a normal RAM'.=20
>=20
> This is not true anymore. Today we have ZONE_DEVICE as a struct page
> type with a whole bunch of non-dram sub-types:
>=20
> enum memory_type {
> 	/* 0 is reserved to catch uninitialized type fields */
> 	MEMORY_DEVICE_PRIVATE =3D 1,
> 	MEMORY_DEVICE_COHERENT,
> 	MEMORY_DEVICE_FS_DAX,
> 	MEMORY_DEVICE_GENERIC,
> 	MEMORY_DEVICE_PCI_P2PDMA,
> };
>=20
> Few of which are kmappable/page_to_virtable() in a way that is useful
> for the DMA API.
>=20
> DMA API sort of ignores all of this and relies on the caller to not
> pass in an incorrect struct page. eg we rely on things like the block
> stack to do the right stuff when a MEMORY_DEVICE_PCI_P2PDMA is present
> in a bio_vec.
>=20
> Which is not really fundamentally different from just using
> phys_addr_t in the first place.
>=20
> Sure, this was a stronger argument when this stuff was originally
> written, before ZONE_DEVICE was invented.
>=20
>> I initially though that phys_addr_t based API will somehow simplify
>> arch specific implementation, as some of them indeed rely on
>> phys_addr_t internally, but I missed other things pointed by
>> Robin. Do we have here any alternative?
>=20
> I think it is less of a code simplification, more as a reduction in
> conceptual load. When we can say directly there is no struct page type
> anyhwere in the DMA API layers then we only have to reason about
> kmap/phys_to_virt compatibly.
>=20
> This is also a weaker overall requirement than needing an actual
> struct page which allows optimizing other parts of the kernel. Like we
> aren't forced to create MEMORY_DEVICE_PCI_P2PDMA stuct pages just to
> use the dma api.
>=20
> Again, any place in the kernel we can get rid of struct page the
> smoother the road will be for the MM side struct page restructuring.
>=20
> For example one of the bigger eventual goes here is to make a bio_vec
> store phys_addr_t, not struct page pointers.
>=20
> DMA API is not alone here, we have been de-struct-paging the kernel
> for a long time now:
>=20
> netdev: https://lore.kernel.org/linux-mm/20250609043225.77229-1-byungch=
ul@sk.com/
> slab: https://lore.kernel.org/linux-mm/20211201181510.18784-1-vbabka@su=
se.cz/
> iommmu: https://lore.kernel.org/all/0-v4-c8663abbb606+3f7-iommu_pages_j=
gg@nvidia.com/
> page tables: https://lore.kernel.org/linux-mm/20230731170332.69404-1-vi=
shal.moola@gmail.com/
> zswap: https://lore.kernel.org/all/20241216150450.1228021-1-42.hyeyoo@g=
mail.com/
>=20
> With a long term goal that struct page only exists for legacy code,
> and is maybe entirely compiled out of modern server kernels.

Why just server kernels?  I suspect client systems actually run
newer kernels than servers do.
--=20
Sincerely,
Demi Marie Obenour (she/her/hers)
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From xen-devel-bounces@lists.xenproject.org Sat Aug 09 17:02:13 2025
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Date: Sat, 09 Aug 2025 17:01:57 +0000
To: Julien Grall 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v14 1/4] xen/domain: unify domain ID allocation
Message-ID: 
In-Reply-To: <400bf35e-65cc-40a6-ae7a-3c134e6d9c49@xen.org>
References: <20250808021938.669855-1-dmukhin@ford.com> <20250808021938.669855-2-dmukhin@ford.com> <400bf35e-65cc-40a6-ae7a-3c134e6d9c49@xen.org>
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On Fri, Aug 08, 2025 at 06:42:03PM +0100, Julien Grall wrote:
> Hi Denis,
>=20
> On 08/08/2025 03:19, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Currently, there are two different domain ID allocation implementations=
:
> >
> >    1) Sequential IDs allocation in dom0less Arm code based on max_init_=
domid;
> >
> >    2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not us=
e
> >       max_init_domid (both Arm and x86).
> >
> > The domain ID allocation covers dom0 or late hwdom, predefined domains,
> > post-boot domains, excluding Xen system domains (domid >=3D
> > DOMID_FIRST_RESERVED).
> >
> > It makes sense to have a common helper code for such task across archit=
ectures
> > (Arm and x86) and between dom0less / toolstack domU allocation.
> >
> > Note, fixing dependency on max_init_domid is out of scope of this patch=
.
> >
> > Wrap the domain ID allocation as an arch-independent function domid_all=
oc() in
> > new common/domid.c based on the bitmap.
> >
> > Allocation algorithm:
> > - If an explicit domain ID is provided, verify its availability and use=
 it if
> >    ID is not used;
> > - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERV=
ED-1],
> >    starting from the last used ID.
> >    Implementation guarantees that two consecutive calls will never retu=
rn the
> >    same ID. ID#0 is reserved for the first boot domain (currently, dom0=
) and
> >    excluded from the allocation range.
> >
> > Remove is_free_domid() helper as it is not needed now.
> >
> > No functional change intended.
> >
> > Signed-off-by: Denis Mukhin 
>=20
> Reviewed-by: Julien Grall 

Thank you!

>=20
> Cheers,
>=20
> --
> Julien Grall
>=20
>=20



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Date: Sat, 09 Aug 2025 17:03:34 +0000
To: Julien Grall 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v14 3/4] tools/tests: introduce unit tests for domain ID allocator
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In-Reply-To: <230593d5-f3a2-4be8-973a-530c2debcb08@xen.org>
References: <20250808021938.669855-1-dmukhin@ford.com> <20250808021938.669855-4-dmukhin@ford.com> <230593d5-f3a2-4be8-973a-530c2debcb08@xen.org>
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On Fri, Aug 08, 2025 at 06:56:16PM +0100, Julien Grall wrote:
> Hi Denis,
>=20
> On 08/08/2025 03:20, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Introduce some basic infrastructure for doing domain ID allocation unit=
 tests,
> > and add a few tests that ensure correctness of the domain ID allocator.
>=20
> I am quite happy to see more unit tests for Xen :).
>=20
> >
> > Use  and xen/lib/find-next-bit.c in test hardness c=
ode.
> >
> > Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.
> >
> > Signed-off-by: Denis Mukhin 
>=20
> With a couple of remarks below:
>=20
> Acked-by: Julien Grall 
>=20
> > ---
> > Changes since v13:
> > - reworked bitops integration
> > - hooked xen/lib/find-next-bit.c
> > - cleaned up harness.h code
> > - made test to use more IDs
> > ---
> >   tools/include/xen-tools/bitops.h       | 10 +++
> >   tools/tests/Makefile                   |  2 +-
> >   tools/tests/domid/.gitignore           |  2 +
> >   tools/tests/domid/Makefile             | 56 +++++++++++++++++
> >   tools/tests/domid/harness.h            | 54 ++++++++++++++++
> >   tools/tests/domid/include/xen/domain.h |  1 +
> >   tools/tests/domid/test-domid.c         | 86 +++++++++++++++++++++++++=
+
> >   xen/lib/find-next-bit.c                |  5 ++
> >   8 files changed, 215 insertions(+), 1 deletion(-)
> >   create mode 100644 tools/tests/domid/.gitignore
> >   create mode 100644 tools/tests/domid/Makefile
> >   create mode 100644 tools/tests/domid/harness.h
> >   create mode 120000 tools/tests/domid/include/xen/domain.h
> >   create mode 100644 tools/tests/domid/test-domid.c
> >
> > diff --git a/tools/include/xen-tools/bitops.h b/tools/include/xen-tools=
/bitops.h
> > index 681482f6759f..3b98fba6d74c 100644
> > --- a/tools/include/xen-tools/bitops.h
> > +++ b/tools/include/xen-tools/bitops.h
> > @@ -12,6 +12,16 @@
> >   #define BITS_PER_LONG 32
> >   #endif
> >
> > +#define ffsl(x)       __builtin_ffsl(x)
> > +
> > +#define BIT_WORD(nr)  ((nr) / BITS_PER_LONG)
> > +
> > +#define BITS_TO_LONGS(bits) \
> > +    (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
> > +
> > +#define DECLARE_BITMAP(name, bits) \
> > +    unsigned long name[BITS_TO_LONGS(bits)]
> > +
> >   #define BITMAP_ENTRY(_nr,_bmap) ((_bmap))[(_nr) / 8]
> >   #define BITMAP_SHIFT(_nr) ((_nr) % 8)
> >
> > diff --git a/tools/tests/Makefile b/tools/tests/Makefile
> > index 36928676a666..ff1666425436 100644
> > --- a/tools/tests/Makefile
> > +++ b/tools/tests/Makefile
> > @@ -1,7 +1,7 @@
> >   XEN_ROOT =3D $(CURDIR)/../..
> >   include $(XEN_ROOT)/tools/Rules.mk
> >
> > -SUBDIRS-y :=3D
> > +SUBDIRS-y :=3D domid
>=20
> I would prefer if we keep SUBDIRST-y :=3D as it is and add a new line
> SUBDIRS-y +=3D. This is mostly to reduce the chance that someone will add
> a new directory "abc" and forgot to update the line containing "domid".

Ack.

>=20
> >   SUBDIRS-y +=3D resource
> >   SUBDIRS-$(CONFIG_X86) +=3D cpu-policy
> >   SUBDIRS-$(CONFIG_X86) +=3D tsx
> > diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignor=
e
> > new file mode 100644
> > index 000000000000..70e306b3c074
> > --- /dev/null
> > +++ b/tools/tests/domid/.gitignore
> > @@ -0,0 +1,2 @@
> > +*.o
> > +test-domid
> > diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile
> > new file mode 100644
> > index 000000000000..d96ceca6d954
> > --- /dev/null
> > +++ b/tools/tests/domid/Makefile
> > @@ -0,0 +1,56 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +#
> > +# Unit tests for domain ID allocator.
> > +#
> > +# Copyright 2025 Ford Motor Company
> > +
> > +XEN_ROOT=3D$(CURDIR)/../../..
> > +include $(XEN_ROOT)/tools/Rules.mk
> > +
> > +TESTS :=3D test-domid
> > +
> > +vpath domid.c $(XEN_ROOT)/xen/common/
> > +vpath find-next-bit.c $(XEN_ROOT)/xen/lib/
> > +
> > +.PHONY: all
> > +all: $(TESTS)
> > +
> > +.PHONY: run
> > +run: $(TESTS)
> > +=09$(foreach t,$(TESTS),./$(t);)
> > +
> > +.PHONY: clean
> > +clean:
> > +=09$(RM) -- *.o $(TESTS) $(DEPS_RM)
> > +
> > +.PHONY: distclean
> > +distclean: clean
> > +=09$(RM) -- *~
> > +
> > +.PHONY: install
> > +install: all
> > +=09$(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests
> > +=09$(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests
> > +
> > +.PHONY: uninstall
> > +uninstall:
> > +=09$(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid
> > +
> > +CFLAGS +=3D -D__XEN_TOOLS__
> > +# find-next-bit.c
> > +CFLAGS +=3D '-DEXPORT_SYMBOL(x)=3D' \
> > +          -Dfind_first_bit \
> > +          -Dfind_first_zero_bit \
> > +          -Dfind_next_bit \
> > +          -Dfind_next_bit_le \
> > +          -Dfind_next_zero_bit_le
> > +CFLAGS +=3D $(APPEND_CFLAGS)
> > +CFLAGS +=3D $(CFLAGS_xeninclude)
> > +CFLAGS +=3D -I./include/
> > +
> > +LDFLAGS +=3D $(APPEND_LDFLAGS)
> > +
> > +test-domid: domid.o find-next-bit.o test-domid.o
> > +=09$(CC) $^ -o $@ $(LDFLAGS)
> > +
> > +-include $(DEPS_INCLUDE)
> > diff --git a/tools/tests/domid/harness.h b/tools/tests/domid/harness.h
> > new file mode 100644
> > index 000000000000..b043519dcb35
> > --- /dev/null
> > +++ b/tools/tests/domid/harness.h
> > @@ -0,0 +1,54 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Unit test harness for domain ID allocator.
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#ifndef _TEST_HARNESS_
> > +#define _TEST_HARNESS_
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +
> > +typedef bool spinlock_t;
> > +typedef uint16_t domid_t;
> > +
> > +extern domid_t domid_alloc(domid_t domid);
> > +extern void domid_free(domid_t domid);
> > +
> > +extern unsigned long find_next_zero_bit(const unsigned long *addr,
> > +                                        unsigned long size,
> > +                                        unsigned long offset);
> > +
> > +#define __test_and_set_bit(nr, addr)    test_and_set_bit(nr, addr)
> > +#define __test_and_clear_bit(nr, addr)  test_and_clear_bit(nr, addr)
> > +#define __set_bit(nr, addr)             set_bit(nr, addr)
> > +
> > +#define BUG_ON(x)                       assert(!(x))
> > +#define ASSERT(x)                       assert(x)
> > +
> > +#define DEFINE_SPINLOCK(l)              spinlock_t l
> > +#define spin_lock(l)                    (*(l) =3D true)
> > +#define spin_unlock(l)                  (*(l) =3D false)
>=20
> NIT: For hardening purpose, I wonder whether we should also assert that
> "l" is "false" for spin_lock() and "true" for spin_unlock(). This would
> help catching any bug in the locking.

Good idea! Will do.

>=20
> > +
> > +#define printk                          printf
> > +
> > +#define DOMID_FIRST_RESERVED            (100)
> > +#define DOMID_INVALID                   (101)
> > +
> > +#endif /* _TEST_HARNESS_ */
> > +
> > +/*
> > + * Local variables:
> > + * mode: C
> > + * c-file-style: "BSD"
> > + * c-basic-offset: 4
> > + * indent-tabs-mode: nil
> > + * End:
> > + */
> > diff --git a/tools/tests/domid/include/xen/domain.h b/tools/tests/domid=
/include/xen/domain.h
> > new file mode 120000
> > index 000000000000..2eda9aed088e
> > --- /dev/null
> > +++ b/tools/tests/domid/include/xen/domain.h
> > @@ -0,0 +1 @@
> > +../../harness.h
> > \ No newline at end of file
> > diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-do=
mid.c
> > new file mode 100644
> > index 000000000000..7b6fb5ee2a7b
> > --- /dev/null
> > +++ b/tools/tests/domid/test-domid.c
> > @@ -0,0 +1,86 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Unit tests for domain ID allocator.
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#include "harness.h"
> > +
> > +#define verify(exp, fmt, args...) do { \
> > +    if ( !(exp) ) \
> > +        printf(fmt, ## args); \
> > +    assert(exp); \
> > +} while (0);
> > +
> > +/*
> > + * Fail on the first error, since tests are dependent on each other.
> > + */
> > +int main(int argc, char **argv)
> > +{
> > +    domid_t expected, allocated;
> > +
> > +    /* Test ID#0 cannot be allocated twice. */
>=20
> For future improvement, we could check that for any domid [0;
> DOMID_FIRST_RESERVED[, we can allocate domid_alloc().
>=20
> This would also confirm that domid_alloc() *only* allocates *one* ID.

Will update.

>=20
> Cheers,
>=20
> --
> Julien Grall
>=20
>=20



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Date: Sat, 09 Aug 2025 17:04:02 +0000
To: Julien Grall 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v14 3/4] tools/tests: introduce unit tests for domain ID allocator
Message-ID: 
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References: <20250808021938.669855-1-dmukhin@ford.com> <20250808021938.669855-4-dmukhin@ford.com> <230593d5-f3a2-4be8-973a-530c2debcb08@xen.org> <44b43350-8c0a-497d-b0b0-034a548afac0@xen.org>
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On Fri, Aug 08, 2025 at 06:57:07PM +0100, Julien Grall wrote:
>=20
>=20
> On 08/08/2025 18:56, Julien Grall wrote:
> > Hi Denis,
> >
> > On 08/08/2025 03:20, dmkhn@proton.me wrote:
> >> From: Denis Mukhin 
> >>
> >> Introduce some basic infrastructure for doing domain ID allocation
> >> unit tests,
> >> and add a few tests that ensure correctness of the domain ID allocator=
.
> >
> > I am quite happy to see more unit tests for Xen :).
> >
> >>
> >> Use  and xen/lib/find-next-bit.c in test hardness
> >> code.
> >>
> >> Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.
> >>
> >> Signed-off-by: Denis Mukhin 
> >
> > With a couple of remarks below:
> >
> > Acked-by: Julien Grall 
>=20
> Actually, this should have been a Reviewed-by tag. Sorry.

Thanks for review!

>=20
> Cheers,
>=20
> --
> Julien Grall
>=20



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Date: Sat, 09 Aug 2025 17:07:54 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v15 0/4] xen/domain: domain ID allocation
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Patch 1 introduces new domid_{alloc,free} calls.
Patch 2 is a prep change for domain ID allocator test.
Patch 3 introduces some basic testing for domain ID allocator.
Patch 4 adjusts create_dom0() messages (use %pd).

Link to v14: https://lore.kernel.org/xen-devel/20250808021938.669855-1-dmuk=
hin@ford.com/
Link to CI: https://gitlab.com/xen-project/people/dmukhin/xen/-/pipelines/1=
975302322

Denis Mukhin (4):
  xen/domain: unify domain ID allocation
  tools/include: move xc_bitops.h to xen-tools/bitops.h
  tools/tests: introduce unit tests for domain ID allocator
  xen/domain: update create_dom0() messages

 .../xen-tools/bitops.h}                       | 16 +++-
 tools/libs/ctrl/xc_misc.c                     | 13 +--
 tools/libs/guest/xg_dom_elfloader.c           |  3 +-
 tools/libs/guest/xg_dom_hvmloader.c           |  3 +-
 tools/libs/guest/xg_private.h                 |  2 +-
 tools/libs/guest/xg_sr_common.h               |  3 +-
 tools/tests/Makefile                          |  1 +
 tools/tests/domid/.gitignore                  |  2 +
 tools/tests/domid/Makefile                    | 56 +++++++++++
 tools/tests/domid/harness.h                   | 54 +++++++++++
 tools/tests/domid/include/xen/domain.h        |  1 +
 tools/tests/domid/test-domid.c                | 93 ++++++++++++++++++
 xen/arch/arm/domain_build.c                   | 13 ++-
 xen/arch/x86/setup.c                          | 11 ++-
 xen/common/Makefile                           |  1 +
 xen/common/device-tree/dom0less-build.c       | 15 +--
 xen/common/domain.c                           |  2 +
 xen/common/domctl.c                           | 43 ++-------
 xen/common/domid.c                            | 95 +++++++++++++++++++
 xen/include/xen/domain.h                      |  3 +
 xen/lib/find-next-bit.c                       |  5 +
 21 files changed, 369 insertions(+), 66 deletions(-)
 rename tools/{libs/ctrl/xc_bitops.h =3D> include/xen-tools/bitops.h} (84%)
 create mode 100644 tools/tests/domid/.gitignore
 create mode 100644 tools/tests/domid/Makefile
 create mode 100644 tools/tests/domid/harness.h
 create mode 120000 tools/tests/domid/include/xen/domain.h
 create mode 100644 tools/tests/domid/test-domid.c
 create mode 100644 xen/common/domid.c

--=20
2.34.1




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Date: Sat, 09 Aug 2025 17:08:00 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall 
Subject: [PATCH v15 1/4] xen/domain: unify domain ID allocation
Message-ID: <20250809170747.1836880-2-dmukhin@ford.com>
In-Reply-To: <20250809170747.1836880-1-dmukhin@ford.com>
References: <20250809170747.1836880-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Currently, there are two different domain ID allocation implementations:

  1) Sequential IDs allocation in dom0less Arm code based on max_init_domid=
;

  2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
     max_init_domid (both Arm and x86).

The domain ID allocation covers dom0 or late hwdom, predefined domains,
post-boot domains, excluding Xen system domains (domid >=3D
DOMID_FIRST_RESERVED).

It makes sense to have a common helper code for such task across architectu=
res
(Arm and x86) and between dom0less / toolstack domU allocation.

Note, fixing dependency on max_init_domid is out of scope of this patch.

Wrap the domain ID allocation as an arch-independent function domid_alloc()=
 in
new common/domid.c based on the bitmap.

Allocation algorithm:
- If an explicit domain ID is provided, verify its availability and use it =
if
  ID is not used;
- If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1=
],
  starting from the last used ID.
  Implementation guarantees that two consecutive calls will never return th=
e
  same ID. ID#0 is reserved for the first boot domain (currently, dom0) and
  excluded from the allocation range.

Remove is_free_domid() helper as it is not needed now.

No functional change intended.

Signed-off-by: Denis Mukhin 
Reviewed-by: Julien Grall 
---
Changes since v14:
- added Julien's R-b
---
 xen/arch/arm/domain_build.c             |  7 +-
 xen/arch/x86/setup.c                    |  7 +-
 xen/common/Makefile                     |  1 +
 xen/common/device-tree/dom0less-build.c | 15 ++--
 xen/common/domain.c                     |  2 +
 xen/common/domctl.c                     | 43 ++---------
 xen/common/domid.c                      | 95 +++++++++++++++++++++++++
 xen/include/xen/domain.h                |  3 +
 8 files changed, 126 insertions(+), 47 deletions(-)
 create mode 100644 xen/common/domid.c

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 463ae4474d30..789f2b9d3ce7 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2050,6 +2050,7 @@ void __init create_dom0(void)
         .grant_opts =3D XEN_DOMCTL_GRANT_version(opt_gnttab_max_version),
     };
     unsigned int flags =3D CDF_privileged | CDF_hardware;
+    domid_t domid;
     int rc;
=20
     /* The vGIC for DOM0 is exactly emulating the hardware GIC */
@@ -2074,7 +2075,11 @@ void __init create_dom0(void)
     if ( !llc_coloring_enabled )
         flags |=3D CDF_directmap;
=20
-    dom0 =3D domain_create(0, &dom0_cfg, flags);
+    domid =3D domid_alloc(0);
+    if ( domid =3D=3D DOMID_INVALID )
+        panic("Error allocating domain ID 0\n");
+
+    dom0 =3D domain_create(domid, &dom0_cfg, flags);
     if ( IS_ERR(dom0) )
         panic("Error creating domain 0 (rc =3D %ld)\n", PTR_ERR(dom0));
=20
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 1543dd251cc6..398da734c0c5 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1047,8 +1047,11 @@ static struct domain *__init create_dom0(struct boot=
_info *bi)
     if ( iommu_enabled )
         dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu;
=20
-    /* Create initial domain.  Not d0 for pvshim. */
-    bd->domid =3D get_initial_domain_id();
+    /* Allocate initial domain ID.  Not d0 for pvshim. */
+    bd->domid =3D domid_alloc(get_initial_domain_id());
+    if ( bd->domid =3D=3D DOMID_INVALID )
+        panic("Error allocating domain ID %u\n", get_initial_domain_id());
+
     d =3D domain_create(bd->domid, &dom0_cfg,
                       pv_shim ? 0 : CDF_privileged | CDF_hardware);
     if ( IS_ERR(d) )
diff --git a/xen/common/Makefile b/xen/common/Makefile
index c316957fcb36..0c7d0f5d46e1 100644
--- a/xen/common/Makefile
+++ b/xen/common/Makefile
@@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) +=3D devic=
e.o
 obj-$(CONFIG_DEVICE_TREE_PARSE) +=3D device-tree/
 obj-$(CONFIG_IOREQ_SERVER) +=3D dm.o
 obj-y +=3D domain.o
+obj-y +=3D domid.o
 obj-y +=3D event_2l.o
 obj-y +=3D event_channel.o
 obj-$(CONFIG_EVTCHN_FIFO) +=3D event_fifo.o
diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tr=
ee/dom0less-build.c
index 6bb038111de9..f4b6b515d2d2 100644
--- a/xen/common/device-tree/dom0less-build.c
+++ b/xen/common/device-tree/dom0less-build.c
@@ -833,6 +833,7 @@ void __init create_domUs(void)
     {
         struct kernel_info ki =3D KERNEL_INFO_INIT;
         int rc =3D parse_dom0less_node(node, &ki.bd);
+        domid_t domid;
=20
         if ( rc =3D=3D -ENOENT )
             continue;
@@ -842,13 +843,13 @@ void __init create_domUs(void)
         if ( (max_init_domid + 1) >=3D DOMID_FIRST_RESERVED )
             panic("No more domain IDs available\n");
=20
-        /*
-         * The variable max_init_domid is initialized with zero, so here i=
t's
-         * very important to use the pre-increment operator to call
-         * domain_create() with a domid > 0. (domid =3D=3D 0 is reserved f=
or Dom0)
-         */
-        ki.bd.d =3D domain_create(++max_init_domid,
-                                &ki.bd.create_cfg, ki.bd.create_flags);
+        domid =3D domid_alloc(DOMID_INVALID);
+        if ( domid =3D=3D DOMID_INVALID )
+            panic("Error allocating ID for domain %s\n", dt_node_name(node=
));
+
+        max_init_domid =3D max(max_init_domid, domid);
+
+        ki.bd.d =3D domain_create(domid, &ki.bd.create_cfg, ki.bd.create_f=
lags);
         if ( IS_ERR(ki.bd.d) )
             panic("Error creating domain %s (rc =3D %ld)\n",
                   dt_node_name(node), PTR_ERR(ki.bd.d));
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 5241a1629eeb..a7e303253d1a 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -692,6 +692,8 @@ static void _domain_destroy(struct domain *d)
=20
     lock_profile_deregister_struct(LOCKPROF_TYPE_PERDOM, d);
=20
+    domid_free(d->domain_id);
+
     free_domain_struct(d);
 }
=20
diff --git a/xen/common/domctl.c b/xen/common/domctl.c
index f2a7caaf853c..71e712c1f316 100644
--- a/xen/common/domctl.c
+++ b/xen/common/domctl.c
@@ -51,20 +51,6 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nodemas=
k,
                                    MAX_NUMNODES);
 }
=20
-static inline int is_free_domid(domid_t dom)
-{
-    struct domain *d;
-
-    if ( dom >=3D DOMID_FIRST_RESERVED )
-        return 0;
-
-    if ( (d =3D rcu_lock_domain_by_id(dom)) =3D=3D NULL )
-        return 1;
-
-    rcu_unlock_domain(d);
-    return 0;
-}
-
 void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info=
)
 {
     struct vcpu *v;
@@ -423,36 +409,19 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u=
_domctl)
=20
     case XEN_DOMCTL_createdomain:
     {
-        domid_t        dom;
-        static domid_t rover =3D 0;
+        /* NB: ID#0 is reserved, find the first suitable ID instead. */
+        domid_t domid =3D domid_alloc(op->domain ?: DOMID_INVALID);
=20
-        dom =3D op->domain;
-        if ( (dom > 0) && (dom < DOMID_FIRST_RESERVED) )
+        if ( domid =3D=3D DOMID_INVALID )
         {
             ret =3D -EEXIST;
-            if ( !is_free_domid(dom) )
-                break;
-        }
-        else
-        {
-            for ( dom =3D rover + 1; dom !=3D rover; dom++ )
-            {
-                if ( dom =3D=3D DOMID_FIRST_RESERVED )
-                    dom =3D 1;
-                if ( is_free_domid(dom) )
-                    break;
-            }
-
-            ret =3D -ENOMEM;
-            if ( dom =3D=3D rover )
-                break;
-
-            rover =3D dom;
+            break;
         }
=20
-        d =3D domain_create(dom, &op->u.createdomain, false);
+        d =3D domain_create(domid, &op->u.createdomain, false);
         if ( IS_ERR(d) )
         {
+            domid_free(domid);
             ret =3D PTR_ERR(d);
             d =3D NULL;
             break;
diff --git a/xen/common/domid.c b/xen/common/domid.c
new file mode 100644
index 000000000000..7839a2885810
--- /dev/null
+++ b/xen/common/domid.c
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Domain ID allocator.
+ *
+ * Covers dom0 or late hwdom, predefined domains, post-boot domains.
+ * Excludes system domains (ID >=3D DOMID_FIRST_RESERVED).
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include 
+
+static DEFINE_SPINLOCK(domid_lock);
+static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED);
+
+/*
+ * Allocate domain ID.
+ *
+ * @param domid Domain ID hint:
+ * - If an explicit domain ID is provided, verify its availability and use=
 it
+ *   if ID is not used;
+ * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] rang=
e,
+ *   starting from the last used ID. Implementation guarantees that two
+ *   consecutive calls will never return the same ID. ID#0 is reserved for
+ *   the first boot domain (currently, dom0) and excluded from the allocat=
ion
+ *   range.
+ * @return Valid domain ID in case of successful allocation,
+ *         DOMID_INVALID - otherwise.
+ */
+domid_t domid_alloc(domid_t domid)
+{
+    static domid_t domid_last;
+
+    spin_lock(&domid_lock);
+
+    /* Exact match. */
+    if ( domid < DOMID_FIRST_RESERVED )
+    {
+        if ( __test_and_set_bit(domid, domid_bitmap) )
+            domid =3D DOMID_INVALID;
+    }
+    /*
+     * Exhaustive search.
+     *
+     * Domain ID#0 is reserved for the first boot domain (e.g. control dom=
ain)
+     * and excluded from allocation.
+     */
+    else
+    {
+        domid_t num =3D DOMID_FIRST_RESERVED;
+
+        domid =3D find_next_zero_bit(domid_bitmap, num, domid_last + 1);
+        if ( domid =3D=3D num && domid_last !=3D 0 )
+        {
+            num =3D domid_last + 1;
+            domid =3D find_next_zero_bit(domid_bitmap, num, 1);
+        }
+
+        ASSERT(domid <=3D DOMID_FIRST_RESERVED);
+        if ( domid < num )
+        {
+            __set_bit(domid, domid_bitmap);
+            domid_last =3D domid;
+        }
+        else
+            domid =3D DOMID_INVALID;
+    }
+
+    spin_unlock(&domid_lock);
+
+    return domid;
+}
+
+void domid_free(domid_t domid)
+{
+    int rc;
+
+    ASSERT(domid <=3D DOMID_FIRST_RESERVED);
+
+    spin_lock(&domid_lock);
+    rc =3D __test_and_clear_bit(domid, domid_bitmap);
+    spin_unlock(&domid_lock);
+
+    ASSERT(rc);
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615fd..8aab05ae93c8 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -38,6 +38,9 @@ void arch_get_domain_info(const struct domain *d,
=20
 domid_t get_initial_domain_id(void);
=20
+domid_t domid_alloc(domid_t domid);
+void domid_free(domid_t domid);
+
 /* CDF_* constant. Internal flags for domain creation. */
 /* Is this a privileged domain? */
 #define CDF_privileged           (1U << 0)
--=20
2.34.1




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Date: Sat, 09 Aug 2025 17:08:07 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v15 2/4] tools/include: move xc_bitops.h to xen-tools/bitops.h
Message-ID: <20250809170747.1836880-3-dmukhin@ford.com>
In-Reply-To: <20250809170747.1836880-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Move xc_bitops.h to common tools location to be shared between
the toolstack and unit test code.

Adjust the guard in xen-tools/bitops.h

Correct the #include directives and comments referring to the old
xc_bitops.h in the toolstack code.

Signed-off-by: Denis Mukhin 
---
Changes since v14:
- n/a
---
 .../ctrl/xc_bitops.h =3D> include/xen-tools/bitops.h} |  6 +++---
 tools/libs/ctrl/xc_misc.c                           | 13 +++++++------
 tools/libs/guest/xg_dom_elfloader.c                 |  3 ++-
 tools/libs/guest/xg_dom_hvmloader.c                 |  3 ++-
 tools/libs/guest/xg_private.h                       |  2 +-
 tools/libs/guest/xg_sr_common.h                     |  3 +--
 6 files changed, 16 insertions(+), 14 deletions(-)
 rename tools/{libs/ctrl/xc_bitops.h =3D> include/xen-tools/bitops.h} (95%)

diff --git a/tools/libs/ctrl/xc_bitops.h b/tools/include/xen-tools/bitops.h
similarity index 95%
rename from tools/libs/ctrl/xc_bitops.h
rename to tools/include/xen-tools/bitops.h
index 4a776dc3a57f..681482f6759f 100644
--- a/tools/libs/ctrl/xc_bitops.h
+++ b/tools/include/xen-tools/bitops.h
@@ -1,5 +1,5 @@
-#ifndef XC_BITOPS_H
-#define XC_BITOPS_H 1
+#ifndef __XEN_TOOLS_BITOPS_H__
+#define __XEN_TOOLS_BITOPS_H__
=20
 /* bitmap operations for single threaded access */
=20
@@ -81,4 +81,4 @@ static inline void bitmap_or(void *_dst, const void *_oth=
er,
         dst[i] |=3D other[i];
 }
=20
-#endif  /* XC_BITOPS_H */
+#endif  /* __XEN_TOOLS_BITOPS_H__ */
diff --git a/tools/libs/ctrl/xc_misc.c b/tools/libs/ctrl/xc_misc.c
index 33e87bac2868..10ddf85667a9 100644
--- a/tools/libs/ctrl/xc_misc.c
+++ b/tools/libs/ctrl/xc_misc.c
@@ -17,8 +17,8 @@
  * License along with this library; If not, see .
  */
=20
-#include "xc_bitops.h"
 #include "xc_private.h"
+#include 
 #include 
=20
 int xc_get_max_cpus(xc_interface *xch)
@@ -94,11 +94,12 @@ xc_cpumap_t xc_cpumap_alloc(xc_interface *xch)
 }
=20
 /*
- * xc_bitops.h has macros that do this as well - however they assume that
- * the bitmask is word aligned but xc_cpumap_t is only guaranteed to be
- * byte aligned and so we need byte versions for architectures which do
- * not support misaligned accesses (which is basically everyone
- * but x86, although even on x86 it can be inefficient).
+ *  has macros that do this as well - however they
+ * assume that the bitmask is word aligned but xc_cpumap_t is only
+ * guaranteed to be byte aligned and so we need byte versions for
+ * architectures which do not support misaligned accesses (which is
+ * basically everyone but x86, although even on x86 it can be
+ * inefficient).
  *
  * NOTE: The xc_bitops macros now use byte alignment.
  * TODO: Clean up the users of this interface.
diff --git a/tools/libs/guest/xg_dom_elfloader.c b/tools/libs/guest/xg_dom_=
elfloader.c
index f17930d98bf7..8531e90f8e21 100644
--- a/tools/libs/guest/xg_dom_elfloader.c
+++ b/tools/libs/guest/xg_dom_elfloader.c
@@ -25,8 +25,9 @@
 #include 
 #include 
=20
+#include 
+
 #include "xg_private.h"
-#include "xc_bitops.h"
=20
 #define XEN_VER "xen-3.0"
=20
diff --git a/tools/libs/guest/xg_dom_hvmloader.c b/tools/libs/guest/xg_dom_=
hvmloader.c
index 39e1e5f579a7..0f569c20c522 100644
--- a/tools/libs/guest/xg_dom_hvmloader.c
+++ b/tools/libs/guest/xg_dom_hvmloader.c
@@ -24,8 +24,9 @@
 #include 
 #include 
=20
+#include 
+
 #include "xg_private.h"
-#include "xc_bitops.h"
=20
 /* -----------------------------------------------------------------------=
- */
 /* parse elf binary                                                       =
  */
diff --git a/tools/libs/guest/xg_private.h b/tools/libs/guest/xg_private.h
index d73947094f2e..285229cf82a3 100644
--- a/tools/libs/guest/xg_private.h
+++ b/tools/libs/guest/xg_private.h
@@ -28,9 +28,9 @@
 #include 
=20
 #include "xc_private.h"
-#include "xc_bitops.h"
 #include "xenguest.h"
=20
+#include 
 #include 
 #include 
 #include 
diff --git a/tools/libs/guest/xg_sr_common.h b/tools/libs/guest/xg_sr_commo=
n.h
index 2f058ee3a6ff..2e583f2eac72 100644
--- a/tools/libs/guest/xg_sr_common.h
+++ b/tools/libs/guest/xg_sr_common.h
@@ -2,11 +2,10 @@
 #define __COMMON__H
=20
 #include 
+#include 
=20
 #include "xg_private.h"
 #include "xg_save_restore.h"
-#include "xc_bitops.h"
-
 #include "xg_sr_stream_format.h"
=20
 /* String representation of Domain Header types. */
--=20
2.34.1




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Date: Sat, 09 Aug 2025 17:08:13 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall 
Subject: [PATCH v15 3/4] tools/tests: introduce unit tests for domain ID allocator
Message-ID: <20250809170747.1836880-4-dmukhin@ford.com>
In-Reply-To: <20250809170747.1836880-1-dmukhin@ford.com>
References: <20250809170747.1836880-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Introduce some basic infrastructure for doing domain ID allocation unit tes=
ts,
and add a few tests that ensure correctness of the domain ID allocator.

Use  and xen/lib/find-next-bit.c in test hardness code.

Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.

Signed-off-by: Denis Mukhin 
Reviewed-by: Julien Grall 
---
Changes since v14:
- addressed NITs from v14's review
- extended the test for exact IDs allocation (trivial change)
- added Julien's R-b=20
---
 tools/include/xen-tools/bitops.h       | 10 +++
 tools/tests/Makefile                   |  1 +
 tools/tests/domid/.gitignore           |  2 +
 tools/tests/domid/Makefile             | 56 ++++++++++++++++
 tools/tests/domid/harness.h            | 54 +++++++++++++++
 tools/tests/domid/include/xen/domain.h |  1 +
 tools/tests/domid/test-domid.c         | 93 ++++++++++++++++++++++++++
 xen/lib/find-next-bit.c                |  5 ++
 8 files changed, 222 insertions(+)
 create mode 100644 tools/tests/domid/.gitignore
 create mode 100644 tools/tests/domid/Makefile
 create mode 100644 tools/tests/domid/harness.h
 create mode 120000 tools/tests/domid/include/xen/domain.h
 create mode 100644 tools/tests/domid/test-domid.c

diff --git a/tools/include/xen-tools/bitops.h b/tools/include/xen-tools/bit=
ops.h
index 681482f6759f..3b98fba6d74c 100644
--- a/tools/include/xen-tools/bitops.h
+++ b/tools/include/xen-tools/bitops.h
@@ -12,6 +12,16 @@
 #define BITS_PER_LONG 32
 #endif
=20
+#define ffsl(x)       __builtin_ffsl(x)
+
+#define BIT_WORD(nr)  ((nr) / BITS_PER_LONG)
+
+#define BITS_TO_LONGS(bits) \
+    (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
+
+#define DECLARE_BITMAP(name, bits) \
+    unsigned long name[BITS_TO_LONGS(bits)]
+
 #define BITMAP_ENTRY(_nr,_bmap) ((_bmap))[(_nr) / 8]
 #define BITMAP_SHIFT(_nr) ((_nr) % 8)
=20
diff --git a/tools/tests/Makefile b/tools/tests/Makefile
index 36928676a666..94fa80c16880 100644
--- a/tools/tests/Makefile
+++ b/tools/tests/Makefile
@@ -2,6 +2,7 @@ XEN_ROOT =3D $(CURDIR)/../..
 include $(XEN_ROOT)/tools/Rules.mk
=20
 SUBDIRS-y :=3D
+SUBDIRS-y +=3D domid
 SUBDIRS-y +=3D resource
 SUBDIRS-$(CONFIG_X86) +=3D cpu-policy
 SUBDIRS-$(CONFIG_X86) +=3D tsx
diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignore
new file mode 100644
index 000000000000..70e306b3c074
--- /dev/null
+++ b/tools/tests/domid/.gitignore
@@ -0,0 +1,2 @@
+*.o
+test-domid
diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile
new file mode 100644
index 000000000000..d96ceca6d954
--- /dev/null
+++ b/tools/tests/domid/Makefile
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Unit tests for domain ID allocator.
+#
+# Copyright 2025 Ford Motor Company
+
+XEN_ROOT=3D$(CURDIR)/../../..
+include $(XEN_ROOT)/tools/Rules.mk
+
+TESTS :=3D test-domid
+
+vpath domid.c $(XEN_ROOT)/xen/common/
+vpath find-next-bit.c $(XEN_ROOT)/xen/lib/
+
+.PHONY: all
+all: $(TESTS)
+
+.PHONY: run
+run: $(TESTS)
+=09$(foreach t,$(TESTS),./$(t);)
+
+.PHONY: clean
+clean:
+=09$(RM) -- *.o $(TESTS) $(DEPS_RM)
+
+.PHONY: distclean
+distclean: clean
+=09$(RM) -- *~
+
+.PHONY: install
+install: all
+=09$(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests
+=09$(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests
+
+.PHONY: uninstall
+uninstall:
+=09$(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid
+
+CFLAGS +=3D -D__XEN_TOOLS__
+# find-next-bit.c
+CFLAGS +=3D '-DEXPORT_SYMBOL(x)=3D' \
+          -Dfind_first_bit \
+          -Dfind_first_zero_bit \
+          -Dfind_next_bit \
+          -Dfind_next_bit_le \
+          -Dfind_next_zero_bit_le
+CFLAGS +=3D $(APPEND_CFLAGS)
+CFLAGS +=3D $(CFLAGS_xeninclude)
+CFLAGS +=3D -I./include/
+
+LDFLAGS +=3D $(APPEND_LDFLAGS)
+
+test-domid: domid.o find-next-bit.o test-domid.o
+=09$(CC) $^ -o $@ $(LDFLAGS)
+
+-include $(DEPS_INCLUDE)
diff --git a/tools/tests/domid/harness.h b/tools/tests/domid/harness.h
new file mode 100644
index 000000000000..17eb22a9a854
--- /dev/null
+++ b/tools/tests/domid/harness.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Unit test harness for domain ID allocator.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#ifndef _TEST_HARNESS_
+#define _TEST_HARNESS_
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+typedef bool spinlock_t;
+typedef uint16_t domid_t;
+
+extern domid_t domid_alloc(domid_t domid);
+extern void domid_free(domid_t domid);
+
+extern unsigned long find_next_zero_bit(const unsigned long *addr,
+                                        unsigned long size,
+                                        unsigned long offset);
+
+#define __test_and_set_bit(nr, addr)    test_and_set_bit(nr, addr)
+#define __test_and_clear_bit(nr, addr)  test_and_clear_bit(nr, addr)
+#define __set_bit(nr, addr)             set_bit(nr, addr)
+
+#define BUG_ON(x)                       assert(!(x))
+#define ASSERT(x)                       assert(x)
+
+#define DEFINE_SPINLOCK(l)              spinlock_t l
+#define spin_lock(l)                    (assert(!*(l)), *(l) =3D true)
+#define spin_unlock(l)                  (assert(*(l)), *(l) =3D false)
+
+#define printk                          printf
+
+#define DOMID_FIRST_RESERVED            (100)
+#define DOMID_INVALID                   (101)
+
+#endif /* _TEST_HARNESS_ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tools/tests/domid/include/xen/domain.h b/tools/tests/domid/inc=
lude/xen/domain.h
new file mode 120000
index 000000000000..2eda9aed088e
--- /dev/null
+++ b/tools/tests/domid/include/xen/domain.h
@@ -0,0 +1 @@
+../../harness.h
\ No newline at end of file
diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-domid.=
c
new file mode 100644
index 000000000000..51a88a6a9550
--- /dev/null
+++ b/tools/tests/domid/test-domid.c
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Unit tests for domain ID allocator.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include "harness.h"
+
+#define verify(exp, fmt, args...) do { \
+    if ( !(exp) ) \
+        printf(fmt, ## args); \
+    assert(exp); \
+} while (0);
+
+/*
+ * Fail on the first error, since tests are dependent on each other.
+ */
+int main(int argc, char **argv)
+{
+    domid_t expected, allocated;
+
+    /* Test ID cannot be allocated twice. */
+    for ( expected =3D 0; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(expected);
+        verify(allocated =3D=3D expected,
+               "TEST 1: expected %u allocated %u\n", expected, allocated);
+    }
+    for ( expected =3D 0; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(expected);
+        verify(allocated =3D=3D DOMID_INVALID,
+               "TEST 2: expected %u allocated %u\n", DOMID_INVALID, alloca=
ted);
+    }
+
+    /* Ensure all IDs, including ID#0 are not allocated. */
+    for ( expected =3D 0; expected < DOMID_FIRST_RESERVED; expected++ )
+        domid_free(expected);
+
+    /*
+     * Test that that two consecutive calls of domid_alloc(DOMID_INVALID)
+     * will never return the same ID.
+     * NB: ID#0 is reserved and shall not be allocated by
+     * domid_alloc(DOMID_INVALID).
+     */
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(DOMID_INVALID);
+        verify(allocated =3D=3D expected,
+               "TEST 3: expected %u allocated %u\n", expected, allocated);
+    }
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(DOMID_INVALID);
+        verify(allocated =3D=3D DOMID_INVALID,
+               "TEST 4: expected %u allocated %u\n", DOMID_INVALID, alloca=
ted);
+    }
+
+    /* Re-allocate first ID from [1..DOMID_FIRST_RESERVED/2]. */
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED / 2; expected++ =
)
+        domid_free(expected);
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED / 2; expected++ =
)
+    {
+        allocated =3D domid_alloc(DOMID_INVALID);
+        verify(allocated =3D=3D expected,
+               "TEST 5: expected %u allocated %u\n", expected, allocated);
+    }
+
+    /* Re-allocate last ID from [1..DOMID_FIRST_RESERVED - 1]. */
+    expected =3D DOMID_FIRST_RESERVED - 1;
+    domid_free(DOMID_FIRST_RESERVED - 1);
+    allocated =3D domid_alloc(DOMID_INVALID);
+    verify(allocated =3D=3D expected,
+           "TEST 6: expected %u allocated %u\n", expected, allocated);
+
+    /* Allocate an invalid ID. */
+    expected =3D DOMID_INVALID;
+    allocated =3D domid_alloc(DOMID_FIRST_RESERVED);
+    verify(allocated =3D=3D expected,
+           "TEST 7: expected %u allocated %u\n", expected, allocated);
+
+    return 0;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/lib/find-next-bit.c b/xen/lib/find-next-bit.c
index 9b8d7814f20c..539c7f2022b0 100644
--- a/xen/lib/find-next-bit.c
+++ b/xen/lib/find-next-bit.c
@@ -8,8 +8,13 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
+
+#ifdef __XEN_TOOLS__
+#include 
+#else
 #include 
 #include 
+#endif
=20
 #define __ffs(x) (ffsl(x) - 1)
 #define ffz(x) __ffs(~(x))
--=20
2.34.1




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	 IDsuSSj58+iIH9Gfa0A2LqzCPiTHLmnndMWkV/Cf7JxUG0cGyCbdbireGaTHIXknZg
	 zNTljc+rutuDA==
Date: Sat, 09 Aug 2025 17:08:20 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Alejandro Vallejo , Julien Grall 
Subject: [PATCH v15 4/4] xen/domain: update create_dom0() messages
Message-ID: <20250809170747.1836880-5-dmukhin@ford.com>
In-Reply-To: <20250809170747.1836880-1-dmukhin@ford.com>
References: <20250809170747.1836880-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Use %pd for domain identification in error/panic messages in create_dom0().

No functional change.

Signed-off-by: Denis Mukhin 
Reviewed-by: Alejandro Vallejo 
Acked-by: Jan Beulich 
Acked-by: Julien Grall 
---
Changes since v14:
- added Julien's A-b
---
 xen/arch/arm/domain_build.c | 6 +++---
 xen/arch/x86/setup.c        | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 789f2b9d3ce7..02a15d160962 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2084,14 +2084,14 @@ void __init create_dom0(void)
         panic("Error creating domain 0 (rc =3D %ld)\n", PTR_ERR(dom0));
=20
     if ( llc_coloring_enabled && (rc =3D dom0_set_llc_colors(dom0)) )
-        panic("Error initializing LLC coloring for domain 0 (rc =3D %d)\n"=
, rc);
+        panic("Error initializing LLC coloring for %pd (rc =3D %d)\n", dom=
0, rc);
=20
     if ( vcpu_create(dom0, 0) =3D=3D NULL )
-        panic("Error creating domain 0 vcpu0\n");
+        panic("Error creating %pdv0\n", dom0);
=20
     rc =3D construct_dom0(dom0);
     if ( rc )
-        panic("Could not set up DOM0 guest OS (rc =3D %d)\n", rc);
+        panic("Could not set up %pd guest OS (rc =3D %d)\n", dom0, rc);
=20
     set_xs_domain(dom0);
 }
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 398da734c0c5..bf21c55f7193 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1084,7 +1084,7 @@ static struct domain *__init create_dom0(struct boot_=
info *bi)
=20
         if ( (strlen(acpi_param) =3D=3D 0) && acpi_disabled )
         {
-            printk("ACPI is disabled, notifying Domain 0 (acpi=3Doff)\n");
+            printk("ACPI is disabled, notifying %pd (acpi=3Doff)\n", d);
             safe_strcpy(acpi_param, "off");
         }
=20
@@ -1099,7 +1099,7 @@ static struct domain *__init create_dom0(struct boot_=
info *bi)
=20
     bd->d =3D d;
     if ( construct_dom0(bd) !=3D 0 )
-        panic("Could not construct domain 0\n");
+        panic("Could not construct %pd\n", d);
=20
     bd->cmdline =3D NULL;
     xfree(cmdline);
--=20
2.34.1




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Date: Sat, 09 Aug 2025 17:15:04 +0000
To: Mykola Kvach 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk 
Subject: Re: [PATCH] xen/arm: irq: add missing spin_unlock() in init_local_irq_data() error path
Message-ID: 
In-Reply-To: 
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On Sat, Aug 09, 2025 at 05:32:41PM +0300, Mykola Kvach wrote:
> From: Mykola Kvach 
>=20
> If init_one_irq_desc() fails, init_local_irq_data() returns without
> releasing local_irqs_type_lock, leading to a possible deadlock.
>=20
> Release the lock before returning to ensure proper cleanup.
>=20
> Signed-off-by: Mykola Kvach 

Nice catch!

Please consider:

Reviewed-by: Denis Mukhin =20

> ---
>  xen/arch/arm/irq.c | 3 +++
>  1 file changed, 3 insertions(+)
>=20
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 4bbf0b0664..02ca82c089 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -94,7 +94,10 @@ static int init_local_irq_data(unsigned int cpu)
>          int rc =3D init_one_irq_desc(desc);
>=20
>          if ( rc )
> +        {
> +            spin_unlock(&local_irqs_type_lock);
>              return rc;
> +        }
>=20
>          desc->irq =3D irq;
>          desc->action  =3D NULL;
> --
> 2.48.1
>=20
>=20



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Date: Sat, 09 Aug 2025 18:37:07 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 5/8] emul/vuart-ns16550: introduce NS16550-compatible UART emulator (x86)
Message-ID: 
In-Reply-To: <5c0589a2-91fe-484d-bded-5a68a1626355@suse.com>
References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-6-dmukhin@ford.com> <5c0589a2-91fe-484d-bded-5a68a1626355@suse.com>
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On Mon, Aug 04, 2025 at 12:53:36PM +0200, Jan Beulich wrote:
> On 31.07.2025 21:22, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Add initial in-hypervisor emulator for NS8250/NS16x50-compatible UARTs =
under
> > CONFIG_VUART_NS16550 for x86 port of Xen.
> >
> > x86 port of Xen lacks vUART facility similar to Arm's SBSA emulator to =
support
> > x86 guest OS bring up in the embedded setups.
> >
> > In parallel domain creation scenario (hyperlaunch), NS16550 emulator he=
lps
> > early guest firmware and/or OS bringup debugging, because it eliminates
> > dependency on the external emulator (qemu) being operational by the tim=
e
> > domains are created.
> >
> > The emulator also allows to forward the physical console input to the x=
86
> > domain which is useful when a system has only one physical UART for ear=
ly
> > debugging and this UART is owned by Xen. Such functionality is limited =
to dom0
> > use currently.
> >
> > By default, CONFIG_VUART_NS16550 enables emulation of NS16550 at I/O po=
rt
> > 0x3f8, IRQ#4 in guest OS (legacy COM1).
> >
> > Legacy COM resources can be selected at built-time and cannot be config=
ured
> > per-domain via .cfg or DT yet.
> >
> > Introduce new emulation flag for virtual UART on x86 and plumb it throu=
gh
> > domain creation code so NS16550 emulator can be instantiated properly.
> >
> > Please refer to the NS16550 emulator code for full list of limitations.
> >
> > Signed-off-by: Denis Mukhin 
> > ---
> > Changes since v3:
> > - feedback addressed
> > - adjusted to new vUART framework APIs
> > - Link to v3: https://lore.kernel.org/xen-devel/20250103-vuart-ns8250-v=
3-v1-21-c5d36b31d66c@ford.com/
> > ---
> >  xen/arch/x86/hvm/hvm.c                |    9 +
> >  xen/arch/x86/include/asm/domain.h     |    4 +-
> >  xen/arch/x86/include/asm/hvm/domain.h |    4 +
> >  xen/common/emul/vuart/Kconfig         |   48 ++
> >  xen/common/emul/vuart/Makefile        |    1 +
> >  xen/common/emul/vuart/vuart-ns16550.c | 1009 +++++++++++++++++++++++++
> >  xen/common/emul/vuart/vuart.c         |    4 +
> >  xen/include/public/arch-x86/xen.h     |    4 +-
> >  xen/include/xen/resource.h            |    3 +
> >  9 files changed, 1084 insertions(+), 2 deletions(-)
> >  create mode 100644 xen/common/emul/vuart/vuart-ns16550.c
>=20
> Overall I think this patch is too large to sensibly review. Surely base s=
tructure
> and then (incrementally) fleshing out of the hooks can be separated from =
one
> another?

I'll do a split.

>=20
> > --- a/xen/arch/x86/hvm/hvm.c
> > +++ b/xen/arch/x86/hvm/hvm.c
> > @@ -31,6 +31,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -702,6 +703,10 @@ int hvm_domain_initialise(struct domain *d,
> >      if ( rc !=3D 0 )
> >          goto fail1;
> >
> > +    rc =3D vuart_init(d, NULL);
> > +    if ( rc !=3D 0 )
> > +        goto out_vioapic_deinit;
> > +
> >      stdvga_init(d);
> >
> >      rtc_init(d);
> > @@ -725,6 +730,8 @@ int hvm_domain_initialise(struct domain *d,
> >      return 0;
> >
> >   fail2:
> > +    vuart_deinit(d);
> > + out_vioapic_deinit:
> >      vioapic_deinit(d);
> >   fail1:
> >      if ( is_hardware_domain(d) )
>=20
> Would be better if vuart_deinit() was idempotent, and hence could be call=
ed
> unconditionally here.

Agree, vuart_deinit() is idempotent even in this submisson.
Will update.

>=20
> > @@ -787,6 +794,8 @@ void hvm_domain_destroy(struct domain *d)
> >      if ( hvm_funcs.domain_destroy )
> >          alternative_vcall(hvm_funcs.domain_destroy, d);
> >
> > +    vuart_deinit(d);
>=20
> You require a fair level of idempotency already anyway, as a domain may n=
ot
> have any vUART, so this call already needs to be "capabale" of doing noth=
ing.
>=20
> > --- a/xen/arch/x86/include/asm/hvm/domain.h
> > +++ b/xen/arch/x86/include/asm/hvm/domain.h
> > @@ -149,6 +149,10 @@ struct hvm_domain {
> >  #ifdef CONFIG_MEM_SHARING
> >      struct mem_sharing_domain mem_sharing;
> >  #endif
> > +
> > +#ifdef CONFIG_VUART_NS16550
> > +    void *vuart; /* Virtual UART handle. */
> > +#endif
> >  };
>=20
> With your framework you allow for multiple vUART drivers. Either the fiel=
d
> looks misnamed or the CONFIG_* option checked is the wrong one.

Agree; will update.

>=20
> Also, why's this x86-specific? NS16550s can exist anywhere, can't they?
> (The present, but presumably temporary tying to x86 looks to be the use o=
f
> I/O ports.)

struct hvm_domain is arch-specific.

I do not think I need to add NS16550 to, say RISC-V's, hvm_domain without
implementing MMIO part and guest DT-binding generation.

>=20
> > --- a/xen/common/emul/vuart/Kconfig
> > +++ b/xen/common/emul/vuart/Kconfig
> > @@ -3,4 +3,52 @@ config HAS_VUART
> >
> >  menu "UART Emulation"
> >
> > +config VUART_NS16550
> > +=09bool "NS16550-compatible UART Emulation" if EXPERT
> > +=09depends on X86 && HVM
> > +=09select HAS_VUART
> > +=09help
> > +=09  In-hypervisor NS16550/NS16x50 UART emulation.
> > +
> > +=09  Only legacy PC I/O ports are emulated.
> > +
> > +=09  This is strictly for testing purposes (such as early HVM guest co=
nsole),
> > +=09  and not appropriate for use in production.
> > +
> > +choice VUART_NS16550_PC
> > +=09prompt "IBM PC COM resources"
> > +=09depends on VUART_NS16550
> > +=09default VUART_NS16550_PC_COM1
> > +=09help
> > +=09  Default emulated NS16550 resources.
> > +
> > +config VUART_NS16550_PC_COM1
> > +=09bool "COM1 (I/O port 0x3f8, IRQ#4)"
> > +
> > +config VUART_NS16550_PC_COM2
> > +=09bool "COM2 (I/O port 0x2f8, IRQ#3)"
> > +
> > +config VUART_NS16550_PC_COM3
> > +=09bool "COM3 (I/O port 0x3e8, IRQ#4)"
> > +
> > +config VUART_NS16550_PC_COM4
> > +=09bool "COM4 (I/O port 0x2e8, IRQ#3)"
> > +
> > +endchoice
> > +
> > +config VUART_NS16550_LOG_LEVEL
> > +=09int "UART emulator verbosity level"
> > +=09range 0 3
> > +=09default "1"
> > +=09depends on VUART_NS16550
> > +=09help
> > +=09  Set the default log level of UART emulator.
> > +=09  See include/xen/config.h for more details.
>=20
> For someone merely running kconfig but not otherwise knowing the sources,
> this isn't an overly helful pointer. But I question the need for such a
> control anyway, and I think I did say so already before.

I'll drop that Kconfig setting.

>=20
> > +config VUART_NS16550_DEBUG
> > +=09bool "UART emulator development debugging"
> > +=09depends on VUART_NS16550
>=20
> && DEBUG ?

I will drop that Kconfig.

>=20
> > --- a/xen/common/emul/vuart/Makefile
> > +++ b/xen/common/emul/vuart/Makefile
> > @@ -1 +1,2 @@
> >  obj-$(CONFIG_HAS_VUART) +=3D vuart.o
> > +obj-$(CONFIG_VUART_NS16550) +=3D vuart-ns16550.o
>=20
> I don't think files in this directory need a vuart- name prefix.

Ack.

Hmm, there's already ns16550.c which is UART driver, so it may be confusing=
 to
have two ns16550s (although in different directories).

I do not have a strong preference on the naming here.

>=20
> > --- /dev/null
> > +++ b/xen/common/emul/vuart/vuart-ns16550.c
> > @@ -0,0 +1,1009 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * NS16550-compatible UART Emulator.
> > + *
> > + * See:
> > + * - Serial and UART Tutorial:
> > + *     https://download.freebsd.org/doc/en/articles/serial-uart/serial=
-uart_en.pdf
> > + * - UART w/ 16 byte FIFO:
> > + *     https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
> > + * - UART w/ 64 byte FIFO:
> > + *     https://www.ti.com/lit/ds/symlink/tl16c750.pdf
> > + *
> > + * Limitations:
> > + * - Only x86;
> > + * - Only HVM domains support (build-time), PVH domains are not suppor=
ted yet;
> > + * - Only legacy COM{1,2,3,4} resources via Kconfig, custom I/O ports/=
IRQs
> > + *   are not supported;
> > + * - Only Xen console as a backend, no inter-domain communication (sim=
ilar to
> > + *   vpl011 on Arm);
> > + * - Only 8n1 emulation (8-bit data, no parity, 1 stop bit);
> > + * - No toolstack integration;
> > + * - No baud rate emulation (reports 115200 baud to the guest OS);
> > + * - No FIFO-less mode emulation;
> > + * - No RX FIFO interrupt moderation (FCR) emulation;
> > + * - No integration w/ VM snapshotting (HVM_REGISTER_SAVE_RESTORE() an=
d
> > + *   friends);
> > + * - No ISA IRQ sharing allowed;
> > + * - No MMIO-based UART emulation.
> > + */
> > +
> > +#define pr_prefix               "ns16550"
> > +#define pr_fmt(fmt)             pr_prefix ": " fmt
> > +#define pr_log_level            CONFIG_VUART_NS16550_LOG_LEVEL
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include 
>=20
> Except for cases where Xen itself runs as a guest, I don't think any of t=
hese
> headers should be used in Xen sources. If I'm not mistaken, ...

I'll double check, thanks.

>=20
> > +/*
> > + * Virtual NS16550 device state.
> > + */
> > +struct vuart_ns16550 {
> > +    struct xencons_interface cons;      /* Emulated RX/TX FIFOs */
>=20
> ... this also isn't to communicate with some remote, but merely to use so=
me
> of the fields conveniently.

The plan is to add peer-to-peer connection over vUART similarly to existing
vpl011.

>=20
> > +    uint8_t regs[NS16550_EMU_REGS_NUM]; /* Emulated registers */
> > +    unsigned int irq;                   /* Emulated IRQ# */
> > +    uint64_t io_addr;                   /* Emulated I/O region base ad=
dress */
> > +    uint64_t io_size;                   /* Emulated I/O region size */
>=20
> These are huge; for the size that's true even if considering future MMIO-
> based emulation.

Ack.

>=20
> > +    const char *name;                   /* Device name */
> > +    struct domain *owner;               /* Owner domain */
> > +    spinlock_t lock;                    /* Protection */
> > +};
> > +
> > +/*
> > + * Virtual device description.
> > + */
> > +struct virtdev_desc {
> > +    const char *name;
> > +    const struct resource *res;
> > +};
> > +
> > +/*
> > + * Legacy IBM PC NS16550 resources.
> > + * There are only 4 I/O port ranges, hardcoding all of them here.
> > + */
> > +static const struct virtdev_desc x86_pc_uarts[4] =3D {
> > +    [0] =3D {
> > +        .name =3D "COM1",
> > +        .res =3D (const struct resource[]){
> > +            { .type =3D IORESOURCE_IO,  .addr =3D 0x3f8, .size =3D NS1=
6550_REGS_NUM },
> > +            { .type =3D IORESOURCE_IRQ, .addr =3D 4,     .size =3D 1 }=
,
> > +            { .type =3D IORESOURCE_UNKNOWN },
> > +        },
> > +    },
> > +    [1] =3D {
> > +        .name =3D "COM2",
> > +        .res =3D (const struct resource[]){
> > +            { .type =3D IORESOURCE_IO,  .addr =3D 0x2f8, .size =3D NS1=
6550_REGS_NUM },
> > +            { .type =3D IORESOURCE_IRQ, .addr =3D 3,     .size =3D 1 }=
,
> > +            { .type =3D IORESOURCE_UNKNOWN },
> > +        },
> > +    },
> > +    [2] =3D {
> > +        .name =3D "COM3",
> > +        .res =3D (const struct resource[]){
> > +            { .type =3D IORESOURCE_IO,  .addr =3D 0x3e8, .size =3D NS1=
6550_REGS_NUM },
> > +            { .type =3D IORESOURCE_IRQ, .addr =3D 4,     .size =3D 1 }=
,
> > +            { .type =3D IORESOURCE_UNKNOWN },
> > +        },
> > +    },
> > +    [3] =3D {
> > +        .name =3D "COM4",
> > +        .res =3D (const struct resource[]){
> > +            { .type =3D IORESOURCE_IO,  .addr =3D 0x2e8, .size =3D NS1=
6550_REGS_NUM },
> > +            { .type =3D IORESOURCE_IRQ, .addr =3D 3,     .size =3D 1 }=
,
> > +            { .type =3D IORESOURCE_UNKNOWN },
> > +        },
> > +    },
> > +};
>=20
> The choice of COMn is at build time. Why do we need all four configuratio=
ns
> resident not only in the binary, but even at (post-init) runtime? Also, t=
he
> way you do initialization of .res, I think adding __initconst to the main
> array wouldn't have the effect of pulling all those inti .init.* as well.
> For the time being I simply don't see the need for the extra level of
> indirection: All instances have two entries (plus the then likely not
> necessary sentinel).

Will rework that.

>=20
> > +static bool cf_check ns16550_iir_check_lsi(const struct vuart_ns16550 =
*vdev)
> > +{
> > +    return !!(vdev->regs[UART_LSR] & UART_LSR_MASK);
>=20
> No need for !! (also elsewhere).

Ack.

>=20
> > --- a/xen/include/xen/resource.h
> > +++ b/xen/include/xen/resource.h
> > @@ -31,4 +31,7 @@ struct resource {
> >
> >  #define resource_size(res)      ((res)->size)
> >
> > +#define for_each_resource(res) \
> > +    for ( ; (res) && (res)->type !=3D IORESOURCE_UNKNOWN; (res)++ )
>=20
> I'm not sure this is a good generic #define; imo it wants keeping local t=
o
> the one file that uses it.

Ack.

>=20
> Jan
>=20



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Date: Sat, 09 Aug 2025 18:55:39 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators
Message-ID: 
In-Reply-To: 
References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-3-dmukhin@ford.com> 
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On Mon, Aug 04, 2025 at 12:11:03PM +0200, Jan Beulich wrote:
> On 31.07.2025 21:21, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Introduce a driver framework to abstract UART emulators in the hypervis=
or.
> >
> > That allows for architecture-independent handling of virtual UARTs in t=
he
> > console driver and simplifies enabling new UART emulators.
> >
> > The framework is built under CONFIG_HAS_VUART, which will be automatica=
lly
> > enabled once the user enables any UART emulator.
>=20
> Yet then still - why "HAS"? Call it just VUART or VUART_FRAMEWORK or some=
 such.
>=20
> > --- a/xen/common/Kconfig
> > +++ b/xen/common/Kconfig
> > @@ -1,6 +1,8 @@
> >
> >  menu "Common Features"
> >
> > +source "common/emul/Kconfig"
> > +
> >  config COMPAT
>=20
> Why at the very top?

I did not find a better place, since the settings are not sorted and to me =
it
makes sense to list emulation capabilities first...

Where would be the best location for that submenu?
Close to another submenu `source "common/sched/Kconfig"`?

>=20
> > --- a/xen/common/Makefile
> > +++ b/xen/common/Makefile
> > @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) +=3D d=
evice.o
> >  obj-$(CONFIG_DEVICE_TREE_PARSE) +=3D device-tree/
> >  obj-$(CONFIG_IOREQ_SERVER) +=3D dm.o
> >  obj-y +=3D domain.o
> > +obj-y +=3D emul/
> >  obj-y +=3D event_2l.o
> >  obj-y +=3D event_channel.o
> >  obj-$(CONFIG_EVTCHN_FIFO) +=3D event_fifo.o
> > diff --git a/xen/common/emul/Kconfig b/xen/common/emul/Kconfig
> > new file mode 100644
> > index 000000000000..7c6764d1756b
> > --- /dev/null
> > +++ b/xen/common/emul/Kconfig
> > @@ -0,0 +1,6 @@
> > +menu "Domain Emulation Features"
> > +=09visible if EXPERT
> > +
> > +source "common/emul/vuart/Kconfig"
> > +
> > +endmenu
> > diff --git a/xen/common/emul/Makefile b/xen/common/emul/Makefile
> > new file mode 100644
> > index 000000000000..670682102c13
> > --- /dev/null
> > +++ b/xen/common/emul/Makefile
> > @@ -0,0 +1 @@
> > +obj-$(CONFIG_HAS_VUART) +=3D vuart/
>=20
> With this you can ...
>=20
> > --- /dev/null
> > +++ b/xen/common/emul/vuart/Makefile
> > @@ -0,0 +1 @@
> > +obj-$(CONFIG_HAS_VUART) +=3D vuart.o
>=20
> ... use the simpler obj-y here.

Thanks.

>=20
> > --- /dev/null
> > +++ b/xen/common/emul/vuart/vuart.c
> > @@ -0,0 +1,112 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * UART emulator framework.
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define VUART_ARRAY_SIZE    (__start_vuart_end - __start_vuart_array)
> > +
> > +#define for_each_vuart(vdev) \
> > +    for (unsigned __i =3D 0; \
> > +         __i < VUART_ARRAY_SIZE && (vdev =3D __start_vuart_array[__i],=
 1); \
> > +         __i++)
>=20
> Nit: Xen style please. Any preferably no leading underscores; in no case
> two of them.

Ack.

>=20
> > +extern const struct vuart_ops *const __start_vuart_array[];
> > +extern const struct vuart_ops *const __start_vuart_end[];
>=20
> Is there an actual need for this extra level of indirection? It is in the
> process of being done away with for vPCI.

Ack.

>=20
> > +int vuart_add_node(struct domain *d, const void *node)
> > +{
> > +    const struct vuart_ops *vdev;
> > +    int rc;
> > +
> > +    for_each_vuart(vdev)
> > +    {
> > +        if ( !vdev->add_node )
> > +            continue;
> > +
> > +        rc =3D vdev->add_node(d, node);
>=20
> Here and below - shouldn't you call hooks only when the kind of driver is
> actually enabled for the domkain in question?

Thanks; this looks a bit raw...

I will rework that in the follow on change. I will drop vuart_add_node()
from NS16550 series since it is not used yet.

>=20
> > +        if ( rc )
> > +            return rc;
> > +    }
> > +
> > +    return 0;
> > +}
> > +
> > +int vuart_init(struct domain *d, struct vuart_params *params)
> > +{
> > +    const struct vuart_ops *vdev;
> > +    int rc;
> > +
> > +    if ( !domain_has_vuart(d) )
> > +        return 0;
> > +
> > +    for_each_vuart(vdev)
> > +    {
> > +        rc =3D vdev->init(d, params);
> > +        if ( rc )
> > +            return rc;
> > +    }
> > +
> > +    d->console.input_allowed =3D true;
>=20
> Unconditionally?

Thanks.
That should be a least under rc =3D=3D 0.

>=20
> > +void vuart_deinit(struct domain *d)
> > +{
> > +    const struct vuart_ops *vdev;
> > +
> > +    for_each_vuart(vdev)
> > +        vdev->deinit(d);
> > +}
>=20
> I can perhaps see why this hook wants to uniformly be set, but ...
>=20
> > +void vuart_dump_state(const struct domain *d)
> > +{
> > +    const struct vuart_ops *vdev;
> > +
> > +    for_each_vuart(vdev)
> > +        vdev->dump_state(d);
> > +}
>=20
> ... state dumping pretty surely wants to be optional?

Ack.

>=20
> > +/*
> > + * Put character to the first suitable emulated UART's FIFO.
> > + */
>=20
> What's "suitable"? Along the lines of the earlier remark, what if the dom=
ain
> has vUART kind A configured, ...

"suitable" is meant to be the first emulator with put_rx !=3D NULL.
I will update that.

>=20
> > +int vuart_put_rx(struct domain *d, char c)
> > +{
> > +    const struct vuart_ops *vdev =3D NULL;
> > +
> > +    ASSERT(domain_has_vuart(d));
> > +
> > +    for_each_vuart(vdev)
> > +        if ( vdev->put_rx )
>=20
> ... but only kind B offers this hook?
>=20
> > +            break;
> > +
> > +    return vdev ? vdev->put_rx(d, c) : -ENODEV;
>=20
> The check for NULL helps for the "no vUART drivers" case, but it won't
> help if you exhausted the array without finding a driver with the wanted
> hook.

Ack.

>=20
> > +}
> > +
> > +bool domain_has_vuart(const struct domain *d)
> > +{
> > +    uint32_t mask =3D 0;
>=20
> unsigned int?

Ack.

>=20
> > --- a/xen/common/keyhandler.c
> > +++ b/xen/common/keyhandler.c
> > @@ -22,6 +22,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >
> >  static unsigned char keypress_key;
> > @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char key=
)
> >                             v->periodic_period / 1000000);
> >              }
> >          }
> > +
> > +        vuart_dump_state(d);
>=20
> How verbose is this going to get?

Looks something like this:
```
(XEN) [   88.334893] 'q' pressed -> dumping domain info (now =3D 8833482830=
3)
[..]
(XEN) [   88.335673] Virtual ns16550 (COM2) I/O port 0x02f8 IRQ#3 owner d0
(XEN) [   88.335681]   RX FIFO size 1024 in_prod 258 in_cons 258 used 0
(XEN) [   88.335689]   TX FIFO size 2048 out_prod 15 out_cons 0 used 15
(XEN) [   88.335696]   00 RBR 02 THR 6f DLL 01 DLM 00
(XEN) [   88.335703]   01 IER 05
(XEN) [   88.335709]   02 FCR 81 IIR c1
(XEN) [   88.335715]   03 LCR 13
(XEN) [   88.335720]   04 MCR 0b
(XEN) [   88.335726]   05 LSR 60
(XEN) [   88.335731]   06 MSR b0
(XEN) [   88.335736]   07 SCR 00

```

>=20
> > --- /dev/null
> > +++ b/xen/include/xen/vuart.h
> > @@ -0,0 +1,84 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * UART emulator framework.
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#ifndef XEN_VUART_H
> > +#define XEN_VUART_H
> > +
> > +#include 
> > +#include 
> > +#include 
>=20
> The order is wrong - types must be available before public headers are in=
cluded.

Ack.

>=20
> > +struct vuart_params {
> > +    domid_t console_domid;
> > +    gfn_t gfn;
> > +    evtchn_port_t evtchn;
> > +};
> > +
> > +struct vuart_ops {
> > +    int (*add_node)(struct domain *d, const void *node);
> > +    int (*init)(struct domain *d, struct vuart_params *params);
> > +    void (*deinit)(struct domain *d);
> > +    void (*dump_state)(const struct domain *d);
> > +    int (*put_rx)(struct domain *d, char c);
> > +};
> > +
> > +#define VUART_REGISTER(name, x) \
> > +    static const struct vuart_ops *const __name##_entry \
> > +        __used_section(".data.vuart." #name) =3D (x);
> > +
> > +#ifdef CONFIG_HAS_VUART
> > +
> > +int vuart_add_node(struct domain *d, const void *node);
> > +int vuart_init(struct domain *d, struct vuart_params *params);
> > +void vuart_deinit(struct domain *d);
> > +void vuart_dump_state(const struct domain *d);
> > +int vuart_put_rx(struct domain *d, char c);
> > +bool domain_has_vuart(const struct domain *d);
> > +
> > +#else
> > +
> > +static inline int vuart_add_node(struct domain *d, const void *node)
> > +{
> > +    return 0;
> > +}
> > +
> > +static inline int vuart_init(struct domain *d, struct vuart_params *pa=
rams)
> > +{
> > +    return 0;
> > +}
> > +
> > +static inline void vuart_deinit(struct domain *d)
> > +{
> > +}
> > +
> > +static inline void vuart_dump_state(const struct domain *d)
> > +{
> > +}
> > +
> > +static inline int vuart_put_rx(struct domain *d, char c)
> > +{
> > +    ASSERT_UNREACHABLE();
> > +    return -ENODEV;
> > +}
> > +
> > +static inline bool domain_has_vuart(const struct domain *d)
> > +{
> > +    return false;
> > +}
>=20
> With this, some of the other stubs should not be necessary. Declarations
> will suffice, e.g. for vuart_put_rx().

Thanks, will update.

>=20
> > --- a/xen/include/xen/xen.lds.h
> > +++ b/xen/include/xen/xen.lds.h
> > @@ -194,4 +194,14 @@
> >  #define VPCI_ARRAY
> >  #endif
> >
> > +#ifdef CONFIG_HAS_VUART
> > +#define VUART_ARRAY     \
> > +       . =3D ALIGN(POINTER_ALIGN); \
> > +       __start_vuart_array =3D .;  \
> > +       *(SORT(.data.vuart.*))    \
>=20
> This is r/o data afaict, so would want naming .rodata.vuart.*. Which in
> turn means the uses of the macros need to move up in the linker scripts.

Ack.

>=20
> Jan
>=20



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Samuel Thibault ,
	Juergen Gross 
Subject: [PATCH 4/5] stubdom: Fix -Wimplicit-int in newlib
Date: Sat,  9 Aug 2025 23:12:05 +0100
Message-Id: <20250809221206.1260861-5-andrew.cooper3@citrix.com>
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This is an error now Debian Trixie's gcc-14

Signed-off-by: Andrew Cooper 
---
CC: Anthony PERARD 
CC: Michal Orzel 
CC: Jan Beulich 
CC: Julien Grall 
CC: Roger Pau Monné 
CC: Stefano Stabellini 
CC: Samuel Thibault 
CC: Juergen Gross 

I really think we need to move onto Unikraft as a maintained base...
---
 stubdom/Makefile               |  1 +
 stubdom/newlib-fix-etext.patch | 23 +++++++++++++++++++++++
 2 files changed, 24 insertions(+)
 create mode 100644 stubdom/newlib-fix-etext.patch

diff --git a/stubdom/Makefile b/stubdom/Makefile
index 666c3221dcd7..9aa0d3dee4de 100644
--- a/stubdom/Makefile
+++ b/stubdom/Makefile
@@ -94,6 +94,7 @@ newlib-$(NEWLIB_VERSION): newlib-$(NEWLIB_VERSION).tar.gz
 	patch -d $@ -p1 < newlib-cygmon-gmon.patch
 	patch -d $@ -p1 < newlib-makedoc.patch
 	patch -d $@ -p1 < newlib-fix-copy_past_newline.patch
+	patch -d $@ -p1 < newlib-fix-etext.patch
 	find $@ -type f | xargs perl -i.bak \
 		-pe 's/\b_(tzname|daylight|timezone)\b/$$1/g'
 	touch $@
diff --git a/stubdom/newlib-fix-etext.patch b/stubdom/newlib-fix-etext.patch
new file mode 100644
index 000000000000..e7bd4bb0cead
--- /dev/null
+++ b/stubdom/newlib-fix-etext.patch
@@ -0,0 +1,23 @@
+GCC-14 in Debian Trixie i386 complains:
+
+../../../../newlib-1.16.0/libgloss/i386/cygmon-gmon.c: In function '_mcount':
+../../../../newlib-1.16.0/libgloss/i386/cygmon-gmon.c:227:14: error: type defaults to 'int' in declaration of '_etext' [-Wimplicit-int]
+  227 |       extern _etext();
+      |              ^~~~~~
+../../../../newlib-1.16.0/libgloss/i386/cygmon-gmon.c:228:14: error: type defaults to 'int' in declaration of '_ftext' [-Wimplicit-int]
+  228 |       extern _ftext();
+      |              ^~~~~~
+
+--- newlib-1.16.0/libgloss/i386/cygmon-gmon.c.orig	2025-08-09 22:48:09.864068481 +0100
++++ newlib-1.16.0/libgloss/i386/cygmon-gmon.c	2025-08-09 22:52:18.458393484 +0100
+@@ -224,8 +224,8 @@
+ 
+   if (! already_setup) 
+     {
+-      extern _etext();
+-      extern _ftext();
++      extern char _etext[];
++      extern char _ftext[];
+       already_setup = 1;
+       monstartup(_ftext, _etext);
+       atexit(_mcleanup);
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Shawn Anastasio ,
	Oleksii Kurochko ,
	Doug Goldstein ,
	=?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Victor Lira 
Subject: [PATCH 2/5] CI: Update ppc64 to use Debian Trixie
Date: Sat,  9 Aug 2025 23:12:03 +0100
Message-Id: <20250809221206.1260861-3-andrew.cooper3@citrix.com>
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Everything works fine with Debian 13.  Provide two new build jobs (for a total
of 6), and update the test job.

Signed-off-by: Andrew Cooper 
---
CC: Anthony PERARD 
CC: Michal Orzel 
CC: Jan Beulich 
CC: Julien Grall 
CC: Roger Pau Monné 
CC: Stefano Stabellini 
CC: Shawn Anastasio 
CC: Oleksii Kurochko 
CC: Doug Goldstein 
CC: Marek Marczykowski-Górecki 
CC: Victor Lira 

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1975927256
---
 automation/gitlab-ci/build.yaml | 18 ++++++++++++++++--
 automation/gitlab-ci/test.yaml  |  2 +-
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index ab5211f77e5e..3fe539dc5683 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -319,10 +319,10 @@ debian-12-x86_64-clang-debug:
   variables:
     CONTAINER: debian:12-x86_64
 
-debian-12-ppc64le-gcc-debug:
+debian-13-ppc64le-gcc-debug:
   extends: .gcc-ppc64le-cross-build-debug
   variables:
-    CONTAINER: debian:12-ppc64le
+    CONTAINER: debian:13-ppc64le
     KBUILD_DEFCONFIG: ppc64_defconfig
     HYPERVISOR_ONLY: y
     EXTRA_XEN_CONFIG: |
@@ -705,6 +705,20 @@ debian-12-ppc64le-gcc:
     KBUILD_DEFCONFIG: ppc64_defconfig
     HYPERVISOR_ONLY: y
 
+debian-12-ppc64le-gcc-debug:
+  extends: .gcc-ppc64le-cross-build-debug
+  variables:
+    CONTAINER: debian:12-ppc64le
+    KBUILD_DEFCONFIG: ppc64_defconfig
+    HYPERVISOR_ONLY: y
+
+debian-13-ppc64le-gcc:
+  extends: .gcc-ppc64le-cross-build
+  variables:
+    CONTAINER: debian:13-ppc64le
+    KBUILD_DEFCONFIG: ppc64_defconfig
+    HYPERVISOR_ONLY: y
+
 # RISC-V 64 cross-build
 debian-12-riscv64-gcc:
   extends: .gcc-riscv64-cross-build
diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
index 1f0b27b2378a..2f6f3affa637 100644
--- a/automation/gitlab-ci/test.yaml
+++ b/automation/gitlab-ci/test.yaml
@@ -712,4 +712,4 @@ qemu-smoke-ppc64le-powernv9-gcc:
   script:
     - ./automation/scripts/qemu-smoke-ppc64le.sh powernv9 2>&1 | tee ${LOGFILE}
   needs:
-    - debian-12-ppc64le-gcc-debug
+    - debian-13-ppc64le-gcc-debug
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Shawn Anastasio ,
	Oleksii Kurochko ,
	Doug Goldstein ,
	=?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Victor Lira 
Subject: [PATCH 1/5] CI: Trixie containers
Date: Sat,  9 Aug 2025 23:12:02 +0100
Message-Id: <20250809221206.1260861-2-andrew.cooper3@citrix.com>
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Debian Trixie has been released.  Provide new containers.

Signed-off-by: Andrew Cooper 
---
CC: Anthony PERARD 
CC: Michal Orzel 
CC: Jan Beulich 
CC: Julien Grall 
CC: Roger Pau Monné 
CC: Stefano Stabellini 
CC: Shawn Anastasio 
CC: Oleksii Kurochko 
CC: Doug Goldstein 
CC: Marek Marczykowski-Górecki 
CC: Victor Lira 

I've deployed these containers already so people can play.

No ARM yet.  There's an (old) outstanding series cleaning up the arm
infrastructure, blocked on unclear root requirements for the Xilinx runners.
That series really needs fixing.
---
 automation/build/debian/13-ppc64le.dockerfile | 37 ++++++++++
 automation/build/debian/13-riscv64.dockerfile | 37 ++++++++++
 automation/build/debian/13-x86_32.dockerfile  | 51 +++++++++++++
 automation/build/debian/13-x86_64.dockerfile  | 74 +++++++++++++++++++
 4 files changed, 199 insertions(+)
 create mode 100644 automation/build/debian/13-ppc64le.dockerfile
 create mode 100644 automation/build/debian/13-riscv64.dockerfile
 create mode 100644 automation/build/debian/13-x86_32.dockerfile
 create mode 100644 automation/build/debian/13-x86_64.dockerfile

diff --git a/automation/build/debian/13-ppc64le.dockerfile b/automation/build/debian/13-ppc64le.dockerfile
new file mode 100644
index 000000000000..5b22a4545842
--- /dev/null
+++ b/automation/build/debian/13-ppc64le.dockerfile
@@ -0,0 +1,37 @@
+# syntax=docker/dockerfile:1
+FROM --platform=linux/amd64 debian:trixie-slim
+LABEL maintainer.name="The Xen Project"
+LABEL maintainer.email="xen-devel@lists.xenproject.org"
+
+ENV DEBIAN_FRONTEND=noninteractive
+ENV CROSS_COMPILE=powerpc64le-linux-gnu-
+ENV XEN_TARGET_ARCH=ppc64
+
+RUN <
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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Shawn Anastasio ,
	Oleksii Kurochko ,
	Doug Goldstein ,
	=?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Victor Lira ,
	Samuel Thibault ,
	Juergen Gross 
Subject: [PATCH for-4.21 0/5] CI: Add Debian Trixie
Date: Sat,  9 Aug 2025 23:12:01 +0100
Message-Id: <20250809221206.1260861-1-andrew.cooper3@citrix.com>
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I know it's past the last-post deadline, but Trixie was only released today.

In terms of backports, we should at least go back to the bugfix branches.

Andrew Cooper (5):
  CI: Trixie containers
  CI: Update ppc64 to use Debian Trixie
  CI: Update riscv64 to use Debian Trixie
  stubdom: Fix -Wimplicit-int in newlib
  CI: Update x86 to use Debian Trixie

 automation/build/debian/13-ppc64le.dockerfile | 37 ++++++++
 automation/build/debian/13-riscv64.dockerfile | 37 ++++++++
 automation/build/debian/13-x86_32.dockerfile  | 51 ++++++++++
 automation/build/debian/13-x86_64.dockerfile  | 74 +++++++++++++++
 automation/gitlab-ci/build.yaml               | 94 +++++++++++++++----
 automation/gitlab-ci/test.yaml                | 14 +--
 stubdom/Makefile                              |  1 +
 stubdom/newlib-fix-etext.patch                | 23 +++++
 8 files changed, 306 insertions(+), 25 deletions(-)
 create mode 100644 automation/build/debian/13-ppc64le.dockerfile
 create mode 100644 automation/build/debian/13-riscv64.dockerfile
 create mode 100644 automation/build/debian/13-x86_32.dockerfile
 create mode 100644 automation/build/debian/13-x86_64.dockerfile
 create mode 100644 stubdom/newlib-fix-etext.patch

-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Shawn Anastasio ,
	Oleksii Kurochko ,
	Doug Goldstein ,
	=?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Victor Lira 
Subject: [PATCH 3/5] CI: Update riscv64 to use Debian Trixie
Date: Sat,  9 Aug 2025 23:12:04 +0100
Message-Id: <20250809221206.1260861-4-andrew.cooper3@citrix.com>
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Everything works fine with Debian 13.  Provide two new build jobs, and update
both the randconfig the test jobs.

Signed-off-by: Andrew Cooper 
---
CC: Anthony PERARD 
CC: Michal Orzel 
CC: Jan Beulich 
CC: Julien Grall 
CC: Roger Pau Monné 
CC: Stefano Stabellini 
CC: Shawn Anastasio 
CC: Oleksii Kurochko 
CC: Doug Goldstein 
CC: Marek Marczykowski-Górecki 
CC: Victor Lira 

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1975929387
---
 automation/gitlab-ci/build.yaml | 22 ++++++++++++++++++----
 automation/gitlab-ci/test.yaml  |  2 +-
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 3fe539dc5683..f8e45f3467c8 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -329,10 +329,10 @@ debian-13-ppc64le-gcc-debug:
       CONFIG_UBSAN=y
       CONFIG_UBSAN_FATAL=y
 
-debian-12-riscv64-gcc-debug:
+debian-13-riscv64-gcc-debug:
   extends: .gcc-riscv64-cross-build-debug
   variables:
-    CONTAINER: debian:12-riscv64
+    CONTAINER: debian:13-riscv64
     KBUILD_DEFCONFIG: tiny64_defconfig
     HYPERVISOR_ONLY: y
     EXTRA_XEN_CONFIG: |
@@ -727,6 +727,20 @@ debian-12-riscv64-gcc:
     KBUILD_DEFCONFIG: tiny64_defconfig
     HYPERVISOR_ONLY: y
 
+debian-12-riscv64-gcc-debug:
+  extends: .gcc-riscv64-cross-build-debug
+  variables:
+    CONTAINER: debian:12-riscv64
+    KBUILD_DEFCONFIG: tiny64_defconfig
+    HYPERVISOR_ONLY: y
+
+debian-13-riscv64-gcc:
+  extends: .gcc-riscv64-cross-build
+  variables:
+    CONTAINER: debian:13-riscv64
+    KBUILD_DEFCONFIG: tiny64_defconfig
+    HYPERVISOR_ONLY: y
+
 .riscv-fixed-randconfig:
   variables: &riscv-fixed-randconfig
     EXTRA_FIXED_RANDCONFIG: |
@@ -739,10 +753,10 @@ debian-12-riscv64-gcc:
       CONFIG_VM_EVENT=n
       CONFIG_XSM=n
 
-debian-12-riscv64-gcc-randconfig:
+debian-13-riscv64-gcc-randconfig:
   extends: .gcc-riscv64-cross-build
   variables:
-    CONTAINER: debian:12-riscv64
+    CONTAINER: debian:13-riscv64
     KBUILD_DEFCONFIG: tiny64_defconfig
     RANDCONFIG: y
     <<: *riscv-fixed-randconfig
diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
index 2f6f3affa637..9acd984d294c 100644
--- a/automation/gitlab-ci/test.yaml
+++ b/automation/gitlab-ci/test.yaml
@@ -705,7 +705,7 @@ qemu-smoke-riscv64-gcc:
   script:
     - ./automation/scripts/qemu-smoke-riscv64.sh 2>&1 | tee ${LOGFILE}
   needs:
-    - debian-12-riscv64-gcc-debug
+    - debian-13-riscv64-gcc-debug
 
 qemu-smoke-ppc64le-powernv9-gcc:
   extends: .qemu-ppc64le
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Shawn Anastasio ,
	Oleksii Kurochko ,
	Doug Goldstein ,
	=?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Victor Lira 
Subject: [PATCH 5/5] CI: Update x86 to use Debian Trixie
Date: Sat,  9 Aug 2025 23:12:06 +0100
Message-Id: <20250809221206.1260861-6-andrew.cooper3@citrix.com>
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With the exception of the custom IBT job, copy all Debian 12 jobs making
Debian 13 versions, then trim the Debian 12 ranconfig jobs.  Update the test
jobs.

Signed-off-by: Andrew Cooper 
---
CC: Anthony PERARD 
CC: Michal Orzel 
CC: Jan Beulich 
CC: Julien Grall 
CC: Roger Pau Monné 
CC: Stefano Stabellini 
CC: Shawn Anastasio 
CC: Oleksii Kurochko 
CC: Doug Goldstein 
CC: Marek Marczykowski-Górecki 
CC: Victor Lira 

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1975958452

We may want to trim a few more jobs, but I'm not sure where the right balance is.
---
 automation/gitlab-ci/build.yaml | 54 +++++++++++++++++++++++++--------
 automation/gitlab-ci/test.yaml  | 10 +++---
 2 files changed, 47 insertions(+), 17 deletions(-)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index f8e45f3467c8..4cb52fe59715 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -309,15 +309,15 @@ alpine-3.18-gcc-debug:
       CONFIG_UCODE_SCAN_DEFAULT=y
       CONFIG_XHCI=y
 
-debian-12-x86_64-gcc-debug:
+debian-13-x86_64-gcc-debug:
   extends: .gcc-x86-64-build-debug
   variables:
-    CONTAINER: debian:12-x86_64
+    CONTAINER: debian:13-x86_64
 
-debian-12-x86_64-clang-debug:
+debian-13-x86_64-clang-debug:
   extends: .clang-x86-64-build-debug
   variables:
-    CONTAINER: debian:12-x86_64
+    CONTAINER: debian:13-x86_64
 
 debian-13-ppc64le-gcc-debug:
   extends: .gcc-ppc64le-cross-build-debug
@@ -545,24 +545,20 @@ debian-12-x86_64-clang:
   variables:
     CONTAINER: debian:12-x86_64
 
-debian-12-x86_64-clang-randconfig:
-  extends: .clang-x86-64-build
+debian-12-x86_64-clang-debug:
+  extends: .clang-x86-64-build-debug
   variables:
     CONTAINER: debian:12-x86_64
-    RANDCONFIG: y
-    EXTRA_FIXED_RANDCONFIG: |
-      CONFIG_COVERAGE=n # Disable coverage otherwise build times out.
 
 debian-12-x86_64-gcc:
   extends: .gcc-x86-64-build
   variables:
     CONTAINER: debian:12-x86_64
 
-debian-12-x86_64-gcc-randconfig:
-  extends: .gcc-x86-64-build
+debian-12-x86_64-gcc-debug:
+  extends: .gcc-x86-64-build-debug
   variables:
     CONTAINER: debian:12-x86_64
-    RANDCONFIG: y
 
 debian-12-x86_32-clang-debug:
   extends: .clang-x86-32-build-debug
@@ -574,6 +570,40 @@ debian-12-x86_32-gcc-debug:
   variables:
     CONTAINER: debian:12-x86_32
 
+debian-13-x86_64-clang:
+  extends: .clang-x86-64-build
+  variables:
+    CONTAINER: debian:13-x86_64
+
+debian-13-x86_64-clang-randconfig:
+  extends: .clang-x86-64-build
+  variables:
+    CONTAINER: debian:13-x86_64
+    RANDCONFIG: y
+    EXTRA_FIXED_RANDCONFIG: |
+      CONFIG_COVERAGE=n # Disable coverage otherwise build times out.
+
+debian-13-x86_64-gcc:
+  extends: .gcc-x86-64-build
+  variables:
+    CONTAINER: debian:13-x86_64
+
+debian-13-x86_64-gcc-randconfig:
+  extends: .gcc-x86-64-build
+  variables:
+    CONTAINER: debian:13-x86_64
+    RANDCONFIG: y
+
+debian-13-x86_32-clang-debug:
+  extends: .clang-x86-32-build-debug
+  variables:
+    CONTAINER: debian:13-x86_32
+
+debian-13-x86_32-gcc-debug:
+  extends: .gcc-x86-32-build-debug
+  variables:
+    CONTAINER: debian:13-x86_32
+
 fedora-41-x86_64-gcc:
   extends: .gcc-x86-64-build
   variables:
diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
index 9acd984d294c..96e952235737 100644
--- a/automation/gitlab-ci/test.yaml
+++ b/automation/gitlab-ci/test.yaml
@@ -661,35 +661,35 @@ qemu-smoke-x86-64-gcc:
   script:
     - ./automation/scripts/qemu-xtf.sh x86-64 pv64 example 2>&1 | tee ${LOGFILE}
   needs:
-    - debian-12-x86_64-gcc-debug
+    - debian-13-x86_64-gcc-debug
 
 qemu-smoke-x86-64-clang:
   extends: .qemu-smoke-x86-64
   script:
     - ./automation/scripts/qemu-xtf.sh x86-64 pv64 example 2>&1 | tee ${LOGFILE}
   needs:
-    - debian-12-x86_64-clang-debug
+    - debian-13-x86_64-clang-debug
 
 qemu-smoke-x86-64-gcc-pvh:
   extends: .qemu-smoke-x86-64
   script:
     - ./automation/scripts/qemu-xtf.sh x86-64 hvm64 example 2>&1 | tee ${LOGFILE}
   needs:
-    - debian-12-x86_64-gcc-debug
+    - debian-13-x86_64-gcc-debug
 
 qemu-smoke-x86-64-clang-pvh:
   extends: .qemu-smoke-x86-64
   script:
     - ./automation/scripts/qemu-xtf.sh x86-64 hvm64 example 2>&1 | tee ${LOGFILE}
   needs:
-    - debian-12-x86_64-clang-debug
+    - debian-13-x86_64-clang-debug
 
 qemu-smoke-x86-64-gcc-efi:
   extends: .qemu-smoke-x86-64
   script:
     - ./automation/scripts/qemu-xtf.sh x86-64-efi pv64 example 2>&1 | tee ${LOGFILE}
   needs:
-    - debian-12-x86_64-gcc-debug
+    - debian-13-x86_64-gcc-debug
 
 qemu-xtf-argo-x86_64-gcc-debug:
   extends: .qemu-smoke-x86-64
-- 
2.39.5



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 <20250803010449df1f5cfb@mail.local>
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From: Ard Biesheuvel 
Date: Sun, 10 Aug 2025 09:02:49 +1000
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Subject: Re: [RFC PATCH 1/3] efi-rtc: Remove wakeup functionality
To: Alexandre Belloni 
Cc: Ard Biesheuvel , linux-kernel@vger.kernel.org, 
	linux-arm-kernel@lists.infradead.org, 
	Heinrich Schuchardt , Feng Tang , 
	Juergen Gross , Stefano Stabellini , 
	Oleksandr Tyshchenko , Sunil V L , 
	Bibo Mao , linux-rtc@vger.kernel.org, linux-efi@vger.kernel.org, 
	xen-devel@lists.xenproject.org, x86@kernel.org, 
	linux-riscv@lists.infradead.org, loongarch@lists.linux.dev
Content-Type: text/plain; charset="UTF-8"

On Sun, 3 Aug 2025 at 11:05, Alexandre Belloni
 wrote:
>
> Hello,
>
> Apart from the topic that should be "rtc: efi:...", I'm ready to apply
> this patch.
>

Thanks, please go ahead.

> On 14/07/2025 08:08:45+0200, Ard Biesheuvel wrote:
> > From: Ard Biesheuvel 
> >
> > The EFI rtc driver is used by non-x86 architectures only, and exposes
> > the get/set wakeup time functionality provided by the underlying
> > platform. This is usually broken on most platforms, and not widely used
> > to begin with [if at all], so let's just remove it.
> >
> > Signed-off-by: Ard Biesheuvel 
> > ---
> >  drivers/rtc/rtc-efi.c | 76 +-------------------
> >  1 file changed, 2 insertions(+), 74 deletions(-)
> >
> > diff --git a/drivers/rtc/rtc-efi.c b/drivers/rtc/rtc-efi.c
> > index fa8bf82df948..b4f44999ef0f 100644
> > --- a/drivers/rtc/rtc-efi.c
> > +++ b/drivers/rtc/rtc-efi.c
> > @@ -112,48 +112,6 @@ convert_from_efi_time(efi_time_t *eft, struct rtc_time *wtime)
> >       return true;
> >  }
> >
> > -static int efi_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
> > -{
> > -     efi_time_t eft;
> > -     efi_status_t status;
> > -
> > -     /*
> > -      * As of EFI v1.10, this call always returns an unsupported status
> > -      */
> > -     status = efi.get_wakeup_time((efi_bool_t *)&wkalrm->enabled,
> > -                                  (efi_bool_t *)&wkalrm->pending, &eft);
> > -
> > -     if (status != EFI_SUCCESS)
> > -             return -EINVAL;
> > -
> > -     if (!convert_from_efi_time(&eft, &wkalrm->time))
> > -             return -EIO;
> > -
> > -     return rtc_valid_tm(&wkalrm->time);
> > -}
> > -
> > -static int efi_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
> > -{
> > -     efi_time_t eft;
> > -     efi_status_t status;
> > -
> > -     convert_to_efi_time(&wkalrm->time, &eft);
> > -
> > -     /*
> > -      * XXX Fixme:
> > -      * As of EFI 0.92 with the firmware I have on my
> > -      * machine this call does not seem to work quite
> > -      * right
> > -      *
> > -      * As of v1.10, this call always returns an unsupported status
> > -      */
> > -     status = efi.set_wakeup_time((efi_bool_t)wkalrm->enabled, &eft);
> > -
> > -     dev_warn(dev, "write status is %d\n", (int)status);
> > -
> > -     return status == EFI_SUCCESS ? 0 : -EINVAL;
> > -}
> > -
> >  static int efi_read_time(struct device *dev, struct rtc_time *tm)
> >  {
> >       efi_status_t status;
> > @@ -188,17 +146,13 @@ static int efi_set_time(struct device *dev, struct rtc_time *tm)
> >
> >  static int efi_procfs(struct device *dev, struct seq_file *seq)
> >  {
> > -     efi_time_t        eft, alm;
> > +     efi_time_t        eft;
> >       efi_time_cap_t    cap;
> > -     efi_bool_t        enabled, pending;
> > -     struct rtc_device *rtc = dev_get_drvdata(dev);
> >
> >       memset(&eft, 0, sizeof(eft));
> > -     memset(&alm, 0, sizeof(alm));
> >       memset(&cap, 0, sizeof(cap));
> >
> >       efi.get_time(&eft, &cap);
> > -     efi.get_wakeup_time(&enabled, &pending, &alm);
> >
> >       seq_printf(seq,
> >                  "Time\t\t: %u:%u:%u.%09u\n"
> > @@ -214,26 +168,6 @@ static int efi_procfs(struct device *dev, struct seq_file *seq)
> >               /* XXX fixme: convert to string? */
> >               seq_printf(seq, "Timezone\t: %u\n", eft.timezone);
> >
> > -     if (test_bit(RTC_FEATURE_ALARM, rtc->features)) {
> > -             seq_printf(seq,
> > -                        "Alarm Time\t: %u:%u:%u.%09u\n"
> > -                        "Alarm Date\t: %u-%u-%u\n"
> > -                        "Alarm Daylight\t: %u\n"
> > -                        "Enabled\t\t: %s\n"
> > -                        "Pending\t\t: %s\n",
> > -                        alm.hour, alm.minute, alm.second, alm.nanosecond,
> > -                        alm.year, alm.month, alm.day,
> > -                        alm.daylight,
> > -                        enabled == 1 ? "yes" : "no",
> > -                        pending == 1 ? "yes" : "no");
> > -
> > -             if (alm.timezone == EFI_UNSPECIFIED_TIMEZONE)
> > -                     seq_puts(seq, "Timezone\t: unspecified\n");
> > -             else
> > -                     /* XXX fixme: convert to string? */
> > -                     seq_printf(seq, "Timezone\t: %u\n", alm.timezone);
> > -     }
> > -
> >       /*
> >        * now prints the capabilities
> >        */
> > @@ -249,8 +183,6 @@ static int efi_procfs(struct device *dev, struct seq_file *seq)
> >  static const struct rtc_class_ops efi_rtc_ops = {
> >       .read_time      = efi_read_time,
> >       .set_time       = efi_set_time,
> > -     .read_alarm     = efi_read_alarm,
> > -     .set_alarm      = efi_set_alarm,
> >       .proc           = efi_procfs,
> >  };
> >
> > @@ -271,11 +203,7 @@ static int __init efi_rtc_probe(struct platform_device *dev)
> >       platform_set_drvdata(dev, rtc);
> >
> >       rtc->ops = &efi_rtc_ops;
> > -     clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->features);
> > -     if (efi_rt_services_supported(EFI_RT_SUPPORTED_WAKEUP_SERVICES))
> > -             set_bit(RTC_FEATURE_ALARM_WAKEUP_ONLY, rtc->features);
> > -     else
> > -             clear_bit(RTC_FEATURE_ALARM, rtc->features);
> > +     clear_bit(RTC_FEATURE_ALARM, rtc->features);
> >
> >       device_init_wakeup(&dev->dev, true);
> >
> > --
> > 2.50.0.727.gbf7dc18ff4-goog
> >
>
> --
> Alexandre Belloni, co-owner and COO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>


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 Xen-devel 
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Subject: Re: [PATCH 4/5] stubdom: Fix -Wimplicit-int in newlib
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From: nicola.vetrini@gmail.com
To: xen-devel@lists.xenproject.org
Cc: Nicola Vetrini ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Nicola Vetrini 
Subject: [XEN PATCH] xen: Drop logic for old clang versions.
Date: Sun, 10 Aug 2025 15:03:53 +0200
Message-ID: 
X-Mailer: git-send-email 2.43.0
MIME-Version: 1.0
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From: Nicola Vetrini 

The enforced toolchain baseline for clang is version 11,
therefore this logic is effectively dead code.

No functional change.

Signed-off-by: Nicola Vetrini 
---
Mentioned in https://gitlab.com/xen-project/xen/-/issues/201
---
 xen/common/coverage/llvm.c   | 4 ----
 xen/include/xen/self-tests.h | 9 +--------
 2 files changed, 1 insertion(+), 12 deletions(-)

diff --git a/xen/common/coverage/llvm.c b/xen/common/coverage/llvm.c
index 50d7a3c5d301..517b2aa8c202 100644
--- a/xen/common/coverage/llvm.c
+++ b/xen/common/coverage/llvm.c
@@ -44,12 +44,8 @@
     ((uint64_t)'f' << 16) | ((uint64_t)'R' << 8)  | ((uint64_t)129)
 #endif
 
-#if __clang_major__ >= 4 || (__clang_major__ == 3 && __clang_minor__ >= 9)
 #define LLVM_PROFILE_VERSION    4
 #define LLVM_PROFILE_NUM_KINDS  2
-#else
-#error "clang version not supported with coverage"
-#endif
 
 struct llvm_profile_data {
     uint64_t name_ref;
diff --git a/xen/include/xen/self-tests.h b/xen/include/xen/self-tests.h
index bd8a4867aa40..c57cceb3b962 100644
--- a/xen/include/xen/self-tests.h
+++ b/xen/include/xen/self-tests.h
@@ -10,16 +10,12 @@
 #include 
 
 /*
- * Check that fn(val) can be calcuated by the compiler, and that it gives the
+ * Check that fn(val) can be calculated by the compiler, and that it gives the
  * expected answer.
  *
- * Clang < 8 can't fold constants through static inlines, causing this to
- * fail.  Simply skip it for incredibly old compilers.
- *
  * N.B. fn is intentionally not bracketed to allow us to test function-like
  * macros too.
  */
-#if !defined(CONFIG_CC_IS_CLANG) || CONFIG_CLANG_VERSION >= 80000
 #define COMPILE_CHECK(fn, val, res)                                     \
     do {                                                                \
         typeof(fn(val)) real = fn(val);                                 \
@@ -29,9 +25,6 @@
         else if ( real != (res) )                                       \
             BUILD_ERROR("Compile time check '" STR(fn(val) == res) "' failed"); \
     } while ( 0 )
-#else
-#define COMPILE_CHECK(fn, val, res)
-#endif
 
 /*
  * Check that Xen's runtime logic for fn(val) gives the expected answer.  This
-- 
2.43.0



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Date: Sun, 10 Aug 2025 14:02:02 -0300
From: Jason Gunthorpe 
To: Demi Marie Obenour 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 00/16] dma-mapping: migrate to physical address-based
 API
Message-ID: <20250810170202.GQ184255@nvidia.com>
References: 
 
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On Sat, Aug 09, 2025 at 12:53:09PM -0400, Demi Marie Obenour wrote:
> > With a long term goal that struct page only exists for legacy code,
> > and is maybe entirely compiled out of modern server kernels.
> 
> Why just server kernels?  I suspect client systems actually run
> newer kernels than servers do.

I would guess this is because of the people who are interested in this
work. Frankly there isn't much benifit for small memory client
systems. Modern servers have > 1TB of memory and struct page really
hurts here.

The flip side of this is the work is enormous and I think there is a
general idea that the smaller set of server related drivers and
subsystems will get ready well before the wider universe of stuff a
client or android might use.

It is not that more can't happen it just ultimately depends on
interest and time.

Many modern servers use quite new kernels if you ignore the enterprise
distros :\

Jason


From xen-devel-bounces@lists.xenproject.org Mon Aug 11 04:05:30 2025
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Subject: Re: [PATCH v11 1/5] vpci: Use cleanup to free capability resource
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Date: Mon, 11 Aug 2025 04:04:57 +0000
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References: <20250808080337.28609-1-Jiqian.Chen@amd.com>
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 <31f9800f-5d2a-4614-9850-07d6bbe232d8@suse.com>
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Subject: Re: [PATCH 02/22] x86/msr: Rename wrmsr_ns() to wrmsrns(), and take
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In-Reply-To: <20250808202314.1045968-3-andrew.cooper3@citrix.com>
Content-Type: text/plain; charset=UTF-8
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On 08/08/2025 9:22 pm, Andrew Cooper wrote:
> In hindsight, having the wrapper name not be the instruction mnemonic was a
> poor choice.  Also, PKS turns out to be quite rare in wanting a split value.
>
> Switch to using a single 64bit value in preparation for new users.
>
> No functional change.
>
> Signed-off-by: Andrew Cooper 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
> ---
>  xen/arch/x86/include/asm/msr.h      | 4 ++--
>  xen/arch/x86/include/asm/prot-key.h | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
> index 4c4f18b3a54d..b6b85b04c3fd 100644
> --- a/xen/arch/x86/include/asm/msr.h
> +++ b/xen/arch/x86/include/asm/msr.h
> @@ -39,7 +39,7 @@ static inline void wrmsrl(unsigned int msr, uint64_t val)
>  }
>  
>  /* Non-serialising WRMSR, when available.  Falls back to a serialising WRMSR. */
> -static inline void wrmsr_ns(uint32_t msr, uint32_t lo, uint32_t hi)
> +static inline void wrmsrns(uint32_t msr, uint64_t val)
>  {
>      /*
>       * WRMSR is 2 bytes.  WRMSRNS is 3 bytes.  Pad WRMSR with a redundant CS
> @@ -47,7 +47,7 @@ static inline void wrmsr_ns(uint32_t msr, uint32_t lo, uint32_t hi)
>       */
>      alternative_input(".byte 0x2e; wrmsr",
>                        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
> -                      "c" (msr), "a" (lo), "d" (hi));
> +                      "c" (msr), "a" (val), "d" (val >> 32));
>  }

It turns out this is the case poor code generation for MSR_STAR.

I've adjusted it to:

@@ -39,8 +39,10 @@ static inline void wrmsrl(unsigned int msr, uint64_t val)
 }
 
 /* Non-serialising WRMSR, when available.  Falls back to a serialising WRMSR. */
-static inline void wrmsr_ns(uint32_t msr, uint32_t lo, uint32_t hi)
+static inline void wrmsrns(uint32_t msr, uint64_t val)
 {
+    uint32_t lo = val, hi = val >> 32;
+
     /*
      * WRMSR is 2 bytes.  WRMSRNS is 3 bytes.  Pad WRMSR with a redundant CS
      * prefix to avoid a trailing NOP.


which stops the compiler from loading the high half of %rax too.

~Andrew


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Subject: Re: [PATCH v11 1/5] vpci: Use cleanup to free capability resource
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To: "Chen, Jiqian" 
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On 11.08.2025 06:04, Chen, Jiqian wrote:
> On 2025/8/8 16:58, Jan Beulich wrote:
>> On 08.08.2025 10:03, Jiqian Chen wrote:
>>> @@ -321,6 +321,29 @@ void vpci_deassign_device(struct pci_dev *pdev)
>>>                      &pdev->domain->vpci_dev_assigned_map);
>>>  #endif
>>>  
>>> +    for ( i = 0; i < NUM_VPCI_INIT; i++ )
>>> +    {
>>> +        const vpci_capability_t *capability = &__start_vpci_array[i];
>>> +        const unsigned int cap = capability->id;
>>> +        unsigned int pos = 0;
>>> +
>>> +        if ( !capability->cleanup )
>>> +            continue;
>>> +
>>> +        if ( !capability->is_ext )
>>> +            pos = pci_find_cap_offset(pdev->sbdf, cap);
>>> +        else if ( is_hardware_domain(pdev->domain) )
>>> +            pos = pci_find_ext_capability(pdev->sbdf, cap);
>>> +        if ( pos )
>>> +        {
>>> +            int rc = capability->cleanup(pdev, false);
>>> +            if ( rc )
>>
>> Nit: Blank line between declaration(s) and statement(s) please. (Likely
>> easy enough to adjust while committing, if no other need for a v12
>> arises.)
> Thanks.
> BTW, do I need for-4.21 flag if I expect this series to be merged before 4.21 release?

I wouldn't say "need", but adding such a tag may now be advisable.

Jan


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Date: Mon, 11 Aug 2025 09:28:11 +0200
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Subject: Re: [PATCH v3 11/20] xen/riscv: implement function to map memory in
 guest p2m
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org,
 Andrew Cooper 
References: 
 
 
 <31c75a64-8b69-47ac-9e08-6010fa6cfb9c@gmail.com>
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From: Jan Beulich 
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On 08.08.2025 15:46, Oleksii Kurochko wrote:
> On 8/5/25 5:20 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> +/* Unlock the flush and do a P2M TLB flush if necessary */
>>> +void p2m_write_unlock(struct p2m_domain *p2m)
>>> +{
>>> +    /*
>>> +     * The final flush is done with the P2M write lock taken to avoid
>>> +     * someone else modifying the P2M wbefore the TLB invalidation has
>> Nit: Stray 'w'.
>>
>>> +     * completed.
>>> +     */
>>> +    p2m_tlb_flush_sync(p2m);
>> Wasn't the plan to have this be conditional?
> 
> Not really, probably, I misunderstood you before.
> 
> Previously, I only had|p2m_force_tlb_flush_sync()| here, instead of
> |p2m_tlb_flush_sync()|, and the latter includes a condition check on
> |p2m->need_flush|.

Just to re-iterate my point: Not every unlock will require a flush. Hence
why I expect the flush to be conditional upon there being an indication
that some change was done that requires flushing.

Jan


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From: Bertrand Marquis 
To: Julien Grall 
CC: "xen-devel@lists.xenproject.org" ,
	"jens.wiklander@linaro.org" , Volodymyr Babchuk
	, Stefano Stabellini ,
	Michal Orzel 
Subject: Re: [PATCH v7 3/6] xen/arm: ffa: Introduce VM to VM support
Thread-Topic: [PATCH v7 3/6] xen/arm: ffa: Introduce VM to VM support
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Date: Mon, 11 Aug 2025 07:34:06 +0000
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Hi Julien,

> On 8 Aug 2025, at 18:53, Julien Grall  wrote:
>=20
> Hi Bertrand,
>=20
> On 17/07/2025 13:11, Bertrand Marquis wrote:
>> Create a CONFIG_FFA_VM_TO_VM parameter to activate FFA communication
>> between VMs.
>> When activated list VMs in the system with FF-A support in part_info_get=
.
>> When VM to VM is activated, Xen will be tainted as Insecure and a
>> message is displayed to the user during the boot as there is no
>> filtering of VMs in FF-A so any VM can communicate or see any other VM
>> in the system.
>> WARNING: There is no filtering for now and all VMs are listed !!
>> This patch is reorganizing the ffa_ctx structure to make clear which
>> lock is protecting what parts.
>> This patch is introducing a chain list of the ffa_ctx with a FFA Version
>> negociated allowing to create the partinfo results for VMs in parallel
>> by using rwlock which only ensure addition/removal of entries are
>> protected.
>> Signed-off-by: Bertrand Marquis 
>=20
> With two remarks below:
>=20
> Acked-by: Julien Grall 
>=20
>> ---
>> Changes in v7:
>> - protect ffa_ctx list with a rw lock to allow several partinfo_get in
>>   parallel but protect adding/removing entries.
>> Changes in v6:
>> - remove ACCESS_ONCE for guest_vers access and take the context lock
>>   before modifying it
>> - move guest_vers in context declaration to fields protected by the
>>   context lock and add a comment to state that lock in only needed when
>>   modifying it
>> Changes in v5:
>> - remove invalid comment about 1.1 firmware support
>> - rename variables from d and dom to curr_d and dest_d (Julien)
>> - add a TODO in the code for potential holding for long of the CPU
>>   (Julien)
>> - use an atomic global variable to store the number of VMs instead of
>>   recomputing the value each time (Julien)
>> - add partinfo information in ffa_ctx (id, cpus and 64bit) and create a
>>   chain list of ctx. Use this chain list to create the partinfo result
>>   without holding a global lock to prevent concurrency issues.
>> - Move some changes in a preparation patch modifying partinfo for sps to
>>   reduce this patch size and make the review easier
>> Changes in v4:
>> - properly handle SPMC version 1.0 header size case in partinfo_get
>> - switch to local counting variables instead of *pointer +=3D 1 form
>> - coding style issue with missing spaces in if ()
>> Changes in v3:
>> - break partinfo_get in several sub functions to make the implementation
>>   easier to understand and lock handling easier
>> - rework implementation to check size along the way and prevent previous
>>   implementation limits which had to check that the number of VMs or SPs
>>   did not change
>> - taint Xen as INSECURE when VM to VM is enabled
>> Changes in v2:
>> - Switch ifdef to IS_ENABLED
>> - dom was not switched to d as requested by Jan because there is already
>>   a variable d pointing to the current domain and it must not be
>>   shadowed.
>> ---
>>  xen/arch/arm/tee/Kconfig        |  11 +++
>>  xen/arch/arm/tee/ffa.c          |  47 +++++++++++++
>>  xen/arch/arm/tee/ffa_partinfo.c | 100 ++++++++++++++++++++++++---
>>  xen/arch/arm/tee/ffa_private.h  | 117 ++++++++++++++++++++++++++------
>>  4 files changed, 245 insertions(+), 30 deletions(-)
>> diff --git a/xen/arch/arm/tee/Kconfig b/xen/arch/arm/tee/Kconfig
>> index c5b0f88d7522..88a4c4c99154 100644
>> --- a/xen/arch/arm/tee/Kconfig
>> +++ b/xen/arch/arm/tee/Kconfig
>> @@ -28,5 +28,16 @@ config FFA
>>       [1] https://developer.arm.com/documentation/den0077/latest
>>  +config FFA_VM_TO_VM
>> +    bool "Enable FF-A between VMs (UNSUPPORTED)" if UNSUPPORTED
>> +    default n
>> +    depends on FFA
>> +    help
>> +      This option enables to use FF-A between VMs.
>> +      This is experimental and there is no access control so any
>> +      guest can communicate with any other guest.
>> +
>> +      If unsure, say N.
>> +
>>  endmenu
>>  diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c
>> index 3bbdd7168a6b..be71eda4869f 100644
>> --- a/xen/arch/arm/tee/ffa.c
>> +++ b/xen/arch/arm/tee/ffa.c
>> @@ -118,6 +118,13 @@ void *ffa_tx __read_mostly;
>>  DEFINE_SPINLOCK(ffa_rx_buffer_lock);
>>  DEFINE_SPINLOCK(ffa_tx_buffer_lock);
>>  +struct list_head ffa_ctx_head;
>=20
> A more common pattern is to use LIST_HEAD(ffa_ctx_head) and ...
>=20
>> +/* RW Lock to protect addition/removal and reading in ffa_ctx_head */
>> +rwlock_t ffa_ctx_list_rwlock;
>=20
> ... DEFINE_RWLOCK(ffa_ctx_list_rwlock) which will also initialize list/rw=
lock for you. So no need for extra code further down and less risk if the v=
ariables are used before they are initialized.

I will modify those and push a v7 to the mailing list today.

Thanks again.

Bertrand

>=20
> Cheers,
>=20
> --=20
> Julien Grall




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Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators
To: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org,
 michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
 dmukhin@ford.com, xen-devel@lists.xenproject.org
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-3-dmukhin@ford.com>
  
Content-Language: en-US
From: Jan Beulich 
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On 09.08.2025 20:55, dmkhn@proton.me wrote:
> On Mon, Aug 04, 2025 at 12:11:03PM +0200, Jan Beulich wrote:
>> On 31.07.2025 21:21, dmkhn@proton.me wrote:
>>> --- a/xen/common/Kconfig
>>> +++ b/xen/common/Kconfig
>>> @@ -1,6 +1,8 @@
>>>
>>>  menu "Common Features"
>>>
>>> +source "common/emul/Kconfig"
>>> +
>>>  config COMPAT
>>
>> Why at the very top?
> 
> I did not find a better place, since the settings are not sorted and to me it
> makes sense to list emulation capabilities first...
> 
> Where would be the best location for that submenu?
> Close to another submenu `source "common/sched/Kconfig"`?

At least below there. Possibly yet further down.

>>> +int vuart_init(struct domain *d, struct vuart_params *params)
>>> +{
>>> +    const struct vuart_ops *vdev;
>>> +    int rc;
>>> +
>>> +    if ( !domain_has_vuart(d) )
>>> +        return 0;
>>> +
>>> +    for_each_vuart(vdev)
>>> +    {
>>> +        rc = vdev->init(d, params);
>>> +        if ( rc )
>>> +            return rc;
>>> +    }
>>> +
>>> +    d->console.input_allowed = true;
>>
>> Unconditionally?
> 
> Thanks.
> That should be a least under rc == 0.

You only ever make it there with rc == 0, though. (In fact that variable's
scope would better be just the loop body.)

>>> +/*
>>> + * Put character to the first suitable emulated UART's FIFO.
>>> + */
>>
>> What's "suitable"? Along the lines of the earlier remark, what if the domain
>> has vUART kind A configured, ...
> 
> "suitable" is meant to be the first emulator with put_rx != NULL.
> I will update that.

Except that, as iirc Roger also pointed out, "first emulator with put_rx != NULL"
is a questionable condition.

>>> --- a/xen/common/keyhandler.c
>>> +++ b/xen/common/keyhandler.c
>>> @@ -22,6 +22,7 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>  #include 
>>>
>>>  static unsigned char keypress_key;
>>> @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char key)
>>>                             v->periodic_period / 1000000);
>>>              }
>>>          }
>>> +
>>> +        vuart_dump_state(d);
>>
>> How verbose is this going to get?
> 
> Looks something like this:
> ```
> (XEN) [   88.334893] 'q' pressed -> dumping domain info (now = 88334828303)
> [..]
> (XEN) [   88.335673] Virtual ns16550 (COM2) I/O port 0x02f8 IRQ#3 owner d0
> (XEN) [   88.335681]   RX FIFO size 1024 in_prod 258 in_cons 258 used 0
> (XEN) [   88.335689]   TX FIFO size 2048 out_prod 15 out_cons 0 used 15
> (XEN) [   88.335696]   00 RBR 02 THR 6f DLL 01 DLM 00
> (XEN) [   88.335703]   01 IER 05
> (XEN) [   88.335709]   02 FCR 81 IIR c1
> (XEN) [   88.335715]   03 LCR 13
> (XEN) [   88.335720]   04 MCR 0b
> (XEN) [   88.335726]   05 LSR 60
> (XEN) [   88.335731]   06 MSR b0
> (XEN) [   88.335736]   07 SCR 00
> 
> ```

Definitely too much (for my taste) to put under 'q'.

Jan


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Date: Mon, 11 Aug 2025 09:39:42 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v4 5/8] emul/vuart-ns16550: introduce NS16550-compatible
 UART emulator (x86)
To: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org,
 michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
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On 09.08.2025 20:37, dmkhn@proton.me wrote:
> On Mon, Aug 04, 2025 at 12:53:36PM +0200, Jan Beulich wrote:
>> On 31.07.2025 21:22, dmkhn@proton.me wrote:
>>> --- a/xen/common/emul/vuart/Makefile
>>> +++ b/xen/common/emul/vuart/Makefile
>>> @@ -1 +1,2 @@
>>>  obj-$(CONFIG_HAS_VUART) += vuart.o
>>> +obj-$(CONFIG_VUART_NS16550) += vuart-ns16550.o
>>
>> I don't think files in this directory need a vuart- name prefix.
> 
> Ack.
> 
> Hmm, there's already ns16550.c which is UART driver, so it may be confusing to
> have two ns16550s (although in different directories).
> 
> I do not have a strong preference on the naming here.

We have several examples of files with the same name in distinct directories.
As an aside - is it really only 16550-s that you emulate? Otherwise the name
may want to be e.g. ns16x50.c or ns8250.c.

Jan


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Date: Mon, 11 Aug 2025 09:47:22 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: nicola.vetrini@gmail.com
Cc: xen-devel@lists.xenproject.org,
	Nicola Vetrini ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich , Julien Grall ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH] xen: Drop logic for old clang versions.
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On Sun, Aug 10, 2025 at 03:03:53PM +0200, nicola.vetrini@gmail.com wrote:
> From: Nicola Vetrini 
> 
> The enforced toolchain baseline for clang is version 11,
> therefore this logic is effectively dead code.
> 
> No functional change.
> 
> Signed-off-by: Nicola Vetrini 

Acked-by: Roger Pau Monné 

> ---
> Mentioned in https://gitlab.com/xen-project/xen/-/issues/201
> ---
>  xen/common/coverage/llvm.c   | 4 ----
>  xen/include/xen/self-tests.h | 9 +--------
>  2 files changed, 1 insertion(+), 12 deletions(-)
> 
> diff --git a/xen/common/coverage/llvm.c b/xen/common/coverage/llvm.c
> index 50d7a3c5d301..517b2aa8c202 100644
> --- a/xen/common/coverage/llvm.c
> +++ b/xen/common/coverage/llvm.c
> @@ -44,12 +44,8 @@
>      ((uint64_t)'f' << 16) | ((uint64_t)'R' << 8)  | ((uint64_t)129)
>  #endif
>  
> -#if __clang_major__ >= 4 || (__clang_major__ == 3 && __clang_minor__ >= 9)
>  #define LLVM_PROFILE_VERSION    4
>  #define LLVM_PROFILE_NUM_KINDS  2
> -#else
> -#error "clang version not supported with coverage"
> -#endif

Rant: most of the LLVM coverage stuff is already kind of dead code, as
the format of the data changes between versions and there's no way for
LLVM to generate the blob itself using a builtin function or
similar.  We haven't kept up with new formats, and now it's not
possible to parse the output coverage data when using newish LLVM
versions.

Linux converts it's LLVM coverage data to gcov format (which AFAIK is
way more stable), and exports it in gcov format.  We should consider
importing that from Linux.

Thanks, Roger.


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Subject: Re: [PATCH] xen/arm: irq: add missing spin_unlock() in
 init_local_irq_data() error path
To: Mykola Kvach 
Cc: Mykola Kvach ,
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On 09.08.2025 16:32, Mykola Kvach wrote:
> From: Mykola Kvach 
> 
> If init_one_irq_desc() fails, init_local_irq_data() returns without
> releasing local_irqs_type_lock, leading to a possible deadlock.
> 
> Release the lock before returning to ensure proper cleanup.
> 
> Signed-off-by: Mykola Kvach 

Pretty likely wants backporting, which would best be indicated by a suitable
Fixes: tag.

Jan

> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -94,7 +94,10 @@ static int init_local_irq_data(unsigned int cpu)
>          int rc = init_one_irq_desc(desc);
>  
>          if ( rc )
> +        {
> +            spin_unlock(&local_irqs_type_lock);
>              return rc;
> +        }
>  
>          desc->irq = irq;
>          desc->action  = NULL;



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On 09.08.2025 19:08, dmkhn@proton.me wrote:
> diff --git a/tools/tests/domid/include/xen/domain.h b/tools/tests/domid/include/xen/domain.h
> new file mode 120000
> index 000000000000..2eda9aed088e
> --- /dev/null
> +++ b/tools/tests/domid/include/xen/domain.h
> @@ -0,0 +1 @@
> +../../harness.h
> \ No newline at end of file

In the tests we generally generate symlinks as necessary, rather than having them be
present in git. Furthermore it's not quite clear why a file of this name is needed
in a test harness anyway. Elsewhere we adjust hypervisor sources to make respective
#include-s conditional.

Jan


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Subject: Re: [XEN PATCH] xen: Drop logic for old clang versions.
To: nicola.vetrini@gmail.com, xen-devel@lists.xenproject.org
Cc: Nicola Vetrini ,
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On 10/08/2025 2:03 pm, nicola.vetrini@gmail.com wrote:
> From: Nicola Vetrini 
>
> The enforced toolchain baseline for clang is version 11,
> therefore this logic is effectively dead code.
>
> No functional change.
>
> Signed-off-by: Nicola Vetrini 

Thanks for the patch, but your From and SoB lines don't match.  Which is
it supposed to be?

~Andrew


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Date: Mon, 11 Aug 2025 10:07:50 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Julien Grall 
Cc: xen-devel@lists.xenproject.org,
	Stefano Stabellini ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich 
Subject: Re: [PATCH v4 2/8] pdx: provide a unified set of unit functions
Message-ID: 
References: <20250805095257.74975-1-roger.pau@citrix.com>
 <20250805095257.74975-3-roger.pau@citrix.com>
 <5b940bdf-9bc0-49b2-af92-7251b2780c71@xen.org>
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On Fri, Aug 08, 2025 at 06:21:29PM +0100, Julien Grall wrote:
> Hi Roger,
> 
> On 05/08/2025 10:52, Roger Pau Monne wrote:
> > diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
> > index a77b31071ed8..ba35bf1fe3bb 100644
> > --- a/xen/arch/arm/setup.c
> > +++ b/xen/arch/arm/setup.c
> > @@ -256,9 +256,11 @@ void __init init_pdx(void)
> >   {
> >       const struct membanks *mem = bootinfo_get_mem();
> >       paddr_t bank_start, bank_size, bank_end, ram_end = 0;
> > -    int bank;
> > +    unsigned int bank;
> >   #ifndef CONFIG_PDX_NONE
> > +    for ( bank = 0 ; bank < mem->nr_banks; bank++ )
> > +        pfn_pdx_add_region(mem->bank[bank].start, mem->bank[bank].size);
> >       /*
> >        * Arm does not have any restrictions on the bits to compress. Pass 0 to
> >        * let the common code further restrict the mask.
> > @@ -266,26 +268,24 @@ void __init init_pdx(void)
> >        * If the logic changes in pfn_pdx_hole_setup we might have to
> >        * update this function too.
> >        */
> > -    uint64_t mask = pdx_init_mask(0x0);
> > -
> > -    for ( bank = 0 ; bank < mem->nr_banks; bank++ )
> > -    {
> > -        bank_start = mem->bank[bank].start;
> > -        bank_size = mem->bank[bank].size;
> > -
> > -        mask |= bank_start | pdx_region_mask(bank_start, bank_size);
> > -    }
> > +    pfn_pdx_compression_setup(0);
> >       for ( bank = 0 ; bank < mem->nr_banks; bank++ )
> >       {
> > -        bank_start = mem->bank[bank].start;
> > -        bank_size = mem->bank[bank].size;
> > -
> > -        if (~mask & pdx_region_mask(bank_start, bank_size))
> > -            mask = 0;
> > +        if ( !pdx_is_region_compressible(
> > +                  mem->bank[bank].start,
> > +                  PFN_UP(mem->bank[bank].start + mem->bank[bank].size) -
> > +                  PFN_DOWN(mem->bank[bank].start)) )
> 
> This code is a bit too verbose. Can we at least introduce "bank =
> &mem->bank[bank]" to reduce a bit the verbosity?

I cannot introduce a `bank` local variable as it's already used as the
index cursor for the loop.  Would you be fine with:

    for ( bank = 0 ; bank < mem->nr_banks; bank++ )
    {
        const struct membank *m = &mem->bank[bank];

        if ( !pdx_is_region_compressible(m->start,
                                         PFN_UP(m->start + m->size) -
                                         PFN_DOWN(m->start)) )
        {
            pfn_pdx_compression_reset();
            printk(XENLOG_WARNING
                   "PFN compression disabled, RAM region [%#" PRIpaddr ", %#"
                   PRIpaddr "] not covered\n",
                   m->start, m->start + m->size - 1);
            break;
        }
    }

> The rest of the logic looks fine. So:
> 
> Acked-by: Julien Grall  # ARM

Thanks, Roger.


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Subject: Re: [PATCH] RFC x86/msr: Use WRMSRNS $imm when available
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808222013.1071291-1-andrew.cooper3@citrix.com>
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On 09.08.2025 00:20, Andrew Cooper wrote:
> Signed-off-by: Andrew Cooper 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
> 
> This is on top of the FRED series for the wrmsrns() cleanup, but otherwise
> unrelated.
> 
> The code generation isn't entirely ideal
> 
>   Function                                     old     new   delta
>   init_fred                                    255     274     +19
>   vmx_set_reg                                  248     256      +8
>   enter_state_helper.cold                     1014    1018      +4
>   __start_xen                                 8893    8897      +4
> 
> but made worse by the the prior codegen for wrmsrns(MSR_STAR, ...) being mad:
> 
>   mov    $0xc0000081,%ecx
>   mov    $0xe023e008,%edx
>   movabs $0xe023e00800000000,%rax
>   cs wrmsr
> 
> The two sources of code expansion come from the compiler not being able to
> construct %eax and %edx separately, and not being able propagate constants.
> 
> Loading 0 is possibly common enough to warrant another specialisation where we
> can use "a" (0), "d" (0) and forgo the MOV+SHR.
> 
> I'm probably overthinking things.  The addition will be in the noise in
> practice, and Intel are sure the advantage of MSR_IMM will not be.

It's not entirely clear to me what the overall effects are now with your
02/22 reply on the FRED series. Nevertheless a nit or two here.

> --- a/xen/arch/x86/include/asm/msr.h
> +++ b/xen/arch/x86/include/asm/msr.h
> @@ -38,9 +38,46 @@ static inline void wrmsrl(unsigned int msr, uint64_t val)
>          wrmsr(msr, lo, hi);
>  }
>  
> +/*
> + * Non-serialising WRMSR with a compile-time constant index, when available.
> + * Falls back to plain WRMSRNS, or to a serialising WRMSR.
> + */
> +static always_inline void __wrmsrns_imm(uint32_t msr, uint64_t val)
> +{
> +    /*
> +     * For best performance, WRMSRNS %r64, $msr is recommended.  For
> +     * compatibility, we need to fall back to plain WRMSRNS, or to WRMSR.
> +     *
> +     * The combined ABI is awkward, because WRMSRNS $imm takes a single r64,
> +     * whereas WRMSR{,NS} takes a split edx:eax pair.
> +     *
> +     * Always use WRMSRNS %rax, $imm, because it has the most in common with
> +     * the legacy forms.  When MSR_IMM isn't available, emit setup logic for
> +     * %ecx and %edx too.
> +     */
> +    alternative_input_2(
> +        "mov $%c[msr], %%ecx\n\t"

Simply %[msr] here?

And then, might it make sense to pull out this and ...

> +        "mov %%rax, %%rdx\n\t"
> +        "shr $32, %%rdx\n\t"
> +        ".byte 0x2e; wrmsr",
> +
> +        /* WRMSRNS %rax, $msr */
> +        ".byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
> +
> +        "mov $%c[msr], %%ecx\n\t"

... this, to ...

> +        "mov %%rax, %%rdx\n\t"
> +        "shr $32, %%rdx\n\t"
> +        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
> +
> +        [msr] "i" (msr), "a" (val) : "rcx", "rdx");

        [msr] "i" (msr), "a" (val), "c" (msr) : "rdx");

allowing the compiler to actually know what's put in %ecx? That'll make
original and 2nd replacement code 10 bytes, better balancing with the 9
bytes of the 1st replacement. And I'd guess that the potentially dead
MOV to %ecx would be hidden in the noise as well.

Then, seeing your use of a CS: prefix on WRMSR, why not also add one to
the 1st replacement, thus not requiring any NOP padding?

Jan


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Date: Mon, 11 Aug 2025 09:17:49 +0100
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Subject: Re: [PATCH 10/22] x86/traps: Move subarch_percpu_traps_init() into
 traps-setup.c
To: Xen-devel 
Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-11-andrew.cooper3@citrix.com>
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In-Reply-To: <20250808202314.1045968-11-andrew.cooper3@citrix.com>
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On 08/08/2025 9:23 pm, Andrew Cooper wrote:
> ... along with the supporting functions.  Switch to Xen coding style, and make
> static as there are no external callers.
>
> Rename to legacy_syscall_init() as a more accurate name.
>
> No functional change.
>
> Signed-off-by: Andrew Cooper 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
> ---
>  xen/arch/x86/include/asm/system.h |  2 -
>  xen/arch/x86/traps-setup.c        | 97 ++++++++++++++++++++++++++++++-
>  xen/arch/x86/x86_64/traps.c       | 92 -----------------------------
>  3 files changed, 95 insertions(+), 96 deletions(-)
>
> diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
> index 3cdc56e4ba6d..6c2800d8158d 100644
> --- a/xen/arch/x86/include/asm/system.h
> +++ b/xen/arch/x86/include/asm/system.h
> @@ -256,6 +256,4 @@ static inline int local_irq_is_enabled(void)
>  #define BROKEN_ACPI_Sx          0x0001
>  #define BROKEN_INIT_AFTER_S1    0x0002
>  
> -void subarch_percpu_traps_init(void);
> -
>  #endif
> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
> index 13b8fcf0ba51..fbae7072c292 100644
> --- a/xen/arch/x86/traps-setup.c
> +++ b/xen/arch/x86/traps-setup.c
> @@ -2,13 +2,15 @@
>  /*
>   * Configuration of event handling for all CPUs.
>   */
> +#include 
>  #include 
>  #include 
>  
> +#include 
>  #include 
>  #include 
>  #include 
> -#include 
> +#include 
>  #include 
>  
>  DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt);
> @@ -19,6 +21,8 @@ static bool __initdata opt_ler;
>  boolean_param("ler", opt_ler);
>  
>  void nocall entry_PF(void);
> +void nocall lstar_enter(void);
> +void nocall cstar_enter(void);
>  
>  /*
>   * Sets up system tables and descriptors for IDT devliery.
> @@ -138,6 +142,95 @@ static void load_system_tables(void)
>      BUG_ON(stack_bottom & 15);
>  }
>  
> +static unsigned int write_stub_trampoline(
> +    unsigned char *stub, unsigned long stub_va,
> +    unsigned long stack_bottom, unsigned long target_va)
> +{
> +    unsigned char *p = stub;
> +
> +    if ( cpu_has_xen_ibt )
> +    {
> +        place_endbr64(p);
> +        p += 4;
> +    }
> +
> +    /* Store guest %rax into %ss slot */
> +    /* movabsq %rax, stack_bottom - 8 */
> +    *p++ = 0x48;
> +    *p++ = 0xa3;
> +    *(uint64_t *)p = stack_bottom - 8;
> +    p += 8;
> +
> +    /* Store guest %rsp in %rax */
> +    /* movq %rsp, %rax */
> +    *p++ = 0x48;
> +    *p++ = 0x89;
> +    *p++ = 0xe0;
> +
> +    /* Switch to Xen stack */
> +    /* movabsq $stack_bottom - 8, %rsp */
> +    *p++ = 0x48;
> +    *p++ = 0xbc;
> +    *(uint64_t *)p = stack_bottom - 8;
> +    p += 8;
> +
> +    /* jmp target_va */
> +    *p++ = 0xe9;
> +    *(int32_t *)p = target_va - (stub_va + (p - stub) + 4);
> +    p += 4;
> +
> +    /* Round up to a multiple of 16 bytes. */
> +    return ROUNDUP(p - stub, 16);
> +}
> +
> +static void legacy_syscall_init(void)
> +{
> +    unsigned long stack_bottom = get_stack_bottom();
> +    unsigned long stub_va = this_cpu(stubs.addr);
> +    unsigned char *stub_page;
> +    unsigned int offset;
> +
> +    /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
> +    if ( !IS_ENABLED(CONFIG_PV) )
> +        return;
> +
> +    stub_page = map_domain_page(_mfn(this_cpu(stubs.mfn)));
> +
> +    /*
> +     * Trampoline for SYSCALL entry from 64-bit mode.  The VT-x HVM vcpu
> +     * context switch logic relies on the SYSCALL trampoline being at the
> +     * start of the stubs.
> +     */
> +    wrmsrl(MSR_LSTAR, stub_va);
> +    offset = write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
> +                                   stub_va, stack_bottom,
> +                                   (unsigned long)lstar_enter);
> +    stub_va += offset;
> +
> +    if ( cpu_has_sep )
> +    {
> +        /* SYSENTER entry. */
> +        wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
> +        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
> +        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
> +    }
> +
> +    /* Trampoline for SYSCALL entry from compatibility mode. */
> +    wrmsrl(MSR_CSTAR, stub_va);
> +    offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
> +                                    stub_va, stack_bottom,
> +                                    (unsigned long)cstar_enter);
> +
> +    /* Don't consume more than half of the stub space here. */
> +    ASSERT(offset <= STUB_BUF_SIZE / 2);
> +
> +    unmap_domain_page(stub_page);
> +
> +    /* Common SYSCALL parameters. */
> +    wrmsrl(MSR_STAR, XEN_MSR_STAR);
> +    wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
> +}

These want adjusting to use wrmsrns(), similarly to the previous patch. 
Fixed locally.

~Andrew


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Andrew Cooper
	, =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Anthony PERARD , "Orzel,
 Michal" , Julien Grall , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v6 12/19] xen/cpufreq: implement amd-cppc driver for CPPC
 in passive mode
Thread-Topic: [PATCH v6 12/19] xen/cpufreq: implement amd-cppc driver for CPPC
 in passive mode
Thread-Index: AQHb8hcm/2j2N+pZoEenN2J+6s0qPrQ2T+AAgCb91HA=
Date: Mon, 11 Aug 2025 08:23:27 +0000
Message-ID:
 
References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
 <20250711035106.2540522-13-Penny.Zheng@amd.com>
 <1899ebd0-c64a-4bb8-bf3d-0bf90f2b6299@suse.com>
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Subject: Re: [XEN PATCH 11/11] Update CHANGELOG and README with dependency on
 json-c
To: Anthony PERARD , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Community Manager ,
 Andrew Cooper ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini 
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-12-anthony@xenproject.org>
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On 8/8/25 4:56 PM, Anthony PERARD wrote:
> From: Anthony PERARD
>
> Signed-off-by: Anthony PERARD

LGTM: Acked-by: Oleksii Kurochko 
With one question ...


> ---
>   CHANGELOG.md | 2 ++
>   README       | 2 +-
>   2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/CHANGELOG.md b/CHANGELOG.md
> index 5f31ca08fe..83195e2dae 100644
> --- a/CHANGELOG.md
> +++ b/CHANGELOG.md
> @@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
>      - For x86, GCC 5.1 and Binutils 2.25, or Clang/LLVM 11
>      - For ARM32 and ARM64, GCC 5.1 and Binutils 2.25
>    - Linux based device model stubdomains are now fully supported.
> + - New dependency on library json-c, the toolstack will prefer it to `YAJL`
> +   when available.
>   
>    - On x86:
>      - Restrict the cache flushing done as a result of guest physical memory map
> diff --git a/README b/README
> index 6ee58f7b35..9329f30e13 100644
> --- a/README
> +++ b/README
> @@ -53,7 +53,7 @@ provided by your OS distributor:
>       * Development install of Python 2.7 or later (e.g., python-dev)
>       * Development install of curses (e.g., libncurses-dev)
>       * Development install of uuid (e.g. uuid-dev)
> -    * Development install of yajl (e.g. libyajl-dev)
> +    * Development install of json-c (e.g. libjson-c-dev) or yajl (e.g. libyajl-dev)

... as you mentioned in the cover letter libyajl-dev is unmaintained for several years. Do any plans
exist to drop libyajl-dev at all? Can't it be dropped now?

~ Oleksii

>       * Development install of libaio (e.g. libaio-dev) version 0.3.107 or
>         greater.
>       * Development install of GLib v2.0 (e.g. libglib2.0-dev)
--------------HWaOhxSqo62uZovjrqlsQOyW
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    On 8/8/25 4:56 PM, Anthony PERARD
      wrote:
    
    
    
    
    
      
    From: Anthony PERARD <anthony.perard@vates.tech>

Signed-off-by: Anthony PERARD <anthony.perard@vates.tech>
    
    
    
    
    LGTM: Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail>
With one question ...

    
    

    
    
    
    
    
      
    ---
 CHANGELOG.md | 2 ++
 README       | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe..83195e2dae 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - For x86, GCC 5.1 and Binutils 2.25, or Clang/LLVM 11
    - For ARM32 and ARM64, GCC 5.1 and Binutils 2.25
  - Linux based device model stubdomains are now fully supported.
+ - New dependency on library json-c, the toolstack will prefer it to `YAJL`
+   when available.
 
  - On x86:
    - Restrict the cache flushing done as a result of guest physical memory map
diff --git a/README b/README
index 6ee58f7b35..9329f30e13 100644
--- a/README
+++ b/README
@@ -53,7 +53,7 @@ provided by your OS distributor:
     * Development install of Python 2.7 or later (e.g., python-dev)
     * Development install of curses (e.g., libncurses-dev)
     * Development install of uuid (e.g. uuid-dev)
-    * Development install of yajl (e.g. libyajl-dev)
+    * Development install of json-c (e.g. libjson-c-dev) or yajl (e.g. libyajl-dev)
    
    
    
    
    ... as you mentioned in the cover letter libyajl-dev is unmaintained for several years. Do any plans
exist to drop libyajl-dev at all? Can't it be dropped now?

~ Oleksii

    
    
    
      
         * Development install of libaio (e.g. libaio-dev) version 0.3.107 or
       greater.
     * Development install of GLib v2.0 (e.g. libglib2.0-dev)

    
    
    
  


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Subject: Re: [PATCH for-4.21 0/5] CI: Add Debian Trixie
To: Andrew Cooper ,
 Xen-devel 
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 Shawn Anastasio ,
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 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
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On 8/10/25 12:12 AM, Andrew Cooper wrote:
> I know it's past the last-post deadline, but Trixie was only released today.

Lets consider it for 4.21:
  Release-Acked-by: Oleksii Kurochko

Thanks.

~ Oleksii

>
> In terms of backports, we should at least go back to the bugfix branches.
>
> Andrew Cooper (5):
>    CI: Trixie containers
>    CI: Update ppc64 to use Debian Trixie
>    CI: Update riscv64 to use Debian Trixie
>    stubdom: Fix -Wimplicit-int in newlib
>    CI: Update x86 to use Debian Trixie
>
>   automation/build/debian/13-ppc64le.dockerfile | 37 ++++++++
>   automation/build/debian/13-riscv64.dockerfile | 37 ++++++++
>   automation/build/debian/13-x86_32.dockerfile  | 51 ++++++++++
>   automation/build/debian/13-x86_64.dockerfile  | 74 +++++++++++++++
>   automation/gitlab-ci/build.yaml               | 94 +++++++++++++++----
>   automation/gitlab-ci/test.yaml                | 14 +--
>   stubdom/Makefile                              |  1 +
>   stubdom/newlib-fix-etext.patch                | 23 +++++
>   8 files changed, 306 insertions(+), 25 deletions(-)
>   create mode 100644 automation/build/debian/13-ppc64le.dockerfile
>   create mode 100644 automation/build/debian/13-riscv64.dockerfile
>   create mode 100644 automation/build/debian/13-x86_32.dockerfile
>   create mode 100644 automation/build/debian/13-x86_64.dockerfile
>   create mode 100644 stubdom/newlib-fix-etext.patch
>
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    On 8/10/25 12:12 AM, Andrew Cooper
      wrote:
    
    
    
    
    
      
    I know it's past the last-post deadline, but Trixie was only released today.
    
    
    
    
    Lets consider it for 4.21:
 Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Thanks.

~ Oleksii

    
    
    
      
    
In terms of backports, we should at least go back to the bugfix branches.

Andrew Cooper (5):
  CI: Trixie containers
  CI: Update ppc64 to use Debian Trixie
  CI: Update riscv64 to use Debian Trixie
  stubdom: Fix -Wimplicit-int in newlib
  CI: Update x86 to use Debian Trixie

 automation/build/debian/13-ppc64le.dockerfile | 37 ++++++++
 automation/build/debian/13-riscv64.dockerfile | 37 ++++++++
 automation/build/debian/13-x86_32.dockerfile  | 51 ++++++++++
 automation/build/debian/13-x86_64.dockerfile  | 74 +++++++++++++++
 automation/gitlab-ci/build.yaml               | 94 +++++++++++++++----
 automation/gitlab-ci/test.yaml                | 14 +--
 stubdom/Makefile                              |  1 +
 stubdom/newlib-fix-etext.patch                | 23 +++++
 8 files changed, 306 insertions(+), 25 deletions(-)
 create mode 100644 automation/build/debian/13-ppc64le.dockerfile
 create mode 100644 automation/build/debian/13-riscv64.dockerfile
 create mode 100644 automation/build/debian/13-x86_32.dockerfile
 create mode 100644 automation/build/debian/13-x86_64.dockerfile
 create mode 100644 stubdom/newlib-fix-etext.patch


    
    
    
  


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Message-ID: <2919f22b-0b0c-488e-b0c6-96b9538e63d9@gmail.com>
Date: Mon, 11 Aug 2025 10:43:10 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH 3/5] CI: Update riscv64 to use Debian Trixie
To: Andrew Cooper ,
 Xen-devel 
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 Shawn Anastasio ,
 Doug Goldstein ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , Victor Lira 
References: <20250809221206.1260861-1-andrew.cooper3@citrix.com>
 <20250809221206.1260861-4-andrew.cooper3@citrix.com>
Content-Language: en-US
From: Oleksii Kurochko 
In-Reply-To: <20250809221206.1260861-4-andrew.cooper3@citrix.com>

This is a multi-part message in MIME format.
--------------jBo8MouCJ84UWa0950Sndq1f
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On 8/10/25 12:12 AM, Andrew Cooper wrote:
> Everything works fine with Debian 13.  Provide two new build jobs, and update
> both the randconfig the test jobs.
>
> Signed-off-by: Andrew Cooper
> ---
> CC: Anthony PERARD
> CC: Michal Orzel
> CC: Jan Beulich
> CC: Julien Grall
> CC: Roger Pau Monné
> CC: Stefano Stabellini
> CC: Shawn Anastasio
> CC: Oleksii Kurochko
> CC: Doug Goldstein
> CC: Marek Marczykowski-Górecki
> CC: Victor Lira
>
> https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1975929387
> ---
>   automation/gitlab-ci/build.yaml | 22 ++++++++++++++++++----
>   automation/gitlab-ci/test.yaml  |  2 +-
>   2 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
> index 3fe539dc5683..f8e45f3467c8 100644
> --- a/automation/gitlab-ci/build.yaml
> +++ b/automation/gitlab-ci/build.yaml
> @@ -329,10 +329,10 @@ debian-13-ppc64le-gcc-debug:
>         CONFIG_UBSAN=y
>         CONFIG_UBSAN_FATAL=y
>   
> -debian-12-riscv64-gcc-debug:
> +debian-13-riscv64-gcc-debug:
>     extends: .gcc-riscv64-cross-build-debug
>     variables:
> -    CONTAINER: debian:12-riscv64
> +    CONTAINER: debian:13-riscv64
>       KBUILD_DEFCONFIG: tiny64_defconfig
>       HYPERVISOR_ONLY: y
>       EXTRA_XEN_CONFIG: |
> @@ -727,6 +727,20 @@ debian-12-riscv64-gcc:
>       KBUILD_DEFCONFIG: tiny64_defconfig
>       HYPERVISOR_ONLY: y
>   
> +debian-12-riscv64-gcc-debug:
> +  extends: .gcc-riscv64-cross-build-debug
> +  variables:
> +    CONTAINER: debian:12-riscv64
> +    KBUILD_DEFCONFIG: tiny64_defconfig
> +    HYPERVISOR_ONLY: y

Don't you mind to keep an order? So:
   debian-12-riscv64-gcc-debug:
   ...
   debian-13-riscv64-gcc-debug:
   ...

Also, it will make a diff a little bit better.

> +
> +debian-13-riscv64-gcc:
> +  extends: .gcc-riscv64-cross-build
> +  variables:
> +    CONTAINER: debian:13-riscv64
> +    KBUILD_DEFCONFIG: tiny64_defconfig
> +    HYPERVISOR_ONLY: y
> +
>   .riscv-fixed-randconfig:
>     variables: &riscv-fixed-randconfig
>       EXTRA_FIXED_RANDCONFIG: |
> @@ -739,10 +753,10 @@ debian-12-riscv64-gcc:
>         CONFIG_VM_EVENT=n
>         CONFIG_XSM=n
>   
> -debian-12-riscv64-gcc-randconfig:
> +debian-13-riscv64-gcc-randconfig:

Are we going to have randconfig build test only for Debian-13?

>     extends: .gcc-riscv64-cross-build
>     variables:
> -    CONTAINER: debian:12-riscv64
> +    CONTAINER: debian:13-riscv64
>       KBUILD_DEFCONFIG: tiny64_defconfig
>       RANDCONFIG: y
>       <<: *riscv-fixed-randconfig
> diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
> index 2f6f3affa637..9acd984d294c 100644
> --- a/automation/gitlab-ci/test.yaml
> +++ b/automation/gitlab-ci/test.yaml
> @@ -705,7 +705,7 @@ qemu-smoke-riscv64-gcc:
>     script:
>       - ./automation/scripts/qemu-smoke-riscv64.sh 2>&1 | tee ${LOGFILE}
>     needs:
> -    - debian-12-riscv64-gcc-debug
> +    - debian-13-riscv64-gcc-debug

The same as above, are we going to run smoke tests only for Debian-13?

If the answer to this and the question above is “yes,†then (probably
keeping the order — first debian-12, then debian-13 — for the jobs):
  Reviewed-by: Oleksii Kurochko

Thanks.

~ Oleksii

>   
>   qemu-smoke-ppc64le-powernv9-gcc:
>     extends: .qemu-ppc64le
--------------jBo8MouCJ84UWa0950Sndq1f
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    On 8/10/25 12:12 AM, Andrew Cooper
      wrote:
    
    
    
    
    
      
    Everything works fine with Debian 13.  Provide two new build jobs, and update
both the randconfig the test jobs.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Anthony PERARD <anthony.perard@vates.tech>
CC: Michal Orzel <michal.orzel@amd.com>
CC: Jan Beulich <jbeulich@suse.com>
CC: Julien Grall <julien@xen.org>
CC: Roger Pau Monné <roger.pau@citrix.com>
CC: Stefano Stabellini <sstabellini@kernel.org>
CC: Shawn Anastasio <sanastasio@raptorengineering.com>
CC: Oleksii Kurochko <oleksii.kurochko@gmail.com>
CC: Doug Goldstein <cardoe@cardoe.com>
CC: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
CC: Victor Lira <victorm.lira@amd.com>

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1975929387
---
 automation/gitlab-ci/build.yaml | 22 ++++++++++++++++++----
 automation/gitlab-ci/test.yaml  |  2 +-
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 3fe539dc5683..f8e45f3467c8 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -329,10 +329,10 @@ debian-13-ppc64le-gcc-debug:
       CONFIG_UBSAN=y
       CONFIG_UBSAN_FATAL=y
 
-debian-12-riscv64-gcc-debug:
+debian-13-riscv64-gcc-debug:
   extends: .gcc-riscv64-cross-build-debug
   variables:
-    CONTAINER: debian:12-riscv64
+    CONTAINER: debian:13-riscv64
     KBUILD_DEFCONFIG: tiny64_defconfig
     HYPERVISOR_ONLY: y
     EXTRA_XEN_CONFIG: |
@@ -727,6 +727,20 @@ debian-12-riscv64-gcc:
     KBUILD_DEFCONFIG: tiny64_defconfig
     HYPERVISOR_ONLY: y
 
+debian-12-riscv64-gcc-debug:
+  extends: .gcc-riscv64-cross-build-debug
+  variables:
+    CONTAINER: debian:12-riscv64
+    KBUILD_DEFCONFIG: tiny64_defconfig
+    HYPERVISOR_ONLY: y
    
    
    
    
    Don't you mind to keep an order? So:
  debian-12-riscv64-gcc-debug:
  ...
  debian-13-riscv64-gcc-debug:
  ...

Also, it will make a diff a little bit better.


    
    
    
      
    +
+debian-13-riscv64-gcc:
+  extends: .gcc-riscv64-cross-build
+  variables:
+    CONTAINER: debian:13-riscv64
+    KBUILD_DEFCONFIG: tiny64_defconfig
+    HYPERVISOR_ONLY: y
+
 .riscv-fixed-randconfig:
   variables: &riscv-fixed-randconfig
     EXTRA_FIXED_RANDCONFIG: |
@@ -739,10 +753,10 @@ debian-12-riscv64-gcc:
       CONFIG_VM_EVENT=n
       CONFIG_XSM=n
 
-debian-12-riscv64-gcc-randconfig:
+debian-13-riscv64-gcc-randconfig:
    
    
    
    
    Are we going to have randconfig build test only for Debian-13?


    
    
    
      
       extends: .gcc-riscv64-cross-build
   variables:
-    CONTAINER: debian:12-riscv64
+    CONTAINER: debian:13-riscv64
     KBUILD_DEFCONFIG: tiny64_defconfig
     RANDCONFIG: y
     <<: *riscv-fixed-randconfig
diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
index 2f6f3affa637..9acd984d294c 100644
--- a/automation/gitlab-ci/test.yaml
+++ b/automation/gitlab-ci/test.yaml
@@ -705,7 +705,7 @@ qemu-smoke-riscv64-gcc:
   script:
     - ./automation/scripts/qemu-smoke-riscv64.sh 2>&1 | tee ${LOGFILE}
   needs:
-    - debian-12-riscv64-gcc-debug
+    - debian-13-riscv64-gcc-debug
    
    
    
    
    The same as above, are we going to run smoke tests only for Debian-13?

If the answer to this and the question above is “yes,†then (probably
keeping the order — first debian-12, then debian-13 — for the jobs):
 Reviewed-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Thanks.

~ Oleksii

    
    
    
      
     
 qemu-smoke-ppc64le-powernv9-gcc:
   extends: .qemu-ppc64le

    
    
    
  


--------------jBo8MouCJ84UWa0950Sndq1f--


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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Denis Mukhin 
Subject: [PATCH v2] xen/arm: irq: add missing spin_unlock() in init_local_irq_data() error path
Date: Mon, 11 Aug 2025 11:45:20 +0300
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From: Mykola Kvach 

If init_one_irq_desc() fails, init_local_irq_data() returns without
releasing local_irqs_type_lock, leading to a possible deadlock.

Release the lock before returning to ensure proper cleanup.

Fixes: 2bb32b809250 ("xen/irq: Propagate the error from init_one_desc_irq() in init_*_irq_data()")
Signed-off-by: Mykola Kvach 
Reviewed-by: Denis Mukhin 
---
 xen/arch/arm/irq.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 4bbf0b0664..02ca82c089 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -94,7 +94,10 @@ static int init_local_irq_data(unsigned int cpu)
         int rc = init_one_irq_desc(desc);
 
         if ( rc )
+        {
+            spin_unlock(&local_irqs_type_lock);
             return rc;
+        }
 
         desc->irq = irq;
         desc->action  = NULL;
-- 
2.48.1



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From: Mykola Kvach 
Date: Mon, 11 Aug 2025 11:48:01 +0300
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Message-ID: 
Subject: Re: [PATCH] xen/arm: irq: add missing spin_unlock() in
 init_local_irq_data() error path
To: Jan Beulich 
Cc: Mykola Kvach , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	xen-devel@lists.xenproject.org
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On Mon, Aug 11, 2025 at 10:53=E2=80=AFAM Jan Beulich  wr=
ote:
>
> On 09.08.2025 16:32, Mykola Kvach wrote:
> > From: Mykola Kvach 
> >
> > If init_one_irq_desc() fails, init_local_irq_data() returns without
> > releasing local_irqs_type_lock, leading to a possible deadlock.
> >
> > Release the lock before returning to ensure proper cleanup.
> >
> > Signed-off-by: Mykola Kvach 
>
> Pretty likely wants backporting, which would best be indicated by a suita=
ble
> Fixes: tag.

I have added the Fixes: tag as suggested and resent the patch.
Thank you for pointing this out.

>
> Jan
>
> > --- a/xen/arch/arm/irq.c
> > +++ b/xen/arch/arm/irq.c
> > @@ -94,7 +94,10 @@ static int init_local_irq_data(unsigned int cpu)
> >          int rc =3D init_one_irq_desc(desc);
> >
> >          if ( rc )
> > +        {
> > +            spin_unlock(&local_irqs_type_lock);
> >              return rc;
> > +        }
> >
> >          desc->irq =3D irq;
> >          desc->action  =3D NULL;
>

Best regards,
Mykola


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Date: Mon, 11 Aug 2025 11:13:22 +0200
From: Nicola Vetrini 
To: Andrew Cooper 
Cc: nicola.vetrini@gmail.com, xen-devel@lists.xenproject.org, Anthony PERARD
 , Michal Orzel , Jan
 Beulich , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini
 
Subject: Re: [XEN PATCH] xen: Drop logic for old clang versions.
In-Reply-To: <96b878a1-2a4e-4df3-900c-a2b2142f0638@citrix.com>
References: 
 <96b878a1-2a4e-4df3-900c-a2b2142f0638@citrix.com>
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On 2025-08-11 10:07, Andrew Cooper wrote:
> On 10/08/2025 2:03 pm, nicola.vetrini@gmail.com wrote:
>> From: Nicola Vetrini 
>> 
>> The enforced toolchain baseline for clang is version 11,
>> therefore this logic is effectively dead code.
>> 
>> No functional change.
>> 
>> Signed-off-by: Nicola Vetrini 
> 
> Thanks for the patch, but your From and SoB lines don't match.  Which 
> is
> it supposed to be?
> 
> ~Andrew

The gmail one, git misconfiguration, sorry. Should I resend?

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Mon, 11 Aug 2025 11:29:49 +0200
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Subject: Re: [PATCH v3 11/20] xen/riscv: implement function to map memory in
 guest p2m
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org,
 Andrew Cooper 
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 <31c75a64-8b69-47ac-9e08-6010fa6cfb9c@gmail.com>
 
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From: Oleksii Kurochko 
In-Reply-To: 

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--------------ZP86uGEkdA3IPxgR203hpA6P
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On 8/11/25 9:28 AM, Jan Beulich wrote:
> On 08.08.2025 15:46, Oleksii Kurochko wrote:
>> On 8/5/25 5:20 PM, Jan Beulich wrote:
>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>> +/* Unlock the flush and do a P2M TLB flush if necessary */
>>>> +void p2m_write_unlock(struct p2m_domain *p2m)
>>>> +{
>>>> +    /*
>>>> +     * The final flush is done with the P2M write lock taken to avoid
>>>> +     * someone else modifying the P2M wbefore the TLB invalidation has
>>> Nit: Stray 'w'.
>>>
>>>> +     * completed.
>>>> +     */
>>>> +    p2m_tlb_flush_sync(p2m);
>>> Wasn't the plan to have this be conditional?
>> Not really, probably, I misunderstood you before.
>>
>> Previously, I only had|p2m_force_tlb_flush_sync()| here, instead of
>> |p2m_tlb_flush_sync()|, and the latter includes a condition check on
>> |p2m->need_flush|.
> Just to re-iterate my point: Not every unlock will require a flush. Hence
> why I expect the flush to be conditional upon there being an indication
> that some change was done that requires flushing.
>
The flush is actually conditional; the condition is inside
|p2m_tlb_flush_sync()|:
   void p2m_tlb_flush_sync(struct p2m_domain *p2m)
   {
     if ( p2m->need_flush )
       p2m_force_tlb_flush_sync(p2m);
   }

~ Oleksii

--------------ZP86uGEkdA3IPxgR203hpA6P
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 7bit



  
    
  
  
    

    
    
    
    
    On 8/11/25 9:28 AM, Jan Beulich wrote:
    
    
    
    
    
      
    On 08.08.2025 15:46, Oleksii Kurochko wrote:

    
      
    
        
    On 8/5/25 5:20 PM, Jan Beulich wrote:

    
        
    
          
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
          
    
            
    +/* Unlock the flush and do a P2M TLB flush if necessary */
+void p2m_write_unlock(struct p2m_domain *p2m)
+{
+    /*
+     * The final flush is done with the P2M write lock taken to avoid
+     * someone else modifying the P2M wbefore the TLB invalidation has

    
          
    
          
    Nit: Stray 'w'.


    
          
    
            
    +     * completed.
+     */
+    p2m_tlb_flush_sync(p2m);

    
          
    
          
    Wasn't the plan to have this be conditional?

    
        
    
        
    Not really, probably, I misunderstood you before.

Previously, I only had|p2m_force_tlb_flush_sync()| here, instead of
|p2m_tlb_flush_sync()|, and the latter includes a condition check on
|p2m->need_flush|.

    
      
    
      
    Just to re-iterate my point: Not every unlock will require a flush. Hence
why I expect the flush to be conditional upon there being an indication
that some change was done that requires flushing.


    
    
    
    
    The flush is actually conditional; the condition is inside
p2m_tlb_flush_sync():
  void p2m_tlb_flush_sync(struct p2m_domain *p2m)
  {
    if ( p2m->need_flush )
      p2m_force_tlb_flush_sync(p2m);
  }

~ Oleksii
    
  


--------------ZP86uGEkdA3IPxgR203hpA6P--


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 Anthony PERARD ,
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On 11/08/2025 10:13 am, Nicola Vetrini wrote:
> On 2025-08-11 10:07, Andrew Cooper wrote:
>> On 10/08/2025 2:03 pm, nicola.vetrini@gmail.com wrote:
>>> From: Nicola Vetrini 
>>>
>>> The enforced toolchain baseline for clang is version 11,
>>> therefore this logic is effectively dead code.
>>>
>>> No functional change.
>>>
>>> Signed-off-by: Nicola Vetrini 
>>
>> Thanks for the patch, but your From and SoB lines don't match.  Which is
>> it supposed to be?
>>
>> ~Andrew
>
> The gmail one, git misconfiguration, sorry. Should I resend?
>

No need.  I can fix up on commit.  Thanks.

~Andrew


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Date: Mon, 11 Aug 2025 11:35:21 +0200
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Subject: Re: [PATCH v3 11/20] xen/riscv: implement function to map memory in
 guest p2m
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org,
 Andrew Cooper 
References: 
 
 
 <31c75a64-8b69-47ac-9e08-6010fa6cfb9c@gmail.com>
 
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On 11.08.2025 11:29, Oleksii Kurochko wrote:
> 
> On 8/11/25 9:28 AM, Jan Beulich wrote:
>> On 08.08.2025 15:46, Oleksii Kurochko wrote:
>>> On 8/5/25 5:20 PM, Jan Beulich wrote:
>>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>>> +/* Unlock the flush and do a P2M TLB flush if necessary */
>>>>> +void p2m_write_unlock(struct p2m_domain *p2m)
>>>>> +{
>>>>> +    /*
>>>>> +     * The final flush is done with the P2M write lock taken to avoid
>>>>> +     * someone else modifying the P2M wbefore the TLB invalidation has
>>>> Nit: Stray 'w'.
>>>>
>>>>> +     * completed.
>>>>> +     */
>>>>> +    p2m_tlb_flush_sync(p2m);
>>>> Wasn't the plan to have this be conditional?
>>> Not really, probably, I misunderstood you before.
>>>
>>> Previously, I only had|p2m_force_tlb_flush_sync()| here, instead of
>>> |p2m_tlb_flush_sync()|, and the latter includes a condition check on
>>> |p2m->need_flush|.
>> Just to re-iterate my point: Not every unlock will require a flush. Hence
>> why I expect the flush to be conditional upon there being an indication
>> that some change was done that requires flushing.
>>
> The flush is actually conditional; the condition is inside
> |p2m_tlb_flush_sync()|:
>    void p2m_tlb_flush_sync(struct p2m_domain *p2m)
>    {
>      if ( p2m->need_flush )
>        p2m_force_tlb_flush_sync(p2m);
>    }

Hmm, I'd consider this misleading function naming then. Especially with
"force" and "sync" being kind of redundant with one another already anyway.
See x86'es naming.

Jan


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Date: Mon, 11 Aug 2025 11:37:46 +0200
From: Nicola Vetrini 
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Cc: nicola.vetrini@gmail.com, xen-devel@lists.xenproject.org, Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Jan Beulich , Julien
 Grall , Stefano Stabellini 
Subject: Re: [XEN PATCH] xen: Drop logic for old clang versions.
In-Reply-To: 
References: 
 
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On 2025-08-11 09:47, Roger Pau Monné wrote:
> On Sun, Aug 10, 2025 at 03:03:53PM +0200, nicola.vetrini@gmail.com 
> wrote:
>> From: Nicola Vetrini 
>> 
>> The enforced toolchain baseline for clang is version 11,
>> therefore this logic is effectively dead code.
>> 
>> No functional change.
>> 
>> Signed-off-by: Nicola Vetrini 
> 
> Acked-by: Roger Pau Monné 
> 
>> ---
>> Mentioned in https://gitlab.com/xen-project/xen/-/issues/201
>> ---
>>  xen/common/coverage/llvm.c   | 4 ----
>>  xen/include/xen/self-tests.h | 9 +--------
>>  2 files changed, 1 insertion(+), 12 deletions(-)
>> 
>> diff --git a/xen/common/coverage/llvm.c b/xen/common/coverage/llvm.c
>> index 50d7a3c5d301..517b2aa8c202 100644
>> --- a/xen/common/coverage/llvm.c
>> +++ b/xen/common/coverage/llvm.c
>> @@ -44,12 +44,8 @@
>>      ((uint64_t)'f' << 16) | ((uint64_t)'R' << 8)  | ((uint64_t)129)
>>  #endif
>> 
>> -#if __clang_major__ >= 4 || (__clang_major__ == 3 && __clang_minor__ 
>> >= 9)
>>  #define LLVM_PROFILE_VERSION    4
>>  #define LLVM_PROFILE_NUM_KINDS  2
>> -#else
>> -#error "clang version not supported with coverage"
>> -#endif
> 
> Rant: most of the LLVM coverage stuff is already kind of dead code, as
> the format of the data changes between versions and there's no way for
> LLVM to generate the blob itself using a builtin function or
> similar.  We haven't kept up with new formats, and now it's not
> possible to parse the output coverage data when using newish LLVM
> versions.
> 
> Linux converts it's LLVM coverage data to gcov format (which AFAIK is
> way more stable), and exports it in gcov format.  We should consider
> importing that from Linux.
> 
> Thanks, Roger.

Fair point. Generally I found coverage reports generated using LLVM 
tooling a bit more informative than gcov's, but I don't know how much 
work would it be to adapt Xen for newer versions of LLVM.

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [PATCH] RFC x86/msr: Use WRMSRNS $imm when available
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808222013.1071291-1-andrew.cooper3@citrix.com>
 
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From: Andrew Cooper 
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On 11/08/2025 9:16 am, Jan Beulich wrote:
> On 09.08.2025 00:20, Andrew Cooper wrote:
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Jan Beulich 
>> CC: Roger Pau Monné 
>>
>> This is on top of the FRED series for the wrmsrns() cleanup, but otherwise
>> unrelated.
>>
>> The code generation isn't entirely ideal
>>
>>   Function                                     old     new   delta
>>   init_fred                                    255     274     +19
>>   vmx_set_reg                                  248     256      +8
>>   enter_state_helper.cold                     1014    1018      +4
>>   __start_xen                                 8893    8897      +4
>>
>> but made worse by the the prior codegen for wrmsrns(MSR_STAR, ...) being mad:
>>
>>   mov    $0xc0000081,%ecx
>>   mov    $0xe023e008,%edx
>>   movabs $0xe023e00800000000,%rax
>>   cs wrmsr
>>
>> The two sources of code expansion come from the compiler not being able to
>> construct %eax and %edx separately, and not being able propagate constants.
>>
>> Loading 0 is possibly common enough to warrant another specialisation where we
>> can use "a" (0), "d" (0) and forgo the MOV+SHR.
>>
>> I'm probably overthinking things.  The addition will be in the noise in
>> practice, and Intel are sure the advantage of MSR_IMM will not be.
> It's not entirely clear to me what the overall effects are now with your
> 02/22 reply on the FRED series.

The delta gets larger now that 2/22 isn't quite as bad as it was.

>  Nevertheless a nit or two here.
>
>> --- a/xen/arch/x86/include/asm/msr.h
>> +++ b/xen/arch/x86/include/asm/msr.h
>> @@ -38,9 +38,46 @@ static inline void wrmsrl(unsigned int msr, uint64_t val)
>>          wrmsr(msr, lo, hi);
>>  }
>>  
>> +/*
>> + * Non-serialising WRMSR with a compile-time constant index, when available.
>> + * Falls back to plain WRMSRNS, or to a serialising WRMSR.
>> + */
>> +static always_inline void __wrmsrns_imm(uint32_t msr, uint64_t val)
>> +{
>> +    /*
>> +     * For best performance, WRMSRNS %r64, $msr is recommended.  For
>> +     * compatibility, we need to fall back to plain WRMSRNS, or to WRMSR.
>> +     *
>> +     * The combined ABI is awkward, because WRMSRNS $imm takes a single r64,
>> +     * whereas WRMSR{,NS} takes a split edx:eax pair.
>> +     *
>> +     * Always use WRMSRNS %rax, $imm, because it has the most in common with
>> +     * the legacy forms.  When MSR_IMM isn't available, emit setup logic for
>> +     * %ecx and %edx too.
>> +     */
>> +    alternative_input_2(
>> +        "mov $%c[msr], %%ecx\n\t"
> Simply %[msr] here?
>
> And then, might it make sense to pull out this and ...
>
>> +        "mov %%rax, %%rdx\n\t"
>> +        "shr $32, %%rdx\n\t"
>> +        ".byte 0x2e; wrmsr",
>> +
>> +        /* WRMSRNS %rax, $msr */
>> +        ".byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
>> +
>> +        "mov $%c[msr], %%ecx\n\t"
> ... this, to ...
>
>> +        "mov %%rax, %%rdx\n\t"
>> +        "shr $32, %%rdx\n\t"
>> +        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
>> +
>> +        [msr] "i" (msr), "a" (val) : "rcx", "rdx");
>         [msr] "i" (msr), "a" (val), "c" (msr) : "rdx");
>
> allowing the compiler to actually know what's put in %ecx? That'll make
> original and 2nd replacement code 10 bytes, better balancing with the 9
> bytes of the 1st replacement. And I'd guess that the potentially dead
> MOV to %ecx would be hidden in the noise as well.

I considered that, but what can the compiler do as a result of knowing %ecx?

That said, we do need an RDMSR form (which I desperately want to make
foo = rdmsr(MSR_BAR) but my cleanup series from 2019 got nowhere), and
in a read+write case I suppose the compiler could deduplicate the setup
of %ecx.

A dead mov $imm, %ecx probably is as close to a nop as makes no difference.

~Andrew


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Subject: Re: [PATCH 3/5] CI: Update riscv64 to use Debian Trixie
To: Oleksii Kurochko ,
 Xen-devel 
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 Shawn Anastasio ,
 Doug Goldstein ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , Victor Lira 
References: <20250809221206.1260861-1-andrew.cooper3@citrix.com>
 <20250809221206.1260861-4-andrew.cooper3@citrix.com>
 <2919f22b-0b0c-488e-b0c6-96b9538e63d9@gmail.com>
Content-Language: en-GB
From: Andrew Cooper 
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In-Reply-To: <2919f22b-0b0c-488e-b0c6-96b9538e63d9@gmail.com>
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On 11/08/2025 9:43 am, Oleksii Kurochko wrote:
>
>
> On 8/10/25 12:12 AM, Andrew Cooper wrote:
>> Everything works fine with Debian 13.  Provide two new build jobs, and update
>> both the randconfig the test jobs.
>>
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Anthony PERARD 
>> CC: Michal Orzel 
>> CC: Jan Beulich 
>> CC: Julien Grall 
>> CC: Roger Pau Monné 
>> CC: Stefano Stabellini 
>> CC: Shawn Anastasio 
>> CC: Oleksii Kurochko 
>> CC: Doug Goldstein 
>> CC: Marek Marczykowski-Górecki 
>> CC: Victor Lira 
>>
>> https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1975929387
>> ---
>>  automation/gitlab-ci/build.yaml | 22 ++++++++++++++++++----
>>  automation/gitlab-ci/test.yaml  |  2 +-
>>  2 files changed, 19 insertions(+), 5 deletions(-)
>>
>> diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
>> index 3fe539dc5683..f8e45f3467c8 100644
>> --- a/automation/gitlab-ci/build.yaml
>> +++ b/automation/gitlab-ci/build.yaml
>> @@ -329,10 +329,10 @@ debian-13-ppc64le-gcc-debug:
>>        CONFIG_UBSAN=y
>>        CONFIG_UBSAN_FATAL=y
>>  
>> -debian-12-riscv64-gcc-debug:
>> +debian-13-riscv64-gcc-debug:
>>    extends: .gcc-riscv64-cross-build-debug
>>    variables:
>> -    CONTAINER: debian:12-riscv64
>> +    CONTAINER: debian:13-riscv64
>>      KBUILD_DEFCONFIG: tiny64_defconfig
>>      HYPERVISOR_ONLY: y
>>      EXTRA_XEN_CONFIG: |
>> @@ -727,6 +727,20 @@ debian-12-riscv64-gcc:
>>      KBUILD_DEFCONFIG: tiny64_defconfig
>>      HYPERVISOR_ONLY: y
>>  
>> +debian-12-riscv64-gcc-debug:
>> +  extends: .gcc-riscv64-cross-build-debug
>> +  variables:
>> +    CONTAINER: debian:12-riscv64
>> +    KBUILD_DEFCONFIG: tiny64_defconfig
>> +    HYPERVISOR_ONLY: y
> Don't you mind to keep an order? So:
>   debian-12-riscv64-gcc-debug:
>   ...
>   debian-13-riscv64-gcc-debug:
>   ...

Notice how those 2 hunks are 400 lines apart in the file.

This is deliberate so debian-13-riscv64-gcc-debug (the one needed for
tests) is scheduled with higher priority than the others.

The diff certainly isn't great, but this is necessary to shorten the
pipeline.

>
> Also, it will make a diff a little bit better.
>
>> +
>> +debian-13-riscv64-gcc:
>> +  extends: .gcc-riscv64-cross-build
>> +  variables:
>> +    CONTAINER: debian:13-riscv64
>> +    KBUILD_DEFCONFIG: tiny64_defconfig
>> +    HYPERVISOR_ONLY: y
>> +
>>  .riscv-fixed-randconfig:
>>    variables: &riscv-fixed-randconfig
>>      EXTRA_FIXED_RANDCONFIG: |
>> @@ -739,10 +753,10 @@ debian-12-riscv64-gcc:
>>        CONFIG_VM_EVENT=n
>>        CONFIG_XSM=n
>>  
>> -debian-12-riscv64-gcc-randconfig:
>> +debian-13-riscv64-gcc-randconfig:
> Are we going to have randconfig build test only for Debian-13?

We only have finite test capacity.

>
>>    extends: .gcc-riscv64-cross-build
>>    variables:
>> -    CONTAINER: debian:12-riscv64
>> +    CONTAINER: debian:13-riscv64
>>      KBUILD_DEFCONFIG: tiny64_defconfig
>>      RANDCONFIG: y
>>      <<: *riscv-fixed-randconfig
>> diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
>> index 2f6f3affa637..9acd984d294c 100644
>> --- a/automation/gitlab-ci/test.yaml
>> +++ b/automation/gitlab-ci/test.yaml
>> @@ -705,7 +705,7 @@ qemu-smoke-riscv64-gcc:
>>    script:
>>      - ./automation/scripts/qemu-smoke-riscv64.sh 2>&1 | tee ${LOGFILE}
>>    needs:
>> -    - debian-12-riscv64-gcc-debug
>> +    - debian-13-riscv64-gcc-debug
> The same as above, are we going to run smoke tests only for Debian-13?

Again, test capacity.  Even for x86 and ARM, we only have one main build
under test.

>
> If the answer to this and the question above is “yes,†then (probably
> keeping the order — first debian-12, then debian-13 — for the jobs):
>  Reviewed-by: Oleksii Kurochko 

Sorry, but rearranging is one thing that can't really happen.  Are you
happy with my justification?

~Andrew


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Date: Mon, 11 Aug 2025 10:56:46 +0100
MIME-Version: 1.0
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Subject: Re: [PATCH 1/5] CI: Trixie containers
To: Oleksii Kurochko ,
 Xen-devel 
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 Shawn Anastasio ,
 Doug Goldstein ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , Victor Lira 
References: <20250809221206.1260861-1-andrew.cooper3@citrix.com>
 <20250809221206.1260861-2-andrew.cooper3@citrix.com>
 <37edbe9d-3c14-422b-b21b-49a5fa25a453@gmail.com>
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On 11/08/2025 9:47 am, Oleksii Kurochko wrote:
>
>
> On 8/10/25 12:12 AM, Andrew Cooper wrote:
>> Debian Trixie has been released.  Provide new containers.
>>
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Anthony PERARD 
>> CC: Michal Orzel 
>> CC: Jan Beulich 
>> CC: Julien Grall 
>> CC: Roger Pau Monné 
>> CC: Stefano Stabellini 
>> CC: Shawn Anastasio 
>> CC: Oleksii Kurochko 
>> CC: Doug Goldstein 
>> CC: Marek Marczykowski-Górecki 
>> CC: Victor Lira 
>>
>> I've deployed these containers already so people can play.
>>
>> No ARM yet.  There's an (old) outstanding series cleaning up the arm
>> infrastructure, blocked on unclear root requirements for the Xilinx runners.
>> That series really needs fixing.
>> ---
>>  automation/build/debian/13-ppc64le.dockerfile | 37 ++++++++++
>>  automation/build/debian/13-riscv64.dockerfile | 37 ++++++++++
> LKGTM: Reviewed-by: Oleksii Kurochko  #riscv
>
> Also, shouldn’t we update the |automation/scripts/containerize| script to
> add Debian 13 support?

Yes, and I should probably put something in Changelog too.

~Andrew


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Subject: Re: [PATCH] RFC x86/msr: Use WRMSRNS $imm when available
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 Xen-devel 
References: <20250808222013.1071291-1-andrew.cooper3@citrix.com>
 
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On 11.08.2025 11:50, Andrew Cooper wrote:
> On 11/08/2025 9:16 am, Jan Beulich wrote:
>> On 09.08.2025 00:20, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/include/asm/msr.h
>>> +++ b/xen/arch/x86/include/asm/msr.h
>>> @@ -38,9 +38,46 @@ static inline void wrmsrl(unsigned int msr, uint64_t val)
>>>          wrmsr(msr, lo, hi);
>>>  }
>>>  
>>> +/*
>>> + * Non-serialising WRMSR with a compile-time constant index, when available.
>>> + * Falls back to plain WRMSRNS, or to a serialising WRMSR.
>>> + */
>>> +static always_inline void __wrmsrns_imm(uint32_t msr, uint64_t val)
>>> +{
>>> +    /*
>>> +     * For best performance, WRMSRNS %r64, $msr is recommended.  For
>>> +     * compatibility, we need to fall back to plain WRMSRNS, or to WRMSR.
>>> +     *
>>> +     * The combined ABI is awkward, because WRMSRNS $imm takes a single r64,
>>> +     * whereas WRMSR{,NS} takes a split edx:eax pair.
>>> +     *
>>> +     * Always use WRMSRNS %rax, $imm, because it has the most in common with
>>> +     * the legacy forms.  When MSR_IMM isn't available, emit setup logic for
>>> +     * %ecx and %edx too.
>>> +     */
>>> +    alternative_input_2(
>>> +        "mov $%c[msr], %%ecx\n\t"
>> Simply %[msr] here?
>>
>> And then, might it make sense to pull out this and ...
>>
>>> +        "mov %%rax, %%rdx\n\t"
>>> +        "shr $32, %%rdx\n\t"
>>> +        ".byte 0x2e; wrmsr",
>>> +
>>> +        /* WRMSRNS %rax, $msr */
>>> +        ".byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
>>> +
>>> +        "mov $%c[msr], %%ecx\n\t"
>> ... this, to ...
>>
>>> +        "mov %%rax, %%rdx\n\t"
>>> +        "shr $32, %%rdx\n\t"
>>> +        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
>>> +
>>> +        [msr] "i" (msr), "a" (val) : "rcx", "rdx");
>>         [msr] "i" (msr), "a" (val), "c" (msr) : "rdx");
>>
>> allowing the compiler to actually know what's put in %ecx? That'll make
>> original and 2nd replacement code 10 bytes, better balancing with the 9
>> bytes of the 1st replacement. And I'd guess that the potentially dead
>> MOV to %ecx would be hidden in the noise as well.
> 
> I considered that, but what can the compiler do as a result of knowing %ecx?

For example ...

> That said, we do need an RDMSR form (which I desperately want to make
> foo = rdmsr(MSR_BAR) but my cleanup series from 2019 got nowhere), and
> in a read+write case I suppose the compiler could deduplicate the setup
> of %ecx.

... this. But also simply to use a good pattern (exposing as much as possible
to the compiler), so there are more good instances of code for future cloning
from. (In size-optimizing builds, the compiler could further favor ADD/SUB
over MOV when the two MSRs accessed are relatively close together.)

Jan


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Subject: Re: [PATCH] RFC x86/msr: Use WRMSRNS $imm when available
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808222013.1071291-1-andrew.cooper3@citrix.com>
 
 <0d78dd8e-af92-4b29-9706-e08c2c06ee89@citrix.com>
 
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On 11/08/2025 11:06 am, Jan Beulich wrote:
> On 11.08.2025 11:50, Andrew Cooper wrote:
>> On 11/08/2025 9:16 am, Jan Beulich wrote:
>>> On 09.08.2025 00:20, Andrew Cooper wrote:
>>>> +        "mov %%rax, %%rdx\n\t"
>>>> +        "shr $32, %%rdx\n\t"
>>>> +        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
>>>> +
>>>> +        [msr] "i" (msr), "a" (val) : "rcx", "rdx");
>>>         [msr] "i" (msr), "a" (val), "c" (msr) : "rdx");
>>>
>>> allowing the compiler to actually know what's put in %ecx? That'll make
>>> original and 2nd replacement code 10 bytes, better balancing with the 9
>>> bytes of the 1st replacement. And I'd guess that the potentially dead
>>> MOV to %ecx would be hidden in the noise as well.
>> I considered that, but what can the compiler do as a result of knowing %ecx?
> For example ...
>
>> That said, we do need an RDMSR form (which I desperately want to make
>> foo = rdmsr(MSR_BAR) but my cleanup series from 2019 got nowhere), and
>> in a read+write case I suppose the compiler could deduplicate the setup
>> of %ecx.
> ... this. But also simply to use a good pattern (exposing as much as possible
> to the compiler), so there are more good instances of code for future cloning
> from. (In size-optimizing builds, the compiler could further favor ADD/SUB
> over MOV when the two MSRs accessed are relatively close together.)

I have seen the compiler do this in the past, but couldn't reproduce it
for this work.

We specifically do not want any conversion to ADD/SUB, because that
takes our "close to a nop" and makes it no so.

~Andrew


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Subject: Re: [PATCH] RFC x86/msr: Use WRMSRNS $imm when available
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808222013.1071291-1-andrew.cooper3@citrix.com>
 
 <0d78dd8e-af92-4b29-9706-e08c2c06ee89@citrix.com>
 
 
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On 11.08.2025 12:16, Andrew Cooper wrote:
> On 11/08/2025 11:06 am, Jan Beulich wrote:
>> On 11.08.2025 11:50, Andrew Cooper wrote:
>>> On 11/08/2025 9:16 am, Jan Beulich wrote:
>>>> On 09.08.2025 00:20, Andrew Cooper wrote:
>>>>> +        "mov %%rax, %%rdx\n\t"
>>>>> +        "shr $32, %%rdx\n\t"
>>>>> +        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
>>>>> +
>>>>> +        [msr] "i" (msr), "a" (val) : "rcx", "rdx");
>>>>         [msr] "i" (msr), "a" (val), "c" (msr) : "rdx");
>>>>
>>>> allowing the compiler to actually know what's put in %ecx? That'll make
>>>> original and 2nd replacement code 10 bytes, better balancing with the 9
>>>> bytes of the 1st replacement. And I'd guess that the potentially dead
>>>> MOV to %ecx would be hidden in the noise as well.
>>> I considered that, but what can the compiler do as a result of knowing %ecx?
>> For example ...
>>
>>> That said, we do need an RDMSR form (which I desperately want to make
>>> foo = rdmsr(MSR_BAR) but my cleanup series from 2019 got nowhere), and
>>> in a read+write case I suppose the compiler could deduplicate the setup
>>> of %ecx.
>> ... this. But also simply to use a good pattern (exposing as much as possible
>> to the compiler), so there are more good instances of code for future cloning
>> from. (In size-optimizing builds, the compiler could further favor ADD/SUB
>> over MOV when the two MSRs accessed are relatively close together.)
> 
> I have seen the compiler do this in the past, but couldn't reproduce it
> for this work.
> 
> We specifically do not want any conversion to ADD/SUB, because that
> takes our "close to a nop" and makes it no so.

Imo when size optimizing, size matters and "close-to-a-NOP" doesn't (as much).

Jan


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Date: Mon, 11 Aug 2025 11:48:19 +0100
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Subject: Re: [XEN PATCH 04/11] tools/configure: Introduce deps on json-c lib
 for libxl
To: Anthony PERARD , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Juergen Gross 
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On 08/08/2025 3:55 pm, Anthony PERARD wrote:
> diff --git a/tools/libs/light/Makefile b/tools/libs/light/Makefile
> index b690d92159..fa2a338c2b 100644
> --- a/tools/libs/light/Makefile
> +++ b/tools/libs/light/Makefile
> @@ -166,7 +166,8 @@ LDLIBS-$(CONFIG_Linux) += -luuid
>  LDLIBS-$(CONFIG_Linux) += -lrt
>  LDLIBS-$(CONFIG_ARM) += -lfdt
>  LDLIBS-y += $(PTHREAD_LIBS)
> -LDLIBS-y += -lyajl
> +LDLIBS-y += $(YAJL_LIBS)
> +LDLIBS-y += $(LIBJSONC_LIBS)
>  LDLIBS += $(LDLIBS-y)
>  
>  $(OBJS-y) $(PIC_OBJS) $(LIBXL_TEST_OBJS): CFLAGS += $(CFLAGS_LIBXL) -include $(XEN_ROOT)/tools/config.h
> @@ -246,7 +247,7 @@ libxenlight_test.so: $(PIC_OBJS) $(LIBXL_TEST_OBJS)
>  	$(CC) $(LDFLAGS) -Wl,$(SONAME_LDFLAG) -Wl,libxenlight.so.$(MAJOR) $(SHLIB_LDFLAGS) -o $@ $^ $(LDLIBS) $(APPEND_LDFLAGS)
>  
>  test_%: test_%.o test_common.o libxenlight_test.so
> -	$(CC) $(LDFLAGS) -o $@ $^ $(filter-out %libxenlight.so, $(LDLIBS_libxenlight)) $(LDLIBS_libxentoollog) $(LDLIBS_libxentoolcore) -lyajl $(APPEND_LDFLAGS)
> +	$(CC) $(LDFLAGS) -o $@ $^ $(filter-out %libxenlight.so, $(LDLIBS_libxenlight)) $(LDLIBS_libxentoollog) $(LDLIBS_libxentoolcore) $(YAJL_LIBS) $(LIBJSONC_LIBS) $(APPEND_LDFLAGS)
>  
>  libxl-save-helper: $(SAVE_HELPER_OBJS) libxenlight.so
>  	$(CC) $(LDFLAGS) -o $@ $(SAVE_HELPER_OBJS) $(LDLIBS_libxentoollog) $(LDLIBS_libxenctrl) $(LDLIBS_libxenguest) $(LDLIBS_libxentoolcore) $(APPEND_LDFLAGS)
> diff --git a/tools/xl/Makefile b/tools/xl/Makefile
> index ad577cdd70..ff7a5aee94 100644
> --- a/tools/xl/Makefile
> +++ b/tools/xl/Makefile
> @@ -33,7 +33,7 @@ $(XL_OBJS): CFLAGS += -include $(XEN_ROOT)/tools/config.h # libxl_json.h needs i
>  all: xl
>  
>  xl: $(XL_OBJS)
> -	$(CC) $(LDFLAGS) -o $@ $(XL_OBJS) $(LDLIBS_libxenutil) $(LDLIBS_libxenlight) $(LDLIBS_libxentoollog) $(LDLIBS_libxenstore) -lyajl $(APPEND_LDFLAGS)
> +	$(CC) $(LDFLAGS) -o $@ $(XL_OBJS) $(LDLIBS_libxenutil) $(LDLIBS_libxenlight) $(LDLIBS_libxentoollog) $(LDLIBS_libxenstore) $(YAJL_LIBS) $(LIBJSONC_LIBS) $(APPEND_LDFLAGS)
>  
>  .PHONY: install
>  install: all

Specifying both isn't entirely great when one is supposed to be empty.

Could we not have XEN_JSON_LIB(s) which is set to either $YAJL_LIBS or
$LIBJSONC_LIBS as appropriate?

~Andrew


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To: "xen-devel@lists.xenproject.org" 
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 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
From: Jan Beulich 
Subject: [PATCH v2 0/2] x86/mm: unmapping and marking-as-I/O in
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What we unmap there are mappings we better wouldn't have established in
the first place. Arrange for us to only ever map RAM, and then drop the
unmapping code, which was flawed anyway.

Nothing with a similar effect as patch 1 needs doing for xen.efi: Prior
to GNU binutils commit a844415db878 ("bfd/PE: correct SizeOfImage
calculation") too large a size was calculated. With that change in place,
image size is properly rounded up to a multiple of 2Mb.

1: mkelf32: pad load segment to 2Mb boundary
2: mm: drop unmapping from marking-as-I/O in arch_init_memory()

Jan


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Subject: [PATCH v2 1/2] x86/mkelf32: pad load segment to 2Mb boundary
From: Jan Beulich 
To: "xen-devel@lists.xenproject.org" 
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In order to legitimately set up initial mappings past _end[], we need
to make sure that the entire mapped range is inside a RAM region.
Therefore we need to inform the bootloader (or alike) that our allocated
size is larger than just the next SECTION_ALIGN-ed boundary past _end[].

This allows dropping a command line option from the tool, which was
introduced to work around a supposed linker bug, when the problem was
really Xen's.

While adjusting adjacent code, correct the argc check to also cover the
case correctly when --notes was passed.

Signed-off-by: Jan Beulich 
---
There's no good Fixes: tag, I don't think, as in theory the issue could
even have happened when we still required to be loaded at a fixed
physical address (1Mb originally, later 2Mb), and when we statically
mapped the low 16Mb. If we assumed such can't happen below 16Mb, these
two should be added:
Fixes: e4dd91ea85a3 ("x86: Ensure RAM holes really are not mapped in Xen's ongoing 1:1 physmap")
Fixes: 7cd7f2f5e116 ("x86/boot: Remove the preconstructed low 16M superpage mappings")
---
v2: New.

--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -130,8 +130,7 @@ orphan-handling-$(call ld-option,--orpha
 
 $(TARGET): TMP = $(dot-target).elf32
 $(TARGET): $(TARGET)-syms $(efi-y) $(obj)/boot/mkelf32
-	$(obj)/boot/mkelf32 $(notes_phdrs) $(TARGET)-syms $(TMP) $(XEN_IMG_OFFSET) \
-	               `$(NM) $(TARGET)-syms | sed -ne 's/^\([^ ]*\) . __2M_rwdata_end$$/0x\1/p'`
+	$(obj)/boot/mkelf32 $(notes_phdrs) $(TARGET)-syms $(TMP) $(XEN_IMG_OFFSET)
 	od -t x4 -N 8192 $(TMP)  | grep 1badb002 > /dev/null || \
 		{ echo "No Multiboot1 header found" >&2; false; }
 	od -t x4 -N 32768 $(TMP) | grep e85250d6 > /dev/null || \
--- a/xen/arch/x86/boot/mkelf32.c
+++ b/xen/arch/x86/boot/mkelf32.c
@@ -248,7 +248,6 @@ static void do_read(int fd, void *data,
 
 int main(int argc, char **argv)
 {
-    uint64_t   final_exec_addr;
     uint32_t   loadbase, dat_siz, mem_siz, note_base, note_sz, offset;
     char      *inimage, *outimage;
     int        infd, outfd;
@@ -261,22 +260,24 @@ int main(int argc, char **argv)
     Elf64_Ehdr in64_ehdr;
     Elf64_Phdr in64_phdr;
 
-    if ( argc < 5 )
+    if ( argc < 4 )
     {
+    help:
         fprintf(stderr, "Usage: mkelf32 [--notes]   "
-                " \n");
+                "\n");
         return 1;
     }
 
     if ( !strcmp(argv[1], "--notes") )
     {
+        if ( argc < 5 )
+            goto help;
         i = 2;
         num_phdrs = 2;
     }
     inimage  = argv[i++];
     outimage = argv[i++];
     loadbase = strtoul(argv[i++], NULL, 16);
-    final_exec_addr = strtoull(argv[i++], NULL, 16);
 
     infd = open(inimage, O_RDONLY);
     if ( infd == -1 )
@@ -339,9 +340,12 @@ int main(int argc, char **argv)
     (void)lseek(infd, in64_phdr.p_offset, SEEK_SET);
     dat_siz = (uint32_t)in64_phdr.p_filesz;
 
-    /* Do not use p_memsz: it does not include BSS alignment padding. */
-    /*mem_siz = (uint32_t)in64_phdr.p_memsz;*/
-    mem_siz = (uint32_t)(final_exec_addr - in64_phdr.p_vaddr);
+    /*
+     * We don't pad .bss in the linker script, but during early boot we map
+     * the Xen image using 2M pages.  To avoid running into adjacent non-RAM
+     * regions, pad the segment to the next 2M boundary.
+     */
+    mem_siz = ((uint32_t)in64_phdr.p_memsz + (1U << 20) - 1) & (-1U << 20);
 
     note_sz = note_base = offset = 0;
     if ( num_phdrs > 1 )



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Subject: [PATCH v2 2/2] x86/mm: drop unmapping from marking-as-I/O in
 arch_init_memory()
From: Jan Beulich 
To: "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
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The unmapping part would have wanted to cover UNUSABLE regions as well,
and it would now have been necessary for space outside the low 16Mb
(wherever Xen is placed). However, with everything up to the next 2Mb
boundary now properly backed by RAM, we don't need to unmap anything
anymore: Space up to __2M_rwdata_end[] is properly reserved, whereas
space past that mark (up to the next 2Mb boundary) is ordinary RAM.

While there, limit the scopes of involved variables.

Signed-off-by: Jan Beulich 
---
v2: Drop unmapping code altogether.

--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -275,8 +275,6 @@ static void __init assign_io_page(struct
 
 void __init arch_init_memory(void)
 {
-    unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn;
-
     /*
      * Basic guest-accessible flags:
      *   PRESENT, R/W, USER, A/D, AVAIL[0,1,2], AVAIL_HIGH, NX (if available).
@@ -292,12 +290,17 @@ void __init arch_init_memory(void)
      * case the low 1MB.
      */
     BUG_ON(pvh_boot && trampoline_phys != 0x1000);
-    for ( i = 0; i < 0x100; i++ )
+    for ( unsigned int i = 0; i < MB(1) >> PAGE_SHIFT; i++ )
         assign_io_page(mfn_to_page(_mfn(i)));
 
-    /* Any areas not specified as RAM by the e820 map are considered I/O. */
-    for ( i = 0, pfn = 0; pfn < max_page; i++ )
+    /*
+     * Any areas not specified as RAM or UNUSABLE by the e820 map are
+     * considered I/O.
+     */
+    for ( unsigned long i = 0, pfn = 0; pfn < max_page; i++ )
     {
+        unsigned long rstart_pfn, rend_pfn;
+
         while ( (i < e820.nr_map) &&
                 (e820.map[i].type != E820_RAM) &&
                 (e820.map[i].type != E820_UNUSABLE) )
@@ -317,17 +320,6 @@ void __init arch_init_memory(void)
                                PFN_DOWN(e820.map[i].addr + e820.map[i].size));
         }
 
-        /*
-         * Make sure any Xen mappings of RAM holes above 1MB are blown away.
-         * In particular this ensures that RAM holes are respected even in
-         * the statically-initialised 1-16MB mapping area.
-         */
-        iostart_pfn = max_t(unsigned long, pfn, 1UL << (20 - PAGE_SHIFT));
-        ioend_pfn = min(rstart_pfn, 16UL << (20 - PAGE_SHIFT));
-        if ( iostart_pfn < ioend_pfn )
-            destroy_xen_mappings((unsigned long)mfn_to_virt(iostart_pfn),
-                                 (unsigned long)mfn_to_virt(ioend_pfn));
-
         /* Mark as I/O up to next RAM region. */
         for ( ; pfn < rstart_pfn; pfn++ )
         {
@@ -365,6 +357,7 @@ void __init arch_init_memory(void)
                     const l3_pgentry_t *l3idle = map_l3t_from_l4e(
                             idle_pg_table[l4_table_offset(split_va)]);
                     l3_pgentry_t *l3tab = map_domain_page(l3mfn);
+                    unsigned int i;
 
                     for ( i = 0; i < l3_table_offset(split_va); ++i )
                         l3tab[i] = l3idle[i];



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To: "xen-devel@lists.xenproject.org" 
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From: Jan Beulich 
Subject: [PATCH] ELF: correct .note.* alignment handling
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The present uniform 4-byte alignment hasn't been right for, I think, a
very long time (albeit not forever). As per e.g. [1], 8-byte alignment
is required in 64-bit ELF containers (and assembler-generated
.note.gnu.property, for example, is 8-byte aligned, while - oddly -
linker-generated .note.gnu.build-id is only 4-byte aligned [2]). Sadly
libelf is also affected, and hence going strictly by the spec would
break kernels also getting it wrong (e.g. Linux). Apply the same
heuristic as GNU readelf does: If section alignment is 4 or less, assume
only 4-byte padding.

[1] https://refspecs.linuxfoundation.org/elf/gabi4+/ch5.pheader.html#note_section
[2] https://sourceware.org/bugzilla/show_bug.cgi?id=33259

Signed-off-by: Jan Beulich 
---
x86's mkelf32 also isn't dealing right with .note.* sections: Due to the
different padding rules for 32- and 64-bit ELF, what is correct in
xen-syms would need adjustment in xen. Question is whether we care
enough, as long as it's only a cosmetic problem: In the shim, the Xen
note comes first, and that's the only thing that really needs looking at
from the outside, aiui. (Since we actively tail-pad .note.Xen entries,
.note.gnu-build-id ends up correctly placed anyway, despite GNU ld only
aligning it at a 4-byte boundary.)

Arguably the spec text is ambiguous as to the width of namesz, descsz,
and type: They could well be meant to be 8-byte quantities in 64-bit
ELF as per "each entry is an array of 8-byte words". Yet with everyone
using 4-byte fields, that's the defacto standard now anyway.

--- a/xen/arch/x86/include/asm/asm_defns.h
+++ b/xen/arch/x86/include/asm/asm_defns.h
@@ -334,14 +334,14 @@ static always_inline void stac(void)
 
 #define ELFNOTE(name, type, desc)           \
     .pushsection .note.name, "a", @note   ; \
-    .p2align 2                            ; \
+    .balign BYTES_PER_LONG                ; \
     .long 2f - 1f       /* namesz */      ; \
     .long 4f - 3f       /* descsz */      ; \
     .long type          /* type   */      ; \
 1:  .asciz #name        /* name   */      ; \
-2:  .p2align 2                            ; \
+2:  .balign BYTES_PER_LONG                ; \
 3:  desc                /* desc   */      ; \
-4:  .p2align 2                            ; \
+4:  .balign BYTES_PER_LONG                ; \
     .popsection
 
 #define ASM_CONSTANT(name, value)                \
--- a/xen/common/libelf/libelf-dominfo.c
+++ b/xen/common/libelf/libelf-dominfo.c
@@ -583,6 +583,8 @@ elf_errorstatus elf_xen_parse(struct elf
     count = elf_phdr_count(elf);
     for ( i = 0; i < count; i++ )
     {
+        unsigned orig_align = elf->note_align;
+
         phdr = elf_phdr_by_index(elf, i);
         if ( !elf_access_ok(elf, ELF_HANDLE_PTRVAL(phdr), 1) )
             /* input has an insane program header count field */
@@ -597,10 +599,15 @@ elf_errorstatus elf_xen_parse(struct elf
         if (elf_uval(elf, phdr, p_offset) == 0)
              continue;
 
+        elf->note_align = elf_uval(elf, phdr, p_align);
+
         more_notes = elf_xen_parse_notes(elf, parms,
                                  elf_segment_start(elf, phdr),
                                  elf_segment_end(elf, phdr),
                                  &total_note_count);
+
+        elf->note_align = orig_align;
+
         if ( more_notes == ELF_NOTE_INVALID )
             return -1;
 
@@ -616,6 +623,8 @@ elf_errorstatus elf_xen_parse(struct elf
         count = elf_shdr_count(elf);
         for ( i = 1; i < count; i++ )
         {
+            unsigned orig_align = elf->note_align;
+
             shdr = elf_shdr_by_index(elf, i);
             if ( !elf_access_ok(elf, ELF_HANDLE_PTRVAL(shdr), 1) )
                 /* input has an insane section header count field */
@@ -624,11 +633,15 @@ elf_errorstatus elf_xen_parse(struct elf
             if ( elf_uval(elf, shdr, sh_type) != SHT_NOTE )
                 continue;
 
+            elf->note_align = elf_uval(elf, shdr, sh_addralign);
+
             more_notes = elf_xen_parse_notes(elf, parms,
                                      elf_section_start(elf, shdr),
                                      elf_section_end(elf, shdr),
                                      &total_note_count);
 
+            elf->note_align = orig_align;
+
             if ( more_notes == ELF_NOTE_INVALID )
                 return -1;
 
--- a/xen/common/libelf/libelf-loader.c
+++ b/xen/common/libelf/libelf-loader.c
@@ -72,6 +72,9 @@ elf_errorstatus elf_init(struct elf_bina
         return -1;
     }
 
+    /* Record default note alignment, as per EI_CLASS. */
+    elf->note_align = elf_64bit(elf) ? 8 : 4;
+
     /* Find section string table. */
     section = elf_uval(elf, elf->ehdr, e_shstrndx);
     shdr = elf_shdr_by_index(elf, section);
--- a/xen/common/libelf/libelf-tools.c
+++ b/xen/common/libelf/libelf-tools.c
@@ -288,6 +288,20 @@ ELF_HANDLE_DECL(elf_sym) elf_sym_by_inde
     return sym;
 }
 
+/*
+ * Notes are special: Formally for a long time the spec has demanded that
+ * 64-bit ELF would have 8-byte padding at respective places.  However, many
+ * producers were never updated, so apply a heuristic GNU readelf also applies:
+ * Take section (or segment) alignment into consideration.  When alignment is 4
+ * or less, assume only 4-byte padding.
+ */
+static unsigned elf_note_round_up(const struct elf_binary *elf, unsigned pos)
+{
+    unsigned align = elf_32bit(elf) || elf->note_align <= 4 ? 4 : 8;
+
+    return (pos + align - 1) & ~(align - 1);
+}
+
 const char *elf_note_name(struct elf_binary *elf, ELF_HANDLE_DECL(elf_note) note)
 {
     return elf_strval(elf, ELF_HANDLE_PTRVAL(note) + elf_size(elf, note));
@@ -295,9 +309,9 @@ const char *elf_note_name(struct elf_bin
 
 elf_ptrval elf_note_desc(struct elf_binary *elf, ELF_HANDLE_DECL(elf_note) note)
 {
-    unsigned namesz = (elf_uval(elf, note, namesz) + 3) & ~3;
-
-    return ELF_HANDLE_PTRVAL(note) + elf_size(elf, note) + namesz;
+    return ELF_HANDLE_PTRVAL(note) +
+           elf_note_round_up(elf,
+                             elf_size(elf, note) + elf_uval(elf, note, namesz));
 }
 
 uint64_t elf_note_numeric(struct elf_binary *elf, ELF_HANDLE_DECL(elf_note) note)
@@ -339,11 +353,9 @@ uint64_t elf_note_numeric_array(struct e
 
 ELF_HANDLE_DECL(elf_note) elf_note_next(struct elf_binary *elf, ELF_HANDLE_DECL(elf_note) note)
 {
-    unsigned namesz = (elf_uval(elf, note, namesz) + 3) & ~3;
-    unsigned descsz = (elf_uval(elf, note, descsz) + 3) & ~3;
-
-    elf_ptrval ptrval = ELF_HANDLE_PTRVAL(note)
-        + elf_size(elf, note) + namesz + descsz;
+    elf_ptrval ptrval =
+        elf_note_desc(elf, note) +
+        elf_note_round_up(elf, elf_uval(elf, note, descsz));
 
     if ( ( ptrval <= ELF_HANDLE_PTRVAL(note) || /* wrapped or stuck */
            !elf_access_ok(elf, ELF_HANDLE_PTRVAL(note), 1) ) )
--- a/xen/include/xen/elf.h
+++ b/xen/include/xen/elf.h
@@ -29,7 +29,7 @@
 
 #include 
 
-#define ELFNOTE_ALIGN(_n_) (((_n_)+3)&~3)
+#define ELFNOTE_ALIGN(_n_) ROUNDUP(_n_, BYTES_PER_LONG)
 #define ELFNOTE_NAME(_n_) ((char*)(_n_) + sizeof(*(_n_)))
 #define ELFNOTE_DESC(_n_) (ELFNOTE_NAME(_n_) + ELFNOTE_ALIGN((_n_)->namesz))
 #define ELFNOTE_NEXT(_n_) ((Elf_Note *)(ELFNOTE_DESC(_n_) + ELFNOTE_ALIGN((_n_)->descsz)))
--- a/xen/include/xen/libelf.h
+++ b/xen/include/xen/libelf.h
@@ -181,6 +181,12 @@ struct elf_binary {
     char class;
     char data;
 
+    /*
+     * Note alignment is defaulted from EI_CLASS, but overridden by
+     * segment / section alignment.
+     */
+    unsigned note_align;
+
     ELF_HANDLE_DECL(elf_ehdr) ehdr;
     elf_ptrval sec_strtab;
     ELF_HANDLE_DECL(elf_shdr) sym_tab;


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Date: Mon, 11 Aug 2025 11:55:04 +0100
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Subject: Re: [XEN PATCH 11/11] Update CHANGELOG and README with dependency on
 json-c
To: Anthony PERARD , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Oleksii Kurochko ,
 Community Manager ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini 
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-12-anthony@xenproject.org>
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In-Reply-To: <20250808145602.41716-12-anthony@xenproject.org>
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On 08/08/2025 3:56 pm, Anthony PERARD wrote:
> From: Anthony PERARD 
>
> Signed-off-by: Anthony PERARD 
> ---
>  CHANGELOG.md | 2 ++
>  README       | 2 +-
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/CHANGELOG.md b/CHANGELOG.md
> index 5f31ca08fe..83195e2dae 100644
> --- a/CHANGELOG.md
> +++ b/CHANGELOG.md
> @@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
>     - For x86, GCC 5.1 and Binutils 2.25, or Clang/LLVM 11
>     - For ARM32 and ARM64, GCC 5.1 and Binutils 2.25
>   - Linux based device model stubdomains are now fully supported.
> + - New dependency on library json-c, the toolstack will prefer it to `YAJL`
> +   when available.
>  
>   - On x86:
>     - Restrict the cache flushing done as a result of guest physical memory map
> diff --git a/README b/README
> index 6ee58f7b35..9329f30e13 100644
> --- a/README
> +++ b/README
> @@ -53,7 +53,7 @@ provided by your OS distributor:
>      * Development install of Python 2.7 or later (e.g., python-dev)
>      * Development install of curses (e.g., libncurses-dev)
>      * Development install of uuid (e.g. uuid-dev)
> -    * Development install of yajl (e.g. libyajl-dev)
> +    * Development install of json-c (e.g. libjson-c-dev) or yajl (e.g. libyajl-dev)
>      * Development install of libaio (e.g. libaio-dev) version 0.3.107 or
>        greater.
>      * Development install of GLib v2.0 (e.g. libglib2.0-dev)

What are we going to do about testing this?

We should add libjson-c to some build containers.  We need to annotate #
Xen < 4.21 in the existing containers so we can drop it in due course.

Also, for a container we don't intend to backport to stable trees, we
should have libjson-c only and no yajl.  Probably best to do this in the
Alpine update which is long overdue.

~Andrew


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Date: Mon, 11 Aug 2025 13:00:00 +0200
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 Grall" , Xen-devel
	
Subject: Re: [PATCH v15 1/4] xen/domain: unify domain ID allocation
From: Alejandro Vallejo 
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On Sat Aug 9, 2025 at 7:08 PM CEST, dmkhn wrote:
> From: Denis Mukhin =20
>
> Currently, there are two different domain ID allocation implementations:
>
>   1) Sequential IDs allocation in dom0less Arm code based on max_init_dom=
id;
>
>   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
>      max_init_domid (both Arm and x86).
>
> The domain ID allocation covers dom0 or late hwdom, predefined domains,
> post-boot domains, excluding Xen system domains (domid >=3D
> DOMID_FIRST_RESERVED).
>
> It makes sense to have a common helper code for such task across architec=
tures
> (Arm and x86) and between dom0less / toolstack domU allocation.
>
> Note, fixing dependency on max_init_domid is out of scope of this patch.
>
> Wrap the domain ID allocation as an arch-independent function domid_alloc=
() in
> new common/domid.c based on the bitmap.
>
> Allocation algorithm:
> - If an explicit domain ID is provided, verify its availability and use i=
t if
>   ID is not used;
> - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED=
-1],
>   starting from the last used ID.
>   Implementation guarantees that two consecutive calls will never return =
the
>   same ID. ID#0 is reserved for the first boot domain (currently, dom0) a=
nd
>   excluded from the allocation range.
>
> Remove is_free_domid() helper as it is not needed now.
>
> No functional change intended.
>
> Signed-off-by: Denis Mukhin 
> Reviewed-by: Julien Grall 

There's a nit below about a change in v14, but with or without that:

  Reviewed-by: Alejandro Vallejo 

> ---
> Changes since v14:
> - added Julien's R-b
> ---
>  xen/arch/arm/domain_build.c             |  7 +-
>  xen/arch/x86/setup.c                    |  7 +-
>  xen/common/Makefile                     |  1 +
>  xen/common/device-tree/dom0less-build.c | 15 ++--
>  xen/common/domain.c                     |  2 +
>  xen/common/domctl.c                     | 43 ++---------
>  xen/common/domid.c                      | 95 +++++++++++++++++++++++++
>  xen/include/xen/domain.h                |  3 +
>  8 files changed, 126 insertions(+), 47 deletions(-)
>  create mode 100644 xen/common/domid.c
>
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index 463ae4474d30..789f2b9d3ce7 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -2050,6 +2050,7 @@ void __init create_dom0(void)
>          .grant_opts =3D XEN_DOMCTL_GRANT_version(opt_gnttab_max_version)=
,
>      };
>      unsigned int flags =3D CDF_privileged | CDF_hardware;
> +    domid_t domid;
>      int rc;
> =20
>      /* The vGIC for DOM0 is exactly emulating the hardware GIC */
> @@ -2074,7 +2075,11 @@ void __init create_dom0(void)
>      if ( !llc_coloring_enabled )
>          flags |=3D CDF_directmap;
> =20
> -    dom0 =3D domain_create(0, &dom0_cfg, flags);
> +    domid =3D domid_alloc(0);
> +    if ( domid =3D=3D DOMID_INVALID )
> +        panic("Error allocating domain ID 0\n");
> +
> +    dom0 =3D domain_create(domid, &dom0_cfg, flags);
>      if ( IS_ERR(dom0) )
>          panic("Error creating domain 0 (rc =3D %ld)\n", PTR_ERR(dom0));
> =20
> diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
> index 1543dd251cc6..398da734c0c5 100644
> --- a/xen/arch/x86/setup.c
> +++ b/xen/arch/x86/setup.c
> @@ -1047,8 +1047,11 @@ static struct domain *__init create_dom0(struct bo=
ot_info *bi)
>      if ( iommu_enabled )
>          dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu;
> =20
> -    /* Create initial domain.  Not d0 for pvshim. */
> -    bd->domid =3D get_initial_domain_id();
> +    /* Allocate initial domain ID.  Not d0 for pvshim. */
> +    bd->domid =3D domid_alloc(get_initial_domain_id());
> +    if ( bd->domid =3D=3D DOMID_INVALID )
> +        panic("Error allocating domain ID %u\n", get_initial_domain_id()=
);
> +
>      d =3D domain_create(bd->domid, &dom0_cfg,
>                        pv_shim ? 0 : CDF_privileged | CDF_hardware);
>      if ( IS_ERR(d) )
> diff --git a/xen/common/Makefile b/xen/common/Makefile
> index c316957fcb36..0c7d0f5d46e1 100644
> --- a/xen/common/Makefile
> +++ b/xen/common/Makefile
> @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) +=3D dev=
ice.o
>  obj-$(CONFIG_DEVICE_TREE_PARSE) +=3D device-tree/
>  obj-$(CONFIG_IOREQ_SERVER) +=3D dm.o
>  obj-y +=3D domain.o
> +obj-y +=3D domid.o
>  obj-y +=3D event_2l.o
>  obj-y +=3D event_channel.o
>  obj-$(CONFIG_EVTCHN_FIFO) +=3D event_fifo.o
> diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-=
tree/dom0less-build.c
> index 6bb038111de9..f4b6b515d2d2 100644
> --- a/xen/common/device-tree/dom0less-build.c
> +++ b/xen/common/device-tree/dom0less-build.c
> @@ -833,6 +833,7 @@ void __init create_domUs(void)
>      {
>          struct kernel_info ki =3D KERNEL_INFO_INIT;
>          int rc =3D parse_dom0less_node(node, &ki.bd);
> +        domid_t domid;
> =20
>          if ( rc =3D=3D -ENOENT )
>              continue;
> @@ -842,13 +843,13 @@ void __init create_domUs(void)
>          if ( (max_init_domid + 1) >=3D DOMID_FIRST_RESERVED )
>              panic("No more domain IDs available\n");
> =20
> -        /*
> -         * The variable max_init_domid is initialized with zero, so here=
 it's
> -         * very important to use the pre-increment operator to call
> -         * domain_create() with a domid > 0. (domid =3D=3D 0 is reserved=
 for Dom0)
> -         */
> -        ki.bd.d =3D domain_create(++max_init_domid,
> -                                &ki.bd.create_cfg, ki.bd.create_flags);
> +        domid =3D domid_alloc(DOMID_INVALID);
> +        if ( domid =3D=3D DOMID_INVALID )
> +            panic("Error allocating ID for domain %s\n", dt_node_name(no=
de));
> +
> +        max_init_domid =3D max(max_init_domid, domid);
> +
> +        ki.bd.d =3D domain_create(domid, &ki.bd.create_cfg, ki.bd.create=
_flags);
>          if ( IS_ERR(ki.bd.d) )
>              panic("Error creating domain %s (rc =3D %ld)\n",
>                    dt_node_name(node), PTR_ERR(ki.bd.d));
> diff --git a/xen/common/domain.c b/xen/common/domain.c
> index 5241a1629eeb..a7e303253d1a 100644
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -692,6 +692,8 @@ static void _domain_destroy(struct domain *d)
> =20
>      lock_profile_deregister_struct(LOCKPROF_TYPE_PERDOM, d);
> =20
> +    domid_free(d->domain_id);
> +
>      free_domain_struct(d);
>  }
> =20
> diff --git a/xen/common/domctl.c b/xen/common/domctl.c
> index f2a7caaf853c..71e712c1f316 100644
> --- a/xen/common/domctl.c
> +++ b/xen/common/domctl.c
> @@ -51,20 +51,6 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nodem=
ask,
>                                     MAX_NUMNODES);
>  }
> =20
> -static inline int is_free_domid(domid_t dom)
> -{
> -    struct domain *d;
> -
> -    if ( dom >=3D DOMID_FIRST_RESERVED )
> -        return 0;
> -
> -    if ( (d =3D rcu_lock_domain_by_id(dom)) =3D=3D NULL )
> -        return 1;
> -
> -    rcu_unlock_domain(d);
> -    return 0;
> -}
> -
>  void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *in=
fo)
>  {
>      struct vcpu *v;
> @@ -423,36 +409,19 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t)=
 u_domctl)
> =20
>      case XEN_DOMCTL_createdomain:
>      {
> -        domid_t        dom;
> -        static domid_t rover =3D 0;
> +        /* NB: ID#0 is reserved, find the first suitable ID instead. */
> +        domid_t domid =3D domid_alloc(op->domain ?: DOMID_INVALID);
> =20
> -        dom =3D op->domain;
> -        if ( (dom > 0) && (dom < DOMID_FIRST_RESERVED) )
> +        if ( domid =3D=3D DOMID_INVALID )
>          {
>              ret =3D -EEXIST;
> -            if ( !is_free_domid(dom) )
> -                break;
> -        }
> -        else
> -        {
> -            for ( dom =3D rover + 1; dom !=3D rover; dom++ )
> -            {
> -                if ( dom =3D=3D DOMID_FIRST_RESERVED )
> -                    dom =3D 1;
> -                if ( is_free_domid(dom) )
> -                    break;
> -            }
> -
> -            ret =3D -ENOMEM;
> -            if ( dom =3D=3D rover )
> -                break;
> -
> -            rover =3D dom;
> +            break;
>          }
> =20
> -        d =3D domain_create(dom, &op->u.createdomain, false);
> +        d =3D domain_create(domid, &op->u.createdomain, false);
>          if ( IS_ERR(d) )
>          {
> +            domid_free(domid);
>              ret =3D PTR_ERR(d);
>              d =3D NULL;
>              break;
> diff --git a/xen/common/domid.c b/xen/common/domid.c
> new file mode 100644
> index 000000000000..7839a2885810
> --- /dev/null
> +++ b/xen/common/domid.c
> @@ -0,0 +1,95 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Domain ID allocator.
> + *
> + * Covers dom0 or late hwdom, predefined domains, post-boot domains.
> + * Excludes system domains (ID >=3D DOMID_FIRST_RESERVED).
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#include 
> +
> +static DEFINE_SPINLOCK(domid_lock);
> +static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED);
> +
> +/*
> + * Allocate domain ID.
> + *
> + * @param domid Domain ID hint:
> + * - If an explicit domain ID is provided, verify its availability and u=
se it
> + *   if ID is not used;
> + * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] ra=
nge,
> + *   starting from the last used ID. Implementation guarantees that two
> + *   consecutive calls will never return the same ID. ID#0 is reserved f=
or
> + *   the first boot domain (currently, dom0) and excluded from the alloc=
ation
> + *   range.
> + * @return Valid domain ID in case of successful allocation,
> + *         DOMID_INVALID - otherwise.
> + */
> +domid_t domid_alloc(domid_t domid)
> +{
> +    static domid_t domid_last;
> +
> +    spin_lock(&domid_lock);
> +
> +    /* Exact match. */
> +    if ( domid < DOMID_FIRST_RESERVED )
> +    {
> +        if ( __test_and_set_bit(domid, domid_bitmap) )
> +            domid =3D DOMID_INVALID;
> +    }
> +    /*
> +     * Exhaustive search.
> +     *
> +     * Domain ID#0 is reserved for the first boot domain (e.g. control d=
omain)
> +     * and excluded from allocation.
> +     */
> +    else
> +    {
> +        domid_t num =3D DOMID_FIRST_RESERVED;

nit: s/num/bound/, or something like that.

I don't care much though. If there's not going to be a v16 (and I hope not.=
 The
series has been girdling the mailing list long enough) feel free to ignore =
this.

> +
> +        domid =3D find_next_zero_bit(domid_bitmap, , domid_last + 1);
> +        if ( domid =3D=3D num && domid_last !=3D 0 )
> +        {
> +            num =3D domid_last + 1;
> +            domid =3D find_next_zero_bit(domid_bitmap, num, 1);
> +        }
> +
> +        ASSERT(domid <=3D DOMID_FIRST_RESERVED);
> +        if ( domid < num )
> +        {
> +            __set_bit(domid, domid_bitmap);
> +            domid_last =3D domid;
> +        }
> +        else
> +            domid =3D DOMID_INVALID;
> +    }
> +
> +    spin_unlock(&domid_lock);
> +
> +    return domid;
> +}
> +
> +void domid_free(domid_t domid)
> +{
> +    int rc;
> +
> +    ASSERT(domid <=3D DOMID_FIRST_RESERVED);
> +
> +    spin_lock(&domid_lock);
> +    rc =3D __test_and_clear_bit(domid, domid_bitmap);
> +    spin_unlock(&domid_lock);
> +
> +    ASSERT(rc);
> +}
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * tab-width: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
> index e10baf2615fd..8aab05ae93c8 100644
> --- a/xen/include/xen/domain.h
> +++ b/xen/include/xen/domain.h
> @@ -38,6 +38,9 @@ void arch_get_domain_info(const struct domain *d,
> =20
>  domid_t get_initial_domain_id(void);
> =20
> +domid_t domid_alloc(domid_t domid);
> +void domid_free(domid_t domid);
> +
>  /* CDF_* constant. Internal flags for domain creation. */
>  /* Is this a privileged domain? */
>  #define CDF_privileged           (1U << 0)



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To: "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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From: Jan Beulich 
Subject: [PATCH for-4.21?] x86: drop detection of ld supporting
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GNU ld 2.25 supports this, and we already assume all lld versions do.

Signed-off-by: Jan Beulich 
---
While past the submission deadline, this fits the toolchain baseline
update we did in this release cycle, so I'd like to ask that it be
considered to still permit this in.

--- a/xen/arch/x86/arch.mk
+++ b/xen/arch/x86/arch.mk
@@ -72,16 +72,6 @@ ifeq ($(CONFIG_UBSAN),y)
 $(call cc-option-add,CFLAGS_UBSAN,CC,-fno-sanitize=alignment)
 endif
 
-ifeq ($(CONFIG_LD_IS_GNU),y)
-# While not much better than going by raw GNU ld version, utilize that the
-# feature we're after has appeared in the same release as the
-# --print-output-format command line option.
-AFLAGS-$(call ld-option,--print-output-format) += -DHAVE_LD_SORT_BY_INIT_PRIORITY
-else
-# Assume all versions of LLD support this.
-AFLAGS += -DHAVE_LD_SORT_BY_INIT_PRIORITY
-endif
-
 ifneq ($(CONFIG_PV_SHIM_EXCLUSIVE),y)
 
 efi-check := arch/x86/efi/check
--- a/xen/arch/x86/xen.lds.S
+++ b/xen/arch/x86/xen.lds.S
@@ -35,10 +35,6 @@ ENTRY(start_pa)
 # define SECTION_ALIGN PAGE_SIZE
 #endif
 
-#ifndef HAVE_LD_SORT_BY_INIT_PRIORITY
-# define SORT_BY_INIT_PRIORITY SORT
-#endif
-
 OUTPUT_FORMAT(FORMAT, FORMAT, FORMAT)
 
 OUTPUT_ARCH(i386:x86-64)


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Subject: Re: [PATCH for-4.21?] x86: drop detection of ld supporting
 SORT_BY_INIT_PRIORITY()
To: Jan Beulich ,
 "xen-devel@lists.xenproject.org" 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Oleksii Kurochko 
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On 11/08/2025 12:02 pm, Jan Beulich wrote:
> GNU ld 2.25 supports this, and we already assume all lld versions do.
>
> Signed-off-by: Jan Beulich 

Acked-by: Andrew Cooper 

> ---
> While past the submission deadline, this fits the toolchain baseline
> update we did in this release cycle, so I'd like to ask that it be
> considered to still permit this in.

There's loads of cleanup still in the ticket I made and talked about at
the start of 4.21.

There are a view bits posted and still in need of pushing through, but I
consider anything along these lines to be fair game in the short term.

~Andrew


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Subject: Re: [PATCH v15 1/4] xen/domain: unify domain ID allocation
To: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org,
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On 09.08.2025 19:08, dmkhn@proton.me wrote:
> --- /dev/null
> +++ b/xen/common/domid.c
> @@ -0,0 +1,95 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Domain ID allocator.
> + *
> + * Covers dom0 or late hwdom, predefined domains, post-boot domains.
> + * Excludes system domains (ID >= DOMID_FIRST_RESERVED).
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#include 
> +
> +static DEFINE_SPINLOCK(domid_lock);
> +static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED);
> +
> +/*
> + * Allocate domain ID.
> + *
> + * @param domid Domain ID hint:
> + * - If an explicit domain ID is provided, verify its availability and use it
> + *   if ID is not used;
> + * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] range,
> + *   starting from the last used ID. Implementation guarantees that two
> + *   consecutive calls will never return the same ID. ID#0 is reserved for
> + *   the first boot domain (currently, dom0) and excluded from the allocation
> + *   range.
> + * @return Valid domain ID in case of successful allocation,
> + *         DOMID_INVALID - otherwise.
> + */
> +domid_t domid_alloc(domid_t domid)
> +{
> +    static domid_t domid_last;
> +
> +    spin_lock(&domid_lock);
> +
> +    /* Exact match. */
> +    if ( domid < DOMID_FIRST_RESERVED )
> +    {
> +        if ( __test_and_set_bit(domid, domid_bitmap) )
> +            domid = DOMID_INVALID;
> +    }
> +    /*
> +     * Exhaustive search.
> +     *
> +     * Domain ID#0 is reserved for the first boot domain (e.g. control domain)
> +     * and excluded from allocation.
> +     */
> +    else
> +    {
> +        domid_t num = DOMID_FIRST_RESERVED;
> +
> +        domid = find_next_zero_bit(domid_bitmap, num, domid_last + 1);
> +        if ( domid == num && domid_last != 0 )

I'm pretty sure I commented on this before, yet then maybe it was in the context
of another patch: Using == here isn't sufficient; it needs to be >=. See e.g.
cpumask_next().

Jan


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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
	nvdimm@lists.linux.dev,
	linuxppc-dev@lists.ozlabs.org,
	David Hildenbrand ,
	Andrew Morton ,
	Madhavan Srinivasan ,
	Michael Ellerman ,
	Nicholas Piggin ,
	Christophe Leroy ,
	Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	Dan Williams ,
	Matthew Wilcox ,
	Jan Kara ,
	Alexander Viro ,
	Christian Brauner ,
	Lorenzo Stoakes ,
	"Liam R. Howlett" ,
	Vlastimil Babka ,
	Mike Rapoport ,
	Suren Baghdasaryan ,
	Michal Hocko ,
	Zi Yan ,
	Baolin Wang ,
	Nico Pache ,
	Ryan Roberts ,
	Dev Jain ,
	Barry Song ,
	Jann Horn ,
	Pedro Falcato ,
	Hugh Dickins ,
	Oscar Salvador ,
	Lance Yang 
Subject: [PATCH v3 00/11] mm: vm_normal_page*() improvements
Date: Mon, 11 Aug 2025 13:26:20 +0200
Message-ID: <20250811112631.759341-1-david@redhat.com>
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Based on mm/mm-new from today.

Cleanup and unify vm_normal_page_*() handling, also marking the
huge zerofolio as special in the PMD. Add+use vm_normal_page_pud() and
cleanup that XEN vm_ops->find_special_page thingy.

There are plans of using vm_normal_page_*() more widely soon.

Briefly tested on UML (making sure vm_normal_page() still works as expected
without pte_special() support) and on x86-64 with a bunch of tests.
Cross-compiled for a variety of weird archs.

v2 -> v3:
* "mm/huge_memory: mark PMD mappings of the huge zero folio special"
 -> Extend vm_normal_page_pmd() comment + patch description
 -> Take care of copy_huge_pmd() checking for pmd_special().
* "powerpc/ptdump: rename "struct pgtable_level" to "struct ptdump_pglevel""
 -> Added
* "mm/rmap: convert "enum rmap_level" to "enum pgtable_level""
 -> Added
* "mm/memory: convert print_bad_pte() to print_bad_page_map()"
 -> Consume level so we can keep the level indication through
    pgtable_level_to_str().
 -> Improve locking comments
* "mm/memory: factor out common code from vm_normal_page_*()"
 -> Factor everything out into __vm_normal_page() and let it consume the
    special bit + pfn (and the value+level for error reporting purposes)
 -> Improve function docs
 -> Improve patch description

v1 -> v2:
* "mm/memory: convert print_bad_pte() to print_bad_page_map()"
 -> Don't use pgdp_get(), because it's broken on some arm configs
 -> Extend patch description
 -> Don't use pmd_val(pmdp_get()), because that doesn't work on some
    m68k configs
* Added RBs

RFC -> v1:
* Dropped the highest_memmap_pfn removal stuff and instead added
  "mm/memory: convert print_bad_pte() to print_bad_page_map()"
* Dropped "mm: compare pfns only if the entry is present when inserting
  pfns/pages" for now, will probably clean that up separately.
* Dropped "mm: remove "horrible special case to handle copy-on-write
  behaviour"", and "mm: drop addr parameter from vm_normal_*_pmd()" will
  require more thought
* "mm/huge_memory: support huge zero folio in vmf_insert_folio_pmd()"
 -> Extend patch description.
* "fs/dax: use vmf_insert_folio_pmd() to insert the huge zero folio"
 -> Extend patch description.
* "mm/huge_memory: mark PMD mappings of the huge zero folio special"
 -> Remove comment from vm_normal_page_pmd().
* "mm/memory: factor out common code from vm_normal_page_*()"
 -> Adjust to print_bad_page_map()/highest_memmap_pfn changes.
 -> Add proper kernel doc to all involved functions
* "mm: introduce and use vm_normal_page_pud()"
 -> Adjust to print_bad_page_map() changes.

Cc: Andrew Morton 
Cc: Madhavan Srinivasan 
Cc: Michael Ellerman 
Cc: Nicholas Piggin 
Cc: Christophe Leroy 
Cc: Juergen Gross 
Cc: Stefano Stabellini 
Cc: Oleksandr Tyshchenko 
Cc: Dan Williams 
Cc: Matthew Wilcox 
Cc: Jan Kara 
Cc: Alexander Viro 
Cc: Christian Brauner 
Cc: Lorenzo Stoakes 
Cc: "Liam R. Howlett" 
Cc: Vlastimil Babka 
Cc: Mike Rapoport 
Cc: Suren Baghdasaryan 
Cc: Michal Hocko 
Cc: Zi Yan 
Cc: Baolin Wang 
Cc: Nico Pache 
Cc: Ryan Roberts 
Cc: Dev Jain 
Cc: Barry Song 
Cc: Jann Horn 
Cc: Pedro Falcato 
Cc: Hugh Dickins 
Cc: Oscar Salvador 
Cc: Lance Yang 

David Hildenbrand (11):
  mm/huge_memory: move more common code into insert_pmd()
  mm/huge_memory: move more common code into insert_pud()
  mm/huge_memory: support huge zero folio in vmf_insert_folio_pmd()
  fs/dax: use vmf_insert_folio_pmd() to insert the huge zero folio
  mm/huge_memory: mark PMD mappings of the huge zero folio special
  powerpc/ptdump: rename "struct pgtable_level" to "struct
    ptdump_pglevel"
  mm/rmap: convert "enum rmap_level" to "enum pgtable_level"
  mm/memory: convert print_bad_pte() to print_bad_page_map()
  mm/memory: factor out common code from vm_normal_page_*()
  mm: introduce and use vm_normal_page_pud()
  mm: rename vm_ops->find_special_page() to vm_ops->find_normal_page()

 arch/powerpc/mm/ptdump/8xx.c      |   2 +-
 arch/powerpc/mm/ptdump/book3s64.c |   2 +-
 arch/powerpc/mm/ptdump/ptdump.h   |   4 +-
 arch/powerpc/mm/ptdump/shared.c   |   2 +-
 drivers/xen/Kconfig               |   1 +
 drivers/xen/gntdev.c              |   5 +-
 fs/dax.c                          |  47 +----
 include/linux/mm.h                |  20 +-
 include/linux/pgtable.h           |  27 +++
 include/linux/rmap.h              |  60 +++---
 mm/Kconfig                        |   2 +
 mm/huge_memory.c                  | 122 +++++------
 mm/memory.c                       | 332 +++++++++++++++++++++---------
 mm/pagewalk.c                     |  20 +-
 mm/rmap.c                         |  56 ++---
 tools/testing/vma/vma_internal.h  |  18 +-
 16 files changed, 421 insertions(+), 299 deletions(-)


base-commit: 53c448023185717d0ed56b5546dc2be405da92ff
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
	nvdimm@lists.linux.dev,
	linuxppc-dev@lists.ozlabs.org,
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	Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
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	Pedro Falcato ,
	Hugh Dickins ,
	Oscar Salvador ,
	Lance Yang ,
	Alistair Popple ,
	Wei Yang 
Subject: [PATCH v3 02/11] mm/huge_memory: move more common code into insert_pud()
Date: Mon, 11 Aug 2025 13:26:22 +0200
Message-ID: <20250811112631.759341-3-david@redhat.com>
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Let's clean it all further up.

No functional change intended.

Reviewed-by: Oscar Salvador 
Reviewed-by: Alistair Popple 
Reviewed-by: Lorenzo Stoakes 
Reviewed-by: Wei Yang 
Signed-off-by: David Hildenbrand 
---
 mm/huge_memory.c | 36 +++++++++++++-----------------------
 1 file changed, 13 insertions(+), 23 deletions(-)

diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index 5314a89d676f1..7933791b75f4d 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -1507,25 +1507,30 @@ static pud_t maybe_pud_mkwrite(pud_t pud, struct vm_area_struct *vma)
 	return pud;
 }
 
-static void insert_pud(struct vm_area_struct *vma, unsigned long addr,
+static vm_fault_t insert_pud(struct vm_area_struct *vma, unsigned long addr,
 		pud_t *pud, struct folio_or_pfn fop, pgprot_t prot, bool write)
 {
 	struct mm_struct *mm = vma->vm_mm;
+	spinlock_t *ptl;
 	pud_t entry;
 
+	if (addr < vma->vm_start || addr >= vma->vm_end)
+		return VM_FAULT_SIGBUS;
+
+	ptl = pud_lock(mm, pud);
 	if (!pud_none(*pud)) {
 		const unsigned long pfn = fop.is_folio ? folio_pfn(fop.folio) :
 					  fop.pfn;
 
 		if (write) {
 			if (WARN_ON_ONCE(pud_pfn(*pud) != pfn))
-				return;
+				goto out_unlock;
 			entry = pud_mkyoung(*pud);
 			entry = maybe_pud_mkwrite(pud_mkdirty(entry), vma);
 			if (pudp_set_access_flags(vma, addr, pud, entry, 1))
 				update_mmu_cache_pud(vma, addr, pud);
 		}
-		return;
+		goto out_unlock;
 	}
 
 	if (fop.is_folio) {
@@ -1544,6 +1549,9 @@ static void insert_pud(struct vm_area_struct *vma, unsigned long addr,
 	}
 	set_pud_at(mm, addr, pud, entry);
 	update_mmu_cache_pud(vma, addr, pud);
+out_unlock:
+	spin_unlock(ptl);
+	return VM_FAULT_NOPAGE;
 }
 
 /**
@@ -1565,7 +1573,6 @@ vm_fault_t vmf_insert_pfn_pud(struct vm_fault *vmf, unsigned long pfn,
 	struct folio_or_pfn fop = {
 		.pfn = pfn,
 	};
-	spinlock_t *ptl;
 
 	/*
 	 * If we had pud_special, we could avoid all these restrictions,
@@ -1577,16 +1584,9 @@ vm_fault_t vmf_insert_pfn_pud(struct vm_fault *vmf, unsigned long pfn,
 						(VM_PFNMAP|VM_MIXEDMAP));
 	BUG_ON((vma->vm_flags & VM_PFNMAP) && is_cow_mapping(vma->vm_flags));
 
-	if (addr < vma->vm_start || addr >= vma->vm_end)
-		return VM_FAULT_SIGBUS;
-
 	pfnmap_setup_cachemode_pfn(pfn, &pgprot);
 
-	ptl = pud_lock(vma->vm_mm, vmf->pud);
-	insert_pud(vma, addr, vmf->pud, fop, pgprot, write);
-	spin_unlock(ptl);
-
-	return VM_FAULT_NOPAGE;
+	return insert_pud(vma, addr, vmf->pud, fop, pgprot, write);
 }
 EXPORT_SYMBOL_GPL(vmf_insert_pfn_pud);
 
@@ -1603,25 +1603,15 @@ vm_fault_t vmf_insert_folio_pud(struct vm_fault *vmf, struct folio *folio,
 {
 	struct vm_area_struct *vma = vmf->vma;
 	unsigned long addr = vmf->address & PUD_MASK;
-	pud_t *pud = vmf->pud;
-	struct mm_struct *mm = vma->vm_mm;
 	struct folio_or_pfn fop = {
 		.folio = folio,
 		.is_folio = true,
 	};
-	spinlock_t *ptl;
-
-	if (addr < vma->vm_start || addr >= vma->vm_end)
-		return VM_FAULT_SIGBUS;
 
 	if (WARN_ON_ONCE(folio_order(folio) != PUD_ORDER))
 		return VM_FAULT_SIGBUS;
 
-	ptl = pud_lock(mm, pud);
-	insert_pud(vma, addr, vmf->pud, fop, vma->vm_page_prot, write);
-	spin_unlock(ptl);
-
-	return VM_FAULT_NOPAGE;
+	return insert_pud(vma, addr, vmf->pud, fop, vma->vm_page_prot, write);
 }
 EXPORT_SYMBOL_GPL(vmf_insert_folio_pud);
 #endif /* CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD */
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
	nvdimm@lists.linux.dev,
	linuxppc-dev@lists.ozlabs.org,
	David Hildenbrand ,
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	Michael Ellerman ,
	Nicholas Piggin ,
	Christophe Leroy ,
	Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	Dan Williams ,
	Matthew Wilcox ,
	Jan Kara ,
	Alexander Viro ,
	Christian Brauner ,
	Lorenzo Stoakes ,
	"Liam R. Howlett" ,
	Vlastimil Babka ,
	Mike Rapoport ,
	Suren Baghdasaryan ,
	Michal Hocko ,
	Zi Yan ,
	Baolin Wang ,
	Nico Pache ,
	Ryan Roberts ,
	Dev Jain ,
	Barry Song ,
	Jann Horn ,
	Pedro Falcato ,
	Hugh Dickins ,
	Oscar Salvador ,
	Lance Yang ,
	Alistair Popple ,
	Wei Yang 
Subject: [PATCH v3 01/11] mm/huge_memory: move more common code into insert_pmd()
Date: Mon, 11 Aug 2025 13:26:21 +0200
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Let's clean it all further up.

No functional change intended.

Reviewed-by: Oscar Salvador 
Reviewed-by: Alistair Popple 
Reviewed-by: Lorenzo Stoakes 
Reviewed-by: Wei Yang 
Signed-off-by: David Hildenbrand 
---
 mm/huge_memory.c | 72 ++++++++++++++++--------------------------------
 1 file changed, 24 insertions(+), 48 deletions(-)

diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index 2b4ea5a2ce7d2..5314a89d676f1 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -1379,15 +1379,25 @@ struct folio_or_pfn {
 	bool is_folio;
 };
 
-static int insert_pmd(struct vm_area_struct *vma, unsigned long addr,
+static vm_fault_t insert_pmd(struct vm_area_struct *vma, unsigned long addr,
 		pmd_t *pmd, struct folio_or_pfn fop, pgprot_t prot,
-		bool write, pgtable_t pgtable)
+		bool write)
 {
 	struct mm_struct *mm = vma->vm_mm;
+	pgtable_t pgtable = NULL;
+	spinlock_t *ptl;
 	pmd_t entry;
 
-	lockdep_assert_held(pmd_lockptr(mm, pmd));
+	if (addr < vma->vm_start || addr >= vma->vm_end)
+		return VM_FAULT_SIGBUS;
 
+	if (arch_needs_pgtable_deposit()) {
+		pgtable = pte_alloc_one(vma->vm_mm);
+		if (!pgtable)
+			return VM_FAULT_OOM;
+	}
+
+	ptl = pmd_lock(mm, pmd);
 	if (!pmd_none(*pmd)) {
 		const unsigned long pfn = fop.is_folio ? folio_pfn(fop.folio) :
 					  fop.pfn;
@@ -1395,15 +1405,14 @@ static int insert_pmd(struct vm_area_struct *vma, unsigned long addr,
 		if (write) {
 			if (pmd_pfn(*pmd) != pfn) {
 				WARN_ON_ONCE(!is_huge_zero_pmd(*pmd));
-				return -EEXIST;
+				goto out_unlock;
 			}
 			entry = pmd_mkyoung(*pmd);
 			entry = maybe_pmd_mkwrite(pmd_mkdirty(entry), vma);
 			if (pmdp_set_access_flags(vma, addr, pmd, entry, 1))
 				update_mmu_cache_pmd(vma, addr, pmd);
 		}
-
-		return -EEXIST;
+		goto out_unlock;
 	}
 
 	if (fop.is_folio) {
@@ -1424,11 +1433,17 @@ static int insert_pmd(struct vm_area_struct *vma, unsigned long addr,
 	if (pgtable) {
 		pgtable_trans_huge_deposit(mm, pmd, pgtable);
 		mm_inc_nr_ptes(mm);
+		pgtable = NULL;
 	}
 
 	set_pmd_at(mm, addr, pmd, entry);
 	update_mmu_cache_pmd(vma, addr, pmd);
-	return 0;
+
+out_unlock:
+	spin_unlock(ptl);
+	if (pgtable)
+		pte_free(mm, pgtable);
+	return VM_FAULT_NOPAGE;
 }
 
 /**
@@ -1450,9 +1465,6 @@ vm_fault_t vmf_insert_pfn_pmd(struct vm_fault *vmf, unsigned long pfn,
 	struct folio_or_pfn fop = {
 		.pfn = pfn,
 	};
-	pgtable_t pgtable = NULL;
-	spinlock_t *ptl;
-	int error;
 
 	/*
 	 * If we had pmd_special, we could avoid all these restrictions,
@@ -1464,25 +1476,9 @@ vm_fault_t vmf_insert_pfn_pmd(struct vm_fault *vmf, unsigned long pfn,
 						(VM_PFNMAP|VM_MIXEDMAP));
 	BUG_ON((vma->vm_flags & VM_PFNMAP) && is_cow_mapping(vma->vm_flags));
 
-	if (addr < vma->vm_start || addr >= vma->vm_end)
-		return VM_FAULT_SIGBUS;
-
-	if (arch_needs_pgtable_deposit()) {
-		pgtable = pte_alloc_one(vma->vm_mm);
-		if (!pgtable)
-			return VM_FAULT_OOM;
-	}
-
 	pfnmap_setup_cachemode_pfn(pfn, &pgprot);
 
-	ptl = pmd_lock(vma->vm_mm, vmf->pmd);
-	error = insert_pmd(vma, addr, vmf->pmd, fop, pgprot, write,
-			   pgtable);
-	spin_unlock(ptl);
-	if (error && pgtable)
-		pte_free(vma->vm_mm, pgtable);
-
-	return VM_FAULT_NOPAGE;
+	return insert_pmd(vma, addr, vmf->pmd, fop, pgprot, write);
 }
 EXPORT_SYMBOL_GPL(vmf_insert_pfn_pmd);
 
@@ -1491,35 +1487,15 @@ vm_fault_t vmf_insert_folio_pmd(struct vm_fault *vmf, struct folio *folio,
 {
 	struct vm_area_struct *vma = vmf->vma;
 	unsigned long addr = vmf->address & PMD_MASK;
-	struct mm_struct *mm = vma->vm_mm;
 	struct folio_or_pfn fop = {
 		.folio = folio,
 		.is_folio = true,
 	};
-	spinlock_t *ptl;
-	pgtable_t pgtable = NULL;
-	int error;
-
-	if (addr < vma->vm_start || addr >= vma->vm_end)
-		return VM_FAULT_SIGBUS;
 
 	if (WARN_ON_ONCE(folio_order(folio) != PMD_ORDER))
 		return VM_FAULT_SIGBUS;
 
-	if (arch_needs_pgtable_deposit()) {
-		pgtable = pte_alloc_one(vma->vm_mm);
-		if (!pgtable)
-			return VM_FAULT_OOM;
-	}
-
-	ptl = pmd_lock(mm, vmf->pmd);
-	error = insert_pmd(vma, addr, vmf->pmd, fop, vma->vm_page_prot,
-			   write, pgtable);
-	spin_unlock(ptl);
-	if (error && pgtable)
-		pte_free(mm, pgtable);
-
-	return VM_FAULT_NOPAGE;
+	return insert_pmd(vma, addr, vmf->pmd, fop, vma->vm_page_prot, write);
 }
 EXPORT_SYMBOL_GPL(vmf_insert_folio_pmd);
 
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
	nvdimm@lists.linux.dev,
	linuxppc-dev@lists.ozlabs.org,
	David Hildenbrand ,
	Andrew Morton ,
	Madhavan Srinivasan ,
	Michael Ellerman ,
	Nicholas Piggin ,
	Christophe Leroy ,
	Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
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	Christian Brauner ,
	Lorenzo Stoakes ,
	"Liam R. Howlett" ,
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	Michal Hocko ,
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	Baolin Wang ,
	Nico Pache ,
	Ryan Roberts ,
	Dev Jain ,
	Barry Song ,
	Jann Horn ,
	Pedro Falcato ,
	Hugh Dickins ,
	Oscar Salvador ,
	Lance Yang ,
	Wei Yang 
Subject: [PATCH v3 03/11] mm/huge_memory: support huge zero folio in vmf_insert_folio_pmd()
Date: Mon, 11 Aug 2025 13:26:23 +0200
Message-ID: <20250811112631.759341-4-david@redhat.com>
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Just like we do for vmf_insert_page_mkwrite() -> ... ->
insert_page_into_pte_locked() with the shared zeropage, support the
huge zero folio in vmf_insert_folio_pmd().

When (un)mapping the huge zero folio in page tables, we neither
adjust the refcount nor the mapcount, just like for the shared zeropage.

For now, the huge zero folio is not marked as special yet, although
vm_normal_page_pmd() really wants to treat it as special. We'll change
that next.

Reviewed-by: Oscar Salvador 
Reviewed-by: Lorenzo Stoakes 
Reviewed-by: Wei Yang 
Signed-off-by: David Hildenbrand 
---
 mm/huge_memory.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index 7933791b75f4d..ec89e0607424e 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -1418,9 +1418,11 @@ static vm_fault_t insert_pmd(struct vm_area_struct *vma, unsigned long addr,
 	if (fop.is_folio) {
 		entry = folio_mk_pmd(fop.folio, vma->vm_page_prot);
 
-		folio_get(fop.folio);
-		folio_add_file_rmap_pmd(fop.folio, &fop.folio->page, vma);
-		add_mm_counter(mm, mm_counter_file(fop.folio), HPAGE_PMD_NR);
+		if (!is_huge_zero_folio(fop.folio)) {
+			folio_get(fop.folio);
+			folio_add_file_rmap_pmd(fop.folio, &fop.folio->page, vma);
+			add_mm_counter(mm, mm_counter_file(fop.folio), HPAGE_PMD_NR);
+		}
 	} else {
 		entry = pmd_mkhuge(pfn_pmd(fop.pfn, prot));
 		entry = pmd_mkspecial(entry);
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
	nvdimm@lists.linux.dev,
	linuxppc-dev@lists.ozlabs.org,
	David Hildenbrand ,
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	Christophe Leroy ,
	Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	Dan Williams ,
	Matthew Wilcox ,
	Jan Kara ,
	Alexander Viro ,
	Christian Brauner ,
	Lorenzo Stoakes ,
	"Liam R. Howlett" ,
	Vlastimil Babka ,
	Mike Rapoport ,
	Suren Baghdasaryan ,
	Michal Hocko ,
	Zi Yan ,
	Baolin Wang ,
	Nico Pache ,
	Ryan Roberts ,
	Dev Jain ,
	Barry Song ,
	Jann Horn ,
	Pedro Falcato ,
	Hugh Dickins ,
	Oscar Salvador ,
	Lance Yang 
Subject: [PATCH v3 05/11] mm/huge_memory: mark PMD mappings of the huge zero folio special
Date: Mon, 11 Aug 2025 13:26:25 +0200
Message-ID: <20250811112631.759341-6-david@redhat.com>
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The huge zero folio is refcounted (+mapcounted -- is that a word?)
differently than "normal" folios, similarly (but different) to the ordinary
shared zeropage.

For this reason, we special-case these pages in
vm_normal_page*/vm_normal_folio*, and only allow selected callers to
still use them (e.g., GUP can still take a reference on them).

vm_normal_page_pmd() already filters out the huge zero folio, to
indicate it a special (return NULL). However, so far we are not making
use of pmd_special() on architectures that support it
(CONFIG_ARCH_HAS_PTE_SPECIAL), like we would with the ordinary shared
zeropage.

Let's mark PMD mappings of the huge zero folio similarly as special, so we
can avoid the manual check for the huge zero folio with
CONFIG_ARCH_HAS_PTE_SPECIAL next, and only perform the check on
!CONFIG_ARCH_HAS_PTE_SPECIAL.

In copy_huge_pmd(), where we have a manual pmd_special() check to handle
PFNMAP, we have to manually rule out the huge zero folio. That code
needs a serious cleanup, but that's something for another day.

While at it, update the doc regarding the shared zero folios.

No functional change intended: vm_normal_page_pmd() still returns NULL
when it encounters the huge zero folio.

Reviewed-by: Oscar Salvador 
Signed-off-by: David Hildenbrand 
---
 mm/huge_memory.c |  8 ++++++--
 mm/memory.c      | 15 ++++++++++-----
 2 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index ec89e0607424e..58bac83e7fa31 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -1309,6 +1309,7 @@ static void set_huge_zero_folio(pgtable_t pgtable, struct mm_struct *mm,
 {
 	pmd_t entry;
 	entry = folio_mk_pmd(zero_folio, vma->vm_page_prot);
+	entry = pmd_mkspecial(entry);
 	pgtable_trans_huge_deposit(mm, pmd, pgtable);
 	set_pmd_at(mm, haddr, pmd, entry);
 	mm_inc_nr_ptes(mm);
@@ -1418,7 +1419,9 @@ static vm_fault_t insert_pmd(struct vm_area_struct *vma, unsigned long addr,
 	if (fop.is_folio) {
 		entry = folio_mk_pmd(fop.folio, vma->vm_page_prot);
 
-		if (!is_huge_zero_folio(fop.folio)) {
+		if (is_huge_zero_folio(fop.folio)) {
+			entry = pmd_mkspecial(entry);
+		} else {
 			folio_get(fop.folio);
 			folio_add_file_rmap_pmd(fop.folio, &fop.folio->page, vma);
 			add_mm_counter(mm, mm_counter_file(fop.folio), HPAGE_PMD_NR);
@@ -1643,7 +1646,8 @@ int copy_huge_pmd(struct mm_struct *dst_mm, struct mm_struct *src_mm,
 	int ret = -ENOMEM;
 
 	pmd = pmdp_get_lockless(src_pmd);
-	if (unlikely(pmd_present(pmd) && pmd_special(pmd))) {
+	if (unlikely(pmd_present(pmd) && pmd_special(pmd) &&
+		     !is_huge_zero_pmd(pmd))) {
 		dst_ptl = pmd_lock(dst_mm, dst_pmd);
 		src_ptl = pmd_lockptr(src_mm, src_pmd);
 		spin_lock_nested(src_ptl, SINGLE_DEPTH_NESTING);
diff --git a/mm/memory.c b/mm/memory.c
index 0ba4f6b718471..626caedce35e0 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -555,7 +555,14 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
  *
  * "Special" mappings do not wish to be associated with a "struct page" (either
  * it doesn't exist, or it exists but they don't want to touch it). In this
- * case, NULL is returned here. "Normal" mappings do have a struct page.
+ * case, NULL is returned here. "Normal" mappings do have a struct page and
+ * are ordinarily refcounted.
+ *
+ * Page mappings of the shared zero folios are always considered "special", as
+ * they are not ordinarily refcounted: neither the refcount nor the mapcount
+ * of these folios is adjusted when mapping them into user page tables.
+ * Selected page table walkers (such as GUP) can still identify mappings of the
+ * shared zero folios and work with the underlying "struct page".
  *
  * There are 2 broad cases. Firstly, an architecture may define a pte_special()
  * pte bit, in which case this function is trivial. Secondly, an architecture
@@ -585,9 +592,8 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
  *
  * VM_MIXEDMAP mappings can likewise contain memory with or without "struct
  * page" backing, however the difference is that _all_ pages with a struct
- * page (that is, those where pfn_valid is true) are refcounted and considered
- * normal pages by the VM. The only exception are zeropages, which are
- * *never* refcounted.
+ * page (that is, those where pfn_valid is true, except the shared zero
+ * folios) are refcounted and considered normal pages by the VM.
  *
  * The disadvantage is that pages are refcounted (which can be slower and
  * simply not an option for some PFNMAP users). The advantage is that we
@@ -667,7 +673,6 @@ struct page *vm_normal_page_pmd(struct vm_area_struct *vma, unsigned long addr,
 {
 	unsigned long pfn = pmd_pfn(pmd);
 
-	/* Currently it's only used for huge pfnmaps */
 	if (unlikely(pmd_special(pmd)))
 		return NULL;
 
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
	nvdimm@lists.linux.dev,
	linuxppc-dev@lists.ozlabs.org,
	David Hildenbrand ,
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	Alistair Popple 
Subject: [PATCH v3 04/11] fs/dax: use vmf_insert_folio_pmd() to insert the huge zero folio
Date: Mon, 11 Aug 2025 13:26:24 +0200
Message-ID: <20250811112631.759341-5-david@redhat.com>
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Let's convert to vmf_insert_folio_pmd().

There is a theoretical change in behavior: in the unlikely case there is
already something mapped, we'll now still call trace_dax_pmd_load_hole()
and return VM_FAULT_NOPAGE.

Previously, we would have returned VM_FAULT_FALLBACK, and the caller
would have zapped the PMD to try a PTE fault.

However, that behavior was different to other PTE+PMD faults, when there
would already be something mapped, and it's not even clear if it could
be triggered.

Assuming the huge zero folio is already mapped, all good, no need to
fallback to PTEs.

Assuming there is already a leaf page table ... the behavior would be
just like when trying to insert a PMD mapping a folio through
dax_fault_iter()->vmf_insert_folio_pmd().

Assuming there is already something else mapped as PMD? It sounds like
a BUG, and the behavior would be just like when trying to insert a PMD
mapping a folio through dax_fault_iter()->vmf_insert_folio_pmd().

So, it sounds reasonable to not handle huge zero folios differently
to inserting PMDs mapping folios when there already is something mapped.

Reviewed-by: Alistair Popple 
Reviewed-by: Lorenzo Stoakes 
Signed-off-by: David Hildenbrand 
---
 fs/dax.c | 47 ++++++++++-------------------------------------
 1 file changed, 10 insertions(+), 37 deletions(-)

diff --git a/fs/dax.c b/fs/dax.c
index 4229513806bea..ae90706674a3f 100644
--- a/fs/dax.c
+++ b/fs/dax.c
@@ -1375,51 +1375,24 @@ static vm_fault_t dax_pmd_load_hole(struct xa_state *xas, struct vm_fault *vmf,
 		const struct iomap_iter *iter, void **entry)
 {
 	struct address_space *mapping = vmf->vma->vm_file->f_mapping;
-	unsigned long pmd_addr = vmf->address & PMD_MASK;
-	struct vm_area_struct *vma = vmf->vma;
 	struct inode *inode = mapping->host;
-	pgtable_t pgtable = NULL;
 	struct folio *zero_folio;
-	spinlock_t *ptl;
-	pmd_t pmd_entry;
-	unsigned long pfn;
+	vm_fault_t ret;
 
 	zero_folio = mm_get_huge_zero_folio(vmf->vma->vm_mm);
 
-	if (unlikely(!zero_folio))
-		goto fallback;
-
-	pfn = page_to_pfn(&zero_folio->page);
-	*entry = dax_insert_entry(xas, vmf, iter, *entry, pfn,
-				  DAX_PMD | DAX_ZERO_PAGE);
-
-	if (arch_needs_pgtable_deposit()) {
-		pgtable = pte_alloc_one(vma->vm_mm);
-		if (!pgtable)
-			return VM_FAULT_OOM;
-	}
-
-	ptl = pmd_lock(vmf->vma->vm_mm, vmf->pmd);
-	if (!pmd_none(*(vmf->pmd))) {
-		spin_unlock(ptl);
-		goto fallback;
+	if (unlikely(!zero_folio)) {
+		trace_dax_pmd_load_hole_fallback(inode, vmf, zero_folio, *entry);
+		return VM_FAULT_FALLBACK;
 	}
 
-	if (pgtable) {
-		pgtable_trans_huge_deposit(vma->vm_mm, vmf->pmd, pgtable);
-		mm_inc_nr_ptes(vma->vm_mm);
-	}
-	pmd_entry = folio_mk_pmd(zero_folio, vmf->vma->vm_page_prot);
-	set_pmd_at(vmf->vma->vm_mm, pmd_addr, vmf->pmd, pmd_entry);
-	spin_unlock(ptl);
-	trace_dax_pmd_load_hole(inode, vmf, zero_folio, *entry);
-	return VM_FAULT_NOPAGE;
+	*entry = dax_insert_entry(xas, vmf, iter, *entry, folio_pfn(zero_folio),
+				  DAX_PMD | DAX_ZERO_PAGE);
 
-fallback:
-	if (pgtable)
-		pte_free(vma->vm_mm, pgtable);
-	trace_dax_pmd_load_hole_fallback(inode, vmf, zero_folio, *entry);
-	return VM_FAULT_FALLBACK;
+	ret = vmf_insert_folio_pmd(vmf, zero_folio, false);
+	if (ret == VM_FAULT_NOPAGE)
+		trace_dax_pmd_load_hole(inode, vmf, zero_folio, *entry);
+	return ret;
 }
 #else
 static vm_fault_t dax_pmd_load_hole(struct xa_state *xas, struct vm_fault *vmf,
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
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	Alexander Viro ,
	Christian Brauner ,
	Lorenzo Stoakes ,
	"Liam R. Howlett" ,
	Vlastimil Babka ,
	Mike Rapoport ,
	Suren Baghdasaryan ,
	Michal Hocko ,
	Zi Yan ,
	Baolin Wang ,
	Nico Pache ,
	Ryan Roberts ,
	Dev Jain ,
	Barry Song ,
	Jann Horn ,
	Pedro Falcato ,
	Hugh Dickins ,
	Oscar Salvador ,
	Lance Yang 
Subject: [PATCH v3 06/11] powerpc/ptdump: rename "struct pgtable_level" to "struct ptdump_pglevel"
Date: Mon, 11 Aug 2025 13:26:26 +0200
Message-ID: <20250811112631.759341-7-david@redhat.com>
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We want to make use of "pgtable_level" for an enum in core-mm. Other
architectures seem to call "struct pgtable_level" either:
* "struct pg_level" when not exposed in a header (riscv, arm)
* "struct ptdump_pg_level" when expose in a header (arm64)

So let's follow what arm64 does.

Signed-off-by: David Hildenbrand 
---
 arch/powerpc/mm/ptdump/8xx.c      | 2 +-
 arch/powerpc/mm/ptdump/book3s64.c | 2 +-
 arch/powerpc/mm/ptdump/ptdump.h   | 4 ++--
 arch/powerpc/mm/ptdump/shared.c   | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/mm/ptdump/8xx.c b/arch/powerpc/mm/ptdump/8xx.c
index b5c79b11ea3c2..4ca9cf7a90c9e 100644
--- a/arch/powerpc/mm/ptdump/8xx.c
+++ b/arch/powerpc/mm/ptdump/8xx.c
@@ -69,7 +69,7 @@ static const struct flag_info flag_array[] = {
 	}
 };
 
-struct pgtable_level pg_level[5] = {
+struct ptdump_pg_level pg_level[5] = {
 	{ /* pgd */
 		.flag	= flag_array,
 		.num	= ARRAY_SIZE(flag_array),
diff --git a/arch/powerpc/mm/ptdump/book3s64.c b/arch/powerpc/mm/ptdump/book3s64.c
index 5ad92d9dc5d10..6b2da9241d4c4 100644
--- a/arch/powerpc/mm/ptdump/book3s64.c
+++ b/arch/powerpc/mm/ptdump/book3s64.c
@@ -102,7 +102,7 @@ static const struct flag_info flag_array[] = {
 	}
 };
 
-struct pgtable_level pg_level[5] = {
+struct ptdump_pg_level pg_level[5] = {
 	{ /* pgd */
 		.flag	= flag_array,
 		.num	= ARRAY_SIZE(flag_array),
diff --git a/arch/powerpc/mm/ptdump/ptdump.h b/arch/powerpc/mm/ptdump/ptdump.h
index 154efae96ae09..4232aa4b57eae 100644
--- a/arch/powerpc/mm/ptdump/ptdump.h
+++ b/arch/powerpc/mm/ptdump/ptdump.h
@@ -11,12 +11,12 @@ struct flag_info {
 	int		shift;
 };
 
-struct pgtable_level {
+struct ptdump_pg_level {
 	const struct flag_info *flag;
 	size_t num;
 	u64 mask;
 };
 
-extern struct pgtable_level pg_level[5];
+extern struct ptdump_pg_level pg_level[5];
 
 void pt_dump_size(struct seq_file *m, unsigned long delta);
diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
index 39c30c62b7ea7..58998960eb9a4 100644
--- a/arch/powerpc/mm/ptdump/shared.c
+++ b/arch/powerpc/mm/ptdump/shared.c
@@ -67,7 +67,7 @@ static const struct flag_info flag_array[] = {
 	}
 };
 
-struct pgtable_level pg_level[5] = {
+struct ptdump_pg_level pg_level[5] = {
 	{ /* pgd */
 		.flag	= flag_array,
 		.num	= ARRAY_SIZE(flag_array),
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
	nvdimm@lists.linux.dev,
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	"Liam R. Howlett" ,
	Vlastimil Babka ,
	Mike Rapoport ,
	Suren Baghdasaryan ,
	Michal Hocko ,
	Zi Yan ,
	Baolin Wang ,
	Nico Pache ,
	Ryan Roberts ,
	Dev Jain ,
	Barry Song ,
	Jann Horn ,
	Pedro Falcato ,
	Hugh Dickins ,
	Oscar Salvador ,
	Lance Yang 
Subject: [PATCH v3 07/11] mm/rmap: convert "enum rmap_level" to "enum pgtable_level"
Date: Mon, 11 Aug 2025 13:26:27 +0200
Message-ID: <20250811112631.759341-8-david@redhat.com>
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Let's factor it out, and convert all checks for unsupported levels to
BUILD_BUG(). The code is written in a way such that force-inlining will
optimize out the levels.

Signed-off-by: David Hildenbrand 
---
 include/linux/pgtable.h |  8 ++++++
 include/linux/rmap.h    | 60 +++++++++++++++++++----------------------
 mm/rmap.c               | 56 +++++++++++++++++++++-----------------
 3 files changed, 66 insertions(+), 58 deletions(-)

diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
index 4c035637eeb77..bff5c4241bf2e 100644
--- a/include/linux/pgtable.h
+++ b/include/linux/pgtable.h
@@ -1958,6 +1958,14 @@ static inline bool arch_has_pfn_modify_check(void)
 /* Page-Table Modification Mask */
 typedef unsigned int pgtbl_mod_mask;
 
+enum pgtable_level {
+	PGTABLE_LEVEL_PTE = 0,
+	PGTABLE_LEVEL_PMD,
+	PGTABLE_LEVEL_PUD,
+	PGTABLE_LEVEL_P4D,
+	PGTABLE_LEVEL_PGD,
+};
+
 #endif /* !__ASSEMBLY__ */
 
 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT)
diff --git a/include/linux/rmap.h b/include/linux/rmap.h
index 6cd020eea37a2..9d40d127bdb78 100644
--- a/include/linux/rmap.h
+++ b/include/linux/rmap.h
@@ -394,18 +394,8 @@ typedef int __bitwise rmap_t;
 /* The anonymous (sub)page is exclusive to a single process. */
 #define RMAP_EXCLUSIVE		((__force rmap_t)BIT(0))
 
-/*
- * Internally, we're using an enum to specify the granularity. We make the
- * compiler emit specialized code for each granularity.
- */
-enum rmap_level {
-	RMAP_LEVEL_PTE = 0,
-	RMAP_LEVEL_PMD,
-	RMAP_LEVEL_PUD,
-};
-
 static inline void __folio_rmap_sanity_checks(const struct folio *folio,
-		const struct page *page, int nr_pages, enum rmap_level level)
+		const struct page *page, int nr_pages, enum pgtable_level level)
 {
 	/* hugetlb folios are handled separately. */
 	VM_WARN_ON_FOLIO(folio_test_hugetlb(folio), folio);
@@ -427,18 +417,18 @@ static inline void __folio_rmap_sanity_checks(const struct folio *folio,
 	VM_WARN_ON_FOLIO(page_folio(page + nr_pages - 1) != folio, folio);
 
 	switch (level) {
-	case RMAP_LEVEL_PTE:
+	case PGTABLE_LEVEL_PTE:
 		break;
-	case RMAP_LEVEL_PMD:
+	case PGTABLE_LEVEL_PMD:
 		/*
 		 * We don't support folios larger than a single PMD yet. So
-		 * when RMAP_LEVEL_PMD is set, we assume that we are creating
+		 * when PGTABLE_LEVEL_PMD is set, we assume that we are creating
 		 * a single "entire" mapping of the folio.
 		 */
 		VM_WARN_ON_FOLIO(folio_nr_pages(folio) != HPAGE_PMD_NR, folio);
 		VM_WARN_ON_FOLIO(nr_pages != HPAGE_PMD_NR, folio);
 		break;
-	case RMAP_LEVEL_PUD:
+	case PGTABLE_LEVEL_PUD:
 		/*
 		 * Assume that we are creating a single "entire" mapping of the
 		 * folio.
@@ -447,7 +437,7 @@ static inline void __folio_rmap_sanity_checks(const struct folio *folio,
 		VM_WARN_ON_FOLIO(nr_pages != HPAGE_PUD_NR, folio);
 		break;
 	default:
-		VM_WARN_ON_ONCE(true);
+		BUILD_BUG();
 	}
 
 	/*
@@ -567,14 +557,14 @@ static inline void hugetlb_remove_rmap(struct folio *folio)
 
 static __always_inline void __folio_dup_file_rmap(struct folio *folio,
 		struct page *page, int nr_pages, struct vm_area_struct *dst_vma,
-		enum rmap_level level)
+		enum pgtable_level level)
 {
 	const int orig_nr_pages = nr_pages;
 
 	__folio_rmap_sanity_checks(folio, page, nr_pages, level);
 
 	switch (level) {
-	case RMAP_LEVEL_PTE:
+	case PGTABLE_LEVEL_PTE:
 		if (!folio_test_large(folio)) {
 			atomic_inc(&folio->_mapcount);
 			break;
@@ -587,11 +577,13 @@ static __always_inline void __folio_dup_file_rmap(struct folio *folio,
 		}
 		folio_add_large_mapcount(folio, orig_nr_pages, dst_vma);
 		break;
-	case RMAP_LEVEL_PMD:
-	case RMAP_LEVEL_PUD:
+	case PGTABLE_LEVEL_PMD:
+	case PGTABLE_LEVEL_PUD:
 		atomic_inc(&folio->_entire_mapcount);
 		folio_inc_large_mapcount(folio, dst_vma);
 		break;
+	default:
+		BUILD_BUG();
 	}
 }
 
@@ -609,13 +601,13 @@ static __always_inline void __folio_dup_file_rmap(struct folio *folio,
 static inline void folio_dup_file_rmap_ptes(struct folio *folio,
 		struct page *page, int nr_pages, struct vm_area_struct *dst_vma)
 {
-	__folio_dup_file_rmap(folio, page, nr_pages, dst_vma, RMAP_LEVEL_PTE);
+	__folio_dup_file_rmap(folio, page, nr_pages, dst_vma, PGTABLE_LEVEL_PTE);
 }
 
 static __always_inline void folio_dup_file_rmap_pte(struct folio *folio,
 		struct page *page, struct vm_area_struct *dst_vma)
 {
-	__folio_dup_file_rmap(folio, page, 1, dst_vma, RMAP_LEVEL_PTE);
+	__folio_dup_file_rmap(folio, page, 1, dst_vma, PGTABLE_LEVEL_PTE);
 }
 
 /**
@@ -632,7 +624,7 @@ static inline void folio_dup_file_rmap_pmd(struct folio *folio,
 		struct page *page, struct vm_area_struct *dst_vma)
 {
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-	__folio_dup_file_rmap(folio, page, HPAGE_PMD_NR, dst_vma, RMAP_LEVEL_PTE);
+	__folio_dup_file_rmap(folio, page, HPAGE_PMD_NR, dst_vma, PGTABLE_LEVEL_PTE);
 #else
 	WARN_ON_ONCE(true);
 #endif
@@ -640,7 +632,7 @@ static inline void folio_dup_file_rmap_pmd(struct folio *folio,
 
 static __always_inline int __folio_try_dup_anon_rmap(struct folio *folio,
 		struct page *page, int nr_pages, struct vm_area_struct *dst_vma,
-		struct vm_area_struct *src_vma, enum rmap_level level)
+		struct vm_area_struct *src_vma, enum pgtable_level level)
 {
 	const int orig_nr_pages = nr_pages;
 	bool maybe_pinned;
@@ -665,7 +657,7 @@ static __always_inline int __folio_try_dup_anon_rmap(struct folio *folio,
 	 * copying if the folio maybe pinned.
 	 */
 	switch (level) {
-	case RMAP_LEVEL_PTE:
+	case PGTABLE_LEVEL_PTE:
 		if (unlikely(maybe_pinned)) {
 			for (i = 0; i < nr_pages; i++)
 				if (PageAnonExclusive(page + i))
@@ -687,8 +679,8 @@ static __always_inline int __folio_try_dup_anon_rmap(struct folio *folio,
 		} while (page++, --nr_pages > 0);
 		folio_add_large_mapcount(folio, orig_nr_pages, dst_vma);
 		break;
-	case RMAP_LEVEL_PMD:
-	case RMAP_LEVEL_PUD:
+	case PGTABLE_LEVEL_PMD:
+	case PGTABLE_LEVEL_PUD:
 		if (PageAnonExclusive(page)) {
 			if (unlikely(maybe_pinned))
 				return -EBUSY;
@@ -697,6 +689,8 @@ static __always_inline int __folio_try_dup_anon_rmap(struct folio *folio,
 		atomic_inc(&folio->_entire_mapcount);
 		folio_inc_large_mapcount(folio, dst_vma);
 		break;
+	default:
+		BUILD_BUG();
 	}
 	return 0;
 }
@@ -730,7 +724,7 @@ static inline int folio_try_dup_anon_rmap_ptes(struct folio *folio,
 		struct vm_area_struct *src_vma)
 {
 	return __folio_try_dup_anon_rmap(folio, page, nr_pages, dst_vma,
-					 src_vma, RMAP_LEVEL_PTE);
+					 src_vma, PGTABLE_LEVEL_PTE);
 }
 
 static __always_inline int folio_try_dup_anon_rmap_pte(struct folio *folio,
@@ -738,7 +732,7 @@ static __always_inline int folio_try_dup_anon_rmap_pte(struct folio *folio,
 		struct vm_area_struct *src_vma)
 {
 	return __folio_try_dup_anon_rmap(folio, page, 1, dst_vma, src_vma,
-					 RMAP_LEVEL_PTE);
+					 PGTABLE_LEVEL_PTE);
 }
 
 /**
@@ -770,7 +764,7 @@ static inline int folio_try_dup_anon_rmap_pmd(struct folio *folio,
 {
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 	return __folio_try_dup_anon_rmap(folio, page, HPAGE_PMD_NR, dst_vma,
-					 src_vma, RMAP_LEVEL_PMD);
+					 src_vma, PGTABLE_LEVEL_PMD);
 #else
 	WARN_ON_ONCE(true);
 	return -EBUSY;
@@ -778,7 +772,7 @@ static inline int folio_try_dup_anon_rmap_pmd(struct folio *folio,
 }
 
 static __always_inline int __folio_try_share_anon_rmap(struct folio *folio,
-		struct page *page, int nr_pages, enum rmap_level level)
+		struct page *page, int nr_pages, enum pgtable_level level)
 {
 	VM_WARN_ON_FOLIO(!folio_test_anon(folio), folio);
 	VM_WARN_ON_FOLIO(!PageAnonExclusive(page), folio);
@@ -873,7 +867,7 @@ static __always_inline int __folio_try_share_anon_rmap(struct folio *folio,
 static inline int folio_try_share_anon_rmap_pte(struct folio *folio,
 		struct page *page)
 {
-	return __folio_try_share_anon_rmap(folio, page, 1, RMAP_LEVEL_PTE);
+	return __folio_try_share_anon_rmap(folio, page, 1, PGTABLE_LEVEL_PTE);
 }
 
 /**
@@ -904,7 +898,7 @@ static inline int folio_try_share_anon_rmap_pmd(struct folio *folio,
 {
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 	return __folio_try_share_anon_rmap(folio, page, HPAGE_PMD_NR,
-					   RMAP_LEVEL_PMD);
+					   PGTABLE_LEVEL_PMD);
 #else
 	WARN_ON_ONCE(true);
 	return -EBUSY;
diff --git a/mm/rmap.c b/mm/rmap.c
index 84a8d8b02ef77..0e9c4041f8687 100644
--- a/mm/rmap.c
+++ b/mm/rmap.c
@@ -1265,7 +1265,7 @@ static void __folio_mod_stat(struct folio *folio, int nr, int nr_pmdmapped)
 
 static __always_inline void __folio_add_rmap(struct folio *folio,
 		struct page *page, int nr_pages, struct vm_area_struct *vma,
-		enum rmap_level level)
+		enum pgtable_level level)
 {
 	atomic_t *mapped = &folio->_nr_pages_mapped;
 	const int orig_nr_pages = nr_pages;
@@ -1274,7 +1274,7 @@ static __always_inline void __folio_add_rmap(struct folio *folio,
 	__folio_rmap_sanity_checks(folio, page, nr_pages, level);
 
 	switch (level) {
-	case RMAP_LEVEL_PTE:
+	case PGTABLE_LEVEL_PTE:
 		if (!folio_test_large(folio)) {
 			nr = atomic_inc_and_test(&folio->_mapcount);
 			break;
@@ -1300,11 +1300,11 @@ static __always_inline void __folio_add_rmap(struct folio *folio,
 
 		folio_add_large_mapcount(folio, orig_nr_pages, vma);
 		break;
-	case RMAP_LEVEL_PMD:
-	case RMAP_LEVEL_PUD:
+	case PGTABLE_LEVEL_PMD:
+	case PGTABLE_LEVEL_PUD:
 		first = atomic_inc_and_test(&folio->_entire_mapcount);
 		if (IS_ENABLED(CONFIG_NO_PAGE_MAPCOUNT)) {
-			if (level == RMAP_LEVEL_PMD && first)
+			if (level == PGTABLE_LEVEL_PMD && first)
 				nr_pmdmapped = folio_large_nr_pages(folio);
 			nr = folio_inc_return_large_mapcount(folio, vma);
 			if (nr == 1)
@@ -1323,7 +1323,7 @@ static __always_inline void __folio_add_rmap(struct folio *folio,
 				 * We only track PMD mappings of PMD-sized
 				 * folios separately.
 				 */
-				if (level == RMAP_LEVEL_PMD)
+				if (level == PGTABLE_LEVEL_PMD)
 					nr_pmdmapped = nr_pages;
 				nr = nr_pages - (nr & FOLIO_PAGES_MAPPED);
 				/* Raced ahead of a remove and another add? */
@@ -1336,6 +1336,8 @@ static __always_inline void __folio_add_rmap(struct folio *folio,
 		}
 		folio_inc_large_mapcount(folio, vma);
 		break;
+	default:
+		BUILD_BUG();
 	}
 	__folio_mod_stat(folio, nr, nr_pmdmapped);
 }
@@ -1427,7 +1429,7 @@ static void __page_check_anon_rmap(const struct folio *folio,
 
 static __always_inline void __folio_add_anon_rmap(struct folio *folio,
 		struct page *page, int nr_pages, struct vm_area_struct *vma,
-		unsigned long address, rmap_t flags, enum rmap_level level)
+		unsigned long address, rmap_t flags, enum pgtable_level level)
 {
 	int i;
 
@@ -1440,20 +1442,22 @@ static __always_inline void __folio_add_anon_rmap(struct folio *folio,
 
 	if (flags & RMAP_EXCLUSIVE) {
 		switch (level) {
-		case RMAP_LEVEL_PTE:
+		case PGTABLE_LEVEL_PTE:
 			for (i = 0; i < nr_pages; i++)
 				SetPageAnonExclusive(page + i);
 			break;
-		case RMAP_LEVEL_PMD:
+		case PGTABLE_LEVEL_PMD:
 			SetPageAnonExclusive(page);
 			break;
-		case RMAP_LEVEL_PUD:
+		case PGTABLE_LEVEL_PUD:
 			/*
 			 * Keep the compiler happy, we don't support anonymous
 			 * PUD mappings.
 			 */
 			WARN_ON_ONCE(1);
 			break;
+		default:
+			BUILD_BUG();
 		}
 	}
 
@@ -1507,7 +1511,7 @@ void folio_add_anon_rmap_ptes(struct folio *folio, struct page *page,
 		rmap_t flags)
 {
 	__folio_add_anon_rmap(folio, page, nr_pages, vma, address, flags,
-			      RMAP_LEVEL_PTE);
+			      PGTABLE_LEVEL_PTE);
 }
 
 /**
@@ -1528,7 +1532,7 @@ void folio_add_anon_rmap_pmd(struct folio *folio, struct page *page,
 {
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 	__folio_add_anon_rmap(folio, page, HPAGE_PMD_NR, vma, address, flags,
-			      RMAP_LEVEL_PMD);
+			      PGTABLE_LEVEL_PMD);
 #else
 	WARN_ON_ONCE(true);
 #endif
@@ -1609,7 +1613,7 @@ void folio_add_new_anon_rmap(struct folio *folio, struct vm_area_struct *vma,
 
 static __always_inline void __folio_add_file_rmap(struct folio *folio,
 		struct page *page, int nr_pages, struct vm_area_struct *vma,
-		enum rmap_level level)
+		enum pgtable_level level)
 {
 	VM_WARN_ON_FOLIO(folio_test_anon(folio), folio);
 
@@ -1634,7 +1638,7 @@ static __always_inline void __folio_add_file_rmap(struct folio *folio,
 void folio_add_file_rmap_ptes(struct folio *folio, struct page *page,
 		int nr_pages, struct vm_area_struct *vma)
 {
-	__folio_add_file_rmap(folio, page, nr_pages, vma, RMAP_LEVEL_PTE);
+	__folio_add_file_rmap(folio, page, nr_pages, vma, PGTABLE_LEVEL_PTE);
 }
 
 /**
@@ -1651,7 +1655,7 @@ void folio_add_file_rmap_pmd(struct folio *folio, struct page *page,
 		struct vm_area_struct *vma)
 {
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-	__folio_add_file_rmap(folio, page, HPAGE_PMD_NR, vma, RMAP_LEVEL_PMD);
+	__folio_add_file_rmap(folio, page, HPAGE_PMD_NR, vma, PGTABLE_LEVEL_PMD);
 #else
 	WARN_ON_ONCE(true);
 #endif
@@ -1672,7 +1676,7 @@ void folio_add_file_rmap_pud(struct folio *folio, struct page *page,
 {
 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
 	defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
-	__folio_add_file_rmap(folio, page, HPAGE_PUD_NR, vma, RMAP_LEVEL_PUD);
+	__folio_add_file_rmap(folio, page, HPAGE_PUD_NR, vma, PGTABLE_LEVEL_PUD);
 #else
 	WARN_ON_ONCE(true);
 #endif
@@ -1680,7 +1684,7 @@ void folio_add_file_rmap_pud(struct folio *folio, struct page *page,
 
 static __always_inline void __folio_remove_rmap(struct folio *folio,
 		struct page *page, int nr_pages, struct vm_area_struct *vma,
-		enum rmap_level level)
+		enum pgtable_level level)
 {
 	atomic_t *mapped = &folio->_nr_pages_mapped;
 	int last = 0, nr = 0, nr_pmdmapped = 0;
@@ -1689,7 +1693,7 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
 	__folio_rmap_sanity_checks(folio, page, nr_pages, level);
 
 	switch (level) {
-	case RMAP_LEVEL_PTE:
+	case PGTABLE_LEVEL_PTE:
 		if (!folio_test_large(folio)) {
 			nr = atomic_add_negative(-1, &folio->_mapcount);
 			break;
@@ -1719,11 +1723,11 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
 
 		partially_mapped = nr && atomic_read(mapped);
 		break;
-	case RMAP_LEVEL_PMD:
-	case RMAP_LEVEL_PUD:
+	case PGTABLE_LEVEL_PMD:
+	case PGTABLE_LEVEL_PUD:
 		if (IS_ENABLED(CONFIG_NO_PAGE_MAPCOUNT)) {
 			last = atomic_add_negative(-1, &folio->_entire_mapcount);
-			if (level == RMAP_LEVEL_PMD && last)
+			if (level == PGTABLE_LEVEL_PMD && last)
 				nr_pmdmapped = folio_large_nr_pages(folio);
 			nr = folio_dec_return_large_mapcount(folio, vma);
 			if (!nr) {
@@ -1743,7 +1747,7 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
 			nr = atomic_sub_return_relaxed(ENTIRELY_MAPPED, mapped);
 			if (likely(nr < ENTIRELY_MAPPED)) {
 				nr_pages = folio_large_nr_pages(folio);
-				if (level == RMAP_LEVEL_PMD)
+				if (level == PGTABLE_LEVEL_PMD)
 					nr_pmdmapped = nr_pages;
 				nr = nr_pages - (nr & FOLIO_PAGES_MAPPED);
 				/* Raced ahead of another remove and an add? */
@@ -1757,6 +1761,8 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
 
 		partially_mapped = nr && nr < nr_pmdmapped;
 		break;
+	default:
+		BUILD_BUG();
 	}
 
 	/*
@@ -1796,7 +1802,7 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
 void folio_remove_rmap_ptes(struct folio *folio, struct page *page,
 		int nr_pages, struct vm_area_struct *vma)
 {
-	__folio_remove_rmap(folio, page, nr_pages, vma, RMAP_LEVEL_PTE);
+	__folio_remove_rmap(folio, page, nr_pages, vma, PGTABLE_LEVEL_PTE);
 }
 
 /**
@@ -1813,7 +1819,7 @@ void folio_remove_rmap_pmd(struct folio *folio, struct page *page,
 		struct vm_area_struct *vma)
 {
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
-	__folio_remove_rmap(folio, page, HPAGE_PMD_NR, vma, RMAP_LEVEL_PMD);
+	__folio_remove_rmap(folio, page, HPAGE_PMD_NR, vma, PGTABLE_LEVEL_PMD);
 #else
 	WARN_ON_ONCE(true);
 #endif
@@ -1834,7 +1840,7 @@ void folio_remove_rmap_pud(struct folio *folio, struct page *page,
 {
 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
 	defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
-	__folio_remove_rmap(folio, page, HPAGE_PUD_NR, vma, RMAP_LEVEL_PUD);
+	__folio_remove_rmap(folio, page, HPAGE_PUD_NR, vma, PGTABLE_LEVEL_PUD);
 #else
 	WARN_ON_ONCE(true);
 #endif
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
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	Lance Yang 
Subject: [PATCH v3 08/11] mm/memory: convert print_bad_pte() to print_bad_page_map()
Date: Mon, 11 Aug 2025 13:26:28 +0200
Message-ID: <20250811112631.759341-9-david@redhat.com>
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print_bad_pte() looks like something that should actually be a WARN
or similar, but historically it apparently has proven to be useful to
detect corruption of page tables even on production systems -- report
the issue and keep the system running to make it easier to actually detect
what is going wrong (e.g., multiple such messages might shed a light).

As we want to unify vm_normal_page_*() handling for PTE/PMD/PUD, we'll have
to take care of print_bad_pte() as well.

Let's prepare for using print_bad_pte() also for non-PTEs by adjusting the
implementation and renaming the function to print_bad_page_map().
Provide print_bad_pte() as a simple wrapper.

Document the implicit locking requirements for the page table re-walk.

To make the function a bit more readable, factor out the ratelimit check
into is_bad_page_map_ratelimited() and place the printing of page
table content into __print_bad_page_map_pgtable(). We'll now dump
information from each level in a single line, and just stop the table
walk once we hit something that is not a present page table.

The report will now look something like (dumping pgd to pmd values):

[   77.943408] BUG: Bad page map in process XXX  pte:80000001233f5867
[   77.944077] addr:00007fd84bb1c000 vm_flags:08100071 anon_vma: ...
[   77.945186] pgd:10a89f067 p4d:10a89f067 pud:10e5a2067 pmd:105327067

Not using pgdp_get(), because that does not work properly on some arm
configs where pgd_t is an array. Note that we are dumping all levels
even when levels are folded for simplicity.

Signed-off-by: David Hildenbrand 
---
 include/linux/pgtable.h |  19 ++++++++
 mm/memory.c             | 104 ++++++++++++++++++++++++++++++++--------
 2 files changed, 103 insertions(+), 20 deletions(-)

diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
index bff5c4241bf2e..33c84b38b7ec6 100644
--- a/include/linux/pgtable.h
+++ b/include/linux/pgtable.h
@@ -1966,6 +1966,25 @@ enum pgtable_level {
 	PGTABLE_LEVEL_PGD,
 };
 
+static inline const char *pgtable_level_to_str(enum pgtable_level level)
+{
+	switch (level) {
+	case PGTABLE_LEVEL_PTE:
+		return "pte";
+	case PGTABLE_LEVEL_PMD:
+		return "pmd";
+	case PGTABLE_LEVEL_PUD:
+		return "pud";
+	case PGTABLE_LEVEL_P4D:
+		return "p4d";
+	case PGTABLE_LEVEL_PGD:
+		return "pgd";
+	default:
+		VM_WARN_ON_ONCE(1);
+		return "unknown";
+	}
+}
+
 #endif /* !__ASSEMBLY__ */
 
 #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT)
diff --git a/mm/memory.c b/mm/memory.c
index 626caedce35e0..dc0107354d37b 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -491,22 +491,8 @@ static inline void add_mm_rss_vec(struct mm_struct *mm, int *rss)
 			add_mm_counter(mm, i, rss[i]);
 }
 
-/*
- * This function is called to print an error when a bad pte
- * is found. For example, we might have a PFN-mapped pte in
- * a region that doesn't allow it.
- *
- * The calling function must still handle the error.
- */
-static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
-			  pte_t pte, struct page *page)
+static bool is_bad_page_map_ratelimited(void)
 {
-	pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
-	p4d_t *p4d = p4d_offset(pgd, addr);
-	pud_t *pud = pud_offset(p4d, addr);
-	pmd_t *pmd = pmd_offset(pud, addr);
-	struct address_space *mapping;
-	pgoff_t index;
 	static unsigned long resume;
 	static unsigned long nr_shown;
 	static unsigned long nr_unshown;
@@ -518,7 +504,7 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
 	if (nr_shown == 60) {
 		if (time_before(jiffies, resume)) {
 			nr_unshown++;
-			return;
+			return true;
 		}
 		if (nr_unshown) {
 			pr_alert("BUG: Bad page map: %lu messages suppressed\n",
@@ -529,15 +515,91 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
 	}
 	if (nr_shown++ == 0)
 		resume = jiffies + 60 * HZ;
+	return false;
+}
+
+static void __print_bad_page_map_pgtable(struct mm_struct *mm, unsigned long addr)
+{
+	unsigned long long pgdv, p4dv, pudv, pmdv;
+	p4d_t p4d, *p4dp;
+	pud_t pud, *pudp;
+	pmd_t pmd, *pmdp;
+	pgd_t *pgdp;
+
+	/*
+	 * Although this looks like a fully lockless pgtable walk, it is not:
+	 * see locking requirements for print_bad_page_map().
+	 */
+	pgdp = pgd_offset(mm, addr);
+	pgdv = pgd_val(*pgdp);
+
+	if (!pgd_present(*pgdp) || pgd_leaf(*pgdp)) {
+		pr_alert("pgd:%08llx\n", pgdv);
+		return;
+	}
+
+	p4dp = p4d_offset(pgdp, addr);
+	p4d = p4dp_get(p4dp);
+	p4dv = p4d_val(p4d);
+
+	if (!p4d_present(p4d) || p4d_leaf(p4d)) {
+		pr_alert("pgd:%08llx p4d:%08llx\n", pgdv, p4dv);
+		return;
+	}
+
+	pudp = pud_offset(p4dp, addr);
+	pud = pudp_get(pudp);
+	pudv = pud_val(pud);
+
+	if (!pud_present(pud) || pud_leaf(pud)) {
+		pr_alert("pgd:%08llx p4d:%08llx pud:%08llx\n", pgdv, p4dv, pudv);
+		return;
+	}
+
+	pmdp = pmd_offset(pudp, addr);
+	pmd = pmdp_get(pmdp);
+	pmdv = pmd_val(pmd);
+
+	/*
+	 * Dumping the PTE would be nice, but it's tricky with CONFIG_HIGHPTE,
+	 * because the table should already be mapped by the caller and
+	 * doing another map would be bad. print_bad_page_map() should
+	 * already take care of printing the PTE.
+	 */
+	pr_alert("pgd:%08llx p4d:%08llx pud:%08llx pmd:%08llx\n", pgdv,
+		 p4dv, pudv, pmdv);
+}
+
+/*
+ * This function is called to print an error when a bad page table entry (e.g.,
+ * corrupted page table entry) is found. For example, we might have a
+ * PFN-mapped pte in a region that doesn't allow it.
+ *
+ * The calling function must still handle the error.
+ *
+ * This function must be called during a proper page table walk, as it will
+ * re-walk the page table to dump information: the caller MUST prevent page
+ * table teardown (by holding mmap, vma or rmap lock) and MUST hold the leaf
+ * page table lock.
+ */
+static void print_bad_page_map(struct vm_area_struct *vma,
+		unsigned long addr, unsigned long long entry, struct page *page,
+		enum pgtable_level level)
+{
+	struct address_space *mapping;
+	pgoff_t index;
+
+	if (is_bad_page_map_ratelimited())
+		return;
 
 	mapping = vma->vm_file ? vma->vm_file->f_mapping : NULL;
 	index = linear_page_index(vma, addr);
 
-	pr_alert("BUG: Bad page map in process %s  pte:%08llx pmd:%08llx\n",
-		 current->comm,
-		 (long long)pte_val(pte), (long long)pmd_val(*pmd));
+	pr_alert("BUG: Bad page map in process %s  %s:%08llx", current->comm,
+		 pgtable_level_to_str(level), entry);
+	__print_bad_page_map_pgtable(vma->vm_mm, addr);
 	if (page)
-		dump_page(page, "bad pte");
+		dump_page(page, "bad page map");
 	pr_alert("addr:%px vm_flags:%08lx anon_vma:%px mapping:%px index:%lx\n",
 		 (void *)addr, vma->vm_flags, vma->anon_vma, mapping, index);
 	pr_alert("file:%pD fault:%ps mmap:%ps mmap_prepare: %ps read_folio:%ps\n",
@@ -549,6 +611,8 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
 	dump_stack();
 	add_taint(TAINT_BAD_PAGE, LOCKDEP_NOW_UNRELIABLE);
 }
+#define print_bad_pte(vma, addr, pte, page) \
+	print_bad_page_map(vma, addr, pte_val(pte), page, PGTABLE_LEVEL_PTE)
 
 /*
  * vm_normal_page -- This function gets the "struct page" associated with a pte.
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
	nvdimm@lists.linux.dev,
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	Lance Yang 
Subject: [PATCH v3 09/11] mm/memory: factor out common code from vm_normal_page_*()
Date: Mon, 11 Aug 2025 13:26:29 +0200
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Let's reduce the code duplication and factor out the non-pte/pmd related
magic into __vm_normal_page().

To keep it simpler, check the pfn against both zero folios, which
shouldn't really make a difference.

It's a good question if we can even hit the !CONFIG_ARCH_HAS_PTE_SPECIAL
scenario in the PMD case in practice: but doesn't really matter, as
it's now all unified in vm_normal_page_pfn().

Add kerneldoc for all involved functions.

Note that, as a side product, we now:
* Support the find_special_page special thingy also for PMD
* Don't check for is_huge_zero_pfn() anymore if we have
  CONFIG_ARCH_HAS_PTE_SPECIAL and the PMD is not special. The
  VM_WARN_ON_ONCE would catch any abuse

No functional change intended.

Reviewed-by: Oscar Salvador 
Signed-off-by: David Hildenbrand 
---
 mm/memory.c | 186 ++++++++++++++++++++++++++++++----------------------
 1 file changed, 109 insertions(+), 77 deletions(-)

diff --git a/mm/memory.c b/mm/memory.c
index dc0107354d37b..78af3f243cee7 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -614,8 +614,14 @@ static void print_bad_page_map(struct vm_area_struct *vma,
 #define print_bad_pte(vma, addr, pte, page) \
 	print_bad_page_map(vma, addr, pte_val(pte), page, PGTABLE_LEVEL_PTE)
 
-/*
- * vm_normal_page -- This function gets the "struct page" associated with a pte.
+/**
+ * __vm_normal_page() - Get the "struct page" associated with a page table entry.
+ * @vma: The VMA mapping the page table entry.
+ * @addr: The address where the page table entry is mapped.
+ * @pfn: The PFN stored in the page table entry.
+ * @special: Whether the page table entry is marked "special".
+ * @level: The page table level for error reporting purposes only.
+ * @entry: The page table entry value for error reporting purposes only.
  *
  * "Special" mappings do not wish to be associated with a "struct page" (either
  * it doesn't exist, or it exists but they don't want to touch it). In this
@@ -628,10 +634,10 @@ static void print_bad_page_map(struct vm_area_struct *vma,
  * Selected page table walkers (such as GUP) can still identify mappings of the
  * shared zero folios and work with the underlying "struct page".
  *
- * There are 2 broad cases. Firstly, an architecture may define a pte_special()
- * pte bit, in which case this function is trivial. Secondly, an architecture
- * may not have a spare pte bit, which requires a more complicated scheme,
- * described below.
+ * There are 2 broad cases. Firstly, an architecture may define a "special"
+ * page table entry bit, such as pte_special(), in which case this function is
+ * trivial. Secondly, an architecture may not have a spare page table
+ * entry bit, which requires a more complicated scheme, described below.
  *
  * A raw VM_PFNMAP mapping (ie. one that is not COWed) is always considered a
  * special mapping (even if there are underlying and valid "struct pages").
@@ -664,63 +670,94 @@ static void print_bad_page_map(struct vm_area_struct *vma,
  * don't have to follow the strict linearity rule of PFNMAP mappings in
  * order to support COWable mappings.
  *
+ * Return: Returns the "struct page" if this is a "normal" mapping. Returns
+ *	   NULL if this is a "special" mapping.
  */
-struct page *vm_normal_page(struct vm_area_struct *vma, unsigned long addr,
-			    pte_t pte)
+static inline struct page *__vm_normal_page(struct vm_area_struct *vma,
+		unsigned long addr, unsigned long pfn, bool special,
+		unsigned long long entry, enum pgtable_level level)
 {
-	unsigned long pfn = pte_pfn(pte);
-
 	if (IS_ENABLED(CONFIG_ARCH_HAS_PTE_SPECIAL)) {
-		if (likely(!pte_special(pte)))
-			goto check_pfn;
-		if (vma->vm_ops && vma->vm_ops->find_special_page)
-			return vma->vm_ops->find_special_page(vma, addr);
-		if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
-			return NULL;
-		if (is_zero_pfn(pfn))
-			return NULL;
-
-		print_bad_pte(vma, addr, pte, NULL);
-		return NULL;
-	}
-
-	/* !CONFIG_ARCH_HAS_PTE_SPECIAL case follows: */
-
-	if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
-		if (vma->vm_flags & VM_MIXEDMAP) {
-			if (!pfn_valid(pfn))
+		if (unlikely(special)) {
+			if (vma->vm_ops && vma->vm_ops->find_special_page)
+				return vma->vm_ops->find_special_page(vma, addr);
+			if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
 				return NULL;
-			if (is_zero_pfn(pfn))
-				return NULL;
-			goto out;
-		} else {
-			unsigned long off;
-			off = (addr - vma->vm_start) >> PAGE_SHIFT;
-			if (pfn == vma->vm_pgoff + off)
-				return NULL;
-			if (!is_cow_mapping(vma->vm_flags))
+			if (is_zero_pfn(pfn) || is_huge_zero_pfn(pfn))
 				return NULL;
+
+			print_bad_page_map(vma, addr, entry, NULL, level);
+			return NULL;
 		}
-	}
+		/*
+		 * With CONFIG_ARCH_HAS_PTE_SPECIAL, any special page table
+		 * mappings (incl. shared zero folios) are marked accordingly.
+		 */
+	} else {
+		if (unlikely(vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))) {
+			if (vma->vm_flags & VM_MIXEDMAP) {
+				/* If it has a "struct page", it's "normal". */
+				if (!pfn_valid(pfn))
+					return NULL;
+			} else {
+				unsigned long off = (addr - vma->vm_start) >> PAGE_SHIFT;
 
-	if (is_zero_pfn(pfn))
-		return NULL;
+				/* Only CoW'ed anon folios are "normal". */
+				if (pfn == vma->vm_pgoff + off)
+					return NULL;
+				if (!is_cow_mapping(vma->vm_flags))
+					return NULL;
+			}
+		}
+
+		if (is_zero_pfn(pfn) || is_huge_zero_pfn(pfn))
+			return NULL;
+	}
 
-check_pfn:
 	if (unlikely(pfn > highest_memmap_pfn)) {
-		print_bad_pte(vma, addr, pte, NULL);
+		/* Corrupted page table entry. */
+		print_bad_page_map(vma, addr, entry, NULL, level);
 		return NULL;
 	}
-
 	/*
 	 * NOTE! We still have PageReserved() pages in the page tables.
-	 * eg. VDSO mappings can cause them to exist.
+	 * For example, VDSO mappings can cause them to exist.
 	 */
-out:
-	VM_WARN_ON_ONCE(is_zero_pfn(pfn));
+	VM_WARN_ON_ONCE(is_zero_pfn(pfn) || is_huge_zero_pfn(pfn));
 	return pfn_to_page(pfn);
 }
 
+/**
+ * vm_normal_page() - Get the "struct page" associated with a PTE
+ * @vma: The VMA mapping the @pte.
+ * @addr: The address where the @pte is mapped.
+ * @pte: The PTE.
+ *
+ * Get the "struct page" associated with a PTE. See __vm_normal_page()
+ * for details on "normal" and "special" mappings.
+ *
+ * Return: Returns the "struct page" if this is a "normal" mapping. Returns
+ *	   NULL if this is a "special" mapping.
+ */
+struct page *vm_normal_page(struct vm_area_struct *vma, unsigned long addr,
+			    pte_t pte)
+{
+	return __vm_normal_page(vma, addr, pte_pfn(pte), pte_special(pte),
+				pte_val(pte), PGTABLE_LEVEL_PTE);
+}
+
+/**
+ * vm_normal_folio() - Get the "struct folio" associated with a PTE
+ * @vma: The VMA mapping the @pte.
+ * @addr: The address where the @pte is mapped.
+ * @pte: The PTE.
+ *
+ * Get the "struct folio" associated with a PTE. See __vm_normal_page()
+ * for details on "normal" and "special" mappings.
+ *
+ * Return: Returns the "struct folio" if this is a "normal" mapping. Returns
+ *	   NULL if this is a "special" mapping.
+ */
 struct folio *vm_normal_folio(struct vm_area_struct *vma, unsigned long addr,
 			    pte_t pte)
 {
@@ -732,42 +769,37 @@ struct folio *vm_normal_folio(struct vm_area_struct *vma, unsigned long addr,
 }
 
 #ifdef CONFIG_PGTABLE_HAS_HUGE_LEAVES
+/**
+ * vm_normal_page_pmd() - Get the "struct page" associated with a PMD
+ * @vma: The VMA mapping the @pmd.
+ * @addr: The address where the @pmd is mapped.
+ * @pmd: The PMD.
+ *
+ * Get the "struct page" associated with a PTE. See __vm_normal_page()
+ * for details on "normal" and "special" mappings.
+ *
+ * Return: Returns the "struct page" if this is a "normal" mapping. Returns
+ *	   NULL if this is a "special" mapping.
+ */
 struct page *vm_normal_page_pmd(struct vm_area_struct *vma, unsigned long addr,
 				pmd_t pmd)
 {
-	unsigned long pfn = pmd_pfn(pmd);
-
-	if (unlikely(pmd_special(pmd)))
-		return NULL;
-
-	if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
-		if (vma->vm_flags & VM_MIXEDMAP) {
-			if (!pfn_valid(pfn))
-				return NULL;
-			goto out;
-		} else {
-			unsigned long off;
-			off = (addr - vma->vm_start) >> PAGE_SHIFT;
-			if (pfn == vma->vm_pgoff + off)
-				return NULL;
-			if (!is_cow_mapping(vma->vm_flags))
-				return NULL;
-		}
-	}
-
-	if (is_huge_zero_pfn(pfn))
-		return NULL;
-	if (unlikely(pfn > highest_memmap_pfn))
-		return NULL;
-
-	/*
-	 * NOTE! We still have PageReserved() pages in the page tables.
-	 * eg. VDSO mappings can cause them to exist.
-	 */
-out:
-	return pfn_to_page(pfn);
+	return __vm_normal_page(vma, addr, pmd_pfn(pmd), pmd_special(pmd),
+				pmd_val(pmd), PGTABLE_LEVEL_PMD);
 }
 
+/**
+ * vm_normal_folio_pmd() - Get the "struct folio" associated with a PMD
+ * @vma: The VMA mapping the @pmd.
+ * @addr: The address where the @pmd is mapped.
+ * @pmd: The PMD.
+ *
+ * Get the "struct folio" associated with a PTE. See __vm_normal_page()
+ * for details on "normal" and "special" mappings.
+ *
+ * Return: Returns the "struct folio" if this is a "normal" mapping. Returns
+ *	   NULL if this is a "special" mapping.
+ */
 struct folio *vm_normal_folio_pmd(struct vm_area_struct *vma,
 				  unsigned long addr, pmd_t pmd)
 {
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
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	Wei Yang 
Subject: [PATCH v3 11/11] mm: rename vm_ops->find_special_page() to vm_ops->find_normal_page()
Date: Mon, 11 Aug 2025 13:26:31 +0200
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... and hide it behind a kconfig option. There is really no need for
any !xen code to perform this check.

The naming is a bit off: we want to find the "normal" page when a PTE
was marked "special". So it's really not "finding a special" page.

Improve the documentation, and add a comment in the code where XEN ends
up performing the pte_mkspecial() through a hypercall. More details can
be found in commit 923b2919e2c3 ("xen/gntdev: mark userspace PTEs as
special on x86 PV guests").

Cc: David Vrabel 
Reviewed-by: Oscar Salvador 
Reviewed-by: Lorenzo Stoakes 
Reviewed-by: Wei Yang 
Signed-off-by: David Hildenbrand 
---
 drivers/xen/Kconfig              |  1 +
 drivers/xen/gntdev.c             |  5 +++--
 include/linux/mm.h               | 18 +++++++++++++-----
 mm/Kconfig                       |  2 ++
 mm/memory.c                      | 12 ++++++++++--
 tools/testing/vma/vma_internal.h | 18 +++++++++++++-----
 6 files changed, 42 insertions(+), 14 deletions(-)

diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
index 24f485827e039..f9a35ed266ecf 100644
--- a/drivers/xen/Kconfig
+++ b/drivers/xen/Kconfig
@@ -138,6 +138,7 @@ config XEN_GNTDEV
 	depends on XEN
 	default m
 	select MMU_NOTIFIER
+	select FIND_NORMAL_PAGE
 	help
 	  Allows userspace processes to use grants.
 
diff --git a/drivers/xen/gntdev.c b/drivers/xen/gntdev.c
index 1f21607656182..26f13b37c78e6 100644
--- a/drivers/xen/gntdev.c
+++ b/drivers/xen/gntdev.c
@@ -321,6 +321,7 @@ static int find_grant_ptes(pte_t *pte, unsigned long addr, void *data)
 	BUG_ON(pgnr >= map->count);
 	pte_maddr = arbitrary_virt_to_machine(pte).maddr;
 
+	/* Note: this will perform a pte_mkspecial() through the hypercall. */
 	gnttab_set_map_op(&map->map_ops[pgnr], pte_maddr, flags,
 			  map->grants[pgnr].ref,
 			  map->grants[pgnr].domid);
@@ -528,7 +529,7 @@ static void gntdev_vma_close(struct vm_area_struct *vma)
 	gntdev_put_map(priv, map);
 }
 
-static struct page *gntdev_vma_find_special_page(struct vm_area_struct *vma,
+static struct page *gntdev_vma_find_normal_page(struct vm_area_struct *vma,
 						 unsigned long addr)
 {
 	struct gntdev_grant_map *map = vma->vm_private_data;
@@ -539,7 +540,7 @@ static struct page *gntdev_vma_find_special_page(struct vm_area_struct *vma,
 static const struct vm_operations_struct gntdev_vmops = {
 	.open = gntdev_vma_open,
 	.close = gntdev_vma_close,
-	.find_special_page = gntdev_vma_find_special_page,
+	.find_normal_page = gntdev_vma_find_normal_page,
 };
 
 /* ------------------------------------------------------------------ */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 8ca7d2fa71343..3868ca1a25f9c 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -657,13 +657,21 @@ struct vm_operations_struct {
 	struct mempolicy *(*get_policy)(struct vm_area_struct *vma,
 					unsigned long addr, pgoff_t *ilx);
 #endif
+#ifdef CONFIG_FIND_NORMAL_PAGE
 	/*
-	 * Called by vm_normal_page() for special PTEs to find the
-	 * page for @addr.  This is useful if the default behavior
-	 * (using pte_page()) would not find the correct page.
+	 * Called by vm_normal_page() for special PTEs in @vma at @addr. This
+	 * allows for returning a "normal" page from vm_normal_page() even
+	 * though the PTE indicates that the "struct page" either does not exist
+	 * or should not be touched: "special".
+	 *
+	 * Do not add new users: this really only works when a "normal" page
+	 * was mapped, but then the PTE got changed to something weird (+
+	 * marked special) that would not make pte_pfn() identify the originally
+	 * inserted page.
 	 */
-	struct page *(*find_special_page)(struct vm_area_struct *vma,
-					  unsigned long addr);
+	struct page *(*find_normal_page)(struct vm_area_struct *vma,
+					 unsigned long addr);
+#endif /* CONFIG_FIND_NORMAL_PAGE */
 };
 
 #ifdef CONFIG_NUMA_BALANCING
diff --git a/mm/Kconfig b/mm/Kconfig
index e443fe8cd6cf2..59a04d0b2e272 100644
--- a/mm/Kconfig
+++ b/mm/Kconfig
@@ -1381,6 +1381,8 @@ config PT_RECLAIM
 
 	  Note: now only empty user PTE page table pages will be reclaimed.
 
+config FIND_NORMAL_PAGE
+	def_bool n
 
 source "mm/damon/Kconfig"
 
diff --git a/mm/memory.c b/mm/memory.c
index 6f806bf3cc994..002c28795d8b7 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -639,6 +639,12 @@ static void print_bad_page_map(struct vm_area_struct *vma,
  * trivial. Secondly, an architecture may not have a spare page table
  * entry bit, which requires a more complicated scheme, described below.
  *
+ * With CONFIG_FIND_NORMAL_PAGE, we might have the "special" bit set on
+ * page table entries that actually map "normal" pages: however, that page
+ * cannot be looked up through the PFN stored in the page table entry, but
+ * instead will be looked up through vm_ops->find_normal_page(). So far, this
+ * only applies to PTEs.
+ *
  * A raw VM_PFNMAP mapping (ie. one that is not COWed) is always considered a
  * special mapping (even if there are underlying and valid "struct pages").
  * COWed pages of a VM_PFNMAP are always normal.
@@ -679,8 +685,10 @@ static inline struct page *__vm_normal_page(struct vm_area_struct *vma,
 {
 	if (IS_ENABLED(CONFIG_ARCH_HAS_PTE_SPECIAL)) {
 		if (unlikely(special)) {
-			if (vma->vm_ops && vma->vm_ops->find_special_page)
-				return vma->vm_ops->find_special_page(vma, addr);
+#ifdef CONFIG_FIND_NORMAL_PAGE
+			if (vma->vm_ops && vma->vm_ops->find_normal_page)
+				return vma->vm_ops->find_normal_page(vma, addr);
+#endif /* CONFIG_FIND_NORMAL_PAGE */
 			if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
 				return NULL;
 			if (is_zero_pfn(pfn) || is_huge_zero_pfn(pfn))
diff --git a/tools/testing/vma/vma_internal.h b/tools/testing/vma/vma_internal.h
index 3639aa8dd2b06..cb1c2a8afe265 100644
--- a/tools/testing/vma/vma_internal.h
+++ b/tools/testing/vma/vma_internal.h
@@ -467,13 +467,21 @@ struct vm_operations_struct {
 	struct mempolicy *(*get_policy)(struct vm_area_struct *vma,
 					unsigned long addr, pgoff_t *ilx);
 #endif
+#ifdef CONFIG_FIND_NORMAL_PAGE
 	/*
-	 * Called by vm_normal_page() for special PTEs to find the
-	 * page for @addr.  This is useful if the default behavior
-	 * (using pte_page()) would not find the correct page.
+	 * Called by vm_normal_page() for special PTEs in @vma at @addr. This
+	 * allows for returning a "normal" page from vm_normal_page() even
+	 * though the PTE indicates that the "struct page" either does not exist
+	 * or should not be touched: "special".
+	 *
+	 * Do not add new users: this really only works when a "normal" page
+	 * was mapped, but then the PTE got changed to something weird (+
+	 * marked special) that would not make pte_pfn() identify the originally
+	 * inserted page.
 	 */
-	struct page *(*find_special_page)(struct vm_area_struct *vma,
-					  unsigned long addr);
+	struct page *(*find_normal_page)(struct vm_area_struct *vma,
+					 unsigned long addr);
+#endif /* CONFIG_FIND_NORMAL_PAGE */
 };
 
 struct vm_unmapped_area_info {
-- 
2.50.1



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From: David Hildenbrand 
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org,
	xen-devel@lists.xenproject.org,
	linux-fsdevel@vger.kernel.org,
	nvdimm@lists.linux.dev,
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	Dev Jain ,
	Barry Song ,
	Jann Horn ,
	Pedro Falcato ,
	Hugh Dickins ,
	Oscar Salvador ,
	Lance Yang ,
	Wei Yang 
Subject: [PATCH v3 10/11] mm: introduce and use vm_normal_page_pud()
Date: Mon, 11 Aug 2025 13:26:30 +0200
Message-ID: <20250811112631.759341-11-david@redhat.com>
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Let's introduce vm_normal_page_pud(), which ends up being fairly simple
because of our new common helpers and there not being a PUD-sized zero
folio.

Use vm_normal_page_pud() in folio_walk_start() to resolve a TODO,
structuring the code like the other (pmd/pte) cases. Defer
introducing vm_normal_folio_pud() until really used.

Note that we can so far get PUDs with hugetlb, daxfs and PFNMAP entries.

Reviewed-by: Wei Yang 
Reviewed-by: Oscar Salvador 
Signed-off-by: David Hildenbrand 
---
 include/linux/mm.h |  2 ++
 mm/memory.c        | 19 +++++++++++++++++++
 mm/pagewalk.c      | 20 ++++++++++----------
 3 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/include/linux/mm.h b/include/linux/mm.h
index b626d1bacef52..8ca7d2fa71343 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -2360,6 +2360,8 @@ struct folio *vm_normal_folio_pmd(struct vm_area_struct *vma,
 				  unsigned long addr, pmd_t pmd);
 struct page *vm_normal_page_pmd(struct vm_area_struct *vma, unsigned long addr,
 				pmd_t pmd);
+struct page *vm_normal_page_pud(struct vm_area_struct *vma, unsigned long addr,
+		pud_t pud);
 
 void zap_vma_ptes(struct vm_area_struct *vma, unsigned long address,
 		  unsigned long size);
diff --git a/mm/memory.c b/mm/memory.c
index 78af3f243cee7..6f806bf3cc994 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -809,6 +809,25 @@ struct folio *vm_normal_folio_pmd(struct vm_area_struct *vma,
 		return page_folio(page);
 	return NULL;
 }
+
+/**
+ * vm_normal_page_pud() - Get the "struct page" associated with a PUD
+ * @vma: The VMA mapping the @pud.
+ * @addr: The address where the @pud is mapped.
+ * @pud: The PUD.
+ *
+ * Get the "struct page" associated with a PUD. See __vm_normal_page()
+ * for details on "normal" and "special" mappings.
+ *
+ * Return: Returns the "struct page" if this is a "normal" mapping. Returns
+ *	   NULL if this is a "special" mapping.
+ */
+struct page *vm_normal_page_pud(struct vm_area_struct *vma,
+		unsigned long addr, pud_t pud)
+{
+	return __vm_normal_page(vma, addr, pud_pfn(pud), pud_special(pud),
+				pud_val(pud), PGTABLE_LEVEL_PUD);
+}
 #endif
 
 /**
diff --git a/mm/pagewalk.c b/mm/pagewalk.c
index 648038247a8d2..c6753d370ff4e 100644
--- a/mm/pagewalk.c
+++ b/mm/pagewalk.c
@@ -902,23 +902,23 @@ struct folio *folio_walk_start(struct folio_walk *fw,
 		fw->pudp = pudp;
 		fw->pud = pud;
 
-		/*
-		 * TODO: FW_MIGRATION support for PUD migration entries
-		 * once there are relevant users.
-		 */
-		if (!pud_present(pud) || pud_special(pud)) {
+		if (pud_none(pud)) {
 			spin_unlock(ptl);
 			goto not_found;
-		} else if (!pud_leaf(pud)) {
+		} else if (pud_present(pud) && !pud_leaf(pud)) {
 			spin_unlock(ptl);
 			goto pmd_table;
+		} else if (pud_present(pud)) {
+			page = vm_normal_page_pud(vma, addr, pud);
+			if (page)
+				goto found;
 		}
 		/*
-		 * TODO: vm_normal_page_pud() will be handy once we want to
-		 * support PUD mappings in VM_PFNMAP|VM_MIXEDMAP VMAs.
+		 * TODO: FW_MIGRATION support for PUD migration entries
+		 * once there are relevant users.
 		 */
-		page = pud_page(pud);
-		goto found;
+		spin_unlock(ptl);
+		goto not_found;
 	}
 
 pmd_table:
-- 
2.50.1



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Subject: Re: [PATCH v3 14/20] xen/riscv: Implement p2m_pte_from_mfn() and
 support PBMT configuration
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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In-Reply-To: <1370613cd6f52e90591b15ad52c95d7c81908cf6.1753973161.git.oleksii.kurochko@gmail.com>
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On 31.07.2025 17:58, Oleksii Kurochko wrote:
> --- a/xen/arch/riscv/p2m.c
> +++ b/xen/arch/riscv/p2m.c
> @@ -1,3 +1,4 @@
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -197,6 +198,18 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
>      return __map_domain_page(p2m->root + root_table_indx);
>  }
>  
> +static int p2m_set_type(pte_t *pte, p2m_type_t t)
> +{
> +    int rc = 0;
> +
> +    if ( t > p2m_ext_storage )

Seeing this separator enumerator in use, it becomes pretty clear that its name
needs to change, so one doesn't need to go look at its definition to understand
whether it's inclusive or exclusive. (This isn't helped by there presently being
a spare entry, which, when made use of, might then cause problems with
expressions like this one as well.)

> @@ -222,11 +235,71 @@ static inline void p2m_clean_pte(pte_t *p, bool clean_pte)
>      p2m_write_pte(p, pte, clean_pte);
>  }
>  
> -static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t)
> +static void p2m_set_permission(pte_t *e, p2m_type_t t)
>  {
> -    panic("%s: hasn't been implemented yet\n", __func__);
> +    e->pte &= ~PTE_ACCESS_MASK;
> +
> +    switch ( t )
> +    {
> +    case p2m_grant_map_rw:
> +    case p2m_ram_rw:
> +        e->pte |= PTE_READABLE | PTE_WRITABLE;
> +        break;

While I agree for r/w grants, shouldn't r/w RAM also be executable?

> +    case p2m_ext_storage:

Why exactly would this placeholder ...

> +    case p2m_mmio_direct_io:
> +        e->pte |= PTE_ACCESS_MASK;
> +        break;

... gain full access? It shouldn't make it here at all, should it?

> +
> +    case p2m_invalid:
> +        e->pte &= ~(PTE_ACCESS_MASK | PTE_VALID);

Redundantly masking off PTE_ACCESS_MASK? (Plus, for the entry to be
invalid, turning off PTE_VALID alone ought to suffice anyway?)

> +        break;
> +
> +    case p2m_grant_map_ro:
> +        e->pte |= PTE_READABLE;
> +        break;
> +
> +    default:
> +        ASSERT_UNREACHABLE();
> +        break;
> +    }
> +}
> +
> +static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
> +{
> +    pte_t e = (pte_t) { PTE_VALID };

This and the rest of the function demand that mfn != INVALID_MFN, no matter
whether ...

> +    switch ( t )
> +    {
> +    case p2m_mmio_direct_io:
> +        e.pte |= PTE_PBMT_IO;
> +        break;
> +
> +    default:
> +        break;
> +    }
> +
> +    pte_set_mfn(&e, mfn);
> +
> +    ASSERT(!(mfn_to_maddr(mfn) & ~PADDR_MASK));

... PADDR_MASK is actually narrow enough to catch that case. Maybe best to
add an explicit assertion to that effect?

> +    if ( !is_table )
> +    {
> +        p2m_set_permission(&e, t);
> +
> +        if ( t < p2m_ext_storage )
> +            p2m_set_type(&e, t);
> +        else
> +            panic("unimplemeted\n");

The check is already done inside p2m_set_type() - why open-code it here?

Jan


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Message-ID: <59303864-c6c7-4d6c-be43-8cf9a887cfe2@citrix.com>
Date: Mon, 11 Aug 2025 12:38:42 +0100
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH 21/22] x86/traps: Introduce FRED entrypoints
To: Xen-devel 
Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-22-andrew.cooper3@citrix.com>
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From: Andrew Cooper 
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In-Reply-To: <20250808202314.1045968-22-andrew.cooper3@citrix.com>
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On 08/08/2025 9:23 pm, Andrew Cooper wrote:
> diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
> index 270b93ed623e..e67a428e4362 100644
> --- a/xen/arch/x86/traps.c
> +++ b/xen/arch/x86/traps.c
> @@ -2181,6 +2240,94 @@ void asmlinkage check_ist_exit(const struct cpu_user_regs *regs, bool ist_exit)
>  }
>  #endif
>  
> +void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
> +{
> +    /* Copy fred_ss.vector into entry_vector as IDT delivery would have done. */
> +    regs->entry_vector = regs->fred_ss.vector;
> +
> +    switch ( regs->fred_ss.type )
> +    {
> +    case X86_ET_EXT_INTR:
> +        do_IRQ(regs);
> +        break;
> +
> +    case X86_ET_NMI:
> +        do_nmi(regs);
> +        break;
> +
> +    case X86_ET_HW_EXC:
> +    case X86_ET_SW_INT:
> +    case X86_ET_PRIV_SW_EXC:
> +    case X86_ET_SW_EXC:
> +        goto fatal;
> +
> +    default:
> +        goto fatal;
> +    }
> +
> +    return;
> +
> + fatal:
> +    fatal_trap(regs, false);
> +}
> +
> +void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
> +{
> +    /* Copy fred_ss.vector into entry_vector as IDT delivery would have done. */
> +    regs->entry_vector = regs->fred_ss.vector;
> +
> +    switch ( regs->fred_ss.type )
> +    {
> +    case X86_ET_EXT_INTR:
> +        do_IRQ(regs);
> +        break;
> +
> +    case X86_ET_NMI:
> +        do_nmi(regs);
> +        break;
> +
> +    case X86_ET_HW_EXC:
> +    case X86_ET_SW_INT:
> +    case X86_ET_PRIV_SW_EXC:
> +    case X86_ET_SW_EXC:
> +        switch ( regs->fred_ss.vector )
> +        {
> +        case X86_EXC_PF:  do_page_fault(regs); break;
> +        case X86_EXC_GP:  do_general_protection(regs); break;
> +        case X86_EXC_UD:  do_invalid_op(regs); break;
> +        case X86_EXC_NM:  do_device_not_available(regs); break;
> +        case X86_EXC_BP:  do_int3(regs); break;
> +        case X86_EXC_DB:  do_debug(regs); break;
> +        case X86_EXC_DF:  do_double_fault(regs); break;
> +
> +        case X86_EXC_DE:
> +        case X86_EXC_OF:
> +        case X86_EXC_BR:
> +        case X86_EXC_NP:
> +        case X86_EXC_SS:
> +        case X86_EXC_MF:
> +        case X86_EXC_AC:
> +        case X86_EXC_XM:
> +            do_trap(regs);
> +            break;
> +
> +        case X86_EXC_CP:  do_entry_CP(regs); break;
> +
> +        default:
> +            goto fatal;
> +        }
> +        break;
> +
> +    default:
> +        goto fatal;
> +    }
> +
> +    return;
> +
> + fatal:
> +    fatal_trap(regs, false);
> +}

Having started work on the PV support, I think this patch needs to
change somewhat.

I've split #DB and #PF to have separate IDT prologues, which in turns
gives us uniform handling of IRQ re-enabling for synchronous actions. 
But, async still needs special handling.

I think we want something that looks more like:

    switch ( regs->fred_ss.type )
    {
    case X86_ET_EXT_INTR: return do_IRQ(regs);
    case X86_ET_NMI:      return do_nmi(regs);
    case X86_ET_HW_EXC:
        if ( regs->fred_ss.vector == X86_EXC_MC )
            return do_machine_check(regs);
        break;
    }

    if ( regs->eflags & X86_EFLAGS_IF ) // From Xen only
        local_irq_enable();             // From both

    switch ( regs->fred_ss.type )


Either way, it's probably not worth focusing too much on how the C in
this patch looks for now.

~Andrew


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Subject: Re: [PATCH v3 15/20] xen/riscv: implement p2m_next_level()
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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On 31.07.2025 17:58, Oleksii Kurochko wrote:
> --- a/xen/arch/riscv/p2m.c
> +++ b/xen/arch/riscv/p2m.c
> @@ -302,6 +302,48 @@ static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
>      return e;
>  }
>  
> +/* Generate table entry with correct attributes. */
> +static pte_t page_to_p2m_table(struct page_info *page)

You don't mean to alter what page points to, so pointer-to-const please.

> @@ -326,9 +368,43 @@ static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl,
>                            unsigned int level, pte_t **table,
>                            unsigned int offset)
>  {
> -    panic("%s: hasn't been implemented yet\n", __func__);
> +    pte_t *entry;
> +    int ret;

Please can this move into the more narrow scope it's (solely) used in?

> +    mfn_t mfn;
> +
> +    /* The function p2m_next_level() is never called at the last level */
> +    ASSERT(level != 0);

The revlog says "move", but ...

> +    entry = *table + offset;
> +
> +    if ( !pte_is_valid(*entry) )
> +    {
> +        if ( !alloc_tbl )
> +            return P2M_TABLE_MAP_NONE;
> +
> +        ret = p2m_create_table(p2m, entry);
> +        if ( ret )
> +            return P2M_TABLE_MAP_NOMEM;
> +    }
> +
> +    /* The function p2m_next_level() is never called at the last level */
> +    ASSERT(level != 0);

... the original one's still here.

> --- a/xen/arch/riscv/paging.c
> +++ b/xen/arch/riscv/paging.c
> @@ -91,6 +91,17 @@ void paging_free_page(struct domain *d, struct page_info *pg)
>      spin_unlock(&d->arch.paging.lock);
>  }
>  
> +struct page_info * paging_alloc_page(struct domain *d)

Nit: Stray blank after *.

Jan


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Subject: Re: [PATCH v3 16/20] xen/riscv: Implement superpage splitting for p2m
 mappings
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <6890f77e577493194ea94834989dc0841d18eed0.1753973161.git.oleksii.kurochko@gmail.com>
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On 31.07.2025 17:58, Oleksii Kurochko wrote:
> Add support for down large memory mappings ("superpages") in the RISC-V
> p2m mapping so that smaller, more precise mappings ("finer-grained entries")
> can be inserted into lower levels of the page table hierarchy.
> 
> To implement that the following is done:
> - Introduce p2m_split_superpage(): Recursively shatters a superpage into
>   smaller page table entries down to the target level, preserving original
>   permissions and attributes.
> - p2m_set_entry() updated to invoke superpage splitting when inserting
>   entries at lower levels within a superpage-mapped region.
> 
> This implementation is based on the ARM code, with modifications to the part
> that follows the BBM (break-before-make) approach, some parts are simplified
> as according to RISC-V spec:
>   It is permitted for multiple address-translation cache entries to co-exist
>   for the same address. This represents the fact that in a conventional
>   TLB hierarchy, it is possible for multiple entries to match a single
>   address if, for example, a page is upgraded to a superpage without first
>   clearing the original non-leaf PTE’s valid bit and executing an SFENCE.VMA
>   with rs1=x0, or if multiple TLBs exist in parallel at a given level of the
>   hierarchy. In this case, just as if an SFENCE.VMA is not executed between
>   a write to the memory-management tables and subsequent implicit read of the
>   same address: it is unpredictable whether the old non-leaf PTE or the new
>   leaf PTE is used, but the behavior is otherwise well defined.
> In contrast to the Arm architecture, where BBM is mandatory and failing to
> use it in some cases can lead to CPU instability, RISC-V guarantees
> stability, and the behavior remains safe — though unpredictable in terms of
> which translation will be used.
> 
> Additionally, the page table walk logic has been adjusted, as ARM uses the
> opposite number of levels compared to RISC-V.

As before, I think you mean "numbering".

> --- a/xen/arch/riscv/p2m.c
> +++ b/xen/arch/riscv/p2m.c
> @@ -539,6 +539,91 @@ static void p2m_free_subtree(struct p2m_domain *p2m,
>      p2m_free_page(p2m, pg);
>  }
>  
> +static bool p2m_split_superpage(struct p2m_domain *p2m, pte_t *entry,
> +                                unsigned int level, unsigned int target,
> +                                const unsigned int *offsets)
> +{
> +    struct page_info *page;
> +    unsigned long i;
> +    pte_t pte, *table;
> +    bool rv = true;
> +
> +    /* Convenience aliases */
> +    mfn_t mfn = pte_get_mfn(*entry);
> +    unsigned int next_level = level - 1;
> +    unsigned int level_order = XEN_PT_LEVEL_ORDER(next_level);
> +
> +    /*
> +     * This should only be called with target != level and the entry is
> +     * a superpage.
> +     */
> +    ASSERT(level > target);
> +    ASSERT(pte_is_superpage(*entry, level));
> +
> +    page = p2m_alloc_page(p2m->domain);
> +    if ( !page )
> +    {
> +        /*
> +         * The caller is in charge to free the sub-tree.
> +         * As we didn't manage to allocate anything, just tell the
> +         * caller there is nothing to free by invalidating the PTE.
> +         */
> +        memset(entry, 0, sizeof(*entry));
> +        return false;
> +    }
> +
> +    table = __map_domain_page(page);
> +
> +    /*
> +     * We are either splitting a second level 1G page into 512 first level
> +     * 2M pages, or a first level 2M page into 512 zero level 4K pages.
> +     */

Such a comment is at risk of (silently) going stale when support for 512G
mappings is added. I wonder if it's really that informative to have here.

> +    for ( i = 0; i < XEN_PT_ENTRIES; i++ )
> +    {
> +        pte_t *new_entry = table + i;
> +
> +        /*
> +         * Use the content of the superpage entry and override
> +         * the necessary fields. So the correct permission are kept.
> +         */

It's not just permissions though? The memory type field also needs
retaining (and is being retained this way). Maybe better say "attributes"?

Jan


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Subject: Ping: [PATCH v3] EFI/runtime: switch to xv[mz]alloc_array()
From: Jan Beulich 
To: Marek Marczykowski ,
 Daniel Smith 
Cc: "xen-devel@lists.xenproject.org" 
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On 23.07.2025 15:39, Jan Beulich wrote:
> Use the more "modern" form, thus doing away with effectively open-coding
> xmalloc_array() at the same time. While there is a difference in
> generated code, as xmalloc_bytes() forces SMP_CACHE_BYTES alignment, if
> code really cared about such higher than default alignment, it should
> request so explicitly.
> 
> Signed-off-by: Jan Beulich 
> ---
> v3: Use xv[mz]alloc_array().

May I ask for an ack (or otherwise) please? Perhaps also for Ross'es
"efi: Call FreePages only if needed"?

Thanks, Jan

> --- a/xen/common/efi/runtime.c
> +++ b/xen/common/efi/runtime.c
> @@ -6,6 +6,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  DEFINE_XEN_GUEST_HANDLE(CHAR16);
>  
> @@ -500,23 +501,23 @@ int efi_runtime_call(struct xenpf_efi_ru
>          len = gwstrlen(guest_handle_cast(op->u.get_variable.name, CHAR16));
>          if ( len < 0 )
>              return len;
> -        name = xmalloc_array(CHAR16, ++len);
> +        name = xvmalloc_array(CHAR16, ++len);
>          if ( !name )
>             return -ENOMEM;
>          if ( __copy_from_guest(name, op->u.get_variable.name, len) ||
>               wmemchr(name, 0, len) != name + len - 1 )
>          {
> -            xfree(name);
> +            xvfree(name);
>              return -EIO;
>          }
>  
>          size = op->u.get_variable.size;
>          if ( size )
>          {
> -            data = xmalloc_bytes(size);
> +            data = xvmalloc_array(unsigned char, size);
>              if ( !data )
>              {
> -                xfree(name);
> +                xvfree(name);
>                  return -ENOMEM;
>              }
>          }
> @@ -539,8 +540,8 @@ int efi_runtime_call(struct xenpf_efi_ru
>          else
>              rc = -EOPNOTSUPP;
>  
> -        xfree(data);
> -        xfree(name);
> +        xvfree(data);
> +        xvfree(name);
>      }
>      break;
>  
> @@ -553,17 +554,17 @@ int efi_runtime_call(struct xenpf_efi_ru
>          len = gwstrlen(guest_handle_cast(op->u.set_variable.name, CHAR16));
>          if ( len < 0 )
>              return len;
> -        name = xmalloc_array(CHAR16, ++len);
> +        name = xvmalloc_array(CHAR16, ++len);
>          if ( !name )
>             return -ENOMEM;
>          if ( __copy_from_guest(name, op->u.set_variable.name, len) ||
>               wmemchr(name, 0, len) != name + len - 1 )
>          {
> -            xfree(name);
> +            xvfree(name);
>              return -EIO;
>          }
>  
> -        data = xmalloc_bytes(op->u.set_variable.size);
> +        data = xvmalloc_array(unsigned char, op->u.set_variable.size);
>          if ( !data )
>              rc = -ENOMEM;
>          else if ( copy_from_guest(data, op->u.set_variable.data,
> @@ -581,8 +582,8 @@ int efi_runtime_call(struct xenpf_efi_ru
>              efi_rs_leave(&state);
>          }
>  
> -        xfree(data);
> -        xfree(name);
> +        xvfree(data);
> +        xvfree(name);
>      }
>      break;
>  
> @@ -598,13 +599,13 @@ int efi_runtime_call(struct xenpf_efi_ru
>              return -EINVAL;
>  
>          size = op->u.get_next_variable_name.size;
> -        name.raw = xzalloc_bytes(size);
> +        name.raw = xvzalloc_array(unsigned char, size);
>          if ( !name.raw )
>              return -ENOMEM;
>          if ( copy_from_guest(name.raw, op->u.get_next_variable_name.name,
>                               size) )
>          {
> -            xfree(name.raw);
> +            xvfree(name.raw);
>              return -EFAULT;
>          }
>  
> @@ -629,7 +630,7 @@ int efi_runtime_call(struct xenpf_efi_ru
>          else
>              rc = -EOPNOTSUPP;
>  
> -        xfree(name.raw);
> +        xvfree(name.raw);
>      }
>      break;
>  



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Subject: Re: [PATCH v3 17/20] xen/riscv: implement put_page()
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
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On 31.07.2025 17:58, Oleksii Kurochko wrote:
> Implement put_page(), as it will be used by p2m_put_code().

I would have ack-ed the code change, but the description is irritating:
Who or what is p2m_put_code() (going to be)?

> Although CONFIG_STATIC_MEMORY has not yet been introduced for RISC-V,
> a stub for PGC_static is added to avoid cluttering the code of
> put_page_nr() with #ifdefs.

There isn't any put_page_nr() being introduced (anymore), though.

Jan


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Subject: Re: [PATCH v3 18/20] xen/riscv: implement mfn_valid() and page
 reference, ownership handling helpers
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
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On 31.07.2025 17:58, Oleksii Kurochko wrote:
> Implement the mfn_valid() macro to verify whether a given MFN is valid by
> checking that it falls within the range [start_page, max_page).
> These bounds are initialized based on the start and end addresses of RAM.
> 
> As part of this patch, start_page is introduced and initialized with the
> PFN of the first RAM page.
> Also, initialize pdx_group_valid() by calling set_pdx_range() when
> memory banks are being mapped.
> 
> Also, after providing a non-stub implementation of the mfn_valid() macro,
> the following compilation errors started to occur:
>   riscv64-linux-gnu-ld: prelink.o: in function `__next_node':
>   /build/xen/./include/xen/nodemask.h:202: undefined reference to `page_is_ram_type'
>   riscv64-linux-gnu-ld: prelink.o: in function `get_free_buddy':
>   /build/xen/common/page_alloc.c:881: undefined reference to `page_is_ram_type'
>   riscv64-linux-gnu-ld: prelink.o: in function `alloc_heap_pages':
>   /build/xen/common/page_alloc.c:1043: undefined reference to `page_get_owner_and_reference'
>   riscv64-linux-gnu-ld: /build/xen/common/page_alloc.c:1098: undefined reference to `page_is_ram_type'
>   riscv64-linux-gnu-ld: prelink.o: in function `ns16550_interrupt':
>   /build/xen/drivers/char/ns16550.c:205: undefined reference to `get_page'
>   riscv64-linux-gnu-ld: ./.xen-syms.0: hidden symbol `page_get_owner_and_reference' isn't defined
>   riscv64-linux-gnu-ld: final link failed: bad value
>   make[2]: *** [arch/riscv/Makefile:35: xen-syms] Error 1
> To resolve these errors, the following functions have also been introduced,
> based on their Arm counterparts:
> - page_get_owner_and_reference() and its variant to safely acquire a
>   reference to a page and retrieve its owner.
> - A stub for page_is_ram_type() that currently always returns 0 and asserts
>   unreachable, as RAM type checking is not yet implemented.

For this latter part I can only repeat that the code is reachable, and hence it
is wrong to put ASSERT_UNREACHABLE() there. That's true for Arm's code as well.

> Signed-off-by: Oleksii Kurochko 

With said line dropped:
Acked-by: Jan Beulich 

Jan


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To: "xen-devel@lists.xenproject.org" 
Cc: Julien Grall , Stefano Stabellini
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From: Jan Beulich 
Subject: [PATCH] Arm: drop assertion from page_is_ram_type()
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Its uses in offline_page() and query_page_offline() make it reachable on
Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
code added. It being reachable was even mentioned in the commit
introducing it, claiming it "clearly shouldn't be called on ARM just
yet".

Fixes: 214c4cd94a80 ("xen: arm: stub page_is_ram_type")
Signed-off-by: Jan Beulich 

--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -66,7 +66,6 @@ int steal_page(
 
 int page_is_ram_type(unsigned long mfn, unsigned long mem_type)
 {
-    ASSERT_UNREACHABLE();
     return 0;
 }
 


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Subject: Re: S3 regression related to XSA-471 patches
To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
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On 07/08/2025 6:29 pm, Marek Marczykowski-Górecki wrote:
> On Wed, Aug 06, 2025 at 12:46:36PM +0200, Marek Marczykowski-Górecki wrote:
>> On Wed, Aug 06, 2025 at 12:36:56PM +0200, Jan Beulich wrote:
>>> On 06.08.2025 12:23, Marek Marczykowski-Górecki wrote:
>>>> We've got several reports that S3 reliability recently regressed. We
>>>> identified it's definitely related to XSA-471 patches, and bisection
>>>> points at "x86/idle: Remove broken MWAIT implementation". I don't have
>>>> reliable reproduction steps, so I'm not 100% sure if it's really this
>>>> patch, or maybe an earlier one - but it's definitely already broken at
>>>> this point in the series. Most reports are about Xen 4.17 (as that's
>>>> what stable Qubes OS version currently use), but I think I've seen
>>>> somebody reporting the issue on 4.19 too (but I don't have clear
>>>> evidence, especially if it's the same issue).
>>> At the time we've been discussing the explicit raising of TIMER_SOFTIRQ
>>> in mwait_idle_with_hints() a lot. If it was now truly missing, that imo
>>> shouldn't cause problems only after resume, but then it may have covered
>>> for some omission during resume. As a far-fetched experiment, could you
>>> try putting that back (including the calculation of the "expires" local
>>> variable)?
>> Sure, I'll try.
> It appears this fixes the issue, at least in ~10 attempts so far
> (usually I could reproduce the issue after 2-3 attempts).
>

Can you show the exact code which seems to have made this stable?

We discussed this in the x86 maintainers meeting, and our best guess is
a timer that's not torn down or recreated properly on S3, but this is
largely speculation.

~Andrew


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Subject: Re: [PATCH v3 19/20] xen/riscv: add support of page lookup by GFN
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <24bb8ca6ad9d325f48d0c64b0fa461db5f0d0cc5.1753973161.git.oleksii.kurochko@gmail.com>
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On 31.07.2025 17:58, Oleksii Kurochko wrote:
> Introduce helper functions for safely querying the P2M (physical-to-machine)
> mapping:
>  - add p2m_read_lock(), p2m_read_unlock(), and p2m_is_locked() for managing
>    P2M lock state.
>  - Implement p2m_get_entry() to retrieve mapping details for a given GFN,
>    including MFN, page order, and validity.
>  - Add p2m_lookup() to encapsulate read-locked MFN retrieval.
>  - Introduce p2m_get_page_from_gfn() to convert a GFN into a page_info
>    pointer, acquiring a reference to the page if valid.
>  - Introduce get_page().
> 
> Implementations are based on Arm's functions with some minor modifications:
> - p2m_get_entry():
>   - Reverse traversal of page tables, as RISC-V uses the opposite level
>     numbering compared to Arm.
>   - Removed the return of p2m_access_t from p2m_get_entry() since
>     mem_access_settings is not introduced for RISC-V.
>   - Updated BUILD_BUG_ON() to check using the level 0 mask, which corresponds
>     to Arm's THIRD_MASK.
>   - Replaced open-coded bit shifts with the BIT() macro.
>   - Other minor changes, such as using RISC-V-specific functions to validate
>     P2M PTEs, and replacing Arm-specific GUEST_* macros with their RISC-V
>     equivalents.
> 
> Signed-off-by: Oleksii Kurochko 
> ---
> Changes in V3:
>  - Add is_p2m_foreign() macro and connected stuff.

What is this about?

> --- a/xen/arch/riscv/include/asm/p2m.h
> +++ b/xen/arch/riscv/include/asm/p2m.h
> @@ -202,6 +202,24 @@ static inline int p2m_is_write_locked(struct p2m_domain *p2m)
>  
>  unsigned long construct_hgatp(struct p2m_domain *p2m, uint16_t vmid);
>  
> +static inline void p2m_read_lock(struct p2m_domain *p2m)
> +{
> +    read_lock(&p2m->lock);
> +}
> +
> +static inline void p2m_read_unlock(struct p2m_domain *p2m)
> +{
> +    read_unlock(&p2m->lock);
> +}
> +
> +static inline int p2m_is_locked(struct p2m_domain *p2m)

bool return type (also for p2m_is_write_locked() in patch 11)? Also perhaps
pointer-to-const parameter?

> --- a/xen/arch/riscv/p2m.c
> +++ b/xen/arch/riscv/p2m.c
> @@ -852,3 +852,139 @@ int map_regions_p2mt(struct domain *d,
>  {
>      return p2m_insert_mapping(p2m_get_hostp2m(d), gfn, nr, mfn, p2mt);
>  }
> +
> +/*
> + * Get the details of a given gfn.
> + *
> + * If the entry is present, the associated MFN will be returned type filled up.

This sentence doesn't really parse, perhaps due to missing words.

> + * The page_order will correspond to the order of the mapping in the page
> + * table (i.e it could be a superpage).
> + *
> + * If the entry is not present, INVALID_MFN will be returned and the
> + * page_order will be set according to the order of the invalid range.
> + *
> + * valid will contain the value of bit[0] (e.g valid bit) of the
> + * entry.
> + */
> +static mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn,
> +                           p2m_type_t *t,
> +                           unsigned int *page_order,
> +                           bool *valid)
> +{
> +    unsigned int level = 0;
> +    pte_t entry, *table;
> +    int rc;
> +    mfn_t mfn = INVALID_MFN;
> +    DECLARE_OFFSETS(offsets, gfn_to_gaddr(gfn));
> +
> +    ASSERT(p2m_is_locked(p2m));
> +    BUILD_BUG_ON(XEN_PT_LEVEL_MAP_MASK(0) != PAGE_MASK);

What function-wide property is this check about? Even when moved ...

> +    if ( valid )
> +        *valid = false;
> +
> +    /* XXX: Check if the mapping is lower than the mapped gfn */

(Nested: What is this about?)

> +    /* This gfn is higher than the highest the p2m map currently holds */
> +    if ( gfn_x(gfn) > gfn_x(p2m->max_mapped_gfn) )
> +    {
> +        for ( level = P2M_ROOT_LEVEL; level; level-- )
> +            if ( (gfn_x(gfn) & (XEN_PT_LEVEL_MASK(level) >> PAGE_SHIFT)) >

... into the more narrow scope where another XEN_PT_LEVEL_MASK() exists I
can't really spot what the check is to guard against.

> +                 gfn_x(p2m->max_mapped_gfn) )
> +                break;
> +
> +        goto out;
> +    }
> +
> +    table = p2m_get_root_pointer(p2m, gfn);
> +
> +    /*
> +     * the table should always be non-NULL because the gfn is below
> +     * p2m->max_mapped_gfn and the root table pages are always present.
> +     */

Nit: Style.

> +    if ( !table )
> +    {
> +        ASSERT_UNREACHABLE();
> +        level = P2M_ROOT_LEVEL;
> +        goto out;
> +    }
> +
> +    for ( level = P2M_ROOT_LEVEL; level; level-- )
> +    {
> +        rc = p2m_next_level(p2m, true, level, &table, offsets[level]);

Why would you blindly allocate a page table (hierarchy) here? If anything,
this may need doing upon caller request (as it's only up the call chain
where the necessary knowledge exists). For example, ...

> +static mfn_t p2m_lookup(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t)
> +{
> +    mfn_t mfn;
> +
> +    p2m_read_lock(p2m);
> +    mfn = p2m_get_entry(p2m, gfn, t, NULL, NULL);

... this (by its name) pretty likely won't want allocation, while ...

> +    p2m_read_unlock(p2m);
> +
> +    return mfn;
> +}
> +
> +struct page_info *p2m_get_page_from_gfn(struct p2m_domain *p2m, gfn_t gfn,
> +                                        p2m_type_t *t)
> +{

... this will. Yet then ...

> +    struct page_info *page;
> +    p2m_type_t p2mt = p2m_invalid;
> +    mfn_t mfn = p2m_lookup(p2m, gfn, t);

... you use the earlier one here.

> +    if ( !mfn_valid(mfn) )
> +        return NULL;
> +
> +    if ( t )
> +        p2mt = *t;
> +
> +    page = mfn_to_page(mfn);
> +
> +    /*
> +     * get_page won't work on foreign mapping because the page doesn't
> +     * belong to the current domain.
> +     */
> +    if ( p2m_is_foreign(p2mt) )
> +    {
> +        struct domain *fdom = page_get_owner_and_reference(page);
> +        ASSERT(fdom != NULL);
> +        ASSERT(fdom != p2m->domain);
> +        return page;

In a release build (with no assertions) this will be wrong if either of the
two condition would not be satisfied. See x86'es respective code.

Jan


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To: xen-devel@lists.xenproject.org
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Volodymyr Babchuk ,
	Jens Wiklander ,
	Julien Grall 
Subject: [PATCH v8 0/6] FF-A VM to VM support
Date: Mon, 11 Aug 2025 15:34:41 +0200
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This patch serie adds support to use FF-A between VM for communications
using indirect messages.

It adds a Kconfig parameter to enable this feature and marks it as
experimental as for now there is no system to restrict communication
rights between VM using this system.

It also adds support to use VM to VM communications using FF-A even if
there is no firmware support for FF-A. As this feature enables FF-A
support in all cases, we also introduce a new command line parameter to
allow the user to force which tee is to be used between FF-A and Optee
to have a solution to enable optee support if FF-A VM to VM is enabled.

Changes since v7:
- typo fixes
- use LIST_HEAD and DEFINE_RWLOCK
- add Jens R-b and Julien A-b

Changes since v6:
- use a rwlock to protect access to the chain list of context
- rebase on top of staging
- add some R-b/A-b from Jens and Julien

Changes since v5:
- coding style fixes
- rework version negociation to use the context lock
- split probe into fw and vm to vm probe to make code clearer
- add some R-b from Jens

Changes since v4:
- fix typos and optimize command line parameter
- split VM to VM support in 2 patches to ease review
- organize ffa contexts in a chain list to be able to build the partinfo
  result without taking the global domain lock
- introduce a maximum number of SPs to prevent holding the CPU for too
  long during partinfo call
- use an atomic to store the number of FF-A VMs
- prevent potential overflows in indirect message handling
- fix copy bug in indirect message introduced in v4

Changes since v3:
- reintroduce firmare v1.0 support in partinfo
- fix a possible TOC/TOU issue in indirect message handling
- typos and small fixes

Changes since v2:
- Rework partition_info_get implementation
- Taint Xen and display a message when VM to VM is enabled
- Various fixes explained in each patch

Changes since v1 (rfc):
- add a tee command line parameter
- use IS_ENABLED instead of ifdef when possible
- rebase on latest staging


Bertrand Marquis (6):
  xen/arm: Create tee command line parameter
  xen/arm: ffa: Rework partinfo_get implementation
  xen/arm: ffa: Introduce VM to VM support
  xen/arm: ffa: Add buffer full notification support
  xen/arm: ffa: Add indirect message between VM
  xen/arm: ffa: Enable VM to VM without firmware

 docs/misc/xen-command-line.pandoc  |  14 ++
 xen/arch/arm/include/asm/tee/tee.h |   4 +
 xen/arch/arm/tee/Kconfig           |  11 ++
 xen/arch/arm/tee/ffa.c             | 112 ++++++++---
 xen/arch/arm/tee/ffa_msg.c         | 117 ++++++++++--
 xen/arch/arm/tee/ffa_notif.c       | 140 ++++++++------
 xen/arch/arm/tee/ffa_partinfo.c    | 292 ++++++++++++++++++++---------
 xen/arch/arm/tee/ffa_private.h     | 158 +++++++++++++---
 xen/arch/arm/tee/tee.c             |  32 ++++
 9 files changed, 665 insertions(+), 215 deletions(-)

-- 
2.47.1



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From: Bertrand Marquis 
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Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Volodymyr Babchuk ,
	Jens Wiklander ,
	Julien Grall 
Subject: [PATCH v8 1/6] xen/arm: Create tee command line parameter
Date: Mon, 11 Aug 2025 15:34:57 +0200
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Add a new command line parameter "tee=" to be used to explicitly select
what tee mediator is to be used by Xen and fail if it does not exist
or the probe function for it failed.

Without specifying which tee is to be used, Xen will use the first one
for which the probe function succeeds which depends on the order of the
mediator list which depends on the compiler.
Using the command line argument, it is now possible to explicit request
a specific TEE mediator and panic on boot if it is not available.

Signed-off-by: Bertrand Marquis 
Reviewed-by: Jens Wiklander 
Acked-by: Julien Grall 
---
Changes in v8:
- None
Changes in v7:
- Add Julien A-b
Changes in v6:
- Add Jens R-b
Changes in v5:
- Typo fix and rewording in command line doc (Julien)
- fix include order in tee.c (Julien)
- use a local bool instead of retesting the string each time in tee_init
  (Julien)
Changes in v4:
- None
Changes in v3:
- Properly classify tee as arm specific (Jan)
Changes in v2:
- Patch introduced to add a command line selection of the TEE
---
 docs/misc/xen-command-line.pandoc  | 14 +++++++++++++
 xen/arch/arm/include/asm/tee/tee.h |  4 ++++
 xen/arch/arm/tee/tee.c             | 32 ++++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 6865a61220ca..ad5800ac45a8 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2655,6 +2655,20 @@ Specify the per-cpu trace buffer size in pages.
 
 Flag to enable TSC deadline as the APIC timer mode.
 
+### tee (arm)
+> `= `
+
+Specify the TEE mediator to be probed and use.
+
+The default behaviour is to probe all TEEs supported by Xen and use
+the first one successfully probed. When this parameter is passed, Xen will
+probe only the TEE mediator passed as argument and boot will fail if this
+mediator is not properly probed or if the requested TEE is not supported by
+Xen.
+
+This parameter can be set to `optee` or `ffa` if the corresponding mediators
+are compiled in.
+
 ### tevt_mask
 > `= `
 
diff --git a/xen/arch/arm/include/asm/tee/tee.h b/xen/arch/arm/include/asm/tee/tee.h
index 0169fd746bcd..15d664e28dce 100644
--- a/xen/arch/arm/include/asm/tee/tee.h
+++ b/xen/arch/arm/include/asm/tee/tee.h
@@ -55,6 +55,9 @@ struct tee_mediator_desc {
     /* Printable name of the TEE. */
     const char *name;
 
+    /* Command line name of the TEE (to be used with tee= cmdline option) */
+    const char *cmdline_name;
+
     /* Mediator callbacks as described above. */
     const struct tee_mediator_ops *ops;
 
@@ -77,6 +80,7 @@ void tee_free_domain_ctx(struct domain *d);
 static const struct tee_mediator_desc __tee_desc_##_name __used     \
 __section(".teemediator.info") = {                                  \
     .name = _namestr,                                               \
+    .cmdline_name = #_name,                                         \
     .ops = _ops,                                                    \
     .tee_type = _type                                               \
 }
diff --git a/xen/arch/arm/tee/tee.c b/xen/arch/arm/tee/tee.c
index 3f65e45a7892..8501443c8e57 100644
--- a/xen/arch/arm/tee/tee.c
+++ b/xen/arch/arm/tee/tee.c
@@ -18,6 +18,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -25,6 +26,10 @@
 extern const struct tee_mediator_desc _steemediator[], _eteemediator[];
 static const struct tee_mediator_desc __read_mostly *cur_mediator;
 
+/* Select the TEE mediator using a name on command line. */
+static char __initdata opt_mediator[16] = "";
+string_param("tee", opt_mediator);
+
 /*
  * TODO: Add function to alter Dom0 DTB, so we can properly describe
  * present TEE.
@@ -80,15 +85,42 @@ uint16_t tee_get_type(void)
 static int __init tee_init(void)
 {
     const struct tee_mediator_desc *desc;
+    bool select_mediator = strcmp(opt_mediator, "");
+
+    if ( select_mediator )
+        printk(XENLOG_INFO "TEE Mediator %s selected from command line\n",
+               opt_mediator);
 
+    /*
+     * When a specific TEE is selected using the 'tee=' command line
+     * argument, we panic if the probe fails or if the requested TEE is not
+     * supported.
+     */
     for ( desc = _steemediator; desc != _eteemediator; desc++ )
     {
+        if ( select_mediator &&
+             strncmp(opt_mediator, desc->cmdline_name, sizeof(opt_mediator)) )
+            continue;
+
         if ( desc->ops->probe() )
         {
             printk(XENLOG_INFO "Using TEE mediator for %s\n", desc->name);
             cur_mediator = desc;
             return 0;
         }
+        else if ( select_mediator )
+        {
+            panic("TEE mediator %s from command line probe failed\n",
+                  opt_mediator);
+            return -EFAULT;
+        }
+    }
+
+    if ( select_mediator )
+    {
+        panic("TEE Mediator %s from command line not supported\n",
+              opt_mediator);
+        return -EINVAL;
     }
 
     return 0;
-- 
2.47.1



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	Stefano Stabellini ,
	Julien Grall ,
	Michal Orzel ,
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	Julien Grall 
Subject: [PATCH v8 2/6] xen/arm: ffa: Rework partinfo_get implementation
Date: Mon, 11 Aug 2025 15:34:58 +0200
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This patch is in preparation for VM to VM support in order to do the
changes on the SP handling part of partinfo_get before adding support
for the VM part.

This patches is doing the following changes:
- split partinfo_get into 3 functions to have the locking handling and
  proper exit on error handled more clearly
- add some potential overflow checks to validate the offset and sizes
  passed by the VM on partinfo call.
- Introduce a maximum number of SPs (for now set to 64) to prevent
  holding the CPU for too long in case there would be a lot of
  partitions in the secure world. The limit currently set is thought to
  be realistic for most use cases as 64 secure partitions is a very high
  number compared to current seen usage (more 3 or 4).
- fix include ordering in ffa_private.h to be in alphabetic order

Signed-off-by: Bertrand Marquis 
Reviewed-by: Jens Wiklander 
Acked-by: Julien Grall 
---
Changes in v8:
- None
Changes in v7:
- add Julien A-b
Changes in v6:
- add missing empty line before ffa_handle_partition_info_get
- add Jens R-b
Changes in v5:
- patch added
---
 xen/arch/arm/tee/ffa_partinfo.c | 202 +++++++++++++++++++-------------
 xen/arch/arm/tee/ffa_private.h  |  18 ++-
 2 files changed, 132 insertions(+), 88 deletions(-)

diff --git a/xen/arch/arm/tee/ffa_partinfo.c b/xen/arch/arm/tee/ffa_partinfo.c
index c0510ceb8338..dfa0b23eaf38 100644
--- a/xen/arch/arm/tee/ffa_partinfo.c
+++ b/xen/arch/arm/tee/ffa_partinfo.c
@@ -63,9 +63,96 @@ static int32_t ffa_partition_info_get(uint32_t *uuid, uint32_t flags,
     return ret;
 }
 
-void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
+static int32_t ffa_get_sp_count(uint32_t *uuid, uint32_t *sp_count)
+{
+    uint32_t src_size;
+
+    return ffa_partition_info_get(uuid, FFA_PARTITION_INFO_GET_COUNT_FLAG,
+                                  sp_count, &src_size);
+}
+
+static int32_t ffa_get_sp_partinfo(uint32_t *uuid, uint32_t *sp_count,
+                                   void *dst_buf, void *end_buf,
+                                   uint32_t dst_size)
 {
     int32_t ret;
+    uint32_t src_size, real_sp_count;
+    void *src_buf = ffa_rx;
+    uint32_t count = 0;
+
+    /* Do we have a RX buffer with the SPMC */
+    if ( !ffa_rx )
+        return FFA_RET_DENIED;
+
+    /* We need to use the RX buffer to receive the list */
+    spin_lock(&ffa_rx_buffer_lock);
+
+    ret = ffa_partition_info_get(uuid, 0, &real_sp_count, &src_size);
+    if ( ret )
+        goto out;
+
+    /* We now own the RX buffer */
+
+    /* Validate the src_size we got */
+    if ( src_size < sizeof(struct ffa_partition_info_1_0) ||
+         src_size >= FFA_PAGE_SIZE )
+    {
+        ret = FFA_RET_NOT_SUPPORTED;
+        goto out_release;
+    }
+
+    /*
+     * Limit the maximum time we hold the CPU by limiting the number of SPs.
+     * We just ignore the extra ones as this is tested during init in
+     * ffa_partinfo_init so the only possible reason is SP have been added
+     * since boot.
+     */
+    if ( real_sp_count > FFA_MAX_NUM_SP )
+        real_sp_count = FFA_MAX_NUM_SP;
+
+    /* Make sure the data fits in our buffer */
+    if ( real_sp_count > (FFA_RXTX_PAGE_COUNT * FFA_PAGE_SIZE) / src_size )
+    {
+        ret = FFA_RET_NOT_SUPPORTED;
+        goto out_release;
+    }
+
+    for ( uint32_t sp_num = 0; sp_num < real_sp_count; sp_num++ )
+    {
+        struct ffa_partition_info_1_1 *fpi = src_buf;
+
+        /* filter out SP not following bit 15 convention if any */
+        if ( FFA_ID_IS_SECURE(fpi->id) )
+        {
+            if ( dst_buf > (end_buf - dst_size) )
+            {
+                ret = FFA_RET_NO_MEMORY;
+                goto out_release;
+            }
+
+            memcpy(dst_buf, src_buf, MIN(src_size, dst_size));
+            if ( dst_size > src_size )
+                memset(dst_buf + src_size, 0, dst_size - src_size);
+
+            dst_buf += dst_size;
+            count++;
+        }
+
+        src_buf += src_size;
+    }
+
+    *sp_count = count;
+
+out_release:
+    ffa_hyp_rx_release();
+out:
+    spin_unlock(&ffa_rx_buffer_lock);
+    return ret;
+}
+
+void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
+{
+    int32_t ret = FFA_RET_OK;
     struct domain *d = current->domain;
     struct ffa_ctx *ctx = d->arch.tee;
     uint32_t flags = get_user_reg(regs, 5);
@@ -75,8 +162,8 @@ void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
         get_user_reg(regs, 3),
         get_user_reg(regs, 4),
     };
-    uint32_t src_size, dst_size;
-    void *dst_buf;
+    uint32_t dst_size = 0;
+    void *dst_buf, *end_buf;
     uint32_t ffa_sp_count = 0;
 
     /*
@@ -89,31 +176,26 @@ void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
     else
         dst_size = sizeof(struct ffa_partition_info_1_1);
 
-    /*
-     * FF-A v1.0 has w5 MBZ while v1.1 allows
-     * FFA_PARTITION_INFO_GET_COUNT_FLAG to be non-zero.
-     *
-     * FFA_PARTITION_INFO_GET_COUNT is only using registers and not the
-     * rxtx buffer so do the partition_info_get directly.
-     */
-    if ( flags == FFA_PARTITION_INFO_GET_COUNT_FLAG &&
-         ctx->guest_vers == FFA_VERSION_1_1 )
+    /* Only count requested */
+    if ( flags )
     {
+        /*
+         * FF-A v1.0 has w5 MBZ while v1.1 allows
+         * FFA_PARTITION_INFO_GET_COUNT_FLAG to be non-zero.
+         */
+        if ( ctx->guest_vers == FFA_VERSION_1_0 ||
+                flags != FFA_PARTITION_INFO_GET_COUNT_FLAG )
+        {
+            ret = FFA_RET_INVALID_PARAMETERS;
+            goto out;
+        }
+
         if ( ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) )
-            ret = ffa_partition_info_get(uuid, flags, &ffa_sp_count,
-                                        &src_size);
-        else
-            ret = FFA_RET_OK;
+            ret = ffa_get_sp_count(uuid, &ffa_sp_count);
 
         goto out;
     }
 
-    if ( flags )
-    {
-        ret = FFA_RET_INVALID_PARAMETERS;
-        goto out;
-    }
-
     if ( !ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) )
     {
         /* Just give an empty partition list to the caller */
@@ -121,80 +203,33 @@ void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
         goto out;
     }
 
+    /* Get the RX buffer to write the list of partitions */
     ret = ffa_rx_acquire(d);
     if ( ret != FFA_RET_OK )
         goto out;
 
     dst_buf = ctx->rx;
+    end_buf = ctx->rx + ctx->page_count * FFA_PAGE_SIZE;
 
-    if ( !ffa_rx )
-    {
-        ret = FFA_RET_DENIED;
-        goto out_rx_release;
-    }
-
-    spin_lock(&ffa_rx_buffer_lock);
-
-    ret = ffa_partition_info_get(uuid, 0, &ffa_sp_count, &src_size);
-
-    if ( ret )
-        goto out_rx_hyp_unlock;
+    /* An entry should be smaller than a page */
+    BUILD_BUG_ON(sizeof(struct ffa_partition_info_1_1) > FFA_PAGE_SIZE);
 
     /*
-     * ffa_partition_info_get() succeeded so we now own the RX buffer we
-     * share with the SPMC. We must give it back using ffa_hyp_rx_release()
-     * once we've copied the content.
+     * Check for overflow and that we can at least store one entry.
+     * page_count cannot be 0 so we have at least one page.
      */
-
-    /* we cannot have a size smaller than 1.0 structure */
-    if ( src_size < sizeof(struct ffa_partition_info_1_0) )
-    {
-        ret = FFA_RET_NOT_SUPPORTED;
-        goto out_rx_hyp_release;
-    }
-
-    if ( ctx->page_count * FFA_PAGE_SIZE < ffa_sp_count * dst_size )
+    if ( dst_buf >= end_buf || dst_buf > (end_buf - dst_size) )
     {
-        ret = FFA_RET_NO_MEMORY;
-        goto out_rx_hyp_release;
+        ret = FFA_RET_INVALID_PARAMETERS;
+        goto out_rx_release;
     }
 
-    if ( ffa_sp_count > 0 )
-    {
-        uint32_t n, n_limit = ffa_sp_count;
-        void *src_buf = ffa_rx;
-
-        /* copy the secure partitions info */
-        for ( n = 0; n < n_limit; n++ )
-        {
-            struct ffa_partition_info_1_1 *fpi = src_buf;
-
-            /* filter out SP not following bit 15 convention if any */
-            if ( FFA_ID_IS_SECURE(fpi->id) )
-            {
-                memcpy(dst_buf, src_buf, dst_size);
-                dst_buf += dst_size;
-            }
-            else
-                ffa_sp_count--;
+    ret = ffa_get_sp_partinfo(uuid, &ffa_sp_count, dst_buf, end_buf,
+                              dst_size);
 
-            src_buf += src_size;
-        }
-    }
 
-out_rx_hyp_release:
-    ffa_hyp_rx_release();
-out_rx_hyp_unlock:
-    spin_unlock(&ffa_rx_buffer_lock);
 out_rx_release:
-    /*
-     * The calling VM RX buffer only contains data to be used by the VM if the
-     * call was successful, in which case the VM has to release the buffer
-     * once it has used the data.
-     * If something went wrong during the call, we have to release the RX
-     * buffer back to the SPMC as the VM will not do it.
-     */
-    if ( ret != FFA_RET_OK )
+    if ( ret )
         ffa_rx_release(d);
 out:
     if ( ret )
@@ -353,9 +388,10 @@ bool ffa_partinfo_init(void)
         goto out;
     }
 
-    if ( count >= UINT16_MAX )
+    if ( count >= FFA_MAX_NUM_SP )
     {
-        printk(XENLOG_ERR "ffa: Impossible number of SPs: %u\n", count);
+        printk(XENLOG_ERR "ffa: More SPs than the maximum supported: %u - %u\n",
+               count, FFA_MAX_NUM_SP);
         goto out;
     }
 
diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h
index c4cd65538908..0a9c1082db28 100644
--- a/xen/arch/arm/tee/ffa_private.h
+++ b/xen/arch/arm/tee/ffa_private.h
@@ -6,15 +6,15 @@
 #ifndef __FFA_PRIVATE_H__
 #define __FFA_PRIVATE_H__
 
+#include 
 #include 
-#include 
-#include 
-#include 
 #include 
-#include 
+#include 
 #include 
+#include 
+#include 
 #include 
-#include 
+#include 
 
 /* Error codes */
 #define FFA_RET_OK                      0
@@ -108,6 +108,14 @@
  */
 #define FFA_CTX_TEARDOWN_DELAY          SECONDS(1)
 
+/*
+ * The maximum number of Secure partitions we support for partinfo_get.
+ * This prevents holding the CPU during potentially to long time during
+ * a partinfo_get call. Value choosen seems realistic for any configuration
+ * but can be incremented here if needed.
+ */
+#define FFA_MAX_NUM_SP                  64
+
 /*
  * We rely on the convention suggested but not mandated by the FF-A
  * specification that secure world endpoint identifiers have the bit 15
-- 
2.47.1



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From: Bertrand Marquis 
To: xen-devel@lists.xenproject.org
Cc: Volodymyr Babchuk ,
	Stefano Stabellini ,
	Julien Grall ,
	Michal Orzel ,
	Jens Wiklander ,
	Julien Grall 
Subject: [PATCH v8 4/6] xen/arm: ffa: Add buffer full notification support
Date: Mon, 11 Aug 2025 15:35:00 +0200
Message-ID: <67db91dfbde26dd777b1575dda9bc83b0a676193.1754899329.git.bertrand.marquis@arm.com>
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Add support to raise a Rx buffer full notification to a VM.
This function will be used for indirect message support between VM and
is only activated if CONFIG_FFA_VM_TO_VM is selected.

Even if there are 32 framework notifications possible, right now only
one is defined so the implementation is simplified to only handle the
buffer full notification using a boolean. If other framework
notifications have to be supported one day, the design will have to be
modified to handle it properly.

Signed-off-by: Bertrand Marquis 
Reviewed-by: Jens Wiklander 
Acked-by: Julien Grall 
---
Changes in v8:
- None
Changes in v7:
- Add Julien A-b
Changes in v6:
- None
Changes in v5:
- None
Changes in v4:
- Add Jens R-b
Changes in v3:
- introduce a vm_pending boolean to track if VM notifications are
  pending and allow to decorelate pending secure notifications from
  pending vm ones
- remove ifdef around boolean entries for notifications and make use of
  IS_ENABLED instead of ifdefs when possible
- Fix notification number signaled to VMs for buffer full to use the
  proper GUEST_FFA_NOTIF_PEND_INTR_ID instead of the identifier received
  from the SPMC.
- Move back into this patch ffa_private.h part which was wrongly in the
  patch for indirect messages between VM
Changes in v2:
- Switch ifdef to IS_ENABLED when possible
---
 xen/arch/arm/tee/ffa_notif.c   | 36 ++++++++++++++++++++++++++++------
 xen/arch/arm/tee/ffa_private.h | 23 +++++++++++++++++++++-
 2 files changed, 52 insertions(+), 7 deletions(-)

diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c
index 00efaf8f7353..f6df2f15bb00 100644
--- a/xen/arch/arm/tee/ffa_notif.c
+++ b/xen/arch/arm/tee/ffa_notif.c
@@ -69,6 +69,7 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs)
 {
     struct domain *d = current->domain;
     struct ffa_ctx *ctx = d->arch.tee;
+    bool notif_pending;
 
     if ( !notif_enabled )
     {
@@ -76,7 +77,11 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs)
         return;
     }
 
-    if ( test_and_clear_bool(ctx->notif.secure_pending) )
+    notif_pending = test_and_clear_bool(ctx->notif.secure_pending);
+    if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) )
+        notif_pending |= test_and_clear_bool(ctx->notif.vm_pending);
+
+    if ( notif_pending )
     {
         /* A pending global notification for the guest */
         ffa_set_regs(regs, FFA_SUCCESS_64, 0,
@@ -93,6 +98,7 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs)
 void ffa_handle_notification_get(struct cpu_user_regs *regs)
 {
     struct domain *d = current->domain;
+    struct ffa_ctx *ctx = d->arch.tee;
     uint32_t recv = get_user_reg(regs, 1);
     uint32_t flags = get_user_reg(regs, 2);
     uint32_t w2 = 0;
@@ -132,11 +138,7 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs)
          */
         if ( ( flags  & FFA_NOTIF_FLAG_BITMAP_SP ) &&
              ( flags & FFA_NOTIF_FLAG_BITMAP_SPM ) )
-        {
-                struct ffa_ctx *ctx = d->arch.tee;
-
-                ACCESS_ONCE(ctx->notif.secure_pending) = false;
-        }
+            ACCESS_ONCE(ctx->notif.secure_pending) = false;
 
         arm_smccc_1_2_smc(&arg, &resp);
         e = ffa_get_ret_code(&resp);
@@ -156,6 +158,14 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs)
             w6 = resp.a6;
     }
 
+    if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) &&
+          flags & FFA_NOTIF_FLAG_BITMAP_HYP &&
+          test_and_clear_bool(ctx->notif.buff_full_pending) )
+    {
+        ACCESS_ONCE(ctx->notif.vm_pending) = false;
+        w7 = FFA_NOTIF_RX_BUFFER_FULL;
+    }
+
     ffa_set_regs(regs, FFA_SUCCESS_32, 0, w2, w3, w4, w5, w6, w7);
 }
 
@@ -178,6 +188,20 @@ int ffa_handle_notification_set(struct cpu_user_regs *regs)
                            bitmap_hi);
 }
 
+#ifdef CONFIG_FFA_VM_TO_VM
+void ffa_raise_rx_buffer_full(struct domain *d)
+{
+    struct ffa_ctx *ctx = d->arch.tee;
+
+    if ( !ctx )
+        return;
+
+    ACCESS_ONCE(ctx->notif.buff_full_pending) = true;
+    if ( !test_and_set_bool(ctx->notif.vm_pending) )
+        vgic_inject_irq(d, d->vcpu[0], GUEST_FFA_NOTIF_PEND_INTR_ID, true);
+}
+#endif
+
 /*
  * Extract a 16-bit ID (index n) from the successful return value from
  * FFA_NOTIFICATION_INFO_GET_64 or FFA_NOTIFICATION_INFO_GET_32. IDs are
diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h
index 5cb2b5171419..6dbdb200d840 100644
--- a/xen/arch/arm/tee/ffa_private.h
+++ b/xen/arch/arm/tee/ffa_private.h
@@ -218,6 +218,8 @@
 #define FFA_NOTIF_INFO_GET_ID_COUNT_SHIFT   7
 #define FFA_NOTIF_INFO_GET_ID_COUNT_MASK    0x1F
 
+#define FFA_NOTIF_RX_BUFFER_FULL        BIT(0, U)
+
 /* Feature IDs used with FFA_FEATURES */
 #define FFA_FEATURE_NOTIF_PEND_INTR     0x1U
 #define FFA_FEATURE_SCHEDULE_RECV_INTR  0x2U
@@ -303,9 +305,20 @@ struct ffa_mem_region {
 struct ffa_ctx_notif {
     /*
      * True if domain is reported by FFA_NOTIFICATION_INFO_GET to have
-     * pending global notifications.
+     * pending notifications from the secure world.
      */
     bool secure_pending;
+
+    /*
+     * True if domain is reported by FFA_NOTIFICATION_INFO_GET to have
+     * pending notifications from VMs (including framework ones).
+     */
+    bool vm_pending;
+
+    /*
+     * True if domain has buffer full notification pending
+     */
+    bool buff_full_pending;
 };
 
 struct ffa_ctx {
@@ -419,6 +432,14 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs);
 void ffa_handle_notification_get(struct cpu_user_regs *regs);
 int ffa_handle_notification_set(struct cpu_user_regs *regs);
 
+#ifdef CONFIG_FFA_VM_TO_VM
+void ffa_raise_rx_buffer_full(struct domain *d);
+#else
+static inline void ffa_raise_rx_buffer_full(struct domain *d)
+{
+}
+#endif
+
 void ffa_handle_msg_send_direct_req(struct cpu_user_regs *regs, uint32_t fid);
 int32_t ffa_handle_msg_send2(struct cpu_user_regs *regs);
 
-- 
2.47.1



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To: xen-devel@lists.xenproject.org
Cc: Volodymyr Babchuk ,
	Stefano Stabellini ,
	Julien Grall ,
	Michal Orzel ,
	Jens Wiklander ,
	Julien Grall 
Subject: [PATCH v8 3/6] xen/arm: ffa: Introduce VM to VM support
Date: Mon, 11 Aug 2025 15:34:59 +0200
Message-ID: <12f24629ed75b638d9307cc549ecde46d225c5c1.1754899329.git.bertrand.marquis@arm.com>
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Create a CONFIG_FFA_VM_TO_VM parameter to activate FFA communication
between VMs.
When activated list VMs in the system with FF-A support in part_info_get.

When VM to VM is activated, Xen will be tainted as Insecure and a
message is displayed to the user during the boot as there is no
filtering of VMs in FF-A so any VM can communicate or see any other VM
in the system.

WARNING: There is no filtering for now and all VMs are listed !!

This patch is reorganizing the ffa_ctx structure to make clear which
lock is protecting what parts.

This patch is introducing a chain list of the ffa_ctx with a FFA Version
negotiated allowing to create the partinfo results for VMs in parallel
by using rwlock which only ensure addition/removal of entries are
protected.

Signed-off-by: Bertrand Marquis 
Reviewed-by: Jens Wiklander 
Acked-by: Julien Grall 
---
Changes in v8;
- fix typo: negociat.. to negotiat..
- use LIST_HEAD and DEFINE_RWLOCK for declarations (Julien)
- add Jens R-b
- add Julien A-b
Changes in v7:
- protect ffa_ctx list with a rw lock to allow several partinfo_get in
  parallel but protect adding/removing entries.
Changes in v6:
- remove ACCESS_ONCE for guest_vers access and take the context lock
  before modifying it
- move guest_vers in context declaration to fields protected by the
  context lock and add a comment to state that lock in only needed when
  modifying it
Changes in v5:
- remove invalid comment about 1.1 firmware support
- rename variables from d and dom to curr_d and dest_d (Julien)
- add a TODO in the code for potential holding for long of the CPU
  (Julien)
- use an atomic global variable to store the number of VMs instead of
  recomputing the value each time (Julien)
- add partinfo information in ffa_ctx (id, cpus and 64bit) and create a
  chain list of ctx. Use this chain list to create the partinfo result
  without holding a global lock to prevent concurrency issues.
- Move some changes in a preparation patch modifying partinfo for sps to
  reduce this patch size and make the review easier
Changes in v4:
- properly handle SPMC version 1.0 header size case in partinfo_get
- switch to local counting variables instead of *pointer += 1 form
- coding style issue with missing spaces in if ()
Changes in v3:
- break partinfo_get in several sub functions to make the implementation
  easier to understand and lock handling easier
- rework implementation to check size along the way and prevent previous
  implementation limits which had to check that the number of VMs or SPs
  did not change
- taint Xen as INSECURE when VM to VM is enabled
Changes in v2:
- Switch ifdef to IS_ENABLED
- dom was not switched to d as requested by Jan because there is already
  a variable d pointing to the current domain and it must not be
  shadowed.
---
 xen/arch/arm/tee/Kconfig        |  11 +++
 xen/arch/arm/tee/ffa.c          |  49 ++++++++++++-
 xen/arch/arm/tee/ffa_partinfo.c | 100 ++++++++++++++++++++++++---
 xen/arch/arm/tee/ffa_private.h  | 117 ++++++++++++++++++++++++++------
 4 files changed, 245 insertions(+), 32 deletions(-)

diff --git a/xen/arch/arm/tee/Kconfig b/xen/arch/arm/tee/Kconfig
index c5b0f88d7522..88a4c4c99154 100644
--- a/xen/arch/arm/tee/Kconfig
+++ b/xen/arch/arm/tee/Kconfig
@@ -28,5 +28,16 @@ config FFA
 
 	  [1] https://developer.arm.com/documentation/den0077/latest
 
+config FFA_VM_TO_VM
+    bool "Enable FF-A between VMs (UNSUPPORTED)" if UNSUPPORTED
+    default n
+    depends on FFA
+    help
+      This option enables to use FF-A between VMs.
+      This is experimental and there is no access control so any
+      guest can communicate with any other guest.
+
+      If unsure, say N.
+
 endmenu
 
diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c
index 3bbdd7168a6b..0eb6a0bda5fb 100644
--- a/xen/arch/arm/tee/ffa.c
+++ b/xen/arch/arm/tee/ffa.c
@@ -118,10 +118,18 @@ void *ffa_tx __read_mostly;
 DEFINE_SPINLOCK(ffa_rx_buffer_lock);
 DEFINE_SPINLOCK(ffa_tx_buffer_lock);
 
+LIST_HEAD(ffa_ctx_head);
+/* RW Lock to protect addition/removal and reading in ffa_ctx_head */
+DEFINE_RWLOCK(ffa_ctx_list_rwlock);
+
+#ifdef CONFIG_FFA_VM_TO_VM
+atomic_t ffa_vm_count;
+#endif
 
 /* Used to track domains that could not be torn down immediately. */
 static struct timer ffa_teardown_timer;
-static struct list_head ffa_teardown_head;
+
+static LIST_HEAD(ffa_teardown_head);
 static DEFINE_SPINLOCK(ffa_teardown_lock);
 
 static bool ffa_get_version(uint32_t *vers)
@@ -151,6 +159,7 @@ static void handle_version(struct cpu_user_regs *regs)
     struct domain *d = current->domain;
     struct ffa_ctx *ctx = d->arch.tee;
     uint32_t vers = get_user_reg(regs, 1);
+    uint32_t old_vers;
 
     /*
      * Guest will use the version it requested if it is our major and minor
@@ -160,10 +169,23 @@ static void handle_version(struct cpu_user_regs *regs)
      */
     if ( FFA_VERSION_MAJOR(vers) == FFA_MY_VERSION_MAJOR )
     {
+        spin_lock(&ctx->lock);
+        old_vers = ctx->guest_vers;
+
         if ( FFA_VERSION_MINOR(vers) > FFA_MY_VERSION_MINOR )
             ctx->guest_vers = FFA_MY_VERSION;
         else
             ctx->guest_vers = vers;
+        spin_unlock(&ctx->lock);
+
+        if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !old_vers )
+        {
+            /* One more VM with FF-A support available */
+            inc_ffa_vm_count();
+            write_lock(&ffa_ctx_list_rwlock);
+            list_add_tail(&ctx->ctx_list, &ffa_ctx_head);
+            write_unlock(&ffa_ctx_list_rwlock);
+        }
     }
     ffa_set_regs(regs, FFA_MY_VERSION, 0, 0, 0, 0, 0, 0, 0);
 }
@@ -345,6 +367,10 @@ static int ffa_domain_init(struct domain *d)
     ctx->teardown_d = d;
     INIT_LIST_HEAD(&ctx->shm_list);
 
+    ctx->ffa_id = ffa_get_vm_id(d);
+    ctx->num_vcpus = d->max_vcpus;
+    ctx->is_64bit = is_64bit_domain(d);
+
     /*
      * ffa_domain_teardown() will be called if ffa_domain_init() returns an
      * error, so no need for cleanup in this function.
@@ -421,6 +447,14 @@ static int ffa_domain_teardown(struct domain *d)
     if ( !ctx )
         return 0;
 
+    if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) && ctx->guest_vers )
+    {
+        dec_ffa_vm_count();
+        write_lock(&ffa_ctx_list_rwlock);
+        list_del(&ctx->ctx_list);
+        write_unlock(&ffa_ctx_list_rwlock);
+    }
+
     ffa_rxtx_domain_destroy(d);
     ffa_notif_domain_destroy(d);
 
@@ -464,6 +498,18 @@ static bool ffa_probe(void)
     printk(XENLOG_INFO "ARM FF-A Mediator version %u.%u\n",
            FFA_MY_VERSION_MAJOR, FFA_MY_VERSION_MINOR);
 
+    if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) )
+    {
+        /*
+         * When FFA VM to VM is enabled, the current implementation does not
+         * offer any way to limit which VM can communicate with which VM using
+         * FF-A.
+         * Signal this in the xen console and taint the system as insecure.
+         * TODO: Introduce a solution to limit what a VM can do through FFA.
+         */
+        printk(XENLOG_ERR "ffa: VM to VM is enabled, system is insecure !!\n");
+        add_taint(TAINT_MACHINE_INSECURE);
+    }
     /*
      * psci_init_smccc() updates this value with what's reported by EL-3
      * or secure world.
@@ -537,7 +583,6 @@ static bool ffa_probe(void)
         goto err_rxtx_destroy;
 
     ffa_notif_init();
-    INIT_LIST_HEAD(&ffa_teardown_head);
     init_timer(&ffa_teardown_timer, ffa_teardown_timer_callback, NULL, 0);
 
     return true;
diff --git a/xen/arch/arm/tee/ffa_partinfo.c b/xen/arch/arm/tee/ffa_partinfo.c
index dfa0b23eaf38..fa56b1587e3b 100644
--- a/xen/arch/arm/tee/ffa_partinfo.c
+++ b/xen/arch/arm/tee/ffa_partinfo.c
@@ -150,6 +150,73 @@ out:
     return ret;
 }
 
+static int32_t ffa_get_vm_partinfo(uint32_t *vm_count, void *dst_buf,
+                                   void *end_buf, uint32_t dst_size)
+{
+    struct ffa_ctx *curr_ctx = current->domain->arch.tee;
+    struct ffa_ctx *dest_ctx;
+    uint32_t count = 0;
+    int32_t ret = FFA_RET_OK;
+
+    /*
+     * There could potentially be a lot of VMs in the system and we could
+     * hold the CPU for long here.
+     * Right now there is no solution in FF-A specification to split
+     * the work in this case.
+     * TODO: Check how we could delay the work or have preemption checks.
+     */
+    read_lock(&ffa_ctx_list_rwlock);
+    list_for_each_entry(dest_ctx, &ffa_ctx_head, ctx_list)
+    {
+        /*
+         * Do not include an entry for the caller VM as the spec is not
+         * clearly mandating it and it is not supported by Linux.
+         */
+        if ( dest_ctx != curr_ctx )
+        {
+            /*
+             * We do not have UUID info for VMs so use
+             * the 1.0 structure so that we set UUIDs to
+             * zero using memset
+             */
+            struct ffa_partition_info_1_0 info;
+
+            if  ( dst_buf > (end_buf - dst_size) )
+            {
+                ret = FFA_RET_NO_MEMORY;
+                goto out;
+            }
+
+            /*
+             * Context might has been removed since we go it or being removed
+             * right now so we might return information for a VM not existing
+             * anymore. This is acceptable as we return a view of the system
+             * which could change at any time.
+             */
+            info.id = dest_ctx->ffa_id;
+            info.execution_context = dest_ctx->num_vcpus;
+            info.partition_properties = FFA_PART_VM_PROP;
+            if ( dest_ctx->is_64bit )
+                info.partition_properties |= FFA_PART_PROP_AARCH64_STATE;
+
+            memcpy(dst_buf, &info, MIN(sizeof(info), dst_size));
+
+            if ( dst_size > sizeof(info) )
+                memset(dst_buf + sizeof(info), 0,
+                       dst_size - sizeof(info));
+
+            dst_buf += dst_size;
+            count++;
+        }
+    }
+    *vm_count = count;
+
+out:
+    read_unlock(&ffa_ctx_list_rwlock);
+
+    return ret;
+}
+
 void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
 {
     int32_t ret = FFA_RET_OK;
@@ -164,7 +231,7 @@ void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
     };
     uint32_t dst_size = 0;
     void *dst_buf, *end_buf;
-    uint32_t ffa_sp_count = 0;
+    uint32_t ffa_vm_count = 0, ffa_sp_count = 0;
 
     /*
      * If the guest is v1.0, he does not get back the entry size so we must
@@ -191,15 +258,18 @@ void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
         }
 
         if ( ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) )
+        {
             ret = ffa_get_sp_count(uuid, &ffa_sp_count);
+            if ( ret )
+                goto out;
+        }
 
-        goto out;
-    }
+        /*
+         * Do not count the caller VM as the spec is not clearly mandating it
+         * and it is not supported by Linux.
+         */
+        ffa_vm_count = get_ffa_vm_count() - 1;
 
-    if ( !ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) )
-    {
-        /* Just give an empty partition list to the caller */
-        ret = FFA_RET_OK;
         goto out;
     }
 
@@ -224,9 +294,19 @@ void ffa_handle_partition_info_get(struct cpu_user_regs *regs)
         goto out_rx_release;
     }
 
-    ret = ffa_get_sp_partinfo(uuid, &ffa_sp_count, dst_buf, end_buf,
-                              dst_size);
+    if ( ffa_fw_supports_fid(FFA_PARTITION_INFO_GET) )
+    {
+        ret = ffa_get_sp_partinfo(uuid, &ffa_sp_count, dst_buf, end_buf,
+                                  dst_size);
+
+        if ( ret )
+            goto out_rx_release;
+
+        dst_buf += ffa_sp_count * dst_size;
+    }
 
+    if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) )
+        ret = ffa_get_vm_partinfo(&ffa_vm_count, dst_buf, end_buf, dst_size);
 
 out_rx_release:
     if ( ret )
@@ -235,7 +315,7 @@ out:
     if ( ret )
         ffa_set_regs_error(regs, ret);
     else
-        ffa_set_regs_success(regs, ffa_sp_count, dst_size);
+        ffa_set_regs_success(regs, ffa_sp_count + ffa_vm_count, dst_size);
 }
 
 static int32_t ffa_direct_req_send_vm(uint16_t sp_id, uint16_t vm_id,
diff --git a/xen/arch/arm/tee/ffa_private.h b/xen/arch/arm/tee/ffa_private.h
index 0a9c1082db28..5cb2b5171419 100644
--- a/xen/arch/arm/tee/ffa_private.h
+++ b/xen/arch/arm/tee/ffa_private.h
@@ -195,6 +195,18 @@
  */
 #define FFA_PARTITION_INFO_GET_COUNT_FLAG BIT(0, U)
 
+/*
+ * Partition properties we give for a normal world VM:
+ * - can send direct message but not receive them
+ * - can handle indirect messages
+ * - can receive notifications
+ * 32/64 bit flag is set depending on the VM
+ */
+#define FFA_PART_VM_PROP    (FFA_PART_PROP_DIRECT_REQ_SEND | \
+                             FFA_PART_PROP_INDIRECT_MSGS | \
+                             FFA_PART_PROP_RECV_NOTIF | \
+                             FFA_PART_PROP_IS_PE_ID)
+
 /* Flags used in calls to FFA_NOTIFICATION_GET interface  */
 #define FFA_NOTIF_FLAG_BITMAP_SP        BIT(0, U)
 #define FFA_NOTIF_FLAG_BITMAP_VM        BIT(1, U)
@@ -297,36 +309,72 @@ struct ffa_ctx_notif {
 };
 
 struct ffa_ctx {
-    void *rx;
-    const void *tx;
-    struct page_info *rx_pg;
-    struct page_info *tx_pg;
+    /*
+     * Chain list of all FF-A contexts.
+     * As we might have several read from the list of context through parallel
+     * partinfo_get but fewer additions/removal as those happen only during a
+     * version negotiation or guest shutdown, access to this list is protected
+     * through a rwlock (addition/removal with write lock, reading through a
+     * read lock).
+     */
+    struct list_head ctx_list; /* chain list of all FF-A contexts */
+
+    /*
+     * Data access unlocked (mainly for part_info_get in VM to VM).
+     * Those should be set before the ctx is added in the list.
+     */
+    /* FF-A Endpoint ID */
+    uint16_t ffa_id;
+    uint16_t num_vcpus;
+    bool is_64bit;
+
+    /*
+     * Global data accessed atomically or using ACCES_ONCE.
+     */
+    struct ffa_ctx_notif notif;
+
+    /*
+     * Global data accessed with lock locked.
+     */
+    spinlock_t lock;
+    /*
+     * FF-A version negotiated by the guest, only modifications to
+     * this field are done with the lock held as this is expected to
+     * be done once at init by a guest.
+     */
+    uint32_t guest_vers;
     /* Number of 4kB pages in each of rx/rx_pg and tx/tx_pg */
     unsigned int page_count;
-    /* FF-A version used by the guest */
-    uint32_t guest_vers;
-    bool rx_is_free;
-    /* Used shared memory objects, struct ffa_shm_mem */
-    struct list_head shm_list;
     /* Number of allocated shared memory object */
     unsigned int shm_count;
-    struct ffa_ctx_notif notif;
+    /* Used shared memory objects, struct ffa_shm_mem */
+    struct list_head shm_list;
+
     /*
-     * tx_lock is used to serialize access to tx
-     * rx_lock is used to serialize access to rx_is_free
-     * lock is used for the rest in this struct
+     * Rx buffer, accessed with rx_lock locked.
+     * rx_is_free is used to serialize access.
      */
-    spinlock_t tx_lock;
     spinlock_t rx_lock;
-    spinlock_t lock;
-    /* Used if domain can't be torn down immediately */
+    bool rx_is_free;
+    void *rx;
+    struct page_info *rx_pg;
+
+    /*
+     * Tx buffer, access with tx_lock locked.
+     */
+    spinlock_t tx_lock;
+    const void *tx;
+    struct page_info *tx_pg;
+
+
+    /*
+     * Domain teardown handling if data shared or used by other domains
+     * do not allow to teardown the domain immediately.
+     */
     struct domain *teardown_d;
     struct list_head teardown_list;
     s_time_t teardown_expire;
-    /*
-     * Used for ffa_domain_teardown() to keep track of which SPs should be
-     * notified that this guest is being destroyed.
-     */
+    /* Keep track of SPs that should be notified of VM destruction */
     unsigned long *vm_destroy_bitmap;
 };
 
@@ -336,6 +384,12 @@ extern spinlock_t ffa_rx_buffer_lock;
 extern spinlock_t ffa_tx_buffer_lock;
 extern DECLARE_BITMAP(ffa_fw_abi_supported, FFA_ABI_BITMAP_SIZE);
 
+extern struct list_head ffa_ctx_head;
+extern rwlock_t ffa_ctx_list_rwlock;
+#ifdef CONFIG_FFA_VM_TO_VM
+extern atomic_t ffa_vm_count;
+#endif
+
 bool ffa_shm_domain_destroy(struct domain *d);
 void ffa_handle_mem_share(struct cpu_user_regs *regs);
 int ffa_handle_mem_reclaim(uint64_t handle, uint32_t flags);
@@ -368,6 +422,29 @@ int ffa_handle_notification_set(struct cpu_user_regs *regs);
 void ffa_handle_msg_send_direct_req(struct cpu_user_regs *regs, uint32_t fid);
 int32_t ffa_handle_msg_send2(struct cpu_user_regs *regs);
 
+#ifdef CONFIG_FFA_VM_TO_VM
+static inline uint16_t get_ffa_vm_count(void)
+{
+    return atomic_read(&ffa_vm_count);
+}
+
+static inline void inc_ffa_vm_count(void)
+{
+    atomic_inc(&ffa_vm_count);
+}
+
+static inline void dec_ffa_vm_count(void)
+{
+    ASSERT(atomic_read(&ffa_vm_count) > 0);
+    atomic_dec(&ffa_vm_count);
+}
+#else
+/* Only count the caller VM */
+#define get_ffa_vm_count()  ((uint16_t)1UL)
+#define inc_ffa_vm_count()  do {} while(0)
+#define dec_ffa_vm_count()  do {} while(0)
+#endif
+
 static inline uint16_t ffa_get_vm_id(const struct domain *d)
 {
     /* +1 since 0 is reserved for the hypervisor in FF-A */
-- 
2.47.1



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From: Bertrand Marquis 
To: xen-devel@lists.xenproject.org
Cc: Volodymyr Babchuk ,
	Stefano Stabellini ,
	Julien Grall ,
	Michal Orzel ,
	Jens Wiklander ,
	Julien Grall 
Subject: [PATCH v8 5/6] xen/arm: ffa: Add indirect message between VM
Date: Mon, 11 Aug 2025 15:35:01 +0200
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Add support for indirect messages between VMs.
This is only enabled if CONFIG_FFA_VM_TO_VM is selected.

Signed-off-by: Bertrand Marquis 
Reviewed-by: Jens Wiklander 
Acked-by: Julien Grall 
---
Change in v8:
- Add Julien A-b
Changes in v7:
- None
Changes in v6:
- fix code alignment (Jens)
- add Jens R-b
Changes in v5:
- Prevent potential overflow in send2 handling (Julien)
- Only use page_count with rx lock acquired
- Fix an issue where send2 between VMs was not doing the copy from the
  tx buffer but from a wrong location in the stack. This bug was
  introduced in v4 when switching to a local copy for the header.
Changes in v4:
- Use a local copy of the message header to prevent a TOC/TOU possible
  issue when using the payload size
Changes in v3:
- Move vm to vm indirect message handling in a sub function to simplify
  lock handling and make implementation easier to read
Changes in v2:
- Switch ifdef to IS_ENABLED
---
 xen/arch/arm/tee/ffa_msg.c | 117 ++++++++++++++++++++++++++++++++-----
 1 file changed, 102 insertions(+), 15 deletions(-)

diff --git a/xen/arch/arm/tee/ffa_msg.c b/xen/arch/arm/tee/ffa_msg.c
index ee594e737fc7..c20c5bec0f76 100644
--- a/xen/arch/arm/tee/ffa_msg.c
+++ b/xen/arch/arm/tee/ffa_msg.c
@@ -88,43 +88,130 @@ out:
                  resp.a7 & mask);
 }
 
+static int32_t ffa_msg_send2_vm(uint16_t dst_id, const void *src_buf,
+                                struct ffa_part_msg_rxtx *src_msg)
+{
+    struct domain *dst_d;
+    struct ffa_ctx *dst_ctx;
+    struct ffa_part_msg_rxtx *dst_msg;
+    int err;
+    int32_t ret;
+
+    if ( dst_id == 0 )
+        /* FF-A ID 0 is the hypervisor, this is not valid */
+        return FFA_RET_INVALID_PARAMETERS;
+
+    /* This is also checking that dest is not src */
+    err = rcu_lock_live_remote_domain_by_id(dst_id - 1, &dst_d);
+    if ( err )
+        return FFA_RET_INVALID_PARAMETERS;
+
+    if ( dst_d->arch.tee == NULL )
+    {
+        ret = FFA_RET_INVALID_PARAMETERS;
+        goto out_unlock;
+    }
+
+    dst_ctx = dst_d->arch.tee;
+    if ( !dst_ctx->guest_vers )
+    {
+        ret = FFA_RET_INVALID_PARAMETERS;
+        goto out_unlock;
+    }
+
+    /* This also checks that destination has set a Rx buffer */
+    ret = ffa_rx_acquire(dst_d);
+    if ( ret )
+        goto out_unlock;
+
+    /* we need to have enough space in the destination buffer */
+    if ( (dst_ctx->page_count * FFA_PAGE_SIZE -
+          sizeof(struct ffa_part_msg_rxtx)) < src_msg->msg_size )
+    {
+        ret = FFA_RET_NO_MEMORY;
+        ffa_rx_release(dst_d);
+        goto out_unlock;
+    }
+
+    dst_msg = dst_ctx->rx;
+
+    /* prepare destination header */
+    dst_msg->flags = 0;
+    dst_msg->reserved = 0;
+    dst_msg->msg_offset = sizeof(struct ffa_part_msg_rxtx);
+    dst_msg->send_recv_id = src_msg->send_recv_id;
+    dst_msg->msg_size = src_msg->msg_size;
+
+    memcpy(dst_ctx->rx + sizeof(struct ffa_part_msg_rxtx),
+           src_buf + src_msg->msg_offset, src_msg->msg_size);
+
+    /* receiver rx buffer will be released by the receiver*/
+
+out_unlock:
+    rcu_unlock_domain(dst_d);
+    if ( !ret )
+        ffa_raise_rx_buffer_full(dst_d);
+
+    return ret;
+}
+
 int32_t ffa_handle_msg_send2(struct cpu_user_regs *regs)
 {
     struct domain *src_d = current->domain;
     struct ffa_ctx *src_ctx = src_d->arch.tee;
-    const struct ffa_part_msg_rxtx *src_msg;
+    struct ffa_part_msg_rxtx src_msg;
     uint16_t dst_id, src_id;
     int32_t ret;
 
-    if ( !ffa_fw_supports_fid(FFA_MSG_SEND2) )
-        return FFA_RET_NOT_SUPPORTED;
+    BUILD_BUG_ON(sizeof(struct ffa_part_msg_rxtx) >= FFA_PAGE_SIZE);
 
     if ( !spin_trylock(&src_ctx->tx_lock) )
         return FFA_RET_BUSY;
 
-    src_msg = src_ctx->tx;
-    src_id = src_msg->send_recv_id >> 16;
-    dst_id = src_msg->send_recv_id & GENMASK(15,0);
+    /* create a copy of the message header */
+    memcpy(&src_msg, src_ctx->tx, sizeof(src_msg));
 
-    if ( src_id != ffa_get_vm_id(src_d) || !FFA_ID_IS_SECURE(dst_id) )
+    src_id = src_msg.send_recv_id >> 16;
+    dst_id = src_msg.send_recv_id & GENMASK(15,0);
+
+    if ( src_id != ffa_get_vm_id(src_d) )
     {
         ret = FFA_RET_INVALID_PARAMETERS;
-        goto out_unlock_tx;
+        goto out;
     }
 
     /* check source message fits in buffer */
-    if ( src_ctx->page_count * FFA_PAGE_SIZE <
-         src_msg->msg_offset + src_msg->msg_size ||
-         src_msg->msg_offset < sizeof(struct ffa_part_msg_rxtx) )
+    if ( src_msg.msg_offset < sizeof(struct ffa_part_msg_rxtx) ||
+            src_msg.msg_size == 0 ||
+            src_msg.msg_offset > src_ctx->page_count * FFA_PAGE_SIZE ||
+            src_msg.msg_size > (src_ctx->page_count * FFA_PAGE_SIZE -
+                                src_msg.msg_offset) )
     {
         ret = FFA_RET_INVALID_PARAMETERS;
-        goto out_unlock_tx;
+        goto out;
     }
 
-    ret = ffa_simple_call(FFA_MSG_SEND2,
-                          ((uint32_t)ffa_get_vm_id(src_d)) << 16, 0, 0, 0);
+    if ( FFA_ID_IS_SECURE(dst_id) )
+    {
+        /* Message for a secure partition */
+        if ( !ffa_fw_supports_fid(FFA_MSG_SEND2) )
+        {
+            ret = FFA_RET_NOT_SUPPORTED;
+            goto out;
+        }
+
+        ret = ffa_simple_call(FFA_MSG_SEND2,
+                              ((uint32_t)ffa_get_vm_id(src_d)) << 16, 0, 0, 0);
+    }
+    else if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) )
+    {
+        /* Message for a VM */
+        ret = ffa_msg_send2_vm(dst_id, src_ctx->tx, &src_msg);
+    }
+    else
+        ret = FFA_RET_INVALID_PARAMETERS;
 
-out_unlock_tx:
+out:
     spin_unlock(&src_ctx->tx_lock);
     return ret;
 }
-- 
2.47.1



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	Stefano Stabellini ,
	Julien Grall ,
	Michal Orzel ,
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	Julien Grall 
Subject: [PATCH v8 6/6] xen/arm: ffa: Enable VM to VM without firmware
Date: Mon, 11 Aug 2025 15:35:02 +0200
Message-ID: <51eebef30505dafbd9f3ccbf9e0dd99bb316c852.1754899329.git.bertrand.marquis@arm.com>
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When VM to VM support is activated and there is no suitable FF-A support
in the firmware, enable FF-A support for VMs to allow using it for VM to
VM communications.
If there is OP-TEE running in the secure world and using the non FF-A
communication system, having CONFIG_FFA_VM_TO_VM could be non functional
(if optee is probed first) or OP-TEE could be non functional (if FF-A is
probed first) so it is not recommended to activate the configuration
option for such systems.

To make buffer full notification work between VMs when there is no
firmware, rework the notification handling and modify the global flag to
only be used as check for firmware notification support instead.

Also split probe function into one for firmware and one for vm to vm to
make the implementation clearer.

Signed-off-by: Bertrand Marquis 
Reviewed-by: Jens Wiklander 
Acked-by: Julien Grall 
---
Changes in v8:
- add Julien A-b
Changes in v7:
- add Jens R-b
Changes in v6:
- split probe into fw and vm_to_vm probe
Changes in v5:
- init ctx list when there is no firmware
- rework init a bit to prevent duplicates
- Remove Jens R-b due to changes done
Changes in v4:
- Fix Optee to OP-TEE in commit message
- Add Jens R-b
Changes in v3:
- fix typos in commit message
- add spaces around <<
- move notification id fix back into buffer full patch
- fix | position in if
Changes in v2:
- replace ifdef with IS_ENABLED when possible
---
 xen/arch/arm/tee/ffa.c       |  87 +++++++++++++++++------------
 xen/arch/arm/tee/ffa_notif.c | 104 ++++++++++++++++-------------------
 2 files changed, 101 insertions(+), 90 deletions(-)

diff --git a/xen/arch/arm/tee/ffa.c b/xen/arch/arm/tee/ffa.c
index 0eb6a0bda5fb..1d0239cf6950 100644
--- a/xen/arch/arm/tee/ffa.c
+++ b/xen/arch/arm/tee/ffa.c
@@ -346,8 +346,9 @@ static int ffa_domain_init(struct domain *d)
     struct ffa_ctx *ctx;
     int ret;
 
-    if ( !ffa_fw_version )
+    if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !ffa_fw_version )
         return -ENODEV;
+
     /*
      * We are using the domain_id + 1 as the FF-A ID for VMs as FF-A ID 0 is
      * reserved for the hypervisor and we only support secure endpoints using
@@ -478,38 +479,12 @@ static void ffa_init_secondary(void)
     ffa_notif_init_interrupt();
 }
 
-static bool ffa_probe(void)
+static bool ffa_probe_fw(void)
 {
     uint32_t vers;
     unsigned int major_vers;
     unsigned int minor_vers;
 
-    /*
-     * FF-A often works in units of 4K pages and currently it's assumed
-     * that we can map memory using that granularity. See also the comment
-     * above the FFA_PAGE_SIZE define.
-     *
-     * It is possible to support a PAGE_SIZE larger than 4K in Xen, but
-     * until that is fully handled in this code make sure that we only use
-     * 4K page sizes.
-     */
-    BUILD_BUG_ON(PAGE_SIZE != FFA_PAGE_SIZE);
-
-    printk(XENLOG_INFO "ARM FF-A Mediator version %u.%u\n",
-           FFA_MY_VERSION_MAJOR, FFA_MY_VERSION_MINOR);
-
-    if ( IS_ENABLED(CONFIG_FFA_VM_TO_VM) )
-    {
-        /*
-         * When FFA VM to VM is enabled, the current implementation does not
-         * offer any way to limit which VM can communicate with which VM using
-         * FF-A.
-         * Signal this in the xen console and taint the system as insecure.
-         * TODO: Introduce a solution to limit what a VM can do through FFA.
-         */
-        printk(XENLOG_ERR "ffa: VM to VM is enabled, system is insecure !!\n");
-        add_taint(TAINT_MACHINE_INSECURE);
-    }
     /*
      * psci_init_smccc() updates this value with what's reported by EL-3
      * or secure world.
@@ -528,11 +503,6 @@ static bool ffa_probe(void)
         goto err_no_fw;
     }
 
-    /* Some sanity check in case we update the version we support */
-    BUILD_BUG_ON(FFA_MIN_SPMC_VERSION > FFA_MY_VERSION);
-    BUILD_BUG_ON(FFA_VERSION_MAJOR(FFA_MIN_SPMC_VERSION) !=
-                                   FFA_MY_VERSION_MAJOR);
-
     major_vers = FFA_VERSION_MAJOR(vers);
     minor_vers = FFA_VERSION_MINOR(vers);
 
@@ -583,7 +553,6 @@ static bool ffa_probe(void)
         goto err_rxtx_destroy;
 
     ffa_notif_init();
-    init_timer(&ffa_teardown_timer, ffa_teardown_timer_callback, NULL, 0);
 
     return true;
 
@@ -597,6 +566,56 @@ err_no_fw:
     return false;
 }
 
+static bool ffa_probe_vm_to_vm(void)
+{
+    if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) )
+        return false;
+
+    /*
+     * When FFA VM to VM is enabled, the current implementation does not
+     * offer any way to limit which VM can communicate with which VM using
+     * FF-A.
+     * Signal this in the xen console and taint the system as insecure.
+     * TODO: Introduce a solution to limit what a VM can do through FFA.
+     */
+    printk(XENLOG_ERR "ffa: VM to VM is enabled, system is insecure !!\n");
+    add_taint(TAINT_MACHINE_INSECURE);
+
+    return true;
+}
+
+static bool ffa_probe(void)
+{
+    /*
+     * FF-A often works in units of 4K pages and currently it's assumed
+     * that we can map memory using that granularity. See also the comment
+     * above the FFA_PAGE_SIZE define.
+     *
+     * It is possible to support a PAGE_SIZE larger than 4K in Xen, but
+     * until that is fully handled in this code make sure that we only use
+     * 4K page sizes.
+     */
+    BUILD_BUG_ON(PAGE_SIZE != FFA_PAGE_SIZE);
+
+    /* Some sanity check in case we update the version we support */
+    BUILD_BUG_ON(FFA_MIN_SPMC_VERSION > FFA_MY_VERSION);
+    BUILD_BUG_ON(FFA_VERSION_MAJOR(FFA_MIN_SPMC_VERSION) !=
+                                   FFA_MY_VERSION_MAJOR);
+
+    printk(XENLOG_INFO "ARM FF-A Mediator version %u.%u\n",
+           FFA_MY_VERSION_MAJOR, FFA_MY_VERSION_MINOR);
+
+    if ( !ffa_probe_fw() && !ffa_probe_vm_to_vm() )
+        return false;
+
+    if ( !ffa_fw_version )
+        printk(XENLOG_INFO "ARM FF-A only available between VMs\n");
+
+    init_timer(&ffa_teardown_timer, ffa_teardown_timer_callback, NULL, 0);
+
+    return true;
+}
+
 static const struct tee_mediator_ops ffa_ops =
 {
     .probe = ffa_probe,
diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c
index f6df2f15bb00..86bef6b3b2ab 100644
--- a/xen/arch/arm/tee/ffa_notif.c
+++ b/xen/arch/arm/tee/ffa_notif.c
@@ -16,7 +16,7 @@
 
 #include "ffa_private.h"
 
-static bool __ro_after_init notif_enabled;
+static bool __ro_after_init fw_notif_enabled;
 static unsigned int __ro_after_init notif_sri_irq;
 
 int ffa_handle_notification_bind(struct cpu_user_regs *regs)
@@ -27,21 +27,17 @@ int ffa_handle_notification_bind(struct cpu_user_regs *regs)
     uint32_t bitmap_lo = get_user_reg(regs, 3);
     uint32_t bitmap_hi = get_user_reg(regs, 4);
 
-    if ( !notif_enabled )
-        return FFA_RET_NOT_SUPPORTED;
-
     if ( (src_dst & 0xFFFFU) != ffa_get_vm_id(d) )
         return FFA_RET_INVALID_PARAMETERS;
 
     if ( flags )    /* Only global notifications are supported */
         return FFA_RET_DENIED;
 
-    /*
-     * We only support notifications from SP so no need to check the sender
-     * endpoint ID, the SPMC will take care of that for us.
-     */
-    return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags, bitmap_lo,
-                           bitmap_hi);
+    if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled )
+        return ffa_simple_call(FFA_NOTIFICATION_BIND, src_dst, flags,
+                               bitmap_lo, bitmap_hi);
+
+    return FFA_RET_NOT_SUPPORTED;
 }
 
 int ffa_handle_notification_unbind(struct cpu_user_regs *regs)
@@ -51,18 +47,14 @@ int ffa_handle_notification_unbind(struct cpu_user_regs *regs)
     uint32_t bitmap_lo = get_user_reg(regs, 3);
     uint32_t bitmap_hi = get_user_reg(regs, 4);
 
-    if ( !notif_enabled )
-        return FFA_RET_NOT_SUPPORTED;
-
     if ( (src_dst & 0xFFFFU) != ffa_get_vm_id(d) )
         return FFA_RET_INVALID_PARAMETERS;
 
-    /*
-     * We only support notifications from SP so no need to check the
-     * destination endpoint ID, the SPMC will take care of that for us.
-     */
-    return  ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitmap_lo,
-                            bitmap_hi);
+    if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled )
+        return  ffa_simple_call(FFA_NOTIFICATION_UNBIND, src_dst, 0, bitmap_lo,
+                                bitmap_hi);
+
+    return FFA_RET_NOT_SUPPORTED;
 }
 
 void ffa_handle_notification_info_get(struct cpu_user_regs *regs)
@@ -71,7 +63,7 @@ void ffa_handle_notification_info_get(struct cpu_user_regs *regs)
     struct ffa_ctx *ctx = d->arch.tee;
     bool notif_pending;
 
-    if ( !notif_enabled )
+    if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled )
     {
         ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED);
         return;
@@ -108,7 +100,7 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs)
     uint32_t w6 = 0;
     uint32_t w7 = 0;
 
-    if ( !notif_enabled )
+    if ( !IS_ENABLED(CONFIG_FFA_VM_TO_VM) && !fw_notif_enabled )
     {
         ffa_set_regs_error(regs, FFA_RET_NOT_SUPPORTED);
         return;
@@ -120,7 +112,8 @@ void ffa_handle_notification_get(struct cpu_user_regs *regs)
         return;
     }
 
-    if ( flags & ( FFA_NOTIF_FLAG_BITMAP_SP | FFA_NOTIF_FLAG_BITMAP_SPM ) )
+    if ( fw_notif_enabled && (flags & ( FFA_NOTIF_FLAG_BITMAP_SP |
+                                        FFA_NOTIF_FLAG_BITMAP_SPM )) )
     {
         struct arm_smccc_1_2_regs arg = {
             .a0 = FFA_NOTIFICATION_GET,
@@ -177,15 +170,14 @@ int ffa_handle_notification_set(struct cpu_user_regs *regs)
     uint32_t bitmap_lo = get_user_reg(regs, 3);
     uint32_t bitmap_hi = get_user_reg(regs, 4);
 
-    if ( !notif_enabled )
-        return FFA_RET_NOT_SUPPORTED;
-
     if ( (src_dst >> 16) != ffa_get_vm_id(d) )
         return FFA_RET_INVALID_PARAMETERS;
 
-    /* Let the SPMC check the destination of the notification */
-    return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bitmap_lo,
-                           bitmap_hi);
+    if ( FFA_ID_IS_SECURE(src_dst >> 16) && fw_notif_enabled )
+        return ffa_simple_call(FFA_NOTIFICATION_SET, src_dst, flags, bitmap_lo,
+                               bitmap_hi);
+
+    return FFA_RET_NOT_SUPPORTED;
 }
 
 #ifdef CONFIG_FFA_VM_TO_VM
@@ -371,7 +363,7 @@ void ffa_notif_init_interrupt(void)
 {
     int ret;
 
-    if ( notif_enabled && notif_sri_irq < NR_GIC_SGI )
+    if ( fw_notif_enabled && notif_sri_irq < NR_GIC_SGI )
     {
         /*
          * An error here is unlikely since the primary CPU has already
@@ -402,41 +394,41 @@ void ffa_notif_init(void)
     int ret;
 
     /* Only enable fw notification if all ABIs we need are supported */
-    if ( !(ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_CREATE) &&
-           ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_DESTROY) &&
-           ffa_fw_supports_fid(FFA_NOTIFICATION_GET) &&
-           ffa_fw_supports_fid(FFA_NOTIFICATION_INFO_GET_64)) )
-        return;
-
-    arm_smccc_1_2_smc(&arg, &resp);
-    if ( resp.a0 != FFA_SUCCESS_32 )
-        return;
-
-    irq = resp.a2;
-    notif_sri_irq = irq;
-    if ( irq >= NR_GIC_SGI )
-        irq_set_type(irq, IRQ_TYPE_EDGE_RISING);
-    ret = request_irq(irq, 0, notif_irq_handler, "FF-A notif", NULL);
-    if ( ret )
+    if ( ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_CREATE) &&
+         ffa_fw_supports_fid(FFA_NOTIFICATION_BITMAP_DESTROY) &&
+         ffa_fw_supports_fid(FFA_NOTIFICATION_GET) &&
+         ffa_fw_supports_fid(FFA_NOTIFICATION_INFO_GET_64) )
     {
-        printk(XENLOG_ERR "ffa: request_irq irq %u failed: error %d\n",
-               irq, ret);
-        return;
-    }
+        arm_smccc_1_2_smc(&arg, &resp);
+        if ( resp.a0 != FFA_SUCCESS_32 )
+            return;
 
-    notif_enabled = true;
+        irq = resp.a2;
+        notif_sri_irq = irq;
+        if ( irq >= NR_GIC_SGI )
+            irq_set_type(irq, IRQ_TYPE_EDGE_RISING);
+        ret = request_irq(irq, 0, notif_irq_handler, "FF-A notif", NULL);
+        if ( ret )
+        {
+            printk(XENLOG_ERR "ffa: request_irq irq %u failed: error %d\n",
+                   irq, ret);
+            return;
+        }
+        fw_notif_enabled = true;
+    }
 }
 
 int ffa_notif_domain_init(struct domain *d)
 {
     int32_t res;
 
-    if ( !notif_enabled )
-        return 0;
+    if ( fw_notif_enabled )
+    {
 
-    res = ffa_notification_bitmap_create(ffa_get_vm_id(d), d->max_vcpus);
-    if ( res )
-        return -ENOMEM;
+        res = ffa_notification_bitmap_create(ffa_get_vm_id(d), d->max_vcpus);
+        if ( res )
+            return -ENOMEM;
+    }
 
     return 0;
 }
@@ -447,6 +439,6 @@ void ffa_notif_domain_destroy(struct domain *d)
      * Call bitmap_destroy even if bitmap create failed as the SPMC will
      * return a DENIED error that we will ignore.
      */
-    if ( notif_enabled )
+    if ( fw_notif_enabled )
         ffa_notification_bitmap_destroy(ffa_get_vm_id(d));
 }
-- 
2.47.1



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        Mon, 11 Aug 2025 07:35:51 -0700 (PDT)
Date: Mon, 11 Aug 2025 16:35:50 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Nicola Vetrini 
Cc: nicola.vetrini@gmail.com, xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich , Julien Grall ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH] xen: Drop logic for old clang versions.
Message-ID: 
References: 
 
 <2ca7082120df5e1ad6a29582d6dfb215@bugseng.com>
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In-Reply-To: <2ca7082120df5e1ad6a29582d6dfb215@bugseng.com>

On Mon, Aug 11, 2025 at 11:37:46AM +0200, Nicola Vetrini wrote:
> On 2025-08-11 09:47, Roger Pau Monné wrote:
> > On Sun, Aug 10, 2025 at 03:03:53PM +0200, nicola.vetrini@gmail.com
> > wrote:
> > > From: Nicola Vetrini 
> > > 
> > > The enforced toolchain baseline for clang is version 11,
> > > therefore this logic is effectively dead code.
> > > 
> > > No functional change.
> > > 
> > > Signed-off-by: Nicola Vetrini 
> > 
> > Acked-by: Roger Pau Monné 
> > 
> > > ---
> > > Mentioned in https://gitlab.com/xen-project/xen/-/issues/201
> > > ---
> > >  xen/common/coverage/llvm.c   | 4 ----
> > >  xen/include/xen/self-tests.h | 9 +--------
> > >  2 files changed, 1 insertion(+), 12 deletions(-)
> > > 
> > > diff --git a/xen/common/coverage/llvm.c b/xen/common/coverage/llvm.c
> > > index 50d7a3c5d301..517b2aa8c202 100644
> > > --- a/xen/common/coverage/llvm.c
> > > +++ b/xen/common/coverage/llvm.c
> > > @@ -44,12 +44,8 @@
> > >      ((uint64_t)'f' << 16) | ((uint64_t)'R' << 8)  | ((uint64_t)129)
> > >  #endif
> > > 
> > > -#if __clang_major__ >= 4 || (__clang_major__ == 3 &&
> > > __clang_minor__ >= 9)
> > >  #define LLVM_PROFILE_VERSION    4
> > >  #define LLVM_PROFILE_NUM_KINDS  2
> > > -#else
> > > -#error "clang version not supported with coverage"
> > > -#endif
> > 
> > Rant: most of the LLVM coverage stuff is already kind of dead code, as
> > the format of the data changes between versions and there's no way for
> > LLVM to generate the blob itself using a builtin function or
> > similar.  We haven't kept up with new formats, and now it's not
> > possible to parse the output coverage data when using newish LLVM
> > versions.
> > 
> > Linux converts it's LLVM coverage data to gcov format (which AFAIK is
> > way more stable), and exports it in gcov format.  We should consider
> > importing that from Linux.
> > 
> > Thanks, Roger.
> 
> Fair point. Generally I found coverage reports generated using LLVM tooling
> a bit more informative than gcov's, but I don't know how much work would it
> be to adapt Xen for newer versions of LLVM.

It's a pain because they keep changing the blob format between
versions, so we would basically need code in Xen to be able to
generate the right blob for each possible clang version.

It would be helpful if clang provided the helpers to generate the
coverage data in a version agnostic way, but so far I haven't found a
way to do it.  I've raised a question with upstream LLVM project, but
no replies:

https://github.com/llvm/llvm-project/issues/123034

Regards, Roger.


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Date: Mon, 11 Aug 2025 16:37:47 +0200
From: Anthony PERARD 
To: Andrew Cooper 
Cc: xen-devel@lists.xenproject.org,
	Anthony PERARD ,
	Oleksii Kurochko ,
	Community Manager ,
	Michal Orzel ,
	Jan Beulich , Julien Grall ,
	Roger Pau =?iso-8859-1?Q?Monn=E9?= ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH 11/11] Update CHANGELOG and README with dependency on
 json-c
Message-ID: 
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-12-anthony@xenproject.org>
 <2f073fa0-5064-4cd2-b332-c3a6ceaf537a@citrix.com>
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On Mon, Aug 11, 2025 at 11:55:04AM +0100, Andrew Cooper wrote:
> On 08/08/2025 3:56 pm, Anthony PERARD wrote:
> > From: Anthony PERARD 
> >
> > Signed-off-by: Anthony PERARD 
> > ---
> >  CHANGELOG.md | 2 ++
> >  README       | 2 +-
> >  2 files changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/CHANGELOG.md b/CHANGELOG.md
> > index 5f31ca08fe..83195e2dae 100644
> > --- a/CHANGELOG.md
> > +++ b/CHANGELOG.md
> > @@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
> >     - For x86, GCC 5.1 and Binutils 2.25, or Clang/LLVM 11
> >     - For ARM32 and ARM64, GCC 5.1 and Binutils 2.25
> >   - Linux based device model stubdomains are now fully supported.
> > + - New dependency on library json-c, the toolstack will prefer it to `YAJL`
> > +   when available.
> >  
> >   - On x86:
> >     - Restrict the cache flushing done as a result of guest physical memory map
> > diff --git a/README b/README
> > index 6ee58f7b35..9329f30e13 100644
> > --- a/README
> > +++ b/README
> > @@ -53,7 +53,7 @@ provided by your OS distributor:
> >      * Development install of Python 2.7 or later (e.g., python-dev)
> >      * Development install of curses (e.g., libncurses-dev)
> >      * Development install of uuid (e.g. uuid-dev)
> > -    * Development install of yajl (e.g. libyajl-dev)
> > +    * Development install of json-c (e.g. libjson-c-dev) or yajl (e.g. libyajl-dev)
> >      * Development install of libaio (e.g. libaio-dev) version 0.3.107 or
> >        greater.
> >      * Development install of GLib v2.0 (e.g. libglib2.0-dev)
> 
> What are we going to do about testing this?
> 
> We should add libjson-c to some build containers.  We need to annotate #
> Xen < 4.21 in the existing containers so we can drop it in due course.

archlinux container already have `json-c` so the CI already do some
build jobs with it. (no *-dev needed for this one container). It even
notice an issue with `debug=n` builds, I had to replace `strncpy` by
`memcpy`.

> Also, for a container we don't intend to backport to stable trees, we
> should have libjson-c only and no yajl.  Probably best to do this in the
> Alpine update which is long overdue.

Doing this on alpine container would allow to actually do some runtime
tests with json-c instead of yajl, so yes.

-- 
Anthony PERARD


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Date: Mon, 11 Aug 2025 16:44:02 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3 14/20] xen/riscv: Implement p2m_pte_from_mfn() and
 support PBMT configuration
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <1370613cd6f52e90591b15ad52c95d7c81908cf6.1753973161.git.oleksii.kurochko@gmail.com>
 <3ede10e7-8e43-4277-9197-14a3e5ab1cc1@suse.com>
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From: Oleksii Kurochko 
In-Reply-To: <3ede10e7-8e43-4277-9197-14a3e5ab1cc1@suse.com>

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On 8/11/25 1:36 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> --- a/xen/arch/riscv/p2m.c
>> +++ b/xen/arch/riscv/p2m.c
>> @@ -1,3 +1,4 @@
>> +#include 
>>   #include 
>>   #include 
>>   #include 
>> @@ -197,6 +198,18 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
>>       return __map_domain_page(p2m->root + root_table_indx);
>>   }
>>   
>> +static int p2m_set_type(pte_t *pte, p2m_type_t t)
>> +{
>> +    int rc = 0;
>> +
>> +    if ( t > p2m_ext_storage )
> Seeing this separator enumerator in use, it becomes pretty clear that its name
> needs to change, so one doesn't need to go look at its definition to understand
> whether it's inclusive or exclusive. (This isn't helped by there presently being
> a spare entry, which, when made use of, might then cause problems with
> expressions like this one as well.)

Then|p2m_pte_type_count| might be a better name, as it indicates how many types are
stored directly in the PTE bits.

>
>> @@ -222,11 +235,71 @@ static inline void p2m_clean_pte(pte_t *p, bool clean_pte)
>>       p2m_write_pte(p, pte, clean_pte);
>>   }
>>   
>> -static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t)
>> +static void p2m_set_permission(pte_t *e, p2m_type_t t)
>>   {
>> -    panic("%s: hasn't been implemented yet\n", __func__);
>> +    e->pte &= ~PTE_ACCESS_MASK;
>> +
>> +    switch ( t )
>> +    {
>> +    case p2m_grant_map_rw:
>> +    case p2m_ram_rw:
>> +        e->pte |= PTE_READABLE | PTE_WRITABLE;
>> +        break;
> While I agree for r/w grants, shouldn't r/w RAM also be executable?
>
>> +    case p2m_ext_storage:
> Why exactly would this placeholder ...
>
>> +    case p2m_mmio_direct_io:
>> +        e->pte |= PTE_ACCESS_MASK;
>> +        break;
> ... gain full access? It shouldn't make it here at all, should it?

I missed to add break between them, but I don't remember why I
put it here.
It could be freely moved before "default".

And, yes, you are right it seems like is shouldn't be handled at all
in this function as this function isn't expected to be called with
this type as this type only is used to indicate that a real type is
stored somwehere.

>
>> +
>> +    case p2m_invalid:
>> +        e->pte &= ~(PTE_ACCESS_MASK | PTE_VALID);
> Redundantly masking off PTE_ACCESS_MASK? (Plus, for the entry to be
> invalid, turning off PTE_VALID alone ought to suffice anyway?)

Agree, turning off PTE_VALID would be just enough.

>> +        break;
>> +
>> +    case p2m_grant_map_ro:
>> +        e->pte |= PTE_READABLE;
>> +        break;
>> +
>> +    default:
>> +        ASSERT_UNREACHABLE();
>> +        break;
>> +    }
>> +}
>> +
>> +static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
>> +{
>> +    pte_t e = (pte_t) { PTE_VALID };
> This and the rest of the function demand that mfn != INVALID_MFN, no matter
> whether ...
>
>> +    switch ( t )
>> +    {
>> +    case p2m_mmio_direct_io:
>> +        e.pte |= PTE_PBMT_IO;
>> +        break;
>> +
>> +    default:
>> +        break;
>> +    }
>> +
>> +    pte_set_mfn(&e, mfn);
>> +
>> +    ASSERT(!(mfn_to_maddr(mfn) & ~PADDR_MASK));
> ... PADDR_MASK is actually narrow enough to catch that case. Maybe best to
> add an explicit assertion to that effect?

Then it should be enough instead of what we have now:
   ASSERT(mfn_valid(mfn));

>
>> +    if ( !is_table )
>> +    {
>> +        p2m_set_permission(&e, t);
>> +
>> +        if ( t < p2m_ext_storage )
>> +            p2m_set_type(&e, t);
>> +        else
>> +            panic("unimplemeted\n");
> The check is already done inside p2m_set_type() - why open-code it here?

It isn't really matters now (so could be dropped), but in further patch this part
of code will look like:
         metadata[indx].pte = p2m_invalid;

         if ( t < p2m_ext_storage )
             p2m_set_type(&e, t, indx);
         else
         {
             e.pte |= MASK_INSR(p2m_ext_storage, P2M_TYPE_PTE_BITS_MASK);
             p2m_set_type(metadata, t, indx);
         }
So my intention was to re-use p2m_set_type() without changing of a prototype. So,
if a type is stored in PTE bits then we pass PTE directly, if not - then pass
metadata.

Thanks.

~ Oleksii

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Content-Transfer-Encoding: 7bit



  
    
  
  
    

    
    
    
    
    On 8/11/25 1:36 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    --- a/xen/arch/riscv/p2m.c
+++ b/xen/arch/riscv/p2m.c
@@ -1,3 +1,4 @@
+#include <xen/bug.h>
 #include <xen/domain_page.h>
 #include <xen/mm.h>
 #include <xen/rwlock.h>
@@ -197,6 +198,18 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
     return __map_domain_page(p2m->root + root_table_indx);
 }
 
+static int p2m_set_type(pte_t *pte, p2m_type_t t)
+{
+    int rc = 0;
+
+    if ( t > p2m_ext_storage )

    
      
    
      
    Seeing this separator enumerator in use, it becomes pretty clear that its name
needs to change, so one doesn't need to go look at its definition to understand
whether it's inclusive or exclusive. (This isn't helped by there presently being
a spare entry, which, when made use of, might then cause problems with
expressions like this one as well.)
    
    
    
    
    Then p2m_pte_type_count might be a better name, as it indicates how many types are
stored directly in the PTE bits.


    
    
    
      
    

    
      
    
        
    @@ -222,11 +235,71 @@ static inline void p2m_clean_pte(pte_t *p, bool clean_pte)
     p2m_write_pte(p, pte, clean_pte);
 }
 
-static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t)
+static void p2m_set_permission(pte_t *e, p2m_type_t t)
 {
-    panic("%s: hasn't been implemented yet\n", __func__);
+    e->pte &= ~PTE_ACCESS_MASK;
+
+    switch ( t )
+    {
+    case p2m_grant_map_rw:
+    case p2m_ram_rw:
+        e->pte |= PTE_READABLE | PTE_WRITABLE;
+        break;

    
      
    
      
    While I agree for r/w grants, shouldn't r/w RAM also be executable?


    
      
    
        
    +    case p2m_ext_storage:

    
      
    
      
    Why exactly would this placeholder ...


    
      
    
        
    +    case p2m_mmio_direct_io:
+        e->pte |= PTE_ACCESS_MASK;
+        break;

    
      
    
      
    ... gain full access? It shouldn't make it here at all, should it?
    
    
    
    
    I missed to add break between them, but I don't remember why I
put it here.
It could be freely moved before "default".

And, yes, you are right it seems like is shouldn't be handled at all
in this function as this function isn't expected to be called with
this type as this type only is used to indicate that a real type is
stored somwehere.

    
    
    
      
    

    
      
    
        
    +
+    case p2m_invalid:
+        e->pte &= ~(PTE_ACCESS_MASK | PTE_VALID);

    
      
    
      
    Redundantly masking off PTE_ACCESS_MASK? (Plus, for the entry to be
invalid, turning off PTE_VALID alone ought to suffice anyway?)

    
    
    
    
    Agree, turning off PTE_VALID would be just enough.

    
    
    
      
    
      
    
        
    +        break;
+
+    case p2m_grant_map_ro:
+        e->pte |= PTE_READABLE;
+        break;
+
+    default:
+        ASSERT_UNREACHABLE();
+        break;
+    }
+}
+
+static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
+{
+    pte_t e = (pte_t) { PTE_VALID };

    
      
    
      
    This and the rest of the function demand that mfn != INVALID_MFN, no matter
whether ...


    
      
    
        
    +    switch ( t )
+    {
+    case p2m_mmio_direct_io:
+        e.pte |= PTE_PBMT_IO;
+        break;
+
+    default:
+        break;
+    }
+
+    pte_set_mfn(&e, mfn);
+
+    ASSERT(!(mfn_to_maddr(mfn) & ~PADDR_MASK));

    
      
    
      
    ... PADDR_MASK is actually narrow enough to catch that case. Maybe best to
add an explicit assertion to that effect?
    
    
    
    
    Then it should be enough instead of what we have now:
  ASSERT(mfn_valid(mfn));


    
    
    
      
    

    
      
    
        
    +    if ( !is_table )
+    {
+        p2m_set_permission(&e, t);
+
+        if ( t < p2m_ext_storage )
+            p2m_set_type(&e, t);
+        else
+            panic("unimplemeted\n");

    
      
    
      
    The check is already done inside p2m_set_type() - why open-code it here?
    
    
    
    
    It isn't really matters now (so could be dropped), but in further patch this part
of code will look like:
        metadata[indx].pte = p2m_invalid;

        if ( t < p2m_ext_storage )
            p2m_set_type(&e, t, indx);
        else
        {
            e.pte |= MASK_INSR(p2m_ext_storage, P2M_TYPE_PTE_BITS_MASK);
            p2m_set_type(metadata, t, indx);
        }
So my intention was to re-use p2m_set_type() without changing of a prototype. So,
if a type is stored in PTE bits then we pass PTE directly, if not - then pass
metadata.

Thanks.

    
    
    ~ Oleksii
    
  


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Date: Mon, 11 Aug 2025 17:11:50 +0200
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Subject: Re: [PATCH v3 14/20] xen/riscv: Implement p2m_pte_from_mfn() and
 support PBMT configuration
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <1370613cd6f52e90591b15ad52c95d7c81908cf6.1753973161.git.oleksii.kurochko@gmail.com>
 <3ede10e7-8e43-4277-9197-14a3e5ab1cc1@suse.com>
 
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From: Jan Beulich 
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On 11.08.2025 16:44, Oleksii Kurochko wrote:
> On 8/11/25 1:36 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> +static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
>>> +{
>>> +    pte_t e = (pte_t) { PTE_VALID };
>> This and the rest of the function demand that mfn != INVALID_MFN, no matter
>> whether ...
>>
>>> +    switch ( t )
>>> +    {
>>> +    case p2m_mmio_direct_io:
>>> +        e.pte |= PTE_PBMT_IO;
>>> +        break;
>>> +
>>> +    default:
>>> +        break;
>>> +    }
>>> +
>>> +    pte_set_mfn(&e, mfn);
>>> +
>>> +    ASSERT(!(mfn_to_maddr(mfn) & ~PADDR_MASK));
>> ... PADDR_MASK is actually narrow enough to catch that case. Maybe best to
>> add an explicit assertion to that effect?
> 
> Then it should be enough instead of what we have now:
>    ASSERT(mfn_valid(mfn));

No, that would exclude MMIO living beyond max_page.

>>> +    if ( !is_table )
>>> +    {
>>> +        p2m_set_permission(&e, t);
>>> +
>>> +        if ( t < p2m_ext_storage )
>>> +            p2m_set_type(&e, t);
>>> +        else
>>> +            panic("unimplemeted\n");
>> The check is already done inside p2m_set_type() - why open-code it here?
> 
> It isn't really matters now (so could be dropped), but in further patch this part
> of code will look like:
>          metadata[indx].pte = p2m_invalid;
> 
>          if ( t < p2m_ext_storage )
>              p2m_set_type(&e, t, indx);
>          else
>          {
>              e.pte |= MASK_INSR(p2m_ext_storage, P2M_TYPE_PTE_BITS_MASK);
>              p2m_set_type(metadata, t, indx);
>          }
> So my intention was to re-use p2m_set_type() without changing of a prototype. So,
> if a type is stored in PTE bits then we pass PTE directly, if not - then pass
> metadata.

Then at the very least p2m_set_type() may not be a good name; a function of this
name imo should set the type, whatever it takes to do so. But I'm unconvinced of
the model as a whole.

Jan


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Date: Mon, 11 Aug 2025 17:19:00 +0200
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Subject: Re: [PATCH v3 16/20] xen/riscv: Implement superpage splitting for p2m
 mappings
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <6890f77e577493194ea94834989dc0841d18eed0.1753973161.git.oleksii.kurochko@gmail.com>
 
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From: Oleksii Kurochko 
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On 8/11/25 1:59 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> Add support for down large memory mappings ("superpages") in the RISC-V
>> p2m mapping so that smaller, more precise mappings ("finer-grained entries")
>> can be inserted into lower levels of the page table hierarchy.
>>
>> To implement that the following is done:
>> - Introduce p2m_split_superpage(): Recursively shatters a superpage into
>>    smaller page table entries down to the target level, preserving original
>>    permissions and attributes.
>> - p2m_set_entry() updated to invoke superpage splitting when inserting
>>    entries at lower levels within a superpage-mapped region.
>>
>> This implementation is based on the ARM code, with modifications to the part
>> that follows the BBM (break-before-make) approach, some parts are simplified
>> as according to RISC-V spec:
>>    It is permitted for multiple address-translation cache entries to co-exist
>>    for the same address. This represents the fact that in a conventional
>>    TLB hierarchy, it is possible for multiple entries to match a single
>>    address if, for example, a page is upgraded to a superpage without first
>>    clearing the original non-leaf PTE’s valid bit and executing an SFENCE.VMA
>>    with rs1=x0, or if multiple TLBs exist in parallel at a given level of the
>>    hierarchy. In this case, just as if an SFENCE.VMA is not executed between
>>    a write to the memory-management tables and subsequent implicit read of the
>>    same address: it is unpredictable whether the old non-leaf PTE or the new
>>    leaf PTE is used, but the behavior is otherwise well defined.
>> In contrast to the Arm architecture, where BBM is mandatory and failing to
>> use it in some cases can lead to CPU instability, RISC-V guarantees
>> stability, and the behavior remains safe — though unpredictable in terms of
>> which translation will be used.
>>
>> Additionally, the page table walk logic has been adjusted, as ARM uses the
>> opposite number of levels compared to RISC-V.
> As before, I think you mean "numbering".

Yes, level numbering would be better.

>
>> --- a/xen/arch/riscv/p2m.c
>> +++ b/xen/arch/riscv/p2m.c
>> @@ -539,6 +539,91 @@ static void p2m_free_subtree(struct p2m_domain *p2m,
>>       p2m_free_page(p2m, pg);
>>   }
>>   
>> +static bool p2m_split_superpage(struct p2m_domain *p2m, pte_t *entry,
>> +                                unsigned int level, unsigned int target,
>> +                                const unsigned int *offsets)
>> +{
>> +    struct page_info *page;
>> +    unsigned long i;
>> +    pte_t pte, *table;
>> +    bool rv = true;
>> +
>> +    /* Convenience aliases */
>> +    mfn_t mfn = pte_get_mfn(*entry);
>> +    unsigned int next_level = level - 1;
>> +    unsigned int level_order = XEN_PT_LEVEL_ORDER(next_level);
>> +
>> +    /*
>> +     * This should only be called with target != level and the entry is
>> +     * a superpage.
>> +     */
>> +    ASSERT(level > target);
>> +    ASSERT(pte_is_superpage(*entry, level));
>> +
>> +    page = p2m_alloc_page(p2m->domain);
>> +    if ( !page )
>> +    {
>> +        /*
>> +         * The caller is in charge to free the sub-tree.
>> +         * As we didn't manage to allocate anything, just tell the
>> +         * caller there is nothing to free by invalidating the PTE.
>> +         */
>> +        memset(entry, 0, sizeof(*entry));
>> +        return false;
>> +    }
>> +
>> +    table = __map_domain_page(page);
>> +
>> +    /*
>> +     * We are either splitting a second level 1G page into 512 first level
>> +     * 2M pages, or a first level 2M page into 512 zero level 4K pages.
>> +     */
> Such a comment is at risk of (silently) going stale when support for 512G
> mappings is added. I wonder if it's really that informative to have here.

Good point, I think we could really drop it.
Regarding support for 512G mappings. Is it really make sense to support
such big mappings? It seems like some operations as splitting or sub-entry
freeing could be pretty long under some circumstances.

>
>> +    for ( i = 0; i < XEN_PT_ENTRIES; i++ )
>> +    {
>> +        pte_t *new_entry = table + i;
>> +
>> +        /*
>> +         * Use the content of the superpage entry and override
>> +         * the necessary fields. So the correct permission are kept.
>> +         */
> It's not just permissions though? The memory type field also needs
> retaining (and is being retained this way). Maybe better say "attributes"?

Sure, I'll use "attributes" instead.

Thanks.

~ Oleksii

--------------wMBQ7AGjueSMXPSR5FEb2k5o
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 8bit



  
    
  
  
    

    
    
    
    
    On 8/11/25 1:59 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    Add support for down large memory mappings ("superpages") in the RISC-V
p2m mapping so that smaller, more precise mappings ("finer-grained entries")
can be inserted into lower levels of the page table hierarchy.

To implement that the following is done:
- Introduce p2m_split_superpage(): Recursively shatters a superpage into
  smaller page table entries down to the target level, preserving original
  permissions and attributes.
- p2m_set_entry() updated to invoke superpage splitting when inserting
  entries at lower levels within a superpage-mapped region.

This implementation is based on the ARM code, with modifications to the part
that follows the BBM (break-before-make) approach, some parts are simplified
as according to RISC-V spec:
  It is permitted for multiple address-translation cache entries to co-exist
  for the same address. This represents the fact that in a conventional
  TLB hierarchy, it is possible for multiple entries to match a single
  address if, for example, a page is upgraded to a superpage without first
  clearing the original non-leaf PTE’s valid bit and executing an SFENCE.VMA
  with rs1=x0, or if multiple TLBs exist in parallel at a given level of the
  hierarchy. In this case, just as if an SFENCE.VMA is not executed between
  a write to the memory-management tables and subsequent implicit read of the
  same address: it is unpredictable whether the old non-leaf PTE or the new
  leaf PTE is used, but the behavior is otherwise well defined.
In contrast to the Arm architecture, where BBM is mandatory and failing to
use it in some cases can lead to CPU instability, RISC-V guarantees
stability, and the behavior remains safe — though unpredictable in terms of
which translation will be used.

Additionally, the page table walk logic has been adjusted, as ARM uses the
opposite number of levels compared to RISC-V.

    
      
    
      
    As before, I think you mean "numbering".
    
    
    
    
    Yes, level numbering would be better.


    
    
    
      
    

    
      
    
        
    --- a/xen/arch/riscv/p2m.c
+++ b/xen/arch/riscv/p2m.c
@@ -539,6 +539,91 @@ static void p2m_free_subtree(struct p2m_domain *p2m,
     p2m_free_page(p2m, pg);
 }
 
+static bool p2m_split_superpage(struct p2m_domain *p2m, pte_t *entry,
+                                unsigned int level, unsigned int target,
+                                const unsigned int *offsets)
+{
+    struct page_info *page;
+    unsigned long i;
+    pte_t pte, *table;
+    bool rv = true;
+
+    /* Convenience aliases */
+    mfn_t mfn = pte_get_mfn(*entry);
+    unsigned int next_level = level - 1;
+    unsigned int level_order = XEN_PT_LEVEL_ORDER(next_level);
+
+    /*
+     * This should only be called with target != level and the entry is
+     * a superpage.
+     */
+    ASSERT(level > target);
+    ASSERT(pte_is_superpage(*entry, level));
+
+    page = p2m_alloc_page(p2m->domain);
+    if ( !page )
+    {
+        /*
+         * The caller is in charge to free the sub-tree.
+         * As we didn't manage to allocate anything, just tell the
+         * caller there is nothing to free by invalidating the PTE.
+         */
+        memset(entry, 0, sizeof(*entry));
+        return false;
+    }
+
+    table = __map_domain_page(page);
+
+    /*
+     * We are either splitting a second level 1G page into 512 first level
+     * 2M pages, or a first level 2M page into 512 zero level 4K pages.
+     */

    
      
    
      
    Such a comment is at risk of (silently) going stale when support for 512G
mappings is added. I wonder if it's really that informative to have here.
    
    
    
    
    Good point, I think we could really drop it.
Regarding support for 512G mappings. Is it really make sense to support
such big mappings? It seems like some operations as splitting or sub-entry
freeing could be pretty long under some circumstances.


    
    
    
      
    

    
      
    
        
    +    for ( i = 0; i < XEN_PT_ENTRIES; i++ )
+    {
+        pte_t *new_entry = table + i;
+
+        /*
+         * Use the content of the superpage entry and override
+         * the necessary fields. So the correct permission are kept.
+         */

    
      
    
      
    It's not just permissions though? The memory type field also needs
retaining (and is being retained this way). Maybe better say "attributes"?
    
    
    
    
    Sure, I'll use "attributes" instead.

Thanks.

~ Oleksii

    
  


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Date: Mon, 11 Aug 2025 17:23:17 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH 3/5] CI: Update riscv64 to use Debian Trixie
To: Andrew Cooper ,
 Xen-devel 
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 Shawn Anastasio ,
 Doug Goldstein ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , Victor Lira 
References: <20250809221206.1260861-1-andrew.cooper3@citrix.com>
 <20250809221206.1260861-4-andrew.cooper3@citrix.com>
 <2919f22b-0b0c-488e-b0c6-96b9538e63d9@gmail.com>
 <2e3412e8-9d62-449b-87e6-22d34ce06e30@citrix.com>
Content-Language: en-US
From: Oleksii Kurochko 
In-Reply-To: <2e3412e8-9d62-449b-87e6-22d34ce06e30@citrix.com>

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On 8/11/25 11:56 AM, Andrew Cooper wrote:
> On 11/08/2025 9:43 am, Oleksii Kurochko wrote:
>>
>> On 8/10/25 12:12 AM, Andrew Cooper wrote:
>>> Everything works fine with Debian 13.  Provide two new build jobs, and update
>>> both the randconfig the test jobs.
>>>
>>> Signed-off-by: Andrew Cooper
>>> ---
>>> CC: Anthony PERARD
>>> CC: Michal Orzel
>>> CC: Jan Beulich
>>> CC: Julien Grall
>>> CC: Roger Pau Monné
>>> CC: Stefano Stabellini
>>> CC: Shawn Anastasio
>>> CC: Oleksii Kurochko
>>> CC: Doug Goldstein
>>> CC: Marek Marczykowski-Górecki
>>> CC: Victor Lira
>>>
>>> https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1975929387
>>> ---
>>>   automation/gitlab-ci/build.yaml | 22 ++++++++++++++++++----
>>>   automation/gitlab-ci/test.yaml  |  2 +-
>>>   2 files changed, 19 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
>>> index 3fe539dc5683..f8e45f3467c8 100644
>>> --- a/automation/gitlab-ci/build.yaml
>>> +++ b/automation/gitlab-ci/build.yaml
>>> @@ -329,10 +329,10 @@ debian-13-ppc64le-gcc-debug:
>>>         CONFIG_UBSAN=y
>>>         CONFIG_UBSAN_FATAL=y
>>>   
>>> -debian-12-riscv64-gcc-debug:
>>> +debian-13-riscv64-gcc-debug:
>>>     extends: .gcc-riscv64-cross-build-debug
>>>     variables:
>>> -    CONTAINER: debian:12-riscv64
>>> +    CONTAINER: debian:13-riscv64
>>>       KBUILD_DEFCONFIG: tiny64_defconfig
>>>       HYPERVISOR_ONLY: y
>>>       EXTRA_XEN_CONFIG: |
>>> @@ -727,6 +727,20 @@ debian-12-riscv64-gcc:
>>>       KBUILD_DEFCONFIG: tiny64_defconfig
>>>       HYPERVISOR_ONLY: y
>>>   
>>> +debian-12-riscv64-gcc-debug:
>>> +  extends: .gcc-riscv64-cross-build-debug
>>> +  variables:
>>> +    CONTAINER: debian:12-riscv64
>>> +    KBUILD_DEFCONFIG: tiny64_defconfig
>>> +    HYPERVISOR_ONLY: y
>> Don't you mind to keep an order? So:
>>    debian-12-riscv64-gcc-debug:
>>    ...
>>    debian-13-riscv64-gcc-debug:
>>    ...
> Notice how those 2 hunks are 400 lines apart in the file.
>
> This is deliberate so debian-13-riscv64-gcc-debug (the one needed for
> tests) is scheduled with higher priority than the others.
>
> The diff certainly isn't great, but this is necessary to shorten the
> pipeline.
>
>> Also, it will make a diff a little bit better.
>>
>>> +
>>> +debian-13-riscv64-gcc:
>>> +  extends: .gcc-riscv64-cross-build
>>> +  variables:
>>> +    CONTAINER: debian:13-riscv64
>>> +    KBUILD_DEFCONFIG: tiny64_defconfig
>>> +    HYPERVISOR_ONLY: y
>>> +
>>>   .riscv-fixed-randconfig:
>>>     variables: &riscv-fixed-randconfig
>>>       EXTRA_FIXED_RANDCONFIG: |
>>> @@ -739,10 +753,10 @@ debian-12-riscv64-gcc:
>>>         CONFIG_VM_EVENT=n
>>>         CONFIG_XSM=n
>>>   
>>> -debian-12-riscv64-gcc-randconfig:
>>> +debian-13-riscv64-gcc-randconfig:
>> Are we going to have randconfig build test only for Debian-13?
> We only have finite test capacity.
>
>>>     extends: .gcc-riscv64-cross-build
>>>     variables:
>>> -    CONTAINER: debian:12-riscv64
>>> +    CONTAINER: debian:13-riscv64
>>>       KBUILD_DEFCONFIG: tiny64_defconfig
>>>       RANDCONFIG: y
>>>       <<: *riscv-fixed-randconfig
>>> diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
>>> index 2f6f3affa637..9acd984d294c 100644
>>> --- a/automation/gitlab-ci/test.yaml
>>> +++ b/automation/gitlab-ci/test.yaml
>>> @@ -705,7 +705,7 @@ qemu-smoke-riscv64-gcc:
>>>     script:
>>>       - ./automation/scripts/qemu-smoke-riscv64.sh 2>&1 | tee ${LOGFILE}
>>>     needs:
>>> -    - debian-12-riscv64-gcc-debug
>>> +    - debian-13-riscv64-gcc-debug
>> The same as above, are we going to run smoke tests only for Debian-13?
> Again, test capacity.  Even for x86 and ARM, we only have one main build
> under test.
>
>> If the answer to this and the question above is “yes,†then (probably
>> keeping the order — first debian-12, then debian-13 — for the jobs):
>>   Reviewed-by: Oleksii Kurochko
> Sorry, but rearranging is one thing that can't really happen.  Are you
> happy with my justification?

Yes, I am happy with that. Feel free to add my Reviewed-by.

Thanks for an explanation.

~ Oleksii

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    On 8/11/25 11:56 AM, Andrew Cooper
      wrote:
    
    
    
    
    
      
    On 11/08/2025 9:43 am, Oleksii Kurochko wrote:

    
      
    
        
    
On 8/10/25 12:12 AM, Andrew Cooper wrote:

    
        
    
          
    Everything works fine with Debian 13.  Provide two new build jobs, and update
both the randconfig the test jobs.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Anthony PERARD <anthony.perard@vates.tech>
CC: Michal Orzel <michal.orzel@amd.com>
CC: Jan Beulich <jbeulich@suse.com>
CC: Julien Grall <julien@xen.org>
CC: Roger Pau Monné <roger.pau@citrix.com>
CC: Stefano Stabellini <sstabellini@kernel.org>
CC: Shawn Anastasio <sanastasio@raptorengineering.com>
CC: Oleksii Kurochko <oleksii.kurochko@gmail.com>
CC: Doug Goldstein <cardoe@cardoe.com>
CC: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
CC: Victor Lira <victorm.lira@amd.com>

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1975929387
---
 automation/gitlab-ci/build.yaml | 22 ++++++++++++++++++----
 automation/gitlab-ci/test.yaml  |  2 +-
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
index 3fe539dc5683..f8e45f3467c8 100644
--- a/automation/gitlab-ci/build.yaml
+++ b/automation/gitlab-ci/build.yaml
@@ -329,10 +329,10 @@ debian-13-ppc64le-gcc-debug:
       CONFIG_UBSAN=y
       CONFIG_UBSAN_FATAL=y
 
-debian-12-riscv64-gcc-debug:
+debian-13-riscv64-gcc-debug:
   extends: .gcc-riscv64-cross-build-debug
   variables:
-    CONTAINER: debian:12-riscv64
+    CONTAINER: debian:13-riscv64
     KBUILD_DEFCONFIG: tiny64_defconfig
     HYPERVISOR_ONLY: y
     EXTRA_XEN_CONFIG: |
@@ -727,6 +727,20 @@ debian-12-riscv64-gcc:
     KBUILD_DEFCONFIG: tiny64_defconfig
     HYPERVISOR_ONLY: y
 
+debian-12-riscv64-gcc-debug:
+  extends: .gcc-riscv64-cross-build-debug
+  variables:
+    CONTAINER: debian:12-riscv64
+    KBUILD_DEFCONFIG: tiny64_defconfig
+    HYPERVISOR_ONLY: y

    
        
    
        
    Don't you mind to keep an order? So:
  debian-12-riscv64-gcc-debug:
  ...
  debian-13-riscv64-gcc-debug:
  ...

    
      
    
      
    Notice how those 2 hunks are 400 lines apart in the file.

This is deliberate so debian-13-riscv64-gcc-debug (the one needed for
tests) is scheduled with higher priority than the others.

The diff certainly isn't great, but this is necessary to shorten the
pipeline.


    
      
    
        
    Also, it will make a diff a little bit better.


    
        
    
          
    +
+debian-13-riscv64-gcc:
+  extends: .gcc-riscv64-cross-build
+  variables:
+    CONTAINER: debian:13-riscv64
+    KBUILD_DEFCONFIG: tiny64_defconfig
+    HYPERVISOR_ONLY: y
+
 .riscv-fixed-randconfig:
   variables: &riscv-fixed-randconfig
     EXTRA_FIXED_RANDCONFIG: |
@@ -739,10 +753,10 @@ debian-12-riscv64-gcc:
       CONFIG_VM_EVENT=n
       CONFIG_XSM=n
 
-debian-12-riscv64-gcc-randconfig:
+debian-13-riscv64-gcc-randconfig:

    
        
    
        
    Are we going to have randconfig build test only for Debian-13?

    
      
    
      
    We only have finite test capacity.


    
      
    
        
    
        
    
          
       extends: .gcc-riscv64-cross-build
   variables:
-    CONTAINER: debian:12-riscv64
+    CONTAINER: debian:13-riscv64
     KBUILD_DEFCONFIG: tiny64_defconfig
     RANDCONFIG: y
     <<: *riscv-fixed-randconfig
diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml
index 2f6f3affa637..9acd984d294c 100644
--- a/automation/gitlab-ci/test.yaml
+++ b/automation/gitlab-ci/test.yaml
@@ -705,7 +705,7 @@ qemu-smoke-riscv64-gcc:
   script:
     - ./automation/scripts/qemu-smoke-riscv64.sh 2>&1 | tee ${LOGFILE}
   needs:
-    - debian-12-riscv64-gcc-debug
+    - debian-13-riscv64-gcc-debug

    
        
    
        
    The same as above, are we going to run smoke tests only for Debian-13?

    
      
    
      
    Again, test capacity.  Even for x86 and ARM, we only have one main build
under test.


    
      
    
        
    If the answer to this and the question above is “yes,†then (probably
keeping the order — first debian-12, then debian-13 — for the jobs):
 Reviewed-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

    
      
    
      
    Sorry, but rearranging is one thing that can't really happen.  Are you
happy with my justification?
    
    
    
    
    Yes, I am happy with that. Feel free to add my Reviewed-by.

Thanks for an explanation.

~ Oleksii
    
  


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Date: Mon, 11 Aug 2025 17:32:44 +0200
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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3 17/20] xen/riscv: implement put_page()
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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 <7a7c07d431fc943e655216d389322638a640b2cd.1753973161.git.oleksii.kurochko@gmail.com>
 
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On 8/11/25 2:43 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> Implement put_page(), as it will be used by p2m_put_code().
> I would have ack-ed the code change, but the description is irritating:
> Who or what is p2m_put_code() (going to be)?

It should be p2m_put_*-related code.

>
>> Although CONFIG_STATIC_MEMORY has not yet been introduced for RISC-V,
>> a stub for PGC_static is added to avoid cluttering the code of
>> put_page_nr() with #ifdefs.
> There isn't any put_page_nr() being introduced (anymore), though.

I'll correct the commit message, it should be put_page() here.

Thanks.

~ Oleksii

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    On 8/11/25 2:43 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    Implement put_page(), as it will be used by p2m_put_code().

    
      
    
      
    I would have ack-ed the code change, but the description is irritating:
Who or what is p2m_put_code() (going to be)?
    
    
    
    
    It should be p2m_put_*-related code.


    
    
    
      
    

    
      
    
        
    Although CONFIG_STATIC_MEMORY has not yet been introduced for RISC-V,
a stub for PGC_static is added to avoid cluttering the code of
put_page_nr() with #ifdefs.

    
      
    
      
    There isn't any put_page_nr() being introduced (anymore), though.
    
    
    
    
    I'll correct the commit message, it should be put_page() here.

Thanks.

~ Oleksii
    
  


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Subject: Re: [PATCH v3 18/20] xen/riscv: implement mfn_valid() and page
 reference, ownership handling helpers
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 8/11/25 2:50 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> Implement the mfn_valid() macro to verify whether a given MFN is valid by
>> checking that it falls within the range [start_page, max_page).
>> These bounds are initialized based on the start and end addresses of RAM.
>>
>> As part of this patch, start_page is introduced and initialized with the
>> PFN of the first RAM page.
>> Also, initialize pdx_group_valid() by calling set_pdx_range() when
>> memory banks are being mapped.
>>
>> Also, after providing a non-stub implementation of the mfn_valid() macro,
>> the following compilation errors started to occur:
>>    riscv64-linux-gnu-ld: prelink.o: in function `__next_node':
>>    /build/xen/./include/xen/nodemask.h:202: undefined reference to `page_is_ram_type'
>>    riscv64-linux-gnu-ld: prelink.o: in function `get_free_buddy':
>>    /build/xen/common/page_alloc.c:881: undefined reference to `page_is_ram_type'
>>    riscv64-linux-gnu-ld: prelink.o: in function `alloc_heap_pages':
>>    /build/xen/common/page_alloc.c:1043: undefined reference to `page_get_owner_and_reference'
>>    riscv64-linux-gnu-ld: /build/xen/common/page_alloc.c:1098: undefined reference to `page_is_ram_type'
>>    riscv64-linux-gnu-ld: prelink.o: in function `ns16550_interrupt':
>>    /build/xen/drivers/char/ns16550.c:205: undefined reference to `get_page'
>>    riscv64-linux-gnu-ld: ./.xen-syms.0: hidden symbol `page_get_owner_and_reference' isn't defined
>>    riscv64-linux-gnu-ld: final link failed: bad value
>>    make[2]: *** [arch/riscv/Makefile:35: xen-syms] Error 1
>> To resolve these errors, the following functions have also been introduced,
>> based on their Arm counterparts:
>> - page_get_owner_and_reference() and its variant to safely acquire a
>>    reference to a page and retrieve its owner.
>> - A stub for page_is_ram_type() that currently always returns 0 and asserts
>>    unreachable, as RAM type checking is not yet implemented.
> For this latter part I can only repeat that the code is reachable, and hence it
> is wrong to put ASSERT_UNREACHABLE() there. That's true for Arm's code as well.

I will drop this stuff in the next patch version.

>
>> Signed-off-by: Oleksii Kurochko
> With said line dropped:
> Acked-by: Jan Beulich

Thanks.

~ Oleksii

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    On 8/11/25 2:50 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    Implement the mfn_valid() macro to verify whether a given MFN is valid by
checking that it falls within the range [start_page, max_page).
These bounds are initialized based on the start and end addresses of RAM.

As part of this patch, start_page is introduced and initialized with the
PFN of the first RAM page.
Also, initialize pdx_group_valid() by calling set_pdx_range() when
memory banks are being mapped.

Also, after providing a non-stub implementation of the mfn_valid() macro,
the following compilation errors started to occur:
  riscv64-linux-gnu-ld: prelink.o: in function `__next_node':
  /build/xen/./include/xen/nodemask.h:202: undefined reference to `page_is_ram_type'
  riscv64-linux-gnu-ld: prelink.o: in function `get_free_buddy':
  /build/xen/common/page_alloc.c:881: undefined reference to `page_is_ram_type'
  riscv64-linux-gnu-ld: prelink.o: in function `alloc_heap_pages':
  /build/xen/common/page_alloc.c:1043: undefined reference to `page_get_owner_and_reference'
  riscv64-linux-gnu-ld: /build/xen/common/page_alloc.c:1098: undefined reference to `page_is_ram_type'
  riscv64-linux-gnu-ld: prelink.o: in function `ns16550_interrupt':
  /build/xen/drivers/char/ns16550.c:205: undefined reference to `get_page'
  riscv64-linux-gnu-ld: ./.xen-syms.0: hidden symbol `page_get_owner_and_reference' isn't defined
  riscv64-linux-gnu-ld: final link failed: bad value
  make[2]: *** [arch/riscv/Makefile:35: xen-syms] Error 1
To resolve these errors, the following functions have also been introduced,
based on their Arm counterparts:
- page_get_owner_and_reference() and its variant to safely acquire a
  reference to a page and retrieve its owner.
- A stub for page_is_ram_type() that currently always returns 0 and asserts
  unreachable, as RAM type checking is not yet implemented.

    
      
    
      
    For this latter part I can only repeat that the code is reachable, and hence it
is wrong to put ASSERT_UNREACHABLE() there. That's true for Arm's code as well.
    
    
    
    
    I will drop this stuff in the next patch version.
    
    
    
      
    

    
      
    
        
    Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

    
      
    
      
    With said line dropped:
Acked-by: Jan Beulich <jbeulich@suse.com>
    
    
    
    
    Thanks.

~ Oleksii
    
  


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Message-ID: <12adb163-5f6b-4478-9592-7423b8db69a9@suse.com>
Date: Mon, 11 Aug 2025 17:44:24 +0200
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Subject: Re: [PATCH v3 20/20] xen/riscv: introduce metadata table to store P2M
 type
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <802d757c167121c0a5ae2e529f5a365f779c5e59.1753973161.git.oleksii.kurochko@gmail.com>
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In-Reply-To: <802d757c167121c0a5ae2e529f5a365f779c5e59.1753973161.git.oleksii.kurochko@gmail.com>
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On 31.07.2025 17:58, Oleksii Kurochko wrote:
> RISC-V's PTE has only two available bits that can be used to store the P2M
> type. This is insufficient to represent all the current RISC-V P2M types.
> Therefore, some P2M types must be stored outside the PTE bits.
> 
> To address this, a metadata table is introduced to store P2M types that
> cannot fit in the PTE itself. Not all P2M types are stored in the
> metadata table—only those that require it.
> 
> The metadata table is linked to the intermediate page table via the
> `struct page_info`'s list field of the corresponding intermediate page.
> 
> To simplify the allocation and linking of intermediate and metadata page
> tables, `p2m_{alloc,free}_table()` functions are implemented.
> 
> These changes impact `p2m_split_superpage()`, since when a superpage is
> split, it is necessary to update the metadata table of the new
> intermediate page table — if the entry being split has its P2M type set
> to `p2m_ext_storage` in its `P2M_TYPES` bits.

Oh, this was an aspect I didn't realize when commenting on the name of
the enumerator. I think you want to keep the name for the purpose here,
but you better wouldn't apply relational operators to it (and hence
have a second value to serve that purpose).

> In addition to updating
> the metadata of the new intermediate page table, the corresponding entry
> in the metadata for the original superpage is invalidated.
> 
> Also, update p2m_{get,set}_type to work with P2M types which don't fit
> into PTE bits.
> 
> Signed-off-by: Oleksii Kurochko 

No Suggested-by: or anything?

> --- a/xen/arch/riscv/include/asm/mm.h
> +++ b/xen/arch/riscv/include/asm/mm.h
> @@ -150,6 +150,15 @@ struct page_info
>              /* Order-size of the free chunk this page is the head of. */
>              unsigned int order;
>          } free;
> +
> +        /* Page is used to store metadata: p2m type. */

That's not correct. The page thus described is what the pointer below
points to. Here it's more like "Page is used as an intermediate P2M
page table".

> +        struct {
> +            /*
> +             * Pointer to a page which store metadata for an intermediate page
> +             * table.
> +             */
> +            struct page_info *metadata;
> +        } md;

In the description you say you would re-use the list field.

> --- a/xen/arch/riscv/p2m.c
> +++ b/xen/arch/riscv/p2m.c
> @@ -101,7 +101,16 @@ static int p2m_alloc_root_table(struct p2m_domain *p2m)
>  {
>      struct domain *d = p2m->domain;
>      struct page_info *page;
> -    const unsigned int nr_root_pages = P2M_ROOT_PAGES;
> +    /*
> +     * If the root page table starts at Level <= 2, and since only 1GB, 2MB,
> +     * and 4KB mappings are supported (as enforced by the ASSERT() in
> +     * p2m_set_entry()), it is necessary to allocate P2M_ROOT_PAGES for
> +     * the root page table itself, plus an additional P2M_ROOT_PAGES for
> +     * metadata storage. This is because only two free bits are available in
> +     * the PTE, which are not sufficient to represent all possible P2M types.
> +     */
> +    const unsigned int nr_root_pages = P2M_ROOT_PAGES *
> +                                       ((P2M_ROOT_LEVEL <= 2) ? 2 : 1);
>  
>      /*
>       * Return back nr_root_pages to assure the root table memory is also
> @@ -114,6 +123,23 @@ static int p2m_alloc_root_table(struct p2m_domain *p2m)
>      if ( !page )
>          return -ENOMEM;
>  
> +    if ( P2M_ROOT_LEVEL <= 2 )
> +    {
> +        /*
> +         * In the case where P2M_ROOT_LEVEL <= 2, it is necessary to allocate
> +         * a page of the same size as that used for the root page table.
> +         * Therefore, p2m_allocate_root() can be safely reused.
> +         */
> +        struct page_info *metadata = p2m_allocate_root(d);
> +        if ( !metadata )
> +        {
> +            free_domheap_pages(page, P2M_ROOT_ORDER);
> +            return -ENOMEM;
> +        }
> +
> +        page->v.md.metadata = metadata;

Don't you need to install such a link for every one of the 4 pages?

> @@ -198,24 +224,25 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
>      return __map_domain_page(p2m->root + root_table_indx);
>  }
>  
> -static int p2m_set_type(pte_t *pte, p2m_type_t t)
> +static void p2m_set_type(pte_t *pte, const p2m_type_t t, const unsigned int i)
>  {
> -    int rc = 0;
> -
>      if ( t > p2m_ext_storage )
> -        panic("unimplemeted\n");
> +    {
> +        ASSERT(pte);
> +
> +        pte[i].pte = t;

What does i identify here?

> +    }
>      else
>          pte->pte |= MASK_INSR(t, P2M_TYPE_PTE_BITS_MASK);
> -
> -    return rc;
>  }
>  
> -static p2m_type_t p2m_get_type(const pte_t pte)
> +static p2m_type_t p2m_get_type(const pte_t pte, const pte_t *metadata,
> +                               const unsigned int i)
>  {
>      p2m_type_t type = MASK_EXTR(pte.pte, P2M_TYPE_PTE_BITS_MASK);
>  
>      if ( type == p2m_ext_storage )
> -        panic("unimplemented\n");
> +        type = metadata[i].pte;
>  
>      return type;
>  }

Overall this feels pretty fragile, as the caller has to pass several values
which all need to be in sync with one another. If you ...

> @@ -265,7 +292,10 @@ static void p2m_set_permission(pte_t *e, p2m_type_t t)
>      }
>  }
>  
> -static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
> +static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t,
> +                              struct page_info *metadata_pg,
> +                              const unsigned int indx,
> +                              bool is_table)
>  {
>      pte_t e = (pte_t) { PTE_VALID };
>  
> @@ -285,12 +315,21 @@ static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
>  
>      if ( !is_table )
>      {
> +        pte_t *metadata = __map_domain_page(metadata_pg);

... map the page anyway, no matter whether ...

>          p2m_set_permission(&e, t);
>  
> +        metadata[indx].pte = p2m_invalid;
> +
>          if ( t < p2m_ext_storage )
> -            p2m_set_type(&e, t);
> +            p2m_set_type(&e, t, indx);
>          else
> -            panic("unimplemeted\n");
> +        {
> +            e.pte |= MASK_INSR(p2m_ext_storage, P2M_TYPE_PTE_BITS_MASK);
> +            p2m_set_type(metadata, t, indx);
> +        }

... you'll actually use it, maybe best to map both pages at the same point?

And as said elsewhere, no, I don't think you want to use p2m_set_type() for
two entirely different purposes.

> @@ -323,22 +364,71 @@ static struct page_info *p2m_alloc_page(struct p2m_domain *p2m)
>      return pg;
>  }
>  
> +static void p2m_free_page(struct p2m_domain *p2m, struct page_info *pg);
> +
> +/*
> + * Allocate a page table with an additional extra page to store
> + * metadata for each entry of the page table.
> + * Link this metadata page to page table page's list field.
> + */
> +static struct page_info * p2m_alloc_table(struct p2m_domain *p2m)

Nit: Stray blank after * again.

> +{
> +    enum table_type
> +    {
> +        INTERMEDIATE_TABLE=0,

If you really think you need the "= 0", then please with blanks around '='.

> +        /*
> +         * At the moment, metadata is going to store P2M type
> +         * for each PTE of page table.
> +         */
> +        METADATA_TABLE,
> +        TABLE_MAX
> +    };
> +
> +    struct page_info *tables[TABLE_MAX];
> +
> +    for ( unsigned int i = 0; i < TABLE_MAX; i++ )
> +    {
> +        tables[i] = p2m_alloc_page(p2m);
> +
> +        if ( !tables[i] )
> +            goto out;
> +
> +        clear_and_clean_page(tables[i]);
> +    }
> +
> +    tables[INTERMEDIATE_TABLE]->v.md.metadata = tables[METADATA_TABLE];
> +
> +    return tables[INTERMEDIATE_TABLE];
> +
> + out:
> +    for ( unsigned int i = 0; i < TABLE_MAX; i++ )
> +        if ( tables[i] )

You didn't clear all of tables[] first, though. This kind of cleanup is
often better done as

    while ( i-- > 0 )
        ...

You don't even need an if() then, as you know allocations succeeded for all
earlier array slots.

> +            p2m_free_page(p2m, tables[i]);
> +
> +    return NULL;
> +}

I'm also surprised you allocate the metadata table no matter whether you'll
actually need it. That'll double your average paging pool usage, when in a
typical case only very few entries would actually require this extra
storage.

> @@ -453,10 +543,9 @@ static void p2m_put_2m_superpage(mfn_t mfn, p2m_type_t type)
>  }
>  
>  /* Put any references on the page referenced by pte. */
> -static void p2m_put_page(const pte_t pte, unsigned int level)
> +static void p2m_put_page(const pte_t pte, unsigned int level, p2m_type_t p2mt)
>  {
>      mfn_t mfn = pte_get_mfn(pte);
> -    p2m_type_t p2m_type = p2m_get_type(pte);
>  
>      ASSERT(pte_is_valid(pte));
>  
> @@ -470,10 +559,10 @@ static void p2m_put_page(const pte_t pte, unsigned int level)
>      switch ( level )
>      {
>      case 1:
> -        return p2m_put_2m_superpage(mfn, p2m_type);
> +        return p2m_put_2m_superpage(mfn, p2mt);
>  
>      case 0:
> -        return p2m_put_4k_page(mfn, p2m_type);
> +        return p2m_put_4k_page(mfn, p2mt);
>      }
>  }

Might it be better to introduce this function in this shape right away, in
the earlier patch?

> @@ -690,18 +791,23 @@ static int p2m_set_entry(struct p2m_domain *p2m,
>      {
>          /* We need to split the original page. */
>          pte_t split_pte = *entry;
> +        struct page_info *metadata = virt_to_page(table)->v.md.metadata;

This (or along these lines) is how I would have expected things to be done
elsewhere as well, limiting the amount of arguments you need to pass
around.

Jan


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Subject: Re: [PATCH v3 16/20] xen/riscv: Implement superpage splitting for p2m
 mappings
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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On 11.08.2025 17:19, Oleksii Kurochko wrote:
> On 8/11/25 1:59 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> --- a/xen/arch/riscv/p2m.c
>>> +++ b/xen/arch/riscv/p2m.c
>>> @@ -539,6 +539,91 @@ static void p2m_free_subtree(struct p2m_domain *p2m,
>>>       p2m_free_page(p2m, pg);
>>>   }
>>>   
>>> +static bool p2m_split_superpage(struct p2m_domain *p2m, pte_t *entry,
>>> +                                unsigned int level, unsigned int target,
>>> +                                const unsigned int *offsets)
>>> +{
>>> +    struct page_info *page;
>>> +    unsigned long i;
>>> +    pte_t pte, *table;
>>> +    bool rv = true;
>>> +
>>> +    /* Convenience aliases */
>>> +    mfn_t mfn = pte_get_mfn(*entry);
>>> +    unsigned int next_level = level - 1;
>>> +    unsigned int level_order = XEN_PT_LEVEL_ORDER(next_level);
>>> +
>>> +    /*
>>> +     * This should only be called with target != level and the entry is
>>> +     * a superpage.
>>> +     */
>>> +    ASSERT(level > target);
>>> +    ASSERT(pte_is_superpage(*entry, level));
>>> +
>>> +    page = p2m_alloc_page(p2m->domain);
>>> +    if ( !page )
>>> +    {
>>> +        /*
>>> +         * The caller is in charge to free the sub-tree.
>>> +         * As we didn't manage to allocate anything, just tell the
>>> +         * caller there is nothing to free by invalidating the PTE.
>>> +         */
>>> +        memset(entry, 0, sizeof(*entry));
>>> +        return false;
>>> +    }
>>> +
>>> +    table = __map_domain_page(page);
>>> +
>>> +    /*
>>> +     * We are either splitting a second level 1G page into 512 first level
>>> +     * 2M pages, or a first level 2M page into 512 zero level 4K pages.
>>> +     */
>> Such a comment is at risk of (silently) going stale when support for 512G
>> mappings is added. I wonder if it's really that informative to have here.
> 
> Good point, I think we could really drop it.
> Regarding support for 512G mappings. Is it really make sense to support
> such big mappings?

I think so, yes (in the longer run). And yes, ...

> It seems like some operations as splitting or sub-entry
> freeing could be pretty long under some circumstances.

... such will need sorting.

Jan


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Subject: Re: [PATCH -next v7 2/7] arm64: entry: Refactor the entry and exit
 for exceptions from EL1
To: Jinjie Ruan 
Cc: catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com,
 sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org,
 broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com,
 akpm@linux-foundation.org, chenl311@chinatelecom.cn,
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References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 <20250729015456.3411143-3-ruanjinjie@huawei.com>
 
 <6825c4c4-2c48-db3b-55e2-97922f25897f@huawei.com>
From: Ada Couprie Diaz 
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On 06/08/2025 03:49, Jinjie Ruan wrote:

> On 2025/8/5 23:06, Ada Couprie Diaz wrote:
>> Hi,
>>
>> On 29/07/2025 02:54, Jinjie Ruan wrote:
>>
>>> [...]
>>> diff --git a/arch/arm64/kernel/entry-common.c
>>> b/arch/arm64/kernel/entry-common.c
>>> index 8e798f46ad28..97e0741abde1 100644
>>> --- a/arch/arm64/kernel/entry-common.c
>>> +++ b/arch/arm64/kernel/entry-common.c
>>> [...]
>>> @@ -475,73 +497,81 @@ UNHANDLED(el1t, 64, error)
>>>    static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
>>>    {
>>>        unsigned long far = read_sysreg(far_el1);
>>> +    arm64_irqentry_state_t state;
>>>    -    enter_from_kernel_mode(regs);
>>> +    state = enter_from_kernel_mode(regs);
>> Nit: There is some inconsistencies with some functions splitting state's
>> definition
>> and declaration (like el1_abort here), while some others do it on the
>> same line
>> (el1_undef() below for example).
>> In some cases it is welcome as the entry function is called after some
>> other work,
>> but here for example it doesn't seem to be beneficial ?
> Both methods can keep the modifications to `enter_from_kernel_mode()` on
> the same line as the original code, which will facilitate code review.
>
> I think it is also fine to do it on the same line here, which can reduce
> one line code, which method is better may be a matter of personal opinion.
Fair point !
Then, as mentioned previously, I'm happy to leave my Reviewed-By.
>>>        local_daif_inherit(regs);
>>>        do_mem_abort(far, esr, regs);
>>>        local_daif_mask();
>>> -    exit_to_kernel_mode(regs);
>>> +    exit_to_kernel_mode(regs, state);
>>>    }
>>>      static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr)
>>>    {
>>>        unsigned long far = read_sysreg(far_el1);
>>> +    arm64_irqentry_state_t state;
>>>    -    enter_from_kernel_mode(regs);
>>> +    state = enter_from_kernel_mode(regs);
>>>        local_daif_inherit(regs);
>>>        do_sp_pc_abort(far, esr, regs);
>>>        local_daif_mask();
>>> -    exit_to_kernel_mode(regs);
>>> +    exit_to_kernel_mode(regs, state);
>>>    }
>>>      static void noinstr el1_undef(struct pt_regs *regs, unsigned long
>>> esr)
>>>    {
>>> -    enter_from_kernel_mode(regs);
>>> +    arm64_irqentry_state_t state = enter_from_kernel_mode(regs);
>>> +
>>>        local_daif_inherit(regs);
>>>        do_el1_undef(regs, esr);
>>>        local_daif_mask();
>>> -    exit_to_kernel_mode(regs);
>>> +    exit_to_kernel_mode(regs, state);
>>>    }
>>>
>>> [...]
>> Other than the small nit:
>> Reviewed-by: Ada Couprie Diaz 


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Subject: Re: [PATCH -next v7 5/7] arm64: entry: Refactor
 preempt_schedule_irq() check code
To: Jinjie Ruan 
Cc: catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com,
 sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org,
 broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com,
 akpm@linux-foundation.org, chenl311@chinatelecom.cn,
 anshuman.khandual@arm.com, kristina.martsenko@arm.com,
 liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org,
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 xen-devel@lists.xenproject.org, Ada Couprie Diaz 
References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 <20250729015456.3411143-6-ruanjinjie@huawei.com>
 <44fd646c-4e31-4ca6-9e22-f715ad19e0d7@arm.com>
 
From: Ada Couprie Diaz 
Content-Language: en-US
Organization: Arm Ltd.
In-Reply-To: 
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On 06/08/2025 07:39, Jinjie Ruan wrote:

> On 2025/8/5 23:06, Ada Couprie Diaz wrote:
>> Hi Jinjie,
>>
>> On 29/07/2025 02:54, Jinjie Ruan wrote:
>>> ARM64 requires an additional check whether to reschedule on return
>>> from interrupt. So add arch_irqentry_exit_need_resched() as the default
>>> NOP implementation and hook it up into the need_resched() condition in
>>> raw_irqentry_exit_cond_resched(). This allows ARM64 to implement
>>> the architecture specific version for switching over to
>>> the generic entry code.
>>> [...]
>> I've had some trouble reviewing this patch : on the one hand because
>> I didn't notice `arch_irqentry_exit_need_resched()` was added in
>> the common entry code, which is on me !
>> On the other hand, I felt that the patch itself was a bit disconnected :
>> we add `arch_irqentry_exit_need_resched()` in the common entry code,
>> with a default NOP, but in the same function we add to arm64,
>> while mentioning that this is for arm64's additional checks,
>> which we only implement in patch 7.
> Yes, it does.
>
>> Would it make sense to move the `arch_irqentry_exit_need_resched()`
>> part of the patch to patch 7, so that the introduction and
>> arch-specific implementation appear together ?
>> To me it seems easier to wrap my head around, as it would look like
>> "Move arm64 to generic entry, but it does additional checks : add a new
>> arch-specific function controlling re-scheduling, defaulting to true,
>> and implement it for arm64". I feel it could help making patch 7's
>> commit message clearer as well.
>>
>>  From what I gathered on the archive `arch_irqentry_exit_need_resched()`
>> being added here was suggested previously, so others might not have the
>> same opinion.
> Yes, introduce `arch_irqentry_exit_need_resched()` here may help
> understand the patch's refactoring purpose.
I can see that as well.
I shared my opinion in case it could be useful, but as I mentioned
in my reply to the cover : it's not a big issue and I'm happy for
`arch_irqentry_exit_need_resched()` to be implemented here if that
makes more sense !
>> Maybe improving the commit message and comment for this would be enough
>> as well, as per my suggestions above.
> Thank you! I'll improve the commit message and comment.
>
My pleasure !
Ada


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Date: Mon, 11 Aug 2025 17:02:42 +0100
MIME-Version: 1.0
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Subject: Re: [PATCH -next v7 5/7] arm64: entry: Refactor
 preempt_schedule_irq() check code
To: Jinjie Ruan 
References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 <20250729015456.3411143-6-ruanjinjie@huawei.com>
From: Ada Couprie Diaz 
Cc: catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com,
 sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org,
 broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com,
 akpm@linux-foundation.org, chenl311@chinatelecom.cn,
 anshuman.khandual@arm.com, kristina.martsenko@arm.com,
 liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org,
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 xen-devel@lists.xenproject.org, Ada Couprie Diaz 
Content-Language: en-US
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In-Reply-To: <20250729015456.3411143-6-ruanjinjie@huawei.com>
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On 29/07/2025 02:54, Jinjie Ruan wrote:

> ARM64 requires an additional check whether to reschedule on return
> from interrupt. So add arch_irqentry_exit_need_resched() as the default
> NOP implementation and hook it up into the need_resched() condition in
> raw_irqentry_exit_cond_resched(). This allows ARM64 to implement
> the architecture specific version for switching over to
> the generic entry code.
>
> To align the structure of the code with irqentry_exit_cond_resched()
> from the generic entry code, hoist the need_irq_preemption()
> and IS_ENABLED() check earlier. And different preemption check functions
> are defined based on whether dynamic preemption is enabled.
>
> Suggested-by: Mark Rutland 
> Suggested-by: Kevin Brodsky 
> Suggested-by: Thomas Gleixner 
> Signed-off-by: Jinjie Ruan 
> ---
Unrelated to the other thread : I noticed that compiling this patch
with `allnoconfig` would fail :
- `raw_irqentry_exit_cond_resched` has no previous prototype,
   as it is defined within `#ifdef CONFIG_PREEMPTION`
- `irqentry_exit_cond_resched()` is not declared, as it is also within
   `#ifdef CONFIG_PREEMPTION`

The patch below fixes the issue, but introduces merge conflicts in
patches 6 and 7, plus the `#ifdef` needs to be moved accordingly
in patch 6 and the empty "without preemption" `irq_exit_cond_resched()`
needs to be removed in patch 7.

I hope this can be useful,
Ada

---
diff --git a/arch/arm64/include/asm/preempt.h 
b/arch/arm64/include/asm/preempt.h
index 0f0ba250efe8..d9aba8b1e466 100644
--- a/arch/arm64/include/asm/preempt.h
+++ b/arch/arm64/include/asm/preempt.h
@@ -103,6 +103,8 @@ void dynamic_irqentry_exit_cond_resched(void);
  #define irqentry_exit_cond_resched() raw_irqentry_exit_cond_resched()

  #endif /* CONFIG_PREEMPT_DYNAMIC */
+#else /* CONFIG_PREEMPTION */
+#define irqentry_exit_cond_resched() {}
  #endif /* CONFIG_PREEMPTION */

  #endif /* __ASM_PREEMPT_H */
diff --git a/arch/arm64/kernel/entry-common.c 
b/arch/arm64/kernel/entry-common.c
index 4f92664fd46c..abd7a315145e 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -661,6 +661,7 @@ static __always_inline void __el1_pnmi(struct 
pt_regs *regs,
         arm64_exit_nmi(regs, state);
  }

+#ifdef CONFIG_PREEMPTION
  void raw_irqentry_exit_cond_resched(void)
  {
         if (!preempt_count()) {
@@ -668,6 +669,7 @@ void raw_irqentry_exit_cond_resched(void)
                         preempt_schedule_irq();
         }
  }
+#endif

  #ifdef CONFIG_PREEMPT_DYNAMIC
  DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);



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Subject: Re: [PATCH -next v7 0/7] arm64: entry: Convert to generic irq entry
To: Jinjie Ruan 
Cc: catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com,
 sstabellini@kernel.org, mark.rutland@arm.com, puranjay@kernel.org,
 broonie@kernel.org, mbenes@suse.cz, ryan.roberts@arm.com,
 akpm@linux-foundation.org, chenl311@chinatelecom.cn,
 anshuman.khandual@arm.com, kristina.martsenko@arm.com,
 liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org,
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 xen-devel@lists.xenproject.org, Ada Couprie Diaz 
References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 <6bd09b5b-9830-42b4-ad9e-9ad1e153e564@arm.com>
 <94757d00-5a8e-ac6b-f832-030f33ccf771@huawei.com>
From: Ada Couprie Diaz 
Content-Language: en-US
Organization: Arm Ltd.
In-Reply-To: <94757d00-5a8e-ac6b-f832-030f33ccf771@huawei.com>
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On 06/08/2025 09:11, Jinjie Ruan wrote:

> On 2025/8/5 23:08, Ada Couprie Diaz wrote:
>> Hi Jinjie,
>>
>> On 29/07/2025 02:54, Jinjie Ruan wrote:
>>
>>> Since commit a70e9f647f50 ("entry: Split generic entry into generic
>>> exception and syscall entry") split the generic entry into generic irq
>>> entry and generic syscall entry, it is time to convert arm64 to use
>>> the generic irq entry. And ARM64 will be completely converted to generic
>>> entry in the upcoming patch series.
>> Note : I had to manually cherry-pick a70e9f647f50 when pulling the series
>> on top of the Linux Arm Kernel for-next/core branch, but there might be
>> something I'm missing here.
> It seems that it is now in mainline v6.16-rc1 and linux-next but not
> Linux Arm Kernel for-next/core branch.
You're right, I misinterpreted the `-next` of the subject, thanks for the
clarification !
>> I'll spend some time testing the series now, specifically given patch 6's
>> changes, but other than that everything I saw made sense and didn't look
>> like it would be of concern to me.
> Thank you for the test and review.

I've spent some time testing the series with a few different configurations,
including PREEMPT_RT, pNMI, various lockup and hang detection options,
UBSAN, shadow call stack, and various CONFIG_DEBUG_XYZ (focused on locks
and IRQs), on both hardware (AMD Seattle) and KVM guests.

I tried to generate a diverse set of interrupts (via debug exceptions,
page faults, perf, kprobes, swapping, OoM) while loading the system with
different workloads, some generating a lot of context switches : hackbench
and signaltest from rt-tests[0], and mc-crusher[1], a memcached stress-test.

I did not have any issues, nor any warning reported by the various
debug features during all my hours of testing, so it looks good !

Tested-by: Ada Couprie Diaz 

Thank you for the series !
Ada

[0]: https://git.kernel.org/pub/scm/utils/rt-tests/rt-tests.git/
[1]: https://github.com/memcached/mc-crusher



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Date: Mon, 11 Aug 2025 17:42:41 +0100
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Subject: Re: [PATCH v4 2/8] pdx: provide a unified set of unit functions
Content-Language: en-GB
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Cc: xen-devel@lists.xenproject.org,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich 
References: <20250805095257.74975-1-roger.pau@citrix.com>
 <20250805095257.74975-3-roger.pau@citrix.com>
 <5b940bdf-9bc0-49b2-af92-7251b2780c71@xen.org>
 
From: Julien Grall 
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Hi Roger,

On 11/08/2025 09:07, Roger Pau Monné wrote:
> On Fri, Aug 08, 2025 at 06:21:29PM +0100, Julien Grall wrote:
>> Hi Roger,
>>
>> On 05/08/2025 10:52, Roger Pau Monne wrote:
>>> diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
>>> index a77b31071ed8..ba35bf1fe3bb 100644
>>> --- a/xen/arch/arm/setup.c
>>> +++ b/xen/arch/arm/setup.c
>>> @@ -256,9 +256,11 @@ void __init init_pdx(void)
>>>    {
>>>        const struct membanks *mem = bootinfo_get_mem();
>>>        paddr_t bank_start, bank_size, bank_end, ram_end = 0;
>>> -    int bank;
>>> +    unsigned int bank;
>>>    #ifndef CONFIG_PDX_NONE
>>> +    for ( bank = 0 ; bank < mem->nr_banks; bank++ )
>>> +        pfn_pdx_add_region(mem->bank[bank].start, mem->bank[bank].size);
>>>        /*
>>>         * Arm does not have any restrictions on the bits to compress. Pass 0 to
>>>         * let the common code further restrict the mask.
>>> @@ -266,26 +268,24 @@ void __init init_pdx(void)
>>>         * If the logic changes in pfn_pdx_hole_setup we might have to
>>>         * update this function too.
>>>         */
>>> -    uint64_t mask = pdx_init_mask(0x0);
>>> -
>>> -    for ( bank = 0 ; bank < mem->nr_banks; bank++ )
>>> -    {
>>> -        bank_start = mem->bank[bank].start;
>>> -        bank_size = mem->bank[bank].size;
>>> -
>>> -        mask |= bank_start | pdx_region_mask(bank_start, bank_size);
>>> -    }
>>> +    pfn_pdx_compression_setup(0);
>>>        for ( bank = 0 ; bank < mem->nr_banks; bank++ )
>>>        {
>>> -        bank_start = mem->bank[bank].start;
>>> -        bank_size = mem->bank[bank].size;
>>> -
>>> -        if (~mask & pdx_region_mask(bank_start, bank_size))
>>> -            mask = 0;
>>> +        if ( !pdx_is_region_compressible(
>>> +                  mem->bank[bank].start,
>>> +                  PFN_UP(mem->bank[bank].start + mem->bank[bank].size) -
>>> +                  PFN_DOWN(mem->bank[bank].start)) )
>>
>> This code is a bit too verbose. Can we at least introduce "bank =
>> &mem->bank[bank]" to reduce a bit the verbosity?
> 
> I cannot introduce a `bank` local variable as it's already used as the
> index cursor for the loop.  Would you be fine with:

Ah yes. I am fine with the logic below. I am happy if you want to commit 
message without resending the series.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH] Arm: drop assertion from page_is_ram_type()
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To: Jan Beulich ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini ,
 Volodymyr Babchuk ,
 Bertrand Marquis ,
 Michal Orzel ,
 Oleksii Kurochko 
References: <804094ae-bb76-4165-9e07-46b775b4b46e@suse.com>
From: Julien Grall 
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Hi Jan,

On 11/08/2025 14:01, Jan Beulich wrote:
> Its uses in offline_page() and query_page_offline() make it reachable on
> Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
> code added. It being reachable was even mentioned in the commit
> introducing it, claiming it "clearly shouldn't be called on ARM just
> yet".

So I agree that the function can be reached. But then I don't think the 
function can simply return 0.

The name is too generic enough that someone may end up to use it in 
common code and there will be no signal to the user that the function 
will not properly indicate a RAM page on Arm.

I can think of two possible approaches:

1/ Implement properly page_is_ram_type(). We don't have an e820, but we 
could mimick it using the memory banks we stored.
2/ Rename page_is_ram_type() to page_offlinable() (or similar) so it is 
clear that the common use is for offlining.

The latter might be the simplest.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v2] xen/arm: irq: add missing spin_unlock() in
 init_local_irq_data() error path
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To: Mykola Kvach , xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Denis Mukhin 
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Hi Mykola,

On 11/08/2025 09:45, Mykola Kvach wrote:
> From: Mykola Kvach 
> 
> If init_one_irq_desc() fails, init_local_irq_data() returns without
> releasing local_irqs_type_lock, leading to a possible deadlock.
> 
> Release the lock before returning to ensure proper cleanup.
> 
> Fixes: 2bb32b809250 ("xen/irq: Propagate the error from init_one_desc_irq() in init_*_irq_data()")
> Signed-off-by: Mykola Kvach 
> Reviewed-by: Denis Mukhin 

Acked-by: Julien Grall 

I will commit the patch soon.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v5 1/2] xen/arm: fix arm_iommu_map_page after f9f6b22abf1d
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To: Stewart Hildebrand ,
 xen-devel@lists.xenproject.org
Cc: Stefano Stabellini ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: <20250725140130.4008-1-stewart.hildebrand@amd.com>
 <5fab90b6-7cae-45d0-bb8e-b1ffa0390b6f@xen.org>
 <7a3a08f4-c08e-4490-a033-53e81b261181@amd.com>
From: Julien Grall 
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Hi Stewart,

On 06/08/2025 14:58, Stewart Hildebrand wrote:
> On 7/26/25 05:23, Julien Grall wrote:
>> Hi,
>>
>> On 25/07/2025 15:01, Stewart Hildebrand wrote:
>>> From: Stefano Stabellini 
>>>
>>> Up until f9f6b22abf1d "xen/arm: Map ITS doorbell register to IOMMU page
>>> tables" the only caller of iommu_map on ARM was grant_table.c which has
>>> a specific usage model and restrictions as described by the in-code
>>> comment in arm_iommu_map_page.
>>>
>>> f9f6b22abf1d introduced a second caller to iommu_map on ARM:
>>> vgic_v3_its_init_virtual. This specific statement in the
>>> f9f6b22abf1d commit message is partially wrong:
>>>
>>> "Note that the 1:1 check in arm_iommu_map_page remains for now, as
>>> virtual ITSes are currently only created for hwdom where the doorbell
>>> mapping is always 1:1."
>>>
>>> Leading to crashes any time the hardware domain is not direct-mapped
>>> (e.g. cache coloring and non-Dom0 hardware domain):
>>>
>>> (XEN) Xen BUG at drivers/passthrough/arm/iommu_helpers.c:47
>>> [...]
>>> (XEN) Xen call trace:
>>> (XEN)    [<00000a000024c758>] arm_iommu_map_page+0x80/0x90 (PC)
>>> (XEN)    [<00000a000024c750>] arm_iommu_map_page+0x78/0x90 (LR)
>>> (XEN)    [<00000a0000250884>] iommu_map+0xcc/0x29c
>>> (XEN)    [<00000a0000288024>] vgic_v3_its_init_domain+0x18c/0x1e8
>>> (XEN)    [<00000a0000285228>] vgic-v3.c#vgic_v3_domain_init+0x168/0x21c
>>> (XEN)    [<00000a0000281dcc>] domain_vgic_init+0x14c/0x210
>>> (XEN)    [<00000a00002705a4>] arch_domain_create+0x150/0x1f0
>>> (XEN)    [<00000a00002055e8>] domain_create+0x47c/0x6c0
>>> (XEN)    [<00000a00002cf090>] create_domUs+0x7f8/0x8cc
>>> (XEN)    [<00000a00002eb588>] start_xen+0x8f4/0x998
>>> (XEN)    [<00000a000020018c>] head.o#primary_switched+0x4/0x10
>>>
>>> Specifically, non-1:1 hardware domain exists with cache coloring
>>> enabled. For that, is_domain_direct_mapped(d) is false but
>>> domain_use_host_layout(d) is true.
>>>
>>> Change the is_domain_direct_mapped(d) checks in arm_iommu_map_page and
>>> arm_iommu_unmap_page into domain_use_host_layout(d) checks.
>>>
>>> Drop stale in-code comment specific to grant table mappings.
>>>
>>> Fixes: f9f6b22abf1d ("xen/arm: Map ITS doorbell register to IOMMU page tables")
>>> Signed-off-by: Stefano Stabellini 
>>> Signed-off-by: Stewart Hildebrand 
>>
>> Reviewed-by: Julien Grall 
> 
> Thanks for the review! Is this ready to be committed?

Yes. Sorry, this fell through the cracks. I have queue the patch for 
testing and committing.

Cheers,

-- 
Julien Grall



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Date: Mon, 11 Aug 2025 19:33:32 +0200
From: Nicola Vetrini 
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Cc: nicola.vetrini@gmail.com, xen-devel@lists.xenproject.org, Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Jan Beulich , Julien
 Grall , Stefano Stabellini 
Subject: Re: [XEN PATCH] xen: Drop logic for old clang versions.
In-Reply-To: 
References: 
 
 <2ca7082120df5e1ad6a29582d6dfb215@bugseng.com>
 
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On 2025-08-11 16:35, Roger Pau Monné wrote:
> On Mon, Aug 11, 2025 at 11:37:46AM +0200, Nicola Vetrini wrote:
>> On 2025-08-11 09:47, Roger Pau Monné wrote:
>> > On Sun, Aug 10, 2025 at 03:03:53PM +0200, nicola.vetrini@gmail.com
>> > wrote:
>> > > From: Nicola Vetrini 
>> > >
>> > > The enforced toolchain baseline for clang is version 11,
>> > > therefore this logic is effectively dead code.
>> > >
>> > > No functional change.
>> > >
>> > > Signed-off-by: Nicola Vetrini 
>> >
>> > Acked-by: Roger Pau Monné 
>> >
>> > > ---
>> > > Mentioned in https://gitlab.com/xen-project/xen/-/issues/201
>> > > ---
>> > >  xen/common/coverage/llvm.c   | 4 ----
>> > >  xen/include/xen/self-tests.h | 9 +--------
>> > >  2 files changed, 1 insertion(+), 12 deletions(-)
>> > >
>> > > diff --git a/xen/common/coverage/llvm.c b/xen/common/coverage/llvm.c
>> > > index 50d7a3c5d301..517b2aa8c202 100644
>> > > --- a/xen/common/coverage/llvm.c
>> > > +++ b/xen/common/coverage/llvm.c
>> > > @@ -44,12 +44,8 @@
>> > >      ((uint64_t)'f' << 16) | ((uint64_t)'R' << 8)  | ((uint64_t)129)
>> > >  #endif
>> > >
>> > > -#if __clang_major__ >= 4 || (__clang_major__ == 3 &&
>> > > __clang_minor__ >= 9)
>> > >  #define LLVM_PROFILE_VERSION    4
>> > >  #define LLVM_PROFILE_NUM_KINDS  2
>> > > -#else
>> > > -#error "clang version not supported with coverage"
>> > > -#endif
>> >
>> > Rant: most of the LLVM coverage stuff is already kind of dead code, as
>> > the format of the data changes between versions and there's no way for
>> > LLVM to generate the blob itself using a builtin function or
>> > similar.  We haven't kept up with new formats, and now it's not
>> > possible to parse the output coverage data when using newish LLVM
>> > versions.
>> >
>> > Linux converts it's LLVM coverage data to gcov format (which AFAIK is
>> > way more stable), and exports it in gcov format.  We should consider
>> > importing that from Linux.
>> >
>> > Thanks, Roger.
>> 
>> Fair point. Generally I found coverage reports generated using LLVM 
>> tooling
>> a bit more informative than gcov's, but I don't know how much work 
>> would it
>> be to adapt Xen for newer versions of LLVM.
> 
> It's a pain because they keep changing the blob format between
> versions, so we would basically need code in Xen to be able to
> generate the right blob for each possible clang version.
> 
> It would be helpful if clang provided the helpers to generate the
> coverage data in a version agnostic way, but so far I haven't found a
> way to do it.  I've raised a question with upstream LLVM project, but
> no replies:
> 
> https://github.com/llvm/llvm-project/issues/123034
> 
> Regards, Roger.

Perhaps the "coverage" and "llvm-cov" tag might help get more traction; 
there is at least one developer working on the source-based code 
coverage area in the past months with various improvements.

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Andrew Cooper
	
Subject: [PATCH] misra: comment default case in single-clause switch
Thread-Topic: [PATCH] misra: comment default case in single-clause switch
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Date: Mon, 11 Aug 2025 17:36:52 +0000
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MISRA Rule 16.4: Every switch statement shall have a default label. The
default clause must contain either a statement or a comment prior to its
terminating break statement.

This change adds comments in default cases in single-clause switches to
avoid violations of the rule where the `default` clause lacks a suitable
comment or statement.

Signed-off-by: Dmytro Prokopchuk 
---
 xen/arch/arm/cpuerrata.c | 5 +++++
 xen/arch/arm/gic.c       | 6 ++++++
 xen/arch/arm/mmu/p2m.c   | 6 ++++++
 xen/arch/arm/time.c      | 6 ++++++
 xen/common/kexec.c       | 6 ++++++
 5 files changed, 29 insertions(+)

diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index 17cf134f1b..e31c72694b 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -735,6 +735,11 @@ static int cpu_errata_callback(struct notifier_block *=
nfb,
         rc =3D enable_nonboot_cpu_caps(arm_errata);
         break;
     default:
+        /*
+         * Default case left empty as other notifier actions do not requir=
e handling here.
+         * The single CPU_STARTING action in the switch is sufficient beca=
use this function
+         * specifically handles enabling errata workarounds during CPU sta=
rtup.
+         */
         break;
     }
=20
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index e80fe0ca24..dfbb0dfe08 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -436,6 +436,12 @@ static int cpu_gic_callback(struct notifier_block *nfb=
,
         release_irq(gic_hw_ops->info->maintenance_irq, NULL);
         break;
     default:
+        /*
+         * Default case left empty as other notifier actions do not requir=
e handling here.
+         * The CPU_DYING action specifically handles releasing resources a=
cquired by
+         * init_maintenance_interrupt(), when the CPU is being taken offli=
ne. Other CPU
+         * actions do not require GIC-specific handling.
+         */
         break;
     }
=20
diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c
index 51abf3504f..d1f0ae0226 100644
--- a/xen/arch/arm/mmu/p2m.c
+++ b/xen/arch/arm/mmu/p2m.c
@@ -1828,6 +1828,12 @@ static int cpu_virt_paging_callback(struct notifier_=
block *nfb,
         setup_virt_paging_one(NULL);
         break;
     default:
+        /*
+         * Default case left empty as other notifier actions do not requir=
e handling here.
+         * The CPU_STARTING action is specifically handled because this fu=
nction sets up
+         * virtual paging for CPUs, particularly for non-boot CPUs during =
hotplug. Other
+         * actions do not involve virtual paging setup.
+         */
         break;
     }
=20
diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
index e74d30d258..4776110d97 100644
--- a/xen/arch/arm/time.c
+++ b/xen/arch/arm/time.c
@@ -382,6 +382,12 @@ static int cpu_time_callback(struct notifier_block *nf=
b,
         deinit_timer_interrupt();
         break;
     default:
+        /*
+         * Default case left empty as other notifier actions do not requir=
e handling here.
+         * The CPU_DYING action is specifically handled to revert actions =
done in
+         * init_timer_interrupt() and properly disable timer interrupts on=
 the CPU being
+         * taken offline. Other actions do not involve timer deinitializat=
ion.
+         */
         break;
     }
=20
diff --git a/xen/common/kexec.c b/xen/common/kexec.c
index 84fe8c3597..0f78087a4a 100644
--- a/xen/common/kexec.c
+++ b/xen/common/kexec.c
@@ -549,6 +549,12 @@ static int cf_check cpu_callback(
         kexec_init_cpu_notes(cpu);
         break;
     default:
+        /*
+         * Default case left empty as other notifier actions do not requir=
e handling here.
+         * The CPU_UP_PREPARE action is specifically handled to allocate c=
rash note buffers
+         * for a newly onlined CPU. Other actions do not pertain to crash =
note allocation
+         * or memory preservation for kexec.
+         */
         break;
     }
     return NOTIFY_DONE;
--=20
2.43.0


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
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	, Anthony PERARD , Jan
 Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
Thread-Topic: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
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Date: Mon, 11 Aug 2025 20:30:37 +0000
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MISRA Rule 16.4: Every switch statement shall have a default label.
The default clause must contain either a statement or a comment
prior to its terminating break statement.

However, there is a documented rule that apply to the Xen in
'docs/misra/rules.rst':
Switch statements with integer types as controlling expression
should have a default label:
 - if the switch is expected to handle all possible cases
  explicitly, then a default label shall be added to handle
  unexpected error conditions, using BUG(), ASSERT(), WARN(),
  domain_crash(), or other appropriate methods;

These changes add `ASSERT_UNREACHABLE()` macro to the default clause of
switch statements that already explicitly handle all possible cases. This
ensures compliance with MISRA, avoids undefined behavior in unreachable
paths, and helps detect errors during development.

Signed-off-by: Dmytro Prokopchuk 
---
 xen/arch/arm/decode.c      |  3 +++
 xen/arch/arm/guest_walk.c  |  4 ++++
 xen/common/grant_table.c   | 10 ++++++++--
 xen/drivers/char/console.c |  3 +++
 4 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c
index 2537dbebc1..cb64137b3b 100644
--- a/xen/arch/arm/decode.c
+++ b/xen/arch/arm/decode.c
@@ -178,6 +178,9 @@ static int decode_thumb(register_t pc, struct hsr_dabt =
*dabt)
         case 3: /* Signed byte */
             update_dabt(dabt, reg, 0, true);
             break;
+        default:
+            ASSERT_UNREACHABLE();
+            break;
         }
=20
         break;
diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c
index 09fe486598..9199a29602 100644
--- a/xen/arch/arm/guest_walk.c
+++ b/xen/arch/arm/guest_walk.c
@@ -167,6 +167,10 @@ static bool guest_walk_sd(const struct vcpu *v,
             *perms |=3D GV2M_EXEC;
=20
         break;
+
+        default:
+            ASSERT_UNREACHABLE();
+            break;
     }
=20
     return true;
diff --git a/xen/common/grant_table.c b/xen/common/grant_table.c
index cf131c43a1..60fc47f0c8 100644
--- a/xen/common/grant_table.c
+++ b/xen/common/grant_table.c
@@ -330,9 +330,12 @@ shared_entry_header(struct grant_table *t, grant_ref_t=
 ref)
         /* Returned values should be independent of speculative execution =
*/
         block_speculation();
         return &shared_entry_v2(t, ref).hdr;
+
+    default:
+        ASSERT_UNREACHABLE();
+        break;
     }
=20
-    ASSERT_UNREACHABLE();
     block_speculation();
=20
     return NULL;
@@ -727,10 +730,13 @@ static unsigned int nr_grant_entries(struct grant_tab=
le *gt)
         /* Make sure we return a value independently of speculative execut=
ion */
         block_speculation();
         return f2e(nr_grant_frames(gt), 2);
+
+    default:
+        ASSERT_UNREACHABLE();
+        break;
 #undef f2e
     }
=20
-    ASSERT_UNREACHABLE();
     block_speculation();
=20
     return 0;
diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c
index 9bd5b4825d..608616f2af 100644
--- a/xen/drivers/char/console.c
+++ b/xen/drivers/char/console.c
@@ -889,6 +889,9 @@ static int cf_check parse_console_timestamps(const char=
 *s)
         opt_con_timestamp_mode =3D TSM_DATE;
         con_timestamp_mode_upd(param_2_parfs(parse_console_timestamps));
         return 0;
+    default:
+        ASSERT_UNREACHABLE();
+        break;
     }
     if ( *s =3D=3D '\0' || /* Compat for old booleanparam() */
          !strcmp(s, "date") )
--=20
2.43.0


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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mirela Simonovic ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Saeed Nowshadi ,
	Mykyta Poturai ,
	Mykola Kvach 
Subject: [PATCH v5 02/12] xen/arm: gic-v2: Implement GIC suspend/resume functions
Date: Mon, 11 Aug 2025 23:47:58 +0300
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From: Mirela Simonovic 

System suspend may lead to a state where GIC would be powered down.
Therefore, Xen should save/restore the context of GIC on suspend/resume.

Note that the context consists of states of registers which are
controlled by the hypervisor. Other GIC registers which are accessible
by guests are saved/restored on context switch.

Tested on Xilinx Ultrascale+ MPSoC with (and without) powering down
the GIC.

Signed-off-by: Mirela Simonovic 
Signed-off-by: Saeed Nowshadi 
Signed-off-by: Mykyta Poturai 
Signed-off-by: Mykola Kvach 
---
Changes in v4:
  - Add error logging for allocation failures

Changes in v3:
  - Drop asserts and return error codes instead.
  - Wrap code with CONFIG_SYSTEM_SUSPEND.

Changes in v2:
  - Minor fixes after review.
---
 xen/arch/arm/gic-v2.c          | 154 +++++++++++++++++++++++++++++++++
 xen/arch/arm/gic.c             |  29 +++++++
 xen/arch/arm/include/asm/gic.h |  12 +++
 3 files changed, 195 insertions(+)

diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index b23e72a3d0..dce8f5e924 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -1098,6 +1098,151 @@ static int gicv2_iomem_deny_access(struct domain *d)
     return iomem_deny_access(d, mfn, mfn + nr);
 }
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+
+/* GICv2 registers to be saved/restored on system suspend/resume */
+struct gicv2_context {
+    /* GICC context */
+    uint32_t gicc_ctlr;
+    uint32_t gicc_pmr;
+    uint32_t gicc_bpr;
+    /* GICD context */
+    uint32_t gicd_ctlr;
+    uint32_t *gicd_isenabler;
+    uint32_t *gicd_isactiver;
+    uint32_t *gicd_ipriorityr;
+    uint32_t *gicd_itargetsr;
+    uint32_t *gicd_icfgr;
+};
+
+static struct gicv2_context gicv2_context;
+
+static int gicv2_suspend(void)
+{
+    unsigned int i;
+
+    if ( !gicv2_context.gicd_isenabler )
+    {
+        dprintk(XENLOG_WARNING, "%s:%d: GICv2 suspend context not allocated!\n",
+            __func__, __LINE__);
+        return -ENOMEM;
+    }
+
+    /* Save GICC configuration */
+    gicv2_context.gicc_ctlr = readl_gicc(GICC_CTLR);
+    gicv2_context.gicc_pmr = readl_gicc(GICC_PMR);
+    gicv2_context.gicc_bpr = readl_gicc(GICC_BPR);
+
+    /* Save GICD configuration */
+    gicv2_context.gicd_ctlr = readl_gicd(GICD_CTLR);
+
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ )
+        gicv2_context.gicd_isenabler[i] = readl_gicd(GICD_ISENABLER + i * 4);
+
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ )
+        gicv2_context.gicd_isactiver[i] = readl_gicd(GICD_ISACTIVER + i * 4);
+
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
+        gicv2_context.gicd_ipriorityr[i] = readl_gicd(GICD_IPRIORITYR + i * 4);
+
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
+        gicv2_context.gicd_itargetsr[i] = readl_gicd(GICD_ITARGETSR + i * 4);
+
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 16); i++ )
+        gicv2_context.gicd_icfgr[i] = readl_gicd(GICD_ICFGR + i * 4);
+
+    return 0;
+}
+
+static void gicv2_resume(void)
+{
+    unsigned int i;
+
+    if ( !gicv2_context.gicd_isenabler )
+    {
+        dprintk(XENLOG_WARNING, "%s:%d: GICv2 suspend context not allocated!\n",
+            __func__, __LINE__);
+        return;
+    }
+
+    gicv2_cpu_disable();
+    /* Disable distributor */
+    writel_gicd(0, GICD_CTLR);
+
+    /* Restore GICD configuration */
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ ) {
+        writel_gicd(0xffffffff, GICD_ICENABLER + i * 4);
+        writel_gicd(gicv2_context.gicd_isenabler[i], GICD_ISENABLER + i * 4);
+    }
+
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ ) {
+        writel_gicd(0xffffffff, GICD_ICACTIVER + i * 4);
+        writel_gicd(gicv2_context.gicd_isactiver[i], GICD_ISACTIVER + i * 4);
+    }
+
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
+        writel_gicd(gicv2_context.gicd_ipriorityr[i], GICD_IPRIORITYR + i * 4);
+
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
+        writel_gicd(gicv2_context.gicd_itargetsr[i], GICD_ITARGETSR + i * 4);
+
+    for ( i = 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 16); i++ )
+        writel_gicd(gicv2_context.gicd_icfgr[i], GICD_ICFGR + i * 4);
+
+    /* Make sure all registers are restored and enable distributor */
+    writel_gicd(gicv2_context.gicd_ctlr | GICD_CTL_ENABLE, GICD_CTLR);
+
+    /* Restore GIC CPU interface configuration */
+    writel_gicc(gicv2_context.gicc_pmr, GICC_PMR);
+    writel_gicc(gicv2_context.gicc_bpr, GICC_BPR);
+
+    /* Enable GIC CPU interface */
+    writel_gicc(gicv2_context.gicc_ctlr | GICC_CTL_ENABLE | GICC_CTL_EOI,
+                GICC_CTLR);
+}
+
+static void gicv2_alloc_context(struct gicv2_context *gc)
+{
+    uint32_t n = gicv2_info.nr_lines;
+
+    gc->gicd_isenabler = xzalloc_array(uint32_t, DIV_ROUND_UP(n, 32));
+    if ( !gc->gicd_isenabler )
+        goto err_free;
+
+    gc->gicd_isactiver = xzalloc_array(uint32_t, DIV_ROUND_UP(n, 32));
+    if ( !gc->gicd_isactiver )
+        goto err_free;
+
+    gc->gicd_itargetsr = xzalloc_array(uint32_t, DIV_ROUND_UP(n, 4));
+    if ( !gc->gicd_itargetsr )
+        goto err_free;
+
+    gc->gicd_ipriorityr = xzalloc_array(uint32_t, DIV_ROUND_UP(n, 4));
+    if ( !gc->gicd_ipriorityr )
+        goto err_free;
+
+    gc->gicd_icfgr = xzalloc_array(uint32_t, DIV_ROUND_UP(n, 16));
+    if ( !gc->gicd_icfgr )
+        goto err_free;
+
+    return;
+
+ err_free:
+    dprintk(XENLOG_ERR,
+            "%s:%d: failed to allocate memory for GICv2 suspend context\n",
+            __func__, __LINE__);
+
+    xfree(gc->gicd_icfgr);
+    xfree(gc->gicd_ipriorityr);
+    xfree(gc->gicd_itargetsr);
+    xfree(gc->gicd_isactiver);
+    xfree(gc->gicd_isenabler);
+
+    memset(gc, 0, sizeof(*gc));
+}
+
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
 #ifdef CONFIG_ACPI
 static unsigned long gicv2_get_hwdom_extra_madt_size(const struct domain *d)
 {
@@ -1302,6 +1447,11 @@ static int __init gicv2_init(void)
 
     spin_unlock(&gicv2.lock);
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+    /* Allocate memory to be used for saving GIC context during the suspend */
+    gicv2_alloc_context(&gicv2_context);
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
     return 0;
 }
 
@@ -1345,6 +1495,10 @@ static const struct gic_hw_operations gicv2_ops = {
     .map_hwdom_extra_mappings = gicv2_map_hwdom_extra_mappings,
     .iomem_deny_access   = gicv2_iomem_deny_access,
     .do_LPI              = gicv2_do_LPI,
+#ifdef CONFIG_SYSTEM_SUSPEND
+    .suspend             = gicv2_suspend,
+    .resume              = gicv2_resume,
+#endif /* CONFIG_SYSTEM_SUSPEND */
 };
 
 /* Set up the GIC */
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index e80fe0ca24..a018bd7715 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -425,6 +425,35 @@ int gic_iomem_deny_access(struct domain *d)
     return gic_hw_ops->iomem_deny_access(d);
 }
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+
+int gic_suspend(void)
+{
+    /* Must be called by boot CPU#0 with interrupts disabled */
+    ASSERT(!local_irq_is_enabled());
+    ASSERT(!smp_processor_id());
+
+    if ( !gic_hw_ops->suspend || !gic_hw_ops->resume )
+        return -ENOSYS;
+
+    return gic_hw_ops->suspend();
+}
+
+void gic_resume(void)
+{
+    /*
+     * Must be called by boot CPU#0 with interrupts disabled after gic_suspend
+     * has returned successfully.
+     */
+    ASSERT(!local_irq_is_enabled());
+    ASSERT(!smp_processor_id());
+    ASSERT(gic_hw_ops->resume);
+
+    gic_hw_ops->resume();
+}
+
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
 static int cpu_gic_callback(struct notifier_block *nfb,
                             unsigned long action,
                             void *hcpu)
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h
index 541f0eeb80..a706303008 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -280,6 +280,12 @@ extern int gicv_setup(struct domain *d);
 extern void gic_save_state(struct vcpu *v);
 extern void gic_restore_state(struct vcpu *v);
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+/* Suspend/resume */
+extern int gic_suspend(void);
+extern void gic_resume(void);
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
 /* SGI (AKA IPIs) */
 enum gic_sgi {
     GIC_SGI_EVENT_CHECK,
@@ -395,6 +401,12 @@ struct gic_hw_operations {
     int (*iomem_deny_access)(struct domain *d);
     /* Handle LPIs, which require special handling */
     void (*do_LPI)(unsigned int lpi);
+#ifdef CONFIG_SYSTEM_SUSPEND
+    /* Save GIC configuration due to the system suspend */
+    int (*suspend)(void);
+    /* Restore GIC configuration due to the system resume */
+    void (*resume)(void);
+#endif /* CONFIG_SYSTEM_SUSPEND */
 };
 
 extern const struct gic_hw_operations *gic_hw_ops;
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mirela Simonovic ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Saeed Nowshadi ,
	Mykola Kvach 
Subject: [PATCH v5 01/12] xen/arm: Add suspend and resume timer helpers
Date: Mon, 11 Aug 2025 23:47:57 +0300
Message-ID: <412e0f48636feda1825885a8aed92386f694c8ca.1754943874.git.mykola_kvach@epam.com>
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From: Mirela Simonovic 

Timer interrupts must be disabled while the system is suspended to prevent
spurious wake-ups. Suspending the timers involves disabling both the EL1
physical timer and the EL2 hypervisor timer. Resuming consists of raising
the TIMER_SOFTIRQ, which prompts the generic timer code to reprogram the
EL2 timer as needed. Re-enabling of the EL1 timer is left to the entity
that uses it.

Introduce a new helper, disable_physical_timers, to encapsulate disabling
of the physical timers.

Signed-off-by: Mirela Simonovic 
Signed-off-by: Saeed Nowshadi 
Signed-off-by: Mykola Kvach 
---
Changes in V4:
  - Rephrased comment and commit message for better clarity
  - Created separate function for disabling physical timers

Changes in V3:
  - time_suspend and time_resume are now conditionally compiled
    under CONFIG_SYSTEM_SUSPEND
---
 xen/arch/arm/include/asm/time.h |  5 +++++
 xen/arch/arm/time.c             | 38 +++++++++++++++++++++++++++------
 2 files changed, 37 insertions(+), 6 deletions(-)

diff --git a/xen/arch/arm/include/asm/time.h b/xen/arch/arm/include/asm/time.h
index 49ad8c1a6d..f4fd0c6af5 100644
--- a/xen/arch/arm/include/asm/time.h
+++ b/xen/arch/arm/include/asm/time.h
@@ -108,6 +108,11 @@ void preinit_xen_time(void);
 
 void force_update_vcpu_system_time(struct vcpu *v);
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+void time_suspend(void);
+void time_resume(void);
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
 #endif /* __ARM_TIME_H__ */
 /*
  * Local variables:
diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
index e74d30d258..ad984fdfdd 100644
--- a/xen/arch/arm/time.c
+++ b/xen/arch/arm/time.c
@@ -303,6 +303,14 @@ static void check_timer_irq_cfg(unsigned int irq, const char *which)
            "WARNING: %s-timer IRQ%u is not level triggered.\n", which, irq);
 }
 
+/* Disable physical timers for EL1 and EL2 on the current CPU */
+static inline void disable_physical_timers(void)
+{
+    WRITE_SYSREG(0, CNTP_CTL_EL0);    /* Physical timer disabled */
+    WRITE_SYSREG(0, CNTHP_CTL_EL2);   /* Hypervisor's timer disabled */
+    isb();
+}
+
 /* Set up the timer interrupt on this CPU */
 void init_timer_interrupt(void)
 {
@@ -310,9 +318,7 @@ void init_timer_interrupt(void)
     WRITE_SYSREG64(0, CNTVOFF_EL2);     /* No VM-specific offset */
     /* Do not let the VMs program the physical timer, only read the physical counter */
     WRITE_SYSREG(CNTHCTL_EL2_EL1PCTEN, CNTHCTL_EL2);
-    WRITE_SYSREG(0, CNTP_CTL_EL0);    /* Physical timer disabled */
-    WRITE_SYSREG(0, CNTHP_CTL_EL2);   /* Hypervisor's timer disabled */
-    isb();
+    disable_physical_timers();
 
     request_irq(timer_irq[TIMER_HYP_PPI], 0, htimer_interrupt,
                 "hyptimer", NULL);
@@ -330,9 +336,7 @@ void init_timer_interrupt(void)
  */
 static void deinit_timer_interrupt(void)
 {
-    WRITE_SYSREG(0, CNTP_CTL_EL0);    /* Disable physical timer */
-    WRITE_SYSREG(0, CNTHP_CTL_EL2);   /* Disable hypervisor's timer */
-    isb();
+    disable_physical_timers();
 
     release_irq(timer_irq[TIMER_HYP_PPI], NULL);
     release_irq(timer_irq[TIMER_VIRT_PPI], NULL);
@@ -372,6 +376,28 @@ void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds)
     /* XXX update guest visible wallclock time */
 }
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+
+void time_suspend(void)
+{
+    disable_physical_timers();
+}
+
+void time_resume(void)
+{
+    /*
+     * Raising the timer softirq triggers generic code to call reprogram_timer
+     * with the correct timeout (not known here).
+     *
+     * No further action is needed to restore timekeeping after power down,
+     * since the system counter is unaffected. See ARM DDI 0487 L.a, D12.1.2
+     * "The system counter must be implemented in an always-on power domain."
+     */
+    raise_softirq(TIMER_SOFTIRQ);
+}
+
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
 static int cpu_time_callback(struct notifier_block *nfb,
                              unsigned long action,
                              void *hcpu)
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v5 03/12] xen/arm: gic-v3: Implement GICv3 suspend/resume functions
Date: Mon, 11 Aug 2025 23:47:59 +0300
Message-ID: <451b8a0527a6193b6687e1c85bd254b4dfda142d.1754943874.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

System suspend may lead to a state where GIC would be powered down.
Therefore, Xen should save/restore the context of GIC on suspend/resume.

Note that the context consists of states of registers which are
controlled by the hypervisor. Other GIC registers which are accessible
by guests are saved/restored on context switch.

Signed-off-by: Mykola Kvach 
---
 xen/arch/arm/gic-v3.c | 233 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 233 insertions(+)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index cd3e1acf79..a9b65ff5d4 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -1776,6 +1776,231 @@ static bool gic_dist_supports_lpis(void)
     return (readl_relaxed(GICD + GICD_TYPER) & GICD_TYPE_LPIS);
 }
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+
+/* GICv3 registers to be saved/restored on system suspend/resume */
+struct gicv3_ctx {
+    struct dist_ctx {
+        uint32_t ctlr;
+        /*
+         * This struct represent block of 32 IRQs
+         * TODO: store extended SPI configuration (GICv3.1+)
+         */
+        struct irq_regs {
+            uint32_t icfgr[2];
+            uint32_t ipriorityr[8];
+            uint64_t irouter[32];
+            uint32_t isactiver;
+            uint32_t isenabler;
+        } *irqs;
+    } dist;
+
+    /* have only one rdist structure for last running CPU during suspend */
+    struct redist_ctx {
+        uint32_t ctlr;
+        /* TODO: handle case when we have more than 16 PPIs (GICv3.1+) */
+        uint32_t icfgr[2];
+        uint32_t igroupr;
+        uint32_t ipriorityr[8];
+        uint32_t isactiver;
+        uint32_t isenabler;
+    } rdist;
+
+    struct cpu_ctx {
+        uint32_t ctlr;
+        uint32_t pmr;
+        uint32_t bpr;
+        uint32_t sre_el2;
+        uint32_t grpen;
+    } cpu;
+};
+
+static struct gicv3_ctx gicv3_ctx;
+
+static void __init gicv3_alloc_context(void)
+{
+    uint32_t blocks = DIV_ROUND_UP(gicv3_info.nr_lines, 32);
+
+    if ( gicv3_its_host_has_its() )
+        return;
+
+    /* according to spec it is possible don't have SPIs */
+    if ( blocks == 1 )
+        return;
+
+    gicv3_ctx.dist.irqs = xzalloc_array(typeof(*gicv3_ctx.dist.irqs), blocks - 1);
+    if ( !gicv3_ctx.dist.irqs )
+        dprintk(XENLOG_ERR,
+                "%s:%d: failed to allocate memory for GICv3 suspend context\n",
+                __func__, __LINE__);
+}
+
+static void gicv3_disable_redist(void)
+{
+    void __iomem* waker = GICD_RDIST_BASE + GICR_WAKER;
+
+    writel_relaxed(readl_relaxed(waker) | GICR_WAKER_ProcessorSleep, waker);
+    while ( (readl_relaxed(waker) & GICR_WAKER_ChildrenAsleep) == 0 );
+}
+
+static int gicv3_suspend(void)
+{
+    unsigned int i;
+    void __iomem *base;
+    typeof(gicv3_ctx.rdist)* rdist = &gicv3_ctx.rdist;
+
+    /* TODO: implement support for ITS */
+    if ( gicv3_its_host_has_its() )
+        return -EOPNOTSUPP;
+
+    if ( !gicv3_ctx.dist.irqs && gicv3_info.nr_lines > NR_GIC_LOCAL_IRQS )
+    {
+        dprintk(XENLOG_WARNING,
+                "%s:%d: GICv3 suspend context is not allocated!\n",
+                __func__, __LINE__);
+        return -ENOMEM;
+    }
+
+    gicv3_save_state(current);
+
+    /* Save GICC configuration */
+    gicv3_ctx.cpu.ctlr     = READ_SYSREG(ICC_CTLR_EL1);
+    gicv3_ctx.cpu.pmr      = READ_SYSREG(ICC_PMR_EL1);
+    gicv3_ctx.cpu.bpr      = READ_SYSREG(ICC_BPR1_EL1);
+    gicv3_ctx.cpu.sre_el2  = READ_SYSREG(ICC_SRE_EL2);
+    gicv3_ctx.cpu.grpen    = READ_SYSREG(ICC_IGRPEN1_EL1);
+
+    gicv3_disable_interface();
+    gicv3_disable_redist();
+
+    /* Save GICR configuration */
+    gicv3_redist_wait_for_rwp();
+
+    base = GICD_RDIST_SGI_BASE;
+
+    rdist->ctlr = readl_relaxed(base + GICR_CTLR);
+
+    /* Set priority on PPI and SGI interrupts */
+    for (i = 0; i < NR_GIC_LOCAL_IRQS / 4; i += 4)
+        rdist->ipriorityr[i] = readl_relaxed(base + GICR_IPRIORITYR0 + 4 * i);
+
+    rdist->isactiver = readl_relaxed(base + GICR_ISACTIVER0);
+    rdist->isenabler = readl_relaxed(base + GICR_ISENABLER0);
+    rdist->igroupr   = readl_relaxed(base + GICR_IGROUPR0);
+    rdist->icfgr[0]  = readl_relaxed(base + GICR_ICFGR0);
+    rdist->icfgr[1]  = readl_relaxed(base + GICR_ICFGR1);
+
+    /* Save GICD configuration */
+    gicv3_dist_wait_for_rwp();
+    gicv3_ctx.dist.ctlr = readl_relaxed(GICD + GICD_CTLR);
+
+    for ( i = 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ )
+    {
+        typeof(gicv3_ctx.dist.irqs) irqs = gicv3_ctx.dist.irqs + i - 1;
+        unsigned int irq;
+
+        base = GICD + GICD_ICFGR + 8 * i;
+        irqs->icfgr[0] = readl_relaxed(base);
+        irqs->icfgr[1] = readl_relaxed(base + 4);
+
+        base = GICD + GICD_IPRIORITYR + 32 * i;
+        for ( irq = 0; irq < 8; irq++ )
+            irqs->ipriorityr[irq] = readl_relaxed(base + 4 * irq);
+
+        base = GICD + GICD_IROUTER + 32 * i;
+        for ( irq = 0; irq < 32; irq++ )
+            irqs->irouter[irq] = readq_relaxed_non_atomic(base + 8 * irq);
+
+        irqs->isactiver = readl_relaxed(GICD + GICD_ISACTIVER + 4 * i);
+        irqs->isenabler = readl_relaxed(GICD + GICD_ISENABLER + 4 * i);
+    }
+
+    return 0;
+}
+
+static void gicv3_resume(void)
+{
+    unsigned int i;
+    void __iomem *base;
+    typeof(gicv3_ctx.rdist)* rdist = &gicv3_ctx.rdist;
+
+    if ( !gicv3_ctx.dist.irqs && gicv3_info.nr_lines > NR_GIC_LOCAL_IRQS )
+    {
+        dprintk(XENLOG_WARNING, "%s:%d: GICv3 suspend context not allocated!\n",
+            __func__, __LINE__);
+        return;
+    }
+
+    writel_relaxed(0, GICD + GICD_CTLR);
+
+    for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 32 )
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4);
+
+    for ( i = 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ )
+    {
+        typeof(gicv3_ctx.dist.irqs) irqs = gicv3_ctx.dist.irqs + i - 1;
+        unsigned int irq;
+
+        base = GICD + GICD_ICFGR + 8 * i;
+        writel_relaxed(irqs->icfgr[0], base);
+        writel_relaxed(irqs->icfgr[1], base + 4);
+
+        base = GICD + GICD_IPRIORITYR + 32 * i;
+        for ( irq = 0; irq < 8; irq++ )
+            writel_relaxed(irqs->ipriorityr[irq], base + 4 * irq );
+
+        base = GICD + GICD_IROUTER + 32 * i;
+        for ( irq = 0; irq < 32; irq++ )
+            writeq_relaxed_non_atomic(irqs->irouter[irq], base + 8 * irq);
+
+        writel_relaxed(irqs->isenabler, GICD + GICD_ISENABLER + i * 4);
+        writel_relaxed(irqs->isactiver, GICD + GICD_ISACTIVER + i * 4);
+    }
+
+    writel_relaxed(gicv3_ctx.dist.ctlr, GICD + GICD_CTLR);
+    gicv3_dist_wait_for_rwp();
+
+    /* Restore GICR (Redistributor) configuration */
+    gicv3_enable_redist();
+
+    base = GICD_RDIST_SGI_BASE;
+
+    writel_relaxed(0xffffffff, base + GICR_ICENABLER0);
+    gicv3_redist_wait_for_rwp();
+
+    for (i = 0; i < NR_GIC_LOCAL_IRQS / 4; i += 4)
+        writel_relaxed(rdist->ipriorityr[i], base + GICR_IPRIORITYR0 + i * 4);
+
+    writel_relaxed(rdist->isactiver, base + GICR_ISACTIVER0);
+
+    writel_relaxed(rdist->igroupr,  base + GICR_IGROUPR0);
+    writel_relaxed(rdist->icfgr[0], base + GICR_ICFGR0);
+    writel_relaxed(rdist->icfgr[1], base + GICR_ICFGR1);
+
+    gicv3_redist_wait_for_rwp();
+
+    writel_relaxed(rdist->isenabler, base + GICR_ISENABLER0);
+    writel_relaxed(rdist->ctlr, GICD_RDIST_BASE + GICR_CTLR);
+
+    gicv3_redist_wait_for_rwp();
+
+    WRITE_SYSREG(gicv3_ctx.cpu.sre_el2, ICC_SRE_EL2);
+    isb();
+
+    /* Restore CPU interface (System registers) */
+    WRITE_SYSREG(gicv3_ctx.cpu.pmr,   ICC_PMR_EL1);
+    WRITE_SYSREG(gicv3_ctx.cpu.bpr,   ICC_BPR1_EL1);
+    WRITE_SYSREG(gicv3_ctx.cpu.ctlr,  ICC_CTLR_EL1);
+    WRITE_SYSREG(gicv3_ctx.cpu.grpen, ICC_IGRPEN1_EL1);
+    isb();
+
+    gicv3_hyp_init();
+
+    gicv3_restore_state(current);
+}
+
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
 /* Set up the GIC */
 static int __init gicv3_init(void)
 {
@@ -1850,6 +2075,10 @@ static int __init gicv3_init(void)
 
     gicv3_hyp_init();
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+    gicv3_alloc_context();
+#endif
+
 out:
     spin_unlock(&gicv3.lock);
 
@@ -1889,6 +2118,10 @@ static const struct gic_hw_operations gicv3_ops = {
 #endif
     .iomem_deny_access   = gicv3_iomem_deny_access,
     .do_LPI              = gicv3_do_LPI,
+#ifdef CONFIG_SYSTEM_SUSPEND
+    .suspend             = gicv3_suspend,
+    .resume              = gicv3_resume,
+#endif
 };
 
 static int __init gicv3_dt_preinit(struct dt_device_node *node, const void *data)
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v5 00/12] Add initial Xen Suspend-to-RAM support on ARM64
Date: Mon, 11 Aug 2025 23:47:56 +0300
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From: Mykola Kvach 

This is part 2 of version 5 of the ARM Xen system suspend/resume patch
series, based on earlier work by Mirela Simonovic and Mykyta Poturai.
This version is ported to Xen master (4.21-unstable) and includes
extensive improvements based on reviewer feedback. The patch series
restructures code to improve robustness, maintainability, and implements
system Suspend-to-RAM support on ARM64 hardware domains.

At a high-level, this patch series provides:
 - Support for Host system suspend/resume via PSCI SYSTEM_SUSPEND (ARM64)
 - Suspend/resume infrastructure for CPU context, timers, GICv2/GICv3 and IPMMU-VMSA
 - Proper error propagation and recovery throughout the suspend/resume flow

Key updates in this series:
 - Introduced architecture-specific suspend/resume infrastructure (new `suspend.c`, `suspend.h`, low-level context save/restore in `head.S`)
 - Integrated GICv2/GICv3 suspend and resume, including memory-backed context save/restore with error handling
 - Added time and IRQ suspend/resume hooks, ensuring correct timer/interrupt state across suspend cycles
 - Implemented proper PSCI SYSTEM_SUSPEND invocation and version checks
 - Improved state management and recovery in error cases during suspend/resume
 - Added support for IPMMU-VMSA context save/restore

---
TODOs:
 - Test system suspend with llc_coloring_enabled set and verify functionality
 - Implement SMMUv3 suspend/resume handlers
 - Enable "xl suspend" support on ARM
 - Properly disable Xen timer watchdog from relevant services (only init.d left)
 - Add suspend/resume CI test for ARM (QEMU if feasible)
 - Investigate feasibility and need for implementing system suspend on ARM32
---
Changes introduced in V5:
 - Add support for IPMMU-VMSA context save/restore
 - Add support for GICv3 context save/restore
 - Select HAS_SYSTEM_SUSPEND in ARM_64 instead of ARM
 - Check llc_coloring_enabled instead of LLC_COLORING during the selection
   of HAS_SYSTEM_SUSPEND config
 - Call host_system_suspend from guest PSCI system suspend instead of
   arch_domain_shutdown, reducing the complexity of the new code

Changes introduced in V4:
  - Remove the prior tasklet-based workaround in favor of a more
    straightforward and safer solution.
  - Rework the approach by adding explicit system state checks around
    request_irq and release_irq calls; skip these calls during suspend
    and resume states to avoid unsafe memory operations when IRQs are
    disabled.
  - Prevent reinitialization of local IRQ descriptors on system resume.
  - Restore the state of local IRQs during system resume for secondary CPUs.
  - Drop code for saving and restoring VCPU context (see part 1 of the patch
    series for details).
  - Remove IOMMU suspend and resume calls until these features are implemented.
  - Move system suspend logic to arch_domain_shutdown, invoked from
    domain_shutdown.
  - Add console_end_sync to the resume path after system suspend.
  - Drop unnecessary DAIF masking; interrupts are already masked on resume.
  - Remove leftover TLB flush instructions; flushing is handled in enable_mmu.
  - Avoid setting x19 in hyp_resume as it is not required.
  - Replace prepare_secondary_mm with set_init_ttbr, and call it from system_suspend.
  - Produce a build-time error for ARM32 when CONFIG_SYSTEM_SUSPEND is enabled.
  - Use register_t instead of uint64_t in the cpu_context structure.
  - Apply minor fixes such as renaming functions, updating comments, and
    modifying commit messages to accurately reflect the changes introduced
    by this patch series.

For earlier changelogs, please refer to the previous cover letters.

Previous versions:
  V1: https://marc.info/?l=xen-devel&m=154202231501850&w=2
  V2: https://marc.info/?l=xen-devel&m=166514782207736&w=2
  V3: https://lists.xen.org/archives/html/xen-devel/2025-03/msg00168.html

Mirela Simonovic (6):
  xen/arm: Add suspend and resume timer helpers
  xen/arm: gic-v2: Implement GIC suspend/resume functions
  xen/arm: Add support for system suspend triggered by hardware domain
  xen/arm: Implement PSCI SYSTEM_SUSPEND call (host interface)
  xen/arm: Resume memory management on Xen resume
  xen/arm: Save/restore context on suspend/resume

Mykola Kvach (4):
  xen/arm: gic-v3: Implement GICv3 suspend/resume functions
  xen/arm: Prevent crash during disable_nonboot_cpus on suspend
  xen/arm: irq: avoid local IRQ descriptors reinit on system resume
  xen/arm: irq: Restore state of local IRQs during system resume

Oleksandr Tyshchenko (2):
  iommu/ipmmu-vmsa: Implement suspend/resume callbacks
  xen/arm: Suspend/resume IOMMU on Xen suspend/resume

 xen/arch/arm/Kconfig                     |   1 +
 xen/arch/arm/Makefile                    |   1 +
 xen/arch/arm/arm64/head.S                | 113 ++++++++++
 xen/arch/arm/gic-v2.c                    | 154 +++++++++++++
 xen/arch/arm/gic-v3.c                    | 233 ++++++++++++++++++++
 xen/arch/arm/gic.c                       |  35 +++
 xen/arch/arm/include/asm/gic.h           |  12 +
 xen/arch/arm/include/asm/mm.h            |   2 +
 xen/arch/arm/include/asm/psci.h          |   1 +
 xen/arch/arm/include/asm/suspend.h       |  44 ++++
 xen/arch/arm/include/asm/time.h          |   5 +
 xen/arch/arm/irq.c                       |  48 ++++
 xen/arch/arm/mmu/smpboot.c               |   2 +-
 xen/arch/arm/psci.c                      |  23 +-
 xen/arch/arm/suspend.c                   | 196 +++++++++++++++++
 xen/arch/arm/tee/ffa_notif.c             |   2 +-
 xen/arch/arm/time.c                      |  56 ++++-
 xen/arch/arm/vpsci.c                     |  12 +-
 xen/common/domain.c                      |   4 +
 xen/drivers/passthrough/arm/ipmmu-vmsa.c | 269 +++++++++++++++++++++++
 20 files changed, 1197 insertions(+), 16 deletions(-)
 create mode 100644 xen/arch/arm/include/asm/suspend.h
 create mode 100644 xen/arch/arm/suspend.c

-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v5 04/12] xen/arm: Prevent crash during disable_nonboot_cpus on suspend
Date: Mon, 11 Aug 2025 23:48:00 +0300
Message-ID: <98957da5c5068ae8340a21a9aa15a962905a8a22.1754943874.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

If we call disable_nonboot_cpus on ARM64 with system_state set
to SYS_STATE_suspend, the following assertion will be triggered:

```
(XEN) [   25.582712] Disabling non-boot CPUs ...
(XEN) [   25.587032] Assertion '!in_irq() && (local_irq_is_enabled() || num_online_cpus() <= 1)' failed at common/xmalloc_tlsf.c:714
[...]
(XEN) [   25.975069] Xen call trace:
(XEN) [   25.978353]    [<00000a000022e098>] xfree+0x130/0x1a4 (PC)
(XEN) [   25.984314]    [<00000a000022e08c>] xfree+0x124/0x1a4 (LR)
(XEN) [   25.990276]    [<00000a00002747d4>] release_irq+0xe4/0xe8
(XEN) [   25.996152]    [<00000a0000278588>] time.c#cpu_time_callback+0x44/0x60
(XEN) [   26.003150]    [<00000a000021d678>] notifier_call_chain+0x7c/0xa0
(XEN) [   26.009717]    [<00000a00002018e0>] cpu.c#cpu_notifier_call_chain+0x24/0x48
(XEN) [   26.017148]    [<00000a000020192c>] cpu.c#_take_cpu_down+0x28/0x34
(XEN) [   26.023801]    [<00000a0000201944>] cpu.c#take_cpu_down+0xc/0x18
(XEN) [   26.030281]    [<00000a0000225c5c>] stop_machine.c#stopmachine_action+0xbc/0xe4
(XEN) [   26.038057]    [<00000a00002264bc>] tasklet.c#do_tasklet_work+0xb8/0x100
(XEN) [   26.045229]    [<00000a00002268a4>] do_tasklet+0x68/0xb0
(XEN) [   26.051018]    [<00000a000026e120>] domain.c#idle_loop+0x7c/0x194
(XEN) [   26.057585]    [<00000a0000277e30>] start_secondary+0x21c/0x220
(XEN) [   26.063978]    [<00000a0000361258>] 00000a0000361258
```

This happens because before invoking take_cpu_down via the stop_machine_run
function on the target CPU, stop_machine_run requests
the STOPMACHINE_DISABLE_IRQ state on that CPU. Releasing memory in
the release_irq function then triggers the assertion:

/*
 * Heap allocations may need TLB flushes which may require IRQs to be
 * enabled (except when only 1 PCPU is online).
 */

This patch adds system state checks to guard calls to request_irq
and release_irq. These calls are now skipped when system_state is
SYS_STATE_{resume,suspend}, preventing unsafe operations during
suspend/resume handling.

Signed-off-by: Mykola Kvach 
---
Changes in V4:
  - removed the prior tasklet-based workaround in favor of a more
    straightforward and safer solution
  - reworked the approach by adding explicit system state checks around
    request_irq and release_irq calls, skips these calls during suspend
    and resume states to avoid unsafe memory operations when IRQs are
    disabled
---
 xen/arch/arm/gic.c           |  6 ++++++
 xen/arch/arm/tee/ffa_notif.c |  2 +-
 xen/arch/arm/time.c          | 18 ++++++++++++------
 3 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index a018bd7715..9856cb1592 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -388,6 +388,9 @@ void gic_dump_info(struct vcpu *v)
 
 void init_maintenance_interrupt(void)
 {
+    if ( system_state == SYS_STATE_resume )
+        return;
+
     request_irq(gic_hw_ops->info->maintenance_irq, 0, maintenance_interrupt,
                 "irq-maintenance", NULL);
 }
@@ -461,6 +464,9 @@ static int cpu_gic_callback(struct notifier_block *nfb,
     switch ( action )
     {
     case CPU_DYING:
+        if ( system_state == SYS_STATE_suspend )
+            break;
+
         /* This is reverting the work done in init_maintenance_interrupt */
         release_irq(gic_hw_ops->info->maintenance_irq, NULL);
         break;
diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c
index 00efaf8f73..06f715a82b 100644
--- a/xen/arch/arm/tee/ffa_notif.c
+++ b/xen/arch/arm/tee/ffa_notif.c
@@ -347,7 +347,7 @@ void ffa_notif_init_interrupt(void)
 {
     int ret;
 
-    if ( notif_enabled && notif_sri_irq < NR_GIC_SGI )
+    if ( notif_enabled && notif_sri_irq < NR_GIC_SGI && system_state != SYS_STATE_resume )
     {
         /*
          * An error here is unlikely since the primary CPU has already
diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
index ad984fdfdd..b2e07ade43 100644
--- a/xen/arch/arm/time.c
+++ b/xen/arch/arm/time.c
@@ -320,10 +320,13 @@ void init_timer_interrupt(void)
     WRITE_SYSREG(CNTHCTL_EL2_EL1PCTEN, CNTHCTL_EL2);
     disable_physical_timers();
 
-    request_irq(timer_irq[TIMER_HYP_PPI], 0, htimer_interrupt,
-                "hyptimer", NULL);
-    request_irq(timer_irq[TIMER_VIRT_PPI], 0, vtimer_interrupt,
-                   "virtimer", NULL);
+    if ( system_state != SYS_STATE_resume )
+    {
+        request_irq(timer_irq[TIMER_HYP_PPI], 0, htimer_interrupt,
+                    "hyptimer", NULL);
+        request_irq(timer_irq[TIMER_VIRT_PPI], 0, vtimer_interrupt,
+                    "virtimer", NULL);
+    }
 
     check_timer_irq_cfg(timer_irq[TIMER_HYP_PPI], "hypervisor");
     check_timer_irq_cfg(timer_irq[TIMER_VIRT_PPI], "virtual");
@@ -338,8 +341,11 @@ static void deinit_timer_interrupt(void)
 {
     disable_physical_timers();
 
-    release_irq(timer_irq[TIMER_HYP_PPI], NULL);
-    release_irq(timer_irq[TIMER_VIRT_PPI], NULL);
+    if ( system_state != SYS_STATE_suspend )
+    {
+        release_irq(timer_irq[TIMER_HYP_PPI], NULL);
+        release_irq(timer_irq[TIMER_VIRT_PPI], NULL);
+    }
 }
 
 /* Wait a set number of microseconds */
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v5 05/12] xen/arm: irq: avoid local IRQ descriptors reinit on system resume
Date: Mon, 11 Aug 2025 23:48:01 +0300
Message-ID: <7686bc019f0c0eff94720e4ca16e00f895819087.1754943874.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

On ARM, during system resume, CPUs are brought online again. This normally
triggers init_local_irq_data, which reinitializes IRQ descriptors for
banked interrupts (SGIs and PPIs).

These descriptors are statically allocated per CPU and retain valid
state across suspend/resume cycles. Re-initializing them on resume is
unnecessary and may result in loss of interrupt configuration or
restored state.

This patch skips init_local_irq_data when system_state is set to
SYS_STATE_resume to preserve banked IRQ descs state during resume.

Signed-off-by: Mykola Kvach 
---
 xen/arch/arm/irq.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 4bbf0b0664..148f184f8b 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -122,6 +122,10 @@ static int cpu_callback(struct notifier_block *nfb, unsigned long action,
     switch ( action )
     {
     case CPU_UP_PREPARE:
+        /* Skip local IRQ cleanup on resume */
+        if ( system_state == SYS_STATE_resume )
+            break;
+
         rc = init_local_irq_data(cpu);
         if ( rc )
             printk(XENLOG_ERR "Unable to allocate local IRQ for CPU%u\n",
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v5 06/12] xen/arm: irq: Restore state of local IRQs during system resume
Date: Mon, 11 Aug 2025 23:48:02 +0300
Message-ID: <779a90853f249f8d8c4973874baeee1f787e92e0.1754943875.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

On ARM, the first 32 interrupts (SGIs and PPIs) are banked per-CPU
and not restored by gic_resume (for secondary cpus).

This patch introduces restore_local_irqs_on_resume, a function that
restores the state of local interrupts on the target CPU during
system resume.

It iterates over all local IRQs and re-enables those that were not
disabled, reprogramming their routing and affinity accordingly.

The function is invoked from start_secondary, ensuring that local IRQ
state is restored early during CPU bring-up after suspend.

Signed-off-by: Mykola Kvach 
---
 xen/arch/arm/irq.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 148f184f8b..b3ff38dc27 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -113,6 +113,47 @@ static int init_local_irq_data(unsigned int cpu)
     return 0;
 }
 
+/*
+ * The first 32 interrupts (PPIs and SGIs) are per-CPU,
+ * so call this function on the target CPU to restore them.
+ *
+ * SPIs are restored via gic_resume.
+ */
+static void restore_local_irqs_on_resume(void)
+{
+    int irq;
+
+    if ( system_state != SYS_STATE_resume )
+        return;
+
+    spin_lock(&local_irqs_type_lock);
+
+    for ( irq = 0; irq < NR_LOCAL_IRQS; irq++ )
+    {
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        spin_lock(&desc->lock);
+
+        if ( test_bit(_IRQ_DISABLED, &desc->status) )
+        {
+            spin_unlock(&desc->lock);
+            continue;
+        }
+
+        /* it is needed to avoid asserts in below calls */
+        set_bit(_IRQ_DISABLED, &desc->status);
+
+        gic_route_irq_to_xen(desc, GIC_PRI_IRQ);
+
+        /* _IRQ_DISABLED is cleared by below call */
+        desc->handler->startup(desc);
+
+        spin_unlock(&desc->lock);
+    }
+
+    spin_unlock(&local_irqs_type_lock);
+}
+
 static int cpu_callback(struct notifier_block *nfb, unsigned long action,
                         void *hcpu)
 {
@@ -131,6 +172,9 @@ static int cpu_callback(struct notifier_block *nfb, unsigned long action,
             printk(XENLOG_ERR "Unable to allocate local IRQ for CPU%u\n",
                    cpu);
         break;
+    case CPU_STARTING:
+        restore_local_irqs_on_resume();
+        break;
     }
 
     return notifier_from_errno(rc);
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mirela Simonovic ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Saeed Nowshadi ,
	Mykyta Poturai ,
	Mykola Kvach 
Subject: [PATCH v5 07/12] xen/arm: Add support for system suspend triggered by hardware domain
Date: Mon, 11 Aug 2025 23:48:03 +0300
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From: Mirela Simonovic 

Trigger Xen suspend when the hardware domain initiates suspend via
SHUTDOWN_suspend. Redirect system suspend to CPU#0 to ensure the
suspend logic runs on the boot CPU, as required.

Introduce full suspend/resume infrastructure gated by CONFIG_SYSTEM_SUSPEND,
including logic to:
 - disable and enable non-boot physical CPUs
 - freeze and thaw domains
 - suspend and resume the GIC, timer and console
 - maintain system state before and after suspend

Remove the restriction in the PSCI interface preventing suspend from the
hardware domain.

Select HAS_SYSTEM_SUSPEND for ARM_64.

Signed-off-by: Mirela Simonovic 
Signed-off-by: Saeed Nowshadi 
Signed-off-by: Mykyta Poturai 
Signed-off-by: Mykola Kvach 
---
Changes in v5:
- select HAS_SYSTEM_SUSPEND in ARM_64 instead of ARM
- check llc_coloring_enabled instead of LLC_COLORING during the selection
  of HAS_SYSTEM_SUSPEND config
- call host_system_suspend from guest PSCI system suspend instead of
  arch_domain_shutdown, reducing the complexity of the new code
- update some comments

Changes introduced in V4:
  - drop code for saving and restoring VCPU context (for more information
    refer part 1 of patch series)
  - remove IOMMU suspend and resume calls until they will be implemented
  - move system suspend logic to arch_domain_shutdown, invoked from
    domain_shutdown
  - apply minor fixes such as renaming functions, updating comments, and
    modifying the commit message to reflect these changes
  - add console_end_sync to resume path after system suspend

Changes introduced in V3:
  - merge changes from other commits into this patch (previously stashed):
    1) disable/enable non-boot physical CPUs and freeze/thaw domains during
       suspend/resume
    2) suspend/resume the timer, GIC, console, IOMMU, and hardware domain
---
 xen/arch/arm/Kconfig               |   1 +
 xen/arch/arm/Makefile              |   1 +
 xen/arch/arm/include/asm/suspend.h |  22 +++++
 xen/arch/arm/suspend.c             | 151 +++++++++++++++++++++++++++++
 xen/arch/arm/vpsci.c               |  12 ++-
 xen/common/domain.c                |   4 +
 6 files changed, 190 insertions(+), 1 deletion(-)
 create mode 100644 xen/arch/arm/include/asm/suspend.h
 create mode 100644 xen/arch/arm/suspend.c

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index a0c8160474..ccdbaa5bc3 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -8,6 +8,7 @@ config ARM_64
 	depends on !ARM_32
 	select 64BIT
 	select HAS_FAST_MULTIPLY
+	select HAS_SYSTEM_SUSPEND if UNSUPPORTED
 	select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH
 
 config ARM
diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
index f833cdf207..3f6247adee 100644
--- a/xen/arch/arm/Makefile
+++ b/xen/arch/arm/Makefile
@@ -51,6 +51,7 @@ obj-y += setup.o
 obj-y += shutdown.o
 obj-y += smp.o
 obj-y += smpboot.o
+obj-$(CONFIG_SYSTEM_SUSPEND) += suspend.o
 obj-$(CONFIG_SYSCTL) += sysctl.o
 obj-y += time.o
 obj-y += traps.o
diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/asm/suspend.h
new file mode 100644
index 0000000000..78d0e2383b
--- /dev/null
+++ b/xen/arch/arm/include/asm/suspend.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ASM_ARM_SUSPEND_H__
+#define __ASM_ARM_SUSPEND_H__
+
+#ifdef CONFIG_SYSTEM_SUSPEND
+
+int host_system_suspend(void);
+
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
+#endif /* __ASM_ARM_SUSPEND_H__ */
+
+ /*
+  * Local variables:
+  * mode: C
+  * c-file-style: "BSD"
+  * c-basic-offset: 4
+  * tab-width: 4
+  * indent-tabs-mode: nil
+  * End:
+  */
diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
new file mode 100644
index 0000000000..abf4b928ce
--- /dev/null
+++ b/xen/arch/arm/suspend.c
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * TODO list:
+ *  - Test system suspend with LLC_COLORING enabled and verify functionality
+ *  - Implement IOMMU suspend/resume handlers and integrate them
+ *    into the suspend/resume path (IPMMU and SMMU)
+ *  - Enable "xl suspend" support on ARM architecture
+ *  - Properly disable Xen timer watchdog from relevant services
+ *  - Add suspend/resume CI test for ARM (QEMU if feasible)
+ *  - Investigate feasibility and need for implementing system suspend on ARM32
+ */
+
+/* Xen suspend. Note: data is not used (suspend is the suspend to RAM) */
+static long system_suspend(void *data)
+{
+    int status;
+    unsigned long flags;
+
+    BUG_ON(system_state != SYS_STATE_active);
+
+    system_state = SYS_STATE_suspend;
+    freeze_domains();
+    scheduler_disable();
+
+    /*
+     * Non-boot CPUs have to be disabled on suspend and enabled on resume
+     * (hotplug-based mechanism). Disabling non-boot CPUs will lead to PSCI
+     * CPU_OFF to be called by each non-boot CPU. Depending on the underlying
+     * platform capabilities, this may lead to the physical powering down of
+     * CPUs. Tested on Xilinx Zynq Ultrascale+ MPSoC (including power down of
+     * each non-boot CPU).
+     */
+    status = disable_nonboot_cpus();
+    if ( status )
+    {
+        system_state = SYS_STATE_resume;
+        goto resume_nonboot_cpus;
+    }
+
+    time_suspend();
+
+    local_irq_save(flags);
+    status = gic_suspend();
+    if ( status )
+    {
+        system_state = SYS_STATE_resume;
+        goto resume_irqs;
+    }
+
+    printk("Xen suspending...\n");
+
+    console_start_sync();
+    status = console_suspend();
+    if ( status )
+    {
+        dprintk(XENLOG_ERR, "Failed to suspend the console, err=%d\n", status);
+        system_state = SYS_STATE_resume;
+        goto resume_console;
+    }
+
+    /*
+     * Enable identity mapping before entering suspend to simplify
+     * the resume path
+     */
+    update_boot_mapping(true);
+
+    system_state = SYS_STATE_resume;
+    update_boot_mapping(false);
+
+ resume_console:
+    console_resume();
+    console_end_sync();
+
+    gic_resume();
+
+ resume_irqs:
+    local_irq_restore(flags);
+    time_resume();
+
+ resume_nonboot_cpus:
+    /*
+     * The rcu_barrier() has to be added to ensure that the per cpu area is
+     * freed before a non-boot CPU tries to initialize it (_free_percpu_area()
+     * has to be called before the init_percpu_area()). This scenario occurs
+     * when non-boot CPUs are hot-unplugged on suspend and hotplugged on resume.
+     */
+    rcu_barrier();
+    enable_nonboot_cpus();
+    scheduler_enable();
+    thaw_domains();
+
+    system_state = SYS_STATE_active;
+
+    /* The resume of hardware domain should always follow Xen's resume. */
+    domain_resume(hardware_domain);
+
+    printk("Resume (status %d)\n", status);
+    return status;
+}
+
+int host_system_suspend(void)
+{
+    int status;
+
+    /* TODO: drop check after verification that features can work together */
+    if ( llc_coloring_enabled )
+    {
+        dprintk(XENLOG_ERR,
+                "System suspend is not supported with LLC_COLORING enabled\n");
+        return -ENOSYS;
+    }
+
+    /*
+     * system_suspend should be called when Dom0 finalizes the suspend
+     * procedure from its boot core (VCPU#0). However, Dom0's VCPU#0 could
+     * be mapped to any PCPU (this function could be executed by any PCPU).
+     * The suspend procedure has to be finalized by the PCPU#0 (non-boot
+     * PCPUs will be disabled during the suspend).
+     */
+    status = continue_hypercall_on_cpu(0, system_suspend, NULL);
+
+    /*
+     * If an error happened, there is nothing that needs to be done here
+     * because the system_suspend always returns in fully functional state
+     * no matter what the outcome of suspend procedure is. If the system
+     * suspended successfully the function will return 0 after the resume.
+     * Otherwise, if an error is returned it means Xen did not suspended,
+     * but it is still in the same state as if the system_suspend was never
+     * called. We dump a debug message in case of an error for debugging/
+     * logging purpose.
+     */
+    if ( status )
+        dprintk(XENLOG_ERR, "Failed to suspend, errno=%d\n", status);
+
+    return status;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index 67d369a8a2..757e719ea7 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -4,6 +4,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -214,9 +215,10 @@ static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid)
     struct vcpu *v;
     struct domain *d = current->domain;
 
-    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
+#ifndef CONFIG_SYSTEM_SUSPEND
     if ( is_hardware_domain(d) )
         return PSCI_NOT_SUPPORTED;
+#endif
 
     /* Ensure that all CPUs other than the calling one are offline */
     domain_lock(d);
@@ -234,6 +236,14 @@ static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid)
     if ( rc )
         return PSCI_DENIED;
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+    if ( is_hardware_domain(d) && host_system_suspend() )
+    {
+        domain_resume_nopause(d);
+        return PSCI_DENIED;
+    }
+#endif
+
     rc = do_setup_vcpu_ctx(current, epoint, cid);
     if ( rc != PSCI_SUCCESS )
     {
diff --git a/xen/common/domain.c b/xen/common/domain.c
index c3609b0cb0..414a691242 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -1311,7 +1311,11 @@ int domain_shutdown(struct domain *d, u8 reason)
         d->shutdown_code = reason;
     reason = d->shutdown_code;
 
+#if defined(CONFIG_SYSTEM_SUSPEND) && defined(CONFIG_ARM)
+    if ( reason != SHUTDOWN_suspend && is_hardware_domain(d) )
+#else
     if ( is_hardware_domain(d) )
+#endif
         hwdom_shutdown(reason);
 
     if ( d->is_shutting_down )
-- 
2.48.1



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        Mon, 11 Aug 2025 13:49:00 -0700 (PDT)
From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mirela Simonovic ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Saeed Nowshadi ,
	Mykyta Poturai ,
	Mykola Kvach 
Subject: [PATCH v5 08/12] xen/arm: Implement PSCI SYSTEM_SUSPEND call (host interface)
Date: Mon, 11 Aug 2025 23:48:04 +0300
Message-ID: 
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From: Mirela Simonovic 

Invoke PSCI SYSTEM_SUSPEND to finalize Xen's suspend sequence on ARM64 platforms.
Pass the resume entry point (hyp_resume) as the first argument to EL3. The resume
handler is currently a stub and will be implemented later in assembly. Ignore the
context ID argument, as is done in Linux.

Only enable this path when CONFIG_SYSTEM_SUSPEND is set and
PSCI version is >= 1.0.

Signed-off-by: Mirela Simonovic 
Signed-off-by: Saeed Nowshadi 
Signed-off-by: Mykyta Poturai 
Signed-off-by: Mykola Kvach 
---
Changes in v4:
  - select the appropriate PSCI SYSTEM_SUSPEND function ID based on platform
  - update comments and commit message to reflect recent changes

Changes in v3:
  - return PSCI_NOT_SUPPORTED instead of a hardcoded 1 on ARM32
  - check PSCI version before invoking SYSTEM_SUSPEND in call_psci_system_suspend
---
 xen/arch/arm/arm64/head.S          |  8 ++++++++
 xen/arch/arm/include/asm/psci.h    |  1 +
 xen/arch/arm/include/asm/suspend.h |  2 ++
 xen/arch/arm/psci.c                | 23 ++++++++++++++++++++++-
 xen/arch/arm/suspend.c             |  5 +++++
 5 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 72c7b24498..3522c497c5 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -561,6 +561,14 @@ END(efi_xen_start)
 
 #endif /* CONFIG_ARM_EFI */
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+
+FUNC(hyp_resume)
+        b .
+END(hyp_resume)
+
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
 /*
  * Local variables:
  * mode: ASM
diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/psci.h
index 48a93e6b79..bb3c73496e 100644
--- a/xen/arch/arm/include/asm/psci.h
+++ b/xen/arch/arm/include/asm/psci.h
@@ -23,6 +23,7 @@ int call_psci_cpu_on(int cpu);
 void call_psci_cpu_off(void);
 void call_psci_system_off(void);
 void call_psci_system_reset(void);
+int call_psci_system_suspend(void);
 
 /* Range of allocated PSCI function numbers */
 #define	PSCI_FNUM_MIN_VALUE                 _AC(0,U)
diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/asm/suspend.h
index 78d0e2383b..55041a5d06 100644
--- a/xen/arch/arm/include/asm/suspend.h
+++ b/xen/arch/arm/include/asm/suspend.h
@@ -7,6 +7,8 @@
 
 int host_system_suspend(void);
 
+void hyp_resume(void);
+
 #endif /* CONFIG_SYSTEM_SUSPEND */
 
 #endif /* __ASM_ARM_SUSPEND_H__ */
diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c
index b6860a7760..c9d126b195 100644
--- a/xen/arch/arm/psci.c
+++ b/xen/arch/arm/psci.c
@@ -17,17 +17,20 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * While a 64-bit OS can make calls with SMC32 calling conventions, for
  * some calls it is necessary to use SMC64 to pass or return 64-bit values.
- * For such calls PSCI_0_2_FN_NATIVE(x) will choose the appropriate
+ * For such calls PSCI_*_FN_NATIVE(x) will choose the appropriate
  * (native-width) function ID.
  */
 #ifdef CONFIG_ARM_64
 #define PSCI_0_2_FN_NATIVE(name)    PSCI_0_2_FN64_##name
+#define PSCI_1_0_FN_NATIVE(name)    PSCI_1_0_FN64_##name
 #else
 #define PSCI_0_2_FN_NATIVE(name)    PSCI_0_2_FN32_##name
+#define PSCI_1_0_FN_NATIVE(name)    PSCI_1_0_FN32_##name
 #endif
 
 uint32_t psci_ver;
@@ -60,6 +63,24 @@ void call_psci_cpu_off(void)
     }
 }
 
+int call_psci_system_suspend(void)
+{
+#ifdef CONFIG_SYSTEM_SUSPEND
+    struct arm_smccc_res res;
+
+    if ( psci_ver < PSCI_VERSION(1, 0) )
+        return PSCI_NOT_SUPPORTED;
+
+    /* 2nd argument (context ID) is not used */
+    arm_smccc_smc(PSCI_1_0_FN_NATIVE(SYSTEM_SUSPEND), __pa(hyp_resume), &res);
+    return PSCI_RET(res);
+#else
+    dprintk(XENLOG_WARNING,
+            "SYSTEM_SUSPEND not supported (CONFIG_SYSTEM_SUSPEND disabled)\n");
+    return PSCI_NOT_SUPPORTED;
+#endif
+}
+
 void call_psci_system_off(void)
 {
     if ( psci_ver > PSCI_VERSION(0, 1) )
diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
index abf4b928ce..11e86b7f51 100644
--- a/xen/arch/arm/suspend.c
+++ b/xen/arch/arm/suspend.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include 
 #include 
 #include 
 #include 
@@ -70,6 +71,10 @@ static long system_suspend(void *data)
      */
     update_boot_mapping(true);
 
+    status = call_psci_system_suspend();
+    if ( status )
+        dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=%d\n", status);
+
     system_state = SYS_STATE_resume;
     update_boot_mapping(false);
 
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mirela Simonovic ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Saeed Nowshadi ,
	Mykyta Poturai ,
	Mykola Kvach 
Subject: [PATCH v5 09/12] xen/arm: Resume memory management on Xen resume
Date: Mon, 11 Aug 2025 23:48:05 +0300
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From: Mirela Simonovic 

The MMU must be enabled during the resume path before restoring context,
as virtual addresses are used to access the saved context data.

This patch adds MMU setup during resume by reusing the existing
enable_secondary_cpu_mm function, which enables data cache and the MMU.
Before the MMU is enabled, the content of TTBR0_EL2 is changed to point
to init_ttbr (page tables used at runtime).

On boot, init_ttbr is normally initialized during secondary CPU hotplug.
On uniprocessor systems, this would leave init_ttbr uninitialized,
causing resume to fail. To address this, the boot CPU now sets init_ttbr
during suspend.

Signed-off-by: Mirela Simonovic 
Signed-off-by: Saeed Nowshadi 
Signed-off-by: Mykyta Poturai 
Signed-off-by: Mykola Kvach 
---
Changes in v4:
- Drop unnecessary DAIF masking; interrupts are already masked on resume
- Remove leftover TLB flush instructions; flushing is done in enable_mmu
- Avoid setting x19 in hyp_resume; not needed
- Replace prepare_secondary_mm with set_init_ttbr; call it from system_suspend

Changes in v3:
- Update commit message for clarity
- Replace create_page_tables, enable_mmu, and mmu_init_secondary_cpu
  with enable_secondary_cpu_mm
- Move prepare_secondary_mm to start_xen to avoid crash
- Add early UART init during resume

Changes in v2:
- Move hyp_resume to head.S to keep resume logic together
- Simplify hyp_resume using existing helpers: check_cpu_mode, cpu_init,
  create_page_tables, enable_mmu
---
 xen/arch/arm/arm64/head.S     | 16 ++++++++++++++++
 xen/arch/arm/include/asm/mm.h |  2 ++
 xen/arch/arm/mmu/smpboot.c    |  2 +-
 xen/arch/arm/suspend.c        |  2 ++
 4 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 3522c497c5..596e960152 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -564,6 +564,22 @@ END(efi_xen_start)
 #ifdef CONFIG_SYSTEM_SUSPEND
 
 FUNC(hyp_resume)
+        /* Initialize the UART if earlyprintk has been enabled. */
+#ifdef CONFIG_EARLY_PRINTK
+        bl    init_uart
+#endif
+        PRINT_ID("- Xen resuming -\r\n")
+
+        bl    check_cpu_mode
+        bl    cpu_init
+
+        ldr   x0, =start
+        adr   x20, start             /* x20 := paddr (start) */
+        sub   x20, x20, x0           /* x20 := phys-offset */
+        ldr   lr, =mmu_resumed
+        b     enable_secondary_cpu_mm
+
+mmu_resumed:
         b .
 END(hyp_resume)
 
diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h
index fb79aeb088..3400cb2bff 100644
--- a/xen/arch/arm/include/asm/mm.h
+++ b/xen/arch/arm/include/asm/mm.h
@@ -365,6 +365,8 @@ static inline void page_set_xenheap_gfn(struct page_info *p, gfn_t gfn)
     } while ( (y = cmpxchg(&p->u.inuse.type_info, x, nx)) != x );
 }
 
+void set_init_ttbr(lpae_t *root);
+
 #endif /*  __ARCH_ARM_MM__ */
 /*
  * Local variables:
diff --git a/xen/arch/arm/mmu/smpboot.c b/xen/arch/arm/mmu/smpboot.c
index 37e91d72b7..ff508ecf40 100644
--- a/xen/arch/arm/mmu/smpboot.c
+++ b/xen/arch/arm/mmu/smpboot.c
@@ -72,7 +72,7 @@ static void clear_boot_pagetables(void)
     clear_table(boot_third);
 }
 
-static void set_init_ttbr(lpae_t *root)
+void set_init_ttbr(lpae_t *root)
 {
     /*
      * init_ttbr is part of the identity mapping which is read-only. So
diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
index 11e86b7f51..08b6acaede 100644
--- a/xen/arch/arm/suspend.c
+++ b/xen/arch/arm/suspend.c
@@ -65,6 +65,8 @@ static long system_suspend(void *data)
         goto resume_console;
     }
 
+    set_init_ttbr(xen_pgtable);
+
     /*
      * Enable identity mapping before entering suspend to simplify
      * the resume path
-- 
2.48.1



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        Mon, 11 Aug 2025 13:49:04 -0700 (PDT)
From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mirela Simonovic ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Saeed Nowshadi ,
	Mykyta Poturai ,
	Mykola Kvach 
Subject: [PATCH v5 10/12] xen/arm: Save/restore context on suspend/resume
Date: Mon, 11 Aug 2025 23:48:06 +0300
Message-ID: <5441d6712a4ca0e61fd066606b9a96414123aaad.1754943875.git.mykola_kvach@epam.com>
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From: Mirela Simonovic 

The context of CPU general purpose and system control registers
has to be saved on suspend and restored on resume. This is
implemented in hyp_suspend and before the return from hyp_resume
function. The hyp_suspend is invoked just before the PSCI system
suspend call is issued to the ATF. The hyp_suspend has to return a
non-zero value so that the calling 'if' statement evaluates to true,
causing the system suspend to be invoked. Upon the resume, context
saved on suspend will be restored, including the link register.
Therefore, after restoring the context the control flow will
return to the address pointed by the saved link register, which
is the place from which the hyp_suspend was called. To ensure
that the calling 'if' statement doesn't again evaluate to true
and initiate system suspend, hyp_resume has to return a zero value
after restoring the context.

Note that the order of saving register context into cpu_context
structure has to match the order of restoring.

Support for ARM32 is not implemented. Instead, compilation fails with a
build-time error if suspend is enabled for ARM32.

Signed-off-by: Mirela Simonovic 
Signed-off-by: Saeed Nowshadi 
Signed-off-by: Mykyta Poturai 
Signed-off-by: Mykola Kvach 
---
Changes in v4:
- produce build-time error for ARM32 when CONFIG_SYSTEM_SUSPEND is enabled
- use register_t instead of uint64_t in cpu_context structure
---
 xen/arch/arm/arm64/head.S          | 91 +++++++++++++++++++++++++++++-
 xen/arch/arm/include/asm/suspend.h | 20 +++++++
 xen/arch/arm/suspend.c             | 23 +++++++-
 3 files changed, 130 insertions(+), 4 deletions(-)

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 596e960152..ad8b48de3a 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -562,6 +562,52 @@ END(efi_xen_start)
 #endif /* CONFIG_ARM_EFI */
 
 #ifdef CONFIG_SYSTEM_SUSPEND
+/*
+ * int hyp_suspend(struct cpu_context *ptr)
+ *
+ * x0 - pointer to the storage where callee's context will be saved
+ *
+ * CPU context saved here will be restored on resume in hyp_resume function.
+ * hyp_suspend shall return a non-zero value. Upon restoring context
+ * hyp_resume shall return value zero instead. From C code that invokes
+ * hyp_suspend, the return value is interpreted to determine whether the context
+ * is saved (hyp_suspend) or restored (hyp_resume).
+ */
+FUNC(hyp_suspend)
+        /* Store callee-saved registers */
+        stp     x19, x20, [x0], #16
+        stp     x21, x22, [x0], #16
+        stp     x23, x24, [x0], #16
+        stp     x25, x26, [x0], #16
+        stp     x27, x28, [x0], #16
+        stp     x29, lr, [x0], #16
+
+        /* Store stack-pointer */
+        mov     x2, sp
+        str     x2, [x0], #8
+
+        /* Store system control registers */
+        mrs     x2, VBAR_EL2
+        str     x2, [x0], #8
+        mrs     x2, VTCR_EL2
+        str     x2, [x0], #8
+        mrs     x2, VTTBR_EL2
+        str     x2, [x0], #8
+        mrs     x2, TPIDR_EL2
+        str     x2, [x0], #8
+        mrs     x2, MDCR_EL2
+        str     x2, [x0], #8
+        mrs     x2, HSTR_EL2
+        str     x2, [x0], #8
+        mrs     x2, CPTR_EL2
+        str     x2, [x0], #8
+        mrs     x2, HCR_EL2
+        str     x2, [x0], #8
+
+        /* hyp_suspend must return a non-zero value */
+        mov     x0, #1
+        ret
+END(hyp_suspend)
 
 FUNC(hyp_resume)
         /* Initialize the UART if earlyprintk has been enabled. */
@@ -580,7 +626,50 @@ FUNC(hyp_resume)
         b     enable_secondary_cpu_mm
 
 mmu_resumed:
-        b .
+        /*
+         * Now we can access the cpu_context, so restore the context here
+         * TODO: can we reuse __context_switch and saved_context struct here ?
+         */
+        ldr     x0, =cpu_context
+
+        /* Restore callee-saved registers */
+        ldp     x19, x20, [x0], #16
+        ldp     x21, x22, [x0], #16
+        ldp     x23, x24, [x0], #16
+        ldp     x25, x26, [x0], #16
+        ldp     x27, x28, [x0], #16
+        ldp     x29, lr, [x0], #16
+
+        /* Restore stack pointer */
+        ldr     x2, [x0], #8
+        mov     sp, x2
+
+        /* Restore system control registers */
+        ldr     x2, [x0], #8
+        msr     VBAR_EL2, x2
+        ldr     x2, [x0], #8
+        msr     VTCR_EL2, x2
+        ldr     x2, [x0], #8
+        msr     VTTBR_EL2, x2
+        ldr     x2, [x0], #8
+        msr     TPIDR_EL2, x2
+        ldr     x2, [x0], #8
+        msr     MDCR_EL2, x2
+        ldr     x2, [x0], #8
+        msr     HSTR_EL2, x2
+        ldr     x2, [x0], #8
+        msr     CPTR_EL2, x2
+        ldr     x2, [x0], #8
+        msr     HCR_EL2, x2
+        isb
+
+        /* Since context is restored return from this function will appear as
+         * return from hyp_suspend. To distinguish a return from hyp_suspend
+         * which is called upon finalizing the suspend, as opposed to return
+         * from this function which executes on resume, we need to return zero
+         * value here. */
+        mov x0, #0
+        ret
 END(hyp_resume)
 
 #endif /* CONFIG_SYSTEM_SUSPEND */
diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/asm/suspend.h
index 55041a5d06..ae71ccb87b 100644
--- a/xen/arch/arm/include/asm/suspend.h
+++ b/xen/arch/arm/include/asm/suspend.h
@@ -5,9 +5,29 @@
 
 #ifdef CONFIG_SYSTEM_SUSPEND
 
+#ifdef CONFIG_ARM_64
+struct cpu_context {
+    register_t callee_regs[12];
+    register_t sp;
+    register_t vbar_el2;
+    register_t vtcr_el2;
+    register_t vttbr_el2;
+    register_t tpidr_el2;
+    register_t mdcr_el2;
+    register_t hstr_el2;
+    register_t cptr_el2;
+    register_t hcr_el2;
+} __aligned(16);
+#else
+#error "Define cpu_context structure for arm32"
+#endif
+
+extern struct cpu_context cpu_context;
+
 int host_system_suspend(void);
 
 void hyp_resume(void);
+int hyp_suspend(struct cpu_context *ptr);
 
 #endif /* CONFIG_SYSTEM_SUSPEND */
 
diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
index 08b6acaede..b5398e5ca6 100644
--- a/xen/arch/arm/suspend.c
+++ b/xen/arch/arm/suspend.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -17,6 +18,8 @@
  *  - Investigate feasibility and need for implementing system suspend on ARM32
  */
 
+struct cpu_context cpu_context;
+
 /* Xen suspend. Note: data is not used (suspend is the suspend to RAM) */
 static long system_suspend(void *data)
 {
@@ -73,9 +76,23 @@ static long system_suspend(void *data)
      */
     update_boot_mapping(true);
 
-    status = call_psci_system_suspend();
-    if ( status )
-        dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=%d\n", status);
+    if ( hyp_suspend(&cpu_context) )
+    {
+        status = call_psci_system_suspend();
+        /*
+         * If suspend is finalized properly by above system suspend PSCI call,
+         * the code below in this 'if' branch will never execute. Execution
+         * will continue from hyp_resume which is the hypervisor's resume point.
+         * In hyp_resume CPU context will be restored and since link-register is
+         * restored as well, it will appear to return from hyp_suspend. The
+         * difference in returning from hyp_suspend on system suspend versus
+         * resume is in function's return value: on suspend, the return value is
+         * a non-zero value, on resume it is zero. That is why the control flow
+         * will not re-enter this 'if' branch on resume.
+         */
+        if ( status )
+            dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=%d\n", status);
+    }
 
     system_state = SYS_STATE_resume;
     update_boot_mapping(false);
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Oleksandr Tyshchenko ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Mykola Kvach ,
	Oleksandr Andrushchenko 
Subject: [PATCH v5 12/12] xen/arm: Suspend/resume IOMMU on Xen suspend/resume
Date: Mon, 11 Aug 2025 23:48:08 +0300
Message-ID: <821e0762f64c8b33260a59c672eabf1da5fb4dd4.1754943875.git.mykola_kvach@epam.com>
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From: Oleksandr Tyshchenko 

This is done using generic iommu_suspend/resume functions that cause
IOMMU driver specific suspend/resume handlers to be called for enabled
IOMMU (if one has suspend/resume driver handlers implemented).

These handlers work only when IPMMU-VMSA is used; otherwise,
we return an error during system suspend requests.

Signed-off-by: Oleksandr Tyshchenko 
Signed-off-by: Mykola Kvach 
Tested-by: Oleksandr Andrushchenko 
---
 xen/arch/arm/suspend.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
index b5398e5ca6..cb86426ebd 100644
--- a/xen/arch/arm/suspend.c
+++ b/xen/arch/arm/suspend.c
@@ -4,6 +4,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -49,6 +50,13 @@ static long system_suspend(void *data)
 
     time_suspend();
 
+    status = iommu_suspend();
+    if ( status )
+    {
+        system_state = SYS_STATE_resume;
+        goto resume_time;
+    }
+
     local_irq_save(flags);
     status = gic_suspend();
     if ( status )
@@ -105,6 +113,10 @@ static long system_suspend(void *data)
 
  resume_irqs:
     local_irq_restore(flags);
+
+    iommu_resume();
+
+ resume_time:
     time_resume();
 
  resume_nonboot_cpus:
@@ -140,6 +152,15 @@ int host_system_suspend(void)
         return -ENOSYS;
     }
 
+    /* TODO: drop check once suspend/resume support for SMMU is implemented */
+#ifndef CONFIG_IPMMU_VMSA
+    if ( iommu_enabled )
+    {
+        dprintk(XENLOG_ERR, "IOMMU is enabled, suspend not supported yet\n");
+        return -ENOSYS;
+    }
+#endif
+
     /*
      * system_suspend should be called when Dom0 finalizes the suspend
      * procedure from its boot core (VCPU#0). However, Dom0's VCPU#0 could
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Oleksandr Tyshchenko ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Mykola Kvach 
Subject: [PATCH v5 11/12] iommu/ipmmu-vmsa: Implement suspend/resume callbacks
Date: Mon, 11 Aug 2025 23:48:07 +0300
Message-ID: <1689d707b930b1ea4f63cc150810e548962cda81.1754943875.git.mykola_kvach@epam.com>
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From: Oleksandr Tyshchenko 

Store and restore active context and micro-TLB registers.

Tested on R-Car H3 Starter Kit.

Signed-off-by: Oleksandr Tyshchenko 
Signed-off-by: Mykola Kvach 
---
 xen/drivers/passthrough/arm/ipmmu-vmsa.c | 269 +++++++++++++++++++++++
 1 file changed, 269 insertions(+)

diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
index dac0dd6d46..ced762657a 100644
--- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
+++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
@@ -58,6 +58,8 @@
 #define dev_print(dev, lvl, fmt, ...)    \
     printk(lvl "ipmmu: %s: " fmt, dev_name(dev), ## __VA_ARGS__)
 
+#define dev_dbg(dev, fmt, ...)    \
+    dev_print(dev, XENLOG_DEBUG, fmt, ## __VA_ARGS__)
 #define dev_info(dev, fmt, ...)    \
     dev_print(dev, XENLOG_INFO, fmt, ## __VA_ARGS__)
 #define dev_warn(dev, fmt, ...)    \
@@ -117,6 +119,23 @@ struct ipmmu_features {
     unsigned int imuctr_ttsel_mask;
 };
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+
+struct hw_register {
+    const char *reg_name;
+    unsigned int reg_offset;
+    unsigned int reg_data;
+};
+
+struct ipmmu_vmsa_backup {
+    struct device *dev;
+    unsigned int *utlbs_val;
+    unsigned int *asids_val;
+    struct list_head list;
+};
+
+#endif
+
 /* Root/Cache IPMMU device's information */
 struct ipmmu_vmsa_device {
     struct device *dev;
@@ -129,6 +148,9 @@ struct ipmmu_vmsa_device {
     struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
     unsigned int utlb_refcount[IPMMU_UTLB_MAX];
     const struct ipmmu_features *features;
+#ifdef CONFIG_SYSTEM_SUSPEND
+    struct hw_register *reg_backup[IPMMU_CTX_MAX];
+#endif
 };
 
 /*
@@ -534,6 +556,235 @@ static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
     spin_unlock_irqrestore(&mmu->lock, flags);
 }
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+
+static DEFINE_SPINLOCK(ipmmu_devices_backup_lock);
+static LIST_HEAD(ipmmu_devices_backup);
+
+#define HW_REGISTER_BACKUP_SIZE 4
+
+static struct hw_register root_pgtable[IPMMU_CTX_MAX][HW_REGISTER_BACKUP_SIZE] = {
+    [0 ... (IPMMU_CTX_MAX - 1)] = {
+        {"IMTTLBR0", IMTTLBR0, 0},
+        {"IMTTUBR0", IMTTUBR0, 0},
+        {"IMTTBCR",  IMTTBCR,  0},
+        {"IMCTR",    IMCTR,    0},
+    }
+};
+
+static uint32_t ipmmu_imuasid_read(struct ipmmu_vmsa_device *mmu,
+                                   unsigned int utlb)
+{
+    return ipmmu_read(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)));
+}
+
+static void ipmmu_utlbs_backup(struct ipmmu_vmsa_device *mmu)
+{
+    struct ipmmu_vmsa_backup *backup_data;
+
+    dev_dbg(mmu->dev, "Handle micro-TLBs backup\n");
+
+    spin_lock(&ipmmu_devices_backup_lock);
+
+    list_for_each_entry( backup_data, &ipmmu_devices_backup, list )
+    {
+        struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(backup_data->dev);
+        unsigned int i;
+
+        if ( to_ipmmu(backup_data->dev) != mmu )
+            continue;
+
+        for ( i = 0; i < fwspec->num_ids; i++ )
+        {
+            unsigned int utlb = fwspec->ids[i];
+
+            backup_data->asids_val[i] = ipmmu_imuasid_read(mmu, utlb);
+            backup_data->utlbs_val[i] = ipmmu_imuctr_read(mmu, utlb);
+        }
+    }
+
+    spin_unlock(&ipmmu_devices_backup_lock);
+}
+
+static void ipmmu_utlbs_restore(struct ipmmu_vmsa_device *mmu)
+{
+    struct ipmmu_vmsa_backup *backup_data;
+
+    dev_dbg(mmu->dev, "Handle micro-TLBs restore\n");
+
+    spin_lock(&ipmmu_devices_backup_lock);
+
+    list_for_each_entry( backup_data, &ipmmu_devices_backup, list )
+    {
+        struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(backup_data->dev);
+        unsigned int i;
+
+        if ( to_ipmmu(backup_data->dev) != mmu )
+            continue;
+
+        for ( i = 0; i < fwspec->num_ids; i++ )
+        {
+            unsigned int utlb = fwspec->ids[i];
+
+            ipmmu_imuasid_write(mmu, utlb, backup_data->asids_val[i]);
+            ipmmu_imuctr_write(mmu, utlb, backup_data->utlbs_val[i]);
+        }
+    }
+
+    spin_unlock(&ipmmu_devices_backup_lock);
+}
+
+static void ipmmu_domain_backup_context(struct ipmmu_vmsa_domain *domain)
+{
+    struct ipmmu_vmsa_device *mmu = domain->mmu->root;
+    struct hw_register *reg = mmu->reg_backup[domain->context_id];
+    unsigned int i;
+
+    dev_dbg(mmu->dev, "Handle domain context %u backup\n", domain->context_id);
+
+    for ( i = 0; i < HW_REGISTER_BACKUP_SIZE; i++ )
+        reg[i].reg_data = ipmmu_ctx_read_root(domain, reg[i].reg_offset);
+}
+
+static void ipmmu_domain_restore_context(struct ipmmu_vmsa_domain *domain)
+{
+    struct ipmmu_vmsa_device *mmu = domain->mmu->root;
+    struct hw_register *reg = mmu->reg_backup[domain->context_id];
+    unsigned int i;
+
+    dev_dbg(mmu->dev, "Handle domain context %u restore\n", domain->context_id);
+
+    for ( i = 0; i < HW_REGISTER_BACKUP_SIZE; i++ )
+    {
+        if ( reg[i].reg_offset != IMCTR )
+            ipmmu_ctx_write_root(domain, reg[i].reg_offset, reg[i].reg_data);
+        else
+            ipmmu_ctx_write_all(domain, reg[i].reg_offset,
+                                reg[i].reg_data | IMCTR_FLUSH);
+    }
+}
+
+/*
+ * Xen: Unlike Linux implementation, Xen uses a single driver instance
+ * for handling all IPMMUs. There is no framework for ipmmu_suspend/resume
+ * callbacks to be invoked for each IPMMU device. So, we need to iterate
+ * through all registered IPMMUs performing required actions.
+ *
+ * Also take care of restoring special settings, such as translation
+ * table format, etc.
+ */
+static int __must_check ipmmu_suspend(void)
+{
+    struct ipmmu_vmsa_device *mmu;
+
+    if ( !iommu_enabled )
+        return 0;
+
+    printk(XENLOG_DEBUG "ipmmu: Suspending ...\n");
+
+    spin_lock(&ipmmu_devices_lock);
+
+    list_for_each_entry( mmu, &ipmmu_devices, list )
+    {
+        if ( ipmmu_is_root(mmu) )
+        {
+            unsigned int i;
+
+            for ( i = 0; i < mmu->num_ctx; i++ )
+            {
+                if ( !mmu->domains[i] )
+                    continue;
+                ipmmu_domain_backup_context(mmu->domains[i]);
+            }
+        }
+        else
+            ipmmu_utlbs_backup(mmu);
+    }
+
+    spin_unlock(&ipmmu_devices_lock);
+
+    return 0;
+}
+
+static void ipmmu_resume(void)
+{
+    struct ipmmu_vmsa_device *mmu;
+
+    if ( !iommu_enabled )
+        return;
+
+    printk(XENLOG_DEBUG "ipmmu: Resuming ...\n");
+
+    spin_lock(&ipmmu_devices_lock);
+
+    list_for_each_entry( mmu, &ipmmu_devices, list )
+    {
+        uint32_t reg;
+
+        /* Do not use security group function */
+        reg = IMSCTLR + mmu->features->control_offset_base;
+        ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) & ~IMSCTLR_USE_SECGRP);
+
+        if ( ipmmu_is_root(mmu) )
+        {
+            unsigned int i;
+
+            /* Use stage 2 translation table format */
+            reg = IMSAUXCTLR + mmu->features->control_offset_base;
+            ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) | IMSAUXCTLR_S2PTE);
+
+            for ( i = 0; i < mmu->num_ctx; i++ )
+            {
+                if ( !mmu->domains[i] )
+                    continue;
+                ipmmu_domain_restore_context(mmu->domains[i]);
+            }
+        }
+        else
+            ipmmu_utlbs_restore(mmu);
+    }
+
+    spin_unlock(&ipmmu_devices_lock);
+}
+
+static int ipmmu_alloc_ctx_suspend(struct device *dev)
+{
+    struct ipmmu_vmsa_backup *backup_data;
+    unsigned int *utlbs_val, *asids_val;
+    struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+
+    utlbs_val = xzalloc_array(unsigned int, fwspec->num_ids);
+    if ( !utlbs_val )
+        return -ENOMEM;
+
+    asids_val = xzalloc_array(unsigned int, fwspec->num_ids);
+    if ( !asids_val )
+    {
+        xfree(utlbs_val);
+        return -ENOMEM;
+    }
+
+    backup_data = xzalloc(struct ipmmu_vmsa_backup);
+    if ( !backup_data )
+    {
+        xfree(utlbs_val);
+        xfree(asids_val);
+        return -ENOMEM;
+    }
+
+    backup_data->dev = dev;
+    backup_data->utlbs_val = utlbs_val;
+    backup_data->asids_val = asids_val;
+
+    spin_lock(&ipmmu_devices_backup_lock);
+    list_add(&backup_data->list, &ipmmu_devices_backup);
+    spin_unlock(&ipmmu_devices_backup_lock);
+
+    return 0;
+}
+
+#endif /* CONFIG_SYSTEM_SUSPEND */
+
 static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
 {
     uint64_t ttbr;
@@ -546,6 +797,9 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
         return ret;
 
     domain->context_id = ret;
+#ifdef CONFIG_SYSTEM_SUSPEND
+    domain->mmu->root->reg_backup[ret] = root_pgtable[ret];
+#endif
 
     /*
      * TTBR0
@@ -602,6 +856,9 @@ static void ipmmu_domain_destroy_context(struct ipmmu_vmsa_domain *domain)
     ipmmu_ctx_write_root(domain, IMCTR, IMCTR_FLUSH);
     ipmmu_tlb_sync(domain);
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+    domain->mmu->root->reg_backup[domain->context_id] = NULL;
+#endif
     ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
 }
 
@@ -1307,6 +1564,14 @@ static int ipmmu_add_device(u8 devfn, struct device *dev)
     /* Let Xen know that the master device is protected by an IOMMU. */
     dt_device_set_protected(dev_to_dt(dev));
 
+#ifdef CONFIG_SYSTEM_SUSPEND
+    if ( ipmmu_alloc_ctx_suspend(dev) )
+    {
+        dev_err(dev, "Failed to allocate context for suspend\n");
+        return -ENOMEM;
+    }
+#endif
+
     dev_info(dev, "Added master device (IPMMU %s micro-TLBs %u)\n",
              dev_name(fwspec->iommu_dev), fwspec->num_ids);
 
@@ -1372,6 +1637,10 @@ static const struct iommu_ops ipmmu_iommu_ops =
     .unmap_page      = arm_iommu_unmap_page,
     .dt_xlate        = ipmmu_dt_xlate,
     .add_device      = ipmmu_add_device,
+#ifdef CONFIG_SYSTEM_SUSPEND
+    .suspend         = ipmmu_suspend,
+    .resume          = ipmmu_resume,
+#endif
 };
 
 static __init int ipmmu_init(struct dt_device_node *node, const void *data)
-- 
2.48.1



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MIME-Version: 1.0
Date: Mon, 11 Aug 2025 23:14:31 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, Stefano Stabellini
 , Julien Grall , Bertrand Marquis
 , Michal Orzel , Volodymyr
 Babchuk , Andrew Cooper
 
Subject: Re: [PATCH] misra: comment default case in single-clause switch
In-Reply-To: <1d3c5364b726e42a8c38c396f2e20efc52790f62.1754933752.git.dmytro_prokopchuk1@epam.com>
References: <1d3c5364b726e42a8c38c396f2e20efc52790f62.1754933752.git.dmytro_prokopchuk1@epam.com>
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On 2025-08-11 19:36, Dmytro Prokopchuk1 wrote:
> MISRA Rule 16.4: Every switch statement shall have a default label. The
> default clause must contain either a statement or a comment prior to 
> its
> terminating break statement.
> 
> This change adds comments in default cases in single-clause switches to
> avoid violations of the rule where the `default` clause lacks a 
> suitable
> comment or statement.
> 

If you want to go this way then at least this config wants dropping:

-doc_begin="A switch statement with a single switch clause and no 
default label may be used in place of an equivalent if statement if it 
is considered to improve readability."
-config=MC3A2.R16.4,switch_clauses+={deliberate,"switch(1)&&default(0)"}
-doc_end

and probably this one too (haven't checked):

-doc_begin="A switch statement with a single switch clause and no 
default label may be used in place of an equivalent if statement if it 
is considered to improve readability."
-config=MC3A2.R16.6,switch_clauses+={deliberate, "default(0)"}
-doc_end

In the end it's a tradeoff; placing a comment with a suitable 
argumentation might be strictly better than simply tagging the tool 
report, at least from a developer's perspective. From a MISRA compliance 
standpoint in my opinion both are fine. Let's see what the maintainers 
think.

> Signed-off-by: Dmytro Prokopchuk 
> ---
>  xen/arch/arm/cpuerrata.c | 5 +++++
>  xen/arch/arm/gic.c       | 6 ++++++
>  xen/arch/arm/mmu/p2m.c   | 6 ++++++
>  xen/arch/arm/time.c      | 6 ++++++
>  xen/common/kexec.c       | 6 ++++++
>  5 files changed, 29 insertions(+)
> 
> diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
> index 17cf134f1b..e31c72694b 100644
> --- a/xen/arch/arm/cpuerrata.c
> +++ b/xen/arch/arm/cpuerrata.c
> @@ -735,6 +735,11 @@ static int cpu_errata_callback(struct 
> notifier_block *nfb,
>          rc = enable_nonboot_cpu_caps(arm_errata);
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not 
> require handling here.
> +         * The single CPU_STARTING action in the switch is sufficient 
> because this function
> +         * specifically handles enabling errata workarounds during CPU 
> startup.
> +         */
>          break;
>      }
> 
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index e80fe0ca24..dfbb0dfe08 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -436,6 +436,12 @@ static int cpu_gic_callback(struct notifier_block 
> *nfb,
>          release_irq(gic_hw_ops->info->maintenance_irq, NULL);
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not 
> require handling here.
> +         * The CPU_DYING action specifically handles releasing 
> resources acquired by
> +         * init_maintenance_interrupt(), when the CPU is being taken 
> offline. Other CPU
> +         * actions do not require GIC-specific handling.
> +         */
>          break;
>      }
> 
> diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c
> index 51abf3504f..d1f0ae0226 100644
> --- a/xen/arch/arm/mmu/p2m.c
> +++ b/xen/arch/arm/mmu/p2m.c
> @@ -1828,6 +1828,12 @@ static int cpu_virt_paging_callback(struct 
> notifier_block *nfb,
>          setup_virt_paging_one(NULL);
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not 
> require handling here.
> +         * The CPU_STARTING action is specifically handled because 
> this function sets up
> +         * virtual paging for CPUs, particularly for non-boot CPUs 
> during hotplug. Other
> +         * actions do not involve virtual paging setup.
> +         */
>          break;
>      }
> 
> diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
> index e74d30d258..4776110d97 100644
> --- a/xen/arch/arm/time.c
> +++ b/xen/arch/arm/time.c
> @@ -382,6 +382,12 @@ static int cpu_time_callback(struct notifier_block 
> *nfb,
>          deinit_timer_interrupt();
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not 
> require handling here.
> +         * The CPU_DYING action is specifically handled to revert 
> actions done in
> +         * init_timer_interrupt() and properly disable timer 
> interrupts on the CPU being
> +         * taken offline. Other actions do not involve timer 
> deinitialization.
> +         */
>          break;
>      }
> 
> diff --git a/xen/common/kexec.c b/xen/common/kexec.c
> index 84fe8c3597..0f78087a4a 100644
> --- a/xen/common/kexec.c
> +++ b/xen/common/kexec.c
> @@ -549,6 +549,12 @@ static int cf_check cpu_callback(
>          kexec_init_cpu_notes(cpu);
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not 
> require handling here.
> +         * The CPU_UP_PREPARE action is specifically handled to 
> allocate crash note buffers
> +         * for a newly onlined CPU. Other actions do not pertain to 
> crash note allocation
> +         * or memory preservation for kexec.
> +         */
>          break;
>      }
>      return NOTIFY_DONE;

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Mon, 11 Aug 2025 22:21:59 +0100
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Subject: Re: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
Content-Language: en-GB
To: Dmytro Prokopchuk1 ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: <7cd71ed21383c189fedb3250ddde54a593f7f98b.1754944131.git.dmytro_prokopchuk1@epam.com>
From: Julien Grall 
In-Reply-To: <7cd71ed21383c189fedb3250ddde54a593f7f98b.1754944131.git.dmytro_prokopchuk1@epam.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
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Hi,

On 11/08/2025 21:30, Dmytro Prokopchuk1 wrote:
> MISRA Rule 16.4: Every switch statement shall have a default label.
> The default clause must contain either a statement or a comment
> prior to its terminating break statement.
> 
> However, there is a documented rule that apply to the Xen in
> 'docs/misra/rules.rst':
> Switch statements with integer types as controlling expression
> should have a default label:
>   - if the switch is expected to handle all possible cases
>    explicitly, then a default label shall be added to handle
>    unexpected error conditions, using BUG(), ASSERT(), WARN(),
>    domain_crash(), or other appropriate methods;
 > > These changes add `ASSERT_UNREACHABLE()` macro to the default clause of
> switch statements that already explicitly handle all possible cases. This
> ensures compliance with MISRA, avoids undefined behavior in unreachable
> paths, and helps detect errors during development.
> 
> Signed-off-by: Dmytro Prokopchuk 
> ---
>   xen/arch/arm/decode.c      |  3 +++
>   xen/arch/arm/guest_walk.c  |  4 ++++
>   xen/common/grant_table.c   | 10 ++++++++--
>   xen/drivers/char/console.c |  3 +++
>   4 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c
> index 2537dbebc1..cb64137b3b 100644
> --- a/xen/arch/arm/decode.c
> +++ b/xen/arch/arm/decode.c
> @@ -178,6 +178,9 @@ static int decode_thumb(register_t pc, struct hsr_dabt *dabt)
>           case 3: /* Signed byte */
>               update_dabt(dabt, reg, 0, true);
>               break;
> +        default:
> +            ASSERT_UNREACHABLE();
> +            break;

I am not sure about this one. Can't the compiler or even ECLAIR detect 
that the value we match "opB & 3" and the 4 different values are handled?

 >           }>
>           break;
> diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c
> index 09fe486598..9199a29602 100644
> --- a/xen/arch/arm/guest_walk.c
> +++ b/xen/arch/arm/guest_walk.c
> @@ -167,6 +167,10 @@ static bool guest_walk_sd(const struct vcpu *v,
>               *perms |= GV2M_EXEC;
>   
>           break;
> +
> +        default:
> +            ASSERT_UNREACHABLE();
> +            break;
>       }
>   
>       return true;
> diff --git a/xen/common/grant_table.c b/xen/common/grant_table.c
> index cf131c43a1..60fc47f0c8 100644
> --- a/xen/common/grant_table.c
> +++ b/xen/common/grant_table.c
> @@ -330,9 +330,12 @@ shared_entry_header(struct grant_table *t, grant_ref_t ref)
>           /* Returned values should be independent of speculative execution */
>           block_speculation();
>           return &shared_entry_v2(t, ref).hdr;
> +
> +    default:
> +        ASSERT_UNREACHABLE();
> +        break;
>       }
>   
> -    ASSERT_UNREACHABLE();
 >       block_speculation();>
>       return NULL;

I know you are trying to apply the MISRA rule. But this is odd that you 
move the ASSERT_UNREACHABLE() but then code after is still only 
reachable from the default. In fact, this is introducing a risk if 
someone decides to add a new case but then forgot to return a value.

By moving the two other lines, the compiler should be able to throw an 
error if you forgot a return.


> @@ -727,10 +730,13 @@ static unsigned int nr_grant_entries(struct grant_table *gt)
>           /* Make sure we return a value independently of speculative execution */
>           block_speculation();
>           return f2e(nr_grant_frames(gt), 2);
> +
> +    default:
> +        ASSERT_UNREACHABLE();
> +        break;
>   #undef f2e
>       }
>   
> -    ASSERT_UNREACHABLE();
>       block_speculation();
>   
>       return 0;

Same remark here.

> diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c
> index 9bd5b4825d..608616f2af 100644
> --- a/xen/drivers/char/console.c
> +++ b/xen/drivers/char/console.c
> @@ -889,6 +889,9 @@ static int cf_check parse_console_timestamps(const char *s)
>           opt_con_timestamp_mode = TSM_DATE;
>           con_timestamp_mode_upd(param_2_parfs(parse_console_timestamps));
>           return 0;
> +    default:
> +        ASSERT_UNREACHABLE();

Looking at the implementation of parse_bool() it can return -1 if the 
input provided is incorrect. So I don't think this path should contain 
ASSERT_UNREACHABLE(). In fact, it should follow this directive:

"
        - if the switch is expected to handle a subset of all possible
          cases, then an empty default label shall be added with an
          in-code comment on top of the default label with a reason and
          when possible a more detailed explanation. Example::

              default:
                  /* Notifier pattern */
                  break;
"

Cheers,

-- 
Julien Grall



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MIME-Version: 1.0
Date: Mon, 11 Aug 2025 23:25:37 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, Stefano Stabellini
 , Julien Grall , Bertrand Marquis
 , Michal Orzel , Volodymyr
 Babchuk , Andrew Cooper
 , Anthony PERARD , Jan
 Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
Subject: Re: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
In-Reply-To: <7cd71ed21383c189fedb3250ddde54a593f7f98b.1754944131.git.dmytro_prokopchuk1@epam.com>
References: <7cd71ed21383c189fedb3250ddde54a593f7f98b.1754944131.git.dmytro_prokopchuk1@epam.com>
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On 2025-08-11 22:30, Dmytro Prokopchuk1 wrote:
> MISRA Rule 16.4: Every switch statement shall have a default label.
> The default clause must contain either a statement or a comment
> prior to its terminating break statement.
> 
> However, there is a documented rule that apply to the Xen in
> 'docs/misra/rules.rst':
> Switch statements with integer types as controlling expression
> should have a default label:
>  - if the switch is expected to handle all possible cases
>   explicitly, then a default label shall be added to handle
>   unexpected error conditions, using BUG(), ASSERT(), WARN(),
>   domain_crash(), or other appropriate methods;
> 
> These changes add `ASSERT_UNREACHABLE()` macro to the default clause of
> switch statements that already explicitly handle all possible cases. 
> This
> ensures compliance with MISRA, avoids undefined behavior in unreachable
> paths, and helps detect errors during development.
> 
> Signed-off-by: Dmytro Prokopchuk 
> ---
>  xen/arch/arm/decode.c      |  3 +++
>  xen/arch/arm/guest_walk.c  |  4 ++++
>  xen/common/grant_table.c   | 10 ++++++++--
>  xen/drivers/char/console.c |  3 +++
>  4 files changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/decode.c b/xen/arch/arm/decode.c
> index 2537dbebc1..cb64137b3b 100644
> --- a/xen/arch/arm/decode.c
> +++ b/xen/arch/arm/decode.c
> @@ -178,6 +178,9 @@ static int decode_thumb(register_t pc, struct 
> hsr_dabt *dabt)
>          case 3: /* Signed byte */
>              update_dabt(dabt, reg, 0, true);
>              break;
> +        default:
> +            ASSERT_UNREACHABLE();
> +            break;
>          }
> 

I think this is fine, and there should be no problems with the break 
being unreachable in some configs due to the call property for 
ASSERT_UNREACHABLE

-doc_begin="Calls to function `__builtin_unreachable()' in the expansion 
of macro
`ASSERT_UNREACHABLE()' are not considered to have the `noreturn' 
property."
-call_properties+={"name(__builtin_unreachable)&&stmt(begin(any_exp(macro(name(ASSERT_UNREACHABLE)))))", 
{"noreturn(false)"}}
-doc_end


>          break;
> diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c
> index 09fe486598..9199a29602 100644
> --- a/xen/arch/arm/guest_walk.c
> +++ b/xen/arch/arm/guest_walk.c
> @@ -167,6 +167,10 @@ static bool guest_walk_sd(const struct vcpu *v,
>              *perms |= GV2M_EXEC;
> 
>          break;
> +
> +        default:
> +            ASSERT_UNREACHABLE();
> +            break;
>      }
> 

This one instead, besides being indented misleadingly IMO, should 
instead be on an enum instead of

/*
  * First level translation table descriptor types used by the AArch32
  * short-descriptor translation table format.
  */
#define L1DESC_INVALID                      (0)
#define L1DESC_PAGE_TABLE                   (1)
#define L1DESC_SECTION                      (2)
#define L1DESC_SECTION_PXN                  (3)

so that

-doc_begin="Switch statements having a controlling expression of enum 
type deliberately do not have a default case: gcc -Wall enables -Wswitch 
which warns (and breaks the build as we use -Werror) if one of the enum 
labels is missing from the switch."
-config=MC3A2.R16.4,reports+={deliberate,'any_area(kind(context)&&^.* 
has no 
`default.*$&&stmt(node(switch_stmt)&&child(cond,skip(__non_syntactic_paren_stmts,type(canonical(enum_underlying_type(any())))))))'}
-doc_end

applies. What do you think?

>      return true;
> diff --git a/xen/common/grant_table.c b/xen/common/grant_table.c
> index cf131c43a1..60fc47f0c8 100644
> --- a/xen/common/grant_table.c
> +++ b/xen/common/grant_table.c
> @@ -330,9 +330,12 @@ shared_entry_header(struct grant_table *t, 
> grant_ref_t ref)
>          /* Returned values should be independent of speculative 
> execution */
>          block_speculation();
>          return &shared_entry_v2(t, ref).hdr;
> +
> +    default:
> +        ASSERT_UNREACHABLE();
> +        break;
>      }
> 
> -    ASSERT_UNREACHABLE();
>      block_speculation();
> 

This is ok I think, same as (1).

>      return NULL;
> @@ -727,10 +730,13 @@ static unsigned int nr_grant_entries(struct 
> grant_table *gt)
>          /* Make sure we return a value independently of speculative 
> execution */
>          block_speculation();
>          return f2e(nr_grant_frames(gt), 2);
> +
> +    default:
> +        ASSERT_UNREACHABLE();
> +        break;
>  #undef f2e
>      }
> 
> -    ASSERT_UNREACHABLE();
>      block_speculation();
> 

Same here.

>      return 0;
> diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c
> index 9bd5b4825d..608616f2af 100644
> --- a/xen/drivers/char/console.c
> +++ b/xen/drivers/char/console.c
> @@ -889,6 +889,9 @@ static int cf_check parse_console_timestamps(const 
> char *s)
>          opt_con_timestamp_mode = TSM_DATE;
>          
> con_timestamp_mode_upd(param_2_parfs(parse_console_timestamps));
>          return 0;
> +    default:
> +        ASSERT_UNREACHABLE();
> +        break;
>      }
>      if ( *s == '\0' || /* Compat for old booleanparam() */
>           !strcmp(s, "date") )

And here as well.

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Mon, 11 Aug 2025 14:38:14 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Ayan Kumar Halder 
cc: xen-devel@lists.xenproject.org, sstabellini@kernel.org, 
    michal.orzel@amd.com
Subject: Re: [ImageBuilder] Add config option to use separate load commands
 for Xen, DOM0 and DOMU binaries
In-Reply-To: <20250806123352.15852-1-ayan.kumar.halder@amd.com>
Message-ID: 
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On Wed, 6 Aug 2025, Ayan Kumar Halder wrote:
> Introduce the following options :-
> 1. XEN_LOAD - This specifies command to load xen hypervisor binary and device
> tree.
> 2. DOM0_LOAD - This specifies command to load Dom0 binaries.
> 3. DOMU_LOAD[] - This specifies command to load DomU binaries.
> 
> There can be situations where Xen, Dom0 and DomU binaries are stored in
> different partitions. Thus, imagebuilder should provide a way the binaries
> using different commands.
> 
> If any of the above options are not specified, LOAD_CMD is used by default.
> 
> Signed-off-by: Ayan Kumar Halder 

The patch is correct and the new config options look good. Two things.

The following check should be removed or, better, modified to account
for the new options:

    if test ! "$LOAD_CMD"
    then
        echo "LOAD_CMD not set, either specify it in the config or set it with the -t option"
        exit 1
    fi

Thanks to this patch, it shouldn't be necessary to specify LOAD_CMD any
longer.

find_root_dev and fit are the only two remaining users of LOAD_CMD.
While I think it makes sense to keep LOAD_CMD for fit, find_root_dev
should probably use DOM0_LOAD instead.

This incremental change (untested) should work. What do you think?



diff --git a/scripts/uboot-script-gen b/scripts/uboot-script-gen
index 9e97944..867876f 100755
--- a/scripts/uboot-script-gen
+++ b/scripts/uboot-script-gen
@@ -824,10 +824,10 @@ function check_compressed_file_type()
 
 function find_root_dev()
 {
-
-    local dev=${LOAD_CMD%:*}
+    local load_cmd=$1
+    local dev=${load_cmd%:*}
     dev=${dev##* }
-    local par=${LOAD_CMD#*:}
+    local par=${load_cmd#*:}
 
     if [ -z "$dev" ] || [ -z "$par" ]
     then
@@ -838,10 +838,10 @@ function find_root_dev()
 
     par=$((par + 1))
 
-    if [[ $LOAD_CMD =~ mmc ]]
+    if [[ $load_cmd =~ mmc ]]
     then
         root_dev="/dev/mmcblk${dev}p${par}"
-    elif [[ $LOAD_CMD =~ scsi ]]
+    elif [[ $load_cmd =~ scsi ]]
     then
         # converts number to a scsi device character
         dev=$((dev + 97))
@@ -912,7 +912,7 @@ function xen_config()
         then
             DOM0_CMD="$DOM0_CMD root=/dev/ram0"
         else
-            find_root_dev
+            find_root_dev "$DOM0_LOAD"
             # $root_dev is set by find_root_dev
             DOM0_CMD="$DOM0_CMD root=$root_dev"
         fi
@@ -960,7 +960,7 @@ function linux_config()
         then
             LINUX_CMD="$LINUX_CMD root=/dev/ram0"
         else
-            find_root_dev
+            find_root_dev "$LOAD_CMD"
             # $root_dev is set by find_root_dev
             LINUX_CMD="$LINUX_CMD root=$root_dev"
         fi
@@ -990,10 +990,6 @@ generate_uboot_images()
 
 xen_file_loading()
 {
-    if test -z "$DOM0_LOAD"
-    then
-        DOM0_LOAD="$LOAD_CMD"
-    fi
     if test "$DOM0_KERNEL"
     then
         check_compressed_file_type $DOM0_KERNEL "executable\|uImage"
@@ -1065,11 +1061,6 @@ xen_file_loading()
         generate_uboot_images
     fi
 
-    if test -z "${XEN_LOAD}"
-    then
-        XEN_LOAD="$LOAD_CMD"
-    fi
-
     kernel_addr=$memaddr
     kernel_path=$XEN
     load_file "$XEN" "host_kernel" "$XEN_LOAD"
@@ -1518,12 +1509,22 @@ then
     FIT="${UBOOT_SOURCE%.source}.fit"
 fi
 
-if test ! "$LOAD_CMD"
+if test ! "$LOAD_CMD" && ! test "$XEN_LOAD"
 then
     echo "LOAD_CMD not set, either specify it in the config or set it with the -t option"
     exit 1
 fi
 
+if test -z "$DOM0_LOAD"
+then
+    DOM0_LOAD="$LOAD_CMD"
+fi
+
+if test -z "${XEN_LOAD}"
+then
+    XEN_LOAD="$LOAD_CMD"
+fi
+
 if test ! "$BOOT_CMD"
 then
     BOOT_CMD="booti"


From xen-devel-bounces@lists.xenproject.org Mon Aug 11 21:53:51 2025
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Date: Mon, 11 Aug 2025 22:53:39 +0100
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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v5 00/12] Add initial Xen Suspend-to-RAM support on ARM64
Content-Language: en-GB
To: Mykola Kvach , xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: 
From: Julien Grall 
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Hi Mykola,

On 11/08/2025 21:47, Mykola Kvach wrote:
> From: Mykola Kvach 
> 
> This is part 2 of version 5 of the ARM Xen system suspend/resume patch
> series, based on earlier work by Mirela Simonovic and Mykyta Poturai.

Thanks for adding support for Suspend-to-RAM. You mention this is part 
2, can you clarify what's the state of part 1? Is this already merged?

If not, then can you add a link in the cover letter? This would be 
helpful to know the review ordering.

Cheers,

-- 
Julien Grall



From xen-devel-bounces@lists.xenproject.org Mon Aug 11 22:22:44 2025
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Date: Mon, 11 Aug 2025 23:22:31 +0100
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Subject: Re: [PATCH] BCM2711 reboot fix
Content-Language: en-GB
To: evgeny@contentwise.tech
Cc: xen-devel@lists.xenproject.org,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Volodymyr Babchuk , miro@contentwise.tech
References: <1754252178882.7.40484@webmail-backend-production-957f95bc8-4zxxx>
From: Julien Grall 
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Hi Evgeny,

(Top-posting because this is related to the process)

Thank you for sending a new version of the patch. I am having trouble to 
apply this patch properly using "b4". It seems to add more content in 
the git log. E.g.:

     Message-ID: 
<0057d145ddd90c01922636205484088c02a0e45a.1748380800.git.megabotva@gmail.com>
     From: Evgeny Beysembaev 
     Date: Tue, 27 May 2025 13:48:31 +0200
     Subject: [PATCH] BCM2711 reboot fix

Looking at the content of the e-mail in more details, I see you posted 
the new version as a reply to the previous patch. So it contains some
part of the previous answer. Patches submission should be on their own 
email (ideally in a new thread) with the subject contain the tag [PATCH 
v] where  is the revision ID (in your case it should be two).


On 03/08/2025 21:16, Evgeny Beysembaev wrote:
> According to the commit b334c1afad17 ("ARM: dts: bcm2711: Use proper 
> compatible in PM/Watchdog node")
> in Linux kernel, the `compatible` string for the watchdog peripheral in 
> the DTS has been modified from
> `brcm,bcm2835-pm` to `brcm,bcm2711-pm`, which caused 
> `rpi4_map_watchdog()` function to fail,
> leading to inability to reboot the system under Xen hypervisor.

On my e-mail client, the lines will be wrapped. But when applied, you 
have some lines well over 72 characters. Please re-wrapped the commit 
message.

For more details how to submit a patch, I would suggest to read:

https://wiki.xenproject.org/wiki/Submitting_Xen_Project_Patches

Patch diff itself looks good to me.

Cheers,

-- 
Julien Grall



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Date: Mon, 11 Aug 2025 16:13:50 -0700 (PDT)
From: Stefano Stabellini 
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To: Ayan Kumar Halder 
cc: xen-devel@lists.xenproject.org, sstabellini@kernel.org, 
    michal.orzel@amd.com, andrei.cherechesu@nxp.com, dmukhin@ford.com
Subject: Re: [ImageBuilder] Make DEVICE_TREE optional parameter
In-Reply-To: <20250807154614.456654-1-ayan.kumar.halder@amd.com>
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On Thu, 7 Aug 2025, Ayan Kumar Halder wrote:
> There are systems where device tree binary is passed by the U-Boot as
> $fdtcontroladdr. In such cases, no external device tree binary is provided
> during uboot script generation.
> 
> This is an enhancement on top of the following commit:-
> uboot-script-gen: Dynamically compute addr and size when loading bina…
> 
> When DEVICE_TREE is not present, $CALC is set as the addresses and sizes should
> be computed dynamically from U-Boot.

I would prefer if we did not automatically enable $CALC. If it doesn't
work without $CALC enabled, we could add a check for it and print an
error and exit. I would prefer that then enabling $CALC silently.

Also I don't think we should use the check ${DEVICE_TREE+x}. I'd prefer
to stick with the existing checks based on test ${DEVICE_TREE}.

The rest looks OK.

It might be possible to simplify this patch down to this (untested).
The last chunk of the diff is actually an unrelated fix, it looks like
we didn't test BOOT_CMD="none" when the -s option was introduced.

What do you think?


diff --git a/scripts/uboot-script-gen b/scripts/uboot-script-gen
index 9e97944..67e0f9a 100755
--- a/scripts/uboot-script-gen
+++ b/scripts/uboot-script-gen
@@ -1646,6 +1646,15 @@ if test "$FIT"
 then
     echo 'fit_addr=$fileaddr' >>  $UBOOT_SOURCE
 fi
+if test -z "$DEVICE_TREE"
+then
+    if test -z "$CALC"
+    then
+       echo "DEVICE_TREE is unset and -s is not specified"
+       exit 1
+    fi
+    echo "setenv host_fdt_addr \${fdtcontroladdr}" >> $UBOOT_SOURCE
+fi
 
 memaddr=$(( $MEMORY_START + $offset ))
 # 12582912 is 0xc00000, 12MB
@@ -1689,9 +1698,12 @@ then
     done
 fi
 
-check_file_type $DEVICE_TREE "Device Tree Blob"
-device_tree_addr=$memaddr
-load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
+if test "$DEVICE_TREE"
+then
+    check_file_type $DEVICE_TREE "Device Tree Blob"
+    device_tree_addr=$memaddr
+    load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
+fi
 bitstream_load_and_config  # bitstream is loaded last but used first
 device_tree_editing $device_tree_addr
 
@@ -1719,8 +1731,11 @@ then
     fi
 else
     # skip boot command but store load addresses to be used later
-    echo "setenv host_kernel_addr $kernel_addr" >> $UBOOT_SOURCE
-    echo "setenv host_fdt_addr $device_tree_addr" >> $UBOOT_SOURCE
+    if test -z "$CALC"
+    then
+        echo "setenv host_kernel_addr $kernel_addr" >> $UBOOT_SOURCE
+        echo "setenv host_fdt_addr $device_tree_addr" >> $UBOOT_SOURCE
+    fi
 fi
 
 if test "$FIT"
--8323329-146452198-1754953035=:2883419--


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To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall , xen-devel@lists.xenproject.org
Subject: Re: [PATCH v15 1/4] xen/domain: unify domain ID allocation
Message-ID: 
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References: <20250809170747.1836880-1-dmukhin@ford.com> <20250809170747.1836880-2-dmukhin@ford.com> 
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On Mon, Aug 11, 2025 at 01:14:49PM +0200, Jan Beulich wrote:
> On 09.08.2025 19:08, dmkhn@proton.me wrote:
> > --- /dev/null
> > +++ b/xen/common/domid.c
> > @@ -0,0 +1,95 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Domain ID allocator.
> > + *
> > + * Covers dom0 or late hwdom, predefined domains, post-boot domains.
> > + * Excludes system domains (ID >=3D DOMID_FIRST_RESERVED).
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#include 
> > +
> > +static DEFINE_SPINLOCK(domid_lock);
> > +static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED);
> > +
> > +/*
> > + * Allocate domain ID.
> > + *
> > + * @param domid Domain ID hint:
> > + * - If an explicit domain ID is provided, verify its availability and=
 use it
> > + *   if ID is not used;
> > + * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] =
range,
> > + *   starting from the last used ID. Implementation guarantees that tw=
o
> > + *   consecutive calls will never return the same ID. ID#0 is reserved=
 for
> > + *   the first boot domain (currently, dom0) and excluded from the all=
ocation
> > + *   range.
> > + * @return Valid domain ID in case of successful allocation,
> > + *         DOMID_INVALID - otherwise.
> > + */
> > +domid_t domid_alloc(domid_t domid)
> > +{
> > +    static domid_t domid_last;
> > +
> > +    spin_lock(&domid_lock);
> > +
> > +    /* Exact match. */
> > +    if ( domid < DOMID_FIRST_RESERVED )
> > +    {
> > +        if ( __test_and_set_bit(domid, domid_bitmap) )
> > +            domid =3D DOMID_INVALID;
> > +    }
> > +    /*
> > +     * Exhaustive search.
> > +     *
> > +     * Domain ID#0 is reserved for the first boot domain (e.g. control=
 domain)
> > +     * and excluded from allocation.
> > +     */
> > +    else
> > +    {
> > +        domid_t num =3D DOMID_FIRST_RESERVED;
> > +
> > +        domid =3D find_next_zero_bit(domid_bitmap, num, domid_last + 1=
);
> > +        if ( domid =3D=3D num && domid_last !=3D 0 )
>=20
> I'm pretty sure I commented on this before, yet then maybe it was in the =
context
> of another patch: Using =3D=3D here isn't sufficient; it needs to be >=3D=
. See e.g.
> cpumask_next().

I've missed that one. Will fix, thank you.

>=20
> Jan



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Date: Mon, 11 Aug 2025 23:47:56 +0000
To: Alejandro Vallejo 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall , Xen-devel 
Subject: Re: [PATCH v15 1/4] xen/domain: unify domain ID allocation
Message-ID: 
In-Reply-To: 
References: <20250809170747.1836880-1-dmukhin@ford.com> <20250809170747.1836880-2-dmukhin@ford.com> 
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On Mon, Aug 11, 2025 at 01:00:00PM +0200, Alejandro Vallejo wrote:
> On Sat Aug 9, 2025 at 7:08 PM CEST, dmkhn wrote:
> > From: Denis Mukhin 
> >
> > Currently, there are two different domain ID allocation implementations=
:
> >
> >   1) Sequential IDs allocation in dom0less Arm code based on max_init_d=
omid;
> >
> >   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
> >      max_init_domid (both Arm and x86).
> >
> > The domain ID allocation covers dom0 or late hwdom, predefined domains,
> > post-boot domains, excluding Xen system domains (domid >=3D
> > DOMID_FIRST_RESERVED).
> >
> > It makes sense to have a common helper code for such task across archit=
ectures
> > (Arm and x86) and between dom0less / toolstack domU allocation.
> >
> > Note, fixing dependency on max_init_domid is out of scope of this patch=
.
> >
> > Wrap the domain ID allocation as an arch-independent function domid_all=
oc() in
> > new common/domid.c based on the bitmap.
> >
> > Allocation algorithm:
> > - If an explicit domain ID is provided, verify its availability and use=
 it if
> >   ID is not used;
> > - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERV=
ED-1],
> >   starting from the last used ID.
> >   Implementation guarantees that two consecutive calls will never retur=
n the
> >   same ID. ID#0 is reserved for the first boot domain (currently, dom0)=
 and
> >   excluded from the allocation range.
> >
> > Remove is_free_domid() helper as it is not needed now.
> >
> > No functional change intended.
> >
> > Signed-off-by: Denis Mukhin 
> > Reviewed-by: Julien Grall 
>=20
> There's a nit below about a change in v14, but with or without that:
>=20
>   Reviewed-by: Alejandro Vallejo 

Thanks

>=20
> > ---
> > Changes since v14:
> > - added Julien's R-b
> > ---
> >  xen/arch/arm/domain_build.c             |  7 +-
> >  xen/arch/x86/setup.c                    |  7 +-
> >  xen/common/Makefile                     |  1 +
> >  xen/common/device-tree/dom0less-build.c | 15 ++--
> >  xen/common/domain.c                     |  2 +
> >  xen/common/domctl.c                     | 43 ++---------
> >  xen/common/domid.c                      | 95 +++++++++++++++++++++++++
> >  xen/include/xen/domain.h                |  3 +
> >  8 files changed, 126 insertions(+), 47 deletions(-)
> >  create mode 100644 xen/common/domid.c
> >
> > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> > index 463ae4474d30..789f2b9d3ce7 100644
> > --- a/xen/arch/arm/domain_build.c
> > +++ b/xen/arch/arm/domain_build.c
> > @@ -2050,6 +2050,7 @@ void __init create_dom0(void)
> >          .grant_opts =3D XEN_DOMCTL_GRANT_version(opt_gnttab_max_versio=
n),
> >      };
> >      unsigned int flags =3D CDF_privileged | CDF_hardware;
> > +    domid_t domid;
> >      int rc;
> >
> >      /* The vGIC for DOM0 is exactly emulating the hardware GIC */
> > @@ -2074,7 +2075,11 @@ void __init create_dom0(void)
> >      if ( !llc_coloring_enabled )
> >          flags |=3D CDF_directmap;
> >
> > -    dom0 =3D domain_create(0, &dom0_cfg, flags);
> > +    domid =3D domid_alloc(0);
> > +    if ( domid =3D=3D DOMID_INVALID )
> > +        panic("Error allocating domain ID 0\n");
> > +
> > +    dom0 =3D domain_create(domid, &dom0_cfg, flags);
> >      if ( IS_ERR(dom0) )
> >          panic("Error creating domain 0 (rc =3D %ld)\n", PTR_ERR(dom0))=
;
> >
> > diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
> > index 1543dd251cc6..398da734c0c5 100644
> > --- a/xen/arch/x86/setup.c
> > +++ b/xen/arch/x86/setup.c
> > @@ -1047,8 +1047,11 @@ static struct domain *__init create_dom0(struct =
boot_info *bi)
> >      if ( iommu_enabled )
> >          dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu;
> >
> > -    /* Create initial domain.  Not d0 for pvshim. */
> > -    bd->domid =3D get_initial_domain_id();
> > +    /* Allocate initial domain ID.  Not d0 for pvshim. */
> > +    bd->domid =3D domid_alloc(get_initial_domain_id());
> > +    if ( bd->domid =3D=3D DOMID_INVALID )
> > +        panic("Error allocating domain ID %u\n", get_initial_domain_id=
());
> > +
> >      d =3D domain_create(bd->domid, &dom0_cfg,
> >                        pv_shim ? 0 : CDF_privileged | CDF_hardware);
> >      if ( IS_ERR(d) )
> > diff --git a/xen/common/Makefile b/xen/common/Makefile
> > index c316957fcb36..0c7d0f5d46e1 100644
> > --- a/xen/common/Makefile
> > +++ b/xen/common/Makefile
> > @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) +=3D d=
evice.o
> >  obj-$(CONFIG_DEVICE_TREE_PARSE) +=3D device-tree/
> >  obj-$(CONFIG_IOREQ_SERVER) +=3D dm.o
> >  obj-y +=3D domain.o
> > +obj-y +=3D domid.o
> >  obj-y +=3D event_2l.o
> >  obj-y +=3D event_channel.o
> >  obj-$(CONFIG_EVTCHN_FIFO) +=3D event_fifo.o
> > diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/devic=
e-tree/dom0less-build.c
> > index 6bb038111de9..f4b6b515d2d2 100644
> > --- a/xen/common/device-tree/dom0less-build.c
> > +++ b/xen/common/device-tree/dom0less-build.c
> > @@ -833,6 +833,7 @@ void __init create_domUs(void)
> >      {
> >          struct kernel_info ki =3D KERNEL_INFO_INIT;
> >          int rc =3D parse_dom0less_node(node, &ki.bd);
> > +        domid_t domid;
> >
> >          if ( rc =3D=3D -ENOENT )
> >              continue;
> > @@ -842,13 +843,13 @@ void __init create_domUs(void)
> >          if ( (max_init_domid + 1) >=3D DOMID_FIRST_RESERVED )
> >              panic("No more domain IDs available\n");
> >
> > -        /*
> > -         * The variable max_init_domid is initialized with zero, so he=
re it's
> > -         * very important to use the pre-increment operator to call
> > -         * domain_create() with a domid > 0. (domid =3D=3D 0 is reserv=
ed for Dom0)
> > -         */
> > -        ki.bd.d =3D domain_create(++max_init_domid,
> > -                                &ki.bd.create_cfg, ki.bd.create_flags)=
;
> > +        domid =3D domid_alloc(DOMID_INVALID);
> > +        if ( domid =3D=3D DOMID_INVALID )
> > +            panic("Error allocating ID for domain %s\n", dt_node_name(=
node));
> > +
> > +        max_init_domid =3D max(max_init_domid, domid);
> > +
> > +        ki.bd.d =3D domain_create(domid, &ki.bd.create_cfg, ki.bd.crea=
te_flags);
> >          if ( IS_ERR(ki.bd.d) )
> >              panic("Error creating domain %s (rc =3D %ld)\n",
> >                    dt_node_name(node), PTR_ERR(ki.bd.d));
> > diff --git a/xen/common/domain.c b/xen/common/domain.c
> > index 5241a1629eeb..a7e303253d1a 100644
> > --- a/xen/common/domain.c
> > +++ b/xen/common/domain.c
> > @@ -692,6 +692,8 @@ static void _domain_destroy(struct domain *d)
> >
> >      lock_profile_deregister_struct(LOCKPROF_TYPE_PERDOM, d);
> >
> > +    domid_free(d->domain_id);
> > +
> >      free_domain_struct(d);
> >  }
> >
> > diff --git a/xen/common/domctl.c b/xen/common/domctl.c
> > index f2a7caaf853c..71e712c1f316 100644
> > --- a/xen/common/domctl.c
> > +++ b/xen/common/domctl.c
> > @@ -51,20 +51,6 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nod=
emask,
> >                                     MAX_NUMNODES);
> >  }
> >
> > -static inline int is_free_domid(domid_t dom)
> > -{
> > -    struct domain *d;
> > -
> > -    if ( dom >=3D DOMID_FIRST_RESERVED )
> > -        return 0;
> > -
> > -    if ( (d =3D rcu_lock_domain_by_id(dom)) =3D=3D NULL )
> > -        return 1;
> > -
> > -    rcu_unlock_domain(d);
> > -    return 0;
> > -}
> > -
> >  void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *=
info)
> >  {
> >      struct vcpu *v;
> > @@ -423,36 +409,19 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_=
t) u_domctl)
> >
> >      case XEN_DOMCTL_createdomain:
> >      {
> > -        domid_t        dom;
> > -        static domid_t rover =3D 0;
> > +        /* NB: ID#0 is reserved, find the first suitable ID instead. *=
/
> > +        domid_t domid =3D domid_alloc(op->domain ?: DOMID_INVALID);
> >
> > -        dom =3D op->domain;
> > -        if ( (dom > 0) && (dom < DOMID_FIRST_RESERVED) )
> > +        if ( domid =3D=3D DOMID_INVALID )
> >          {
> >              ret =3D -EEXIST;
> > -            if ( !is_free_domid(dom) )
> > -                break;
> > -        }
> > -        else
> > -        {
> > -            for ( dom =3D rover + 1; dom !=3D rover; dom++ )
> > -            {
> > -                if ( dom =3D=3D DOMID_FIRST_RESERVED )
> > -                    dom =3D 1;
> > -                if ( is_free_domid(dom) )
> > -                    break;
> > -            }
> > -
> > -            ret =3D -ENOMEM;
> > -            if ( dom =3D=3D rover )
> > -                break;
> > -
> > -            rover =3D dom;
> > +            break;
> >          }
> >
> > -        d =3D domain_create(dom, &op->u.createdomain, false);
> > +        d =3D domain_create(domid, &op->u.createdomain, false);
> >          if ( IS_ERR(d) )
> >          {
> > +            domid_free(domid);
> >              ret =3D PTR_ERR(d);
> >              d =3D NULL;
> >              break;
> > diff --git a/xen/common/domid.c b/xen/common/domid.c
> > new file mode 100644
> > index 000000000000..7839a2885810
> > --- /dev/null
> > +++ b/xen/common/domid.c
> > @@ -0,0 +1,95 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Domain ID allocator.
> > + *
> > + * Covers dom0 or late hwdom, predefined domains, post-boot domains.
> > + * Excludes system domains (ID >=3D DOMID_FIRST_RESERVED).
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#include 
> > +
> > +static DEFINE_SPINLOCK(domid_lock);
> > +static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED);
> > +
> > +/*
> > + * Allocate domain ID.
> > + *
> > + * @param domid Domain ID hint:
> > + * - If an explicit domain ID is provided, verify its availability and=
 use it
> > + *   if ID is not used;
> > + * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] =
range,
> > + *   starting from the last used ID. Implementation guarantees that tw=
o
> > + *   consecutive calls will never return the same ID. ID#0 is reserved=
 for
> > + *   the first boot domain (currently, dom0) and excluded from the all=
ocation
> > + *   range.
> > + * @return Valid domain ID in case of successful allocation,
> > + *         DOMID_INVALID - otherwise.
> > + */
> > +domid_t domid_alloc(domid_t domid)
> > +{
> > +    static domid_t domid_last;
> > +
> > +    spin_lock(&domid_lock);
> > +
> > +    /* Exact match. */
> > +    if ( domid < DOMID_FIRST_RESERVED )
> > +    {
> > +        if ( __test_and_set_bit(domid, domid_bitmap) )
> > +            domid =3D DOMID_INVALID;
> > +    }
> > +    /*
> > +     * Exhaustive search.
> > +     *
> > +     * Domain ID#0 is reserved for the first boot domain (e.g. control=
 domain)
> > +     * and excluded from allocation.
> > +     */
> > +    else
> > +    {
> > +        domid_t num =3D DOMID_FIRST_RESERVED;
>=20
> nit: s/num/bound/, or something like that.
>=20
> I don't care much though. If there's not going to be a v16 (and I hope no=
t. The
> series has been girdling the mailing list long enough) feel free to ignor=
e this.

Will address.

>=20
> > +
> > +        domid =3D find_next_zero_bit(domid_bitmap, , domid_last + 1);
> > +        if ( domid =3D=3D num && domid_last !=3D 0 )
> > +        {
> > +            num =3D domid_last + 1;
> > +            domid =3D find_next_zero_bit(domid_bitmap, num, 1);
> > +        }
> > +
> > +        ASSERT(domid <=3D DOMID_FIRST_RESERVED);
> > +        if ( domid < num )
> > +        {
> > +            __set_bit(domid, domid_bitmap);
> > +            domid_last =3D domid;
> > +        }
> > +        else
> > +            domid =3D DOMID_INVALID;
> > +    }
> > +
> > +    spin_unlock(&domid_lock);
> > +
> > +    return domid;
> > +}
> > +
> > +void domid_free(domid_t domid)
> > +{
> > +    int rc;
> > +
> > +    ASSERT(domid <=3D DOMID_FIRST_RESERVED);
> > +
> > +    spin_lock(&domid_lock);
> > +    rc =3D __test_and_clear_bit(domid, domid_bitmap);
> > +    spin_unlock(&domid_lock);
> > +
> > +    ASSERT(rc);
> > +}
> > +
> > +/*
> > + * Local variables:
> > + * mode: C
> > + * c-file-style: "BSD"
> > + * c-basic-offset: 4
> > + * tab-width: 4
> > + * indent-tabs-mode: nil
> > + * End:
> > + */
> > diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
> > index e10baf2615fd..8aab05ae93c8 100644
> > --- a/xen/include/xen/domain.h
> > +++ b/xen/include/xen/domain.h
> > @@ -38,6 +38,9 @@ void arch_get_domain_info(const struct domain *d,
> >
> >  domid_t get_initial_domain_id(void);
> >
> > +domid_t domid_alloc(domid_t domid);
> > +void domid_free(domid_t domid);
> > +
> >  /* CDF_* constant. Internal flags for domain creation. */
> >  /* Is this a privileged domain? */
> >  #define CDF_privileged           (1U << 0)
>=20



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Date: Mon, 11 Aug 2025 23:53:13 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall , xen-devel@lists.xenproject.org
Subject: Re: [PATCH v15 3/4] tools/tests: introduce unit tests for domain ID allocator
Message-ID: 
In-Reply-To: <0089146c-fe86-42b5-afa7-72dffb08c3b7@suse.com>
References: <20250809170747.1836880-1-dmukhin@ford.com> <20250809170747.1836880-4-dmukhin@ford.com> <0089146c-fe86-42b5-afa7-72dffb08c3b7@suse.com>
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On Mon, Aug 11, 2025 at 09:58:24AM +0200, Jan Beulich wrote:
> On 09.08.2025 19:08, dmkhn@proton.me wrote:
> > diff --git a/tools/tests/domid/include/xen/domain.h b/tools/tests/domid=
/include/xen/domain.h
> > new file mode 120000
> > index 000000000000..2eda9aed088e
> > --- /dev/null
> > +++ b/tools/tests/domid/include/xen/domain.h
> > @@ -0,0 +1 @@
> > +../../harness.h
> > \ No newline at end of file
>=20
> In the tests we generally generate symlinks as necessary, rather than hav=
ing them be
> present in git. Furthermore it's not quite clear why a file of this name =
is needed
> in a test harness anyway. Elsewhere we adjust hypervisor sources to make =
respective
> #include-s conditional.

I'll fix the makefile for the test so dependencies are resolved on the fly
and no need for code adjustment.

>=20
> Jan



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Date: Mon, 11 Aug 2025 23:55:56 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators
Message-ID: 
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References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-3-dmukhin@ford.com>   <6953603b-8c3f-4f12-9f5e-45cb553fe8cc@suse.com>
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On Mon, Aug 11, 2025 at 09:34:58AM +0200, Jan Beulich wrote:
> On 09.08.2025 20:55, dmkhn@proton.me wrote:
> > On Mon, Aug 04, 2025 at 12:11:03PM +0200, Jan Beulich wrote:
> >> On 31.07.2025 21:21, dmkhn@proton.me wrote:
> >>> --- a/xen/common/Kconfig
> >>> +++ b/xen/common/Kconfig
> >>> @@ -1,6 +1,8 @@
> >>>
> >>>  menu "Common Features"
> >>>
> >>> +source "common/emul/Kconfig"
> >>> +
> >>>  config COMPAT
> >>
> >> Why at the very top?
> >
> > I did not find a better place, since the settings are not sorted and to=
 me it
> > makes sense to list emulation capabilities first...
> >
> > Where would be the best location for that submenu?
> > Close to another submenu `source "common/sched/Kconfig"`?
>=20
> At least below there. Possibly yet further down.
>=20
> >>> +int vuart_init(struct domain *d, struct vuart_params *params)
> >>> +{
> >>> +    const struct vuart_ops *vdev;
> >>> +    int rc;
> >>> +
> >>> +    if ( !domain_has_vuart(d) )
> >>> +        return 0;
> >>> +
> >>> +    for_each_vuart(vdev)
> >>> +    {
> >>> +        rc =3D vdev->init(d, params);
> >>> +        if ( rc )
> >>> +            return rc;
> >>> +    }
> >>> +
> >>> +    d->console.input_allowed =3D true;
> >>
> >> Unconditionally?
> >
> > Thanks.
> > That should be a least under rc =3D=3D 0.
>=20
> You only ever make it there with rc =3D=3D 0, though. (In fact that varia=
ble's
> scope would better be just the loop body.)
>=20
> >>> +/*
> >>> + * Put character to the first suitable emulated UART's FIFO.
> >>> + */
> >>
> >> What's "suitable"? Along the lines of the earlier remark, what if the =
domain
> >> has vUART kind A configured, ...
> >
> > "suitable" is meant to be the first emulator with put_rx !=3D NULL.
> > I will update that.
>=20
> Except that, as iirc Roger also pointed out, "first emulator with put_rx =
!=3D NULL"
> is a questionable condition.
>=20
> >>> --- a/xen/common/keyhandler.c
> >>> +++ b/xen/common/keyhandler.c
> >>> @@ -22,6 +22,7 @@
> >>>  #include 
> >>>  #include 
> >>>  #include 
> >>> +#include 
> >>>  #include 
> >>>
> >>>  static unsigned char keypress_key;
> >>> @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char k=
ey)
> >>>                             v->periodic_period / 1000000);
> >>>              }
> >>>          }
> >>> +
> >>> +        vuart_dump_state(d);
> >>
> >> How verbose is this going to get?
> >
> > Looks something like this:
> > ```
> > (XEN) [   88.334893] 'q' pressed -> dumping domain info (now =3D 883348=
28303)
> > [..]
> > (XEN) [   88.335673] Virtual ns16550 (COM2) I/O port 0x02f8 IRQ#3 owner=
 d0
> > (XEN) [   88.335681]   RX FIFO size 1024 in_prod 258 in_cons 258 used 0
> > (XEN) [   88.335689]   TX FIFO size 2048 out_prod 15 out_cons 0 used 15
> > (XEN) [   88.335696]   00 RBR 02 THR 6f DLL 01 DLM 00
> > (XEN) [   88.335703]   01 IER 05
> > (XEN) [   88.335709]   02 FCR 81 IIR c1
> > (XEN) [   88.335715]   03 LCR 13
> > (XEN) [   88.335720]   04 MCR 0b
> > (XEN) [   88.335726]   05 LSR 60
> > (XEN) [   88.335731]   06 MSR b0
> > (XEN) [   88.335736]   07 SCR 00
> >
> > ```
>=20
> Definitely too much (for my taste) to put under 'q'.

I'll try to limit the number of printed lines; register dump can be made
compact for sure.

>=20
> Jan



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Date: Tue, 12 Aug 2025 00:06:36 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 5/8] emul/vuart-ns16550: introduce NS16550-compatible UART emulator (x86)
Message-ID: 
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References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-6-dmukhin@ford.com> <5c0589a2-91fe-484d-bded-5a68a1626355@suse.com>  <32cd30fb-190c-44f0-824f-1c4583635250@suse.com>
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On Mon, Aug 11, 2025 at 09:39:42AM +0200, Jan Beulich wrote:
> On 09.08.2025 20:37, dmkhn@proton.me wrote:
> > On Mon, Aug 04, 2025 at 12:53:36PM +0200, Jan Beulich wrote:
> >> On 31.07.2025 21:22, dmkhn@proton.me wrote:
> >>> --- a/xen/common/emul/vuart/Makefile
> >>> +++ b/xen/common/emul/vuart/Makefile
> >>> @@ -1 +1,2 @@
> >>>  obj-$(CONFIG_HAS_VUART) +=3D vuart.o
> >>> +obj-$(CONFIG_VUART_NS16550) +=3D vuart-ns16550.o
> >>
> >> I don't think files in this directory need a vuart- name prefix.
> >
> > Ack.
> >
> > Hmm, there's already ns16550.c which is UART driver, so it may be confu=
sing to
> > have two ns16550s (although in different directories).
> >
> > I do not have a strong preference on the naming here.
>=20
> We have several examples of files with the same name in distinct director=
ies.
> As an aside - is it really only 16550-s that you emulate? Otherwise the n=
ame
> may want to be e.g. ns16x50.c or ns8250.c.

I'll use ns16x50.c.

>=20
> Jan



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On 7/23/25 09:39, Jan Beulich wrote:
> Use the more "modern" form, thus doing away with effectively open-coding
> xmalloc_array() at the same time. While there is a difference in
> generated code, as xmalloc_bytes() forces SMP_CACHE_BYTES alignment, if
> code really cared about such higher than default alignment, it should
> request so explicitly.

While I don't object to the change itself, I think this description is a 
bit over simplification of the change. If the allocation is under 
PAGE_SIZE, then they are equivalent, but if it is over the page size 
there are a few more differences than just cache alignment. It 
completely changes the underlying allocator. I personally also find it a 
bit of a stretch to call xmalloc_bytes(size) an open coded version of 
xmalloc_array(char, size).

> Signed-off-by: Jan Beulich 
> ---
> v3: Use xv[mz]alloc_array().
> 
> --- a/xen/common/efi/runtime.c
> +++ b/xen/common/efi/runtime.c
> @@ -6,6 +6,7 @@
>   #include 
>   #include 
>   #include 
> +#include 
>   
>   DEFINE_XEN_GUEST_HANDLE(CHAR16);
>   
> @@ -500,23 +501,23 @@ int efi_runtime_call(struct xenpf_efi_ru
>           len = gwstrlen(guest_handle_cast(op->u.get_variable.name, CHAR16));
>           if ( len < 0 )
>               return len;
> -        name = xmalloc_array(CHAR16, ++len);
> +        name = xvmalloc_array(CHAR16, ++len);
>           if ( !name )
>              return -ENOMEM;
>           if ( __copy_from_guest(name, op->u.get_variable.name, len) ||
>                wmemchr(name, 0, len) != name + len - 1 )
>           {
> -            xfree(name);
> +            xvfree(name);
>               return -EIO;
>           }
>   
>           size = op->u.get_variable.size;
>           if ( size )
>           {
> -            data = xmalloc_bytes(size);
> +            data = xvmalloc_array(unsigned char, size);
>               if ( !data )
>               {
> -                xfree(name);
> +                xvfree(name);
>                   return -ENOMEM;
>               }
>           }
> @@ -539,8 +540,8 @@ int efi_runtime_call(struct xenpf_efi_ru
>           else
>               rc = -EOPNOTSUPP;
>   
> -        xfree(data);
> -        xfree(name);
> +        xvfree(data);
> +        xvfree(name);
>       }
>       break;
>   
> @@ -553,17 +554,17 @@ int efi_runtime_call(struct xenpf_efi_ru
>           len = gwstrlen(guest_handle_cast(op->u.set_variable.name, CHAR16));
>           if ( len < 0 )
>               return len;
> -        name = xmalloc_array(CHAR16, ++len);
> +        name = xvmalloc_array(CHAR16, ++len);
>           if ( !name )
>              return -ENOMEM;
>           if ( __copy_from_guest(name, op->u.set_variable.name, len) ||
>                wmemchr(name, 0, len) != name + len - 1 )
>           {
> -            xfree(name);
> +            xvfree(name);
>               return -EIO;
>           }
>   
> -        data = xmalloc_bytes(op->u.set_variable.size);
> +        data = xvmalloc_array(unsigned char, op->u.set_variable.size);
>           if ( !data )
>               rc = -ENOMEM;
>           else if ( copy_from_guest(data, op->u.set_variable.data,
> @@ -581,8 +582,8 @@ int efi_runtime_call(struct xenpf_efi_ru
>               efi_rs_leave(&state);
>           }
>   
> -        xfree(data);
> -        xfree(name);
> +        xvfree(data);
> +        xvfree(name);
>       }
>       break;
>   
> @@ -598,13 +599,13 @@ int efi_runtime_call(struct xenpf_efi_ru
>               return -EINVAL;
>   
>           size = op->u.get_next_variable_name.size;
> -        name.raw = xzalloc_bytes(size);
> +        name.raw = xvzalloc_array(unsigned char, size);
>           if ( !name.raw )
>               return -ENOMEM;
>           if ( copy_from_guest(name.raw, op->u.get_next_variable_name.name,
>                                size) )
>           {
> -            xfree(name.raw);
> +            xvfree(name.raw);
>               return -EFAULT;
>           }
>   
> @@ -629,7 +630,7 @@ int efi_runtime_call(struct xenpf_efi_ru
>           else
>               rc = -EOPNOTSUPP;
>   
> -        xfree(name.raw);
> +        xvfree(name.raw);
>       }
>       break;
>   

With a stronger description of the change,

Acked-by: Daniel P. Smith 


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Date: Mon, 11 Aug 2025 20:21:34 -0400
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Subject: Re: [PATCH 1/2] efi: Call FreePages only if needed
Content-Language: en-US
To: Ross Lagerwall ,
 Xen-devel , xen-devel@lists.xenproject.org
Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , Jan Beulich 
References: <20250805163204.3631483-1-ross.lagerwall@citrix.com>
 <20250805163204.3631483-2-ross.lagerwall@citrix.com>
From: "Daniel P. Smith" 
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On 8/5/25 12:32, Ross Lagerwall wrote:
> If the config file is builtin, cfg.addr will be zero but Xen
> unconditionally calls FreePages() on the address.
> 
> Xen may also call FreePages() with a zero address if blexit() is called
> after this point since cfg.need_to_free is not set to false.
> 
> The UEFI specification does not say whether calling FreePages() with a
> zero address is allowed so let's be cautious and use cfg.need_to_free
> properly.
> 
> Signed-off-by: Ross Lagerwall 
> ---
>   xen/common/efi/boot.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
> index 778a39cc48e6..50ff1d1bd225 100644
> --- a/xen/common/efi/boot.c
> +++ b/xen/common/efi/boot.c
> @@ -1534,8 +1534,11 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE ImageHandle,
>   
>           efi_arch_cfg_file_late(loaded_image, dir_handle, section.s);
>   
> -        efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
> -        cfg.addr = 0;
> +        if ( cfg.need_to_free )
> +        {
> +            efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
> +            cfg.need_to_free = false;
> +        }
>   
>           if ( dir_handle )
>               dir_handle->Close(dir_handle);

Acked-by Daniel P. Smith 


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Subject: Re: [PATCH 1/2] efi: Call FreePages only if needed
Content-Language: en-US
To: Ross Lagerwall ,
 Xen-devel , xen-devel@lists.xenproject.org
Cc: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , Jan Beulich 
References: <20250805163204.3631483-1-ross.lagerwall@citrix.com>
 <20250805163204.3631483-2-ross.lagerwall@citrix.com>
From: "Daniel P. Smith" 
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On 8/5/25 12:32, Ross Lagerwall wrote:
> If the config file is builtin, cfg.addr will be zero but Xen
> unconditionally calls FreePages() on the address.
> 
> Xen may also call FreePages() with a zero address if blexit() is called
> after this point since cfg.need_to_free is not set to false.
> 
> The UEFI specification does not say whether calling FreePages() with a
> zero address is allowed so let's be cautious and use cfg.need_to_free
> properly.
> 
> Signed-off-by: Ross Lagerwall 
> ---
>   xen/common/efi/boot.c | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
> index 778a39cc48e6..50ff1d1bd225 100644
> --- a/xen/common/efi/boot.c
> +++ b/xen/common/efi/boot.c
> @@ -1534,8 +1534,11 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE ImageHandle,
>   
>           efi_arch_cfg_file_late(loaded_image, dir_handle, section.s);
>   
> -        efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
> -        cfg.addr = 0;
> +        if ( cfg.need_to_free )
> +        {
> +            efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
> +            cfg.need_to_free = false;
> +        }
>   
>           if ( dir_handle )
>               dir_handle->Close(dir_handle);

Acked-by Daniel P. Smith 


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From: Mykola Kvach 
Date: Tue, 12 Aug 2025 07:58:05 +0300
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Subject: Re: [PATCH v5 00/12] Add initial Xen Suspend-to-RAM support on ARM64
To: Julien Grall 
Cc: xen-devel@lists.xenproject.org, Mykola Kvach , 
	Stefano Stabellini , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Andrew Cooper , Anthony PERARD , 
	Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
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Hi Julien,

On Tue, Aug 12, 2025 at 12:53=E2=80=AFAM Julien Grall  wrot=
e:
>
> Hi Mykola,
>
> On 11/08/2025 21:47, Mykola Kvach wrote:
> > From: Mykola Kvach 
> >
> > This is part 2 of version 5 of the ARM Xen system suspend/resume patch
> > series, based on earlier work by Mirela Simonovic and Mykyta Poturai.
>
> Thanks for adding support for Suspend-to-RAM. You mention this is part
> 2, can you clarify what's the state of part 1? Is this already merged?
>
> If not, then can you add a link in the cover letter? This would be
> helpful to know the review ordering.

Thank you for pointing this out. I missed adding the link to the
corresponding part of this patch series. Here is part 1:
https://patchew.org/Xen/cover.1754595198.git.mykola._5Fkvach@epam.com/

>
> Cheers,
>
> --
> Julien Grall
>

Best regards,
Mykola


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Date: Tue, 12 Aug 2025 12:52:59 +0800
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Subject: Re: [PATCH v3 01/11] mm/huge_memory: move more common code into
 insert_pmd()
Content-Language: en-US
To: David Hildenbrand 
Cc: linux-mm@kvack.org, xen-devel@lists.xenproject.org,
 linux-fsdevel@vger.kernel.org, nvdimm@lists.linux.dev,
 linuxppc-dev@lists.ozlabs.org, Andrew Morton ,
 Madhavan Srinivasan ,
 Michael Ellerman , Nicholas Piggin ,
 Christophe Leroy ,
 Juergen Gross , Stefano Stabellini
 ,
 Oleksandr Tyshchenko ,
 Dan Williams , Matthew Wilcox
 , Jan Kara ,
 Alexander Viro ,
 Christian Brauner ,
 Lorenzo Stoakes ,
 "Liam R. Howlett" , Vlastimil Babka
 , Mike Rapoport ,
 Suren Baghdasaryan , Michal Hocko ,
 Zi Yan , Baolin Wang ,
 Nico Pache , Ryan Roberts ,
 Dev Jain , Barry Song ,
 Jann Horn , Pedro Falcato ,
 Hugh Dickins , Oscar Salvador ,
 Alistair Popple , Wei Yang ,
 linux-kernel@vger.kernel.org
References: <20250811112631.759341-1-david@redhat.com>
 <20250811112631.759341-2-david@redhat.com>
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On 2025/8/11 19:26, David Hildenbrand wrote:
> Let's clean it all further up.
> 
> No functional change intended.
> 
> Reviewed-by: Oscar Salvador 
> Reviewed-by: Alistair Popple 
> Reviewed-by: Lorenzo Stoakes 
> Reviewed-by: Wei Yang 
> Signed-off-by: David Hildenbrand 

Nice. Feel free to add:

Reviewed-by: Lance Yang 

Thanks,
Lance

> ---
>   mm/huge_memory.c | 72 ++++++++++++++++--------------------------------
>   1 file changed, 24 insertions(+), 48 deletions(-)
> 
> diff --git a/mm/huge_memory.c b/mm/huge_memory.c
> index 2b4ea5a2ce7d2..5314a89d676f1 100644
> --- a/mm/huge_memory.c
> +++ b/mm/huge_memory.c
> @@ -1379,15 +1379,25 @@ struct folio_or_pfn {
>   	bool is_folio;
>   };
>   
> -static int insert_pmd(struct vm_area_struct *vma, unsigned long addr,
> +static vm_fault_t insert_pmd(struct vm_area_struct *vma, unsigned long addr,
>   		pmd_t *pmd, struct folio_or_pfn fop, pgprot_t prot,
> -		bool write, pgtable_t pgtable)
> +		bool write)
>   {
>   	struct mm_struct *mm = vma->vm_mm;
> +	pgtable_t pgtable = NULL;
> +	spinlock_t *ptl;
>   	pmd_t entry;
>   
> -	lockdep_assert_held(pmd_lockptr(mm, pmd));
> +	if (addr < vma->vm_start || addr >= vma->vm_end)
> +		return VM_FAULT_SIGBUS;
>   
> +	if (arch_needs_pgtable_deposit()) {
> +		pgtable = pte_alloc_one(vma->vm_mm);
> +		if (!pgtable)
> +			return VM_FAULT_OOM;
> +	}
> +
> +	ptl = pmd_lock(mm, pmd);
>   	if (!pmd_none(*pmd)) {
>   		const unsigned long pfn = fop.is_folio ? folio_pfn(fop.folio) :
>   					  fop.pfn;
> @@ -1395,15 +1405,14 @@ static int insert_pmd(struct vm_area_struct *vma, unsigned long addr,
>   		if (write) {
>   			if (pmd_pfn(*pmd) != pfn) {
>   				WARN_ON_ONCE(!is_huge_zero_pmd(*pmd));
> -				return -EEXIST;
> +				goto out_unlock;
>   			}
>   			entry = pmd_mkyoung(*pmd);
>   			entry = maybe_pmd_mkwrite(pmd_mkdirty(entry), vma);
>   			if (pmdp_set_access_flags(vma, addr, pmd, entry, 1))
>   				update_mmu_cache_pmd(vma, addr, pmd);
>   		}
> -
> -		return -EEXIST;
> +		goto out_unlock;
>   	}
>   
>   	if (fop.is_folio) {
> @@ -1424,11 +1433,17 @@ static int insert_pmd(struct vm_area_struct *vma, unsigned long addr,
>   	if (pgtable) {
>   		pgtable_trans_huge_deposit(mm, pmd, pgtable);
>   		mm_inc_nr_ptes(mm);
> +		pgtable = NULL;
>   	}
>   
>   	set_pmd_at(mm, addr, pmd, entry);
>   	update_mmu_cache_pmd(vma, addr, pmd);
> -	return 0;
> +
> +out_unlock:
> +	spin_unlock(ptl);
> +	if (pgtable)
> +		pte_free(mm, pgtable);
> +	return VM_FAULT_NOPAGE;
>   }
>   
>   /**
> @@ -1450,9 +1465,6 @@ vm_fault_t vmf_insert_pfn_pmd(struct vm_fault *vmf, unsigned long pfn,
>   	struct folio_or_pfn fop = {
>   		.pfn = pfn,
>   	};
> -	pgtable_t pgtable = NULL;
> -	spinlock_t *ptl;
> -	int error;
>   
>   	/*
>   	 * If we had pmd_special, we could avoid all these restrictions,
> @@ -1464,25 +1476,9 @@ vm_fault_t vmf_insert_pfn_pmd(struct vm_fault *vmf, unsigned long pfn,
>   						(VM_PFNMAP|VM_MIXEDMAP));
>   	BUG_ON((vma->vm_flags & VM_PFNMAP) && is_cow_mapping(vma->vm_flags));
>   
> -	if (addr < vma->vm_start || addr >= vma->vm_end)
> -		return VM_FAULT_SIGBUS;
> -
> -	if (arch_needs_pgtable_deposit()) {
> -		pgtable = pte_alloc_one(vma->vm_mm);
> -		if (!pgtable)
> -			return VM_FAULT_OOM;
> -	}
> -
>   	pfnmap_setup_cachemode_pfn(pfn, &pgprot);
>   
> -	ptl = pmd_lock(vma->vm_mm, vmf->pmd);
> -	error = insert_pmd(vma, addr, vmf->pmd, fop, pgprot, write,
> -			   pgtable);
> -	spin_unlock(ptl);
> -	if (error && pgtable)
> -		pte_free(vma->vm_mm, pgtable);
> -
> -	return VM_FAULT_NOPAGE;
> +	return insert_pmd(vma, addr, vmf->pmd, fop, pgprot, write);
>   }
>   EXPORT_SYMBOL_GPL(vmf_insert_pfn_pmd);
>   
> @@ -1491,35 +1487,15 @@ vm_fault_t vmf_insert_folio_pmd(struct vm_fault *vmf, struct folio *folio,
>   {
>   	struct vm_area_struct *vma = vmf->vma;
>   	unsigned long addr = vmf->address & PMD_MASK;
> -	struct mm_struct *mm = vma->vm_mm;
>   	struct folio_or_pfn fop = {
>   		.folio = folio,
>   		.is_folio = true,
>   	};
> -	spinlock_t *ptl;
> -	pgtable_t pgtable = NULL;
> -	int error;
> -
> -	if (addr < vma->vm_start || addr >= vma->vm_end)
> -		return VM_FAULT_SIGBUS;
>   
>   	if (WARN_ON_ONCE(folio_order(folio) != PMD_ORDER))
>   		return VM_FAULT_SIGBUS;
>   
> -	if (arch_needs_pgtable_deposit()) {
> -		pgtable = pte_alloc_one(vma->vm_mm);
> -		if (!pgtable)
> -			return VM_FAULT_OOM;
> -	}
> -
> -	ptl = pmd_lock(mm, vmf->pmd);
> -	error = insert_pmd(vma, addr, vmf->pmd, fop, vma->vm_page_prot,
> -			   write, pgtable);
> -	spin_unlock(ptl);
> -	if (error && pgtable)
> -		pte_free(mm, pgtable);
> -
> -	return VM_FAULT_NOPAGE;
> +	return insert_pmd(vma, addr, vmf->pmd, fop, vma->vm_page_prot, write);
>   }
>   EXPORT_SYMBOL_GPL(vmf_insert_folio_pmd);
>   



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Message-ID: <755dd957-514b-4316-82f5-3619c19cbb15@suse.com>
Date: Tue, 12 Aug 2025 08:12:39 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3] EFI/runtime: switch to xv[mz]alloc_array()
To: "Daniel P. Smith" 
Cc: Marek Marczykowski ,
 "xen-devel@lists.xenproject.org" 
References: <41b7e14c-59ef-40f5-8c43-69bdc5fb4531@suse.com>
 <761b584a-51fb-403d-948e-3366501cea50@apertussolutions.com>
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On 12.08.2025 02:19, Daniel P. Smith wrote:
> On 7/23/25 09:39, Jan Beulich wrote:
>> Use the more "modern" form, thus doing away with effectively open-coding
>> xmalloc_array() at the same time. While there is a difference in
>> generated code, as xmalloc_bytes() forces SMP_CACHE_BYTES alignment, if
>> code really cared about such higher than default alignment, it should
>> request so explicitly.
> 
> While I don't object to the change itself, I think this description is a 
> bit over simplification of the change. If the allocation is under 
> PAGE_SIZE, then they are equivalent, but if it is over the page size 
> there are a few more differences than just cache alignment. It 
> completely changes the underlying allocator. I personally also find it a 
> bit of a stretch to call xmalloc_bytes(size) an open coded version of 
> xmalloc_array(char, size).

My take is that xmalloc_bytes() should never have existed. Hence why I
didn't add xzmalloc_bytes() when introducing that family of interfaces.

> With a stronger description of the change,

So what exactly do you mean by "stronger"? I can add that in the unlikely
event that one of the allocations is (near) PAGE_SIZE or larger, we now
wouldn't require contiguous memory anymore. Yet based on your comment at
the top I'm not quite sure if that's what you're after and/or enough to
satisfy your request.

> Acked-by: Daniel P. Smith 

Thanks, but will need clarification first as per above.

Jan


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Subject: Re: [PATCH] Arm: drop assertion from page_is_ram_type()
To: Julien Grall 
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On 11.08.2025 19:24, Julien Grall wrote:
> On 11/08/2025 14:01, Jan Beulich wrote:
>> Its uses in offline_page() and query_page_offline() make it reachable on
>> Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
>> code added. It being reachable was even mentioned in the commit
>> introducing it, claiming it "clearly shouldn't be called on ARM just
>> yet".
> 
> So I agree that the function can be reached. But then I don't think the 
> function can simply return 0.
> 
> The name is too generic enough that someone may end up to use it in 
> common code and there will be no signal to the user that the function 
> will not properly indicate a RAM page on Arm.
> 
> I can think of two possible approaches:
> 
> 1/ Implement properly page_is_ram_type(). We don't have an e820, but we 
> could mimick it using the memory banks we stored.
> 2/ Rename page_is_ram_type() to page_offlinable() (or similar) so it is 
> clear that the common use is for offlining.
> 
> The latter might be the simplest.

I consider page_offlinable() potentially ambiguous: When you offline a PCI
device, you offline its MMIO as well, for example. Or, much like RAM, some
page in, say, a video device's framebuffer may have gone bad. One might
think that such would then also be covered by that function. So minimally
page_offlinable_ram() or page_is_offlinable_ram(), I think. That would
then have the benefit of allowing an avenue towards x86 also making its
checking more precise, as certain RAM ranges can't possibly be offlined.
If that's fine with you, I can enlarge the patch accordingly.

Jan


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Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators
To: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org,
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On 12.08.2025 01:55, dmkhn@proton.me wrote:
> On Mon, Aug 11, 2025 at 09:34:58AM +0200, Jan Beulich wrote:
>> On 09.08.2025 20:55, dmkhn@proton.me wrote:
>>> On Mon, Aug 04, 2025 at 12:11:03PM +0200, Jan Beulich wrote:
>>>> On 31.07.2025 21:21, dmkhn@proton.me wrote:
>>>>> @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char key)
>>>>>                             v->periodic_period / 1000000);
>>>>>              }
>>>>>          }
>>>>> +
>>>>> +        vuart_dump_state(d);
>>>>
>>>> How verbose is this going to get?
>>>
>>> Looks something like this:
>>> ```
>>> (XEN) [   88.334893] 'q' pressed -> dumping domain info (now = 88334828303)
>>> [..]
>>> (XEN) [   88.335673] Virtual ns16550 (COM2) I/O port 0x02f8 IRQ#3 owner d0
>>> (XEN) [   88.335681]   RX FIFO size 1024 in_prod 258 in_cons 258 used 0
>>> (XEN) [   88.335689]   TX FIFO size 2048 out_prod 15 out_cons 0 used 15
>>> (XEN) [   88.335696]   00 RBR 02 THR 6f DLL 01 DLM 00
>>> (XEN) [   88.335703]   01 IER 05
>>> (XEN) [   88.335709]   02 FCR 81 IIR c1
>>> (XEN) [   88.335715]   03 LCR 13
>>> (XEN) [   88.335720]   04 MCR 0b
>>> (XEN) [   88.335726]   05 LSR 60
>>> (XEN) [   88.335731]   06 MSR b0
>>> (XEN) [   88.335736]   07 SCR 00
>>>
>>> ```
>>
>> Definitely too much (for my taste) to put under 'q'.
> 
> I'll try to limit the number of printed lines; register dump can be made
> compact for sure.

Yet even then I'm inclined to say that device specific data simply doesn't
belong here.

Jan


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Subject: Re: [PATCH v5 07/12] xen/arm: Add support for system suspend
 triggered by hardware domain
To: Mykola Kvach ,
 Stefano Stabellini 
Cc: Mirela Simonovic ,
 Julien Grall , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Saeed Nowshadi ,
 Mykyta Poturai ,
 Mykola Kvach , xen-devel@lists.xenproject.org
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On 11.08.2025 22:48, Mykola Kvach wrote:
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -1311,7 +1311,11 @@ int domain_shutdown(struct domain *d, u8 reason)
>          d->shutdown_code = reason;
>      reason = d->shutdown_code;
>  
> +#if defined(CONFIG_SYSTEM_SUSPEND) && defined(CONFIG_ARM)
> +    if ( reason != SHUTDOWN_suspend && is_hardware_domain(d) )
> +#else
>      if ( is_hardware_domain(d) )
> +#endif
>          hwdom_shutdown(reason);

There better wouldn't be any #ifdef here. Afaict you can easily use
IS_ENABLED(CONFIG_SYSTEM_SUSPEND). For CONFIG_ARM, though, I think some
new abstraction will need adding. E.g. HAS_HWDOM_SUSPEND (with want for
a better, yet not overly long name).

With the hwdom / ctldom separation work in mind I wonder though if it's
really hwdom to be in charge of initiating system suspend. Imo
conceptually that rather would want to be ctldom. Stefano?

Jan


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CC: "xen-devel@lists.xenproject.org" , Stefano
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	Volodymyr Babchuk , Andrew Cooper
	
Subject: Re: [PATCH] misra: comment default case in single-clause switch
Thread-Topic: [PATCH] misra: comment default case in single-clause switch
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Subject: Re: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
To: Nicola Vetrini 
Cc: xen-devel@lists.xenproject.org,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Dmytro Prokopchuk1 
References: <7cd71ed21383c189fedb3250ddde54a593f7f98b.1754944131.git.dmytro_prokopchuk1@epam.com>
 
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On 11.08.2025 23:25, Nicola Vetrini wrote:
> On 2025-08-11 22:30, Dmytro Prokopchuk1 wrote:
>> --- a/xen/arch/arm/decode.c
>> +++ b/xen/arch/arm/decode.c
>> @@ -178,6 +178,9 @@ static int decode_thumb(register_t pc, struct 
>> hsr_dabt *dabt)
>>          case 3: /* Signed byte */
>>              update_dabt(dabt, reg, 0, true);
>>              break;
>> +        default:
>> +            ASSERT_UNREACHABLE();
>> +            break;
>>          }
>>
> 
> I think this is fine, and there should be no problems with the break 
> being unreachable in some configs due to the call property for 
> ASSERT_UNREACHABLE
> 
> -doc_begin="Calls to function `__builtin_unreachable()' in the expansion 
> of macro
> `ASSERT_UNREACHABLE()' are not considered to have the `noreturn' 
> property."
> -call_properties+={"name(__builtin_unreachable)&&stmt(begin(any_exp(macro(name(ASSERT_UNREACHABLE)))))", 
> {"noreturn(false)"}}
> -doc_end

Did you also see Julien's reply? Imo, to address a complaint from one
rule, another rule is then being violated: The "default" label itself
is unreachable here.

Jan


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Subject: Re: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
To: Julien Grall ,
 Dmytro Prokopchuk1 
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "xen-devel@lists.xenproject.org" 
References: <7cd71ed21383c189fedb3250ddde54a593f7f98b.1754944131.git.dmytro_prokopchuk1@epam.com>
 <59396fd1-ca82-4655-9dcf-ec36e0d51ffc@xen.org>
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On 11.08.2025 23:21, Julien Grall wrote:
> On 11/08/2025 21:30, Dmytro Prokopchuk1 wrote:
>> --- a/xen/common/grant_table.c
>> +++ b/xen/common/grant_table.c
>> @@ -330,9 +330,12 @@ shared_entry_header(struct grant_table *t, grant_ref_t ref)
>>           /* Returned values should be independent of speculative execution */
>>           block_speculation();
>>           return &shared_entry_v2(t, ref).hdr;
>> +
>> +    default:
>> +        ASSERT_UNREACHABLE();
>> +        break;
>>       }
>>   
>> -    ASSERT_UNREACHABLE();
>  >       block_speculation();>
>>       return NULL;
> 
> I know you are trying to apply the MISRA rule. But this is odd that you 
> move the ASSERT_UNREACHABLE() but then code after is still only 
> reachable from the default. In fact, this is introducing a risk if 
> someone decides to add a new case but then forgot to return a value.
> 
> By moving the two other lines, the compiler should be able to throw an 
> error if you forgot a return.

I think we did discuss this pattern in the past. While moving everything up
to the "return" into the default: handling will please Eclair / Misra, we'll
then end up with no return statement at the end of a non-void function.
Beyond being good practice (imo) to have such a "main" return statement,
that's actually another rule, just one we apparently didn't accept (15.5).

Jan


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Date: Tue, 12 Aug 2025 09:35:00 +0200
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Subject: Re: [PATCH] misra: comment default case in single-clause switch
To: Dmytro Prokopchuk1 ,
 Nicola Vetrini 
Cc: "xen-devel@lists.xenproject.org" ,
 Stefano Stabellini , Julien Grall ,
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 <110fc2a9-2f48-4718-995b-3295b9c7e9aa@epam.com>
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On 12.08.2025 09:19, Dmytro Prokopchuk1 wrote:
> 
> 
> On 8/12/25 00:14, Nicola Vetrini wrote:
>> On 2025-08-11 19:36, Dmytro Prokopchuk1 wrote:
>>> MISRA Rule 16.4: Every switch statement shall have a default label. The
>>> default clause must contain either a statement or a comment prior to its
>>> terminating break statement.
>>>
>>> This change adds comments in default cases in single-clause switches to
>>> avoid violations of the rule where the `default` clause lacks a suitable
>>> comment or statement.
>>>
>>
>> If you want to go this way then at least this config wants dropping:
>>
>> -doc_begin="A switch statement with a single switch clause and no 
>> default label may be used in place of an equivalent if statement if it 
>> is considered to improve readability."
>> -config=MC3A2.R16.4,switch_clauses+={deliberate,"switch(1)&&default(0)"}
>> -doc_end
>>
>> and probably this one too (haven't checked):
>>
>> -doc_begin="A switch statement with a single switch clause and no 
>> default label may be used in place of an equivalent if statement if it 
>> is considered to improve readability."
>> -config=MC3A2.R16.6,switch_clauses+={deliberate, "default(0)"}
>> -doc_end
>>
>> In the end it's a tradeoff; placing a comment with a suitable 
>> argumentation might be strictly better than simply tagging the tool 
>> report, at least from a developer's perspective. From a MISRA compliance 
>> standpoint in my opinion both are fine. Let's see what the maintainers 
>> think.
>>
> 
> According to Jan's comment here
> https://patchew.org/Xen/725ec86ac1aa883c35fb30b8f226c95cbe0934e9.1754322299.git.dmytro._5Fprokopchuk1@epam.com/
> there were discussions about placing comments inside 'default' case.

For notifier functions in particular, yes. The config quoted above covers
more than those, though, if I'm not mistaken.

Jan


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Andrew Cooper
	, Anthony PERARD ,
	"Orzel, Michal" , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v6 13/19] xen/x86: implement amd-cppc-epp driver for CPPC
 in active mode
Thread-Topic: [PATCH v6 13/19] xen/x86: implement amd-cppc-epp driver for CPPC
 in active mode
Thread-Index: AQHb8hcniovO//xAlkude/GkR6xpVbQ2WzUAgCh1DAA=
Date: Tue, 12 Aug 2025 07:40:42 +0000
Message-ID:
 
References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
 <20250711035106.2540522-14-Penny.Zheng@amd.com>
 
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Date: Tue, 12 Aug 2025 09:49:07 +0200
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Subject: Re: [PATCH] misra: comment default case in single-clause switch
To: Dmytro Prokopchuk1 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 "xen-devel@lists.xenproject.org" 
References: <1d3c5364b726e42a8c38c396f2e20efc52790f62.1754933752.git.dmytro_prokopchuk1@epam.com>
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From: Jan Beulich 
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On 11.08.2025 19:36, Dmytro Prokopchuk1 wrote:
> --- a/xen/arch/arm/cpuerrata.c
> +++ b/xen/arch/arm/cpuerrata.c
> @@ -735,6 +735,11 @@ static int cpu_errata_callback(struct notifier_block *nfb,
>          rc = enable_nonboot_cpu_caps(arm_errata);
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not require handling here.
> +         * The single CPU_STARTING action in the switch is sufficient because this function
> +         * specifically handles enabling errata workarounds during CPU startup.
> +         */
>          break;
>      }

Here and below - please obey to the 80 char line length limit set forth
by ./CODING_STYLE.

As to what the comment says: There not being a need to clean up is tied to
there not being any resources allocated during CPU_STARTING. Whether that's
the case is left unclear.

> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -436,6 +436,12 @@ static int cpu_gic_callback(struct notifier_block *nfb,
>          release_irq(gic_hw_ops->info->maintenance_irq, NULL);
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not require handling here.
> +         * The CPU_DYING action specifically handles releasing resources acquired by
> +         * init_maintenance_interrupt(), when the CPU is being taken offline. Other CPU
> +         * actions do not require GIC-specific handling.
> +         */
>          break;
>      }

I don't think this suffices. What about CPU_UP_CANCELED or
CPU_RESUME_FAILED? It may well be that in that case
init_maintenance_interrupt() would never have run, yet imo such needs
stating explicitly.

> --- a/xen/arch/arm/mmu/p2m.c
> +++ b/xen/arch/arm/mmu/p2m.c
> @@ -1828,6 +1828,12 @@ static int cpu_virt_paging_callback(struct notifier_block *nfb,
>          setup_virt_paging_one(NULL);
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not require handling here.
> +         * The CPU_STARTING action is specifically handled because this function sets up
> +         * virtual paging for CPUs, particularly for non-boot CPUs during hotplug. Other
> +         * actions do not involve virtual paging setup.
> +         */
>          break;
>      }

See cpu_errata_callback() comment.

> --- a/xen/arch/arm/time.c
> +++ b/xen/arch/arm/time.c
> @@ -382,6 +382,12 @@ static int cpu_time_callback(struct notifier_block *nfb,
>          deinit_timer_interrupt();
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not require handling here.
> +         * The CPU_DYING action is specifically handled to revert actions done in
> +         * init_timer_interrupt() and properly disable timer interrupts on the CPU being
> +         * taken offline. Other actions do not involve timer deinitialization.
> +         */
>          break;
>      }

See cpu_gic_callback() comment.

> --- a/xen/common/kexec.c
> +++ b/xen/common/kexec.c
> @@ -549,6 +549,12 @@ static int cf_check cpu_callback(
>          kexec_init_cpu_notes(cpu);
>          break;
>      default:
> +        /*
> +         * Default case left empty as other notifier actions do not require handling here.
> +         * The CPU_UP_PREPARE action is specifically handled to allocate crash note buffers
> +         * for a newly onlined CPU. Other actions do not pertain to crash note allocation
> +         * or memory preservation for kexec.
> +         */
>          break;
>      }

Yet when bringing down a CPU, these allocations are leaked. Looking at
kexec_init_cpu_notes() that appears to be intentional, but again - such needs
saying explicitly. Plus of course intentional leaks are always somewhat
questionable, so extra justification may be on order.

One further suggestion: Please consider splitting such patches at
maintainer boundaries. For the patch to go in as is, you need both Arm and
kexec approval. If you split, the part having got its approval could go in
without need to wait for the other approval to trickle in.

Jan


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On 08.08.2025 22:22, Andrew Cooper wrote:
> The name AMD chose is rather more concise.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

I'm okay with the (much) shorter name, so:
Acked-by: Jan Beulich 

But I can't make the connection to AMD: It's INTERRUPT_SST_TABLE (figure)
or INTERRUPT_SSP_TABLE (text) there, afaics. And ISST_ADDR in yet further
places.

Jan


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Subject: Re: [PATCH 02/22] x86/msr: Rename wrmsr_ns() to wrmsrns(), and take
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To: Andrew Cooper 
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References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 11.08.2025 08:36, Andrew Cooper wrote:
> On 08/08/2025 9:22 pm, Andrew Cooper wrote:
>> In hindsight, having the wrapper name not be the instruction mnemonic was a
>> poor choice.  Also, PKS turns out to be quite rare in wanting a split value.
>>
>> Switch to using a single 64bit value in preparation for new users.
>>
>> No functional change.
>>
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Jan Beulich 
>> CC: Roger Pau Monné 
>> ---
>>  xen/arch/x86/include/asm/msr.h      | 4 ++--
>>  xen/arch/x86/include/asm/prot-key.h | 4 ++--
>>  2 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
>> index 4c4f18b3a54d..b6b85b04c3fd 100644
>> --- a/xen/arch/x86/include/asm/msr.h
>> +++ b/xen/arch/x86/include/asm/msr.h
>> @@ -39,7 +39,7 @@ static inline void wrmsrl(unsigned int msr, uint64_t val)
>>  }
>>  
>>  /* Non-serialising WRMSR, when available.  Falls back to a serialising WRMSR. */
>> -static inline void wrmsr_ns(uint32_t msr, uint32_t lo, uint32_t hi)
>> +static inline void wrmsrns(uint32_t msr, uint64_t val)
>>  {
>>      /*
>>       * WRMSR is 2 bytes.  WRMSRNS is 3 bytes.  Pad WRMSR with a redundant CS
>> @@ -47,7 +47,7 @@ static inline void wrmsr_ns(uint32_t msr, uint32_t lo, uint32_t hi)
>>       */
>>      alternative_input(".byte 0x2e; wrmsr",
>>                        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
>> -                      "c" (msr), "a" (lo), "d" (hi));
>> +                      "c" (msr), "a" (val), "d" (val >> 32));
>>  }
> 
> It turns out this is the case poor code generation for MSR_STAR.
> 
> I've adjusted it to:
> 
> @@ -39,8 +39,10 @@ static inline void wrmsrl(unsigned int msr, uint64_t val)
>  }
>  
>  /* Non-serialising WRMSR, when available.  Falls back to a serialising WRMSR. */
> -static inline void wrmsr_ns(uint32_t msr, uint32_t lo, uint32_t hi)
> +static inline void wrmsrns(uint32_t msr, uint64_t val)
>  {
> +    uint32_t lo = val, hi = val >> 32;
> +
>      /*
>       * WRMSR is 2 bytes.  WRMSRNS is 3 bytes.  Pad WRMSR with a redundant CS
>       * prefix to avoid a trailing NOP.
> 
> 
> which stops the compiler from loading the high half of %rax too.

Acked-by: Jan Beulich 



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Subject: Re: [PATCH 03/22] x86/traps: Drop incorrect BUILD_BUG_ON() and
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On 08.08.2025 22:22, Andrew Cooper wrote:
> This was added erroneously by me.
> 
> Hardware task switching does demand a TSS of at least 0x67 bytes, but that's
> not relevant in 64bit, and not relevant for Xen since commit
> 5d1181a5ea5e ("xen: Remove x86_32 build target.") in 2012.
> 
> We already load a 0-length TSS in early_traps_init() demonstrating that it's
> possible.
> 
> Signed-off-by: Andrew Cooper 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
> ---
>  xen/arch/x86/cpu/common.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
> index f6ec5c9df522..cdc41248d4e9 100644
> --- a/xen/arch/x86/cpu/common.c
> +++ b/xen/arch/x86/cpu/common.c
> @@ -936,8 +936,6 @@ void load_system_tables(void)
>  		wrmsrl(MSR_ISST, (unsigned long)ist_ssp);
>  	}
>  
> -	BUILD_BUG_ON(sizeof(*tss) <= 0x67); /* Mandated by the architecture. */
> -
>  	_set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
>  			 sizeof(*tss) - 1, SYS_DESC_tss_avail);
>  	if ( IS_ENABLED(CONFIG_PV32) )

Well, the comment is wrong. Whether the BUILD_BUG_ON() itself is also wrong
depends on our intentions with the structure. Don't we need it to be that
size for everything (incl I/O bitmap) to work correctly elsewhere?

Jan


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Subject: Re: [PATCH 04/22] x86/idt: Minor improvements to
 _update_gate_addr_lower()
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On 08.08.2025 22:22, Andrew Cooper wrote:
> After some experimentation, using .a/.b makes far better logic than using the
> named fields, as both Clang and GCC spill idte to the stack when named fields
> are used.
> 
> GCC seems to do something very daft for the addr1 field.  It takes addr,
> shifts it by 32, then ANDs with 0xffff0000000000000UL, which requires
> manifesting a MOVABS.
> 
> Clang follows the C, whereby it ANDs with $imm32, then shifts, avoiding the
> MOVABS entirely.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 
albeit I have to admit that I'm not quite happy about ...

> --- a/xen/arch/x86/include/asm/idt.h
> +++ b/xen/arch/x86/include/asm/idt.h
> @@ -92,15 +92,16 @@ static inline void _set_gate_lower(idt_entry_t *gate, unsigned long type,
>   * Update the lower half handler of an IDT entry, without changing any other
>   * configuration.
>   */
> -static inline void _update_gate_addr_lower(idt_entry_t *gate, void *addr)
> +static inline void _update_gate_addr_lower(idt_entry_t *gate, void *_addr)
>  {
> +    unsigned long addr = (unsigned long)_addr;
> +    unsigned int addr1 = addr & 0xffff0000U; /* GCC force better codegen. */
>      idt_entry_t idte;
> -    idte.a = gate->a;
>  
> -    idte.b = ((unsigned long)(addr) >> 32);
> -    idte.a &= 0x0000FFFFFFFF0000ULL;
> -    idte.a |= (((unsigned long)(addr) & 0xFFFF0000UL) << 32) |
> -        ((unsigned long)(addr) & 0xFFFFUL);
> +    idte.b = addr >> 32;
> +    idte.a = gate->a & 0x0000ffffffff0000UL;
> +    idte.a |= (unsigned long)addr1 << 32;

... the cast here. Yet perhaps gcc still generates a MOVABS when you make
addr1 unsigned long?

As to the comment next to the variable declaration: Could I talk you into
adding a colon after "GCC"? Without one, the comment reads somewhat
ambiguously to me.

Jan


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Subject: Re: [PATCH 05/22] x86/traps: Rename early_traps_init() to
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On 08.08.2025 22:22, Andrew Cooper wrote:
> We're going to want to introduce an AP version shortly.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 



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Subject: Re: [PATCH 06/22] x86/traps: Introduce bsp_traps_reinit()
To: Andrew Cooper 
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On 08.08.2025 22:22, Andrew Cooper wrote:
> ... to abstract away updating the refereces to the old BSP stack.
> 
> Signed-off-by: Andrew Cooper 

If it helps later:
Acked-by: Jan Beulich 
with ..

> --- a/xen/arch/x86/traps-setup.c
> +++ b/xen/arch/x86/traps-setup.c
> @@ -107,6 +107,15 @@ void __init traps_init(void)
>      percpu_traps_init();
>  }
>  
> +/*
> + * Re-initialise all state referencing the early-boot stack.
> + */
> +void bsp_traps_reinit(void)

... __init added here.

Jan


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From: Dmytro Prokopchuk1 
To: Julien Grall , "xen-devel@lists.xenproject.org"
	
CC: Stefano Stabellini , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Andrew Cooper
	, Anthony PERARD , Jan
 Beulich , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	
Subject: Re: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
Thread-Topic: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
Thread-Index: AQHcCv7M4bE5kwDncUeSEAS4rjYqyLRd9fOAgAC4EwA=
Date: Tue, 12 Aug 2025 08:20:48 +0000
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Subject: Re: [PATCH 07/22] x86/spec-ctrl: Rework init_shadow_spec_ctrl_state()
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On 08.08.2025 22:22, Andrew Cooper wrote:
> We're going to want to reuse it for a remote stack shortly.

Are we? From the titles of subsequent patches I can't judge where that would
be, so it's hard to peek ahead. And iirc earlier on it was a concious decision
to only ever run this locally.

> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Nevertheless, trusting that you have a good reason:
Acked-by: Jan Beulich 

Jan


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Subject: Re: [PATCH 08/22] x86/traps: Introduce ap_early_traps_init() and set
 up exception handling earlier
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 08.08.2025 22:23, Andrew Cooper wrote:
> --- a/xen/arch/x86/acpi/wakeup_prot.S
> +++ b/xen/arch/x86/acpi/wakeup_prot.S
> @@ -63,6 +63,9 @@ LABEL(s3_resume)
>          pushq   %rax
>          lretq
>  1:
> +        /* Set up early exceptions and CET before entering C properly. */
> +        call    ap_early_traps_init

But this is the BSP?

> --- a/xen/arch/x86/smpboot.c
> +++ b/xen/arch/x86/smpboot.c
> @@ -327,12 +327,7 @@ void asmlinkage start_secondary(void)
>      struct cpu_info *info = get_cpu_info();
>      unsigned int cpu = smp_processor_id();
>  
> -    /* Critical region without IDT or TSS.  Any fault is deadly! */
> -
> -    set_current(idle_vcpu[cpu]);
> -    this_cpu(curr_vcpu) = idle_vcpu[cpu];
>      rdmsrl(MSR_EFER, this_cpu(efer));
> -    init_shadow_spec_ctrl_state(info);
>  
>      /*
>       * Just as during early bootstrap, it is convenient here to disable
> @@ -352,14 +347,6 @@ void asmlinkage start_secondary(void)
>       */
>      spin_debug_disable();
>  
> -    get_cpu_info()->use_pv_cr3 = false;
> -    get_cpu_info()->xen_cr3 = 0;
> -    get_cpu_info()->pv_cr3 = 0;
> -
> -    load_system_tables();
> -
> -    /* Full exception support from here on in. */
> -
>      if ( cpu_has_pks )
>          wrpkrs_and_cache(0); /* Must be before setting CR4.PKS */
>  
> @@ -1064,8 +1051,12 @@ static int cpu_smpboot_alloc(unsigned int cpu)
>              goto out;
>  
>      info = get_cpu_info_from_stack((unsigned long)stack_base[cpu]);
> +    memset(info, 0, sizeof(*info));

Why do we suddenly need this? Or is this just out of an abundance of
caution (while making the individual ->*_cr3 writes unnecessary)?

> +    init_shadow_spec_ctrl_state(info);

May I suggest to move this further down a little, at least ...

>      info->processor_id = cpu;

... past here? Just in case other values in the struct may be needed
in the function at some point.

>      info->per_cpu_offset = __per_cpu_offset[cpu];
> +    info->current_vcpu = idle_vcpu[cpu];

To be able to spot this, I think it wants /* set_current() */ or some
such.

> +    per_cpu(curr_vcpu, cpu) = idle_vcpu[cpu];

It's a little odd to do this early (and remotely), but it looks all fine
with how the variable is currently used.

Jan


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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
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To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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In-Reply-To: <20250808202314.1045968-10-andrew.cooper3@citrix.com>
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On 08.08.2025 22:23, Andrew Cooper wrote:
> Switch it to Xen coding style and fix MISRA violations.

That were all ul -> UL suffix transformations, afaics?

>  Make it static as
> there are no external caller now.
> 
> Since commit a35816b5cae8 ("x86/traps: Introduce early_traps_init() and
> simplify setup"), load_system_tables() is called later on the BSP, so the
> SYS_STATE_early_boot check can be dropped from the safety BUG_ON().
> 
> Move the BUILD_BUG_ON() into build_assertions(),

I'm not quite convinced of this move - having the related BUILD_BUG_ON()
and BUG_ON() next to each other would seem better to me. (Same would
apply to the TSS size related BUILD_BUG_ON(), if in the earlier patch
we ended up agreeing that only the comment wants dropping there.)

> @@ -139,3 +258,16 @@ void asmlinkage ap_early_traps_init(void)
>  {
>      load_system_tables();
>  }
> +
> +static void __init __maybe_unused build_assertions(void)
> +{
> +    /*
> +     * This is best-effort (it doesn't cover some padding corner cases), but
> +     * is preforable to hitting the check at boot time.

Nit: "preferable"

Jan


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Date: Tue, 12 Aug 2025 11:43:35 +0200
From: Nicola Vetrini 
To: Andrew Cooper 
Cc: Xen-devel , Jan Beulich
 , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
 traps-setup.c
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On 2025-08-08 22:23, Andrew Cooper wrote:
> Switch it to Xen coding style and fix MISRA violations.  Make it static 
> as
> there are no external caller now.
> 
> Since commit a35816b5cae8 ("x86/traps: Introduce early_traps_init() and
> simplify setup"), load_system_tables() is called later on the BSP, so 
> the
> SYS_STATE_early_boot check can be dropped from the safety BUG_ON().
> 
> Move the BUILD_BUG_ON() into build_assertions(), and introduce an
> endof_field() helper to make the expression clearer.
> 
> Swap wrmsrl(MSR_ISST, ...) for wrmsrns().  No serialisation is needed 
> at this
> point.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
> ---
>  xen/arch/x86/cpu/common.c         | 118 --------------------------
>  xen/arch/x86/include/asm/system.h |   1 -
>  xen/arch/x86/traps-setup.c        | 132 ++++++++++++++++++++++++++++++
>  xen/include/xen/macros.h          |   2 +
>  4 files changed, 134 insertions(+), 119 deletions(-)
> 
> diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
> index cdc41248d4e9..da05015578aa 100644
> --- a/xen/arch/x86/cpu/common.c
> +++ b/xen/arch/x86/cpu/common.c
> @@ -843,124 +843,6 @@ void print_cpu_info(unsigned int cpu)
> 
>  static cpumask_t cpu_initialized;
> 
> -/*
> - * Sets up system tables and descriptors.
> - *
> - * - Sets up TSS with stack pointers, including ISTs
> - * - Inserts TSS selector into regular and compat GDTs
> - * - Loads GDT, IDT, TR then null LDT
> - * - Sets up IST references in the IDT
> - */
> -void load_system_tables(void)
> -{
> -	unsigned int i, cpu = smp_processor_id();
> -	unsigned long stack_bottom = get_stack_bottom(),
> -		stack_top = stack_bottom & ~(STACK_SIZE - 1);
> -	/*
> -	 * NB: define tss_page as a local variable because clang 3.5 doesn't
> -	 * support using ARRAY_SIZE against per-cpu variables.
> -	 */
> -	struct tss_page *tss_page = &this_cpu(tss_page);
> -	idt_entry_t *idt = this_cpu(idt);
> -
> -	/* The TSS may be live.	 Disuade any clever optimisations. */
> -	volatile struct tss64 *tss = &tss_page->tss;
> -	seg_desc_t *gdt =
> -		this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY;
> -
> -	const struct desc_ptr gdtr = {
> -		.base = (unsigned long)gdt,
> -		.limit = LAST_RESERVED_GDT_BYTE,
> -	};
> -	const struct desc_ptr idtr = {
> -		.base = (unsigned long)idt,
> -		.limit = sizeof(bsp_idt) - 1,
> -	};
> -
> -	/*
> -	 * Set up the TSS.  Warning - may be live, and the NMI/#MC must 
> remain
> -	 * valid on every instruction boundary.  (Note: these are all
> -	 * semantically ACCESS_ONCE() due to tss's volatile qualifier.)
> -	 *
> -	 * rsp0 refers to the primary stack.  #MC, NMI, #DB and #DF handlers
> -	 * each get their own stacks.  No IO Bitmap.
> -	 */
> -	tss->rsp0 = stack_bottom;
> -	tss->ist[IST_MCE - 1] = stack_top + (1 + IST_MCE) * PAGE_SIZE;
> -	tss->ist[IST_NMI - 1] = stack_top + (1 + IST_NMI) * PAGE_SIZE;
> -	tss->ist[IST_DB  - 1] = stack_top + (1 + IST_DB)  * PAGE_SIZE;
> -	tss->ist[IST_DF  - 1] = stack_top + (1 + IST_DF)  * PAGE_SIZE;
> -	tss->bitmap = IOBMP_INVALID_OFFSET;
> -
> -	/* All other stack pointers poisioned. */
> -	for ( i = IST_MAX; i < ARRAY_SIZE(tss->ist); ++i )
> -		tss->ist[i] = 0x8600111111111111ul;
> -	tss->rsp1 = 0x8600111111111111ul;
> -	tss->rsp2 = 0x8600111111111111ul;
> -
> -	/*
> -	 * Set up the shadow stack IST.  Used entries must point at the
> -	 * supervisor stack token.  Unused entries are poisoned.
> -	 *
> -	 * This IST Table may be live, and the NMI/#MC entries must
> -	 * remain valid on every instruction boundary, hence the
> -	 * volatile qualifier.
> -	 */
> -	if (cpu_has_xen_shstk) {
> -		volatile uint64_t *ist_ssp = tss_page->ist_ssp;
> -		unsigned long
> -			mce_ssp = stack_top + (IST_MCE * IST_SHSTK_SIZE) - 8,
> -			nmi_ssp = stack_top + (IST_NMI * IST_SHSTK_SIZE) - 8,
> -			db_ssp  = stack_top + (IST_DB  * IST_SHSTK_SIZE) - 8,
> -			df_ssp  = stack_top + (IST_DF  * IST_SHSTK_SIZE) - 8;
> -
> -		ist_ssp[0] = 0x8600111111111111ul;
> -		ist_ssp[IST_MCE] = mce_ssp;
> -		ist_ssp[IST_NMI] = nmi_ssp;
> -		ist_ssp[IST_DB]	 = db_ssp;
> -		ist_ssp[IST_DF]	 = df_ssp;
> -		for ( i = IST_DF + 1; i < ARRAY_SIZE(tss_page->ist_ssp); ++i )
> -			ist_ssp[i] = 0x8600111111111111ul;
> -
> -		if (IS_ENABLED(CONFIG_XEN_SHSTK) && rdssp() != SSP_NO_SHSTK) {
> -			/*
> -			 * Rewrite supervisor tokens when shadow stacks are
> -			 * active.  This resets any busy bits left across S3.
> -			 */
> -			wrss(mce_ssp, _p(mce_ssp));
> -			wrss(nmi_ssp, _p(nmi_ssp));
> -			wrss(db_ssp,  _p(db_ssp));
> -			wrss(df_ssp,  _p(df_ssp));
> -		}
> -
> -		wrmsrl(MSR_ISST, (unsigned long)ist_ssp);
> -	}
> -
> -	_set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
> -			 sizeof(*tss) - 1, SYS_DESC_tss_avail);
> -	if ( IS_ENABLED(CONFIG_PV32) )
> -		_set_tssldt_desc(
> -			this_cpu(compat_gdt) - FIRST_RESERVED_GDT_ENTRY + TSS_ENTRY,
> -			(unsigned long)tss, sizeof(*tss) - 1, SYS_DESC_tss_busy);
> -
> -	per_cpu(full_gdt_loaded, cpu) = false;
> -	lgdt(&gdtr);
> -	lidt(&idtr);
> -	ltr(TSS_SELECTOR);
> -	lldt(0);
> -
> -	enable_each_ist(idt);
> -
> -	/*
> -	 * Bottom-of-stack must be 16-byte aligned!
> -	 *
> -	 * Defer checks until exception support is sufficiently set up.
> -	 */
> -	BUILD_BUG_ON((sizeof(struct cpu_info) -
> -		      sizeof(struct cpu_user_regs)) & 0xf);
> -	BUG_ON(system_state != SYS_STATE_early_boot && (stack_bottom & 0xf));
> -}
> -
>  static void skinit_enable_intr(void)
>  {
>  	uint64_t val;
> diff --git a/xen/arch/x86/include/asm/system.h 
> b/xen/arch/x86/include/asm/system.h
> index 57446c5b465c..3cdc56e4ba6d 100644
> --- a/xen/arch/x86/include/asm/system.h
> +++ b/xen/arch/x86/include/asm/system.h
> @@ -256,7 +256,6 @@ static inline int local_irq_is_enabled(void)
>  #define BROKEN_ACPI_Sx          0x0001
>  #define BROKEN_INIT_AFTER_S1    0x0002
> 
> -void load_system_tables(void);
>  void subarch_percpu_traps_init(void);
> 
>  #endif
> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
> index 8ca379c9e4cb..13b8fcf0ba51 100644
> --- a/xen/arch/x86/traps-setup.c
> +++ b/xen/arch/x86/traps-setup.c
> @@ -7,6 +7,7 @@
> 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
> 
> @@ -19,6 +20,124 @@ boolean_param("ler", opt_ler);
> 
>  void nocall entry_PF(void);
> 
> +/*
> + * Sets up system tables and descriptors for IDT devliery.
> + *
> + * - Sets up TSS with stack pointers, including ISTs
> + * - Inserts TSS selector into regular and compat GDTs
> + * - Loads GDT, IDT, TR then null LDT
> + * - Sets up IST references in the IDT
> + */
> +static void load_system_tables(void)
> +{
> +    unsigned int i, cpu = smp_processor_id();
> +    unsigned long stack_bottom = get_stack_bottom(),
> +        stack_top = stack_bottom & ~(STACK_SIZE - 1);
> +    /*
> +     * NB: define tss_page as a local variable because clang 3.5 
> doesn't
> +     * support using ARRAY_SIZE against per-cpu variables.
> +     */
> +    struct tss_page *tss_page = &this_cpu(tss_page);
> +    idt_entry_t *idt = this_cpu(idt);
> +

Given the clang baseline this might not be needed anymore?

> +    /* The TSS may be live.  Disuade any clever optimisations. */
> +    volatile struct tss64 *tss = &tss_page->tss;
> +    seg_desc_t *gdt =
> +        this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY;
> +
> +    const struct desc_ptr gdtr = {
> +        .base = (unsigned long)gdt,
> +        .limit = LAST_RESERVED_GDT_BYTE,
> +    };
> +    const struct desc_ptr idtr = {
> +        .base = (unsigned long)idt,
> +        .limit = sizeof(bsp_idt) - 1,
> +    };
> +
> +    /*
> +     * Set up the TSS.  Warning - may be live, and the NMI/#MC must 
> remain
> +     * valid on every instruction boundary.  (Note: these are all
> +     * semantically ACCESS_ONCE() due to tss's volatile qualifier.)
> +     *
> +     * rsp0 refers to the primary stack.  #MC, NMI, #DB and #DF 
> handlers
> +     * each get their own stacks.  No IO Bitmap.
> +     */
> +    tss->rsp0 = stack_bottom;
> +    tss->ist[IST_MCE - 1] = stack_top + (1 + IST_MCE) * PAGE_SIZE;
> +    tss->ist[IST_NMI - 1] = stack_top + (1 + IST_NMI) * PAGE_SIZE;
> +    tss->ist[IST_DB  - 1] = stack_top + (1 + IST_DB)  * PAGE_SIZE;
> +    tss->ist[IST_DF  - 1] = stack_top + (1 + IST_DF)  * PAGE_SIZE;
> +    tss->bitmap = IOBMP_INVALID_OFFSET;
> +
> +    /* All other stack pointers poisioned. */
> +    for ( i = IST_MAX; i < ARRAY_SIZE(tss->ist); ++i )
> +        tss->ist[i] = 0x8600111111111111UL;
> +    tss->rsp1 = 0x8600111111111111UL;
> +    tss->rsp2 = 0x8600111111111111UL;
> +
> +    /*
> +     * Set up the shadow stack IST.  Used entries must point at the
> +     * supervisor stack token.  Unused entries are poisoned.
> +     *
> +     * This IST Table may be live, and the NMI/#MC entries must
> +     * remain valid on every instruction boundary, hence the
> +     * volatile qualifier.
> +     */
> +    if ( cpu_has_xen_shstk )
> +    {
> +        volatile uint64_t *ist_ssp = tss_page->ist_ssp;
> +        unsigned long
> +            mce_ssp = stack_top + (IST_MCE * IST_SHSTK_SIZE) - 8,
> +            nmi_ssp = stack_top + (IST_NMI * IST_SHSTK_SIZE) - 8,
> +            db_ssp  = stack_top + (IST_DB  * IST_SHSTK_SIZE) - 8,
> +            df_ssp  = stack_top + (IST_DF  * IST_SHSTK_SIZE) - 8;
> +
> +        ist_ssp[0] = 0x8600111111111111UL;
> +        ist_ssp[IST_MCE] = mce_ssp;
> +        ist_ssp[IST_NMI] = nmi_ssp;
> +        ist_ssp[IST_DB]  = db_ssp;
> +        ist_ssp[IST_DF]  = df_ssp;
> +        for ( i = IST_DF + 1; i < ARRAY_SIZE(tss_page->ist_ssp); ++i )
> +            ist_ssp[i] = 0x8600111111111111UL;
> +
> +        if ( IS_ENABLED(CONFIG_XEN_SHSTK) && rdssp() != SSP_NO_SHSTK )
> +        {
> +            /*
> +             * Rewrite supervisor tokens when shadow stacks are
> +             * active.  This resets any busy bits left across S3.
> +             */
> +            wrss(mce_ssp, _p(mce_ssp));
> +            wrss(nmi_ssp, _p(nmi_ssp));
> +            wrss(db_ssp,  _p(db_ssp));
> +            wrss(df_ssp,  _p(df_ssp));
> +        }
> +
> +        wrmsrns(MSR_ISST, (unsigned long)ist_ssp);
> +    }
> +
> +    _set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
> +                     sizeof(*tss) - 1, SYS_DESC_tss_avail);
> +    if ( IS_ENABLED(CONFIG_PV32) )
> +        _set_tssldt_desc(
> +            this_cpu(compat_gdt) - FIRST_RESERVED_GDT_ENTRY + 
> TSS_ENTRY,
> +            (unsigned long)tss, sizeof(*tss) - 1, SYS_DESC_tss_busy);
> +
> +    per_cpu(full_gdt_loaded, cpu) = false;
> +    lgdt(&gdtr);
> +    lidt(&idtr);
> +    ltr(TSS_SELECTOR);
> +    lldt(0);
> +
> +    enable_each_ist(idt);
> +
> +    /*
> +     * tss->rsp0 must be 16-byte aligned.
> +     *
> +     * Defer checks until exception support is sufficiently set up.
> +     */
> +    BUG_ON(stack_bottom & 15);
> +}
> +
>  static void __init init_ler(void)
>  {
>      unsigned int msr = 0;
> @@ -139,3 +258,16 @@ void asmlinkage ap_early_traps_init(void)
>  {
>      load_system_tables();
>  }
> +
> +static void __init __maybe_unused build_assertions(void)
> +{
> +    /*
> +     * This is best-effort (it doesn't cover some padding corner 
> cases), but
> +     * is preforable to hitting the check at boot time.
> +     *
> +     * tss->rsp0, pointing at the end of cpu_info.guest_cpu_user_regs, 
> must be
> +     * 16-byte aligned.
> +     */
> +    BUILD_BUG_ON((sizeof(struct cpu_info) -
> +                  endof_field(struct cpu_info, guest_cpu_user_regs)) & 
> 15);
> +}
> diff --git a/xen/include/xen/macros.h b/xen/include/xen/macros.h
> index cd528fbdb127..726ba221e0d8 100644
> --- a/xen/include/xen/macros.h
> +++ b/xen/include/xen/macros.h
> @@ -102,6 +102,8 @@
>   */
>  #define sizeof_field(type, member) sizeof(((type *)NULL)->member)
> 
> +#define endof_field(type, member) (offsetof(type, member) + 
> sizeof_field(type, member))
> +
>  /* Cast an arbitrary integer to a pointer. */
>  #define _p(x) ((void *)(unsigned long)(x))

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Tue, 12 Aug 2025 11:52:38 +0200
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Subject: Re: [PATCH 10/22] x86/traps: Move subarch_percpu_traps_init() into
 traps-setup.c
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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 <646c538a-850a-4370-8132-c06d9be8b422@citrix.com>
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In-Reply-To: <646c538a-850a-4370-8132-c06d9be8b422@citrix.com>
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On 11.08.2025 10:17, Andrew Cooper wrote:
> On 08/08/2025 9:23 pm, Andrew Cooper wrote:
>> ... along with the supporting functions.  Switch to Xen coding style, and make
>> static as there are no external callers.
>>
>> Rename to legacy_syscall_init() as a more accurate name.
>>
>> No functional change.
>>
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Jan Beulich 
>> CC: Roger Pau Monné 
>> ---
>>  xen/arch/x86/include/asm/system.h |  2 -
>>  xen/arch/x86/traps-setup.c        | 97 ++++++++++++++++++++++++++++++-
>>  xen/arch/x86/x86_64/traps.c       | 92 -----------------------------
>>  3 files changed, 95 insertions(+), 96 deletions(-)
>>
>> diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
>> index 3cdc56e4ba6d..6c2800d8158d 100644
>> --- a/xen/arch/x86/include/asm/system.h
>> +++ b/xen/arch/x86/include/asm/system.h
>> @@ -256,6 +256,4 @@ static inline int local_irq_is_enabled(void)
>>  #define BROKEN_ACPI_Sx          0x0001
>>  #define BROKEN_INIT_AFTER_S1    0x0002
>>  
>> -void subarch_percpu_traps_init(void);
>> -
>>  #endif
>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>> index 13b8fcf0ba51..fbae7072c292 100644
>> --- a/xen/arch/x86/traps-setup.c
>> +++ b/xen/arch/x86/traps-setup.c
>> @@ -2,13 +2,15 @@
>>  /*
>>   * Configuration of event handling for all CPUs.
>>   */
>> +#include 
>>  #include 
>>  #include 
>>  
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> -#include 
>> +#include 
>>  #include 
>>  
>>  DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt);
>> @@ -19,6 +21,8 @@ static bool __initdata opt_ler;
>>  boolean_param("ler", opt_ler);
>>  
>>  void nocall entry_PF(void);
>> +void nocall lstar_enter(void);
>> +void nocall cstar_enter(void);
>>  
>>  /*
>>   * Sets up system tables and descriptors for IDT devliery.
>> @@ -138,6 +142,95 @@ static void load_system_tables(void)
>>      BUG_ON(stack_bottom & 15);
>>  }
>>  
>> +static unsigned int write_stub_trampoline(
>> +    unsigned char *stub, unsigned long stub_va,
>> +    unsigned long stack_bottom, unsigned long target_va)
>> +{
>> +    unsigned char *p = stub;
>> +
>> +    if ( cpu_has_xen_ibt )
>> +    {
>> +        place_endbr64(p);
>> +        p += 4;
>> +    }
>> +
>> +    /* Store guest %rax into %ss slot */
>> +    /* movabsq %rax, stack_bottom - 8 */
>> +    *p++ = 0x48;
>> +    *p++ = 0xa3;
>> +    *(uint64_t *)p = stack_bottom - 8;
>> +    p += 8;
>> +
>> +    /* Store guest %rsp in %rax */
>> +    /* movq %rsp, %rax */
>> +    *p++ = 0x48;
>> +    *p++ = 0x89;
>> +    *p++ = 0xe0;
>> +
>> +    /* Switch to Xen stack */
>> +    /* movabsq $stack_bottom - 8, %rsp */
>> +    *p++ = 0x48;
>> +    *p++ = 0xbc;
>> +    *(uint64_t *)p = stack_bottom - 8;
>> +    p += 8;
>> +
>> +    /* jmp target_va */
>> +    *p++ = 0xe9;
>> +    *(int32_t *)p = target_va - (stub_va + (p - stub) + 4);
>> +    p += 4;
>> +
>> +    /* Round up to a multiple of 16 bytes. */
>> +    return ROUNDUP(p - stub, 16);
>> +}
>> +
>> +static void legacy_syscall_init(void)
>> +{
>> +    unsigned long stack_bottom = get_stack_bottom();
>> +    unsigned long stub_va = this_cpu(stubs.addr);
>> +    unsigned char *stub_page;
>> +    unsigned int offset;
>> +
>> +    /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
>> +    if ( !IS_ENABLED(CONFIG_PV) )
>> +        return;
>> +
>> +    stub_page = map_domain_page(_mfn(this_cpu(stubs.mfn)));
>> +
>> +    /*
>> +     * Trampoline for SYSCALL entry from 64-bit mode.  The VT-x HVM vcpu
>> +     * context switch logic relies on the SYSCALL trampoline being at the
>> +     * start of the stubs.
>> +     */
>> +    wrmsrl(MSR_LSTAR, stub_va);
>> +    offset = write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>> +                                   stub_va, stack_bottom,
>> +                                   (unsigned long)lstar_enter);
>> +    stub_va += offset;
>> +
>> +    if ( cpu_has_sep )
>> +    {
>> +        /* SYSENTER entry. */
>> +        wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
>> +        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
>> +        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
>> +    }
>> +
>> +    /* Trampoline for SYSCALL entry from compatibility mode. */
>> +    wrmsrl(MSR_CSTAR, stub_va);
>> +    offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>> +                                    stub_va, stack_bottom,
>> +                                    (unsigned long)cstar_enter);
>> +
>> +    /* Don't consume more than half of the stub space here. */
>> +    ASSERT(offset <= STUB_BUF_SIZE / 2);
>> +
>> +    unmap_domain_page(stub_page);
>> +
>> +    /* Common SYSCALL parameters. */
>> +    wrmsrl(MSR_STAR, XEN_MSR_STAR);
>> +    wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
>> +}
> 
> These want adjusting to use wrmsrns(), similarly to the previous patch. 
> Fixed locally.

Also the one higher in the function, I suppose.

Acked-by: Jan Beulich 

Jan


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Subject: Re: [PATCH 11/22] x86/traps: Fold x86_64/traps.c into traps.c
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On 08.08.2025 22:23, Andrew Cooper wrote:
> It's now just the double fault handler and various state dumping functions.

Ah, yes - long awaited consolidation.

> Swap u64 for uint64_t, and fix a few other minor style issues.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 



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On 08.08.2025 22:23, Andrew Cooper wrote:
> These can become static now the two traps.c have been merged.
> 
> No fucntional change.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 



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MIME-Version: 1.0
Date: Tue, 12 Aug 2025 11:55:29 +0200
From: Nicola Vetrini 
To: Jan Beulich 
Cc: xen-devel@lists.xenproject.org, Stefano Stabellini
 , Julien Grall , Bertrand Marquis
 , Michal Orzel , Volodymyr
 Babchuk , Andrew Cooper
 , Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Dmytro Prokopchuk1
 
Subject: Re: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
In-Reply-To: 
References: <7cd71ed21383c189fedb3250ddde54a593f7f98b.1754944131.git.dmytro_prokopchuk1@epam.com>
 
 
Message-ID: <8ce96224f88513e4041d33248456fab3@bugseng.com>
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On 2025-08-12 09:25, Jan Beulich wrote:
> On 11.08.2025 23:25, Nicola Vetrini wrote:
>> On 2025-08-11 22:30, Dmytro Prokopchuk1 wrote:
>>> --- a/xen/arch/arm/decode.c
>>> +++ b/xen/arch/arm/decode.c
>>> @@ -178,6 +178,9 @@ static int decode_thumb(register_t pc, struct
>>> hsr_dabt *dabt)
>>>          case 3: /* Signed byte */
>>>              update_dabt(dabt, reg, 0, true);
>>>              break;
>>> +        default:
>>> +            ASSERT_UNREACHABLE();
>>> +            break;
>>>          }
>>> 
>> 
>> I think this is fine, and there should be no problems with the break
>> being unreachable in some configs due to the call property for
>> ASSERT_UNREACHABLE
>> 
>> -doc_begin="Calls to function `__builtin_unreachable()' in the 
>> expansion
>> of macro
>> `ASSERT_UNREACHABLE()' are not considered to have the `noreturn'
>> property."
>> -call_properties+={"name(__builtin_unreachable)&&stmt(begin(any_exp(macro(name(ASSERT_UNREACHABLE)))))",
>> {"noreturn(false)"}}
>> -doc_end
> 
> Did you also see Julien's reply? Imo, to address a complaint from one
> rule, another rule is then being violated: The "default" label itself
> is unreachable here.
> 
> Jan

Unfortunately only after sending my reply, however the point here is 
that ASSERT_UNREACHABLE() is now considered as if it was not actually a 
source of unreachability for any statement below (which is the case only 
in configurations where NDEBUG is undefined iirc). This was done mainly 
to allow stubs for Rule 2.1 so that their return statement just after an 
ASSERT_UNREACHABLE() is not seen as a problem, but given that the 
configuration to obtain that is global it influences treatment for other 
rules as well, and its addition is relatively recent compared to the 
text written in rules.rst.

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v6 15/19] tools/cpufreq: introduce helper to deal with
 CPPC-related parameters
Thread-Topic: [PATCH v6 15/19] tools/cpufreq: introduce helper to deal with
 CPPC-related parameters
Thread-Index: AQHb8hcn+tWFoATVBE6qNhfRcQLSnbQ/8H0AgB8IiuA=
Date: Tue, 12 Aug 2025 09:56:27 +0000
Message-ID:
 
References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
 <20250711035106.2540522-16-Penny.Zheng@amd.com>
 <9df16790-268b-4221-87ec-829ab4446872@suse.com>
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From: "L, John Preetham (893)" 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" 
Subject: RE: Guide for Launching Full Linux VM on Xen (R-Car H3e Board)
Thread-Topic: Guide for Launching Full Linux VM on Xen (R-Car H3e Board)
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Hi Volodymyr,
Is there any update on my request?

Regards,
John Preetham L

From: L, John Preetham (893)
Sent: 06 August 2025 16:55
To: Volodymyr Babchuk 
Cc: xen-devel@lists.xenproject.org
Subject: Guide for Launching Full Linux VM on Xen (R-Car H3e Board)


Hi Volodymyr,


I'm currently working with the R-Car H3e board and exploring Xen virtualiza=
tion on this platform. While I've found resources related to dom0 and domU =
configurations, I'm specifically looking for guidance on building and launc=
hing a full-fledged Linux VM on Xen-beyond the domd setup.

Are there any official or community-maintained guides or examples tailored =
for ARM-based platforms like the R-Car H3e that walk through setting up a s=
tandalone Linux VM with full capabilities (networking, storage, graphical i=
nterface, etc.)?

Any help or direction would be greatly appreciated.

Best regards,
John Preetham


If you are not the addressee, please inform us immediately that you have re=
ceived this e-mail by mistake, and delete it. We thank you for your support=
.


--_000_FR6P281MB3484B232D3995BC4C79D25F4B82BAFR6P281MB3484DEUP_
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    Hi Volodymyr,
    
Is there any update on my request?
    

    
Regards,
    
John Preetham L
    

     
    

    

    

    From:
 L, John Preetham (893) 
    
Sent: 06 August 2025 16:55
    
To: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
    
Cc: xen-devel@lists.xenproject.org
    
Subject: Guide for Launching Full Linux VM on Xen (R-Car H3e Board)<=
o:p>
    

    

    

     
    

    Hi Volodymyr,
    

     
    

    I’m currently working with the R-Car H3e board=
 and exploring Xen virtualization on this platform. While I’ve found =
resources related to dom0 and domU configurations, I’m specifically l=
ooking for guidance on building and launching a full-fledged
 Linux VM on Xen—beyond the domd setup.
    

     
    

    Are there any official or community-maintained guide=
s or examples tailored for ARM-based platforms like the R-Car H3e that walk=
 through setting up a standalone Linux VM with full capabilities (networkin=
g, storage, graphical interface, etc.)?
    

     
    

    Any help or direction would be greatly appreciated.<=
o:p>
    

     
    

    Best regards,  
    

    John Preetham
    

     
    

    

<=
br>
If you are not the addressee, please inform us immediately that you have re=
ceived this e-mail by mistake, and delete it. We thank you for your support=
.
    

    

    


    



--_000_FR6P281MB3484B232D3995BC4C79D25F4B82BAFR6P281MB3484DEUP_--


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To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v6 15/19] tools/cpufreq: introduce helper to deal with
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Thread-Topic: [PATCH v6 15/19] tools/cpufreq: introduce helper to deal with
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Date: Tue, 12 Aug 2025 10:11:38 +0000
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References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
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From: "Penny, Zheng" 
To: "Andryuk, Jason" , Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, Juergen Gross , Andrew Cooper
	, "Orzel, Michal" , Julien
 Grall , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Stefano Stabellini ,
	"xen-devel@lists.xenproject.org" 
Subject: RE: [PATCH v6 16/19] xen/cpufreq: introduce GET_CPUFREQ_CPPC sub-op
Thread-Topic: [PATCH v6 16/19] xen/cpufreq: introduce GET_CPUFREQ_CPPC sub-op
Thread-Index: AQHb8hcsas/z4nFla0Oi87EUBsxHHbRBWmQAgAAMwYCAHZXsIA==
Date: Tue, 12 Aug 2025 10:15:22 +0000
Message-ID:
 
References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
 <20250711035106.2540522-17-Penny.Zheng@amd.com>
 <87d9d5a1-39aa-46ca-9f2a-9169a2ef7a6c@suse.com>
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On 12.08.2025 11:55, Nicola Vetrini wrote:
> On 2025-08-12 09:25, Jan Beulich wrote:
>> On 11.08.2025 23:25, Nicola Vetrini wrote:
>>> On 2025-08-11 22:30, Dmytro Prokopchuk1 wrote:
>>>> --- a/xen/arch/arm/decode.c
>>>> +++ b/xen/arch/arm/decode.c
>>>> @@ -178,6 +178,9 @@ static int decode_thumb(register_t pc, struct
>>>> hsr_dabt *dabt)
>>>>          case 3: /* Signed byte */
>>>>              update_dabt(dabt, reg, 0, true);
>>>>              break;
>>>> +        default:
>>>> +            ASSERT_UNREACHABLE();
>>>> +            break;
>>>>          }
>>>>
>>>
>>> I think this is fine, and there should be no problems with the break
>>> being unreachable in some configs due to the call property for
>>> ASSERT_UNREACHABLE
>>>
>>> -doc_begin="Calls to function `__builtin_unreachable()' in the 
>>> expansion
>>> of macro
>>> `ASSERT_UNREACHABLE()' are not considered to have the `noreturn'
>>> property."
>>> -call_properties+={"name(__builtin_unreachable)&&stmt(begin(any_exp(macro(name(ASSERT_UNREACHABLE)))))",
>>> {"noreturn(false)"}}
>>> -doc_end
>>
>> Did you also see Julien's reply? Imo, to address a complaint from one
>> rule, another rule is then being violated: The "default" label itself
>> is unreachable here.
> 
> Unfortunately only after sending my reply, however the point here is 
> that ASSERT_UNREACHABLE() is now considered as if it was not actually a 
> source of unreachability for any statement below (which is the case only 
> in configurations where NDEBUG is undefined iirc). This was done mainly 
> to allow stubs for Rule 2.1 so that their return statement just after an 
> ASSERT_UNREACHABLE() is not seen as a problem, but given that the 
> configuration to obtain that is global it influences treatment for other 
> rules as well, and its addition is relatively recent compared to the 
> text written in rules.rst.

I understand the special treatment of ASSERT_UNREACHABLE(). Yet even if that
wasn't there, both the default: label and the break; statement would be
unreachable here.

Jan


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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH] x86/current: Annotate get_cpu_info() as attr_const
Date: Tue, 12 Aug 2025 11:30:40 +0100
Message-Id: <20250812103040.1765666-1-andrew.cooper3@citrix.com>
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The result of this calculation will always be identical, even across context
switch in x86.  Tell the compiler.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

  add/remove: 0/0 grow/shrink: 0/15 up/down: 0/-300 (-300)
  Function                                     old     new   delta
  nsvm_vcpu_vmexit_event                       114     111      -3
  nsvm_vcpu_reset                              178     175      -3
  nestedsvm_vcpu_interrupt                     302     299      -3
  compat_memory_op.cold                        200     197      -3
  vcpu_block_enable_events                      30      26      -4
  nestedsvm_vmexit_defer                        90      86      -4
  dom0_construct                              8441    8435      -6
  svm_vmexit_do_clgi                           206     198      -8
  nsvm_vcpu_vmrun                             2530    2522      -8
  compat_multicall                            1194    1178     -16
  arch_do_domctl                              8621    8605     -16
  hvm_set_param.cold                            74      44     -30
  do_multicall                                1165    1133     -32
  ept_set_entry                               2023    1978     -45
  compat_memory_op                            7440    7321    -119
---
 xen/arch/x86/include/asm/current.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index a7c9473428b2..fd30422707d9 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -83,7 +83,7 @@ static inline struct cpu_info *get_cpu_info_from_stack(unsigned long sp)
     return (struct cpu_info *)((sp | (STACK_SIZE - 1)) + 1) - 1;
 }
 
-static inline struct cpu_info *get_cpu_info(void)
+static inline attr_const struct cpu_info *get_cpu_info(void)
 {
 #ifdef __clang__
     /* Clang complains that sp in the else case is not initialised. */
-- 
2.39.5



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Date: Tue, 12 Aug 2025 11:30:59 +0100
From: Hari Limaye 
To: Ayan Kumar Halder 
Cc: xen-devel@lists.xenproject.org, 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Volodymyr Babchuk 
Subject: Re: [PATCH v1 1/2] arm/mpu: Enable is_xen_heap_page and co for ARM_32
Message-ID: 
References: <20250807174529.595577-1-ayan.kumar.halder@amd.com>
 <20250807174529.595577-2-ayan.kumar.halder@amd.com>
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Hi Ayan,

> On Thu, Aug 07, 2025 at 06:45:28PM +0000, Ayan Kumar Halder wrote:
> In case of ARM_32, all of the RAM will be covered by a permanent contiguous
> mapping (where VA == PA) and there will be a single heap. Thus, the memory
> allocated from Xen heap uses PGC_xen_heap.
> This is similar to the scenario described for
> "CONFIG_SEPARATE_XENHEAP=n W/ DIRECT MAP OF ALL RAM" in common/page_alloc.c.
> 
> Signed-off-by: Ayan Kumar Halder 
> ---

This patch breaks the build for ARM_32, CONFIG_MMU targets due to
multiple definition of `is_xen_heap_page` and `is_xen_heap_mfn`. The
pre-existing definitions are located at xen/arch/arm/include/asm/mmu/mm.h:30:9

Cheers,
Hari


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Subject: Re: [PATCH] x86/current: Annotate get_cpu_info() as attr_const
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250812103040.1765666-1-andrew.cooper3@citrix.com>
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On 12.08.2025 12:30, Andrew Cooper wrote:
> The result of this calculation will always be identical, even across context
> switch in x86.  Tell the compiler.

Or if it ended up different (e.g. due to stack pointer corruption) we're
hosed anyway.

> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 



From xen-devel-bounces@lists.xenproject.org Tue Aug 12 10:50:03 2025
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Date: Tue, 12 Aug 2025 11:49:46 +0100
From: Hari Limaye 
To: Ayan Kumar Halder 
Cc: xen-devel@lists.xenproject.org, 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Volodymyr Babchuk 
Subject: Re: [PATCH v1 2/2] arm/mpu: Disable map_domain_page for MPU
Message-ID: 
References: <20250807174529.595577-1-ayan.kumar.halder@amd.com>
 <20250807174529.595577-3-ayan.kumar.halder@amd.com>
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In-Reply-To: <20250807174529.595577-3-ayan.kumar.halder@amd.com>

Hi Ayan,

> On Thu, Aug 07, 2025 at 06:45:29PM +0000, Ayan Kumar Halder wrote:
> There is no domheap for ARM_32. All of the RAM is mapped and VA == PA.
> 
> Signed-off-by: Ayan Kumar Halder 
> ---
>  xen/arch/arm/Kconfig           |  2 +-
>  xen/arch/arm/mpu/domain-page.c | 45 ----------------------------------
>  2 files changed, 1 insertion(+), 46 deletions(-)
>  delete mode 100644 xen/arch/arm/mpu/domain-page.c
> 
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index a0c8160474..5355534f3d 100644
> --- a/xen/arch/arm/Kconfig

This patch is breaking ARM_32, MPU builds for me. I think this also needs:

```
diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile
index 50f8fe4326..4963c8b550 100644
--- a/xen/arch/arm/mpu/Makefile
+++ b/xen/arch/arm/mpu/Makefile
@@ -1,6 +1,5 @@
 obj-$(CONFIG_ARM_32) += arm32/
 obj-$(CONFIG_ARM_64) += arm64/
-obj-$(CONFIG_ARM_32) += domain-page.o
 obj-y += mm.o
 obj-y += p2m.o
 obj-y += setup.init.o
 ```

Cheers,
Hari


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Date: Tue, 12 Aug 2025 12:01:27 +0100
From: Mark Rutland 
To: Jinjie Ruan 
Cc: catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com,
	sstabellini@kernel.org, puranjay@kernel.org, broonie@kernel.org,
	mbenes@suse.cz, ryan.roberts@arm.com, akpm@linux-foundation.org,
	chenl311@chinatelecom.cn, ada.coupriediaz@arm.com,
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	liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org,
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH -next v7 2/7] arm64: entry: Refactor the entry and exit
 for exceptions from EL1
Message-ID: 
References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 <20250729015456.3411143-3-ruanjinjie@huawei.com>
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In-Reply-To: <20250729015456.3411143-3-ruanjinjie@huawei.com>

Hi Jinjie,

On Tue, Jul 29, 2025 at 09:54:51AM +0800, Jinjie Ruan wrote:
> The generic entry code uses irqentry_state_t to track lockdep and RCU
> state across exception entry and return. For historical reasons, arm64
> embeds similar fields within its pt_regs structure.
> 
> In preparation for moving arm64 over to the generic entry code, pull
> these fields out of arm64's pt_regs, and use a separate structure,
> matching the style of the generic entry code.
> 
> No functional changes.
> 
> Suggested-by: Mark Rutland 
> Signed-off-by: Jinjie Ruan 

One minor formatting nit below, but with aside from that this looks
great, and with that fixed up:

Acked-by: Mark Rutland 

[...]

> @@ -475,73 +497,81 @@ UNHANDLED(el1t, 64, error)
>  static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
>  {
>  	unsigned long far = read_sysreg(far_el1);
> +	arm64_irqentry_state_t state;
>  
> -	enter_from_kernel_mode(regs);
> +	state = enter_from_kernel_mode(regs);
>  	local_daif_inherit(regs);
>  	do_mem_abort(far, esr, regs);
>  	local_daif_mask();
> -	exit_to_kernel_mode(regs);
> +	exit_to_kernel_mode(regs, state);
>  }
>  
>  static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr)
>  {
>  	unsigned long far = read_sysreg(far_el1);
> +	arm64_irqentry_state_t state;
>  
> -	enter_from_kernel_mode(regs);
> +	state = enter_from_kernel_mode(regs);
>  	local_daif_inherit(regs);
>  	do_sp_pc_abort(far, esr, regs);
>  	local_daif_mask();
> -	exit_to_kernel_mode(regs);
> +	exit_to_kernel_mode(regs, state);
>  }
>  
>  static void noinstr el1_undef(struct pt_regs *regs, unsigned long esr)
>  {
> -	enter_from_kernel_mode(regs);
> +	arm64_irqentry_state_t state = enter_from_kernel_mode(regs);
> +
>  	local_daif_inherit(regs);
>  	do_el1_undef(regs, esr);
>  	local_daif_mask();
> -	exit_to_kernel_mode(regs);
> +	exit_to_kernel_mode(regs, state);
>  }

I'd prefer if we consistently defined 'state' on a separate line, before
the main block consisting of:

	state = enter_from_kernel_mode(regs);
	local_daif_inherit(regs);
	do_el1_undef(regs, esr);
	local_daif_mask();
	exit_to_kernel_mode(regs, state);

... since that way the enter/exit functions clearly enclose the whole
block, which isn't as clear when there's a line gap between
enter_from_kernel_mode() and the rest of the block.

That would also be more consistent with what we do for functions that
need to read other registers (e.g. el1_abort() and el1_pc() above).

If that could be applied consistently here and below, that'd be great.

Mark.

>  static void noinstr el1_bti(struct pt_regs *regs, unsigned long esr)
>  {
> -	enter_from_kernel_mode(regs);
> +	arm64_irqentry_state_t state = enter_from_kernel_mode(regs);
> +
>  	local_daif_inherit(regs);
>  	do_el1_bti(regs, esr);
>  	local_daif_mask();
> -	exit_to_kernel_mode(regs);
> +	exit_to_kernel_mode(regs, state);
>  }
>  
>  static void noinstr el1_gcs(struct pt_regs *regs, unsigned long esr)
>  {
> -	enter_from_kernel_mode(regs);
> +	arm64_irqentry_state_t state = enter_from_kernel_mode(regs);
> +
>  	local_daif_inherit(regs);
>  	do_el1_gcs(regs, esr);
>  	local_daif_mask();
> -	exit_to_kernel_mode(regs);
> +	exit_to_kernel_mode(regs, state);
>  }
>  
>  static void noinstr el1_mops(struct pt_regs *regs, unsigned long esr)
>  {
> -	enter_from_kernel_mode(regs);
> +	arm64_irqentry_state_t state = enter_from_kernel_mode(regs);
> +
>  	local_daif_inherit(regs);
>  	do_el1_mops(regs, esr);
>  	local_daif_mask();
> -	exit_to_kernel_mode(regs);
> +	exit_to_kernel_mode(regs, state);
>  }
>  
>  static void noinstr el1_breakpt(struct pt_regs *regs, unsigned long esr)
>  {
> -	arm64_enter_el1_dbg(regs);
> +	arm64_irqentry_state_t state = arm64_enter_el1_dbg(regs);
> +
>  	debug_exception_enter(regs);
>  	do_breakpoint(esr, regs);
>  	debug_exception_exit(regs);
> -	arm64_exit_el1_dbg(regs);
> +	arm64_exit_el1_dbg(regs, state);
>  }
>  
>  static void noinstr el1_softstp(struct pt_regs *regs, unsigned long esr)
>  {
> -	arm64_enter_el1_dbg(regs);
> +	arm64_irqentry_state_t state = arm64_enter_el1_dbg(regs);
> +
>  	if (!cortex_a76_erratum_1463225_debug_handler(regs)) {
>  		debug_exception_enter(regs);
>  		/*
> @@ -554,37 +584,40 @@ static void noinstr el1_softstp(struct pt_regs *regs, unsigned long esr)
>  			do_el1_softstep(esr, regs);
>  		debug_exception_exit(regs);
>  	}
> -	arm64_exit_el1_dbg(regs);
> +	arm64_exit_el1_dbg(regs, state);
>  }
>  
>  static void noinstr el1_watchpt(struct pt_regs *regs, unsigned long esr)
>  {
>  	/* Watchpoints are the only debug exception to write FAR_EL1 */
>  	unsigned long far = read_sysreg(far_el1);
> +	arm64_irqentry_state_t state;
>  
> -	arm64_enter_el1_dbg(regs);
> +	state = arm64_enter_el1_dbg(regs);
>  	debug_exception_enter(regs);
>  	do_watchpoint(far, esr, regs);
>  	debug_exception_exit(regs);
> -	arm64_exit_el1_dbg(regs);
> +	arm64_exit_el1_dbg(regs, state);
>  }
>  
>  static void noinstr el1_brk64(struct pt_regs *regs, unsigned long esr)
>  {
> -	arm64_enter_el1_dbg(regs);
> +	arm64_irqentry_state_t state = arm64_enter_el1_dbg(regs);
> +
>  	debug_exception_enter(regs);
>  	do_el1_brk64(esr, regs);
>  	debug_exception_exit(regs);
> -	arm64_exit_el1_dbg(regs);
> +	arm64_exit_el1_dbg(regs, state);
>  }
>  
>  static void noinstr el1_fpac(struct pt_regs *regs, unsigned long esr)
>  {
> -	enter_from_kernel_mode(regs);
> +	arm64_irqentry_state_t state = enter_from_kernel_mode(regs);
> +
>  	local_daif_inherit(regs);
>  	do_el1_fpac(regs, esr);
>  	local_daif_mask();
> -	exit_to_kernel_mode(regs);
> +	exit_to_kernel_mode(regs, state);
>  }
>  
>  asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs)
> @@ -639,15 +672,16 @@ asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs)
>  static __always_inline void __el1_pnmi(struct pt_regs *regs,
>  				       void (*handler)(struct pt_regs *))
>  {
> -	arm64_enter_nmi(regs);
> +	arm64_irqentry_state_t state = arm64_enter_nmi(regs);
> +
>  	do_interrupt_handler(regs, handler);
> -	arm64_exit_nmi(regs);
> +	arm64_exit_nmi(regs, state);
>  }
>  
>  static __always_inline void __el1_irq(struct pt_regs *regs,
>  				      void (*handler)(struct pt_regs *))
>  {
> -	enter_from_kernel_mode(regs);
> +	arm64_irqentry_state_t state = enter_from_kernel_mode(regs);
>  
>  	irq_enter_rcu();
>  	do_interrupt_handler(regs, handler);
> @@ -655,7 +689,7 @@ static __always_inline void __el1_irq(struct pt_regs *regs,
>  
>  	arm64_preempt_schedule_irq();
>  
> -	exit_to_kernel_mode(regs);
> +	exit_to_kernel_mode(regs, state);
>  }
>  static void noinstr el1_interrupt(struct pt_regs *regs,
>  				  void (*handler)(struct pt_regs *))
> @@ -681,11 +715,12 @@ asmlinkage void noinstr el1h_64_fiq_handler(struct pt_regs *regs)
>  asmlinkage void noinstr el1h_64_error_handler(struct pt_regs *regs)
>  {
>  	unsigned long esr = read_sysreg(esr_el1);
> +	arm64_irqentry_state_t state;
>  
>  	local_daif_restore(DAIF_ERRCTX);
> -	arm64_enter_nmi(regs);
> +	state = arm64_enter_nmi(regs);
>  	do_serror(regs, esr);
> -	arm64_exit_nmi(regs);
> +	arm64_exit_nmi(regs, state);
>  }
>  
>  static void noinstr el0_da(struct pt_regs *regs, unsigned long esr)
> @@ -997,12 +1032,13 @@ asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs)
>  static void noinstr __el0_error_handler_common(struct pt_regs *regs)
>  {
>  	unsigned long esr = read_sysreg(esr_el1);
> +	arm64_irqentry_state_t state;
>  
>  	enter_from_user_mode(regs);
>  	local_daif_restore(DAIF_ERRCTX);
> -	arm64_enter_nmi(regs);
> +	state = arm64_enter_nmi(regs);
>  	do_serror(regs, esr);
> -	arm64_exit_nmi(regs);
> +	arm64_exit_nmi(regs, state);
>  	local_daif_restore(DAIF_PROCCTX);
>  	exit_to_user_mode(regs);
>  }
> @@ -1122,6 +1158,7 @@ asmlinkage void noinstr __noreturn handle_bad_stack(struct pt_regs *regs)
>  asmlinkage noinstr unsigned long
>  __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
>  {
> +	arm64_irqentry_state_t state;
>  	unsigned long ret;
>  
>  	/*
> @@ -1146,9 +1183,9 @@ __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
>  	else if (cpu_has_pan())
>  		set_pstate_pan(0);
>  
> -	arm64_enter_nmi(regs);
> +	state = arm64_enter_nmi(regs);
>  	ret = do_sdei_event(regs, arg);
> -	arm64_exit_nmi(regs);
> +	arm64_exit_nmi(regs, state);
>  
>  	return ret;
>  }
> -- 
> 2.34.1
> 


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Subject: Re: [PATCH] Arm: drop assertion from page_is_ram_type()
Content-Language: en-GB
To: Jan Beulich 
Cc: Stefano Stabellini ,
 Volodymyr Babchuk ,
 Bertrand Marquis ,
 Michal Orzel ,
 Oleksii Kurochko ,
 "xen-devel@lists.xenproject.org" 
References: <804094ae-bb76-4165-9e07-46b775b4b46e@suse.com>
 <86faa2fa-9f23-49a9-a909-a3dd3d5a938f@xen.org>
 
From: Julien Grall 
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Hi Jan,

On 12/08/2025 07:29, Jan Beulich wrote:
> On 11.08.2025 19:24, Julien Grall wrote:
>> On 11/08/2025 14:01, Jan Beulich wrote:
>>> Its uses in offline_page() and query_page_offline() make it reachable on
>>> Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
>>> code added. It being reachable was even mentioned in the commit
>>> introducing it, claiming it "clearly shouldn't be called on ARM just
>>> yet".
>>
>> So I agree that the function can be reached. But then I don't think the
>> function can simply return 0.
>>
>> The name is too generic enough that someone may end up to use it in
>> common code and there will be no signal to the user that the function
>> will not properly indicate a RAM page on Arm.
>>
>> I can think of two possible approaches:
>>
>> 1/ Implement properly page_is_ram_type(). We don't have an e820, but we
>> could mimick it using the memory banks we stored.
>> 2/ Rename page_is_ram_type() to page_offlinable() (or similar) so it is
>> clear that the common use is for offlining.
>>
>> The latter might be the simplest.
> 
> I consider page_offlinable() potentially ambiguous: When you offline a PCI
> device, you offline its MMIO as well, for example. Or, much like RAM, some
> page in, say, a video device's framebuffer may have gone bad. One might
> think that such would then also be covered by that function. So minimally
> page_offlinable_ram() or page_is_offlinable_ram(), I think. That would
> then have the benefit of allowing an avenue towards x86 also making its
> checking more precise, as certain RAM ranges can't possibly be offlined.
> If that's fine with you, I can enlarge the patch accordingly.

I would be fine with either name you proposed.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v5 1/2] xen/arm: fix arm_iommu_map_page after f9f6b22abf1d
Content-Language: en-GB
From: Julien Grall 
To: Stewart Hildebrand ,
 xen-devel@lists.xenproject.org
Cc: Stefano Stabellini ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: <20250725140130.4008-1-stewart.hildebrand@amd.com>
 <5fab90b6-7cae-45d0-bb8e-b1ffa0390b6f@xen.org>
 <7a3a08f4-c08e-4490-a033-53e81b261181@amd.com>
 
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On 11/08/2025 18:32, Julien Grall wrote:
> On 06/08/2025 14:58, Stewart Hildebrand wrote:
>> On 7/26/25 05:23, Julien Grall wrote:
>>> Hi,
>>>
>>> On 25/07/2025 15:01, Stewart Hildebrand wrote:
>>>> From: Stefano Stabellini 
>>>>
>>>> Up until f9f6b22abf1d "xen/arm: Map ITS doorbell register to IOMMU page
>>>> tables" the only caller of iommu_map on ARM was grant_table.c which has
>>>> a specific usage model and restrictions as described by the in-code
>>>> comment in arm_iommu_map_page.
>>>>
>>>> f9f6b22abf1d introduced a second caller to iommu_map on ARM:
>>>> vgic_v3_its_init_virtual. This specific statement in the
>>>> f9f6b22abf1d commit message is partially wrong:
>>>>
>>>> "Note that the 1:1 check in arm_iommu_map_page remains for now, as
>>>> virtual ITSes are currently only created for hwdom where the doorbell
>>>> mapping is always 1:1."
>>>>
>>>> Leading to crashes any time the hardware domain is not direct-mapped
>>>> (e.g. cache coloring and non-Dom0 hardware domain):
>>>>
>>>> (XEN) Xen BUG at drivers/passthrough/arm/iommu_helpers.c:47
>>>> [...]
>>>> (XEN) Xen call trace:
>>>> (XEN)    [<00000a000024c758>] arm_iommu_map_page+0x80/0x90 (PC)
>>>> (XEN)    [<00000a000024c750>] arm_iommu_map_page+0x78/0x90 (LR)
>>>> (XEN)    [<00000a0000250884>] iommu_map+0xcc/0x29c
>>>> (XEN)    [<00000a0000288024>] vgic_v3_its_init_domain+0x18c/0x1e8
>>>> (XEN)    [<00000a0000285228>] vgic-v3.c#vgic_v3_domain_init+0x168/0x21c
>>>> (XEN)    [<00000a0000281dcc>] domain_vgic_init+0x14c/0x210
>>>> (XEN)    [<00000a00002705a4>] arch_domain_create+0x150/0x1f0
>>>> (XEN)    [<00000a00002055e8>] domain_create+0x47c/0x6c0
>>>> (XEN)    [<00000a00002cf090>] create_domUs+0x7f8/0x8cc
>>>> (XEN)    [<00000a00002eb588>] start_xen+0x8f4/0x998
>>>> (XEN)    [<00000a000020018c>] head.o#primary_switched+0x4/0x10
>>>>
>>>> Specifically, non-1:1 hardware domain exists with cache coloring
>>>> enabled. For that, is_domain_direct_mapped(d) is false but
>>>> domain_use_host_layout(d) is true.
>>>>
>>>> Change the is_domain_direct_mapped(d) checks in arm_iommu_map_page and
>>>> arm_iommu_unmap_page into domain_use_host_layout(d) checks.
>>>>
>>>> Drop stale in-code comment specific to grant table mappings.
>>>>
>>>> Fixes: f9f6b22abf1d ("xen/arm: Map ITS doorbell register to IOMMU 
>>>> page tables")
>>>> Signed-off-by: Stefano Stabellini 
>>>> Signed-off-by: Stewart Hildebrand 
>>>
>>> Reviewed-by: Julien Grall 
>>
>> Thanks for the review! Is this ready to be committed?
> 
> Yes. Sorry, this fell through the cracks. I have queue the patch for 
> testing and committing.

This is now merged.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v8 0/6] FF-A VM to VM support
Content-Language: en-GB
To: Bertrand Marquis ,
 xen-devel@lists.xenproject.org
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Volodymyr Babchuk ,
 Jens Wiklander , Julien Grall 
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From: Julien Grall 
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Hi Bertrand,

On 11/08/2025 14:34, Bertrand Marquis wrote:
> This patch serie adds support to use FF-A between VM for communications
> using indirect messages.
> 
> It adds a Kconfig parameter to enable this feature and marks it as
> experimental as for now there is no system to restrict communication
> rights between VM using this system.
> 
> It also adds support to use VM to VM communications using FF-A even if
> there is no firmware support for FF-A. As this feature enables FF-A
> support in all cases, we also introduce a new command line parameter to
> allow the user to force which tee is to be used between FF-A and Optee
> to have a solution to enable optee support if FF-A VM to VM is enabled.
> 
> Changes since v7:
> - typo fixes
> - use LIST_HEAD and DEFINE_RWLOCK
> - add Jens R-b and Julien A-b
> 
> Changes since v6:
> - use a rwlock to protect access to the chain list of context
> - rebase on top of staging
> - add some R-b/A-b from Jens and Julien
> 
> Changes since v5:
> - coding style fixes
> - rework version negociation to use the context lock
> - split probe into fw and vm to vm probe to make code clearer
> - add some R-b from Jens
> 
> Changes since v4:
> - fix typos and optimize command line parameter
> - split VM to VM support in 2 patches to ease review
> - organize ffa contexts in a chain list to be able to build the partinfo
>    result without taking the global domain lock
> - introduce a maximum number of SPs to prevent holding the CPU for too
>    long during partinfo call
> - use an atomic to store the number of FF-A VMs
> - prevent potential overflows in indirect message handling
> - fix copy bug in indirect message introduced in v4
> 
> Changes since v3:
> - reintroduce firmare v1.0 support in partinfo
> - fix a possible TOC/TOU issue in indirect message handling
> - typos and small fixes
> 
> Changes since v2:
> - Rework partition_info_get implementation
> - Taint Xen and display a message when VM to VM is enabled
> - Various fixes explained in each patch
> 
> Changes since v1 (rfc):
> - add a tee command line parameter
> - use IS_ENABLED instead of ifdef when possible
> - rebase on latest staging
> 
> 
> Bertrand Marquis (6):
>    xen/arm: Create tee command line parameter
>    xen/arm: ffa: Rework partinfo_get implementation
>    xen/arm: ffa: Introduce VM to VM support
>    xen/arm: ffa: Add buffer full notification support
>    xen/arm: ffa: Add indirect message between VM
>    xen/arm: ffa: Enable VM to VM without firmware

I merged the series.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v2] xen/arm: irq: add missing spin_unlock() in
 init_local_irq_data() error path
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From: Julien Grall 
To: Mykola Kvach , xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Denis Mukhin 
References: 
 <1a51ba8c-93c5-4cfb-b76e-26e318c0b22d@xen.org>
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On 11/08/2025 18:28, Julien Grall wrote:
> Hi Mykola,
> 
> On 11/08/2025 09:45, Mykola Kvach wrote:
>> From: Mykola Kvach 
>>
>> If init_one_irq_desc() fails, init_local_irq_data() returns without
>> releasing local_irqs_type_lock, leading to a possible deadlock.
>>
>> Release the lock before returning to ensure proper cleanup.
>>
>> Fixes: 2bb32b809250 ("xen/irq: Propagate the error from 
>> init_one_desc_irq() in init_*_irq_data()")
>> Signed-off-by: Mykola Kvach 
>> Reviewed-by: Denis Mukhin 
> 
> Acked-by: Julien Grall 
> 
> I will commit the patch soon.

This is now merged.

Cheers,

-- 
Julien Grall



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Date: Tue, 12 Aug 2025 12:07:58 +0100
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Subject: Re: [PATCH v3] xen/dom0less: arm: fix hwdom 1:1 low memory allocation
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To: Grygorii Strashko ,
 "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Volodymyr Babchuk ,
 Denis Mukhin , Jason Andryuk ,
 Julien Grall 
References: <20250807100323.513384-1-grygorii_strashko@epam.com>
From: Julien Grall 
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Hi Grygorii,

On 07/08/2025 11:03, Grygorii Strashko wrote:
> From: Grygorii Strashko 
> 
> Call stack for dom0less hwdom case (1:1) memory:
> create_domUs
> |-construct_domU
>    |-construct_hwdom()
>      |-allocate_memory_11()
> 
> And allocate_memory_11() uses "dom0_mem" as:
> min_low_order =
>    get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128)));
> 
> In case of dom0less boot the "dom0_mem" is not used and defaulted to 0,
> which causes min_low_order to get high value > order and so no allocations
> happens from low memory.
> 
> Fix it, by using kinfo->unassigned_mem instead of "dom0_mem" which has
> correct memory size in both cases: regular dom0 boot and dom0less boot.
> 
> Fixes: 52cb53f1816a ("xen/arm: dom0less hwdom construction")
> Signed-off-by: Grygorii Strashko 
> Reviewed-by: Denis Mukhin 
> Reviewed-by: Jason Andryuk 
> Acked-by: Julien Grall 

I have now committed the patch.

Cheers,

-- 
Julien Grall



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CC: Luca Fancellu , Stefano Stabellini
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Date: Tue, 12 Aug 2025 12:13:42 +0100
From: Mark Rutland 
To: Jinjie Ruan 
Cc: catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com,
	sstabellini@kernel.org, puranjay@kernel.org, broonie@kernel.org,
	mbenes@suse.cz, ryan.roberts@arm.com, akpm@linux-foundation.org,
	chenl311@chinatelecom.cn, ada.coupriediaz@arm.com,
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	liaochang1@huawei.com, ardb@kernel.org, leitao@debian.org,
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH -next v7 5/7] arm64: entry: Refactor
 preempt_schedule_irq() check code
Message-ID: 
References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 <20250729015456.3411143-6-ruanjinjie@huawei.com>
MIME-Version: 1.0
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In-Reply-To: <20250729015456.3411143-6-ruanjinjie@huawei.com>

On Tue, Jul 29, 2025 at 09:54:54AM +0800, Jinjie Ruan wrote:
> ARM64 requires an additional check whether to reschedule on return
> from interrupt. So add arch_irqentry_exit_need_resched() as the default
> NOP implementation and hook it up into the need_resched() condition in
> raw_irqentry_exit_cond_resched(). This allows ARM64 to implement
> the architecture specific version for switching over to
> the generic entry code.
> 
> To align the structure of the code with irqentry_exit_cond_resched()
> from the generic entry code, hoist the need_irq_preemption()
> and IS_ENABLED() check earlier. And different preemption check functions
> are defined based on whether dynamic preemption is enabled.
> 
> Suggested-by: Mark Rutland 
> Suggested-by: Kevin Brodsky 
> Suggested-by: Thomas Gleixner 
> Signed-off-by: Jinjie Ruan 
> ---
>  arch/arm64/include/asm/preempt.h |  4 ++++
>  arch/arm64/kernel/entry-common.c | 35 ++++++++++++++++++--------------
>  kernel/entry/common.c            | 16 ++++++++++++++-
>  3 files changed, 39 insertions(+), 16 deletions(-)

Can you please split the change to kernel/entry/common.c into a separate
patch? That doesn't depend on the arm64-specific changes, and it'll make
it easier to handle any conflcits when merging this.

Mark.

> 
> diff --git a/arch/arm64/include/asm/preempt.h b/arch/arm64/include/asm/preempt.h
> index 0159b625cc7f..0f0ba250efe8 100644
> --- a/arch/arm64/include/asm/preempt.h
> +++ b/arch/arm64/include/asm/preempt.h
> @@ -85,6 +85,7 @@ static inline bool should_resched(int preempt_offset)
>  void preempt_schedule(void);
>  void preempt_schedule_notrace(void);
>  
> +void raw_irqentry_exit_cond_resched(void);
>  #ifdef CONFIG_PREEMPT_DYNAMIC
>  
>  DECLARE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
> @@ -92,11 +93,14 @@ void dynamic_preempt_schedule(void);
>  #define __preempt_schedule()		dynamic_preempt_schedule()
>  void dynamic_preempt_schedule_notrace(void);
>  #define __preempt_schedule_notrace()	dynamic_preempt_schedule_notrace()
> +void dynamic_irqentry_exit_cond_resched(void);
> +#define irqentry_exit_cond_resched()	dynamic_irqentry_exit_cond_resched()
>  
>  #else /* CONFIG_PREEMPT_DYNAMIC */
>  
>  #define __preempt_schedule()		preempt_schedule()
>  #define __preempt_schedule_notrace()	preempt_schedule_notrace()
> +#define irqentry_exit_cond_resched()	raw_irqentry_exit_cond_resched()
>  
>  #endif /* CONFIG_PREEMPT_DYNAMIC */
>  #endif /* CONFIG_PREEMPTION */
> diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
> index 7c2299c1ba79..4f92664fd46c 100644
> --- a/arch/arm64/kernel/entry-common.c
> +++ b/arch/arm64/kernel/entry-common.c
> @@ -285,19 +285,8 @@ static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs,
>  		lockdep_hardirqs_on(CALLER_ADDR0);
>  }
>  
> -#ifdef CONFIG_PREEMPT_DYNAMIC
> -DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
> -#define need_irq_preemption() \
> -	(static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
> -#else
> -#define need_irq_preemption()	(IS_ENABLED(CONFIG_PREEMPTION))
> -#endif
> -
>  static inline bool arm64_preempt_schedule_irq(void)
>  {
> -	if (!need_irq_preemption())
> -		return false;
> -
>  	/*
>  	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
>  	 * priority masking is used the GIC irqchip driver will clear DAIF.IF
> @@ -672,6 +661,24 @@ static __always_inline void __el1_pnmi(struct pt_regs *regs,
>  	arm64_exit_nmi(regs, state);
>  }
>  
> +void raw_irqentry_exit_cond_resched(void)
> +{
> +	if (!preempt_count()) {
> +		if (need_resched() && arm64_preempt_schedule_irq())
> +			preempt_schedule_irq();
> +	}
> +}
> +
> +#ifdef CONFIG_PREEMPT_DYNAMIC
> +DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
> +void dynamic_irqentry_exit_cond_resched(void)
> +{
> +	if (!static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
> +		return;
> +	raw_irqentry_exit_cond_resched();
> +}
> +#endif
> +
>  static __always_inline void __el1_irq(struct pt_regs *regs,
>  				      void (*handler)(struct pt_regs *))
>  {
> @@ -681,10 +688,8 @@ static __always_inline void __el1_irq(struct pt_regs *regs,
>  	do_interrupt_handler(regs, handler);
>  	irq_exit_rcu();
>  
> -	if (!preempt_count() && need_resched()) {
> -		if (arm64_preempt_schedule_irq())
> -			preempt_schedule_irq();
> -	}
> +	if (IS_ENABLED(CONFIG_PREEMPTION))
> +		irqentry_exit_cond_resched();
>  
>  	exit_to_kernel_mode(regs, state);
>  }
> diff --git a/kernel/entry/common.c b/kernel/entry/common.c
> index b82032777310..4aa9656fa1b4 100644
> --- a/kernel/entry/common.c
> +++ b/kernel/entry/common.c
> @@ -142,6 +142,20 @@ noinstr irqentry_state_t irqentry_enter(struct pt_regs *regs)
>  	return ret;
>  }
>  
> +/**
> + * arch_irqentry_exit_need_resched - Architecture specific need resched function
> + *
> + * Invoked from raw_irqentry_exit_cond_resched() to check if need resched.
> + * Defaults return true.
> + *
> + * The main purpose is to permit arch to skip preempt a task from an IRQ.
> + */
> +static inline bool arch_irqentry_exit_need_resched(void);
> +
> +#ifndef arch_irqentry_exit_need_resched
> +static inline bool arch_irqentry_exit_need_resched(void) { return true; }
> +#endif
> +
>  void raw_irqentry_exit_cond_resched(void)
>  {
>  	if (!preempt_count()) {
> @@ -149,7 +163,7 @@ void raw_irqentry_exit_cond_resched(void)
>  		rcu_irq_exit_check_preempt();
>  		if (IS_ENABLED(CONFIG_DEBUG_ENTRY))
>  			WARN_ON_ONCE(!on_thread_stack());
> -		if (need_resched())
> +		if (need_resched() && arch_irqentry_exit_need_resched())
>  			preempt_schedule_irq();
>  	}
>  }
> -- 
> 2.34.1
> 


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Subject: Re: [PATCH v1 3/3] xen/pci: add discovered PCI device at boot
To: Mykyta Poturai 
Cc: Luca Fancellu ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "xen-devel@lists.xenproject.org" 
References: 
 <5097b76acf0a5c64cc78522f6af6233370c948e6.1753968306.git.mykyta_poturai@epam.com>
 <123626b4-3234-40e5-b1cf-bd5c2b19cbc8@suse.com>
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From: Jan Beulich 
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On 12.08.2025 13:09, Mykyta Poturai wrote:
> On 04.08.25 11:35, Jan Beulich wrote:
>> On 01.08.2025 11:22, Mykyta Poturai wrote:
>>> Create add_discovered_pci_devices function that calls pci_device_add
>>> on every PCI device discovered.
>>> The devices will be added to dom_io so that they can be assigned
>>> later to other domains.
>>
>> And why's the intermediate step necessary? IOW can't they be assigned to their
>> target domains right away, and only whatever's left would go to DOM_IO?
> 
> For Dom0less case, guest domains are not yet created at this point.

I understand that, but this doesn't answer my question. Once the guest domains
are there, can't you directly assign their devices to them?

>>> --- a/xen/drivers/passthrough/pci.c
>>> +++ b/xen/drivers/passthrough/pci.c
>>> @@ -1180,6 +1180,34 @@ int __init scan_pci_devices(void)
>>>       return ret;
>>>   }
>>>   
>>> +static int __init _add_discovered_pci_devices(struct pci_seg *pseg, void *arg)
>>> +{
>>> +    struct pci_dev *pdev;
>>> +    int ret = 0;
>>> +
>>> +    list_for_each_entry ( pdev, &pseg->alldevs_list, alldevs_list )
>>> +    {
>>> +        ret = pci_add_device(dom_io, pdev->seg, pdev->bus, pdev->devfn, NULL,
>>> +                             NUMA_NO_NODE);
>>> +        if ( ret < 0 )
>>> +        {
>>> +            printk(XENLOG_ERR
>>> +                   "%pp: Failure adding the discovered pci device (Error %d)\n",
>>> +                   &pdev->sbdf, ret);
>>> +            break;
>>> +        }
>>> +    }
>>> +
>>> +    return ret;
>>> +}
>>> +
>>> +void __init add_discovered_pci_devices(void)
>>> +{
>>> +    pcidevs_lock();
>>> +    pci_segments_iterate(_add_discovered_pci_devices, NULL);
>>> +    pcidevs_unlock();
>>> +}
>>
>> This looks to merely be a specialized form of what ...
>>
>>>   struct setup_hwdom {
>>>       struct domain *d;
>>>       int (*handler)(uint8_t devfn, struct pci_dev *pdev);
>>
>> ... follows below here. By generalizing what we have (perhaps from the top, i.e.
>> iommu_hwdom_init()), you'd also avoid violating Misra rule 2.1 on x86, as you add
>> unreachable code there.
> 
> Can you please elaborate a little further on how you see this 
> generalization? With routines you mentioned being specifically for 
> hwdom, which may not exist,

That's precisely the generalization I'm having in mind. What's hwdom-only
now ought to be possible to be made usable in wider manner.

> and the different approaches to PCI 
> initialization on Arm/x86 (as far as I understand on x86 all of the PCI 
> related stuff is initialized from iommu helpers, while Arm has a 
> dedicated init step)

This, too, may want harmonizing.

> I am afraid I can't find a nice point of contact to 
> generalize this, but I can be missing somthing due to unfamiliarity with 
> x86 code.
> 
> Another way of addressing possible MISRA violation I can see is moving 
> the add_discovered_pci_devices to xen/arch/arm/pci/pci.c so it will only 
> be compiled when used.

And pose a problem when e.g. RISC-V also wants the same.

Jan


From xen-devel-bounces@lists.xenproject.org Tue Aug 12 11:19:41 2025
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Date: Tue, 12 Aug 2025 12:19:30 +0100
From: Mark Rutland 
To: Jinjie Ruan 
Cc: catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com,
	sstabellini@kernel.org, puranjay@kernel.org, broonie@kernel.org,
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	xen-devel@lists.xenproject.org
Subject: Re: [PATCH -next v7 0/7] arm64: entry: Convert to generic irq entry
Message-ID: 
References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
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Hi,

This is looking pretty good now, thanks for continuing to work on this!

I've left a couple of minor comments, and Ada has left a few more. If
you're able to address those and respin atop v6.17-rc1, I think we can
start figuring out how to queue this.

Mark.

On Tue, Jul 29, 2025 at 09:54:49AM +0800, Jinjie Ruan wrote:
> Currently, x86, Riscv, Loongarch use the generic entry. Also convert
> arm64 to use the generic entry infrastructure from kernel/entry/*.
> The generic entry makes maintainers' work easier and codes more elegant,
> which will make PREEMPT_DYNAMIC and PREEMPT_LAZY use the generic entry
> common code and remove a lot of duplicate code.
> 
> Since commit a70e9f647f50 ("entry: Split generic entry into generic
> exception and syscall entry") split the generic entry into generic irq
> entry and generic syscall entry, it is time to convert arm64 to use
> the generic irq entry. And ARM64 will be completely converted to generic
> entry in the upcoming patch series.
> 
> The main convert steps are as follows:
> - Split generic entry into generic irq entry and generic syscall to
>   make the single patch more concentrated in switching to one thing.
> - Make arm64 easier to use irqentry_enter/exit().
> - Make arm64 closer to the PREEMPT_DYNAMIC code of generic entry.
> - Switch to generic irq entry.
> 
> It was tested ok with following test cases on QEMU virt platform:
>  - Perf tests.
>  - Different `dynamic preempt` mode switch.
>  - Pseudo NMI tests.
>  - Stress-ng CPU stress test.
>  - MTE test case in Documentation/arch/arm64/memory-tagging-extension.rst
>    and all test cases in tools/testing/selftests/arm64/mte/*.
> 
> The test QEMU configuration is as follows:
> 
> 	qemu-system-aarch64 \
> 		-M virt,gic-version=3,virtualization=on,mte=on \
> 		-cpu max,pauth-impdef=on \
> 		-kernel Image \
> 		-smp 8,sockets=1,cores=4,threads=2 \
> 		-m 512m \
> 		-nographic \
> 		-no-reboot \
> 		-device virtio-rng-pci \
> 		-append "root=/dev/vda rw console=ttyAMA0 kgdboc=ttyAMA0,115200 \
> 			earlycon preempt=voluntary irqchip.gicv3_pseudo_nmi=1" \
> 		-drive if=none,file=images/rootfs.ext4,format=raw,id=hd0 \
> 		-device virtio-blk-device,drive=hd0 \
> 
> Changes in v7:
> - Rebased on v6.16-rc7 and remove the merged first patch.
> - Update the commit message.
> 
> Changes in v6:
> - Rebased on 6.14 rc2 next.
> - Put the syscall bits aside and split it out.
> - Have the split patch before the arm64 changes.
> - Merge some tightly coupled patches.
> - Adjust the order of some patches to make them more reasonable.
> - Define regs_irqs_disabled() by inline function.
> - Define interrupts_enabled() in terms of regs_irqs_disabled().
> - Delete the fast_interrupts_enabled() macro.
> - irqentry_state_t -> arm64_irqentry_state_t.
> - Remove arch_exit_to_user_mode_prepare() and pull local_daif_mask() later
>   in the arm64 exit sequence
> - Update the commit message.
> 
> Changes in v5:
> - Not change arm32 and keep inerrupts_enabled() macro for gicv3 driver.
> - Move irqentry_state definition into arch/arm64/kernel/entry-common.c.
> - Avoid removing the __enter_from_*() and __exit_to_*() wrappers.
> - Update "irqentry_state_t ret/irq_state" to "state"
>   to keep it consistently.
> - Use generic irq entry header for PREEMPT_DYNAMIC after split
>   the generic entry.
> - Also refactor the ARM64 syscall code.
> - Introduce arch_ptrace_report_syscall_entry/exit(), instead of
>   arch_pre/post_report_syscall_entry/exit() to simplify code.
> - Make the syscall patches clear separation.
> - Update the commit message.
> 
> Changes in v4:
> - Rework/cleanup split into a few patches as Mark suggested.
> - Replace interrupts_enabled() macro with regs_irqs_disabled(), instead
>   of left it here.
> - Remove rcu and lockdep state in pt_regs by using temporary
>   irqentry_state_t as Mark suggested.
> - Remove some unnecessary intermediate functions to make it clear.
> - Rework preempt irq and PREEMPT_DYNAMIC code
>   to make the switch more clear.
> - arch_prepare_*_entry/exit() -> arch_pre_*_entry/exit().
> - Expand the arch functions comment.
> - Make arch functions closer to its caller.
> - Declare saved_reg in for block.
> - Remove arch_exit_to_kernel_mode_prepare(), arch_enter_from_kernel_mode().
> - Adjust "Add few arch functions to use generic entry" patch to be
>   the penultimate.
> - Update the commit message.
> - Add suggested-by.
> 
> Changes in v3:
> - Test the MTE test cases.
> - Handle forget_syscall() in arch_post_report_syscall_entry()
> - Make the arch funcs not use __weak as Thomas suggested, so move
>   the arch funcs to entry-common.h, and make arch_forget_syscall() folded
>   in arch_post_report_syscall_entry() as suggested.
> - Move report_single_step() to thread_info.h for arm64
> - Change __always_inline() to inline, add inline for the other arch funcs.
> - Remove unused signal.h for entry-common.h.
> - Add Suggested-by.
> - Update the commit message.
> 
> Changes in v2:
> - Add tested-by.
> - Fix a bug that not call arch_post_report_syscall_entry() in
>   syscall_trace_enter() if ptrace_report_syscall_entry() return not zero.
> - Refactor report_syscall().
> - Add comment for arch_prepare_report_syscall_exit().
> - Adjust entry-common.h header file inclusion to alphabetical order.
> - Update the commit message.
> 
> Jinjie Ruan (7):
>   arm64: ptrace: Replace interrupts_enabled() with regs_irqs_disabled()
>   arm64: entry: Refactor the entry and exit for exceptions from EL1
>   arm64: entry: Rework arm64_preempt_schedule_irq()
>   arm64: entry: Use preempt_count() and need_resched() helper
>   arm64: entry: Refactor preempt_schedule_irq() check code
>   arm64: entry: Move arm64_preempt_schedule_irq() into
>     __exit_to_kernel_mode()
>   arm64: entry: Switch to generic IRQ entry
> 
>  arch/arm64/Kconfig                    |   1 +
>  arch/arm64/include/asm/daifflags.h    |   2 +-
>  arch/arm64/include/asm/entry-common.h |  56 ++++
>  arch/arm64/include/asm/preempt.h      |   2 -
>  arch/arm64/include/asm/ptrace.h       |  13 +-
>  arch/arm64/include/asm/xen/events.h   |   2 +-
>  arch/arm64/kernel/acpi.c              |   2 +-
>  arch/arm64/kernel/debug-monitors.c    |   2 +-
>  arch/arm64/kernel/entry-common.c      | 411 +++++++++-----------------
>  arch/arm64/kernel/sdei.c              |   2 +-
>  arch/arm64/kernel/signal.c            |   3 +-
>  kernel/entry/common.c                 |  16 +-
>  12 files changed, 217 insertions(+), 295 deletions(-)
>  create mode 100644 arch/arm64/include/asm/entry-common.h
> 
> -- 
> 2.34.1
> 


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Message-ID: <923d76de-2849-4496-b1e6-c1362e007696@gmail.com>
Date: Tue, 12 Aug 2025 13:42:55 +0200
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From: Oleksii Kurochko 
Subject: Re: [PATCH v3 19/20] xen/riscv: add support of page lookup by GFN
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <24bb8ca6ad9d325f48d0c64b0fa461db5f0d0cc5.1753973161.git.oleksii.kurochko@gmail.com>
 
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On 8/11/25 3:25 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> Introduce helper functions for safely querying the P2M (physical-to-machine)
>> mapping:
>>   - add p2m_read_lock(), p2m_read_unlock(), and p2m_is_locked() for managing
>>     P2M lock state.
>>   - Implement p2m_get_entry() to retrieve mapping details for a given GFN,
>>     including MFN, page order, and validity.
>>   - Add p2m_lookup() to encapsulate read-locked MFN retrieval.
>>   - Introduce p2m_get_page_from_gfn() to convert a GFN into a page_info
>>     pointer, acquiring a reference to the page if valid.
>>   - Introduce get_page().
>>
>> Implementations are based on Arm's functions with some minor modifications:
>> - p2m_get_entry():
>>    - Reverse traversal of page tables, as RISC-V uses the opposite level
>>      numbering compared to Arm.
>>    - Removed the return of p2m_access_t from p2m_get_entry() since
>>      mem_access_settings is not introduced for RISC-V.
>>    - Updated BUILD_BUG_ON() to check using the level 0 mask, which corresponds
>>      to Arm's THIRD_MASK.
>>    - Replaced open-coded bit shifts with the BIT() macro.
>>    - Other minor changes, such as using RISC-V-specific functions to validate
>>      P2M PTEs, and replacing Arm-specific GUEST_* macros with their RISC-V
>>      equivalents.
>>
>> Signed-off-by: Oleksii Kurochko
>> ---
>> Changes in V3:
>>   - Add is_p2m_foreign() macro and connected stuff.
> What is this about?

Sorry for that, it is a stale change. I will drop it in the next patch version.

>> --- a/xen/arch/riscv/include/asm/p2m.h
>> +++ b/xen/arch/riscv/include/asm/p2m.h
>> @@ -202,6 +202,24 @@ static inline int p2m_is_write_locked(struct p2m_domain *p2m)
>>   
>>   unsigned long construct_hgatp(struct p2m_domain *p2m, uint16_t vmid);
>>   
>> +static inline void p2m_read_lock(struct p2m_domain *p2m)
>> +{
>> +    read_lock(&p2m->lock);
>> +}
>> +
>> +static inline void p2m_read_unlock(struct p2m_domain *p2m)
>> +{
>> +    read_unlock(&p2m->lock);
>> +}
>> +
>> +static inline int p2m_is_locked(struct p2m_domain *p2m)
> bool return type (also for p2m_is_write_locked() in patch 11)? Also perhaps
> pointer-to-const parameter?

I haven't checked what is a argument type of rw_is_locked() inside, so, automatically
use just pointer parameter, but now I see that it could be really const.

>> --- a/xen/arch/riscv/p2m.c
>> +++ b/xen/arch/riscv/p2m.c
>> @@ -852,3 +852,139 @@ int map_regions_p2mt(struct domain *d,
>>   {
>>       return p2m_insert_mapping(p2m_get_hostp2m(d), gfn, nr, mfn, p2mt);
>>   }
>> +
>> +/*
>> + * Get the details of a given gfn.
>> + *
>> + * If the entry is present, the associated MFN will be returned type filled up.
> This sentence doesn't really parse, perhaps due to missing words.

IDK what happened but it should be:
   ... the associated MFN will returned and type filled up ...
Perhpaps, it would be better just:
   ... the associated MFN will returned and the p2m type of the mapping.
   (or just entry's type)

>> + * The page_order will correspond to the order of the mapping in the page
>> + * table (i.e it could be a superpage).
>> + *
>> + * If the entry is not present, INVALID_MFN will be returned and the
>> + * page_order will be set according to the order of the invalid range.
>> + *
>> + * valid will contain the value of bit[0] (e.g valid bit) of the
>> + * entry.
>> + */
>> +static mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn,
>> +                           p2m_type_t *t,
>> +                           unsigned int *page_order,
>> +                           bool *valid)
>> +{
>> +    unsigned int level = 0;
>> +    pte_t entry, *table;
>> +    int rc;
>> +    mfn_t mfn = INVALID_MFN;
>> +    DECLARE_OFFSETS(offsets, gfn_to_gaddr(gfn));
>> +
>> +    ASSERT(p2m_is_locked(p2m));
>> +    BUILD_BUG_ON(XEN_PT_LEVEL_MAP_MASK(0) != PAGE_MASK);
> What function-wide property is this check about? Even when moved ...

I think this check isn't needed anymore.

This check is/was needed to be sure that 4k page(s) are used on L3 (in Arm terms)
mapping as Arm can support 4k, 16k and 64k.
Initially this check derived from:
   https://lore.kernel.org/xen-devel/1402394278-9850-4-git-send-email-ian.campbell@citrix.com/
And it was needed because of the way how maddr is calculated, calculation for which
could be wrong if page size isn't 4k.
But then this check was migrated to p2m_get_entry():
   https://lore.kernel.org/xen-devel/1469717505-8026-13-git-send-email-julien.grall@arm.com/
But the way how maddr is got isn't depends on mask and PAGE_MASK, and I don't see any other
reason to why BUILD_BUG_ON() is needed now.

>
>> +    if ( valid )
>> +        *valid = false;
>> +
>> +    /* XXX: Check if the mapping is lower than the mapped gfn */
> (Nested: What is this about?)
>
>> +    /* This gfn is higher than the highest the p2m map currently holds */
>> +    if ( gfn_x(gfn) > gfn_x(p2m->max_mapped_gfn) )
>> +    {
>> +        for ( level = P2M_ROOT_LEVEL; level; level-- )
>> +            if ( (gfn_x(gfn) & (XEN_PT_LEVEL_MASK(level) >> PAGE_SHIFT)) >
> ... into the more narrow scope where another XEN_PT_LEVEL_MASK() exists I
> can't really spot what the check is to guard against.
>
>> +                 gfn_x(p2m->max_mapped_gfn) )
>> +                break;
>> +
>> +        goto out;
>> +    }
>> +
>> +    table = p2m_get_root_pointer(p2m, gfn);
>> +
>> +    /*
>> +     * the table should always be non-NULL because the gfn is below
>> +     * p2m->max_mapped_gfn and the root table pages are always present.
>> +     */
> Nit: Style.
>
>> +    if ( !table )
>> +    {
>> +        ASSERT_UNREACHABLE();
>> +        level = P2M_ROOT_LEVEL;
>> +        goto out;
>> +    }
>> +
>> +    for ( level = P2M_ROOT_LEVEL; level; level-- )
>> +    {
>> +        rc = p2m_next_level(p2m, true, level, &table, offsets[level]);
> Why would you blindly allocate a page table (hierarchy) here? If anything,
> this may need doing upon caller request (as it's only up the call chain
> where the necessary knowledge exists).

I wanted to set it to always|false|, as based on the name|p2m_get_entry()|,
it is expected that the page tables are already allocated.

> For example, ...
>
>> +static mfn_t p2m_lookup(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t)
>> +{
>> +    mfn_t mfn;
>> +
>> +    p2m_read_lock(p2m);
>> +    mfn = p2m_get_entry(p2m, gfn, t, NULL, NULL);
> ... this (by its name) pretty likely won't want allocation, while ...
>
>> +    p2m_read_unlock(p2m);
>> +
>> +    return mfn;
>> +}
>> +
>> +struct page_info *p2m_get_page_from_gfn(struct p2m_domain *p2m, gfn_t gfn,
>> +                                        p2m_type_t *t)
>> +{
> ... this will. Yet then ...

I didn't really get why p2m_get_page_from_gfn() is expected to allocate
page table. My understanding is that GFN will point to a page only if
a mapping was done before for the GFN.

>
>> +    struct page_info *page;
>> +    p2m_type_t p2mt = p2m_invalid;
>> +    mfn_t mfn = p2m_lookup(p2m, gfn, t);
> ... you use the earlier one here.

We don't need|page_order| and/or the valid bit in|p2m_get_page_from_gfn()|.

>
>> +    if ( !mfn_valid(mfn) )
>> +        return NULL;
>> +
>> +    if ( t )
>> +        p2mt = *t;
>> +
>> +    page = mfn_to_page(mfn);
>> +
>> +    /*
>> +     * get_page won't work on foreign mapping because the page doesn't
>> +     * belong to the current domain.
>> +     */
>> +    if ( p2m_is_foreign(p2mt) )
>> +    {
>> +        struct domain *fdom = page_get_owner_and_reference(page);
>> +        ASSERT(fdom != NULL);
>> +        ASSERT(fdom != p2m->domain);
>> +        return page;
> In a release build (with no assertions) this will be wrong if either of the
> two condition would not be satisfied. See x86'es respective code.

I will add the following then instead:
     if ( unlikely(p2m_is_foreign(t)) )
     {
         const struct domain *fdom = page_get_owner_and_reference(page);

         if ( fdom )
         {
             if ( likely(fdom != d) )
                 return page;
             ASSERT_UNREACHABLE();
             put_page(page);
         }

         return NULL;
     }

I'm not sure that unlikely() is needed, x86 has it.
It seems then Arm needs such a change too.

Thanks.

~ Oleksii


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    On 8/11/25 3:25 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    Introduce helper functions for safely querying the P2M (physical-to-machine)
mapping:
 - add p2m_read_lock(), p2m_read_unlock(), and p2m_is_locked() for managing
   P2M lock state.
 - Implement p2m_get_entry() to retrieve mapping details for a given GFN,
   including MFN, page order, and validity.
 - Add p2m_lookup() to encapsulate read-locked MFN retrieval.
 - Introduce p2m_get_page_from_gfn() to convert a GFN into a page_info
   pointer, acquiring a reference to the page if valid.
 - Introduce get_page().

Implementations are based on Arm's functions with some minor modifications:
- p2m_get_entry():
  - Reverse traversal of page tables, as RISC-V uses the opposite level
    numbering compared to Arm.
  - Removed the return of p2m_access_t from p2m_get_entry() since
    mem_access_settings is not introduced for RISC-V.
  - Updated BUILD_BUG_ON() to check using the level 0 mask, which corresponds
    to Arm's THIRD_MASK.
  - Replaced open-coded bit shifts with the BIT() macro.
  - Other minor changes, such as using RISC-V-specific functions to validate
    P2M PTEs, and replacing Arm-specific GUEST_* macros with their RISC-V
    equivalents.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
Changes in V3:
 - Add is_p2m_foreign() macro and connected stuff.

    
      
    
      
    What is this about?
    
    
    
    
    Sorry for that, it is a stale change. I will drop it in the next patch version.


    
    
    
      
    
        
    --- a/xen/arch/riscv/include/asm/p2m.h
+++ b/xen/arch/riscv/include/asm/p2m.h
@@ -202,6 +202,24 @@ static inline int p2m_is_write_locked(struct p2m_domain *p2m)
 
 unsigned long construct_hgatp(struct p2m_domain *p2m, uint16_t vmid);
 
+static inline void p2m_read_lock(struct p2m_domain *p2m)
+{
+    read_lock(&p2m->lock);
+}
+
+static inline void p2m_read_unlock(struct p2m_domain *p2m)
+{
+    read_unlock(&p2m->lock);
+}
+
+static inline int p2m_is_locked(struct p2m_domain *p2m)

    
      
    
      
    bool return type (also for p2m_is_write_locked() in patch 11)? Also perhaps
pointer-to-const parameter?
    
    
    
    
    I haven't checked what is a argument type of rw_is_locked() inside, so, automatically
use just pointer parameter, but now I see that it could be really const.


    
    
    
      
    
        
    --- a/xen/arch/riscv/p2m.c
+++ b/xen/arch/riscv/p2m.c
@@ -852,3 +852,139 @@ int map_regions_p2mt(struct domain *d,
 {
     return p2m_insert_mapping(p2m_get_hostp2m(d), gfn, nr, mfn, p2mt);
 }
+
+/*
+ * Get the details of a given gfn.
+ *
+ * If the entry is present, the associated MFN will be returned type filled up.

    
      
    
      
    This sentence doesn't really parse, perhaps due to missing words.
    
    
    
    
    IDK what happened but it should be:
  ... the associated MFN will returned and type filled up ...
Perhpaps, it would be better just:
  ... the associated MFN will returned and the p2m type of the mapping.
  (or just entry's type)


    
    
    
      
    
        
    + * The page_order will correspond to the order of the mapping in the page
+ * table (i.e it could be a superpage).
+ *
+ * If the entry is not present, INVALID_MFN will be returned and the
+ * page_order will be set according to the order of the invalid range.
+ *
+ * valid will contain the value of bit[0] (e.g valid bit) of the
+ * entry.
+ */
+static mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn,
+                           p2m_type_t *t,
+                           unsigned int *page_order,
+                           bool *valid)
+{
+    unsigned int level = 0;
+    pte_t entry, *table;
+    int rc;
+    mfn_t mfn = INVALID_MFN;
+    DECLARE_OFFSETS(offsets, gfn_to_gaddr(gfn));
+
+    ASSERT(p2m_is_locked(p2m));
+    BUILD_BUG_ON(XEN_PT_LEVEL_MAP_MASK(0) != PAGE_MASK);

    
      
    
      
    What function-wide property is this check about? Even when moved ...
    
    
    
    
    I think this check isn't needed anymore.

This check is/was needed to be sure that 4k page(s) are used on L3 (in Arm terms)
mapping as Arm can support 4k, 16k and 64k.
Initially this check derived from:
  https://lore.kernel.org/xen-devel/1402394278-9850-4-git-send-email-ian.campbell@citrix.com/
And it was needed because of the way how maddr is calculated, calculation for which
could be wrong if page size isn't 4k.
But then this check was migrated to p2m_get_entry():
  https://lore.kernel.org/xen-devel/1469717505-8026-13-git-send-email-julien.grall@arm.com/
But the way how maddr is got isn't depends on mask and PAGE_MASK, and I don't see any other
reason to why BUILD_BUG_ON() is needed now.


    
    
    
      
    

    
      
    
        
    +    if ( valid )
+        *valid = false;
+
+    /* XXX: Check if the mapping is lower than the mapped gfn */

    
      
    
      
    (Nested: What is this about?)


    
      
    
        
    +    /* This gfn is higher than the highest the p2m map currently holds */
+    if ( gfn_x(gfn) > gfn_x(p2m->max_mapped_gfn) )
+    {
+        for ( level = P2M_ROOT_LEVEL; level; level-- )
+            if ( (gfn_x(gfn) & (XEN_PT_LEVEL_MASK(level) >> PAGE_SHIFT)) >

    
      
    
      
    ... into the more narrow scope where another XEN_PT_LEVEL_MASK() exists I
can't really spot what the check is to guard against.


    
      
    
        
    +                 gfn_x(p2m->max_mapped_gfn) )
+                break;
+
+        goto out;
+    }
+
+    table = p2m_get_root_pointer(p2m, gfn);
+
+    /*
+     * the table should always be non-NULL because the gfn is below
+     * p2m->max_mapped_gfn and the root table pages are always present.
+     */

    
      
    
      
    Nit: Style.


    
      
    
        
    +    if ( !table )
+    {
+        ASSERT_UNREACHABLE();
+        level = P2M_ROOT_LEVEL;
+        goto out;
+    }
+
+    for ( level = P2M_ROOT_LEVEL; level; level-- )
+    {
+        rc = p2m_next_level(p2m, true, level, &table, offsets[level]);

    
      
    
      
    Why would you blindly allocate a page table (hierarchy) here? If anything,
this may need doing upon caller request (as it's only up the call chain
where the necessary knowledge exists). 
    
    
    
    
    I wanted to set it to always false, as based on the name p2m_get_entry(),
it is expected that the page tables are already allocated.


    
    
    
      
    For example, ...


    
      
    
        
    +static mfn_t p2m_lookup(struct p2m_domain *p2m, gfn_t gfn, p2m_type_t *t)
+{
+    mfn_t mfn;
+
+    p2m_read_lock(p2m);
+    mfn = p2m_get_entry(p2m, gfn, t, NULL, NULL);

    
      
    
      
    ... this (by its name) pretty likely won't want allocation, while ...


    
      
    
        
    +    p2m_read_unlock(p2m);
+
+    return mfn;
+}
+
+struct page_info *p2m_get_page_from_gfn(struct p2m_domain *p2m, gfn_t gfn,
+                                        p2m_type_t *t)
+{

    
      
    
      
    ... this will. Yet then ...
    
    
    
    
    I didn't really get why p2m_get_page_from_gfn() is expected to allocate
page table. My understanding is that GFN will point to a page only if
a mapping was done before for the GFN.


    
    
    
      
    

    
      
    
        
    +    struct page_info *page;
+    p2m_type_t p2mt = p2m_invalid;
+    mfn_t mfn = p2m_lookup(p2m, gfn, t);

    
      
    
      
    ... you use the earlier one here.
    
    
    
    
    We don't need page_order and/or the valid bit in p2m_get_page_from_gfn().


    
    
    
      
    

    
      
    
        
    +    if ( !mfn_valid(mfn) )
+        return NULL;
+
+    if ( t )
+        p2mt = *t;
+
+    page = mfn_to_page(mfn);
+
+    /*
+     * get_page won't work on foreign mapping because the page doesn't
+     * belong to the current domain.
+     */
+    if ( p2m_is_foreign(p2mt) )
+    {
+        struct domain *fdom = page_get_owner_and_reference(page);
+        ASSERT(fdom != NULL);
+        ASSERT(fdom != p2m->domain);
+        return page;

    
      
    
      
    In a release build (with no assertions) this will be wrong if either of the
two condition would not be satisfied. See x86'es respective code.
    
    
    
    
    I will add the following then instead:
    if ( unlikely(p2m_is_foreign(t)) )
    {
        const struct domain *fdom = page_get_owner_and_reference(page);

        if ( fdom )
        {
            if ( likely(fdom != d) )
                return page;
            ASSERT_UNREACHABLE();
            put_page(page);
        }

        return NULL;
    }

    
    
    I'm not sure that unlikely() is needed, x86 has it.
It seems then Arm needs such a change too.

Thanks.

~ Oleksii

    
    
    
  


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From:	Daniel Kiper 
To:	Aaron Rainbolt 
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Subject: Re: [PATCH v4 1/2] include/xen: Rename MAX_GUEST_CMDLINE to
 GRUB_XEN_MAX_GUEST_CMDLINE
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On Mon, Aug 04, 2025 at 11:49:11PM -0500, Aaron Rainbolt wrote:
> The xen.h header was using an overly generic name to refer to the
> maximum length of the command line passed from Xen to a guest. Rename it
> to avoid confusion or conflicts in the future.
>
> Signed-off-by: Aaron Rainbolt 

Reviewed-by: Daniel Kiper 

Daniel


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Subject: Re: [PATCH v3 20/20] xen/riscv: introduce metadata table to store P2M
 type
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <802d757c167121c0a5ae2e529f5a365f779c5e59.1753973161.git.oleksii.kurochko@gmail.com>
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On 8/11/25 5:44 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> RISC-V's PTE has only two available bits that can be used to store the P2M
>> type. This is insufficient to represent all the current RISC-V P2M types.
>> Therefore, some P2M types must be stored outside the PTE bits.
>>
>> To address this, a metadata table is introduced to store P2M types that
>> cannot fit in the PTE itself. Not all P2M types are stored in the
>> metadata table—only those that require it.
>>
>> The metadata table is linked to the intermediate page table via the
>> `struct page_info`'s list field of the corresponding intermediate page.
>>
>> To simplify the allocation and linking of intermediate and metadata page
>> tables, `p2m_{alloc,free}_table()` functions are implemented.
>>
>> These changes impact `p2m_split_superpage()`, since when a superpage is
>> split, it is necessary to update the metadata table of the new
>> intermediate page table — if the entry being split has its P2M type set
>> to `p2m_ext_storage` in its `P2M_TYPES` bits.
> Oh, this was an aspect I didn't realize when commenting on the name of
> the enumerator. I think you want to keep the name for the purpose here,
> but you better wouldn't apply relational operators to it (and hence
> have a second value to serve that purpose).

It could be done in this way, but I think that it would be better just to have
one value with a better name as I suggested in the reply to other patch.

>
>> In addition to updating
>> the metadata of the new intermediate page table, the corresponding entry
>> in the metadata for the original superpage is invalidated.
>>
>> Also, update p2m_{get,set}_type to work with P2M types which don't fit
>> into PTE bits.
>>
>> Signed-off-by: Oleksii Kurochko
> No Suggested-by: or anything?

Sorry for that, Suggested-by should be added here, I'll fix that in the
next patch series version.

>
>> --- a/xen/arch/riscv/include/asm/mm.h
>> +++ b/xen/arch/riscv/include/asm/mm.h
>> @@ -150,6 +150,15 @@ struct page_info
>>               /* Order-size of the free chunk this page is the head of. */
>>               unsigned int order;
>>           } free;
>> +
>> +        /* Page is used to store metadata: p2m type. */
> That's not correct. The page thus described is what the pointer below
> points to. Here it's more like "Page is used as an intermediate P2M
> page table".
>
>> +        struct {
>> +            /*
>> +             * Pointer to a page which store metadata for an intermediate page
>> +             * table.
>> +             */
>> +            struct page_info *metadata;
>> +        } md;
> In the description you say you would re-use the list field.

It was so in a first version of storing P2M type outside PTE bits, so, it is a
stale part of the commit message. I'll correct it.

>
>> --- a/xen/arch/riscv/p2m.c
>> +++ b/xen/arch/riscv/p2m.c
>> @@ -101,7 +101,16 @@ static int p2m_alloc_root_table(struct p2m_domain *p2m)
>>   {
>>       struct domain *d = p2m->domain;
>>       struct page_info *page;
>> -    const unsigned int nr_root_pages = P2M_ROOT_PAGES;
>> +    /*
>> +     * If the root page table starts at Level <= 2, and since only 1GB, 2MB,
>> +     * and 4KB mappings are supported (as enforced by the ASSERT() in
>> +     * p2m_set_entry()), it is necessary to allocate P2M_ROOT_PAGES for
>> +     * the root page table itself, plus an additional P2M_ROOT_PAGES for
>> +     * metadata storage. This is because only two free bits are available in
>> +     * the PTE, which are not sufficient to represent all possible P2M types.
>> +     */
>> +    const unsigned int nr_root_pages = P2M_ROOT_PAGES *
>> +                                       ((P2M_ROOT_LEVEL <= 2) ? 2 : 1);
>>   
>>       /*
>>        * Return back nr_root_pages to assure the root table memory is also
>> @@ -114,6 +123,23 @@ static int p2m_alloc_root_table(struct p2m_domain *p2m)
>>       if ( !page )
>>           return -ENOMEM;
>>   
>> +    if ( P2M_ROOT_LEVEL <= 2 )
>> +    {
>> +        /*
>> +         * In the case where P2M_ROOT_LEVEL <= 2, it is necessary to allocate
>> +         * a page of the same size as that used for the root page table.
>> +         * Therefore, p2m_allocate_root() can be safely reused.
>> +         */
>> +        struct page_info *metadata = p2m_allocate_root(d);
>> +        if ( !metadata )
>> +        {
>> +            free_domheap_pages(page, P2M_ROOT_ORDER);
>> +            return -ENOMEM;
>> +        }
>> +
>> +        page->v.md.metadata = metadata;
> Don't you need to install such a link for every one of the 4 pages?

Yes, I need to do that. Thanks.

>
>> @@ -198,24 +224,25 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
>>       return __map_domain_page(p2m->root + root_table_indx);
>>   }
>>   
>> -static int p2m_set_type(pte_t *pte, p2m_type_t t)
>> +static void p2m_set_type(pte_t *pte, const p2m_type_t t, const unsigned int i)
>>   {
>> -    int rc = 0;
>> -
>>       if ( t > p2m_ext_storage )
>> -        panic("unimplemeted\n");
>> +    {
>> +        ASSERT(pte);
>> +
>> +        pte[i].pte = t;
> What does i identify here?

An index in metadata page where P2M type for corresponding PTE is stored.
I will re-name it to metadata_indx for more clarity.

>
>> +    }
>>       else
>>           pte->pte |= MASK_INSR(t, P2M_TYPE_PTE_BITS_MASK);
>> -
>> -    return rc;
>>   }
>>   
>> -static p2m_type_t p2m_get_type(const pte_t pte)
>> +static p2m_type_t p2m_get_type(const pte_t pte, const pte_t *metadata,
>> +                               const unsigned int i)
>>   {
>>       p2m_type_t type = MASK_EXTR(pte.pte, P2M_TYPE_PTE_BITS_MASK);
>>   
>>       if ( type == p2m_ext_storage )
>> -        panic("unimplemented\n");
>> +        type = metadata[i].pte;
>>   
>>       return type;
>>   }
> Overall this feels pretty fragile, as the caller has to pass several values
> which all need to be in sync with one another. If you ...

Generally, agree it is fragile enough.

>
>> @@ -265,7 +292,10 @@ static void p2m_set_permission(pte_t *e, p2m_type_t t)
>>       }
>>   }
>>   
>> -static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
>> +static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t,
>> +                              struct page_info *metadata_pg,
>> +                              const unsigned int indx,
>> +                              bool is_table)
>>   {
>>       pte_t e = (pte_t) { PTE_VALID };
>>   
>> @@ -285,12 +315,21 @@ static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
>>   
>>       if ( !is_table )
>>       {
>> +        pte_t *metadata = __map_domain_page(metadata_pg);
> ... map the page anyway, no matter whether ...
>
>>           p2m_set_permission(&e, t);
>>   
>> +        metadata[indx].pte = p2m_invalid;
>> +
>>           if ( t < p2m_ext_storage )
>> -            p2m_set_type(&e, t);
>> +            p2m_set_type(&e, t, indx);
>>           else
>> -            panic("unimplemeted\n");
>> +        {
>> +            e.pte |= MASK_INSR(p2m_ext_storage, P2M_TYPE_PTE_BITS_MASK);
>> +            p2m_set_type(metadata, t, indx);
>> +        }
> ... you'll actually use it, maybe best to map both pages at the same point?

Only one page is mapped here (?) and it should be mapped here, I suppose, it could be a case
when a previous set type is overwritten, so, it could be needed to invalidate a type written
in metadata.

> And as said elsewhere, no, I don't think you want to use p2m_set_type() for
> two entirely different purposes.

I wasn't very happy too, but, at the same time I didn't want to have a prototype where
it isn't really clear when it is needed to pass metadata and where it is not. But considering
your comments then this one solution isn't good too. So maybe it would be better just have
two separate functions: p2m_set_pte_type() and p2m_set_metadata_type().

>
>> @@ -323,22 +364,71 @@ static struct page_info *p2m_alloc_page(struct p2m_domain *p2m)
>>       return pg;
>>   }
>>   
>> +static void p2m_free_page(struct p2m_domain *p2m, struct page_info *pg);
>> +
>> +/*
>> + * Allocate a page table with an additional extra page to store
>> + * metadata for each entry of the page table.
>> + * Link this metadata page to page table page's list field.
>> + */
>> +static struct page_info * p2m_alloc_table(struct p2m_domain *p2m)
> Nit: Stray blank after * again.
>
>> +{
>> +    enum table_type
>> +    {
>> +        INTERMEDIATE_TABLE=0,
> If you really think you need the "= 0", then please with blanks around '='.
>
>> +        /*
>> +         * At the moment, metadata is going to store P2M type
>> +         * for each PTE of page table.
>> +         */
>> +        METADATA_TABLE,
>> +        TABLE_MAX
>> +    };
>> +
>> +    struct page_info *tables[TABLE_MAX];
>> +
>> +    for ( unsigned int i = 0; i < TABLE_MAX; i++ )
>> +    {
>> +        tables[i] = p2m_alloc_page(p2m);
>> +
>> +        if ( !tables[i] )
>> +            goto out;
>> +
>> +        clear_and_clean_page(tables[i]);
>> +    }
>> +
>> +    tables[INTERMEDIATE_TABLE]->v.md.metadata = tables[METADATA_TABLE];
>> +
>> +    return tables[INTERMEDIATE_TABLE];
>> +
>> + out:
>> +    for ( unsigned int i = 0; i < TABLE_MAX; i++ )
>> +        if ( tables[i] )
> You didn't clear all of tables[] first, though.

Oh, right, i missed an initalizer for tables[] array.

>   This kind of cleanup is
> often better done as
>
>      while ( i-- > 0 )
>          ...
>
> You don't even need an if() then, as you know allocations succeeded for all
> earlier array slots.

Yes, it looks very nice.

>
>> +            p2m_free_page(p2m, tables[i]);
>> +
>> +    return NULL;
>> +}
> I'm also surprised you allocate the metadata table no matter whether you'll
> actually need it. That'll double your average paging pool usage, when in a
> typical case only very few entries would actually require this extra
> storage.

Nice point, we could really do a delayed allocation instead and allocate only
when requested P2M type is > p2m_ext_storage.
I'll implement that.

>
>> @@ -453,10 +543,9 @@ static void p2m_put_2m_superpage(mfn_t mfn, p2m_type_t type)
>>   }
>>   
>>   /* Put any references on the page referenced by pte. */
>> -static void p2m_put_page(const pte_t pte, unsigned int level)
>> +static void p2m_put_page(const pte_t pte, unsigned int level, p2m_type_t p2mt)
>>   {
>>       mfn_t mfn = pte_get_mfn(pte);
>> -    p2m_type_t p2m_type = p2m_get_type(pte);
>>   
>>       ASSERT(pte_is_valid(pte));
>>   
>> @@ -470,10 +559,10 @@ static void p2m_put_page(const pte_t pte, unsigned int level)
>>       switch ( level )
>>       {
>>       case 1:
>> -        return p2m_put_2m_superpage(mfn, p2m_type);
>> +        return p2m_put_2m_superpage(mfn, p2mt);
>>   
>>       case 0:
>> -        return p2m_put_4k_page(mfn, p2m_type);
>> +        return p2m_put_4k_page(mfn, p2mt);
>>       }
>>   }
> Might it be better to introduce this function in this shape right away, in
> the earlier patch?

Agree, probably, I did that intentionally, but I don't remember why. I will try to
avoid these changes in this patch as it looks unnecessary here.

>
>> @@ -690,18 +791,23 @@ static int p2m_set_entry(struct p2m_domain *p2m,
>>       {
>>           /* We need to split the original page. */
>>           pte_t split_pte = *entry;
>> +        struct page_info *metadata = virt_to_page(table)->v.md.metadata;
> This (or along these lines) is how I would have expected things to be done
> elsewhere as well, limiting the amount of arguments you need to pass
> around.

I will try to re-use this approach elsewhere I can.

Thanks.

~ Oleksii

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Content-Transfer-Encoding: 8bit



  
    
  
  
    

    
    
    
    
    On 8/11/25 5:44 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    RISC-V's PTE has only two available bits that can be used to store the P2M
type. This is insufficient to represent all the current RISC-V P2M types.
Therefore, some P2M types must be stored outside the PTE bits.

To address this, a metadata table is introduced to store P2M types that
cannot fit in the PTE itself. Not all P2M types are stored in the
metadata table—only those that require it.

The metadata table is linked to the intermediate page table via the
`struct page_info`'s list field of the corresponding intermediate page.

To simplify the allocation and linking of intermediate and metadata page
tables, `p2m_{alloc,free}_table()` functions are implemented.

These changes impact `p2m_split_superpage()`, since when a superpage is
split, it is necessary to update the metadata table of the new
intermediate page table — if the entry being split has its P2M type set
to `p2m_ext_storage` in its `P2M_TYPES` bits.

    
      
    
      
    Oh, this was an aspect I didn't realize when commenting on the name of
the enumerator. I think you want to keep the name for the purpose here,
but you better wouldn't apply relational operators to it (and hence
have a second value to serve that purpose).
    
    
    
    
    It could be done in this way, but I think that it would be better just to have
one value with a better name as I suggested in the reply to other patch.


    
    
    
      
    

    
      
    
        
    In addition to updating
the metadata of the new intermediate page table, the corresponding entry
in the metadata for the original superpage is invalidated.

Also, update p2m_{get,set}_type to work with P2M types which don't fit
into PTE bits.

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

    
      
    
      
    No Suggested-by: or anything?
    
    
    
    
    Sorry for that, Suggested-by should be added here, I'll fix that in the
next patch series version.


    
    
    
      
    

    
      
    
        
    --- a/xen/arch/riscv/include/asm/mm.h
+++ b/xen/arch/riscv/include/asm/mm.h
@@ -150,6 +150,15 @@ struct page_info
             /* Order-size of the free chunk this page is the head of. */
             unsigned int order;
         } free;
+
+        /* Page is used to store metadata: p2m type. */

    
      
    
      
    That's not correct. The page thus described is what the pointer below
points to. Here it's more like "Page is used as an intermediate P2M
page table".


    
      
    
        
    +        struct {
+            /*
+             * Pointer to a page which store metadata for an intermediate page
+             * table.
+             */
+            struct page_info *metadata;
+        } md;

    
      
    
      
    In the description you say you would re-use the list field.
    
    
    
    
    It was so in a first version of storing P2M type outside PTE bits, so, it is a 
stale part of the commit message. I'll correct it.


    
    
    
      
    

    
      
    
        
    --- a/xen/arch/riscv/p2m.c
+++ b/xen/arch/riscv/p2m.c
@@ -101,7 +101,16 @@ static int p2m_alloc_root_table(struct p2m_domain *p2m)
 {
     struct domain *d = p2m->domain;
     struct page_info *page;
-    const unsigned int nr_root_pages = P2M_ROOT_PAGES;
+    /*
+     * If the root page table starts at Level <= 2, and since only 1GB, 2MB,
+     * and 4KB mappings are supported (as enforced by the ASSERT() in
+     * p2m_set_entry()), it is necessary to allocate P2M_ROOT_PAGES for
+     * the root page table itself, plus an additional P2M_ROOT_PAGES for
+     * metadata storage. This is because only two free bits are available in
+     * the PTE, which are not sufficient to represent all possible P2M types.
+     */
+    const unsigned int nr_root_pages = P2M_ROOT_PAGES *
+                                       ((P2M_ROOT_LEVEL <= 2) ? 2 : 1);
 
     /*
      * Return back nr_root_pages to assure the root table memory is also
@@ -114,6 +123,23 @@ static int p2m_alloc_root_table(struct p2m_domain *p2m)
     if ( !page )
         return -ENOMEM;
 
+    if ( P2M_ROOT_LEVEL <= 2 )
+    {
+        /*
+         * In the case where P2M_ROOT_LEVEL <= 2, it is necessary to allocate
+         * a page of the same size as that used for the root page table.
+         * Therefore, p2m_allocate_root() can be safely reused.
+         */
+        struct page_info *metadata = p2m_allocate_root(d);
+        if ( !metadata )
+        {
+            free_domheap_pages(page, P2M_ROOT_ORDER);
+            return -ENOMEM;
+        }
+
+        page->v.md.metadata = metadata;

    
      
    
      
    Don't you need to install such a link for every one of the 4 pages?
    
    
    
    
    Yes, I need to do that. Thanks.


    
    
    
      
    

    
      
    
        
    @@ -198,24 +224,25 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
     return __map_domain_page(p2m->root + root_table_indx);
 }
 
-static int p2m_set_type(pte_t *pte, p2m_type_t t)
+static void p2m_set_type(pte_t *pte, const p2m_type_t t, const unsigned int i)
 {
-    int rc = 0;
-
     if ( t > p2m_ext_storage )
-        panic("unimplemeted\n");
+    {
+        ASSERT(pte);
+
+        pte[i].pte = t;

    
      
    
      
    What does i identify here?
    
    
    
    
    An index in metadata page where P2M type for corresponding PTE is stored.
I will re-name it to metadata_indx for more clarity.


    
    
    
      
    

    
      
    
        
    +    }
     else
         pte->pte |= MASK_INSR(t, P2M_TYPE_PTE_BITS_MASK);
-
-    return rc;
 }
 
-static p2m_type_t p2m_get_type(const pte_t pte)
+static p2m_type_t p2m_get_type(const pte_t pte, const pte_t *metadata,
+                               const unsigned int i)
 {
     p2m_type_t type = MASK_EXTR(pte.pte, P2M_TYPE_PTE_BITS_MASK);
 
     if ( type == p2m_ext_storage )
-        panic("unimplemented\n");
+        type = metadata[i].pte;
 
     return type;
 }

    
      
    
      
    Overall this feels pretty fragile, as the caller has to pass several values
which all need to be in sync with one another. If you ...
    
    
    
    
    Generally, agree it is fragile enough.


    
    
    
      
    

    
      
    
        
    @@ -265,7 +292,10 @@ static void p2m_set_permission(pte_t *e, p2m_type_t t)
     }
 }
 
-static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
+static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t,
+                              struct page_info *metadata_pg,
+                              const unsigned int indx,
+                              bool is_table)
 {
     pte_t e = (pte_t) { PTE_VALID };
 
@@ -285,12 +315,21 @@ static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t, bool is_table)
 
     if ( !is_table )
     {
+        pte_t *metadata = __map_domain_page(metadata_pg);

    
      
    
      
    ... map the page anyway, no matter whether ...


    
      
    
        
             p2m_set_permission(&e, t);
 
+        metadata[indx].pte = p2m_invalid;
+
         if ( t < p2m_ext_storage )
-            p2m_set_type(&e, t);
+            p2m_set_type(&e, t, indx);
         else
-            panic("unimplemeted\n");
+        {
+            e.pte |= MASK_INSR(p2m_ext_storage, P2M_TYPE_PTE_BITS_MASK);
+            p2m_set_type(metadata, t, indx);
+        }

    
      
    
      
    ... you'll actually use it, maybe best to map both pages at the same point?
    
    
    
    
    Only one page is mapped here (?) and it should be mapped here, I suppose, it could be a case
when a previous set type is overwritten, so, it could be needed to invalidate a type written
in metadata.


    
    
    
      
    And as said elsewhere, no, I don't think you want to use p2m_set_type() for
two entirely different purposes.
    
    
    
    
    I wasn't very happy too, but, at the same time I didn't want to have a prototype where
it isn't really clear when it is needed to pass metadata and where it is not. But considering
your comments then this one solution isn't good too. So maybe it would be better just have
two separate functions: p2m_set_pte_type() and p2m_set_metadata_type().


    
    
    
      
    

    
      
    
        
    @@ -323,22 +364,71 @@ static struct page_info *p2m_alloc_page(struct p2m_domain *p2m)
     return pg;
 }
 
+static void p2m_free_page(struct p2m_domain *p2m, struct page_info *pg);
+
+/*
+ * Allocate a page table with an additional extra page to store
+ * metadata for each entry of the page table.
+ * Link this metadata page to page table page's list field.
+ */
+static struct page_info * p2m_alloc_table(struct p2m_domain *p2m)

    
      
    
      
    Nit: Stray blank after * again.


    
      
    
        
    +{
+    enum table_type
+    {
+        INTERMEDIATE_TABLE=0,

    
      
    
      
    If you really think you need the "= 0", then please with blanks around '='.


    
      
    
        
    +        /*
+         * At the moment, metadata is going to store P2M type
+         * for each PTE of page table.
+         */
+        METADATA_TABLE,
+        TABLE_MAX
+    };
+
+    struct page_info *tables[TABLE_MAX];
+
+    for ( unsigned int i = 0; i < TABLE_MAX; i++ )
+    {
+        tables[i] = p2m_alloc_page(p2m);
+
+        if ( !tables[i] )
+            goto out;
+
+        clear_and_clean_page(tables[i]);
+    }
+
+    tables[INTERMEDIATE_TABLE]->v.md.metadata = tables[METADATA_TABLE];
+
+    return tables[INTERMEDIATE_TABLE];
+
+ out:
+    for ( unsigned int i = 0; i < TABLE_MAX; i++ )
+        if ( tables[i] )

    
      
    
      
    You didn't clear all of tables[] first, though.
    
    
    
    
    Oh, right, i missed an initalizer for tables[] array.

    
    
    
      
     This kind of cleanup is
often better done as

    while ( i-- > 0 )
        ...

You don't even need an if() then, as you know allocations succeeded for all
earlier array slots.
    
    
    
    
    Yes, it looks very nice.


    
    
    
      
    

    
      
    
        
    +            p2m_free_page(p2m, tables[i]);
+
+    return NULL;
+}

    
      
    
      
    I'm also surprised you allocate the metadata table no matter whether you'll
actually need it. That'll double your average paging pool usage, when in a
typical case only very few entries would actually require this extra
storage.
    
    
    
    
    Nice point, we could really do a delayed allocation instead and allocate only
when requested P2M type is > p2m_ext_storage.
I'll implement that.


    
    
    
      
    

    
      
    
        
    @@ -453,10 +543,9 @@ static void p2m_put_2m_superpage(mfn_t mfn, p2m_type_t type)
 }
 
 /* Put any references on the page referenced by pte. */
-static void p2m_put_page(const pte_t pte, unsigned int level)
+static void p2m_put_page(const pte_t pte, unsigned int level, p2m_type_t p2mt)
 {
     mfn_t mfn = pte_get_mfn(pte);
-    p2m_type_t p2m_type = p2m_get_type(pte);
 
     ASSERT(pte_is_valid(pte));
 
@@ -470,10 +559,10 @@ static void p2m_put_page(const pte_t pte, unsigned int level)
     switch ( level )
     {
     case 1:
-        return p2m_put_2m_superpage(mfn, p2m_type);
+        return p2m_put_2m_superpage(mfn, p2mt);
 
     case 0:
-        return p2m_put_4k_page(mfn, p2m_type);
+        return p2m_put_4k_page(mfn, p2mt);
     }
 }

    
      
    
      
    Might it be better to introduce this function in this shape right away, in
the earlier patch?
    
    
    
    
    Agree, probably, I did that intentionally, but I don't remember why. I will try to
avoid these changes in this patch as it looks unnecessary here.


    
    
    
      
    

    
      
    
        
    @@ -690,18 +791,23 @@ static int p2m_set_entry(struct p2m_domain *p2m,
     {
         /* We need to split the original page. */
         pte_t split_pte = *entry;
+        struct page_info *metadata = virt_to_page(table)->v.md.metadata;

    
      
    
      
    This (or along these lines) is how I would have expected things to be done
elsewhere as well, limiting the amount of arguments you need to pass
around.
    
    
    
    
    I will try to re-use this approach elsewhere I can.

Thanks.

~ Oleksii
    
  


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        Tue, 12 Aug 2025 08:08:15 -0700 (PDT)
From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: Roger Pau Monne ,
	Oleksii Kurochko ,
	Community Manager ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	Stefano Stabellini 
Subject: [PATCH v5] pdx: introduce a new compression algorithm based on region offsets
Date: Tue, 12 Aug 2025 17:06:24 +0200
Message-ID: <20250812150624.64898-1-roger.pau@citrix.com>
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With the appearance of Intel Sierra Forest and Granite Rapids it's now
possible to get a production x86 host with the following memory map:

SRAT: Node 0 PXM 0 [0000000000000000, 000000007fffffff]
SRAT: Node 0 PXM 0 [0000000100000000, 000000807fffffff]
SRAT: Node 1 PXM 1 [0000063e80000000, 000006be7fffffff]
SRAT: Node 2 PXM 2 [00000c7e80000000, 00000cfe7fffffff]
SRAT: Node 3 PXM 3 [000012be80000000, 0000133e7fffffff]

This is from a four socket Granite Rapids system, with each node having
512GB of memory.  The total amount of RAM on the system is 2TB, but without
enabling CONFIG_BIGMEM the last range is not accessible, as it's above the
16TB boundary covered by the frame table. Sierra Forest and Granite Rapids
are socket compatible, however Sierra Forest only supports 2 socket
configurations, while Granite Rapids can go up to 8 sockets.

Note that while the memory map is very sparse, it couldn't be compressed
using the current PDX_MASK compression algorithm, which relies on all
ranges having a shared zeroed region of bits that can be removed.

The memory map presented above has the property of all regions being
similarly spaced between each other, and all having also a similar size.
Use a lookup table to store the offsets to translate from/to PFN and PDX
spaces.  Such table is indexed based on the input PFN or PDX to translated.
The example PFN layout about would get compressed using the following:

PFN compression using PFN lookup table shift 29 and PDX region size 0x10000000
 range 0 [0000000000000, 0x0000807ffff] PFN IDX  0 : 0000000000000
 range 1 [0x00063e80000, 0x0006be7ffff] PFN IDX  3 : 0x00053e80000
 range 2 [0x000c7e80000, 0x000cfe7ffff] PFN IDX  6 : 0x000a7e80000
 range 3 [0x0012be80000, 0x00133e7ffff] PFN IDX  9 : 0x000fbe80000

Note how the tow ranges belonging to node 0 get merged into a single PDX
region by the compression algorithm.

The default size of lookup tables currently set in Kconfig is 64 entries,
and the example memory map consumes 10 entries.  Such memory map is from a
4 socket Granite Rapids host, which in theory supports up to 8 sockets
according to Intel documentation.  Assuming the layout of a 8 socket system
is similar to the 4 socket one, it would require 21 lookup table entries to
support it, way below the current default of 64 entries.

The valid range of lookup table size is currently restricted from 1 to 512
elements in Kconfig.

An extra array is used to keep track of the base PFN for each translated
range.  Non used slots are set to ~0UL, so that in mfn_valid() the mfn <
base check always fails, thus reporting the mfn as invalid.

Introduce __init_or_pdx_mask and use it on some shared functions between
PDX mask and offset compression, as otherwise some code becomes unreachable
after boot if PDX offset compression is used.  Mark the code as __init in
that case, so it's pruned after boot.

Signed-off-by: Roger Pau Monné 
---
Changes since v4:
 - Fold pfn_offset_sanitize_ranges() into pfn_pdx_compression_setup().
 - Fix usage of SWAP().
 - Indented code block added to mfn_valid().
 - Optimize a loop.
 - Move definition of pdx_region_size.

Changes since v3:
 - Rename __init_or_pdx_mask.
 - Reorder logic in pfn_offset_sanitize_ranges() to reduce code.
 - Print a message if the table index is truncated from what would be
   required to represent all input ranges independently.
 - Cast size to paddr_t for pdx_init_mask() call.

Changes since v2:
 - s/PDX_OFFSET_TLB_ORDER/PDX_OFFSET_TBL_ORDER/.
 - Fix changelog mention of Sapphire Rapids.
 - Misc fixes in the test harness.
 - Use SWAP() macro.
 - Introduce an extra table to keep the bases of the valid ranges.

Changes since v1:
 - Use a lookup table with the offsets.
 - Split the adding of the test to a pre-patch.
 - Amend diagram to also show possible padding after compression.
---
 CHANGELOG.md               |   3 +
 tools/tests/pdx/.gitignore |   1 +
 tools/tests/pdx/Makefile   |   3 +-
 tools/tests/pdx/harness.h  |  14 +++
 tools/tests/pdx/test-pdx.c |   4 +
 xen/common/Kconfig         |  21 +++-
 xen/common/pdx.c           | 241 ++++++++++++++++++++++++++++++++++++-
 xen/include/xen/pdx.h      |  87 ++++++++++++-
 8 files changed, 368 insertions(+), 6 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe3f..f9ef893f4851 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -20,6 +20,9 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
      grant table or foreign memory.
 
 ### Added
+ - Introduce new PDX compression algorithm to cope with Intel Sierra Forest and
+   Granite Rapids having sparse memory maps.
+
  - On x86:
    - Option to attempt to fixup p2m page-faults on PVH dom0.
    - Resizable BARs is supported for PVH dom0.
diff --git a/tools/tests/pdx/.gitignore b/tools/tests/pdx/.gitignore
index a32c7db4de79..1202a531a7fd 100644
--- a/tools/tests/pdx/.gitignore
+++ b/tools/tests/pdx/.gitignore
@@ -1,2 +1,3 @@
 /pdx.h
 /test-pdx-mask
+/test-pdx-offset
diff --git a/tools/tests/pdx/Makefile b/tools/tests/pdx/Makefile
index b3734afde686..10b354f0cefd 100644
--- a/tools/tests/pdx/Makefile
+++ b/tools/tests/pdx/Makefile
@@ -1,7 +1,7 @@
 XEN_ROOT=$(CURDIR)/../../..
 include $(XEN_ROOT)/tools/Rules.mk
 
-TARGETS := test-pdx-mask
+TARGETS := test-pdx-mask test-pdx-offset
 
 .PHONY: all
 all: $(TARGETS)
@@ -42,6 +42,7 @@ CFLAGS += $(APPEND_CFLAGS)
 CFLAGS += $(CFLAGS_xeninclude)
 
 test-pdx-mask: CFLAGS += -DCONFIG_PDX_MASK_COMPRESSION
+test-pdx-offset: CFLAGS += -DCONFIG_PDX_OFFSET_COMPRESSION
 
 test-pdx-%: test-pdx.c pdx.h
 	$(CC) $(CPPFLAGS) $(CFLAGS) $(CFLAGS_$*.o) -o $@ $< $(APPEND_CFLAGS)
diff --git a/tools/tests/pdx/harness.h b/tools/tests/pdx/harness.h
index 5bef7df650d2..7c1c5a246868 100644
--- a/tools/tests/pdx/harness.h
+++ b/tools/tests/pdx/harness.h
@@ -44,8 +44,10 @@
 
 #define MAX_RANGES 16
 #define MAX_PFN_RANGES MAX_RANGES
+#define CONFIG_PDX_OFFSET_TBL_ORDER 6
 
 #define ASSERT assert
+#define ASSERT_UNREACHABLE() assert(0)
 
 #define CONFIG_DEBUG
 
@@ -66,10 +68,22 @@ static inline unsigned int find_next(
 #define find_next_zero_bit(a, s, o) find_next(a, s, o, false)
 #define find_next_bit(a, s, o)      find_next(a, s, o, true)
 
+#define flsl(x) ((x) ? BITS_PER_LONG - __builtin_clzl(x) : 0)
+#define ffsl(x) __builtin_ffsl(x)
+
 #define boolean_param(name, func)
 
 typedef uint64_t paddr_t;
 
+#define SWAP(a, b) \
+   do { typeof(a) t_ = (a); (a) = (b); (b) = t_; } while ( 0 )
+
+#define sort(elem, nr, size, cmp, swp) ({                               \
+    /* Consume swp() so compiler doesn't complain it's unused. */       \
+    (void)swp;                                                          \
+    qsort(elem, nr, size, cmp);                                         \
+})
+
 #include "pdx.h"
 
 #endif
diff --git a/tools/tests/pdx/test-pdx.c b/tools/tests/pdx/test-pdx.c
index 0798ccee359b..eefd54c76815 100644
--- a/tools/tests/pdx/test-pdx.c
+++ b/tools/tests/pdx/test-pdx.c
@@ -51,7 +51,11 @@ int main(int argc, char **argv)
                 { .start =  0xc7e80000UL, .end =  0xcfe80000UL },
                 { .start = 0x12be80000UL, .end = 0x133e80000UL },
             },
+#ifdef CONFIG_PDX_OFFSET_COMPRESSION
+            .compress = true,
+#else
             .compress = false,
+#endif
         },
         /* Simple hole. */
         {
diff --git a/xen/common/Kconfig b/xen/common/Kconfig
index 8dad0c923a9d..76f9ce705f7a 100644
--- a/xen/common/Kconfig
+++ b/xen/common/Kconfig
@@ -59,7 +59,8 @@ config EVTCHN_FIFO
 
 choice
 	prompt "PDX (Page inDeX) compression"
-	default PDX_MASK_COMPRESSION if !X86 && !RISCV
+	default PDX_OFFSET_COMPRESSION if X86
+	default PDX_MASK_COMPRESSION if !RISCV
 	default PDX_NONE
 	help
 	  PDX compression is a technique designed to reduce the memory
@@ -78,12 +79,30 @@ config PDX_MASK_COMPRESSION
 	help
 	  Compression relying on all RAM addresses sharing a zeroed bit region.
 
+config PDX_OFFSET_COMPRESSION
+	bool "Offset compression"
+	help
+	  Compression relying on size and distance between RAM regions being
+	  compressible using an offset lookup table.
+
 config PDX_NONE
 	bool "None"
 	help
 	  No compression
 endchoice
 
+config PDX_OFFSET_TBL_ORDER
+	int "PDX offset compression lookup table order" if EXPERT
+	depends on PDX_OFFSET_COMPRESSION
+	default 6
+	range 0 9
+	help
+	  Order of the PFN to PDX and PDX to PFN translation lookup tables.
+	  Number of table entries is calculated as 2^N.
+
+	  Size of the tables can be adjusted from 1 entry (order 0) to 512
+	  entries (order 9).
+
 config ALTERNATIVE_CALL
 	bool
 
diff --git a/xen/common/pdx.c b/xen/common/pdx.c
index 9e6b36086fbd..7e070ff962e8 100644
--- a/xen/common/pdx.c
+++ b/xen/common/pdx.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /**
  * Maximum (non-inclusive) usable pdx. Must be
@@ -40,6 +41,12 @@ bool __mfn_valid(unsigned long mfn)
 
 #ifdef CONFIG_PDX_MASK_COMPRESSION
     invalid |= mfn & pfn_hole_mask;
+#elif defined(CONFIG_PDX_OFFSET_COMPRESSION)
+    {
+        unsigned long base = pfn_bases[PFN_TBL_IDX(mfn)];
+
+        invalid |= mfn < base || mfn >= base + pdx_region_size;
+    }
 #endif
 
     if ( unlikely(evaluate_nospec(invalid)) )
@@ -75,6 +82,13 @@ void set_pdx_range(unsigned long smfn, unsigned long emfn)
 # error "Missing architecture maximum number of RAM ranges"
 #endif
 
+/* Some functions should be init when not using PDX mask compression. */
+#ifndef CONFIG_PDX_MASK_COMPRESSION
+# define __init_or_mask_compr __init
+#else
+# define __init_or_mask_compr
+#endif
+
 /* Generic PFN compression helpers. */
 static struct pfn_range {
     unsigned long base_pfn, pages;
@@ -102,7 +116,7 @@ void __init pfn_pdx_add_region(paddr_t base, paddr_t size)
 }
 
 /* Sets all bits from the most-significant 1-bit down to the LSB */
-static uint64_t fill_mask(uint64_t mask)
+static uint64_t __init_or_mask_compr fill_mask(uint64_t mask)
 {
     while (mask & (mask + 1))
         mask |= mask + 1;
@@ -128,7 +142,7 @@ static uint64_t fill_mask(uint64_t mask)
  * @param len  Size in octets of the region
  * @return Mask of moving bits at the bottom of all the region addresses
  */
-static uint64_t pdx_region_mask(uint64_t base, uint64_t len)
+static uint64_t __init_or_mask_compr pdx_region_mask(uint64_t base, uint64_t len)
 {
     /*
      * We say a bit "moves" in a range if there exist 2 addresses in that
@@ -294,7 +308,228 @@ void __init pfn_pdx_compression_reset(void)
     nr_ranges = 0;
 }
 
-#endif /* CONFIG_PDX_COMPRESSION */
+#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) /* CONFIG_PDX_MASK_COMPRESSION */
+
+unsigned int __ro_after_init pfn_index_shift;
+unsigned int __ro_after_init pdx_index_shift;
+unsigned long __ro_after_init pdx_region_size = ~0UL;
+
+unsigned long __ro_after_init pfn_pdx_lookup[CONFIG_PDX_NR_LOOKUP];
+unsigned long __ro_after_init pdx_pfn_lookup[CONFIG_PDX_NR_LOOKUP];
+unsigned long __ro_after_init pfn_bases[CONFIG_PDX_NR_LOOKUP];
+
+bool pdx_is_region_compressible(paddr_t base, unsigned long npages)
+{
+    unsigned long pfn = PFN_DOWN(base);
+    unsigned long pfn_base = pfn_bases[PFN_TBL_IDX(pfn)];
+
+    return pfn >= pfn_base &&
+           pfn + npages <= pfn_base + pdx_region_size;
+}
+
+static int __init cf_check cmp_node(const void *a, const void *b)
+{
+    const struct pfn_range *l = a, *r = b;
+
+    if ( l->base_pfn > r->base_pfn )
+        return 1;
+    if ( l->base_pfn < r->base_pfn )
+        return -1;
+
+    return 0;
+}
+
+static void __init cf_check swp_node(void *a, void *b)
+{
+    struct pfn_range *l = a, *r = b;
+
+    SWAP(*l, *r);
+}
+
+bool __init pfn_pdx_compression_setup(paddr_t base)
+{
+    unsigned long mask = PFN_DOWN(pdx_init_mask(base)), idx_mask = 0;
+    unsigned long pages = 0;
+    unsigned int i;
+
+    if ( !nr_ranges )
+    {
+        printk(XENLOG_DEBUG "PFN compression disabled%s\n",
+               pdx_compress ? ": no ranges provided" : "");
+        return false;
+    }
+
+    if ( nr_ranges > ARRAY_SIZE(ranges) )
+    {
+        printk(XENLOG_WARNING
+               "Too many PFN ranges (%u > %zu), not attempting PFN compression\n",
+               nr_ranges, ARRAY_SIZE(ranges));
+        return false;
+    }
+
+    /* Sort ranges by start address. */
+    sort(ranges, nr_ranges, sizeof(*ranges), cmp_node, swp_node);
+
+    for ( i = 0; i < nr_ranges; i++ )
+    {
+        unsigned long start = ranges[i].base_pfn;
+
+        /*
+         * Align range base to MAX_ORDER.  This is required so the PDX offset
+         * for the bits below MAX_ORDER matches the MFN offset, and pages
+         * greater than the minimal order can be used to populate the
+         * directmap.
+         */
+        ranges[i].base_pfn = start & ~((1UL << MAX_ORDER) - 1);
+        ranges[i].pages = start + ranges[i].pages - ranges[i].base_pfn;
+
+        /*
+         * Only merge overlapped regions now, leave adjacent regions separated.
+         * They would be merged later if both use the same index into the
+         * lookup table.
+         */
+        if ( !i ||
+             ranges[i].base_pfn >=
+             (ranges[i - 1].base_pfn + ranges[i - 1].pages) )
+        {
+            mask |= pdx_region_mask(ranges[i].base_pfn, ranges[i].pages);
+            continue;
+        }
+
+        ranges[i - 1].pages = ranges[i].base_pfn + ranges[i].pages -
+                              ranges[i - 1].base_pfn;
+
+        if ( i + 1 < nr_ranges )
+            memmove(&ranges[i], &ranges[i + 1],
+                    (nr_ranges - (i + 1)) * sizeof(ranges[0]));
+        else /* last range */
+            mask |= pdx_region_mask(ranges[i].base_pfn, ranges[i].pages);
+        nr_ranges--;
+        i--;
+    }
+
+    /*
+     * Populate a mask with the non-equal bits of the different ranges, do this
+     * to calculate the maximum PFN shift to use as the lookup table index.
+     */
+    for ( i = 0; i < nr_ranges; i++ )
+        for ( unsigned int j = i + 1; j < nr_ranges; j++ )
+            idx_mask |= ranges[i].base_pfn ^ ranges[j].base_pfn;
+    /* Mask out the bits that change inside of ranges. */
+    idx_mask &= ~mask;
+
+    if ( !idx_mask )
+        /* Single region case. */
+        pfn_index_shift = flsl(mask);
+    else if ( flsl(idx_mask) - ffsl(idx_mask) < CONFIG_PDX_OFFSET_TBL_ORDER )
+        /* The changed mask fits in the table index width. */
+        pfn_index_shift = ffsl(idx_mask) - 1;
+    else
+    {
+        /* Changed mask is wider than array size, use most significant bits. */
+        pfn_index_shift = flsl(idx_mask) - CONFIG_PDX_OFFSET_TBL_ORDER;
+        printk(XENLOG_DEBUG
+               "PFN compression table index truncated, requires order %u\n",
+               flsl(idx_mask) - ffsl(idx_mask) + 1);
+    }
+
+    /*
+     * Check correctness of the calculated values, plus merge ranges if they
+     * use the same lookup table index.
+     */
+    for ( i = 0; i < nr_ranges; i++ )
+    {
+        /*
+         * Ensure ranges [start, end] use the same offset table index.  Should
+         * be guaranteed by the logic that calculates the pfn shift.
+         */
+        if ( PFN_TBL_IDX(ranges[i].base_pfn) !=
+             PFN_TBL_IDX(ranges[i].base_pfn + ranges[i].pages - 1) )
+        {
+            printk(XENLOG_DEBUG "PFN compression is invalid, disabling\n");
+            ASSERT_UNREACHABLE();
+            pfn_pdx_compression_reset();
+            return false;
+        }
+
+        if ( !i ||
+             PFN_TBL_IDX(ranges[i - 1].base_pfn) !=
+             PFN_TBL_IDX(ranges[i].base_pfn) )
+            continue;
+
+        /* Merge ranges with the same table index. */
+        ranges[i - 1].pages = ranges[i].base_pfn + ranges[i].pages -
+                              ranges[i - 1].base_pfn;
+        if ( i + 1 < nr_ranges )
+            memmove(&ranges[i], &ranges[i + 1],
+                    (nr_ranges - (i + 1)) * sizeof(ranges[0]));
+        nr_ranges--;
+        i--;
+    }
+
+    /*
+     * Find the maximum PFN range size after having merged ranges with same
+     * index.  The rounded up region size will be the base for the PDX region
+     * size and shift.
+     */
+    for ( i = 0; i < nr_ranges; i++ )
+        pages = max(pages, ranges[i].pages);
+
+    /* pdx_init_mask() already takes MAX_ORDER into account. */
+    mask = PFN_DOWN(pdx_init_mask((paddr_t)pages << PAGE_SHIFT));
+    pdx_index_shift = flsl(mask);
+
+    /* Avoid compression if there's no gain. */
+    if ( (mask + 1) * (nr_ranges - 1) >= ranges[nr_ranges - 1].base_pfn )
+    {
+        printk(XENLOG_DEBUG
+               "PFN compression yields no space gain, disabling\n");
+        pfn_pdx_compression_reset();
+        return false;
+    }
+
+    /*
+     * Set all entries in the bases table to ~0 to force both mfn_valid() and
+     * pdx_is_region_compressible() to return false for non-handled pfns.
+     */
+    memset(pfn_bases, ~0, sizeof(pfn_bases));
+
+    pdx_region_size = mask + 1;
+
+    printk(XENLOG_INFO
+           "PFN compression using lookup table shift %u and region size %#lx\n",
+           pfn_index_shift, pdx_region_size);
+
+    for ( i = 0; i < nr_ranges; i++ )
+    {
+        unsigned int idx = PFN_TBL_IDX(ranges[i].base_pfn);
+
+        pfn_pdx_lookup[idx] = ranges[i].base_pfn - (mask + 1) * i;
+        pdx_pfn_lookup[i] = pfn_pdx_lookup[idx];
+        pfn_bases[idx] = ranges[i].base_pfn;
+
+        printk(XENLOG_DEBUG
+               " range %3u [%013lx, %013lx] PFN IDX %3u : %013lx\n",
+               i, ranges[i].base_pfn, ranges[i].base_pfn + ranges[i].pages - 1,
+               idx, pfn_pdx_lookup[idx]);
+    }
+
+    return true;
+}
+
+void __init pfn_pdx_compression_reset(void)
+{
+    memset(pfn_pdx_lookup, 0, sizeof(pfn_pdx_lookup));
+    memset(pdx_pfn_lookup, 0, sizeof(pfn_pdx_lookup));
+    memset(pfn_bases, 0, sizeof(pfn_bases));
+    pfn_index_shift = 0;
+    pdx_index_shift = 0;
+    pdx_region_size = ~0UL;
+
+    nr_ranges = 0;
+}
+
+#endif /* CONFIG_PDX_OFFSET_COMPRESSION */
 
 /*
  * Local variables:
diff --git a/xen/include/xen/pdx.h b/xen/include/xen/pdx.h
index 425d45e9f08e..856fc3e8a0e6 100644
--- a/xen/include/xen/pdx.h
+++ b/xen/include/xen/pdx.h
@@ -65,6 +65,46 @@
  * This scheme also holds for multiple regions, where HHHHHHH acts as
  * the region identifier and LLLLLL fully contains the span of every
  * region involved.
+ *
+ * ## PDX offset compression
+ *
+ * Alternative compression mechanism that relies on RAM ranges having a similar
+ * size and offset between them:
+ *
+ * PFN address space:
+ * ┌────────┬──────────┬────────┬──────────┠  ┌────────┬──────────â”
+ * │ RAM 0  │          │ RAM 1  │          │...│ RAM N  │          │
+ * ├────────┼──────────┼────────┴──────────┘   └────────┴──────────┘
+ * │<------>│          │
+ * │  size             │
+ * │<----------------->│
+ *         offset
+ *
+ * The compression reduces the holes between RAM regions:
+ *
+ * PDX address space:
+ * ┌────────┬───┬────────┬───┠  ┌─┬────────â”
+ * │ RAM 0  │   │ RAM 1  │   │...│ │ RAM N  │
+ * ├────────┴───┼────────┴───┘   └─┴────────┘
+ * │<---------->│
+ *   pdx region size
+ *
+ * The offsets to convert from PFN to PDX and from PDX to PFN are stored in a
+ * pair of lookup tables, and the index into those tables to find the offset
+ * for each PFN or PDX is obtained by shifting the to be translated address by
+ * a specific value calculated at boot:
+ *
+ * pdx = pfn - pfn_lookup_table[pfn >> pfn_shift]
+ * pfn = pdx + pdx_lookup_table[pdx >> pdx_shift]
+ *
+ * Note the indexes into the lookup tables are masked to avoid out of bounds
+ * accesses.
+ *
+ * This compression requires the PFN ranges to contain a non-equal most
+ * significant part that's smaller than the lookup table size, so that a valid
+ * shift value can be found to differentiate between PFN regions.  The setup
+ * algorithm might merge otherwise separate PFN ranges to use the same lookup
+ * table entry.
  */
 
 extern unsigned long max_pdx;
@@ -157,7 +197,52 @@ static inline paddr_t directmapoff_to_maddr_xlate(unsigned long offset)
             (offset & ma_va_bottom_mask));
 }
 
-#endif /* CONFIG_PDX_MASK_COMPRESSION */
+#elif defined(CONFIG_PDX_OFFSET_COMPRESSION) /* CONFIG_PDX_MASK_COMPRESSION */
+
+#include 
+
+#define CONFIG_PDX_NR_LOOKUP (1UL << CONFIG_PDX_OFFSET_TBL_ORDER)
+#define PDX_TBL_MASK (CONFIG_PDX_NR_LOOKUP - 1)
+
+#define PFN_TBL_IDX(pfn) \
+    (((pfn) >> pfn_index_shift) & PDX_TBL_MASK)
+#define PDX_TBL_IDX(pdx) \
+    (((pdx) >> pdx_index_shift) & PDX_TBL_MASK)
+#define MADDR_TBL_IDX(ma) \
+    (((ma) >> (pfn_index_shift + PAGE_SHIFT)) & PDX_TBL_MASK)
+#define DMAPOFF_TBL_IDX(off) \
+    (((off) >> (pdx_index_shift + PAGE_SHIFT)) & PDX_TBL_MASK)
+
+extern unsigned int pfn_index_shift;
+extern unsigned int pdx_index_shift;
+extern unsigned long pdx_region_size;
+
+extern unsigned long pfn_pdx_lookup[];
+extern unsigned long pdx_pfn_lookup[];
+extern unsigned long pfn_bases[];
+
+static inline unsigned long pfn_to_pdx_xlate(unsigned long pfn)
+{
+    return pfn - pfn_pdx_lookup[PFN_TBL_IDX(pfn)];
+}
+
+static inline unsigned long pdx_to_pfn_xlate(unsigned long pdx)
+{
+    return pdx + pdx_pfn_lookup[PDX_TBL_IDX(pdx)];
+}
+
+static inline unsigned long maddr_to_directmapoff_xlate(paddr_t ma)
+{
+    return ma - ((paddr_t)pfn_pdx_lookup[MADDR_TBL_IDX(ma)] << PAGE_SHIFT);
+}
+
+static inline paddr_t directmapoff_to_maddr_xlate(unsigned long offset)
+{
+    return offset + ((paddr_t)pdx_pfn_lookup[DMAPOFF_TBL_IDX(offset)] <<
+                     PAGE_SHIFT);
+}
+
+#endif /* CONFIG_PDX_OFFSET_COMPRESSION */
 
 #ifdef CONFIG_PDX_NONE
 
-- 
2.49.0



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From: Stewart Hildebrand 
To: 
CC: Stewart Hildebrand ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Jiqian Chen
	
Subject: [PATCH] vpci/msix: conditionally invoke vpci_make_msix_hole
Date: Tue, 12 Aug 2025 11:17:42 -0400
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A hotplugged PCI device may be added uninitialized. In particular,
memory decoding may be disabled and the BARs may be zeroed. In this
case, the BARs will not be mapped in p2m. However, currently
vpci_make_msix_hole is called unconditionally in init_msix, and the
initialization fails in this case:

(XEN) d0v0 0000:01:00.0: existing mapping (mfn: 1c1880 type: 0) at 0 clobbers MSIX MMIO area
(XEN) d0 0000:01:00.0: init legacy cap 17 fail rc=-17, mask it

vpci_make_msix_hole should only be called if the BARs containing the
MSI-X/PBA tables are mapped in p2m.

Take the opportunity to fix a typo in the preceding comment.

Fixes: ee2eb6849d50 ("vpci: Refactor REGISTER_VPCI_INIT")
Signed-off-by: Stewart Hildebrand 
---
 xen/drivers/vpci/msix.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c
index 54a5070733aa..39d1c45bd296 100644
--- a/xen/drivers/vpci/msix.c
+++ b/xen/drivers/vpci/msix.c
@@ -705,10 +705,16 @@ static int cf_check init_msix(struct pci_dev *pdev)
 
     /*
      * vPCI header initialization will have mapped the whole BAR into the
-     * p2m, as MSI-X capability was not yet initialized.  Crave a hole for
+     * p2m, as MSI-X capability was not yet initialized.  Carve a hole for
      * the MSI-X table here, so that Xen can trap accesses.
      */
-    return vpci_make_msix_hole(pdev);
+    if ( pdev->vpci->header.bars[
+             msix->tables[VPCI_MSIX_TABLE] & PCI_MSIX_BIRMASK].enabled ||
+         pdev->vpci->header.bars[
+             msix->tables[VPCI_MSIX_PBA] & PCI_MSIX_BIRMASK].enabled )
+        return vpci_make_msix_hole(pdev);
+
+    return 0;
 }
 REGISTER_VPCI_CAP(MSIX, init_msix, NULL);
 

base-commit: 4cde4a552ed35f3cc74df877d5a7cfbbfced8fb3
-- 
2.50.1



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From: Frediano Ziglio 
To: xen-devel@lists.xenproject.org
Cc: Frediano Ziglio ,
	Jan Beulich ,
	Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH] x86/boot: Remove unused symbols from linker script
Date: Tue, 12 Aug 2025 16:19:20 +0100
Message-ID: <20250812151923.96832-1-frediano.ziglio@cloud.com>
X-Mailer: git-send-email 2.43.0
MIME-Version: 1.0
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The symbols declared with DECLARE_IMPORT are meant to be
used by the 32 bit code.
The __base_relocs_{start,end} symbols were not used by the
code.
No functional changes.

Signed-off-by: Frediano Ziglio 
---
 xen/arch/x86/boot/build32.lds.S | 2 --
 1 file changed, 2 deletions(-)

diff --git a/xen/arch/x86/boot/build32.lds.S b/xen/arch/x86/boot/build32.lds.S
index 1e59732edd..e4f7c7fc2f 100644
--- a/xen/arch/x86/boot/build32.lds.S
+++ b/xen/arch/x86/boot/build32.lds.S
@@ -43,8 +43,6 @@ SECTIONS
          * Attention should be paid to pointers taking care of possible later
          * relocation.
          */
-        DECLARE_IMPORT(__base_relocs_start);
-        DECLARE_IMPORT(__base_relocs_end);
         DECLARE_IMPORT(__trampoline_rel_start);
         DECLARE_IMPORT(__trampoline_rel_stop);
         DECLARE_IMPORT(__trampoline_seg_start);
-- 
2.43.0



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From: Ayan Kumar Halder 
To: 
CC: , ,
	, , Ayan Kumar Halder
	
Subject: [ImageBuilder v2] Add config option to use separate load commands for Xen, DOM0 and DOMU binaries
Date: Tue, 12 Aug 2025 16:19:45 +0100
Message-ID: <20250812151945.2430295-1-ayan.kumar.halder@amd.com>
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Introduce the following options :-
1. XEN_LOAD - This specifies command to load xen hypervisor binary and device
tree.
2. DOM0_LOAD - This specifies command to load Dom0 binaries.
3. DOMU_LOAD[] - This specifies command to load DomU binaries.

There can be situations where Xen, Dom0 and DomU binaries are stored in
different partitions. Thus, imagebuilder should provide a way the binaries
using different commands.

If any of the above options are not specified, LOAD_CMD is used by default.

Signed-off-by: Ayan Kumar Halder 
---
This patch should be applied first.

Changes from :-

v1 - 1. Make LOAD_CMD optional when XEN is set
2. find_root_dev() should be invoked with either "$DOM0_CMD" or "$LOAD_CMD"
depending on if it is invoked from xen_config() or linux_config().
3. User needs to set either LOAD_CMD or XEN_LOAD. If neither is set, throw
an error. This is true for DOM0_LOAD and DOMU_LOAD[].

 README.md                | 18 +++++++++-
 scripts/uboot-script-gen | 76 ++++++++++++++++++++++++++++------------
 2 files changed, 71 insertions(+), 23 deletions(-)

diff --git a/README.md b/README.md
index b7be268..59919df 100644
--- a/README.md
+++ b/README.md
@@ -33,10 +33,12 @@ BOOT_CMD="booti"
 
 DEVICE_TREE="mpsoc.dtb"
 XEN="xen"
+XEN_LOAD="ext4load mmc 0:1"
 XEN_CMD="console=dtuart dtuart=serial0 dom0_mem=1G dom0_max_vcpus=1 bootscrub=0 vwfi=native sched=null"
 PASSTHROUGH_DTS_REPO="git@github.com:Xilinx/xen-passthrough-device-trees.git device-trees-2021.2/zcu102"
 DOM0_KERNEL="Image-dom0"
 DOM0_CMD="console=hvc0 earlycon=xen earlyprintk=xen clk_ignore_unused"
+DOM0_LOAD="ext4load mmc 2:1"
 DOM0_RAMDISK="dom0-ramdisk.cpio"
 DOM0_MEM=1024
 DOM0_VCPUS=1
@@ -46,11 +48,13 @@ DT_OVERLAY[0]="host_dt_overlay.dtbo"
 
 NUM_DOMUS=2
 DOMU_KERNEL[0]="zynqmp-dom1/Image-domU"
+DOMU_LOAD[0]="ext4load mmc 4:1"
 DOMU_PASSTHROUGH_PATHS[0]="/axi/ethernet@ff0e0000 /axi/serial@ff000000"
 DOMU_CMD[0]="console=ttyPS0 earlycon console=ttyPS0,115200 clk_ignore_unused rdinit=/sbin/init root=/dev/ram0 init=/bin/sh"
 DOMU_RAMDISK[0]="zynqmp-dom1/domU-ramdisk.cpio"
 DOMU_COLORS[0]="6-14"
 DOMU_KERNEL[1]="zynqmp-dom2/Image-domU"
+DOMU_LOAD[1]="ext4load mmc 5:1"
 DOMU_CMD[1]="console=ttyAMA0 clk_ignore_unused rdinit=/sbin/init root=/dev/ram0 init=/bin/sh"
 DOMU_RAMDISK[1]="zynqmp-dom2/domU-ramdisk.cpio"
 DOMU_MEM[1]=512
@@ -77,7 +81,9 @@ Where:
 - LOAD_CMD specifies the u-boot command used to load the binaries. This
   can be left out of the config and be (over)written by the -t CLI
   argument. It has to be set either in the config file or CLI argument
-  though.
+  though. This is optional when XEN is set as user can provide specific
+  options (ie XEN_LOAD, DOM0_LOAD, DOMU_LOAD) to load Xen, Dom0 and DomU
+  binaries.
 
 - BOOT_CMD specifies the u-boot command used to boot the binaries.
   By default, it is 'booti'. The acceptable values are 'booti', 'bootm',
@@ -99,6 +105,9 @@ Where:
 - XEN_CMD specifies the command line arguments used for Xen.  If not
   set, the default one will be used.
 
+- XEN_LOAD specifies the command to load XEN and DEVICE_TREE. If not set,
+  LOAD_CMD will be used.
+
 - XEN_STATIC_HEAP="baseaddr1 size1 ... baseaddrN sizeN"
   if specified, indicates the host physical address regions
   [baseaddr, baseaddr + size) to be reserved as Xen static heap.
@@ -109,6 +118,9 @@ Where:
   uboot-script-gen will compile the partial device trees which have
   been specified in DOMU_PASSTHROUGH_PATHS[number].
 
+- DOM0_LOAD specifies the command to load DOM0_KERNEL and DOM0_RAMDISK. If not
+  set, LOAD_CMD will be used.
+
 - DOM0_KERNEL specifies the Dom0 kernel file to load.
   For dom0less configurations, the parameter is optional.
 
@@ -159,6 +171,10 @@ Where:
   kernel. If not set and DOMU_VPL011[number] is not set to 0, then
   "console=ttyAMA0" is used.
 
+- DOMU_LOAD[number] specifies the command to load DOMU_KERNEL[number],
+  DOMU_RAMDISK[number] and DOMU_PASSTHROUGH_DTB[number]. If not set, then
+  LOAD_CMD is used.
+
 - DOMU_RAMDISK[number] specifies the DomU ramdisk to use.
 
 - DOMU_PASSTHROUGH_PATHS[number] specifies the passthrough devices (
diff --git a/scripts/uboot-script-gen b/scripts/uboot-script-gen
index b81e614..656de72 100755
--- a/scripts/uboot-script-gen
+++ b/scripts/uboot-script-gen
@@ -737,6 +737,7 @@ function load_file()
 {
     local filename=$1
     local fit_scr_name=$2
+    local load_cmd=$3
 
     local absolute_path="$(realpath --no-symlinks $filename)"
     local base="$(realpath $PWD)"/
@@ -748,10 +749,10 @@ function load_file()
         add_size_from_file $filename
     else
         if test "$CALC"; then
-            echo "$LOAD_CMD \${memaddr} ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
+            echo "$load_cmd \${memaddr} ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
             add_size_calculate $fit_scr_name
         else
-            echo "$LOAD_CMD $memaddr ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
+            echo "$load_cmd $memaddr ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
             add_size_from_file $filename
         fi
     fi
@@ -830,10 +831,10 @@ function check_compressed_file_type()
 
 function find_root_dev()
 {
-
-    local dev=${LOAD_CMD%:*}
+    local load_cmd="$1"
+    local dev=${load_cmd%:*}
     dev=${dev##* }
-    local par=${LOAD_CMD#*:}
+    local par=${load_cmd#*:}
 
     if [ -z "$dev" ] || [ -z "$par" ]
     then
@@ -844,10 +845,10 @@ function find_root_dev()
 
     par=$((par + 1))
 
-    if [[ $LOAD_CMD =~ mmc ]]
+    if [[ $load_cmd =~ mmc ]]
     then
         root_dev="/dev/mmcblk${dev}p${par}"
-    elif [[ $LOAD_CMD =~ scsi ]]
+    elif [[ $load_cmd =~ scsi ]]
     then
         # converts number to a scsi device character
         dev=$((dev + 97))
@@ -925,7 +926,7 @@ function xen_config()
         then
             DOM0_CMD="$DOM0_CMD root=/dev/ram0"
         else
-            find_root_dev
+            find_root_dev "$DOM0_LOAD"
             # $root_dev is set by find_root_dev
             DOM0_CMD="$DOM0_CMD root=$root_dev"
         fi
@@ -973,7 +974,7 @@ function linux_config()
         then
             LINUX_CMD="$LINUX_CMD root=/dev/ram0"
         else
-            find_root_dev
+            find_root_dev "$LOAD_CMD"
             # $root_dev is set by find_root_dev
             LINUX_CMD="$LINUX_CMD root=$root_dev"
         fi
@@ -1003,11 +1004,22 @@ generate_uboot_images()
 
 xen_file_loading()
 {
+    if test -z "$DOM0_LOAD"
+    then
+        if test "$LOAD_CMD"
+        then
+            DOM0_LOAD="$LOAD_CMD"
+        else
+            echo "Neither DOM0_LOAD nor LOAD_CMD is specified"
+            exit
+        fi
+    fi
+
     if test "$DOM0_KERNEL"
     then
         check_compressed_file_type $DOM0_KERNEL "executable\|uImage"
         dom0_kernel_addr=$memaddr
-        load_file $DOM0_KERNEL "dom0_linux"
+        load_file $DOM0_KERNEL "dom0_linux" "$DOM0_LOAD"
         dom0_kernel_size=$filesize
     fi
     if test "$DOM0_RAMDISK"
@@ -1015,7 +1027,7 @@ xen_file_loading()
         check_compressed_file_type $DOM0_RAMDISK "cpio archive"
         ramdisk_addr=$memaddr
         ramdisk_path=$DOM0_RAMDISK
-        load_file "$DOM0_RAMDISK" "dom0_ramdisk"
+        load_file "$DOM0_RAMDISK" "dom0_ramdisk" "$DOM0_LOAD"
         ramdisk_size=$filesize
     else
         ramdisk_addr="-"
@@ -1024,6 +1036,16 @@ xen_file_loading()
     i=0
     while test $i -lt $NUM_DOMUS
     do
+        if test -z "${DOMU_LOAD[$i]}"
+        then
+            if test "$LOAD_CMD"
+            then
+                DOMU_LOAD[$i]="$LOAD_CMD"
+            else
+                echo "Neither DOMU_LOAD[] nor LOAD_CMD is specified"
+                exit
+            fi
+        fi
         if test "${DOMU_ROOTFS[$i]}" || test "${DOMU_NOBOOT[$i]}"
         then
             if test -z "${DOMU_NOBOOT[$i]}"
@@ -1042,20 +1064,20 @@ xen_file_loading()
 
         check_compressed_file_type ${DOMU_KERNEL[$i]} "executable\|uImage"
         domU_kernel_addr[$i]=$memaddr
-        load_file ${DOMU_KERNEL[$i]} "domU${i}_kernel"
+        load_file ${DOMU_KERNEL[$i]} "domU${i}_kernel" "${DOMU_LOAD[$i]}"
         domU_kernel_size[$i]=$filesize
         if test "${DOMU_RAMDISK[$i]}"
         then
             check_compressed_file_type ${DOMU_RAMDISK[$i]} "cpio archive"
             domU_ramdisk_addr[$i]=$memaddr
-            load_file ${DOMU_RAMDISK[$i]} "domU${i}_ramdisk"
+            load_file ${DOMU_RAMDISK[$i]} "domU${i}_ramdisk" "${DOMU_LOAD[$i]}"
             domU_ramdisk_size[$i]=$filesize
         fi
         if test "${DOMU_PASSTHROUGH_DTB[$i]}"
         then
             check_compressed_file_type ${DOMU_PASSTHROUGH_DTB[$i]} "Device Tree Blob"
             domU_passthrough_dtb_addr[$i]=$memaddr
-            load_file ${DOMU_PASSTHROUGH_DTB[$i]} "domU${i}_fdt"
+            load_file ${DOMU_PASSTHROUGH_DTB[$i]} "domU${i}_fdt" "${DOMU_LOAD[$i]}"
             domU_passthrough_dtb_size[$i]=$filesize
         fi
         i=$(( $i + 1 ))
@@ -1070,9 +1092,20 @@ xen_file_loading()
         generate_uboot_images
     fi
 
+    if test -z "$XEN_LOAD"
+    then
+        if test "$LOAD_CMD"
+        then
+            XEN_LOAD="$LOAD_CMD"
+        else
+            echo "Neither XEN_LOAD nor LOAD_CMD is specified"
+            exit
+        fi
+    fi
+
     kernel_addr=$memaddr
     kernel_path=$XEN
-    load_file "$XEN" "host_kernel"
+    load_file "$XEN" "host_kernel" "$XEN_LOAD"
 
     xen_policy_addr="-"
     if test -n "$XEN_POLICY"
@@ -1518,12 +1551,6 @@ then
     FIT="${UBOOT_SOURCE%.source}.fit"
 fi
 
-if test ! "$LOAD_CMD"
-then
-    echo "LOAD_CMD not set, either specify it in the config or set it with the -t option"
-    exit 1
-fi
-
 if test ! "$BOOT_CMD"
 then
     BOOT_CMD="booti"
@@ -1543,6 +1570,11 @@ then
 elif test "$LINUX"
 then
     os="linux"
+    if test ! "$LOAD_CMD"
+    then
+        echo "LOAD_CMD not set, either specify it in the config or set it with the -t option"
+        exit 1
+    fi
     linux_config
 else
     echo "Neither a Xen or Linux kernel is specified, exiting"
@@ -1691,7 +1723,7 @@ fi
 
 check_file_type $DEVICE_TREE "Device Tree Blob"
 device_tree_addr=$memaddr
-load_file $DEVICE_TREE "host_fdt"
+load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
 bitstream_load_and_config  # bitstream is loaded last but used first
 device_tree_editing $device_tree_addr
 
-- 
2.25.1



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Subject: Re: [ImageBuilder] Add config option to use separate load commands
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To: Stefano Stabellini , Ayan Kumar Halder
	
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Hi Stefano,

On 11/08/2025 22:38, Stefano Stabellini wrote:
> On Wed, 6 Aug 2025, Ayan Kumar Halder wrote:
>> Introduce the following options :-
>> 1. XEN_LOAD - This specifies command to load xen hypervisor binary and device
>> tree.
>> 2. DOM0_LOAD - This specifies command to load Dom0 binaries.
>> 3. DOMU_LOAD[] - This specifies command to load DomU binaries.
>>
>> There can be situations where Xen, Dom0 and DomU binaries are stored in
>> different partitions. Thus, imagebuilder should provide a way the binaries
>> using different commands.
>>
>> If any of the above options are not specified, LOAD_CMD is used by default.
>>
>> Signed-off-by: Ayan Kumar Halder 
> The patch is correct and the new config options look good. Two things.
>
> The following check should be removed or, better, modified to account
> for the new options:
>
>      if test ! "$LOAD_CMD"
>      then
>          echo "LOAD_CMD not set, either specify it in the config or set it with the -t option"
>          exit 1
>      fi
>
> Thanks to this patch, it shouldn't be necessary to specify LOAD_CMD any
> longer.

Actually, we should keep this check when Linux is loaded (without Xen). IOW,

@@ -1557,6 +1551,11 @@ then
  elif test "$LINUX"
  then
      os="linux"
+    if test ! "$LOAD_CMD"
+    then
+        echo "LOAD_CMD not set, either specify it in the config or set 
it with the -t option"
+        exit 1
+    fi
      linux_config

>
> find_root_dev and fit are the only two remaining users of LOAD_CMD.
> While I think it makes sense to keep LOAD_CMD for fit, find_root_dev
> should probably use DOM0_LOAD instead.
yes.
>
> This incremental change (untested) should work. What do you think?
>
>
>
> diff --git a/scripts/uboot-script-gen b/scripts/uboot-script-gen
> index 9e97944..867876f 100755
> --- a/scripts/uboot-script-gen
> +++ b/scripts/uboot-script-gen
> @@ -824,10 +824,10 @@ function check_compressed_file_type()
>   
>   function find_root_dev()
>   {
> -
> -    local dev=${LOAD_CMD%:*}
> +    local load_cmd=$1
> +    local dev=${load_cmd%:*}
>       dev=${dev##* }
> -    local par=${LOAD_CMD#*:}
> +    local par=${load_cmd#*:}
>   
>       if [ -z "$dev" ] || [ -z "$par" ]
>       then
> @@ -838,10 +838,10 @@ function find_root_dev()
>   
>       par=$((par + 1))
>   
> -    if [[ $LOAD_CMD =~ mmc ]]
> +    if [[ $load_cmd =~ mmc ]]
>       then
>           root_dev="/dev/mmcblk${dev}p${par}"
> -    elif [[ $LOAD_CMD =~ scsi ]]
> +    elif [[ $load_cmd =~ scsi ]]
>       then
>           # converts number to a scsi device character
>           dev=$((dev + 97))
> @@ -912,7 +912,7 @@ function xen_config()
>           then
>               DOM0_CMD="$DOM0_CMD root=/dev/ram0"
>           else
> -            find_root_dev
> +            find_root_dev "$DOM0_LOAD"
>               # $root_dev is set by find_root_dev
>               DOM0_CMD="$DOM0_CMD root=$root_dev"
>           fi
> @@ -960,7 +960,7 @@ function linux_config()
>           then
>               LINUX_CMD="$LINUX_CMD root=/dev/ram0"
>           else
> -            find_root_dev
> +            find_root_dev "$LOAD_CMD"
>               # $root_dev is set by find_root_dev
>               LINUX_CMD="$LINUX_CMD root=$root_dev"
>           fi
Till here the change looks ok.
> @@ -990,10 +990,6 @@ generate_uboot_images()
>   
>   xen_file_loading()
>   {
> -    if test -z "$DOM0_LOAD"
> -    then
> -        DOM0_LOAD="$LOAD_CMD"
> -    fi
This and
>       if test "$DOM0_KERNEL"
>       then
>           check_compressed_file_type $DOM0_KERNEL "executable\|uImage"
> @@ -1065,11 +1061,6 @@ xen_file_loading()
>           generate_uboot_images
>       fi
>   
> -    if test -z "${XEN_LOAD}"
> -    then
> -        XEN_LOAD="$LOAD_CMD"
> -    fi
> -

this, I have a concern about moving the changes out of xen_file_loading()

In xen_file_loading(), we set DOM0_LOAD, XEN_LOAD and DOMU_LOAD[i]. With 
this change, we set DOM0_LOAD , XEN_LOAD at the beginning of the script 
and DOMU_LOAD[i] in the function. This looks a bit odd to me.

Further DOM0_LOAD and XEN_LOAD should be set only when "$XEN" is set.

I can leave the change as it is in the current patch or I can move them 
to xen_config().

Please let me know your thoughts.

I have sent "[ImageBuilder v2] Add config option to use separate load 
commands for Xen, DOM0 and DOMU binaries" so that it becomes a bit clear.

- Ayan

>       kernel_addr=$memaddr
>       kernel_path=$XEN
>       load_file "$XEN" "host_kernel" "$XEN_LOAD"
> @@ -1518,12 +1509,22 @@ then
>       FIT="${UBOOT_SOURCE%.source}.fit"
>   fi
>   
> -if test ! "$LOAD_CMD"
> +if test ! "$LOAD_CMD" && ! test "$XEN_LOAD"
>   then
>       echo "LOAD_CMD not set, either specify it in the config or set it with the -t option"
>       exit 1
>   fi
>   
> +if test -z "$DOM0_LOAD"
> +then
> +    DOM0_LOAD="$LOAD_CMD"
> +fi
> +
> +if test -z "${XEN_LOAD}"
> +then
> +    XEN_LOAD="$LOAD_CMD"
> +fi
> +
>   if test ! "$BOOT_CMD"
>   then
>       BOOT_CMD="booti"


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH] misra: add missing noreturn attribute for __div0()
Thread-Topic: [PATCH] misra: add missing noreturn attribute for __div0()
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Date: Tue, 12 Aug 2025 15:46:43 +0000
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The __div0() function never returns to its caller, causing a violation
of MISRA C Rule 2.1: "A project shall not contain unreachable code".
Add the `noreturn` attribute to fix this.

Signed-off-by: Dmytro Prokopchuk 
---
Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1980129839
---
 xen/arch/arm/traps.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 445e7378dd..2bc3e1df04 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -172,7 +172,7 @@ void init_traps(void)
     isb();
 }
=20
-void asmlinkage __div0(void)
+void asmlinkage noreturn __div0(void)
 {
     printk("Division by zero in hypervisor.\n");
     BUG();
--=20
2.43.0


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MIME-Version: 1.0
Date: Tue, 12 Aug 2025 17:49:35 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, Stefano Stabellini
 , Julien Grall , Bertrand Marquis
 , Michal Orzel , Volodymyr
 Babchuk 
Subject: Re: [PATCH] misra: add missing noreturn attribute for __div0()
In-Reply-To: <1b5549a97db31c65edb769302deff73576cec41d.1755013482.git.dmytro_prokopchuk1@epam.com>
References: <1b5549a97db31c65edb769302deff73576cec41d.1755013482.git.dmytro_prokopchuk1@epam.com>
Message-ID: <6aa50b8147d14e4d654f1291fc3b9cef@bugseng.com>
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On 2025-08-12 17:46, Dmytro Prokopchuk1 wrote:
> The __div0() function never returns to its caller, causing a violation
> of MISRA C Rule 2.1: "A project shall not contain unreachable code".
> Add the `noreturn` attribute to fix this.
> 

I was convinced that this was already upstream, as I made a patch a 
while ago, but evidently I forgot to send it.

> Signed-off-by: Dmytro Prokopchuk 

Reviewed-by: Nicola Vetrini 
> ---
> Test CI pipeline:
> https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1980129839
> ---
>  xen/arch/arm/traps.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> index 445e7378dd..2bc3e1df04 100644
> --- a/xen/arch/arm/traps.c
> +++ b/xen/arch/arm/traps.c
> @@ -172,7 +172,7 @@ void init_traps(void)
>      isb();
>  }
> 
> -void asmlinkage __div0(void)
> +void asmlinkage noreturn __div0(void)
>  {
>      printk("Division by zero in hypervisor.\n");
>      BUG();

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Tue, 12 Aug 2025 16:51:13 +0100
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Subject: Re: [PATCH] x86/boot: Remove unused symbols from linker script
To: Frediano Ziglio ,
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Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
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On 12/08/2025 4:19 pm, Frediano Ziglio wrote:
> The symbols declared with DECLARE_IMPORT are meant to be
> used by the 32 bit code.
> The __base_relocs_{start,end} symbols were not used by the
> code.
> No functional changes.
>
> Signed-off-by: Frediano Ziglio 

Reported-by: Jan

Reviewed-by: Andrew Cooper 

Can be fixed on commit.


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Date: Tue, 12 Aug 2025 17:58:54 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Stewart Hildebrand 
Cc: xen-devel@lists.xenproject.org, Jiqian Chen 
Subject: Re: [PATCH] vpci/msix: conditionally invoke vpci_make_msix_hole
Message-ID: 
References: <20250812151744.460953-1-stewart.hildebrand@amd.com>
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On Tue, Aug 12, 2025 at 11:17:42AM -0400, Stewart Hildebrand wrote:
> A hotplugged PCI device may be added uninitialized. In particular,
> memory decoding may be disabled and the BARs may be zeroed. In this
> case, the BARs will not be mapped in p2m. However, currently
> vpci_make_msix_hole is called unconditionally in init_msix, and the
> initialization fails in this case:
> 
> (XEN) d0v0 0000:01:00.0: existing mapping (mfn: 1c1880 type: 0) at 0 clobbers MSIX MMIO area
> (XEN) d0 0000:01:00.0: init legacy cap 17 fail rc=-17, mask it
> 
> vpci_make_msix_hole should only be called if the BARs containing the
> MSI-X/PBA tables are mapped in p2m.
> 
> Take the opportunity to fix a typo in the preceding comment.
> 
> Fixes: ee2eb6849d50 ("vpci: Refactor REGISTER_VPCI_INIT")
> Signed-off-by: Stewart Hildebrand 
> ---
>  xen/drivers/vpci/msix.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c
> index 54a5070733aa..39d1c45bd296 100644
> --- a/xen/drivers/vpci/msix.c
> +++ b/xen/drivers/vpci/msix.c
> @@ -705,10 +705,16 @@ static int cf_check init_msix(struct pci_dev *pdev)
>  
>      /*
>       * vPCI header initialization will have mapped the whole BAR into the
> -     * p2m, as MSI-X capability was not yet initialized.  Crave a hole for
> +     * p2m, as MSI-X capability was not yet initialized.  Carve a hole for
>       * the MSI-X table here, so that Xen can trap accesses.
>       */
> -    return vpci_make_msix_hole(pdev);
> +    if ( pdev->vpci->header.bars[
> +             msix->tables[VPCI_MSIX_TABLE] & PCI_MSIX_BIRMASK].enabled ||
> +         pdev->vpci->header.bars[
> +             msix->tables[VPCI_MSIX_PBA] & PCI_MSIX_BIRMASK].enabled )
> +        return vpci_make_msix_hole(pdev);

I think it might be better to place this checks inside of
vpci_make_msix_hole() itself, so that in case the guest moves the BAR
to an invalid position vpci_make_msix_hole() doesn't return error
either.

At the same time, you might want to introduce some helper to make this
less cumbersome, for example:

bool vmsix_table_bar_valid(const struct vpci *vpci, unsigned int nr)
{
    return vpci->header.bars[vpci->msix->tables[nr] &
                             PCI_MSIX_BIRMASK].enabled;
}

Note that if you adjust vpci_make_msix_hole() this way you will also
need to move the call in modify_decoding() so it happens strictly
after bar->enabled is set.

Thanks, Roger.


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Date: Tue, 12 Aug 2025 18:18:36 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: "xen-devel@lists.xenproject.org" ,
	Andrew Cooper 
Subject: Re: [PATCH v2 1/2] x86/mkelf32: pad load segment to 2Mb boundary
Message-ID: 
References: 
 <6e295921-0432-435e-9efe-51caa106f203@suse.com>
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On Mon, Aug 11, 2025 at 12:49:57PM +0200, Jan Beulich wrote:
> In order to legitimately set up initial mappings past _end[], we need
> to make sure that the entire mapped range is inside a RAM region.
> Therefore we need to inform the bootloader (or alike) that our allocated
> size is larger than just the next SECTION_ALIGN-ed boundary past _end[].
> 
> This allows dropping a command line option from the tool, which was
> introduced to work around a supposed linker bug, when the problem was
> really Xen's.
> 
> While adjusting adjacent code, correct the argc check to also cover the
> case correctly when --notes was passed.
> 
> Signed-off-by: Jan Beulich 
> ---
> There's no good Fixes: tag, I don't think, as in theory the issue could
> even have happened when we still required to be loaded at a fixed
> physical address (1Mb originally, later 2Mb), and when we statically
> mapped the low 16Mb. If we assumed such can't happen below 16Mb, these
> two should be added:
> Fixes: e4dd91ea85a3 ("x86: Ensure RAM holes really are not mapped in Xen's ongoing 1:1 physmap")
> Fixes: 7cd7f2f5e116 ("x86/boot: Remove the preconstructed low 16M superpage mappings")
> ---
> v2: New.
> 
> --- a/xen/arch/x86/Makefile
> +++ b/xen/arch/x86/Makefile
> @@ -130,8 +130,7 @@ orphan-handling-$(call ld-option,--orpha
>  
>  $(TARGET): TMP = $(dot-target).elf32
>  $(TARGET): $(TARGET)-syms $(efi-y) $(obj)/boot/mkelf32
> -	$(obj)/boot/mkelf32 $(notes_phdrs) $(TARGET)-syms $(TMP) $(XEN_IMG_OFFSET) \
> -	               `$(NM) $(TARGET)-syms | sed -ne 's/^\([^ ]*\) . __2M_rwdata_end$$/0x\1/p'`
> +	$(obj)/boot/mkelf32 $(notes_phdrs) $(TARGET)-syms $(TMP) $(XEN_IMG_OFFSET)
>  	od -t x4 -N 8192 $(TMP)  | grep 1badb002 > /dev/null || \
>  		{ echo "No Multiboot1 header found" >&2; false; }
>  	od -t x4 -N 32768 $(TMP) | grep e85250d6 > /dev/null || \
> --- a/xen/arch/x86/boot/mkelf32.c
> +++ b/xen/arch/x86/boot/mkelf32.c
> @@ -248,7 +248,6 @@ static void do_read(int fd, void *data,
>  
>  int main(int argc, char **argv)
>  {
> -    uint64_t   final_exec_addr;
>      uint32_t   loadbase, dat_siz, mem_siz, note_base, note_sz, offset;
>      char      *inimage, *outimage;
>      int        infd, outfd;
> @@ -261,22 +260,24 @@ int main(int argc, char **argv)
>      Elf64_Ehdr in64_ehdr;
>      Elf64_Phdr in64_phdr;
>  
> -    if ( argc < 5 )
> +    if ( argc < 4 )
>      {
> +    help:
>          fprintf(stderr, "Usage: mkelf32 [--notes]   "
> -                " \n");
> +                "\n");
>          return 1;
>      }
>  
>      if ( !strcmp(argv[1], "--notes") )
>      {
> +        if ( argc < 5 )
> +            goto help;
>          i = 2;
>          num_phdrs = 2;
>      }
>      inimage  = argv[i++];
>      outimage = argv[i++];
>      loadbase = strtoul(argv[i++], NULL, 16);
> -    final_exec_addr = strtoull(argv[i++], NULL, 16);
>  
>      infd = open(inimage, O_RDONLY);
>      if ( infd == -1 )
> @@ -339,9 +340,12 @@ int main(int argc, char **argv)
>      (void)lseek(infd, in64_phdr.p_offset, SEEK_SET);
>      dat_siz = (uint32_t)in64_phdr.p_filesz;
>  
> -    /* Do not use p_memsz: it does not include BSS alignment padding. */
> -    /*mem_siz = (uint32_t)in64_phdr.p_memsz;*/
> -    mem_siz = (uint32_t)(final_exec_addr - in64_phdr.p_vaddr);
> +    /*
> +     * We don't pad .bss in the linker script, but during early boot we map
> +     * the Xen image using 2M pages.  To avoid running into adjacent non-RAM
> +     * regions, pad the segment to the next 2M boundary.

Won't it be easier to pad in the linker script?  We could still have
__bss_end before the padding, so that initialization isn't done to the
extra padding area.  Otherwise it would be helpful to mention why the
padding must be done here (opposed to being done in the linker
script).

Thanks, Roger.


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From: Andrew Cooper 
To: Xen-devel 
Cc: Javi Merino ,
	Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Anthony PERARD 
Subject: [PATCH] CI: Turn debian/12-x86_64 into a non-root container
Date: Tue, 12 Aug 2025 17:29:50 +0100
Message-Id: <20250812162950.1903901-1-andrew.cooper3@citrix.com>
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From: Javi Merino 

Since commit 4611ae6fb8f9 ("CI: save toolstack artifact as cpio.gz"), the
various automation/scripts/* no longer need to be root to correctly repack the
initrd for test.

Signed-off-by: Javi Merino 
Signed-off-by: Andrew Cooper 
---
CC: Roger Pau Monné 
CC: Stefano Stabellini 
CC: Anthony PERARD 

Xen 4.20 and later uses debian:12-x86_64 and also contains 4611ae6fb8f9 so
this is safe to change generally.
---
 automation/build/debian/12-x86_64.dockerfile | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/automation/build/debian/12-x86_64.dockerfile b/automation/build/debian/12-x86_64.dockerfile
index e26a19079e38..3cf99c730b61 100644
--- a/automation/build/debian/12-x86_64.dockerfile
+++ b/automation/build/debian/12-x86_64.dockerfile
@@ -9,6 +9,8 @@ RUN <
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Date: Tue, 12 Aug 2025 18:30:27 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: "xen-devel@lists.xenproject.org" ,
	Andrew Cooper 
Subject: Re: [PATCH v2 2/2] x86/mm: drop unmapping from marking-as-I/O in
 arch_init_memory()
Message-ID: 
References: 
 <5a862787-40d8-4c9f-bd89-01d866648120@suse.com>
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On Mon, Aug 11, 2025 at 12:50:23PM +0200, Jan Beulich wrote:
> The unmapping part would have wanted to cover UNUSABLE regions as well,
> and it would now have been necessary for space outside the low 16Mb
> (wherever Xen is placed). However, with everything up to the next 2Mb
> boundary now properly backed by RAM, we don't need to unmap anything
> anymore: Space up to __2M_rwdata_end[] is properly reserved, whereas
> space past that mark (up to the next 2Mb boundary) is ordinary RAM.

Oh, I see, so this was done to unmap trailing space when the Xen image
region is mapped using 2M pages.

> While there, limit the scopes of involved variables.
> 
> Signed-off-by: Jan Beulich 

Acked-by: Roger Pau Monné 

> ---
> v2: Drop unmapping code altogether.
> 
> --- a/xen/arch/x86/mm.c
> +++ b/xen/arch/x86/mm.c
> @@ -275,8 +275,6 @@ static void __init assign_io_page(struct
>  
>  void __init arch_init_memory(void)
>  {
> -    unsigned long i, pfn, rstart_pfn, rend_pfn, iostart_pfn, ioend_pfn;
> -
>      /*
>       * Basic guest-accessible flags:
>       *   PRESENT, R/W, USER, A/D, AVAIL[0,1,2], AVAIL_HIGH, NX (if available).
> @@ -292,12 +290,17 @@ void __init arch_init_memory(void)
>       * case the low 1MB.
>       */
>      BUG_ON(pvh_boot && trampoline_phys != 0x1000);
> -    for ( i = 0; i < 0x100; i++ )
> +    for ( unsigned int i = 0; i < MB(1) >> PAGE_SHIFT; i++ )

I would use PFN_DOWN() rather than the shift, but that's just my
preference.

Thanks, Roger.


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Date:	Tue, 12 Aug 2025 19:02:11 +0200
From:	Daniel Kiper 
To:	Aaron Rainbolt 
Cc:	grub-devel@gnu.org, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 2/2] kern/xen: Add Xen command line parsing
Message-ID: <20250812170211.q7ezlveygfsdkz34@tomti.i.net-space.pl>
References: <20250804234816.3d14f53f@kf-m2g5>
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On Mon, Aug 04, 2025 at 11:50:09PM -0500, Aaron Rainbolt wrote:
> Xen traditionally allows customizing guest behavior by passing arguments
> to the VM kernel via the kernel command line. This is no longer possible
> when using GRUB with Xen, as the kernel command line is decided by the
> GRUB configuration file within the guest, not data passed to the guest
> by Xen.
>
> To work around this limitation, enable GRUB to parse a command line
> passed to it by Xen, and expose data from the command line to the GRUB
> configuration as environment variables. These variables can be used in
> the GRUB configuration for any desired purpose, such as extending the
> kernel command line passed to the guest. The command line format is
> inspired by the Linux kernel's command line format.
>
> To reduce the risk of misuse, abuse, or accidents in production, the
> command line will only be parsed if it consists entirely of 7-bit ASCII
> characters, only alphabetical characters and underscores are permitted
> in variable names, and all variable names must start with the string
> "xen_grub_env_". This also allows room for expanding the command line
> arguments accepted by GRUB in the future, should other arguments end up
> becoming desirable in the future.
>
> Signed-off-by: Aaron Rainbolt 
> ---
>  docs/grub.texi                |  51 +++++
>  grub-core/Makefile.core.def   |   2 +
>  grub-core/kern/i386/xen/pvh.c |  23 +++
>  grub-core/kern/xen/cmdline.c  | 376 ++++++++++++++++++++++++++++++++++
>  grub-core/kern/xen/init.c     |   2 +
>  include/grub/xen.h            |   2 +
>  6 files changed, 456 insertions(+)
>  create mode 100644 grub-core/kern/xen/cmdline.c
>
> diff --git a/docs/grub.texi b/docs/grub.texi
> index 34b3484..b58cf98 100644
> --- a/docs/grub.texi
> +++ b/docs/grub.texi
> @@ -3271,6 +3271,7 @@ GRUB.  Others may be used freely in GRUB configuration files.
>  @menu
>  * Special environment variables::
>  * Environment block::
> +* Passing environment variables through Xen::
>  @end menu
>
>
> @@ -3871,6 +3872,56 @@ using BIOS or EFI functions (no ATA, USB or IEEE1275).
>  @command{grub-mkconfig} uses this facility to implement
>  @samp{GRUB_SAVEDEFAULT} (@pxref{Simple configuration}).
>
> +@node Passing environment variables through Xen
> +@section Passing environment variables through Xen
> +
> +If you are using a GRUB image as the kernel for a PV or PVH Xen virtual
> +machine, you can pass environment variables from Xen's dom0 to the VM through
> +the Xen-provided kernel command line. When combined with a properly configured
> +guest, this can be used to customize the guest's behavior on bootup via the
> +VM's Xen configuration file.
> +
> +GRUB will parse the kernel command line passed to it by Xen during bootup.
> +The command line will be split into space-delimited words. Single and
> +double quotes may be used to quote words or portions of words that contain
> +spaces. Single quotes will be considered part of a word if inside double
> +quotes, and vice versa. Arbitrary characters may be backslash-escaped to make
> +them a literal component of a word rather than being parsed as quotes or word
> +separators. The command line must consist entirely of printable 7-bit ASCII
> +characters and spaces. If a non-printing ASCII character is found anywhere in
> +the command line, the entire command line will be ignored by GRUB.
> +
> +Each word should be a variable assignment in the format ``variable'' or
> +``variable=value''. Variable names must contain only the characters A-Z, a-z,
> +and underscore (``_''). Variable names must begin with the string
> +``xen_grub_env_''. Variable values can contain arbitrary printable 7-bit
> +ASCII characters and space. If any variable contains an illegal name, that
> +variable will be ignored.
> +
> +If a variable name and value are both specified, the variable will be set to
> +the specified value. If only a variable name is specified, the variable's
> +value will be set to ``1''.
> +
> +The following is a simple example of how to use this functionality to append
> +arbitrary variables to a guest's kernel command line:
> +
> +@example
> +# In the Xen configuration file for the guest
> +name = "linux_vm"
> +type = "pvh"
> +kernel = "/path/to/grub-i386-xen_pvh.bin"
> +extra = "xen_grub_env_linux_append='loglevel=3'"
> +memory = 1024
> +disk = [ "file:/srv/vms/linux_vm.img,sda,w" ]
> +
> +# In the guest's GRUB configuration file
> +menuentry "Linux VM with dom0-specified kernel parameters" @{
> +    search --set=root --label linux_vm --hint hd0,msdos1
> +    linux /boot/vmlinuz root=LABEL=linux_vm $@{xen_grub_env_linux_append@}
> +    initrd /boot/initrd.img
> +@}
> +@end example
> +
>  @node Modules
>  @chapter Modules
>
> diff --git a/grub-core/Makefile.core.def b/grub-core/Makefile.core.def
> index b3f7119..df0f266 100644
> --- a/grub-core/Makefile.core.def
> +++ b/grub-core/Makefile.core.def
> @@ -248,6 +248,7 @@ kernel = {
>    xen = term/xen/console.c;
>    xen = disk/xen/xendisk.c;
>    xen = commands/boot.c;
> +  xen = kern/xen/cmdline.c;
>
>    i386_xen_pvh = commands/boot.c;
>    i386_xen_pvh = disk/xen/xendisk.c;
> @@ -255,6 +256,7 @@ kernel = {
>    i386_xen_pvh = kern/i386/xen/tsc.c;
>    i386_xen_pvh = kern/i386/xen/pvh.c;
>    i386_xen_pvh = kern/xen/init.c;
> +  i386_xen_pvh = kern/xen/cmdline.c;
>    i386_xen_pvh = term/xen/console.c;
>
>    ia64_efi = kern/ia64/efi/startup.S;
> diff --git a/grub-core/kern/i386/xen/pvh.c b/grub-core/kern/i386/xen/pvh.c
> index 91fbca8..a8988d2 100644
> --- a/grub-core/kern/i386/xen/pvh.c
> +++ b/grub-core/kern/i386/xen/pvh.c
> @@ -321,6 +321,8 @@ void
>  grub_xen_setup_pvh (void)
>  {
>    grub_addr_t par;
> +  const char *xen_cmdline;
> +  int i;
>
>    grub_xen_cpuid_base ();
>    grub_xen_setup_hypercall_page ();
> @@ -352,6 +354,27 @@ grub_xen_setup_pvh (void)
>    grub_xen_mm_init_regions ();
>
>    grub_rsdp_addr = pvh_start_info->rsdp_paddr;
> +
> +  xen_cmdline = (const char *) pvh_start_info->cmdline_paddr;
> +  for (i = 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++)
> +    {
> +      if (xen_cmdline[i] == '\0')

This code still does not make a lot of sense for me. You have NUL check
in grub_parse_xen_cmdline(). So, you duplicate the check here...

I would just fire grub_strncpy() here and forget...

> +        {
> +          grub_strncpy ((char *) grub_xen_start_page_addr->cmd_line,
> +			(char *) pvh_start_info->cmdline_paddr,
> +			GRUB_XEN_MAX_GUEST_CMDLINE);
> +
> +          if (grub_xen_start_page_addr->cmd_line[GRUB_XEN_MAX_GUEST_CMDLINE - 1] != '\0')

If you convince me this code is still needed then I am afraid that this
is not what you meant here...

> +            {
> +              grub_error (GRUB_ERR_BUG,
> +			  "Xen command line is not NUL-terminated");
> +              grub_print_error ();
> +              grub_exit ();

grub_fatal() and you are done...

> +            }
> +
> +          break;
> +        }
> +    }
>  }
>
>  grub_err_t
> diff --git a/grub-core/kern/xen/cmdline.c b/grub-core/kern/xen/cmdline.c
> new file mode 100644
> index 0000000..46a9998
> --- /dev/null
> +++ b/grub-core/kern/xen/cmdline.c
> @@ -0,0 +1,376 @@
> +/*
> + *  GRUB  --  GRand Unified Bootloader
> + *  Copyright (C) 2025  Free Software Foundation, Inc.
> + *
> + *  GRUB is free software: you can redistribute it and/or modify
> + *  it under the terms of the GNU General Public License as published by
> + *  the Free Software Foundation, either version 3 of the License, or
> + *  (at your option) any later version.
> + *
> + *  GRUB is distributed in the hope that it will be useful,
> + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *  GNU General Public License for more details.
> + *
> + *  You should have received a copy of the GNU General Public License
> + *  along with GRUB.  If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +enum splitter_state
> +{
> +  SPLITTER_HIT_BACKSLASH = 0x1,
> +  SPLITTER_IN_SINGLE_QUOTES = 0x2,
> +  SPLITTER_IN_DOUBLE_QUOTES = 0x4,
> +};
> +typedef enum splitter_state splitter_state_t;
> +
> +/*
> + * The initial size of the current_word buffer. The buffer may be resized as
> + * needed.
> + */
> +#define PARSER_BASE_WORD_SIZE 32
> +
> +struct parser_state
> +{
> +  grub_size_t word_list_len;

s/word_list_len/words_count/

And I would put it behind word_list...

> +  char **word_list;

s/word_list/words/

> +  grub_size_t current_word_len;
> +  grub_size_t current_word_pos;
> +  char *current_word;
> +};
> +typedef struct parser_state parser_state_t;
> +
> +static bool

s/bool/grub_err_t/

> +append_char_to_word (parser_state_t *s, char c, bool allow_null)
> +{
> +  /*
> +   * We ban any chars that are not in the ASCII printable range. If
> +   * allow_null == true, we make an exception for NUL. (This is needed so that
> +   * append_word_to_list can add a NUL terminator to the word).
> +   */
> +  if (grub_isprint (c) == false && allow_null == false)

grub_isprint() et consortes return int instead of bool. So, it should be
"!grub_isprint(c)" here...

> +    return false;
> +  else if (allow_null == true && c != '\0')
> +    return false;
> +
> +  if (s->current_word_pos == s->current_word_len)
> +    {
> +      s->current_word = grub_realloc (s->current_word, s->current_word_len *= 2);
> +      if (s->current_word == NULL)
> +        {
> +          s->current_word_len /= 2;
> +          return false;
> +        }
> +    }
> +
> +  s->current_word[s->current_word_pos++] = c;
> +  return true;
> +}
> +
> +static bool

s/bool/grub_err_t/

> +append_word_to_list (parser_state_t *s)
> +{
> +  /* No-op on empty words. */
> +  if (s->current_word_pos == 0)
> +    return true;
> +
> +  if (append_char_to_word (s, '\0', true) == false)
> +    {
> +      grub_error (GRUB_ERR_BUG,
> +		  "couldn't append NUL terminator to word during Xen cmdline parsing");
> +      grub_print_error ();
> +      grub_exit ();

grub_fatal()

> +    }
> +
> +  s->current_word_len = grub_strlen (s->current_word) + 1;
> +  s->current_word = grub_realloc (s->current_word, s->current_word_len);
> +  if (s->current_word == NULL)
> +    return false;

return grub_errno;

> +  s->word_list = grub_realloc (s->word_list, ++s->word_list_len * sizeof (char *));
> +  if (s->word_list == NULL)
> +    return false;

return grub_errno;

...

I think many (related) functions in this code returning bool should
really return grub_err_t...

> +  s->word_list[s->word_list_len - 1] = s->current_word;
> +
> +  s->current_word_len = PARSER_BASE_WORD_SIZE;
> +  s->current_word_pos = 0;
> +  s->current_word = grub_malloc (s->current_word_len);
> +  if (s->current_word == NULL)
> +    return false;
> +
> +  return true;
> +}
> +
> +static bool

But this bool makes sense...

> +is_key_safe (char *key, grub_size_t len)
> +{
> +  grub_size_t i;
> +
> +  for (i = 0; i < len; i++)
> +    {
> +      if (! (grub_isalpha (key[i]) || key[i] == '_'))

Please drop space after "!"...

> +        return false;
> +    }

You can drop curly braces from here...

> +
> +  return true;
> +}
> +
> +void
> +grub_parse_xen_cmdline (void)
> +{
> +  parser_state_t *s = NULL;

parser_state_t ps = {0};

... and you do not need grub_malloc(s) and stuff any longer below...

And I would put it next to splitter_state...

> +  const char *cmdline = (const char *) grub_xen_start_page_addr->cmd_line;
> +  grub_size_t cmdline_len;
> +  bool cmdline_valid = false;
> +  char **param_keys = NULL;
> +  char **param_vals = NULL;
> +  grub_size_t param_dict_len = 0;
> +  grub_size_t param_dict_pos = 0;
> +  splitter_state_t splitter_state = 0;

You nicely define an enum and then assign plain number. Sigh...
I think you should define SPLITTER_NORMAL or something similar
as well...

And s/splitter_state/ss/...

> +  char current_char = '\0';
> +  grub_size_t i = 0;
> +
> +  s = grub_malloc (sizeof (parser_state_t));
> +  if (s == NULL)
> +    goto cleanup_final;
> +
> +  /*
> +   * The following algorithm is used to parse the Xen command line:
> +   *
> +   * - The command line is split into space-separated words.
> +   *   - Single and double quotes may be used to suppress the splitting
> +   *     behavior of spaces.
> +   *   - Double quotes are appended to the current word verbatim if they
> +   *     appear within a single-quoted string portion, and vice versa.
> +   *   - Backslashes may be used to cause the next character to be
> +   *     appended to the current word verbatim. This is only useful when
> +   *     used to escape quotes, spaces, and backslashes, but for simplicity
> +   *     we allow backslash-escaping anything.
> +   * - After splitting the command line into words, each word is checked to
> +   *   see if it contains an equals sign.
> +   *   - If it does, it is split on the equals sign into a key-value pair. The
> +   *     key is then treated as an variable name, and the value is treated as
> +   *     the variable's value.
> +   *   - If it does not, the entire word is treated as a variable name. The
> +   *     variable's value is implicitly considered to be `1`.
> +   * - All variables detected on the command line are checked to see if their
> +   *   names begin with the string `xen_grub_env_`. Variables that do not pass
> +   *   this check are discarded, variables that do pass this check are
> +   *   exported so they are available to the GRUB configuration.
> +   */
> +
> +  s->current_word_len = PARSER_BASE_WORD_SIZE;
> +  s->current_word = grub_malloc (s->current_word_len);
> +  if (s->current_word == NULL)
> +    goto cleanup_main;
> +
> +  for (i = 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++)
> +    {
> +      if (cmdline[i] == '\0')
> +        {
> +          cmdline_valid = true;
> +          break;
> +        }
> +    }
> +
> +  if (cmdline_valid == false)
> +    {
> +      grub_error (GRUB_ERR_BAD_ARGUMENT,
> +		  "command line from Xen is not NUL-terminated");
> +      grub_print_error ();

grub_fatal()?

> +      goto cleanup_main;
> +    }
> +
> +  cmdline_len = grub_strlen (cmdline);
> +  for (i = 0; i < cmdline_len; i++)
> +    {
> +      current_char = cmdline[i];
> +
> +      /*
> +       * If the previous character was a backslash, append the current
> +       * character to the word verbatim
> +       */
> +      if (splitter_state & SPLITTER_HIT_BACKSLASH)
> +        {
> +          splitter_state &= ~SPLITTER_HIT_BACKSLASH;
> +          if (append_char_to_word (s, current_char, false) == false)
> +            goto cleanup_main;
> +          continue;
> +        }
> +
> +      switch (current_char)
> +        {
> +        case '\\':
> +          /* Backslashes escape arbitrary characters. */
> +          splitter_state |= SPLITTER_HIT_BACKSLASH;
> +          continue;
> +
> +        case '\'':
> +          /*
> +           * Single quotes suppress word splitting and double quoting until
> +           * the next single quote is encountered.
> +           */
> +          if (splitter_state & SPLITTER_IN_DOUBLE_QUOTES)
> +            {
> +              if (append_char_to_word (s, current_char, false) == false)
> +                goto cleanup_main;
> +              continue;
> +            }
> +
> +          splitter_state ^= SPLITTER_IN_SINGLE_QUOTES;
> +          continue;
> +
> +        case '"':
> +          /*
> +           * Double quotes suppress word splitting and single quoting until
> +           * the next double quote is encountered.
> +           */
> +          if (splitter_state & SPLITTER_IN_SINGLE_QUOTES)
> +            {
> +              if (append_char_to_word (s, current_char, false) == false)
> +                goto cleanup_main;
> +              continue;
> +            }
> +
> +          splitter_state ^= SPLITTER_IN_DOUBLE_QUOTES;
> +          continue;
> +
> +        case ' ':
> +          /* Spaces separate words in the command line from each other. */
> +          if (splitter_state & SPLITTER_IN_SINGLE_QUOTES ||
> +              splitter_state & SPLITTER_IN_DOUBLE_QUOTES)
> +            {
> +              if (append_char_to_word (s, current_char, false) == false)
> +                goto cleanup_main;
> +              continue;
> +            }
> +
> +          if (append_word_to_list (s) == false)
> +            goto cleanup_main;

I think this is not fully correct. You should not run append_word_to_list()
until the closing quote. So, here you should have "else" for the first "if",
i.e., "if (splitter_state & ..." and call append_word_to_list() for closing
\" and \' above.

> +          continue;
> +        }
> +
> +      if (append_char_to_word (s, current_char, false) == false)
> +        goto cleanup_main;

This should be part of "default:" for the switch above... Even if it
works now...

Then many "continue" should be converted to more natural "break"...

> +    }
> +
> +  if (append_word_to_list (s) == false)
> +    goto cleanup_main;
> +
> +  param_keys = grub_malloc (s->word_list_len * sizeof (char *));
> +  if (param_keys == NULL)
> +    goto cleanup_main;
> +  param_vals = grub_malloc (s->word_list_len * sizeof (char *));
> +  if (param_vals == NULL)
> +    goto cleanup_main;
> +
> +  for (i = 0; i < s->word_list_len; i++)
> +    {
> +      char *current_word_eq_ptr;

s/current_word_eq_ptr/eq_pos/

> +      s->current_word = s->word_list[i];
> +      s->current_word_len = grub_strlen (s->current_word) + 1;
> +      current_word_eq_ptr = grub_strchr (s->current_word, '=');
> +
> +      if (current_word_eq_ptr != NULL)
> +        {
> +          /*
> +           * Both pre_eq_len and post_eq_len represent substring lengths
> +           * without a NUL terminator.
> +           */
> +          grub_size_t pre_eq_len = (grub_size_t) (current_word_eq_ptr - s->current_word);
> +          /*
> +           * s->current_word_len includes the NUL terminator, so we subtract
> +           * one to get rid of the terminator, and one more to get rid of the
> +           * equals sign.
> +           */
> +          grub_size_t post_eq_len = (s->current_word_len - 2) - pre_eq_len;
> +
> +          if (is_key_safe (s->current_word, pre_eq_len) == true)
> +            {
> +              param_dict_pos = param_dict_len++;
> +              param_keys[param_dict_pos] = grub_malloc (pre_eq_len + 1);
> +              if (param_keys == NULL)
> +                goto cleanup_main;
> +              param_vals[param_dict_pos] = grub_malloc (post_eq_len + 1);
> +              if (param_vals == NULL)
> +                goto cleanup_main;
> +
> +              grub_strncpy (param_keys[param_dict_pos], s->current_word, pre_eq_len);
> +              grub_strncpy (param_vals[param_dict_pos],
> +			    s->current_word + pre_eq_len + 1, post_eq_len);
> +              param_keys[param_dict_pos][pre_eq_len] = '\0';
> +              param_vals[param_dict_pos][post_eq_len] = '\0';
> +            }
> +        }
> +      else

else if (is_key_safe (s->current_word, s->current_word_len - 1) == true)

... and you can drop an extra indention...

> +        {
> +          if (is_key_safe (s->current_word, s->current_word_len - 1) == true)
> +            {
> +              param_dict_pos = param_dict_len++;
> +              param_keys[param_dict_pos] = grub_malloc (s->current_word_len);
> +              if (param_keys == NULL)
> +                goto cleanup_main;
> +              param_vals[param_dict_pos] = grub_malloc (2);
> +              if (param_vals == NULL)
> +                goto cleanup_main;
> +
> +              grub_strncpy (param_keys[param_dict_pos], s->current_word,
> +			    s->current_word_len);
> +              if (param_keys[param_dict_pos][s->current_word_len - 1] != '\0' )
> +                {
> +                  grub_error (GRUB_ERR_BUG,
> +			      "NUL terminator missing from key during Xen cmdline parsing");
> +                  grub_print_error ();
> +                  grub_exit ();

grub_fatal()

> +                }
> +              grub_strcpy (param_vals[param_dict_pos], "1");
> +            }
> +        }
> +    }

Daniel


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There are systems where device tree binary is passed by the U-Boot as
$fdtcontroladdr. In such cases, no external device tree binary is provided
during uboot script generation.

This is an enhancement on top of the following commit:-
uboot-script-gen: Dynamically compute addr and size when loading bina…

When DEVICE_TREE is not present, user should provide '-s' as the addresses and
sizes should be computed dynamically from U-Boot.

Also, fixed uboot-script-gen to set host_kernel_addr when BOOT_CMD="none" and
'-s' is not used.

Signed-off-by: Ayan Kumar Halder 
---
This patch should be applied after the previous patch.
"[ImageBuilder v2] Add config option to use separate load commands for..."

Changes from :-

v1 :- 1. Check that user provides '-s' when DEVICE_TREE is not set, instead of
setting CALC silently.

2. Set 'host_fdt_addr' to '\${fdtcontroladdr}' when DEVICE_TREE is not set.

3. Add a fix for BOOT_CMD="none".
 
 README.md                |  5 ++++-
 scripts/uboot-script-gen | 29 +++++++++++++++++++++++------
 2 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/README.md b/README.md
index 59919df..fc448e0 100644
--- a/README.md
+++ b/README.md
@@ -92,7 +92,10 @@ Where:
   DTB are stored in 'host_kernel_addr' and 'host_fdt_addr' u-boot
   env variables respectively, to be used manually when booting.
 
-- DEVICE_TREE specifies the DTB file to load.
+- DEVICE_TREE specifies the DTB file to load. If not set, then $fdtcontroladdr
+  is used as the address of the DTB loaded by u-boot. If user does not set this
+  option, then '-s' should be provided to ensure that addresses and sizes are
+  calculated dynamically by uboot.
 
 - XEN specifies the Xen hypervisor binary to load. Note that it has to
   be a regular Xen binary, not a u-boot binary.
diff --git a/scripts/uboot-script-gen b/scripts/uboot-script-gen
index 656de72..be61fc4 100755
--- a/scripts/uboot-script-gen
+++ b/scripts/uboot-script-gen
@@ -591,7 +591,7 @@ function device_tree_editing()
 
 function fill_reserved_spaces_from_dtb()
 {
-    if [ ! -f $DEVICE_TREE ]
+    if test ! -f $DEVICE_TREE || test -z "$DEVICE_TREE"
     then
         if test "$CALC"; then
             return
@@ -1674,6 +1674,16 @@ fi
 
 rm -f $UBOOT_SOURCE $UBOOT_SCRIPT
 
+if test -z "$DEVICE_TREE"
+then
+    if test -z "$CALC"
+    then
+       echo "DEVICE_TREE is unset and -s is not specified"
+       exit 1
+    fi
+    echo "setenv host_fdt_addr \${fdtcontroladdr}" >> $UBOOT_SOURCE
+fi
+
 if test "$FIT"
 then
     echo 'fit_addr=$fileaddr' >>  $UBOOT_SOURCE
@@ -1721,9 +1731,13 @@ then
     done
 fi
 
-check_file_type $DEVICE_TREE "Device Tree Blob"
-device_tree_addr=$memaddr
-load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
+if test "$DEVICE_TREE"
+then
+    check_file_type $DEVICE_TREE "Device Tree Blob"
+    device_tree_addr=$memaddr
+    load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
+fi
+
 bitstream_load_and_config  # bitstream is loaded last but used first
 device_tree_editing $device_tree_addr
 
@@ -1751,8 +1765,11 @@ then
     fi
 else
     # skip boot command but store load addresses to be used later
-    echo "setenv host_kernel_addr $kernel_addr" >> $UBOOT_SOURCE
-    echo "setenv host_fdt_addr $device_tree_addr" >> $UBOOT_SOURCE
+    if test -z "$CALC"
+    then
+        echo "setenv host_kernel_addr $kernel_addr" >> $UBOOT_SOURCE
+        echo "setenv host_fdt_addr $device_tree_addr" >> $UBOOT_SOURCE
+    fi
 fi
 
 if test "$FIT"
-- 
2.25.1



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Date: Tue, 12 Aug 2025 18:34:59 +0100
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Subject: Re: [ImageBuilder] Make DEVICE_TREE optional parameter
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To: Stefano Stabellini , Ayan Kumar Halder
	
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	, 
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Hi Stefano,

On 12/08/2025 00:13, Stefano Stabellini wrote:
> On Thu, 7 Aug 2025, Ayan Kumar Halder wrote:
>> There are systems where device tree binary is passed by the U-Boot as
>> $fdtcontroladdr. In such cases, no external device tree binary is provided
>> during uboot script generation.
>>
>> This is an enhancement on top of the following commit:-
>> uboot-script-gen: Dynamically compute addr and size when loading bina…
>>
>> When DEVICE_TREE is not present, $CALC is set as the addresses and sizes should
>> be computed dynamically from U-Boot.
> I would prefer if we did not automatically enable $CALC. If it doesn't
> work without $CALC enabled, we could add a check for it and print an
> error and exit. I would prefer that then enabling $CALC silently.
Ack
>
> Also I don't think we should use the check ${DEVICE_TREE+x}. I'd prefer
> to stick with the existing checks based on test ${DEVICE_TREE}.
Ack
>
> The rest looks OK.
>
> It might be possible to simplify this patch down to this (untested).
> The last chunk of the diff is actually an unrelated fix, it looks like
> we didn't test BOOT_CMD="none" when the -s option was introduced.
>
> What do you think?

Slightly changed the chunk. With that it works well.

I have sent "[ImageBuilder v2] Make DEVICE_TREE optional parameter" for 
review.

- Ayan



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Date: Tue, 12 Aug 2025 19:14:54 +0100
From: Lorenzo Stoakes 
To: David Hildenbrand 
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
        xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org,
        nvdimm@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
        Andrew Morton ,
        Madhavan Srinivasan ,
        Michael Ellerman ,
        Nicholas Piggin ,
        Christophe Leroy ,
        Juergen Gross ,
        Stefano Stabellini ,
        Oleksandr Tyshchenko ,
        Dan Williams ,
        Matthew Wilcox , Jan Kara ,
        Alexander Viro ,
        Christian Brauner ,
        "Liam R. Howlett" ,
        Vlastimil Babka , Mike Rapoport ,
        Suren Baghdasaryan , Michal Hocko ,
        Zi Yan , Baolin Wang ,
        Nico Pache , Ryan Roberts ,
        Dev Jain , Barry Song ,
        Jann Horn , Pedro Falcato ,
        Hugh Dickins , Oscar Salvador ,
        Lance Yang 
Subject: Re: [PATCH v3 05/11] mm/huge_memory: mark PMD mappings of the huge
 zero folio special
Message-ID: <511317b9-7155-40c7-91e0-faf134622b9d@lucifer.local>
References: <20250811112631.759341-1-david@redhat.com>
 <20250811112631.759341-6-david@redhat.com>
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On Mon, Aug 11, 2025 at 01:26:25PM +0200, David Hildenbrand wrote:
> The huge zero folio is refcounted (+mapcounted -- is that a word?)
> differently than "normal" folios, similarly (but different) to the ordinary
> shared zeropage.
>
> For this reason, we special-case these pages in
> vm_normal_page*/vm_normal_folio*, and only allow selected callers to
> still use them (e.g., GUP can still take a reference on them).

Hm, interestingly in gup_fast_pmd_leaf() we explicitly check pmd_special(),
so surely setting the zero huge pmd special will change behaviour there?

But I guess this is actually _more_ correct as it's not really sensible to
grab the huge zero PMD page.

Then again, follow_huge_pmd() _will_, afaict.

I see the GUP fast change was introduced by commit ae3c99e650da ("mm/gup:
detect huge pfnmap entries in gup-fast") so was specifically intended for
pfnmap not the zero page.

>
> vm_normal_page_pmd() already filters out the huge zero folio, to
> indicate it a special (return NULL). However, so far we are not making
> use of pmd_special() on architectures that support it
> (CONFIG_ARCH_HAS_PTE_SPECIAL), like we would with the ordinary shared
> zeropage.
>
> Let's mark PMD mappings of the huge zero folio similarly as special, so we
> can avoid the manual check for the huge zero folio with
> CONFIG_ARCH_HAS_PTE_SPECIAL next, and only perform the check on
> !CONFIG_ARCH_HAS_PTE_SPECIAL.
>
> In copy_huge_pmd(), where we have a manual pmd_special() check to handle
> PFNMAP, we have to manually rule out the huge zero folio. That code
> needs a serious cleanup, but that's something for another day.
>
> While at it, update the doc regarding the shared zero folios.
>
> No functional change intended: vm_normal_page_pmd() still returns NULL
> when it encounters the huge zero folio.
>
> Reviewed-by: Oscar Salvador 
> Signed-off-by: David Hildenbrand 

I R-b this before, and Wei did also, did you drop because of changes?

Anyway, apart from query about GUP-fast above, this LGTM so:

Reviewed-by: Lorenzo Stoakes 

> ---
>  mm/huge_memory.c |  8 ++++++--
>  mm/memory.c      | 15 ++++++++++-----
>  2 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/mm/huge_memory.c b/mm/huge_memory.c
> index ec89e0607424e..58bac83e7fa31 100644
> --- a/mm/huge_memory.c
> +++ b/mm/huge_memory.c
> @@ -1309,6 +1309,7 @@ static void set_huge_zero_folio(pgtable_t pgtable, struct mm_struct *mm,
>  {
>  	pmd_t entry;
>  	entry = folio_mk_pmd(zero_folio, vma->vm_page_prot);
> +	entry = pmd_mkspecial(entry);
>  	pgtable_trans_huge_deposit(mm, pmd, pgtable);
>  	set_pmd_at(mm, haddr, pmd, entry);
>  	mm_inc_nr_ptes(mm);
> @@ -1418,7 +1419,9 @@ static vm_fault_t insert_pmd(struct vm_area_struct *vma, unsigned long addr,
>  	if (fop.is_folio) {
>  		entry = folio_mk_pmd(fop.folio, vma->vm_page_prot);
>
> -		if (!is_huge_zero_folio(fop.folio)) {
> +		if (is_huge_zero_folio(fop.folio)) {
> +			entry = pmd_mkspecial(entry);
> +		} else {
>  			folio_get(fop.folio);
>  			folio_add_file_rmap_pmd(fop.folio, &fop.folio->page, vma);
>  			add_mm_counter(mm, mm_counter_file(fop.folio), HPAGE_PMD_NR);
> @@ -1643,7 +1646,8 @@ int copy_huge_pmd(struct mm_struct *dst_mm, struct mm_struct *src_mm,
>  	int ret = -ENOMEM;
>
>  	pmd = pmdp_get_lockless(src_pmd);
> -	if (unlikely(pmd_present(pmd) && pmd_special(pmd))) {
> +	if (unlikely(pmd_present(pmd) && pmd_special(pmd) &&
> +		     !is_huge_zero_pmd(pmd))) {

OK yeah this is new I see from cover letter + ranged-diff.

Yeah this is important actually wow, as otherwise the is_huge_zero_pmd()
branch will not be executed.

Good spot!

>  		dst_ptl = pmd_lock(dst_mm, dst_pmd);
>  		src_ptl = pmd_lockptr(src_mm, src_pmd);
>  		spin_lock_nested(src_ptl, SINGLE_DEPTH_NESTING);
> diff --git a/mm/memory.c b/mm/memory.c
> index 0ba4f6b718471..626caedce35e0 100644
> --- a/mm/memory.c
> +++ b/mm/memory.c
> @@ -555,7 +555,14 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
>   *
>   * "Special" mappings do not wish to be associated with a "struct page" (either
>   * it doesn't exist, or it exists but they don't want to touch it). In this
> - * case, NULL is returned here. "Normal" mappings do have a struct page.
> + * case, NULL is returned here. "Normal" mappings do have a struct page and
> + * are ordinarily refcounted.
> + *
> + * Page mappings of the shared zero folios are always considered "special", as
> + * they are not ordinarily refcounted: neither the refcount nor the mapcount
> + * of these folios is adjusted when mapping them into user page tables.
> + * Selected page table walkers (such as GUP) can still identify mappings of the
> + * shared zero folios and work with the underlying "struct page".

Thanks for this.

>   *
>   * There are 2 broad cases. Firstly, an architecture may define a pte_special()
>   * pte bit, in which case this function is trivial. Secondly, an architecture
> @@ -585,9 +592,8 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
>   *
>   * VM_MIXEDMAP mappings can likewise contain memory with or without "struct
>   * page" backing, however the difference is that _all_ pages with a struct
> - * page (that is, those where pfn_valid is true) are refcounted and considered
> - * normal pages by the VM. The only exception are zeropages, which are
> - * *never* refcounted.
> + * page (that is, those where pfn_valid is true, except the shared zero
> + * folios) are refcounted and considered normal pages by the VM.
>   *
>   * The disadvantage is that pages are refcounted (which can be slower and
>   * simply not an option for some PFNMAP users). The advantage is that we
> @@ -667,7 +673,6 @@ struct page *vm_normal_page_pmd(struct vm_area_struct *vma, unsigned long addr,
>  {
>  	unsigned long pfn = pmd_pfn(pmd);
>
> -	/* Currently it's only used for huge pfnmaps */
>  	if (unlikely(pmd_special(pmd)))
>  		return NULL;
>
> --
> 2.50.1
>


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Date: Tue, 12 Aug 2025 21:22:31 +0300
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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH] BCM2711 reboot fix
To: Julien Grall 
Cc: xen-devel@lists.xenproject.org,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Volodymyr Babchuk , miro@contentwise.tech
References: <1754252178882.7.40484@webmail-backend-production-957f95bc8-4zxxx>
 
Content-Language: en-US
From: Evgeny Beysembaev 
In-Reply-To: 
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Sorry, this is quite a rare experience for me. I'll prepare a new 
submission in a separate thread. Thanks

Evgeny

On 12.08.2025 01:22, Julien Grall wrote:
> Hi Evgeny,
>
> (Top-posting because this is related to the process)
>
> Thank you for sending a new version of the patch. I am having trouble 
> to apply this patch properly using "b4". It seems to add more content 
> in the git log. E.g.:
>
>     Message-ID: 
> <0057d145ddd90c01922636205484088c02a0e45a.1748380800.git.megabotva@gmail.com>
>     From: Evgeny Beysembaev 
>     Date: Tue, 27 May 2025 13:48:31 +0200
>     Subject: [PATCH] BCM2711 reboot fix
>
> Looking at the content of the e-mail in more details, I see you posted 
> the new version as a reply to the previous patch. So it contains some
> part of the previous answer. Patches submission should be on their own 
> email (ideally in a new thread) with the subject contain the tag 
> [PATCH v] where  is the revision ID (in your case it should be 
> two).
>
>
> On 03/08/2025 21:16, Evgeny Beysembaev wrote:
>> According to the commit b334c1afad17 ("ARM: dts: bcm2711: Use proper 
>> compatible in PM/Watchdog node")
>> in Linux kernel, the `compatible` string for the watchdog peripheral 
>> in the DTS has been modified from
>> `brcm,bcm2835-pm` to `brcm,bcm2711-pm`, which caused 
>> `rpi4_map_watchdog()` function to fail,
>> leading to inability to reboot the system under Xen hypervisor.
>
> On my e-mail client, the lines will be wrapped. But when applied, you 
> have some lines well over 72 characters. Please re-wrapped the commit 
> message.
>
> For more details how to submit a patch, I would suggest to read:
>
> https://wiki.xenproject.org/wiki/Submitting_Xen_Project_Patches
>
> Patch diff itself looks good to me.
>
> Cheers,
>



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Date: Tue, 12 Aug 2025 19:23:48 +0100
From: Lorenzo Stoakes 
To: David Hildenbrand 
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
        xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org,
        nvdimm@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
        Andrew Morton ,
        Madhavan Srinivasan ,
        Michael Ellerman ,
        Nicholas Piggin ,
        Christophe Leroy ,
        Juergen Gross ,
        Stefano Stabellini ,
        Oleksandr Tyshchenko ,
        Dan Williams ,
        Matthew Wilcox , Jan Kara ,
        Alexander Viro ,
        Christian Brauner ,
        "Liam R. Howlett" ,
        Vlastimil Babka , Mike Rapoport ,
        Suren Baghdasaryan , Michal Hocko ,
        Zi Yan , Baolin Wang ,
        Nico Pache , Ryan Roberts ,
        Dev Jain , Barry Song ,
        Jann Horn , Pedro Falcato ,
        Hugh Dickins , Oscar Salvador ,
        Lance Yang 
Subject: Re: [PATCH v3 06/11] powerpc/ptdump: rename "struct pgtable_level"
 to "struct ptdump_pglevel"
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On Mon, Aug 11, 2025 at 01:26:26PM +0200, David Hildenbrand wrote:
> We want to make use of "pgtable_level" for an enum in core-mm. Other
> architectures seem to call "struct pgtable_level" either:
> * "struct pg_level" when not exposed in a header (riscv, arm)
> * "struct ptdump_pg_level" when expose in a header (arm64)
>
> So let's follow what arm64 does.
>
> Signed-off-by: David Hildenbrand 

This LGTM, but I'm super confused what these are for, they don't seem to be
used anywhere? Maybe I'm missing some macro madness, but it seems like dead
code anyway?

Anyway:

Reviewed-by: Lorenzo Stoakes 

> ---
>  arch/powerpc/mm/ptdump/8xx.c      | 2 +-
>  arch/powerpc/mm/ptdump/book3s64.c | 2 +-
>  arch/powerpc/mm/ptdump/ptdump.h   | 4 ++--
>  arch/powerpc/mm/ptdump/shared.c   | 2 +-
>  4 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/mm/ptdump/8xx.c b/arch/powerpc/mm/ptdump/8xx.c
> index b5c79b11ea3c2..4ca9cf7a90c9e 100644
> --- a/arch/powerpc/mm/ptdump/8xx.c
> +++ b/arch/powerpc/mm/ptdump/8xx.c
> @@ -69,7 +69,7 @@ static const struct flag_info flag_array[] = {
>  	}
>  };
>
> -struct pgtable_level pg_level[5] = {
> +struct ptdump_pg_level pg_level[5] = {
>  	{ /* pgd */
>  		.flag	= flag_array,
>  		.num	= ARRAY_SIZE(flag_array),
> diff --git a/arch/powerpc/mm/ptdump/book3s64.c b/arch/powerpc/mm/ptdump/book3s64.c
> index 5ad92d9dc5d10..6b2da9241d4c4 100644
> --- a/arch/powerpc/mm/ptdump/book3s64.c
> +++ b/arch/powerpc/mm/ptdump/book3s64.c
> @@ -102,7 +102,7 @@ static const struct flag_info flag_array[] = {
>  	}
>  };
>
> -struct pgtable_level pg_level[5] = {
> +struct ptdump_pg_level pg_level[5] = {
>  	{ /* pgd */
>  		.flag	= flag_array,
>  		.num	= ARRAY_SIZE(flag_array),
> diff --git a/arch/powerpc/mm/ptdump/ptdump.h b/arch/powerpc/mm/ptdump/ptdump.h
> index 154efae96ae09..4232aa4b57eae 100644
> --- a/arch/powerpc/mm/ptdump/ptdump.h
> +++ b/arch/powerpc/mm/ptdump/ptdump.h
> @@ -11,12 +11,12 @@ struct flag_info {
>  	int		shift;
>  };
>
> -struct pgtable_level {
> +struct ptdump_pg_level {
>  	const struct flag_info *flag;
>  	size_t num;
>  	u64 mask;
>  };
>
> -extern struct pgtable_level pg_level[5];
> +extern struct ptdump_pg_level pg_level[5];
>
>  void pt_dump_size(struct seq_file *m, unsigned long delta);
> diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
> index 39c30c62b7ea7..58998960eb9a4 100644
> --- a/arch/powerpc/mm/ptdump/shared.c
> +++ b/arch/powerpc/mm/ptdump/shared.c
> @@ -67,7 +67,7 @@ static const struct flag_info flag_array[] = {
>  	}
>  };
>
> -struct pgtable_level pg_level[5] = {
> +struct ptdump_pg_level pg_level[5] = {
>  	{ /* pgd */
>  		.flag	= flag_array,
>  		.num	= ARRAY_SIZE(flag_array),
> --
> 2.50.1
>


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Date: Tue, 12 Aug 2025 19:33:06 +0100
From: Lorenzo Stoakes 
To: David Hildenbrand 
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
        xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org,
        nvdimm@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
        Andrew Morton ,
        Madhavan Srinivasan ,
        Michael Ellerman ,
        Nicholas Piggin ,
        Christophe Leroy ,
        Juergen Gross ,
        Stefano Stabellini ,
        Oleksandr Tyshchenko ,
        Dan Williams ,
        Matthew Wilcox , Jan Kara ,
        Alexander Viro ,
        Christian Brauner ,
        "Liam R. Howlett" ,
        Vlastimil Babka , Mike Rapoport ,
        Suren Baghdasaryan , Michal Hocko ,
        Zi Yan , Baolin Wang ,
        Nico Pache , Ryan Roberts ,
        Dev Jain , Barry Song ,
        Jann Horn , Pedro Falcato ,
        Hugh Dickins , Oscar Salvador ,
        Lance Yang 
Subject: Re: [PATCH v3 07/11] mm/rmap: convert "enum rmap_level" to "enum
 pgtable_level"
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References: <20250811112631.759341-1-david@redhat.com>
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On Mon, Aug 11, 2025 at 01:26:27PM +0200, David Hildenbrand wrote:
> Let's factor it out, and convert all checks for unsupported levels to
> BUILD_BUG(). The code is written in a way such that force-inlining will
> optimize out the levels.
>
> Signed-off-by: David Hildenbrand 

Nice cleanup! This LGTM, so:

Reviewed-by: Lorenzo Stoakes 

> ---
>  include/linux/pgtable.h |  8 ++++++
>  include/linux/rmap.h    | 60 +++++++++++++++++++----------------------
>  mm/rmap.c               | 56 +++++++++++++++++++++-----------------
>  3 files changed, 66 insertions(+), 58 deletions(-)
>
> diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
> index 4c035637eeb77..bff5c4241bf2e 100644
> --- a/include/linux/pgtable.h
> +++ b/include/linux/pgtable.h
> @@ -1958,6 +1958,14 @@ static inline bool arch_has_pfn_modify_check(void)
>  /* Page-Table Modification Mask */
>  typedef unsigned int pgtbl_mod_mask;
>
> +enum pgtable_level {
> +	PGTABLE_LEVEL_PTE = 0,
> +	PGTABLE_LEVEL_PMD,
> +	PGTABLE_LEVEL_PUD,
> +	PGTABLE_LEVEL_P4D,
> +	PGTABLE_LEVEL_PGD,
> +};
> +
>  #endif /* !__ASSEMBLY__ */
>
>  #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT)
> diff --git a/include/linux/rmap.h b/include/linux/rmap.h
> index 6cd020eea37a2..9d40d127bdb78 100644
> --- a/include/linux/rmap.h
> +++ b/include/linux/rmap.h
> @@ -394,18 +394,8 @@ typedef int __bitwise rmap_t;
>  /* The anonymous (sub)page is exclusive to a single process. */
>  #define RMAP_EXCLUSIVE		((__force rmap_t)BIT(0))
>
> -/*
> - * Internally, we're using an enum to specify the granularity. We make the
> - * compiler emit specialized code for each granularity.
> - */
> -enum rmap_level {
> -	RMAP_LEVEL_PTE = 0,
> -	RMAP_LEVEL_PMD,
> -	RMAP_LEVEL_PUD,
> -};
> -
>  static inline void __folio_rmap_sanity_checks(const struct folio *folio,
> -		const struct page *page, int nr_pages, enum rmap_level level)
> +		const struct page *page, int nr_pages, enum pgtable_level level)
>  {
>  	/* hugetlb folios are handled separately. */
>  	VM_WARN_ON_FOLIO(folio_test_hugetlb(folio), folio);
> @@ -427,18 +417,18 @@ static inline void __folio_rmap_sanity_checks(const struct folio *folio,
>  	VM_WARN_ON_FOLIO(page_folio(page + nr_pages - 1) != folio, folio);
>
>  	switch (level) {
> -	case RMAP_LEVEL_PTE:
> +	case PGTABLE_LEVEL_PTE:
>  		break;
> -	case RMAP_LEVEL_PMD:
> +	case PGTABLE_LEVEL_PMD:
>  		/*
>  		 * We don't support folios larger than a single PMD yet. So
> -		 * when RMAP_LEVEL_PMD is set, we assume that we are creating
> +		 * when PGTABLE_LEVEL_PMD is set, we assume that we are creating
>  		 * a single "entire" mapping of the folio.
>  		 */
>  		VM_WARN_ON_FOLIO(folio_nr_pages(folio) != HPAGE_PMD_NR, folio);
>  		VM_WARN_ON_FOLIO(nr_pages != HPAGE_PMD_NR, folio);
>  		break;
> -	case RMAP_LEVEL_PUD:
> +	case PGTABLE_LEVEL_PUD:
>  		/*
>  		 * Assume that we are creating a single "entire" mapping of the
>  		 * folio.
> @@ -447,7 +437,7 @@ static inline void __folio_rmap_sanity_checks(const struct folio *folio,
>  		VM_WARN_ON_FOLIO(nr_pages != HPAGE_PUD_NR, folio);
>  		break;
>  	default:
> -		VM_WARN_ON_ONCE(true);
> +		BUILD_BUG();
>  	}
>
>  	/*
> @@ -567,14 +557,14 @@ static inline void hugetlb_remove_rmap(struct folio *folio)
>
>  static __always_inline void __folio_dup_file_rmap(struct folio *folio,
>  		struct page *page, int nr_pages, struct vm_area_struct *dst_vma,
> -		enum rmap_level level)
> +		enum pgtable_level level)
>  {
>  	const int orig_nr_pages = nr_pages;
>
>  	__folio_rmap_sanity_checks(folio, page, nr_pages, level);
>
>  	switch (level) {
> -	case RMAP_LEVEL_PTE:
> +	case PGTABLE_LEVEL_PTE:
>  		if (!folio_test_large(folio)) {
>  			atomic_inc(&folio->_mapcount);
>  			break;
> @@ -587,11 +577,13 @@ static __always_inline void __folio_dup_file_rmap(struct folio *folio,
>  		}
>  		folio_add_large_mapcount(folio, orig_nr_pages, dst_vma);
>  		break;
> -	case RMAP_LEVEL_PMD:
> -	case RMAP_LEVEL_PUD:
> +	case PGTABLE_LEVEL_PMD:
> +	case PGTABLE_LEVEL_PUD:
>  		atomic_inc(&folio->_entire_mapcount);
>  		folio_inc_large_mapcount(folio, dst_vma);
>  		break;
> +	default:
> +		BUILD_BUG();
>  	}
>  }
>
> @@ -609,13 +601,13 @@ static __always_inline void __folio_dup_file_rmap(struct folio *folio,
>  static inline void folio_dup_file_rmap_ptes(struct folio *folio,
>  		struct page *page, int nr_pages, struct vm_area_struct *dst_vma)
>  {
> -	__folio_dup_file_rmap(folio, page, nr_pages, dst_vma, RMAP_LEVEL_PTE);
> +	__folio_dup_file_rmap(folio, page, nr_pages, dst_vma, PGTABLE_LEVEL_PTE);
>  }
>
>  static __always_inline void folio_dup_file_rmap_pte(struct folio *folio,
>  		struct page *page, struct vm_area_struct *dst_vma)
>  {
> -	__folio_dup_file_rmap(folio, page, 1, dst_vma, RMAP_LEVEL_PTE);
> +	__folio_dup_file_rmap(folio, page, 1, dst_vma, PGTABLE_LEVEL_PTE);
>  }
>
>  /**
> @@ -632,7 +624,7 @@ static inline void folio_dup_file_rmap_pmd(struct folio *folio,
>  		struct page *page, struct vm_area_struct *dst_vma)
>  {
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> -	__folio_dup_file_rmap(folio, page, HPAGE_PMD_NR, dst_vma, RMAP_LEVEL_PTE);
> +	__folio_dup_file_rmap(folio, page, HPAGE_PMD_NR, dst_vma, PGTABLE_LEVEL_PTE);
>  #else
>  	WARN_ON_ONCE(true);
>  #endif
> @@ -640,7 +632,7 @@ static inline void folio_dup_file_rmap_pmd(struct folio *folio,
>
>  static __always_inline int __folio_try_dup_anon_rmap(struct folio *folio,
>  		struct page *page, int nr_pages, struct vm_area_struct *dst_vma,
> -		struct vm_area_struct *src_vma, enum rmap_level level)
> +		struct vm_area_struct *src_vma, enum pgtable_level level)
>  {
>  	const int orig_nr_pages = nr_pages;
>  	bool maybe_pinned;
> @@ -665,7 +657,7 @@ static __always_inline int __folio_try_dup_anon_rmap(struct folio *folio,
>  	 * copying if the folio maybe pinned.
>  	 */
>  	switch (level) {
> -	case RMAP_LEVEL_PTE:
> +	case PGTABLE_LEVEL_PTE:
>  		if (unlikely(maybe_pinned)) {
>  			for (i = 0; i < nr_pages; i++)
>  				if (PageAnonExclusive(page + i))
> @@ -687,8 +679,8 @@ static __always_inline int __folio_try_dup_anon_rmap(struct folio *folio,
>  		} while (page++, --nr_pages > 0);
>  		folio_add_large_mapcount(folio, orig_nr_pages, dst_vma);
>  		break;
> -	case RMAP_LEVEL_PMD:
> -	case RMAP_LEVEL_PUD:
> +	case PGTABLE_LEVEL_PMD:
> +	case PGTABLE_LEVEL_PUD:
>  		if (PageAnonExclusive(page)) {
>  			if (unlikely(maybe_pinned))
>  				return -EBUSY;
> @@ -697,6 +689,8 @@ static __always_inline int __folio_try_dup_anon_rmap(struct folio *folio,
>  		atomic_inc(&folio->_entire_mapcount);
>  		folio_inc_large_mapcount(folio, dst_vma);
>  		break;
> +	default:
> +		BUILD_BUG();
>  	}
>  	return 0;
>  }
> @@ -730,7 +724,7 @@ static inline int folio_try_dup_anon_rmap_ptes(struct folio *folio,
>  		struct vm_area_struct *src_vma)
>  {
>  	return __folio_try_dup_anon_rmap(folio, page, nr_pages, dst_vma,
> -					 src_vma, RMAP_LEVEL_PTE);
> +					 src_vma, PGTABLE_LEVEL_PTE);
>  }
>
>  static __always_inline int folio_try_dup_anon_rmap_pte(struct folio *folio,
> @@ -738,7 +732,7 @@ static __always_inline int folio_try_dup_anon_rmap_pte(struct folio *folio,
>  		struct vm_area_struct *src_vma)
>  {
>  	return __folio_try_dup_anon_rmap(folio, page, 1, dst_vma, src_vma,
> -					 RMAP_LEVEL_PTE);
> +					 PGTABLE_LEVEL_PTE);
>  }
>
>  /**
> @@ -770,7 +764,7 @@ static inline int folio_try_dup_anon_rmap_pmd(struct folio *folio,
>  {
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
>  	return __folio_try_dup_anon_rmap(folio, page, HPAGE_PMD_NR, dst_vma,
> -					 src_vma, RMAP_LEVEL_PMD);
> +					 src_vma, PGTABLE_LEVEL_PMD);
>  #else
>  	WARN_ON_ONCE(true);
>  	return -EBUSY;
> @@ -778,7 +772,7 @@ static inline int folio_try_dup_anon_rmap_pmd(struct folio *folio,
>  }
>
>  static __always_inline int __folio_try_share_anon_rmap(struct folio *folio,
> -		struct page *page, int nr_pages, enum rmap_level level)
> +		struct page *page, int nr_pages, enum pgtable_level level)
>  {
>  	VM_WARN_ON_FOLIO(!folio_test_anon(folio), folio);
>  	VM_WARN_ON_FOLIO(!PageAnonExclusive(page), folio);
> @@ -873,7 +867,7 @@ static __always_inline int __folio_try_share_anon_rmap(struct folio *folio,
>  static inline int folio_try_share_anon_rmap_pte(struct folio *folio,
>  		struct page *page)
>  {
> -	return __folio_try_share_anon_rmap(folio, page, 1, RMAP_LEVEL_PTE);
> +	return __folio_try_share_anon_rmap(folio, page, 1, PGTABLE_LEVEL_PTE);
>  }
>
>  /**
> @@ -904,7 +898,7 @@ static inline int folio_try_share_anon_rmap_pmd(struct folio *folio,
>  {
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
>  	return __folio_try_share_anon_rmap(folio, page, HPAGE_PMD_NR,
> -					   RMAP_LEVEL_PMD);
> +					   PGTABLE_LEVEL_PMD);
>  #else
>  	WARN_ON_ONCE(true);
>  	return -EBUSY;
> diff --git a/mm/rmap.c b/mm/rmap.c
> index 84a8d8b02ef77..0e9c4041f8687 100644
> --- a/mm/rmap.c
> +++ b/mm/rmap.c
> @@ -1265,7 +1265,7 @@ static void __folio_mod_stat(struct folio *folio, int nr, int nr_pmdmapped)
>
>  static __always_inline void __folio_add_rmap(struct folio *folio,
>  		struct page *page, int nr_pages, struct vm_area_struct *vma,
> -		enum rmap_level level)
> +		enum pgtable_level level)
>  {
>  	atomic_t *mapped = &folio->_nr_pages_mapped;
>  	const int orig_nr_pages = nr_pages;
> @@ -1274,7 +1274,7 @@ static __always_inline void __folio_add_rmap(struct folio *folio,
>  	__folio_rmap_sanity_checks(folio, page, nr_pages, level);
>
>  	switch (level) {
> -	case RMAP_LEVEL_PTE:
> +	case PGTABLE_LEVEL_PTE:
>  		if (!folio_test_large(folio)) {
>  			nr = atomic_inc_and_test(&folio->_mapcount);
>  			break;
> @@ -1300,11 +1300,11 @@ static __always_inline void __folio_add_rmap(struct folio *folio,
>
>  		folio_add_large_mapcount(folio, orig_nr_pages, vma);
>  		break;
> -	case RMAP_LEVEL_PMD:
> -	case RMAP_LEVEL_PUD:
> +	case PGTABLE_LEVEL_PMD:
> +	case PGTABLE_LEVEL_PUD:
>  		first = atomic_inc_and_test(&folio->_entire_mapcount);
>  		if (IS_ENABLED(CONFIG_NO_PAGE_MAPCOUNT)) {
> -			if (level == RMAP_LEVEL_PMD && first)
> +			if (level == PGTABLE_LEVEL_PMD && first)
>  				nr_pmdmapped = folio_large_nr_pages(folio);
>  			nr = folio_inc_return_large_mapcount(folio, vma);
>  			if (nr == 1)
> @@ -1323,7 +1323,7 @@ static __always_inline void __folio_add_rmap(struct folio *folio,
>  				 * We only track PMD mappings of PMD-sized
>  				 * folios separately.
>  				 */
> -				if (level == RMAP_LEVEL_PMD)
> +				if (level == PGTABLE_LEVEL_PMD)
>  					nr_pmdmapped = nr_pages;
>  				nr = nr_pages - (nr & FOLIO_PAGES_MAPPED);
>  				/* Raced ahead of a remove and another add? */
> @@ -1336,6 +1336,8 @@ static __always_inline void __folio_add_rmap(struct folio *folio,
>  		}
>  		folio_inc_large_mapcount(folio, vma);
>  		break;
> +	default:
> +		BUILD_BUG();
>  	}
>  	__folio_mod_stat(folio, nr, nr_pmdmapped);
>  }
> @@ -1427,7 +1429,7 @@ static void __page_check_anon_rmap(const struct folio *folio,
>
>  static __always_inline void __folio_add_anon_rmap(struct folio *folio,
>  		struct page *page, int nr_pages, struct vm_area_struct *vma,
> -		unsigned long address, rmap_t flags, enum rmap_level level)
> +		unsigned long address, rmap_t flags, enum pgtable_level level)
>  {
>  	int i;
>
> @@ -1440,20 +1442,22 @@ static __always_inline void __folio_add_anon_rmap(struct folio *folio,
>
>  	if (flags & RMAP_EXCLUSIVE) {
>  		switch (level) {
> -		case RMAP_LEVEL_PTE:
> +		case PGTABLE_LEVEL_PTE:
>  			for (i = 0; i < nr_pages; i++)
>  				SetPageAnonExclusive(page + i);
>  			break;
> -		case RMAP_LEVEL_PMD:
> +		case PGTABLE_LEVEL_PMD:
>  			SetPageAnonExclusive(page);
>  			break;
> -		case RMAP_LEVEL_PUD:
> +		case PGTABLE_LEVEL_PUD:
>  			/*
>  			 * Keep the compiler happy, we don't support anonymous
>  			 * PUD mappings.
>  			 */
>  			WARN_ON_ONCE(1);
>  			break;
> +		default:
> +			BUILD_BUG();
>  		}
>  	}
>
> @@ -1507,7 +1511,7 @@ void folio_add_anon_rmap_ptes(struct folio *folio, struct page *page,
>  		rmap_t flags)
>  {
>  	__folio_add_anon_rmap(folio, page, nr_pages, vma, address, flags,
> -			      RMAP_LEVEL_PTE);
> +			      PGTABLE_LEVEL_PTE);
>  }
>
>  /**
> @@ -1528,7 +1532,7 @@ void folio_add_anon_rmap_pmd(struct folio *folio, struct page *page,
>  {
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
>  	__folio_add_anon_rmap(folio, page, HPAGE_PMD_NR, vma, address, flags,
> -			      RMAP_LEVEL_PMD);
> +			      PGTABLE_LEVEL_PMD);
>  #else
>  	WARN_ON_ONCE(true);
>  #endif
> @@ -1609,7 +1613,7 @@ void folio_add_new_anon_rmap(struct folio *folio, struct vm_area_struct *vma,
>
>  static __always_inline void __folio_add_file_rmap(struct folio *folio,
>  		struct page *page, int nr_pages, struct vm_area_struct *vma,
> -		enum rmap_level level)
> +		enum pgtable_level level)
>  {
>  	VM_WARN_ON_FOLIO(folio_test_anon(folio), folio);
>
> @@ -1634,7 +1638,7 @@ static __always_inline void __folio_add_file_rmap(struct folio *folio,
>  void folio_add_file_rmap_ptes(struct folio *folio, struct page *page,
>  		int nr_pages, struct vm_area_struct *vma)
>  {
> -	__folio_add_file_rmap(folio, page, nr_pages, vma, RMAP_LEVEL_PTE);
> +	__folio_add_file_rmap(folio, page, nr_pages, vma, PGTABLE_LEVEL_PTE);
>  }
>
>  /**
> @@ -1651,7 +1655,7 @@ void folio_add_file_rmap_pmd(struct folio *folio, struct page *page,
>  		struct vm_area_struct *vma)
>  {
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> -	__folio_add_file_rmap(folio, page, HPAGE_PMD_NR, vma, RMAP_LEVEL_PMD);
> +	__folio_add_file_rmap(folio, page, HPAGE_PMD_NR, vma, PGTABLE_LEVEL_PMD);
>  #else
>  	WARN_ON_ONCE(true);
>  #endif
> @@ -1672,7 +1676,7 @@ void folio_add_file_rmap_pud(struct folio *folio, struct page *page,
>  {
>  #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
>  	defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
> -	__folio_add_file_rmap(folio, page, HPAGE_PUD_NR, vma, RMAP_LEVEL_PUD);
> +	__folio_add_file_rmap(folio, page, HPAGE_PUD_NR, vma, PGTABLE_LEVEL_PUD);
>  #else
>  	WARN_ON_ONCE(true);
>  #endif
> @@ -1680,7 +1684,7 @@ void folio_add_file_rmap_pud(struct folio *folio, struct page *page,
>
>  static __always_inline void __folio_remove_rmap(struct folio *folio,
>  		struct page *page, int nr_pages, struct vm_area_struct *vma,
> -		enum rmap_level level)
> +		enum pgtable_level level)
>  {
>  	atomic_t *mapped = &folio->_nr_pages_mapped;
>  	int last = 0, nr = 0, nr_pmdmapped = 0;
> @@ -1689,7 +1693,7 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
>  	__folio_rmap_sanity_checks(folio, page, nr_pages, level);
>
>  	switch (level) {
> -	case RMAP_LEVEL_PTE:
> +	case PGTABLE_LEVEL_PTE:
>  		if (!folio_test_large(folio)) {
>  			nr = atomic_add_negative(-1, &folio->_mapcount);
>  			break;
> @@ -1719,11 +1723,11 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
>
>  		partially_mapped = nr && atomic_read(mapped);
>  		break;
> -	case RMAP_LEVEL_PMD:
> -	case RMAP_LEVEL_PUD:
> +	case PGTABLE_LEVEL_PMD:
> +	case PGTABLE_LEVEL_PUD:
>  		if (IS_ENABLED(CONFIG_NO_PAGE_MAPCOUNT)) {
>  			last = atomic_add_negative(-1, &folio->_entire_mapcount);
> -			if (level == RMAP_LEVEL_PMD && last)
> +			if (level == PGTABLE_LEVEL_PMD && last)
>  				nr_pmdmapped = folio_large_nr_pages(folio);
>  			nr = folio_dec_return_large_mapcount(folio, vma);
>  			if (!nr) {
> @@ -1743,7 +1747,7 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
>  			nr = atomic_sub_return_relaxed(ENTIRELY_MAPPED, mapped);
>  			if (likely(nr < ENTIRELY_MAPPED)) {
>  				nr_pages = folio_large_nr_pages(folio);
> -				if (level == RMAP_LEVEL_PMD)
> +				if (level == PGTABLE_LEVEL_PMD)
>  					nr_pmdmapped = nr_pages;
>  				nr = nr_pages - (nr & FOLIO_PAGES_MAPPED);
>  				/* Raced ahead of another remove and an add? */
> @@ -1757,6 +1761,8 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
>
>  		partially_mapped = nr && nr < nr_pmdmapped;
>  		break;
> +	default:
> +		BUILD_BUG();
>  	}
>
>  	/*
> @@ -1796,7 +1802,7 @@ static __always_inline void __folio_remove_rmap(struct folio *folio,
>  void folio_remove_rmap_ptes(struct folio *folio, struct page *page,
>  		int nr_pages, struct vm_area_struct *vma)
>  {
> -	__folio_remove_rmap(folio, page, nr_pages, vma, RMAP_LEVEL_PTE);
> +	__folio_remove_rmap(folio, page, nr_pages, vma, PGTABLE_LEVEL_PTE);
>  }
>
>  /**
> @@ -1813,7 +1819,7 @@ void folio_remove_rmap_pmd(struct folio *folio, struct page *page,
>  		struct vm_area_struct *vma)
>  {
>  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> -	__folio_remove_rmap(folio, page, HPAGE_PMD_NR, vma, RMAP_LEVEL_PMD);
> +	__folio_remove_rmap(folio, page, HPAGE_PMD_NR, vma, PGTABLE_LEVEL_PMD);
>  #else
>  	WARN_ON_ONCE(true);
>  #endif
> @@ -1834,7 +1840,7 @@ void folio_remove_rmap_pud(struct folio *folio, struct page *page,
>  {
>  #if defined(CONFIG_TRANSPARENT_HUGEPAGE) && \
>  	defined(CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD)
> -	__folio_remove_rmap(folio, page, HPAGE_PUD_NR, vma, RMAP_LEVEL_PUD);
> +	__folio_remove_rmap(folio, page, HPAGE_PUD_NR, vma, PGTABLE_LEVEL_PUD);
>  #else
>  	WARN_ON_ONCE(true);
>  #endif
> --
> 2.50.1
>


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Date: Tue, 12 Aug 2025 19:48:07 +0100
From: Lorenzo Stoakes 
To: David Hildenbrand 
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
        xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org,
        nvdimm@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
        Andrew Morton ,
        Madhavan Srinivasan ,
        Michael Ellerman ,
        Nicholas Piggin ,
        Christophe Leroy ,
        Juergen Gross ,
        Stefano Stabellini ,
        Oleksandr Tyshchenko ,
        Dan Williams ,
        Matthew Wilcox , Jan Kara ,
        Alexander Viro ,
        Christian Brauner ,
        "Liam R. Howlett" ,
        Vlastimil Babka , Mike Rapoport ,
        Suren Baghdasaryan , Michal Hocko ,
        Zi Yan , Baolin Wang ,
        Nico Pache , Ryan Roberts ,
        Dev Jain , Barry Song ,
        Jann Horn , Pedro Falcato ,
        Hugh Dickins , Oscar Salvador ,
        Lance Yang 
Subject: Re: [PATCH v3 08/11] mm/memory: convert print_bad_pte() to
 print_bad_page_map()
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References: <20250811112631.759341-1-david@redhat.com>
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On Mon, Aug 11, 2025 at 01:26:28PM +0200, David Hildenbrand wrote:
> print_bad_pte() looks like something that should actually be a WARN
> or similar, but historically it apparently has proven to be useful to
> detect corruption of page tables even on production systems -- report
> the issue and keep the system running to make it easier to actually detect
> what is going wrong (e.g., multiple such messages might shed a light).
>
> As we want to unify vm_normal_page_*() handling for PTE/PMD/PUD, we'll have
> to take care of print_bad_pte() as well.
>
> Let's prepare for using print_bad_pte() also for non-PTEs by adjusting the
> implementation and renaming the function to print_bad_page_map().
> Provide print_bad_pte() as a simple wrapper.
>
> Document the implicit locking requirements for the page table re-walk.
>
> To make the function a bit more readable, factor out the ratelimit check
> into is_bad_page_map_ratelimited() and place the printing of page
> table content into __print_bad_page_map_pgtable(). We'll now dump
> information from each level in a single line, and just stop the table
> walk once we hit something that is not a present page table.
>
> The report will now look something like (dumping pgd to pmd values):
>
> [   77.943408] BUG: Bad page map in process XXX  pte:80000001233f5867
> [   77.944077] addr:00007fd84bb1c000 vm_flags:08100071 anon_vma: ...
> [   77.945186] pgd:10a89f067 p4d:10a89f067 pud:10e5a2067 pmd:105327067
>
> Not using pgdp_get(), because that does not work properly on some arm
> configs where pgd_t is an array. Note that we are dumping all levels
> even when levels are folded for simplicity.
>
> Signed-off-by: David Hildenbrand 

This LGTM, great explanations and thanks for the page table level stuff!

Reviewed-by: Lorenzo Stoakes 

> ---
>  include/linux/pgtable.h |  19 ++++++++
>  mm/memory.c             | 104 ++++++++++++++++++++++++++++++++--------
>  2 files changed, 103 insertions(+), 20 deletions(-)
>
> diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
> index bff5c4241bf2e..33c84b38b7ec6 100644
> --- a/include/linux/pgtable.h
> +++ b/include/linux/pgtable.h
> @@ -1966,6 +1966,25 @@ enum pgtable_level {
>  	PGTABLE_LEVEL_PGD,
>  };
>
> +static inline const char *pgtable_level_to_str(enum pgtable_level level)
> +{
> +	switch (level) {
> +	case PGTABLE_LEVEL_PTE:
> +		return "pte";
> +	case PGTABLE_LEVEL_PMD:
> +		return "pmd";
> +	case PGTABLE_LEVEL_PUD:
> +		return "pud";
> +	case PGTABLE_LEVEL_P4D:
> +		return "p4d";
> +	case PGTABLE_LEVEL_PGD:
> +		return "pgd";
> +	default:
> +		VM_WARN_ON_ONCE(1);
> +		return "unknown";
> +	}
> +}
> +
>  #endif /* !__ASSEMBLY__ */
>
>  #if !defined(MAX_POSSIBLE_PHYSMEM_BITS) && !defined(CONFIG_64BIT)
> diff --git a/mm/memory.c b/mm/memory.c
> index 626caedce35e0..dc0107354d37b 100644
> --- a/mm/memory.c
> +++ b/mm/memory.c
> @@ -491,22 +491,8 @@ static inline void add_mm_rss_vec(struct mm_struct *mm, int *rss)
>  			add_mm_counter(mm, i, rss[i]);
>  }
>
> -/*
> - * This function is called to print an error when a bad pte
> - * is found. For example, we might have a PFN-mapped pte in
> - * a region that doesn't allow it.
> - *
> - * The calling function must still handle the error.
> - */
> -static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
> -			  pte_t pte, struct page *page)
> +static bool is_bad_page_map_ratelimited(void)
>  {
> -	pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
> -	p4d_t *p4d = p4d_offset(pgd, addr);
> -	pud_t *pud = pud_offset(p4d, addr);
> -	pmd_t *pmd = pmd_offset(pud, addr);
> -	struct address_space *mapping;
> -	pgoff_t index;
>  	static unsigned long resume;
>  	static unsigned long nr_shown;
>  	static unsigned long nr_unshown;
> @@ -518,7 +504,7 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
>  	if (nr_shown == 60) {
>  		if (time_before(jiffies, resume)) {
>  			nr_unshown++;
> -			return;
> +			return true;
>  		}
>  		if (nr_unshown) {
>  			pr_alert("BUG: Bad page map: %lu messages suppressed\n",
> @@ -529,15 +515,91 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
>  	}
>  	if (nr_shown++ == 0)
>  		resume = jiffies + 60 * HZ;
> +	return false;
> +}
> +
> +static void __print_bad_page_map_pgtable(struct mm_struct *mm, unsigned long addr)
> +{
> +	unsigned long long pgdv, p4dv, pudv, pmdv;
> +	p4d_t p4d, *p4dp;
> +	pud_t pud, *pudp;
> +	pmd_t pmd, *pmdp;
> +	pgd_t *pgdp;
> +
> +	/*
> +	 * Although this looks like a fully lockless pgtable walk, it is not:
> +	 * see locking requirements for print_bad_page_map().
> +	 */

Thanks

> +	pgdp = pgd_offset(mm, addr);
> +	pgdv = pgd_val(*pgdp);
> +
> +	if (!pgd_present(*pgdp) || pgd_leaf(*pgdp)) {
> +		pr_alert("pgd:%08llx\n", pgdv);
> +		return;
> +	}
> +
> +	p4dp = p4d_offset(pgdp, addr);
> +	p4d = p4dp_get(p4dp);
> +	p4dv = p4d_val(p4d);
> +
> +	if (!p4d_present(p4d) || p4d_leaf(p4d)) {
> +		pr_alert("pgd:%08llx p4d:%08llx\n", pgdv, p4dv);
> +		return;
> +	}
> +
> +	pudp = pud_offset(p4dp, addr);
> +	pud = pudp_get(pudp);
> +	pudv = pud_val(pud);
> +
> +	if (!pud_present(pud) || pud_leaf(pud)) {
> +		pr_alert("pgd:%08llx p4d:%08llx pud:%08llx\n", pgdv, p4dv, pudv);
> +		return;
> +	}
> +
> +	pmdp = pmd_offset(pudp, addr);
> +	pmd = pmdp_get(pmdp);
> +	pmdv = pmd_val(pmd);
> +
> +	/*
> +	 * Dumping the PTE would be nice, but it's tricky with CONFIG_HIGHPTE,

Sigh, 32-bit.

> +	 * because the table should already be mapped by the caller and
> +	 * doing another map would be bad. print_bad_page_map() should
> +	 * already take care of printing the PTE.
> +	 */
> +	pr_alert("pgd:%08llx p4d:%08llx pud:%08llx pmd:%08llx\n", pgdv,
> +		 p4dv, pudv, pmdv);
> +}
> +
> +/*
> + * This function is called to print an error when a bad page table entry (e.g.,
> + * corrupted page table entry) is found. For example, we might have a
> + * PFN-mapped pte in a region that doesn't allow it.
> + *
> + * The calling function must still handle the error.
> + *
> + * This function must be called during a proper page table walk, as it will
> + * re-walk the page table to dump information: the caller MUST prevent page
> + * table teardown (by holding mmap, vma or rmap lock) and MUST hold the leaf
> + * page table lock.
> + */

Thanks this is good!

> +static void print_bad_page_map(struct vm_area_struct *vma,
> +		unsigned long addr, unsigned long long entry, struct page *page,
> +		enum pgtable_level level)
> +{
> +	struct address_space *mapping;
> +	pgoff_t index;
> +
> +	if (is_bad_page_map_ratelimited())
> +		return;
>
>  	mapping = vma->vm_file ? vma->vm_file->f_mapping : NULL;
>  	index = linear_page_index(vma, addr);
>
> -	pr_alert("BUG: Bad page map in process %s  pte:%08llx pmd:%08llx\n",
> -		 current->comm,
> -		 (long long)pte_val(pte), (long long)pmd_val(*pmd));
> +	pr_alert("BUG: Bad page map in process %s  %s:%08llx", current->comm,
> +		 pgtable_level_to_str(level), entry);
> +	__print_bad_page_map_pgtable(vma->vm_mm, addr);
>  	if (page)
> -		dump_page(page, "bad pte");
> +		dump_page(page, "bad page map");
>  	pr_alert("addr:%px vm_flags:%08lx anon_vma:%px mapping:%px index:%lx\n",
>  		 (void *)addr, vma->vm_flags, vma->anon_vma, mapping, index);
>  	pr_alert("file:%pD fault:%ps mmap:%ps mmap_prepare: %ps read_folio:%ps\n",
> @@ -549,6 +611,8 @@ static void print_bad_pte(struct vm_area_struct *vma, unsigned long addr,
>  	dump_stack();
>  	add_taint(TAINT_BAD_PAGE, LOCKDEP_NOW_UNRELIABLE);
>  }
> +#define print_bad_pte(vma, addr, pte, page) \
> +	print_bad_page_map(vma, addr, pte_val(pte), page, PGTABLE_LEVEL_PTE)

This is a nice abstraction.

>
>  /*
>   * vm_normal_page -- This function gets the "struct page" associated with a pte.
> --
> 2.50.1
>


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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3 06/11] powerpc/ptdump: rename "struct pgtable_level" to
 "struct ptdump_pglevel"
To: Lorenzo Stoakes ,
 David Hildenbrand 
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
 xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org,
 nvdimm@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
 Andrew Morton ,
 Madhavan Srinivasan ,
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 Juergen Gross , Stefano Stabellini
 ,
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 , Jan Kara ,
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 , Mike Rapoport ,
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 Hugh Dickins , Oscar Salvador ,
 Lance Yang 
References: <20250811112631.759341-1-david@redhat.com>
 <20250811112631.759341-7-david@redhat.com>
 
From: Christophe Leroy 
Content-Language: fr-FR
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Hi Lorenzo,

Le 12/08/2025 à 20:23, Lorenzo Stoakes a écrit :
> On Mon, Aug 11, 2025 at 01:26:26PM +0200, David Hildenbrand wrote:
>> We want to make use of "pgtable_level" for an enum in core-mm. Other
>> architectures seem to call "struct pgtable_level" either:
>> * "struct pg_level" when not exposed in a header (riscv, arm)
>> * "struct ptdump_pg_level" when expose in a header (arm64)
>>
>> So let's follow what arm64 does.
>>
>> Signed-off-by: David Hildenbrand 
> 
> This LGTM, but I'm super confused what these are for, they don't seem to be
> used anywhere? Maybe I'm missing some macro madness, but it seems like dead
> code anyway?

pg_level[] are used several times in arch/powerpc/mm/ptdump/ptdump.c, 
for instance here:

static void note_page_update_state(struct pg_state *st, unsigned long 
addr, int level, u64 val)
{
	u64 flag = level >= 0 ? val & pg_level[level].mask : 0;
	u64 pa = val & PTE_RPN_MASK;

	st->level = level;
	st->current_flags = flag;
	st->start_address = addr;
	st->start_pa = pa;

	while (addr >= st->marker[1].start_address) {
		st->marker++;
		pt_dump_seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
	}
}

> 
> Anyway:
> 
> Reviewed-by: Lorenzo Stoakes 
> 
>> ---
>>   arch/powerpc/mm/ptdump/8xx.c      | 2 +-
>>   arch/powerpc/mm/ptdump/book3s64.c | 2 +-
>>   arch/powerpc/mm/ptdump/ptdump.h   | 4 ++--
>>   arch/powerpc/mm/ptdump/shared.c   | 2 +-
>>   4 files changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/powerpc/mm/ptdump/8xx.c b/arch/powerpc/mm/ptdump/8xx.c
>> index b5c79b11ea3c2..4ca9cf7a90c9e 100644
>> --- a/arch/powerpc/mm/ptdump/8xx.c
>> +++ b/arch/powerpc/mm/ptdump/8xx.c
>> @@ -69,7 +69,7 @@ static const struct flag_info flag_array[] = {
>>   	}
>>   };
>>
>> -struct pgtable_level pg_level[5] = {
>> +struct ptdump_pg_level pg_level[5] = {
>>   	{ /* pgd */
>>   		.flag	= flag_array,
>>   		.num	= ARRAY_SIZE(flag_array),
>> diff --git a/arch/powerpc/mm/ptdump/book3s64.c b/arch/powerpc/mm/ptdump/book3s64.c
>> index 5ad92d9dc5d10..6b2da9241d4c4 100644
>> --- a/arch/powerpc/mm/ptdump/book3s64.c
>> +++ b/arch/powerpc/mm/ptdump/book3s64.c
>> @@ -102,7 +102,7 @@ static const struct flag_info flag_array[] = {
>>   	}
>>   };
>>
>> -struct pgtable_level pg_level[5] = {
>> +struct ptdump_pg_level pg_level[5] = {
>>   	{ /* pgd */
>>   		.flag	= flag_array,
>>   		.num	= ARRAY_SIZE(flag_array),
>> diff --git a/arch/powerpc/mm/ptdump/ptdump.h b/arch/powerpc/mm/ptdump/ptdump.h
>> index 154efae96ae09..4232aa4b57eae 100644
>> --- a/arch/powerpc/mm/ptdump/ptdump.h
>> +++ b/arch/powerpc/mm/ptdump/ptdump.h
>> @@ -11,12 +11,12 @@ struct flag_info {
>>   	int		shift;
>>   };
>>
>> -struct pgtable_level {
>> +struct ptdump_pg_level {
>>   	const struct flag_info *flag;
>>   	size_t num;
>>   	u64 mask;
>>   };
>>
>> -extern struct pgtable_level pg_level[5];
>> +extern struct ptdump_pg_level pg_level[5];
>>
>>   void pt_dump_size(struct seq_file *m, unsigned long delta);
>> diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
>> index 39c30c62b7ea7..58998960eb9a4 100644
>> --- a/arch/powerpc/mm/ptdump/shared.c
>> +++ b/arch/powerpc/mm/ptdump/shared.c
>> @@ -67,7 +67,7 @@ static const struct flag_info flag_array[] = {
>>   	}
>>   };
>>
>> -struct pgtable_level pg_level[5] = {
>> +struct ptdump_pg_level pg_level[5] = {
>>   	{ /* pgd */
>>   		.flag	= flag_array,
>>   		.num	= ARRAY_SIZE(flag_array),
>> --
>> 2.50.1
>>



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Date: Tue, 12 Aug 2025 19:54:58 +0100
From: Lorenzo Stoakes 
To: Christophe Leroy 
Cc: David Hildenbrand , linux-kernel@vger.kernel.org,
        linux-mm@kvack.org, xen-devel@lists.xenproject.org,
        linux-fsdevel@vger.kernel.org, nvdimm@lists.linux.dev,
        linuxppc-dev@lists.ozlabs.org,
        Andrew Morton ,
        Madhavan Srinivasan ,
        Michael Ellerman ,
        Nicholas Piggin , Juergen Gross ,
        Stefano Stabellini ,
        Oleksandr Tyshchenko ,
        Dan Williams ,
        Matthew Wilcox , Jan Kara ,
        Alexander Viro ,
        Christian Brauner ,
        "Liam R. Howlett" ,
        Vlastimil Babka , Mike Rapoport ,
        Suren Baghdasaryan , Michal Hocko ,
        Zi Yan , Baolin Wang ,
        Nico Pache , Ryan Roberts ,
        Dev Jain , Barry Song ,
        Jann Horn , Pedro Falcato ,
        Hugh Dickins , Oscar Salvador ,
        Lance Yang 
Subject: Re: [PATCH v3 06/11] powerpc/ptdump: rename "struct pgtable_level"
 to "struct ptdump_pglevel"
Message-ID: 
References: <20250811112631.759341-1-david@redhat.com>
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On Tue, Aug 12, 2025 at 08:39:36PM +0200, Christophe Leroy wrote:
> Hi Lorenzo,
>
> Le 12/08/2025 à 20:23, Lorenzo Stoakes a écrit :
> > On Mon, Aug 11, 2025 at 01:26:26PM +0200, David Hildenbrand wrote:
> > > We want to make use of "pgtable_level" for an enum in core-mm. Other
> > > architectures seem to call "struct pgtable_level" either:
> > > * "struct pg_level" when not exposed in a header (riscv, arm)
> > > * "struct ptdump_pg_level" when expose in a header (arm64)
> > >
> > > So let's follow what arm64 does.
> > >
> > > Signed-off-by: David Hildenbrand 
> >
> > This LGTM, but I'm super confused what these are for, they don't seem to be
> > used anywhere? Maybe I'm missing some macro madness, but it seems like dead
> > code anyway?
>
> pg_level[] are used several times in arch/powerpc/mm/ptdump/ptdump.c, for
> instance here:
>
> static void note_page_update_state(struct pg_state *st, unsigned long addr,
> int level, u64 val)
> {
> 	u64 flag = level >= 0 ? val & pg_level[level].mask : 0;
> 	u64 pa = val & PTE_RPN_MASK;
>
> 	st->level = level;
> 	st->current_flags = flag;
> 	st->start_address = addr;
> 	st->start_pa = pa;
>
> 	while (addr >= st->marker[1].start_address) {
> 		st->marker++;
> 		pt_dump_seq_printf(st->seq, "---[ %s ]---\n", st->marker->name);
> 	}
> }
>

Ahhhh ok so you're _always_ happening to reference a field in the global value,
thereby not referencing the _type_ anywhere but referencing fields of the
global.

Thanks, that clears that up! :)


From xen-devel-bounces@lists.xenproject.org Tue Aug 12 18:56:03 2025
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Date: Tue, 12 Aug 2025 20:55:59 +0200
From: Anthony PERARD 
To: Andrew Cooper 
Cc: Xen-devel ,
	Javi Merino ,
	Roger Pau =?iso-8859-1?Q?Monn=E9?= ,
	Stefano Stabellini ,
	Anthony PERARD 
Subject: Re: [PATCH] CI: Turn debian/12-x86_64 into a non-root container
Message-ID: 
References: <20250812162950.1903901-1-andrew.cooper3@citrix.com>
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On Tue, Aug 12, 2025 at 05:29:50PM +0100, Andrew Cooper wrote:
> From: Javi Merino 
> 
> Since commit 4611ae6fb8f9 ("CI: save toolstack artifact as cpio.gz"), the
> various automation/scripts/* no longer need to be root to correctly repack the
> initrd for test.
> 
> Signed-off-by: Javi Merino 
> Signed-off-by: Andrew Cooper 
> ---
> CC: Roger Pau Monné 
> CC: Stefano Stabellini 
> CC: Anthony PERARD 
> 
> Xen 4.20 and later uses debian:12-x86_64 and also contains 4611ae6fb8f9 so
> this is safe to change generally.

I gave it a try, just to be sure:
    https://gitlab.com/xen-project/people/anthonyper/xen/-/pipelines/1980442689
and staging-4.20:
    https://gitlab.com/xen-project/people/anthonyper/xen/-/pipelines/1980621317

(all the failed build should be because I was lazy and didn't rebuild
all containers or didn't select a subset of the builds. All test passed
or are skipped, which is what I was looking for)

So:
Reviewed-by: Anthony PERARD 

Thanks,

-- 
Anthony PERARD


From xen-devel-bounces@lists.xenproject.org Tue Aug 12 19:01:04 2025
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From: Jason Andryuk 
To: Juergen Gross , Stefano Stabellini
	, Oleksandr Tyshchenko
	, Chris Wright , "Jeremy
 Fitzhardinge" 
CC: Jason Andryuk , ,
	, 
Subject: [PATCH] xen/events: Fix Global and Domain VIRQ tracking
Date: Tue, 12 Aug 2025 15:00:40 -0400
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VIRQs come in 3 flavors, per-VPU, per-domain, and global.  The existing
tracking of VIRQs is handled by per-cpu variables virq_to_irq.

The issue is that bind_virq_to_irq() sets the per_cpu virq_to_irq at
registration time - typically CPU 0.  Later, the interrupt can migrate,
and info->cpu is updated.  When calling unbind_from_irq(), the per-cpu
virq_to_irq is cleared for a different cpu.  If bind_virq_to_irq() is
called again with CPU 0, the stale irq is returned.

Change the virq_to_irq tracking to use CPU 0 for per-domain and global
VIRQs.  As there can be at most one of each, there is no need for
per-vcpu tracking.  Also, per-domain and global VIRQs need to be
registered on CPU 0 and can later move, so this matches the expectation.

Fixes: e46cdb66c8fc ("xen: event channels")
Cc: stable@vger.kernel.org
Signed-off-by: Jason Andryuk 
---
Fixes is the introduction of the virq_to_irq per-cpu array.

This was found with the out-of-tree argo driver during suspend/resume.
On suspend, the per-domain VIRQ_ARGO is unbound.  On resume, the driver
attempts to bind VIRQ_ARGO.  The stale irq is returned, but the
WARN_ON(info == NULL || info->type != IRQT_VIRQ) in bind_virq_to_irq()
triggers for NULL info.  The bind fails and execution continues with the
driver trying to clean up by unbinding.  This eventually faults over the
NULL info.
---
 drivers/xen/events/events_base.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index 41309d38f78c..a27e4d7f061e 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -159,7 +159,19 @@ static DEFINE_MUTEX(irq_mapping_update_lock);
 
 static LIST_HEAD(xen_irq_list_head);
 
-/* IRQ <-> VIRQ mapping. */
+static bool is_per_vcpu_virq(int virq) {
+	switch (virq) {
+	case VIRQ_TIMER:
+	case VIRQ_DEBUG:
+	case VIRQ_XENOPROF:
+	case VIRQ_XENPMU:
+		return true;
+	default:
+		return false;
+	}
+}
+
+/* IRQ <-> VIRQ mapping.  Global/Domain virqs are tracked in cpu 0.  */
 static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
 
 /* IRQ <-> IPI mapping */
@@ -974,6 +986,9 @@ static void __unbind_from_irq(struct irq_info *info, unsigned int irq)
 
 		switch (info->type) {
 		case IRQT_VIRQ:
+			if (!is_per_vcpu_virq(virq_from_irq(info)))
+				cpu = 0;
+
 			per_cpu(virq_to_irq, cpu)[virq_from_irq(info)] = -1;
 			break;
 		case IRQT_IPI:
-- 
2.50.1



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Date: Tue, 12 Aug 2025 20:06:34 +0100
From: Lorenzo Stoakes 
To: David Hildenbrand 
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
        xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org,
        nvdimm@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
        Andrew Morton ,
        Madhavan Srinivasan ,
        Michael Ellerman ,
        Nicholas Piggin ,
        Christophe Leroy ,
        Juergen Gross ,
        Stefano Stabellini ,
        Oleksandr Tyshchenko ,
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        Alexander Viro ,
        Christian Brauner ,
        "Liam R. Howlett" ,
        Vlastimil Babka , Mike Rapoport ,
        Suren Baghdasaryan , Michal Hocko ,
        Zi Yan , Baolin Wang ,
        Nico Pache , Ryan Roberts ,
        Dev Jain , Barry Song ,
        Jann Horn , Pedro Falcato ,
        Hugh Dickins , Oscar Salvador ,
        Lance Yang 
Subject: Re: [PATCH v3 09/11] mm/memory: factor out common code from
 vm_normal_page_*()
Message-ID: <59c0c6b2-7112-4afd-8ea7-9e8bfaf86394@lucifer.local>
References: <20250811112631.759341-1-david@redhat.com>
 <20250811112631.759341-10-david@redhat.com>
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On Mon, Aug 11, 2025 at 01:26:29PM +0200, David Hildenbrand wrote:
> Let's reduce the code duplication and factor out the non-pte/pmd related
> magic into __vm_normal_page().
>
> To keep it simpler, check the pfn against both zero folios, which
> shouldn't really make a difference.
>
> It's a good question if we can even hit the !CONFIG_ARCH_HAS_PTE_SPECIAL
> scenario in the PMD case in practice: but doesn't really matter, as
> it's now all unified in vm_normal_page_pfn().
>
> Add kerneldoc for all involved functions.
>
> Note that, as a side product, we now:
> * Support the find_special_page special thingy also for PMD
> * Don't check for is_huge_zero_pfn() anymore if we have
>   CONFIG_ARCH_HAS_PTE_SPECIAL and the PMD is not special. The
>   VM_WARN_ON_ONCE would catch any abuse
>
> No functional change intended.
>
> Reviewed-by: Oscar Salvador 
> Signed-off-by: David Hildenbrand 

Fantastic cleanup, thanks for refactoring with levels, this looks great!

Reviewed-by: Lorenzo Stoakes 

> ---
>  mm/memory.c | 186 ++++++++++++++++++++++++++++++----------------------
>  1 file changed, 109 insertions(+), 77 deletions(-)
>
> diff --git a/mm/memory.c b/mm/memory.c
> index dc0107354d37b..78af3f243cee7 100644
> --- a/mm/memory.c
> +++ b/mm/memory.c
> @@ -614,8 +614,14 @@ static void print_bad_page_map(struct vm_area_struct *vma,
>  #define print_bad_pte(vma, addr, pte, page) \
>  	print_bad_page_map(vma, addr, pte_val(pte), page, PGTABLE_LEVEL_PTE)
>
> -/*
> - * vm_normal_page -- This function gets the "struct page" associated with a pte.
> +/**
> + * __vm_normal_page() - Get the "struct page" associated with a page table entry.
> + * @vma: The VMA mapping the page table entry.
> + * @addr: The address where the page table entry is mapped.
> + * @pfn: The PFN stored in the page table entry.
> + * @special: Whether the page table entry is marked "special".
> + * @level: The page table level for error reporting purposes only.
> + * @entry: The page table entry value for error reporting purposes only.
>   *
>   * "Special" mappings do not wish to be associated with a "struct page" (either
>   * it doesn't exist, or it exists but they don't want to touch it). In this
> @@ -628,10 +634,10 @@ static void print_bad_page_map(struct vm_area_struct *vma,
>   * Selected page table walkers (such as GUP) can still identify mappings of the
>   * shared zero folios and work with the underlying "struct page".
>   *
> - * There are 2 broad cases. Firstly, an architecture may define a pte_special()
> - * pte bit, in which case this function is trivial. Secondly, an architecture
> - * may not have a spare pte bit, which requires a more complicated scheme,
> - * described below.
> + * There are 2 broad cases. Firstly, an architecture may define a "special"
> + * page table entry bit, such as pte_special(), in which case this function is
> + * trivial. Secondly, an architecture may not have a spare page table
> + * entry bit, which requires a more complicated scheme, described below.

OK cool, nice to have this here in one place!

>   *
>   * A raw VM_PFNMAP mapping (ie. one that is not COWed) is always considered a
>   * special mapping (even if there are underlying and valid "struct pages").
> @@ -664,63 +670,94 @@ static void print_bad_page_map(struct vm_area_struct *vma,
>   * don't have to follow the strict linearity rule of PFNMAP mappings in
>   * order to support COWable mappings.
>   *
> + * Return: Returns the "struct page" if this is a "normal" mapping. Returns
> + *	   NULL if this is a "special" mapping.
>   */
> -struct page *vm_normal_page(struct vm_area_struct *vma, unsigned long addr,
> -			    pte_t pte)
> +static inline struct page *__vm_normal_page(struct vm_area_struct *vma,
> +		unsigned long addr, unsigned long pfn, bool special,
> +		unsigned long long entry, enum pgtable_level level)
>  {
> -	unsigned long pfn = pte_pfn(pte);
> -
>  	if (IS_ENABLED(CONFIG_ARCH_HAS_PTE_SPECIAL)) {
> -		if (likely(!pte_special(pte)))
> -			goto check_pfn;
> -		if (vma->vm_ops && vma->vm_ops->find_special_page)
> -			return vma->vm_ops->find_special_page(vma, addr);
> -		if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
> -			return NULL;
> -		if (is_zero_pfn(pfn))
> -			return NULL;
> -
> -		print_bad_pte(vma, addr, pte, NULL);
> -		return NULL;
> -	}
> -
> -	/* !CONFIG_ARCH_HAS_PTE_SPECIAL case follows: */
> -
> -	if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
> -		if (vma->vm_flags & VM_MIXEDMAP) {
> -			if (!pfn_valid(pfn))
> +		if (unlikely(special)) {
> +			if (vma->vm_ops && vma->vm_ops->find_special_page)
> +				return vma->vm_ops->find_special_page(vma, addr);
> +			if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
>  				return NULL;
> -			if (is_zero_pfn(pfn))
> -				return NULL;
> -			goto out;
> -		} else {
> -			unsigned long off;
> -			off = (addr - vma->vm_start) >> PAGE_SHIFT;
> -			if (pfn == vma->vm_pgoff + off)
> -				return NULL;
> -			if (!is_cow_mapping(vma->vm_flags))
> +			if (is_zero_pfn(pfn) || is_huge_zero_pfn(pfn))

Yeah this works fine.

>  				return NULL;
> +
> +			print_bad_page_map(vma, addr, entry, NULL, level);

OK nice this is where the the print_bad_page_map() with level comes in handy.

> +			return NULL;
>  		}
> -	}
> +		/*
> +		 * With CONFIG_ARCH_HAS_PTE_SPECIAL, any special page table
> +		 * mappings (incl. shared zero folios) are marked accordingly.
> +		 */
> +	} else {
> +		if (unlikely(vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))) {
> +			if (vma->vm_flags & VM_MIXEDMAP) {
> +				/* If it has a "struct page", it's "normal". */
> +				if (!pfn_valid(pfn))
> +					return NULL;
> +			} else {
> +				unsigned long off = (addr - vma->vm_start) >> PAGE_SHIFT;
>
> -	if (is_zero_pfn(pfn))
> -		return NULL;
> +				/* Only CoW'ed anon folios are "normal". */
> +				if (pfn == vma->vm_pgoff + off)
> +					return NULL;
> +				if (!is_cow_mapping(vma->vm_flags))
> +					return NULL;
> +			}
> +		}
> +
> +		if (is_zero_pfn(pfn) || is_huge_zero_pfn(pfn))

Yeah this is fine too! This is all working out rather neatly! :)

> +			return NULL;
> +	}
>
> -check_pfn:
>  	if (unlikely(pfn > highest_memmap_pfn)) {
> -		print_bad_pte(vma, addr, pte, NULL);
> +		/* Corrupted page table entry. */
> +		print_bad_page_map(vma, addr, entry, NULL, level);
>  		return NULL;
>  	}
> -
>  	/*
>  	 * NOTE! We still have PageReserved() pages in the page tables.
> -	 * eg. VDSO mappings can cause them to exist.
> +	 * For example, VDSO mappings can cause them to exist.
>  	 */
> -out:
> -	VM_WARN_ON_ONCE(is_zero_pfn(pfn));
> +	VM_WARN_ON_ONCE(is_zero_pfn(pfn) || is_huge_zero_pfn(pfn));

And ACK on this as well.

>  	return pfn_to_page(pfn);
>  }
>
> +/**
> + * vm_normal_page() - Get the "struct page" associated with a PTE
> + * @vma: The VMA mapping the @pte.
> + * @addr: The address where the @pte is mapped.
> + * @pte: The PTE.
> + *
> + * Get the "struct page" associated with a PTE. See __vm_normal_page()
> + * for details on "normal" and "special" mappings.

Lovely.

> + *
> + * Return: Returns the "struct page" if this is a "normal" mapping. Returns
> + *	   NULL if this is a "special" mapping.
> + */
> +struct page *vm_normal_page(struct vm_area_struct *vma, unsigned long addr,
> +			    pte_t pte)
> +{
> +	return __vm_normal_page(vma, addr, pte_pfn(pte), pte_special(pte),
> +				pte_val(pte), PGTABLE_LEVEL_PTE);

Nice and neat!

> +}
> +
> +/**
> + * vm_normal_folio() - Get the "struct folio" associated with a PTE
> + * @vma: The VMA mapping the @pte.
> + * @addr: The address where the @pte is mapped.
> + * @pte: The PTE.
> + *
> + * Get the "struct folio" associated with a PTE. See __vm_normal_page()
> + * for details on "normal" and "special" mappings.
> + *
> + * Return: Returns the "struct folio" if this is a "normal" mapping. Returns
> + *	   NULL if this is a "special" mapping.
> + */

Great, thanks for adding this! I especially like '*special*' :P

>  struct folio *vm_normal_folio(struct vm_area_struct *vma, unsigned long addr,
>  			    pte_t pte)
>  {
> @@ -732,42 +769,37 @@ struct folio *vm_normal_folio(struct vm_area_struct *vma, unsigned long addr,
>  }
>
>  #ifdef CONFIG_PGTABLE_HAS_HUGE_LEAVES
> +/**
> + * vm_normal_page_pmd() - Get the "struct page" associated with a PMD
> + * @vma: The VMA mapping the @pmd.
> + * @addr: The address where the @pmd is mapped.
> + * @pmd: The PMD.
> + *
> + * Get the "struct page" associated with a PTE. See __vm_normal_page()
> + * for details on "normal" and "special" mappings.
> + *
> + * Return: Returns the "struct page" if this is a "normal" mapping. Returns
> + *	   NULL if this is a "special" mapping.
> + */
>  struct page *vm_normal_page_pmd(struct vm_area_struct *vma, unsigned long addr,
>  				pmd_t pmd)
>  {
> -	unsigned long pfn = pmd_pfn(pmd);
> -
> -	if (unlikely(pmd_special(pmd)))
> -		return NULL;
> -
> -	if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
> -		if (vma->vm_flags & VM_MIXEDMAP) {
> -			if (!pfn_valid(pfn))
> -				return NULL;
> -			goto out;
> -		} else {
> -			unsigned long off;
> -			off = (addr - vma->vm_start) >> PAGE_SHIFT;
> -			if (pfn == vma->vm_pgoff + off)
> -				return NULL;
> -			if (!is_cow_mapping(vma->vm_flags))
> -				return NULL;
> -		}
> -	}
> -
> -	if (is_huge_zero_pfn(pfn))
> -		return NULL;
> -	if (unlikely(pfn > highest_memmap_pfn))
> -		return NULL;
> -
> -	/*
> -	 * NOTE! We still have PageReserved() pages in the page tables.
> -	 * eg. VDSO mappings can cause them to exist.
> -	 */
> -out:
> -	return pfn_to_page(pfn);
> +	return __vm_normal_page(vma, addr, pmd_pfn(pmd), pmd_special(pmd),
> +				pmd_val(pmd), PGTABLE_LEVEL_PMD);

So much red... so much delight! :) this is great!

>  }
>
> +/**
> + * vm_normal_folio_pmd() - Get the "struct folio" associated with a PMD
> + * @vma: The VMA mapping the @pmd.
> + * @addr: The address where the @pmd is mapped.
> + * @pmd: The PMD.
> + *
> + * Get the "struct folio" associated with a PTE. See __vm_normal_page()
> + * for details on "normal" and "special" mappings.
> + *
> + * Return: Returns the "struct folio" if this is a "normal" mapping. Returns
> + *	   NULL if this is a "special" mapping.
> + */

This is great also!

>  struct folio *vm_normal_folio_pmd(struct vm_area_struct *vma,
>  				  unsigned long addr, pmd_t pmd)
>  {
> --
> 2.50.1
>


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Message-ID: <5407877d-4c7c-494f-8fc1-d44eea4762b9@citrix.com>
Date: Tue, 12 Aug 2025 20:10:09 +0100
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH] xen/events: Fix Global and Domain VIRQ tracking
To: Jason Andryuk , Juergen Gross ,
 Stefano Stabellini ,
 Oleksandr Tyshchenko ,
 Chris Wright ,
 Jeremy Fitzhardinge ,
 Christopher Clark ,
 Daniel Smith 
Cc: stable@vger.kernel.org, xen-devel@lists.xenproject.org,
 linux-kernel@vger.kernel.org
References: <20250812190041.23276-1-jason.andryuk@amd.com>
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From: Andrew Cooper 
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In-Reply-To: <20250812190041.23276-1-jason.andryuk@amd.com>
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On 12/08/2025 8:00 pm, Jason Andryuk wrote:
> VIRQs come in 3 flavors, per-VPU, per-domain, and global.  The existing
> tracking of VIRQs is handled by per-cpu variables virq_to_irq.
>
> The issue is that bind_virq_to_irq() sets the per_cpu virq_to_irq at
> registration time - typically CPU 0.  Later, the interrupt can migrate,
> and info->cpu is updated.  When calling unbind_from_irq(), the per-cpu
> virq_to_irq is cleared for a different cpu.  If bind_virq_to_irq() is
> called again with CPU 0, the stale irq is returned.
>
> Change the virq_to_irq tracking to use CPU 0 for per-domain and global
> VIRQs.  As there can be at most one of each, there is no need for
> per-vcpu tracking.  Also, per-domain and global VIRQs need to be
> registered on CPU 0 and can later move, so this matches the expectation.
>
> Fixes: e46cdb66c8fc ("xen: event channels")
> Cc: stable@vger.kernel.org
> Signed-off-by: Jason Andryuk 
> ---
> Fixes is the introduction of the virq_to_irq per-cpu array.
>
> This was found with the out-of-tree argo driver during suspend/resume.
> On suspend, the per-domain VIRQ_ARGO is unbound.  On resume, the driver
> attempts to bind VIRQ_ARGO.  The stale irq is returned, but the
> WARN_ON(info == NULL || info->type != IRQT_VIRQ) in bind_virq_to_irq()
> triggers for NULL info.  The bind fails and execution continues with the
> driver trying to clean up by unbinding.  This eventually faults over the
> NULL info.

I don't think the Fixes: tag is entirely appropriate.

per-domain VIRQs were created (unexpectedly) by the merge of ARGO into
Xen.  It was during some unrelated cleanup that this was noticed and
bugfixed into working.  i.e. the ARGO VIRQ is the singular weird one here.

In Xen we did accept that per-domain VIRQs now exist; they had for
several releases before we realised.

~Andrew

> ---
>  drivers/xen/events/events_base.c | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
> index 41309d38f78c..a27e4d7f061e 100644
> --- a/drivers/xen/events/events_base.c
> +++ b/drivers/xen/events/events_base.c
> @@ -159,7 +159,19 @@ static DEFINE_MUTEX(irq_mapping_update_lock);
>  
>  static LIST_HEAD(xen_irq_list_head);
>  
> -/* IRQ <-> VIRQ mapping. */
> +static bool is_per_vcpu_virq(int virq) {
> +	switch (virq) {
> +	case VIRQ_TIMER:
> +	case VIRQ_DEBUG:
> +	case VIRQ_XENOPROF:
> +	case VIRQ_XENPMU:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +/* IRQ <-> VIRQ mapping.  Global/Domain virqs are tracked in cpu 0.  */
>  static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
>  
>  /* IRQ <-> IPI mapping */
> @@ -974,6 +986,9 @@ static void __unbind_from_irq(struct irq_info *info, unsigned int irq)
>  
>  		switch (info->type) {
>  		case IRQT_VIRQ:
> +			if (!is_per_vcpu_virq(virq_from_irq(info)))
> +				cpu = 0;
> +
>  			per_cpu(virq_to_irq, cpu)[virq_from_irq(info)] = -1;
>  			break;
>  		case IRQT_IPI:



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Subject: Re: [PATCH] CI: Turn debian/12-x86_64 into a non-root container
To: Anthony PERARD 
Cc: Xen-devel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Anthony PERARD 
References: <20250812162950.1903901-1-andrew.cooper3@citrix.com>
 
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From: Andrew Cooper 
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On 12/08/2025 7:55 pm, Anthony PERARD wrote:
> On Tue, Aug 12, 2025 at 05:29:50PM +0100, Andrew Cooper wrote:
>> From: Javi Merino 
>>
>> Since commit 4611ae6fb8f9 ("CI: save toolstack artifact as cpio.gz"), the
>> various automation/scripts/* no longer need to be root to correctly repack the
>> initrd for test.
>>
>> Signed-off-by: Javi Merino 
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Roger Pau Monné 
>> CC: Stefano Stabellini 
>> CC: Anthony PERARD 
>>
>> Xen 4.20 and later uses debian:12-x86_64 and also contains 4611ae6fb8f9 so
>> this is safe to change generally.
> I gave it a try, just to be sure:
>     https://gitlab.com/xen-project/people/anthonyper/xen/-/pipelines/1980442689
> and staging-4.20:
>     https://gitlab.com/xen-project/people/anthonyper/xen/-/pipelines/1980621317
>
> (all the failed build should be because I was lazy and didn't rebuild
> all containers or didn't select a subset of the builds. All test passed
> or are skipped, which is what I was looking for)
>
> So:
> Reviewed-by: Anthony PERARD 

Thanks.  I'll commit and deploy this now.

~Andrew


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MISRA C Rule 2.1 states: "A project shall not contain unreachable code."

Function `PrintErrMesg(const CHAR16*, EFI_STATUS)` isn't intended to return
control to its caller. At the end, it calls `blexit()`, which, in turn,
invokes the `__builtin_unreachable()` function, making subsequent return
statements in `read_file()` unreachable:

    PrintErrMesg(name, ret);
    /* not reached */
    return false;

This also causes unreachability of the code meant to handle `read_file()`
errors, as seen in these examples:

In this block:
    if ( read_file(dir_handle, file_name, &cfg, NULL) )
        break;
    *tail =3D 0;
    }
    if ( !tail )
        blexit(L"No configuration file found.");

And here:
    else if ( !read_file(dir_handle, cfg_file_name, &cfg, NULL) )
        blexit(L"Configuration file not found.");

And here:
    if ( !read_file(dir_handle, s2w(&name), &cfg, NULL) )
    {
        PrintStr(L"Chained configuration file '");
        PrintStr(name.w);
        efi_bs->FreePool(name.w);
        blexit(L"'not found.");
    }

The issue arises because when an error occurs inside `read_file()`, it call=
s
`PrintErrMesg()` and does not return to the caller.

To address this the following changes are applied:
1. Remove `PrintErrMesg(name, ret);` from the `read_file()` function.
2. Replaced it with `PrintErr(name);`, which prints the file name and retur=
ns
   control to the caller.
3. Change the `read_file()` return type from `bool` to `EFI_STATUS`, allowi=
ng
   file operation result codes to be returned to the caller.
4. Properly handle error codes returned from the `read_file()` function in =
the
   relevant areas of the code.
5. Replace `blexit()` calls with informative error codes using `PrintErrMes=
g()`
   where appropriate.

Signed-off-by: Dmytro Prokopchuk 
---
Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1980590118
---
 xen/common/efi/boot.c | 57 ++++++++++++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 17 deletions(-)

diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
index 50ff1d1bd2..ddbafb2f9c 100644
--- a/xen/common/efi/boot.c
+++ b/xen/common/efi/boot.c
@@ -132,7 +132,7 @@ struct file {
     };
 };
=20
-static bool read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
+static EFI_STATUS read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
                       struct file *file, const char *options);
 static bool read_section(const EFI_LOADED_IMAGE *image, const CHAR16 *name=
,
                          struct file *file, const char *options);
@@ -782,7 +782,7 @@ static void __init handle_file_info(const CHAR16 *name,
     efi_arch_handle_module(file, name, options);
 }
=20
-static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
+static EFI_STATUS __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *nam=
e,
                              struct file *file, const char *options)
 {
     EFI_FILE_HANDLE FileHandle =3D NULL;
@@ -791,7 +791,7 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle=
, CHAR16 *name,
     const CHAR16 *what =3D NULL;
=20
     if ( !name )
-        PrintErrMesg(L"No filename", EFI_OUT_OF_RESOURCES);
+        return EFI_INVALID_PARAMETER;
=20
     what =3D L"Open";
     if ( dir_handle )
@@ -842,7 +842,7 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle=
, CHAR16 *name,
=20
     efi_arch_flush_dcache_area(file->ptr, file->size);
=20
-    return true;
+    return ret;
=20
  fail:
     if ( FileHandle )
@@ -850,10 +850,9 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handl=
e, CHAR16 *name,
=20
     PrintErr(what);
     PrintErr(L" failed for ");
-    PrintErrMesg(name, ret);
+    PrintErr(name);
=20
-    /* not reached */
-    return false;
+    return ret;
 }
=20
 static bool __init read_section(const EFI_LOADED_IMAGE *image,
@@ -1433,18 +1432,20 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE Im=
ageHandle,
             while ( (tail =3D point_tail(file_name)) !=3D NULL )
             {
                 wstrcpy(tail, L".cfg");
-                if ( read_file(dir_handle, file_name, &cfg, NULL) )
+                if ( (status =3D read_file(dir_handle, file_name,
+                                         &cfg, NULL)) =3D=3D EFI_SUCCESS )
                     break;
                 *tail =3D 0;
             }
             if ( !tail )
-                blexit(L"No configuration file found.");
+                PrintErrMesg(L"Configuration file failure.", status);
             PrintStr(L"Using configuration file '");
             PrintStr(file_name);
             PrintStr(L"'\r\n");
         }
-        else if ( !read_file(dir_handle, cfg_file_name, &cfg, NULL) )
-            blexit(L"Configuration file not found.");
+        else if ( (status =3D read_file(dir_handle, cfg_file_name,
+                                      &cfg, NULL)) !=3D EFI_SUCCESS )
+            PrintErrMesg(L"Configuration file failure.", status);
         pre_parse(&cfg);
=20
         if ( section.w )
@@ -1465,12 +1466,13 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE Im=
ageHandle,
                 efi_bs->FreePages(cfg.addr, PFN_UP(cfg.size));
                 cfg.need_to_free =3D false;
             }
-            if ( !read_file(dir_handle, s2w(&name), &cfg, NULL) )
+            if ( (status =3D read_file(dir_handle, s2w(&name),
+                                     &cfg, NULL)) !=3D EFI_SUCCESS )
             {
-                PrintStr(L"Chained configuration file '");
+                PrintStr(L"Configuration file '");
                 PrintStr(name.w);
                 efi_bs->FreePool(name.w);
-                blexit(L"'not found.");
+                PrintErrMesg(L"'failure.", status);
             }
             pre_parse(&cfg);
             efi_bs->FreePool(name.w);
@@ -1483,7 +1485,14 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE Ima=
geHandle,
         if ( !read_section(loaded_image, L"kernel", &kernel, option_str) &=
&
              name.s )
         {
-            read_file(dir_handle, s2w(&name), &kernel, option_str);
+            status =3D read_file(dir_handle, s2w(&name), &kernel, option_s=
tr);
+            if ( status !=3D EFI_SUCCESS )
+            {
+                PrintStr(L"Configuration file '");
+                PrintStr(name.w);
+                efi_bs->FreePool(name.w);
+                PrintErrMesg(L"'failure.", status);
+            }
             efi_bs->FreePool(name.w);
         }
         else
@@ -1497,7 +1506,14 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE Ima=
geHandle,
             name.s =3D get_value(&cfg, section.s, "ramdisk");
             if ( name.s )
             {
-                read_file(dir_handle, s2w(&name), &ramdisk, NULL);
+                status =3D read_file(dir_handle, s2w(&name), &ramdisk, NUL=
L);
+                if ( status !=3D EFI_SUCCESS )
+                {
+                    PrintStr(L"Configuration file '");
+                    PrintStr(name.w);
+                    efi_bs->FreePool(name.w);
+                    PrintErrMesg(L"'failure.", status);
+                }
                 efi_bs->FreePool(name.w);
             }
         }
@@ -1507,7 +1523,14 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE Ima=
geHandle,
             name.s =3D get_value(&cfg, section.s, "xsm");
             if ( name.s )
             {
-                read_file(dir_handle, s2w(&name), &xsm, NULL);
+                status =3D read_file(dir_handle, s2w(&name), &xsm, NULL);
+                if ( status !=3D EFI_SUCCESS )
+                {
+                    PrintStr(L"Configuration file '");
+                    PrintStr(name.w);
+                    efi_bs->FreePool(name.w);
+                    PrintErrMesg(L"'failure.", status);
+                }
                 efi_bs->FreePool(name.w);
             }
         }
--=20
2.43.0


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Subject: Re: [PATCH] xen/events: Fix Global and Domain VIRQ tracking
To: Andrew Cooper , Juergen Gross
	, Stefano Stabellini , Oleksandr
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On 2025-08-12 15:10, Andrew Cooper wrote:
> On 12/08/2025 8:00 pm, Jason Andryuk wrote:
>> VIRQs come in 3 flavors, per-VPU, per-domain, and global.  The existing
>> tracking of VIRQs is handled by per-cpu variables virq_to_irq.
>>
>> The issue is that bind_virq_to_irq() sets the per_cpu virq_to_irq at
>> registration time - typically CPU 0.  Later, the interrupt can migrate,
>> and info->cpu is updated.  When calling unbind_from_irq(), the per-cpu
>> virq_to_irq is cleared for a different cpu.  If bind_virq_to_irq() is
>> called again with CPU 0, the stale irq is returned.
>>
>> Change the virq_to_irq tracking to use CPU 0 for per-domain and global
>> VIRQs.  As there can be at most one of each, there is no need for
>> per-vcpu tracking.  Also, per-domain and global VIRQs need to be
>> registered on CPU 0 and can later move, so this matches the expectation.
>>
>> Fixes: e46cdb66c8fc ("xen: event channels")
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Jason Andryuk 
>> ---
>> Fixes is the introduction of the virq_to_irq per-cpu array.
>>
>> This was found with the out-of-tree argo driver during suspend/resume.
>> On suspend, the per-domain VIRQ_ARGO is unbound.  On resume, the driver
>> attempts to bind VIRQ_ARGO.  The stale irq is returned, but the
>> WARN_ON(info == NULL || info->type != IRQT_VIRQ) in bind_virq_to_irq()
>> triggers for NULL info.  The bind fails and execution continues with the
>> driver trying to clean up by unbinding.  This eventually faults over the
>> NULL info.
> 
> I don't think the Fixes: tag is entirely appropriate.
> 
> per-domain VIRQs were created (unexpectedly) by the merge of ARGO into
> Xen.  It was during some unrelated cleanup that this was noticed and
> bugfixed into working.  i.e. the ARGO VIRQ is the singular weird one here.
> 
> In Xen we did accept that per-domain VIRQs now exist; they had for
> several releases before we realised.

AFAICT, global VIRQs have the same issue - I think they just aren't 
unbound and rebound.  I just happened to trigger this with the 
per-domain ARGO VIRQ.

I double checked, and the cpu is updated like so:

set_affinity_irq()
   rebind_irq_to_cpu()
     bind_evtchn_to_cpu()
       cpu_evtchn[chn] = cpu;

unbind_from_irq()
     case IRQT_VIRQ:
         per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
                 [index_from_irq(irq)] = -1;

cpu_from_evtchn()
     return cpu_evtchn[evtchn];

So global VIRQs were mis-tracked even in the Fixes commit.

Regards,
Jason

>> ---
>>   drivers/xen/events/events_base.c | 17 ++++++++++++++++-
>>   1 file changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
>> index 41309d38f78c..a27e4d7f061e 100644
>> --- a/drivers/xen/events/events_base.c
>> +++ b/drivers/xen/events/events_base.c
>> @@ -159,7 +159,19 @@ static DEFINE_MUTEX(irq_mapping_update_lock);
>>   
>>   static LIST_HEAD(xen_irq_list_head);
>>   
>> -/* IRQ <-> VIRQ mapping. */
>> +static bool is_per_vcpu_virq(int virq) {
>> +	switch (virq) {
>> +	case VIRQ_TIMER:
>> +	case VIRQ_DEBUG:
>> +	case VIRQ_XENOPROF:
>> +	case VIRQ_XENPMU:
>> +		return true;
>> +	default:
>> +		return false;
>> +	}
>> +}
>> +
>> +/* IRQ <-> VIRQ mapping.  Global/Domain virqs are tracked in cpu 0.  */
>>   static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
>>   
>>   /* IRQ <-> IPI mapping */
>> @@ -974,6 +986,9 @@ static void __unbind_from_irq(struct irq_info *info, unsigned int irq)
>>   
>>   		switch (info->type) {
>>   		case IRQT_VIRQ:
>> +			if (!is_per_vcpu_virq(virq_from_irq(info)))
>> +				cpu = 0;
>> +
>>   			per_cpu(virq_to_irq, cpu)[virq_from_irq(info)] = -1;
>>   			break;
>>   		case IRQT_IPI:
> 



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        Nico Pache , Ryan Roberts ,
        Dev Jain , Barry Song ,
        Jann Horn , Pedro Falcato ,
        Hugh Dickins , Oscar Salvador ,
        Lance Yang ,
        Wei Yang 
Subject: Re: [PATCH v3 10/11] mm: introduce and use vm_normal_page_pud()
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On Mon, Aug 11, 2025 at 01:26:30PM +0200, David Hildenbrand wrote:
> Let's introduce vm_normal_page_pud(), which ends up being fairly simple
> because of our new common helpers and there not being a PUD-sized zero
> folio.
>
> Use vm_normal_page_pud() in folio_walk_start() to resolve a TODO,
> structuring the code like the other (pmd/pte) cases. Defer
> introducing vm_normal_folio_pud() until really used.
>
> Note that we can so far get PUDs with hugetlb, daxfs and PFNMAP entries.

I guess hugetlb will be handled in a separate way, daxfs will be... special, I
think? and PFNMAP definitely is.

>
> Reviewed-by: Wei Yang 
> Reviewed-by: Oscar Salvador 
> Signed-off-by: David Hildenbrand 

Anyway this is nice, thanks! Nice to resolve the todo :)

Reviewed-by: Lorenzo Stoakes 

> ---
>  include/linux/mm.h |  2 ++
>  mm/memory.c        | 19 +++++++++++++++++++
>  mm/pagewalk.c      | 20 ++++++++++----------
>  3 files changed, 31 insertions(+), 10 deletions(-)
>
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index b626d1bacef52..8ca7d2fa71343 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -2360,6 +2360,8 @@ struct folio *vm_normal_folio_pmd(struct vm_area_struct *vma,
>  				  unsigned long addr, pmd_t pmd);
>  struct page *vm_normal_page_pmd(struct vm_area_struct *vma, unsigned long addr,
>  				pmd_t pmd);
> +struct page *vm_normal_page_pud(struct vm_area_struct *vma, unsigned long addr,
> +		pud_t pud);
>
>  void zap_vma_ptes(struct vm_area_struct *vma, unsigned long address,
>  		  unsigned long size);
> diff --git a/mm/memory.c b/mm/memory.c
> index 78af3f243cee7..6f806bf3cc994 100644
> --- a/mm/memory.c
> +++ b/mm/memory.c
> @@ -809,6 +809,25 @@ struct folio *vm_normal_folio_pmd(struct vm_area_struct *vma,
>  		return page_folio(page);
>  	return NULL;
>  }
> +
> +/**
> + * vm_normal_page_pud() - Get the "struct page" associated with a PUD
> + * @vma: The VMA mapping the @pud.
> + * @addr: The address where the @pud is mapped.
> + * @pud: The PUD.
> + *
> + * Get the "struct page" associated with a PUD. See __vm_normal_page()
> + * for details on "normal" and "special" mappings.
> + *
> + * Return: Returns the "struct page" if this is a "normal" mapping. Returns
> + *	   NULL if this is a "special" mapping.
> + */
> +struct page *vm_normal_page_pud(struct vm_area_struct *vma,
> +		unsigned long addr, pud_t pud)
> +{
> +	return __vm_normal_page(vma, addr, pud_pfn(pud), pud_special(pud),
> +				pud_val(pud), PGTABLE_LEVEL_PUD);
> +}
>  #endif
>
>  /**
> diff --git a/mm/pagewalk.c b/mm/pagewalk.c
> index 648038247a8d2..c6753d370ff4e 100644
> --- a/mm/pagewalk.c
> +++ b/mm/pagewalk.c
> @@ -902,23 +902,23 @@ struct folio *folio_walk_start(struct folio_walk *fw,
>  		fw->pudp = pudp;
>  		fw->pud = pud;
>
> -		/*
> -		 * TODO: FW_MIGRATION support for PUD migration entries
> -		 * once there are relevant users.
> -		 */
> -		if (!pud_present(pud) || pud_special(pud)) {
> +		if (pud_none(pud)) {
>  			spin_unlock(ptl);
>  			goto not_found;
> -		} else if (!pud_leaf(pud)) {
> +		} else if (pud_present(pud) && !pud_leaf(pud)) {
>  			spin_unlock(ptl);
>  			goto pmd_table;
> +		} else if (pud_present(pud)) {
> +			page = vm_normal_page_pud(vma, addr, pud);
> +			if (page)
> +				goto found;
>  		}
>  		/*
> -		 * TODO: vm_normal_page_pud() will be handy once we want to
> -		 * support PUD mappings in VM_PFNMAP|VM_MIXEDMAP VMAs.
> +		 * TODO: FW_MIGRATION support for PUD migration entries
> +		 * once there are relevant users.
>  		 */
> -		page = pud_page(pud);
> -		goto found;
> +		spin_unlock(ptl);
> +		goto not_found;
>  	}
>
>  pmd_table:
> --
> 2.50.1
>


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Date: Tue, 12 Aug 2025 20:43:20 +0100
From: Lorenzo Stoakes 
To: David Hildenbrand 
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
        xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org,
        nvdimm@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
        Andrew Morton ,
        Madhavan Srinivasan ,
        Michael Ellerman ,
        Nicholas Piggin ,
        Christophe Leroy ,
        Juergen Gross ,
        Stefano Stabellini ,
        Oleksandr Tyshchenko ,
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        "Liam R. Howlett" ,
        Vlastimil Babka , Mike Rapoport ,
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        Nico Pache , Ryan Roberts ,
        Dev Jain , Barry Song ,
        Jann Horn , Pedro Falcato ,
        Hugh Dickins , Oscar Salvador ,
        Lance Yang ,
        David Vrabel ,
        Wei Yang 
Subject: Re: [PATCH v3 11/11] mm: rename vm_ops->find_special_page() to
 vm_ops->find_normal_page()
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References: <20250811112631.759341-1-david@redhat.com>
 <20250811112631.759341-12-david@redhat.com>
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On Mon, Aug 11, 2025 at 01:26:31PM +0200, David Hildenbrand wrote:
> ... and hide it behind a kconfig option. There is really no need for
> any !xen code to perform this check.
>
> The naming is a bit off: we want to find the "normal" page when a PTE
> was marked "special". So it's really not "finding a special" page.
>
> Improve the documentation, and add a comment in the code where XEN ends
> up performing the pte_mkspecial() through a hypercall. More details can
> be found in commit 923b2919e2c3 ("xen/gntdev: mark userspace PTEs as
> special on x86 PV guests").
>
> Cc: David Vrabel 
> Reviewed-by: Oscar Salvador 
> Reviewed-by: Lorenzo Stoakes 
> Reviewed-by: Wei Yang 
> Signed-off-by: David Hildenbrand 

Oh I already reviewed it. But anyway, may as well say - THANKS fof this
it's great again :)

> ---
>  drivers/xen/Kconfig              |  1 +
>  drivers/xen/gntdev.c             |  5 +++--
>  include/linux/mm.h               | 18 +++++++++++++-----
>  mm/Kconfig                       |  2 ++
>  mm/memory.c                      | 12 ++++++++++--
>  tools/testing/vma/vma_internal.h | 18 +++++++++++++-----
>  6 files changed, 42 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
> index 24f485827e039..f9a35ed266ecf 100644
> --- a/drivers/xen/Kconfig
> +++ b/drivers/xen/Kconfig
> @@ -138,6 +138,7 @@ config XEN_GNTDEV
>  	depends on XEN
>  	default m
>  	select MMU_NOTIFIER
> +	select FIND_NORMAL_PAGE
>  	help
>  	  Allows userspace processes to use grants.
>
> diff --git a/drivers/xen/gntdev.c b/drivers/xen/gntdev.c
> index 1f21607656182..26f13b37c78e6 100644
> --- a/drivers/xen/gntdev.c
> +++ b/drivers/xen/gntdev.c
> @@ -321,6 +321,7 @@ static int find_grant_ptes(pte_t *pte, unsigned long addr, void *data)
>  	BUG_ON(pgnr >= map->count);
>  	pte_maddr = arbitrary_virt_to_machine(pte).maddr;
>
> +	/* Note: this will perform a pte_mkspecial() through the hypercall. */
>  	gnttab_set_map_op(&map->map_ops[pgnr], pte_maddr, flags,
>  			  map->grants[pgnr].ref,
>  			  map->grants[pgnr].domid);
> @@ -528,7 +529,7 @@ static void gntdev_vma_close(struct vm_area_struct *vma)
>  	gntdev_put_map(priv, map);
>  }
>
> -static struct page *gntdev_vma_find_special_page(struct vm_area_struct *vma,
> +static struct page *gntdev_vma_find_normal_page(struct vm_area_struct *vma,
>  						 unsigned long addr)
>  {
>  	struct gntdev_grant_map *map = vma->vm_private_data;
> @@ -539,7 +540,7 @@ static struct page *gntdev_vma_find_special_page(struct vm_area_struct *vma,
>  static const struct vm_operations_struct gntdev_vmops = {
>  	.open = gntdev_vma_open,
>  	.close = gntdev_vma_close,
> -	.find_special_page = gntdev_vma_find_special_page,
> +	.find_normal_page = gntdev_vma_find_normal_page,
>  };
>
>  /* ------------------------------------------------------------------ */
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index 8ca7d2fa71343..3868ca1a25f9c 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -657,13 +657,21 @@ struct vm_operations_struct {
>  	struct mempolicy *(*get_policy)(struct vm_area_struct *vma,
>  					unsigned long addr, pgoff_t *ilx);
>  #endif
> +#ifdef CONFIG_FIND_NORMAL_PAGE
>  	/*
> -	 * Called by vm_normal_page() for special PTEs to find the
> -	 * page for @addr.  This is useful if the default behavior
> -	 * (using pte_page()) would not find the correct page.
> +	 * Called by vm_normal_page() for special PTEs in @vma at @addr. This
> +	 * allows for returning a "normal" page from vm_normal_page() even
> +	 * though the PTE indicates that the "struct page" either does not exist
> +	 * or should not be touched: "special".
> +	 *
> +	 * Do not add new users: this really only works when a "normal" page
> +	 * was mapped, but then the PTE got changed to something weird (+
> +	 * marked special) that would not make pte_pfn() identify the originally
> +	 * inserted page.
>  	 */
> -	struct page *(*find_special_page)(struct vm_area_struct *vma,
> -					  unsigned long addr);
> +	struct page *(*find_normal_page)(struct vm_area_struct *vma,
> +					 unsigned long addr);
> +#endif /* CONFIG_FIND_NORMAL_PAGE */
>  };
>
>  #ifdef CONFIG_NUMA_BALANCING
> diff --git a/mm/Kconfig b/mm/Kconfig
> index e443fe8cd6cf2..59a04d0b2e272 100644
> --- a/mm/Kconfig
> +++ b/mm/Kconfig
> @@ -1381,6 +1381,8 @@ config PT_RECLAIM
>
>  	  Note: now only empty user PTE page table pages will be reclaimed.
>
> +config FIND_NORMAL_PAGE
> +	def_bool n
>
>  source "mm/damon/Kconfig"
>
> diff --git a/mm/memory.c b/mm/memory.c
> index 6f806bf3cc994..002c28795d8b7 100644
> --- a/mm/memory.c
> +++ b/mm/memory.c
> @@ -639,6 +639,12 @@ static void print_bad_page_map(struct vm_area_struct *vma,
>   * trivial. Secondly, an architecture may not have a spare page table
>   * entry bit, which requires a more complicated scheme, described below.
>   *
> + * With CONFIG_FIND_NORMAL_PAGE, we might have the "special" bit set on
> + * page table entries that actually map "normal" pages: however, that page
> + * cannot be looked up through the PFN stored in the page table entry, but
> + * instead will be looked up through vm_ops->find_normal_page(). So far, this
> + * only applies to PTEs.
> + *
>   * A raw VM_PFNMAP mapping (ie. one that is not COWed) is always considered a
>   * special mapping (even if there are underlying and valid "struct pages").
>   * COWed pages of a VM_PFNMAP are always normal.
> @@ -679,8 +685,10 @@ static inline struct page *__vm_normal_page(struct vm_area_struct *vma,
>  {
>  	if (IS_ENABLED(CONFIG_ARCH_HAS_PTE_SPECIAL)) {
>  		if (unlikely(special)) {
> -			if (vma->vm_ops && vma->vm_ops->find_special_page)
> -				return vma->vm_ops->find_special_page(vma, addr);
> +#ifdef CONFIG_FIND_NORMAL_PAGE
> +			if (vma->vm_ops && vma->vm_ops->find_normal_page)
> +				return vma->vm_ops->find_normal_page(vma, addr);
> +#endif /* CONFIG_FIND_NORMAL_PAGE */
>  			if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
>  				return NULL;
>  			if (is_zero_pfn(pfn) || is_huge_zero_pfn(pfn))
> diff --git a/tools/testing/vma/vma_internal.h b/tools/testing/vma/vma_internal.h
> index 3639aa8dd2b06..cb1c2a8afe265 100644
> --- a/tools/testing/vma/vma_internal.h
> +++ b/tools/testing/vma/vma_internal.h
> @@ -467,13 +467,21 @@ struct vm_operations_struct {
>  	struct mempolicy *(*get_policy)(struct vm_area_struct *vma,
>  					unsigned long addr, pgoff_t *ilx);
>  #endif
> +#ifdef CONFIG_FIND_NORMAL_PAGE
>  	/*
> -	 * Called by vm_normal_page() for special PTEs to find the
> -	 * page for @addr.  This is useful if the default behavior
> -	 * (using pte_page()) would not find the correct page.
> +	 * Called by vm_normal_page() for special PTEs in @vma at @addr. This
> +	 * allows for returning a "normal" page from vm_normal_page() even
> +	 * though the PTE indicates that the "struct page" either does not exist
> +	 * or should not be touched: "special".
> +	 *
> +	 * Do not add new users: this really only works when a "normal" page
> +	 * was mapped, but then the PTE got changed to something weird (+
> +	 * marked special) that would not make pte_pfn() identify the originally
> +	 * inserted page.
>  	 */
> -	struct page *(*find_special_page)(struct vm_area_struct *vma,
> -					  unsigned long addr);
> +	struct page *(*find_normal_page)(struct vm_area_struct *vma,
> +					 unsigned long addr);
> +#endif /* CONFIG_FIND_NORMAL_PAGE */
>  };
>
>  struct vm_unmapped_area_info {
> --
> 2.50.1
>


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Date: Tue, 12 Aug 2025 22:30:39 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall , Alejandro Vallejo 
Subject: [PATCH v16 1/4] xen/domain: unify domain ID allocation
Message-ID: <20250812223024.2364749-2-dmukhin@ford.com>
In-Reply-To: <20250812223024.2364749-1-dmukhin@ford.com>
References: <20250812223024.2364749-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Currently, there are two different domain ID allocation implementations:

  1) Sequential IDs allocation in dom0less Arm code based on max_init_domid=
;

  2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
     max_init_domid (both Arm and x86).

The domain ID allocation covers dom0 or late hwdom, predefined domains,
post-boot domains, excluding Xen system domains (domid >=3D
DOMID_FIRST_RESERVED).

It makes sense to have a common helper code for such task across architectu=
res
(Arm and x86) and between dom0less / toolstack domU allocation.

Note, fixing dependency on max_init_domid is out of scope of this patch.

Wrap the domain ID allocation as an arch-independent function domid_alloc()=
 in
new common/domid.c based on the bitmap.

Allocation algorithm:
- If an explicit domain ID is provided, verify its availability and use it =
if
  ID is not used;
- If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1=
],
  starting from the last used ID.
  Implementation guarantees that two consecutive calls will never return th=
e
  same ID. ID#0 is reserved for the first boot domain (currently, dom0) and
  excluded from the allocation range.

Remove is_free_domid() helper as it is not needed now.

No functional change intended.

Signed-off-by: Denis Mukhin 
Reviewed-by: Julien Grall 
Reviewed-by: Alejandro Vallejo 
---
Changes since v15:
- fixup for check after the first pass in the bitarray in domid_alloc()
- trivial renaming for the local variable in domid_alloc()
- kept Julien's R-b, added Alejandro's R-b
---
 xen/arch/arm/domain_build.c             |  7 +-
 xen/arch/x86/setup.c                    |  7 +-
 xen/common/Makefile                     |  1 +
 xen/common/device-tree/dom0less-build.c | 15 ++--
 xen/common/domain.c                     |  2 +
 xen/common/domctl.c                     | 43 ++---------
 xen/common/domid.c                      | 95 +++++++++++++++++++++++++
 xen/include/xen/domain.h                |  3 +
 8 files changed, 126 insertions(+), 47 deletions(-)
 create mode 100644 xen/common/domid.c

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index a9e4153e3cf9..aca35b8961d6 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2050,6 +2050,7 @@ void __init create_dom0(void)
         .grant_opts =3D XEN_DOMCTL_GRANT_version(opt_gnttab_max_version),
     };
     unsigned int flags =3D CDF_privileged | CDF_hardware;
+    domid_t domid;
     int rc;
=20
     /* The vGIC for DOM0 is exactly emulating the hardware GIC */
@@ -2074,7 +2075,11 @@ void __init create_dom0(void)
     if ( !llc_coloring_enabled )
         flags |=3D CDF_directmap;
=20
-    dom0 =3D domain_create(0, &dom0_cfg, flags);
+    domid =3D domid_alloc(0);
+    if ( domid =3D=3D DOMID_INVALID )
+        panic("Error allocating domain ID 0\n");
+
+    dom0 =3D domain_create(domid, &dom0_cfg, flags);
     if ( IS_ERR(dom0) )
         panic("Error creating domain 0 (rc =3D %ld)\n", PTR_ERR(dom0));
=20
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 1543dd251cc6..398da734c0c5 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1047,8 +1047,11 @@ static struct domain *__init create_dom0(struct boot=
_info *bi)
     if ( iommu_enabled )
         dom0_cfg.flags |=3D XEN_DOMCTL_CDF_iommu;
=20
-    /* Create initial domain.  Not d0 for pvshim. */
-    bd->domid =3D get_initial_domain_id();
+    /* Allocate initial domain ID.  Not d0 for pvshim. */
+    bd->domid =3D domid_alloc(get_initial_domain_id());
+    if ( bd->domid =3D=3D DOMID_INVALID )
+        panic("Error allocating domain ID %u\n", get_initial_domain_id());
+
     d =3D domain_create(bd->domid, &dom0_cfg,
                       pv_shim ? 0 : CDF_privileged | CDF_hardware);
     if ( IS_ERR(d) )
diff --git a/xen/common/Makefile b/xen/common/Makefile
index c316957fcb36..0c7d0f5d46e1 100644
--- a/xen/common/Makefile
+++ b/xen/common/Makefile
@@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) +=3D devic=
e.o
 obj-$(CONFIG_DEVICE_TREE_PARSE) +=3D device-tree/
 obj-$(CONFIG_IOREQ_SERVER) +=3D dm.o
 obj-y +=3D domain.o
+obj-y +=3D domid.o
 obj-y +=3D event_2l.o
 obj-y +=3D event_channel.o
 obj-$(CONFIG_EVTCHN_FIFO) +=3D event_fifo.o
diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tr=
ee/dom0less-build.c
index 6bb038111de9..f4b6b515d2d2 100644
--- a/xen/common/device-tree/dom0less-build.c
+++ b/xen/common/device-tree/dom0less-build.c
@@ -833,6 +833,7 @@ void __init create_domUs(void)
     {
         struct kernel_info ki =3D KERNEL_INFO_INIT;
         int rc =3D parse_dom0less_node(node, &ki.bd);
+        domid_t domid;
=20
         if ( rc =3D=3D -ENOENT )
             continue;
@@ -842,13 +843,13 @@ void __init create_domUs(void)
         if ( (max_init_domid + 1) >=3D DOMID_FIRST_RESERVED )
             panic("No more domain IDs available\n");
=20
-        /*
-         * The variable max_init_domid is initialized with zero, so here i=
t's
-         * very important to use the pre-increment operator to call
-         * domain_create() with a domid > 0. (domid =3D=3D 0 is reserved f=
or Dom0)
-         */
-        ki.bd.d =3D domain_create(++max_init_domid,
-                                &ki.bd.create_cfg, ki.bd.create_flags);
+        domid =3D domid_alloc(DOMID_INVALID);
+        if ( domid =3D=3D DOMID_INVALID )
+            panic("Error allocating ID for domain %s\n", dt_node_name(node=
));
+
+        max_init_domid =3D max(max_init_domid, domid);
+
+        ki.bd.d =3D domain_create(domid, &ki.bd.create_cfg, ki.bd.create_f=
lags);
         if ( IS_ERR(ki.bd.d) )
             panic("Error creating domain %s (rc =3D %ld)\n",
                   dt_node_name(node), PTR_ERR(ki.bd.d));
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 5241a1629eeb..a7e303253d1a 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -692,6 +692,8 @@ static void _domain_destroy(struct domain *d)
=20
     lock_profile_deregister_struct(LOCKPROF_TYPE_PERDOM, d);
=20
+    domid_free(d->domain_id);
+
     free_domain_struct(d);
 }
=20
diff --git a/xen/common/domctl.c b/xen/common/domctl.c
index f2a7caaf853c..71e712c1f316 100644
--- a/xen/common/domctl.c
+++ b/xen/common/domctl.c
@@ -51,20 +51,6 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nodemas=
k,
                                    MAX_NUMNODES);
 }
=20
-static inline int is_free_domid(domid_t dom)
-{
-    struct domain *d;
-
-    if ( dom >=3D DOMID_FIRST_RESERVED )
-        return 0;
-
-    if ( (d =3D rcu_lock_domain_by_id(dom)) =3D=3D NULL )
-        return 1;
-
-    rcu_unlock_domain(d);
-    return 0;
-}
-
 void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info=
)
 {
     struct vcpu *v;
@@ -423,36 +409,19 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u=
_domctl)
=20
     case XEN_DOMCTL_createdomain:
     {
-        domid_t        dom;
-        static domid_t rover =3D 0;
+        /* NB: ID#0 is reserved, find the first suitable ID instead. */
+        domid_t domid =3D domid_alloc(op->domain ?: DOMID_INVALID);
=20
-        dom =3D op->domain;
-        if ( (dom > 0) && (dom < DOMID_FIRST_RESERVED) )
+        if ( domid =3D=3D DOMID_INVALID )
         {
             ret =3D -EEXIST;
-            if ( !is_free_domid(dom) )
-                break;
-        }
-        else
-        {
-            for ( dom =3D rover + 1; dom !=3D rover; dom++ )
-            {
-                if ( dom =3D=3D DOMID_FIRST_RESERVED )
-                    dom =3D 1;
-                if ( is_free_domid(dom) )
-                    break;
-            }
-
-            ret =3D -ENOMEM;
-            if ( dom =3D=3D rover )
-                break;
-
-            rover =3D dom;
+            break;
         }
=20
-        d =3D domain_create(dom, &op->u.createdomain, false);
+        d =3D domain_create(domid, &op->u.createdomain, false);
         if ( IS_ERR(d) )
         {
+            domid_free(domid);
             ret =3D PTR_ERR(d);
             d =3D NULL;
             break;
diff --git a/xen/common/domid.c b/xen/common/domid.c
new file mode 100644
index 000000000000..2387ddb08300
--- /dev/null
+++ b/xen/common/domid.c
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Domain ID allocator.
+ *
+ * Covers dom0 or late hwdom, predefined domains, post-boot domains.
+ * Excludes system domains (ID >=3D DOMID_FIRST_RESERVED).
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include 
+
+static DEFINE_SPINLOCK(domid_lock);
+static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED);
+
+/*
+ * Allocate domain ID.
+ *
+ * @param domid Domain ID hint:
+ * - If an explicit domain ID is provided, verify its availability and use=
 it
+ *   if ID is not used;
+ * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] rang=
e,
+ *   starting from the last used ID. Implementation guarantees that two
+ *   consecutive calls will never return the same ID. ID#0 is reserved for
+ *   the first boot domain (currently, dom0) and excluded from the allocat=
ion
+ *   range.
+ * @return Valid domain ID in case of successful allocation,
+ *         DOMID_INVALID - otherwise.
+ */
+domid_t domid_alloc(domid_t domid)
+{
+    static domid_t domid_last;
+
+    spin_lock(&domid_lock);
+
+    /* Exact match. */
+    if ( domid < DOMID_FIRST_RESERVED )
+    {
+        if ( __test_and_set_bit(domid, domid_bitmap) )
+            domid =3D DOMID_INVALID;
+    }
+    /*
+     * Exhaustive search.
+     *
+     * Domain ID#0 is reserved for the first boot domain (e.g. control dom=
ain)
+     * and excluded from allocation.
+     */
+    else
+    {
+        domid_t bound =3D DOMID_FIRST_RESERVED;
+
+        domid =3D find_next_zero_bit(domid_bitmap, bound, domid_last + 1);
+        if ( domid >=3D bound && domid_last !=3D 0 )
+        {
+            bound =3D domid_last + 1;
+            domid =3D find_next_zero_bit(domid_bitmap, bound, 1);
+        }
+
+        ASSERT(domid <=3D DOMID_FIRST_RESERVED);
+        if ( domid < bound )
+        {
+            __set_bit(domid, domid_bitmap);
+            domid_last =3D domid;
+        }
+        else
+            domid =3D DOMID_INVALID;
+    }
+
+    spin_unlock(&domid_lock);
+
+    return domid;
+}
+
+void domid_free(domid_t domid)
+{
+    int rc;
+
+    ASSERT(domid <=3D DOMID_FIRST_RESERVED);
+
+    spin_lock(&domid_lock);
+    rc =3D __test_and_clear_bit(domid, domid_bitmap);
+    spin_unlock(&domid_lock);
+
+    ASSERT(rc);
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615fd..8aab05ae93c8 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -38,6 +38,9 @@ void arch_get_domain_info(const struct domain *d,
=20
 domid_t get_initial_domain_id(void);
=20
+domid_t domid_alloc(domid_t domid);
+void domid_free(domid_t domid);
+
 /* CDF_* constant. Internal flags for domain creation. */
 /* Is this a privileged domain? */
 #define CDF_privileged           (1U << 0)
--=20
2.34.1




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To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v16 0/4] xen/domain: domain ID allocation
Message-ID: <20250812223024.2364749-1-dmukhin@ford.com>
Feedback-ID: 123220910:user:proton
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Patch 1 introduces new domid_{alloc,free} calls.
Patch 2 is a prep change for domain ID allocator test.
Patch 3 introduces some basic testing for domain ID allocator.
Patch 4 adjusts create_dom0() messages (use %pd).

Link to v15: https://lore.kernel.org/xen-devel/20250809170747.1836880-1-dmu=
khin@ford.com/
Link to CI: https://gitlab.com/xen-project/people/dmukhin/xen/-/pipelines/1=
980989231

Denis Mukhin (4):
  xen/domain: unify domain ID allocation
  tools/include: move xc_bitops.h to xen-tools/bitops.h
  tools/tests: introduce unit tests for domain ID allocator
  xen/domain: update create_dom0() messages

 .../xen-tools/bitops.h}                       | 16 +++-
 tools/libs/ctrl/xc_misc.c                     | 13 +--
 tools/libs/guest/xg_dom_elfloader.c           |  3 +-
 tools/libs/guest/xg_dom_hvmloader.c           |  3 +-
 tools/libs/guest/xg_private.h                 |  2 +-
 tools/libs/guest/xg_sr_common.h               |  3 +-
 tools/tests/Makefile                          |  1 +
 tools/tests/domid/.gitignore                  |  3 +
 tools/tests/domid/Makefile                    | 84 ++++++++++++++++
 tools/tests/domid/harness.h                   | 54 +++++++++++
 tools/tests/domid/test-domid.c                | 93 ++++++++++++++++++
 xen/arch/arm/domain_build.c                   | 13 ++-
 xen/arch/x86/setup.c                          | 11 ++-
 xen/common/Makefile                           |  1 +
 xen/common/device-tree/dom0less-build.c       | 15 +--
 xen/common/domain.c                           |  2 +
 xen/common/domctl.c                           | 43 ++-------
 xen/common/domid.c                            | 95 +++++++++++++++++++
 xen/include/xen/domain.h                      |  3 +
 xen/lib/find-next-bit.c                       |  5 +
 20 files changed, 397 insertions(+), 66 deletions(-)
 rename tools/{libs/ctrl/xc_bitops.h =3D> include/xen-tools/bitops.h} (84%)
 create mode 100644 tools/tests/domid/.gitignore
 create mode 100644 tools/tests/domid/Makefile
 create mode 100644 tools/tests/domid/harness.h
 create mode 100644 tools/tests/domid/test-domid.c
 create mode 100644 xen/common/domid.c

--=20
2.34.1




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To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall 
Subject: [PATCH v16 3/4] tools/tests: introduce unit tests for domain ID allocator
Message-ID: <20250812223024.2364749-4-dmukhin@ford.com>
In-Reply-To: <20250812223024.2364749-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Introduce some basic infrastructure for doing domain ID allocation unit tes=
ts,
and add a few tests that ensure correctness of the domain ID allocator.

Use  and xen/lib/find-next-bit.c in test hardness code.

Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.

Signed-off-by: Denis Mukhin 
Reviewed-by: Julien Grall 
---
Changes since v15:
- fixed generating harness dependencies on the fly during the test build
- kept Julien's R-b
---
 tools/include/xen-tools/bitops.h | 10 ++++
 tools/tests/Makefile             |  1 +
 tools/tests/domid/.gitignore     |  3 ++
 tools/tests/domid/Makefile       | 84 +++++++++++++++++++++++++++++
 tools/tests/domid/harness.h      | 54 +++++++++++++++++++
 tools/tests/domid/test-domid.c   | 93 ++++++++++++++++++++++++++++++++
 xen/lib/find-next-bit.c          |  5 ++
 7 files changed, 250 insertions(+)
 create mode 100644 tools/tests/domid/.gitignore
 create mode 100644 tools/tests/domid/Makefile
 create mode 100644 tools/tests/domid/harness.h
 create mode 100644 tools/tests/domid/test-domid.c

diff --git a/tools/include/xen-tools/bitops.h b/tools/include/xen-tools/bit=
ops.h
index 681482f6759f..3b98fba6d74c 100644
--- a/tools/include/xen-tools/bitops.h
+++ b/tools/include/xen-tools/bitops.h
@@ -12,6 +12,16 @@
 #define BITS_PER_LONG 32
 #endif
=20
+#define ffsl(x)       __builtin_ffsl(x)
+
+#define BIT_WORD(nr)  ((nr) / BITS_PER_LONG)
+
+#define BITS_TO_LONGS(bits) \
+    (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
+
+#define DECLARE_BITMAP(name, bits) \
+    unsigned long name[BITS_TO_LONGS(bits)]
+
 #define BITMAP_ENTRY(_nr,_bmap) ((_bmap))[(_nr) / 8]
 #define BITMAP_SHIFT(_nr) ((_nr) % 8)
=20
diff --git a/tools/tests/Makefile b/tools/tests/Makefile
index 97ba2a13894d..ac5737364623 100644
--- a/tools/tests/Makefile
+++ b/tools/tests/Makefile
@@ -2,6 +2,7 @@ XEN_ROOT =3D $(CURDIR)/../..
 include $(XEN_ROOT)/tools/Rules.mk
=20
 SUBDIRS-y :=3D
+SUBDIRS-y +=3D domid
 SUBDIRS-y +=3D resource
 SUBDIRS-$(CONFIG_X86) +=3D cpu-policy
 SUBDIRS-$(CONFIG_X86) +=3D tsx
diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignore
new file mode 100644
index 000000000000..0e02715159c2
--- /dev/null
+++ b/tools/tests/domid/.gitignore
@@ -0,0 +1,3 @@
+*.o
+generated
+test-domid
diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile
new file mode 100644
index 000000000000..0a124a8bfc76
--- /dev/null
+++ b/tools/tests/domid/Makefile
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Unit tests for domain ID allocator.
+#
+# Copyright 2025 Ford Motor Company
+
+XEN_ROOT=3D$(CURDIR)/../../..
+include $(XEN_ROOT)/tools/Rules.mk
+
+TESTS :=3D test-domid
+
+strip-list =3D $(sort $(strip $(foreach x,$(1),$(strip $(x)))))
+
+define list-c-headers
+$(shell sed -n -r \
+    's/^[ \t]*# *include[ \t]*[<"]([^">]+)[">].*/\1/p' $(1) 2>/dev/null)
+endef
+
+define emit-harness-nested-rule
+$(1): $(CURDIR)/harness.h
+=09mkdir -p $$(dir $$@)
+=09ln -sf $$^ $$@
+endef
+
+define emit-harness-rules
+ifneq ($(strip $(3)),)
+$(foreach h,$(3),$(call emit-harness-nested-rule,$(CURDIR)/generated/$(h))=
)
+vpath $(1) $(2)
+$(1:.c=3D.o): $(addprefix $(CURDIR)/generated/,$(3))
+endif
+endef
+
+define vpath-with-harness-deps
+$(call emit-harness-rules,$(1),$(2),\
+    $(call strip-list,$(call list-c-headers,$(2)$(1))))
+endef
+
+.PHONY: all
+all: $(TESTS)
+
+.PHONY: run
+run: $(TESTS)
+=09$(foreach t,$(TESTS),./$(t);)
+
+.PHONY: clean
+clean:
+=09$(RM) -rf $(CURDIR)/generated
+=09$(RM) -- *.o $(TESTS) $(DEPS_RM)
+
+.PHONY: distclean
+distclean: clean
+=09$(RM) -- *~
+
+.PHONY: install
+install: all
+=09$(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests
+=09$(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests
+
+.PHONY: uninstall
+uninstall:
+=09$(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid
+
+CFLAGS +=3D -D__XEN_TOOLS__
+# find-next-bit.c
+CFLAGS +=3D '-DEXPORT_SYMBOL(x)=3D' \
+          -Dfind_first_bit \
+          -Dfind_first_zero_bit \
+          -Dfind_next_bit \
+          -Dfind_next_bit_le \
+          -Dfind_next_zero_bit_le
+CFLAGS +=3D $(APPEND_CFLAGS)
+CFLAGS +=3D $(CFLAGS_xeninclude)
+CFLAGS +=3D -I./generated/
+
+LDFLAGS +=3D $(APPEND_LDFLAGS)
+
+vpath find-next-bit.c $(XEN_ROOT)/xen/lib/
+# Ubuntu {16,18}.04 need single eval at the call site.
+$(eval $(call vpath-with-harness-deps,domid.c,$(XEN_ROOT)/xen/common/))
+
+test-domid: domid.o find-next-bit.o test-domid.o
+=09$(CC) $^ -o $@ $(LDFLAGS)
+
+-include $(DEPS_INCLUDE)
diff --git a/tools/tests/domid/harness.h b/tools/tests/domid/harness.h
new file mode 100644
index 000000000000..17eb22a9a854
--- /dev/null
+++ b/tools/tests/domid/harness.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Unit test harness for domain ID allocator.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#ifndef _TEST_HARNESS_
+#define _TEST_HARNESS_
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+typedef bool spinlock_t;
+typedef uint16_t domid_t;
+
+extern domid_t domid_alloc(domid_t domid);
+extern void domid_free(domid_t domid);
+
+extern unsigned long find_next_zero_bit(const unsigned long *addr,
+                                        unsigned long size,
+                                        unsigned long offset);
+
+#define __test_and_set_bit(nr, addr)    test_and_set_bit(nr, addr)
+#define __test_and_clear_bit(nr, addr)  test_and_clear_bit(nr, addr)
+#define __set_bit(nr, addr)             set_bit(nr, addr)
+
+#define BUG_ON(x)                       assert(!(x))
+#define ASSERT(x)                       assert(x)
+
+#define DEFINE_SPINLOCK(l)              spinlock_t l
+#define spin_lock(l)                    (assert(!*(l)), *(l) =3D true)
+#define spin_unlock(l)                  (assert(*(l)), *(l) =3D false)
+
+#define printk                          printf
+
+#define DOMID_FIRST_RESERVED            (100)
+#define DOMID_INVALID                   (101)
+
+#endif /* _TEST_HARNESS_ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-domid.=
c
new file mode 100644
index 000000000000..51a88a6a9550
--- /dev/null
+++ b/tools/tests/domid/test-domid.c
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Unit tests for domain ID allocator.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include "harness.h"
+
+#define verify(exp, fmt, args...) do { \
+    if ( !(exp) ) \
+        printf(fmt, ## args); \
+    assert(exp); \
+} while (0);
+
+/*
+ * Fail on the first error, since tests are dependent on each other.
+ */
+int main(int argc, char **argv)
+{
+    domid_t expected, allocated;
+
+    /* Test ID cannot be allocated twice. */
+    for ( expected =3D 0; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(expected);
+        verify(allocated =3D=3D expected,
+               "TEST 1: expected %u allocated %u\n", expected, allocated);
+    }
+    for ( expected =3D 0; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(expected);
+        verify(allocated =3D=3D DOMID_INVALID,
+               "TEST 2: expected %u allocated %u\n", DOMID_INVALID, alloca=
ted);
+    }
+
+    /* Ensure all IDs, including ID#0 are not allocated. */
+    for ( expected =3D 0; expected < DOMID_FIRST_RESERVED; expected++ )
+        domid_free(expected);
+
+    /*
+     * Test that that two consecutive calls of domid_alloc(DOMID_INVALID)
+     * will never return the same ID.
+     * NB: ID#0 is reserved and shall not be allocated by
+     * domid_alloc(DOMID_INVALID).
+     */
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(DOMID_INVALID);
+        verify(allocated =3D=3D expected,
+               "TEST 3: expected %u allocated %u\n", expected, allocated);
+    }
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated =3D domid_alloc(DOMID_INVALID);
+        verify(allocated =3D=3D DOMID_INVALID,
+               "TEST 4: expected %u allocated %u\n", DOMID_INVALID, alloca=
ted);
+    }
+
+    /* Re-allocate first ID from [1..DOMID_FIRST_RESERVED/2]. */
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED / 2; expected++ =
)
+        domid_free(expected);
+    for ( expected =3D 1; expected < DOMID_FIRST_RESERVED / 2; expected++ =
)
+    {
+        allocated =3D domid_alloc(DOMID_INVALID);
+        verify(allocated =3D=3D expected,
+               "TEST 5: expected %u allocated %u\n", expected, allocated);
+    }
+
+    /* Re-allocate last ID from [1..DOMID_FIRST_RESERVED - 1]. */
+    expected =3D DOMID_FIRST_RESERVED - 1;
+    domid_free(DOMID_FIRST_RESERVED - 1);
+    allocated =3D domid_alloc(DOMID_INVALID);
+    verify(allocated =3D=3D expected,
+           "TEST 6: expected %u allocated %u\n", expected, allocated);
+
+    /* Allocate an invalid ID. */
+    expected =3D DOMID_INVALID;
+    allocated =3D domid_alloc(DOMID_FIRST_RESERVED);
+    verify(allocated =3D=3D expected,
+           "TEST 7: expected %u allocated %u\n", expected, allocated);
+
+    return 0;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/lib/find-next-bit.c b/xen/lib/find-next-bit.c
index 9b8d7814f20c..539c7f2022b0 100644
--- a/xen/lib/find-next-bit.c
+++ b/xen/lib/find-next-bit.c
@@ -8,8 +8,13 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
+
+#ifdef __XEN_TOOLS__
+#include 
+#else
 #include 
 #include 
+#endif
=20
 #define __ffs(x) (ffsl(x) - 1)
 #define ffz(x) __ffs(~(x))
--=20
2.34.1




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To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v16 2/4] tools/include: move xc_bitops.h to xen-tools/bitops.h
Message-ID: <20250812223024.2364749-3-dmukhin@ford.com>
In-Reply-To: <20250812223024.2364749-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Move xc_bitops.h to common tools location to be shared between
the toolstack and unit test code.

Adjust the guard in xen-tools/bitops.h

Correct the #include directives and comments referring to the old
xc_bitops.h in the toolstack code.

Signed-off-by: Denis Mukhin 
---
Changes since v15:
- n/a
---
 .../ctrl/xc_bitops.h =3D> include/xen-tools/bitops.h} |  6 +++---
 tools/libs/ctrl/xc_misc.c                           | 13 +++++++------
 tools/libs/guest/xg_dom_elfloader.c                 |  3 ++-
 tools/libs/guest/xg_dom_hvmloader.c                 |  3 ++-
 tools/libs/guest/xg_private.h                       |  2 +-
 tools/libs/guest/xg_sr_common.h                     |  3 +--
 6 files changed, 16 insertions(+), 14 deletions(-)
 rename tools/{libs/ctrl/xc_bitops.h =3D> include/xen-tools/bitops.h} (95%)

diff --git a/tools/libs/ctrl/xc_bitops.h b/tools/include/xen-tools/bitops.h
similarity index 95%
rename from tools/libs/ctrl/xc_bitops.h
rename to tools/include/xen-tools/bitops.h
index 4a776dc3a57f..681482f6759f 100644
--- a/tools/libs/ctrl/xc_bitops.h
+++ b/tools/include/xen-tools/bitops.h
@@ -1,5 +1,5 @@
-#ifndef XC_BITOPS_H
-#define XC_BITOPS_H 1
+#ifndef __XEN_TOOLS_BITOPS_H__
+#define __XEN_TOOLS_BITOPS_H__
=20
 /* bitmap operations for single threaded access */
=20
@@ -81,4 +81,4 @@ static inline void bitmap_or(void *_dst, const void *_oth=
er,
         dst[i] |=3D other[i];
 }
=20
-#endif  /* XC_BITOPS_H */
+#endif  /* __XEN_TOOLS_BITOPS_H__ */
diff --git a/tools/libs/ctrl/xc_misc.c b/tools/libs/ctrl/xc_misc.c
index 33e87bac2868..10ddf85667a9 100644
--- a/tools/libs/ctrl/xc_misc.c
+++ b/tools/libs/ctrl/xc_misc.c
@@ -17,8 +17,8 @@
  * License along with this library; If not, see .
  */
=20
-#include "xc_bitops.h"
 #include "xc_private.h"
+#include 
 #include 
=20
 int xc_get_max_cpus(xc_interface *xch)
@@ -94,11 +94,12 @@ xc_cpumap_t xc_cpumap_alloc(xc_interface *xch)
 }
=20
 /*
- * xc_bitops.h has macros that do this as well - however they assume that
- * the bitmask is word aligned but xc_cpumap_t is only guaranteed to be
- * byte aligned and so we need byte versions for architectures which do
- * not support misaligned accesses (which is basically everyone
- * but x86, although even on x86 it can be inefficient).
+ *  has macros that do this as well - however they
+ * assume that the bitmask is word aligned but xc_cpumap_t is only
+ * guaranteed to be byte aligned and so we need byte versions for
+ * architectures which do not support misaligned accesses (which is
+ * basically everyone but x86, although even on x86 it can be
+ * inefficient).
  *
  * NOTE: The xc_bitops macros now use byte alignment.
  * TODO: Clean up the users of this interface.
diff --git a/tools/libs/guest/xg_dom_elfloader.c b/tools/libs/guest/xg_dom_=
elfloader.c
index f17930d98bf7..8531e90f8e21 100644
--- a/tools/libs/guest/xg_dom_elfloader.c
+++ b/tools/libs/guest/xg_dom_elfloader.c
@@ -25,8 +25,9 @@
 #include 
 #include 
=20
+#include 
+
 #include "xg_private.h"
-#include "xc_bitops.h"
=20
 #define XEN_VER "xen-3.0"
=20
diff --git a/tools/libs/guest/xg_dom_hvmloader.c b/tools/libs/guest/xg_dom_=
hvmloader.c
index 39e1e5f579a7..0f569c20c522 100644
--- a/tools/libs/guest/xg_dom_hvmloader.c
+++ b/tools/libs/guest/xg_dom_hvmloader.c
@@ -24,8 +24,9 @@
 #include 
 #include 
=20
+#include 
+
 #include "xg_private.h"
-#include "xc_bitops.h"
=20
 /* -----------------------------------------------------------------------=
- */
 /* parse elf binary                                                       =
  */
diff --git a/tools/libs/guest/xg_private.h b/tools/libs/guest/xg_private.h
index d73947094f2e..285229cf82a3 100644
--- a/tools/libs/guest/xg_private.h
+++ b/tools/libs/guest/xg_private.h
@@ -28,9 +28,9 @@
 #include 
=20
 #include "xc_private.h"
-#include "xc_bitops.h"
 #include "xenguest.h"
=20
+#include 
 #include 
 #include 
 #include 
diff --git a/tools/libs/guest/xg_sr_common.h b/tools/libs/guest/xg_sr_commo=
n.h
index 2f058ee3a6ff..2e583f2eac72 100644
--- a/tools/libs/guest/xg_sr_common.h
+++ b/tools/libs/guest/xg_sr_common.h
@@ -2,11 +2,10 @@
 #define __COMMON__H
=20
 #include 
+#include 
=20
 #include "xg_private.h"
 #include "xg_save_restore.h"
-#include "xc_bitops.h"
-
 #include "xg_sr_stream_format.h"
=20
 /* String representation of Domain Header types. */
--=20
2.34.1




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Date: Tue, 12 Aug 2025 22:30:55 +0000
To: xen-devel@lists.xenproject.org
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Alejandro Vallejo , Julien Grall 
Subject: [PATCH v16 4/4] xen/domain: update create_dom0() messages
Message-ID: <20250812223024.2364749-5-dmukhin@ford.com>
In-Reply-To: <20250812223024.2364749-1-dmukhin@ford.com>
References: <20250812223024.2364749-1-dmukhin@ford.com>
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From: Denis Mukhin =20

Use %pd for domain identification in error/panic messages in create_dom0().

No functional change.

Signed-off-by: Denis Mukhin 
Reviewed-by: Alejandro Vallejo 
Acked-by: Jan Beulich 
Reviewed-by: Julien Grall 
---
Changes since v15:
- n/a
---
 xen/arch/arm/domain_build.c | 6 +++---
 xen/arch/x86/setup.c        | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index aca35b8961d6..670f634b8b0d 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2084,14 +2084,14 @@ void __init create_dom0(void)
         panic("Error creating domain 0 (rc =3D %ld)\n", PTR_ERR(dom0));
=20
     if ( llc_coloring_enabled && (rc =3D dom0_set_llc_colors(dom0)) )
-        panic("Error initializing LLC coloring for domain 0 (rc =3D %d)\n"=
, rc);
+        panic("Error initializing LLC coloring for %pd (rc =3D %d)\n", dom=
0, rc);
=20
     if ( vcpu_create(dom0, 0) =3D=3D NULL )
-        panic("Error creating domain 0 vcpu0\n");
+        panic("Error creating %pdv0\n", dom0);
=20
     rc =3D construct_dom0(dom0);
     if ( rc )
-        panic("Could not set up DOM0 guest OS (rc =3D %d)\n", rc);
+        panic("Could not set up %pd guest OS (rc =3D %d)\n", dom0, rc);
=20
     set_xs_domain(dom0);
 }
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 398da734c0c5..bf21c55f7193 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1084,7 +1084,7 @@ static struct domain *__init create_dom0(struct boot_=
info *bi)
=20
         if ( (strlen(acpi_param) =3D=3D 0) && acpi_disabled )
         {
-            printk("ACPI is disabled, notifying Domain 0 (acpi=3Doff)\n");
+            printk("ACPI is disabled, notifying %pd (acpi=3Doff)\n", d);
             safe_strcpy(acpi_param, "off");
         }
=20
@@ -1099,7 +1099,7 @@ static struct domain *__init create_dom0(struct boot_=
info *bi)
=20
     bd->d =3D d;
     if ( construct_dom0(bd) !=3D 0 )
-        panic("Could not construct domain 0\n");
+        panic("Could not construct %pd\n", d);
=20
     bd->cmdline =3D NULL;
     xfree(cmdline);
--=20
2.34.1




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Subject: Re: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
Content-Language: en-GB
To: Jan Beulich ,
 Dmytro Prokopchuk1 
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "xen-devel@lists.xenproject.org" 
References: <7cd71ed21383c189fedb3250ddde54a593f7f98b.1754944131.git.dmytro_prokopchuk1@epam.com>
 <59396fd1-ca82-4655-9dcf-ec36e0d51ffc@xen.org>
 
From: Julien Grall 
In-Reply-To: 
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Content-Transfer-Encoding: 7bit

Hi Jan,

On 12/08/2025 08:32, Jan Beulich wrote:
> On 11.08.2025 23:21, Julien Grall wrote:
>> On 11/08/2025 21:30, Dmytro Prokopchuk1 wrote:
>>> --- a/xen/common/grant_table.c
>>> +++ b/xen/common/grant_table.c
>>> @@ -330,9 +330,12 @@ shared_entry_header(struct grant_table *t, grant_ref_t ref)
>>>            /* Returned values should be independent of speculative execution */
>>>            block_speculation();
>>>            return &shared_entry_v2(t, ref).hdr;
>>> +
>>> +    default:
>>> +        ASSERT_UNREACHABLE();
>>> +        break;
>>>        }
>>>    
>>> -    ASSERT_UNREACHABLE();
>>   >       block_speculation();>
>>>        return NULL;
>>
>> I know you are trying to apply the MISRA rule. But this is odd that you
>> move the ASSERT_UNREACHABLE() but then code after is still only
>> reachable from the default. In fact, this is introducing a risk if
>> someone decides to add a new case but then forgot to return a value.
>>
>> By moving the two other lines, the compiler should be able to throw an
>> error if you forgot a return.
> 
> I think we did discuss this pattern in the past. While moving everything up
> to the "return" into the default: handling will please Eclair / Misra, we'll
> then end up with no return statement at the end of a non-void function.
> Beyond being good practice (imo) to have such a "main" return statement,
> that's actually another rule, just one we apparently didn't accept (15.5).

Reading 15.5, this seems to be about having a single return in the 
function. Unless I misunderstood something, this is different from what 
you suggest.

Anyway, my main problem with this change is that ASSERT_UNREACHABLE() is 
moved. I could possibly settle with:

default:
   break;
}

ASSERT_UNREACHABLE();
...

But at least to me, this pattern is more difficult to read because I 
have to look through the switch to understand the patch is only meant ot 
be used by the "default" case.

Cheers,

-- 
Julien Grall



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Date: Tue, 12 Aug 2025 16:09:47 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Ayan Kumar Halder 
cc: xen-devel@lists.xenproject.org, sstabellini@kernel.org, 
    michal.orzel@amd.com, andrei.cherechesu@nxp.com, dmukhin@ford.com
Subject: Re: [ImageBuilder v2] Add config option to use separate load commands
 for Xen, DOM0 and DOMU binaries
In-Reply-To: <20250812151945.2430295-1-ayan.kumar.halder@amd.com>
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On Tue, 12 Aug 2025, Ayan Kumar Halder wrote:
> Introduce the following options :-
> 1. XEN_LOAD - This specifies command to load xen hypervisor binary and device
> tree.
> 2. DOM0_LOAD - This specifies command to load Dom0 binaries.
> 3. DOMU_LOAD[] - This specifies command to load DomU binaries.
> 
> There can be situations where Xen, Dom0 and DomU binaries are stored in
> different partitions. Thus, imagebuilder should provide a way the binaries
> using different commands.
> 
> If any of the above options are not specified, LOAD_CMD is used by default.
> 
> Signed-off-by: Ayan Kumar Halder 


Reviewed-by: Stefano Stabellini 

with a small caveat: the exits should be exit 1 because they are due to
errors. I made the change on commit.


> ---
> This patch should be applied first.
> 
> Changes from :-
> 
> v1 - 1. Make LOAD_CMD optional when XEN is set
> 2. find_root_dev() should be invoked with either "$DOM0_CMD" or "$LOAD_CMD"
> depending on if it is invoked from xen_config() or linux_config().
> 3. User needs to set either LOAD_CMD or XEN_LOAD. If neither is set, throw
> an error. This is true for DOM0_LOAD and DOMU_LOAD[].
> 
>  README.md                | 18 +++++++++-
>  scripts/uboot-script-gen | 76 ++++++++++++++++++++++++++++------------
>  2 files changed, 71 insertions(+), 23 deletions(-)
> 
> diff --git a/README.md b/README.md
> index b7be268..59919df 100644
> --- a/README.md
> +++ b/README.md
> @@ -33,10 +33,12 @@ BOOT_CMD="booti"
>  
>  DEVICE_TREE="mpsoc.dtb"
>  XEN="xen"
> +XEN_LOAD="ext4load mmc 0:1"
>  XEN_CMD="console=dtuart dtuart=serial0 dom0_mem=1G dom0_max_vcpus=1 bootscrub=0 vwfi=native sched=null"
>  PASSTHROUGH_DTS_REPO="git@github.com:Xilinx/xen-passthrough-device-trees.git device-trees-2021.2/zcu102"
>  DOM0_KERNEL="Image-dom0"
>  DOM0_CMD="console=hvc0 earlycon=xen earlyprintk=xen clk_ignore_unused"
> +DOM0_LOAD="ext4load mmc 2:1"
>  DOM0_RAMDISK="dom0-ramdisk.cpio"
>  DOM0_MEM=1024
>  DOM0_VCPUS=1
> @@ -46,11 +48,13 @@ DT_OVERLAY[0]="host_dt_overlay.dtbo"
>  
>  NUM_DOMUS=2
>  DOMU_KERNEL[0]="zynqmp-dom1/Image-domU"
> +DOMU_LOAD[0]="ext4load mmc 4:1"
>  DOMU_PASSTHROUGH_PATHS[0]="/axi/ethernet@ff0e0000 /axi/serial@ff000000"
>  DOMU_CMD[0]="console=ttyPS0 earlycon console=ttyPS0,115200 clk_ignore_unused rdinit=/sbin/init root=/dev/ram0 init=/bin/sh"
>  DOMU_RAMDISK[0]="zynqmp-dom1/domU-ramdisk.cpio"
>  DOMU_COLORS[0]="6-14"
>  DOMU_KERNEL[1]="zynqmp-dom2/Image-domU"
> +DOMU_LOAD[1]="ext4load mmc 5:1"
>  DOMU_CMD[1]="console=ttyAMA0 clk_ignore_unused rdinit=/sbin/init root=/dev/ram0 init=/bin/sh"
>  DOMU_RAMDISK[1]="zynqmp-dom2/domU-ramdisk.cpio"
>  DOMU_MEM[1]=512
> @@ -77,7 +81,9 @@ Where:
>  - LOAD_CMD specifies the u-boot command used to load the binaries. This
>    can be left out of the config and be (over)written by the -t CLI
>    argument. It has to be set either in the config file or CLI argument
> -  though.
> +  though. This is optional when XEN is set as user can provide specific
> +  options (ie XEN_LOAD, DOM0_LOAD, DOMU_LOAD) to load Xen, Dom0 and DomU
> +  binaries.
>  
>  - BOOT_CMD specifies the u-boot command used to boot the binaries.
>    By default, it is 'booti'. The acceptable values are 'booti', 'bootm',
> @@ -99,6 +105,9 @@ Where:
>  - XEN_CMD specifies the command line arguments used for Xen.  If not
>    set, the default one will be used.
>  
> +- XEN_LOAD specifies the command to load XEN and DEVICE_TREE. If not set,
> +  LOAD_CMD will be used.
> +
>  - XEN_STATIC_HEAP="baseaddr1 size1 ... baseaddrN sizeN"
>    if specified, indicates the host physical address regions
>    [baseaddr, baseaddr + size) to be reserved as Xen static heap.
> @@ -109,6 +118,9 @@ Where:
>    uboot-script-gen will compile the partial device trees which have
>    been specified in DOMU_PASSTHROUGH_PATHS[number].
>  
> +- DOM0_LOAD specifies the command to load DOM0_KERNEL and DOM0_RAMDISK. If not
> +  set, LOAD_CMD will be used.
> +
>  - DOM0_KERNEL specifies the Dom0 kernel file to load.
>    For dom0less configurations, the parameter is optional.
>  
> @@ -159,6 +171,10 @@ Where:
>    kernel. If not set and DOMU_VPL011[number] is not set to 0, then
>    "console=ttyAMA0" is used.
>  
> +- DOMU_LOAD[number] specifies the command to load DOMU_KERNEL[number],
> +  DOMU_RAMDISK[number] and DOMU_PASSTHROUGH_DTB[number]. If not set, then
> +  LOAD_CMD is used.
> +
>  - DOMU_RAMDISK[number] specifies the DomU ramdisk to use.
>  
>  - DOMU_PASSTHROUGH_PATHS[number] specifies the passthrough devices (
> diff --git a/scripts/uboot-script-gen b/scripts/uboot-script-gen
> index b81e614..656de72 100755
> --- a/scripts/uboot-script-gen
> +++ b/scripts/uboot-script-gen
> @@ -737,6 +737,7 @@ function load_file()
>  {
>      local filename=$1
>      local fit_scr_name=$2
> +    local load_cmd=$3
>  
>      local absolute_path="$(realpath --no-symlinks $filename)"
>      local base="$(realpath $PWD)"/
> @@ -748,10 +749,10 @@ function load_file()
>          add_size_from_file $filename
>      else
>          if test "$CALC"; then
> -            echo "$LOAD_CMD \${memaddr} ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
> +            echo "$load_cmd \${memaddr} ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
>              add_size_calculate $fit_scr_name
>          else
> -            echo "$LOAD_CMD $memaddr ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
> +            echo "$load_cmd $memaddr ${prepend_path:+$prepend_path/}$relative_path" >> $UBOOT_SOURCE
>              add_size_from_file $filename
>          fi
>      fi
> @@ -830,10 +831,10 @@ function check_compressed_file_type()
>  
>  function find_root_dev()
>  {
> -
> -    local dev=${LOAD_CMD%:*}
> +    local load_cmd="$1"
> +    local dev=${load_cmd%:*}
>      dev=${dev##* }
> -    local par=${LOAD_CMD#*:}
> +    local par=${load_cmd#*:}
>  
>      if [ -z "$dev" ] || [ -z "$par" ]
>      then
> @@ -844,10 +845,10 @@ function find_root_dev()
>  
>      par=$((par + 1))
>  
> -    if [[ $LOAD_CMD =~ mmc ]]
> +    if [[ $load_cmd =~ mmc ]]
>      then
>          root_dev="/dev/mmcblk${dev}p${par}"
> -    elif [[ $LOAD_CMD =~ scsi ]]
> +    elif [[ $load_cmd =~ scsi ]]
>      then
>          # converts number to a scsi device character
>          dev=$((dev + 97))
> @@ -925,7 +926,7 @@ function xen_config()
>          then
>              DOM0_CMD="$DOM0_CMD root=/dev/ram0"
>          else
> -            find_root_dev
> +            find_root_dev "$DOM0_LOAD"
>              # $root_dev is set by find_root_dev
>              DOM0_CMD="$DOM0_CMD root=$root_dev"
>          fi
> @@ -973,7 +974,7 @@ function linux_config()
>          then
>              LINUX_CMD="$LINUX_CMD root=/dev/ram0"
>          else
> -            find_root_dev
> +            find_root_dev "$LOAD_CMD"
>              # $root_dev is set by find_root_dev
>              LINUX_CMD="$LINUX_CMD root=$root_dev"
>          fi
> @@ -1003,11 +1004,22 @@ generate_uboot_images()
>  
>  xen_file_loading()
>  {
> +    if test -z "$DOM0_LOAD"
> +    then
> +        if test "$LOAD_CMD"
> +        then
> +            DOM0_LOAD="$LOAD_CMD"
> +        else
> +            echo "Neither DOM0_LOAD nor LOAD_CMD is specified"
> +            exit
> +        fi
> +    fi
> +
>      if test "$DOM0_KERNEL"
>      then
>          check_compressed_file_type $DOM0_KERNEL "executable\|uImage"
>          dom0_kernel_addr=$memaddr
> -        load_file $DOM0_KERNEL "dom0_linux"
> +        load_file $DOM0_KERNEL "dom0_linux" "$DOM0_LOAD"
>          dom0_kernel_size=$filesize
>      fi
>      if test "$DOM0_RAMDISK"
> @@ -1015,7 +1027,7 @@ xen_file_loading()
>          check_compressed_file_type $DOM0_RAMDISK "cpio archive"
>          ramdisk_addr=$memaddr
>          ramdisk_path=$DOM0_RAMDISK
> -        load_file "$DOM0_RAMDISK" "dom0_ramdisk"
> +        load_file "$DOM0_RAMDISK" "dom0_ramdisk" "$DOM0_LOAD"
>          ramdisk_size=$filesize
>      else
>          ramdisk_addr="-"
> @@ -1024,6 +1036,16 @@ xen_file_loading()
>      i=0
>      while test $i -lt $NUM_DOMUS
>      do
> +        if test -z "${DOMU_LOAD[$i]}"
> +        then
> +            if test "$LOAD_CMD"
> +            then
> +                DOMU_LOAD[$i]="$LOAD_CMD"
> +            else
> +                echo "Neither DOMU_LOAD[] nor LOAD_CMD is specified"
> +                exit
> +            fi
> +        fi
>          if test "${DOMU_ROOTFS[$i]}" || test "${DOMU_NOBOOT[$i]}"
>          then
>              if test -z "${DOMU_NOBOOT[$i]}"
> @@ -1042,20 +1064,20 @@ xen_file_loading()
>  
>          check_compressed_file_type ${DOMU_KERNEL[$i]} "executable\|uImage"
>          domU_kernel_addr[$i]=$memaddr
> -        load_file ${DOMU_KERNEL[$i]} "domU${i}_kernel"
> +        load_file ${DOMU_KERNEL[$i]} "domU${i}_kernel" "${DOMU_LOAD[$i]}"
>          domU_kernel_size[$i]=$filesize
>          if test "${DOMU_RAMDISK[$i]}"
>          then
>              check_compressed_file_type ${DOMU_RAMDISK[$i]} "cpio archive"
>              domU_ramdisk_addr[$i]=$memaddr
> -            load_file ${DOMU_RAMDISK[$i]} "domU${i}_ramdisk"
> +            load_file ${DOMU_RAMDISK[$i]} "domU${i}_ramdisk" "${DOMU_LOAD[$i]}"
>              domU_ramdisk_size[$i]=$filesize
>          fi
>          if test "${DOMU_PASSTHROUGH_DTB[$i]}"
>          then
>              check_compressed_file_type ${DOMU_PASSTHROUGH_DTB[$i]} "Device Tree Blob"
>              domU_passthrough_dtb_addr[$i]=$memaddr
> -            load_file ${DOMU_PASSTHROUGH_DTB[$i]} "domU${i}_fdt"
> +            load_file ${DOMU_PASSTHROUGH_DTB[$i]} "domU${i}_fdt" "${DOMU_LOAD[$i]}"
>              domU_passthrough_dtb_size[$i]=$filesize
>          fi
>          i=$(( $i + 1 ))
> @@ -1070,9 +1092,20 @@ xen_file_loading()
>          generate_uboot_images
>      fi
>  
> +    if test -z "$XEN_LOAD"
> +    then
> +        if test "$LOAD_CMD"
> +        then
> +            XEN_LOAD="$LOAD_CMD"
> +        else
> +            echo "Neither XEN_LOAD nor LOAD_CMD is specified"
> +            exit
> +        fi
> +    fi
> +
>      kernel_addr=$memaddr
>      kernel_path=$XEN
> -    load_file "$XEN" "host_kernel"
> +    load_file "$XEN" "host_kernel" "$XEN_LOAD"
>  
>      xen_policy_addr="-"
>      if test -n "$XEN_POLICY"
> @@ -1518,12 +1551,6 @@ then
>      FIT="${UBOOT_SOURCE%.source}.fit"
>  fi
>  
> -if test ! "$LOAD_CMD"
> -then
> -    echo "LOAD_CMD not set, either specify it in the config or set it with the -t option"
> -    exit 1
> -fi
> -
>  if test ! "$BOOT_CMD"
>  then
>      BOOT_CMD="booti"
> @@ -1543,6 +1570,11 @@ then
>  elif test "$LINUX"
>  then
>      os="linux"
> +    if test ! "$LOAD_CMD"
> +    then
> +        echo "LOAD_CMD not set, either specify it in the config or set it with the -t option"
> +        exit 1
> +    fi
>      linux_config
>  else
>      echo "Neither a Xen or Linux kernel is specified, exiting"
> @@ -1691,7 +1723,7 @@ fi
>  
>  check_file_type $DEVICE_TREE "Device Tree Blob"
>  device_tree_addr=$memaddr
> -load_file $DEVICE_TREE "host_fdt"
> +load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
>  bitstream_load_and_config  # bitstream is loaded last but used first
>  device_tree_editing $device_tree_addr
>  
> -- 
> 2.25.1
> 


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Date: Tue, 12 Aug 2025 16:10:00 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Ayan Kumar Halder 
cc: xen-devel@lists.xenproject.org, sstabellini@kernel.org, 
    michal.orzel@amd.com, andrei.cherechesu@nxp.com, dmukhin@ford.com
Subject: Re: [ImageBuilder v2] Make DEVICE_TREE optional parameter
In-Reply-To: <20250812173350.2612682-1-ayan.kumar.halder@amd.com>
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On Tue, 12 Aug 2025, Ayan Kumar Halder wrote:
> There are systems where device tree binary is passed by the U-Boot as
> $fdtcontroladdr. In such cases, no external device tree binary is provided
> during uboot script generation.
> 
> This is an enhancement on top of the following commit:-
> uboot-script-gen: Dynamically compute addr and size when loading bina…
> 
> When DEVICE_TREE is not present, user should provide '-s' as the addresses and
> sizes should be computed dynamically from U-Boot.
> 
> Also, fixed uboot-script-gen to set host_kernel_addr when BOOT_CMD="none" and
> '-s' is not used.
> 
> Signed-off-by: Ayan Kumar Halder 

Reviewed-by: Stefano Stabellini 


> ---
> This patch should be applied after the previous patch.
> "[ImageBuilder v2] Add config option to use separate load commands for..."
> 
> Changes from :-
> 
> v1 :- 1. Check that user provides '-s' when DEVICE_TREE is not set, instead of
> setting CALC silently.
> 
> 2. Set 'host_fdt_addr' to '\${fdtcontroladdr}' when DEVICE_TREE is not set.
> 
> 3. Add a fix for BOOT_CMD="none".
>  
>  README.md                |  5 ++++-
>  scripts/uboot-script-gen | 29 +++++++++++++++++++++++------
>  2 files changed, 27 insertions(+), 7 deletions(-)
> 
> diff --git a/README.md b/README.md
> index 59919df..fc448e0 100644
> --- a/README.md
> +++ b/README.md
> @@ -92,7 +92,10 @@ Where:
>    DTB are stored in 'host_kernel_addr' and 'host_fdt_addr' u-boot
>    env variables respectively, to be used manually when booting.
>  
> -- DEVICE_TREE specifies the DTB file to load.
> +- DEVICE_TREE specifies the DTB file to load. If not set, then $fdtcontroladdr
> +  is used as the address of the DTB loaded by u-boot. If user does not set this
> +  option, then '-s' should be provided to ensure that addresses and sizes are
> +  calculated dynamically by uboot.
>  
>  - XEN specifies the Xen hypervisor binary to load. Note that it has to
>    be a regular Xen binary, not a u-boot binary.
> diff --git a/scripts/uboot-script-gen b/scripts/uboot-script-gen
> index 656de72..be61fc4 100755
> --- a/scripts/uboot-script-gen
> +++ b/scripts/uboot-script-gen
> @@ -591,7 +591,7 @@ function device_tree_editing()
>  
>  function fill_reserved_spaces_from_dtb()
>  {
> -    if [ ! -f $DEVICE_TREE ]
> +    if test ! -f $DEVICE_TREE || test -z "$DEVICE_TREE"
>      then
>          if test "$CALC"; then
>              return
> @@ -1674,6 +1674,16 @@ fi
>  
>  rm -f $UBOOT_SOURCE $UBOOT_SCRIPT
>  
> +if test -z "$DEVICE_TREE"
> +then
> +    if test -z "$CALC"
> +    then
> +       echo "DEVICE_TREE is unset and -s is not specified"
> +       exit 1
> +    fi
> +    echo "setenv host_fdt_addr \${fdtcontroladdr}" >> $UBOOT_SOURCE
> +fi
> +
>  if test "$FIT"
>  then
>      echo 'fit_addr=$fileaddr' >>  $UBOOT_SOURCE
> @@ -1721,9 +1731,13 @@ then
>      done
>  fi
>  
> -check_file_type $DEVICE_TREE "Device Tree Blob"
> -device_tree_addr=$memaddr
> -load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
> +if test "$DEVICE_TREE"
> +then
> +    check_file_type $DEVICE_TREE "Device Tree Blob"
> +    device_tree_addr=$memaddr
> +    load_file $DEVICE_TREE "host_fdt" "$XEN_LOAD"
> +fi
> +
>  bitstream_load_and_config  # bitstream is loaded last but used first
>  device_tree_editing $device_tree_addr
>  
> @@ -1751,8 +1765,11 @@ then
>      fi
>  else
>      # skip boot command but store load addresses to be used later
> -    echo "setenv host_kernel_addr $kernel_addr" >> $UBOOT_SOURCE
> -    echo "setenv host_fdt_addr $device_tree_addr" >> $UBOOT_SOURCE
> +    if test -z "$CALC"
> +    then
> +        echo "setenv host_kernel_addr $kernel_addr" >> $UBOOT_SOURCE
> +        echo "setenv host_fdt_addr $device_tree_addr" >> $UBOOT_SOURCE
> +    fi
>  fi
>  
>  if test "$FIT"
> -- 
> 2.25.1
> 
--8323329-1638558391-1755040203=:2883419--


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Date: Tue, 12 Aug 2025 18:55:15 -0500
From: Aaron Rainbolt 
To: Daniel Kiper 
Cc: grub-devel@gnu.org, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 2/2] kern/xen: Add Xen command line parsing
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On Tue, 12 Aug 2025 19:02:11 +0200
Daniel Kiper  wrote:

> On Mon, Aug 04, 2025 at 11:50:09PM -0500, Aaron Rainbolt wrote:
> > Xen traditionally allows customizing guest behavior by passing
> > arguments to the VM kernel via the kernel command line. This is no
> > longer possible when using GRUB with Xen, as the kernel command
> > line is decided by the GRUB configuration file within the guest,
> > not data passed to the guest by Xen.
> >
> > To work around this limitation, enable GRUB to parse a command line
> > passed to it by Xen, and expose data from the command line to the
> > GRUB configuration as environment variables. These variables can be
> > used in the GRUB configuration for any desired purpose, such as
> > extending the kernel command line passed to the guest. The command
> > line format is inspired by the Linux kernel's command line format.
> >
> > To reduce the risk of misuse, abuse, or accidents in production, the
> > command line will only be parsed if it consists entirely of 7-bit
> > ASCII characters, only alphabetical characters and underscores are
> > permitted in variable names, and all variable names must start with
> > the string "xen_grub_env_". This also allows room for expanding the
> > command line arguments accepted by GRUB in the future, should other
> > arguments end up becoming desirable in the future.
> >
> > Signed-off-by: Aaron Rainbolt 
> > ---
> >  docs/grub.texi                |  51 +++++
> >  grub-core/Makefile.core.def   |   2 +
> >  grub-core/kern/i386/xen/pvh.c |  23 +++
> >  grub-core/kern/xen/cmdline.c  | 376
> > ++++++++++++++++++++++++++++++++++ grub-core/kern/xen/init.c     |
> >  2 + include/grub/xen.h            |   2 +
> >  6 files changed, 456 insertions(+)
> >  create mode 100644 grub-core/kern/xen/cmdline.c
> >
> > diff --git a/docs/grub.texi b/docs/grub.texi
> > index 34b3484..b58cf98 100644
> > --- a/docs/grub.texi
> > +++ b/docs/grub.texi
> > @@ -3271,6 +3271,7 @@ GRUB.  Others may be used freely in GRUB
> > configuration files. @menu
> >  * Special environment variables::
> >  * Environment block::
> > +* Passing environment variables through Xen::
> >  @end menu
> >
> >
> > @@ -3871,6 +3872,56 @@ using BIOS or EFI functions (no ATA, USB or
> > IEEE1275). @command{grub-mkconfig} uses this facility to implement
> >  @samp{GRUB_SAVEDEFAULT} (@pxref{Simple configuration}).
> >
> > +@node Passing environment variables through Xen
> > +@section Passing environment variables through Xen
> > +
> > +If you are using a GRUB image as the kernel for a PV or PVH Xen
> > virtual +machine, you can pass environment variables from Xen's
> > dom0 to the VM through +the Xen-provided kernel command line. When
> > combined with a properly configured +guest, this can be used to
> > customize the guest's behavior on bootup via the +VM's Xen
> > configuration file. +
> > +GRUB will parse the kernel command line passed to it by Xen during
> > bootup. +The command line will be split into space-delimited words.
> > Single and +double quotes may be used to quote words or portions of
> > words that contain +spaces. Single quotes will be considered part
> > of a word if inside double +quotes, and vice versa. Arbitrary
> > characters may be backslash-escaped to make +them a literal
> > component of a word rather than being parsed as quotes or word
> > +separators. The command line must consist entirely of printable
> > 7-bit ASCII +characters and spaces. If a non-printing ASCII
> > character is found anywhere in +the command line, the entire
> > command line will be ignored by GRUB. + +Each word should be a
> > variable assignment in the format ``variable'' or
> > +``variable=3Dvalue''. Variable names must contain only the
> > characters A-Z, a-z, +and underscore (``_''). Variable names must
> > begin with the string +``xen_grub_env_''. Variable values can
> > contain arbitrary printable 7-bit +ASCII characters and space. If
> > any variable contains an illegal name, that +variable will be
> > ignored. + +If a variable name and value are both specified, the
> > variable will be set to +the specified value. If only a variable
> > name is specified, the variable's +value will be set to ``1''.
> > +
> > +The following is a simple example of how to use this functionality
> > to append +arbitrary variables to a guest's kernel command line:
> > +
> > +@example
> > +# In the Xen configuration file for the guest
> > +name =3D "linux_vm"
> > +type =3D "pvh"
> > +kernel =3D "/path/to/grub-i386-xen_pvh.bin"
> > +extra =3D "xen_grub_env_linux_append=3D'loglevel=3D3'"
> > +memory =3D 1024
> > +disk =3D [ "file:/srv/vms/linux_vm.img,sda,w" ]
> > +
> > +# In the guest's GRUB configuration file
> > +menuentry "Linux VM with dom0-specified kernel parameters" @{
> > +    search --set=3Droot --label linux_vm --hint hd0,msdos1
> > +    linux /boot/vmlinuz root=3DLABEL=3Dlinux_vm
> > $@{xen_grub_env_linux_append@}
> > +    initrd /boot/initrd.img
> > +@}
> > +@end example
> > +
> >  @node Modules
> >  @chapter Modules
> >
> > diff --git a/grub-core/Makefile.core.def
> > b/grub-core/Makefile.core.def index b3f7119..df0f266 100644
> > --- a/grub-core/Makefile.core.def
> > +++ b/grub-core/Makefile.core.def
> > @@ -248,6 +248,7 @@ kernel =3D {
> >    xen =3D term/xen/console.c;
> >    xen =3D disk/xen/xendisk.c;
> >    xen =3D commands/boot.c;
> > +  xen =3D kern/xen/cmdline.c;
> >
> >    i386_xen_pvh =3D commands/boot.c;
> >    i386_xen_pvh =3D disk/xen/xendisk.c;
> > @@ -255,6 +256,7 @@ kernel =3D {
> >    i386_xen_pvh =3D kern/i386/xen/tsc.c;
> >    i386_xen_pvh =3D kern/i386/xen/pvh.c;
> >    i386_xen_pvh =3D kern/xen/init.c;
> > +  i386_xen_pvh =3D kern/xen/cmdline.c;
> >    i386_xen_pvh =3D term/xen/console.c;
> >
> >    ia64_efi =3D kern/ia64/efi/startup.S;
> > diff --git a/grub-core/kern/i386/xen/pvh.c
> > b/grub-core/kern/i386/xen/pvh.c index 91fbca8..a8988d2 100644
> > --- a/grub-core/kern/i386/xen/pvh.c
> > +++ b/grub-core/kern/i386/xen/pvh.c
> > @@ -321,6 +321,8 @@ void
> >  grub_xen_setup_pvh (void)
> >  {
> >    grub_addr_t par;
> > +  const char *xen_cmdline;
> > +  int i;
> >
> >    grub_xen_cpuid_base ();
> >    grub_xen_setup_hypercall_page ();
> > @@ -352,6 +354,27 @@ grub_xen_setup_pvh (void)
> >    grub_xen_mm_init_regions ();
> >
> >    grub_rsdp_addr =3D pvh_start_info->rsdp_paddr;
> > +
> > +  xen_cmdline =3D (const char *) pvh_start_info->cmdline_paddr;
> > +  for (i =3D 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++)
> > +    {
> > +      if (xen_cmdline[i] =3D=3D '\0') =20
>=20
> This code still does not make a lot of sense for me. You have NUL
> check in grub_parse_xen_cmdline(). So, you duplicate the check here...
>=20
> I would just fire grub_strncpy() here and forget...

I guess it depends on how you view grub_xen_start_page_addr->cmd_line's
semantics. In my mind, cmd_line is a NUL-terminated string, always. If
you boot in PV mode, Xen ensures it's a NUL-terminated string, so it's
reasonable for code in GRUB to assume it will be one. If you boot in
PVH mode, it starts out initialized to all zeros which is technically a
NUL-terminated string, and the code that exists here ensures that if we
copy the kernel command line to cmd_line, it will still be a
NUL-terminated string. If we use a "bare" grub_strncpy() here, then if
someone passes a kernel command line larger than
GRUB_XEN_MAX_GUEST_CMDLINE - 1, cmd_line will end up not being
NUL-terminated anymore, and any code added to GRUB in the future that
assumes it is a NUL-terminated string may buffer overflow.

One could argue "let's keep the NUL check here and remove it from
grub_parse_xen_cmdline()", but that doesn't work either because we only
get to control the contents of cmd_line if we boot in PVH mode. If
instead we boot in PV mode, cmd_line is initialized by Xen itself. GRUB
receives a pre-populated and ready-to-use start_info struct directly
from the hypervisor in this scenario. Xen is supposed to ensure that
start_info is always NUL-terminated, but if there's ever a bug in Xen
that breaks that assumption, that could result in bad things happening,
the same as if we didn't do the NUL check in grub_xen_setup_pvh(). Now
of course there's nothing we can do about Xen possibly being buggy (if
it gives us a GRUB_XEN_MAX_GUEST_CMDLINE-long buffer with no NUL
terminator, too bad), but we can at least make sure that we're ready
for that eventuality. That's why I like having both NUL checks - we're
ready for if Xen does things wrong, and any future code that isn't
ready for that eventuality will still work if things go wrong, at least
in PVH mode.

(Arguably any new code that depends on cmd_line *should* check it for a
NUL terminator. But I don't want to assume that all new code *will* do
so.)

> > +        {
> > +          grub_strncpy ((char *)
> > grub_xen_start_page_addr->cmd_line,
> > +			(char *) pvh_start_info->cmdline_paddr,
> > +			GRUB_XEN_MAX_GUEST_CMDLINE);
> > +
> > +          if
> > (grub_xen_start_page_addr->cmd_line[GRUB_XEN_MAX_GUEST_CMDLINE - 1]
> > !=3D '\0') =20
>=20
> If you convince me this code is still needed then I am afraid that
> this is not what you meant here...

grub_strncpy doesn't just NUL-terminate the command line, it also fills
the entire remainder of the buffer with NUL characters. Therefore if
grub_strncpy NUL-terminated the copied string, the last character of
the buffer will always be NUL. This is a redundant check since the code
above goes to great lengths to avoid ever putting anything
non-NUL-terminated into the buffer, but I was under the impression you
wanted the check added just in case. I'm happy to remove it if it's not
desirable.

> > +            {
> > +              grub_error (GRUB_ERR_BUG,
> > +			  "Xen command line is not
> > NUL-terminated");
> > +              grub_print_error ();
> > +              grub_exit (); =20
>=20
> grub_fatal() and you are done...

Will change.

> > +            }
> > +
> > +          break;
> > +        }
> > +    }
> >  }
> >
> >  grub_err_t
> > diff --git a/grub-core/kern/xen/cmdline.c
> > b/grub-core/kern/xen/cmdline.c new file mode 100644
> > index 0000000..46a9998
> > --- /dev/null
> > +++ b/grub-core/kern/xen/cmdline.c
> > @@ -0,0 +1,376 @@
> > +/*
> > + *  GRUB  --  GRand Unified Bootloader
> > + *  Copyright (C) 2025  Free Software Foundation, Inc.
> > + *
> > + *  GRUB is free software: you can redistribute it and/or modify
> > + *  it under the terms of the GNU General Public License as
> > published by
> > + *  the Free Software Foundation, either version 3 of the License,
> > or
> > + *  (at your option) any later version.
> > + *
> > + *  GRUB is distributed in the hope that it will be useful,
> > + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + *  GNU General Public License for more details.
> > + *
> > + *  You should have received a copy of the GNU General Public
> > License
> > + *  along with GRUB.  If not, see .
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +enum splitter_state
> > +{
> > +  SPLITTER_HIT_BACKSLASH =3D 0x1,
> > +  SPLITTER_IN_SINGLE_QUOTES =3D 0x2,
> > +  SPLITTER_IN_DOUBLE_QUOTES =3D 0x4,
> > +};
> > +typedef enum splitter_state splitter_state_t;
> > +
> > +/*
> > + * The initial size of the current_word buffer. The buffer may be
> > resized as
> > + * needed.
> > + */
> > +#define PARSER_BASE_WORD_SIZE 32
> > +
> > +struct parser_state
> > +{
> > +  grub_size_t word_list_len; =20
>=20
> s/word_list_len/words_count/
>=20
> And I would put it behind word_list...

Will change.

> > +  char **word_list; =20
>=20
> s/word_list/words/

Will change.

> > +  grub_size_t current_word_len;
> > +  grub_size_t current_word_pos;
> > +  char *current_word;
> > +};
> > +typedef struct parser_state parser_state_t;
> > +
> > +static bool =20
>=20
> s/bool/grub_err_t/

Will change.

> > +append_char_to_word (parser_state_t *s, char c, bool allow_null)
> > +{
> > +  /*
> > +   * We ban any chars that are not in the ASCII printable range. If
> > +   * allow_null =3D=3D true, we make an exception for NUL. (This is
> > needed so that
> > +   * append_word_to_list can add a NUL terminator to the word).
> > +   */
> > +  if (grub_isprint (c) =3D=3D false && allow_null =3D=3D false) =20
>=20
> grub_isprint() et consortes return int instead of bool. So, it should
> be "!grub_isprint(c)" here...

Argh, right, because I can't assume that false =3D=3D 0 and true =3D=3D
non-zero. Will fix.

> > +    return false;
> > +  else if (allow_null =3D=3D true && c !=3D '\0')
> > +    return false;
> > +
> > +  if (s->current_word_pos =3D=3D s->current_word_len)
> > +    {
> > +      s->current_word =3D grub_realloc (s->current_word,
> > s->current_word_len *=3D 2);
> > +      if (s->current_word =3D=3D NULL)
> > +        {
> > +          s->current_word_len /=3D 2;
> > +          return false;
> > +        }
> > +    }
> > +
> > +  s->current_word[s->current_word_pos++] =3D c;
> > +  return true;
> > +}
> > +
> > +static bool =20
>=20
> s/bool/grub_err_t/

Will change.

> > +append_word_to_list (parser_state_t *s)
> > +{
> > +  /* No-op on empty words. */
> > +  if (s->current_word_pos =3D=3D 0)
> > +    return true;
> > +
> > +  if (append_char_to_word (s, '\0', true) =3D=3D false)
> > +    {
> > +      grub_error (GRUB_ERR_BUG,
> > +		  "couldn't append NUL terminator to word during
> > Xen cmdline parsing");
> > +      grub_print_error ();
> > +      grub_exit (); =20
>=20
> grub_fatal()

Will change.

> > +    }
> > +
> > +  s->current_word_len =3D grub_strlen (s->current_word) + 1;
> > +  s->current_word =3D grub_realloc (s->current_word,
> > s->current_word_len);
> > +  if (s->current_word =3D=3D NULL)
> > +    return false; =20
>=20
> return grub_errno;

Will change.

> > +  s->word_list =3D grub_realloc (s->word_list, ++s->word_list_len *
> > sizeof (char *));
> > +  if (s->word_list =3D=3D NULL)
> > +    return false; =20
>=20
> return grub_errno;
>=20
> ...
>=20
> I think many (related) functions in this code returning bool should
> really return grub_err_t...

That makes sense to me, will change where appropriate.

> > +  s->word_list[s->word_list_len - 1] =3D s->current_word;
> > +
> > +  s->current_word_len =3D PARSER_BASE_WORD_SIZE;
> > +  s->current_word_pos =3D 0;
> > +  s->current_word =3D grub_malloc (s->current_word_len);
> > +  if (s->current_word =3D=3D NULL)
> > +    return false;
> > +
> > +  return true;
> > +}
> > +
> > +static bool =20
>=20
> But this bool makes sense...

OK.

> > +is_key_safe (char *key, grub_size_t len)
> > +{
> > +  grub_size_t i;
> > +
> > +  for (i =3D 0; i < len; i++)
> > +    {
> > +      if (! (grub_isalpha (key[i]) || key[i] =3D=3D '_')) =20
>=20
> Please drop space after "!"...

Will change.

> > +        return false;
> > +    } =20
>=20
> You can drop curly braces from here...

Will change.

(I initially kept this written the way it was though because the GNU
coding standards seemed to indicate I should keep the braces. "When
you have an if-else statement nested in another if statement, always
put braces around the if-else." [1] This isn't a nested if, but it's an
if within a for which is very similar.)

Is there any recommended coding style documentation I should be looking
at other than the GNU coding standards and the GRUB coding style
guidelines? It seems I'm making an awful lot of style mistakes and
would like to avoid that going forward.

> > +
> > +  return true;
> > +}
> > +
> > +void
> > +grub_parse_xen_cmdline (void)
> > +{
> > +  parser_state_t *s =3D NULL; =20
>=20
> parser_state_t ps =3D {0};
>=20
> ... and you do not need grub_malloc(s) and stuff any longer below...
>=20
> And I would put it next to splitter_state...

Will change.

> > +  const char *cmdline =3D (const char *)
> > grub_xen_start_page_addr->cmd_line;
> > +  grub_size_t cmdline_len;
> > +  bool cmdline_valid =3D false;
> > +  char **param_keys =3D NULL;
> > +  char **param_vals =3D NULL;
> > +  grub_size_t param_dict_len =3D 0;
> > +  grub_size_t param_dict_pos =3D 0;
> > +  splitter_state_t splitter_state =3D 0; =20
>=20
> You nicely define an enum and then assign plain number. Sigh...
> I think you should define SPLITTER_NORMAL or something similar
> as well...
>
> And s/splitter_state/ss/...

Will implement both changes.

> > +  char current_char =3D '\0';
> > +  grub_size_t i =3D 0;
> > +
> > +  s =3D grub_malloc (sizeof (parser_state_t));
> > +  if (s =3D=3D NULL)
> > +    goto cleanup_final;
> > +
> > +  /*
> > +   * The following algorithm is used to parse the Xen command line:
> > +   *
> > +   * - The command line is split into space-separated words.
> > +   *   - Single and double quotes may be used to suppress the
> > splitting
> > +   *     behavior of spaces.
> > +   *   - Double quotes are appended to the current word verbatim
> > if they
> > +   *     appear within a single-quoted string portion, and vice
> > versa.
> > +   *   - Backslashes may be used to cause the next character to be
> > +   *     appended to the current word verbatim. This is only
> > useful when
> > +   *     used to escape quotes, spaces, and backslashes, but for
> > simplicity
> > +   *     we allow backslash-escaping anything.
> > +   * - After splitting the command line into words, each word is
> > checked to
> > +   *   see if it contains an equals sign.
> > +   *   - If it does, it is split on the equals sign into a
> > key-value pair. The
> > +   *     key is then treated as an variable name, and the value is
> > treated as
> > +   *     the variable's value.
> > +   *   - If it does not, the entire word is treated as a variable
> > name. The
> > +   *     variable's value is implicitly considered to be `1`.
> > +   * - All variables detected on the command line are checked to
> > see if their
> > +   *   names begin with the string `xen_grub_env_`. Variables that
> > do not pass
> > +   *   this check are discarded, variables that do pass this check
> > are
> > +   *   exported so they are available to the GRUB configuration.
> > +   */
> > +
> > +  s->current_word_len =3D PARSER_BASE_WORD_SIZE;
> > +  s->current_word =3D grub_malloc (s->current_word_len);
> > +  if (s->current_word =3D=3D NULL)
> > +    goto cleanup_main;
> > +
> > +  for (i =3D 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++)
> > +    {
> > +      if (cmdline[i] =3D=3D '\0')
> > +        {
> > +          cmdline_valid =3D true;
> > +          break;
> > +        }
> > +    }
> > +
> > +  if (cmdline_valid =3D=3D false)
> > +    {
> > +      grub_error (GRUB_ERR_BAD_ARGUMENT,
> > +		  "command line from Xen is not NUL-terminated");
> > +      grub_print_error (); =20
>=20
> grub_fatal()?

That would probably be a bad idea here. We use (or, at least, will use)
grub_fatal() in grub_xen_setup_pvh() because if grub_strncpy() doesn't
NUL-terminate the string it copies, it indicates a bug in GRUB (either
in grub_strncpy, or more likely in the nearby NUL-checking code). On
the other hand, cmdline_valid may equal false if we boot in PV mode and
Xen incorrectly hands us a non-NUL-terminated string. That's bad and
prevents us from parsing the command line safely, but I'd argue it
shouldn't entirely block boot. (Then again, maybe if it does block
boot, that will make this kind of theoretical Xen bug be much more
noticeable and help it get fixed quicker. If you'd prefer that we bail
out entirely here, I'm happy to change it.)

> > +      goto cleanup_main;
> > +    }
> > +
> > +  cmdline_len =3D grub_strlen (cmdline);
> > +  for (i =3D 0; i < cmdline_len; i++)
> > +    {
> > +      current_char =3D cmdline[i];
> > +
> > +      /*
> > +       * If the previous character was a backslash, append the
> > current
> > +       * character to the word verbatim
> > +       */
> > +      if (splitter_state & SPLITTER_HIT_BACKSLASH)
> > +        {
> > +          splitter_state &=3D ~SPLITTER_HIT_BACKSLASH;
> > +          if (append_char_to_word (s, current_char, false) =3D=3D
> > false)
> > +            goto cleanup_main;
> > +          continue;
> > +        }
> > +
> > +      switch (current_char)
> > +        {
> > +        case '\\':
> > +          /* Backslashes escape arbitrary characters. */
> > +          splitter_state |=3D SPLITTER_HIT_BACKSLASH;
> > +          continue;
> > +
> > +        case '\'':
> > +          /*
> > +           * Single quotes suppress word splitting and double
> > quoting until
> > +           * the next single quote is encountered.
> > +           */
> > +          if (splitter_state & SPLITTER_IN_DOUBLE_QUOTES)
> > +            {
> > +              if (append_char_to_word (s, current_char, false) =3D=3D
> > false)
> > +                goto cleanup_main;
> > +              continue;
> > +            }
> > +
> > +          splitter_state ^=3D SPLITTER_IN_SINGLE_QUOTES;
> > +          continue;
> > +
> > +        case '"':
> > +          /*
> > +           * Double quotes suppress word splitting and single
> > quoting until
> > +           * the next double quote is encountered.
> > +           */
> > +          if (splitter_state & SPLITTER_IN_SINGLE_QUOTES)
> > +            {
> > +              if (append_char_to_word (s, current_char, false) =3D=3D
> > false)
> > +                goto cleanup_main;
> > +              continue;
> > +            }
> > +
> > +          splitter_state ^=3D SPLITTER_IN_DOUBLE_QUOTES;
> > +          continue;
> > +
> > +        case ' ':
> > +          /* Spaces separate words in the command line from each
> > other. */
> > +          if (splitter_state & SPLITTER_IN_SINGLE_QUOTES ||
> > +              splitter_state & SPLITTER_IN_DOUBLE_QUOTES)
> > +            {
> > +              if (append_char_to_word (s, current_char, false) =3D=3D
> > false)
> > +                goto cleanup_main;
> > +              continue;
> > +            }
> > +
> > +          if (append_word_to_list (s) =3D=3D false)
> > +            goto cleanup_main; =20
>=20
> I think this is not fully correct. You should not run
> append_word_to_list() until the closing quote. So, here you should
> have "else" for the first "if", i.e., "if (splitter_state & ..." and
> call append_word_to_list() for closing \" and \' above.

What closing quote? If we're in quotes, the `if (splitter_state &...`
block will run. That block runs `continue`, restarting the loop before
we get to the `append_word_to_list (s)` call. If we hit a closing
quote, either the `case '\''` or the `case '"'` block will be
triggered, changing the splitter's state so that it knows it's no
longer within a quote block, and then the next space (or the end of the
string) will cause `append_word_to_list()` to be called, adding the
quoted word to the list. Even if this `continue` changes to a `break`
like suggested below, the logic and control flow will remain the same.

Calling `append_word_to_list()` for closing quotes would break the
splitter. I'm trying to implement splitting behavior similar to Bash or
GRUB's configuration language, both of which parse
`xen_grub_env_var=3D"abc def"ghi` into the variable `xen_grub_env_var`
with the value `abc defghi`. If we split on closing quotes too, the
input above will be parsed into two words, `xen_grub_env_var=3Dabc def`
and an extra word `ghi`, resulting in the environment variable
`xen_grub_env_var` being set to `abc def` and the `ghi` being lost
entirely. One could argue that this is reasonable behavior, but it
isn't consistent with the other splitting behavior in GRUB.

> > +          continue;
> > +        }
> > +
> > +      if (append_char_to_word (s, current_char, false) =3D=3D false)
> > +        goto cleanup_main; =20
>=20
> This should be part of "default:" for the switch above... Even if it
> works now...
>=20
> Then many "continue" should be converted to more natural "break"...

Good point, will change.

> > +    }
> > +
> > +  if (append_word_to_list (s) =3D=3D false)
> > +    goto cleanup_main;
> > +
> > +  param_keys =3D grub_malloc (s->word_list_len * sizeof (char *));
> > +  if (param_keys =3D=3D NULL)
> > +    goto cleanup_main;
> > +  param_vals =3D grub_malloc (s->word_list_len * sizeof (char *));
> > +  if (param_vals =3D=3D NULL)
> > +    goto cleanup_main;
> > +
> > +  for (i =3D 0; i < s->word_list_len; i++)
> > +    {
> > +      char *current_word_eq_ptr; =20
>=20
> s/current_word_eq_ptr/eq_pos/

Will change.

> > +      s->current_word =3D s->word_list[i];
> > +      s->current_word_len =3D grub_strlen (s->current_word) + 1;
> > +      current_word_eq_ptr =3D grub_strchr (s->current_word, '=3D');
> > +
> > +      if (current_word_eq_ptr !=3D NULL)
> > +        {
> > +          /*
> > +           * Both pre_eq_len and post_eq_len represent substring
> > lengths
> > +           * without a NUL terminator.
> > +           */
> > +          grub_size_t pre_eq_len =3D (grub_size_t)
> > (current_word_eq_ptr - s->current_word);
> > +          /*
> > +           * s->current_word_len includes the NUL terminator, so
> > we subtract
> > +           * one to get rid of the terminator, and one more to get
> > rid of the
> > +           * equals sign.
> > +           */
> > +          grub_size_t post_eq_len =3D (s->current_word_len - 2) -
> > pre_eq_len; +
> > +          if (is_key_safe (s->current_word, pre_eq_len) =3D=3D true)
> > +            {
> > +              param_dict_pos =3D param_dict_len++;
> > +              param_keys[param_dict_pos] =3D grub_malloc (pre_eq_len
> > + 1);
> > +              if (param_keys =3D=3D NULL)
> > +                goto cleanup_main;
> > +              param_vals[param_dict_pos] =3D grub_malloc
> > (post_eq_len + 1);
> > +              if (param_vals =3D=3D NULL)
> > +                goto cleanup_main;
> > +
> > +              grub_strncpy (param_keys[param_dict_pos],
> > s->current_word, pre_eq_len);
> > +              grub_strncpy (param_vals[param_dict_pos],
> > +			    s->current_word + pre_eq_len + 1,
> > post_eq_len);
> > +              param_keys[param_dict_pos][pre_eq_len] =3D '\0';
> > +              param_vals[param_dict_pos][post_eq_len] =3D '\0';
> > +            }
> > +        }
> > +      else =20
>=20
> else if (is_key_safe (s->current_word, s->current_word_len - 1) =3D=3D
> true)
>=20
> ... and you can drop an extra indention...

Will change.

> > +        {
> > +          if (is_key_safe (s->current_word, s->current_word_len -
> > 1) =3D=3D true)
> > +            {
> > +              param_dict_pos =3D param_dict_len++;
> > +              param_keys[param_dict_pos] =3D grub_malloc
> > (s->current_word_len);
> > +              if (param_keys =3D=3D NULL)
> > +                goto cleanup_main;
> > +              param_vals[param_dict_pos] =3D grub_malloc (2);
> > +              if (param_vals =3D=3D NULL)
> > +                goto cleanup_main;
> > +
> > +              grub_strncpy (param_keys[param_dict_pos],
> > s->current_word,
> > +			    s->current_word_len);
> > +              if (param_keys[param_dict_pos][s->current_word_len -
> > 1] !=3D '\0' )
> > +                {
> > +                  grub_error (GRUB_ERR_BUG,
> > +			      "NUL terminator missing from key
> > during Xen cmdline parsing");
> > +                  grub_print_error ();
> > +                  grub_exit (); =20
>=20
> grub_fatal()

Will change.

> > +                }
> > +              grub_strcpy (param_vals[param_dict_pos], "1");
> > +            }
> > +        }
> > +    } =20
>=20
> Daniel


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Date: Wed, 13 Aug 2025 04:53:53 +0200
From: =?ISO-8859-1?Q?Marek_Marczykowski-G=F3recki?= 
To: Andrew Cooper , Jan Beulich 
CC: xen-devel 
Subject: Re: S3 regression related to XSA-471 patches
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On August 11, 2025 3:16:46 PM GMT+02:00, Andrew Cooper  wrote:
>On 07/08/2025 6:29 pm, Marek Marczykowski-G=C3=B3recki wrote:
>> On Wed, Aug 06, 2025 at 12:46:36PM +0200, Marek Marczykowski-G=C3=B3rec=
ki wrote:
>>> On Wed, Aug 06, 2025 at 12:36:56PM +0200, Jan Beulich wrote:
>>>> On 06=2E08=2E2025 12:23, Marek Marczykowski-G=C3=B3recki wrote:
>>>>> We've got several reports that S3 reliability recently regressed=2E =
We
>>>>> identified it's definitely related to XSA-471 patches, and bisection
>>>>> points at "x86/idle: Remove broken MWAIT implementation"=2E I don't =
have
>>>>> reliable reproduction steps, so I'm not 100% sure if it's really thi=
s
>>>>> patch, or maybe an earlier one - but it's definitely already broken =
at
>>>>> this point in the series=2E Most reports are about Xen 4=2E17 (as th=
at's
>>>>> what stable Qubes OS version currently use), but I think I've seen
>>>>> somebody reporting the issue on 4=2E19 too (but I don't have clear
>>>>> evidence, especially if it's the same issue)=2E
>>>> At the time we've been discussing the explicit raising of TIMER_SOFTI=
RQ
>>>> in mwait_idle_with_hints() a lot=2E If it was now truly missing, that=
 imo
>>>> shouldn't cause problems only after resume, but then it may have cove=
red
>>>> for some omission during resume=2E As a far-fetched experiment, could=
 you
>>>> try putting that back (including the calculation of the "expires" loc=
al
>>>> variable)?
>>> Sure, I'll try=2E
>> It appears this fixes the issue, at least in ~10 attempts so far
>> (usually I could reproduce the issue after 2-3 attempts)=2E
>>
>
>Can you show the exact code which seems to have made this stable?

This patch: https://github=2Ecom/marmarek/qubes-vmm-xen/blob/7c9e9e312948c=
772d9a68090109964121c1d16fe/0001-DEBUG-S3=2Epatch

>
>We discussed this in the x86 maintainers meeting, and our best guess is
>a timer that's not torn down or recreated properly on S3, but this is
>largely speculation=2E
>
>~Andrew


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v6 18/19] xen/cpufreq: bypass governor-related para for
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Thread-Topic: [PATCH v6 18/19] xen/cpufreq: bypass governor-related para for
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Date: Wed, 13 Aug 2025 06:57:37 +0000
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Date: Wed, 13 Aug 2025 09:26:09 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
Cc: Andrew Cooper ,
	Jan Beulich ,
	xen-devel 
Subject: Re: S3 regression related to XSA-471 patches
Message-ID: 
References: 
 
 
 
 <4fb544d7-fede-46b8-950e-f9c4af1cb04f@citrix.com>
 
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On Wed, Aug 13, 2025 at 04:53:53AM +0200, Marek Marczykowski-Górecki wrote:
> 
> 
> On August 11, 2025 3:16:46 PM GMT+02:00, Andrew Cooper  wrote:
> >On 07/08/2025 6:29 pm, Marek Marczykowski-Górecki wrote:
> >> On Wed, Aug 06, 2025 at 12:46:36PM +0200, Marek Marczykowski-Górecki wrote:
> >>> On Wed, Aug 06, 2025 at 12:36:56PM +0200, Jan Beulich wrote:
> >>>> On 06.08.2025 12:23, Marek Marczykowski-Górecki wrote:
> >>>>> We've got several reports that S3 reliability recently regressed. We
> >>>>> identified it's definitely related to XSA-471 patches, and bisection
> >>>>> points at "x86/idle: Remove broken MWAIT implementation". I don't have
> >>>>> reliable reproduction steps, so I'm not 100% sure if it's really this
> >>>>> patch, or maybe an earlier one - but it's definitely already broken at
> >>>>> this point in the series. Most reports are about Xen 4.17 (as that's
> >>>>> what stable Qubes OS version currently use), but I think I've seen
> >>>>> somebody reporting the issue on 4.19 too (but I don't have clear
> >>>>> evidence, especially if it's the same issue).
> >>>> At the time we've been discussing the explicit raising of TIMER_SOFTIRQ
> >>>> in mwait_idle_with_hints() a lot. If it was now truly missing, that imo
> >>>> shouldn't cause problems only after resume, but then it may have covered
> >>>> for some omission during resume. As a far-fetched experiment, could you
> >>>> try putting that back (including the calculation of the "expires" local
> >>>> variable)?
> >>> Sure, I'll try.
> >> It appears this fixes the issue, at least in ~10 attempts so far
> >> (usually I could reproduce the issue after 2-3 attempts).
> >>
> >
> >Can you show the exact code which seems to have made this stable?
> 
> This patch: https://github.com/marmarek/qubes-vmm-xen/blob/7c9e9e312948c772d9a68090109964121c1d16fe/0001-DEBUG-S3.patch

Hello,

Can you test if the patch below in isolation makes any difference?

Thanks, Roger.
---
diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c
index 2ac162c997fe..27d672ad5dbb 100644
--- a/xen/arch/x86/acpi/power.c
+++ b/xen/arch/x86/acpi/power.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -310,6 +311,7 @@ static int enter_state(u32 state)
     thaw_domains();
     system_state = SYS_STATE_active;
     spin_unlock(&pm_lock);
+    raise_softirq(TIMER_SOFTIRQ);
     return error;
 }
 
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 0fd8bdba7067..9d66db861b74 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -65,7 +65,6 @@ static struct {
     unsigned int apic_lvt0;
     unsigned int apic_lvt1;
     unsigned int apic_lvterr;
-    unsigned int apic_tmict;
     unsigned int apic_tdcr;
     unsigned int apic_thmr;
 } apic_pm_state;
@@ -658,7 +657,6 @@ int lapic_suspend(void)
     apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
     apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
     apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
-    apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
     apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
     if (maxlvt >= 5)
         apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
@@ -718,7 +716,7 @@ int lapic_resume(void)
         apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
     apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
     apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
-    apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
+    apic_write(APIC_TMICT, 0);
     apic_write(APIC_ESR, 0);
     apic_read(APIC_ESR);
     apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);



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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH for-4.21?] x86: drop detection of ld supporting
 SORT_BY_INIT_PRIORITY()
To: Andrew Cooper , Jan Beulich
 ,
 "xen-devel@lists.xenproject.org" 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: <7a24d8c9-97c2-4721-9e38-600858b30119@suse.com>
 <75f5d54e-8ec1-42dd-8f4f-6023113203ee@citrix.com>
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From: Oleksii Kurochko 
In-Reply-To: <75f5d54e-8ec1-42dd-8f4f-6023113203ee@citrix.com>

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On 8/11/25 1:10 PM, Andrew Cooper wrote:
> On 11/08/2025 12:02 pm, Jan Beulich wrote:
>> GNU ld 2.25 supports this, and we already assume all lld versions do.
>>
>> Signed-off-by: Jan Beulich
> Acked-by: Andrew Cooper
>
>> ---
>> While past the submission deadline, this fits the toolchain baseline
>> update we did in this release cycle, so I'd like to ask that it be
>> considered to still permit this in.
> There's loads of cleanup still in the ticket I made and talked about at
> the start of 4.21.
>
> There are a view bits posted and still in need of pushing through, but I
> consider anything along these lines to be fair game in the short term.

Agree with that.

Release-Acked-By: Oleksii Kurochko

~ Oleksii

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    On 8/11/25 1:10 PM, Andrew Cooper
      wrote:
    
    
    
    
    
      
    On 11/08/2025 12:02 pm, Jan Beulich wrote:

    
      
    
        
    GNU ld 2.25 supports this, and we already assume all lld versions do.

Signed-off-by: Jan Beulich <jbeulich@suse.com>

    
      
    
      
    Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>


    
      
    
        
    ---
While past the submission deadline, this fits the toolchain baseline
update we did in this release cycle, so I'd like to ask that it be
considered to still permit this in.

    
      
    
      
    There's loads of cleanup still in the ticket I made and talked about at
the start of 4.21.

There are a view bits posted and still in need of pushing through, but I
consider anything along these lines to be fair game in the short term.
    
    
    
    
    Agree with that.

Release-Acked-By: Oleksii Kurochko <oleksii.kurochko@gmail.com>

~ Oleksii

    
  


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To: Nicola Vetrini ,
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CC: "sstabellini@kernel.org" ,
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Subject: Re: [XEN PATCH 2/2] Address violation of MISRA C Rule 13.1 involving
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Thread-Topic: [XEN PATCH 2/2] Address violation of MISRA C Rule 13.1 involving
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Date: Wed, 13 Aug 2025 07:41:23 +0000
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MIME-Version: 1.0
Date: Wed, 13 Aug 2025 09:46:15 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, sstabellini@kernel.org,
 consulting@bugseng.com, andrew.cooper3@citrix.com, jbeulich@suse.com, Doug
 Goldstein 
Subject: Re: [XEN PATCH 2/2] Address violation of MISRA C Rule 13.1 involving
 asm side effects.
In-Reply-To: <175d7b47-32bb-4b5d-a16b-7402bd823b15@epam.com>
References: <1283be3b76d76814af244bbca544f6a3b74a04de.1754689062.git.nicola.vetrini@bugseng.com>
 
 <175d7b47-32bb-4b5d-a16b-7402bd823b15@epam.com>
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On 2025-08-13 09:41, Dmytro Prokopchuk1 wrote:
> On 8/9/25 00:40, Nicola Vetrini wrote:
>> The rule states: "Initializer lists shall not contain persistent side 
>> effects".
>> The specific way in which the 'mrs' instruction is used does not lead 
>> to
>> visible side effects for the surrounding code.
>> 
>> Signed-off-by: Nicola Vetrini 
>> ---
>> Not yet tested on the Xen ECLAIR runner, as the syntax used in the 
>> deviation
>> is only supported after updating the runner.
>> 
>> What the tool is reporting is that due to the '=r' constraint and the
>> semantics of the instruction, there is the side effect of writing to 
>> '_r',
>> but this is not observable outside the stmt expr. The deviation ends 
>> up being
>> a bit too general for my taste, but the restriction on the actual 
>> istruction
>> should be enough to limit applicability to cases that are arguably 
>> safe in
>> practice.
>> 
>> An alternative approach would be represented by stating that side 
>> effects in
>> 'READ_SYSREG64' are safe, but this is not true in general.
>> ---
>>   automation/eclair_analysis/ECLAIR/deviations.ecl | 4 ++++
>>   1 file changed, 4 insertions(+)
>> 
>> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl 
>> b/automation/eclair_analysis/ECLAIR/deviations.ecl
>> index ec0cac797e5f..6b492e38505d 100644
>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>> @@ -437,6 +437,10 @@ write or not"
>>   # Series 13
>>   #
>> 
>> +-doc_begin="Consider the asm instruction to read an Arm system 
>> register to have no side effects."
>> +-asm_properties+={"asm(any())&&child(text, 
>> ast_field(value,^mrs\\s+%0.*$))", {no_side_effect}}
>> +-doc_end
>> +
>>   -doc_begin="All developers and reviewers can be safely assumed to be 
>> well aware
>>   of the short-circuit evaluation strategy of such logical operators."
>>   -config=MC3A2.R13.5,reports+={disapplied,"any()"}
> 
> I think it's worth to add example of macro expansion in the commit
> description or asm_properties doc:
> 
> uint64_t _r; asm volatile("mrs  %0, ""TPIDR_EL2" : "=r" (_r));
> 
> This uses the 'mrs' instruction to read from the TPIDR_EL2 register.
> While this read operation accesses a system register, reading itself
> doesn't cause any persistent side effects, as no program state is 
> modified.
> 

Definitely not in the -doc_begin, perhaps in deviations.rst, though in 
reality it is a single case this currently applies to. Reading the 
register is not the reason why this deviation was requested, but the 
write with the "=r" constraint on "_r", as that is the side effect the 
tool is pointing at.

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [PATCH 01/22] x86/msr: Rename MSR_INTERRUPT_SSP_TABLE to MSR_ISST
To: Jan Beulich 
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 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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 <9f13d1c5-8f92-4a73-8a67-f4b44b72fa50@suse.com>
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On 12/08/2025 9:06 am, Jan Beulich wrote:
> On 08.08.2025 22:22, Andrew Cooper wrote:
>> The name AMD chose is rather more concise.
>>
>> No functional change.
>>
>> Signed-off-by: Andrew Cooper 
> I'm okay with the (much) shorter name, so:
> Acked-by: Jan Beulich 

Thanks.

>
> But I can't make the connection to AMD: It's INTERRUPT_SST_TABLE (figure)
> or INTERRUPT_SSP_TABLE (text) there, afaics. And ISST_ADDR in yet further
> places.

ISST has a better association with IST than the long form, which is
ambiguous if turned into an initialism.  The ADDR suffix I dropped like
we do elsewhere.

But now you point it out, there is a confusing mix in AMD.  I'm pretty
sure SST is a plain typo, and I've fed this back.

I'll tweak the wording a little bit.

~Andrew


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From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: Roger Pau Monne ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	Stefano Stabellini 
Subject: [PATCH] x86/pvh: update "Host ACPI" support status
Date: Wed, 13 Aug 2025 11:32:20 +0200
Message-ID: <20250813093220.76030-1-roger.pau@citrix.com>
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For x86 PVH dom0 makes uses of the host ACPI tables, and hence the status
of Host ACPI entry should have been updated to reflect that PVH dom0 is now
supported, and Host ACPI support is not one of the caveats.

Fixes: ea1cb444c28c ('x86/pvh: declare PVH dom0 supported with caveats')
Signed-off-by: Roger Pau Monné 
---
 SUPPORT.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/SUPPORT.md b/SUPPORT.md
index 6a82a9218991..109b62835f99 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -70,7 +70,7 @@ For the Cortex A77 r0p0 - r1p0, see Errata 1508412.
 
 ### Host ACPI (via Domain 0)
 
-    Status, x86 PV: Supported
+    Status, x86: Supported
     Status, ARM: Experimental
 
 ### Host EFI Boot
-- 
2.49.0



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Subject: Re: [PATCH 03/22] x86/traps: Drop incorrect BUILD_BUG_ON() and
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To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 12/08/2025 9:11 am, Jan Beulich wrote:
> On 08.08.2025 22:22, Andrew Cooper wrote:
>> This was added erroneously by me.
>>
>> Hardware task switching does demand a TSS of at least 0x67 bytes, but that's
>> not relevant in 64bit, and not relevant for Xen since commit
>> 5d1181a5ea5e ("xen: Remove x86_32 build target.") in 2012.
>>
>> We already load a 0-length TSS in early_traps_init() demonstrating that it's
>> possible.
>>
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Jan Beulich 
>> CC: Roger Pau Monné 
>> ---
>>  xen/arch/x86/cpu/common.c | 2 --
>>  1 file changed, 2 deletions(-)
>>
>> diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
>> index f6ec5c9df522..cdc41248d4e9 100644
>> --- a/xen/arch/x86/cpu/common.c
>> +++ b/xen/arch/x86/cpu/common.c
>> @@ -936,8 +936,6 @@ void load_system_tables(void)
>>  		wrmsrl(MSR_ISST, (unsigned long)ist_ssp);
>>  	}
>>  
>> -	BUILD_BUG_ON(sizeof(*tss) <= 0x67); /* Mandated by the architecture. */
>> -
>>  	_set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
>>  			 sizeof(*tss) - 1, SYS_DESC_tss_avail);
>>  	if ( IS_ENABLED(CONFIG_PV32) )
> Well, the comment is wrong. Whether the BUILD_BUG_ON() itself is also wrong
> depends on our intentions with the structure. Don't we need it to be that
> size for everything (incl I/O bitmap) to work correctly elsewhere?

We don't use the IO bitmap.  We've talked about it a few times, but
never got it sorted.

Xen's TSS could be as short as 0x37 (covering IST3) and still work
correctly and safely (as there's no task switching).

A failure to read tss->iopb is the same as a failure to read the bitmap
itself.  In fact, it's probably marginally faster for users of
IOBMP_INVALID_OFFSET as it fails one step earlier.

~Andrew


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From: Dmytro Prokopchuk1 
To: Julien Grall , Jan Beulich , Nicola
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CC: Stefano Stabellini , Bertrand Marquis
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Subject: Re: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
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Subject: Re: [PATCH 04/22] x86/idt: Minor improvements to
 _update_gate_addr_lower()
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-5-andrew.cooper3@citrix.com>
 <44c9a7ba-8e01-41cc-8c93-32b022885439@suse.com>
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From: Andrew Cooper 
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In-Reply-To: <44c9a7ba-8e01-41cc-8c93-32b022885439@suse.com>
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On 12/08/2025 9:16 am, Jan Beulich wrote:
> On 08.08.2025 22:22, Andrew Cooper wrote:
>> After some experimentation, using .a/.b makes far better logic than using the
>> named fields, as both Clang and GCC spill idte to the stack when named fields
>> are used.
>>
>> GCC seems to do something very daft for the addr1 field.  It takes addr,
>> shifts it by 32, then ANDs with 0xffff0000000000000UL, which requires
>> manifesting a MOVABS.
>>
>> Clang follows the C, whereby it ANDs with $imm32, then shifts, avoiding the
>> MOVABS entirely.
>>
>> No functional change.
>>
>> Signed-off-by: Andrew Cooper 
> Acked-by: Jan Beulich 

Thanks.

> albeit I have to admit that I'm not quite happy about ...
>
>> --- a/xen/arch/x86/include/asm/idt.h
>> +++ b/xen/arch/x86/include/asm/idt.h
>> @@ -92,15 +92,16 @@ static inline void _set_gate_lower(idt_entry_t *gate, unsigned long type,
>>   * Update the lower half handler of an IDT entry, without changing any other
>>   * configuration.
>>   */
>> -static inline void _update_gate_addr_lower(idt_entry_t *gate, void *addr)
>> +static inline void _update_gate_addr_lower(idt_entry_t *gate, void *_addr)
>>  {
>> +    unsigned long addr = (unsigned long)_addr;
>> +    unsigned int addr1 = addr & 0xffff0000U; /* GCC force better codegen. */
>>      idt_entry_t idte;
>> -    idte.a = gate->a;
>>  
>> -    idte.b = ((unsigned long)(addr) >> 32);
>> -    idte.a &= 0x0000FFFFFFFF0000ULL;
>> -    idte.a |= (((unsigned long)(addr) & 0xFFFF0000UL) << 32) |
>> -        ((unsigned long)(addr) & 0xFFFFUL);
>> +    idte.b = addr >> 32;
>> +    idte.a = gate->a & 0x0000ffffffff0000UL;
>> +    idte.a |= (unsigned long)addr1 << 32;
> ... the cast here. Yet perhaps gcc still generates a MOVABS when you make
> addr1 unsigned long?

Correct.  Forcing the mask operation to be 32bit is the only way I found
of avoiding the MOVABS.

>
> As to the comment next to the variable declaration: Could I talk you into
> adding a colon after "GCC"? Without one, the comment reads somewhat
> ambiguously to me.

Ok.

~Andrew


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Subject: Re: [PATCH 06/22] x86/traps: Introduce bsp_traps_reinit()
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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In-Reply-To: <59f267a5-ca5f-4708-8538-e2c7d5fc0c3b@suse.com>
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On 12/08/2025 9:19 am, Jan Beulich wrote:
> On 08.08.2025 22:22, Andrew Cooper wrote:
>> ... to abstract away updating the refereces to the old BSP stack.
>>
>> Signed-off-by: Andrew Cooper 
> If it helps later:
> Acked-by: Jan Beulich 
> with ..
>
>> --- a/xen/arch/x86/traps-setup.c
>> +++ b/xen/arch/x86/traps-setup.c
>> @@ -107,6 +107,15 @@ void __init traps_init(void)
>>      percpu_traps_init();
>>  }
>>  
>> +/*
>> + * Re-initialise all state referencing the early-boot stack.
>> + */
>> +void bsp_traps_reinit(void)
> ... __init added here.

Oops, yes.  Fixed.  Thanks.

~Andrew


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Date: Wed, 13 Aug 2025 12:04:57 +0200
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH 00/20] Add SMMUv3 Stage 1 Support for XEN guests
To: Julien Grall 
Cc: "xen-devel@lists.xenproject.org" ,
 Bertrand Marquis ,
 Rahul Singh ,
 Stefano Stabellini ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Anthony PERARD ,
 Nick Rosbrook , George Dunlap ,
 Juergen Gross , Andrew Cooper 
References: 
 
Content-Language: en-US
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On 8/7/25 19:58, Julien Grall wrote:
> Hi Milan,
> 
> On Thu, 7 Aug 2025 at 17:55, Milan Djokic  > wrote:
> 
>     This patch series represents a rebase of an older patch series
>     implemented and
>     sumbitted by Rahul Singh as an RFC: https://patchwork.kernel.org/
>     project/xen-devel/cover/cover.1669888522.git.rahul.singh@arm.com/
>          url=https%3A%2F%2Fpatchwork.kernel.org%2Fproject%2Fxen-
>     devel%2Fcover%2Fcover.1669888522.git.rahul.singh%40arm.com%2F&data=05%7C02%7Cmilan_djokic%40epam.com%7C03265dfcc1a94a11e83f08ddd5dc0edc%7Cb41b72d04e9f4c268a69f949f367c91d%7C1%7C0%7C638901863296475715%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=bdsPyXoIqvzwWIWk0Ot3BDOu8yAaF%2Bq3Vrs4wsmZJEA%3D&reserved=0>.
>     Original patch series content is aligned with the latest xen
>     structure in terms of common/arch-specific code structuring.
>     Some minor bugfixes are also applied:
>     - Sanity checks / error handling
>     - Non-pci devices support for emulated iommu
> 
> 
> 
>     Overall description of stage-1 support is available in the original
>     patch series cover letter. Original commits structure with detailed
>     explanation for each commit
>     functionality is maintained.
> 
> 
> I am a bit surprised not much has changed. Last time we asked a document 
> to explain the overall design of the vSMMU including some details on the 
> security posture. I can’t remember if this was ever posted.
> 
> If not, then you need to start with that. Otherwise, if is going to be 
> pretty difficult to review this series.
> 
> Cheers,
Hello Julien,

We have prepared a design document and it will be part of the updated 
patch series (added in docs/design). I'll also extend cover letter with 
details on implementation structure to make review easier.
Following is the design document content which will be provided in 
updated patch series:

Design Proposal: Add SMMUv3 Stage-1 Support for XEN Guests
==========================================================

Author: Milan Djokic 
Date:   2025-08-07
Status: Draft

Introduction
------------

The SMMUv3 supports two stages of translation. Each stage of translation
can be independently enabled. An incoming address is logically
translated from VA to IPA in stage 1, then the IPA is input to stage 2
which translates the IPA to the output PA. Stage 1 translation support
is required to provide isolation between different devices within the OS.

Xen already supports Stage 2 translation but there is no support for
Stage 1 translation. This design proposal outlines the introduction of
Stage-1 SMMUv3 support in Xen for ARM guests.

Motivation
----------

ARM systems utilizing SMMUv3 require Stage-1 address translation to
ensure correct and secure DMA behavior inside guests.

This feature enables:
- Stage-1 translation in guest domain
- Safe device passthrough under secure memory translation

Design Overview
---------------

These changes provide emulated SMMUv3 support:

- SMMUv3 Stage-1 Translation: stage-1 and nested translation support in
   SMMUv3 driver
- vIOMMU Abstraction: virtual IOMMU framework for guest Stage-1 handling
- Register/Command Emulation: SMMUv3 register emulation and command
   queue handling
- Device Tree Extensions: adds iommus and virtual SMMUv3 nodes to
   device trees for dom0 and dom0less scenarios
- Runtime Configuration: introduces a 'viommu' boot parameter for
   dynamic enablement

Security Considerations
------------------------

viommu security benefits:
- Stage-1 translation ensures guest devices cannot perform unauthorized
   DMA
- Emulated SMMUv3 for domains removes dependency on host hardware while
   maintaining isolation

Observations and Potential Risks
--------------------------------

1. Observation:
Support for Stage-1 translation introduces new data structures
(s1_cfg and s2_cfg) and logic to write both Stage-1 and Stage-2 entries
in the Stream Table Entry (STE), including an abort field for partial
config states.

Risk:
A partially applied Stage-1 configuration might leave guest DMA
mappings in an inconsistent state, enabling unauthorized access or
cross-domain interference.

Mitigation (Handled by design):
Both s1_cfg and s2_cfg are written atomically. The abort field ensures
Stage-1 config is only used when fully applied. Incomplete configs are
ignored by the hypervisor.

2. Observation:
Guests can now issue Stage-1 cache invalidations.

Risk:
Failure to propagate invalidations could leave stale mappings, enabling
data leakage or misrouting.

Mitigation (Handled by design):
Guest invalidations are forwarded to the hardware to ensure IOMMU
coherency.

3. Observation:
The feature introduces large functional changes including the vIOMMU
framework, vsmmuv3 devices, command queues, event queues, domain
handling, and Device Tree modifications.

Risk:
Increased attack surface with risk of race conditions, malformed
commands, or misconfiguration via the device tree.

Mitigation:
- Improved sanity checks and error handling
- Feature is marked as Tech Preview and self-contained to reduce risk
   to unrelated code

4. Observation:
The implementation supports nested and standard translation modes,
using guest command queues (e.g. CMD_CFGI_STE) and events.

Risk:
Malicious commands could bypass validation and corrupt SMMUv3 state or
destabilize dom0.

Mitigation (Handled by design):
Command queues are validated, and only permitted configuration changes
are accepted. Handled in vsmmuv3 and cmdqueue logic.

5. Observation:
Device Tree changes inject iommus and vsmmuv3 nodes via libxl.

Risk:
Malicious or incorrect DT fragments could result in wrong device
assignments or hardware access.

Mitigation:
Only vetted and sanitized DT fragments are allowed. libxl limits what
guests can inject.

6. Observation:
The feature is enabled per-guest via viommu setting.

Risk:
Guests without viommu may behave differently, potentially causing
confusion, privilege drift, or accidental exposure.

Mitigation:
Ensure downgrade paths are safe. Perform isolation audits in
multi-guest environments to ensure correct behavior.

Performance Impact
------------------

Hardware-managed translations are expected to have minimal overhead.
Emulated vIOMMU may introduce some latency during initialization or
event processing.

Testing
-------

- QEMU-based testing for Stage-1 and nested translation
- Hardware testing on Renesas SMMUv3-enabled ARM systems
- Unit tests for translation accuracy (not yet implemented)

Migration and Compatibility
---------------------------

This feature is optional and disabled by default (viommu="") to ensure
backward compatibility.

References
----------

- Original implementation by Rahul Singh:
  
https://patchwork.kernel.org/project/xen-devel/cover/cover.1669888522.git.rahul.singh@arm.com/
- ARM SMMUv3 architecture documentation
- Existing vIOMMU code in Xen


BR,
Milan




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Subject: Re: [PATCH 07/20] xen/arm: vIOMMU: Add cmdline boot option "viommu =
 "
To: Jan Beulich 
Cc: Rahul Singh ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Volodymyr Babchuk ,
 "xen-devel@lists.xenproject.org" 
References: 
 
 
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Hello Jan,

On 8/8/25 08:20, Jan Beulich wrote:
> On 07.08.2025 18:59, Milan Djokic wrote:
>> --- a/docs/misc/xen-command-line.pandoc
>> +++ b/docs/misc/xen-command-line.pandoc
>> @@ -2058,6 +2058,13 @@ This option can be specified more than once (up to 8 times at present).
>>   
>>   Flag to enable or disable support for PCI passthrough
>>   
>> +### viommu (arm)
>> +> `= `
>> +
>> +> Default: `false`
>> +
>> +Flag to enable or disable support for Virtual IOMMU for guests.
> 
> Isn't this too coarse-grained? IOW don't you want to specify the kind of IOMMU
> to use, even if right now only one is being implemented? Also - why on the
> command line? Isn't this rather a per-guest setting?
>
Yes, it would make more sense to specify IOMMU kind instead of plain 
enable/disable parameter. Updated in new patch series version.
As for reasons to have this parameter in xen command line, it is needed 
for xen smmuv3 driver initialization, where viommu initialization is 
done if 'viommu' is enabled. Also, for dom0less mode and dom0 itself, 
viommu for domain is enabled while domain is created based on this 
argument. We do have per-guest viommu enablement option for guests 
created with xl, but this does not cover dom0 (and dom0-less).

>>   ### pcid (x86)
>>   > `=  | xpti=`
> 
> Also, seeing this adjacent entry, you're inserting in the wrong place. The
> options are supposed to be alphabetically sorted.
>
We'll fix this in the new version with other suggested changes included.

> Jan

BR,
Milan



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Subject: Re: [PATCH 07/22] x86/spec-ctrl: Rework init_shadow_spec_ctrl_state()
 to take an info pointer
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-8-andrew.cooper3@citrix.com>
 
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On 12/08/2025 9:27 am, Jan Beulich wrote:
> On 08.08.2025 22:22, Andrew Cooper wrote:
>> We're going to want to reuse it for a remote stack shortly.
> Are we? From the titles of subsequent patches I can't judge where that would
> be, so it's hard to peek ahead. And iirc earlier on it was a concious decision
> to only ever run this locally.

I don't recall that.  I recall bugs which occurred because there were
several variables and we failed to sync one of them.

Either way, it's very clearly the right course of action to take now.

>
>> No functional change.
>>
>> Signed-off-by: Andrew Cooper 
> Nevertheless, trusting that you have a good reason:
> Acked-by: Jan Beulich 

Thanks.

~Andrew


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From: Andrew Cooper 
Subject: Re: [PATCH 08/22] x86/traps: Introduce ap_early_traps_init() and set
 up exception handling earlier
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 12/08/2025 9:41 am, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> --- a/xen/arch/x86/acpi/wakeup_prot.S
>> +++ b/xen/arch/x86/acpi/wakeup_prot.S
>> @@ -63,6 +63,9 @@ LABEL(s3_resume)
>>          pushq   %rax
>>          lretq
>>  1:
>> +        /* Set up early exceptions and CET before entering C properly. */
>> +        call    ap_early_traps_init
> But this is the BSP?

By the end of the cleanup, what we have is:

At boot only:
 * really early init, basic exception handling only
 * regular init (inc syscall trampolines)
 * late re-init as we change the stack linear address

For everything else (APs, S3, hot-online):
 * early, full exception handling
 * regular init (inc syscall trampolines)


Currently, these are named:
 * bsp_early_traps_init()
 * traps_init()
 * bsp_traps_reinit()

and
 * ap_early_traps_init()
 * percpu_traps_init()


Perhaps ap_early_traps_init() should be named
percpu_early_traps_init()?  But I'm open to suggestions.

>
>> --- a/xen/arch/x86/smpboot.c
>> +++ b/xen/arch/x86/smpboot.c
>> @@ -327,12 +327,7 @@ void asmlinkage start_secondary(void)
>>      struct cpu_info *info = get_cpu_info();
>>      unsigned int cpu = smp_processor_id();
>>  
>> -    /* Critical region without IDT or TSS.  Any fault is deadly! */
>> -
>> -    set_current(idle_vcpu[cpu]);
>> -    this_cpu(curr_vcpu) = idle_vcpu[cpu];
>>      rdmsrl(MSR_EFER, this_cpu(efer));
>> -    init_shadow_spec_ctrl_state(info);
>>  
>>      /*
>>       * Just as during early bootstrap, it is convenient here to disable
>> @@ -352,14 +347,6 @@ void asmlinkage start_secondary(void)
>>       */
>>      spin_debug_disable();
>>  
>> -    get_cpu_info()->use_pv_cr3 = false;
>> -    get_cpu_info()->xen_cr3 = 0;
>> -    get_cpu_info()->pv_cr3 = 0;
>> -
>> -    load_system_tables();
>> -
>> -    /* Full exception support from here on in. */
>> -
>>      if ( cpu_has_pks )
>>          wrpkrs_and_cache(0); /* Must be before setting CR4.PKS */
>>  
>> @@ -1064,8 +1051,12 @@ static int cpu_smpboot_alloc(unsigned int cpu)
>>              goto out;
>>  
>>      info = get_cpu_info_from_stack((unsigned long)stack_base[cpu]);
>> +    memset(info, 0, sizeof(*info));
> Why do we suddenly need this? Or is this just out of an abundance of
> caution (while making the individual ->*_cr3 writes unnecessary)?

cpu_alloc_stack() explicitly uses alloc_xenheap_pages() which uses
MEMF_no_scrub.  It will usually be zeroed memory because we allocate
them all at the start of day, but it also has a habbit of being 0xc2'd
when running under Xen.

Also yes, I do dislike the ad-hoc zeroes of misc fields.

>
>> +    init_shadow_spec_ctrl_state(info);
> May I suggest to move this further down a little, at least ...
>
>>      info->processor_id = cpu;
> ... past here? Just in case other values in the struct may be needed
> in the function at some point.

Ok.

>
>>      info->per_cpu_offset = __per_cpu_offset[cpu];
>> +    info->current_vcpu = idle_vcpu[cpu];
> To be able to spot this, I think it wants /* set_current() */ or some
> such.

Ok.

>
>> +    per_cpu(curr_vcpu, cpu) = idle_vcpu[cpu];
> It's a little odd to do this early (and remotely), but it looks all fine
> with how the variable is currently used.

It did take a little while for me to conclude that it is safe, but yes -
it does relax a lot of ordering constraints for AP bringup.

~Andrew



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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
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To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 12/08/2025 10:19 am, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> Switch it to Xen coding style and fix MISRA violations.
> That were all ul -> UL suffix transformations, afaics?

Yes.

>
>>  Make it static as
>> there are no external caller now.
>>
>> Since commit a35816b5cae8 ("x86/traps: Introduce early_traps_init() and
>> simplify setup"), load_system_tables() is called later on the BSP, so the
>> SYS_STATE_early_boot check can be dropped from the safety BUG_ON().
>>
>> Move the BUILD_BUG_ON() into build_assertions(),
> I'm not quite convinced of this move - having the related BUILD_BUG_ON()
> and BUG_ON() next to each other would seem better to me.

I don't see a specific reason for them to be together, and the comment
explains what's going on.

With FRED, we want a related BUILD_BUG_ON(), but there's no equivalent
BUG_ON() because MSR_RSP_SL0 will #GP on being misaligned.

>> @@ -139,3 +258,16 @@ void asmlinkage ap_early_traps_init(void)
>>  {
>>      load_system_tables();
>>  }
>> +
>> +static void __init __maybe_unused build_assertions(void)
>> +{
>> +    /*
>> +     * This is best-effort (it doesn't cover some padding corner cases), but
>> +     * is preforable to hitting the check at boot time.
> Nit: "preferable"

Fixed.

~Andrew


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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
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To: Nicola Vetrini 
Cc: Xen-devel ,
 Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 12/08/2025 10:43 am, Nicola Vetrini wrote:
> On 2025-08-08 22:23, Andrew Cooper wrote:
>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>> index 8ca379c9e4cb..13b8fcf0ba51 100644
>> --- a/xen/arch/x86/traps-setup.c
>> +++ b/xen/arch/x86/traps-setup.c
>> @@ -19,6 +20,124 @@ boolean_param("ler", opt_ler);
>>
>>  void nocall entry_PF(void);
>>
>> +/*
>> + * Sets up system tables and descriptors for IDT devliery.
>> + *
>> + * - Sets up TSS with stack pointers, including ISTs
>> + * - Inserts TSS selector into regular and compat GDTs
>> + * - Loads GDT, IDT, TR then null LDT
>> + * - Sets up IST references in the IDT
>> + */
>> +static void load_system_tables(void)
>> +{
>> +    unsigned int i, cpu = smp_processor_id();
>> +    unsigned long stack_bottom = get_stack_bottom(),
>> +        stack_top = stack_bottom & ~(STACK_SIZE - 1);
>> +    /*
>> +     * NB: define tss_page as a local variable because clang 3.5
>> doesn't
>> +     * support using ARRAY_SIZE against per-cpu variables.
>> +     */
>> +    struct tss_page *tss_page = &this_cpu(tss_page);
>> +    idt_entry_t *idt = this_cpu(idt);
>> +
>
> Given the clang baseline this might not be needed anymore?

Hmm.  While true, looking at 51461114e26, the code is definitely better
written with the tss_page variable and we wouldn't want to go back to
the old form.

I think that I'll simply drop the comment.

~Andrew

P.S.

Generally speaking, because of the RELOC_HIDE() in this_cpu(), any time
you ever want two accesses to a variable, it's better (code gen wise) to
construct a pointer to it and use the point multiple times.

I don't understand why there's a RELOC_HIDE() in this_cpu().  The
justification doesn't make sense, but I've not had time to explore what
happens if we take it out.


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Subject: [Coverity complaint] Re: [PATCH v5] pdx: introduce a new compression
 algorithm based on region offsets
To: Roger Pau Monne , xen-devel@lists.xenproject.org
Cc: Oleksii Kurochko ,
 Community Manager ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , Stefano Stabellini 
References: <20250812150624.64898-1-roger.pau@citrix.com>
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In-Reply-To: <20250812150624.64898-1-roger.pau@citrix.com>
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On 12/08/2025 4:06 pm, Roger Pau Monne wrote:
> Signed-off-by: Roger Pau Monné 

Not this patch, but this is probably the best place to report it.

https://scan5.scan.coverity.com/#/project-view/30554/10426?selectedIssue=1662707

Something you did in the series made enough changes in
pfn_pdx_compression_setup() for Coverity to start reporting an issue in
some decade-old code.

The complaint is on line:

277    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
CID 1662707: (#1 of 1): Bad bit shift operation (BAD_SHIFT)

34. large_shift: In expression 0x1000 << bottom_shift, left shifting by more than 31 bits
has undefined behavior. The shift amount, bottom_shift, is as much as 63.


The relevant part of earlier analysis seems to be the "i >=
BITS_PER_LONG" check in the order loop, causing Coverity to think that i
can be up to 63.

~Andrew


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On 12/08/2025 10:52 am, Jan Beulich wrote:
> On 11.08.2025 10:17, Andrew Cooper wrote:
>> On 08/08/2025 9:23 pm, Andrew Cooper wrote:
>>> ... along with the supporting functions.  Switch to Xen coding style, and make
>>> static as there are no external callers.
>>>
>>> Rename to legacy_syscall_init() as a more accurate name.
>>>
>>> No functional change.
>>>
>>> Signed-off-by: Andrew Cooper 
>>> ---
>>> CC: Jan Beulich 
>>> CC: Roger Pau Monné 
>>> ---
>>>  xen/arch/x86/include/asm/system.h |  2 -
>>>  xen/arch/x86/traps-setup.c        | 97 ++++++++++++++++++++++++++++++-
>>>  xen/arch/x86/x86_64/traps.c       | 92 -----------------------------
>>>  3 files changed, 95 insertions(+), 96 deletions(-)
>>>
>>> diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
>>> index 3cdc56e4ba6d..6c2800d8158d 100644
>>> --- a/xen/arch/x86/include/asm/system.h
>>> +++ b/xen/arch/x86/include/asm/system.h
>>> @@ -256,6 +256,4 @@ static inline int local_irq_is_enabled(void)
>>>  #define BROKEN_ACPI_Sx          0x0001
>>>  #define BROKEN_INIT_AFTER_S1    0x0002
>>>  
>>> -void subarch_percpu_traps_init(void);
>>> -
>>>  #endif
>>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>>> index 13b8fcf0ba51..fbae7072c292 100644
>>> --- a/xen/arch/x86/traps-setup.c
>>> +++ b/xen/arch/x86/traps-setup.c
>>> @@ -2,13 +2,15 @@
>>>  /*
>>>   * Configuration of event handling for all CPUs.
>>>   */
>>> +#include 
>>>  #include 
>>>  #include 
>>>  
>>> +#include 
>>>  #include 
>>>  #include 
>>>  #include 
>>> -#include 
>>> +#include 
>>>  #include 
>>>  
>>>  DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt);
>>> @@ -19,6 +21,8 @@ static bool __initdata opt_ler;
>>>  boolean_param("ler", opt_ler);
>>>  
>>>  void nocall entry_PF(void);
>>> +void nocall lstar_enter(void);
>>> +void nocall cstar_enter(void);
>>>  
>>>  /*
>>>   * Sets up system tables and descriptors for IDT devliery.
>>> @@ -138,6 +142,95 @@ static void load_system_tables(void)
>>>      BUG_ON(stack_bottom & 15);
>>>  }
>>>  
>>> +static unsigned int write_stub_trampoline(
>>> +    unsigned char *stub, unsigned long stub_va,
>>> +    unsigned long stack_bottom, unsigned long target_va)
>>> +{
>>> +    unsigned char *p = stub;
>>> +
>>> +    if ( cpu_has_xen_ibt )
>>> +    {
>>> +        place_endbr64(p);
>>> +        p += 4;
>>> +    }
>>> +
>>> +    /* Store guest %rax into %ss slot */
>>> +    /* movabsq %rax, stack_bottom - 8 */
>>> +    *p++ = 0x48;
>>> +    *p++ = 0xa3;
>>> +    *(uint64_t *)p = stack_bottom - 8;
>>> +    p += 8;
>>> +
>>> +    /* Store guest %rsp in %rax */
>>> +    /* movq %rsp, %rax */
>>> +    *p++ = 0x48;
>>> +    *p++ = 0x89;
>>> +    *p++ = 0xe0;
>>> +
>>> +    /* Switch to Xen stack */
>>> +    /* movabsq $stack_bottom - 8, %rsp */
>>> +    *p++ = 0x48;
>>> +    *p++ = 0xbc;
>>> +    *(uint64_t *)p = stack_bottom - 8;
>>> +    p += 8;
>>> +
>>> +    /* jmp target_va */
>>> +    *p++ = 0xe9;
>>> +    *(int32_t *)p = target_va - (stub_va + (p - stub) + 4);
>>> +    p += 4;
>>> +
>>> +    /* Round up to a multiple of 16 bytes. */
>>> +    return ROUNDUP(p - stub, 16);
>>> +}
>>> +
>>> +static void legacy_syscall_init(void)
>>> +{
>>> +    unsigned long stack_bottom = get_stack_bottom();
>>> +    unsigned long stub_va = this_cpu(stubs.addr);
>>> +    unsigned char *stub_page;
>>> +    unsigned int offset;
>>> +
>>> +    /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
>>> +    if ( !IS_ENABLED(CONFIG_PV) )
>>> +        return;
>>> +
>>> +    stub_page = map_domain_page(_mfn(this_cpu(stubs.mfn)));
>>> +
>>> +    /*
>>> +     * Trampoline for SYSCALL entry from 64-bit mode.  The VT-x HVM vcpu
>>> +     * context switch logic relies on the SYSCALL trampoline being at the
>>> +     * start of the stubs.
>>> +     */
>>> +    wrmsrl(MSR_LSTAR, stub_va);
>>> +    offset = write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>> +                                   stub_va, stack_bottom,
>>> +                                   (unsigned long)lstar_enter);
>>> +    stub_va += offset;
>>> +
>>> +    if ( cpu_has_sep )
>>> +    {
>>> +        /* SYSENTER entry. */
>>> +        wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
>>> +        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
>>> +        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
>>> +    }
>>> +
>>> +    /* Trampoline for SYSCALL entry from compatibility mode. */
>>> +    wrmsrl(MSR_CSTAR, stub_va);
>>> +    offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>> +                                    stub_va, stack_bottom,
>>> +                                    (unsigned long)cstar_enter);
>>> +
>>> +    /* Don't consume more than half of the stub space here. */
>>> +    ASSERT(offset <= STUB_BUF_SIZE / 2);
>>> +
>>> +    unmap_domain_page(stub_page);
>>> +
>>> +    /* Common SYSCALL parameters. */
>>> +    wrmsrl(MSR_STAR, XEN_MSR_STAR);
>>> +    wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
>>> +}
>> These want adjusting to use wrmsrns(), similarly to the previous patch. 
>> Fixed locally.
> Also the one higher in the function, I suppose.

All of them.

I'm not aware of anywhere were we want serialising behaviour, except for
ICR which is buggly non-serialising and has workarounds.

But I'm also not sure enough of this to suggest that we make wrmsr() be
wrmsrns() by default.

> Acked-by: Jan Beulich 

Thanks.

~Andrew


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Date: Wed, 13 Aug 2025 13:11:12 +0100
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH 00/20] Add SMMUv3 Stage 1 Support for XEN guests
Content-Language: en-GB
To: Milan Djokic ,
 Julien Grall 
Cc: "xen-devel@lists.xenproject.org" ,
 Bertrand Marquis ,
 Rahul Singh ,
 Stefano Stabellini ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Anthony PERARD ,
 Nick Rosbrook , George Dunlap ,
 Juergen Gross , Andrew Cooper 
References: 
 
 <12ba4388-ee23-4e17-910f-9702271865ad@epam.com>
From: Julien Grall 
In-Reply-To: <12ba4388-ee23-4e17-910f-9702271865ad@epam.com>
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On 13/08/2025 11:04, Milan Djokic wrote:
> Hello Julien,

Hi Milan,

> 
> We have prepared a design document and it will be part of the updated 
> patch series (added in docs/design). I'll also extend cover letter with 
> details on implementation structure to make review easier.

I would suggest to just iterate on the design document for now.

> Following is the design document content which will be provided in 
> updated patch series:
> 
> Design Proposal: Add SMMUv3 Stage-1 Support for XEN Guests
> ==========================================================
> 
> Author: Milan Djokic 
> Date:   2025-08-07
> Status: Draft
> 
> Introduction
> ------------
> 
> The SMMUv3 supports two stages of translation. Each stage of translation
> can be independently enabled. An incoming address is logically
> translated from VA to IPA in stage 1, then the IPA is input to stage 2
> which translates the IPA to the output PA. Stage 1 translation support
> is required to provide isolation between different devices within the OS.
> 
> Xen already supports Stage 2 translation but there is no support for
> Stage 1 translation. This design proposal outlines the introduction of
> Stage-1 SMMUv3 support in Xen for ARM guests.
> 
> Motivation
> ----------
> 
> ARM systems utilizing SMMUv3 require Stage-1 address translation to
> ensure correct and secure DMA behavior inside guests.

Can you clarify what you mean by "correct"? DMA would still work without 
stage-1.
> 
> This feature enables:
> - Stage-1 translation in guest domain
> - Safe device passthrough under secure memory translation
> 
> Design Overview
> ---------------
> 
> These changes provide emulated SMMUv3 support:
> 
> - SMMUv3 Stage-1 Translation: stage-1 and nested translation support in
>    SMMUv3 driver
> - vIOMMU Abstraction: virtual IOMMU framework for guest Stage-1 handling

So what are you planning to expose to a guest? Is it one vIOMMU per 
pIOMMU? Or a single one?

Have you considered the pros/cons for both?
> - Register/Command Emulation: SMMUv3 register emulation and command
>    queue handling

For each pSMMU, we have a single command queue that will receive command 
from all the guests. How do you plan to prevent a guest hogging the 
command queue?

In addition to that, AFAIU, the size of the virtual command queue is 
fixed by the guest rather than Xen. If a guest is filling up the queue 
with commands before notifying Xen, how do you plan to ensure we don't 
spend too much time in Xen (which is not preemptible)?

Lastly, what do you plan to expose? Is it a full vIOMMU (including event 
forwarding)?

> - Device Tree Extensions: adds iommus and virtual SMMUv3 nodes to
>    device trees for dom0 and dom0less scenarios
> - Runtime Configuration: introduces a 'viommu' boot parameter for
>    dynamic enablement
> 
> Security Considerations
> ------------------------
> 
> viommu security benefits:
> - Stage-1 translation ensures guest devices cannot perform unauthorized
>    DMA
> - Emulated SMMUv3 for domains removes dependency on host hardware while
>    maintaining isolation

I don't understand this sentence.

> 
> Observations and Potential Risks
> --------------------------------
> 
> 1. Observation:
> Support for Stage-1 translation introduces new data structures
> (s1_cfg and s2_cfg) and logic to write both Stage-1 and Stage-2 entries
> in the Stream Table Entry (STE), including an abort field for partial
> config states.
> 
> Risk:
> A partially applied Stage-1 configuration might leave guest DMA
> mappings in an inconsistent state, enabling unauthorized access or
> cross-domain interference.

I don't understand how a misconfigured stage-1 could lead to 
cross-domain interference. Can you clarify?

> 
> Mitigation (Handled by design):
> Both s1_cfg and s2_cfg are written atomically. The abort field ensures
> Stage-1 config is only used when fully applied. Incomplete configs are
> ignored by the hypervisor.
> 
> 2. Observation:
> Guests can now issue Stage-1 cache invalidations.
> 
> Risk:
> Failure to propagate invalidations could leave stale mappings, enabling
> data leakage or misrouting.

This is a risk from the guest PoV, right? IOW, this would not open up a 
security hole in Xen.

> 
> Mitigation (Handled by design):
> Guest invalidations are forwarded to the hardware to ensure IOMMU
> coherency.
> 
> 3. Observation:
> The feature introduces large functional changes including the vIOMMU
> framework, vsmmuv3 devices, command queues, event queues, domain
> handling, and Device Tree modifications.
> 
> Risk:
> Increased attack surface with risk of race conditions, malformed
> commands, or misconfiguration via the device tree.
> 
> Mitigation:
> - Improved sanity checks and error handling
> - Feature is marked as Tech Preview and self-contained to reduce risk
>    to unrelated code

Surely, you will want to use the code in production... No?

> 
> 4. Observation:
> The implementation supports nested and standard translation modes,
> using guest command queues (e.g. CMD_CFGI_STE) and events.
> 
> Risk:
> Malicious commands could bypass validation and corrupt SMMUv3 state or
> destabilize dom0.
> 
> Mitigation (Handled by design):
> Command queues are validated, and only permitted configuration changes
> are accepted. Handled in vsmmuv3 and cmdqueue logic.

I didn't mention anything in obversation 1 but now I have to say it... 
The observations you wrote are what I would expect to be handled in any 
submission to our code base. This is the bare minimum to have the code 
secure. But you don't seem to address the more subttle ones which are 
more related to scheduling issue (see some above). They require some 
design and discussion.

> 
> 5. Observation:
> Device Tree changes inject iommus and vsmmuv3 nodes via libxl.
> 
> Risk:
> Malicious or incorrect DT fragments could result in wrong device
> assignments or hardware access.
> 
> Mitigation:
> Only vetted and sanitized DT fragments are allowed. libxl limits what
> guests can inject.

Today, libxl doesn't do any sanitisation on the DT. In fact, this is 
pretty much impossible because libfdt expects trusted DT. Is this 
something you are planning to change?
> 
> 6. Observation:
> The feature is enabled per-guest via viommu setting.
> 
> Risk:
> Guests without viommu may behave differently, potentially causing
> confusion, privilege drift, or accidental exposure.
> 
> Mitigation:
> Ensure downgrade paths are safe. Perform isolation audits in
> multi-guest environments to ensure correct behavior.
> 
> Performance Impact
> ------------------
> 
> Hardware-managed translations are expected to have minimal overhead.
> Emulated vIOMMU may introduce some latency during initialization or
> event processing.

Latency to who? We still expect isolation between guests and a guest 
will not go over its time slice.

For the guest itself, the main performance impact will be TLB flushes 
because they are commands that will end up to be emulated by Xen. 
Depending on your Linux configuration (I haven't checked other), this 
will either happen every unmap operation or they will be batch. The 
performance of the latter will be the worse one.

Have you done any benchmark to confirm the impact? Just to note, I would 
not gate the work for virtual SMMUv3 based on the performance. I think 
it is ok to offer the support if the user want extra security and 
doesn't care about performance. But it would be good to outline them as 
I expect them to be pretty bad...

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH 13/22] x86: FRED enumerations
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Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
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In-Reply-To: <20250808202314.1045968-14-andrew.cooper3@citrix.com>
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On 08/08/2025 9:23 pm, Andrew Cooper wrote:
> diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig
> index a45ce106e210..90cbad13a7c7 100644
> --- a/xen/arch/x86/Kconfig
> +++ b/xen/arch/x86/Kconfig
> @@ -57,6 +57,10 @@ config HAS_CC_CET_IBT
>  	# Retpoline check to work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654
>  	def_bool $(cc-option,-fcf-protection=branch -mmanual-endbr -mindirect-branch=thunk-extern) && $(as-instr,endbr64)
>  
> +config HAS_AS_FRED
> +	# binutils >= 2.41 or LLVM >= 19
> +	def_bool $(as-instr,eretu;lkgs %ax)
> +
>  menu "Architecture Features"
>  
>  source "arch/x86/Kconfig.cpu"
> diff --git a/xen/arch/x86/include/asm/asm-defns.h b/xen/arch/x86/include/asm/asm-defns.h
> index 61a5faf90446..2e5200b94b82 100644
> --- a/xen/arch/x86/include/asm/asm-defns.h
> +++ b/xen/arch/x86/include/asm/asm-defns.h
> @@ -4,6 +4,15 @@
>      .byte 0x0f, 0x01, 0xfc
>  .endm
>  
> +#ifndef CONFIG_HAS_AS_FRED
> +.macro eretu
> +    .byte 0xf3, 0x0f, 0x01, 0xca
> +.endm
> +.macro erets
> +    .byte 0xf2, 0x0f, 0x01, 0xca
> +.endm
> +#endif

Seeing as I know you are going to be unhappy with the Kconfig...

I think I'm dev complete on the PV support now, and there's not an LKGS
in sight.

We don't strictly need the conditional in asm-defns.h, and if we don't
need it in C either then we can drop the Kconfig entirely.

~Andrew


From xen-devel-bounces@lists.xenproject.org Wed Aug 13 12:38:36 2025
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Date: Wed, 13 Aug 2025 14:38:29 +0200
From: Anthony PERARD 
To: Marek =?iso-8859-1?Q?Marczykowski-G=F3recki?= 
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH v2 1/3] CI: Rework run-tools-test exit path
Message-ID: 
References: <20250730152602.45436-1-anthony@xenproject.org>
 <20250730152602.45436-2-anthony@xenproject.org>
 
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On Sat, Aug 09, 2025 at 06:22:33PM +0200, Marek Marczykowski-Górecki wrote:
> On Wed, Jul 30, 2025 at 05:26:00PM +0200, Anthony PERARD wrote:
> > From: Anthony PERARD 
> > 
> > The main script expect to find the string "$passed" or it just timeout
> > and doesn't try to download the junit file in this case. So we ignore
> > the return value of run-tools-test to always print "$passed" and
> > instead look for failure in the generated junit file. If the junit
> > report is incomplete, this will also result in a failure of the job.
> > 
> > Signed-off-by: Anthony PERARD 
> > ---
> > 
> > Notes:
> >     Changes in v2:
> >     - This squash both patch "CI: Ignore run-tools-test return value" and
> >       "CI: Have the gitlab job fail on tools/tests failure"
> >     - grep for ''
> > 
> >  automation/scripts/qubes-x86-64.sh | 13 +++++++++++--
> >  1 file changed, 11 insertions(+), 2 deletions(-)
> > 
> > diff --git a/automation/scripts/qubes-x86-64.sh b/automation/scripts/qubes-x86-64.sh
> > index 2750d24eba..21dcd9b063 100755
> > --- a/automation/scripts/qubes-x86-64.sh
> > +++ b/automation/scripts/qubes-x86-64.sh
> > @@ -135,10 +135,11 @@ done
> >      ### tests: tools-tests-pv, tools-tests-pvh
> >      "tools-tests-pv"|"tools-tests-pvh")
> >          retrieve_xml=1
> > -        passed="test passed"
> > +        passed="run-tools-test over"
> >          domU_check=""
> >          dom0_check="
> > -/root/run-tools-tests /usr/lib/xen/tests /tmp/tests-junit.xml && echo \"${passed}\"
> > +/root/run-tools-tests /usr/lib/xen/tests /tmp/tests-junit.xml ||:
> > +echo \"${passed}\"
> >  nc -l -p 8080 < /tmp/tests-junit.xml >/dev/null &
> >  "
> >          if [ "${test_variant}" = "tools-tests-pvh" ]; then
> > @@ -297,6 +298,14 @@ TEST_RESULT=$?
> >  
> >  if [ -n "$retrieve_xml" ]; then
> >      nc -w 10 "$SUT_ADDR" 8080 > tests-junit.xml  > +    # Findout if one of the test failed
> > +    if ! grep -q '' tests-junit.xml; then
> > +        echo "ERROR: tests-junit.xml is incomplete or missing."
> > +        TEST_RESULT=1
> > +    # Only match "type=failure" to allow to "tolerable" for example.
> > +    elif grep -q ' 
> Maybe drop -q here, or add some message? Otherwise it's not obvious why it failed. See for example:
> https://gitlab.com/xen-project/people/marmarek/xen/-/jobs/10968674458
> 
> Yes, you can click "Test summary" link, but it isn't obvious by looking
> at the final part of the log. Alternatively, this can be combined with
> my "CI: list failed tests at the end of tools job" patch (already
> reviewed by Andrew), but I had an impression this series is supposed to
> be included instead of that one.

Dropping "-q" sounds good here, it mean in your pipeline example we
would have the following in the logs:
   
Which should be could enough for now.

Thanks,

-- 
Anthony PERARD


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Date: Wed, 13 Aug 2025 14:41:02 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Andrew Cooper 
Cc: xen-devel@lists.xenproject.org,
	Oleksii Kurochko ,
	Community Manager ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich , Julien Grall ,
	Stefano Stabellini 
Subject: Re: [Coverity complaint] Re: [PATCH v5] pdx: introduce a new
 compression algorithm based on region offsets
Message-ID: 
References: <20250812150624.64898-1-roger.pau@citrix.com>
 
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On Wed, Aug 13, 2025 at 12:47:37PM +0100, Andrew Cooper wrote:
> On 12/08/2025 4:06 pm, Roger Pau Monne wrote:
> > Signed-off-by: Roger Pau Monné 
> 
> Not this patch, but this is probably the best place to report it.
> 
> https://scan5.scan.coverity.com/#/project-view/30554/10426?selectedIssue=1662707
> 
> Something you did in the series made enough changes in
> pfn_pdx_compression_setup() for Coverity to start reporting an issue in
> some decade-old code.
> 
> The complaint is on line:
> 
> 277    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
> CID 1662707: (#1 of 1): Bad bit shift operation (BAD_SHIFT)
> 
> 34. large_shift: In expression 0x1000 << bottom_shift, left shifting by more than 31 bits
> has undefined behavior. The shift amount, bottom_shift, is as much as 63.
> 
> 
> The relevant part of earlier analysis seems to be the "i >=
> BITS_PER_LONG" check in the order loop, causing Coverity to think that i
> can be up to 63.

Yes, I've also got the email.  This is existing code, so the issue
wasn't introduced by the previous patches, it's probably result of
the code movement that Coverity picked it up.

I will send a patch to fix this.

Thanks, Roger.


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From: "Teddy Astie" 
Subject: =?utf-8?Q?[PATCH]=20libxl:=20Add=20virtio=20(virtio-vga)=20display=20support?=
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Cc: "Teddy Astie" , "Oleksii Kurochko" , "Community Manager" , "Anthony PERARD" , "Juergen Gross" 
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Add "virtio" vga which uses the virtio-vga device provided by upstream QEMU.
It is VGA compatible and can be enlightened with virtio-gpu drivers which are
available since Linux 4.4 and as a part of KVM Windows drivers.

Signed-off-by: Teddy Astie 
---
 CHANGELOG.md                     | 1 +
 docs/man/xl.cfg.5.pod.in         | 6 +++++-
 tools/libs/light/libxl_dm.c      | 3 +++
 tools/libs/light/libxl_types.idl | 1 +
 tools/xl/xl_parse.c              | 2 ++
 5 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe..88ff5b9a77 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -26,6 +26,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV
      capability usage is not yet supported on PVH dom0).
    - Smoke tests for the FreeBSD Xen builds in Cirrus CI.
+   - Virtio-VGA display support for HVM guests
 
  - On Arm:
     - Ability to enable stack protector
diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
index f0c920b39d..445064ff6e 100644
--- a/docs/man/xl.cfg.5.pod.in
+++ b/docs/man/xl.cfg.5.pod.in
@@ -2566,6 +2566,8 @@ default and minimum is 8 MB.
 For QXL vga, both the default and minimal are 128MB.
 If B is set less than 128MB, an error will be triggered.
 
+When using virtio, this parameter is ignored.
+
 =item B
 
 Specifies a standard VGA card with VBE (VESA BIOS Extensions) as the
@@ -2579,7 +2581,7 @@ B.
 =item B
 
 Selects the emulated video card.
-Options are: B, B, B and B.
+Options are: B, B, B, B and B.
 The default is B.
 
 In general, QXL should work with the Spice remote display protocol
@@ -2587,6 +2589,8 @@ for acceleration, and a QXL driver is necessary in the guest in that case.
 QXL can also work with the VNC protocol, but it will be like a standard
 VGA card without acceleration.
 
+virtio uses the VGA compatible variant of virtio-gpu.
+
 =item B
 
 Allow access to the display via the VNC protocol.  This enables the
diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c
index 511ec76a65..a561ba695a 100644
--- a/tools/libs/light/libxl_dm.c
+++ b/tools/libs/light/libxl_dm.c
@@ -1210,6 +1210,9 @@ static int libxl__build_device_model_args_new(libxl__gc *gc,
                 GCSPRINTF("qxl-vga,vram_size_mb=%"PRIu64",ram_size_mb=%"PRIu64,
                 (b_info->video_memkb/2/1024), (b_info->video_memkb/2/1024) ) );
             break;
+        case LIBXL_VGA_INTERFACE_TYPE_VIRTIO:
+            flexarray_append_pair(dm_args, "-device", "virtio-vga");
+            break;
         default:
             LOGD(ERROR, guest_domid, "Invalid emulated video card specified");
             return ERROR_INVAL;
diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl
index a6030a2dbd..577fd6d90d 100644
--- a/tools/libs/light/libxl_types.idl
+++ b/tools/libs/light/libxl_types.idl
@@ -238,6 +238,7 @@ libxl_vga_interface_type = Enumeration("vga_interface_type", [
     (2, "STD"),
     (3, "NONE"),
     (4, "QXL"),
+    (5, "VIRTIO"),
     ], init_val = "LIBXL_VGA_INTERFACE_TYPE_UNKNOWN")
 
 libxl_vendor_device = Enumeration("vendor_device", [
diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
index 90c9386f5b..cc68d42dca 100644
--- a/tools/xl/xl_parse.c
+++ b/tools/xl/xl_parse.c
@@ -2833,6 +2833,8 @@ skip_usbdev:
                 b_info->u.hvm.vga.kind = LIBXL_VGA_INTERFACE_TYPE_NONE;
             } else if (!strcmp(buf, "qxl")) {
                 b_info->u.hvm.vga.kind = LIBXL_VGA_INTERFACE_TYPE_QXL;
+            } else if (!strcmp(buf, "virtio")) {
+                b_info->u.hvm.vga.kind = LIBXL_VGA_INTERFACE_TYPE_VIRTIO;
             } else {
                 fprintf(stderr, "Unknown vga \"%s\" specified\n", buf);
                 exit(1);
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



From xen-devel-bounces@lists.xenproject.org Wed Aug 13 12:46:33 2025
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Date: Wed, 13 Aug 2025 14:46:25 +0200
From: Anthony PERARD 
To: Marek =?iso-8859-1?Q?Marczykowski-G=F3recki?= 
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Doug Goldstein ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH v2 3/3] CI: Workaround extra content in junit
Message-ID: 
References: <20250730152602.45436-1-anthony@xenproject.org>
 <20250730152602.45436-4-anthony@xenproject.org>
 
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On Sat, Aug 09, 2025 at 06:25:28PM +0200, Marek Marczykowski-Górecki wrote:
> On Wed, Jul 30, 2025 at 05:26:02PM +0200, Anthony PERARD wrote:
> > From: Anthony PERARD 
> > 
> > Signed-off-by: Anthony PERARD 
> 
> Is it still an issue? AFAIR similar issue was fixed together with fixing
> xml upload hanging.

It was an issue in June:
    https://lore.kernel.org/xen-devel/20250603124222.52057-9-anthony@xenproject.org/

And it still is:
    https://gitlab.com/xen-project/people/marmarek/xen/-/jobs/10969191455
    > WARNING: Found 75 too many lines in junit.

Thanks,

-- 
Anthony PERARD


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        Wed, 13 Aug 2025 05:55:53 -0700 (PDT)
From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: Roger Pau Monne ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	Stefano Stabellini 
Subject: [PATCH] pdx: cast PAGE_SIZE value ahead of shifting
Date: Wed, 13 Aug 2025 14:55:38 +0200
Message-ID: <20250813125538.78174-1-roger.pau@citrix.com>
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Coverity complains that:

277    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
 In expression 0x1000 << bottom_shift, left shifting by more than 31 bits
 has undefined behavior. The shift amount, bottom_shift, is as much as 63.

Cast PAGE_SIZE to paddr_t so it has the right width.

Reported-by: Andrew Cooper 
Coverity ID: 1662707
Fixes: bac2000063ba ('x86-64: reduce range spanned by 1:1 mapping and frame table indexes')
Signed-off-by: Roger Pau Monné 
---
 xen/common/pdx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/common/pdx.c b/xen/common/pdx.c
index 7e070ff962e8..5f54dd18f90d 100644
--- a/xen/common/pdx.c
+++ b/xen/common/pdx.c
@@ -288,7 +288,7 @@ bool __init pfn_pdx_compression_setup(paddr_t base)
 
     pfn_pdx_hole_shift  = hole_shift;
     pfn_pdx_bottom_mask = (1UL << bottom_shift) - 1;
-    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
+    ma_va_bottom_mask   = ((paddr_t)PAGE_SIZE << bottom_shift) - 1;
     pfn_hole_mask       = ((1UL << hole_shift) - 1) << bottom_shift;
     pfn_top_mask        = ~(pfn_pdx_bottom_mask | pfn_hole_mask);
     ma_top_mask         = pfn_top_mask << PAGE_SHIFT;
-- 
2.49.0



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Subject: Re: [PATCH] pdx: cast PAGE_SIZE value ahead of shifting
To: Roger Pau Monne , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , Stefano Stabellini 
References: <20250813125538.78174-1-roger.pau@citrix.com>
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On 13/08/2025 1:55 pm, Roger Pau Monne wrote:
> Coverity complains that:
>
> 277    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;

I'd perhaps drop this line from the commit message.  The sentence below
is fine, and there's only a single hunk so it's obvious what is being
referred to.

>  In expression 0x1000 << bottom_shift, left shifting by more than 31 bits
>  has undefined behavior. The shift amount, bottom_shift, is as much as 63.
>
> Cast PAGE_SIZE to paddr_t so it has the right width.
>
> Reported-by: Andrew Cooper 
> Coverity ID: 1662707
> Fixes: bac2000063ba ('x86-64: reduce range spanned by 1:1 mapping and frame table indexes')
> Signed-off-by: Roger Pau Monné 

Formatting aside, Reviewed-by: Andrew Cooper 


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Date:	Wed, 13 Aug 2025 16:27:11 +0200
From:	Daniel Kiper 
To:	Aaron Rainbolt 
Cc:	grub-devel@gnu.org, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 2/2] kern/xen: Add Xen command line parsing
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On Tue, Aug 12, 2025 at 06:55:15PM -0500, Aaron Rainbolt wrote:
> On Tue, 12 Aug 2025 19:02:11 +0200 Daniel Kiper  wrote:
> > On Mon, Aug 04, 2025 at 11:50:09PM -0500, Aaron Rainbolt wrote:
> > > Xen traditionally allows customizing guest behavior by passing
> > > arguments to the VM kernel via the kernel command line. This is no
> > > longer possible when using GRUB with Xen, as the kernel command
> > > line is decided by the GRUB configuration file within the guest,
> > > not data passed to the guest by Xen.
> > >
> > > To work around this limitation, enable GRUB to parse a command line
> > > passed to it by Xen, and expose data from the command line to the
> > > GRUB configuration as environment variables. These variables can be
> > > used in the GRUB configuration for any desired purpose, such as
> > > extending the kernel command line passed to the guest. The command
> > > line format is inspired by the Linux kernel's command line format.
> > >
> > > To reduce the risk of misuse, abuse, or accidents in production, the
> > > command line will only be parsed if it consists entirely of 7-bit
> > > ASCII characters, only alphabetical characters and underscores are
> > > permitted in variable names, and all variable names must start with
> > > the string "xen_grub_env_". This also allows room for expanding the
> > > command line arguments accepted by GRUB in the future, should other
> > > arguments end up becoming desirable in the future.
> > >
> > > Signed-off-by: Aaron Rainbolt 

[...]

> > > diff --git a/grub-core/kern/i386/xen/pvh.c b/grub-core/kern/i386/xen/pvh.c index 91fbca8..a8988d2 100644
> > > --- a/grub-core/kern/i386/xen/pvh.c
> > > +++ b/grub-core/kern/i386/xen/pvh.c
> > > @@ -321,6 +321,8 @@ void
> > >  grub_xen_setup_pvh (void)
> > >  {
> > >    grub_addr_t par;
> > > +  const char *xen_cmdline;
> > > +  int i;
> > >
> > >    grub_xen_cpuid_base ();
> > >    grub_xen_setup_hypercall_page ();
> > > @@ -352,6 +354,27 @@ grub_xen_setup_pvh (void)
> > >    grub_xen_mm_init_regions ();
> > >
> > >    grub_rsdp_addr = pvh_start_info->rsdp_paddr;
> > > +
> > > +  xen_cmdline = (const char *) pvh_start_info->cmdline_paddr;
> > > +  for (i = 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++)
> > > +    {
> > > +      if (xen_cmdline[i] == '\0')
> >
> > This code still does not make a lot of sense for me. You have NUL
> > check in grub_parse_xen_cmdline(). So, you duplicate the check here...
> >
> > I would just fire grub_strncpy() here and forget...
>
> I guess it depends on how you view grub_xen_start_page_addr->cmd_line's
> semantics. In my mind, cmd_line is a NUL-terminated string, always. If
> you boot in PV mode, Xen ensures it's a NUL-terminated string, so it's
> reasonable for code in GRUB to assume it will be one. If you boot in
> PVH mode, it starts out initialized to all zeros which is technically a
> NUL-terminated string, and the code that exists here ensures that if we
> copy the kernel command line to cmd_line, it will still be a
> NUL-terminated string. If we use a "bare" grub_strncpy() here, then if
> someone passes a kernel command line larger than
> GRUB_XEN_MAX_GUEST_CMDLINE - 1, cmd_line will end up not being
> NUL-terminated anymore, and any code added to GRUB in the future that
> assumes it is a NUL-terminated string may buffer overflow.
>
> One could argue "let's keep the NUL check here and remove it from
> grub_parse_xen_cmdline()", but that doesn't work either because we only
> get to control the contents of cmd_line if we boot in PVH mode. If
> instead we boot in PV mode, cmd_line is initialized by Xen itself. GRUB
> receives a pre-populated and ready-to-use start_info struct directly
> from the hypervisor in this scenario. Xen is supposed to ensure that
> start_info is always NUL-terminated, but if there's ever a bug in Xen
> that breaks that assumption, that could result in bad things happening,
> the same as if we didn't do the NUL check in grub_xen_setup_pvh(). Now
> of course there's nothing we can do about Xen possibly being buggy (if
> it gives us a GRUB_XEN_MAX_GUEST_CMDLINE-long buffer with no NUL
> terminator, too bad), but we can at least make sure that we're ready
> for that eventuality. That's why I like having both NUL checks - we're
> ready for if Xen does things wrong, and any future code that isn't
> ready for that eventuality will still work if things go wrong, at least
> in PVH mode.

OK, it looks like this explanation, in shortened form, should land
around this code... Or not... Please look below...

> (Arguably any new code that depends on cmd_line *should* check it for a
> NUL terminator. But I don't want to assume that all new code *will* do
> so.)
>
> > > +        {
> > > +          grub_strncpy ((char *)
> > > grub_xen_start_page_addr->cmd_line,
> > > +			(char *) pvh_start_info->cmdline_paddr,
> > > +			GRUB_XEN_MAX_GUEST_CMDLINE);
> > > +
> > > +          if
> > > (grub_xen_start_page_addr->cmd_line[GRUB_XEN_MAX_GUEST_CMDLINE - 1]
> > > != '\0')
> >
> > If you convince me this code is still needed then I am afraid that
> > this is not what you meant here...
>
> grub_strncpy doesn't just NUL-terminate the command line, it also fills
> the entire remainder of the buffer with NUL characters. Therefore if

I am afraid we are looking at different grub_strncpy() functions...

> grub_strncpy NUL-terminated the copied string, the last character of
> the buffer will always be NUL. This is a redundant check since the code
> above goes to great lengths to avoid ever putting anything
> non-NUL-terminated into the buffer, but I was under the impression you
> wanted the check added just in case. I'm happy to remove it if it's not
> desirable.

I think we misunderstood each other. This code is redundant now...

[...]

> > > +is_key_safe (char *key, grub_size_t len)
> > > +{
> > > +  grub_size_t i;
> > > +
> > > +  for (i = 0; i < len; i++)
> > > +    {
> > > +      if (! (grub_isalpha (key[i]) || key[i] == '_'))
> >
> > Please drop space after "!"...
>
> Will change.
>
> > > +        return false;
> > > +    }
> >
> > You can drop curly braces from here...
>
> Will change.
>
> (I initially kept this written the way it was though because the GNU
> coding standards seemed to indicate I should keep the braces. "When
> you have an if-else statement nested in another if statement, always
> put braces around the if-else." [1] This isn't a nested if, but it's an
> if within a for which is very similar.)
>
> Is there any recommended coding style documentation I should be looking
> at other than the GNU coding standards and the GRUB coding style
> guidelines? It seems I'm making an awful lot of style mistakes and
> would like to avoid that going forward.

Yes, it is but sadly it is not fully/properly/.. documented [1]...

[...]

> > > +  for (i = 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++)
> > > +    {
> > > +      if (cmdline[i] == '\0')
> > > +        {
> > > +          cmdline_valid = true;
> > > +          break;
> > > +        }
> > > +    }
> > > +
> > > +  if (cmdline_valid == false)
> > > +    {
> > > +      grub_error (GRUB_ERR_BAD_ARGUMENT,
> > > +		  "command line from Xen is not NUL-terminated");
> > > +      grub_print_error ();
> >
> > grub_fatal()?
>
> That would probably be a bad idea here. We use (or, at least, will use)
> grub_fatal() in grub_xen_setup_pvh() because if grub_strncpy() doesn't
> NUL-terminate the string it copies, it indicates a bug in GRUB (either
> in grub_strncpy, or more likely in the nearby NUL-checking code). On
> the other hand, cmdline_valid may equal false if we boot in PV mode and
> Xen incorrectly hands us a non-NUL-terminated string. That's bad and
> prevents us from parsing the command line safely, but I'd argue it
> shouldn't entirely block boot. (Then again, maybe if it does block
> boot, that will make this kind of theoretical Xen bug be much more
> noticeable and help it get fixed quicker. If you'd prefer that we bail
> out entirely here, I'm happy to change it.)

As I said earlier, I would simply call grub_strncpy() in grub_xen_setup_pvh()
without additional NUL-check there and fail if non-NUL-terminated string
is detected here...

> > > +      goto cleanup_main;
> > > +    }
> > > +
> > > +  cmdline_len = grub_strlen (cmdline);
> > > +  for (i = 0; i < cmdline_len; i++)
> > > +    {
> > > +      current_char = cmdline[i];
> > > +
> > > +      /*
> > > +       * If the previous character was a backslash, append the current
> > > +       * character to the word verbatim
> > > +       */
> > > +      if (splitter_state & SPLITTER_HIT_BACKSLASH)
> > > +        {
> > > +          splitter_state &= ~SPLITTER_HIT_BACKSLASH;
> > > +          if (append_char_to_word (s, current_char, false) == false)
> > > +            goto cleanup_main;
> > > +          continue;
> > > +        }
> > > +
> > > +      switch (current_char)
> > > +        {
> > > +        case '\\':
> > > +          /* Backslashes escape arbitrary characters. */
> > > +          splitter_state |= SPLITTER_HIT_BACKSLASH;
> > > +          continue;
> > > +
> > > +        case '\'':
> > > +          /*
> > > +           * Single quotes suppress word splitting and double quoting until
> > > +           * the next single quote is encountered.
> > > +           */
> > > +          if (splitter_state & SPLITTER_IN_DOUBLE_QUOTES)
> > > +            {
> > > +              if (append_char_to_word (s, current_char, false) == false)
> > > +                goto cleanup_main;
> > > +              continue;
> > > +            }
> > > +
> > > +          splitter_state ^= SPLITTER_IN_SINGLE_QUOTES;
> > > +          continue;
> > > +
> > > +        case '"':
> > > +          /*
> > > +           * Double quotes suppress word splitting and single quoting until
> > > +           * the next double quote is encountered.
> > > +           */
> > > +          if (splitter_state & SPLITTER_IN_SINGLE_QUOTES)
> > > +            {
> > > +              if (append_char_to_word (s, current_char, false) == false)
> > > +                goto cleanup_main;
> > > +              continue;
> > > +            }
> > > +
> > > +          splitter_state ^= SPLITTER_IN_DOUBLE_QUOTES;
> > > +          continue;
> > > +
> > > +        case ' ':
> > > +          /* Spaces separate words in the command line from each other. */
> > > +          if (splitter_state & SPLITTER_IN_SINGLE_QUOTES ||
> > > +              splitter_state & SPLITTER_IN_DOUBLE_QUOTES)
> > > +            {
> > > +              if (append_char_to_word (s, current_char, false) == false)
> > > +                goto cleanup_main;
> > > +              continue;
> > > +            }
> > > +
> > > +          if (append_word_to_list (s) == false)
> > > +            goto cleanup_main;
> >
> > I think this is not fully correct. You should not run
> > append_word_to_list() until the closing quote. So, here you should
> > have "else" for the first "if", i.e., "if (splitter_state & ..." and
> > call append_word_to_list() for closing \" and \' above.
>
> What closing quote? If we're in quotes, the `if (splitter_state &...`
> block will run. That block runs `continue`, restarting the loop before
> we get to the `append_word_to_list (s)` call. If we hit a closing
> quote, either the `case '\''` or the `case '"'` block will be
> triggered, changing the splitter's state so that it knows it's no
> longer within a quote block, and then the next space (or the end of the
> string) will cause `append_word_to_list()` to be called, adding the
> quoted word to the list. Even if this `continue` changes to a `break`
> like suggested below, the logic and control flow will remain the same.
>
> Calling `append_word_to_list()` for closing quotes would break the
> splitter. I'm trying to implement splitting behavior similar to Bash or
> GRUB's configuration language, both of which parse
> `xen_grub_env_var="abc def"ghi` into the variable `xen_grub_env_var`
> with the value `abc defghi`. If we split on closing quotes too, the
> input above will be parsed into two words, `xen_grub_env_var=abc def`
> and an extra word `ghi`, resulting in the environment variable
> `xen_grub_env_var` being set to `abc def` and the `ghi` being lost
> entirely. One could argue that this is reasonable behavior, but it
> isn't consistent with the other splitting behavior in GRUB.

OK, makes sense for me... Maybe you should mention somewhere in the code
current splitter behavior...

Daniel

[1] https://www.gnu.org/software/grub/manual/grub-dev/grub-dev.html#Coding-style


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On 2025-08-12 15:00, Jason Andryuk wrote:
> VIRQs come in 3 flavors, per-VPU, per-domain, and global.  The existing
> tracking of VIRQs is handled by per-cpu variables virq_to_irq.
> 
> The issue is that bind_virq_to_irq() sets the per_cpu virq_to_irq at
> registration time - typically CPU 0.  Later, the interrupt can migrate,
> and info->cpu is updated.  When calling unbind_from_irq(), the per-cpu
> virq_to_irq is cleared for a different cpu.  If bind_virq_to_irq() is
> called again with CPU 0, the stale irq is returned.
> 
> Change the virq_to_irq tracking to use CPU 0 for per-domain and global
> VIRQs.  As there can be at most one of each, there is no need for
> per-vcpu tracking.  Also, per-domain and global VIRQs need to be
> registered on CPU 0 and can later move, so this matches the expectation.
> 
> Fixes: e46cdb66c8fc ("xen: event channels")
> Cc: stable@vger.kernel.org
> Signed-off-by: Jason Andryuk 
> ---
> Fixes is the introduction of the virq_to_irq per-cpu array.
> 
> This was found with the out-of-tree argo driver during suspend/resume.
> On suspend, the per-domain VIRQ_ARGO is unbound.  On resume, the driver
> attempts to bind VIRQ_ARGO.  The stale irq is returned, but the
> WARN_ON(info == NULL || info->type != IRQT_VIRQ) in bind_virq_to_irq()
> triggers for NULL info.  The bind fails and execution continues with the
> driver trying to clean up by unbinding.  This eventually faults over the
> NULL info.
> ---
>   drivers/xen/events/events_base.c | 17 ++++++++++++++++-
>   1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
> index 41309d38f78c..a27e4d7f061e 100644
> --- a/drivers/xen/events/events_base.c
> +++ b/drivers/xen/events/events_base.c
> @@ -159,7 +159,19 @@ static DEFINE_MUTEX(irq_mapping_update_lock);
>   
>   static LIST_HEAD(xen_irq_list_head);
>   
> -/* IRQ <-> VIRQ mapping. */
> +static bool is_per_vcpu_virq(int virq) {
> +	switch (virq) {
> +	case VIRQ_TIMER:
> +	case VIRQ_DEBUG:
> +	case VIRQ_XENOPROF:
> +	case VIRQ_XENPMU:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +/* IRQ <-> VIRQ mapping.  Global/Domain virqs are tracked in cpu 0.  */
>   static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
>   
>   /* IRQ <-> IPI mapping */
> @@ -974,6 +986,9 @@ static void __unbind_from_irq(struct irq_info *info, unsigned int irq)
>   
>   		switch (info->type) {
>   		case IRQT_VIRQ:
> +			if (!is_per_vcpu_virq(virq_from_irq(info)))
> +				cpu = 0;
> +
>   			per_cpu(virq_to_irq, cpu)[virq_from_irq(info)] = -1;
>   			break;
>   		case IRQT_IPI:

Thinking about it a little more, bind_virq_to_irq() should ensure cpu == 
0 for per-domain and global VIRQs to ensure the property holds.  Also 
virq_to_irq accesses should go through wrappers to ensure all accesses 
are handled consistently.

I'll send a v2.

Regards,
Jason


From xen-devel-bounces@lists.xenproject.org Wed Aug 13 15:07:29 2025
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Date: Wed, 13 Aug 2025 18:07:18 +0300
From: Leon Romanovsky 
To: Jason Gunthorpe 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 08/16] kmsan: convert kmsan_handle_dma to use physical
 addresses
Message-ID: <20250813150718.GB310013@unreal>
References: 
 <5b40377b621e49ff4107fa10646c828ccc94e53e.1754292567.git.leon@kernel.org>
 <20250807122115.GH184255@nvidia.com>
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On Thu, Aug 07, 2025 at 09:21:15AM -0300, Jason Gunthorpe wrote:
> On Mon, Aug 04, 2025 at 03:42:42PM +0300, Leon Romanovsky wrote:
> > From: Leon Romanovsky 
> > 
> > Convert the KMSAN DMA handling function from page-based to physical
> > address-based interface.
> > 
> > The refactoring renames kmsan_handle_dma() parameters from accepting
> > (struct page *page, size_t offset, size_t size) to (phys_addr_t phys,
> > size_t size). A PFN_VALID check is added to prevent KMSAN operations
> > on non-page memory, preventing from non struct page backed address,
> > 
> > As part of this change, support for highmem addresses is implemented
> > using kmap_local_page() to handle both lowmem and highmem regions
> > properly. All callers throughout the codebase are updated to use the
> > new phys_addr_t based interface.
> 
> Use the function Matthew pointed at kmap_local_pfn()
> 
> Maybe introduce the kmap_local_phys() he suggested too.

At this point it gives nothing.

> 
> >  /* Helper function to handle DMA data transfers. */
> > -void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
> > +void kmsan_handle_dma(phys_addr_t phys, size_t size,
> >  		      enum dma_data_direction dir)
> >  {
> >  	u64 page_offset, to_go, addr;
> > +	struct page *page;
> > +	void *kaddr;
> >  
> > -	if (PageHighMem(page))
> > +	if (!pfn_valid(PHYS_PFN(phys)))
> >  		return;
> 
> Not needed, the caller must pass in a phys that is kmap
> compatible. Maybe just leave a comment. FWIW today this is also not
> checking for P2P or DEVICE non-kmap struct pages either, so it should
> be fine without checks.

It is not true as we will call to kmsan_handle_dma() unconditionally in
dma_map_phys(). The reason to it is that kmsan_handle_dma() is guarded
with debug kconfig options and cost of pfn_valid() can be accommodated
in that case. It gives more clean DMA code.

   155 dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
   156                 enum dma_data_direction dir, unsigned long attrs)
   157 {
   <...>
   187
   188         kmsan_handle_dma(phys, size, dir);
   189         trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
   190         debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
   191
   192         return addr;
   193 }
   194 EXPORT_SYMBOL_GPL(dma_map_phys);

So let's keep this patch as is.

Thanks


From xen-devel-bounces@lists.xenproject.org Wed Aug 13 15:17:08 2025
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Date: Wed, 13 Aug 2025 17:16:58 +0200
From: Anthony PERARD 
To: Andrew Cooper 
Cc: Xen-devel ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich , Julien Grall ,
	Roger Pau =?iso-8859-1?Q?Monn=E9?= ,
	Stefano Stabellini ,
	Shawn Anastasio ,
	Oleksii Kurochko ,
	Doug Goldstein ,
	Marek =?iso-8859-1?Q?Marczykowski-G=F3recki?= ,
	Victor Lira 
Subject: Re: [PATCH 2/5] CI: Update ppc64 to use Debian Trixie
Message-ID: 
References: <20250809221206.1260861-1-andrew.cooper3@citrix.com>
 <20250809221206.1260861-3-andrew.cooper3@citrix.com>
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On Sat, Aug 09, 2025 at 11:12:03PM +0100, Andrew Cooper wrote:
> diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml
> index ab5211f77e5e..3fe539dc5683 100644
> --- a/automation/gitlab-ci/build.yaml
> +++ b/automation/gitlab-ci/build.yaml
> @@ -319,10 +319,10 @@ debian-12-x86_64-clang-debug:
>    variables:
>      CONTAINER: debian:12-x86_64
>  
> -debian-12-ppc64le-gcc-debug:
> +debian-13-ppc64le-gcc-debug:
>    extends: .gcc-ppc64le-cross-build-debug
>    variables:
> -    CONTAINER: debian:12-ppc64le
> +    CONTAINER: debian:13-ppc64le
>      KBUILD_DEFCONFIG: ppc64_defconfig
>      HYPERVISOR_ONLY: y
>      EXTRA_XEN_CONFIG: |
> @@ -705,6 +705,20 @@ debian-12-ppc64le-gcc:
>      KBUILD_DEFCONFIG: ppc64_defconfig
>      HYPERVISOR_ONLY: y
>  
> +debian-12-ppc64le-gcc-debug:
> +  extends: .gcc-ppc64le-cross-build-debug
> +  variables:
> +    CONTAINER: debian:12-ppc64le
> +    KBUILD_DEFCONFIG: ppc64_defconfig
> +    HYPERVISOR_ONLY: y
> +

Why did you remove the EXTRA_XEN_CONFIG from this job? Currently, the
job is setup as:

    debian-12-ppc64le-gcc-debug:
      extends: .gcc-ppc64le-cross-build-debug
      variables:
        CONTAINER: debian:12-ppc64le
        KBUILD_DEFCONFIG: ppc64_defconfig
        HYPERVISOR_ONLY: y
        EXTRA_XEN_CONFIG: |
          CONFIG_UBSAN=y
          CONFIG_UBSAN_FATAL=y

Thanks,

-- 
Anthony PERARD


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Date: Wed, 13 Aug 2025 18:37:28 +0300
From: Leon Romanovsky 
To: Jason Gunthorpe 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 16/16] nvme-pci: unmap MMIO pages with appropriate
 interface
Message-ID: <20250813153728.GC310013@unreal>
References: 
 <5b0131f82a3d14acaa85f0d1dd608d2913af84e2.1754292567.git.leon@kernel.org>
 <20250807134533.GM184255@nvidia.com>
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In-Reply-To: <20250807134533.GM184255@nvidia.com>

On Thu, Aug 07, 2025 at 10:45:33AM -0300, Jason Gunthorpe wrote:
> On Mon, Aug 04, 2025 at 03:42:50PM +0300, Leon Romanovsky wrote:
> > From: Leon Romanovsky 
> > 
> > Block layer maps MMIO memory through dma_map_phys() interface
> > with help of DMA_ATTR_MMIO attribute. There is a need to unmap
> > that memory with the appropriate unmap function.
> 
> Be specific, AFIACT the issue is that on dma_ops platforms the map
> will call ops->map_resource for ATTR_MMIO so we must have the unmap
> call ops->unmap_resournce
> 
> Maybe these patches should be swapped then, as adding ATTR_MMIO seems
> like it created this issue?

The best variant will be to squash previous patch "block-dma: properly
take MMIO path", but I don't want to mix them as they for different
kernel areas.

Thanks

> 
> Jason
> 


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Date: Wed, 13 Aug 2025 17:42:48 +0200
From: Anthony PERARD 
To: Andrew Cooper 
Cc: xen-devel@lists.xenproject.org,
	Anthony PERARD ,
	Juergen Gross 
Subject: Re: [XEN PATCH 04/11] tools/configure: Introduce deps on json-c lib
 for libxl
Message-ID: 
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-5-anthony@xenproject.org>
 <5de6ae46-8398-46ab-b79a-df45358c5c30@citrix.com>
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On Mon, Aug 11, 2025 at 11:48:19AM +0100, Andrew Cooper wrote:
> On 08/08/2025 3:55 pm, Anthony PERARD wrote:
> >  xl: $(XL_OBJS)
> > -	$(CC) $(LDFLAGS) -o $@ $(XL_OBJS) $(LDLIBS_libxenutil) $(LDLIBS_libxenlight) $(LDLIBS_libxentoollog) $(LDLIBS_libxenstore) -lyajl $(APPEND_LDFLAGS)
> > +	$(CC) $(LDFLAGS) -o $@ $(XL_OBJS) $(LDLIBS_libxenutil) $(LDLIBS_libxenlight) $(LDLIBS_libxentoollog) $(LDLIBS_libxenstore) $(YAJL_LIBS) $(LIBJSONC_LIBS) $(APPEND_LDFLAGS)
> >  
> >  .PHONY: install
> >  install: all
> 
> Specifying both isn't entirely great when one is supposed to be empty.
> 
> Could we not have XEN_JSON_LIB(s) which is set to either $YAJL_LIBS or
> $LIBJSONC_LIBS as appropriate?

Yes, that sounds good.

Thanks,

-- 
Anthony PERARD


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Misra Rule 11.1 states: "Conversions shall not be performed between a
pointer to a function and any other type."

The violation occurs in the macro:
    __typeof__(**(ptr)) *const o_ =3D (o);                                \
    __typeof__(**(ptr)) *n_ =3D (n);                                      \
    ((__typeof__(*(ptr)))__cmpxchg(ptr, (unsigned long)o_,              \
                                   (unsigned long)n_, sizeof(*(ptr)))); \
})
when it is used for handling function pointers of type:
typedef void (*)(struct vcpu *, unsigned int).
The issue happens because the '__cmpxchg()' function returns an 'unsigned
long', which is then converted back into a function pointer, causing a
violation of Rule 11.1. In this particular usage, the return value of the
macro 'cmpxchgptr()' is not required. To address the violation, the macro
has been replaced to discard the return value of '__cmpxchg()', preventing
the conversion.

Signed-off-by: Dmytro Prokopchuk 
---
Probably separate macro is too much for this single case.

And the following will be enought:
__cmpxchg(&xen_consumers[i], (unsigned long)NULL, (unsigned long)fn, sizeof=
(*(&xen_consumers[i])));
---
 xen/common/event_channel.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index 67700b050a..2094338b28 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -93,6 +93,17 @@ static void cf_check default_xen_notification_fn(
         vcpu_wake(v);
 }
=20
+/*
+ * A slightly more updated variant of cmpxchgptr() where old value
+ * is not returned.
+ */
+#define cmpxchgptr_noret(ptr, o, n) ({                  \
+    __typeof__(**(ptr)) *const o_ =3D (o);                \
+    __typeof__(**(ptr)) *n_ =3D (n);                      \
+    (void)__cmpxchg(ptr, (unsigned long)o_,             \
+                    (unsigned long)n_, sizeof(*(ptr))); \
+})
+
 /*
  * Given a notification function, return the value to stash in
  * the evtchn->xen_consumer field.
@@ -106,9 +117,9 @@ static uint8_t get_xen_consumer(xen_event_channel_notif=
ication_t fn)
=20
     for ( i =3D 0; i < ARRAY_SIZE(xen_consumers); i++ )
     {
-        /* Use cmpxchgptr() in lieu of a global lock. */
+        /* Use cmpxchgptr_noret() in lieu of a global lock. */
         if ( xen_consumers[i] =3D=3D NULL )
-            cmpxchgptr(&xen_consumers[i], NULL, fn);
+            cmpxchgptr_noret(&xen_consumers[i], NULL, fn);
         if ( xen_consumers[i] =3D=3D fn )
             break;
     }
--=20
2.43.0


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Nicola Vetrini
	, Doug Goldstein , Stefano
 Stabellini , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Bertrand Marquis ,
	Volodymyr Babchuk 
Subject: [RFC PATCH] misra: allow conversion from unsigned long to function
 pointer
Thread-Topic: [RFC PATCH] misra: allow conversion from unsigned long to
 function pointer
Thread-Index: AQHcDH/2fJv669AP80eUn9D9WGE5wg==
Date: Wed, 13 Aug 2025 18:27:45 +0000
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...

from `vaddr_t' (that is `unsigned long') to `switch_ttbr_fn*' (that is `voi=
d(*)(unsigned long)')

Signed-off-by: Dmytro Prokopchuk 
---
This is just a RFC patch.
The commit message is not important at this stage.

I am seeking comments regarding this case.

Thanks.
---
 automation/eclair_analysis/ECLAIR/deviations.ecl |  8 ++++++++
 docs/misra/deviations.rst                        | 10 ++++++++++
 docs/misra/rules.rst                             |  8 +++++++-
 xen/arch/arm/arm64/mmu/mm.c                      |  2 ++
 4 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index ebce1ceab9..f9fd6076b7 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -365,6 +365,14 @@ constant expressions are required.\""
 }
 -doc_end
=20
+-doc_begin=3D"The conversion from unsigned long to a function pointer does=
 not lose any information, provided that the source type has enough bits to=
 restore it."
+-config=3DMC3A2.R11.1,casts+=3D{safe,
+  "from(type(canonical(builtin(unsigned long))))
+   &&to(type(canonical(__function_pointer_types)))
+   &&relation(definitely_preserves_value)"
+}
+-doc_end
+
 -doc_begin=3D"The conversion from a function pointer to a boolean has a we=
ll-known semantics that do not lead to unexpected behaviour."
 -config=3DMC3A2.R11.1,casts+=3D{safe,
   "from(type(canonical(__function_pointer_types)))
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 3c46a1e47a..27848602f6 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -348,6 +348,16 @@ Deviations related to MISRA C:2012 Rules:
        to store it.
      - Tagged as `safe` for ECLAIR.
=20
+   * - R11.1
+     - The conversion from unsigned long to a function pointer does not lo=
se any
+       information or violate type safety assumptions if the unsigned long=
 type
+       is guaranteed to be at least as large as a function pointer. This e=
nsures
+       that the function pointer address can be fully represented without
+       truncation or corruption. Macro BUILD_BUG_ON can be integrated into=
 the
+       build system to confirm that 'sizeof(unsigned long) >=3D sizeof(voi=
d (*)())'
+       on all target platforms.
+     - Tagged as `safe` for ECLAIR.
+
    * - R11.1
      - The conversion from a function pointer to a boolean has a well-know=
n
        semantics that do not lead to unexpected behaviour.
diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
index 6812eb7e8a..8b97ecf3f4 100644
--- a/docs/misra/rules.rst
+++ b/docs/misra/rules.rst
@@ -414,7 +414,13 @@ maintainers if you want to suggest a change.
      - All conversions to integer types are permitted if the destination
        type has enough bits to hold the entire value. Conversions to bool
        and void* are permitted. Conversions from 'void noreturn (*)(...)'
-       to 'void (*)(...)' are permitted.
+       to 'void (*)(...)' are permitted. Conversions from unsigned long to
+       function pointer are permitted if the unsigned long type has a size
+       and representation sufficient to store the entire function pointer
+       value without truncation or corruption. Example::
+
+           unsigned long func_addr =3D (unsigned long)&some_function;
+           void (*restored_func)(void) =3D (void (*)(void))func_addr;
=20
    * - `Rule 11.2 `_
      - Required
diff --git a/xen/arch/arm/arm64/mmu/mm.c b/xen/arch/arm/arm64/mmu/mm.c
index 3e64be6ae6..998d52c162 100644
--- a/xen/arch/arm/arm64/mmu/mm.c
+++ b/xen/arch/arm/arm64/mmu/mm.c
@@ -150,6 +150,7 @@ void __init relocate_and_switch_ttbr(uint64_t ttbr)
     vaddr_t id_addr =3D virt_to_maddr(relocate_xen);
     relocate_xen_fn *fn =3D (relocate_xen_fn *)id_addr;
     lpae_t pte;
+    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
=20
     /* Enable the identity mapping in the boot page tables */
     update_identity_mapping(true);
@@ -178,6 +179,7 @@ void __init switch_ttbr(uint64_t ttbr)
     vaddr_t id_addr =3D virt_to_maddr(switch_ttbr_id);
     switch_ttbr_fn *fn =3D (switch_ttbr_fn *)id_addr;
     lpae_t pte;
+    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
=20
     /* Enable the identity mapping in the boot page tables */
     update_identity_mapping(true);
--=20
2.43.0


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From: nicola.vetrini@gmail.com
To: xen-devel@lists.xenproject.org
Cc: Nicola Vetrini ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	"Daniel P. Smith" ,
	=?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
Subject: [XEN PATCH 0/3] Drop alternative definitions for unsupported GCCs
Date: Wed, 13 Aug 2025 21:12:47 +0200
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From: Nicola Vetrini 

Similar to e4a042062787, drop alternative defines for older GCC versions

Nicola Vetrini (3):
  xen/compiler: drop alternative unreachable() definition for older GCC
  xen/macros: Drop alternative definition of BUILD_BUG_ON(_ZERO)? for
    old GCC
  xen/efi: efibind: Drop alternative define for old GCC versions

 xen/arch/x86/include/asm/x86_64/efibind.h | 4 +---
 xen/include/xen/compiler.h                | 4 ----
 xen/include/xen/macros.h                  | 8 --------
 3 files changed, 1 insertion(+), 15 deletions(-)

-- 
2.43.0



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From: nicola.vetrini@gmail.com
To: xen-devel@lists.xenproject.org
Cc: Nicola Vetrini ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini 
Subject: [XEN PATCH 1/3] xen/compiler: drop alternative unreachable() definition for older GCC
Date: Wed, 13 Aug 2025 21:12:48 +0200
Message-ID: <9215845f364527203efaea9dd1019cd1e3c1768b.1755111932.git.nicola.vetrini@bugseng.com>
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From: Nicola Vetrini 

The GCC baseline version is 5.1, which supports __builtin_unreachable(),
therefore the alternative definition can be dropped

Signed-off-by: Nicola Vetrini 
---
Mentioned in https://gitlab.com/xen-project/xen/-/issues/201
---
 xen/include/xen/compiler.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
index 735c844d2d15..88bf26bc5109 100644
--- a/xen/include/xen/compiler.h
+++ b/xen/include/xen/compiler.h
@@ -47,11 +47,7 @@
 # define cf_check
 #endif
 
-#if (!defined(__clang__) && (__GNUC__ == 4) && (__GNUC_MINOR__ < 5))
-#define unreachable() do {} while (1)
-#else
 #define unreachable() __builtin_unreachable()
-#endif
 
 /*
  * Compilers estimate the size of an asm() block for inlining purposes.
-- 
2.43.0



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From: nicola.vetrini@gmail.com
To: xen-devel@lists.xenproject.org
Cc: Nicola Vetrini ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini 
Subject: [XEN PATCH 2/3] xen/macros: Drop alternative definition of BUILD_BUG_ON(_ZERO)? for old GCC
Date: Wed, 13 Aug 2025 21:12:49 +0200
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From: Nicola Vetrini 

The toolchain baseline for GCC is 5.1, which supports _Static_assert
in c99 mode

No functional change.

Signed-off-by: Nicola Vetrini 
---
Mentioned in https://gitlab.com/xen-project/xen/-/issues/201
---
 xen/include/xen/macros.h | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/xen/include/xen/macros.h b/xen/include/xen/macros.h
index cd528fbdb127..f9ccde86fb23 100644
--- a/xen/include/xen/macros.h
+++ b/xen/include/xen/macros.h
@@ -40,9 +40,6 @@
 
 #ifndef __ASSEMBLY__
 
-/* All clang versions supported by Xen have _Static_assert. */
-#if defined(__clang__) || \
-    (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6))
 /* Force a compilation error if condition is true */
 #define BUILD_BUG_ON(cond) ({ _Static_assert(!(cond), "!(" #cond ")"); })
 
@@ -54,11 +51,6 @@
  */
 #define BUILD_BUG_ON_ZERO(cond) \
     (sizeof(struct { char c; _Static_assert(!(cond), "!(" #cond ")"); }) & 0)
-#else
-#define BUILD_BUG_ON_ZERO(cond) \
-    (sizeof(struct { unsigned u : !(cond); }) & 0)
-#define BUILD_BUG_ON(cond) ((void)BUILD_BUG_ON_ZERO(cond))
-#endif
 
 /*
  * Force a compilation error.  This is for code which, in the normal case,
-- 
2.43.0



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From: nicola.vetrini@gmail.com
To: xen-devel@lists.xenproject.org
Cc: Nicola Vetrini ,
	"Daniel P. Smith" ,
	=?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Jan Beulich ,
	Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [XEN PATCH 3/3] xen/efi: efibind: Drop alternative define for old GCC versions
Date: Wed, 13 Aug 2025 21:12:50 +0200
Message-ID: <4140895d7382e1e1d84b5f3988b497a7edd67034.1755111932.git.nicola.vetrini@bugseng.com>
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From: Nicola Vetrini 

Since the toolchain baseline for GCC is 5.1, there is no need for
this case.

Signed-off-by: Nicola Vetrini 
---
Mentioned in https://gitlab.com/xen-project/xen/-/issues/201
---
 xen/arch/x86/include/asm/x86_64/efibind.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/xen/arch/x86/include/asm/x86_64/efibind.h b/xen/arch/x86/include/asm/x86_64/efibind.h
index b29342c61cac..d71b9324a6bb 100644
--- a/xen/arch/x86/include/asm/x86_64/efibind.h
+++ b/xen/arch/x86/include/asm/x86_64/efibind.h
@@ -173,10 +173,8 @@ typedef uint64_t   UINTN;
 #ifndef EFIAPI                  // Forces EFI calling conventions reguardless of compiler options
     #ifdef _MSC_EXTENSIONS
         #define EFIAPI __cdecl  // Force C calling convention for Microsoft C compiler
-    #elif __clang__ || __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
-        #define EFIAPI __attribute__((__ms_abi__))  // Force Microsoft ABI
     #else
-        #define EFIAPI          // Substitute expression to force C calling convention
+        #define EFIAPI __attribute__((__ms_abi__))  // Force Microsoft ABI
     #endif
 #endif
 
-- 
2.43.0



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Date: Wed, 13 Aug 2025 13:17:29 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Roger Pau Monne 
cc: xen-devel@lists.xenproject.org, Andrew Cooper , 
    Anthony PERARD , 
    Michal Orzel , Jan Beulich , 
    Julien Grall , Stefano Stabellini 
Subject: Re: [PATCH] x86/pvh: update "Host ACPI" support status
In-Reply-To: <20250813093220.76030-1-roger.pau@citrix.com>
Message-ID: 
References: <20250813093220.76030-1-roger.pau@citrix.com>
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On Wed, 13 Aug 2025, Roger Pau Monne wrote:
> For x86 PVH dom0 makes uses of the host ACPI tables, and hence the status
> of Host ACPI entry should have been updated to reflect that PVH dom0 is now
> supported, and Host ACPI support is not one of the caveats.
> 
> Fixes: ea1cb444c28c ('x86/pvh: declare PVH dom0 supported with caveats')
> Signed-off-by: Roger Pau Monné 

Acked-by: Stefano Stabellini 


> ---
>  SUPPORT.md | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/SUPPORT.md b/SUPPORT.md
> index 6a82a9218991..109b62835f99 100644
> --- a/SUPPORT.md
> +++ b/SUPPORT.md
> @@ -70,7 +70,7 @@ For the Cortex A77 r0p0 - r1p0, see Errata 1508412.
>  
>  ### Host ACPI (via Domain 0)
>  
> -    Status, x86 PV: Supported
> +    Status, x86: Supported
>      Status, ARM: Experimental
>  
>  ### Host EFI Boot
> -- 
> 2.49.0
> 
--8323329-895347095-1755116253=:10166--


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Date: Wed, 13 Aug 2025 17:20:40 -0500
From: Aaron Rainbolt 
To: Daniel Kiper 
Cc: grub-devel@gnu.org, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 2/2] kern/xen: Add Xen command line parsing
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On Wed, 13 Aug 2025 16:27:11 +0200
Daniel Kiper  wrote:

> On Tue, Aug 12, 2025 at 06:55:15PM -0500, Aaron Rainbolt wrote:
> > On Tue, 12 Aug 2025 19:02:11 +0200 Daniel Kiper
> >  wrote: =20
> > > On Mon, Aug 04, 2025 at 11:50:09PM -0500, Aaron Rainbolt wrote: =20
> > > > Xen traditionally allows customizing guest behavior by passing
> > > > arguments to the VM kernel via the kernel command line. This is
> > > > no longer possible when using GRUB with Xen, as the kernel
> > > > command line is decided by the GRUB configuration file within
> > > > the guest, not data passed to the guest by Xen.
> > > >
> > > > To work around this limitation, enable GRUB to parse a command
> > > > line passed to it by Xen, and expose data from the command line
> > > > to the GRUB configuration as environment variables. These
> > > > variables can be used in the GRUB configuration for any desired
> > > > purpose, such as extending the kernel command line passed to
> > > > the guest. The command line format is inspired by the Linux
> > > > kernel's command line format.
> > > >
> > > > To reduce the risk of misuse, abuse, or accidents in
> > > > production, the command line will only be parsed if it consists
> > > > entirely of 7-bit ASCII characters, only alphabetical
> > > > characters and underscores are permitted in variable names, and
> > > > all variable names must start with the string "xen_grub_env_".
> > > > This also allows room for expanding the command line arguments
> > > > accepted by GRUB in the future, should other arguments end up
> > > > becoming desirable in the future.
> > > >
> > > > Signed-off-by: Aaron Rainbolt  =20
>=20
> [...]
>=20
> > > > diff --git a/grub-core/kern/i386/xen/pvh.c
> > > > b/grub-core/kern/i386/xen/pvh.c index 91fbca8..a8988d2 100644
> > > > --- a/grub-core/kern/i386/xen/pvh.c +++
> > > > b/grub-core/kern/i386/xen/pvh.c @@ -321,6 +321,8 @@ void
> > > >  grub_xen_setup_pvh (void)
> > > >  {
> > > >    grub_addr_t par;
> > > > +  const char *xen_cmdline;
> > > > +  int i;
> > > >
> > > >    grub_xen_cpuid_base ();
> > > >    grub_xen_setup_hypercall_page ();
> > > > @@ -352,6 +354,27 @@ grub_xen_setup_pvh (void)
> > > >    grub_xen_mm_init_regions ();
> > > >
> > > >    grub_rsdp_addr =3D pvh_start_info->rsdp_paddr;
> > > > +
> > > > +  xen_cmdline =3D (const char *) pvh_start_info->cmdline_paddr;
> > > > +  for (i =3D 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++)
> > > > +    {
> > > > +      if (xen_cmdline[i] =3D=3D '\0') =20
> > >
> > > This code still does not make a lot of sense for me. You have NUL
> > > check in grub_parse_xen_cmdline(). So, you duplicate the check
> > > here...
> > >
> > > I would just fire grub_strncpy() here and forget... =20
> >
> > I guess it depends on how you view
> > grub_xen_start_page_addr->cmd_line's semantics. In my mind,
> > cmd_line is a NUL-terminated string, always. If you boot in PV
> > mode, Xen ensures it's a NUL-terminated string, so it's reasonable
> > for code in GRUB to assume it will be one. If you boot in PVH mode,
> > it starts out initialized to all zeros which is technically a
> > NUL-terminated string, and the code that exists here ensures that
> > if we copy the kernel command line to cmd_line, it will still be a
> > NUL-terminated string. If we use a "bare" grub_strncpy() here, then
> > if someone passes a kernel command line larger than
> > GRUB_XEN_MAX_GUEST_CMDLINE - 1, cmd_line will end up not being
> > NUL-terminated anymore, and any code added to GRUB in the future
> > that assumes it is a NUL-terminated string may buffer overflow.
> >
> > One could argue "let's keep the NUL check here and remove it from
> > grub_parse_xen_cmdline()", but that doesn't work either because we
> > only get to control the contents of cmd_line if we boot in PVH
> > mode. If instead we boot in PV mode, cmd_line is initialized by Xen
> > itself. GRUB receives a pre-populated and ready-to-use start_info
> > struct directly from the hypervisor in this scenario. Xen is
> > supposed to ensure that start_info is always NUL-terminated, but if
> > there's ever a bug in Xen that breaks that assumption, that could
> > result in bad things happening, the same as if we didn't do the NUL
> > check in grub_xen_setup_pvh(). Now of course there's nothing we can
> > do about Xen possibly being buggy (if it gives us a
> > GRUB_XEN_MAX_GUEST_CMDLINE-long buffer with no NUL terminator, too
> > bad), but we can at least make sure that we're ready for that
> > eventuality. That's why I like having both NUL checks - we're ready
> > for if Xen does things wrong, and any future code that isn't ready
> > for that eventuality will still work if things go wrong, at least
> > in PVH mode. =20
>=20
> OK, it looks like this explanation, in shortened form, should land
> around this code... Or not... Please look below...
>=20
> > (Arguably any new code that depends on cmd_line *should* check it
> > for a NUL terminator. But I don't want to assume that all new code
> > *will* do so.)
> > =20
> > > > +        {
> > > > +          grub_strncpy ((char *)
> > > > grub_xen_start_page_addr->cmd_line,
> > > > +			(char *) pvh_start_info->cmdline_paddr,
> > > > +			GRUB_XEN_MAX_GUEST_CMDLINE);
> > > > +
> > > > +          if
> > > > (grub_xen_start_page_addr->cmd_line[GRUB_XEN_MAX_GUEST_CMDLINE
> > > > - 1] !=3D '\0') =20
> > >
> > > If you convince me this code is still needed then I am afraid that
> > > this is not what you meant here... =20
> >
> > grub_strncpy doesn't just NUL-terminate the command line, it also
> > fills the entire remainder of the buffer with NUL characters.
> > Therefore if =20
>=20
> I am afraid we are looking at different grub_strncpy() functions...

Crud. I was going off the semantics of `strncpy` documented in `man
3 stpncpy`. I see now that GRUB's implementation doesn't have the NUL
padding behavior. I'll take a closer look at all uses of grub_strncpy()
and make sure I'm not relying on that behavior anywhere else.

> > grub_strncpy NUL-terminated the copied string, the last character of
> > the buffer will always be NUL. This is a redundant check since the
> > code above goes to great lengths to avoid ever putting anything
> > non-NUL-terminated into the buffer, but I was under the impression
> > you wanted the check added just in case. I'm happy to remove it if
> > it's not desirable. =20
>=20
> I think we misunderstood each other. This code is redundant now...

Alright, will remove.

> [...]
>=20
> > > > +is_key_safe (char *key, grub_size_t len)
> > > > +{
> > > > +  grub_size_t i;
> > > > +
> > > > +  for (i =3D 0; i < len; i++)
> > > > +    {
> > > > +      if (! (grub_isalpha (key[i]) || key[i] =3D=3D '_')) =20
> > >
> > > Please drop space after "!"... =20
> >
> > Will change.
> > =20
> > > > +        return false;
> > > > +    } =20
> > >
> > > You can drop curly braces from here... =20
> >
> > Will change.
> >
> > (I initially kept this written the way it was though because the GNU
> > coding standards seemed to indicate I should keep the braces. "When
> > you have an if-else statement nested in another if statement, always
> > put braces around the if-else." [1] This isn't a nested if, but
> > it's an if within a for which is very similar.)
> >
> > Is there any recommended coding style documentation I should be
> > looking at other than the GNU coding standards and the GRUB coding
> > style guidelines? It seems I'm making an awful lot of style
> > mistakes and would like to avoid that going forward. =20
>=20
> Yes, it is but sadly it is not fully/properly/.. documented [1]...
>=20
> [...]
>=20
> > > > +  for (i =3D 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++)
> > > > +    {
> > > > +      if (cmdline[i] =3D=3D '\0')
> > > > +        {
> > > > +          cmdline_valid =3D true;
> > > > +          break;
> > > > +        }
> > > > +    }
> > > > +
> > > > +  if (cmdline_valid =3D=3D false)
> > > > +    {
> > > > +      grub_error (GRUB_ERR_BAD_ARGUMENT,
> > > > +		  "command line from Xen is not
> > > > NUL-terminated");
> > > > +      grub_print_error (); =20
> > >
> > > grub_fatal()? =20
> >
> > That would probably be a bad idea here. We use (or, at least, will
> > use) grub_fatal() in grub_xen_setup_pvh() because if grub_strncpy()
> > doesn't NUL-terminate the string it copies, it indicates a bug in
> > GRUB (either in grub_strncpy, or more likely in the nearby
> > NUL-checking code). On the other hand, cmdline_valid may equal
> > false if we boot in PV mode and Xen incorrectly hands us a
> > non-NUL-terminated string. That's bad and prevents us from parsing
> > the command line safely, but I'd argue it shouldn't entirely block
> > boot. (Then again, maybe if it does block boot, that will make this
> > kind of theoretical Xen bug be much more noticeable and help it get
> > fixed quicker. If you'd prefer that we bail out entirely here, I'm
> > happy to change it.) =20
>=20
> As I said earlier, I would simply call grub_strncpy() in
> grub_xen_setup_pvh() without additional NUL-check there and fail if
> non-NUL-terminated string is detected here...

OK, I'll do that then. It will be of critical importance that if any
new code is introduced in GRUB in the future, that it does not assume
cmd_line is NUL-terminated. I'll add a comment to the appropriate
header so that future developers are aware of the danger.

> > > > +      goto cleanup_main;
> > > > +    }
> > > > +
> > > > +  cmdline_len =3D grub_strlen (cmdline);
> > > > +  for (i =3D 0; i < cmdline_len; i++)
> > > > +    {
> > > > +      current_char =3D cmdline[i];
> > > > +
> > > > +      /*
> > > > +       * If the previous character was a backslash, append the
> > > > current
> > > > +       * character to the word verbatim
> > > > +       */
> > > > +      if (splitter_state & SPLITTER_HIT_BACKSLASH)
> > > > +        {
> > > > +          splitter_state &=3D ~SPLITTER_HIT_BACKSLASH;
> > > > +          if (append_char_to_word (s, current_char, false) =3D=3D
> > > > false)
> > > > +            goto cleanup_main;
> > > > +          continue;
> > > > +        }
> > > > +
> > > > +      switch (current_char)
> > > > +        {
> > > > +        case '\\':
> > > > +          /* Backslashes escape arbitrary characters. */
> > > > +          splitter_state |=3D SPLITTER_HIT_BACKSLASH;
> > > > +          continue;
> > > > +
> > > > +        case '\'':
> > > > +          /*
> > > > +           * Single quotes suppress word splitting and double
> > > > quoting until
> > > > +           * the next single quote is encountered.
> > > > +           */
> > > > +          if (splitter_state & SPLITTER_IN_DOUBLE_QUOTES)
> > > > +            {
> > > > +              if (append_char_to_word (s, current_char, false)
> > > > =3D=3D false)
> > > > +                goto cleanup_main;
> > > > +              continue;
> > > > +            }
> > > > +
> > > > +          splitter_state ^=3D SPLITTER_IN_SINGLE_QUOTES;
> > > > +          continue;
> > > > +
> > > > +        case '"':
> > > > +          /*
> > > > +           * Double quotes suppress word splitting and single
> > > > quoting until
> > > > +           * the next double quote is encountered.
> > > > +           */
> > > > +          if (splitter_state & SPLITTER_IN_SINGLE_QUOTES)
> > > > +            {
> > > > +              if (append_char_to_word (s, current_char, false)
> > > > =3D=3D false)
> > > > +                goto cleanup_main;
> > > > +              continue;
> > > > +            }
> > > > +
> > > > +          splitter_state ^=3D SPLITTER_IN_DOUBLE_QUOTES;
> > > > +          continue;
> > > > +
> > > > +        case ' ':
> > > > +          /* Spaces separate words in the command line from
> > > > each other. */
> > > > +          if (splitter_state & SPLITTER_IN_SINGLE_QUOTES ||
> > > > +              splitter_state & SPLITTER_IN_DOUBLE_QUOTES)
> > > > +            {
> > > > +              if (append_char_to_word (s, current_char, false)
> > > > =3D=3D false)
> > > > +                goto cleanup_main;
> > > > +              continue;
> > > > +            }
> > > > +
> > > > +          if (append_word_to_list (s) =3D=3D false)
> > > > +            goto cleanup_main; =20
> > >
> > > I think this is not fully correct. You should not run
> > > append_word_to_list() until the closing quote. So, here you should
> > > have "else" for the first "if", i.e., "if (splitter_state & ..."
> > > and call append_word_to_list() for closing \" and \' above. =20
> >
> > What closing quote? If we're in quotes, the `if (splitter_state
> > &...` block will run. That block runs `continue`, restarting the
> > loop before we get to the `append_word_to_list (s)` call. If we hit
> > a closing quote, either the `case '\''` or the `case '"'` block
> > will be triggered, changing the splitter's state so that it knows
> > it's no longer within a quote block, and then the next space (or
> > the end of the string) will cause `append_word_to_list()` to be
> > called, adding the quoted word to the list. Even if this `continue`
> > changes to a `break` like suggested below, the logic and control
> > flow will remain the same.
> >
> > Calling `append_word_to_list()` for closing quotes would break the
> > splitter. I'm trying to implement splitting behavior similar to
> > Bash or GRUB's configuration language, both of which parse
> > `xen_grub_env_var=3D"abc def"ghi` into the variable `xen_grub_env_var`
> > with the value `abc defghi`. If we split on closing quotes too, the
> > input above will be parsed into two words, `xen_grub_env_var=3Dabc
> > def` and an extra word `ghi`, resulting in the environment variable
> > `xen_grub_env_var` being set to `abc def` and the `ghi` being lost
> > entirely. One could argue that this is reasonable behavior, but it
> > isn't consistent with the other splitting behavior in GRUB. =20
>=20
> OK, makes sense for me... Maybe you should mention somewhere in the
> code current splitter behavior...

Technically the behavior is documented in the comment immediately
before the splitter code, but the rationale isn't entirely explained,
so I'll add some extra info to the comment so it's more clear.

--
Aaron

> Daniel
>=20
> [1]
> https://www.gnu.org/software/grub/manual/grub-dev/grub-dev.html#Coding-st=
yle


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Subject: Re: [XEN PATCH 1/3] xen/compiler: drop alternative unreachable()
 definition for older GCC
To: nicola.vetrini@gmail.com, xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini 
References: 
 <9215845f364527203efaea9dd1019cd1e3c1768b.1755111932.git.nicola.vetrini@bugseng.com>
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In-Reply-To: <9215845f364527203efaea9dd1019cd1e3c1768b.1755111932.git.nicola.vetrini@bugseng.com>
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On 13/08/2025 8:12 pm, nicola.vetrini@gmail.com wrote:
> From: Nicola Vetrini 
>
> The GCC baseline version is 5.1, which supports __builtin_unreachable(),
> therefore the alternative definition can be dropped
>
> Signed-off-by: Nicola Vetrini 
> ---
> Mentioned in https://gitlab.com/xen-project/xen/-/issues/201

Reviewed-by: Andrew Cooper 


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Subject: Re: [XEN PATCH 2/3] xen/macros: Drop alternative definition of
 BUILD_BUG_ON(_ZERO)? for old GCC
To: nicola.vetrini@gmail.com, xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
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On 13/08/2025 8:12 pm, nicola.vetrini@gmail.com wrote:
> From: Nicola Vetrini 
>
> The toolchain baseline for GCC is 5.1, which supports _Static_assert
> in c99 mode
>
> No functional change.
>
> Signed-off-by: Nicola Vetrini 
> ---
> Mentioned in https://gitlab.com/xen-project/xen/-/issues/201

Reviewed-by: Andrew Cooper 


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Date: Wed, 13 Aug 2025 23:39:57 +0100
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Subject: Re: [XEN PATCH 3/3] xen/efi: efibind: Drop alternative define for old
 GCC versions
To: nicola.vetrini@gmail.com, xen-devel@lists.xenproject.org
Cc: "Daniel P. Smith" ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
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On 13/08/2025 8:12 pm, nicola.vetrini@gmail.com wrote:
> From: Nicola Vetrini 
>
> Since the toolchain baseline for GCC is 5.1, there is no need for
> this case.
>
> Signed-off-by: Nicola Vetrini 
> ---
> Mentioned in https://gitlab.com/xen-project/xen/-/issues/201

I personally am in favour of this change, but in the past there has been
objection to changing this header it is vendered from elsewhere.

e.g. far more could be stripped out if ...

> ---
>  xen/arch/x86/include/asm/x86_64/efibind.h | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/xen/arch/x86/include/asm/x86_64/efibind.h b/xen/arch/x86/include/asm/x86_64/efibind.h
> index b29342c61cac..d71b9324a6bb 100644
> --- a/xen/arch/x86/include/asm/x86_64/efibind.h
> +++ b/xen/arch/x86/include/asm/x86_64/efibind.h
> @@ -173,10 +173,8 @@ typedef uint64_t   UINTN;
>  #ifndef EFIAPI                  // Forces EFI calling conventions reguardless of compiler options
>      #ifdef _MSC_EXTENSIONS
>          #define EFIAPI __cdecl  // Force C calling convention for Microsoft C compiler

... it's noted that Xen doesn't use MSC and I can't see anyone taking
the time to make it work.

~Andrew


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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Nicola Vetrini 
Subject: [PATCH] x86/cpu-policy: Drop workaround for pre-GCC-5 PIC issue
Date: Thu, 14 Aug 2025 00:05:25 +0100
Message-Id: <20250813230525.2435414-1-andrew.cooper3@citrix.com>
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GCC 5.1 is the minimum supported toolchain version now.  Drop the workaround
for the PIC hard register in earlier versions.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
CC: Nicola Vetrini 

Noticed when reviewing the other GCC cleanup.
---
 xen/include/xen/lib/x86/cpu-policy.h | 35 ++++------------------------
 1 file changed, 4 insertions(+), 31 deletions(-)

diff --git a/xen/include/xen/lib/x86/cpu-policy.h b/xen/include/xen/lib/x86/cpu-policy.h
index dd204a825b07..f94f23e159d2 100644
--- a/xen/include/xen/lib/x86/cpu-policy.h
+++ b/xen/include/xen/lib/x86/cpu-policy.h
@@ -29,45 +29,18 @@ struct cpuid_leaf
     uint32_t a, b, c, d;
 };
 
-/*
- * Versions of GCC before 5 unconditionally reserve %rBX as the PIC hard
- * register, and are unable to cope with spilling it.  This results in a
- * rather cryptic error:
- *    error: inconsistent operand constraints in an ‘asm’
- *
- * In affected situations, work around the issue by using a separate register
- * to hold the the %rBX output, and xchg twice to leave %rBX preserved around
- * the asm() statement.
- */
-#if defined(__PIC__) && __GNUC__ < 5 && !defined(__clang__) && defined(__i386__)
-# define XCHG_BX "xchg %%ebx, %[bx];"
-# define BX_CON [bx] "=&r"
-#elif defined(__PIC__) && __GNUC__ < 5 && !defined(__clang__) && \
-    defined(__x86_64__) && (defined(__code_model_medium__) || \
-                            defined(__code_model_large__))
-# define XCHG_BX "xchg %%rbx, %q[bx];"
-# define BX_CON [bx] "=&r"
-#else
-# define XCHG_BX ""
-# define BX_CON "=&b"
-#endif
-
 static inline void cpuid_leaf(uint32_t leaf, struct cpuid_leaf *l)
 {
-    asm ( XCHG_BX
-          "cpuid;"
-          XCHG_BX
-          : "=a" (l->a), BX_CON (l->b), "=&c" (l->c), "=&d" (l->d)
+    asm ( "cpuid"
+          : "=a" (l->a), "=b" (l->b), "=c" (l->c), "=d" (l->d)
           : "a" (leaf) );
 }
 
 static inline void cpuid_count_leaf(
     uint32_t leaf, uint32_t subleaf, struct cpuid_leaf *l)
 {
-    asm ( XCHG_BX
-          "cpuid;"
-          XCHG_BX
-          : "=a" (l->a), BX_CON (l->b), "=c" (l->c), "=&d" (l->d)
+    asm ( "cpuid"
+          : "=a" (l->a), "=b" (l->b), "=c" (l->c), "=d" (l->d)
           : "a" (leaf), "c" (subleaf) );
 }
 
-- 
2.39.5



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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[PATCH]=20misra:=20address=20Rule=2011.1=20violation=20in=20cmpxchgptr()?=
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Hello,

Le 13/08/2025 =C3=A0 20:07, Dmytro Prokopchuk1 a =C3=A9crit=C2=A0:
> Misra Rule 11.1 states: "Conversions shall not be performed between a
> pointer to a function and any other type."
> 
> The violation occurs in the macro:
>      __typeof__(**(ptr)) *const o_ =3D (o);                              =
  \
>      __typeof__(**(ptr)) *n_ =3D (n);                                    =
  \
>      ((__typeof__(*(ptr)))__cmpxchg(ptr, (unsigned long)o_,              =
\
>                                     (unsigned long)n_, sizeof(*(ptr)))); =
\
> })
> when it is used for handling function pointers of type:
> typedef void (*)(struct vcpu *, unsigned int).
> The issue happens because the '__cmpxchg()' function returns an 'unsigned
> long', which is then converted back into a function pointer, causing a
> violation of Rule 11.1. In this particular usage, the return value of the
> macro 'cmpxchgptr()' is not required. To address the violation, the macro
> has been replaced to discard the return value of '__cmpxchg()', preventin=
g
> the conversion.
> 
> Signed-off-by: Dmytro Prokopchuk 
> ---
> Probably separate macro is too much for this single case.
> 
> And the following will be enought:
> __cmpxchg(&xen_consumers[i], (unsigned long)NULL, (unsigned long)fn, size=
of(*(&xen_consumers[i])));
> ---
>   xen/common/event_channel.c | 15 +++++++++++++--
>   1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
> index 67700b050a..2094338b28 100644
> --- a/xen/common/event_channel.c
> +++ b/xen/common/event_channel.c
> @@ -93,6 +93,17 @@ static void cf_check default_xen_notification_fn(
>           vcpu_wake(v);
>   }
>   
> +/*
> + * A slightly more updated variant of cmpxchgptr() where old value
> + * is not returned.
> + */
> +#define cmpxchgptr_noret(ptr, o, n) ({                  \
> +    __typeof__(**(ptr)) *const o_ =3D (o);                \
> +    __typeof__(**(ptr)) *n_ =3D (n);                      \
> +    (void)__cmpxchg(ptr, (unsigned long)o_,             \
> +                    (unsigned long)n_, sizeof(*(ptr))); \
> +})
> +
>   /*
>    * Given a notification function, return the value to stash in
>    * the evtchn->xen_consumer field.
> @@ -106,9 +117,9 @@ static uint8_t get_xen_consumer(xen_event_channel_not=
ification_t fn)
>   
>       for ( i =3D 0; i < ARRAY_SIZE(xen_consumers); i++ )
>       {
> -        /* Use cmpxchgptr() in lieu of a global lock. */
> +        /* Use cmpxchgptr_noret() in lieu of a global lock. */
>           if ( xen_consumers[i] =3D=3D NULL )
> -            cmpxchgptr(&xen_consumers[i], NULL, fn);
> +            cmpxchgptr_noret(&xen_consumers[i], NULL, fn);
>           if ( xen_consumers[i] =3D=3D fn )
>               break;
>       }

AFAICS, Rule 11.1 has a deviation which allows this specific case.

In docs/misra/deviations.rst
> * - R11.1
>   - The conversion from a function pointer to unsigned long or (void \*) =
does
>     not lose any information, provided that the target type has enough bi=
ts
>     to store it.
>   - Tagged as `safe` for ECLAIR.

Here, we are constructing a function pointer from a unsigned long. I 
assume this rule goes the other way it says, and allow converting a 
unsigned long into a function pointer as long as its value is a valid 
function pointer.

Teddy


Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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On 8/12/25 02:12, Jan Beulich wrote:
> On 12.08.2025 02:19, Daniel P. Smith wrote:
>> On 7/23/25 09:39, Jan Beulich wrote:
>>> Use the more "modern" form, thus doing away with effectively open-coding
>>> xmalloc_array() at the same time. While there is a difference in
>>> generated code, as xmalloc_bytes() forces SMP_CACHE_BYTES alignment, if
>>> code really cared about such higher than default alignment, it should
>>> request so explicitly.
>>
>> While I don't object to the change itself, I think this description is a
>> bit over simplification of the change. If the allocation is under
>> PAGE_SIZE, then they are equivalent, but if it is over the page size
>> there are a few more differences than just cache alignment. It
>> completely changes the underlying allocator. I personally also find it a
>> bit of a stretch to call xmalloc_bytes(size) an open coded version of
>> xmalloc_array(char, size).
> 
> My take is that xmalloc_bytes() should never have existed. Hence why I
> didn't add xzmalloc_bytes() when introducing that family of interfaces.

Right, which would be a valid argument for replacing it with 
xmalloc_array(). Though, I would note that there is an xzalloc_bytes(). 
My concern was that you stated there was an open coding, which had me 
expecting there was a line of the form, xmanlloc_bytes(count * 
size_of_something bigger), being replaced by 
xvmalloc_arryay(something_bigger, count).

IMHO, while the C spec does specify char as 1 byte and thus 
interchangeable, I would agree that from a contextual perspective, 
xmalloc_array() is the more appropriate call. The use of the allocation 
is a character array and not a chunk of bytes for an arbitrary buffer.

>> With a stronger description of the change,
> 
> So what exactly do you mean by "stronger"? I can add that in the unlikely
> event that one of the allocations is (near) PAGE_SIZE or larger, we now
> wouldn't require contiguous memory anymore. Yet based on your comment at
> the top I'm not quite sure if that's what you're after and/or enough to
> satisfy your request.

The phrasing stronger was meant to be more clear on the change/effect, 
specifically that the underlying allocator is being changed when the 
allocation is greater than a PAGE_SIZE. Not necessarily a long 
explanation, just the fact that the allocation will be coming from the 
dom heap allocator as opposed to the xen heap allocator. There are 
implications to changing the allocater, e.g.,  at a minimum the 
allocation order and nonphysical vs. physically contiguous effects. 
Having it noted in the commit makes it more obvious what this change is 
actually doing. Which may not be obvious when seeing the simple line 
changes occurring in the diff. Later, if there is an unexpected 
consequence caused by this change, a stronger commit will be helpful 
with the bisection investigations.

dps

>> Acked-by: Daniel P. Smith 
> 
> Thanks, but will need clarification first as per above.
> 
> Jan



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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[RFC=20PATCH]=20misra:=20allow=20conversion=20from=20unsigned=20long=20to=20function=20pointer?=
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To: "Dmytro Prokopchuk1" , xen-devel@lists.xenproject.org
Cc: "Nicola Vetrini" , "Doug Goldstein" , "Stefano Stabellini" , "Andrew Cooper" , "Anthony PERARD" , "Michal Orzel" , "Jan Beulich" , "Julien Grall" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Bertrand Marquis" , "Volodymyr Babchuk" 
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Hello,

Le 13/08/2025 =C3=A0 20:30, Dmytro Prokopchuk1 a =C3=A9crit=C2=A0:
> ...
> 
> from `vaddr_t' (that is `unsigned long') to `switch_ttbr_fn*' (that is `v=
oid(*)(unsigned long)')
> 
> Signed-off-by: Dmytro Prokopchuk 
> ---
> This is just a RFC patch.
> The commit message is not important at this stage.
> 
> I am seeking comments regarding this case.
> 
> Thanks.
> ---
>   automation/eclair_analysis/ECLAIR/deviations.ecl |  8 ++++++++
>   docs/misra/deviations.rst                        | 10 ++++++++++
>   docs/misra/rules.rst                             |  8 +++++++-
>   xen/arch/arm/arm64/mmu/mm.c                      |  2 ++
>   4 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automatio=
n/eclair_analysis/ECLAIR/deviations.ecl
> index ebce1ceab9..f9fd6076b7 100644
> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -365,6 +365,14 @@ constant expressions are required.\""
>   }
>   -doc_end
>   
> +-doc_begin=3D"The conversion from unsigned long to a function pointer do=
es not lose any information, provided that the source type has enough bits =
to restore it."
> +-config=3DMC3A2.R11.1,casts+=3D{safe,
> +  "from(type(canonical(builtin(unsigned long))))
> +   &&to(type(canonical(__function_pointer_types)))
> +   &&relation(definitely_preserves_value)"
> +}
> +-doc_end
> +
>   -doc_begin=3D"The conversion from a function pointer to a boolean has a=
 well-known semantics that do not lead to unexpected behaviour."
>   -config=3DMC3A2.R11.1,casts+=3D{safe,
>     "from(type(canonical(__function_pointer_types)))
> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
> index 3c46a1e47a..27848602f6 100644
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -348,6 +348,16 @@ Deviations related to MISRA C:2012 Rules:
>          to store it.
>        - Tagged as `safe` for ECLAIR.
>   
> +   * - R11.1
> +     - The conversion from unsigned long to a function pointer does not =
lose any
> +       information or violate type safety assumptions if the unsigned lo=
ng type
> +       is guaranteed to be at least as large as a function pointer. This=
 ensures
> +       that the function pointer address can be fully represented withou=
t
> +       truncation or corruption. Macro BUILD_BUG_ON can be integrated in=
to the
> +       build system to confirm that 'sizeof(unsigned long) >=3D sizeof(v=
oid (*)())'

Wouldn't `sizeof(unsigned long) =3D=3D sizeof(void (*)())` be preferable ?

I assume sizeof(unsigned long) is the size of a CPU word.
Having `sizeof(unsigned long) < sizeof(void (*)())` makes use of 
operations like cmpxchg unsuitable on function pointers (because of 
object size mismatch).

> +       on all target platforms.
> +     - Tagged as `safe` for ECLAIR.
> +
>      * - R11.1
>        - The conversion from a function pointer to a boolean has a well-k=
nown
>          semantics that do not lead to unexpected behaviour.
> diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
> index 6812eb7e8a..8b97ecf3f4 100644
> --- a/docs/misra/rules.rst
> +++ b/docs/misra/rules.rst
> @@ -414,7 +414,13 @@ maintainers if you want to suggest a change.
>        - All conversions to integer types are permitted if the destinatio=
n
>          type has enough bits to hold the entire value. Conversions to bo=
ol
>          and void* are permitted. Conversions from 'void noreturn (*)(...=
)'
> -       to 'void (*)(...)' are permitted.
> +       to 'void (*)(...)' are permitted. Conversions from unsigned long =
to
> +       function pointer are permitted if the unsigned long type has a si=
ze
> +       and representation sufficient to store the entire function pointe=
r
> +       value without truncation or corruption. Example::
> +
> +           unsigned long func_addr =3D (unsigned long)&some_function;
> +           void (*restored_func)(void) =3D (void (*)(void))func_addr;
>   
>      * - `Rule 11.2 `_
>        - Required
> diff --git a/xen/arch/arm/arm64/mmu/mm.c b/xen/arch/arm/arm64/mmu/mm.c
> index 3e64be6ae6..998d52c162 100644
> --- a/xen/arch/arm/arm64/mmu/mm.c
> +++ b/xen/arch/arm/arm64/mmu/mm.c
> @@ -150,6 +150,7 @@ void __init relocate_and_switch_ttbr(uint64_t ttbr)
>       vaddr_t id_addr =3D virt_to_maddr(relocate_xen);
>       relocate_xen_fn *fn =3D (relocate_xen_fn *)id_addr;
>       lpae_t pte;
> +    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
>   
>       /* Enable the identity mapping in the boot page tables */
>       update_identity_mapping(true);
> @@ -178,6 +179,7 @@ void __init switch_ttbr(uint64_t ttbr)
>       vaddr_t id_addr =3D virt_to_maddr(switch_ttbr_id);
>       switch_ttbr_fn *fn =3D (switch_ttbr_fn *)id_addr;
>       lpae_t pte;
> +    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
>   
>       /* Enable the identity mapping in the boot page tables */
>       update_identity_mapping(true);



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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To: grub-devel@gnu.org,
	xen-devel@lists.xenproject.org
Cc: Aaron Rainbolt 
Subject: [PATCH v5 1/3] include/xen: Rename MAX_GUEST_CMDLINE to GRUB_XEN_MAX_GUEST_CMDLINE
Date: Wed, 13 Aug 2025 20:36:43 -0500
Message-ID: <20250814013645.2488043-2-arraybolt3@gmail.com>
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From: Aaron Rainbolt 

The xen.h header was using an overly generic name to refer to the
maximum length of the command line passed from Xen to a guest. Rename it
to avoid confusion or conflicts in the future.

Signed-off-by: Aaron Rainbolt 
---
 include/xen/xen.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/xen/xen.h b/include/xen/xen.h
index 692f97a..fdf0fc4 100644
--- a/include/xen/xen.h
+++ b/include/xen/xen.h
@@ -823,8 +823,8 @@ struct start_info {
                                 /* (PFN of pre-loaded module if           */
                                 /*  SIF_MOD_START_PFN set in flags).      */
     unsigned long mod_len;      /* Size (bytes) of pre-loaded module.     */
-#define MAX_GUEST_CMDLINE 1024
-    int8_t cmd_line[MAX_GUEST_CMDLINE];
+#define GRUB_XEN_MAX_GUEST_CMDLINE 1024
+    int8_t cmd_line[GRUB_XEN_MAX_GUEST_CMDLINE];
     /* The pfn range here covers both page table and p->m table frames.   */
     unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table.    */
     unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table.  */
-- 
2.50.1



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From: arraybolt3@gmail.com
To: grub-devel@gnu.org,
	xen-devel@lists.xenproject.org
Cc: Aaron Rainbolt 
Subject: [PATCH v5 0/3] kern/xen: Add Xen command line parsing
Date: Wed, 13 Aug 2025 20:36:42 -0500
Message-ID: <20250814013645.2488043-1-arraybolt3@gmail.com>
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From: Aaron Rainbolt 

The purpose of this patch is to allow the Xen hypervisor to pass extra
data to GRUB in the form of a kernel command line, allowing the host to
customize the boot process of the guest. The command line from Xen is
parsed, and any variables within that start with the string
`xen_grub_env_` are exposed as environment variables. The grub.cfg
script can then use those environment variables as it sees fit.

The main reason for doing this is to allow implementing boot modes in
Qubes OS while also using in-VM kernels. For more context on Qubes boot
modes, see [1]. In order for this to work with in-VM kernels, it is
necessary for dom0 to pass kernel parameters to the guest without
modifying the guest's grub.cfg manually. This patch allows this to be
done, by allowing dom0 to pass kernel parameters to GRUB, which then
provides them to grub.cfg as an environment variable. The grub.cfg
script within the VM can then append those parameters to the kernel
command line.

All of the changes from version 4 of the patch are simply refinements
after review from Daniel Kiper. The patch's functionality is unchanged.

Since there are substantial changes since version 4, I've re-run the
entire battery of tests that were used against the v4 patch. All tests
pass. As previously, the tests were done by booting a patched GRUB in
Xen with various different parameters passed to it via the Xen-provided
kernel command line. The effects of these parameters on the
bootloader's environment were then tested, and then an Arch Linux image
was booted to ensure that boot still worked.

[1] https://github.com/QubesOS/qubes-linux-pvgrub2/pull/16

Aaron Rainbolt (3):
  include/xen: Rename MAX_GUEST_CMDLINE to GRUB_XEN_MAX_GUEST_CMDLINE
  include/xen: Add warning comment for cmd_line
  kern/xen: Add Xen command line parsing

 docs/grub.texi                |  52 +++++
 grub-core/Makefile.core.def   |   2 +
 grub-core/kern/i386/xen/pvh.c |   4 +
 grub-core/kern/xen/cmdline.c  | 361 ++++++++++++++++++++++++++++++++++
 grub-core/kern/xen/init.c     |   2 +
 include/grub/xen.h            |   2 +
 include/xen/xen.h             |   9 +-
 7 files changed, 430 insertions(+), 2 deletions(-)
 create mode 100644 grub-core/kern/xen/cmdline.c

--
2.50.1



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        Wed, 13 Aug 2025 18:37:08 -0700 (PDT)
From: arraybolt3@gmail.com
To: grub-devel@gnu.org,
	xen-devel@lists.xenproject.org
Cc: Aaron Rainbolt 
Subject: [PATCH v5 3/3] kern/xen: Add Xen command line parsing
Date: Wed, 13 Aug 2025 20:36:45 -0500
Message-ID: <20250814013645.2488043-4-arraybolt3@gmail.com>
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From: Aaron Rainbolt 

Xen traditionally allows customizing guest behavior by passing arguments
to the VM kernel via the kernel command line. This is no longer possible
when using GRUB with Xen, as the kernel command line is decided by the
GRUB configuration file within the guest, not data passed to the guest
by Xen.

To work around this limitation, enable GRUB to parse a command line
passed to it by Xen, and expose data from the command line to the GRUB
configuration as environment variables. These variables can be used in
the GRUB configuration for any desired purpose, such as extending the
kernel command line passed to the guest. The command line format is
inspired by the Linux kernel's command line format.

To reduce the risk of misuse, abuse, or accidents in production, the
command line will only be parsed if it consists entirely of 7-bit ASCII
characters, only alphabetical characters and underscores are permitted
in variable names, and all variable names must start with the string
"xen_grub_env_". This also allows room for expanding the command line
arguments accepted by GRUB in the future, should other arguments end up
becoming desirable in the future.

Signed-off-by: Aaron Rainbolt 
---
 docs/grub.texi                |  52 +++++
 grub-core/Makefile.core.def   |   2 +
 grub-core/kern/i386/xen/pvh.c |   4 +
 grub-core/kern/xen/cmdline.c  | 361 ++++++++++++++++++++++++++++++++++
 grub-core/kern/xen/init.c     |   2 +
 include/grub/xen.h            |   2 +
 6 files changed, 423 insertions(+)
 create mode 100644 grub-core/kern/xen/cmdline.c

diff --git a/docs/grub.texi b/docs/grub.texi
index 34b3484..cd4e539 100644
--- a/docs/grub.texi
+++ b/docs/grub.texi
@@ -3271,6 +3271,7 @@ GRUB.  Others may be used freely in GRUB configuration files.
 @menu
 * Special environment variables::
 * Environment block::
+* Passing environment variables through Xen::
 @end menu
 
 
@@ -3871,6 +3872,57 @@ using BIOS or EFI functions (no ATA, USB or IEEE1275).
 @command{grub-mkconfig} uses this facility to implement
 @samp{GRUB_SAVEDEFAULT} (@pxref{Simple configuration}).
 
+@node Passing environment variables through Xen
+@section Passing environment variables through Xen
+
+If you are using a GRUB image as the kernel for a PV or PVH Xen virtual
+machine, you can pass environment variables from Xen's dom0 to the VM through
+the Xen-provided kernel command line. When combined with a properly configured
+guest, this can be used to customize the guest's behavior on bootup via the
+VM's Xen configuration file.
+
+GRUB will parse the kernel command line passed to it by Xen during bootup.
+The command line will be split into space-delimited words. Single and
+double quotes may be used to quote words or portions of words that contain
+spaces. Single quotes will be considered part of a word if inside double
+quotes, and vice versa. Arbitrary characters may be backslash-escaped to make
+them a literal component of a word rather than being parsed as quotes or word
+separators. The command line must consist entirely of printable 7-bit ASCII
+characters and spaces. If a non-printing ASCII character is found anywhere in
+the command line, the entire command line will be ignored by GRUB. (This
+splitter algorithm is meant to behave somewhat like Bash's word splitting.)
+
+Each word should be a variable assignment in the format ``variable'' or
+``variable=value''. Variable names must contain only the characters A-Z, a-z,
+and underscore (``_''). Variable names must begin with the string
+``xen_grub_env_''. Variable values can contain arbitrary printable 7-bit
+ASCII characters and space. If any variable contains an illegal name, that
+variable will be ignored.
+
+If a variable name and value are both specified, the variable will be set to
+the specified value. If only a variable name is specified, the variable's
+value will be set to ``1''.
+
+The following is a simple example of how to use this functionality to append
+arbitrary variables to a guest's kernel command line:
+
+@example
+# In the Xen configuration file for the guest
+name = "linux_vm"
+type = "pvh"
+kernel = "/path/to/grub-i386-xen_pvh.bin"
+extra = "xen_grub_env_linux_append='loglevel=3'"
+memory = 1024
+disk = [ "file:/srv/vms/linux_vm.img,sda,w" ]
+
+# In the guest's GRUB configuration file
+menuentry "Linux VM with dom0-specified kernel parameters" @{
+    search --set=root --label linux_vm --hint hd0,msdos1
+    linux /boot/vmlinuz root=LABEL=linux_vm $@{xen_grub_env_linux_append@}
+    initrd /boot/initrd.img
+@}
+@end example
+
 @node Modules
 @chapter Modules
 
diff --git a/grub-core/Makefile.core.def b/grub-core/Makefile.core.def
index b3f7119..df0f266 100644
--- a/grub-core/Makefile.core.def
+++ b/grub-core/Makefile.core.def
@@ -248,6 +248,7 @@ kernel = {
   xen = term/xen/console.c;
   xen = disk/xen/xendisk.c;
   xen = commands/boot.c;
+  xen = kern/xen/cmdline.c;
 
   i386_xen_pvh = commands/boot.c;
   i386_xen_pvh = disk/xen/xendisk.c;
@@ -255,6 +256,7 @@ kernel = {
   i386_xen_pvh = kern/i386/xen/tsc.c;
   i386_xen_pvh = kern/i386/xen/pvh.c;
   i386_xen_pvh = kern/xen/init.c;
+  i386_xen_pvh = kern/xen/cmdline.c;
   i386_xen_pvh = term/xen/console.c;
 
   ia64_efi = kern/ia64/efi/startup.S;
diff --git a/grub-core/kern/i386/xen/pvh.c b/grub-core/kern/i386/xen/pvh.c
index 91fbca8..52020b7 100644
--- a/grub-core/kern/i386/xen/pvh.c
+++ b/grub-core/kern/i386/xen/pvh.c
@@ -352,6 +352,10 @@ grub_xen_setup_pvh (void)
   grub_xen_mm_init_regions ();
 
   grub_rsdp_addr = pvh_start_info->rsdp_paddr;
+
+  grub_strncpy ((char *) grub_xen_start_page_addr->cmd_line,
+		(const char *) pvh_start_info->cmdline_paddr,
+		GRUB_XEN_MAX_GUEST_CMDLINE);
 }
 
 grub_err_t
diff --git a/grub-core/kern/xen/cmdline.c b/grub-core/kern/xen/cmdline.c
new file mode 100644
index 0000000..8021bf8
--- /dev/null
+++ b/grub-core/kern/xen/cmdline.c
@@ -0,0 +1,361 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 2025  Free Software Foundation, Inc.
+ *
+ *  GRUB is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  GRUB is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with GRUB.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+enum splitter_state
+{
+  SPLITTER_NORMAL = 0x0,
+  SPLITTER_HIT_BACKSLASH = 0x1,
+  SPLITTER_IN_SINGLE_QUOTES = 0x2,
+  SPLITTER_IN_DOUBLE_QUOTES = 0x4,
+};
+typedef enum splitter_state splitter_state_t;
+
+/*
+ * The initial size of the current_word buffer. The buffer may be resized as
+ * needed.
+ */
+#define PARSER_BASE_WORD_SIZE 32
+
+struct parser_state
+{
+  char **words;
+  grub_size_t words_count;
+  char *current_word;
+  grub_size_t current_word_len;
+  grub_size_t current_word_pos;
+};
+typedef struct parser_state parser_state_t;
+
+static grub_err_t
+append_char_to_word (parser_state_t *ps, char c, bool allow_null)
+{
+  /*
+   * We ban any chars that are not in the ASCII printable range. If
+   * allow_null == true, we make an exception for NUL. (This is needed so that
+   * append_word_to_list can add a NUL terminator to the word).
+   */
+  if (!grub_isprint (c) && allow_null == false)
+    return GRUB_ERR_BAD_ARGUMENT;
+  else if (allow_null == true && c != '\0')
+    return GRUB_ERR_BAD_ARGUMENT;
+
+  if (ps->current_word_pos == ps->current_word_len)
+    {
+      ps->current_word = grub_realloc (ps->current_word, ps->current_word_len *= 2);
+      if (ps->current_word == NULL)
+        {
+          ps->current_word_len /= 2;
+          return grub_errno;
+        }
+    }
+
+  ps->current_word[ps->current_word_pos++] = c;
+  return GRUB_ERR_NONE;
+}
+
+static grub_err_t
+append_word_to_list (parser_state_t *ps)
+{
+  /* No-op on empty words. */
+  if (ps->current_word_pos == 0)
+    return GRUB_ERR_NONE;
+
+  if (append_char_to_word (ps, '\0', true) != GRUB_ERR_NONE)
+    grub_fatal ("couldn't append NUL terminator to word during Xen cmdline parsing");
+
+  ps->current_word_len = grub_strlen (ps->current_word) + 1;
+  ps->current_word = grub_realloc (ps->current_word, ps->current_word_len);
+  if (ps->current_word == NULL)
+    return grub_errno;
+  ps->words = grub_realloc (ps->words, ++ps->words_count * sizeof (char *));
+  if (ps->words == NULL)
+    return grub_errno;
+  ps->words[ps->words_count - 1] = ps->current_word;
+
+  ps->current_word_len = PARSER_BASE_WORD_SIZE;
+  ps->current_word_pos = 0;
+  ps->current_word = grub_malloc (ps->current_word_len);
+  if (ps->current_word == NULL)
+    return grub_errno;
+
+  return GRUB_ERR_NONE;
+}
+
+static bool
+is_key_safe (char *key, grub_size_t len)
+{
+  grub_size_t i;
+
+  for (i = 0; i < len; i++)
+    if (!grub_isalpha (key[i]) && key[i] != '_')
+      return false;
+
+  return true;
+}
+
+void
+grub_parse_xen_cmdline (void)
+{
+  parser_state_t ps = {0};
+  splitter_state_t ss = SPLITTER_NORMAL;
+
+  const char *cmdline = (const char *) grub_xen_start_page_addr->cmd_line;
+  grub_size_t cmdline_len;
+  bool cmdline_valid = false;
+  char **param_keys = NULL;
+  char **param_vals = NULL;
+  grub_size_t param_dict_len = 0;
+  grub_size_t param_dict_pos = 0;
+  char current_char = '\0';
+  grub_size_t i = 0;
+
+  /*
+   * The following algorithm is used to parse the Xen command line:
+   *
+   * - The command line is split into space-separated words.
+   *   - Single and double quotes may be used to suppress the splitting
+   *     behavior of spaces.
+   *   - Double quotes are appended to the current word verbatim if they
+   *     appear within a single-quoted string portion, and vice versa.
+   *   - Backslashes may be used to cause the next character to be
+   *     appended to the current word verbatim. This is only useful when
+   *     used to escape quotes, spaces, and backslashes, but for simplicity
+   *     we allow backslash-escaping anything.
+   * - After splitting the command line into words, each word is checked to
+   *   see if it contains an equals sign.
+   *   - If it does, it is split on the equals sign into a key-value pair. The
+   *     key is then treated as an variable name, and the value is treated as
+   *     the variable's value.
+   *   - If it does not, the entire word is treated as a variable name. The
+   *     variable's value is implicitly considered to be `1`.
+   * - All variables detected on the command line are checked to see if their
+   *   names begin with the string `xen_grub_env_`. Variables that do not pass
+   *   this check are discarded, variables that do pass this check are
+   *   exported so they are available to the GRUB configuration.
+   *
+   * This behavior is intended to somewhat mimic the splitter behavior in Bash
+   * and in GRUB's config file parser.
+   */
+
+  ps.current_word_len = PARSER_BASE_WORD_SIZE;
+  ps.current_word = grub_malloc (ps.current_word_len);
+  if (ps.current_word == NULL)
+    goto cleanup_main;
+
+  for (i = 0; i < GRUB_XEN_MAX_GUEST_CMDLINE; i++)
+    {
+      if (cmdline[i] == '\0')
+        {
+          cmdline_valid = true;
+          break;
+        }
+    }
+
+  if (cmdline_valid == false)
+    {
+      grub_error (GRUB_ERR_BAD_ARGUMENT,
+		  "command line from Xen is not NUL-terminated");
+      grub_print_error ();
+      goto cleanup_main;
+    }
+
+  cmdline_len = grub_strlen (cmdline);
+  for (i = 0; i < cmdline_len; i++)
+    {
+      current_char = cmdline[i];
+
+      /*
+       * If the previous character was a backslash, append the current
+       * character to the word verbatim
+       */
+      if (ss & SPLITTER_HIT_BACKSLASH)
+        {
+          ss &= ~SPLITTER_HIT_BACKSLASH;
+          if (append_char_to_word (&ps, current_char, false) != GRUB_ERR_NONE)
+            goto cleanup_main;
+          continue;
+        }
+
+      switch (current_char)
+        {
+        case '\\':
+          /* Backslashes escape arbitrary characters. */
+          ss |= SPLITTER_HIT_BACKSLASH;
+          break;
+
+        case '\'':
+          /*
+           * Single quotes suppress word splitting and double quoting until
+           * the next single quote is encountered.
+           */
+          if (ss & SPLITTER_IN_DOUBLE_QUOTES)
+            {
+              if (append_char_to_word (&ps, current_char, false) != GRUB_ERR_NONE)
+                goto cleanup_main;
+              break;
+            }
+
+          ss ^= SPLITTER_IN_SINGLE_QUOTES;
+          break;
+
+        case '"':
+          /*
+           * Double quotes suppress word splitting and single quoting until
+           * the next double quote is encountered.
+           */
+          if (ss & SPLITTER_IN_SINGLE_QUOTES)
+            {
+              if (append_char_to_word (&ps, current_char, false) != GRUB_ERR_NONE)
+                goto cleanup_main;
+              break;
+            }
+
+          ss ^= SPLITTER_IN_DOUBLE_QUOTES;
+          break;
+
+        case ' ':
+          /* Spaces separate words in the command line from each other. */
+          if (ss & SPLITTER_IN_SINGLE_QUOTES ||
+              ss & SPLITTER_IN_DOUBLE_QUOTES)
+            {
+              if (append_char_to_word (&ps, current_char, false) != GRUB_ERR_NONE)
+                goto cleanup_main;
+              break;
+            }
+
+          if (append_word_to_list (&ps) != GRUB_ERR_NONE)
+            goto cleanup_main;
+          break;
+
+        default:
+          if (append_char_to_word (&ps, current_char, false) != GRUB_ERR_NONE)
+            goto cleanup_main;
+        }
+    }
+
+  if (append_word_to_list (&ps) != GRUB_ERR_NONE)
+    goto cleanup_main;
+
+  param_keys = grub_malloc (ps.words_count * sizeof (char *));
+  if (param_keys == NULL)
+    goto cleanup_main;
+  param_vals = grub_malloc (ps.words_count * sizeof (char *));
+  if (param_vals == NULL)
+    goto cleanup_main;
+
+  for (i = 0; i < ps.words_count; i++)
+    {
+      char *eq_pos;
+
+      ps.current_word = ps.words[i];
+      ps.current_word_len = grub_strlen (ps.current_word) + 1;
+      eq_pos = grub_strchr (ps.current_word, '=');
+
+      if (eq_pos != NULL)
+        {
+          /*
+           * Both pre_eq_len and post_eq_len represent substring lengths
+           * without a NUL terminator.
+           */
+          grub_size_t pre_eq_len = (grub_size_t) (eq_pos - ps.current_word);
+          /*
+           * ps.current_word_len includes the NUL terminator, so we subtract
+           * one to get rid of the terminator, and one more to get rid of the
+           * equals sign.
+           */
+          grub_size_t post_eq_len = (ps.current_word_len - 2) - pre_eq_len;
+
+          if (is_key_safe (ps.current_word, pre_eq_len) == true)
+            {
+              param_dict_pos = param_dict_len++;
+              param_keys[param_dict_pos] = grub_malloc (pre_eq_len + 1);
+              if (param_keys == NULL)
+                goto cleanup_main;
+              param_vals[param_dict_pos] = grub_malloc (post_eq_len + 1);
+              if (param_vals == NULL)
+                goto cleanup_main;
+
+              grub_strncpy (param_keys[param_dict_pos], ps.current_word, pre_eq_len);
+              grub_strncpy (param_vals[param_dict_pos],
+			    ps.current_word + pre_eq_len + 1, post_eq_len);
+              param_keys[param_dict_pos][pre_eq_len] = '\0';
+              param_vals[param_dict_pos][post_eq_len] = '\0';
+            }
+        }
+      else if (is_key_safe (ps.current_word, ps.current_word_len - 1) == true)
+        {
+          param_dict_pos = param_dict_len++;
+          param_keys[param_dict_pos] = grub_malloc (ps.current_word_len);
+          if (param_keys == NULL)
+            goto cleanup_main;
+          param_vals[param_dict_pos] = grub_malloc (2);
+          if (param_vals == NULL)
+            goto cleanup_main;
+
+          grub_strncpy (param_keys[param_dict_pos], ps.current_word,
+			ps.current_word_len);
+          if (param_keys[param_dict_pos][ps.current_word_len - 1] != '\0' )
+            grub_fatal ("NUL terminator missing from key during Xen cmdline parsing");
+          grub_strcpy (param_vals[param_dict_pos], "1");
+        }
+     
+    }
+
+  for (i = 0; i < param_dict_len; i++)
+    {
+      /*
+       * Find keys that start with "xen_grub_env_" and export them
+       * as environment variables.
+       */
+      if (grub_strncmp (param_keys[i],
+			"xen_grub_env_",
+			sizeof ("xen_grub_env_") - 1) != 0)
+        continue;
+
+      if (grub_env_set (param_keys[i], param_vals[i]) != GRUB_ERR_NONE)
+        {
+          grub_printf ("warning: could not set environment variable `%s' to value `%s'\n",
+		       param_keys[i], param_vals[i]);
+          continue;
+        }
+
+      if (grub_env_export (param_keys[i]) != GRUB_ERR_NONE)
+        grub_printf ("warning: could not export environment variable `%s'",
+		     param_keys[i]);
+    }
+
+ cleanup_main:
+  for (i = 0; i < ps.words_count; i++)
+    grub_free (ps.words[i]);
+
+  for (i = 0; i < param_dict_len; i++)
+    {
+      grub_free (param_keys[i]);
+      grub_free (param_vals[i]);
+    }
+
+  grub_free (param_keys);
+  grub_free (param_vals);
+  grub_free (ps.words);
+}
diff --git a/grub-core/kern/xen/init.c b/grub-core/kern/xen/init.c
index 782ca72..69cf59f 100644
--- a/grub-core/kern/xen/init.c
+++ b/grub-core/kern/xen/init.c
@@ -581,6 +581,8 @@ grub_machine_init (void)
   grub_xendisk_init ();
 
   grub_boot_init ();
+
+  grub_parse_xen_cmdline ();
 }
 
 void
diff --git a/include/grub/xen.h b/include/grub/xen.h
index 91cb7cf..7f9efee 100644
--- a/include/grub/xen.h
+++ b/include/grub/xen.h
@@ -89,6 +89,8 @@ void grub_console_init (void);
 void grub_xendisk_fini (void);
 void grub_xendisk_init (void);
 
+void grub_parse_xen_cmdline (void);
+
 #ifdef __x86_64__
 typedef grub_uint64_t grub_xen_mfn_t;
 #else
-- 
2.50.1



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From: arraybolt3@gmail.com
To: grub-devel@gnu.org,
	xen-devel@lists.xenproject.org
Cc: Aaron Rainbolt 
Subject: [PATCH v5 2/3] include/xen: Add warning comment for cmd_line
Date: Wed, 13 Aug 2025 20:36:44 -0500
Message-ID: <20250814013645.2488043-3-arraybolt3@gmail.com>
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In-Reply-To: <20250814013645.2488043-1-arraybolt3@gmail.com>
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From: Aaron Rainbolt 

The cmd_line field of the start_info struct is not guaranteed to be
NUL-terminated, even though it is intended to contain a NUL-terminated
string. Add a warning about this in a comment so future consumers of
this field know to check it for a NUL terminator before using it.

Signed-off-by: Aaron Rainbolt 
---
 include/xen/xen.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/include/xen/xen.h b/include/xen/xen.h
index fdf0fc4..16f3fd7 100644
--- a/include/xen/xen.h
+++ b/include/xen/xen.h
@@ -823,6 +823,11 @@ struct start_info {
                                 /* (PFN of pre-loaded module if           */
                                 /*  SIF_MOD_START_PFN set in flags).      */
     unsigned long mod_len;      /* Size (bytes) of pre-loaded module.     */
+    /* 
+     * cmd_line will contain a NUL-termianted string if it contains valid
+     * data, but it MAY be invalid and not contain a NUL byte at all. Code
+     * that accesses cmd_line MUST NOT assume it is NUL-terminated.
+     */
 #define GRUB_XEN_MAX_GUEST_CMDLINE 1024
     int8_t cmd_line[GRUB_XEN_MAX_GUEST_CMDLINE];
     /* The pfn range here covers both page table and p->m table frames.   */
-- 
2.50.1



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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, Andrew Cooper ,
	"Orzel, Michal" , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Topic: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Index: AQHb8hcuzjUv9QY8PkCazI2v8DQHmbRBbryAgCA3tFA=
Date: Thu, 14 Aug 2025 03:13:11 +0000
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References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
 <20250711035106.2540522-20-Penny.Zheng@amd.com>
 <796a9251-8b4f-4266-a31e-828d4da29f54@suse.com>
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From xen-devel-bounces@lists.xenproject.org Thu Aug 14 06:33:21 2025
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Date: Thu, 14 Aug 2025 06:32:55 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 2/8] emul/vuart: introduce framework for UART emulators
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References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-3-dmukhin@ford.com>   <6953603b-8c3f-4f12-9f5e-45cb553fe8cc@suse.com>  <61aeb2a2-dc53-4f52-ab65-a9a8143a3307@suse.com>
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On Tue, Aug 12, 2025 at 08:52:18AM +0200, Jan Beulich wrote:
> On 12.08.2025 01:55, dmkhn@proton.me wrote:
> > On Mon, Aug 11, 2025 at 09:34:58AM +0200, Jan Beulich wrote:
> >> On 09.08.2025 20:55, dmkhn@proton.me wrote:
> >>> On Mon, Aug 04, 2025 at 12:11:03PM +0200, Jan Beulich wrote:
> >>>> On 31.07.2025 21:21, dmkhn@proton.me wrote:
> >>>>> @@ -354,6 +355,8 @@ static void cf_check dump_domains(unsigned char=
 key)
> >>>>>                             v->periodic_period / 1000000);
> >>>>>              }
> >>>>>          }
> >>>>> +
> >>>>> +        vuart_dump_state(d);
> >>>>
> >>>> How verbose is this going to get?
> >>>
> >>> Looks something like this:
> >>> ```
> >>> (XEN) [   88.334893] 'q' pressed -> dumping domain info (now =3D 8833=
4828303)
> >>> [..]
> >>> (XEN) [   88.335673] Virtual ns16550 (COM2) I/O port 0x02f8 IRQ#3 own=
er d0
> >>> (XEN) [   88.335681]   RX FIFO size 1024 in_prod 258 in_cons 258 used=
 0
> >>> (XEN) [   88.335689]   TX FIFO size 2048 out_prod 15 out_cons 0 used =
15
> >>> (XEN) [   88.335696]   00 RBR 02 THR 6f DLL 01 DLM 00
> >>> (XEN) [   88.335703]   01 IER 05
> >>> (XEN) [   88.335709]   02 FCR 81 IIR c1
> >>> (XEN) [   88.335715]   03 LCR 13
> >>> (XEN) [   88.335720]   04 MCR 0b
> >>> (XEN) [   88.335726]   05 LSR 60
> >>> (XEN) [   88.335731]   06 MSR b0
> >>> (XEN) [   88.335736]   07 SCR 00
> >>>
> >>> ```
> >>
> >> Definitely too much (for my taste) to put under 'q'.
> >
> > I'll try to limit the number of printed lines; register dump can be mad=
e
> > compact for sure.
>=20
> Yet even then I'm inclined to say that device specific data simply doesn'=
t
> belong here.

Ability to produce such traces was helpful during debug, TBH.

I will hide per-vuart dump_state behind CONFIG_VUART_DUMP_STATE (or alike)
so default config does not enable it.



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Subject: Re: [PATCH] misra: add ASSERT_UNREACHABLE() in default clauses
To: Julien Grall 
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "xen-devel@lists.xenproject.org" ,
 Dmytro Prokopchuk1 
References: <7cd71ed21383c189fedb3250ddde54a593f7f98b.1754944131.git.dmytro_prokopchuk1@epam.com>
 <59396fd1-ca82-4655-9dcf-ec36e0d51ffc@xen.org>
 
 <24d8591e-f669-4142-a783-c7cfea87034c@xen.org>
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On 13.08.2025 00:54, Julien Grall wrote:
> Hi Jan,
> 
> On 12/08/2025 08:32, Jan Beulich wrote:
>> On 11.08.2025 23:21, Julien Grall wrote:
>>> On 11/08/2025 21:30, Dmytro Prokopchuk1 wrote:
>>>> --- a/xen/common/grant_table.c
>>>> +++ b/xen/common/grant_table.c
>>>> @@ -330,9 +330,12 @@ shared_entry_header(struct grant_table *t, grant_ref_t ref)
>>>>            /* Returned values should be independent of speculative execution */
>>>>            block_speculation();
>>>>            return &shared_entry_v2(t, ref).hdr;
>>>> +
>>>> +    default:
>>>> +        ASSERT_UNREACHABLE();
>>>> +        break;
>>>>        }
>>>>    
>>>> -    ASSERT_UNREACHABLE();
>>>   >       block_speculation();>
>>>>        return NULL;
>>>
>>> I know you are trying to apply the MISRA rule. But this is odd that you
>>> move the ASSERT_UNREACHABLE() but then code after is still only
>>> reachable from the default. In fact, this is introducing a risk if
>>> someone decides to add a new case but then forgot to return a value.
>>>
>>> By moving the two other lines, the compiler should be able to throw an
>>> error if you forgot a return.
>>
>> I think we did discuss this pattern in the past. While moving everything up
>> to the "return" into the default: handling will please Eclair / Misra, we'll
>> then end up with no return statement at the end of a non-void function.
>> Beyond being good practice (imo) to have such a "main" return statement,
>> that's actually another rule, just one we apparently didn't accept (15.5).
> 
> Reading 15.5, this seems to be about having a single return in the 
> function. Unless I misunderstood something, this is different from what 
> you suggest.

Sue, the connection is a lose one. What I mean is that adding yet another
return _not_ at the end of the function moves use further away from 15.5
compliance.

> Anyway, my main problem with this change is that ASSERT_UNREACHABLE() is 
> moved. I could possibly settle with:
> 
> default:
>    break;
> }

Which would violate another rule, iirc (demanding that there be more than
just "break").

> ASSERT_UNREACHABLE();
> ...
> 
> But at least to me, this pattern is more difficult to read because I 
> have to look through the switch to understand the patch is only meant ot 
> be used by the "default" case.

+1

Jan


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Subject: Re: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
To: "Penny, Zheng" 
Cc: "Huang, Ray" ,
 Anthony PERARD ,
 Andrew Cooper ,
 "Orzel, Michal" , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" 
References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
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 <796a9251-8b4f-4266-a31e-828d4da29f54@suse.com>
 
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On 14.08.2025 05:13, Penny, Zheng wrote:
> [Public]
> 
>> -----Original Message-----
>> From: Jan Beulich 
>> Sent: Thursday, July 24, 2025 10:44 PM
>> To: Penny, Zheng 
>> Cc: Huang, Ray ; Anthony PERARD
>> ; Andrew Cooper ;
>> Orzel, Michal ; Julien Grall ; Roger Pau
>> Monné ; Stefano Stabellini ; xen-
>> devel@lists.xenproject.org
>> Subject: Re: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
>> xen_sysctl_pm_op for amd-cppc driver
>>
>> On 11.07.2025 05:51, Penny Zheng wrote:
>>> Introduce helper set_amd_cppc_para() and get_amd_cppc_para() to
>>> SET/GET CPPC-related para for amd-cppc/amd-cppc-epp driver.
>>>
>>> In get_cpufreq_cppc()/set_cpufreq_cppc(), we include
>>> "processor_pminfo[cpuid]->init & XEN_CPPC_INIT" condition check to
>>> deal with cpufreq driver in amd-cppc.
>>>
>>> Also, a new field "policy" has also been added in "struct xen_get_cppc_para"
>>> to describe performance policy in active mode. It gets printed with
>>> other cppc paras. Move manifest constants "XEN_CPUFREQ_POLICY_xxx" to
>>> public header to let it be used in user space tools. Also add a new
>>> anchor "XEN_CPUFREQ_POLICY_xxx" for array overrun check.
>>
>> If only they indeed had XEN_ prefixes.
>>
>>> Signed-off-by: Penny Zheng 
>>> ---
>>> v1 -> v2:
>>> - Give the variable des_perf an initializer of 0
>>> - Use the strncmp()s directly in the if()
>>> ---
>>> v3 -> v4
>>> - refactor comments
>>> - remove double blank lines
>>> - replace amd_cppc_in_use flag with XEN_PROCESSOR_PM_CPPC
>>> ---
>>> v4 -> v5:
>>> - add new field "policy" in "struct xen_cppc_para"
>>> - add new performamce policy XEN_CPUFREQ_POLICY_BALANCE
>>> - drop string comparisons with "processor_pminfo[cpuid]->init &
>> XEN_CPPC_INIT"
>>> and "cpufreq.setpolicy == NULL"
>>> - Blank line ahead of the main "return" of a function
>>> - refactor comments, commit message and title
>>> ---
>>> v5 -> v6:
>>> - remove duplicated manifest constants, and just move it to public
>>> header
>>> - use "else if" to avoid confusion that it looks as if both paths
>>> could be taken
>>> - add check for legitimate perf values
>>> - use "unknown" instead of "none"
>>> - introduce "CPUFREQ_POLICY_END" for array overrun check in user space
>>> tools
>>> +         (set_cppc->maximum > data->caps.highest_perf ||
>>> +          set_cppc->maximum < data->caps.lowest_nonlinear_perf) )
>>> +        return -EINVAL;
>>> +    /*
>>> +     * Minimum performance may be set to any performance value in the range
>>> +     * [Nonlinear Lowest Performance, Highest Performance], inclusive but must
>>> +     * be set to a value that is less than or equal to Maximum Performance.
>>> +     */
>>> +    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM &&
>>> +         (set_cppc->minimum < data->caps.lowest_nonlinear_perf ||
>>> +          (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM &&
>>> +           set_cppc->minimum > set_cppc->maximum) ||
>>> +          (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
>>
>> Hmm, I find this confusing to read, and was first thinking the ! was wrong here. Imo
>> such is better expressed with the conditional operator:
>>
>>
>>           set_cppc->minimum > (set_cppc->set_params &
>> XEN_SYSCTL_CPPC_SET_MAXIMUM
>>                                ? set_cppc->maximum
>>                                : data->req.max_perf)
>>
> 
> Thx, understood!
> 
>> Which also makes it easier to spot that here you use data->req, when in the
>> minimum check you use data->caps. Why this difference?
>>
> 
>  minimum check has two boundary check,
> left boundary check is against data->caps.lowest_nonlinear_perf. And right boundary check is against data->req.max_perf. As it shall not only not larger than caps.highest_perf , but also req.max_perf. The relation between max_perf and highest_perf is validated in the maximum check. So here, we are only considering max_perf

I still don't get why one check is against capabilities (permitted values) why the
other is again what's currently set.

Jan


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Subject: Re: [PATCH v3] EFI/runtime: switch to xv[mz]alloc_array()
To: "Daniel P. Smith" 
Cc: Marek Marczykowski ,
 "xen-devel@lists.xenproject.org" 
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On 14.08.2025 02:29, Daniel P. Smith wrote:
> On 8/12/25 02:12, Jan Beulich wrote:
>> On 12.08.2025 02:19, Daniel P. Smith wrote:
>>> On 7/23/25 09:39, Jan Beulich wrote:
>>>> Use the more "modern" form, thus doing away with effectively open-coding
>>>> xmalloc_array() at the same time. While there is a difference in
>>>> generated code, as xmalloc_bytes() forces SMP_CACHE_BYTES alignment, if
>>>> code really cared about such higher than default alignment, it should
>>>> request so explicitly.
>>>
>>> While I don't object to the change itself, I think this description is a
>>> bit over simplification of the change. If the allocation is under
>>> PAGE_SIZE, then they are equivalent, but if it is over the page size
>>> there are a few more differences than just cache alignment. It
>>> completely changes the underlying allocator. I personally also find it a
>>> bit of a stretch to call xmalloc_bytes(size) an open coded version of
>>> xmalloc_array(char, size).
>>
>> My take is that xmalloc_bytes() should never have existed. Hence why I
>> didn't add xzmalloc_bytes() when introducing that family of interfaces.
> 
> Right, which would be a valid argument for replacing it with 
> xmalloc_array(). Though, I would note that there is an xzalloc_bytes(). 
> My concern was that you stated there was an open coding, which had me 
> expecting there was a line of the form, xmanlloc_bytes(count * 
> size_of_something bigger), being replaced by 
> xvmalloc_arryay(something_bigger, count).

Both fir this and ...

> IMHO, while the C spec does specify char as 1 byte and thus 
> interchangeable, I would agree that from a contextual perspective, 
> xmalloc_array() is the more appropriate call. The use of the allocation 
> is a character array and not a chunk of bytes for an arbitrary buffer.

... for this: Hence my wording using "effectively".

>>> With a stronger description of the change,
>>
>> So what exactly do you mean by "stronger"? I can add that in the unlikely
>> event that one of the allocations is (near) PAGE_SIZE or larger, we now
>> wouldn't require contiguous memory anymore. Yet based on your comment at
>> the top I'm not quite sure if that's what you're after and/or enough to
>> satisfy your request.
> 
> The phrasing stronger was meant to be more clear on the change/effect, 
> specifically that the underlying allocator is being changed when the 
> allocation is greater than a PAGE_SIZE. Not necessarily a long 
> explanation, just the fact that the allocation will be coming from the 
> dom heap allocator as opposed to the xen heap allocator. There are 
> implications to changing the allocater, e.g.,  at a minimum the 
> allocation order and nonphysical vs. physically contiguous effects. 
> Having it noted in the commit makes it more obvious what this change is 
> actually doing. Which may not be obvious when seeing the simple line 
> changes occurring in the diff. Later, if there is an unexpected 
> consequence caused by this change, a stronger commit will be helpful 
> with the bisection investigations.

First: I don't think each and every such change (there are going to be many)
should re-explain the switch to the xvmalloc() family of functions. This is
already stated clearly at the top of xvmalloc.h: Over time, the entire code
base is meant to be switched.

Beyond that, to achieve the stronger wording you're after, would it perhaps
suffice to have the first sentence say "..., thus also doing away ..."?
Otherwise, may I ask that you please make a more concrete suggestion?

Jan


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Subject: Re: Consider changing CONFIG_ACPI default on ARM?
To: Elliott Mitchell 
Cc: xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
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On 06.08.2025 06:30, Elliott Mitchell wrote:
> On Tue, Jul 01, 2025 at 10:01:13PM +0200, Paul Leiber wrote:
>>
>> Unfortunately, I don't have a direct answer to the question (as is so often
>> the case, due to my limited knowledge and experience). However, I am
>> successfully running Xen on a RPi 4 (mostly, except for some VLAN related
>> networking issues).
>>
>> I used instructions in [1] to install vanilla Debian on the RPi, including
>> UEFI boot and grub. I then compiled Xen with expert options and ACPI
>> enabled.
>>
>> I don't know if there are better solutions. For example, I suffer from the
>> fact that I2C doesn't work when using UEFI boot on a RPi. Nowadays, Debian
>> provides their own vanilla Debian images for RPi and with working I2C, but
>> these images are using a different boot method that I didn't know how to use
>> with Xen.  So far, the procedure described above seems to be the easiest
>> solution for me.
> 
> 
>> [1] https://forums.raspberrypi.com/viewtopic.php?t=282839
>>
>> Am 30.06.2025 um 12:35 schrieb Sumit Semwal:
>>>
>>> I've just begun to experiment with the Raspberry Pi 5, trying to run a
>>> simple xen + Dom0 setup, using uBoot, and the bookworm based Rpi
>>> distro.
>>>
>>> I've tried combinations of the following setup:
>>>
>>> 1. prebuilt Rpi5 kernel + dtbs, and have also tried to build them from
>>> source [1]
>>> 2. Xen from upstream [2] and xen-troops [3]
>>> 3. upstream uBoot from [4]
>>>
>>> but with the same result: [short log below; I can provide a fuller log
>>> if needed]
>>>
>>> (XEN) DT: ** translation for device /axi/msi-controller@1000130000 **
>>> (XEN) DT: bus is default (na=2, ns=2) on /axi
>>> (XEN) DT: translating address:<3> 000000ff<3> fffff000<3>
>>> (XEN) DT: parent bus is default (na=2, ns=1) on /
>>> (XEN) DT: walking ranges...
>>> (XEN) DT: default map, cp=0, s=1000000000, da=fffffff000
>>> (XEN) DT: default map, cp=1000000000, s=100000000, da=fffffff000
>>> (XEN) DT: default map, cp=1400000000, s=400000000, da=fffffff000
>>> (XEN) DT: default map, cp=1800000000, s=400000000, da=fffffff000
>>> (XEN) DT: default map, cp=1c00000000, s=400000000, da=fffffff000
>>> (XEN) DT: not found !
>>> (XEN) Unable to retrieve address 1 for /axi/msi-controller@1000130000
>>> (XEN) Device tree generation failed (-22).
>>> (XEN) debugtrace_dump() global buffer starting
>>> 1 cpupool_create(pool=0,sched=6)
>>> 2 Created cpupool 0 with scheduler SMP Credit Scheduler rev2 (credit2)
>>> 3 cpupool_add_domain(dom=0,pool=0) n_dom 1 rc 0
>>> (XEN) wrap: 0
>>> (XEN) debugtrace_dump() global buffer finished
>>> (XEN)
>>> (XEN) ****************************************
>>> (XEN) Panic on CPU 0:
>>> (XEN) Could not set up DOM0 guest OS (rc = -22)
>>> (XEN) ****************************************
>>>
>>>
>>> I'm certain I'm missing something, but before I delve deeper, I just
>>> wanted to ask if this is a known issue, and if so, are there any
>>> workarounds or solutions available for this?
>>>
>>> Any help about this is highly appreciated!
>>>
>>> Thanks and Best regards,
>>> Sumit.
>>>
>>> [1]:  https://github.com/raspberrypi/linux rpi-6.12.y branch
>>> [2]: git://xenbits.xen.org/xen.git - main branch
>>> [3] xen-troops https://github.com/xen-troops/xen - rpi5_dev branch
>>> [4]: https://github.com/u-boot/u-boot.git master branch
> 
> Ultimately Debian is choosing to leave most defaults alone.  So far the
> Xen developers have left CONFIG_ACPI defaulting to off on ARM*.  The
> Debian project doesn't have paid people to support Raspberry PI hardware,
> despite being rather common.  As a result there aren't any official
> Raspberry PI images, but people associated with Tianocore have gotten
> generic images to boot on Raspberry PI hardware.
> 
> I'm unsure of the likelihood of getting the Debian maintainers to
> override the default.  Yet due being by far the simplest way to install
> Debian and Xen on a very common ARM64 platform, perhaps the Xen
> developers should consider changing?

In an open source project everyone is a developer. There is a
significant amount of work someone needs to pick up to change this
SUPPORT.md entry:

### Host ACPI (via Domain 0)

    Status, x86 PV: Supported
    Status, ARM: Experimental

Parties interested in changing the support status of any component are the
primary candidates to actually carry out the necessary work.

Jan


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On 12.08.2025 18:18, Roger Pau Monné wrote:
> On Mon, Aug 11, 2025 at 12:49:57PM +0200, Jan Beulich wrote:
>> @@ -339,9 +340,12 @@ int main(int argc, char **argv)
>>      (void)lseek(infd, in64_phdr.p_offset, SEEK_SET);
>>      dat_siz = (uint32_t)in64_phdr.p_filesz;
>>  
>> -    /* Do not use p_memsz: it does not include BSS alignment padding. */
>> -    /*mem_siz = (uint32_t)in64_phdr.p_memsz;*/
>> -    mem_siz = (uint32_t)(final_exec_addr - in64_phdr.p_vaddr);
>> +    /*
>> +     * We don't pad .bss in the linker script, but during early boot we map
>> +     * the Xen image using 2M pages.  To avoid running into adjacent non-RAM
>> +     * regions, pad the segment to the next 2M boundary.
> 
> Won't it be easier to pad in the linker script?  We could still have
> __bss_end before the padding, so that initialization isn't done to the
> extra padding area.  Otherwise it would be helpful to mention why the
> padding must be done here (opposed to being done in the linker
> script).

The way the linker script currently is written doesn't lend itself to do
the padding there: It would either mean to introduce an artificial
padding section (which I'd dislike), or it would result in _end[] and
__2M_rwdata_end[] also moving, which pretty clearly we don't want. Maybe
there are other options that I simply don't see.

A further complication would be xen.efi's .reloc, which we don't want to
needlessly move either. That may be coverable by pr-processor
conditionals, but I wanted to mention the aspect nevertheless.

Jan


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On 12.08.2025 18:30, Roger Pau Monné wrote:
> On Mon, Aug 11, 2025 at 12:50:23PM +0200, Jan Beulich wrote:
>> The unmapping part would have wanted to cover UNUSABLE regions as well,
>> and it would now have been necessary for space outside the low 16Mb
>> (wherever Xen is placed). However, with everything up to the next 2Mb
>> boundary now properly backed by RAM, we don't need to unmap anything
>> anymore: Space up to __2M_rwdata_end[] is properly reserved, whereas
>> space past that mark (up to the next 2Mb boundary) is ordinary RAM.
> 
> Oh, I see, so this was done to unmap trailing space when the Xen image
> region is mapped using 2M pages.
> 
>> While there, limit the scopes of involved variables.
>>
>> Signed-off-by: Jan Beulich 
> 
> Acked-by: Roger Pau Monné 

Thanks.

>> @@ -292,12 +290,17 @@ void __init arch_init_memory(void)
>>       * case the low 1MB.
>>       */
>>      BUG_ON(pvh_boot && trampoline_phys != 0x1000);
>> -    for ( i = 0; i < 0x100; i++ )
>> +    for ( unsigned int i = 0; i < MB(1) >> PAGE_SHIFT; i++ )
> 
> I would use PFN_DOWN() rather than the shift, but that's just my
> preference.

Oh, yes, fine with me.

Jan


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Subject: Re: [PATCH v16 1/4] xen/domain: unify domain ID allocation
To: dmkhn@proton.me
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On 13.08.2025 00:30, dmkhn@proton.me wrote:
> From: Denis Mukhin  
> 
> Currently, there are two different domain ID allocation implementations:
> 
>   1) Sequential IDs allocation in dom0less Arm code based on max_init_domid;
> 
>   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
>      max_init_domid (both Arm and x86).
> 
> The domain ID allocation covers dom0 or late hwdom, predefined domains,
> post-boot domains, excluding Xen system domains (domid >=
> DOMID_FIRST_RESERVED).
> 
> It makes sense to have a common helper code for such task across architectures
> (Arm and x86) and between dom0less / toolstack domU allocation.
> 
> Note, fixing dependency on max_init_domid is out of scope of this patch.
> 
> Wrap the domain ID allocation as an arch-independent function domid_alloc() in
> new common/domid.c based on the bitmap.
> 
> Allocation algorithm:
> - If an explicit domain ID is provided, verify its availability and use it if
>   ID is not used;
> - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1],
>   starting from the last used ID.
>   Implementation guarantees that two consecutive calls will never return the
>   same ID. ID#0 is reserved for the first boot domain (currently, dom0) and
>   excluded from the allocation range.
> 
> Remove is_free_domid() helper as it is not needed now.
> 
> No functional change intended.
> 
> Signed-off-by: Denis Mukhin 
> Reviewed-by: Julien Grall 
> Reviewed-by: Alejandro Vallejo 
> ---
> Changes since v15:
> - fixup for check after the first pass in the bitarray in domid_alloc()
> - trivial renaming for the local variable in domid_alloc()
> - kept Julien's R-b, added Alejandro's R-b

Just to mention: My take is that this kind of a fix ought to invalidate all
earlier R-b. It's not just a cosmetic change, after all.

Jan


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Subject: Re: [Coverity complaint] Re: [PATCH v5] pdx: introduce a new
 compression algorithm based on region offsets
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Cc: xen-devel@lists.xenproject.org,
 Oleksii Kurochko ,
 Community Manager ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini ,
 Andrew Cooper 
References: <20250812150624.64898-1-roger.pau@citrix.com>
 
 
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On 13.08.2025 14:41, Roger Pau Monné wrote:
> On Wed, Aug 13, 2025 at 12:47:37PM +0100, Andrew Cooper wrote:
>> On 12/08/2025 4:06 pm, Roger Pau Monne wrote:
>>> Signed-off-by: Roger Pau Monné 
>>
>> Not this patch, but this is probably the best place to report it.
>>
>> https://scan5.scan.coverity.com/#/project-view/30554/10426?selectedIssue=1662707
>>
>> Something you did in the series made enough changes in
>> pfn_pdx_compression_setup() for Coverity to start reporting an issue in
>> some decade-old code.
>>
>> The complaint is on line:
>>
>> 277    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
>> CID 1662707: (#1 of 1): Bad bit shift operation (BAD_SHIFT)
>>
>> 34. large_shift: In expression 0x1000 << bottom_shift, left shifting by more than 31 bits
>> has undefined behavior. The shift amount, bottom_shift, is as much as 63.
>>
>>
>> The relevant part of earlier analysis seems to be the "i >=
>> BITS_PER_LONG" check in the order loop, causing Coverity to think that i
>> can be up to 63.
> 
> Yes, I've also got the email.  This is existing code, so the issue
> wasn't introduced by the previous patches, it's probably result of
> the code movement that Coverity picked it up.
> 
> I will send a patch to fix this.

Isn't it simply because this file is now also built for a toolstack side
test?

Jan


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Subject: Re: [PATCH] pdx: cast PAGE_SIZE value ahead of shifting
To: Roger Pau Monne 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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On 13.08.2025 14:55, Roger Pau Monne wrote:
> --- a/xen/common/pdx.c
> +++ b/xen/common/pdx.c
> @@ -288,7 +288,7 @@ bool __init pfn_pdx_compression_setup(paddr_t base)
>  
>      pfn_pdx_hole_shift  = hole_shift;
>      pfn_pdx_bottom_mask = (1UL << bottom_shift) - 1;
> -    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
> +    ma_va_bottom_mask   = ((paddr_t)PAGE_SIZE << bottom_shift) - 1;

Given

#define PAGE_SIZE           (_AC(1,L) << PAGE_SHIFT)

this shouldn't be needed, except maybe for Arm32. There, however, ...

>      pfn_hole_mask       = ((1UL << hole_shift) - 1) << bottom_shift;

... this and the shift immediately ahead would also be a problem afaict,
which makes me conclude this isn't what Coverity has looked at. I expect
the problem is with the toolstack side definition of PAGE_SIZE, which imo
would rather be addressed there. (And yes, I'm pretty averse to arbitrary
casts like this being introduced.)

Jan


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Subject: Re: [PATCH] x86/pvh: update "Host ACPI" support status
To: Roger Pau Monne 
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 Anthony PERARD ,
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On 13.08.2025 11:32, Roger Pau Monne wrote:
> For x86 PVH dom0 makes uses of the host ACPI tables, and hence the status
> of Host ACPI entry should have been updated to reflect that PVH dom0 is now
> supported, and Host ACPI support is not one of the caveats.

Well, not explicitly, but seeing changes like 6378909b41c4 ("x86/PVH: expose
OEMx ACPI tables to Dom0") I'm not convinced we're there yet.

Jan


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Date: Thu, 14 Aug 2025 09:26:53 +0200
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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
 traps-setup.c
To: Andrew Cooper 
Cc: Xen-devel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Nicola Vetrini 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-10-andrew.cooper3@citrix.com>
 <80285a06f5d4fb3bd3e378317cca61ca@bugseng.com>
 <7e906964-b07d-4205-a683-e665f19d5edc@citrix.com>
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From: Jan Beulich 
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On 13.08.2025 13:36, Andrew Cooper wrote:
> On 12/08/2025 10:43 am, Nicola Vetrini wrote:
>> On 2025-08-08 22:23, Andrew Cooper wrote:
>>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>>> index 8ca379c9e4cb..13b8fcf0ba51 100644
>>> --- a/xen/arch/x86/traps-setup.c
>>> +++ b/xen/arch/x86/traps-setup.c
>>> @@ -19,6 +20,124 @@ boolean_param("ler", opt_ler);
>>>
>>>  void nocall entry_PF(void);
>>>
>>> +/*
>>> + * Sets up system tables and descriptors for IDT devliery.
>>> + *
>>> + * - Sets up TSS with stack pointers, including ISTs
>>> + * - Inserts TSS selector into regular and compat GDTs
>>> + * - Loads GDT, IDT, TR then null LDT
>>> + * - Sets up IST references in the IDT
>>> + */
>>> +static void load_system_tables(void)
>>> +{
>>> +    unsigned int i, cpu = smp_processor_id();
>>> +    unsigned long stack_bottom = get_stack_bottom(),
>>> +        stack_top = stack_bottom & ~(STACK_SIZE - 1);
>>> +    /*
>>> +     * NB: define tss_page as a local variable because clang 3.5
>>> doesn't
>>> +     * support using ARRAY_SIZE against per-cpu variables.
>>> +     */
>>> +    struct tss_page *tss_page = &this_cpu(tss_page);
>>> +    idt_entry_t *idt = this_cpu(idt);
>>> +
>>
>> Given the clang baseline this might not be needed anymore?
> 
> Hmm.  While true, looking at 51461114e26, the code is definitely better
> written with the tss_page variable and we wouldn't want to go back to
> the old form.
> 
> I think that I'll simply drop the comment.
> 
> ~Andrew
> 
> P.S.
> 
> Generally speaking, because of the RELOC_HIDE() in this_cpu(), any time
> you ever want two accesses to a variable, it's better (code gen wise) to
> construct a pointer to it and use the point multiple times.
> 
> I don't understand why there's a RELOC_HIDE() in this_cpu().  The
> justification doesn't make sense, but I've not had time to explore what
> happens if we take it out.

There's no justification in xen/percpu.h?

My understanding is that we simply may not expose any accesses to per_cpu_*
variables directly to the compiler, or there's a risk that it might access
the "master" variable (i.e. CPU0's on at least x86).

Jan


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Subject: Re: Consider changing CONFIG_ACPI default on ARM?
To: Jan Beulich 
Cc: Elliott Mitchell , Xen-users , 
	xen-devel@lists.xenproject.org, Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Paul Leiber 
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Jan Beulich  schrieb am Do., 14. Aug. 2025, 08:55:

> On 06.08.2025 06:30, Elliott Mitchell wrote:
> > On Tue, Jul 01, 2025 at 10:01:13PM +0200, Paul Leiber wrote:
> >>
> >> Unfortunately, I don't have a direct answer to the question (as is so
> often
> >> the case, due to my limited knowledge and experience). However, I am
> >> successfully running Xen on a RPi 4 (mostly, except for some VLAN
> related
> >> networking issues).
> >>
> >> I used instructions in [1] to install vanilla Debian on the RPi,
> including
> >> UEFI boot and grub. I then compiled Xen with expert options and ACPI
> >> enabled.
> >>
> >> I don't know if there are better solutions. For example, I suffer from
> the
> >> fact that I2C doesn't work when using UEFI boot on a RPi.
>

Snipped:
Xen panicking on a $100 platform that is the planet wide reference for
commodity/community SBC.
Reported by someone with just questions and an obvious suggestion to maybe
move things forward.

>>> I'm certain I'm missing something, but before I delve deeper, I just
> >>> wanted to ask if this is a known issue, and if so, are there any
> >>> workarounds or solutions available for this?
> >>>
> >>> Any help about this is highly appreciated!
> >>>
> >>> Thanks and Best regards,
> >>> Sumit.
> >>>
> >>> [1]:  https://github.com/raspberrypi/linux rpi-6.12.y branch
> >>> [2]: git://xenbits.xen.org/xen.git - main branch
> >>> [3] xen-troops https://github.com/xen-troops/xen - rpi5_dev branch
> >>> [4]: https://github.com/u-boot/u-boot.git master branch
> >
> > Ultimately Debian is choosing to leave most defaults alone.  So far
>
[...]

> > I'm unsure of the likelihood of getting the Debian maintainers to
> > override the default.  Yet due being by far the simplest way to install
> > Debian and Xen on a very common ARM64 platform, perhaps the Xen
> > developers should consider changing?
>
> In an open source project everyone is a developer. There is a
> significant amount of work someone needs to pick up to change this
> SUPPORT.md entry:
>
> ### Host ACPI (via Domain 0)
>
>     Status, x86 PV: Supported
>     Status, ARM: Experimental
>
> Parties interested in changing the support status of any component are the
> primary candidates to actually carry out the necessary work.
>
> Jan
>

The wording matters, experimental tells a different story of status and
ownership and activity.
It implies someone has brought it that far and wishes for experimenting and
feedback.
It implies that the experiment is ongoing.
It implies that good results would be noted and then it's likely that its
brought to a supported state.
It implies someone is looking at the results.

It's not sufficient to just tell someone "yeah if you care you're in the
best position to change that support status".
That status was written there and summarised based on certain criteria
which are historically a problem. How many xen/arm versions were there?
Mips? How many IB implementations, how many FT clones, how many versions of
whatever piece in the project.
Many parties have cared and contributed stuff that didn't ever get anywhere
because they were never told what other steps they need to take or that
there's simply not enough people around to review those 100k lines of
whatever.

As long as theres no better insight than experimental no experimenting
party can know if someone else is working on their issue other than them
asking here.
Telling them hey, actually that's YOU and your BEST approach is to be or
wait for someone with the resources to change this, oh BTW, really massive
tasks situation.

Some examples for what we could have named things over the last 20 years
Experimental with no HCL or near term roadmap. Experimental drop with no
current activity
Experimental, stale
Experimental with assumption to later integrate
Experimental and tentative, will be proceed only with other partes
involvement
Experimental, waiting for feedback
Experimental, lacking hw support

Be honest and be kind to people that try to fix one little piece when
you're sitting on a pile of broken castles. If everyone is a developer we
ought to enable everyone to help.

I'm gonna unsubscribe at last. I'm old and it gets too repetitive.

Flo


--

>


the purpose of libvirt is to provide an abstraction layer hiding all xen
features added since 2006 until they were finally understood and copied by
the kvm devs.

>

--000000000000f63b05063c4e3f20
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable






    Jan Beulich <jbeulich@suse.com> schrieb am Do., 14. Aug. 20=
25, 08:55:
    On 06=
.08.2025 06:30, Elliott Mitchell wrote:
    
> On Tue, Jul 01, 2025 at 10:01:13PM +0200, Paul Leiber wrote:
    
>>
    
>> Unfortunately, I don't have a direct answer to the question (a=
s is so often
    
>> the case, due to my limited knowledge and experience). However, I =
am
    
>> successfully running Xen on a RPi 4 (mostly, except for some VLAN =
related
    
>> networking issues).
    
>>
    
>> I used instructions in [1] to install vanilla Debian on the RPi, i=
ncluding
    
>> UEFI boot and grub. I then compiled Xen with expert options and AC=
PI
    
>> enabled.
    
>>
    
>> I don't know if there are better solutions. For example, I suf=
fer from the
    
>> fact that I2C doesn't work when using UEFI boot on a RPi.=C2=
=A0

    Snipped:
    Xen panicking on=
 a $100 platform that is the planet wide reference for commodity/community =
SBC.
    Reported by someone with just questions and an =
obvious suggestion to maybe move things forward.
    <=
blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-l=
eft:1px solid rgb(204,204,204);padding-left:1ex">
>>> I'm certain I'm missing something, but before I delve =
deeper, I just
    
>>> wanted to ask if this is a known issue, and if so, are there a=
ny
    
>>> workarounds or solutions available for this?
    
>>>
    
>>> Any help about this is highly appreciated!
    
>>>
    
>>> Thanks and Best regards,
    
>>> Sumit.
    
>>>
    
>>> [1]:=C2=A0 https://github.com/raspberryp=
i/linux rpi-6.12.y branch
    
>>> [2]: git://xenbits.xen.org/xen.git - main =
branch
    
>>> [3] xen-troops https://github.com/xen-troop=
s/xen - rpi5_dev branch
    
>>> [4]: https://github.com/u-boot/u-boot.gi=
t master branch
    
> 
    
> Ultimately Debian is choosing to leave most defaults alone.=C2=A0 So f=
ar=C2=A0
    [...]
    
> I'm unsure of the likelihood of getting the Debian maintainers to<=
br>
> override the default.=C2=A0 Yet due being by far the simplest way to i=
nstall
    
> Debian and Xen on a very common ARM64 platform, perhaps the Xen
    
> developers should consider changing?
    

    
In an open source project everyone is a developer. There is a
    
significant amount of work someone needs to pick up to change this
    
SUPPORT.md entry:
    

    
### Host ACPI (via Domain 0)
    

    
=C2=A0 =C2=A0 Status, x86 PV: Supported
    
=C2=A0 =C2=A0 Status, ARM: Experimental
    

    
Parties interested in changing the support status of any component are the<=
br>
primary candidates to actually carry out the necessary work.
    

    
Jan

    The wording matters, experimental tells a different story of status and =
ownership and activity.
    It implies someone has broug=
ht it that far and wishes for experimenting and feedback.
    It implies that the experiment is ongoing.
    It =
implies that good results would be noted and then it's likely that its =
brought to a supported state.
    It implies someone is =
looking at the results.

    =
It's not sufficient to just tell someone "yeah if you care you'=
;re in the best position to change that support status".
    That status was written there and summarised based on certain cri=
teria which are historically a problem. How many xen/arm versions were ther=
e? Mips? How many IB implementations, how many FT clones, how many versions=
 of whatever piece in the project.
    Many parties have=
 cared and contributed stuff that didn't ever get anywhere because they=
 were never told what other steps they need to take or that there's sim=
ply not enough people around to review those 100k lines of whatever.
    <=
div dir=3D"auto">
    As long as theres no better in=
sight than experimental no experimenting party can know if someone else is =
working on their issue other than them asking here.
    =
Telling them hey, actually that's YOU and your BEST approach is to be o=
r wait for someone with the resources to change this, oh BTW, really massiv=
e tasks situation.=C2=A0

    Some examples for what we could have named things over the last 20 years
    Experimental with no HCL or near term roadmap. Experi=
mental drop with no current activity=C2=A0
    Experimen=
tal, stale
    Experimental with assumption to later int=
egrate
    Experimental and tentative, will be proceed o=
nly with other partes involvement=C2=A0
    Experimental=
, waiting for feedback
    Experimental, lacking hw supp=
ort

    Be honest and be kin=
d to people that try to fix one little piece when you're sitting on a p=
ile of broken castles. If everyone is a developer we ought to enable everyo=
ne to help.

    I'm gonn=
a unsubscribe at last. I'm old and it gets too repetitive.

    Flo


    --

    =



    t=
he purpose of libvirt is to provide an abstraction layer hiding all xen fea=
tures added since 2006 until they were finally understood and copied by the=
 kvm devs.
    

--000000000000f63b05063c4e3f20--


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Subject: Re: [PATCH 13/22] x86: FRED enumerations
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 13.08.2025 14:28, Andrew Cooper wrote:
> On 08/08/2025 9:23 pm, Andrew Cooper wrote:
>> diff --git a/xen/arch/x86/Kconfig b/xen/arch/x86/Kconfig
>> index a45ce106e210..90cbad13a7c7 100644
>> --- a/xen/arch/x86/Kconfig
>> +++ b/xen/arch/x86/Kconfig
>> @@ -57,6 +57,10 @@ config HAS_CC_CET_IBT
>>  	# Retpoline check to work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654
>>  	def_bool $(cc-option,-fcf-protection=branch -mmanual-endbr -mindirect-branch=thunk-extern) && $(as-instr,endbr64)
>>  
>> +config HAS_AS_FRED
>> +	# binutils >= 2.41 or LLVM >= 19
>> +	def_bool $(as-instr,eretu;lkgs %ax)
>> +
>>  menu "Architecture Features"
>>  
>>  source "arch/x86/Kconfig.cpu"
>> diff --git a/xen/arch/x86/include/asm/asm-defns.h b/xen/arch/x86/include/asm/asm-defns.h
>> index 61a5faf90446..2e5200b94b82 100644
>> --- a/xen/arch/x86/include/asm/asm-defns.h
>> +++ b/xen/arch/x86/include/asm/asm-defns.h
>> @@ -4,6 +4,15 @@
>>      .byte 0x0f, 0x01, 0xfc
>>  .endm
>>  
>> +#ifndef CONFIG_HAS_AS_FRED
>> +.macro eretu
>> +    .byte 0xf3, 0x0f, 0x01, 0xca
>> +.endm
>> +.macro erets
>> +    .byte 0xf2, 0x0f, 0x01, 0xca
>> +.endm
>> +#endif
> 
> Seeing as I know you are going to be unhappy with the Kconfig...

Well, we've got several, so adding one more isn't going to be the end of
the world. What we really need to do is finally settle for one method,
and then switch everything over to whatever it is going to be. I've
taken note to set up another design session on the topic in San Jose.

> I think I'm dev complete on the PV support now, and there's not an LKGS
> in sight.
> 
> We don't strictly need the conditional in asm-defns.h, and if we don't
> need it in C either then we can drop the Kconfig entirely.

Yeah, might be best for now.

Jan


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, Andrew Cooper ,
	"Orzel, Michal" , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Topic: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Index: AQHb8hcuzjUv9QY8PkCazI2v8DQHmbRBbryAgCA3tFCAAEHpAIAADdDQ
Date: Thu, 14 Aug 2025 07:34:25 +0000
Message-ID:
 
References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
 <20250711035106.2540522-20-Penny.Zheng@amd.com>
 <796a9251-8b4f-4266-a31e-828d4da29f54@suse.com>
 
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Subject: Re: [XEN PATCH 2/2] Address violation of MISRA C Rule 13.1 involving
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To: Nicola Vetrini 
Cc: sstabellini@kernel.org, consulting@bugseng.com,
 dmytro_prokopchuk1@epam.com, andrew.cooper3@citrix.com,
 Doug Goldstein , xen-devel@lists.xenproject.org
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On 08.08.2025 23:40, Nicola Vetrini wrote:
> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -437,6 +437,10 @@ write or not"
>  # Series 13
>  #
>  
> +-doc_begin="Consider the asm instruction to read an Arm system register to have no side effects."
> +-asm_properties+={"asm(any())&&child(text, ast_field(value,^mrs\\s+%0.*$))", {no_side_effect}}
> +-doc_end

Is this actually strict enough to not allow multiple instructions in the asm(),
where some of the others would yield side effects we actually need to respect?

Jan


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Subject: Re: [PATCH] x86/cpu-policy: Drop workaround for pre-GCC-5 PIC issue
To: Andrew Cooper 
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On 14.08.2025 01:05, Andrew Cooper wrote:
> GCC 5.1 is the minimum supported toolchain version now.  Drop the workaround
> for the PIC hard register in earlier versions.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 



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Subject: Re: [XEN PATCH 3/3] xen/efi: efibind: Drop alternative define for old
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On 14.08.2025 00:39, Andrew Cooper wrote:
> On 13/08/2025 8:12 pm, nicola.vetrini@gmail.com wrote:
>> From: Nicola Vetrini 
>>
>> Since the toolchain baseline for GCC is 5.1, there is no need for
>> this case.
>>
>> Signed-off-by: Nicola Vetrini 
>> ---
>> Mentioned in https://gitlab.com/xen-project/xen/-/issues/201
> 
> I personally am in favour of this change, but in the past there has been
> objection to changing this header it is vendered from elsewhere.

The two lines Nicola is taking out altogether were our additions already
anyway. Playing with them ought to be fine. Context may better be left
intact. I'd like to note though that in gnuefi the detection logic has
changed, too. Maintainers may want to sync that.

As to me, earlier on, objecting to fiddling with imported files here:
Now that maintainership has changed, the new maintainers will need to
make up their take on this.

Jan


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To: nicola.vetrini@gmail.com
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On 13.08.2025 21:12, nicola.vetrini@gmail.com wrote:
> From: Nicola Vetrini 
> 
> The toolchain baseline for GCC is 5.1, which supports _Static_assert
> in c99 mode

Hmm, interesting. I can confirm the behavior, but isn't this a bug? There's no
_Static_assert() in plain C99. Respective notes in the "Changes, New Features,
and Fixes" are also saying otherwise: https://gcc.gnu.org/gcc-4.6/changes.html
has "This support may be selected with -std=c1x, or -std=gnu1x for C1X with
GNU extensions." Nothing new is said in any of the respective documents up to
the release of gcc5. (In fact, the compiler accepts the construct even with
-std=c89.)

Our misra/C-language-toolchain.rst refers to a section in gcc12's doc which
doesn't mention _Static_assert() at all, afaics.

Jan


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Hi all,

This series is related to
"[PATCH 0/5] Third series for R82 MPU support". There is no build dependency
between the two series.

At the end of these 2 series, R82 and R52 boot till the same point
(approximately).

Kind regards,
Ayan

Ayan Kumar Halder (2):
  arm/mpu: Enable is_xen_heap_page and is_xen_heap_mfn for ARM_32
  arm/mpu: Disable map_domain_page for MPU

 xen/arch/arm/Kconfig              |  2 +-
 xen/arch/arm/include/asm/mm.h     |  2 +-
 xen/arch/arm/include/asm/mpu/mm.h |  5 ----
 xen/arch/arm/mpu/Makefile         |  1 -
 xen/arch/arm/mpu/domain-page.c    | 45 -------------------------------
 5 files changed, 2 insertions(+), 53 deletions(-)
 delete mode 100644 xen/arch/arm/mpu/domain-page.c

-- 
2.25.1



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From: Ayan Kumar Halder 
To: 
CC: Ayan Kumar Halder , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , "Volodymyr
 Babchuk" 
Subject: [PATCH v2 2/2] arm/mpu: Disable map_domain_page for MPU
Date: Thu, 14 Aug 2025 09:19:59 +0100
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There is no domheap for ARM_32. All of the RAM is mapped and VA == PA.

Signed-off-by: Ayan Kumar Halder 
---
Changes from :-

v1 - 1. No changes.

 xen/arch/arm/Kconfig           |  2 +-
 xen/arch/arm/mpu/Makefile      |  1 -
 xen/arch/arm/mpu/domain-page.c | 45 ----------------------------------
 3 files changed, 1 insertion(+), 47 deletions(-)
 delete mode 100644 xen/arch/arm/mpu/domain-page.c

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index a0c8160474..5355534f3d 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -1,7 +1,7 @@
 config ARM_32
 	def_bool y
 	depends on "$(ARCH)" = "arm32"
-	select ARCH_MAP_DOMAIN_PAGE
+	select ARCH_MAP_DOMAIN_PAGE if MMU
 
 config ARM_64
 	def_bool y
diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile
index 50f8fe4326..4963c8b550 100644
--- a/xen/arch/arm/mpu/Makefile
+++ b/xen/arch/arm/mpu/Makefile
@@ -1,6 +1,5 @@
 obj-$(CONFIG_ARM_32) += arm32/
 obj-$(CONFIG_ARM_64) += arm64/
-obj-$(CONFIG_ARM_32) += domain-page.o
 obj-y += mm.o
 obj-y += p2m.o
 obj-y += setup.init.o
diff --git a/xen/arch/arm/mpu/domain-page.c b/xen/arch/arm/mpu/domain-page.c
deleted file mode 100644
index df5e06b6db..0000000000
--- a/xen/arch/arm/mpu/domain-page.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include 
-#include 
-#include 
-#include 
-
-void *map_domain_page_global(mfn_t mfn)
-{
-    BUG_ON("unimplemented");
-    return NULL;
-}
-
-/* Map a page of domheap memory */
-void *map_domain_page(mfn_t mfn)
-{
-    BUG_ON("unimplemented");
-    return NULL;
-}
-
-/* Release a mapping taken with map_domain_page() */
-void unmap_domain_page(const void *ptr)
-{
-    BUG_ON("unimplemented");
-}
-
-mfn_t domain_page_map_to_mfn(const void *ptr)
-{
-    BUG_ON("unimplemented");
-    return INVALID_MFN;
-}
-
-void unmap_domain_page_global(const void *va)
-{
-    BUG_ON("unimplemented");
-}
-
-/*
- * Local variables:
- * mode: C
- * c-file-style: "BSD"
- * c-basic-offset: 4
- * indent-tabs-mode: nil
- * End:
- */
-- 
2.25.1



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From: Ayan Kumar Halder 
To: 
CC: Ayan Kumar Halder , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , "Volodymyr
 Babchuk" 
Subject: [PATCH v2 1/2] arm/mpu: Enable is_xen_heap_page and is_xen_heap_mfn for ARM_32
Date: Thu, 14 Aug 2025 09:19:58 +0100
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In case of ARM_32, all of the RAM will be covered by a permanent contiguous
mapping (where VA == PA) and there will be a single heap. Thus, the memory
allocated from Xen heap uses PGC_xen_heap.
This is similar to the scenario described for
"CONFIG_SEPARATE_XENHEAP=n W/ DIRECT MAP OF ALL RAM" in common/page_alloc.c.

Signed-off-by: Ayan Kumar Halder 
---
Changes from :-

v1 - 1. Enable is_xen_heap_page() and is_xen_heap_mfn() definitions for ARM_64
or MPU (fixed a build break).

 xen/arch/arm/include/asm/mm.h     | 2 +-
 xen/arch/arm/include/asm/mpu/mm.h | 5 -----
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h
index fb79aeb088..7a93dad2ed 100644
--- a/xen/arch/arm/include/asm/mm.h
+++ b/xen/arch/arm/include/asm/mm.h
@@ -170,7 +170,7 @@ struct page_info
 #define _PGC_need_scrub   _PGC_allocated
 #define PGC_need_scrub    PGC_allocated
 
-#ifdef CONFIG_ARM_64
+#if defined(CONFIG_ARM_64) || defined(CONFIG_MPU)
 #define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap)
 #define is_xen_heap_mfn(mfn) \
     (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn)))
diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
index c32fac8905..e1ded6521d 100644
--- a/xen/arch/arm/include/asm/mpu/mm.h
+++ b/xen/arch/arm/include/asm/mpu/mm.h
@@ -27,11 +27,6 @@ extern pr_t xen_mpumap[MAX_MPU_REGION_NR];
 
 #define virt_to_maddr(va) ((paddr_t)((vaddr_t)(va) & PADDR_MASK))
 
-#ifdef CONFIG_ARM_32
-#define is_xen_heap_page(page) ({ BUG_ON("unimplemented"); false; })
-#define is_xen_heap_mfn(mfn) ({ BUG_ON("unimplemented"); false; })
-#endif
-
 /* On MPU systems there is no translation, ma == va. */
 static inline void *maddr_to_virt(paddr_t ma)
 {
-- 
2.25.1



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In-Reply-To: <52dbb5c5c1385b3b9d8522ef308ef15248973368.1755023074.git.dmytro_prokopchuk1@epam.com>
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On 12.08.2025 21:17, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 2.1 states: "A project shall not contain unreachable code."
> 
> Function `PrintErrMesg(const CHAR16*, EFI_STATUS)` isn't intended to return
> control to its caller. At the end, it calls `blexit()`, which, in turn,
> invokes the `__builtin_unreachable()` function, making subsequent return
> statements in `read_file()` unreachable:
> 
>     PrintErrMesg(name, ret);
>     /* not reached */
>     return false;
> 
> This also causes unreachability of the code meant to handle `read_file()`
> errors, as seen in these examples:
> 
> In this block:
>     if ( read_file(dir_handle, file_name, &cfg, NULL) )
>         break;
>     *tail = 0;
>     }
>     if ( !tail )
>         blexit(L"No configuration file found.");
> 
> And here:
>     else if ( !read_file(dir_handle, cfg_file_name, &cfg, NULL) )
>         blexit(L"Configuration file not found.");
> 
> And here:
>     if ( !read_file(dir_handle, s2w(&name), &cfg, NULL) )
>     {
>         PrintStr(L"Chained configuration file '");
>         PrintStr(name.w);
>         efi_bs->FreePool(name.w);
>         blexit(L"'not found.");
>     }
> 
> The issue arises because when an error occurs inside `read_file()`, it calls
> `PrintErrMesg()` and does not return to the caller.
> 
> To address this the following changes are applied:
> 1. Remove `PrintErrMesg(name, ret);` from the `read_file()` function.
> 2. Replaced it with `PrintErr(name);`, which prints the file name and returns
>    control to the caller.
> 3. Change the `read_file()` return type from `bool` to `EFI_STATUS`, allowing
>    file operation result codes to be returned to the caller.
> 4. Properly handle error codes returned from the `read_file()` function in the
>    relevant areas of the code.
> 5. Replace `blexit()` calls with informative error codes using `PrintErrMesg()`
>    where appropriate.
> 
> Signed-off-by: Dmytro Prokopchuk 
> ---
> Test CI pipeline:
> https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1980590118
> ---
>  xen/common/efi/boot.c | 57 ++++++++++++++++++++++++++++++-------------
>  1 file changed, 40 insertions(+), 17 deletions(-)
> 
> diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
> index 50ff1d1bd2..ddbafb2f9c 100644
> --- a/xen/common/efi/boot.c
> +++ b/xen/common/efi/boot.c
> @@ -132,7 +132,7 @@ struct file {
>      };
>  };
>  
> -static bool read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
> +static EFI_STATUS read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
>                        struct file *file, const char *options);
>  static bool read_section(const EFI_LOADED_IMAGE *image, const CHAR16 *name,
>                           struct file *file, const char *options);
> @@ -782,7 +782,7 @@ static void __init handle_file_info(const CHAR16 *name,
>      efi_arch_handle_module(file, name, options);
>  }
>  
> -static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
> +static EFI_STATUS __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
>                               struct file *file, const char *options)
>  {
>      EFI_FILE_HANDLE FileHandle = NULL;
> @@ -791,7 +791,7 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
>      const CHAR16 *what = NULL;
>  
>      if ( !name )
> -        PrintErrMesg(L"No filename", EFI_OUT_OF_RESOURCES);
> +        return EFI_INVALID_PARAMETER;

Why the change in error code? EFI_OUT_OF_RESOURCES() was used deliberately for
cases where the result of s2w() is passed directly into here.

Between this hunk and ...

> @@ -842,7 +842,7 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
>  
>      efi_arch_flush_dcache_area(file->ptr, file->size);
>  
> -    return true;
> +    return ret;
>  
>   fail:
>      if ( FileHandle )

... this one there's at least one "return false" which you leave untouched, thus
wrongly reporting EFI_SUCCESS now to the caller.

> @@ -850,10 +850,9 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
>  
>      PrintErr(what);
>      PrintErr(L" failed for ");
> -    PrintErrMesg(name, ret);
> +    PrintErr(name);
>  
> -    /* not reached */
> -    return false;
> +    return ret;
>  }

With the comment here - possibly adjusted to become a SAF one - all should be
fine with no other changes? Because of the other "return false" callers simply
can't assume the function would never indicate failure back to them. (New
"return false" could in principle also appear, which is why I think the base
structure wants keeping as is, including in the callers.)

Jan


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Message-ID: <0496ce54-84b5-43a1-871a-b77d15460427@amd.com>
Date: Thu, 14 Aug 2025 09:24:16 +0100
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v1 1/2] arm/mpu: Enable is_xen_heap_page and co for ARM_32
To: Hari Limaye , Ayan Kumar Halder
	
CC: , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , "Volodymyr
 Babchuk" 
References: <20250807174529.595577-1-ayan.kumar.halder@amd.com>
 <20250807174529.595577-2-ayan.kumar.halder@amd.com>
 
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On 12/08/2025 11:30, Hari Limaye wrote:
> Hi Ayan,
Hi Hari,
>
>> On Thu, Aug 07, 2025 at 06:45:28PM +0000, Ayan Kumar Halder wrote:
>> In case of ARM_32, all of the RAM will be covered by a permanent contiguous
>> mapping (where VA == PA) and there will be a single heap. Thus, the memory
>> allocated from Xen heap uses PGC_xen_heap.
>> This is similar to the scenario described for
>> "CONFIG_SEPARATE_XENHEAP=n W/ DIRECT MAP OF ALL RAM" in common/page_alloc.c.
>>
>> Signed-off-by: Ayan Kumar Halder 
>> ---
> This patch breaks the build for ARM_32, CONFIG_MMU targets due to
> multiple definition of `is_xen_heap_page` and `is_xen_heap_mfn`. The
> pre-existing definitions are located at xen/arch/arm/include/asm/mmu/mm.h:30:9

Thanks for checking this and apologies for the build break. I should 
have tested this before sending.

I have sent out

[PATCH v2 0/2] R52 MPU support (for "Third series for R82 MPU")

This time I tested 
https://gitlab.com/xen-project/people/ayankuma/xen/-/pipelines/1982700286 
 :)

- Ayan


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Subject: Re: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
To: "Penny, Zheng" 
Cc: "Huang, Ray" ,
 Anthony PERARD ,
 Andrew Cooper ,
 "Orzel, Michal" , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" 
References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
 <20250711035106.2540522-20-Penny.Zheng@amd.com>
 <796a9251-8b4f-4266-a31e-828d4da29f54@suse.com>
 
 <98aa5a7b-5268-41ae-a1d5-25028b0704b6@suse.com>
 
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From: Jan Beulich 
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On 14.08.2025 09:34, Penny, Zheng wrote:
> [Public]
> 
>> -----Original Message-----
>> From: Jan Beulich 
>> Sent: Thursday, August 14, 2025 2:40 PM
>> To: Penny, Zheng 
>> Cc: Huang, Ray ; Anthony PERARD
>> ; Andrew Cooper ;
>> Orzel, Michal ; Julien Grall ; Roger Pau
>> Monné ; Stefano Stabellini ; xen-
>> devel@lists.xenproject.org
>> Subject: Re: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
>> xen_sysctl_pm_op for amd-cppc driver
>>
>> On 14.08.2025 05:13, Penny, Zheng wrote:
>>> [Public]
>>>
>>>> -----Original Message-----
>>>> From: Jan Beulich 
>>>> Sent: Thursday, July 24, 2025 10:44 PM
>>>> To: Penny, Zheng 
>>>> Cc: Huang, Ray ; Anthony PERARD
>>>> ; Andrew Cooper
>>>> ; Orzel, Michal ;
>>>> Julien Grall ; Roger Pau Monné
>>>> ; Stefano Stabellini ;
>>>> xen- devel@lists.xenproject.org
>>>> Subject: Re: [PATCH v6 19/19] xen/cpufreq: Adapt
>> SET/GET_CPUFREQ_CPPC
>>>> xen_sysctl_pm_op for amd-cppc driver
>>>>
>>>> On 11.07.2025 05:51, Penny Zheng wrote:
>>>>> Introduce helper set_amd_cppc_para() and get_amd_cppc_para() to
>>>>> SET/GET CPPC-related para for amd-cppc/amd-cppc-epp driver.
>>>>>
>>>>> In get_cpufreq_cppc()/set_cpufreq_cppc(), we include
>>>>> "processor_pminfo[cpuid]->init & XEN_CPPC_INIT" condition check to
>>>>> deal with cpufreq driver in amd-cppc.
>>>>>
>>>>> Also, a new field "policy" has also been added in "struct xen_get_cppc_para"
>>>>> to describe performance policy in active mode. It gets printed with
>>>>> other cppc paras. Move manifest constants "XEN_CPUFREQ_POLICY_xxx"
>>>>> to public header to let it be used in user space tools. Also add a
>>>>> new anchor "XEN_CPUFREQ_POLICY_xxx" for array overrun check.
>>>>
>>>> If only they indeed had XEN_ prefixes.
>>>>
>>>>> Signed-off-by: Penny Zheng 
>>>>> ---
>>>>> v1 -> v2:
>>>>> - Give the variable des_perf an initializer of 0
>>>>> - Use the strncmp()s directly in the if()
>>>>> ---
>>>>> v3 -> v4
>>>>> - refactor comments
>>>>> - remove double blank lines
>>>>> - replace amd_cppc_in_use flag with XEN_PROCESSOR_PM_CPPC
>>>>> ---
>>>>> v4 -> v5:
>>>>> - add new field "policy" in "struct xen_cppc_para"
>>>>> - add new performamce policy XEN_CPUFREQ_POLICY_BALANCE
>>>>> - drop string comparisons with "processor_pminfo[cpuid]->init &
>>>> XEN_CPPC_INIT"
>>>>> and "cpufreq.setpolicy == NULL"
>>>>> - Blank line ahead of the main "return" of a function
>>>>> - refactor comments, commit message and title
>>>>> ---
>>>>> v5 -> v6:
>>>>> - remove duplicated manifest constants, and just move it to public
>>>>> header
>>>>> - use "else if" to avoid confusion that it looks as if both paths
>>>>> could be taken
>>>>> - add check for legitimate perf values
>>>>> - use "unknown" instead of "none"
>>>>> - introduce "CPUFREQ_POLICY_END" for array overrun check in user
>>>>> space tools
>>>>> +         (set_cppc->maximum > data->caps.highest_perf ||
>>>>> +          set_cppc->maximum < data->caps.lowest_nonlinear_perf) )
>>>>> +        return -EINVAL;
>>>>> +    /*
>>>>> +     * Minimum performance may be set to any performance value in the range
>>>>> +     * [Nonlinear Lowest Performance, Highest Performance], inclusive but
>> must
>>>>> +     * be set to a value that is less than or equal to Maximum Performance.
>>>>> +     */
>>>>> +    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM &&
>>>>> +         (set_cppc->minimum < data->caps.lowest_nonlinear_perf ||
>>>>> +          (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM &&
>>>>> +           set_cppc->minimum > set_cppc->maximum) ||
>>>>> +          (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM)
>> &&
>>>>
>>>> Hmm, I find this confusing to read, and was first thinking the ! was
>>>> wrong here. Imo such is better expressed with the conditional operator:
>>>>
>>>>
>>>>           set_cppc->minimum > (set_cppc->set_params &
>>>> XEN_SYSCTL_CPPC_SET_MAXIMUM
>>>>                                ? set_cppc->maximum
>>>>                                : data->req.max_perf)
>>>>
>>>
>>> Thx, understood!
>>>
>>>> Which also makes it easier to spot that here you use data->req, when
>>>> in the minimum check you use data->caps. Why this difference?
>>>>
>>>
>>>  minimum check has two boundary check, left boundary check is against
>>> data->caps.lowest_nonlinear_perf. And right boundary check is against
>>> data->req.max_perf. As it shall not only not larger than
>>> caps.highest_perf , but also req.max_perf. The relation between
>>> max_perf and highest_perf is validated in the maximum check. So here,
>>> we are only considering max_perf
>>
>> I still don't get why one check is against capabilities (permitted values) why the
>> other is again what's currently set.
> 
> It needs to meet the following two criteria:
> 
> 1. caps.lowest_nonlinear <= min_perf <= caps.highest_perf
> 2. min_perf <= max_perf. If users don't set max_perf at the same time, we are using the values stored in req.max_perf, which is the last setting.

Hmm, I see. Yet then what about the case of max being set without also setting
min? Overall I'm expecting full symmetry in the checking that's being done.

Jan


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, Andrew Cooper ,
	"Orzel, Michal" , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Topic: [PATCH v6 19/19] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Index:
 AQHb8hcuzjUv9QY8PkCazI2v8DQHmbRBbryAgCA3tFCAAEHpAIAADdDQgAAQ4wCAAABlEA==
Date: Thu, 14 Aug 2025 08:32:44 +0000
Message-ID:
 
References: <20250711035106.2540522-1-Penny.Zheng@amd.com>
 <20250711035106.2540522-20-Penny.Zheng@amd.com>
 <796a9251-8b4f-4266-a31e-828d4da29f54@suse.com>
 
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On 13.08.2025 20:27, Dmytro Prokopchuk1 wrote:
> ...
> 
> from `vaddr_t' (that is `unsigned long') to `switch_ttbr_fn*' (that is `void(*)(unsigned long)')
> 
> Signed-off-by: Dmytro Prokopchuk 
> ---
> This is just a RFC patch.
> The commit message is not important at this stage.
> 
> I am seeking comments regarding this case.
> 
> Thanks.
> ---
>  automation/eclair_analysis/ECLAIR/deviations.ecl |  8 ++++++++
>  docs/misra/deviations.rst                        | 10 ++++++++++
>  docs/misra/rules.rst                             |  8 +++++++-
>  xen/arch/arm/arm64/mmu/mm.c                      |  2 ++
>  4 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/eclair_analysis/ECLAIR/deviations.ecl
> index ebce1ceab9..f9fd6076b7 100644
> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -365,6 +365,14 @@ constant expressions are required.\""
>  }
>  -doc_end
>  
> +-doc_begin="The conversion from unsigned long to a function pointer does not lose any information, provided that the source type has enough bits to restore it."
> +-config=MC3A2.R11.1,casts+={safe,
> +  "from(type(canonical(builtin(unsigned long))))
> +   &&to(type(canonical(__function_pointer_types)))
> +   &&relation(definitely_preserves_value)"
> +}
> +-doc_end
> +
>  -doc_begin="The conversion from a function pointer to a boolean has a well-known semantics that do not lead to unexpected behaviour."
>  -config=MC3A2.R11.1,casts+={safe,
>    "from(type(canonical(__function_pointer_types)))
> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
> index 3c46a1e47a..27848602f6 100644
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -348,6 +348,16 @@ Deviations related to MISRA C:2012 Rules:
>         to store it.
>       - Tagged as `safe` for ECLAIR.
>  
> +   * - R11.1
> +     - The conversion from unsigned long to a function pointer does not lose any
> +       information or violate type safety assumptions if the unsigned long type
> +       is guaranteed to be at least as large as a function pointer. This ensures
> +       that the function pointer address can be fully represented without
> +       truncation or corruption. Macro BUILD_BUG_ON can be integrated into the
> +       build system to confirm that 'sizeof(unsigned long) >= sizeof(void (*)())'
> +       on all target platforms.

If sizeof(unsigned long) > sizeof(void (*)()), there is loss of information.
Unless (not said here) the unsigned long value itself is the result of
converting a function pointer to unsigned long. Whether all of that together
can be properly expressed to Eclair I don't know. Hence, as Teddy already
suggested, == may want specifying instead.

> --- a/xen/arch/arm/arm64/mmu/mm.c
> +++ b/xen/arch/arm/arm64/mmu/mm.c
> @@ -150,6 +150,7 @@ void __init relocate_and_switch_ttbr(uint64_t ttbr)
>      vaddr_t id_addr = virt_to_maddr(relocate_xen);
>      relocate_xen_fn *fn = (relocate_xen_fn *)id_addr;
>      lpae_t pte;
> +    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
>  
>      /* Enable the identity mapping in the boot page tables */
>      update_identity_mapping(true);
> @@ -178,6 +179,7 @@ void __init switch_ttbr(uint64_t ttbr)
>      vaddr_t id_addr = virt_to_maddr(switch_ttbr_id);
>      switch_ttbr_fn *fn = (switch_ttbr_fn *)id_addr;
>      lpae_t pte;
> +    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
>  
>      /* Enable the identity mapping in the boot page tables */
>      update_identity_mapping(true);

BUILD_BUG_ON() is a statement, not a declaration, and hence wants grouping
as such. Question is whether we indeed want to sprinkle such checks all
over the code base. (I expect the two cases here aren't all we have.)

Jan


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Subject: Re: [PATCH -next v7 5/7] arm64: entry: Refactor
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To: Ada Couprie Diaz 
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References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 <20250729015456.3411143-6-ruanjinjie@huawei.com>
 <4242ef37-efeb-446f-abbc-0104b805ad12@arm.com>
From: Jinjie Ruan 
In-Reply-To: <4242ef37-efeb-446f-abbc-0104b805ad12@arm.com>
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On 2025/8/12 0:02, Ada Couprie Diaz wrote:
> On 29/07/2025 02:54, Jinjie Ruan wrote:
> 
>> ARM64 requires an additional check whether to reschedule on return
>> from interrupt. So add arch_irqentry_exit_need_resched() as the default
>> NOP implementation and hook it up into the need_resched() condition in
>> raw_irqentry_exit_cond_resched(). This allows ARM64 to implement
>> the architecture specific version for switching over to
>> the generic entry code.
>>
>> To align the structure of the code with irqentry_exit_cond_resched()
>> from the generic entry code, hoist the need_irq_preemption()
>> and IS_ENABLED() check earlier. And different preemption check functions
>> are defined based on whether dynamic preemption is enabled.
>>
>> Suggested-by: Mark Rutland 
>> Suggested-by: Kevin Brodsky 
>> Suggested-by: Thomas Gleixner 
>> Signed-off-by: Jinjie Ruan 
>> ---
> Unrelated to the other thread : I noticed that compiling this patch
> with `allnoconfig` would fail :
> - `raw_irqentry_exit_cond_resched` has no previous prototype,
>   as it is defined within `#ifdef CONFIG_PREEMPTION`
> - `irqentry_exit_cond_resched()` is not declared, as it is also within
>   `#ifdef CONFIG_PREEMPTION`

You are right, thank you! I'll fix it.

> 
> The patch below fixes the issue, but introduces merge conflicts in
> patches 6 and 7, plus the `#ifdef` needs to be moved accordingly
> in patch 6 and the empty "without preemption" `irq_exit_cond_resched()`
> needs to be removed in patch 7.
> 
> I hope this can be useful,
> Ada
> 
> ---
> diff --git a/arch/arm64/include/asm/preempt.h
> b/arch/arm64/include/asm/preempt.h
> index 0f0ba250efe8..d9aba8b1e466 100644
> --- a/arch/arm64/include/asm/preempt.h
> +++ b/arch/arm64/include/asm/preempt.h
> @@ -103,6 +103,8 @@ void dynamic_irqentry_exit_cond_resched(void);
>  #define irqentry_exit_cond_resched() raw_irqentry_exit_cond_resched()
> 
>  #endif /* CONFIG_PREEMPT_DYNAMIC */
> +#else /* CONFIG_PREEMPTION */
> +#define irqentry_exit_cond_resched() {}
>  #endif /* CONFIG_PREEMPTION */
> 
>  #endif /* __ASM_PREEMPT_H */
> diff --git a/arch/arm64/kernel/entry-common.c
> b/arch/arm64/kernel/entry-common.c
> index 4f92664fd46c..abd7a315145e 100644
> --- a/arch/arm64/kernel/entry-common.c
> +++ b/arch/arm64/kernel/entry-common.c
> @@ -661,6 +661,7 @@ static __always_inline void __el1_pnmi(struct
> pt_regs *regs,
>         arm64_exit_nmi(regs, state);
>  }
> 
> +#ifdef CONFIG_PREEMPTION
>  void raw_irqentry_exit_cond_resched(void)
>  {
>         if (!preempt_count()) {
> @@ -668,6 +669,7 @@ void raw_irqentry_exit_cond_resched(void)
>                         preempt_schedule_irq();
>         }
>  }
> +#endif
> 
>  #ifdef CONFIG_PREEMPT_DYNAMIC
>  DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
> 
> 


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Subject: Re: [PATCH 03/22] x86/traps: Drop incorrect BUILD_BUG_ON() and
 comment in load_system_tables()
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-4-andrew.cooper3@citrix.com>
 
 <5aadadb9-65e2-4f30-bac5-a2b3a2f4a29e@citrix.com>
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On 13.08.2025 11:40, Andrew Cooper wrote:
> On 12/08/2025 9:11 am, Jan Beulich wrote:
>> On 08.08.2025 22:22, Andrew Cooper wrote:
>>> This was added erroneously by me.
>>>
>>> Hardware task switching does demand a TSS of at least 0x67 bytes, but that's
>>> not relevant in 64bit, and not relevant for Xen since commit
>>> 5d1181a5ea5e ("xen: Remove x86_32 build target.") in 2012.
>>>
>>> We already load a 0-length TSS in early_traps_init() demonstrating that it's
>>> possible.
>>>
>>> Signed-off-by: Andrew Cooper 
>>> ---
>>> CC: Jan Beulich 
>>> CC: Roger Pau Monné 
>>> ---
>>>  xen/arch/x86/cpu/common.c | 2 --
>>>  1 file changed, 2 deletions(-)
>>>
>>> diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
>>> index f6ec5c9df522..cdc41248d4e9 100644
>>> --- a/xen/arch/x86/cpu/common.c
>>> +++ b/xen/arch/x86/cpu/common.c
>>> @@ -936,8 +936,6 @@ void load_system_tables(void)
>>>  		wrmsrl(MSR_ISST, (unsigned long)ist_ssp);
>>>  	}
>>>  
>>> -	BUILD_BUG_ON(sizeof(*tss) <= 0x67); /* Mandated by the architecture. */
>>> -
>>>  	_set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
>>>  			 sizeof(*tss) - 1, SYS_DESC_tss_avail);
>>>  	if ( IS_ENABLED(CONFIG_PV32) )
>> Well, the comment is wrong. Whether the BUILD_BUG_ON() itself is also wrong
>> depends on our intentions with the structure. Don't we need it to be that
>> size for everything (incl I/O bitmap) to work correctly elsewhere?
> 
> We don't use the IO bitmap.  We've talked about it a few times, but
> never got it sorted.
> 
> Xen's TSS could be as short as 0x37 (covering IST3) and still work
> correctly and safely (as there's no task switching).

Then shouldn't we have a BUILD_BUG_ON(sizeof(*tss) <= 0x37) here? Hmm,
arguably that get pretty close to useless, though, so
Acked-by: Jan Beulich 

> A failure to read tss->iopb is the same as a failure to read the bitmap
> itself.  In fact, it's probably marginally faster for users of
> IOBMP_INVALID_OFFSET as it fails one step earlier.

(Provided there are no errata lurking anywhere.)

Jan


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On 13.08.2025 13:13, Andrew Cooper wrote:
> On 12/08/2025 9:41 am, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/acpi/wakeup_prot.S
>>> +++ b/xen/arch/x86/acpi/wakeup_prot.S
>>> @@ -63,6 +63,9 @@ LABEL(s3_resume)
>>>          pushq   %rax
>>>          lretq
>>>  1:
>>> +        /* Set up early exceptions and CET before entering C properly. */
>>> +        call    ap_early_traps_init
>> But this is the BSP?
> 
> By the end of the cleanup, what we have is:
> 
> At boot only:
>  * really early init, basic exception handling only
>  * regular init (inc syscall trampolines)
>  * late re-init as we change the stack linear address
> 
> For everything else (APs, S3, hot-online):
>  * early, full exception handling
>  * regular init (inc syscall trampolines)
> 
> 
> Currently, these are named:
>  * bsp_early_traps_init()
>  * traps_init()
>  * bsp_traps_reinit()
> 
> and
>  * ap_early_traps_init()
>  * percpu_traps_init()
> 
> 
> Perhaps ap_early_traps_init() should be named
> percpu_early_traps_init()?  But I'm open to suggestions.

That name looks like a better fit to me, yes.

Jan


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On 13.08.2025 13:25, Andrew Cooper wrote:
> On 12/08/2025 10:19 am, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> Since commit a35816b5cae8 ("x86/traps: Introduce early_traps_init() and
>>> simplify setup"), load_system_tables() is called later on the BSP, so the
>>> SYS_STATE_early_boot check can be dropped from the safety BUG_ON().
>>>
>>> Move the BUILD_BUG_ON() into build_assertions(),
>> I'm not quite convinced of this move - having the related BUILD_BUG_ON()
>> and BUG_ON() next to each other would seem better to me.
> 
> I don't see a specific reason for them to be together, and the comment
> explains what's going on.
> 
> With FRED, we want a related BUILD_BUG_ON(), but there's no equivalent
> BUG_ON() because MSR_RSP_SL0 will #GP on being misaligned.

That BUILD_BUG_ON() could then sit next to the MSR write? Unless of course
that ends up sitting in an assembly source.

Jan


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Date: Thu, 14 Aug 2025 10:58:03 +0200
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Subject: Re: [PATCH 10/22] x86/traps: Move subarch_percpu_traps_init() into
 traps-setup.c
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 13.08.2025 13:53, Andrew Cooper wrote:
> On 12/08/2025 10:52 am, Jan Beulich wrote:
>> On 11.08.2025 10:17, Andrew Cooper wrote:
>>> On 08/08/2025 9:23 pm, Andrew Cooper wrote:
>>>> ... along with the supporting functions.  Switch to Xen coding style, and make
>>>> static as there are no external callers.
>>>>
>>>> Rename to legacy_syscall_init() as a more accurate name.
>>>>
>>>> No functional change.
>>>>
>>>> Signed-off-by: Andrew Cooper 
>>>> ---
>>>> CC: Jan Beulich 
>>>> CC: Roger Pau Monné 
>>>> ---
>>>>  xen/arch/x86/include/asm/system.h |  2 -
>>>>  xen/arch/x86/traps-setup.c        | 97 ++++++++++++++++++++++++++++++-
>>>>  xen/arch/x86/x86_64/traps.c       | 92 -----------------------------
>>>>  3 files changed, 95 insertions(+), 96 deletions(-)
>>>>
>>>> diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
>>>> index 3cdc56e4ba6d..6c2800d8158d 100644
>>>> --- a/xen/arch/x86/include/asm/system.h
>>>> +++ b/xen/arch/x86/include/asm/system.h
>>>> @@ -256,6 +256,4 @@ static inline int local_irq_is_enabled(void)
>>>>  #define BROKEN_ACPI_Sx          0x0001
>>>>  #define BROKEN_INIT_AFTER_S1    0x0002
>>>>  
>>>> -void subarch_percpu_traps_init(void);
>>>> -
>>>>  #endif
>>>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>>>> index 13b8fcf0ba51..fbae7072c292 100644
>>>> --- a/xen/arch/x86/traps-setup.c
>>>> +++ b/xen/arch/x86/traps-setup.c
>>>> @@ -2,13 +2,15 @@
>>>>  /*
>>>>   * Configuration of event handling for all CPUs.
>>>>   */
>>>> +#include 
>>>>  #include 
>>>>  #include 
>>>>  
>>>> +#include 
>>>>  #include 
>>>>  #include 
>>>>  #include 
>>>> -#include 
>>>> +#include 
>>>>  #include 
>>>>  
>>>>  DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt);
>>>> @@ -19,6 +21,8 @@ static bool __initdata opt_ler;
>>>>  boolean_param("ler", opt_ler);
>>>>  
>>>>  void nocall entry_PF(void);
>>>> +void nocall lstar_enter(void);
>>>> +void nocall cstar_enter(void);
>>>>  
>>>>  /*
>>>>   * Sets up system tables and descriptors for IDT devliery.
>>>> @@ -138,6 +142,95 @@ static void load_system_tables(void)
>>>>      BUG_ON(stack_bottom & 15);
>>>>  }
>>>>  
>>>> +static unsigned int write_stub_trampoline(
>>>> +    unsigned char *stub, unsigned long stub_va,
>>>> +    unsigned long stack_bottom, unsigned long target_va)
>>>> +{
>>>> +    unsigned char *p = stub;
>>>> +
>>>> +    if ( cpu_has_xen_ibt )
>>>> +    {
>>>> +        place_endbr64(p);
>>>> +        p += 4;
>>>> +    }
>>>> +
>>>> +    /* Store guest %rax into %ss slot */
>>>> +    /* movabsq %rax, stack_bottom - 8 */
>>>> +    *p++ = 0x48;
>>>> +    *p++ = 0xa3;
>>>> +    *(uint64_t *)p = stack_bottom - 8;
>>>> +    p += 8;
>>>> +
>>>> +    /* Store guest %rsp in %rax */
>>>> +    /* movq %rsp, %rax */
>>>> +    *p++ = 0x48;
>>>> +    *p++ = 0x89;
>>>> +    *p++ = 0xe0;
>>>> +
>>>> +    /* Switch to Xen stack */
>>>> +    /* movabsq $stack_bottom - 8, %rsp */
>>>> +    *p++ = 0x48;
>>>> +    *p++ = 0xbc;
>>>> +    *(uint64_t *)p = stack_bottom - 8;
>>>> +    p += 8;
>>>> +
>>>> +    /* jmp target_va */
>>>> +    *p++ = 0xe9;
>>>> +    *(int32_t *)p = target_va - (stub_va + (p - stub) + 4);
>>>> +    p += 4;
>>>> +
>>>> +    /* Round up to a multiple of 16 bytes. */
>>>> +    return ROUNDUP(p - stub, 16);
>>>> +}
>>>> +
>>>> +static void legacy_syscall_init(void)
>>>> +{
>>>> +    unsigned long stack_bottom = get_stack_bottom();
>>>> +    unsigned long stub_va = this_cpu(stubs.addr);
>>>> +    unsigned char *stub_page;
>>>> +    unsigned int offset;
>>>> +
>>>> +    /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
>>>> +    if ( !IS_ENABLED(CONFIG_PV) )
>>>> +        return;
>>>> +
>>>> +    stub_page = map_domain_page(_mfn(this_cpu(stubs.mfn)));
>>>> +
>>>> +    /*
>>>> +     * Trampoline for SYSCALL entry from 64-bit mode.  The VT-x HVM vcpu
>>>> +     * context switch logic relies on the SYSCALL trampoline being at the
>>>> +     * start of the stubs.
>>>> +     */
>>>> +    wrmsrl(MSR_LSTAR, stub_va);
>>>> +    offset = write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>>> +                                   stub_va, stack_bottom,
>>>> +                                   (unsigned long)lstar_enter);
>>>> +    stub_va += offset;
>>>> +
>>>> +    if ( cpu_has_sep )
>>>> +    {
>>>> +        /* SYSENTER entry. */
>>>> +        wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
>>>> +        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
>>>> +        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
>>>> +    }
>>>> +
>>>> +    /* Trampoline for SYSCALL entry from compatibility mode. */
>>>> +    wrmsrl(MSR_CSTAR, stub_va);
>>>> +    offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>>> +                                    stub_va, stack_bottom,
>>>> +                                    (unsigned long)cstar_enter);
>>>> +
>>>> +    /* Don't consume more than half of the stub space here. */
>>>> +    ASSERT(offset <= STUB_BUF_SIZE / 2);
>>>> +
>>>> +    unmap_domain_page(stub_page);
>>>> +
>>>> +    /* Common SYSCALL parameters. */
>>>> +    wrmsrl(MSR_STAR, XEN_MSR_STAR);
>>>> +    wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
>>>> +}
>>> These want adjusting to use wrmsrns(), similarly to the previous patch. 
>>> Fixed locally.
>> Also the one higher in the function, I suppose.
> 
> All of them.
> 
> I'm not aware of anywhere were we want serialising behaviour, except for
> ICR which is buggly non-serialising and has workarounds.
> 
> But I'm also not sure enough of this to suggest that we make wrmsr() be
> wrmsrns() by default.

I'm pretty sure we don't want this. If nothing else then to avoid code bloat
for MSR writes which are non-serializing even in the original form.

Jan


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From: Nicola Vetrini 
Date: Thu, 14 Aug 2025 11:16:50 +0200
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Subject: Re: [XEN PATCH 2/3] xen/macros: Drop alternative definition of
 BUILD_BUG_ON(_ZERO)? for old GCC
To: Jan Beulich 
Cc: Andrew Cooper , Anthony PERARD , 
	Michal Orzel , Julien Grall , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Stefano Stabellini , xen-devel@lists.xenproject.org
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--0000000000008007b2063c4fbc19
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On Thu, Aug 14, 2025, 10:08 Jan Beulich  wrote:

> On 13.08.2025 21:12, nicola.vetrini@gmail.com wrote:
> > From: Nicola Vetrini 
> >
> > The toolchain baseline for GCC is 5.1, which supports _Static_assert
> > in c99 mode
>
> Hmm, interesting. I can confirm the behavior, but isn't this a bug?
> There's no
> _Static_assert() in plain C99. Respective notes in the "Changes, New
> Features,
> and Fixes" are also saying otherwise:
> https://gcc.gnu.org/gcc-4.6/changes.html
> has "This support may be selected with -std=c1x, or -std=gnu1x for C1X with
> GNU extensions." Nothing new is said in any of the respective documents up
> to
> the release of gcc5. (In fact, the compiler accepts the construct even with
> -std=c89.)
>

 Some features that are part of the C99 standard are accepted as extensions
in C90 mode, and some features that are part of the C11 standard are
accepted as extensions in C90 and C99 modes. Use of the -std options listed
above disables these extensions where they conflict with the C standard
version selected

If my reading is correct then this paragraph gives them the leeway needed
to use it even in c89, except maybe with -pedantic


> Our misra/C-language-toolchain.rst refers to a section in gcc12's doc which
> doesn't mention _Static_assert() at all, afaics.
>
> Jan
>

I can check with my colleagues, but I suspect this is not documented as an
extension by GCC because it's not one in C11, and gcc12 supports all(?) of
C11, therefore it is an extension only with respect to certain conditions,
which GCC does not use as a category in their docs, but we keep track of
what is an extension and what is not, given the CU standard selected.

>

--0000000000008007b2063c4fbc19
Content-Type: text/html; charset="UTF-8"
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    On Thu, Aug 14, 2025, 10:08 Jan Beulich <jbeulich@su=
se.com> wrote:
    On 13.08.2025=
 21:12, nicola.vetrini@gmail.com wrote:
    
> From: Nicola Vetrini <nicola.vetrini@gmail.com=
>
    
> 
    
> The toolchain baseline for GCC is 5.1, which supports _Static_assert
> in c99 mode
    

    
Hmm, interesting. I can confirm the behavior, but isn't this a bug? The=
re's no
    
_Static_assert() in plain C99. Respective notes in the "Changes, New F=
eatures,
    
and Fixes" are also saying otherwise: https://gcc.gnu.org/gcc-4.6/changes.html
    
has "This support may be selected with -std=3Dc1x, or -std=3Dgnu1x for=
 C1X with
    
GNU extensions." Nothing new is said in any of the respective document=
s up to
    
the release of gcc5. (In fact, the compiler accepts the construct even with=

    
-std=3Dc89.)

    =C2=A0Some features that are part of the C99 standard are accep=
ted as extensions in C90 mode, and some features that are part of the C11 s=
tandard are accepted as extensions in C90 and C99 modes. Use of the -std op=
tions listed above disables these extensions where they conflict with the C=
 standard version selected

    If my reading is correct then this paragraph gives them the leeway neede=
d to use it even in c89, except maybe with -pedantic

    

    
Our misra/C-language-toolchain.rst refers to a section in gcc12's doc w=
hich
    
doesn't mention _Static_assert() at all, afaics.
    

    
Jan

    I can check with my colleagues, but I suspect this is not documented as =
an extension by GCC because it's not one in C11, and gcc12 supports all=
(?) of C11, therefore it is an extension only with respect to certain condi=
tions, which GCC does not use as a category in their docs, but we keep trac=
k of what is an extension and what is not, given the CU standard selected.=
=C2=A0
    

    

--0000000000008007b2063c4fbc19--


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Subject: Re: [PATCH -next v7 5/7] arm64: entry: Refactor
 preempt_schedule_irq() check code
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References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 <20250729015456.3411143-6-ruanjinjie@huawei.com>
 
From: Jinjie Ruan 
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On 2025/8/12 19:13, Mark Rutland wrote:
> On Tue, Jul 29, 2025 at 09:54:54AM +0800, Jinjie Ruan wrote:
>> ARM64 requires an additional check whether to reschedule on return
>> from interrupt. So add arch_irqentry_exit_need_resched() as the default
>> NOP implementation and hook it up into the need_resched() condition in
>> raw_irqentry_exit_cond_resched(). This allows ARM64 to implement
>> the architecture specific version for switching over to
>> the generic entry code.
>>
>> To align the structure of the code with irqentry_exit_cond_resched()
>> from the generic entry code, hoist the need_irq_preemption()
>> and IS_ENABLED() check earlier. And different preemption check functions
>> are defined based on whether dynamic preemption is enabled.
>>
>> Suggested-by: Mark Rutland 
>> Suggested-by: Kevin Brodsky 
>> Suggested-by: Thomas Gleixner 
>> Signed-off-by: Jinjie Ruan 
>> ---
>>  arch/arm64/include/asm/preempt.h |  4 ++++
>>  arch/arm64/kernel/entry-common.c | 35 ++++++++++++++++++--------------
>>  kernel/entry/common.c            | 16 ++++++++++++++-
>>  3 files changed, 39 insertions(+), 16 deletions(-)
> 
> Can you please split the change to kernel/entry/common.c into a separate
> patch? That doesn't depend on the arm64-specific changes, and it'll make
> it easier to handle any conflcits when merging this.

Sure, I'll split the change into separate patch.

> 
> Mark.
> 
>>
>> diff --git a/arch/arm64/include/asm/preempt.h b/arch/arm64/include/asm/preempt.h
>> index 0159b625cc7f..0f0ba250efe8 100644
>> --- a/arch/arm64/include/asm/preempt.h
>> +++ b/arch/arm64/include/asm/preempt.h
>> @@ -85,6 +85,7 @@ static inline bool should_resched(int preempt_offset)
>>  void preempt_schedule(void);
>>  void preempt_schedule_notrace(void);
>>  
>> +void raw_irqentry_exit_cond_resched(void);
>>  #ifdef CONFIG_PREEMPT_DYNAMIC
>>  
>>  DECLARE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
>> @@ -92,11 +93,14 @@ void dynamic_preempt_schedule(void);
>>  #define __preempt_schedule()		dynamic_preempt_schedule()
>>  void dynamic_preempt_schedule_notrace(void);
>>  #define __preempt_schedule_notrace()	dynamic_preempt_schedule_notrace()
>> +void dynamic_irqentry_exit_cond_resched(void);
>> +#define irqentry_exit_cond_resched()	dynamic_irqentry_exit_cond_resched()
>>  
>>  #else /* CONFIG_PREEMPT_DYNAMIC */
>>  
>>  #define __preempt_schedule()		preempt_schedule()
>>  #define __preempt_schedule_notrace()	preempt_schedule_notrace()
>> +#define irqentry_exit_cond_resched()	raw_irqentry_exit_cond_resched()
>>  
>>  #endif /* CONFIG_PREEMPT_DYNAMIC */
>>  #endif /* CONFIG_PREEMPTION */
>> diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
>> index 7c2299c1ba79..4f92664fd46c 100644
>> --- a/arch/arm64/kernel/entry-common.c
>> +++ b/arch/arm64/kernel/entry-common.c
>> @@ -285,19 +285,8 @@ static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs,
>>  		lockdep_hardirqs_on(CALLER_ADDR0);
>>  }
>>  
>> -#ifdef CONFIG_PREEMPT_DYNAMIC
>> -DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
>> -#define need_irq_preemption() \
>> -	(static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
>> -#else
>> -#define need_irq_preemption()	(IS_ENABLED(CONFIG_PREEMPTION))
>> -#endif
>> -
>>  static inline bool arm64_preempt_schedule_irq(void)
>>  {
>> -	if (!need_irq_preemption())
>> -		return false;
>> -
>>  	/*
>>  	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
>>  	 * priority masking is used the GIC irqchip driver will clear DAIF.IF
>> @@ -672,6 +661,24 @@ static __always_inline void __el1_pnmi(struct pt_regs *regs,
>>  	arm64_exit_nmi(regs, state);
>>  }
>>  
>> +void raw_irqentry_exit_cond_resched(void)
>> +{
>> +	if (!preempt_count()) {
>> +		if (need_resched() && arm64_preempt_schedule_irq())
>> +			preempt_schedule_irq();
>> +	}
>> +}
>> +
>> +#ifdef CONFIG_PREEMPT_DYNAMIC
>> +DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
>> +void dynamic_irqentry_exit_cond_resched(void)
>> +{
>> +	if (!static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
>> +		return;
>> +	raw_irqentry_exit_cond_resched();
>> +}
>> +#endif
>> +
>>  static __always_inline void __el1_irq(struct pt_regs *regs,
>>  				      void (*handler)(struct pt_regs *))
>>  {
>> @@ -681,10 +688,8 @@ static __always_inline void __el1_irq(struct pt_regs *regs,
>>  	do_interrupt_handler(regs, handler);
>>  	irq_exit_rcu();
>>  
>> -	if (!preempt_count() && need_resched()) {
>> -		if (arm64_preempt_schedule_irq())
>> -			preempt_schedule_irq();
>> -	}
>> +	if (IS_ENABLED(CONFIG_PREEMPTION))
>> +		irqentry_exit_cond_resched();
>>  
>>  	exit_to_kernel_mode(regs, state);
>>  }
>> diff --git a/kernel/entry/common.c b/kernel/entry/common.c
>> index b82032777310..4aa9656fa1b4 100644
>> --- a/kernel/entry/common.c
>> +++ b/kernel/entry/common.c
>> @@ -142,6 +142,20 @@ noinstr irqentry_state_t irqentry_enter(struct pt_regs *regs)
>>  	return ret;
>>  }
>>  
>> +/**
>> + * arch_irqentry_exit_need_resched - Architecture specific need resched function
>> + *
>> + * Invoked from raw_irqentry_exit_cond_resched() to check if need resched.
>> + * Defaults return true.
>> + *
>> + * The main purpose is to permit arch to skip preempt a task from an IRQ.
>> + */
>> +static inline bool arch_irqentry_exit_need_resched(void);
>> +
>> +#ifndef arch_irqentry_exit_need_resched
>> +static inline bool arch_irqentry_exit_need_resched(void) { return true; }
>> +#endif
>> +
>>  void raw_irqentry_exit_cond_resched(void)
>>  {
>>  	if (!preempt_count()) {
>> @@ -149,7 +163,7 @@ void raw_irqentry_exit_cond_resched(void)
>>  		rcu_irq_exit_check_preempt();
>>  		if (IS_ENABLED(CONFIG_DEBUG_ENTRY))
>>  			WARN_ON_ONCE(!on_thread_stack());
>> -		if (need_resched())
>> +		if (need_resched() && arch_irqentry_exit_need_resched())
>>  			preempt_schedule_irq();
>>  	}
>>  }
>> -- 
>> 2.34.1
>>
> 
> 


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Subject: Re: [PATCH -next v7 0/7] arm64: entry: Convert to generic irq entry
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References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 <6bd09b5b-9830-42b4-ad9e-9ad1e153e564@arm.com>
 <94757d00-5a8e-ac6b-f832-030f33ccf771@huawei.com>
 
From: Jinjie Ruan 
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On 2025/8/12 0:03, Ada Couprie Diaz wrote:
> On 06/08/2025 09:11, Jinjie Ruan wrote:
> 
>> On 2025/8/5 23:08, Ada Couprie Diaz wrote:
>>> Hi Jinjie,
>>>
>>> On 29/07/2025 02:54, Jinjie Ruan wrote:
>>>
>>>> Since commit a70e9f647f50 ("entry: Split generic entry into generic
>>>> exception and syscall entry") split the generic entry into generic irq
>>>> entry and generic syscall entry, it is time to convert arm64 to use
>>>> the generic irq entry. And ARM64 will be completely converted to
>>>> generic
>>>> entry in the upcoming patch series.
>>> Note : I had to manually cherry-pick a70e9f647f50 when pulling the
>>> series
>>> on top of the Linux Arm Kernel for-next/core branch, but there might be
>>> something I'm missing here.
>> It seems that it is now in mainline v6.16-rc1 and linux-next but not
>> Linux Arm Kernel for-next/core branch.
> You're right, I misinterpreted the `-next` of the subject, thanks for the
> clarification !
>>> I'll spend some time testing the series now, specifically given patch
>>> 6's
>>> changes, but other than that everything I saw made sense and didn't look
>>> like it would be of concern to me.
>> Thank you for the test and review.
> 
> I've spent some time testing the series with a few different
> configurations,
> including PREEMPT_RT, pNMI, various lockup and hang detection options,
> UBSAN, shadow call stack, and various CONFIG_DEBUG_XYZ (focused on locks
> and IRQs), on both hardware (AMD Seattle) and KVM guests.
> 
> I tried to generate a diverse set of interrupts (via debug exceptions,
> page faults, perf, kprobes, swapping, OoM) while loading the system with
> different workloads, some generating a lot of context switches : hackbench
> and signaltest from rt-tests[0], and mc-crusher[1], a memcached
> stress-test.
> 
> I did not have any issues, nor any warning reported by the various
> debug features during all my hours of testing, so it looks good !
> 
> Tested-by: Ada Couprie Diaz 

Thank you for your comprehensive testing and code review.

> 
> Thank you for the series !
> Ada
> 
> [0]: https://git.kernel.org/pub/scm/utils/rt-tests/rt-tests.git/
> [1]: https://github.com/memcached/mc-crusher
> 
> 


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Subject: Re: [PATCH -next v7 0/7] arm64: entry: Convert to generic irq entry
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References: <20250729015456.3411143-1-ruanjinjie@huawei.com>
 
From: Jinjie Ruan 
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On 2025/8/12 19:19, Mark Rutland wrote:
> Hi,
> 
> This is looking pretty good now, thanks for continuing to work on this!
> 
> I've left a couple of minor comments, and Ada has left a few more. If
> you're able to address those and respin atop v6.17-rc1, I think we can
> start figuring out how to queue this.

Sure，I will revise these review comments based on v6.17-rc1 and release
a new version after local testing.

> 
> Mark.
> 
> On Tue, Jul 29, 2025 at 09:54:49AM +0800, Jinjie Ruan wrote:
>> Currently, x86, Riscv, Loongarch use the generic entry. Also convert
>> arm64 to use the generic entry infrastructure from kernel/entry/*.
>> The generic entry makes maintainers' work easier and codes more elegant,
>> which will make PREEMPT_DYNAMIC and PREEMPT_LAZY use the generic entry
>> common code and remove a lot of duplicate code.
>>
>> Since commit a70e9f647f50 ("entry: Split generic entry into generic
>> exception and syscall entry") split the generic entry into generic irq
>> entry and generic syscall entry, it is time to convert arm64 to use
>> the generic irq entry. And ARM64 will be completely converted to generic
>> entry in the upcoming patch series.
>>
>> The main convert steps are as follows:
>> - Split generic entry into generic irq entry and generic syscall to
>>   make the single patch more concentrated in switching to one thing.
>> - Make arm64 easier to use irqentry_enter/exit().
>> - Make arm64 closer to the PREEMPT_DYNAMIC code of generic entry.
>> - Switch to generic irq entry.
>>
>> It was tested ok with following test cases on QEMU virt platform:
>>  - Perf tests.
>>  - Different `dynamic preempt` mode switch.
>>  - Pseudo NMI tests.
>>  - Stress-ng CPU stress test.
>>  - MTE test case in Documentation/arch/arm64/memory-tagging-extension.rst
>>    and all test cases in tools/testing/selftests/arm64/mte/*.
>>
>> The test QEMU configuration is as follows:
>>
>> 	qemu-system-aarch64 \
>> 		-M virt,gic-version=3,virtualization=on,mte=on \
>> 		-cpu max,pauth-impdef=on \
>> 		-kernel Image \
>> 		-smp 8,sockets=1,cores=4,threads=2 \
>> 		-m 512m \
>> 		-nographic \
>> 		-no-reboot \
>> 		-device virtio-rng-pci \
>> 		-append "root=/dev/vda rw console=ttyAMA0 kgdboc=ttyAMA0,115200 \
>> 			earlycon preempt=voluntary irqchip.gicv3_pseudo_nmi=1" \
>> 		-drive if=none,file=images/rootfs.ext4,format=raw,id=hd0 \
>> 		-device virtio-blk-device,drive=hd0 \
>>
>> Changes in v7:
>> - Rebased on v6.16-rc7 and remove the merged first patch.
>> - Update the commit message.
>>
>> Changes in v6:
>> - Rebased on 6.14 rc2 next.
>> - Put the syscall bits aside and split it out.
>> - Have the split patch before the arm64 changes.
>> - Merge some tightly coupled patches.
>> - Adjust the order of some patches to make them more reasonable.
>> - Define regs_irqs_disabled() by inline function.
>> - Define interrupts_enabled() in terms of regs_irqs_disabled().
>> - Delete the fast_interrupts_enabled() macro.
>> - irqentry_state_t -> arm64_irqentry_state_t.
>> - Remove arch_exit_to_user_mode_prepare() and pull local_daif_mask() later
>>   in the arm64 exit sequence
>> - Update the commit message.
>>
>> Changes in v5:
>> - Not change arm32 and keep inerrupts_enabled() macro for gicv3 driver.
>> - Move irqentry_state definition into arch/arm64/kernel/entry-common.c.
>> - Avoid removing the __enter_from_*() and __exit_to_*() wrappers.
>> - Update "irqentry_state_t ret/irq_state" to "state"
>>   to keep it consistently.
>> - Use generic irq entry header for PREEMPT_DYNAMIC after split
>>   the generic entry.
>> - Also refactor the ARM64 syscall code.
>> - Introduce arch_ptrace_report_syscall_entry/exit(), instead of
>>   arch_pre/post_report_syscall_entry/exit() to simplify code.
>> - Make the syscall patches clear separation.
>> - Update the commit message.
>>
>> Changes in v4:
>> - Rework/cleanup split into a few patches as Mark suggested.
>> - Replace interrupts_enabled() macro with regs_irqs_disabled(), instead
>>   of left it here.
>> - Remove rcu and lockdep state in pt_regs by using temporary
>>   irqentry_state_t as Mark suggested.
>> - Remove some unnecessary intermediate functions to make it clear.
>> - Rework preempt irq and PREEMPT_DYNAMIC code
>>   to make the switch more clear.
>> - arch_prepare_*_entry/exit() -> arch_pre_*_entry/exit().
>> - Expand the arch functions comment.
>> - Make arch functions closer to its caller.
>> - Declare saved_reg in for block.
>> - Remove arch_exit_to_kernel_mode_prepare(), arch_enter_from_kernel_mode().
>> - Adjust "Add few arch functions to use generic entry" patch to be
>>   the penultimate.
>> - Update the commit message.
>> - Add suggested-by.
>>
>> Changes in v3:
>> - Test the MTE test cases.
>> - Handle forget_syscall() in arch_post_report_syscall_entry()
>> - Make the arch funcs not use __weak as Thomas suggested, so move
>>   the arch funcs to entry-common.h, and make arch_forget_syscall() folded
>>   in arch_post_report_syscall_entry() as suggested.
>> - Move report_single_step() to thread_info.h for arm64
>> - Change __always_inline() to inline, add inline for the other arch funcs.
>> - Remove unused signal.h for entry-common.h.
>> - Add Suggested-by.
>> - Update the commit message.
>>
>> Changes in v2:
>> - Add tested-by.
>> - Fix a bug that not call arch_post_report_syscall_entry() in
>>   syscall_trace_enter() if ptrace_report_syscall_entry() return not zero.
>> - Refactor report_syscall().
>> - Add comment for arch_prepare_report_syscall_exit().
>> - Adjust entry-common.h header file inclusion to alphabetical order.
>> - Update the commit message.
>>
>> Jinjie Ruan (7):
>>   arm64: ptrace: Replace interrupts_enabled() with regs_irqs_disabled()
>>   arm64: entry: Refactor the entry and exit for exceptions from EL1
>>   arm64: entry: Rework arm64_preempt_schedule_irq()
>>   arm64: entry: Use preempt_count() and need_resched() helper
>>   arm64: entry: Refactor preempt_schedule_irq() check code
>>   arm64: entry: Move arm64_preempt_schedule_irq() into
>>     __exit_to_kernel_mode()
>>   arm64: entry: Switch to generic IRQ entry
>>
>>  arch/arm64/Kconfig                    |   1 +
>>  arch/arm64/include/asm/daifflags.h    |   2 +-
>>  arch/arm64/include/asm/entry-common.h |  56 ++++
>>  arch/arm64/include/asm/preempt.h      |   2 -
>>  arch/arm64/include/asm/ptrace.h       |  13 +-
>>  arch/arm64/include/asm/xen/events.h   |   2 +-
>>  arch/arm64/kernel/acpi.c              |   2 +-
>>  arch/arm64/kernel/debug-monitors.c    |   2 +-
>>  arch/arm64/kernel/entry-common.c      | 411 +++++++++-----------------
>>  arch/arm64/kernel/sdei.c              |   2 +-
>>  arch/arm64/kernel/signal.c            |   3 +-
>>  kernel/entry/common.c                 |  16 +-
>>  12 files changed, 217 insertions(+), 295 deletions(-)
>>  create mode 100644 arch/arm64/include/asm/entry-common.h
>>
>> -- 
>> 2.34.1
>>
> 


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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
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	Michael Ellerman ,
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	xen-devel@lists.xenproject.org
Subject: [PATCH v2 02/16] iommu/dma: implement DMA_ATTR_MMIO for dma_iova_link().
Date: Thu, 14 Aug 2025 13:13:20 +0300
Message-ID: <4f39936e5a7319a848b1eebffe928c251e2ec0d6.1755153054.git.leon@kernel.org>
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From: Leon Romanovsky 

This will replace the hacky use of DMA_ATTR_SKIP_CPU_SYNC to avoid
touching the possibly non-KVA MMIO memory.

Also correct the incorrect caching attribute for the IOMMU, MMIO
memory should not be cachable inside the IOMMU mapping or it can
possibly create system problems. Set IOMMU_MMIO for DMA_ATTR_MMIO.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index ea2ef53bd4fe..e1185ba73e23 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -724,7 +724,12 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, struct device *dev
 static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
 		     unsigned long attrs)
 {
-	int prot = coherent ? IOMMU_CACHE : 0;
+	int prot;
+
+	if (attrs & DMA_ATTR_MMIO)
+		prot = IOMMU_MMIO;
+	else
+		prot = coherent ? IOMMU_CACHE : 0;
 
 	if (attrs & DMA_ATTR_PRIVILEGED)
 		prot |= IOMMU_PRIV;
@@ -1838,12 +1843,13 @@ static int __dma_iova_link(struct device *dev, dma_addr_t addr,
 		unsigned long attrs)
 {
 	bool coherent = dev_is_dma_coherent(dev);
+	int prot = dma_info_to_prot(dir, coherent, attrs);
 
-	if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+	if (!coherent && !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
 		arch_sync_dma_for_device(phys, size, dir);
 
 	return iommu_map_nosync(iommu_get_dma_domain(dev), addr, phys, size,
-			dma_info_to_prot(dir, coherent, attrs), GFP_ATOMIC);
+			prot, GFP_ATOMIC);
 }
 
 static int iommu_dma_iova_bounce_and_link(struct device *dev, dma_addr_t addr,
@@ -1949,9 +1955,13 @@ int dma_iova_link(struct device *dev, struct dma_iova_state *state,
 		return -EIO;
 
 	if (dev_use_swiotlb(dev, size, dir) &&
-	    iova_unaligned(iovad, phys, size))
+	    iova_unaligned(iovad, phys, size)) {
+		if (attrs & DMA_ATTR_MMIO)
+			return -EPERM;
+
 		return iommu_dma_iova_link_swiotlb(dev, state, phys, offset,
 				size, dir, attrs);
+	}
 
 	return __dma_iova_link(dev, state->addr + offset - iova_start_pad,
 			phys - iova_start_pad,
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 00/16] dma-mapping: migrate to physical address-based API
Date: Thu, 14 Aug 2025 13:13:18 +0300
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Changelog:
v2:
 * Used commit messages and cover letter from Jason
 * Moved setting IOMMU_MMIO flag to dma_info_to_prot function
 * Micro-optimized the code
 * Rebased code on v6.17-rc1
v1: https://lore.kernel.org/all/cover.1754292567.git.leon@kernel.org
 * Added new DMA_ATTR_MMIO attribute to indicate
   PCI_P2PDMA_MAP_THRU_HOST_BRIDGE path.
 * Rewrote dma_map_* functions to use thus new attribute
v0: https://lore.kernel.org/all/cover.1750854543.git.leon@kernel.org/
------------------------------------------------------------------------

This series refactors the DMA mapping to use physical addresses
as the primary interface instead of page+offset parameters. This
change aligns the DMA API with the underlying hardware reality where
DMA operations work with physical addresses, not page structures.

The series maintains export symbol backward compatibility by keeping
the old page-based API as wrapper functions around the new physical
address-based implementations.

This series refactors the DMA mapping API to provide a phys_addr_t
based, and struct-page free, external API that can handle all the
mapping cases we want in modern systems:

 - struct page based cachable DRAM
 - struct page MEMORY_DEVICE_PCI_P2PDMA PCI peer to peer non-cachable
   MMIO
 - struct page-less PCI peer to peer non-cachable MMIO
 - struct page-less "resource" MMIO

Overall this gets much closer to Matthew's long term wish for
struct-pageless IO to cachable DRAM. The remaining primary work would
be in the mm side to allow kmap_local_pfn()/phys_to_virt() to work on
phys_addr_t without a struct page.

The general design is to remove struct page usage entirely from the
DMA API inner layers. For flows that need to have a KVA for the
physical address they can use kmap_local_pfn() or phys_to_virt(). This
isolates the struct page requirements to MM code only. Long term all
removals of struct page usage are supporting Matthew's memdesc
project which seeks to substantially transform how struct page works.

Instead make the DMA API internals work on phys_addr_t. Internally
there are still dedicated 'page' and 'resource' flows, except they are
now distinguished by a new DMA_ATTR_MMIO instead of by callchain. Both
flows use the same phys_addr_t.

When DMA_ATTR_MMIO is specified things work similar to the existing
'resource' flow. kmap_local_pfn(), phys_to_virt(), phys_to_page(),
pfn_valid(), etc are never called on the phys_addr_t. This requires
rejecting any configuration that would need swiotlb. CPU cache
flushing is not required, and avoided, as ATTR_MMIO also indicates the
address have no cachable mappings. This effectively removes any
DMA API side requirement to have struct page when DMA_ATTR_MMIO is
used.

In the !DMA_ATTR_MMIO mode things work similarly to the 'page' flow,
except on the common path of no cache flush, no swiotlb it never
touches a struct page. When cache flushing or swiotlb copying
kmap_local_pfn()/phys_to_virt() are used to get a KVA for CPU
usage. This was already the case on the unmap side, now the map side
is symmetric.

Callers are adjusted to set DMA_ATTR_MMIO. Existing 'resource' users
must set it. The existing struct page based MEMORY_DEVICE_PCI_P2PDMA
path must also set it. This corrects some existing bugs where iommu
mappings for P2P MMIO were improperly marked IOMMU_CACHE.

Since ATTR_MMIO is made to work with all the existing DMA map entry
points, particularly dma_iova_link(), this finally allows a way to use
the new DMA API to map PCI P2P MMIO without creating struct page. The
VFIO DMABUF series demonstrates how this works. This is intended to
replace the incorrect driver use of dma_map_resource() on PCI BAR
addresses.

This series does the core code and modern flows. A followup series
will give the same treatment to the legacy dma_ops implementation.

Thanks

Leon Romanovsky (16):
  dma-mapping: introduce new DMA attribute to indicate MMIO memory
  iommu/dma: implement DMA_ATTR_MMIO for dma_iova_link().
  dma-debug: refactor to use physical addresses for page mapping
  dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys
  iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys
  iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory
  dma-mapping: convert dma_direct_*map_page to be phys_addr_t based
  kmsan: convert kmsan_handle_dma to use physical addresses
  dma-mapping: handle MMIO flow in dma_map|unmap_page
  xen: swiotlb: Open code map_resource callback
  dma-mapping: export new dma_*map_phys() interface
  mm/hmm: migrate to physical address-based DMA mapping API
  mm/hmm: properly take MMIO path
  block-dma: migrate to dma_map_phys instead of map_page
  block-dma: properly take MMIO path
  nvme-pci: unmap MMIO pages with appropriate interface

 Documentation/core-api/dma-api.rst        |   4 +-
 Documentation/core-api/dma-attributes.rst |  18 ++++
 arch/powerpc/kernel/dma-iommu.c           |   4 +-
 block/blk-mq-dma.c                        |  15 ++-
 drivers/iommu/dma-iommu.c                 |  61 ++++++------
 drivers/nvme/host/pci.c                   |  18 +++-
 drivers/virtio/virtio_ring.c              |   4 +-
 drivers/xen/swiotlb-xen.c                 |  21 +++-
 include/linux/blk-mq-dma.h                |   6 +-
 include/linux/blk_types.h                 |   2 +
 include/linux/dma-direct.h                |   2 -
 include/linux/dma-map-ops.h               |   8 +-
 include/linux/dma-mapping.h               |  33 ++++++
 include/linux/iommu-dma.h                 |  11 +-
 include/linux/kmsan.h                     |  12 ++-
 include/trace/events/dma.h                |   9 +-
 kernel/dma/debug.c                        |  71 ++++---------
 kernel/dma/debug.h                        |  37 ++-----
 kernel/dma/direct.c                       |  22 +---
 kernel/dma/direct.h                       |  52 ++++++----
 kernel/dma/mapping.c                      | 116 +++++++++++++---------
 kernel/dma/ops_helpers.c                  |   6 +-
 mm/hmm.c                                  |  19 ++--
 mm/kmsan/hooks.c                          |  36 +++++--
 rust/kernel/dma.rs                        |   3 +
 tools/virtio/linux/kmsan.h                |   2 +-
 26 files changed, 333 insertions(+), 259 deletions(-)

-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 01/16] dma-mapping: introduce new DMA attribute to indicate MMIO memory
Date: Thu, 14 Aug 2025 13:13:19 +0300
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From: Leon Romanovsky 

This patch introduces the DMA_ATTR_MMIO attribute to mark DMA buffers
that reside in memory-mapped I/O (MMIO) regions, such as device BARs
exposed through the host bridge, which are accessible for peer-to-peer
(P2P) DMA.

This attribute is especially useful for exporting device memory to other
devices for DMA without CPU involvement, and avoids unnecessary or
potentially detrimental CPU cache maintenance calls.

DMA_ATTR_MMIO is supposed to provide dma_map_resource() functionality
without need to call to special function and perform branching by
the callers.

Signed-off-by: Leon Romanovsky 
---
 Documentation/core-api/dma-attributes.rst | 18 ++++++++++++++++++
 include/linux/dma-mapping.h               | 20 ++++++++++++++++++++
 include/trace/events/dma.h                |  3 ++-
 rust/kernel/dma.rs                        |  3 +++
 4 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst
index 1887d92e8e92..58a1528a9bb9 100644
--- a/Documentation/core-api/dma-attributes.rst
+++ b/Documentation/core-api/dma-attributes.rst
@@ -130,3 +130,21 @@ accesses to DMA buffers in both privileged "supervisor" and unprivileged
 subsystem that the buffer is fully accessible at the elevated privilege
 level (and ideally inaccessible or at least read-only at the
 lesser-privileged levels).
+
+DMA_ATTR_MMIO
+-------------
+
+This attribute indicates the physical address is not normal system
+memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page()
+functions, it may not be cachable, and access using CPU load/store
+instructions may not be allowed.
+
+Usually this will be used to describe MMIO addresses, or other non
+cachable register addresses. When DMA mapping this sort of address we
+call the operation Peer to Peer as a one device is DMA'ing to another
+device. For PCI devices the p2pdma APIs must be used to determine if
+DMA_ATTR_MMIO is appropriate.
+
+For architectures that require cache flushing for DMA coherence
+DMA_ATTR_MMIO will not perform any cache flushing. The address
+provided must never be mapped cachable into the CPU.
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 55c03e5fe8cb..ead5514d389e 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -58,6 +58,26 @@
  */
 #define DMA_ATTR_PRIVILEGED		(1UL << 9)
 
+/*
+ * DMA_ATTR_MMIO - Indicates memory-mapped I/O (MMIO) region for DMA mapping
+ *
+ * This attribute indicates the physical address is not normal system
+ * memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page()
+ * functions, it may not be cachable, and access using CPU load/store
+ * instructions may not be allowed.
+ *
+ * Usually this will be used to describe MMIO addresses, or other non
+ * cachable register addresses. When DMA mapping this sort of address we
+ * call the operation Peer to Peer as a one device is DMA'ing to another
+ * device. For PCI devices the p2pdma APIs must be used to determine if
+ * DMA_ATTR_MMIO is appropriate.
+ *
+ * For architectures that require cache flushing for DMA coherence
+ * DMA_ATTR_MMIO will not perform any cache flushing. The address
+ * provided must never be mapped cachable into the CPU.
+ */
+#define DMA_ATTR_MMIO		(1UL << 10)
+
 /*
  * A dma_addr_t can hold any valid DMA or bus address for the platform.  It can
  * be given to a device to use as a DMA source or target.  It is specific to a
diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h
index d8ddc27b6a7c..ee90d6f1dcf3 100644
--- a/include/trace/events/dma.h
+++ b/include/trace/events/dma.h
@@ -31,7 +31,8 @@ TRACE_DEFINE_ENUM(DMA_NONE);
 		{ DMA_ATTR_FORCE_CONTIGUOUS, "FORCE_CONTIGUOUS" }, \
 		{ DMA_ATTR_ALLOC_SINGLE_PAGES, "ALLOC_SINGLE_PAGES" }, \
 		{ DMA_ATTR_NO_WARN, "NO_WARN" }, \
-		{ DMA_ATTR_PRIVILEGED, "PRIVILEGED" })
+		{ DMA_ATTR_PRIVILEGED, "PRIVILEGED" }, \
+		{ DMA_ATTR_MMIO, "MMIO" })
 
 DECLARE_EVENT_CLASS(dma_map,
 	TP_PROTO(struct device *dev, phys_addr_t phys_addr, dma_addr_t dma_addr,
diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs
index 2bc8ab51ec28..61d9eed7a786 100644
--- a/rust/kernel/dma.rs
+++ b/rust/kernel/dma.rs
@@ -242,6 +242,9 @@ pub mod attrs {
     /// Indicates that the buffer is fully accessible at an elevated privilege level (and
     /// ideally inaccessible or at least read-only at lesser-privileged levels).
     pub const DMA_ATTR_PRIVILEGED: Attrs = Attrs(bindings::DMA_ATTR_PRIVILEGED);
+
+    /// Indicates that the buffer is MMIO memory.
+    pub const DMA_ATTR_MMIO: Attrs = Attrs(bindings::DMA_ATTR_MMIO);
 }
 
 /// An abstraction of the `dma_alloc_coherent` API.
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 04/16] dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys
Date: Thu, 14 Aug 2025 13:13:22 +0300
Message-ID: <18459094e29f22a137a9a77c614bcef07963f769.1755153054.git.leon@kernel.org>
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From: Leon Romanovsky 

As a preparation for following map_page -> map_phys API conversion,
let's rename trace_dma_*map_page() to be trace_dma_*map_phys().

Signed-off-by: Leon Romanovsky 
---
 include/trace/events/dma.h | 4 ++--
 kernel/dma/mapping.c       | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h
index ee90d6f1dcf3..84416c7d6bfa 100644
--- a/include/trace/events/dma.h
+++ b/include/trace/events/dma.h
@@ -72,7 +72,7 @@ DEFINE_EVENT(dma_map, name, \
 		 size_t size, enum dma_data_direction dir, unsigned long attrs), \
 	TP_ARGS(dev, phys_addr, dma_addr, size, dir, attrs))
 
-DEFINE_MAP_EVENT(dma_map_page);
+DEFINE_MAP_EVENT(dma_map_phys);
 DEFINE_MAP_EVENT(dma_map_resource);
 
 DECLARE_EVENT_CLASS(dma_unmap,
@@ -110,7 +110,7 @@ DEFINE_EVENT(dma_unmap, name, \
 		 enum dma_data_direction dir, unsigned long attrs), \
 	TP_ARGS(dev, addr, size, dir, attrs))
 
-DEFINE_UNMAP_EVENT(dma_unmap_page);
+DEFINE_UNMAP_EVENT(dma_unmap_phys);
 DEFINE_UNMAP_EVENT(dma_unmap_resource);
 
 DECLARE_EVENT_CLASS(dma_alloc_class,
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 4c1dfbabb8ae..fe1f0da6dc50 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -173,7 +173,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
 	kmsan_handle_dma(page, offset, size, dir);
-	trace_dma_map_page(dev, phys, addr, size, dir, attrs);
+	trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
 	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
 	return addr;
@@ -193,7 +193,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 		iommu_dma_unmap_page(dev, addr, size, dir, attrs);
 	else
 		ops->unmap_page(dev, addr, size, dir, attrs);
-	trace_dma_unmap_page(dev, addr, size, dir, attrs);
+	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
 	debug_dma_unmap_phys(dev, addr, size, dir);
 }
 EXPORT_SYMBOL(dma_unmap_page_attrs);
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
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	xen-devel@lists.xenproject.org
Subject: [PATCH v2 05/16] iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys
Date: Thu, 14 Aug 2025 13:13:23 +0300
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From: Leon Romanovsky 

Rename the IOMMU DMA mapping functions to better reflect their actual
calling convention. The functions iommu_dma_map_page() and
iommu_dma_unmap_page() are renamed to iommu_dma_map_phys() and
iommu_dma_unmap_phys() respectively, as they already operate on physical
addresses rather than page structures.

The calling convention changes from accepting (struct page *page,
unsigned long offset) to (phys_addr_t phys), which eliminates the need
for page-to-physical address conversion within the functions. This
renaming prepares for the broader DMA API conversion from page-based
to physical address-based mapping throughout the kernel.

All callers are updated to pass physical addresses directly, including
dma_map_page_attrs(), scatterlist mapping functions, and DMA page
allocation helpers. The change simplifies the code by removing the
page_to_phys() + offset calculation that was previously done inside
the IOMMU functions.

Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c | 14 ++++++--------
 include/linux/iommu-dma.h |  7 +++----
 kernel/dma/mapping.c      |  4 ++--
 kernel/dma/ops_helpers.c  |  6 +++---
 4 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index e1185ba73e23..aea119f32f96 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -1195,11 +1195,9 @@ static inline size_t iova_unaligned(struct iova_domain *iovad, phys_addr_t phys,
 	return iova_offset(iovad, phys | size);
 }
 
-dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
-	      unsigned long offset, size_t size, enum dma_data_direction dir,
-	      unsigned long attrs)
+dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs)
 {
-	phys_addr_t phys = page_to_phys(page) + offset;
 	bool coherent = dev_is_dma_coherent(dev);
 	int prot = dma_info_to_prot(dir, coherent, attrs);
 	struct iommu_domain *domain = iommu_get_dma_domain(dev);
@@ -1227,7 +1225,7 @@ dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
 	return iova;
 }
 
-void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
+void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
 	struct iommu_domain *domain = iommu_get_dma_domain(dev);
@@ -1346,7 +1344,7 @@ static void iommu_dma_unmap_sg_swiotlb(struct device *dev, struct scatterlist *s
 	int i;
 
 	for_each_sg(sg, s, nents, i)
-		iommu_dma_unmap_page(dev, sg_dma_address(s),
+		iommu_dma_unmap_phys(dev, sg_dma_address(s),
 				sg_dma_len(s), dir, attrs);
 }
 
@@ -1359,8 +1357,8 @@ static int iommu_dma_map_sg_swiotlb(struct device *dev, struct scatterlist *sg,
 	sg_dma_mark_swiotlb(sg);
 
 	for_each_sg(sg, s, nents, i) {
-		sg_dma_address(s) = iommu_dma_map_page(dev, sg_page(s),
-				s->offset, s->length, dir, attrs);
+		sg_dma_address(s) = iommu_dma_map_phys(dev, sg_phys(s),
+				s->length, dir, attrs);
 		if (sg_dma_address(s) == DMA_MAPPING_ERROR)
 			goto out_unmap;
 		sg_dma_len(s) = s->length;
diff --git a/include/linux/iommu-dma.h b/include/linux/iommu-dma.h
index 508beaa44c39..485bdffed988 100644
--- a/include/linux/iommu-dma.h
+++ b/include/linux/iommu-dma.h
@@ -21,10 +21,9 @@ static inline bool use_dma_iommu(struct device *dev)
 }
 #endif /* CONFIG_IOMMU_DMA */
 
-dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
-		unsigned long offset, size_t size, enum dma_data_direction dir,
-		unsigned long attrs);
-void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
+dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs);
+void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle,
 		size_t size, enum dma_data_direction dir, unsigned long attrs);
 int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 		enum dma_data_direction dir, unsigned long attrs);
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index fe1f0da6dc50..58482536db9b 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -169,7 +169,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 	    arch_dma_map_page_direct(dev, phys + size))
 		addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
 	else if (use_dma_iommu(dev))
-		addr = iommu_dma_map_page(dev, page, offset, size, dir, attrs);
+		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
 	kmsan_handle_dma(page, offset, size, dir);
@@ -190,7 +190,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 	    arch_dma_unmap_page_direct(dev, addr + size))
 		dma_direct_unmap_page(dev, addr, size, dir, attrs);
 	else if (use_dma_iommu(dev))
-		iommu_dma_unmap_page(dev, addr, size, dir, attrs);
+		iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
 	else
 		ops->unmap_page(dev, addr, size, dir, attrs);
 	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
diff --git a/kernel/dma/ops_helpers.c b/kernel/dma/ops_helpers.c
index 9afd569eadb9..6f9d604d9d40 100644
--- a/kernel/dma/ops_helpers.c
+++ b/kernel/dma/ops_helpers.c
@@ -72,8 +72,8 @@ struct page *dma_common_alloc_pages(struct device *dev, size_t size,
 		return NULL;
 
 	if (use_dma_iommu(dev))
-		*dma_handle = iommu_dma_map_page(dev, page, 0, size, dir,
-						 DMA_ATTR_SKIP_CPU_SYNC);
+		*dma_handle = iommu_dma_map_phys(dev, page_to_phys(page), size,
+						 dir, DMA_ATTR_SKIP_CPU_SYNC);
 	else
 		*dma_handle = ops->map_page(dev, page, 0, size, dir,
 					    DMA_ATTR_SKIP_CPU_SYNC);
@@ -92,7 +92,7 @@ void dma_common_free_pages(struct device *dev, size_t size, struct page *page,
 	const struct dma_map_ops *ops = get_dma_ops(dev);
 
 	if (use_dma_iommu(dev))
-		iommu_dma_unmap_page(dev, dma_handle, size, dir,
+		iommu_dma_unmap_phys(dev, dma_handle, size, dir,
 				     DMA_ATTR_SKIP_CPU_SYNC);
 	else if (ops->unmap_page)
 		ops->unmap_page(dev, dma_handle, size, dir,
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
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	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 06/16] iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory
Date: Thu, 14 Aug 2025 13:13:24 +0300
Message-ID: <3086f426f3ded9c671e9a6441810c21efc9ad87f.1755153054.git.leon@kernel.org>
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From: Leon Romanovsky 

Combine iommu_dma_*map_phys with iommu_dma_*map_resource interfaces in
order to allow single phys_addr_t flow.

In the following patches, the iommu_dma_map_resource() will be removed
in favour of iommu_dma_map_phys(..., attrs | DMA_ATTR_MMIO) flow.

Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index aea119f32f96..6804aaf034a1 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -1211,16 +1211,19 @@ dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
 	 */
 	if (dev_use_swiotlb(dev, size, dir) &&
 	    iova_unaligned(iovad, phys, size)) {
+		if (attrs & DMA_ATTR_MMIO)
+			return DMA_MAPPING_ERROR;
+
 		phys = iommu_dma_map_swiotlb(dev, phys, size, dir, attrs);
 		if (phys == (phys_addr_t)DMA_MAPPING_ERROR)
 			return DMA_MAPPING_ERROR;
 	}
 
-	if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+	if (!coherent && !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
 		arch_sync_dma_for_device(phys, size, dir);
 
 	iova = __iommu_dma_map(dev, phys, size, prot, dma_mask);
-	if (iova == DMA_MAPPING_ERROR)
+	if (iova == DMA_MAPPING_ERROR && !(attrs & DMA_ATTR_MMIO))
 		swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
 	return iova;
 }
@@ -1228,10 +1231,14 @@ dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
 void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
-	struct iommu_domain *domain = iommu_get_dma_domain(dev);
 	phys_addr_t phys;
 
-	phys = iommu_iova_to_phys(domain, dma_handle);
+	if (attrs & DMA_ATTR_MMIO) {
+		__iommu_dma_unmap(dev, dma_handle, size);
+		return;
+	}
+
+	phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
 	if (WARN_ON(!phys))
 		return;
 
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 03/16] dma-debug: refactor to use physical addresses for page mapping
Date: Thu, 14 Aug 2025 13:13:21 +0300
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From: Leon Romanovsky 

Convert the DMA debug infrastructure from page-based to physical address-based
mapping as a preparation to rely on physical address for DMA mapping routines.

The refactoring renames debug_dma_map_page() to debug_dma_map_phys() and
changes its signature to accept a phys_addr_t parameter instead of struct page
and offset. Similarly, debug_dma_unmap_page() becomes debug_dma_unmap_phys().
A new dma_debug_phy type is introduced to distinguish physical address mappings
from other debug entry types. All callers throughout the codebase are updated
to pass physical addresses directly, eliminating the need for page-to-physical
conversion in the debug layer.

This refactoring eliminates the need to convert between page pointers and
physical addresses in the debug layer, making the code more efficient and
consistent with the DMA mapping API's physical address focus.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 Documentation/core-api/dma-api.rst |  4 ++--
 kernel/dma/debug.c                 | 28 +++++++++++++++++-----------
 kernel/dma/debug.h                 | 16 +++++++---------
 kernel/dma/mapping.c               | 15 ++++++++-------
 4 files changed, 34 insertions(+), 29 deletions(-)

diff --git a/Documentation/core-api/dma-api.rst b/Documentation/core-api/dma-api.rst
index 3087bea715ed..ca75b3541679 100644
--- a/Documentation/core-api/dma-api.rst
+++ b/Documentation/core-api/dma-api.rst
@@ -761,7 +761,7 @@ example warning message may look like this::
 	[] find_busiest_group+0x207/0x8a0
 	[] _spin_lock_irqsave+0x1f/0x50
 	[] check_unmap+0x203/0x490
-	[] debug_dma_unmap_page+0x49/0x50
+	[] debug_dma_unmap_phys+0x49/0x50
 	[] nv_tx_done_optimized+0xc6/0x2c0
 	[] nv_nic_irq_optimized+0x73/0x2b0
 	[] handle_IRQ_event+0x34/0x70
@@ -855,7 +855,7 @@ that a driver may be leaking mappings.
 dma-debug interface debug_dma_mapping_error() to debug drivers that fail
 to check DMA mapping errors on addresses returned by dma_map_single() and
 dma_map_page() interfaces. This interface clears a flag set by
-debug_dma_map_page() to indicate that dma_mapping_error() has been called by
+debug_dma_map_phys() to indicate that dma_mapping_error() has been called by
 the driver. When driver does unmap, debug_dma_unmap() checks the flag and if
 this flag is still set, prints warning message that includes call trace that
 leads up to the unmap. This interface can be called from dma_mapping_error()
diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c
index e43c6de2bce4..da6734e3a4ce 100644
--- a/kernel/dma/debug.c
+++ b/kernel/dma/debug.c
@@ -39,6 +39,7 @@ enum {
 	dma_debug_sg,
 	dma_debug_coherent,
 	dma_debug_resource,
+	dma_debug_phy,
 };
 
 enum map_err_types {
@@ -141,6 +142,7 @@ static const char *type2name[] = {
 	[dma_debug_sg] = "scatter-gather",
 	[dma_debug_coherent] = "coherent",
 	[dma_debug_resource] = "resource",
+	[dma_debug_phy] = "phy",
 };
 
 static const char *dir2name[] = {
@@ -1201,9 +1203,8 @@ void debug_dma_map_single(struct device *dev, const void *addr,
 }
 EXPORT_SYMBOL(debug_dma_map_single);
 
-void debug_dma_map_page(struct device *dev, struct page *page, size_t offset,
-			size_t size, int direction, dma_addr_t dma_addr,
-			unsigned long attrs)
+void debug_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		int direction, dma_addr_t dma_addr, unsigned long attrs)
 {
 	struct dma_debug_entry *entry;
 
@@ -1218,19 +1219,24 @@ void debug_dma_map_page(struct device *dev, struct page *page, size_t offset,
 		return;
 
 	entry->dev       = dev;
-	entry->type      = dma_debug_single;
-	entry->paddr	 = page_to_phys(page) + offset;
+	entry->type      = dma_debug_phy;
+	entry->paddr	 = phys;
 	entry->dev_addr  = dma_addr;
 	entry->size      = size;
 	entry->direction = direction;
 	entry->map_err_type = MAP_ERR_NOT_CHECKED;
 
-	check_for_stack(dev, page, offset);
+	if (!(attrs & DMA_ATTR_MMIO)) {
+		struct page *page = phys_to_page(phys);
+		size_t offset = offset_in_page(page);
 
-	if (!PageHighMem(page)) {
-		void *addr = page_address(page) + offset;
+		check_for_stack(dev, page, offset);
 
-		check_for_illegal_area(dev, addr, size);
+		if (!PageHighMem(page)) {
+			void *addr = page_address(page) + offset;
+
+			check_for_illegal_area(dev, addr, size);
+		}
 	}
 
 	add_dma_entry(entry, attrs);
@@ -1274,11 +1280,11 @@ void debug_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 }
 EXPORT_SYMBOL(debug_dma_mapping_error);
 
-void debug_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
+void debug_dma_unmap_phys(struct device *dev, dma_addr_t dma_addr,
 			  size_t size, int direction)
 {
 	struct dma_debug_entry ref = {
-		.type           = dma_debug_single,
+		.type           = dma_debug_phy,
 		.dev            = dev,
 		.dev_addr       = dma_addr,
 		.size           = size,
diff --git a/kernel/dma/debug.h b/kernel/dma/debug.h
index f525197d3cae..76adb42bffd5 100644
--- a/kernel/dma/debug.h
+++ b/kernel/dma/debug.h
@@ -9,12 +9,11 @@
 #define _KERNEL_DMA_DEBUG_H
 
 #ifdef CONFIG_DMA_API_DEBUG
-extern void debug_dma_map_page(struct device *dev, struct page *page,
-			       size_t offset, size_t size,
-			       int direction, dma_addr_t dma_addr,
+extern void debug_dma_map_phys(struct device *dev, phys_addr_t phys,
+			       size_t size, int direction, dma_addr_t dma_addr,
 			       unsigned long attrs);
 
-extern void debug_dma_unmap_page(struct device *dev, dma_addr_t addr,
+extern void debug_dma_unmap_phys(struct device *dev, dma_addr_t addr,
 				 size_t size, int direction);
 
 extern void debug_dma_map_sg(struct device *dev, struct scatterlist *sg,
@@ -55,14 +54,13 @@ extern void debug_dma_sync_sg_for_device(struct device *dev,
 					 struct scatterlist *sg,
 					 int nelems, int direction);
 #else /* CONFIG_DMA_API_DEBUG */
-static inline void debug_dma_map_page(struct device *dev, struct page *page,
-				      size_t offset, size_t size,
-				      int direction, dma_addr_t dma_addr,
-				      unsigned long attrs)
+static inline void debug_dma_map_phys(struct device *dev, phys_addr_t phys,
+				      size_t size, int direction,
+				      dma_addr_t dma_addr, unsigned long attrs)
 {
 }
 
-static inline void debug_dma_unmap_page(struct device *dev, dma_addr_t addr,
+static inline void debug_dma_unmap_phys(struct device *dev, dma_addr_t addr,
 					size_t size, int direction)
 {
 }
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 107e4a4d251d..4c1dfbabb8ae 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -157,6 +157,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
+	phys_addr_t phys = page_to_phys(page) + offset;
 	dma_addr_t addr;
 
 	BUG_ON(!valid_dma_direction(dir));
@@ -165,16 +166,15 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		return DMA_MAPPING_ERROR;
 
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_map_page_direct(dev, page_to_phys(page) + offset + size))
+	    arch_dma_map_page_direct(dev, phys + size))
 		addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		addr = iommu_dma_map_page(dev, page, offset, size, dir, attrs);
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
 	kmsan_handle_dma(page, offset, size, dir);
-	trace_dma_map_page(dev, page_to_phys(page) + offset, addr, size, dir,
-			   attrs);
-	debug_dma_map_page(dev, page, offset, size, dir, addr, attrs);
+	trace_dma_map_page(dev, phys, addr, size, dir, attrs);
+	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
 	return addr;
 }
@@ -194,7 +194,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 	else
 		ops->unmap_page(dev, addr, size, dir, attrs);
 	trace_dma_unmap_page(dev, addr, size, dir, attrs);
-	debug_dma_unmap_page(dev, addr, size, dir);
+	debug_dma_unmap_phys(dev, addr, size, dir);
 }
 EXPORT_SYMBOL(dma_unmap_page_attrs);
 
@@ -712,7 +712,8 @@ struct page *dma_alloc_pages(struct device *dev, size_t size,
 	if (page) {
 		trace_dma_alloc_pages(dev, page_to_virt(page), *dma_handle,
 				      size, dir, gfp, 0);
-		debug_dma_map_page(dev, page, 0, size, dir, *dma_handle, 0);
+		debug_dma_map_phys(dev, page_to_phys(page), size, dir,
+				   *dma_handle, 0);
 	} else {
 		trace_dma_alloc_pages(dev, NULL, 0, size, dir, gfp, 0);
 	}
@@ -738,7 +739,7 @@ void dma_free_pages(struct device *dev, size_t size, struct page *page,
 		dma_addr_t dma_handle, enum dma_data_direction dir)
 {
 	trace_dma_free_pages(dev, page_to_virt(page), dma_handle, size, dir, 0);
-	debug_dma_unmap_page(dev, dma_handle, size, dir);
+	debug_dma_unmap_phys(dev, dma_handle, size, dir);
 	__dma_free_pages(dev, size, page, dma_handle, dir);
 }
 EXPORT_SYMBOL_GPL(dma_free_pages);
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 08/16] kmsan: convert kmsan_handle_dma to use physical addresses
Date: Thu, 14 Aug 2025 13:13:26 +0300
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From: Leon Romanovsky 

Convert the KMSAN DMA handling function from page-based to physical
address-based interface.

The refactoring renames kmsan_handle_dma() parameters from accepting
(struct page *page, size_t offset, size_t size) to (phys_addr_t phys,
size_t size). A PFN_VALID check is added to prevent KMSAN operations
on non-page memory, preventing from non struct page backed address,

As part of this change, support for highmem addresses is implemented
using kmap_local_page() to handle both lowmem and highmem regions
properly. All callers throughout the codebase are updated to use the
new phys_addr_t based interface.

Signed-off-by: Leon Romanovsky 
---
 drivers/virtio/virtio_ring.c |  4 ++--
 include/linux/kmsan.h        | 12 +++++++-----
 kernel/dma/mapping.c         |  2 +-
 mm/kmsan/hooks.c             | 36 +++++++++++++++++++++++++++++-------
 tools/virtio/linux/kmsan.h   |  2 +-
 5 files changed, 40 insertions(+), 16 deletions(-)

diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index f5062061c408..c147145a6593 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -378,7 +378,7 @@ static int vring_map_one_sg(const struct vring_virtqueue *vq, struct scatterlist
 		 * is initialized by the hardware. Explicitly check/unpoison it
 		 * depending on the direction.
 		 */
-		kmsan_handle_dma(sg_page(sg), sg->offset, sg->length, direction);
+		kmsan_handle_dma(sg_phys(sg), sg->length, direction);
 		*addr = (dma_addr_t)sg_phys(sg);
 		return 0;
 	}
@@ -3157,7 +3157,7 @@ dma_addr_t virtqueue_dma_map_single_attrs(struct virtqueue *_vq, void *ptr,
 	struct vring_virtqueue *vq = to_vvq(_vq);
 
 	if (!vq->use_dma_api) {
-		kmsan_handle_dma(virt_to_page(ptr), offset_in_page(ptr), size, dir);
+		kmsan_handle_dma(virt_to_phys(ptr), size, dir);
 		return (dma_addr_t)virt_to_phys(ptr);
 	}
 
diff --git a/include/linux/kmsan.h b/include/linux/kmsan.h
index 2b1432cc16d5..6f27b9824ef7 100644
--- a/include/linux/kmsan.h
+++ b/include/linux/kmsan.h
@@ -182,8 +182,7 @@ void kmsan_iounmap_page_range(unsigned long start, unsigned long end);
 
 /**
  * kmsan_handle_dma() - Handle a DMA data transfer.
- * @page:   first page of the buffer.
- * @offset: offset of the buffer within the first page.
+ * @phys:   physical address of the buffer.
  * @size:   buffer size.
  * @dir:    one of possible dma_data_direction values.
  *
@@ -191,8 +190,11 @@ void kmsan_iounmap_page_range(unsigned long start, unsigned long end);
  * * checks the buffer, if it is copied to device;
  * * initializes the buffer, if it is copied from device;
  * * does both, if this is a DMA_BIDIRECTIONAL transfer.
+ *
+ * The function handles page lookup internally and supports both lowmem
+ * and highmem addresses.
  */
-void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
+void kmsan_handle_dma(phys_addr_t phys, size_t size,
 		      enum dma_data_direction dir);
 
 /**
@@ -372,8 +374,8 @@ static inline void kmsan_iounmap_page_range(unsigned long start,
 {
 }
 
-static inline void kmsan_handle_dma(struct page *page, size_t offset,
-				    size_t size, enum dma_data_direction dir)
+static inline void kmsan_handle_dma(phys_addr_t phys, size_t size,
+				    enum dma_data_direction dir)
 {
 }
 
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 80481a873340..709405d46b2b 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -172,7 +172,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
-	kmsan_handle_dma(page, offset, size, dir);
+	kmsan_handle_dma(phys, size, dir);
 	trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
 	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
diff --git a/mm/kmsan/hooks.c b/mm/kmsan/hooks.c
index 97de3d6194f0..eab7912a3bf0 100644
--- a/mm/kmsan/hooks.c
+++ b/mm/kmsan/hooks.c
@@ -336,25 +336,48 @@ static void kmsan_handle_dma_page(const void *addr, size_t size,
 }
 
 /* Helper function to handle DMA data transfers. */
-void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
+void kmsan_handle_dma(phys_addr_t phys, size_t size,
 		      enum dma_data_direction dir)
 {
 	u64 page_offset, to_go, addr;
+	struct page *page;
+	void *kaddr;
 
-	if (PageHighMem(page))
+	if (!pfn_valid(PHYS_PFN(phys)))
 		return;
-	addr = (u64)page_address(page) + offset;
+
+	page = phys_to_page(phys);
+	page_offset = offset_in_page(phys);
+
 	/*
 	 * The kernel may occasionally give us adjacent DMA pages not belonging
 	 * to the same allocation. Process them separately to avoid triggering
 	 * internal KMSAN checks.
 	 */
 	while (size > 0) {
-		page_offset = offset_in_page(addr);
 		to_go = min(PAGE_SIZE - page_offset, (u64)size);
+
+		if (PageHighMem(page))
+			/* Handle highmem pages using kmap */
+			kaddr = kmap_local_page(page);
+		else
+			/* Lowmem pages can be accessed directly */
+			kaddr = page_address(page);
+
+		addr = (u64)kaddr + page_offset;
 		kmsan_handle_dma_page((void *)addr, to_go, dir);
-		addr += to_go;
+
+		if (PageHighMem(page))
+			kunmap_local(page);
+
+		phys += to_go;
 		size -= to_go;
+
+		/* Move to next page if needed */
+		if (size > 0) {
+			page = phys_to_page(phys);
+			page_offset = offset_in_page(phys);
+		}
 	}
 }
 EXPORT_SYMBOL_GPL(kmsan_handle_dma);
@@ -366,8 +389,7 @@ void kmsan_handle_dma_sg(struct scatterlist *sg, int nents,
 	int i;
 
 	for_each_sg(sg, item, nents, i)
-		kmsan_handle_dma(sg_page(item), item->offset, item->length,
-				 dir);
+		kmsan_handle_dma(sg_phys(item), item->length, dir);
 }
 
 /* Functions from kmsan-checks.h follow. */
diff --git a/tools/virtio/linux/kmsan.h b/tools/virtio/linux/kmsan.h
index 272b5aa285d5..6cd2e3efd03d 100644
--- a/tools/virtio/linux/kmsan.h
+++ b/tools/virtio/linux/kmsan.h
@@ -4,7 +4,7 @@
 
 #include 
 
-inline void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
+inline void kmsan_handle_dma(phys_addr_t phys, size_t size,
 			     enum dma_data_direction dir)
 {
 }
-- 
2.50.1



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Date: Thu, 14 Aug 2025 11:17:57 +0100
MIME-Version: 1.0
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Subject: Re: [PATCH 10/22] x86/traps: Move subarch_percpu_traps_init() into
 traps-setup.c
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-11-andrew.cooper3@citrix.com>
 <646c538a-850a-4370-8132-c06d9be8b422@citrix.com>
 <769ba73f-b490-43db-a056-fc1d95ec9f27@suse.com>
 <3ff00f71-b16e-4426-98f5-27bc6f6b92cf@citrix.com>
 
Content-Language: en-GB
From: Andrew Cooper 
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In-Reply-To: 
Content-Type: text/plain; charset=UTF-8
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On 14/08/2025 9:58 am, Jan Beulich wrote:
> On 13.08.2025 13:53, Andrew Cooper wrote:
>> On 12/08/2025 10:52 am, Jan Beulich wrote:
>>> On 11.08.2025 10:17, Andrew Cooper wrote:
>>>> On 08/08/2025 9:23 pm, Andrew Cooper wrote:
>>>>> ... along with the supporting functions.  Switch to Xen coding style, and make
>>>>> static as there are no external callers.
>>>>>
>>>>> Rename to legacy_syscall_init() as a more accurate name.
>>>>>
>>>>> No functional change.
>>>>>
>>>>> Signed-off-by: Andrew Cooper 
>>>>> ---
>>>>> CC: Jan Beulich 
>>>>> CC: Roger Pau Monné 
>>>>> ---
>>>>>  xen/arch/x86/include/asm/system.h |  2 -
>>>>>  xen/arch/x86/traps-setup.c        | 97 ++++++++++++++++++++++++++++++-
>>>>>  xen/arch/x86/x86_64/traps.c       | 92 -----------------------------
>>>>>  3 files changed, 95 insertions(+), 96 deletions(-)
>>>>>
>>>>> diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
>>>>> index 3cdc56e4ba6d..6c2800d8158d 100644
>>>>> --- a/xen/arch/x86/include/asm/system.h
>>>>> +++ b/xen/arch/x86/include/asm/system.h
>>>>> @@ -256,6 +256,4 @@ static inline int local_irq_is_enabled(void)
>>>>>  #define BROKEN_ACPI_Sx          0x0001
>>>>>  #define BROKEN_INIT_AFTER_S1    0x0002
>>>>>  
>>>>> -void subarch_percpu_traps_init(void);
>>>>> -
>>>>>  #endif
>>>>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>>>>> index 13b8fcf0ba51..fbae7072c292 100644
>>>>> --- a/xen/arch/x86/traps-setup.c
>>>>> +++ b/xen/arch/x86/traps-setup.c
>>>>> @@ -2,13 +2,15 @@
>>>>>  /*
>>>>>   * Configuration of event handling for all CPUs.
>>>>>   */
>>>>> +#include 
>>>>>  #include 
>>>>>  #include 
>>>>>  
>>>>> +#include 
>>>>>  #include 
>>>>>  #include 
>>>>>  #include 
>>>>> -#include 
>>>>> +#include 
>>>>>  #include 
>>>>>  
>>>>>  DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt);
>>>>> @@ -19,6 +21,8 @@ static bool __initdata opt_ler;
>>>>>  boolean_param("ler", opt_ler);
>>>>>  
>>>>>  void nocall entry_PF(void);
>>>>> +void nocall lstar_enter(void);
>>>>> +void nocall cstar_enter(void);
>>>>>  
>>>>>  /*
>>>>>   * Sets up system tables and descriptors for IDT devliery.
>>>>> @@ -138,6 +142,95 @@ static void load_system_tables(void)
>>>>>      BUG_ON(stack_bottom & 15);
>>>>>  }
>>>>>  
>>>>> +static unsigned int write_stub_trampoline(
>>>>> +    unsigned char *stub, unsigned long stub_va,
>>>>> +    unsigned long stack_bottom, unsigned long target_va)
>>>>> +{
>>>>> +    unsigned char *p = stub;
>>>>> +
>>>>> +    if ( cpu_has_xen_ibt )
>>>>> +    {
>>>>> +        place_endbr64(p);
>>>>> +        p += 4;
>>>>> +    }
>>>>> +
>>>>> +    /* Store guest %rax into %ss slot */
>>>>> +    /* movabsq %rax, stack_bottom - 8 */
>>>>> +    *p++ = 0x48;
>>>>> +    *p++ = 0xa3;
>>>>> +    *(uint64_t *)p = stack_bottom - 8;
>>>>> +    p += 8;
>>>>> +
>>>>> +    /* Store guest %rsp in %rax */
>>>>> +    /* movq %rsp, %rax */
>>>>> +    *p++ = 0x48;
>>>>> +    *p++ = 0x89;
>>>>> +    *p++ = 0xe0;
>>>>> +
>>>>> +    /* Switch to Xen stack */
>>>>> +    /* movabsq $stack_bottom - 8, %rsp */
>>>>> +    *p++ = 0x48;
>>>>> +    *p++ = 0xbc;
>>>>> +    *(uint64_t *)p = stack_bottom - 8;
>>>>> +    p += 8;
>>>>> +
>>>>> +    /* jmp target_va */
>>>>> +    *p++ = 0xe9;
>>>>> +    *(int32_t *)p = target_va - (stub_va + (p - stub) + 4);
>>>>> +    p += 4;
>>>>> +
>>>>> +    /* Round up to a multiple of 16 bytes. */
>>>>> +    return ROUNDUP(p - stub, 16);
>>>>> +}
>>>>> +
>>>>> +static void legacy_syscall_init(void)
>>>>> +{
>>>>> +    unsigned long stack_bottom = get_stack_bottom();
>>>>> +    unsigned long stub_va = this_cpu(stubs.addr);
>>>>> +    unsigned char *stub_page;
>>>>> +    unsigned int offset;
>>>>> +
>>>>> +    /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
>>>>> +    if ( !IS_ENABLED(CONFIG_PV) )
>>>>> +        return;
>>>>> +
>>>>> +    stub_page = map_domain_page(_mfn(this_cpu(stubs.mfn)));
>>>>> +
>>>>> +    /*
>>>>> +     * Trampoline for SYSCALL entry from 64-bit mode.  The VT-x HVM vcpu
>>>>> +     * context switch logic relies on the SYSCALL trampoline being at the
>>>>> +     * start of the stubs.
>>>>> +     */
>>>>> +    wrmsrl(MSR_LSTAR, stub_va);
>>>>> +    offset = write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>>>> +                                   stub_va, stack_bottom,
>>>>> +                                   (unsigned long)lstar_enter);
>>>>> +    stub_va += offset;
>>>>> +
>>>>> +    if ( cpu_has_sep )
>>>>> +    {
>>>>> +        /* SYSENTER entry. */
>>>>> +        wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
>>>>> +        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
>>>>> +        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
>>>>> +    }
>>>>> +
>>>>> +    /* Trampoline for SYSCALL entry from compatibility mode. */
>>>>> +    wrmsrl(MSR_CSTAR, stub_va);
>>>>> +    offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>>>> +                                    stub_va, stack_bottom,
>>>>> +                                    (unsigned long)cstar_enter);
>>>>> +
>>>>> +    /* Don't consume more than half of the stub space here. */
>>>>> +    ASSERT(offset <= STUB_BUF_SIZE / 2);
>>>>> +
>>>>> +    unmap_domain_page(stub_page);
>>>>> +
>>>>> +    /* Common SYSCALL parameters. */
>>>>> +    wrmsrl(MSR_STAR, XEN_MSR_STAR);
>>>>> +    wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
>>>>> +}
>>>> These want adjusting to use wrmsrns(), similarly to the previous patch. 
>>>> Fixed locally.
>>> Also the one higher in the function, I suppose.
>> All of them.
>>
>> I'm not aware of anywhere were we want serialising behaviour, except for
>> ICR which is buggly non-serialising and has workarounds.
>>
>> But I'm also not sure enough of this to suggest that we make wrmsr() be
>> wrmsrns() by default.
> I'm pretty sure we don't want this. If nothing else then to avoid code bloat
> for MSR writes which are non-serializing even in the original form.

Even that's complicated.

For FRED, FS/GS_BASE/KERN need changes because the lack of SWAPGS forces
MSR accesses even if we do have FSGSBASE active.

Writes to these were made non-serialising in Zen2 and later, but are
still serialising on Intel.  i.e. they need converting to WRMSRNS even
though plain WRMSR would be "fine" on all AMD systems (either because
it's the only option, or because it's non-serialising).

~Andrew


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Date: Thu, 14 Aug 2025 11:18:38 +0100
From: Hari Limaye 
To: Ayan Kumar Halder 
Cc: xen-devel@lists.xenproject.org, 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Volodymyr Babchuk 
Subject: Re: [PATCH v2 1/2] arm/mpu: Enable is_xen_heap_page and
 is_xen_heap_mfn for ARM_32
Message-ID: 
References: <20250814081959.3504145-1-ayan.kumar.halder@amd.com>
 <20250814081959.3504145-2-ayan.kumar.halder@amd.com>
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Hi Ayan,

On Thu, Aug 14, 2025 at 09:19:58AM +0000, Ayan Kumar Halder wrote:
> In case of ARM_32, all of the RAM will be covered by a permanent contiguous
> mapping (where VA == PA) and there will be a single heap. Thus, the memory
> allocated from Xen heap uses PGC_xen_heap.
> This is similar to the scenario described for
> "CONFIG_SEPARATE_XENHEAP=n W/ DIRECT MAP OF ALL RAM" in common/page_alloc.c.
> 
> Signed-off-by: Ayan Kumar Halder 
Reviewed-by: Hari Limaye 
Tested-by: Hari Limaye 

LGTM now, thanks for updating. Tested (build-only) on AArch32 and
AArch64 MMU and MPU systems.

Cheers,
Hari


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	Christoph Hellwig ,
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Subject: [PATCH v2 09/16] dma-mapping: handle MMIO flow in dma_map|unmap_page
Date: Thu, 14 Aug 2025 13:13:27 +0300
Message-ID: <7b8c8f88f61c85d60e24f04e88d42357b898ccbc.1755153054.git.leon@kernel.org>
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From: Leon Romanovsky 

Extend base DMA page API to handle MMIO flow and follow
existing dma_map_resource() implementation to rely on dma_map_direct()
only to take DMA direct path.

Signed-off-by: Leon Romanovsky 
---
 kernel/dma/mapping.c | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 709405d46b2b..8725508a6c57 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -158,6 +158,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
 	phys_addr_t phys = page_to_phys(page) + offset;
+	bool is_mmio = attrs & DMA_ATTR_MMIO;
 	dma_addr_t addr;
 
 	BUG_ON(!valid_dma_direction(dir));
@@ -166,12 +167,23 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		return DMA_MAPPING_ERROR;
 
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_map_phys_direct(dev, phys + size))
+	    (!is_mmio && arch_dma_map_phys_direct(dev, phys + size)))
 		addr = dma_direct_map_phys(dev, phys, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
-	else
+	else if (is_mmio) {
+		if (!ops->map_resource)
+			return DMA_MAPPING_ERROR;
+
+		addr = ops->map_resource(dev, phys, size, dir, attrs);
+	} else {
+		/*
+		 * The dma_ops API contract for ops->map_page() requires
+		 * kmappable memory, while ops->map_resource() does not.
+		 */
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
+	}
+
 	kmsan_handle_dma(phys, size, dir);
 	trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
 	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
@@ -184,14 +196,18 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
+	bool is_mmio = attrs & DMA_ATTR_MMIO;
 
 	BUG_ON(!valid_dma_direction(dir));
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_unmap_phys_direct(dev, addr + size))
+	    (!is_mmio && arch_dma_unmap_phys_direct(dev, addr + size)))
 		dma_direct_unmap_phys(dev, addr, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
-	else
+	else if (is_mmio) {
+		if (ops->unmap_resource)
+			ops->unmap_resource(dev, addr, size, dir, attrs);
+	} else
 		ops->unmap_page(dev, addr, size, dir, attrs);
 	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
 	debug_dma_unmap_phys(dev, addr, size, dir);
-- 
2.50.1



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	Alexander Potapenko ,
	Alex Gaynor ,
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	Christoph Hellwig ,
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Subject: [PATCH v2 16/16] nvme-pci: unmap MMIO pages with appropriate interface
Date: Thu, 14 Aug 2025 13:13:34 +0300
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From: Leon Romanovsky 

Block layer maps MMIO memory through dma_map_phys() interface
with help of DMA_ATTR_MMIO attribute. There is a need to unmap
that memory with the appropriate unmap function, something which
wasn't possible before adding new REQ attribute to block layer in
previous patch.

Signed-off-by: Leon Romanovsky 
---
 drivers/nvme/host/pci.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 2c6d9506b172..f8ecc0e0f576 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -682,11 +682,15 @@ static void nvme_free_prps(struct request *req)
 {
 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
+	unsigned int attrs = 0;
 	unsigned int i;
 
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
+
 	for (i = 0; i < iod->nr_dma_vecs; i++)
-		dma_unmap_page(nvmeq->dev->dev, iod->dma_vecs[i].addr,
-				iod->dma_vecs[i].len, rq_dma_dir(req));
+		dma_unmap_phys(nvmeq->dev->dev, iod->dma_vecs[i].addr,
+				iod->dma_vecs[i].len, rq_dma_dir(req), attrs);
 	mempool_free(iod->dma_vecs, nvmeq->dev->dmavec_mempool);
 }
 
@@ -699,15 +703,19 @@ static void nvme_free_sgls(struct request *req)
 	unsigned int sqe_dma_len = le32_to_cpu(iod->cmd.common.dptr.sgl.length);
 	struct nvme_sgl_desc *sg_list = iod->descriptors[0];
 	enum dma_data_direction dir = rq_dma_dir(req);
+	unsigned int attrs = 0;
+
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
 
 	if (iod->nr_descriptors) {
 		unsigned int nr_entries = sqe_dma_len / sizeof(*sg_list), i;
 
 		for (i = 0; i < nr_entries; i++)
-			dma_unmap_page(dma_dev, le64_to_cpu(sg_list[i].addr),
-				le32_to_cpu(sg_list[i].length), dir);
+			dma_unmap_phys(dma_dev, le64_to_cpu(sg_list[i].addr),
+				le32_to_cpu(sg_list[i].length), dir, attrs);
 	} else {
-		dma_unmap_page(dma_dev, sqe_dma_addr, sqe_dma_len, dir);
+		dma_unmap_phys(dma_dev, sqe_dma_addr, sqe_dma_len, dir, attrs);
 	}
 }
 
-- 
2.50.1



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	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
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Subject: [PATCH v2 10/16] xen: swiotlb: Open code map_resource callback
Date: Thu, 14 Aug 2025 13:13:28 +0300
Message-ID: <972e4cd98b0d3683e02d06b7a35a2c1d76a226e4.1755153054.git.leon@kernel.org>
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From: Leon Romanovsky 

General dma_direct_map_resource() is going to be removed
in next patch, so simply open-code it in xen driver.

Reviewed-by: Juergen Gross 
Signed-off-by: Leon Romanovsky 
---
 drivers/xen/swiotlb-xen.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c
index da1a7d3d377c..dd7747a2de87 100644
--- a/drivers/xen/swiotlb-xen.c
+++ b/drivers/xen/swiotlb-xen.c
@@ -392,6 +392,25 @@ xen_swiotlb_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
 	}
 }
 
+static dma_addr_t xen_swiotlb_direct_map_resource(struct device *dev,
+						  phys_addr_t paddr,
+						  size_t size,
+						  enum dma_data_direction dir,
+						  unsigned long attrs)
+{
+	dma_addr_t dma_addr = paddr;
+
+	if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
+		dev_err_once(dev,
+			     "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
+			     &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
+		WARN_ON_ONCE(1);
+		return DMA_MAPPING_ERROR;
+	}
+
+	return dma_addr;
+}
+
 /*
  * Return whether the given device DMA address mask can be supported
  * properly.  For example, if your device can only drive the low 24-bits
@@ -426,5 +445,5 @@ const struct dma_map_ops xen_swiotlb_dma_ops = {
 	.alloc_pages_op = dma_common_alloc_pages,
 	.free_pages = dma_common_free_pages,
 	.max_mapping_size = swiotlb_max_mapping_size,
-	.map_resource = dma_direct_map_resource,
+	.map_resource = xen_swiotlb_direct_map_resource,
 };
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
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	xen-devel@lists.xenproject.org
Subject: [PATCH v2 15/16] block-dma: properly take MMIO path
Date: Thu, 14 Aug 2025 13:13:33 +0300
Message-ID: <87b7d3a0e3f6be9da49947923d52355ed0835833.1755153054.git.leon@kernel.org>
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From: Leon Romanovsky 

Make sure that CPU is not synced and IOMMU is configured to take
MMIO path by providing newly introduced DMA_ATTR_MMIO attribute.

Signed-off-by: Leon Romanovsky 
---
 block/blk-mq-dma.c         | 13 +++++++++++--
 include/linux/blk-mq-dma.h |  6 +++++-
 include/linux/blk_types.h  |  2 ++
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/block/blk-mq-dma.c b/block/blk-mq-dma.c
index 37e2142be4f7..d415088ed9fd 100644
--- a/block/blk-mq-dma.c
+++ b/block/blk-mq-dma.c
@@ -87,8 +87,13 @@ static bool blk_dma_map_bus(struct blk_dma_iter *iter, struct phys_vec *vec)
 static bool blk_dma_map_direct(struct request *req, struct device *dma_dev,
 		struct blk_dma_iter *iter, struct phys_vec *vec)
 {
+	unsigned int attrs = 0;
+
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
+
 	iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len,
-			rq_dma_dir(req), 0);
+			rq_dma_dir(req), attrs);
 	if (dma_mapping_error(dma_dev, iter->addr)) {
 		iter->status = BLK_STS_RESOURCE;
 		return false;
@@ -103,14 +108,17 @@ static bool blk_rq_dma_map_iova(struct request *req, struct device *dma_dev,
 {
 	enum dma_data_direction dir = rq_dma_dir(req);
 	unsigned int mapped = 0;
+	unsigned int attrs = 0;
 	int error;
 
 	iter->addr = state->addr;
 	iter->len = dma_iova_size(state);
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
 
 	do {
 		error = dma_iova_link(dma_dev, state, vec->paddr, mapped,
-				vec->len, dir, 0);
+				vec->len, dir, attrs);
 		if (error)
 			break;
 		mapped += vec->len;
@@ -176,6 +184,7 @@ bool blk_rq_dma_map_iter_start(struct request *req, struct device *dma_dev,
 			 * same as non-P2P transfers below and during unmap.
 			 */
 			req->cmd_flags &= ~REQ_P2PDMA;
+			req->cmd_flags |= REQ_MMIO;
 			break;
 		default:
 			iter->status = BLK_STS_INVAL;
diff --git a/include/linux/blk-mq-dma.h b/include/linux/blk-mq-dma.h
index c26a01aeae00..6c55f5e58511 100644
--- a/include/linux/blk-mq-dma.h
+++ b/include/linux/blk-mq-dma.h
@@ -48,12 +48,16 @@ static inline bool blk_rq_dma_map_coalesce(struct dma_iova_state *state)
 static inline bool blk_rq_dma_unmap(struct request *req, struct device *dma_dev,
 		struct dma_iova_state *state, size_t mapped_len)
 {
+	unsigned int attrs = 0;
+
 	if (req->cmd_flags & REQ_P2PDMA)
 		return true;
 
 	if (dma_use_iova(state)) {
+		if (req->cmd_flags & REQ_MMIO)
+			attrs = DMA_ATTR_MMIO;
 		dma_iova_destroy(dma_dev, state, mapped_len, rq_dma_dir(req),
-				 0);
+				 attrs);
 		return true;
 	}
 
diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
index 09b99d52fd36..283058bcb5b1 100644
--- a/include/linux/blk_types.h
+++ b/include/linux/blk_types.h
@@ -387,6 +387,7 @@ enum req_flag_bits {
 	__REQ_FS_PRIVATE,	/* for file system (submitter) use */
 	__REQ_ATOMIC,		/* for atomic write operations */
 	__REQ_P2PDMA,		/* contains P2P DMA pages */
+	__REQ_MMIO,		/* contains MMIO memory */
 	/*
 	 * Command specific flags, keep last:
 	 */
@@ -420,6 +421,7 @@ enum req_flag_bits {
 #define REQ_FS_PRIVATE	(__force blk_opf_t)(1ULL << __REQ_FS_PRIVATE)
 #define REQ_ATOMIC	(__force blk_opf_t)(1ULL << __REQ_ATOMIC)
 #define REQ_P2PDMA	(__force blk_opf_t)(1ULL << __REQ_P2PDMA)
+#define REQ_MMIO	(__force blk_opf_t)(1ULL << __REQ_MMIO)
 
 #define REQ_NOUNMAP	(__force blk_opf_t)(1ULL << __REQ_NOUNMAP)
 
-- 
2.50.1



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Date: Thu, 14 Aug 2025 11:22:45 +0100
From: Hari Limaye 
To: Ayan Kumar Halder 
Cc: xen-devel@lists.xenproject.org, 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Volodymyr Babchuk 
Subject: Re: [PATCH v2 2/2] arm/mpu: Disable map_domain_page for MPU
Message-ID: 
References: <20250814081959.3504145-1-ayan.kumar.halder@amd.com>
 <20250814081959.3504145-3-ayan.kumar.halder@amd.com>
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In-Reply-To: <20250814081959.3504145-3-ayan.kumar.halder@amd.com>

Hi Ayan,

> On Thu, Aug 14, 2025 at 09:19:59AM +0000, Ayan Kumar Halder wrote:
> There is no domheap for ARM_32. All of the RAM is mapped and VA == PA.
> 
> Signed-off-by: Ayan Kumar Halder 
> ---
> Changes from :-
> 
> v1 - 1. No changes.
> 
Slightly surprised by this, as it looks like the suggested change from
https://patchwork.kernel.org/comment/26507841/ has been incorporated in
this v2 version of the patch...

But anyway, LGTM now!

Reviewed-by: Hari Limaye 
Tested-by: Hari Limaye 

Cheers,
Hari


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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 14/16] block-dma: migrate to dma_map_phys instead of map_page
Date: Thu, 14 Aug 2025 13:13:32 +0300
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From: Leon Romanovsky 

After introduction of dma_map_phys(), there is no need to convert
from physical address to struct page in order to map page. So let's
use it directly.

Signed-off-by: Leon Romanovsky 
---
 block/blk-mq-dma.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/block/blk-mq-dma.c b/block/blk-mq-dma.c
index ad283017caef..37e2142be4f7 100644
--- a/block/blk-mq-dma.c
+++ b/block/blk-mq-dma.c
@@ -87,8 +87,8 @@ static bool blk_dma_map_bus(struct blk_dma_iter *iter, struct phys_vec *vec)
 static bool blk_dma_map_direct(struct request *req, struct device *dma_dev,
 		struct blk_dma_iter *iter, struct phys_vec *vec)
 {
-	iter->addr = dma_map_page(dma_dev, phys_to_page(vec->paddr),
-			offset_in_page(vec->paddr), vec->len, rq_dma_dir(req));
+	iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len,
+			rq_dma_dir(req), 0);
 	if (dma_mapping_error(dma_dev, iter->addr)) {
 		iter->status = BLK_STS_RESOURCE;
 		return false;
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 11/16] dma-mapping: export new dma_*map_phys() interface
Date: Thu, 14 Aug 2025 13:13:29 +0300
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From: Leon Romanovsky 

Introduce new DMA mapping functions dma_map_phys() and dma_unmap_phys()
that operate directly on physical addresses instead of page+offset
parameters. This provides a more efficient interface for drivers that
already have physical addresses available.

The new functions are implemented as the primary mapping layer, with
the existing dma_map_page_attrs()/dma_map_resource() and
dma_unmap_page_attrs()/dma_unmap_resource() functions converted to simple
wrappers around the phys-based implementations.

In case dma_map_page_attrs(), the struct page is converted to physical
address with help of page_to_phys() function and dma_map_resource()
provides physical address as is together with addition of DMA_ATTR_MMIO
attribute.

The old page-based API is preserved in mapping.c to ensure that existing
code won't be affected by changing EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
variant for dma_*map_phys().

Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c   | 14 --------
 include/linux/dma-direct.h  |  2 --
 include/linux/dma-mapping.h | 13 +++++++
 include/linux/iommu-dma.h   |  4 ---
 include/trace/events/dma.h  |  2 --
 kernel/dma/debug.c          | 43 -----------------------
 kernel/dma/debug.h          | 21 -----------
 kernel/dma/direct.c         | 16 ---------
 kernel/dma/mapping.c        | 69 ++++++++++++++++++++-----------------
 9 files changed, 50 insertions(+), 134 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 6804aaf034a1..7944a3af4545 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -1556,20 +1556,6 @@ void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
 		__iommu_dma_unmap(dev, start, end - start);
 }
 
-dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
-		size_t size, enum dma_data_direction dir, unsigned long attrs)
-{
-	return __iommu_dma_map(dev, phys, size,
-			dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO,
-			dma_get_mask(dev));
-}
-
-void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
-		size_t size, enum dma_data_direction dir, unsigned long attrs)
-{
-	__iommu_dma_unmap(dev, handle, size);
-}
-
 static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr)
 {
 	size_t alloc_size = PAGE_ALIGN(size);
diff --git a/include/linux/dma-direct.h b/include/linux/dma-direct.h
index f3bc0bcd7098..c249912456f9 100644
--- a/include/linux/dma-direct.h
+++ b/include/linux/dma-direct.h
@@ -149,7 +149,5 @@ void dma_direct_free_pages(struct device *dev, size_t size,
 		struct page *page, dma_addr_t dma_addr,
 		enum dma_data_direction dir);
 int dma_direct_supported(struct device *dev, u64 mask);
-dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
-		size_t size, enum dma_data_direction dir, unsigned long attrs);
 
 #endif /* _LINUX_DMA_DIRECT_H */
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index ead5514d389e..cebfbe237595 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -138,6 +138,10 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		unsigned long attrs);
 void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs);
+dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs);
+void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size,
+		enum dma_data_direction dir, unsigned long attrs);
 unsigned int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
 		int nents, enum dma_data_direction dir, unsigned long attrs);
 void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg,
@@ -192,6 +196,15 @@ static inline void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
 }
+static inline dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys,
+		size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+	return DMA_MAPPING_ERROR;
+}
+static inline void dma_unmap_phys(struct device *dev, dma_addr_t addr,
+		size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+}
 static inline unsigned int dma_map_sg_attrs(struct device *dev,
 		struct scatterlist *sg, int nents, enum dma_data_direction dir,
 		unsigned long attrs)
diff --git a/include/linux/iommu-dma.h b/include/linux/iommu-dma.h
index 485bdffed988..a92b3ff9b934 100644
--- a/include/linux/iommu-dma.h
+++ b/include/linux/iommu-dma.h
@@ -42,10 +42,6 @@ size_t iommu_dma_opt_mapping_size(void);
 size_t iommu_dma_max_mapping_size(struct device *dev);
 void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr,
 		dma_addr_t handle, unsigned long attrs);
-dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
-		size_t size, enum dma_data_direction dir, unsigned long attrs);
-void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
-		size_t size, enum dma_data_direction dir, unsigned long attrs);
 struct sg_table *iommu_dma_alloc_noncontiguous(struct device *dev, size_t size,
 		enum dma_data_direction dir, gfp_t gfp, unsigned long attrs);
 void iommu_dma_free_noncontiguous(struct device *dev, size_t size,
diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h
index 84416c7d6bfa..5da59fd8121d 100644
--- a/include/trace/events/dma.h
+++ b/include/trace/events/dma.h
@@ -73,7 +73,6 @@ DEFINE_EVENT(dma_map, name, \
 	TP_ARGS(dev, phys_addr, dma_addr, size, dir, attrs))
 
 DEFINE_MAP_EVENT(dma_map_phys);
-DEFINE_MAP_EVENT(dma_map_resource);
 
 DECLARE_EVENT_CLASS(dma_unmap,
 	TP_PROTO(struct device *dev, dma_addr_t addr, size_t size,
@@ -111,7 +110,6 @@ DEFINE_EVENT(dma_unmap, name, \
 	TP_ARGS(dev, addr, size, dir, attrs))
 
 DEFINE_UNMAP_EVENT(dma_unmap_phys);
-DEFINE_UNMAP_EVENT(dma_unmap_resource);
 
 DECLARE_EVENT_CLASS(dma_alloc_class,
 	TP_PROTO(struct device *dev, void *virt_addr, dma_addr_t dma_addr,
diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c
index da6734e3a4ce..06e31fd216e3 100644
--- a/kernel/dma/debug.c
+++ b/kernel/dma/debug.c
@@ -38,7 +38,6 @@ enum {
 	dma_debug_single,
 	dma_debug_sg,
 	dma_debug_coherent,
-	dma_debug_resource,
 	dma_debug_phy,
 };
 
@@ -141,7 +140,6 @@ static const char *type2name[] = {
 	[dma_debug_single] = "single",
 	[dma_debug_sg] = "scatter-gather",
 	[dma_debug_coherent] = "coherent",
-	[dma_debug_resource] = "resource",
 	[dma_debug_phy] = "phy",
 };
 
@@ -1448,47 +1446,6 @@ void debug_dma_free_coherent(struct device *dev, size_t size,
 	check_unmap(&ref);
 }
 
-void debug_dma_map_resource(struct device *dev, phys_addr_t addr, size_t size,
-			    int direction, dma_addr_t dma_addr,
-			    unsigned long attrs)
-{
-	struct dma_debug_entry *entry;
-
-	if (unlikely(dma_debug_disabled()))
-		return;
-
-	entry = dma_entry_alloc();
-	if (!entry)
-		return;
-
-	entry->type		= dma_debug_resource;
-	entry->dev		= dev;
-	entry->paddr		= addr;
-	entry->size		= size;
-	entry->dev_addr		= dma_addr;
-	entry->direction	= direction;
-	entry->map_err_type	= MAP_ERR_NOT_CHECKED;
-
-	add_dma_entry(entry, attrs);
-}
-
-void debug_dma_unmap_resource(struct device *dev, dma_addr_t dma_addr,
-			      size_t size, int direction)
-{
-	struct dma_debug_entry ref = {
-		.type           = dma_debug_resource,
-		.dev            = dev,
-		.dev_addr       = dma_addr,
-		.size           = size,
-		.direction      = direction,
-	};
-
-	if (unlikely(dma_debug_disabled()))
-		return;
-
-	check_unmap(&ref);
-}
-
 void debug_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 				   size_t size, int direction)
 {
diff --git a/kernel/dma/debug.h b/kernel/dma/debug.h
index 76adb42bffd5..424b8f912ade 100644
--- a/kernel/dma/debug.h
+++ b/kernel/dma/debug.h
@@ -30,14 +30,6 @@ extern void debug_dma_alloc_coherent(struct device *dev, size_t size,
 extern void debug_dma_free_coherent(struct device *dev, size_t size,
 				    void *virt, dma_addr_t addr);
 
-extern void debug_dma_map_resource(struct device *dev, phys_addr_t addr,
-				   size_t size, int direction,
-				   dma_addr_t dma_addr,
-				   unsigned long attrs);
-
-extern void debug_dma_unmap_resource(struct device *dev, dma_addr_t dma_addr,
-				     size_t size, int direction);
-
 extern void debug_dma_sync_single_for_cpu(struct device *dev,
 					  dma_addr_t dma_handle, size_t size,
 					  int direction);
@@ -88,19 +80,6 @@ static inline void debug_dma_free_coherent(struct device *dev, size_t size,
 {
 }
 
-static inline void debug_dma_map_resource(struct device *dev, phys_addr_t addr,
-					  size_t size, int direction,
-					  dma_addr_t dma_addr,
-					  unsigned long attrs)
-{
-}
-
-static inline void debug_dma_unmap_resource(struct device *dev,
-					    dma_addr_t dma_addr, size_t size,
-					    int direction)
-{
-}
-
 static inline void debug_dma_sync_single_for_cpu(struct device *dev,
 						 dma_addr_t dma_handle,
 						 size_t size, int direction)
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index fa75e3070073..1062caac47e7 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -502,22 +502,6 @@ int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
 	return ret;
 }
 
-dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
-		size_t size, enum dma_data_direction dir, unsigned long attrs)
-{
-	dma_addr_t dma_addr = paddr;
-
-	if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
-		dev_err_once(dev,
-			     "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
-			     &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
-		WARN_ON_ONCE(1);
-		return DMA_MAPPING_ERROR;
-	}
-
-	return dma_addr;
-}
-
 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
 		void *cpu_addr, dma_addr_t dma_addr, size_t size,
 		unsigned long attrs)
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 8725508a6c57..7e0e21a7ba04 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -152,12 +152,10 @@ static inline bool dma_map_direct(struct device *dev,
 	return dma_go_direct(dev, *dev->dma_mask, ops);
 }
 
-dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
-		size_t offset, size_t size, enum dma_data_direction dir,
-		unsigned long attrs)
+dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
-	phys_addr_t phys = page_to_phys(page) + offset;
 	bool is_mmio = attrs & DMA_ATTR_MMIO;
 	dma_addr_t addr;
 
@@ -177,6 +175,9 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 
 		addr = ops->map_resource(dev, phys, size, dir, attrs);
 	} else {
+		struct page *page = phys_to_page(phys);
+		size_t offset = offset_in_page(phys);
+
 		/*
 		 * The dma_ops API contract for ops->map_page() requires
 		 * kmappable memory, while ops->map_resource() does not.
@@ -190,9 +191,26 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 
 	return addr;
 }
+EXPORT_SYMBOL_GPL(dma_map_phys);
+
+dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
+		size_t offset, size_t size, enum dma_data_direction dir,
+		unsigned long attrs)
+{
+	phys_addr_t phys = page_to_phys(page) + offset;
+
+	if (unlikely(attrs & DMA_ATTR_MMIO))
+		return DMA_MAPPING_ERROR;
+
+	if (IS_ENABLED(CONFIG_DMA_API_DEBUG) &&
+	    WARN_ON_ONCE(is_zone_device_page(page)))
+		return DMA_MAPPING_ERROR;
+
+	return dma_map_phys(dev, phys, size, dir, attrs);
+}
 EXPORT_SYMBOL(dma_map_page_attrs);
 
-void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
+void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
@@ -212,6 +230,16 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
 	debug_dma_unmap_phys(dev, addr, size, dir);
 }
+EXPORT_SYMBOL_GPL(dma_unmap_phys);
+
+void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
+		 enum dma_data_direction dir, unsigned long attrs)
+{
+	if (unlikely(attrs & DMA_ATTR_MMIO))
+		return;
+
+	dma_unmap_phys(dev, addr, size, dir, attrs);
+}
 EXPORT_SYMBOL(dma_unmap_page_attrs);
 
 static int __dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
@@ -337,41 +365,18 @@ EXPORT_SYMBOL(dma_unmap_sg_attrs);
 dma_addr_t dma_map_resource(struct device *dev, phys_addr_t phys_addr,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
-	const struct dma_map_ops *ops = get_dma_ops(dev);
-	dma_addr_t addr = DMA_MAPPING_ERROR;
-
-	BUG_ON(!valid_dma_direction(dir));
-
-	if (WARN_ON_ONCE(!dev->dma_mask))
+	if (IS_ENABLED(CONFIG_DMA_API_DEBUG) &&
+	    WARN_ON_ONCE(pfn_valid(PHYS_PFN(phys_addr))))
 		return DMA_MAPPING_ERROR;
 
-	if (dma_map_direct(dev, ops))
-		addr = dma_direct_map_resource(dev, phys_addr, size, dir, attrs);
-	else if (use_dma_iommu(dev))
-		addr = iommu_dma_map_resource(dev, phys_addr, size, dir, attrs);
-	else if (ops->map_resource)
-		addr = ops->map_resource(dev, phys_addr, size, dir, attrs);
-
-	trace_dma_map_resource(dev, phys_addr, addr, size, dir, attrs);
-	debug_dma_map_resource(dev, phys_addr, size, dir, addr, attrs);
-	return addr;
+	return dma_map_phys(dev, phys_addr, size, dir, attrs | DMA_ATTR_MMIO);
 }
 EXPORT_SYMBOL(dma_map_resource);
 
 void dma_unmap_resource(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs)
 {
-	const struct dma_map_ops *ops = get_dma_ops(dev);
-
-	BUG_ON(!valid_dma_direction(dir));
-	if (dma_map_direct(dev, ops))
-		; /* nothing to do: uncached and no swiotlb */
-	else if (use_dma_iommu(dev))
-		iommu_dma_unmap_resource(dev, addr, size, dir, attrs);
-	else if (ops->unmap_resource)
-		ops->unmap_resource(dev, addr, size, dir, attrs);
-	trace_dma_unmap_resource(dev, addr, size, dir, attrs);
-	debug_dma_unmap_resource(dev, addr, size, dir);
+	dma_unmap_phys(dev, addr, size, dir, attrs | DMA_ATTR_MMIO);
 }
 EXPORT_SYMBOL(dma_unmap_resource);
 
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
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	linux-nvme@lists.infradead.org,
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	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 12/16] mm/hmm: migrate to physical address-based DMA mapping API
Date: Thu, 14 Aug 2025 13:13:30 +0300
Message-ID: <259668e7a332148edf8738b7b4637c2b264f51ea.1755153054.git.leon@kernel.org>
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From: Leon Romanovsky 

Convert HMM DMA operations from the legacy page-based API to the new
physical address-based dma_map_phys() and dma_unmap_phys() functions.
This demonstrates the preferred approach for new code that should use
physical addresses directly rather than page+offset parameters.

The change replaces dma_map_page() and dma_unmap_page() calls with
dma_map_phys() and dma_unmap_phys() respectively, using the physical
address that was already available in the code. This eliminates the
redundant page-to-physical address conversion and aligns with the
DMA subsystem's move toward physical address-centric interfaces.

This serves as an example of how new code should be written to leverage
the more efficient physical address API, which provides cleaner interfaces
for drivers that already have access to physical addresses.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 mm/hmm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index d545e2494994..015ab243f081 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -775,8 +775,8 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
 		if (WARN_ON_ONCE(dma_need_unmap(dev) && !dma_addrs))
 			goto error;
 
-		dma_addr = dma_map_page(dev, page, 0, map->dma_entry_size,
-					DMA_BIDIRECTIONAL);
+		dma_addr = dma_map_phys(dev, paddr, map->dma_entry_size,
+					DMA_BIDIRECTIONAL, 0);
 		if (dma_mapping_error(dev, dma_addr))
 			goto error;
 
@@ -819,8 +819,8 @@ bool hmm_dma_unmap_pfn(struct device *dev, struct hmm_dma_map *map, size_t idx)
 		dma_iova_unlink(dev, state, idx * map->dma_entry_size,
 				map->dma_entry_size, DMA_BIDIRECTIONAL, attrs);
 	} else if (dma_need_unmap(dev))
-		dma_unmap_page(dev, dma_addrs[idx], map->dma_entry_size,
-			       DMA_BIDIRECTIONAL);
+		dma_unmap_phys(dev, dma_addrs[idx], map->dma_entry_size,
+			       DMA_BIDIRECTIONAL, 0);
 
 	pfns[idx] &=
 		~(HMM_PFN_DMA_MAPPED | HMM_PFN_P2PDMA | HMM_PFN_P2PDMA_BUS);
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 07/16] dma-mapping: convert dma_direct_*map_page to be phys_addr_t based
Date: Thu, 14 Aug 2025 13:13:25 +0300
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From: Leon Romanovsky 

Convert the DMA direct mapping functions to accept physical addresses
directly instead of page+offset parameters. The functions were already
operating on physical addresses internally, so this change eliminates
the redundant page-to-physical conversion at the API boundary.

The functions dma_direct_map_page() and dma_direct_unmap_page() are
renamed to dma_direct_map_phys() and dma_direct_unmap_phys() respectively,
with their calling convention changed from (struct page *page,
unsigned long offset) to (phys_addr_t phys).

Architecture-specific functions arch_dma_map_page_direct() and
arch_dma_unmap_page_direct() are similarly renamed to
arch_dma_map_phys_direct() and arch_dma_unmap_phys_direct().

The is_pci_p2pdma_page() checks are replaced with DMA_ATTR_MMIO checks
to allow integration with dma_direct_map_resource and dma_direct_map_phys()
is extended to support MMIO path either.

Signed-off-by: Leon Romanovsky 
---
 arch/powerpc/kernel/dma-iommu.c |  4 +--
 include/linux/dma-map-ops.h     |  8 ++---
 kernel/dma/direct.c             |  6 ++--
 kernel/dma/direct.h             | 52 +++++++++++++++++++++------------
 kernel/dma/mapping.c            |  8 ++---
 5 files changed, 46 insertions(+), 32 deletions(-)

diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index 4d64a5db50f3..0359ab72cd3b 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -14,7 +14,7 @@
 #define can_map_direct(dev, addr) \
 	((dev)->bus_dma_limit >= phys_to_dma((dev), (addr)))
 
-bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr)
+bool arch_dma_map_phys_direct(struct device *dev, phys_addr_t addr)
 {
 	if (likely(!dev->bus_dma_limit))
 		return false;
@@ -24,7 +24,7 @@ bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr)
 
 #define is_direct_handle(dev, h) ((h) >= (dev)->archdata.dma_offset)
 
-bool arch_dma_unmap_page_direct(struct device *dev, dma_addr_t dma_handle)
+bool arch_dma_unmap_phys_direct(struct device *dev, dma_addr_t dma_handle)
 {
 	if (likely(!dev->bus_dma_limit))
 		return false;
diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
index f48e5fb88bd5..71f5b3025415 100644
--- a/include/linux/dma-map-ops.h
+++ b/include/linux/dma-map-ops.h
@@ -392,15 +392,15 @@ void *arch_dma_set_uncached(void *addr, size_t size);
 void arch_dma_clear_uncached(void *addr, size_t size);
 
 #ifdef CONFIG_ARCH_HAS_DMA_MAP_DIRECT
-bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr);
-bool arch_dma_unmap_page_direct(struct device *dev, dma_addr_t dma_handle);
+bool arch_dma_map_phys_direct(struct device *dev, phys_addr_t addr);
+bool arch_dma_unmap_phys_direct(struct device *dev, dma_addr_t dma_handle);
 bool arch_dma_map_sg_direct(struct device *dev, struct scatterlist *sg,
 		int nents);
 bool arch_dma_unmap_sg_direct(struct device *dev, struct scatterlist *sg,
 		int nents);
 #else
-#define arch_dma_map_page_direct(d, a)		(false)
-#define arch_dma_unmap_page_direct(d, a)	(false)
+#define arch_dma_map_phys_direct(d, a)		(false)
+#define arch_dma_unmap_phys_direct(d, a)	(false)
 #define arch_dma_map_sg_direct(d, s, n)		(false)
 #define arch_dma_unmap_sg_direct(d, s, n)	(false)
 #endif
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 24c359d9c879..fa75e3070073 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -453,7 +453,7 @@ void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
 		if (sg_dma_is_bus_address(sg))
 			sg_dma_unmark_bus_address(sg);
 		else
-			dma_direct_unmap_page(dev, sg->dma_address,
+			dma_direct_unmap_phys(dev, sg->dma_address,
 					      sg_dma_len(sg), dir, attrs);
 	}
 }
@@ -476,8 +476,8 @@ int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
 			 */
 			break;
 		case PCI_P2PDMA_MAP_NONE:
-			sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
-					sg->offset, sg->length, dir, attrs);
+			sg->dma_address = dma_direct_map_phys(dev, sg_phys(sg),
+					sg->length, dir, attrs);
 			if (sg->dma_address == DMA_MAPPING_ERROR) {
 				ret = -EIO;
 				goto out_unmap;
diff --git a/kernel/dma/direct.h b/kernel/dma/direct.h
index d2c0b7e632fc..92dbadcd3b2f 100644
--- a/kernel/dma/direct.h
+++ b/kernel/dma/direct.h
@@ -80,42 +80,56 @@ static inline void dma_direct_sync_single_for_cpu(struct device *dev,
 		arch_dma_mark_clean(paddr, size);
 }
 
-static inline dma_addr_t dma_direct_map_page(struct device *dev,
-		struct page *page, unsigned long offset, size_t size,
-		enum dma_data_direction dir, unsigned long attrs)
+static inline dma_addr_t dma_direct_map_phys(struct device *dev,
+		phys_addr_t phys, size_t size, enum dma_data_direction dir,
+		unsigned long attrs)
 {
-	phys_addr_t phys = page_to_phys(page) + offset;
-	dma_addr_t dma_addr = phys_to_dma(dev, phys);
+	dma_addr_t dma_addr;
+	bool capable;
 
 	if (is_swiotlb_force_bounce(dev)) {
-		if (is_pci_p2pdma_page(page))
-			return DMA_MAPPING_ERROR;
+		if (attrs & DMA_ATTR_MMIO)
+			goto err_overflow;
+
 		return swiotlb_map(dev, phys, size, dir, attrs);
 	}
 
-	if (unlikely(!dma_capable(dev, dma_addr, size, true)) ||
-	    dma_kmalloc_needs_bounce(dev, size, dir)) {
-		if (is_pci_p2pdma_page(page))
-			return DMA_MAPPING_ERROR;
-		if (is_swiotlb_active(dev))
+	if (attrs & DMA_ATTR_MMIO)
+		dma_addr = phys;
+	else
+		dma_addr = phys_to_dma(dev, phys);
+
+	capable = dma_capable(dev, dma_addr, size, !(attrs & DMA_ATTR_MMIO));
+	if (unlikely(!capable) || dma_kmalloc_needs_bounce(dev, size, dir)) {
+		if (is_swiotlb_active(dev) && !(attrs & DMA_ATTR_MMIO))
 			return swiotlb_map(dev, phys, size, dir, attrs);
 
-		dev_WARN_ONCE(dev, 1,
-			     "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
-			     &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
-		return DMA_MAPPING_ERROR;
+		goto err_overflow;
 	}
 
-	if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+	if (!dev_is_dma_coherent(dev) &&
+	    !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
 		arch_sync_dma_for_device(phys, size, dir);
 	return dma_addr;
+
+err_overflow:
+	dev_WARN_ONCE(
+		dev, 1,
+		"DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
+		&dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
+	return DMA_MAPPING_ERROR;
 }
 
-static inline void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
+static inline void dma_direct_unmap_phys(struct device *dev, dma_addr_t addr,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
-	phys_addr_t phys = dma_to_phys(dev, addr);
+	phys_addr_t phys;
+
+	if (attrs & DMA_ATTR_MMIO)
+		/* nothing to do: uncached and no swiotlb */
+		return;
 
+	phys = dma_to_phys(dev, addr);
 	if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
 		dma_direct_sync_single_for_cpu(dev, addr, size, dir);
 
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 58482536db9b..80481a873340 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -166,8 +166,8 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		return DMA_MAPPING_ERROR;
 
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_map_page_direct(dev, phys + size))
-		addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
+	    arch_dma_map_phys_direct(dev, phys + size))
+		addr = dma_direct_map_phys(dev, phys, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
 	else
@@ -187,8 +187,8 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 
 	BUG_ON(!valid_dma_direction(dir));
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_unmap_page_direct(dev, addr + size))
-		dma_direct_unmap_page(dev, addr, size, dir, attrs);
+	    arch_dma_unmap_phys_direct(dev, addr + size))
+		dma_direct_unmap_phys(dev, addr, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
 	else
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v2 13/16] mm/hmm: properly take MMIO path
Date: Thu, 14 Aug 2025 13:13:31 +0300
Message-ID: <1c5a07cc7b40e956b2d75328fc95e45e82d2da5d.1755153054.git.leon@kernel.org>
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From: Leon Romanovsky 

In case peer-to-peer transaction traverses through host bridge,
the IOMMU needs to have IOMMU_MMIO flag, together with skip of
CPU sync.

The latter was handled by provided DMA_ATTR_SKIP_CPU_SYNC flag,
but IOMMU flag was missed, due to assumption that such memory
can be treated as regular one.

Reuse newly introduced DMA attribute to properly take MMIO path.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 mm/hmm.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index 015ab243f081..6556c0e074ba 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -746,7 +746,7 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
 	case PCI_P2PDMA_MAP_NONE:
 		break;
 	case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
-		attrs |= DMA_ATTR_SKIP_CPU_SYNC;
+		attrs |= DMA_ATTR_MMIO;
 		pfns[idx] |= HMM_PFN_P2PDMA;
 		break;
 	case PCI_P2PDMA_MAP_BUS_ADDR:
@@ -776,7 +776,7 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
 			goto error;
 
 		dma_addr = dma_map_phys(dev, paddr, map->dma_entry_size,
-					DMA_BIDIRECTIONAL, 0);
+					DMA_BIDIRECTIONAL, attrs);
 		if (dma_mapping_error(dev, dma_addr))
 			goto error;
 
@@ -811,16 +811,17 @@ bool hmm_dma_unmap_pfn(struct device *dev, struct hmm_dma_map *map, size_t idx)
 	if ((pfns[idx] & valid_dma) != valid_dma)
 		return false;
 
+	if (pfns[idx] & HMM_PFN_P2PDMA)
+		attrs |= DMA_ATTR_MMIO;
+
 	if (pfns[idx] & HMM_PFN_P2PDMA_BUS)
 		; /* no need to unmap bus address P2P mappings */
-	else if (dma_use_iova(state)) {
-		if (pfns[idx] & HMM_PFN_P2PDMA)
-			attrs |= DMA_ATTR_SKIP_CPU_SYNC;
+	else if (dma_use_iova(state))
 		dma_iova_unlink(dev, state, idx * map->dma_entry_size,
 				map->dma_entry_size, DMA_BIDIRECTIONAL, attrs);
-	} else if (dma_need_unmap(dev))
+	else if (dma_need_unmap(dev))
 		dma_unmap_phys(dev, dma_addrs[idx], map->dma_entry_size,
-			       DMA_BIDIRECTIONAL, 0);
+			       DMA_BIDIRECTIONAL, attrs);
 
 	pfns[idx] &=
 		~(HMM_PFN_DMA_MAPPED | HMM_PFN_P2PDMA | HMM_PFN_P2PDMA_BUS);
-- 
2.50.1



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        Thu, 14 Aug 2025 03:28:35 -0700 (PDT)
Date: Thu, 14 Aug 2025 12:28:34 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel , Julien Grall ,
	Stefano Stabellini ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH] pdx: cast PAGE_SIZE value ahead of shifting
Message-ID: 
References: <20250813125538.78174-1-roger.pau@citrix.com>
 
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On Thu, Aug 14, 2025 at 09:18:45AM +0200, Jan Beulich wrote:
> On 13.08.2025 14:55, Roger Pau Monne wrote:
> > --- a/xen/common/pdx.c
> > +++ b/xen/common/pdx.c
> > @@ -288,7 +288,7 @@ bool __init pfn_pdx_compression_setup(paddr_t base)
> >  
> >      pfn_pdx_hole_shift  = hole_shift;
> >      pfn_pdx_bottom_mask = (1UL << bottom_shift) - 1;
> > -    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
> > +    ma_va_bottom_mask   = ((paddr_t)PAGE_SIZE << bottom_shift) - 1;
> 
> Given
> 
> #define PAGE_SIZE           (_AC(1,L) << PAGE_SHIFT)
> 
> this shouldn't be needed, except maybe for Arm32. There, however, ...
> 
> >      pfn_hole_mask       = ((1UL << hole_shift) - 1) << bottom_shift;
> 
> ... this and the shift immediately ahead would also be a problem afaict,
> which makes me conclude this isn't what Coverity has looked at. I expect
> the problem is with the toolstack side definition of PAGE_SIZE, which imo
> would rather be addressed there. (And yes, I'm pretty averse to arbitrary
> casts like this being introduced.)

As I've realized while looking at this, wouldn't ma_va_bottom_mask
also better be of type paddr_t, since it's not operating on pfns, but
physical addresses.  I didn't adjust the type of ma_va_bottom_mask,
but I would be happy to do it if you agree.

Thanks, roger.


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Date: Thu, 14 Aug 2025 12:35:52 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel , Julien Grall ,
	Stefano Stabellini ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH] x86/pvh: update "Host ACPI" support status
Message-ID: 
References: <20250813093220.76030-1-roger.pau@citrix.com>
 
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On Thu, Aug 14, 2025 at 09:21:53AM +0200, Jan Beulich wrote:
> On 13.08.2025 11:32, Roger Pau Monne wrote:
> > For x86 PVH dom0 makes uses of the host ACPI tables, and hence the status
> > of Host ACPI entry should have been updated to reflect that PVH dom0 is now
> > supported, and Host ACPI support is not one of the caveats.
> 
> Well, not explicitly, but seeing changes like 6378909b41c4 ("x86/PVH: expose
> OEMx ACPI tables to Dom0") I'm not convinced we're there yet.

How would we know when we are there?  I think listing it here means it
had some degree of testing (which it does in Gitlab CI), plus that we
will address issues and backport fixes (which to my knowledge we
already do).

AFAICT the only way x86 PVH dom0 can get it's hardware information is
from ACPI, so not listing it as supported is IMO weird, it's not like
PCI passthrough or some additional feature, without ACPI support you
cannot really boot a PVH dom0 I think.

Thanks, Roger.


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On 14.08.2025 12:28, Roger Pau Monné wrote:
> On Thu, Aug 14, 2025 at 09:18:45AM +0200, Jan Beulich wrote:
>> On 13.08.2025 14:55, Roger Pau Monne wrote:
>>> --- a/xen/common/pdx.c
>>> +++ b/xen/common/pdx.c
>>> @@ -288,7 +288,7 @@ bool __init pfn_pdx_compression_setup(paddr_t base)
>>>  
>>>      pfn_pdx_hole_shift  = hole_shift;
>>>      pfn_pdx_bottom_mask = (1UL << bottom_shift) - 1;
>>> -    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
>>> +    ma_va_bottom_mask   = ((paddr_t)PAGE_SIZE << bottom_shift) - 1;
>>
>> Given
>>
>> #define PAGE_SIZE           (_AC(1,L) << PAGE_SHIFT)
>>
>> this shouldn't be needed, except maybe for Arm32. There, however, ...
>>
>>>      pfn_hole_mask       = ((1UL << hole_shift) - 1) << bottom_shift;
>>
>> ... this and the shift immediately ahead would also be a problem afaict,
>> which makes me conclude this isn't what Coverity has looked at. I expect
>> the problem is with the toolstack side definition of PAGE_SIZE, which imo
>> would rather be addressed there. (And yes, I'm pretty averse to arbitrary
>> casts like this being introduced.)
> 
> As I've realized while looking at this, wouldn't ma_va_bottom_mask
> also better be of type paddr_t, since it's not operating on pfns, but
> physical addresses.  I didn't adjust the type of ma_va_bottom_mask,
> but I would be happy to do it if you agree.

No, as its name says it's also used on virtual addresses (really: offsets
into the direct map). It hence would better not have any bits set outside
of the range that VAs can cover. With that, imo the cast (if any) also
should have been to unsigned long, not paddr_t. Yet as said, im the cast
would better not be there in the first place. Just that meanwhile I've
learned that this was committed already.

Jan


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On 14.08.2025 12:35, Roger Pau Monné wrote:
> On Thu, Aug 14, 2025 at 09:21:53AM +0200, Jan Beulich wrote:
>> On 13.08.2025 11:32, Roger Pau Monne wrote:
>>> For x86 PVH dom0 makes uses of the host ACPI tables, and hence the status
>>> of Host ACPI entry should have been updated to reflect that PVH dom0 is now
>>> supported, and Host ACPI support is not one of the caveats.
>>
>> Well, not explicitly, but seeing changes like 6378909b41c4 ("x86/PVH: expose
>> OEMx ACPI tables to Dom0") I'm not convinced we're there yet.
> 
> How would we know when we are there?

That's the downside of the whitelisting approach: We may make it there
temporarily, but then a new table type may break us again.

>  I think listing it here means it
> had some degree of testing (which it does in Gitlab CI), plus that we
> will address issues and backport fixes (which to my knowledge we
> already do).

We do, yes. We did already before it was supported, to encourage its use.

> AFAICT the only way x86 PVH dom0 can get it's hardware information is
> from ACPI, so not listing it as supported is IMO weird, it's not like
> PCI passthrough or some additional feature, without ACPI support you
> cannot really boot a PVH dom0 I think.

I agree. And from that angle I also agree it ought to be marked as
supported. I really don't have a good suggestion here. My concern, in
any event, shouldn't stand in the way of this going in with someone
else's ack (e.g. Stefano's, that iirc you already got). Yet I'm
hesitant to provide one myself.

Jan


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Message-ID: <50b2b50a-da3a-44f9-9fea-10e2426ad0e6@suse.com>
Date: Thu, 14 Aug 2025 12:52:48 +0200
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Subject: Re: [PATCH 10/22] x86/traps: Move subarch_percpu_traps_init() into
 traps-setup.c
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-11-andrew.cooper3@citrix.com>
 <646c538a-850a-4370-8132-c06d9be8b422@citrix.com>
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From: Jan Beulich 
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On 14.08.2025 12:17, Andrew Cooper wrote:
> On 14/08/2025 9:58 am, Jan Beulich wrote:
>> On 13.08.2025 13:53, Andrew Cooper wrote:
>>> On 12/08/2025 10:52 am, Jan Beulich wrote:
>>>> On 11.08.2025 10:17, Andrew Cooper wrote:
>>>>> On 08/08/2025 9:23 pm, Andrew Cooper wrote:
>>>>>> ... along with the supporting functions.  Switch to Xen coding style, and make
>>>>>> static as there are no external callers.
>>>>>>
>>>>>> Rename to legacy_syscall_init() as a more accurate name.
>>>>>>
>>>>>> No functional change.
>>>>>>
>>>>>> Signed-off-by: Andrew Cooper 
>>>>>> ---
>>>>>> CC: Jan Beulich 
>>>>>> CC: Roger Pau Monné 
>>>>>> ---
>>>>>>  xen/arch/x86/include/asm/system.h |  2 -
>>>>>>  xen/arch/x86/traps-setup.c        | 97 ++++++++++++++++++++++++++++++-
>>>>>>  xen/arch/x86/x86_64/traps.c       | 92 -----------------------------
>>>>>>  3 files changed, 95 insertions(+), 96 deletions(-)
>>>>>>
>>>>>> diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
>>>>>> index 3cdc56e4ba6d..6c2800d8158d 100644
>>>>>> --- a/xen/arch/x86/include/asm/system.h
>>>>>> +++ b/xen/arch/x86/include/asm/system.h
>>>>>> @@ -256,6 +256,4 @@ static inline int local_irq_is_enabled(void)
>>>>>>  #define BROKEN_ACPI_Sx          0x0001
>>>>>>  #define BROKEN_INIT_AFTER_S1    0x0002
>>>>>>  
>>>>>> -void subarch_percpu_traps_init(void);
>>>>>> -
>>>>>>  #endif
>>>>>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>>>>>> index 13b8fcf0ba51..fbae7072c292 100644
>>>>>> --- a/xen/arch/x86/traps-setup.c
>>>>>> +++ b/xen/arch/x86/traps-setup.c
>>>>>> @@ -2,13 +2,15 @@
>>>>>>  /*
>>>>>>   * Configuration of event handling for all CPUs.
>>>>>>   */
>>>>>> +#include 
>>>>>>  #include 
>>>>>>  #include 
>>>>>>  
>>>>>> +#include 
>>>>>>  #include 
>>>>>>  #include 
>>>>>>  #include 
>>>>>> -#include 
>>>>>> +#include 
>>>>>>  #include 
>>>>>>  
>>>>>>  DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt);
>>>>>> @@ -19,6 +21,8 @@ static bool __initdata opt_ler;
>>>>>>  boolean_param("ler", opt_ler);
>>>>>>  
>>>>>>  void nocall entry_PF(void);
>>>>>> +void nocall lstar_enter(void);
>>>>>> +void nocall cstar_enter(void);
>>>>>>  
>>>>>>  /*
>>>>>>   * Sets up system tables and descriptors for IDT devliery.
>>>>>> @@ -138,6 +142,95 @@ static void load_system_tables(void)
>>>>>>      BUG_ON(stack_bottom & 15);
>>>>>>  }
>>>>>>  
>>>>>> +static unsigned int write_stub_trampoline(
>>>>>> +    unsigned char *stub, unsigned long stub_va,
>>>>>> +    unsigned long stack_bottom, unsigned long target_va)
>>>>>> +{
>>>>>> +    unsigned char *p = stub;
>>>>>> +
>>>>>> +    if ( cpu_has_xen_ibt )
>>>>>> +    {
>>>>>> +        place_endbr64(p);
>>>>>> +        p += 4;
>>>>>> +    }
>>>>>> +
>>>>>> +    /* Store guest %rax into %ss slot */
>>>>>> +    /* movabsq %rax, stack_bottom - 8 */
>>>>>> +    *p++ = 0x48;
>>>>>> +    *p++ = 0xa3;
>>>>>> +    *(uint64_t *)p = stack_bottom - 8;
>>>>>> +    p += 8;
>>>>>> +
>>>>>> +    /* Store guest %rsp in %rax */
>>>>>> +    /* movq %rsp, %rax */
>>>>>> +    *p++ = 0x48;
>>>>>> +    *p++ = 0x89;
>>>>>> +    *p++ = 0xe0;
>>>>>> +
>>>>>> +    /* Switch to Xen stack */
>>>>>> +    /* movabsq $stack_bottom - 8, %rsp */
>>>>>> +    *p++ = 0x48;
>>>>>> +    *p++ = 0xbc;
>>>>>> +    *(uint64_t *)p = stack_bottom - 8;
>>>>>> +    p += 8;
>>>>>> +
>>>>>> +    /* jmp target_va */
>>>>>> +    *p++ = 0xe9;
>>>>>> +    *(int32_t *)p = target_va - (stub_va + (p - stub) + 4);
>>>>>> +    p += 4;
>>>>>> +
>>>>>> +    /* Round up to a multiple of 16 bytes. */
>>>>>> +    return ROUNDUP(p - stub, 16);
>>>>>> +}
>>>>>> +
>>>>>> +static void legacy_syscall_init(void)
>>>>>> +{
>>>>>> +    unsigned long stack_bottom = get_stack_bottom();
>>>>>> +    unsigned long stub_va = this_cpu(stubs.addr);
>>>>>> +    unsigned char *stub_page;
>>>>>> +    unsigned int offset;
>>>>>> +
>>>>>> +    /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
>>>>>> +    if ( !IS_ENABLED(CONFIG_PV) )
>>>>>> +        return;
>>>>>> +
>>>>>> +    stub_page = map_domain_page(_mfn(this_cpu(stubs.mfn)));
>>>>>> +
>>>>>> +    /*
>>>>>> +     * Trampoline for SYSCALL entry from 64-bit mode.  The VT-x HVM vcpu
>>>>>> +     * context switch logic relies on the SYSCALL trampoline being at the
>>>>>> +     * start of the stubs.
>>>>>> +     */
>>>>>> +    wrmsrl(MSR_LSTAR, stub_va);
>>>>>> +    offset = write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>>>>> +                                   stub_va, stack_bottom,
>>>>>> +                                   (unsigned long)lstar_enter);
>>>>>> +    stub_va += offset;
>>>>>> +
>>>>>> +    if ( cpu_has_sep )
>>>>>> +    {
>>>>>> +        /* SYSENTER entry. */
>>>>>> +        wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
>>>>>> +        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
>>>>>> +        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
>>>>>> +    }
>>>>>> +
>>>>>> +    /* Trampoline for SYSCALL entry from compatibility mode. */
>>>>>> +    wrmsrl(MSR_CSTAR, stub_va);
>>>>>> +    offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>>>>> +                                    stub_va, stack_bottom,
>>>>>> +                                    (unsigned long)cstar_enter);
>>>>>> +
>>>>>> +    /* Don't consume more than half of the stub space here. */
>>>>>> +    ASSERT(offset <= STUB_BUF_SIZE / 2);
>>>>>> +
>>>>>> +    unmap_domain_page(stub_page);
>>>>>> +
>>>>>> +    /* Common SYSCALL parameters. */
>>>>>> +    wrmsrl(MSR_STAR, XEN_MSR_STAR);
>>>>>> +    wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
>>>>>> +}
>>>>> These want adjusting to use wrmsrns(), similarly to the previous patch. 
>>>>> Fixed locally.
>>>> Also the one higher in the function, I suppose.
>>> All of them.
>>>
>>> I'm not aware of anywhere were we want serialising behaviour, except for
>>> ICR which is buggly non-serialising and has workarounds.
>>>
>>> But I'm also not sure enough of this to suggest that we make wrmsr() be
>>> wrmsrns() by default.
>> I'm pretty sure we don't want this. If nothing else then to avoid code bloat
>> for MSR writes which are non-serializing even in the original form.
> 
> Even that's complicated.
> 
> For FRED, FS/GS_BASE/KERN need changes because the lack of SWAPGS forces
> MSR accesses even if we do have FSGSBASE active.
> 
> Writes to these were made non-serialising in Zen2 and later, but are
> still serialising on Intel.  i.e. they need converting to WRMSRNS even
> though plain WRMSR would be "fine" on all AMD systems (either because
> it's the only option, or because it's non-serialising).

Right, such would need converting. But x2APIC MSR accesses, for example,
should have a need.

Jan


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Date: Thu, 14 Aug 2025 12:02:01 +0100
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Subject: Re: [PATCH 10/22] x86/traps: Move subarch_percpu_traps_init() into
 traps-setup.c
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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 <646c538a-850a-4370-8132-c06d9be8b422@citrix.com>
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 <3ff00f71-b16e-4426-98f5-27bc6f6b92cf@citrix.com>
 
 
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In-Reply-To: <50b2b50a-da3a-44f9-9fea-10e2426ad0e6@suse.com>
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On 14/08/2025 11:52 am, Jan Beulich wrote:
> On 14.08.2025 12:17, Andrew Cooper wrote:
>> On 14/08/2025 9:58 am, Jan Beulich wrote:
>>> On 13.08.2025 13:53, Andrew Cooper wrote:
>>>> On 12/08/2025 10:52 am, Jan Beulich wrote:
>>>>> On 11.08.2025 10:17, Andrew Cooper wrote:
>>>>>> On 08/08/2025 9:23 pm, Andrew Cooper wrote:
>>>>>>> ... along with the supporting functions.  Switch to Xen coding style, and make
>>>>>>> static as there are no external callers.
>>>>>>>
>>>>>>> Rename to legacy_syscall_init() as a more accurate name.
>>>>>>>
>>>>>>> No functional change.
>>>>>>>
>>>>>>> Signed-off-by: Andrew Cooper 
>>>>>>> ---
>>>>>>> CC: Jan Beulich 
>>>>>>> CC: Roger Pau Monné 
>>>>>>> ---
>>>>>>>  xen/arch/x86/include/asm/system.h |  2 -
>>>>>>>  xen/arch/x86/traps-setup.c        | 97 ++++++++++++++++++++++++++++++-
>>>>>>>  xen/arch/x86/x86_64/traps.c       | 92 -----------------------------
>>>>>>>  3 files changed, 95 insertions(+), 96 deletions(-)
>>>>>>>
>>>>>>> diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h
>>>>>>> index 3cdc56e4ba6d..6c2800d8158d 100644
>>>>>>> --- a/xen/arch/x86/include/asm/system.h
>>>>>>> +++ b/xen/arch/x86/include/asm/system.h
>>>>>>> @@ -256,6 +256,4 @@ static inline int local_irq_is_enabled(void)
>>>>>>>  #define BROKEN_ACPI_Sx          0x0001
>>>>>>>  #define BROKEN_INIT_AFTER_S1    0x0002
>>>>>>>  
>>>>>>> -void subarch_percpu_traps_init(void);
>>>>>>> -
>>>>>>>  #endif
>>>>>>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>>>>>>> index 13b8fcf0ba51..fbae7072c292 100644
>>>>>>> --- a/xen/arch/x86/traps-setup.c
>>>>>>> +++ b/xen/arch/x86/traps-setup.c
>>>>>>> @@ -2,13 +2,15 @@
>>>>>>>  /*
>>>>>>>   * Configuration of event handling for all CPUs.
>>>>>>>   */
>>>>>>> +#include 
>>>>>>>  #include 
>>>>>>>  #include 
>>>>>>>  
>>>>>>> +#include 
>>>>>>>  #include 
>>>>>>>  #include 
>>>>>>>  #include 
>>>>>>> -#include 
>>>>>>> +#include 
>>>>>>>  #include 
>>>>>>>  
>>>>>>>  DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt);
>>>>>>> @@ -19,6 +21,8 @@ static bool __initdata opt_ler;
>>>>>>>  boolean_param("ler", opt_ler);
>>>>>>>  
>>>>>>>  void nocall entry_PF(void);
>>>>>>> +void nocall lstar_enter(void);
>>>>>>> +void nocall cstar_enter(void);
>>>>>>>  
>>>>>>>  /*
>>>>>>>   * Sets up system tables and descriptors for IDT devliery.
>>>>>>> @@ -138,6 +142,95 @@ static void load_system_tables(void)
>>>>>>>      BUG_ON(stack_bottom & 15);
>>>>>>>  }
>>>>>>>  
>>>>>>> +static unsigned int write_stub_trampoline(
>>>>>>> +    unsigned char *stub, unsigned long stub_va,
>>>>>>> +    unsigned long stack_bottom, unsigned long target_va)
>>>>>>> +{
>>>>>>> +    unsigned char *p = stub;
>>>>>>> +
>>>>>>> +    if ( cpu_has_xen_ibt )
>>>>>>> +    {
>>>>>>> +        place_endbr64(p);
>>>>>>> +        p += 4;
>>>>>>> +    }
>>>>>>> +
>>>>>>> +    /* Store guest %rax into %ss slot */
>>>>>>> +    /* movabsq %rax, stack_bottom - 8 */
>>>>>>> +    *p++ = 0x48;
>>>>>>> +    *p++ = 0xa3;
>>>>>>> +    *(uint64_t *)p = stack_bottom - 8;
>>>>>>> +    p += 8;
>>>>>>> +
>>>>>>> +    /* Store guest %rsp in %rax */
>>>>>>> +    /* movq %rsp, %rax */
>>>>>>> +    *p++ = 0x48;
>>>>>>> +    *p++ = 0x89;
>>>>>>> +    *p++ = 0xe0;
>>>>>>> +
>>>>>>> +    /* Switch to Xen stack */
>>>>>>> +    /* movabsq $stack_bottom - 8, %rsp */
>>>>>>> +    *p++ = 0x48;
>>>>>>> +    *p++ = 0xbc;
>>>>>>> +    *(uint64_t *)p = stack_bottom - 8;
>>>>>>> +    p += 8;
>>>>>>> +
>>>>>>> +    /* jmp target_va */
>>>>>>> +    *p++ = 0xe9;
>>>>>>> +    *(int32_t *)p = target_va - (stub_va + (p - stub) + 4);
>>>>>>> +    p += 4;
>>>>>>> +
>>>>>>> +    /* Round up to a multiple of 16 bytes. */
>>>>>>> +    return ROUNDUP(p - stub, 16);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void legacy_syscall_init(void)
>>>>>>> +{
>>>>>>> +    unsigned long stack_bottom = get_stack_bottom();
>>>>>>> +    unsigned long stub_va = this_cpu(stubs.addr);
>>>>>>> +    unsigned char *stub_page;
>>>>>>> +    unsigned int offset;
>>>>>>> +
>>>>>>> +    /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
>>>>>>> +    if ( !IS_ENABLED(CONFIG_PV) )
>>>>>>> +        return;
>>>>>>> +
>>>>>>> +    stub_page = map_domain_page(_mfn(this_cpu(stubs.mfn)));
>>>>>>> +
>>>>>>> +    /*
>>>>>>> +     * Trampoline for SYSCALL entry from 64-bit mode.  The VT-x HVM vcpu
>>>>>>> +     * context switch logic relies on the SYSCALL trampoline being at the
>>>>>>> +     * start of the stubs.
>>>>>>> +     */
>>>>>>> +    wrmsrl(MSR_LSTAR, stub_va);
>>>>>>> +    offset = write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>>>>>> +                                   stub_va, stack_bottom,
>>>>>>> +                                   (unsigned long)lstar_enter);
>>>>>>> +    stub_va += offset;
>>>>>>> +
>>>>>>> +    if ( cpu_has_sep )
>>>>>>> +    {
>>>>>>> +        /* SYSENTER entry. */
>>>>>>> +        wrmsrl(MSR_IA32_SYSENTER_ESP, stack_bottom);
>>>>>>> +        wrmsrl(MSR_IA32_SYSENTER_EIP, (unsigned long)sysenter_entry);
>>>>>>> +        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
>>>>>>> +    }
>>>>>>> +
>>>>>>> +    /* Trampoline for SYSCALL entry from compatibility mode. */
>>>>>>> +    wrmsrl(MSR_CSTAR, stub_va);
>>>>>>> +    offset += write_stub_trampoline(stub_page + (stub_va & ~PAGE_MASK),
>>>>>>> +                                    stub_va, stack_bottom,
>>>>>>> +                                    (unsigned long)cstar_enter);
>>>>>>> +
>>>>>>> +    /* Don't consume more than half of the stub space here. */
>>>>>>> +    ASSERT(offset <= STUB_BUF_SIZE / 2);
>>>>>>> +
>>>>>>> +    unmap_domain_page(stub_page);
>>>>>>> +
>>>>>>> +    /* Common SYSCALL parameters. */
>>>>>>> +    wrmsrl(MSR_STAR, XEN_MSR_STAR);
>>>>>>> +    wrmsrl(MSR_SYSCALL_MASK, XEN_SYSCALL_MASK);
>>>>>>> +}
>>>>>> These want adjusting to use wrmsrns(), similarly to the previous patch. 
>>>>>> Fixed locally.
>>>>> Also the one higher in the function, I suppose.
>>>> All of them.
>>>>
>>>> I'm not aware of anywhere were we want serialising behaviour, except for
>>>> ICR which is buggly non-serialising and has workarounds.
>>>>
>>>> But I'm also not sure enough of this to suggest that we make wrmsr() be
>>>> wrmsrns() by default.
>>> I'm pretty sure we don't want this. If nothing else then to avoid code bloat
>>> for MSR writes which are non-serializing even in the original form.
>> Even that's complicated.
>>
>> For FRED, FS/GS_BASE/KERN need changes because the lack of SWAPGS forces
>> MSR accesses even if we do have FSGSBASE active.
>>
>> Writes to these were made non-serialising in Zen2 and later, but are
>> still serialising on Intel.  i.e. they need converting to WRMSRNS even
>> though plain WRMSR would be "fine" on all AMD systems (either because
>> it's the only option, or because it's non-serialising).
> Right, such would need converting. But x2APIC MSR accesses, for example,
> should have a need.

For serialising-ness, yes, but they still want to be MSR_IMM when
available, at which point the code bloat price is already paid.

~Andrew


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Subject: Re: [PATCH 13/22] x86: FRED enumerations
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-14-andrew.cooper3@citrix.com>
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On 08.08.2025 22:23, Andrew Cooper wrote:
> Of note, CR4.FRED is bit 32 and cannot enabled outside of 64bit mode.
> 
> Most supported toolchains don't understand the FRED instructions yet.  ERETU
> and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC), while LKGS is
> more complicated and deferred for now.
> 
> I have intentionally named the FRED MSRs differently to the spec.  In the
> spec, the stack pointer names alias the TSS fields of the same name, despite
> very different semantics.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 
with ...

> --- a/xen/arch/x86/Kconfig
> +++ b/xen/arch/x86/Kconfig
> @@ -57,6 +57,10 @@ config HAS_CC_CET_IBT
>  	# Retpoline check to work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654
>  	def_bool $(cc-option,-fcf-protection=branch -mmanual-endbr -mindirect-branch=thunk-extern) && $(as-instr,endbr64)
>  
> +config HAS_AS_FRED
> +	# binutils >= 2.41 or LLVM >= 19
> +	def_bool $(as-instr,eretu;lkgs %ax)

..., as per your reply, this preferably dropped (without me insisting), and
with ...

> --- a/xen/arch/x86/include/asm/x86-defns.h
> +++ b/xen/arch/x86/include/asm/x86-defns.h
> @@ -75,6 +75,7 @@
>  #define X86_CR4_PKE        0x00400000 /* enable PKE */
>  #define X86_CR4_CET        0x00800000 /* Control-flow Enforcement Technology */
>  #define X86_CR4_PKS        0x01000000 /* Protection Key Supervisor */
> +#define X86_CR4_FRED      0x100000000 /* Fast Return and Event Delivery */

... a UL suffix added here for Misra.

> --- a/xen/include/public/arch-x86/cpufeatureset.h
> +++ b/xen/include/public/arch-x86/cpufeatureset.h
> @@ -310,7 +310,10 @@ XEN_CPUFEATURE(ARCH_PERF_MON, 10*32+8) /*   Architectural Perfmon */
>  XEN_CPUFEATURE(FZRM,         10*32+10) /*A  Fast Zero-length REP MOVSB */
>  XEN_CPUFEATURE(FSRS,         10*32+11) /*A  Fast Short REP STOSB */
>  XEN_CPUFEATURE(FSRCS,        10*32+12) /*A  Fast Short REP CMPSB/SCASB */
> +XEN_CPUFEATURE(FRED,         10*32+17) /*   Fast Return and Event Delivery */
> +XEN_CPUFEATURE(LKGS,         10*32+18) /*   Load Kernel GS instruction */
>  XEN_CPUFEATURE(WRMSRNS,      10*32+19) /*S  WRMSR Non-Serialising */
> +XEN_CPUFEATURE(NMI_SRC,      10*32+20) /*   NMI-Source Reporting */
>  XEN_CPUFEATURE(AMX_FP16,     10*32+21) /*   AMX FP16 instruction */
>  XEN_CPUFEATURE(AVX_IFMA,     10*32+23) /*A  AVX-IFMA Instructions */
>  XEN_CPUFEATURE(LAM,          10*32+26) /*   Linear Address Masking */

I'd like to note that we could long have had this if my long-pending emulator
patch had gone in at some point.

Jan


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Subject: Re: [PATCH 13/22] x86: FRED enumerations
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14/08/2025 12:20 pm, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> Of note, CR4.FRED is bit 32 and cannot enabled outside of 64bit mode.
>>
>> Most supported toolchains don't understand the FRED instructions yet.  ERETU
>> and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC), while LKGS is
>> more complicated and deferred for now.
>>
>> I have intentionally named the FRED MSRs differently to the spec.  In the
>> spec, the stack pointer names alias the TSS fields of the same name, despite
>> very different semantics.
>>
>> Signed-off-by: Andrew Cooper 
> Acked-by: Jan Beulich 

Thanks.

>> --- a/xen/arch/x86/include/asm/x86-defns.h
>> +++ b/xen/arch/x86/include/asm/x86-defns.h
>> @@ -75,6 +75,7 @@
>>  #define X86_CR4_PKE        0x00400000 /* enable PKE */
>>  #define X86_CR4_CET        0x00800000 /* Control-flow Enforcement Technology */
>>  #define X86_CR4_PKS        0x01000000 /* Protection Key Supervisor */
>> +#define X86_CR4_FRED      0x100000000 /* Fast Return and Event Delivery */
> ... a UL suffix added here for Misra.

I was surprised, but Eclair is entirely fine with this.

~Andrew


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Subject: Re: [PATCH 13/22] x86: FRED enumerations
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On 14.08.2025 13:42, Andrew Cooper wrote:
> On 14/08/2025 12:20 pm, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/include/asm/x86-defns.h
>>> +++ b/xen/arch/x86/include/asm/x86-defns.h
>>> @@ -75,6 +75,7 @@
>>>  #define X86_CR4_PKE        0x00400000 /* enable PKE */
>>>  #define X86_CR4_CET        0x00800000 /* Control-flow Enforcement Technology */
>>>  #define X86_CR4_PKS        0x01000000 /* Protection Key Supervisor */
>>> +#define X86_CR4_FRED      0x100000000 /* Fast Return and Event Delivery */
>> ... a UL suffix added here for Misra.
> 
> I was surprised, but Eclair is entirely fine with this.

And there is a use of the identifier in a monitored C file?

Jan


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Subject: Re: [PATCH 13/22] x86: FRED enumerations
To: Jan Beulich 
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 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14/08/2025 12:44 pm, Jan Beulich wrote:
> On 14.08.2025 13:42, Andrew Cooper wrote:
>> On 14/08/2025 12:20 pm, Jan Beulich wrote:
>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>> --- a/xen/arch/x86/include/asm/x86-defns.h
>>>> +++ b/xen/arch/x86/include/asm/x86-defns.h
>>>> @@ -75,6 +75,7 @@
>>>>  #define X86_CR4_PKE        0x00400000 /* enable PKE */
>>>>  #define X86_CR4_CET        0x00800000 /* Control-flow Enforcement Technology */
>>>>  #define X86_CR4_PKS        0x01000000 /* Protection Key Supervisor */
>>>> +#define X86_CR4_FRED      0x100000000 /* Fast Return and Event Delivery */
>>> ... a UL suffix added here for Misra.
>> I was surprised, but Eclair is entirely fine with this.
> And there is a use of the identifier in a monitored C file?

Yes.  traps-setup.c which definitely has not been added to an exclusion
list.

~Andrew


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Date: Thu, 14 Aug 2025 09:13:16 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 08/16] kmsan: convert kmsan_handle_dma to use physical
 addresses
Message-ID: <20250814121316.GC699432@nvidia.com>
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On Wed, Aug 13, 2025 at 06:07:18PM +0300, Leon Romanovsky wrote:
> > >  /* Helper function to handle DMA data transfers. */
> > > -void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
> > > +void kmsan_handle_dma(phys_addr_t phys, size_t size,
> > >  		      enum dma_data_direction dir)
> > >  {
> > >  	u64 page_offset, to_go, addr;
> > > +	struct page *page;
> > > +	void *kaddr;
> > >  
> > > -	if (PageHighMem(page))
> > > +	if (!pfn_valid(PHYS_PFN(phys)))
> > >  		return;
> > 
> > Not needed, the caller must pass in a phys that is kmap
> > compatible. Maybe just leave a comment. FWIW today this is also not
> > checking for P2P or DEVICE non-kmap struct pages either, so it should
> > be fine without checks.
> 
> It is not true as we will call to kmsan_handle_dma() unconditionally in
> dma_map_phys(). The reason to it is that kmsan_handle_dma() is guarded
> with debug kconfig options and cost of pfn_valid() can be accommodated
> in that case. It gives more clean DMA code.

Then check attrs here, not pfn_valid.

> So let's keep this patch as is.

Still need to fix the remarks you clipped, do not check PageHighMem
just call kmap_local_pfn(). All thie PageHighMem stuff is new to this
patch and should not be here, it is the wrong way to use highmem.

Jason


From xen-devel-bounces@lists.xenproject.org Thu Aug 14 12:35:25 2025
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Date: Thu, 14 Aug 2025 15:35:06 +0300
From: Leon Romanovsky 
To: Jason Gunthorpe 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 08/16] kmsan: convert kmsan_handle_dma to use physical
 addresses
Message-ID: <20250814123506.GD310013@unreal>
References: 
 <5b40377b621e49ff4107fa10646c828ccc94e53e.1754292567.git.leon@kernel.org>
 <20250807122115.GH184255@nvidia.com>
 <20250813150718.GB310013@unreal>
 <20250814121316.GC699432@nvidia.com>
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In-Reply-To: <20250814121316.GC699432@nvidia.com>

On Thu, Aug 14, 2025 at 09:13:16AM -0300, Jason Gunthorpe wrote:
> On Wed, Aug 13, 2025 at 06:07:18PM +0300, Leon Romanovsky wrote:
> > > >  /* Helper function to handle DMA data transfers. */
> > > > -void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
> > > > +void kmsan_handle_dma(phys_addr_t phys, size_t size,
> > > >  		      enum dma_data_direction dir)
> > > >  {
> > > >  	u64 page_offset, to_go, addr;
> > > > +	struct page *page;
> > > > +	void *kaddr;
> > > >  
> > > > -	if (PageHighMem(page))
> > > > +	if (!pfn_valid(PHYS_PFN(phys)))
> > > >  		return;
> > > 
> > > Not needed, the caller must pass in a phys that is kmap
> > > compatible. Maybe just leave a comment. FWIW today this is also not
> > > checking for P2P or DEVICE non-kmap struct pages either, so it should
> > > be fine without checks.
> > 
> > It is not true as we will call to kmsan_handle_dma() unconditionally in
> > dma_map_phys(). The reason to it is that kmsan_handle_dma() is guarded
> > with debug kconfig options and cost of pfn_valid() can be accommodated
> > in that case. It gives more clean DMA code.
> 
> Then check attrs here, not pfn_valid.

attrs are not available in kmsan_handle_dma(). I can add it if you prefer.

> 
> > So let's keep this patch as is.
> 
> Still need to fix the remarks you clipped, do not check PageHighMem
> just call kmap_local_pfn(). All thie PageHighMem stuff is new to this
> patch and should not be here, it is the wrong way to use highmem.

Sure, thanks

> 
> Jason
> 


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Date: Thu, 14 Aug 2025 09:44:48 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 08/16] kmsan: convert kmsan_handle_dma to use physical
 addresses
Message-ID: <20250814124448.GE699432@nvidia.com>
References: 
 <5b40377b621e49ff4107fa10646c828ccc94e53e.1754292567.git.leon@kernel.org>
 <20250807122115.GH184255@nvidia.com>
 <20250813150718.GB310013@unreal>
 <20250814121316.GC699432@nvidia.com>
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On Thu, Aug 14, 2025 at 03:35:06PM +0300, Leon Romanovsky wrote:
> > Then check attrs here, not pfn_valid.
> 
> attrs are not available in kmsan_handle_dma(). I can add it if you prefer.

That makes more sense to the overall design. The comments I gave
before were driving at a promise to never try to touch a struct page
for ATTR_MMIO and think this should be comphrensive to never touching
a struct page even if pfnvalid.

> > > So let's keep this patch as is.
> > 
> > Still need to fix the remarks you clipped, do not check PageHighMem
> > just call kmap_local_pfn(). All thie PageHighMem stuff is new to this
> > patch and should not be here, it is the wrong way to use highmem.
> 
> Sure, thanks

I am wondering if there is some reason it was written like this in the
first place. Maybe we can't even do kmap here.. So perhaps if there is
not a strong reason to change it just continue to check pagehighmem
and fail.

if (!(attrs & ATTR_MMIO) && PageHighMem(phys_to_page(phys)))
   return;

Jason


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Date: Thu, 14 Aug 2025 15:01:56 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel , Julien Grall ,
	Stefano Stabellini ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH] pdx: cast PAGE_SIZE value ahead of shifting
Message-ID: 
References: <20250813125538.78174-1-roger.pau@citrix.com>
 
 
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On Thu, Aug 14, 2025 at 12:45:40PM +0200, Jan Beulich wrote:
> On 14.08.2025 12:28, Roger Pau Monné wrote:
> > On Thu, Aug 14, 2025 at 09:18:45AM +0200, Jan Beulich wrote:
> >> On 13.08.2025 14:55, Roger Pau Monne wrote:
> >>> --- a/xen/common/pdx.c
> >>> +++ b/xen/common/pdx.c
> >>> @@ -288,7 +288,7 @@ bool __init pfn_pdx_compression_setup(paddr_t base)
> >>>  
> >>>      pfn_pdx_hole_shift  = hole_shift;
> >>>      pfn_pdx_bottom_mask = (1UL << bottom_shift) - 1;
> >>> -    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
> >>> +    ma_va_bottom_mask   = ((paddr_t)PAGE_SIZE << bottom_shift) - 1;
> >>
> >> Given
> >>
> >> #define PAGE_SIZE           (_AC(1,L) << PAGE_SHIFT)
> >>
> >> this shouldn't be needed, except maybe for Arm32. There, however, ...
> >>
> >>>      pfn_hole_mask       = ((1UL << hole_shift) - 1) << bottom_shift;
> >>
> >> ... this and the shift immediately ahead would also be a problem afaict,
> >> which makes me conclude this isn't what Coverity has looked at. I expect
> >> the problem is with the toolstack side definition of PAGE_SIZE, which imo
> >> would rather be addressed there. (And yes, I'm pretty averse to arbitrary
> >> casts like this being introduced.)
> > 
> > As I've realized while looking at this, wouldn't ma_va_bottom_mask
> > also better be of type paddr_t, since it's not operating on pfns, but
> > physical addresses.  I didn't adjust the type of ma_va_bottom_mask,
> > but I would be happy to do it if you agree.
> 
> No, as its name says it's also used on virtual addresses (really: offsets
> into the direct map). It hence would better not have any bits set outside
> of the range that VAs can cover.

It's confusing that it's sometimes used against a paddr_t or an
unsigned long type.  The logic itself already limits the shift so it's
below the width of unsigned long AFAICT.

> With that, imo the cast (if any) also
> should have been to unsigned long, not paddr_t. Yet as said, im the cast
> would better not be there in the first place. Just that meanwhile I've
> learned that this was committed already.

Sorry, I should have waited for your opinion.

I think you would prefer the patch below.  I can send this formally,
not sure whether you would prefer a formal revert of the previous
patch, plus the new fix applied, or doing the revert in the new patc
(like below) is fine.

Thanks, Roger.
---
diff --git a/tools/tests/pdx/harness.h b/tools/tests/pdx/harness.h
index 5bef7df650d2..a0fe33b4f1e0 100644
--- a/tools/tests/pdx/harness.h
+++ b/tools/tests/pdx/harness.h
@@ -33,7 +33,7 @@
 #define PAGE_SHIFT    12
 /* Some libcs define PAGE_SIZE in limits.h. */
 #undef  PAGE_SIZE
-#define PAGE_SIZE     (1 << PAGE_SHIFT)
+#define PAGE_SIZE     (1UL << PAGE_SHIFT)
 #define MAX_ORDER     18 /* 2 * PAGETABLE_ORDER (9) */
 
 #define PFN_DOWN(x)   ((x) >> PAGE_SHIFT)
diff --git a/xen/common/pdx.c b/xen/common/pdx.c
index 06536cc639f3..9e6b36086fbd 100644
--- a/xen/common/pdx.c
+++ b/xen/common/pdx.c
@@ -274,7 +274,7 @@ bool __init pfn_pdx_compression_setup(paddr_t base)
 
     pfn_pdx_hole_shift  = hole_shift;
     pfn_pdx_bottom_mask = (1UL << bottom_shift) - 1;
-    ma_va_bottom_mask   = ((paddr_t)PAGE_SIZE << bottom_shift) - 1;
+    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
     pfn_hole_mask       = ((1UL << hole_shift) - 1) << bottom_shift;
     pfn_top_mask        = ~(pfn_pdx_bottom_mask | pfn_hole_mask);
     ma_top_mask         = pfn_top_mask << PAGE_SHIFT;



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On 08.08.2025 22:23, Andrew Cooper wrote:
> @@ -42,17 +46,76 @@ struct cpu_user_regs
>       */
>  
>      union { uint64_t rip;    uint32_t eip;    uint16_t ip; };
> -    uint16_t cs, _pad0[1];
> -    uint8_t  saved_upcall_mask; /* PV (v)rflags.IF == !saved_upcall_mask */
> -    uint8_t  _pad1[3];
> +    union {
> +        struct {
> +            uint16_t      cs;
> +            unsigned long :16;
> +            uint8_t       saved_upcall_mask; /* PV (v)rflags.IF == !saved_upcall_mask */

Would this better be reproduced ...

> +        };
> +        unsigned long     csx;
> +        struct {
> +            /*
> +             * Bits 0 thru 31 control ERET{U,S} behaviour, and is state of the
> +             * interrupted context.
> +             */
> +            uint16_t      cs;
> +            unsigned int  sl:2;      /* Stack Level */
> +            bool          wfe:1;     /* Wait-for-ENDBRANCH state */

... here as well, just like you reproduce "cs"?

> +        } fred_cs;
> +    };
>      union { uint64_t rflags; uint32_t eflags; uint16_t flags; };
>      union { uint64_t rsp;    uint32_t esp;    uint16_t sp;    uint8_t spl; };
> -    uint16_t ss, _pad2[3];
> +    union {
> +        uint16_t          ss;
> +        unsigned long     ssx;

What use do you foresee for this and "csx"?

> +        struct {
> +            /*
> +             * Bits 0 thru 31 control ERET{U,S} behaviour, and is state about
> +             * the event which occured.
> +             */
> +            uint16_t      ss;
> +            bool          sti:1;     /* Was blocked-by-STI, and not cancelled */
> +            bool          swint:1;   /* Was a SYSCALL/SYSENTER/INT $N */
> +            bool          nmi:1;     /* Was an NMI. */
> +            unsigned long :13;
> +
> +            /*
> +             * Bits 32 thru 63 are ignored by ERET{U,S} and are informative
> +             * only.
> +             */
> +            uint8_t       vector;
> +            unsigned long :8;
> +            unsigned int  type:4;    /* X86_ET_* */
> +            unsigned long :4;
> +            bool          enclave:1; /* Event taken in SGX mode */
> +            bool          lm:1;      /* Was in Long Mode */

The bit indicates 64-bit mode aiui, not long mode (without which FRED isn't even
available).

> --- a/xen/arch/x86/include/asm/current.h
> +++ b/xen/arch/x86/include/asm/current.h
> @@ -38,6 +38,8 @@ struct vcpu;
>  
>  struct cpu_info {
>      struct cpu_user_regs guest_cpu_user_regs;
> +    struct fred_info _fred; /* Only used when FRED is active. */

Any particular need for the leading underscore?

Jan


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Date: Thu, 14 Aug 2025 15:15:26 +0200
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Subject: Re: [PATCH] pdx: cast PAGE_SIZE value ahead of shifting
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: <20250813125538.78174-1-roger.pau@citrix.com>
 
 
 <3fbdd1fc-e739-42cf-892b-a561910a5693@suse.com>
 
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From: Jan Beulich 
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On 14.08.2025 15:01, Roger Pau Monné wrote:
> On Thu, Aug 14, 2025 at 12:45:40PM +0200, Jan Beulich wrote:
>> On 14.08.2025 12:28, Roger Pau Monné wrote:
>>> On Thu, Aug 14, 2025 at 09:18:45AM +0200, Jan Beulich wrote:
>>>> On 13.08.2025 14:55, Roger Pau Monne wrote:
>>>>> --- a/xen/common/pdx.c
>>>>> +++ b/xen/common/pdx.c
>>>>> @@ -288,7 +288,7 @@ bool __init pfn_pdx_compression_setup(paddr_t base)
>>>>>  
>>>>>      pfn_pdx_hole_shift  = hole_shift;
>>>>>      pfn_pdx_bottom_mask = (1UL << bottom_shift) - 1;
>>>>> -    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
>>>>> +    ma_va_bottom_mask   = ((paddr_t)PAGE_SIZE << bottom_shift) - 1;
>>>>
>>>> Given
>>>>
>>>> #define PAGE_SIZE           (_AC(1,L) << PAGE_SHIFT)
>>>>
>>>> this shouldn't be needed, except maybe for Arm32. There, however, ...
>>>>
>>>>>      pfn_hole_mask       = ((1UL << hole_shift) - 1) << bottom_shift;
>>>>
>>>> ... this and the shift immediately ahead would also be a problem afaict,
>>>> which makes me conclude this isn't what Coverity has looked at. I expect
>>>> the problem is with the toolstack side definition of PAGE_SIZE, which imo
>>>> would rather be addressed there. (And yes, I'm pretty averse to arbitrary
>>>> casts like this being introduced.)
>>>
>>> As I've realized while looking at this, wouldn't ma_va_bottom_mask
>>> also better be of type paddr_t, since it's not operating on pfns, but
>>> physical addresses.  I didn't adjust the type of ma_va_bottom_mask,
>>> but I would be happy to do it if you agree.
>>
>> No, as its name says it's also used on virtual addresses (really: offsets
>> into the direct map). It hence would better not have any bits set outside
>> of the range that VAs can cover.
> 
> It's confusing that it's sometimes used against a paddr_t or an
> unsigned long type.  The logic itself already limits the shift so it's
> below the width of unsigned long AFAICT.

Well, the variable simply doesn't need to be wider than the narrowest type
it's used with.

>> With that, imo the cast (if any) also
>> should have been to unsigned long, not paddr_t. Yet as said, im the cast
>> would better not be there in the first place. Just that meanwhile I've
>> learned that this was committed already.
> 
> Sorry, I should have waited for your opinion.
> 
> I think you would prefer the patch below.

Yes.

>  I can send this formally,
> not sure whether you would prefer a formal revert of the previous
> patch, plus the new fix applied, or doing the revert in the new patc
> (like below) is fine.

Acked-by: Jan Beulich 

I don't see a strong need for an outright revert.

Jan


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Subject: Re: [PATCH] pdx: cast PAGE_SIZE value ahead of shifting
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Jan Beulich 
Cc: Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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On 14/08/2025 2:01 pm, Roger Pau Monné wrote:
> On Thu, Aug 14, 2025 at 12:45:40PM +0200, Jan Beulich wrote:
>> On 14.08.2025 12:28, Roger Pau Monné wrote:
>>> On Thu, Aug 14, 2025 at 09:18:45AM +0200, Jan Beulich wrote:
> diff --git a/tools/tests/pdx/harness.h b/tools/tests/pdx/harness.h
> index 5bef7df650d2..a0fe33b4f1e0 100644
> --- a/tools/tests/pdx/harness.h
> +++ b/tools/tests/pdx/harness.h
> @@ -33,7 +33,7 @@
>  #define PAGE_SHIFT    12
>  /* Some libcs define PAGE_SIZE in limits.h. */
>  #undef  PAGE_SIZE
> -#define PAGE_SIZE     (1 << PAGE_SHIFT)
> +#define PAGE_SIZE     (1UL << PAGE_SHIFT)

It should be 1L to match Xen.

~Andrew


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On 14.08.2025 13:20, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> --- a/xen/include/public/arch-x86/cpufeatureset.h
>> +++ b/xen/include/public/arch-x86/cpufeatureset.h
>> @@ -310,7 +310,10 @@ XEN_CPUFEATURE(ARCH_PERF_MON, 10*32+8) /*   Architectural Perfmon */
>>  XEN_CPUFEATURE(FZRM,         10*32+10) /*A  Fast Zero-length REP MOVSB */
>>  XEN_CPUFEATURE(FSRS,         10*32+11) /*A  Fast Short REP STOSB */
>>  XEN_CPUFEATURE(FSRCS,        10*32+12) /*A  Fast Short REP CMPSB/SCASB */
>> +XEN_CPUFEATURE(FRED,         10*32+17) /*   Fast Return and Event Delivery */
>> +XEN_CPUFEATURE(LKGS,         10*32+18) /*   Load Kernel GS instruction */
>>  XEN_CPUFEATURE(WRMSRNS,      10*32+19) /*S  WRMSR Non-Serialising */
>> +XEN_CPUFEATURE(NMI_SRC,      10*32+20) /*   NMI-Source Reporting */
>>  XEN_CPUFEATURE(AMX_FP16,     10*32+21) /*   AMX FP16 instruction */
>>  XEN_CPUFEATURE(AVX_IFMA,     10*32+23) /*A  AVX-IFMA Instructions */
>>  XEN_CPUFEATURE(LAM,          10*32+26) /*   Linear Address Masking */
> 
> I'd like to note that we could long have had this if my long-pending emulator
> patch had gone in at some point.

Actually what I further have there, and what in the context of patch 15 I
notice you should have here is

--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -278,7 +278,8 @@ def crunch_numbers(state):
         # superpages, PCID and PKU are only available in 4 level paging.
         # NO_LMSL indicates the absense of Long Mode Segment Limits, which
         # have been dropped in hardware.
-        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD],
+        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD,
+             LKGS],
 
         # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the
         # standard 3DNow in the earlier K6 processors.
@@ -347,6 +348,9 @@ def crunch_numbers(state):
         # computational instructions.  All further AMX features are built on top
         # of AMX-TILE.
         AMX_TILE: [AMX_BF16, AMX_INT8, AMX_FP16, AMX_COMPLEX],
+
+        # FRED builds on the LKGS instruction.
+        LKGS: [FRED],
     }
 
     deep_features = tuple(sorted(deps.keys()))

Jan


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Subject: Re: [PATCH 15/22] x86/traps: Introduce opt_fred
To: Andrew Cooper 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-16-andrew.cooper3@citrix.com>
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On 08.08.2025 22:23, Andrew Cooper wrote:
> ... disabled by default.  There is a lot of work before FRED can be enabled by
> default.
> 
> One part of FRED, the LKGS (Load Kernel GS) instruction, is enumerated
> separately but is mandatory as FRED disallows the SWAPGS instruction.
> Therefore, both CPUID bits must be checked.

See my (further) reply to patch 13 - I think FRED simply ought to depend on
LKGS.

> @@ -20,6 +22,9 @@ unsigned int __ro_after_init ler_msr;
>  static bool __initdata opt_ler;
>  boolean_param("ler", opt_ler);
>  
> +int8_t __ro_after_init opt_fred = 0; /* -1 when supported. */

I'm a little puzzled by the comment? DYM "once default-enabled"? Then ...

> @@ -305,6 +310,32 @@ void __init traps_init(void)
>      /* Replace early pagefault with real pagefault handler. */
>      _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF);
>  
> +    if ( !cpu_has_fred || !cpu_has_lkgs )
> +    {
> +        if ( opt_fred )

... this won't work anymore once the initializer is changed.

> +            printk(XENLOG_WARNING "FRED not available, ignoring\n");
> +        opt_fred = false;

Better use 0 here?

> +    }
> +
> +    if ( opt_fred == -1 )
> +        opt_fred = !pv_shim;

Imo it would be better to have the initializer be -1 right away, and comment
out the "!pv_shim" here, until we mean it to be default-enabled.

> +    if ( opt_fred )
> +    {
> +#ifdef CONFIG_PV32
> +        if ( opt_pv32 )
> +        {
> +            opt_pv32 = 0;
> +            printk(XENLOG_INFO "Disabling PV32 due to FRED\n");
> +        }
> +#endif
> +        printk("Using FRED event delivery\n");
> +    }
> +    else
> +    {
> +        printk("Using IDT event delivery\n");
> +    }

Could I talk you into omitting the figure braces here? Hmm, or perhaps you
mean to later move code here.

Jan


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Date: Thu, 14 Aug 2025 16:31:06 +0300
From: Leon Romanovsky 
To: Jason Gunthorpe 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 08/16] kmsan: convert kmsan_handle_dma to use physical
 addresses
Message-ID: <20250814133106.GE310013@unreal>
References: 
 <5b40377b621e49ff4107fa10646c828ccc94e53e.1754292567.git.leon@kernel.org>
 <20250807122115.GH184255@nvidia.com>
 <20250813150718.GB310013@unreal>
 <20250814121316.GC699432@nvidia.com>
 <20250814123506.GD310013@unreal>
 <20250814124448.GE699432@nvidia.com>
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In-Reply-To: <20250814124448.GE699432@nvidia.com>

On Thu, Aug 14, 2025 at 09:44:48AM -0300, Jason Gunthorpe wrote:
> On Thu, Aug 14, 2025 at 03:35:06PM +0300, Leon Romanovsky wrote:
> > > Then check attrs here, not pfn_valid.
> > 
> > attrs are not available in kmsan_handle_dma(). I can add it if you prefer.
> 
> That makes more sense to the overall design. The comments I gave
> before were driving at a promise to never try to touch a struct page
> for ATTR_MMIO and think this should be comphrensive to never touching
> a struct page even if pfnvalid.
> 
> > > > So let's keep this patch as is.
> > > 
> > > Still need to fix the remarks you clipped, do not check PageHighMem
> > > just call kmap_local_pfn(). All thie PageHighMem stuff is new to this
> > > patch and should not be here, it is the wrong way to use highmem.
> > 
> > Sure, thanks
> 
> I am wondering if there is some reason it was written like this in the
> first place. Maybe we can't even do kmap here.. So perhaps if there is
> not a strong reason to change it just continue to check pagehighmem
> and fail.
> 
> if (!(attrs & ATTR_MMIO) && PageHighMem(phys_to_page(phys)))
>    return;

Does this version good enough? There is no need to call to
kmap_local_pfn() if we prevent PageHighMem pages.

diff --git a/mm/kmsan/hooks.c b/mm/kmsan/hooks.c
index eab7912a3bf0..d9cf70f4159c 100644
--- a/mm/kmsan/hooks.c
+++ b/mm/kmsan/hooks.c
@@ -337,13 +337,13 @@ static void kmsan_handle_dma_page(const void *addr, size_t size,

 /* Helper function to handle DMA data transfers. */
 void kmsan_handle_dma(phys_addr_t phys, size_t size,
-                     enum dma_data_direction dir)
+                     enum dma_data_direction dir, unsigned long attrs)
 {
        u64 page_offset, to_go, addr;
        struct page *page;
        void *kaddr;

-       if (!pfn_valid(PHYS_PFN(phys)))
+       if ((attrs & ATTR_MMIO) || PageHighMem(phys_to_page(phys)))
                return;

        page = phys_to_page(phys);
@@ -357,19 +357,12 @@ void kmsan_handle_dma(phys_addr_t phys, size_t size,
        while (size > 0) {
                to_go = min(PAGE_SIZE - page_offset, (u64)size);

-               if (PageHighMem(page))
-                       /* Handle highmem pages using kmap */
-                       kaddr = kmap_local_page(page);
-               else
-                       /* Lowmem pages can be accessed directly */
-                       kaddr = page_address(page);
+               /* Lowmem pages can be accessed directly */
+               kaddr = page_address(page);

                addr = (u64)kaddr + page_offset;
                kmsan_handle_dma_page((void *)addr, to_go, dir);

-               if (PageHighMem(page))
-                       kunmap_local(page);
-
                phys += to_go;
                size -= to_go;

(END)


> 
> Jason
> 


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Date: Thu, 14 Aug 2025 16:04:59 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: "xen-devel@lists.xenproject.org" ,
	Andrew Cooper 
Subject: Re: [PATCH v2 1/2] x86/mkelf32: pad load segment to 2Mb boundary
Message-ID: 
References: 
 <6e295921-0432-435e-9efe-51caa106f203@suse.com>
 
 <38430fbf-a6e4-4ba9-bbff-2279108721e6@suse.com>
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On Thu, Aug 14, 2025 at 09:02:35AM +0200, Jan Beulich wrote:
> On 12.08.2025 18:18, Roger Pau Monné wrote:
> > On Mon, Aug 11, 2025 at 12:49:57PM +0200, Jan Beulich wrote:
> >> @@ -339,9 +340,12 @@ int main(int argc, char **argv)
> >>      (void)lseek(infd, in64_phdr.p_offset, SEEK_SET);
> >>      dat_siz = (uint32_t)in64_phdr.p_filesz;
> >>  
> >> -    /* Do not use p_memsz: it does not include BSS alignment padding. */
> >> -    /*mem_siz = (uint32_t)in64_phdr.p_memsz;*/
> >> -    mem_siz = (uint32_t)(final_exec_addr - in64_phdr.p_vaddr);
> >> +    /*
> >> +     * We don't pad .bss in the linker script, but during early boot we map
> >> +     * the Xen image using 2M pages.  To avoid running into adjacent non-RAM
> >> +     * regions, pad the segment to the next 2M boundary.
> > 
> > Won't it be easier to pad in the linker script?  We could still have
> > __bss_end before the padding, so that initialization isn't done to the
> > extra padding area.  Otherwise it would be helpful to mention why the
> > padding must be done here (opposed to being done in the linker
> > script).
> 
> The way the linker script currently is written doesn't lend itself to do
> the padding there: It would either mean to introduce an artificial
> padding section (which I'd dislike), or it would result in _end[] and
> __2M_rwdata_end[] also moving, which pretty clearly we don't want. Maybe
> there are other options that I simply don't see.

We could move both _end and __2M_rwdata_end inside the .bss section,
but that's also ugly IMO.  I would probably prefer the extra padding
section.

> A further complication would be xen.efi's .reloc, which we don't want to
> needlessly move either. That may be coverable by pr-processor
> conditionals, but I wanted to mention the aspect nevertheless.

Yeah, we could make the extra padding section depend on pre-processor
checks.  I think I would prefer the usage of such extra section rather
than mangling the elf program headers afterwards, but since we are
already doing it:

Acked-by: Roger Pau Monné 

Thanks, Roger.


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Date: Thu, 14 Aug 2025 11:14:37 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 08/16] kmsan: convert kmsan_handle_dma to use physical
 addresses
Message-ID: <20250814141437.GH802098@nvidia.com>
References: 
 <5b40377b621e49ff4107fa10646c828ccc94e53e.1754292567.git.leon@kernel.org>
 <20250807122115.GH184255@nvidia.com>
 <20250813150718.GB310013@unreal>
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On Thu, Aug 14, 2025 at 04:31:06PM +0300, Leon Romanovsky wrote:
> On Thu, Aug 14, 2025 at 09:44:48AM -0300, Jason Gunthorpe wrote:
> > On Thu, Aug 14, 2025 at 03:35:06PM +0300, Leon Romanovsky wrote:
> > > > Then check attrs here, not pfn_valid.
> > > 
> > > attrs are not available in kmsan_handle_dma(). I can add it if you prefer.
> > 
> > That makes more sense to the overall design. The comments I gave
> > before were driving at a promise to never try to touch a struct page
> > for ATTR_MMIO and think this should be comphrensive to never touching
> > a struct page even if pfnvalid.
> > 
> > > > > So let's keep this patch as is.
> > > > 
> > > > Still need to fix the remarks you clipped, do not check PageHighMem
> > > > just call kmap_local_pfn(). All thie PageHighMem stuff is new to this
> > > > patch and should not be here, it is the wrong way to use highmem.
> > > 
> > > Sure, thanks
> > 
> > I am wondering if there is some reason it was written like this in the
> > first place. Maybe we can't even do kmap here.. So perhaps if there is
> > not a strong reason to change it just continue to check pagehighmem
> > and fail.
> > 
> > if (!(attrs & ATTR_MMIO) && PageHighMem(phys_to_page(phys)))
> >    return;
> 
> Does this version good enough? There is no need to call to
> kmap_local_pfn() if we prevent PageHighMem pages.

Why make the rest of the changes though, isn't it just:

        if (PageHighMem(page))
                return;

Becomes:

        if (attrs & ATTR_MMIO))
                return;

	page = phys_to_page(phys);
	if (PageHighMem(page))
                 return;

Leave the rest as is?

Jason


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Subject: Re: [PATCH 16/22] x86/boot: Adjust CR4 handling around
 ap_early_traps_init()
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-17-andrew.cooper3@citrix.com>
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On 08.08.2025 22:23, Andrew Cooper wrote:
> ap_early_traps_init() will shortly be setting CR4.FRED.  This requires that
> cpu_info->cr4 is already set up, and that the enablement of CET doesn't
> truncate FRED back out because of it's 32bit logic.
> 
> For __high_start(), defer re-loading XEN_MINIMAL_CR4 until after %rsp is set
> up and we can store the result in the cr4 field too.
> 
> For s3_resume(), explicitly re-load XEN_MINIMAL_CR4.  Later when loading all
> features, use the mmu_cr4_features variable which is how the rest of Xen
> performs this operation.
> 
> No functional change, yet.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 

> --- a/xen/arch/x86/acpi/wakeup_prot.S
> +++ b/xen/arch/x86/acpi/wakeup_prot.S
> @@ -63,6 +63,14 @@ LABEL(s3_resume)
>          pushq   %rax
>          lretq
>  1:
> +
> +        GET_STACK_END(15)
> +
> +        /* Enable minimal CR4 features. */
> +        mov     $XEN_MINIMAL_CR4, %eax
> +        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)

Strictly speaking this and ...

> --- a/xen/arch/x86/boot/x86_64.S
> +++ b/xen/arch/x86/boot/x86_64.S
> @@ -11,16 +11,19 @@ ENTRY(__high_start)
>          mov     %ecx,%gs
>          mov     %ecx,%ss
>  
> -        /* Enable minimal CR4 features. */
> -        mov     $XEN_MINIMAL_CR4,%rcx
> -        mov     %rcx,%cr4
> -
>          mov     stack_start(%rip),%rsp
>  
>          /* Reset EFLAGS (subsumes CLI and CLD). */
>          pushq   $0
>          popf
>  
> +        GET_STACK_END(15)
> +
> +        /* Enable minimal CR4 features. */
> +        mov     $XEN_MINIMAL_CR4, %eax
> +        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)

... this could be 32-bit stores, even in the longer run.

Jan


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On 08.08.2025 22:23, Andrew Cooper wrote:
> Under FRED, SETSSBSY is unavailable, and we want to be setting up FRED prior
> to setting up shadow stacks.  Luckily, RSTORSSP will also work in this case.
> 
> This involves a new type of shadow stack token, the Restore Token, which is
> distinguished from the Supervisor Token by pointing to the adjacent slot on
> the shadow stack rather than pointing at itself.
> 
> In the short term, this logic still needs to load MSR_PL0_SSP.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 



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On 14/08/2025 3:47 pm, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> ap_early_traps_init() will shortly be setting CR4.FRED.  This requires that
>> cpu_info->cr4 is already set up, and that the enablement of CET doesn't
>> truncate FRED back out because of it's 32bit logic.
>>
>> For __high_start(), defer re-loading XEN_MINIMAL_CR4 until after %rsp is set
>> up and we can store the result in the cr4 field too.
>>
>> For s3_resume(), explicitly re-load XEN_MINIMAL_CR4.  Later when loading all
>> features, use the mmu_cr4_features variable which is how the rest of Xen
>> performs this operation.
>>
>> No functional change, yet.
>>
>> Signed-off-by: Andrew Cooper 
> Reviewed-by: Jan Beulich 

Thanks.

Unfortunately, ...

>
>> --- a/xen/arch/x86/acpi/wakeup_prot.S
>> +++ b/xen/arch/x86/acpi/wakeup_prot.S
>> @@ -63,6 +63,14 @@ LABEL(s3_resume)
>>          pushq   %rax
>>          lretq
>>  1:
>> +
>> +        GET_STACK_END(15)
>> +
>> +        /* Enable minimal CR4 features. */
>> +        mov     $XEN_MINIMAL_CR4, %eax
>> +        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
> Strictly speaking this and ...
>
>> --- a/xen/arch/x86/boot/x86_64.S
>> +++ b/xen/arch/x86/boot/x86_64.S
>> @@ -11,16 +11,19 @@ ENTRY(__high_start)
>>          mov     %ecx,%gs
>>          mov     %ecx,%ss
>>  
>> -        /* Enable minimal CR4 features. */
>> -        mov     $XEN_MINIMAL_CR4,%rcx
>> -        mov     %rcx,%cr4
>> -
>>          mov     stack_start(%rip),%rsp
>>  
>>          /* Reset EFLAGS (subsumes CLI and CLD). */
>>          pushq   $0
>>          popf
>>  
>> +        GET_STACK_END(15)
>> +
>> +        /* Enable minimal CR4 features. */
>> +        mov     $XEN_MINIMAL_CR4, %eax
>> +        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
> ... this could be 32-bit stores, even in the longer run.

... no, they can't.

The store also serves to clear out stale X86_CR4_FRED, prior to FRED
getting reconfigured again.

fatal_trap() uses info->cr4 to decide whether it's safe to look at the
extended FRED metadata.  Strictly speaking I probably ought to read the
real CR4 (in read_registers too), but using a 32bit store here would
extend a 1-instruction window into quite a larger window where exception
handling would not work quite right.

~Andrew


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Subject: Re: [PATCH 16/22] x86/boot: Adjust CR4 handling around
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To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14.08.2025 16:54, Andrew Cooper wrote:
> On 14/08/2025 3:47 pm, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/acpi/wakeup_prot.S
>>> +++ b/xen/arch/x86/acpi/wakeup_prot.S
>>> @@ -63,6 +63,14 @@ LABEL(s3_resume)
>>>          pushq   %rax
>>>          lretq
>>>  1:
>>> +
>>> +        GET_STACK_END(15)
>>> +
>>> +        /* Enable minimal CR4 features. */
>>> +        mov     $XEN_MINIMAL_CR4, %eax
>>> +        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
>> Strictly speaking this and ...
>>
>>> --- a/xen/arch/x86/boot/x86_64.S
>>> +++ b/xen/arch/x86/boot/x86_64.S
>>> @@ -11,16 +11,19 @@ ENTRY(__high_start)
>>>          mov     %ecx,%gs
>>>          mov     %ecx,%ss
>>>  
>>> -        /* Enable minimal CR4 features. */
>>> -        mov     $XEN_MINIMAL_CR4,%rcx
>>> -        mov     %rcx,%cr4
>>> -
>>>          mov     stack_start(%rip),%rsp
>>>  
>>>          /* Reset EFLAGS (subsumes CLI and CLD). */
>>>          pushq   $0
>>>          popf
>>>  
>>> +        GET_STACK_END(15)
>>> +
>>> +        /* Enable minimal CR4 features. */
>>> +        mov     $XEN_MINIMAL_CR4, %eax
>>> +        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
>> ... this could be 32-bit stores, even in the longer run.
> 
> ... no, they can't.
> 
> The store also serves to clear out stale X86_CR4_FRED, prior to FRED
> getting reconfigured again.
> 
> fatal_trap() uses info->cr4 to decide whether it's safe to look at the
> extended FRED metadata.  Strictly speaking I probably ought to read the
> real CR4 (in read_registers too), but using a 32bit store here would
> extend a 1-instruction window into quite a larger window where exception
> handling would not work quite right.

Oh, I see. Mind me asking to add brief comments there to this effect?

Jan


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From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel , Julien Grall ,
	Stefano Stabellini ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH] pdx: cast PAGE_SIZE value ahead of shifting
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On Thu, Aug 14, 2025 at 03:15:26PM +0200, Jan Beulich wrote:
> On 14.08.2025 15:01, Roger Pau Monné wrote:
> > On Thu, Aug 14, 2025 at 12:45:40PM +0200, Jan Beulich wrote:
> >> On 14.08.2025 12:28, Roger Pau Monné wrote:
> >>> On Thu, Aug 14, 2025 at 09:18:45AM +0200, Jan Beulich wrote:
> >>>> On 13.08.2025 14:55, Roger Pau Monne wrote:
> >>>>> --- a/xen/common/pdx.c
> >>>>> +++ b/xen/common/pdx.c
> >>>>> @@ -288,7 +288,7 @@ bool __init pfn_pdx_compression_setup(paddr_t base)
> >>>>>  
> >>>>>      pfn_pdx_hole_shift  = hole_shift;
> >>>>>      pfn_pdx_bottom_mask = (1UL << bottom_shift) - 1;
> >>>>> -    ma_va_bottom_mask   = (PAGE_SIZE << bottom_shift) - 1;
> >>>>> +    ma_va_bottom_mask   = ((paddr_t)PAGE_SIZE << bottom_shift) - 1;
> >>>>
> >>>> Given
> >>>>
> >>>> #define PAGE_SIZE           (_AC(1,L) << PAGE_SHIFT)
> >>>>
> >>>> this shouldn't be needed, except maybe for Arm32. There, however, ...
> >>>>
> >>>>>      pfn_hole_mask       = ((1UL << hole_shift) - 1) << bottom_shift;
> >>>>
> >>>> ... this and the shift immediately ahead would also be a problem afaict,
> >>>> which makes me conclude this isn't what Coverity has looked at. I expect
> >>>> the problem is with the toolstack side definition of PAGE_SIZE, which imo
> >>>> would rather be addressed there. (And yes, I'm pretty averse to arbitrary
> >>>> casts like this being introduced.)
> >>>
> >>> As I've realized while looking at this, wouldn't ma_va_bottom_mask
> >>> also better be of type paddr_t, since it's not operating on pfns, but
> >>> physical addresses.  I didn't adjust the type of ma_va_bottom_mask,
> >>> but I would be happy to do it if you agree.
> >>
> >> No, as its name says it's also used on virtual addresses (really: offsets
> >> into the direct map). It hence would better not have any bits set outside
> >> of the range that VAs can cover.
> > 
> > It's confusing that it's sometimes used against a paddr_t or an
> > unsigned long type.  The logic itself already limits the shift so it's
> > below the width of unsigned long AFAICT.
> 
> Well, the variable simply doesn't need to be wider than the narrowest type
> it's used with.
> 
> >> With that, imo the cast (if any) also
> >> should have been to unsigned long, not paddr_t. Yet as said, im the cast
> >> would better not be there in the first place. Just that meanwhile I've
> >> learned that this was committed already.
> > 
> > Sorry, I should have waited for your opinion.
> > 
> > I think you would prefer the patch below.
> 
> Yes.
> 
> >  I can send this formally,
> > not sure whether you would prefer a formal revert of the previous
> > patch, plus the new fix applied, or doing the revert in the new patc
> > (like below) is fine.
> 
> Acked-by: Jan Beulich 
> 
> I don't see a strong need for an outright revert.

I've adjusted UL -> L as requested by Andrew, and added the following
commit message:

tests/pdx: define PAGE_SIZE as long

Otherwise Coverity complains about possibly shifting an integer more than
31 bits.

This also reverts the previous attempt to fix this Coverity reported
issue, commit 4dd323029094d93dbc8d174fe744fd7f54f0a7a4.

Suggested-by: Jan Beulich 
Coverity ID: 1662707
Fixes: cb50e4033717 ('test/pdx: add PDX compression unit tests')
Signed-off-by: Roger Pau Monné 
Acked-by: Jan Beulich 

Let me know if you are OK with the adjustment and commit message.

Thanks, Roger.


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Subject: Re: [PATCH 18/22] x86/traps: Set MSR_PL0_SSP in load_system_tables()
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
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On 08.08.2025 22:23, Andrew Cooper wrote:
> FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
> means that the value they load into MSR_PL0_SSP differs by 8.
> 
> s3_resume() in particular has logic which is otherwise invariant of FRED mode,
> and must not clobber a FRED MSR_PL0_SSP with an IDT one.
> 
> This also simplifies the AP path too.  Updating reinit_bsp_stack() is deferred
> until later.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

I wonder why this was originally done in assembly in the first place, when
we aim at reducing tghe assembly code we have.

> --- a/xen/arch/x86/boot/x86_64.S
> +++ b/xen/arch/x86/boot/x86_64.S
> @@ -65,17 +65,11 @@ ENTRY(__high_start)
>          or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %rdx
>  
>          /*
> -         * Write a new supervisor token.  Doesn't matter on boot, but for S3
> -         * resume this clears the busy bit.
> +         * Write a new Supervisor Token.  It doesn't matter the first time a
> +         * CPU boots, but for S3 resume or CPU hot re-add, this clears the
> +         * busy bit.
>           */
>          wrssq   %rdx, (%rdx)
> -
> -        /* Point MSR_PL0_SSP at the token. */
> -        mov     $MSR_PL0_SSP, %ecx
> -        mov     %edx, %eax
> -        shr     $32, %rdx
> -        wrmsr
> -
>          setssbsy

This is ending up a little odd: The comment says the write is to clear the
busy bit, when that's re-set immediately afterwards.

Jan


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Subject: Re: [PATCH] pdx: cast PAGE_SIZE value ahead of shifting
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: <20250813125538.78174-1-roger.pau@citrix.com>
 
 
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On 14.08.2025 16:57, Roger Pau Monné wrote:
> I've adjusted UL -> L as requested by Andrew, and added the following
> commit message:
> 
> tests/pdx: define PAGE_SIZE as long
> 
> Otherwise Coverity complains about possibly shifting an integer more than
> 31 bits.
> 
> This also reverts the previous attempt to fix this Coverity reported
> issue, commit 4dd323029094d93dbc8d174fe744fd7f54f0a7a4.
> 
> Suggested-by: Jan Beulich 
> Coverity ID: 1662707
> Fixes: cb50e4033717 ('test/pdx: add PDX compression unit tests')
> Signed-off-by: Roger Pau Monné 
> Acked-by: Jan Beulich 
> 
> Let me know if you are OK with the adjustment and commit message.

Fine with me.

Jan


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On 14/08/2025 2:12 pm, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> @@ -42,17 +46,76 @@ struct cpu_user_regs
>>       */
>>  
>>      union { uint64_t rip;    uint32_t eip;    uint16_t ip; };
>> -    uint16_t cs, _pad0[1];
>> -    uint8_t  saved_upcall_mask; /* PV (v)rflags.IF == !saved_upcall_mask */
>> -    uint8_t  _pad1[3];
>> +    union {
>> +        struct {
>> +            uint16_t      cs;
>> +            unsigned long :16;
>> +            uint8_t       saved_upcall_mask; /* PV (v)rflags.IF == !saved_upcall_mask */
> Would this better be reproduced ...
>
>> +        };
>> +        unsigned long     csx;
>> +        struct {
>> +            /*
>> +             * Bits 0 thru 31 control ERET{U,S} behaviour, and is state of the
>> +             * interrupted context.
>> +             */
>> +            uint16_t      cs;
>> +            unsigned int  sl:2;      /* Stack Level */
>> +            bool          wfe:1;     /* Wait-for-ENDBRANCH state */
> ... here as well, just like you reproduce "cs"?

saved_upcall_mask is a property of an in-guest IRET frame only.  It is
only produced in create_bounce_frame, and never consumed by Xen.

It needs to exist in this structure so asm-offsets.c can generate a
constant.

Also, be aware that there are new features being planned which rely on FRED.

>
>> +        } fred_cs;
>> +    };
>>      union { uint64_t rflags; uint32_t eflags; uint16_t flags; };
>>      union { uint64_t rsp;    uint32_t esp;    uint16_t sp;    uint8_t spl; };
>> -    uint16_t ss, _pad2[3];
>> +    union {
>> +        uint16_t          ss;
>> +        unsigned long     ssx;
> What use do you foresee for this and "csx"?

That also came from Linux.  I'm using it to zero the control metadata so
ERETU behaves more like IRET.

>
>> +        struct {
>> +            /*
>> +             * Bits 0 thru 31 control ERET{U,S} behaviour, and is state about
>> +             * the event which occured.
>> +             */
>> +            uint16_t      ss;
>> +            bool          sti:1;     /* Was blocked-by-STI, and not cancelled */
>> +            bool          swint:1;   /* Was a SYSCALL/SYSENTER/INT $N */
>> +            bool          nmi:1;     /* Was an NMI. */
>> +            unsigned long :13;
>> +
>> +            /*
>> +             * Bits 32 thru 63 are ignored by ERET{U,S} and are informative
>> +             * only.
>> +             */
>> +            uint8_t       vector;
>> +            unsigned long :8;
>> +            unsigned int  type:4;    /* X86_ET_* */
>> +            unsigned long :4;
>> +            bool          enclave:1; /* Event taken in SGX mode */
>> +            bool          lm:1;      /* Was in Long Mode */
> The bit indicates 64-bit mode aiui, not long mode (without which FRED isn't even
> available).

Oh, yes.  This is something that changed across revisions, and I wrote
this patch to an older spec.

It's %cs.l of the interrupted context, so I probably should just drop the m.

>
>> --- a/xen/arch/x86/include/asm/current.h
>> +++ b/xen/arch/x86/include/asm/current.h
>> @@ -38,6 +38,8 @@ struct vcpu;
>>  
>>  struct cpu_info {
>>      struct cpu_user_regs guest_cpu_user_regs;
>> +    struct fred_info _fred; /* Only used when FRED is active. */
> Any particular need for the leading underscore?

Somewhat, yes.  It's not safe to reference this field, except for
loading MSR_PL0_RSP.

Everyone else should use cpu_regs_fred_info() to get the fred_info,
which has a safety ASSERT().

~Andrew


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Date: Thu, 14 Aug 2025 17:09:52 +0200
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From: Oleksii Kurochko 
Subject: Re: [PATCH v3 13/20] xen/riscv: Implement p2m_free_subtree() and
 related helpers
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <41845723a7b0e3efd09095d13e57aace6f7747ef.1753973161.git.oleksii.kurochko@gmail.com>
 <98dc796e-bb14-435e-8c19-53e5de60cc43@suse.com>
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In-Reply-To: <98dc796e-bb14-435e-8c19-53e5de60cc43@suse.com>

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On 8/6/25 5:55 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> --- a/xen/arch/riscv/include/asm/p2m.h
>> +++ b/xen/arch/riscv/include/asm/p2m.h
>> @@ -79,10 +79,20 @@ typedef enum {
>>       p2m_ext_storage,    /* Following types'll be stored outsude PTE bits: */
>>       p2m_grant_map_rw,   /* Read/write grant mapping */
>>       p2m_grant_map_ro,   /* Read-only grant mapping */
>> +    p2m_map_foreign_rw, /* Read/write RAM pages from foreign domain */
>> +    p2m_map_foreign_ro, /* Read-only RAM pages from foreign domain */
>>   } p2m_type_t;
>>   
>>   #define p2m_mmio_direct p2m_mmio_direct_io
>>   
>> +/*
>> + * Bits 8 and 9 are reserved for use by supervisor software;
>> + * the implementation shall ignore this field.
>> + * We are going to use to save in these bits frequently used types to avoid
>> + * get/set of a type from radix tree.
>> + */
>> +#define P2M_TYPE_PTE_BITS_MASK  0x300
>> +
>>   /* We use bitmaps and mask to handle groups of types */
>>   #define p2m_to_mask(t_) BIT(t_, UL)
>>   
>> @@ -93,10 +103,16 @@ typedef enum {
>>   #define P2M_GRANT_TYPES (p2m_to_mask(p2m_grant_map_rw) | \
>>                            p2m_to_mask(p2m_grant_map_ro))
>>   
>> +                            /* Foreign mappings types */
> Nit: Why so far to the right?
>
>> --- a/xen/arch/riscv/p2m.c
>> +++ b/xen/arch/riscv/p2m.c
>> @@ -197,6 +197,16 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
>>       return __map_domain_page(p2m->root + root_table_indx);
>>   }
>>   
>> +static p2m_type_t p2m_get_type(const pte_t pte)
>> +{
>> +    p2m_type_t type = MASK_EXTR(pte.pte, P2M_TYPE_PTE_BITS_MASK);
>> +
>> +    if ( type == p2m_ext_storage )
>> +        panic("unimplemented\n");
> That is, as per p2m.h additions you pretend to add support for foreign types
> here, but then you don't?

I count foreign types as p2m_ext_storage type, so a support for them will be added in the patch
[1] of this patch series as a type for p2m_ext_storage type will stored in metadata
due to the lack of free bits in PTE.

[1]https://lore.kernel.org/xen-devel/cover.1753973161.git.oleksii.kurochko@gmail.com/T/#mcc1a0367fdbfbf3ca073f152efa799c1a4354974

>> @@ -248,11 +258,136 @@ static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl,
>>       return P2M_TABLE_MAP_NONE;
>>   }
>>   
>> +static void p2m_put_foreign_page(struct page_info *pg)
>> +{
>> +    /*
>> +     * It’s safe to call put_page() here because arch_flush_tlb_mask()
>> +     * will be invoked if the page is reallocated before the end of
>> +     * this loop, which will trigger a flush of the guest TLBs.
>> +     */
>> +    put_page(pg);
>> +}
> How can one know the comment is true? arch_flush_tlb_mask() still lives in
> stubs.c, and hence what it is eventually going to do (something like Arm's
> vs more like x86'es) is entirely unknown right now.

I'll introduce arch_flush_tlb_mask() in this patch in the next version.

>> +/* Put any references on the single 4K page referenced by mfn. */
>> +static void p2m_put_4k_page(mfn_t mfn, p2m_type_t type)
>> +{
>> +    /* TODO: Handle other p2m types */
>> +
>> +    if ( p2m_is_foreign(type) )
>> +    {
>> +        ASSERT(mfn_valid(mfn));
>> +        p2m_put_foreign_page(mfn_to_page(mfn));
>> +    }
>> +
>> +    /*
>> +     * Detect the xenheap page and mark the stored GFN as invalid.
>> +     * We don't free the underlying page until the guest requested to do so.
>> +     * So we only need to tell the page is not mapped anymore in the P2M by
>> +     * marking the stored GFN as invalid.
>> +     */
>> +    if ( p2m_is_ram(type) && is_xen_heap_mfn(mfn) )
>> +        page_set_xenheap_gfn(mfn_to_page(mfn), INVALID_GFN);
> Isn't this for grants? p2m_is_ram() doesn't cover p2m_grant_map_*.

p2m_is_ram() looks really unnecessary here. I'm thinking if it could be useful
to store for RAM types GFNs too to have something like M2P.

>> +}
>> +
>> +/* Put any references on the superpage referenced by mfn. */
>> +static void p2m_put_2m_superpage(mfn_t mfn, p2m_type_t type)
>> +{
>> +    struct page_info *pg;
>> +    unsigned int i;
>> +
>> +    ASSERT(mfn_valid(mfn));
>> +
>> +    pg = mfn_to_page(mfn);
>> +
>> +    for ( i = 0; i < XEN_PT_ENTRIES; i++, pg++ )
>> +        p2m_put_foreign_page(pg);
>> +}
> In p2m_put_4k_page() you check the type, whereas here you don't.

Missed to add that:
       if ( !p2m_is_foreign(type) )
         return;

>> +/* Put any references on the page referenced by pte. */
>> +static void p2m_put_page(const pte_t pte, unsigned int level)
>> +{
>> +    mfn_t mfn = pte_get_mfn(pte);
>> +    p2m_type_t p2m_type = p2m_get_type(pte);
>> +
>> +    ASSERT(pte_is_valid(pte));
>> +
>> +    /*
>> +     * TODO: Currently we don't handle level 2 super-page, Xen is not
>> +     * preemptible and therefore some work is needed to handle such
>> +     * superpages, for which at some point Xen might end up freeing memory
>> +     * and therefore for such a big mapping it could end up in a very long
>> +     * operation.
>> +     */
>> +    switch ( level )
>> +    {
>> +    case 1:
>> +        return p2m_put_2m_superpage(mfn, p2m_type);
>> +
>> +    case 0:
>> +        return p2m_put_4k_page(mfn, p2m_type);
>> +    }
> Yet despite the comment not even an assertion for level 2 and up?

Not sure that an ASSERT() is needed here as a reference(s) for such page(s)
will be put during domain_relinquish_resources() as there we could do preemption.
Something like Arm does here:
   https://gitlab.com/xen-project/people/olkur/xen/-/blob/staging/xen/arch/arm/mmu/p2m.c?ref_type=heads#L1587

I'm thinking that probably it makes sense to put only 4k page(s) and
all other cases postpone until domain_relinquish_resources() is called.

>>   /* Free pte sub-tree behind an entry */
>>   static void p2m_free_subtree(struct p2m_domain *p2m,
>>                                pte_t entry, unsigned int level)
>>   {
>> -    panic("%s: hasn't been implemented yet\n", __func__);
>> +    unsigned int i;
>> +    pte_t *table;
>> +    mfn_t mfn;
>> +    struct page_info *pg;
>> +
>> +    /* Nothing to do if the entry is invalid. */
>> +    if ( !pte_is_valid(entry) )
>> +        return;
>> +
>> +    if ( pte_is_superpage(entry, level) || (level == 0) )
> Perhaps swap the two conditions around?
>
>> +    {
>> +#ifdef CONFIG_IOREQ_SERVER
>> +        /*
>> +         * If this gets called then either the entry was replaced by an entry
>> +         * with a different base (valid case) or the shattering of a superpage
>> +         * has failed (error case).
>> +         * So, at worst, the spurious mapcache invalidation might be sent.
>> +         */
>> +        if ( p2m_is_ram(p2m_get_type(p2m, entry)) &&
>> +             domain_has_ioreq_server(p2m->domain) )
>> +            ioreq_request_mapcache_invalidate(p2m->domain);
>> +#endif
>> +
>> +        p2m_put_page(entry, level);
>> +
>> +        return;
>> +    }
>> +
>> +    table = map_domain_page(pte_get_mfn(entry));
>> +    for ( i = 0; i < XEN_PT_ENTRIES; i++ )
>> +        p2m_free_subtree(p2m, table[i], level - 1);
> In p2m_put_page() you comment towards concerns for level >= 2; no similar
> concerns for the resulting recursion here?

This function is generic enough to handle any level.

Except that it is possible that it will be needed, for example, to split 1G mapping
into something smaller then p2m_free_subtree() could be called for freeing a subtree
of 1gb mapping.

>> +    unmap_domain_page(table);
>> +
>> +    /*
>> +     * Make sure all the references in the TLB have been removed before
>> +     * freing the intermediate page table.
>> +     * XXX: Should we defer the free of the page table to avoid the
>> +     * flush?
>> +     */
>> +    p2m_tlb_flush_sync(p2m);
>> +
>> +    mfn = pte_get_mfn(entry);
>> +    ASSERT(mfn_valid(mfn));
>> +
>> +    pg = mfn_to_page(mfn);
>> +
>> +    page_list_del(pg, &p2m->pages);
>> +    p2m_free_page(p2m, pg);
> Once again I wonder whether this code path was actually tested: p2m_free_page()
> also invokes page_list_del(), and double deletions typically won't end very
> well.

Agree, it should be dropped here and left only in p2m_free_page().

It should be tested, I have a test case where I'm chaning MFN so this one should be called:
+    /*
+     * Free the entry only if the original pte was valid and the base
+     * is different (to avoid freeing when permission is changed).
+     */
+    if ( pte_is_valid(orig_pte) &&
+         !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) )
+        p2m_free_subtree(p2m, orig_pte, level);

I will double check.

But I think I was lucky because I've tested only the whole patch series and in one of a
further patches page_list_del(pg, &p2m->pages) is dropped.

~ Oleksii

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    On 8/6/25 5:55 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    --- a/xen/arch/riscv/include/asm/p2m.h
+++ b/xen/arch/riscv/include/asm/p2m.h
@@ -79,10 +79,20 @@ typedef enum {
     p2m_ext_storage,    /* Following types'll be stored outsude PTE bits: */
     p2m_grant_map_rw,   /* Read/write grant mapping */
     p2m_grant_map_ro,   /* Read-only grant mapping */
+    p2m_map_foreign_rw, /* Read/write RAM pages from foreign domain */
+    p2m_map_foreign_ro, /* Read-only RAM pages from foreign domain */
 } p2m_type_t;
 
 #define p2m_mmio_direct p2m_mmio_direct_io
 
+/*
+ * Bits 8 and 9 are reserved for use by supervisor software;
+ * the implementation shall ignore this field.
+ * We are going to use to save in these bits frequently used types to avoid
+ * get/set of a type from radix tree.
+ */
+#define P2M_TYPE_PTE_BITS_MASK  0x300
+
 /* We use bitmaps and mask to handle groups of types */
 #define p2m_to_mask(t_) BIT(t_, UL)
 
@@ -93,10 +103,16 @@ typedef enum {
 #define P2M_GRANT_TYPES (p2m_to_mask(p2m_grant_map_rw) | \
                          p2m_to_mask(p2m_grant_map_ro))
 
+                            /* Foreign mappings types */

    
      
    
      
    Nit: Why so far to the right?


    
      
    
        
    --- a/xen/arch/riscv/p2m.c
+++ b/xen/arch/riscv/p2m.c
@@ -197,6 +197,16 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
     return __map_domain_page(p2m->root + root_table_indx);
 }
 
+static p2m_type_t p2m_get_type(const pte_t pte)
+{
+    p2m_type_t type = MASK_EXTR(pte.pte, P2M_TYPE_PTE_BITS_MASK);
+
+    if ( type == p2m_ext_storage )
+        panic("unimplemented\n");

    
      
    
      
    That is, as per p2m.h additions you pretend to add support for foreign types
here, but then you don't?
    
    
    
    
    I count foreign types as p2m_ext_storage type, so a support for them will be added in the patch
[1] of this patch series as a type for p2m_ext_storage type will stored in metadata
due to the lack of free bits in PTE.

[1] https://lore.kernel.org/xen-devel/cover.1753973161.git.oleksii.kurochko@gmail.com/T/#mcc1a0367fdbfbf3ca073f152efa799c1a4354974

    
    
    
      
    
        
    @@ -248,11 +258,136 @@ static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl,
     return P2M_TABLE_MAP_NONE;
 }
 
+static void p2m_put_foreign_page(struct page_info *pg)
+{
+    /*
+     * It’s safe to call put_page() here because arch_flush_tlb_mask()
+     * will be invoked if the page is reallocated before the end of
+     * this loop, which will trigger a flush of the guest TLBs.
+     */
+    put_page(pg);
+}

    
      
    
      
    How can one know the comment is true? arch_flush_tlb_mask() still lives in
stubs.c, and hence what it is eventually going to do (something like Arm's
vs more like x86'es) is entirely unknown right now.
    
    
    
    
    I'll introduce arch_flush_tlb_mask() in this patch in the next version.


    
    
    
      
    
        
    +/* Put any references on the single 4K page referenced by mfn. */
+static void p2m_put_4k_page(mfn_t mfn, p2m_type_t type)
+{
+    /* TODO: Handle other p2m types */
+
+    if ( p2m_is_foreign(type) )
+    {
+        ASSERT(mfn_valid(mfn));
+        p2m_put_foreign_page(mfn_to_page(mfn));
+    }
+
+    /*
+     * Detect the xenheap page and mark the stored GFN as invalid.
+     * We don't free the underlying page until the guest requested to do so.
+     * So we only need to tell the page is not mapped anymore in the P2M by
+     * marking the stored GFN as invalid.
+     */
+    if ( p2m_is_ram(type) && is_xen_heap_mfn(mfn) )
+        page_set_xenheap_gfn(mfn_to_page(mfn), INVALID_GFN);

    
      
    
      
    Isn't this for grants? p2m_is_ram() doesn't cover p2m_grant_map_*.
    
    
    
    
    p2m_is_ram() looks really unnecessary here. I'm thinking if it could be useful
to store for RAM types GFNs too to have something like M2P.

    
    
    
      
    
        
    +}
+
+/* Put any references on the superpage referenced by mfn. */
+static void p2m_put_2m_superpage(mfn_t mfn, p2m_type_t type)
+{
+    struct page_info *pg;
+    unsigned int i;
+
+    ASSERT(mfn_valid(mfn));
+
+    pg = mfn_to_page(mfn);
+
+    for ( i = 0; i < XEN_PT_ENTRIES; i++, pg++ )
+        p2m_put_foreign_page(pg);
+}

    
      
    
      
    In p2m_put_4k_page() you check the type, whereas here you don't.
    
    
    
    
    Missed to add that:
      if ( !p2m_is_foreign(type) )
        return;


    
    
    
      
    
        
    +/* Put any references on the page referenced by pte. */
+static void p2m_put_page(const pte_t pte, unsigned int level)
+{
+    mfn_t mfn = pte_get_mfn(pte);
+    p2m_type_t p2m_type = p2m_get_type(pte);
+
+    ASSERT(pte_is_valid(pte));
+
+    /*
+     * TODO: Currently we don't handle level 2 super-page, Xen is not
+     * preemptible and therefore some work is needed to handle such
+     * superpages, for which at some point Xen might end up freeing memory
+     * and therefore for such a big mapping it could end up in a very long
+     * operation.
+     */
+    switch ( level )
+    {
+    case 1:
+        return p2m_put_2m_superpage(mfn, p2m_type);
+
+    case 0:
+        return p2m_put_4k_page(mfn, p2m_type);
+    }

    
      
    
      
    Yet despite the comment not even an assertion for level 2 and up?
    
    
    
    
    Not sure that an ASSERT() is needed here as a reference(s) for such page(s)
will be put during domain_relinquish_resources() as there we could do preemption.
Something like Arm does here:
  https://gitlab.com/xen-project/people/olkur/xen/-/blob/staging/xen/arch/arm/mmu/p2m.c?ref_type=heads#L1587

I'm thinking that probably it makes sense to put only 4k page(s) and
all other cases postpone until domain_relinquish_resources() is called.


    
    
    
      
    
        
     /* Free pte sub-tree behind an entry */
 static void p2m_free_subtree(struct p2m_domain *p2m,
                              pte_t entry, unsigned int level)
 {
-    panic("%s: hasn't been implemented yet\n", __func__);
+    unsigned int i;
+    pte_t *table;
+    mfn_t mfn;
+    struct page_info *pg;
+
+    /* Nothing to do if the entry is invalid. */
+    if ( !pte_is_valid(entry) )
+        return;
+
+    if ( pte_is_superpage(entry, level) || (level == 0) )

    
      
    
      
    Perhaps swap the two conditions around?


    
      
    
        
    +    {
+#ifdef CONFIG_IOREQ_SERVER
+        /*
+         * If this gets called then either the entry was replaced by an entry
+         * with a different base (valid case) or the shattering of a superpage
+         * has failed (error case).
+         * So, at worst, the spurious mapcache invalidation might be sent.
+         */
+        if ( p2m_is_ram(p2m_get_type(p2m, entry)) &&
+             domain_has_ioreq_server(p2m->domain) )
+            ioreq_request_mapcache_invalidate(p2m->domain);
+#endif
+
+        p2m_put_page(entry, level);
+
+        return;
+    }
+
+    table = map_domain_page(pte_get_mfn(entry));
+    for ( i = 0; i < XEN_PT_ENTRIES; i++ )
+        p2m_free_subtree(p2m, table[i], level - 1);

    
      
    
      
    In p2m_put_page() you comment towards concerns for level >= 2; no similar
concerns for the resulting recursion here?
    
    
    
    
    This function is generic enough to handle any level.

Except that it is possible that it will be needed, for example, to split 1G mapping
into something smaller then p2m_free_subtree() could be called for freeing a subtree
of 1gb mapping.


    
    
    
      
    
        
    +    unmap_domain_page(table);
+
+    /*
+     * Make sure all the references in the TLB have been removed before
+     * freing the intermediate page table.
+     * XXX: Should we defer the free of the page table to avoid the
+     * flush?
+     */
+    p2m_tlb_flush_sync(p2m);
+
+    mfn = pte_get_mfn(entry);
+    ASSERT(mfn_valid(mfn));
+
+    pg = mfn_to_page(mfn);
+
+    page_list_del(pg, &p2m->pages);
+    p2m_free_page(p2m, pg);

    
      
    
      
    Once again I wonder whether this code path was actually tested: p2m_free_page()
also invokes page_list_del(), and double deletions typically won't end very
well.
    
    
    
    
    Agree, it should be dropped here and left only in p2m_free_page().

It should be tested, I have a test case where I'm chaning MFN so this one should be called:
+    /*
+     * Free the entry only if the original pte was valid and the base
+     * is different (to avoid freeing when permission is changed).
+     */
+    if ( pte_is_valid(orig_pte) &&
+         !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) )
+        p2m_free_subtree(p2m, orig_pte, level);

I will double check.

But I think I was lucky because I've tested only the whole patch series and in one of a
further patches page_list_del(pg, &p2m->pages) is dropped.

~ Oleksii
    
  


--------------vYx2KQ1Dkw3zffA1AKgYiN5b--


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Subject: Re: [PATCH 19/22] x86/boot: Use RSTORSSP to establish SSP
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 08.08.2025 22:23, Andrew Cooper wrote:
> Under FRED, SETSSBSY is unavailable, and we want to be setting up FRED prior
> to setting up shadow stacks.  As we still need Supervisor Tokens in IDT mode,
> we need mode-specific logic to establish SSP.
> 
> In FRED mode, write a Restore Token, RSTORSSP it, and discard the resulting
> Previous-SSP token.
> 
> No change outside of FRED mode.
> 
> Signed-off-by: Andrew Cooper 

Why is it that in patch 17 you could use identical code, but here you can't?

> @@ -912,10 +913,30 @@ static void __init noreturn reinit_bsp_stack(void)
>  
>      if ( cpu_has_xen_shstk )
>      {
> -        wrmsrl(MSR_PL0_SSP,
> -               (unsigned long)stack + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8);

Does this removal perhaps belong elsewhere, especially with "No change
outside of FRED mode" in the description?

Jan


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Subject: Re: [PATCH v3 13/20] xen/riscv: Implement p2m_free_subtree() and
 related helpers
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
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On 14.08.2025 17:09, Oleksii Kurochko wrote:
> On 8/6/25 5:55 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> +/* Put any references on the page referenced by pte. */
>>> +static void p2m_put_page(const pte_t pte, unsigned int level)
>>> +{
>>> +    mfn_t mfn = pte_get_mfn(pte);
>>> +    p2m_type_t p2m_type = p2m_get_type(pte);
>>> +
>>> +    ASSERT(pte_is_valid(pte));
>>> +
>>> +    /*
>>> +     * TODO: Currently we don't handle level 2 super-page, Xen is not
>>> +     * preemptible and therefore some work is needed to handle such
>>> +     * superpages, for which at some point Xen might end up freeing memory
>>> +     * and therefore for such a big mapping it could end up in a very long
>>> +     * operation.
>>> +     */
>>> +    switch ( level )
>>> +    {
>>> +    case 1:
>>> +        return p2m_put_2m_superpage(mfn, p2m_type);
>>> +
>>> +    case 0:
>>> +        return p2m_put_4k_page(mfn, p2m_type);
>>> +    }
>> Yet despite the comment not even an assertion for level 2 and up?
> 
> Not sure that an ASSERT() is needed here as a reference(s) for such page(s)
> will be put during domain_relinquish_resources() as there we could do preemption.
> Something like Arm does here:
>    https://gitlab.com/xen-project/people/olkur/xen/-/blob/staging/xen/arch/arm/mmu/p2m.c?ref_type=heads#L1587
> 
> I'm thinking that probably it makes sense to put only 4k page(s) and
> all other cases postpone until domain_relinquish_resources() is called.

How can you defer to domain cleanup? How would handling of foreign mappings
(or e.g. ballooning? not sure) work when you don't drop references as
necessary?

>>>   /* Free pte sub-tree behind an entry */
>>>   static void p2m_free_subtree(struct p2m_domain *p2m,
>>>                                pte_t entry, unsigned int level)
>>>   {
>>> -    panic("%s: hasn't been implemented yet\n", __func__);
>>> +    unsigned int i;
>>> +    pte_t *table;
>>> +    mfn_t mfn;
>>> +    struct page_info *pg;
>>> +
>>> +    /* Nothing to do if the entry is invalid. */
>>> +    if ( !pte_is_valid(entry) )
>>> +        return;
>>> +
>>> +    if ( pte_is_superpage(entry, level) || (level == 0) )
>> Perhaps swap the two conditions around?
>>
>>> +    {
>>> +#ifdef CONFIG_IOREQ_SERVER
>>> +        /*
>>> +         * If this gets called then either the entry was replaced by an entry
>>> +         * with a different base (valid case) or the shattering of a superpage
>>> +         * has failed (error case).
>>> +         * So, at worst, the spurious mapcache invalidation might be sent.
>>> +         */
>>> +        if ( p2m_is_ram(p2m_get_type(p2m, entry)) &&
>>> +             domain_has_ioreq_server(p2m->domain) )
>>> +            ioreq_request_mapcache_invalidate(p2m->domain);
>>> +#endif
>>> +
>>> +        p2m_put_page(entry, level);
>>> +
>>> +        return;
>>> +    }
>>> +
>>> +    table = map_domain_page(pte_get_mfn(entry));
>>> +    for ( i = 0; i < XEN_PT_ENTRIES; i++ )
>>> +        p2m_free_subtree(p2m, table[i], level - 1);
>> In p2m_put_page() you comment towards concerns for level >= 2; no similar
>> concerns for the resulting recursion here?
> 
> This function is generic enough to handle any level.
> 
> Except that it is possible that it will be needed, for example, to split 1G mapping
> into something smaller then p2m_free_subtree() could be called for freeing a subtree
> of 1gb mapping.

The question wasn't about it being generic enough, but it possibly taking
too much time for level >= 2.

Jan


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Subject: Re: [PATCH 20/22] x86/traps: Alter switch_stack_and_jump() for FRED
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To: Andrew Cooper 
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On 08.08.2025 22:23, Andrew Cooper wrote:
> FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
> means that switch_stack_and_jump() needs to discard one extra word when FRED
> is active.
> 
> Signed-off-by: Andrew Cooper 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
> 
> RFC.  I don't like this, but it does work.
> 
> This emits opt_fred logic outside of CONFIG_XEN_SHSTK.

opt_fred and XEN_SHSTK are orthogonal, so that's fine anyway. What I guess
you may mean is that you now have a shstk-related calculation outside of
a respective #ifdef. Given the simplicity of the calculation, ...

>  But frankly, the
> construct is already too unweildly, and all options I can think of make it
> moreso.

... I agree having it like this is okay.

> @@ -154,7 +155,6 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>      "rdsspd %[ssp];"                                            \
>      "cmp $1, %[ssp];"                                           \
>      "je .L_shstk_done.%=;" /* CET not active?  Skip. */         \
> -    "mov $%c[skstk_base], %[val];"                              \
>      "and $%c[stack_mask], %[ssp];"                              \
>      "sub %[ssp], %[val];"                                       \
>      "shr $3, %[val];"                                           \

With the latter two insns here, ...

> @@ -177,6 +177,8 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>  
>  #define switch_stack_and_jump(fn, instr, constr)                        \
>      ({                                                                  \
> +        unsigned int token_offset =                                     \
> +            (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - (opt_fred ? 0 : 8);  \
>          unsigned int tmp;                                               \
>          BUILD_BUG_ON(!ssaj_has_attr_noreturn(fn));                      \
>          __asm__ __volatile__ (                                          \
> @@ -184,12 +186,11 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>              "mov %[stk], %%rsp;"                                        \
>              CHECK_FOR_LIVEPATCH_WORK                                    \
>              instr "[fun]"                                               \
> -            : [val] "=&r" (tmp),                                        \
> +            : [val] "=r" (tmp),                                         \

... I don't think you can legitimately drop the & from here? With it
retained:
Reviewed-by: Jan Beulich 

Jan


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Date: Thu, 14 Aug 2025 17:57:38 +0200
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Subject: Re: [PATCH 21/22] x86/traps: Introduce FRED entrypoints
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-22-andrew.cooper3@citrix.com>
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On 08.08.2025 22:23, Andrew Cooper wrote:
> --- a/xen/arch/x86/include/asm/asm_defns.h
> +++ b/xen/arch/x86/include/asm/asm_defns.h
> @@ -315,6 +315,71 @@ static always_inline void stac(void)
>          subq  $-(UREGS_error_code-UREGS_r15+\adj), %rsp
>  .endm
>  
> +/*
> + * Push and clear GPRs
> + */
> +.macro PUSH_AND_CLEAR_GPRS
> +        push  %rdi
> +        xor   %edi, %edi
> +        push  %rsi
> +        xor   %esi, %esi
> +        push  %rdx
> +        xor   %edx, %edx
> +        push  %rcx
> +        xor   %ecx, %ecx
> +        push  %rax
> +        xor   %eax, %eax
> +        push  %r8
> +        xor   %r8d, %r8d
> +        push  %r9
> +        xor   %r9d, %r9d
> +        push  %r10
> +        xor   %r10d, %r10d
> +        push  %r11
> +        xor   %r11d, %r11d
> +        push  %rbx
> +        xor   %ebx, %ebx
> +        push  %rbp
> +#ifdef CONFIG_FRAME_POINTER
> +/* Indicate special exception stack frame by inverting the frame pointer. */
> +        mov   %rsp, %rbp
> +        notq  %rbp
> +#else
> +        xor   %ebp, %ebp
> +#endif
> +        push  %r12
> +        xor   %r12d, %r12d
> +        push  %r13
> +        xor   %r13d, %r13d
> +        push  %r14
> +        xor   %r14d, %r14d
> +        push  %r15
> +        xor   %r15d, %r15d
> +.endm
> +
> +/*
> + * POP GPRs from a UREGS_* frame on the stack.  Does not modify flags.
> + *
> + * @rax: Alternative destination for the %rax value on the stack.
> + */
> +.macro POP_GPRS rax=%rax
> +        pop   %r15
> +        pop   %r14
> +        pop   %r13
> +        pop   %r12
> +        pop   %rbp
> +        pop   %rbx
> +        pop   %r11
> +        pop   %r10
> +        pop   %r9
> +        pop   %r8
> +        pop   \rax
> +        pop   %rcx
> +        pop   %rdx
> +        pop   %rsi
> +        pop   %rdi
> +.endm

Hmm, yes, differences are apparently large enough to warrant the redundancy
with SAVE_ALL / RESTORE_ALL.

> --- a/xen/arch/x86/include/asm/msr.h
> +++ b/xen/arch/x86/include/asm/msr.h
> @@ -202,9 +202,9 @@ static inline unsigned long read_gs_base(void)
>  
>  static inline unsigned long read_gs_shadow(void)
>  {
> -    unsigned long base;
> +    unsigned long base, cr4 = read_cr4();
>  
> -    if ( read_cr4() & X86_CR4_FSGSBASE )
> +    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
>      {
>          asm volatile ( "swapgs" );
>          base = __rdgsbase();
> @@ -234,7 +234,9 @@ static inline void write_gs_base(unsigned long base)
>  
>  static inline void write_gs_shadow(unsigned long base)
>  {
> -    if ( read_cr4() & X86_CR4_FSGSBASE )
> +    unsigned long cr4 = read_cr4();
> +
> +    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
>      {
>          asm volatile ( "swapgs\n\t"
>                         "wrgsbase %0\n\t"

I don't quite get how these changes fit into this patch.

> --- a/xen/arch/x86/traps.c
> +++ b/xen/arch/x86/traps.c
> @@ -1013,6 +1013,32 @@ void show_execution_state_nmi(const cpumask_t *mask, bool show_all)
>          printk("Non-responding CPUs: {%*pbl}\n", CPUMASK_PR(&show_state_mask));
>  }
>  
> +static const char *x86_et_name(unsigned int type)
> +{
> +    static const char *const names[] = {
> +        [X86_ET_EXT_INTR]    = "EXT_INTR",
> +        [X86_ET_NMI]         = "NMI",
> +        [X86_ET_HW_EXC]      = "HW_EXC",
> +        [X86_ET_SW_INT]      = "SW_INT",
> +        [X86_ET_PRIV_SW_EXC] = "PRIV_SW_EXEC",
> +        [X86_ET_SW_EXC]      = "SW_EXEC",
> +        [X86_ET_OTHER]       = "OTHER",
> +    };
> +
> +    return (type < ARRAY_SIZE(names) && names[type]) ? names[type] : "???";
> +}
> +
> +static const char *x86_et_other_name(unsigned int vec)

This isn't really a vector, is it?

> +{
> +    static const char *const names[] = {
> +        [0] = "MTF",
> +        [1] = "SYSCALL",
> +        [2] = "SYSENTER",
> +    };
> +
> +    return (vec < ARRAY_SIZE(names) && names[vec][0]) ? names[vec] : "???";

Did you mean to check names[ves] for being NULL? Or is this a leftover
from the array being something like names[][10]?

> --- a/xen/arch/x86/x86_64/Makefile
> +++ b/xen/arch/x86/x86_64/Makefile
> @@ -1,6 +1,7 @@
>  obj-$(CONFIG_PV32) += compat/
>  
>  obj-bin-y += entry.o
> +obj-bin-y += entry-fred.o

For the ordering here, ...

> --- /dev/null
> +++ b/xen/arch/x86/x86_64/entry-fred.S
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +
> +        .file "x86_64/entry-fred.S"
> +
> +#include 
> +#include 
> +
> +        .section .text.entry, "ax", @progbits
> +
> +        /* The Ring3 entry point is required to be 4k aligned. */
> +
> +FUNC(entry_FRED_R3, 4096)

... doesn't this 4k-alignment requirement suggest we want to put
entry-fred.o first? Also, might it be more natural to use PAGE_SIZE
here?

Jan


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From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: stewart.hildebrand@amd.com,
	Jiqian.Chen@amd.com,
	jbeulich@suse.com,
	Roger Pau Monne 
Subject: [PATCH 2/5] xen/vpci: make BAR mapping more resilient for the hardware domain
Date: Thu, 14 Aug 2025 18:03:55 +0200
Message-ID: <20250814160358.95543-3-roger.pau@citrix.com>
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The logic in map_range() will bubble up failures to the upper layer, which
will result in any remaining regions being skip, and for the non-hardware
domain case the owner domain of the device would be destroyed.  However for
the hardware domain the intent is to continue execution, hopping the
failure to modify the p2m could be worked around by the hardware domain.

To accomplish that in a better way, ignore failures and skip the range in
that case, possibly continuing to map further ranges.

Since the error path in vpci_process_pending() should only be used by domUs
now, and it will unconditionally end up calling domain_crash(), simplify
it: there's no need to cleanup if the domain will be destroyed.

No functional change for domUs intended.

Signed-off-by: Roger Pau Monné 
---
 xen/drivers/vpci/header.c | 51 +++++++++++++++++++++------------------
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
index b9756b364300..1035dcca242d 100644
--- a/xen/drivers/vpci/header.c
+++ b/xen/drivers/vpci/header.c
@@ -64,7 +64,8 @@ static int cf_check map_range(
             printk(XENLOG_G_WARNING
                    "%pd denied access to MMIO range [%#lx, %#lx]\n",
                    map->d, map_mfn, m_end);
-            return -EPERM;
+            rc = -EPERM;
+            goto done;
         }
 
         rc = xsm_iomem_mapping(XSM_HOOK, map->d, map_mfn, m_end, map->map);
@@ -73,7 +74,7 @@ static int cf_check map_range(
             printk(XENLOG_G_WARNING
                    "%pd XSM denied access to MMIO range [%#lx, %#lx]: %d\n",
                    map->d, map_mfn, m_end, rc);
-            return rc;
+            goto done;
         }
 
         /*
@@ -87,17 +88,27 @@ static int cf_check map_range(
 
         rc = map->map ? map_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn))
                       : unmap_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn));
-        if ( rc == 0 )
-        {
-            *c += size;
-            break;
-        }
         if ( rc < 0 )
         {
             printk(XENLOG_G_WARNING
                    "Failed to %smap [%lx %lx] -> [%lx %lx] for %pd: %d\n",
                    map->map ? "" : "un", s, e, map_mfn,
                    map_mfn + size, map->d, rc);
+            goto done;
+        }
+        if ( rc == 0 )
+        {
+ done:
+            if ( is_hardware_domain(map->d) )
+            {
+                /*
+                 * Ignore failures for the hardware domain and skip the range.
+                 * Do it as a best effort workaround to attempt to get the
+                 * hardware domain to boot.
+                 */
+                rc = 0;
+                *c += size;
+            }
             break;
         }
         ASSERT(rc < size);
@@ -213,28 +224,22 @@ bool vpci_process_pending(struct vcpu *v)
             return true;
         }
 
-        if ( rc )
+        if ( rc && !is_hardware_domain(v->domain) )
         {
-            spin_lock(&pdev->vpci->lock);
-            /* Disable memory decoding unconditionally on failure. */
-            modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY,
-                            false);
-            spin_unlock(&pdev->vpci->lock);
-
-            /* Clean all the rangesets */
-            for ( i = 0; i < ARRAY_SIZE(header->bars); i++ )
-                if ( !rangeset_is_empty(header->bars[i].mem) )
-                     rangeset_purge(header->bars[i].mem);
-
-            v->vpci.pdev = NULL;
-
             read_unlock(&v->domain->pci_lock);
 
-            if ( !is_hardware_domain(v->domain) )
-                domain_crash(v->domain);
+            domain_crash(v->domain);
 
             return false;
         }
+        ASSERT(!rc);
+        /*
+         * Purge rangeset to deal with the hardware domain having triggered an
+         * error.  It shouldn't be possible, as map_range() will always shallow
+         * errors for hardware domain owned devices, and
+         * rangeset_consume_ranges() itself doesn't generate any errors.
+         */
+        rangeset_purge(bar->mem);
     }
     v->vpci.pdev = NULL;
 
-- 
2.49.0



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From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: stewart.hildebrand@amd.com,
	Jiqian.Chen@amd.com,
	jbeulich@suse.com,
	Roger Pau Monne 
Subject: [PATCH 0/5] xen/vpci: miscellaneous fixes
Date: Thu, 14 Aug 2025 18:03:53 +0200
Message-ID: <20250814160358.95543-1-roger.pau@citrix.com>
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Hello,

The following series started with the report in:

https://lore.kernel.org/xen-devel/dbc003a2-9202-46ec-bf87-2829d8a63d53@citrix.com/

And ended up doing a bit of cleanup on the way.  I think the overall
result is nicer, I never really liked the deferral of the setting of the
command and ROM BAR registers, as it makes the logic much harder to
follow.  I've done some testing, but I will probably do some
specific testing to ensure the error paths work as expected - as I don't
have a system that trigger those.  Posting it ahead because some patches
are fairly trivial, and to get feedback on the approach.

Thanks, Roger.

Roger Pau Monne (5):
  xen/vpci: purge BAR rangeset contents before use
  xen/vpci: make BAR mapping more resilient for the hardware domain
  xen/vpci: simplify handling of memory decoding and ROM enable writes
  vpci/msix: move MSI-X hole punching as a result of memory decoding
    enable
  xen/vpci: only check BAR validity once

 xen/drivers/vpci/header.c | 186 ++++++++++++++++----------------------
 xen/include/xen/vpci.h    |   5 +
 2 files changed, 82 insertions(+), 109 deletions(-)

-- 
2.49.0



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From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: stewart.hildebrand@amd.com,
	Jiqian.Chen@amd.com,
	jbeulich@suse.com,
	Roger Pau Monne 
Subject: [PATCH 3/5] xen/vpci: simplify handling of memory decoding and ROM enable writes
Date: Thu, 14 Aug 2025 18:03:56 +0200
Message-ID: <20250814160358.95543-4-roger.pau@citrix.com>
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Deferring the actual write of the PCI register bit, either the memory
decoding or the ROM enable is not helpful, and adds an unnecessary amount of
complexity to the preemptible handling of BAR related p2m modifications.

In the hardware domain case, whether the PCI register write is done ahead
or after the p2m changes doesn't matter, a hardware domain has plenty of
ways to mess with the PCI register state if it wants to.  Any poking at the
BAR p2m regions ahead of the guest write having completed will be
undefined.

On the other hand, for domUs the memory decoding bit shouldn't really
change as a result of guest actions, and should always be enabled.  Guest
toggling the memory decoding command register should only result in p2m
modifications, but no propagation to the device PCI registers.  Having
memory decoding unconditionally enabled ensures the domU attempting to
perform p2m accesses while the p2m changes are taking place will always
access the BAR contents. This is not the current behavior for domUs, so add
a note that it would preferably done that way.

Signed-off-by: Roger Pau Monné 
---
 xen/drivers/vpci/header.c | 42 +++++++++++++++++++--------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
index 1035dcca242d..1a501a0ba47e 100644
--- a/xen/drivers/vpci/header.c
+++ b/xen/drivers/vpci/header.c
@@ -163,8 +163,6 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd,
             if ( pci_check_bar(pdev, _mfn(PFN_DOWN(bar->addr)),
                                _mfn(PFN_DOWN(bar->addr + bar->size - 1))) )
                 bar->enabled = map;
-            header->rom_enabled = map;
-            pci_conf_write32(pdev->sbdf, rom_pos, val);
             return;
         }
 
@@ -174,14 +172,6 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd,
                            _mfn(PFN_DOWN(bar->addr + bar->size - 1))) )
             bar->enabled = map;
     }
-
-    if ( !rom_only )
-    {
-        pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd);
-        header->bars_mapped = map;
-    }
-    else
-        ASSERT_UNREACHABLE();
 }
 
 bool vpci_process_pending(struct vcpu *v)
@@ -547,16 +537,23 @@ static void cf_check cmd_write(
      * decoding one. Bits that are not allowed for DomU are already
      * handled above and by the rsvdp_mask.
      */
-    if ( header->bars_mapped != !!(cmd & PCI_COMMAND_MEMORY) )
+    if ( header->bars_mapped != !!(cmd & PCI_COMMAND_MEMORY) &&
+         modify_bars(pdev, cmd, false) )
         /*
          * Ignore the error. No memory has been added or removed from the p2m
          * (because the actual p2m changes are deferred in defer_map) and the
          * memory decoding bit has not been changed, so leave everything as-is,
          * hoping the guest will realize and try again.
          */
-        modify_bars(pdev, cmd, false);
-    else
-        pci_conf_write16(pdev->sbdf, reg, cmd);
+        return;
+
+    /*
+     * FIXME: for domUs we don't want the guest toggling the memory decoding
+     * bit.  It should be set in vpci_init_header() and guest attempts to
+     * modify it should only lead to guest p2m changes.
+     */
+    header->bars_mapped = cmd & PCI_COMMAND_MEMORY;
+    pci_conf_write16(pdev->sbdf, reg, cmd);
 }
 
 static uint32_t cf_check guest_cmd_read(
@@ -712,17 +709,11 @@ static void cf_check rom_write(
         rom->guest_addr = rom->addr;
     }
 
-    if ( !header->bars_mapped || rom->enabled == new_enabled )
-    {
-        /* Just update the ROM BAR field. */
-        header->rom_enabled = new_enabled;
-        pci_conf_write32(pdev->sbdf, reg, val);
-    }
     /*
      * Pass PCI_COMMAND_MEMORY or 0 to signal a map/unmap request, note that
      * this fabricated command is never going to be written to the register.
      */
-    else if ( modify_bars(pdev, new_enabled ? PCI_COMMAND_MEMORY : 0, true) )
+    if ( modify_bars(pdev, new_enabled ? PCI_COMMAND_MEMORY : 0, true) )
         /*
          * No memory has been added or removed from the p2m (because the actual
          * p2m changes are deferred in defer_map) and the ROM enable bit has
@@ -733,6 +724,8 @@ static void cf_check rom_write(
          */
         return;
 
+    header->rom_enabled = new_enabled;
+    pci_conf_write32(pdev->sbdf, reg, val);
     if ( !new_enabled )
     {
         rom->addr = val & PCI_ROM_ADDRESS_MASK;
@@ -1057,6 +1050,13 @@ int vpci_init_header(struct pci_dev *pdev)
             goto fail;
     }
 
+    if ( cmd & PCI_COMMAND_MEMORY )
+    {
+        /* Restore command register value. */
+        header->bars_mapped = true;
+        pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd);
+    }
+
     return (cmd & PCI_COMMAND_MEMORY) ? modify_bars(pdev, cmd, false) : 0;
 
  fail:
-- 
2.49.0



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From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: stewart.hildebrand@amd.com,
	Jiqian.Chen@amd.com,
	jbeulich@suse.com,
	Roger Pau Monne ,
	Andrew Cooper 
Subject: [PATCH 5/5] xen/vpci: only check BAR validity once
Date: Thu, 14 Aug 2025 18:03:58 +0200
Message-ID: <20250814160358.95543-6-roger.pau@citrix.com>
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Avoid multiple calls to pci_check_bar() for the same memory decoding
related operation, as each call can possibly print a warning message avoid
a BAR being in an invalid position.

Store whether the BAR is validly positioned in modify_bars(), and used that
cached value for the whole operation.  This allows to get rid of
modify_decoding(), as the setting of whether the BAR is enabled or not can
be easily done in vpci_process_pending() itself, without the need for an
external helper.

Reported-by: Andrew Cooper 
Fixes: 4acab25a9300 ('x86/vpci: fix handling of BAR overlaps with non-hole regions')
Signed-off-by: Roger Pau Monné 
---
 xen/drivers/vpci/header.c | 69 ++++++++++-----------------------------
 xen/include/xen/vpci.h    |  5 +++
 2 files changed, 23 insertions(+), 51 deletions(-)

diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
index 255c6d54b406..2071bed81676 100644
--- a/xen/drivers/vpci/header.c
+++ b/xen/drivers/vpci/header.c
@@ -121,46 +121,6 @@ static int cf_check map_range(
     return rc;
 }
 
-/*
- * The rom_only parameter is used to signal the map/unmap helpers that the ROM
- * BAR's enable bit has changed with the memory decoding bit already enabled.
- * If rom_only is not set then it's the memory decoding bit that changed.
- */
-static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd,
-                            bool rom_only)
-{
-    struct vpci_header *header = &pdev->vpci->header;
-    bool map = cmd & PCI_COMMAND_MEMORY;
-    unsigned int i;
-
-    for ( i = 0; i < ARRAY_SIZE(header->bars); i++ )
-    {
-        struct vpci_bar *bar = &header->bars[i];
-
-        if ( !MAPPABLE_BAR(bar) )
-            continue;
-
-        if ( rom_only && bar->type == VPCI_BAR_ROM )
-        {
-            unsigned int rom_pos = (i == PCI_HEADER_NORMAL_NR_BARS)
-                                   ? PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
-            uint32_t val = bar->addr |
-                           (map ? PCI_ROM_ADDRESS_ENABLE : 0);
-
-            if ( pci_check_bar(pdev, _mfn(PFN_DOWN(bar->addr)),
-                               _mfn(PFN_DOWN(bar->addr + bar->size - 1))) )
-                bar->enabled = map;
-            return;
-        }
-
-        if ( !rom_only &&
-             (bar->type != VPCI_BAR_ROM || header->rom_enabled) &&
-             pci_check_bar(pdev, _mfn(PFN_DOWN(bar->addr)),
-                           _mfn(PFN_DOWN(bar->addr + bar->size - 1))) )
-            bar->enabled = map;
-    }
-}
-
 bool vpci_process_pending(struct vcpu *v)
 {
     const struct pci_dev *pdev = v->vpci.pdev;
@@ -190,8 +150,10 @@ bool vpci_process_pending(struct vcpu *v)
         };
         int rc;
 
+        ASSERT(bar->valid || rangeset_is_empty(bar->mem));
+
         if ( rangeset_is_empty(bar->mem) )
-            continue;
+            goto next;
 
         rc = rangeset_consume_ranges(bar->mem, map_range, &data);
 
@@ -217,13 +179,13 @@ bool vpci_process_pending(struct vcpu *v)
          * rangeset_consume_ranges() itself doesn't generate any errors.
          */
         rangeset_purge(bar->mem);
+
+ next:
+        if ( bar->valid )
+            bar->enabled = v->vpci.cmd & PCI_COMMAND_MEMORY;
     }
     v->vpci.pdev = NULL;
 
-    spin_lock(&pdev->vpci->lock);
-    modify_decoding(pdev, v->vpci.cmd, v->vpci.rom_only);
-    spin_unlock(&pdev->vpci->lock);
-
     read_unlock(&v->domain->pci_lock);
 
     return false;
@@ -243,10 +205,8 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev,
         struct vpci_bar *bar = &header->bars[i];
         struct map_data data = { .d = d, .map = true, .bar = bar };
 
-        if ( rangeset_is_empty(bar->mem) )
-            continue;
-
-        while ( (rc = rangeset_consume_ranges(bar->mem, map_range,
+        while ( bar->mem &&
+                (rc = rangeset_consume_ranges(bar->mem, map_range,
                                               &data)) == -ERESTART )
         {
             /*
@@ -258,9 +218,10 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev,
             process_pending_softirqs();
             write_lock(&d->pci_lock);
         }
+
+        if ( bar->valid )
+            bar->enabled = true;
     }
-    if ( !rc )
-        modify_decoding(pdev, cmd, false);
 
     return rc;
 }
@@ -326,6 +287,9 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only)
          */
         rangeset_purge(bar->mem);
 
+        /* Reset whether the BAR is valid, will be checked below. */
+        bar->valid = false;
+
         if ( !MAPPABLE_BAR(bar) ||
              (rom_only ? bar->type != VPCI_BAR_ROM
                        : (bar->type == VPCI_BAR_ROM && !header->rom_enabled)) ||
@@ -341,6 +305,8 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only)
             continue;
         }
 
+        bar->valid = true;
+
         /*
          * Make sure that the guest set address has the same page offset
          * as the physical address on the host or otherwise things won't work as
@@ -539,6 +505,7 @@ static void cf_check cmd_write(
     if ( (cmd & PCI_COMMAND_MEMORY) && vpci_make_msix_hole(pdev) )
         return;
 #endif
+
     /*
      * FIXME: for domUs we don't want the guest toggling the memory decoding
      * bit.  It should be set in vpci_init_header() and guest attempts to
diff --git a/xen/include/xen/vpci.h b/xen/include/xen/vpci.h
index 17cfecb0aabf..6bdbbb842f58 100644
--- a/xen/include/xen/vpci.h
+++ b/xen/include/xen/vpci.h
@@ -128,6 +128,11 @@ struct vpci {
             bool prefetchable : 1;
             /* Store whether the BAR is mapped into guest p2m. */
             bool enabled      : 1;
+            /*
+             * Is the BAR position valid?  Used to store intermediate state
+             * before BAR modifications are applied to the p2m.
+             */
+            bool valid        : 1;
         } bars[PCI_HEADER_NORMAL_NR_BARS + 1];
         /* At most 6 BARS + 1 expansion ROM BAR. */
 
-- 
2.49.0



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From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: stewart.hildebrand@amd.com,
	Jiqian.Chen@amd.com,
	jbeulich@suse.com,
	Roger Pau Monne 
Subject: [PATCH 4/5] vpci/msix: move MSI-X hole punching as a result of memory decoding enable
Date: Thu, 14 Aug 2025 18:03:57 +0200
Message-ID: <20250814160358.95543-5-roger.pau@citrix.com>
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Deferring the p2m unpopulate of the MSI-X table region to after the BAR are
mapped in the p2m is not needed.  The aim of vpci_make_msix_hole() is to
cope with the BAR containing the MSI-X table being positioned over a
reserved e820 region, by making sure the MSI-X table region is
unpopulated on the p2m. Note that reserved e820 regions are identity mapped
in the hardware domain p2m by default.

Doing it before or after the BAR p2m changes are done is irrelevant, hence
do it ahead of the p2m changes, as that's simpler.

Signed-off-by: Roger Pau Monné 
---
 xen/drivers/vpci/header.c | 18 +++++-------------
 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
index 1a501a0ba47e..255c6d54b406 100644
--- a/xen/drivers/vpci/header.c
+++ b/xen/drivers/vpci/header.c
@@ -133,19 +133,6 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd,
     bool map = cmd & PCI_COMMAND_MEMORY;
     unsigned int i;
 
-    /*
-     * Make sure there are no mappings in the MSIX MMIO areas, so that accesses
-     * can be trapped (and emulated) by Xen when the memory decoding bit is
-     * enabled.
-     *
-     * FIXME: punching holes after the p2m has been set up might be racy for
-     * DomU usage, needs to be revisited.
-     */
-#ifdef CONFIG_HAS_PCI_MSI
-    if ( map && !rom_only && vpci_make_msix_hole(pdev) )
-        return;
-#endif
-
     for ( i = 0; i < ARRAY_SIZE(header->bars); i++ )
     {
         struct vpci_bar *bar = &header->bars[i];
@@ -547,6 +534,11 @@ static void cf_check cmd_write(
          */
         return;
 
+#ifdef CONFIG_HAS_PCI_MSI
+    /* Unpopulate MSI-X table region, so accesses trap into Xen. */
+    if ( (cmd & PCI_COMMAND_MEMORY) && vpci_make_msix_hole(pdev) )
+        return;
+#endif
     /*
      * FIXME: for domUs we don't want the guest toggling the memory decoding
      * bit.  It should be set in vpci_init_header() and guest attempts to
-- 
2.49.0



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From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: stewart.hildebrand@amd.com,
	Jiqian.Chen@amd.com,
	jbeulich@suse.com,
	Roger Pau Monne 
Subject: [PATCH 1/5] xen/vpci: purge BAR rangeset contents before use
Date: Thu, 14 Aug 2025 18:03:54 +0200
Message-ID: <20250814160358.95543-2-roger.pau@citrix.com>
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It's possible for the BAR rangeset to contain stale data when used in
modify_bars() if previous calls to modify_bars() resulted in errors.

Fix by always purging the rangeset before usage, thus getting rid of any
previous stale data.  Remove the ASSERT that checked whether the rangeset
was empty, it was incorrect.

Fixes: 52ebde3cfae2 ('vpci/header: program p2m with guest BAR view')
Signed-off-by: Roger Pau Monné 
---
 xen/drivers/vpci/header.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
index 469f4977441a..b9756b364300 100644
--- a/xen/drivers/vpci/header.c
+++ b/xen/drivers/vpci/header.c
@@ -338,6 +338,12 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only)
         if ( !bar->mem )
             continue;
 
+        /*
+         * Empty before use, previous failures might have left stale data in
+         * the rangeset.
+         */
+        rangeset_purge(bar->mem);
+
         if ( !MAPPABLE_BAR(bar) ||
              (rom_only ? bar->type != VPCI_BAR_ROM
                        : (bar->type == VPCI_BAR_ROM && !header->rom_enabled)) ||
@@ -353,8 +359,6 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only)
             continue;
         }
 
-        ASSERT(rangeset_is_empty(bar->mem));
-
         /*
          * Make sure that the guest set address has the same page offset
          * as the physical address on the host or otherwise things won't work as
-- 
2.49.0



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Hello Julien,

On 8/13/25 14:11, Julien Grall wrote:
> On 13/08/2025 11:04, Milan Djokic wrote:
>> Hello Julien,
> 
> Hi Milan,
> 
>>
>> We have prepared a design document and it will be part of the updated
>> patch series (added in docs/design). I'll also extend cover letter with
>> details on implementation structure to make review easier.
> 
> I would suggest to just iterate on the design document for now.
> 
>> Following is the design document content which will be provided in
>> updated patch series:
>>
>> Design Proposal: Add SMMUv3 Stage-1 Support for XEN Guests
>> ==========================================================
>>
>> Author: Milan Djokic 
>> Date:   2025-08-07
>> Status: Draft
>>
>> Introduction
>> ------------
>>
>> The SMMUv3 supports two stages of translation. Each stage of translation
>> can be independently enabled. An incoming address is logically
>> translated from VA to IPA in stage 1, then the IPA is input to stage 2
>> which translates the IPA to the output PA. Stage 1 translation support
>> is required to provide isolation between different devices within the OS.
>>
>> Xen already supports Stage 2 translation but there is no support for
>> Stage 1 translation. This design proposal outlines the introduction of
>> Stage-1 SMMUv3 support in Xen for ARM guests.
>>
>> Motivation
>> ----------
>>
>> ARM systems utilizing SMMUv3 require Stage-1 address translation to
>> ensure correct and secure DMA behavior inside guests.
> 
> Can you clarify what you mean by "correct"? DMA would still work without
> stage-1.

Correct in terms of working with guest managed I/O space. I'll rephrase 
this statement, it seems ambiguous.

>>
>> This feature enables:
>> - Stage-1 translation in guest domain
>> - Safe device passthrough under secure memory translation
>>
>> Design Overview
>> ---------------
>>
>> These changes provide emulated SMMUv3 support:
>>
>> - SMMUv3 Stage-1 Translation: stage-1 and nested translation support in
>>     SMMUv3 driver
>> - vIOMMU Abstraction: virtual IOMMU framework for guest Stage-1 handling
> 
> So what are you planning to expose to a guest? Is it one vIOMMU per
> pIOMMU? Or a single one?

Single vIOMMU model is used in this design.

> 
> Have you considered the pros/cons for both?
>> - Register/Command Emulation: SMMUv3 register emulation and command
>>     queue handling
> 

That's a point for consideration.
single vIOMMU prevails in terms of less complex implementation and a 
simple guest iommmu model - single vIOMMU node, one interrupt path, 
event queue, single set of trap handlers for emulation, etc.
Cons for a single vIOMMU model could be less accurate hw representation 
and a potential bottleneck with one emulated queue and interrupt path.
On the other hand, vIOMMU per pIOMMU provides more accurate hw modeling 
and offers better scalability in case of many IOMMUs in the system, but 
this comes with more complex emulation logic and device tree, also 
handling multiple vIOMMUs on guest side.
IMO, single vIOMMU model seems like a better option mostly because it's 
less complex, easier to maintain and debug. Of course, this decision can 
and should be discussed.

> For each pSMMU, we have a single command queue that will receive command
> from all the guests. How do you plan to prevent a guest hogging the
> command queue?
> 
> In addition to that, AFAIU, the size of the virtual command queue is
> fixed by the guest rather than Xen. If a guest is filling up the queue
> with commands before notifying Xen, how do you plan to ensure we don't
> spend too much time in Xen (which is not preemptible)?
> 

We'll have to do a detailed analysis on these scenarios, they are not 
covered by the design (as well as some others which is clear after your 
comments). I'll come back with an updated design.

> Lastly, what do you plan to expose? Is it a full vIOMMU (including event
> forwarding)?
> 

Yes, implementation provides full vIOMMU functionality, with stage-1 
event forwarding to guest.

>> - Device Tree Extensions: adds iommus and virtual SMMUv3 nodes to
>>     device trees for dom0 and dom0less scenarios
>> - Runtime Configuration: introduces a 'viommu' boot parameter for
>>     dynamic enablement
>>
>> Security Considerations
>> ------------------------
>>
>> viommu security benefits:
>> - Stage-1 translation ensures guest devices cannot perform unauthorized
>>     DMA
>> - Emulated SMMUv3 for domains removes dependency on host hardware while
>>     maintaining isolation
> 
> I don't understand this sentence.
> 

Current implementation emulates IOMMU with predefined capabilities, 
exposed as a single vIOMMU to guest. That's where "removes dependency on 
host hardware" came from. I'll rephrase this part to be more clear.


>>
>> Observations and Potential Risks
>> --------------------------------
>>
>> 1. Observation:
>> Support for Stage-1 translation introduces new data structures
>> (s1_cfg and s2_cfg) and logic to write both Stage-1 and Stage-2 entries
>> in the Stream Table Entry (STE), including an abort field for partial
>> config states.
>>
>> Risk:
>> A partially applied Stage-1 configuration might leave guest DMA
>> mappings in an inconsistent state, enabling unauthorized access or
>> cross-domain interference.
> 
> I don't understand how a misconfigured stage-1 could lead to
> cross-domain interference. Can you clarify?
> 

For stage-1 support, SID-to-device mapping and per device  io_domain 
allocation is introduced in Xen smmu driver, and we have to take care 
that these mappings are valid all the time. If these are not properly 
managed, structures and SIDs could be mapped to wrong device (and 
consequentially wrong guest) in some extreme cases.
This is covered by the design, but listed as a risc anyway for eventual 
future updates in this area.


>>
>> Mitigation (Handled by design):
>> Both s1_cfg and s2_cfg are written atomically. The abort field ensures
>> Stage-1 config is only used when fully applied. Incomplete configs are
>> ignored by the hypervisor.
>>
>> 2. Observation:
>> Guests can now issue Stage-1 cache invalidations.
>>
>> Risk:
>> Failure to propagate invalidations could leave stale mappings, enabling
>> data leakage or misrouting.
> 
> This is a risk from the guest PoV, right? IOW, this would not open up a
> security hole in Xen.
> 

Yes, this is guest PoV, although still related to vIOMMU.

>>
>> Mitigation (Handled by design):
>> Guest invalidations are forwarded to the hardware to ensure IOMMU
>> coherency.
>>
>> 3. Observation:
>> The feature introduces large functional changes including the vIOMMU
>> framework, vsmmuv3 devices, command queues, event queues, domain
>> handling, and Device Tree modifications.
>>
>> Risk:
>> Increased attack surface with risk of race conditions, malformed
>> commands, or misconfiguration via the device tree.
>>
>> Mitigation:
>> - Improved sanity checks and error handling
>> - Feature is marked as Tech Preview and self-contained to reduce risk
>>     to unrelated code
> 
> Surely, you will want to use the code in production... No?
> 

Yes, it is planned for production usage. At the moment, it is optionally 
enabled (grouped under unsupported features), needs community feedback, 
complete security analysis and performance benchmarking/optimization. 
That's the reason it's marked as a Tech Preview at this point.


>>
>> 4. Observation:
>> The implementation supports nested and standard translation modes,
>> using guest command queues (e.g. CMD_CFGI_STE) and events.
>>
>> Risk:
>> Malicious commands could bypass validation and corrupt SMMUv3 state or
>> destabilize dom0.
>>
>> Mitigation (Handled by design):
>> Command queues are validated, and only permitted configuration changes
>> are accepted. Handled in vsmmuv3 and cmdqueue logic.
> 
> I didn't mention anything in obversation 1 but now I have to say it...
> The observations you wrote are what I would expect to be handled in any
> submission to our code base. This is the bare minimum to have the code
> secure. But you don't seem to address the more subttle ones which are
> more related to scheduling issue (see some above). They require some
> design and discussion.
> 

Yes, it's clear to me after your comments that some important 
observations are missing. We'll do additional analysis and come back 
with a more complete design.

>>
>> 5. Observation:
>> Device Tree changes inject iommus and vsmmuv3 nodes via libxl.
>>
>> Risk:
>> Malicious or incorrect DT fragments could result in wrong device
>> assignments or hardware access.
>>
>> Mitigation:
>> Only vetted and sanitized DT fragments are allowed. libxl limits what
>> guests can inject.
> 
> Today, libxl doesn't do any sanitisation on the DT. In fact, this is
> pretty much impossible because libfdt expects trusted DT. Is this
> something you are planning to change?

I've referred to libxl parsing only supported fragments/nodes from DT, 
but yes, that's not actual sanitization. I'll update these statements.

>>
>> 6. Observation:
>> The feature is enabled per-guest via viommu setting.
>>
>> Risk:
>> Guests without viommu may behave differently, potentially causing
>> confusion, privilege drift, or accidental exposure.
>>
>> Mitigation:
>> Ensure downgrade paths are safe. Perform isolation audits in
>> multi-guest environments to ensure correct behavior.
>>
>> Performance Impact
>> ------------------
>>
>> Hardware-managed translations are expected to have minimal overhead.
>> Emulated vIOMMU may introduce some latency during initialization or
>> event processing.
> 
> Latency to who? We still expect isolation between guests and a guest
> will not go over its time slice.
> 

This is more related to comparison of emulated vs hw translation, and 
overall overhead introduced with these mechanisms. I'll rephrase this 
part to be more clear.

> For the guest itself, the main performance impact will be TLB flushes
> because they are commands that will end up to be emulated by Xen.
> Depending on your Linux configuration (I haven't checked other), this
> will either happen every unmap operation or they will be batch. The
> performance of the latter will be the worse one.
> 
> Have you done any benchmark to confirm the impact? Just to note, I would
> not gate the work for virtual SMMUv3 based on the performance. I think
> it is ok to offer the support if the user want extra security and
> doesn't care about performance. But it would be good to outline them as
> I expect them to be pretty bad...
> 

We haven't performed detailed benchmarking, just a measurement of boot 
time and our domU application execution rate with and without viommu. We 
could perform some measurements for viommu operations and add results in 
this section.

Thank you for your feedback, I'll come back with an updated design 
document for further review.

BR,
Milan


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Date: Thu, 14 Aug 2025 10:37:22 -0700
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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v2 01/16] dma-mapping: introduce new DMA attribute to
 indicate MMIO memory
To: Leon Romanovsky ,
 Marek Szyprowski 
Cc: Leon Romanovsky , Jason Gunthorpe ,
 Abdiel Janulgue ,
 Alexander Potapenko , Alex Gaynor
 , Andrew Morton ,
 Christoph Hellwig , Danilo Krummrich ,
 iommu@lists.linux.dev, Jason Wang ,
 Jens Axboe , Joerg Roedel ,
 Jonathan Corbet , Juergen Gross ,
 kasan-dev@googlegroups.com, Keith Busch ,
 linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-mm@kvack.org,
 linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
 linux-trace-kernel@vger.kernel.org, Madhavan Srinivasan
 , Masami Hiramatsu ,
 Michael Ellerman , "Michael S. Tsirkin"
 , Miguel Ojeda ,
 Robin Murphy , rust-for-linux@vger.kernel.org,
 Sagi Grimberg , Stefano Stabellini
 , Steven Rostedt ,
 virtualization@lists.linux.dev, Will Deacon ,
 xen-devel@lists.xenproject.org
References: 
 
Content-Language: en-US
From: Randy Dunlap 
In-Reply-To: 
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Hi Leon,

On 8/14/25 3:13 AM, Leon Romanovsky wrote:
> diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst
> index 1887d92e8e92..58a1528a9bb9 100644
> --- a/Documentation/core-api/dma-attributes.rst
> +++ b/Documentation/core-api/dma-attributes.rst
> @@ -130,3 +130,21 @@ accesses to DMA buffers in both privileged "supervisor" and unprivileged
>  subsystem that the buffer is fully accessible at the elevated privilege
>  level (and ideally inaccessible or at least read-only at the
>  lesser-privileged levels).
> +
> +DMA_ATTR_MMIO
> +-------------
> +
> +This attribute indicates the physical address is not normal system
> +memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page()
> +functions, it may not be cachable, and access using CPU load/store

Usually "cacheable" (git grep -w cacheable counts 1042 hits vs.
55 hits for "cachable"). And the $internet agrees.

> +instructions may not be allowed.
> +
> +Usually this will be used to describe MMIO addresses, or other non

non-cacheable

> +cachable register addresses. When DMA mapping this sort of address we

> +call the operation Peer to Peer as a one device is DMA'ing to another
> +device. For PCI devices the p2pdma APIs must be used to determine if
> +DMA_ATTR_MMIO is appropriate.
> +
> +For architectures that require cache flushing for DMA coherence
> +DMA_ATTR_MMIO will not perform any cache flushing. The address
> +provided must never be mapped cachable into the CPU.
again.

thanks.
-- 
~Randy



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Date: Thu, 14 Aug 2025 20:43:33 +0300
From: Leon Romanovsky 
To: Randy Dunlap 
Cc: Marek Szyprowski ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v2 01/16] dma-mapping: introduce new DMA attribute to
 indicate MMIO memory
Message-ID: <20250814174333.GA8427@unreal>
References: 
 
 
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On Thu, Aug 14, 2025 at 10:37:22AM -0700, Randy Dunlap wrote:
> Hi Leon,
> 
> On 8/14/25 3:13 AM, Leon Romanovsky wrote:
> > diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst
> > index 1887d92e8e92..58a1528a9bb9 100644
> > --- a/Documentation/core-api/dma-attributes.rst
> > +++ b/Documentation/core-api/dma-attributes.rst
> > @@ -130,3 +130,21 @@ accesses to DMA buffers in both privileged "supervisor" and unprivileged
> >  subsystem that the buffer is fully accessible at the elevated privilege
> >  level (and ideally inaccessible or at least read-only at the
> >  lesser-privileged levels).
> > +
> > +DMA_ATTR_MMIO
> > +-------------
> > +
> > +This attribute indicates the physical address is not normal system
> > +memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page()
> > +functions, it may not be cachable, and access using CPU load/store
> 
> Usually "cacheable" (git grep -w cacheable counts 1042 hits vs.
> 55 hits for "cachable"). And the $internet agrees.
> 
> > +instructions may not be allowed.
> > +
> > +Usually this will be used to describe MMIO addresses, or other non
> 
> non-cacheable
> 
> > +cachable register addresses. When DMA mapping this sort of address we
> 
> > +call the operation Peer to Peer as a one device is DMA'ing to another
> > +device. For PCI devices the p2pdma APIs must be used to determine if
> > +DMA_ATTR_MMIO is appropriate.
> > +
> > +For architectures that require cache flushing for DMA coherence
> > +DMA_ATTR_MMIO will not perform any cache flushing. The address
> > +provided must never be mapped cachable into the CPU.
> again.

Thanks, I will fix.

> 
> thanks.
> -- 
> ~Randy
> 
> 


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Date: Thu, 14 Aug 2025 19:49:07 +0200
From: Nicola Vetrini 
To: Jan Beulich 
Cc: sstabellini@kernel.org, consulting@bugseng.com,
 dmytro_prokopchuk1@epam.com, andrew.cooper3@citrix.com, Doug Goldstein
 , xen-devel@lists.xenproject.org
Subject: Re: [XEN PATCH 2/2] Address violation of MISRA C Rule 13.1 involving
 asm side effects.
In-Reply-To: <0b55d5f9-35ad-4598-94ab-1aa4991c0e3a@suse.com>
References: <1283be3b76d76814af244bbca544f6a3b74a04de.1754689062.git.nicola.vetrini@bugseng.com>
 
 <0b55d5f9-35ad-4598-94ab-1aa4991c0e3a@suse.com>
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On 2025-08-14 09:36, Jan Beulich wrote:
> On 08.08.2025 23:40, Nicola Vetrini wrote:
>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>> @@ -437,6 +437,10 @@ write or not"
>>  # Series 13
>>  #
>> 
>> +-doc_begin="Consider the asm instruction to read an Arm system 
>> register to have no side effects."
>> +-asm_properties+={"asm(any())&&child(text, 
>> ast_field(value,^mrs\\s+%0.*$))", {no_side_effect}}
>> +-doc_end
> 
> Is this actually strict enough to not allow multiple instructions in 
> the asm(),
> where some of the others would yield side effects we actually need to 
> respect?
> 
> Jan

Good point, I didn't think of that. As it is, there is only one MRS asm, 
so no worries here, but in general the remark is valid. The regex could 
be a bit stricter, though the real solution here would be to match the 
context in which this asm is present to limit the scope of the 
deviation. This does not make much sense for an asm property because the 
properties of an asm statement (at the level of granularity targeted by 
ECLAIR) can be derived mostly in isolation from the surrounding code.

Another improvement we are pursuing is allowing single effects in 
init-list-exprs, but it will take a bit of time to surface (i.e., next 
major release probably).

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v3 01/16] dma-mapping: introduce new DMA attribute to indicate MMIO memory
Date: Thu, 14 Aug 2025 20:53:52 +0300
Message-ID: <08e044a00a872932e106f7e27449a8eab2690dbc.1755193625.git.leon@kernel.org>
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From: Leon Romanovsky 

This patch introduces the DMA_ATTR_MMIO attribute to mark DMA buffers
that reside in memory-mapped I/O (MMIO) regions, such as device BARs
exposed through the host bridge, which are accessible for peer-to-peer
(P2P) DMA.

This attribute is especially useful for exporting device memory to other
devices for DMA without CPU involvement, and avoids unnecessary or
potentially detrimental CPU cache maintenance calls.

DMA_ATTR_MMIO is supposed to provide dma_map_resource() functionality
without need to call to special function and perform branching by
the callers.

Signed-off-by: Leon Romanovsky 
---
 Documentation/core-api/dma-attributes.rst | 18 ++++++++++++++++++
 include/linux/dma-mapping.h               | 20 ++++++++++++++++++++
 include/trace/events/dma.h                |  3 ++-
 rust/kernel/dma.rs                        |  3 +++
 4 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst
index 1887d92e8e92..0bdc2be65e57 100644
--- a/Documentation/core-api/dma-attributes.rst
+++ b/Documentation/core-api/dma-attributes.rst
@@ -130,3 +130,21 @@ accesses to DMA buffers in both privileged "supervisor" and unprivileged
 subsystem that the buffer is fully accessible at the elevated privilege
 level (and ideally inaccessible or at least read-only at the
 lesser-privileged levels).
+
+DMA_ATTR_MMIO
+-------------
+
+This attribute indicates the physical address is not normal system
+memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page()
+functions, it may not be cacheable, and access using CPU load/store
+instructions may not be allowed.
+
+Usually this will be used to describe MMIO addresses, or other non-cacheable
+register addresses. When DMA mapping this sort of address we call
+the operation Peer to Peer as a one device is DMA'ing to another device.
+For PCI devices the p2pdma APIs must be used to determine if
+DMA_ATTR_MMIO is appropriate.
+
+For architectures that require cache flushing for DMA coherence
+DMA_ATTR_MMIO will not perform any cache flushing. The address
+provided must never be mapped cacheable into the CPU.
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 55c03e5fe8cb..4254fd9bdf5d 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -58,6 +58,26 @@
  */
 #define DMA_ATTR_PRIVILEGED		(1UL << 9)
 
+/*
+ * DMA_ATTR_MMIO - Indicates memory-mapped I/O (MMIO) region for DMA mapping
+ *
+ * This attribute indicates the physical address is not normal system
+ * memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page()
+ * functions, it may not be cacheable, and access using CPU load/store
+ * instructions may not be allowed.
+ *
+ * Usually this will be used to describe MMIO addresses, or other non-cacheable
+ * register addresses. When DMA mapping this sort of address we call
+ * the operation Peer to Peer as a one device is DMA'ing to another device.
+ * For PCI devices the p2pdma APIs must be used to determine if DMA_ATTR_MMIO
+ * is appropriate.
+ *
+ * For architectures that require cache flushing for DMA coherence
+ * DMA_ATTR_MMIO will not perform any cache flushing. The address
+ * provided must never be mapped cacheable into the CPU.
+ */
+#define DMA_ATTR_MMIO		(1UL << 10)
+
 /*
  * A dma_addr_t can hold any valid DMA or bus address for the platform.  It can
  * be given to a device to use as a DMA source or target.  It is specific to a
diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h
index d8ddc27b6a7c..ee90d6f1dcf3 100644
--- a/include/trace/events/dma.h
+++ b/include/trace/events/dma.h
@@ -31,7 +31,8 @@ TRACE_DEFINE_ENUM(DMA_NONE);
 		{ DMA_ATTR_FORCE_CONTIGUOUS, "FORCE_CONTIGUOUS" }, \
 		{ DMA_ATTR_ALLOC_SINGLE_PAGES, "ALLOC_SINGLE_PAGES" }, \
 		{ DMA_ATTR_NO_WARN, "NO_WARN" }, \
-		{ DMA_ATTR_PRIVILEGED, "PRIVILEGED" })
+		{ DMA_ATTR_PRIVILEGED, "PRIVILEGED" }, \
+		{ DMA_ATTR_MMIO, "MMIO" })
 
 DECLARE_EVENT_CLASS(dma_map,
 	TP_PROTO(struct device *dev, phys_addr_t phys_addr, dma_addr_t dma_addr,
diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs
index 2bc8ab51ec28..61d9eed7a786 100644
--- a/rust/kernel/dma.rs
+++ b/rust/kernel/dma.rs
@@ -242,6 +242,9 @@ pub mod attrs {
     /// Indicates that the buffer is fully accessible at an elevated privilege level (and
     /// ideally inaccessible or at least read-only at lesser-privileged levels).
     pub const DMA_ATTR_PRIVILEGED: Attrs = Attrs(bindings::DMA_ATTR_PRIVILEGED);
+
+    /// Indicates that the buffer is MMIO memory.
+    pub const DMA_ATTR_MMIO: Attrs = Attrs(bindings::DMA_ATTR_MMIO);
 }
 
 /// An abstraction of the `dma_alloc_coherent` API.
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
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	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
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	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v3 00/16] dma-mapping: migrate to physical address-based API
Date: Thu, 14 Aug 2025 20:53:51 +0300
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Changelog:
v3:
 * Fixed typo in "cacheable" word
 * Simplified kmsan patch a lot to be simple argument refactoring
v2: https://lore.kernel.org/all/cover.1755153054.git.leon@kernel.org
 * Used commit messages and cover letter from Jason
 * Moved setting IOMMU_MMIO flag to dma_info_to_prot function
 * Micro-optimized the code
 * Rebased code on v6.17-rc1
v1: https://lore.kernel.org/all/cover.1754292567.git.leon@kernel.org
 * Added new DMA_ATTR_MMIO attribute to indicate
   PCI_P2PDMA_MAP_THRU_HOST_BRIDGE path.
 * Rewrote dma_map_* functions to use thus new attribute
v0: https://lore.kernel.org/all/cover.1750854543.git.leon@kernel.org/
------------------------------------------------------------------------

This series refactors the DMA mapping to use physical addresses
as the primary interface instead of page+offset parameters. This
change aligns the DMA API with the underlying hardware reality where
DMA operations work with physical addresses, not page structures.

The series maintains export symbol backward compatibility by keeping
the old page-based API as wrapper functions around the new physical
address-based implementations.

This series refactors the DMA mapping API to provide a phys_addr_t
based, and struct-page free, external API that can handle all the
mapping cases we want in modern systems:

 - struct page based cachable DRAM
 - struct page MEMORY_DEVICE_PCI_P2PDMA PCI peer to peer non-cachable
   MMIO
 - struct page-less PCI peer to peer non-cachable MMIO
 - struct page-less "resource" MMIO

Overall this gets much closer to Matthew's long term wish for
struct-pageless IO to cachable DRAM. The remaining primary work would
be in the mm side to allow kmap_local_pfn()/phys_to_virt() to work on
phys_addr_t without a struct page.

The general design is to remove struct page usage entirely from the
DMA API inner layers. For flows that need to have a KVA for the
physical address they can use kmap_local_pfn() or phys_to_virt(). This
isolates the struct page requirements to MM code only. Long term all
removals of struct page usage are supporting Matthew's memdesc
project which seeks to substantially transform how struct page works.

Instead make the DMA API internals work on phys_addr_t. Internally
there are still dedicated 'page' and 'resource' flows, except they are
now distinguished by a new DMA_ATTR_MMIO instead of by callchain. Both
flows use the same phys_addr_t.

When DMA_ATTR_MMIO is specified things work similar to the existing
'resource' flow. kmap_local_pfn(), phys_to_virt(), phys_to_page(),
pfn_valid(), etc are never called on the phys_addr_t. This requires
rejecting any configuration that would need swiotlb. CPU cache
flushing is not required, and avoided, as ATTR_MMIO also indicates the
address have no cachable mappings. This effectively removes any
DMA API side requirement to have struct page when DMA_ATTR_MMIO is
used.

In the !DMA_ATTR_MMIO mode things work similarly to the 'page' flow,
except on the common path of no cache flush, no swiotlb it never
touches a struct page. When cache flushing or swiotlb copying
kmap_local_pfn()/phys_to_virt() are used to get a KVA for CPU
usage. This was already the case on the unmap side, now the map side
is symmetric.

Callers are adjusted to set DMA_ATTR_MMIO. Existing 'resource' users
must set it. The existing struct page based MEMORY_DEVICE_PCI_P2PDMA
path must also set it. This corrects some existing bugs where iommu
mappings for P2P MMIO were improperly marked IOMMU_CACHE.

Since ATTR_MMIO is made to work with all the existing DMA map entry
points, particularly dma_iova_link(), this finally allows a way to use
the new DMA API to map PCI P2P MMIO without creating struct page. The
VFIO DMABUF series demonstrates how this works. This is intended to
replace the incorrect driver use of dma_map_resource() on PCI BAR
addresses.

This series does the core code and modern flows. A followup series
will give the same treatment to the legacy dma_ops implementation.

Thanks

Leon Romanovsky (16):
  dma-mapping: introduce new DMA attribute to indicate MMIO memory
  iommu/dma: implement DMA_ATTR_MMIO for dma_iova_link().
  dma-debug: refactor to use physical addresses for page mapping
  dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys
  iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys
  iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory
  dma-mapping: convert dma_direct_*map_page to be phys_addr_t based
  kmsan: convert kmsan_handle_dma to use physical addresses
  dma-mapping: handle MMIO flow in dma_map|unmap_page
  xen: swiotlb: Open code map_resource callback
  dma-mapping: export new dma_*map_phys() interface
  mm/hmm: migrate to physical address-based DMA mapping API
  mm/hmm: properly take MMIO path
  block-dma: migrate to dma_map_phys instead of map_page
  block-dma: properly take MMIO path
  nvme-pci: unmap MMIO pages with appropriate interface

 Documentation/core-api/dma-api.rst        |   4 +-
 Documentation/core-api/dma-attributes.rst |  18 ++++
 arch/powerpc/kernel/dma-iommu.c           |   4 +-
 block/blk-mq-dma.c                        |  15 ++-
 drivers/iommu/dma-iommu.c                 |  61 +++++------
 drivers/nvme/host/pci.c                   |  18 +++-
 drivers/virtio/virtio_ring.c              |   4 +-
 drivers/xen/swiotlb-xen.c                 |  21 +++-
 include/linux/blk-mq-dma.h                |   6 +-
 include/linux/blk_types.h                 |   2 +
 include/linux/dma-direct.h                |   2 -
 include/linux/dma-map-ops.h               |   8 +-
 include/linux/dma-mapping.h               |  33 ++++++
 include/linux/iommu-dma.h                 |  11 +-
 include/linux/kmsan.h                     |   9 +-
 include/trace/events/dma.h                |   9 +-
 kernel/dma/debug.c                        |  71 ++++---------
 kernel/dma/debug.h                        |  37 ++-----
 kernel/dma/direct.c                       |  22 +---
 kernel/dma/direct.h                       |  52 ++++++----
 kernel/dma/mapping.c                      | 117 +++++++++++++---------
 kernel/dma/ops_helpers.c                  |   6 +-
 mm/hmm.c                                  |  19 ++--
 mm/kmsan/hooks.c                          |   7 +-
 rust/kernel/dma.rs                        |   3 +
 tools/virtio/linux/kmsan.h                |   2 +-
 26 files changed, 306 insertions(+), 255 deletions(-)

-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v3 03/16] dma-debug: refactor to use physical addresses for page mapping
Date: Thu, 14 Aug 2025 20:53:54 +0300
Message-ID: <478d5b7135008b3c82f100faa9d3830839fc6562.1755193625.git.leon@kernel.org>
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From: Leon Romanovsky 

Convert the DMA debug infrastructure from page-based to physical address-based
mapping as a preparation to rely on physical address for DMA mapping routines.

The refactoring renames debug_dma_map_page() to debug_dma_map_phys() and
changes its signature to accept a phys_addr_t parameter instead of struct page
and offset. Similarly, debug_dma_unmap_page() becomes debug_dma_unmap_phys().
A new dma_debug_phy type is introduced to distinguish physical address mappings
from other debug entry types. All callers throughout the codebase are updated
to pass physical addresses directly, eliminating the need for page-to-physical
conversion in the debug layer.

This refactoring eliminates the need to convert between page pointers and
physical addresses in the debug layer, making the code more efficient and
consistent with the DMA mapping API's physical address focus.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 Documentation/core-api/dma-api.rst |  4 ++--
 kernel/dma/debug.c                 | 28 +++++++++++++++++-----------
 kernel/dma/debug.h                 | 16 +++++++---------
 kernel/dma/mapping.c               | 15 ++++++++-------
 4 files changed, 34 insertions(+), 29 deletions(-)

diff --git a/Documentation/core-api/dma-api.rst b/Documentation/core-api/dma-api.rst
index 3087bea715ed..ca75b3541679 100644
--- a/Documentation/core-api/dma-api.rst
+++ b/Documentation/core-api/dma-api.rst
@@ -761,7 +761,7 @@ example warning message may look like this::
 	[] find_busiest_group+0x207/0x8a0
 	[] _spin_lock_irqsave+0x1f/0x50
 	[] check_unmap+0x203/0x490
-	[] debug_dma_unmap_page+0x49/0x50
+	[] debug_dma_unmap_phys+0x49/0x50
 	[] nv_tx_done_optimized+0xc6/0x2c0
 	[] nv_nic_irq_optimized+0x73/0x2b0
 	[] handle_IRQ_event+0x34/0x70
@@ -855,7 +855,7 @@ that a driver may be leaking mappings.
 dma-debug interface debug_dma_mapping_error() to debug drivers that fail
 to check DMA mapping errors on addresses returned by dma_map_single() and
 dma_map_page() interfaces. This interface clears a flag set by
-debug_dma_map_page() to indicate that dma_mapping_error() has been called by
+debug_dma_map_phys() to indicate that dma_mapping_error() has been called by
 the driver. When driver does unmap, debug_dma_unmap() checks the flag and if
 this flag is still set, prints warning message that includes call trace that
 leads up to the unmap. This interface can be called from dma_mapping_error()
diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c
index e43c6de2bce4..da6734e3a4ce 100644
--- a/kernel/dma/debug.c
+++ b/kernel/dma/debug.c
@@ -39,6 +39,7 @@ enum {
 	dma_debug_sg,
 	dma_debug_coherent,
 	dma_debug_resource,
+	dma_debug_phy,
 };
 
 enum map_err_types {
@@ -141,6 +142,7 @@ static const char *type2name[] = {
 	[dma_debug_sg] = "scatter-gather",
 	[dma_debug_coherent] = "coherent",
 	[dma_debug_resource] = "resource",
+	[dma_debug_phy] = "phy",
 };
 
 static const char *dir2name[] = {
@@ -1201,9 +1203,8 @@ void debug_dma_map_single(struct device *dev, const void *addr,
 }
 EXPORT_SYMBOL(debug_dma_map_single);
 
-void debug_dma_map_page(struct device *dev, struct page *page, size_t offset,
-			size_t size, int direction, dma_addr_t dma_addr,
-			unsigned long attrs)
+void debug_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		int direction, dma_addr_t dma_addr, unsigned long attrs)
 {
 	struct dma_debug_entry *entry;
 
@@ -1218,19 +1219,24 @@ void debug_dma_map_page(struct device *dev, struct page *page, size_t offset,
 		return;
 
 	entry->dev       = dev;
-	entry->type      = dma_debug_single;
-	entry->paddr	 = page_to_phys(page) + offset;
+	entry->type      = dma_debug_phy;
+	entry->paddr	 = phys;
 	entry->dev_addr  = dma_addr;
 	entry->size      = size;
 	entry->direction = direction;
 	entry->map_err_type = MAP_ERR_NOT_CHECKED;
 
-	check_for_stack(dev, page, offset);
+	if (!(attrs & DMA_ATTR_MMIO)) {
+		struct page *page = phys_to_page(phys);
+		size_t offset = offset_in_page(page);
 
-	if (!PageHighMem(page)) {
-		void *addr = page_address(page) + offset;
+		check_for_stack(dev, page, offset);
 
-		check_for_illegal_area(dev, addr, size);
+		if (!PageHighMem(page)) {
+			void *addr = page_address(page) + offset;
+
+			check_for_illegal_area(dev, addr, size);
+		}
 	}
 
 	add_dma_entry(entry, attrs);
@@ -1274,11 +1280,11 @@ void debug_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 }
 EXPORT_SYMBOL(debug_dma_mapping_error);
 
-void debug_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
+void debug_dma_unmap_phys(struct device *dev, dma_addr_t dma_addr,
 			  size_t size, int direction)
 {
 	struct dma_debug_entry ref = {
-		.type           = dma_debug_single,
+		.type           = dma_debug_phy,
 		.dev            = dev,
 		.dev_addr       = dma_addr,
 		.size           = size,
diff --git a/kernel/dma/debug.h b/kernel/dma/debug.h
index f525197d3cae..76adb42bffd5 100644
--- a/kernel/dma/debug.h
+++ b/kernel/dma/debug.h
@@ -9,12 +9,11 @@
 #define _KERNEL_DMA_DEBUG_H
 
 #ifdef CONFIG_DMA_API_DEBUG
-extern void debug_dma_map_page(struct device *dev, struct page *page,
-			       size_t offset, size_t size,
-			       int direction, dma_addr_t dma_addr,
+extern void debug_dma_map_phys(struct device *dev, phys_addr_t phys,
+			       size_t size, int direction, dma_addr_t dma_addr,
 			       unsigned long attrs);
 
-extern void debug_dma_unmap_page(struct device *dev, dma_addr_t addr,
+extern void debug_dma_unmap_phys(struct device *dev, dma_addr_t addr,
 				 size_t size, int direction);
 
 extern void debug_dma_map_sg(struct device *dev, struct scatterlist *sg,
@@ -55,14 +54,13 @@ extern void debug_dma_sync_sg_for_device(struct device *dev,
 					 struct scatterlist *sg,
 					 int nelems, int direction);
 #else /* CONFIG_DMA_API_DEBUG */
-static inline void debug_dma_map_page(struct device *dev, struct page *page,
-				      size_t offset, size_t size,
-				      int direction, dma_addr_t dma_addr,
-				      unsigned long attrs)
+static inline void debug_dma_map_phys(struct device *dev, phys_addr_t phys,
+				      size_t size, int direction,
+				      dma_addr_t dma_addr, unsigned long attrs)
 {
 }
 
-static inline void debug_dma_unmap_page(struct device *dev, dma_addr_t addr,
+static inline void debug_dma_unmap_phys(struct device *dev, dma_addr_t addr,
 					size_t size, int direction)
 {
 }
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 107e4a4d251d..4c1dfbabb8ae 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -157,6 +157,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
+	phys_addr_t phys = page_to_phys(page) + offset;
 	dma_addr_t addr;
 
 	BUG_ON(!valid_dma_direction(dir));
@@ -165,16 +166,15 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		return DMA_MAPPING_ERROR;
 
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_map_page_direct(dev, page_to_phys(page) + offset + size))
+	    arch_dma_map_page_direct(dev, phys + size))
 		addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		addr = iommu_dma_map_page(dev, page, offset, size, dir, attrs);
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
 	kmsan_handle_dma(page, offset, size, dir);
-	trace_dma_map_page(dev, page_to_phys(page) + offset, addr, size, dir,
-			   attrs);
-	debug_dma_map_page(dev, page, offset, size, dir, addr, attrs);
+	trace_dma_map_page(dev, phys, addr, size, dir, attrs);
+	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
 	return addr;
 }
@@ -194,7 +194,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 	else
 		ops->unmap_page(dev, addr, size, dir, attrs);
 	trace_dma_unmap_page(dev, addr, size, dir, attrs);
-	debug_dma_unmap_page(dev, addr, size, dir);
+	debug_dma_unmap_phys(dev, addr, size, dir);
 }
 EXPORT_SYMBOL(dma_unmap_page_attrs);
 
@@ -712,7 +712,8 @@ struct page *dma_alloc_pages(struct device *dev, size_t size,
 	if (page) {
 		trace_dma_alloc_pages(dev, page_to_virt(page), *dma_handle,
 				      size, dir, gfp, 0);
-		debug_dma_map_page(dev, page, 0, size, dir, *dma_handle, 0);
+		debug_dma_map_phys(dev, page_to_phys(page), size, dir,
+				   *dma_handle, 0);
 	} else {
 		trace_dma_alloc_pages(dev, NULL, 0, size, dir, gfp, 0);
 	}
@@ -738,7 +739,7 @@ void dma_free_pages(struct device *dev, size_t size, struct page *page,
 		dma_addr_t dma_handle, enum dma_data_direction dir)
 {
 	trace_dma_free_pages(dev, page_to_virt(page), dma_handle, size, dir, 0);
-	debug_dma_unmap_page(dev, dma_handle, size, dir);
+	debug_dma_unmap_phys(dev, dma_handle, size, dir);
 	__dma_free_pages(dev, size, page, dma_handle, dir);
 }
 EXPORT_SYMBOL_GPL(dma_free_pages);
-- 
2.50.1



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	Jason Gunthorpe ,
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	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
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Subject: [PATCH v3 04/16] dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys
Date: Thu, 14 Aug 2025 20:53:55 +0300
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From: Leon Romanovsky 

As a preparation for following map_page -> map_phys API conversion,
let's rename trace_dma_*map_page() to be trace_dma_*map_phys().

Signed-off-by: Leon Romanovsky 
---
 include/trace/events/dma.h | 4 ++--
 kernel/dma/mapping.c       | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h
index ee90d6f1dcf3..84416c7d6bfa 100644
--- a/include/trace/events/dma.h
+++ b/include/trace/events/dma.h
@@ -72,7 +72,7 @@ DEFINE_EVENT(dma_map, name, \
 		 size_t size, enum dma_data_direction dir, unsigned long attrs), \
 	TP_ARGS(dev, phys_addr, dma_addr, size, dir, attrs))
 
-DEFINE_MAP_EVENT(dma_map_page);
+DEFINE_MAP_EVENT(dma_map_phys);
 DEFINE_MAP_EVENT(dma_map_resource);
 
 DECLARE_EVENT_CLASS(dma_unmap,
@@ -110,7 +110,7 @@ DEFINE_EVENT(dma_unmap, name, \
 		 enum dma_data_direction dir, unsigned long attrs), \
 	TP_ARGS(dev, addr, size, dir, attrs))
 
-DEFINE_UNMAP_EVENT(dma_unmap_page);
+DEFINE_UNMAP_EVENT(dma_unmap_phys);
 DEFINE_UNMAP_EVENT(dma_unmap_resource);
 
 DECLARE_EVENT_CLASS(dma_alloc_class,
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 4c1dfbabb8ae..fe1f0da6dc50 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -173,7 +173,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
 	kmsan_handle_dma(page, offset, size, dir);
-	trace_dma_map_page(dev, phys, addr, size, dir, attrs);
+	trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
 	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
 	return addr;
@@ -193,7 +193,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 		iommu_dma_unmap_page(dev, addr, size, dir, attrs);
 	else
 		ops->unmap_page(dev, addr, size, dir, attrs);
-	trace_dma_unmap_page(dev, addr, size, dir, attrs);
+	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
 	debug_dma_unmap_phys(dev, addr, size, dir);
 }
 EXPORT_SYMBOL(dma_unmap_page_attrs);
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
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	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v3 05/16] iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys
Date: Thu, 14 Aug 2025 20:53:56 +0300
Message-ID: <66e7cc6854e4e40278b598b38e0c4d49d7fcec91.1755193625.git.leon@kernel.org>
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From: Leon Romanovsky 

Rename the IOMMU DMA mapping functions to better reflect their actual
calling convention. The functions iommu_dma_map_page() and
iommu_dma_unmap_page() are renamed to iommu_dma_map_phys() and
iommu_dma_unmap_phys() respectively, as they already operate on physical
addresses rather than page structures.

The calling convention changes from accepting (struct page *page,
unsigned long offset) to (phys_addr_t phys), which eliminates the need
for page-to-physical address conversion within the functions. This
renaming prepares for the broader DMA API conversion from page-based
to physical address-based mapping throughout the kernel.

All callers are updated to pass physical addresses directly, including
dma_map_page_attrs(), scatterlist mapping functions, and DMA page
allocation helpers. The change simplifies the code by removing the
page_to_phys() + offset calculation that was previously done inside
the IOMMU functions.

Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c | 14 ++++++--------
 include/linux/iommu-dma.h |  7 +++----
 kernel/dma/mapping.c      |  4 ++--
 kernel/dma/ops_helpers.c  |  6 +++---
 4 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index e1185ba73e23..aea119f32f96 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -1195,11 +1195,9 @@ static inline size_t iova_unaligned(struct iova_domain *iovad, phys_addr_t phys,
 	return iova_offset(iovad, phys | size);
 }
 
-dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
-	      unsigned long offset, size_t size, enum dma_data_direction dir,
-	      unsigned long attrs)
+dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs)
 {
-	phys_addr_t phys = page_to_phys(page) + offset;
 	bool coherent = dev_is_dma_coherent(dev);
 	int prot = dma_info_to_prot(dir, coherent, attrs);
 	struct iommu_domain *domain = iommu_get_dma_domain(dev);
@@ -1227,7 +1225,7 @@ dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
 	return iova;
 }
 
-void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
+void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
 	struct iommu_domain *domain = iommu_get_dma_domain(dev);
@@ -1346,7 +1344,7 @@ static void iommu_dma_unmap_sg_swiotlb(struct device *dev, struct scatterlist *s
 	int i;
 
 	for_each_sg(sg, s, nents, i)
-		iommu_dma_unmap_page(dev, sg_dma_address(s),
+		iommu_dma_unmap_phys(dev, sg_dma_address(s),
 				sg_dma_len(s), dir, attrs);
 }
 
@@ -1359,8 +1357,8 @@ static int iommu_dma_map_sg_swiotlb(struct device *dev, struct scatterlist *sg,
 	sg_dma_mark_swiotlb(sg);
 
 	for_each_sg(sg, s, nents, i) {
-		sg_dma_address(s) = iommu_dma_map_page(dev, sg_page(s),
-				s->offset, s->length, dir, attrs);
+		sg_dma_address(s) = iommu_dma_map_phys(dev, sg_phys(s),
+				s->length, dir, attrs);
 		if (sg_dma_address(s) == DMA_MAPPING_ERROR)
 			goto out_unmap;
 		sg_dma_len(s) = s->length;
diff --git a/include/linux/iommu-dma.h b/include/linux/iommu-dma.h
index 508beaa44c39..485bdffed988 100644
--- a/include/linux/iommu-dma.h
+++ b/include/linux/iommu-dma.h
@@ -21,10 +21,9 @@ static inline bool use_dma_iommu(struct device *dev)
 }
 #endif /* CONFIG_IOMMU_DMA */
 
-dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
-		unsigned long offset, size_t size, enum dma_data_direction dir,
-		unsigned long attrs);
-void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
+dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs);
+void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle,
 		size_t size, enum dma_data_direction dir, unsigned long attrs);
 int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 		enum dma_data_direction dir, unsigned long attrs);
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index fe1f0da6dc50..58482536db9b 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -169,7 +169,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 	    arch_dma_map_page_direct(dev, phys + size))
 		addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
 	else if (use_dma_iommu(dev))
-		addr = iommu_dma_map_page(dev, page, offset, size, dir, attrs);
+		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
 	kmsan_handle_dma(page, offset, size, dir);
@@ -190,7 +190,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 	    arch_dma_unmap_page_direct(dev, addr + size))
 		dma_direct_unmap_page(dev, addr, size, dir, attrs);
 	else if (use_dma_iommu(dev))
-		iommu_dma_unmap_page(dev, addr, size, dir, attrs);
+		iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
 	else
 		ops->unmap_page(dev, addr, size, dir, attrs);
 	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
diff --git a/kernel/dma/ops_helpers.c b/kernel/dma/ops_helpers.c
index 9afd569eadb9..6f9d604d9d40 100644
--- a/kernel/dma/ops_helpers.c
+++ b/kernel/dma/ops_helpers.c
@@ -72,8 +72,8 @@ struct page *dma_common_alloc_pages(struct device *dev, size_t size,
 		return NULL;
 
 	if (use_dma_iommu(dev))
-		*dma_handle = iommu_dma_map_page(dev, page, 0, size, dir,
-						 DMA_ATTR_SKIP_CPU_SYNC);
+		*dma_handle = iommu_dma_map_phys(dev, page_to_phys(page), size,
+						 dir, DMA_ATTR_SKIP_CPU_SYNC);
 	else
 		*dma_handle = ops->map_page(dev, page, 0, size, dir,
 					    DMA_ATTR_SKIP_CPU_SYNC);
@@ -92,7 +92,7 @@ void dma_common_free_pages(struct device *dev, size_t size, struct page *page,
 	const struct dma_map_ops *ops = get_dma_ops(dev);
 
 	if (use_dma_iommu(dev))
-		iommu_dma_unmap_page(dev, dma_handle, size, dir,
+		iommu_dma_unmap_phys(dev, dma_handle, size, dir,
 				     DMA_ATTR_SKIP_CPU_SYNC);
 	else if (ops->unmap_page)
 		ops->unmap_page(dev, dma_handle, size, dir,
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
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	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
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Subject: [PATCH v3 02/16] iommu/dma: implement DMA_ATTR_MMIO for dma_iova_link().
Date: Thu, 14 Aug 2025 20:53:53 +0300
Message-ID: <62d9a6c3ca03037631f6d0640ebec5fbac41d547.1755193625.git.leon@kernel.org>
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From: Leon Romanovsky 

This will replace the hacky use of DMA_ATTR_SKIP_CPU_SYNC to avoid
touching the possibly non-KVA MMIO memory.

Also correct the incorrect caching attribute for the IOMMU, MMIO
memory should not be cachable inside the IOMMU mapping or it can
possibly create system problems. Set IOMMU_MMIO for DMA_ATTR_MMIO.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index ea2ef53bd4fe..e1185ba73e23 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -724,7 +724,12 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, struct device *dev
 static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
 		     unsigned long attrs)
 {
-	int prot = coherent ? IOMMU_CACHE : 0;
+	int prot;
+
+	if (attrs & DMA_ATTR_MMIO)
+		prot = IOMMU_MMIO;
+	else
+		prot = coherent ? IOMMU_CACHE : 0;
 
 	if (attrs & DMA_ATTR_PRIVILEGED)
 		prot |= IOMMU_PRIV;
@@ -1838,12 +1843,13 @@ static int __dma_iova_link(struct device *dev, dma_addr_t addr,
 		unsigned long attrs)
 {
 	bool coherent = dev_is_dma_coherent(dev);
+	int prot = dma_info_to_prot(dir, coherent, attrs);
 
-	if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+	if (!coherent && !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
 		arch_sync_dma_for_device(phys, size, dir);
 
 	return iommu_map_nosync(iommu_get_dma_domain(dev), addr, phys, size,
-			dma_info_to_prot(dir, coherent, attrs), GFP_ATOMIC);
+			prot, GFP_ATOMIC);
 }
 
 static int iommu_dma_iova_bounce_and_link(struct device *dev, dma_addr_t addr,
@@ -1949,9 +1955,13 @@ int dma_iova_link(struct device *dev, struct dma_iova_state *state,
 		return -EIO;
 
 	if (dev_use_swiotlb(dev, size, dir) &&
-	    iova_unaligned(iovad, phys, size))
+	    iova_unaligned(iovad, phys, size)) {
+		if (attrs & DMA_ATTR_MMIO)
+			return -EPERM;
+
 		return iommu_dma_iova_link_swiotlb(dev, state, phys, offset,
 				size, dir, attrs);
+	}
 
 	return __dma_iova_link(dev, state->addr + offset - iova_start_pad,
 			phys - iova_start_pad,
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v3 07/16] dma-mapping: convert dma_direct_*map_page to be phys_addr_t based
Date: Thu, 14 Aug 2025 20:53:58 +0300
Message-ID: <3faa9c978e243a904ffe01496148c4563dc9274e.1755193625.git.leon@kernel.org>
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From: Leon Romanovsky 

Convert the DMA direct mapping functions to accept physical addresses
directly instead of page+offset parameters. The functions were already
operating on physical addresses internally, so this change eliminates
the redundant page-to-physical conversion at the API boundary.

The functions dma_direct_map_page() and dma_direct_unmap_page() are
renamed to dma_direct_map_phys() and dma_direct_unmap_phys() respectively,
with their calling convention changed from (struct page *page,
unsigned long offset) to (phys_addr_t phys).

Architecture-specific functions arch_dma_map_page_direct() and
arch_dma_unmap_page_direct() are similarly renamed to
arch_dma_map_phys_direct() and arch_dma_unmap_phys_direct().

The is_pci_p2pdma_page() checks are replaced with DMA_ATTR_MMIO checks
to allow integration with dma_direct_map_resource and dma_direct_map_phys()
is extended to support MMIO path either.

Signed-off-by: Leon Romanovsky 
---
 arch/powerpc/kernel/dma-iommu.c |  4 +--
 include/linux/dma-map-ops.h     |  8 ++---
 kernel/dma/direct.c             |  6 ++--
 kernel/dma/direct.h             | 52 +++++++++++++++++++++------------
 kernel/dma/mapping.c            |  8 ++---
 5 files changed, 46 insertions(+), 32 deletions(-)

diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index 4d64a5db50f3..0359ab72cd3b 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -14,7 +14,7 @@
 #define can_map_direct(dev, addr) \
 	((dev)->bus_dma_limit >= phys_to_dma((dev), (addr)))
 
-bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr)
+bool arch_dma_map_phys_direct(struct device *dev, phys_addr_t addr)
 {
 	if (likely(!dev->bus_dma_limit))
 		return false;
@@ -24,7 +24,7 @@ bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr)
 
 #define is_direct_handle(dev, h) ((h) >= (dev)->archdata.dma_offset)
 
-bool arch_dma_unmap_page_direct(struct device *dev, dma_addr_t dma_handle)
+bool arch_dma_unmap_phys_direct(struct device *dev, dma_addr_t dma_handle)
 {
 	if (likely(!dev->bus_dma_limit))
 		return false;
diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
index f48e5fb88bd5..71f5b3025415 100644
--- a/include/linux/dma-map-ops.h
+++ b/include/linux/dma-map-ops.h
@@ -392,15 +392,15 @@ void *arch_dma_set_uncached(void *addr, size_t size);
 void arch_dma_clear_uncached(void *addr, size_t size);
 
 #ifdef CONFIG_ARCH_HAS_DMA_MAP_DIRECT
-bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr);
-bool arch_dma_unmap_page_direct(struct device *dev, dma_addr_t dma_handle);
+bool arch_dma_map_phys_direct(struct device *dev, phys_addr_t addr);
+bool arch_dma_unmap_phys_direct(struct device *dev, dma_addr_t dma_handle);
 bool arch_dma_map_sg_direct(struct device *dev, struct scatterlist *sg,
 		int nents);
 bool arch_dma_unmap_sg_direct(struct device *dev, struct scatterlist *sg,
 		int nents);
 #else
-#define arch_dma_map_page_direct(d, a)		(false)
-#define arch_dma_unmap_page_direct(d, a)	(false)
+#define arch_dma_map_phys_direct(d, a)		(false)
+#define arch_dma_unmap_phys_direct(d, a)	(false)
 #define arch_dma_map_sg_direct(d, s, n)		(false)
 #define arch_dma_unmap_sg_direct(d, s, n)	(false)
 #endif
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 24c359d9c879..fa75e3070073 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -453,7 +453,7 @@ void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
 		if (sg_dma_is_bus_address(sg))
 			sg_dma_unmark_bus_address(sg);
 		else
-			dma_direct_unmap_page(dev, sg->dma_address,
+			dma_direct_unmap_phys(dev, sg->dma_address,
 					      sg_dma_len(sg), dir, attrs);
 	}
 }
@@ -476,8 +476,8 @@ int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
 			 */
 			break;
 		case PCI_P2PDMA_MAP_NONE:
-			sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
-					sg->offset, sg->length, dir, attrs);
+			sg->dma_address = dma_direct_map_phys(dev, sg_phys(sg),
+					sg->length, dir, attrs);
 			if (sg->dma_address == DMA_MAPPING_ERROR) {
 				ret = -EIO;
 				goto out_unmap;
diff --git a/kernel/dma/direct.h b/kernel/dma/direct.h
index d2c0b7e632fc..92dbadcd3b2f 100644
--- a/kernel/dma/direct.h
+++ b/kernel/dma/direct.h
@@ -80,42 +80,56 @@ static inline void dma_direct_sync_single_for_cpu(struct device *dev,
 		arch_dma_mark_clean(paddr, size);
 }
 
-static inline dma_addr_t dma_direct_map_page(struct device *dev,
-		struct page *page, unsigned long offset, size_t size,
-		enum dma_data_direction dir, unsigned long attrs)
+static inline dma_addr_t dma_direct_map_phys(struct device *dev,
+		phys_addr_t phys, size_t size, enum dma_data_direction dir,
+		unsigned long attrs)
 {
-	phys_addr_t phys = page_to_phys(page) + offset;
-	dma_addr_t dma_addr = phys_to_dma(dev, phys);
+	dma_addr_t dma_addr;
+	bool capable;
 
 	if (is_swiotlb_force_bounce(dev)) {
-		if (is_pci_p2pdma_page(page))
-			return DMA_MAPPING_ERROR;
+		if (attrs & DMA_ATTR_MMIO)
+			goto err_overflow;
+
 		return swiotlb_map(dev, phys, size, dir, attrs);
 	}
 
-	if (unlikely(!dma_capable(dev, dma_addr, size, true)) ||
-	    dma_kmalloc_needs_bounce(dev, size, dir)) {
-		if (is_pci_p2pdma_page(page))
-			return DMA_MAPPING_ERROR;
-		if (is_swiotlb_active(dev))
+	if (attrs & DMA_ATTR_MMIO)
+		dma_addr = phys;
+	else
+		dma_addr = phys_to_dma(dev, phys);
+
+	capable = dma_capable(dev, dma_addr, size, !(attrs & DMA_ATTR_MMIO));
+	if (unlikely(!capable) || dma_kmalloc_needs_bounce(dev, size, dir)) {
+		if (is_swiotlb_active(dev) && !(attrs & DMA_ATTR_MMIO))
 			return swiotlb_map(dev, phys, size, dir, attrs);
 
-		dev_WARN_ONCE(dev, 1,
-			     "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
-			     &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
-		return DMA_MAPPING_ERROR;
+		goto err_overflow;
 	}
 
-	if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+	if (!dev_is_dma_coherent(dev) &&
+	    !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
 		arch_sync_dma_for_device(phys, size, dir);
 	return dma_addr;
+
+err_overflow:
+	dev_WARN_ONCE(
+		dev, 1,
+		"DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
+		&dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
+	return DMA_MAPPING_ERROR;
 }
 
-static inline void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
+static inline void dma_direct_unmap_phys(struct device *dev, dma_addr_t addr,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
-	phys_addr_t phys = dma_to_phys(dev, addr);
+	phys_addr_t phys;
+
+	if (attrs & DMA_ATTR_MMIO)
+		/* nothing to do: uncached and no swiotlb */
+		return;
 
+	phys = dma_to_phys(dev, addr);
 	if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
 		dma_direct_sync_single_for_cpu(dev, addr, size, dir);
 
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 58482536db9b..80481a873340 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -166,8 +166,8 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		return DMA_MAPPING_ERROR;
 
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_map_page_direct(dev, phys + size))
-		addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
+	    arch_dma_map_phys_direct(dev, phys + size))
+		addr = dma_direct_map_phys(dev, phys, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
 	else
@@ -187,8 +187,8 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 
 	BUG_ON(!valid_dma_direction(dir));
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_unmap_page_direct(dev, addr + size))
-		dma_direct_unmap_page(dev, addr, size, dir, attrs);
+	    arch_dma_unmap_phys_direct(dev, addr + size))
+		dma_direct_unmap_phys(dev, addr, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
 	else
-- 
2.50.1



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	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
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Subject: [PATCH v3 08/16] kmsan: convert kmsan_handle_dma to use physical addresses
Date: Thu, 14 Aug 2025 20:53:59 +0300
Message-ID: <38de1c5ffb567c5705826f14742fcaf54522c083.1755193625.git.leon@kernel.org>
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From: Leon Romanovsky 

Convert the KMSAN DMA handling function from page-based to physical
address-based interface.

The refactoring renames kmsan_handle_dma() parameters from accepting
(struct page *page, size_t offset, size_t size) to (phys_addr_t phys,
size_t size). The existing semantics where callers are expected to
provide only kmap memory is continued here.

Signed-off-by: Leon Romanovsky 
---
 drivers/virtio/virtio_ring.c | 4 ++--
 include/linux/kmsan.h        | 9 ++++-----
 kernel/dma/mapping.c         | 3 ++-
 mm/kmsan/hooks.c             | 7 ++++---
 tools/virtio/linux/kmsan.h   | 2 +-
 5 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index f5062061c408..c147145a6593 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -378,7 +378,7 @@ static int vring_map_one_sg(const struct vring_virtqueue *vq, struct scatterlist
 		 * is initialized by the hardware. Explicitly check/unpoison it
 		 * depending on the direction.
 		 */
-		kmsan_handle_dma(sg_page(sg), sg->offset, sg->length, direction);
+		kmsan_handle_dma(sg_phys(sg), sg->length, direction);
 		*addr = (dma_addr_t)sg_phys(sg);
 		return 0;
 	}
@@ -3157,7 +3157,7 @@ dma_addr_t virtqueue_dma_map_single_attrs(struct virtqueue *_vq, void *ptr,
 	struct vring_virtqueue *vq = to_vvq(_vq);
 
 	if (!vq->use_dma_api) {
-		kmsan_handle_dma(virt_to_page(ptr), offset_in_page(ptr), size, dir);
+		kmsan_handle_dma(virt_to_phys(ptr), size, dir);
 		return (dma_addr_t)virt_to_phys(ptr);
 	}
 
diff --git a/include/linux/kmsan.h b/include/linux/kmsan.h
index 2b1432cc16d5..f2fd221107bb 100644
--- a/include/linux/kmsan.h
+++ b/include/linux/kmsan.h
@@ -182,8 +182,7 @@ void kmsan_iounmap_page_range(unsigned long start, unsigned long end);
 
 /**
  * kmsan_handle_dma() - Handle a DMA data transfer.
- * @page:   first page of the buffer.
- * @offset: offset of the buffer within the first page.
+ * @phys:   physical address of the buffer.
  * @size:   buffer size.
  * @dir:    one of possible dma_data_direction values.
  *
@@ -192,7 +191,7 @@ void kmsan_iounmap_page_range(unsigned long start, unsigned long end);
  * * initializes the buffer, if it is copied from device;
  * * does both, if this is a DMA_BIDIRECTIONAL transfer.
  */
-void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
+void kmsan_handle_dma(phys_addr_t phys, size_t size,
 		      enum dma_data_direction dir);
 
 /**
@@ -372,8 +371,8 @@ static inline void kmsan_iounmap_page_range(unsigned long start,
 {
 }
 
-static inline void kmsan_handle_dma(struct page *page, size_t offset,
-				    size_t size, enum dma_data_direction dir)
+static inline void kmsan_handle_dma(phys_addr_t phys, size_t size,
+				    enum dma_data_direction dir)
 {
 }
 
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 80481a873340..891e1fc3e582 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -172,7 +172,8 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
-	kmsan_handle_dma(page, offset, size, dir);
+
+	kmsan_handle_dma(phys, size, dir);
 	trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
 	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
diff --git a/mm/kmsan/hooks.c b/mm/kmsan/hooks.c
index 97de3d6194f0..a080400290e7 100644
--- a/mm/kmsan/hooks.c
+++ b/mm/kmsan/hooks.c
@@ -336,14 +336,15 @@ static void kmsan_handle_dma_page(const void *addr, size_t size,
 }
 
 /* Helper function to handle DMA data transfers. */
-void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
-		      enum dma_data_direction dir)
+void kmsan_handle_dma(phys_addr_t phys, size_t size,
+		      enum dma_data_direction dir, unsigned int attrs)
 {
+	struct page *page = phys_to_page(phys);
 	u64 page_offset, to_go, addr;
 
 	if (PageHighMem(page))
 		return;
-	addr = (u64)page_address(page) + offset;
+	addr = (u64)page_address(page) + offset_in_page(phys);
 	/*
 	 * The kernel may occasionally give us adjacent DMA pages not belonging
 	 * to the same allocation. Process them separately to avoid triggering
diff --git a/tools/virtio/linux/kmsan.h b/tools/virtio/linux/kmsan.h
index 272b5aa285d5..6cd2e3efd03d 100644
--- a/tools/virtio/linux/kmsan.h
+++ b/tools/virtio/linux/kmsan.h
@@ -4,7 +4,7 @@
 
 #include 
 
-inline void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
+inline void kmsan_handle_dma(phys_addr_t phys, size_t size,
 			     enum dma_data_direction dir)
 {
 }
-- 
2.50.1



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	Christoph Hellwig ,
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Subject: [PATCH v3 14/16] block-dma: migrate to dma_map_phys instead of map_page
Date: Thu, 14 Aug 2025 20:54:05 +0300
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From: Leon Romanovsky 

After introduction of dma_map_phys(), there is no need to convert
from physical address to struct page in order to map page. So let's
use it directly.

Signed-off-by: Leon Romanovsky 
---
 block/blk-mq-dma.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/block/blk-mq-dma.c b/block/blk-mq-dma.c
index ad283017caef..37e2142be4f7 100644
--- a/block/blk-mq-dma.c
+++ b/block/blk-mq-dma.c
@@ -87,8 +87,8 @@ static bool blk_dma_map_bus(struct blk_dma_iter *iter, struct phys_vec *vec)
 static bool blk_dma_map_direct(struct request *req, struct device *dma_dev,
 		struct blk_dma_iter *iter, struct phys_vec *vec)
 {
-	iter->addr = dma_map_page(dma_dev, phys_to_page(vec->paddr),
-			offset_in_page(vec->paddr), vec->len, rq_dma_dir(req));
+	iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len,
+			rq_dma_dir(req), 0);
 	if (dma_mapping_error(dma_dev, iter->addr)) {
 		iter->status = BLK_STS_RESOURCE;
 		return false;
-- 
2.50.1



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	Christoph Hellwig ,
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Subject: [PATCH v3 10/16] xen: swiotlb: Open code map_resource callback
Date: Thu, 14 Aug 2025 20:54:01 +0300
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From: Leon Romanovsky 

General dma_direct_map_resource() is going to be removed
in next patch, so simply open-code it in xen driver.

Reviewed-by: Juergen Gross 
Signed-off-by: Leon Romanovsky 
---
 drivers/xen/swiotlb-xen.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c
index da1a7d3d377c..dd7747a2de87 100644
--- a/drivers/xen/swiotlb-xen.c
+++ b/drivers/xen/swiotlb-xen.c
@@ -392,6 +392,25 @@ xen_swiotlb_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
 	}
 }
 
+static dma_addr_t xen_swiotlb_direct_map_resource(struct device *dev,
+						  phys_addr_t paddr,
+						  size_t size,
+						  enum dma_data_direction dir,
+						  unsigned long attrs)
+{
+	dma_addr_t dma_addr = paddr;
+
+	if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
+		dev_err_once(dev,
+			     "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
+			     &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
+		WARN_ON_ONCE(1);
+		return DMA_MAPPING_ERROR;
+	}
+
+	return dma_addr;
+}
+
 /*
  * Return whether the given device DMA address mask can be supported
  * properly.  For example, if your device can only drive the low 24-bits
@@ -426,5 +445,5 @@ const struct dma_map_ops xen_swiotlb_dma_ops = {
 	.alloc_pages_op = dma_common_alloc_pages,
 	.free_pages = dma_common_free_pages,
 	.max_mapping_size = swiotlb_max_mapping_size,
-	.map_resource = dma_direct_map_resource,
+	.map_resource = xen_swiotlb_direct_map_resource,
 };
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
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	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v3 09/16] dma-mapping: handle MMIO flow in dma_map|unmap_page
Date: Thu, 14 Aug 2025 20:54:00 +0300
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From: Leon Romanovsky 

Extend base DMA page API to handle MMIO flow and follow
existing dma_map_resource() implementation to rely on dma_map_direct()
only to take DMA direct path.

Signed-off-by: Leon Romanovsky 
---
 kernel/dma/mapping.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 891e1fc3e582..fdabfdaeff1d 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -158,6 +158,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
 	phys_addr_t phys = page_to_phys(page) + offset;
+	bool is_mmio = attrs & DMA_ATTR_MMIO;
 	dma_addr_t addr;
 
 	BUG_ON(!valid_dma_direction(dir));
@@ -166,14 +167,25 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		return DMA_MAPPING_ERROR;
 
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_map_phys_direct(dev, phys + size))
+	    (!is_mmio && arch_dma_map_phys_direct(dev, phys + size)))
 		addr = dma_direct_map_phys(dev, phys, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
-	else
+	else if (is_mmio) {
+		if (!ops->map_resource)
+			return DMA_MAPPING_ERROR;
+
+		addr = ops->map_resource(dev, phys, size, dir, attrs);
+	} else {
+		/*
+		 * The dma_ops API contract for ops->map_page() requires
+		 * kmappable memory, while ops->map_resource() does not.
+		 */
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
+	}
 
-	kmsan_handle_dma(phys, size, dir);
+	if (!is_mmio)
+		kmsan_handle_dma(phys, size, dir);
 	trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
 	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
@@ -185,14 +197,18 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
+	bool is_mmio = attrs & DMA_ATTR_MMIO;
 
 	BUG_ON(!valid_dma_direction(dir));
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_unmap_phys_direct(dev, addr + size))
+	    (!is_mmio && arch_dma_unmap_phys_direct(dev, addr + size)))
 		dma_direct_unmap_phys(dev, addr, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
-	else
+	else if (is_mmio) {
+		if (ops->unmap_resource)
+			ops->unmap_resource(dev, addr, size, dir, attrs);
+	} else
 		ops->unmap_page(dev, addr, size, dir, attrs);
 	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
 	debug_dma_unmap_phys(dev, addr, size, dir);
-- 
2.50.1



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	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
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Subject: [PATCH v3 06/16] iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory
Date: Thu, 14 Aug 2025 20:53:57 +0300
Message-ID: <4f84639baf6d5d0e107fd2001dff91b6538ff9ae.1755193625.git.leon@kernel.org>
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From: Leon Romanovsky 

Combine iommu_dma_*map_phys with iommu_dma_*map_resource interfaces in
order to allow single phys_addr_t flow.

In the following patches, the iommu_dma_map_resource() will be removed
in favour of iommu_dma_map_phys(..., attrs | DMA_ATTR_MMIO) flow.

Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index aea119f32f96..6804aaf034a1 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -1211,16 +1211,19 @@ dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
 	 */
 	if (dev_use_swiotlb(dev, size, dir) &&
 	    iova_unaligned(iovad, phys, size)) {
+		if (attrs & DMA_ATTR_MMIO)
+			return DMA_MAPPING_ERROR;
+
 		phys = iommu_dma_map_swiotlb(dev, phys, size, dir, attrs);
 		if (phys == (phys_addr_t)DMA_MAPPING_ERROR)
 			return DMA_MAPPING_ERROR;
 	}
 
-	if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+	if (!coherent && !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
 		arch_sync_dma_for_device(phys, size, dir);
 
 	iova = __iommu_dma_map(dev, phys, size, prot, dma_mask);
-	if (iova == DMA_MAPPING_ERROR)
+	if (iova == DMA_MAPPING_ERROR && !(attrs & DMA_ATTR_MMIO))
 		swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
 	return iova;
 }
@@ -1228,10 +1231,14 @@ dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
 void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
-	struct iommu_domain *domain = iommu_get_dma_domain(dev);
 	phys_addr_t phys;
 
-	phys = iommu_iova_to_phys(domain, dma_handle);
+	if (attrs & DMA_ATTR_MMIO) {
+		__iommu_dma_unmap(dev, dma_handle, size);
+		return;
+	}
+
+	phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
 	if (WARN_ON(!phys))
 		return;
 
-- 
2.50.1



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	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
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Subject: [PATCH v3 13/16] mm/hmm: properly take MMIO path
Date: Thu, 14 Aug 2025 20:54:04 +0300
Message-ID: <44e4937b3d906a77a6b905946f8a74b49659b0c7.1755193625.git.leon@kernel.org>
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From: Leon Romanovsky 

In case peer-to-peer transaction traverses through host bridge,
the IOMMU needs to have IOMMU_MMIO flag, together with skip of
CPU sync.

The latter was handled by provided DMA_ATTR_SKIP_CPU_SYNC flag,
but IOMMU flag was missed, due to assumption that such memory
can be treated as regular one.

Reuse newly introduced DMA attribute to properly take MMIO path.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 mm/hmm.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index 015ab243f081..6556c0e074ba 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -746,7 +746,7 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
 	case PCI_P2PDMA_MAP_NONE:
 		break;
 	case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
-		attrs |= DMA_ATTR_SKIP_CPU_SYNC;
+		attrs |= DMA_ATTR_MMIO;
 		pfns[idx] |= HMM_PFN_P2PDMA;
 		break;
 	case PCI_P2PDMA_MAP_BUS_ADDR:
@@ -776,7 +776,7 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
 			goto error;
 
 		dma_addr = dma_map_phys(dev, paddr, map->dma_entry_size,
-					DMA_BIDIRECTIONAL, 0);
+					DMA_BIDIRECTIONAL, attrs);
 		if (dma_mapping_error(dev, dma_addr))
 			goto error;
 
@@ -811,16 +811,17 @@ bool hmm_dma_unmap_pfn(struct device *dev, struct hmm_dma_map *map, size_t idx)
 	if ((pfns[idx] & valid_dma) != valid_dma)
 		return false;
 
+	if (pfns[idx] & HMM_PFN_P2PDMA)
+		attrs |= DMA_ATTR_MMIO;
+
 	if (pfns[idx] & HMM_PFN_P2PDMA_BUS)
 		; /* no need to unmap bus address P2P mappings */
-	else if (dma_use_iova(state)) {
-		if (pfns[idx] & HMM_PFN_P2PDMA)
-			attrs |= DMA_ATTR_SKIP_CPU_SYNC;
+	else if (dma_use_iova(state))
 		dma_iova_unlink(dev, state, idx * map->dma_entry_size,
 				map->dma_entry_size, DMA_BIDIRECTIONAL, attrs);
-	} else if (dma_need_unmap(dev))
+	else if (dma_need_unmap(dev))
 		dma_unmap_phys(dev, dma_addrs[idx], map->dma_entry_size,
-			       DMA_BIDIRECTIONAL, 0);
+			       DMA_BIDIRECTIONAL, attrs);
 
 	pfns[idx] &=
 		~(HMM_PFN_DMA_MAPPED | HMM_PFN_P2PDMA | HMM_PFN_P2PDMA_BUS);
-- 
2.50.1



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	h=From:To:Cc:Subject:Date:In-Reply-To:References:From;
	b=bHYYYSKADkxeM+Ac633UQDO/08P4WWJTTsQl6m+kz2gOcj8R6CGIb+RC3QVMGasAO
	 iE4XCWhrY43gFBXiJfGMDzXyrHd/xdFbEE5B/LB87/iG3WQ3/X7WbArlsB60JDMvAU
	 OwxHcEOW9uU/lMZm5JAciboMdjyBuVRnwXVSRTCXBrqUUlUZchH25gVP39l6u48+kM
	 1v/6/EFZL+vpAJJ5gImSNIz7k+Naq8cBnwZCewYDLppEr9TXTVNb2Nmb6PCb3031OG
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	 PT0+RUPfXFSQA==
From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v3 11/16] dma-mapping: export new dma_*map_phys() interface
Date: Thu, 14 Aug 2025 20:54:02 +0300
Message-ID: <60724b0fdc808c8290014ae38a2ee5d9f3d091ee.1755193625.git.leon@kernel.org>
X-Mailer: git-send-email 2.50.1
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From: Leon Romanovsky 

Introduce new DMA mapping functions dma_map_phys() and dma_unmap_phys()
that operate directly on physical addresses instead of page+offset
parameters. This provides a more efficient interface for drivers that
already have physical addresses available.

The new functions are implemented as the primary mapping layer, with
the existing dma_map_page_attrs()/dma_map_resource() and
dma_unmap_page_attrs()/dma_unmap_resource() functions converted to simple
wrappers around the phys-based implementations.

In case dma_map_page_attrs(), the struct page is converted to physical
address with help of page_to_phys() function and dma_map_resource()
provides physical address as is together with addition of DMA_ATTR_MMIO
attribute.

The old page-based API is preserved in mapping.c to ensure that existing
code won't be affected by changing EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
variant for dma_*map_phys().

Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c   | 14 --------
 include/linux/dma-direct.h  |  2 --
 include/linux/dma-mapping.h | 13 +++++++
 include/linux/iommu-dma.h   |  4 ---
 include/trace/events/dma.h  |  2 --
 kernel/dma/debug.c          | 43 -----------------------
 kernel/dma/debug.h          | 21 -----------
 kernel/dma/direct.c         | 16 ---------
 kernel/dma/mapping.c        | 69 ++++++++++++++++++++-----------------
 9 files changed, 50 insertions(+), 134 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 6804aaf034a1..7944a3af4545 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -1556,20 +1556,6 @@ void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
 		__iommu_dma_unmap(dev, start, end - start);
 }
 
-dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
-		size_t size, enum dma_data_direction dir, unsigned long attrs)
-{
-	return __iommu_dma_map(dev, phys, size,
-			dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO,
-			dma_get_mask(dev));
-}
-
-void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
-		size_t size, enum dma_data_direction dir, unsigned long attrs)
-{
-	__iommu_dma_unmap(dev, handle, size);
-}
-
 static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr)
 {
 	size_t alloc_size = PAGE_ALIGN(size);
diff --git a/include/linux/dma-direct.h b/include/linux/dma-direct.h
index f3bc0bcd7098..c249912456f9 100644
--- a/include/linux/dma-direct.h
+++ b/include/linux/dma-direct.h
@@ -149,7 +149,5 @@ void dma_direct_free_pages(struct device *dev, size_t size,
 		struct page *page, dma_addr_t dma_addr,
 		enum dma_data_direction dir);
 int dma_direct_supported(struct device *dev, u64 mask);
-dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
-		size_t size, enum dma_data_direction dir, unsigned long attrs);
 
 #endif /* _LINUX_DMA_DIRECT_H */
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 4254fd9bdf5d..8248ff9363ee 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -138,6 +138,10 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		unsigned long attrs);
 void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs);
+dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs);
+void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size,
+		enum dma_data_direction dir, unsigned long attrs);
 unsigned int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
 		int nents, enum dma_data_direction dir, unsigned long attrs);
 void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg,
@@ -192,6 +196,15 @@ static inline void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
 }
+static inline dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys,
+		size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+	return DMA_MAPPING_ERROR;
+}
+static inline void dma_unmap_phys(struct device *dev, dma_addr_t addr,
+		size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+}
 static inline unsigned int dma_map_sg_attrs(struct device *dev,
 		struct scatterlist *sg, int nents, enum dma_data_direction dir,
 		unsigned long attrs)
diff --git a/include/linux/iommu-dma.h b/include/linux/iommu-dma.h
index 485bdffed988..a92b3ff9b934 100644
--- a/include/linux/iommu-dma.h
+++ b/include/linux/iommu-dma.h
@@ -42,10 +42,6 @@ size_t iommu_dma_opt_mapping_size(void);
 size_t iommu_dma_max_mapping_size(struct device *dev);
 void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr,
 		dma_addr_t handle, unsigned long attrs);
-dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
-		size_t size, enum dma_data_direction dir, unsigned long attrs);
-void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
-		size_t size, enum dma_data_direction dir, unsigned long attrs);
 struct sg_table *iommu_dma_alloc_noncontiguous(struct device *dev, size_t size,
 		enum dma_data_direction dir, gfp_t gfp, unsigned long attrs);
 void iommu_dma_free_noncontiguous(struct device *dev, size_t size,
diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h
index 84416c7d6bfa..5da59fd8121d 100644
--- a/include/trace/events/dma.h
+++ b/include/trace/events/dma.h
@@ -73,7 +73,6 @@ DEFINE_EVENT(dma_map, name, \
 	TP_ARGS(dev, phys_addr, dma_addr, size, dir, attrs))
 
 DEFINE_MAP_EVENT(dma_map_phys);
-DEFINE_MAP_EVENT(dma_map_resource);
 
 DECLARE_EVENT_CLASS(dma_unmap,
 	TP_PROTO(struct device *dev, dma_addr_t addr, size_t size,
@@ -111,7 +110,6 @@ DEFINE_EVENT(dma_unmap, name, \
 	TP_ARGS(dev, addr, size, dir, attrs))
 
 DEFINE_UNMAP_EVENT(dma_unmap_phys);
-DEFINE_UNMAP_EVENT(dma_unmap_resource);
 
 DECLARE_EVENT_CLASS(dma_alloc_class,
 	TP_PROTO(struct device *dev, void *virt_addr, dma_addr_t dma_addr,
diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c
index da6734e3a4ce..06e31fd216e3 100644
--- a/kernel/dma/debug.c
+++ b/kernel/dma/debug.c
@@ -38,7 +38,6 @@ enum {
 	dma_debug_single,
 	dma_debug_sg,
 	dma_debug_coherent,
-	dma_debug_resource,
 	dma_debug_phy,
 };
 
@@ -141,7 +140,6 @@ static const char *type2name[] = {
 	[dma_debug_single] = "single",
 	[dma_debug_sg] = "scatter-gather",
 	[dma_debug_coherent] = "coherent",
-	[dma_debug_resource] = "resource",
 	[dma_debug_phy] = "phy",
 };
 
@@ -1448,47 +1446,6 @@ void debug_dma_free_coherent(struct device *dev, size_t size,
 	check_unmap(&ref);
 }
 
-void debug_dma_map_resource(struct device *dev, phys_addr_t addr, size_t size,
-			    int direction, dma_addr_t dma_addr,
-			    unsigned long attrs)
-{
-	struct dma_debug_entry *entry;
-
-	if (unlikely(dma_debug_disabled()))
-		return;
-
-	entry = dma_entry_alloc();
-	if (!entry)
-		return;
-
-	entry->type		= dma_debug_resource;
-	entry->dev		= dev;
-	entry->paddr		= addr;
-	entry->size		= size;
-	entry->dev_addr		= dma_addr;
-	entry->direction	= direction;
-	entry->map_err_type	= MAP_ERR_NOT_CHECKED;
-
-	add_dma_entry(entry, attrs);
-}
-
-void debug_dma_unmap_resource(struct device *dev, dma_addr_t dma_addr,
-			      size_t size, int direction)
-{
-	struct dma_debug_entry ref = {
-		.type           = dma_debug_resource,
-		.dev            = dev,
-		.dev_addr       = dma_addr,
-		.size           = size,
-		.direction      = direction,
-	};
-
-	if (unlikely(dma_debug_disabled()))
-		return;
-
-	check_unmap(&ref);
-}
-
 void debug_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 				   size_t size, int direction)
 {
diff --git a/kernel/dma/debug.h b/kernel/dma/debug.h
index 76adb42bffd5..424b8f912ade 100644
--- a/kernel/dma/debug.h
+++ b/kernel/dma/debug.h
@@ -30,14 +30,6 @@ extern void debug_dma_alloc_coherent(struct device *dev, size_t size,
 extern void debug_dma_free_coherent(struct device *dev, size_t size,
 				    void *virt, dma_addr_t addr);
 
-extern void debug_dma_map_resource(struct device *dev, phys_addr_t addr,
-				   size_t size, int direction,
-				   dma_addr_t dma_addr,
-				   unsigned long attrs);
-
-extern void debug_dma_unmap_resource(struct device *dev, dma_addr_t dma_addr,
-				     size_t size, int direction);
-
 extern void debug_dma_sync_single_for_cpu(struct device *dev,
 					  dma_addr_t dma_handle, size_t size,
 					  int direction);
@@ -88,19 +80,6 @@ static inline void debug_dma_free_coherent(struct device *dev, size_t size,
 {
 }
 
-static inline void debug_dma_map_resource(struct device *dev, phys_addr_t addr,
-					  size_t size, int direction,
-					  dma_addr_t dma_addr,
-					  unsigned long attrs)
-{
-}
-
-static inline void debug_dma_unmap_resource(struct device *dev,
-					    dma_addr_t dma_addr, size_t size,
-					    int direction)
-{
-}
-
 static inline void debug_dma_sync_single_for_cpu(struct device *dev,
 						 dma_addr_t dma_handle,
 						 size_t size, int direction)
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index fa75e3070073..1062caac47e7 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -502,22 +502,6 @@ int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
 	return ret;
 }
 
-dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
-		size_t size, enum dma_data_direction dir, unsigned long attrs)
-{
-	dma_addr_t dma_addr = paddr;
-
-	if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
-		dev_err_once(dev,
-			     "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
-			     &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
-		WARN_ON_ONCE(1);
-		return DMA_MAPPING_ERROR;
-	}
-
-	return dma_addr;
-}
-
 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
 		void *cpu_addr, dma_addr_t dma_addr, size_t size,
 		unsigned long attrs)
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index fdabfdaeff1d..0ca098d2e88d 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -152,12 +152,10 @@ static inline bool dma_map_direct(struct device *dev,
 	return dma_go_direct(dev, *dev->dma_mask, ops);
 }
 
-dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
-		size_t offset, size_t size, enum dma_data_direction dir,
-		unsigned long attrs)
+dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
-	phys_addr_t phys = page_to_phys(page) + offset;
 	bool is_mmio = attrs & DMA_ATTR_MMIO;
 	dma_addr_t addr;
 
@@ -177,6 +175,9 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 
 		addr = ops->map_resource(dev, phys, size, dir, attrs);
 	} else {
+		struct page *page = phys_to_page(phys);
+		size_t offset = offset_in_page(phys);
+
 		/*
 		 * The dma_ops API contract for ops->map_page() requires
 		 * kmappable memory, while ops->map_resource() does not.
@@ -191,9 +192,26 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 
 	return addr;
 }
+EXPORT_SYMBOL_GPL(dma_map_phys);
+
+dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
+		size_t offset, size_t size, enum dma_data_direction dir,
+		unsigned long attrs)
+{
+	phys_addr_t phys = page_to_phys(page) + offset;
+
+	if (unlikely(attrs & DMA_ATTR_MMIO))
+		return DMA_MAPPING_ERROR;
+
+	if (IS_ENABLED(CONFIG_DMA_API_DEBUG) &&
+	    WARN_ON_ONCE(is_zone_device_page(page)))
+		return DMA_MAPPING_ERROR;
+
+	return dma_map_phys(dev, phys, size, dir, attrs);
+}
 EXPORT_SYMBOL(dma_map_page_attrs);
 
-void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
+void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
@@ -213,6 +231,16 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
 	debug_dma_unmap_phys(dev, addr, size, dir);
 }
+EXPORT_SYMBOL_GPL(dma_unmap_phys);
+
+void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
+		 enum dma_data_direction dir, unsigned long attrs)
+{
+	if (unlikely(attrs & DMA_ATTR_MMIO))
+		return;
+
+	dma_unmap_phys(dev, addr, size, dir, attrs);
+}
 EXPORT_SYMBOL(dma_unmap_page_attrs);
 
 static int __dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
@@ -338,41 +366,18 @@ EXPORT_SYMBOL(dma_unmap_sg_attrs);
 dma_addr_t dma_map_resource(struct device *dev, phys_addr_t phys_addr,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
-	const struct dma_map_ops *ops = get_dma_ops(dev);
-	dma_addr_t addr = DMA_MAPPING_ERROR;
-
-	BUG_ON(!valid_dma_direction(dir));
-
-	if (WARN_ON_ONCE(!dev->dma_mask))
+	if (IS_ENABLED(CONFIG_DMA_API_DEBUG) &&
+	    WARN_ON_ONCE(pfn_valid(PHYS_PFN(phys_addr))))
 		return DMA_MAPPING_ERROR;
 
-	if (dma_map_direct(dev, ops))
-		addr = dma_direct_map_resource(dev, phys_addr, size, dir, attrs);
-	else if (use_dma_iommu(dev))
-		addr = iommu_dma_map_resource(dev, phys_addr, size, dir, attrs);
-	else if (ops->map_resource)
-		addr = ops->map_resource(dev, phys_addr, size, dir, attrs);
-
-	trace_dma_map_resource(dev, phys_addr, addr, size, dir, attrs);
-	debug_dma_map_resource(dev, phys_addr, size, dir, addr, attrs);
-	return addr;
+	return dma_map_phys(dev, phys_addr, size, dir, attrs | DMA_ATTR_MMIO);
 }
 EXPORT_SYMBOL(dma_map_resource);
 
 void dma_unmap_resource(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs)
 {
-	const struct dma_map_ops *ops = get_dma_ops(dev);
-
-	BUG_ON(!valid_dma_direction(dir));
-	if (dma_map_direct(dev, ops))
-		; /* nothing to do: uncached and no swiotlb */
-	else if (use_dma_iommu(dev))
-		iommu_dma_unmap_resource(dev, addr, size, dir, attrs);
-	else if (ops->unmap_resource)
-		ops->unmap_resource(dev, addr, size, dir, attrs);
-	trace_dma_unmap_resource(dev, addr, size, dir, attrs);
-	debug_dma_unmap_resource(dev, addr, size, dir);
+	dma_unmap_phys(dev, addr, size, dir, attrs | DMA_ATTR_MMIO);
 }
 EXPORT_SYMBOL(dma_unmap_resource);
 
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
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Subject: [PATCH v3 16/16] nvme-pci: unmap MMIO pages with appropriate interface
Date: Thu, 14 Aug 2025 20:54:07 +0300
Message-ID: <16e541279b4b030de54a0a2f1829e601b7923523.1755193625.git.leon@kernel.org>
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From: Leon Romanovsky 

Block layer maps MMIO memory through dma_map_phys() interface
with help of DMA_ATTR_MMIO attribute. There is a need to unmap
that memory with the appropriate unmap function, something which
wasn't possible before adding new REQ attribute to block layer in
previous patch.

Signed-off-by: Leon Romanovsky 
---
 drivers/nvme/host/pci.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 2c6d9506b172..f8ecc0e0f576 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -682,11 +682,15 @@ static void nvme_free_prps(struct request *req)
 {
 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
+	unsigned int attrs = 0;
 	unsigned int i;
 
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
+
 	for (i = 0; i < iod->nr_dma_vecs; i++)
-		dma_unmap_page(nvmeq->dev->dev, iod->dma_vecs[i].addr,
-				iod->dma_vecs[i].len, rq_dma_dir(req));
+		dma_unmap_phys(nvmeq->dev->dev, iod->dma_vecs[i].addr,
+				iod->dma_vecs[i].len, rq_dma_dir(req), attrs);
 	mempool_free(iod->dma_vecs, nvmeq->dev->dmavec_mempool);
 }
 
@@ -699,15 +703,19 @@ static void nvme_free_sgls(struct request *req)
 	unsigned int sqe_dma_len = le32_to_cpu(iod->cmd.common.dptr.sgl.length);
 	struct nvme_sgl_desc *sg_list = iod->descriptors[0];
 	enum dma_data_direction dir = rq_dma_dir(req);
+	unsigned int attrs = 0;
+
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
 
 	if (iod->nr_descriptors) {
 		unsigned int nr_entries = sqe_dma_len / sizeof(*sg_list), i;
 
 		for (i = 0; i < nr_entries; i++)
-			dma_unmap_page(dma_dev, le64_to_cpu(sg_list[i].addr),
-				le32_to_cpu(sg_list[i].length), dir);
+			dma_unmap_phys(dma_dev, le64_to_cpu(sg_list[i].addr),
+				le32_to_cpu(sg_list[i].length), dir, attrs);
 	} else {
-		dma_unmap_page(dma_dev, sqe_dma_addr, sqe_dma_len, dir);
+		dma_unmap_phys(dma_dev, sqe_dma_addr, sqe_dma_len, dir, attrs);
 	}
 }
 
-- 
2.50.1



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Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
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Subject: [PATCH v3 15/16] block-dma: properly take MMIO path
Date: Thu, 14 Aug 2025 20:54:06 +0300
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From: Leon Romanovsky 

Make sure that CPU is not synced and IOMMU is configured to take
MMIO path by providing newly introduced DMA_ATTR_MMIO attribute.

Signed-off-by: Leon Romanovsky 
---
 block/blk-mq-dma.c         | 13 +++++++++++--
 include/linux/blk-mq-dma.h |  6 +++++-
 include/linux/blk_types.h  |  2 ++
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/block/blk-mq-dma.c b/block/blk-mq-dma.c
index 37e2142be4f7..d415088ed9fd 100644
--- a/block/blk-mq-dma.c
+++ b/block/blk-mq-dma.c
@@ -87,8 +87,13 @@ static bool blk_dma_map_bus(struct blk_dma_iter *iter, struct phys_vec *vec)
 static bool blk_dma_map_direct(struct request *req, struct device *dma_dev,
 		struct blk_dma_iter *iter, struct phys_vec *vec)
 {
+	unsigned int attrs = 0;
+
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
+
 	iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len,
-			rq_dma_dir(req), 0);
+			rq_dma_dir(req), attrs);
 	if (dma_mapping_error(dma_dev, iter->addr)) {
 		iter->status = BLK_STS_RESOURCE;
 		return false;
@@ -103,14 +108,17 @@ static bool blk_rq_dma_map_iova(struct request *req, struct device *dma_dev,
 {
 	enum dma_data_direction dir = rq_dma_dir(req);
 	unsigned int mapped = 0;
+	unsigned int attrs = 0;
 	int error;
 
 	iter->addr = state->addr;
 	iter->len = dma_iova_size(state);
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
 
 	do {
 		error = dma_iova_link(dma_dev, state, vec->paddr, mapped,
-				vec->len, dir, 0);
+				vec->len, dir, attrs);
 		if (error)
 			break;
 		mapped += vec->len;
@@ -176,6 +184,7 @@ bool blk_rq_dma_map_iter_start(struct request *req, struct device *dma_dev,
 			 * same as non-P2P transfers below and during unmap.
 			 */
 			req->cmd_flags &= ~REQ_P2PDMA;
+			req->cmd_flags |= REQ_MMIO;
 			break;
 		default:
 			iter->status = BLK_STS_INVAL;
diff --git a/include/linux/blk-mq-dma.h b/include/linux/blk-mq-dma.h
index c26a01aeae00..6c55f5e58511 100644
--- a/include/linux/blk-mq-dma.h
+++ b/include/linux/blk-mq-dma.h
@@ -48,12 +48,16 @@ static inline bool blk_rq_dma_map_coalesce(struct dma_iova_state *state)
 static inline bool blk_rq_dma_unmap(struct request *req, struct device *dma_dev,
 		struct dma_iova_state *state, size_t mapped_len)
 {
+	unsigned int attrs = 0;
+
 	if (req->cmd_flags & REQ_P2PDMA)
 		return true;
 
 	if (dma_use_iova(state)) {
+		if (req->cmd_flags & REQ_MMIO)
+			attrs = DMA_ATTR_MMIO;
 		dma_iova_destroy(dma_dev, state, mapped_len, rq_dma_dir(req),
-				 0);
+				 attrs);
 		return true;
 	}
 
diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
index 09b99d52fd36..283058bcb5b1 100644
--- a/include/linux/blk_types.h
+++ b/include/linux/blk_types.h
@@ -387,6 +387,7 @@ enum req_flag_bits {
 	__REQ_FS_PRIVATE,	/* for file system (submitter) use */
 	__REQ_ATOMIC,		/* for atomic write operations */
 	__REQ_P2PDMA,		/* contains P2P DMA pages */
+	__REQ_MMIO,		/* contains MMIO memory */
 	/*
 	 * Command specific flags, keep last:
 	 */
@@ -420,6 +421,7 @@ enum req_flag_bits {
 #define REQ_FS_PRIVATE	(__force blk_opf_t)(1ULL << __REQ_FS_PRIVATE)
 #define REQ_ATOMIC	(__force blk_opf_t)(1ULL << __REQ_ATOMIC)
 #define REQ_P2PDMA	(__force blk_opf_t)(1ULL << __REQ_P2PDMA)
+#define REQ_MMIO	(__force blk_opf_t)(1ULL << __REQ_MMIO)
 
 #define REQ_NOUNMAP	(__force blk_opf_t)(1ULL << __REQ_NOUNMAP)
 
-- 
2.50.1



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	Alexander Potapenko ,
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	Christoph Hellwig ,
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Subject: [PATCH v3 12/16] mm/hmm: migrate to physical address-based DMA mapping API
Date: Thu, 14 Aug 2025 20:54:03 +0300
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From: Leon Romanovsky 

Convert HMM DMA operations from the legacy page-based API to the new
physical address-based dma_map_phys() and dma_unmap_phys() functions.
This demonstrates the preferred approach for new code that should use
physical addresses directly rather than page+offset parameters.

The change replaces dma_map_page() and dma_unmap_page() calls with
dma_map_phys() and dma_unmap_phys() respectively, using the physical
address that was already available in the code. This eliminates the
redundant page-to-physical address conversion and aligns with the
DMA subsystem's move toward physical address-centric interfaces.

This serves as an example of how new code should be written to leverage
the more efficient physical address API, which provides cleaner interfaces
for drivers that already have access to physical addresses.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 mm/hmm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index d545e2494994..015ab243f081 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -775,8 +775,8 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
 		if (WARN_ON_ONCE(dma_need_unmap(dev) && !dma_addrs))
 			goto error;
 
-		dma_addr = dma_map_page(dev, page, 0, map->dma_entry_size,
-					DMA_BIDIRECTIONAL);
+		dma_addr = dma_map_phys(dev, paddr, map->dma_entry_size,
+					DMA_BIDIRECTIONAL, 0);
 		if (dma_mapping_error(dev, dma_addr))
 			goto error;
 
@@ -819,8 +819,8 @@ bool hmm_dma_unmap_pfn(struct device *dev, struct hmm_dma_map *map, size_t idx)
 		dma_iova_unlink(dev, state, idx * map->dma_entry_size,
 				map->dma_entry_size, DMA_BIDIRECTIONAL, attrs);
 	} else if (dma_need_unmap(dev))
-		dma_unmap_page(dev, dma_addrs[idx], map->dma_entry_size,
-			       DMA_BIDIRECTIONAL);
+		dma_unmap_phys(dev, dma_addrs[idx], map->dma_entry_size,
+			       DMA_BIDIRECTIONAL, 0);
 
 	pfns[idx] &=
 		~(HMM_PFN_DMA_MAPPED | HMM_PFN_P2PDMA | HMM_PFN_P2PDMA_BUS);
-- 
2.50.1



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v1.1 08/22] x86/traps: Introduce percpu_early_traps_init() and set up exception handling earlier
Date: Thu, 14 Aug 2025 19:07:48 +0100
Message-Id: <20250814180748.2532533-1-andrew.cooper3@citrix.com>
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As things stand, we set up AP/S3 exception handling marginally after the
fragile activity of setting up shadow stacks.  Shadow stack setup is going to
get more complicated under FRED.

Introduce percpu_early_traps_init() and call it ahead of setting up shadow
stacks.  To start with, call load_system_tables() which is sufficient to set
up full exception handling.

In order to handle exceptions, current and the speculation controls needs to
work.  cpu_smpboot_alloc() already constructs some of the AP's top-of-stack
block, so have it set up a little more.  Zero the whole structure to subsume
other misc setup.

This gets us complete exception coverage of setting up shadow stacks, rather
than dying with a triple fault.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Rename to percpu_early_traps_init()
 * Reorder setup
---
 xen/arch/x86/acpi/wakeup_prot.S |  5 +++--
 xen/arch/x86/boot/x86_64.S      |  5 ++++-
 xen/arch/x86/smpboot.c          | 19 ++++++-------------
 xen/arch/x86/traps-setup.c      | 12 ++++++++++++
 4 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/xen/arch/x86/acpi/wakeup_prot.S b/xen/arch/x86/acpi/wakeup_prot.S
index 92af6230b31f..cc40fddc38d4 100644
--- a/xen/arch/x86/acpi/wakeup_prot.S
+++ b/xen/arch/x86/acpi/wakeup_prot.S
@@ -63,6 +63,9 @@ LABEL(s3_resume)
         pushq   %rax
         lretq
 1:
+        /* Set up early exceptions and CET before entering C properly. */
+        call    percpu_early_traps_init
+
 #if defined(CONFIG_XEN_SHSTK) || defined(CONFIG_XEN_IBT)
         call    xen_msr_s_cet_value
         test    %eax, %eax
@@ -117,8 +120,6 @@ LABEL(s3_resume)
 .L_cet_done:
 #endif /* CONFIG_XEN_SHSTK || CONFIG_XEN_IBT */
 
-        call    load_system_tables
-
         /* Restore CR4 from the cpuinfo block. */
         GET_STACK_END(bx)
         mov     STACK_CPUINFO_FIELD(cr4)(%rbx), %rax
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 95a6b6cf63bd..d0e7449a149f 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -30,7 +30,10 @@ ENTRY(__high_start)
         test    %ebx,%ebx
         jz      .L_bsp
 
-        /* APs.  Set up CET before entering C properly. */
+        /* APs.  Set up early exceptions and CET before entering C properly. */
+
+        call    percpu_early_traps_init
+
 #if defined(CONFIG_XEN_SHSTK) || defined(CONFIG_XEN_IBT)
         call    xen_msr_s_cet_value
         test    %eax, %eax
diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index ce4862dde5a7..efb5adb3a12a 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -327,12 +327,7 @@ void asmlinkage start_secondary(void)
     struct cpu_info *info = get_cpu_info();
     unsigned int cpu = smp_processor_id();
 
-    /* Critical region without IDT or TSS.  Any fault is deadly! */
-
-    set_current(idle_vcpu[cpu]);
-    this_cpu(curr_vcpu) = idle_vcpu[cpu];
     rdmsrl(MSR_EFER, this_cpu(efer));
-    init_shadow_spec_ctrl_state(info);
 
     /*
      * Just as during early bootstrap, it is convenient here to disable
@@ -352,14 +347,6 @@ void asmlinkage start_secondary(void)
      */
     spin_debug_disable();
 
-    get_cpu_info()->use_pv_cr3 = false;
-    get_cpu_info()->xen_cr3 = 0;
-    get_cpu_info()->pv_cr3 = 0;
-
-    load_system_tables();
-
-    /* Full exception support from here on in. */
-
     if ( cpu_has_pks )
         wrpkrs_and_cache(0); /* Must be before setting CR4.PKS */
 
@@ -1064,9 +1051,15 @@ static int cpu_smpboot_alloc(unsigned int cpu)
             goto out;
 
     info = get_cpu_info_from_stack((unsigned long)stack_base[cpu]);
+    memset(info, 0, sizeof(*info));
     info->processor_id = cpu;
     info->per_cpu_offset = __per_cpu_offset[cpu];
 
+    init_shadow_spec_ctrl_state(info);
+
+    info->current_vcpu = idle_vcpu[cpu]; /* set_current() */
+    per_cpu(curr_vcpu, cpu) = idle_vcpu[cpu];
+
     gdt = per_cpu(gdt, cpu) ?: alloc_xenheap_pages(0, memflags);
     if ( gdt == NULL )
         goto out;
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index 99257bbb16ec..758c67b335bd 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -127,3 +127,15 @@ void percpu_traps_init(void)
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
 }
+
+/*
+ * Configure exception handling on APs and S3.  Called before entering C
+ * properly, and before shadow stacks are activated.
+ *
+ * boot_gdt is currently loaded, and we must switch to our local GDT.  The
+ * local IDT has unknown IST-ness.
+ */
+void asmlinkage percpu_early_traps_init(void)
+{
+    load_system_tables();
+}
-- 
2.39.5



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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
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 Xen-devel 
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On 14/08/2025 9:55 am, Jan Beulich wrote:
> On 13.08.2025 13:25, Andrew Cooper wrote:
>> On 12/08/2025 10:19 am, Jan Beulich wrote:
>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>> Since commit a35816b5cae8 ("x86/traps: Introduce early_traps_init() and
>>>> simplify setup"), load_system_tables() is called later on the BSP, so the
>>>> SYS_STATE_early_boot check can be dropped from the safety BUG_ON().
>>>>
>>>> Move the BUILD_BUG_ON() into build_assertions(),
>>> I'm not quite convinced of this move - having the related BUILD_BUG_ON()
>>> and BUG_ON() next to each other would seem better to me.
>> I don't see a specific reason for them to be together, and the comment
>> explains what's going on.
>>
>> With FRED, we want a related BUILD_BUG_ON(), but there's no equivalent
>> BUG_ON() because MSR_RSP_SL0 will #GP on being misaligned.
> That BUILD_BUG_ON() could then sit next to the MSR write? Unless of course
> that ends up sitting in an assembly source.

It's the bottom hunk in patch 14, which you've looked at now.

Personally, I think both BUILD_BUG_ON()'s should be together, because
they are related.

~Andrew


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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
 traps-setup.c
To: Jan Beulich 
Cc: Xen-devel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Nicola Vetrini 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-10-andrew.cooper3@citrix.com>
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On 14/08/2025 8:26 am, Jan Beulich wrote:
> On 13.08.2025 13:36, Andrew Cooper wrote:
>> On 12/08/2025 10:43 am, Nicola Vetrini wrote:
>>> On 2025-08-08 22:23, Andrew Cooper wrote:
>>>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>>>> index 8ca379c9e4cb..13b8fcf0ba51 100644
>>>> --- a/xen/arch/x86/traps-setup.c
>>>> +++ b/xen/arch/x86/traps-setup.c
>>>> @@ -19,6 +20,124 @@ boolean_param("ler", opt_ler);
>>>>
>>>>  void nocall entry_PF(void);
>>>>
>>>> +/*
>>>> + * Sets up system tables and descriptors for IDT devliery.
>>>> + *
>>>> + * - Sets up TSS with stack pointers, including ISTs
>>>> + * - Inserts TSS selector into regular and compat GDTs
>>>> + * - Loads GDT, IDT, TR then null LDT
>>>> + * - Sets up IST references in the IDT
>>>> + */
>>>> +static void load_system_tables(void)
>>>> +{
>>>> +    unsigned int i, cpu = smp_processor_id();
>>>> +    unsigned long stack_bottom = get_stack_bottom(),
>>>> +        stack_top = stack_bottom & ~(STACK_SIZE - 1);
>>>> +    /*
>>>> +     * NB: define tss_page as a local variable because clang 3.5
>>>> doesn't
>>>> +     * support using ARRAY_SIZE against per-cpu variables.
>>>> +     */
>>>> +    struct tss_page *tss_page = &this_cpu(tss_page);
>>>> +    idt_entry_t *idt = this_cpu(idt);
>>>> +
>>> Given the clang baseline this might not be needed anymore?
>> Hmm.  While true, looking at 51461114e26, the code is definitely better
>> written with the tss_page variable and we wouldn't want to go back to
>> the old form.
>>
>> I think that I'll simply drop the comment.
>>
>> ~Andrew
>>
>> P.S.
>>
>> Generally speaking, because of the RELOC_HIDE() in this_cpu(), any time
>> you ever want two accesses to a variable, it's better (code gen wise) to
>> construct a pointer to it and use the point multiple times.
>>
>> I don't understand why there's a RELOC_HIDE() in this_cpu().  The
>> justification doesn't make sense, but I've not had time to explore what
>> happens if we take it out.
> There's no justification in xen/percpu.h?

Well, it's given in compiler.h by RELOC_HIDE().

/* This macro obfuscates arithmetic on a variable address so that gcc
   shouldn't recognize the original var, and make assumptions about it */


But this is far from convincing.

>
> My understanding is that we simply may not expose any accesses to per_cpu_*
> variables directly to the compiler, or there's a risk that it might access
> the "master" variable (i.e. CPU0's on at least x86).

RELOC_HIDE() doesn't do anything about the correctness of the pointer
arithmetic expression to make the access work.

I don't see how a correct expression can ever access CPU0's data by
accident.

~Andrew


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Subject: Re: [PATCH 13/22] x86: FRED enumerations
To: Jan Beulich 
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 Xen-devel 
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On 14/08/2025 2:19 pm, Jan Beulich wrote:
> On 14.08.2025 13:20, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> --- a/xen/include/public/arch-x86/cpufeatureset.h
>>> +++ b/xen/include/public/arch-x86/cpufeatureset.h
>>> @@ -310,7 +310,10 @@ XEN_CPUFEATURE(ARCH_PERF_MON, 10*32+8) /*   Architectural Perfmon */
>>>  XEN_CPUFEATURE(FZRM,         10*32+10) /*A  Fast Zero-length REP MOVSB */
>>>  XEN_CPUFEATURE(FSRS,         10*32+11) /*A  Fast Short REP STOSB */
>>>  XEN_CPUFEATURE(FSRCS,        10*32+12) /*A  Fast Short REP CMPSB/SCASB */
>>> +XEN_CPUFEATURE(FRED,         10*32+17) /*   Fast Return and Event Delivery */
>>> +XEN_CPUFEATURE(LKGS,         10*32+18) /*   Load Kernel GS instruction */
>>>  XEN_CPUFEATURE(WRMSRNS,      10*32+19) /*S  WRMSR Non-Serialising */
>>> +XEN_CPUFEATURE(NMI_SRC,      10*32+20) /*   NMI-Source Reporting */
>>>  XEN_CPUFEATURE(AMX_FP16,     10*32+21) /*   AMX FP16 instruction */
>>>  XEN_CPUFEATURE(AVX_IFMA,     10*32+23) /*A  AVX-IFMA Instructions */
>>>  XEN_CPUFEATURE(LAM,          10*32+26) /*   Linear Address Masking */
>> I'd like to note that we could long have had this if my long-pending emulator
>> patch had gone in at some point.
> Actually what I further have there, and what in the context of patch 15 I
> notice you should have here is
>
> --- a/xen/tools/gen-cpuid.py
> +++ b/xen/tools/gen-cpuid.py
> @@ -278,7 +278,8 @@ def crunch_numbers(state):
>          # superpages, PCID and PKU are only available in 4 level paging.
>          # NO_LMSL indicates the absense of Long Mode Segment Limits, which
>          # have been dropped in hardware.
> -        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD],
> +        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD,
> +             LKGS],
>  
>          # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the
>          # standard 3DNow in the earlier K6 processors.
> @@ -347,6 +348,9 @@ def crunch_numbers(state):
>          # computational instructions.  All further AMX features are built on top
>          # of AMX-TILE.
>          AMX_TILE: [AMX_BF16, AMX_INT8, AMX_FP16, AMX_COMPLEX],
> +
> +        # FRED builds on the LKGS instruction.
> +        LKGS: [FRED],
>      }
>  
>      deep_features = tuple(sorted(deps.keys()))

Hmm.  Yes, but normally this is part of guest enablement.

Having now done the Xen work and concluded that we don't actually need
LKGS, I'm rethinking the linkage here.  It's probably the right thing to
do in practice, but probably needs a bit more in the way of
justification.  "built on" doesn't quite cut it IMO.

~Andrew


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Subject: Re: [PATCH 15/22] x86/traps: Introduce opt_fred
To: Jan Beulich 
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On 14/08/2025 2:30 pm, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> ... disabled by default.  There is a lot of work before FRED can be enabled by
>> default.
>>
>> One part of FRED, the LKGS (Load Kernel GS) instruction, is enumerated
>> separately but is mandatory as FRED disallows the SWAPGS instruction.
>> Therefore, both CPUID bits must be checked.
> See my (further) reply to patch 13 - I think FRED simply ought to depend on
> LKGS.
>
>> @@ -20,6 +22,9 @@ unsigned int __ro_after_init ler_msr;
>>  static bool __initdata opt_ler;
>>  boolean_param("ler", opt_ler);
>>  
>> +int8_t __ro_after_init opt_fred = 0; /* -1 when supported. */
> I'm a little puzzled by the comment? DYM "once default-enabled"?

Well, I have this temporary patch
https://gitlab.com/xen-project/hardware/xen-staging/-/commit/70ef6a1178a411a29b7b1745a1112e267ffb6245
that will turn into a real patch when we enable FRED by default.

As much as anything else, it was just a TODO.


>  Then ...
>
>> @@ -305,6 +310,32 @@ void __init traps_init(void)
>>      /* Replace early pagefault with real pagefault handler. */
>>      _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF);
>>  
>> +    if ( !cpu_has_fred || !cpu_has_lkgs )
>> +    {
>> +        if ( opt_fred )
> ... this won't work anymore once the initializer is changed.

Hmm yes.  That wants to be an == 1 check.  Fixed.

>
>> +            printk(XENLOG_WARNING "FRED not available, ignoring\n");
>> +        opt_fred = false;
> Better use 0 here?
>
>> +    }
>> +
>> +    if ( opt_fred == -1 )
>> +        opt_fred = !pv_shim;
> Imo it would be better to have the initializer be -1 right away, and comment
> out the "!pv_shim" here, until we mean it to be default-enabled.

It cannot be -1, or Xen will fail spectacularly on any FRED capable
hardware.  Setting to -1 is the point at which FRED becomes security
supported.

>
>> +    if ( opt_fred )
>> +    {
>> +#ifdef CONFIG_PV32
>> +        if ( opt_pv32 )
>> +        {
>> +            opt_pv32 = 0;
>> +            printk(XENLOG_INFO "Disabling PV32 due to FRED\n");
>> +        }
>> +#endif
>> +        printk("Using FRED event delivery\n");
>> +    }
>> +    else
>> +    {
>> +        printk("Using IDT event delivery\n");
>> +    }
> Could I talk you into omitting the figure braces here? Hmm, or perhaps you
> mean to later move code here.

Indeed, patch 22.

~Andrew


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Date: Thu, 14 Aug 2025 21:05:42 +0200
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Subject: Re: [PATCH v3 00/16] dma-mapping: migrate to physical address-based
 API
To: Leon Romanovsky ,
 Marek Szyprowski 
Cc: Jason Gunthorpe ,
 Abdiel Janulgue ,
 Alexander Potapenko , Alex Gaynor
 , Andrew Morton ,
 Christoph Hellwig , Danilo Krummrich ,
 iommu@lists.linux.dev, Jason Wang ,
 Jens Axboe , Joerg Roedel ,
 Jonathan Corbet , Juergen Gross ,
 kasan-dev@googlegroups.com, Keith Busch ,
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 , Masami Hiramatsu ,
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 , Miguel Ojeda ,
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 Sagi Grimberg , Stefano Stabellini
 , Steven Rostedt ,
 virtualization@lists.linux.dev, Will Deacon ,
 xen-devel@lists.xenproject.org
References: 
From: Christophe Leroy 
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Le 14/08/2025 à 19:53, Leon Romanovsky a écrit :
> Changelog:
> v3:
>   * Fixed typo in "cacheable" word
>   * Simplified kmsan patch a lot to be simple argument refactoring

v2 sent today at 12:13, v3 sent today at 19:53 .... for only that ?

Have you read 
https://docs.kernel.org//process/submitting-patches.html#don-t-get-discouraged-or-impatient 
?

Thanks
Christophe

> v2: https://lore.kernel.org/all/cover.1755153054.git.leon@kernel.org
>   * Used commit messages and cover letter from Jason
>   * Moved setting IOMMU_MMIO flag to dma_info_to_prot function
>   * Micro-optimized the code
>   * Rebased code on v6.17-rc1
> v1: https://lore.kernel.org/all/cover.1754292567.git.leon@kernel.org
>   * Added new DMA_ATTR_MMIO attribute to indicate
>     PCI_P2PDMA_MAP_THRU_HOST_BRIDGE path.
>   * Rewrote dma_map_* functions to use thus new attribute
> v0: https://lore.kernel.org/all/cover.1750854543.git.leon@kernel.org/
> ------------------------------------------------------------------------
> 
> This series refactors the DMA mapping to use physical addresses
> as the primary interface instead of page+offset parameters. This
> change aligns the DMA API with the underlying hardware reality where
> DMA operations work with physical addresses, not page structures.
> 
> The series maintains export symbol backward compatibility by keeping
> the old page-based API as wrapper functions around the new physical
> address-based implementations.
> 
> This series refactors the DMA mapping API to provide a phys_addr_t
> based, and struct-page free, external API that can handle all the
> mapping cases we want in modern systems:
> 
>   - struct page based cachable DRAM
>   - struct page MEMORY_DEVICE_PCI_P2PDMA PCI peer to peer non-cachable
>     MMIO
>   - struct page-less PCI peer to peer non-cachable MMIO
>   - struct page-less "resource" MMIO
> 
> Overall this gets much closer to Matthew's long term wish for
> struct-pageless IO to cachable DRAM. The remaining primary work would
> be in the mm side to allow kmap_local_pfn()/phys_to_virt() to work on
> phys_addr_t without a struct page.
> 
> The general design is to remove struct page usage entirely from the
> DMA API inner layers. For flows that need to have a KVA for the
> physical address they can use kmap_local_pfn() or phys_to_virt(). This
> isolates the struct page requirements to MM code only. Long term all
> removals of struct page usage are supporting Matthew's memdesc
> project which seeks to substantially transform how struct page works.
> 
> Instead make the DMA API internals work on phys_addr_t. Internally
> there are still dedicated 'page' and 'resource' flows, except they are
> now distinguished by a new DMA_ATTR_MMIO instead of by callchain. Both
> flows use the same phys_addr_t.
> 
> When DMA_ATTR_MMIO is specified things work similar to the existing
> 'resource' flow. kmap_local_pfn(), phys_to_virt(), phys_to_page(),
> pfn_valid(), etc are never called on the phys_addr_t. This requires
> rejecting any configuration that would need swiotlb. CPU cache
> flushing is not required, and avoided, as ATTR_MMIO also indicates the
> address have no cachable mappings. This effectively removes any
> DMA API side requirement to have struct page when DMA_ATTR_MMIO is
> used.
> 
> In the !DMA_ATTR_MMIO mode things work similarly to the 'page' flow,
> except on the common path of no cache flush, no swiotlb it never
> touches a struct page. When cache flushing or swiotlb copying
> kmap_local_pfn()/phys_to_virt() are used to get a KVA for CPU
> usage. This was already the case on the unmap side, now the map side
> is symmetric.
> 
> Callers are adjusted to set DMA_ATTR_MMIO. Existing 'resource' users
> must set it. The existing struct page based MEMORY_DEVICE_PCI_P2PDMA
> path must also set it. This corrects some existing bugs where iommu
> mappings for P2P MMIO were improperly marked IOMMU_CACHE.
> 
> Since ATTR_MMIO is made to work with all the existing DMA map entry
> points, particularly dma_iova_link(), this finally allows a way to use
> the new DMA API to map PCI P2P MMIO without creating struct page. The
> VFIO DMABUF series demonstrates how this works. This is intended to
> replace the incorrect driver use of dma_map_resource() on PCI BAR
> addresses.
> 
> This series does the core code and modern flows. A followup series
> will give the same treatment to the legacy dma_ops implementation.
> 
> Thanks
> 
> Leon Romanovsky (16):
>    dma-mapping: introduce new DMA attribute to indicate MMIO memory
>    iommu/dma: implement DMA_ATTR_MMIO for dma_iova_link().
>    dma-debug: refactor to use physical addresses for page mapping
>    dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys
>    iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys
>    iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory
>    dma-mapping: convert dma_direct_*map_page to be phys_addr_t based
>    kmsan: convert kmsan_handle_dma to use physical addresses
>    dma-mapping: handle MMIO flow in dma_map|unmap_page
>    xen: swiotlb: Open code map_resource callback
>    dma-mapping: export new dma_*map_phys() interface
>    mm/hmm: migrate to physical address-based DMA mapping API
>    mm/hmm: properly take MMIO path
>    block-dma: migrate to dma_map_phys instead of map_page
>    block-dma: properly take MMIO path
>    nvme-pci: unmap MMIO pages with appropriate interface
> 
>   Documentation/core-api/dma-api.rst        |   4 +-
>   Documentation/core-api/dma-attributes.rst |  18 ++++
>   arch/powerpc/kernel/dma-iommu.c           |   4 +-
>   block/blk-mq-dma.c                        |  15 ++-
>   drivers/iommu/dma-iommu.c                 |  61 +++++------
>   drivers/nvme/host/pci.c                   |  18 +++-
>   drivers/virtio/virtio_ring.c              |   4 +-
>   drivers/xen/swiotlb-xen.c                 |  21 +++-
>   include/linux/blk-mq-dma.h                |   6 +-
>   include/linux/blk_types.h                 |   2 +
>   include/linux/dma-direct.h                |   2 -
>   include/linux/dma-map-ops.h               |   8 +-
>   include/linux/dma-mapping.h               |  33 ++++++
>   include/linux/iommu-dma.h                 |  11 +-
>   include/linux/kmsan.h                     |   9 +-
>   include/trace/events/dma.h                |   9 +-
>   kernel/dma/debug.c                        |  71 ++++---------
>   kernel/dma/debug.h                        |  37 ++-----
>   kernel/dma/direct.c                       |  22 +---
>   kernel/dma/direct.h                       |  52 ++++++----
>   kernel/dma/mapping.c                      | 117 +++++++++++++---------
>   kernel/dma/ops_helpers.c                  |   6 +-
>   mm/hmm.c                                  |  19 ++--
>   mm/kmsan/hooks.c                          |   7 +-
>   rust/kernel/dma.rs                        |   3 +
>   tools/virtio/linux/kmsan.h                |   2 +-
>   26 files changed, 306 insertions(+), 255 deletions(-)
> 



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Subject: Re: [PATCH 16/22] x86/boot: Adjust CR4 handling around
 ap_early_traps_init()
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14/08/2025 3:56 pm, Jan Beulich wrote:
> On 14.08.2025 16:54, Andrew Cooper wrote:
>> On 14/08/2025 3:47 pm, Jan Beulich wrote:
>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>> --- a/xen/arch/x86/boot/x86_64.S
>>>> +++ b/xen/arch/x86/boot/x86_64.S
>>>> @@ -11,16 +11,19 @@ ENTRY(__high_start)
>>>>          mov     %ecx,%gs
>>>>          mov     %ecx,%ss
>>>>  
>>>> -        /* Enable minimal CR4 features. */
>>>> -        mov     $XEN_MINIMAL_CR4,%rcx
>>>> -        mov     %rcx,%cr4
>>>> -
>>>>          mov     stack_start(%rip),%rsp
>>>>  
>>>>          /* Reset EFLAGS (subsumes CLI and CLD). */
>>>>          pushq   $0
>>>>          popf
>>>>  
>>>> +        GET_STACK_END(15)
>>>> +
>>>> +        /* Enable minimal CR4 features. */
>>>> +        mov     $XEN_MINIMAL_CR4, %eax
>>>> +        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
>>> ... this could be 32-bit stores, even in the longer run.
>> ... no, they can't.
>>
>> The store also serves to clear out stale X86_CR4_FRED, prior to FRED
>> getting reconfigured again.
>>
>> fatal_trap() uses info->cr4 to decide whether it's safe to look at the
>> extended FRED metadata.  Strictly speaking I probably ought to read the
>> real CR4 (in read_registers too), but using a 32bit store here would
>> extend a 1-instruction window into quite a larger window where exception
>> handling would not work quite right.
> Oh, I see. Mind me asking to add brief comments there to this effect?

I've changed it to:

/* Enable minimal CR4 features, sync cached state. */

~Andrew


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Date: Thu, 14 Aug 2025 21:37:07 +0200
From: Nicola Vetrini 
To: Andrew Cooper 
Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Xen-devel 
Subject: Re: [PATCH 13/22] x86: FRED enumerations
In-Reply-To: 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-14-andrew.cooper3@citrix.com>
 <9b4da5b3-dd68-4052-92cc-fe322164eaa5@suse.com>
 <9cc46920-b1a6-4085-8481-abf0f1cd0aab@citrix.com>
 
 
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On 2025-08-14 13:47, Andrew Cooper wrote:
> On 14/08/2025 12:44 pm, Jan Beulich wrote:
>> On 14.08.2025 13:42, Andrew Cooper wrote:
>>> On 14/08/2025 12:20 pm, Jan Beulich wrote:
>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>> --- a/xen/arch/x86/include/asm/x86-defns.h
>>>>> +++ b/xen/arch/x86/include/asm/x86-defns.h
>>>>> @@ -75,6 +75,7 @@
>>>>>  #define X86_CR4_PKE        0x00400000 /* enable PKE */
>>>>>  #define X86_CR4_CET        0x00800000 /* Control-flow Enforcement 
>>>>> Technology */
>>>>>  #define X86_CR4_PKS        0x01000000 /* Protection Key Supervisor 
>>>>> */
>>>>> +#define X86_CR4_FRED      0x100000000 /* Fast Return and Event 
>>>>> Delivery */
>>>> ... a UL suffix added here for Misra.
>>> I was surprised, but Eclair is entirely fine with this.
>> And there is a use of the identifier in a monitored C file?
> 
> Yes.  traps-setup.c which definitely has not been added to an exclusion
> list.
> 

Might look into it before the end of the week, if time allows. Is [1] 
the right branch to look at?

[1] 
https://gitlab.com/xen-project/hardware/xen-staging/-/commits/andrew/fred

> ~Andrew

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [PATCH 18/22] x86/traps: Set MSR_PL0_SSP in load_system_tables()
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14/08/2025 4:00 pm, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
>> means that the value they load into MSR_PL0_SSP differs by 8.
>>
>> s3_resume() in particular has logic which is otherwise invariant of FRED mode,
>> and must not clobber a FRED MSR_PL0_SSP with an IDT one.
>>
>> This also simplifies the AP path too.  Updating reinit_bsp_stack() is deferred
>> until later.
>>
>> No functional change.
>>
>> Signed-off-by: Andrew Cooper 
> I wonder why this was originally done in assembly in the first place, when
> we aim at reducing tghe assembly code we have.

It took several iterations (and releases) to get the setup of the
supervisor tokens correct.

I can't even recall if we had load_system_tables() working like this
when the first code went it.  It may have been following a subsequent
clean-up series.

>
>> --- a/xen/arch/x86/boot/x86_64.S
>> +++ b/xen/arch/x86/boot/x86_64.S
>> @@ -65,17 +65,11 @@ ENTRY(__high_start)
>>          or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %rdx
>>  
>>          /*
>> -         * Write a new supervisor token.  Doesn't matter on boot, but for S3
>> -         * resume this clears the busy bit.
>> +         * Write a new Supervisor Token.  It doesn't matter the first time a
>> +         * CPU boots, but for S3 resume or CPU hot re-add, this clears the
>> +         * busy bit.
>>           */
>>          wrssq   %rdx, (%rdx)
>> -
>> -        /* Point MSR_PL0_SSP at the token. */
>> -        mov     $MSR_PL0_SSP, %ecx
>> -        mov     %edx, %eax
>> -        shr     $32, %rdx
>> -        wrmsr
>> -
>>          setssbsy
> This is ending up a little odd: The comment says the write is to clear the
> busy bit, when that's re-set immediately afterwards.

That comment is about the wrssq.  I suppose what isn't said is that
setssbsy will fault if not.  How about ", so SETSSBSY can set it again" ?

~Andrew


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Subject: Re: [PATCH 13/22] x86: FRED enumerations
To: Nicola Vetrini 
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References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14/08/2025 8:37 pm, Nicola Vetrini wrote:
> On 2025-08-14 13:47, Andrew Cooper wrote:
>> On 14/08/2025 12:44 pm, Jan Beulich wrote:
>>> On 14.08.2025 13:42, Andrew Cooper wrote:
>>>> On 14/08/2025 12:20 pm, Jan Beulich wrote:
>>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>>> --- a/xen/arch/x86/include/asm/x86-defns.h
>>>>>> +++ b/xen/arch/x86/include/asm/x86-defns.h
>>>>>> @@ -75,6 +75,7 @@
>>>>>>  #define X86_CR4_PKE        0x00400000 /* enable PKE */
>>>>>>  #define X86_CR4_CET        0x00800000 /* Control-flow
>>>>>> Enforcement Technology */
>>>>>>  #define X86_CR4_PKS        0x01000000 /* Protection Key
>>>>>> Supervisor */
>>>>>> +#define X86_CR4_FRED      0x100000000 /* Fast Return and Event
>>>>>> Delivery */
>>>>> ... a UL suffix added here for Misra.
>>>> I was surprised, but Eclair is entirely fine with this.
>>> And there is a use of the identifier in a monitored C file?
>>
>> Yes.  traps-setup.c which definitely has not been added to an exclusion
>> list.
>>
>
> Might look into it before the end of the week, if time allows. Is [1]
> the right branch to look at?
>
> [1]
> https://gitlab.com/xen-project/hardware/xen-staging/-/commits/andrew/fred

Yes, although I am force pushing this with fixes as I find them.

In the latest run at the time of writing, I had one trivial R8.4
violation to fix, and all other clean rules came up fine.  I expect the
next run to be clean.

One thing that might be relevant, IIRC it's implementation defined
behaviour what happens to constants which are wider than int to begin with.

~Andrew


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To: Jan Beulich 
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 Xen-devel 
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On 14/08/2025 4:11 pm, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> Under FRED, SETSSBSY is unavailable, and we want to be setting up FRED prior
>> to setting up shadow stacks.  As we still need Supervisor Tokens in IDT mode,
>> we need mode-specific logic to establish SSP.
>>
>> In FRED mode, write a Restore Token, RSTORSSP it, and discard the resulting
>> Previous-SSP token.
>>
>> No change outside of FRED mode.
>>
>> Signed-off-by: Andrew Cooper 
> Why is it that in patch 17 you could use identical code, but here you can't?

This caught me out at first too.

For S3, we're going from "no shadow stack" to "back to where we were on
an active shadow stack".  All we need to do is get saved_ssp back into
the SSP register.

Here, we're going from "no shadow stack" to "on a good, empty, shadow
stack".  For FRED we only need to load a value into SSP, but in IDT mode
we must also arrange to create a busy Supervisor Token on the base of
the stack.

We could in principle conditionally write a busy supervisor token, then
unconditionally RSTORSSP, but that's even more complicated to follow IMO.

It also flips around our position of "clean the busy bit on S3/hotplug"
to "set it even on first-bringup".





>
>> @@ -912,10 +913,30 @@ static void __init noreturn reinit_bsp_stack(void)
>>  
>>      if ( cpu_has_xen_shstk )
>>      {
>> -        wrmsrl(MSR_PL0_SSP,
>> -               (unsigned long)stack + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8);
> Does this removal perhaps belong elsewhere, especially with "No change
> outside of FRED mode" in the description?

This is the "Updating reinit_bsp_stack() is deferred until later." note
in the previous patch.

This hunk was illegible without the split, although I have to admit that
I can't quite remember why now.

~Andrew


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Date: Thu, 14 Aug 2025 22:18:56 +0200
From: Nicola Vetrini 
To: Andrew Cooper 
Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Xen-devel 
Subject: Re: [PATCH 13/22] x86: FRED enumerations
In-Reply-To: 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-14-andrew.cooper3@citrix.com>
 <9b4da5b3-dd68-4052-92cc-fe322164eaa5@suse.com>
 <9cc46920-b1a6-4085-8481-abf0f1cd0aab@citrix.com>
 
 
 
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On 2025-08-14 21:37, Nicola Vetrini wrote:
> On 2025-08-14 13:47, Andrew Cooper wrote:
>> On 14/08/2025 12:44 pm, Jan Beulich wrote:
>>> On 14.08.2025 13:42, Andrew Cooper wrote:
>>>> On 14/08/2025 12:20 pm, Jan Beulich wrote:
>>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>>> --- a/xen/arch/x86/include/asm/x86-defns.h
>>>>>> +++ b/xen/arch/x86/include/asm/x86-defns.h
>>>>>> @@ -75,6 +75,7 @@
>>>>>>  #define X86_CR4_PKE        0x00400000 /* enable PKE */
>>>>>>  #define X86_CR4_CET        0x00800000 /* Control-flow Enforcement 
>>>>>> Technology */
>>>>>>  #define X86_CR4_PKS        0x01000000 /* Protection Key 
>>>>>> Supervisor */
>>>>>> +#define X86_CR4_FRED      0x100000000 /* Fast Return and Event 
>>>>>> Delivery */
>>>>> ... a UL suffix added here for Misra.
>>>> I was surprised, but Eclair is entirely fine with this.
>>> And there is a use of the identifier in a monitored C file?
>> 
>> Yes.  traps-setup.c which definitely has not been added to an 
>> exclusion
>> list.
>> 
> 
> Might look into it before the end of the week, if time allows. Is [1] 
> the right branch to look at?
> 
> [1] 
> https://gitlab.com/xen-project/hardware/xen-staging/-/commits/andrew/fred
> 

Actually thinking about it, this is indeed represented in a signed type 
in x86: according to the standard it's just a signed long [2], therefore 
the rule does not apply. Then you would have a R10 violation due to the 
conversion at the callsite. I would put a U regardless, since the 
intention was clearly to have an unsigned long.

[2] https://godbolt.org/z/rT5j4j9vj

>> ~Andrew

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Thu, 14 Aug 2025 21:40:38 +0100
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Subject: Re: [PATCH 21/22] x86/traps: Introduce FRED entrypoints
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14/08/2025 4:57 pm, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> --- a/xen/arch/x86/include/asm/asm_defns.h
>> +++ b/xen/arch/x86/include/asm/asm_defns.h
>> @@ -315,6 +315,71 @@ static always_inline void stac(void)
>>          subq  $-(UREGS_error_code-UREGS_r15+\adj), %rsp
>>  .endm
>>  
>> +/*
>> + * Push and clear GPRs
>> + */
>> +.macro PUSH_AND_CLEAR_GPRS
>> +        push  %rdi
>> +        xor   %edi, %edi
>> +        push  %rsi
>> +        xor   %esi, %esi
>> +        push  %rdx
>> +        xor   %edx, %edx
>> +        push  %rcx
>> +        xor   %ecx, %ecx
>> +        push  %rax
>> +        xor   %eax, %eax
>> +        push  %r8
>> +        xor   %r8d, %r8d
>> +        push  %r9
>> +        xor   %r9d, %r9d
>> +        push  %r10
>> +        xor   %r10d, %r10d
>> +        push  %r11
>> +        xor   %r11d, %r11d
>> +        push  %rbx
>> +        xor   %ebx, %ebx
>> +        push  %rbp
>> +#ifdef CONFIG_FRAME_POINTER
>> +/* Indicate special exception stack frame by inverting the frame pointer. */
>> +        mov   %rsp, %rbp
>> +        notq  %rbp
>> +#else
>> +        xor   %ebp, %ebp
>> +#endif
>> +        push  %r12
>> +        xor   %r12d, %r12d
>> +        push  %r13
>> +        xor   %r13d, %r13d
>> +        push  %r14
>> +        xor   %r14d, %r14d
>> +        push  %r15
>> +        xor   %r15d, %r15d
>> +.endm
>> +
>> +/*
>> + * POP GPRs from a UREGS_* frame on the stack.  Does not modify flags.
>> + *
>> + * @rax: Alternative destination for the %rax value on the stack.
>> + */
>> +.macro POP_GPRS rax=%rax
>> +        pop   %r15
>> +        pop   %r14
>> +        pop   %r13
>> +        pop   %r12
>> +        pop   %rbp
>> +        pop   %rbx
>> +        pop   %r11
>> +        pop   %r10
>> +        pop   %r9
>> +        pop   %r8
>> +        pop   \rax
>> +        pop   %rcx
>> +        pop   %rdx
>> +        pop   %rsi
>> +        pop   %rdi
>> +.endm
> Hmm, yes, differences are apparently large enough to warrant the redundancy
> with SAVE_ALL / RESTORE_ALL.

You may recall this construct from prior attempts I've had to remove
SAVE_ALL/RESTORE_ALL, even with the \rax parameter for SVM.  I still
intend to complete that work at some point.

>
>> --- a/xen/arch/x86/include/asm/msr.h
>> +++ b/xen/arch/x86/include/asm/msr.h
>> @@ -202,9 +202,9 @@ static inline unsigned long read_gs_base(void)
>>  
>>  static inline unsigned long read_gs_shadow(void)
>>  {
>> -    unsigned long base;
>> +    unsigned long base, cr4 = read_cr4();
>>  
>> -    if ( read_cr4() & X86_CR4_FSGSBASE )
>> +    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
>>      {
>>          asm volatile ( "swapgs" );
>>          base = __rdgsbase();
>> @@ -234,7 +234,9 @@ static inline void write_gs_base(unsigned long base)
>>  
>>  static inline void write_gs_shadow(unsigned long base)
>>  {
>> -    if ( read_cr4() & X86_CR4_FSGSBASE )
>> +    unsigned long cr4 = read_cr4();
>> +
>> +    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
>>      {
>>          asm volatile ( "swapgs\n\t"
>>                         "wrgsbase %0\n\t"
> I don't quite get how these changes fit into this patch.

Without the change, read_registers() suffers #UD because of the SWAPGS.

This recurses until hitting the guard page, then repeats the same on the
#DF stack.  And because stacks work nicely under FRED, you eventually
hit #DF's guard page.

Strictly speaking it's only read_gs_shadow() which we need to change to
make exception handling work, but I fixed both at the same time.

That said, I have actually cleaned this codepath up with the MSR work
because the code gen in read_registers() is terrible.  Due to
no-strict-aliasing, every store into state-> forces a recalculation of
get_cpu_info(), meaning that read_cr4() cannot be hoisted, and there's a
branch in every helper.

I'm still not sure how best to fit it into this series.

>
>> --- a/xen/arch/x86/traps.c
>> +++ b/xen/arch/x86/traps.c
>> @@ -1013,6 +1013,32 @@ void show_execution_state_nmi(const cpumask_t *mask, bool show_all)
>>          printk("Non-responding CPUs: {%*pbl}\n", CPUMASK_PR(&show_state_mask));
>>  }
>>  
>> +static const char *x86_et_name(unsigned int type)
>> +{
>> +    static const char *const names[] = {
>> +        [X86_ET_EXT_INTR]    = "EXT_INTR",
>> +        [X86_ET_NMI]         = "NMI",
>> +        [X86_ET_HW_EXC]      = "HW_EXC",
>> +        [X86_ET_SW_INT]      = "SW_INT",
>> +        [X86_ET_PRIV_SW_EXC] = "PRIV_SW_EXEC",
>> +        [X86_ET_SW_EXC]      = "SW_EXEC",
>> +        [X86_ET_OTHER]       = "OTHER",
>> +    };
>> +
>> +    return (type < ARRAY_SIZE(names) && names[type]) ? names[type] : "???";
>> +}
>> +
>> +static const char *x86_et_other_name(unsigned int vec)
> This isn't really a vector, is it?

Well - you are decoding the field name regs->fred_ss.vector.

Also I see I've typo'd EXEC in two of those names.

>
>> +{
>> +    static const char *const names[] = {
>> +        [0] = "MTF",
>> +        [1] = "SYSCALL",
>> +        [2] = "SYSENTER",
>> +    };
>> +
>> +    return (vec < ARRAY_SIZE(names) && names[vec][0]) ? names[vec] : "???";
> Did you mean to check names[ves] for being NULL? Or is this a leftover
> from the array being something like names[][10]?

Oh, bad copy&paste.  Will fix.

>
>> --- a/xen/arch/x86/x86_64/Makefile
>> +++ b/xen/arch/x86/x86_64/Makefile
>> @@ -1,6 +1,7 @@
>>  obj-$(CONFIG_PV32) += compat/
>>  
>>  obj-bin-y += entry.o
>> +obj-bin-y += entry-fred.o
> For the ordering here, ...
>
>> --- /dev/null
>> +++ b/xen/arch/x86/x86_64/entry-fred.S
>> @@ -0,0 +1,35 @@
>> +/* SPDX-License-Identifier: GPL-2.0-or-later */
>> +
>> +        .file "x86_64/entry-fred.S"
>> +
>> +#include 
>> +#include 
>> +
>> +        .section .text.entry, "ax", @progbits
>> +
>> +        /* The Ring3 entry point is required to be 4k aligned. */
>> +
>> +FUNC(entry_FRED_R3, 4096)
> ... doesn't this 4k-alignment requirement suggest we want to put
> entry-fred.o first?

Perhaps, but that is quite subtle.  I did also consider a
.text.entry.page_aligned section, but .text.entry only matters for XPTI
which (as agreed), I'm not intending to implement in FRED mode unless it
proves to be necessary.

Also IIRC there's still a symbol bug where _sentrytext takes priority
over entry_FRED_R3, so the backtrace is effectively wrong.

(These are all bad excuses, but some parts of this series are rather old.)

>  Also, might it be more natural to use PAGE_SIZE
> here?

I did debate that, but the spec uses 0xfff, not pages, even if the
pipline surely does have an optimisation for chopping 12 metadata bits
off the bottom of a pointer.

~Andrew


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MIME-Version: 1.0
Date: Thu, 14 Aug 2025 22:43:35 +0200
From: Nicola Vetrini 
To: Jan Beulich 
Cc: Dmytro Prokopchuk1 , Doug Goldstein
 , Stefano Stabellini , Andrew
 Cooper , Anthony PERARD
 , Michal Orzel , Julien
 Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Bertrand Marquis ,
 Volodymyr Babchuk ,
 xen-devel@lists.xenproject.org
Subject: Re: [RFC PATCH] misra: allow conversion from unsigned long to
 function pointer
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References: <8cbc9e6d881661d0d7a1055cbcef5a65e20522be.1755109168.git.dmytro_prokopchuk1@epam.com>
 <06120b08-7ce8-4d03-b3cd-cbb22547eca3@suse.com>
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On 2025-08-14 10:36, Jan Beulich wrote:
> On 13.08.2025 20:27, Dmytro Prokopchuk1 wrote:
>> ...
>> 
>> from `vaddr_t' (that is `unsigned long') to `switch_ttbr_fn*' (that is 
>> `void(*)(unsigned long)')
>> 
>> Signed-off-by: Dmytro Prokopchuk 
>> ---
>> This is just a RFC patch.
>> The commit message is not important at this stage.
>> 
>> I am seeking comments regarding this case.
>> 
>> Thanks.
>> ---
>>  automation/eclair_analysis/ECLAIR/deviations.ecl |  8 ++++++++
>>  docs/misra/deviations.rst                        | 10 ++++++++++
>>  docs/misra/rules.rst                             |  8 +++++++-
>>  xen/arch/arm/arm64/mmu/mm.c                      |  2 ++
>>  4 files changed, 27 insertions(+), 1 deletion(-)
>> 
>> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl 
>> b/automation/eclair_analysis/ECLAIR/deviations.ecl
>> index ebce1ceab9..f9fd6076b7 100644
>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>> @@ -365,6 +365,14 @@ constant expressions are required.\""
>>  }
>>  -doc_end
>> 
>> +-doc_begin="The conversion from unsigned long to a function pointer 
>> does not lose any information, provided that the source type has 
>> enough bits to restore it."
>> +-config=MC3A2.R11.1,casts+={safe,
>> +  "from(type(canonical(builtin(unsigned long))))
>> +   &&to(type(canonical(__function_pointer_types)))
>> +   &&relation(definitely_preserves_value)"
>> +}
>> +-doc_end
>> +

This check is not quite targeted at this situation, as the behaviour of 
different compilers is a bit of a grey area (even GCC, though that works 
in practice). The relation is mostly aimed at testing whether the 
pointer are represented using the same number of bits as unsigned long 
(which happens to be the case fortunately).

>>  -doc_begin="The conversion from a function pointer to a boolean has a 
>> well-known semantics that do not lead to unexpected behaviour."
>>  -config=MC3A2.R11.1,casts+={safe,
>>    "from(type(canonical(__function_pointer_types)))
>> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
>> index 3c46a1e47a..27848602f6 100644
>> --- a/docs/misra/deviations.rst
>> +++ b/docs/misra/deviations.rst
>> @@ -348,6 +348,16 @@ Deviations related to MISRA C:2012 Rules:
>>         to store it.
>>       - Tagged as `safe` for ECLAIR.
>> 
>> +   * - R11.1
>> +     - The conversion from unsigned long to a function pointer does 
>> not lose any
>> +       information or violate type safety assumptions if the unsigned 
>> long type
>> +       is guaranteed to be at least as large as a function pointer. 
>> This ensures
>> +       that the function pointer address can be fully represented 
>> without
>> +       truncation or corruption. Macro BUILD_BUG_ON can be integrated 
>> into the
>> +       build system to confirm that 'sizeof(unsigned long) >= 
>> sizeof(void (*)())'
>> +       on all target platforms.
> 
> If sizeof(unsigned long) > sizeof(void (*)()), there is loss of 
> information.
> Unless (not said here) the unsigned long value itself is the result of
> converting a function pointer to unsigned long. Whether all of that 
> together
> can be properly expressed to Eclair I don't know. Hence, as Teddy 
> already
> suggested, == may want specifying instead.
> 

+1; it might be worth to add both the eclair config and the 
BUILD_BUG_ON, noting that neither is sufficient on its own: unless the 
compiler guarantees not to fiddle with the value is unaltered when cast 
back and forth all checks on the number of bits are moot.

>> --- a/xen/arch/arm/arm64/mmu/mm.c
>> +++ b/xen/arch/arm/arm64/mmu/mm.c
>> @@ -150,6 +150,7 @@ void __init relocate_and_switch_ttbr(uint64_t 
>> ttbr)
>>      vaddr_t id_addr = virt_to_maddr(relocate_xen);
>>      relocate_xen_fn *fn = (relocate_xen_fn *)id_addr;
>>      lpae_t pte;
>> +    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
>> 
>>      /* Enable the identity mapping in the boot page tables */
>>      update_identity_mapping(true);
>> @@ -178,6 +179,7 @@ void __init switch_ttbr(uint64_t ttbr)
>>      vaddr_t id_addr = virt_to_maddr(switch_ttbr_id);
>>      switch_ttbr_fn *fn = (switch_ttbr_fn *)id_addr;
>>      lpae_t pte;
>> +    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
>> 
>>      /* Enable the identity mapping in the boot page tables */
>>      update_identity_mapping(true);
> 
> BUILD_BUG_ON() is a statement, not a declaration, and hence wants 
> grouping
> as such. Question is whether we indeed want to sprinkle such checks all
> over the code base. (I expect the two cases here aren't all we have.)
> 

+1 as well. I would expect such check to live e.g. in compiler.h or any 
similarly general header, since this is a widespread and largely 
arch-neutral property that Xen wants to be always true I believe.

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [PATCH 20/22] x86/traps: Alter switch_stack_and_jump() for FRED
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To: Jan Beulich 
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 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14/08/2025 4:35 pm, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
>> means that switch_stack_and_jump() needs to discard one extra word when FRED
>> is active.
>>
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Jan Beulich 
>> CC: Roger Pau Monné 
>>
>> RFC.  I don't like this, but it does work.
>>
>> This emits opt_fred logic outside of CONFIG_XEN_SHSTK.
> opt_fred and XEN_SHSTK are orthogonal, so that's fine anyway. What I guess
> you may mean is that you now have a shstk-related calculation outside of
> a respective #ifdef.

I really mean "outside of the path where shadow stacks are known to be
active", i.e. inside the middle of SHADOW_STACK_WORK

>  Given the simplicity of the calculation, ...
>
>>  But frankly, the
>> construct is already too unweildly, and all options I can think of make it
>> moreso.
> ... I agree having it like this is okay.

Yes, but it is a read of a global even when it's not used.

And as a tangent, we probably want __ro_after_init_read_mostly too.  The
read mostly is about cache locality, and is applicable even to the
__ro_after_init section.

>
>> @@ -154,7 +155,6 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>      "rdsspd %[ssp];"                                            \
>>      "cmp $1, %[ssp];"                                           \
>>      "je .L_shstk_done.%=;" /* CET not active?  Skip. */         \
>> -    "mov $%c[skstk_base], %[val];"                              \
>>      "and $%c[stack_mask], %[ssp];"                              \
>>      "sub %[ssp], %[val];"                                       \
>>      "shr $3, %[val];"                                           \
> With the latter two insns here, ...
>
>> @@ -177,6 +177,8 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>  
>>  #define switch_stack_and_jump(fn, instr, constr)                        \
>>      ({                                                                  \
>> +        unsigned int token_offset =                                     \
>> +            (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - (opt_fred ? 0 : 8);  \
>>          unsigned int tmp;                                               \
>>          BUILD_BUG_ON(!ssaj_has_attr_noreturn(fn));                      \
>>          __asm__ __volatile__ (                                          \
>> @@ -184,12 +186,11 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>              "mov %[stk], %%rsp;"                                        \
>>              CHECK_FOR_LIVEPATCH_WORK                                    \
>>              instr "[fun]"                                               \
>> -            : [val] "=&r" (tmp),                                        \
>> +            : [val] "=r" (tmp),                                         \
> ... I don't think you can legitimately drop the & from here? With it
> retained:
> Reviewed-by: Jan Beulich 

You chopped the bit which has an explicit input for "[val]", making the
earlyclobber incorrect.

IIRC, one version of Clang complained.

~Andrew


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On 2025-08-14 03:05, Jürgen Groß wrote:
> On 13.08.25 17:03, Jason Andryuk wrote:
>> On 2025-08-12 15:00, Jason Andryuk wrote:
>>> VIRQs come in 3 flavors, per-VPU, per-domain, and global.  The existing
>>> tracking of VIRQs is handled by per-cpu variables virq_to_irq.
>>>
>>> The issue is that bind_virq_to_irq() sets the per_cpu virq_to_irq at
>>> registration time - typically CPU 0.  Later, the interrupt can migrate,
>>> and info->cpu is updated.  When calling unbind_from_irq(), the per-cpu
>>> virq_to_irq is cleared for a different cpu.  If bind_virq_to_irq() is
> 
> This is what needs to be fixed. At migration the per_cpu virq_to_irq of the
> source and the target cpu need to be updated to reflect that migration.

I considered this, and even implemented it, before changing my approach. 
  My concern was that the single VIRQ is now in one of the N per_cpu 
virq_to_irq arrays.  A second attempt to register on CPU 0 will probably 
find -1 and continue and issue the hypercall.

It looks like Xen tracks virq on the bind_virq vcpu, so 
per-domain/global stays on vcpu0.  Binding again would return -EEXISTS. 
find_virq() would not match the virq if it was re-bound to a different vcpu.

If we don't care about handling duplicate registration, then updating 
the virq_to_irq tables should be is fine.

>>> called again with CPU 0, the stale irq is returned.
>>>
>>> Change the virq_to_irq tracking to use CPU 0 for per-domain and global
>>> VIRQs.  As there can be at most one of each, there is no need for
>>> per-vcpu tracking.  Also, per-domain and global VIRQs need to be
>>> registered on CPU 0 and can later move, so this matches the expectation.
>>>
>>> Fixes: e46cdb66c8fc ("xen: event channels")
>>> Cc: stable@vger.kernel.org
>>> Signed-off-by: Jason Andryuk 
>>> ---
>>> Fixes is the introduction of the virq_to_irq per-cpu array.
>>>
>>> This was found with the out-of-tree argo driver during suspend/resume.
>>> On suspend, the per-domain VIRQ_ARGO is unbound.  On resume, the driver
>>> attempts to bind VIRQ_ARGO.  The stale irq is returned, but the
>>> WARN_ON(info == NULL || info->type != IRQT_VIRQ) in bind_virq_to_irq()
>>> triggers for NULL info.  The bind fails and execution continues with the
>>> driver trying to clean up by unbinding.  This eventually faults over the
>>> NULL info.
>>> ---
>>>   drivers/xen/events/events_base.c | 17 ++++++++++++++++-
>>>   1 file changed, 16 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/ 
>>> events_base.c
>>> index 41309d38f78c..a27e4d7f061e 100644
>>> --- a/drivers/xen/events/events_base.c
>>> +++ b/drivers/xen/events/events_base.c
>>> @@ -159,7 +159,19 @@ static DEFINE_MUTEX(irq_mapping_update_lock);
>>>   static LIST_HEAD(xen_irq_list_head);
>>> -/* IRQ <-> VIRQ mapping. */
>>> +static bool is_per_vcpu_virq(int virq) {
>>> +    switch (virq) {
>>> +    case VIRQ_TIMER:
>>> +    case VIRQ_DEBUG:
>>> +    case VIRQ_XENOPROF:
>>> +    case VIRQ_XENPMU:
>>> +        return true;
>>> +    default:
>>> +        return false;
>>> +    }
>>> +}
>>> +
>>> +/* IRQ <-> VIRQ mapping.  Global/Domain virqs are tracked in cpu 0.  */
>>>   static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... 
>>> NR_VIRQS-1] = -1};
>>>   /* IRQ <-> IPI mapping */
>>> @@ -974,6 +986,9 @@ static void __unbind_from_irq(struct irq_info 
>>> *info, unsigned int irq)
>>>           switch (info->type) {
>>>           case IRQT_VIRQ:
>>> +            if (!is_per_vcpu_virq(virq_from_irq(info)))
>>> +                cpu = 0;
>>> +
>>>               per_cpu(virq_to_irq, cpu)[virq_from_irq(info)] = -1;
>>>               break;
>>>           case IRQT_IPI:
>>
>> Thinking about it a little more, bind_virq_to_irq() should ensure cpu 
>> == 0 for per-domain and global VIRQs to ensure the property holds.  
>> Also virq_to_irq 
> 
> In Xen's evtchn_bind_virq() there is:
> 
>      if ( type != VIRQ_VCPU && vcpu != 0 )
>          return -EINVAL;
> 
> Making sure in Linux that there is never a violation of that restriction 
> would
> require to always have an up-to-date table of all possible VIRQs and their
> type, which I'd like to avoid.

Yes, I agree with this.

> I think it is the user of the VIRQ who is responsible to ensure cpu 0 is 
> passed
> to bind_virq_to_irq(), as this user knows that such a restriction 
> applies to
> the VIRQ in question (at least he should know that).
> 
> Special handling for really used VIRQs in the kernel can have some special
> handling, of course, as they are known already and should be used 
> correctly.

Thanks,
Jason


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Date: Thu, 14 Aug 2025 23:27:21 +0200
From: Nicola Vetrini 
To: Andrew Cooper 
Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Xen-devel 
Subject: Re: [PATCH 13/22] x86: FRED enumerations
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On 2025-08-14 21:44, Andrew Cooper wrote:
> On 14/08/2025 8:37 pm, Nicola Vetrini wrote:
>> On 2025-08-14 13:47, Andrew Cooper wrote:
>>> On 14/08/2025 12:44 pm, Jan Beulich wrote:
>>>> On 14.08.2025 13:42, Andrew Cooper wrote:
>>>>> On 14/08/2025 12:20 pm, Jan Beulich wrote:
>>>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>>>> --- a/xen/arch/x86/include/asm/x86-defns.h
>>>>>>> +++ b/xen/arch/x86/include/asm/x86-defns.h
>>>>>>> @@ -75,6 +75,7 @@
>>>>>>>  #define X86_CR4_PKE        0x00400000 /* enable PKE */
>>>>>>>  #define X86_CR4_CET        0x00800000 /* Control-flow
>>>>>>> Enforcement Technology */
>>>>>>>  #define X86_CR4_PKS        0x01000000 /* Protection Key
>>>>>>> Supervisor */
>>>>>>> +#define X86_CR4_FRED      0x100000000 /* Fast Return and Event
>>>>>>> Delivery */
>>>>>> ... a UL suffix added here for Misra.
>>>>> I was surprised, but Eclair is entirely fine with this.
>>>> And there is a use of the identifier in a monitored C file?
>>> 
>>> Yes.  traps-setup.c which definitely has not been added to an 
>>> exclusion
>>> list.
>>> 
>> 
>> Might look into it before the end of the week, if time allows. Is [1]
>> the right branch to look at?
>> 
>> [1]
>> https://gitlab.com/xen-project/hardware/xen-staging/-/commits/andrew/fred
> 
> Yes, although I am force pushing this with fixes as I find them.
> 
> In the latest run at the time of writing, I had one trivial R8.4
> violation to fix, and all other clean rules came up fine.  I expect the
> next run to be clean.
> 
> One thing that might be relevant, IIRC it's implementation defined
> behaviour what happens to constants which are wider than int to begin 
> with.
> 

See my other reply in this thread; the rule is concerned with the type 
of the constant present after preprocessing, which is defined in C99 
6.4.4.1.5 . As such, I'm not sure what you're hinting at regarding IDB 
here. Of course I might be wrong.

> ~Andrew

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Message-ID: <6e9b5265-7a3b-4fd5-b14e-0e60a8b49833@gmail.com>
Date: Thu, 14 Aug 2025 17:27:56 -0400
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Subject: Re: Consider changing CONFIG_ACPI default on ARM?
To: Jan Beulich , Elliott Mitchell 
Cc: xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Paul Leiber 
References: 
 
 
 <1b96f2f3-55a2-4b33-84b1-a7c18d38d10c@suse.com>
Content-Language: en-US
From: Demi Marie Obenour 
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From: Demi Marie Obenour 
To: Jan Beulich , Elliott Mitchell 
Cc: xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Paul Leiber 
Message-ID: <6e9b5265-7a3b-4fd5-b14e-0e60a8b49833@gmail.com>
Subject: Re: Consider changing CONFIG_ACPI default on ARM?
References: 
 
 
 <1b96f2f3-55a2-4b33-84b1-a7c18d38d10c@suse.com>
In-Reply-To: <1b96f2f3-55a2-4b33-84b1-a7c18d38d10c@suse.com>

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On 8/14/25 02:55, Jan Beulich wrote:
> On 06.08.2025 06:30, Elliott Mitchell wrote:
>> On Tue, Jul 01, 2025 at 10:01:13PM +0200, Paul Leiber wrote:
>>>
>>> Unfortunately, I don't have a direct answer to the question (as is so=
 often
>>> the case, due to my limited knowledge and experience). However, I am
>>> successfully running Xen on a RPi 4 (mostly, except for some VLAN rel=
ated
>>> networking issues).
>>>
>>> I used instructions in [1] to install vanilla Debian on the RPi, incl=
uding
>>> UEFI boot and grub. I then compiled Xen with expert options and ACPI
>>> enabled.
>>>
>>> I don't know if there are better solutions. For example, I suffer fro=
m the
>>> fact that I2C doesn't work when using UEFI boot on a RPi. Nowadays, D=
ebian
>>> provides their own vanilla Debian images for RPi and with working I2C=
, but
>>> these images are using a different boot method that I didn't know how=
 to use
>>> with Xen.  So far, the procedure described above seems to be the easi=
est
>>> solution for me.
>>
>>
>>> [1] https://forums.raspberrypi.com/viewtopic.php?t=3D282839
>>>
>>> Am 30.06.2025 um 12:35 schrieb Sumit Semwal:
>>>>
>>>> I've just begun to experiment with the Raspberry Pi 5, trying to run=
 a
>>>> simple xen + Dom0 setup, using uBoot, and the bookworm based Rpi
>>>> distro.
>>>>
>>>> I've tried combinations of the following setup:
>>>>
>>>> 1. prebuilt Rpi5 kernel + dtbs, and have also tried to build them fr=
om
>>>> source [1]
>>>> 2. Xen from upstream [2] and xen-troops [3]
>>>> 3. upstream uBoot from [4]
>>>>
>>>> but with the same result: [short log below; I can provide a fuller l=
og
>>>> if needed]
>>>>
>>>> (XEN) DT: ** translation for device /axi/msi-controller@1000130000 *=
*
>>>> (XEN) DT: bus is default (na=3D2, ns=3D2) on /axi
>>>> (XEN) DT: translating address:<3> 000000ff<3> fffff000<3>
>>>> (XEN) DT: parent bus is default (na=3D2, ns=3D1) on /
>>>> (XEN) DT: walking ranges...
>>>> (XEN) DT: default map, cp=3D0, s=3D1000000000, da=3Dfffffff000
>>>> (XEN) DT: default map, cp=3D1000000000, s=3D100000000, da=3Dfffffff0=
00
>>>> (XEN) DT: default map, cp=3D1400000000, s=3D400000000, da=3Dfffffff0=
00
>>>> (XEN) DT: default map, cp=3D1800000000, s=3D400000000, da=3Dfffffff0=
00
>>>> (XEN) DT: default map, cp=3D1c00000000, s=3D400000000, da=3Dfffffff0=
00
>>>> (XEN) DT: not found !
>>>> (XEN) Unable to retrieve address 1 for /axi/msi-controller@100013000=
0
>>>> (XEN) Device tree generation failed (-22).
>>>> (XEN) debugtrace_dump() global buffer starting
>>>> 1 cpupool_create(pool=3D0,sched=3D6)
>>>> 2 Created cpupool 0 with scheduler SMP Credit Scheduler rev2 (credit=
2)
>>>> 3 cpupool_add_domain(dom=3D0,pool=3D0) n_dom 1 rc 0
>>>> (XEN) wrap: 0
>>>> (XEN) debugtrace_dump() global buffer finished
>>>> (XEN)
>>>> (XEN) ****************************************
>>>> (XEN) Panic on CPU 0:
>>>> (XEN) Could not set up DOM0 guest OS (rc =3D -22)
>>>> (XEN) ****************************************
>>>>
>>>>
>>>> I'm certain I'm missing something, but before I delve deeper, I just=

>>>> wanted to ask if this is a known issue, and if so, are there any
>>>> workarounds or solutions available for this?
>>>>
>>>> Any help about this is highly appreciated!
>>>>
>>>> Thanks and Best regards,
>>>> Sumit.
>>>>
>>>> [1]:  https://github.com/raspberrypi/linux rpi-6.12.y branch
>>>> [2]: git://xenbits.xen.org/xen.git - main branch
>>>> [3] xen-troops https://github.com/xen-troops/xen - rpi5_dev branch
>>>> [4]: https://github.com/u-boot/u-boot.git master branch
>>
>> Ultimately Debian is choosing to leave most defaults alone.  So far th=
e
>> Xen developers have left CONFIG_ACPI defaulting to off on ARM*.  The
>> Debian project doesn't have paid people to support Raspberry PI hardwa=
re,
>> despite being rather common.  As a result there aren't any official
>> Raspberry PI images, but people associated with Tianocore have gotten
>> generic images to boot on Raspberry PI hardware.
>>
>> I'm unsure of the likelihood of getting the Debian maintainers to
>> override the default.  Yet due being by far the simplest way to instal=
l
>> Debian and Xen on a very common ARM64 platform, perhaps the Xen
>> developers should consider changing?
>=20
> In an open source project everyone is a developer. There is a
> significant amount of work someone needs to pick up to change this
> SUPPORT.md entry:
>=20
> ### Host ACPI (via Domain 0)
>=20
>     Status, x86 PV: Supported
>     Status, ARM: Experimental
>=20
> Parties interested in changing the support status of any component are =
the
> primary candidates to actually carry out the necessary work.
>=20
> Jan

What is that work?
--=20
Sincerely,
Demi Marie Obenour (she/her/hers)
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        Thu, 14 Aug 2025 15:25:26 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Roberto Bagnara ,
	Nicola Vetrini ,
	"consulting @ bugseng . com" 
Subject: [PATCH v2] xen: Use auto as per C23
Date: Thu, 14 Aug 2025 23:25:24 +0100
Message-Id: <20250814222524.2638883-1-andrew.cooper3@citrix.com>
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In macros it is common to declare local variables using typeof(param) in order
to ensure that side effects are only evaluated once.  A consequence of this is
double textural expansion of the parameter, which can get out of hand very
quickly with nested macros.

In C23, the auto keyword has been repurposed to perform type inference.

A GCC extension, __auto_type, is now avaialble in the new toolchain baseline
and avoids the double textural expansion.

Signed-off-by: Andrew Cooper 
---
CC: Anthony PERARD 
CC: Michal Orzel 
CC: Jan Beulich 
CC: Julien Grall 
CC: Roger Pau Monné 
CC: Stefano Stabellini 
CC: Roberto Bagnara 
CC: Nicola Vetrini 
CC: consulting@bugseng.com 

The resulting build is identical.

v2:
 * Use auto directly
 * Eclair configuration

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1985289434
---
 automation/eclair_analysis/ECLAIR/toolchain.ecl | 11 +++++++++--
 docs/misra/C-language-toolchain.rst             |  2 ++
 xen/include/xen/compiler.h                      | 14 ++++++++++++++
 xen/include/xen/macros.h                        | 14 +++++++-------
 4 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/automation/eclair_analysis/ECLAIR/toolchain.ecl b/automation/eclair_analysis/ECLAIR/toolchain.ecl
index 842f8377e561..125f99a06583 100644
--- a/automation/eclair_analysis/ECLAIR/toolchain.ecl
+++ b/automation/eclair_analysis/ECLAIR/toolchain.ecl
@@ -15,6 +15,7 @@
     __alignof__, __alignof: see Sections \"6.48 Alternate Keywords\" and \"6.44 Determining the Alignment of Functions, Types or Variables\" of "GCC_MANUAL".
     asm, __asm__: see Sections \"6.48 Alternate Keywords\" and \"6.47 How to Use Inline Assembly Language in C Code\" of "GCC_MANUAL".
     __attribute__: see Section \"6.39 Attribute Syntax\" of "GCC_MANUAL".
+    __auto_type: see Section \"6.7 Referring to a Type with typeof\" of "GCC_MANUAL".
     __builtin_offsetof: see Section \"6.53 Support for offsetof\" of "GCC_MANUAL".
     __builtin_types_compatible_p: see Section \"6.59 Other Built-in Functions Provided by GCC\" of "GCC_MANUAL".
     __builtin_va_arg: non-documented GCC extension.
@@ -26,6 +27,7 @@
 -name_selector+={alignof, "^(__alignof__|__alignof)$"}
 -name_selector+={asm, "^(__asm__|asm)$"}
 -name_selector+={attribute, "^__attribute__$"}
+-name_selector+={auto_type, "^__auto_type$"}
 -name_selector+={builtin_offsetof, "^__builtin_offsetof$"}
 -name_selector+={builtin_types_p, "^__builtin_types_compatible_p$"}
 -name_selector+={builtin_va_arg, "^__builtin_va_arg$"}
@@ -39,6 +41,7 @@
 "alignof||
 asm||
 attribute||
+auto_type||
 builtin_offsetof||
 builtin_types_p||
 builtin_va_arg||
@@ -114,6 +117,7 @@ volatile"
 -doc_end
 
 -doc_begin="
+    ext_auto_type: see Section \"6.7 Referring to a Type with typeof\" of "GCC_MANUAL".
     ext_c_missing_varargs_arg: see Section \"6.21 Macros with a Variable Number of Arguments\" of "GCC_MANUAL".
     ext_enum_value_not_int: non-documented GCC extension.
     ext_flexible_array_in_array: see Section \"6.18 Arrays of Length Zero\" of "GCC_MANUAL".
@@ -126,6 +130,7 @@ volatile"
     ext_return_has_void_expr: see the documentation for -Wreturn-type in Section \"3.8 Options to Request or Suppress Warnings\" of "GCC_MANUAL".
     ext_sizeof_alignof_void_type: see Section \"6.24 Arithmetic on void- and Function-Pointers\" of "GCC_MANUAL".
 "
+-name_selector+={ext_auto_type, "^ext_auto_type$"}
 -name_selector+={ext_c_missing_varargs_arg, "^ext_c_missing_varargs_arg$"}
 -name_selector+={ext_enum_value_not_int, "^ext_enum_value_not_int$"}
 -name_selector+={ext_flexible_array_in_array, "^ext_flexible_array_in_array$"}
@@ -139,7 +144,8 @@ volatile"
 -name_selector+={ext_sizeof_alignof_void_type, "^ext_sizeof_alignof_void_type$"}
 
 -config=STD.diag,behavior+={c99,GCC_ARM64,
-"ext_c_missing_varargs_arg||
+"ext_auto_type||
+ext_c_missing_varargs_arg||
 ext_forward_ref_enum_def||
 ext_gnu_array_range||
 ext_gnu_statement_expr_macro||
@@ -149,7 +155,8 @@ ext_return_has_void_expr||
 ext_sizeof_alignof_void_type"
 }
 -config=STD.diag,behavior+={c99,GCC_X86_64,
-"ext_c_missing_varargs_arg||
+"ext_auto_type||
+ext_c_missing_varargs_arg||
 ext_enum_value_not_int||
 ext_flexible_array_in_array||
 ext_flexible_array_in_struct||
diff --git a/docs/misra/C-language-toolchain.rst b/docs/misra/C-language-toolchain.rst
index cb81f5c09872..635936004554 100644
--- a/docs/misra/C-language-toolchain.rst
+++ b/docs/misra/C-language-toolchain.rst
@@ -94,6 +94,8 @@ The table columns are as follows:
           see Sections "6.48 Alternate Keywords" and "6.44 Determining the Alignment of Functions, Types or Variables" of GCC_MANUAL.
        __attribute__:
           see Section "6.39 Attribute Syntax" of GCC_MANUAL.
+       __auto_type:
+          see Section "6.7 Referring to a Type with typeof" of GCC_MANUAL.
        __builtin_types_compatible_p:
           see Section "6.59 Other Built-in Functions Provided by GCC" of GCC_MANUAL.
        __builtin_va_arg:
diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
index 88bf26bc5109..38ef5d82ad95 100644
--- a/xen/include/xen/compiler.h
+++ b/xen/include/xen/compiler.h
@@ -64,6 +64,20 @@
 # define asm_inline asm
 #endif
 
+/*
+ * In C23, the auto keyword has been repurposed to perform type inference.
+ *
+ * This behaviour is available via the __auto_type extension in supported
+ * toolchains.
+ *
+ * https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
+ * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
+ */
+#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
+/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23 meaning. */
+#define auto __auto_type
+#endif
+
 /*
  * Add the pseudo keyword 'fallthrough' so case statement blocks
  * must end with any of these keywords:
diff --git a/xen/include/xen/macros.h b/xen/include/xen/macros.h
index f9ccde86fb23..ceca2e4a1bf1 100644
--- a/xen/include/xen/macros.h
+++ b/xen/include/xen/macros.h
@@ -63,18 +63,18 @@
 /* Hide a value from the optimiser. */
 #define HIDE(x)                                 \
     ({                                          \
-        typeof(x) _x = (x);                     \
+        auto _x = (x);                          \
         asm volatile ( "" : "+r" (_x) );        \
         _x;                                     \
     })
 
 #define ABS(x) ({                              \
-    typeof(x) x_ = (x);                        \
+    auto x_ = (x);                             \
     (x_ < 0) ? -x_ : x_;                       \
 })
 
 #define SWAP(a, b) \
-   do { typeof(a) t_ = (a); (a) = (b); (b) = t_; } while ( 0 )
+   do { auto t_ = (a); (a) = (b); (b) = t_; } while ( 0 )
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]) + __must_be_array(x))
 
@@ -102,15 +102,15 @@
  */
 #define min(x, y)                               \
     ({                                          \
-        const typeof(x) _x = (x);               \
-        const typeof(y) _y = (y);               \
+        const auto _x = (x);                    \
+        const auto _y = (y);                    \
         (void)(&_x == &_y); /* typecheck */     \
         _x < _y ? _x : _y;                      \
     })
 #define max(x, y)                               \
     ({                                          \
-        const typeof(x) _x = (x);               \
-        const typeof(y) _y = (y);               \
+        const auto _x = (x);                    \
+        const auto _y = (y);                    \
         (void)(&_x == &_y); /* typecheck */     \
         _x > _y ? _x : _y;                      \
     })

base-commit: b2c0dc44b37516b758c38de04c61ad295ac0dff2
-- 
2.39.5



From xen-devel-bounces@lists.xenproject.org Thu Aug 14 23:14:39 2025
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Date: Thu, 14 Aug 2025 16:14:17 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Jan Beulich 
cc: "Penny, Zheng" , "Huang, Ray" , 
    Andrew Cooper , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Anthony PERARD , 
    "Orzel, Michal" , Julien Grall , 
    Stefano Stabellini , 
    "xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH v1 01/25] xen/x86: move domctl.o out of
 PV_SHIM_EXCLUSIVE
In-Reply-To: <3e20688c-c125-4aa4-bc06-1fe634550f70@suse.com>
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References: <20250803094738.3625269-1-Penny.Zheng@amd.com> <20250803094738.3625269-2-Penny.Zheng@amd.com> <371bc812-acdb-41ef-950b-3c9e5feea48e@suse.com> 
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On Tue, 5 Aug 2025, Jan Beulich wrote:
> On 05.08.2025 05:38, Penny, Zheng wrote:
> > [Public]
> > 
> >> -----Original Message-----
> >> From: Jan Beulich 
> >> Sent: Monday, August 4, 2025 3:43 PM
> >> To: Penny, Zheng 
> >> Cc: Huang, Ray ; Andrew Cooper
> >> ; Roger Pau Monné ;
> >> Anthony PERARD ; Orzel, Michal
> >> ; Julien Grall ; Stefano Stabellini
> >> ; xen-devel@lists.xenproject.org
> >> Subject: Re: [PATCH v1 01/25] xen/x86: move domctl.o out of
> >> PV_SHIM_EXCLUSIVE
> >>
> >> On 03.08.2025 11:47, Penny Zheng wrote:
> >>> In order to fix CI error of a randconfig picking both
> >>> PV_SHIM_EXCLUSIVE=y and HVM=y results in hvm.c being built, but
> >>> domctl.c not being built, which leaves a few functions, like
> >>> domctl_lock_acquire/release() undefined, causing linking to fail.
> >>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE
> >>> Makefile /hypercall-defs section, with this adjustment, we also need
> >>> to release redundant vnuma_destroy() stub definition and paging_domctl
> >>> hypercall-defs from PV_SHIM_EXCLUSIVE guardian, to not break
> >>> compilation Above change will leave dead code in the shim binary
> >>> temporarily and will be fixed with the introduction of CONFIG_DOMCTL.
> >>>
> >>> Fixes: 568f806cba4c ("xen/x86: remove "depends on
> >>> !PV_SHIM_EXCLUSIVE"")
> >>> Reported-by: Jan Beulich 
> >>> Signed-off-by: Penny Zheng 
> >>> ---
> >>> v1 -> v2:
> >>> - remove paging_domctl hypercall-defs
> >>
> >> And you've run this through a full round of testing this time, in isolation?
> > 
> > This commit shall be committed together with "xen/x86: complement PG_log_dirty wrapping", (I've added in change log, idk why it didn't get delivered in the mail list in the last).
> 
> And "committed together" still means the two at least build okay independently
> (i.e. allowing the build-each-commit job to succeed)?
> 
> As to the missing indication thereof in the submission: Patch 01 has a revlog,
> so if anything was missing there you must have added it some other way. But
> the cover letter is lacking that information as well. (As indicated earlier,
> to increase the chance of such a remark actually being noticed, it's best put
> in both places.)
> 
> > As PG_log_dirty is disabled on PV mode, paging_domctl() will still have "undefined reference" on PV mode, which gets fixed in "xen/x86: complement PG_log_dirty wrapping".  I thought it better sits there.
> > If it doesn't comply with the commit policy, I'll move according fix here.
> 
> Let me post a pair of patches dealing with part of the problem, in an imo
> (longer term) more desirable way.

With this patch https://marc.info/?l=xen-devel&m=175438069103017
committed, can we go ahead with this patch, to resolve the outstanding
build problem?

Reviewed-by: Stefano Stabellini 
--8323329-1533615221-1755212732=:10166--


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CC: 
Subject: [PATCH v8 2/8] arm64: entry: Refactor the entry and exit for exceptions from EL1
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The generic entry code uses irqentry_state_t to track lockdep and RCU
state across exception entry and return. For historical reasons, arm64
embeds similar fields within its pt_regs structure.

In preparation for moving arm64 over to the generic entry code, pull
these fields out of arm64's pt_regs, and use a separate structure,
matching the style of the generic entry code.

No functional changes.

Acked-by: Mark Rutland 
Reviewed-by: Ada Couprie Diaz 
Suggested-by: Mark Rutland 
Signed-off-by: Jinjie Ruan 
---
 arch/arm64/include/asm/ptrace.h  |   4 -
 arch/arm64/kernel/entry-common.c | 163 ++++++++++++++++++++-----------
 2 files changed, 106 insertions(+), 61 deletions(-)

diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index 8b915d4a9d4b..65b053a24d82 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -169,10 +169,6 @@ struct pt_regs {
 
 	u64 sdei_ttbr1;
 	struct frame_record_meta stackframe;
-
-	/* Only valid for some EL1 exceptions. */
-	u64 lockdep_hardirqs;
-	u64 exit_rcu;
 };
 
 /* For correct stack alignment, pt_regs has to be a multiple of 16 bytes. */
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index 8e798f46ad28..93c95fc51cc0 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -29,6 +29,13 @@
 #include 
 #include 
 
+typedef struct irqentry_state {
+	union {
+		bool	exit_rcu;
+		bool	lockdep;
+	};
+} arm64_irqentry_state_t;
+
 /*
  * Handle IRQ/context state management when entering from kernel mode.
  * Before this function is called it is not safe to call regular kernel code,
@@ -37,29 +44,37 @@
  * This is intended to match the logic in irqentry_enter(), handling the kernel
  * mode transitions only.
  */
-static __always_inline void __enter_from_kernel_mode(struct pt_regs *regs)
+static __always_inline arm64_irqentry_state_t __enter_from_kernel_mode(struct pt_regs *regs)
 {
-	regs->exit_rcu = false;
+	arm64_irqentry_state_t state = {
+		.exit_rcu = false,
+	};
 
 	if (!IS_ENABLED(CONFIG_TINY_RCU) && is_idle_task(current)) {
 		lockdep_hardirqs_off(CALLER_ADDR0);
 		ct_irq_enter();
 		trace_hardirqs_off_finish();
 
-		regs->exit_rcu = true;
-		return;
+		state.exit_rcu = true;
+		return state;
 	}
 
 	lockdep_hardirqs_off(CALLER_ADDR0);
 	rcu_irq_enter_check_tick();
 	trace_hardirqs_off_finish();
+
+	return state;
 }
 
-static void noinstr enter_from_kernel_mode(struct pt_regs *regs)
+static noinstr arm64_irqentry_state_t enter_from_kernel_mode(struct pt_regs *regs)
 {
-	__enter_from_kernel_mode(regs);
+	arm64_irqentry_state_t state;
+
+	state = __enter_from_kernel_mode(regs);
 	mte_check_tfsr_entry();
 	mte_disable_tco_entry(current);
+
+	return state;
 }
 
 /*
@@ -70,12 +85,13 @@ static void noinstr enter_from_kernel_mode(struct pt_regs *regs)
  * This is intended to match the logic in irqentry_exit(), handling the kernel
  * mode transitions only, and with preemption handled elsewhere.
  */
-static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs)
+static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs,
+						  arm64_irqentry_state_t state)
 {
 	lockdep_assert_irqs_disabled();
 
 	if (!regs_irqs_disabled(regs)) {
-		if (regs->exit_rcu) {
+		if (state.exit_rcu) {
 			trace_hardirqs_on_prepare();
 			lockdep_hardirqs_on_prepare();
 			ct_irq_exit();
@@ -85,15 +101,16 @@ static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs)
 
 		trace_hardirqs_on();
 	} else {
-		if (regs->exit_rcu)
+		if (state.exit_rcu)
 			ct_irq_exit();
 	}
 }
 
-static void noinstr exit_to_kernel_mode(struct pt_regs *regs)
+static void noinstr exit_to_kernel_mode(struct pt_regs *regs,
+					arm64_irqentry_state_t state)
 {
 	mte_check_tfsr_exit();
-	__exit_to_kernel_mode(regs);
+	__exit_to_kernel_mode(regs, state);
 }
 
 /*
@@ -194,9 +211,11 @@ asmlinkage void noinstr asm_exit_to_user_mode(struct pt_regs *regs)
  * mode. Before this function is called it is not safe to call regular kernel
  * code, instrumentable code, or any code which may trigger an exception.
  */
-static void noinstr arm64_enter_nmi(struct pt_regs *regs)
+static noinstr arm64_irqentry_state_t arm64_enter_nmi(struct pt_regs *regs)
 {
-	regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
+	arm64_irqentry_state_t state;
+
+	state.lockdep = lockdep_hardirqs_enabled();
 
 	__nmi_enter();
 	lockdep_hardirqs_off(CALLER_ADDR0);
@@ -205,6 +224,8 @@ static void noinstr arm64_enter_nmi(struct pt_regs *regs)
 
 	trace_hardirqs_off_finish();
 	ftrace_nmi_enter();
+
+	return state;
 }
 
 /*
@@ -212,19 +233,18 @@ static void noinstr arm64_enter_nmi(struct pt_regs *regs)
  * mode. After this function returns it is not safe to call regular kernel
  * code, instrumentable code, or any code which may trigger an exception.
  */
-static void noinstr arm64_exit_nmi(struct pt_regs *regs)
+static void noinstr arm64_exit_nmi(struct pt_regs *regs,
+				   arm64_irqentry_state_t state)
 {
-	bool restore = regs->lockdep_hardirqs;
-
 	ftrace_nmi_exit();
-	if (restore) {
+	if (state.lockdep) {
 		trace_hardirqs_on_prepare();
 		lockdep_hardirqs_on_prepare();
 	}
 
 	ct_nmi_exit();
 	lockdep_hardirq_exit();
-	if (restore)
+	if (state.lockdep)
 		lockdep_hardirqs_on(CALLER_ADDR0);
 	__nmi_exit();
 }
@@ -234,14 +254,18 @@ static void noinstr arm64_exit_nmi(struct pt_regs *regs)
  * kernel mode. Before this function is called it is not safe to call regular
  * kernel code, instrumentable code, or any code which may trigger an exception.
  */
-static void noinstr arm64_enter_el1_dbg(struct pt_regs *regs)
+static noinstr arm64_irqentry_state_t arm64_enter_el1_dbg(struct pt_regs *regs)
 {
-	regs->lockdep_hardirqs = lockdep_hardirqs_enabled();
+	arm64_irqentry_state_t state;
+
+	state.lockdep = lockdep_hardirqs_enabled();
 
 	lockdep_hardirqs_off(CALLER_ADDR0);
 	ct_nmi_enter();
 
 	trace_hardirqs_off_finish();
+
+	return state;
 }
 
 /*
@@ -249,17 +273,16 @@ static void noinstr arm64_enter_el1_dbg(struct pt_regs *regs)
  * kernel mode. After this function returns it is not safe to call regular
  * kernel code, instrumentable code, or any code which may trigger an exception.
  */
-static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs)
+static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs,
+				       arm64_irqentry_state_t state)
 {
-	bool restore = regs->lockdep_hardirqs;
-
-	if (restore) {
+	if (state.lockdep) {
 		trace_hardirqs_on_prepare();
 		lockdep_hardirqs_on_prepare();
 	}
 
 	ct_nmi_exit();
-	if (restore)
+	if (state.lockdep)
 		lockdep_hardirqs_on(CALLER_ADDR0);
 }
 
@@ -475,73 +498,87 @@ UNHANDLED(el1t, 64, error)
 static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
 {
 	unsigned long far = read_sysreg(far_el1);
+	arm64_irqentry_state_t state;
 
-	enter_from_kernel_mode(regs);
+	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
 	do_mem_abort(far, esr, regs);
 	local_daif_mask();
-	exit_to_kernel_mode(regs);
+	exit_to_kernel_mode(regs, state);
 }
 
 static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr)
 {
 	unsigned long far = read_sysreg(far_el1);
+	arm64_irqentry_state_t state;
 
-	enter_from_kernel_mode(regs);
+	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
 	do_sp_pc_abort(far, esr, regs);
 	local_daif_mask();
-	exit_to_kernel_mode(regs);
+	exit_to_kernel_mode(regs, state);
 }
 
 static void noinstr el1_undef(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_kernel_mode(regs);
+	arm64_irqentry_state_t state;
+
+	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
 	do_el1_undef(regs, esr);
 	local_daif_mask();
-	exit_to_kernel_mode(regs);
+	exit_to_kernel_mode(regs, state);
 }
 
 static void noinstr el1_bti(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_kernel_mode(regs);
+	arm64_irqentry_state_t state;
+
+	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
 	do_el1_bti(regs, esr);
 	local_daif_mask();
-	exit_to_kernel_mode(regs);
+	exit_to_kernel_mode(regs, state);
 }
 
 static void noinstr el1_gcs(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_kernel_mode(regs);
+	arm64_irqentry_state_t state;
+
+	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
 	do_el1_gcs(regs, esr);
 	local_daif_mask();
-	exit_to_kernel_mode(regs);
+	exit_to_kernel_mode(regs, state);
 }
 
 static void noinstr el1_mops(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_kernel_mode(regs);
+	arm64_irqentry_state_t state;
+
+	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
 	do_el1_mops(regs, esr);
 	local_daif_mask();
-	exit_to_kernel_mode(regs);
+	exit_to_kernel_mode(regs, state);
 }
 
 static void noinstr el1_breakpt(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_enter_el1_dbg(regs);
+	arm64_irqentry_state_t state;
+
+	state = arm64_enter_el1_dbg(regs);
 	debug_exception_enter(regs);
 	do_breakpoint(esr, regs);
 	debug_exception_exit(regs);
-	arm64_exit_el1_dbg(regs);
+	arm64_exit_el1_dbg(regs, state);
 }
 
 static void noinstr el1_softstp(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_enter_el1_dbg(regs);
+	arm64_irqentry_state_t state;
+
+	state = arm64_enter_el1_dbg(regs);
 	if (!cortex_a76_erratum_1463225_debug_handler(regs)) {
 		debug_exception_enter(regs);
 		/*
@@ -554,37 +591,42 @@ static void noinstr el1_softstp(struct pt_regs *regs, unsigned long esr)
 			do_el1_softstep(esr, regs);
 		debug_exception_exit(regs);
 	}
-	arm64_exit_el1_dbg(regs);
+	arm64_exit_el1_dbg(regs, state);
 }
 
 static void noinstr el1_watchpt(struct pt_regs *regs, unsigned long esr)
 {
 	/* Watchpoints are the only debug exception to write FAR_EL1 */
 	unsigned long far = read_sysreg(far_el1);
+	arm64_irqentry_state_t state;
 
-	arm64_enter_el1_dbg(regs);
+	state = arm64_enter_el1_dbg(regs);
 	debug_exception_enter(regs);
 	do_watchpoint(far, esr, regs);
 	debug_exception_exit(regs);
-	arm64_exit_el1_dbg(regs);
+	arm64_exit_el1_dbg(regs, state);
 }
 
 static void noinstr el1_brk64(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_enter_el1_dbg(regs);
+	arm64_irqentry_state_t state;
+
+	state = arm64_enter_el1_dbg(regs);
 	debug_exception_enter(regs);
 	do_el1_brk64(esr, regs);
 	debug_exception_exit(regs);
-	arm64_exit_el1_dbg(regs);
+	arm64_exit_el1_dbg(regs, state);
 }
 
 static void noinstr el1_fpac(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_kernel_mode(regs);
+	arm64_irqentry_state_t state;
+
+	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
 	do_el1_fpac(regs, esr);
 	local_daif_mask();
-	exit_to_kernel_mode(regs);
+	exit_to_kernel_mode(regs, state);
 }
 
 asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs)
@@ -639,15 +681,19 @@ asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs)
 static __always_inline void __el1_pnmi(struct pt_regs *regs,
 				       void (*handler)(struct pt_regs *))
 {
-	arm64_enter_nmi(regs);
+	arm64_irqentry_state_t state;
+
+	state = arm64_enter_nmi(regs);
 	do_interrupt_handler(regs, handler);
-	arm64_exit_nmi(regs);
+	arm64_exit_nmi(regs, state);
 }
 
 static __always_inline void __el1_irq(struct pt_regs *regs,
 				      void (*handler)(struct pt_regs *))
 {
-	enter_from_kernel_mode(regs);
+	arm64_irqentry_state_t state;
+
+	state = enter_from_kernel_mode(regs);
 
 	irq_enter_rcu();
 	do_interrupt_handler(regs, handler);
@@ -655,7 +701,7 @@ static __always_inline void __el1_irq(struct pt_regs *regs,
 
 	arm64_preempt_schedule_irq();
 
-	exit_to_kernel_mode(regs);
+	exit_to_kernel_mode(regs, state);
 }
 static void noinstr el1_interrupt(struct pt_regs *regs,
 				  void (*handler)(struct pt_regs *))
@@ -681,11 +727,12 @@ asmlinkage void noinstr el1h_64_fiq_handler(struct pt_regs *regs)
 asmlinkage void noinstr el1h_64_error_handler(struct pt_regs *regs)
 {
 	unsigned long esr = read_sysreg(esr_el1);
+	arm64_irqentry_state_t state;
 
 	local_daif_restore(DAIF_ERRCTX);
-	arm64_enter_nmi(regs);
+	state = arm64_enter_nmi(regs);
 	do_serror(regs, esr);
-	arm64_exit_nmi(regs);
+	arm64_exit_nmi(regs, state);
 }
 
 static void noinstr el0_da(struct pt_regs *regs, unsigned long esr)
@@ -997,12 +1044,13 @@ asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs)
 static void noinstr __el0_error_handler_common(struct pt_regs *regs)
 {
 	unsigned long esr = read_sysreg(esr_el1);
+	arm64_irqentry_state_t state;
 
 	enter_from_user_mode(regs);
 	local_daif_restore(DAIF_ERRCTX);
-	arm64_enter_nmi(regs);
+	state = arm64_enter_nmi(regs);
 	do_serror(regs, esr);
-	arm64_exit_nmi(regs);
+	arm64_exit_nmi(regs, state);
 	local_daif_restore(DAIF_PROCCTX);
 	exit_to_user_mode(regs);
 }
@@ -1122,6 +1170,7 @@ asmlinkage void noinstr __noreturn handle_bad_stack(struct pt_regs *regs)
 asmlinkage noinstr unsigned long
 __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
 {
+	arm64_irqentry_state_t state;
 	unsigned long ret;
 
 	/*
@@ -1146,9 +1195,9 @@ __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
 	else if (cpu_has_pan())
 		set_pstate_pan(0);
 
-	arm64_enter_nmi(regs);
+	state = arm64_enter_nmi(regs);
 	ret = do_sdei_event(regs, arg);
-	arm64_exit_nmi(regs);
+	arm64_exit_nmi(regs, state);
 
 	return ret;
 }
-- 
2.34.1



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CC: 
Subject: [PATCH v8 7/8] arm64: entry: Move arm64_preempt_schedule_irq() into __exit_to_kernel_mode()
Date: Fri, 15 Aug 2025 11:06:32 +0800
Message-ID: <20250815030633.448613-8-ruanjinjie@huawei.com>
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The arm64 entry code only preempts a kernel context upon a return from
a regular IRQ exception. The generic entry code may preempt a kernel
context for any exception return where irqentry_exit() is used, and so
may preempt other exceptions such as faults.

In preparation for moving arm64 over to the generic entry code, align
arm64 with the generic behaviour by calling
arm64_preempt_schedule_irq() from exit_to_kernel_mode(). To make this
possible, arm64_preempt_schedule_irq()
and dynamic/raw_irqentry_exit_cond_resched() are moved earlier in
the file, with no changes.

As Mark pointed out, this change will have the following 2 key impact:

- " We'll preempt even without taking a "real" interrupt. That
    shouldn't result in preemption that wasn't possible before,
    but it does change the probability of preempting at certain points,
    and might have a performance impact, so probably warrants a
    benchmark."

- " We will not preempt when taking interrupts from a region of kernel
    code where IRQs are enabled but RCU is not watching, matching the
    behaviour of the generic entry code.

    This has the potential to introduce livelock if we can ever have a
    screaming interrupt in such a region, so we'll need to go figure out
    whether that's actually a problem.

    Having this as a separate patch will make it easier to test/bisect
    for that specifically."

Reviewed-by: Ada Couprie Diaz 
Suggested-by: Mark Rutland 
Signed-off-by: Jinjie Ruan 
---
 arch/arm64/kernel/entry-common.c | 96 ++++++++++++++++----------------
 1 file changed, 48 insertions(+), 48 deletions(-)

diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index 64066c643f97..f52067d17baf 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -77,6 +77,51 @@ static noinstr arm64_irqentry_state_t enter_from_kernel_mode(struct pt_regs *reg
 	return state;
 }
 
+static inline bool arm64_preempt_schedule_irq(void)
+{
+	/*
+	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
+	 * priority masking is used the GIC irqchip driver will clear DAIF.IF
+	 * using gic_arch_enable_irqs() for normal IRQs. If anything is set in
+	 * DAIF we must have handled an NMI, so skip preemption.
+	 */
+	if (system_uses_irq_prio_masking() && read_sysreg(daif))
+		return false;
+
+	/*
+	 * Preempting a task from an IRQ means we leave copies of PSTATE
+	 * on the stack. cpufeature's enable calls may modify PSTATE, but
+	 * resuming one of these preempted tasks would undo those changes.
+	 *
+	 * Only allow a task to be preempted once cpufeatures have been
+	 * enabled.
+	 */
+	if (!system_capabilities_finalized())
+		return false;
+
+	return true;
+}
+
+#ifdef CONFIG_PREEMPTION
+void raw_irqentry_exit_cond_resched(void)
+{
+	if (!preempt_count()) {
+		if (need_resched() && arm64_preempt_schedule_irq())
+			preempt_schedule_irq();
+	}
+}
+#endif
+
+#ifdef CONFIG_PREEMPT_DYNAMIC
+DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
+void dynamic_irqentry_exit_cond_resched(void)
+{
+	if (!static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
+		return;
+	raw_irqentry_exit_cond_resched();
+}
+#endif
+
 /*
  * Handle IRQ/context state management when exiting to kernel mode.
  * After this function returns it is not safe to call regular kernel code,
@@ -99,6 +144,9 @@ static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs,
 			return;
 		}
 
+		if (IS_ENABLED(CONFIG_PREEMPTION))
+			irqentry_exit_cond_resched();
+
 		trace_hardirqs_on();
 	} else {
 		if (state.exit_rcu)
@@ -286,31 +334,6 @@ static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs,
 		lockdep_hardirqs_on(CALLER_ADDR0);
 }
 
-static inline bool arm64_preempt_schedule_irq(void)
-{
-	/*
-	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
-	 * priority masking is used the GIC irqchip driver will clear DAIF.IF
-	 * using gic_arch_enable_irqs() for normal IRQs. If anything is set in
-	 * DAIF we must have handled an NMI, so skip preemption.
-	 */
-	if (system_uses_irq_prio_masking() && read_sysreg(daif))
-		return false;
-
-	/*
-	 * Preempting a task from an IRQ means we leave copies of PSTATE
-	 * on the stack. cpufeature's enable calls may modify PSTATE, but
-	 * resuming one of these preempted tasks would undo those changes.
-	 *
-	 * Only allow a task to be preempted once cpufeatures have been
-	 * enabled.
-	 */
-	if (!system_capabilities_finalized())
-		return false;
-
-	return true;
-}
-
 static void do_interrupt_handler(struct pt_regs *regs,
 				 void (*handler)(struct pt_regs *))
 {
@@ -671,26 +694,6 @@ static __always_inline void __el1_pnmi(struct pt_regs *regs,
 	arm64_exit_nmi(regs, state);
 }
 
-#ifdef CONFIG_PREEMPTION
-void raw_irqentry_exit_cond_resched(void)
-{
-	if (!preempt_count()) {
-		if (need_resched() && arm64_preempt_schedule_irq())
-			preempt_schedule_irq();
-	}
-}
-#endif
-
-#ifdef CONFIG_PREEMPT_DYNAMIC
-DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
-void dynamic_irqentry_exit_cond_resched(void)
-{
-	if (!static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
-		return;
-	raw_irqentry_exit_cond_resched();
-}
-#endif
-
 static __always_inline void __el1_irq(struct pt_regs *regs,
 				      void (*handler)(struct pt_regs *))
 {
@@ -702,9 +705,6 @@ static __always_inline void __el1_irq(struct pt_regs *regs,
 	do_interrupt_handler(regs, handler);
 	irq_exit_rcu();
 
-	if (IS_ENABLED(CONFIG_PREEMPTION))
-		irqentry_exit_cond_resched();
-
 	exit_to_kernel_mode(regs, state);
 }
 static void noinstr el1_interrupt(struct pt_regs *regs,
-- 
2.34.1



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CC: 
Subject: [PATCH v8 6/8] arm64: entry: Refactor preempt_schedule_irq() check code
Date: Fri, 15 Aug 2025 11:06:31 +0800
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To align the structure of the code with irqentry_exit_cond_resched()
from the generic entry code, hoist the need_irq_preemption()
and IS_ENABLED() check earlier. And different preemption check functions
are defined based on whether dynamic preemption is enabled.

Signed-off-by: Jinjie Ruan 
---
 arch/arm64/include/asm/preempt.h |  6 ++++++
 arch/arm64/kernel/entry-common.c | 37 +++++++++++++++++++-------------
 2 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/arch/arm64/include/asm/preempt.h b/arch/arm64/include/asm/preempt.h
index 0159b625cc7f..c2437ea0790f 100644
--- a/arch/arm64/include/asm/preempt.h
+++ b/arch/arm64/include/asm/preempt.h
@@ -85,6 +85,7 @@ static inline bool should_resched(int preempt_offset)
 void preempt_schedule(void);
 void preempt_schedule_notrace(void);
 
+void raw_irqentry_exit_cond_resched(void);
 #ifdef CONFIG_PREEMPT_DYNAMIC
 
 DECLARE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
@@ -92,13 +93,18 @@ void dynamic_preempt_schedule(void);
 #define __preempt_schedule()		dynamic_preempt_schedule()
 void dynamic_preempt_schedule_notrace(void);
 #define __preempt_schedule_notrace()	dynamic_preempt_schedule_notrace()
+void dynamic_irqentry_exit_cond_resched(void);
+#define irqentry_exit_cond_resched()	dynamic_irqentry_exit_cond_resched()
 
 #else /* CONFIG_PREEMPT_DYNAMIC */
 
 #define __preempt_schedule()		preempt_schedule()
 #define __preempt_schedule_notrace()	preempt_schedule_notrace()
+#define irqentry_exit_cond_resched()	raw_irqentry_exit_cond_resched()
 
 #endif /* CONFIG_PREEMPT_DYNAMIC */
+#else /* CONFIG_PREEMPTION */
+#define irqentry_exit_cond_resched()	{}
 #endif /* CONFIG_PREEMPTION */
 
 #endif /* __ASM_PREEMPT_H */
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index 1ba1d40fa6a7..64066c643f97 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -286,19 +286,8 @@ static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs,
 		lockdep_hardirqs_on(CALLER_ADDR0);
 }
 
-#ifdef CONFIG_PREEMPT_DYNAMIC
-DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
-#define need_irq_preemption() \
-	(static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
-#else
-#define need_irq_preemption()	(IS_ENABLED(CONFIG_PREEMPTION))
-#endif
-
 static inline bool arm64_preempt_schedule_irq(void)
 {
-	if (!need_irq_preemption())
-		return false;
-
 	/*
 	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
 	 * priority masking is used the GIC irqchip driver will clear DAIF.IF
@@ -682,6 +671,26 @@ static __always_inline void __el1_pnmi(struct pt_regs *regs,
 	arm64_exit_nmi(regs, state);
 }
 
+#ifdef CONFIG_PREEMPTION
+void raw_irqentry_exit_cond_resched(void)
+{
+	if (!preempt_count()) {
+		if (need_resched() && arm64_preempt_schedule_irq())
+			preempt_schedule_irq();
+	}
+}
+#endif
+
+#ifdef CONFIG_PREEMPT_DYNAMIC
+DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
+void dynamic_irqentry_exit_cond_resched(void)
+{
+	if (!static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
+		return;
+	raw_irqentry_exit_cond_resched();
+}
+#endif
+
 static __always_inline void __el1_irq(struct pt_regs *regs,
 				      void (*handler)(struct pt_regs *))
 {
@@ -693,10 +702,8 @@ static __always_inline void __el1_irq(struct pt_regs *regs,
 	do_interrupt_handler(regs, handler);
 	irq_exit_rcu();
 
-	if (!preempt_count() && need_resched()) {
-		if (arm64_preempt_schedule_irq())
-			preempt_schedule_irq();
-	}
+	if (IS_ENABLED(CONFIG_PREEMPTION))
+		irqentry_exit_cond_resched();
 
 	exit_to_kernel_mode(regs, state);
 }
-- 
2.34.1



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CC: 
Subject: [PATCH v8 4/8] arm64: entry: Use preempt_count() and need_resched() helper
Date: Fri, 15 Aug 2025 11:06:29 +0800
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The generic entry code uses preempt_count() and need_resched() helpers to
check if it should do preempt_schedule_irq(). Currently, arm64 use its own
check logic, that is "READ_ONCE(current_thread_info()->preempt_count == 0",
which is equivalent to "preempt_count() == 0 && need_resched()".

In preparation for moving arm64 over to the generic entry code, use
these helpers to replace arm64's own code and move it ahead.

No functional changes.

Reviewed-by: Ada Couprie Diaz 
Signed-off-by: Jinjie Ruan 
---
 arch/arm64/kernel/entry-common.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index dd7903f371ad..1ba1d40fa6a7 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -299,14 +299,6 @@ static inline bool arm64_preempt_schedule_irq(void)
 	if (!need_irq_preemption())
 		return false;
 
-	/*
-	 * Note: thread_info::preempt_count includes both thread_info::count
-	 * and thread_info::need_resched, and is not equivalent to
-	 * preempt_count().
-	 */
-	if (READ_ONCE(current_thread_info()->preempt_count) != 0)
-		return false;
-
 	/*
 	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
 	 * priority masking is used the GIC irqchip driver will clear DAIF.IF
@@ -701,8 +693,10 @@ static __always_inline void __el1_irq(struct pt_regs *regs,
 	do_interrupt_handler(regs, handler);
 	irq_exit_rcu();
 
-	if (arm64_preempt_schedule_irq())
-		preempt_schedule_irq();
+	if (!preempt_count() && need_resched()) {
+		if (arm64_preempt_schedule_irq())
+			preempt_schedule_irq();
+	}
 
 	exit_to_kernel_mode(regs, state);
 }
-- 
2.34.1



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CC: 
Subject: [PATCH v8 1/8] arm64: ptrace: Replace interrupts_enabled() with regs_irqs_disabled()
Date: Fri, 15 Aug 2025 11:06:26 +0800
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The generic entry code expects architecture code to provide
regs_irqs_disabled(regs) function, but arm64 does not have this and
provides interrupts_enabled(regs), which has the opposite polarity.

In preparation for moving arm64 over to the generic entry code,
relace arm64's interrupts_enabled() with regs_irqs_disabled() and
update its callers under arch/arm64.

For the moment, a definition of interrupts_enabled() is provided for
the GICv3 driver. Once arch/arm implement regs_irqs_disabled(), this
can be removed.

Delete the fast_interrupts_enabled() macro as it is unused and we
don't want any new users to show up.

No functional changes.

Reviewed-by: Ada Couprie Diaz 
Acked-by: Mark Rutland 
Suggested-by: Mark Rutland 
Signed-off-by: Jinjie Ruan 
---
 arch/arm64/include/asm/daifflags.h  | 2 +-
 arch/arm64/include/asm/ptrace.h     | 9 +++++----
 arch/arm64/include/asm/xen/events.h | 2 +-
 arch/arm64/kernel/acpi.c            | 2 +-
 arch/arm64/kernel/debug-monitors.c  | 2 +-
 arch/arm64/kernel/entry-common.c    | 4 ++--
 arch/arm64/kernel/sdei.c            | 2 +-
 7 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/include/asm/daifflags.h b/arch/arm64/include/asm/daifflags.h
index fbb5c99eb2f9..5fca48009043 100644
--- a/arch/arm64/include/asm/daifflags.h
+++ b/arch/arm64/include/asm/daifflags.h
@@ -128,7 +128,7 @@ static inline void local_daif_inherit(struct pt_regs *regs)
 {
 	unsigned long flags = regs->pstate & DAIF_MASK;
 
-	if (interrupts_enabled(regs))
+	if (!regs_irqs_disabled(regs))
 		trace_hardirqs_on();
 
 	if (system_uses_irq_prio_masking())
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index 47ff8654c5ec..8b915d4a9d4b 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -214,11 +214,12 @@ static inline void forget_syscall(struct pt_regs *regs)
 		(regs)->pmr == GIC_PRIO_IRQON :				\
 		true)
 
-#define interrupts_enabled(regs)			\
-	(!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
+static __always_inline bool regs_irqs_disabled(const struct pt_regs *regs)
+{
+	return (regs->pstate & PSR_I_BIT) || !irqs_priority_unmasked(regs);
+}
 
-#define fast_interrupts_enabled(regs) \
-	(!((regs)->pstate & PSR_F_BIT))
+#define interrupts_enabled(regs)	(!regs_irqs_disabled(regs))
 
 static inline unsigned long user_stack_pointer(struct pt_regs *regs)
 {
diff --git a/arch/arm64/include/asm/xen/events.h b/arch/arm64/include/asm/xen/events.h
index 2788e95d0ff0..2977b5fe068d 100644
--- a/arch/arm64/include/asm/xen/events.h
+++ b/arch/arm64/include/asm/xen/events.h
@@ -14,7 +14,7 @@ enum ipi_vector {
 
 static inline int xen_irqs_disabled(struct pt_regs *regs)
 {
-	return !interrupts_enabled(regs);
+	return regs_irqs_disabled(regs);
 }
 
 #define xchg_xen_ulong(ptr, val) xchg((ptr), (val))
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index 4d529ff7ba51..3fbce0a9a0fe 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -407,7 +407,7 @@ int apei_claim_sea(struct pt_regs *regs)
 	return_to_irqs_enabled = !irqs_disabled_flags(arch_local_save_flags());
 
 	if (regs)
-		return_to_irqs_enabled = interrupts_enabled(regs);
+		return_to_irqs_enabled = !regs_irqs_disabled(regs);
 
 	/*
 	 * SEA can interrupt SError, mask it and describe this as an NMI so
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index 110d9ff54174..85fc162a6f9b 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -167,7 +167,7 @@ static void send_user_sigtrap(int si_code)
 	if (WARN_ON(!user_mode(regs)))
 		return;
 
-	if (interrupts_enabled(regs))
+	if (!regs_irqs_disabled(regs))
 		local_irq_enable();
 
 	arm64_force_sig_fault(SIGTRAP, si_code, instruction_pointer(regs),
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index 2b0c5925502e..8e798f46ad28 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -74,7 +74,7 @@ static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs)
 {
 	lockdep_assert_irqs_disabled();
 
-	if (interrupts_enabled(regs)) {
+	if (!regs_irqs_disabled(regs)) {
 		if (regs->exit_rcu) {
 			trace_hardirqs_on_prepare();
 			lockdep_hardirqs_on_prepare();
@@ -662,7 +662,7 @@ static void noinstr el1_interrupt(struct pt_regs *regs,
 {
 	write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
 
-	if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && !interrupts_enabled(regs))
+	if (IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && regs_irqs_disabled(regs))
 		__el1_pnmi(regs, handler);
 	else
 		__el1_irq(regs, handler);
diff --git a/arch/arm64/kernel/sdei.c b/arch/arm64/kernel/sdei.c
index 6f24a0251e18..95169f7b6531 100644
--- a/arch/arm64/kernel/sdei.c
+++ b/arch/arm64/kernel/sdei.c
@@ -243,7 +243,7 @@ unsigned long __kprobes do_sdei_event(struct pt_regs *regs,
 	 * If we interrupted the kernel with interrupts masked, we always go
 	 * back to wherever we came from.
 	 */
-	if (mode == kernel_mode && !interrupts_enabled(regs))
+	if (mode == kernel_mode && regs_irqs_disabled(regs))
 		return SDEI_EV_HANDLED;
 
 	/*
-- 
2.34.1



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CC: 
Subject: [PATCH v8 3/8] arm64: entry: Rework arm64_preempt_schedule_irq()
Date: Fri, 15 Aug 2025 11:06:28 +0800
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The generic entry code has the form:

| raw_irqentry_exit_cond_resched()
| {
| 	if (!preempt_count()) {
| 		...
| 		if (need_resched())
| 			preempt_schedule_irq();
| 	}
| }

In preparation for moving arm64 over to the generic entry code, align
the structure of the arm64 code with raw_irqentry_exit_cond_resched() from
the generic entry code.

Reviewed-by: Ada Couprie Diaz 
Signed-off-by: Jinjie Ruan 
---
 arch/arm64/kernel/entry-common.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index 93c95fc51cc0..dd7903f371ad 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -294,10 +294,10 @@ DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
 #define need_irq_preemption()	(IS_ENABLED(CONFIG_PREEMPTION))
 #endif
 
-static void __sched arm64_preempt_schedule_irq(void)
+static inline bool arm64_preempt_schedule_irq(void)
 {
 	if (!need_irq_preemption())
-		return;
+		return false;
 
 	/*
 	 * Note: thread_info::preempt_count includes both thread_info::count
@@ -305,7 +305,7 @@ static void __sched arm64_preempt_schedule_irq(void)
 	 * preempt_count().
 	 */
 	if (READ_ONCE(current_thread_info()->preempt_count) != 0)
-		return;
+		return false;
 
 	/*
 	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
@@ -314,7 +314,7 @@ static void __sched arm64_preempt_schedule_irq(void)
 	 * DAIF we must have handled an NMI, so skip preemption.
 	 */
 	if (system_uses_irq_prio_masking() && read_sysreg(daif))
-		return;
+		return false;
 
 	/*
 	 * Preempting a task from an IRQ means we leave copies of PSTATE
@@ -324,8 +324,10 @@ static void __sched arm64_preempt_schedule_irq(void)
 	 * Only allow a task to be preempted once cpufeatures have been
 	 * enabled.
 	 */
-	if (system_capabilities_finalized())
-		preempt_schedule_irq();
+	if (!system_capabilities_finalized())
+		return false;
+
+	return true;
 }
 
 static void do_interrupt_handler(struct pt_regs *regs,
@@ -699,7 +701,8 @@ static __always_inline void __el1_irq(struct pt_regs *regs,
 	do_interrupt_handler(regs, handler);
 	irq_exit_rcu();
 
-	arm64_preempt_schedule_irq();
+	if (arm64_preempt_schedule_irq())
+		preempt_schedule_irq();
 
 	exit_to_kernel_mode(regs, state);
 }
-- 
2.34.1



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CC: 
Subject: [PATCH v8 8/8] arm64: entry: Switch to generic IRQ entry
Date: Fri, 15 Aug 2025 11:06:33 +0800
Message-ID: <20250815030633.448613-9-ruanjinjie@huawei.com>
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 dggpemf500011.china.huawei.com (7.185.36.131)

Currently, x86, Riscv and Loongarch use the generic entry code, which
makes maintainer's work easier and code more elegant. Start converting
arm64 to use the generic entry infrastructure from kernel/entry/* by
switching it to generic IRQ entry, which removes 100+ lines of duplicate
code. arm64 will completely switch to generic entry in a later series.

The changes are below:
 - Remove *enter_from/exit_to_kernel_mode(), and wrap with generic
   irqentry_enter/exit() as their code and functionality are almost
   identical.

 - Define ARCH_EXIT_TO_USER_MODE_WORK and implement
   arch_exit_to_user_mode_work() to check arm64-specific thread flags
   "_TIF_MTE_ASYNC_FAULT" and "_TIF_FOREIGN_FPSTATE".
   So also remove *enter_from/exit_to_user_mode(), and wrap with
   generic enter_from/exit_to_user_mode() because they are
   exactly the same.

 - Remove arm64_enter/exit_nmi() and use generic irqentry_nmi_enter/exit()
   because they're exactly the same, so the temporary arm64 version
   irqentry_state can also be removed.

 - Remove PREEMPT_DYNAMIC code, as generic irqentry_exit_cond_resched()
   has the same functionality.

 - Implement arch_irqentry_exit_need_resched() with
   arm64_preempt_schedule_irq() for arm64 which will allow arm64 to do
   its architecture specific checks.

Tested-by: Ada Couprie Diaz 
Suggested-by: Ada Couprie Diaz 
Suggested-by: Mark Rutland 
Signed-off-by: Jinjie Ruan 
---
 arch/arm64/Kconfig                    |   1 +
 arch/arm64/include/asm/entry-common.h |  57 ++++
 arch/arm64/include/asm/exception.h    |   1 -
 arch/arm64/include/asm/preempt.h      |   8 -
 arch/arm64/kernel/entry-common.c      | 378 +++++++-------------------
 arch/arm64/kernel/signal.c            |   3 +-
 6 files changed, 156 insertions(+), 292 deletions(-)
 create mode 100644 arch/arm64/include/asm/entry-common.h

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index e9bbfacc35a6..6bb60a0620ec 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -151,6 +151,7 @@ config ARM64
 	select GENERIC_EARLY_IOREMAP
 	select GENERIC_IDLE_POLL_SETUP
 	select GENERIC_IOREMAP
+	select GENERIC_IRQ_ENTRY
 	select GENERIC_IRQ_IPI
 	select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD
 	select GENERIC_IRQ_PROBE
diff --git a/arch/arm64/include/asm/entry-common.h b/arch/arm64/include/asm/entry-common.h
new file mode 100644
index 000000000000..cab8cd78f693
--- /dev/null
+++ b/arch/arm64/include/asm/entry-common.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _ASM_ARM64_ENTRY_COMMON_H
+#define _ASM_ARM64_ENTRY_COMMON_H
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ARCH_EXIT_TO_USER_MODE_WORK (_TIF_MTE_ASYNC_FAULT | _TIF_FOREIGN_FPSTATE)
+
+static __always_inline void arch_exit_to_user_mode_work(struct pt_regs *regs,
+							unsigned long ti_work)
+{
+	if (ti_work & _TIF_MTE_ASYNC_FAULT) {
+		clear_thread_flag(TIF_MTE_ASYNC_FAULT);
+		send_sig_fault(SIGSEGV, SEGV_MTEAERR, (void __user *)NULL, current);
+	}
+
+	if (ti_work & _TIF_FOREIGN_FPSTATE)
+		fpsimd_restore_current_state();
+}
+
+#define arch_exit_to_user_mode_work arch_exit_to_user_mode_work
+
+static inline bool arch_irqentry_exit_need_resched(void)
+{
+	/*
+	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
+	 * priority masking is used the GIC irqchip driver will clear DAIF.IF
+	 * using gic_arch_enable_irqs() for normal IRQs. If anything is set in
+	 * DAIF we must have handled an NMI, so skip preemption.
+	 */
+	if (system_uses_irq_prio_masking() && read_sysreg(daif))
+		return false;
+
+	/*
+	 * Preempting a task from an IRQ means we leave copies of PSTATE
+	 * on the stack. cpufeature's enable calls may modify PSTATE, but
+	 * resuming one of these preempted tasks would undo those changes.
+	 *
+	 * Only allow a task to be preempted once cpufeatures have been
+	 * enabled.
+	 */
+	if (!system_capabilities_finalized())
+		return false;
+
+	return true;
+}
+
+#define arch_irqentry_exit_need_resched arch_irqentry_exit_need_resched
+
+#endif /* _ASM_ARM64_ENTRY_COMMON_H */
diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h
index e3874c4fc399..a2da3cb21c24 100644
--- a/arch/arm64/include/asm/exception.h
+++ b/arch/arm64/include/asm/exception.h
@@ -89,7 +89,6 @@ void do_el1_fpac(struct pt_regs *regs, unsigned long esr);
 void do_el0_mops(struct pt_regs *regs, unsigned long esr);
 void do_el1_mops(struct pt_regs *regs, unsigned long esr);
 void do_serror(struct pt_regs *regs, unsigned long esr);
-void do_signal(struct pt_regs *regs);
 
 void __noreturn panic_bad_stack(struct pt_regs *regs, unsigned long esr, unsigned long far);
 #endif	/* __ASM_EXCEPTION_H */
diff --git a/arch/arm64/include/asm/preempt.h b/arch/arm64/include/asm/preempt.h
index c2437ea0790f..932ea4b62042 100644
--- a/arch/arm64/include/asm/preempt.h
+++ b/arch/arm64/include/asm/preempt.h
@@ -2,7 +2,6 @@
 #ifndef __ASM_PREEMPT_H
 #define __ASM_PREEMPT_H
 
-#include 
 #include 
 
 #define PREEMPT_NEED_RESCHED	BIT(32)
@@ -85,26 +84,19 @@ static inline bool should_resched(int preempt_offset)
 void preempt_schedule(void);
 void preempt_schedule_notrace(void);
 
-void raw_irqentry_exit_cond_resched(void);
 #ifdef CONFIG_PREEMPT_DYNAMIC
 
-DECLARE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
 void dynamic_preempt_schedule(void);
 #define __preempt_schedule()		dynamic_preempt_schedule()
 void dynamic_preempt_schedule_notrace(void);
 #define __preempt_schedule_notrace()	dynamic_preempt_schedule_notrace()
-void dynamic_irqentry_exit_cond_resched(void);
-#define irqentry_exit_cond_resched()	dynamic_irqentry_exit_cond_resched()
 
 #else /* CONFIG_PREEMPT_DYNAMIC */
 
 #define __preempt_schedule()		preempt_schedule()
 #define __preempt_schedule_notrace()	preempt_schedule_notrace()
-#define irqentry_exit_cond_resched()	raw_irqentry_exit_cond_resched()
 
 #endif /* CONFIG_PREEMPT_DYNAMIC */
-#else /* CONFIG_PREEMPTION */
-#define irqentry_exit_cond_resched()	{}
 #endif /* CONFIG_PREEMPTION */
 
 #endif /* __ASM_PREEMPT_H */
diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c
index f52067d17baf..f546a914f041 100644
--- a/arch/arm64/kernel/entry-common.c
+++ b/arch/arm64/kernel/entry-common.c
@@ -6,6 +6,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -29,13 +30,6 @@
 #include 
 #include 
 
-typedef struct irqentry_state {
-	union {
-		bool	exit_rcu;
-		bool	lockdep;
-	};
-} arm64_irqentry_state_t;
-
 /*
  * Handle IRQ/context state management when entering from kernel mode.
  * Before this function is called it is not safe to call regular kernel code,
@@ -44,31 +38,14 @@ typedef struct irqentry_state {
  * This is intended to match the logic in irqentry_enter(), handling the kernel
  * mode transitions only.
  */
-static __always_inline arm64_irqentry_state_t __enter_from_kernel_mode(struct pt_regs *regs)
+static __always_inline irqentry_state_t __enter_from_kernel_mode(struct pt_regs *regs)
 {
-	arm64_irqentry_state_t state = {
-		.exit_rcu = false,
-	};
-
-	if (!IS_ENABLED(CONFIG_TINY_RCU) && is_idle_task(current)) {
-		lockdep_hardirqs_off(CALLER_ADDR0);
-		ct_irq_enter();
-		trace_hardirqs_off_finish();
-
-		state.exit_rcu = true;
-		return state;
-	}
-
-	lockdep_hardirqs_off(CALLER_ADDR0);
-	rcu_irq_enter_check_tick();
-	trace_hardirqs_off_finish();
-
-	return state;
+	return irqentry_enter(regs);
 }
 
-static noinstr arm64_irqentry_state_t enter_from_kernel_mode(struct pt_regs *regs)
+static noinstr irqentry_state_t enter_from_kernel_mode(struct pt_regs *regs)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = __enter_from_kernel_mode(regs);
 	mte_check_tfsr_entry();
@@ -77,51 +54,6 @@ static noinstr arm64_irqentry_state_t enter_from_kernel_mode(struct pt_regs *reg
 	return state;
 }
 
-static inline bool arm64_preempt_schedule_irq(void)
-{
-	/*
-	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
-	 * priority masking is used the GIC irqchip driver will clear DAIF.IF
-	 * using gic_arch_enable_irqs() for normal IRQs. If anything is set in
-	 * DAIF we must have handled an NMI, so skip preemption.
-	 */
-	if (system_uses_irq_prio_masking() && read_sysreg(daif))
-		return false;
-
-	/*
-	 * Preempting a task from an IRQ means we leave copies of PSTATE
-	 * on the stack. cpufeature's enable calls may modify PSTATE, but
-	 * resuming one of these preempted tasks would undo those changes.
-	 *
-	 * Only allow a task to be preempted once cpufeatures have been
-	 * enabled.
-	 */
-	if (!system_capabilities_finalized())
-		return false;
-
-	return true;
-}
-
-#ifdef CONFIG_PREEMPTION
-void raw_irqentry_exit_cond_resched(void)
-{
-	if (!preempt_count()) {
-		if (need_resched() && arm64_preempt_schedule_irq())
-			preempt_schedule_irq();
-	}
-}
-#endif
-
-#ifdef CONFIG_PREEMPT_DYNAMIC
-DEFINE_STATIC_KEY_TRUE(sk_dynamic_irqentry_exit_cond_resched);
-void dynamic_irqentry_exit_cond_resched(void)
-{
-	if (!static_branch_unlikely(&sk_dynamic_irqentry_exit_cond_resched))
-		return;
-	raw_irqentry_exit_cond_resched();
-}
-#endif
-
 /*
  * Handle IRQ/context state management when exiting to kernel mode.
  * After this function returns it is not safe to call regular kernel code,
@@ -131,31 +63,13 @@ void dynamic_irqentry_exit_cond_resched(void)
  * mode transitions only, and with preemption handled elsewhere.
  */
 static __always_inline void __exit_to_kernel_mode(struct pt_regs *regs,
-						  arm64_irqentry_state_t state)
-{
-	lockdep_assert_irqs_disabled();
-
-	if (!regs_irqs_disabled(regs)) {
-		if (state.exit_rcu) {
-			trace_hardirqs_on_prepare();
-			lockdep_hardirqs_on_prepare();
-			ct_irq_exit();
-			lockdep_hardirqs_on(CALLER_ADDR0);
-			return;
-		}
-
-		if (IS_ENABLED(CONFIG_PREEMPTION))
-			irqentry_exit_cond_resched();
-
-		trace_hardirqs_on();
-	} else {
-		if (state.exit_rcu)
-			ct_irq_exit();
-	}
+						  irqentry_state_t state)
+{
+	irqentry_exit(regs, state);
 }
 
 static void noinstr exit_to_kernel_mode(struct pt_regs *regs,
-					arm64_irqentry_state_t state)
+					irqentry_state_t state)
 {
 	mte_check_tfsr_exit();
 	__exit_to_kernel_mode(regs, state);
@@ -166,18 +80,15 @@ static void noinstr exit_to_kernel_mode(struct pt_regs *regs,
  * Before this function is called it is not safe to call regular kernel code,
  * instrumentable code, or any code which may trigger an exception.
  */
-static __always_inline void __enter_from_user_mode(void)
+static __always_inline void __enter_from_user_mode(struct pt_regs *regs)
 {
-	lockdep_hardirqs_off(CALLER_ADDR0);
-	CT_WARN_ON(ct_state() != CT_STATE_USER);
-	user_exit_irqoff();
-	trace_hardirqs_off_finish();
+	enter_from_user_mode(regs);
 	mte_disable_tco_entry(current);
 }
 
-static __always_inline void enter_from_user_mode(struct pt_regs *regs)
+static __always_inline void arm64_enter_from_user_mode(struct pt_regs *regs)
 {
-	__enter_from_user_mode();
+	__enter_from_user_mode(regs);
 }
 
 /*
@@ -185,116 +96,19 @@ static __always_inline void enter_from_user_mode(struct pt_regs *regs)
  * After this function returns it is not safe to call regular kernel code,
  * instrumentable code, or any code which may trigger an exception.
  */
-static __always_inline void __exit_to_user_mode(void)
-{
-	trace_hardirqs_on_prepare();
-	lockdep_hardirqs_on_prepare();
-	user_enter_irqoff();
-	lockdep_hardirqs_on(CALLER_ADDR0);
-}
 
-static void do_notify_resume(struct pt_regs *regs, unsigned long thread_flags)
+static __always_inline void arm64_exit_to_user_mode(struct pt_regs *regs)
 {
-	do {
-		local_irq_enable();
-
-		if (thread_flags & (_TIF_NEED_RESCHED | _TIF_NEED_RESCHED_LAZY))
-			schedule();
-
-		if (thread_flags & _TIF_UPROBE)
-			uprobe_notify_resume(regs);
-
-		if (thread_flags & _TIF_MTE_ASYNC_FAULT) {
-			clear_thread_flag(TIF_MTE_ASYNC_FAULT);
-			send_sig_fault(SIGSEGV, SEGV_MTEAERR,
-				       (void __user *)NULL, current);
-		}
-
-		if (thread_flags & _TIF_PATCH_PENDING)
-			klp_update_patch_state(current);
-
-		if (thread_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL))
-			do_signal(regs);
-
-		if (thread_flags & _TIF_NOTIFY_RESUME)
-			resume_user_mode_work(regs);
-
-		if (thread_flags & _TIF_FOREIGN_FPSTATE)
-			fpsimd_restore_current_state();
-
-		local_irq_disable();
-		thread_flags = read_thread_flags();
-	} while (thread_flags & _TIF_WORK_MASK);
-}
-
-static __always_inline void exit_to_user_mode_prepare(struct pt_regs *regs)
-{
-	unsigned long flags;
-
 	local_irq_disable();
-
-	flags = read_thread_flags();
-	if (unlikely(flags & _TIF_WORK_MASK))
-		do_notify_resume(regs, flags);
-
-	local_daif_mask();
-
-	lockdep_sys_exit();
-}
-
-static __always_inline void exit_to_user_mode(struct pt_regs *regs)
-{
 	exit_to_user_mode_prepare(regs);
+	local_daif_mask();
 	mte_check_tfsr_exit();
-	__exit_to_user_mode();
+	exit_to_user_mode();
 }
 
 asmlinkage void noinstr asm_exit_to_user_mode(struct pt_regs *regs)
 {
-	exit_to_user_mode(regs);
-}
-
-/*
- * Handle IRQ/context state management when entering an NMI from user/kernel
- * mode. Before this function is called it is not safe to call regular kernel
- * code, instrumentable code, or any code which may trigger an exception.
- */
-static noinstr arm64_irqentry_state_t arm64_enter_nmi(struct pt_regs *regs)
-{
-	arm64_irqentry_state_t state;
-
-	state.lockdep = lockdep_hardirqs_enabled();
-
-	__nmi_enter();
-	lockdep_hardirqs_off(CALLER_ADDR0);
-	lockdep_hardirq_enter();
-	ct_nmi_enter();
-
-	trace_hardirqs_off_finish();
-	ftrace_nmi_enter();
-
-	return state;
-}
-
-/*
- * Handle IRQ/context state management when exiting an NMI from user/kernel
- * mode. After this function returns it is not safe to call regular kernel
- * code, instrumentable code, or any code which may trigger an exception.
- */
-static void noinstr arm64_exit_nmi(struct pt_regs *regs,
-				   arm64_irqentry_state_t state)
-{
-	ftrace_nmi_exit();
-	if (state.lockdep) {
-		trace_hardirqs_on_prepare();
-		lockdep_hardirqs_on_prepare();
-	}
-
-	ct_nmi_exit();
-	lockdep_hardirq_exit();
-	if (state.lockdep)
-		lockdep_hardirqs_on(CALLER_ADDR0);
-	__nmi_exit();
+	arm64_exit_to_user_mode(regs);
 }
 
 /*
@@ -302,9 +116,9 @@ static void noinstr arm64_exit_nmi(struct pt_regs *regs,
  * kernel mode. Before this function is called it is not safe to call regular
  * kernel code, instrumentable code, or any code which may trigger an exception.
  */
-static noinstr arm64_irqentry_state_t arm64_enter_el1_dbg(struct pt_regs *regs)
+static noinstr irqentry_state_t arm64_enter_el1_dbg(struct pt_regs *regs)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state.lockdep = lockdep_hardirqs_enabled();
 
@@ -322,7 +136,7 @@ static noinstr arm64_irqentry_state_t arm64_enter_el1_dbg(struct pt_regs *regs)
  * kernel code, instrumentable code, or any code which may trigger an exception.
  */
 static void noinstr arm64_exit_el1_dbg(struct pt_regs *regs,
-				       arm64_irqentry_state_t state)
+				       irqentry_state_t state)
 {
 	if (state.lockdep) {
 		trace_hardirqs_on_prepare();
@@ -353,7 +167,7 @@ extern void (*handle_arch_fiq)(struct pt_regs *);
 static void noinstr __panic_unhandled(struct pt_regs *regs, const char *vector,
 				      unsigned long esr)
 {
-	arm64_enter_nmi(regs);
+	irqentry_nmi_enter(regs);
 
 	console_verbose();
 
@@ -504,7 +318,7 @@ UNHANDLED(el1t, 64, error)
 static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
 {
 	unsigned long far = read_sysreg(far_el1);
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
@@ -516,7 +330,7 @@ static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr)
 static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr)
 {
 	unsigned long far = read_sysreg(far_el1);
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
@@ -527,7 +341,7 @@ static void noinstr el1_pc(struct pt_regs *regs, unsigned long esr)
 
 static void noinstr el1_undef(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
@@ -538,7 +352,7 @@ static void noinstr el1_undef(struct pt_regs *regs, unsigned long esr)
 
 static void noinstr el1_bti(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
@@ -549,7 +363,7 @@ static void noinstr el1_bti(struct pt_regs *regs, unsigned long esr)
 
 static void noinstr el1_gcs(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
@@ -560,7 +374,7 @@ static void noinstr el1_gcs(struct pt_regs *regs, unsigned long esr)
 
 static void noinstr el1_mops(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
@@ -571,7 +385,7 @@ static void noinstr el1_mops(struct pt_regs *regs, unsigned long esr)
 
 static void noinstr el1_breakpt(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = arm64_enter_el1_dbg(regs);
 	debug_exception_enter(regs);
@@ -582,7 +396,7 @@ static void noinstr el1_breakpt(struct pt_regs *regs, unsigned long esr)
 
 static void noinstr el1_softstp(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = arm64_enter_el1_dbg(regs);
 	if (!cortex_a76_erratum_1463225_debug_handler(regs)) {
@@ -604,7 +418,7 @@ static void noinstr el1_watchpt(struct pt_regs *regs, unsigned long esr)
 {
 	/* Watchpoints are the only debug exception to write FAR_EL1 */
 	unsigned long far = read_sysreg(far_el1);
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = arm64_enter_el1_dbg(regs);
 	debug_exception_enter(regs);
@@ -615,7 +429,7 @@ static void noinstr el1_watchpt(struct pt_regs *regs, unsigned long esr)
 
 static void noinstr el1_brk64(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = arm64_enter_el1_dbg(regs);
 	debug_exception_enter(regs);
@@ -626,7 +440,7 @@ static void noinstr el1_brk64(struct pt_regs *regs, unsigned long esr)
 
 static void noinstr el1_fpac(struct pt_regs *regs, unsigned long esr)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = enter_from_kernel_mode(regs);
 	local_daif_inherit(regs);
@@ -687,17 +501,17 @@ asmlinkage void noinstr el1h_64_sync_handler(struct pt_regs *regs)
 static __always_inline void __el1_pnmi(struct pt_regs *regs,
 				       void (*handler)(struct pt_regs *))
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
-	state = arm64_enter_nmi(regs);
+	state = irqentry_nmi_enter(regs);
 	do_interrupt_handler(regs, handler);
-	arm64_exit_nmi(regs, state);
+	irqentry_nmi_exit(regs, state);
 }
 
 static __always_inline void __el1_irq(struct pt_regs *regs,
 				      void (*handler)(struct pt_regs *))
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	state = enter_from_kernel_mode(regs);
 
@@ -731,22 +545,22 @@ asmlinkage void noinstr el1h_64_fiq_handler(struct pt_regs *regs)
 asmlinkage void noinstr el1h_64_error_handler(struct pt_regs *regs)
 {
 	unsigned long esr = read_sysreg(esr_el1);
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
 	local_daif_restore(DAIF_ERRCTX);
-	state = arm64_enter_nmi(regs);
+	state = irqentry_nmi_enter(regs);
 	do_serror(regs, esr);
-	arm64_exit_nmi(regs, state);
+	irqentry_nmi_exit(regs, state);
 }
 
 static void noinstr el0_da(struct pt_regs *regs, unsigned long esr)
 {
 	unsigned long far = read_sysreg(far_el1);
 
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_mem_abort(far, esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_ia(struct pt_regs *regs, unsigned long esr)
@@ -761,50 +575,50 @@ static void noinstr el0_ia(struct pt_regs *regs, unsigned long esr)
 	if (!is_ttbr0_addr(far))
 		arm64_apply_bp_hardening();
 
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_mem_abort(far, esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_fpsimd_acc(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_fpsimd_acc(esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_sve_acc(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_sve_acc(esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_sme_acc(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_sme_acc(esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_fpsimd_exc(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_fpsimd_exc(esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_sys(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_sys(esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_pc(struct pt_regs *regs, unsigned long esr)
@@ -814,58 +628,58 @@ static void noinstr el0_pc(struct pt_regs *regs, unsigned long esr)
 	if (!is_ttbr0_addr(instruction_pointer(regs)))
 		arm64_apply_bp_hardening();
 
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_sp_pc_abort(far, esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_sp(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_sp_pc_abort(regs->sp, esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_undef(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_undef(regs, esr);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_bti(struct pt_regs *regs)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_bti(regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_mops(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_mops(regs, esr);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_gcs(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_gcs(regs, esr);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_inv(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	bad_el0_sync(regs, 0, esr);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_breakpt(struct pt_regs *regs, unsigned long esr)
@@ -873,12 +687,12 @@ static void noinstr el0_breakpt(struct pt_regs *regs, unsigned long esr)
 	if (!is_ttbr0_addr(regs->pc))
 		arm64_apply_bp_hardening();
 
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	debug_exception_enter(regs);
 	do_breakpoint(esr, regs);
 	debug_exception_exit(regs);
 	local_daif_restore(DAIF_PROCCTX);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_softstp(struct pt_regs *regs, unsigned long esr)
@@ -886,7 +700,7 @@ static void noinstr el0_softstp(struct pt_regs *regs, unsigned long esr)
 	if (!is_ttbr0_addr(regs->pc))
 		arm64_apply_bp_hardening();
 
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	/*
 	 * After handling a breakpoint, we suspend the breakpoint
 	 * and use single-step to move to the next instruction.
@@ -897,7 +711,7 @@ static void noinstr el0_softstp(struct pt_regs *regs, unsigned long esr)
 		local_daif_restore(DAIF_PROCCTX);
 		do_el0_softstep(esr, regs);
 	}
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_watchpt(struct pt_regs *regs, unsigned long esr)
@@ -905,39 +719,39 @@ static void noinstr el0_watchpt(struct pt_regs *regs, unsigned long esr)
 	/* Watchpoints are the only debug exception to write FAR_EL1 */
 	unsigned long far = read_sysreg(far_el1);
 
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	debug_exception_enter(regs);
 	do_watchpoint(far, esr, regs);
 	debug_exception_exit(regs);
 	local_daif_restore(DAIF_PROCCTX);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_brk64(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_brk64(esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_svc(struct pt_regs *regs)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	cortex_a76_erratum_1463225_svc_handler();
 	fpsimd_syscall_enter();
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_svc(regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 	fpsimd_syscall_exit();
 }
 
 static void noinstr el0_fpac(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_fpac(regs, esr);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs)
@@ -1011,7 +825,7 @@ asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs)
 static void noinstr el0_interrupt(struct pt_regs *regs,
 				  void (*handler)(struct pt_regs *))
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 
 	write_sysreg(DAIF_PROCCTX_NOIRQ, daif);
 
@@ -1022,7 +836,7 @@ static void noinstr el0_interrupt(struct pt_regs *regs,
 	do_interrupt_handler(regs, handler);
 	irq_exit_rcu();
 
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr __el0_irq_handler_common(struct pt_regs *regs)
@@ -1048,15 +862,15 @@ asmlinkage void noinstr el0t_64_fiq_handler(struct pt_regs *regs)
 static void noinstr __el0_error_handler_common(struct pt_regs *regs)
 {
 	unsigned long esr = read_sysreg(esr_el1);
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_ERRCTX);
-	state = arm64_enter_nmi(regs);
+	state = irqentry_nmi_enter(regs);
 	do_serror(regs, esr);
-	arm64_exit_nmi(regs, state);
+	irqentry_nmi_exit(regs, state);
 	local_daif_restore(DAIF_PROCCTX);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 asmlinkage void noinstr el0t_64_error_handler(struct pt_regs *regs)
@@ -1067,27 +881,27 @@ asmlinkage void noinstr el0t_64_error_handler(struct pt_regs *regs)
 #ifdef CONFIG_COMPAT
 static void noinstr el0_cp15(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_cp15(esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_svc_compat(struct pt_regs *regs)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	cortex_a76_erratum_1463225_svc_handler();
 	local_daif_restore(DAIF_PROCCTX);
 	do_el0_svc_compat(regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 static void noinstr el0_bkpt32(struct pt_regs *regs, unsigned long esr)
 {
-	enter_from_user_mode(regs);
+	arm64_enter_from_user_mode(regs);
 	local_daif_restore(DAIF_PROCCTX);
 	do_bkpt32(esr, regs);
-	exit_to_user_mode(regs);
+	arm64_exit_to_user_mode(regs);
 }
 
 asmlinkage void noinstr el0t_32_sync_handler(struct pt_regs *regs)
@@ -1166,7 +980,7 @@ asmlinkage void noinstr __noreturn handle_bad_stack(struct pt_regs *regs)
 	unsigned long esr = read_sysreg(esr_el1);
 	unsigned long far = read_sysreg(far_el1);
 
-	arm64_enter_nmi(regs);
+	irqentry_nmi_enter(regs);
 	panic_bad_stack(regs, esr, far);
 }
 
@@ -1174,7 +988,7 @@ asmlinkage void noinstr __noreturn handle_bad_stack(struct pt_regs *regs)
 asmlinkage noinstr unsigned long
 __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
 {
-	arm64_irqentry_state_t state;
+	irqentry_state_t state;
 	unsigned long ret;
 
 	/*
@@ -1199,9 +1013,9 @@ __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg)
 	else if (cpu_has_pan())
 		set_pstate_pan(0);
 
-	state = arm64_enter_nmi(regs);
+	state = irqentry_nmi_enter(regs);
 	ret = do_sdei_event(regs, arg);
-	arm64_exit_nmi(regs, state);
+	irqentry_nmi_exit(regs, state);
 
 	return ret;
 }
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index db3f972f8cd9..1110eeb21f57 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1576,7 +1577,7 @@ static void handle_signal(struct ksignal *ksig, struct pt_regs *regs)
  * the kernel can handle, and then we build all the user-level signal handling
  * stack-frames in one go after that.
  */
-void do_signal(struct pt_regs *regs)
+void arch_do_signal_or_restart(struct pt_regs *regs)
 {
 	unsigned long continue_addr = 0, restart_addr = 0;
 	int retval = 0;
-- 
2.34.1



From xen-devel-bounces@lists.xenproject.org Fri Aug 15 03:07:09 2025
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CC: 
Subject: [PATCH v8 0/8] arm64: entry: Convert to generic irq entry
Date: Fri, 15 Aug 2025 11:06:25 +0800
Message-ID: <20250815030633.448613-1-ruanjinjie@huawei.com>
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 dggpemf500011.china.huawei.com (7.185.36.131)

Currently, x86, Riscv, Loongarch use the generic entry which makes
maintainers' work easier and codes more elegant. So also convert arm64
to use the generic entry infrastructure from kernel/entry/* by
switching it to generic IRQ entry first, which will make PREEMPT_DYNAMIC
and PREEMPT_LAZY use the generic entry common code and remove a lot of
duplicate code.

Since commit a70e9f647f50 ("entry: Split generic entry into generic
exception and syscall entry") split the generic entry into generic irq
entry and generic syscall entry, it is time to convert arm64 to use
the generic irq entry. And ARM64 will be completely converted to generic
entry in the upcoming patch series.

The main convert steps are as follows:
- Split generic entry into generic irq entry and generic syscall to
  make the single patch more concentrated in switching to one thing.
- Make arm64 easier to use irqentry_enter/exit().
- Make arm64 closer to the PREEMPT_DYNAMIC code of generic entry.
- Switch to generic irq entry.

This patch set is rebased on v6.17-rc1.

It was tested ok with following test cases on QEMU virt platform:
 - Perf tests.
 - Different `dynamic preempt` mode switch.
 - Pseudo NMI tests.
 - Stress-ng CPU stress test.
 - MTE test case in Documentation/arch/arm64/memory-tagging-extension.rst
   and all test cases in tools/testing/selftests/arm64/mte/*.

The test QEMU configuration is as follows:

	qemu-system-aarch64 \
		-M virt,gic-version=3,virtualization=on,mte=on \
		-cpu max,pauth-impdef=on \
		-kernel Image \
		-smp 8,sockets=1,cores=4,threads=2 \
		-m 512m \
		-nographic \
		-no-reboot \
		-device virtio-rng-pci \
		-append "root=/dev/vda rw console=ttyAMA0 kgdboc=ttyAMA0,115200 \
			earlycon preempt=voluntary irqchip.gicv3_pseudo_nmi=1" \
		-drive if=none,file=images/rootfs.ext4,format=raw,id=hd0 \
		-device virtio-blk-device,drive=hd0 \

Changes in v8:
- Update the comment.
- Fix a typo, inerrupts_enabled(regs) -> interrupts_enabled(regs).
- Consistently defined 'state' on a separate line, before the main block.
- Split the "arch_irqentry_exit_need_resched()" patch.
- Fix CONFIG_PREEMPTION not set build issue.
- Remove do_signal() declaration in exception.h as there remains
  no users of `do_signal().
- Add asm/cpufeature.h header for entry-common.h
- Add Reviewed-by, Acked-by and Tested-by.
- Update the commit message.
- Link to v7: https://lore.kernel.org/all/20250729015456.3411143-1-ruanjinjie@huawei.com/

Changes in v7:
- Rebased on v6.16-rc7 and remove the merged first patch.
- Update the commit message.
- Link to v6: https://lore.kernel.org/all/20250213130007.1418890-1-ruanjinjie@huawei.com/

Changes in v6:
- Rebased on 6.14 rc2 next.
- Put the syscall bits aside and split it out.
- Have the split patch before the arm64 changes.
- Merge some tightly coupled patches.
- Adjust the order of some patches to make them more reasonable.
- Define regs_irqs_disabled() by inline function.
- Define interrupts_enabled() in terms of regs_irqs_disabled().
- Delete the fast_interrupts_enabled() macro.
- irqentry_state_t -> arm64_irqentry_state_t.
- Remove arch_exit_to_user_mode_prepare() and pull local_daif_mask() later
  in the arm64 exit sequence
- Update the commit message.
- Link to v5: https://lkml.org/lkml/2024/12/6/609

Changes in v5:
- Not change arm32 and keep inerrupts_enabled() macro for gicv3 driver.
- Move irqentry_state definition into arch/arm64/kernel/entry-common.c.
- Avoid removing the __enter_from_*() and __exit_to_*() wrappers.
- Update "irqentry_state_t ret/irq_state" to "state"
  to keep it consistently.
- Use generic irq entry header for PREEMPT_DYNAMIC after split
  the generic entry.
- Also refactor the ARM64 syscall code.
- Introduce arch_ptrace_report_syscall_entry/exit(), instead of
  arch_pre/post_report_syscall_entry/exit() to simplify code.
- Make the syscall patches clear separation.
- Update the commit message.
- Link to v4: https://lkml.indiana.edu/2410.3/02309.html

Changes in v4:
- Rework/cleanup split into a few patches as Mark suggested.
- Replace interrupts_enabled() macro with regs_irqs_disabled(), instead
  of left it here.
- Remove rcu and lockdep state in pt_regs by using temporary
  irqentry_state_t as Mark suggested.
- Remove some unnecessary intermediate functions to make it clear.
- Rework preempt irq and PREEMPT_DYNAMIC code
  to make the switch more clear.
- arch_prepare_*_entry/exit() -> arch_pre_*_entry/exit().
- Expand the arch functions comment.
- Make arch functions closer to its caller.
- Declare saved_reg in for block.
- Remove arch_exit_to_kernel_mode_prepare(), arch_enter_from_kernel_mode().
- Adjust "Add few arch functions to use generic entry" patch to be
  the penultimate.
- Update the commit message.
- Add suggested-by.

Changes in v3:
- Test the MTE test cases.
- Handle forget_syscall() in arch_post_report_syscall_entry()
- Make the arch funcs not use __weak as Thomas suggested, so move
  the arch funcs to entry-common.h, and make arch_forget_syscall() folded
  in arch_post_report_syscall_entry() as suggested.
- Move report_single_step() to thread_info.h for arm64
- Change __always_inline() to inline, add inline for the other arch funcs.
- Remove unused signal.h for entry-common.h.
- Add Suggested-by.
- Update the commit message.

Changes in v2:
- Add tested-by.
- Fix a bug that not call arch_post_report_syscall_entry() in
  syscall_trace_enter() if ptrace_report_syscall_entry() return not zero.
- Refactor report_syscall().
- Add comment for arch_prepare_report_syscall_exit().
- Adjust entry-common.h header file inclusion to alphabetical order.
- Update the commit message.

Jinjie Ruan (8):
  arm64: ptrace: Replace interrupts_enabled() with regs_irqs_disabled()
  arm64: entry: Refactor the entry and exit for exceptions from EL1
  arm64: entry: Rework arm64_preempt_schedule_irq()
  arm64: entry: Use preempt_count() and need_resched() helper
  entry: Add arch_irqentry_exit_need_resched() for arm64
  arm64: entry: Refactor preempt_schedule_irq() check code
  arm64: entry: Move arm64_preempt_schedule_irq() into
    __exit_to_kernel_mode()
  arm64: entry: Switch to generic IRQ entry

 arch/arm64/Kconfig                    |   1 +
 arch/arm64/include/asm/daifflags.h    |   2 +-
 arch/arm64/include/asm/entry-common.h |  57 ++++
 arch/arm64/include/asm/exception.h    |   1 -
 arch/arm64/include/asm/preempt.h      |   2 -
 arch/arm64/include/asm/ptrace.h       |  13 +-
 arch/arm64/include/asm/xen/events.h   |   2 +-
 arch/arm64/kernel/acpi.c              |   2 +-
 arch/arm64/kernel/debug-monitors.c    |   2 +-
 arch/arm64/kernel/entry-common.c      | 423 +++++++++-----------------
 arch/arm64/kernel/sdei.c              |   2 +-
 arch/arm64/kernel/signal.c            |   3 +-
 kernel/entry/common.c                 |  16 +-
 13 files changed, 230 insertions(+), 296 deletions(-)
 create mode 100644 arch/arm64/include/asm/entry-common.h

-- 
2.34.1



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CC: 
Subject: [PATCH v8 5/8] entry: Add arch_irqentry_exit_need_resched() for arm64
Date: Fri, 15 Aug 2025 11:06:30 +0800
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Compared to the generic entry code, ARM64 does additional checks
when deciding to reschedule on return from interrupt. So introduce
arch_irqentry_exit_need_resched() in the need_resched()
condition of the generic raw_irqentry_exit_cond_resched(), with
a NOP default. This will allow ARM64 to implement the architecture
specific version for switching over to the generic entry code.

Suggested-by: Ada Couprie Diaz 
Suggested-by: Mark Rutland 
Suggested-by: Kevin Brodsky 
Suggested-by: Thomas Gleixner 
Signed-off-by: Jinjie Ruan 
---
 kernel/entry/common.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/kernel/entry/common.c b/kernel/entry/common.c
index 408d28b5179d..f62e1d1b2063 100644
--- a/kernel/entry/common.c
+++ b/kernel/entry/common.c
@@ -143,6 +143,20 @@ noinstr irqentry_state_t irqentry_enter(struct pt_regs *regs)
 	return ret;
 }
 
+/**
+ * arch_irqentry_exit_need_resched - Architecture specific need resched function
+ *
+ * Invoked from raw_irqentry_exit_cond_resched() to check if resched is needed.
+ * Defaults return true.
+ *
+ * The main purpose is to permit arch to avoid preemption of a task from an IRQ.
+ */
+static inline bool arch_irqentry_exit_need_resched(void);
+
+#ifndef arch_irqentry_exit_need_resched
+static inline bool arch_irqentry_exit_need_resched(void) { return true; }
+#endif
+
 void raw_irqentry_exit_cond_resched(void)
 {
 	if (!preempt_count()) {
@@ -150,7 +164,7 @@ void raw_irqentry_exit_cond_resched(void)
 		rcu_irq_exit_check_preempt();
 		if (IS_ENABLED(CONFIG_DEBUG_ENTRY))
 			WARN_ON_ONCE(!on_thread_stack());
-		if (need_resched())
+		if (need_resched() && arch_irqentry_exit_need_resched())
 			preempt_schedule_irq();
 	}
 }
-- 
2.34.1



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Date: Fri, 15 Aug 2025 08:10:43 +0300
From: "Leon Romanovsky" 
To: "Christophe Leroy" ,
 "Marek Szyprowski" 
Cc: "Jason Gunthorpe" ,
 "Abdiel Janulgue" ,
 "Alexander Potapenko" ,
 "Alex Gaynor" ,
 "Andrew Morton" ,
 "Christoph Hellwig" , "Danilo Krummrich" ,
 iommu@lists.linux.dev, "Jason Wang" ,
 "Jens Axboe" , "Joerg Roedel" ,
 "Jonathan Corbet" , "Juergen Gross" ,
 kasan-dev@googlegroups.com, "Keith Busch" ,
 linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-mm@kvack.org,
 linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
 linux-trace-kernel@vger.kernel.org,
 "Madhavan Srinivasan" ,
 "Masami Hiramatsu" ,
 "Michael Ellerman" ,
 "Michael S. Tsirkin" , "Miguel Ojeda" ,
 "Robin Murphy" , rust-for-linux@vger.kernel.org,
 "Sagi Grimberg" ,
 "Stefano Stabellini" ,
 "Steven Rostedt" , virtualization@lists.linux.dev,
 "Will Deacon" , xen-devel@lists.xenproject.org
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In-Reply-To: 
References: 
 
Subject: Re: [PATCH v3 00/16] dma-mapping: migrate to physical address-based API
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On Thu, Aug 14, 2025, at 22:05, Christophe Leroy wrote:
> Le 14/08/2025 =C3=A0 19:53, Leon Romanovsky a =C3=A9crit=C2=A0:
>> Changelog:
>> v3:
>>   * Fixed typo in "cacheable" word
>>   * Simplified kmsan patch a lot to be simple argument refactoring
>
> v2 sent today at 12:13, v3 sent today at 19:53 .... for only that ?
>
> Have you read=20
> https://docs.kernel.org//process/submitting-patches.html#don-t-get-dis=
couraged-or-impatient=20
> ?

Yes, I'm aware of that section. It is not even remotely close to the rea=
lity in different subsystems.

There are some places in the kernel where you never get any responses.

Thanks


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Message-ID: <3823aae9-34cd-430f-8cf5-873d354c52ac@suse.com>
Date: Fri, 15 Aug 2025 07:12:36 +0200
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Subject: Re: [PATCH] xen/events: Fix Global and Domain VIRQ tracking
To: Jason Andryuk ,
 Stefano Stabellini ,
 Oleksandr Tyshchenko ,
 Chris Wright ,
 Jeremy Fitzhardinge 
Cc: stable@vger.kernel.org, xen-devel@lists.xenproject.org,
 linux-kernel@vger.kernel.org
References: <20250812190041.23276-1-jason.andryuk@amd.com>
 
 <6bf9bac0-a394-4064-bb5d-924f5a920e7e@suse.com>
 <238b2fd0-33ab-4279-9205-de58332fa944@amd.com>
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From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= 
To: Jason Andryuk ,
 Stefano Stabellini ,
 Oleksandr Tyshchenko ,
 Chris Wright ,
 Jeremy Fitzhardinge 
Cc: stable@vger.kernel.org, xen-devel@lists.xenproject.org,
 linux-kernel@vger.kernel.org
Message-ID: <3823aae9-34cd-430f-8cf5-873d354c52ac@suse.com>
Subject: Re: [PATCH] xen/events: Fix Global and Domain VIRQ tracking
References: <20250812190041.23276-1-jason.andryuk@amd.com>
 
 <6bf9bac0-a394-4064-bb5d-924f5a920e7e@suse.com>
 <238b2fd0-33ab-4279-9205-de58332fa944@amd.com>
In-Reply-To: <238b2fd0-33ab-4279-9205-de58332fa944@amd.com>

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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini 
Subject: [PATCH] docs/misra: fix sphinx-build issues
Thread-Topic: [PATCH] docs/misra: fix sphinx-build issues
Thread-Index: AQHcDbJCdYlsiZdfl0mX5ViIXi0+6A==
Date: Fri, 15 Aug 2025 07:00:18 +0000
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Fix the following issues:
1. xen/docs/misra/deviations.rst:90: WARNING: Inline interpreted text or
phrase reference start-string without end-string. [docutils]
2. xen/docs/misra/deviations.rst:54: ERROR: Error parsing content block
for the "list-table" directive: uniform two-level bullet list expected,
but row 6 does not contain the same number of items as row 1 (2 vs 3).
* - R2.1
  - Calls to the `__builtin_unreachable()` function inside the expansion of
    the `ASSERT_UNREACHABLE()` macro may cause a function to be marked as
    non-returning. This behavior occurs only in configurations where
    assertions are enabled. To address this, the `noreturn` property for
    `__builtin_unreachable()` is overridden in these contexts, resulting in
    the absence of reports that do not have an impact on safety, despite
    being true positives.
    Xen expects developers to ensure code remains safe and reliable in buil=
ds,
    even when debug-only assertions like `ASSERT_UNREACHABLE() are removed.
3. xen/docs/misra/rules.rst:127: WARNING: Inline interpreted text or phrase
reference start-string without end-string. [docutils]

Signed-off-by: Dmytro Prokopchuk 
---
 docs/misra/deviations.rst | 3 ++-
 docs/misra/rules.rst      | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 3c46a1e47a..2be49076e1 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -95,7 +95,8 @@ Deviations related to MISRA C:2012 Rules:
        the absence of reports that do not have an impact on safety, despit=
e
        being true positives.
        Xen expects developers to ensure code remains safe and reliable in =
builds,
-       even when debug-only assertions like `ASSERT_UNREACHABLE() are remo=
ved.
+       even when debug-only assertions like `ASSERT_UNREACHABLE()` are rem=
oved.
+     - ECLAIR has been configured to ignore those statements.
=20
    * - R2.2
      - Proving compliance with respect to Rule 2.2 is generally impossible=
:
diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
index 6812eb7e8a..382331447e 100644
--- a/docs/misra/rules.rst
+++ b/docs/misra/rules.rst
@@ -124,7 +124,7 @@ maintainers if you want to suggest a change.
            they are used to generate definitions for asm modules
          - Declarations without initializer are safe, as they are not
            executed
-         - Functions that are no-return due to calls to the `ASSERT_UNREAC=
HABLE()'
+         - Functions that are no-return due to calls to the 'ASSERT_UNREAC=
HABLE()'
            macro in debug build configurations are not considered violatio=
ns::
=20
               static inline bool
--=20
2.43.0


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MIME-Version: 1.0
Date: Fri, 15 Aug 2025 09:09:47 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Jan Beulich , Julien
 Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini 
Subject: Re: [PATCH] docs/misra: fix sphinx-build issues
In-Reply-To: 
References: 
Message-ID: 
X-Sender: nicola.vetrini@bugseng.com
Organization: BUGSENG s.r.l.
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 format=flowed
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On 2025-08-15 09:00, Dmytro Prokopchuk1 wrote:
> Fix the following issues:
> 1. xen/docs/misra/deviations.rst:90: WARNING: Inline interpreted text 
> or
> phrase reference start-string without end-string. [docutils]
> 2. xen/docs/misra/deviations.rst:54: ERROR: Error parsing content block
> for the "list-table" directive: uniform two-level bullet list expected,
> but row 6 does not contain the same number of items as row 1 (2 vs 3).
> * - R2.1
>   - Calls to the `__builtin_unreachable()` function inside the 
> expansion of
>     the `ASSERT_UNREACHABLE()` macro may cause a function to be marked 
> as
>     non-returning. This behavior occurs only in configurations where
>     assertions are enabled. To address this, the `noreturn` property 
> for
>     `__builtin_unreachable()` is overridden in these contexts, 
> resulting in
>     the absence of reports that do not have an impact on safety, 
> despite
>     being true positives.
>     Xen expects developers to ensure code remains safe and reliable in 
> builds,
>     even when debug-only assertions like `ASSERT_UNREACHABLE() are 
> removed.
> 3. xen/docs/misra/rules.rst:127: WARNING: Inline interpreted text or 
> phrase
> reference start-string without end-string. [docutils]
> 
> Signed-off-by: Dmytro Prokopchuk 

Reviewed-by: Nicola Vetrini 

I recall that Andrew wanted to add a doc build test to avoid introducing 
warnings. On that front, with my Sphinx version I also see this build 
warning:

Running Sphinx v8.1.3
WARNING: Calling get_html_theme_path is deprecated. If you are calling 
it to define html_theme_path, you are safe to remove that code.

> ---
>  docs/misra/deviations.rst | 3 ++-
>  docs/misra/rules.rst      | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
> index 3c46a1e47a..2be49076e1 100644
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -95,7 +95,8 @@ Deviations related to MISRA C:2012 Rules:
>         the absence of reports that do not have an impact on safety, 
> despite
>         being true positives.
>         Xen expects developers to ensure code remains safe and reliable 
> in builds,
> -       even when debug-only assertions like `ASSERT_UNREACHABLE() are 
> removed.
> +       even when debug-only assertions like `ASSERT_UNREACHABLE()` are 
> removed.
> +     - ECLAIR has been configured to ignore those statements.
> 
>     * - R2.2
>       - Proving compliance with respect to Rule 2.2 is generally 
> impossible:
> diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
> index 6812eb7e8a..382331447e 100644
> --- a/docs/misra/rules.rst
> +++ b/docs/misra/rules.rst
> @@ -124,7 +124,7 @@ maintainers if you want to suggest a change.
>             they are used to generate definitions for asm modules
>           - Declarations without initializer are safe, as they are not
>             executed
> -         - Functions that are no-return due to calls to the 
> `ASSERT_UNREACHABLE()'
> +         - Functions that are no-return due to calls to the 
> 'ASSERT_UNREACHABLE()'
>             macro in debug build configurations are not considered 
> violations::
> 
>                static inline bool

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Fri, 15 Aug 2025 09:20:46 +0200
From: Nicola Vetrini 
To: Andrew Cooper 
Cc: Xen-devel , Anthony PERARD
 , Michal Orzel , Jan
 Beulich , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini
 , Roberto Bagnara ,
 "consulting @ bugseng . com" 
Subject: Re: [PATCH v2] xen: Use auto as per C23
In-Reply-To: <20250814222524.2638883-1-andrew.cooper3@citrix.com>
References: <20250814222524.2638883-1-andrew.cooper3@citrix.com>
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On 2025-08-15 00:25, Andrew Cooper wrote:
> In macros it is common to declare local variables using typeof(param) 
> in order
> to ensure that side effects are only evaluated once.  A consequence of 
> this is
> double textural expansion of the parameter, which can get out of hand 
> very
> quickly with nested macros.
> 
> In C23, the auto keyword has been repurposed to perform type inference.
> 
> A GCC extension, __auto_type, is now avaialble in the new toolchain 
> baseline
> and avoids the double textural expansion.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Nicola Vetrini 

with a nit below:

> ---
> CC: Anthony PERARD 
> CC: Michal Orzel 
> CC: Jan Beulich 
> CC: Julien Grall 
> CC: Roger Pau Monné 
> CC: Stefano Stabellini 
> CC: Roberto Bagnara 
> CC: Nicola Vetrini 
> CC: consulting@bugseng.com 
> 
> The resulting build is identical.
> 
> v2:
>  * Use auto directly
>  * Eclair configuration
> 
> https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1985289434
> ---
>  automation/eclair_analysis/ECLAIR/toolchain.ecl | 11 +++++++++--
>  docs/misra/C-language-toolchain.rst             |  2 ++
>  xen/include/xen/compiler.h                      | 14 ++++++++++++++
>  xen/include/xen/macros.h                        | 14 +++++++-------
>  4 files changed, 32 insertions(+), 9 deletions(-)
> 
> diff --git a/automation/eclair_analysis/ECLAIR/toolchain.ecl 
> b/automation/eclair_analysis/ECLAIR/toolchain.ecl
> index 842f8377e561..125f99a06583 100644
> --- a/automation/eclair_analysis/ECLAIR/toolchain.ecl
> +++ b/automation/eclair_analysis/ECLAIR/toolchain.ecl
> @@ -15,6 +15,7 @@
>      __alignof__, __alignof: see Sections \"6.48 Alternate Keywords\" 
> and \"6.44 Determining the Alignment of Functions, Types or Variables\" 
> of "GCC_MANUAL".
>      asm, __asm__: see Sections \"6.48 Alternate Keywords\" and \"6.47 
> How to Use Inline Assembly Language in C Code\" of "GCC_MANUAL".
>      __attribute__: see Section \"6.39 Attribute Syntax\" of 
> "GCC_MANUAL".
> +    __auto_type: see Section \"6.7 Referring to a Type with typeof\" 
> of "GCC_MANUAL".
>      __builtin_offsetof: see Section \"6.53 Support for offsetof\" of 
> "GCC_MANUAL".
>      __builtin_types_compatible_p: see Section \"6.59 Other Built-in 
> Functions Provided by GCC\" of "GCC_MANUAL".
>      __builtin_va_arg: non-documented GCC extension.
> @@ -26,6 +27,7 @@
>  -name_selector+={alignof, "^(__alignof__|__alignof)$"}
>  -name_selector+={asm, "^(__asm__|asm)$"}
>  -name_selector+={attribute, "^__attribute__$"}
> +-name_selector+={auto_type, "^__auto_type$"}
>  -name_selector+={builtin_offsetof, "^__builtin_offsetof$"}
>  -name_selector+={builtin_types_p, "^__builtin_types_compatible_p$"}
>  -name_selector+={builtin_va_arg, "^__builtin_va_arg$"}
> @@ -39,6 +41,7 @@
>  "alignof||
>  asm||
>  attribute||
> +auto_type||
>  builtin_offsetof||
>  builtin_types_p||
>  builtin_va_arg||
> @@ -114,6 +117,7 @@ volatile"
>  -doc_end
> 
>  -doc_begin="
> +    ext_auto_type: see Section \"6.7 Referring to a Type with typeof\" 
> of "GCC_MANUAL".
>      ext_c_missing_varargs_arg: see Section \"6.21 Macros with a 
> Variable Number of Arguments\" of "GCC_MANUAL".
>      ext_enum_value_not_int: non-documented GCC extension.
>      ext_flexible_array_in_array: see Section \"6.18 Arrays of Length 
> Zero\" of "GCC_MANUAL".
> @@ -126,6 +130,7 @@ volatile"
>      ext_return_has_void_expr: see the documentation for -Wreturn-type 
> in Section \"3.8 Options to Request or Suppress Warnings\" of 
> "GCC_MANUAL".
>      ext_sizeof_alignof_void_type: see Section \"6.24 Arithmetic on 
> void- and Function-Pointers\" of "GCC_MANUAL".
>  "
> +-name_selector+={ext_auto_type, "^ext_auto_type$"}
>  -name_selector+={ext_c_missing_varargs_arg, 
> "^ext_c_missing_varargs_arg$"}
>  -name_selector+={ext_enum_value_not_int, "^ext_enum_value_not_int$"}
>  -name_selector+={ext_flexible_array_in_array, 
> "^ext_flexible_array_in_array$"}
> @@ -139,7 +144,8 @@ volatile"
>  -name_selector+={ext_sizeof_alignof_void_type, 
> "^ext_sizeof_alignof_void_type$"}
> 
>  -config=STD.diag,behavior+={c99,GCC_ARM64,
> -"ext_c_missing_varargs_arg||
> +"ext_auto_type||
> +ext_c_missing_varargs_arg||
>  ext_forward_ref_enum_def||
>  ext_gnu_array_range||
>  ext_gnu_statement_expr_macro||
> @@ -149,7 +155,8 @@ ext_return_has_void_expr||
>  ext_sizeof_alignof_void_type"
>  }
>  -config=STD.diag,behavior+={c99,GCC_X86_64,
> -"ext_c_missing_varargs_arg||
> +"ext_auto_type||
> +ext_c_missing_varargs_arg||
>  ext_enum_value_not_int||
>  ext_flexible_array_in_array||
>  ext_flexible_array_in_struct||
> diff --git a/docs/misra/C-language-toolchain.rst 
> b/docs/misra/C-language-toolchain.rst
> index cb81f5c09872..635936004554 100644
> --- a/docs/misra/C-language-toolchain.rst
> +++ b/docs/misra/C-language-toolchain.rst
> @@ -94,6 +94,8 @@ The table columns are as follows:
>            see Sections "6.48 Alternate Keywords" and "6.44 Determining 
> the Alignment of Functions, Types or Variables" of GCC_MANUAL.
>         __attribute__:
>            see Section "6.39 Attribute Syntax" of GCC_MANUAL.
> +       __auto_type:
> +          see Section "6.7 Referring to a Type with typeof" of 
> GCC_MANUAL.
>         __builtin_types_compatible_p:
>            see Section "6.59 Other Built-in Functions Provided by GCC" 
> of GCC_MANUAL.
>         __builtin_va_arg:
> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
> index 88bf26bc5109..38ef5d82ad95 100644
> --- a/xen/include/xen/compiler.h
> +++ b/xen/include/xen/compiler.h
> @@ -64,6 +64,20 @@
>  # define asm_inline asm
>  #endif
> 
> +/*
> + * In C23, the auto keyword has been repurposed to perform type 
> inference.
> + *
> + * This behaviour is available via the __auto_type extension in 
> supported
> + * toolchains.
> + *
> + * 
> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
> + */
> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23 meaning. 
> */
> +#define auto __auto_type
> +#endif
> +

A more detailed explanation should live in deviations.rst under this 
bullet point

    * - R20.4
      - The override of the keyword \"inline\" in xen/compiler.h is 
present so
        that section contents checks pass when the compiler chooses not 
to
        inline a particular function.
      - Comment-based deviation.

as described in the SAF entry:

         {
             "id": "SAF-3-safe",
             "analyser": {
                 "eclair": "MC3A2.R20.4"
             },
             "name": "MC3A2.R20.4: allow the definition of a macro with 
the same name as a keyword in some special cases",
             "text": "The definition of a macro with the same name as a 
keyword can be useful in certain configurations to improve the 
guarantees that can be provided by Xen. See docs/misra/deviations.rst 
for a precise rationale for all such cases."
         },


>  /*
>   * Add the pseudo keyword 'fallthrough' so case statement blocks
>   * must end with any of these keywords:
> diff --git a/xen/include/xen/macros.h b/xen/include/xen/macros.h
> index f9ccde86fb23..ceca2e4a1bf1 100644
> --- a/xen/include/xen/macros.h
> +++ b/xen/include/xen/macros.h
> @@ -63,18 +63,18 @@
>  /* Hide a value from the optimiser. */
>  #define HIDE(x)                                 \
>      ({                                          \
> -        typeof(x) _x = (x);                     \
> +        auto _x = (x);                          \
>          asm volatile ( "" : "+r" (_x) );        \
>          _x;                                     \
>      })
> 
>  #define ABS(x) ({                              \
> -    typeof(x) x_ = (x);                        \
> +    auto x_ = (x);                             \
>      (x_ < 0) ? -x_ : x_;                       \
>  })
> 
>  #define SWAP(a, b) \
> -   do { typeof(a) t_ = (a); (a) = (b); (b) = t_; } while ( 0 )
> +   do { auto t_ = (a); (a) = (b); (b) = t_; } while ( 0 )
> 
>  #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]) + 
> __must_be_array(x))
> 
> @@ -102,15 +102,15 @@
>   */
>  #define min(x, y)                               \
>      ({                                          \
> -        const typeof(x) _x = (x);               \
> -        const typeof(y) _y = (y);               \
> +        const auto _x = (x);                    \
> +        const auto _y = (y);                    \
>          (void)(&_x == &_y); /* typecheck */     \
>          _x < _y ? _x : _y;                      \
>      })
>  #define max(x, y)                               \
>      ({                                          \
> -        const typeof(x) _x = (x);               \
> -        const typeof(y) _y = (y);               \
> +        const auto _x = (x);                    \
> +        const auto _y = (y);                    \
>          (void)(&_x == &_y); /* typecheck */     \
>          _x > _y ? _x : _y;                      \
>      })
> 
> base-commit: b2c0dc44b37516b758c38de04c61ad295ac0dff2

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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From: Dmytro Prokopchuk1 
To: Nicola Vetrini 
CC: "xen-devel@lists.xenproject.org" , Andrew
 Cooper , Anthony PERARD
	, Michal Orzel , Jan Beulich
	, Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Stefano
 Stabellini 
Subject: Re: [PATCH] docs/misra: fix sphinx-build issues
Thread-Topic: [PATCH] docs/misra: fix sphinx-build issues
Thread-Index: AQHcDbJCdYlsiZdfl0mX5ViIXi0+6LRjS8aAgAAFGoA=
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From: Juergen Gross 
To: linux-kernel@vger.kernel.org
Cc: Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	xen-devel@lists.xenproject.org
Subject: [PATCH] drivers/xen/xenbus: remove quirk for Xen 3.x
Date: Fri, 15 Aug 2025 09:40:52 +0200
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The kernel is not supported to run as a Xen guest on Xen versions
older than 4.0.

Remove xen_strict_xenbus_quirk() which is testing the Xen version to be
at least 4.0.

Signed-off-by: Juergen Gross 
---
 drivers/xen/xenbus/xenbus_xs.c | 23 -----------------------
 1 file changed, 23 deletions(-)

diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c
index 3c9da446b85d..528682bf0c7f 100644
--- a/drivers/xen/xenbus/xenbus_xs.c
+++ b/drivers/xen/xenbus/xenbus_xs.c
@@ -718,26 +718,6 @@ int xs_watch_msg(struct xs_watch_event *event)
 	return 0;
 }
 
-/*
- * Certain older XenBus toolstack cannot handle reading values that are
- * not populated. Some Xen 3.4 installation are incapable of doing this
- * so if we are running on anything older than 4 do not attempt to read
- * control/platform-feature-xs_reset_watches.
- */
-static bool xen_strict_xenbus_quirk(void)
-{
-#ifdef CONFIG_X86
-	uint32_t eax, ebx, ecx, edx, base;
-
-	base = xen_cpuid_base();
-	cpuid(base + 1, &eax, &ebx, &ecx, &edx);
-
-	if ((eax >> 16) < 4)
-		return true;
-#endif
-	return false;
-
-}
 static void xs_reset_watches(void)
 {
 	int err;
@@ -745,9 +725,6 @@ static void xs_reset_watches(void)
 	if (!xen_hvm_domain() || xen_initial_domain())
 		return;
 
-	if (xen_strict_xenbus_quirk())
-		return;
-
 	if (!xenbus_read_unsigned("control",
 				  "platform-feature-xs_reset_watches", 0))
 		return;
-- 
2.43.0



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Date: Fri, 15 Aug 2025 10:11:54 +0200
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Subject: Re: [PATCH v1 01/25] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
To: Stefano Stabellini 
Cc: "Penny, Zheng" , "Huang, Ray" ,
 Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 "Orzel, Michal" , Julien Grall ,
 "xen-devel@lists.xenproject.org" 
References: <20250803094738.3625269-1-Penny.Zheng@amd.com>
 <20250803094738.3625269-2-Penny.Zheng@amd.com>
 <371bc812-acdb-41ef-950b-3c9e5feea48e@suse.com>
 
 <3e20688c-c125-4aa4-bc06-1fe634550f70@suse.com>
 
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From: Jan Beulich 
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On 15.08.2025 01:14, Stefano Stabellini wrote:
> On Tue, 5 Aug 2025, Jan Beulich wrote:
>> On 05.08.2025 05:38, Penny, Zheng wrote:
>>> [Public]
>>>
>>>> -----Original Message-----
>>>> From: Jan Beulich 
>>>> Sent: Monday, August 4, 2025 3:43 PM
>>>> To: Penny, Zheng 
>>>> Cc: Huang, Ray ; Andrew Cooper
>>>> ; Roger Pau Monné ;
>>>> Anthony PERARD ; Orzel, Michal
>>>> ; Julien Grall ; Stefano Stabellini
>>>> ; xen-devel@lists.xenproject.org
>>>> Subject: Re: [PATCH v1 01/25] xen/x86: move domctl.o out of
>>>> PV_SHIM_EXCLUSIVE
>>>>
>>>> On 03.08.2025 11:47, Penny Zheng wrote:
>>>>> In order to fix CI error of a randconfig picking both
>>>>> PV_SHIM_EXCLUSIVE=y and HVM=y results in hvm.c being built, but
>>>>> domctl.c not being built, which leaves a few functions, like
>>>>> domctl_lock_acquire/release() undefined, causing linking to fail.
>>>>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE
>>>>> Makefile /hypercall-defs section, with this adjustment, we also need
>>>>> to release redundant vnuma_destroy() stub definition and paging_domctl
>>>>> hypercall-defs from PV_SHIM_EXCLUSIVE guardian, to not break
>>>>> compilation Above change will leave dead code in the shim binary
>>>>> temporarily and will be fixed with the introduction of CONFIG_DOMCTL.
>>>>>
>>>>> Fixes: 568f806cba4c ("xen/x86: remove "depends on
>>>>> !PV_SHIM_EXCLUSIVE"")
>>>>> Reported-by: Jan Beulich 
>>>>> Signed-off-by: Penny Zheng 
>>>>> ---
>>>>> v1 -> v2:
>>>>> - remove paging_domctl hypercall-defs
>>>>
>>>> And you've run this through a full round of testing this time, in isolation?
>>>
>>> This commit shall be committed together with "xen/x86: complement PG_log_dirty wrapping", (I've added in change log, idk why it didn't get delivered in the mail list in the last).
>>
>> And "committed together" still means the two at least build okay independently
>> (i.e. allowing the build-each-commit job to succeed)?
>>
>> As to the missing indication thereof in the submission: Patch 01 has a revlog,
>> so if anything was missing there you must have added it some other way. But
>> the cover letter is lacking that information as well. (As indicated earlier,
>> to increase the chance of such a remark actually being noticed, it's best put
>> in both places.)
>>
>>> As PG_log_dirty is disabled on PV mode, paging_domctl() will still have "undefined reference" on PV mode, which gets fixed in "xen/x86: complement PG_log_dirty wrapping".  I thought it better sits there.
>>> If it doesn't comply with the commit policy, I'll move according fix here.
>>
>> Let me post a pair of patches dealing with part of the problem, in an imo
>> (longer term) more desirable way.
> 
> With this patch https://marc.info/?l=xen-devel&m=175438069103017
> committed, can we go ahead with this patch, to resolve the outstanding
> build problem?

It first needs re-basing, I expect. There were also other anomalies, like a
requirement to commit together with another patch.

Jan


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Date: Fri, 15 Aug 2025 10:14:42 +0200
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Subject: Re: Consider changing CONFIG_ACPI default on ARM?
To: Demi Marie Obenour 
Cc: xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Paul Leiber , Elliott Mitchell 
References: 
 
 
 <1b96f2f3-55a2-4b33-84b1-a7c18d38d10c@suse.com>
 <6e9b5265-7a3b-4fd5-b14e-0e60a8b49833@gmail.com>
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On 14.08.2025 23:27, Demi Marie Obenour wrote:
> On 8/14/25 02:55, Jan Beulich wrote:
>> On 06.08.2025 06:30, Elliott Mitchell wrote:
>>> On Tue, Jul 01, 2025 at 10:01:13PM +0200, Paul Leiber wrote:
>>>>
>>>> Unfortunately, I don't have a direct answer to the question (as is so often
>>>> the case, due to my limited knowledge and experience). However, I am
>>>> successfully running Xen on a RPi 4 (mostly, except for some VLAN related
>>>> networking issues).
>>>>
>>>> I used instructions in [1] to install vanilla Debian on the RPi, including
>>>> UEFI boot and grub. I then compiled Xen with expert options and ACPI
>>>> enabled.
>>>>
>>>> I don't know if there are better solutions. For example, I suffer from the
>>>> fact that I2C doesn't work when using UEFI boot on a RPi. Nowadays, Debian
>>>> provides their own vanilla Debian images for RPi and with working I2C, but
>>>> these images are using a different boot method that I didn't know how to use
>>>> with Xen.  So far, the procedure described above seems to be the easiest
>>>> solution for me.
>>>
>>>
>>>> [1] https://forums.raspberrypi.com/viewtopic.php?t=282839
>>>>
>>>> Am 30.06.2025 um 12:35 schrieb Sumit Semwal:
>>>>>
>>>>> I've just begun to experiment with the Raspberry Pi 5, trying to run a
>>>>> simple xen + Dom0 setup, using uBoot, and the bookworm based Rpi
>>>>> distro.
>>>>>
>>>>> I've tried combinations of the following setup:
>>>>>
>>>>> 1. prebuilt Rpi5 kernel + dtbs, and have also tried to build them from
>>>>> source [1]
>>>>> 2. Xen from upstream [2] and xen-troops [3]
>>>>> 3. upstream uBoot from [4]
>>>>>
>>>>> but with the same result: [short log below; I can provide a fuller log
>>>>> if needed]
>>>>>
>>>>> (XEN) DT: ** translation for device /axi/msi-controller@1000130000 **
>>>>> (XEN) DT: bus is default (na=2, ns=2) on /axi
>>>>> (XEN) DT: translating address:<3> 000000ff<3> fffff000<3>
>>>>> (XEN) DT: parent bus is default (na=2, ns=1) on /
>>>>> (XEN) DT: walking ranges...
>>>>> (XEN) DT: default map, cp=0, s=1000000000, da=fffffff000
>>>>> (XEN) DT: default map, cp=1000000000, s=100000000, da=fffffff000
>>>>> (XEN) DT: default map, cp=1400000000, s=400000000, da=fffffff000
>>>>> (XEN) DT: default map, cp=1800000000, s=400000000, da=fffffff000
>>>>> (XEN) DT: default map, cp=1c00000000, s=400000000, da=fffffff000
>>>>> (XEN) DT: not found !
>>>>> (XEN) Unable to retrieve address 1 for /axi/msi-controller@1000130000
>>>>> (XEN) Device tree generation failed (-22).
>>>>> (XEN) debugtrace_dump() global buffer starting
>>>>> 1 cpupool_create(pool=0,sched=6)
>>>>> 2 Created cpupool 0 with scheduler SMP Credit Scheduler rev2 (credit2)
>>>>> 3 cpupool_add_domain(dom=0,pool=0) n_dom 1 rc 0
>>>>> (XEN) wrap: 0
>>>>> (XEN) debugtrace_dump() global buffer finished
>>>>> (XEN)
>>>>> (XEN) ****************************************
>>>>> (XEN) Panic on CPU 0:
>>>>> (XEN) Could not set up DOM0 guest OS (rc = -22)
>>>>> (XEN) ****************************************
>>>>>
>>>>>
>>>>> I'm certain I'm missing something, but before I delve deeper, I just
>>>>> wanted to ask if this is a known issue, and if so, are there any
>>>>> workarounds or solutions available for this?
>>>>>
>>>>> Any help about this is highly appreciated!
>>>>>
>>>>> Thanks and Best regards,
>>>>> Sumit.
>>>>>
>>>>> [1]:  https://github.com/raspberrypi/linux rpi-6.12.y branch
>>>>> [2]: git://xenbits.xen.org/xen.git - main branch
>>>>> [3] xen-troops https://github.com/xen-troops/xen - rpi5_dev branch
>>>>> [4]: https://github.com/u-boot/u-boot.git master branch
>>>
>>> Ultimately Debian is choosing to leave most defaults alone.  So far the
>>> Xen developers have left CONFIG_ACPI defaulting to off on ARM*.  The
>>> Debian project doesn't have paid people to support Raspberry PI hardware,
>>> despite being rather common.  As a result there aren't any official
>>> Raspberry PI images, but people associated with Tianocore have gotten
>>> generic images to boot on Raspberry PI hardware.
>>>
>>> I'm unsure of the likelihood of getting the Debian maintainers to
>>> override the default.  Yet due being by far the simplest way to install
>>> Debian and Xen on a very common ARM64 platform, perhaps the Xen
>>> developers should consider changing?
>>
>> In an open source project everyone is a developer. There is a
>> significant amount of work someone needs to pick up to change this
>> SUPPORT.md entry:
>>
>> ### Host ACPI (via Domain 0)
>>
>>     Status, x86 PV: Supported
>>     Status, ARM: Experimental
>>
>> Parties interested in changing the support status of any component are the
>> primary candidates to actually carry out the necessary work.
> 
> What is that work?

To determine what exactly needs doing is part of the exercise. I, for one, am
unaware of a concrete written down set of things which need doing.

Jan


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Date: Fri, 15 Aug 2025 09:17:45 +0100
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Subject: Re: [PATCH v2] xen: Use auto as per C23
To: Nicola Vetrini 
Cc: Xen-devel ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 Roberto Bagnara ,
 "consulting @ bugseng . com" 
References: <20250814222524.2638883-1-andrew.cooper3@citrix.com>
 <3056ed85948288639110e3cdd6b28c6e@bugseng.com>
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From: Andrew Cooper 
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On 15/08/2025 8:20 am, Nicola Vetrini wrote:
> On 2025-08-15 00:25, Andrew Cooper wrote:
>> In macros it is common to declare local variables using typeof(param)
>> in order
>> to ensure that side effects are only evaluated once.  A consequence
>> of this is
>> double textural expansion of the parameter, which can get out of hand
>> very
>> quickly with nested macros.
>>
>> In C23, the auto keyword has been repurposed to perform type inference.
>>
>> A GCC extension, __auto_type, is now avaialble in the new toolchain
>> baseline
>> and avoids the double textural expansion.
>>
>> Signed-off-by: Andrew Cooper 
>
> Reviewed-by: Nicola Vetrini 

Thankyou.

>>
>> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
>> index 88bf26bc5109..38ef5d82ad95 100644
>> --- a/xen/include/xen/compiler.h
>> +++ b/xen/include/xen/compiler.h
>> @@ -64,6 +64,20 @@
>>  # define asm_inline asm
>>  #endif
>>
>> +/*
>> + * In C23, the auto keyword has been repurposed to perform type
>> inference.
>> + *
>> + * This behaviour is available via the __auto_type extension in
>> supported
>> + * toolchains.
>> + *
>> + *
>> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
>> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
>> + */
>> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
>> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23
>> meaning. */
>> +#define auto __auto_type
>> +#endif
>> +
>
> A more detailed explanation should live in deviations.rst under this
> bullet point
>
>    * - R20.4
>      - The override of the keyword \"inline\" in xen/compiler.h is
> present so
>        that section contents checks pass when the compiler chooses not to
>        inline a particular function.
>      - Comment-based deviation.
>
> as described in the SAF entry:
>
>         {
>             "id": "SAF-3-safe",
>             "analyser": {
>                 "eclair": "MC3A2.R20.4"
>             },
>             "name": "MC3A2.R20.4: allow the definition of a macro with
> the same name as a keyword in some special cases",
>             "text": "The definition of a macro with the same name as a
> keyword can be useful in certain configurations to improve the
> guarantees that can be provided by Xen. See docs/misra/deviations.rst
> for a precise rationale for all such cases."
>         },

Ah right.  What about this:

"Xen does not use the \"auto\" keyword as a storage qualifier.  The
override of the keyword \"auto\" in xen/compiler.h is to give it it's
C23 behaviour of type inference."

?

~Andrew

P.S. I thought that final fix was too easy.  Your instructions for the
main config were spot on and worked first time, except for getting the
R20.4 violation too.


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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
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On 14.08.2025 20:09, Andrew Cooper wrote:
> On 14/08/2025 9:55 am, Jan Beulich wrote:
>> On 13.08.2025 13:25, Andrew Cooper wrote:
>>> On 12/08/2025 10:19 am, Jan Beulich wrote:
>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>> Since commit a35816b5cae8 ("x86/traps: Introduce early_traps_init() and
>>>>> simplify setup"), load_system_tables() is called later on the BSP, so the
>>>>> SYS_STATE_early_boot check can be dropped from the safety BUG_ON().
>>>>>
>>>>> Move the BUILD_BUG_ON() into build_assertions(),
>>>> I'm not quite convinced of this move - having the related BUILD_BUG_ON()
>>>> and BUG_ON() next to each other would seem better to me.
>>> I don't see a specific reason for them to be together, and the comment
>>> explains what's going on.
>>>
>>> With FRED, we want a related BUILD_BUG_ON(), but there's no equivalent
>>> BUG_ON() because MSR_RSP_SL0 will #GP on being misaligned.
>> That BUILD_BUG_ON() could then sit next to the MSR write? Unless of course
>> that ends up sitting in an assembly source.
> 
> It's the bottom hunk in patch 14, which you've looked at now.
> 
> Personally, I think both BUILD_BUG_ON()'s should be together, because
> they are related.

I don't really agree, but I also won't insist on my preference to be followed.
IOW please keep as is.

Jan


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On 15/08/2025 8:28 am, Dmytro Prokopchuk1 wrote:
>
> On 8/15/25 10:09, Nicola Vetrini wrote:
>> On 2025-08-15 09:00, Dmytro Prokopchuk1 wrote:
>>> Fix the following issues:
>>> 1. xen/docs/misra/deviations.rst:90: WARNING: Inline interpreted text or
>>> phrase reference start-string without end-string. [docutils]
>>> 2. xen/docs/misra/deviations.rst:54: ERROR: Error parsing content block
>>> for the "list-table" directive: uniform two-level bullet list expected,
>>> but row 6 does not contain the same number of items as row 1 (2 vs 3).
>>> * - R2.1
>>>   - Calls to the `__builtin_unreachable()` function inside the 
>>> expansion of
>>>     the `ASSERT_UNREACHABLE()` macro may cause a function to be marked as
>>>     non-returning. This behavior occurs only in configurations where
>>>     assertions are enabled. To address this, the `noreturn` property for
>>>     `__builtin_unreachable()` is overridden in these contexts, 
>>> resulting in
>>>     the absence of reports that do not have an impact on safety, despite
>>>     being true positives.
>>>     Xen expects developers to ensure code remains safe and reliable in 
>>> builds,
>>>     even when debug-only assertions like `ASSERT_UNREACHABLE() are 
>>> removed.
>>> 3. xen/docs/misra/rules.rst:127: WARNING: Inline interpreted text or 
>>> phrase
>>> reference start-string without end-string. [docutils]
>>>
>>> Signed-off-by: Dmytro Prokopchuk 
>> Reviewed-by: Nicola Vetrini 

Reviewed-by: Andrew Cooper 

>>
>> I recall that Andrew wanted to add a doc build test to avoid introducing 
>> warnings.

Yes I do, but sadly still on my TODO list.

>>  On that front, with my Sphinx version I also see this build 
>> warning:
>>
>> Running Sphinx v8.1.3
>> WARNING: Calling get_html_theme_path is deprecated. If you are calling 
>> it to define html_theme_path, you are safe to remove that code.
>>
> Yes, I see the same warning on my end.
> Need to address that in docs/conf.py as well.

IIRC, this needs ignoring for now.  It is still required in the minimum
Sphinx version we support.

~Andrew


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Date: Fri, 15 Aug 2025 09:28:25 +0100
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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
 traps-setup.c
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 15/08/2025 9:22 am, Jan Beulich wrote:
> On 14.08.2025 20:09, Andrew Cooper wrote:
>> On 14/08/2025 9:55 am, Jan Beulich wrote:
>>> On 13.08.2025 13:25, Andrew Cooper wrote:
>>>> On 12/08/2025 10:19 am, Jan Beulich wrote:
>>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>>> Since commit a35816b5cae8 ("x86/traps: Introduce early_traps_init() and
>>>>>> simplify setup"), load_system_tables() is called later on the BSP, so the
>>>>>> SYS_STATE_early_boot check can be dropped from the safety BUG_ON().
>>>>>>
>>>>>> Move the BUILD_BUG_ON() into build_assertions(),
>>>>> I'm not quite convinced of this move - having the related BUILD_BUG_ON()
>>>>> and BUG_ON() next to each other would seem better to me.
>>>> I don't see a specific reason for them to be together, and the comment
>>>> explains what's going on.
>>>>
>>>> With FRED, we want a related BUILD_BUG_ON(), but there's no equivalent
>>>> BUG_ON() because MSR_RSP_SL0 will #GP on being misaligned.
>>> That BUILD_BUG_ON() could then sit next to the MSR write? Unless of course
>>> that ends up sitting in an assembly source.
>> It's the bottom hunk in patch 14, which you've looked at now.
>>
>> Personally, I think both BUILD_BUG_ON()'s should be together, because
>> they are related.
> I don't really agree, but I also won't insist on my preference to be followed.
> IOW please keep as is.

Thankyou.  Can I consider this to be A-by then?  (This, and the rename
to percpu_early_traps_init() are the only two remaining items in the
entire first half of the series.)

~Andrew



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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
 traps-setup.c
To: Andrew Cooper 
Cc: Xen-devel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Nicola Vetrini 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-10-andrew.cooper3@citrix.com>
 <80285a06f5d4fb3bd3e378317cca61ca@bugseng.com>
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On 14.08.2025 20:20, Andrew Cooper wrote:
> On 14/08/2025 8:26 am, Jan Beulich wrote:
>> On 13.08.2025 13:36, Andrew Cooper wrote:
>>> On 12/08/2025 10:43 am, Nicola Vetrini wrote:
>>>> On 2025-08-08 22:23, Andrew Cooper wrote:
>>>>> diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
>>>>> index 8ca379c9e4cb..13b8fcf0ba51 100644
>>>>> --- a/xen/arch/x86/traps-setup.c
>>>>> +++ b/xen/arch/x86/traps-setup.c
>>>>> @@ -19,6 +20,124 @@ boolean_param("ler", opt_ler);
>>>>>
>>>>>  void nocall entry_PF(void);
>>>>>
>>>>> +/*
>>>>> + * Sets up system tables and descriptors for IDT devliery.
>>>>> + *
>>>>> + * - Sets up TSS with stack pointers, including ISTs
>>>>> + * - Inserts TSS selector into regular and compat GDTs
>>>>> + * - Loads GDT, IDT, TR then null LDT
>>>>> + * - Sets up IST references in the IDT
>>>>> + */
>>>>> +static void load_system_tables(void)
>>>>> +{
>>>>> +    unsigned int i, cpu = smp_processor_id();
>>>>> +    unsigned long stack_bottom = get_stack_bottom(),
>>>>> +        stack_top = stack_bottom & ~(STACK_SIZE - 1);
>>>>> +    /*
>>>>> +     * NB: define tss_page as a local variable because clang 3.5
>>>>> doesn't
>>>>> +     * support using ARRAY_SIZE against per-cpu variables.
>>>>> +     */
>>>>> +    struct tss_page *tss_page = &this_cpu(tss_page);
>>>>> +    idt_entry_t *idt = this_cpu(idt);
>>>>> +
>>>> Given the clang baseline this might not be needed anymore?
>>> Hmm.  While true, looking at 51461114e26, the code is definitely better
>>> written with the tss_page variable and we wouldn't want to go back to
>>> the old form.
>>>
>>> I think that I'll simply drop the comment.
>>>
>>> ~Andrew
>>>
>>> P.S.
>>>
>>> Generally speaking, because of the RELOC_HIDE() in this_cpu(), any time
>>> you ever want two accesses to a variable, it's better (code gen wise) to
>>> construct a pointer to it and use the point multiple times.
>>>
>>> I don't understand why there's a RELOC_HIDE() in this_cpu().  The
>>> justification doesn't make sense, but I've not had time to explore what
>>> happens if we take it out.
>> There's no justification in xen/percpu.h?
> 
> Well, it's given in compiler.h by RELOC_HIDE().
> 
> /* This macro obfuscates arithmetic on a variable address so that gcc
>    shouldn't recognize the original var, and make assumptions about it */
> 
> 
> But this is far from convincing.
> 
>>
>> My understanding is that we simply may not expose any accesses to per_cpu_*
>> variables directly to the compiler, or there's a risk that it might access
>> the "master" variable (i.e. CPU0's on at least x86).
> 
> RELOC_HIDE() doesn't do anything about the correctness of the pointer
> arithmetic expression to make the access work.
> 
> I don't see how a correct expression can ever access CPU0's data by
> accident.

Hmm, upon another look I agree. I wonder whether we inherited this from
Linux, where in turn it may have been merely a workaround to deal with
preemptible code not correctly accessing per-CPU data (i.e. not
accounting for get_per_cpu_offset() not being stable across preemption).
Yet then per_cpu() would have been of similar concern when "cpu" isn't
properly re-fetched after any possible preemption point ...

Jan


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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
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To: Andrew Cooper 
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On 15.08.2025 10:28, Andrew Cooper wrote:
> On 15/08/2025 9:22 am, Jan Beulich wrote:
>> On 14.08.2025 20:09, Andrew Cooper wrote:
>>> On 14/08/2025 9:55 am, Jan Beulich wrote:
>>>> On 13.08.2025 13:25, Andrew Cooper wrote:
>>>>> On 12/08/2025 10:19 am, Jan Beulich wrote:
>>>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>>>> Since commit a35816b5cae8 ("x86/traps: Introduce early_traps_init() and
>>>>>>> simplify setup"), load_system_tables() is called later on the BSP, so the
>>>>>>> SYS_STATE_early_boot check can be dropped from the safety BUG_ON().
>>>>>>>
>>>>>>> Move the BUILD_BUG_ON() into build_assertions(),
>>>>>> I'm not quite convinced of this move - having the related BUILD_BUG_ON()
>>>>>> and BUG_ON() next to each other would seem better to me.
>>>>> I don't see a specific reason for them to be together, and the comment
>>>>> explains what's going on.
>>>>>
>>>>> With FRED, we want a related BUILD_BUG_ON(), but there's no equivalent
>>>>> BUG_ON() because MSR_RSP_SL0 will #GP on being misaligned.
>>>> That BUILD_BUG_ON() could then sit next to the MSR write? Unless of course
>>>> that ends up sitting in an assembly source.
>>> It's the bottom hunk in patch 14, which you've looked at now.
>>>
>>> Personally, I think both BUILD_BUG_ON()'s should be together, because
>>> they are related.
>> I don't really agree, but I also won't insist on my preference to be followed.
>> IOW please keep as is.
> 
> Thankyou.  Can I consider this to be A-by then?  (This, and the rename
> to percpu_early_traps_init() are the only two remaining items in the
> entire first half of the series.)

Yes:
Acked-by: Jan Beulich 

Jan


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Date: Fri, 15 Aug 2025 10:33:45 +0200
From: Nicola Vetrini 
To: Andrew Cooper 
Cc: Xen-devel , Anthony PERARD
 , Michal Orzel , Jan
 Beulich , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini
 , Roberto Bagnara ,
 "consulting @ bugseng . com" 
Subject: Re: [PATCH v2] xen: Use auto as per C23
In-Reply-To: 
References: <20250814222524.2638883-1-andrew.cooper3@citrix.com>
 <3056ed85948288639110e3cdd6b28c6e@bugseng.com>
 
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On 2025-08-15 10:17, Andrew Cooper wrote:
> On 15/08/2025 8:20 am, Nicola Vetrini wrote:
>> On 2025-08-15 00:25, Andrew Cooper wrote:
>>> In macros it is common to declare local variables using typeof(param)
>>> in order
>>> to ensure that side effects are only evaluated once.  A consequence
>>> of this is
>>> double textural expansion of the parameter, which can get out of hand
>>> very
>>> quickly with nested macros.
>>> 
>>> In C23, the auto keyword has been repurposed to perform type 
>>> inference.
>>> 
>>> A GCC extension, __auto_type, is now avaialble in the new toolchain
>>> baseline
>>> and avoids the double textural expansion.
>>> 
>>> Signed-off-by: Andrew Cooper 
>> 
>> Reviewed-by: Nicola Vetrini 
> 
> Thankyou.
> 
>>> 
>>> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
>>> index 88bf26bc5109..38ef5d82ad95 100644
>>> --- a/xen/include/xen/compiler.h
>>> +++ b/xen/include/xen/compiler.h
>>> @@ -64,6 +64,20 @@
>>>  # define asm_inline asm
>>>  #endif
>>> 
>>> +/*
>>> + * In C23, the auto keyword has been repurposed to perform type
>>> inference.
>>> + *
>>> + * This behaviour is available via the __auto_type extension in
>>> supported
>>> + * toolchains.
>>> + *
>>> + *
>>> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
>>> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
>>> + */
>>> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
>>> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23
>>> meaning. */
>>> +#define auto __auto_type
>>> +#endif
>>> +
>> 
>> A more detailed explanation should live in deviations.rst under this
>> bullet point
>> 
>>    * - R20.4
>>      - The override of the keyword \"inline\" in xen/compiler.h is
>> present so
>>        that section contents checks pass when the compiler chooses not 
>> to
>>        inline a particular function.
>>      - Comment-based deviation.
>> 
>> as described in the SAF entry:
>> 
>>         {
>>             "id": "SAF-3-safe",
>>             "analyser": {
>>                 "eclair": "MC3A2.R20.4"
>>             },
>>             "name": "MC3A2.R20.4: allow the definition of a macro with
>> the same name as a keyword in some special cases",
>>             "text": "The definition of a macro with the same name as a
>> keyword can be useful in certain configurations to improve the
>> guarantees that can be provided by Xen. See docs/misra/deviations.rst
>> for a precise rationale for all such cases."
>>         },
> 
> Ah right.  What about this:
> 
> "Xen does not use the \"auto\" keyword as a storage qualifier.  The
> override of the keyword \"auto\" in xen/compiler.h is to give it it's
> C23 behaviour of type inference."
> 
> ?
> 

Seems good to me. Maybe this should be spelled out in ./CODING_STYLE as 
well, so that newcomers don't trip over this?

> ~Andrew
> 
> P.S. I thought that final fix was too easy.  Your instructions for the
> main config were spot on and worked first time, except for getting the
> R20.4 violation too.

Yeah, forgot about that one; it's not so common to override keywords.

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [PATCH 13/22] x86: FRED enumerations
To: Andrew Cooper 
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 Xen-devel 
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On 14.08.2025 20:45, Andrew Cooper wrote:
> On 14/08/2025 2:19 pm, Jan Beulich wrote:
>> On 14.08.2025 13:20, Jan Beulich wrote:
>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>> --- a/xen/include/public/arch-x86/cpufeatureset.h
>>>> +++ b/xen/include/public/arch-x86/cpufeatureset.h
>>>> @@ -310,7 +310,10 @@ XEN_CPUFEATURE(ARCH_PERF_MON, 10*32+8) /*   Architectural Perfmon */
>>>>  XEN_CPUFEATURE(FZRM,         10*32+10) /*A  Fast Zero-length REP MOVSB */
>>>>  XEN_CPUFEATURE(FSRS,         10*32+11) /*A  Fast Short REP STOSB */
>>>>  XEN_CPUFEATURE(FSRCS,        10*32+12) /*A  Fast Short REP CMPSB/SCASB */
>>>> +XEN_CPUFEATURE(FRED,         10*32+17) /*   Fast Return and Event Delivery */
>>>> +XEN_CPUFEATURE(LKGS,         10*32+18) /*   Load Kernel GS instruction */
>>>>  XEN_CPUFEATURE(WRMSRNS,      10*32+19) /*S  WRMSR Non-Serialising */
>>>> +XEN_CPUFEATURE(NMI_SRC,      10*32+20) /*   NMI-Source Reporting */
>>>>  XEN_CPUFEATURE(AMX_FP16,     10*32+21) /*   AMX FP16 instruction */
>>>>  XEN_CPUFEATURE(AVX_IFMA,     10*32+23) /*A  AVX-IFMA Instructions */
>>>>  XEN_CPUFEATURE(LAM,          10*32+26) /*   Linear Address Masking */
>>> I'd like to note that we could long have had this if my long-pending emulator
>>> patch had gone in at some point.
>> Actually what I further have there, and what in the context of patch 15 I
>> notice you should have here is
>>
>> --- a/xen/tools/gen-cpuid.py
>> +++ b/xen/tools/gen-cpuid.py
>> @@ -278,7 +278,8 @@ def crunch_numbers(state):
>>          # superpages, PCID and PKU are only available in 4 level paging.
>>          # NO_LMSL indicates the absense of Long Mode Segment Limits, which
>>          # have been dropped in hardware.
>> -        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD],
>> +        LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL, AMX_TILE, CMPCCXADD,
>> +             LKGS],
>>  
>>          # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the
>>          # standard 3DNow in the earlier K6 processors.
>> @@ -347,6 +348,9 @@ def crunch_numbers(state):
>>          # computational instructions.  All further AMX features are built on top
>>          # of AMX-TILE.
>>          AMX_TILE: [AMX_BF16, AMX_INT8, AMX_FP16, AMX_COMPLEX],
>> +
>> +        # FRED builds on the LKGS instruction.
>> +        LKGS: [FRED],
>>      }
>>  
>>      deep_features = tuple(sorted(deps.keys()))
> 
> Hmm.  Yes, but normally this is part of guest enablement.

Hence why I would have wanted the emulator patch to long have gone in.

> Having now done the Xen work and concluded that we don't actually need
> LKGS, I'm rethinking the linkage here.  It's probably the right thing to
> do in practice, but probably needs a bit more in the way of
> justification.  "built on" doesn't quite cut it IMO.

The comment can be adjusted (or dropped). Im "builds on" is quite adequate,
as without SWAPGS you won't really have a way to get things working in an
OS without having LKGS available. In Xen we're in a slightly different
position ...

Jan


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Subject: Re: [PATCH 15/22] x86/traps: Introduce opt_fred
To: Andrew Cooper 
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On 14.08.2025 21:16, Andrew Cooper wrote:
> On 14/08/2025 2:30 pm, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> ... disabled by default.  There is a lot of work before FRED can be enabled by
>>> default.
>>>
>>> One part of FRED, the LKGS (Load Kernel GS) instruction, is enumerated
>>> separately but is mandatory as FRED disallows the SWAPGS instruction.
>>> Therefore, both CPUID bits must be checked.
>> See my (further) reply to patch 13 - I think FRED simply ought to depend on
>> LKGS.
>>
>>> @@ -20,6 +22,9 @@ unsigned int __ro_after_init ler_msr;
>>>  static bool __initdata opt_ler;
>>>  boolean_param("ler", opt_ler);
>>>  
>>> +int8_t __ro_after_init opt_fred = 0; /* -1 when supported. */
>> I'm a little puzzled by the comment? DYM "once default-enabled"?
> 
> Well, I have this temporary patch
> https://gitlab.com/xen-project/hardware/xen-staging/-/commit/70ef6a1178a411a29b7b1745a1112e267ffb6245
> that will turn into a real patch when we enable FRED by default.
> 
> As much as anything else, it was just a TODO.
> 
> 
>>  Then ...
>>
>>> @@ -305,6 +310,32 @@ void __init traps_init(void)
>>>      /* Replace early pagefault with real pagefault handler. */
>>>      _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF);
>>>  
>>> +    if ( !cpu_has_fred || !cpu_has_lkgs )
>>> +    {
>>> +        if ( opt_fred )
>> ... this won't work anymore once the initializer is changed.
> 
> Hmm yes.  That wants to be an == 1 check.  Fixed.
> 
>>
>>> +            printk(XENLOG_WARNING "FRED not available, ignoring\n");
>>> +        opt_fred = false;
>> Better use 0 here?
>>
>>> +    }
>>> +
>>> +    if ( opt_fred == -1 )
>>> +        opt_fred = !pv_shim;
>> Imo it would be better to have the initializer be -1 right away, and comment
>> out the "!pv_shim" here, until we mean it to be default-enabled.
> 
> It cannot be -1, or Xen will fail spectacularly on any FRED capable
> hardware.  Setting to -1 is the point at which FRED becomes security
> supported.

I guess I'm not following: If it was -1, and if the code here was

    if ( opt_fred < 0 )
        opt_fred = 0 /* !pv_shim */;

why would things "fail spectacularly" unless someone passed "fred" on
the command line?

Jan


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Date: Fri, 15 Aug 2025 10:40:12 +0200
From: Nicola Vetrini 
To: Jan Beulich 
Cc: Andrew Cooper , Xen-devel
 , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
 traps-setup.c
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On 2025-08-15 10:30, Jan Beulich wrote:
> On 14.08.2025 20:20, Andrew Cooper wrote:
>> On 14/08/2025 8:26 am, Jan Beulich wrote:
>>> On 13.08.2025 13:36, Andrew Cooper wrote:
>>>> On 12/08/2025 10:43 am, Nicola Vetrini wrote:
>>>>> On 2025-08-08 22:23, Andrew Cooper wrote:
>>>>>> diff --git a/xen/arch/x86/traps-setup.c 
>>>>>> b/xen/arch/x86/traps-setup.c
>>>>>> index 8ca379c9e4cb..13b8fcf0ba51 100644
>>>>>> --- a/xen/arch/x86/traps-setup.c
>>>>>> +++ b/xen/arch/x86/traps-setup.c
>>>>>> @@ -19,6 +20,124 @@ boolean_param("ler", opt_ler);
>>>>>> 
>>>>>>  void nocall entry_PF(void);
>>>>>> 
>>>>>> +/*
>>>>>> + * Sets up system tables and descriptors for IDT devliery.
>>>>>> + *
>>>>>> + * - Sets up TSS with stack pointers, including ISTs
>>>>>> + * - Inserts TSS selector into regular and compat GDTs
>>>>>> + * - Loads GDT, IDT, TR then null LDT
>>>>>> + * - Sets up IST references in the IDT
>>>>>> + */
>>>>>> +static void load_system_tables(void)
>>>>>> +{
>>>>>> +    unsigned int i, cpu = smp_processor_id();
>>>>>> +    unsigned long stack_bottom = get_stack_bottom(),
>>>>>> +        stack_top = stack_bottom & ~(STACK_SIZE - 1);
>>>>>> +    /*
>>>>>> +     * NB: define tss_page as a local variable because clang 3.5
>>>>>> doesn't
>>>>>> +     * support using ARRAY_SIZE against per-cpu variables.
>>>>>> +     */
>>>>>> +    struct tss_page *tss_page = &this_cpu(tss_page);
>>>>>> +    idt_entry_t *idt = this_cpu(idt);
>>>>>> +
>>>>> Given the clang baseline this might not be needed anymore?
>>>> Hmm.  While true, looking at 51461114e26, the code is definitely 
>>>> better
>>>> written with the tss_page variable and we wouldn't want to go back 
>>>> to
>>>> the old form.
>>>> 
>>>> I think that I'll simply drop the comment.
>>>> 
>>>> ~Andrew
>>>> 
>>>> P.S.
>>>> 
>>>> Generally speaking, because of the RELOC_HIDE() in this_cpu(), any 
>>>> time
>>>> you ever want two accesses to a variable, it's better (code gen 
>>>> wise) to
>>>> construct a pointer to it and use the point multiple times.
>>>> 
>>>> I don't understand why there's a RELOC_HIDE() in this_cpu().  The
>>>> justification doesn't make sense, but I've not had time to explore 
>>>> what
>>>> happens if we take it out.
>>> There's no justification in xen/percpu.h?
>> 
>> Well, it's given in compiler.h by RELOC_HIDE().
>> 
>> /* This macro obfuscates arithmetic on a variable address so that gcc
>>    shouldn't recognize the original var, and make assumptions about it 
>> */
>> 
>> 
>> But this is far from convincing.
>> 
>>> 
>>> My understanding is that we simply may not expose any accesses to 
>>> per_cpu_*
>>> variables directly to the compiler, or there's a risk that it might 
>>> access
>>> the "master" variable (i.e. CPU0's on at least x86).
>> 
>> RELOC_HIDE() doesn't do anything about the correctness of the pointer
>> arithmetic expression to make the access work.
>> 
>> I don't see how a correct expression can ever access CPU0's data by
>> accident.
> 
> Hmm, upon another look I agree. I wonder whether we inherited this from
> Linux, where in turn it may have been merely a workaround to deal with
> preemptible code not correctly accessing per-CPU data (i.e. not
> accounting for get_per_cpu_offset() not being stable across 
> preemption).
> Yet then per_cpu() would have been of similar concern when "cpu" isn't
> properly re-fetched after any possible preemption point ...
> 
> Jan

Probably inherited with a stripped-down comment on top of RELOC_HIDE, 
see [1]. In a way it does make sense that the compiler may decide to 
optimize based on this assumption, though I don't know whether wrapping 
is meant to happen with per-CPU variables.

[1] 
https://elixir.bootlin.com/linux/v6.16/source/include/linux/compiler-gcc.h#L31

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [PATCH] docs/misra: fix sphinx-build issues
To: Dmytro Prokopchuk1 
Cc: Andrew Cooper ,
 Anthony PERARD ,
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On 15.08.2025 09:00, Dmytro Prokopchuk1 wrote:
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -95,7 +95,8 @@ Deviations related to MISRA C:2012 Rules:
>         the absence of reports that do not have an impact on safety, despite
>         being true positives.
>         Xen expects developers to ensure code remains safe and reliable in builds,
> -       even when debug-only assertions like `ASSERT_UNREACHABLE() are removed.
> +       even when debug-only assertions like `ASSERT_UNREACHABLE()` are removed.
> +     - ECLAIR has been configured to ignore those statements.

Mind me asking why one form of quoting is used here (using back-tick), while ...

> --- a/docs/misra/rules.rst
> +++ b/docs/misra/rules.rst
> @@ -124,7 +124,7 @@ maintainers if you want to suggest a change.
>             they are used to generate definitions for asm modules
>           - Declarations without initializer are safe, as they are not
>             executed
> -         - Functions that are no-return due to calls to the `ASSERT_UNREACHABLE()'
> +         - Functions that are no-return due to calls to the 'ASSERT_UNREACHABLE()'

... another is used here (single quotes)?

Jan


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Subject: Re: [PATCH 09/22] x86/traps: Move load_system_tables() into
 traps-setup.c
To: Nicola Vetrini 
Cc: Andrew Cooper ,
 Xen-devel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 15.08.2025 10:40, Nicola Vetrini wrote:
> On 2025-08-15 10:30, Jan Beulich wrote:
>> On 14.08.2025 20:20, Andrew Cooper wrote:
>>> On 14/08/2025 8:26 am, Jan Beulich wrote:
>>>> On 13.08.2025 13:36, Andrew Cooper wrote:
>>>>> On 12/08/2025 10:43 am, Nicola Vetrini wrote:
>>>>>> On 2025-08-08 22:23, Andrew Cooper wrote:
>>>>>>> diff --git a/xen/arch/x86/traps-setup.c 
>>>>>>> b/xen/arch/x86/traps-setup.c
>>>>>>> index 8ca379c9e4cb..13b8fcf0ba51 100644
>>>>>>> --- a/xen/arch/x86/traps-setup.c
>>>>>>> +++ b/xen/arch/x86/traps-setup.c
>>>>>>> @@ -19,6 +20,124 @@ boolean_param("ler", opt_ler);
>>>>>>>
>>>>>>>  void nocall entry_PF(void);
>>>>>>>
>>>>>>> +/*
>>>>>>> + * Sets up system tables and descriptors for IDT devliery.
>>>>>>> + *
>>>>>>> + * - Sets up TSS with stack pointers, including ISTs
>>>>>>> + * - Inserts TSS selector into regular and compat GDTs
>>>>>>> + * - Loads GDT, IDT, TR then null LDT
>>>>>>> + * - Sets up IST references in the IDT
>>>>>>> + */
>>>>>>> +static void load_system_tables(void)
>>>>>>> +{
>>>>>>> +    unsigned int i, cpu = smp_processor_id();
>>>>>>> +    unsigned long stack_bottom = get_stack_bottom(),
>>>>>>> +        stack_top = stack_bottom & ~(STACK_SIZE - 1);
>>>>>>> +    /*
>>>>>>> +     * NB: define tss_page as a local variable because clang 3.5
>>>>>>> doesn't
>>>>>>> +     * support using ARRAY_SIZE against per-cpu variables.
>>>>>>> +     */
>>>>>>> +    struct tss_page *tss_page = &this_cpu(tss_page);
>>>>>>> +    idt_entry_t *idt = this_cpu(idt);
>>>>>>> +
>>>>>> Given the clang baseline this might not be needed anymore?
>>>>> Hmm.  While true, looking at 51461114e26, the code is definitely 
>>>>> better
>>>>> written with the tss_page variable and we wouldn't want to go back 
>>>>> to
>>>>> the old form.
>>>>>
>>>>> I think that I'll simply drop the comment.
>>>>>
>>>>> ~Andrew
>>>>>
>>>>> P.S.
>>>>>
>>>>> Generally speaking, because of the RELOC_HIDE() in this_cpu(), any 
>>>>> time
>>>>> you ever want two accesses to a variable, it's better (code gen 
>>>>> wise) to
>>>>> construct a pointer to it and use the point multiple times.
>>>>>
>>>>> I don't understand why there's a RELOC_HIDE() in this_cpu().  The
>>>>> justification doesn't make sense, but I've not had time to explore 
>>>>> what
>>>>> happens if we take it out.
>>>> There's no justification in xen/percpu.h?
>>>
>>> Well, it's given in compiler.h by RELOC_HIDE().
>>>
>>> /* This macro obfuscates arithmetic on a variable address so that gcc
>>>    shouldn't recognize the original var, and make assumptions about it 
>>> */
>>>
>>>
>>> But this is far from convincing.
>>>
>>>>
>>>> My understanding is that we simply may not expose any accesses to 
>>>> per_cpu_*
>>>> variables directly to the compiler, or there's a risk that it might 
>>>> access
>>>> the "master" variable (i.e. CPU0's on at least x86).
>>>
>>> RELOC_HIDE() doesn't do anything about the correctness of the pointer
>>> arithmetic expression to make the access work.
>>>
>>> I don't see how a correct expression can ever access CPU0's data by
>>> accident.
>>
>> Hmm, upon another look I agree. I wonder whether we inherited this from
>> Linux, where in turn it may have been merely a workaround to deal with
>> preemptible code not correctly accessing per-CPU data (i.e. not
>> accounting for get_per_cpu_offset() not being stable across 
>> preemption).
>> Yet then per_cpu() would have been of similar concern when "cpu" isn't
>> properly re-fetched after any possible preemption point ...
> 
> Probably inherited with a stripped-down comment on top of RELOC_HIDE, 
> see [1]. In a way it does make sense that the compiler may decide to 
> optimize based on this assumption, though I don't know whether wrapping 
> is meant to happen with per-CPU variables.

I wouldn't call it "meant to", but wrapping certainly is possible. This
is arch-independent code, and hence whether any wrapping would occur
depends on the VA layout of the individual architectures.

Jan


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Subject: Re: [PATCH 18/22] x86/traps: Set MSR_PL0_SSP in load_system_tables()
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On 14.08.2025 21:37, Andrew Cooper wrote:
> On 14/08/2025 4:00 pm, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/boot/x86_64.S
>>> +++ b/xen/arch/x86/boot/x86_64.S
>>> @@ -65,17 +65,11 @@ ENTRY(__high_start)
>>>          or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %rdx
>>>  
>>>          /*
>>> -         * Write a new supervisor token.  Doesn't matter on boot, but for S3
>>> -         * resume this clears the busy bit.
>>> +         * Write a new Supervisor Token.  It doesn't matter the first time a
>>> +         * CPU boots, but for S3 resume or CPU hot re-add, this clears the
>>> +         * busy bit.
>>>           */
>>>          wrssq   %rdx, (%rdx)
>>> -
>>> -        /* Point MSR_PL0_SSP at the token. */
>>> -        mov     $MSR_PL0_SSP, %ecx
>>> -        mov     %edx, %eax
>>> -        shr     $32, %rdx
>>> -        wrmsr
>>> -
>>>          setssbsy
>> This is ending up a little odd: The comment says the write is to clear the
>> busy bit, when that's re-set immediately afterwards.
> 
> That comment is about the wrssq.  I suppose what isn't said is that
> setssbsy will fault if not.  How about ", so SETSSBSY can set it again" ?

That would improve things, but then it's still unclear to me why we need to
go through this. If the busy bit is already set, why clear it just to set
it again. Or perhaps asked differently: Wouldn't we be better off if we
cleared the busy bit when a CPU went offline?

Jan


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Subject: Re: [PATCH 19/22] x86/boot: Use RSTORSSP to establish SSP
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
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On 14.08.2025 22:09, Andrew Cooper wrote:
> On 14/08/2025 4:11 pm, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> Under FRED, SETSSBSY is unavailable, and we want to be setting up FRED prior
>>> to setting up shadow stacks.  As we still need Supervisor Tokens in IDT mode,
>>> we need mode-specific logic to establish SSP.
>>>
>>> In FRED mode, write a Restore Token, RSTORSSP it, and discard the resulting
>>> Previous-SSP token.
>>>
>>> No change outside of FRED mode.
>>>
>>> Signed-off-by: Andrew Cooper 
>> Why is it that in patch 17 you could use identical code, but here you can't?
> 
> This caught me out at first too.
> 
> For S3, we're going from "no shadow stack" to "back to where we were on
> an active shadow stack".  All we need to do is get saved_ssp back into
> the SSP register.
> 
> Here, we're going from "no shadow stack" to "on a good, empty, shadow
> stack".  For FRED we only need to load a value into SSP, but in IDT mode
> we must also arrange to create a busy Supervisor Token on the base of
> the stack.
> 
> We could in principle conditionally write a busy supervisor token, then
> unconditionally RSTORSSP, but that's even more complicated to follow IMO.

Why would the write need to be conditional? Can't we write what effectively
is already there? Or is it more a safety measure to avoid the write when
it's supposed to be unnecessary, to avoid papering over bugs?

>>> @@ -912,10 +913,30 @@ static void __init noreturn reinit_bsp_stack(void)
>>>  
>>>      if ( cpu_has_xen_shstk )
>>>      {
>>> -        wrmsrl(MSR_PL0_SSP,
>>> -               (unsigned long)stack + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8);
>> Does this removal perhaps belong elsewhere, especially with "No change
>> outside of FRED mode" in the description?
> 
> This is the "Updating reinit_bsp_stack() is deferred until later." note
> in the previous patch.
> 
> This hunk was illegible without the split, although I have to admit that
> I can't quite remember why now.

Hmm, if it is to stay like this, would you mind adding a respective remark
also in the description here?

Jan


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On 14.08.2025 22:55, Andrew Cooper wrote:
> On 14/08/2025 4:35 pm, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
>>> means that switch_stack_and_jump() needs to discard one extra word when FRED
>>> is active.
>>>
>>> Signed-off-by: Andrew Cooper 
>>> ---
>>> CC: Jan Beulich 
>>> CC: Roger Pau Monné 
>>>
>>> RFC.  I don't like this, but it does work.
>>>
>>> This emits opt_fred logic outside of CONFIG_XEN_SHSTK.
>> opt_fred and XEN_SHSTK are orthogonal, so that's fine anyway. What I guess
>> you may mean is that you now have a shstk-related calculation outside of
>> a respective #ifdef.
> 
> I really mean "outside of the path where shadow stacks are known to be
> active", i.e. inside the middle of SHADOW_STACK_WORK
> 
>>  Given the simplicity of the calculation, ...
>>
>>>  But frankly, the
>>> construct is already too unweildly, and all options I can think of make it
>>> moreso.
>> ... I agree having it like this is okay.
> 
> Yes, but it is a read of a global even when it's not used.
> 
> And as a tangent, we probably want __ro_after_init_read_mostly too.  The
> read mostly is about cache locality, and is applicable even to the
> __ro_after_init section.

Not really: __read_mostly is to keep stuff rarely written apart from stuff
more frequently written (cache locality, yes). There's not going to be any
frequently written data next to a __ro_after_init item; it's all r/o post-
boot. And I don't think we care much during boot.

>>> @@ -154,7 +155,6 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>>      "rdsspd %[ssp];"                                            \
>>>      "cmp $1, %[ssp];"                                           \
>>>      "je .L_shstk_done.%=;" /* CET not active?  Skip. */         \
>>> -    "mov $%c[skstk_base], %[val];"                              \
>>>      "and $%c[stack_mask], %[ssp];"                              \
>>>      "sub %[ssp], %[val];"                                       \
>>>      "shr $3, %[val];"                                           \
>> With the latter two insns here, ...
>>
>>> @@ -177,6 +177,8 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>>  
>>>  #define switch_stack_and_jump(fn, instr, constr)                        \
>>>      ({                                                                  \
>>> +        unsigned int token_offset =                                     \
>>> +            (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - (opt_fred ? 0 : 8);  \
>>>          unsigned int tmp;                                               \
>>>          BUILD_BUG_ON(!ssaj_has_attr_noreturn(fn));                      \
>>>          __asm__ __volatile__ (                                          \
>>> @@ -184,12 +186,11 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>>              "mov %[stk], %%rsp;"                                        \
>>>              CHECK_FOR_LIVEPATCH_WORK                                    \
>>>              instr "[fun]"                                               \
>>> -            : [val] "=&r" (tmp),                                        \
>>> +            : [val] "=r" (tmp),                                         \
>> ... I don't think you can legitimately drop the & from here? With it
>> retained:
>> Reviewed-by: Jan Beulich 
> 
> You chopped the bit which has an explicit input for "[val]", making the
> earlyclobber incorrect.

I was wondering whether there was a connection there, but ...

> IIRC, one version of Clang complained.

... that's not good. Without the early-clobber the asm() isn't quite
correct imo. If the same value appeared as another input, the compiler
may validly tie both together, assuming the register stays intact until
the very last insn (and hence even that last insn could still use the
register as an input). IOW if there's a Clang issue here, I think it
may need working around explicitly.

Jan


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Date: Fri, 15 Aug 2025 11:22:05 +0200
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Subject: Re: [PATCH 21/22] x86/traps: Introduce FRED entrypoints
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14.08.2025 22:40, Andrew Cooper wrote:
> On 14/08/2025 4:57 pm, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/include/asm/msr.h
>>> +++ b/xen/arch/x86/include/asm/msr.h
>>> @@ -202,9 +202,9 @@ static inline unsigned long read_gs_base(void)
>>>  
>>>  static inline unsigned long read_gs_shadow(void)
>>>  {
>>> -    unsigned long base;
>>> +    unsigned long base, cr4 = read_cr4();
>>>  
>>> -    if ( read_cr4() & X86_CR4_FSGSBASE )
>>> +    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
>>>      {
>>>          asm volatile ( "swapgs" );
>>>          base = __rdgsbase();
>>> @@ -234,7 +234,9 @@ static inline void write_gs_base(unsigned long base)
>>>  
>>>  static inline void write_gs_shadow(unsigned long base)
>>>  {
>>> -    if ( read_cr4() & X86_CR4_FSGSBASE )
>>> +    unsigned long cr4 = read_cr4();
>>> +
>>> +    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
>>>      {
>>>          asm volatile ( "swapgs\n\t"
>>>                         "wrgsbase %0\n\t"
>> I don't quite get how these changes fit into this patch.
> 
> Without the change, read_registers() suffers #UD because of the SWAPGS.
> 
> This recurses until hitting the guard page, then repeats the same on the
> #DF stack.  And because stacks work nicely under FRED, you eventually
> hit #DF's guard page.
> 
> Strictly speaking it's only read_gs_shadow() which we need to change to
> make exception handling work, but I fixed both at the same time.
> 
> That said, I have actually cleaned this codepath up with the MSR work
> because the code gen in read_registers() is terrible.  Due to
> no-strict-aliasing, every store into state-> forces a recalculation of
> get_cpu_info(), meaning that read_cr4() cannot be hoisted, and there's a
> branch in every helper.
> 
> I'm still not sure how best to fit it into this series.

Could these two hunks move to another prereq patch, then coming with its
own description?

>>> --- a/xen/arch/x86/traps.c
>>> +++ b/xen/arch/x86/traps.c
>>> @@ -1013,6 +1013,32 @@ void show_execution_state_nmi(const cpumask_t *mask, bool show_all)
>>>          printk("Non-responding CPUs: {%*pbl}\n", CPUMASK_PR(&show_state_mask));
>>>  }
>>>  
>>> +static const char *x86_et_name(unsigned int type)
>>> +{
>>> +    static const char *const names[] = {
>>> +        [X86_ET_EXT_INTR]    = "EXT_INTR",
>>> +        [X86_ET_NMI]         = "NMI",
>>> +        [X86_ET_HW_EXC]      = "HW_EXC",
>>> +        [X86_ET_SW_INT]      = "SW_INT",
>>> +        [X86_ET_PRIV_SW_EXC] = "PRIV_SW_EXEC",
>>> +        [X86_ET_SW_EXC]      = "SW_EXEC",
>>> +        [X86_ET_OTHER]       = "OTHER",
>>> +    };
>>> +
>>> +    return (type < ARRAY_SIZE(names) && names[type]) ? names[type] : "???";
>>> +}
>>> +
>>> +static const char *x86_et_other_name(unsigned int vec)
>> This isn't really a vector, is it?
> 
> Well - you are decoding the field name regs->fred_ss.vector.

Hmm, yes, the field is re-used, but I'm in trouble viewing these as vectors.
Anyway - I would prefer a rename, but I won't insist.

>>> --- a/xen/arch/x86/x86_64/Makefile
>>> +++ b/xen/arch/x86/x86_64/Makefile
>>> @@ -1,6 +1,7 @@
>>>  obj-$(CONFIG_PV32) += compat/
>>>  
>>>  obj-bin-y += entry.o
>>> +obj-bin-y += entry-fred.o
>> For the ordering here, ...
>>
>>> --- /dev/null
>>> +++ b/xen/arch/x86/x86_64/entry-fred.S
>>> @@ -0,0 +1,35 @@
>>> +/* SPDX-License-Identifier: GPL-2.0-or-later */
>>> +
>>> +        .file "x86_64/entry-fred.S"
>>> +
>>> +#include 
>>> +#include 
>>> +
>>> +        .section .text.entry, "ax", @progbits
>>> +
>>> +        /* The Ring3 entry point is required to be 4k aligned. */
>>> +
>>> +FUNC(entry_FRED_R3, 4096)
>> ... doesn't this 4k-alignment requirement suggest we want to put
>> entry-fred.o first?
> 
> Perhaps, but that is quite subtle.  I did also consider a
> .text.entry.page_aligned section, but .text.entry only matters for XPTI
> which (as agreed), I'm not intending to implement in FRED mode unless it
> proves to be necessary.
> 
> Also IIRC there's still a symbol bug where _sentrytext takes priority
> over entry_FRED_R3, so the backtrace is effectively wrong.
> 
> (These are all bad excuses, but some parts of this series are rather old.)

Are you sure this is still the case with entry_FRED_R properly typed as
functions (while _stextentry has no type)? When choosing which symbol to
display, objdump prefers typed over type-less symbols:

  /* Sort function and object symbols before global symbols before
     local symbols before section symbols before debugging symbols.  */

>>  Also, might it be more natural to use PAGE_SIZE
>> here?
> 
> I did debate that, but the spec uses 0xfff, not pages, even if the
> pipline surely does have an optimisation for chopping 12 metadata bits
> off the bottom of a pointer.

Plus pretty certainly a page boundary is meant here, no matter how things
are worded.

Jan


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Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
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 <20250814180748.2532533-1-andrew.cooper3@citrix.com>
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On 14.08.2025 20:07, Andrew Cooper wrote:
> As things stand, we set up AP/S3 exception handling marginally after the
> fragile activity of setting up shadow stacks.  Shadow stack setup is going to
> get more complicated under FRED.
> 
> Introduce percpu_early_traps_init() and call it ahead of setting up shadow
> stacks.  To start with, call load_system_tables() which is sufficient to set
> up full exception handling.
> 
> In order to handle exceptions, current and the speculation controls needs to
> work.  cpu_smpboot_alloc() already constructs some of the AP's top-of-stack
> block, so have it set up a little more.  Zero the whole structure to subsume
> other misc setup.
> 
> This gets us complete exception coverage of setting up shadow stacks, rather
> than dying with a triple fault.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 



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Subject: Re: [PATCH v2] xen: Use auto as per C23
To: Nicola Vetrini ,
 Andrew Cooper 
Cc: Xen-devel ,
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 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 15.08.2025 10:33, Nicola Vetrini wrote:
> On 2025-08-15 10:17, Andrew Cooper wrote:
>> On 15/08/2025 8:20 am, Nicola Vetrini wrote:
>>> On 2025-08-15 00:25, Andrew Cooper wrote:
>>>> In macros it is common to declare local variables using typeof(param)
>>>> in order
>>>> to ensure that side effects are only evaluated once.  A consequence
>>>> of this is
>>>> double textural expansion of the parameter, which can get out of hand
>>>> very
>>>> quickly with nested macros.
>>>>
>>>> In C23, the auto keyword has been repurposed to perform type 
>>>> inference.
>>>>
>>>> A GCC extension, __auto_type, is now avaialble in the new toolchain
>>>> baseline
>>>> and avoids the double textural expansion.
>>>>
>>>> Signed-off-by: Andrew Cooper 
>>>
>>> Reviewed-by: Nicola Vetrini 
>>
>> Thankyou.
>>
>>>>
>>>> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
>>>> index 88bf26bc5109..38ef5d82ad95 100644
>>>> --- a/xen/include/xen/compiler.h
>>>> +++ b/xen/include/xen/compiler.h
>>>> @@ -64,6 +64,20 @@
>>>>  # define asm_inline asm
>>>>  #endif
>>>>
>>>> +/*
>>>> + * In C23, the auto keyword has been repurposed to perform type
>>>> inference.
>>>> + *
>>>> + * This behaviour is available via the __auto_type extension in
>>>> supported
>>>> + * toolchains.
>>>> + *
>>>> + *
>>>> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
>>>> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
>>>> + */
>>>> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
>>>> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23
>>>> meaning. */
>>>> +#define auto __auto_type
>>>> +#endif
>>>> +
>>>
>>> A more detailed explanation should live in deviations.rst under this
>>> bullet point
>>>
>>>    * - R20.4
>>>      - The override of the keyword \"inline\" in xen/compiler.h is
>>> present so
>>>        that section contents checks pass when the compiler chooses not 
>>> to
>>>        inline a particular function.
>>>      - Comment-based deviation.
>>>
>>> as described in the SAF entry:
>>>
>>>         {
>>>             "id": "SAF-3-safe",
>>>             "analyser": {
>>>                 "eclair": "MC3A2.R20.4"
>>>             },
>>>             "name": "MC3A2.R20.4: allow the definition of a macro with
>>> the same name as a keyword in some special cases",
>>>             "text": "The definition of a macro with the same name as a
>>> keyword can be useful in certain configurations to improve the
>>> guarantees that can be provided by Xen. See docs/misra/deviations.rst
>>> for a precise rationale for all such cases."
>>>         },
>>
>> Ah right.  What about this:
>>
>> "Xen does not use the \"auto\" keyword as a storage qualifier.  The
>> override of the keyword \"auto\" in xen/compiler.h is to give it it's
>> C23 behaviour of type inference."
>>
>> ?
> 
> Seems good to me. Maybe this should be spelled out in ./CODING_STYLE as 
> well, so that newcomers don't trip over this?

I'm not sure newcomers would look there, but in the absence of any better
place that's perhaps indeed where to mention this.

I am, however, still not quite sure if we're doing ourselves a favor with
the re-purposing of auto (while not using C23 in general). It'll certainly
hit me as unexpected, for some time, to see uses of the keyword. It simply
has been for too long that it had its earlier meaning (of very limited use).

Jan


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Subject: Re: [PATCH v2] xen: rework error handling in vcpu_create
To: Jan Beulich ,
 Stewart Hildebrand 
Cc: Andrew Cooper ,
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 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Dario Faggioli , George Dunlap ,
 xen-devel@lists.xenproject.org
References: <20250801202418.38977-1-stewart.hildebrand@amd.com>
 <52ea4f10-26b4-447b-8753-0e4287a03408@suse.com>
 
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Date: Fri, 15 Aug 2025 10:51:20 +0100
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Subject: Re: [PATCH v2] xen: Use auto as per C23
To: Jan Beulich ,
 Nicola Vetrini 
Cc: Xen-devel ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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References: <20250814222524.2638883-1-andrew.cooper3@citrix.com>
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On 15/08/2025 10:36 am, Jan Beulich wrote:
> On 15.08.2025 10:33, Nicola Vetrini wrote:
>> On 2025-08-15 10:17, Andrew Cooper wrote:
>>> On 15/08/2025 8:20 am, Nicola Vetrini wrote:
>>>> On 2025-08-15 00:25, Andrew Cooper wrote:
>>>>> In macros it is common to declare local variables using typeof(param)
>>>>> in order
>>>>> to ensure that side effects are only evaluated once.  A consequence
>>>>> of this is
>>>>> double textural expansion of the parameter, which can get out of hand
>>>>> very
>>>>> quickly with nested macros.
>>>>>
>>>>> In C23, the auto keyword has been repurposed to perform type 
>>>>> inference.
>>>>>
>>>>> A GCC extension, __auto_type, is now avaialble in the new toolchain
>>>>> baseline
>>>>> and avoids the double textural expansion.
>>>>>
>>>>> Signed-off-by: Andrew Cooper 
>>>> Reviewed-by: Nicola Vetrini 
>>> Thankyou.
>>>
>>>>> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
>>>>> index 88bf26bc5109..38ef5d82ad95 100644
>>>>> --- a/xen/include/xen/compiler.h
>>>>> +++ b/xen/include/xen/compiler.h
>>>>> @@ -64,6 +64,20 @@
>>>>>  # define asm_inline asm
>>>>>  #endif
>>>>>
>>>>> +/*
>>>>> + * In C23, the auto keyword has been repurposed to perform type
>>>>> inference.
>>>>> + *
>>>>> + * This behaviour is available via the __auto_type extension in
>>>>> supported
>>>>> + * toolchains.
>>>>> + *
>>>>> + *
>>>>> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
>>>>> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
>>>>> + */
>>>>> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
>>>>> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23
>>>>> meaning. */
>>>>> +#define auto __auto_type
>>>>> +#endif
>>>>> +
>>>> A more detailed explanation should live in deviations.rst under this
>>>> bullet point
>>>>
>>>>    * - R20.4
>>>>      - The override of the keyword \"inline\" in xen/compiler.h is
>>>> present so
>>>>        that section contents checks pass when the compiler chooses not 
>>>> to
>>>>        inline a particular function.
>>>>      - Comment-based deviation.
>>>>
>>>> as described in the SAF entry:
>>>>
>>>>         {
>>>>             "id": "SAF-3-safe",
>>>>             "analyser": {
>>>>                 "eclair": "MC3A2.R20.4"
>>>>             },
>>>>             "name": "MC3A2.R20.4: allow the definition of a macro with
>>>> the same name as a keyword in some special cases",
>>>>             "text": "The definition of a macro with the same name as a
>>>> keyword can be useful in certain configurations to improve the
>>>> guarantees that can be provided by Xen. See docs/misra/deviations.rst
>>>> for a precise rationale for all such cases."
>>>>         },
>>> Ah right.  What about this:
>>>
>>> "Xen does not use the \"auto\" keyword as a storage qualifier.  The
>>> override of the keyword \"auto\" in xen/compiler.h is to give it it's
>>> C23 behaviour of type inference."
>>>
>>> ?
>> Seems good to me. Maybe this should be spelled out in ./CODING_STYLE as 
>> well, so that newcomers don't trip over this?
> I'm not sure newcomers would look there, but in the absence of any better
> place that's perhaps indeed where to mention this.

How about this:

diff --git a/CODING_STYLE b/CODING_STYLE
index 7bf3848444ad..e33b9d1170cf 100644
--- a/CODING_STYLE
+++ b/CODING_STYLE
@@ -129,6 +129,10 @@ Fixed width types should only be used when a fixed width quantity is
 meant (which for example may be a value read from or to be written to a
 register).
 
+Macros which otherwise would use "typeof(arg) newarg =" to avoid double
+evaluation of side effects should use "auto newarg =" per it's C23 behaviour,
+to also avoid double textural expansion.
+
 Especially with pointer types, whenever the pointed to object is not
 (supposed to be) modified, qualify the pointed to type with "const".



>
> I am, however, still not quite sure if we're doing ourselves a favor with
> the re-purposing of auto (while not using C23 in general). It'll certainly
> hit me as unexpected, for some time, to see uses of the keyword. It simply
> has been for too long that it had its earlier meaning (of very limited use).

I suspect that people won't find this great reasoning, but here's how I
see it.

Linux already does this, so familiarity in wider circles is growing. 
Now C23 is available, people starting new projects will be using it,
which will normalise the construct further.

People are going to be forced to get used to it, one way or another. 
They can simply choose whether it's now, or later.

Within Xen, the scope is narrow.  I am specifically not advocating that
we get it used outside of macros.

~Andrew


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From: Oleksii Kurochko 
Subject: Re: [PATCH v3 12/20] xen/riscv: implement p2m_set_range()
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
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On 8/5/25 6:04 PM, Jan Beulich wrote:
> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>> This patch introduces p2m_set_range() and its core helper p2m_set_entry() for
> Nit: This patch doesn't introduce p2m_set_range(); it merely fleshes it out.
>
>> --- a/xen/arch/riscv/include/asm/p2m.h
>> +++ b/xen/arch/riscv/include/asm/p2m.h
>> @@ -7,11 +7,13 @@
>>   #include 
>>   #include 
>>   
>> +#include 
>>   #include 
>>   
>>   extern unsigned int p2m_root_order;
>>   #define P2M_ROOT_ORDER  p2m_root_order
>>   #define P2M_ROOT_PAGES  BIT(P2M_ROOT_ORDER, U)
>> +#define P2M_ROOT_LEVEL  HYP_PT_ROOT_LEVEL
> I think I commented on this before, and I would have hoped for at least a remark
> in the description to appear (perhaps even a comment here): It's okay(ish) to tie
> these together for now, but in the longer run I don't expect this is going to be
> wanted. If e.g. we ran Xen in Sv57 mode, there would be no reason at all to force
> all P2Ms to use 5 levels of page tables.

Do you mean that for G-stage it could be chosen any SvXX mode to limit an amount
of page tables necessary for G-stage? If yes, then, at least, I agree that a
comment should be added or, probably, "#warning optimize an amount of p2m root level
for MMU mode > Sv48" (or maybe >=).

Or do you mean if we set hgatp.mode=Sv57 then it is possible to limit an amount of
page table's levels to use? In this case I think hardware still will expect to see
5 levels of page tables.


>> @@ -175,13 +179,257 @@ int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted)
>>       return 0;
>>   }
>>   
>> +/*
>> + * Find and map the root page table. The caller is responsible for
>> + * unmapping the table.
>> + *
>> + * The function will return NULL if the offset into the root table is
>> + * invalid.
>> + */
>> +static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
>> +{
>> +    unsigned long root_table_indx;
>> +
>> +    root_table_indx = gfn_x(gfn) >> XEN_PT_LEVEL_ORDER(P2M_ROOT_LEVEL);
> Right now page table layouts / arrangements are indeed similar enough to
> share accessor constructs. Nevertheless I find it problematic (doc-wise
> at the very least) that a Xen page table construct is used to access a
> P2M page table. If and when these needed to be decoupled, it would likely
> help of the distinction was already made, by - for now - simply
> introducing aliases (here e.g. P2M_LEVEL_ORDER(), expanding to
> XEN_PT_LEVEL_ORDER() for the time being).

I think it's better to define this correctly now, as I initially missed
that only non-root page tables and all page table entries (PTEs) share
the same format as their corresponding Sv39, Sv48, or Sv57 modes
(i.e., corresponding to SvXXx4).

However, in this case, we're dealing with the*root level*, which is extended
by 2 extra bits. Therefore, using|XEN_PT_LEVEL_ORDER()| would be incorrect
if those two extra bits are actually used.

We're just fortunate that no one currently uses these extra 2 bits.

>> +    if ( root_table_indx >= P2M_ROOT_PAGES )
>> +        return NULL;
>> +
>> +    return __map_domain_page(p2m->root + root_table_indx);
>> +}
>> +
>> +static inline void p2m_write_pte(pte_t *p, pte_t pte, bool clean_pte)
>> +{
>> +    write_pte(p, pte);
>> +    if ( clean_pte )
>> +        clean_dcache_va_range(p, sizeof(*p));
> Not necessarily for right away, but if multiple adjacent PTEs are
> written without releasing the lock, this then redundant cache flushing
> can be a performance issue.

Can't it be resolved on a caller side? Something like:
   p2m_write_pte(p1, pte1, false);
   p2m_write_pte(p2, pte2, false);
   p2m_write_pte(p3, pte3, false);
   p2m_write_pte(p4, pte4, true);
where p1-p4 are adjacent.

  

>> +}
>> +
>> +static inline void p2m_clean_pte(pte_t *p, bool clean_pte)
>> +{
>> +    pte_t pte;
>> +
>> +    memset(&pte, 0, sizeof(pte));
> Why memset()? Why not simply give the variable an appropriate initializer?

Good point. It would be much better just to use an appropriate initializer.

> Or use ...
>
>> +    p2m_write_pte(p, pte, clean_pte);
> ... a compound literal here, like you do ...
>
>> +}
>> +
>> +static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t)
>> +{
>> +    panic("%s: hasn't been implemented yet\n", __func__);
>> +
>> +    return (pte_t) { .pte = 0 };
> ... here? (Just {} would also do, if I'm not mistaken.)

According to C99 it will be enough {}, but {.pte = 0} is more obvious and
clearer, IMO.

>> +}
>> +
>> +#define P2M_TABLE_MAP_NONE 0
>> +#define P2M_TABLE_MAP_NOMEM 1
>> +#define P2M_TABLE_SUPER_PAGE 2
>> +#define P2M_TABLE_NORMAL 3
>> +
>> +/*
>> + * Take the currently mapped table, find the corresponding the entry
>> + * corresponding to the GFN, and map the next table, if available.
> Nit: Double "corresponding".
>
>> + * The previous table will be unmapped if the next level was mapped
>> + * (e.g P2M_TABLE_NORMAL returned).
>> + *
>> + * `alloc_tbl` parameter indicates whether intermediate tables should
>> + * be allocated when not present.
>> + *
>> + * Return values:
>> + *  P2M_TABLE_MAP_NONE: a table allocation isn't permitted.
>> + *  P2M_TABLE_MAP_NOMEM: allocating a new page failed.
>> + *  P2M_TABLE_SUPER_PAGE: next level or leaf mapped normally.
>> + *  P2M_TABLE_NORMAL: The next entry points to a superpage.
>> + */
>> +static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl,
>> +                          unsigned int level, pte_t **table,
>> +                          unsigned int offset)
>> +{
>> +    panic("%s: hasn't been implemented yet\n", __func__);
>> +
>> +    return P2M_TABLE_MAP_NONE;
>> +}
>> +
>> +/* Free pte sub-tree behind an entry */
>> +static void p2m_free_subtree(struct p2m_domain *p2m,
>> +                             pte_t entry, unsigned int level)
>> +{
>> +    panic("%s: hasn't been implemented yet\n", __func__);
>> +}
>> +
>> +/*
>> + * Insert an entry in the p2m. This should be called with a mapping
>> + * equal to a page/superpage.
>> + */
>> +static int p2m_set_entry(struct p2m_domain *p2m,
>> +                           gfn_t gfn,
>> +                           unsigned long page_order,
>> +                           mfn_t mfn,
>> +                           p2m_type_t t)
>> +{
>> +    unsigned int level;
>> +    unsigned int target = page_order / PAGETABLE_ORDER;
>> +    pte_t *entry, *table, orig_pte;
>> +    int rc;
>> +    /* A mapping is removed if the MFN is invalid. */
>> +    bool removing_mapping = mfn_eq(mfn, INVALID_MFN);
> Comment and code don't fit together. Many MFNs are invalid (any for which
> mfn_valid() returns false), yet you only check for INVALID_MFN here.

Probably, it makes sense to add an|ASSERT()| here for the case when
|mfn_valid(mfn)| is false, but the MFN is not explicitly equal to|INVALID_MFN|.
This would indicate that someone attempted to perform a mapping with an
incorrect MFN, which, IMO, is entirely wrong.
In the case where the MFN is explicitly set to|INVALID_MFN|, I believe it's
enough to indicate that a mapping is being removed.

>> +    DECLARE_OFFSETS(offsets, gfn_to_gaddr(gfn));
>> +
>> +    ASSERT(p2m_is_write_locked(p2m));
>> +
>> +    /*
>> +     * Check if the level target is valid: we only support
>> +     * 4K - 2M - 1G mapping.
>> +     */
>> +    ASSERT((target <= 2) && !(page_order % PAGETABLE_ORDER));
> If you think you need to check this, don't you also want to check that
> GFN and MFN (the latter if it isn't INVALID_MFN) fit the requested order?

I'm not 100% sure it makes sense to check|page_order|, as in IMO, proper
alignment is already guaranteed by|p2m_mapping_order(sgfn, smfn, left)|,
and thus both GFN and MFN are aligned accordingly.
So, I think this part of the check could be dropped.

>> +    table = p2m_get_root_pointer(p2m, gfn);
>> +    if ( !table )
>> +        return -EINVAL;
>> +
>> +    for ( level = P2M_ROOT_LEVEL; level > target; level-- )
>> +    {
>> +        /*
>> +         * Don't try to allocate intermediate page table if the mapping
>> +         * is about to be removed.
>> +         */
>> +        rc = p2m_next_level(p2m, !removing_mapping,
>> +                            level, &table, offsets[level]);
>> +        if ( (rc == P2M_TABLE_MAP_NONE) || (rc == P2M_TABLE_MAP_NOMEM) )
>> +        {
>> +            rc = (rc == P2M_TABLE_MAP_NONE) ? -ENOENT : -ENOMEM;
>> +            /*
>> +             * We are here because p2m_next_level has failed to map
>> +             * the intermediate page table (e.g the table does not exist
>> +             * and they p2m tree is read-only). It is a valid case
>> +             * when removing a mapping as it may not exist in the
>> +             * page table. In this case, just ignore it.
>> +             */
>> +            rc = removing_mapping ?  0 : rc;
> Nit: Stray blank.
>
>> +            goto out;
>> +        }
>> +
>> +        if ( rc != P2M_TABLE_NORMAL )
>> +            break;
>> +    }
>> +
>> +    entry = table + offsets[level];
>> +
>> +    /*
>> +     * If we are here with level > target, we must be at a leaf node,
>> +     * and we need to break up the superpage.
>> +     */
>> +    if ( level > target )
>> +    {
>> +        panic("Shattering isn't implemented\n");
>> +    }
>> +
>> +    /*
>> +     * We should always be there with the correct level because all the
>> +     * intermediate tables have been installed if necessary.
>> +     */
>> +    ASSERT(level == target);
>> +
>> +    orig_pte = *entry;
>> +
>> +    if ( removing_mapping )
>> +        p2m_clean_pte(entry, p2m->clean_pte);
>> +    else
>> +    {
>> +        pte_t pte = p2m_pte_from_mfn(mfn, t);
>> +
>> +        p2m_write_pte(entry, pte, p2m->clean_pte);
>> +
>> +        p2m->max_mapped_gfn = gfn_max(p2m->max_mapped_gfn,
>> +                                      gfn_add(gfn, BIT(page_order, UL) - 1));
>> +        p2m->lowest_mapped_gfn = gfn_min(p2m->lowest_mapped_gfn, gfn);
>> +    }
>> +
>> +    p2m->need_flush = true;
>> +
>> +    /*
>> +     * Currently, the infrastructure required to enable CONFIG_HAS_PASSTHROUGH
>> +     * is not ready for RISC-V support.
>> +     *
>> +     * When CONFIG_HAS_PASSTHROUGH=y, iommu_iotlb_flush() should be done
>> +     * here.
>> +     */
>> +#ifdef CONFIG_HAS_PASSTHROUGH
>> +#   error "add code to flush IOMMU TLB"
>> +#endif
>> +
>> +    rc = 0;
>> +
>> +    /*
>> +     * Free the entry only if the original pte was valid and the base
>> +     * is different (to avoid freeing when permission is changed).
>> +     */
>> +    if ( pte_is_valid(orig_pte) &&
>> +         !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) )
> I'm puzzled by this 2nd check: A permission change would - I expect - only
> occur to a leaf entry. If the new entry is a super-page one and the old
> wasn't, don't you still need to free the sub-tree, no matter whether the
> MFNs are the same?

I expect the MFNs to differ in this scenario, so the old sub-tree will be freed.

Based on your example (new entry is super-page and old entry isn't):
For old mapping (lets say, 4 KiB leaf) p2m_set_entry() walks all levels down
to L0, so we will have the following MMU page table walks:
   L2 PTE -> L1 PTE (MFN of L0 page table) -> L0 PTE -> RAM

When new mapping (lets say, 2 MiB superpage) will be requested, p2m_set_entry()
will stop at L1 (the superpage level):
  L2 PTE -> L1 PTE (at this moment, L1 PTE points to L0 page table, which
                    points to RAM)
Then the old L1 PTE will be saved in 'orig_pte', then writes 'entry' with
the RAM MFN for the 2 MiB mapping. The walk becomes:
   L2 PTE -> L1 PTE -> RAM

Therefore, 'entry' now holds an MFN pointing to RAM (superpage leaf). 'orig_pte'
still holds an MFN pointing to the L0 table (the old sub-tree). Since these MFNs
differ, the code calls p2m_free_subtree(p2m, orig_pte, …) and frees the old L0
sub-tree.

     

>   Plus consider the special case of MFN 0: If you clear
> an entry using MFN 0, you will find old and new PTEs' both having the same
> MFN.

Isn't this happen only when a mapping removal is explicitly requested?
In the case of a mapping removal it seems to me it is enough just to
clear PTE with all zeroes.

>   static int p2m_set_range(struct p2m_domain *p2m,
>                            gfn_t sgfn,
>                            unsigned long nr,
>                            mfn_t smfn,
>                            p2m_type_t t)
>   {
> -    return -EOPNOTSUPP;
> +    int rc = 0;
> +    unsigned long left = nr;
> +
> +    /*
> +     * Any reference taken by the P2M mappings (e.g. foreign mapping) will
> +     * be dropped in relinquish_p2m_mapping(). As the P2M will still
> +     * be accessible after, we need to prevent mapping to be added when the
> +     * domain is dying.
> +     */
> +    if ( unlikely(p2m->domain->is_dying) )
> +        return -EACCES;
> +
> +    while ( left )
> +    {
> +        unsigned long order = p2m_mapping_order(sgfn, smfn, left);
> +
> +        rc = p2m_set_entry(p2m, sgfn, order, smfn, t);
> +        if ( rc )
> +            break;
> +
> +        sgfn = gfn_add(sgfn, BIT(order, UL));
> +        if ( !mfn_eq(smfn, INVALID_MFN) )
> +           smfn = mfn_add(smfn, BIT(order, UL));
> +
> +        left -= BIT(order, UL);
> +    }
> +
> +    return !left ? 0 : left == nr ? rc : (nr - left);
> The function returning "int", you may be truncating the return value here.
> In the worst case indicating success (0) or an error (negative) when some
> of the upper bits were set.

I think what will be better:
or (1) Return long instead of int and the following check:
    long result = nr - left;
    if (result < 0 || result > LONG_MAX)
       return -ERANGE;
or (2) Just add new `left_to_map` (or just left) argument to p2m_set_range().

> Also looks like you could get away with a single conditional operator here:
>
>      return !left || left == nr ? rc : (nr - left);

Thanks.

~ Oleksii

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    On 8/5/25 6:04 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
      
    
        
    This patch introduces p2m_set_range() and its core helper p2m_set_entry() for

    
      
    
      
    Nit: This patch doesn't introduce p2m_set_range(); it merely fleshes it out.


    
      
    
        
    --- a/xen/arch/riscv/include/asm/p2m.h
+++ b/xen/arch/riscv/include/asm/p2m.h
@@ -7,11 +7,13 @@
 #include <xen/rwlock.h>
 #include <xen/types.h>
 
+#include <asm/page.h>
 #include <asm/page-bits.h>
 
 extern unsigned int p2m_root_order;
 #define P2M_ROOT_ORDER  p2m_root_order
 #define P2M_ROOT_PAGES  BIT(P2M_ROOT_ORDER, U)
+#define P2M_ROOT_LEVEL  HYP_PT_ROOT_LEVEL

    
      
    
      
    I think I commented on this before, and I would have hoped for at least a remark
in the description to appear (perhaps even a comment here): It's okay(ish) to tie
these together for now, but in the longer run I don't expect this is going to be
wanted. If e.g. we ran Xen in Sv57 mode, there would be no reason at all to force
all P2Ms to use 5 levels of page tables.
    
    
    
    
    Do you mean that for G-stage it could be chosen any SvXX mode to limit an amount
of page tables necessary for G-stage? If yes, then, at least, I agree that a
comment should be added or, probably, "#warning optimize an amount of p2m root level
for MMU mode > Sv48" (or maybe >=).

Or do you mean if we set hgatp.mode=Sv57 then it is possible to limit an amount of
page table's levels to use? In this case I think hardware still will expect to see
5 levels of page tables.



    
    
    
      
    
        
    @@ -175,13 +179,257 @@ int p2m_set_allocation(struct domain *d, unsigned long pages, bool *preempted)
     return 0;
 }
 
+/*
+ * Find and map the root page table. The caller is responsible for
+ * unmapping the table.
+ *
+ * The function will return NULL if the offset into the root table is
+ * invalid.
+ */
+static pte_t *p2m_get_root_pointer(struct p2m_domain *p2m, gfn_t gfn)
+{
+    unsigned long root_table_indx;
+
+    root_table_indx = gfn_x(gfn) >> XEN_PT_LEVEL_ORDER(P2M_ROOT_LEVEL);

    
      
    
      
    Right now page table layouts / arrangements are indeed similar enough to
share accessor constructs. Nevertheless I find it problematic (doc-wise
at the very least) that a Xen page table construct is used to access a
P2M page table. If and when these needed to be decoupled, it would likely
help of the distinction was already made, by - for now - simply
introducing aliases (here e.g. P2M_LEVEL_ORDER(), expanding to
XEN_PT_LEVEL_ORDER() for the time being).
    
    
    
    
    I think it's better to define this correctly now, as I initially missed
that only non-root page tables and all page table entries (PTEs) share
the same format as their corresponding Sv39, Sv48, or Sv57 modes
(i.e., corresponding to SvXXx4).
    
    
    However, in this case, we're dealing with the root level, which is extended
by 2 extra bits. Therefore, using XEN_PT_LEVEL_ORDER() would be incorrect
if those two extra bits are actually used.
    
    
    We're just fortunate that no one currently uses these extra 2 bits.

    
    
    
      
    
        
    +    if ( root_table_indx >= P2M_ROOT_PAGES )
+        return NULL;
+
+    return __map_domain_page(p2m->root + root_table_indx);
+}
+
+static inline void p2m_write_pte(pte_t *p, pte_t pte, bool clean_pte)
+{
+    write_pte(p, pte);
+    if ( clean_pte )
+        clean_dcache_va_range(p, sizeof(*p));

    
      
    
      
    Not necessarily for right away, but if multiple adjacent PTEs are
written without releasing the lock, this then redundant cache flushing
can be a performance issue.
    
    
    
    
    Can't it be resolved on a caller side? Something like:
  p2m_write_pte(p1, pte1, false);
  p2m_write_pte(p2, pte2, false);
  p2m_write_pte(p3, pte3, false);
  p2m_write_pte(p4, pte4, true);
where p1-p4 are adjacent.

 

    
    
    
      
    
        
    +}
+
+static inline void p2m_clean_pte(pte_t *p, bool clean_pte)
+{
+    pte_t pte;
+
+    memset(&pte, 0, sizeof(pte));

    
      
    
      
    Why memset()? Why not simply give the variable an appropriate initializer?
    
    
    
    
    Good point. It would be much better just to use an appropriate initializer.


    
    
    
      
    Or use ...


    
      
    
        
    +    p2m_write_pte(p, pte, clean_pte);

    
      
    
      
    ... a compound literal here, like you do ...


    
      
    
        
    +}
+
+static pte_t p2m_pte_from_mfn(mfn_t mfn, p2m_type_t t)
+{
+    panic("%s: hasn't been implemented yet\n", __func__);
+
+    return (pte_t) { .pte = 0 };

    
      
    
      
    ... here? (Just {} would also do, if I'm not mistaken.)
    
    
    
    
    According to C99 it will be enough {}, but {.pte = 0} is more obvious and
clearer, IMO.


    
    
    
      
    
        
    +}
+
+#define P2M_TABLE_MAP_NONE 0
+#define P2M_TABLE_MAP_NOMEM 1
+#define P2M_TABLE_SUPER_PAGE 2
+#define P2M_TABLE_NORMAL 3
+
+/*
+ * Take the currently mapped table, find the corresponding the entry
+ * corresponding to the GFN, and map the next table, if available.

    
      
    
      
    Nit: Double "corresponding".


    
      
    
        
    + * The previous table will be unmapped if the next level was mapped
+ * (e.g P2M_TABLE_NORMAL returned).
+ *
+ * `alloc_tbl` parameter indicates whether intermediate tables should
+ * be allocated when not present.
+ *
+ * Return values:
+ *  P2M_TABLE_MAP_NONE: a table allocation isn't permitted.
+ *  P2M_TABLE_MAP_NOMEM: allocating a new page failed.
+ *  P2M_TABLE_SUPER_PAGE: next level or leaf mapped normally.
+ *  P2M_TABLE_NORMAL: The next entry points to a superpage.
+ */
+static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl,
+                          unsigned int level, pte_t **table,
+                          unsigned int offset)
+{
+    panic("%s: hasn't been implemented yet\n", __func__);
+
+    return P2M_TABLE_MAP_NONE;
+}
+
+/* Free pte sub-tree behind an entry */
+static void p2m_free_subtree(struct p2m_domain *p2m,
+                             pte_t entry, unsigned int level)
+{
+    panic("%s: hasn't been implemented yet\n", __func__);
+}
+
+/*
+ * Insert an entry in the p2m. This should be called with a mapping
+ * equal to a page/superpage.
+ */
+static int p2m_set_entry(struct p2m_domain *p2m,
+                           gfn_t gfn,
+                           unsigned long page_order,
+                           mfn_t mfn,
+                           p2m_type_t t)
+{
+    unsigned int level;
+    unsigned int target = page_order / PAGETABLE_ORDER;
+    pte_t *entry, *table, orig_pte;
+    int rc;
+    /* A mapping is removed if the MFN is invalid. */
+    bool removing_mapping = mfn_eq(mfn, INVALID_MFN);

    
      
    
      
    Comment and code don't fit together. Many MFNs are invalid (any for which
mfn_valid() returns false), yet you only check for INVALID_MFN here.
    
    
    
    
    Probably, it makes sense to add an ASSERT() here for the case when
mfn_valid(mfn) is false, but the MFN is not explicitly equal to INVALID_MFN.
This would indicate that someone attempted to perform a mapping with an
incorrect MFN, which, IMO, is entirely wrong.
In the case where the MFN is explicitly set to INVALID_MFN, I believe it's
enough to indicate that a mapping is being removed.


    
    
    
      
    
        
    +    DECLARE_OFFSETS(offsets, gfn_to_gaddr(gfn));
+
+    ASSERT(p2m_is_write_locked(p2m));
+
+    /*
+     * Check if the level target is valid: we only support
+     * 4K - 2M - 1G mapping.
+     */
+    ASSERT((target <= 2) && !(page_order % PAGETABLE_ORDER));

    
      
    
      
    If you think you need to check this, don't you also want to check that
GFN and MFN (the latter if it isn't INVALID_MFN) fit the requested order?
    
    
    
    
    I'm not 100% sure it makes sense to check page_order, as in IMO, proper
alignment is already guaranteed by p2m_mapping_order(sgfn, smfn, left),
and thus both GFN and MFN are aligned accordingly.
So, I think this part of the check could be dropped.
    
    
    
      
    
        
    +    table = p2m_get_root_pointer(p2m, gfn);
+    if ( !table )
+        return -EINVAL;
+
+    for ( level = P2M_ROOT_LEVEL; level > target; level-- )
+    {
+        /*
+         * Don't try to allocate intermediate page table if the mapping
+         * is about to be removed.
+         */
+        rc = p2m_next_level(p2m, !removing_mapping,
+                            level, &table, offsets[level]);
+        if ( (rc == P2M_TABLE_MAP_NONE) || (rc == P2M_TABLE_MAP_NOMEM) )
+        {
+            rc = (rc == P2M_TABLE_MAP_NONE) ? -ENOENT : -ENOMEM;
+            /*
+             * We are here because p2m_next_level has failed to map
+             * the intermediate page table (e.g the table does not exist
+             * and they p2m tree is read-only). It is a valid case
+             * when removing a mapping as it may not exist in the
+             * page table. In this case, just ignore it.
+             */
+            rc = removing_mapping ?  0 : rc;

    
      
    
      
    Nit: Stray blank.


    
      
    
        
    +            goto out;
+        }
+
+        if ( rc != P2M_TABLE_NORMAL )
+            break;
+    }
+
+    entry = table + offsets[level];
+
+    /*
+     * If we are here with level > target, we must be at a leaf node,
+     * and we need to break up the superpage.
+     */
+    if ( level > target )
+    {
+        panic("Shattering isn't implemented\n");
+    }
+
+    /*
+     * We should always be there with the correct level because all the
+     * intermediate tables have been installed if necessary.
+     */
+    ASSERT(level == target);
+
+    orig_pte = *entry;
+
+    if ( removing_mapping )
+        p2m_clean_pte(entry, p2m->clean_pte);
+    else
+    {
+        pte_t pte = p2m_pte_from_mfn(mfn, t);
+
+        p2m_write_pte(entry, pte, p2m->clean_pte);
+
+        p2m->max_mapped_gfn = gfn_max(p2m->max_mapped_gfn,
+                                      gfn_add(gfn, BIT(page_order, UL) - 1));
+        p2m->lowest_mapped_gfn = gfn_min(p2m->lowest_mapped_gfn, gfn);
+    }
+
+    p2m->need_flush = true;
+
+    /*
+     * Currently, the infrastructure required to enable CONFIG_HAS_PASSTHROUGH
+     * is not ready for RISC-V support.
+     *
+     * When CONFIG_HAS_PASSTHROUGH=y, iommu_iotlb_flush() should be done
+     * here.
+     */
+#ifdef CONFIG_HAS_PASSTHROUGH
+#   error "add code to flush IOMMU TLB"
+#endif
+
+    rc = 0;
+
+    /*
+     * Free the entry only if the original pte was valid and the base
+     * is different (to avoid freeing when permission is changed).
+     */
+    if ( pte_is_valid(orig_pte) &&
+         !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) )

    
      
    
      
    I'm puzzled by this 2nd check: A permission change would - I expect - only
occur to a leaf entry. If the new entry is a super-page one and the old
wasn't, don't you still need to free the sub-tree, no matter whether the
MFNs are the same?
    
    
    
    
    I expect the MFNs to differ in this scenario, so the old sub-tree will be freed.

Based on your example (new entry is super-page and old entry isn't):
For old mapping (lets say, 4 KiB leaf) p2m_set_entry() walks all levels down
to L0, so we will have the following MMU page table walks:
  L2 PTE -> L1 PTE (MFN of L0 page table) -> L0 PTE -> RAM

When new mapping (lets say, 2 MiB superpage) will be requested, p2m_set_entry()
will stop at L1 (the superpage level):
 L2 PTE -> L1 PTE (at this moment, L1 PTE points to L0 page table, which
                   points to RAM)
Then the old L1 PTE will be saved in 'orig_pte', then writes 'entry' with
the RAM MFN for the 2 MiB mapping. The walk becomes:
  L2 PTE -> L1 PTE -> RAM

Therefore, 'entry' now holds an MFN pointing to RAM (superpage leaf). 'orig_pte'
still holds an MFN pointing to the L0 table (the old sub-tree). Since these MFNs
differ, the code calls p2m_free_subtree(p2m, orig_pte, …) and frees the old L0
sub-tree.
    
    
        
    
    
    
      
     Plus consider the special case of MFN 0: If you clear
an entry using MFN 0, you will find old and new PTEs' both having the same
MFN.
    
    
    
    
    Isn't this happen only when a mapping removal is explicitly requested?
In the case of a mapping removal it seems to me it is enough just to
clear PTE with all zeroes.


    
    
    
      
     static int p2m_set_range(struct p2m_domain *p2m,
                          gfn_t sgfn,
                          unsigned long nr,
                          mfn_t smfn,
                          p2m_type_t t)
 {
-    return -EOPNOTSUPP;
+    int rc = 0;
+    unsigned long left = nr;
+
+    /*
+     * Any reference taken by the P2M mappings (e.g. foreign mapping) will
+     * be dropped in relinquish_p2m_mapping(). As the P2M will still
+     * be accessible after, we need to prevent mapping to be added when the
+     * domain is dying.
+     */
+    if ( unlikely(p2m->domain->is_dying) )
+        return -EACCES;
+
+    while ( left )
+    {
+        unsigned long order = p2m_mapping_order(sgfn, smfn, left);
+
+        rc = p2m_set_entry(p2m, sgfn, order, smfn, t);
+        if ( rc )
+            break;
+
+        sgfn = gfn_add(sgfn, BIT(order, UL));
+        if ( !mfn_eq(smfn, INVALID_MFN) )
+           smfn = mfn_add(smfn, BIT(order, UL));
+
+        left -= BIT(order, UL);
+    }
+
+    return !left ? 0 : left == nr ? rc : (nr - left);

    
    
    
    
    
      
     
    
      
    The function returning "int", you may be truncating the return value here.
In the worst case indicating success (0) or an error (negative) when some
of the upper bits were set.
    
    
    
    
    I think what will be better:
or (1) Return long instead of int and the following check:
   long result = nr - left;
   if (result < 0 || result > LONG_MAX)
      return -ERANGE;
or (2) Just add new `left_to_map` (or just left) argument to p2m_set_range().


    
    
    
      
    Also looks like you could get away with a single conditional operator here:

    return !left || left == nr ? rc : (nr - left);
    
    
    
    
    Thanks. 

~ Oleksii
    
  


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To: "xen-devel@lists.xenproject.org" 
CC: Jan Beulich , Andrew Cooper
	, =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: [PATCH] x86/hvm/ioreq: Fix condition in hvm_alloc_legacy_ioreq_gfn()
Thread-Topic: [PATCH] x86/hvm/ioreq: Fix condition in
 hvm_alloc_legacy_ioreq_gfn()
Thread-Index: AQHcDc4g80PGAKCUYEOWQIOrbWg9cg==
Date: Fri, 15 Aug 2025 10:19:47 +0000
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Fix the incorrect condition that causes hvm_alloc_legacy_ioreq_gfn()
to return INVALID_GFN even if the HVM param was installed properly by
the toolstack.

Fixes: 3486f398a3dd (' x86/hvm/ioreq: allow ioreq servers to use HVM_PARAM_=
[BUF]IOREQ_PFN')
Signed-off-by: Oleksandr Tyshchenko 
---
When playing with the XEN_DMOP_get_ioreq_server_info sub-op, I noticed weir=
d
behavior where the hypercall returned success only the second time.
---
---
 xen/arch/x86/hvm/ioreq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c
index ec709e5f47..4d30f2d730 100644
--- a/xen/arch/x86/hvm/ioreq.c
+++ b/xen/arch/x86/hvm/ioreq.c
@@ -63,7 +63,7 @@ static gfn_t hvm_alloc_legacy_ioreq_gfn(struct ioreq_serv=
er *s)
=20
     for ( i =3D HVM_PARAM_IOREQ_PFN; i <=3D HVM_PARAM_BUFIOREQ_PFN; i++ )
     {
-        if ( !test_and_clear_bit(i, &d->arch.hvm.ioreq_gfn.legacy_mask) )
+        if ( test_and_clear_bit(i, &d->arch.hvm.ioreq_gfn.legacy_mask) )
             return _gfn(d->arch.hvm.params[i]);
     }
=20
--=20
2.34.1


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Feedback-ID: iff35298b:Fastmail
From: Sergiy Kibrik 
To: xen-devel@lists.xenproject.org
Cc: Sergiy Kibrik ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	"Daniel P. Smith" ,
	Stefano Stabellini 
Subject: [RFC PATCH] xsm/flask: add AVC pre-allocation boot parameter
Date: Fri, 15 Aug 2025 13:23:30 +0300
Message-Id: <20250815102330.778749-1-Sergiy_Kibrik@epam.com>
X-Mailer: git-send-email 2.25.1
MIME-Version: 1.0
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In the system configured for safety it may not be desirable to do guest-triggered
dynamic memory allocations at runtime, or allow changing memory layout by
adjusting AVC size after boot.
This patch introduces `avc_prealloc` boot parameter that enables allocation of
AVC nodes in advance so that no Xen heap allocations take place at runtime.

In case when pre-allocated cache is exhausted the reclaim of old nodes is
started, just as before, but no new node added to cache while cache is full.
AV is computed and returned to requester, but not cached during the reclaim.
So there's some performance penalty here.

Signed-off-by: Sergiy Kibrik 
---
This RFC presents one possible way to hard limit the memory AVC can consume.
With current implementation of AV cache threshold reclaim of memory only starts
after threshold has been reached, and we only reclaim up to AVC_CACHE_RECLAIM=16
nodes at a time.
As allocation of new nodes is always allowed, in a hypothetical situation of
great AVC pressure when more then AVC_CACHE_RECLAIM new nodes are quickly
requested while reclaim is still in progress, it won't be possible to decrease
allocation below threshold.
Does this scenario make sense? Or is there a better way to address it? Thank you!

  -Sergiy
---
 docs/misc/xen-command-line.pandoc |  9 +++++++
 xen/xsm/flask/avc.c               | 44 ++++++++++++++++++++++++++-----
 xen/xsm/flask/flask_op.c          |  3 +++
 xen/xsm/flask/include/avc.h       |  2 ++
 4 files changed, 52 insertions(+), 6 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index a75b6c9301..9044827e78 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -238,6 +238,15 @@ loops for Queued Invalidation completions.**
 Specify a maximum amount of available memory, to which Xen will clamp
 the e820 table.
 
+### avc_prealloc
+> `= `
+
+> Default: `false`
+
+Allocate XSM Access Vector Cache at boot. This forbids runtime dynamic
+allocation of AVC nodes from Xen heap and changing AVC size via
+FLASK_SETAVC_THRESHOLD hypercall.
+
 ### badpage
 > `= List of [  | - ]`
 
diff --git a/xen/xsm/flask/avc.c b/xen/xsm/flask/avc.c
index 3d39e55cae..19e524fe35 100644
--- a/xen/xsm/flask/avc.c
+++ b/xen/xsm/flask/avc.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -84,6 +85,7 @@ struct avc_cache {
     atomic_t        lru_hint;    /* LRU hint for reclaim scan */
     atomic_t        active_nodes;
     u32            latest_notif;    /* latest revocation notification */
+    struct hlist_head freelist;
 };
 
 /* Exported via Flask hypercall */
@@ -97,6 +99,9 @@ static struct avc_cache avc_cache;
 
 static DEFINE_RCU_READ_LOCK(avc_rcu_lock);
 
+bool __read_mostly opt_avc_prealloc = false;
+boolean_param("avc_prealloc", opt_avc_prealloc);
+
 static inline int avc_hash(u32 ssid, u32 tsid, u16 tclass)
 {
     return (ssid ^ (tsid<<2) ^ (tclass<<4)) & (AVC_CACHE_SLOTS - 1);
@@ -239,6 +244,16 @@ void __init avc_init(void)
     }
     atomic_set(&avc_cache.active_nodes, 0);
     atomic_set(&avc_cache.lru_hint, 0);
+    INIT_HLIST_HEAD(&avc_cache.freelist);
+    for ( i = 0; opt_avc_prealloc && i < avc_cache_threshold + 1; i++ )
+    {
+        struct avc_node *node = xzalloc(struct avc_node);
+        if ( !node )
+        {
+            break;
+        }
+        hlist_add_head(&node->list, &avc_cache.freelist);
+    }
 }
 
 int avc_get_hash_stats(struct xen_flask_hash_stats *arg)
@@ -280,7 +295,10 @@ int avc_get_hash_stats(struct xen_flask_hash_stats *arg)
 static void cf_check avc_node_free(struct rcu_head *rhead)
 {
     struct avc_node *node = container_of(rhead, struct avc_node, rhead);
-    xfree(node);
+    if ( opt_avc_prealloc )
+        hlist_add_head(&node->list, &avc_cache.freelist);
+    else
+        xfree(node);
     avc_cache_stats_incr(frees);
 }
 
@@ -293,7 +311,10 @@ static void avc_node_delete(struct avc_node *node)
 
 static void avc_node_kill(struct avc_node *node)
 {
-    xfree(node);
+    if ( opt_avc_prealloc )
+        hlist_add_head(&node->list, &avc_cache.freelist);
+    else
+        xfree(node);
     avc_cache_stats_incr(frees);
     atomic_dec(&avc_cache.active_nodes);
 }
@@ -344,11 +365,22 @@ static inline int avc_reclaim_node(void)
 
 static struct avc_node *avc_alloc_node(void)
 {
-    struct avc_node *node;
+    struct avc_node *node = NULL;
 
-    node = xzalloc(struct avc_node);
-    if (!node)
-        goto out;
+    if ( opt_avc_prealloc )
+    {
+        if ( hlist_empty(&avc_cache.freelist) )
+            goto out;
+
+        node = hlist_entry(avc_cache.freelist.first, struct avc_node, list);
+        hlist_del(&node->list);
+    }
+    else
+    {
+        node = xzalloc(struct avc_node);
+        if ( !node )
+            goto out;
+    }
 
     INIT_RCU_HEAD(&node->rhead);
     INIT_HLIST_NODE(&node->list);
diff --git a/xen/xsm/flask/flask_op.c b/xen/xsm/flask/flask_op.c
index ea7dd10dc8..5415a696a0 100644
--- a/xen/xsm/flask/flask_op.c
+++ b/xen/xsm/flask/flask_op.c
@@ -226,6 +226,9 @@ static int flask_security_setavc_threshold(
 {
     int rv = 0;
 
+    if ( opt_avc_prealloc )
+        return -EACCES;
+
     if ( arg->threshold != avc_cache_threshold )
     {
         rv = domain_has_security(current->domain, SECURITY__SETSECPARAM);
diff --git a/xen/xsm/flask/include/avc.h b/xen/xsm/flask/include/avc.h
index e29949f5a8..d6122f3dc9 100644
--- a/xen/xsm/flask/include/avc.h
+++ b/xen/xsm/flask/include/avc.h
@@ -95,6 +95,8 @@ int avc_has_perm(u32 ssid, u32 tsid, u16 tclass, u32 requested,
 struct xen_flask_hash_stats;
 int avc_get_hash_stats(struct xen_flask_hash_stats *arg);
 extern unsigned int avc_cache_threshold;
+/* pre-allocate AVC at boot and forbid SETAVC_THRESHOLD flask_op */
+extern bool opt_avc_prealloc;
 
 #ifdef CONFIG_XSM_FLASK_AVC_STATS
 DECLARE_PER_CPU(struct avc_cache_stats, avc_cache_stats);
-- 
2.25.1



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Date: Fri, 15 Aug 2025 12:25:52 +0200
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Subject: Re: [PATCH v2] xen: Use auto as per C23
To: Andrew Cooper 
Cc: Xen-devel ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Roberto Bagnara ,
 "consulting @ bugseng . com" ,
 Nicola Vetrini 
References: <20250814222524.2638883-1-andrew.cooper3@citrix.com>
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 <7fc93aeef27153f1d6caa786bd44420f@bugseng.com>
 
 
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On 15.08.2025 11:51, Andrew Cooper wrote:
> On 15/08/2025 10:36 am, Jan Beulich wrote:
>> On 15.08.2025 10:33, Nicola Vetrini wrote:
>>> On 2025-08-15 10:17, Andrew Cooper wrote:
>>>> On 15/08/2025 8:20 am, Nicola Vetrini wrote:
>>>>> On 2025-08-15 00:25, Andrew Cooper wrote:
>>>>>> In macros it is common to declare local variables using typeof(param)
>>>>>> in order
>>>>>> to ensure that side effects are only evaluated once.  A consequence
>>>>>> of this is
>>>>>> double textural expansion of the parameter, which can get out of hand
>>>>>> very
>>>>>> quickly with nested macros.
>>>>>>
>>>>>> In C23, the auto keyword has been repurposed to perform type 
>>>>>> inference.
>>>>>>
>>>>>> A GCC extension, __auto_type, is now avaialble in the new toolchain
>>>>>> baseline
>>>>>> and avoids the double textural expansion.
>>>>>>
>>>>>> Signed-off-by: Andrew Cooper 
>>>>> Reviewed-by: Nicola Vetrini 
>>>> Thankyou.
>>>>
>>>>>> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
>>>>>> index 88bf26bc5109..38ef5d82ad95 100644
>>>>>> --- a/xen/include/xen/compiler.h
>>>>>> +++ b/xen/include/xen/compiler.h
>>>>>> @@ -64,6 +64,20 @@
>>>>>>  # define asm_inline asm
>>>>>>  #endif
>>>>>>
>>>>>> +/*
>>>>>> + * In C23, the auto keyword has been repurposed to perform type
>>>>>> inference.
>>>>>> + *
>>>>>> + * This behaviour is available via the __auto_type extension in
>>>>>> supported
>>>>>> + * toolchains.
>>>>>> + *
>>>>>> + *
>>>>>> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
>>>>>> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
>>>>>> + */
>>>>>> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
>>>>>> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23
>>>>>> meaning. */
>>>>>> +#define auto __auto_type
>>>>>> +#endif
>>>>>> +
>>>>> A more detailed explanation should live in deviations.rst under this
>>>>> bullet point
>>>>>
>>>>>    * - R20.4
>>>>>      - The override of the keyword \"inline\" in xen/compiler.h is
>>>>> present so
>>>>>        that section contents checks pass when the compiler chooses not 
>>>>> to
>>>>>        inline a particular function.
>>>>>      - Comment-based deviation.
>>>>>
>>>>> as described in the SAF entry:
>>>>>
>>>>>         {
>>>>>             "id": "SAF-3-safe",
>>>>>             "analyser": {
>>>>>                 "eclair": "MC3A2.R20.4"
>>>>>             },
>>>>>             "name": "MC3A2.R20.4: allow the definition of a macro with
>>>>> the same name as a keyword in some special cases",
>>>>>             "text": "The definition of a macro with the same name as a
>>>>> keyword can be useful in certain configurations to improve the
>>>>> guarantees that can be provided by Xen. See docs/misra/deviations.rst
>>>>> for a precise rationale for all such cases."
>>>>>         },
>>>> Ah right.  What about this:
>>>>
>>>> "Xen does not use the \"auto\" keyword as a storage qualifier.  The
>>>> override of the keyword \"auto\" in xen/compiler.h is to give it it's
>>>> C23 behaviour of type inference."
>>>>
>>>> ?
>>> Seems good to me. Maybe this should be spelled out in ./CODING_STYLE as 
>>> well, so that newcomers don't trip over this?
>> I'm not sure newcomers would look there, but in the absence of any better
>> place that's perhaps indeed where to mention this.
> 
> How about this:
> 
> diff --git a/CODING_STYLE b/CODING_STYLE
> index 7bf3848444ad..e33b9d1170cf 100644
> --- a/CODING_STYLE
> +++ b/CODING_STYLE
> @@ -129,6 +129,10 @@ Fixed width types should only be used when a fixed width quantity is
>  meant (which for example may be a value read from or to be written to a
>  register).
>  
> +Macros which otherwise would use "typeof(arg) newarg =" to avoid double
> +evaluation of side effects should use "auto newarg =" per it's C23 behaviour,
> +to also avoid double textural expansion.
> +
>  Especially with pointer types, whenever the pointed to object is not
>  (supposed to be) modified, qualify the pointed to type with "const".

That doesn't focus on the pitfall though, in that people shouldn't be using
the "auto" keyword (except in said cases).

Jan


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From: "Penny, Zheng" 
To: Jan Beulich , Stefano Stabellini
	
CC: "Huang, Ray" , Andrew Cooper
	, =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Anthony PERARD , "Orzel,
 Michal" , Julien Grall ,
	"xen-devel@lists.xenproject.org" 
Subject: RE: [PATCH v1 01/25] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
Thread-Topic: [PATCH v1 01/25] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
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Date: Fri, 15 Aug 2025 10:26:25 +0000
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References: <20250803094738.3625269-1-Penny.Zheng@amd.com>
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From: Penny Zheng 
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	, Michal Orzel , "Julien
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Subject: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
Date: Fri, 15 Aug 2025 18:27:28 +0800
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In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and
HVM=y results in hvm.c being built, but domctl.c not being built, which leaves
a few functions, like domctl_lock_acquire/release() undefined, causing linking
to fail.
To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile
/hypercall-defs section, with this adjustment, we also need to release
redundant vnuma_destroy() stub definition from PV_SHIM_EXCLUSIVE guardian,
to not break compilation
Above change will leave dead code in the shim binary temporarily and will be
fixed with the introduction of domctl-op wrapping.

Fixes: 568f806cba4c ("xen/x86: remove "depends on !PV_SHIM_EXCLUSIVE"")
Reported-by: Jan Beulich 
Signed-off-by: Penny Zheng 
---
v1 -> v2:
- remove paging_domctl hypercall-defs
---
v2 -> v3:
- remove paging_domctl change
---
 xen/arch/x86/Makefile        | 2 +-
 xen/common/Makefile          | 5 +----
 xen/include/hypercall-defs.c | 4 +---
 xen/include/xen/domain.h     | 4 ----
 4 files changed, 3 insertions(+), 12 deletions(-)

diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
index 5aab30a0c4..7676d7cdd8 100644
--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -28,6 +28,7 @@ obj-y += delay.o
 obj-y += desc.o
 obj-bin-y += dmi_scan.init.o
 obj-y += domain.o
+obj-y += domctl.o
 obj-bin-y += dom0_build.init.o
 obj-y += domain_page.o
 obj-y += e820.o
@@ -79,7 +80,6 @@ obj-y += vm_event.o
 obj-y += xstate.o
 
 ifneq ($(CONFIG_PV_SHIM_EXCLUSIVE),y)
-obj-y += domctl.o
 obj-y += platform_hypercall.o
 obj-$(CONFIG_COMPAT) += x86_64/platform_hypercall.o
 endif
diff --git a/xen/common/Makefile b/xen/common/Makefile
index c316957fcb..756ddf52c3 100644
--- a/xen/common/Makefile
+++ b/xen/common/Makefile
@@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o
 obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/
 obj-$(CONFIG_IOREQ_SERVER) += dm.o
 obj-y += domain.o
+obj-y += domctl.o
 obj-y += event_2l.o
 obj-y += event_channel.o
 obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o
@@ -69,10 +70,6 @@ obj-bin-$(CONFIG_X86) += $(foreach n,decompress bunzip2 unxz unlzma lzo unlzo un
 
 obj-$(CONFIG_COMPAT) += $(addprefix compat/,domain.o memory.o multicall.o xlat.o)
 
-ifneq ($(CONFIG_PV_SHIM_EXCLUSIVE),y)
-obj-y += domctl.o
-endif
-
 extra-y := symbols-dummy.o
 
 obj-$(CONFIG_COVERAGE) += coverage/
diff --git a/xen/include/hypercall-defs.c b/xen/include/hypercall-defs.c
index 8370b4b289..221dc25f6f 100644
--- a/xen/include/hypercall-defs.c
+++ b/xen/include/hypercall-defs.c
@@ -200,8 +200,8 @@ sysctl(xen_sysctl_t *u_sysctl)
 #if defined(CONFIG_X86) && defined(CONFIG_PAGING)
 paging_domctl_cont(xen_domctl_t *u_domctl)
 #endif
-#ifndef CONFIG_PV_SHIM_EXCLUSIVE
 domctl(xen_domctl_t *u_domctl)
+#ifndef CONFIG_PV_SHIM_EXCLUSIVE
 platform_op(xen_platform_op_t *u_xenpf_op)
 #endif
 #ifdef CONFIG_HVM
@@ -280,9 +280,7 @@ hvm_op                             do       do       do       do       do
 #ifdef CONFIG_SYSCTL
 sysctl                             do       do       do       do       do
 #endif
-#ifndef CONFIG_PV_SHIM_EXCLUSIVE
 domctl                             do       do       do       do       do
-#endif
 #ifdef CONFIG_KEXEC
 kexec_op                           compat   do       -        -        -
 #endif
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615..33dd90357c 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -182,11 +182,7 @@ struct vnuma_info {
     struct xen_vmemrange *vmemrange;
 };
 
-#ifndef CONFIG_PV_SHIM_EXCLUSIVE
 void vnuma_destroy(struct vnuma_info *vnuma);
-#else
-static inline void vnuma_destroy(struct vnuma_info *vnuma) { ASSERT(!vnuma); }
-#endif
 
 extern bool vmtrace_available;
 
-- 
2.34.1



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From: Dmytro Prokopchuk1 
To: Jan Beulich 
CC: Andrew Cooper , Anthony PERARD
	, Michal Orzel , Julien
 Grall , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Stefano Stabellini ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH] docs/misra: fix sphinx-build issues
Thread-Topic: [PATCH] docs/misra: fix sphinx-build issues
Thread-Index: AQHcDbJCdYlsiZdfl0mX5ViIXi0+6LRjZcaAgAAeAoA=
Date: Fri, 15 Aug 2025 10:30:16 +0000
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From: Frediano Ziglio 
Date: Fri, 15 Aug 2025 11:32:38 +0100
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Subject: Re: [PATCH v2] xen/efi: Fix crash with initial empty EFI options
To: xen-devel@lists.xenproject.org
Cc: "Daniel P. Smith" , 
	=?UTF-8?Q?Marek_Marczykowski=2DG=C3=B3recki?= , 
	Jan Beulich 
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ping

On Mon, Jul 28, 2025 at 11:39=E2=80=AFAM Frediano Ziglio
 wrote:
>
> ping
>
> On Tue, Jul 8, 2025 at 2:57=E2=80=AFPM Frediano Ziglio
>  wrote:
> >
> > EFI code path split options from EFI LoadOptions fields in 2
> > pieces, first EFI options, second Xen options.
> > "get_argv" function is called first to get the number of arguments
> > in the LoadOptions, second, after allocating enough space, to
> > fill some "argc"/"argv" variable. However the first parsing could
> > be different from second as second is able to detect "--" argument
> > separator. So it was possible that "argc" was bigger that the "argv"
> > array leading to potential buffer overflows, in particular
> > a string like "-- a b c" would lead to buffer overflow in "argv"
> > resulting in crashes.
> > Using EFI shell is possible to pass any kind of string in
> > LoadOptions.
> >
> > Fixes: bf6501a62e80 ("x86-64: EFI boot code")
> > Signed-off-by: Frediano Ziglio 
> > ---
> > Changes since v1:
> > - use argc to make code more clear;
> > - fix commit reference;
> > - improve commit message.
> > ---
> >  xen/common/efi/boot.c | 13 +++++++------
> >  1 file changed, 7 insertions(+), 6 deletions(-)
> >
> > diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
> > index 9306dc8953..385292ad4e 100644
> > --- a/xen/common/efi/boot.c
> > +++ b/xen/common/efi/boot.c
> > @@ -350,10 +350,11 @@ static unsigned int __init get_argv(unsigned int =
argc, CHAR16 **argv,
> >
> >      if ( argc )
> >      {
> > +        argc =3D 0;
> >          cmdline =3D data + *offset;
> >          /* EFI_LOAD_OPTION does not supply an image name as first comp=
onent. */
> >          if ( *offset )
> > -            *argv++ =3D NULL;
> > +            argv[argc++] =3D NULL;
> >      }
> >      else if ( size > sizeof(*cmdline) && !(size % sizeof(*cmdline)) &&
> >                (wmemchr(data, 0, size / sizeof(*cmdline)) =3D=3D
> > @@ -414,14 +415,14 @@ static unsigned int __init get_argv(unsigned int =
argc, CHAR16 **argv,
> >                  ++argc;
> >              else if ( prev && wstrcmp(prev, L"--") =3D=3D 0 )
> >              {
> > -                --argv;
> > +                --argc;
> >                  if ( options )
> >                      *options =3D cmdline;
> >                  break;
> >              }
> >              else
> >              {
> > -                *argv++ =3D prev =3D ptr;
> > +                argv[argc++] =3D prev =3D ptr;
> >                  *ptr =3D *cmdline;
> >                  *++ptr =3D 0;
> >              }
> > @@ -429,7 +430,7 @@ static unsigned int __init get_argv(unsigned int ar=
gc, CHAR16 **argv,
> >          prev_sep =3D cur_sep;
> >      }
> >      if ( argv )
> > -        *argv =3D NULL;
> > +        argv[argc] =3D NULL;
> >      return argc;
> >  }
> >
> > @@ -1348,8 +1349,8 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE =
ImageHandle,
> >                                    (argc + 1) * sizeof(*argv) +
> >                                        loaded_image->LoadOptionsSize,
> >                                    (void **)&argv) =3D=3D EFI_SUCCESS )
> > -            get_argv(argc, argv, loaded_image->LoadOptions,
> > -                     loaded_image->LoadOptionsSize, &offset, &options)=
;
> > +            argc =3D get_argv(argc, argv, loaded_image->LoadOptions,
> > +                            loaded_image->LoadOptionsSize, &offset, &o=
ptions);
> >          else
> >              argc =3D 0;
> >          for ( i =3D 1; i < argc; ++i )
> > --
> > 2.43.0
> >


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From: Frediano Ziglio 
Date: Fri, 15 Aug 2025 11:33:29 +0100
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Message-ID: 
Subject: Re: [PATCH v2] xen: Strip xen.efi by default
To: xen-devel@lists.xenproject.org
Cc: Andrew Cooper , Anthony PERARD , 
	Michal Orzel , Jan Beulich , Julien Grall , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Stefano Stabellini 
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ping

On Mon, Jul 28, 2025 at 11:34=E2=80=AFAM Frediano Ziglio
 wrote:
>
> ping
>
> On Wed, Jun 25, 2025 at 12:49=E2=80=AFPM Frediano Ziglio
>  wrote:
> >
> > On Thu, Jun 12, 2025 at 11:07=E2=80=AFAM Frediano Ziglio
> >  wrote:
> > >
> > > For xen.gz file we strip all symbols and have an additional
> > > xen-syms file version with all symbols.
> > > Make xen.efi more coherent stripping all symbols too.
> > > xen.efi.elf can be used for debugging.
> > >
> > > Signed-off-by: Frediano Ziglio 
> > > ---
> > > Changes since v1:
> > > - avoid leaving target if some command fails
> > > ---
> > >  docs/misc/efi.pandoc  |  8 +-------
> > >  xen/Kconfig.debug     |  9 ++-------
> > >  xen/Makefile          | 19 -------------------
> > >  xen/arch/x86/Makefile |  8 +++++---
> > >  4 files changed, 8 insertions(+), 36 deletions(-)
> > >
> > > diff --git a/docs/misc/efi.pandoc b/docs/misc/efi.pandoc
> > > index 11c1ac3346..c66b18a66b 100644
> > > --- a/docs/misc/efi.pandoc
> > > +++ b/docs/misc/efi.pandoc
> > > @@ -20,13 +20,7 @@ Xen to load the configuration file even if multibo=
ot modules are found.
> > >  Once built, `make install-xen` will place the resulting binary direc=
tly into
> > >  the EFI boot partition, provided `EFI_VENDOR` is set in the environm=
ent (and
> > >  `EFI_MOUNTPOINT` is overridden as needed, should the default of `/bo=
ot/efi` not
> > > -match your system). When built with debug info, the binary can be qu=
ite large.
> > > -Setting `INSTALL_EFI_STRIP=3D1` in the environment will cause it to =
be stripped
> > > -of debug info in the process of installing. `INSTALL_EFI_STRIP` can =
also be set
> > > -to any combination of options suitable to pass to `strip`, in case t=
he default
> > > -ones don't do. The xen.efi binary will also be installed in `/usr/li=
b64/efi/`,
> > > -unless `EFI_DIR` is set in the environment to override this default.=
 This
> > > -binary will not be stripped in the process.
> > > +match your system).
> > >
> > >  The binary itself will require a configuration file (names with the =
`.efi`
> > >  extension of the binary's name replaced by `.cfg`, and - until an ex=
isting
> > > diff --git a/xen/Kconfig.debug b/xen/Kconfig.debug
> > > index d14093017e..cafbb1236c 100644
> > > --- a/xen/Kconfig.debug
> > > +++ b/xen/Kconfig.debug
> > > @@ -147,12 +147,7 @@ config DEBUG_INFO
> > >           Say Y here if you want to build Xen with debug information.=
 This
> > >           information is needed e.g. for doing crash dump analysis of=
 the
> > >           hypervisor via the "crash" tool.
> > > -         Saying Y will increase the size of the xen-syms and xen.efi
> > > -         binaries. In case the space on the EFI boot partition is ra=
ther
> > > -         limited, you may want to install a stripped variant of xen.=
efi in
> > > -         the EFI boot partition (look for "INSTALL_EFI_STRIP" in
> > > -         docs/misc/efi.pandoc for more information - when not using
> > > -         "make install-xen" for installing xen.efi, stripping needs =
to be
> > > -         done outside the Xen build environment).
> > > +         Saying Y will increase the size of the xen-syms and xen.efi=
.elf
> > > +         binaries.
> > >
> > >  endmenu
> > > diff --git a/xen/Makefile b/xen/Makefile
> > > index 8fc4e042ff..664c4ea7b8 100644
> > > --- a/xen/Makefile
> > > +++ b/xen/Makefile
> > > @@ -488,22 +488,6 @@ endif
> > >  .PHONY: _build
> > >  _build: $(TARGET)$(CONFIG_XEN_INSTALL_SUFFIX)
> > >
> > > -# Strip
> > > -#
> > > -# INSTALL_EFI_STRIP, if defined, will cause xen.efi to be stripped b=
efore it
> > > -# is installed. If INSTALL_EFI_STRIP is '1', then the default option=
(s) below
> > > -# will be used. Otherwise, INSTALL_EFI_STRIP value will be used as t=
he
> > > -# option(s) to the strip command.
> > > -ifdef INSTALL_EFI_STRIP
> > > -
> > > -ifeq ($(INSTALL_EFI_STRIP),1)
> > > -efi-strip-opt :=3D --strip-debug --keep-file-symbols
> > > -else
> > > -efi-strip-opt :=3D $(INSTALL_EFI_STRIP)
> > > -endif
> > > -
> > > -endif
> > > -
> > >  .PHONY: _install
> > >  _install: D=3D$(DESTDIR)
> > >  _install: T=3D$(notdir $(TARGET))
> > > @@ -530,9 +514,6 @@ _install: $(TARGET)$(CONFIG_XEN_INSTALL_SUFFIX)
> > >                 ln -sf $(T)-$(XEN_FULLVERSION).efi $(D)$(EFI_DIR)/$(T=
)-$(XEN_VERSION).efi; \
> > >                 ln -sf $(T)-$(XEN_FULLVERSION).efi $(D)$(EFI_DIR)/$(T=
).efi; \
> > >                 if [ -n '$(EFI_MOUNTPOINT)' -a -n '$(EFI_VENDOR)' ]; =
then \
> > > -                       $(if $(efi-strip-opt), \
> > > -                            $(STRIP) $(efi-strip-opt) -p -o $(TARGET=
).efi.stripped $(TARGET).efi && \
> > > -                            $(INSTALL_DATA) $(TARGET).efi.stripped $=
(D)$(EFI_MOUNTPOINT)/efi/$(EFI_VENDOR)/$(T)-$(XEN_FULLVERSION).efi ||) \
> > >                         $(INSTALL_DATA) $(TARGET).efi $(D)$(EFI_MOUNT=
POINT)/efi/$(EFI_VENDOR)/$(T)-$(XEN_FULLVERSION).efi; \
> > >                 elif [ "$(D)" =3D "$(patsubst $(shell cd $(XEN_ROOT) =
&& pwd)/%,%,$(D))" ]; then \
> > >                         echo 'EFI installation only partially done (E=
FI_VENDOR not set)' >&2; \
> > > diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
> > > index ce724a9daa..e0ebc8c73e 100644
> > > --- a/xen/arch/x86/Makefile
> > > +++ b/xen/arch/x86/Makefile
> > > @@ -232,14 +232,16 @@ endif
> > >         $(MAKE) $(build)=3D$(@D) .$(@F).1r.o .$(@F).1s.o
> > >         $(LD) $(call EFI_LDFLAGS,$(VIRT_BASE)) -T $(obj)/efi.lds $< \
> > >               $(dot-target).1r.o $(dot-target).1s.o $(orphan-handling=
-y) \
> > > -             $(note_file_option) -o $@
> > > -       $(NM) -pa --format=3Dsysv $@ \
> > > +             $(note_file_option) -o $@.tmp
> > > +       $(NM) -pa --format=3Dsysv $@.tmp \
> > >                 | $(objtree)/tools/symbols --all-symbols --xensyms --=
sysv --sort \
> > >                 > $@.map
> > >  ifeq ($(CONFIG_DEBUG_INFO),y)
> > > -       $(if $(filter --strip-debug,$(EFI_LDFLAGS)),:$(space))$(OBJCO=
PY) -O elf64-x86-64 $@ $@.elf
> > > +       $(if $(filter --strip-debug,$(EFI_LDFLAGS)),:$(space))$(OBJCO=
PY) -O elf64-x86-64 $@.tmp $@.elf
> > > +       $(if $(filter --strip-debug,$(EFI_LDFLAGS)),:$(space))$(STRIP=
) $@.tmp
> > >  endif
> > >         rm -f $(dot-target).[0-9]* $(@D)/..$(@F).[0-9]*
> > > +       mv -f $@.tmp $@
> > >  ifeq ($(CONFIG_XEN_IBT),y)
> > >         $(SHELL) $(srctree)/tools/check-endbr.sh $@
> > >  endif
> >
> > Any comments on this version?
> >
> > Frediano


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Subject: Re: [PATCH v2] xen: Use auto as per C23
To: Jan Beulich 
Cc: Xen-devel ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Roberto Bagnara ,
 "consulting @ bugseng . com" ,
 Nicola Vetrini 
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On 15/08/2025 11:25 am, Jan Beulich wrote:
> On 15.08.2025 11:51, Andrew Cooper wrote:
>> On 15/08/2025 10:36 am, Jan Beulich wrote:
>>> On 15.08.2025 10:33, Nicola Vetrini wrote:
>>>> On 2025-08-15 10:17, Andrew Cooper wrote:
>>>>> On 15/08/2025 8:20 am, Nicola Vetrini wrote:
>>>>>> On 2025-08-15 00:25, Andrew Cooper wrote:
>>>>>>> In macros it is common to declare local variables using typeof(param)
>>>>>>> in order
>>>>>>> to ensure that side effects are only evaluated once.  A consequence
>>>>>>> of this is
>>>>>>> double textural expansion of the parameter, which can get out of hand
>>>>>>> very
>>>>>>> quickly with nested macros.
>>>>>>>
>>>>>>> In C23, the auto keyword has been repurposed to perform type 
>>>>>>> inference.
>>>>>>>
>>>>>>> A GCC extension, __auto_type, is now avaialble in the new toolchain
>>>>>>> baseline
>>>>>>> and avoids the double textural expansion.
>>>>>>>
>>>>>>> Signed-off-by: Andrew Cooper 
>>>>>> Reviewed-by: Nicola Vetrini 
>>>>> Thankyou.
>>>>>
>>>>>>> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
>>>>>>> index 88bf26bc5109..38ef5d82ad95 100644
>>>>>>> --- a/xen/include/xen/compiler.h
>>>>>>> +++ b/xen/include/xen/compiler.h
>>>>>>> @@ -64,6 +64,20 @@
>>>>>>>  # define asm_inline asm
>>>>>>>  #endif
>>>>>>>
>>>>>>> +/*
>>>>>>> + * In C23, the auto keyword has been repurposed to perform type
>>>>>>> inference.
>>>>>>> + *
>>>>>>> + * This behaviour is available via the __auto_type extension in
>>>>>>> supported
>>>>>>> + * toolchains.
>>>>>>> + *
>>>>>>> + *
>>>>>>> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
>>>>>>> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
>>>>>>> + */
>>>>>>> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
>>>>>>> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23
>>>>>>> meaning. */
>>>>>>> +#define auto __auto_type
>>>>>>> +#endif
>>>>>>> +
>>>>>> A more detailed explanation should live in deviations.rst under this
>>>>>> bullet point
>>>>>>
>>>>>>    * - R20.4
>>>>>>      - The override of the keyword \"inline\" in xen/compiler.h is
>>>>>> present so
>>>>>>        that section contents checks pass when the compiler chooses not 
>>>>>> to
>>>>>>        inline a particular function.
>>>>>>      - Comment-based deviation.
>>>>>>
>>>>>> as described in the SAF entry:
>>>>>>
>>>>>>         {
>>>>>>             "id": "SAF-3-safe",
>>>>>>             "analyser": {
>>>>>>                 "eclair": "MC3A2.R20.4"
>>>>>>             },
>>>>>>             "name": "MC3A2.R20.4: allow the definition of a macro with
>>>>>> the same name as a keyword in some special cases",
>>>>>>             "text": "The definition of a macro with the same name as a
>>>>>> keyword can be useful in certain configurations to improve the
>>>>>> guarantees that can be provided by Xen. See docs/misra/deviations.rst
>>>>>> for a precise rationale for all such cases."
>>>>>>         },
>>>>> Ah right.  What about this:
>>>>>
>>>>> "Xen does not use the \"auto\" keyword as a storage qualifier.  The
>>>>> override of the keyword \"auto\" in xen/compiler.h is to give it it's
>>>>> C23 behaviour of type inference."
>>>>>
>>>>> ?
>>>> Seems good to me. Maybe this should be spelled out in ./CODING_STYLE as 
>>>> well, so that newcomers don't trip over this?
>>> I'm not sure newcomers would look there, but in the absence of any better
>>> place that's perhaps indeed where to mention this.
>> How about this:
>>
>> diff --git a/CODING_STYLE b/CODING_STYLE
>> index 7bf3848444ad..e33b9d1170cf 100644
>> --- a/CODING_STYLE
>> +++ b/CODING_STYLE
>> @@ -129,6 +129,10 @@ Fixed width types should only be used when a fixed width quantity is
>>  meant (which for example may be a value read from or to be written to a
>>  register).
>>  
>> +Macros which otherwise would use "typeof(arg) newarg =" to avoid double
>> +evaluation of side effects should use "auto newarg =" per it's C23 behaviour,
>> +to also avoid double textural expansion.
>> +
>>  Especially with pointer types, whenever the pointed to object is not
>>  (supposed to be) modified, qualify the pointed to type with "const".
> That doesn't focus on the pitfall though, in that people shouldn't be using
> the "auto" keyword (except in said cases).

/sigh, this is why noone does patches to CODING_STYLE.

If you don't like the wording, propose some wording that you do like.

Or I will commit the patch without this hunk, because I'm not going to
get drawn into the cycle of blind guessing that every change to
CODING_STYLE seems to get caught in.

~Andrew


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Date: Fri, 15 Aug 2025 12:21:52 +0100
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Subject: Re: [RFC PATCH] xsm/flask: add AVC pre-allocation boot parameter
To: Sergiy Kibrik , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 "Daniel P. Smith" ,
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On 15/08/2025 11:23 am, Sergiy Kibrik wrote:
> diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
> index a75b6c9301..9044827e78 100644
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -238,6 +238,15 @@ loops for Queued Invalidation completions.**
>  Specify a maximum amount of available memory, to which Xen will clamp
>  the e820 table.
>  
> +### avc_prealloc
> +> `= `
> +
> +> Default: `false`
> +
> +Allocate XSM Access Vector Cache at boot. This forbids runtime dynamic
> +allocation of AVC nodes from Xen heap and changing AVC size via
> +FLASK_SETAVC_THRESHOLD hypercall.

I don't have any input on memory allocation side of things, but this
needs to be a sub-option under the existing flask=, and it looks like
you're going to need to turn it into a comma separated list.

Also, if you actually want to use Flask in a safety system, Flask needs
to become security supported in Xen.

~Andrew


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From: Frediano Ziglio 
Date: Fri, 15 Aug 2025 12:35:54 +0100
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Message-ID: 
Subject: Re: [PATCH v2] xen: Use auto as per C23
To: Andrew Cooper 
Cc: Xen-devel , 
	Anthony PERARD , Michal Orzel , 
	Jan Beulich , Julien Grall , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Stefano Stabellini , Roberto Bagnara , 
	Nicola Vetrini , 
	"consulting @ bugseng . com" 
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On Thu, Aug 14, 2025 at 11:25=E2=80=AFPM Andrew Cooper
 wrote:
>
> In macros it is common to declare local variables using typeof(param) in =
order
> to ensure that side effects are only evaluated once.  A consequence of th=
is is
> double textural expansion of the parameter, which can get out of hand ver=
y
> quickly with nested macros.
>
> In C23, the auto keyword has been repurposed to perform type inference.
>
> A GCC extension, __auto_type, is now avaialble in the new toolchain basel=
ine
> and avoids the double textural expansion.
>
> Signed-off-by: Andrew Cooper 
> ---
> CC: Anthony PERARD 
> CC: Michal Orzel 
> CC: Jan Beulich 
> CC: Julien Grall 
> CC: Roger Pau Monn=C3=A9 
> CC: Stefano Stabellini 
> CC: Roberto Bagnara 
> CC: Nicola Vetrini 
> CC: consulting@bugseng.com 
>
> The resulting build is identical.
>
> v2:
>  * Use auto directly
>  * Eclair configuration
>
> https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/198528943=
4
> ---
>  automation/eclair_analysis/ECLAIR/toolchain.ecl | 11 +++++++++--
>  docs/misra/C-language-toolchain.rst             |  2 ++
>  xen/include/xen/compiler.h                      | 14 ++++++++++++++
>  xen/include/xen/macros.h                        | 14 +++++++-------
>  4 files changed, 32 insertions(+), 9 deletions(-)
>
> diff --git a/automation/eclair_analysis/ECLAIR/toolchain.ecl b/automation=
/eclair_analysis/ECLAIR/toolchain.ecl
> index 842f8377e561..125f99a06583 100644
> --- a/automation/eclair_analysis/ECLAIR/toolchain.ecl
> +++ b/automation/eclair_analysis/ECLAIR/toolchain.ecl
> @@ -15,6 +15,7 @@
>      __alignof__, __alignof: see Sections \"6.48 Alternate Keywords\" and=
 \"6.44 Determining the Alignment of Functions, Types or Variables\" of "GC=
C_MANUAL".
>      asm, __asm__: see Sections \"6.48 Alternate Keywords\" and \"6.47 Ho=
w to Use Inline Assembly Language in C Code\" of "GCC_MANUAL".
>      __attribute__: see Section \"6.39 Attribute Syntax\" of "GCC_MANUAL"=
.
> +    __auto_type: see Section \"6.7 Referring to a Type with typeof\" of =
"GCC_MANUAL".
>      __builtin_offsetof: see Section \"6.53 Support for offsetof\" of "GC=
C_MANUAL".
>      __builtin_types_compatible_p: see Section \"6.59 Other Built-in Func=
tions Provided by GCC\" of "GCC_MANUAL".
>      __builtin_va_arg: non-documented GCC extension.
> @@ -26,6 +27,7 @@
>  -name_selector+=3D{alignof, "^(__alignof__|__alignof)$"}
>  -name_selector+=3D{asm, "^(__asm__|asm)$"}
>  -name_selector+=3D{attribute, "^__attribute__$"}
> +-name_selector+=3D{auto_type, "^__auto_type$"}
>  -name_selector+=3D{builtin_offsetof, "^__builtin_offsetof$"}
>  -name_selector+=3D{builtin_types_p, "^__builtin_types_compatible_p$"}
>  -name_selector+=3D{builtin_va_arg, "^__builtin_va_arg$"}
> @@ -39,6 +41,7 @@
>  "alignof||
>  asm||
>  attribute||
> +auto_type||
>  builtin_offsetof||
>  builtin_types_p||
>  builtin_va_arg||
> @@ -114,6 +117,7 @@ volatile"
>  -doc_end
>
>  -doc_begin=3D"
> +    ext_auto_type: see Section \"6.7 Referring to a Type with typeof\" o=
f "GCC_MANUAL".
>      ext_c_missing_varargs_arg: see Section \"6.21 Macros with a Variable=
 Number of Arguments\" of "GCC_MANUAL".
>      ext_enum_value_not_int: non-documented GCC extension.
>      ext_flexible_array_in_array: see Section \"6.18 Arrays of Length Zer=
o\" of "GCC_MANUAL".
> @@ -126,6 +130,7 @@ volatile"
>      ext_return_has_void_expr: see the documentation for -Wreturn-type in=
 Section \"3.8 Options to Request or Suppress Warnings\" of "GCC_MANUAL".
>      ext_sizeof_alignof_void_type: see Section \"6.24 Arithmetic on void-=
 and Function-Pointers\" of "GCC_MANUAL".
>  "
> +-name_selector+=3D{ext_auto_type, "^ext_auto_type$"}
>  -name_selector+=3D{ext_c_missing_varargs_arg, "^ext_c_missing_varargs_ar=
g$"}
>  -name_selector+=3D{ext_enum_value_not_int, "^ext_enum_value_not_int$"}
>  -name_selector+=3D{ext_flexible_array_in_array, "^ext_flexible_array_in_=
array$"}
> @@ -139,7 +144,8 @@ volatile"
>  -name_selector+=3D{ext_sizeof_alignof_void_type, "^ext_sizeof_alignof_vo=
id_type$"}
>
>  -config=3DSTD.diag,behavior+=3D{c99,GCC_ARM64,
> -"ext_c_missing_varargs_arg||
> +"ext_auto_type||
> +ext_c_missing_varargs_arg||
>  ext_forward_ref_enum_def||
>  ext_gnu_array_range||
>  ext_gnu_statement_expr_macro||
> @@ -149,7 +155,8 @@ ext_return_has_void_expr||
>  ext_sizeof_alignof_void_type"
>  }
>  -config=3DSTD.diag,behavior+=3D{c99,GCC_X86_64,
> -"ext_c_missing_varargs_arg||
> +"ext_auto_type||
> +ext_c_missing_varargs_arg||
>  ext_enum_value_not_int||
>  ext_flexible_array_in_array||
>  ext_flexible_array_in_struct||
> diff --git a/docs/misra/C-language-toolchain.rst b/docs/misra/C-language-=
toolchain.rst
> index cb81f5c09872..635936004554 100644
> --- a/docs/misra/C-language-toolchain.rst
> +++ b/docs/misra/C-language-toolchain.rst
> @@ -94,6 +94,8 @@ The table columns are as follows:
>            see Sections "6.48 Alternate Keywords" and "6.44 Determining t=
he Alignment of Functions, Types or Variables" of GCC_MANUAL.
>         __attribute__:
>            see Section "6.39 Attribute Syntax" of GCC_MANUAL.
> +       __auto_type:
> +          see Section "6.7 Referring to a Type with typeof" of GCC_MANUA=
L.
>         __builtin_types_compatible_p:
>            see Section "6.59 Other Built-in Functions Provided by GCC" of=
 GCC_MANUAL.
>         __builtin_va_arg:
> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
> index 88bf26bc5109..38ef5d82ad95 100644
> --- a/xen/include/xen/compiler.h
> +++ b/xen/include/xen/compiler.h
> @@ -64,6 +64,20 @@
>  # define asm_inline asm
>  #endif
>
> +/*
> + * In C23, the auto keyword has been repurposed to perform type inferenc=
e.
> + *
> + * This behaviour is available via the __auto_type extension in supporte=
d
> + * toolchains.
> + *
> + * https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Ty=
pe.html
> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
> + */
> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23 meaning. */
> +#define auto __auto_type
> +#endif
> +
>  /*
>   * Add the pseudo keyword 'fallthrough' so case statement blocks
>   * must end with any of these keywords:
> diff --git a/xen/include/xen/macros.h b/xen/include/xen/macros.h
> index f9ccde86fb23..ceca2e4a1bf1 100644
> --- a/xen/include/xen/macros.h
> +++ b/xen/include/xen/macros.h
> @@ -63,18 +63,18 @@
>  /* Hide a value from the optimiser. */
>  #define HIDE(x)                                 \
>      ({                                          \
> -        typeof(x) _x =3D (x);                     \
> +        auto _x =3D (x);                          \
>          asm volatile ( "" : "+r" (_x) );        \
>          _x;                                     \
>      })
>
>  #define ABS(x) ({                              \
> -    typeof(x) x_ =3D (x);                        \
> +    auto x_ =3D (x);                             \
>      (x_ < 0) ? -x_ : x_;                       \
>  })
>
>  #define SWAP(a, b) \
> -   do { typeof(a) t_ =3D (a); (a) =3D (b); (b) =3D t_; } while ( 0 )
> +   do { auto t_ =3D (a); (a) =3D (b); (b) =3D t_; } while ( 0 )
>
>  #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]) + __must_be_array(x))
>
> @@ -102,15 +102,15 @@
>   */
>  #define min(x, y)                               \
>      ({                                          \
> -        const typeof(x) _x =3D (x);               \
> -        const typeof(y) _y =3D (y);               \
> +        const auto _x =3D (x);                    \
> +        const auto _y =3D (y);                    \
>          (void)(&_x =3D=3D &_y); /* typecheck */     \
>          _x < _y ? _x : _y;                      \
>      })
>  #define max(x, y)                               \
>      ({                                          \
> -        const typeof(x) _x =3D (x);               \
> -        const typeof(y) _y =3D (y);               \
> +        const auto _x =3D (x);                    \
> +        const auto _y =3D (y);                    \
>          (void)(&_x =3D=3D &_y); /* typecheck */     \
>          _x > _y ? _x : _y;                      \
>      })
>
> base-commit: b2c0dc44b37516b758c38de04c61ad295ac0dff2

Thanks for the change, nice to have it.

Reviewed-by: Frediano Ziglio 

Frediano


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Subject: Re: [RFC PATCH] xsm/flask: add AVC pre-allocation boot parameter
From: Andrew Cooper 
To: Sergiy Kibrik , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
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 Stefano Stabellini 
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On 15/08/2025 12:21 pm, Andrew Cooper wrote:
> On 15/08/2025 11:23 am, Sergiy Kibrik wrote:
>> diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
>> index a75b6c9301..9044827e78 100644
>> --- a/docs/misc/xen-command-line.pandoc
>> +++ b/docs/misc/xen-command-line.pandoc
>> @@ -238,6 +238,15 @@ loops for Queued Invalidation completions.**
>>  Specify a maximum amount of available memory, to which Xen will clamp
>>  the e820 table.
>>  
>> +### avc_prealloc
>> +> `= `
>> +
>> +> Default: `false`
>> +
>> +Allocate XSM Access Vector Cache at boot. This forbids runtime dynamic
>> +allocation of AVC nodes from Xen heap and changing AVC size via
>> +FLASK_SETAVC_THRESHOLD hypercall.
> I don't have any input on memory allocation side of things, but this
> needs to be a sub-option under the existing flask=, and it looks like
> you're going to need to turn it into a comma separated list.
>
> Also, if you actually want to use Flask in a safety system, Flask needs
> to become security supported in Xen.

Sorry, sent a little too early.  x86's dom0= is probably the closes good
example to follow, having both comma separated booleans and a choice-of-$N.

~Andrew


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Subject: Re: [RFC PATCH] xsm/flask: add AVC pre-allocation boot parameter
To: Sergiy Kibrik 
Cc: Andrew Cooper ,
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 Stefano Stabellini ,
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On 15.08.2025 12:23, Sergiy Kibrik wrote:
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -238,6 +238,15 @@ loops for Queued Invalidation completions.**
>  Specify a maximum amount of available memory, to which Xen will clamp
>  the e820 table.
>  
> +### avc_prealloc

In addition to what Andrew said, please prefer dashes over underscores in new
options.

> @@ -97,6 +99,9 @@ static struct avc_cache avc_cache;
>  
>  static DEFINE_RCU_READ_LOCK(avc_rcu_lock);
>  
> +bool __read_mostly opt_avc_prealloc = false;

__ro_after_init?

Jan


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Date: Fri, 15 Aug 2025 14:28:08 +0200
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Subject: Re: [PATCH v2] xen: Use auto as per C23
To: Andrew Cooper 
Cc: Xen-devel ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Roberto Bagnara ,
 "consulting @ bugseng . com" ,
 Nicola Vetrini 
References: <20250814222524.2638883-1-andrew.cooper3@citrix.com>
 <3056ed85948288639110e3cdd6b28c6e@bugseng.com>
 
 <7fc93aeef27153f1d6caa786bd44420f@bugseng.com>
 
 
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Content-Language: en-US
From: Jan Beulich 
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On 15.08.2025 12:53, Andrew Cooper wrote:
> On 15/08/2025 11:25 am, Jan Beulich wrote:
>> On 15.08.2025 11:51, Andrew Cooper wrote:
>>> On 15/08/2025 10:36 am, Jan Beulich wrote:
>>>> On 15.08.2025 10:33, Nicola Vetrini wrote:
>>>>> On 2025-08-15 10:17, Andrew Cooper wrote:
>>>>>> On 15/08/2025 8:20 am, Nicola Vetrini wrote:
>>>>>>> On 2025-08-15 00:25, Andrew Cooper wrote:
>>>>>>>> In macros it is common to declare local variables using typeof(param)
>>>>>>>> in order
>>>>>>>> to ensure that side effects are only evaluated once.  A consequence
>>>>>>>> of this is
>>>>>>>> double textural expansion of the parameter, which can get out of hand
>>>>>>>> very
>>>>>>>> quickly with nested macros.
>>>>>>>>
>>>>>>>> In C23, the auto keyword has been repurposed to perform type 
>>>>>>>> inference.
>>>>>>>>
>>>>>>>> A GCC extension, __auto_type, is now avaialble in the new toolchain
>>>>>>>> baseline
>>>>>>>> and avoids the double textural expansion.
>>>>>>>>
>>>>>>>> Signed-off-by: Andrew Cooper 
>>>>>>> Reviewed-by: Nicola Vetrini 
>>>>>> Thankyou.
>>>>>>
>>>>>>>> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
>>>>>>>> index 88bf26bc5109..38ef5d82ad95 100644
>>>>>>>> --- a/xen/include/xen/compiler.h
>>>>>>>> +++ b/xen/include/xen/compiler.h
>>>>>>>> @@ -64,6 +64,20 @@
>>>>>>>>  # define asm_inline asm
>>>>>>>>  #endif
>>>>>>>>
>>>>>>>> +/*
>>>>>>>> + * In C23, the auto keyword has been repurposed to perform type
>>>>>>>> inference.
>>>>>>>> + *
>>>>>>>> + * This behaviour is available via the __auto_type extension in
>>>>>>>> supported
>>>>>>>> + * toolchains.
>>>>>>>> + *
>>>>>>>> + *
>>>>>>>> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
>>>>>>>> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
>>>>>>>> + */
>>>>>>>> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
>>>>>>>> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23
>>>>>>>> meaning. */
>>>>>>>> +#define auto __auto_type
>>>>>>>> +#endif
>>>>>>>> +
>>>>>>> A more detailed explanation should live in deviations.rst under this
>>>>>>> bullet point
>>>>>>>
>>>>>>>    * - R20.4
>>>>>>>      - The override of the keyword \"inline\" in xen/compiler.h is
>>>>>>> present so
>>>>>>>        that section contents checks pass when the compiler chooses not 
>>>>>>> to
>>>>>>>        inline a particular function.
>>>>>>>      - Comment-based deviation.
>>>>>>>
>>>>>>> as described in the SAF entry:
>>>>>>>
>>>>>>>         {
>>>>>>>             "id": "SAF-3-safe",
>>>>>>>             "analyser": {
>>>>>>>                 "eclair": "MC3A2.R20.4"
>>>>>>>             },
>>>>>>>             "name": "MC3A2.R20.4: allow the definition of a macro with
>>>>>>> the same name as a keyword in some special cases",
>>>>>>>             "text": "The definition of a macro with the same name as a
>>>>>>> keyword can be useful in certain configurations to improve the
>>>>>>> guarantees that can be provided by Xen. See docs/misra/deviations.rst
>>>>>>> for a precise rationale for all such cases."
>>>>>>>         },
>>>>>> Ah right.  What about this:
>>>>>>
>>>>>> "Xen does not use the \"auto\" keyword as a storage qualifier.  The
>>>>>> override of the keyword \"auto\" in xen/compiler.h is to give it it's
>>>>>> C23 behaviour of type inference."
>>>>>>
>>>>>> ?
>>>>> Seems good to me. Maybe this should be spelled out in ./CODING_STYLE as 
>>>>> well, so that newcomers don't trip over this?
>>>> I'm not sure newcomers would look there, but in the absence of any better
>>>> place that's perhaps indeed where to mention this.
>>> How about this:
>>>
>>> diff --git a/CODING_STYLE b/CODING_STYLE
>>> index 7bf3848444ad..e33b9d1170cf 100644
>>> --- a/CODING_STYLE
>>> +++ b/CODING_STYLE
>>> @@ -129,6 +129,10 @@ Fixed width types should only be used when a fixed width quantity is
>>>  meant (which for example may be a value read from or to be written to a
>>>  register).
>>>  
>>> +Macros which otherwise would use "typeof(arg) newarg =" to avoid double
>>> +evaluation of side effects should use "auto newarg =" per it's C23 behaviour,
>>> +to also avoid double textural expansion.
>>> +
>>>  Especially with pointer types, whenever the pointed to object is not
>>>  (supposed to be) modified, qualify the pointed to type with "const".
>> That doesn't focus on the pitfall though, in that people shouldn't be using
>> the "auto" keyword (except in said cases).
> 
> /sigh, this is why noone does patches to CODING_STYLE.
> 
> If you don't like the wording, propose some wording that you do like.
> 
> Or I will commit the patch without this hunk, because I'm not going to
> get drawn into the cycle of blind guessing that every change to
> CODING_STYLE seems to get caught in.

I don't care about the wording; what I do care about is to get the caveat
across. Maybe:

'"auto" isn't used in its traditional sense, but rather with its C23 meaning.
 Such uses are intended to be limited to macro-local variables.'

Jan


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Subject: Re: [PATCH v2] xen: Use auto as per C23
To: Jan Beulich 
Cc: Andrew Cooper , Xen-devel , 
	Anthony PERARD , Michal Orzel , 
	Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Stefano Stabellini , Roberto Bagnara , 
	"consulting @ bugseng . com" , Nicola Vetrini 
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Fri, Aug 15, 2025 at 1:28=E2=80=AFPM Jan Beulich  wro=
te:
>
> On 15.08.2025 12:53, Andrew Cooper wrote:
> > On 15/08/2025 11:25 am, Jan Beulich wrote:
> >> On 15.08.2025 11:51, Andrew Cooper wrote:
> >>> On 15/08/2025 10:36 am, Jan Beulich wrote:
> >>>> On 15.08.2025 10:33, Nicola Vetrini wrote:
> >>>>> On 2025-08-15 10:17, Andrew Cooper wrote:
> >>>>>> On 15/08/2025 8:20 am, Nicola Vetrini wrote:
> >>>>>>> On 2025-08-15 00:25, Andrew Cooper wrote:
> >>>>>>>> In macros it is common to declare local variables using typeof(p=
aram)
> >>>>>>>> in order
> >>>>>>>> to ensure that side effects are only evaluated once.  A conseque=
nce
> >>>>>>>> of this is
> >>>>>>>> double textural expansion of the parameter, which can get out of=
 hand
> >>>>>>>> very
> >>>>>>>> quickly with nested macros.
> >>>>>>>>
> >>>>>>>> In C23, the auto keyword has been repurposed to perform type
> >>>>>>>> inference.
> >>>>>>>>
> >>>>>>>> A GCC extension, __auto_type, is now avaialble in the new toolch=
ain
> >>>>>>>> baseline
> >>>>>>>> and avoids the double textural expansion.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Andrew Cooper 
> >>>>>>> Reviewed-by: Nicola Vetrini 
> >>>>>> Thankyou.
> >>>>>>
> >>>>>>>> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compil=
er.h
> >>>>>>>> index 88bf26bc5109..38ef5d82ad95 100644
> >>>>>>>> --- a/xen/include/xen/compiler.h
> >>>>>>>> +++ b/xen/include/xen/compiler.h
> >>>>>>>> @@ -64,6 +64,20 @@
> >>>>>>>>  # define asm_inline asm
> >>>>>>>>  #endif
> >>>>>>>>
> >>>>>>>> +/*
> >>>>>>>> + * In C23, the auto keyword has been repurposed to perform type
> >>>>>>>> inference.
> >>>>>>>> + *
> >>>>>>>> + * This behaviour is available via the __auto_type extension in
> >>>>>>>> supported
> >>>>>>>> + * toolchains.
> >>>>>>>> + *
> >>>>>>>> + *
> >>>>>>>> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Au=
to-Type.html
> >>>>>>>> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-typ=
e
> >>>>>>>> + */
> >>>>>>>> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
> >>>>>>>> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23
> >>>>>>>> meaning. */
> >>>>>>>> +#define auto __auto_type
> >>>>>>>> +#endif
> >>>>>>>> +
> >>>>>>> A more detailed explanation should live in deviations.rst under t=
his
> >>>>>>> bullet point
> >>>>>>>
> >>>>>>>    * - R20.4
> >>>>>>>      - The override of the keyword \"inline\" in xen/compiler.h i=
s
> >>>>>>> present so
> >>>>>>>        that section contents checks pass when the compiler choose=
s not
> >>>>>>> to
> >>>>>>>        inline a particular function.
> >>>>>>>      - Comment-based deviation.
> >>>>>>>
> >>>>>>> as described in the SAF entry:
> >>>>>>>
> >>>>>>>         {
> >>>>>>>             "id": "SAF-3-safe",
> >>>>>>>             "analyser": {
> >>>>>>>                 "eclair": "MC3A2.R20.4"
> >>>>>>>             },
> >>>>>>>             "name": "MC3A2.R20.4: allow the definition of a macro=
 with
> >>>>>>> the same name as a keyword in some special cases",
> >>>>>>>             "text": "The definition of a macro with the same name=
 as a
> >>>>>>> keyword can be useful in certain configurations to improve the
> >>>>>>> guarantees that can be provided by Xen. See docs/misra/deviations=
.rst
> >>>>>>> for a precise rationale for all such cases."
> >>>>>>>         },
> >>>>>> Ah right.  What about this:
> >>>>>>
> >>>>>> "Xen does not use the \"auto\" keyword as a storage qualifier.  Th=
e
> >>>>>> override of the keyword \"auto\" in xen/compiler.h is to give it i=
t's
> >>>>>> C23 behaviour of type inference."
> >>>>>>
> >>>>>> ?
> >>>>> Seems good to me. Maybe this should be spelled out in ./CODING_STYL=
E as
> >>>>> well, so that newcomers don't trip over this?
> >>>> I'm not sure newcomers would look there, but in the absence of any b=
etter
> >>>> place that's perhaps indeed where to mention this.
> >>> How about this:
> >>>
> >>> diff --git a/CODING_STYLE b/CODING_STYLE
> >>> index 7bf3848444ad..e33b9d1170cf 100644
> >>> --- a/CODING_STYLE
> >>> +++ b/CODING_STYLE
> >>> @@ -129,6 +129,10 @@ Fixed width types should only be used when a fix=
ed width quantity is
> >>>  meant (which for example may be a value read from or to be written t=
o a
> >>>  register).
> >>>
> >>> +Macros which otherwise would use "typeof(arg) newarg =3D" to avoid d=
ouble
> >>> +evaluation of side effects should use "auto newarg =3D" per it's C23=
 behaviour,
> >>> +to also avoid double textural expansion.
> >>> +
> >>>  Especially with pointer types, whenever the pointed to object is not
> >>>  (supposed to be) modified, qualify the pointed to type with "const".
> >> That doesn't focus on the pitfall though, in that people shouldn't be =
using
> >> the "auto" keyword (except in said cases).
> >
> > /sigh, this is why noone does patches to CODING_STYLE.
> >
> > If you don't like the wording, propose some wording that you do like.
> >
> > Or I will commit the patch without this hunk, because I'm not going to
> > get drawn into the cycle of blind guessing that every change to
> > CODING_STYLE seems to get caught in.
>
> I don't care about the wording; what I do care about is to get the caveat
> across. Maybe:
>
> '"auto" isn't used in its traditional sense, but rather with its C23 mean=
ing.
>  Such uses are intended to be limited to macro-local variables.'
>

Why limiting to macros?

> Jan
>

Frediano


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Date: Fri, 15 Aug 2025 14:39:47 +0200
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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v2] xen: Use auto as per C23
To: Frediano Ziglio 
Cc: Andrew Cooper ,
 Xen-devel ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Roberto Bagnara ,
 "consulting @ bugseng . com" ,
 Nicola Vetrini 
References: <20250814222524.2638883-1-andrew.cooper3@citrix.com>
 <3056ed85948288639110e3cdd6b28c6e@bugseng.com>
 
 <7fc93aeef27153f1d6caa786bd44420f@bugseng.com>
 
 
 <5ff1e337-9ec5-466b-b21f-cf29274b007b@suse.com>
 
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From: Jan Beulich 
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On 15.08.2025 14:35, Frediano Ziglio wrote:
> On Fri, Aug 15, 2025 at 1:28 PM Jan Beulich  wrote:
>>
>> On 15.08.2025 12:53, Andrew Cooper wrote:
>>> On 15/08/2025 11:25 am, Jan Beulich wrote:
>>>> On 15.08.2025 11:51, Andrew Cooper wrote:
>>>>> On 15/08/2025 10:36 am, Jan Beulich wrote:
>>>>>> On 15.08.2025 10:33, Nicola Vetrini wrote:
>>>>>>> On 2025-08-15 10:17, Andrew Cooper wrote:
>>>>>>>> On 15/08/2025 8:20 am, Nicola Vetrini wrote:
>>>>>>>>> On 2025-08-15 00:25, Andrew Cooper wrote:
>>>>>>>>>> In macros it is common to declare local variables using typeof(param)
>>>>>>>>>> in order
>>>>>>>>>> to ensure that side effects are only evaluated once.  A consequence
>>>>>>>>>> of this is
>>>>>>>>>> double textural expansion of the parameter, which can get out of hand
>>>>>>>>>> very
>>>>>>>>>> quickly with nested macros.
>>>>>>>>>>
>>>>>>>>>> In C23, the auto keyword has been repurposed to perform type
>>>>>>>>>> inference.
>>>>>>>>>>
>>>>>>>>>> A GCC extension, __auto_type, is now avaialble in the new toolchain
>>>>>>>>>> baseline
>>>>>>>>>> and avoids the double textural expansion.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Andrew Cooper 
>>>>>>>>> Reviewed-by: Nicola Vetrini 
>>>>>>>> Thankyou.
>>>>>>>>
>>>>>>>>>> diff --git a/xen/include/xen/compiler.h b/xen/include/xen/compiler.h
>>>>>>>>>> index 88bf26bc5109..38ef5d82ad95 100644
>>>>>>>>>> --- a/xen/include/xen/compiler.h
>>>>>>>>>> +++ b/xen/include/xen/compiler.h
>>>>>>>>>> @@ -64,6 +64,20 @@
>>>>>>>>>>  # define asm_inline asm
>>>>>>>>>>  #endif
>>>>>>>>>>
>>>>>>>>>> +/*
>>>>>>>>>> + * In C23, the auto keyword has been repurposed to perform type
>>>>>>>>>> inference.
>>>>>>>>>> + *
>>>>>>>>>> + * This behaviour is available via the __auto_type extension in
>>>>>>>>>> supported
>>>>>>>>>> + * toolchains.
>>>>>>>>>> + *
>>>>>>>>>> + *
>>>>>>>>>> https://www.gnu.org/software/c-intro-and-ref/manual/html_node/Auto-Type.html
>>>>>>>>>> + * https://clang.llvm.org/docs/LanguageExtensions.html#auto-type
>>>>>>>>>> + */
>>>>>>>>>> +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 202311L
>>>>>>>>>> +/* SAF-3-safe MISRA C Rule 20.4: Giving the keyword it's C23
>>>>>>>>>> meaning. */
>>>>>>>>>> +#define auto __auto_type
>>>>>>>>>> +#endif
>>>>>>>>>> +
>>>>>>>>> A more detailed explanation should live in deviations.rst under this
>>>>>>>>> bullet point
>>>>>>>>>
>>>>>>>>>    * - R20.4
>>>>>>>>>      - The override of the keyword \"inline\" in xen/compiler.h is
>>>>>>>>> present so
>>>>>>>>>        that section contents checks pass when the compiler chooses not
>>>>>>>>> to
>>>>>>>>>        inline a particular function.
>>>>>>>>>      - Comment-based deviation.
>>>>>>>>>
>>>>>>>>> as described in the SAF entry:
>>>>>>>>>
>>>>>>>>>         {
>>>>>>>>>             "id": "SAF-3-safe",
>>>>>>>>>             "analyser": {
>>>>>>>>>                 "eclair": "MC3A2.R20.4"
>>>>>>>>>             },
>>>>>>>>>             "name": "MC3A2.R20.4: allow the definition of a macro with
>>>>>>>>> the same name as a keyword in some special cases",
>>>>>>>>>             "text": "The definition of a macro with the same name as a
>>>>>>>>> keyword can be useful in certain configurations to improve the
>>>>>>>>> guarantees that can be provided by Xen. See docs/misra/deviations.rst
>>>>>>>>> for a precise rationale for all such cases."
>>>>>>>>>         },
>>>>>>>> Ah right.  What about this:
>>>>>>>>
>>>>>>>> "Xen does not use the \"auto\" keyword as a storage qualifier.  The
>>>>>>>> override of the keyword \"auto\" in xen/compiler.h is to give it it's
>>>>>>>> C23 behaviour of type inference."
>>>>>>>>
>>>>>>>> ?
>>>>>>> Seems good to me. Maybe this should be spelled out in ./CODING_STYLE as
>>>>>>> well, so that newcomers don't trip over this?
>>>>>> I'm not sure newcomers would look there, but in the absence of any better
>>>>>> place that's perhaps indeed where to mention this.
>>>>> How about this:
>>>>>
>>>>> diff --git a/CODING_STYLE b/CODING_STYLE
>>>>> index 7bf3848444ad..e33b9d1170cf 100644
>>>>> --- a/CODING_STYLE
>>>>> +++ b/CODING_STYLE
>>>>> @@ -129,6 +129,10 @@ Fixed width types should only be used when a fixed width quantity is
>>>>>  meant (which for example may be a value read from or to be written to a
>>>>>  register).
>>>>>
>>>>> +Macros which otherwise would use "typeof(arg) newarg =" to avoid double
>>>>> +evaluation of side effects should use "auto newarg =" per it's C23 behaviour,
>>>>> +to also avoid double textural expansion.
>>>>> +
>>>>>  Especially with pointer types, whenever the pointed to object is not
>>>>>  (supposed to be) modified, qualify the pointed to type with "const".
>>>> That doesn't focus on the pitfall though, in that people shouldn't be using
>>>> the "auto" keyword (except in said cases).
>>>
>>> /sigh, this is why noone does patches to CODING_STYLE.
>>>
>>> If you don't like the wording, propose some wording that you do like.
>>>
>>> Or I will commit the patch without this hunk, because I'm not going to
>>> get drawn into the cycle of blind guessing that every change to
>>> CODING_STYLE seems to get caught in.
>>
>> I don't care about the wording; what I do care about is to get the caveat
>> across. Maybe:
>>
>> '"auto" isn't used in its traditional sense, but rather with its C23 meaning.
>>  Such uses are intended to be limited to macro-local variables.'
> 
> Why limiting to macros?

Because, if I understood Andrew correctly, the specific goal is to help limit
what macros expand to.

Jan


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	, Stefano Stabellini ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH] docs/misra: fix sphinx-build issues
Thread-Topic: [PATCH] docs/misra: fix sphinx-build issues
Thread-Index: AQHcDbJCdYlsiZdfl0mX5ViIXi0+6LRjZcaAgAAeAoCAACUOAA==
Date: Fri, 15 Aug 2025 12:42:52 +0000
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Date: Fri, 15 Aug 2025 14:50:37 +0200
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Subject: Re: [PATCH v3 12/20] xen/riscv: implement p2m_set_range()
To: Oleksii Kurochko 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 
 
 <62a3c3ef-1f19-4fac-b967-f7730e8f235f@gmail.com>
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On 15.08.2025 11:52, Oleksii Kurochko wrote:
> On 8/5/25 6:04 PM, Jan Beulich wrote:
>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>> This patch introduces p2m_set_range() and its core helper p2m_set_entry() for
>> Nit: This patch doesn't introduce p2m_set_range(); it merely fleshes it out.
>>
>>> --- a/xen/arch/riscv/include/asm/p2m.h
>>> +++ b/xen/arch/riscv/include/asm/p2m.h
>>> @@ -7,11 +7,13 @@
>>>   #include 
>>>   #include 
>>>   
>>> +#include 
>>>   #include 
>>>   
>>>   extern unsigned int p2m_root_order;
>>>   #define P2M_ROOT_ORDER  p2m_root_order
>>>   #define P2M_ROOT_PAGES  BIT(P2M_ROOT_ORDER, U)
>>> +#define P2M_ROOT_LEVEL  HYP_PT_ROOT_LEVEL
>> I think I commented on this before, and I would have hoped for at least a remark
>> in the description to appear (perhaps even a comment here): It's okay(ish) to tie
>> these together for now, but in the longer run I don't expect this is going to be
>> wanted. If e.g. we ran Xen in Sv57 mode, there would be no reason at all to force
>> all P2Ms to use 5 levels of page tables.
> 
> Do you mean that for G-stage it could be chosen any SvXX mode to limit an amount
> of page tables necessary for G-stage? If yes, then, at least, I agree that a
> comment should be added or, probably, "#warning optimize an amount of p2m root level
> for MMU mode > Sv48" (or maybe >=).

Yes.

> Or do you mean if we set hgatp.mode=Sv57 then it is possible to limit an amount of
> page table's levels to use? In this case I think hardware still will expect to see
> 5 levels of page tables.

No.

>>> +static inline void p2m_write_pte(pte_t *p, pte_t pte, bool clean_pte)
>>> +{
>>> +    write_pte(p, pte);
>>> +    if ( clean_pte )
>>> +        clean_dcache_va_range(p, sizeof(*p));
>> Not necessarily for right away, but if multiple adjacent PTEs are
>> written without releasing the lock, this then redundant cache flushing
>> can be a performance issue.
> 
> Can't it be resolved on a caller side? Something like:
>    p2m_write_pte(p1, pte1, false);
>    p2m_write_pte(p2, pte2, false);
>    p2m_write_pte(p3, pte3, false);
>    p2m_write_pte(p4, pte4, true);
> where p1-p4 are adjacent.

No. You wouldn't know whether the last write flushes what the earlier
three have written. There may be a cacheline boundary in between. Plus
I didn't really think of back-to-back writes, but e.g. a loop doing
many of them, where a single wider flush may then be more efficient.

>>> +#define P2M_TABLE_MAP_NONE 0
>>> +#define P2M_TABLE_MAP_NOMEM 1
>>> +#define P2M_TABLE_SUPER_PAGE 2
>>> +#define P2M_TABLE_NORMAL 3
>>> +
>>> +/*
>>> + * Take the currently mapped table, find the corresponding the entry
>>> + * corresponding to the GFN, and map the next table, if available.
>> Nit: Double "corresponding".
>>
>>> + * The previous table will be unmapped if the next level was mapped
>>> + * (e.g P2M_TABLE_NORMAL returned).
>>> + *
>>> + * `alloc_tbl` parameter indicates whether intermediate tables should
>>> + * be allocated when not present.
>>> + *
>>> + * Return values:
>>> + *  P2M_TABLE_MAP_NONE: a table allocation isn't permitted.
>>> + *  P2M_TABLE_MAP_NOMEM: allocating a new page failed.
>>> + *  P2M_TABLE_SUPER_PAGE: next level or leaf mapped normally.
>>> + *  P2M_TABLE_NORMAL: The next entry points to a superpage.
>>> + */
>>> +static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl,
>>> +                          unsigned int level, pte_t **table,
>>> +                          unsigned int offset)
>>> +{
>>> +    panic("%s: hasn't been implemented yet\n", __func__);
>>> +
>>> +    return P2M_TABLE_MAP_NONE;
>>> +}
>>> +
>>> +/* Free pte sub-tree behind an entry */
>>> +static void p2m_free_subtree(struct p2m_domain *p2m,
>>> +                             pte_t entry, unsigned int level)
>>> +{
>>> +    panic("%s: hasn't been implemented yet\n", __func__);
>>> +}
>>> +
>>> +/*
>>> + * Insert an entry in the p2m. This should be called with a mapping
>>> + * equal to a page/superpage.
>>> + */
>>> +static int p2m_set_entry(struct p2m_domain *p2m,
>>> +                           gfn_t gfn,
>>> +                           unsigned long page_order,
>>> +                           mfn_t mfn,
>>> +                           p2m_type_t t)
>>> +{
>>> +    unsigned int level;
>>> +    unsigned int target = page_order / PAGETABLE_ORDER;
>>> +    pte_t *entry, *table, orig_pte;
>>> +    int rc;
>>> +    /* A mapping is removed if the MFN is invalid. */
>>> +    bool removing_mapping = mfn_eq(mfn, INVALID_MFN);
>> Comment and code don't fit together. Many MFNs are invalid (any for which
>> mfn_valid() returns false), yet you only check for INVALID_MFN here.
> 
> Probably, it makes sense to add an|ASSERT()| here for the case when
> |mfn_valid(mfn)| is false, but the MFN is not explicitly equal to|INVALID_MFN|.
> This would indicate that someone attempted to perform a mapping with an
> incorrect MFN, which, IMO, is entirely wrong.

No, and we've been there before. MMIO can live anywhere, and mappings for
such still will need to be permitted. It is correct to check only for
INVALID_MFN here imo; it's just the comment which also needs to reflect
that.

>>> +    /*
>>> +     * If we are here with level > target, we must be at a leaf node,
>>> +     * and we need to break up the superpage.
>>> +     */
>>> +    if ( level > target )
>>> +    {
>>> +        panic("Shattering isn't implemented\n");
>>> +    }
>>> +
>>> +    /*
>>> +     * We should always be there with the correct level because all the
>>> +     * intermediate tables have been installed if necessary.
>>> +     */
>>> +    ASSERT(level == target);
>>> +
>>> +    orig_pte = *entry;
>>> +
>>> +    if ( removing_mapping )
>>> +        p2m_clean_pte(entry, p2m->clean_pte);
>>> +    else
>>> +    {
>>> +        pte_t pte = p2m_pte_from_mfn(mfn, t);
>>> +
>>> +        p2m_write_pte(entry, pte, p2m->clean_pte);
>>> +
>>> +        p2m->max_mapped_gfn = gfn_max(p2m->max_mapped_gfn,
>>> +                                      gfn_add(gfn, BIT(page_order, UL) - 1));
>>> +        p2m->lowest_mapped_gfn = gfn_min(p2m->lowest_mapped_gfn, gfn);
>>> +    }
>>> +
>>> +    p2m->need_flush = true;
>>> +
>>> +    /*
>>> +     * Currently, the infrastructure required to enable CONFIG_HAS_PASSTHROUGH
>>> +     * is not ready for RISC-V support.
>>> +     *
>>> +     * When CONFIG_HAS_PASSTHROUGH=y, iommu_iotlb_flush() should be done
>>> +     * here.
>>> +     */
>>> +#ifdef CONFIG_HAS_PASSTHROUGH
>>> +#   error "add code to flush IOMMU TLB"
>>> +#endif
>>> +
>>> +    rc = 0;
>>> +
>>> +    /*
>>> +     * Free the entry only if the original pte was valid and the base
>>> +     * is different (to avoid freeing when permission is changed).
>>> +     */
>>> +    if ( pte_is_valid(orig_pte) &&
>>> +         !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) )
>> I'm puzzled by this 2nd check: A permission change would - I expect - only
>> occur to a leaf entry. If the new entry is a super-page one and the old
>> wasn't, don't you still need to free the sub-tree, no matter whether the
>> MFNs are the same?
> 
> I expect the MFNs to differ in this scenario, so the old sub-tree will be freed.

You expecting something isn't a good criteria. If it's possible, even if
unexpected (by you), it needs dealing with correctly.

> Based on your example (new entry is super-page and old entry isn't):
> For old mapping (lets say, 4 KiB leaf) p2m_set_entry() walks all levels down
> to L0, so we will have the following MMU page table walks:
>    L2 PTE -> L1 PTE (MFN of L0 page table) -> L0 PTE -> RAM
> 
> When new mapping (lets say, 2 MiB superpage) will be requested, p2m_set_entry()
> will stop at L1 (the superpage level):
>   L2 PTE -> L1 PTE (at this moment, L1 PTE points to L0 page table, which
>                     points to RAM)
> Then the old L1 PTE will be saved in 'orig_pte', then writes 'entry' with
> the RAM MFN for the 2 MiB mapping. The walk becomes:
>    L2 PTE -> L1 PTE -> RAM
> 
> Therefore, 'entry' now holds an MFN pointing to RAM (superpage leaf). 'orig_pte'
> still holds an MFN pointing to the L0 table (the old sub-tree). Since these MFNs
> differ, the code calls p2m_free_subtree(p2m, orig_pte, …) and frees the old L0
> sub-tree.

A particular example doesn't help. All possible cases need handling correctly.

>>   Plus consider the special case of MFN 0: If you clear
>> an entry using MFN 0, you will find old and new PTEs' both having the same
>> MFN.
> 
> Isn't this happen only when a mapping removal is explicitly requested?
> In the case of a mapping removal it seems to me it is enough just to
> clear PTE with all zeroes.

Correct. Which means original MFN (PPN) and new MFN (PPN) would match.

Jan


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Subject: Re: [PATCH] docs/misra: fix sphinx-build issues
To: Dmytro Prokopchuk1 
Cc: Andrew Cooper ,
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 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
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On 15.08.2025 14:42, Dmytro Prokopchuk1 wrote:
> On 8/15/25 13:30, Dmytro Prokopchuk wrote:
>> On 8/15/25 11:42, Jan Beulich wrote:
>>> On 15.08.2025 09:00, Dmytro Prokopchuk1 wrote:
>>>> --- a/docs/misra/deviations.rst
>>>> +++ b/docs/misra/deviations.rst
>>>> @@ -95,7 +95,8 @@ Deviations related to MISRA C:2012 Rules:
>>>>          the absence of reports that do not have an impact on safety, 
>>>> despite
>>>>          being true positives.
>>>>          Xen expects developers to ensure code remains safe and 
>>>> reliable in builds,
>>>> -       even when debug-only assertions like `ASSERT_UNREACHABLE() 
>>>> are removed.
>>>> +       even when debug-only assertions like `ASSERT_UNREACHABLE()` 
>>>> are removed.
>>>> +     - ECLAIR has been configured to ignore those statements.
>>>
>>> Mind me asking why one form of quoting is used here (using back-tick), 
>>> while ...
>>>
>>>> --- a/docs/misra/rules.rst
>>>> +++ b/docs/misra/rules.rst
>>>> @@ -124,7 +124,7 @@ maintainers if you want to suggest a change.
>>>>              they are used to generate definitions for asm modules
>>>>            - Declarations without initializer are safe, as they are not
>>>>              executed
>>>> -         - Functions that are no-return due to calls to the 
>>>> `ASSERT_UNREACHABLE()'
>>>> +         - Functions that are no-return due to calls to the 
>>>> 'ASSERT_UNREACHABLE()'
>>>
>>> ... another is used here (single quotes)?
>>>
>>> Jan
>>
>> Good question...
>> I'll align a style.
>>
>> Dmytro.
> 
> Well, the deviations.rst and rules.rst files have a mixed style.
> Sometimes file names are in '', and sometimes in ``.
> The same inconsistency applies to referring to code.
> 
> Any style suggestions?

That depends on how both quoting styles are treated by Sphinx. Which is
something I don't know. I merely noticed the inconsistency within this
single patch.

Jan


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Subject: Re: [PATCH] x86/hvm/ioreq: Fix condition in
 hvm_alloc_legacy_ioreq_gfn()
To: Oleksandr Tyshchenko ,
 "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
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On 15.08.2025 12:19, Oleksandr Tyshchenko wrote:
> Fix the incorrect condition that causes hvm_alloc_legacy_ioreq_gfn()
> to return INVALID_GFN even if the HVM param was installed properly by
> the toolstack.
> 
> Fixes: 3486f398a3dd (' x86/hvm/ioreq: allow ioreq servers to use HVM_PARAM_[BUF]IOREQ_PFN')
> Signed-off-by: Oleksandr Tyshchenko 

Reviewed-by: Jan Beulich 



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Subject: Re: [PATCH 18/22] x86/traps: Set MSR_PL0_SSP in load_system_tables()
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-19-andrew.cooper3@citrix.com>
 <74a76087-e45e-4d7a-8df3-2711f77eea2a@suse.com>
 
 <2377fe95-2c04-4b71-8bdd-ea61996c82a4@suse.com>
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From: Andrew Cooper 
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On 15/08/2025 9:52 am, Jan Beulich wrote:
> On 14.08.2025 21:37, Andrew Cooper wrote:
>> On 14/08/2025 4:00 pm, Jan Beulich wrote:
>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>> --- a/xen/arch/x86/boot/x86_64.S
>>>> +++ b/xen/arch/x86/boot/x86_64.S
>>>> @@ -65,17 +65,11 @@ ENTRY(__high_start)
>>>>          or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %rdx
>>>>  
>>>>          /*
>>>> -         * Write a new supervisor token.  Doesn't matter on boot, but for S3
>>>> -         * resume this clears the busy bit.
>>>> +         * Write a new Supervisor Token.  It doesn't matter the first time a
>>>> +         * CPU boots, but for S3 resume or CPU hot re-add, this clears the
>>>> +         * busy bit.
>>>>           */
>>>>          wrssq   %rdx, (%rdx)
>>>> -
>>>> -        /* Point MSR_PL0_SSP at the token. */
>>>> -        mov     $MSR_PL0_SSP, %ecx
>>>> -        mov     %edx, %eax
>>>> -        shr     $32, %rdx
>>>> -        wrmsr
>>>> -
>>>>          setssbsy
>>> This is ending up a little odd: The comment says the write is to clear the
>>> busy bit, when that's re-set immediately afterwards.
>> That comment is about the wrssq.  I suppose what isn't said is that
>> setssbsy will fault if not.  How about ", so SETSSBSY can set it again" ?
> That would improve things, but then it's still unclear to me why we need to
> go through this. If the busy bit is already set, why clear it just to set
> it again.

Because the behaviour of SETSSBSY is along the lines of:

    if ( test_and_set(busy) )
        SSP = token;
    else
        #GP

It really is quite an ugly instruction, and I'm not sorry to see it go.

> Or perhaps asked differently: Wouldn't we be better off if we
> cleared the busy bit when a CPU went offline?

That's actually quite hard.  The shadow stack is in use until the CPU
takes an INIT, so ought to have it's busy bit set.

In practice, clearing the primary shstk busy bit is probably safe to do
when we're certain we'll never return to PV context again.

But this is still a larger change (needs wrss() in every play dead) and
more fragile than just clearing it before we're about to use the stack
fresh.

~Andrew


From xen-devel-bounces@lists.xenproject.org Fri Aug 15 14:16:04 2025
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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Andrew Cooper
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Subject: [PATCH v2] docs/misra: fix sphinx-build issues
Thread-Topic: [PATCH v2] docs/misra: fix sphinx-build issues
Thread-Index: AQHcDe8as9q/ao3zhECV/xRhyhAMwQ==
Date: Fri, 15 Aug 2025 14:15:50 +0000
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Fix the following issues:
1. xen/docs/misra/deviations.rst:90: WARNING: Inline interpreted text or
phrase reference start-string without end-string. [docutils]
2. xen/docs/misra/deviations.rst:54: ERROR: Error parsing content block
for the "list-table" directive: uniform two-level bullet list expected,
but row 6 does not contain the same number of items as row 1 (2 vs 3).
* - R2.1
  - Calls to the `__builtin_unreachable()` function inside the expansion of
    the `ASSERT_UNREACHABLE()` macro may cause a function to be marked as
    non-returning. This behavior occurs only in configurations where
    assertions are enabled. To address this, the `noreturn` property for
    `__builtin_unreachable()` is overridden in these contexts, resulting in
    the absence of reports that do not have an impact on safety, despite
    being true positives.
    Xen expects developers to ensure code remains safe and reliable in buil=
ds,
    even when debug-only assertions like `ASSERT_UNREACHABLE() are removed.
3. xen/docs/misra/rules.rst:127: WARNING: Inline interpreted text or phrase
reference start-string without end-string. [docutils]
4. remove backticks from references to source code in the file rules.rst
to have a consistent style in this file

Signed-off-by: Dmytro Prokopchuk 
Reviewed-by: Nicola Vetrini 
Reviewed-by: Andrew Cooper 
---
Link to v1:
https://patchew.org/Xen/fb809a94e8a50bd3a59aa47ee1832c61af8a9f40.1755241166=
.git.dmytro._5Fprokopchuk1@epam.com/

Changes in v2:
- updated commit message (item 4)
- added review tags
- in the file rules.rst, removed backticks from references to source code
---
 docs/misra/deviations.rst | 3 ++-
 docs/misra/rules.rst      | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 3c46a1e47a..2be49076e1 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -95,7 +95,8 @@ Deviations related to MISRA C:2012 Rules:
        the absence of reports that do not have an impact on safety, despit=
e
        being true positives.
        Xen expects developers to ensure code remains safe and reliable in =
builds,
-       even when debug-only assertions like `ASSERT_UNREACHABLE() are remo=
ved.
+       even when debug-only assertions like `ASSERT_UNREACHABLE()` are rem=
oved.
+     - ECLAIR has been configured to ignore those statements.
=20
    * - R2.2
      - Proving compliance with respect to Rule 2.2 is generally impossible=
:
diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
index 6812eb7e8a..be315bc991 100644
--- a/docs/misra/rules.rst
+++ b/docs/misra/rules.rst
@@ -119,12 +119,12 @@ maintainers if you want to suggest a change.
          - Switch with a controlling value statically determined not to
            match one or more case statements
          - Functions that are intended to be referenced only from
-           assembly code (e.g. 'do_trap_fiq')
+           assembly code (e.g. do_trap_fiq)
          - asm-offsets.c, as they are not linked deliberately, because
            they are used to generate definitions for asm modules
          - Declarations without initializer are safe, as they are not
            executed
-         - Functions that are no-return due to calls to the `ASSERT_UNREAC=
HABLE()'
+         - Functions that are no-return due to calls to the ASSERT_UNREACH=
ABLE()
            macro in debug build configurations are not considered violatio=
ns::
=20
               static inline bool
@@ -413,8 +413,8 @@ maintainers if you want to suggest a change.
        and any other type
      - All conversions to integer types are permitted if the destination
        type has enough bits to hold the entire value. Conversions to bool
-       and void* are permitted. Conversions from 'void noreturn (*)(...)'
-       to 'void (*)(...)' are permitted.
+       and void* are permitted. Conversions from void noreturn (*)(...)
+       to void (*)(...) are permitted.
=20
    * - `Rule 11.2 `_
      - Required
--=20
2.43.0


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From: Juergen Gross 
To: xen-devel@lists.xenproject.org
Cc: Juergen Gross ,
	Anthony PERARD ,
	Andrew Cooper 
Subject: [PATCH] tools/xl: hide xenstore-features behind option
Date: Fri, 15 Aug 2025 16:32:36 +0200
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In order to be able to use "xl info" before Xenstore has been started
or after it has crashed, hide obtaining the available Xenstore features
behind the new option "-x".

Fixes: ecce7970cfe7 ("tools/xl: add available Xenstore features to xl info output")
Reported-by: Andrew Cooper 
Signed-off-by: Juergen Gross 
---
 docs/man/xl.1.pod.in     |  4 ++++
 docs/man/xl.cfg.5.pod.in |  2 +-
 tools/xl/xl_info.c       | 14 ++++++++++----
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/docs/man/xl.1.pod.in b/docs/man/xl.1.pod.in
index fe38724b2b..88ccf7ad82 100644
--- a/docs/man/xl.1.pod.in
+++ b/docs/man/xl.1.pod.in
@@ -996,6 +996,10 @@ B
 
 List host NUMA topology information
 
+=item B<-x>, B<--xenstore>
+
+Show Xenstore features available.
+
 =back
 
 =item B
diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
index f0c920b39d..acff45d308 100644
--- a/docs/man/xl.cfg.5.pod.in
+++ b/docs/man/xl.cfg.5.pod.in
@@ -743,7 +743,7 @@ condition.
 =back
 
 The features supported by the running Xenstore instance can be retrieved
-via the B command in dom0.
+via the B command in dom0.
 
 The default value is B<0xffffffff>, meaning that all possible Xenstore
 features are visible by the guest.
diff --git a/tools/xl/xl_info.c b/tools/xl/xl_info.c
index eb019e3ee9..d3583cbf8f 100644
--- a/tools/xl/xl_info.c
+++ b/tools/xl/xl_info.c
@@ -353,7 +353,7 @@ static void output_xenstore_info(void)
     xs_close(xsh);
 }
 
-static void print_info(int numa)
+static void print_info(int numa, bool xs)
 {
     output_nodeinfo();
 
@@ -365,7 +365,8 @@ static void print_info(int numa)
     }
     output_xeninfo();
 
-    output_xenstore_info();
+    if (xs)
+        output_xenstore_info();
 
     maybe_printf("xend_config_format     : 4\n");
 
@@ -631,14 +632,19 @@ int main_info(int argc, char **argv)
     int opt;
     static struct option opts[] = {
         {"numa", 0, 0, 'n'},
+        {"xenstore", 0, 0, 'x'},
         COMMON_LONG_OPTS
     };
     int numa = 0;
+    bool xs = false;
 
-    SWITCH_FOREACH_OPT(opt, "n", opts, "info", 0) {
+    SWITCH_FOREACH_OPT(opt, "nx", opts, "info", 0) {
     case 'n':
         numa = 1;
         break;
+    case 'x':
+        xs = true;
+        break;
     }
 
     /*
@@ -648,7 +654,7 @@ int main_info(int argc, char **argv)
     if (numa == 0 && argc > optind)
         info_name = argv[optind];
 
-    print_info(numa);
+    print_info(numa, xs);
     return 0;
 }
 
-- 
2.43.0



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Date: Fri, 15 Aug 2025 16:35:37 +0200
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Subject: Re: [PATCH] tools/xl: hide xenstore-features behind option
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Andrew Cooper ,
 Oleksii 
References: <20250815143236.27641-1-jgross@suse.com>
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From: Juergen Gross 
To: xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Andrew Cooper ,
 Oleksii 
Message-ID: <115eca26-32a3-403f-9bf6-553c6b20940c@suse.com>
Subject: Re: [PATCH] tools/xl: hide xenstore-features behind option
References: <20250815143236.27641-1-jgross@suse.com>
In-Reply-To: <20250815143236.27641-1-jgross@suse.com>

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Subject: Re: [PATCH] tools/xl: hide xenstore-features behind option
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On 15/08/2025 3:32 pm, Juergen Gross wrote:
> In order to be able to use "xl info" before Xenstore has been started
> or after it has crashed, hide obtaining the available Xenstore features
> behind the new option "-x".
>
> Fixes: ecce7970cfe7 ("tools/xl: add available Xenstore features to xl info output")
> Reported-by: Andrew Cooper 
> Signed-off-by: Juergen Gross 

Probably ought to be Reported-by Ross Lagerwall.  He did all the hard
work debugging this; I just insisted that the conversation move onto Matrix.

For the change itself, Reviewed-by: Andrew Cooper



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Subject: Re: [PATCH] tools/xl: hide xenstore-features behind option
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Cc: Anthony PERARD 
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To: Andrew Cooper , xen-devel@lists.xenproject.org
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Subject: Re: [PATCH] tools/xl: hide xenstore-features behind option
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 <3ef1fc73-601c-4de0-b94e-bbf9cc27d081@citrix.com>
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Subject: Re: [PATCH] tools/xl: hide xenstore-features behind option
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Cc: Anthony PERARD 
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On 15/08/2025 3:39 pm, Jürgen Groß wrote:
> On 15.08.25 16:36, Andrew Cooper wrote:
>> On 15/08/2025 3:32 pm, Juergen Gross wrote:
>>> In order to be able to use "xl info" before Xenstore has been started
>>> or after it has crashed, hide obtaining the available Xenstore features
>>> behind the new option "-x".
>>>
>>> Fixes: ecce7970cfe7 ("tools/xl: add available Xenstore features to
>>> xl info output")
>>> Reported-by: Andrew Cooper 
>>> Signed-off-by: Juergen Gross 
>>
>> Probably ought to be Reported-by Ross Lagerwall.  He did all the hard
>> work debugging this; I just insisted that the conversation move onto
>> Matrix.
>>
>> For the change itself, Reviewed-by: Andrew Cooper
>> 
>
> Thanks.
>
> Should I send V2 with the "Reported-by" corrected, or can this be done
> when committing?

Happy to fix on commit.

~Andrew


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On 8/14/25 12:03, Roger Pau Monne wrote:
> It's possible for the BAR rangeset to contain stale data when used in
> modify_bars() if previous calls to modify_bars() resulted in errors.
> 
> Fix by always purging the rangeset before usage, thus getting rid of any
> previous stale data.  Remove the ASSERT that checked whether the rangeset
> was empty, it was incorrect.
> 
> Fixes: 52ebde3cfae2 ('vpci/header: program p2m with guest BAR view')
> Signed-off-by: Roger Pau Monné 

Reviewed-by: Stewart Hildebrand 


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On 8/14/25 12:03, Roger Pau Monne wrote:
> The logic in map_range() will bubble up failures to the upper layer, which
> will result in any remaining regions being skip, and for the non-hardware
> domain case the owner domain of the device would be destroyed.  However for
> the hardware domain the intent is to continue execution, hopping the
> failure to modify the p2m could be worked around by the hardware domain.
> 
> To accomplish that in a better way, ignore failures and skip the range in
> that case, possibly continuing to map further ranges.
> 
> Since the error path in vpci_process_pending() should only be used by domUs
> now, and it will unconditionally end up calling domain_crash(), simplify
> it: there's no need to cleanup if the domain will be destroyed.
> 
> No functional change for domUs intended.
> 
> Signed-off-by: Roger Pau Monné 
> ---
>  xen/drivers/vpci/header.c | 51 +++++++++++++++++++++------------------
>  1 file changed, 28 insertions(+), 23 deletions(-)
> 
> diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
> index b9756b364300..1035dcca242d 100644
> --- a/xen/drivers/vpci/header.c
> +++ b/xen/drivers/vpci/header.c
> @@ -64,7 +64,8 @@ static int cf_check map_range(
>              printk(XENLOG_G_WARNING
>                     "%pd denied access to MMIO range [%#lx, %#lx]\n",
>                     map->d, map_mfn, m_end);
> -            return -EPERM;
> +            rc = -EPERM;
> +            goto done;
>          }
>  
>          rc = xsm_iomem_mapping(XSM_HOOK, map->d, map_mfn, m_end, map->map);
> @@ -73,7 +74,7 @@ static int cf_check map_range(
>              printk(XENLOG_G_WARNING
>                     "%pd XSM denied access to MMIO range [%#lx, %#lx]: %d\n",
>                     map->d, map_mfn, m_end, rc);
> -            return rc;
> +            goto done;
>          }
>  
>          /*
> @@ -87,17 +88,27 @@ static int cf_check map_range(
>  
>          rc = map->map ? map_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn))
>                        : unmap_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn));
> -        if ( rc == 0 )
> -        {
> -            *c += size;
> -            break;
> -        }
>          if ( rc < 0 )
>          {
>              printk(XENLOG_G_WARNING
>                     "Failed to %smap [%lx %lx] -> [%lx %lx] for %pd: %d\n",
>                     map->map ? "" : "un", s, e, map_mfn,
>                     map_mfn + size, map->d, rc);
> +            goto done;
> +        }
> +        if ( rc == 0 )
> +        {
> + done:
> +            if ( is_hardware_domain(map->d) )
> +            {
> +                /*
> +                 * Ignore failures for the hardware domain and skip the range.
> +                 * Do it as a best effort workaround to attempt to get the
> +                 * hardware domain to boot.
> +                 */
> +                rc = 0;

If we return success and size is zero, we will potentially attempt to map/unmap
the same region again in an infinite loop. rangeset_consume_ranges would invoke
map_range again directly without returning to vpci_process_pending.

> +                *c += size;

This line is now only executed for hwdom, but ...

> +            }

... it should go outside of the hwdom check because domUs still need it.

>              break;
>          }
>          ASSERT(rc < size);
> @@ -213,28 +224,22 @@ bool vpci_process_pending(struct vcpu *v)
>              return true;
>          }
>  
> -        if ( rc )
> +        if ( rc && !is_hardware_domain(v->domain) )
>          {
> -            spin_lock(&pdev->vpci->lock);
> -            /* Disable memory decoding unconditionally on failure. */
> -            modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY,
> -                            false);

This path could be taken for either map or unmap. Do we still want to disable
memory decoding in case of unmap?

> -            spin_unlock(&pdev->vpci->lock);
> -
> -            /* Clean all the rangesets */
> -            for ( i = 0; i < ARRAY_SIZE(header->bars); i++ )
> -                if ( !rangeset_is_empty(header->bars[i].mem) )
> -                     rangeset_purge(header->bars[i].mem);
> -
> -            v->vpci.pdev = NULL;
> -
>              read_unlock(&v->domain->pci_lock);
>  
> -            if ( !is_hardware_domain(v->domain) )
> -                domain_crash(v->domain);
> +            domain_crash(v->domain);
>  
>              return false;
>          }
> +        ASSERT(!rc);
> +        /*
> +         * Purge rangeset to deal with the hardware domain having triggered an
> +         * error.  It shouldn't be possible, as map_range() will always shallow
> +         * errors for hardware domain owned devices, and
> +         * rangeset_consume_ranges() itself doesn't generate any errors.
> +         */
> +        rangeset_purge(bar->mem);

Reiterating what was mentioned above: if map_range returned 0 without
incrementing *c, we won't make it back here.

>      }
>      v->vpci.pdev = NULL;
>  



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Date: Fri, 15 Aug 2025 12:23:40 -0700 (PDT)
From: Stefano Stabellini 
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To: Penny Zheng 
cc: xen-devel@lists.xenproject.org, ray.huang@amd.com, 
    Jan Beulich , Andrew Cooper , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Anthony PERARD , 
    Michal Orzel , Julien Grall , 
    Stefano Stabellini 
Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
In-Reply-To: <20250815102728.1340505-1-Penny.Zheng@amd.com>
Message-ID: 
References: <20250815102728.1340505-1-Penny.Zheng@amd.com>
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On Fri, 15 Aug 2025, Penny Zheng wrote:
> In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and
> HVM=y results in hvm.c being built, but domctl.c not being built, which leaves
> a few functions, like domctl_lock_acquire/release() undefined, causing linking
> to fail.
> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile
> /hypercall-defs section, with this adjustment, we also need to release
> redundant vnuma_destroy() stub definition from PV_SHIM_EXCLUSIVE guardian,
> to not break compilation
> Above change will leave dead code in the shim binary temporarily and will be
> fixed with the introduction of domctl-op wrapping.
> 
> Fixes: 568f806cba4c ("xen/x86: remove "depends on !PV_SHIM_EXCLUSIVE"")
> Reported-by: Jan Beulich 
> Signed-off-by: Penny Zheng 

Reviewed-by: Stefano Stabellini 



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On 8/15/25 14:53, Stewart Hildebrand wrote:
> On 8/14/25 12:03, Roger Pau Monne wrote:
>> The logic in map_range() will bubble up failures to the upper layer, which
>> will result in any remaining regions being skip, and for the non-hardware
>> domain case the owner domain of the device would be destroyed.  However for
>> the hardware domain the intent is to continue execution, hopping the
>> failure to modify the p2m could be worked around by the hardware domain.
>>
>> To accomplish that in a better way, ignore failures and skip the range in
>> that case, possibly continuing to map further ranges.
>>
>> Since the error path in vpci_process_pending() should only be used by domUs
>> now, and it will unconditionally end up calling domain_crash(), simplify
>> it: there's no need to cleanup if the domain will be destroyed.
>>
>> No functional change for domUs intended.
>>
>> Signed-off-by: Roger Pau Monné 
>> ---
>>  xen/drivers/vpci/header.c | 51 +++++++++++++++++++++------------------
>>  1 file changed, 28 insertions(+), 23 deletions(-)
>>
>> diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
>> index b9756b364300..1035dcca242d 100644
>> --- a/xen/drivers/vpci/header.c
>> +++ b/xen/drivers/vpci/header.c
>> @@ -64,7 +64,8 @@ static int cf_check map_range(
>>              printk(XENLOG_G_WARNING
>>                     "%pd denied access to MMIO range [%#lx, %#lx]\n",
>>                     map->d, map_mfn, m_end);
>> -            return -EPERM;
>> +            rc = -EPERM;
>> +            goto done;
>>          }
>>  
>>          rc = xsm_iomem_mapping(XSM_HOOK, map->d, map_mfn, m_end, map->map);
>> @@ -73,7 +74,7 @@ static int cf_check map_range(
>>              printk(XENLOG_G_WARNING
>>                     "%pd XSM denied access to MMIO range [%#lx, %#lx]: %d\n",
>>                     map->d, map_mfn, m_end, rc);
>> -            return rc;
>> +            goto done;
>>          }
>>  
>>          /*
>> @@ -87,17 +88,27 @@ static int cf_check map_range(
>>  
>>          rc = map->map ? map_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn))
>>                        : unmap_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn));
>> -        if ( rc == 0 )
>> -        {
>> -            *c += size;
>> -            break;
>> -        }
>>          if ( rc < 0 )
>>          {
>>              printk(XENLOG_G_WARNING
>>                     "Failed to %smap [%lx %lx] -> [%lx %lx] for %pd: %d\n",
>>                     map->map ? "" : "un", s, e, map_mfn,
>>                     map_mfn + size, map->d, rc);
>> +            goto done;
>> +        }
>> +        if ( rc == 0 )
>> +        {
>> + done:
>> +            if ( is_hardware_domain(map->d) )
>> +            {
>> +                /*
>> +                 * Ignore failures for the hardware domain and skip the range.
>> +                 * Do it as a best effort workaround to attempt to get the
>> +                 * hardware domain to boot.
>> +                 */
>> +                rc = 0;
> 
> If we return success and size is zero, we will potentially attempt to map/unmap
> the same region again in an infinite loop. rangeset_consume_ranges would invoke
> map_range again directly without returning to vpci_process_pending.

Sorry, I sent the previous email too soon, I see now that it shouldn't be
possible for size to be zero.

> 
>> +                *c += size;
> 
> This line is now only executed for hwdom, but ...
> 
>> +            }
> 
> ... it should go outside of the hwdom check because domUs still need it.
> 
>>              break;
>>          }
>>          ASSERT(rc < size);
>> @@ -213,28 +224,22 @@ bool vpci_process_pending(struct vcpu *v)
>>              return true;
>>          }
>>  
>> -        if ( rc )
>> +        if ( rc && !is_hardware_domain(v->domain) )
>>          {
>> -            spin_lock(&pdev->vpci->lock);
>> -            /* Disable memory decoding unconditionally on failure. */
>> -            modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY,
>> -                            false);
> 
> This path could be taken for either map or unmap. Do we still want to disable
> memory decoding in case of unmap?
> 
>> -            spin_unlock(&pdev->vpci->lock);
>> -
>> -            /* Clean all the rangesets */
>> -            for ( i = 0; i < ARRAY_SIZE(header->bars); i++ )
>> -                if ( !rangeset_is_empty(header->bars[i].mem) )
>> -                     rangeset_purge(header->bars[i].mem);
>> -
>> -            v->vpci.pdev = NULL;
>> -
>>              read_unlock(&v->domain->pci_lock);
>>  
>> -            if ( !is_hardware_domain(v->domain) )
>> -                domain_crash(v->domain);
>> +            domain_crash(v->domain);
>>  
>>              return false;
>>          }
>> +        ASSERT(!rc);
>> +        /*
>> +         * Purge rangeset to deal with the hardware domain having triggered an
>> +         * error.  It shouldn't be possible, as map_range() will always shallow
>> +         * errors for hardware domain owned devices, and
>> +         * rangeset_consume_ranges() itself doesn't generate any errors.
>> +         */
>> +        rangeset_purge(bar->mem);
> 
> Reiterating what was mentioned above: if map_range returned 0 without
> incrementing *c, we won't make it back here.
> 
>>      }
>>      v->vpci.pdev = NULL;
>>  


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Date: Fri, 15 Aug 2025 12:27:51 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Juergen Gross 
cc: linux-kernel@vger.kernel.org, Stefano Stabellini , 
    Oleksandr Tyshchenko , 
    xen-devel@lists.xenproject.org
Subject: Re: [PATCH] drivers/xen/xenbus: remove quirk for Xen 3.x
In-Reply-To: <20250815074052.13792-1-jgross@suse.com>
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On Fri, 15 Aug 2025, Juergen Gross wrote:
> The kernel is not supported to run as a Xen guest on Xen versions
> older than 4.0.
> 
> Remove xen_strict_xenbus_quirk() which is testing the Xen version to be
> at least 4.0.
> 
> Signed-off-by: Juergen Gross 

Acked-by: Stefano Stabellini 


> ---
>  drivers/xen/xenbus/xenbus_xs.c | 23 -----------------------
>  1 file changed, 23 deletions(-)
> 
> diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c
> index 3c9da446b85d..528682bf0c7f 100644
> --- a/drivers/xen/xenbus/xenbus_xs.c
> +++ b/drivers/xen/xenbus/xenbus_xs.c
> @@ -718,26 +718,6 @@ int xs_watch_msg(struct xs_watch_event *event)
>  	return 0;
>  }
>  
> -/*
> - * Certain older XenBus toolstack cannot handle reading values that are
> - * not populated. Some Xen 3.4 installation are incapable of doing this
> - * so if we are running on anything older than 4 do not attempt to read
> - * control/platform-feature-xs_reset_watches.
> - */
> -static bool xen_strict_xenbus_quirk(void)
> -{
> -#ifdef CONFIG_X86
> -	uint32_t eax, ebx, ecx, edx, base;
> -
> -	base = xen_cpuid_base();
> -	cpuid(base + 1, &eax, &ebx, &ecx, &edx);
> -
> -	if ((eax >> 16) < 4)
> -		return true;
> -#endif
> -	return false;
> -
> -}
>  static void xs_reset_watches(void)
>  {
>  	int err;
> @@ -745,9 +725,6 @@ static void xs_reset_watches(void)
>  	if (!xen_hvm_domain() || xen_initial_domain())
>  		return;
>  
> -	if (xen_strict_xenbus_quirk())
> -		return;
> -
>  	if (!xenbus_read_unsigned("control",
>  				  "platform-feature-xs_reset_watches", 0))
>  		return;
> -- 
> 2.43.0
> 


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Date: Fri, 15 Aug 2025 12:44:01 -0700 (PDT)
From: Stefano Stabellini 
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To: Nicola Vetrini 
cc: Dmytro Prokopchuk1 , 
    xen-devel@lists.xenproject.org, Doug Goldstein , 
    Stefano Stabellini , 
    Andrew Cooper , 
    Anthony PERARD , 
    Michal Orzel , Jan Beulich , 
    Julien Grall , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Subject: Re: [PATCH v4] misra: add deviations of MISRA C Rule 5.5
In-Reply-To: <874c914eafd42020afc2087eccf4d7a3@bugseng.com>
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On Thu, 7 Aug 2025, Nicola Vetrini wrote:
> On 2025-07-31 22:43, Dmytro Prokopchuk1 wrote:
> > MISRA C Rule 5.5 states: "Identifiers shall be distinct from macro names".
> > 
> > Update ECLAIR configuration to deviate clashes: specify the macros that
> > should be ignored. Update deviations.rst and rules.rst accordingly.
> > 
> > Signed-off-by: Dmytro Prokopchuk 
> 
> Reviewed-by: Nicola Vetrini 

Acked-by: Stefano Stabellini 



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To: Nicola Vetrini 
cc: xen-devel@lists.xenproject.org, sstabellini@kernel.org, 
    consulting@bugseng.com, dmytro_prokopchuk1@epam.com, 
    andrew.cooper3@citrix.com, jbeulich@suse.com, 
    Doug Goldstein 
Subject: Re: [XEN PATCH 2/2] Address violation of MISRA C Rule 13.1 involving
 asm side effects.
In-Reply-To: 
Message-ID: 
References: <1283be3b76d76814af244bbca544f6a3b74a04de.1754689062.git.nicola.vetrini@bugseng.com> 
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On Fri, 8 Aug 2025, Nicola Vetrini wrote:
> The rule states: "Initializer lists shall not contain persistent side effects".
> The specific way in which the 'mrs' instruction is used does not lead to
> visible side effects for the surrounding code.
> 
> Signed-off-by: Nicola Vetrini 

Acked-by: Stefano Stabellini 

Ideally, with the improved doc as suggested by Dmytro.


> ---
> Not yet tested on the Xen ECLAIR runner, as the syntax used in the deviation
> is only supported after updating the runner.
> 
> What the tool is reporting is that due to the '=r' constraint and the
> semantics of the instruction, there is the side effect of writing to '_r',
> but this is not observable outside the stmt expr. The deviation ends up being
> a bit too general for my taste, but the restriction on the actual istruction
> should be enough to limit applicability to cases that are arguably safe in
> practice.
> 
> An alternative approach would be represented by stating that side effects in
> 'READ_SYSREG64' are safe, but this is not true in general.
> ---
>  automation/eclair_analysis/ECLAIR/deviations.ecl | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/eclair_analysis/ECLAIR/deviations.ecl
> index ec0cac797e5f..6b492e38505d 100644
> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -437,6 +437,10 @@ write or not"
>  # Series 13
>  #
>  
> +-doc_begin="Consider the asm instruction to read an Arm system register to have no side effects."
> +-asm_properties+={"asm(any())&&child(text, ast_field(value,^mrs\\s+%0.*$))", {no_side_effect}}
> +-doc_end
> +
>  -doc_begin="All developers and reviewers can be safely assumed to be well aware
>  of the short-circuit evaluation strategy of such logical operators."
>  -config=MC3A2.R13.5,reports+={disapplied,"any()"}
> -- 
> 2.43.0
> 


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From: Stefano Stabellini 
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To: Nicola Vetrini 
cc: Dmytro Prokopchuk1 , 
    xen-devel@lists.xenproject.org, 
    Stefano Stabellini , Julien Grall , 
    Bertrand Marquis , 
    Michal Orzel , 
    Volodymyr Babchuk 
Subject: Re: [PATCH] misra: add missing noreturn attribute for __div0()
In-Reply-To: <6aa50b8147d14e4d654f1291fc3b9cef@bugseng.com>
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References: <1b5549a97db31c65edb769302deff73576cec41d.1755013482.git.dmytro_prokopchuk1@epam.com> <6aa50b8147d14e4d654f1291fc3b9cef@bugseng.com>
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On Tue, 12 Aug 2025, Nicola Vetrini wrote:
> On 2025-08-12 17:46, Dmytro Prokopchuk1 wrote:
> > The __div0() function never returns to its caller, causing a violation
> > of MISRA C Rule 2.1: "A project shall not contain unreachable code".
> > Add the `noreturn` attribute to fix this.
> > 
> 
> I was convinced that this was already upstream, as I made a patch a while ago,
> but evidently I forgot to send it.
> 
> > Signed-off-by: Dmytro Prokopchuk 
> 
> Reviewed-by: Nicola Vetrini 

Acked-by: Stefano Stabellini 



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Date: Fri, 15 Aug 2025 12:58:47 -0700 (PDT)
From: Stefano Stabellini 
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To: Teddy Astie 
cc: Dmytro Prokopchuk1 , 
    xen-devel@lists.xenproject.org, Andrew Cooper , 
    Anthony PERARD , 
    Michal Orzel , Jan Beulich , 
    Julien Grall , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini 
Subject: Re: [PATCH] misra: address Rule 11.1 violation in cmpxchgptr()
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On Thu, 14 Aug 2025, Teddy Astie wrote:
> Hello,
> 
> Le 13/08/2025 à 20:07, Dmytro Prokopchuk1 a écrit :
> > Misra Rule 11.1 states: "Conversions shall not be performed between a
> > pointer to a function and any other type."
> >
> > The violation occurs in the macro:
> >      __typeof__(**(ptr)) *const o_ = (o);                                \
> >      __typeof__(**(ptr)) *n_ = (n);                                      \
> >      ((__typeof__(*(ptr)))__cmpxchg(ptr, (unsigned long)o_,              \
> >                                     (unsigned long)n_, sizeof(*(ptr)))); \
> > })
> > when it is used for handling function pointers of type:
> > typedef void (*)(struct vcpu *, unsigned int).
> > The issue happens because the '__cmpxchg()' function returns an 'unsigned
> > long', which is then converted back into a function pointer, causing a
> > violation of Rule 11.1. In this particular usage, the return value of the
> > macro 'cmpxchgptr()' is not required. To address the violation, the macro
> > has been replaced to discard the return value of '__cmpxchg()', preventing
> > the conversion.
> >
> > Signed-off-by: Dmytro Prokopchuk 
> > ---
> > Probably separate macro is too much for this single case.
> >
> > And the following will be enought:
> > __cmpxchg(&xen_consumers[i], (unsigned long)NULL, (unsigned long)fn, sizeof(*(&xen_consumers[i])));
> > ---
> >   xen/common/event_channel.c | 15 +++++++++++++--
> >   1 file changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
> > index 67700b050a..2094338b28 100644
> > --- a/xen/common/event_channel.c
> > +++ b/xen/common/event_channel.c
> > @@ -93,6 +93,17 @@ static void cf_check default_xen_notification_fn(
> >           vcpu_wake(v);
> >   }
> >
> > +/*
> > + * A slightly more updated variant of cmpxchgptr() where old value
> > + * is not returned.
> > + */
> > +#define cmpxchgptr_noret(ptr, o, n) ({                  \
> > +    __typeof__(**(ptr)) *const o_ = (o);                \
> > +    __typeof__(**(ptr)) *n_ = (n);                      \
> > +    (void)__cmpxchg(ptr, (unsigned long)o_,             \
> > +                    (unsigned long)n_, sizeof(*(ptr))); \
> > +})
> > +
> >   /*
> >    * Given a notification function, return the value to stash in
> >    * the evtchn->xen_consumer field.
> > @@ -106,9 +117,9 @@ static uint8_t get_xen_consumer(xen_event_channel_notification_t fn)
> >
> >       for ( i = 0; i < ARRAY_SIZE(xen_consumers); i++ )
> >       {
> > -        /* Use cmpxchgptr() in lieu of a global lock. */
> > +        /* Use cmpxchgptr_noret() in lieu of a global lock. */
> >           if ( xen_consumers[i] == NULL )
> > -            cmpxchgptr(&xen_consumers[i], NULL, fn);
> > +            cmpxchgptr_noret(&xen_consumers[i], NULL, fn);
> >           if ( xen_consumers[i] == fn )
> >               break;
> >       }
> 
> AFAICS, Rule 11.1 has a deviation which allows this specific case.
> 
> In docs/misra/deviations.rst
> > * - R11.1
> >   - The conversion from a function pointer to unsigned long or (void \*) does
> >     not lose any information, provided that the target type has enough bits
> >     to store it.
> >   - Tagged as `safe` for ECLAIR.
> 
> Here, we are constructing a function pointer from a unsigned long. I
> assume this rule goes the other way it says, and allow converting a
> unsigned long into a function pointer as long as its value is a valid
> function pointer.

You are right, we should need to update the deviation instead here:


-doc_begin="The conversion from a function pointer to unsigned long or (void *) does not lose any information, provided that the target type has enough bits to store it."
-config=MC3A2.R11.1,casts+={safe,
  "from(type(canonical(__function_pointer_types)))
   &&to(type(canonical(builtin(unsigned long)||pointer(builtin(void)))))
   &&relation(definitely_preserves_value)"
}
-doc_end

--8323329-1824684921-1755287930=:923618--


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Date: Fri, 15 Aug 2025 13:12:00 -0700 (PDT)
From: Stefano Stabellini 
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To: xen-devel@lists.xenproject.org
cc: sstabellini@kernel.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, michal.orzel@amd.com, jbeulich@suse.com, 
    julien@xen.org, roger.pau@citrix.com
Subject: [PATCH] docs/sending-patches: add GitLab pipeline link
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When submitting patches to xen-devel, add a link to a successful
pipeline run.

Signed-off-by: Stefano Stabellini 

diff --git a/docs/process/sending-patches.pandoc b/docs/process/sending-patches.pandoc
index 1991932b68..6e1401ea22 100644
--- a/docs/process/sending-patches.pandoc
+++ b/docs/process/sending-patches.pandoc
@@ -314,3 +314,23 @@ A patch should always be sent **to** the xen-devel mailing list
 of all touched code areas should get a copy of the mail via **Cc**. In case
 some other recipients are known to be interested in the patch, they can be
 added via **Cc**, too.
+
+## Testing
+
+Xen Project uses a GitLab-based CI infrastructure. You can request to
+have your GitLab account added to the Xen Project organization on GitLab
+(https://gitlab.com/xen-project) by reaching out to THE REST maintainers
+via xen-devel or Matrix. Once your account is added to the Xen Project
+organization on GitLab, also a personal Xen repository will be created
+for you under https://gitlab.com/xen-project/people//xen.
+You will be able to trigger a GitLab testing pipeline with a single git
+push to your personal Xen repository.
+
+When submitting a non-trivial patch or a non-trivial patch series,
+please include a link to the successful GitLab pipeline run on your
+personal branch. This information can be added after the `---` line.
+For example:
+
+    ---
+    Test CI pipeline:
+    https://gitlab.com/xen-project/people/your-username/xen/-/pipelines/1980129839


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Subject: Re: [PATCH 3/5] xen/vpci: simplify handling of memory decoding and
 ROM enable writes
To: Roger Pau Monne , 
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On 8/14/25 12:03, Roger Pau Monne wrote:
> Deferring the actual write of the PCI register bit, either the memory
> decoding or the ROM enable is not helpful, and adds an unnecessary amount of
> complexity to the preemptible handling of BAR related p2m modifications.
> 
> In the hardware domain case, whether the PCI register write is done ahead
> or after the p2m changes doesn't matter, a hardware domain has plenty of
> ways to mess with the PCI register state if it wants to.  Any poking at the
> BAR p2m regions ahead of the guest write having completed will be
> undefined.
> 
> On the other hand, for domUs the memory decoding bit shouldn't really
> change as a result of guest actions, and should always be enabled.  Guest
> toggling the memory decoding command register should only result in p2m
> modifications, but no propagation to the device PCI registers.  Having
> memory decoding unconditionally enabled ensures the domU attempting to
> perform p2m accesses while the p2m changes are taking place will always
> access the BAR contents. This is not the current behavior for domUs, so add
> a note that it would preferably done that way.
> 

Nit: I think you want:
Resolves: https://gitlab.com/xen-project/xen/-/issues/98

> Signed-off-by: Roger Pau Monné 
> ---
>  xen/drivers/vpci/header.c | 42 +++++++++++++++++++--------------------
>  1 file changed, 21 insertions(+), 21 deletions(-)
> 
> diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
> index 1035dcca242d..1a501a0ba47e 100644
> --- a/xen/drivers/vpci/header.c
> +++ b/xen/drivers/vpci/header.c
> @@ -163,8 +163,6 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd,
>              if ( pci_check_bar(pdev, _mfn(PFN_DOWN(bar->addr)),
>                                 _mfn(PFN_DOWN(bar->addr + bar->size - 1))) )
>                  bar->enabled = map;
> -            header->rom_enabled = map;
> -            pci_conf_write32(pdev->sbdf, rom_pos, val);

rom_pos and val are unused

drivers/vpci/header.c: In function ‘modify_decoding’:
drivers/vpci/header.c:160:22: error: unused variable ‘val’ [-Werror=unused-variable]
  160 |             uint32_t val = bar->addr |
      |                      ^~~
drivers/vpci/header.c:158:26: error: unused variable ‘rom_pos’ [-Werror=unused-variable]
  158 |             unsigned int rom_pos = (i == PCI_HEADER_NORMAL_NR_BARS)
      |                          ^~~~~~~

Other than that the patch looks good to me

>              return;
>          }
>  
> @@ -174,14 +172,6 @@ static void modify_decoding(const struct pci_dev *pdev, uint16_t cmd,
>                             _mfn(PFN_DOWN(bar->addr + bar->size - 1))) )
>              bar->enabled = map;
>      }
> -
> -    if ( !rom_only )
> -    {
> -        pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd);
> -        header->bars_mapped = map;
> -    }
> -    else
> -        ASSERT_UNREACHABLE();
>  }
>  
>  bool vpci_process_pending(struct vcpu *v)
> @@ -547,16 +537,23 @@ static void cf_check cmd_write(
>       * decoding one. Bits that are not allowed for DomU are already
>       * handled above and by the rsvdp_mask.
>       */
> -    if ( header->bars_mapped != !!(cmd & PCI_COMMAND_MEMORY) )
> +    if ( header->bars_mapped != !!(cmd & PCI_COMMAND_MEMORY) &&
> +         modify_bars(pdev, cmd, false) )
>          /*
>           * Ignore the error. No memory has been added or removed from the p2m
>           * (because the actual p2m changes are deferred in defer_map) and the
>           * memory decoding bit has not been changed, so leave everything as-is,
>           * hoping the guest will realize and try again.
>           */
> -        modify_bars(pdev, cmd, false);
> -    else
> -        pci_conf_write16(pdev->sbdf, reg, cmd);
> +        return;
> +
> +    /*
> +     * FIXME: for domUs we don't want the guest toggling the memory decoding
> +     * bit.  It should be set in vpci_init_header() and guest attempts to
> +     * modify it should only lead to guest p2m changes.
> +     */
> +    header->bars_mapped = cmd & PCI_COMMAND_MEMORY;
> +    pci_conf_write16(pdev->sbdf, reg, cmd);
>  }
>  
>  static uint32_t cf_check guest_cmd_read(
> @@ -712,17 +709,11 @@ static void cf_check rom_write(
>          rom->guest_addr = rom->addr;
>      }
>  
> -    if ( !header->bars_mapped || rom->enabled == new_enabled )
> -    {
> -        /* Just update the ROM BAR field. */
> -        header->rom_enabled = new_enabled;
> -        pci_conf_write32(pdev->sbdf, reg, val);
> -    }
>      /*
>       * Pass PCI_COMMAND_MEMORY or 0 to signal a map/unmap request, note that
>       * this fabricated command is never going to be written to the register.
>       */
> -    else if ( modify_bars(pdev, new_enabled ? PCI_COMMAND_MEMORY : 0, true) )
> +    if ( modify_bars(pdev, new_enabled ? PCI_COMMAND_MEMORY : 0, true) )
>          /*
>           * No memory has been added or removed from the p2m (because the actual
>           * p2m changes are deferred in defer_map) and the ROM enable bit has
> @@ -733,6 +724,8 @@ static void cf_check rom_write(
>           */
>          return;
>  
> +    header->rom_enabled = new_enabled;
> +    pci_conf_write32(pdev->sbdf, reg, val);
>      if ( !new_enabled )
>      {
>          rom->addr = val & PCI_ROM_ADDRESS_MASK;
> @@ -1057,6 +1050,13 @@ int vpci_init_header(struct pci_dev *pdev)
>              goto fail;
>      }
>  
> +    if ( cmd & PCI_COMMAND_MEMORY )
> +    {
> +        /* Restore command register value. */
> +        header->bars_mapped = true;
> +        pci_conf_write16(pdev->sbdf, PCI_COMMAND, cmd);
> +    }
> +
>      return (cmd & PCI_COMMAND_MEMORY) ? modify_bars(pdev, cmd, false) : 0;
>  
>   fail:



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 00/16] x86/msr: Cleanup and FRED prep
Date: Fri, 15 Aug 2025 21:41:01 +0100
Message-Id: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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This started as the final couple of patches, and escalated...

Some has been posted before, two even back in 2018 (work literally done in
Nanjing airport leaving XenSummit, and there was an 8h delay).  The rest is
FRED prep work, targetted for 4.21.

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1986711791

Andrew Cooper (16):
  x86/msr: Implement rdmsr_safe() in C
  x86/msr: Rework rdmsr_safe() using asm goto()
  x86: Sort headers
  x86/msr: Split out guest-msr.h
  x86/msr: Split out fsgsbase.h
  x86/msr: Split out tsc.h
  x86/msr: Move msr_{split,fold}() into asm/cpu-user-regs.h
  x86: Clean up asm/time.h
  x86: Clean up asm/msr.h
  x86/svm: Rename variable in svm_msr_write_intercept()
  x86/msr: Change rdmsr() to have normal API
  x86/msr: Change wrmsr() to take a single parameter
  x86/msr: Use MSR_IMM when available
  x86/fsgsbase: Split out __{rd,wr}gskern() helpers
  x86/fsgsbase: Update fs/gs helpers to use wrmsrns()
  x86/fsgsbase: Improve code generation in read_registers()

 xen/arch/x86/acpi/cpufreq/acpi.c            |   7 +-
 xen/arch/x86/acpi/cpufreq/cpufreq.c         |   3 +
 xen/arch/x86/acpi/cpufreq/hwp.c             |  18 +-
 xen/arch/x86/acpi/cpufreq/powernow.c        |  12 +-
 xen/arch/x86/apic.c                         |   2 +-
 xen/arch/x86/cpu/amd.c                      |  33 +-
 xen/arch/x86/cpu/common.c                   |  27 +-
 xen/arch/x86/cpu/intel.c                    |  38 +-
 xen/arch/x86/cpu/mcheck/mce.h               |   3 +-
 xen/arch/x86/cpu/mcheck/mce_amd.c           |   2 +-
 xen/arch/x86/cpu/mcheck/mce_intel.c         |   6 +-
 xen/arch/x86/cpu/microcode/intel.c          |   4 +
 xen/arch/x86/cpuid.c                        |   1 +
 xen/arch/x86/debug.c                        |   2 +
 xen/arch/x86/domain.c                       |  16 +-
 xen/arch/x86/domctl.c                       |  45 +-
 xen/arch/x86/genapic/x2apic.c               |   5 +-
 xen/arch/x86/guest/hyperv/hyperv.c          |   1 +
 xen/arch/x86/hvm/hvm.c                      |  77 +--
 xen/arch/x86/hvm/ioreq.c                    |   3 +-
 xen/arch/x86/hvm/svm/svm.c                  |  31 +-
 xen/arch/x86/hvm/svm/vmcb.c                 |   5 +-
 xen/arch/x86/hvm/vmx/vmcs.c                 |  32 +-
 xen/arch/x86/hvm/vmx/vmx.c                  |  64 +--
 xen/arch/x86/hvm/vmx/vvmx.c                 |   8 +-
 xen/arch/x86/include/asm/alternative.h      |   7 +
 xen/arch/x86/include/asm/cpu-user-regs.h    |  11 +
 xen/arch/x86/include/asm/fsgsbase.h         | 112 +++++
 xen/arch/x86/include/asm/guest-msr.h        | 155 ++++++
 xen/arch/x86/include/asm/hvm/hvm.h          |   3 +-
 xen/arch/x86/include/asm/msr.h              | 502 +++++++-------------
 xen/arch/x86/include/asm/prot-key.h         |   6 +-
 xen/arch/x86/include/asm/time.h             |  13 +-
 xen/arch/x86/include/asm/tsc.h              |  46 ++
 xen/arch/x86/machine_kexec.c                |   1 +
 xen/arch/x86/msr.c                          |   9 +-
 xen/arch/x86/nmi.c                          |  18 +-
 xen/arch/x86/oprofile/op_model_athlon.c     |   2 +-
 xen/arch/x86/platform_hypercall.c           |   2 +-
 xen/arch/x86/psr.c                          |   2 +
 xen/arch/x86/pv/domain.c                    |   1 +
 xen/arch/x86/pv/emul-priv-op.c              |  22 +-
 xen/arch/x86/pv/emulate.h                   |   1 +
 xen/arch/x86/pv/misc-hypercalls.c           |   1 +
 xen/arch/x86/spec_ctrl.c                    |   2 +-
 xen/arch/x86/tboot.c                        |  16 +-
 xen/arch/x86/traps.c                        |  16 +-
 xen/arch/x86/tsx.c                          |  29 +-
 xen/arch/x86/x86_64/asm-offsets.c           |   1 +
 xen/arch/x86/x86_64/mmconfig-shared.c       |   2 +-
 xen/arch/x86/xstate.c                       |   5 +-
 xen/common/efi/runtime.c                    |   1 +
 xen/common/ubsan/ubsan.c                    |   2 +
 xen/drivers/acpi/apei/apei-base.c           |  15 +-
 xen/drivers/acpi/tables/tbfadt.c            |   2 +
 xen/drivers/acpi/utilities/utmisc.c         |   3 +
 xen/drivers/passthrough/vtd/iommu.c         |   2 +-
 xen/include/public/arch-x86/cpufeatureset.h |   1 +
 xen/lib/x86/private.h                       |   2 +-
 59 files changed, 846 insertions(+), 612 deletions(-)
 create mode 100644 xen/arch/x86/include/asm/fsgsbase.h
 create mode 100644 xen/arch/x86/include/asm/guest-msr.h
 create mode 100644 xen/arch/x86/include/asm/tsc.h

-- 
2.39.5



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        Fri, 15 Aug 2025 13:41:22 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 03/16] x86: Sort headers
Date: Fri, 15 Aug 2025 21:41:04 +0100
Message-Id: <20250815204117.3312742-4-andrew.cooper3@citrix.com>
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In-Reply-To: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

I'm disappointed to notice that this is the second time I've done this to
arch/x86/domain.c recently, and screwed it up the first time.

I think we need some tooling to help keep this in order, not that I remotely
have time to look into this.
---
 xen/arch/x86/acpi/cpufreq/acpi.c   |  2 +-
 xen/arch/x86/cpu/mcheck/mce.h      |  2 +-
 xen/arch/x86/domain.c              |  4 +-
 xen/arch/x86/domctl.c              | 44 ++++++++---------
 xen/arch/x86/hvm/hvm.c             | 76 +++++++++++++++---------------
 xen/arch/x86/hvm/svm/svm.c         |  6 +--
 xen/arch/x86/hvm/svm/vmcb.c        |  4 +-
 xen/arch/x86/hvm/vmx/vmx.c         | 54 +++++++++++----------
 xen/arch/x86/hvm/vmx/vvmx.c        |  6 +--
 xen/arch/x86/include/asm/hvm/hvm.h |  2 +-
 xen/arch/x86/tboot.c               | 15 +++---
 xen/arch/x86/xstate.c              |  4 +-
 xen/drivers/acpi/apei/apei-base.c  | 14 +++---
 13 files changed, 121 insertions(+), 112 deletions(-)

diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/acpi.c
index 0c2537640608..b81f2afc9b9b 100644
--- a/xen/arch/x86/acpi/cpufreq/acpi.c
+++ b/xen/arch/x86/acpi/cpufreq/acpi.c
@@ -11,8 +11,8 @@
  *      porting acpi-cpufreq.c from Linux 2.6.23 to Xen hypervisor
  */
 
-#include 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h
index eba4b536c797..6157a41aaeea 100644
--- a/xen/arch/x86/cpu/mcheck/mce.h
+++ b/xen/arch/x86/cpu/mcheck/mce.h
@@ -7,8 +7,8 @@
 #include 
 #include 
 
-#include 
 #include 
+#include 
 
 #include "x86_mca.h"
 #include "mctelem.h"
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 28c91cf023f1..6e3fd35c934e 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -24,11 +24,13 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -64,8 +66,6 @@
 #include 
 #include 
 #include 
-#include 
-#include 
 
 #include 
 #include 
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index f07cae6a70b8..d7781b7dc5fd 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -4,39 +4,41 @@
  * Copyright (c) 2002-2006, K A Fraser
  */
 
-#include 
-#include 
-#include 
-#include 
 #include 
-#include 
-#include 
-#include 
+#include 
 #include 
-#include 
 #include 
-#include 
-#include 
-#include 
+#include 
+#include 
+#include 
 #include 
+#include 
+#include 
+#include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
 
+#include 
+#include 
 #include 
-#include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
 #include 
-#include  /* for hvm_acpi_power_button */
-#include  /* for arch_do_domctl */
+#include 
+#include 
+
 #include 
-#include 
-#include 
+
+#include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
 
 static int update_domain_cpu_policy(struct domain *d,
                                     xen_domctl_cpu_policy_t *xdpc)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index cb8ecd050d41..6d2b937b62ba 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -7,64 +7,66 @@
  * Copyright (c) 2008, Citrix Systems, Inc.
  */
 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
+#include 
 #include 
-#include 
 #include 
-#include 
-#include 
-#include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
-#include 
-#include 
-#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
+#include 
+#include 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
 #include 
+#include 
+#include 
 #include 
 #include 
-#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
-#include 
+#include 
+#include 
+#include 
+#include 
 #include 
-#include 
+#include 
+
+#include 
 #include 
-#include 
 #include 
+#include 
+#include 
 #include 
-#include 
 
 #include 
 
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 57520ac3ec2d..a807cab305aa 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -18,7 +18,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -29,13 +28,14 @@
 #include 
 #include 
 #include 
-#include 
 #include 
+#include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
-#include 
 #include 
 #include 
 
diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
index 839d3ff91b5a..e4c797608f25 100644
--- a/xen/arch/x86/hvm/svm/vmcb.c
+++ b/xen/arch/x86/hvm/svm/vmcb.c
@@ -14,11 +14,11 @@
 #include 
 #include 
 
+#include 
+#include 
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
 
 struct vmcb_struct *alloc_vmcb(void)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 6341fa20457c..c6bf435b744a 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -4,51 +4,53 @@
  * Copyright (c) 2004, Intel Corporation.
  */
 
+#include 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
-#include 
+#include 
 #include 
-#include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
+#include 
+
+#include 
+#include 
 #include 
-#include 
+#include 
 #include 
-#include 
-#include 
-#include 
+#include 
+#include 
 #include 
 #include 
+#include 
+#include 
 #include 
-#include 
-#include 
-#include 
-#include 
 #include 
-#include 
+#include 
+#include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
+#include 
+#include 
 #include 
+#include 
 #include 
+#include 
+#include 
+#include 
 #include 
+#include 
 #include 
 #include 
+#include 
+#include 
+
 #include 
+#include 
+#include 
+#include 
 
 static bool __initdata opt_force_ept;
 boolean_param("force-ept", opt_force_ept);
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 2432af58e0e0..95d3c2ee7b79 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -10,12 +10,12 @@
 
 #include 
 
-#include 
-#include 
+#include 
 #include 
 #include 
 #include 
-#include 
+#include 
+#include 
 
 static DEFINE_PER_CPU(u64 *, vvmcs_buf);
 
diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h
index 18e40910ff71..228f47dbde8b 100644
--- a/xen/arch/x86/include/asm/hvm/hvm.h
+++ b/xen/arch/x86/include/asm/hvm/hvm.h
@@ -14,8 +14,8 @@
 
 #include 
 #include 
-#include 
 #include 
+#include 
 
 struct pirq; /* needed by pi_update_irte */
 
diff --git a/xen/arch/x86/tboot.c b/xen/arch/x86/tboot.c
index d5db60d335e3..319116857d4a 100644
--- a/xen/arch/x86/tboot.c
+++ b/xen/arch/x86/tboot.c
@@ -1,19 +1,20 @@
+#include 
+#include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
 #include 
+#include 
+#include 
+
+#include 
 #include 
 #include 
 #include 
-#include 
-#include 
 #include 
+#include 
 #include 
 
 #include 
diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c
index e8e218caed36..f6d677eb121d 100644
--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -10,12 +10,12 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
-#include 
 #include 
+#include 
 #include 
-#include 
 
 /*
  * Maximum size (in byte) of the XSAVE/XRSTOR save area required by all
diff --git a/xen/drivers/acpi/apei/apei-base.c b/xen/drivers/acpi/apei/apei-base.c
index 053a92c307bb..4fe99573a220 100644
--- a/xen/drivers/acpi/apei/apei-base.c
+++ b/xen/drivers/acpi/apei/apei-base.c
@@ -30,15 +30,17 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; If not, see .
  */
-#include 
-#include 
+
+#include 
 #include 
-#include 
-#include 
-#include 
+#include 
 #include 
-#include 
+#include 
+#include 
+#include 
+
 #include 
+
 #include 
 #include 
 
-- 
2.39.5



From xen-devel-bounces@lists.xenproject.org Fri Aug 15 20:41:27 2025
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        Fri, 15 Aug 2025 13:41:23 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 04/16] x86/msr: Split out guest-msr.h
Date: Fri, 15 Aug 2025 21:41:05 +0100
Message-Id: <20250815204117.3312742-5-andrew.cooper3@citrix.com>
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struct vcpu_msrs has a very different purpose to everything else in msr.h

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/cpu/common.c            |   1 +
 xen/arch/x86/cpuid.c                 |   1 +
 xen/arch/x86/debug.c                 |   1 +
 xen/arch/x86/domain.c                |   1 +
 xen/arch/x86/domctl.c                |   1 +
 xen/arch/x86/hvm/hvm.c               |   1 +
 xen/arch/x86/hvm/svm/svm.c           |   1 +
 xen/arch/x86/hvm/svm/vmcb.c          |   1 +
 xen/arch/x86/hvm/vmx/vmx.c           |   1 +
 xen/arch/x86/hvm/vmx/vvmx.c          |   1 +
 xen/arch/x86/include/asm/guest-msr.h | 155 +++++++++++++++++++++++++++
 xen/arch/x86/include/asm/msr.h       | 145 -------------------------
 xen/arch/x86/msr.c                   |   1 +
 xen/arch/x86/pv/emulate.h            |   1 +
 xen/arch/x86/x86_64/asm-offsets.c    |   1 +
 15 files changed, 168 insertions(+), 145 deletions(-)
 create mode 100644 xen/arch/x86/include/asm/guest-msr.h

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 60f3c9a29e67..530b9eb39abc 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 8dc68945f7ae..b63a82dd3815 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -7,6 +7,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/xen/arch/x86/debug.c b/xen/arch/x86/debug.c
index 71755dea6ff2..11b0a7e5475a 100644
--- a/xen/arch/x86/debug.c
+++ b/xen/arch/x86/debug.c
@@ -9,6 +9,7 @@
 
 #include 
 #include 
+#include 
 
 /*
  * Merge new bits into dr6.  'new' is always given in positive polarity,
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 6e3fd35c934e..1bbe53e36b59 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -44,6 +44,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index d7781b7dc5fd..6153e3c07e2d 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 6d2b937b62ba..bd64faf2071c 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -38,6 +38,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index a807cab305aa..4fc6206edac0 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
index e4c797608f25..334950709f69 100644
--- a/xen/arch/x86/hvm/svm/vmcb.c
+++ b/xen/arch/x86/hvm/svm/vmcb.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index c6bf435b744a..4664a014bc8a 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 95d3c2ee7b79..6201665d9f4c 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -10,6 +10,7 @@
 
 #include 
 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/include/asm/guest-msr.h b/xen/arch/x86/include/asm/guest-msr.h
new file mode 100644
index 000000000000..5f0cb0a93995
--- /dev/null
+++ b/xen/arch/x86/include/asm/guest-msr.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef X86_GUEST_MSR_H
+#define X86_GUEST_MSR_H
+
+#include 
+
+/* Container object for per-vCPU MSRs */
+struct vcpu_msrs
+{
+    /*
+     * 0x00000048 - MSR_SPEC_CTRL
+     * 0xc001011f - MSR_VIRT_SPEC_CTRL (if X86_FEATURE_AMD_SSBD)
+     *
+     * For PV guests, this holds the guest kernel value.  It is accessed on
+     * every entry/exit path.
+     *
+     * For VT-x guests, one of two situations exist:
+     *
+     * - If hardware supports virtualized MSR_SPEC_CTRL, it is active by
+     *   default and the guest value lives in the VMCS.
+     * - Otherwise, the guest value is held in the MSR load/save list.
+     *
+     * For SVM, the guest value lives in the VMCB, and hardware saves/restores
+     * the host value automatically.  However, guests run with the OR of the
+     * host and guest value, which allows Xen to set protections behind the
+     * guest's back.
+     *
+     * We must clear/restore Xen's value before/after VMRUN to avoid unduly
+     * influencing the guest.  In order to support "behind the guest's back"
+     * protections, we load this value (commonly 0) before VMRUN.
+     *
+     * Once of such "behind the guest's back" usages is setting SPEC_CTRL.SSBD
+     * if the guest sets VIRT_SPEC_CTRL.SSBD.
+     */
+    struct {
+        uint32_t raw;
+    } spec_ctrl;
+
+    /*
+     * 0x00000140 - MSR_INTEL_MISC_FEATURES_ENABLES
+     *
+     * This MSR is non-architectural, but for simplicy we allow it to be read
+     * unconditionally.  The CPUID Faulting bit is the only writeable bit, and
+     * only if enumerated by MSR_PLATFORM_INFO.
+     */
+    union {
+        uint32_t raw;
+        struct {
+            bool cpuid_faulting:1;
+        };
+    } misc_features_enables;
+
+    /*
+     * 0x00000560 ... 57x - MSR_RTIT_*
+     *
+     * "Real Time Instruction Trace", now called Processor Trace.
+     *
+     * These MSRs are not exposed to guests.  They are controlled by Xen
+     * behind the scenes, when vmtrace is enabled for the domain.
+     *
+     * MSR_RTIT_OUTPUT_BASE not stored here.  It is fixed per vcpu, and
+     * derived from v->vmtrace.buf.
+     */
+    struct {
+        /*
+         * Placed in the MSR load/save lists.  Only modified by hypercall in
+         * the common case.
+         */
+        uint64_t ctl;
+
+        /*
+         * Updated by hardware in non-root mode.  Synchronised here on vcpu
+         * context switch.
+         */
+        uint64_t status;
+        union {
+            uint64_t output_mask;
+            struct {
+                uint32_t output_limit;
+                uint32_t output_offset;
+            };
+        };
+    } rtit;
+
+    /*
+     * 0x000006e1 - MSR_PKRS - Protection Key Supervisor.
+     *
+     * Exposed R/W to guests.  Xen doesn't use PKS yet, so only context
+     * switched per vcpu.  When in current context, live value is in hardware,
+     * and this value is stale.
+     */
+    uint32_t pkrs;
+
+    /* 0x00000da0 - MSR_IA32_XSS */
+    struct {
+        uint64_t raw;
+    } xss;
+
+    /*
+     * 0xc0000103 - MSR_TSC_AUX
+     *
+     * Value is guest chosen, and always loaded in vcpu context.  Guests have
+     * no direct MSR access, and the value is accessible to userspace with the
+     * RDTSCP and RDPID instructions.
+     */
+    uint32_t tsc_aux;
+
+    /*
+     * 0xc001011f - MSR_VIRT_SPEC_CTRL (if !X86_FEATURE_AMD_SSBD)
+     *
+     * AMD only, used on Zen1 and older hardware (pre-AMD_SSBD).  Holds the
+     * the guests value.
+     *
+     * In the default case, Xen doesn't protect itself from SSB, and guests
+     * are expected to use VIRT_SPEC_CTRL.SSBD=1 sparingly.  Xen therefore
+     * runs in the guest kernel's choice of SSBD.
+     *
+     * However, if the global enable `spec-ctrl=ssbd` is selected, hardware is
+     * always configured with SSBD=1 and the guest's setting is never loaded
+     * into hardware.
+     */
+    struct {
+        uint32_t raw;
+    } virt_spec_ctrl;
+
+    /*
+     * 0xc00110{27,19-1b} MSR_AMD64_DR{0-3}_ADDRESS_MASK
+     *
+     * Loaded into hardware for guests which have active %dr7 settings.
+     * Furthermore, HVM guests are offered direct access, meaning that the
+     * values here may be stale in current context.
+     */
+    uint32_t dr_mask[4];
+};
+
+struct vcpu;
+struct cpu_policy;
+
+int init_vcpu_msr_policy(struct vcpu *v);
+
+/*
+ * Below functions can return X86EMUL_UNHANDLEABLE which means that MSR is
+ * not (yet) handled by it and must be processed by legacy handlers. Such
+ * behaviour is needed for transition period until all rd/wrmsr are handled
+ * by the new MSR infrastructure.
+ *
+ * These functions are also used by the migration logic, so need to cope with
+ * being used outside of v's context.
+ */
+int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val);
+int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val);
+
+uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp);
+
+#endif /* X86_GUEST_MSR_H */
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 6a97b41bae07..787517802d9d 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -299,149 +299,4 @@ static inline void wrmsr_tsc_aux(uint32_t val)
     }
 }
 
-uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp);
-
-/* Container object for per-vCPU MSRs */
-struct vcpu_msrs
-{
-    /*
-     * 0x00000048 - MSR_SPEC_CTRL
-     * 0xc001011f - MSR_VIRT_SPEC_CTRL (if X86_FEATURE_AMD_SSBD)
-     *
-     * For PV guests, this holds the guest kernel value.  It is accessed on
-     * every entry/exit path.
-     *
-     * For VT-x guests, one of two situations exist:
-     *
-     * - If hardware supports virtualized MSR_SPEC_CTRL, it is active by
-     *   default and the guest value lives in the VMCS.
-     * - Otherwise, the guest value is held in the MSR load/save list.
-     *
-     * For SVM, the guest value lives in the VMCB, and hardware saves/restores
-     * the host value automatically.  However, guests run with the OR of the
-     * host and guest value, which allows Xen to set protections behind the
-     * guest's back.
-     *
-     * We must clear/restore Xen's value before/after VMRUN to avoid unduly
-     * influencing the guest.  In order to support "behind the guest's back"
-     * protections, we load this value (commonly 0) before VMRUN.
-     *
-     * Once of such "behind the guest's back" usages is setting SPEC_CTRL.SSBD
-     * if the guest sets VIRT_SPEC_CTRL.SSBD.
-     */
-    struct {
-        uint32_t raw;
-    } spec_ctrl;
-
-    /*
-     * 0x00000140 - MSR_INTEL_MISC_FEATURES_ENABLES
-     *
-     * This MSR is non-architectural, but for simplicy we allow it to be read
-     * unconditionally.  The CPUID Faulting bit is the only writeable bit, and
-     * only if enumerated by MSR_PLATFORM_INFO.
-     */
-    union {
-        uint32_t raw;
-        struct {
-            bool cpuid_faulting:1;
-        };
-    } misc_features_enables;
-
-    /*
-     * 0x00000560 ... 57x - MSR_RTIT_*
-     *
-     * "Real Time Instruction Trace", now called Processor Trace.
-     *
-     * These MSRs are not exposed to guests.  They are controlled by Xen
-     * behind the scenes, when vmtrace is enabled for the domain.
-     *
-     * MSR_RTIT_OUTPUT_BASE not stored here.  It is fixed per vcpu, and
-     * derived from v->vmtrace.buf.
-     */
-    struct {
-        /*
-         * Placed in the MSR load/save lists.  Only modified by hypercall in
-         * the common case.
-         */
-        uint64_t ctl;
-
-        /*
-         * Updated by hardware in non-root mode.  Synchronised here on vcpu
-         * context switch.
-         */
-        uint64_t status;
-        union {
-            uint64_t output_mask;
-            struct {
-                uint32_t output_limit;
-                uint32_t output_offset;
-            };
-        };
-    } rtit;
-
-    /*
-     * 0x000006e1 - MSR_PKRS - Protection Key Supervisor.
-     *
-     * Exposed R/W to guests.  Xen doesn't use PKS yet, so only context
-     * switched per vcpu.  When in current context, live value is in hardware,
-     * and this value is stale.
-     */
-    uint32_t pkrs;
-
-    /* 0x00000da0 - MSR_IA32_XSS */
-    struct {
-        uint64_t raw;
-    } xss;
-
-    /*
-     * 0xc0000103 - MSR_TSC_AUX
-     *
-     * Value is guest chosen, and always loaded in vcpu context.  Guests have
-     * no direct MSR access, and the value is accessible to userspace with the
-     * RDTSCP and RDPID instructions.
-     */
-    uint32_t tsc_aux;
-
-    /*
-     * 0xc001011f - MSR_VIRT_SPEC_CTRL (if !X86_FEATURE_AMD_SSBD)
-     *
-     * AMD only, used on Zen1 and older hardware (pre-AMD_SSBD).  Holds the
-     * the guests value.
-     *
-     * In the default case, Xen doesn't protect itself from SSB, and guests
-     * are expected to use VIRT_SPEC_CTRL.SSBD=1 sparingly.  Xen therefore
-     * runs in the guest kernel's choice of SSBD.
-     *
-     * However, if the global enable `spec-ctrl=ssbd` is selected, hardware is
-     * always configured with SSBD=1 and the guest's setting is never loaded
-     * into hardware.
-     */
-    struct {
-        uint32_t raw;
-    } virt_spec_ctrl;
-
-    /*
-     * 0xc00110{27,19-1b} MSR_AMD64_DR{0-3}_ADDRESS_MASK
-     *
-     * Loaded into hardware for guests which have active %dr7 settings.
-     * Furthermore, HVM guests are offered direct access, meaning that the
-     * values here may be stale in current context.
-     */
-    uint32_t dr_mask[4];
-};
-
-int init_vcpu_msr_policy(struct vcpu *v);
-
-/*
- * Below functions can return X86EMUL_UNHANDLEABLE which means that MSR is
- * not (yet) handled by it and must be processed by legacy handlers. Such
- * behaviour is needed for transition period until all rd/wrmsr are handled
- * by the new MSR infrastructure.
- *
- * These functions are also used by the migration logic, so need to cope with
- * being used outside of v's context.
- */
-int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val);
-int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val);
-
 #endif /* __ASM_MSR_H */
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index b301143ed2d4..ad75a2e10855 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/pv/emulate.h b/xen/arch/x86/pv/emulate.h
index 49a4d34832df..c74e45e50c08 100644
--- a/xen/arch/x86/pv/emulate.h
+++ b/xen/arch/x86/pv/emulate.h
@@ -3,6 +3,7 @@
 
 #include 
 
+#include 
 #include 
 #include 
 
diff --git a/xen/arch/x86/x86_64/asm-offsets.c b/xen/arch/x86/x86_64/asm-offsets.c
index 2258b4ce1b95..9d4536402661 100644
--- a/xen/arch/x86/x86_64/asm-offsets.c
+++ b/xen/arch/x86/x86_64/asm-offsets.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifdef CONFIG_VIDEO
 # include "../boot/video.h"
-- 
2.39.5



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        Fri, 15 Aug 2025 13:41:21 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 01/16] x86/msr: Implement rdmsr_safe() in C
Date: Fri, 15 Aug 2025 21:41:02 +0100
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... in preparation to be able to use asm goto.

Notably this mean that the value parameter must be taken by pointer rather
than by value.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/acpi/cpufreq/hwp.c       | 14 +++++------
 xen/arch/x86/apic.c                   |  2 +-
 xen/arch/x86/cpu/amd.c                | 25 +++++++++----------
 xen/arch/x86/cpu/common.c             |  6 ++---
 xen/arch/x86/cpu/intel.c              |  8 +++---
 xen/arch/x86/cpu/mcheck/mce_amd.c     |  2 +-
 xen/arch/x86/cpu/mcheck/mce_intel.c   |  6 ++---
 xen/arch/x86/hvm/ioreq.c              |  2 +-
 xen/arch/x86/hvm/svm/svm.c            | 16 ++++++------
 xen/arch/x86/hvm/vmx/vmx.c            |  4 +--
 xen/arch/x86/include/asm/msr.h        | 35 ++++++++++++++++-----------
 xen/arch/x86/msr.c                    |  8 +++---
 xen/arch/x86/platform_hypercall.c     |  2 +-
 xen/arch/x86/pv/emul-priv-op.c        | 18 +++++++-------
 xen/arch/x86/spec_ctrl.c              |  2 +-
 xen/arch/x86/x86_64/mmconfig-shared.c |  2 +-
 xen/drivers/passthrough/vtd/iommu.c   |  2 +-
 17 files changed, 80 insertions(+), 74 deletions(-)

diff --git a/xen/arch/x86/acpi/cpufreq/hwp.c b/xen/arch/x86/acpi/cpufreq/hwp.c
index f22b4674dfe9..26dce9aaf89a 100644
--- a/xen/arch/x86/acpi/cpufreq/hwp.c
+++ b/xen/arch/x86/acpi/cpufreq/hwp.c
@@ -245,7 +245,7 @@ static void cf_check hwp_write_request(void *info)
     {
         hwp_verbose("CPU%u: error wrmsr_safe(MSR_HWP_REQUEST, %lx)\n",
                     policy->cpu, hwp_req.raw);
-        rdmsr_safe(MSR_HWP_REQUEST, data->curr_req.raw);
+        rdmsr_safe(MSR_HWP_REQUEST, &data->curr_req.raw);
         data->ret = -EINVAL;
     }
 }
@@ -281,7 +281,7 @@ static bool hdc_set_pkg_hdc_ctl(unsigned int cpu, bool val)
 {
     uint64_t msr;
 
-    if ( rdmsr_safe(MSR_PKG_HDC_CTL, msr) )
+    if ( rdmsr_safe(MSR_PKG_HDC_CTL, &msr) )
     {
         hwp_err(cpu, "rdmsr_safe(MSR_PKG_HDC_CTL)\n");
         return false;
@@ -305,7 +305,7 @@ static bool hdc_set_pm_ctl1(unsigned int cpu, bool val)
 {
     uint64_t msr;
 
-    if ( rdmsr_safe(MSR_PM_CTL1, msr) )
+    if ( rdmsr_safe(MSR_PM_CTL1, &msr) )
     {
         hwp_err(cpu, "rdmsr_safe(MSR_PM_CTL1)\n");
         return false;
@@ -353,7 +353,7 @@ static void cf_check hwp_init_msrs(void *info)
      * Package level MSR, but we don't have a good idea of packages here, so
      * just do it everytime.
      */
-    if ( rdmsr_safe(MSR_PM_ENABLE, val) )
+    if ( rdmsr_safe(MSR_PM_ENABLE, &val) )
     {
         hwp_err(policy->cpu, "rdmsr_safe(MSR_PM_ENABLE)\n");
         data->curr_req.raw = -1;
@@ -375,13 +375,13 @@ static void cf_check hwp_init_msrs(void *info)
         }
     }
 
-    if ( rdmsr_safe(MSR_HWP_CAPABILITIES, data->hwp_caps) )
+    if ( rdmsr_safe(MSR_HWP_CAPABILITIES, &data->hwp_caps) )
     {
         hwp_err(policy->cpu, "rdmsr_safe(MSR_HWP_CAPABILITIES)\n");
         goto error;
     }
 
-    if ( rdmsr_safe(MSR_HWP_REQUEST, data->curr_req.raw) )
+    if ( rdmsr_safe(MSR_HWP_REQUEST, &data->curr_req.raw) )
     {
         hwp_err(policy->cpu, "rdmsr_safe(MSR_HWP_REQUEST)\n");
         goto error;
@@ -481,7 +481,7 @@ static void cf_check hwp_set_misc_turbo(void *info)
 
     data->ret = 0;
 
-    if ( rdmsr_safe(MSR_IA32_MISC_ENABLE, msr) )
+    if ( rdmsr_safe(MSR_IA32_MISC_ENABLE, &msr) )
     {
         hwp_verbose("CPU%u: error rdmsr_safe(MSR_IA32_MISC_ENABLE)\n",
                     policy->cpu);
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 0fd8bdba7067..cac5ba39e615 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -764,7 +764,7 @@ static int __init detect_init_APIC (void)
     if (enable_local_apic < 0)
         return -1;
 
-    if ( rdmsr_safe(MSR_APIC_BASE, msr_content) )
+    if ( rdmsr_safe(MSR_APIC_BASE, &msr_content) )
     {
         printk("No local APIC present\n");
         return -1;
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index eb428f284ecb..567b992a9fe2 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -496,7 +496,7 @@ static void cf_check disable_c1e(void *unused)
 	 * The MSR does not exist in all FamilyF CPUs (only Rev F and above),
 	 * but we safely catch the #GP in that case.
 	 */
-	if ((rdmsr_safe(MSR_K8_ENABLE_C1E, msr_content) == 0) &&
+	if ((rdmsr_safe(MSR_K8_ENABLE_C1E, &msr_content) == 0) &&
 	    (msr_content & (3ULL << 27)) &&
 	    (wrmsr_safe(MSR_K8_ENABLE_C1E, msr_content & ~(3ULL << 27)) != 0))
 		printk(KERN_ERR "Failed to disable C1E on CPU#%u (%16"PRIx64")\n",
@@ -695,21 +695,21 @@ static void amd_process_freq(const struct cpuinfo_x86 *c,
 
 	lo = 0; /* gcc may not recognize the loop having at least 5 iterations */
 	for (h = c->x86 == 0x10 ? 5 : 8; h--; )
-		if (!rdmsr_safe(0xC0010064 + h, lo) && (lo >> 63))
+		if (!rdmsr_safe(0xC0010064 + h, &lo) && (lo >> 63))
 			break;
 	if (!(lo >> 63))
 		return;
 
 	if (idx && idx < h &&
-	    !rdmsr_safe(0xC0010064 + idx, val) && (val >> 63) &&
-	    !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) {
+	    !rdmsr_safe(0xC0010064 + idx, &val) && (val >> 63) &&
+	    !rdmsr_safe(0xC0010064, &hi) && (hi >> 63)) {
 		if (nom_mhz)
 			*nom_mhz = amd_parse_freq(c->x86, val);
 		if (low_mhz)
 			*low_mhz = amd_parse_freq(c->x86, lo);
 		if (hi_mhz)
 			*hi_mhz = amd_parse_freq(c->x86, hi);
-	} else if (h && !rdmsr_safe(0xC0010064, hi) && (hi >> 63)) {
+	} else if (h && !rdmsr_safe(0xC0010064, &hi) && (hi >> 63)) {
 		if (low_mhz)
 			*low_mhz = amd_parse_freq(c->x86, lo);
 		if (hi_mhz)
@@ -765,7 +765,7 @@ void amd_init_lfence(struct cpuinfo_x86 *c)
 	 * rather than per-thread, so do a full safe read/write/readback cycle
 	 * in the worst case.
 	 */
-	if (rdmsr_safe(MSR_AMD64_DE_CFG, value))
+	if (rdmsr_safe(MSR_AMD64_DE_CFG, &value))
 		/* Unable to read.  Assume the safer default. */
 		__clear_bit(X86_FEATURE_LFENCE_DISPATCH,
 			    c->x86_capability);
@@ -775,7 +775,7 @@ void amd_init_lfence(struct cpuinfo_x86 *c)
 			  c->x86_capability);
 	else if (wrmsr_safe(MSR_AMD64_DE_CFG,
 			    value | AMD64_DE_CFG_LFENCE_SERIALISE) ||
-		 rdmsr_safe(MSR_AMD64_DE_CFG, value) ||
+		 rdmsr_safe(MSR_AMD64_DE_CFG, &value) ||
 		 !(value & AMD64_DE_CFG_LFENCE_SERIALISE))
 		/* Attempt to set failed.  Assume the safer default. */
 		__clear_bit(X86_FEATURE_LFENCE_DISPATCH,
@@ -804,7 +804,7 @@ static bool set_legacy_ssbd(const struct cpuinfo_x86 *c, bool enable)
 	if (bit >= 0) {
 		uint64_t val, mask = 1ull << bit;
 
-		if (rdmsr_safe(MSR_AMD64_LS_CFG, val) ||
+		if (rdmsr_safe(MSR_AMD64_LS_CFG, &val) ||
 		    ({
 			    val &= ~mask;
 			    if (enable)
@@ -962,7 +962,7 @@ void amd_init_spectral_chicken(void)
 	if (cpu_has_hypervisor || !is_zen2_uarch())
 		return;
 
-	if (rdmsr_safe(MSR_AMD64_DE_CFG2, val) == 0 && !(val & chickenbit))
+	if (rdmsr_safe(MSR_AMD64_DE_CFG2, &val) == 0 && !(val & chickenbit))
 		wrmsr_safe(MSR_AMD64_DE_CFG2, val | chickenbit);
 }
 
@@ -1116,8 +1116,7 @@ static void amd_check_bp_cfg(void)
 static void cf_check init_amd(struct cpuinfo_x86 *c)
 {
 	u32 l, h;
-
-	unsigned long long value;
+	uint64_t value;
 
 	/* Disable TLB flush filter by setting HWCR.FFDIS on K8
 	 * bit 6 of msr C001_0015
@@ -1251,7 +1250,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	if ((c->x86 == 0x15) &&
 	    (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
 	    !cpu_has(c, X86_FEATURE_TOPOEXT) &&
-	    !rdmsr_safe(MSR_K8_EXT_FEATURE_MASK, value)) {
+	    !rdmsr_safe(MSR_K8_EXT_FEATURE_MASK, &value)) {
 		value |= 1ULL << 54;
 		wrmsr_safe(MSR_K8_EXT_FEATURE_MASK, value);
 		rdmsrl(MSR_K8_EXT_FEATURE_MASK, value);
@@ -1267,7 +1266,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	 * Disable it on the affected CPUs.
 	 */
 	if (c->x86 == 0x15 && c->x86_model >= 0x02 && c->x86_model < 0x20 &&
-	    !rdmsr_safe(MSR_AMD64_IC_CFG, value) && (value & 0x1e) != 0x1e)
+	    !rdmsr_safe(MSR_AMD64_IC_CFG, &value) && (value & 0x1e) != 0x1e)
 		wrmsr_safe(MSR_AMD64_IC_CFG, value | 0x1e);
 
         amd_get_topology(c);
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index da05015578aa..60f3c9a29e67 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -130,14 +130,14 @@ bool __init probe_cpuid_faulting(void)
 	uint64_t val;
 	int rc;
 
-	if ((rc = rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val)) == 0)
+	if ((rc = rdmsr_safe(MSR_INTEL_PLATFORM_INFO, &val)) == 0)
 		raw_cpu_policy.platform_info.cpuid_faulting =
 			val & MSR_PLATFORM_INFO_CPUID_FAULTING;
 
 	if (rc ||
 	    !(val & MSR_PLATFORM_INFO_CPUID_FAULTING) ||
 	    rdmsr_safe(MSR_INTEL_MISC_FEATURES_ENABLES,
-		       this_cpu(msr_misc_features)))
+		       &this_cpu(msr_misc_features)))
 	{
 		setup_clear_cpu_cap(X86_FEATURE_CPUID_FAULTING);
 		return false;
@@ -851,7 +851,7 @@ static void skinit_enable_intr(void)
 	 * If the platform is performing a Secure Launch via SKINIT
 	 * INIT_REDIRECTION flag will be active.
 	 */
-	if ( !cpu_has_skinit || rdmsr_safe(MSR_K8_VM_CR, val) ||
+	if ( !cpu_has_skinit || rdmsr_safe(MSR_K8_VM_CR, &val) ||
 	     !(val & VM_CR_INIT_REDIRECTION) )
 		return;
 
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 29144ffe37a5..ecca11f04db8 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -115,7 +115,7 @@ static uint64_t __init _probe_mask_msr(unsigned int *msr, uint64_t caps)
 
 	expected_levelling_cap |= caps;
 
-	if (rdmsr_safe(*msr, val) || wrmsr_safe(*msr, val))
+	if (rdmsr_safe(*msr, &val) || wrmsr_safe(*msr, val))
 		*msr = 0;
 	else
 		levelling_caps |= caps;
@@ -546,7 +546,7 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
             { 26667, 13333, 20000, 16667, 33333, 10000, 40000 };
 
     case 6:
-        if ( rdmsr_safe(MSR_INTEL_PLATFORM_INFO, msrval) )
+        if ( rdmsr_safe(MSR_INTEL_PLATFORM_INFO, &msrval) )
             return;
         max_ratio = msrval >> 8;
         min_ratio = msrval >> 40;
@@ -566,7 +566,7 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
              */
             if ( min_ratio > max_ratio )
                 SWAP(min_ratio, max_ratio);
-            if ( rdmsr_safe(MSR_FSB_FREQ, msrval) ||
+            if ( rdmsr_safe(MSR_FSB_FREQ, &msrval) ||
                  (msrval &= 7) >= ARRAY_SIZE(core_factors) )
                 return;
             factor = core_factors[msrval];
@@ -584,7 +584,7 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
         break;
 
     case 0xf:
-        if ( rdmsr_safe(MSR_IA32_EBC_FREQUENCY_ID, msrval) )
+        if ( rdmsr_safe(MSR_IA32_EBC_FREQUENCY_ID, &msrval) )
             return;
         max_ratio = msrval >> 24;
         min_ratio = 0;
diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mce_amd.c
index 4f06a3153b91..25c29eb3d255 100644
--- a/xen/arch/x86/cpu/mcheck/mce_amd.c
+++ b/xen/arch/x86/cpu/mcheck/mce_amd.c
@@ -195,7 +195,7 @@ static void mcequirk_amd_apply(enum mcequirk_amd_flags flags)
         break;
 
     case MCEQUIRK_F10_GART:
-        if ( rdmsr_safe(MSR_AMD64_MCx_MASK(4), val) == 0 )
+        if ( rdmsr_safe(MSR_AMD64_MCx_MASK(4), &val) == 0 )
             wrmsr_safe(MSR_AMD64_MCx_MASK(4), val | (1 << 10));
         break;
 
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 1e52b1ac25a4..c4655de401c6 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -726,7 +726,7 @@ static bool intel_enable_lmce(void)
      * MSR_IA32_MCG_EXT_CTL.LMCE_EN.
      */
 
-    if ( rdmsr_safe(MSR_IA32_FEATURE_CONTROL, msr_content) )
+    if ( rdmsr_safe(MSR_IA32_FEATURE_CONTROL, &msr_content) )
         return false;
 
     if ( (msr_content & IA32_FEATURE_CONTROL_LOCK) &&
@@ -879,14 +879,14 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
     case 0x8f: /* Sapphire Rapids X */
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||
-             rdmsr_safe(MSR_PPIN_CTL, val) )
+             rdmsr_safe(MSR_PPIN_CTL, &val) )
             return;
 
         /* If PPIN is disabled, but not locked, try to enable. */
         if ( !(val & (PPIN_ENABLE | PPIN_LOCKOUT)) )
         {
             wrmsr_safe(MSR_PPIN_CTL, val | PPIN_ENABLE);
-            rdmsr_safe(MSR_PPIN_CTL, val);
+            rdmsr_safe(MSR_PPIN_CTL, &val);
         }
 
         if ( !(val & PPIN_ENABLE) )
diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c
index ec709e5f4741..98b0dd7972c2 100644
--- a/xen/arch/x86/hvm/ioreq.c
+++ b/xen/arch/x86/hvm/ioreq.c
@@ -292,7 +292,7 @@ bool arch_ioreq_server_get_type_addr(const struct domain *d,
         {
             uint64_t msr_val;
 
-            if ( !rdmsr_safe(MSR_AMD64_NB_CFG, msr_val) &&
+            if ( !rdmsr_safe(MSR_AMD64_NB_CFG, &msr_val) &&
                  (msr_val & (1ULL << AMD64_NB_CFG_CF8_EXT_ENABLE_BIT)) )
                 *addr |= CF8_ADDR_HI(cf8);
         }
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index fce750ca1f7a..57520ac3ec2d 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1082,8 +1082,8 @@ static void svm_host_osvw_init(void)
     {
         uint64_t len, status;
 
-        if ( rdmsr_safe(MSR_AMD_OSVW_ID_LENGTH, len) ||
-             rdmsr_safe(MSR_AMD_OSVW_STATUS, status) )
+        if ( rdmsr_safe(MSR_AMD_OSVW_ID_LENGTH, &len) ||
+             rdmsr_safe(MSR_AMD_OSVW_STATUS, &status) )
             len = status = 0;
 
         if ( len < osvw_length )
@@ -1481,7 +1481,7 @@ static void svm_init_erratum_383(const struct cpuinfo_x86 *c)
         return;
 
     /* use safe methods to be compatible with nested virtualization */
-    if ( rdmsr_safe(MSR_AMD64_DC_CFG, msr_content) == 0 &&
+    if ( rdmsr_safe(MSR_AMD64_DC_CFG, &msr_content) == 0 &&
          wrmsr_safe(MSR_AMD64_DC_CFG, msr_content | (1ULL << 47)) == 0 )
         amd_erratum383_found = 1;
     else
@@ -1785,7 +1785,7 @@ static int cf_check svm_msr_read_intercept(
         break;
 
     case MSR_F10_BU_CFG:
-        if ( !rdmsr_safe(msr, *msr_content) )
+        if ( !rdmsr_safe(msr, msr_content) )
             break;
 
         if ( boot_cpu_data.x86 == 0xf )
@@ -1804,7 +1804,7 @@ static int cf_check svm_msr_read_intercept(
         goto gpf;
 
     case MSR_F10_BU_CFG2:
-        if ( rdmsr_safe(msr, *msr_content) )
+        if ( rdmsr_safe(msr, msr_content) )
             goto gpf;
         break;
 
@@ -1881,7 +1881,7 @@ static int cf_check svm_msr_read_intercept(
         break;
 
     default:
-        if ( d->arch.msr_relaxed && !rdmsr_safe(msr, tmp) )
+        if ( d->arch.msr_relaxed && !rdmsr_safe(msr, &tmp) )
         {
             *msr_content = 0;
             break;
@@ -2047,7 +2047,7 @@ static int cf_check svm_msr_write_intercept(
 
     case MSR_F10_BU_CFG:
     case MSR_F10_BU_CFG2:
-        if ( rdmsr_safe(msr, msr_content) )
+        if ( rdmsr_safe(msr, &msr_content) )
             goto gpf;
         break;
 
@@ -2068,7 +2068,7 @@ static int cf_check svm_msr_write_intercept(
         break;
 
     default:
-        if ( d->arch.msr_relaxed && !rdmsr_safe(msr, msr_content) )
+        if ( d->arch.msr_relaxed && !rdmsr_safe(msr, &msr_content) )
             break;
 
         gdprintk(XENLOG_WARNING,
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index cb82d52ef035..6341fa20457c 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -3499,7 +3499,7 @@ static int cf_check vmx_msr_read_intercept(
             break;
         }
 
-        if ( curr->domain->arch.msr_relaxed && !rdmsr_safe(msr, tmp) )
+        if ( curr->domain->arch.msr_relaxed && !rdmsr_safe(msr, &tmp) )
         {
             *msr_content = 0;
             break;
@@ -3809,7 +3809,7 @@ static int cf_check vmx_msr_write_intercept(
              is_last_branch_msr(msr) )
             break;
 
-        if ( v->domain->arch.msr_relaxed && !rdmsr_safe(msr, msr_content) )
+        if ( v->domain->arch.msr_relaxed && !rdmsr_safe(msr, &msr_content) )
             break;
 
         gdprintk(XENLOG_WARNING,
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index e185db096756..d2c86ddb09e9 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -53,20 +53,27 @@ static inline void wrmsrns(uint32_t msr, uint64_t val)
 }
 
 /* rdmsr with exception handling */
-#define rdmsr_safe(msr,val) ({\
-    int rc_; \
-    uint64_t lo_, hi_; \
-    __asm__ __volatile__( \
-        "1: rdmsr\n2:\n" \
-        ".section .fixup,\"ax\"\n" \
-        "3: xorl %k0,%k0\n; xorl %k1,%k1\n" \
-        "   movl %5,%2\n; jmp 2b\n" \
-        ".previous\n" \
-        _ASM_EXTABLE(1b, 3b) \
-        : "=a" (lo_), "=d" (hi_), "=&r" (rc_) \
-        : "c" (msr), "2" (0), "i" (-EFAULT)); \
-    val = lo_ | (hi_ << 32); \
-    rc_; })
+static inline int rdmsr_safe(unsigned int msr, uint64_t *val)
+{
+    int rc;
+    uint64_t lo, hi;
+
+    asm_inline volatile (
+        "1: rdmsr\n2:\n"
+        ".section .fixup,\"ax\"\n"
+        "3: xorl %k0,%k0\n\t"
+        "   xorl %k1,%k1\n\t"
+        "   movl %5,%2\n\t"
+        "   jmp 2b\n\t"
+        ".previous"
+        _ASM_EXTABLE(1b, 3b)
+        : "=a" (lo), "=d" (hi), "=&r" (rc)
+        : "c" (msr), "2" (0), "i" (-EFAULT) );
+
+    *val = lo | (hi << 32);
+
+    return rc;
+}
 
 /* wrmsr with exception handling */
 static inline int wrmsr_safe(unsigned int msr, uint64_t val)
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 1bf117cbd80f..b301143ed2d4 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -191,7 +191,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
         if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) ||
              !(boot_cpu_data.x86_vendor &
                (X86_VENDOR_INTEL | X86_VENDOR_AMD)) ||
-             rdmsr_safe(MSR_AMD_PATCHLEVEL, *val) )
+             rdmsr_safe(MSR_AMD_PATCHLEVEL, val) )
             goto gp_fault;
         break;
 
@@ -239,7 +239,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
             goto gp_fault;
 
         *val = 0;
-        if ( likely(!is_cpufreq_controller(d)) || rdmsr_safe(msr, *val) == 0 )
+        if ( likely(!is_cpufreq_controller(d)) || rdmsr_safe(msr, val) == 0 )
             break;
         goto gp_fault;
 
@@ -305,7 +305,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
             goto gp_fault;
         if ( !is_hardware_domain(d) )
             return X86EMUL_UNHANDLEABLE;
-        if ( rdmsr_safe(msr, *val) )
+        if ( rdmsr_safe(msr, val) )
             goto gp_fault;
         if ( msr == MSR_K8_SYSCFG )
             *val &= (SYSCFG_TOM2_FORCE_WB | SYSCFG_MTRR_TOM2_EN |
@@ -321,7 +321,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
     case MSR_FAM10H_MMIO_CONF_BASE:
         if ( !is_hardware_domain(d) ||
              !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ||
-             rdmsr_safe(msr, *val) )
+             rdmsr_safe(msr, val) )
             goto gp_fault;
 
         break;
diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c
index 3eba791889bd..21f9f795c1c7 100644
--- a/xen/arch/x86/platform_hypercall.c
+++ b/xen/arch/x86/platform_hypercall.c
@@ -186,7 +186,7 @@ void cf_check resource_access(void *info)
                 if ( unlikely(read_tsc) )
                     local_irq_save(flags);
 
-                ret = rdmsr_safe(entry->idx, entry->val);
+                ret = rdmsr_safe(entry->idx, &entry->val);
 
                 if ( unlikely(read_tsc) )
                 {
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index f3f012f8fb55..4afbee59e53e 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -248,7 +248,7 @@ static bool pci_cfg_ok(struct domain *currd, unsigned int start,
     {
         uint64_t msr_val;
 
-        if ( rdmsr_safe(MSR_AMD64_NB_CFG, msr_val) )
+        if ( rdmsr_safe(MSR_AMD64_NB_CFG, &msr_val) )
             return false;
         if ( msr_val & (1ULL << AMD64_NB_CFG_CF8_EXT_ENABLE_BIT) )
             start |= CF8_ADDR_HI(currd->arch.pci_cf8);
@@ -961,7 +961,7 @@ static int cf_check read_msr(
         return X86EMUL_OKAY;
 
     case MSR_IA32_MISC_ENABLE:
-        if ( rdmsr_safe(reg, *val) )
+        if ( rdmsr_safe(reg, val) )
             break;
         *val = guest_misc_enable(*val);
         return X86EMUL_OKAY;
@@ -991,7 +991,7 @@ static int cf_check read_msr(
         }
         /* fall through */
     default:
-        if ( currd->arch.msr_relaxed && !rdmsr_safe(reg, tmp) )
+        if ( currd->arch.msr_relaxed && !rdmsr_safe(reg, &tmp) )
         {
             *val = 0;
             return X86EMUL_OKAY;
@@ -1001,14 +1001,14 @@ static int cf_check read_msr(
         break;
 
     normal:
-        if ( rdmsr_safe(reg, *val) )
+        if ( rdmsr_safe(reg, val) )
             break;
         return X86EMUL_OKAY;
     }
 
  done:
     if ( ret != X86EMUL_OKAY && !curr->arch.pv.trap_ctxt[X86_EXC_GP].address &&
-         (reg >> 16) != 0x4000 && !rdmsr_safe(reg, tmp) )
+         (reg >> 16) != 0x4000 && !rdmsr_safe(reg, &tmp) )
     {
         gprintk(XENLOG_WARNING, "faking RDMSR 0x%08x\n", reg);
         *val = 0;
@@ -1095,7 +1095,7 @@ static int cf_check write_msr(
     case MSR_AMD64_NB_CFG:
         if ( !is_hwdom_pinned_vcpu(curr) )
             return X86EMUL_OKAY;
-        if ( (rdmsr_safe(MSR_AMD64_NB_CFG, temp) != 0) ||
+        if ( (rdmsr_safe(MSR_AMD64_NB_CFG, &temp) != 0) ||
              ((val ^ temp) & ~(1ULL << AMD64_NB_CFG_CF8_EXT_ENABLE_BIT)) )
             goto invalid;
         if ( wrmsr_safe(MSR_AMD64_NB_CFG, val) == 0 )
@@ -1108,7 +1108,7 @@ static int cf_check write_msr(
             break;
         if ( !is_hwdom_pinned_vcpu(curr) )
             return X86EMUL_OKAY;
-        if ( rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, temp) != 0 )
+        if ( rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, &temp) != 0 )
             break;
         if ( (pci_probe & PCI_PROBE_MASK) == PCI_PROBE_MMCONF ?
              temp != val :
@@ -1124,7 +1124,7 @@ static int cf_check write_msr(
         break;
 
     case MSR_IA32_MISC_ENABLE:
-        if ( rdmsr_safe(reg, temp) )
+        if ( rdmsr_safe(reg, &temp) )
             break;
         if ( val != guest_misc_enable(temp) )
             goto invalid;
@@ -1171,7 +1171,7 @@ static int cf_check write_msr(
         }
         /* fall through */
     default:
-        if ( currd->arch.msr_relaxed && !rdmsr_safe(reg, val) )
+        if ( currd->arch.msr_relaxed && !rdmsr_safe(reg, &val) )
             return X86EMUL_OKAY;
 
         gdprintk(XENLOG_WARNING,
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 1ff3d6835d9d..e71f62c60186 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -714,7 +714,7 @@ static bool __init check_smt_enabled(void)
      */
     if ( boot_cpu_data.vendor == X86_VENDOR_INTEL &&
          boot_cpu_data.family != 0xf && !cpu_has_hypervisor &&
-         !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, val) )
+         !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, &val) )
         return (MASK_EXTR(val, MSR_CTC_CORE_MASK) !=
                 MASK_EXTR(val, MSR_CTC_THREAD_MASK));
 
diff --git a/xen/arch/x86/x86_64/mmconfig-shared.c b/xen/arch/x86/x86_64/mmconfig-shared.c
index f1a3d42c5b21..d2364b32563f 100644
--- a/xen/arch/x86/x86_64/mmconfig-shared.c
+++ b/xen/arch/x86/x86_64/mmconfig-shared.c
@@ -149,7 +149,7 @@ static const char *__init cf_check pci_mmcfg_amd_fam10h(void)
         return NULL;
 
     address = MSR_FAM10H_MMIO_CONF_BASE;
-    if (rdmsr_safe(address, msr_content))
+    if ( rdmsr_safe(address, &msr_content) )
         return NULL;
 
     /* mmconfig is not enable */
diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c
index c55f02c97e16..b4105163cc78 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -2286,7 +2286,7 @@ static bool __init vtd_ept_page_compatible(const struct vtd_iommu *iommu)
 
     /* EPT is not initialised yet, so we must check the capability in
      * the MSR explicitly rather than use cpu_has_vmx_ept_*() */
-    if ( rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, ept_cap) != 0 ) 
+    if ( rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, &ept_cap) != 0 )
         return false;
 
     return (ept_has_2mb(ept_cap) && opt_hap_2mb) <=
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 02/16] x86/msr: Rework rdmsr_safe() using asm goto()
Date: Fri, 15 Aug 2025 21:41:03 +0100
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... on capable toolchains.

This avoids needing to hold rc in a register across the RDMSR, and in most
cases removes direct testing and branching based on rc, as the fault label can
be rearranged to directly land on the out-of-line block.

There is a subtle difference in behaviour.  The old behaviour would, on fault,
still produce 0's and write to val.

The new behaviour only writes val on success, and write_msr() is the only
place where this matters.  Move temp out of switch() scope and initialise it
to 0.

Resolves: https://gitlab.com/xen-project/xen/-/work_items/217
Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

Doing this safely does depend on getting GCC-14 into CI somewhere.  Debian
13/Trixie satisfies this, as does archlinux I expect.
---
 xen/arch/x86/include/asm/msr.h | 19 +++++++++++++++++++
 xen/arch/x86/pv/emul-priv-op.c |  3 +--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index d2c86ddb09e9..6a97b41bae07 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -55,6 +55,24 @@ static inline void wrmsrns(uint32_t msr, uint64_t val)
 /* rdmsr with exception handling */
 static inline int rdmsr_safe(unsigned int msr, uint64_t *val)
 {
+#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
+    uint64_t lo, hi;
+
+    asm_inline goto (
+        "1: rdmsr\n\t"
+        _ASM_EXTABLE(1b, %l[fault])
+        : "=a" (lo), "=d" (hi)
+        : "c" (msr)
+        :
+        : fault );
+
+    *val = lo | (hi << 32);
+
+    return 0;
+
+ fault:
+    return -EFAULT;
+#else
     int rc;
     uint64_t lo, hi;
 
@@ -73,6 +91,7 @@ static inline int rdmsr_safe(unsigned int msr, uint64_t *val)
     *val = lo | (hi << 32);
 
     return rc;
+#endif
 }
 
 /* wrmsr with exception handling */
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 4afbee59e53e..c3a484c50bf8 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -1027,6 +1027,7 @@ static int cf_check write_msr(
     struct vcpu *curr = current;
     const struct domain *currd = curr->domain;
     const struct cpu_policy *cp = currd->arch.cpu_policy;
+    uint64_t temp = 0;
     bool vpmu_msr = false;
     int ret;
 
@@ -1040,8 +1041,6 @@ static int cf_check write_msr(
 
     switch ( reg )
     {
-        uint64_t temp;
-
     case MSR_FS_BASE:
     case MSR_GS_BASE:
     case MSR_SHADOW_GS_BASE:
-- 
2.39.5



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        Fri, 15 Aug 2025 13:41:24 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 05/16] x86/msr: Split out fsgsbase.h
Date: Fri, 15 Aug 2025 21:41:06 +0100
Message-Id: <20250815204117.3312742-6-andrew.cooper3@citrix.com>
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It is a large and complex API, but only a handful of translation units need
access.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/domain.c               |   1 +
 xen/arch/x86/hvm/vmx/vmx.c          |   1 +
 xen/arch/x86/include/asm/fsgsbase.h | 114 ++++++++++++++++++++++++++++
 xen/arch/x86/include/asm/msr.h      | 105 -------------------------
 xen/arch/x86/pv/domain.c            |   1 +
 xen/arch/x86/pv/emul-priv-op.c      |   1 +
 xen/arch/x86/pv/misc-hypercalls.c   |   1 +
 xen/arch/x86/traps.c                |   1 +
 8 files changed, 120 insertions(+), 105 deletions(-)
 create mode 100644 xen/arch/x86/include/asm/fsgsbase.h

diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 1bbe53e36b59..3015aac4adbc 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -44,6 +44,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 4664a014bc8a..f97a7746531a 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/include/asm/fsgsbase.h b/xen/arch/x86/include/asm/fsgsbase.h
new file mode 100644
index 000000000000..03e6a85d31ce
--- /dev/null
+++ b/xen/arch/x86/include/asm/fsgsbase.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef X86_FSGSBASE_H
+#define X86_FSGSBASE_H
+
+#include 
+#include 
+#include 
+
+/*
+ * On hardware supporting FSGSBASE, the value loaded into hardware is the
+ * guest kernel's choice for 64bit PV guests (Xen's choice for Idle, HVM and
+ * 32bit PV).
+ *
+ * Therefore, the {RD,WR}{FS,GS}BASE instructions are only safe to use if
+ * %cr4.fsgsbase is set.
+ */
+static inline unsigned long __rdfsbase(void)
+{
+    unsigned long base;
+
+    asm volatile ( "rdfsbase %0" : "=r" (base) );
+
+    return base;
+}
+
+static inline unsigned long __rdgsbase(void)
+{
+    unsigned long base;
+
+    asm volatile ( "rdgsbase %0" : "=r" (base) );
+
+    return base;
+}
+
+static inline void __wrfsbase(unsigned long base)
+{
+    asm volatile ( "wrfsbase %0" :: "r" (base) );
+}
+
+static inline void __wrgsbase(unsigned long base)
+{
+    asm volatile ( "wrgsbase %0" :: "r" (base) );
+}
+
+static inline unsigned long read_fs_base(void)
+{
+    unsigned long base;
+
+    if ( read_cr4() & X86_CR4_FSGSBASE )
+        return __rdfsbase();
+
+    rdmsrl(MSR_FS_BASE, base);
+
+    return base;
+}
+
+static inline unsigned long read_gs_base(void)
+{
+    unsigned long base;
+
+    if ( read_cr4() & X86_CR4_FSGSBASE )
+        return __rdgsbase();
+
+    rdmsrl(MSR_GS_BASE, base);
+
+    return base;
+}
+
+static inline unsigned long read_gs_shadow(void)
+{
+    unsigned long base;
+
+    if ( read_cr4() & X86_CR4_FSGSBASE )
+    {
+        asm volatile ( "swapgs" );
+        base = __rdgsbase();
+        asm volatile ( "swapgs" );
+    }
+    else
+        rdmsrl(MSR_SHADOW_GS_BASE, base);
+
+    return base;
+}
+
+static inline void write_fs_base(unsigned long base)
+{
+    if ( read_cr4() & X86_CR4_FSGSBASE )
+        __wrfsbase(base);
+    else
+        wrmsrl(MSR_FS_BASE, base);
+}
+
+static inline void write_gs_base(unsigned long base)
+{
+    if ( read_cr4() & X86_CR4_FSGSBASE )
+        __wrgsbase(base);
+    else
+        wrmsrl(MSR_GS_BASE, base);
+}
+
+static inline void write_gs_shadow(unsigned long base)
+{
+    if ( read_cr4() & X86_CR4_FSGSBASE )
+    {
+        asm volatile ( "swapgs\n\t"
+                       "wrgsbase %0\n\t"
+                       "swapgs"
+                       :: "r" (base) );
+    }
+    else
+        wrmsrl(MSR_SHADOW_GS_BASE, base);
+}
+
+#endif /* X86_FSGSBASE_H */
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 787517802d9d..4a35cd0fdff6 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -168,111 +168,6 @@ static inline uint64_t rdtsc_ordered(void)
 			  : "=a" (low), "=d" (high) \
 			  : "c" (counter))
 
-/*
- * On hardware supporting FSGSBASE, the value loaded into hardware is the
- * guest kernel's choice for 64bit PV guests (Xen's choice for Idle, HVM and
- * 32bit PV).
- *
- * Therefore, the {RD,WR}{FS,GS}BASE instructions are only safe to use if
- * %cr4.fsgsbase is set.
- */
-static inline unsigned long __rdfsbase(void)
-{
-    unsigned long base;
-
-    asm volatile ( "rdfsbase %0" : "=r" (base) );
-
-    return base;
-}
-
-static inline unsigned long __rdgsbase(void)
-{
-    unsigned long base;
-
-    asm volatile ( "rdgsbase %0" : "=r" (base) );
-
-    return base;
-}
-
-static inline void __wrfsbase(unsigned long base)
-{
-    asm volatile ( "wrfsbase %0" :: "r" (base) );
-}
-
-static inline void __wrgsbase(unsigned long base)
-{
-    asm volatile ( "wrgsbase %0" :: "r" (base) );
-}
-
-static inline unsigned long read_fs_base(void)
-{
-    unsigned long base;
-
-    if ( read_cr4() & X86_CR4_FSGSBASE )
-        return __rdfsbase();
-
-    rdmsrl(MSR_FS_BASE, base);
-
-    return base;
-}
-
-static inline unsigned long read_gs_base(void)
-{
-    unsigned long base;
-
-    if ( read_cr4() & X86_CR4_FSGSBASE )
-        return __rdgsbase();
-
-    rdmsrl(MSR_GS_BASE, base);
-
-    return base;
-}
-
-static inline unsigned long read_gs_shadow(void)
-{
-    unsigned long base;
-
-    if ( read_cr4() & X86_CR4_FSGSBASE )
-    {
-        asm volatile ( "swapgs" );
-        base = __rdgsbase();
-        asm volatile ( "swapgs" );
-    }
-    else
-        rdmsrl(MSR_SHADOW_GS_BASE, base);
-
-    return base;
-}
-
-static inline void write_fs_base(unsigned long base)
-{
-    if ( read_cr4() & X86_CR4_FSGSBASE )
-        __wrfsbase(base);
-    else
-        wrmsrl(MSR_FS_BASE, base);
-}
-
-static inline void write_gs_base(unsigned long base)
-{
-    if ( read_cr4() & X86_CR4_FSGSBASE )
-        __wrgsbase(base);
-    else
-        wrmsrl(MSR_GS_BASE, base);
-}
-
-static inline void write_gs_shadow(unsigned long base)
-{
-    if ( read_cr4() & X86_CR4_FSGSBASE )
-    {
-        asm volatile ( "swapgs\n\t"
-                       "wrgsbase %0\n\t"
-                       "swapgs"
-                       :: "r" (base) );
-    }
-    else
-        wrmsrl(MSR_SHADOW_GS_BASE, base);
-}
-
 DECLARE_PER_CPU(uint64_t, efer);
 static inline uint64_t read_efer(void)
 {
diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c
index 9334da1dab93..9c4785c187dd 100644
--- a/xen/arch/x86/pv/domain.c
+++ b/xen/arch/x86/pv/domain.c
@@ -12,6 +12,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index c3a484c50bf8..225d4cff03c1 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/pv/misc-hypercalls.c b/xen/arch/x86/pv/misc-hypercalls.c
index 17030d800d1b..7a37f16bf038 100644
--- a/xen/arch/x86/pv/misc-hypercalls.c
+++ b/xen/arch/x86/pv/misc-hypercalls.c
@@ -10,6 +10,7 @@
 #include 
 
 #include 
+#include 
 
 long do_set_debugreg(int reg, unsigned long value)
 {
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 270b93ed623e..0c5393cb2166 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 06/16] x86/msr: Split out tsc.h
Date: Fri, 15 Aug 2025 21:41:07 +0100
Message-Id: <20250815204117.3312742-7-andrew.cooper3@citrix.com>
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The TSC functionality is only related to MSRs by write_tsc(), and this really
does not want to be available as widely as is currently is.

asm/time.h shouldn't be including asm/msr.h, but this turns out to be
sufficiently tangled that I've chosen to break it out into it's own patch.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/msr.h  | 39 ----------------------------
 xen/arch/x86/include/asm/time.h |  1 +
 xen/arch/x86/include/asm/tsc.h  | 46 +++++++++++++++++++++++++++++++++
 3 files changed, 47 insertions(+), 39 deletions(-)
 create mode 100644 xen/arch/x86/include/asm/tsc.h

diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 4a35cd0fdff6..1c0e768d9123 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -124,45 +124,6 @@ static inline void msr_split(struct cpu_user_regs *regs, uint64_t val)
     regs->rax = (uint32_t)val;
 }
 
-static inline uint64_t rdtsc(void)
-{
-    uint64_t low, high;
-
-    __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
-
-    return (high << 32) | low;
-}
-
-static inline uint64_t rdtsc_ordered(void)
-{
-    uint64_t low, high, aux;
-
-    /*
-     * The RDTSC instruction is not serializing.  Make it dispatch serializing
-     * for the purposes here by issuing LFENCE (or MFENCE if necessary) ahead
-     * of it.
-     *
-     * RDTSCP, otoh, "does wait until all previous instructions have executed
-     * and all previous loads are globally visible" (SDM) / "forces all older
-     * instructions to retire before reading the timestamp counter" (APM).
-     */
-    alternative_io_2("lfence; rdtsc",
-                     "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
-                     "rdtscp",        X86_FEATURE_RDTSCP,
-                     ASM_OUTPUT2("=a" (low), "=d" (high), "=c" (aux)),
-                     /* no inputs */);
-
-    return (high << 32) | low;
-}
-
-#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
-#define write_tsc(val) ({                                       \
-    /* Reliable TSCs are in lockstep across all CPUs. We should \
-     * never write to them. */                                  \
-    ASSERT(!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));            \
-    __write_tsc(val);                                           \
-})
-
 #define rdpmc(counter,low,high) \
      __asm__ __volatile__("rdpmc" \
 			  : "=a" (low), "=d" (high) \
diff --git a/xen/arch/x86/include/asm/time.h b/xen/arch/x86/include/asm/time.h
index 3dfbb5297a25..c55b69831448 100644
--- a/xen/arch/x86/include/asm/time.h
+++ b/xen/arch/x86/include/asm/time.h
@@ -3,6 +3,7 @@
 #define __X86_TIME_H__
 
 #include 
+#include 
 
 typedef u64 cycles_t;
 
diff --git a/xen/arch/x86/include/asm/tsc.h b/xen/arch/x86/include/asm/tsc.h
new file mode 100644
index 000000000000..5f48fed26c23
--- /dev/null
+++ b/xen/arch/x86/include/asm/tsc.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef X86_TSC_H
+#define X86_TSC_H
+
+#include 
+
+static inline uint64_t rdtsc(void)
+{
+    uint64_t low, high;
+
+    asm volatile ( "rdtsc" : "=a" (low), "=d" (high) );
+
+    return (high << 32) | low;
+}
+
+static inline uint64_t rdtsc_ordered(void)
+{
+    uint64_t low, high, aux;
+
+    /*
+     * The RDTSC instruction is not serializing.  Make it dispatch serializing
+     * for the purposes here by issuing LFENCE (or MFENCE if necessary) ahead
+     * of it.
+     *
+     * RDTSCP, otoh, "does wait until all previous instructions have executed
+     * and all previous loads are globally visible" (SDM) / "forces all older
+     * instructions to retire before reading the timestamp counter" (APM).
+     */
+    alternative_io_2("lfence; rdtsc",
+                     "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
+                     "rdtscp",        X86_FEATURE_RDTSCP,
+                     ASM_OUTPUT2("=a" (low), "=d" (high), "=c" (aux)),
+                     /* no inputs */);
+
+    return (high << 32) | low;
+}
+
+#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
+#define write_tsc(val) ({                                       \
+    /* Reliable TSCs are in lockstep across all CPUs. We should \
+     * never write to them. */                                  \
+    ASSERT(!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));            \
+    __write_tsc(val);                                           \
+})
+
+#endif /* X86_TSC_H */
-- 
2.39.5



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        Fri, 15 Aug 2025 13:41:25 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 07/16] x86/msr: Move msr_{split,fold}() into asm/cpu-user-regs.h
Date: Fri, 15 Aug 2025 21:41:08 +0100
Message-Id: <20250815204117.3312742-8-andrew.cooper3@citrix.com>
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Now there is a local header, asm/cpu-user-regs.h is a far better place for
these to live.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/cpu-user-regs.h | 11 +++++++++++
 xen/arch/x86/include/asm/msr.h           | 11 -----------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/include/asm/cpu-user-regs.h
index d700a3ef3447..5b283a2f6d02 100644
--- a/xen/arch/x86/include/asm/cpu-user-regs.h
+++ b/xen/arch/x86/include/asm/cpu-user-regs.h
@@ -55,4 +55,15 @@ struct cpu_user_regs
      */
 };
 
+static inline uint64_t msr_fold(const struct cpu_user_regs *regs)
+{
+    return (regs->rdx << 32) | regs->eax;
+}
+
+static inline void msr_split(struct cpu_user_regs *regs, uint64_t val)
+{
+    regs->rdx = val >> 32;
+    regs->rax = (uint32_t)val;
+}
+
 #endif /* X86_CPU_USER_REGS_H */
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 1c0e768d9123..4aeb06f6524d 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -113,17 +113,6 @@ static inline int wrmsr_safe(unsigned int msr, uint64_t val)
     return -EFAULT;
 }
 
-static inline uint64_t msr_fold(const struct cpu_user_regs *regs)
-{
-    return (regs->rdx << 32) | regs->eax;
-}
-
-static inline void msr_split(struct cpu_user_regs *regs, uint64_t val)
-{
-    regs->rdx = val >> 32;
-    regs->rax = (uint32_t)val;
-}
-
 #define rdpmc(counter,low,high) \
      __asm__ __volatile__("rdpmc" \
 			  : "=a" (low), "=d" (high) \
-- 
2.39.5



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        Fri, 15 Aug 2025 13:41:28 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 10/16] x86/svm: Rename variable in svm_msr_write_intercept()
Date: Fri, 15 Aug 2025 21:41:11 +0100
Message-Id: <20250815204117.3312742-11-andrew.cooper3@citrix.com>
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We're about to turn the rdmsr() macro into a real function, at which point
Eclair complains that we're now shadowing an identifer.

Rename rdmsr to is_rdmsr.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/hvm/svm/svm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 4fc6206edac0..90f19d98422a 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -2087,14 +2087,14 @@ static int cf_check svm_msr_write_intercept(
 static void svm_do_msr_access(struct cpu_user_regs *regs)
 {
     struct vcpu *curr = current;
-    bool rdmsr = curr->arch.hvm.svm.vmcb->exitinfo1 == 0;
-    int rc, inst_len = svm_get_insn_len(curr, rdmsr ? INSTR_RDMSR
-                                                    : INSTR_WRMSR);
+    bool is_rdmsr = curr->arch.hvm.svm.vmcb->exitinfo1 == 0;
+    int rc, inst_len = svm_get_insn_len(curr, is_rdmsr ? INSTR_RDMSR
+                                                       : INSTR_WRMSR);
 
     if ( inst_len == 0 )
         return;
 
-    if ( rdmsr )
+    if ( is_rdmsr )
     {
         uint64_t msr_content = 0;
 
-- 
2.39.5



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        Fri, 15 Aug 2025 13:41:26 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 08/16] x86: Clean up asm/time.h
Date: Fri, 15 Aug 2025 21:41:09 +0100
Message-Id: <20250815204117.3312742-9-andrew.cooper3@citrix.com>
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With asm/tsc.h split out, asm/time.h shouldn't be including asm/msr.h, but it
turns out that an outrageous number of files (even some headers) are pulling
their dependentices transitively through asm/time.h -> asm/msr.h

Most are asm/msr{,-index}.h, but in some cases it's printk(), va_args, and
even PRIxxx macros.

Give asm/time.h an SPDX tag, and strip trailing whitespace.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

Randconfig in CI has stopped finding new issues, but there's a reasonable risk
that more is still lurking.

ubsan.c needing asm/processor.h isn't good but it does work with all 4
architectures right now.  We really ought to have dump_execution_state()
somewhere more common.
---
 xen/arch/x86/acpi/cpufreq/acpi.c    |  3 ++-
 xen/arch/x86/acpi/cpufreq/cpufreq.c |  3 +++
 xen/arch/x86/cpu/mcheck/mce.h       |  1 +
 xen/arch/x86/debug.c                |  1 +
 xen/arch/x86/guest/hyperv/hyperv.c  |  1 +
 xen/arch/x86/hvm/ioreq.c            |  1 +
 xen/arch/x86/hvm/vmx/vvmx.c         |  1 +
 xen/arch/x86/include/asm/hvm/hvm.h  |  1 +
 xen/arch/x86/include/asm/time.h     | 12 ++++++------
 xen/arch/x86/machine_kexec.c        |  1 +
 xen/arch/x86/psr.c                  |  2 ++
 xen/arch/x86/tboot.c                |  1 +
 xen/arch/x86/xstate.c               |  1 +
 xen/common/efi/runtime.c            |  1 +
 xen/common/ubsan/ubsan.c            |  2 ++
 xen/drivers/acpi/apei/apei-base.c   |  1 +
 xen/drivers/acpi/tables/tbfadt.c    |  2 ++
 xen/drivers/acpi/utilities/utmisc.c |  3 +++
 xen/lib/x86/private.h               |  2 +-
 19 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/acpi.c
index b81f2afc9b9b..567c10dd0643 100644
--- a/xen/arch/x86/acpi/cpufreq/acpi.c
+++ b/xen/arch/x86/acpi/cpufreq/acpi.c
@@ -14,7 +14,8 @@
 #include 
 #include 
 #include 
-#include 
+
+#include 
 
 #include 
 #include 
diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c
index 45f301f354ac..d18735c7ae1b 100644
--- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
+++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
@@ -30,6 +30,9 @@
 #include 
 #include 
 #include 
+
+#include 
+
 #include 
 
 struct acpi_cpufreq_data *cpufreq_drv_data[NR_CPUS];
diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h
index 6157a41aaeea..aa00e94cb5b1 100644
--- a/xen/arch/x86/cpu/mcheck/mce.h
+++ b/xen/arch/x86/cpu/mcheck/mce.h
@@ -8,6 +8,7 @@
 #include 
 
 #include 
+#include 
 #include 
 
 #include "x86_mca.h"
diff --git a/xen/arch/x86/debug.c b/xen/arch/x86/debug.c
index 11b0a7e5475a..037f97d6f17b 100644
--- a/xen/arch/x86/debug.c
+++ b/xen/arch/x86/debug.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * Merge new bits into dr6.  'new' is always given in positive polarity,
diff --git a/xen/arch/x86/guest/hyperv/hyperv.c b/xen/arch/x86/guest/hyperv/hyperv.c
index 6989af38f180..90757e079362 100644
--- a/xen/arch/x86/guest/hyperv/hyperv.c
+++ b/xen/arch/x86/guest/hyperv/hyperv.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "private.h"
diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c
index 98b0dd7972c2..d79a1a23655e 100644
--- a/xen/arch/x86/hvm/ioreq.c
+++ b/xen/arch/x86/hvm/ioreq.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 6201665d9f4c..e4f3a5fe4c71 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/hvm/hvm.h
index 228f47dbde8b..5c5a790f9e41 100644
--- a/xen/arch/x86/include/asm/hvm/hvm.h
+++ b/xen/arch/x86/include/asm/hvm/hvm.h
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 struct pirq; /* needed by pi_update_irte */
diff --git a/xen/arch/x86/include/asm/time.h b/xen/arch/x86/include/asm/time.h
index c55b69831448..e474a76e64df 100644
--- a/xen/arch/x86/include/asm/time.h
+++ b/xen/arch/x86/include/asm/time.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef X86_TIME_H
+#define X86_TIME_H
 
-#ifndef __X86_TIME_H__
-#define __X86_TIME_H__
-
-#include 
 #include 
 
 typedef u64 cycles_t;
@@ -38,6 +37,7 @@ uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks);
 
 uint64_t tsc_ticks2ns(uint64_t ticks);
 
+struct cpu_user_regs;
 uint64_t pv_soft_rdtsc(const struct vcpu *v, const struct cpu_user_regs *regs);
 uint64_t gtime_to_gtsc(const struct domain *d, uint64_t time);
 uint64_t gtsc_to_gtime(const struct domain *d, uint64_t tsc);
@@ -47,7 +47,7 @@ int tsc_set_info(struct domain *d, uint32_t tsc_mode, uint64_t elapsed_nsec,
 
 void tsc_get_info(struct domain *d, uint32_t *tsc_mode, uint64_t *elapsed_nsec,
                   uint32_t *gtsc_khz, uint32_t *incarnation);
-   
+
 
 void force_update_vcpu_system_time(struct vcpu *v);
 
@@ -93,4 +93,4 @@ u64 scale_delta(u64 delta, const struct time_scale *scale);
 #define PIT_STATUS_NULL_COUNT (1 << 6)
 /* Lower bits match Timer Control Word. */
 
-#endif /* __X86_TIME_H__ */
+#endif /* X86_TIME_H */
diff --git a/xen/arch/x86/machine_kexec.c b/xen/arch/x86/machine_kexec.c
index 35fa5c82e9c2..f921eec5aae6 100644
--- a/xen/arch/x86/machine_kexec.c
+++ b/xen/arch/x86/machine_kexec.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 /*
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 499d320e6163..9c7aab9f4021 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -18,6 +18,8 @@
 #include 
 #include 
 #include 
+
+#include 
 #include 
 
 /*
diff --git a/xen/arch/x86/tboot.c b/xen/arch/x86/tboot.c
index 319116857d4a..9d9bb6e7cf6d 100644
--- a/xen/arch/x86/tboot.c
+++ b/xen/arch/x86/tboot.c
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c
index f6d677eb121d..e990abc9d18c 100644
--- a/xen/arch/x86/xstate.c
+++ b/xen/arch/x86/xstate.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/xen/common/efi/runtime.c b/xen/common/efi/runtime.c
index 7e1fce291d92..42386c6bde42 100644
--- a/xen/common/efi/runtime.c
+++ b/xen/common/efi/runtime.c
@@ -33,6 +33,7 @@ void efi_rs_leave(struct efi_rs_state *state);
 
 #ifndef CONFIG_ARM
 # include 
+# include 
 # include 
 # include 
 #endif
diff --git a/xen/common/ubsan/ubsan.c b/xen/common/ubsan/ubsan.c
index 20aa0cb598e1..15ae34816412 100644
--- a/xen/common/ubsan/ubsan.c
+++ b/xen/common/ubsan/ubsan.c
@@ -16,6 +16,8 @@
 #include 
 #include 
 
+#include 
+
 #define __noreturn    noreturn
 #define pr_err(...) printk(XENLOG_ERR __VA_ARGS__)
 struct xen_ubsan { int in_ubsan; };
diff --git a/xen/drivers/acpi/apei/apei-base.c b/xen/drivers/acpi/apei/apei-base.c
index 4fe99573a220..1722698ba675 100644
--- a/xen/drivers/acpi/apei/apei-base.c
+++ b/xen/drivers/acpi/apei/apei-base.c
@@ -36,6 +36,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
diff --git a/xen/drivers/acpi/tables/tbfadt.c b/xen/drivers/acpi/tables/tbfadt.c
index a03836e0dc8a..32678700bdc8 100644
--- a/xen/drivers/acpi/tables/tbfadt.c
+++ b/xen/drivers/acpi/tables/tbfadt.c
@@ -42,6 +42,8 @@
  */
 
 #include 
+#include 
+
 #include 
 #include 
 
diff --git a/xen/drivers/acpi/utilities/utmisc.c b/xen/drivers/acpi/utilities/utmisc.c
index ee22c83e3842..b7756e4ebf29 100644
--- a/xen/drivers/acpi/utilities/utmisc.c
+++ b/xen/drivers/acpi/utilities/utmisc.c
@@ -42,6 +42,9 @@
  */
 
 #include 
+#include 
+#include 
+
 #include 
 
 #define _COMPONENT          ACPI_UTILITIES
diff --git a/xen/lib/x86/private.h b/xen/lib/x86/private.h
index 60bb82a400b7..aedd8e482121 100644
--- a/xen/lib/x86/private.h
+++ b/xen/lib/x86/private.h
@@ -10,7 +10,7 @@
 #include 
 #include 
 
-#include 
+#include 
 
 #define copy_to_buffer_offset copy_to_guest_offset
 #define copy_from_buffer_offset copy_from_guest_offset
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 09/16] x86: Clean up asm/msr.h
Date: Fri, 15 Aug 2025 21:41:10 +0100
Message-Id: <20250815204117.3312742-10-andrew.cooper3@citrix.com>
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Now that content has been split out, minimise the header files as msr.h is
included by many translation units.  A few more TUs were pulling dependencies
in transitively, so fix them up.

Give asm/time.h an SPDX tag, and strip trailing whitespace.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/acpi/cpufreq/acpi.c   |  2 ++
 xen/arch/x86/acpi/cpufreq/hwp.c    |  4 ++++
 xen/arch/x86/cpu/microcode/intel.c |  4 ++++
 xen/arch/x86/include/asm/msr.h     | 22 ++++++----------------
 xen/arch/x86/tsx.c                 |  2 ++
 5 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/acpi.c
index 567c10dd0643..b02745941701 100644
--- a/xen/arch/x86/acpi/cpufreq/acpi.c
+++ b/xen/arch/x86/acpi/cpufreq/acpi.c
@@ -14,8 +14,10 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
+#include 
 
 #include 
 #include 
diff --git a/xen/arch/x86/acpi/cpufreq/hwp.c b/xen/arch/x86/acpi/cpufreq/hwp.c
index 26dce9aaf89a..38037d8300cd 100644
--- a/xen/arch/x86/acpi/cpufreq/hwp.c
+++ b/xen/arch/x86/acpi/cpufreq/hwp.c
@@ -8,8 +8,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+
 #include 
+#include 
+
 #include 
 
 static bool __ro_after_init hwp_in_use;
diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcode/intel.c
index 3f8e9ca63b55..281993e725cc 100644
--- a/xen/arch/x86/cpu/microcode/intel.c
+++ b/xen/arch/x86/cpu/microcode/intel.c
@@ -23,8 +23,12 @@
 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 #include 
+#include 
 #include 
 
 #include "private.h"
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 4aeb06f6524d..c0d66562956d 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -1,18 +1,13 @@
-#ifndef __ASM_MSR_H
-#define __ASM_MSR_H
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef X86_MSR_H
+#define X86_MSR_H
 
-#include "msr-index.h"
-
-#include 
 #include 
 #include 
-#include 
-
-#include 
 
+#include 
 #include 
-#include 
-#include 
+#include 
 
 #define rdmsr(msr,val1,val2) \
      __asm__ __volatile__("rdmsr" \
@@ -113,11 +108,6 @@ static inline int wrmsr_safe(unsigned int msr, uint64_t val)
     return -EFAULT;
 }
 
-#define rdpmc(counter,low,high) \
-     __asm__ __volatile__("rdpmc" \
-			  : "=a" (low), "=d" (high) \
-			  : "c" (counter))
-
 DECLARE_PER_CPU(uint64_t, efer);
 static inline uint64_t read_efer(void)
 {
@@ -144,4 +134,4 @@ static inline void wrmsr_tsc_aux(uint32_t val)
     }
 }
 
-#endif /* __ASM_MSR_H */
+#endif /* X86_MSR_H */
diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c
index fbdd05971c8b..2a0c7c08a2ba 100644
--- a/xen/arch/x86/tsx.c
+++ b/xen/arch/x86/tsx.c
@@ -1,7 +1,9 @@
 #include 
 #include 
+
 #include 
 #include 
+#include 
 
 /*
  * Valid values:
-- 
2.39.5



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        Fri, 15 Aug 2025 13:41:29 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 12/16] x86/msr: Change wrmsr() to take a single parameter
Date: Fri, 15 Aug 2025 21:41:13 +0100
Message-Id: <20250815204117.3312742-13-andrew.cooper3@citrix.com>
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Mirroring the cleanup to rdmsr(), do the same to wrmsr().  It now has the same
API as wrmsrl(), but we'll want to drop that wrapper in due course.

It's telling that almost all remaining users pass in 0.  Most are converted
directly to WRMSRNS, but a few are not.

MSR_VIRT_SPEC_CTRL is unconditionally intercepted is orders of magnitude more
expensive than just serialising.  In disable_lapic_nmi_watchdog(), the P4 case
won't run on hardware which has anything more than plain WRMSR.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/cpu/amd.c                  |  2 +-
 xen/arch/x86/hvm/vmx/vmcs.c             |  2 +-
 xen/arch/x86/include/asm/msr.h          | 20 ++++++++++----------
 xen/arch/x86/nmi.c                      | 18 +++++++++---------
 xen/arch/x86/oprofile/op_model_athlon.c |  2 +-
 5 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 769413e96a3f..e03fba935510 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -934,7 +934,7 @@ void amd_set_legacy_ssbd(bool enable)
 		return;
 
 	if (cpu_has_virt_ssbd)
-		wrmsr(MSR_VIRT_SPEC_CTRL, enable ? SPEC_CTRL_SSBD : 0, 0);
+		wrmsr(MSR_VIRT_SPEC_CTRL, enable ? SPEC_CTRL_SSBD : 0);
 	else if (amd_legacy_ssbd)
 		core_set_legacy_ssbd(enable);
 	else
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 1fa61a944b23..328cba64387d 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -754,7 +754,7 @@ static int _vmx_cpu_up(bool bsp)
         eax |= IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX;
         if ( test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) )
             eax |= IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX;
-        wrmsr(MSR_IA32_FEATURE_CONTROL, eax, 0);
+        wrmsrns(MSR_IA32_FEATURE_CONTROL, eax);
     }
 
     if ( (rc = vmx_init_vmcs_config(bsp)) != 0 )
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index f1b2bd5adc9f..1bd27b989a4d 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -15,13 +15,17 @@
  *   uint64_t foo = rdmsr(MSR_BAR);
  *   wrmsrns(MSR_BAR, foo);
  *
+ * and, if architectural serialisaition is necessary, or there are other
+ * reasons that WRMSRNS is inapplicable, then:
+ *
+ *   wrmsr(MSR_BAR, foo);
+ *
  * In addition, *_safe() wrappers exist to cope gracefully with a #GP.
  *
  *
  * All legacy forms are to be phased out:
  *
  *  rdmsrl(MSR_FOO, val);
- *  wrmsr(MSR_FOO, lo, hi);
  *  wrmsrl(MSR_FOO, val);
  */
 
@@ -43,17 +47,13 @@ static inline uint64_t rdmsr(unsigned int msr)
        val = a__ | ((u64)b__<<32); \
 } while(0)
 
-#define wrmsr(msr,val1,val2) \
-     __asm__ __volatile__("wrmsr" \
-			  : /* no outputs */ \
-			  : "c" (msr), "a" (val1), "d" (val2))
-
-static inline void wrmsrl(unsigned int msr, uint64_t val)
+static inline void wrmsr(unsigned int msr, uint64_t val)
 {
-        uint32_t lo = val, hi = val >> 32;
+    uint32_t lo = val, hi = val >> 32;
 
-        wrmsr(msr, lo, hi);
+    asm volatile ( "wrmsr" :: "a" (lo), "d" (hi), "c" (msr) );
 }
+#define wrmsrl(msr, val) wrmsr(msr, val)
 
 /* Non-serialising WRMSR, when available.  Falls back to a serialising WRMSR. */
 static inline void wrmsrns(uint32_t msr, uint64_t val)
@@ -151,7 +151,7 @@ static inline void wrmsr_tsc_aux(uint32_t val)
 
     if ( *this_tsc_aux != val )
     {
-        wrmsr(MSR_TSC_AUX, val, 0);
+        wrmsrns(MSR_TSC_AUX, val);
         *this_tsc_aux = val;
     }
 }
diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c
index 9793fa23168d..0d4aaa5a0b57 100644
--- a/xen/arch/x86/nmi.c
+++ b/xen/arch/x86/nmi.c
@@ -218,16 +218,16 @@ void disable_lapic_nmi_watchdog(void)
         return;
     switch (boot_cpu_data.x86_vendor) {
     case X86_VENDOR_AMD:
-        wrmsr(MSR_K7_EVNTSEL0, 0, 0);
+        wrmsrns(MSR_K7_EVNTSEL0, 0);
         break;
     case X86_VENDOR_INTEL:
         switch (boot_cpu_data.x86) {
         case 6:
-            wrmsr(MSR_P6_EVNTSEL(0), 0, 0);
+            wrmsrns(MSR_P6_EVNTSEL(0), 0);
             break;
         case 15:
-            wrmsr(MSR_P4_IQ_CCCR0, 0, 0);
-            wrmsr(MSR_P4_CRU_ESCR0, 0, 0);
+            wrmsr(MSR_P4_IQ_CCCR0, 0);
+            wrmsr(MSR_P4_CRU_ESCR0, 0);
             break;
         }
         break;
@@ -282,7 +282,7 @@ static void clear_msr_range(unsigned int base, unsigned int n)
     unsigned int i;
 
     for (i = 0; i < n; i++)
-        wrmsr(base+i, 0, 0);
+        wrmsrns(base + i, 0);
 }
 
 static inline void write_watchdog_counter(const char *descr)
@@ -308,11 +308,11 @@ static void setup_k7_watchdog(void)
         | K7_EVNTSEL_USR
         | K7_NMI_EVENT;
 
-    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
+    wrmsr(MSR_K7_EVNTSEL0, evntsel);
     write_watchdog_counter("K7_PERFCTR0");
     apic_write(APIC_LVTPC, APIC_DM_NMI);
     evntsel |= K7_EVNTSEL_ENABLE;
-    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
+    wrmsr(MSR_K7_EVNTSEL0, evntsel);
 }
 
 static void setup_p6_watchdog(unsigned counter)
@@ -338,11 +338,11 @@ static void setup_p6_watchdog(unsigned counter)
         | P6_EVNTSEL_USR
         | counter;
 
-    wrmsr(MSR_P6_EVNTSEL(0), evntsel, 0);
+    wrmsrns(MSR_P6_EVNTSEL(0), evntsel);
     write_watchdog_counter("P6_PERFCTR0");
     apic_write(APIC_LVTPC, APIC_DM_NMI);
     evntsel |= P6_EVNTSEL0_ENABLE;
-    wrmsr(MSR_P6_EVNTSEL(0), evntsel, 0);
+    wrmsrns(MSR_P6_EVNTSEL(0), evntsel);
 }
 
 static void setup_p4_watchdog(void)
diff --git a/xen/arch/x86/oprofile/op_model_athlon.c b/xen/arch/x86/oprofile/op_model_athlon.c
index bf897a4b6328..fd454b04c353 100644
--- a/xen/arch/x86/oprofile/op_model_athlon.c
+++ b/xen/arch/x86/oprofile/op_model_athlon.c
@@ -34,7 +34,7 @@
 #define MAX_COUNTERS FAM15H_NUM_COUNTERS
 
 #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, (msr_content));} while (0)
-#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1);} while (0)
+#define CTR_WRITE(l,msrs,c) do { wrmsr(msrs->counters[(c)].addr, -l); } while (0)
 #define CTR_OVERFLOWED(n) (!((n) & (1ULL<<31)))
 
 #define CTRL_READ(msr_content,msrs,c) do {rdmsrl(msrs->controls[(c)].addr, (msr_content));} while (0)
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 13/16] x86/msr: Use MSR_IMM when available
Date: Fri, 15 Aug 2025 21:41:14 +0100
Message-Id: <20250815204117.3312742-14-andrew.cooper3@citrix.com>
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Most MSR accesses have compile time constant indexes.  By using the immediate
form when available, the decoder can start issuing uops directly for the
relevant MSR, rather than having to issue uops to implement "switch (%ecx)".
Modern CPUs have tens of thousands of MSRs, so that's quite an if/else chain.

Create __{rdmsr,wrmsrns}_imm() helpers and use them from {rdmsr,wrmsrns}()
when the compiler can determine that the msr index is known at compile time.

At the instruction level, the combined ABI is awkward.  Explain our choices in
detail.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

The expression wrmsrns(MSR_STAR, rdmsr(MSR_STAR)) now yields:

  :
      b9 81 00 00 c0          mov    $0xc0000081,%ecx
      0f 32                   rdmsr
      48 c1 e2 20             shl    $0x20,%rdx
      48 09 d0                or     %rdx,%rax
      48 89 c2                mov    %rax,%rdx
      48 c1 ea 20             shr    $0x20,%rdx
      2e 0f 30                cs wrmsr
      e9 a3 84 e8 ff          jmp    ffff82d040204260 <__x86_return_thunk>

which is as good as we can manage.  The alternative form of this looks like:

  :
      b9 81 00 00 c0          mov    $0xc0000081,%ecx
      c4 e7 7b f6 c0 81 00    rdmsr  $0xc0000081,%rax
      00 c0
      2e c4 e7 7a f6 c0 81    cs wrmsrns %rax,$0xc0000081
      00 00 c0
      e9 xx xx xx xx          jmp    ffff82d040204260 <__x86_return_thunk>

Still TBD.  We ought to update the *_safe() forms too.  rdmsr_safe() is easier
because the potential #GP locations line up, but there need to be two variants
because of

v2:
 * Let the compiler do %ecx setup
 * Add RDMSR $imm too
---
 xen/arch/x86/include/asm/alternative.h      |  7 ++
 xen/arch/x86/include/asm/msr.h              | 86 ++++++++++++++++++++-
 xen/include/public/arch-x86/cpufeatureset.h |  1 +
 3 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/include/asm/alternative.h b/xen/arch/x86/include/asm/alternative.h
index 0482bbf7cbf1..fe87b15ec72c 100644
--- a/xen/arch/x86/include/asm/alternative.h
+++ b/xen/arch/x86/include/asm/alternative.h
@@ -151,6 +151,13 @@ extern void alternative_instructions(void);
         ALTERNATIVE(oldinstr, newinstr, feature)                        \
         :: input )
 
+#define alternative_input_2(oldinstr, newinstr1, feature1,              \
+                            newinstr2, feature2, input...)              \
+    asm_inline volatile (                                               \
+        ALTERNATIVE_2(oldinstr, newinstr1, feature1,                    \
+                      newinstr2, feature2)                              \
+        :: input )
+
 /* Like alternative_input, but with a single output argument */
 #define alternative_io(oldinstr, newinstr, feature, output, input...)   \
     asm_inline volatile (                                               \
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index 1bd27b989a4d..2ceff6cca8bb 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -29,10 +29,52 @@
  *  wrmsrl(MSR_FOO, val);
  */
 
-static inline uint64_t rdmsr(unsigned int msr)
+/*
+ * RDMSR with a compile-time constant index, when available.  Falls back to
+ * plain RDMSR.
+ */
+static always_inline uint64_t __rdmsr_imm(uint32_t msr)
+{
+    uint64_t val;
+
+    /*
+     * For best performance, RDMSR $msr, %r64 is recommended.  For
+     * compatibility, we need to fall back to plain RDMSR.
+     *
+     * The combined ABI is awkward, because RDMSR $imm produces an r64,
+     * whereas WRMSR{,NS} produces a split edx:eax pair.
+     *
+     * Always use RDMSR $imm, %rax, because it has the most in common with the
+     * legacy form.  When MSR_IMM isn't available, emit logic to fold %edx
+     * back into %rax.
+     *
+     * Let the compiler do %ecx setup.  This does mean there's a useless `mov
+     * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it means
+     * the compiler can de-duplicate the setup in the common case of reading
+     * and writing the same MSR.
+     */
+    alternative_io(
+        "rdmsr\n\t"
+        "shl $32, %%rdx\n\t"
+        "or %%rdx, %%rax\n\t",
+
+        /* RDMSR $msr, %rax */
+        ".byte 0xc4,0xe7,0x7b,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
+
+        "=a" (val),
+
+        [msr] "i" (msr), "c" (msr) : "rdx");
+
+    return val;
+}
+
+static always_inline uint64_t rdmsr(unsigned int msr)
 {
     unsigned long lo, hi;
 
+    if ( __builtin_constant_p(msr) )
+        return __rdmsr_imm(msr);
+
     asm volatile ( "rdmsr"
                    : "=a" (lo), "=d" (hi)
                    : "c" (msr) );
@@ -55,11 +97,51 @@ static inline void wrmsr(unsigned int msr, uint64_t val)
 }
 #define wrmsrl(msr, val) wrmsr(msr, val)
 
+/*
+ * Non-serialising WRMSR with a compile-time constant index, when available.
+ * Falls back to plain WRMSRNS, or to a serialising WRMSR.
+ */
+static always_inline void __wrmsrns_imm(uint32_t msr, uint64_t val)
+{
+    /*
+     * For best performance, WRMSRNS %r64, $msr is recommended.  For
+     * compatibility, we need to fall back to plain WRMSRNS, or to WRMSR.
+     *
+     * The combined ABI is awkward, because WRMSRNS $imm takes a single r64,
+     * whereas WRMSR{,NS} takes a split edx:eax pair.
+     *
+     * Always use WRMSRNS %rax, $imm, because it has the most in common with
+     * the legacy forms.  When MSR_IMM isn't available, emit setup logic for
+     * %edx.
+     *
+     * Let the compiler do %ecx setup.  This does mean there's a useless `mov
+     * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it means
+     * the compiler can de-duplicate the setup in the common case of reading
+     * and writing the same MSR.
+     */
+    alternative_input_2(
+        "mov %%rax, %%rdx\n\t"
+        "shr $32, %%rdx\n\t"
+        ".byte 0x2e; wrmsr",
+
+        /* CS WRMSRNS %rax, $msr */
+        ".byte 0x2e,0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
+
+        "mov %%rax, %%rdx\n\t"
+        "shr $32, %%rdx\n\t"
+        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
+
+        [msr] "i" (msr), "a" (val), "c" (msr) : "rdx");
+}
+
 /* Non-serialising WRMSR, when available.  Falls back to a serialising WRMSR. */
-static inline void wrmsrns(uint32_t msr, uint64_t val)
+static always_inline void wrmsrns(uint32_t msr, uint64_t val)
 {
     uint32_t lo = val, hi = val >> 32;
 
+    if ( __builtin_constant_p(msr) )
+        return __wrmsrns_imm(msr, val);
+
     /*
      * WRMSR is 2 bytes.  WRMSRNS is 3 bytes.  Pad WRMSR with a redundant CS
      * prefix to avoid a trailing NOP.
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index f7312e0b04e7..990b1d13f301 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -349,6 +349,7 @@ XEN_CPUFEATURE(MCDT_NO,            13*32+ 5) /*A  MCDT_NO */
 XEN_CPUFEATURE(UC_LOCK_DIS,        13*32+ 6) /*   UC-lock disable */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
+XEN_CPUFEATURE(MSR_IMM,            14*32+ 5) /*   {RD,WR}MSR $imm32 */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.edx, word 15 */
 XEN_CPUFEATURE(AVX_VNNI_INT8,      15*32+ 4) /*A  AVX-VNNI-INT8 Instructions */
-- 
2.39.5



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        Fri, 15 Aug 2025 13:41:29 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 11/16] x86/msr: Change rdmsr() to have normal API
Date: Fri, 15 Aug 2025 21:41:12 +0100
Message-Id: <20250815204117.3312742-12-andrew.cooper3@citrix.com>
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We want a consistent MSR API, and these want to be named rdmsr() and wrmsr(),
but not with their current APIs.  The current rdmsr() flavours writing to
their parameters by name makes code that reads like invalid C, and is
unergonomic to use in lots of cases.

Change the API, and update the callers all in one go.  Where appropriate,
update the write side to wrmsrns() as per the recommendation.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

I do have a more creative solution if this patch is considered to be too
large.  https://gitlab.com/xen-project/hardware/xen-staging/-/commit/e13cf25d06d08481e2c138daa1fd902cf36d757b
---
 xen/arch/x86/acpi/cpufreq/powernow.c | 12 ++++++-----
 xen/arch/x86/cpu/amd.c               |  6 +++---
 xen/arch/x86/cpu/common.c            | 20 +++++++++++--------
 xen/arch/x86/cpu/intel.c             | 30 ++++++++++++++--------------
 xen/arch/x86/genapic/x2apic.c        |  5 +----
 xen/arch/x86/hvm/vmx/vmcs.c          | 30 +++++++++++++++++++++-------
 xen/arch/x86/include/asm/msr.h       | 30 ++++++++++++++++++++++++----
 xen/arch/x86/include/asm/prot-key.h  |  6 +-----
 xen/arch/x86/tsx.c                   | 27 ++++++++++---------------
 9 files changed, 99 insertions(+), 67 deletions(-)

diff --git a/xen/arch/x86/acpi/cpufreq/powernow.c b/xen/arch/x86/acpi/cpufreq/powernow.c
index 12fca45b4551..71ac0b45261a 100644
--- a/xen/arch/x86/acpi/cpufreq/powernow.c
+++ b/xen/arch/x86/acpi/cpufreq/powernow.c
@@ -140,23 +140,25 @@ static int cf_check powernow_cpufreq_target(
 
 static void amd_fixup_frequency(struct xen_processor_px *px)
 {
-    u32 hi, lo, fid, did;
+    uint64_t val;
+    uint32_t fid, did;
     int index = px->control & 0x00000007;
     const struct cpuinfo_x86 *c = ¤t_cpu_data;
 
     if ((c->x86 != 0x10 || c->x86_model >= 10) && c->x86 != 0x11)
         return;
 
-    rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi);
+    val = rdmsr(MSR_PSTATE_DEF_BASE + index);
+
     /*
      * MSR C001_0064+:
      * Bit 63: PstateEn. Read-write. If set, the P-state is valid.
      */
-    if (!(hi & (1U << 31)))
+    if (!(val & (1UL << 63)))
         return;
 
-    fid = lo & 0x3f;
-    did = (lo >> 6) & 7;
+    fid = val & 0x3f;
+    did = (val >> 6) & 7;
     if (c->x86 == 0x10)
         px->core_frequency = (100 * (fid + 16)) >> did;
     else
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 567b992a9fe2..769413e96a3f 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -1369,9 +1369,9 @@ static void cf_check init_amd(struct cpuinfo_x86 *c)
 	}
 
 	if (cpu_has(c, X86_FEATURE_EFRO)) {
-		rdmsr(MSR_K8_HWCR, l, h);
-		l |= (1 << 27); /* Enable read-only APERF/MPERF bit */
-		wrmsr(MSR_K8_HWCR, l, h);
+		/* Enable read-only APERF/MPERF bit */
+		wrmsrns(MSR_K8_HWCR,
+			rdmsr(MSR_K8_HWCR) | (1 << 27));
 	}
 
 	/* Prevent TSC drift in non single-processor, single-core platforms. */
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 530b9eb39abc..9c6b8c291d6e 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -329,6 +329,7 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 void __init early_cpu_init(bool verbose)
 {
 	struct cpuinfo_x86 *c = &boot_cpu_data;
+	uint64_t val;
 	u32 eax, ebx, ecx, edx;
 
 	c->x86_cache_alignment = 32;
@@ -412,10 +413,11 @@ void __init early_cpu_init(bool verbose)
 			    &c->x86_capability[FEATURESET_7c0],
 			    &c->x86_capability[FEATURESET_7d0]);
 
-		if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability))
-			rdmsr(MSR_ARCH_CAPABILITIES,
-			      c->x86_capability[FEATURESET_m10Al],
-			      c->x86_capability[FEATURESET_m10Ah]);
+		if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) {
+			val = rdmsr(MSR_ARCH_CAPABILITIES);
+			c->x86_capability[FEATURESET_m10Al] = val;
+			c->x86_capability[FEATURESET_m10Al] = val >> 32;
+		}
 
 		if (max_subleaf >= 1)
 			cpuid_count(7, 1, &eax, &ebx, &ecx,
@@ -467,6 +469,7 @@ void reset_cpuinfo(struct cpuinfo_x86 *c, bool keep_basic)
 
 static void generic_identify(struct cpuinfo_x86 *c)
 {
+	uint64_t val;
 	u32 eax, ebx, ecx, edx, tmp;
 
 	/* Get vendor name */
@@ -559,10 +562,11 @@ static void generic_identify(struct cpuinfo_x86 *c)
 			    &c->x86_capability[FEATURESET_Da1],
 			    &tmp, &tmp, &tmp);
 
-	if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability))
-		rdmsr(MSR_ARCH_CAPABILITIES,
-		      c->x86_capability[FEATURESET_m10Al],
-		      c->x86_capability[FEATURESET_m10Ah]);
+	if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) {
+		val = rdmsr(MSR_ARCH_CAPABILITIES);
+		c->x86_capability[FEATURESET_m10Al] = val;
+		c->x86_capability[FEATURESET_m10Al] = val >> 32;
+	}
 }
 
 /*
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index ecca11f04db8..4f5bb022deea 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -23,17 +23,17 @@ static uint32_t __ro_after_init mcu_opt_ctrl_val;
 
 void update_mcu_opt_ctrl(void)
 {
-    uint32_t mask = mcu_opt_ctrl_mask, lo, hi;
+    uint32_t mask = mcu_opt_ctrl_mask, val;
 
     if ( !mask )
         return;
 
-    rdmsr(MSR_MCU_OPT_CTRL, lo, hi);
+    val = rdmsr(MSR_MCU_OPT_CTRL);
 
-    lo &= ~mask;
-    lo |= mcu_opt_ctrl_val;
+    val &= ~mask;
+    val |= mcu_opt_ctrl_val;
 
-    wrmsr(MSR_MCU_OPT_CTRL, lo, hi);
+    wrmsrns(MSR_MCU_OPT_CTRL, val);
 }
 
 void __init set_in_mcu_opt_ctrl(uint32_t mask, uint32_t val)
@@ -51,17 +51,17 @@ static uint32_t __ro_after_init pb_opt_ctrl_val;
 
 void update_pb_opt_ctrl(void)
 {
-    uint32_t mask = pb_opt_ctrl_mask, lo, hi;
+    uint32_t mask = pb_opt_ctrl_mask, val;
 
     if ( !mask )
         return;
 
-    rdmsr(MSR_PB_OPT_CTRL, lo, hi);
+    val = rdmsr(MSR_PB_OPT_CTRL);
 
-    lo &= ~mask;
-    lo |= pb_opt_ctrl_val;
+    val &= ~mask;
+    val |= pb_opt_ctrl_val;
 
-    wrmsr(MSR_PB_OPT_CTRL, lo, hi);
+    wrmsrns(MSR_PB_OPT_CTRL, val);
 }
 
 void __init set_in_pb_opt_ctrl(uint32_t mask, uint32_t val)
@@ -456,15 +456,15 @@ static void __init probe_mwait_errata(void)
  */
 static void Intel_errata_workarounds(struct cpuinfo_x86 *c)
 {
-	unsigned long lo, hi;
+	uint64_t val;
 
 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
-		rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
-		if ((lo & (1<<9)) == 0) {
+		val = rdmsr(MSR_IA32_MISC_ENABLE);
+		if ((val & (1 << 9)) == 0) {
 			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
-			lo |= (1<<9);	/* Disable hw prefetching */
-			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
+			val |= (1 << 9); /* Disable hw prefetching */
+			wrmsrns(MSR_IA32_MISC_ENABLE, val);
 		}
 	}
 
diff --git a/xen/arch/x86/genapic/x2apic.c b/xen/arch/x86/genapic/x2apic.c
index 1d55eb6b8a41..58157c217ee8 100644
--- a/xen/arch/x86/genapic/x2apic.c
+++ b/xen/arch/x86/genapic/x2apic.c
@@ -268,14 +268,11 @@ const struct genapic *__init apic_x2apic_probe(void)
 
 void __init check_x2apic_preenabled(void)
 {
-    u32 lo, hi;
-
     if ( !cpu_has_x2apic )
         return;
 
     /* Check whether x2apic mode was already enabled by the BIOS. */
-    rdmsr(MSR_APIC_BASE, lo, hi);
-    if ( lo & APIC_BASE_EXTD )
+    if ( rdmsr(MSR_APIC_BASE) & APIC_BASE_EXTD )
     {
         printk("x2APIC mode is already enabled by BIOS.\n");
         x2apic_enabled = 1;
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index ab8b1c87ec0f..1fa61a944b23 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -207,9 +207,13 @@ static void __init vmx_display_features(void)
 static u32 adjust_vmx_controls(
     const char *name, u32 ctl_min, u32 ctl_opt, u32 msr, bool *mismatch)
 {
+    uint64_t val;
     u32 vmx_msr_low, vmx_msr_high, ctl = ctl_min | ctl_opt;
 
-    rdmsr(msr, vmx_msr_low, vmx_msr_high);
+    val = rdmsr(msr);
+
+    vmx_msr_low = val;
+    vmx_msr_high = val >> 32;
 
     ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
     ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
@@ -258,10 +262,13 @@ static int vmx_init_vmcs_config(bool bsp)
 {
     u32 vmx_basic_msr_low, vmx_basic_msr_high, min, opt;
     struct vmx_caps caps = {};
-    u64 _vmx_misc_cap = 0;
+    uint64_t _vmx_misc_cap = 0, val;
     bool mismatch = false;
 
-    rdmsr(MSR_IA32_VMX_BASIC, vmx_basic_msr_low, vmx_basic_msr_high);
+    val = rdmsr(MSR_IA32_VMX_BASIC);
+
+    vmx_basic_msr_low = val;
+    vmx_basic_msr_high = val >> 32;
 
     min = (PIN_BASED_EXT_INTR_MASK |
            PIN_BASED_NMI_EXITING);
@@ -366,7 +373,10 @@ static int vmx_init_vmcs_config(bool bsp)
     if ( caps.secondary_exec_control & (SECONDARY_EXEC_ENABLE_EPT |
                                         SECONDARY_EXEC_ENABLE_VPID) )
     {
-        rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, caps.ept, caps.vpid);
+        val = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
+
+        caps.ept = val;
+        caps.vpid = val >> 32;
 
         if ( !opt_ept_ad )
             caps.ept &= ~VMX_EPT_AD_BIT;
@@ -408,9 +418,15 @@ static int vmx_init_vmcs_config(bool bsp)
          * We check VMX_BASIC_MSR[55] to correctly handle default controls.
          */
         uint32_t must_be_one, must_be_zero, msr = MSR_IA32_VMX_PROCBASED_CTLS;
+
         if ( vmx_basic_msr_high & (VMX_BASIC_DEFAULT1_ZERO >> 32) )
             msr = MSR_IA32_VMX_TRUE_PROCBASED_CTLS;
-        rdmsr(msr, must_be_one, must_be_zero);
+
+        val = rdmsr(msr);
+
+        must_be_one = val;
+        must_be_zero = val >> 32;
+
         if ( must_be_one & (CPU_BASED_INVLPG_EXITING |
                             CPU_BASED_CR3_LOAD_EXITING |
                             CPU_BASED_CR3_STORE_EXITING) )
@@ -699,7 +715,7 @@ void cf_check vmx_cpu_dead(unsigned int cpu)
 
 static int _vmx_cpu_up(bool bsp)
 {
-    u32 eax, edx;
+    u32 eax;
     int rc, bios_locked, cpu = smp_processor_id();
     u64 cr0, vmx_cr0_fixed0, vmx_cr0_fixed1;
 
@@ -719,7 +735,7 @@ static int _vmx_cpu_up(bool bsp)
         return -EINVAL;
     }
 
-    rdmsr(MSR_IA32_FEATURE_CONTROL, eax, edx);
+    eax = rdmsr(MSR_IA32_FEATURE_CONTROL);
 
     bios_locked = !!(eax & IA32_FEATURE_CONTROL_LOCK);
     if ( bios_locked )
diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
index c0d66562956d..f1b2bd5adc9f 100644
--- a/xen/arch/x86/include/asm/msr.h
+++ b/xen/arch/x86/include/asm/msr.h
@@ -9,10 +9,32 @@
 #include 
 #include 
 
-#define rdmsr(msr,val1,val2) \
-     __asm__ __volatile__("rdmsr" \
-			  : "=a" (val1), "=d" (val2) \
-			  : "c" (msr))
+/*
+ * MSR APIs.  Most logic is expected to use:
+ *
+ *   uint64_t foo = rdmsr(MSR_BAR);
+ *   wrmsrns(MSR_BAR, foo);
+ *
+ * In addition, *_safe() wrappers exist to cope gracefully with a #GP.
+ *
+ *
+ * All legacy forms are to be phased out:
+ *
+ *  rdmsrl(MSR_FOO, val);
+ *  wrmsr(MSR_FOO, lo, hi);
+ *  wrmsrl(MSR_FOO, val);
+ */
+
+static inline uint64_t rdmsr(unsigned int msr)
+{
+    unsigned long lo, hi;
+
+    asm volatile ( "rdmsr"
+                   : "=a" (lo), "=d" (hi)
+                   : "c" (msr) );
+
+    return (hi << 32) | lo;
+}
 
 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
        __asm__ __volatile__("rdmsr" \
diff --git a/xen/arch/x86/include/asm/prot-key.h b/xen/arch/x86/include/asm/prot-key.h
index 3e9c2eaef415..8fb15b5c32e9 100644
--- a/xen/arch/x86/include/asm/prot-key.h
+++ b/xen/arch/x86/include/asm/prot-key.h
@@ -52,11 +52,7 @@ DECLARE_PER_CPU(uint32_t, pkrs);
 
 static inline uint32_t rdpkrs(void)
 {
-    uint32_t pkrs, tmp;
-
-    rdmsr(MSR_PKRS, pkrs, tmp);
-
-    return pkrs;
+    return rdmsr(MSR_PKRS);
 }
 
 static inline uint32_t rdpkrs_and_cache(void)
diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c
index 2a0c7c08a2ba..fe9f0ab4f792 100644
--- a/xen/arch/x86/tsx.c
+++ b/xen/arch/x86/tsx.c
@@ -42,6 +42,8 @@ void tsx_init(void)
 {
     static bool __read_mostly once;
 
+    uint64_t val;
+
     /*
      * This function is first called between microcode being loaded, and
      * CPUID being scanned generally. early_cpu_init() has already prepared
@@ -62,8 +64,6 @@ void tsx_init(void)
              * On a TAA-vulnerable or later part with at least the May 2020
              * microcode mitigating SRBDS.
              */
-            uint64_t val;
-
             rdmsrl(MSR_MCU_OPT_CTRL, val);
 
             /*
@@ -118,8 +118,6 @@ void tsx_init(void)
 
         if ( cpu_has_tsx_force_abort )
         {
-            uint64_t val;
-
             /*
              * On an early TSX-enabled Skylake part subject to the memory
              * ordering erratum, with at least the March 2019 microcode.
@@ -250,18 +248,17 @@ void tsx_init(void)
          *    controlled, we have or will set MSR_MCU_OPT_CTRL.RTM_ALLOW to
          *    let TSX_CTRL.RTM_DISABLE be usable.
          */
-        uint32_t hi, lo;
 
-        rdmsr(MSR_TSX_CTRL, lo, hi);
+        val = rdmsr(MSR_TSX_CTRL);
 
         /* Check bottom bit only.  Higher bits are various sentinels. */
         rtm_disabled = !(opt_tsx & 1);
 
-        lo &= ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR);
+        val &= ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR);
         if ( rtm_disabled )
-            lo |= TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR;
+            val |= TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR;
 
-        wrmsr(MSR_TSX_CTRL, lo, hi);
+        wrmsrns(MSR_TSX_CTRL, val);
     }
     else if ( cpu_has_tsx_force_abort )
     {
@@ -269,14 +266,12 @@ void tsx_init(void)
          * On an early TSX-enable Skylake part subject to the memory ordering
          * erratum, with at least the March 2019 microcode.
          */
-        uint32_t hi, lo;
-
-        rdmsr(MSR_TSX_FORCE_ABORT, lo, hi);
+        val = rdmsr(MSR_TSX_FORCE_ABORT);
 
         /* Check bottom bit only.  Higher bits are various sentinels. */
         rtm_disabled = !(opt_tsx & 1);
 
-        lo &= ~(TSX_FORCE_ABORT_RTM | TSX_CPUID_CLEAR | TSX_ENABLE_RTM);
+        val &= ~(TSX_FORCE_ABORT_RTM | TSX_CPUID_CLEAR | TSX_ENABLE_RTM);
 
         if ( cpu_has_rtm_always_abort )
         {
@@ -291,7 +286,7 @@ void tsx_init(void)
              *  - TSX_FORCE_ABORT.ENABLE_RTM may be used to opt in to
              *    re-enabling RTM, at the users own risk.
              */
-            lo |= rtm_disabled ? TSX_CPUID_CLEAR : TSX_ENABLE_RTM;
+            val |= rtm_disabled ? TSX_CPUID_CLEAR : TSX_ENABLE_RTM;
         }
         else
         {
@@ -304,10 +299,10 @@ void tsx_init(void)
              *    setting TSX_FORCE_ABORT.FORCE_ABORT_RTM.
              */
             if ( rtm_disabled )
-                lo |= TSX_FORCE_ABORT_RTM;
+                val |= TSX_FORCE_ABORT_RTM;
         }
 
-        wrmsr(MSR_TSX_FORCE_ABORT, lo, hi);
+        wrmsrns(MSR_TSX_FORCE_ABORT, val);
     }
     else if ( opt_tsx >= 0 )
         printk_once(XENLOG_WARNING
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 14/16] x86/fsgsbase: Split out __{rd,wr}gskern() helpers
Date: Fri, 15 Aug 2025 21:41:15 +0100
Message-Id: <20250815204117.3312742-15-andrew.cooper3@citrix.com>
X-Mailer: git-send-email 2.39.5
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Right now they're inline in {read,write}_gs_shadow(), but we're going to need
to use these elsewhere to support FRED.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/include/asm/fsgsbase.h | 36 ++++++++++++++++++-----------
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/xen/arch/x86/include/asm/fsgsbase.h b/xen/arch/x86/include/asm/fsgsbase.h
index 03e6a85d31ce..90d116f3bb54 100644
--- a/xen/arch/x86/include/asm/fsgsbase.h
+++ b/xen/arch/x86/include/asm/fsgsbase.h
@@ -32,6 +32,17 @@ static inline unsigned long __rdgsbase(void)
     return base;
 }
 
+static inline unsigned long __rdgskern(void)
+{
+    unsigned long base;
+
+    asm_inline volatile ( "swapgs\n\t"
+                          "rdgsbase %0\n\t"
+                          "swapgs" : "=r" (base) );
+
+    return base;
+}
+
 static inline void __wrfsbase(unsigned long base)
 {
     asm volatile ( "wrfsbase %0" :: "r" (base) );
@@ -42,6 +53,14 @@ static inline void __wrgsbase(unsigned long base)
     asm volatile ( "wrgsbase %0" :: "r" (base) );
 }
 
+static inline void __wrgskern(unsigned long base)
+{
+    asm_inline volatile ( "swapgs\n\t"
+                          "wrgsbase %0\n\t"
+                          "swapgs"
+                          :: "r" (base) );
+}
+
 static inline unsigned long read_fs_base(void)
 {
     unsigned long base;
@@ -71,13 +90,9 @@ static inline unsigned long read_gs_shadow(void)
     unsigned long base;
 
     if ( read_cr4() & X86_CR4_FSGSBASE )
-    {
-        asm volatile ( "swapgs" );
-        base = __rdgsbase();
-        asm volatile ( "swapgs" );
-    }
-    else
-        rdmsrl(MSR_SHADOW_GS_BASE, base);
+        return __rdgskern();
+
+    rdmsrl(MSR_SHADOW_GS_BASE, base);
 
     return base;
 }
@@ -101,12 +116,7 @@ static inline void write_gs_base(unsigned long base)
 static inline void write_gs_shadow(unsigned long base)
 {
     if ( read_cr4() & X86_CR4_FSGSBASE )
-    {
-        asm volatile ( "swapgs\n\t"
-                       "wrgsbase %0\n\t"
-                       "swapgs"
-                       :: "r" (base) );
-    }
+        __wrgskern(base);
     else
         wrmsrl(MSR_SHADOW_GS_BASE, base);
 }
-- 
2.39.5



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        Fri, 15 Aug 2025 13:41:32 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 15/16] x86/fsgsbase: Update fs/gs helpers to use wrmsrns()
Date: Fri, 15 Aug 2025 21:41:16 +0100
Message-Id: <20250815204117.3312742-16-andrew.cooper3@citrix.com>
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... and rdmsr() while here.

Most of these accesses are in fastpaths and do not need serialising behaviour,
but the write side is serialising on all Intel hardware as well as older AMD
hardware.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/domain.c               | 10 +++++-----
 xen/arch/x86/hvm/vmx/vmx.c          |  4 ++--
 xen/arch/x86/include/asm/fsgsbase.h | 30 +++++++++--------------------
 3 files changed, 16 insertions(+), 28 deletions(-)

diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 3015aac4adbc..2a9bb87729c8 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1824,9 +1824,9 @@ static void load_segments(struct vcpu *n)
         }
         else
         {
-            wrmsrl(MSR_FS_BASE, n->arch.pv.fs_base);
-            wrmsrl(MSR_GS_BASE, gsb);
-            wrmsrl(MSR_SHADOW_GS_BASE, gss);
+            wrmsrns(MSR_FS_BASE, n->arch.pv.fs_base);
+            wrmsrns(MSR_GS_BASE, gsb);
+            wrmsrns(MSR_SHADOW_GS_BASE, gss);
         }
     }
 
@@ -1951,8 +1951,8 @@ static void save_segments(struct vcpu *v)
         }
         else
         {
-            rdmsrl(MSR_FS_BASE, fs_base);
-            rdmsrl(MSR_GS_BASE, gs_base);
+            fs_base = rdmsr(MSR_FS_BASE);
+            gs_base = rdmsr(MSR_GS_BASE);
         }
 
         v->arch.pv.fs_base = fs_base;
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index f97a7746531a..9ba140c4811c 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2733,8 +2733,8 @@ static uint64_t cf_check vmx_get_reg(struct vcpu *v, unsigned int reg)
     case MSR_SHADOW_GS_BASE:
         if ( v != curr )
             return v->arch.hvm.vmx.shadow_gs;
-        rdmsrl(MSR_SHADOW_GS_BASE, val);
-        return val;
+        else
+            return rdmsr(MSR_SHADOW_GS_BASE);
     }
 
     /* Logic which maybe requires remote VMCS acquisition. */
diff --git a/xen/arch/x86/include/asm/fsgsbase.h b/xen/arch/x86/include/asm/fsgsbase.h
index 90d116f3bb54..7a0b623cca8f 100644
--- a/xen/arch/x86/include/asm/fsgsbase.h
+++ b/xen/arch/x86/include/asm/fsgsbase.h
@@ -63,38 +63,26 @@ static inline void __wrgskern(unsigned long base)
 
 static inline unsigned long read_fs_base(void)
 {
-    unsigned long base;
-
     if ( read_cr4() & X86_CR4_FSGSBASE )
         return __rdfsbase();
-
-    rdmsrl(MSR_FS_BASE, base);
-
-    return base;
+    else
+        return rdmsr(MSR_FS_BASE);
 }
 
 static inline unsigned long read_gs_base(void)
 {
-    unsigned long base;
-
     if ( read_cr4() & X86_CR4_FSGSBASE )
         return __rdgsbase();
-
-    rdmsrl(MSR_GS_BASE, base);
-
-    return base;
+    else
+        return rdmsr(MSR_GS_BASE);
 }
 
 static inline unsigned long read_gs_shadow(void)
 {
-    unsigned long base;
-
     if ( read_cr4() & X86_CR4_FSGSBASE )
         return __rdgskern();
-
-    rdmsrl(MSR_SHADOW_GS_BASE, base);
-
-    return base;
+    else
+        return rdmsr(MSR_SHADOW_GS_BASE);
 }
 
 static inline void write_fs_base(unsigned long base)
@@ -102,7 +90,7 @@ static inline void write_fs_base(unsigned long base)
     if ( read_cr4() & X86_CR4_FSGSBASE )
         __wrfsbase(base);
     else
-        wrmsrl(MSR_FS_BASE, base);
+        wrmsrns(MSR_FS_BASE, base);
 }
 
 static inline void write_gs_base(unsigned long base)
@@ -110,7 +98,7 @@ static inline void write_gs_base(unsigned long base)
     if ( read_cr4() & X86_CR4_FSGSBASE )
         __wrgsbase(base);
     else
-        wrmsrl(MSR_GS_BASE, base);
+        wrmsrns(MSR_GS_BASE, base);
 }
 
 static inline void write_gs_shadow(unsigned long base)
@@ -118,7 +106,7 @@ static inline void write_gs_shadow(unsigned long base)
     if ( read_cr4() & X86_CR4_FSGSBASE )
         __wrgskern(base);
     else
-        wrmsrl(MSR_SHADOW_GS_BASE, base);
+        wrmsrns(MSR_SHADOW_GS_BASE, base);
 }
 
 #endif /* X86_FSGSBASE_H */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 16/16] x86/fsgsbase: Improve code generation in read_registers()
Date: Fri, 15 Aug 2025 21:41:17 +0100
Message-Id: <20250815204117.3312742-17-andrew.cooper3@citrix.com>
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It turns out that using the higher level helpers adjacent like this leads to
terrible code generation.  Due to -fno-strict-alising, the store into state->
invalidates the read_cr4() address calculation (which is really cpu_info->cr4
under the hood), meaning that it can't be hoisted.

As a result we get "locate the top of stack block, get cr4, and see if
FSGSBASE is set" repeated 3 times, and an unreasoanble number of basic blocks.

Hoist the calculation manually, which results in two basic blocks.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

Side-by-side disassembly: https://termbin.com/9xfq
---
 xen/arch/x86/traps.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 0c5393cb2166..8c261d219c07 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -118,9 +118,18 @@ static void read_registers(struct extra_state *state)
     state->cr3 = read_cr3();
     state->cr4 = read_cr4();
 
-    state->fsb = read_fs_base();
-    state->gsb = read_gs_base();
-    state->gss = read_gs_shadow();
+    if ( state->cr4 & X86_CR4_FSGSBASE )
+    {
+        state->fsb = __rdfsbase();
+        state->gsb = __rdgsbase();
+        state->gss = __rdgskern();
+    }
+    else
+    {
+        state->fsb = rdmsr(MSR_FS_BASE);
+        state->gsb = rdmsr(MSR_GS_BASE);
+        state->gss = rdmsr(MSR_SHADOW_GS_BASE);
+    }
 
     asm ( "mov %%ds, %0" : "=m" (state->ds) );
     asm ( "mov %%es, %0" : "=m" (state->es) );
-- 
2.39.5



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Juergen Gross ,
	Julien Grall , Anthony PERARD 
Subject: [PATCH v6 2/8] tools/xenstored: Add get_domain_evtchn() to find evtchn
Date: Fri, 15 Aug 2025 17:35:50 -0400
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Add helpers to lookup the event channel for a domid.  This hides some
of the differences between dom0 and stubdom xenstored.  Each version
defines its own.

It highlights the different meanings between get_xenbus_evtchn() in a
stubdom, where it looks up dom0's event channel, and dom0, where it
looks up the local event channel.

get_domain_evtchn() replaces get_xenbus_evtchn(), and
get_xenbus_evtchn() is removed from minios.c as it is inlined in the new
function.

The default return 0 will be fine as any other auto-introduced domain
will needs the event channel populated in the grant.

Signed-off-by: Jason Andryuk 
Reviewed-by: Juergen Gross 
---
v6:
R-b: Juergen

v5:
Split get_domain_evtchn() in minios.c and posix.c versions
s/dom0/stubdom/
---
 tools/xenstored/core.h   |  2 +-
 tools/xenstored/domain.c | 10 +++++++---
 tools/xenstored/minios.c | 19 ++++++++++++++++---
 tools/xenstored/posix.c  | 16 +++++++++++++++-
 4 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/tools/xenstored/core.h b/tools/xenstored/core.h
index 5071f1dedd..cef3c71eb0 100644
--- a/tools/xenstored/core.h
+++ b/tools/xenstored/core.h
@@ -397,7 +397,7 @@ static inline bool domain_is_unprivileged(const struct connection *conn)
 extern xenevtchn_handle *xce_handle; /* in domain.c */
 
 /* Return the event channel used by xenbus. */
-evtchn_port_t get_xenbus_evtchn(void);
+evtchn_port_t get_domain_evtchn(unsigned int domid);
 void early_init(bool live_update, bool dofork, const char *pidfile);
 void late_init(bool live_update);
 
diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c
index 60d398682f..0866e04aa9 100644
--- a/tools/xenstored/domain.c
+++ b/tools/xenstored/domain.c
@@ -1330,7 +1330,7 @@ void dom0_init(void)
 	evtchn_port_t port;
 	struct domain *dom0;
 
-	port = get_xenbus_evtchn();
+	port = get_domain_evtchn(xenbus_master_domid());
 	if (port == -1)
 		barf_perror("Failed to initialize dom0 port");
 
@@ -1345,13 +1345,17 @@ void stubdom_init(bool live_update)
 {
 #ifdef __MINIOS__
 	struct domain *stubdom;
+	evtchn_port_t port;
 
 	if (stub_domid < 0)
 		return;
 
 	if (!live_update) {
-		stubdom = introduce_domain(NULL, stub_domid, xenbus_evtchn,
-					   false);
+		port = get_domain_evtchn(stub_domid);
+		if (port == -1)
+			barf_perror("Failed to initialize stubdom port");
+
+		stubdom = introduce_domain(NULL, stub_domid, port, false);
 		if (!stubdom)
 			barf_perror("Failed to initialize stubdom");
 
diff --git a/tools/xenstored/minios.c b/tools/xenstored/minios.c
index f04423fe09..60d921cf01 100644
--- a/tools/xenstored/minios.c
+++ b/tools/xenstored/minios.c
@@ -41,9 +41,22 @@ struct connection *add_socket_connection(int fd)
 	barf("socket based connection without sockets");
 }
 
-evtchn_port_t get_xenbus_evtchn(void)
-{
-	return dom0_event;
+/*
+ * minios stubdom looks up dom0's event channel from the command line
+ * (--event).  The stubdom's own event channel is returned directly.
+ *
+ * Any other existing domains from dom0less/Hyperlaunch will have
+ * the event channel in the xenstore page, so lookup here isn't necessary.
+ * --event would not be set, so it would default to 0.
+ */
+evtchn_port_t get_domain_evtchn(unsigned int domid)
+{
+	if (domid == stub_domid)
+		return xenbus_evtchn;
+	else if (domid == priv_domid)
+		return dom0_event;
+
+	return 0;
 }
 
 void *xenbus_map(void)
diff --git a/tools/xenstored/posix.c b/tools/xenstored/posix.c
index 97561701ae..4a97f53dc0 100644
--- a/tools/xenstored/posix.c
+++ b/tools/xenstored/posix.c
@@ -139,7 +139,7 @@ void unmap_xenbus(void *interface)
 	munmap(interface, getpagesize());
 }
 
-evtchn_port_t get_xenbus_evtchn(void)
+static evtchn_port_t get_xenbus_evtchn(void)
 {
 	int fd;
 	int rc;
@@ -166,6 +166,20 @@ evtchn_port_t get_xenbus_evtchn(void)
 	return port;
 }
 
+/*
+ * dom0 xenstored uses get_xenbus_evtchn() to lookup with XENSTORED_PORT_DEV.
+ *
+ * Any other existing domains from dom0less/Hyperlaunch will have
+ * the event channel in the xenstore page, so lookup here isn't necessary.
+ */
+evtchn_port_t get_domain_evtchn(unsigned int domid)
+{
+	if (domid == xenbus_master_domid())
+		return get_xenbus_evtchn();
+
+	return 0;
+}
+
 void *xenbus_map(void)
 {
 	int fd;
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Juergen Gross ,
	Julien Grall , Anthony PERARD 
Subject: [PATCH v6 1/8] tools/xenstored: Read event channel from xenstored page
Date: Fri, 15 Aug 2025 17:35:49 -0400
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Make introduce_domain() use an event channel from the the xenstore page.
It is only used if non-zero.  Otherwise the passed in event channel port
is used.

The is useful for a xenstored stubdom to configure domains autonomously.

Signed-off-by: Jason Andryuk 
Reviewed-by: Juergen Gross 
---
v4:
R-b Juergen

v2:
Remove iface_port variable.
---
 tools/xenstored/domain.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c
index 34ebeaac9b..60d398682f 100644
--- a/tools/xenstored/domain.c
+++ b/tools/xenstored/domain.c
@@ -1036,6 +1036,10 @@ static struct domain *introduce_domain(const void *ctx,
 		interface = map_interface(domid);
 		if (!interface && !restore)
 			return NULL;
+
+		if (interface->evtchn_port)
+			port = interface->evtchn_port;
+
 		if (new_domain(domain, port, restore)) {
 			rc = errno;
 			if (interface)
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Juergen Gross ,
	Julien Grall , Anthony PERARD 
Subject: [PATCH v6 0/8] xenstored patches from split hardware control
Date: Fri, 15 Aug 2025 17:35:48 -0400
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This is a subset of patches focusing on xenstored changes from my split
hardware control domain series.

"tools/xenstored: Check NULL domain in domain_chk_quota()" is new.

The xenstore changes are reviewed aside from the new commit.

stubdom was tested in gitlab-ci - xl list shows Domain-0 and Xenstore.

"tools/xenstored: Use priv_domid for manual nodes and permission" is an
interesting result of looking to rename some internal variables to
better align their purpose.

Any review or guidance on the approach is appreciated.

Jason Andryuk (8):
  tools/xenstored: Read event channel from xenstored page
  tools/xenstored: Add get_domain_evtchn() to find evtchn
  tools/xenstored: Auto-introduce domains
  tools/xenstored: Check NULL domain in domain_chk_quota()
  tools/xenstored: Use priv_domid for manual nodes and permission
  tools/xenstored: Rename dom0_domid to store_domid
  tools/xenstored: Remove stubdom special casing
  tools/xenstored: Remove hardcoded implicit path

 tools/xenstored/core.c   |  17 +++---
 tools/xenstored/core.h   |   8 +--
 tools/xenstored/domain.c | 128 +++++++++++++++++++++++++++++----------
 tools/xenstored/domain.h |   2 +-
 tools/xenstored/minios.c |  21 +++++--
 tools/xenstored/posix.c  |  18 +++++-
 6 files changed, 141 insertions(+), 53 deletions(-)

-- 
2.50.1



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From: Jason Andryuk 
To: 
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	Julien Grall , Anthony PERARD 
Subject: [PATCH v6 3/8] tools/xenstored: Auto-introduce domains
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Replace dom0_init() with init_domains() which uses libxenmanage to
iterate through all existing domains, storing them in a list.  The xenstore
domain is introduced first, and then all the other domains are
introduced.  The xenstore domain needs to be introduced first to setup
structures needed for firing watches.

dom0_domid is updated with the xenstore domain, since it really
indicates the local domain.

priv_domid is set to the control domain.  This makes it limited to a
single domain.

These features let xenstore automatically connect any existing domains,
which means it doesn't need to be done manually from init-dom0less.

For a legacy dom0, the result should be unchanged.

For a late xenstore stubdom it should also be the same, but priv_domid
would be set automatically to control domain (which default to 0
normally).

Always signal the event channel for initial domains.  This gets dom0 (a
local xenstored domain) to connect.

Also always write XENSTORE_CONNECTED since we know we are connected at
this point.

To support ARM dom0less domains with xen,enhanced = "no-xenstore" a
failed introduce_domain() becomes non-fatal.  Normally,
HVM_PARAM_STORE_EVTCHN is used to identify .

priv_domid from the command line is used, or the first control domain is
used.

dom0_domid will set to the last xenstore found.  This will handle dom0
or dom0less, where only 1 xenstore domain can exist, or stubdom, where
dom0 and dom1 exist, and we want to take the stubdom.

Signed-off-by: Jason Andryuk 
Reviewed-by: Juergen Gross 
---
v6:
R-b: Juergen

v5:
Add init_domain() helper and call for dom0_domid first outside loop.
Fix HVM_PARAM_STORE_EVTCHN typo
Only take first priv_domid and respect command line setting
Take last dom0_domid
Set priv_domid & dom0_domid default values - bail if both unset
Use talloc_realloc
Remove domain_conn_reset()
---
 tools/xenstored/core.c   |   6 +--
 tools/xenstored/domain.c | 100 ++++++++++++++++++++++++++++++---------
 tools/xenstored/domain.h |   2 +-
 3 files changed, 81 insertions(+), 27 deletions(-)

diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c
index 5377d72f54..d447e1167e 100644
--- a/tools/xenstored/core.c
+++ b/tools/xenstored/core.c
@@ -2567,9 +2567,9 @@ static struct option options[] = {
 #endif
 	{ NULL, 0, NULL, 0 } };
 
-int dom0_domid = 0;
+int dom0_domid = DOMID_INVALID;
 int dom0_event = 0;
-int priv_domid = 0;
+int priv_domid = DOMID_INVALID;
 domid_t stub_domid = DOMID_INVALID;
 
 static unsigned int get_optval_uint(const char *arg)
@@ -2760,7 +2760,7 @@ int main(int argc, char *argv[])
 	/* Listen to hypervisor. */
 	if (!live_update) {
 		domain_init(-1);
-		dom0_init();
+		init_domains();
 	}
 
 	/* redirect to /dev/null now we're ready to accept connections */
diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c
index 0866e04aa9..051e3fd164 100644
--- a/tools/xenstored/domain.c
+++ b/tools/xenstored/domain.c
@@ -1325,43 +1325,97 @@ const char *get_implicit_path(const struct connection *conn)
 	return conn->domain->path;
 }
 
-void dom0_init(void)
+static bool init_domain(unsigned int domid)
 {
 	evtchn_port_t port;
-	struct domain *dom0;
+	struct domain *domain;
 
-	port = get_domain_evtchn(xenbus_master_domid());
+	port = get_domain_evtchn(domid);
 	if (port == -1)
-		barf_perror("Failed to initialize dom0 port");
+		barf_perror("Failed to initialize dom%u port", domid);
 
-	dom0 = introduce_domain(NULL, xenbus_master_domid(), port, false);
-	if (!dom0)
-		barf_perror("Failed to initialize dom0");
+	domain = introduce_domain(NULL, domid, port, false);
+	if (!domain) {
+		xprintf("Could not initialize dom%u", domid);
+		return false;
+	}
 
-	xenevtchn_notify(xce_handle, dom0->port);
-}
+	if (domain->interface)
+		domain->interface->connection = XENSTORE_CONNECTED;
 
-void stubdom_init(bool live_update)
+	xenevtchn_notify(xce_handle, domain->port);
+
+	return true;
+}
+void init_domains(void)
 {
-#ifdef __MINIOS__
-	struct domain *stubdom;
-	evtchn_port_t port;
+	unsigned int *domids = NULL;
+	unsigned int nr_domids = 0;
+	unsigned int domid;
+	unsigned int state;
+	unsigned int caps;
+	uint64_t unique_id;
+	int introduce_count = 0;
 
-	if (stub_domid < 0)
-		return;
+	while (!xenmanage_poll_changed_domain(xm_handle, &domid, &state, &caps,
+					      &unique_id)) {
+		nr_domids++;
+		domids = talloc_realloc(NULL, domids, unsigned int, nr_domids);
+		if (!domids)
+			barf_perror("Failed to reallocate domids");
+
+		domids[nr_domids - 1] = domid;
+
+		if (caps & XENMANAGE_GETDOMSTATE_CAP_CONTROL) {
+			/*
+			 * Only update with first found - otherwise use command
+			 * line.
+			 */
+			if (priv_domid == DOMID_INVALID)
+				priv_domid = domid;
+		}
+
+		if (caps & XENMANAGE_GETDOMSTATE_CAP_XENSTORE) {
+			/*
+			 * Update with last found.  dom0 or dom0less will only
+			 * have 1 domain.  stubdom there will be dom0 and dom1,
+			 * so this will take the second for stubdom.
+			 */
+			dom0_domid = domid;
+		}
+	}
+
+	if (dom0_domid == DOMID_INVALID)
+		dom0_domid = priv_domid;
 
-	if (!live_update) {
-		port = get_domain_evtchn(stub_domid);
-		if (port == -1)
-			barf_perror("Failed to initialize stubdom port");
+	if (dom0_domid == DOMID_INVALID)
+		barf("Could not determine xenstore domid\n");
+
+	/*
+	 * Local domid must be first to setup structures for firing the special
+	 * watches.
+	 */
+	if (init_domain(dom0_domid))
+		introduce_count++;
 
-		stubdom = introduce_domain(NULL, stub_domid, port, false);
-		if (!stubdom)
-			barf_perror("Failed to initialize stubdom");
+	for (unsigned int i = 0; i < nr_domids; i++) {
+		domid = domids[i];
+		if (domid == dom0_domid)
+			continue;
 
-		xenevtchn_notify(xce_handle, stubdom->port);
+		if (init_domain(domid))
+			introduce_count++;
 	}
 
+	talloc_free(domids);
+
+	if (introduce_count == 0)
+		barf("Did not initialize any domains");
+}
+
+void stubdom_init(bool live_update)
+{
+#ifdef __MINIOS__
 	mount_9pfs(live_update);
 #endif
 }
diff --git a/tools/xenstored/domain.h b/tools/xenstored/domain.h
index 3ca702f56d..3b1fce74cf 100644
--- a/tools/xenstored/domain.h
+++ b/tools/xenstored/domain.h
@@ -92,7 +92,7 @@ int do_set_feature(const void *ctx, struct connection *conn,
 
 void domain_early_init(void);
 void domain_init(int evtfd);
-void dom0_init(void);
+void init_domains(void);
 void stubdom_init(bool live_update);
 void domain_deinit(void);
 void ignore_connection(struct connection *conn, unsigned int err);
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Juergen Gross ,
	Julien Grall , Anthony PERARD 
Subject: [PATCH v6 4/8] tools/xenstored: Check NULL domain in domain_chk_quota()
Date: Fri, 15 Aug 2025 17:35:52 -0400
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With separate control and xenstore domains, the xenstore domain itself
is no longer privileged.  Local socket connections do not have
conn->domain assigned, but domain_chk_quota() will go ahead and
dereference it.  The !domid_is_unprivileged(conn->id) check usually
means the function would have already returned.

Bail out on !conn->domain to avoid faulting.  This adds a similar check
to that in domain_max_chk()

Signed-off-by: Jason Andryuk 
---
v6:
New
---
 tools/xenstored/domain.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c
index 051e3fd164..c74bafa165 100644
--- a/tools/xenstored/domain.c
+++ b/tools/xenstored/domain.c
@@ -1762,7 +1762,7 @@ static bool domain_chk_quota(struct connection *conn, unsigned int mem)
 	time_t now;
 	struct domain *domain;
 
-	if (!conn || !domid_is_unprivileged(conn->id) ||
+	if (!conn || !conn->domain || !domid_is_unprivileged(conn->id) ||
 	    conn->is_ignored)
 		return false;
 
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Juergen Gross ,
	Julien Grall , Anthony PERARD 
Subject: [PATCH v6 5/8] tools/xenstored: Use priv_domid for manual nodes and permission
Date: Fri, 15 Aug 2025 17:35:53 -0400
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Usually, priv_domid == dom0_domid == 0, and that is what is expected.
If we rename s/dom0_domid/store_domid/, it seems more likely we want to
actually have the priv_domid as the owner.

That leads to follow on changes to ensure that the priv_domid is created
first.

Signed-off-by: Jason Andryuk 
Reviewed-by: Juergen Gross 
---
v5:
R-b Juergen
s/Local/Privileged/ in comment
---
 tools/xenstored/core.c   |  4 ++--
 tools/xenstored/domain.c | 14 +++++++-------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c
index d447e1167e..7a65ddb585 100644
--- a/tools/xenstored/core.c
+++ b/tools/xenstored/core.c
@@ -2269,7 +2269,7 @@ struct connection *get_connection_by_id(unsigned int conn_id)
 static void manual_node(const char *name, const char *child)
 {
 	struct node *node;
-	struct xs_permissions perms = { .id = dom0_domid,
+	struct xs_permissions perms = { .id = priv_domid,
 					.perms = XS_PERM_NONE };
 
 	node = talloc_zero(NULL, struct node);
@@ -2320,7 +2320,7 @@ void setup_structure(bool live_update)
 		manual_node("/tool/xenstored", NULL);
 		manual_node("@releaseDomain", NULL);
 		manual_node("@introduceDomain", NULL);
-		domain_nbentry_fix(dom0_domid, 5, true);
+		domain_nbentry_fix(priv_domid, 5, true);
 	}
 }
 
diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c
index c74bafa165..bcc63104b7 100644
--- a/tools/xenstored/domain.c
+++ b/tools/xenstored/domain.c
@@ -1026,7 +1026,7 @@ static struct domain *introduce_domain(const void *ctx,
 	struct domain *domain;
 	int rc;
 	struct xenstore_domain_interface *interface;
-	bool is_master_domain = (domid == xenbus_master_domid());
+	bool is_priv_domain = (domid == priv_domid);
 
 	domain = find_or_alloc_domain(ctx, domid);
 	if (!domain)
@@ -1051,13 +1051,13 @@ static struct domain *introduce_domain(const void *ctx,
 		if (!restore)
 			interface->server_features = domain->features;
 
-		if (is_master_domain)
+		if (is_priv_domain)
 			setup_structure(restore);
 
 		/* Now domain belongs to its connection. */
 		talloc_steal(domain->conn, domain);
 
-		if (!is_master_domain && !restore)
+		if (!is_priv_domain && !restore)
 			fire_special_watches("@introduceDomain");
 	} else {
 		/* Use XS_INTRODUCE for recreating the xenbus event-channel. */
@@ -1392,15 +1392,15 @@ void init_domains(void)
 		barf("Could not determine xenstore domid\n");
 
 	/*
-	 * Local domid must be first to setup structures for firing the special
-	 * watches.
+	 * Privileged domid must be first to setup structures for firing the
+	 * special watches.
 	 */
-	if (init_domain(dom0_domid))
+	if (init_domain(priv_domid))
 		introduce_count++;
 
 	for (unsigned int i = 0; i < nr_domids; i++) {
 		domid = domids[i];
-		if (domid == dom0_domid)
+		if (domid == priv_domid)
 			continue;
 
 		if (init_domain(domid))
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Juergen Gross ,
	Julien Grall , Anthony PERARD 
Subject: [PATCH v6 6/8] tools/xenstored: Rename dom0_domid to store_domid
Date: Fri, 15 Aug 2025 17:35:54 -0400
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The dom0_domid variable is misnamed and conflates purposes.  If we have
xenstored running in a Linux domain that is not dom0, this variable
controls the lookup of /proc/xen/xsd_kva and the event channel.

Rename to store_domid to better show its purpose.

One implication of this change is that the xenstore domain is not
privileged by virtue of considering store_domid as privileged.

domain_is_unprivileged() removes the dom0_domid/store_domid check, so
xenstore domain is no longer considered privileged.

onearg_domain() is updated to return EINVAL for store_domid or priv_domid
to maintain the ability to call XS_RESUME.

xenbus_master_domid() is removed with store_domid being used instead.

Add a description of the -m/--master-domid options while
doing this.

Signed-off-by: Jason Andryuk 
Reviewed-by: Juergen Gross 
---
v6:
R-b: Juergen

v5:
Remove xenbus_master_domid()
domain_is_unprivileged() drop dom0/store_domid.
XS_RESUME/onearg_domain() check store_domid || priv_domid
---
 tools/xenstored/core.c   |  9 ++++++---
 tools/xenstored/core.h   |  6 ++----
 tools/xenstored/domain.c | 14 +++++++-------
 tools/xenstored/posix.c  |  4 ++--
 4 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/tools/xenstored/core.c b/tools/xenstored/core.c
index 7a65ddb585..64c478a801 100644
--- a/tools/xenstored/core.c
+++ b/tools/xenstored/core.c
@@ -2539,7 +2539,10 @@ static void usage(void)
 "                          allowed timeout candidates are:\n"
 "                          watch-event: time a watch-event is kept pending\n"
 "  -K, --keep-orphans      don't delete nodes owned by a domain when the\n"
-"                          domain is deleted (this is a security risk!)\n");
+"                          domain is deleted (this is a security risk!)\n"
+"  -m, --master-domid      specify the domid of the domain where xenstored\n"
+"                          is running.  defaults to 0\n"
+);
 }
 
 
@@ -2567,7 +2570,7 @@ static struct option options[] = {
 #endif
 	{ NULL, 0, NULL, 0 } };
 
-int dom0_domid = DOMID_INVALID;
+int store_domid = DOMID_INVALID;
 int dom0_event = 0;
 int priv_domid = DOMID_INVALID;
 domid_t stub_domid = DOMID_INVALID;
@@ -2736,7 +2739,7 @@ int main(int argc, char *argv[])
 			dom0_event = get_optval_uint(optarg);
 			break;
 		case 'm':
-			dom0_domid = get_optval_uint(optarg);
+			store_domid = get_optval_uint(optarg);
 			break;
 		case 'p':
 			priv_domid = get_optval_uint(optarg);
diff --git a/tools/xenstored/core.h b/tools/xenstored/core.h
index cef3c71eb0..e0b48e4978 100644
--- a/tools/xenstored/core.h
+++ b/tools/xenstored/core.h
@@ -365,7 +365,7 @@ do {						\
 		trace("tdb: " __VA_ARGS__);	\
 } while (0)
 
-extern int dom0_domid;
+extern int store_domid;
 extern int dom0_event;
 extern int priv_domid;
 extern domid_t stub_domid;
@@ -382,11 +382,9 @@ uint64_t get_now_msec(void);
 void *xenbus_map(void);
 void unmap_xenbus(void *interface);
 
-static inline int xenbus_master_domid(void) { return dom0_domid; }
-
 static inline bool domid_is_unprivileged(unsigned int domid)
 {
-	return domid != dom0_domid && domid != priv_domid;
+	return domid != priv_domid;
 }
 
 static inline bool domain_is_unprivileged(const struct connection *conn)
diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c
index bcc63104b7..e282b5c5ed 100644
--- a/tools/xenstored/domain.c
+++ b/tools/xenstored/domain.c
@@ -509,7 +509,7 @@ static const struct interface_funcs domain_funcs = {
 
 static void *map_interface(domid_t domid)
 {
-	if (domid == xenbus_master_domid())
+	if (domid == store_domid)
 		return xenbus_map();
 
 #ifdef __MINIOS__
@@ -524,7 +524,7 @@ static void *map_interface(domid_t domid)
 
 static void unmap_interface(domid_t domid, void *interface)
 {
-	if (domid == xenbus_master_domid())
+	if (domid == store_domid)
 		unmap_xenbus(interface);
 	else if (domid != stub_domid)
 		xengnttab_unmap(*xgt_handle, interface, 1);
@@ -1158,7 +1158,7 @@ static struct domain *onearg_domain(struct connection *conn,
 		return ERR_PTR(-EINVAL);
 
 	domid = atoi(domid_str);
-	if (domid == dom0_domid)
+	if (domid == store_domid || domid == priv_domid)
 		return ERR_PTR(-EINVAL);
 
 	return find_connected_domain(domid);
@@ -1381,14 +1381,14 @@ void init_domains(void)
 			 * have 1 domain.  stubdom there will be dom0 and dom1,
 			 * so this will take the second for stubdom.
 			 */
-			dom0_domid = domid;
+			store_domid = domid;
 		}
 	}
 
-	if (dom0_domid == DOMID_INVALID)
-		dom0_domid = priv_domid;
+	if (store_domid == DOMID_INVALID)
+		store_domid = priv_domid;
 
-	if (dom0_domid == DOMID_INVALID)
+	if (store_domid == DOMID_INVALID)
 		barf("Could not determine xenstore domid\n");
 
 	/*
diff --git a/tools/xenstored/posix.c b/tools/xenstored/posix.c
index 4a97f53dc0..0ec7babb7a 100644
--- a/tools/xenstored/posix.c
+++ b/tools/xenstored/posix.c
@@ -174,7 +174,7 @@ static evtchn_port_t get_xenbus_evtchn(void)
  */
 evtchn_port_t get_domain_evtchn(unsigned int domid)
 {
-	if (domid == xenbus_master_domid())
+	if (domid == store_domid)
 		return get_xenbus_evtchn();
 
 	return 0;
@@ -280,7 +280,7 @@ static void accept_connection(int sock)
 	conn = new_connection(&socket_funcs);
 	if (conn) {
 		conn->fd = fd;
-		conn->id = dom0_domid;
+		conn->id = store_domid;
 	} else
 		close(fd);
 }
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Juergen Gross ,
	Julien Grall , Anthony PERARD 
Subject: [PATCH v6 7/8] tools/xenstored: Remove stubdom special casing
Date: Fri, 15 Aug 2025 17:35:55 -0400
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posix.c and minios.c implement the same named functions serving slightly
different purposes.

For xenbus_map()
posix.c maps the local /dev/xen/xsd_kva
minios.c maps dom0 via grant and there is open coding for stub_domid in
map_interface.

Change xenbus_map() to map the local domain's interface.  The default
grant table mapping is performed otherwise.

Signed-off-by: Jason Andryuk 
Reviewed-by: Juergen Gross 
---
v6:
R-b: Juergen

v5:
Re-order later
---
 tools/xenstored/domain.c | 5 -----
 tools/xenstored/minios.c | 4 +---
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c
index e282b5c5ed..cf5a54965a 100644
--- a/tools/xenstored/domain.c
+++ b/tools/xenstored/domain.c
@@ -512,11 +512,6 @@ static void *map_interface(domid_t domid)
 	if (domid == store_domid)
 		return xenbus_map();
 
-#ifdef __MINIOS__
-	if (domid == stub_domid)
-		return xenstore_buf;
-#endif
-
 	return xengnttab_map_grant_ref(*xgt_handle, domid,
 				       GNTTAB_RESERVED_XENSTORE,
 				       PROT_READ|PROT_WRITE);
diff --git a/tools/xenstored/minios.c b/tools/xenstored/minios.c
index 60d921cf01..a214e23907 100644
--- a/tools/xenstored/minios.c
+++ b/tools/xenstored/minios.c
@@ -61,13 +61,11 @@ evtchn_port_t get_domain_evtchn(unsigned int domid)
 
 void *xenbus_map(void)
 {
-	return xengnttab_map_grant_ref(*xgt_handle, xenbus_master_domid(),
-			GNTTAB_RESERVED_XENSTORE, PROT_READ|PROT_WRITE);
+	return xenstore_buf;
 }
 
 void unmap_xenbus(void *interface)
 {
-	xengnttab_unmap(*xgt_handle, interface, 1);
 }
 
 void early_init(bool live_update, bool dofork, const char *pidfile)
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Juergen Gross ,
	Julien Grall , Anthony PERARD 
Subject: [PATCH v6 8/8] tools/xenstored: Remove hardcoded implicit path
Date: Fri, 15 Aug 2025 17:35:56 -0400
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Update get_implicit_path to return the correct value for a non-dom0
xenstored domain.

Signed-off-by: Jason Andryuk 
Reviewed-by: Juergen Gross 
---
v5:
R-b: Juergen
---
 tools/xenstored/domain.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c
index cf5a54965a..694d68670a 100644
--- a/tools/xenstored/domain.c
+++ b/tools/xenstored/domain.c
@@ -1312,11 +1312,13 @@ static int close_xgt_handle(void *_handle)
 	return 0;
 }
 
+static char store_domain_path[] = "/local/domain/65535";
+
 /* Returns the implicit path of a connection (only domains have this) */
 const char *get_implicit_path(const struct connection *conn)
 {
 	if (!conn->domain)
-		return "/local/domain/0";
+		return store_domain_path;
 	return conn->domain->path;
 }
 
@@ -1386,6 +1388,9 @@ void init_domains(void)
 	if (store_domid == DOMID_INVALID)
 		barf("Could not determine xenstore domid\n");
 
+	snprintf(store_domain_path, sizeof(store_domain_path),
+		 "/local/domain/%u", store_domid);
+
 	/*
 	 * Privileged domid must be first to setup structures for firing the
 	 * special watches.
-- 
2.50.1



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Date: Fri, 15 Aug 2025 17:36:57 -0400
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Subject: Re: [PATCH] drivers/xen/xenbus: remove quirk for Xen 3.x
To: Juergen Gross , 
CC: Stefano Stabellini , Oleksandr Tyshchenko
	, 
References: <20250815074052.13792-1-jgross@suse.com>
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From: Jason Andryuk 
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On 2025-08-15 03:40, Juergen Gross wrote:
> The kernel is not supported to run as a Xen guest on Xen versions
> older than 4.0.
> 
> Remove xen_strict_xenbus_quirk() which is testing the Xen version to be
> at least 4.0.
> 
> Signed-off-by: Juergen Gross 

Reviewed-by: Jason Andryuk 


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From: Bernhard Kaindl 
To: xen-devel@lists.xenproject.org
Cc: Bernhard Kaindl ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Tamas K Lengyel ,
	"Daniel P. Smith" ,
	Juergen Gross ,
	Christian Lindig ,
	David Scott ,
	Alejandro Vallejo 
Subject: [PATCH v2 0/7] xen/page_alloc: Add NUMA-node specific memory claims
Date: Sat, 16 Aug 2025 13:19:26 +0200
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Xen supports claiming an amount of memory ahead of allocating it to
ensure that the memory for the domain is available for allocation.

On NUMA hosts, the same assurance is needed on a per-NUMA-node basis
to ensure optimal placement of domain memory on the correct NUMA node:

Add per-NUMA-node claims and add a new Hypercall to claim memory for
a domain using XEN_DOMCTL_claim_memory and xc_domain_claim_memory().

As we will implement multi-node claims as well, we updated the design
to be flexible for multi-node claims, so that a 2nd series can build
upon it without changing the hypercall API.

Bernhard Kaindl (6):
  xen/page_alloc: Simplify domain_adjust_tot_pages for future changes
  xen: New API to claim memory for a domain using XEN_DOMCTL_claim_memory

Alejandro Vallejo (1):
  xen/page_alloc: Remove `claim` from domain_set_outstanding_pages()

Alejandro Vallejo and Bernhard Kaindl (5):
  xen/page_alloc: Add static per-NUMA-node counts of free pages
  xen: Add node argument to
    domain_{adjust_tot_pages,set_outstanding_pages}()
  xen/page_alloc.c: Create per-node outstanding claims
  xen/page_alloc: Check per-node claims in alloc_heap_pages()

 tools/flask/policy/modules/dom0.te  |   1 +
 tools/flask/policy/modules/xen.if   |   1 +
 tools/include/xenctrl.h             |   4 +
 tools/libs/ctrl/xc_domain.c         |  42 ++++++++
 tools/ocaml/libs/xc/xenctrl.ml      |   9 ++
 tools/ocaml/libs/xc/xenctrl.mli     |   9 ++
 tools/ocaml/libs/xc/xenctrl_stubs.c |  21 ++++
 xen/arch/x86/mm.c                   |   3 +-
 xen/arch/x86/mm/mem_sharing.c       |   4 +-
 xen/common/domain.c                 |  32 +++++-
 xen/common/domctl.c                 |   8 ++
 xen/common/grant_table.c            |   4 +-
 xen/common/memory.c                 |   6 +-
 xen/common/page_alloc.c             | 154 ++++++++++++++++++++++------
 xen/include/public/domctl.h         |  17 +++
 xen/include/xen/domain.h            |   2 +
 xen/include/xen/mm.h                |   6 +-
 xen/include/xen/sched.h             |   1 +
 xen/xsm/flask/hooks.c               |   3 +
 xen/xsm/flask/policy/access_vectors |   2 +
 20 files changed, 285 insertions(+), 44 deletions(-)

-- 
2.43.0



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From: Bernhard Kaindl 
To: xen-devel@lists.xenproject.org
Cc: Bernhard Kaindl ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Alejandro Vallejo 
Subject: [PATCH v2 1/7] xen/page_alloc: Simplify domain_adjust_tot_pages for future changes
Date: Sat, 16 Aug 2025 13:19:27 +0200
Message-ID: <5f417fea5ca8e4da0d4b9679103c3eff4bc92900.1755341947.git.bernhard.kaindl@cloud.com>
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domain_adjust_tot_pages() is used to update the domain's total pages
after allocating and freeing memory.

Simplify the design for updating it for single and even more so
for multi-node claims regarding the case where we could have
allocated more memory than we had claims left.

Replace it with min() to avoid reducing the outstadings claims
by more than we had left to claim:

When domain memory is freed, we skip changing the claim. Thus, this
only handles reducing the claims after allocating. So, min() is fine.

Signed-off-by: Bernhard Kaindl 
Cc: Alejandro Vallejo 
---
 xen/common/page_alloc.c | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c
index ec9dec365e..e1ac22b9ed 100644
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -510,8 +510,14 @@ static unsigned long avail_heap_pages(
     return free_pages;
 }
 
+/*
+ * Update the total number of pages and outstanding claims of a domain.
+ * - When pages were freed, we do not increase outstanding claims.
+ */
 unsigned long domain_adjust_tot_pages(struct domain *d, long pages)
 {
+    unsigned long adjustment;
+
     ASSERT(rspin_is_locked(&d->page_alloc_lock));
     d->tot_pages += pages;
 
@@ -519,23 +525,22 @@ unsigned long domain_adjust_tot_pages(struct domain *d, long pages)
      * can test d->outstanding_pages race-free because it can only change
      * if d->page_alloc_lock and heap_lock are both held, see also
      * domain_set_outstanding_pages below
+     *
+     * If the domain has no outstanding claims (or we freed pages instead),
+     * we don't update outstanding claims and skip the claims adjustment.
      */
     if ( !d->outstanding_pages || pages <= 0 )
         goto out;
 
     spin_lock(&heap_lock);
     BUG_ON(outstanding_claims < d->outstanding_pages);
-    if ( d->outstanding_pages < pages )
-    {
-        /* `pages` exceeds the domain's outstanding count. Zero it out. */
-        outstanding_claims -= d->outstanding_pages;
-        d->outstanding_pages = 0;
-    }
-    else
-    {
-        outstanding_claims -= pages;
-        d->outstanding_pages -= pages;
-    }
+    /*
+     * Reduce claims by outstanding claims or pages (whichever is smaller):
+     * If allocated > outstanding, reduce the claims only by outstanding pages.
+     */
+    adjustment = min(d->outstanding_pages, (unsigned int)pages);
+    d->outstanding_pages -= adjustment;
+    outstanding_claims -= adjustment;
     spin_unlock(&heap_lock);
 
 out:
-- 
2.43.0



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From: Bernhard Kaindl 
To: xen-devel@lists.xenproject.org
Cc: Bernhard Kaindl ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Alejandro Vallejo 
Subject: [PATCH v2 2/7] xen/page_alloc: Remove `claim` from domain_set_outstanding_pages()
Date: Sat, 16 Aug 2025 13:19:28 +0200
Message-ID: <73dc08d9ec628823309acc40a2603e9138bdd4b1.1755341947.git.bernhard.kaindl@cloud.com>
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With a single global count for the claims it is easy to substract
domain_tot_pages() from the claim so the number given in the hypercall
is the real reservation of the domain. This is the current behaviour.

However, a later patch introduces node-specific claims and those interact
very poorly with such a scheme. Since accounting domain_tot_pages() in
one case but not the other seems strictly worse than not accounting them
at all (which is at least consistent), this patch stops substracting
tot_pages from the claim and instead checks that claimed memory +
allocated memory don't exceed max_mem.

Arguably it's also clearer for the caller to align the amount of claimed
memory with that of the requested claim. xl/libxenguest code never updated
an existing claim: It stakes a claim, allocates all domain memory, cancels
a possible leftover claim, finishes building the domain and unpauses it.

Signed-off-by: Bernhard Kaindl 
Signed-off-by: Alejandro Vallejo 
---
 xen/common/page_alloc.c | 19 ++++++-------------
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c
index e1ac22b9ed..7e90b9cc1e 100644
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -550,7 +550,7 @@ out:
 int domain_set_outstanding_pages(struct domain *d, unsigned long pages)
 {
     int ret = -ENOMEM;
-    unsigned long claim, avail_pages;
+    unsigned long avail_pages;
 
     /*
      * take the domain's page_alloc_lock, else all d->tot_page adjustments
@@ -576,28 +576,21 @@ int domain_set_outstanding_pages(struct domain *d, unsigned long pages)
         goto out;
     }
 
-    /* disallow a claim not exceeding domain_tot_pages() or above max_pages */
-    if ( (pages <= domain_tot_pages(d)) || (pages > d->max_pages) )
+    /* Don't claim past max_pages */
+    if ( (domain_tot_pages(d) + pages) > d->max_pages )
     {
         ret = -EINVAL;
         goto out;
     }
 
     /* how much memory is available? */
-    avail_pages = total_avail_pages;
+    avail_pages = total_avail_pages - outstanding_claims;
 
-    avail_pages -= outstanding_claims;
-
-    /*
-     * Note, if domain has already allocated memory before making a claim
-     * then the claim must take domain_tot_pages() into account
-     */
-    claim = pages - domain_tot_pages(d);
-    if ( claim > avail_pages )
+    if ( pages > avail_pages )
         goto out;
 
     /* yay, claim fits in available memory, stake the claim, success! */
-    d->outstanding_pages = claim;
+    d->outstanding_pages = pages;
     outstanding_claims += d->outstanding_pages;
     ret = 0;
 
-- 
2.43.0



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        Sat, 16 Aug 2025 04:22:38 -0700 (PDT)
From: Bernhard Kaindl 
To: xen-devel@lists.xenproject.org
Cc: Bernhard Kaindl ,
	Jan Beulich ,
	Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Anthony PERARD ,
	Michal Orzel ,
	Julien Grall ,
	Stefano Stabellini ,
	Tamas K Lengyel ,
	Alejandro Vallejo 
Subject: [PATCH v2 4/7] xen/page_alloc: Add node argument to domain_{adjust_tot_pages,set_outstanding_pages}()
Date: Sat, 16 Aug 2025 13:19:30 +0200
Message-ID: <62a9612c4f9d507184c50f720b5fe22f4921e85e.1755341947.git.bernhard.kaindl@cloud.com>
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domain_adjust_tot_pages() adjusts the total pages of a domain
after allocating or freeing memory. When allocating, it also
reduces the outstanding claims of a domain as pages are allocated.

When adding the node argument, we pass the node from which the pages
were allocated. When pages are freed, we simply pass NUMA_NO_NODE as
when freeing, the outstanding claims are not updated anyways.

domain_set_outstanding_pages() sets the amount of outstanding claims
of a domain. We pass the node on which to to stake an claim,
or NUMA_NO_NODE for host-wide claims.

No functional change, as neither function uses the arguments
for anything yet. It's a prerequisite to simplify for the next
patch that introduces per-node claim counts.

Changed since v1:
- Fix for the correct indentation of line with '-dec_count));'

Signed-off-by: Bernhard Kaindl 
Signed-off-by: Alejandro Vallejo 
---
 xen/arch/x86/mm.c             |  3 ++-
 xen/arch/x86/mm/mem_sharing.c |  4 ++--
 xen/common/domain.c           |  2 +-
 xen/common/grant_table.c      |  4 ++--
 xen/common/memory.c           |  6 ++++--
 xen/common/page_alloc.c       | 17 ++++++++++++-----
 xen/include/xen/mm.h          |  6 ++++--
 7 files changed, 27 insertions(+), 15 deletions(-)

diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c
index e7fd56c7ce..effc67c6ba 100644
--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -4444,7 +4444,8 @@ int steal_page(
     page_list_del(page, &d->page_list);
 
     /* Unlink from original owner. */
-    if ( !(memflags & MEMF_no_refcount) && !domain_adjust_tot_pages(d, -1) )
+    if ( !(memflags & MEMF_no_refcount) &&
+         !domain_adjust_tot_pages(d, NUMA_NO_NODE, -1) )
         drop_dom_ref = true;
 
     nrspin_unlock(&d->page_alloc_lock);
diff --git a/xen/arch/x86/mm/mem_sharing.c b/xen/arch/x86/mm/mem_sharing.c
index da28266ef0..2551c0d86e 100644
--- a/xen/arch/x86/mm/mem_sharing.c
+++ b/xen/arch/x86/mm/mem_sharing.c
@@ -720,7 +720,7 @@ static int page_make_sharable(struct domain *d,
     if ( !validate_only )
     {
         page_set_owner(page, dom_cow);
-        drop_dom_ref = !domain_adjust_tot_pages(d, -1);
+        drop_dom_ref = !domain_adjust_tot_pages(d, NUMA_NO_NODE, -1);
         page_list_del(page, &d->page_list);
     }
 
@@ -766,7 +766,7 @@ static int page_make_private(struct domain *d, struct page_info *page)
     ASSERT(page_get_owner(page) == dom_cow);
     page_set_owner(page, d);
 
-    if ( domain_adjust_tot_pages(d, 1) == 1 )
+    if ( domain_adjust_tot_pages(d, page_to_nid(page), 1) == 1 )
         get_knownalive_domain(d);
     page_list_add_tail(page, &d->page_list);
     nrspin_unlock(&d->page_alloc_lock);
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 5241a1629e..1beadb05e1 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -1239,7 +1239,7 @@ int domain_kill(struct domain *d)
         rspin_barrier(&d->domain_lock);
         argo_destroy(d);
         vnuma_destroy(d->vnuma);
-        domain_set_outstanding_pages(d, 0);
+        domain_set_outstanding_pages(d, NUMA_NO_NODE, 0);
         /* fallthrough */
     case DOMDYING_dying:
         rc = domain_teardown(d);
diff --git a/xen/common/grant_table.c b/xen/common/grant_table.c
index cf131c43a1..8fea75dbb2 100644
--- a/xen/common/grant_table.c
+++ b/xen/common/grant_table.c
@@ -2405,7 +2405,7 @@ gnttab_transfer(
         }
 
         /* Okay, add the page to 'e'. */
-        if ( unlikely(domain_adjust_tot_pages(e, 1) == 1) )
+        if ( unlikely(domain_adjust_tot_pages(e, page_to_nid(page), 1) == 1) )
             get_knownalive_domain(e);
 
         /*
@@ -2431,7 +2431,7 @@ gnttab_transfer(
              * page in the page total
              */
             nrspin_lock(&e->page_alloc_lock);
-            drop_dom_ref = !domain_adjust_tot_pages(e, -1);
+            drop_dom_ref = !domain_adjust_tot_pages(e, NUMA_NO_NODE, -1);
             nrspin_unlock(&e->page_alloc_lock);
 
             if ( okay /* i.e. e->is_dying due to the surrounding if() */ )
diff --git a/xen/common/memory.c b/xen/common/memory.c
index 3688e6dd50..b8cf4bd23d 100644
--- a/xen/common/memory.c
+++ b/xen/common/memory.c
@@ -775,7 +775,8 @@ static long memory_exchange(XEN_GUEST_HANDLE_PARAM(xen_memory_exchange_t) arg)
 
                 nrspin_lock(&d->page_alloc_lock);
                 drop_dom_ref = (dec_count &&
-                                !domain_adjust_tot_pages(d, -dec_count));
+                                !domain_adjust_tot_pages(d, NUMA_NO_NODE,
+                                                         -dec_count));
                 nrspin_unlock(&d->page_alloc_lock);
 
                 if ( drop_dom_ref )
@@ -1682,7 +1683,8 @@ long do_memory_op(unsigned long cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
         rc = xsm_claim_pages(XSM_PRIV, d);
 
         if ( !rc )
-            rc = domain_set_outstanding_pages(d, reservation.nr_extents);
+            rc = domain_set_outstanding_pages(d, NUMA_NO_NODE,
+                                              reservation.nr_extents);
 
         rcu_unlock_domain(d);
 
diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c
index 43de9296fd..e8ba21dc46 100644
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -517,7 +517,8 @@ static unsigned long avail_heap_pages(
  * Update the total number of pages and outstanding claims of a domain.
  * - When pages were freed, we do not increase outstanding claims.
  */
-unsigned long domain_adjust_tot_pages(struct domain *d, long pages)
+unsigned long domain_adjust_tot_pages(struct domain *d, nodeid_t node,
+                                      long pages)
 {
     unsigned long adjustment;
 
@@ -550,7 +551,8 @@ out:
     return d->tot_pages;
 }
 
-int domain_set_outstanding_pages(struct domain *d, unsigned long pages)
+int domain_set_outstanding_pages(struct domain *d, nodeid_t node,
+                                 unsigned long pages)
 {
     int ret = -ENOMEM;
     unsigned long avail_pages;
@@ -2620,6 +2622,8 @@ int assign_pages(
 
     if ( !(memflags & MEMF_no_refcount) )
     {
+        nodeid_t node = page_to_nid(&pg[0]);
+
         if ( unlikely(d->tot_pages + nr < nr) )
         {
             gprintk(XENLOG_INFO,
@@ -2631,7 +2635,9 @@ int assign_pages(
             goto out;
         }
 
-        if ( unlikely(domain_adjust_tot_pages(d, nr) == nr) )
+        ASSERT(node == page_to_nid(&pg[nr - 1]));
+
+        if ( unlikely(domain_adjust_tot_pages(d, node, nr) == nr) )
             get_knownalive_domain(d);
     }
 
@@ -2764,7 +2770,8 @@ void free_domheap_pages(struct page_info *pg, unsigned int order)
                 }
             }
 
-            drop_dom_ref = !domain_adjust_tot_pages(d, -(1 << order));
+            drop_dom_ref = !domain_adjust_tot_pages(d, NUMA_NO_NODE,
+                                                    -(1 << order));
 
             rspin_unlock(&d->page_alloc_lock);
 
@@ -2970,7 +2977,7 @@ void free_domstatic_page(struct page_info *page)
 
     arch_free_heap_page(d, page);
 
-    drop_dom_ref = !domain_adjust_tot_pages(d, -1);
+    drop_dom_ref = !domain_adjust_tot_pages(d, NUMA_NO_NODE, -1);
 
     unprepare_staticmem_pages(page, 1, scrub_debug);
 
diff --git a/xen/include/xen/mm.h b/xen/include/xen/mm.h
index 93c037d618..f977e73b1c 100644
--- a/xen/include/xen/mm.h
+++ b/xen/include/xen/mm.h
@@ -65,6 +65,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -130,8 +131,9 @@ mfn_t xen_map_to_mfn(unsigned long va);
 int populate_pt_range(unsigned long virt, unsigned long nr_mfns);
 /* Claim handling */
 unsigned long __must_check domain_adjust_tot_pages(struct domain *d,
-    long pages);
-int domain_set_outstanding_pages(struct domain *d, unsigned long pages);
+    nodeid_t node, long pages);
+int domain_set_outstanding_pages(struct domain *d, nodeid_t node,
+                                 unsigned long pages);
 void get_outstanding_claims(uint64_t *free_pages, uint64_t *outstanding_pages);
 
 /* Domain suballocator. These functions are *not* interrupt-safe.*/
-- 
2.43.0



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        Sat, 16 Aug 2025 04:23:36 -0700 (PDT)
From: Bernhard Kaindl 
To: xen-devel@lists.xenproject.org
Cc: Bernhard Kaindl ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Marcus Granado ,
	Alejandro Vallejo 
Subject: [PATCH v2 5/7] xen/page_alloc: Create per-node outstanding claims
Date: Sat, 16 Aug 2025 13:19:31 +0200
Message-ID: <646f3bdbbfef5ace7902ca18c532b5518612f36e.1755341947.git.bernhard.kaindl@cloud.com>
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Extend domain_set_outstanding_claims() to allow staking claims on a
specific NUMA node instead of host-wide:

A claim on a specific NUMA node is the amount of d->outstanding_claims
where the new field d->claim_node field is not NUMA_NO_NODE.

We use the most straightforward implementation to minimise the amount
of changes in this commit and the rest of the series: In the next series
that converts the claims handling the multi-node claims, this will of
course be converted into another structure. It helps to keep this
commit focused on the central challenge of the new type of claim and
leaves extending claims to multi-node claims for the next series.

Also extend get_free_buddy() for when it circles round-robin over nodes:
Make it skip NUMA nodes that do not have enough unclaimed memory left.

---
Changes since v1:
- Join all conditions into a single if clause
- Improve the function description and comments
- Use const when passing struct domain when applicable
- Renamed pernode_oc[] to per_node_outstanding_claims[]
- Reject invalid node IDs in domain_set_outstanding_pages()
- Use nodeid_t instead of unsigned int for the claim_node field.
- Removed dependency on MEMF_EXACT_NODE (checked in get_free_buddy())
- Added awareness for honoring NUMA claims to get_free_buddy()

Signed-off-by: Bernhard Kaindl 
Signed-off-by: Marcus Granado 
Signed-off-by: Alejandro Vallejo 
---
 xen/common/page_alloc.c | 37 +++++++++++++++++++++++++++++++++++--
 xen/include/xen/sched.h |  1 +
 2 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c
index e8ba21dc46..63ecd74dcc 100644
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -491,6 +491,7 @@ static unsigned long per_node_avail_pages[MAX_NUMNODES];
 
 static DEFINE_SPINLOCK(heap_lock);
 static long outstanding_claims; /* total outstanding claims by all domains */
+static unsigned long per_node_outstanding_claims[MAX_NUMNODES];
 
 static unsigned long avail_heap_pages(
     unsigned int zone_lo, unsigned int zone_hi, unsigned int node)
@@ -532,8 +533,12 @@ unsigned long domain_adjust_tot_pages(struct domain *d, nodeid_t node,
      *
      * If the domain has no outstanding claims (or we freed pages instead),
      * we don't update outstanding claims and skip the claims adjustment.
+     *
+     * Also don't update outstanding claims when the domain has node-specific
+     * claims, but the memory allocation was from a different NUMA node.
      */
-    if ( !d->outstanding_pages || pages <= 0 )
+    if ( !d->outstanding_pages || pages <= 0 ||
+         (d->claim_node != NUMA_NO_NODE && d->claim_node != node) )
         goto out;
 
     spin_lock(&heap_lock);
@@ -544,6 +549,8 @@ unsigned long domain_adjust_tot_pages(struct domain *d, nodeid_t node,
      */
     adjustment = min(d->outstanding_pages, (unsigned int)pages);
     d->outstanding_pages -= adjustment;
+    if ( d->claim_node != NUMA_NO_NODE ) /* adjust the static per-node claims */
+        per_node_outstanding_claims[d->claim_node] -= adjustment;
     outstanding_claims -= adjustment;
     spin_unlock(&heap_lock);
 
@@ -557,6 +564,9 @@ int domain_set_outstanding_pages(struct domain *d, nodeid_t node,
     int ret = -ENOMEM;
     unsigned long avail_pages;
 
+    if ( node != NUMA_NO_NODE && !node_online(node) )
+        return -EINVAL;
+
     /*
      * take the domain's page_alloc_lock, else all d->tot_page adjustments
      * must always take the global heap_lock rather than only in the much
@@ -569,6 +579,10 @@ int domain_set_outstanding_pages(struct domain *d, nodeid_t node,
     if ( pages == 0 )
     {
         outstanding_claims -= d->outstanding_pages;
+
+        if ( d->claim_node != NUMA_NO_NODE )
+            per_node_outstanding_claims[d->claim_node] -= d->outstanding_pages;
+
         d->outstanding_pages = 0;
         ret = 0;
         goto out;
@@ -591,12 +605,26 @@ int domain_set_outstanding_pages(struct domain *d, nodeid_t node,
     /* how much memory is available? */
     avail_pages = total_avail_pages - outstanding_claims;
 
+    /* This check can't be skipped for the NUMA case, or we may overclaim */
     if ( pages > avail_pages )
         goto out;
 
+    if ( node != NUMA_NO_NODE )
+    {
+        avail_pages = per_node_avail_pages[node] - per_node_outstanding_claims[node];
+
+        if ( pages > avail_pages )
+            goto out;
+    }
+
     /* yay, claim fits in available memory, stake the claim, success! */
     d->outstanding_pages = pages;
     outstanding_claims += d->outstanding_pages;
+    d->claim_node = node;
+
+    if ( node != NUMA_NO_NODE )
+        per_node_outstanding_claims[node] += pages;
+
     ret = 0;
 
 out:
@@ -934,7 +962,12 @@ static struct page_info *get_free_buddy(unsigned int zone_lo,
         zone = zone_hi;
         do {
             /* Check if target node can support the allocation. */
-            if ( !avail[node] || (avail[node][zone] < (1UL << order)) )
+            if ( !avail[node] || (avail[node][zone] < (1UL << order)) ||
+                 /* For host-wide allocations, skip nodes without enough
+                  * unclaimed memory. */
+                  (req_node == NUMA_NO_NODE && outstanding_claims &&
+                   ((per_node_avail_pages[node] -
+                     per_node_outstanding_claims[node]) < (1UL << order))) )
                 continue;
 
             /* Find smallest order which can satisfy the request. */
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index fd5c9f9333..9535ed7a6a 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -406,6 +406,7 @@ struct domain
     unsigned int     max_pages;         /* maximum value for domain_tot_pages() */
     unsigned int     extra_pages;       /* pages not included in domain_tot_pages() */
 
+    nodeid_t         claim_node;        /* NUMA_NO_NODE for host-wide claims */
 #ifdef CONFIG_MEM_SHARING
     atomic_t         shr_pages;         /* shared pages */
 #endif
-- 
2.43.0



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From: Bernhard Kaindl 
To: xen-devel@lists.xenproject.org
Cc: Bernhard Kaindl ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Alejandro Vallejo 
Subject: [PATCH v2 6/7] xen/page_alloc: Check per-node claims in alloc_heap_pages()
Date: Sat, 16 Aug 2025 13:19:32 +0200
Message-ID: <3836533d5424baa470e69838bac89862e14d44e0.1755341947.git.bernhard.kaindl@cloud.com>
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Extend the claim checks in alloc_heap_pages() to NUMA claims.

Signed-off-by: Bernhard Kaindl 
Signed-off-by: Alejandro Vallejo 

---
Changes since v1:
- No longer require the memflags & MEMF_exact_node for using claims

- If the NUMA node is not passed in memflags, get the NUMA node to
  conume claims from using the claim itself and confirm it using
  the domain's d->node_affinity, which is where get_free_buddy will
  allocate from. This also eases the conversion to multi-node claim
  usage as memflags in inherently single-node.
---
 xen/common/page_alloc.c | 46 ++++++++++++++++++++++++++++++++++++++---
 1 file changed, 43 insertions(+), 3 deletions(-)

diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c
index 63ecd74dcc..12e1d6a049 100644
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -1027,6 +1027,48 @@ static void init_free_page_fields(struct page_info *pg)
     page_set_owner(pg, NULL);
 }
 
+/*
+ * Check if a heap allocation is allowed (helper for alloc_heap_pages)
+ */
+static bool can_alloc(const struct domain *d, unsigned int memflags,
+                      unsigned long request)
+{
+    nodeid_t node = MEMF_get_node(memflags);
+
+    /*
+     * If memflags don't define a node to allocate from, get_free_buddy() will
+     * use d->node_affinity for the allocation: Allow the allocation to
+     * take advantage of it when the claimed node is exactly d->node_affinity:
+     */
+    if ( node == NUMA_NO_NODE && d && d->claim_node != NUMA_NO_NODE )
+    {
+        nodemask_t claim_node = nodemask_of_node(d->claim_node);
+
+        if (nodes_equal(d->node_affinity, claim_node))
+            node = d->claim_node;
+    }
+
+    if ( outstanding_claims + request <= total_avail_pages && /* host-wide, */
+         (node == NUMA_NO_NODE || /* if the alloc is node-specific, then also */
+          per_node_outstanding_claims[node] + request <= /* check per-node */
+          per_node_avail_pages[node]) )
+        return true;
+
+    /*
+     * The requested allocation can only be satisfied by outstanding claims.
+     * Claimed memory is considered unavailable unless the request
+     * is made by a domain with sufficient unclaimed pages.
+     *
+     * Only allow if the allocation matches the available claims of the domain.
+     * For host-wide allocs and claims, node == d->claim_node == NUMA_NO_NODE.
+     *
+     * Only refcounted allocs attributed to domains may have been claimed:
+     * Not refcounted allocs cannot consume claimed memory.
+     */
+    return d && d->claim_node == node && d->outstanding_pages >= request &&
+           !(memflags & MEMF_no_refcount);
+}
+
 /* Allocate 2^@order contiguous pages. */
 static struct page_info *alloc_heap_pages(
     unsigned int zone_lo, unsigned int zone_hi,
@@ -1057,9 +1099,7 @@ static struct page_info *alloc_heap_pages(
      * Claimed memory is considered unavailable unless the request
      * is made by a domain with sufficient unclaimed pages.
      */
-    if ( (outstanding_claims + request > total_avail_pages) &&
-          ((memflags & MEMF_no_refcount) ||
-           !d || d->outstanding_pages < request) )
+    if ( !can_alloc(d, memflags, request) )
     {
         spin_unlock(&heap_lock);
         return NULL;
-- 
2.43.0



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From: Bernhard Kaindl 
To: xen-devel@lists.xenproject.org
Cc: Bernhard Kaindl ,
	"Daniel P. Smith" ,
	Anthony PERARD ,
	Andrew Cooper ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Juergen Gross ,
	Christian Lindig ,
	David Scott ,
	Alejandro Vallejo 
Subject: [PATCH v2 7/7] xen: New API to claim memory for a domain using XEN_DOMCTL_claim_memory
Date: Sat, 16 Aug 2025 13:19:33 +0200
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Add the new hypercall requested during the review of the v1 series
do not require changing the API for multi-node claims.

The hypercall receives a number of claims, intented to be one claim per
NUMA node, and limited to one claim for now. The changes to update the
NUMA claims management to handle updating the claims for multiple
NUMA nodes of a domain at once are deferred to the next series.

Signed-off-by: Bernhard Kaindl 
Cc: Alejandro Vallejo 
---
 tools/flask/policy/modules/dom0.te  |  1 +
 tools/flask/policy/modules/xen.if   |  1 +
 tools/include/xenctrl.h             |  4 +++
 tools/libs/ctrl/xc_domain.c         | 42 +++++++++++++++++++++++++++++
 tools/ocaml/libs/xc/xenctrl.ml      |  9 +++++++
 tools/ocaml/libs/xc/xenctrl.mli     |  9 +++++++
 tools/ocaml/libs/xc/xenctrl_stubs.c | 21 +++++++++++++++
 xen/common/domain.c                 | 30 +++++++++++++++++++++
 xen/common/domctl.c                 |  8 ++++++
 xen/include/public/domctl.h         | 17 ++++++++++++
 xen/include/xen/domain.h            |  2 ++
 xen/xsm/flask/hooks.c               |  3 +++
 xen/xsm/flask/policy/access_vectors |  2 ++
 13 files changed, 149 insertions(+)

diff --git a/tools/flask/policy/modules/dom0.te b/tools/flask/policy/modules/dom0.te
index ad2b4f9ea7..8801cb24f2 100644
--- a/tools/flask/policy/modules/dom0.te
+++ b/tools/flask/policy/modules/dom0.te
@@ -105,6 +105,7 @@ allow dom0_t dom0_t:domain2 {
 	get_cpu_policy
 	dt_overlay
 	get_domain_state
+	claim_memory
 };
 allow dom0_t dom0_t:resource {
 	add
diff --git a/tools/flask/policy/modules/xen.if b/tools/flask/policy/modules/xen.if
index ef7d8f438c..8e2dceb505 100644
--- a/tools/flask/policy/modules/xen.if
+++ b/tools/flask/policy/modules/xen.if
@@ -98,6 +98,7 @@ define(`create_domain_common', `
 		vuart_op
 		set_llc_colors
 		get_domain_state
+		claim_memory
 	};
 	allow $1 $2:security check_context;
 	allow $1 $2:shadow enable;
diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h
index 4955981231..1059629d94 100644
--- a/tools/include/xenctrl.h
+++ b/tools/include/xenctrl.h
@@ -2660,6 +2660,10 @@ int xc_domain_set_llc_colors(xc_interface *xch, uint32_t domid,
                              const uint32_t *llc_colors,
                              uint32_t num_llc_colors);
 
+int xc_domain_claim_memory(xc_interface *xch, uint32_t domid,
+                           uint32_t nr_claims,
+                           const memory_claim_t *claims);
+
 #if defined(__arm__) || defined(__aarch64__)
 int xc_dt_overlay(xc_interface *xch, void *overlay_fdt,
                   uint32_t overlay_fdt_size, uint8_t overlay_op);
diff --git a/tools/libs/ctrl/xc_domain.c b/tools/libs/ctrl/xc_domain.c
index 2ddc3f4f42..370917d877 100644
--- a/tools/libs/ctrl/xc_domain.c
+++ b/tools/libs/ctrl/xc_domain.c
@@ -2229,6 +2229,48 @@ out:
 
     return ret;
 }
+
+/*
+ * Claim memory for a domain. A Domain can only have one type of claim:
+ *
+ * If the number of claims is 0, existing claims are cancelled.
+ * Updating claims is not supported, cancel the existing claim first.
+ *
+ * Memory allocations consume the outstanding claim and if not enough memory is
+ * free, the allocation must be satisfied from the remaining outstanding claim.
+ */
+int xc_domain_claim_memory(xc_interface *xch, uint32_t domid,
+                           uint32_t nr_claims,
+                           const memory_claim_t *claims)
+{
+    struct xen_domctl domctl = {
+        .cmd = XEN_DOMCTL_claim_memory,
+        .domain = domid,
+        .u.claim_memory.nr_claims = nr_claims,
+    };
+    int ret;
+    DECLARE_HYPERCALL_BUFFER(struct xen_domctl_claim_memory, buffer);
+
+    /* Use an array to not need changes for multi-node claims in the future */
+    if ( nr_claims )
+    {
+        size_t bytes = sizeof(memory_claim_t) * nr_claims;
+
+        buffer = xc_hypercall_buffer_alloc(xch, buffer, bytes);
+        if ( buffer == NULL )
+        {
+            PERROR("Could not allocate memory for xc_domain_claim_memory");
+            return -1;
+        }
+        memcpy(buffer, claims, bytes);
+        set_xen_guest_handle(domctl.u.claim_memory.claims, buffer);
+    }
+
+    ret = do_domctl(xch, &domctl);
+    xc_hypercall_buffer_free(xch, buffer);
+    return ret;
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/tools/ocaml/libs/xc/xenctrl.ml b/tools/ocaml/libs/xc/xenctrl.ml
index 7e1aabad6c..cb1c18481b 100644
--- a/tools/ocaml/libs/xc/xenctrl.ml
+++ b/tools/ocaml/libs/xc/xenctrl.ml
@@ -369,6 +369,15 @@ external domain_deassign_device: handle -> domid -> (int * int * int * int) -> u
 external domain_test_assign_device: handle -> domid -> (int * int * int * int) -> bool
   = "stub_xc_domain_test_assign_device"
 
+type claim =
+  {
+    node: int;
+    nr_pages: int64;
+  }
+
+external domain_claim_memory: handle -> domid -> int -> claim array -> unit
+  = "stub_xc_domain_claim_memory"
+
 external version: handle -> version = "stub_xc_version_version"
 external version_compile_info: handle -> compile_info
   = "stub_xc_version_compile_info"
diff --git a/tools/ocaml/libs/xc/xenctrl.mli b/tools/ocaml/libs/xc/xenctrl.mli
index f44dba61ae..32786a5f7f 100644
--- a/tools/ocaml/libs/xc/xenctrl.mli
+++ b/tools/ocaml/libs/xc/xenctrl.mli
@@ -296,6 +296,15 @@ external domain_deassign_device: handle -> domid -> (int * int * int * int) -> u
 external domain_test_assign_device: handle -> domid -> (int * int * int * int) -> bool
   = "stub_xc_domain_test_assign_device"
 
+type claim =
+  {
+    node: int;
+    nr_pages: int64;
+  }
+
+external domain_claim_memory: handle -> domid -> int -> claim array -> unit
+  = "stub_xc_domain_claim_memory"
+
 external version : handle -> version = "stub_xc_version_version"
 external version_compile_info : handle -> compile_info
   = "stub_xc_version_compile_info"
diff --git a/tools/ocaml/libs/xc/xenctrl_stubs.c b/tools/ocaml/libs/xc/xenctrl_stubs.c
index b51fd66788..c27e6c4683 100644
--- a/tools/ocaml/libs/xc/xenctrl_stubs.c
+++ b/tools/ocaml/libs/xc/xenctrl_stubs.c
@@ -1424,6 +1424,27 @@ CAMLprim value stub_xc_watchdog(value xch_val, value domid, value timeout)
 	CAMLreturn(Val_int(ret));
 }
 
+/* Claim memory for a domain. See xc_domain_claim_memory() for details. */
+CAMLprim value stub_xc_domain_claim_memory(value xch_val, value domid,
+                                           value num_claims, value desc)
+{
+	CAMLparam4(xch_val, domid, num_claims, desc);
+	xc_interface *xch = xch_of_val(xch_val);
+	int i, retval, nr_claims = Int_val(num_claims);
+	memory_claim_t claim[nr_claims];
+
+	for (i = 0; i < nr_claims; i++) {
+		claim[i].node = Int_val(Field(desc, i*2));
+		claim[i].nr_pages = Int64_val(Field(desc, i*2 + 1));
+	}
+
+	retval = xc_domain_claim_memory(xch, Int_val(domid), nr_claims, claim);
+	if (retval < 0)
+		failwith_xc(xch);
+
+	CAMLreturn(Val_unit);
+}
+
 /*
  * Local variables:
  *  indent-tabs-mode: t
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 1beadb05e1..dcfad4ab15 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -267,6 +267,36 @@ int get_domain_state(struct xen_domctl_get_domain_state *info, struct domain *d,
     return rc;
 }
 
+/* XEN_DOMCTL_claim_memory: Claim an amount of memory for a domain */
+int claim_memory(struct domain *d, const struct xen_domctl_claim_memory *uinfo)
+{
+    memory_claim_t claim;
+    int rc;
+
+    switch ( uinfo->nr_claims )
+    {
+        case 0:
+            /* Cancel existing claim. */
+            rc = domain_set_outstanding_pages(d, 0, 0);
+            break;
+
+        case 1:
+            /* Only single node claims supported at the moment. */
+            if ( copy_from_guest(&claim, uinfo->claims, 1) )
+                return -EFAULT;
+
+            rc = domain_set_outstanding_pages(d, claim.node,
+                                              claim.nr_pages);
+            break;
+
+        default:
+            rc = -EOPNOTSUPP;
+            break;
+    }
+
+    return rc;
+}
+
 static void __domain_finalise_shutdown(struct domain *d)
 {
     struct vcpu *v;
diff --git a/xen/common/domctl.c b/xen/common/domctl.c
index f2a7caaf85..e7576ae00b 100644
--- a/xen/common/domctl.c
+++ b/xen/common/domctl.c
@@ -894,6 +894,14 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl)
         ret = get_domain_state(&op->u.get_domain_state, d, &op->domain);
         break;
 
+    case XEN_DOMCTL_claim_memory:
+        ret = xsm_claim_pages(XSM_PRIV, d);
+        if ( ret )
+            break;
+
+        ret = claim_memory(d, &op->u.claim_memory);
+        break;
+
     default:
         ret = arch_do_domctl(op, d, u_domctl);
         break;
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 0c75d9d27f..5e924abd85 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1273,6 +1273,21 @@ struct xen_domctl_get_domain_state {
     uint64_t unique_id;      /* Unique domain identifier. */
 };
 
+struct xen_memory_claim {
+    unsigned int node;      /* NUMA node, XC_NUMA_NO_NODE for a host claim */
+    unsigned long nr_pages; /* Number of pages to claim */
+};
+typedef struct xen_memory_claim memory_claim_t;
+DEFINE_XEN_GUEST_HANDLE(memory_claim_t);
+
+/* XEN_DOMCTL_claim_memory: Claim an amount of memory for a domain */
+struct xen_domctl_claim_memory {
+    /* IN: array of memory claims */
+    XEN_GUEST_HANDLE_64(memory_claim_t) claims;
+    /* IN: number of claims */
+    unsigned int nr_claims;
+};
+
 struct xen_domctl {
 /* Stable domctl ops: interface_version is required to be 0.  */
     uint32_t cmd;
@@ -1365,6 +1380,7 @@ struct xen_domctl {
 #define XEN_DOMCTL_gsi_permission                88
 #define XEN_DOMCTL_set_llc_colors                89
 #define XEN_DOMCTL_get_domain_state              90 /* stable interface */
+#define XEN_DOMCTL_claim_memory                  91
 #define XEN_DOMCTL_gdbsx_guestmemio            1000
 #define XEN_DOMCTL_gdbsx_pausevcpu             1001
 #define XEN_DOMCTL_gdbsx_unpausevcpu           1002
@@ -1433,6 +1449,7 @@ struct xen_domctl {
 #endif
         struct xen_domctl_set_llc_colors    set_llc_colors;
         struct xen_domctl_get_domain_state  get_domain_state;
+        struct xen_domctl_claim_memory      claim_memory;
         uint8_t                             pad[128];
     } u;
 };
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615..bd5f37bd64 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -192,4 +192,6 @@ extern bool vmtrace_available;
 
 extern bool vpmu_is_available;
 
+int claim_memory(struct domain *d, const struct xen_domctl_claim_memory *uinfo);
+
 #endif /* __XEN_DOMAIN_H__ */
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index b0308e1b26..6b2535b666 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -853,6 +853,9 @@ static int cf_check flask_domctl(struct domain *d, unsigned int cmd,
     case XEN_DOMCTL_set_llc_colors:
         return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SET_LLC_COLORS);
 
+    case XEN_DOMCTL_claim_memory:
+        return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__CLAIM_MEMORY);
+
     default:
         return avc_unknown_permission("domctl", cmd);
     }
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 51a1577a66..87338b5c2a 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -259,6 +259,8 @@ class domain2
     set_llc_colors
 # XEN_DOMCTL_get_domain_state
     get_domain_state
+# XEN_DOMCTL_claim_memory
+    claim_memory
 }
 
 # Similar to class domain, but primarily contains domctls related to HVM domains
-- 
2.43.0



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From: Bernhard Kaindl 
To: xen-devel@lists.xenproject.org
Cc: Bernhard Kaindl ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini ,
	Alejandro Vallejo 
Subject: [PATCH v2 3/7] xen/page_alloc: Add static per-NUMA-node counts of free pages
Date: Sat, 16 Aug 2025 13:19:29 +0200
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The static per-NUMA-node count of free pages is the sum of free memory
in all zones of a node. It's an optimisation to avoid doing that operation
frequently in the following patches that introduce per-NUMA-node claims.

---
Changed since v1:
- Added ASSERT(per_node_avail_pages[node] >= request) as requested
  during review by Roger: Comment by me: As we have
  ASSERT(avail[node][zone] >= request);
  directly before it, request is already valid, so this checks
  that per_node_avail_pages[node] is not mis-accounted too low.

Signed-off-by: Bernhard Kaindl 
Signed-off-by: Alejandro Vallejo 
---
 xen/common/page_alloc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c
index 7e90b9cc1e..43de9296fd 100644
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -486,6 +486,9 @@ static unsigned long node_need_scrub[MAX_NUMNODES];
 static unsigned long *avail[MAX_NUMNODES];
 static long total_avail_pages;
 
+/* Per-NUMA-node counts of free pages */
+static unsigned long per_node_avail_pages[MAX_NUMNODES];
+
 static DEFINE_SPINLOCK(heap_lock);
 static long outstanding_claims; /* total outstanding claims by all domains */
 
@@ -1066,6 +1069,8 @@ static struct page_info *alloc_heap_pages(
 
     ASSERT(avail[node][zone] >= request);
     avail[node][zone] -= request;
+    ASSERT(per_node_avail_pages[node] >= request);
+    per_node_avail_pages[node] -= request;
     total_avail_pages -= request;
     ASSERT(total_avail_pages >= 0);
 
@@ -1226,6 +1231,8 @@ static int reserve_offlined_page(struct page_info *head)
             continue;
 
         avail[node][zone]--;
+        ASSERT(per_node_avail_pages[node] > 0);
+        per_node_avail_pages[node]--;
         total_avail_pages--;
         ASSERT(total_avail_pages >= 0);
 
@@ -1550,6 +1557,7 @@ static void free_heap_pages(
     }
 
     avail[node][zone] += 1 << order;
+    per_node_avail_pages[node] += 1 << order;
     total_avail_pages += 1 << order;
     if ( need_scrub )
     {
-- 
2.43.0



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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Andrew Cooper , Jan Beulich
	, =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Anthony PERARD , Michal
 Orzel , Julien Grall , Stefano
 Stabellini , Dmytro Prokopchuk1
	
Subject: [PATCH v2] xen/irq: Delete the pirq_cleanup_check() macro
Thread-Topic: [PATCH v2] xen/irq: Delete the pirq_cleanup_check() macro
Thread-Index: AQHcDss9HzeZqtz/Tk6XtiCEDCCXBQ==
Date: Sat, 16 Aug 2025 16:31:38 +0000
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From: Andrew Cooper 

MISRA Rule 5.5 objects to a macro aliasing a function, which is what
pirq_cleanup_check() does. The macro was originally intended to ensure
the condition 'if (!pirq->evtchn)' is always checked before invoking
the function, avoiding errors across call sites.

To achieve MISRA compliance, the condition is expanded inline at all
call sites, using plain C constructs. This ensures clarity while
retaining the original behavior. While this complies with MISRA, it
shifts the responsibility to developers to check 'if (!pirq->evtchn)'
at call sites.

No functional changes.

Signed-off-by: Andrew Cooper 
Signed-off-by: Dmytro Prokopchuk 
---
Link to v1:
https://patchew.org/Xen/20250729223110.3404441-1-andrew.cooper3@citrix.com/

Changes in v2:
- updated commit message
---
 xen/arch/x86/irq.c                | 11 +++++++----
 xen/common/event_channel.c        |  5 ++++-
 xen/drivers/passthrough/x86/hvm.c |  9 ++++++---
 xen/include/xen/irq.h             |  3 ---
 4 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c
index 556134f85a..1ed85c0c11 100644
--- a/xen/arch/x86/irq.c
+++ b/xen/arch/x86/irq.c
@@ -1325,7 +1325,8 @@ static void clear_domain_irq_pirq(struct domain *d, i=
nt irq, struct pirq *pirq)
 static void cleanup_domain_irq_pirq(struct domain *d, int irq,
                                     struct pirq *pirq)
 {
-    pirq_cleanup_check(pirq, d);
+    if ( !pirq->evtchn )
+        pirq_cleanup_check(pirq, d);
     radix_tree_delete(&d->arch.irq_pirq, irq);
 }
=20
@@ -1383,7 +1384,7 @@ struct pirq *alloc_pirq_struct(struct domain *d)
     return pirq;
 }
=20
-void (pirq_cleanup_check)(struct pirq *pirq, struct domain *d)
+void pirq_cleanup_check(struct pirq *pirq, struct domain *d)
 {
     /*
      * Check whether all fields have their default values, and delete
@@ -2823,7 +2824,8 @@ int map_domain_emuirq_pirq(struct domain *d, int pirq=
, int emuirq)
                 radix_tree_int_to_ptr(pirq));
             break;
         default:
-            pirq_cleanup_check(info, d);
+            if ( !info->evtchn )
+                pirq_cleanup_check(info, d);
             return err;
         }
     }
@@ -2858,7 +2860,8 @@ int unmap_domain_pirq_emuirq(struct domain *d, int pi=
rq)
     if ( info )
     {
         info->arch.hvm.emuirq =3D IRQ_UNBOUND;
-        pirq_cleanup_check(info, d);
+        if ( !info->evtchn )
+            pirq_cleanup_check(info, d);
     }
     if ( emuirq !=3D IRQ_PT )
         radix_tree_delete(&d->arch.hvm.emuirq_pirq, emuirq);
diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index 67700b050a..a3d18bc464 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -741,11 +741,14 @@ int evtchn_close(struct domain *d1, int port1, bool g=
uest)
             if ( !is_hvm_domain(d1) ||
                  domain_pirq_to_irq(d1, pirq->pirq) <=3D 0 ||
                  unmap_domain_pirq_emuirq(d1, pirq->pirq) < 0 )
+            {
                 /*
                  * The successful path of unmap_domain_pirq_emuirq() will =
have
                  * called pirq_cleanup_check() already.
                  */
-                pirq_cleanup_check(pirq, d1);
+                if ( !pirq->evtchn )
+                    pirq_cleanup_check(pirq, d1);
+            }
         }
         unlink_pirq_port(chn1, d1->vcpu[chn1->notify_vcpu_id]);
         break;
diff --git a/xen/drivers/passthrough/x86/hvm.c b/xen/drivers/passthrough/x8=
6/hvm.c
index a2ca7e0e57..b73bb55055 100644
--- a/xen/drivers/passthrough/x86/hvm.c
+++ b/xen/drivers/passthrough/x86/hvm.c
@@ -329,7 +329,8 @@ int pt_irq_create_bind(
                 pirq_dpci->gmsi.gvec =3D 0;
                 pirq_dpci->dom =3D NULL;
                 pirq_dpci->flags =3D 0;
-                pirq_cleanup_check(info, d);
+                if ( !info->evtchn )
+                    pirq_cleanup_check(info, d);
                 write_unlock(&d->event_lock);
                 return rc;
             }
@@ -536,7 +537,8 @@ int pt_irq_create_bind(
                     hvm_irq_dpci->link_cnt[link]--;
                 }
                 pirq_dpci->flags =3D 0;
-                pirq_cleanup_check(info, d);
+                if ( !info->evtchn )
+                    pirq_cleanup_check(info, d);
                 write_unlock(&d->event_lock);
                 xfree(girq);
                 xfree(digl);
@@ -693,7 +695,8 @@ int pt_irq_destroy_bind(
          */
         pt_pirq_softirq_reset(pirq_dpci);
=20
-        pirq_cleanup_check(pirq, d);
+        if ( !pirq->evtchn )
+            pirq_cleanup_check(pirq, d);
     }
=20
     write_unlock(&d->event_lock);
diff --git a/xen/include/xen/irq.h b/xen/include/xen/irq.h
index 95034c0d6b..6071b00f62 100644
--- a/xen/include/xen/irq.h
+++ b/xen/include/xen/irq.h
@@ -185,9 +185,6 @@ extern struct pirq *pirq_get_info(struct domain *d, int=
 pirq);
=20
 void pirq_cleanup_check(struct pirq *pirq, struct domain *d);
=20
-#define pirq_cleanup_check(pirq, d) \
-    (!(pirq)->evtchn ? pirq_cleanup_check(pirq, d) : (void)0)
-
 extern void pirq_guest_eoi(struct pirq *pirq);
 extern void desc_guest_eoi(struct irq_desc *desc, struct pirq *pirq);
 extern int pirq_guest_unmask(struct domain *d);
--=20
2.43.0


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From: pratyush.brahma@oss.qualcomm.com
X-Google-Original-From: Pratyush
Date: Mon, 18 Aug 2025 12:11:15 +0530
Subject: [PATCH] mm/numa: Rename memory_add_physaddr_to_nid to
 memory_get_phys_to_nid
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From: Pratyush Brahma 

The function `memory_add_physaddr_to_nid` seems a misnomer.
It does not to "add" a physical address to a NID mapping,
but rather it gets the NID associated with a given physical address.

Improve the semantic clarity of the API by renaming to a more
descriptive name.

Signed-off-by: Pratyush Brahma 
---
 arch/powerpc/include/asm/sparsemem.h | 4 ++--
 arch/powerpc/mm/mem.c                | 4 ++--
 arch/s390/include/asm/sparsemem.h    | 4 ++--
 drivers/acpi/acpi_memhotplug.c       | 2 +-
 drivers/acpi/nfit/core.c             | 2 +-
 drivers/base/memory.c                | 2 +-
 drivers/cxl/pmem.c                   | 2 +-
 drivers/dax/cxl.c                    | 2 +-
 drivers/hv/hv_balloon.c              | 6 +++---
 drivers/nvdimm/virtio_pmem.c         | 2 +-
 drivers/virtio/virtio_mem.c          | 2 +-
 drivers/xen/balloon.c                | 2 +-
 include/linux/numa.h                 | 6 +++---
 include/linux/numa_memblks.h         | 4 ++--
 mm/numa.c                            | 6 +++---
 mm/numa_memblks.c                    | 4 ++--
 16 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
index d072866842e4229159fcb6635745fd19a2788413..cdb5594616c8e32ab8ae3d209d0b2df20f3564f6 100644
--- a/arch/powerpc/include/asm/sparsemem.h
+++ b/arch/powerpc/include/asm/sparsemem.h
@@ -14,8 +14,8 @@
 
 #ifdef CONFIG_MEMORY_HOTPLUG
 extern int remove_section_mapping(unsigned long start, unsigned long end);
-extern int memory_add_physaddr_to_nid(u64 start);
-#define memory_add_physaddr_to_nid memory_add_physaddr_to_nid
+extern int memory_get_phys_to_nid(u64 start);
+#define memory_get_phys_to_nid memory_get_phys_to_nid
 
 #ifdef CONFIG_NUMA
 extern int hot_add_scn_to_nid(unsigned long scn_addr);
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 3ddbfdbfa9413a17d8321885724ce432d967005a..5665b2e2fc68df8634613c11706e1a9158a3a616 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -54,11 +54,11 @@ EXPORT_SYMBOL(__phys_mem_access_prot);
 static DEFINE_MUTEX(linear_mapping_mutex);
 
 #ifdef CONFIG_NUMA
-int memory_add_physaddr_to_nid(u64 start)
+int memory_get_phys_to_nid(u64 start)
 {
 	return hot_add_scn_to_nid(start);
 }
-EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
+EXPORT_SYMBOL_GPL(memory_get_phys_to_nid);
 #endif
 
 int __weak create_section_mapping(unsigned long start, unsigned long end,
diff --git a/arch/s390/include/asm/sparsemem.h b/arch/s390/include/asm/sparsemem.h
index 668dfc5de538742269af1b25151372506105fd4d..744c67dce4c106d063cb5436b37412045da0fd2a 100644
--- a/arch/s390/include/asm/sparsemem.h
+++ b/arch/s390/include/asm/sparsemem.h
@@ -7,11 +7,11 @@
 
 #ifdef CONFIG_NUMA
 
-static inline int memory_add_physaddr_to_nid(u64 addr)
+static inline int memory_get_phys_to_nid(u64 addr)
 {
 	return 0;
 }
-#define memory_add_physaddr_to_nid memory_add_physaddr_to_nid
+#define memory_get_phys_to_nid memory_get_phys_to_nid
 
 static inline int phys_to_target_node(u64 start)
 {
diff --git a/drivers/acpi/acpi_memhotplug.c b/drivers/acpi/acpi_memhotplug.c
index d0c1a71007d0a3054608bec8fddc8e86bdffb78b..6f968243ffc3cc5864e73b914d1bf67748e30e66 100644
--- a/drivers/acpi/acpi_memhotplug.c
+++ b/drivers/acpi/acpi_memhotplug.c
@@ -183,7 +183,7 @@ static int acpi_memory_enable_device(struct acpi_memory_device *mem_device)
 			continue;
 		/* We want a single node for the whole memory group */
 		if (node < 0)
-			node = memory_add_physaddr_to_nid(info->start_addr);
+			node = memory_get_phys_to_nid(info->start_addr);
 		total_length += info->length;
 	}
 
diff --git a/drivers/acpi/nfit/core.c b/drivers/acpi/nfit/core.c
index ae035b93da087812dee6ec47d9ef4aa97dc8e7bc..04c3ab311e4d5923aef50252efabd193c5fb7850 100644
--- a/drivers/acpi/nfit/core.c
+++ b/drivers/acpi/nfit/core.c
@@ -2630,7 +2630,7 @@ static int acpi_nfit_register_region(struct acpi_nfit_desc *acpi_desc,
 
 	/* Fallback to address based numa information if node lookup failed */
 	if (ndr_desc->numa_node == NUMA_NO_NODE) {
-		ndr_desc->numa_node = memory_add_physaddr_to_nid(spa->address);
+		ndr_desc->numa_node = memory_get_phys_to_nid(spa->address);
 		dev_info(acpi_desc->dev, "changing numa node from %d to %d for nfit region [%pa-%pa]",
 			NUMA_NO_NODE, ndr_desc->numa_node, &res.start, &res.end);
 	}
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index 5c6c1d6bb59f1241a5f42a3396be1a8e2058c965..f657520855408804761afec379e3c0b2a238b239 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -599,7 +599,7 @@ static ssize_t probe_store(struct device *dev, struct device_attribute *attr,
 	if (ret)
 		return ret;
 
-	nid = memory_add_physaddr_to_nid(phys_addr);
+	nid = memory_get_phys_to_nid(phys_addr);
 	ret = __add_memory(nid, phys_addr,
 			   MIN_MEMORY_BLOCK_SIZE * sections_per_block,
 			   MHP_NONE);
diff --git a/drivers/cxl/pmem.c b/drivers/cxl/pmem.c
index e197883690efc11f60c31bd56aeb5695665d422b..471aed4e11241948e994d0b9d53600c147e38fb0 100644
--- a/drivers/cxl/pmem.c
+++ b/drivers/cxl/pmem.c
@@ -410,7 +410,7 @@ static int cxl_pmem_region_probe(struct device *dev)
 	ndr_desc.res = res;
 	ndr_desc.provider_data = cxlr_pmem;
 
-	ndr_desc.numa_node = memory_add_physaddr_to_nid(res->start);
+	ndr_desc.numa_node = memory_get_phys_to_nid(res->start);
 	ndr_desc.target_node = phys_to_target_node(res->start);
 	if (ndr_desc.target_node == NUMA_NO_NODE) {
 		ndr_desc.target_node = ndr_desc.numa_node;
diff --git a/drivers/dax/cxl.c b/drivers/dax/cxl.c
index 13cd94d32ff7a1d70af7821c1aecd7490302149d..35843791872ba466f571c022e1484816368a1198 100644
--- a/drivers/dax/cxl.c
+++ b/drivers/dax/cxl.c
@@ -15,7 +15,7 @@ static int cxl_dax_region_probe(struct device *dev)
 	struct dev_dax_data data;
 
 	if (nid == NUMA_NO_NODE)
-		nid = memory_add_physaddr_to_nid(cxlr_dax->hpa_range.start);
+		nid = memory_get_phys_to_nid(cxlr_dax->hpa_range.start);
 
 	dax_region = alloc_dax_region(dev, cxlr->id, &cxlr_dax->hpa_range, nid,
 				      PMD_SIZE, IORESOURCE_DAX_KMEM);
diff --git a/drivers/hv/hv_balloon.c b/drivers/hv/hv_balloon.c
index 2b4080e51f97c30e7adb06faa56b1403bc08b53c..8878aac6da9cd3bd6f499eae2588e989b7219af3 100644
--- a/drivers/hv/hv_balloon.c
+++ b/drivers/hv/hv_balloon.c
@@ -725,7 +725,7 @@ static void hv_mem_hot_add(unsigned long start, unsigned long size,
 
 		reinit_completion(&dm_device.ol_waitevent);
 
-		nid = memory_add_physaddr_to_nid(PFN_PHYS(start_pfn));
+		nid = memory_get_phys_to_nid(PFN_PHYS(start_pfn));
 		ret = add_memory(nid, PFN_PHYS((start_pfn)),
 				 HA_BYTES_IN_CHUNK, MHP_MERGE_RESOURCE);
 
@@ -1701,8 +1701,8 @@ static int hot_add_enabled(void)
 {
 	/*
 	 * Disable hot add on ARM64, because we currently rely on
-	 * memory_add_physaddr_to_nid() to get a node id of a hot add range,
-	 * however ARM64's memory_add_physaddr_to_nid() always return 0 and
+	 * memory_get_phys_to_nid() to get a node id of a hot add range,
+	 * however ARM64's memory_get_phys_to_nid() always return 0 and
 	 * DM_MEM_HOT_ADD_REQUEST doesn't have the NUMA node information for
 	 * add_memory().
 	 */
diff --git a/drivers/nvdimm/virtio_pmem.c b/drivers/nvdimm/virtio_pmem.c
index 2396d19ce5496974f8b93b54cc8c95e48dda103d..df6a3fd552d11a577d85708f80e7558ea83839d2 100644
--- a/drivers/nvdimm/virtio_pmem.c
+++ b/drivers/nvdimm/virtio_pmem.c
@@ -100,7 +100,7 @@ static int virtio_pmem_probe(struct virtio_device *vdev)
 
 	ndr_desc.res = &res;
 
-	ndr_desc.numa_node = memory_add_physaddr_to_nid(res.start);
+	ndr_desc.numa_node = memory_get_phys_to_nid(res.start);
 	ndr_desc.target_node = phys_to_target_node(res.start);
 	if (ndr_desc.target_node == NUMA_NO_NODE) {
 		ndr_desc.target_node = ndr_desc.numa_node;
diff --git a/drivers/virtio/virtio_mem.c b/drivers/virtio/virtio_mem.c
index 1688ecd69a0445d5c21d108a9a1d60577f96d7ac..6154f03a12c3efa65728f626e43b6270245d439c 100644
--- a/drivers/virtio/virtio_mem.c
+++ b/drivers/virtio/virtio_mem.c
@@ -2858,7 +2858,7 @@ static int virtio_mem_init(struct virtio_mem *vm)
 
 	/* Determine the nid for the device based on the lowest address. */
 	if (vm->nid == NUMA_NO_NODE)
-		vm->nid = memory_add_physaddr_to_nid(vm->addr);
+		vm->nid = memory_get_phys_to_nid(vm->addr);
 
 	dev_info(&vm->vdev->dev, "start address: 0x%llx", vm->addr);
 	dev_info(&vm->vdev->dev, "region size: 0x%llx", vm->region_size);
diff --git a/drivers/xen/balloon.c b/drivers/xen/balloon.c
index 2de37dcd75566fc1a03b75232cbe17fc0f53909d..93ca270ddd516ec11bc3f096eb518b9789d92664 100644
--- a/drivers/xen/balloon.c
+++ b/drivers/xen/balloon.c
@@ -284,7 +284,7 @@ static enum bp_state reserve_additional_memory(void)
 	if (!resource)
 		goto err;
 
-	nid = memory_add_physaddr_to_nid(resource->start);
+	nid = memory_get_phys_to_nid(resource->start);
 
 #ifdef CONFIG_XEN_HAVE_PVMMU
 	/*
diff --git a/include/linux/numa.h b/include/linux/numa.h
index e6baaf6051bcff6c23308d3b67f790053fbd29dc..ed65a20f39718a5a3157f6f9db60561f4418b000 100644
--- a/include/linux/numa.h
+++ b/include/linux/numa.h
@@ -33,8 +33,8 @@ int numa_nearest_node(int node, unsigned int state);
 
 int nearest_node_nodemask(int node, nodemask_t *mask);
 
-#ifndef memory_add_physaddr_to_nid
-int memory_add_physaddr_to_nid(u64 start);
+#ifndef memory_get_phys_to_nid
+int memory_get_phys_to_nid(u64 start);
 #endif
 
 #ifndef phys_to_target_node
@@ -54,7 +54,7 @@ static inline int nearest_node_nodemask(int node, nodemask_t *mask)
 	return NUMA_NO_NODE;
 }
 
-static inline int memory_add_physaddr_to_nid(u64 start)
+static inline int memory_get_phys_to_nid(u64 start)
 {
 	return 0;
 }
diff --git a/include/linux/numa_memblks.h b/include/linux/numa_memblks.h
index 991076cba7c5016d845eb40a2f9887f73fa83862..37cc0987e738f8aa2eb5c8f1ca2c94394def4780 100644
--- a/include/linux/numa_memblks.h
+++ b/include/linux/numa_memblks.h
@@ -53,8 +53,8 @@ static inline int numa_emu_cmdline(char *str)
 #ifdef CONFIG_NUMA_KEEP_MEMINFO
 extern int phys_to_target_node(u64 start);
 #define phys_to_target_node phys_to_target_node
-extern int memory_add_physaddr_to_nid(u64 start);
-#define memory_add_physaddr_to_nid memory_add_physaddr_to_nid
+extern int memory_get_phys_to_nid(u64 start);
+#define memory_get_phys_to_nid memory_get_phys_to_nid
 #endif /* CONFIG_NUMA_KEEP_MEMINFO */
 
 #endif /* CONFIG_NUMA_MEMBLKS */
diff --git a/mm/numa.c b/mm/numa.c
index 7d5e06fe5bd4a2790b83dd7dbe646617f6476d8c..f7b5ac8aea608368b75c606970187eb147ddf427 100644
--- a/mm/numa.c
+++ b/mm/numa.c
@@ -40,14 +40,14 @@ void __init alloc_offline_node_data(int nid)
 
 /* Stub functions: */
 
-#ifndef memory_add_physaddr_to_nid
-int memory_add_physaddr_to_nid(u64 start)
+#ifndef memory_get_phys_to_nid
+int memory_get_phys_to_nid(u64 start)
 {
 	pr_info_once("Unknown online node for memory at 0x%llx, assuming node 0\n",
 			start);
 	return 0;
 }
-EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
+EXPORT_SYMBOL_GPL(memory_get_phys_to_nid);
 #endif
 
 #ifndef phys_to_target_node
diff --git a/mm/numa_memblks.c b/mm/numa_memblks.c
index 541a99c4071a67e5b0ef66f4136dee268a880003..346039bd933390fb014931fc61ccd2f96a773c37 100644
--- a/mm/numa_memblks.c
+++ b/mm/numa_memblks.c
@@ -580,7 +580,7 @@ int phys_to_target_node(u64 start)
 }
 EXPORT_SYMBOL_GPL(phys_to_target_node);
 
-int memory_add_physaddr_to_nid(u64 start)
+int memory_get_phys_to_nid(u64 start)
 {
 	int nid = meminfo_to_nid(&numa_meminfo, start);
 
@@ -588,6 +588,6 @@ int memory_add_physaddr_to_nid(u64 start)
 		nid = numa_meminfo.blk[0].nid;
 	return nid;
 }
-EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
+EXPORT_SYMBOL_GPL(memory_get_phys_to_nid);
 
 #endif /* CONFIG_NUMA_KEEP_MEMINFO */

---
base-commit: 479058002c32b77acac43e883b92174e22c4be2d
change-id: 20250814-numa_memblks-b54a878820de

Best regards,
-- 
Pratyush Brahma 



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Date: Mon, 18 Aug 2025 08:58:59 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH] mm/numa: Rename memory_add_physaddr_to_nid to
 memory_get_phys_to_nid
To: pratyush.brahma@oss.qualcomm.com,
 Madhavan Srinivasan ,
 Michael Ellerman , Nicholas Piggin ,
 Christophe Leroy ,
 Heiko Carstens , Vasily Gorbik ,
 Alexander Gordeev ,
 Christian Borntraeger ,
 Sven Schnelle , "Rafael J. Wysocki"
 , Len Brown ,
 Dan Williams ,
 Vishal Verma , Dave Jiang ,
 Ira Weiny , Oscar Salvador ,
 Greg Kroah-Hartman ,
 Danilo Krummrich , Davidlohr Bueso ,
 Jonathan Cameron ,
 Alison Schofield ,
 "K. Y. Srinivasan" ,
 Haiyang Zhang , Wei Liu ,
 Dexuan Cui , Pankaj Gupta
 , "Michael S. Tsirkin" ,
 Jason Wang , Xuan Zhuo ,
 =?UTF-8?Q?Eugenio_P=C3=A9rez?= ,
 Juergen Gross , Stefano Stabellini
 ,
 Oleksandr Tyshchenko ,
 Andrew Morton , Mike Rapoport 
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
 linux-s390@vger.kernel.org, linux-acpi@vger.kernel.org,
 nvdimm@lists.linux.dev, linux-mm@kvack.org, linux-cxl@vger.kernel.org,
 linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev,
 xen-devel@lists.xenproject.org
References: <20250818-numa_memblks-v1-1-9eb29ade560a@oss.qualcomm.com>
From: David Hildenbrand 
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On 18.08.25 08:41, pratyush.brahma@oss.qualcomm.com wrote:
> From: Pratyush Brahma 
> 
> The function `memory_add_physaddr_to_nid` seems a misnomer.
> It does not to "add" a physical address to a NID mapping,
> but rather it gets the NID associated with a given physical address.

You probably misunderstood what the function is used for: memory hotplug 
aka "memory_add".

This patch is making matters worse by stripping that detail, unfortunately.


-- 
Cheers

David / dhildenb



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Date: Mon, 18 Aug 2025 09:38:15 +0200
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Subject: Re: [PATCH v2] docs/misra: fix sphinx-build issues
To: Dmytro Prokopchuk1 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Nicola Vetrini ,
 "xen-devel@lists.xenproject.org" 
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On 15.08.2025 16:15, Dmytro Prokopchuk1 wrote:
> Fix the following issues:
> 1. xen/docs/misra/deviations.rst:90: WARNING: Inline interpreted text or
> phrase reference start-string without end-string. [docutils]
> 2. xen/docs/misra/deviations.rst:54: ERROR: Error parsing content block
> for the "list-table" directive: uniform two-level bullet list expected,
> but row 6 does not contain the same number of items as row 1 (2 vs 3).
> * - R2.1
>   - Calls to the `__builtin_unreachable()` function inside the expansion of
>     the `ASSERT_UNREACHABLE()` macro may cause a function to be marked as
>     non-returning. This behavior occurs only in configurations where
>     assertions are enabled. To address this, the `noreturn` property for
>     `__builtin_unreachable()` is overridden in these contexts, resulting in
>     the absence of reports that do not have an impact on safety, despite
>     being true positives.
>     Xen expects developers to ensure code remains safe and reliable in builds,
>     even when debug-only assertions like `ASSERT_UNREACHABLE() are removed.
> 3. xen/docs/misra/rules.rst:127: WARNING: Inline interpreted text or phrase
> reference start-string without end-string. [docutils]
> 4. remove backticks from references to source code in the file rules.rst
> to have a consistent style in this file

I don't understand this: For one, why remove quotation? Personally I
consider such quoting useful. And then ...

> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -95,7 +95,8 @@ Deviations related to MISRA C:2012 Rules:
>         the absence of reports that do not have an impact on safety, despite
>         being true positives.
>         Xen expects developers to ensure code remains safe and reliable in builds,
> -       even when debug-only assertions like `ASSERT_UNREACHABLE() are removed.
> +       even when debug-only assertions like `ASSERT_UNREACHABLE()` are removed.
> +     - ECLAIR has been configured to ignore those statements.

... backticks are still kept here (kind of in line with what you say in
4, but still somewhat puzzling). Whereas what you remove ...

> --- a/docs/misra/rules.rst
> +++ b/docs/misra/rules.rst
> @@ -119,12 +119,12 @@ maintainers if you want to suggest a change.
>           - Switch with a controlling value statically determined not to
>             match one or more case statements
>           - Functions that are intended to be referenced only from
> -           assembly code (e.g. 'do_trap_fiq')
> +           assembly code (e.g. do_trap_fiq)

... e.g. here are single quotes.

Jan


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Date: Mon, 18 Aug 2025 09:42:36 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Stewart Hildebrand 
Cc: xen-devel@lists.xenproject.org, Jiqian.Chen@amd.com, jbeulich@suse.com
Subject: Re: [PATCH 2/5] xen/vpci: make BAR mapping more resilient for the
 hardware domain
Message-ID: 
References: <20250814160358.95543-1-roger.pau@citrix.com>
 <20250814160358.95543-3-roger.pau@citrix.com>
 <269db2aa-9ca1-446b-98f7-60ea2386fc03@amd.com>
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On Fri, Aug 15, 2025 at 02:53:35PM -0400, Stewart Hildebrand wrote:
> On 8/14/25 12:03, Roger Pau Monne wrote:
> > The logic in map_range() will bubble up failures to the upper layer, which
> > will result in any remaining regions being skip, and for the non-hardware
> > domain case the owner domain of the device would be destroyed.  However for
> > the hardware domain the intent is to continue execution, hopping the
> > failure to modify the p2m could be worked around by the hardware domain.
> > 
> > To accomplish that in a better way, ignore failures and skip the range in
> > that case, possibly continuing to map further ranges.
> > 
> > Since the error path in vpci_process_pending() should only be used by domUs
> > now, and it will unconditionally end up calling domain_crash(), simplify
> > it: there's no need to cleanup if the domain will be destroyed.
> > 
> > No functional change for domUs intended.
> > 
> > Signed-off-by: Roger Pau Monné 
> > ---
> >  xen/drivers/vpci/header.c | 51 +++++++++++++++++++++------------------
> >  1 file changed, 28 insertions(+), 23 deletions(-)
> > 
> > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
> > index b9756b364300..1035dcca242d 100644
> > --- a/xen/drivers/vpci/header.c
> > +++ b/xen/drivers/vpci/header.c
> > @@ -64,7 +64,8 @@ static int cf_check map_range(
> >              printk(XENLOG_G_WARNING
> >                     "%pd denied access to MMIO range [%#lx, %#lx]\n",
> >                     map->d, map_mfn, m_end);
> > -            return -EPERM;
> > +            rc = -EPERM;
> > +            goto done;
> >          }
> >  
> >          rc = xsm_iomem_mapping(XSM_HOOK, map->d, map_mfn, m_end, map->map);
> > @@ -73,7 +74,7 @@ static int cf_check map_range(
> >              printk(XENLOG_G_WARNING
> >                     "%pd XSM denied access to MMIO range [%#lx, %#lx]: %d\n",
> >                     map->d, map_mfn, m_end, rc);
> > -            return rc;
> > +            goto done;
> >          }
> >  
> >          /*
> > @@ -87,17 +88,27 @@ static int cf_check map_range(
> >  
> >          rc = map->map ? map_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn))
> >                        : unmap_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn));
> > -        if ( rc == 0 )
> > -        {
> > -            *c += size;
> > -            break;
> > -        }
> >          if ( rc < 0 )
> >          {
> >              printk(XENLOG_G_WARNING
> >                     "Failed to %smap [%lx %lx] -> [%lx %lx] for %pd: %d\n",
> >                     map->map ? "" : "un", s, e, map_mfn,
> >                     map_mfn + size, map->d, rc);
> > +            goto done;
> > +        }
> > +        if ( rc == 0 )
> > +        {
> > + done:
> > +            if ( is_hardware_domain(map->d) )
> > +            {
> > +                /*
> > +                 * Ignore failures for the hardware domain and skip the range.
> > +                 * Do it as a best effort workaround to attempt to get the
> > +                 * hardware domain to boot.
> > +                 */
> > +                rc = 0;
> 
> If we return success and size is zero, we will potentially attempt to map/unmap
> the same region again in an infinite loop. rangeset_consume_ranges would invoke
> map_range again directly without returning to vpci_process_pending.
> 
> > +                *c += size;
> 
> This line is now only executed for hwdom, but ...
> 
> > +            }
> 
> ... it should go outside of the hwdom check because domUs still need it.
> 
> >              break;
> >          }
> >          ASSERT(rc < size);
> > @@ -213,28 +224,22 @@ bool vpci_process_pending(struct vcpu *v)
> >              return true;
> >          }
> >  
> > -        if ( rc )
> > +        if ( rc && !is_hardware_domain(v->domain) )
> >          {
> > -            spin_lock(&pdev->vpci->lock);
> > -            /* Disable memory decoding unconditionally on failure. */
> > -            modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY,
> > -                            false);
> 
> This path could be taken for either map or unmap. Do we still want to disable
> memory decoding in case of unmap?

Does it make an effective difference?  For the hardware domain we
should never get here, and for domUs the domain will be destroyed, so
disabling memory decoding is not helpful?

Thanks, Roger.


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Date: Mon, 18 Aug 2025 09:42:58 +0200
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Subject: Re: [PATCH] tools/xl: hide xenstore-features behind option
To: Juergen Gross 
Cc: Anthony PERARD ,
 Andrew Cooper ,
 Oleksii , xen-devel@lists.xenproject.org
References: <20250815143236.27641-1-jgross@suse.com>
 <115eca26-32a3-403f-9bf6-553c6b20940c@suse.com>
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From: Jan Beulich 
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On 15.08.2025 16:35, Juergen Gross wrote:
> + Release Manager

While this surely doesn't hurt, my understanding is that bug fixes don't
require release-acks just yet.

Jan

> On 15.08.25 16:32, Juergen Gross wrote:
>> In order to be able to use "xl info" before Xenstore has been started
>> or after it has crashed, hide obtaining the available Xenstore features
>> behind the new option "-x".
>>
>> Fixes: ecce7970cfe7 ("tools/xl: add available Xenstore features to xl info output")
>> Reported-by: Andrew Cooper 
>> Signed-off-by: Juergen Gross 
>> ---
>>   docs/man/xl.1.pod.in     |  4 ++++
>>   docs/man/xl.cfg.5.pod.in |  2 +-
>>   tools/xl/xl_info.c       | 14 ++++++++++----
>>   3 files changed, 15 insertions(+), 5 deletions(-)
>>
>> diff --git a/docs/man/xl.1.pod.in b/docs/man/xl.1.pod.in
>> index fe38724b2b..88ccf7ad82 100644
>> --- a/docs/man/xl.1.pod.in
>> +++ b/docs/man/xl.1.pod.in
>> @@ -996,6 +996,10 @@ B
>>   
>>   List host NUMA topology information
>>   
>> +=item B<-x>, B<--xenstore>
>> +
>> +Show Xenstore features available.
>> +
>>   =back
>>   
>>   =item B
>> diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
>> index f0c920b39d..acff45d308 100644
>> --- a/docs/man/xl.cfg.5.pod.in
>> +++ b/docs/man/xl.cfg.5.pod.in
>> @@ -743,7 +743,7 @@ condition.
>>   =back
>>   
>>   The features supported by the running Xenstore instance can be retrieved
>> -via the B command in dom0.
>> +via the B command in dom0.
>>   
>>   The default value is B<0xffffffff>, meaning that all possible Xenstore
>>   features are visible by the guest.
>> diff --git a/tools/xl/xl_info.c b/tools/xl/xl_info.c
>> index eb019e3ee9..d3583cbf8f 100644
>> --- a/tools/xl/xl_info.c
>> +++ b/tools/xl/xl_info.c
>> @@ -353,7 +353,7 @@ static void output_xenstore_info(void)
>>       xs_close(xsh);
>>   }
>>   
>> -static void print_info(int numa)
>> +static void print_info(int numa, bool xs)
>>   {
>>       output_nodeinfo();
>>   
>> @@ -365,7 +365,8 @@ static void print_info(int numa)
>>       }
>>       output_xeninfo();
>>   
>> -    output_xenstore_info();
>> +    if (xs)
>> +        output_xenstore_info();
>>   
>>       maybe_printf("xend_config_format     : 4\n");
>>   
>> @@ -631,14 +632,19 @@ int main_info(int argc, char **argv)
>>       int opt;
>>       static struct option opts[] = {
>>           {"numa", 0, 0, 'n'},
>> +        {"xenstore", 0, 0, 'x'},
>>           COMMON_LONG_OPTS
>>       };
>>       int numa = 0;
>> +    bool xs = false;
>>   
>> -    SWITCH_FOREACH_OPT(opt, "n", opts, "info", 0) {
>> +    SWITCH_FOREACH_OPT(opt, "nx", opts, "info", 0) {
>>       case 'n':
>>           numa = 1;
>>           break;
>> +    case 'x':
>> +        xs = true;
>> +        break;
>>       }
>>   
>>       /*
>> @@ -648,7 +654,7 @@ int main_info(int argc, char **argv)
>>       if (numa == 0 && argc > optind)
>>           info_name = argv[optind];
>>   
>> -    print_info(numa);
>> +    print_info(numa, xs);
>>       return 0;
>>   }
>>   
> 



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        Mon, 18 Aug 2025 00:47:21 -0700 (PDT)
Date: Mon, 18 Aug 2025 09:47:20 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Stewart Hildebrand 
Cc: xen-devel@lists.xenproject.org, Jiqian.Chen@amd.com, jbeulich@suse.com
Subject: Re: [PATCH 2/5] xen/vpci: make BAR mapping more resilient for the
 hardware domain
Message-ID: 
References: <20250814160358.95543-1-roger.pau@citrix.com>
 <20250814160358.95543-3-roger.pau@citrix.com>
 <269db2aa-9ca1-446b-98f7-60ea2386fc03@amd.com>
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On Fri, Aug 15, 2025 at 02:53:35PM -0400, Stewart Hildebrand wrote:
> On 8/14/25 12:03, Roger Pau Monne wrote:
> > The logic in map_range() will bubble up failures to the upper layer, which
> > will result in any remaining regions being skip, and for the non-hardware
> > domain case the owner domain of the device would be destroyed.  However for
> > the hardware domain the intent is to continue execution, hopping the
> > failure to modify the p2m could be worked around by the hardware domain.
> > 
> > To accomplish that in a better way, ignore failures and skip the range in
> > that case, possibly continuing to map further ranges.
> > 
> > Since the error path in vpci_process_pending() should only be used by domUs
> > now, and it will unconditionally end up calling domain_crash(), simplify
> > it: there's no need to cleanup if the domain will be destroyed.
> > 
> > No functional change for domUs intended.
> > 
> > Signed-off-by: Roger Pau Monné 
> > ---
> >  xen/drivers/vpci/header.c | 51 +++++++++++++++++++++------------------
> >  1 file changed, 28 insertions(+), 23 deletions(-)
> > 
> > diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
> > index b9756b364300..1035dcca242d 100644
> > --- a/xen/drivers/vpci/header.c
> > +++ b/xen/drivers/vpci/header.c
> > @@ -64,7 +64,8 @@ static int cf_check map_range(
> >              printk(XENLOG_G_WARNING
> >                     "%pd denied access to MMIO range [%#lx, %#lx]\n",
> >                     map->d, map_mfn, m_end);
> > -            return -EPERM;
> > +            rc = -EPERM;
> > +            goto done;
> >          }
> >  
> >          rc = xsm_iomem_mapping(XSM_HOOK, map->d, map_mfn, m_end, map->map);
> > @@ -73,7 +74,7 @@ static int cf_check map_range(
> >              printk(XENLOG_G_WARNING
> >                     "%pd XSM denied access to MMIO range [%#lx, %#lx]: %d\n",
> >                     map->d, map_mfn, m_end, rc);
> > -            return rc;
> > +            goto done;
> >          }
> >  
> >          /*
> > @@ -87,17 +88,27 @@ static int cf_check map_range(
> >  
> >          rc = map->map ? map_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn))
> >                        : unmap_mmio_regions(map->d, _gfn(s), size, _mfn(map_mfn));
> > -        if ( rc == 0 )
> > -        {
> > -            *c += size;
> > -            break;
> > -        }
> >          if ( rc < 0 )
> >          {
> >              printk(XENLOG_G_WARNING
> >                     "Failed to %smap [%lx %lx] -> [%lx %lx] for %pd: %d\n",
> >                     map->map ? "" : "un", s, e, map_mfn,
> >                     map_mfn + size, map->d, rc);
> > +            goto done;
> > +        }
> > +        if ( rc == 0 )
> > +        {
> > + done:
> > +            if ( is_hardware_domain(map->d) )
> > +            {
> > +                /*
> > +                 * Ignore failures for the hardware domain and skip the range.
> > +                 * Do it as a best effort workaround to attempt to get the
> > +                 * hardware domain to boot.
> > +                 */
> > +                rc = 0;
> 
> If we return success and size is zero, we will potentially attempt to map/unmap
> the same region again in an infinite loop. rangeset_consume_ranges would invoke
> map_range again directly without returning to vpci_process_pending.
> 
> > +                *c += size;
> 
> This line is now only executed for hwdom, but ...
> 
> > +            }
> 
> ... it should go outside of the hwdom check because domUs still need it.

Indeed, this should be:

            if ( is_hardware_domain(map->d) )
                /*
                 * Ignore failures for the hardware domain and skip the range.
                 * Do it as a best effort workaround to attempt to get the
                 * hardware domain to boot.
                 */
                rc = 0;

            *c += size;
            break;

Otherwise domU won't make progress.  It would be helpful to have some
domU testing in the CI loop, otherwise I have no way to test the domU
side when modifying vPCI.

Thanks, Roger.


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From: Jan Beulich 
Subject: [PATCH v2 0/2] constrain page_is_ram_type() to x86
To: "xen-devel@lists.xenproject.org" 
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Re-worked the plain dropping of an assertion to a function rename, and then
isolating of the original function to just x86.

1: Arm: drop assertion from page_is_ram_type()
2: common: make page_{is,get}_ram_type() x86-only

Jan


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Its uses in offline_page() and query_page_offline() make it reachable on
Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
code added. It being reachable was even mentioned in the commit
introducing it, claiming it "clearly shouldn't be called on ARM just
yet".

However, dropping the assertion from a function of this name is deemed
problematic. Rename it to better reflect its sole purpose outside of
x86-specific code.

Fixes: 214c4cd94a80 ("xen: arm: stub page_is_ram_type")
Signed-off-by: Jan Beulich 
---
v2: Rename the function used in common code.
---
The new name is chosen such that, down the road, offlining of non-RAM
could in principle also become possible.

--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -64,10 +64,9 @@ int steal_page(
     return -EOPNOTSUPP;
 }
 
-int page_is_ram_type(unsigned long mfn, unsigned long mem_type)
+bool page_is_offlinable(mfn_t mfn)
 {
-    ASSERT_UNREACHABLE();
-    return 0;
+    return false;
 }
 
 unsigned long domain_get_maximum_gpfn(struct domain *d)
--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -425,6 +425,11 @@ int page_is_ram_type(unsigned long mfn,
     return 0;
 }
 
+bool page_is_offlinable(mfn_t mfn)
+{
+    return page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL);
+}
+
 unsigned int page_get_ram_type(mfn_t mfn)
 {
     uint64_t last = 0, maddr = mfn_to_maddr(mfn);
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -1635,7 +1635,7 @@ static unsigned long mark_page_offline(s
 {
     unsigned long nx, x, y = pg->count_info;
 
-    ASSERT(page_is_ram_type(mfn_x(page_to_mfn(pg)), RAM_TYPE_CONVENTIONAL));
+    ASSERT(page_is_offlinable(page_to_mfn(pg)));
     ASSERT(spin_is_locked(&heap_lock));
 
     do {
@@ -1711,7 +1711,7 @@ int offline_page(mfn_t mfn, int broken,
      * N.B. xen's txt in x86_64 is marked reserved and handled already.
      * Also kexec range is reserved.
      */
-    if ( !page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL) )
+    if ( !page_is_offlinable(mfn) )
     {
         *status = PG_OFFLINE_FAILED | PG_OFFLINE_NOT_CONV_RAM;
         return -EINVAL;
@@ -1851,7 +1851,7 @@ int query_page_offline(mfn_t mfn, uint32
 {
     struct page_info *pg;
 
-    if ( !mfn_valid(mfn) || !page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL) )
+    if ( !mfn_valid(mfn) || !page_is_offlinable(mfn) )
     {
         dprintk(XENLOG_WARNING, "call expand_pages() first\n");
         return -EINVAL;
--- a/xen/include/xen/mm.h
+++ b/xen/include/xen/mm.h
@@ -144,9 +144,11 @@ unsigned long avail_domheap_pages_region
 unsigned long avail_node_heap_pages(unsigned int nodeid);
 #define alloc_domheap_page(d,f) (alloc_domheap_pages(d,0,f))
 #define free_domheap_page(p)  (free_domheap_pages(p,0))
+
 int online_page(mfn_t mfn, uint32_t *status);
 int offline_page(mfn_t mfn, int broken, uint32_t *status);
 int query_page_offline(mfn_t mfn, uint32_t *status);
+bool page_is_offlinable(mfn_t mfn);
 
 void heap_init_late(void);
 



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Subject: [PATCH v2 2/2] common: make page_{is,get}_ram_type() x86-only
From: Jan Beulich 
To: "xen-devel@lists.xenproject.org" 
Cc: Julien Grall , Stefano Stabellini
 , Volodymyr Babchuk ,
 Bertrand Marquis ,
 Michal Orzel ,
 Oleksii Kurochko ,
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The classification is pretty E820-centric anyway, and all uses of the
function are now in x86-only code.

Switch the boolean return type to properly use bool while at it.

Signed-off-by: Jan Beulich 
---
v2: New.

--- a/xen/arch/x86/include/asm/mm.h
+++ b/xen/arch/x86/include/asm/mm.h
@@ -464,6 +464,16 @@ extern bool opt_pv_linear_pt;
     ASSERT(((_p)->count_info & PGC_count_mask) != 0);          \
     ASSERT(page_get_owner(_p) == (_d))
 
+#define RAM_TYPE_CONVENTIONAL 0x00000001
+#define RAM_TYPE_RESERVED     0x00000002
+#define RAM_TYPE_UNUSABLE     0x00000004
+#define RAM_TYPE_ACPI         0x00000008
+#define RAM_TYPE_UNKNOWN      0x00000010
+/* TRUE if the whole page at @mfn is of the requested RAM type(s) above. */
+bool page_is_ram_type(unsigned long mfn, unsigned long mem_type);
+/* Returns the page type(s). */
+unsigned int page_get_ram_type(mfn_t mfn);
+
 /******************************************************************************
  * With shadow pagetables, the different kinds of address start
  * to get get confusing.
--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -385,7 +385,7 @@ void __init arch_init_memory(void)
     ASM_CONSTANT(FIXADDR_X_SIZE, FIXADDR_X_SIZE);
 }
 
-int page_is_ram_type(unsigned long mfn, unsigned long mem_type)
+bool page_is_ram_type(unsigned long mfn, unsigned long mem_type)
 {
     uint64_t maddr = pfn_to_paddr(mfn);
     int i;
@@ -419,10 +419,10 @@ int page_is_ram_type(unsigned long mfn,
         /* Test the range. */
         if ( (e820.map[i].addr <= maddr) &&
              ((e820.map[i].addr + e820.map[i].size) >= (maddr + PAGE_SIZE)) )
-            return 1;
+            return true;
     }
 
-    return 0;
+    return false;
 }
 
 bool page_is_offlinable(mfn_t mfn)
--- a/xen/include/xen/mm.h
+++ b/xen/include/xen/mm.h
@@ -565,15 +565,6 @@ int __must_check guest_remove_page(struc
 int __must_check steal_page(struct domain *d, struct page_info *page,
                             unsigned int memflags);
 
-#define RAM_TYPE_CONVENTIONAL 0x00000001
-#define RAM_TYPE_RESERVED     0x00000002
-#define RAM_TYPE_UNUSABLE     0x00000004
-#define RAM_TYPE_ACPI         0x00000008
-#define RAM_TYPE_UNKNOWN      0x00000010
-/* TRUE if the whole page at @mfn is of the requested RAM type(s) above. */
-int page_is_ram_type(unsigned long mfn, unsigned long mem_type);
-/* Returns the page type(s). */
-unsigned int page_get_ram_type(mfn_t mfn);
 /* Check if a range falls into a hole in the memory map. */
 bool is_memory_hole(mfn_t start, mfn_t end);
 



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Subject: Re: [PATCH v2] xen/irq: Delete the pirq_cleanup_check() macro
To: Dmytro Prokopchuk1 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" 
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On 16.08.2025 18:31, Dmytro Prokopchuk1 wrote:
> From: Andrew Cooper 
> 
> MISRA Rule 5.5 objects to a macro aliasing a function, which is what
> pirq_cleanup_check() does. The macro was originally intended to ensure
> the condition 'if (!pirq->evtchn)' is always checked before invoking
> the function, avoiding errors across call sites.
> 
> To achieve MISRA compliance, the condition is expanded inline at all
> call sites,

That's not correct. Andrew's description specifically said "..., and
one path in evtchn_bind_pirq() where the expanded form simplies back
to no delta, as it follows an unconditional clear of info->evtchn."
Imo this wording wants adding back, with adjustments as necessary to
make it fit the rest of the sentence. (Likely doable on commit, if
no other reason for a v3 arises.)

Jan

> using plain C constructs. This ensures clarity while
> retaining the original behavior. While this complies with MISRA, it
> shifts the responsibility to developers to check 'if (!pirq->evtchn)'
> at call sites.
> 
> No functional changes.
> 
> Signed-off-by: Andrew Cooper 
> Signed-off-by: Dmytro Prokopchuk 


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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Stefano Stabellini ,
	Julien Grall ,
	Volodymyr Babchuk ,
	Bertrand Marquis ,
	Michal Orzel 
Subject: [PATCH] arm/link: Remove exception table sections
Date: Mon, 18 Aug 2025 09:18:24 +0100
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This was almost certainly copy&paste from x86.  ARM does not us these nor
selects HAS_EX_TABLE, so drop the sections and their boundary markers.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Stefano Stabellini 
CC: Julien Grall 
CC: Volodymyr Babchuk 
CC: Bertrand Marquis 
CC: Michal Orzel 

Found because I'm getting rid of .ex_table.pre on x86 too.
---
 xen/arch/arm/xen.lds.S | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S
index 9f30c3a13ed1..db17ff1efa98 100644
--- a/xen/arch/arm/xen.lds.S
+++ b/xen/arch/arm/xen.lds.S
@@ -86,16 +86,6 @@ SECTIONS
   } : text
 
   .data.read_mostly : {
-       /* Exception table */
-       __start___ex_table = .;
-       *(.ex_table)
-       __stop___ex_table = .;
-
-       /* Pre-exception table */
-       __start___pre_ex_table = .;
-       *(.ex_table.pre)
-       __stop___pre_ex_table = .;
-
        *(.data.read_mostly)
   } :text
 
-- 
2.39.5



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To: Erkai Yu 
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 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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On 18.08.2025 03:06, "Erkai Yu failedtofindaname"@gmail.com wrote:
> From: Erkai Yu 
> 
> Update LLVM profile raw format version from 4 to 10, supporting
> LLVM 19 and LLVM 20. Only the file xen/common/coverage/llvm.c is 
> changed.
> 
> I’m not sure whether maintainers want to update this version, since
> version 4 is already a bit outdated. My patch currently supports LLVM
> 19 and 20; it’s unclear if maintainers would prefer support for all
> format versions from 4 to 10.

This shouldn't be part of the commit message imo, but yes - we can't
very well support just one version when it constantly changes.

Jan


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From: Oleksii Kurochko 
Subject: Re: [PATCH v3 13/20] xen/riscv: Implement p2m_free_subtree() and
 related helpers
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
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On 8/14/25 5:17 PM, Jan Beulich wrote:
> On 14.08.2025 17:09, Oleksii Kurochko wrote:
>> On 8/6/25 5:55 PM, Jan Beulich wrote:
>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>> +/* Put any references on the page referenced by pte. */
>>>> +static void p2m_put_page(const pte_t pte, unsigned int level)
>>>> +{
>>>> +    mfn_t mfn = pte_get_mfn(pte);
>>>> +    p2m_type_t p2m_type = p2m_get_type(pte);
>>>> +
>>>> +    ASSERT(pte_is_valid(pte));
>>>> +
>>>> +    /*
>>>> +     * TODO: Currently we don't handle level 2 super-page, Xen is not
>>>> +     * preemptible and therefore some work is needed to handle such
>>>> +     * superpages, for which at some point Xen might end up freeing memory
>>>> +     * and therefore for such a big mapping it could end up in a very long
>>>> +     * operation.
>>>> +     */
>>>> +    switch ( level )
>>>> +    {
>>>> +    case 1:
>>>> +        return p2m_put_2m_superpage(mfn, p2m_type);
>>>> +
>>>> +    case 0:
>>>> +        return p2m_put_4k_page(mfn, p2m_type);
>>>> +    }
>>> Yet despite the comment not even an assertion for level 2 and up?
>> Not sure that an ASSERT() is needed here as a reference(s) for such page(s)
>> will be put during domain_relinquish_resources() as there we could do preemption.
>> Something like Arm does here:
>>     https://gitlab.com/xen-project/people/olkur/xen/-/blob/staging/xen/arch/arm/mmu/p2m.c?ref_type=heads#L1587
>>
>> I'm thinking that probably it makes sense to put only 4k page(s) and
>> all other cases postpone until domain_relinquish_resources() is called.
> How can you defer to domain cleanup? How would handling of foreign mappings
> (or e.g. ballooning? not sure) work when you don't drop references as
> necessary?

I was confused by the code in|relinquish_p2m_mapping()|, since it removes
foreign mappings from the P2M. My current understanding is that it is called
for foreign mappings that weren’t explicitly unmapped, in order to drop the
page reference taken when the mapping was created. Initially, I thought it
would be enough to just perform the (un)map in the P2M page tables to have
foreign mapping working, but that could result in a page never being fully
released, which would in turn break or confuse other logic.

So, yes, I agree that your initial suggestion to add ASSERT() is useful to
be sure that no one is using level 2 super-pages for foreign mapping.

>>>>    /* Free pte sub-tree behind an entry */
>>>>    static void p2m_free_subtree(struct p2m_domain *p2m,
>>>>                                 pte_t entry, unsigned int level)
>>>>    {
>>>> -    panic("%s: hasn't been implemented yet\n", __func__);
>>>> +    unsigned int i;
>>>> +    pte_t *table;
>>>> +    mfn_t mfn;
>>>> +    struct page_info *pg;
>>>> +
>>>> +    /* Nothing to do if the entry is invalid. */
>>>> +    if ( !pte_is_valid(entry) )
>>>> +        return;
>>>> +
>>>> +    if ( pte_is_superpage(entry, level) || (level == 0) )
>>> Perhaps swap the two conditions around?
>>>
>>>> +    {
>>>> +#ifdef CONFIG_IOREQ_SERVER
>>>> +        /*
>>>> +         * If this gets called then either the entry was replaced by an entry
>>>> +         * with a different base (valid case) or the shattering of a superpage
>>>> +         * has failed (error case).
>>>> +         * So, at worst, the spurious mapcache invalidation might be sent.
>>>> +         */
>>>> +        if ( p2m_is_ram(p2m_get_type(p2m, entry)) &&
>>>> +             domain_has_ioreq_server(p2m->domain) )
>>>> +            ioreq_request_mapcache_invalidate(p2m->domain);
>>>> +#endif
>>>> +
>>>> +        p2m_put_page(entry, level);
>>>> +
>>>> +        return;
>>>> +    }
>>>> +
>>>> +    table = map_domain_page(pte_get_mfn(entry));
>>>> +    for ( i = 0; i < XEN_PT_ENTRIES; i++ )
>>>> +        p2m_free_subtree(p2m, table[i], level - 1);
>>> In p2m_put_page() you comment towards concerns for level >= 2; no similar
>>> concerns for the resulting recursion here?
>> This function is generic enough to handle any level.
>>
>> Except that it is possible that it will be needed, for example, to split 1G mapping
>> into something smaller then p2m_free_subtree() could be called for freeing a subtree
>> of 1gb mapping.
> The question wasn't about it being generic enough, but it possibly taking
> too much time for level >= 2.

In this terms it makes sense to add such an assertion which will check that we are
working with levels <= 2.

Thanks.

~ Oleksii

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    On 8/14/25 5:17 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 14.08.2025 17:09, Oleksii Kurochko wrote:

    
      
    
        
    On 8/6/25 5:55 PM, Jan Beulich wrote:

    
        
    
          
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
          
    
            
    +/* Put any references on the page referenced by pte. */
+static void p2m_put_page(const pte_t pte, unsigned int level)
+{
+    mfn_t mfn = pte_get_mfn(pte);
+    p2m_type_t p2m_type = p2m_get_type(pte);
+
+    ASSERT(pte_is_valid(pte));
+
+    /*
+     * TODO: Currently we don't handle level 2 super-page, Xen is not
+     * preemptible and therefore some work is needed to handle such
+     * superpages, for which at some point Xen might end up freeing memory
+     * and therefore for such a big mapping it could end up in a very long
+     * operation.
+     */
+    switch ( level )
+    {
+    case 1:
+        return p2m_put_2m_superpage(mfn, p2m_type);
+
+    case 0:
+        return p2m_put_4k_page(mfn, p2m_type);
+    }

    
          
    
          
    Yet despite the comment not even an assertion for level 2 and up?

    
        
    
        
    Not sure that an ASSERT() is needed here as a reference(s) for such page(s)
will be put during domain_relinquish_resources() as there we could do preemption.
Something like Arm does here:
   https://gitlab.com/xen-project/people/olkur/xen/-/blob/staging/xen/arch/arm/mmu/p2m.c?ref_type=heads#L1587

I'm thinking that probably it makes sense to put only 4k page(s) and
all other cases postpone until domain_relinquish_resources() is called.

    
      
    
      
    How can you defer to domain cleanup? How would handling of foreign mappings
(or e.g. ballooning? not sure) work when you don't drop references as
necessary?
    
    
    
    
    I was confused by the code in relinquish_p2m_mapping(), since it removes
foreign mappings from the P2M. My current understanding is that it is called
for foreign mappings that weren’t explicitly unmapped, in order to drop the
page reference taken when the mapping was created. Initially, I thought it
would be enough to just perform the (un)map in the P2M page tables to have
foreign mapping working, but that could result in a page never being fully
released, which would in turn break or confuse other logic.

So, yes, I agree that your initial suggestion to add ASSERT() is useful to
be sure that no one is using level 2 super-pages for foreign mapping.


    
    
    
      
    
        
    
          
    
            
      /* Free pte sub-tree behind an entry */
  static void p2m_free_subtree(struct p2m_domain *p2m,
                               pte_t entry, unsigned int level)
  {
-    panic("%s: hasn't been implemented yet\n", __func__);
+    unsigned int i;
+    pte_t *table;
+    mfn_t mfn;
+    struct page_info *pg;
+
+    /* Nothing to do if the entry is invalid. */
+    if ( !pte_is_valid(entry) )
+        return;
+
+    if ( pte_is_superpage(entry, level) || (level == 0) )

    
          
    
          
    Perhaps swap the two conditions around?


    
          
    
            
    +    {
+#ifdef CONFIG_IOREQ_SERVER
+        /*
+         * If this gets called then either the entry was replaced by an entry
+         * with a different base (valid case) or the shattering of a superpage
+         * has failed (error case).
+         * So, at worst, the spurious mapcache invalidation might be sent.
+         */
+        if ( p2m_is_ram(p2m_get_type(p2m, entry)) &&
+             domain_has_ioreq_server(p2m->domain) )
+            ioreq_request_mapcache_invalidate(p2m->domain);
+#endif
+
+        p2m_put_page(entry, level);
+
+        return;
+    }
+
+    table = map_domain_page(pte_get_mfn(entry));
+    for ( i = 0; i < XEN_PT_ENTRIES; i++ )
+        p2m_free_subtree(p2m, table[i], level - 1);

    
          
    
          
    In p2m_put_page() you comment towards concerns for level >= 2; no similar
concerns for the resulting recursion here?

    
        
    
        
    This function is generic enough to handle any level.

Except that it is possible that it will be needed, for example, to split 1G mapping
into something smaller then p2m_free_subtree() could be called for freeing a subtree
of 1gb mapping.

    
      
    
      
    The question wasn't about it being generic enough, but it possibly taking
too much time for level >= 2.
    
    
    
    
    In this terms it makes sense to add such an assertion which will check that we are
working with levels <= 2.

Thanks.
    
    
    ~ Oleksii

    
  


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From: Dmytro Prokopchuk1 
To: Jan Beulich 
CC: Andrew Cooper , Anthony PERARD
	, Michal Orzel , Julien
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	, Stefano Stabellini , Nicola
 Vetrini , "xen-devel@lists.xenproject.org"
	
Subject: Re: [PATCH v2] docs/misra: fix sphinx-build issues
Thread-Topic: [PATCH v2] docs/misra: fix sphinx-build issues
Thread-Index: AQHcDe8as9q/ao3zhECV/xRhyhAMwbRoCj+AgAANtAA=
Date: Mon, 18 Aug 2025 08:27:18 +0000
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Subject: Re: [PATCH] mm/numa: Rename memory_add_physaddr_to_nid to memory_get_phys_to_nid
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On Mon, Aug 18, 2025 at 12:29=E2=80=AFPM David Hildenbrand  wrote:
>
> On 18.08.25 08:41, pratyush.brahma@oss.qualcomm.com wrote:
> > From: Pratyush Brahma 
> >
> > The function `memory_add_physaddr_to_nid` seems a misnomer.
> > It does not to "add" a physical address to a NID mapping,
> > but rather it gets the NID associated with a given physical address.
>
> You probably misunderstood what the function is used for: memory hotplug
> aka "memory_add".
Thanks for your feedback. I get the part about memory hotplug here but
using memory_add still seems a little odd as it doesn't truly reflect
what this api is doing.
However, I agree that my current suggestion
may not be the perfect choice for the name, so I'm open to suggestions.

Perhaps, something like "memory_add_get_nid_by_phys" may work here?
>
> This patch is making matters worse by stripping that detail, unfortunatel=
y.
>
>
> --
> Cheers
>
> David / dhildenb
>
Thanks and Regards
Pratyush


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Subject: Re: [PATCH v2 7/7] xen: New API to claim memory for a domain using
 XEN_DOMCTL_claim_memory
From: Christian Lindig 
In-Reply-To: 
Date: Mon, 18 Aug 2025 09:28:02 +0100
Cc: xen-devel@lists.xenproject.org,
 "Daniel P. Smith" ,
 Anthony PERARD ,
 Andrew Cooper ,
 Michal Orzel ,
 Jan Beulich ,
 Julien Grall ,
 =?utf-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Juergen Gross ,
 Christian Lindig ,
 David Scott ,
 Alejandro Vallejo 
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References: 
 
To: Bernhard Kaindl 
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Acked-by: Christian Lindig 


> On 16 Aug 2025, at 12:19, Bernhard Kaindl  =
wrote:
>=20
> Add the new hypercall requested during the review of the v1 series
> do not require changing the API for multi-node claims.
>=20
> The hypercall receives a number of claims, intented to be one claim =
per
> NUMA node, and limited to one claim for now. The changes to update the
> NUMA claims management to handle updating the claims for multiple
> NUMA nodes of a domain at once are deferred to the next series.
>=20
> Signed-off-by: Bernhard Kaindl 
> Cc: Alejandro Vallejo 
> ---
> tools/flask/policy/modules/dom0.te  |  1 +
> tools/flask/policy/modules/xen.if   |  1 +
> tools/include/xenctrl.h             |  4 +++
> tools/libs/ctrl/xc_domain.c         | 42 +++++++++++++++++++++++++++++
> tools/ocaml/libs/xc/xenctrl.ml      |  9 +++++++
> tools/ocaml/libs/xc/xenctrl.mli     |  9 +++++++
> tools/ocaml/libs/xc/xenctrl_stubs.c | 21 +++++++++++++++
> xen/common/domain.c                 | 30 +++++++++++++++++++++
> xen/common/domctl.c                 |  8 ++++++
> xen/include/public/domctl.h         | 17 ++++++++++++
> xen/include/xen/domain.h            |  2 ++
> xen/xsm/flask/hooks.c               |  3 +++
> xen/xsm/flask/policy/access_vectors |  2 ++
> 13 files changed, 149 insertions(+)

> +
> +    /* Use an array to not need changes for multi-node claims in the =
future */
> +    if ( nr_claims )
> +    {
> +        size_t bytes =3D sizeof(memory_claim_t) * nr_claims;
> +
> +        buffer =3D xc_hypercall_buffer_alloc(xch, buffer, bytes);
> +        if ( buffer =3D=3D NULL )
> +        {
> +            PERROR("Could not allocate memory for =
xc_domain_claim_memory");
> +            return -1;
> +        }
> +        memcpy(buffer, claims, bytes);
> +        set_xen_guest_handle(domctl.u.claim_memory.claims, buffer);
> +    }
> +
> +    ret =3D do_domctl(xch, &domctl);
> +    xc_hypercall_buffer_free(xch, buffer);
> +    return ret;
> +}

Should this be "if (nr_claims > 0)=E2=80=9D or have an assertion against =
negative values?

=E2=80=94 C



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Subject: Re: [PATCH] mm/numa: Rename memory_add_physaddr_to_nid to
 memory_get_phys_to_nid
To: Pratyush Brahma 
Cc: Madhavan Srinivasan ,
 Michael Ellerman , Nicholas Piggin ,
 Christophe Leroy ,
 Heiko Carstens , Vasily Gorbik ,
 Alexander Gordeev ,
 Christian Borntraeger ,
 Sven Schnelle , "Rafael J. Wysocki"
 , Len Brown ,
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 "K. Y. Srinivasan" ,
 Haiyang Zhang , Wei Liu ,
 Dexuan Cui , Pankaj Gupta
 , "Michael S. Tsirkin" ,
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 =?UTF-8?Q?Eugenio_P=C3=A9rez?= ,
 Juergen Gross , Stefano Stabellini
 ,
 Oleksandr Tyshchenko ,
 Andrew Morton , Mike Rapoport ,
 linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
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References: <20250818-numa_memblks-v1-1-9eb29ade560a@oss.qualcomm.com>
 
 
From: David Hildenbrand 
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On 18.08.25 10:27, Pratyush Brahma wrote:
> On Mon, Aug 18, 2025 at 12:29 PM David Hildenbrand  wrote:
>>
>> On 18.08.25 08:41, pratyush.brahma@oss.qualcomm.com wrote:
>>> From: Pratyush Brahma 
>>>
>>> The function `memory_add_physaddr_to_nid` seems a misnomer.
>>> It does not to "add" a physical address to a NID mapping,
>>> but rather it gets the NID associated with a given physical address.
>>
>> You probably misunderstood what the function is used for: memory hotplug
>> aka "memory_add".
> Thanks for your feedback. I get the part about memory hotplug here but
> using memory_add still seems a little odd as it doesn't truly reflect
> what this api is doing.
> However, I agree that my current suggestion
> may not be the perfect choice for the name, so I'm open to suggestions.
> 
> Perhaps, something like "memory_add_get_nid_by_phys" may work here?

I don't think this name is really any better and worth the churn :(

-- 
Cheers

David / dhildenb



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Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
To: Penny Zheng ,
 Oleksii Kurochko 
Cc: ray.huang@amd.com, Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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On 15.08.2025 12:27, Penny Zheng wrote:
> In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and
> HVM=y results in hvm.c being built, but domctl.c not being built, which leaves
> a few functions, like domctl_lock_acquire/release() undefined, causing linking
> to fail.
> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile
> /hypercall-defs section, with this adjustment, we also need to release
> redundant vnuma_destroy() stub definition from PV_SHIM_EXCLUSIVE guardian,
> to not break compilation
> Above change will leave dead code in the shim binary temporarily and will be
> fixed with the introduction of domctl-op wrapping.

Well, "temporarily" is now getting interesting. While v1 of "Introduce
CONFIG_DOMCTL" was submitted in time to still be eligible for taking into
4.21, that - as indicated elsewhere - is moving us further in an unwanted
direction. Hence I'm not sure this can even be counted as an in-time
submission. Plus it looks to be pretty extensive re-work in some areas.
Hence I'm somewhat weary as to 4.21 here. IOW question, mainly to Oleksii,
is whether to
1) strive to complete that work in time (and hence take the patch here),
2) take the patch here, accepting the size regression for the shim, or
3) revert what has caused the randconfig issues, and retry the effort in
   4.22.

> Fixes: 568f806cba4c ("xen/x86: remove "depends on !PV_SHIM_EXCLUSIVE"")
> Reported-by: Jan Beulich 
> Signed-off-by: Penny Zheng 

My earlier question (when the patch still was part of a series) sadly has
remained unanswered: You've run this through a full round of testing this
time?

Jan


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On Mon, Aug 18, 2025 at 2:01=E2=80=AFPM David Hildenbrand  wrote:
>
> On 18.08.25 10:27, Pratyush Brahma wrote:
> > On Mon, Aug 18, 2025 at 12:29=E2=80=AFPM David Hildenbrand  wrote:
> >>
> >> On 18.08.25 08:41, pratyush.brahma@oss.qualcomm.com wrote:
> >>> From: Pratyush Brahma 
> >>>
> >>> The function `memory_add_physaddr_to_nid` seems a misnomer.
> >>> It does not to "add" a physical address to a NID mapping,
> >>> but rather it gets the NID associated with a given physical address.
> >>
> >> You probably misunderstood what the function is used for: memory hotpl=
ug
> >> aka "memory_add".
> > Thanks for your feedback. I get the part about memory hotplug here but
> > using memory_add still seems a little odd as it doesn't truly reflect
> > what this api is doing.
> > However, I agree that my current suggestion
> > may not be the perfect choice for the name, so I'm open to suggestions.
> >
> > Perhaps, something like "memory_add_get_nid_by_phys" may work here?
>
> I don't think this name is really any better and worth the churn :(
>
Sure. Thanks for taking a look. Will drop this.
> --
> Cheers
>
> David / dhildenb
>
Thanks & Regards
Pratyush


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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini 
Subject: [PATCH v9 3/4] SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
Date: Mon, 18 Aug 2025 11:49:26 +0300
Message-ID: <433d74567cabf33c2a672afc0f96e58efec75c54.1755506449.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

Add a new entry under the "Virtual Hardware, QEMU" section documenting
support for the optional PSCI SYSTEM_SUSPEND function exposed to guests.

This function is available via the virtual PSCI (vPSCI) interface and
allows guest domains (domUs) to initiate system suspend operations.

The feature is currently marked as Experimental.

Signed-off-by: Mykola Kvach 
---
Changes in v6:
- Dropped the generic guest PSCI support entry (merged in a separate patch)
- This patch now documents only the SYSTEM_SUSPEND optional function
- Reworded commit message to match the final form after rebase

Changes in v5:
- Dropped ARM/PSCI entry: this refers to internal use of PSCI SMC calls,
  which is not relevant for SUPPORT.md
- Added a dedicated entry for PSCI SYSTEM_SUSPEND instead of generic guest
  PSCI info; guest PSCI support was documented in a separate patch
---
 SUPPORT.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/SUPPORT.md b/SUPPORT.md
index 6a82a92189..b5ab049b52 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -962,8 +962,9 @@ Emulated PSCI interface exposed to guests. We support all mandatory
 functions of PSCI 1.1. See below for the list of optional PSCI call
 implemented and their status.
 
-   Status, Mandatory: Supported
-   Status, MIGRATE_INFO_TYPE: Supported
+    Status, Mandatory: Supported
+    Status, MIGRATE_INFO_TYPE: Supported
+    Status, SYSTEM_SUSPEND: Experimental
 
 ## Virtual Hardware, QEMU
 
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Juergen Gross ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v9 0/4] Enable guest suspend/resume support on ARM via vPSCI
Date: Mon, 18 Aug 2025 11:49:23 +0300
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From: Mykola Kvach 

This patch series introduces the initial support for guest suspend
and resume on ARM platforms using the PSCI SYSTEM_SUSPEND interface. The main
goal is to allow ARM guests to request suspension using PSCI and be resumed
by the control domain (e.g., via "xl resume").

### Background

The PSCI SYSTEM_SUSPEND call is part of the PSCI v1.0+ specification and is
used by guests to enter the deepest possible power state. On Xen/ARM, we
emulate this interface in the virtual PSCI (vPSCI) layer for guests.

This series includes:

1. A new vPSCI implementation of the PSCI SYSTEM_SUSPEND function for guests
2. Documentation updates to SUPPORT.md to reflect PSCI and vPSCI support status
3. Enabling "xl resume" command compilation for ARM, which was previously disabled

### Usage

For Linux-based guests:
  - Suspend can be triggered using: "echo mem > /sys/power/state" or "systemctl suspend"
  - Resume can be performed from control domain using: "xl resume "

For more information, refer to the official Linux kernel documentation on power management.

Note that currently, SYSTEM_SUSPEND is supported only for guest domains (not for
the hardware domain).
---

TODO: enable "xl suspend" for ARM
---

This is the first part of previous patch series and originally consist only
with necessary changes needed for guest domain suspend.

The second part can be found here:
    https://patchew.org/Xen/cover.1754943874.git.mykola._5Fkvach@epam.com/

Changes in V9:
- no functional changes
- enhance commit message and add extra comment to the code after review

Changes in V8:
- GIC and virtual timer context saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Main changes in V6:
- Skip execution of ctxt_switch_from for VCPUs in paused domains.
- Implement domain_resume_nopause
- Add a helper to determine if a VCPU is in suspended domain.
- Ignore upper 32 bits of arguments for 64-bit domains calling SMC32 SYSTEM_SUSPEND.
- Macro renamed from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND for clarity.
- Documentation now focuses only on the SYSTEM_SUSPEND function, with improved wording and structure.
- Changelog and commit messages refined for clarity and to remove redundant explanations.

Main change in V5:
  - Reverted the logic related to suspending domains. Instead of the standby
    mode introduced in v4, domains now resume execution at the point provided
    during suspend

The rest of the minor changes are described in the changelog of each commit.

Previous versions of this patch series:
  V1: https://lists.xenproject.org/archives/html/xen-devel/2018-11/msg01093.html
  V2: https://marc.info/?l=xen-devel&m=166514782207736&w=2
  V3: https://lists.xenproject.org/archives/html/xen-devel/2025-03/msg00168.html

Mykola Kvach (4):
  xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
  tools/xl: Allow compilation of 'xl resume' command on Arm
  SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
  CHANGELOG: Document guest suspend/resume to RAM support on Arm

 CHANGELOG.md                          |   2 +
 SUPPORT.md                            |   5 +-
 tools/include/libxl.h                 |   1 -
 tools/xl/xl.h                         |   4 +-
 tools/xl/xl_cmdtable.c                |   4 +-
 tools/xl/xl_migrate.c                 |   2 +-
 tools/xl/xl_saverestore.c             |   2 +-
 tools/xl/xl_vmcontrol.c               |  12 +--
 xen/arch/arm/domain.c                 |  17 +++--
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   2 +-
 xen/arch/arm/vpsci.c                  | 101 ++++++++++++++++++++++----
 xen/common/domain.c                   |  31 ++++++--
 xen/include/xen/sched.h               |   6 ++
 15 files changed, 148 insertions(+), 44 deletions(-)

-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Anthony PERARD ,
	Juergen Gross 
Subject: [PATCH v9 2/4] tools/xl: Allow compilation of 'xl resume' command on Arm
Date: Mon, 18 Aug 2025 11:49:25 +0300
Message-ID: <60c29f80837b0642fcf225aaff3cd2b07310c0ce.1755506449.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

The "xl resume" command was previously excluded from Arm builds because
system suspend/resume (e.g., SYSTEM_SUSPEND via vPSCI) was not
implemented. On x86, this command is used for resume.

This change enables compilation of `xl resume` on Arm regardless of the
underlying implementation status, making the tool available for testing
and future feature support. The relevant libxl infrastructure and handler
functions are already present and usable.

Note: This does not imply full system suspend/resume support on Arm.
      The `xl suspend` command still does not work on Arm platforms.

Signed-off-by: Mykola Kvach 
Acked-by: Anthony PERARD 
---
Changes in v7:
- dropped renaming of LIBXL_HAVE_NO_SUSPEND_RESUME macro

Changes in v6:
- Renamed macro from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND
  to better reflect the scope of this change
- Applied cosmetic changes based on review feedback
---
 tools/include/libxl.h     |  1 -
 tools/xl/xl.h             |  4 ++--
 tools/xl/xl_cmdtable.c    |  4 ++--
 tools/xl/xl_migrate.c     |  2 +-
 tools/xl/xl_saverestore.c |  2 +-
 tools/xl/xl_vmcontrol.c   | 12 ++++++------
 6 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/tools/include/libxl.h b/tools/include/libxl.h
index 185f74d8a8..b204fc5e2e 100644
--- a/tools/include/libxl.h
+++ b/tools/include/libxl.h
@@ -1140,7 +1140,6 @@ typedef struct libxl__ctx libxl_ctx;
  * restoring or migrating a domain. In this case the related functions
  * should be expected to return failure. That is:
  *  - libxl_domain_suspend
- *  - libxl_domain_resume
  *  - libxl_domain_remus_start
  */
 #if defined(__arm__) || defined(__aarch64__)
diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index 45745f0dbb..9233b73f85 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -65,7 +65,7 @@ static const char migrate_permission_to_go[]=
     "domain is yours, you are cleared to unpause";
 static const char migrate_report[]=
     "my copy unpause results are as follows";
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
   /* followed by one byte:
    *     0: everything went well, domain is running
@@ -130,8 +130,8 @@ int main_migrate_receive(int argc, char **argv);
 int main_save(int argc, char **argv);
 int main_migrate(int argc, char **argv);
 int main_suspend(int argc, char **argv);
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 int main_resume(int argc, char **argv);
-#endif
 int main_dump_core(int argc, char **argv);
 int main_pause(int argc, char **argv);
 int main_unpause(int argc, char **argv);
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 06a0039718..bcb2d233cc 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -198,12 +198,12 @@ const struct cmd_spec cmd_table[] = {
       "Suspend a domain to RAM",
       "",
     },
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "resume",
       &main_resume, 0, 1,
       "Resume a domain from RAM",
       "",
     },
-#endif
     { "dump-core",
       &main_dump_core, 0, 1,
       "Core dump a domain",
@@ -548,7 +548,7 @@ const struct cmd_spec cmd_table[] = {
       "                        checkpoint must be disabled.\n"
       "-p                      Use COLO userspace proxy."
     },
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "devd",
       &main_devd, 0, 1,
       "Daemon that listens for devices and launches backends",
diff --git a/tools/xl/xl_migrate.c b/tools/xl/xl_migrate.c
index b8594f44a5..4b4a379aa1 100644
--- a/tools/xl/xl_migrate.c
+++ b/tools/xl/xl_migrate.c
@@ -767,7 +767,7 @@ int main_remus(int argc, char **argv)
     close(send_fd);
     return EXIT_FAILURE;
 }
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 /*
diff --git a/tools/xl/xl_saverestore.c b/tools/xl/xl_saverestore.c
index 953d791d1a..747094ec7b 100644
--- a/tools/xl/xl_saverestore.c
+++ b/tools/xl/xl_saverestore.c
@@ -270,7 +270,7 @@ int main_save(int argc, char **argv)
     return EXIT_SUCCESS;
 }
 
-#endif /* LIBXL_HAVE_NO_SUSPEND_RESUME */
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 
diff --git a/tools/xl/xl_vmcontrol.c b/tools/xl/xl_vmcontrol.c
index c813732838..93766f631b 100644
--- a/tools/xl/xl_vmcontrol.c
+++ b/tools/xl/xl_vmcontrol.c
@@ -38,11 +38,6 @@ static void suspend_domain(uint32_t domid)
     libxl_domain_suspend_only(ctx, domid, NULL);
 }
 
-static void resume_domain(uint32_t domid)
-{
-    libxl_domain_resume(ctx, domid, 1, NULL);
-}
-
 int main_suspend(int argc, char **argv)
 {
     int opt;
@@ -55,6 +50,12 @@ int main_suspend(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
+
+static void resume_domain(uint32_t domid)
+{
+    libxl_domain_resume(ctx, domid, 1, NULL);
+}
 
 int main_resume(int argc, char **argv)
 {
@@ -68,7 +69,6 @@ int main_resume(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
-#endif
 
 static void pause_domain(uint32_t domid)
 {
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
Date: Mon, 18 Aug 2025 11:49:24 +0300
Message-ID: <205b2b354ff1d34d0e9ec4777ca3c94492f6d9d1.1755506449.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPSCI
(virtual PSCI) interface, allowing guests to request suspend via the PSCI
v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).

The implementation:
- Adds SYSTEM_SUSPEND function IDs to PSCI definitions
- Implements trapping and handling of SYSTEM_SUSPEND in vPSCI
- Allows only non-hardware domains to invoke SYSTEM_SUSPEND; for the
  hardware domain, PSCI_NOT_SUPPORTED is returned to avoid halting the
  system in hwdom_shutdown() called from domain_shutdown
- Ensures all secondary VCPUs of the calling domain are offline before
  allowing suspend due to PSCI spec

GIC and virtual timer context must be saved when the domain suspends.
This is done by moving the respective code in ctxt_switch_from
before the return that happens if the domain suspended.

domain_resume_nopause() is introduced to allow resuming a domain from
SYSTEM_SUSPEND without pausing it first. This avoids problematic
domain_pause() calls when resuming from suspend on Arm, particularly
in error paths. The function is only used on Arm; other architectures
continue to use the original domain_resume().

Usage:

For Linux-based guests, suspend can be initiated with:
    echo mem > /sys/power/state
or via:
    systemctl suspend

Resuming the guest is performed from control domain using:
      xl resume 

Signed-off-by: Mykola Kvach 
---
Changes in V9:
- no functional changes
- cosmetic chnages after review
- enhance commit message and add extra comment to the code after review

Changes in V8:
- GIC and virtual timer context must be saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Changes in V6:
- skip execution of ctxt_switch_from for vcpu that is in paused domain
- add implementation of domain_resume without domain_pause
- add helper function to determine if vcpu is suspended or not
- ignore upper 32 bits of argument values when the domain is 64-bit
  and calls the SMC32 SYSTEM_SUSPEND function
- cosmetic changes after review

Changes in V5:
- don't use standby mode, restore execution in a provided by guest point
- move checking that all CPUs, except current one, are offline to after
  pausing the vCPUs
- provide ret status from arch_domain_shutdown and handle it in
  domain_shutdown
- adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI functions

Changes in V4:
Dropped all changes related to watchdog, domain is marked as shutting
down in domain_shutdown and watchdog timeout handler won't trigger
because of it.

Previous versions included code to manage Xen watchdog timers during suspend,
but this was removed. When a guest OS starts the Xen watchdog (either via the
kernel driver or xenwatchdogd), it is responsible for managing that state
across suspend/resume. On Linux, the Xen kernel driver properly stops the
watchdog during suspend. However, when xenwatchdogd is used instead, suspend
handling is incomplete, potentially leading to watchdog-triggered resets on
resume. Xen leaves watchdog handling to the guest OS and its services.

Dropped all changes related to VCPU context, because instead domain_shutdown
is used, so we don't need any extra changes for suspending domain.

Changes in V3:
Dropped all domain flags and related code (which touched common functions like
vcpu_unblock), keeping only the necessary changes for Xen suspend/resume, i.e.
suspend/resume is now fully supported only for the hardware domain.
Proper support for domU suspend/resume will be added in a future patch.
This patch does not yet include VCPU context reset or domain context
restoration in VCPU.
---
 xen/arch/arm/domain.c                 |  17 +++--
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   2 +-
 xen/arch/arm/vpsci.c                  | 101 ++++++++++++++++++++++----
 xen/common/domain.c                   |  31 ++++++--
 xen/include/xen/sched.h               |   6 ++
 7 files changed, 131 insertions(+), 29 deletions(-)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 310c578909..9e9649c4e2 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -90,6 +90,16 @@ static void ctxt_switch_from(struct vcpu *p)
     if ( is_idle_vcpu(p) )
         return;
 
+    /* Arch timer */
+    p->arch.cntkctl = READ_SYSREG(CNTKCTL_EL1);
+    virt_timer_save(p);
+
+    /* VGIC */
+    gic_save_state(p);
+
+    if ( test_bit(_VPF_suspended, &p->pause_flags) )
+        return;
+
     p2m_save_state(p);
 
     /* CP 15 */
@@ -106,10 +116,6 @@ static void ctxt_switch_from(struct vcpu *p)
     p->arch.tpidrro_el0 = READ_SYSREG(TPIDRRO_EL0);
     p->arch.tpidr_el1 = READ_SYSREG(TPIDR_EL1);
 
-    /* Arch timer */
-    p->arch.cntkctl = READ_SYSREG(CNTKCTL_EL1);
-    virt_timer_save(p);
-
     if ( is_32bit_domain(p->domain) && cpu_has_thumbee )
     {
         p->arch.teecr = READ_SYSREG(TEECR32_EL1);
@@ -158,9 +164,6 @@ static void ctxt_switch_from(struct vcpu *p)
 
     /* XXX MPU */
 
-    /* VGIC */
-    gic_save_state(p);
-
     isb();
 }
 
diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/include/asm/perfc_defn.h
index effd25b69e..8dfcac7e3b 100644
--- a/xen/arch/arm/include/asm/perfc_defn.h
+++ b/xen/arch/arm/include/asm/perfc_defn.h
@@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system_reset")
 PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
 PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
 PERFCOUNTER(vpsci_features,            "vpsci: features")
+PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
 
 PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
 
diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/psci.h
index 4780972621..48a93e6b79 100644
--- a/xen/arch/arm/include/asm/psci.h
+++ b/xen/arch/arm/include/asm/psci.h
@@ -47,10 +47,12 @@ void call_psci_system_reset(void);
 #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
 #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
 #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
+#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
 
 #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
 #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
 #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
+#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
 
 /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
 #define PSCI_0_2_AFFINITY_LEVEL_ON      0
diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/asm/vpsci.h
index 0cca5e6830..69d40f9d7f 100644
--- a/xen/arch/arm/include/asm/vpsci.h
+++ b/xen/arch/arm/include/asm/vpsci.h
@@ -23,7 +23,7 @@
 #include 
 
 /* Number of function implemented by virtual PSCI (only 0.2 or later) */
-#define VPSCI_NR_FUNCS  12
+#define VPSCI_NR_FUNCS  14
 
 /* Functions handle PSCI calls from the guests */
 bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index 7ba9ccd94b..67d369a8a2 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -10,28 +10,18 @@
 
 #include 
 
-static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
-                            register_t context_id)
+static int do_setup_vcpu_ctx(struct vcpu *v, register_t entry_point,
+                      register_t context_id)
 {
-    struct vcpu *v;
     struct domain *d = current->domain;
     struct vcpu_guest_context *ctxt;
     int rc;
     bool is_thumb = entry_point & 1;
-    register_t vcpuid;
-
-    vcpuid = vaffinity_to_vcpuid(target_cpu);
-
-    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
-        return PSCI_INVALID_PARAMETERS;
 
     /* THUMB set is not allowed with 64-bit domain */
     if ( is_64bit_domain(d) && is_thumb )
         return PSCI_INVALID_ADDRESS;
 
-    if ( !test_bit(_VPF_down, &v->pause_flags) )
-        return PSCI_ALREADY_ON;
-
     if ( (ctxt = alloc_vcpu_guest_context()) == NULL )
         return PSCI_DENIED;
 
@@ -78,11 +68,32 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
     if ( rc < 0 )
         return PSCI_DENIED;
 
-    vcpu_wake(v);
-
     return PSCI_SUCCESS;
 }
 
+static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
+                            register_t context_id)
+{
+    int rc;
+    struct vcpu *v;
+    struct domain *d = current->domain;
+    register_t vcpuid;
+
+    vcpuid = vaffinity_to_vcpuid(target_cpu);
+
+    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
+        return PSCI_INVALID_PARAMETERS;
+
+    if ( !test_bit(_VPF_down, &v->pause_flags) )
+        return PSCI_ALREADY_ON;
+
+    rc = do_setup_vcpu_ctx(v, entry_point, context_id);
+    if ( rc == PSCI_SUCCESS )
+        vcpu_wake(v);
+
+    return rc;
+}
+
 static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
 {
     int32_t ret;
@@ -197,6 +208,48 @@ static void do_psci_0_2_system_reset(void)
     domain_shutdown(d,SHUTDOWN_reboot);
 }
 
+static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid)
+{
+    int32_t rc;
+    struct vcpu *v;
+    struct domain *d = current->domain;
+
+    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
+    if ( is_hardware_domain(d) )
+        return PSCI_NOT_SUPPORTED;
+
+    /* Ensure that all CPUs other than the calling one are offline */
+    domain_lock(d);
+    for_each_vcpu ( d, v )
+    {
+        if ( v != current && is_vcpu_online(v) )
+        {
+            domain_unlock(d);
+            return PSCI_DENIED;
+        }
+    }
+    domain_unlock(d);
+
+    rc = domain_shutdown(d, SHUTDOWN_suspend);
+    if ( rc )
+        return PSCI_DENIED;
+
+    rc = do_setup_vcpu_ctx(current, epoint, cid);
+    if ( rc != PSCI_SUCCESS )
+    {
+        domain_resume_nopause(d);
+        return rc;
+    }
+
+    set_bit(_VPF_suspended, ¤t->pause_flags);
+
+    dprintk(XENLOG_DEBUG,
+            "Dom %u: SYSTEM_SUSPEND requested, epoint=%#lx, cid=%#lx\n",
+            d->domain_id, epoint, cid);
+
+    return rc;
+}
+
 static int32_t do_psci_1_0_features(uint32_t psci_func_id)
 {
     /* /!\ Ordered by function ID and not name */
@@ -214,6 +267,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id)
     case PSCI_0_2_FN32_SYSTEM_OFF:
     case PSCI_0_2_FN32_SYSTEM_RESET:
     case PSCI_1_0_FN32_PSCI_FEATURES:
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
     case ARM_SMCCC_VERSION_FID:
         return 0;
     default:
@@ -344,6 +399,24 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
         return true;
     }
 
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
+    {
+        register_t epoint = PSCI_ARG(regs, 1);
+        register_t cid = PSCI_ARG(regs, 2);
+
+        if ( is_64bit_domain(current->domain) &&
+             fid == PSCI_1_0_FN32_SYSTEM_SUSPEND )
+        {
+            epoint &= GENMASK(31, 0);
+            cid &= GENMASK(31, 0);
+        }
+
+        perfc_incr(vpsci_system_suspend);
+        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
+        return true;
+    }
+
     default:
         return false;
     }
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 5241a1629e..624c3e2c27 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -1343,16 +1343,13 @@ int domain_shutdown(struct domain *d, u8 reason)
     return 0;
 }
 
-void domain_resume(struct domain *d)
+#ifndef CONFIG_ARM
+static
+#endif
+void domain_resume_nopause(struct domain *d)
 {
     struct vcpu *v;
 
-    /*
-     * Some code paths assume that shutdown status does not get reset under
-     * their feet (e.g., some assertions make this assumption).
-     */
-    domain_pause(d);
-
     spin_lock(&d->shutdown_lock);
 
     d->is_shutting_down = d->is_shut_down = 0;
@@ -1360,13 +1357,33 @@ void domain_resume(struct domain *d)
 
     for_each_vcpu ( d, v )
     {
+        /*
+         * No need to conditionally clear _VPF_suspended here:
+         * - This bit is only set on Arm64, and only after a successful suspend.
+         * - domain_resume_nopause() may also be called from paths other than
+         *   the suspend/resume flow, such as "soft-reset" actions (e.g.,
+         *   on_poweroff), as part of the Xenstore control/shutdown protocol.
+         *   These require guest acknowledgement to complete the operation.
+         * So clearing the bit unconditionally is safe.
+         */
+        clear_bit(_VPF_suspended, &v->pause_flags);
+
         if ( v->paused_for_shutdown )
             vcpu_unpause(v);
         v->paused_for_shutdown = 0;
     }
 
     spin_unlock(&d->shutdown_lock);
+}
 
+void domain_resume(struct domain *d)
+{
+    /*
+     * Some code paths assume that shutdown status does not get reset under
+     * their feet (e.g., some assertions make this assumption).
+     */
+    domain_pause(d);
+    domain_resume_nopause(d);
     domain_unpause(d);
 }
 
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index fd5c9f9333..c1848d8ea6 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -814,6 +814,9 @@ void domain_destroy(struct domain *d);
 int domain_kill(struct domain *d);
 int domain_shutdown(struct domain *d, u8 reason);
 void domain_resume(struct domain *d);
+#ifdef CONFIG_ARM
+void domain_resume_nopause(struct domain *d);
+#endif
 
 int domain_soft_reset(struct domain *d, bool resuming);
 
@@ -1010,6 +1013,9 @@ static inline struct domain *next_domain_in_cpupool(
 /* VCPU is parked. */
 #define _VPF_parked          8
 #define VPF_parked           (1UL<<_VPF_parked)
+/* VCPU is suspended. */
+#define _VPF_suspended       9
+#define VPF_suspended        (1UL << _VPF_suspended)
 
 static inline bool vcpu_runnable(const struct vcpu *v)
 {
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v9 4/4] CHANGELOG: Document guest suspend/resume to RAM support on Arm
Date: Mon, 18 Aug 2025 11:49:27 +0300
Message-ID: <5d570383467445e4c89347d1cab7f4a3f062e740.1755506449.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

Mention the newly added support for guest suspend and resume to/from
RAM via vPSCI on Arm platforms.

This support is limited to non-hardware domain guests.

Signed-off-by: Mykola Kvach 
Acked-by: Oleksii Kurochko 
---
Chnages in v6:
- removed reduntand explanation that thi support added for
  both arm32 and arm64.

Changes in v5:
- adjustments to the commit title and message
- expanded the changelog entry to include more context about
  suspend/resume support introduced in this patch series
---
 CHANGELOG.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe..7e42ca9b59 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -29,6 +29,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 
  - On Arm:
     - Ability to enable stack protector
+    - Support for guest suspend and resume to/from RAM via vPSCI.
+      Applies only to non-hardware domain guests.
 
 ### Removed
  - On x86:
-- 
2.48.1



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From: Mykola Kvach 
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Subject: Re: [PATCH v8 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Jan Beulich 
Cc: Mykola Kvach , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Andrew Cooper , Anthony PERARD , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	xen-devel@lists.xenproject.org
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Hi Jan,

On Fri, Aug 8, 2025 at 9:33=E2=80=AFAM Jan Beulich  wrot=
e:
>
> On 07.08.2025 21:39, Mykola Kvach wrote:
> > From: Mykola Kvach 
> >
> > This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPS=
CI
> > (virtual PSCI) interface, allowing guests to request suspend via the PS=
CI
> > v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).
> >
> > The implementation:
> > - Adds SYSTEM_SUSPEND function IDs to PSCI definitions
> > - Implements trapping and handling of SYSTEM_SUSPEND in vPSCI
> > - Allows only non-hardware domains to invoke SYSTEM_SUSPEND; for the
> >   hardware domain, PSCI_NOT_SUPPORTED is returned to avoid halting the
> >   system in hwdom_shutdown() called from domain_shutdown
> > - Ensures all secondary VCPUs of the calling domain are offline before
> >   allowing suspend due to PSCI spec
> >
> > GIC and virtual timer context must be saved when the domain suspends.
> > This is done by moving the respective code in ctxt_switch_from
> > before the return that happens if the domain suspended.
> >
> > Usage:
> >
> > For Linux-based guests, suspend can be initiated with:
> >     echo mem > /sys/power/state
> > or via:
> >     systemctl suspend
> >
> > Resuming the guest is performed from control domain using:
> >       xl resume 
> >
> > Signed-off-by: Mykola Kvach 
>
> Nothing is being said on why domain_resume_nopause() would be needed. Whi=
le this
> may be entirely obvious to Arm people, the change is done in common code.
>
> > --- a/xen/common/domain.c
> > +++ b/xen/common/domain.c
> > @@ -1343,16 +1343,13 @@ int domain_shutdown(struct domain *d, u8 reason=
)
> >      return 0;
> >  }
> >
> > -void domain_resume(struct domain *d)
> > +#ifndef CONFIG_ARM
> > +static
> > +#endif
> > +void domain_resume_nopause(struct domain *d)
> >  {
> >      struct vcpu *v;
> >
> > -    /*
> > -     * Some code paths assume that shutdown status does not get reset =
under
> > -     * their feet (e.g., some assertions make this assumption).
> > -     */
> > -    domain_pause(d);
> > -
> >      spin_lock(&d->shutdown_lock);
> >
> >      d->is_shutting_down =3D d->is_shut_down =3D 0;
> > @@ -1360,13 +1357,24 @@ void domain_resume(struct domain *d)
> >
> >      for_each_vcpu ( d, v )
> >      {
> > +        clear_bit(_VPF_suspended, &v->pause_flags);
>
> Similarly it's not becoming clear why unconditionally doing this here wou=
ld
> be correct (now and going forward). There are other calls to this functio=
n,
> after all.
>
> > --- a/xen/include/xen/sched.h
> > +++ b/xen/include/xen/sched.h
> > @@ -814,6 +814,9 @@ void domain_destroy(struct domain *d);
> >  int domain_kill(struct domain *d);
> >  int domain_shutdown(struct domain *d, u8 reason);
> >  void domain_resume(struct domain *d);
> > +#ifdef CONFIG_ARM
> > +void domain_resume_nopause(struct domain *d);
> > +#endif
> >
> >  int domain_soft_reset(struct domain *d, bool resuming);
> >
> > @@ -1010,6 +1013,9 @@ static inline struct domain *next_domain_in_cpupo=
ol(
> >  /* VCPU is parked. */
> >  #define _VPF_parked          8
> >  #define VPF_parked           (1UL<<_VPF_parked)
> > +/* VCPU is suspended. */
> > +#define _VPF_suspended 9
> > +#define VPF_suspended (1UL<<_VPF_suspended)
>
> And then, even if it's "only" style: With how adjacent code is formatted,
> how come there's no suitable blank padding here? If anything wants (and
> really needs) doing differently from pre-existing code, then to have
> blanks around the << as well.

Thank you for reviewing this patch series.
All your comments have been addressed in the next version of this patch
series, V9.

Best regards,
Mykola

>
> Jan


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Subject: Re: [PATCH 21/22] x86/traps: Introduce FRED entrypoints
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14.08.2025 22:40, Andrew Cooper wrote:
> On 14/08/2025 4:57 pm, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> --- /dev/null
>>> +++ b/xen/arch/x86/x86_64/entry-fred.S
>>> @@ -0,0 +1,35 @@
>>> +/* SPDX-License-Identifier: GPL-2.0-or-later */
>>> +
>>> +        .file "x86_64/entry-fred.S"
>>> +
>>> +#include 
>>> +#include 
>>> +
>>> +        .section .text.entry, "ax", @progbits
>>> +
>>> +        /* The Ring3 entry point is required to be 4k aligned. */
>>> +
>>> +FUNC(entry_FRED_R3, 4096)
>> ... doesn't this 4k-alignment requirement suggest we want to put
>> entry-fred.o first?
> 
> Perhaps, but that is quite subtle.  I did also consider a
> .text.entry.page_aligned section, but .text.entry only matters for XPTI
> which (as agreed), I'm not intending to implement in FRED mode unless it
> proves to be necessary.
> 
> Also IIRC there's still a symbol bug where _sentrytext takes priority
> over entry_FRED_R3, so the backtrace is effectively wrong.
> 
> (These are all bad excuses, but some parts of this series are rather old.)
> 
>>  Also, might it be more natural to use PAGE_SIZE
>> here?
> 
> I did debate that, but the spec uses 0xfff, not pages, even if the
> pipline surely does have an optimisation for chopping 12 metadata bits
> off the bottom of a pointer.

I found this, though:

"Bits 63:12 contain the upper bits of the linear address of a page in memory
 containing event handlers. FRED event delivery will load RIP to refer to an
 entry point on this page. See Section 5.1.1."

Jan


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From: Mykola Kvach 
Date: Mon, 18 Aug 2025 11:51:19 +0300
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Subject: Re: [PATCH v2] xen/arm: irq: add missing spin_unlock() in
 init_local_irq_data() error path
To: Julien Grall 
Cc: xen-devel@lists.xenproject.org, Mykola Kvach , 
	Stefano Stabellini , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Denis Mukhin 
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On Tue, Aug 12, 2025 at 2:07=E2=80=AFPM Julien Grall  wrote=
:
>
>
>
> On 11/08/2025 18:28, Julien Grall wrote:
> > Hi Mykola,
> >
> > On 11/08/2025 09:45, Mykola Kvach wrote:
> >> From: Mykola Kvach 
> >>
> >> If init_one_irq_desc() fails, init_local_irq_data() returns without
> >> releasing local_irqs_type_lock, leading to a possible deadlock.
> >>
> >> Release the lock before returning to ensure proper cleanup.
> >>
> >> Fixes: 2bb32b809250 ("xen/irq: Propagate the error from
> >> init_one_desc_irq() in init_*_irq_data()")
> >> Signed-off-by: Mykola Kvach 
> >> Reviewed-by: Denis Mukhin 
> >
> > Acked-by: Julien Grall 
> >
> > I will commit the patch soon.
>
> This is now merged.

Thanks everyone for the reviews and merging!

Best regards,
Mykola

>
> Cheers,
>
> --
> Julien Grall
>


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Date: Mon, 18 Aug 2025 11:02:11 +0200
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Subject: Re: [PATCH 13/22] x86: FRED enumerations
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-14-andrew.cooper3@citrix.com>
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On 08.08.2025 22:23, Andrew Cooper wrote:
> Of note, CR4.FRED is bit 32 and cannot enabled outside of 64bit mode.
> 
> Most supported toolchains don't understand the FRED instructions yet.  ERETU
> and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC), while LKGS is
> more complicated and deferred for now.
> 
> I have intentionally named the FRED MSRs differently to the spec.  In the
> spec, the stack pointer names alias the TSS fields of the same name, despite
> very different semantics.

Hmm, looking at this again I'm not entirely convinced: Staying in sync with
the spec also has its merits, and the FRED infix is sufficiently distinguishing
imo.

Jan


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Subject: Re: [PATCH] arm/link: Remove exception table sections
To: Andrew Cooper ,
 Xen-devel 
Cc: Stefano Stabellini ,
 Volodymyr Babchuk ,
 Bertrand Marquis ,
 Michal Orzel 
References: <20250818081824.3538065-1-andrew.cooper3@citrix.com>
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Hi Andrew,

On 18/08/2025 09:18, Andrew Cooper wrote:
> This was almost certainly copy&paste from x86.  ARM does not us these nor
> selects HAS_EX_TABLE, so drop the sections and their boundary markers.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Julien Grall 

Cheers,

> ---
> CC: Stefano Stabellini 
> CC: Julien Grall 
> CC: Volodymyr Babchuk 
> CC: Bertrand Marquis 
> CC: Michal Orzel 
> 
> Found because I'm getting rid of .ex_table.pre on x86 too.
> ---
>   xen/arch/arm/xen.lds.S | 10 ----------
>   1 file changed, 10 deletions(-)
> 
> diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S
> index 9f30c3a13ed1..db17ff1efa98 100644
> --- a/xen/arch/arm/xen.lds.S
> +++ b/xen/arch/arm/xen.lds.S
> @@ -86,16 +86,6 @@ SECTIONS
>     } : text
>   
>     .data.read_mostly : {
> -       /* Exception table */
> -       __start___ex_table = .;
> -       *(.ex_table)
> -       __stop___ex_table = .;
> -
> -       /* Pre-exception table */
> -       __start___pre_ex_table = .;
> -       *(.ex_table.pre)
> -       __stop___pre_ex_table = .;
> -
>          *(.data.read_mostly)
>     } :text
>   

-- 
Julien Grall



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Subject: Re: [PATCH] docs/sending-patches: add GitLab pipeline link
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To: Stefano Stabellini ,
 xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech,
 michal.orzel@amd.com, jbeulich@suse.com, roger.pau@citrix.com
References: 
From: Julien Grall 
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Hi Stefano,

On 15/08/2025 21:12, Stefano Stabellini wrote:
> When submitting patches to xen-devel, add a link to a successful
> pipeline run.

Does this mean we have enough capacity to handle normal CI job + submission?

Also, as we try to encourage people to use the gitlab CI. So we would 
probably also encourage them to write new tests because in a lot of 
cases we will add new code. So the pipeline is only going to confirm 
that we are regressing existing tests (which may be irrelevant to the 
subsystem modified).
> 
> Signed-off-by: Stefano Stabellini 
> 
> diff --git a/docs/process/sending-patches.pandoc b/docs/process/sending-patches.pandoc
> index 1991932b68..6e1401ea22 100644
> --- a/docs/process/sending-patches.pandoc
> +++ b/docs/process/sending-patches.pandoc
> @@ -314,3 +314,23 @@ A patch should always be sent **to** the xen-devel mailing list
>   of all touched code areas should get a copy of the mail via **Cc**. In case
>   some other recipients are known to be interested in the patch, they can be
>   added via **Cc**, too.
> +
> +## Testing
> +
> +Xen Project uses a GitLab-based CI infrastructure. You can request to
> +have your GitLab account added to the Xen Project organization on GitLab
> +(https://gitlab.com/xen-project) by reaching out to THE REST maintainers
> +via xen-devel or Matrix. Once your account is added to the Xen Project
> +organization on GitLab, also a personal Xen repository will be created
> +for you under https://gitlab.com/xen-project/people//xen.
> +You will be able to trigger a GitLab testing pipeline with a single git
> +push to your personal Xen repository.

I think it would be worth mentioning that this should be based on a 
recent "master" (I would say less than two days old).

Also, can you clarify why we are asking the user to trigger the pipeline 
rather than having a both that will pick a series and test it?

> +
> +When submitting a non-trivial patch or a non-trivial patch series,

This wording is ambiguous. But even trivial patch could result to 
regression. So I am not sure why we would want to exclude them. Can you 
clarify?

> +please include a link to the successful GitLab pipeline run on your
> +personal branch. This information can be added after the `---` line.
 >> +For example:
> +
> +    ---
> +    Test CI pipeline:
> +    https://gitlab.com/xen-project/people/your-username/xen/-/pipelines/1980129839

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH 22/22] x86/traps: Enable FRED when requested
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-23-andrew.cooper3@citrix.com>
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On 08.08.2025 22:23, Andrew Cooper wrote:
> With the shadow stack and exception handling adjustements in place, we can now
> activate FRED when appropriate.  Note that opt_fred is still disabled by
> default.
> 
> Introduce init_fred() to set up all the MSRs relevant for FRED.  FRED uses
> MSR_STAR (entries from Ring3 only), and MSR_FRED_SSP_SL0 aliases MSR_PL0_SSP
> when CET-SS is active.  Otherwise, they're all new MSRs.
> 
> With init_fred() existing, load_system_tables() and legacy_syscall_init()
> should only be used when setting up IDT delivery.  Insert ASSERT()s to this
> effect, and adjust the various *_init() functions to make this property true.
> 
> Per the documentation, ap_early_traps_init() is responsible for switching off
> the boot GDT, which needs doing even in FRED mode.
> 
> Finally, set CR4.FRED in {bsp,ap}_early_traps_init().

Probably you've done that already, but these last two paragraphs will need
updating following patch 08 v1.1.

> Xen can now boot in FRED mode up until starting a PV guest, where it faults
> because IRET is not permitted to change privilege.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 

> @@ -274,6 +279,44 @@ static void __init init_ler(void)
>      setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
>  }
>  
> +/*
> + * Set up all MSRs relevant for FRED event delivery.
> + *
> + * Xen does not use any of the optional config in MSR_FRED_CONFIG, so all that
> + * is needed is the entrypoint.
> + *
> + * Because FRED always provides a good stack, NMI and #DB do not need any
> + * special treatment.  Only #DF needs another stack level, and #MC for the
> + * offchance that Xen's main stack suffers an uncorrectable error.
> + *
> + * FRED reuses MSR_STAR to provide the segment selector values to load on
> + * entry from Ring3.  Entry from Ring0 leave %cs and %ss unmodified.
> + */
> +static void init_fred(void)
> +{
> +    unsigned long stack_top = get_stack_bottom() & ~(STACK_SIZE - 1);
> +
> +    ASSERT(opt_fred == 1);
> +
> +    wrmsrns(MSR_STAR, XEN_MSR_STAR);
> +    wrmsrns(MSR_FRED_CONFIG, (unsigned long)entry_FRED_R3);
> +
> +    wrmsrns(MSR_FRED_RSP_SL0, (unsigned long)(&get_cpu_info()->_fred + 1));
> +    wrmsrns(MSR_FRED_RSP_SL1, 0);

In the event of a bug somewhere causing this slot to be accessed, is the
wrapping behavior well-defined, resulting in an attempt to write to the
top end of VA space? (Then again, if the wrapping itself caused a fault,
the overall effect would be largely the same - in many cases #DF.)

Jan


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Subject: Re: [PATCH 22/22] x86/traps: Enable FRED when requested
To: Jan Beulich 
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 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 18/08/2025 10:35 am, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> With the shadow stack and exception handling adjustements in place, we can now
>> activate FRED when appropriate.  Note that opt_fred is still disabled by
>> default.
>>
>> Introduce init_fred() to set up all the MSRs relevant for FRED.  FRED uses
>> MSR_STAR (entries from Ring3 only), and MSR_FRED_SSP_SL0 aliases MSR_PL0_SSP
>> when CET-SS is active.  Otherwise, they're all new MSRs.
>>
>> With init_fred() existing, load_system_tables() and legacy_syscall_init()
>> should only be used when setting up IDT delivery.  Insert ASSERT()s to this
>> effect, and adjust the various *_init() functions to make this property true.
>>
>> Per the documentation, ap_early_traps_init() is responsible for switching off
>> the boot GDT, which needs doing even in FRED mode.
>>
>> Finally, set CR4.FRED in {bsp,ap}_early_traps_init().
> Probably you've done that already, but these last two paragraphs will need
> updating following patch 08 v1.1.

It's on my list, but not done yet.

>
>> Xen can now boot in FRED mode up until starting a PV guest, where it faults
>> because IRET is not permitted to change privilege.
>>
>> Signed-off-by: Andrew Cooper 
> Reviewed-by: Jan Beulich 

Thanks, but I fear this patch has changed too much.  I'll take a
decision when I've cleaned up the integration of the PV work.

>
>> @@ -274,6 +279,44 @@ static void __init init_ler(void)
>>      setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
>>  }
>>  
>> +/*
>> + * Set up all MSRs relevant for FRED event delivery.
>> + *
>> + * Xen does not use any of the optional config in MSR_FRED_CONFIG, so all that
>> + * is needed is the entrypoint.
>> + *
>> + * Because FRED always provides a good stack, NMI and #DB do not need any
>> + * special treatment.  Only #DF needs another stack level, and #MC for the
>> + * offchance that Xen's main stack suffers an uncorrectable error.
>> + *
>> + * FRED reuses MSR_STAR to provide the segment selector values to load on
>> + * entry from Ring3.  Entry from Ring0 leave %cs and %ss unmodified.
>> + */
>> +static void init_fred(void)
>> +{
>> +    unsigned long stack_top = get_stack_bottom() & ~(STACK_SIZE - 1);
>> +
>> +    ASSERT(opt_fred == 1);
>> +
>> +    wrmsrns(MSR_STAR, XEN_MSR_STAR);
>> +    wrmsrns(MSR_FRED_CONFIG, (unsigned long)entry_FRED_R3);
>> +
>> +    wrmsrns(MSR_FRED_RSP_SL0, (unsigned long)(&get_cpu_info()->_fred + 1));
>> +    wrmsrns(MSR_FRED_RSP_SL1, 0);
> In the event of a bug somewhere causing this slot to be accessed, is the
> wrapping behavior well-defined, resulting in an attempt to write to the
> top end of VA space? (Then again, if the wrapping itself caused a fault,
> the overall effect would be largely the same - in many cases #DF.)

The wrapping is well defined - like other cases, it goes to the top of
address space, but that's owned by PV guests.  SMAP ought to mitigate
what would otherwise be a priv-esc.

With IDT, we poisoned the unused pointers with non-canonical addresses,
but that's not possible here, as they're MSRs and checked at this point,
rather than when they're used.

I suspect the best we can do is reuse the #DB or NMI stacks, and
intentionally reverse the regular and shadow stack pointers, meaning
that any attempt to use SL1 will hit a guard page and escalate to #DF.

~Andrew


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Subject: Re: [PATCH 22/22] x86/traps: Enable FRED when requested
To: Andrew Cooper 
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 Xen-devel 
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On 18.08.2025 11:47, Andrew Cooper wrote:
> On 18/08/2025 10:35 am, Jan Beulich wrote:
>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>> With the shadow stack and exception handling adjustements in place, we can now
>>> activate FRED when appropriate.  Note that opt_fred is still disabled by
>>> default.
>>>
>>> Introduce init_fred() to set up all the MSRs relevant for FRED.  FRED uses
>>> MSR_STAR (entries from Ring3 only), and MSR_FRED_SSP_SL0 aliases MSR_PL0_SSP
>>> when CET-SS is active.  Otherwise, they're all new MSRs.
>>>
>>> With init_fred() existing, load_system_tables() and legacy_syscall_init()
>>> should only be used when setting up IDT delivery.  Insert ASSERT()s to this
>>> effect, and adjust the various *_init() functions to make this property true.
>>>
>>> Per the documentation, ap_early_traps_init() is responsible for switching off
>>> the boot GDT, which needs doing even in FRED mode.
>>>
>>> Finally, set CR4.FRED in {bsp,ap}_early_traps_init().
>> Probably you've done that already, but these last two paragraphs will need
>> updating following patch 08 v1.1.
> 
> It's on my list, but not done yet.
> 
>>
>>> Xen can now boot in FRED mode up until starting a PV guest, where it faults
>>> because IRET is not permitted to change privilege.
>>>
>>> Signed-off-by: Andrew Cooper 
>> Reviewed-by: Jan Beulich 
> 
> Thanks, but I fear this patch has changed too much.  I'll take a
> decision when I've cleaned up the integration of the PV work.
> 
>>
>>> @@ -274,6 +279,44 @@ static void __init init_ler(void)
>>>      setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
>>>  }
>>>  
>>> +/*
>>> + * Set up all MSRs relevant for FRED event delivery.
>>> + *
>>> + * Xen does not use any of the optional config in MSR_FRED_CONFIG, so all that
>>> + * is needed is the entrypoint.
>>> + *
>>> + * Because FRED always provides a good stack, NMI and #DB do not need any
>>> + * special treatment.  Only #DF needs another stack level, and #MC for the
>>> + * offchance that Xen's main stack suffers an uncorrectable error.
>>> + *
>>> + * FRED reuses MSR_STAR to provide the segment selector values to load on
>>> + * entry from Ring3.  Entry from Ring0 leave %cs and %ss unmodified.
>>> + */
>>> +static void init_fred(void)
>>> +{
>>> +    unsigned long stack_top = get_stack_bottom() & ~(STACK_SIZE - 1);
>>> +
>>> +    ASSERT(opt_fred == 1);
>>> +
>>> +    wrmsrns(MSR_STAR, XEN_MSR_STAR);
>>> +    wrmsrns(MSR_FRED_CONFIG, (unsigned long)entry_FRED_R3);
>>> +
>>> +    wrmsrns(MSR_FRED_RSP_SL0, (unsigned long)(&get_cpu_info()->_fred + 1));
>>> +    wrmsrns(MSR_FRED_RSP_SL1, 0);
>> In the event of a bug somewhere causing this slot to be accessed, is the
>> wrapping behavior well-defined, resulting in an attempt to write to the
>> top end of VA space? (Then again, if the wrapping itself caused a fault,
>> the overall effect would be largely the same - in many cases #DF.)
> 
> The wrapping is well defined - like other cases, it goes to the top of
> address space, but that's owned by PV guests.  SMAP ought to mitigate
> what would otherwise be a priv-esc.
> 
> With IDT, we poisoned the unused pointers with non-canonical addresses,
> but that's not possible here, as they're MSRs and checked at this point,
> rather than when they're used.
> 
> I suspect the best we can do is reuse the #DB or NMI stacks, and
> intentionally reverse the regular and shadow stack pointers, meaning
> that any attempt to use SL1 will hit a guard page and escalate to #DF.

I was wondering whether to store the upper end of zero_page[]. Or else
point into entirely unmapped space.

Jan


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Subject: Re: [PATCH 23/22] x86/vmx: Adjust NMI handling for FRED
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 09.08.2025 01:49, Andrew Cooper wrote:
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -4209,8 +4209,18 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_regs *regs)
>               ((intr_info & INTR_INFO_INTR_TYPE_MASK) ==
>                MASK_INSR(X86_ET_NMI, INTR_INFO_INTR_TYPE_MASK)) )
>          {
> -            do_nmi(regs);
> -            enable_nmis();
> +            /*
> +             * If we exited because of an NMI, NMIs are blocked in hardware,
> +             * but software is expected to invoke the handler.
> +             *
> +             * Use INT $2.  Combined with the current state, it is the correct
> +             * architectural state for the NMI handler,

Not quite, I would say: For profiling (and anything else which may want to
look at the outer context's register state from within the handler) we'd
always appear to have been in Xen when the NMI "occurred".

> and the IRET on the
> +             * way back out will unblock NMIs.
> +             *
> +             * In FRED mode, we can spot this trick and cause the ERETS to
> +             * unblock NMIs too.
> +             */
> +            asm ("int $2");
>          }
>          break;
>      case EXIT_REASON_MCE_DURING_VMENTRY:
> --- a/xen/arch/x86/traps.c
> +++ b/xen/arch/x86/traps.c
> @@ -2285,8 +2285,22 @@ void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
>          do_nmi(regs);
>          break;
>  
> -    case X86_ET_HW_EXC:
>      case X86_ET_SW_INT:
> +        if ( regs->fred_ss.vector == 2 )
> +        {
> +            /*
> +             * Explicit request from the the VMExit handler.  Rewrite the FRED
> +             * frame to look like it was a real NMI, and go around again.
> +             */
> +            regs->fred_ss.swint = false;
> +            regs->fred_ss.nmi = true;
> +            regs->fred_ss.type = X86_ET_NMI;
> +            regs->fred_ss.insnlen = 0;
> +
> +            return entry_from_xen(regs);

Any particular reason to use recursion here (which the compiler may or may
not transform)? In fact I'm having trouble seeing why you couldn't invoke
do_nmi() here directly.

Jan


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Date: Mon, 18 Aug 2025 12:03:39 +0200
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Subject: Re: [PATCH 21/22] x86/traps: Introduce FRED entrypoints
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-22-andrew.cooper3@citrix.com>
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From: Jan Beulich 
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On 08.08.2025 22:23, Andrew Cooper wrote:
> Under FRED, there's one entrypoint from Ring 3, and one from Ring 0.
> 
> FRED gives us a good stack (even for SYSCALL/SYSENTER), and a unified event
> frame on the stack, meaing that all software needs to do is spill the GPRs
> with a line of PUSHes.  Introduce PUSH_AND_CLEAR_GPRS and POP_GPRS for this
> purpose.
> 
> Introduce entry_FRED_R0() which to a first appoximation is complete for all
> event handling within Xen.
> 
> entry_FRED_R0() needs deriving from entry_FRED_R3(), so introduce a basic
> handler.  There is more work required to make the return-to-guest path work
> under FRED, so leave a BUG clearly in place.
> 
> Also introduce entry_from_{xen,pv}() to be the C level handlers.  By simply
> copying regs->fred_ss.vector into regs->entry_vector, we can reuse all the
> existing fault handlers.
> 
> Extend fatal_trap() to render the event type, including by name, when FRED is
> active.  This is slightly complicated, because X86_ET_OTHER must not use
> vector_name() or SYSCALL and SYSENTER get rendered as #BP and #DB.  Also,
> {read,write}_gs_shadow() needs modifying to avoid the SWAPGS instruction,
> which is disallowed in FRED mode.
> 
> This is sufficient to handle all interrupts and exceptions encountered during
> development, including plenty of Double Faults.
> 
> Signed-off-by: Andrew Cooper 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
> 
> SIMICS hasn't been updated to the FRED v9, and still wants ENDBR instructions
> at the entrypoints.
> ---
>  xen/arch/x86/include/asm/asm_defns.h |  65 ++++++++++++
>  xen/arch/x86/include/asm/msr.h       |   8 +-
>  xen/arch/x86/traps.c                 | 153 ++++++++++++++++++++++++++-
>  xen/arch/x86/x86_64/Makefile         |   1 +
>  xen/arch/x86/x86_64/entry-fred.S     |  35 ++++++
>  5 files changed, 256 insertions(+), 6 deletions(-)
>  create mode 100644 xen/arch/x86/x86_64/entry-fred.S
> 
> diff --git a/xen/arch/x86/include/asm/asm_defns.h b/xen/arch/x86/include/asm/asm_defns.h
> index 72a0082d319d..a81a4043d0f1 100644
> --- a/xen/arch/x86/include/asm/asm_defns.h
> +++ b/xen/arch/x86/include/asm/asm_defns.h
> @@ -315,6 +315,71 @@ static always_inline void stac(void)
>          subq  $-(UREGS_error_code-UREGS_r15+\adj), %rsp
>  .endm
>  
> +/*
> + * Push and clear GPRs
> + */
> +.macro PUSH_AND_CLEAR_GPRS
> +        push  %rdi
> +        xor   %edi, %edi
> +        push  %rsi
> +        xor   %esi, %esi
> +        push  %rdx
> +        xor   %edx, %edx
> +        push  %rcx
> +        xor   %ecx, %ecx
> +        push  %rax
> +        xor   %eax, %eax
> +        push  %r8
> +        xor   %r8d, %r8d
> +        push  %r9
> +        xor   %r9d, %r9d
> +        push  %r10
> +        xor   %r10d, %r10d
> +        push  %r11
> +        xor   %r11d, %r11d
> +        push  %rbx
> +        xor   %ebx, %ebx
> +        push  %rbp
> +#ifdef CONFIG_FRAME_POINTER
> +/* Indicate special exception stack frame by inverting the frame pointer. */
> +        mov   %rsp, %rbp
> +        notq  %rbp
> +#else
> +        xor   %ebp, %ebp
> +#endif
> +        push  %r12
> +        xor   %r12d, %r12d
> +        push  %r13
> +        xor   %r13d, %r13d
> +        push  %r14
> +        xor   %r14d, %r14d
> +        push  %r15
> +        xor   %r15d, %r15d
> +.endm
> +
> +/*
> + * POP GPRs from a UREGS_* frame on the stack.  Does not modify flags.
> + *
> + * @rax: Alternative destination for the %rax value on the stack.
> + */
> +.macro POP_GPRS rax=%rax
> +        pop   %r15
> +        pop   %r14
> +        pop   %r13
> +        pop   %r12
> +        pop   %rbp
> +        pop   %rbx
> +        pop   %r11
> +        pop   %r10
> +        pop   %r9
> +        pop   %r8
> +        pop   \rax
> +        pop   %rcx
> +        pop   %rdx
> +        pop   %rsi
> +        pop   %rdi
> +.endm
> +
>  #ifdef CONFIG_PV32
>  #define CR4_PV32_RESTORE                               \
>      ALTERNATIVE_2 "",                                  \
> diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
> index b6b85b04c3fd..01f510315ffe 100644
> --- a/xen/arch/x86/include/asm/msr.h
> +++ b/xen/arch/x86/include/asm/msr.h
> @@ -202,9 +202,9 @@ static inline unsigned long read_gs_base(void)
>  
>  static inline unsigned long read_gs_shadow(void)
>  {
> -    unsigned long base;
> +    unsigned long base, cr4 = read_cr4();
>  
> -    if ( read_cr4() & X86_CR4_FSGSBASE )
> +    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
>      {
>          asm volatile ( "swapgs" );
>          base = __rdgsbase();
> @@ -234,7 +234,9 @@ static inline void write_gs_base(unsigned long base)
>  
>  static inline void write_gs_shadow(unsigned long base)
>  {
> -    if ( read_cr4() & X86_CR4_FSGSBASE )
> +    unsigned long cr4 = read_cr4();
> +
> +    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
>      {
>          asm volatile ( "swapgs\n\t"
>                         "wrgsbase %0\n\t"
> diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
> index 270b93ed623e..e67a428e4362 100644
> --- a/xen/arch/x86/traps.c
> +++ b/xen/arch/x86/traps.c
> @@ -1013,6 +1013,32 @@ void show_execution_state_nmi(const cpumask_t *mask, bool show_all)
>          printk("Non-responding CPUs: {%*pbl}\n", CPUMASK_PR(&show_state_mask));
>  }
>  
> +static const char *x86_et_name(unsigned int type)
> +{
> +    static const char *const names[] = {
> +        [X86_ET_EXT_INTR]    = "EXT_INTR",
> +        [X86_ET_NMI]         = "NMI",
> +        [X86_ET_HW_EXC]      = "HW_EXC",
> +        [X86_ET_SW_INT]      = "SW_INT",
> +        [X86_ET_PRIV_SW_EXC] = "PRIV_SW_EXEC",
> +        [X86_ET_SW_EXC]      = "SW_EXEC",
> +        [X86_ET_OTHER]       = "OTHER",
> +    };
> +
> +    return (type < ARRAY_SIZE(names) && names[type]) ? names[type] : "???";
> +}
> +
> +static const char *x86_et_other_name(unsigned int vec)
> +{
> +    static const char *const names[] = {
> +        [0] = "MTF",
> +        [1] = "SYSCALL",
> +        [2] = "SYSENTER",
> +    };
> +
> +    return (vec < ARRAY_SIZE(names) && names[vec][0]) ? names[vec] : "???";
> +}
> +
>  const char *vector_name(unsigned int vec)
>  {
>      static const char names[][4] = {
> @@ -1091,9 +1117,42 @@ void fatal_trap(const struct cpu_user_regs *regs, bool show_remote)
>          }
>      }
>  
> -    panic("FATAL TRAP: vec %u, %s[%04x]%s\n",
> -          trapnr, vector_name(trapnr), regs->error_code,
> -          (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
> +    if ( read_cr4() & X86_CR4_FRED )
> +    {
> +        bool render_ec = false;
> +        const char *vec_name = NULL;
> +
> +        switch ( regs->fred_ss.type )
> +        {
> +        case X86_ET_HW_EXC:
> +        case X86_ET_SW_INT:
> +        case X86_ET_PRIV_SW_EXC:
> +        case X86_ET_SW_EXC:
> +            render_ec = true;
> +            vec_name = vector_name(regs->fred_ss.vector);
> +            break;
> +
> +        case X86_ET_OTHER:
> +            vec_name = x86_et_other_name(regs->fred_ss.vector);
> +            break;
> +        }
> +
> +        if ( render_ec )
> +            panic("Fatal TRAP: type %u, %s, vec %u, %s[%04x]%s\n",
> +                  regs->fred_ss.type, x86_et_name(regs->fred_ss.type),
> +                  regs->fred_ss.vector, vec_name ?: "",
> +                  regs->error_code,
> +                  (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
> +        else
> +            panic("Fatal TRAP: type %u, %s, vec %u, %s%s\n",
> +                  regs->fred_ss.type, x86_et_name(regs->fred_ss.type),
> +                  regs->fred_ss.vector, vec_name ?: "",
> +                  (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
> +    }
> +    else
> +        panic("FATAL TRAP: vec %u, %s[%04x]%s\n",
> +              trapnr, vector_name(trapnr), regs->error_code,
> +              (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
>  }
>  
>  void asmlinkage noreturn do_unhandled_trap(struct cpu_user_regs *regs)
> @@ -2181,6 +2240,94 @@ void asmlinkage check_ist_exit(const struct cpu_user_regs *regs, bool ist_exit)
>  }
>  #endif
>  
> +void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
> +{
> +    /* Copy fred_ss.vector into entry_vector as IDT delivery would have done. */
> +    regs->entry_vector = regs->fred_ss.vector;
> +
> +    switch ( regs->fred_ss.type )
> +    {
> +    case X86_ET_EXT_INTR:
> +        do_IRQ(regs);
> +        break;
> +
> +    case X86_ET_NMI:
> +        do_nmi(regs);
> +        break;
> +
> +    case X86_ET_HW_EXC:
> +    case X86_ET_SW_INT:
> +    case X86_ET_PRIV_SW_EXC:
> +    case X86_ET_SW_EXC:
> +        goto fatal;
> +
> +    default:
> +        goto fatal;
> +    }
> +
> +    return;
> +
> + fatal:
> +    fatal_trap(regs, false);
> +}

Noticed only now: Shouldn't this be surrounded with #ifdef CONFIG_PV (with
knock-on effects elsewhere)?

Jan


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Subject: Re: [PATCH 21/22] x86/traps: Introduce FRED entrypoints
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-22-andrew.cooper3@citrix.com>
 
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On 18/08/2025 11:03 am, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
>> index 270b93ed623e..e67a428e4362 100644
>> --- a/xen/arch/x86/traps.c
>> +++ b/xen/arch/x86/traps.c
>> @@ -2181,6 +2240,94 @@ void asmlinkage check_ist_exit(const struct cpu_user_regs *regs, bool ist_exit)
>>  }
>>  #endif
>>  
>> +void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
>> +{
>> +    /* Copy fred_ss.vector into entry_vector as IDT delivery would have done. */
>> +    regs->entry_vector = regs->fred_ss.vector;
>> +
>> +    switch ( regs->fred_ss.type )
>> +    {
>> +    case X86_ET_EXT_INTR:
>> +        do_IRQ(regs);
>> +        break;
>> +
>> +    case X86_ET_NMI:
>> +        do_nmi(regs);
>> +        break;
>> +
>> +    case X86_ET_HW_EXC:
>> +    case X86_ET_SW_INT:
>> +    case X86_ET_PRIV_SW_EXC:
>> +    case X86_ET_SW_EXC:
>> +        goto fatal;
>> +
>> +    default:
>> +        goto fatal;
>> +    }
>> +
>> +    return;
>> +
>> + fatal:
>> +    fatal_trap(regs, false);
>> +}
> Noticed only now: Shouldn't this be surrounded with #ifdef CONFIG_PV (with
> knock-on effects elsewhere)?

Randconfig had a fun time with CONFIG_PV.

I've got an early "if ( IS_ENABLED(CONFIG_PV) ) goto fatal;" but there's
a bit of extra complexity in the ASM.  entry_FRED_R3() needs to exist
even outside of CONFIG_PV, despite things like test_all_events being
conditional.

Also, this is changing a bit as part of getting PV support working.

~Andrew


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Date: Mon, 18 Aug 2025 12:15:10 +0200
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Subject: Re: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
To: Mykola Kvach 
Cc: Mykola Kvach ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 18.08.2025 10:49, Mykola Kvach wrote:
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -90,6 +90,16 @@ static void ctxt_switch_from(struct vcpu *p)
>      if ( is_idle_vcpu(p) )
>          return;
>  
> +    /* Arch timer */
> +    p->arch.cntkctl = READ_SYSREG(CNTKCTL_EL1);
> +    virt_timer_save(p);
> +
> +    /* VGIC */
> +    gic_save_state(p);
> +
> +    if ( test_bit(_VPF_suspended, &p->pause_flags) )
> +        return;

As I had to look at the Arm side uses of the new bit to at least try to
follow the comment further down, I came across this. And now I wonder:
Why would one of the pause flags need special casing here?

> @@ -1360,13 +1357,33 @@ void domain_resume(struct domain *d)
>  
>      for_each_vcpu ( d, v )
>      {
> +        /*
> +         * No need to conditionally clear _VPF_suspended here:
> +         * - This bit is only set on Arm64, and only after a successful suspend.
> +         * - domain_resume_nopause() may also be called from paths other than
> +         *   the suspend/resume flow, such as "soft-reset" actions (e.g.,
> +         *   on_poweroff), as part of the Xenstore control/shutdown protocol.
> +         *   These require guest acknowledgement to complete the operation.
> +         * So clearing the bit unconditionally is safe.
> +         */
> +        clear_bit(_VPF_suspended, &v->pause_flags);

Seeing that you set this bit for a single vCPU in a domain only, I wonder why
it needs to be a per-vCPU flag.

Apart from this, with the comment I still fear I wouldn't feel capable of
ack-ing this, as there's too much Arm-only interaction in here. It's not even
clear whether this could easily be re-used by another port.

Jan


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From: Dmytro Prokopchuk1 
To: Nicola Vetrini , Jan Beulich
	
CC: Doug Goldstein , Stefano Stabellini
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	Volodymyr Babchuk ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [RFC PATCH] misra: allow conversion from unsigned long to
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Thread-Topic: [RFC PATCH] misra: allow conversion from unsigned long to
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Thread-Index: AQHcDH/2fJv669AP80eUn9D9WGE5wrRh1CUAgADLEICABZoWgA==
Date: Mon, 18 Aug 2025 10:16:24 +0000
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In-Reply-To: <20250812150624.64898-1-roger.pau@citrix.com>
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On 12.08.2025 17:06, Roger Pau Monne wrote:
> With the appearance of Intel Sierra Forest and Granite Rapids it's now
> possible to get a production x86 host with the following memory map:
> 
> SRAT: Node 0 PXM 0 [0000000000000000, 000000007fffffff]
> SRAT: Node 0 PXM 0 [0000000100000000, 000000807fffffff]
> SRAT: Node 1 PXM 1 [0000063e80000000, 000006be7fffffff]
> SRAT: Node 2 PXM 2 [00000c7e80000000, 00000cfe7fffffff]
> SRAT: Node 3 PXM 3 [000012be80000000, 0000133e7fffffff]
> 
> This is from a four socket Granite Rapids system, with each node having
> 512GB of memory.  The total amount of RAM on the system is 2TB, but without
> enabling CONFIG_BIGMEM the last range is not accessible, as it's above the
> 16TB boundary covered by the frame table. Sierra Forest and Granite Rapids
> are socket compatible, however Sierra Forest only supports 2 socket
> configurations, while Granite Rapids can go up to 8 sockets.
> 
> Note that while the memory map is very sparse, it couldn't be compressed
> using the current PDX_MASK compression algorithm, which relies on all
> ranges having a shared zeroed region of bits that can be removed.
> 
> The memory map presented above has the property of all regions being
> similarly spaced between each other, and all having also a similar size.
> Use a lookup table to store the offsets to translate from/to PFN and PDX
> spaces.  Such table is indexed based on the input PFN or PDX to translated.
> The example PFN layout about would get compressed using the following:
> 
> PFN compression using PFN lookup table shift 29 and PDX region size 0x10000000
>  range 0 [0000000000000, 0x0000807ffff] PFN IDX  0 : 0000000000000
>  range 1 [0x00063e80000, 0x0006be7ffff] PFN IDX  3 : 0x00053e80000
>  range 2 [0x000c7e80000, 0x000cfe7ffff] PFN IDX  6 : 0x000a7e80000
>  range 3 [0x0012be80000, 0x00133e7ffff] PFN IDX  9 : 0x000fbe80000
> 
> Note how the tow ranges belonging to node 0 get merged into a single PDX
> region by the compression algorithm.
> 
> The default size of lookup tables currently set in Kconfig is 64 entries,
> and the example memory map consumes 10 entries.  Such memory map is from a
> 4 socket Granite Rapids host, which in theory supports up to 8 sockets
> according to Intel documentation.  Assuming the layout of a 8 socket system
> is similar to the 4 socket one, it would require 21 lookup table entries to
> support it, way below the current default of 64 entries.
> 
> The valid range of lookup table size is currently restricted from 1 to 512
> elements in Kconfig.
> 
> An extra array is used to keep track of the base PFN for each translated
> range.  Non used slots are set to ~0UL, so that in mfn_valid() the mfn <
> base check always fails, thus reporting the mfn as invalid.
> 
> Introduce __init_or_pdx_mask and use it on some shared functions between
> PDX mask and offset compression, as otherwise some code becomes unreachable
> after boot if PDX offset compression is used.  Mark the code as __init in
> that case, so it's pruned after boot.
> 
> Signed-off-by: Roger Pau Monné 

Reviewed-by: Jan Beulich 
with one cosmetic remark (sorry for not spotting this earlier):

> --- a/tools/tests/pdx/harness.h
> +++ b/tools/tests/pdx/harness.h
> @@ -44,8 +44,10 @@
>  
>  #define MAX_RANGES 16
>  #define MAX_PFN_RANGES MAX_RANGES
> +#define CONFIG_PDX_OFFSET_TBL_ORDER 6
>  
>  #define ASSERT assert
> +#define ASSERT_UNREACHABLE() assert(0)
>  
>  #define CONFIG_DEBUG
>  
> @@ -66,10 +68,22 @@ static inline unsigned int find_next(
>  #define find_next_zero_bit(a, s, o) find_next(a, s, o, false)
>  #define find_next_bit(a, s, o)      find_next(a, s, o, true)
>  
> +#define flsl(x) ((x) ? BITS_PER_LONG - __builtin_clzl(x) : 0)
> +#define ffsl(x) __builtin_ffsl(x)
> +
>  #define boolean_param(name, func)
>  
>  typedef uint64_t paddr_t;
>  
> +#define SWAP(a, b) \
> +   do { typeof(a) t_ = (a); (a) = (b); (b) = t_; } while ( 0 )
> +
> +#define sort(elem, nr, size, cmp, swp) ({                               \
> +    /* Consume swp() so compiler doesn't complain it's unused. */       \
> +    (void)swp;                                                          \

It generally shouldn't matter here, yet maybe still better to parenthesize swp.

Jan


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Date: Mon, 18 Aug 2025 13:03:04 +0200
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From: Oleksii Kurochko 
Subject: Re: [PATCH v3 12/20] xen/riscv: implement p2m_set_range()
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 8/15/25 2:50 PM, Jan Beulich wrote:
> On 15.08.2025 11:52, Oleksii Kurochko wrote:
>> On 8/5/25 6:04 PM, Jan Beulich wrote:
>>> On 31.07.2025 17:58, Oleksii Kurochko wrote:
>>>> +static inline void p2m_write_pte(pte_t *p, pte_t pte, bool clean_pte)
>>>> +{
>>>> +    write_pte(p, pte);
>>>> +    if ( clean_pte )
>>>> +        clean_dcache_va_range(p, sizeof(*p));
>>> Not necessarily for right away, but if multiple adjacent PTEs are
>>> written without releasing the lock, this then redundant cache flushing
>>> can be a performance issue.
>> Can't it be resolved on a caller side? Something like:
>>     p2m_write_pte(p1, pte1, false);
>>     p2m_write_pte(p2, pte2, false);
>>     p2m_write_pte(p3, pte3, false);
>>     p2m_write_pte(p4, pte4, true);
>> where p1-p4 are adjacent.
> No. You wouldn't know whether the last write flushes what the earlier
> three have written. There may be a cacheline boundary in between.

Oh, correct. It would be hard to detect, so agree that it will work
badly...

> Plus
> I didn't really think of back-to-back writes, but e.g. a loop doing
> many of them, where a single wider flush may then be more efficient.

... So IIUC you mean something like:
   for (i = 0; i < nr_entries; i++)
       p2m_write_pte(&pt[i], entries[i], false);  // no flush yet

   clean_dcache_va_range(pt, nr_entries * sizeof(pte_t));

>>>> +#define P2M_TABLE_MAP_NONE 0
>>>> +#define P2M_TABLE_MAP_NOMEM 1
>>>> +#define P2M_TABLE_SUPER_PAGE 2
>>>> +#define P2M_TABLE_NORMAL 3
>>>> +
>>>> +/*
>>>> + * Take the currently mapped table, find the corresponding the entry
>>>> + * corresponding to the GFN, and map the next table, if available.
>>> Nit: Double "corresponding".
>>>
>>>> + * The previous table will be unmapped if the next level was mapped
>>>> + * (e.g P2M_TABLE_NORMAL returned).
>>>> + *
>>>> + * `alloc_tbl` parameter indicates whether intermediate tables should
>>>> + * be allocated when not present.
>>>> + *
>>>> + * Return values:
>>>> + *  P2M_TABLE_MAP_NONE: a table allocation isn't permitted.
>>>> + *  P2M_TABLE_MAP_NOMEM: allocating a new page failed.
>>>> + *  P2M_TABLE_SUPER_PAGE: next level or leaf mapped normally.
>>>> + *  P2M_TABLE_NORMAL: The next entry points to a superpage.
>>>> + */
>>>> +static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl,
>>>> +                          unsigned int level, pte_t **table,
>>>> +                          unsigned int offset)
>>>> +{
>>>> +    panic("%s: hasn't been implemented yet\n", __func__);
>>>> +
>>>> +    return P2M_TABLE_MAP_NONE;
>>>> +}
>>>> +
>>>> +/* Free pte sub-tree behind an entry */
>>>> +static void p2m_free_subtree(struct p2m_domain *p2m,
>>>> +                             pte_t entry, unsigned int level)
>>>> +{
>>>> +    panic("%s: hasn't been implemented yet\n", __func__);
>>>> +}
>>>> +
>>>> +/*
>>>> + * Insert an entry in the p2m. This should be called with a mapping
>>>> + * equal to a page/superpage.
>>>> + */
>>>> +static int p2m_set_entry(struct p2m_domain *p2m,
>>>> +                           gfn_t gfn,
>>>> +                           unsigned long page_order,
>>>> +                           mfn_t mfn,
>>>> +                           p2m_type_t t)
>>>> +{
>>>> +    unsigned int level;
>>>> +    unsigned int target = page_order / PAGETABLE_ORDER;
>>>> +    pte_t *entry, *table, orig_pte;
>>>> +    int rc;
>>>> +    /* A mapping is removed if the MFN is invalid. */
>>>> +    bool removing_mapping = mfn_eq(mfn, INVALID_MFN);
>>> Comment and code don't fit together. Many MFNs are invalid (any for which
>>> mfn_valid() returns false), yet you only check for INVALID_MFN here.
>> Probably, it makes sense to add an|ASSERT()| here for the case when
>> |mfn_valid(mfn)| is false, but the MFN is not explicitly equal to|INVALID_MFN|.
>> This would indicate that someone attempted to perform a mapping with an
>> incorrect MFN, which, IMO, is entirely wrong.
> No, and we've been there before. MMIO can live anywhere, and mappings for
> such still will need to be permitted. It is correct to check only for
> INVALID_MFN here imo; it's just the comment which also needs to reflect
> that.

Got it now. The original one comment looked clear to me, but considering what
you wrote, I will update the comment then to:
   A mapping is removed only if the MFN is explicitly passed as INVALID_MFN.
Also, perhaps, it makes sense to add the following:
   Other MFNs that are not valid (e.g., MMIO) from mfn_valid() point of
   view are allowed.

Does it make more sense now?

>
>>>> +    /*
>>>> +     * If we are here with level > target, we must be at a leaf node,
>>>> +     * and we need to break up the superpage.
>>>> +     */
>>>> +    if ( level > target )
>>>> +    {
>>>> +        panic("Shattering isn't implemented\n");
>>>> +    }
>>>> +
>>>> +    /*
>>>> +     * We should always be there with the correct level because all the
>>>> +     * intermediate tables have been installed if necessary.
>>>> +     */
>>>> +    ASSERT(level == target);
>>>> +
>>>> +    orig_pte = *entry;
>>>> +
>>>> +    if ( removing_mapping )
>>>> +        p2m_clean_pte(entry, p2m->clean_pte);
>>>> +    else
>>>> +    {
>>>> +        pte_t pte = p2m_pte_from_mfn(mfn, t);
>>>> +
>>>> +        p2m_write_pte(entry, pte, p2m->clean_pte);
>>>> +
>>>> +        p2m->max_mapped_gfn = gfn_max(p2m->max_mapped_gfn,
>>>> +                                      gfn_add(gfn, BIT(page_order, UL) - 1));
>>>> +        p2m->lowest_mapped_gfn = gfn_min(p2m->lowest_mapped_gfn, gfn);
>>>> +    }
>>>> +
>>>> +    p2m->need_flush = true;
>>>> +
>>>> +    /*
>>>> +     * Currently, the infrastructure required to enable CONFIG_HAS_PASSTHROUGH
>>>> +     * is not ready for RISC-V support.
>>>> +     *
>>>> +     * When CONFIG_HAS_PASSTHROUGH=y, iommu_iotlb_flush() should be done
>>>> +     * here.
>>>> +     */
>>>> +#ifdef CONFIG_HAS_PASSTHROUGH
>>>> +#   error "add code to flush IOMMU TLB"
>>>> +#endif
>>>> +
>>>> +    rc = 0;
>>>> +
>>>> +    /*
>>>> +     * Free the entry only if the original pte was valid and the base
>>>> +     * is different (to avoid freeing when permission is changed).
>>>> +     */
>>>> +    if ( pte_is_valid(orig_pte) &&
>>>> +         !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) )
>>> I'm puzzled by this 2nd check: A permission change would - I expect - only
>>> occur to a leaf entry. If the new entry is a super-page one and the old
>>> wasn't, don't you still need to free the sub-tree, no matter whether the
>>> MFNs are the same?
>> I expect the MFNs to differ in this scenario, so the old sub-tree will be freed.
> You expecting something isn't a good criteria. If it's possible, even if
> unexpected (by you), it needs dealing with correctly.
>
>> Based on your example (new entry is super-page and old entry isn't):
>> For old mapping (lets say, 4 KiB leaf) p2m_set_entry() walks all levels down
>> to L0, so we will have the following MMU page table walks:
>>     L2 PTE -> L1 PTE (MFN of L0 page table) -> L0 PTE -> RAM
>>
>> When new mapping (lets say, 2 MiB superpage) will be requested, p2m_set_entry()
>> will stop at L1 (the superpage level):
>>    L2 PTE -> L1 PTE (at this moment, L1 PTE points to L0 page table, which
>>                      points to RAM)
>> Then the old L1 PTE will be saved in 'orig_pte', then writes 'entry' with
>> the RAM MFN for the 2 MiB mapping. The walk becomes:
>>     L2 PTE -> L1 PTE -> RAM
>>
>> Therefore, 'entry' now holds an MFN pointing to RAM (superpage leaf). 'orig_pte'
>> still holds an MFN pointing to the L0 table (the old sub-tree). Since these MFNs
>> differ, the code calls p2m_free_subtree(p2m, orig_pte, …) and frees the old L0
>> sub-tree.
> A particular example doesn't help. All possible cases need handling correctly.

For sure, all possible cases need handling correctly, but I don't see any cases
except one you mentioned below where MFNs will be the same.

>
>>>    Plus consider the special case of MFN 0: If you clear
>>> an entry using MFN 0, you will find old and new PTEs' both having the same
>>> MFN.
>> Isn't this happen only when a mapping removal is explicitly requested?
>> In the case of a mapping removal it seems to me it is enough just to
>> clear PTE with all zeroes.
> Correct. Which means original MFN (PPN) and new MFN (PPN) would match.

Oh, I got it what is the issue here. If previously MFN 0 was mapped, then
it is going to be removed and considering that during removing MFN 0 is
used, we won't put MFN 0 page reference (mapped earlier) because
p2m_free_subtree() won't be called.

In this case, if-condidtion should be updated with:
   @@ -883,7 +890,8 @@ static int p2m_set_entry(struct p2m_domain *p2m,
         * is different (to avoid freeing when permission is changed).
         */
        if ( pte_is_valid(orig_pte) &&
   -         !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) )
   +         (!mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) ||
   +          (removing_mapping && mfn_eq(pte_get_mfn(*entry), mfn_t(0))) )

or call p2m_free_subentry() in remove_mapping handling:
   @@ -850,7 +852,12 @@ static int p2m_set_entry(struct p2m_domain *p2m,
        orig_pte = *entry;
  
        if ( removing_mapping )
   +    {
   +       if ( mfn_eq(pte_get_mfn(*entry), mfn_t(0) )
   +            p2m_free_subtree(p2m, orig_pte, level,  virt_to_page(table), offsets[level]);
   +
          p2m_clean_pte(entry, p2m->clean_pte);
   +    }
        else

~ Oleksii

--------------JjfAIznUMdWgBed42B00sOpd
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 8bit



  
    
  
  
    

    
    
    
    
    On 8/15/25 2:50 PM, Jan Beulich wrote:
    
    
    
    
    
      
    On 15.08.2025 11:52, Oleksii Kurochko wrote:

    
      
    
        
    On 8/5/25 6:04 PM, Jan Beulich wrote:

    
        
    
          
    On 31.07.2025 17:58, Oleksii Kurochko wrote:

    
        
    
      
    
      
    
        
    
          
    
            
    +static inline void p2m_write_pte(pte_t *p, pte_t pte, bool clean_pte)
+{
+    write_pte(p, pte);
+    if ( clean_pte )
+        clean_dcache_va_range(p, sizeof(*p));

    
          
    
          
    Not necessarily for right away, but if multiple adjacent PTEs are
written without releasing the lock, this then redundant cache flushing
can be a performance issue.

    
        
    
        
    Can't it be resolved on a caller side? Something like:
   p2m_write_pte(p1, pte1, false);
   p2m_write_pte(p2, pte2, false);
   p2m_write_pte(p3, pte3, false);
   p2m_write_pte(p4, pte4, true);
where p1-p4 are adjacent.

    
      
    
      
    No. You wouldn't know whether the last write flushes what the earlier
three have written. There may be a cacheline boundary in between. 
    
    
    
    
    Oh, correct. It would be hard to detect, so agree that it will work
badly...

    
    
    
      
    Plus
I didn't really think of back-to-back writes, but e.g. a loop doing
many of them, where a single wider flush may then be more efficient.
    
    
    
    
    ... So IIUC you mean something like:
  for (i = 0; i < nr_entries; i++)
      p2m_write_pte(&pt[i], entries[i], false);  // no flush yet

  clean_dcache_va_range(pt, nr_entries * sizeof(pte_t));


    
    
    
      
    
        
    
          
    
            
    +#define P2M_TABLE_MAP_NONE 0
+#define P2M_TABLE_MAP_NOMEM 1
+#define P2M_TABLE_SUPER_PAGE 2
+#define P2M_TABLE_NORMAL 3
+
+/*
+ * Take the currently mapped table, find the corresponding the entry
+ * corresponding to the GFN, and map the next table, if available.

    
          
    
          
    Nit: Double "corresponding".


    
          
    
            
    + * The previous table will be unmapped if the next level was mapped
+ * (e.g P2M_TABLE_NORMAL returned).
+ *
+ * `alloc_tbl` parameter indicates whether intermediate tables should
+ * be allocated when not present.
+ *
+ * Return values:
+ *  P2M_TABLE_MAP_NONE: a table allocation isn't permitted.
+ *  P2M_TABLE_MAP_NOMEM: allocating a new page failed.
+ *  P2M_TABLE_SUPER_PAGE: next level or leaf mapped normally.
+ *  P2M_TABLE_NORMAL: The next entry points to a superpage.
+ */
+static int p2m_next_level(struct p2m_domain *p2m, bool alloc_tbl,
+                          unsigned int level, pte_t **table,
+                          unsigned int offset)
+{
+    panic("%s: hasn't been implemented yet\n", __func__);
+
+    return P2M_TABLE_MAP_NONE;
+}
+
+/* Free pte sub-tree behind an entry */
+static void p2m_free_subtree(struct p2m_domain *p2m,
+                             pte_t entry, unsigned int level)
+{
+    panic("%s: hasn't been implemented yet\n", __func__);
+}
+
+/*
+ * Insert an entry in the p2m. This should be called with a mapping
+ * equal to a page/superpage.
+ */
+static int p2m_set_entry(struct p2m_domain *p2m,
+                           gfn_t gfn,
+                           unsigned long page_order,
+                           mfn_t mfn,
+                           p2m_type_t t)
+{
+    unsigned int level;
+    unsigned int target = page_order / PAGETABLE_ORDER;
+    pte_t *entry, *table, orig_pte;
+    int rc;
+    /* A mapping is removed if the MFN is invalid. */
+    bool removing_mapping = mfn_eq(mfn, INVALID_MFN);

    
          
    
          
    Comment and code don't fit together. Many MFNs are invalid (any for which
mfn_valid() returns false), yet you only check for INVALID_MFN here.

    
        
    
        
    Probably, it makes sense to add an|ASSERT()| here for the case when
|mfn_valid(mfn)| is false, but the MFN is not explicitly equal to|INVALID_MFN|.
This would indicate that someone attempted to perform a mapping with an
incorrect MFN, which, IMO, is entirely wrong.

    
      
    
      
    No, and we've been there before. MMIO can live anywhere, and mappings for
such still will need to be permitted. It is correct to check only for
INVALID_MFN here imo; it's just the comment which also needs to reflect
that.
    
    
    
    
    Got it now. The original one comment looked clear to me, but considering what
you wrote, I will update the comment then to:
  A mapping is removed only if the MFN is explicitly passed as INVALID_MFN.
Also, perhaps, it makes sense to add the following:
  Other MFNs that are not valid (e.g., MMIO) from mfn_valid() point of
  view are allowed.

Does it make more sense now?


    
    
    
      
    

    
      
    
        
    
          
    
            
    +    /*
+     * If we are here with level > target, we must be at a leaf node,
+     * and we need to break up the superpage.
+     */
+    if ( level > target )
+    {
+        panic("Shattering isn't implemented\n");
+    }
+
+    /*
+     * We should always be there with the correct level because all the
+     * intermediate tables have been installed if necessary.
+     */
+    ASSERT(level == target);
+
+    orig_pte = *entry;
+
+    if ( removing_mapping )
+        p2m_clean_pte(entry, p2m->clean_pte);
+    else
+    {
+        pte_t pte = p2m_pte_from_mfn(mfn, t);
+
+        p2m_write_pte(entry, pte, p2m->clean_pte);
+
+        p2m->max_mapped_gfn = gfn_max(p2m->max_mapped_gfn,
+                                      gfn_add(gfn, BIT(page_order, UL) - 1));
+        p2m->lowest_mapped_gfn = gfn_min(p2m->lowest_mapped_gfn, gfn);
+    }
+
+    p2m->need_flush = true;
+
+    /*
+     * Currently, the infrastructure required to enable CONFIG_HAS_PASSTHROUGH
+     * is not ready for RISC-V support.
+     *
+     * When CONFIG_HAS_PASSTHROUGH=y, iommu_iotlb_flush() should be done
+     * here.
+     */
+#ifdef CONFIG_HAS_PASSTHROUGH
+#   error "add code to flush IOMMU TLB"
+#endif
+
+    rc = 0;
+
+    /*
+     * Free the entry only if the original pte was valid and the base
+     * is different (to avoid freeing when permission is changed).
+     */
+    if ( pte_is_valid(orig_pte) &&
+         !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) )

    
          
    
          
    I'm puzzled by this 2nd check: A permission change would - I expect - only
occur to a leaf entry. If the new entry is a super-page one and the old
wasn't, don't you still need to free the sub-tree, no matter whether the
MFNs are the same?

    
        
    
        
    I expect the MFNs to differ in this scenario, so the old sub-tree will be freed.

    
      
    
      
    You expecting something isn't a good criteria. If it's possible, even if
unexpected (by you), it needs dealing with correctly.


    
      
    
        
    Based on your example (new entry is super-page and old entry isn't):
For old mapping (lets say, 4 KiB leaf) p2m_set_entry() walks all levels down
to L0, so we will have the following MMU page table walks:
   L2 PTE -> L1 PTE (MFN of L0 page table) -> L0 PTE -> RAM

When new mapping (lets say, 2 MiB superpage) will be requested, p2m_set_entry()
will stop at L1 (the superpage level):
  L2 PTE -> L1 PTE (at this moment, L1 PTE points to L0 page table, which
                    points to RAM)
Then the old L1 PTE will be saved in 'orig_pte', then writes 'entry' with
the RAM MFN for the 2 MiB mapping. The walk becomes:
   L2 PTE -> L1 PTE -> RAM

Therefore, 'entry' now holds an MFN pointing to RAM (superpage leaf). 'orig_pte'
still holds an MFN pointing to the L0 table (the old sub-tree). Since these MFNs
differ, the code calls p2m_free_subtree(p2m, orig_pte, …) and frees the old L0
sub-tree.

    
      
    
      
    A particular example doesn't help. All possible cases need handling correctly.
    
    
    
    
    For sure, all possible cases need handling correctly, but I don't see any cases
except one you mentioned below where MFNs will be the same.


    
    
    
      
    

    
      
    
        
    
          
      Plus consider the special case of MFN 0: If you clear
an entry using MFN 0, you will find old and new PTEs' both having the same
MFN.

    
        
    
        
    Isn't this happen only when a mapping removal is explicitly requested?
In the case of a mapping removal it seems to me it is enough just to
clear PTE with all zeroes.

    
      
    
      
    Correct. Which means original MFN (PPN) and new MFN (PPN) would match.
    
    
    
    
    Oh, I got it what is the issue here. If previously MFN 0 was mapped, then
it is going to be removed and considering that during removing MFN 0 is
used, we won't put MFN 0 page reference (mapped earlier) because
p2m_free_subtree() won't be called.

In this case, if-condidtion should be updated with:
  @@ -883,7 +890,8 @@ static int p2m_set_entry(struct p2m_domain *p2m,
        * is different (to avoid freeing when permission is changed).
        */
       if ( pte_is_valid(orig_pte) &&
  -         !mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) )
  +         (!mfn_eq(pte_get_mfn(*entry), pte_get_mfn(orig_pte)) ||
  +          (removing_mapping && mfn_eq(pte_get_mfn(*entry), mfn_t(0))) )

or call p2m_free_subentry() in remove_mapping handling:
  @@ -850,7 +852,12 @@ static int p2m_set_entry(struct p2m_domain *p2m,
       orig_pte = *entry;
 
       if ( removing_mapping )
  +    {
  +       if ( mfn_eq(pte_get_mfn(*entry), mfn_t(0) )
  +            p2m_free_subtree(p2m, orig_pte, level,  virt_to_page(table), offsets[level]);
  +
         p2m_clean_pte(entry, p2m->clean_pte);
  +    }
       else

    
    
    ~ Oleksii

    
  


--------------JjfAIznUMdWgBed42B00sOpd--


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15.08.25 15:20, Jan Beulich:
> On 15.08.2025 12:23, Sergiy Kibrik wrote:
>> --- a/docs/misc/xen-command-line.pandoc
>> +++ b/docs/misc/xen-command-line.pandoc
>> @@ -238,6 +238,15 @@ loops for Queued Invalidation completions.**
>>   Specify a maximum amount of available memory, to which Xen will clamp
>>   the e820 table.
>>   
>> +### avc_prealloc
> 
> In addition to what Andrew said, please prefer dashes over underscores in new
> options.
> 
>> @@ -97,6 +99,9 @@ static struct avc_cache avc_cache;
>>   
>>   static DEFINE_RCU_READ_LOCK(avc_rcu_lock);
>>   
>> +bool __read_mostly opt_avc_prealloc = false;
> 
> __ro_after_init?
> 

sure, will do that. Thank you!

   -Sergiy


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Date: Mon, 18 Aug 2025 14:05:30 +0300
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Subject: Re: [RFC PATCH] xsm/flask: add AVC pre-allocation boot parameter
To: Andrew Cooper , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 "Daniel P. Smith" ,
 Stefano Stabellini 
References: <20250815102330.778749-1-Sergiy_Kibrik@epam.com>
 <37206bd7-b455-499a-9632-f435ab87888e@citrix.com>
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15.08.25 14:43, Andrew Cooper:
> On 15/08/2025 12:21 pm, Andrew Cooper wrote:
>> On 15/08/2025 11:23 am, Sergiy Kibrik wrote:
>>> diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
>>> index a75b6c9301..9044827e78 100644
>>> --- a/docs/misc/xen-command-line.pandoc
>>> +++ b/docs/misc/xen-command-line.pandoc
>>> @@ -238,6 +238,15 @@ loops for Queued Invalidation completions.**
>>>   Specify a maximum amount of available memory, to which Xen will clamp
>>>   the e820 table.
>>>   
>>> +### avc_prealloc
>>> +> `= `
>>> +
>>> +> Default: `false`
>>> +
>>> +Allocate XSM Access Vector Cache at boot. This forbids runtime dynamic
>>> +allocation of AVC nodes from Xen heap and changing AVC size via
>>> +FLASK_SETAVC_THRESHOLD hypercall.
>> I don't have any input on memory allocation side of things, but this
>> needs to be a sub-option under the existing flask=, and it looks like
>> you're going to need to turn it into a comma separated list.
>>
>> Also, if you actually want to use Flask in a safety system, Flask needs
>> to become security supported in Xen.
> 
> Sorry, sent a little too early.  x86's dom0= is probably the closes good
> example to follow, having both comma separated booleans and a choice-of-$N.
> 

yes, I'll try to integrate that option into flask=

  -Sergiy


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Subject: Re: [PATCH v2 01/16] x86/msr: Implement rdmsr_safe() in C
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 15.08.2025 22:41, Andrew Cooper wrote:
> ... in preparation to be able to use asm goto.
> 
> Notably this mean that the value parameter must be taken by pointer rather
> than by value.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

In principle
Reviewed-by: Jan Beulich 
However, having looked at patch 2 first, ...

> @@ -879,14 +879,14 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
>      case 0x8f: /* Sapphire Rapids X */
>  
>          if ( (c != &boot_cpu_data && !ppin_msr) ||
> -             rdmsr_safe(MSR_PPIN_CTL, val) )
> +             rdmsr_safe(MSR_PPIN_CTL, &val) )
>              return;

... with this, wouldn't we be better off using ...

>          /* If PPIN is disabled, but not locked, try to enable. */
>          if ( !(val & (PPIN_ENABLE | PPIN_LOCKOUT)) )
>          {
>              wrmsr_safe(MSR_PPIN_CTL, val | PPIN_ENABLE);
> -            rdmsr_safe(MSR_PPIN_CTL, val);
> +            rdmsr_safe(MSR_PPIN_CTL, &val);

... plain rdmsr() here, thus not leaving it open to the behavioral change
patch 2 comes with?

Jan


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Subject: Re: [PATCH v2 02/16] x86/msr: Rework rdmsr_safe() using asm goto()
To: Andrew Cooper 
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On 15.08.2025 22:41, Andrew Cooper wrote:
> ... on capable toolchains.
> 
> This avoids needing to hold rc in a register across the RDMSR, and in most
> cases removes direct testing and branching based on rc, as the fault label can
> be rearranged to directly land on the out-of-line block.
> 
> There is a subtle difference in behaviour.  The old behaviour would, on fault,
> still produce 0's and write to val.
> 
> The new behaviour only writes val on success, and write_msr() is the only
> place where this matters.  Move temp out of switch() scope and initialise it
> to 0.

But what's the motivation behind making this behavioral change? At least in
the cases where the return value isn't checked, it would feel safer if we
continued clearing the value. Even if in all cases where this could matter
(besides the one you cover here) one can prove correctness by looking at
surrounding code.

> --- a/xen/arch/x86/include/asm/msr.h
> +++ b/xen/arch/x86/include/asm/msr.h
> @@ -55,6 +55,24 @@ static inline void wrmsrns(uint32_t msr, uint64_t val)
>  /* rdmsr with exception handling */
>  static inline int rdmsr_safe(unsigned int msr, uint64_t *val)
>  {
> +#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
> +    uint64_t lo, hi;

Could at least this line move ahead of the #ifdef, to also cover ...

> +    asm_inline goto (
> +        "1: rdmsr\n\t"
> +        _ASM_EXTABLE(1b, %l[fault])
> +        : "=a" (lo), "=d" (hi)
> +        : "c" (msr)
> +        :
> +        : fault );
> +
> +    *val = lo | (hi << 32);
> +
> +    return 0;
> +
> + fault:
> +    return -EFAULT;
> +#else
>      int rc;
>      uint64_t lo, hi;

... the same being needed here?

Jan


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On 15.08.2025 22:41, Andrew Cooper wrote:
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 



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Date: Mon, 18 Aug 2025 12:34:19 +0100
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Subject: Re: [PATCH v2 11/16] x86/msr: Change rdmsr() to have normal API
To: Xen-devel 
Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
 <20250815204117.3312742-12-andrew.cooper3@citrix.com>
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From: Andrew Cooper 
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On 15/08/2025 9:41 pm, Andrew Cooper wrote:
> diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
> index 530b9eb39abc..9c6b8c291d6e 100644
> --- a/xen/arch/x86/cpu/common.c
> +++ b/xen/arch/x86/cpu/common.c
> @@ -329,6 +329,7 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
>  void __init early_cpu_init(bool verbose)
>  {
>  	struct cpuinfo_x86 *c = &boot_cpu_data;
> +	uint64_t val;
>  	u32 eax, ebx, ecx, edx;
>  
>  	c->x86_cache_alignment = 32;
> @@ -412,10 +413,11 @@ void __init early_cpu_init(bool verbose)
>  			    &c->x86_capability[FEATURESET_7c0],
>  			    &c->x86_capability[FEATURESET_7d0]);
>  
> -		if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability))
> -			rdmsr(MSR_ARCH_CAPABILITIES,
> -			      c->x86_capability[FEATURESET_m10Al],
> -			      c->x86_capability[FEATURESET_m10Ah]);
> +		if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) {
> +			val = rdmsr(MSR_ARCH_CAPABILITIES);
> +			c->x86_capability[FEATURESET_m10Al] = val;
> +			c->x86_capability[FEATURESET_m10Al] = val >> 32;

This is a typo.  Fixed locally.

~Andrew


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In-Reply-To: <5bf9b184-70fb-4698-a01e-e8cbcb05935f@suse.com>
From: Mykola Kvach 
Date: Mon, 18 Aug 2025 15:43:31 +0300
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Message-ID: 
Subject: Re: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Jan Beulich 
Cc: Mykola Kvach , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Andrew Cooper , Anthony PERARD , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	xen-devel@lists.xenproject.org
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Hi Jan,

On Mon, Aug 18, 2025 at 1:15=E2=80=AFPM Jan Beulich  wro=
te:
>
> On 18.08.2025 10:49, Mykola Kvach wrote:
> > --- a/xen/arch/arm/domain.c
> > +++ b/xen/arch/arm/domain.c
> > @@ -90,6 +90,16 @@ static void ctxt_switch_from(struct vcpu *p)
> >      if ( is_idle_vcpu(p) )
> >          return;
> >
> > +    /* Arch timer */
> > +    p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1);
> > +    virt_timer_save(p);
> > +
> > +    /* VGIC */
> > +    gic_save_state(p);
> > +
> > +    if ( test_bit(_VPF_suspended, &p->pause_flags) )
> > +        return;
>
> As I had to look at the Arm side uses of the new bit to at least try to
> follow the comment further down, I came across this. And now I wonder:
> Why would one of the pause flags need special casing here?

Some kind of answer was given in a previous version of this patch series,
see:
https://patchew.org/Xen/cover.1751020456.git.mykola._5Fkvach@epam.com/07227=
0e0940b6bcc2743d56a336363f4719ba60a.1751020456.git.mykola._5Fkvach@epam.com=
/#066c6e93-a478-4c8f-b161-d109bd0e6bb4@xen.org

To clarify:

We need to avoid updating the vCPU context when switching from a vCPU of a
domain that is being suspended to a vCPU of another domain. After the curre=
nt
HVC trap, which handles the PSCI SYSTEM_SUSPEND call, completes, the schedu=
ler
will switch to a vCPU from another domain. At this point, the virtual CPU i=
s
marked as paused either via pause_count (domain_shutdown -> vcpu_pause_nosy=
nc)
or by having the _VPF_suspended bit set in pause_flags. In both cases,
vcpu_runnable() will return false, so control will not be returned to the g=
uest
OS from this trap, and the scheduler will switch to another domain's vCPU.

During this context switch, we must not update the saved context of certain
vCPU registers for the domain that has entered suspend. The vCPU context fo=
r
suspend is set up in do_setup_vcpu_ctx(). If another function were to overw=
rite
the saved values with the current ones in a physical CPU at this point, the
domain would not be able to resume correctly after a resume command.


As an alternative, all suspend-related actions could be performed in a task=
let,
which would avoid the need for modifications in domain_pause and the
introduction of the new flag. The tasklet would execute after the context
switch, but this approach would increase code complexity and introduce
synchronization issues, such as passing the suspend command context to the
tasklet, adding extra locks, or creating a dedicated tasklet for each domai=
n.
Locking would also need to be reworked to handle cases where another domain
might attempt to change the vCPU context concurrently and just domain_pause
won't be enough.

Since the trap is a synchronous call, the current approach greatly simplifi=
es
synchronization compared to the tasklet-based alternative.

>
> > @@ -1360,13 +1357,33 @@ void domain_resume(struct domain *d)
> >
> >      for_each_vcpu ( d, v )
> >      {
> > +        /*
> > +         * No need to conditionally clear _VPF_suspended here:
> > +         * - This bit is only set on Arm64, and only after a successfu=
l suspend.

Note to self: s/Arm64/Arm/g

> > +         * - domain_resume_nopause() may also be called from paths oth=
er than
> > +         *   the suspend/resume flow, such as "soft-reset" actions (e.=
g.,
> > +         *   on_poweroff), as part of the Xenstore control/shutdown pr=
otocol.
> > +         *   These require guest acknowledgement to complete the opera=
tion.
> > +         * So clearing the bit unconditionally is safe.
> > +         */
> > +        clear_bit(_VPF_suspended, &v->pause_flags);
>
> Seeing that you set this bit for a single vCPU in a domain only, I wonder=
 why
> it needs to be a per-vCPU flag.

That's a good question. In earlier versions of this patch series, both I an=
d
some other contributors used existed fields from the domain structure, such=
 as
shutdown_code and is_shutting_down, for this purpose. However, I recall tha=
t
in a previous review, this approach was not well received. See:
https://lore.kernel.org/all/d24be446-af5a-7881-2db4-b25afac3e1f4@citrix.com=
/

Technically, there is nothing preventing me from storing this information i=
n
the domain structure. However, I do not see much benefit in introducing a n=
ew
field to the domain struct when there is already an existing per-vCPU flags
field that tracks powerdown and pause states. Using one more bit in the
pause_flags field seems sufficient and avoids further bloating the domain
structure.

>
> Apart from this, with the comment I still fear I wouldn't feel capable of
> ack-ing this, as there's too much Arm-only interaction in here. It's not =
even
> clear whether this could easily be re-used by another port.

Thank you for your feedback.

I understand your concern regarding the Arm-specific nature of this code an=
d
the potential challenges for reusing it on other architectures. The current
implementation is focused on supporting PSCI SYSTEM_SUSPEND, which is an
Arm-specific interface, so much of the logic is naturally tied to Arm.

That said, I have tried to keep the changes as contained as possible, and
where feasible, I have avoided making unnecessary modifications to common c=
ode.
If there is interest or a use case for supporting similar suspend/resume fl=
ows
on other architectures, I am open to suggestions on how to further abstract=
 or
generalize the implementation.

If you have specific recommendations for making this code more portable or
easier to adapt for other ports, I would be happy to discuss and consider
them.

>
> Jan

Best regards,
Mykola


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To: Jan Beulich 
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Subject: Re: [PATCH] efi: remove unreachable code in read_file()
Thread-Topic: [PATCH] efi: remove unreachable code in read_file()
Thread-Index: AQHcC72+MqlVxdSA/E6jjiAcMI3Nd7Rh0dCAgAaSrYA=
Date: Mon, 18 Aug 2025 12:45:34 +0000
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On 18.08.2025 14:43, Mykola Kvach wrote:
> On Mon, Aug 18, 2025 at 1:15 PM Jan Beulich  wrote:
>> On 18.08.2025 10:49, Mykola Kvach wrote:
>>> @@ -1360,13 +1357,33 @@ void domain_resume(struct domain *d)
>>>
>>>      for_each_vcpu ( d, v )
>>>      {
>>> +        /*
>>> +         * No need to conditionally clear _VPF_suspended here:
>>> +         * - This bit is only set on Arm64, and only after a successful suspend.
> 
> Note to self: s/Arm64/Arm/g
> 
>>> +         * - domain_resume_nopause() may also be called from paths other than
>>> +         *   the suspend/resume flow, such as "soft-reset" actions (e.g.,
>>> +         *   on_poweroff), as part of the Xenstore control/shutdown protocol.
>>> +         *   These require guest acknowledgement to complete the operation.
>>> +         * So clearing the bit unconditionally is safe.
>>> +         */
>>> +        clear_bit(_VPF_suspended, &v->pause_flags);
>>
>> Seeing that you set this bit for a single vCPU in a domain only, I wonder why
>> it needs to be a per-vCPU flag.
> 
> That's a good question. In earlier versions of this patch series, both I and
> some other contributors used existed fields from the domain structure, such as
> shutdown_code and is_shutting_down, for this purpose. However, I recall that
> in a previous review, this approach was not well received. See:
> https://lore.kernel.org/all/d24be446-af5a-7881-2db4-b25afac3e1f4@citrix.com/
> 
> Technically, there is nothing preventing me from storing this information in
> the domain structure. However, I do not see much benefit in introducing a new
> field to the domain struct when there is already an existing per-vCPU flags
> field that tracks powerdown and pause states. Using one more bit in the
> pause_flags field seems sufficient and avoids further bloating the domain
> structure.

Hmm, yes, I was mis-remembering something here: I thought that much like we
have pause_count both for vCPU-s and for domains, we'd also have pause_flags
for both. Perhaps indeed okay as is then, as far as where to put the flag
goes.

Jan


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On 15.08.2025 22:41, Andrew Cooper wrote:
> struct vcpu_msrs has a very different purpose to everything else in msr.h
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 



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On 15.08.2025 22:41, Andrew Cooper wrote:
> It is a large and complex API, but only a handful of translation units need
> access.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 



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Subject: Re: [PATCH v2 06/16] x86/msr: Split out tsc.h
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On 15.08.2025 22:41, Andrew Cooper wrote:
> The TSC functionality is only related to MSRs by write_tsc(), and this really
> does not want to be available as widely as is currently is.
> 
> asm/time.h shouldn't be including asm/msr.h, but this turns out to be
> sufficiently tangled that I've chosen to break it out into it's own patch.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 
with one nit:

> --- /dev/null
> +++ b/xen/arch/x86/include/asm/tsc.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#ifndef X86_TSC_H
> +#define X86_TSC_H
> +
> +#include 
> +
> +static inline uint64_t rdtsc(void)
> +{
> +    uint64_t low, high;
> +
> +    asm volatile ( "rdtsc" : "=a" (low), "=d" (high) );
> +
> +    return (high << 32) | low;
> +}
> +
> +static inline uint64_t rdtsc_ordered(void)
> +{
> +    uint64_t low, high, aux;
> +
> +    /*
> +     * The RDTSC instruction is not serializing.  Make it dispatch serializing
> +     * for the purposes here by issuing LFENCE (or MFENCE if necessary) ahead
> +     * of it.
> +     *
> +     * RDTSCP, otoh, "does wait until all previous instructions have executed
> +     * and all previous loads are globally visible" (SDM) / "forces all older
> +     * instructions to retire before reading the timestamp counter" (APM).
> +     */
> +    alternative_io_2("lfence; rdtsc",
> +                     "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
> +                     "rdtscp",        X86_FEATURE_RDTSCP,
> +                     ASM_OUTPUT2("=a" (low), "=d" (high), "=c" (aux)),
> +                     /* no inputs */);
> +
> +    return (high << 32) | low;
> +}
> +
> +#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
> +#define write_tsc(val) ({                                       \
> +    /* Reliable TSCs are in lockstep across all CPUs. We should \
> +     * never write to them. */                                  \

This comment may want to become a proper Xen-style one while being moved.

Jan


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In-Reply-To: 
From: Frediano Ziglio 
Date: Mon, 18 Aug 2025 14:25:03 +0100
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Subject: Re: [PATCH v2 06/16] x86/msr: Split out tsc.h
To: Jan Beulich 
Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Xen-devel 
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On Mon, Aug 18, 2025 at 2:07=E2=80=AFPM Jan Beulich  wro=
te:
>
> On 15.08.2025 22:41, Andrew Cooper wrote:
> > The TSC functionality is only related to MSRs by write_tsc(), and this =
really
> > does not want to be available as widely as is currently is.
> >
> > asm/time.h shouldn't be including asm/msr.h, but this turns out to be
> > sufficiently tangled that I've chosen to break it out into it's own pat=
ch.
> >
> > No functional change.
> >
> > Signed-off-by: Andrew Cooper 
>
> Acked-by: Jan Beulich 
> with one nit:
>
> > --- /dev/null
> > +++ b/xen/arch/x86/include/asm/tsc.h
> > @@ -0,0 +1,46 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +#ifndef X86_TSC_H
> > +#define X86_TSC_H
> > +
> > +#include 
> > +
> > +static inline uint64_t rdtsc(void)
> > +{
> > +    uint64_t low, high;
> > +
> > +    asm volatile ( "rdtsc" : "=3Da" (low), "=3Dd" (high) );
> > +
> > +    return (high << 32) | low;
> > +}
> > +
> > +static inline uint64_t rdtsc_ordered(void)
> > +{
> > +    uint64_t low, high, aux;
> > +
> > +    /*
> > +     * The RDTSC instruction is not serializing.  Make it dispatch ser=
ializing
> > +     * for the purposes here by issuing LFENCE (or MFENCE if necessary=
) ahead
> > +     * of it.
> > +     *
> > +     * RDTSCP, otoh, "does wait until all previous instructions have e=
xecuted
> > +     * and all previous loads are globally visible" (SDM) / "forces al=
l older
> > +     * instructions to retire before reading the timestamp counter" (A=
PM).
> > +     */
> > +    alternative_io_2("lfence; rdtsc",
> > +                     "mfence; rdtsc", X86_FEATURE_MFENCE_RDTSC,
> > +                     "rdtscp",        X86_FEATURE_RDTSCP,
> > +                     ASM_OUTPUT2("=3Da" (low), "=3Dd" (high), "=3Dc" (=
aux)),
> > +                     /* no inputs */);
> > +
> > +    return (high << 32) | low;
> > +}
> > +
> > +#define __write_tsc(val) wrmsrl(MSR_IA32_TSC, val)
> > +#define write_tsc(val) ({                                       \
> > +    /* Reliable TSCs are in lockstep across all CPUs. We should \
> > +     * never write to them. */                                  \
>
> This comment may want to become a proper Xen-style one while being moved.
>
> Jan
>

Does it make sense to move the comment out of the macro?

Frediano


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Date: Mon, 18 Aug 2025 15:28:59 +0200
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Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
To: Jan Beulich , Penny Zheng 
Cc: ray.huang@amd.com, Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: <20250815102728.1340505-1-Penny.Zheng@amd.com>
 
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From: Oleksii Kurochko 
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On 8/18/25 10:31 AM, Jan Beulich wrote:
> On 15.08.2025 12:27, Penny Zheng wrote:
>> In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and
>> HVM=y results in hvm.c being built, but domctl.c not being built, which leaves
>> a few functions, like domctl_lock_acquire/release() undefined, causing linking
>> to fail.
>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile
>> /hypercall-defs section, with this adjustment, we also need to release
>> redundant vnuma_destroy() stub definition from PV_SHIM_EXCLUSIVE guardian,
>> to not break compilation
>> Above change will leave dead code in the shim binary temporarily and will be
>> fixed with the introduction of domctl-op wrapping.
> Well, "temporarily" is now getting interesting. While v1 of "Introduce
> CONFIG_DOMCTL" was submitted in time to still be eligible for taking into
> 4.21, that - as indicated elsewhere - is moving us further in an unwanted
> direction.

Do you mean that specifically this patch or the whole patch series is moving us
in unwanted direction? (1)


>   Hence I'm not sure this can even be counted as an in-time
> submission. Plus it looks to be pretty extensive re-work in some areas.

It doesn't clear based on change log why this patch is sent outside "Introduce
CONFIG_DOMCTL" (2) as it looks the same as in (2) and it was reverted once with
the reason "for breaking the x86 build". (I haven't checked what was changed so
it won't lead to build issue again.)

> Hence I'm somewhat weary as to 4.21 here. IOW question, mainly to Oleksii,
> is whether to
> 1) strive to complete that work in time (and hence take the patch here),
> 2) take the patch here, accepting the size regression for the shim, or
> 3) revert what has caused the randconfig issues, and retry the effort in
>     4.22.
>
In the current context, I think I prefer option 3.
However, if option 1 is possible, it could also be considered—except in the
case where the answer to (1) is that the whole patch series is moving us in
an unwanted direction. In that situation, IMO, only option 3 remains viable.

>> Fixes: 568f806cba4c ("xen/x86: remove "depends on !PV_SHIM_EXCLUSIVE"")
>> Reported-by: Jan Beulich
>> Signed-off-by: Penny Zheng
> My earlier question (when the patch still was part of a series) sadly has
> remained unanswered: You've run this through a full round of testing this
> time?
>
> Jan
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    On 8/18/25 10:31 AM, Jan Beulich wrote:
    
    
    
    
    
      
    On 15.08.2025 12:27, Penny Zheng wrote:

    
      
    
        
    In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and
HVM=y results in hvm.c being built, but domctl.c not being built, which leaves
a few functions, like domctl_lock_acquire/release() undefined, causing linking
to fail.
To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile
/hypercall-defs section, with this adjustment, we also need to release
redundant vnuma_destroy() stub definition from PV_SHIM_EXCLUSIVE guardian,
to not break compilation
Above change will leave dead code in the shim binary temporarily and will be
fixed with the introduction of domctl-op wrapping.

    
      
    
      
    Well, "temporarily" is now getting interesting. While v1 of "Introduce
CONFIG_DOMCTL" was submitted in time to still be eligible for taking into
4.21, that - as indicated elsewhere - is moving us further in an unwanted
direction.
    
    
    
    
    Do you mean that specifically this patch or the whole patch series is moving us
in unwanted direction? (1)



    
    
    
      
     Hence I'm not sure this can even be counted as an in-time
submission. Plus it looks to be pretty extensive re-work in some areas.
    
    
    
    
    It doesn't clear based on change log why this patch is sent outside "Introduce
CONFIG_DOMCTL" (2) as it looks the same as in (2) and it was reverted once with
the reason "for breaking the x86 build". (I haven't checked what was changed so
it won't lead to build issue again.)


    
    
    
      
    Hence I'm somewhat weary as to 4.21 here. IOW question, mainly to Oleksii,
is whether to
1) strive to complete that work in time (and hence take the patch here),
2) take the patch here, accepting the size regression for the shim, or
3) revert what has caused the randconfig issues, and retry the effort in
   4.22.


    
    
    
    
    In the current context, I think I prefer option 3.
However, if option 1 is possible, it could also be considered—except in the
case where the answer to (1) is that the whole patch series is moving us in
an unwanted direction. In that situation, IMO, only option 3 remains viable.


    
    
    
      
    
        
    Fixes: 568f806cba4c ("xen/x86: remove "depends on !PV_SHIM_EXCLUSIVE"")
Reported-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Penny Zheng <Penny.Zheng@amd.com>

    
      
    
      
    My earlier question (when the patch still was part of a series) sadly has
remained unanswered: You've run this through a full round of testing this
time?

Jan

    
    
    
  


--------------s2ykdF5OBL13o3ZOvpkj09nB--


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Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
To: Oleksii Kurochko 
Cc: ray.huang@amd.com, Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org,
 Penny Zheng 
References: <20250815102728.1340505-1-Penny.Zheng@amd.com>
 
 
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On 18.08.2025 15:28, Oleksii Kurochko wrote:
> On 8/18/25 10:31 AM, Jan Beulich wrote:
>> On 15.08.2025 12:27, Penny Zheng wrote:
>>> In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and
>>> HVM=y results in hvm.c being built, but domctl.c not being built, which leaves
>>> a few functions, like domctl_lock_acquire/release() undefined, causing linking
>>> to fail.
>>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile
>>> /hypercall-defs section, with this adjustment, we also need to release
>>> redundant vnuma_destroy() stub definition from PV_SHIM_EXCLUSIVE guardian,
>>> to not break compilation
>>> Above change will leave dead code in the shim binary temporarily and will be
>>> fixed with the introduction of domctl-op wrapping.
>> Well, "temporarily" is now getting interesting. While v1 of "Introduce
>> CONFIG_DOMCTL" was submitted in time to still be eligible for taking into
>> 4.21, that - as indicated elsewhere - is moving us further in an unwanted
>> direction.
> 
> Do you mean that specifically this patch or the whole patch series is moving us
> in unwanted direction? (1)

That series. We said we don't want individual CONFIG_SYSCTL, CONFIG_DOMCTL, etc.
Instead a single umbrella option wants introducing. Which means there series
doesn't need re-doing from scratch, but it may end up being a significant re-
work, especially considering that CONFIG_SYSCTL is already in the codebase and
hence now also needs replacing.

>>   Hence I'm not sure this can even be counted as an in-time
>> submission. Plus it looks to be pretty extensive re-work in some areas.
> 
> It doesn't clear based on change log why this patch is sent outside "Introduce
> CONFIG_DOMCTL" (2) as it looks the same as in (2) and it was reverted once with
> the reason "for breaking the x86 build". (I haven't checked what was changed so
> it won't lead to build issue again.)

Before we can even consider further work in the intended direction, the present
randconfig build issue wants sorting. Which supposedly this patch alone does.

Jan


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Date: Mon, 18 Aug 2025 15:37:58 +0200
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Subject: Re: [PATCH v2 1/2] Arm: drop assertion from page_is_ram_type()
To: Jan Beulich ,
 "xen-devel@lists.xenproject.org" 
Cc: Julien Grall , Stefano Stabellini
 , Volodymyr Babchuk ,
 Bertrand Marquis ,
 Michal Orzel ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: 
 <753ce2a1-8d9c-41ba-a066-abf6f625cb60@suse.com>
Content-Language: en-US
From: Oleksii Kurochko 
In-Reply-To: <753ce2a1-8d9c-41ba-a066-abf6f625cb60@suse.com>

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On 8/18/25 9:55 AM, Jan Beulich wrote:
> Its uses in offline_page() and query_page_offline() make it reachable on
> Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
> code added. It being reachable was even mentioned in the commit
> introducing it, claiming it "clearly shouldn't be called on ARM just
> yet".
>
> However, dropping the assertion from a function of this name is deemed
> problematic. Rename it to better reflect its sole purpose outside of
> x86-specific code.
>
> Fixes: 214c4cd94a80 ("xen: arm: stub page_is_ram_type")
> Signed-off-by: Jan Beulich
> ---
> v2: Rename the function used in common code.
> ---
> The new name is chosen such that, down the road, offlining of non-RAM
> could in principle also become possible.

I think it could be useful to put in commit message.

LGTM: Reviewed-by: Oleksii Kurochko

~ Oleksii

>
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -64,10 +64,9 @@ int steal_page(
>       return -EOPNOTSUPP;
>   }
>   
> -int page_is_ram_type(unsigned long mfn, unsigned long mem_type)
> +bool page_is_offlinable(mfn_t mfn)
>   {
> -    ASSERT_UNREACHABLE();
> -    return 0;
> +    return false;
>   }
>   
>   unsigned long domain_get_maximum_gpfn(struct domain *d)
> --- a/xen/arch/x86/mm.c
> +++ b/xen/arch/x86/mm.c
> @@ -425,6 +425,11 @@ int page_is_ram_type(unsigned long mfn,
>       return 0;
>   }
>   
> +bool page_is_offlinable(mfn_t mfn)
> +{
> +    return page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL);
> +}
> +
>   unsigned int page_get_ram_type(mfn_t mfn)
>   {
>       uint64_t last = 0, maddr = mfn_to_maddr(mfn);
> --- a/xen/common/page_alloc.c
> +++ b/xen/common/page_alloc.c
> @@ -1635,7 +1635,7 @@ static unsigned long mark_page_offline(s
>   {
>       unsigned long nx, x, y = pg->count_info;
>   
> -    ASSERT(page_is_ram_type(mfn_x(page_to_mfn(pg)), RAM_TYPE_CONVENTIONAL));
> +    ASSERT(page_is_offlinable(page_to_mfn(pg)));
>       ASSERT(spin_is_locked(&heap_lock));
>   
>       do {
> @@ -1711,7 +1711,7 @@ int offline_page(mfn_t mfn, int broken,
>        * N.B. xen's txt in x86_64 is marked reserved and handled already.
>        * Also kexec range is reserved.
>        */
> -    if ( !page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL) )
> +    if ( !page_is_offlinable(mfn) )
>       {
>           *status = PG_OFFLINE_FAILED | PG_OFFLINE_NOT_CONV_RAM;
>           return -EINVAL;
> @@ -1851,7 +1851,7 @@ int query_page_offline(mfn_t mfn, uint32
>   {
>       struct page_info *pg;
>   
> -    if ( !mfn_valid(mfn) || !page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL) )
> +    if ( !mfn_valid(mfn) || !page_is_offlinable(mfn) )
>       {
>           dprintk(XENLOG_WARNING, "call expand_pages() first\n");
>           return -EINVAL;
> --- a/xen/include/xen/mm.h
> +++ b/xen/include/xen/mm.h
> @@ -144,9 +144,11 @@ unsigned long avail_domheap_pages_region
>   unsigned long avail_node_heap_pages(unsigned int nodeid);
>   #define alloc_domheap_page(d,f) (alloc_domheap_pages(d,0,f))
>   #define free_domheap_page(p)  (free_domheap_pages(p,0))
> +
>   int online_page(mfn_t mfn, uint32_t *status);
>   int offline_page(mfn_t mfn, int broken, uint32_t *status);
>   int query_page_offline(mfn_t mfn, uint32_t *status);
> +bool page_is_offlinable(mfn_t mfn);
>   
>   void heap_init_late(void);
>   
>
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    On 8/18/25 9:55 AM, Jan Beulich wrote:
    
    
    
    
    
      
    Its uses in offline_page() and query_page_offline() make it reachable on
Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
code added. It being reachable was even mentioned in the commit
introducing it, claiming it "clearly shouldn't be called on ARM just
yet".

However, dropping the assertion from a function of this name is deemed
problematic. Rename it to better reflect its sole purpose outside of
x86-specific code.

Fixes: 214c4cd94a80 ("xen: arm: stub page_is_ram_type")
Signed-off-by: Jan Beulich <jbeulich@suse.com>
---
v2: Rename the function used in common code.
---
The new name is chosen such that, down the road, offlining of non-RAM
could in principle also become possible.
    
    
    
    
    I think it could be useful to put in commit message.

LGTM: Reviewed-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

~ Oleksii

    
    
    
      
    
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -64,10 +64,9 @@ int steal_page(
     return -EOPNOTSUPP;
 }
 
-int page_is_ram_type(unsigned long mfn, unsigned long mem_type)
+bool page_is_offlinable(mfn_t mfn)
 {
-    ASSERT_UNREACHABLE();
-    return 0;
+    return false;
 }
 
 unsigned long domain_get_maximum_gpfn(struct domain *d)
--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -425,6 +425,11 @@ int page_is_ram_type(unsigned long mfn,
     return 0;
 }
 
+bool page_is_offlinable(mfn_t mfn)
+{
+    return page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL);
+}
+
 unsigned int page_get_ram_type(mfn_t mfn)
 {
     uint64_t last = 0, maddr = mfn_to_maddr(mfn);
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -1635,7 +1635,7 @@ static unsigned long mark_page_offline(s
 {
     unsigned long nx, x, y = pg->count_info;
 
-    ASSERT(page_is_ram_type(mfn_x(page_to_mfn(pg)), RAM_TYPE_CONVENTIONAL));
+    ASSERT(page_is_offlinable(page_to_mfn(pg)));
     ASSERT(spin_is_locked(&heap_lock));
 
     do {
@@ -1711,7 +1711,7 @@ int offline_page(mfn_t mfn, int broken,
      * N.B. xen's txt in x86_64 is marked reserved and handled already.
      * Also kexec range is reserved.
      */
-    if ( !page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL) )
+    if ( !page_is_offlinable(mfn) )
     {
         *status = PG_OFFLINE_FAILED | PG_OFFLINE_NOT_CONV_RAM;
         return -EINVAL;
@@ -1851,7 +1851,7 @@ int query_page_offline(mfn_t mfn, uint32
 {
     struct page_info *pg;
 
-    if ( !mfn_valid(mfn) || !page_is_ram_type(mfn_x(mfn), RAM_TYPE_CONVENTIONAL) )
+    if ( !mfn_valid(mfn) || !page_is_offlinable(mfn) )
     {
         dprintk(XENLOG_WARNING, "call expand_pages() first\n");
         return -EINVAL;
--- a/xen/include/xen/mm.h
+++ b/xen/include/xen/mm.h
@@ -144,9 +144,11 @@ unsigned long avail_domheap_pages_region
 unsigned long avail_node_heap_pages(unsigned int nodeid);
 #define alloc_domheap_page(d,f) (alloc_domheap_pages(d,0,f))
 #define free_domheap_page(p)  (free_domheap_pages(p,0))
+
 int online_page(mfn_t mfn, uint32_t *status);
 int offline_page(mfn_t mfn, int broken, uint32_t *status);
 int query_page_offline(mfn_t mfn, uint32_t *status);
+bool page_is_offlinable(mfn_t mfn);
 
 void heap_init_late(void);
 


    
    
    
  


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Message-ID: 
Date: Mon, 18 Aug 2025 15:39:03 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH] tools/xl: hide xenstore-features behind option
To: Jan Beulich , Juergen Gross 
Cc: Anthony PERARD ,
 Andrew Cooper , xen-devel@lists.xenproject.org
References: <20250815143236.27641-1-jgross@suse.com>
 <115eca26-32a3-403f-9bf6-553c6b20940c@suse.com>
 <6330d03a-b228-4946-bb5e-c0142d0df6c8@suse.com>
Content-Language: en-US
From: Oleksii Kurochko 
In-Reply-To: <6330d03a-b228-4946-bb5e-c0142d0df6c8@suse.com>

This is a multi-part message in MIME format.
--------------9bLFxSR9aZ0wdvA79F6IpIYB
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On 8/18/25 9:42 AM, Jan Beulich wrote:
> On 15.08.2025 16:35, Juergen Gross wrote:
>> + Release Manager
> While this surely doesn't hurt, my understanding is that bug fixes don't
> require release-acks just yet.

Yes, your understanding is correct.


~ Oleksii

>> On 15.08.25 16:32, Juergen Gross wrote:
>>> In order to be able to use "xl info" before Xenstore has been started
>>> or after it has crashed, hide obtaining the available Xenstore features
>>> behind the new option "-x".
>>>
>>> Fixes: ecce7970cfe7 ("tools/xl: add available Xenstore features to xl info output")
>>> Reported-by: Andrew Cooper
>>> Signed-off-by: Juergen Gross
>>> ---
>>>    docs/man/xl.1.pod.in     |  4 ++++
>>>    docs/man/xl.cfg.5.pod.in |  2 +-
>>>    tools/xl/xl_info.c       | 14 ++++++++++----
>>>    3 files changed, 15 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/docs/man/xl.1.pod.in b/docs/man/xl.1.pod.in
>>> index fe38724b2b..88ccf7ad82 100644
>>> --- a/docs/man/xl.1.pod.in
>>> +++ b/docs/man/xl.1.pod.in
>>> @@ -996,6 +996,10 @@ B
>>>    
>>>    List host NUMA topology information
>>>    
>>> +=item B<-x>, B<--xenstore>
>>> +
>>> +Show Xenstore features available.
>>> +
>>>    =back
>>>    
>>>    =item B
>>> diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
>>> index f0c920b39d..acff45d308 100644
>>> --- a/docs/man/xl.cfg.5.pod.in
>>> +++ b/docs/man/xl.cfg.5.pod.in
>>> @@ -743,7 +743,7 @@ condition.
>>>    =back
>>>    
>>>    The features supported by the running Xenstore instance can be retrieved
>>> -via the B command in dom0.
>>> +via the B command in dom0.
>>>    
>>>    The default value is B<0xffffffff>, meaning that all possible Xenstore
>>>    features are visible by the guest.
>>> diff --git a/tools/xl/xl_info.c b/tools/xl/xl_info.c
>>> index eb019e3ee9..d3583cbf8f 100644
>>> --- a/tools/xl/xl_info.c
>>> +++ b/tools/xl/xl_info.c
>>> @@ -353,7 +353,7 @@ static void output_xenstore_info(void)
>>>        xs_close(xsh);
>>>    }
>>>    
>>> -static void print_info(int numa)
>>> +static void print_info(int numa, bool xs)
>>>    {
>>>        output_nodeinfo();
>>>    
>>> @@ -365,7 +365,8 @@ static void print_info(int numa)
>>>        }
>>>        output_xeninfo();
>>>    
>>> -    output_xenstore_info();
>>> +    if (xs)
>>> +        output_xenstore_info();
>>>    
>>>        maybe_printf("xend_config_format     : 4\n");
>>>    
>>> @@ -631,14 +632,19 @@ int main_info(int argc, char **argv)
>>>        int opt;
>>>        static struct option opts[] = {
>>>            {"numa", 0, 0, 'n'},
>>> +        {"xenstore", 0, 0, 'x'},
>>>            COMMON_LONG_OPTS
>>>        };
>>>        int numa = 0;
>>> +    bool xs = false;
>>>    
>>> -    SWITCH_FOREACH_OPT(opt, "n", opts, "info", 0) {
>>> +    SWITCH_FOREACH_OPT(opt, "nx", opts, "info", 0) {
>>>        case 'n':
>>>            numa = 1;
>>>            break;
>>> +    case 'x':
>>> +        xs = true;
>>> +        break;
>>>        }
>>>    
>>>        /*
>>> @@ -648,7 +654,7 @@ int main_info(int argc, char **argv)
>>>        if (numa == 0 && argc > optind)
>>>            info_name = argv[optind];
>>>    
>>> -    print_info(numa);
>>> +    print_info(numa, xs);
>>>        return 0;
>>>    }
>>>    
--------------9bLFxSR9aZ0wdvA79F6IpIYB
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 7bit



  
    
  
  
    

    
    
    
    
    On 8/18/25 9:42 AM, Jan Beulich wrote:
    
    
    
    
    
      
    On 15.08.2025 16:35, Juergen Gross wrote:

    
      
    
        
    + Release Manager

    
      
    
      
    While this surely doesn't hurt, my understanding is that bug fixes don't
require release-acks just yet.
    
    
    
    
    Yes, your understanding is correct.


~ Oleksii
    
    
    
      
    
        
    On 15.08.25 16:32, Juergen Gross wrote:

    
        
    
          
    In order to be able to use "xl info" before Xenstore has been started
or after it has crashed, hide obtaining the available Xenstore features
behind the new option "-x".

Fixes: ecce7970cfe7 ("tools/xl: add available Xenstore features to xl info output")
Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
  docs/man/xl.1.pod.in     |  4 ++++
  docs/man/xl.cfg.5.pod.in |  2 +-
  tools/xl/xl_info.c       | 14 ++++++++++----
  3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/docs/man/xl.1.pod.in b/docs/man/xl.1.pod.in
index fe38724b2b..88ccf7ad82 100644
--- a/docs/man/xl.1.pod.in
+++ b/docs/man/xl.1.pod.in
@@ -996,6 +996,10 @@ B<OPTIONS>
  
  List host NUMA topology information
  
+=item B<-x>, B<--xenstore>
+
+Show Xenstore features available.
+
  =back
  
  =item B<top>
diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
index f0c920b39d..acff45d308 100644
--- a/docs/man/xl.cfg.5.pod.in
+++ b/docs/man/xl.cfg.5.pod.in
@@ -743,7 +743,7 @@ condition.
  =back
  
  The features supported by the running Xenstore instance can be retrieved
-via the B<xl info> command in dom0.
+via the B<xl info -x> command in dom0.
  
  The default value is B<0xffffffff>, meaning that all possible Xenstore
  features are visible by the guest.
diff --git a/tools/xl/xl_info.c b/tools/xl/xl_info.c
index eb019e3ee9..d3583cbf8f 100644
--- a/tools/xl/xl_info.c
+++ b/tools/xl/xl_info.c
@@ -353,7 +353,7 @@ static void output_xenstore_info(void)
      xs_close(xsh);
  }
  
-static void print_info(int numa)
+static void print_info(int numa, bool xs)
  {
      output_nodeinfo();
  
@@ -365,7 +365,8 @@ static void print_info(int numa)
      }
      output_xeninfo();
  
-    output_xenstore_info();
+    if (xs)
+        output_xenstore_info();
  
      maybe_printf("xend_config_format     : 4\n");
  
@@ -631,14 +632,19 @@ int main_info(int argc, char **argv)
      int opt;
      static struct option opts[] = {
          {"numa", 0, 0, 'n'},
+        {"xenstore", 0, 0, 'x'},
          COMMON_LONG_OPTS
      };
      int numa = 0;
+    bool xs = false;
  
-    SWITCH_FOREACH_OPT(opt, "n", opts, "info", 0) {
+    SWITCH_FOREACH_OPT(opt, "nx", opts, "info", 0) {
      case 'n':
          numa = 1;
          break;
+    case 'x':
+        xs = true;
+        break;
      }
  
      /*
@@ -648,7 +654,7 @@ int main_info(int argc, char **argv)
      if (numa == 0 && argc > optind)
          info_name = argv[optind];
  
-    print_info(numa);
+    print_info(numa, xs);
      return 0;
  }
  

    
        
    
        
    
      
    
      
    
    
    
  


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Date: Mon, 18 Aug 2025 17:01:37 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: Jan Beulich , Doug Goldstein ,
 Stefano Stabellini , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Bertrand Marquis
 , Volodymyr Babchuk ,
 xen-devel@lists.xenproject.org
Subject: Re: [RFC PATCH] misra: allow conversion from unsigned long to
 function pointer
In-Reply-To: 
References: <8cbc9e6d881661d0d7a1055cbcef5a65e20522be.1755109168.git.dmytro_prokopchuk1@epam.com>
 <06120b08-7ce8-4d03-b3cd-cbb22547eca3@suse.com>
 <6990512dab007bfa51e4281dda3cc2f0@bugseng.com>
 
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On 2025-08-18 12:16, Dmytro Prokopchuk1 wrote:
> On 8/14/25 23:43, Nicola Vetrini wrote:
>> On 2025-08-14 10:36, Jan Beulich wrote:
>>> On 13.08.2025 20:27, Dmytro Prokopchuk1 wrote:
>>>> ...
>>>> 
>>>> from `vaddr_t' (that is `unsigned long') to `switch_ttbr_fn*' (that
>>>> is `void(*)(unsigned long)')
>>>> 
>>>> Signed-off-by: Dmytro Prokopchuk 
>>>> ---
>>>> This is just a RFC patch.
>>>> The commit message is not important at this stage.
>>>> 
>>>> I am seeking comments regarding this case.
>>>> 
>>>> Thanks.
>>>> ---
>>>>  automation/eclair_analysis/ECLAIR/deviations.ecl |  8 ++++++++
>>>>  docs/misra/deviations.rst                        | 10 ++++++++++
>>>>  docs/misra/rules.rst                             |  8 +++++++-
>>>>  xen/arch/arm/arm64/mmu/mm.c                      |  2 ++
>>>>  4 files changed, 27 insertions(+), 1 deletion(-)
>>>> 
>>>> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/
>>>> automation/eclair_analysis/ECLAIR/deviations.ecl
>>>> index ebce1ceab9..f9fd6076b7 100644
>>>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>>>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>>>> @@ -365,6 +365,14 @@ constant expressions are required.\""
>>>>  }
>>>>  -doc_end
>>>> 
>>>> +-doc_begin="The conversion from unsigned long to a function pointer
>>>> does not lose any information, provided that the source type has
>>>> enough bits to restore it."
>>>> +-config=MC3A2.R11.1,casts+={safe,
>>>> +  "from(type(canonical(builtin(unsigned long))))
>>>> +   &&to(type(canonical(__function_pointer_types)))
>>>> +   &&relation(definitely_preserves_value)"
>>>> +}
>>>> +-doc_end
>>>> +
>> 
>> This check is not quite targeted at this situation, as the behaviour 
>> of
>> different compilers is a bit of a grey area (even GCC, though that 
>> works
>> in practice). The relation is mostly aimed at testing whether the
>> pointer are represented using the same number of bits as unsigned long
>> (which happens to be the case fortunately).
> 
> Hi Nicola.
> 
> Well, we're telling Eclair the conversion types from() and to(), but 
> can
> Eclair determine their sizes (in bits) for particular architecture?
> I mean, is it possible to avoid this "sizeof(unsigned long) ==
> sizeof(void (*)())" in source code using only Eclair configs?
> 
> Dmytro.
> 

Unfortunately no. ECLAIR knowns the number of bytes used to represent 
pointer and unsigned long, but what it cannot tell is whether the bits 
are preserved after being converted. What we can do, as it was done 
here, is provide a written justification that this is indeed the case 
for the toolchain we care about (GCC in the specific case). I suggest 
having both the config and the assertion to be extra sure that the 
assumption is never broken (despite being very unlikely).

>> 
>>>>  -doc_begin="The conversion from a function pointer to a boolean has
>>>> a well-known semantics that do not lead to unexpected behaviour."
>>>>  -config=MC3A2.R11.1,casts+={safe,
>>>>    "from(type(canonical(__function_pointer_types)))
>>>> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
>>>> index 3c46a1e47a..27848602f6 100644
>>>> --- a/docs/misra/deviations.rst
>>>> +++ b/docs/misra/deviations.rst
>>>> @@ -348,6 +348,16 @@ Deviations related to MISRA C:2012 Rules:
>>>>         to store it.
>>>>       - Tagged as `safe` for ECLAIR.
>>>> 
>>>> +   * - R11.1
>>>> +     - The conversion from unsigned long to a function pointer does
>>>> not lose any
>>>> +       information or violate type safety assumptions if the
>>>> unsigned long type
>>>> +       is guaranteed to be at least as large as a function pointer.
>>>> This ensures
>>>> +       that the function pointer address can be fully represented
>>>> without
>>>> +       truncation or corruption. Macro BUILD_BUG_ON can be
>>>> integrated into the
>>>> +       build system to confirm that 'sizeof(unsigned long) >=
>>>> sizeof(void (*)())'
>>>> +       on all target platforms.
>>> 
>>> If sizeof(unsigned long) > sizeof(void (*)()), there is loss of
>>> information.
>>> Unless (not said here) the unsigned long value itself is the result 
>>> of
>>> converting a function pointer to unsigned long. Whether all of that
>>> together
>>> can be properly expressed to Eclair I don't know. Hence, as Teddy 
>>> already
>>> suggested, == may want specifying instead.
>>> 
>> 
>> +1; it might be worth to add both the eclair config and the
>> BUILD_BUG_ON, noting that neither is sufficient on its own: unless the
>> compiler guarantees not to fiddle with the value is unaltered when 
>> cast
>> back and forth all checks on the number of bits are moot.
>> 
>>>> --- a/xen/arch/arm/arm64/mmu/mm.c
>>>> +++ b/xen/arch/arm/arm64/mmu/mm.c
>>>> @@ -150,6 +150,7 @@ void __init relocate_and_switch_ttbr(uint64_t 
>>>> ttbr)
>>>>      vaddr_t id_addr = virt_to_maddr(relocate_xen);
>>>>      relocate_xen_fn *fn = (relocate_xen_fn *)id_addr;
>>>>      lpae_t pte;
>>>> +    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
>>>> 
>>>>      /* Enable the identity mapping in the boot page tables */
>>>>      update_identity_mapping(true);
>>>> @@ -178,6 +179,7 @@ void __init switch_ttbr(uint64_t ttbr)
>>>>      vaddr_t id_addr = virt_to_maddr(switch_ttbr_id);
>>>>      switch_ttbr_fn *fn = (switch_ttbr_fn *)id_addr;
>>>>      lpae_t pte;
>>>> +    BUILD_BUG_ON(sizeof(unsigned long) < sizeof(fn));
>>>> 
>>>>      /* Enable the identity mapping in the boot page tables */
>>>>      update_identity_mapping(true);
>>> 
>>> BUILD_BUG_ON() is a statement, not a declaration, and hence wants
>>> grouping
>>> as such. Question is whether we indeed want to sprinkle such checks 
>>> all
>>> over the code base. (I expect the two cases here aren't all we have.)
>>> 
>> 
>> +1 as well. I would expect such check to live e.g. in compiler.h or 
>> any
>> similarly general header, since this is a widespread and largely arch-
>> neutral property that Xen wants to be always true I believe.
>> 

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date:	Mon, 18 Aug 2025 17:19:17 +0200
From:	Daniel Kiper 
To:	arraybolt3@gmail.com
Cc:	grub-devel@gnu.org, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v5 2/3] include/xen: Add warning comment for cmd_line
Message-ID: <20250818151917.66iwgczi5t3ildrs@tomti.i.net-space.pl>
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On Wed, Aug 13, 2025 at 08:36:44PM -0500, arraybolt3@gmail.com wrote:
> From: Aaron Rainbolt 
>
> The cmd_line field of the start_info struct is not guaranteed to be
> NUL-terminated, even though it is intended to contain a NUL-terminated
> string. Add a warning about this in a comment so future consumers of
> this field know to check it for a NUL terminator before using it.
>
> Signed-off-by: Aaron Rainbolt 

Reviewed-by: Daniel Kiper 

Daniel


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Cc:	grub-devel@gnu.org, xen-devel@lists.xenproject.org
Subject: Re: [PATCH v5 3/3] kern/xen: Add Xen command line parsing
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On Wed, Aug 13, 2025 at 08:36:45PM -0500, arraybolt3@gmail.com wrote:
> From: Aaron Rainbolt 
>
> Xen traditionally allows customizing guest behavior by passing arguments
> to the VM kernel via the kernel command line. This is no longer possible
> when using GRUB with Xen, as the kernel command line is decided by the
> GRUB configuration file within the guest, not data passed to the guest
> by Xen.
>
> To work around this limitation, enable GRUB to parse a command line
> passed to it by Xen, and expose data from the command line to the GRUB
> configuration as environment variables. These variables can be used in
> the GRUB configuration for any desired purpose, such as extending the
> kernel command line passed to the guest. The command line format is
> inspired by the Linux kernel's command line format.
>
> To reduce the risk of misuse, abuse, or accidents in production, the
> command line will only be parsed if it consists entirely of 7-bit ASCII
> characters, only alphabetical characters and underscores are permitted
> in variable names, and all variable names must start with the string
> "xen_grub_env_". This also allows room for expanding the command line
> arguments accepted by GRUB in the future, should other arguments end up
> becoming desirable in the future.
>
> Signed-off-by: Aaron Rainbolt 

Reviewed-by: Daniel Kiper 

... but two nits below...

> +      else if (is_key_safe (ps.current_word, ps.current_word_len - 1) == true)
> +        {
> +          param_dict_pos = param_dict_len++;
> +          param_keys[param_dict_pos] = grub_malloc (ps.current_word_len);
> +          if (param_keys == NULL)
> +            goto cleanup_main;
> +          param_vals[param_dict_pos] = grub_malloc (2);

grub_zalloc()

> +          if (param_vals == NULL)
> +            goto cleanup_main;
> +
> +          grub_strncpy (param_keys[param_dict_pos], ps.current_word,
> +			ps.current_word_len);
> +          if (param_keys[param_dict_pos][ps.current_word_len - 1] != '\0' )
> +            grub_fatal ("NUL terminator missing from key during Xen cmdline parsing");
> +          grub_strcpy (param_vals[param_dict_pos], "1");

*param_vals[param_dict_pos] = '1';

I can fix these two issues for you before push...

If I do not hear any objections from Xen community in a week or
so I will push this patch into GRUB upstream git repo.

Anyway, thank you for doing this work!

Daniel


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On 2025-08-07 03:00, Jürgen Groß wrote:
> On 07.08.25 03:56, Jason Andryuk wrote:
>> With hyperlaunch, a domU can start before its console ring is connected
>> by xenconsoled.  With nothing emptying the ring, it can quickly fill
>> during boot.  In domU_write_console(), __write_console() returns 0 when
>> the ring is full.  This loops spins until xenconsoled starts emptying
>> the ring:
>>
>>          while (len) {
>>                  ssize_t sent = __write_console(cons, data, len);
>>
>>                  if (sent < 0)
>>                          return sent;
>>
>>                  data += sent;
>>                  len -= sent;
>>
>>                  if (unlikely(len))
>>                          HYPERVISOR_sched_op(SCHEDOP_yield, NULL);
>>          }
>>
>> The goal of this patch is to add a way for the frontend to know when a
>> console is connected.  This patch adds a new flag to the end of the
>> console ring structure.  It is used for the backend to indicate that it
>> has connected and started servicing the page.
>>
>> The two values are
>> XENCONSOLE_DISCONNECTED 1
>> XENCONSOLE_CONNECTED    0
>>
>> XENCONSOLE_DISCONNECTED indicates to the guest that ring is
>> disconnected, so it will not be serviced.  The guest can avoid writing
>> into it in that case.  A domU can use console hypercalls and only
>> transition to the ring when it is connected and won't fill and block.
>>
>> Once the backend (xenconsoled) maps and starts servicing the
>> console, the flag will be set to XENCONSOLE_CONNECTED (0) to indicate
>> the backend state to the frontend.
>>
>> The connected value as 0 will be match the default of a zero-ed console
>> page.  Hyperlaunch can set the flag to XENCONSOLE_DISCONNECTED and let
>> xenconsoled set to XENCONSOLE_CONNECTED.
> 
> I think libxenguest should set XENCONSOLE_DISCONNECTED as well (see below).
> 
>>
>> Old domU hvc_xen drivers won't check the flag.
>> New domU hvc_xen running on a new xen/xenconsoled will work properly.
>> New domU hvc_xen on old xen/xenconsoled should only see a 0 for the flag
>> and behave as if connected.
>>
>> Signed-off-by: Jason Andryuk 
> 
> Adapt the title of the patch?
> 
>> ---
>> v1:
>> Remove evtchn notify call
>> Set connected later when there is no error
>>
>> RFC v3:
>> Flip flag values so 0 is connected.
>>
>> The other option would be to add:
>> uint32_t features
>> uint32_t connected
>>
>> New domUs would check features for a magic value and/or flag to know
>> they can rely on connected transitioning.
>>
>> I think making XENCONSOLE_CONNECTED == 0 side steps the need for
>> an additional features field.  As long as assuming zero-ed memory is
>> acceptable.  However, this only matters for a hyperlaunched guest -
>> xenconsoled will normally readily connect the console and set the value.
> 
> I'd like to consider other cases as well, e.g. a console driver domain.
> So any instance creating a domain with a console ring page should set the
> flag initially to "disconnected".

Setting disconnected for domain creation is fine.  Looking at 
libxenguest, there is also domain restore.  There the console could be 
set to disconnected again before domain restore.  Again, this should 
work and xenconsoled would set it connected again.  I originally 
intended for a single one way transition disconnected -> connected.

Alternatively, restore could skip setting disconnected and just assume 
xenconsoled will promptly attach.  Restore implies a toolstack is 
running, so there isn't the indefinite time period that is involved with 
hyperlaunch/dom0less.  But I guess an actively changing flag accurately 
shows the state, so that is preferable.

>> This assumes that existing frontends are not using the flag space for
>> some other use.
>>
>> Removed idea:
>> Send an event channel notification to let the domU know that xenconsoled
>> is connected.  Xenstored does similar, but for xenstore, the xenstore
>> driver owns the event channel/irq and can rebind it.  For hvc_xen, the
>> hvc subsystem owns the irq, so it isn't readily available for rebinding.
>> This is not implemented.
>>
>> I had the idea for the kernel to use a static key and switch writing
>> from the hypercall to the PV ring once connected.  It didn't actually
>> work in my short attempt - I think changing the static key from within
>> an interupt was wrong.  I fell back to just checking the flag directly
> 
> You'd need to do the static key changing from a worker thread instead.

My static key idea has an issue.  The flag needs to be per-instance, 
primary console and any additional PV consoles, but the kernel has only 
a single function to handle all of them.  Either the primary console 
needs dedicated ops, or the the flag would need to be checked in the 
function.  If the flag will toggle back and forth, then a static key may 
not be appropriate.

Regards,
Jason


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On 18/08/2025 11:02 am, Jan Beulich wrote:
> On 09.08.2025 01:49, Andrew Cooper wrote:
>> --- a/xen/arch/x86/hvm/vmx/vmx.c
>> +++ b/xen/arch/x86/hvm/vmx/vmx.c
>> @@ -4209,8 +4209,18 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_regs *regs)
>>               ((intr_info & INTR_INFO_INTR_TYPE_MASK) ==
>>                MASK_INSR(X86_ET_NMI, INTR_INFO_INTR_TYPE_MASK)) )
>>          {
>> -            do_nmi(regs);
>> -            enable_nmis();
>> +            /*
>> +             * If we exited because of an NMI, NMIs are blocked in hardware,
>> +             * but software is expected to invoke the handler.
>> +             *
>> +             * Use INT $2.  Combined with the current state, it is the correct
>> +             * architectural state for the NMI handler,
> Not quite, I would say: For profiling (and anything else which may want to
> look at the outer context's register state from within the handler) we'd
> always appear to have been in Xen when the NMI "occurred".

We are always inside Xen when the NMI "occurred".

In fact there's a latent bug I didn't spot before.  Nothing appears to,
but if anything in do_nmi() were to to look at regs->entry_vector, it
will see stack rubble (release build) or poison (debug build).

Having gone searching, it's only the watchdog and oprofile which
configure perf counters with NMIs.  vPMU uses fixed interrupts, which
further calls into question it's utility.

>
>> and the IRET on the
>> +             * way back out will unblock NMIs.
>> +             *
>> +             * In FRED mode, we can spot this trick and cause the ERETS to
>> +             * unblock NMIs too.
>> +             */
>> +            asm ("int $2");
>>          }
>>          break;
>>      case EXIT_REASON_MCE_DURING_VMENTRY:
>> --- a/xen/arch/x86/traps.c
>> +++ b/xen/arch/x86/traps.c
>> @@ -2285,8 +2285,22 @@ void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
>>          do_nmi(regs);
>>          break;
>>  
>> -    case X86_ET_HW_EXC:
>>      case X86_ET_SW_INT:
>> +        if ( regs->fred_ss.vector == 2 )
>> +        {
>> +            /*
>> +             * Explicit request from the the VMExit handler.  Rewrite the FRED
>> +             * frame to look like it was a real NMI, and go around again.
>> +             */
>> +            regs->fred_ss.swint = false;
>> +            regs->fred_ss.nmi = true;
>> +            regs->fred_ss.type = X86_ET_NMI;
>> +            regs->fred_ss.insnlen = 0;
>> +
>> +            return entry_from_xen(regs);
> Any particular reason to use recursion here (which the compiler may or may
> not transform)? In fact I'm having trouble seeing why you couldn't invoke
> do_nmi() here directly.

The first way I had entry_from_xen(), this was necessary to get the
right behaviour.  GCC did manage to transform it into a call to do_nmi().

But this has changed somewhat now so I think I can do it with a fallthrough.

~Andrew


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Date: Mon, 18 Aug 2025 15:58:51 -0700 (PDT)
From: Stefano Stabellini 
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To: Julien Grall 
cc: Stefano Stabellini , 
    xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, michal.orzel@amd.com, jbeulich@suse.com, 
    roger.pau@citrix.com
Subject: Re: [PATCH] docs/sending-patches: add GitLab pipeline link
In-Reply-To: <9f5a77c1-ff99-40db-ae49-86e34cc1a391@xen.org>
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On Mon, 18 Aug 2025, Julien Grall wrote:
> Hi Stefano,
> 
> On 15/08/2025 21:12, Stefano Stabellini wrote:
> > When submitting patches to xen-devel, add a link to a successful
> > pipeline run.
> 
> Does this mean we have enough capacity to handle normal CI job + submission?

Yes, it should be OK, especially given that most regular contributors
already run CI jobs before submitting.


> Also, as we try to encourage people to use the gitlab CI. So we would probably
> also encourage them to write new tests because in a lot of cases we will add
> new code. So the pipeline is only going to confirm that we are regressing
> existing tests (which may be irrelevant to the subsystem modified).

Good point


> > Signed-off-by: Stefano Stabellini 
> > 
> > diff --git a/docs/process/sending-patches.pandoc
> > b/docs/process/sending-patches.pandoc
> > index 1991932b68..6e1401ea22 100644
> > --- a/docs/process/sending-patches.pandoc
> > +++ b/docs/process/sending-patches.pandoc
> > @@ -314,3 +314,23 @@ A patch should always be sent **to** the xen-devel
> > mailing list
> >   of all touched code areas should get a copy of the mail via **Cc**. In
> > case
> >   some other recipients are known to be interested in the patch, they can be
> >   added via **Cc**, too.
> > +
> > +## Testing
> > +
> > +Xen Project uses a GitLab-based CI infrastructure. You can request to
> > +have your GitLab account added to the Xen Project organization on GitLab
> > +(https://gitlab.com/xen-project) by reaching out to THE REST maintainers
> > +via xen-devel or Matrix. Once your account is added to the Xen Project
> > +organization on GitLab, also a personal Xen repository will be created
> > +for you under https://gitlab.com/xen-project/people//xen.
> > +You will be able to trigger a GitLab testing pipeline with a single git
> > +push to your personal Xen repository.
> 
> I think it would be worth mentioning that this should be based on a recent
> "master" (I would say less than two days old).

Good idea


> Also, can you clarify why we are asking the user to trigger the pipeline
> rather than having a both that will pick a series and test it?

I'll add an explanation


> > +
> > +When submitting a non-trivial patch or a non-trivial patch series,
> 
> This wording is ambiguous. But even trivial patch could result to regression.
> So I am not sure why we would want to exclude them. Can you clarify?

I'll take it out.


> > +please include a link to the successful GitLab pipeline run on your
> > +personal branch. This information can be added after the `---` line.
> >> +For example:
> > +
> > +    ---
> > +    Test CI pipeline:
> > +
> > https://gitlab.com/xen-project/people/your-username/xen/-/pipelines/1980129839
> 
> Cheers,
> 
> -- 
> Julien Grall
> 


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Date: Mon, 18 Aug 2025 16:00:11 -0700 (PDT)
From: Stefano Stabellini 
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To: xen-devel@lists.xenproject.org
cc: sstabellini@kernel.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, michal.orzel@amd.com, jbeulich@suse.com, 
    julien@xen.org, roger.pau@citrix.com
Subject: [PATCH v2] docs/sending-patches: add GitLab pipeline link
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When submitting patches to xen-devel, add a link to a successful
pipeline run.

Signed-off-by: Stefano Stabellini 
---
Changes in v2:
- address Julien's comments

diff --git a/docs/process/sending-patches.pandoc b/docs/process/sending-patches.pandoc
index 1991932b68..13bb3bf47a 100644
--- a/docs/process/sending-patches.pandoc
+++ b/docs/process/sending-patches.pandoc
@@ -314,3 +314,38 @@ A patch should always be sent **to** the xen-devel mailing list
 of all touched code areas should get a copy of the mail via **Cc**. In case
 some other recipients are known to be interested in the patch, they can be
 added via **Cc**, too.
+
+## Testing
+
+Xen Project uses a GitLab-based CI infrastructure. You can request to
+have your GitLab account added to the Xen Project organization on GitLab
+(https://gitlab.com/xen-project) by reaching out to THE REST maintainers
+via xen-devel or Matrix. Once your account is added to the Xen Project
+organization on GitLab, also a personal Xen repository will be created
+for you under https://gitlab.com/xen-project/people//xen.
+You will be able to trigger a GitLab testing pipeline with a single git
+push to your personal Xen repository.
+
+When submitting a patch or patch series, please include a link to the
+successful GitLab pipeline run on your personal branch. The branch
+should be based on a recent version of the "master" branch, ideally not
+older than two days.
+
+This information can be added after the `---` line.  For example:
+
+    ---
+    Test CI pipeline:
+    https://gitlab.com/xen-project/people/your-username/xen/-/pipelines/1980129839
+
+While it is technically possible to implement an automated system that
+picks up patches and patch series from xen-devel and runs the GitLab
+pipeline on them automatically, doing so would consume a significant
+amount of resources on the testing infrastructure. There is no reliable
+way to automatically determine whether a patch is close to being
+committed or still undergoing substantial review. By having users submit
+the link to the pipeline manually, we can manage testing resources much
+more efficiently.
+
+When submitting new features, please also consider whether you can add a
+GitLab test for the feature to ensure it continues to work correctly in
+the future.


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    Nicola Vetrini , 
    "xen-devel@lists.xenproject.org" , 
    Jan Beulich 
Subject: Re: [RFC] Next steps for MISRA C Rule 17.7 in XEN
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On Mon, 18 Aug 2025, Dmytro Prokopchuk1 wrote:
> On 8/4/25 11:02, Jan Beulich wrote:
> > On 02.08.2025 19:48, Dmytro Prokopchuk1 wrote:
> >> There are a lot of MISRA C R17.7 violations in the XEN.
> >> This rule states: "The value returned by a function having non-void
> >> return type shall be used".
> >>
> >> Actually, need to decide how to deal with these violations.
> >> Quick analyze shown that there are different cases in XEN code base.
> > 
> > Long ago, when we discussed the rules in a mainly abstract way, there already
> > was quite a bit of discussion around this. Stefano - I wonder if you had
> > taken (and have kept) notes back at the time?
> > 
> > Jan
> 
> Hi Stefano.
> 
> This is a kind reminder.

Yes, I am appending below the unmodified notes which I took when we
discussed R17.7. It looks like the decision was to accept the rule and
use a mix of deviations and void casts to reach compliance.


MISRA 17.7 Use expressions' results
-----------------------------------

ACCEPT 17.7

Returning void when appropriate

When function results are used on some of the times. Use a comment to
explain why the return value is ignored and a void cast so that the
warning doesn't trigger (there is also a gcc warning).

Some functions are returning a value just for convenience (e.g. memcpy).
They need to be deviated.

Add must_check to all functions by default somehow? So that developers
will get automatic feedback when they do develpment without having to
wait for ECLAIR

For new code use return values for error, rather than optional
information


From xen-devel-bounces@lists.xenproject.org Mon Aug 18 23:51:43 2025
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Date: Mon, 18 Aug 2025 16:51:31 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Jan Beulich 
cc: Oleksii Kurochko , ray.huang@amd.com, 
    Andrew Cooper , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Anthony PERARD , 
    Michal Orzel , Julien Grall , 
    Stefano Stabellini , 
    xen-devel@lists.xenproject.org, Penny Zheng 
Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
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On Mon, 18 Aug 2025, Jan Beulich wrote:
> On 18.08.2025 15:28, Oleksii Kurochko wrote:
> > On 8/18/25 10:31 AM, Jan Beulich wrote:
> >> On 15.08.2025 12:27, Penny Zheng wrote:
> >>> In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and
> >>> HVM=y results in hvm.c being built, but domctl.c not being built, which leaves
> >>> a few functions, like domctl_lock_acquire/release() undefined, causing linking
> >>> to fail.
> >>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile
> >>> /hypercall-defs section, with this adjustment, we also need to release
> >>> redundant vnuma_destroy() stub definition from PV_SHIM_EXCLUSIVE guardian,
> >>> to not break compilation
> >>> Above change will leave dead code in the shim binary temporarily and will be
> >>> fixed with the introduction of domctl-op wrapping.
> >> Well, "temporarily" is now getting interesting. While v1 of "Introduce
> >> CONFIG_DOMCTL" was submitted in time to still be eligible for taking into
> >> 4.21, that - as indicated elsewhere - is moving us further in an unwanted
> >> direction.
> > 
> > Do you mean that specifically this patch or the whole patch series is moving us
> > in unwanted direction? (1)
> 
> That series. We said we don't want individual CONFIG_SYSCTL, CONFIG_DOMCTL, etc.
> Instead a single umbrella option wants introducing. Which means there series
> doesn't need re-doing from scratch, but it may end up being a significant re-
> work, especially considering that CONFIG_SYSCTL is already in the codebase and
> hence now also needs replacing.

I would not characterize this series as "moving us in an unwanted
direction". Yes, it introduces a separate CONFIG_DOMCTL, which we
agreed we do not want. However, simplifying it to reuse a single
CONFIG is a minor improvement that can be addressed in v2. The main
challenge in this series is adding the #ifdef in the appropriate
places, and using a single CONFIG for domctl and sysctl would
actually help.


> >>   Hence I'm not sure this can even be counted as an in-time
> >> submission. Plus it looks to be pretty extensive re-work in some areas.
> > 
> > It doesn't clear based on change log why this patch is sent outside "Introduce
> > CONFIG_DOMCTL" (2) as it looks the same as in (2) and it was reverted once with
> > the reason "for breaking the x86 build". (I haven't checked what was changed so
> > it won't lead to build issue again.)
> 
> Before we can even consider further work in the intended direction, the present
> randconfig build issue wants sorting. Which supposedly this patch alone does.

I think we should take this patch right away.

I also think we should consider "Introduce CONFIG_DOMCTL" for 4.21.


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Subject: Re: [PATCH v1] xenconsole: Add connected flag
To: Jason Andryuk , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 "Alejandro.GarciaVallejo@amd.com" 
References: <20250807015606.4427-1-jason.andryuk@amd.com>
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To: Jason Andryuk , xen-devel@lists.xenproject.org
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 "Alejandro.GarciaVallejo@amd.com" 
Message-ID: 
Subject: Re: [PATCH v1] xenconsole: Add connected flag
References: <20250807015606.4427-1-jason.andryuk@amd.com>
 <25745d45-d506-4277-8ccd-302cd1316707@suse.com>
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Content-Type: application/pgp-signature; name="OpenPGP_signature.asc"
Content-Description: OpenPGP digital signature
Content-Disposition: attachment; filename="OpenPGP_signature.asc"

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Date: Tue, 19 Aug 2025 08:31:50 +0200
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Subject: Re: [PATCH 23/22] x86/vmx: Adjust NMI handling for FRED
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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 <9657758b-6f10-46c6-84cb-14f425f412b8@citrix.com>
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On 18.08.2025 19:18, Andrew Cooper wrote:
> On 18/08/2025 11:02 am, Jan Beulich wrote:
>> On 09.08.2025 01:49, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/hvm/vmx/vmx.c
>>> +++ b/xen/arch/x86/hvm/vmx/vmx.c
>>> @@ -4209,8 +4209,18 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_regs *regs)
>>>               ((intr_info & INTR_INFO_INTR_TYPE_MASK) ==
>>>                MASK_INSR(X86_ET_NMI, INTR_INFO_INTR_TYPE_MASK)) )
>>>          {
>>> -            do_nmi(regs);
>>> -            enable_nmis();
>>> +            /*
>>> +             * If we exited because of an NMI, NMIs are blocked in hardware,
>>> +             * but software is expected to invoke the handler.
>>> +             *
>>> +             * Use INT $2.  Combined with the current state, it is the correct
>>> +             * architectural state for the NMI handler,
>> Not quite, I would say: For profiling (and anything else which may want to
>> look at the outer context's register state from within the handler) we'd
>> always appear to have been in Xen when the NMI "occurred".
> 
> We are always inside Xen when the NMI "occurred".

How that? The perception is based on "regs", isn't it? They're representing
guest context here, just with ...

> In fact there's a latent bug I didn't spot before.  Nothing appears to,
> but if anything in do_nmi() were to to look at regs->entry_vector, it
> will see stack rubble (release build) or poison (debug build).

... a few fields (apparently wrongly) not filled.

Jan


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To: Jason Andryuk , xen-devel@lists.xenproject.org
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Subject: Re: [PATCH v6 4/8] tools/xenstored: Check NULL domain in
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On 30.07.2025 11:56, Petr Beneš wrote:
> Petr Beneš (3):
>   tools: add sizeof_field and offsetof_end macros
>   hvmloader: fix SMBIOS table length checks
>   hvmloader: add new SMBIOS tables (7, 8, 9, 26, 27, 28)
> 
>  tools/firmware/hvmloader/smbios.c       | 290 ++++++++++++++++++------
>  tools/firmware/hvmloader/smbios_types.h | 109 +++++++--
>  tools/include/xen-tools/common-macros.h |   5 +
>  3 files changed, 317 insertions(+), 87 deletions(-)

Just to mention, also affecting your MAX_ALTP2M series: It is on you to chase
missing acks. It would of course be nice for this work of yours to not go in
only at the last minute, or even miss 4.21.

Jan


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Subject: Re: [RFC] Next steps for MISRA C Rule 17.7 in XEN
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On 19.08.2025 01:45, Stefano Stabellini wrote:
> On Mon, 18 Aug 2025, Dmytro Prokopchuk1 wrote:
>> On 8/4/25 11:02, Jan Beulich wrote:
>>> On 02.08.2025 19:48, Dmytro Prokopchuk1 wrote:
>>>> There are a lot of MISRA C R17.7 violations in the XEN.
>>>> This rule states: "The value returned by a function having non-void
>>>> return type shall be used".
>>>>
>>>> Actually, need to decide how to deal with these violations.
>>>> Quick analyze shown that there are different cases in XEN code base.
>>>
>>> Long ago, when we discussed the rules in a mainly abstract way, there already
>>> was quite a bit of discussion around this. Stefano - I wonder if you had
>>> taken (and have kept) notes back at the time?
>>>
>>> Jan
>>
>> Hi Stefano.
>>
>> This is a kind reminder.
> 
> Yes, I am appending below the unmodified notes which I took when we
> discussed R17.7. It looks like the decision was to accept the rule and
> use a mix of deviations and void casts to reach compliance.
> 
> 
> MISRA 17.7 Use expressions' results
> -----------------------------------
> 
> ACCEPT 17.7
> 
> Returning void when appropriate
> 
> When function results are used on some of the times. Use a comment to
> explain why the return value is ignored and a void cast so that the
> warning doesn't trigger (there is also a gcc warning).
> 
> Some functions are returning a value just for convenience (e.g. memcpy).
> They need to be deviated.
> 
> Add must_check to all functions by default somehow? So that developers
> will get automatic feedback when they do develpment without having to
> wait for ECLAIR

Isn't doing this "by default" equivalent to enabling the compiler warning?
If doing this by default (one way or another), it'll need to be clear how
to mark functions as "exceptions" (like memcpy() that you mention).

Jan


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Subject: Re: [PATCH v4 0/3] hvmloader: add new SMBIOS tables (7,8,9,26,27,28)
To: Jan Beulich 
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	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
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On Tue, Aug 19, 2025 at 8:45=E2=80=AFAM Jan Beulich  wro=
te:
> Just to mention, also affecting your MAX_ALTP2M series: It is on you to c=
hase
> missing acks. It would of course be nice for this work of yours to not go=
 in
> only at the last minute, or even miss 4.21.

Thank you, I've been watching the timeline and wondering, what could I
do to pursue this. Which... I still don't know how to do it.

How exactly can I chase the missing acks? The Submitting Xen Project
Patches wiki page mentions that I should re-send the patch with
[RESEND] in the subject. Should I do just that?

P.


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On 19.08.2025 12:26, Petr Beneš wrote:
> On Tue, Aug 19, 2025 at 8:45 AM Jan Beulich  wrote:
>> Just to mention, also affecting your MAX_ALTP2M series: It is on you to chase
>> missing acks. It would of course be nice for this work of yours to not go in
>> only at the last minute, or even miss 4.21.
> 
> Thank you, I've been watching the timeline and wondering, what could I
> do to pursue this. Which... I still don't know how to do it.
> 
> How exactly can I chase the missing acks? The Submitting Xen Project
> Patches wiki page mentions that I should re-send the patch with
> [RESEND] in the subject. Should I do just that?

Or, less spammy, simply reply to the respective patches with e.g. a Ping: subject
prefix. Or ping people on Matrix.

Jan


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On 15.08.2025 22:41, Andrew Cooper wrote:
> Now there is a local header, asm/cpu-user-regs.h is a far better place for
> these to live.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 



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Date: Tue, 19 Aug 2025 12:40:02 +0200
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Subject: Re: [PATCH v2 08/16] x86: Clean up asm/time.h
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
 <20250815204117.3312742-9-andrew.cooper3@citrix.com>
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From: Jan Beulich 
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In-Reply-To: <20250815204117.3312742-9-andrew.cooper3@citrix.com>
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On 15.08.2025 22:41, Andrew Cooper wrote:
> With asm/tsc.h split out, asm/time.h shouldn't be including asm/msr.h, but it
> turns out that an outrageous number of files (even some headers) are pulling
> their dependentices transitively through asm/time.h -> asm/msr.h
> 
> Most are asm/msr{,-index}.h, but in some cases it's printk(), va_args, and
> even PRIxxx macros.
> 
> Give asm/time.h an SPDX tag, and strip trailing whitespace.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 
preferably ...

> --- a/xen/arch/x86/include/asm/time.h
> +++ b/xen/arch/x86/include/asm/time.h
> @@ -1,8 +1,7 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#ifndef X86_TIME_H
> +#define X86_TIME_H
>  
> -#ifndef __X86_TIME_H__
> -#define __X86_TIME_H__
> -
> -#include 
>  #include 
>  
>  typedef u64 cycles_t;
> @@ -38,6 +37,7 @@ uint64_t cf_check acpi_pm_tick_to_ns(uint64_t ticks);
>  
>  uint64_t tsc_ticks2ns(uint64_t ticks);
>  
> +struct cpu_user_regs;
>  uint64_t pv_soft_rdtsc(const struct vcpu *v, const struct cpu_user_regs *regs);
>  uint64_t gtime_to_gtsc(const struct domain *d, uint64_t time);
>  uint64_t gtsc_to_gtime(const struct domain *d, uint64_t tsc);
> @@ -47,7 +47,7 @@ int tsc_set_info(struct domain *d, uint32_t tsc_mode, uint64_t elapsed_nsec,
>  
>  void tsc_get_info(struct domain *d, uint32_t *tsc_mode, uint64_t *elapsed_nsec,
>                    uint32_t *gtsc_khz, uint32_t *incarnation);
> -   
> +
>  
>  void force_update_vcpu_system_time(struct vcpu *v);

... with that one line dropped rather than just pruned of trailing blanks, so
we no longer have a double blank line here.

Jan


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Subject: Re: [PATCH v2 09/16] x86: Clean up asm/msr.h
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
 <20250815204117.3312742-10-andrew.cooper3@citrix.com>
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From: Jan Beulich 
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In-Reply-To: <20250815204117.3312742-10-andrew.cooper3@citrix.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit

On 15.08.2025 22:41, Andrew Cooper wrote:
> Now that content has been split out, minimise the header files as msr.h is
> included by many translation units.  A few more TUs were pulling dependencies
> in transitively, so fix them up.
> 
> Give asm/time.h an SPDX tag, and strip trailing whitespace.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 

I think though that ...

> --- a/xen/arch/x86/include/asm/msr.h
> +++ b/xen/arch/x86/include/asm/msr.h
> @@ -1,18 +1,13 @@
> -#ifndef __ASM_MSR_H
> -#define __ASM_MSR_H
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#ifndef X86_MSR_H
> +#define X86_MSR_H
>  
> -#include "msr-index.h"
> -
> -#include 
>  #include 
>  #include 
> -#include 
> -
> -#include 
>  
> +#include 
>  #include 
> -#include 
> -#include 
> +#include 
>  
>  #define rdmsr(msr,val1,val2) \
>       __asm__ __volatile__("rdmsr" \
> @@ -113,11 +108,6 @@ static inline int wrmsr_safe(unsigned int msr, uint64_t val)
>      return -EFAULT;
>  }
>  
> -#define rdpmc(counter,low,high) \
> -     __asm__ __volatile__("rdpmc" \
> -			  : "=a" (low), "=d" (high) \
> -			  : "c" (counter))
> -

... this removal wants mentioning in the description. I'm actually surprised this
is unused - how does vPMU get away?

Jan


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From: Ayan Kumar Halder 
To: 
CC: Ayan Kumar Halder , Stefano Stabellini
	, Bertrand Marquis , Michal
 Orzel , Artem Mygaiev 
Subject: [PATCH v4 1/2] docs: fusa: Define the requirements for XEN_VERSION hypercall.
Date: Tue, 19 Aug 2025 12:27:08 +0100
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Define the requirements which are common for all the commands.

Signed-off-by: Ayan Kumar Halder 
---
Changes from -

v1 - 1. Fixed `XenProd~version_hyp_ret_val~1` requirement as Xen does not return
0 for success in all the cases.
2. Reworded the requirements so as to write them from Xen's perspective (not
domain's perspective).

v2 - 1. Specified the register details.
2. Specified the type of buffer.

v3 - Fixed some wordings to make it precise (eg register details, bit fields).

 .../fusa/reqs/design-reqs/arm64/hypercall.rst | 60 +++++++++++++++++++
 docs/fusa/reqs/index.rst                      |  2 +
 docs/fusa/reqs/market-reqs/reqs.rst           | 16 +++++
 .../reqs/product-reqs/version_hypercall.rst   | 42 +++++++++++++
 4 files changed, 120 insertions(+)
 create mode 100644 docs/fusa/reqs/design-reqs/arm64/hypercall.rst
 create mode 100644 docs/fusa/reqs/product-reqs/version_hypercall.rst

diff --git a/docs/fusa/reqs/design-reqs/arm64/hypercall.rst b/docs/fusa/reqs/design-reqs/arm64/hypercall.rst
new file mode 100644
index 0000000000..82ecf690a3
--- /dev/null
+++ b/docs/fusa/reqs/design-reqs/arm64/hypercall.rst
@@ -0,0 +1,60 @@
+.. SPDX-License-Identifier: CC-BY-4.0
+
+Hypercall
+=========
+
+Instruction
+-----------
+
+`XenSwdgn~arm64_hyp_instr~1`
+
+Description:
+Xen shall treat domain hvc instruction execution (with 0xEA1) as hypercall
+requests.
+
+Rationale:
+
+Comments:
+Hypercall is one of the communication mechanism between Xen and domains.
+Domains use hypercalls for various requests to Xen.
+The exception syndrome register should have the following values :-
+ESR_EL2.ISS should be 0xEA1.
+ESR_EL2.EC should be 0x16.
+
+Covers:
+ - `XenProd~version_hyp_first_param~1`
+ - `XenProd~version_hyp_second_param~1`
+
+Parameters
+----------
+
+`XenSwdgn~arm64_hyp_param~1`
+
+Description:
+Xen shall use x0 - x4 core registers to obtain the arguments for domain hypercall
+requests.
+
+Rationale:
+
+Comments:
+Xen shall read x0 for the first argument, x1 for the second argument and so on.
+
+Covers:
+ - `XenProd~version_hyp_first_param~1`
+ - `XenProd~version_hyp_second_param~1`
+
+Hypercall number
+----------------
+
+`XenSwdgn~arm64_hyp_num~1`
+
+Description:
+Xen shall read x16 to obtain the hypercall number.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenProd~version_hyp_first_param~1`
+ - `XenProd~version_hyp_second_param~1`
diff --git a/docs/fusa/reqs/index.rst b/docs/fusa/reqs/index.rst
index 1088a51d52..d8683edce7 100644
--- a/docs/fusa/reqs/index.rst
+++ b/docs/fusa/reqs/index.rst
@@ -10,5 +10,7 @@ Requirements documentation
    market-reqs/reqs
    product-reqs/reqs
    product-reqs/arm64/reqs
+   product-reqs/version_hypercall
    design-reqs/arm64/generic-timer
    design-reqs/arm64/sbsa-uart
+   design-reqs/arm64/hypercall
diff --git a/docs/fusa/reqs/market-reqs/reqs.rst b/docs/fusa/reqs/market-reqs/reqs.rst
index 2d297ecc13..7e3912c8f8 100644
--- a/docs/fusa/reqs/market-reqs/reqs.rst
+++ b/docs/fusa/reqs/market-reqs/reqs.rst
@@ -79,3 +79,19 @@ Comments:
 
 Needs:
  - XenProd
+
+Version hypercall
+-----------------
+
+`XenMkt~version_hypercall~1`
+
+Description:
+Xen shall provide a hypercall for the domains to retrieve Xen's version, type
+and compilation information.
+
+Rationale:
+
+Comments:
+
+Needs:
+ - XenProd
diff --git a/docs/fusa/reqs/product-reqs/version_hypercall.rst b/docs/fusa/reqs/product-reqs/version_hypercall.rst
new file mode 100644
index 0000000000..b824c539b0
--- /dev/null
+++ b/docs/fusa/reqs/product-reqs/version_hypercall.rst
@@ -0,0 +1,42 @@
+.. SPDX-License-Identifier: CC-BY-4.0
+
+Version hypercall
+=================
+
+First Parameter
+---------------
+
+`XenProd~version_hyp_first_param~1`
+
+Description:
+Xen shall treat the value stored in x0 as the command number for the hypercall.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~version_hypercall~1`
+
+Needs:
+ - XenSwdgn
+
+Second Parameter
+----------------
+
+`XenProd~version_hyp_second_param~1`
+
+Description:
+Xen shall treat the value stored in x1 as a domain virtual address (mapped as
+Normal Inner Write-Back Outer Write-Back Inner-Shareable) to buffer in domain's
+memory.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~version_hypercall~1`
+
+Needs:
+ - XenSwdgn
-- 
2.25.1



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From: Ayan Kumar Halder 
To: 
CC: Ayan Kumar Halder , Stefano Stabellini
	, Bertrand Marquis , Michal
 Orzel , Artem Mygaiev 
Subject: [PATCH v4 2/2] docs: fusa: Add the requirements for some of the commands of XEN_VERSION
Date: Tue, 19 Aug 2025 12:27:09 +0100
Message-ID: <20250819112709.3789987-2-ayan.kumar.halder@amd.com>
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We have written the requirements for some of the commands of the XEN_VERSION
hypercall.

Signed-off-by: Ayan Kumar Halder 
---
Changes from -

v1 - 1. Reworded the requirement so as to avoid mentioining variable names
or hardcoded strings. Otherwise, one would need to change the requirement
each time the code changes.

v2 - 1. Moved few changes to previous patch.

v3 - 1. Removed the internal implementation details from the design requirements
so that they can be verified by black box tests.

 .../fusa/reqs/design-reqs/arm64/hypercall.rst | 15 ++++
 .../design-reqs/arm64/version_hypercall.rst   | 32 +++++++
 .../reqs/design-reqs/version_hypercall.rst    | 63 ++++++++++++++
 docs/fusa/reqs/index.rst                      |  3 +
 docs/fusa/reqs/product-reqs/hypercall.rst     | 20 +++++
 .../reqs/product-reqs/version_hypercall.rst   | 85 +++++++++++++++++++
 6 files changed, 218 insertions(+)
 create mode 100644 docs/fusa/reqs/design-reqs/arm64/version_hypercall.rst
 create mode 100644 docs/fusa/reqs/design-reqs/version_hypercall.rst
 create mode 100644 docs/fusa/reqs/product-reqs/hypercall.rst

diff --git a/docs/fusa/reqs/design-reqs/arm64/hypercall.rst b/docs/fusa/reqs/design-reqs/arm64/hypercall.rst
index 82ecf690a3..3b4af18323 100644
--- a/docs/fusa/reqs/design-reqs/arm64/hypercall.rst
+++ b/docs/fusa/reqs/design-reqs/arm64/hypercall.rst
@@ -58,3 +58,18 @@ Comments:
 Covers:
  - `XenProd~version_hyp_first_param~1`
  - `XenProd~version_hyp_second_param~1`
+
+Return value
+------------
+
+`XenSwdgn~arm64_ret_val~1`
+
+Description:
+Xen shall store the return value in x0.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenProd~hyp_err_ret_val~1`
diff --git a/docs/fusa/reqs/design-reqs/arm64/version_hypercall.rst b/docs/fusa/reqs/design-reqs/arm64/version_hypercall.rst
new file mode 100644
index 0000000000..ccfcb35a7a
--- /dev/null
+++ b/docs/fusa/reqs/design-reqs/arm64/version_hypercall.rst
@@ -0,0 +1,32 @@
+.. SPDX-License-Identifier: CC-BY-4.0
+
+Capabilities
+------------
+
+`XenSwdgn~arm64_capabilities~1`
+
+Description:
+Xen shall return xen-3.0-aarch64 to denote that the cpu is running in arm64 mode.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenProd~version_hyp_capabilities_cmd~1`
+
+Capabilities AArch32
+--------------------
+
+`XenSwdgn~arm64_capabilities_aarch32~1`
+
+Description:
+Xen shall return xen-3.0-armv7l to denote that the cpu is running in arm32 mode.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenProd~version_hyp_capabilities_cmd~1`
+
diff --git a/docs/fusa/reqs/design-reqs/version_hypercall.rst b/docs/fusa/reqs/design-reqs/version_hypercall.rst
new file mode 100644
index 0000000000..b05481b9dc
--- /dev/null
+++ b/docs/fusa/reqs/design-reqs/version_hypercall.rst
@@ -0,0 +1,63 @@
+.. SPDX-License-Identifier: CC-BY-4.0
+
+Version
+-------
+
+`XenSwdgn~version~1`
+
+Description:
+Xen shall return its version when XENVER_version command is invoked.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenProd~version_hyp_version_cmd~1`
+
+Error copying buffer
+--------------------
+
+`XenSwdgn~error_copy_buffer~1`
+
+Description:
+Xen shall return -EFAULT if it is not able to copy data to domain's buffer.
+
+Rationale:
+-EFAULT is one of the error code defined in
+http://xenbits.xen.org/gitweb/?p=xen.git;a=blob;f=xen/include/public/errno.h.
+
+Comments:
+
+Covers:
+ - `XenProd~hyp_err_ret_val~1`
+
+Extraversion
+------------
+
+`XenSwdgn~extraversion~1`
+
+Description:
+Xen shall return its extraversion when XENVER_extraversion command is invoked.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenProd~version_hyp_extraversion_cmd~1`
+
+Changeset
+---------
+
+`XenSwdgn~changeset~1`
+
+Description:
+Xen shall return its changeset when XENVER_changeset command is invoked.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenProd~version_hyp_changeset_cmd~1`
diff --git a/docs/fusa/reqs/index.rst b/docs/fusa/reqs/index.rst
index d8683edce7..de19b0cda2 100644
--- a/docs/fusa/reqs/index.rst
+++ b/docs/fusa/reqs/index.rst
@@ -11,6 +11,9 @@ Requirements documentation
    product-reqs/reqs
    product-reqs/arm64/reqs
    product-reqs/version_hypercall
+   product-reqs/hypercall
    design-reqs/arm64/generic-timer
    design-reqs/arm64/sbsa-uart
    design-reqs/arm64/hypercall
+   design-reqs/arm64/version_hypercall
+   design-reqs/version_hypercall
diff --git a/docs/fusa/reqs/product-reqs/hypercall.rst b/docs/fusa/reqs/product-reqs/hypercall.rst
new file mode 100644
index 0000000000..9fb46cf451
--- /dev/null
+++ b/docs/fusa/reqs/product-reqs/hypercall.rst
@@ -0,0 +1,20 @@
+.. SPDX-License-Identifier: CC-BY-4.0
+
+Error Return Value
+------------------
+
+`XenProd~hyp_err_ret_val~1`
+
+Description:
+In case any hypercall fails, Xen shall return one of the error codes defined
+in http://xenbits.xen.org/gitweb/?p=xen.git;a=blob;f=xen/include/public/errno.h.
+
+Rationale:
+
+Comments:
+
+Covers:
+ - `XenMkt~version_hypercall~1`
+
+Needs:
+ - XenSwdgn
diff --git a/docs/fusa/reqs/product-reqs/version_hypercall.rst b/docs/fusa/reqs/product-reqs/version_hypercall.rst
index b824c539b0..466eb4108b 100644
--- a/docs/fusa/reqs/product-reqs/version_hypercall.rst
+++ b/docs/fusa/reqs/product-reqs/version_hypercall.rst
@@ -40,3 +40,88 @@ Covers:
 
 Needs:
  - XenSwdgn
+
+Version command
+---------------
+
+`XenProd~version_hyp_version_cmd~1`
+
+Description:
+Xen shall provide a command (num 0) for  hypercall (num 17) to retrieve Xen's
+version in the domain's register 0.
+
+Rationale:
+
+Comments:
+Xen version is composed of major (ie version) and minor (ie subversion) number.
+The minor number is encoded in the 16 least significant bits and the major number
+is encoded in the top remaining bits.
+
+Covers:
+ - `XenMkt~version_hypercall~1`
+
+Needs:
+ - XenSwdgn
+
+Extraversion command
+--------------------
+
+`XenProd~version_hyp_extraversion_cmd~1`
+
+Description:
+Xen shall provide a command (num 1) for hypercall (num 17) to copy its
+extraversion in the domain's buffer.
+
+Rationale:
+
+Comments:
+Xen's extra version consists of a string passed with 'XEN_VENDORVERSION' command
+line parameter while building Xen.
+
+Covers:
+ - `XenMkt~version_hypercall~1`
+
+Needs:
+ - XenSwdgn
+
+Capabilities command
+--------------------
+
+`XenProd~version_hyp_capabilities_cmd~1`
+
+Description:
+Xen shall provide a command (num 3) for hypercall (num 17) to copy its
+capabilities to the domain's buffer.
+
+Rationale:
+
+Comments:
+Capabilities related information is represented by char[1024].
+For Arm64, the capabilities should contain "xen-3.0-aarch64" string.
+
+Covers:
+ - `XenMkt~version_hypercall~1`
+
+Needs:
+ - XenSwdgn
+
+Changeset command
+-----------------
+
+`XenProd~version_hyp_changeset_cmd~1`
+
+Description:
+Xen shall provide a command (num 4) for hypercall (num 17) to copy changeset
+to the domain's buffer.
+
+Rationale:
+
+Comments:
+Changeset is string denoting the date, time and git hash of the last change
+made to Xen's codebase.
+
+Covers:
+ - `XenMkt~version_hypercall~1`
+
+Needs:
+ - XenSwdgn
-- 
2.25.1



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Subject: Re: [PATCH v2 10/16] x86/svm: Rename variable in
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To: Andrew Cooper 
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On 15.08.2025 22:41, Andrew Cooper wrote:
> We're about to turn the rdmsr() macro into a real function, at which point
> Eclair complains that we're now shadowing an identifer.
> 
> Rename rdmsr to is_rdmsr.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 


> --- a/xen/arch/x86/hvm/svm/svm.c
> +++ b/xen/arch/x86/hvm/svm/svm.c
> @@ -2087,14 +2087,14 @@ static int cf_check svm_msr_write_intercept(
>  static void svm_do_msr_access(struct cpu_user_regs *regs)
>  {
>      struct vcpu *curr = current;
> -    bool rdmsr = curr->arch.hvm.svm.vmcb->exitinfo1 == 0;
> -    int rc, inst_len = svm_get_insn_len(curr, rdmsr ? INSTR_RDMSR
> -                                                    : INSTR_WRMSR);
> +    bool is_rdmsr = curr->arch.hvm.svm.vmcb->exitinfo1 == 0;

Could also have used the shorter "read" or "rd" instead.

Jan

> +    int rc, inst_len = svm_get_insn_len(curr, is_rdmsr ? INSTR_RDMSR
> +                                                       : INSTR_WRMSR);
>  
>      if ( inst_len == 0 )
>          return;
>  
> -    if ( rdmsr )
> +    if ( is_rdmsr )
>      {
>          uint64_t msr_content = 0;
>  



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Subject: Re: [PATCH v2 11/16] x86/msr: Change rdmsr() to have normal API
To: Andrew Cooper 
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On 15.08.2025 22:41, Andrew Cooper wrote:
> We want a consistent MSR API, and these want to be named rdmsr() and wrmsr(),
> but not with their current APIs.  The current rdmsr() flavours writing to
> their parameters by name makes code that reads like invalid C, and is
> unergonomic to use in lots of cases.
> 
> Change the API, and update the callers all in one go.  Where appropriate,
> update the write side to wrmsrns() as per the recommendation.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
> 
> I do have a more creative solution if this patch is considered to be too
> large.  https://gitlab.com/xen-project/hardware/xen-staging/-/commit/e13cf25d06d08481e2c138daa1fd902cf36d757b

I'm not concerned by the size of this patch.

> --- a/xen/arch/x86/cpu/intel.c
> +++ b/xen/arch/x86/cpu/intel.c
> @@ -23,17 +23,17 @@ static uint32_t __ro_after_init mcu_opt_ctrl_val;
>  
>  void update_mcu_opt_ctrl(void)
>  {
> -    uint32_t mask = mcu_opt_ctrl_mask, lo, hi;
> +    uint32_t mask = mcu_opt_ctrl_mask, val;
>  
>      if ( !mask )
>          return;
>  
> -    rdmsr(MSR_MCU_OPT_CTRL, lo, hi);
> +    val = rdmsr(MSR_MCU_OPT_CTRL);
>  
> -    lo &= ~mask;
> -    lo |= mcu_opt_ctrl_val;
> +    val &= ~mask;
> +    val |= mcu_opt_ctrl_val;
>  
> -    wrmsr(MSR_MCU_OPT_CTRL, lo, hi);
> +    wrmsrns(MSR_MCU_OPT_CTRL, val);
>  }

I don't consider it a good idea to suddenly clear the upper half of this
MSR, and ...

> @@ -51,17 +51,17 @@ static uint32_t __ro_after_init pb_opt_ctrl_val;
>  
>  void update_pb_opt_ctrl(void)
>  {
> -    uint32_t mask = pb_opt_ctrl_mask, lo, hi;
> +    uint32_t mask = pb_opt_ctrl_mask, val;
>  
>      if ( !mask )
>          return;
>  
> -    rdmsr(MSR_PB_OPT_CTRL, lo, hi);
> +    val = rdmsr(MSR_PB_OPT_CTRL);
>  
> -    lo &= ~mask;
> -    lo |= pb_opt_ctrl_val;
> +    val &= ~mask;
> +    val |= pb_opt_ctrl_val;
>  
> -    wrmsr(MSR_PB_OPT_CTRL, lo, hi);
> +    wrmsrns(MSR_PB_OPT_CTRL, val);
>  }

... this one.

> @@ -456,15 +456,15 @@ static void __init probe_mwait_errata(void)
>   */
>  static void Intel_errata_workarounds(struct cpuinfo_x86 *c)
>  {
> -	unsigned long lo, hi;
> +	uint64_t val;
>  
>  	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
> -		rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
> -		if ((lo & (1<<9)) == 0) {
> +		val = rdmsr(MSR_IA32_MISC_ENABLE);
> +		if ((val & (1 << 9)) == 0) {
>  			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
>  			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
> -			lo |= (1<<9);	/* Disable hw prefetching */
> -			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
> +			val |= (1 << 9); /* Disable hw prefetching */
> +			wrmsrns(MSR_IA32_MISC_ENABLE, val);
>  		}
>  	}

Move val into the more narrow scope at the same time?

> @@ -699,7 +715,7 @@ void cf_check vmx_cpu_dead(unsigned int cpu)
>  
>  static int _vmx_cpu_up(bool bsp)
>  {
> -    u32 eax, edx;
> +    u32 eax;

Like you do elsewhere, switch to uint32_t at the same time?

> --- a/xen/arch/x86/tsx.c
> +++ b/xen/arch/x86/tsx.c
> @@ -42,6 +42,8 @@ void tsx_init(void)
>  {
>      static bool __read_mostly once;
>  
> +    uint64_t val;
> +
>      /*

No real need for yet another newline, I would say.

Jan


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Subject: Re: [PATCH v2 11/16] x86/msr: Change rdmsr() to have normal API
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 18.08.2025 13:34, Andrew Cooper wrote:
> On 15/08/2025 9:41 pm, Andrew Cooper wrote:
>> diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
>> index 530b9eb39abc..9c6b8c291d6e 100644
>> --- a/xen/arch/x86/cpu/common.c
>> +++ b/xen/arch/x86/cpu/common.c
>> @@ -329,6 +329,7 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
>>  void __init early_cpu_init(bool verbose)
>>  {
>>  	struct cpuinfo_x86 *c = &boot_cpu_data;
>> +	uint64_t val;
>>  	u32 eax, ebx, ecx, edx;
>>  
>>  	c->x86_cache_alignment = 32;
>> @@ -412,10 +413,11 @@ void __init early_cpu_init(bool verbose)
>>  			    &c->x86_capability[FEATURESET_7c0],
>>  			    &c->x86_capability[FEATURESET_7d0]);
>>  
>> -		if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability))
>> -			rdmsr(MSR_ARCH_CAPABILITIES,
>> -			      c->x86_capability[FEATURESET_m10Al],
>> -			      c->x86_capability[FEATURESET_m10Ah]);
>> +		if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) {
>> +			val = rdmsr(MSR_ARCH_CAPABILITIES);
>> +			c->x86_capability[FEATURESET_m10Al] = val;
>> +			c->x86_capability[FEATURESET_m10Al] = val >> 32;
> 
> This is a typo.  Fixed locally.

Both of them, I expect.

Jan


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Subject: Re: [PATCH v2 12/16] x86/msr: Change wrmsr() to take a single
 parameter
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
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On 15.08.2025 22:41, Andrew Cooper wrote:
> --- a/xen/arch/x86/nmi.c
> +++ b/xen/arch/x86/nmi.c
> @@ -218,16 +218,16 @@ void disable_lapic_nmi_watchdog(void)
>          return;
>      switch (boot_cpu_data.x86_vendor) {
>      case X86_VENDOR_AMD:
> -        wrmsr(MSR_K7_EVNTSEL0, 0, 0);
> +        wrmsrns(MSR_K7_EVNTSEL0, 0);

Since you switch to non-serializing here, ...

> @@ -308,11 +308,11 @@ static void setup_k7_watchdog(void)
>          | K7_EVNTSEL_USR
>          | K7_NMI_EVENT;
>  
> -    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
> +    wrmsr(MSR_K7_EVNTSEL0, evntsel);
>      write_watchdog_counter("K7_PERFCTR0");
>      apic_write(APIC_LVTPC, APIC_DM_NMI);
>      evntsel |= K7_EVNTSEL_ENABLE;
> -    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
> +    wrmsr(MSR_K7_EVNTSEL0, evntsel);
>  }

... why not also here?

> --- a/xen/arch/x86/oprofile/op_model_athlon.c
> +++ b/xen/arch/x86/oprofile/op_model_athlon.c
> @@ -34,7 +34,7 @@
>  #define MAX_COUNTERS FAM15H_NUM_COUNTERS
>  
>  #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, (msr_content));} while (0)
> -#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1);} while (0)
> +#define CTR_WRITE(l,msrs,c) do { wrmsr(msrs->counters[(c)].addr, -l); } while (0)

This isn't obviously correct (as in: no functional change): The macro is,
for example, passed reset_value[] contents, which is of type unsigned long.
Quite possible that the original code was wrong, though.

In any event l wants parenthesizing.

Jan


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Subject: Re: [PATCH v2 13/16] x86/msr: Use MSR_IMM when available
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
 <20250815204117.3312742-14-andrew.cooper3@citrix.com>
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On 15.08.2025 22:41, Andrew Cooper wrote:
> Most MSR accesses have compile time constant indexes.  By using the immediate
> form when available, the decoder can start issuing uops directly for the
> relevant MSR, rather than having to issue uops to implement "switch (%ecx)".
> Modern CPUs have tens of thousands of MSRs, so that's quite an if/else chain.
> 
> Create __{rdmsr,wrmsrns}_imm() helpers and use them from {rdmsr,wrmsrns}()
> when the compiler can determine that the msr index is known at compile time.
> 
> At the instruction level, the combined ABI is awkward.  Explain our choices in
> detail.
> 
> Signed-off-by: Andrew Cooper 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
> 
> The expression wrmsrns(MSR_STAR, rdmsr(MSR_STAR)) now yields:
> 
>   :
>       b9 81 00 00 c0          mov    $0xc0000081,%ecx
>       0f 32                   rdmsr
>       48 c1 e2 20             shl    $0x20,%rdx
>       48 09 d0                or     %rdx,%rax
>       48 89 c2                mov    %rax,%rdx
>       48 c1 ea 20             shr    $0x20,%rdx
>       2e 0f 30                cs wrmsr
>       e9 a3 84 e8 ff          jmp    ffff82d040204260 <__x86_return_thunk>
> 
> which is as good as we can manage.  The alternative form of this looks like:
> 
>   :
>       b9 81 00 00 c0          mov    $0xc0000081,%ecx
>       c4 e7 7b f6 c0 81 00    rdmsr  $0xc0000081,%rax
>       00 c0
>       2e c4 e7 7a f6 c0 81    cs wrmsrns %rax,$0xc0000081
>       00 00 c0
>       e9 xx xx xx xx          jmp    ffff82d040204260 <__x86_return_thunk>
> 
> Still TBD.  We ought to update the *_safe() forms too.  rdmsr_safe() is easier
> because the potential #GP locations line up, but there need to be two variants
> because of

Because of ...?

> --- a/xen/arch/x86/include/asm/alternative.h
> +++ b/xen/arch/x86/include/asm/alternative.h
> @@ -151,6 +151,13 @@ extern void alternative_instructions(void);
>          ALTERNATIVE(oldinstr, newinstr, feature)                        \
>          :: input )
>  
> +#define alternative_input_2(oldinstr, newinstr1, feature1,              \
> +                            newinstr2, feature2, input...)              \
> +    asm_inline volatile (                                               \
> +        ALTERNATIVE_2(oldinstr, newinstr1, feature1,                    \
> +                      newinstr2, feature2)                              \
> +        :: input )
> +
>  /* Like alternative_input, but with a single output argument */
>  #define alternative_io(oldinstr, newinstr, feature, output, input...)   \
>      asm_inline volatile (                                               \
> diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
> index 1bd27b989a4d..2ceff6cca8bb 100644
> --- a/xen/arch/x86/include/asm/msr.h
> +++ b/xen/arch/x86/include/asm/msr.h
> @@ -29,10 +29,52 @@
>   *  wrmsrl(MSR_FOO, val);
>   */
>  
> -static inline uint64_t rdmsr(unsigned int msr)
> +/*
> + * RDMSR with a compile-time constant index, when available.  Falls back to
> + * plain RDMSR.
> + */
> +static always_inline uint64_t __rdmsr_imm(uint32_t msr)
> +{
> +    uint64_t val;
> +
> +    /*
> +     * For best performance, RDMSR $msr, %r64 is recommended.  For
> +     * compatibility, we need to fall back to plain RDMSR.
> +     *
> +     * The combined ABI is awkward, because RDMSR $imm produces an r64,
> +     * whereas WRMSR{,NS} produces a split edx:eax pair.
> +     *
> +     * Always use RDMSR $imm, %rax, because it has the most in common with the
> +     * legacy form.  When MSR_IMM isn't available, emit logic to fold %edx
> +     * back into %rax.
> +     *
> +     * Let the compiler do %ecx setup.  This does mean there's a useless `mov
> +     * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it means
> +     * the compiler can de-duplicate the setup in the common case of reading
> +     * and writing the same MSR.
> +     */
> +    alternative_io(
> +        "rdmsr\n\t"
> +        "shl $32, %%rdx\n\t"
> +        "or %%rdx, %%rax\n\t",
> +
> +        /* RDMSR $msr, %rax */
> +        ".byte 0xc4,0xe7,0x7b,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
> +
> +        "=a" (val),

Strictly speaking "=&a". Not that it matters much here; just to not
set a bad precedent.

> @@ -55,11 +97,51 @@ static inline void wrmsr(unsigned int msr, uint64_t val)
>  }
>  #define wrmsrl(msr, val) wrmsr(msr, val)
>  
> +/*
> + * Non-serialising WRMSR with a compile-time constant index, when available.
> + * Falls back to plain WRMSRNS, or to a serialising WRMSR.
> + */
> +static always_inline void __wrmsrns_imm(uint32_t msr, uint64_t val)
> +{
> +    /*
> +     * For best performance, WRMSRNS %r64, $msr is recommended.  For
> +     * compatibility, we need to fall back to plain WRMSRNS, or to WRMSR.
> +     *
> +     * The combined ABI is awkward, because WRMSRNS $imm takes a single r64,
> +     * whereas WRMSR{,NS} takes a split edx:eax pair.
> +     *
> +     * Always use WRMSRNS %rax, $imm, because it has the most in common with
> +     * the legacy forms.  When MSR_IMM isn't available, emit setup logic for
> +     * %edx.
> +     *
> +     * Let the compiler do %ecx setup.  This does mean there's a useless `mov
> +     * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it means
> +     * the compiler can de-duplicate the setup in the common case of reading
> +     * and writing the same MSR.
> +     */
> +    alternative_input_2(
> +        "mov %%rax, %%rdx\n\t"
> +        "shr $32, %%rdx\n\t"
> +        ".byte 0x2e; wrmsr",
> +
> +        /* CS WRMSRNS %rax, $msr */
> +        ".byte 0x2e,0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
> +
> +        "mov %%rax, %%rdx\n\t"
> +        "shr $32, %%rdx\n\t"
> +        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,

Isn't this the wrong way round for hardware which has both features? The
last active alternative wins, iirc.

Jan


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Date: Tue, 19 Aug 2025 13:55:45 +0100
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Subject: Re: [PATCH v2 09/16] x86: Clean up asm/msr.h
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
 <20250815204117.3312742-10-andrew.cooper3@citrix.com>
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On 19/08/2025 11:42 am, Jan Beulich wrote:
> On 15.08.2025 22:41, Andrew Cooper wrote:
>> Now that content has been split out, minimise the header files as msr.h is
>> included by many translation units.  A few more TUs were pulling dependencies
>> in transitively, so fix them up.
>>
>> Give asm/time.h an SPDX tag, and strip trailing whitespace.
>>
>> No functional change.
>>
>> Signed-off-by: Andrew Cooper 
> Acked-by: Jan Beulich 

Thanks.

>
> I think though that ...
>
>> --- a/xen/arch/x86/include/asm/msr.h
>> +++ b/xen/arch/x86/include/asm/msr.h
>> @@ -1,18 +1,13 @@
>> -#ifndef __ASM_MSR_H
>> -#define __ASM_MSR_H
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +#ifndef X86_MSR_H
>> +#define X86_MSR_H
>>  
>> -#include "msr-index.h"
>> -
>> -#include 
>>  #include 
>>  #include 
>> -#include 
>> -
>> -#include 
>>  
>> +#include 
>>  #include 
>> -#include 
>> -#include 
>> +#include 
>>  
>>  #define rdmsr(msr,val1,val2) \
>>       __asm__ __volatile__("rdmsr" \
>> @@ -113,11 +108,6 @@ static inline int wrmsr_safe(unsigned int msr, uint64_t val)
>>      return -EFAULT;
>>  }
>>  
>> -#define rdpmc(counter,low,high) \
>> -     __asm__ __volatile__("rdpmc" \
>> -			  : "=a" (low), "=d" (high) \
>> -			  : "c" (counter))
>> -
> ... this removal wants mentioning in the description. I'm actually surprised this
> is unused - how does vPMU get away?

Kernel software can't really use RDPMC.  Everything else about perf
counters needs model specific knowledge, and given that model specific
knowledge, transforming the indices into another address space is just a
waste.

~Andrew


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Subject: Re: [PATCH v2 14/16] x86/fsgsbase: Split out __{rd,wr}gskern()
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On 15.08.2025 22:41, Andrew Cooper wrote:
> Right now they're inline in {read,write}_gs_shadow(), but we're going to need
> to use these elsewhere to support FRED.

But why "kern"? We're not dealing with GS in kernel / user terms, but in
real / shadow ones. I'm also not quite happy with the double leading
underscores, fwiw.

As to using them elsewhere to support FRED: How can we when they use SWAPGS,
which isn't available under FRED?

> --- a/xen/arch/x86/include/asm/fsgsbase.h
> +++ b/xen/arch/x86/include/asm/fsgsbase.h
> @@ -32,6 +32,17 @@ static inline unsigned long __rdgsbase(void)
>      return base;
>  }
>  
> +static inline unsigned long __rdgskern(void)
> +{
> +    unsigned long base;
> +
> +    asm_inline volatile ( "swapgs\n\t"
> +                          "rdgsbase %0\n\t"
> +                          "swapgs" : "=r" (base) );

Again strictly speaking "=&r", if already you open-code rdgsbase() now.

Jan


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Subject: Re: [PATCH v2 15/16] x86/fsgsbase: Update fs/gs helpers to use
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On 15.08.2025 22:41, Andrew Cooper wrote:
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -2733,8 +2733,8 @@ static uint64_t cf_check vmx_get_reg(struct vcpu *v, unsigned int reg)
>      case MSR_SHADOW_GS_BASE:
>          if ( v != curr )
>              return v->arch.hvm.vmx.shadow_gs;
> -        rdmsrl(MSR_SHADOW_GS_BASE, val);
> -        return val;
> +        else
> +            return rdmsr(MSR_SHADOW_GS_BASE);
>      }

Here and below, can we please do without the pointless "else"? Strictly
speaking in Misra's terms that's "dead code" (things working identically
without), and I'm quite happy that I can now use this argument to
support my personal antipathy to this style of coding. Or else use the
conditional operator in such cases (where applicable).

Jan


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Nicola Vetrini
	, Doug Goldstein , Stefano
 Stabellini , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: [PATCH] misra: add deviation for PrintErrMesg() function
Thread-Topic: [PATCH] misra: add deviation for PrintErrMesg() function
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Date: Tue, 19 Aug 2025 13:12:59 +0000
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MISRA C Rule 2.1 states: "A project shall not contain unreachable code."

The function 'PrintErrMesg()' is implemented to never return control to
its caller. At the end of its execution, it calls 'blexit()', which, in
turn, invokes '__builtin_unreachable()'. This makes the 'return false;'
statement in 'read_file()' function unreachable.

Configure Eclair to do not report this violation.

Signed-off-by: Dmytro Prokopchuk 
---
Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1991518214
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 4 ++++
 docs/misra/deviations.rst                        | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index 7f3fd35a33..5c262aa5ad 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -41,6 +41,10 @@ not executable, and therefore it is safe for them to be =
unreachable."
 -call_properties+=3D{"name(__builtin_unreachable)&&stmt(begin(any_exp(macr=
o(name(ASSERT_UNREACHABLE)))))", {"noreturn(false)"}}
 -doc_end
=20
+-doc_begin=3D"Unreachability caused by the call to the 'PrintErrMesg()' fu=
nction is deliberate, as it terminates execution, ensuring no control flow =
continues past this point."
+-config=3DMC3A2.R2.1,reports+=3D{deliberate, "any_area(^.*PrintErrMesg.*$ =
&& any_loc(file(^xen/common/efi/boot\\.c$)))"}
+-doc_end
+
 -doc_begin=3D"Proving compliance with respect to Rule 2.2 is generally imp=
ossible:
 see https://arxiv.org/abs/2212.13933 for details. Moreover, peer review gi=
ves us
 confidence that no evidence of errors in the program's logic has been miss=
ed due
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..8df3c207ff 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -97,6 +97,13 @@ Deviations related to MISRA C:2012 Rules:
        Xen expects developers to ensure code remains safe and reliable in =
builds,
        even when debug-only assertions like `ASSERT_UNREACHABLE() are remo=
ved.
=20
+   * - R2.1
+     - Function `PrintErrMesg()` terminates execution (at the end it calls
+       `blexit()`, which, in turn, invokes `__builtin_unreachable()`), ens=
uring
+       no code beyond this point is ever reached. This guarantees that exe=
cution
+       won't incorrectly proceed or introduce unwanted behavior.
+     - Tagged as `deliberate` for ECLAIR.
+
    * - R2.2
      - Proving compliance with respect to Rule 2.2 is generally impossible=
:
        see ``_ for details. Moreover, pe=
er
--=20
2.43.0


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On 15.08.2025 22:41, Andrew Cooper wrote:
> It turns out that using the higher level helpers adjacent like this leads to
> terrible code generation.  Due to -fno-strict-alising, the store into state->
> invalidates the read_cr4() address calculation (which is really cpu_info->cr4
> under the hood), meaning that it can't be hoisted.
> 
> As a result we get "locate the top of stack block, get cr4, and see if
> FSGSBASE is set" repeated 3 times, and an unreasoanble number of basic blocks.
> 
> Hoist the calculation manually, which results in two basic blocks.
> 
> Signed-off-by: Andrew Cooper 

Otoh the function here isn't really performance or size critical. I'm undecided
whether the undesirable open-coding or the bad code gen are the lesser evil.

> --- a/xen/arch/x86/traps.c
> +++ b/xen/arch/x86/traps.c
> @@ -118,9 +118,18 @@ static void read_registers(struct extra_state *state)
>      state->cr3 = read_cr3();
>      state->cr4 = read_cr4();
>  
> -    state->fsb = read_fs_base();
> -    state->gsb = read_gs_base();
> -    state->gss = read_gs_shadow();
> +    if ( state->cr4 & X86_CR4_FSGSBASE )
> +    {
> +        state->fsb = __rdfsbase();
> +        state->gsb = __rdgsbase();
> +        state->gss = __rdgskern();

This, btw, supports my desire to not use "kern" but "shadow" in the new helper's
name.

Jan


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Subject: Re: [PATCH] misra: add deviation for PrintErrMesg() function
To: Dmytro Prokopchuk1 
Cc: Nicola Vetrini ,
 Doug Goldstein ,
 Stefano Stabellini ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 19.08.2025 15:12, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 2.1 states: "A project shall not contain unreachable code."
> 
> The function 'PrintErrMesg()' is implemented to never return control to
> its caller. At the end of its execution, it calls 'blexit()', which, in
> turn, invokes '__builtin_unreachable()'. This makes the 'return false;'
> statement in 'read_file()' function unreachable.

I'm disappointed. In earlier review comments I pointed out that there are
two. Yet you say "the", without further disambiguation.

> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -41,6 +41,10 @@ not executable, and therefore it is safe for them to be unreachable."
>  -call_properties+={"name(__builtin_unreachable)&&stmt(begin(any_exp(macro(name(ASSERT_UNREACHABLE)))))", {"noreturn(false)"}}
>  -doc_end
>  
> +-doc_begin="Unreachability caused by the call to the 'PrintErrMesg()' function is deliberate, as it terminates execution, ensuring no control flow continues past this point."
> +-config=MC3A2.R2.1,reports+={deliberate, "any_area(^.*PrintErrMesg.*$ && any_loc(file(^xen/common/efi/boot\\.c$)))"}
> +-doc_end

I don't understand the description here, nor ...

> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -97,6 +97,13 @@ Deviations related to MISRA C:2012 Rules:
>         Xen expects developers to ensure code remains safe and reliable in builds,
>         even when debug-only assertions like `ASSERT_UNREACHABLE() are removed.
>  
> +   * - R2.1
> +     - Function `PrintErrMesg()` terminates execution (at the end it calls
> +       `blexit()`, which, in turn, invokes `__builtin_unreachable()`), ensuring
> +       no code beyond this point is ever reached. This guarantees that execution
> +       won't incorrectly proceed or introduce unwanted behavior.
> +     - Tagged as `deliberate` for ECLAIR.

.. the text here. PrintErrMesg() is noreturn. Why would anything need saying about
it? Isn't the problem here solely with the tail of read_file(), while other uses
of PrintErrMesg() are okay?

Jan


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Subject: Re: [PATCH v2 01/16] x86/msr: Implement rdmsr_safe() in C
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
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On 18/08/2025 12:23 pm, Jan Beulich wrote:
> On 15.08.2025 22:41, Andrew Cooper wrote:
>> ... in preparation to be able to use asm goto.
>>
>> Notably this mean that the value parameter must be taken by pointer rather
>> than by value.
>>
>> No functional change.
>>
>> Signed-off-by: Andrew Cooper 
> In principle
> Reviewed-by: Jan Beulich 

Thanks.

> However, having looked at patch 2 first, ...
>
>> @@ -879,14 +879,14 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
>>      case 0x8f: /* Sapphire Rapids X */
>>  
>>          if ( (c != &boot_cpu_data && !ppin_msr) ||
>> -             rdmsr_safe(MSR_PPIN_CTL, val) )
>> +             rdmsr_safe(MSR_PPIN_CTL, &val) )
>>              return;
> ... with this, wouldn't we be better off using ...
>
>>          /* If PPIN is disabled, but not locked, try to enable. */
>>          if ( !(val & (PPIN_ENABLE | PPIN_LOCKOUT)) )
>>          {
>>              wrmsr_safe(MSR_PPIN_CTL, val | PPIN_ENABLE);
>> -            rdmsr_safe(MSR_PPIN_CTL, val);
>> +            rdmsr_safe(MSR_PPIN_CTL, &val);
> ... plain rdmsr() here, thus not leaving it open to the behavioral change
> patch 2 comes with?

Yeah, probably.  At the point we've read it once, and written to it, a
subsequent read is not going fail.

I'll adjust, although it will have to be a rdmsrl().

~Andrew


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Subject: Re: [PATCH v2 01/16] x86/msr: Implement rdmsr_safe() in C
From: Andrew Cooper 
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 19/08/2025 2:28 pm, Andrew Cooper wrote:
> On 18/08/2025 12:23 pm, Jan Beulich wrote:
>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>> ... in preparation to be able to use asm goto.
>>>
>>> Notably this mean that the value parameter must be taken by pointer rather
>>> than by value.
>>>
>>> No functional change.
>>>
>>> Signed-off-by: Andrew Cooper 
>> In principle
>> Reviewed-by: Jan Beulich 
> Thanks.
>
>> However, having looked at patch 2 first, ...
>>
>>> @@ -879,14 +879,14 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
>>>      case 0x8f: /* Sapphire Rapids X */
>>>  
>>>          if ( (c != &boot_cpu_data && !ppin_msr) ||
>>> -             rdmsr_safe(MSR_PPIN_CTL, val) )
>>> +             rdmsr_safe(MSR_PPIN_CTL, &val) )
>>>              return;
>> ... with this, wouldn't we be better off using ...
>>
>>>          /* If PPIN is disabled, but not locked, try to enable. */
>>>          if ( !(val & (PPIN_ENABLE | PPIN_LOCKOUT)) )
>>>          {
>>>              wrmsr_safe(MSR_PPIN_CTL, val | PPIN_ENABLE);
>>> -            rdmsr_safe(MSR_PPIN_CTL, val);
>>> +            rdmsr_safe(MSR_PPIN_CTL, &val);
>> ... plain rdmsr() here, thus not leaving it open to the behavioral change
>> patch 2 comes with?
> Yeah, probably.  At the point we've read it once, and written to it, a
> subsequent read is not going fail.
>
> I'll adjust, although it will have to be a rdmsrl().

No.  That would introduce a bug, because this path ignores a write error
too.

There isn't actually a problem even with patch 2, because of the how the
logic is currently laid out.

~Andrew


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Date: Tue, 19 Aug 2025 14:52:24 +0100
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Subject: Re: [PATCH v2 02/16] x86/msr: Rework rdmsr_safe() using asm goto()
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 18/08/2025 12:27 pm, Jan Beulich wrote:
> On 15.08.2025 22:41, Andrew Cooper wrote:
>> ... on capable toolchains.
>>
>> This avoids needing to hold rc in a register across the RDMSR, and in most
>> cases removes direct testing and branching based on rc, as the fault label can
>> be rearranged to directly land on the out-of-line block.
>>
>> There is a subtle difference in behaviour.  The old behaviour would, on fault,
>> still produce 0's and write to val.
>>
>> The new behaviour only writes val on success, and write_msr() is the only
>> place where this matters.  Move temp out of switch() scope and initialise it
>> to 0.
> But what's the motivation behind making this behavioral change? At least in
> the cases where the return value isn't checked, it would feel safer if we
> continued clearing the value. Even if in all cases where this could matter
> (besides the one you cover here) one can prove correctness by looking at
> surrounding code.

I didn't realise I'd made a change at first, but it's a consequence of
the compiler's ability to rearrange basic blocks.

It can be fixed with ...

>
>> --- a/xen/arch/x86/include/asm/msr.h
>> +++ b/xen/arch/x86/include/asm/msr.h
>> @@ -55,6 +55,24 @@ static inline void wrmsrns(uint32_t msr, uint64_t val)
>>  /* rdmsr with exception handling */
>>  static inline int rdmsr_safe(unsigned int msr, uint64_t *val)
>>  {
>> +#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
>> +    uint64_t lo, hi;
>> +    asm_inline goto (
>> +        "1: rdmsr\n\t"
>> +        _ASM_EXTABLE(1b, %l[fault])
>> +        : "=a" (lo), "=d" (hi)
>> +        : "c" (msr)
>> +        :
>> +        : fault );
>> +
>> +    *val = lo | (hi << 32);
>> +
>> +    return 0;
>> +
>> + fault:

    *val = 0;

here, but I don't want to do this.  Because val is by pointer and
generally spilled to the stack, the compiler can't optimise away the store.

I'd far rather get a real compiler error, than to have logic relying on
the result of a faulting MSR read.

>> +    return -EFAULT;
>> +#else
>>      int rc;
>>      uint64_t lo, hi;
> ... the same being needed here?

Fixed.

~Andrew


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From: Dmytro Prokopchuk1 
To: Jan Beulich 
CC: Nicola Vetrini , Doug Goldstein
	, Stefano Stabellini , Andrew
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	, Michal Orzel , Julien
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	, "xen-devel@lists.xenproject.org"
	
Subject: Re: [PATCH] misra: add deviation for PrintErrMesg() function
Thread-Topic: [PATCH] misra: add deviation for PrintErrMesg() function
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Date: Tue, 19 Aug 2025 14:32:52 +0000
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Subject: Re: [PATCH] misra: add deviation for PrintErrMesg() function
To: Dmytro Prokopchuk1 
Cc: Nicola Vetrini ,
 Doug Goldstein ,
 Stefano Stabellini ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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References: <5944d87aae330246b7dab6eebd04d5d71a7d7e8f.1755608417.git.dmytro_prokopchuk1@epam.com>
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On 19.08.2025 16:32, Dmytro Prokopchuk1 wrote:
> On 8/19/25 16:25, Jan Beulich wrote:
>> On 19.08.2025 15:12, Dmytro Prokopchuk1 wrote:
>>> MISRA C Rule 2.1 states: "A project shall not contain unreachable code."
>>>
>>> The function 'PrintErrMesg()' is implemented to never return control to
>>> its caller. At the end of its execution, it calls 'blexit()', which, in
>>> turn, invokes '__builtin_unreachable()'. This makes the 'return false;'
>>> statement in 'read_file()' function unreachable.
>>
>> I'm disappointed. In earlier review comments I pointed out that there are
>> two. Yet you say "the", without further disambiguation.
>>
>>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>>> @@ -41,6 +41,10 @@ not executable, and therefore it is safe for them to be unreachable."
>>>   -call_properties+={"name(__builtin_unreachable)&&stmt(begin(any_exp(macro(name(ASSERT_UNREACHABLE)))))", {"noreturn(false)"}}
>>>   -doc_end
>>>   
>>> +-doc_begin="Unreachability caused by the call to the 'PrintErrMesg()' function is deliberate, as it terminates execution, ensuring no control flow continues past this point."
>>> +-config=MC3A2.R2.1,reports+={deliberate, "any_area(^.*PrintErrMesg.*$ && any_loc(file(^xen/common/efi/boot\\.c$)))"}
>>> +-doc_end
>>
>> I don't understand the description here, nor ...
>>
>>> --- a/docs/misra/deviations.rst
>>> +++ b/docs/misra/deviations.rst
>>> @@ -97,6 +97,13 @@ Deviations related to MISRA C:2012 Rules:
>>>          Xen expects developers to ensure code remains safe and reliable in builds,
>>>          even when debug-only assertions like `ASSERT_UNREACHABLE() are removed.
>>>   
>>> +   * - R2.1
>>> +     - Function `PrintErrMesg()` terminates execution (at the end it calls
>>> +       `blexit()`, which, in turn, invokes `__builtin_unreachable()`), ensuring
>>> +       no code beyond this point is ever reached. This guarantees that execution
>>> +       won't incorrectly proceed or introduce unwanted behavior.
>>> +     - Tagged as `deliberate` for ECLAIR.
>>
>> .. the text here. PrintErrMesg() is noreturn. Why would anything need saying about
>> it? Isn't the problem here solely with the tail of read_file(), while other uses
>> of PrintErrMesg() are okay?
> 
> I'm a little bit confused.
> 
> As I understood you proposed to insert the SAF comment before the 
> 'return' statement (with proper justification).
> 
> And current Eclair configuration & descriptions are not good at all.

Not sure how that's related, but apart from this, ...

> Am I right?

... yes. Yet how is what you submitted here related to the issue in read_file(),
which may be addressable by a simple SAF comment (as you say in your reply)?

Jan


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Subject: Re: [PATCH v2 01/16] x86/msr: Implement rdmsr_safe() in C
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References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 19.08.2025 15:35, Andrew Cooper wrote:
> On 19/08/2025 2:28 pm, Andrew Cooper wrote:
>> On 18/08/2025 12:23 pm, Jan Beulich wrote:
>>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>>> ... in preparation to be able to use asm goto.
>>>>
>>>> Notably this mean that the value parameter must be taken by pointer rather
>>>> than by value.
>>>>
>>>> No functional change.
>>>>
>>>> Signed-off-by: Andrew Cooper 
>>> In principle
>>> Reviewed-by: Jan Beulich 
>> Thanks.
>>
>>> However, having looked at patch 2 first, ...
>>>
>>>> @@ -879,14 +879,14 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
>>>>      case 0x8f: /* Sapphire Rapids X */
>>>>  
>>>>          if ( (c != &boot_cpu_data && !ppin_msr) ||
>>>> -             rdmsr_safe(MSR_PPIN_CTL, val) )
>>>> +             rdmsr_safe(MSR_PPIN_CTL, &val) )
>>>>              return;
>>> ... with this, wouldn't we be better off using ...
>>>
>>>>          /* If PPIN is disabled, but not locked, try to enable. */
>>>>          if ( !(val & (PPIN_ENABLE | PPIN_LOCKOUT)) )
>>>>          {
>>>>              wrmsr_safe(MSR_PPIN_CTL, val | PPIN_ENABLE);
>>>> -            rdmsr_safe(MSR_PPIN_CTL, val);
>>>> +            rdmsr_safe(MSR_PPIN_CTL, &val);
>>> ... plain rdmsr() here, thus not leaving it open to the behavioral change
>>> patch 2 comes with?
>> Yeah, probably.  At the point we've read it once, and written to it, a
>> subsequent read is not going fail.
>>
>> I'll adjust, although it will have to be a rdmsrl().
> 
> No.  That would introduce a bug, because this path ignores a write error
> too.

Why would there be a bug? Irrespective of the WRMSR, we know the earlier
RDMSR worked.

> There isn't actually a problem even with patch 2, because of the how the
> logic is currently laid out.

Yes, the logic would still be correct, just less obviously so.

Jan


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Subject: Re: [PATCH v2 02/16] x86/msr: Rework rdmsr_safe() using asm goto()
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
 <20250815204117.3312742-3-andrew.cooper3@citrix.com>
 
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On 19.08.2025 15:52, Andrew Cooper wrote:
> On 18/08/2025 12:27 pm, Jan Beulich wrote:
>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>> ... on capable toolchains.
>>>
>>> This avoids needing to hold rc in a register across the RDMSR, and in most
>>> cases removes direct testing and branching based on rc, as the fault label can
>>> be rearranged to directly land on the out-of-line block.
>>>
>>> There is a subtle difference in behaviour.  The old behaviour would, on fault,
>>> still produce 0's and write to val.
>>>
>>> The new behaviour only writes val on success, and write_msr() is the only
>>> place where this matters.  Move temp out of switch() scope and initialise it
>>> to 0.
>> But what's the motivation behind making this behavioral change? At least in
>> the cases where the return value isn't checked, it would feel safer if we
>> continued clearing the value. Even if in all cases where this could matter
>> (besides the one you cover here) one can prove correctness by looking at
>> surrounding code.
> 
> I didn't realise I'd made a change at first, but it's a consequence of
> the compiler's ability to rearrange basic blocks.
> 
> It can be fixed with ...
> 
>>
>>> --- a/xen/arch/x86/include/asm/msr.h
>>> +++ b/xen/arch/x86/include/asm/msr.h
>>> @@ -55,6 +55,24 @@ static inline void wrmsrns(uint32_t msr, uint64_t val)
>>>  /* rdmsr with exception handling */
>>>  static inline int rdmsr_safe(unsigned int msr, uint64_t *val)
>>>  {
>>> +#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
>>> +    uint64_t lo, hi;
>>> +    asm_inline goto (
>>> +        "1: rdmsr\n\t"
>>> +        _ASM_EXTABLE(1b, %l[fault])
>>> +        : "=a" (lo), "=d" (hi)
>>> +        : "c" (msr)
>>> +        :
>>> +        : fault );
>>> +
>>> +    *val = lo | (hi << 32);
>>> +
>>> +    return 0;
>>> +
>>> + fault:
> 
>     *val = 0;
> 
> here, but I don't want to do this.  Because val is by pointer and
> generally spilled to the stack, the compiler can't optimise away the store.

But the compiler is dealing with such indirection in inline functions just
fine. I don't expect it would typically spill val to the stack. Is there
anything specific here that you think would make this more likely?

> I'd far rather get a real compiler error, than to have logic relying on
> the result of a faulting MSR read.

A compiler error? (Hmm, perhaps you think of uninitialized variable
diagnostics. That may or may not trigger, depending on how else the
caller's variable is used.)

Jan


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From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: Roger Pau Monne ,
	Jan Beulich ,
	Andrew Cooper 
Subject: [PATCH] x86/iommu: setup MMCFG ahead of IOMMU
Date: Tue, 19 Aug 2025 19:18:26 +0200
Message-ID: <20250819171826.60700-1-roger.pau@citrix.com>
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Otherwise the PCI accesses to segments different than the first one done by
the IOMMU initialization code would silently fail by returning all ones.

Introduce a new helper, called pci_setup(), and move both the creation of
PCI segment 0 internal data structures, plus the parsing of ACPI MMCFG
table to it.

Signed-off-by: Roger Pau Monné 
---
 xen/arch/x86/acpi/boot.c              |  2 --
 xen/arch/x86/include/asm/pci.h        |  2 ++
 xen/arch/x86/pci.c                    | 16 ++++++++++++++++
 xen/arch/x86/setup.c                  |  7 +++----
 xen/arch/x86/x86_64/mmconfig-shared.c |  3 +++
 5 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/acpi/boot.c b/xen/arch/x86/acpi/boot.c
index 3901f9d9825b..1ca2360e0065 100644
--- a/xen/arch/x86/acpi/boot.c
+++ b/xen/arch/x86/acpi/boot.c
@@ -748,8 +748,6 @@ int __init acpi_boot_init(void)
 
 	acpi_table_parse(ACPI_SIG_HPET, acpi_parse_hpet);
 
-	acpi_mmcfg_init();
-
 	erst_init();
 
 	acpi_hest_init();
diff --git a/xen/arch/x86/include/asm/pci.h b/xen/arch/x86/include/asm/pci.h
index 665b32116521..0b98081aeaa4 100644
--- a/xen/arch/x86/include/asm/pci.h
+++ b/xen/arch/x86/include/asm/pci.h
@@ -74,4 +74,6 @@ bool pci_check_bar(const struct pci_dev *pdev, mfn_t start, mfn_t end);
 struct rangeset;
 int pci_sanitize_bar_memory(struct rangeset *r);
 
+void pci_setup(void);
+
 #endif /* __X86_PCI_H__ */
diff --git a/xen/arch/x86/pci.c b/xen/arch/x86/pci.c
index 26bb7f6a3c3a..e75a29e851a7 100644
--- a/xen/arch/x86/pci.c
+++ b/xen/arch/x86/pci.c
@@ -6,7 +6,10 @@
 
 #include 
 #include 
+
+#include 
 #include 
+
 #include 
 
 static DEFINE_SPINLOCK(pci_config_lock);
@@ -139,6 +142,19 @@ int pci_sanitize_bar_memory(struct rangeset *r)
     return 0;
 }
 
+void __init pci_setup(void)
+{
+    /*
+     * Ahead of any ACPI table parsing make sure we have control structures
+     * for PCI segment 0.
+     */
+    if ( pci_add_segment(0) )
+        panic("Could not initialize PCI segment 0\n");
+
+    /* Parse ACPI MMCFG ahead of IOMMU, so accesses to segments > 0 is setup. */
+    acpi_mmcfg_init();
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 6fb42c5a5f95..bd648323bfed 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1938,11 +1938,10 @@ void asmlinkage __init noreturn __start_xen(void)
     setup_system_domains();
 
     /*
-     * Ahead of any ACPI table parsing make sure we have control structures
-     * for PCI segment 0.
+     * Initialize PCI (create segment 0, setup MMCFG access) ahead of IOMMU
+     * setup, as it requires access to the PCI config space.
      */
-    if ( pci_add_segment(0) )
-        panic("Could not initialize PCI segment 0\n");
+    pci_setup();
 
     /*
      * IOMMU-related ACPI table parsing has to happen before APIC probing, for
diff --git a/xen/arch/x86/x86_64/mmconfig-shared.c b/xen/arch/x86/x86_64/mmconfig-shared.c
index f1a3d42c5b21..fbe2676f8636 100644
--- a/xen/arch/x86/x86_64/mmconfig-shared.c
+++ b/xen/arch/x86/x86_64/mmconfig-shared.c
@@ -402,6 +402,9 @@ void __init acpi_mmcfg_init(void)
 {
     bool valid = true;
 
+    if ( acpi_disabled )
+        return;
+
     /* MMCONFIG disabled */
     if ((pci_probe & PCI_PROBE_MMCONF) == 0)
         return;
-- 
2.49.0



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
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	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
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	virtualization@lists.linux.dev,
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	xen-devel@lists.xenproject.org
Subject: [PATCH v4 00/16] dma-mapping: migrate to physical address-based API
Date: Tue, 19 Aug 2025 20:36:44 +0300
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Changelog:
v4:
 * Fixed kbuild error with mismatch in kmsan function declaration due to
   rebase error.
v3: https://lore.kernel.org/all/cover.1755193625.git.leon@kernel.org
 * Fixed typo in "cacheable" word
 * Simplified kmsan patch a lot to be simple argument refactoring
v2: https://lore.kernel.org/all/cover.1755153054.git.leon@kernel.org
 * Used commit messages and cover letter from Jason
 * Moved setting IOMMU_MMIO flag to dma_info_to_prot function
 * Micro-optimized the code
 * Rebased code on v6.17-rc1
v1: https://lore.kernel.org/all/cover.1754292567.git.leon@kernel.org
 * Added new DMA_ATTR_MMIO attribute to indicate
   PCI_P2PDMA_MAP_THRU_HOST_BRIDGE path.
 * Rewrote dma_map_* functions to use thus new attribute
v0: https://lore.kernel.org/all/cover.1750854543.git.leon@kernel.org/
------------------------------------------------------------------------

This series refactors the DMA mapping to use physical addresses
as the primary interface instead of page+offset parameters. This
change aligns the DMA API with the underlying hardware reality where
DMA operations work with physical addresses, not page structures.

The series maintains export symbol backward compatibility by keeping
the old page-based API as wrapper functions around the new physical
address-based implementations.

This series refactors the DMA mapping API to provide a phys_addr_t
based, and struct-page free, external API that can handle all the
mapping cases we want in modern systems:

 - struct page based cachable DRAM
 - struct page MEMORY_DEVICE_PCI_P2PDMA PCI peer to peer non-cachable
   MMIO
 - struct page-less PCI peer to peer non-cachable MMIO
 - struct page-less "resource" MMIO

Overall this gets much closer to Matthew's long term wish for
struct-pageless IO to cachable DRAM. The remaining primary work would
be in the mm side to allow kmap_local_pfn()/phys_to_virt() to work on
phys_addr_t without a struct page.

The general design is to remove struct page usage entirely from the
DMA API inner layers. For flows that need to have a KVA for the
physical address they can use kmap_local_pfn() or phys_to_virt(). This
isolates the struct page requirements to MM code only. Long term all
removals of struct page usage are supporting Matthew's memdesc
project which seeks to substantially transform how struct page works.

Instead make the DMA API internals work on phys_addr_t. Internally
there are still dedicated 'page' and 'resource' flows, except they are
now distinguished by a new DMA_ATTR_MMIO instead of by callchain. Both
flows use the same phys_addr_t.

When DMA_ATTR_MMIO is specified things work similar to the existing
'resource' flow. kmap_local_pfn(), phys_to_virt(), phys_to_page(),
pfn_valid(), etc are never called on the phys_addr_t. This requires
rejecting any configuration that would need swiotlb. CPU cache
flushing is not required, and avoided, as ATTR_MMIO also indicates the
address have no cachable mappings. This effectively removes any
DMA API side requirement to have struct page when DMA_ATTR_MMIO is
used.

In the !DMA_ATTR_MMIO mode things work similarly to the 'page' flow,
except on the common path of no cache flush, no swiotlb it never
touches a struct page. When cache flushing or swiotlb copying
kmap_local_pfn()/phys_to_virt() are used to get a KVA for CPU
usage. This was already the case on the unmap side, now the map side
is symmetric.

Callers are adjusted to set DMA_ATTR_MMIO. Existing 'resource' users
must set it. The existing struct page based MEMORY_DEVICE_PCI_P2PDMA
path must also set it. This corrects some existing bugs where iommu
mappings for P2P MMIO were improperly marked IOMMU_CACHE.

Since ATTR_MMIO is made to work with all the existing DMA map entry
points, particularly dma_iova_link(), this finally allows a way to use
the new DMA API to map PCI P2P MMIO without creating struct page. The
VFIO DMABUF series demonstrates how this works. This is intended to
replace the incorrect driver use of dma_map_resource() on PCI BAR
addresses.

This series does the core code and modern flows. A followup series
will give the same treatment to the legacy dma_ops implementation.

Thanks

Leon Romanovsky (16):
  dma-mapping: introduce new DMA attribute to indicate MMIO memory
  iommu/dma: implement DMA_ATTR_MMIO for dma_iova_link().
  dma-debug: refactor to use physical addresses for page mapping
  dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys
  iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys
  iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory
  dma-mapping: convert dma_direct_*map_page to be phys_addr_t based
  kmsan: convert kmsan_handle_dma to use physical addresses
  dma-mapping: handle MMIO flow in dma_map|unmap_page
  xen: swiotlb: Open code map_resource callback
  dma-mapping: export new dma_*map_phys() interface
  mm/hmm: migrate to physical address-based DMA mapping API
  mm/hmm: properly take MMIO path
  block-dma: migrate to dma_map_phys instead of map_page
  block-dma: properly take MMIO path
  nvme-pci: unmap MMIO pages with appropriate interface

 Documentation/core-api/dma-api.rst        |   4 +-
 Documentation/core-api/dma-attributes.rst |  18 ++++
 arch/powerpc/kernel/dma-iommu.c           |   4 +-
 block/blk-mq-dma.c                        |  15 ++-
 drivers/iommu/dma-iommu.c                 |  61 +++++------
 drivers/nvme/host/pci.c                   |  18 +++-
 drivers/virtio/virtio_ring.c              |   4 +-
 drivers/xen/swiotlb-xen.c                 |  21 +++-
 include/linux/blk-mq-dma.h                |   6 +-
 include/linux/blk_types.h                 |   2 +
 include/linux/dma-direct.h                |   2 -
 include/linux/dma-map-ops.h               |   8 +-
 include/linux/dma-mapping.h               |  33 ++++++
 include/linux/iommu-dma.h                 |  11 +-
 include/linux/kmsan.h                     |   9 +-
 include/trace/events/dma.h                |   9 +-
 kernel/dma/debug.c                        |  71 ++++---------
 kernel/dma/debug.h                        |  37 ++-----
 kernel/dma/direct.c                       |  22 +---
 kernel/dma/direct.h                       |  52 ++++++----
 kernel/dma/mapping.c                      | 117 +++++++++++++---------
 kernel/dma/ops_helpers.c                  |   6 +-
 mm/hmm.c                                  |  19 ++--
 mm/kmsan/hooks.c                          |   5 +-
 rust/kernel/dma.rs                        |   3 +
 tools/virtio/linux/kmsan.h                |   2 +-
 26 files changed, 305 insertions(+), 254 deletions(-)

-- 
2.50.1



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To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
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	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v4 03/16] dma-debug: refactor to use physical addresses for page mapping
Date: Tue, 19 Aug 2025 20:36:47 +0300
Message-ID: <478d5b7135008b3c82f100faa9d3830839fc6562.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

Convert the DMA debug infrastructure from page-based to physical address-based
mapping as a preparation to rely on physical address for DMA mapping routines.

The refactoring renames debug_dma_map_page() to debug_dma_map_phys() and
changes its signature to accept a phys_addr_t parameter instead of struct page
and offset. Similarly, debug_dma_unmap_page() becomes debug_dma_unmap_phys().
A new dma_debug_phy type is introduced to distinguish physical address mappings
from other debug entry types. All callers throughout the codebase are updated
to pass physical addresses directly, eliminating the need for page-to-physical
conversion in the debug layer.

This refactoring eliminates the need to convert between page pointers and
physical addresses in the debug layer, making the code more efficient and
consistent with the DMA mapping API's physical address focus.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 Documentation/core-api/dma-api.rst |  4 ++--
 kernel/dma/debug.c                 | 28 +++++++++++++++++-----------
 kernel/dma/debug.h                 | 16 +++++++---------
 kernel/dma/mapping.c               | 15 ++++++++-------
 4 files changed, 34 insertions(+), 29 deletions(-)

diff --git a/Documentation/core-api/dma-api.rst b/Documentation/core-api/dma-api.rst
index 3087bea715ed..ca75b3541679 100644
--- a/Documentation/core-api/dma-api.rst
+++ b/Documentation/core-api/dma-api.rst
@@ -761,7 +761,7 @@ example warning message may look like this::
 	[] find_busiest_group+0x207/0x8a0
 	[] _spin_lock_irqsave+0x1f/0x50
 	[] check_unmap+0x203/0x490
-	[] debug_dma_unmap_page+0x49/0x50
+	[] debug_dma_unmap_phys+0x49/0x50
 	[] nv_tx_done_optimized+0xc6/0x2c0
 	[] nv_nic_irq_optimized+0x73/0x2b0
 	[] handle_IRQ_event+0x34/0x70
@@ -855,7 +855,7 @@ that a driver may be leaking mappings.
 dma-debug interface debug_dma_mapping_error() to debug drivers that fail
 to check DMA mapping errors on addresses returned by dma_map_single() and
 dma_map_page() interfaces. This interface clears a flag set by
-debug_dma_map_page() to indicate that dma_mapping_error() has been called by
+debug_dma_map_phys() to indicate that dma_mapping_error() has been called by
 the driver. When driver does unmap, debug_dma_unmap() checks the flag and if
 this flag is still set, prints warning message that includes call trace that
 leads up to the unmap. This interface can be called from dma_mapping_error()
diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c
index e43c6de2bce4..da6734e3a4ce 100644
--- a/kernel/dma/debug.c
+++ b/kernel/dma/debug.c
@@ -39,6 +39,7 @@ enum {
 	dma_debug_sg,
 	dma_debug_coherent,
 	dma_debug_resource,
+	dma_debug_phy,
 };
 
 enum map_err_types {
@@ -141,6 +142,7 @@ static const char *type2name[] = {
 	[dma_debug_sg] = "scatter-gather",
 	[dma_debug_coherent] = "coherent",
 	[dma_debug_resource] = "resource",
+	[dma_debug_phy] = "phy",
 };
 
 static const char *dir2name[] = {
@@ -1201,9 +1203,8 @@ void debug_dma_map_single(struct device *dev, const void *addr,
 }
 EXPORT_SYMBOL(debug_dma_map_single);
 
-void debug_dma_map_page(struct device *dev, struct page *page, size_t offset,
-			size_t size, int direction, dma_addr_t dma_addr,
-			unsigned long attrs)
+void debug_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		int direction, dma_addr_t dma_addr, unsigned long attrs)
 {
 	struct dma_debug_entry *entry;
 
@@ -1218,19 +1219,24 @@ void debug_dma_map_page(struct device *dev, struct page *page, size_t offset,
 		return;
 
 	entry->dev       = dev;
-	entry->type      = dma_debug_single;
-	entry->paddr	 = page_to_phys(page) + offset;
+	entry->type      = dma_debug_phy;
+	entry->paddr	 = phys;
 	entry->dev_addr  = dma_addr;
 	entry->size      = size;
 	entry->direction = direction;
 	entry->map_err_type = MAP_ERR_NOT_CHECKED;
 
-	check_for_stack(dev, page, offset);
+	if (!(attrs & DMA_ATTR_MMIO)) {
+		struct page *page = phys_to_page(phys);
+		size_t offset = offset_in_page(page);
 
-	if (!PageHighMem(page)) {
-		void *addr = page_address(page) + offset;
+		check_for_stack(dev, page, offset);
 
-		check_for_illegal_area(dev, addr, size);
+		if (!PageHighMem(page)) {
+			void *addr = page_address(page) + offset;
+
+			check_for_illegal_area(dev, addr, size);
+		}
 	}
 
 	add_dma_entry(entry, attrs);
@@ -1274,11 +1280,11 @@ void debug_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 }
 EXPORT_SYMBOL(debug_dma_mapping_error);
 
-void debug_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
+void debug_dma_unmap_phys(struct device *dev, dma_addr_t dma_addr,
 			  size_t size, int direction)
 {
 	struct dma_debug_entry ref = {
-		.type           = dma_debug_single,
+		.type           = dma_debug_phy,
 		.dev            = dev,
 		.dev_addr       = dma_addr,
 		.size           = size,
diff --git a/kernel/dma/debug.h b/kernel/dma/debug.h
index f525197d3cae..76adb42bffd5 100644
--- a/kernel/dma/debug.h
+++ b/kernel/dma/debug.h
@@ -9,12 +9,11 @@
 #define _KERNEL_DMA_DEBUG_H
 
 #ifdef CONFIG_DMA_API_DEBUG
-extern void debug_dma_map_page(struct device *dev, struct page *page,
-			       size_t offset, size_t size,
-			       int direction, dma_addr_t dma_addr,
+extern void debug_dma_map_phys(struct device *dev, phys_addr_t phys,
+			       size_t size, int direction, dma_addr_t dma_addr,
 			       unsigned long attrs);
 
-extern void debug_dma_unmap_page(struct device *dev, dma_addr_t addr,
+extern void debug_dma_unmap_phys(struct device *dev, dma_addr_t addr,
 				 size_t size, int direction);
 
 extern void debug_dma_map_sg(struct device *dev, struct scatterlist *sg,
@@ -55,14 +54,13 @@ extern void debug_dma_sync_sg_for_device(struct device *dev,
 					 struct scatterlist *sg,
 					 int nelems, int direction);
 #else /* CONFIG_DMA_API_DEBUG */
-static inline void debug_dma_map_page(struct device *dev, struct page *page,
-				      size_t offset, size_t size,
-				      int direction, dma_addr_t dma_addr,
-				      unsigned long attrs)
+static inline void debug_dma_map_phys(struct device *dev, phys_addr_t phys,
+				      size_t size, int direction,
+				      dma_addr_t dma_addr, unsigned long attrs)
 {
 }
 
-static inline void debug_dma_unmap_page(struct device *dev, dma_addr_t addr,
+static inline void debug_dma_unmap_phys(struct device *dev, dma_addr_t addr,
 					size_t size, int direction)
 {
 }
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 107e4a4d251d..4c1dfbabb8ae 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -157,6 +157,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
+	phys_addr_t phys = page_to_phys(page) + offset;
 	dma_addr_t addr;
 
 	BUG_ON(!valid_dma_direction(dir));
@@ -165,16 +166,15 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		return DMA_MAPPING_ERROR;
 
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_map_page_direct(dev, page_to_phys(page) + offset + size))
+	    arch_dma_map_page_direct(dev, phys + size))
 		addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		addr = iommu_dma_map_page(dev, page, offset, size, dir, attrs);
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
 	kmsan_handle_dma(page, offset, size, dir);
-	trace_dma_map_page(dev, page_to_phys(page) + offset, addr, size, dir,
-			   attrs);
-	debug_dma_map_page(dev, page, offset, size, dir, addr, attrs);
+	trace_dma_map_page(dev, phys, addr, size, dir, attrs);
+	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
 	return addr;
 }
@@ -194,7 +194,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 	else
 		ops->unmap_page(dev, addr, size, dir, attrs);
 	trace_dma_unmap_page(dev, addr, size, dir, attrs);
-	debug_dma_unmap_page(dev, addr, size, dir);
+	debug_dma_unmap_phys(dev, addr, size, dir);
 }
 EXPORT_SYMBOL(dma_unmap_page_attrs);
 
@@ -712,7 +712,8 @@ struct page *dma_alloc_pages(struct device *dev, size_t size,
 	if (page) {
 		trace_dma_alloc_pages(dev, page_to_virt(page), *dma_handle,
 				      size, dir, gfp, 0);
-		debug_dma_map_page(dev, page, 0, size, dir, *dma_handle, 0);
+		debug_dma_map_phys(dev, page_to_phys(page), size, dir,
+				   *dma_handle, 0);
 	} else {
 		trace_dma_alloc_pages(dev, NULL, 0, size, dir, gfp, 0);
 	}
@@ -738,7 +739,7 @@ void dma_free_pages(struct device *dev, size_t size, struct page *page,
 		dma_addr_t dma_handle, enum dma_data_direction dir)
 {
 	trace_dma_free_pages(dev, page_to_virt(page), dma_handle, size, dir, 0);
-	debug_dma_unmap_page(dev, dma_handle, size, dir);
+	debug_dma_unmap_phys(dev, dma_handle, size, dir);
 	__dma_free_pages(dev, size, page, dma_handle, dir);
 }
 EXPORT_SYMBOL_GPL(dma_free_pages);
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v4 01/16] dma-mapping: introduce new DMA attribute to indicate MMIO memory
Date: Tue, 19 Aug 2025 20:36:45 +0300
Message-ID: <08e044a00a872932e106f7e27449a8eab2690dbc.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

This patch introduces the DMA_ATTR_MMIO attribute to mark DMA buffers
that reside in memory-mapped I/O (MMIO) regions, such as device BARs
exposed through the host bridge, which are accessible for peer-to-peer
(P2P) DMA.

This attribute is especially useful for exporting device memory to other
devices for DMA without CPU involvement, and avoids unnecessary or
potentially detrimental CPU cache maintenance calls.

DMA_ATTR_MMIO is supposed to provide dma_map_resource() functionality
without need to call to special function and perform branching by
the callers.

Signed-off-by: Leon Romanovsky 
---
 Documentation/core-api/dma-attributes.rst | 18 ++++++++++++++++++
 include/linux/dma-mapping.h               | 20 ++++++++++++++++++++
 include/trace/events/dma.h                |  3 ++-
 rust/kernel/dma.rs                        |  3 +++
 4 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst
index 1887d92e8e92..0bdc2be65e57 100644
--- a/Documentation/core-api/dma-attributes.rst
+++ b/Documentation/core-api/dma-attributes.rst
@@ -130,3 +130,21 @@ accesses to DMA buffers in both privileged "supervisor" and unprivileged
 subsystem that the buffer is fully accessible at the elevated privilege
 level (and ideally inaccessible or at least read-only at the
 lesser-privileged levels).
+
+DMA_ATTR_MMIO
+-------------
+
+This attribute indicates the physical address is not normal system
+memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page()
+functions, it may not be cacheable, and access using CPU load/store
+instructions may not be allowed.
+
+Usually this will be used to describe MMIO addresses, or other non-cacheable
+register addresses. When DMA mapping this sort of address we call
+the operation Peer to Peer as a one device is DMA'ing to another device.
+For PCI devices the p2pdma APIs must be used to determine if
+DMA_ATTR_MMIO is appropriate.
+
+For architectures that require cache flushing for DMA coherence
+DMA_ATTR_MMIO will not perform any cache flushing. The address
+provided must never be mapped cacheable into the CPU.
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 55c03e5fe8cb..4254fd9bdf5d 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -58,6 +58,26 @@
  */
 #define DMA_ATTR_PRIVILEGED		(1UL << 9)
 
+/*
+ * DMA_ATTR_MMIO - Indicates memory-mapped I/O (MMIO) region for DMA mapping
+ *
+ * This attribute indicates the physical address is not normal system
+ * memory. It may not be used with kmap*()/phys_to_virt()/phys_to_page()
+ * functions, it may not be cacheable, and access using CPU load/store
+ * instructions may not be allowed.
+ *
+ * Usually this will be used to describe MMIO addresses, or other non-cacheable
+ * register addresses. When DMA mapping this sort of address we call
+ * the operation Peer to Peer as a one device is DMA'ing to another device.
+ * For PCI devices the p2pdma APIs must be used to determine if DMA_ATTR_MMIO
+ * is appropriate.
+ *
+ * For architectures that require cache flushing for DMA coherence
+ * DMA_ATTR_MMIO will not perform any cache flushing. The address
+ * provided must never be mapped cacheable into the CPU.
+ */
+#define DMA_ATTR_MMIO		(1UL << 10)
+
 /*
  * A dma_addr_t can hold any valid DMA or bus address for the platform.  It can
  * be given to a device to use as a DMA source or target.  It is specific to a
diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h
index d8ddc27b6a7c..ee90d6f1dcf3 100644
--- a/include/trace/events/dma.h
+++ b/include/trace/events/dma.h
@@ -31,7 +31,8 @@ TRACE_DEFINE_ENUM(DMA_NONE);
 		{ DMA_ATTR_FORCE_CONTIGUOUS, "FORCE_CONTIGUOUS" }, \
 		{ DMA_ATTR_ALLOC_SINGLE_PAGES, "ALLOC_SINGLE_PAGES" }, \
 		{ DMA_ATTR_NO_WARN, "NO_WARN" }, \
-		{ DMA_ATTR_PRIVILEGED, "PRIVILEGED" })
+		{ DMA_ATTR_PRIVILEGED, "PRIVILEGED" }, \
+		{ DMA_ATTR_MMIO, "MMIO" })
 
 DECLARE_EVENT_CLASS(dma_map,
 	TP_PROTO(struct device *dev, phys_addr_t phys_addr, dma_addr_t dma_addr,
diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs
index 2bc8ab51ec28..61d9eed7a786 100644
--- a/rust/kernel/dma.rs
+++ b/rust/kernel/dma.rs
@@ -242,6 +242,9 @@ pub mod attrs {
     /// Indicates that the buffer is fully accessible at an elevated privilege level (and
     /// ideally inaccessible or at least read-only at lesser-privileged levels).
     pub const DMA_ATTR_PRIVILEGED: Attrs = Attrs(bindings::DMA_ATTR_PRIVILEGED);
+
+    /// Indicates that the buffer is MMIO memory.
+    pub const DMA_ATTR_MMIO: Attrs = Attrs(bindings::DMA_ATTR_MMIO);
 }
 
 /// An abstraction of the `dma_alloc_coherent` API.
-- 
2.50.1



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Subject: [PATCH v4 02/16] iommu/dma: implement DMA_ATTR_MMIO for dma_iova_link().
Date: Tue, 19 Aug 2025 20:36:46 +0300
Message-ID: <62d9a6c3ca03037631f6d0640ebec5fbac41d547.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

This will replace the hacky use of DMA_ATTR_SKIP_CPU_SYNC to avoid
touching the possibly non-KVA MMIO memory.

Also correct the incorrect caching attribute for the IOMMU, MMIO
memory should not be cachable inside the IOMMU mapping or it can
possibly create system problems. Set IOMMU_MMIO for DMA_ATTR_MMIO.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index ea2ef53bd4fe..e1185ba73e23 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -724,7 +724,12 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, struct device *dev
 static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
 		     unsigned long attrs)
 {
-	int prot = coherent ? IOMMU_CACHE : 0;
+	int prot;
+
+	if (attrs & DMA_ATTR_MMIO)
+		prot = IOMMU_MMIO;
+	else
+		prot = coherent ? IOMMU_CACHE : 0;
 
 	if (attrs & DMA_ATTR_PRIVILEGED)
 		prot |= IOMMU_PRIV;
@@ -1838,12 +1843,13 @@ static int __dma_iova_link(struct device *dev, dma_addr_t addr,
 		unsigned long attrs)
 {
 	bool coherent = dev_is_dma_coherent(dev);
+	int prot = dma_info_to_prot(dir, coherent, attrs);
 
-	if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+	if (!coherent && !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
 		arch_sync_dma_for_device(phys, size, dir);
 
 	return iommu_map_nosync(iommu_get_dma_domain(dev), addr, phys, size,
-			dma_info_to_prot(dir, coherent, attrs), GFP_ATOMIC);
+			prot, GFP_ATOMIC);
 }
 
 static int iommu_dma_iova_bounce_and_link(struct device *dev, dma_addr_t addr,
@@ -1949,9 +1955,13 @@ int dma_iova_link(struct device *dev, struct dma_iova_state *state,
 		return -EIO;
 
 	if (dev_use_swiotlb(dev, size, dir) &&
-	    iova_unaligned(iovad, phys, size))
+	    iova_unaligned(iovad, phys, size)) {
+		if (attrs & DMA_ATTR_MMIO)
+			return -EPERM;
+
 		return iommu_dma_iova_link_swiotlb(dev, state, phys, offset,
 				size, dir, attrs);
+	}
 
 	return __dma_iova_link(dev, state->addr + offset - iova_start_pad,
 			phys - iova_start_pad,
-- 
2.50.1



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Subject: [PATCH v4 04/16] dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys
Date: Tue, 19 Aug 2025 20:36:48 +0300
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From: Leon Romanovsky 

As a preparation for following map_page -> map_phys API conversion,
let's rename trace_dma_*map_page() to be trace_dma_*map_phys().

Signed-off-by: Leon Romanovsky 
---
 include/trace/events/dma.h | 4 ++--
 kernel/dma/mapping.c       | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h
index ee90d6f1dcf3..84416c7d6bfa 100644
--- a/include/trace/events/dma.h
+++ b/include/trace/events/dma.h
@@ -72,7 +72,7 @@ DEFINE_EVENT(dma_map, name, \
 		 size_t size, enum dma_data_direction dir, unsigned long attrs), \
 	TP_ARGS(dev, phys_addr, dma_addr, size, dir, attrs))
 
-DEFINE_MAP_EVENT(dma_map_page);
+DEFINE_MAP_EVENT(dma_map_phys);
 DEFINE_MAP_EVENT(dma_map_resource);
 
 DECLARE_EVENT_CLASS(dma_unmap,
@@ -110,7 +110,7 @@ DEFINE_EVENT(dma_unmap, name, \
 		 enum dma_data_direction dir, unsigned long attrs), \
 	TP_ARGS(dev, addr, size, dir, attrs))
 
-DEFINE_UNMAP_EVENT(dma_unmap_page);
+DEFINE_UNMAP_EVENT(dma_unmap_phys);
 DEFINE_UNMAP_EVENT(dma_unmap_resource);
 
 DECLARE_EVENT_CLASS(dma_alloc_class,
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 4c1dfbabb8ae..fe1f0da6dc50 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -173,7 +173,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
 	kmsan_handle_dma(page, offset, size, dir);
-	trace_dma_map_page(dev, phys, addr, size, dir, attrs);
+	trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
 	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
 	return addr;
@@ -193,7 +193,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 		iommu_dma_unmap_page(dev, addr, size, dir, attrs);
 	else
 		ops->unmap_page(dev, addr, size, dir, attrs);
-	trace_dma_unmap_page(dev, addr, size, dir, attrs);
+	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
 	debug_dma_unmap_phys(dev, addr, size, dir);
 }
 EXPORT_SYMBOL(dma_unmap_page_attrs);
-- 
2.50.1



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	Christoph Hellwig ,
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Subject: [PATCH v4 06/16] iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory
Date: Tue, 19 Aug 2025 20:36:50 +0300
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From: Leon Romanovsky 

Combine iommu_dma_*map_phys with iommu_dma_*map_resource interfaces in
order to allow single phys_addr_t flow.

In the following patches, the iommu_dma_map_resource() will be removed
in favour of iommu_dma_map_phys(..., attrs | DMA_ATTR_MMIO) flow.

Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index aea119f32f96..6804aaf034a1 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -1211,16 +1211,19 @@ dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
 	 */
 	if (dev_use_swiotlb(dev, size, dir) &&
 	    iova_unaligned(iovad, phys, size)) {
+		if (attrs & DMA_ATTR_MMIO)
+			return DMA_MAPPING_ERROR;
+
 		phys = iommu_dma_map_swiotlb(dev, phys, size, dir, attrs);
 		if (phys == (phys_addr_t)DMA_MAPPING_ERROR)
 			return DMA_MAPPING_ERROR;
 	}
 
-	if (!coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+	if (!coherent && !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
 		arch_sync_dma_for_device(phys, size, dir);
 
 	iova = __iommu_dma_map(dev, phys, size, prot, dma_mask);
-	if (iova == DMA_MAPPING_ERROR)
+	if (iova == DMA_MAPPING_ERROR && !(attrs & DMA_ATTR_MMIO))
 		swiotlb_tbl_unmap_single(dev, phys, size, dir, attrs);
 	return iova;
 }
@@ -1228,10 +1231,14 @@ dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
 void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
-	struct iommu_domain *domain = iommu_get_dma_domain(dev);
 	phys_addr_t phys;
 
-	phys = iommu_iova_to_phys(domain, dma_handle);
+	if (attrs & DMA_ATTR_MMIO) {
+		__iommu_dma_unmap(dev, dma_handle, size);
+		return;
+	}
+
+	phys = iommu_iova_to_phys(iommu_get_dma_domain(dev), dma_handle);
 	if (WARN_ON(!phys))
 		return;
 
-- 
2.50.1



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Date: Tue, 19 Aug 2025 13:40:26 -0400
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Subject: Re: [PATCH v2 1/2] Arm: drop assertion from page_is_ram_type()
To: Jan Beulich , "xen-devel@lists.xenproject.org"
	
CC: Julien Grall , Stefano Stabellini
	, Volodymyr Babchuk ,
	Bertrand Marquis , Michal Orzel
	, Oleksii Kurochko , Andrew
 Cooper , Anthony PERARD
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On 2025-08-18 03:55, Jan Beulich wrote:
> Its uses in offline_page() and query_page_offline() make it reachable on
> Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
> code added. It being reachable was even mentioned in the commit
> introducing it, claiming it "clearly shouldn't be called on ARM just
> yet".
> 
> However, dropping the assertion from a function of this name is deemed
> problematic. Rename it to better reflect its sole purpose outside of
> x86-specific code.
> 
> Fixes: 214c4cd94a80 ("xen: arm: stub page_is_ram_type")
> Signed-off-by: Jan Beulich 

Reviewed-by: Jason Andryuk 


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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
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Subject: [PATCH v4 07/16] dma-mapping: convert dma_direct_*map_page to be phys_addr_t based
Date: Tue, 19 Aug 2025 20:36:51 +0300
Message-ID: <3faa9c978e243a904ffe01496148c4563dc9274e.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

Convert the DMA direct mapping functions to accept physical addresses
directly instead of page+offset parameters. The functions were already
operating on physical addresses internally, so this change eliminates
the redundant page-to-physical conversion at the API boundary.

The functions dma_direct_map_page() and dma_direct_unmap_page() are
renamed to dma_direct_map_phys() and dma_direct_unmap_phys() respectively,
with their calling convention changed from (struct page *page,
unsigned long offset) to (phys_addr_t phys).

Architecture-specific functions arch_dma_map_page_direct() and
arch_dma_unmap_page_direct() are similarly renamed to
arch_dma_map_phys_direct() and arch_dma_unmap_phys_direct().

The is_pci_p2pdma_page() checks are replaced with DMA_ATTR_MMIO checks
to allow integration with dma_direct_map_resource and dma_direct_map_phys()
is extended to support MMIO path either.

Signed-off-by: Leon Romanovsky 
---
 arch/powerpc/kernel/dma-iommu.c |  4 +--
 include/linux/dma-map-ops.h     |  8 ++---
 kernel/dma/direct.c             |  6 ++--
 kernel/dma/direct.h             | 52 +++++++++++++++++++++------------
 kernel/dma/mapping.c            |  8 ++---
 5 files changed, 46 insertions(+), 32 deletions(-)

diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index 4d64a5db50f3..0359ab72cd3b 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -14,7 +14,7 @@
 #define can_map_direct(dev, addr) \
 	((dev)->bus_dma_limit >= phys_to_dma((dev), (addr)))
 
-bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr)
+bool arch_dma_map_phys_direct(struct device *dev, phys_addr_t addr)
 {
 	if (likely(!dev->bus_dma_limit))
 		return false;
@@ -24,7 +24,7 @@ bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr)
 
 #define is_direct_handle(dev, h) ((h) >= (dev)->archdata.dma_offset)
 
-bool arch_dma_unmap_page_direct(struct device *dev, dma_addr_t dma_handle)
+bool arch_dma_unmap_phys_direct(struct device *dev, dma_addr_t dma_handle)
 {
 	if (likely(!dev->bus_dma_limit))
 		return false;
diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h
index f48e5fb88bd5..71f5b3025415 100644
--- a/include/linux/dma-map-ops.h
+++ b/include/linux/dma-map-ops.h
@@ -392,15 +392,15 @@ void *arch_dma_set_uncached(void *addr, size_t size);
 void arch_dma_clear_uncached(void *addr, size_t size);
 
 #ifdef CONFIG_ARCH_HAS_DMA_MAP_DIRECT
-bool arch_dma_map_page_direct(struct device *dev, phys_addr_t addr);
-bool arch_dma_unmap_page_direct(struct device *dev, dma_addr_t dma_handle);
+bool arch_dma_map_phys_direct(struct device *dev, phys_addr_t addr);
+bool arch_dma_unmap_phys_direct(struct device *dev, dma_addr_t dma_handle);
 bool arch_dma_map_sg_direct(struct device *dev, struct scatterlist *sg,
 		int nents);
 bool arch_dma_unmap_sg_direct(struct device *dev, struct scatterlist *sg,
 		int nents);
 #else
-#define arch_dma_map_page_direct(d, a)		(false)
-#define arch_dma_unmap_page_direct(d, a)	(false)
+#define arch_dma_map_phys_direct(d, a)		(false)
+#define arch_dma_unmap_phys_direct(d, a)	(false)
 #define arch_dma_map_sg_direct(d, s, n)		(false)
 #define arch_dma_unmap_sg_direct(d, s, n)	(false)
 #endif
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 24c359d9c879..fa75e3070073 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -453,7 +453,7 @@ void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
 		if (sg_dma_is_bus_address(sg))
 			sg_dma_unmark_bus_address(sg);
 		else
-			dma_direct_unmap_page(dev, sg->dma_address,
+			dma_direct_unmap_phys(dev, sg->dma_address,
 					      sg_dma_len(sg), dir, attrs);
 	}
 }
@@ -476,8 +476,8 @@ int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
 			 */
 			break;
 		case PCI_P2PDMA_MAP_NONE:
-			sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
-					sg->offset, sg->length, dir, attrs);
+			sg->dma_address = dma_direct_map_phys(dev, sg_phys(sg),
+					sg->length, dir, attrs);
 			if (sg->dma_address == DMA_MAPPING_ERROR) {
 				ret = -EIO;
 				goto out_unmap;
diff --git a/kernel/dma/direct.h b/kernel/dma/direct.h
index d2c0b7e632fc..92dbadcd3b2f 100644
--- a/kernel/dma/direct.h
+++ b/kernel/dma/direct.h
@@ -80,42 +80,56 @@ static inline void dma_direct_sync_single_for_cpu(struct device *dev,
 		arch_dma_mark_clean(paddr, size);
 }
 
-static inline dma_addr_t dma_direct_map_page(struct device *dev,
-		struct page *page, unsigned long offset, size_t size,
-		enum dma_data_direction dir, unsigned long attrs)
+static inline dma_addr_t dma_direct_map_phys(struct device *dev,
+		phys_addr_t phys, size_t size, enum dma_data_direction dir,
+		unsigned long attrs)
 {
-	phys_addr_t phys = page_to_phys(page) + offset;
-	dma_addr_t dma_addr = phys_to_dma(dev, phys);
+	dma_addr_t dma_addr;
+	bool capable;
 
 	if (is_swiotlb_force_bounce(dev)) {
-		if (is_pci_p2pdma_page(page))
-			return DMA_MAPPING_ERROR;
+		if (attrs & DMA_ATTR_MMIO)
+			goto err_overflow;
+
 		return swiotlb_map(dev, phys, size, dir, attrs);
 	}
 
-	if (unlikely(!dma_capable(dev, dma_addr, size, true)) ||
-	    dma_kmalloc_needs_bounce(dev, size, dir)) {
-		if (is_pci_p2pdma_page(page))
-			return DMA_MAPPING_ERROR;
-		if (is_swiotlb_active(dev))
+	if (attrs & DMA_ATTR_MMIO)
+		dma_addr = phys;
+	else
+		dma_addr = phys_to_dma(dev, phys);
+
+	capable = dma_capable(dev, dma_addr, size, !(attrs & DMA_ATTR_MMIO));
+	if (unlikely(!capable) || dma_kmalloc_needs_bounce(dev, size, dir)) {
+		if (is_swiotlb_active(dev) && !(attrs & DMA_ATTR_MMIO))
 			return swiotlb_map(dev, phys, size, dir, attrs);
 
-		dev_WARN_ONCE(dev, 1,
-			     "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
-			     &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
-		return DMA_MAPPING_ERROR;
+		goto err_overflow;
 	}
 
-	if (!dev_is_dma_coherent(dev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+	if (!dev_is_dma_coherent(dev) &&
+	    !(attrs & (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_MMIO)))
 		arch_sync_dma_for_device(phys, size, dir);
 	return dma_addr;
+
+err_overflow:
+	dev_WARN_ONCE(
+		dev, 1,
+		"DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
+		&dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
+	return DMA_MAPPING_ERROR;
 }
 
-static inline void dma_direct_unmap_page(struct device *dev, dma_addr_t addr,
+static inline void dma_direct_unmap_phys(struct device *dev, dma_addr_t addr,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
-	phys_addr_t phys = dma_to_phys(dev, addr);
+	phys_addr_t phys;
+
+	if (attrs & DMA_ATTR_MMIO)
+		/* nothing to do: uncached and no swiotlb */
+		return;
 
+	phys = dma_to_phys(dev, addr);
 	if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
 		dma_direct_sync_single_for_cpu(dev, addr, size, dir);
 
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 58482536db9b..80481a873340 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -166,8 +166,8 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		return DMA_MAPPING_ERROR;
 
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_map_page_direct(dev, phys + size))
-		addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
+	    arch_dma_map_phys_direct(dev, phys + size))
+		addr = dma_direct_map_phys(dev, phys, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
 	else
@@ -187,8 +187,8 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 
 	BUG_ON(!valid_dma_direction(dir));
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_unmap_page_direct(dev, addr + size))
-		dma_direct_unmap_page(dev, addr, size, dir, attrs);
+	    arch_dma_unmap_phys_direct(dev, addr + size))
+		dma_direct_unmap_phys(dev, addr, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
 	else
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
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Subject: [PATCH v4 09/16] dma-mapping: handle MMIO flow in dma_map|unmap_page
Date: Tue, 19 Aug 2025 20:36:53 +0300
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From: Leon Romanovsky 

Extend base DMA page API to handle MMIO flow and follow
existing dma_map_resource() implementation to rely on dma_map_direct()
only to take DMA direct path.

Signed-off-by: Leon Romanovsky 
---
 kernel/dma/mapping.c | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 891e1fc3e582..fdabfdaeff1d 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -158,6 +158,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
 	phys_addr_t phys = page_to_phys(page) + offset;
+	bool is_mmio = attrs & DMA_ATTR_MMIO;
 	dma_addr_t addr;
 
 	BUG_ON(!valid_dma_direction(dir));
@@ -166,14 +167,25 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		return DMA_MAPPING_ERROR;
 
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_map_phys_direct(dev, phys + size))
+	    (!is_mmio && arch_dma_map_phys_direct(dev, phys + size)))
 		addr = dma_direct_map_phys(dev, phys, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
-	else
+	else if (is_mmio) {
+		if (!ops->map_resource)
+			return DMA_MAPPING_ERROR;
+
+		addr = ops->map_resource(dev, phys, size, dir, attrs);
+	} else {
+		/*
+		 * The dma_ops API contract for ops->map_page() requires
+		 * kmappable memory, while ops->map_resource() does not.
+		 */
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
+	}
 
-	kmsan_handle_dma(phys, size, dir);
+	if (!is_mmio)
+		kmsan_handle_dma(phys, size, dir);
 	trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
 	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
@@ -185,14 +197,18 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
+	bool is_mmio = attrs & DMA_ATTR_MMIO;
 
 	BUG_ON(!valid_dma_direction(dir));
 	if (dma_map_direct(dev, ops) ||
-	    arch_dma_unmap_phys_direct(dev, addr + size))
+	    (!is_mmio && arch_dma_unmap_phys_direct(dev, addr + size)))
 		dma_direct_unmap_phys(dev, addr, size, dir, attrs);
 	else if (use_dma_iommu(dev))
 		iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
-	else
+	else if (is_mmio) {
+		if (ops->unmap_resource)
+			ops->unmap_resource(dev, addr, size, dir, attrs);
+	} else
 		ops->unmap_page(dev, addr, size, dir, attrs);
 	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
 	debug_dma_unmap_phys(dev, addr, size, dir);
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
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	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v4 11/16] dma-mapping: export new dma_*map_phys() interface
Date: Tue, 19 Aug 2025 20:36:55 +0300
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From: Leon Romanovsky 

Introduce new DMA mapping functions dma_map_phys() and dma_unmap_phys()
that operate directly on physical addresses instead of page+offset
parameters. This provides a more efficient interface for drivers that
already have physical addresses available.

The new functions are implemented as the primary mapping layer, with
the existing dma_map_page_attrs()/dma_map_resource() and
dma_unmap_page_attrs()/dma_unmap_resource() functions converted to simple
wrappers around the phys-based implementations.

In case dma_map_page_attrs(), the struct page is converted to physical
address with help of page_to_phys() function and dma_map_resource()
provides physical address as is together with addition of DMA_ATTR_MMIO
attribute.

The old page-based API is preserved in mapping.c to ensure that existing
code won't be affected by changing EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
variant for dma_*map_phys().

Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c   | 14 --------
 include/linux/dma-direct.h  |  2 --
 include/linux/dma-mapping.h | 13 +++++++
 include/linux/iommu-dma.h   |  4 ---
 include/trace/events/dma.h  |  2 --
 kernel/dma/debug.c          | 43 -----------------------
 kernel/dma/debug.h          | 21 -----------
 kernel/dma/direct.c         | 16 ---------
 kernel/dma/mapping.c        | 69 ++++++++++++++++++++-----------------
 9 files changed, 50 insertions(+), 134 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 6804aaf034a1..7944a3af4545 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -1556,20 +1556,6 @@ void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
 		__iommu_dma_unmap(dev, start, end - start);
 }
 
-dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
-		size_t size, enum dma_data_direction dir, unsigned long attrs)
-{
-	return __iommu_dma_map(dev, phys, size,
-			dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO,
-			dma_get_mask(dev));
-}
-
-void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
-		size_t size, enum dma_data_direction dir, unsigned long attrs)
-{
-	__iommu_dma_unmap(dev, handle, size);
-}
-
 static void __iommu_dma_free(struct device *dev, size_t size, void *cpu_addr)
 {
 	size_t alloc_size = PAGE_ALIGN(size);
diff --git a/include/linux/dma-direct.h b/include/linux/dma-direct.h
index f3bc0bcd7098..c249912456f9 100644
--- a/include/linux/dma-direct.h
+++ b/include/linux/dma-direct.h
@@ -149,7 +149,5 @@ void dma_direct_free_pages(struct device *dev, size_t size,
 		struct page *page, dma_addr_t dma_addr,
 		enum dma_data_direction dir);
 int dma_direct_supported(struct device *dev, u64 mask);
-dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
-		size_t size, enum dma_data_direction dir, unsigned long attrs);
 
 #endif /* _LINUX_DMA_DIRECT_H */
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 4254fd9bdf5d..8248ff9363ee 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -138,6 +138,10 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		unsigned long attrs);
 void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs);
+dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs);
+void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size,
+		enum dma_data_direction dir, unsigned long attrs);
 unsigned int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
 		int nents, enum dma_data_direction dir, unsigned long attrs);
 void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg,
@@ -192,6 +196,15 @@ static inline void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
 }
+static inline dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys,
+		size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+	return DMA_MAPPING_ERROR;
+}
+static inline void dma_unmap_phys(struct device *dev, dma_addr_t addr,
+		size_t size, enum dma_data_direction dir, unsigned long attrs)
+{
+}
 static inline unsigned int dma_map_sg_attrs(struct device *dev,
 		struct scatterlist *sg, int nents, enum dma_data_direction dir,
 		unsigned long attrs)
diff --git a/include/linux/iommu-dma.h b/include/linux/iommu-dma.h
index 485bdffed988..a92b3ff9b934 100644
--- a/include/linux/iommu-dma.h
+++ b/include/linux/iommu-dma.h
@@ -42,10 +42,6 @@ size_t iommu_dma_opt_mapping_size(void);
 size_t iommu_dma_max_mapping_size(struct device *dev);
 void iommu_dma_free(struct device *dev, size_t size, void *cpu_addr,
 		dma_addr_t handle, unsigned long attrs);
-dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
-		size_t size, enum dma_data_direction dir, unsigned long attrs);
-void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
-		size_t size, enum dma_data_direction dir, unsigned long attrs);
 struct sg_table *iommu_dma_alloc_noncontiguous(struct device *dev, size_t size,
 		enum dma_data_direction dir, gfp_t gfp, unsigned long attrs);
 void iommu_dma_free_noncontiguous(struct device *dev, size_t size,
diff --git a/include/trace/events/dma.h b/include/trace/events/dma.h
index 84416c7d6bfa..5da59fd8121d 100644
--- a/include/trace/events/dma.h
+++ b/include/trace/events/dma.h
@@ -73,7 +73,6 @@ DEFINE_EVENT(dma_map, name, \
 	TP_ARGS(dev, phys_addr, dma_addr, size, dir, attrs))
 
 DEFINE_MAP_EVENT(dma_map_phys);
-DEFINE_MAP_EVENT(dma_map_resource);
 
 DECLARE_EVENT_CLASS(dma_unmap,
 	TP_PROTO(struct device *dev, dma_addr_t addr, size_t size,
@@ -111,7 +110,6 @@ DEFINE_EVENT(dma_unmap, name, \
 	TP_ARGS(dev, addr, size, dir, attrs))
 
 DEFINE_UNMAP_EVENT(dma_unmap_phys);
-DEFINE_UNMAP_EVENT(dma_unmap_resource);
 
 DECLARE_EVENT_CLASS(dma_alloc_class,
 	TP_PROTO(struct device *dev, void *virt_addr, dma_addr_t dma_addr,
diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c
index da6734e3a4ce..06e31fd216e3 100644
--- a/kernel/dma/debug.c
+++ b/kernel/dma/debug.c
@@ -38,7 +38,6 @@ enum {
 	dma_debug_single,
 	dma_debug_sg,
 	dma_debug_coherent,
-	dma_debug_resource,
 	dma_debug_phy,
 };
 
@@ -141,7 +140,6 @@ static const char *type2name[] = {
 	[dma_debug_single] = "single",
 	[dma_debug_sg] = "scatter-gather",
 	[dma_debug_coherent] = "coherent",
-	[dma_debug_resource] = "resource",
 	[dma_debug_phy] = "phy",
 };
 
@@ -1448,47 +1446,6 @@ void debug_dma_free_coherent(struct device *dev, size_t size,
 	check_unmap(&ref);
 }
 
-void debug_dma_map_resource(struct device *dev, phys_addr_t addr, size_t size,
-			    int direction, dma_addr_t dma_addr,
-			    unsigned long attrs)
-{
-	struct dma_debug_entry *entry;
-
-	if (unlikely(dma_debug_disabled()))
-		return;
-
-	entry = dma_entry_alloc();
-	if (!entry)
-		return;
-
-	entry->type		= dma_debug_resource;
-	entry->dev		= dev;
-	entry->paddr		= addr;
-	entry->size		= size;
-	entry->dev_addr		= dma_addr;
-	entry->direction	= direction;
-	entry->map_err_type	= MAP_ERR_NOT_CHECKED;
-
-	add_dma_entry(entry, attrs);
-}
-
-void debug_dma_unmap_resource(struct device *dev, dma_addr_t dma_addr,
-			      size_t size, int direction)
-{
-	struct dma_debug_entry ref = {
-		.type           = dma_debug_resource,
-		.dev            = dev,
-		.dev_addr       = dma_addr,
-		.size           = size,
-		.direction      = direction,
-	};
-
-	if (unlikely(dma_debug_disabled()))
-		return;
-
-	check_unmap(&ref);
-}
-
 void debug_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
 				   size_t size, int direction)
 {
diff --git a/kernel/dma/debug.h b/kernel/dma/debug.h
index 76adb42bffd5..424b8f912ade 100644
--- a/kernel/dma/debug.h
+++ b/kernel/dma/debug.h
@@ -30,14 +30,6 @@ extern void debug_dma_alloc_coherent(struct device *dev, size_t size,
 extern void debug_dma_free_coherent(struct device *dev, size_t size,
 				    void *virt, dma_addr_t addr);
 
-extern void debug_dma_map_resource(struct device *dev, phys_addr_t addr,
-				   size_t size, int direction,
-				   dma_addr_t dma_addr,
-				   unsigned long attrs);
-
-extern void debug_dma_unmap_resource(struct device *dev, dma_addr_t dma_addr,
-				     size_t size, int direction);
-
 extern void debug_dma_sync_single_for_cpu(struct device *dev,
 					  dma_addr_t dma_handle, size_t size,
 					  int direction);
@@ -88,19 +80,6 @@ static inline void debug_dma_free_coherent(struct device *dev, size_t size,
 {
 }
 
-static inline void debug_dma_map_resource(struct device *dev, phys_addr_t addr,
-					  size_t size, int direction,
-					  dma_addr_t dma_addr,
-					  unsigned long attrs)
-{
-}
-
-static inline void debug_dma_unmap_resource(struct device *dev,
-					    dma_addr_t dma_addr, size_t size,
-					    int direction)
-{
-}
-
 static inline void debug_dma_sync_single_for_cpu(struct device *dev,
 						 dma_addr_t dma_handle,
 						 size_t size, int direction)
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index fa75e3070073..1062caac47e7 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -502,22 +502,6 @@ int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
 	return ret;
 }
 
-dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
-		size_t size, enum dma_data_direction dir, unsigned long attrs)
-{
-	dma_addr_t dma_addr = paddr;
-
-	if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
-		dev_err_once(dev,
-			     "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
-			     &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
-		WARN_ON_ONCE(1);
-		return DMA_MAPPING_ERROR;
-	}
-
-	return dma_addr;
-}
-
 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
 		void *cpu_addr, dma_addr_t dma_addr, size_t size,
 		unsigned long attrs)
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index fdabfdaeff1d..0ca098d2e88d 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -152,12 +152,10 @@ static inline bool dma_map_direct(struct device *dev,
 	return dma_go_direct(dev, *dev->dma_mask, ops);
 }
 
-dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
-		size_t offset, size_t size, enum dma_data_direction dir,
-		unsigned long attrs)
+dma_addr_t dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
-	phys_addr_t phys = page_to_phys(page) + offset;
 	bool is_mmio = attrs & DMA_ATTR_MMIO;
 	dma_addr_t addr;
 
@@ -177,6 +175,9 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 
 		addr = ops->map_resource(dev, phys, size, dir, attrs);
 	} else {
+		struct page *page = phys_to_page(phys);
+		size_t offset = offset_in_page(phys);
+
 		/*
 		 * The dma_ops API contract for ops->map_page() requires
 		 * kmappable memory, while ops->map_resource() does not.
@@ -191,9 +192,26 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 
 	return addr;
 }
+EXPORT_SYMBOL_GPL(dma_map_phys);
+
+dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
+		size_t offset, size_t size, enum dma_data_direction dir,
+		unsigned long attrs)
+{
+	phys_addr_t phys = page_to_phys(page) + offset;
+
+	if (unlikely(attrs & DMA_ATTR_MMIO))
+		return DMA_MAPPING_ERROR;
+
+	if (IS_ENABLED(CONFIG_DMA_API_DEBUG) &&
+	    WARN_ON_ONCE(is_zone_device_page(page)))
+		return DMA_MAPPING_ERROR;
+
+	return dma_map_phys(dev, phys, size, dir, attrs);
+}
 EXPORT_SYMBOL(dma_map_page_attrs);
 
-void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
+void dma_unmap_phys(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs)
 {
 	const struct dma_map_ops *ops = get_dma_ops(dev);
@@ -213,6 +231,16 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
 	debug_dma_unmap_phys(dev, addr, size, dir);
 }
+EXPORT_SYMBOL_GPL(dma_unmap_phys);
+
+void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
+		 enum dma_data_direction dir, unsigned long attrs)
+{
+	if (unlikely(attrs & DMA_ATTR_MMIO))
+		return;
+
+	dma_unmap_phys(dev, addr, size, dir, attrs);
+}
 EXPORT_SYMBOL(dma_unmap_page_attrs);
 
 static int __dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
@@ -338,41 +366,18 @@ EXPORT_SYMBOL(dma_unmap_sg_attrs);
 dma_addr_t dma_map_resource(struct device *dev, phys_addr_t phys_addr,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
-	const struct dma_map_ops *ops = get_dma_ops(dev);
-	dma_addr_t addr = DMA_MAPPING_ERROR;
-
-	BUG_ON(!valid_dma_direction(dir));
-
-	if (WARN_ON_ONCE(!dev->dma_mask))
+	if (IS_ENABLED(CONFIG_DMA_API_DEBUG) &&
+	    WARN_ON_ONCE(pfn_valid(PHYS_PFN(phys_addr))))
 		return DMA_MAPPING_ERROR;
 
-	if (dma_map_direct(dev, ops))
-		addr = dma_direct_map_resource(dev, phys_addr, size, dir, attrs);
-	else if (use_dma_iommu(dev))
-		addr = iommu_dma_map_resource(dev, phys_addr, size, dir, attrs);
-	else if (ops->map_resource)
-		addr = ops->map_resource(dev, phys_addr, size, dir, attrs);
-
-	trace_dma_map_resource(dev, phys_addr, addr, size, dir, attrs);
-	debug_dma_map_resource(dev, phys_addr, size, dir, addr, attrs);
-	return addr;
+	return dma_map_phys(dev, phys_addr, size, dir, attrs | DMA_ATTR_MMIO);
 }
 EXPORT_SYMBOL(dma_map_resource);
 
 void dma_unmap_resource(struct device *dev, dma_addr_t addr, size_t size,
 		enum dma_data_direction dir, unsigned long attrs)
 {
-	const struct dma_map_ops *ops = get_dma_ops(dev);
-
-	BUG_ON(!valid_dma_direction(dir));
-	if (dma_map_direct(dev, ops))
-		; /* nothing to do: uncached and no swiotlb */
-	else if (use_dma_iommu(dev))
-		iommu_dma_unmap_resource(dev, addr, size, dir, attrs);
-	else if (ops->unmap_resource)
-		ops->unmap_resource(dev, addr, size, dir, attrs);
-	trace_dma_unmap_resource(dev, addr, size, dir, attrs);
-	debug_dma_unmap_resource(dev, addr, size, dir);
+	dma_unmap_phys(dev, addr, size, dir, attrs | DMA_ATTR_MMIO);
 }
 EXPORT_SYMBOL(dma_unmap_resource);
 
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
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	Juergen Gross ,
	kasan-dev@googlegroups.com,
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	Madhavan Srinivasan ,
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	"Michael S. Tsirkin" ,
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	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
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	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v4 08/16] kmsan: convert kmsan_handle_dma to use physical addresses
Date: Tue, 19 Aug 2025 20:36:52 +0300
Message-ID: 
X-Mailer: git-send-email 2.50.1
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References: 
MIME-Version: 1.0
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From: Leon Romanovsky 

Convert the KMSAN DMA handling function from page-based to physical
address-based interface.

The refactoring renames kmsan_handle_dma() parameters from accepting
(struct page *page, size_t offset, size_t size) to (phys_addr_t phys,
size_t size). The existing semantics where callers are expected to
provide only kmap memory is continued here.

Signed-off-by: Leon Romanovsky 
---
 drivers/virtio/virtio_ring.c | 4 ++--
 include/linux/kmsan.h        | 9 ++++-----
 kernel/dma/mapping.c         | 3 ++-
 mm/kmsan/hooks.c             | 5 +++--
 tools/virtio/linux/kmsan.h   | 2 +-
 5 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index f5062061c408..c147145a6593 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -378,7 +378,7 @@ static int vring_map_one_sg(const struct vring_virtqueue *vq, struct scatterlist
 		 * is initialized by the hardware. Explicitly check/unpoison it
 		 * depending on the direction.
 		 */
-		kmsan_handle_dma(sg_page(sg), sg->offset, sg->length, direction);
+		kmsan_handle_dma(sg_phys(sg), sg->length, direction);
 		*addr = (dma_addr_t)sg_phys(sg);
 		return 0;
 	}
@@ -3157,7 +3157,7 @@ dma_addr_t virtqueue_dma_map_single_attrs(struct virtqueue *_vq, void *ptr,
 	struct vring_virtqueue *vq = to_vvq(_vq);
 
 	if (!vq->use_dma_api) {
-		kmsan_handle_dma(virt_to_page(ptr), offset_in_page(ptr), size, dir);
+		kmsan_handle_dma(virt_to_phys(ptr), size, dir);
 		return (dma_addr_t)virt_to_phys(ptr);
 	}
 
diff --git a/include/linux/kmsan.h b/include/linux/kmsan.h
index 2b1432cc16d5..f2fd221107bb 100644
--- a/include/linux/kmsan.h
+++ b/include/linux/kmsan.h
@@ -182,8 +182,7 @@ void kmsan_iounmap_page_range(unsigned long start, unsigned long end);
 
 /**
  * kmsan_handle_dma() - Handle a DMA data transfer.
- * @page:   first page of the buffer.
- * @offset: offset of the buffer within the first page.
+ * @phys:   physical address of the buffer.
  * @size:   buffer size.
  * @dir:    one of possible dma_data_direction values.
  *
@@ -192,7 +191,7 @@ void kmsan_iounmap_page_range(unsigned long start, unsigned long end);
  * * initializes the buffer, if it is copied from device;
  * * does both, if this is a DMA_BIDIRECTIONAL transfer.
  */
-void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
+void kmsan_handle_dma(phys_addr_t phys, size_t size,
 		      enum dma_data_direction dir);
 
 /**
@@ -372,8 +371,8 @@ static inline void kmsan_iounmap_page_range(unsigned long start,
 {
 }
 
-static inline void kmsan_handle_dma(struct page *page, size_t offset,
-				    size_t size, enum dma_data_direction dir)
+static inline void kmsan_handle_dma(phys_addr_t phys, size_t size,
+				    enum dma_data_direction dir)
 {
 }
 
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index 80481a873340..891e1fc3e582 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -172,7 +172,8 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
-	kmsan_handle_dma(page, offset, size, dir);
+
+	kmsan_handle_dma(phys, size, dir);
 	trace_dma_map_phys(dev, phys, addr, size, dir, attrs);
 	debug_dma_map_phys(dev, phys, size, dir, addr, attrs);
 
diff --git a/mm/kmsan/hooks.c b/mm/kmsan/hooks.c
index 97de3d6194f0..6de5c4820330 100644
--- a/mm/kmsan/hooks.c
+++ b/mm/kmsan/hooks.c
@@ -336,14 +336,15 @@ static void kmsan_handle_dma_page(const void *addr, size_t size,
 }
 
 /* Helper function to handle DMA data transfers. */
-void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
+void kmsan_handle_dma(phys_addr_t phys, size_t size,
 		      enum dma_data_direction dir)
 {
+	struct page *page = phys_to_page(phys);
 	u64 page_offset, to_go, addr;
 
 	if (PageHighMem(page))
 		return;
-	addr = (u64)page_address(page) + offset;
+	addr = (u64)page_address(page) + offset_in_page(phys);
 	/*
 	 * The kernel may occasionally give us adjacent DMA pages not belonging
 	 * to the same allocation. Process them separately to avoid triggering
diff --git a/tools/virtio/linux/kmsan.h b/tools/virtio/linux/kmsan.h
index 272b5aa285d5..6cd2e3efd03d 100644
--- a/tools/virtio/linux/kmsan.h
+++ b/tools/virtio/linux/kmsan.h
@@ -4,7 +4,7 @@
 
 #include 
 
-inline void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
+inline void kmsan_handle_dma(phys_addr_t phys, size_t size,
 			     enum dma_data_direction dir)
 {
 }
-- 
2.50.1



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To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
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Subject: [PATCH v4 15/16] block-dma: properly take MMIO path
Date: Tue, 19 Aug 2025 20:36:59 +0300
Message-ID: <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

Make sure that CPU is not synced and IOMMU is configured to take
MMIO path by providing newly introduced DMA_ATTR_MMIO attribute.

Signed-off-by: Leon Romanovsky 
---
 block/blk-mq-dma.c         | 13 +++++++++++--
 include/linux/blk-mq-dma.h |  6 +++++-
 include/linux/blk_types.h  |  2 ++
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/block/blk-mq-dma.c b/block/blk-mq-dma.c
index 37e2142be4f7..d415088ed9fd 100644
--- a/block/blk-mq-dma.c
+++ b/block/blk-mq-dma.c
@@ -87,8 +87,13 @@ static bool blk_dma_map_bus(struct blk_dma_iter *iter, struct phys_vec *vec)
 static bool blk_dma_map_direct(struct request *req, struct device *dma_dev,
 		struct blk_dma_iter *iter, struct phys_vec *vec)
 {
+	unsigned int attrs = 0;
+
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
+
 	iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len,
-			rq_dma_dir(req), 0);
+			rq_dma_dir(req), attrs);
 	if (dma_mapping_error(dma_dev, iter->addr)) {
 		iter->status = BLK_STS_RESOURCE;
 		return false;
@@ -103,14 +108,17 @@ static bool blk_rq_dma_map_iova(struct request *req, struct device *dma_dev,
 {
 	enum dma_data_direction dir = rq_dma_dir(req);
 	unsigned int mapped = 0;
+	unsigned int attrs = 0;
 	int error;
 
 	iter->addr = state->addr;
 	iter->len = dma_iova_size(state);
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
 
 	do {
 		error = dma_iova_link(dma_dev, state, vec->paddr, mapped,
-				vec->len, dir, 0);
+				vec->len, dir, attrs);
 		if (error)
 			break;
 		mapped += vec->len;
@@ -176,6 +184,7 @@ bool blk_rq_dma_map_iter_start(struct request *req, struct device *dma_dev,
 			 * same as non-P2P transfers below and during unmap.
 			 */
 			req->cmd_flags &= ~REQ_P2PDMA;
+			req->cmd_flags |= REQ_MMIO;
 			break;
 		default:
 			iter->status = BLK_STS_INVAL;
diff --git a/include/linux/blk-mq-dma.h b/include/linux/blk-mq-dma.h
index c26a01aeae00..6c55f5e58511 100644
--- a/include/linux/blk-mq-dma.h
+++ b/include/linux/blk-mq-dma.h
@@ -48,12 +48,16 @@ static inline bool blk_rq_dma_map_coalesce(struct dma_iova_state *state)
 static inline bool blk_rq_dma_unmap(struct request *req, struct device *dma_dev,
 		struct dma_iova_state *state, size_t mapped_len)
 {
+	unsigned int attrs = 0;
+
 	if (req->cmd_flags & REQ_P2PDMA)
 		return true;
 
 	if (dma_use_iova(state)) {
+		if (req->cmd_flags & REQ_MMIO)
+			attrs = DMA_ATTR_MMIO;
 		dma_iova_destroy(dma_dev, state, mapped_len, rq_dma_dir(req),
-				 0);
+				 attrs);
 		return true;
 	}
 
diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
index 09b99d52fd36..283058bcb5b1 100644
--- a/include/linux/blk_types.h
+++ b/include/linux/blk_types.h
@@ -387,6 +387,7 @@ enum req_flag_bits {
 	__REQ_FS_PRIVATE,	/* for file system (submitter) use */
 	__REQ_ATOMIC,		/* for atomic write operations */
 	__REQ_P2PDMA,		/* contains P2P DMA pages */
+	__REQ_MMIO,		/* contains MMIO memory */
 	/*
 	 * Command specific flags, keep last:
 	 */
@@ -420,6 +421,7 @@ enum req_flag_bits {
 #define REQ_FS_PRIVATE	(__force blk_opf_t)(1ULL << __REQ_FS_PRIVATE)
 #define REQ_ATOMIC	(__force blk_opf_t)(1ULL << __REQ_ATOMIC)
 #define REQ_P2PDMA	(__force blk_opf_t)(1ULL << __REQ_P2PDMA)
+#define REQ_MMIO	(__force blk_opf_t)(1ULL << __REQ_MMIO)
 
 #define REQ_NOUNMAP	(__force blk_opf_t)(1ULL << __REQ_NOUNMAP)
 
-- 
2.50.1



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From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig ,
	Danilo Krummrich ,
	iommu@lists.linux.dev,
	Jason Wang ,
	Jens Axboe ,
	Joerg Roedel ,
	Jonathan Corbet ,
	Juergen Gross ,
	kasan-dev@googlegroups.com,
	Keith Busch ,
	linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-mm@kvack.org,
	linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy ,
	rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev,
	Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: [PATCH v4 05/16] iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys
Date: Tue, 19 Aug 2025 20:36:49 +0300
Message-ID: <66e7cc6854e4e40278b598b38e0c4d49d7fcec91.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

Rename the IOMMU DMA mapping functions to better reflect their actual
calling convention. The functions iommu_dma_map_page() and
iommu_dma_unmap_page() are renamed to iommu_dma_map_phys() and
iommu_dma_unmap_phys() respectively, as they already operate on physical
addresses rather than page structures.

The calling convention changes from accepting (struct page *page,
unsigned long offset) to (phys_addr_t phys), which eliminates the need
for page-to-physical address conversion within the functions. This
renaming prepares for the broader DMA API conversion from page-based
to physical address-based mapping throughout the kernel.

All callers are updated to pass physical addresses directly, including
dma_map_page_attrs(), scatterlist mapping functions, and DMA page
allocation helpers. The change simplifies the code by removing the
page_to_phys() + offset calculation that was previously done inside
the IOMMU functions.

Signed-off-by: Leon Romanovsky 
---
 drivers/iommu/dma-iommu.c | 14 ++++++--------
 include/linux/iommu-dma.h |  7 +++----
 kernel/dma/mapping.c      |  4 ++--
 kernel/dma/ops_helpers.c  |  6 +++---
 4 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index e1185ba73e23..aea119f32f96 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -1195,11 +1195,9 @@ static inline size_t iova_unaligned(struct iova_domain *iovad, phys_addr_t phys,
 	return iova_offset(iovad, phys | size);
 }
 
-dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
-	      unsigned long offset, size_t size, enum dma_data_direction dir,
-	      unsigned long attrs)
+dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs)
 {
-	phys_addr_t phys = page_to_phys(page) + offset;
 	bool coherent = dev_is_dma_coherent(dev);
 	int prot = dma_info_to_prot(dir, coherent, attrs);
 	struct iommu_domain *domain = iommu_get_dma_domain(dev);
@@ -1227,7 +1225,7 @@ dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
 	return iova;
 }
 
-void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
+void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle,
 		size_t size, enum dma_data_direction dir, unsigned long attrs)
 {
 	struct iommu_domain *domain = iommu_get_dma_domain(dev);
@@ -1346,7 +1344,7 @@ static void iommu_dma_unmap_sg_swiotlb(struct device *dev, struct scatterlist *s
 	int i;
 
 	for_each_sg(sg, s, nents, i)
-		iommu_dma_unmap_page(dev, sg_dma_address(s),
+		iommu_dma_unmap_phys(dev, sg_dma_address(s),
 				sg_dma_len(s), dir, attrs);
 }
 
@@ -1359,8 +1357,8 @@ static int iommu_dma_map_sg_swiotlb(struct device *dev, struct scatterlist *sg,
 	sg_dma_mark_swiotlb(sg);
 
 	for_each_sg(sg, s, nents, i) {
-		sg_dma_address(s) = iommu_dma_map_page(dev, sg_page(s),
-				s->offset, s->length, dir, attrs);
+		sg_dma_address(s) = iommu_dma_map_phys(dev, sg_phys(s),
+				s->length, dir, attrs);
 		if (sg_dma_address(s) == DMA_MAPPING_ERROR)
 			goto out_unmap;
 		sg_dma_len(s) = s->length;
diff --git a/include/linux/iommu-dma.h b/include/linux/iommu-dma.h
index 508beaa44c39..485bdffed988 100644
--- a/include/linux/iommu-dma.h
+++ b/include/linux/iommu-dma.h
@@ -21,10 +21,9 @@ static inline bool use_dma_iommu(struct device *dev)
 }
 #endif /* CONFIG_IOMMU_DMA */
 
-dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
-		unsigned long offset, size_t size, enum dma_data_direction dir,
-		unsigned long attrs);
-void iommu_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
+dma_addr_t iommu_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
+		enum dma_data_direction dir, unsigned long attrs);
+void iommu_dma_unmap_phys(struct device *dev, dma_addr_t dma_handle,
 		size_t size, enum dma_data_direction dir, unsigned long attrs);
 int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 		enum dma_data_direction dir, unsigned long attrs);
diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
index fe1f0da6dc50..58482536db9b 100644
--- a/kernel/dma/mapping.c
+++ b/kernel/dma/mapping.c
@@ -169,7 +169,7 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
 	    arch_dma_map_page_direct(dev, phys + size))
 		addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
 	else if (use_dma_iommu(dev))
-		addr = iommu_dma_map_page(dev, page, offset, size, dir, attrs);
+		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
 	else
 		addr = ops->map_page(dev, page, offset, size, dir, attrs);
 	kmsan_handle_dma(page, offset, size, dir);
@@ -190,7 +190,7 @@ void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr, size_t size,
 	    arch_dma_unmap_page_direct(dev, addr + size))
 		dma_direct_unmap_page(dev, addr, size, dir, attrs);
 	else if (use_dma_iommu(dev))
-		iommu_dma_unmap_page(dev, addr, size, dir, attrs);
+		iommu_dma_unmap_phys(dev, addr, size, dir, attrs);
 	else
 		ops->unmap_page(dev, addr, size, dir, attrs);
 	trace_dma_unmap_phys(dev, addr, size, dir, attrs);
diff --git a/kernel/dma/ops_helpers.c b/kernel/dma/ops_helpers.c
index 9afd569eadb9..6f9d604d9d40 100644
--- a/kernel/dma/ops_helpers.c
+++ b/kernel/dma/ops_helpers.c
@@ -72,8 +72,8 @@ struct page *dma_common_alloc_pages(struct device *dev, size_t size,
 		return NULL;
 
 	if (use_dma_iommu(dev))
-		*dma_handle = iommu_dma_map_page(dev, page, 0, size, dir,
-						 DMA_ATTR_SKIP_CPU_SYNC);
+		*dma_handle = iommu_dma_map_phys(dev, page_to_phys(page), size,
+						 dir, DMA_ATTR_SKIP_CPU_SYNC);
 	else
 		*dma_handle = ops->map_page(dev, page, 0, size, dir,
 					    DMA_ATTR_SKIP_CPU_SYNC);
@@ -92,7 +92,7 @@ void dma_common_free_pages(struct device *dev, size_t size, struct page *page,
 	const struct dma_map_ops *ops = get_dma_ops(dev);
 
 	if (use_dma_iommu(dev))
-		iommu_dma_unmap_page(dev, dma_handle, size, dir,
+		iommu_dma_unmap_phys(dev, dma_handle, size, dir,
 				     DMA_ATTR_SKIP_CPU_SYNC);
 	else if (ops->unmap_page)
 		ops->unmap_page(dev, dma_handle, size, dir,
-- 
2.50.1



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	Alex Gaynor ,
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	Christoph Hellwig ,
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Subject: [PATCH v4 12/16] mm/hmm: migrate to physical address-based DMA mapping API
Date: Tue, 19 Aug 2025 20:36:56 +0300
Message-ID: <18165db0ff83f8222bfd05c4807cda206bec02f7.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

Convert HMM DMA operations from the legacy page-based API to the new
physical address-based dma_map_phys() and dma_unmap_phys() functions.
This demonstrates the preferred approach for new code that should use
physical addresses directly rather than page+offset parameters.

The change replaces dma_map_page() and dma_unmap_page() calls with
dma_map_phys() and dma_unmap_phys() respectively, using the physical
address that was already available in the code. This eliminates the
redundant page-to-physical address conversion and aligns with the
DMA subsystem's move toward physical address-centric interfaces.

This serves as an example of how new code should be written to leverage
the more efficient physical address API, which provides cleaner interfaces
for drivers that already have access to physical addresses.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 mm/hmm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index d545e2494994..015ab243f081 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -775,8 +775,8 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
 		if (WARN_ON_ONCE(dma_need_unmap(dev) && !dma_addrs))
 			goto error;
 
-		dma_addr = dma_map_page(dev, page, 0, map->dma_entry_size,
-					DMA_BIDIRECTIONAL);
+		dma_addr = dma_map_phys(dev, paddr, map->dma_entry_size,
+					DMA_BIDIRECTIONAL, 0);
 		if (dma_mapping_error(dev, dma_addr))
 			goto error;
 
@@ -819,8 +819,8 @@ bool hmm_dma_unmap_pfn(struct device *dev, struct hmm_dma_map *map, size_t idx)
 		dma_iova_unlink(dev, state, idx * map->dma_entry_size,
 				map->dma_entry_size, DMA_BIDIRECTIONAL, attrs);
 	} else if (dma_need_unmap(dev))
-		dma_unmap_page(dev, dma_addrs[idx], map->dma_entry_size,
-			       DMA_BIDIRECTIONAL);
+		dma_unmap_phys(dev, dma_addrs[idx], map->dma_entry_size,
+			       DMA_BIDIRECTIONAL, 0);
 
 	pfns[idx] &=
 		~(HMM_PFN_DMA_MAPPED | HMM_PFN_P2PDMA | HMM_PFN_P2PDMA_BUS);
-- 
2.50.1



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	Christoph Hellwig ,
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Subject: [PATCH v4 13/16] mm/hmm: properly take MMIO path
Date: Tue, 19 Aug 2025 20:36:57 +0300
Message-ID: <4b929da0b2dec4bccf489f35ee06098b437053b2.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

In case peer-to-peer transaction traverses through host bridge,
the IOMMU needs to have IOMMU_MMIO flag, together with skip of
CPU sync.

The latter was handled by provided DMA_ATTR_SKIP_CPU_SYNC flag,
but IOMMU flag was missed, due to assumption that such memory
can be treated as regular one.

Reuse newly introduced DMA attribute to properly take MMIO path.

Reviewed-by: Jason Gunthorpe 
Signed-off-by: Leon Romanovsky 
---
 mm/hmm.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/mm/hmm.c b/mm/hmm.c
index 015ab243f081..6556c0e074ba 100644
--- a/mm/hmm.c
+++ b/mm/hmm.c
@@ -746,7 +746,7 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
 	case PCI_P2PDMA_MAP_NONE:
 		break;
 	case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
-		attrs |= DMA_ATTR_SKIP_CPU_SYNC;
+		attrs |= DMA_ATTR_MMIO;
 		pfns[idx] |= HMM_PFN_P2PDMA;
 		break;
 	case PCI_P2PDMA_MAP_BUS_ADDR:
@@ -776,7 +776,7 @@ dma_addr_t hmm_dma_map_pfn(struct device *dev, struct hmm_dma_map *map,
 			goto error;
 
 		dma_addr = dma_map_phys(dev, paddr, map->dma_entry_size,
-					DMA_BIDIRECTIONAL, 0);
+					DMA_BIDIRECTIONAL, attrs);
 		if (dma_mapping_error(dev, dma_addr))
 			goto error;
 
@@ -811,16 +811,17 @@ bool hmm_dma_unmap_pfn(struct device *dev, struct hmm_dma_map *map, size_t idx)
 	if ((pfns[idx] & valid_dma) != valid_dma)
 		return false;
 
+	if (pfns[idx] & HMM_PFN_P2PDMA)
+		attrs |= DMA_ATTR_MMIO;
+
 	if (pfns[idx] & HMM_PFN_P2PDMA_BUS)
 		; /* no need to unmap bus address P2P mappings */
-	else if (dma_use_iova(state)) {
-		if (pfns[idx] & HMM_PFN_P2PDMA)
-			attrs |= DMA_ATTR_SKIP_CPU_SYNC;
+	else if (dma_use_iova(state))
 		dma_iova_unlink(dev, state, idx * map->dma_entry_size,
 				map->dma_entry_size, DMA_BIDIRECTIONAL, attrs);
-	} else if (dma_need_unmap(dev))
+	else if (dma_need_unmap(dev))
 		dma_unmap_phys(dev, dma_addrs[idx], map->dma_entry_size,
-			       DMA_BIDIRECTIONAL, 0);
+			       DMA_BIDIRECTIONAL, attrs);
 
 	pfns[idx] &=
 		~(HMM_PFN_DMA_MAPPED | HMM_PFN_P2PDMA | HMM_PFN_P2PDMA_BUS);
-- 
2.50.1



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	Christoph Hellwig ,
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Subject: [PATCH v4 14/16] block-dma: migrate to dma_map_phys instead of map_page
Date: Tue, 19 Aug 2025 20:36:58 +0300
Message-ID: <22b824931bc8ba090979ab902e4c1c2ec8327b65.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

After introduction of dma_map_phys(), there is no need to convert
from physical address to struct page in order to map page. So let's
use it directly.

Signed-off-by: Leon Romanovsky 
---
 block/blk-mq-dma.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/block/blk-mq-dma.c b/block/blk-mq-dma.c
index ad283017caef..37e2142be4f7 100644
--- a/block/blk-mq-dma.c
+++ b/block/blk-mq-dma.c
@@ -87,8 +87,8 @@ static bool blk_dma_map_bus(struct blk_dma_iter *iter, struct phys_vec *vec)
 static bool blk_dma_map_direct(struct request *req, struct device *dma_dev,
 		struct blk_dma_iter *iter, struct phys_vec *vec)
 {
-	iter->addr = dma_map_page(dma_dev, phys_to_page(vec->paddr),
-			offset_in_page(vec->paddr), vec->len, rq_dma_dir(req));
+	iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len,
+			rq_dma_dir(req), 0);
 	if (dma_mapping_error(dma_dev, iter->addr)) {
 		iter->status = BLK_STS_RESOURCE;
 		return false;
-- 
2.50.1



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	Christoph Hellwig ,
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Subject: [PATCH v4 16/16] nvme-pci: unmap MMIO pages with appropriate interface
Date: Tue, 19 Aug 2025 20:37:00 +0300
Message-ID: <545fffb8c364f36102919a5a1d57137731409f3c.1755624249.git.leon@kernel.org>
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From: Leon Romanovsky 

Block layer maps MMIO memory through dma_map_phys() interface
with help of DMA_ATTR_MMIO attribute. There is a need to unmap
that memory with the appropriate unmap function, something which
wasn't possible before adding new REQ attribute to block layer in
previous patch.

Signed-off-by: Leon Romanovsky 
---
 drivers/nvme/host/pci.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 2c6d9506b172..f8ecc0e0f576 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -682,11 +682,15 @@ static void nvme_free_prps(struct request *req)
 {
 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 	struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
+	unsigned int attrs = 0;
 	unsigned int i;
 
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
+
 	for (i = 0; i < iod->nr_dma_vecs; i++)
-		dma_unmap_page(nvmeq->dev->dev, iod->dma_vecs[i].addr,
-				iod->dma_vecs[i].len, rq_dma_dir(req));
+		dma_unmap_phys(nvmeq->dev->dev, iod->dma_vecs[i].addr,
+				iod->dma_vecs[i].len, rq_dma_dir(req), attrs);
 	mempool_free(iod->dma_vecs, nvmeq->dev->dmavec_mempool);
 }
 
@@ -699,15 +703,19 @@ static void nvme_free_sgls(struct request *req)
 	unsigned int sqe_dma_len = le32_to_cpu(iod->cmd.common.dptr.sgl.length);
 	struct nvme_sgl_desc *sg_list = iod->descriptors[0];
 	enum dma_data_direction dir = rq_dma_dir(req);
+	unsigned int attrs = 0;
+
+	if (req->cmd_flags & REQ_MMIO)
+		attrs = DMA_ATTR_MMIO;
 
 	if (iod->nr_descriptors) {
 		unsigned int nr_entries = sqe_dma_len / sizeof(*sg_list), i;
 
 		for (i = 0; i < nr_entries; i++)
-			dma_unmap_page(dma_dev, le64_to_cpu(sg_list[i].addr),
-				le32_to_cpu(sg_list[i].length), dir);
+			dma_unmap_phys(dma_dev, le64_to_cpu(sg_list[i].addr),
+				le32_to_cpu(sg_list[i].length), dir, attrs);
 	} else {
-		dma_unmap_page(dma_dev, sqe_dma_addr, sqe_dma_len, dir);
+		dma_unmap_phys(dma_dev, sqe_dma_addr, sqe_dma_len, dir, attrs);
 	}
 }
 
-- 
2.50.1



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To: Marek Szyprowski 
Cc: Leon Romanovsky ,
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Subject: [PATCH v4 10/16] xen: swiotlb: Open code map_resource callback
Date: Tue, 19 Aug 2025 20:36:54 +0300
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From: Leon Romanovsky 

General dma_direct_map_resource() is going to be removed
in next patch, so simply open-code it in xen driver.

Reviewed-by: Juergen Gross 
Signed-off-by: Leon Romanovsky 
---
 drivers/xen/swiotlb-xen.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c
index da1a7d3d377c..dd7747a2de87 100644
--- a/drivers/xen/swiotlb-xen.c
+++ b/drivers/xen/swiotlb-xen.c
@@ -392,6 +392,25 @@ xen_swiotlb_sync_sg_for_device(struct device *dev, struct scatterlist *sgl,
 	}
 }
 
+static dma_addr_t xen_swiotlb_direct_map_resource(struct device *dev,
+						  phys_addr_t paddr,
+						  size_t size,
+						  enum dma_data_direction dir,
+						  unsigned long attrs)
+{
+	dma_addr_t dma_addr = paddr;
+
+	if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
+		dev_err_once(dev,
+			     "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
+			     &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
+		WARN_ON_ONCE(1);
+		return DMA_MAPPING_ERROR;
+	}
+
+	return dma_addr;
+}
+
 /*
  * Return whether the given device DMA address mask can be supported
  * properly.  For example, if your device can only drive the low 24-bits
@@ -426,5 +445,5 @@ const struct dma_map_ops xen_swiotlb_dma_ops = {
 	.alloc_pages_op = dma_common_alloc_pages,
 	.free_pages = dma_common_free_pages,
 	.max_mapping_size = swiotlb_max_mapping_size,
-	.map_resource = dma_direct_map_resource,
+	.map_resource = xen_swiotlb_direct_map_resource,
 };
-- 
2.50.1



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On 2025-08-18 03:57, Jan Beulich wrote:
> The classification is pretty E820-centric anyway, and all uses of the
> function are now in x86-only code.
> 
> Switch the boolean return type to properly use bool while at it.
> 
> Signed-off-by: Jan Beulich 

Reviewed-by: Jason Andryuk 


From xen-devel-bounces@lists.xenproject.org Tue Aug 19 18:20:37 2025
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Date: Tue, 19 Aug 2025 12:20:04 -0600
From: Keith Busch 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 14/16] block-dma: migrate to dma_map_phys instead of
 map_page
Message-ID: 
References: 
 <22b824931bc8ba090979ab902e4c1c2ec8327b65.1755624249.git.leon@kernel.org>
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On Tue, Aug 19, 2025 at 08:36:58PM +0300, Leon Romanovsky wrote:
>  static bool blk_dma_map_direct(struct request *req, struct device *dma_dev,
>  		struct blk_dma_iter *iter, struct phys_vec *vec)
>  {
> -	iter->addr = dma_map_page(dma_dev, phys_to_page(vec->paddr),
> -			offset_in_page(vec->paddr), vec->len, rq_dma_dir(req));
> +	iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len,
> +			rq_dma_dir(req), 0);

Looks good.

Reviewed-by: Keith Busch 

Just a random thought when I had to double back to check what the "0"
means: many dma_ api's have a default macro without an "attrs" argument,
then an _attrs() version for when you need it. Not sure if you want to
strictly follow that pattern, but merely a suggestion.


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Date: Tue, 19 Aug 2025 12:22:30 -0600
From: Keith Busch 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
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	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 11/16] dma-mapping: export new dma_*map_phys()
 interface
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On Tue, Aug 19, 2025 at 08:36:55PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Introduce new DMA mapping functions dma_map_phys() and dma_unmap_phys()
> that operate directly on physical addresses instead of page+offset
> parameters. This provides a more efficient interface for drivers that
> already have physical addresses available.
> 
> The new functions are implemented as the primary mapping layer, with
> the existing dma_map_page_attrs()/dma_map_resource() and
> dma_unmap_page_attrs()/dma_unmap_resource() functions converted to simple
> wrappers around the phys-based implementations.
> 
> In case dma_map_page_attrs(), the struct page is converted to physical
> address with help of page_to_phys() function and dma_map_resource()
> provides physical address as is together with addition of DMA_ATTR_MMIO
> attribute.
> 
> The old page-based API is preserved in mapping.c to ensure that existing
> code won't be affected by changing EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
> variant for dma_*map_phys().

Looks good.

Reviewed-by: Keith Busch 


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In-Reply-To: <20250819171826.60700-1-roger.pau@citrix.com>
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On 19/08/2025 6:18 pm, Roger Pau Monne wrote:
> Otherwise the PCI accesses to segments different than the first one done by
> the IOMMU initialization code would silently fail by returning all ones.
>
> Introduce a new helper, called pci_setup(), and move both the creation of
> PCI segment 0 internal data structures, plus the parsing of ACPI MMCFG
> table to it.
>
> Signed-off-by: Roger Pau Monné 

And moving acpi_mmcfg_init() slightly earlier from acpi_boot_init() into
pci_setup().

> diff --git a/xen/arch/x86/pci.c b/xen/arch/x86/pci.c
> index 26bb7f6a3c3a..e75a29e851a7 100644
> --- a/xen/arch/x86/pci.c
> +++ b/xen/arch/x86/pci.c
> @@ -139,6 +142,19 @@ int pci_sanitize_bar_memory(struct rangeset *r)
>      return 0;
>  }
>  
> +void __init pci_setup(void)
> +{
> +    /*
> +     * Ahead of any ACPI table parsing make sure we have control structures
> +     * for PCI segment 0.
> +     */
> +    if ( pci_add_segment(0) )
> +        panic("Could not initialize PCI segment 0\n");
> +
> +    /* Parse ACPI MMCFG ahead of IOMMU, so accesses to segments > 0 is setup. */

"ahead of IOMMU" isn't helpful here because the relevant context is in
the caller.  Instead, I'd just say:

/* Parse ACPI MMCFG to see if other segments are available. */

> +    acpi_mmcfg_init();
> +}
> +
>  /*
>   * Local variables:
>   * mode: C
> diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
> index 6fb42c5a5f95..bd648323bfed 100644
> --- a/xen/arch/x86/setup.c
> +++ b/xen/arch/x86/setup.c
> @@ -1938,11 +1938,10 @@ void asmlinkage __init noreturn __start_xen(void)
>      setup_system_domains();
>  
>      /*
> -     * Ahead of any ACPI table parsing make sure we have control structures
> -     * for PCI segment 0.
> +     * Initialize PCI (create segment 0, setup MMCFG access) ahead of IOMMU
> +     * setup, as it requires access to the PCI config space.
>       */

Again, this isn't terribly clear IMO.

"ahead of IOMMU setup, as the IOMMUs might not all live on segment 0." ?


> -    if ( pci_add_segment(0) )
> -        panic("Could not initialize PCI segment 0\n");
> +    pci_setup();
>  
>      /*
>       * IOMMU-related ACPI table parsing has to happen before APIC probing, for
> diff --git a/xen/arch/x86/x86_64/mmconfig-shared.c b/xen/arch/x86/x86_64/mmconfig-shared.c
> index f1a3d42c5b21..fbe2676f8636 100644
> --- a/xen/arch/x86/x86_64/mmconfig-shared.c
> +++ b/xen/arch/x86/x86_64/mmconfig-shared.c
> @@ -402,6 +402,9 @@ void __init acpi_mmcfg_init(void)
>  {
>      bool valid = true;
>  
> +    if ( acpi_disabled )
> +        return;

This is fine for the patch, making things consistent with the prior
behaviour.

However, I think it's well gone time we drop support for pre-APCI
systems, including things like acpi_disabled, etc.

Nothing good can possibly come of these codepaths these days.

~Andrew


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Date: Tue, 19 Aug 2025 12:24:42 -0600
From: Keith Busch 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
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	Christoph Hellwig , Danilo Krummrich ,
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	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
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References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
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On Tue, Aug 19, 2025 at 08:36:59PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Make sure that CPU is not synced and IOMMU is configured to take
> MMIO path by providing newly introduced DMA_ATTR_MMIO attribute.

We may have a minor patch conflict here with my unmerged dma metadata
series, but not a big deal.

Looks good.

Reviewed-by: Keith Busch 


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Subject: Re: [PATCH] misra: add deviation for PrintErrMesg() function
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Subject: Re: [PATCH v2 2/2] common: make page_{is,get}_ram_type() x86-only
To: Jan Beulich ,
 "xen-devel@lists.xenproject.org" 
Cc: Julien Grall , Stefano Stabellini
 , Volodymyr Babchuk ,
 Bertrand Marquis ,
 Michal Orzel ,
 Oleksii Kurochko ,
 Anthony PERARD ,
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On 18/08/2025 8:57 am, Jan Beulich wrote:
> --- a/xen/arch/x86/include/asm/mm.h
> +++ b/xen/arch/x86/include/asm/mm.h
> @@ -464,6 +464,16 @@ extern bool opt_pv_linear_pt;
>      ASSERT(((_p)->count_info & PGC_count_mask) != 0);          \
>      ASSERT(page_get_owner(_p) == (_d))
>  
> +#define RAM_TYPE_CONVENTIONAL 0x00000001
> +#define RAM_TYPE_RESERVED     0x00000002
> +#define RAM_TYPE_UNUSABLE     0x00000004
> +#define RAM_TYPE_ACPI         0x00000008
> +#define RAM_TYPE_UNKNOWN      0x00000010
> +/* TRUE if the whole page at @mfn is of the requested RAM type(s) above. */
> +bool page_is_ram_type(unsigned long mfn, unsigned long mem_type);

Making it x86-only is fine, but if you're changing the return type,
mem_type can become shorter too.


Also, I'm struggling to convince myself that page_is_ram_type() is
correct.  Even if it is correct, it is horribly inefficient, and we run
this algorithm lots on boot.

Checking the type before the range is the backwards way of doing this,
and it can be a binary search because we go out of our way to fix
unsorted e820 maps.

Finally, acpi_memory_banned() shows that this really isn't the greatest
API in the first place.  It's explicitly designed to take multiple
inputs, but does the wrong thing for its' single caller wanting that
behaviour.  I can't help but feel we'd be in a better position by
removing this entirely and using plain E820 queries.

~Andrew


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Date: Tue, 19 Aug 2025 20:49:08 +0200
From: "Leon Romanovsky" 
To: "Keith Busch" 
Cc: "Marek Szyprowski" ,
 "Leon Romanovsky" ,
 "Jason Gunthorpe" ,
 "Abdiel Janulgue" ,
 "Alexander Potapenko" ,
 "Alex Gaynor" ,
 "Andrew Morton" ,
 "Christoph Hellwig" , "Danilo Krummrich" ,
 iommu@lists.linux.dev, "Jason Wang" ,
 "Jens Axboe" , "Joerg Roedel" ,
 "Jonathan Corbet" , "Juergen Gross" ,
 kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
 linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
 linux-mm@kvack.org, linux-nvme@lists.infradead.org,
 linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
 "Madhavan Srinivasan" ,
 "Masami Hiramatsu" ,
 "Michael Ellerman" ,
 "Michael S. Tsirkin" , "Miguel Ojeda" ,
 "Robin Murphy" , rust-for-linux@vger.kernel.org,
 "Sagi Grimberg" ,
 "Stefano Stabellini" ,
 "Steven Rostedt" , virtualization@lists.linux.dev,
 "Will Deacon" , xen-devel@lists.xenproject.org
Message-Id: <82f3cf3c-960b-41bc-82a8-ce84353706ed@app.fastmail.com>
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References: 
 <22b824931bc8ba090979ab902e4c1c2ec8327b65.1755624249.git.leon@kernel.org>
 
Subject: Re: [PATCH v4 14/16] block-dma: migrate to dma_map_phys instead of map_page
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On Tue, Aug 19, 2025, at 20:20, Keith Busch wrote:
> On Tue, Aug 19, 2025 at 08:36:58PM +0300, Leon Romanovsky wrote:
>>  static bool blk_dma_map_direct(struct request *req, struct device *dma_dev,
>>  		struct blk_dma_iter *iter, struct phys_vec *vec)
>>  {
>> -	iter->addr = dma_map_page(dma_dev, phys_to_page(vec->paddr),
>> -			offset_in_page(vec->paddr), vec->len, rq_dma_dir(req));
>> +	iter->addr = dma_map_phys(dma_dev, vec->paddr, vec->len,
>> +			rq_dma_dir(req), 0);
>
> Looks good.
>
> Reviewed-by: Keith Busch 
>
> Just a random thought when I had to double back to check what the "0"
> means: many dma_ api's have a default macro without an "attrs" argument,
> then an _attrs() version for when you need it. Not sure if you want to
> strictly follow that pattern, but merely a suggestion.

At some point,  I had both functions with and without attrs, but Christoph said that it is an artefact and I should introduce one function which accepts attrs but without _attrs in the name.

Thanks 


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Nicola Vetrini
	, Doug Goldstein , Stefano
 Stabellini , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: [PATCH] misra: consider conversion from UL or (void*) to function
 pointer as safe
Thread-Topic: [PATCH] misra: consider conversion from UL or (void*) to
 function pointer as safe
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Date: Tue, 19 Aug 2025 18:55:48 +0000
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Rule 11.1 states as following: "Conversions shall not be performed
between a pointer to a function and any other type."

The conversion from unsigned long or (void *) to a function pointer
is safe in Xen because the architectures it supports (e.g., x86 and
ARM) guarantee compatible representations between these types.

Configure Eclair to avoid reporting violations for conversions from
unsigned long or (void *) to a function pointer.

Add a compile-time assertion to the file 'xen/common/version.c' to
confirm this conversion compatibility across all target platforms
(assuming this file is common for all platforms).

Signed-off-by: Dmytro Prokopchuk 
---
Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1991940822

RFC thread:
https://patchew.org/Xen/8cbc9e6d881661d0d7a1055cbcef5a65e20522be.1755109168=
.git.dmytro._5Fprokopchuk1@epam.com/
---
 automation/eclair_analysis/ECLAIR/deviations.ecl |  8 ++++++++
 docs/misra/deviations.rst                        | 10 ++++++++++
 docs/misra/rules.rst                             |  8 +++++++-
 xen/common/version.c                             | 11 +++++++++++
 4 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index 7f3fd35a33..0083c9c505 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -375,6 +375,14 @@ constant expressions are required.\""
 }
 -doc_end
=20
+-doc_begin=3D"The conversion from unsigned long or (void *) to a function =
pointer is safe because the architectures Xen supports (e.g., x86 and ARM) =
guarantee compatible representations between these types."
+-config=3DMC3A2.R11.1,casts+=3D{safe,
+  "from(type(canonical(builtin(unsigned long)||pointer(builtin(void)))))
+   &&to(type(canonical(__function_pointer_types)))
+   &&relation(definitely_preserves_value)"
+}
+-doc_end
+
 -doc_begin=3D"The conversion from a function pointer to a boolean has a we=
ll-known semantics that do not lead to unexpected behaviour."
 -config=3DMC3A2.R11.1,casts+=3D{safe,
   "from(type(canonical(__function_pointer_types)))
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..74540e0565 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -370,6 +370,16 @@ Deviations related to MISRA C:2012 Rules:
        to store it.
      - Tagged as `safe` for ECLAIR.
=20
+   * - R11.1
+     - The conversion from unsigned long or (void \*) to a function pointe=
r does
+       not lose any information or violate type safety assumptions if unsi=
gned
+       long or (void \*) type is guaranteed to be the same bit size as a
+       function pointer. This ensures that the function pointer can be ful=
ly
+       represented without truncation or corruption. The macro BUILD_BUG_O=
N is
+       integrated into xen/common/version.c to confirm conversion compatib=
ility
+       across all target platforms.
+     - Tagged as `safe` for ECLAIR.
+
    * - R11.1
      - The conversion from a function pointer to a boolean has a well-know=
n
        semantics that do not lead to unexpected behaviour.
diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
index a2e4e9f4ff..ff48a90963 100644
--- a/docs/misra/rules.rst
+++ b/docs/misra/rules.rst
@@ -431,7 +431,13 @@ maintainers if you want to suggest a change.
      - All conversions to integer types are permitted if the destination
        type has enough bits to hold the entire value. Conversions to bool
        and void* are permitted. Conversions from 'void noreturn (*)(...)'
-       to 'void (*)(...)' are permitted.
+       to 'void (*)(...)' are permitted. Conversions from unsigned long or
+       (void \*) to a function pointer are permitted if the source type ha=
s
+       enough bits to restore function pointer without truncation or corru=
ption.
+       Example::
+
+           unsigned long func_addr =3D (unsigned long)&some_function;
+           void (*restored_func)(void) =3D (void (*)(void))func_addr;
=20
    * - `Rule 11.2 `_
      - Required
diff --git a/xen/common/version.c b/xen/common/version.c
index 553b97ba9b..7091a6d440 100644
--- a/xen/common/version.c
+++ b/xen/common/version.c
@@ -217,6 +217,17 @@ void __init xen_build_init(void)
 #endif /* CONFIG_X86 */
 }
 #endif /* BUILD_ID */
+
+static void __init __maybe_unused build_assertions(void)
+{
+    /*
+     * To confirm conversion compatibility between unsigned long, (void *)
+     * and function pointers for all supported architectures.
+     */
+    BUILD_BUG_ON(sizeof(unsigned long) !=3D sizeof(void (*)(void)));
+    BUILD_BUG_ON(sizeof(void *) !=3D sizeof(void (*)(void)));
+}
+
 /*
  * Local variables:
  * mode: C
--=20
2.43.0


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Date: Tue, 19 Aug 2025 20:45:19 +0100
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Subject: Re: [PATCH v2 11/16] x86/msr: Change rdmsr() to have normal API
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 19/08/2025 1:04 pm, Jan Beulich wrote:
> On 15.08.2025 22:41, Andrew Cooper wrote:
>> We want a consistent MSR API, and these want to be named rdmsr() and wrmsr(),
>> but not with their current APIs.  The current rdmsr() flavours writing to
>> their parameters by name makes code that reads like invalid C, and is
>> unergonomic to use in lots of cases.
>>
>> Change the API, and update the callers all in one go.  Where appropriate,
>> update the write side to wrmsrns() as per the recommendation.
>>
>> No functional change.
>>
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Jan Beulich 
>> CC: Roger Pau Monné 
>>
>> I do have a more creative solution if this patch is considered to be too
>> large.  https://gitlab.com/xen-project/hardware/xen-staging/-/commit/e13cf25d06d08481e2c138daa1fd902cf36d757b
> I'm not concerned by the size of this patch.
>
>> --- a/xen/arch/x86/cpu/intel.c
>> +++ b/xen/arch/x86/cpu/intel.c
>> @@ -23,17 +23,17 @@ static uint32_t __ro_after_init mcu_opt_ctrl_val;
>>  
>>  void update_mcu_opt_ctrl(void)
>>  {
>> -    uint32_t mask = mcu_opt_ctrl_mask, lo, hi;
>> +    uint32_t mask = mcu_opt_ctrl_mask, val;
>>  
>>      if ( !mask )
>>          return;
>>  
>> -    rdmsr(MSR_MCU_OPT_CTRL, lo, hi);
>> +    val = rdmsr(MSR_MCU_OPT_CTRL);
>>  
>> -    lo &= ~mask;
>> -    lo |= mcu_opt_ctrl_val;
>> +    val &= ~mask;
>> +    val |= mcu_opt_ctrl_val;
>>  
>> -    wrmsr(MSR_MCU_OPT_CTRL, lo, hi);
>> +    wrmsrns(MSR_MCU_OPT_CTRL, val);
>>  }
> I don't consider it a good idea to suddenly clear the upper half of this
> MSR, and ...
>
>> @@ -51,17 +51,17 @@ static uint32_t __ro_after_init pb_opt_ctrl_val;
>>  
>>  void update_pb_opt_ctrl(void)
>>  {
>> -    uint32_t mask = pb_opt_ctrl_mask, lo, hi;
>> +    uint32_t mask = pb_opt_ctrl_mask, val;
>>  
>>      if ( !mask )
>>          return;
>>  
>> -    rdmsr(MSR_PB_OPT_CTRL, lo, hi);
>> +    val = rdmsr(MSR_PB_OPT_CTRL);
>>  
>> -    lo &= ~mask;
>> -    lo |= pb_opt_ctrl_val;
>> +    val &= ~mask;
>> +    val |= pb_opt_ctrl_val;
>>  
>> -    wrmsr(MSR_PB_OPT_CTRL, lo, hi);
>> +    wrmsrns(MSR_PB_OPT_CTRL, val);
>>  }
> ... this one.

Yeah, both the local variables need turning into uint64_t here.

>
>> @@ -456,15 +456,15 @@ static void __init probe_mwait_errata(void)
>>   */
>>  static void Intel_errata_workarounds(struct cpuinfo_x86 *c)
>>  {
>> -	unsigned long lo, hi;
>> +	uint64_t val;
>>  
>>  	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
>> -		rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
>> -		if ((lo & (1<<9)) == 0) {
>> +		val = rdmsr(MSR_IA32_MISC_ENABLE);
>> +		if ((val & (1 << 9)) == 0) {
>>  			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
>>  			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
>> -			lo |= (1<<9);	/* Disable hw prefetching */
>> -			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
>> +			val |= (1 << 9); /* Disable hw prefetching */
>> +			wrmsrns(MSR_IA32_MISC_ENABLE, val);
>>  		}
>>  	}
> Move val into the more narrow scope at the same time?

No, not based on the history of this function.

>
>> @@ -699,7 +715,7 @@ void cf_check vmx_cpu_dead(unsigned int cpu)
>>  
>>  static int _vmx_cpu_up(bool bsp)
>>  {
>> -    u32 eax, edx;
>> +    u32 eax;
> Like you do elsewhere, switch to uint32_t at the same time?

Will do.

>
>> --- a/xen/arch/x86/tsx.c
>> +++ b/xen/arch/x86/tsx.c
>> @@ -42,6 +42,8 @@ void tsx_init(void)
>>  {
>>      static bool __read_mostly once;
>>  
>> +    uint64_t val;
>> +
>>      /*
> No real need for yet another newline, I would say.

Where?  Before?  that's separation of static and not.  After? that's
separation of variables and code.  All as we do elsewhere.

~Andrew


From xen-devel-bounces@lists.xenproject.org Tue Aug 19 19:58:41 2025
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Date: Tue, 19 Aug 2025 13:58:22 -0600
From: Keith Busch 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
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	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
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	"Michael S. Tsirkin" ,
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	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 16/16] nvme-pci: unmap MMIO pages with appropriate
 interface
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References: 
 <545fffb8c364f36102919a5a1d57137731409f3c.1755624249.git.leon@kernel.org>
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In-Reply-To: <545fffb8c364f36102919a5a1d57137731409f3c.1755624249.git.leon@kernel.org>

On Tue, Aug 19, 2025 at 08:37:00PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Block layer maps MMIO memory through dma_map_phys() interface
> with help of DMA_ATTR_MMIO attribute. There is a need to unmap
> that memory with the appropriate unmap function, something which
> wasn't possible before adding new REQ attribute to block layer in
> previous patch.

Looks good.

Reviewed-by: Keith Busch 


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Date: Tue, 19 Aug 2025 14:43:36 -0700 (PDT)
From: Stefano Stabellini 
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To: Jan Beulich 
cc: Stefano Stabellini , 
    Nicola Vetrini , 
    "xen-devel@lists.xenproject.org" , 
    Dmytro Prokopchuk1 
Subject: Re: [RFC] Next steps for MISRA C Rule 17.7 in XEN
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On Tue, 18 Aug 2025, Jan Beulich wrote:
> On 19.08.2025 01:45, Stefano Stabellini wrote:
> > On Mon, 18 Aug 2025, Dmytro Prokopchuk1 wrote:
> >> On 8/4/25 11:02, Jan Beulich wrote:
> >>> On 02.08.2025 19:48, Dmytro Prokopchuk1 wrote:
> >>>> There are a lot of MISRA C R17.7 violations in the XEN.
> >>>> This rule states: "The value returned by a function having non-void
> >>>> return type shall be used".
> >>>>
> >>>> Actually, need to decide how to deal with these violations.
> >>>> Quick analyze shown that there are different cases in XEN code base.
> >>>
> >>> Long ago, when we discussed the rules in a mainly abstract way, there already
> >>> was quite a bit of discussion around this. Stefano - I wonder if you had
> >>> taken (and have kept) notes back at the time?
> >>>
> >>> Jan
> >>
> >> Hi Stefano.
> >>
> >> This is a kind reminder.
> > 
> > Yes, I am appending below the unmodified notes which I took when we
> > discussed R17.7. It looks like the decision was to accept the rule and
> > use a mix of deviations and void casts to reach compliance.
> > 
> > 
> > MISRA 17.7 Use expressions' results
> > -----------------------------------
> > 
> > ACCEPT 17.7
> > 
> > Returning void when appropriate
> > 
> > When function results are used on some of the times. Use a comment to
> > explain why the return value is ignored and a void cast so that the
> > warning doesn't trigger (there is also a gcc warning).
> > 
> > Some functions are returning a value just for convenience (e.g. memcpy).
> > They need to be deviated.
> > 
> > Add must_check to all functions by default somehow? So that developers
> > will get automatic feedback when they do develpment without having to
> > wait for ECLAIR
> 
> Isn't doing this "by default" equivalent to enabling the compiler warning?
> If doing this by default (one way or another), it'll need to be clear how
> to mark functions as "exceptions" (like memcpy() that you mention).

Indeed, that is the problem.

I think the idea was to employ a different strategy depending on
whether the function returns an error or simply provides optional
information.

For functions that return errors, we would use explicit (void) casts.
For functions that return optional information, we would apply global
deviations.

Of course, these are only general guidelines. If a function that returns
errors has thousands of violations, making it impractical to address
each one individually, we would likely opt for a global deviation in
that case as well.



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Date: Tue, 19 Aug 2025 23:58:31 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall , Alejandro Vallejo , xen-devel@lists.xenproject.org
Subject: Re: [PATCH v16 1/4] xen/domain: unify domain ID allocation
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In-Reply-To: 
References: <20250812223024.2364749-1-dmukhin@ford.com> <20250812223024.2364749-2-dmukhin@ford.com> 
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On Thu, Aug 14, 2025 at 09:11:11AM +0200, Jan Beulich wrote:
> On 13.08.2025 00:30, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Currently, there are two different domain ID allocation implementations=
:
> >
> >   1) Sequential IDs allocation in dom0less Arm code based on max_init_d=
omid;
> >
> >   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
> >      max_init_domid (both Arm and x86).
> >
> > The domain ID allocation covers dom0 or late hwdom, predefined domains,
> > post-boot domains, excluding Xen system domains (domid >=3D
> > DOMID_FIRST_RESERVED).
> >
> > It makes sense to have a common helper code for such task across archit=
ectures
> > (Arm and x86) and between dom0less / toolstack domU allocation.
> >
> > Note, fixing dependency on max_init_domid is out of scope of this patch=
.
> >
> > Wrap the domain ID allocation as an arch-independent function domid_all=
oc() in
> > new common/domid.c based on the bitmap.
> >
> > Allocation algorithm:
> > - If an explicit domain ID is provided, verify its availability and use=
 it if
> >   ID is not used;
> > - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERV=
ED-1],
> >   starting from the last used ID.
> >   Implementation guarantees that two consecutive calls will never retur=
n the
> >   same ID. ID#0 is reserved for the first boot domain (currently, dom0)=
 and
> >   excluded from the allocation range.
> >
> > Remove is_free_domid() helper as it is not needed now.
> >
> > No functional change intended.
> >
> > Signed-off-by: Denis Mukhin 
> > Reviewed-by: Julien Grall 
> > Reviewed-by: Alejandro Vallejo 
> > ---
> > Changes since v15:
> > - fixup for check after the first pass in the bitarray in domid_alloc()
> > - trivial renaming for the local variable in domid_alloc()
> > - kept Julien's R-b, added Alejandro's R-b
>=20
> Just to mention: My take is that this kind of a fix ought to invalidate a=
ll
> earlier R-b. It's not just a cosmetic change, after all.

Sorry for the hiccup here, did not mean to overrule the review process.

My bold assumption was that in case of small fixups like this it is
satisfactory to carry over previous acks.

I asked (matrix) both Julien and Alejandro to re-review and confirm.

>=20
> Jan



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From: "Penny, Zheng" 
To: Jan Beulich , Oleksii Kurochko
	
CC: "Huang, Ray" , Andrew Cooper
	, =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Anthony PERARD , "Orzel,
 Michal" , Julien Grall , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
Thread-Topic: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
Thread-Index: AQHcDc9CvptjGFID1k2o17sSnGSDybRoGVoAgALK9QA=
Date: Wed, 20 Aug 2025 03:12:30 +0000
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References: <20250815102728.1340505-1-Penny.Zheng@amd.com>
 
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From: Juergen Gross 
To: xen-devel@lists.xenproject.org
Cc: Oleksii Kurochko ,
 Community Manager 
Message-ID: <09819192-cdeb-441f-9bdf-d334e076c833@suse.com>
Subject: Re: [PATCH v3 9/9] CHANGELOG.md: add xenstorepvh-stubdom live update
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 <20250730122305.4050-10-jgross@suse.com>
In-Reply-To: <20250730122305.4050-10-jgross@suse.com>

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Date: Wed, 20 Aug 2025 08:05:54 +0200
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Subject: Re: [PATCH v3 8/9] SUPPORT.md: add xenstorepvh-stubdom live update
To: xen-devel@lists.xenproject.org
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini 
References: <20250730122305.4050-1-jgross@suse.com>
 <20250730122305.4050-9-jgross@suse.com>
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From: Juergen Gross 
To: xen-devel@lists.xenproject.org
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini 
Message-ID: 
Subject: Re: [PATCH v3 8/9] SUPPORT.md: add xenstorepvh-stubdom live update
References: <20250730122305.4050-1-jgross@suse.com>
 <20250730122305.4050-9-jgross@suse.com>
In-Reply-To: <20250730122305.4050-9-jgross@suse.com>
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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Nicola Vetrini
	, Doug Goldstein , Stefano
 Stabellini , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: [PATCH] misra: add deviation for MISRA C Rule 11.3
Thread-Topic: [PATCH] misra: add deviation for MISRA C Rule 11.3
Thread-Index: AQHcEaKMMDydbZiTjE+UNGKddouDNQ==
Date: Wed, 20 Aug 2025 07:17:54 +0000
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MISRA C Rule 11.3 states: "A cast shall not be performed between a pointer
to object type and a pointer to a different object type."

Violations of this rule arise due to the 'container_of' macro, which casts
a member of a structure to its containing structure:
    container_of(ptr, type, member) ({                             \
           typeof_field(type, member) *__mptr =3D (ptr);             \
           (type *)( (char *)__mptr - offsetof(type,member) );})

The 'container_of' macro is safe because it relies on the standardized and
well-defined 'offsetof' macro to calculate the memory address of the
containing structure, while assuming proper alignment and ensuring no
undefined behavior, provided that the input pointer is valid and points to
the specified member.

Configure Eclair to suppress violation reports related to 'container_of
macro. Update 'deviations.rst' file accordingly. Add Rule 11.3 to the
monitored list.
No functional changes.

Signed-off-by: Dmytro Prokopchuk 
---
Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1992968166
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 8 ++++++++
 automation/eclair_analysis/ECLAIR/monitored.ecl  | 1 +
 docs/misra/deviations.rst                        | 8 ++++++++
 3 files changed, 17 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index 7f3fd35a33..3e595e3a8c 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -403,6 +403,14 @@ because the semantics of the 'noreturn' attribute do n=
ot alter the calling conve
 }
 -doc_end
=20
+-doc_begin=3D"Convesions in the 'container_of' macro are safe because it r=
elies on
+the standardized and well-defined 'offsetof' macro to calculate the memory=
 address
+of the containing structure, while assuming proper alignment and ensuring =
no
+undefined behavior, provided that the input pointer is valid and points to=
 the
+specified member."
+-config=3DMC3A2.R11.3,reports+=3D{safe,"any_area(any_loc(any_exp(macro(^co=
ntainer_of$))))"}
+-doc_end
+
 -doc_begin=3D"Conversions from and to integral types are safe, in the assu=
mption that the target type has enough bits to store the value.
 See also Section \"4.7 Arrays and Pointers\" of \"GCC_MANUAL\""
 -config=3DMC3A2.R11.6,casts+=3D{safe,
diff --git a/automation/eclair_analysis/ECLAIR/monitored.ecl b/automation/e=
clair_analysis/ECLAIR/monitored.ecl
index 72698b2eb1..abfc102d60 100644
--- a/automation/eclair_analysis/ECLAIR/monitored.ecl
+++ b/automation/eclair_analysis/ECLAIR/monitored.ecl
@@ -45,6 +45,7 @@
 -enable=3DMC3A2.R10.2
 -enable=3DMC3A2.R11.1
 -enable=3DMC3A2.R11.2
+-enable=3DMC3A2.R11.3
 -enable=3DMC3A2.R11.6
 -enable=3DMC3A2.R11.7
 -enable=3DMC3A2.R11.8
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..33b045a5a9 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -393,6 +393,14 @@ Deviations related to MISRA C:2012 Rules:
        (i.e., less strict) alignment requirement are safe.
      - Tagged as `safe` for ECLAIR.
=20
+   * - R11.3
+     - Convesions in the 'container_of' macro are safe because it relies o=
n
+       the standardized and well-defined 'offsetof' macro to calculate the=
 memory
+       address of the containing structure, while assuming proper alignmen=
t and
+       ensuring no undefined behavior, provided that the input pointer is =
valid
+       and points to the specified member.
+     - Tagged as `safe` for ECLAIR.
+
    * - R11.6
      - Conversions from and to integral types are safe, in the assumption =
that
        the target type has enough bits to store the value.
--=20
2.43.0


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH] misra: fix Rule 11.3 violation in 'vcpu_mark_events_pending'
Thread-Topic: [PATCH] misra: fix Rule 11.3 violation in
 'vcpu_mark_events_pending'
Thread-Index: AQHcEahzo6Ns4M/vpkyFl3Gc8+EN0g==
Date: Wed, 20 Aug 2025 08:00:09 +0000
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MISRA C:2012 Rule 11.3 states: "A cast shall not be performed between
a pointer to object type and a pointer to a different object type."

The function 'vcpu_mark_events_pending' contains a non-compliant cast
to (unsigned long*). Remove the explicit cast and pass the compatible
pointer type to the 'guest_test_and_set_bit' macro.

Fixes: c626aa1a5a (arm: implement event injection, 2012-06-01)
Signed-off-by: Dmytro Prokopchuk 
---
Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1993054203
---
 xen/arch/arm/domain.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 310c578909..6371e68cc7 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -1166,7 +1166,7 @@ void arch_dump_vcpu_info(struct vcpu *v)
 void vcpu_mark_events_pending(struct vcpu *v)
 {
     bool already_pending =3D guest_test_and_set_bit(v->domain,
-        0, (unsigned long *)&vcpu_info(v, evtchn_upcall_pending));
+        0, &vcpu_info(v, evtchn_upcall_pending));
=20
     if ( already_pending )
         return;
--=20
2.43.0


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From: Dmytro Prokopchuk1 
To: Stefano Stabellini , Jan Beulich
	, Nicola Vetrini 
CC: Doug Goldstein , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , "Daniel P.
 Smith" ,
	=?utf-8?B?TWFyZWsgTWFyY3p5a293c2tpLUfDs3JlY2tp?=
	, Dario Faggioli ,
	Juergen Gross , George Dunlap ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH] misra: address MISRA C Rule 18.3 compliance
Thread-Topic: [PATCH] misra: address MISRA C Rule 18.3 compliance
Thread-Index: AQHb+7pQeGfsWWy0sUade1ju+9GDKrQ/vEEAgAOkMwCABlLfAIAhvCAA
Date: Wed, 20 Aug 2025 09:18:57 +0000
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From: Juergen Gross 
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 George Dunlap ,
 "xen-devel@lists.xenproject.org" 
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Subject: Re: [PATCH] misra: address MISRA C Rule 18.3 compliance
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 <36042f23-7795-4717-be4a-cd22e52b3145@epam.com>
 
 
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From: Juergen Gross 
To: xen-devel@lists.xenproject.org
Cc: Juergen Gross ,
	Julien Grall ,
	Anthony PERARD 
Subject: [PATCH] tools/xenstored: fix possible NULL deref
Date: Wed, 20 Aug 2025 12:46:17 +0200
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Avoid dereferencing NULL in introduce_domain() when called during
live update.

Coverity ID: 1665111
Fixes: f78895ad78c9 ("tools/xenstored: Read event channel from xenstored page")

Signed-off-by: Juergen Gross 
---
 tools/xenstored/domain.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/xenstored/domain.c b/tools/xenstored/domain.c
index 694d68670a..5ce539d640 100644
--- a/tools/xenstored/domain.c
+++ b/tools/xenstored/domain.c
@@ -1032,7 +1032,7 @@ static struct domain *introduce_domain(const void *ctx,
 		if (!interface && !restore)
 			return NULL;
 
-		if (interface->evtchn_port)
+		if (!restore && interface->evtchn_port)
 			port = interface->evtchn_port;
 
 		if (new_domain(domain, port, restore)) {
-- 
2.43.0



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From: =?UTF-8?Q?Petr_Bene=C5=A1?= 
Date: Wed, 20 Aug 2025 12:47:23 +0200
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Message-ID: 
Subject: Ping: [PATCH v12 0/6] x86: Make MAX_ALTP2M configurable
To: Xen-devel 
Cc: Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Volodymyr Babchuk , Andrew Cooper , 
	Anthony PERARD , Jan Beulich , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Shawn Anastasio , 
	Alistair Francis , Bob Eshleman , 
	Connor Davis , Oleksii Kurochko , 
	Tamas K Lengyel , Alexandru Isaila , 
	Petre Pircalabu , Juergen Gross , 
	Christian Lindig , David Scott 
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Thu, Jul 31, 2025 at 11:28=E2=80=AFAM Petr Bene=C5=A1  wrote:
>
> From: Petr Bene=C5=A1 
>
> This series introduces the ability to configure the maximum number of alt=
p2m
> tables during domain creation. Previously, the limits were hardcoded to a
> maximum of 10. This change allows for greater flexibility in environments=
 that
> require more or fewer altp2m views.
>
> This enhancement is particularly relevant for users leveraging Xen's feat=
ures
> for virtual machine introspection.
>
> Changes since v11:
> - altp2m: Drop p2m_altp2m_check() stubs on non-x86, move prototype, and g=
uard
>   uses
>     - s/following/subsequent/ in the commit message + Reviewed-by: Jan Be=
ulich
>     - Despite agreeing to let Jan make this change, this commit wasn't st=
ill in
>       the staging branch at the time of sending this patch.
>
> - x86/altp2m: Wrap altp2m-specific code in #ifdef CONFIG_ALTP2M
>     - Change typo #else /* !CONFIG_HVM */ -> #else /* !CONFIG_ALTP2M */ i=
n p2m.h
>     - Move p2m_altp2m_get_or_propagate & p2m_altp2m_propagate_change outs=
ide of
>       #ifdef CONFIG_ALTP2M / #else / #endif and added comment mentioning =
that
>       these altp2m declarations are outside of the #ifdef scope intention=
ally.
>
> Changes since v10:
> - x86/altp2m: Remove p2m_altp2m_check stubs from unsupported architecture=
s
>     - (now "altp2m: drop p2m_altp2m_check() stubs on non-x86, move protot=
ype,
>        and guard uses").
>     - Changed commit message to reflect new changes.
>     - Removed p2m_altp2m_check from x86/include/asm/p2m.h.
>     - Introduced p2m_altp2m_check in xen/include/xen/p2m-common.h.
>     - Replaced #ifdef CONFIG_ALTP2M with IS_ENABLED(CONFIG_ALTP2M) in
>       vm_event.c.
>
> - x86/altp2m: Wrap altp2m-specific code in #ifdef CONFIG_ALTP2M
>     - Added `else if ( IS_ENABLED(CONFIG_ALTP2M) )` before calling
>       hvm_fast_singlestep in vm_event_toggle_singlestep, to make sure tha=
t
>       hvm_fast_singlestep is unreachable when ALTP2M=3Dn.
>
>       Also, the #ifdef CONFIG_ALTP2M inside hvm_fast_singlestep was moved=
 to be
>       _outside_ the function (wrapping it entirely).
>
>     - Removed formatting of the hvmemul_vmfunc function header + moved
>       the #ifdef to be inside the function body.
>
>     - Removed altp2m_vcpu_update_{p2m,vmfunc_ve}() declarations
>       from hvm.h, since they are not used when CONFIG_ALTP2M is not set.
>
> - xen: Make the maximum number of altp2m views configurable for x86
>     - In do_altp2m_op, -EOPNOTSUPP is now returned when nr_altp2m =3D=3D =
0, instead
>       of -EINVAL.
>
>     - Removed stray empty lines that were introduced in
>       p2m_mem_access_emulate_check & p2m_mem_access_check.
>
> Changes since v9:
> - Introduced 3 more patches:
>   - x86/p2m: Short-circuit p2m_is_altp2m() when CONFIG_ALTP2M=3Dn
>     - Needed to optimize out `if ( p2m_is_altp2m(p2m) )` when CONFIG_ALTP=
2M=3Dn.
>   - x86/altp2m: Remove p2m_altp2m_check stubs from unsupported architectu=
res
>     - Removes p2m_altp2m_check stubs from archs that don't support altp2m=
.
>   - x86/altp2m: Wrap altp2m-specific code in #ifdef CONFIG_ALTP2M
>     - Self-explanatory - based on Jans review suggestion
> - Small changes based on review:
>   - if ( v->domain->nr_altp2m =3D=3D 0 ) -> if ( !v->domain->nr_altp2m )
>   - removed unnecessary condition in p2m_teardown_altp2m
>   - Added ASSERT(!config->altp2m.nr) when CONFIG_ALTP2M=3Dn in domain_cre=
ate
>
> Changes since v8:
> - Removed 1st patch, which was already applied.
> - Removed Reviewed-by from "tools/xl: Add altp2m_count parameter" patch.
> - (No code changes)
>
> Changes since v7:
> - Fix condition in libxl_create.c that caused assertions in CI.
> - Removed incorrect mention of introduction of hvm_altp2m_supported() in =
commit
>   message of patch 0004.
> - Adjust comments in altp2m_is_eptp_valid().
> - Guard ALTP2M features with CONFIG_ALTP2M where appropriate. I made my b=
est to
>   ensure that the following configurations compile correctly:
>   * CONFIG_HVM=3Dn (CONFIG_ALTP2M=3Dn implied)
>   * CONFIG_HVM=3Dy CONFIG_ALTP2M=3Dn
>   * CONFIG_HVM=3Dy CONFIG_ALTP2M=3Dy
>   * Note: Besides taking inspiration from CONFIG_MEM_SHARING &
>     CONFIG_MEM_PAGING, the reason for guards instead of wrapper methods i=
s that
>     all ALTP2M features and fields became guarded by CONFIG_ALTP2M - ther=
efore,
>     lots of code inside ALTP2M blocks would be touching inexisting fields=
.
>
>     This could be solved by introducing wrapped functions for each ALTP2M
>     field, but I believe that would be overkill.
>
> Changes since v6:
> - Rebased on top of staging
> - Added missing Acks/Reviewed-bys where appropriate.
> - No changes in patches since v6, with the exception of 0004: xen: Make t=
he
>   maximum number of altp2m views configurable for x86... which was the on=
ly
>   patch that was left unacked/not reviewed
>   - In that patch, I made changes suggested by Jan - that is:
>     - Create altp2m_is_eptp_valid function and use it in places where
>       we don't control the index
>     - Fixed a nit: "Number of altp2ms to allocate." -> "... to permit."
>     - Cosmetic: moved altp2m_vcpu_idx() in altp2m.h up, so the order of
>       functions matches with the order in the #else block
>
> Changes since v5:
> - Reverted "Introduction of accessor functions for altp2m arrays and
>   refactoring the code to use them."
>   - Reason is minimizing the code changes, and save the code consistency.
>   - I've addressed (hopefully all) issues with long lines and mismatched
>     _nospec replacements mentioned in previous reviews.
> - Removed "struct domain *d" from altp2m_vcpu_initialise/destroy.
>
> Changes since v4:
> - Rebased on top of staging (applying Roger's changes).
> - Fix mixed tabs/spaces in xenctrl_stubs.c.
> - Add missing OCaml bindings for altp2m_opts.
> - Substitute altp2m_opts into an unnamed structure. (This is a preparatio=
n for
>   the next patch that will introduce the `nr` field.)
> - altp2m.opts is then shortened to uint16_t and a new field altp2m.nr is =
added -
>   also uint16_t. This value is then verified by libxl to not exceed the m=
aximum
>   uint16_t value.
>
>   This puts a hard limit to number of altp2m to 65535, which is enough, a=
t least
>   for the time being. Also, altp2m.opts currently uses only 2 bits. There=
fore
>   I believe this change is justified.
> - Introduction of accessor functions for altp2m arrays and refactoring th=
e code
>   to use them.
> - Added a check to arm/arch_sanitise_domain_config() to disallow creating
>   domains with altp2m.nr !=3D 0.
> - Added dummy hvm_altp2m_supported() to avoid build errors when CONFIG_HV=
M is
>   disabled.
> - Finally, expose altp2m_count to OCaml bindings (and verify both altp2m_=
opts
>   and altp2m_count fit uint16_t).
> - I also removed Christian Lindig from the Acked-by, since I think this c=
hange
>   is significant enough to require a re-review.
>
> Changes since v3:
> - Rebased on top of staging (some functions were moved to altp2m.c).
> - Re-added the array_index_nospec() where it was removed.
>
> Changes since v2:
> - Changed max_altp2m to nr_altp2m.
> - Moved arch-dependent check from xen/common/domain.c to xen/arch/x86/dom=
ain.c.
> - Replaced min(d->nr_altp2m, MAX_EPTP) occurences for just d->nr_altp2m.
> - Replaced array_index_nospec(altp2m_idx, ...) for just altp2m_idx.
> - Shortened long lines.
> - Removed unnecessary comments in altp2m_vcpu_initialise/destroy.
> - Moved nr_altp2m field after max_ fields in xen_domctl_createdomain.
> - Removed the commit that adjusted the initial allocation of pages from 2=
56
>   to 1024. This means that after these patches, technically, the nr_altp2=
m will
>   be capped to (256 - 1 - vcpus - MAX_NESTEDP2M) instead of MAX_EPTP (512=
).
>   Future work will be needed to fix this.
>
> Petr Bene=C5=A1 (6):
>   altp2m: Drop p2m_altp2m_check() stubs on non-x86, move prototype, and
>     guard uses
>   x86/altp2m: Wrap altp2m-specific code in #ifdef CONFIG_ALTP2M
>   xen: Make the maximum number of altp2m views configurable for x86
>   tools/libxl: Activate the altp2m_count feature
>   xen/x86: Disallow creating domains with altp2m enabled and altp2m.nr
>     =3D=3D 0
>   tools/ocaml: Add altp2m_count parameter
>
>  tools/libs/light/libxl_create.c     |  4 ++
>  tools/ocaml/libs/xc/xenctrl.ml      |  1 +
>  tools/ocaml/libs/xc/xenctrl.mli     |  1 +
>  tools/ocaml/libs/xc/xenctrl_stubs.c | 19 ++++++--
>  xen/arch/arm/domain.c               |  2 +-
>  xen/arch/arm/include/asm/p2m.h      |  6 ---
>  xen/arch/ppc/include/asm/p2m.h      |  5 --
>  xen/arch/riscv/include/asm/p2m.h    |  5 --
>  xen/arch/x86/domain.c               | 41 +++++++++++++---
>  xen/arch/x86/hvm/emulate.c          |  4 ++
>  xen/arch/x86/hvm/hvm.c              | 18 +++++++-
>  xen/arch/x86/hvm/monitor.c          |  2 +
>  xen/arch/x86/hvm/vmx/vmx.c          | 10 +++-
>  xen/arch/x86/include/asm/altp2m.h   | 28 +++++++++--
>  xen/arch/x86/include/asm/domain.h   | 11 +++--
>  xen/arch/x86/include/asm/hvm/hvm.h  |  6 +++
>  xen/arch/x86/include/asm/hvm/vcpu.h |  4 ++
>  xen/arch/x86/include/asm/p2m.h      | 43 +++++++++--------
>  xen/arch/x86/mm/altp2m.c            | 72 +++++++++++++++--------------
>  xen/arch/x86/mm/hap/hap.c           | 12 +++--
>  xen/arch/x86/mm/mem_access.c        | 28 +++++------
>  xen/arch/x86/mm/mem_sharing.c       |  4 +-
>  xen/arch/x86/mm/p2m-ept.c           | 11 +++--
>  xen/arch/x86/mm/p2m-pt.c            |  2 +
>  xen/arch/x86/mm/p2m.c               | 17 +++++--
>  xen/arch/x86/vm_event.c             |  2 +-
>  xen/common/domain.c                 |  6 +++
>  xen/common/vm_event.c               |  3 +-
>  xen/include/public/domctl.h         |  5 +-
>  xen/include/xen/p2m-common.h        |  3 ++
>  xen/include/xen/sched.h             |  4 ++
>  31 files changed, 261 insertions(+), 118 deletions(-)
>
> --
> 2.34.1
>


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From: =?UTF-8?Q?Petr_Bene=C5=A1?= 
Date: Wed, 20 Aug 2025 12:47:53 +0200
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Message-ID: 
Subject: Ping: [PATCH v4 0/3] hvmloader: add new SMBIOS tables (7,8,9,26,27,28)
To: Xen-devel 
Cc: Anthony PERARD , Jan Beulich , 
	Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
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On Wed, Jul 30, 2025 at 11:56=E2=80=AFAM Petr Bene=C5=A1  wrote:
>
> From: Petr Bene=C5=A1 
>
> Changes since v3:
> - Renamed offsetofend macro to offsetof_end.
>
> Changes since v2:
> - Added sizeof_field and offsetofend macros to common-macros.h.
> - Used offsetofend macro everywhere to make semantically sense.
> - Added BUILD_BUG_ON to ensure offsets are correct based on the SMBIOS
>   specification (with explanation in the comments).
> - Fixed commit message of the second patch to mention the new smbios_pt_c=
opy
>   function.
> - Fixed nits (empty lines, misplaced *).
> - Retained the original comment "Only present when passed in" + added it =
to
>   the new tables where applicable.
> - Replaced hardcoded offset for chassis_handle in smbios_type_2_init.
>
> Changes since v1:
> - Swapped the order of S-o-b in the last commit message.
>
> Resubmitting patch from Anton Belousov and addressing review comments
> from Jan: https://old-list-archives.xen.org/archives/html/xen-devel/2022-=
01/msg00725.html
>
> Original message:
> > SMBIOS tables like 7,8,9,26,27,28 are neccessary to prevent sandbox det=
ection
> > by malware using WMI-queries. New tables can be mapped to memory from b=
inary
> > file specified in "smbios_firmware" parameter of domain configuration.
> > If particular table is absent in binary file, then it will not be mappe=
d to
> > memory. This method works for Windows domains as tables 7,8,9,26,27,28 =
are not
> > critical for OS boot and runtime. Also if "smbios_firmware" parameter i=
s not
> > provided, these tables will be skipped in write_smbios_tables function.
>
> Further explanation:
> Some malware samples are known to check presence of various hardware comp=
onents
> (like CPU fan, CPU temperature sensor, etc.) by WMI queries. If these com=
ponents
> are not present, then malware can assume that it is running in a sandbox =
and
> will not execute its payload.
>
> This patch will allow security researchers to create a custom SMBIOS
> firmware binary file that contains these tables.
>
> Petr Bene=C5=A1 (3):
>   tools: add sizeof_field and offsetof_end macros
>   hvmloader: fix SMBIOS table length checks
>   hvmloader: add new SMBIOS tables (7, 8, 9, 26, 27, 28)
>
>  tools/firmware/hvmloader/smbios.c       | 290 ++++++++++++++++++------
>  tools/firmware/hvmloader/smbios_types.h | 109 +++++++--
>  tools/include/xen-tools/common-macros.h |   5 +
>  3 files changed, 317 insertions(+), 87 deletions(-)
>
> --
> 2.34.1
>


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Date: Wed, 20 Aug 2025 13:33:38 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Andrew Cooper 
Cc: xen-devel@lists.xenproject.org, Jan Beulich 
Subject: Re: [PATCH] x86/iommu: setup MMCFG ahead of IOMMU
Message-ID: 
References: <20250819171826.60700-1-roger.pau@citrix.com>
 <6852c430-155c-4530-8aa6-67a6e97ef6b3@citrix.com>
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On Tue, Aug 19, 2025 at 07:23:57PM +0100, Andrew Cooper wrote:
> On 19/08/2025 6:18 pm, Roger Pau Monne wrote:
> > Otherwise the PCI accesses to segments different than the first one done by
> > the IOMMU initialization code would silently fail by returning all ones.
> >
> > Introduce a new helper, called pci_setup(), and move both the creation of
> > PCI segment 0 internal data structures, plus the parsing of ACPI MMCFG
> > table to it.
> >
> > Signed-off-by: Roger Pau Monné 
> 
> And moving acpi_mmcfg_init() slightly earlier from acpi_boot_init() into
> pci_setup().
> 
> > diff --git a/xen/arch/x86/pci.c b/xen/arch/x86/pci.c
> > index 26bb7f6a3c3a..e75a29e851a7 100644
> > --- a/xen/arch/x86/pci.c
> > +++ b/xen/arch/x86/pci.c
> > @@ -139,6 +142,19 @@ int pci_sanitize_bar_memory(struct rangeset *r)
> >      return 0;
> >  }
> >  
> > +void __init pci_setup(void)
> > +{
> > +    /*
> > +     * Ahead of any ACPI table parsing make sure we have control structures
> > +     * for PCI segment 0.
> > +     */
> > +    if ( pci_add_segment(0) )
> > +        panic("Could not initialize PCI segment 0\n");
> > +
> > +    /* Parse ACPI MMCFG ahead of IOMMU, so accesses to segments > 0 is setup. */
> 
> "ahead of IOMMU" isn't helpful here because the relevant context is in
> the caller.  Instead, I'd just say:
> 
> /* Parse ACPI MMCFG to see if other segments are available. */

Sure.

> > +    acpi_mmcfg_init();
> > +}
> > +
> >  /*
> >   * Local variables:
> >   * mode: C
> > diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
> > index 6fb42c5a5f95..bd648323bfed 100644
> > --- a/xen/arch/x86/setup.c
> > +++ b/xen/arch/x86/setup.c
> > @@ -1938,11 +1938,10 @@ void asmlinkage __init noreturn __start_xen(void)
> >      setup_system_domains();
> >  
> >      /*
> > -     * Ahead of any ACPI table parsing make sure we have control structures
> > -     * for PCI segment 0.
> > +     * Initialize PCI (create segment 0, setup MMCFG access) ahead of IOMMU
> > +     * setup, as it requires access to the PCI config space.
> >       */
> 
> Again, this isn't terribly clear IMO.
> 
> "ahead of IOMMU setup, as the IOMMUs might not all live on segment 0." ?

It's not just IOMMUs, but for example on VT-d we also need to poke at
the config space of bridges, and when such bridges live in segment > 0
that results in garbage being returned.

I'm not sure acpi_iommu_init() accesses the IOMMU PCI device config
space, but it does at least access the config space of bridges in
order to detect hierarchy.  See how acpi_parse_dev_scope() performs
PCI reads.

What about using:

/*
 * Initialize PCI (create segment 0, setup MMCFG access) ahead of IOMMU
 * setup, as devices in segment > 0 must also be discoverable.
 */

Thanks, Roger.


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Date: Wed, 20 Aug 2025 12:37:51 +0100
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Subject: Re: [PATCH] x86/iommu: setup MMCFG ahead of IOMMU
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Cc: xen-devel@lists.xenproject.org, Jan Beulich 
References: <20250819171826.60700-1-roger.pau@citrix.com>
 <6852c430-155c-4530-8aa6-67a6e97ef6b3@citrix.com>
 
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On 20/08/2025 12:33 pm, Roger Pau Monné wrote:
> On Tue, Aug 19, 2025 at 07:23:57PM +0100, Andrew Cooper wrote:
>> On 19/08/2025 6:18 pm, Roger Pau Monne wrote:
>>> diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
>>> index 6fb42c5a5f95..bd648323bfed 100644
>>> --- a/xen/arch/x86/setup.c
>>> +++ b/xen/arch/x86/setup.c
>>> @@ -1938,11 +1938,10 @@ void asmlinkage __init noreturn __start_xen(void)
>>>      setup_system_domains();
>>>  
>>>      /*
>>> -     * Ahead of any ACPI table parsing make sure we have control structures
>>> -     * for PCI segment 0.
>>> +     * Initialize PCI (create segment 0, setup MMCFG access) ahead of IOMMU
>>> +     * setup, as it requires access to the PCI config space.
>>>       */
>> Again, this isn't terribly clear IMO.
>>
>> "ahead of IOMMU setup, as the IOMMUs might not all live on segment 0." ?
> It's not just IOMMUs, but for example on VT-d we also need to poke at
> the config space of bridges, and when such bridges live in segment > 0
> that results in garbage being returned.
>
> I'm not sure acpi_iommu_init() accesses the IOMMU PCI device config
> space, but it does at least access the config space of bridges in
> order to detect hierarchy.  See how acpi_parse_dev_scope() performs
> PCI reads.
>
> What about using:
>
> /*
>  * Initialize PCI (create segment 0, setup MMCFG access) ahead of IOMMU
>  * setup, as devices in segment > 0 must also be discoverable.
>  */

Yeah, that works.

With those comment adjustments, Reviewed-by: Andrew Cooper



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To: Jan Beulich ,
 "xen-devel@lists.xenproject.org" 
Cc: Julien Grall , Stefano Stabellini
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On 15/07/2025 7:33 am, Jan Beulich wrote:
> Other projects have long switched to xz and/or lzip.
>
> In the mktarball script, don't rely on the tar used supporting the -J
> (xz) or --lzip (lzip) options.
>
> Signed-off-by: Jan Beulich 
> ---
> Question (to the release technicians) is whether this would be adding
> undue overhead, primarily as a result of anything done outside of the
> build system.

I'm happy with this.

>
> It's unclear to me why we have git create a tarball, extract that, just
> to then make a tarball again (without any special options, like to
> override owner or timestamps;

That's because in c5be91eb8140 you deleted the intermediate step of
merging qemus


> in this context I notice that tarballs
> created by Andrew have file ownership of andrew/andrew, while ones made
> by Julien use root/root).

Ownership where exactly?  the tarball itself (which will be down to
accounts on downloads.xenproject.org) or the tarball contents itself?

>
> Without passing -9, I observe lzip to compress worse than xz; the win
> of passing -9 to xz isn't overly big anyway (about 100k, compared to
> about 250k with lzip).

As these are created once and downloaded many times, we should always do
max compression.  Even if it takes minutes extra to create, that's still
a win overall.

>
> lzip, unlike the other two tools, doesn't really show a progress
> indicator with -v. Merely having final statistics may make the use of
> the option here questionable.

I can't say I find any of the stats relevant.

> --- a/docs/process/xen-release-management.pandoc
> +++ b/docs/process/xen-release-management.pandoc
> @@ -274,10 +274,10 @@ Xen X.Y rcZ is tagged. You can check tha
>  https://xenbits.xen.org/git-http/xen.git X.Y.0-rcZ
>  
>  For your convenience there is also a tarball at:
> -https://downloads.xenproject.org/release/xen/X.Y.0-rcZ/xen-X.Y.0-rcZ.tar.gz
> +https://downloads.xenproject.org/release/xen/X.Y.0-rcZ/xen-X.Y.0-rcZ.tar.[glx]z
>  
>  And the signature is at:
> -https://downloads.xenproject.org/release/xen/X.Y.0-rcZ/xen-X.Y.0-rcZ.tar.gz.sig
> +https://downloads.xenproject.org/release/xen/X.Y.0-rcZ/xen-X.Y.0-rcZ.tar.[glx]z.sig
>  
>  Please send bug reports and test reports to xen-devel@lists.xenproject.org.
>  When sending bug reports, please CC relevant maintainers and me
> --- a/tools/misc/mktarball
> +++ b/tools/misc/mktarball
> @@ -31,4 +31,14 @@ git_archive_into $xen_root $tdir/xen-$de
>  
>  GZIP=-9v tar cz -f $xen_root/dist/xen-$desc.tar.gz -C $tdir xen-$desc
>  
> -echo "Source tarball in $xen_root/dist/xen-$desc.tar.gz"
> +if [ -n "$(command -v xz)" ]
> +then
> +  tar c -C $tdir xen-$desc | $(command -v xz) -v -9 >$xen_root/dist/xen-$desc.tar.xz
> +fi
> +
> +if [ -n "$(command -v lzip)" ]
> +then
> +  tar c -C $tdir xen-$desc | $(command -v lzip) -v -9 >$xen_root/dist/xen-$desc.tar.lz
> +fi
> +
> +echo "Source tarball in $xen_root/dist/xen-$desc".tar.[glx]z

If we're deciding to use multiple compressions, they want to not be
optional here.  I'd far rather have a reminder to install the package,
than for it to simply be omitted.

We don't want to be re-tar-ing now that the qemu's are gone, so I think
the structure wants to end up as:

git archive --format=tar HEAD > tmp.tar
gzip -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.gz &
zx -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.xz &
lzip -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.lz &
wait

Might as well use the multiple cores better...

~Andrew


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From: Mykyta Poturai 
To: "xen-devel@lists.xenproject.org" 
CC: Edward Pickup , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini , Bertrand
 Marquis , Volodymyr Babchuk
	, Luca Fancellu , Mykyta
 Poturai , Stewart Hildebrand
	
Subject: [PATCH v2 1/3] arm/pci: Add pci-scan boot argument
Thread-Topic: [PATCH v2 1/3] arm/pci: Add pci-scan boot argument
Thread-Index: AQHcEc3mM5cSdUcCDk+EahVSEKlf4g==
Date: Wed, 20 Aug 2025 12:28:14 +0000
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From: Edward Pickup 

This patch adds a Xen boot arguments that, if enabled, causes a call to
existing code to scan pci devices enumerated by the firmware.

This will be needed ahead of dom0less support for pci passthrough on
arm.

Signed-off-by: Luca Fancellu 
Signed-off-by: Mykyta Poturai 
---
(cherry picked from commit bce463e1588a45e1bfdf59fc0d5f88b16604e439 from
 the downstream branch poc/pci-passthrough from
 https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git)

v1->v2:
* remove is_pci_scan_enabled wrapper
* make pci_scan_enabled ro_after_init
* drop debug prints
* drop Edward's SOB

changes since cherry-pick:
* s/always_inline/inline/
* replace additional kconfig option with config DEBUG

Signed-off-by: Stewart Hildebrand 
---
 docs/misc/xen-command-line.pandoc  |  7 +++++++
 xen/arch/arm/include/asm/pci.h     |  3 +++
 xen/arch/arm/pci/pci-host-common.c |  1 +
 xen/arch/arm/pci/pci.c             | 24 ++++++++++++++++++++++--
 4 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line=
.pandoc
index a75b6c9301..762a1a4f5f 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -2059,6 +2059,13 @@ This option can be specified more than once (up to 8=
 times at present).
=20
 Flag to enable or disable support for PCI passthrough
=20
+### pci-scan (arm)
+> `=3D `
+
+> Default: `false`
+
+Flag to enable or disable Xen PCI scan at boot.
+
 ### pcid (x86)
 > `=3D  | xpti=3D`
=20
diff --git a/xen/arch/arm/include/asm/pci.h b/xen/arch/arm/include/asm/pci.=
h
index 08ffcd4438..7289f7688b 100644
--- a/xen/arch/arm/include/asm/pci.h
+++ b/xen/arch/arm/include/asm/pci.h
@@ -23,6 +23,7 @@
 #define pci_to_dev(pcidev) (&(pcidev)->arch.dev)
=20
 extern bool pci_passthrough_enabled;
+extern bool pci_scan_enabled;
=20
 struct rangeset;
=20
@@ -155,6 +156,8 @@ bool arch_pci_device_physdevop(void);
=20
 #else   /*!CONFIG_HAS_PCI*/
=20
+#define pci_scan_enabled false
+
 struct pci_dev;
=20
 static inline void arch_pci_init_pdev(struct pci_dev *pdev) {}
diff --git a/xen/arch/arm/pci/pci-host-common.c b/xen/arch/arm/pci/pci-host=
-common.c
index 487c545f3a..d3481b05eb 100644
--- a/xen/arch/arm/pci/pci-host-common.c
+++ b/xen/arch/arm/pci/pci-host-common.c
@@ -284,6 +284,7 @@ pci_host_common_probe(struct dt_device_node *dev,
     }
=20
     pci_add_host_bridge(bridge);
+    pci_add_segment(bridge->segment);
=20
     return bridge;
=20
diff --git a/xen/arch/arm/pci/pci.c b/xen/arch/arm/pci/pci.c
index beb1f971fa..1b34e17517 100644
--- a/xen/arch/arm/pci/pci.c
+++ b/xen/arch/arm/pci/pci.c
@@ -91,8 +91,14 @@ bool arch_pci_device_physdevop(void)
 bool __read_mostly pci_passthrough_enabled;
 boolean_param("pci-passthrough", pci_passthrough_enabled);
=20
+/* By default pci scan is disabled. */
+bool __ro_after_init pci_scan_enabled;
+boolean_param("pci-scan", pci_scan_enabled);
+
 static int __init pci_init(void)
 {
+    int ret;
+
     /*
      * Enable PCI passthrough when has been enabled explicitly
      * (pci-passthrough=3Don).
@@ -104,9 +110,23 @@ static int __init pci_init(void)
         panic("Could not initialize PCI segment 0\n");
=20
     if ( acpi_disabled )
-        return dt_pci_init();
+        ret =3D dt_pci_init();
     else
-        return acpi_pci_init();
+        ret =3D acpi_pci_init();
+
+    if ( ret < 0 )
+        return ret;
+
+    if ( pci_scan_enabled )
+    {
+        ret =3D scan_pci_devices();
+
+        if ( ret < 0 )
+            return ret;
+
+    }
+
+    return 0;
 }
 __initcall(pci_init);
=20
--=20
2.34.1


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From: Mykyta Poturai 
To: "xen-devel@lists.xenproject.org" 
CC: Luca Fancellu , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Andrew Cooper
	, Anthony PERARD , Jan
 Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, "Daniel P. Smith" ,
	Mykyta Poturai 
Subject: [PATCH v2 3/3] xen/pci: add discovered PCI device at boot
Thread-Topic: [PATCH v2 3/3] xen/pci: add discovered PCI device at boot
Thread-Index: AQHcEc3mKXITpUZcl0ea3L2+fX5U/Q==
Date: Wed, 20 Aug 2025 12:28:15 +0000
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From: Luca Fancellu 

In dom0less mode, there is no dom0 that can call PCI physdev ops to
register PCI devices to iommu, so it needs to be done by Xen.
pci_add_device requires some default domain, we don't have hwdom, and
the guests are not yet created during the PCI init phase, so use dom_io
as a temporary sentinel before devices are assigned to their target
domains.

Rename setup_hwdom_pci_devices to setup_pci_devices and add dom0less
handling to it.

In pci_add_device there is a call to xsm that doesn't consider the
requester of the function to be Xen itself, so add a check to skip
the call if the owner domain is dom_io, since it means the call is
coming directly from Xen.

Signed-off-by: Luca Fancellu 
Signed-off-by: Mykyta Poturai 
---
(cherry picked from commit eff51e50021b75f5a50533f7de681b2ce044f5bd from
 the downstream branch poc/pci-passthrough from
 https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git)

v1->v2:
* integrate add_discovered_pci_devices into existing routines
* better explain the need for dom_io
---
 xen/arch/arm/pci/pci.c                      |  1 +
 xen/drivers/passthrough/amd/pci_amd_iommu.c |  2 +-
 xen/drivers/passthrough/pci.c               | 42 ++++++++++++++-------
 xen/drivers/passthrough/vtd/iommu.c         |  2 +-
 xen/include/xen/pci.h                       |  5 +--
 5 files changed, 33 insertions(+), 19 deletions(-)

diff --git a/xen/arch/arm/pci/pci.c b/xen/arch/arm/pci/pci.c
index 1b34e17517..909fbdd694 100644
--- a/xen/arch/arm/pci/pci.c
+++ b/xen/arch/arm/pci/pci.c
@@ -124,6 +124,7 @@ static int __init pci_init(void)
         if ( ret < 0 )
             return ret;
=20
+        setup_pci_devices(dom_io, NULL);
     }
=20
     return 0;
diff --git a/xen/drivers/passthrough/amd/pci_amd_iommu.c b/xen/drivers/pass=
through/amd/pci_amd_iommu.c
index 3a14770855..f3a83a0ab7 100644
--- a/xen/drivers/passthrough/amd/pci_amd_iommu.c
+++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c
@@ -401,7 +401,7 @@ static void __hwdom_init cf_check amd_iommu_hwdom_init(=
struct domain *d)
=20
     /* Make sure workarounds are applied (if needed) before adding devices=
. */
     arch_iommu_hwdom_init(d);
-    setup_hwdom_pci_devices(d, amd_iommu_add_device);
+    setup_pci_devices(d, amd_iommu_add_device);
 }
=20
 static void amd_iommu_disable_domain_device(const struct domain *domain,
diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c
index 09b424d1b3..6ddc6811df 100644
--- a/xen/drivers/passthrough/pci.c
+++ b/xen/drivers/passthrough/pci.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include "ats.h"
+#include "xen/dom0less-build.h"
=20
 struct pci_seg {
     struct list_head alldevs_list;
@@ -676,9 +677,12 @@ int pci_add_device(uint16_t seg, uint8_t bus, uint8_t =
devfn,
     else
         type =3D "device";
=20
-    ret =3D xsm_resource_plug_pci(XSM_PRIV, (seg << 16) | (bus << 8) | dev=
fn);
-    if ( ret )
-        return ret;
+    if ( d !=3D dom_io )
+    {
+        ret =3D xsm_resource_plug_pci(XSM_PRIV, (seg << 16) | (bus << 8) |=
 devfn);
+        if ( ret )
+            return ret;
+    }
=20
     ret =3D -ENOMEM;
=20
@@ -1181,19 +1185,21 @@ int __init scan_pci_devices(void)
     return ret;
 }
=20
-struct setup_hwdom {
+struct setup_ctxt {
     struct domain *d;
     int (*handler)(uint8_t devfn, struct pci_dev *pdev);
 };
=20
-static void __hwdom_init setup_one_hwdom_device(const struct setup_hwdom *=
ctxt,
+static void __hwdom_init setup_one_pci_device(const struct setup_ctxt *ctx=
t,
                                                 struct pci_dev *pdev)
 {
     u8 devfn =3D pdev->devfn;
-    int err;
+    int err =3D 0;
=20
     do {
-        err =3D ctxt->handler(devfn, pdev);
+        if ( ctxt->handler )
+            err =3D ctxt->handler(devfn, pdev);
+
         if ( err )
         {
             printk(XENLOG_ERR "setup %pp for d%d failed (%d)\n",
@@ -1213,10 +1219,10 @@ static void __hwdom_init setup_one_hwdom_device(con=
st struct setup_hwdom *ctxt,
                ctxt->d->domain_id, err);
 }
=20
-static int __hwdom_init cf_check _setup_hwdom_pci_devices(
+static int __hwdom_init cf_check _setup_pci_devices(
     struct pci_seg *pseg, void *arg)
 {
-    struct setup_hwdom *ctxt =3D arg;
+    struct setup_ctxt *ctxt =3D arg;
     int bus, devfn;
=20
     for ( bus =3D 0; bus < 256; bus++ )
@@ -1229,18 +1235,26 @@ static int __hwdom_init cf_check _setup_hwdom_pci_d=
evices(
             if ( !pdev )
                 continue;
=20
+            if ( is_dom0less_mode() ) {
+                int ret =3D pci_add_device(pdev->seg, pdev->bus, pdev->dev=
fn, NULL,
+                                         NUMA_NO_NODE, ctxt->d);
+                if (ret)
+                    printk(XENLOG_ERR "Failed to add PCI device %pp: %d\n"=
, &pdev->sbdf, ret);
+                continue;
+            }
+
             if ( !pdev->domain )
             {
                 pdev->domain =3D ctxt->d;
                 write_lock(&ctxt->d->pci_lock);
                 list_add(&pdev->domain_list, &ctxt->d->pdev_list);
                 write_unlock(&ctxt->d->pci_lock);
-                setup_one_hwdom_device(ctxt, pdev);
+                setup_one_pci_device(ctxt, pdev);
             }
             else if ( pdev->domain =3D=3D dom_xen )
             {
                 pdev->domain =3D ctxt->d;
-                setup_one_hwdom_device(ctxt, pdev);
+                setup_one_pci_device(ctxt, pdev);
                 pdev->domain =3D dom_xen;
             }
             else if ( pdev->domain !=3D ctxt->d )
@@ -1266,13 +1280,13 @@ static int __hwdom_init cf_check _setup_hwdom_pci_d=
evices(
     return 0;
 }
=20
-void __hwdom_init setup_hwdom_pci_devices(
+void __hwdom_init setup_pci_devices(
     struct domain *d, int (*handler)(uint8_t devfn, struct pci_dev *pdev))
 {
-    struct setup_hwdom ctxt =3D { .d =3D d, .handler =3D handler };
+    struct setup_ctxt ctxt =3D { .d =3D d, .handler =3D handler };
=20
     pcidevs_lock();
-    pci_segments_iterate(_setup_hwdom_pci_devices, &ctxt);
+    pci_segments_iterate(_setup_pci_devices, &ctxt);
     pcidevs_unlock();
 }
=20
diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/=
vtd/iommu.c
index c55f02c97e..1096c16327 100644
--- a/xen/drivers/passthrough/vtd/iommu.c
+++ b/xen/drivers/passthrough/vtd/iommu.c
@@ -1451,7 +1451,7 @@ static void __hwdom_init cf_check intel_iommu_hwdom_i=
nit(struct domain *d)
 {
     struct acpi_drhd_unit *drhd;
=20
-    setup_hwdom_pci_devices(d, setup_hwdom_device);
+    setup_pci_devices(d, setup_hwdom_device);
     setup_hwdom_rmrr(d);
     /* Make sure workarounds are applied before enabling the IOMMU(s). */
     arch_iommu_hwdom_init(d);
diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h
index 89f3281b7c..61f69a8a1b 100644
--- a/xen/include/xen/pci.h
+++ b/xen/include/xen/pci.h
@@ -220,9 +220,8 @@ int scan_pci_devices(void);
 enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn);
 int find_upstream_bridge(u16 seg, u8 *bus, u8 *devfn, u8 *secbus);
=20
-void setup_hwdom_pci_devices(struct domain *d,
-                             int (*handler)(uint8_t devfn,
-                                            struct pci_dev *pdev));
+void setup_pci_devices(struct domain *d, int (*handler)(uint8_t devfn,
+                                                        struct pci_dev *pd=
ev));
 int pci_release_devices(struct domain *d);
 int pci_add_segment(u16 seg);
 const unsigned long *pci_get_ro_map(u16 seg);
--=20
2.34.1


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Subject: [PATCH v2 0/3] dom0less pci passthrough support on Arm part 1
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This series adds basic PCI device enumeration in Xen. This will allow us to=
 not
rely on Dom0 enumeration for supported controllers, which will enable PCI
passthrough for dom0less setups.

Enumeration is disabled by default and can be enabled with "pci-scan" cmdli=
ne
option. Discovered devices are added to Xen and assigned to dom_io by defau=
lt.

Edward Pickup (1):
  arm/pci: Add pci-scan boot argument

Luca Fancellu (2):
  xen/pci: modify pci_add_device to handle device add by Xen
  xen/pci: add discovered PCI device at boot

 docs/misc/xen-command-line.pandoc           |  7 ++
 xen/arch/arm/include/asm/pci.h              |  3 +
 xen/arch/arm/pci/pci-host-common.c          |  1 +
 xen/arch/arm/pci/pci.c                      | 25 +++++++-
 xen/arch/x86/physdev.c                      |  9 ++-
 xen/drivers/passthrough/amd/pci_amd_iommu.c |  2 +-
 xen/drivers/passthrough/pci.c               | 71 ++++++++++++++-------
 xen/drivers/passthrough/vtd/iommu.c         |  2 +-
 xen/drivers/pci/physdev.c                   |  3 +-
 xen/include/xen/pci.h                       | 10 +--
 10 files changed, 94 insertions(+), 39 deletions(-)

--=20
2.34.1


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From: Mykyta Poturai 
To: "xen-devel@lists.xenproject.org" 
CC: Luca Fancellu , Jan Beulich ,
	Andrew Cooper , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Anthony PERARD , Michal
 Orzel , Julien Grall , Stefano
 Stabellini , Mykyta Poturai 
Subject: [PATCH v2 2/3] xen/pci: modify pci_add_device to handle device add by
 Xen
Thread-Topic: [PATCH v2 2/3] xen/pci: modify pci_add_device to handle device
 add by Xen
Thread-Index: AQHcEc3mB6OQkCaDf06b+uo3Fz43YA==
Date: Wed, 20 Aug 2025 12:28:14 +0000
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From: Luca Fancellu 

Currently pci_add_device is called from hypercalls requested by Dom0
to add pci devices and when the device has no domain associated with
it, it is assumed that hardware_domain is the owner.

On the dom0less scenario, the enumeration is performed by the
firmware and Xen at boot time might want to assign some pci devices
to guests, so it has to firstly add the device and then assign it to
the final guest.

Modify pci_add_device to have the owner domain passed as a parameter
to the function, so that when it is called from the hypercall the
owner would be the caller domain, otherwise when Xen is calling it,
it would be another domain since hw domain could not be there
(dom0less guests without Dom0 use case).

Signed-off-by: Luca Fancellu 
Signed-off-by: Mykyta Poturai 
---
(cherry picked from commit f0c85d9043f7c9402e85b73361c8a13c683428ca from
 the downstream branch poc/pci-passthrough from
 https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git)

v1->v2:
* remove dom_io check
* fixup pci_add_device parameters
* use current->domain instead of hardware_domain

changes since cherry-pick:
* s/hardware_domain/d/ in some write_unlock calls in xen/drivers/passthroug=
h/pci.c
---
 xen/arch/x86/physdev.c        |  9 ++++-----
 xen/drivers/passthrough/pci.c | 29 +++++++++++++++++++----------
 xen/drivers/pci/physdev.c     |  3 ++-
 xen/include/xen/pci.h         |  5 +++--
 4 files changed, 28 insertions(+), 18 deletions(-)

diff --git a/xen/arch/x86/physdev.c b/xen/arch/x86/physdev.c
index 4dfa1c0191..04d179e81b 100644
--- a/xen/arch/x86/physdev.c
+++ b/xen/arch/x86/physdev.c
@@ -446,8 +446,8 @@ ret_t do_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(voi=
d) arg)
         if ( copy_from_guest(&manage_pci, arg, 1) !=3D 0 )
             break;
=20
-        ret =3D pci_add_device(0, manage_pci.bus, manage_pci.devfn,
-                             NULL, NUMA_NO_NODE);
+        ret =3D pci_add_device(0, manage_pci.bus, manage_pci.devfn, NULL,
+                             NUMA_NO_NODE, current->domain);
         break;
     }
=20
@@ -477,9 +477,8 @@ ret_t do_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(voi=
d) arg)
         pdev_info.is_virtfn =3D manage_pci_ext.is_virtfn;
         pdev_info.physfn.bus =3D manage_pci_ext.physfn.bus;
         pdev_info.physfn.devfn =3D manage_pci_ext.physfn.devfn;
-        ret =3D pci_add_device(0, manage_pci_ext.bus,
-                             manage_pci_ext.devfn,
-                             &pdev_info, NUMA_NO_NODE);
+        ret =3D pci_add_device(0, manage_pci_ext.bus, manage_pci_ext.devfn=
,
+                             &pdev_info, NUMA_NO_NODE, current->domain);
         break;
     }
=20
diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c
index 3edcfa8a04..09b424d1b3 100644
--- a/xen/drivers/passthrough/pci.c
+++ b/xen/drivers/passthrough/pci.c
@@ -654,8 +654,9 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned=
 int pos,
     return is64bits ? 2 : 1;
 }
=20
-int pci_add_device(u16 seg, u8 bus, u8 devfn,
-                   const struct pci_dev_info *info, nodeid_t node)
+int pci_add_device(uint16_t seg, uint8_t bus, uint8_t devfn,
+                   const struct pci_dev_info *info, nodeid_t node,
+                   struct domain *d)
 {
     struct pci_seg *pseg;
     struct pci_dev *pdev;
@@ -663,6 +664,9 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn,
     const char *type;
     int ret;
=20
+    if ( !d )
+        return -EINVAL;
+
     if ( !info )
         type =3D "device";
     else if ( info->is_virtfn )
@@ -767,9 +771,9 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn,
     ret =3D 0;
     if ( !pdev->domain )
     {
-        pdev->domain =3D hardware_domain;
-        write_lock(&hardware_domain->pci_lock);
-        list_add(&pdev->domain_list, &hardware_domain->pdev_list);
+        pdev->domain =3D d;
+        write_lock(&d->pci_lock);
+        list_add(&pdev->domain_list, &pdev->domain->pdev_list);
=20
         /*
          * For devices not discovered by Xen during boot, add vPCI handler=
s
@@ -779,25 +783,30 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn,
         if ( ret )
         {
             list_del(&pdev->domain_list);
-            write_unlock(&hardware_domain->pci_lock);
+            write_unlock(&d->pci_lock);
             pdev->domain =3D NULL;
             printk(XENLOG_ERR "Setup of vPCI failed: %d\n", ret);
             goto out;
         }
-        write_unlock(&hardware_domain->pci_lock);
+        write_unlock(&d->pci_lock);
         ret =3D iommu_add_device(pdev);
         if ( ret )
         {
-            write_lock(&hardware_domain->pci_lock);
+            write_lock(&d->pci_lock);
             vpci_deassign_device(pdev);
             list_del(&pdev->domain_list);
-            write_unlock(&hardware_domain->pci_lock);
+            write_unlock(&d->pci_lock);
             pdev->domain =3D NULL;
             goto out;
         }
     }
-    else
+    else if ( pdev->domain =3D=3D d )
         iommu_enable_device(pdev);
+    else
+    {
+        ret =3D -EINVAL;
+        goto out;
+    }
=20
     pci_enable_acs(pdev);
=20
diff --git a/xen/drivers/pci/physdev.c b/xen/drivers/pci/physdev.c
index d46501b884..cd3a36903b 100644
--- a/xen/drivers/pci/physdev.c
+++ b/xen/drivers/pci/physdev.c
@@ -50,7 +50,8 @@ ret_t pci_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void=
) arg)
         }
 #endif
=20
-        ret =3D pci_add_device(add.seg, add.bus, add.devfn, &pdev_info, no=
de);
+        ret =3D pci_add_device(add.seg, add.bus, add.devfn,
+                             &pdev_info, node, current->domain);
         break;
     }
=20
diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h
index 130c2a8c1a..89f3281b7c 100644
--- a/xen/include/xen/pci.h
+++ b/xen/include/xen/pci.h
@@ -226,8 +226,9 @@ void setup_hwdom_pci_devices(struct domain *d,
 int pci_release_devices(struct domain *d);
 int pci_add_segment(u16 seg);
 const unsigned long *pci_get_ro_map(u16 seg);
-int pci_add_device(u16 seg, u8 bus, u8 devfn,
-                   const struct pci_dev_info *info, nodeid_t node);
+int pci_add_device(uint16_t seg, uint8_t bus, uint8_t devfn,
+                   const struct pci_dev_info *info, nodeid_t node,
+                   struct domain *d);
 int pci_remove_device(u16 seg, u8 bus, u8 devfn);
 int pci_ro_device(int seg, int bus, int devfn);
 int pci_hide_device(unsigned int seg, unsigned int bus, unsigned int devfn=
);
--=20
2.34.1


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Message-ID: <29aa715a-f70e-4cb8-8708-dda4d9fb4d0b@citrix.com>
Date: Wed, 20 Aug 2025 13:39:06 +0100
MIME-Version: 1.0
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Subject: Re: [PATCH v4 1/3] tools: add sizeof_field and offsetof_end macros
To: =?UTF-8?Q?Petr_Bene=C5=A1?= ,
 xen-devel@lists.xenproject.org
Cc: Anthony PERARD 
References: 
 <8cfd773bd5cc9ecac25a4a92104483f07021c991.1753869323.git.w1benny@gmail.com>
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In-Reply-To: <8cfd773bd5cc9ecac25a4a92104483f07021c991.1753869323.git.w1benny@gmail.com>
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On 30/07/2025 10:56 am, Petr Beneš wrote:
> From: Petr Beneš 
>
> * `sizeof_field` returns the size of a specific struct member
> * `offsetof_end` returns the offset to the end of the member within the struct
>
> It will be useful in upcoming layout checks of SMBIOS structs.
>
> Signed-off-by: Petr Beneš 
> ---
>  tools/include/xen-tools/common-macros.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/tools/include/xen-tools/common-macros.h b/tools/include/xen-tools/common-macros.h
> index 0088208c2e..3899e06753 100644
> --- a/tools/include/xen-tools/common-macros.h
> +++ b/tools/include/xen-tools/common-macros.h
> @@ -83,6 +83,11 @@
>  #define __packed __attribute__((__packed__))
>  #endif
>  
> +#define sizeof_field(type, member) sizeof(((type *)NULL)->member)
> +
> +#define offsetof_end(type, member) \
> +    (offsetof(type, member) + sizeof_field(type, member))

In Xen, we have this called endof_field()  (although I realise doing
this post-dated your patch).

Please could you adjust, and send out a full series.  I see there were
some minor changes needed in patch 2.

Also, please add a final patch which adds to CHANGELOG.md in the root
directly.  You want a bullet point under Added/x86 about this.

~Andrew


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Nicola Vetrini
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 Stabellini , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: [PATCH] misra: add deviation for MISRA C Rule 18.3
Thread-Topic: [PATCH] misra: add deviation for MISRA C Rule 18.3
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Date: Wed, 20 Aug 2025 12:44:19 +0000
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MISRA C Rule 18.3 states:"The relational operators >, >=3D, < and <=3D shal=
l
not be applied to objects of pointer type except where they point into
the same object."

Comparisons in the 'find_text_region()' function are safe because linker
symbols '_stext' and '_etext' represent fixed virtual addresses within
the same '.text' region, and the function 'addr' argument is explicitly
compared to known valid memory bounds ('text_start' and 'text_end')
derived from these linker symbols:
    if ( (void *)addr >=3D iter->text_start &&
         (void *)addr <  iter->text_end )

Configure Eclair to suppress violation reports occured in the function
'find_text_region()'. Update 'deviations.rst' file accordingly.
No functional changes.

Signed-off-by: Dmytro Prokopchuk 
---
Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1993673043
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 6 ++++++
 docs/misra/deviations.rst                        | 8 ++++++++
 2 files changed, 14 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index 7f3fd35a33..32b596c9da 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -590,6 +590,12 @@ C99 Undefined Behaviour 45: Pointers that do not point=
 into, or just beyond, the
 -config=3DMC3A2.R18.2,reports+=3D{safe, "any_area(any_loc(any_exp(macro(^p=
age_to_mfn$))))"}
 -doc_end
=20
+-doc_begin=3D"Comparisons in the 'find_text_region()' function are safe be=
cause linker symbols '_stext' and '_etext' represent fixed
+virtual addresses within the same '.text' region, and the function 'addr' =
argument is explicitly compared to known valid memory
+bounds ('text_start' and 'text_end') derived from these linker symbols."
+-config=3DMC3A2.R18.3,reports+=3D{safe, "any_area(any_loc(file(^xen/common=
/virtual_region\\.c$))&&context(name(find_text_region)))"}
+-doc_end
+
 -doc_begin=3D"Flexible array members are deliberately used and XEN develop=
ers are aware of the dangers related to them:
 unexpected result when the structure is given as argument to a sizeof() op=
erator and the truncation in assignment between structures."
 -config=3DMC3A2.R18.7,reports+=3D{deliberate, "any()"}
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..a726fb22a8 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -586,6 +586,14 @@ Deviations related to MISRA C:2012 Rules:
        are safe.
      - Tagged as `safe` for ECLAIR.
=20
+   * - R18.3
+     - Comparisons in the 'find_text_region()' function are safe because
+       linker symbols '_stext' and '_etext' represent fixed virtual
+       addresses within the same '.text' region, and the function 'addr'
+       argument is explicitly compared to known valid memory bounds
+       ('text_start' and 'text_end') derived from these linker symbols.
+     - Tagged as `safe` for ECLAIR.
+
    * - R20.4
      - The override of the keyword \"inline\" in xen/compiler.h is present=
 so
        that section contents checks pass when the compiler chooses not to
--=20
2.43.0


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Date: Wed, 20 Aug 2025 15:03:11 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, Doug Goldstein ,
 Stefano Stabellini , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Jan Beulich , Julien
 Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
Subject: Re: [PATCH] misra: add deviation for MISRA C Rule 18.3
In-Reply-To: <901917945f704643e95842a773be9e8676f76d10.1755690681.git.dmytro_prokopchuk1@epam.com>
References: <901917945f704643e95842a773be9e8676f76d10.1755690681.git.dmytro_prokopchuk1@epam.com>
Message-ID: 
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On 2025-08-20 14:44, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 18.3 states:"The relational operators >, >=, < and <= 
> shall
> not be applied to objects of pointer type except where they point into
> the same object."
> 
> Comparisons in the 'find_text_region()' function are safe because 
> linker
> symbols '_stext' and '_etext' represent fixed virtual addresses within
> the same '.text' region, and the function 'addr' argument is explicitly
> compared to known valid memory bounds ('text_start' and 'text_end')
> derived from these linker symbols:
>     if ( (void *)addr >= iter->text_start &&
>          (void *)addr <  iter->text_end )
> 
> Configure Eclair to suppress violation reports occured in the function
> 'find_text_region()'. Update 'deviations.rst' file accordingly.
> No functional changes.
> 
> Signed-off-by: Dmytro Prokopchuk 

Reviewed-by: Nicola Vetrini 

with two NITs below:

> ---
> Test CI pipeline:
> https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1993673043
> ---
>  automation/eclair_analysis/ECLAIR/deviations.ecl | 6 ++++++
>  docs/misra/deviations.rst                        | 8 ++++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl 
> b/automation/eclair_analysis/ECLAIR/deviations.ecl
> index 7f3fd35a33..32b596c9da 100644
> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -590,6 +590,12 @@ C99 Undefined Behaviour 45: Pointers that do not 
> point into, or just beyond, the
>  -config=MC3A2.R18.2,reports+={safe, 
> "any_area(any_loc(any_exp(macro(^page_to_mfn$))))"}
>  -doc_end
> 
> +-doc_begin="Comparisons in the 'find_text_region()' function are safe 
> because linker symbols '_stext' and '_etext' represent fixed
> +virtual addresses within the same '.text' region, and the function 
> 'addr' argument is explicitly compared to known valid memory
> +bounds ('text_start' and 'text_end') derived from these linker 
> symbols."

Maybe ['text_start', 'text_end') here and below to emphasize that this 
is a range?

> +-config=MC3A2.R18.3,reports+={safe, 
> "any_area(any_loc(file(^xen/common/virtual_region\\.c$))&&context(name(find_text_region)))"}
> +-doc_end
> +
>  -doc_begin="Flexible array members are deliberately used and XEN 
> developers are aware of the dangers related to them:
>  unexpected result when the structure is given as argument to a 
> sizeof() operator and the truncation in assignment between structures."
>  -config=MC3A2.R18.7,reports+={deliberate, "any()"}
> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
> index 2119066531..a726fb22a8 100644
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -586,6 +586,14 @@ Deviations related to MISRA C:2012 Rules:
>         are safe.
>       - Tagged as `safe` for ECLAIR.
> 
> +   * - R18.3
> +     - Comparisons in the 'find_text_region()' function are safe 
> because
> +       linker symbols '_stext' and '_etext' represent fixed virtual
> +       addresses within the same '.text' region, and the function 
> 'addr'

s/function 'addr' argument/function parameter 'addr'/

> +       argument is explicitly compared to known valid memory bounds
> +       ('text_start' and 'text_end') derived from these linker 
> symbols.
> +     - Tagged as `safe` for ECLAIR.
> +
>     * - R20.4
>       - The override of the keyword \"inline\" in xen/compiler.h is 
> present so
>         that section contents checks pass when the compiler chooses not 
> to

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Wed, 20 Aug 2025 15:23:08 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Andrew Cooper 
Cc: xen-devel@lists.xenproject.org, Jan Beulich 
Subject: Re: [PATCH] x86/iommu: setup MMCFG ahead of IOMMU
Message-ID: 
References: <20250819171826.60700-1-roger.pau@citrix.com>
 <6852c430-155c-4530-8aa6-67a6e97ef6b3@citrix.com>
 
 <541c8586-b77b-478a-9dae-cde7884ee57d@citrix.com>
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On Wed, Aug 20, 2025 at 12:37:51PM +0100, Andrew Cooper wrote:
> On 20/08/2025 12:33 pm, Roger Pau Monné wrote:
> > On Tue, Aug 19, 2025 at 07:23:57PM +0100, Andrew Cooper wrote:
> >> On 19/08/2025 6:18 pm, Roger Pau Monne wrote:
> >>> diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
> >>> index 6fb42c5a5f95..bd648323bfed 100644
> >>> --- a/xen/arch/x86/setup.c
> >>> +++ b/xen/arch/x86/setup.c
> >>> @@ -1938,11 +1938,10 @@ void asmlinkage __init noreturn __start_xen(void)
> >>>      setup_system_domains();
> >>>  
> >>>      /*
> >>> -     * Ahead of any ACPI table parsing make sure we have control structures
> >>> -     * for PCI segment 0.
> >>> +     * Initialize PCI (create segment 0, setup MMCFG access) ahead of IOMMU
> >>> +     * setup, as it requires access to the PCI config space.
> >>>       */
> >> Again, this isn't terribly clear IMO.
> >>
> >> "ahead of IOMMU setup, as the IOMMUs might not all live on segment 0." ?
> > It's not just IOMMUs, but for example on VT-d we also need to poke at
> > the config space of bridges, and when such bridges live in segment > 0
> > that results in garbage being returned.
> >
> > I'm not sure acpi_iommu_init() accesses the IOMMU PCI device config
> > space, but it does at least access the config space of bridges in
> > order to detect hierarchy.  See how acpi_parse_dev_scope() performs
> > PCI reads.
> >
> > What about using:
> >
> > /*
> >  * Initialize PCI (create segment 0, setup MMCFG access) ahead of IOMMU
> >  * setup, as devices in segment > 0 must also be discoverable.
> >  */
> 
> Yeah, that works.
> 
> With those comment adjustments, Reviewed-by: Andrew Cooper
> 

Forgot to add it, this patch should have:

Fixes: 3950f2485bbc ('x86/x2APIC: defer probe until after IOMMU ACPI table parsing')

In the commit message.

Thanks, Roger.


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On 2025-08-20 06:46, Juergen Gross wrote:
> Avoid dereferencing NULL in introduce_domain() when called during
> live update.
> 
> Coverity ID: 1665111
> Fixes: f78895ad78c9 ("tools/xenstored: Read event channel from xenstored page")
> 
> Signed-off-by: Juergen Gross 

Reviewed-by: Jason Andryuk 

Thanks,
Jason


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MISRA C Rule 2.1 states: "A project shall not contain unreachable code."

The return statements in the 'read_file()' function is unreachable due
to function 'PrintErrMesg()' which is noreturn:
    PrintErrMesg(name, ret);
    /* not reached */
    return false;

This is deviated using a SAF-xx-safe comment (specified in the file
'docs/misra/safe.json').
No functional change.

Signed-off-by: Dmytro Prokopchuk 
---
Previous thread:
https://patchew.org/Xen/5944d87aae330246b7dab6eebd04d5d71a7d7e8f.1755608417=
.git.dmytro._5Fprokopchuk1@epam.com/

Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1994619131
---
 docs/misra/safe.json  | 8 ++++++++
 xen/common/efi/boot.c | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/docs/misra/safe.json b/docs/misra/safe.json
index 3584cb90c6..2b3178de2d 100644
--- a/docs/misra/safe.json
+++ b/docs/misra/safe.json
@@ -124,6 +124,14 @@
         },
         {
             "id": "SAF-15-safe",
+            "analyser": {
+                "eclair": "MC3A2.R2.1"
+            },
+            "name": "Rule 2.1: unreachable code",
+            "text": "This is a deliberate use of unreachable code. The ret=
urn statement is retained to improve code clarity and readability by explic=
itly specifying the intended behavior for a case if PrintErrMesg() was to r=
eturn."
+        },
+        {
+            "id": "SAF-16-safe",
             "analyser": {},
             "name": "Sentinel",
             "text": "Next ID to be used"
diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
index 50ff1d1bd2..860c41c8e7 100644
--- a/xen/common/efi/boot.c
+++ b/xen/common/efi/boot.c
@@ -852,7 +852,7 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle=
, CHAR16 *name,
     PrintErr(L" failed for ");
     PrintErrMesg(name, ret);
=20
-    /* not reached */
+    /* SAF-15-safe deliberately unreachable code */
     return false;
 }
=20
--=20
2.43.0


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Date: Wed, 20 Aug 2025 14:32:48 -0400
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Subject: Re: [PATCH 2/5] xen/vpci: make BAR mapping more resilient for the
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To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
CC: , ,
	
References: <20250814160358.95543-1-roger.pau@citrix.com>
 <20250814160358.95543-3-roger.pau@citrix.com>
 <269db2aa-9ca1-446b-98f7-60ea2386fc03@amd.com>
 
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On 8/18/25 03:42, Roger Pau Monné wrote:
> On Fri, Aug 15, 2025 at 02:53:35PM -0400, Stewart Hildebrand wrote:
>> On 8/14/25 12:03, Roger Pau Monne wrote:
>>> The logic in map_range() will bubble up failures to the upper layer, which
>>> will result in any remaining regions being skip, and for the non-hardware
>>> domain case the owner domain of the device would be destroyed.  However for
>>> the hardware domain the intent is to continue execution, hopping the
>>> failure to modify the p2m could be worked around by the hardware domain.
>>>
>>> To accomplish that in a better way, ignore failures and skip the range in
>>> that case, possibly continuing to map further ranges.
>>>
>>> Since the error path in vpci_process_pending() should only be used by domUs
>>> now, and it will unconditionally end up calling domain_crash(), simplify
>>> it: there's no need to cleanup if the domain will be destroyed.
>>>
>>> No functional change for domUs intended.
>>>
>>> Signed-off-by: Roger Pau Monné 
>>> ---
>>>  xen/drivers/vpci/header.c | 51 +++++++++++++++++++++------------------
>>>  1 file changed, 28 insertions(+), 23 deletions(-)
>>>
>>> diff --git a/xen/drivers/vpci/header.c b/xen/drivers/vpci/header.c
>>> index b9756b364300..1035dcca242d 100644
>>> --- a/xen/drivers/vpci/header.c
>>> +++ b/xen/drivers/vpci/header.c



>>> @@ -213,28 +224,22 @@ bool vpci_process_pending(struct vcpu *v)
>>>              return true;
>>>          }
>>>  
>>> -        if ( rc )
>>> +        if ( rc && !is_hardware_domain(v->domain) )
>>>          {
>>> -            spin_lock(&pdev->vpci->lock);
>>> -            /* Disable memory decoding unconditionally on failure. */
>>> -            modify_decoding(pdev, v->vpci.cmd & ~PCI_COMMAND_MEMORY,
>>> -                            false);
>>
>> This path could be taken for either map or unmap. Do we still want to disable
>> memory decoding in case of unmap?
> 
> Does it make an effective difference?  For the hardware domain we
> should never get here, and for domUs the domain will be destroyed, so
> disabling memory decoding is not helpful?

Since the domU will be destroyed, the PCI device will get assigned back to hwdom
or put into quarantine. In case of quarantine, it shouldn't matter. In case of
assignment back to hwdom, I think by keeping memory decoding enabled it could
potentially trigger additional p2m operations.

In any case, I don't have a strong opinion on disabling memory decoding vs not,
but I think the commit message ought to mention something about it.


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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: [PATCH] xen/dom0less: Clear xenstore page
Date: Wed, 20 Aug 2025 17:12:42 -0400
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C Xenstored was seen failing to map a domU's event channel.  Enhancing
Xen's error messages shows:
common/event_channel.c:427:d0v0 EVTCHNOP failure: d1, port 3267543746 error -22

Port 3267543746 is 0xc2c2c2c2 - SCRUB_PATTERN.

Xenstore expects a non-zero evtchn_port to be valid.  Explicitly zero
the page to avoid this.

Fixes: f78895ad78c9 ("tools/xenstored: Read event channel from xenstored page")
Signed-off-by: Jason Andryuk 
---
Tweaked stubdom & dom0less C xenstored pipeline success:
Test CI pipeline:
https://gitlab.com/xen-project/people/jandryuk-amd/xen/-/pipelines/1994879466

Example failure:
https://gitlab.com/xen-project/people/jandryuk-amd/xen/-/jobs/11084356847

Alternatively, a fixes could be:
Fixes: df2c03e2ebfe ("xen/arm: Alloc XenStore page for Dom0less DomUs from hypervisor")
If the page should have been zero from the start.

gitlab-ci uses oxenstored for most testings, so this isn't seen by
default.  I don't see this in local testing, so I guess I don't have
SCRUB_PATTERN writing enabled?
---
 xen/common/device-tree/dom0less-build.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c
index 6bb038111d..badc227031 100644
--- a/xen/common/device-tree/dom0less-build.c
+++ b/xen/common/device-tree/dom0less-build.c
@@ -600,6 +600,7 @@ static int __init alloc_xenstore_page(struct domain *d)
     d->arch.hvm.params[HVM_PARAM_STORE_PFN] = gfn_x(gfn);
 #endif
     interface = map_domain_page(mfn);
+    clear_page(interface);
     interface->connection = XENSTORE_RECONNECT;
     unmap_domain_page(interface);
 
-- 
2.50.1



From xen-devel-bounces@lists.xenproject.org Wed Aug 20 21:33:28 2025
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Date: Wed, 20 Aug 2025 22:33:16 +0100
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Subject: Re: [PATCH v16 1/4] xen/domain: unify domain ID allocation
Content-Language: en-GB
To: dmkhn@proton.me, xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com,
 michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
 dmukhin@ford.com, Julien Grall ,
 Alejandro Vallejo 
References: <20250812223024.2364749-1-dmukhin@ford.com>
 <20250812223024.2364749-2-dmukhin@ford.com>
From: Julien Grall 
In-Reply-To: <20250812223024.2364749-2-dmukhin@ford.com>
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Hi Denis,

On 12/08/2025 23:30, dmkhn@proton.me wrote:
> From: Denis Mukhin 
> 
> Currently, there are two different domain ID allocation implementations:
> 
>    1) Sequential IDs allocation in dom0less Arm code based on max_init_domid;
> 
>    2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
>       max_init_domid (both Arm and x86).
> 
> The domain ID allocation covers dom0 or late hwdom, predefined domains,
> post-boot domains, excluding Xen system domains (domid >=
> DOMID_FIRST_RESERVED).
> 
> It makes sense to have a common helper code for such task across architectures
> (Arm and x86) and between dom0less / toolstack domU allocation.
> 
> Note, fixing dependency on max_init_domid is out of scope of this patch.
> 
> Wrap the domain ID allocation as an arch-independent function domid_alloc() in
> new common/domid.c based on the bitmap.
> 
> Allocation algorithm:
> - If an explicit domain ID is provided, verify its availability and use it if
>    ID is not used;
> - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1],
>    starting from the last used ID.
>    Implementation guarantees that two consecutive calls will never return the
>    same ID. ID#0 is reserved for the first boot domain (currently, dom0) and
>    excluded from the allocation range.
> 
> Remove is_free_domid() helper as it is not needed now.
> 
> No functional change intended.
> 
> Signed-off-by: Denis Mukhin 
> Reviewed-by: Julien Grall 
 > Reviewed-by: Alejandro Vallejo 
 > ---> Changes since v15:
> - fixup for check after the first pass in the bitarray in domid_alloc()

This was a good catch from Jan. Has a unit-test been added for this issue?

Anyway, my reviewed-by holds.

Cheers,

-- 
Julien Grall



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Date: Wed, 20 Aug 2025 18:12:43 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Mykyta Poturai 
cc: "xen-devel@lists.xenproject.org" , 
    Oleksandr Tyshchenko , 
    Stefano Stabellini , Julien Grall , 
    Bertrand Marquis , 
    Michal Orzel , 
    Volodymyr Babchuk 
Subject: Re: [PATCH v2 3/3] iommu/ipmmu-vmsa: Implement basic PCIE-IPMMU OSID
 support
In-Reply-To: <8d0e16b6cb439000571ab6771a6c0e61627825ce.1752482857.git.mykyta_poturai@epam.com>
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On Mon, 14 Jul 2025, Mykyta Poturai wrote:
> From: Oleksandr Tyshchenko 
> 
> Program PCIE BDF-OSID assignment according to the S4_PCIe_IPMMU-OSID
> when adding PCI device to the IOMMU in ipmmu_add_device callback.
> This is needed for being able to assign PCI devices to different
> domains at the same time. Programmed OSID is emmited as sideband data on
> the AXI bus during PCI DMA transactions and then used by IPMMU to match
> the transaction to the corresponding uTLB.
> 
> Signed-off-by: Oleksandr Tyshchenko 
> Signed-off-by: Mykyta Poturai 

Acked-by: Stefano Stabellini 


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Date: Wed, 20 Aug 2025 18:14:40 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Mykyta Poturai 
cc: "xen-devel@lists.xenproject.org" , 
    Edward Pickup , 
    Andrew Cooper , 
    Anthony PERARD , 
    Michal Orzel , Jan Beulich , 
    Julien Grall , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Bertrand Marquis , 
    Volodymyr Babchuk , 
    Luca Fancellu , 
    Stewart Hildebrand 
Subject: Re: [PATCH v2 1/3] arm/pci: Add pci-scan boot argument
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On Wed, 20 Aug 2025, Mykyta Poturai wrote:
> From: Edward Pickup 
> 
> This patch adds a Xen boot arguments that, if enabled, causes a call to
> existing code to scan pci devices enumerated by the firmware.
> 
> This will be needed ahead of dom0less support for pci passthrough on
> arm.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Mykyta Poturai 

Acked-by: Stefano Stabellini 


> ---
> (cherry picked from commit bce463e1588a45e1bfdf59fc0d5f88b16604e439 from
>  the downstream branch poc/pci-passthrough from
>  https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git)
> 
> v1->v2:
> * remove is_pci_scan_enabled wrapper
> * make pci_scan_enabled ro_after_init
> * drop debug prints
> * drop Edward's SOB
> 
> changes since cherry-pick:
> * s/always_inline/inline/
> * replace additional kconfig option with config DEBUG
> 
> Signed-off-by: Stewart Hildebrand 
> ---
>  docs/misc/xen-command-line.pandoc  |  7 +++++++
>  xen/arch/arm/include/asm/pci.h     |  3 +++
>  xen/arch/arm/pci/pci-host-common.c |  1 +
>  xen/arch/arm/pci/pci.c             | 24 ++++++++++++++++++++++--
>  4 files changed, 33 insertions(+), 2 deletions(-)
> 
> diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
> index a75b6c9301..762a1a4f5f 100644
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -2059,6 +2059,13 @@ This option can be specified more than once (up to 8 times at present).
>  
>  Flag to enable or disable support for PCI passthrough
>  
> +### pci-scan (arm)
> +> `= `
> +
> +> Default: `false`
> +
> +Flag to enable or disable Xen PCI scan at boot.
> +
>  ### pcid (x86)
>  > `=  | xpti=`
>  
> diff --git a/xen/arch/arm/include/asm/pci.h b/xen/arch/arm/include/asm/pci.h
> index 08ffcd4438..7289f7688b 100644
> --- a/xen/arch/arm/include/asm/pci.h
> +++ b/xen/arch/arm/include/asm/pci.h
> @@ -23,6 +23,7 @@
>  #define pci_to_dev(pcidev) (&(pcidev)->arch.dev)
>  
>  extern bool pci_passthrough_enabled;
> +extern bool pci_scan_enabled;
>  
>  struct rangeset;
>  
> @@ -155,6 +156,8 @@ bool arch_pci_device_physdevop(void);
>  
>  #else   /*!CONFIG_HAS_PCI*/
>  
> +#define pci_scan_enabled false
> +
>  struct pci_dev;
>  
>  static inline void arch_pci_init_pdev(struct pci_dev *pdev) {}
> diff --git a/xen/arch/arm/pci/pci-host-common.c b/xen/arch/arm/pci/pci-host-common.c
> index 487c545f3a..d3481b05eb 100644
> --- a/xen/arch/arm/pci/pci-host-common.c
> +++ b/xen/arch/arm/pci/pci-host-common.c
> @@ -284,6 +284,7 @@ pci_host_common_probe(struct dt_device_node *dev,
>      }
>  
>      pci_add_host_bridge(bridge);
> +    pci_add_segment(bridge->segment);
>  
>      return bridge;
>  
> diff --git a/xen/arch/arm/pci/pci.c b/xen/arch/arm/pci/pci.c
> index beb1f971fa..1b34e17517 100644
> --- a/xen/arch/arm/pci/pci.c
> +++ b/xen/arch/arm/pci/pci.c
> @@ -91,8 +91,14 @@ bool arch_pci_device_physdevop(void)
>  bool __read_mostly pci_passthrough_enabled;
>  boolean_param("pci-passthrough", pci_passthrough_enabled);
>  
> +/* By default pci scan is disabled. */
> +bool __ro_after_init pci_scan_enabled;
> +boolean_param("pci-scan", pci_scan_enabled);
> +
>  static int __init pci_init(void)
>  {
> +    int ret;
> +
>      /*
>       * Enable PCI passthrough when has been enabled explicitly
>       * (pci-passthrough=on).
> @@ -104,9 +110,23 @@ static int __init pci_init(void)
>          panic("Could not initialize PCI segment 0\n");
>  
>      if ( acpi_disabled )
> -        return dt_pci_init();
> +        ret = dt_pci_init();
>      else
> -        return acpi_pci_init();
> +        ret = acpi_pci_init();
> +
> +    if ( ret < 0 )
> +        return ret;
> +
> +    if ( pci_scan_enabled )
> +    {
> +        ret = scan_pci_devices();
> +
> +        if ( ret < 0 )
> +            return ret;
> +
> +    }
> +
> +    return 0;
>  }
>  __initcall(pci_init);
>  
> -- 
> 2.34.1
> 


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Date: Wed, 20 Aug 2025 18:17:21 -0700 (PDT)
From: Stefano Stabellini 
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To: Mykyta Poturai 
cc: "xen-devel@lists.xenproject.org" , 
    Luca Fancellu , Jan Beulich , 
    Andrew Cooper , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Anthony PERARD , 
    Michal Orzel , Julien Grall , 
    Stefano Stabellini 
Subject: Re: [PATCH v2 2/3] xen/pci: modify pci_add_device to handle device
 add by Xen
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On Wed, 20 Aug 2025, Mykyta Poturai wrote:
> From: Luca Fancellu 
> 
> Currently pci_add_device is called from hypercalls requested by Dom0
> to add pci devices and when the device has no domain associated with
> it, it is assumed that hardware_domain is the owner.
> 
> On the dom0less scenario, the enumeration is performed by the
> firmware and Xen at boot time might want to assign some pci devices
> to guests, so it has to firstly add the device and then assign it to
> the final guest.
> 
> Modify pci_add_device to have the owner domain passed as a parameter
> to the function, so that when it is called from the hypercall the
> owner would be the caller domain, otherwise when Xen is calling it,
> it would be another domain since hw domain could not be there
> (dom0less guests without Dom0 use case).
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Mykyta Poturai 

Reviewed-by: Stefano Stabellini 



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From: Juergen Gross 
To: Jason Andryuk , xen-devel@lists.xenproject.org
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel 
Message-ID: <0cbd6cac-4745-4561-96e5-d3fec8dc7426@suse.com>
Subject: Re: [PATCH] xen/dom0less: Clear xenstore page
References: <20250820211242.116868-1-jason.andryuk@amd.com>
In-Reply-To: <20250820211242.116868-1-jason.andryuk@amd.com>

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On 19.08.2025 20:45, Andrew Cooper wrote:
> On 18/08/2025 8:57 am, Jan Beulich wrote:
>> --- a/xen/arch/x86/include/asm/mm.h
>> +++ b/xen/arch/x86/include/asm/mm.h
>> @@ -464,6 +464,16 @@ extern bool opt_pv_linear_pt;
>>      ASSERT(((_p)->count_info & PGC_count_mask) != 0);          \
>>      ASSERT(page_get_owner(_p) == (_d))
>>  
>> +#define RAM_TYPE_CONVENTIONAL 0x00000001
>> +#define RAM_TYPE_RESERVED     0x00000002
>> +#define RAM_TYPE_UNUSABLE     0x00000004
>> +#define RAM_TYPE_ACPI         0x00000008
>> +#define RAM_TYPE_UNKNOWN      0x00000010
>> +/* TRUE if the whole page at @mfn is of the requested RAM type(s) above. */
>> +bool page_is_ram_type(unsigned long mfn, unsigned long mem_type);
> 
> Making it x86-only is fine, but if you're changing the return type,
> mem_type can become shorter too.

Oh, indeed - done. Won't re-post just for this, though.

> Also, I'm struggling to convince myself that page_is_ram_type() is
> correct.  Even if it is correct, it is horribly inefficient, and we run
> this algorithm lots on boot.
> 
> Checking the type before the range is the backwards way of doing this,
> and it can be a binary search because we go out of our way to fix
> unsorted e820 maps.
> 
> Finally, acpi_memory_banned() shows that this really isn't the greatest
> API in the first place.  It's explicitly designed to take multiple
> inputs, but does the wrong thing for its' single caller wanting that
> behaviour.  I can't help but feel we'd be in a better position by
> removing this entirely and using plain E820 queries.

All valid remarks, but all to be taken care of separately imo.

Jan


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On 19.08.2025 21:45, Andrew Cooper wrote:
> On 19/08/2025 1:04 pm, Jan Beulich wrote:
>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/tsx.c
>>> +++ b/xen/arch/x86/tsx.c
>>> @@ -42,6 +42,8 @@ void tsx_init(void)
>>>  {
>>>      static bool __read_mostly once;
>>>  
>>> +    uint64_t val;
>>> +
>>>      /*
>> No real need for yet another newline, I would say.
> 
> Where?  Before?  that's separation of static and not.  After? that's
> separation of variables and code.  All as we do elsewhere.

The latter we do elsewhere too, sure. But separating statics from auto
variables we don't normally do, unless the set of declarations is rather
large.

Jan


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Subject: Re: [PATCH v16 1/4] xen/domain: unify domain ID allocation
To: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org,
 michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
 dmukhin@ford.com, Julien Grall ,
 Alejandro Vallejo ,
 xen-devel@lists.xenproject.org
References: <20250812223024.2364749-1-dmukhin@ford.com>
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On 20.08.2025 01:58, dmkhn@proton.me wrote:
> On Thu, Aug 14, 2025 at 09:11:11AM +0200, Jan Beulich wrote:
>> On 13.08.2025 00:30, dmkhn@proton.me wrote:
>>> From: Denis Mukhin 
>>>
>>> Currently, there are two different domain ID allocation implementations:
>>>
>>>   1) Sequential IDs allocation in dom0less Arm code based on max_init_domid;
>>>
>>>   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
>>>      max_init_domid (both Arm and x86).
>>>
>>> The domain ID allocation covers dom0 or late hwdom, predefined domains,
>>> post-boot domains, excluding Xen system domains (domid >=
>>> DOMID_FIRST_RESERVED).
>>>
>>> It makes sense to have a common helper code for such task across architectures
>>> (Arm and x86) and between dom0less / toolstack domU allocation.
>>>
>>> Note, fixing dependency on max_init_domid is out of scope of this patch.
>>>
>>> Wrap the domain ID allocation as an arch-independent function domid_alloc() in
>>> new common/domid.c based on the bitmap.
>>>
>>> Allocation algorithm:
>>> - If an explicit domain ID is provided, verify its availability and use it if
>>>   ID is not used;
>>> - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1],
>>>   starting from the last used ID.
>>>   Implementation guarantees that two consecutive calls will never return the
>>>   same ID. ID#0 is reserved for the first boot domain (currently, dom0) and
>>>   excluded from the allocation range.
>>>
>>> Remove is_free_domid() helper as it is not needed now.
>>>
>>> No functional change intended.
>>>
>>> Signed-off-by: Denis Mukhin 
>>> Reviewed-by: Julien Grall 
>>> Reviewed-by: Alejandro Vallejo 
>>> ---
>>> Changes since v15:
>>> - fixup for check after the first pass in the bitarray in domid_alloc()
>>> - trivial renaming for the local variable in domid_alloc()
>>> - kept Julien's R-b, added Alejandro's R-b
>>
>> Just to mention: My take is that this kind of a fix ought to invalidate all
>> earlier R-b. It's not just a cosmetic change, after all.
> 
> Sorry for the hiccup here, did not mean to overrule the review process.
> 
> My bold assumption was that in case of small fixups like this it is
> satisfactory to carry over previous acks.

Acks may be okay to keep, but imo R-b need dropping when an actual bug was
fixed. Irrespective of how severe the bug was.

> I asked (matrix) both Julien and Alejandro to re-review and confirm.

While good to ask, that's of limited use. It'll be impossible later on to
figure whether such a confirmation was given. Decisions (and acks and alike
effectively fall into that category) need to be on the list, to be able to
locate them later on.

Jan


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Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
To: "Penny, Zheng" 
Cc: "Huang, Ray" ,
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 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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 "Orzel, Michal" , Julien Grall ,
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On 20.08.2025 05:12, Penny, Zheng wrote:
> [Public]
> 
>> -----Original Message-----
>> From: Jan Beulich 
>> Sent: Monday, August 18, 2025 4:31 PM
>> To: Penny, Zheng ; Oleksii Kurochko
>> 
>> Cc: Huang, Ray ; Andrew Cooper
>> ; Roger Pau Monné ;
>> Anthony PERARD ; Orzel, Michal
>> ; Julien Grall ; Stefano Stabellini
>> ; xen-devel@lists.xenproject.org
>> Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
>>
>> On 15.08.2025 12:27, Penny Zheng wrote:
>>> In order to fix CI error of a randconfig picking both
>>> PV_SHIM_EXCLUSIVE=y and HVM=y results in hvm.c being built, but
>>> domctl.c not being built, which leaves a few functions, like
>>> domctl_lock_acquire/release() undefined, causing linking to fail.
>>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE
>>> Makefile /hypercall-defs section, with this adjustment, we also need
>>> to release redundant vnuma_destroy() stub definition from
>>> PV_SHIM_EXCLUSIVE guardian, to not break compilation Above change will
>>> leave dead code in the shim binary temporarily and will be fixed with
>>> the introduction of domctl-op wrapping.
>>
>> Well, "temporarily" is now getting interesting. While v1 of "Introduce
>> CONFIG_DOMCTL" was submitted in time to still be eligible for taking into 4.21,
>> that - as indicated elsewhere - is moving us further in an unwanted direction. Hence
>> I'm not sure this can even be counted as an in-time submission. Plus it looks to be
>> pretty extensive re-work in some areas.
>> Hence I'm somewhat weary as to 4.21 here. IOW question, mainly to Oleksii, is
>> whether to
>> 1) strive to complete that work in time (and hence take the patch here),
>> 2) take the patch here, accepting the size regression for the shim, or
>> 3) revert what has caused the randconfig issues, and retry the effort in
>>    4.22.
>>
>>> Fixes: 568f806cba4c ("xen/x86: remove "depends on
>>> !PV_SHIM_EXCLUSIVE"")
>>> Reported-by: Jan Beulich 
>>> Signed-off-by: Penny Zheng 
>>
>> My earlier question (when the patch still was part of a series) sadly has remained
>> unanswered: You've run this through a full round of testing this time?
> 
> Sorry, missed that, yes, it has been tested with both default defconfig and allyesconfig.

I'm sorry if my request was unclear, but with "full round of testing" I in particular
meant a full CI pipeline, plus (given the issue that's being fixed) some extra
randconfig testing.

Jan


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Subject: Re: [PATCH] releases: use newer compression methods for tarballs
To: Andrew Cooper 
Cc: Julien Grall , Stefano Stabellini
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On 20.08.2025 14:15, Andrew Cooper wrote:
> On 15/07/2025 7:33 am, Jan Beulich wrote:
>> It's unclear to me why we have git create a tarball, extract that, just
>> to then make a tarball again (without any special options, like to
>> override owner or timestamps;
> 
> That's because in c5be91eb8140 you deleted the intermediate step of
> merging qemus

Hmm, perhaps - I'm generally trying to keep the size of such changes down,
when working in an area I'm not overly familiar with.

>> in this context I notice that tarballs
>> created by Andrew have file ownership of andrew/andrew, while ones made
>> by Julien use root/root).
> 
> Ownership where exactly?  the tarball itself (which will be down to
> accounts on downloads.xenproject.org) or the tarball contents itself?

tarball contents.

>> lzip, unlike the other two tools, doesn't really show a progress
>> indicator with -v. Merely having final statistics may make the use of
>> the option here questionable.
> 
> I can't say I find any of the stats relevant.

Happy to drop the v options.

>> --- a/tools/misc/mktarball
>> +++ b/tools/misc/mktarball
>> @@ -31,4 +31,14 @@ git_archive_into $xen_root $tdir/xen-$de
>>  
>>  GZIP=-9v tar cz -f $xen_root/dist/xen-$desc.tar.gz -C $tdir xen-$desc
>>  
>> -echo "Source tarball in $xen_root/dist/xen-$desc.tar.gz"
>> +if [ -n "$(command -v xz)" ]
>> +then
>> +  tar c -C $tdir xen-$desc | $(command -v xz) -v -9 >$xen_root/dist/xen-$desc.tar.xz
>> +fi
>> +
>> +if [ -n "$(command -v lzip)" ]
>> +then
>> +  tar c -C $tdir xen-$desc | $(command -v lzip) -v -9 >$xen_root/dist/xen-$desc.tar.lz
>> +fi
>> +
>> +echo "Source tarball in $xen_root/dist/xen-$desc".tar.[glx]z
> 
> If we're deciding to use multiple compressions, they want to not be
> optional here.  I'd far rather have a reminder to install the package,
> than for it to simply be omitted.
> 
> We don't want to be re-tar-ing now that the qemu's are gone, so I think
> the structure wants to end up as:
> 
> git archive --format=tar HEAD > tmp.tar
> gzip -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.gz &
> zx -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.xz &
> lzip -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.lz &
> wait
> 
> Might as well use the multiple cores better...

I, too, was thinking of that. Yet as per above, when fiddling with code I'm
not overly familiar with, I try to limit the amount of change done. As you
ask for a bigger change, I can certainly do so.

Jan


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Subject: Re: [PATCH v3 9/9] CHANGELOG.md: add xenstorepvh-stubdom live update
To: Juergen Gross , xen-devel@lists.xenproject.org
Cc: Community Manager 
References: <20250730122305.4050-1-jgross@suse.com>
 <20250730122305.4050-10-jgross@suse.com>
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From: Oleksii Kurochko 
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On 8/20/25 8:06 AM, Juergen Gross wrote:
> Ping?
>
> On 30.07.25 14:23, Juergen Gross wrote:
>> Signed-off-by: Juergen Gross 
>> ---
>> V2:
>> - new patch
>> ---
>>   CHANGELOG.md | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/CHANGELOG.md b/CHANGELOG.md
>> index 5f31ca08fe..d118bb1c8c 100644
>> --- a/CHANGELOG.md
>> +++ b/CHANGELOG.md
>> @@ -26,6 +26,7 @@ The format is based on [Keep a 
>> Changelog](https://keepachangelog.com/en/1.0.0/)
>>      - Support PCI passthrough for HVM domUs when dom0 is PVH (note 
>> SR-IOV
>>        capability usage is not yet supported on PVH dom0).
>>      - Smoke tests for the FreeBSD Xen builds in Cirrus CI.
>> +   - PVH xenstore-stubdom now supports Live Update.

LGTM: Acked-by: Oleksii Kurochko

Thanks.

~ Oleksii

>>      - On Arm:
>>       - Ability to enable stack protector
>
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    On 8/20/25 8:06 AM, Juergen Gross
      wrote:
    
    
    
    
    Ping?
      
    
      
    
      On 30.07.25 14:23, Juergen Gross wrote:
      
    
      
    Signed-off-by: Juergen Gross
        <jgross@suse.com>
        
    
        ---
        
    
        V2:
        
    
        - new patch
        
    
        ---
        
    
          CHANGELOG.md | 1 +
        
    
          1 file changed, 1 insertion(+)
        
    
        
    
        diff --git a/CHANGELOG.md b/CHANGELOG.md
        
    
        index 5f31ca08fe..d118bb1c8c 100644
        
    
        --- a/CHANGELOG.md
        
    
        +++ b/CHANGELOG.md
        
    
        @@ -26,6 +26,7 @@ The format is based on [Keep a
        Changelog](https://keepachangelog.com/en/1.0.0/)
        
    
             - Support PCI passthrough for HVM domUs when dom0 is PVH
        (note SR-IOV
        
    
               capability usage is not yet supported on PVH dom0).
        
    
             - Smoke tests for the FreeBSD Xen builds in Cirrus CI.
        
    
        +   - PVH xenstore-stubdom now supports Live Update.
        
    
      
    
    
    
    
    LGTM: Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Thanks.

~ Oleksii

    
    
    
      
         - On Arm:
        
    
              - Ability to enable stack protector
        
    
      
    
      
    
    
    
  


--------------uR5ghdodlNzVWntO1WGvf6e0--


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On 20.08.2025 12:47, Petr Beneš wrote:
> On Thu, Jul 31, 2025 at 11:28 AM Petr Beneš  wrote:
>>
>> From: Petr Beneš 
>>
>> This series introduces the ability to configure the maximum number of altp2m
>> tables during domain creation. Previously, the limits were hardcoded to a
>> maximum of 10. This change allows for greater flexibility in environments that
>> require more or fewer altp2m views.
>>
>> This enhancement is particularly relevant for users leveraging Xen's features
>> for virtual machine introspection.

One remark: Besides having added the Ping: prefix in the subject, there's no
new content here. You also sent the email To: the list. It thus remains
unclear what your pinging for, as you have collected some tag(s) already. It
generally helps if you make clear whom you're addressing with what expectation.
(Things may be different if for a patch / series you didn't have any response
at all.)

Jan


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On 19.08.2025 20:55, Dmytro Prokopchuk1 wrote:
> Rule 11.1 states as following: "Conversions shall not be performed
> between a pointer to a function and any other type."
> 
> The conversion from unsigned long or (void *) to a function pointer
> is safe in Xen because the architectures it supports (e.g., x86 and
> ARM) guarantee compatible representations between these types.

I think we need to be as precise as possible here. The architectures
guarantee nothing, they only offer necessary fundamentals. In the
Windows x86 ABI, for example, you can't convert pointers to/from longs
without losing data. What we build upon is what respective ABIs say,
possibly in combination of implementation specifics left to compilers.

> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -370,6 +370,16 @@ Deviations related to MISRA C:2012 Rules:
>         to store it.
>       - Tagged as `safe` for ECLAIR.
>  
> +   * - R11.1
> +     - The conversion from unsigned long or (void \*) to a function pointer does
> +       not lose any information or violate type safety assumptions if unsigned
> +       long or (void \*) type is guaranteed to be the same bit size as a
> +       function pointer. This ensures that the function pointer can be fully
> +       represented without truncation or corruption. The macro BUILD_BUG_ON is
> +       integrated into xen/common/version.c to confirm conversion compatibility
> +       across all target platforms.
> +     - Tagged as `safe` for ECLAIR.

Why the escaping of * here, when ...

> --- a/docs/misra/rules.rst
> +++ b/docs/misra/rules.rst
> @@ -431,7 +431,13 @@ maintainers if you want to suggest a change.
>       - All conversions to integer types are permitted if the destination
>         type has enough bits to hold the entire value. Conversions to bool
>         and void* are permitted. Conversions from 'void noreturn (*)(...)'
> -       to 'void (*)(...)' are permitted.
> +       to 'void (*)(...)' are permitted. Conversions from unsigned long or
> +       (void \*) to a function pointer are permitted if the source type has
> +       enough bits to restore function pointer without truncation or corruption.
> +       Example::
> +
> +           unsigned long func_addr = (unsigned long)&some_function;
> +           void (*restored_func)(void) = (void (*)(void))func_addr;

... context here suggests they work fine un-escaped, and you even add some un-
escaped instances as well. Perhaps I'm simply unaware of some peculiarity?

Jan


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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
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	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann 
Subject: [PATCH v6 04/25] drm/gem-shmem: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:11 +0200
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Tomi Valkeinen 
---
 drivers/gpu/drm/drm_gem_shmem_helper.c | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c
index 5d1349c34afd..b90096ad82d8 100644
--- a/drivers/gpu/drm/drm_gem_shmem_helper.c
+++ b/drivers/gpu/drm/drm_gem_shmem_helper.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -518,18 +519,11 @@ EXPORT_SYMBOL_GPL(drm_gem_shmem_purge_locked);
 int drm_gem_shmem_dumb_create(struct drm_file *file, struct drm_device *dev,
 			      struct drm_mode_create_dumb *args)
 {
-	u32 min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+	int ret;
 
-	if (!args->pitch || !args->size) {
-		args->pitch = min_pitch;
-		args->size = PAGE_ALIGN(args->pitch * args->height);
-	} else {
-		/* ensure sane minimum values */
-		if (args->pitch < min_pitch)
-			args->pitch = min_pitch;
-		if (args->size < args->pitch * args->height)
-			args->size = PAGE_ALIGN(args->pitch * args->height);
-	}
+	ret = drm_mode_size_dumb(dev, args, SZ_8, 0);
+	if (ret)
+		return ret;
 
 	return drm_gem_shmem_create_with_handle(file, dev, args->size, &args->handle);
 }
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
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	linux-renesas-soc@vger.kernel.org,
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	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann 
Subject: [PATCH v6 01/25] drm/dumb-buffers: Sanitize output on errors
Date: Thu, 21 Aug 2025 10:17:08 +0200
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The ioctls MODE_CREATE_DUMB and MODE_MAP_DUMB return results into a
memory buffer supplied by user space. On errors, it is possible that
intermediate values are being returned. The exact semantics depends
on the DRM driver's implementation of these ioctls. Although this is
most-likely not a security problem in practice, avoid any uncertainty
by clearing the memory to 0 on errors.

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Tomi Valkeinen 
---
 drivers/gpu/drm/drm_dumb_buffers.c | 40 ++++++++++++++++++++++--------
 1 file changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/drm_dumb_buffers.c b/drivers/gpu/drm/drm_dumb_buffers.c
index 70032bba1c97..9916aaf5b3f2 100644
--- a/drivers/gpu/drm/drm_dumb_buffers.c
+++ b/drivers/gpu/drm/drm_dumb_buffers.c
@@ -99,7 +99,30 @@ int drm_mode_create_dumb(struct drm_device *dev,
 int drm_mode_create_dumb_ioctl(struct drm_device *dev,
 			       void *data, struct drm_file *file_priv)
 {
-	return drm_mode_create_dumb(dev, data, file_priv);
+	struct drm_mode_create_dumb *args = data;
+	int err;
+
+	err = drm_mode_create_dumb(dev, args, file_priv);
+	if (err) {
+		args->handle = 0;
+		args->pitch = 0;
+		args->size = 0;
+	}
+	return err;
+}
+
+static int drm_mode_mmap_dumb(struct drm_device *dev, struct drm_mode_map_dumb *args,
+			      struct drm_file *file_priv)
+{
+	if (!dev->driver->dumb_create)
+		return -ENOSYS;
+
+	if (dev->driver->dumb_map_offset)
+		return dev->driver->dumb_map_offset(file_priv, dev, args->handle,
+						    &args->offset);
+	else
+		return drm_gem_dumb_map_offset(file_priv, dev, args->handle,
+					       &args->offset);
 }
 
 /**
@@ -120,17 +143,12 @@ int drm_mode_mmap_dumb_ioctl(struct drm_device *dev,
 			     void *data, struct drm_file *file_priv)
 {
 	struct drm_mode_map_dumb *args = data;
+	int err;
 
-	if (!dev->driver->dumb_create)
-		return -ENOSYS;
-
-	if (dev->driver->dumb_map_offset)
-		return dev->driver->dumb_map_offset(file_priv, dev,
-						    args->handle,
-						    &args->offset);
-	else
-		return drm_gem_dumb_map_offset(file_priv, dev, args->handle,
-					       &args->offset);
+	err = drm_mode_mmap_dumb(dev, args, file_priv);
+	if (err)
+		args->offset = 0;
+	return err;
 }
 
 int drm_mode_destroy_dumb(struct drm_device *dev, u32 handle,
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
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	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann 
Subject: [PATCH v6 05/25] drm/gem-vram: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:12 +0200
Message-ID: <20250821081918.79786-6-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Inline code from drm_gem_vram_fill_create_dumb() without
the existing size computation. Align the pitch to a multiple of 8.

Only hibmc and vboxvideo use gem-vram. Hibmc invokes the call to
drm_gem_vram_fill_create_dumb() directly and is therefore not affected.

Signed-off-by: Thomas Zimmermann 
---
 drivers/gpu/drm/drm_gem_vram_helper.c | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c
index b04cde4a60e7..dd4537bf63dc 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -545,10 +546,31 @@ int drm_gem_vram_driver_dumb_create(struct drm_file *file,
 				    struct drm_device *dev,
 				    struct drm_mode_create_dumb *args)
 {
+	struct drm_gem_vram_object *gbo;
+	int ret;
+
 	if (WARN_ONCE(!dev->vram_mm, "VRAM MM not initialized"))
 		return -EINVAL;
 
-	return drm_gem_vram_fill_create_dumb(file, dev, 0, 0, args);
+	ret = drm_mode_size_dumb(dev, args, SZ_8, 0);
+	if (ret)
+		return ret;
+
+	gbo = drm_gem_vram_create(dev, args->size, 0);
+	if (IS_ERR(gbo))
+		return PTR_ERR(gbo);
+
+	ret = drm_gem_handle_create(file, &gbo->bo.base, &args->handle);
+	if (ret)
+		goto err_drm_gem_object_put;
+
+	drm_gem_object_put(&gbo->bo.base);
+
+	return 0;
+
+err_drm_gem_object_put:
+	drm_gem_object_put(&gbo->bo.base);
+	return ret;
 }
 EXPORT_SYMBOL(drm_gem_vram_driver_dumb_create);
 
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
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	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann 
Subject: [PATCH v6 03/25] drm/gem-dma: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:10 +0200
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.

Push the current calculation into the only direct caller imx. Imx's
hardware requires the framebuffer width to be aligned to 8. The
driver's current approach is actually incorrect, as it only guarantees
this implicitly and requires bpp to be a multiple of 8 already. A
later commit will fix this problem by aligning the scanline pitch
such that an aligned width still fits into each scanline's memory.

A number of other drivers are build on top of gem-dma helpers and
implement their own dumb-buffer allocation. These drivers invoke
drm_gem_dma_dumb_create_internal(), which is not affected by this
commit.

v5:
- avoid reset of arguments (Tomi)

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Tomi Valkeinen 
---
 drivers/gpu/drm/drm_gem_dma_helper.c     | 7 +++++--
 drivers/gpu/drm/imx/ipuv3/imx-drm-core.c | 4 +++-
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem_dma_helper.c b/drivers/gpu/drm/drm_gem_dma_helper.c
index 4f0320df858f..ab1a70b1d6f1 100644
--- a/drivers/gpu/drm/drm_gem_dma_helper.c
+++ b/drivers/gpu/drm/drm_gem_dma_helper.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -304,9 +305,11 @@ int drm_gem_dma_dumb_create(struct drm_file *file_priv,
 			    struct drm_mode_create_dumb *args)
 {
 	struct drm_gem_dma_object *dma_obj;
+	int ret;
 
-	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
-	args->size = args->pitch * args->height;
+	ret = drm_mode_size_dumb(drm, args, SZ_8, 0);
+	if (ret)
+		return ret;
 
 	dma_obj = drm_gem_dma_create_with_handle(file_priv, drm, args->size,
 						 &args->handle);
diff --git a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
index ec5fd9a01f1e..af4a30311e18 100644
--- a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
@@ -145,8 +145,10 @@ static int imx_drm_dumb_create(struct drm_file *file_priv,
 	int ret;
 
 	args->width = ALIGN(width, 8);
+	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+	args->size = args->pitch * args->height;
 
-	ret = drm_gem_dma_dumb_create(file_priv, drm, args);
+	ret = drm_gem_dma_dumb_create_internal(file_priv, drm, args);
 	if (ret)
 		return ret;
 
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann 
Subject: [PATCH v6 02/25] drm/dumb-buffers: Provide helper to set pitch and size
Date: Thu, 21 Aug 2025 10:17:09 +0200
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Add drm_modes_size_dumb(), a helper to calculate the dumb-buffer
scanline pitch and allocation size. Implementations of struct
drm_driver.dumb_create can call the new helper for their size
computations.

There is currently quite a bit of code duplication among DRM's
memory managers. Each calculates scanline pitch and buffer size
from the given arguments, but the implementations are inconsistent
in how they treat alignment and format support. Later patches will
unify this code on top of drm_mode_size_dumb() as much as possible.

drm_mode_size_dumb() uses existing 4CC format helpers to interpret
the given color mode. This makes the dumb-buffer interface behave
similar the kernel's video= parameter. Current per-driver implementations
again likely have subtle differences or bugs in how they support color
modes.

The dumb-buffer UAPI is only specified for known color modes. These
values describe linear, single-plane RGB color formats or legacy index
formats. Other values should not be specified. But some user space
still does. So for unknown color modes, there are a number of known
exceptions for which drm_mode_size_dumb() calculates the pitch from
the bpp value, as before. All other values work the same but print
an error.

v6:
- document additional use cases for DUMB_CREATE2 in TODO list (Tomi)
- fix typos in documentation (Tomi)
v5:
- check for overflows with check_mul_overflow() (Tomi)
v4:
- use %u conversion specifier (Geert)
- list DRM_FORMAT_Dn in UAPI docs (Geert)
- avoid dmesg spamming with drm_warn_once() (Sima)
- add more information about bpp special case (Sima)
- clarify parameters for hardware alignment
- add a TODO item for DUMB_CREATE2
v3:
- document the UAPI semantics
- compute scanline pitch from for unknown color modes (Andy, Tomi)

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Tomi Valkeinen 
Reviewed-by: Tomi Valkeinen 
---
 Documentation/gpu/todo.rst         |  37 ++++++++
 drivers/gpu/drm/drm_dumb_buffers.c | 130 +++++++++++++++++++++++++++++
 include/drm/drm_dumb_buffers.h     |  14 ++++
 include/uapi/drm/drm_mode.h        |  50 ++++++++++-
 4 files changed, 230 insertions(+), 1 deletion(-)
 create mode 100644 include/drm/drm_dumb_buffers.h

diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 92db80793bba..98ed38241dc6 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -648,6 +648,43 @@ Contact: Thomas Zimmermann , Simona Vetter
 
 Level: Advanced
 
+Implement a new DUMB_CREATE2 ioctl
+----------------------------------
+
+The current DUMB_CREATE ioctl is not well defined. Instead of a pixel and
+framebuffer format, it only accepts a color mode of vague semantics. Assuming
+a linear framebuffer, the color mode gives an idea of the supported pixel
+format. But userspace effectively has to guess the correct values. It really
+only works reliably with framebuffers in XRGB8888. Userspace has begun to
+workaround these limitations by computing arbitrary format's buffer sizes and
+calculating their sizes in terms of XRGB8888 pixels.
+
+One possible solution is a new ioctl DUMB_CREATE2. It should accept a DRM
+format and a format modifier to resolve the color mode's ambiguity. As
+framebuffers can be multi-planar, the new ioctl has to return the buffer size,
+pitch and GEM handle for each individual color plane.
+
+In the first step, the new ioctl can be limited to the current features of
+the existing DUMB_CREATE. Individual drivers can then be extended to support
+multi-planar formats. Rockchip might require this and would be a good candidate.
+
+It might also be helpful to userspace to query information about the size of
+a potential buffer, if allocated. Userspace would supply geometry and format;
+the kernel would return minimal allocation sizes and scanline pitch. There is
+interest to allocate that memory from another device and provide it to the
+DRM driver (say via dma-buf).
+
+Another requested feature is the ability to allocate a buffer by size, without
+format. Accelators use this for their buffer allocation and it could likely be
+generalized.
+
+In addition to the kernel implementation, there must be user-space support
+for the new ioctl. There's code in Mesa that might be able to use the new
+call.
+
+Contact: Thomas Zimmermann 
+
+Level: Advanced
 
 Better Testing
 ==============
diff --git a/drivers/gpu/drm/drm_dumb_buffers.c b/drivers/gpu/drm/drm_dumb_buffers.c
index 9916aaf5b3f2..e9eed9a5b760 100644
--- a/drivers/gpu/drm/drm_dumb_buffers.c
+++ b/drivers/gpu/drm/drm_dumb_buffers.c
@@ -25,6 +25,8 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 
@@ -57,6 +59,134 @@
  * a hardware-specific ioctl to allocate suitable buffer objects.
  */
 
+static int drm_mode_align_dumb(struct drm_mode_create_dumb *args,
+			       unsigned long hw_pitch_align,
+			       unsigned long hw_size_align)
+{
+	u32 pitch = args->pitch;
+	u32 size;
+
+	if (!pitch)
+		return -EINVAL;
+
+	if (hw_pitch_align)
+		pitch = roundup(pitch, hw_pitch_align);
+
+	if (!hw_size_align)
+		hw_size_align = PAGE_SIZE;
+	else if (!IS_ALIGNED(hw_size_align, PAGE_SIZE))
+		return -EINVAL; /* TODO: handle this if necessary */
+
+	if (check_mul_overflow(args->height, pitch, &size))
+		return -EINVAL;
+	size = ALIGN(size, hw_size_align);
+	if (!size)
+		return -EINVAL;
+
+	args->pitch = pitch;
+	args->size = size;
+
+	return 0;
+}
+
+/**
+ * drm_mode_size_dumb - Calculates the scanline and buffer sizes for dumb buffers
+ * @dev: DRM device
+ * @args: Parameters for the dumb buffer
+ * @hw_pitch_align: Hardware scanline alignment in bytes
+ * @hw_size_align: Hardware buffer-size alignment in bytes
+ *
+ * The helper drm_mode_size_dumb() calculates the size of the buffer
+ * allocation and the scanline size for a dumb buffer. Callers have to
+ * set the buffers width, height and color mode in the argument @arg.
+ * The helper validates the correctness of the input and tests for
+ * possible overflows. If successful, it returns the dumb buffer's
+ * required scanline pitch and size in &args.
+ *
+ * The parameter @hw_pitch_align allows the driver to specifies an
+ * alignment for the scanline pitch, if the hardware requires any. The
+ * calculated pitch will be a multiple of the alignment. The parameter
+ * @hw_size_align allows to specify an alignment for buffer sizes. The
+ * provided alignment should represent requirements of the graphics
+ * hardware. drm_mode_size_dumb() handles GEM-related constraints
+ * automatically across all drivers and hardware. For example, the
+ * returned buffer size is always a multiple of PAGE_SIZE, which is
+ * required by mmap().
+ *
+ * Returns:
+ * Zero on success, or a negative error code otherwise.
+ */
+int drm_mode_size_dumb(struct drm_device *dev,
+		       struct drm_mode_create_dumb *args,
+		       unsigned long hw_pitch_align,
+		       unsigned long hw_size_align)
+{
+	u64 pitch = 0;
+	u32 fourcc;
+
+	/*
+	 * The scanline pitch depends on the buffer width and the color
+	 * format. The latter is specified as a color-mode constant for
+	 * which we first have to find the corresponding color format.
+	 *
+	 * Different color formats can have the same color-mode constant.
+	 * For example XRGB8888 and BGRX8888 both have a color mode of 32.
+	 * It is possible to use different formats for dumb-buffer allocation
+	 * and rendering as long as all involved formats share the same
+	 * color-mode constant.
+	 */
+	fourcc = drm_driver_color_mode_format(dev, args->bpp);
+	if (fourcc != DRM_FORMAT_INVALID) {
+		const struct drm_format_info *info = drm_format_info(fourcc);
+
+		if (!info)
+			return -EINVAL;
+		pitch = drm_format_info_min_pitch(info, 0, args->width);
+	} else if (args->bpp) {
+		/*
+		 * Some userspace throws in arbitrary values for bpp and
+		 * relies on the kernel to figure it out. In this case we
+		 * fall back to the old method of using bpp directly. The
+		 * over-commitment of memory from the rounding is acceptable
+		 * for compatibility with legacy userspace. We have a number
+		 * of deprecated legacy values that are explicitly supported.
+		 */
+		switch (args->bpp) {
+		default:
+			drm_warn_once(dev,
+				      "Unknown color mode %u; guessing buffer size.\n",
+				      args->bpp);
+			fallthrough;
+		/*
+		 * These constants represent various YUV formats supported by
+		 * drm_gem_afbc_get_bpp().
+		 */
+		case 12: // DRM_FORMAT_YUV420_8BIT
+		case 15: // DRM_FORMAT_YUV420_10BIT
+		case 30: // DRM_FORMAT_VUY101010
+			fallthrough;
+		/*
+		 * Used by Mesa and Gstreamer to allocate NV formats and others
+		 * as RGB buffers. Technically, XRGB16161616F formats are RGB,
+		 * but the dumb buffers are not supposed to be used for anything
+		 * beyond 32 bits per pixels.
+		 */
+		case 10: // DRM_FORMAT_NV{15,20,30}, DRM_FORMAT_P010
+		case 64: // DRM_FORMAT_{XRGB,XBGR,ARGB,ABGR}16161616F
+			pitch = args->width * DIV_ROUND_UP(args->bpp, SZ_8);
+			break;
+		}
+	}
+
+	if (!pitch || pitch > U32_MAX)
+		return -EINVAL;
+
+	args->pitch = pitch;
+
+	return drm_mode_align_dumb(args, hw_pitch_align, hw_size_align);
+}
+EXPORT_SYMBOL(drm_mode_size_dumb);
+
 int drm_mode_create_dumb(struct drm_device *dev,
 			 struct drm_mode_create_dumb *args,
 			 struct drm_file *file_priv)
diff --git a/include/drm/drm_dumb_buffers.h b/include/drm/drm_dumb_buffers.h
new file mode 100644
index 000000000000..1f3a8236fb3d
--- /dev/null
+++ b/include/drm/drm_dumb_buffers.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+
+#ifndef __DRM_DUMB_BUFFERS_H__
+#define __DRM_DUMB_BUFFERS_H__
+
+struct drm_device;
+struct drm_mode_create_dumb;
+
+int drm_mode_size_dumb(struct drm_device *dev,
+		       struct drm_mode_create_dumb *args,
+		       unsigned long hw_pitch_align,
+		       unsigned long hw_size_align);
+
+#endif
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index a122bea25593..1e0e02a79b5c 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -1066,7 +1066,7 @@ struct drm_mode_crtc_page_flip_target {
  * struct drm_mode_create_dumb - Create a KMS dumb buffer for scanout.
  * @height: buffer height in pixels
  * @width: buffer width in pixels
- * @bpp: bits per pixel
+ * @bpp: color mode
  * @flags: must be zero
  * @handle: buffer object handle
  * @pitch: number of bytes between two consecutive lines
@@ -1074,6 +1074,54 @@ struct drm_mode_crtc_page_flip_target {
  *
  * User-space fills @height, @width, @bpp and @flags. If the IOCTL succeeds,
  * the kernel fills @handle, @pitch and @size.
+ *
+ * The value of @bpp is a color-mode number describing a specific format
+ * or a variant thereof. The value often corresponds to the number of bits
+ * per pixel for most modes, although there are exceptions. Each color mode
+ * maps to a DRM format plus a number of modes with similar pixel layout.
+ * Framebuffer layout is always linear.
+ *
+ * Support for all modes and formats is optional. Even if dumb-buffer
+ * creation with a certain color mode succeeds, it is not guaranteed that
+ * the DRM driver supports any of the related formats. Most drivers support
+ * a color mode of 32 with a format of DRM_FORMAT_XRGB8888 on their primary
+ * plane.
+ *
+ * +------------+------------------------+------------------------+
+ * | Color mode | Framebuffer format     | Compatible formats     |
+ * +============+========================+========================+
+ * |     32     |  * DRM_FORMAT_XRGB8888 |  * DRM_FORMAT_BGRX8888 |
+ * |            |                        |  * DRM_FORMAT_RGBX8888 |
+ * |            |                        |  * DRM_FORMAT_XBGR8888 |
+ * +------------+------------------------+------------------------+
+ * |     24     |  * DRM_FORMAT_RGB888   |  * DRM_FORMAT_BGR888   |
+ * +------------+------------------------+------------------------+
+ * |     16     |  * DRM_FORMAT_RGB565   |  * DRM_FORMAT_BGR565   |
+ * +------------+------------------------+------------------------+
+ * |     15     |  * DRM_FORMAT_XRGB1555 |  * DRM_FORMAT_BGRX1555 |
+ * |            |                        |  * DRM_FORMAT_RGBX1555 |
+ * |            |                        |  * DRM_FORMAT_XBGR1555 |
+ * +------------+------------------------+------------------------+
+ * |      8     |  * DRM_FORMAT_C8       |  * DRM_FORMAT_D8       |
+ * |            |                        |  * DRM_FORMAT_R8       |
+ * +------------+------------------------+------------------------+
+ * |      4     |  * DRM_FORMAT_C4       |  * DRM_FORMAT_D4       |
+ * |            |                        |  * DRM_FORMAT_R4       |
+ * +------------+------------------------+------------------------+
+ * |      2     |  * DRM_FORMAT_C2       |  * DRM_FORMAT_D2       |
+ * |            |                        |  * DRM_FORMAT_R2       |
+ * +------------+------------------------+------------------------+
+ * |      1     |  * DRM_FORMAT_C1       |  * DRM_FORMAT_D1       |
+ * |            |                        |  * DRM_FORMAT_R1       |
+ * +------------+------------------------+------------------------+
+ *
+ * Color modes of 10, 12, 15, 30 and 64 are only supported for use by
+ * legacy user space. Please don't use them in new code. Other modes
+ * are not support.
+ *
+ * Do not attempt to allocate anything but linear framebuffer memory
+ * with single-plane RGB data. Allocation of other framebuffer
+ * layouts requires dedicated ioctls in the respective DRM driver.
  */
 struct drm_mode_create_dumb {
 	__u32 height;
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann 
Subject: [PATCH v6 00/25] drm/dumb-buffers: Fix and improve buffer-size calculation
Date: Thu, 21 Aug 2025 10:17:07 +0200
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Dumb-buffer pitch and size is specified by width, height, bits-per-pixel
plus various hardware-specific alignments. The calculation of these
values is inconsistent and duplicated among drivers. The results for
formats with bpp < 8 are sometimes incorrect.

This series fixes this for most drivers. Default scanline pitch and
buffer size are now calculated with the existing 4CC helpers. There is
a new helper drm_mode_size_dumb() that calculates scanline pitch and
buffer size according to driver requirements.

The series fixes the common GEM implementations for DMA, SHMEM and
VRAM. It further changes most implementations of dumb_create to use
the new helper. A small number of drivers has more complicated
calculations and will be updated by a later patches.

v6:
- extend TODO item (Tomi)
- fix typos in documentation (Tomi)
v5:
- use check_mul_overflow() for overflow test (Tomi)
- imx: fix intermediate code (Tomi)
- rz-du: include dumb-buffers header
v4:
- improve UAPI documentation
- document bpp special cases
- use drm_warn_once()
- add TODO lists
- armada: fix pitch alignment
v3:
- document UAPI semantics
- fall back to bpp-based allocation for unknown color modes
- cleanups
v2:
- rewrite series
- convert many individual drivers besides the shared GEM helpers

Thomas Zimmermann (25):
  drm/dumb-buffers: Sanitize output on errors
  drm/dumb-buffers: Provide helper to set pitch and size
  drm/gem-dma: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/gem-shmem: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/gem-vram: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/armada: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/exynos: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/gma500: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/hibmc: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/imx/ipuv3: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/loongson: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/mediatek: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/msm: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/nouveau: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/omapdrm: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/qxl: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/renesas/rcar-du: Compute dumb-buffer sizes with
    drm_mode_size_dumb()
  drm/renesas/rz-du: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/rockchip: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/tegra: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/virtio: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/vmwgfx: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/xe: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/xen: Compute dumb-buffer sizes with drm_mode_size_dumb()
  drm/xlnx: Compute dumb-buffer sizes with drm_mode_size_dumb()

 Documentation/gpu/todo.rst                    |  37 ++++
 drivers/gpu/drm/armada/armada_gem.c           |  16 +-
 drivers/gpu/drm/drm_dumb_buffers.c            | 170 ++++++++++++++++--
 drivers/gpu/drm/drm_gem_dma_helper.c          |   7 +-
 drivers/gpu/drm/drm_gem_shmem_helper.c        |  16 +-
 drivers/gpu/drm/drm_gem_vram_helper.c         |  89 +++------
 drivers/gpu/drm/exynos/exynos_drm_gem.c       |   8 +-
 drivers/gpu/drm/gma500/gem.c                  |  21 +--
 .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c   |  25 ++-
 drivers/gpu/drm/imx/ipuv3/imx-drm-core.c      |  29 ++-
 drivers/gpu/drm/loongson/lsdc_gem.c           |  29 +--
 drivers/gpu/drm/mediatek/mtk_gem.c            |  13 +-
 drivers/gpu/drm/msm/msm_gem.c                 |  27 ++-
 drivers/gpu/drm/nouveau/nouveau_display.c     |   7 +-
 drivers/gpu/drm/omapdrm/omap_gem.c            |  15 +-
 drivers/gpu/drm/qxl/qxl_dumb.c                |  17 +-
 drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c |   7 +-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c  |   8 +-
 drivers/gpu/drm/rockchip/rockchip_drm_gem.c   |  12 +-
 drivers/gpu/drm/tegra/gem.c                   |   8 +-
 drivers/gpu/drm/virtio/virtgpu_gem.c          |  11 +-
 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c       |  21 +--
 drivers/gpu/drm/xe/xe_bo.c                    |   8 +-
 drivers/gpu/drm/xen/xen_drm_front.c           |   7 +-
 drivers/gpu/drm/xlnx/zynqmp_kms.c             |   7 +-
 include/drm/drm_dumb_buffers.h                |  14 ++
 include/drm/drm_gem_vram_helper.h             |   6 -
 include/uapi/drm/drm_mode.h                   |  50 +++++-
 28 files changed, 457 insertions(+), 228 deletions(-)
 create mode 100644 include/drm/drm_dumb_buffers.h

-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
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	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Russell King 
Subject: [PATCH v6 06/25] drm/armada: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:13 +0200
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 128.

v4:
- align pitch to 128 bytes (Russell)

Signed-off-by: Thomas Zimmermann 
Cc: Russell King 
---
 drivers/gpu/drm/armada/armada_gem.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/armada/armada_gem.c b/drivers/gpu/drm/armada/armada_gem.c
index 1a1680d71486..a767c4edd5c8 100644
--- a/drivers/gpu/drm/armada/armada_gem.c
+++ b/drivers/gpu/drm/armada/armada_gem.c
@@ -9,6 +9,7 @@
 #include 
 
 #include 
+#include 
 #include 
 
 #include "armada_drm.h"
@@ -244,14 +245,13 @@ int armada_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 	struct drm_mode_create_dumb *args)
 {
 	struct armada_gem_object *dobj;
-	u32 handle;
-	size_t size;
 	int ret;
 
-	args->pitch = armada_pitch(args->width, args->bpp);
-	args->size = size = args->pitch * args->height;
+	ret = drm_mode_size_dumb(dev, args, SZ_128, 0);
+	if (ret)
+		return ret;
 
-	dobj = armada_gem_alloc_private_object(dev, size);
+	dobj = armada_gem_alloc_private_object(dev, args->size);
 	if (dobj == NULL)
 		return -ENOMEM;
 
@@ -259,14 +259,12 @@ int armada_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 	if (ret)
 		goto err;
 
-	ret = drm_gem_handle_create(file, &dobj->obj, &handle);
+	ret = drm_gem_handle_create(file, &dobj->obj, &args->handle);
 	if (ret)
 		goto err;
 
-	args->handle = handle;
-
 	/* drop reference from allocate - handle holds it now */
-	DRM_DEBUG_DRIVER("obj %p size %zu handle %#x\n", dobj, size, handle);
+	DRM_DEBUG_DRIVER("obj %p size %llu handle %#x\n", dobj, args->size, args->handle);
  err:
 	drm_gem_object_put(&dobj->obj);
 	return ret;
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
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	linux-renesas-soc@vger.kernel.org,
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	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Patrik Jakobsson 
Subject: [PATCH v6 08/25] drm/gma500: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:15 +0200
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 64.

Signed-off-by: Thomas Zimmermann 
Cc: Patrik Jakobsson 
---
 drivers/gpu/drm/gma500/gem.c | 21 ++++++---------------
 1 file changed, 6 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/gma500/gem.c b/drivers/gpu/drm/gma500/gem.c
index 4b7627a72637..fc337db0a948 100644
--- a/drivers/gpu/drm/gma500/gem.c
+++ b/drivers/gpu/drm/gma500/gem.c
@@ -16,6 +16,7 @@
 #include 
 
 #include 
+#include 
 #include 
 
 #include "gem.h"
@@ -199,35 +200,25 @@ psb_gem_create(struct drm_device *dev, u64 size, const char *name, bool stolen,
 int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 			struct drm_mode_create_dumb *args)
 {
-	size_t pitch, size;
 	struct psb_gem_object *pobj;
 	struct drm_gem_object *obj;
-	u32 handle;
 	int ret;
 
-	pitch = args->width * DIV_ROUND_UP(args->bpp, 8);
-	pitch = ALIGN(pitch, 64);
-
-	size = pitch * args->height;
-	size = roundup(size, PAGE_SIZE);
-	if (!size)
-		return -EINVAL;
+	ret = drm_mode_size_dumb(dev, args, SZ_64, 0);
+	if (ret)
+		return ret;
 
-	pobj = psb_gem_create(dev, size, "gem", false, PAGE_SIZE);
+	pobj = psb_gem_create(dev, args->size, "gem", false, PAGE_SIZE);
 	if (IS_ERR(pobj))
 		return PTR_ERR(pobj);
 	obj = &pobj->base;
 
-	ret = drm_gem_handle_create(file, obj, &handle);
+	ret = drm_gem_handle_create(file, obj, &args->handle);
 	if (ret)
 		goto err_drm_gem_object_put;
 
 	drm_gem_object_put(obj);
 
-	args->pitch = pitch;
-	args->size = size;
-	args->handle = handle;
-
 	return 0;
 
 err_drm_gem_object_put:
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Inki Dae ,
	Seung-Woo Kim ,
	Kyungmin Park ,
	Krzysztof Kozlowski ,
	Alim Akhtar 
Subject: [PATCH v6 07/25] drm/exynos: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:14 +0200
Message-ID: <20250821081918.79786-8-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. No alignment required.

Signed-off-by: Thomas Zimmermann 
Cc: Inki Dae 
Cc: Seung-Woo Kim 
Cc: Kyungmin Park 
Cc: Krzysztof Kozlowski 
Cc: Alim Akhtar 
Acked-by: Inki Dae 
---
 drivers/gpu/drm/exynos/exynos_drm_gem.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index e3fbb45f37a2..02714c9ab639 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
@@ -329,15 +330,16 @@ int exynos_drm_gem_dumb_create(struct drm_file *file_priv,
 	unsigned int flags;
 	int ret;
 
+	ret = drm_mode_size_dumb(dev, args, 0, 0);
+	if (ret)
+		return ret;
+
 	/*
 	 * allocate memory to be used for framebuffer.
 	 * - this callback would be called by user application
 	 *	with DRM_IOCTL_MODE_CREATE_DUMB command.
 	 */
 
-	args->pitch = args->width * ((args->bpp + 7) / 8);
-	args->size = args->pitch * args->height;
-
 	if (is_drm_iommu_supported(dev))
 		flags = EXYNOS_BO_NONCONTIG | EXYNOS_BO_WC;
 	else
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Xinliang Liu ,
	Tian Tao ,
	Xinwei Kong ,
	Sumit Semwal ,
	Yongqin Liu ,
	John Stultz 
Subject: [PATCH v6 09/25] drm/hibmc: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:16 +0200
Message-ID: <20250821081918.79786-10-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 128.

The hibmc driver's new hibmc_dumb_create() is similar to the one
in GEM VRAM helpers. The driver was the only caller of
drm_gem_vram_fill_create_dumb(). Remove the now unused helper.

Signed-off-by: Thomas Zimmermann 
Cc: Xinliang Liu 
Cc: Tian Tao 
Cc: Xinwei Kong 
Cc: Sumit Semwal 
Cc: Yongqin Liu 
Cc: John Stultz 
---
 drivers/gpu/drm/drm_gem_vram_helper.c         | 65 -------------------
 .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c   | 25 ++++++-
 include/drm/drm_gem_vram_helper.h             |  6 --
 3 files changed, 24 insertions(+), 72 deletions(-)

diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c
index dd4537bf63dc..d5a6d5134c55 100644
--- a/drivers/gpu/drm/drm_gem_vram_helper.c
+++ b/drivers/gpu/drm/drm_gem_vram_helper.c
@@ -407,71 +407,6 @@ void drm_gem_vram_vunmap(struct drm_gem_vram_object *gbo,
 }
 EXPORT_SYMBOL(drm_gem_vram_vunmap);
 
-/**
- * drm_gem_vram_fill_create_dumb() - Helper for implementing
- *				     &struct drm_driver.dumb_create
- *
- * @file:		the DRM file
- * @dev:		the DRM device
- * @pg_align:		the buffer's alignment in multiples of the page size
- * @pitch_align:	the scanline's alignment in powers of 2
- * @args:		the arguments as provided to
- *			&struct drm_driver.dumb_create
- *
- * This helper function fills &struct drm_mode_create_dumb, which is used
- * by &struct drm_driver.dumb_create. Implementations of this interface
- * should forwards their arguments to this helper, plus the driver-specific
- * parameters.
- *
- * Returns:
- * 0 on success, or
- * a negative error code otherwise.
- */
-int drm_gem_vram_fill_create_dumb(struct drm_file *file,
-				  struct drm_device *dev,
-				  unsigned long pg_align,
-				  unsigned long pitch_align,
-				  struct drm_mode_create_dumb *args)
-{
-	size_t pitch, size;
-	struct drm_gem_vram_object *gbo;
-	int ret;
-	u32 handle;
-
-	pitch = args->width * DIV_ROUND_UP(args->bpp, 8);
-	if (pitch_align) {
-		if (WARN_ON_ONCE(!is_power_of_2(pitch_align)))
-			return -EINVAL;
-		pitch = ALIGN(pitch, pitch_align);
-	}
-	size = pitch * args->height;
-
-	size = roundup(size, PAGE_SIZE);
-	if (!size)
-		return -EINVAL;
-
-	gbo = drm_gem_vram_create(dev, size, pg_align);
-	if (IS_ERR(gbo))
-		return PTR_ERR(gbo);
-
-	ret = drm_gem_handle_create(file, &gbo->bo.base, &handle);
-	if (ret)
-		goto err_drm_gem_object_put;
-
-	drm_gem_object_put(&gbo->bo.base);
-
-	args->pitch = pitch;
-	args->size = size;
-	args->handle = handle;
-
-	return 0;
-
-err_drm_gem_object_put:
-	drm_gem_object_put(&gbo->bo.base);
-	return ret;
-}
-EXPORT_SYMBOL(drm_gem_vram_fill_create_dumb);
-
 /*
  * Helpers for struct ttm_device_funcs
  */
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
index 289304500ab0..14a018c47c73 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
@@ -18,10 +18,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -70,7 +72,28 @@ static irqreturn_t hibmc_dp_interrupt(int irq, void *arg)
 static int hibmc_dumb_create(struct drm_file *file, struct drm_device *dev,
 			     struct drm_mode_create_dumb *args)
 {
-	return drm_gem_vram_fill_create_dumb(file, dev, 0, 128, args);
+	struct drm_gem_vram_object *gbo;
+	int ret;
+
+	ret = drm_mode_size_dumb(dev, args, SZ_128, 0);
+	if (ret)
+		return ret;
+
+	gbo = drm_gem_vram_create(dev, args->size, 0);
+	if (IS_ERR(gbo))
+		return PTR_ERR(gbo);
+
+	ret = drm_gem_handle_create(file, &gbo->bo.base, &args->handle);
+	if (ret)
+		goto err_drm_gem_object_put;
+
+	drm_gem_object_put(&gbo->bo.base);
+
+	return 0;
+
+err_drm_gem_object_put:
+	drm_gem_object_put(&gbo->bo.base);
+	return ret;
 }
 
 static const struct drm_driver hibmc_driver = {
diff --git a/include/drm/drm_gem_vram_helper.h b/include/drm/drm_gem_vram_helper.h
index 2dd42bed679d..1190064f5760 100644
--- a/include/drm/drm_gem_vram_helper.h
+++ b/include/drm/drm_gem_vram_helper.h
@@ -98,12 +98,6 @@ int drm_gem_vram_vmap(struct drm_gem_vram_object *gbo, struct iosys_map *map);
 void drm_gem_vram_vunmap(struct drm_gem_vram_object *gbo,
 			 struct iosys_map *map);
 
-int drm_gem_vram_fill_create_dumb(struct drm_file *file,
-				  struct drm_device *dev,
-				  unsigned long pg_align,
-				  unsigned long pitch_align,
-				  struct drm_mode_create_dumb *args);
-
 /*
  * Helpers for struct drm_driver
  */
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Philipp Zabel ,
	Shawn Guo ,
	Sascha Hauer ,
	Pengutronix Kernel Team ,
	Fabio Estevam 
Subject: [PATCH v6 10/25] drm/imx/ipuv3: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:17 +0200
Message-ID: <20250821081918.79786-11-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. The hardware requires the framebuffer width to be a
multiple of 8. The scanline pitch has to be large enough to support
this. Therefore compute the byte size of 8 pixels in the given color
mode and align the pitch accordingly.

v5:
- fix typo in commit description

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Philipp Zabel 
Cc: Philipp Zabel 
Cc: Shawn Guo 
Cc: Sascha Hauer 
Cc: Pengutronix Kernel Team 
Cc: Fabio Estevam 
---
 drivers/gpu/drm/imx/ipuv3/imx-drm-core.c | 31 ++++++++++++++++++------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
index af4a30311e18..465b5a6ad5bb 100644
--- a/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/ipuv3/imx-drm-core.c
@@ -17,7 +17,9 @@
 #include 
 #include 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -141,19 +143,32 @@ static int imx_drm_dumb_create(struct drm_file *file_priv,
 			       struct drm_device *drm,
 			       struct drm_mode_create_dumb *args)
 {
-	u32 width = args->width;
+	u32 fourcc;
+	const struct drm_format_info *info;
+	u64 pitch_align;
 	int ret;
 
-	args->width = ALIGN(width, 8);
-	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
-	args->size = args->pitch * args->height;
-
-	ret = drm_gem_dma_dumb_create_internal(file_priv, drm, args);
+	/*
+	 * Hardware requires the framebuffer width to be aligned to
+	 * multiples of 8. The mode-setting code handles this, but
+	 * the buffer pitch has to be aligned as well. Set the pitch
+	 * alignment accordingly, so that the each scanline fits into
+	 * the allocated buffer.
+	 */
+	fourcc = drm_driver_color_mode_format(drm, args->bpp);
+	if (fourcc == DRM_FORMAT_INVALID)
+		return -EINVAL;
+	info = drm_format_info(fourcc);
+	if (!info)
+		return -EINVAL;
+	pitch_align = drm_format_info_min_pitch(info, 0, SZ_8);
+	if (!pitch_align || pitch_align > U32_MAX)
+		return -EINVAL;
+	ret = drm_mode_size_dumb(drm, args, pitch_align, 0);
 	if (ret)
 		return ret;
 
-	args->width = width;
-	return ret;
+	return drm_gem_dma_dumb_create(file_priv, drm, args);
 }
 
 static const struct drm_driver imx_drm_driver = {
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Chun-Kuang Hu ,
	Philipp Zabel ,
	Matthias Brugger ,
	AngeloGioacchino Del Regno 
Subject: [PATCH v6 12/25] drm/mediatek: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:19 +0200
Message-ID: <20250821081918.79786-13-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.

Signed-off-by: Thomas Zimmermann 
Cc: Chun-Kuang Hu 
Cc: Philipp Zabel 
Cc: Matthias Brugger 
Cc: AngeloGioacchino Del Regno 
---
 drivers/gpu/drm/mediatek/mtk_gem.c | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_gem.c b/drivers/gpu/drm/mediatek/mtk_gem.c
index a172456d1d7b..21e08fabfd7f 100644
--- a/drivers/gpu/drm/mediatek/mtk_gem.c
+++ b/drivers/gpu/drm/mediatek/mtk_gem.c
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -124,15 +125,9 @@ int mtk_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev,
 	struct mtk_gem_obj *mtk_gem;
 	int ret;
 
-	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
-
-	/*
-	 * Multiply 2 variables of different types,
-	 * for example: args->size = args->spacing * args->height;
-	 * may cause coverity issue with unintentional overflow.
-	 */
-	args->size = args->pitch;
-	args->size *= args->height;
+	ret = drm_mode_size_dumb(dev, args, SZ_8, 0);
+	if (ret)
+		return ret;
 
 	mtk_gem = mtk_gem_create(dev, args->size, false);
 	if (IS_ERR(mtk_gem))
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Dmitry Baryshkov ,
	Rob Clark ,
	Abhinav Kumar ,
	Sean Paul ,
	Marijn Suijten 
Subject: [PATCH v6 13/25] drm/msm: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:20 +0200
Message-ID: <20250821081918.79786-14-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Alignment is specified in bytes, but the hardware
requires the scanline pitch to be a multiple of 32 pixels. Therefore
compute the byte size of 32 pixels in the given color mode and align
the pitch accordingly. This replaces the existing code in the driver's
align_pitch() helper.

v3:
- clarify pitch alignment in commit message (Dmitry)

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Dmitry Baryshkov 
Cc: Rob Clark 
Cc: Abhinav Kumar 
Cc: Dmitry Baryshkov 
Cc: Sean Paul 
Cc: Marijn Suijten 
---
 drivers/gpu/drm/msm/msm_gem.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 7ff994d4f91a..d854444ba1b5 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -10,8 +10,10 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -691,8 +693,29 @@ void msm_gem_unpin_iova(struct drm_gem_object *obj, struct drm_gpuvm *vm)
 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 		struct drm_mode_create_dumb *args)
 {
-	args->pitch = align_pitch(args->width, args->bpp);
-	args->size  = PAGE_ALIGN(args->pitch * args->height);
+	u32 fourcc;
+	const struct drm_format_info *info;
+	u64 pitch_align;
+	int ret;
+
+	/*
+	 * Adreno needs pitch aligned to 32 pixels. Compute the number
+	 * of bytes for a block of 32 pixels at the given color format.
+	 * Use the result as pitch alignment.
+	 */
+	fourcc = drm_driver_color_mode_format(dev, args->bpp);
+	if (fourcc == DRM_FORMAT_INVALID)
+		return -EINVAL;
+	info = drm_format_info(fourcc);
+	if (!info)
+		return -EINVAL;
+	pitch_align = drm_format_info_min_pitch(info, 0, SZ_32);
+	if (!pitch_align || pitch_align > U32_MAX)
+		return -EINVAL;
+	ret = drm_mode_size_dumb(dev, args, pitch_align, 0);
+	if (ret)
+		return ret;
+
 	return msm_gem_new_handle(dev, file, args->size,
 			MSM_BO_SCANOUT | MSM_BO_WC, &args->handle, "dumb");
 }
-- 
2.50.1



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Date: Thu, 21 Aug 2025 10:25:34 +0200
From: Nicola Vetrini 
To: Jan Beulich 
Cc: Dmytro Prokopchuk1 , Doug Goldstein
 , Stefano Stabellini , Andrew
 Cooper , Anthony PERARD
 , Michal Orzel , Julien
 Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , xen-devel@lists.xenproject.org
Subject: Re: [PATCH] misra: consider conversion from UL or (void*) to function
 pointer as safe
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On 2025-08-21 10:01, Jan Beulich wrote:
> On 19.08.2025 20:55, Dmytro Prokopchuk1 wrote:
>> Rule 11.1 states as following: "Conversions shall not be performed
>> between a pointer to a function and any other type."
>> 
>> The conversion from unsigned long or (void *) to a function pointer
>> is safe in Xen because the architectures it supports (e.g., x86 and
>> ARM) guarantee compatible representations between these types.
> 
> I think we need to be as precise as possible here. The architectures
> guarantee nothing, they only offer necessary fundamentals. In the
> Windows x86 ABI, for example, you can't convert pointers to/from longs
> without losing data. What we build upon is what respective ABIs say,
> possibly in combination of implementation specifics left to compilers.
> 

+1, a mention of the compilers and targets this deviation relies upon is 
needed.

>> --- a/docs/misra/deviations.rst
>> +++ b/docs/misra/deviations.rst
>> @@ -370,6 +370,16 @@ Deviations related to MISRA C:2012 Rules:
>>         to store it.
>>       - Tagged as `safe` for ECLAIR.
>> 
>> +   * - R11.1
>> +     - The conversion from unsigned long or (void \*) to a function 
>> pointer does
>> +       not lose any information or violate type safety assumptions if 
>> unsigned
>> +       long or (void \*) type is guaranteed to be the same bit size 
>> as a
>> +       function pointer. This ensures that the function pointer can 
>> be fully
>> +       represented without truncation or corruption. The macro 
>> BUILD_BUG_ON is
>> +       integrated into xen/common/version.c to confirm conversion 
>> compatibility
>> +       across all target platforms.
>> +     - Tagged as `safe` for ECLAIR.
> 
> Why the escaping of * here, when ...
> 
>> --- a/docs/misra/rules.rst
>> +++ b/docs/misra/rules.rst
>> @@ -431,7 +431,13 @@ maintainers if you want to suggest a change.
>>       - All conversions to integer types are permitted if the 
>> destination
>>         type has enough bits to hold the entire value. Conversions to 
>> bool
>>         and void* are permitted. Conversions from 'void noreturn 
>> (*)(...)'
>> -       to 'void (*)(...)' are permitted.
>> +       to 'void (*)(...)' are permitted. Conversions from unsigned 
>> long or
>> +       (void \*) to a function pointer are permitted if the source 
>> type has
>> +       enough bits to restore function pointer without truncation or 
>> corruption.
>> +       Example::
>> +
>> +           unsigned long func_addr = (unsigned long)&some_function;
>> +           void (*restored_func)(void) = (void (*)(void))func_addr;
> 
> ... context here suggests they work fine un-escaped, and you even add 
> some un-
> escaped instances as well. Perhaps I'm simply unaware of some 
> peculiarity?
> 

This is a literal rst block, while the other is not (* acts as a bullet 
point in rst iirc)

> Jan

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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(sorry, original patch already gone from my mailbox)

This looks to have introduced a new randconfig failure, as per CI [1]:

In file included from drivers/passthrough/arm/ipmmu-vmsa.c:54:
./include/../arch/arm/pci/pci-host-rcar4.h:7:37: error: 'struct pci_host_bridge' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
    7 | void rcar4_pcie_osid_bdf_set(struct pci_host_bridge *bridge,
      |                                     ^~~~~~~~~~~~~~~
./include/../arch/arm/pci/pci-host-rcar4.h:9:39: error: 'struct pci_host_bridge' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
    9 | void rcar4_pcie_osid_bdf_clear(struct pci_host_bridge *bridge,
      |                                       ^~~~~~~~~~~~~~~
./include/../arch/arm/pci/pci-host-rcar4.h:11:36: error: 'struct pci_host_bridge' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
   11 | void rcar4_pcie_bdf_msk_set(struct pci_host_bridge *bridge, unsigned int reg_id,
      |                                    ^~~~~~~~~~~~~~~
./include/../arch/arm/pci/pci-host-rcar4.h:13:38: error: 'struct pci_host_bridge' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
   13 | int rcar4_pcie_osid_reg_alloc(struct pci_host_bridge *bridge);
      |                                      ^~~~~~~~~~~~~~~
./include/../arch/arm/pci/pci-host-rcar4.h:14:38: error: 'struct pci_host_bridge' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
   14 | void rcar4_pcie_osid_reg_free(struct pci_host_bridge *bridge,
      |                                      ^~~~~~~~~~~~~~~
./include/../arch/arm/pci/pci-host-rcar4.h:16:38: error: 'struct pci_host_bridge' declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
   16 | int rcar4_pcie_osid_regs_init(struct pci_host_bridge *bridge);
      |                                      ^~~~~~~~~~~~~~~

We either need a quick correction, or this may need reverting.

Jan

[1] https://gitlab.com/xen-project/hardware/xen/-/jobs/11087233227


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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
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	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Lyude Paul ,
	Karol Herbst ,
	Danilo Krummrich 
Subject: [PATCH v6 14/25] drm/nouveau: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:21 +0200
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 256.

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Lyude Paul 
Cc: Karol Herbst 
Cc: Lyude Paul 
Cc: Danilo Krummrich 
---
 drivers/gpu/drm/nouveau/nouveau_display.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 805d0a87aa54..54aed3656a4c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -807,9 +808,9 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev,
 	uint32_t domain;
 	int ret;
 
-	args->pitch = roundup(args->width * (args->bpp / 8), 256);
-	args->size = args->pitch * args->height;
-	args->size = roundup(args->size, PAGE_SIZE);
+	ret = drm_mode_size_dumb(dev, args, SZ_256, 0);
+	if (ret)
+		return ret;
 
 	/* Use VRAM if there is any ; otherwise fallback to system memory */
 	if (nouveau_drm(dev)->client.device.info.ram_size != 0)
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
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	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Oleksandr Andrushchenko 
Subject: [PATCH v6 24/25] drm/xen: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:31 +0200
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Align the pitch to a multiple of 8.

Signed-off-by: Thomas Zimmermann 
Cc: Oleksandr Andrushchenko 
---
 drivers/gpu/drm/xen/xen_drm_front.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xen/xen_drm_front.c b/drivers/gpu/drm/xen/xen_drm_front.c
index 1bda7ef606cc..fd2f250fbc33 100644
--- a/drivers/gpu/drm/xen/xen_drm_front.c
+++ b/drivers/gpu/drm/xen/xen_drm_front.c
@@ -14,6 +14,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -414,8 +415,10 @@ static int xen_drm_drv_dumb_create(struct drm_file *filp,
 	 * object without pages etc.
 	 * For details also see drm_gem_handle_create
 	 */
-	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
-	args->size = args->pitch * args->height;
+
+	ret = drm_mode_size_dumb(dev, args, SZ_8, 0);
+	if (ret)
+		return ret;
 
 	obj = xen_drm_front_gem_create(dev, args->size);
 	if (IS_ERR(obj)) {
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Dave Airlie ,
	Gerd Hoffmann 
Subject: [PATCH v6 16/25] drm/qxl: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:23 +0200
Message-ID: <20250821081918.79786-17-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. No alignment required.

Signed-off-by: Thomas Zimmermann 
Cc: Dave Airlie 
Cc: Gerd Hoffmann 
---
 drivers/gpu/drm/qxl/qxl_dumb.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/qxl/qxl_dumb.c b/drivers/gpu/drm/qxl/qxl_dumb.c
index 17df5c7ccf69..1200946767ce 100644
--- a/drivers/gpu/drm/qxl/qxl_dumb.c
+++ b/drivers/gpu/drm/qxl/qxl_dumb.c
@@ -23,6 +23,8 @@
  *          Alon Levy
  */
 
+#include 
+
 #include "qxl_drv.h"
 #include "qxl_object.h"
 
@@ -35,14 +37,13 @@ int qxl_mode_dumb_create(struct drm_file *file_priv,
 	struct qxl_device *qdev = to_qxl(dev);
 	struct qxl_bo *qobj;
 	struct drm_gem_object *gobj;
-	uint32_t handle;
 	int r;
 	struct qxl_surface surf;
-	uint32_t pitch, format;
+	u32 format;
 
-	pitch = args->width * ((args->bpp + 1) / 8);
-	args->size = pitch * args->height;
-	args->size = ALIGN(args->size, PAGE_SIZE);
+	r = drm_mode_size_dumb(dev, args, 0, 0);
+	if (r)
+		return r;
 
 	switch (args->bpp) {
 	case 16:
@@ -57,20 +58,18 @@ int qxl_mode_dumb_create(struct drm_file *file_priv,
 
 	surf.width = args->width;
 	surf.height = args->height;
-	surf.stride = pitch;
+	surf.stride = args->pitch;
 	surf.format = format;
 	surf.data = 0;
 
 	r = qxl_gem_object_create_with_handle(qdev, file_priv,
 					      QXL_GEM_DOMAIN_CPU,
 					      args->size, &surf, &gobj,
-					      &handle);
+					      &args->handle);
 	if (r)
 		return r;
 	qobj = gem_to_qxl_bo(gobj);
 	qobj->is_dumb = true;
 	drm_gem_object_put(gobj);
-	args->pitch = pitch;
-	args->handle = handle;
 	return 0;
 }
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
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	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Sui Jingfeng 
Subject: [PATCH v6 11/25] drm/loongson: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:18 +0200
Message-ID: <20250821081918.79786-12-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Sui Jingfeng 
Cc: Sui Jingfeng 
---
 drivers/gpu/drm/loongson/lsdc_gem.c | 29 ++++++++---------------------
 1 file changed, 8 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/loongson/lsdc_gem.c b/drivers/gpu/drm/loongson/lsdc_gem.c
index a720d8f53209..9f982b85301f 100644
--- a/drivers/gpu/drm/loongson/lsdc_gem.c
+++ b/drivers/gpu/drm/loongson/lsdc_gem.c
@@ -6,6 +6,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -204,45 +205,31 @@ int lsdc_dumb_create(struct drm_file *file, struct drm_device *ddev,
 	const struct lsdc_desc *descp = ldev->descp;
 	u32 domain = LSDC_GEM_DOMAIN_VRAM;
 	struct drm_gem_object *gobj;
-	size_t size;
-	u32 pitch;
-	u32 handle;
 	int ret;
 
-	if (!args->width || !args->height)
-		return -EINVAL;
-
-	if (args->bpp != 32 && args->bpp != 16)
-		return -EINVAL;
-
-	pitch = args->width * args->bpp / 8;
-	pitch = ALIGN(pitch, descp->pitch_align);
-	size = pitch * args->height;
-	size = ALIGN(size, PAGE_SIZE);
+	ret = drm_mode_size_dumb(ddev, args, descp->pitch_align, 0);
+	if (ret)
+		return ret;
 
 	/* Maximum single bo size allowed is the half vram size available */
-	if (size > ldev->vram_size / 2) {
-		drm_err(ddev, "Requesting(%zuMiB) failed\n", size >> 20);
+	if (args->size > ldev->vram_size / 2) {
+		drm_err(ddev, "Requesting(%zuMiB) failed\n", (size_t)(args->size >> PAGE_SHIFT));
 		return -ENOMEM;
 	}
 
-	gobj = lsdc_gem_object_create(ddev, domain, size, false, NULL, NULL);
+	gobj = lsdc_gem_object_create(ddev, domain, args->size, false, NULL, NULL);
 	if (IS_ERR(gobj)) {
 		drm_err(ddev, "Failed to create gem object\n");
 		return PTR_ERR(gobj);
 	}
 
-	ret = drm_gem_handle_create(file, gobj, &handle);
+	ret = drm_gem_handle_create(file, gobj, &args->handle);
 
 	/* drop reference from allocate, handle holds it now */
 	drm_gem_object_put(gobj);
 	if (ret)
 		return ret;
 
-	args->pitch = pitch;
-	args->size = size;
-	args->handle = handle;
-
 	return 0;
 }
 
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
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	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	David Airlie ,
	Gerd Hoffmann ,
	Gurchetan Singh ,
	Chia-I Wu 
Subject: [PATCH v6 21/25] drm/virtio: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:28 +0200
Message-ID: <20250821081918.79786-22-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 4.

Signed-off-by: Thomas Zimmermann 
Cc: David Airlie 
Cc: Gerd Hoffmann 
Cc: Gurchetan Singh 
Cc: Chia-I Wu 
---
 drivers/gpu/drm/virtio/virtgpu_gem.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/virtio/virtgpu_gem.c b/drivers/gpu/drm/virtio/virtgpu_gem.c
index 90c99d83c4cf..7e515d6e781d 100644
--- a/drivers/gpu/drm/virtio/virtgpu_gem.c
+++ b/drivers/gpu/drm/virtio/virtgpu_gem.c
@@ -23,6 +23,7 @@
  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include 
 #include 
 
@@ -66,15 +67,14 @@ int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
 	struct virtio_gpu_object_params params = { 0 };
 	struct virtio_gpu_device *vgdev = dev->dev_private;
 	int ret;
-	uint32_t pitch;
+
+	ret = drm_mode_size_dumb(dev, args, SZ_4, 0);
+	if (ret)
+		return ret;
 
 	if (args->bpp != 32)
 		return -EINVAL;
 
-	pitch = args->width * 4;
-	args->size = pitch * args->height;
-	args->size = ALIGN(args->size, PAGE_SIZE);
-
 	params.format = virtio_gpu_translate_format(DRM_FORMAT_HOST_XRGB8888);
 	params.width = args->width;
 	params.height = args->height;
@@ -92,7 +92,6 @@ int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
 	if (ret)
 		goto fail;
 
-	args->pitch = pitch;
 	return ret;
 
 fail:
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
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	xen-devel@lists.xenproject.org,
	Thomas Zimmermann 
Subject: [PATCH v6 15/25] drm/omapdrm: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:22 +0200
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 8.

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Tomi Valkeinen 
Cc: Tomi Valkeinen 
---
 drivers/gpu/drm/omapdrm/omap_gem.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c b/drivers/gpu/drm/omapdrm/omap_gem.c
index 381552bfb409..78563a8d8732 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 
@@ -580,15 +581,13 @@ static int omap_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struc
 int omap_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 		struct drm_mode_create_dumb *args)
 {
-	union omap_gem_size gsize;
-
-	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
-
-	args->size = PAGE_ALIGN(args->pitch * args->height);
+	union omap_gem_size gsize = { };
+	int ret;
 
-	gsize = (union omap_gem_size){
-		.bytes = args->size,
-	};
+	ret = drm_mode_size_dumb(dev, args, SZ_8, 0);
+	if (ret)
+		return ret;
+	gsize.bytes = args->size;
 
 	return omap_gem_new_handle(dev, file, gsize,
 			OMAP_BO_SCANOUT | OMAP_BO_WC, &args->handle);
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Biju Das 
Subject: [PATCH v6 18/25] drm/renesas/rz-du: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:25 +0200
Message-ID: <20250821081918.79786-19-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.

v5:
- include dumb-buffers header for drm_mode_size_dumb() (kernel test robot)

Signed-off-by: Thomas Zimmermann 
Cc: Biju Das 
---
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
index 87f171145a23..5fcade2b6054 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_kms.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -181,10 +182,11 @@ const struct rzg2l_du_format_info *rzg2l_du_format_info(u32 fourcc)
 int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device *dev,
 			 struct drm_mode_create_dumb *args)
 {
-	unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
-	unsigned int align = 16 * args->bpp / 8;
+	int ret;
 
-	args->pitch = roundup(min_pitch, align);
+	ret = drm_mode_size_dumb(dev, args, 16 * args->bpp / 8, 0);
+	if (ret)
+		return ret;
 
 	return drm_gem_dma_dumb_create_internal(file, dev, args);
 }
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Heiko Stuebner ,
	Sandy Huang ,
	Andy Yan 
Subject: [PATCH v6 19/25] drm/rockchip: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:26 +0200
Message-ID: <20250821081918.79786-20-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch to a multiple of 64.

Signed-off-by: Thomas Zimmermann 
Acked-by: Heiko Stuebner 
Cc: Sandy Huang 
Cc: "Heiko Stübner" 
Cc: Andy Yan 
---
 drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
index 6330b883efc3..3bd06202e232 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c
@@ -9,6 +9,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -403,13 +404,12 @@ int rockchip_gem_dumb_create(struct drm_file *file_priv,
 			     struct drm_mode_create_dumb *args)
 {
 	struct rockchip_gem_object *rk_obj;
-	int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+	int ret;
 
-	/*
-	 * align to 64 bytes since Mali requires it.
-	 */
-	args->pitch = ALIGN(min_pitch, 64);
-	args->size = args->pitch * args->height;
+	/* 64-byte alignment required by Mali */
+	ret = drm_mode_size_dumb(dev, args, SZ_64, 0);
+	if (ret)
+		return ret;
 
 	rk_obj = rockchip_gem_create_with_handle(file_priv, dev, args->size,
 						 &args->handle);
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Thierry Reding ,
	Thierry Reding ,
	Mikko Perttunen 
Subject: [PATCH v6 20/25] drm/tegra: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:27 +0200
Message-ID: <20250821081918.79786-21-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.

Signed-off-by: Thomas Zimmermann 
Acked-by: Thierry Reding 
Cc: Thierry Reding 
Cc: Mikko Perttunen 
---
 drivers/gpu/drm/tegra/gem.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index 41a285ec889f..84719c9d8720 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -16,6 +16,7 @@
 #include 
 
 #include 
+#include 
 #include 
 
 #include "drm.h"
@@ -542,12 +543,13 @@ void tegra_bo_free_object(struct drm_gem_object *gem)
 int tegra_bo_dumb_create(struct drm_file *file, struct drm_device *drm,
 			 struct drm_mode_create_dumb *args)
 {
-	unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
 	struct tegra_drm *tegra = drm->dev_private;
 	struct tegra_bo *bo;
+	int ret;
 
-	args->pitch = round_up(min_pitch, tegra->pitch_align);
-	args->size = args->pitch * args->height;
+	ret = drm_mode_size_dumb(drm, args, tegra->pitch_align, 0);
+	if (ret)
+		return ret;
 
 	bo = tegra_bo_create_with_handle(file, drm, args->size, 0,
 					 &args->handle);
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
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	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Matthew Auld ,
	Lucas De Marchi ,
	=?UTF-8?q?Thomas=20Hellstr=C3=B6m?= ,
	Rodrigo Vivi 
Subject: [PATCH v6 23/25] drm/xe: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:30 +0200
Message-ID: <20250821081918.79786-24-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. Align the pitch to a multiple of 8. Align the
buffer size according to hardware requirements.

Xe's internal calculation allowed for 64-bit wide buffer sizes, but
the ioctl's internal checks always verified against 32-bit wide limits.
Hance, it is safe to limit the driver code to 32-bit calculations as
well.

v3:
- mention 32-bit calculation in commit description (Matthew)

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Matthew Auld 
Cc: Lucas De Marchi 
Cc: "Thomas Hellström" 
Cc: Rodrigo Vivi 
---
 drivers/gpu/drm/xe/xe_bo.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 6fea39842e1e..2be7a618165a 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -9,6 +9,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -3130,14 +3131,13 @@ int xe_bo_dumb_create(struct drm_file *file_priv,
 	struct xe_device *xe = to_xe_device(dev);
 	struct xe_bo *bo;
 	uint32_t handle;
-	int cpp = DIV_ROUND_UP(args->bpp, 8);
 	int err;
 	u32 page_size = max_t(u32, PAGE_SIZE,
 		xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K);
 
-	args->pitch = ALIGN(args->width * cpp, 64);
-	args->size = ALIGN(mul_u32_u32(args->pitch, args->height),
-			   page_size);
+	err = drm_mode_size_dumb(dev, args, SZ_64, page_size);
+	if (err)
+		return err;
 
 	bo = xe_bo_create_user(xe, NULL, NULL, args->size,
 			       DRM_XE_GEM_CPU_CACHING_WC,
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
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	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Laurent Pinchart ,
	Kieran Bingham ,
	Laurent Pinchart ,
	Tomi Valkeinen 
Subject: [PATCH v6 17/25] drm/renesas/rcar-du: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:24 +0200
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.

Signed-off-by: Thomas Zimmermann 
Cc: Laurent Pinchart 
Cc: Kieran Bingham 
Reviewed-by: Laurent Pinchart 
Reviewed-by: Tomi Valkeinen 
---
 drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c
index 216219accfd9..6294443f6068 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_kms.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -407,8 +408,8 @@ int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
 			struct drm_mode_create_dumb *args)
 {
 	struct rcar_du_device *rcdu = to_rcar_du_device(dev);
-	unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
 	unsigned int align;
+	int ret;
 
 	/*
 	 * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
@@ -419,7 +420,9 @@ int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
 	else
 		align = 16 * args->bpp / 8;
 
-	args->pitch = roundup(min_pitch, align);
+	ret = drm_mode_size_dumb(dev, args, align, 0);
+	if (ret)
+		return ret;
 
 	return drm_gem_dma_dumb_create_internal(file, dev, args);
 }
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Laurent Pinchart 
Subject: [PATCH v6 25/25] drm/xlnx: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:32 +0200
Message-ID: <20250821081918.79786-26-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
buffer size. Align the pitch according to hardware requirements.

Signed-off-by: Thomas Zimmermann 
Cc: Laurent Pinchart 
Cc: Tomi Valkeinen 
Reviewed-by: Laurent Pinchart 
Reviewed-by: Tomi Valkeinen 
---
 drivers/gpu/drm/xlnx/zynqmp_kms.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c b/drivers/gpu/drm/xlnx/zynqmp_kms.c
index 2bee0a2275ed..02f3a7d78cf8 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_kms.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -363,10 +364,12 @@ static int zynqmp_dpsub_dumb_create(struct drm_file *file_priv,
 				    struct drm_mode_create_dumb *args)
 {
 	struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(drm);
-	unsigned int pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+	int ret;
 
 	/* Enforce the alignment constraints of the DMA engine. */
-	args->pitch = ALIGN(pitch, dpsub->dma_align);
+	ret = drm_mode_size_dumb(drm, args, dpsub->dma_align, 0);
+	if (ret)
+		return ret;
 
 	return drm_gem_dma_dumb_create_internal(file_priv, drm, args);
 }
-- 
2.50.1



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From: Thomas Zimmermann 
To: simona@ffwll.ch,
	airlied@gmail.com,
	mripard@kernel.org,
	maarten.lankhorst@linux.intel.com,
	geert@linux-m68k.org,
	tomi.valkeinen@ideasonboard.com
Cc: dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org,
	freedreno@lists.freedesktop.org,
	linux-arm-msm@vger.kernel.org,
	imx@lists.linux.dev,
	linux-samsung-soc@vger.kernel.org,
	nouveau@lists.freedesktop.org,
	virtualization@lists.linux.dev,
	spice-devel@lists.freedesktop.org,
	linux-renesas-soc@vger.kernel.org,
	linux-rockchip@lists.infradead.org,
	linux-tegra@vger.kernel.org,
	intel-xe@lists.freedesktop.org,
	xen-devel@lists.xenproject.org,
	Thomas Zimmermann ,
	Zack Rusin ,
	Broadcom internal kernel review list 
Subject: [PATCH v6 22/25] drm/vmwgfx: Compute dumb-buffer sizes with drm_mode_size_dumb()
Date: Thu, 21 Aug 2025 10:17:29 +0200
Message-ID: <20250821081918.79786-23-tzimmermann@suse.de>
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Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
and buffer size. No alignment required.

Signed-off-by: Thomas Zimmermann 
Reviewed-by: Zack Rusin 
Cc: Zack Rusin 
Cc: Broadcom internal kernel review list 
---
 drivers/gpu/drm/vmwgfx/vmwgfx_surface.c | 21 ++++-----------------
 1 file changed, 4 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
index 7e281c3c6bc5..c4ac9b47e23a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
@@ -15,6 +15,7 @@
 #include "vmw_surface_cache.h"
 #include "device_include/svga3d_surfacedefs.h"
 
+#include 
 #include 
 
 #define SVGA3D_FLAGS_64(upper32, lower32) (((uint64_t)upper32 << 32) | lower32)
@@ -2267,23 +2268,9 @@ int vmw_dumb_create(struct drm_file *file_priv,
 	 * contents is going to be rendered guest side.
 	 */
 	if (!dev_priv->has_mob || !vmw_supports_3d(dev_priv)) {
-		int cpp = DIV_ROUND_UP(args->bpp, 8);
-
-		switch (cpp) {
-		case 1: /* DRM_FORMAT_C8 */
-		case 2: /* DRM_FORMAT_RGB565 */
-		case 4: /* DRM_FORMAT_XRGB8888 */
-			break;
-		default:
-			/*
-			 * Dumb buffers don't allow anything else.
-			 * This is tested via IGT's dumb_buffers
-			 */
-			return -EINVAL;
-		}
-
-		args->pitch = args->width * cpp;
-		args->size = ALIGN(args->pitch * args->height, PAGE_SIZE);
+		ret = drm_mode_size_dumb(dev, args, 0, 0);
+		if (ret)
+			return ret;
 
 		ret = vmw_gem_object_create_with_handle(dev_priv, file_priv,
 							args->size, &args->handle,
-- 
2.50.1



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From: Mykyta Poturai 
To: Jan Beulich , Stefano Stabellini
	
CC: "xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH v2 2/3] pci/rcar: implement OSID configuration for Renesas
 RCar Gen4 PCIe host
Thread-Topic: [PATCH v2 2/3] pci/rcar: implement OSID configuration for
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Date: Thu, 21 Aug 2025 08:39:10 +0000
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Subject: Re: [PATCH] misra: consider conversion from UL or (void*) to function
 pointer as safe
To: Nicola Vetrini 
Cc: Dmytro Prokopchuk1 ,
 Doug Goldstein ,
 Stefano Stabellini ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 21.08.2025 10:25, Nicola Vetrini wrote:
> On 2025-08-21 10:01, Jan Beulich wrote:
>> On 19.08.2025 20:55, Dmytro Prokopchuk1 wrote:
>>> Rule 11.1 states as following: "Conversions shall not be performed
>>> between a pointer to a function and any other type."
>>>
>>> The conversion from unsigned long or (void *) to a function pointer
>>> is safe in Xen because the architectures it supports (e.g., x86 and
>>> ARM) guarantee compatible representations between these types.
>>
>> I think we need to be as precise as possible here. The architectures
>> guarantee nothing, they only offer necessary fundamentals. In the
>> Windows x86 ABI, for example, you can't convert pointers to/from longs
>> without losing data. What we build upon is what respective ABIs say,
>> possibly in combination of implementation specifics left to compilers.
>>
> 
> +1, a mention of the compilers and targets this deviation relies upon is 
> needed.
> 
>>> --- a/docs/misra/deviations.rst
>>> +++ b/docs/misra/deviations.rst
>>> @@ -370,6 +370,16 @@ Deviations related to MISRA C:2012 Rules:
>>>         to store it.
>>>       - Tagged as `safe` for ECLAIR.
>>>
>>> +   * - R11.1
>>> +     - The conversion from unsigned long or (void \*) to a function 
>>> pointer does
>>> +       not lose any information or violate type safety assumptions if 
>>> unsigned
>>> +       long or (void \*) type is guaranteed to be the same bit size 
>>> as a
>>> +       function pointer. This ensures that the function pointer can 
>>> be fully
>>> +       represented without truncation or corruption. The macro 
>>> BUILD_BUG_ON is
>>> +       integrated into xen/common/version.c to confirm conversion 
>>> compatibility
>>> +       across all target platforms.
>>> +     - Tagged as `safe` for ECLAIR.
>>
>> Why the escaping of * here, when ...
>>
>>> --- a/docs/misra/rules.rst
>>> +++ b/docs/misra/rules.rst
>>> @@ -431,7 +431,13 @@ maintainers if you want to suggest a change.
>>>       - All conversions to integer types are permitted if the 
>>> destination
>>>         type has enough bits to hold the entire value. Conversions to 
>>> bool
>>>         and void* are permitted. Conversions from 'void noreturn 
>>> (*)(...)'
>>> -       to 'void (*)(...)' are permitted.
>>> +       to 'void (*)(...)' are permitted. Conversions from unsigned 
>>> long or
>>> +       (void \*) to a function pointer are permitted if the source 
>>> type has
>>> +       enough bits to restore function pointer without truncation or 
>>> corruption.
>>> +       Example::
>>> +
>>> +           unsigned long func_addr = (unsigned long)&some_function;
>>> +           void (*restored_func)(void) = (void (*)(void))func_addr;
>>
>> ... context here suggests they work fine un-escaped, and you even add 
>> some un-
>> escaped instances as well. Perhaps I'm simply unaware of some 
>> peculiarity?
> 
> This is a literal rst block, while the other is not (* acts as a bullet 
> point in rst iirc)

But everything here is bullet-pointed (with at least two levels)?

Jan


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Subject: Re: [PATCH v2 2/3] xen/pci: modify pci_add_device to handle device
 add by Xen
To: Mykyta Poturai 
Cc: Luca Fancellu ,
 Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" ,
 Daniel Smith 
References: 
 
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From: Jan Beulich 
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On 20.08.2025 14:28, Mykyta Poturai wrote:
> From: Luca Fancellu 
> 
> Currently pci_add_device is called from hypercalls requested by Dom0
> to add pci devices and when the device has no domain associated with
> it, it is assumed that hardware_domain is the owner.
> 
> On the dom0less scenario, the enumeration is performed by the
> firmware and Xen at boot time might want to assign some pci devices
> to guests, so it has to firstly add the device and then assign it to
> the final guest.
> 
> Modify pci_add_device to have the owner domain passed as a parameter
> to the function, so that when it is called from the hypercall the
> owner would be the caller domain, otherwise when Xen is calling it,
> it would be another domain since hw domain could not be there
> (dom0less guests without Dom0 use case).
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Mykyta Poturai 
> ---
> (cherry picked from commit f0c85d9043f7c9402e85b73361c8a13c683428ca from
>  the downstream branch poc/pci-passthrough from
>  https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git)
> 
> v1->v2:
> * remove dom_io check
> * fixup pci_add_device parameters
> * use current->domain instead of hardware_domain

What I'm missing (as per my v1 comment) is discussion of the hardware_domain
-> current->domain change, including the XSM aspect. Because of the XSM aspect,
please also Cc the XSM maintainer going forward (I'm adding him here as well).

> --- a/xen/drivers/passthrough/pci.c
> +++ b/xen/drivers/passthrough/pci.c
> @@ -654,8 +654,9 @@ unsigned int pci_size_mem_bar(pci_sbdf_t sbdf, unsigned int pos,
>      return is64bits ? 2 : 1;
>  }
>  
> -int pci_add_device(u16 seg, u8 bus, u8 devfn,
> -                   const struct pci_dev_info *info, nodeid_t node)
> +int pci_add_device(uint16_t seg, uint8_t bus, uint8_t devfn,
> +                   const struct pci_dev_info *info, nodeid_t node,
> +                   struct domain *d)
>  {
>      struct pci_seg *pseg;
>      struct pci_dev *pdev;
> @@ -663,6 +664,9 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn,
>      const char *type;
>      int ret;
>  
> +    if ( !d )
> +        return -EINVAL;

This should't be needed. Very remotely ASSERT(d) could be added here, but
we don't normally do so elsewhere.

> @@ -767,9 +771,9 @@ int pci_add_device(u16 seg, u8 bus, u8 devfn,
>      ret = 0;
>      if ( !pdev->domain )
>      {
> -        pdev->domain = hardware_domain;
> -        write_lock(&hardware_domain->pci_lock);
> -        list_add(&pdev->domain_list, &hardware_domain->pdev_list);
> +        pdev->domain = d;
> +        write_lock(&d->pci_lock);
> +        list_add(&pdev->domain_list, &pdev->domain->pdev_list);

Why pdev->domain instead of the shorter and more efficient d?

Jan


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Date: Thu, 21 Aug 2025 11:08:05 +0200
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Subject: Re: [PATCH v2 3/3] xen/pci: add discovered PCI device at boot
To: Mykyta Poturai 
Cc: Luca Fancellu ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "Daniel P. Smith" ,
 "xen-devel@lists.xenproject.org" 
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On 20.08.2025 14:28, Mykyta Poturai wrote:
> From: Luca Fancellu 
> 
> In dom0less mode, there is no dom0 that can call PCI physdev ops to
> register PCI devices to iommu, so it needs to be done by Xen.
> pci_add_device requires some default domain, we don't have hwdom, and
> the guests are not yet created during the PCI init phase, so use dom_io
> as a temporary sentinel before devices are assigned to their target
> domains.
> 
> Rename setup_hwdom_pci_devices to setup_pci_devices and add dom0less
> handling to it.
> 
> In pci_add_device there is a call to xsm that doesn't consider the
> requester of the function to be Xen itself, so add a check to skip
> the call if the owner domain is dom_io, since it means the call is
> coming directly from Xen.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Mykyta Poturai 
> ---
> (cherry picked from commit eff51e50021b75f5a50533f7de681b2ce044f5bd from
>  the downstream branch poc/pci-passthrough from
>  https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git)
> 
> v1->v2:
> * integrate add_discovered_pci_devices into existing routines
> * better explain the need for dom_io

What I continue to miss is an explanation of why devices can't go to their
ultimate "destination" domain right away (once those have been created),
i.e. why the dom_io intermediary is necessary in the first place.

> --- a/xen/drivers/passthrough/pci.c
> +++ b/xen/drivers/passthrough/pci.c
> @@ -35,6 +35,7 @@
>  #include 
>  #include 
>  #include "ats.h"
> +#include "xen/dom0less-build.h"

No, please don't, at the very least not this way (using quotes rather than
angle brackets). I may guess that it's for is_dom0less_mode(), but even
then I wonder whether that declaration wouldn't better move elsewhere. It
simply feels somewhat wrong to include this header here.

> @@ -1181,19 +1185,21 @@ int __init scan_pci_devices(void)
>      return ret;
>  }
>  
> -struct setup_hwdom {
> +struct setup_ctxt {
>      struct domain *d;
>      int (*handler)(uint8_t devfn, struct pci_dev *pdev);
>  };
>  
> -static void __hwdom_init setup_one_hwdom_device(const struct setup_hwdom *ctxt,
> +static void __hwdom_init setup_one_pci_device(const struct setup_ctxt *ctxt,
>                                                  struct pci_dev *pdev)

Nit: Indentation then also needds to change on this following line.

>  {
>      u8 devfn = pdev->devfn;
> -    int err;
> +    int err = 0;

This doesn't suffice, as ...

>      do {
> -        err = ctxt->handler(devfn, pdev);
> +        if ( ctxt->handler )
> +            err = ctxt->handler(devfn, pdev);
> +
>          if ( err )
>          {
>              printk(XENLOG_ERR "setup %pp for d%d failed (%d)\n",

... below here we may continue the loop even if we got an error. "err"
needs setting unconditionally in the loop body, and hence maybe better
with a conditional expression.

> @@ -1229,18 +1235,26 @@ static int __hwdom_init cf_check _setup_hwdom_pci_devices(
>              if ( !pdev )
>                  continue;
>  
> +            if ( is_dom0less_mode() ) {

We're in a __hwdom_init function. You can't call an __init one from here.

Also nit (style): Brace placement.

> +                int ret = pci_add_device(pdev->seg, pdev->bus, pdev->devfn, NULL,
> +                                         NUMA_NO_NODE, ctxt->d);
> +                if (ret)

Nit (style): Missing blanks.

> --- a/xen/include/xen/pci.h
> +++ b/xen/include/xen/pci.h
> @@ -220,9 +220,8 @@ int scan_pci_devices(void);
>  enum pdev_type pdev_type(u16 seg, u8 bus, u8 devfn);
>  int find_upstream_bridge(u16 seg, u8 *bus, u8 *devfn, u8 *secbus);
>  
> -void setup_hwdom_pci_devices(struct domain *d,
> -                             int (*handler)(uint8_t devfn,
> -                                            struct pci_dev *pdev));
> +void setup_pci_devices(struct domain *d, int (*handler)(uint8_t devfn,
> +                                                        struct pci_dev *pdev));

I think in this case the 2nd parameter would better remain on the following
line, to limit overall indentation.

Jan


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Subject: Re: [PATCH] misra: add deviation for MISRA C Rule 11.3
To: Dmytro Prokopchuk1 
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On 20.08.2025 09:17, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 11.3 states: "A cast shall not be performed between a pointer
> to object type and a pointer to a different object type."
> 
> Violations of this rule arise due to the 'container_of' macro, which casts
> a member of a structure to its containing structure:
>     container_of(ptr, type, member) ({                             \
>            typeof_field(type, member) *__mptr = (ptr);             \
>            (type *)( (char *)__mptr - offsetof(type,member) );})
> 
> The 'container_of' macro is safe because it relies on the standardized and
> well-defined 'offsetof' macro to calculate the memory address of the
> containing structure, while assuming proper alignment and ensuring no
> undefined behavior, provided that the input pointer is valid and points to
> the specified member.
> 
> Configure Eclair to suppress violation reports related to 'container_of
> macro. Update 'deviations.rst' file accordingly. Add Rule 11.3 to the
> monitored list.
> No functional changes.
> 
> Signed-off-by: Dmytro Prokopchuk 

Looks largely okay; just one nit and a question:

> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -403,6 +403,14 @@ because the semantics of the 'noreturn' attribute do not alter the calling conve
>  }
>  -doc_end
>  
> +-doc_begin="Convesions in the 'container_of' macro are safe because it relies on

"Conversions" (also in deviations.rst)

> --- a/automation/eclair_analysis/ECLAIR/monitored.ecl
> +++ b/automation/eclair_analysis/ECLAIR/monitored.ecl
> @@ -45,6 +45,7 @@
>  -enable=MC3A2.R10.2
>  -enable=MC3A2.R11.1
>  -enable=MC3A2.R11.2
> +-enable=MC3A2.R11.3

While the description mentions this change, it doesn't say why (e.g. "no
violations left" or "only this and that violation left" or some such).

> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -393,6 +393,14 @@ Deviations related to MISRA C:2012 Rules:
>         (i.e., less strict) alignment requirement are safe.
>       - Tagged as `safe` for ECLAIR.
>  
> +   * - R11.3
> +     - Convesions in the 'container_of' macro are safe because it relies on
> +       the standardized and well-defined 'offsetof' macro to calculate the memory

Actually another nit: Here as well as in the description, it would be nice
to add parentheses, so indicate the function-ness of both macros (i.e.
container_of() and offsetof()).

Jan


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On 21/08/2025 8:26 am, Jan Beulich wrote:
> On 20.08.2025 14:15, Andrew Cooper wrote:
>> On 15/07/2025 7:33 am, Jan Beulich wrote:
>>> It's unclear to me why we have git create a tarball, extract that, just
>>> to then make a tarball again (without any special options, like to
>>> override owner or timestamps;
>> That's because in c5be91eb8140 you deleted the intermediate step of
>> merging qemus
> Hmm, perhaps - I'm generally trying to keep the size of such changes down,
> when working in an area I'm not overly familiar with.
>
>>> in this context I notice that tarballs
>>> created by Andrew have file ownership of andrew/andrew, while ones made
>>> by Julien use root/root).
>> Ownership where exactly?  the tarball itself (which will be down to
>> accounts on downloads.xenproject.org) or the tarball contents itself?
> tarball contents.
>
>>> lzip, unlike the other two tools, doesn't really show a progress
>>> indicator with -v. Merely having final statistics may make the use of
>>> the option here questionable.
>> I can't say I find any of the stats relevant.
> Happy to drop the v options.
>
>>> --- a/tools/misc/mktarball
>>> +++ b/tools/misc/mktarball
>>> @@ -31,4 +31,14 @@ git_archive_into $xen_root $tdir/xen-$de
>>>  
>>>  GZIP=-9v tar cz -f $xen_root/dist/xen-$desc.tar.gz -C $tdir xen-$desc
>>>  
>>> -echo "Source tarball in $xen_root/dist/xen-$desc.tar.gz"
>>> +if [ -n "$(command -v xz)" ]
>>> +then
>>> +  tar c -C $tdir xen-$desc | $(command -v xz) -v -9 >$xen_root/dist/xen-$desc.tar.xz
>>> +fi
>>> +
>>> +if [ -n "$(command -v lzip)" ]
>>> +then
>>> +  tar c -C $tdir xen-$desc | $(command -v lzip) -v -9 >$xen_root/dist/xen-$desc.tar.lz
>>> +fi
>>> +
>>> +echo "Source tarball in $xen_root/dist/xen-$desc".tar.[glx]z
>> If we're deciding to use multiple compressions, they want to not be
>> optional here.  I'd far rather have a reminder to install the package,
>> than for it to simply be omitted.
>>
>> We don't want to be re-tar-ing now that the qemu's are gone, so I think
>> the structure wants to end up as:
>>
>> git archive --format=tar HEAD > tmp.tar
>> gzip -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.gz &
>> zx -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.xz &
>> lzip -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.lz &
>> wait
>>
>> Might as well use the multiple cores better...
> I, too, was thinking of that. Yet as per above, when fiddling with code I'm
> not overly familiar with, I try to limit the amount of change done. As you
> ask for a bigger change, I can certainly do so.

Would you like me to do the patch then?

~Andrew


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Date: Thu, 21 Aug 2025 11:35:48 +0200
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Subject: Re: [PATCH] misra: fix Rule 11.3 violation in
 'vcpu_mark_events_pending'
To: Dmytro Prokopchuk1 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 "xen-devel@lists.xenproject.org" 
References: <7210337994620b60ed123ec6fc73e469c287adf6.1755676142.git.dmytro_prokopchuk1@epam.com>
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On 20.08.2025 10:00, Dmytro Prokopchuk1 wrote:
> MISRA C:2012 Rule 11.3 states: "A cast shall not be performed between
> a pointer to object type and a pointer to a different object type."
> 
> The function 'vcpu_mark_events_pending' contains a non-compliant cast
> to (unsigned long*). Remove the explicit cast and pass the compatible
> pointer type to the 'guest_test_and_set_bit' macro.

No-where up to here (incl the subject) it is said that this is an Arm-
only issue. Hence why I ended up looking in the first place.

> Fixes: c626aa1a5a (arm: implement event injection, 2012-06-01)
> Signed-off-by: Dmytro Prokopchuk 
> ---
> Test CI pipeline:
> https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1993054203
> ---
>  xen/arch/arm/domain.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index 310c578909..6371e68cc7 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -1166,7 +1166,7 @@ void arch_dump_vcpu_info(struct vcpu *v)
>  void vcpu_mark_events_pending(struct vcpu *v)
>  {
>      bool already_pending = guest_test_and_set_bit(v->domain,
> -        0, (unsigned long *)&vcpu_info(v, evtchn_upcall_pending));
> +        0, &vcpu_info(v, evtchn_upcall_pending));

It'll be Arm maintainers to judge, but my take is that the previously
questionable construct better wouldn't be made yet more questionable.
What's missing, at least for Arm32 aiui, is a (build-time) check that
the field actually lives at a 32-bit boundary and that read-modify-
write operations carried out on it at 32-bit width (this is true even
for Arm64) won't have an impact on what follows (this may be possible
to cover by just a comment, as you can't really check for the absence
of struct fields).

Jan


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Date: Thu, 21 Aug 2025 10:40:36 +0100
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Subject: Re: [PATCH v12 1/6] altp2m: Drop p2m_altp2m_check() stubs on non-x86,
 move prototype, and guard uses
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To: =?UTF-8?Q?Petr_Bene=C5=A1?= ,
 xen-devel@lists.xenproject.org
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Shawn Anastasio ,
 Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Oleksii Kurochko ,
 Tamas K Lengyel ,
 Alexandru Isaila ,
 Petre Pircalabu 
References: 
 <44b4b60854cd7db6d529ff23bb228e9ac19a2a75.1753953832.git.w1benny@gmail.com>
From: Julien Grall 
In-Reply-To: <44b4b60854cd7db6d529ff23bb228e9ac19a2a75.1753953832.git.w1benny@gmail.com>
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Hi Petr,

On 31/07/2025 10:27, Petr Beneš wrote:
> From: Petr Beneš 
> 
> Remove the no‑op stubs from the ARM, PPC, and RISC‑V p2m headers and stop
> providing a stub in arch/x86/include/asm/p2m.h.
> 
> Declare p2m_altp2m_check() in xen/include/xen/p2m-common.h and gate all
> call sites with CONFIG_ALTP2M:
>   - wrap the fast_single_step block in hvm/monitor.c with #ifdef CONFIG_ALTP2M
>     (IS_ENABLED(CONFIG_ALTP2M) is not used here, because in the subsequent commit
>     hvm_vcpu::fast_single_step will be guarded by CONFIG_ALTP2M)
>   - make the vm_event.c path conditional via IS_ENABLED(CONFIG_ALTP2M)
> 
> No functional change intended: on builds without ALTP2M the calls are
> compiled out; on builds with ALTP2M behavior is unchanged.
> 
> Signed-off-by: Petr Beneš 
> Reviewed-by: Jan Beulich 

Acked-by: Julien Grall  # arm

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH] misra: add deviation for MISRA C Rule 18.3
To: Dmytro Prokopchuk1 
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On 20.08.2025 14:44, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 18.3 states:"The relational operators >, >=, < and <= shall
> not be applied to objects of pointer type except where they point into
> the same object."
> 
> Comparisons in the 'find_text_region()' function are safe because linker
> symbols '_stext' and '_etext' represent fixed virtual addresses within

All symbols, after linking, "represent fixed virtual addresses". Not sure
what you're actually meaning to get across here.

> the same '.text' region, and the function 'addr' argument is explicitly
> compared to known valid memory bounds ('text_start' and 'text_end')
> derived from these linker symbols:
>     if ( (void *)addr >= iter->text_start &&
>          (void *)addr <  iter->text_end )

Overall I don't think the deviation can be justified this way. Or else
the same could be said about other similar checks, which may not be
valid to deviate. One particularly important aspect that imo needs
discussing is the safety of the logic with code transformations in mind
that a compiler may in principle do (leveraging UB for optimization
purposes).

Jan


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 <5b87bb85-3e52-453e-82ab-6d4f9b7eec28@citrix.com>
Content-Language: en-US
From: Jan Beulich 
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In-Reply-To: <5b87bb85-3e52-453e-82ab-6d4f9b7eec28@citrix.com>
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On 21.08.2025 11:31, Andrew Cooper wrote:
> On 21/08/2025 8:26 am, Jan Beulich wrote:
>> On 20.08.2025 14:15, Andrew Cooper wrote:
>>> On 15/07/2025 7:33 am, Jan Beulich wrote:
>>>> It's unclear to me why we have git create a tarball, extract that, just
>>>> to then make a tarball again (without any special options, like to
>>>> override owner or timestamps;
>>> That's because in c5be91eb8140 you deleted the intermediate step of
>>> merging qemus
>> Hmm, perhaps - I'm generally trying to keep the size of such changes down,
>> when working in an area I'm not overly familiar with.
>>
>>>> in this context I notice that tarballs
>>>> created by Andrew have file ownership of andrew/andrew, while ones made
>>>> by Julien use root/root).
>>> Ownership where exactly?  the tarball itself (which will be down to
>>> accounts on downloads.xenproject.org) or the tarball contents itself?
>> tarball contents.
>>
>>>> lzip, unlike the other two tools, doesn't really show a progress
>>>> indicator with -v. Merely having final statistics may make the use of
>>>> the option here questionable.
>>> I can't say I find any of the stats relevant.
>> Happy to drop the v options.
>>
>>>> --- a/tools/misc/mktarball
>>>> +++ b/tools/misc/mktarball
>>>> @@ -31,4 +31,14 @@ git_archive_into $xen_root $tdir/xen-$de
>>>>  
>>>>  GZIP=-9v tar cz -f $xen_root/dist/xen-$desc.tar.gz -C $tdir xen-$desc
>>>>  
>>>> -echo "Source tarball in $xen_root/dist/xen-$desc.tar.gz"
>>>> +if [ -n "$(command -v xz)" ]
>>>> +then
>>>> +  tar c -C $tdir xen-$desc | $(command -v xz) -v -9 >$xen_root/dist/xen-$desc.tar.xz
>>>> +fi
>>>> +
>>>> +if [ -n "$(command -v lzip)" ]
>>>> +then
>>>> +  tar c -C $tdir xen-$desc | $(command -v lzip) -v -9 >$xen_root/dist/xen-$desc.tar.lz
>>>> +fi
>>>> +
>>>> +echo "Source tarball in $xen_root/dist/xen-$desc".tar.[glx]z
>>> If we're deciding to use multiple compressions, they want to not be
>>> optional here.  I'd far rather have a reminder to install the package,
>>> than for it to simply be omitted.
>>>
>>> We don't want to be re-tar-ing now that the qemu's are gone, so I think
>>> the structure wants to end up as:
>>>
>>> git archive --format=tar HEAD > tmp.tar
>>> gzip -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.gz &
>>> zx -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.xz &
>>> lzip -9 < tmp.tar > $xen_root/dist/xen-$desc.tar.lz &
>>> wait
>>>
>>> Might as well use the multiple cores better...
>> I, too, was thinking of that. Yet as per above, when fiddling with code I'm
>> not overly familiar with, I try to limit the amount of change done. As you
>> ask for a bigger change, I can certainly do so.
> 
> Would you like me to do the patch then?

No worries, I'll make a v2. It's just that in some cases I'm asked to limit changes
to what's strictly necessary, yet then (when I try to from the start) in others I'm
asked to make a bigger change.

Jan


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Subject: [PATCH v3 2/3] pci/rcar: implement OSID configuration for Renesas
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For IPMMU to be able to associate a specific PCI device with it's TLB
the BDF to OSID mapping needs to be set up in the host bridge. The
configured OSID is then emmited as a sideband data on the AXI bus during
PCI DMA transactions. OSID configuration registers are located in the
"app" region of the host bridge.

Map the "app" region on init and implement methods for setting up
BDF->OSID mappings

Signed-off-by: Mykyta Poturai 
Acked-by: Stefano Stabellini 
---
v2->v3:
* no changes

v1->v2:
* add Stefano's AB
---
 xen/arch/arm/pci/pci-host-rcar4.c | 148 ++++++++++++++++++++++++++++++
 xen/arch/arm/pci/pci-host-rcar4.h |  18 ++++
 2 files changed, 166 insertions(+)
 create mode 100644 xen/arch/arm/pci/pci-host-rcar4.h

diff --git a/xen/arch/arm/pci/pci-host-rcar4.c b/xen/arch/arm/pci/pci-host-=
rcar4.c
index 62d2130a63..9290c6cac5 100644
--- a/xen/arch/arm/pci/pci-host-rcar4.c
+++ b/xen/arch/arm/pci/pci-host-rcar4.c
@@ -16,6 +16,32 @@
=20
 #define RCAR4_DWC_VERSION       0x520A
=20
+/* PCIE BDF-OSID assignment */
+#define CNVID(n)             (0x700 + ((n) * 4))
+#define CNVID_CNV_EN         (1U << 31)
+#define CNVID_OSID_MASK      (0x0F << 16)
+#define CNVID_OSID_SHIFT     16
+#define CNVID_BDF_MASK       (0xFFFF << 0)
+#define CNVID_BDF_SHIFT      0
+
+#define CNVIDMSK(n)                (0x780 + ((n) * 4))
+#define CNVIDMSK_BDF_MSK_MASK      (0xFFFF << 0)
+#define CNVIDMSK_BDF_MSK_SHIFT     0
+
+#define CNVOSIDCTRL                0x800
+#define CNVOSIDCTRL_OSID_MASK      (0x0F << 16)
+#define CNVOSIDCTRL_OSID_SHIFT     16
+
+#define DEFAULT_OSID    0
+
+#define NUM_OSID_REGS    16
+
+struct rcar4_pcie_priv {
+    bool init_done;
+    void __iomem *app_base;
+    DECLARE_BITMAP(osid_regs, NUM_OSID_REGS);
+};
+
 /*
  * PCI host bridges often have different ways to access the root and child
  * bus config spaces:
@@ -65,17 +91,139 @@ static const struct dt_device_match __initconstrel rca=
r4_pcie_dt_match[] =3D {
     {},
 };
=20
+static void rcar4_pcie_writel_app(struct rcar4_pcie_priv *pci, uint32_t re=
g,
+                                  uint32_t val)
+{
+    writel(val, pci->app_base + reg);
+}
+
+static uint32_t rcar4_pcie_readl_app(struct rcar4_pcie_priv *pci, uint32_t=
 reg)
+{
+    return readl(pci->app_base + reg);
+}
+
+int rcar4_pcie_osid_regs_init(struct pci_host_bridge *bridge)
+{
+    struct rcar4_pcie_priv *priv =3D dw_pcie_get_priv(bridge);
+    uint32_t val =3D rcar4_pcie_readl_app(priv, CNVOSIDCTRL);
+
+    if ( priv->init_done )
+        return 0;
+    priv->init_done =3D true;
+
+    val =3D (val & ~CNVOSIDCTRL_OSID_MASK) |
+          (DEFAULT_OSID << CNVOSIDCTRL_OSID_SHIFT);
+    rcar4_pcie_writel_app(priv, CNVOSIDCTRL, val);
+    bitmap_zero(priv->osid_regs, NUM_OSID_REGS);
+
+    printk("%s: Initialized OSID regs (default OSID %u)\n",
+           bridge->dt_node->full_name, DEFAULT_OSID);
+
+    return 0;
+}
+
+int rcar4_pcie_osid_reg_alloc(struct pci_host_bridge *bridge)
+{
+    struct rcar4_pcie_priv *priv =3D dw_pcie_get_priv(bridge);
+    int ret;
+
+    ret =3D find_first_zero_bit(priv->osid_regs, NUM_OSID_REGS);
+    if ( ret !=3D NUM_OSID_REGS )
+        set_bit(ret, priv->osid_regs);
+    else
+        ret =3D -EBUSY;
+
+    return ret;
+}
+
+void rcar4_pcie_osid_reg_free(struct pci_host_bridge *bridge,
+                              unsigned int reg_id)
+{
+    struct rcar4_pcie_priv *priv =3D dw_pcie_get_priv(bridge);
+
+    clear_bit(reg_id, priv->osid_regs);
+}
+
+void rcar4_pcie_osid_bdf_set(struct pci_host_bridge *bridge,
+                             unsigned int reg_id, uint32_t osid, uint32_t =
bdf)
+{
+    struct rcar4_pcie_priv *priv =3D dw_pcie_get_priv(bridge);
+    uint32_t data =3D rcar4_pcie_readl_app(priv, CNVID(reg_id));
+
+    data &=3D ~(CNVID_OSID_MASK | CNVID_BDF_MASK);
+    data |=3D CNVID_CNV_EN | (osid << CNVID_OSID_SHIFT) |
+            (bdf << CNVID_BDF_SHIFT);
+    rcar4_pcie_writel_app(priv, CNVID(reg_id), data);
+}
+
+void rcar4_pcie_osid_bdf_clear(struct pci_host_bridge *bridge,
+                               unsigned int reg_id)
+{
+    struct rcar4_pcie_priv *priv =3D dw_pcie_get_priv(bridge);
+    uint32_t data =3D rcar4_pcie_readl_app(priv, CNVID(reg_id));
+
+    data &=3D ~CNVID_CNV_EN;
+    rcar4_pcie_writel_app(priv, CNVID(reg_id), data);
+}
+
+void rcar4_pcie_bdf_msk_set(struct pci_host_bridge *bridge, unsigned int r=
eg_id,
+                            uint32_t data)
+{
+    struct rcar4_pcie_priv *priv =3D dw_pcie_get_priv(bridge);
+
+    uint32_t val =3D rcar4_pcie_readl_app(priv, CNVIDMSK(reg_id));
+
+    val =3D (val & ~CNVIDMSK_BDF_MSK_MASK) | (data << CNVIDMSK_BDF_MSK_SHI=
FT);
+
+    rcar4_pcie_writel_app(priv, CNVIDMSK(reg_id), val);
+}
+
 static int __init pci_host_rcar4_probe(struct dt_device_node *dev,
                                        const void *data)
 {
     struct pci_host_bridge *bridge;
+    paddr_t app_phys_addr;
+    paddr_t app_size;
+    int app_idx, ret;
+
+    struct rcar4_pcie_priv *priv =3D xzalloc(struct rcar4_pcie_priv);
+    if ( !priv )
+        return -ENOMEM;
=20
     bridge =3D dw_pcie_host_probe(dev, data, &rcar4_pcie_ops,
                                 &rcar4_pcie_child_ops);
=20
+    app_idx =3D dt_property_match_string(dev, "reg-names", "app");
+    if ( app_idx < 0 )
+    {
+        printk(XENLOG_ERR "Cannot find \"app\" range index in device tree\=
n");
+        ret =3D app_idx;
+        goto err;
+    }
+    ret =3D dt_device_get_address(dev, app_idx, &app_phys_addr, &app_size)=
;
+    if ( ret )
+    {
+        printk(XENLOG_ERR "Cannot find \"app\" range in device tree\n");
+        goto err;
+    }
+
+    priv->app_base =3D ioremap_nocache(app_phys_addr, app_size);
+    if ( !priv->app_base )
+    {
+        printk(XENLOG_ERR "APP ioremap failed\n");
+        ret =3D -ENXIO;
+        goto err;
+    }
+    printk("APP at [mem 0x%" PRIpaddr "-0x%" PRIpaddr "]\n", app_phys_addr=
,
+           app_phys_addr + app_size - 1);
+
+    dw_pcie_set_priv(bridge, priv);
     dw_pcie_set_version(bridge, RCAR4_DWC_VERSION);
=20
     return 0;
+err:
+    xfree(priv);
+    return ret;
 }
=20
 DT_DEVICE_START(pci_gen, "PCI HOST R-CAR GEN4", DEVICE_PCI_HOSTBRIDGE)
diff --git a/xen/arch/arm/pci/pci-host-rcar4.h b/xen/arch/arm/pci/pci-host-=
rcar4.h
new file mode 100644
index 0000000000..8ac6626a22
--- /dev/null
+++ b/xen/arch/arm/pci/pci-host-rcar4.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include 
+
+#ifndef __PCI_HOST_RCAR4_H__
+#define __PCI_HOST_RCAR4_H__
+
+void rcar4_pcie_osid_bdf_set(struct pci_host_bridge *bridge,
+                             unsigned int reg_id, uint32_t osid, uint32_t =
bdf);
+void rcar4_pcie_osid_bdf_clear(struct pci_host_bridge *bridge,
+                               unsigned int reg_id);
+void rcar4_pcie_bdf_msk_set(struct pci_host_bridge *bridge, unsigned int r=
eg_id,
+                            uint32_t data);
+int rcar4_pcie_osid_reg_alloc(struct pci_host_bridge *bridge);
+void rcar4_pcie_osid_reg_free(struct pci_host_bridge *bridge,
+                              unsigned int reg_id);
+int rcar4_pcie_osid_regs_init(struct pci_host_bridge *bridge);
+
+#endif /* __PCI_HOST_RCAR4_H__ */
--=20
2.34.1


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From: Mykyta Poturai 
To: "xen-devel@lists.xenproject.org" 
CC: Mykyta Poturai 
Subject: [PATCH v3 0/3]  IPMMU handling for PCIe Passthrough on ARM
Thread-Topic: [PATCH v3 0/3]  IPMMU handling for PCIe Passthrough on ARM
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This series introduces IPMMU handling for PCIe passthrough on ARM. It inclu=
des
changes to pci-designware, pci-host-rcar and ipmmu-vmsa drivers to enable
configuring BDF->OSID->uTLB translation chain needed to pass different PCIe
devices to different domains.

Tested on RCar S4 Spider board.

v2->v3:
* see individual patches

v1->v2:
* see individual patches

Mykyta Poturai (2):
  arm/pci: allow designware-based hosts to have private data
  pci/rcar: implement OSID configuration for Renesas RCar Gen4 PCIe host

Oleksandr Tyshchenko (1):
  iommu/ipmmu-vmsa: Implement basic PCIE-IPMMU OSID support

 xen/arch/arm/pci/pci-designware.c        |  12 ++
 xen/arch/arm/pci/pci-designware.h        |   4 +
 xen/arch/arm/pci/pci-host-rcar4.c        | 148 +++++++++++++++++++++++
 xen/arch/arm/pci/pci-host-rcar4.h        |  18 +++
 xen/drivers/passthrough/arm/ipmmu-vmsa.c | 138 +++++++++++++++++++--
 5 files changed, 312 insertions(+), 8 deletions(-)
 create mode 100644 xen/arch/arm/pci/pci-host-rcar4.h

--=20
2.34.1


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From: Mykyta Poturai 
To: "xen-devel@lists.xenproject.org" 
CC: Mykyta Poturai , Stefano Stabellini
	
Subject: [PATCH v3 1/3] arm/pci: allow designware-based hosts to have private
 data
Thread-Topic: [PATCH v3 1/3] arm/pci: allow designware-based hosts to have
 private data
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Date: Thu, 21 Aug 2025 10:15:31 +0000
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Introduce an additional private data field in `dw_pcie_priv` to allow
vendors to store custom data without interfering with bridge->priv.
Also add get/set pair to make accesing that private data less
cumbersome.

Signed-off-by: Mykyta Poturai 
Acked-by: Stefano Stabellini 
---
v2->v3:
* no changes

v1->v2:
* add Stefano's AB
---
 xen/arch/arm/pci/pci-designware.c | 12 ++++++++++++
 xen/arch/arm/pci/pci-designware.h |  4 ++++
 2 files changed, 16 insertions(+)

diff --git a/xen/arch/arm/pci/pci-designware.c b/xen/arch/arm/pci/pci-desig=
nware.c
index 47dd2dd4c0..0bd67524ac 100644
--- a/xen/arch/arm/pci/pci-designware.c
+++ b/xen/arch/arm/pci/pci-designware.c
@@ -403,3 +403,15 @@ dw_pcie_host_probe(struct dt_device_node *dev, const v=
oid *data,
=20
     return bridge;
 }
+
+void *dw_pcie_get_priv(struct pci_host_bridge *bridge)
+{
+    struct dw_pcie_priv *priv =3D bridge->priv;
+    return priv->priv;
+}
+
+void dw_pcie_set_priv(struct pci_host_bridge *bridge, void *other)
+{
+    struct dw_pcie_priv *priv =3D bridge->priv;
+    priv->priv =3D other;
+}
diff --git a/xen/arch/arm/pci/pci-designware.h b/xen/arch/arm/pci/pci-desig=
nware.h
index 7efb1dc9a2..b9deb3b138 100644
--- a/xen/arch/arm/pci/pci-designware.h
+++ b/xen/arch/arm/pci/pci-designware.h
@@ -66,8 +66,12 @@ struct dw_pcie_priv {
     bool iatu_unroll_enabled;
     void __iomem *atu_base;
     unsigned int version;
+    void *priv;
 };
=20
+void *dw_pcie_get_priv(struct pci_host_bridge *bridge);
+void dw_pcie_set_priv(struct pci_host_bridge *bridge, void *other);
+
 void dw_pcie_set_version(struct pci_host_bridge *bridge, unsigned int vers=
ion);
=20
 void __iomem *dw_pcie_child_map_bus(struct pci_host_bridge *bridge,
--=20
2.34.1


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From: Mykyta Poturai 
To: "xen-devel@lists.xenproject.org" 
CC: Oleksandr Tyshchenko , Mykyta Poturai
	, Stefano Stabellini 
Subject: [PATCH v3 3/3] iommu/ipmmu-vmsa: Implement basic PCIE-IPMMU OSID
 support
Thread-Topic: [PATCH v3 3/3] iommu/ipmmu-vmsa: Implement basic PCIE-IPMMU OSID
 support
Thread-Index: AQHcEoSHUe5gc4yzc02M5y5xupQnTQ==
Date: Thu, 21 Aug 2025 10:15:32 +0000
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From: Oleksandr Tyshchenko 

Program PCIE BDF-OSID assignment according to the S4_PCIe_IPMMU-OSID
when adding PCI device to the IOMMU in ipmmu_add_device callback.
This is needed for being able to assign PCI devices to different
domains at the same time. Programmed OSID is emmited as sideband data on
the AXI bus during PCI DMA transactions and then used by IPMMU to match
the transaction to the corresponding uTLB.

Signed-off-by: Oleksandr Tyshchenko 
Signed-off-by: Mykyta Poturai 
Acked-by: Stefano Stabellini 
---
v2->v3:
* fix compilation error with HAS_PCI=3Dn
* add Stefano's AB

v1->v2:
* rework VF handling to be in line with SMMU drivers
* add locking to domain_list manipulations
* remove assignment print
---
 xen/drivers/passthrough/arm/ipmmu-vmsa.c | 138 +++++++++++++++++++++--
 1 file changed, 130 insertions(+), 8 deletions(-)

diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthr=
ough/arm/ipmmu-vmsa.c
index dac0dd6d46..49f149e222 100644
--- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
+++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
@@ -51,12 +51,27 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_HAS_PCI
+#include "../arch/arm/pci/pci-host-rcar4.h"
+#endif
=20
 #define dev_name(dev) dt_node_full_name(dev_to_dt(dev))
=20
 /* Device logger functions */
+#ifndef CONFIG_HAS_PCI
 #define dev_print(dev, lvl, fmt, ...)    \
     printk(lvl "ipmmu: %s: " fmt, dev_name(dev), ## __VA_ARGS__)
+#else
+#define dev_print(dev, lvl, fmt, ...) ({                                \
+    if ( !dev_is_pci((dev)) )                                           \
+        printk(lvl "ipmmu: %s: " fmt, dev_name((dev)), ## __VA_ARGS__);  \
+    else                                                                \
+    {                                                                   \
+        struct pci_dev *pdev =3D dev_to_pci((dev));                       =
\
+        printk(lvl "ipmmu: %pp: " fmt, &pdev->sbdf, ## __VA_ARGS__);     \
+    }                                                                   \
+})
+#endif
=20
 #define dev_info(dev, fmt, ...)    \
     dev_print(dev, XENLOG_INFO, fmt, ## __VA_ARGS__)
@@ -1125,6 +1140,8 @@ static void ipmmu_free_root_domain(struct ipmmu_vmsa_=
domain *domain)
     xfree(domain);
 }
=20
+static int ipmmu_deassign_device(struct domain *d, struct device *dev);
+
 static int ipmmu_assign_device(struct domain *d, u8 devfn, struct device *=
dev,
                                uint32_t flag)
 {
@@ -1138,8 +1155,38 @@ static int ipmmu_assign_device(struct domain *d, u8 =
devfn, struct device *dev,
     if ( !to_ipmmu(dev) )
         return -ENODEV;
=20
-    spin_lock(&xen_domain->lock);
+#ifdef CONFIG_HAS_PCI
+    if ( dev_is_pci(dev) )
+    {
+        struct pci_dev *pdev =3D dev_to_pci(dev);
+        struct domain *old_d =3D pdev->domain;
+
+        /* Ignore calls for phantom functions */
+        if ( devfn !=3D pdev->devfn )
+            return 0;
+
+        write_lock(&d->pci_lock);
+        list_move(&pdev->domain_list, &d->pdev_list);
+        write_unlock(&d->pci_lock);
+        pdev->domain =3D d;
+
+        /* dom_io is used as a sentinel for quarantined devices */
+        if ( d =3D=3D dom_io )
+        {
+            int ret;
+
+            /*
+             * Try to de-assign: do not return error if it was already
+             * de-assigned.
+             */
+            ret =3D ipmmu_deassign_device(old_d, dev);
+
+            return ret =3D=3D -ESRCH ? 0 : ret;
+        }
+    }
+#endif
=20
+    spin_lock(&xen_domain->lock);
     /*
      * The IPMMU context for the Xen domain is not allocated beforehand
      * (at the Xen domain creation time), but on demand only, when the fir=
st
@@ -1244,7 +1291,7 @@ static int ipmmu_reassign_device(struct domain *s, st=
ruct domain *t,
     int ret =3D 0;
=20
     /* Don't allow remapping on other domain than hwdom */
-    if ( t && !is_hardware_domain(t) )
+    if ( t && !is_hardware_domain(t) && (t !=3D dom_io) )
         return -EPERM;
=20
     if ( t =3D=3D s )
@@ -1292,20 +1339,95 @@ static int ipmmu_dt_xlate(struct device *dev,
=20
 static int ipmmu_add_device(u8 devfn, struct device *dev)
 {
-    struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev);
+    struct iommu_fwspec *fwspec;
+
+#ifdef CONFIG_HAS_PCI
+    if ( dev_is_pci(dev) )
+    {
+        struct pci_dev *pdev =3D dev_to_pci(dev);
+        int ret;
+
+        if ( devfn !=3D pdev->devfn )
+            return 0;
+
+        ret =3D iommu_add_pci_sideband_ids(pdev);
+        if ( ret < 0 )
+            iommu_fwspec_free(dev);
+    }
+#endif
+
+    fwspec =3D dev_iommu_fwspec_get(dev);
=20
     /* Only let through devices that have been verified in xlate(). */
     if ( !to_ipmmu(dev) )
         return -ENODEV;
=20
-    if ( dt_device_is_protected(dev_to_dt(dev)) )
+    if ( !dev_is_pci(dev) )
     {
-        dev_err(dev, "Already added to IPMMU\n");
-        return -EEXIST;
+        if ( dt_device_is_protected(dev_to_dt(dev)) )
+        {
+            dev_err(dev, "Already added to IPMMU\n");
+            return -EEXIST;
+        }
+
+        /* Let Xen know that the master device is protected by an IOMMU. *=
/
+        dt_device_set_protected(dev_to_dt(dev));
     }
+#ifdef CONFIG_HAS_PCI
+    if ( dev_is_pci(dev) )
+    {
+        struct pci_dev *pdev =3D dev_to_pci(dev);
+        unsigned int reg_id, osid;
+        struct pci_host_bridge *bridge;
+        struct iommu_fwspec *fwspec_bridge;
+        unsigned int utlb_osid0 =3D 0;
+        int ret;
+
+        bridge =3D pci_find_host_bridge(pdev->seg, pdev->bus);
+        if ( !bridge )
+        {
+            dev_err(dev, "Failed to find host bridge\n");
+            return -ENODEV;
+        }
+
+        fwspec_bridge =3D dev_iommu_fwspec_get(dt_to_dev(bridge->dt_node))=
;
+        if ( fwspec_bridge->num_ids < 1 )
+        {
+            dev_err(dev, "Failed to find host bridge uTLB\n");
+            return -ENXIO;
+        }
+
+        if ( fwspec->num_ids < 1 )
+        {
+            dev_err(dev, "Failed to find uTLB");
+            return -ENXIO;
+        }
+
+        rcar4_pcie_osid_regs_init(bridge);
+
+        ret =3D rcar4_pcie_osid_reg_alloc(bridge);
+        if ( ret < 0 )
+        {
+            dev_err(dev, "No unused OSID regs\n");
+            return ret;
+        }
+        reg_id =3D ret;
+
+        osid =3D fwspec->ids[0] - utlb_osid0;
+        rcar4_pcie_osid_bdf_set(bridge, reg_id, osid, pdev->sbdf.bdf);
+        rcar4_pcie_bdf_msk_set(bridge, reg_id, 0);
+
+        dev_info(dev, "Allocated OSID reg %u (OSID %u)\n", reg_id, osid);
=20
-    /* Let Xen know that the master device is protected by an IOMMU. */
-    dt_device_set_protected(dev_to_dt(dev));
+        ret =3D ipmmu_assign_device(pdev->domain, devfn, dev, 0);
+        if ( ret )
+        {
+            rcar4_pcie_osid_bdf_clear(bridge, reg_id);
+            rcar4_pcie_osid_reg_free(bridge, reg_id);
+            return ret;
+        }
+    }
+#endif
=20
     dev_info(dev, "Added master device (IPMMU %s micro-TLBs %u)\n",
              dev_name(fwspec->iommu_dev), fwspec->num_ids);
--=20
2.34.1


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Message-ID: 
Date: Thu, 21 Aug 2025 11:20:17 +0100
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3 3/3] iommu/ipmmu-vmsa: Implement basic PCIE-IPMMU OSID
 support
To: Mykyta Poturai ,
 "xen-devel@lists.xenproject.org" 
Cc: Oleksandr Tyshchenko ,
 Stefano Stabellini 
References: 
 
Content-Language: en-GB
From: Andrew Cooper 
Autocrypt: addr=andrew.cooper3@citrix.com; keydata=
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In-Reply-To: 
Content-Type: text/plain; charset=UTF-8
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On 21/08/2025 11:15 am, Mykyta Poturai wrote:
> diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> index dac0dd6d46..49f149e222 100644
> --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> @@ -1138,8 +1155,38 @@ static int ipmmu_assign_device(struct domain *d, u8 devfn, struct device *dev,
>      if ( !to_ipmmu(dev) )
>          return -ENODEV;
>  
> -    spin_lock(&xen_domain->lock);
> +#ifdef CONFIG_HAS_PCI
> +    if ( dev_is_pci(dev) )
> +    {
> +        struct pci_dev *pdev = dev_to_pci(dev);
> +        struct domain *old_d = pdev->domain;
> +
> +        /* Ignore calls for phantom functions */
> +        if ( devfn != pdev->devfn )
> +            return 0;
> +
> +        write_lock(&d->pci_lock);
> +        list_move(&pdev->domain_list, &d->pdev_list);
> +        write_unlock(&d->pci_lock);
> +        pdev->domain = d;
> +
> +        /* dom_io is used as a sentinel for quarantined devices */
> +        if ( d == dom_io )
> +        {
> +            int ret;
> +
> +            /*
> +             * Try to de-assign: do not return error if it was already
> +             * de-assigned.
> +             */
> +            ret = ipmmu_deassign_device(old_d, dev);
> +
> +            return ret == -ESRCH ? 0 : ret;
> +        }
> +    }
> +#endif
>  
> +    spin_lock(&xen_domain->lock);

Minor point.  You've removed a newline here, which is why the hunk is
not cleanly ahead of the spin_lock() call.

~Andrew


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Date: Thu, 21 Aug 2025 12:22:28 +0200
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Subject: Re: [PATCH v3 0/3] IPMMU handling for PCIe Passthrough on ARM
To: Mykyta Poturai 
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From: Jan Beulich 
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On 21.08.2025 12:15, Mykyta Poturai wrote:
> This series introduces IPMMU handling for PCIe passthrough on ARM. It includes
> changes to pci-designware, pci-host-rcar and ipmmu-vmsa drivers to enable
> configuring BDF->OSID->uTLB translation chain needed to pass different PCIe
> devices to different domains.
> 
> Tested on RCar S4 Spider board.
> 
> v2->v3:
> * see individual patches
> 
> v1->v2:
> * see individual patches
> 
> Mykyta Poturai (2):
>   arm/pci: allow designware-based hosts to have private data
>   pci/rcar: implement OSID configuration for Renesas RCar Gen4 PCIe host
> 
> Oleksandr Tyshchenko (1):
>   iommu/ipmmu-vmsa: Implement basic PCIE-IPMMU OSID support

These patches went in already, one causing a randconfig issue. What is this
re-posting about? Are you implying that the entire series is going to be
reverted? (I really expected an incremental patch to deal with the issue CI
ran into.)

Jan


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On Thu Aug 21, 2025 at 9:16 AM CEST, Jan Beulich wrote:
> On 20.08.2025 01:58, dmkhn@proton.me wrote:
>> On Thu, Aug 14, 2025 at 09:11:11AM +0200, Jan Beulich wrote:
>>> On 13.08.2025 00:30, dmkhn@proton.me wrote:
>>>> From: Denis Mukhin 
>>>>
>>>> Currently, there are two different domain ID allocation implementation=
s:
>>>>
>>>>   1) Sequential IDs allocation in dom0less Arm code based on max_init_=
domid;
>>>>
>>>>   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not us=
e
>>>>      max_init_domid (both Arm and x86).
>>>>
>>>> The domain ID allocation covers dom0 or late hwdom, predefined domains=
,
>>>> post-boot domains, excluding Xen system domains (domid >=3D
>>>> DOMID_FIRST_RESERVED).
>>>>
>>>> It makes sense to have a common helper code for such task across archi=
tectures
>>>> (Arm and x86) and between dom0less / toolstack domU allocation.
>>>>
>>>> Note, fixing dependency on max_init_domid is out of scope of this patc=
h.
>>>>
>>>> Wrap the domain ID allocation as an arch-independent function domid_al=
loc() in
>>>> new common/domid.c based on the bitmap.
>>>>
>>>> Allocation algorithm:
>>>> - If an explicit domain ID is provided, verify its availability and us=
e it if
>>>>   ID is not used;
>>>> - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESER=
VED-1],
>>>>   starting from the last used ID.
>>>>   Implementation guarantees that two consecutive calls will never retu=
rn the
>>>>   same ID. ID#0 is reserved for the first boot domain (currently, dom0=
) and
>>>>   excluded from the allocation range.
>>>>
>>>> Remove is_free_domid() helper as it is not needed now.
>>>>
>>>> No functional change intended.
>>>>
>>>> Signed-off-by: Denis Mukhin 
>>>> Reviewed-by: Julien Grall 
>>>> Reviewed-by: Alejandro Vallejo 
>>>> ---
>>>> Changes since v15:
>>>> - fixup for check after the first pass in the bitarray in domid_alloc(=
)
>>>> - trivial renaming for the local variable in domid_alloc()
>>>> - kept Julien's R-b, added Alejandro's R-b
>>>
>>> Just to mention: My take is that this kind of a fix ought to invalidate=
 all
>>> earlier R-b. It's not just a cosmetic change, after all.
>>=20
>> Sorry for the hiccup here, did not mean to overrule the review process.
>>=20
>> My bold assumption was that in case of small fixups like this it is
>> satisfactory to carry over previous acks.
>
> Acks may be okay to keep, but imo R-b need dropping when an actual bug wa=
s
> fixed.

I don't know. Unless the bugfix involves a change in the code with wide rea=
ching
consequences I'd say it's reasonable to keep them. But that's something for=
 you
(the committers) to decide, and this just my .02 cents.

> Irrespective of how severe the bug was.

It's not so much about the severity (imo), as the behavioural differences
involved in the fixup. In this case (afaics?) it's a straight s/=3D=3D/>=3D=
/, which is
self-contained and has no wide-reaching side effects at all.

>
>> I asked (matrix) both Julien and Alejandro to re-review and confirm.
>
> While good to ask, that's of limited use. It'll be impossible later on to
> figure whether such a confirmation was given. Decisions (and acks and ali=
ke
> effectively fall into that category) need to be on the list, to be able t=
o
> locate them later on.
>
> Jan

He meant he reached out to ask for an in-list confirmation. As far as I'm
concerned, my R-by still holds.

Cheers,
Alejandro


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Subject: Re: [PATCH] common/efi: deviate Rule 2.1 violation in read_file()
To: Dmytro Prokopchuk1 
Cc: Andrew Cooper ,
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On 20.08.2025 20:05, Dmytro Prokopchuk1 wrote:
> --- a/xen/common/efi/boot.c
> +++ b/xen/common/efi/boot.c
> @@ -852,7 +852,7 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
>      PrintErr(L" failed for ");
>      PrintErrMesg(name, ret);
>  
> -    /* not reached */
> +    /* SAF-15-safe deliberately unreachable code */
>      return false;
>  }

Much better (even if not tagged as v2). Yet then, did you consider
alternatives? For example, with PrintErrMesg() properly annotated "noreturn",
I'd kind of expect compilers to not object to the omission of the "return"
statement here. This would then let us get away without a new SAF comment.
While you explain in the SAF text why you retain the statement, I'm not
convinced of code clarity suffering if it was deleted, as long as a suitable
comment is still there. If PrintErrMesg() lost its "noreturn", surely
compilers would then diagnose the lack of "return".

Jan


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From: Mykyta Poturai 
To: Jan Beulich 
CC: "xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH v3 0/3] IPMMU handling for PCIe Passthrough on ARM
Thread-Topic: [PATCH v3 0/3] IPMMU handling for PCIe Passthrough on ARM
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Subject: Re: [PATCH 1/5] arm/mpu: Implement setup_frametable_mappings for MPU
 systems
To: Hari Limaye , 
CC: , Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Volodymyr Babchuk 
References: 
 
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On 30/07/2025 10:45, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Implement the MPU variant of `setup_frametable_mappings`. This function
> will be called by `setup_mm` when an implementation for MPU systems is
> added in a follow up commit.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
> ---
>  xen/arch/arm/mpu/mm.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
> index c6891607ec..6a16fa348d 100644
> --- a/xen/arch/arm/mpu/mm.c
> +++ b/xen/arch/arm/mpu/mm.c
> @@ -168,6 +168,25 @@ int mpumap_contains_region(pr_t *table, uint8_t nr_regions, paddr_t base,
>      return MPUMAP_REGION_NOTFOUND;
>  }
>  
> +/* Map a frame table to cover physical addresses ps through pe */
> +void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
> +{
> +    mfn_t base_mfn;
> +    unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(pe), -1)) -
> +                            mfn_to_pdx(maddr_to_mfn(ps)) + 1;
Don't you need to make sure that ps is rounded up to page size and e rounded down?

> +    unsigned long frametable_size = nr_pdxs * sizeof(struct page_info);
Why don't you need sanity checking with BUILD_BUG_ON to check frametable size?

> +
> +    frametable_base_pdx = paddr_to_pdx(ps);
> +    frametable_size = ROUNDUP(frametable_size, PAGE_SIZE);
> +
> +    base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1);
> +    frame_table = (struct page_info *)mfn_to_virt(mfn_x(base_mfn));
> +
> +    memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info));
> +    memset(&frame_table[nr_pdxs], -1,
> +           frametable_size - (nr_pdxs * sizeof(struct page_info)));
> +}
> +
>  /*
>   * Allocate an entry for a new EL2 MPU region in the bitmap xen_mpumap_mask.
>   * @param idx   Set to the index of the allocated EL2 MPU region on success.
Other than that:
Reviewed-by: Michal Orzel 

~Michal




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From: Mykyta Poturai 
To: "xen-devel@lists.xenproject.org" 
CC: Mykyta Poturai , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: [PATCH v1] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
Thread-Topic: [PATCH v1] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
Thread-Index: AQHcEol6WY2CZ9Gyh0KXEcdKpt6HNg==
Date: Thu, 21 Aug 2025 10:50:59 +0000
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With PCI disabled the build fails due to undefined struct
pci_host_bridge.

Add ifdef guard around pci-host-rcar4.h to not include it when PCI
support is disabled.

Signed-off-by: Mykyta Poturai 
---
This patch can be squashed with iommu/ipmmu-vmsa: Implement basic PCIE-IPMM=
U OSID support
---
 xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthr=
ough/arm/ipmmu-vmsa.c
index ea9fa9ddf3..49f149e222 100644
--- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
+++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
@@ -51,7 +51,9 @@
 #include 
 #include 
 #include 
+#ifdef CONFIG_HAS_PCI
 #include "../arch/arm/pci/pci-host-rcar4.h"
+#endif
=20
 #define dev_name(dev) dt_node_full_name(dev_to_dt(dev))
=20
--=20
2.34.1


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On 30/07/2025 10:45, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Implement `setup_mm` for MPU systems. This variant doesn't need to set
> up the direct map.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
> ---
>  xen/arch/arm/mpu/mm.c | 64 ++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 63 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
> index 6a16fa348d..0b05103180 100644
> --- a/xen/arch/arm/mpu/mm.c
> +++ b/xen/arch/arm/mpu/mm.c
> @@ -8,9 +8,12 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  struct page_info *frame_table;
> @@ -364,9 +367,68 @@ int map_pages_to_xen(unsigned long virt, mfn_t mfn, unsigned long nr_mfns,
>      return xen_mpumap_update(virt, mfn_to_maddr(mfn_add(mfn, nr_mfns)), flags);
>  }
>  
> +/*
> + * Heap must be statically configured in Device Tree through "xen,static-heap"
> + * on MPU systems.
> + */
> +static void __init setup_staticheap_mappings(void)
> +{
> +    const struct membanks *reserved_mem = bootinfo_get_reserved_mem();
> +    unsigned int bank = 0;
> +
> +    for ( ; bank < reserved_mem->nr_banks; bank++ )
> +    {
> +        if ( reserved_mem->bank[bank].type == MEMBANK_STATIC_HEAP )
> +        {
> +            paddr_t bank_start = round_pgup(reserved_mem->bank[bank].start);
> +            paddr_t bank_size = round_pgdown(reserved_mem->bank[bank].size);
> +            paddr_t bank_end = bank_start + bank_size;
> +
> +            /* Map static heap with one MPU protection region */
> +            if ( xen_mpumap_update(bank_start, bank_end, PAGE_HYPERVISOR) )
> +                panic("Failed to map static heap\n");
> +
> +            break;
> +        }
> +    }
> +
> +    if ( bank == reserved_mem->nr_banks )
> +        panic("No static heap memory bank found\n");
> +}
> +
>  void __init setup_mm(void)
>  {
> -    BUG_ON("unimplemented");
> +    const struct membanks *mem = bootinfo_get_mem();
> +    paddr_t ram_start = INVALID_PADDR, ram_end = 0, ram_size = 0;
> +
> +    if ( !mem->nr_banks )
> +        panic("No memory bank\n");
> +
> +    init_pdx();
> +
> +    populate_boot_allocator();
> +
> +    total_pages = 0;
There's no other place setting up total_pages between this and += ram_size
so I consider it not needed assignment. And actually, this could be calculated
in init_pdx() next to max_page to avoid requiring each arch (arm32, arm64, mpu)
to set it exactly the same.

> +    for ( unsigned int bank = 0 ; bank < mem->nr_banks; bank++ )
; should be added right after a field, so bank = 0; > +    {
> +        paddr_t bank_start = round_pgup(mem->bank[bank].start);
> +        paddr_t bank_size = round_pgdown(mem->bank[bank].size);
> +        paddr_t bank_end = bank_start + bank_size;
> +
> +        ram_size = ram_size + bank_size;
> +        ram_start = min(ram_start, bank_start);
> +        ram_end = max(ram_end, bank_end);
> +    }
> +
> +    setup_staticheap_mappings();
> +
> +    total_pages += ram_size >> PAGE_SHIFT;
> +    max_page = PFN_DOWN(ram_end);
This is already calculated in init_pdx() after my recent changes

> +
> +    setup_frametable_mappings(ram_start, ram_end);
> +
> +    init_staticmem_pages();
> +    init_sharedmem_pages();
>  }
>  
>  int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int nf)

~Michal



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Subject: Re: [PATCH v1] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
To: Mykyta Poturai 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 "xen-devel@lists.xenproject.org" 
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On 21.08.2025 12:50, Mykyta Poturai wrote:
> --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> @@ -51,7 +51,9 @@
>  #include 
>  #include 
>  #include 
> +#ifdef CONFIG_HAS_PCI
>  #include "../arch/arm/pci/pci-host-rcar4.h"
> +#endif
>  
>  #define dev_name(dev) dt_node_full_name(dev_to_dt(dev))

Hmm, while this may take care of the immediate issue, I wonder if it wouldn't
better be the header itself which is modified. Then perhaps also taking care
of the other (Misra) issue there: The header guard check not being first in
the file, but sitting after an #include.

I further assume there is a good reason why a private header is included here
from some other subtree.

Jan


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Subject: Re: [PATCH v1] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
To: Mykyta Poturai 
Cc: Stefano Stabellini , Julien Grall
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On 21.08.2025 12:50, Mykyta Poturai wrote:
> With PCI disabled the build fails due to undefined struct
> pci_host_bridge.
> 
> Add ifdef guard around pci-host-rcar4.h to not include it when PCI
> support is disabled.
> 
> Signed-off-by: Mykyta Poturai 

Oh, and - Reported-by: ... please.

Jan


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On 30/07/2025 10:45, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Add a scheme to distinguish transient MPU regions, to identify MPU
> regions which will be mapped for a short period of time.
The commit msg lacks description why this is needed.

> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
> ---
>  xen/arch/arm/include/asm/arm32/mpu.h     |  2 ++
>  xen/arch/arm/include/asm/arm64/mpu.h     |  2 ++
>  xen/arch/arm/include/asm/mpu/mm.h        | 14 +++++++++++++-
>  xen/arch/arm/include/asm/mpu/regions.inc | 19 +++++++++++++++++--
>  xen/arch/arm/mpu/mm.c                    | 23 ++++++++++++++---------
>  5 files changed, 48 insertions(+), 12 deletions(-)
> 
> diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/asm/arm32/mpu.h
> index 0a6930b3a0..9906d98809 100644
> --- a/xen/arch/arm/include/asm/arm32/mpu.h
> +++ b/xen/arch/arm/include/asm/arm32/mpu.h
> @@ -39,6 +39,8 @@ typedef union {
>  typedef struct {
>      prbar_t prbar;
>      prlar_t prlar;
> +    bool transient;
> +    uint8_t pad[7]; /* Pad structure to 16 Bytes */
>  } pr_t;
>  
>  #endif /* __ASSEMBLY__ */
> diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/asm/arm64/mpu.h
> index f0ce344e78..1d1843eda0 100644
> --- a/xen/arch/arm/include/asm/arm64/mpu.h
> +++ b/xen/arch/arm/include/asm/arm64/mpu.h
> @@ -38,6 +38,8 @@ typedef union {
>  typedef struct {
>      prbar_t prbar;
>      prlar_t prlar;
> +    bool transient;
> +    uint8_t pad[15]; /* Pad structure to 32 Bytes */
>  } pr_t;
>  
>  #endif /* __ASSEMBLY__ */
> diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
> index c32fac8905..56ca411af4 100644
> --- a/xen/arch/arm/include/asm/mpu/mm.h
> +++ b/xen/arch/arm/include/asm/mpu/mm.h
> @@ -60,6 +60,16 @@ static inline void context_sync_mpu(void)
>      isb();
>  }
>  
> +static inline bool region_is_transient(pr_t *pr)
As this is just a read helper, pr could be const?

~Michal




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Subject: Re: [PATCH v2 1/2] arm/mpu: Enable is_xen_heap_page and
 is_xen_heap_mfn for ARM_32
To: Ayan Kumar Halder ,
	
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , "Volodymyr
 Babchuk" 
References: <20250814081959.3504145-1-ayan.kumar.halder@amd.com>
 <20250814081959.3504145-2-ayan.kumar.halder@amd.com>
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On 14/08/2025 10:19, Ayan Kumar Halder wrote:
> In case of ARM_32, all of the RAM will be covered by a permanent contiguous
> mapping (where VA == PA) and there will be a single heap. Thus, the memory
> allocated from Xen heap uses PGC_xen_heap.
> This is similar to the scenario described for
> "CONFIG_SEPARATE_XENHEAP=n W/ DIRECT MAP OF ALL RAM" in common/page_alloc.c.
> 
> Signed-off-by: Ayan Kumar Halder 
Reviewed-by: Michal Orzel 

~Michal



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Subject: Re: [PATCH v2 2/2] arm/mpu: Disable map_domain_page for MPU
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On 14/08/2025 10:19, Ayan Kumar Halder wrote:
> There is no domheap for ARM_32. All of the RAM is mapped and VA == PA.
NIT for the future: It's always better to mention explicitly that you're talking
about MPU also in commit msg. Without looking at the commit title, one can be
confused.

> 
> Signed-off-by: Ayan Kumar Halder 
Reviewed-by: Michal Orzel 

~Michal



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With PCI disabled the build fails due to undefined struct
pci_host_bridge.

Add ifdef guard to pci-host-rcar4.h to not require the stuct being
defined when PCI support is disabled. All call sites are already covered
by HAS_PCI check, so no dummy implementations are needed.

Also move includes under the header guard to not break MISRA rules.

Reported-by: Jan Beulich 
Signed-off-by: Mykyta Poturai 
---
 xen/arch/arm/pci/pci-host-rcar4.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/pci/pci-host-rcar4.h b/xen/arch/arm/pci/pci-host-=
rcar4.h
index 8ac6626a22..31ef9d2d40 100644
--- a/xen/arch/arm/pci/pci-host-rcar4.h
+++ b/xen/arch/arm/pci/pci-host-rcar4.h
@@ -1,9 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-#include 
-
 #ifndef __PCI_HOST_RCAR4_H__
 #define __PCI_HOST_RCAR4_H__
=20
+#include 
+
+#ifdef CONFIG_HAS_PCI
 void rcar4_pcie_osid_bdf_set(struct pci_host_bridge *bridge,
                              unsigned int reg_id, uint32_t osid, uint32_t =
bdf);
 void rcar4_pcie_osid_bdf_clear(struct pci_host_bridge *bridge,
@@ -14,5 +15,6 @@ int rcar4_pcie_osid_reg_alloc(struct pci_host_bridge *bri=
dge);
 void rcar4_pcie_osid_reg_free(struct pci_host_bridge *bridge,
                               unsigned int reg_id);
 int rcar4_pcie_osid_regs_init(struct pci_host_bridge *bridge);
+#endif
=20
 #endif /* __PCI_HOST_RCAR4_H__ */
--=20
2.34.1


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Subject: Re: [PATCH] common/efi: deviate Rule 2.1 violation in read_file()
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From: Biju Das 
To: Thomas Zimmermann , "simona@ffwll.ch"
	, "airlied@gmail.com" ,
	"mripard@kernel.org" ,
	"maarten.lankhorst@linux.intel.com" ,
	geert , tomi.valkeinen
	
CC: "dri-devel@lists.freedesktop.org" ,
	"linux-mediatek@lists.infradead.org" ,
	"freedreno@lists.freedesktop.org" ,
	"linux-arm-msm@vger.kernel.org" ,
	"imx@lists.linux.dev" ,
	"linux-samsung-soc@vger.kernel.org" ,
	"nouveau@lists.freedesktop.org" ,
	"virtualization@lists.linux.dev" ,
	"spice-devel@lists.freedesktop.org" ,
	"linux-renesas-soc@vger.kernel.org" ,
	"linux-rockchip@lists.infradead.org" ,
	"linux-tegra@vger.kernel.org" ,
	"intel-xe@lists.freedesktop.org" ,
	"xen-devel@lists.xenproject.org" 
Subject: RE: [PATCH v6 18/25] drm/renesas/rz-du: Compute dumb-buffer sizes
 with drm_mode_size_dumb()
Thread-Topic: [PATCH v6 18/25] drm/renesas/rz-du: Compute dumb-buffer sizes
 with drm_mode_size_dumb()
Thread-Index: AQHcEnS9RPzKheS8DUq4xJ6ExVmpC7Rs+CdA
Date: Thu, 21 Aug 2025 11:28:24 +0000
Message-ID:
 
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 <20250821081918.79786-19-tzimmermann@suse.de>
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Hi Thomas Zimmermann,

Thanks for the patch.

> -----Original Message-----
> From: Thomas Zimmermann 
> Sent: 21 August 2025 09:17
> Subject: [PATCH v6 18/25] drm/renesas/rz-du: Compute dumb-buffer sizes wi=
th drm_mode_size_dumb()
>=20
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and buffe=
r size. Align the pitch
> according to hardware requirements.
>=20
> v5:
> - include dumb-buffers header for drm_mode_size_dumb() (kernel test robot=
)
>=20
> Signed-off-by: Thomas Zimmermann 
> Cc: Biju Das 

Tested-by: Biju Das 

Cheers,
Biju


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Message-ID: <7918ea7e-8914-4c0f-97be-d660043a4aab@suse.de>
Date: Thu, 21 Aug 2025 13:55:59 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v6 18/25] drm/renesas/rz-du: Compute dumb-buffer sizes
 with drm_mode_size_dumb()
To: Biju Das , "simona@ffwll.ch"
 , "airlied@gmail.com" ,
 "mripard@kernel.org" ,
 "maarten.lankhorst@linux.intel.com" ,
 geert ,
 "tomi.valkeinen" 
Cc: "dri-devel@lists.freedesktop.org" ,
 "linux-mediatek@lists.infradead.org" ,
 "freedreno@lists.freedesktop.org" ,
 "linux-arm-msm@vger.kernel.org" ,
 "imx@lists.linux.dev" ,
 "linux-samsung-soc@vger.kernel.org" ,
 "nouveau@lists.freedesktop.org" ,
 "virtualization@lists.linux.dev" ,
 "spice-devel@lists.freedesktop.org" ,
 "linux-renesas-soc@vger.kernel.org" ,
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 "intel-xe@lists.freedesktop.org" ,
 "xen-devel@lists.xenproject.org" 
References: <20250821081918.79786-1-tzimmermann@suse.de>
 <20250821081918.79786-19-tzimmermann@suse.de>
 
Content-Language: en-US
From: Thomas Zimmermann 
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Hi

Am 21.08.25 um 13:28 schrieb Biju Das:
> Hi Thomas Zimmermann,
>
> Thanks for the patch.
>
>> -----Original Message-----
>> From: Thomas Zimmermann 
>> Sent: 21 August 2025 09:17
>> Subject: [PATCH v6 18/25] drm/renesas/rz-du: Compute dumb-buffer sizes with drm_mode_size_dumb()
>>
>> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and buffer size. Align the pitch
>> according to hardware requirements.
>>
>> v5:
>> - include dumb-buffers header for drm_mode_size_dumb() (kernel test robot)
>>
>> Signed-off-by: Thomas Zimmermann 
>> Cc: Biju Das 
> Tested-by: Biju Das 

Thanks for testing. Could you also review the patch, please?

Best regards
Thomas

>
> Cheers,
> Biju

-- 
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)




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In-Reply-To: 
From: Mykola Kvach 
Date: Thu, 21 Aug 2025 15:03:21 +0300
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Subject: Re: [PATCH v1] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
To: Mykyta Poturai 
Cc: "xen-devel@lists.xenproject.org" , 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Volodymyr Babchuk 
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

Hi Mykyta,

On Thu, Aug 21, 2025 at 1:51=E2=80=AFPM Mykyta Poturai  wrote:
>
> With PCI disabled the build fails due to undefined struct
> pci_host_bridge.
>
> Add ifdef guard around pci-host-rcar4.h to not include it when PCI
> support is disabled.
>
> Signed-off-by: Mykyta Poturai 
> ---
> This patch can be squashed with iommu/ipmmu-vmsa: Implement basic PCIE-IP=
MMU OSID support
> ---
>  xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passt=
hrough/arm/ipmmu-vmsa.c
> index ea9fa9ddf3..49f149e222 100644
> --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> @@ -51,7 +51,9 @@
>  #include 
>  #include 
>  #include 
> +#ifdef CONFIG_HAS_PCI
>  #include "../arch/arm/pci/pci-host-rcar4.h"
> +#endif

As far as I know, the IPMMU VMSA driver can also be used on other
R-Car platforms. Is there a chance we could have HAS_PCI enabled
together with IPMMU VMSA, but not be on an R-Car Gen4 platform,
for example, on R-Car3 or possibly some future R-Car variants?

Wouldn't it be better to use:
#ifdef CONFIG_RCAR4
?

>
>  #define dev_name(dev) dt_node_full_name(dev_to_dt(dev))
>
> --
> 2.34.1
>

Best regards,
Mykola


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Date: Thu, 21 Aug 2025 14:04:14 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Dmytro Prokopchuk1 
Cc: Jan Beulich ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel , Julien Grall ,
	Roger Pau =?utf-8?B?TW9ubsOp?= ,
	Stefano Stabellini ,
	"Daniel P. Smith" ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH] common/efi: deviate Rule 2.1 violation in read_file()
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 <98e8ca88-75cd-4d59-9e94-f758324fa46a@suse.com>
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--M4dvO/larT36ENG1
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Date: Thu, 21 Aug 2025 14:04:14 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Dmytro Prokopchuk1 
Cc: Jan Beulich ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel , Julien Grall ,
	Roger Pau =?utf-8?B?TW9ubsOp?= ,
	Stefano Stabellini ,
	"Daniel P. Smith" ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH] common/efi: deviate Rule 2.1 violation in read_file()

On Thu, Aug 21, 2025 at 11:28:01AM +0000, Dmytro Prokopchuk1 wrote:
>=20
>=20
> On 8/21/25 13:33, Jan Beulich wrote:
> > On 20.08.2025 20:05, Dmytro Prokopchuk1 wrote:
> >> --- a/xen/common/efi/boot.c
> >> +++ b/xen/common/efi/boot.c
> >> @@ -852,7 +852,7 @@ static bool __init read_file(EFI_FILE_HANDLE dir_h=
andle, CHAR16 *name,
> >>       PrintErr(L" failed for ");
> >>       PrintErrMesg(name, ret);
> >>  =20
> >> -    /* not reached */
> >> +    /* SAF-15-safe deliberately unreachable code */
> >>       return false;
> >>   }
> >=20
> > Much better (even if not tagged as v2). Yet then, did you consider
> > alternatives? For example, with PrintErrMesg() properly annotated "nore=
turn",
> > I'd kind of expect compilers to not object to the omission of the "retu=
rn"
> > statement here. This would then let us get away without a new SAF comme=
nt.
> > While you explain in the SAF text why you retain the statement, I'm not
> > convinced of code clarity suffering if it was deleted, as long as a sui=
table
> > comment is still there. If PrintErrMesg() lost its "noreturn", surely
> > compilers would then diagnose the lack of "return".
> >=20
> > Jan
>=20
> Sure, the next version will be v3.
> Actually, the PrintErrMesg() already has property 'noreturn'.
> And it really gives an alternative way: remove 'return false;' from the=
=20
> function read_file() (leaving comment there).
>=20
> With that change Misra is "happy".
>=20
> In case of removing 'noreturn' attribute from PrintErrMesg() function=20
> compiler will detect that:
> arch/arm/efi/boot.c: In function =E2=80=98read_file=E2=80=99:
> arch/arm/efi/boot.c:854:1: error: control reaches end of non-void=20
> function [-Werror=3Dreturn-type]
>   }
>   ^
>=20
> Is it OK to prepare such ^ patch?

IMO sounds like the best solution for this issue.

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Subject: [PATCH] CI: Use 'watchdog' for x86 hardware
Date: Thu, 21 Aug 2025 13:06:52 +0100
Message-Id: <20250821120652.3910926-1-andrew.cooper3@citrix.com>
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This detects various hangs and turns them into a crash with backtrace.

Signed-off-by: Andrew Cooper 
---
CC: Anthony PERARD 
CC: Jan Beulich 
CC: Marek Marczykowski-Górecki 
CC: Michal Orzel 
CC: Roger Pau Monné 
CC: Stefano Stabellini 
---
 automation/scripts/qubes-x86-64.sh             | 4 ++--
 automation/scripts/xilinx-smoke-dom0-x86_64.sh | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/automation/scripts/qubes-x86-64.sh b/automation/scripts/qubes-x86-64.sh
index 2750d24eba17..b49a44c5b1ab 100755
--- a/automation/scripts/qubes-x86-64.sh
+++ b/automation/scripts/qubes-x86-64.sh
@@ -260,14 +260,14 @@ TFTP=/scratch/gitlab-runner/tftp
 CONTROLLER=control@thor.testnet
 
 echo "
-multiboot2 (http)/gitlab-ci/xen $CONSOLE_OPTS loglvl=all guest_loglvl=all dom0_mem=4G console_timestamps=boot $extra_xen_opts
+multiboot2 (http)/gitlab-ci/xen $CONSOLE_OPTS loglvl=all guest_loglvl=all dom0_mem=4G console_timestamps=boot watchdog $extra_xen_opts
 module2 (http)/gitlab-ci/vmlinuz console=hvc0 root=/dev/ram0 earlyprintk=xen
 module2 --nounzip (http)/gitlab-ci/initrd-dom0
 " > $TFTP/grub.cfg
 
 echo "#!ipxe
 
-kernel /gitlab-ci/xen $CONSOLE_OPTS loglvl=all guest_loglvl=all dom0_mem=4G console_timestamps=boot $extra_xen_opts || reboot
+kernel /gitlab-ci/xen $CONSOLE_OPTS loglvl=all guest_loglvl=all dom0_mem=4G console_timestamps=boot watchdog $extra_xen_opts || reboot
 module /gitlab-ci/vmlinuz console=hvc0 root=/dev/ram0 earlyprintk=xen || reboot
 module /gitlab-ci/initrd-dom0 || reboot
 boot
diff --git a/automation/scripts/xilinx-smoke-dom0-x86_64.sh b/automation/scripts/xilinx-smoke-dom0-x86_64.sh
index 6970a8658d5f..0ad8f658e396 100755
--- a/automation/scripts/xilinx-smoke-dom0-x86_64.sh
+++ b/automation/scripts/xilinx-smoke-dom0-x86_64.sh
@@ -15,7 +15,7 @@ WORKDIR="${PWD}"
 TEST="$1"
 PASS_MSG="Test passed: ${TEST}"
 XEN_CMD_DOM0="dom0=pvh dom0_max_vcpus=4 dom0_mem=4G"
-XEN_CMD_XEN="sched=null loglvl=all guest_loglvl=all console_timestamps=boot"
+XEN_CMD_XEN="sched=null loglvl=all guest_loglvl=all console_timestamps=boot watchdog"
 XEN_CMD_EXTRA=""
 DOM0_CMD=""
 DOMU_CMD=""

base-commit: 97f9db488a48d5f7c41681ac3bde7047dcfca899
-- 
2.39.5



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Date: Thu, 21 Aug 2025 14:21:41 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Andrew Cooper 
Cc: Xen-devel ,
	Anthony PERARD ,
	Jan Beulich ,
	Michal Orzel ,
	Roger Pau =?utf-8?B?TW9ubsOp?= ,
	Stefano Stabellini 
Subject: Re: [PATCH] CI: Use 'watchdog' for x86 hardware
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Date: Thu, 21 Aug 2025 14:21:41 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Andrew Cooper 
Cc: Xen-devel ,
	Anthony PERARD ,
	Jan Beulich ,
	Michal Orzel ,
	Roger Pau =?utf-8?B?TW9ubsOp?= ,
	Stefano Stabellini 
Subject: Re: [PATCH] CI: Use 'watchdog' for x86 hardware

On Thu, Aug 21, 2025 at 01:06:52PM +0100, Andrew Cooper wrote:
> This detects various hangs and turns them into a crash with backtrace.
>=20
> Signed-off-by: Andrew Cooper 

Should it also apply to in-QEMU tests?

Anyway:

Reviewed-by: Marek Marczykowski-G=C3=B3recki 

> ---
> CC: Anthony PERARD 
> CC: Jan Beulich 
> CC: Marek Marczykowski-G=C3=B3recki 
> CC: Michal Orzel 
> CC: Roger Pau Monn=C3=A9 
> CC: Stefano Stabellini 
> ---
>  automation/scripts/qubes-x86-64.sh             | 4 ++--
>  automation/scripts/xilinx-smoke-dom0-x86_64.sh | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
>=20
> diff --git a/automation/scripts/qubes-x86-64.sh b/automation/scripts/qube=
s-x86-64.sh
> index 2750d24eba17..b49a44c5b1ab 100755
> --- a/automation/scripts/qubes-x86-64.sh
> +++ b/automation/scripts/qubes-x86-64.sh
> @@ -260,14 +260,14 @@ TFTP=3D/scratch/gitlab-runner/tftp
>  CONTROLLER=3Dcontrol@thor.testnet
> =20
>  echo "
> -multiboot2 (http)/gitlab-ci/xen $CONSOLE_OPTS loglvl=3Dall guest_loglvl=
=3Dall dom0_mem=3D4G console_timestamps=3Dboot $extra_xen_opts
> +multiboot2 (http)/gitlab-ci/xen $CONSOLE_OPTS loglvl=3Dall guest_loglvl=
=3Dall dom0_mem=3D4G console_timestamps=3Dboot watchdog $extra_xen_opts
>  module2 (http)/gitlab-ci/vmlinuz console=3Dhvc0 root=3D/dev/ram0 earlypr=
intk=3Dxen
>  module2 --nounzip (http)/gitlab-ci/initrd-dom0
>  " > $TFTP/grub.cfg
> =20
>  echo "#!ipxe
> =20
> -kernel /gitlab-ci/xen $CONSOLE_OPTS loglvl=3Dall guest_loglvl=3Dall dom0=
_mem=3D4G console_timestamps=3Dboot $extra_xen_opts || reboot
> +kernel /gitlab-ci/xen $CONSOLE_OPTS loglvl=3Dall guest_loglvl=3Dall dom0=
_mem=3D4G console_timestamps=3Dboot watchdog $extra_xen_opts || reboot
>  module /gitlab-ci/vmlinuz console=3Dhvc0 root=3D/dev/ram0 earlyprintk=3D=
xen || reboot
>  module /gitlab-ci/initrd-dom0 || reboot
>  boot
> diff --git a/automation/scripts/xilinx-smoke-dom0-x86_64.sh b/automation/=
scripts/xilinx-smoke-dom0-x86_64.sh
> index 6970a8658d5f..0ad8f658e396 100755
> --- a/automation/scripts/xilinx-smoke-dom0-x86_64.sh
> +++ b/automation/scripts/xilinx-smoke-dom0-x86_64.sh
> @@ -15,7 +15,7 @@ WORKDIR=3D"${PWD}"
>  TEST=3D"$1"
>  PASS_MSG=3D"Test passed: ${TEST}"
>  XEN_CMD_DOM0=3D"dom0=3Dpvh dom0_max_vcpus=3D4 dom0_mem=3D4G"
> -XEN_CMD_XEN=3D"sched=3Dnull loglvl=3Dall guest_loglvl=3Dall console_time=
stamps=3Dboot"
> +XEN_CMD_XEN=3D"sched=3Dnull loglvl=3Dall guest_loglvl=3Dall console_time=
stamps=3Dboot watchdog"
>  XEN_CMD_EXTRA=3D""
>  DOM0_CMD=3D""
>  DOMU_CMD=3D""
>=20
> base-commit: 97f9db488a48d5f7c41681ac3bde7047dcfca899
> --=20
> 2.39.5
>=20

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Subject: Re: [PATCH] CI: Use 'watchdog' for x86 hardware
To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 
Cc: Xen-devel ,
 Anthony PERARD , Jan Beulich ,
 Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini 
References: <20250821120652.3910926-1-andrew.cooper3@citrix.com>
 
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From: Andrew Cooper 
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On 21/08/2025 1:21 pm, Marek Marczykowski-Górecki wrote:
> On Thu, Aug 21, 2025 at 01:06:52PM +0100, Andrew Cooper wrote:
>> This detects various hangs and turns them into a crash with backtrace.
>>
>> Signed-off-by: Andrew Cooper 
> Should it also apply to in-QEMU tests?

I doubt QEMU can emulate performance counters.  I certainly wouldn't
trust an emulation which claims to be able to.

>
> Anyway:
>
> Reviewed-by: Marek Marczykowski-Górecki 

Thanks.

~Andrew


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Subject: Re: [PATCH v2] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
To: Mykyta Poturai 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 "xen-devel@lists.xenproject.org" 
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On 21.08.2025 13:23, Mykyta Poturai wrote:
> With PCI disabled the build fails due to undefined struct
> pci_host_bridge.
> 
> Add ifdef guard to pci-host-rcar4.h to not require the stuct being
> defined when PCI support is disabled. All call sites are already covered
> by HAS_PCI check, so no dummy implementations are needed.
> 
> Also move includes under the header guard to not break MISRA rules.
> 
> Reported-by: Jan Beulich 
> Signed-off-by: Mykyta Poturai 

Along with the Reported-by I thought a Fixes: tag would go without saying.
Can likely be added while committing.

Jan


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From: Biju Das 
To: Thomas Zimmermann , "simona@ffwll.ch"
	, "airlied@gmail.com" ,
	"mripard@kernel.org" ,
	"maarten.lankhorst@linux.intel.com" ,
	geert , tomi.valkeinen
	
CC: "dri-devel@lists.freedesktop.org" ,
	"linux-mediatek@lists.infradead.org" ,
	"freedreno@lists.freedesktop.org" ,
	"linux-arm-msm@vger.kernel.org" ,
	"imx@lists.linux.dev" ,
	"linux-samsung-soc@vger.kernel.org" ,
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	"linux-tegra@vger.kernel.org" ,
	"intel-xe@lists.freedesktop.org" ,
	"xen-devel@lists.xenproject.org" 
Subject: RE: [PATCH v6 18/25] drm/renesas/rz-du: Compute dumb-buffer sizes
 with drm_mode_size_dumb()
Thread-Topic: [PATCH v6 18/25] drm/renesas/rz-du: Compute dumb-buffer sizes
 with drm_mode_size_dumb()
Thread-Index: AQHcEnS9RPzKheS8DUq4xJ6ExVmpC7Rs+CdAgAAIDYCAAAp/AA==
Date: Thu, 21 Aug 2025 12:34:14 +0000
Message-ID:
 
References: <20250821081918.79786-1-tzimmermann@suse.de>
 <20250821081918.79786-19-tzimmermann@suse.de>
 
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From: Mykyta Poturai 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel ,
	Volodymyr Babchuk 
Subject: Re: [PATCH v1] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
Thread-Topic: [PATCH v1] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
Thread-Index: AQHcEol6WY2CZ9Gyh0KXEcdKpt6HNrRtAhqAgAASeQA=
Date: Thu, 21 Aug 2025 13:09:29 +0000
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Message-ID: <6f05a6849fb7b22db35216dcf12bf537f8a43a92.camel@infradead.org>
Subject: Re: [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural
 constant_tsc model checks
From: David Woodhouse 
To: Sohil Mehta , x86@kernel.org, Dave Hansen
	 , Tony Luck , 
 =?ISO-8859-1?Q?J=FCrgen?= Gross
	 , Boris Ostrovsky , xen-devel
	 
Cc: Peter Zijlstra , Ingo Molnar , 
 Arnaldo Carvalho de Melo , Namhyung Kim
 , Mark Rutland , Alexander
 Shishkin ,  Jiri Olsa
 , Ian Rogers , Adrian Hunter
 ,  Kan Liang , Thomas
 Gleixner , Borislav Petkov , "H . Peter
 Anvin" , "Rafael J . Wysocki" , Len Brown
 , Andy Lutomirski , Viresh Kumar
 , Jean Delvare , Guenter Roeck
 , Zhang Rui , Andrew Cooper
 , David Laight ,
 Dapeng Mi ,  linux-perf-users@vger.kernel.org,
 linux-kernel@vger.kernel.org,  linux-acpi@vger.kernel.org,
 linux-pm@vger.kernel.org
Date: Thu, 21 Aug 2025 14:15:05 +0100
In-Reply-To: <20250219184133.816753-14-sohil.mehta@intel.com>
References: <20250219184133.816753-1-sohil.mehta@intel.com>
	 <20250219184133.816753-14-sohil.mehta@intel.com>
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On Wed, 2025-02-19 at 18:41 +0000, Sohil Mehta wrote:
> X86_FEATURE_CONSTANT_TSC is a Linux-defined, synthesized feature flag.
> It is used across several vendors. Intel CPUs will set the feature when
> the architectural CPUID.80000007.EDX[1] bit is set. There are also some
> Intel CPUs that have the X86_FEATURE_CONSTANT_TSC behavior but don't
> enumerate it with the architectural bit.=C2=A0 Those currently have a mod=
el
> range check.
>=20
> Today, virtually all of the CPUs that have the CPUID bit *also* match
> the "model >=3D 0x0e" check. This is confusing. Instead of an open-ended
> check, pick some models (INTEL_IVYBRIDGE and P4_WILLAMETTE) as the end
> of goofy CPUs that should enumerate the bit but don't.=C2=A0 These models=
 are
> relatively arbitrary but conservative pick for this.
>=20
> This makes it obvious that later CPUs (like Family 18+) no longer need
> to synthesize X86_FEATURE_CONSTANT_TSC.
>=20
> Signed-off-by: Sohil Mehta 
> ---
> v3: Make the non-architectural model checks more explicit.
> =C2=A0=C2=A0=C2=A0 Improve commit message.
>=20
> v2: No change.
> ---
> =C2=A0arch/x86/kernel/cpu/intel.c | 10 ++++++----
> =C2=A01 file changed, 6 insertions(+), 4 deletions(-)
>=20
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index fc68561d9f92..4fbc5465ca67 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -210,10 +210,6 @@ static void early_init_intel(struct cpuinfo_x86 *c)
> =C2=A0{
> =C2=A0	u64 misc_enable;
> =C2=A0
> -	if ((c->x86 =3D=3D 0xf && c->x86_model >=3D 0x03) ||
> -		(c->x86 =3D=3D 0x6 && c->x86_model >=3D 0x0e))
> -		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
> -
> =C2=A0	if (c->x86 >=3D 6 && !cpu_has(c, X86_FEATURE_IA64))
> =C2=A0		c->microcode =3D intel_get_microcode_revision();
> =C2=A0
> @@ -266,10 +262,16 @@ static void early_init_intel(struct cpuinfo_x86 *c)
> =C2=A0	 *
> =C2=A0	 * It is also reliable across cores and sockets. (but not across
> =C2=A0	 * cabinets - we turn it off in that case explicitly.)
> +	 *
> +	 * Use a model-specific check for some older CPUs that have invariant
> +	 * TSC but may not report it architecturally via 8000_0007.
> =C2=A0	 */
> =C2=A0	if (c->x86_power & (1 << 8)) {
> =C2=A0		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
> =C2=A0		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
> +	} else if ((c->x86_vfm >=3D INTEL_P4_PRESCOTT && c->x86_vfm <=3D INTEL_=
P4_WILLAMETTE) ||
> +		=C2=A0=C2=A0 (c->x86_vfm >=3D INTEL_CORE_YONAH=C2=A0 && c->x86_vfm <=
=3D INTEL_IVYBRIDGE)) {
> +		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
> =C2=A0	}
> =C2=A0
> =C2=A0	/* Penwell and Cloverview have the TSC which doesn't sleep on S3 *=
/

Hm. My test host is INTEL_HASWELL_X (0x63f). For reasons which are
unclear to me, QEMU doesn't set bit 8 of 0x80000007 EDX unless I
explicitly append ',+invtsc' to the existing '-cpu host' on its command
line. So now my guest doesn't think it has X86_FEATURE_CONSTANT_TSC.

For reasons I also don't understand, for a Xen (in qemu/kvm) guest this
results in about a four-second delay when bringing up each vCPU.
Timestamps added to QEMU's stdout because the kernel's own timestamps
are lying...

1755781767: [    0.489434] smp: Bringing up secondary CPUs ...
1755781767: [    0.489434] installing Xen timer for CPU 1
1755781767: [    0.489434] smpboot: x86: Booting SMP configuration:
1755781767: [    0.489434] .... node  #0, CPUs:          #1
1755781767: [    0.489434] installing Xen timer for CPU 2
1755781767: [    0.489434]    #2
1755781767: [    0.489434] installing Xen timer for CPU 3
1755781767: [    0.489434]    #3
1755781771: [    0.489434] cpu 1 spinlock event irq 45
1755781775: [    0.544262] cpu 2 spinlock event irq 46
1755781779: [    0.604306] cpu 3 spinlock event irq 47
1755781779: [    0.604792] smp: Brought up 1 node, 4 CPUs
1755781779: [    0.604792] smpboot: Total of 4 processors activated (103411=
8.38 BogoMIPS)




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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , "Daniel P. Smith"
	, =?iso-8859-1?Q?Marek_Marczykowski-G=F3recki?=
	, Jan Beulich 
Subject: [PATCH v3] common/efi: fix Rule 2.1 violation in read_file()
Thread-Topic: [PATCH v3] common/efi: fix Rule 2.1 violation in read_file()
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Date: Thu, 21 Aug 2025 13:56:28 +0000
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MISRA C Rule 2.1 states: "A project shall not contain unreachable code."

The return statements in the 'read_file()' function is unreachable due
to function 'PrintErrMesg()' which has 'noreturn' attribute:
        PrintErrMesg(name, ret);
        /* not reached */
        return false;
    }

No explicit return statement is needed here. Remove the statement and
write a justification comment instead. No functional changes.

Signed-off-by: Dmytro Prokopchuk 
---
Link to v2:
https://patchew.org/Xen/c20a58f24875806adfaf491f9c6eef2ca8682d18.1755711594=
.git.dmytro._5Fprokopchuk1@epam.com/

Changes in v3:
- removed unreachable code instead of deviation
- updated commit subject and message

Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1996439444
---
 xen/common/efi/boot.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
index 50ff1d1bd2..325de05b18 100644
--- a/xen/common/efi/boot.c
+++ b/xen/common/efi/boot.c
@@ -851,9 +851,13 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handl=
e, CHAR16 *name,
     PrintErr(what);
     PrintErr(L" failed for ");
     PrintErrMesg(name, ret);
-
-    /* not reached */
-    return false;
+    /*
+     * No explicit return statement is needed here because 'PrintErrMesg()=
' is
+     * marked as 'noreturn', which guarantees that it never returns contro=
l to
+     * the caller. If the 'noreturn' attribute of 'PrintErrMesg()' is remo=
ved
+     * in the future, compiler will emit an error about the missing return
+     * statement (build-time safeguard).
+     */
 }
=20
 static bool __init read_section(const EFI_LOADED_IMAGE *image,
--=20
2.43.0


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From: Dmytro Prokopchuk1 
To: Jan Beulich 
CC: Nicola Vetrini , Doug Goldstein
	, Stefano Stabellini , Andrew
 Cooper , Anthony PERARD
	, Michal Orzel , Julien
 Grall , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, "xen-devel@lists.xenproject.org"
	
Subject: Re: [PATCH] misra: add deviation for MISRA C Rule 11.3
Thread-Topic: [PATCH] misra: add deviation for MISRA C Rule 11.3
Thread-Index: AQHcEaKMMDydbZiTjE+UNGKddouDNbRs1fAAgABSSoA=
Date: Thu, 21 Aug 2025 14:13:22 +0000
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Date: Thu, 21 Aug 2025 16:24:57 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Dmytro Prokopchuk1 
Cc: "xen-devel@lists.xenproject.org" ,
	"Daniel P. Smith" ,
	Jan Beulich 
Subject: Re: [PATCH v3] common/efi: fix Rule 2.1 violation in read_file()
Message-ID: 
References: <4a1a4a3406d227348afa1ad2ce90dc5264fdb44a.1755783750.git.dmytro_prokopchuk1@epam.com>
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Date: Thu, 21 Aug 2025 16:24:57 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Dmytro Prokopchuk1 
Cc: "xen-devel@lists.xenproject.org" ,
	"Daniel P. Smith" ,
	Jan Beulich 
Subject: Re: [PATCH v3] common/efi: fix Rule 2.1 violation in read_file()

On Thu, Aug 21, 2025 at 01:56:28PM +0000, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 2.1 states: "A project shall not contain unreachable code."
>=20
> The return statements in the 'read_file()' function is unreachable due
> to function 'PrintErrMesg()' which has 'noreturn' attribute:
>         PrintErrMesg(name, ret);
>         /* not reached */
>         return false;
>     }
>=20
> No explicit return statement is needed here. Remove the statement and
> write a justification comment instead. No functional changes.
>=20
> Signed-off-by: Dmytro Prokopchuk 
> ---
> Link to v2:
> https://patchew.org/Xen/c20a58f24875806adfaf491f9c6eef2ca8682d18.17557115=
94.git.dmytro._5Fprokopchuk1@epam.com/
>=20
> Changes in v3:
> - removed unreachable code instead of deviation
> - updated commit subject and message
>=20
> Test CI pipeline:
> https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/19964394=
44
> ---
>  xen/common/efi/boot.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>=20
> diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
> index 50ff1d1bd2..325de05b18 100644
> --- a/xen/common/efi/boot.c
> +++ b/xen/common/efi/boot.c
> @@ -851,9 +851,13 @@ static bool __init read_file(EFI_FILE_HANDLE dir_han=
dle, CHAR16 *name,
>      PrintErr(what);
>      PrintErr(L" failed for ");
>      PrintErrMesg(name, ret);
> -
> -    /* not reached */
> -    return false;
> +    /*
> +     * No explicit return statement is needed here because 'PrintErrMesg=
()' is
> +     * marked as 'noreturn', which guarantees that it never returns cont=
rol to
> +     * the caller. If the 'noreturn' attribute of 'PrintErrMesg()' is re=
moved
> +     * in the future, compiler will emit an error about the missing retu=
rn
> +     * statement (build-time safeguard).
> +     */

I don't think this verbose code comment is needed here. Other similar places
use simply "Doesn't return." next to the function call, or nothing at
all if the function name already suggests it (which IMO is not the case
here). The longer explanation may be put in the commit message.

With that addressed:

Reviewed-by: Marek Marczykowski-G=C3=B3recki 

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Subject: Re: [PATCH v3] common/efi: fix Rule 2.1 violation in read_file()
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Cc: "xen-devel@lists.xenproject.org" ,
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In-Reply-To: 
Content-Type: text/plain; charset=UTF-8
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On 21.08.2025 16:24, Marek Marczykowski-Górecki wrote:
> On Thu, Aug 21, 2025 at 01:56:28PM +0000, Dmytro Prokopchuk1 wrote:
>> MISRA C Rule 2.1 states: "A project shall not contain unreachable code."
>>
>> The return statements in the 'read_file()' function is unreachable due
>> to function 'PrintErrMesg()' which has 'noreturn' attribute:
>>         PrintErrMesg(name, ret);
>>         /* not reached */
>>         return false;
>>     }
>>
>> No explicit return statement is needed here. Remove the statement and
>> write a justification comment instead. No functional changes.
>>
>> Signed-off-by: Dmytro Prokopchuk 
>> ---
>> Link to v2:
>> https://patchew.org/Xen/c20a58f24875806adfaf491f9c6eef2ca8682d18.1755711594.git.dmytro._5Fprokopchuk1@epam.com/
>>
>> Changes in v3:
>> - removed unreachable code instead of deviation
>> - updated commit subject and message
>>
>> Test CI pipeline:
>> https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/1996439444
>> ---
>>  xen/common/efi/boot.c | 10 +++++++---
>>  1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
>> index 50ff1d1bd2..325de05b18 100644
>> --- a/xen/common/efi/boot.c
>> +++ b/xen/common/efi/boot.c
>> @@ -851,9 +851,13 @@ static bool __init read_file(EFI_FILE_HANDLE dir_handle, CHAR16 *name,
>>      PrintErr(what);
>>      PrintErr(L" failed for ");
>>      PrintErrMesg(name, ret);
>> -
>> -    /* not reached */
>> -    return false;
>> +    /*
>> +     * No explicit return statement is needed here because 'PrintErrMesg()' is
>> +     * marked as 'noreturn', which guarantees that it never returns control to
>> +     * the caller. If the 'noreturn' attribute of 'PrintErrMesg()' is removed
>> +     * in the future, compiler will emit an error about the missing return
>> +     * statement (build-time safeguard).
>> +     */
> 
> I don't think this verbose code comment is needed here. Other similar places
> use simply "Doesn't return." next to the function call, or nothing at
> all if the function name already suggests it (which IMO is not the case
> here).

Or simply keep the comment that was already there?

Jan

> The longer explanation may be put in the commit message.
> 
> With that addressed:
> 
> Reviewed-by: Marek Marczykowski-Górecki 
> 



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From: Dmytro Prokopchuk1 
To: Jan Beulich 
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	, Stefano Stabellini , Andrew
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	, Michal Orzel , Julien
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Subject: Re: [PATCH] misra: add deviation for MISRA C Rule 11.3
Thread-Topic: [PATCH] misra: add deviation for MISRA C Rule 11.3
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Date: Thu, 21 Aug 2025 14:28:21 +0000
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From: Mykola Kvach 
Date: Thu, 21 Aug 2025 17:30:28 +0300
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Message-ID: 
Subject: Re: [PATCH v1] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
To: Mykyta Poturai 
Cc: "xen-devel@lists.xenproject.org" , 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Volodymyr Babchuk 
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On Thu, Aug 21, 2025 at 4:09=E2=80=AFPM Mykyta Poturai  wrote:
>
> On 21.08.25 15:03, Mykola Kvach wrote:
> > Hi Mykyta,
> >
> > On Thu, Aug 21, 2025 at 1:51=E2=80=AFPM Mykyta Poturai  wrote:
> >>
> >> With PCI disabled the build fails due to undefined struct
> >> pci_host_bridge.
> >>
> >> Add ifdef guard around pci-host-rcar4.h to not include it when PCI
> >> support is disabled.
> >>
> >> Signed-off-by: Mykyta Poturai 
> >> ---
> >> This patch can be squashed with iommu/ipmmu-vmsa: Implement basic PCIE=
-IPMMU OSID support
> >> ---
> >>   xen/drivers/passthrough/arm/ipmmu-vmsa.c | 2 ++
> >>   1 file changed, 2 insertions(+)
> >>
> >> diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/pa=
ssthrough/arm/ipmmu-vmsa.c
> >> index ea9fa9ddf3..49f149e222 100644
> >> --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> >> +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> >> @@ -51,7 +51,9 @@
> >>   #include 
> >>   #include 
> >>   #include 
> >> +#ifdef CONFIG_HAS_PCI
> >>   #include "../arch/arm/pci/pci-host-rcar4.h"
> >> +#endif
> >
> > As far as I know, the IPMMU VMSA driver can also be used on other
> > R-Car platforms. Is there a chance we could have HAS_PCI enabled
> > together with IPMMU VMSA, but not be on an R-Car Gen4 platform,
> > for example, on R-Car3 or possibly some future R-Car variants?
> >
> > Wouldn't it be better to use:
> > #ifdef CONFIG_RCAR4
> > ?
>
> Gen5 boards will use SMMU, so this will not be applicable to them. In
> any case, checking for RCAR4 will not help here, as PCI can be disabled
> regardless of the platform revision.

I see your point that CONFIG_RCAR4 alone isn=E2=80=99t enough, since PCI ca=
n be disabled
even on Gen4. My concern is that we=E2=80=99re adding Gen4-specific code in=
to a generic
IPMMU VMSA driver, which is used on multiple R-Car generations.

>
> >
> > Best regards,
> > Mykola
>
> --
> Mykyta


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Subject: Re: [PATCH] misra: add deviation for MISRA C Rule 11.3
To: Dmytro Prokopchuk1 
Cc: Nicola Vetrini ,
 Doug Goldstein ,
 Stefano Stabellini ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "xen-devel@lists.xenproject.org" 
References: 
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On 21.08.2025 16:13, Dmytro Prokopchuk1 wrote:
> On 8/21/25 12:18, Jan Beulich wrote:
>> On 20.08.2025 09:17, Dmytro Prokopchuk1 wrote:
>>> --- a/automation/eclair_analysis/ECLAIR/monitored.ecl
>>> +++ b/automation/eclair_analysis/ECLAIR/monitored.ecl
>>> @@ -45,6 +45,7 @@
>>>   -enable=MC3A2.R10.2
>>>   -enable=MC3A2.R11.1
>>>   -enable=MC3A2.R11.2
>>> +-enable=MC3A2.R11.3
>>
>> While the description mentions this change, it doesn't say why (e.g. "no
>> violations left" or "only this and that violation left" or some such).
> ARM:  813V ->   16V
> X86: 1422V -> 1035V
> 
> Looks OK for ARM (to be added in the monitoring list), but X86...
> Anyway the number of reported errors has no side effect.

Does it not, i.e. not even on the time it takes Eclair to do a full run?

> Jan, decision up to you (include into monitored.ecl or not).

For x86 I think the count is still too high. And no, it's not solely my
decision.

Jan


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Date: Thu, 21 Aug 2025 16:47:35 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: Jan Beulich , Doug Goldstein ,
 Stefano Stabellini , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 xen-devel@lists.xenproject.org
Subject: Re: [PATCH] misra: add deviation for MISRA C Rule 11.3
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References: 
 <5199396a-685c-4839-b7cb-d32e3f4a0b48@suse.com>
 <159de776-d0bf-4f77-a6b6-670246eca85e@epam.com>
 
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On 2025-08-21 16:28, Dmytro Prokopchuk1 wrote:
> On 8/21/25 17:13, Dmytro Prokopchuk wrote:
>> 
>> 
>> On 8/21/25 12:18, Jan Beulich wrote:
>>> On 20.08.2025 09:17, Dmytro Prokopchuk1 wrote:
>>>> MISRA C Rule 11.3 states: "A cast shall not be performed between a
>>>> pointer
>>>> to object type and a pointer to a different object type."
>>>> 
>>>> Violations of this rule arise due to the 'container_of' macro, which
>>>> casts
>>>> a member of a structure to its containing structure:
>>>>      container_of(ptr, type, member) ({                             
>>>> \
>>>>             typeof_field(type, member) *__mptr = (ptr);             
>>>> \
>>>>             (type *)( (char *)__mptr - offsetof(type,member) );})
>>>> 
>>>> The 'container_of' macro is safe because it relies on the
>>>> standardized and
>>>> well-defined 'offsetof' macro to calculate the memory address of the
>>>> containing structure, while assuming proper alignment and ensuring 
>>>> no
>>>> undefined behavior, provided that the input pointer is valid and
>>>> points to
>>>> the specified member.
>>>> 
>>>> Configure Eclair to suppress violation reports related to 
>>>> 'container_of
>>>> macro. Update 'deviations.rst' file accordingly. Add Rule 11.3 to 
>>>> the
>>>> monitored list.
>>>> No functional changes.
>>>> 
>>>> Signed-off-by: Dmytro Prokopchuk 
>>> 
>>> Looks largely okay; just one nit and a question:
>>> 
>>>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>>>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>>>> @@ -403,6 +403,14 @@ because the semantics of the 'noreturn'
>>>> attribute do not alter the calling conve
>>>>   }
>>>>   -doc_end
>>>> +-doc_begin="Convesions in the 'container_of' macro are safe because
>>>> it relies on
>>> 
>>> "Conversions" (also in deviations.rst)
>>> 
>>>> --- a/automation/eclair_analysis/ECLAIR/monitored.ecl
>>>> +++ b/automation/eclair_analysis/ECLAIR/monitored.ecl
>>>> @@ -45,6 +45,7 @@
>>>>   -enable=MC3A2.R10.2
>>>>   -enable=MC3A2.R11.1
>>>>   -enable=MC3A2.R11.2
>>>> +-enable=MC3A2.R11.3
>>> 
>>> While the description mentions this change, it doesn't say why (e.g. 
>>> "no
>>> violations left" or "only this and that violation left" or some 
>>> such).
>> ARM:  813V ->   16V
>> X86: 1422V -> 1035V
>> 
>> Looks OK for ARM (to be added in the monitoring list), but X86...
>> Anyway the number of reported errors has no side effect.
>> 
>> Jan, decision up to you (include into monitored.ecl or not).
>> 
>> Dmytro.
> 
> Actually, better way is to remove '-enable=MC3A2.R11.3' from the
> monitored.ecl file and create separate patch (in future).
> 

I agree

> Dmytro.
> 
>>> 
>>>> --- a/docs/misra/deviations.rst
>>>> +++ b/docs/misra/deviations.rst
>>>> @@ -393,6 +393,14 @@ Deviations related to MISRA C:2012 Rules:
>>>>          (i.e., less strict) alignment requirement are safe.
>>>>        - Tagged as `safe` for ECLAIR.
>>>> +   * - R11.3
>>>> +     - Convesions in the 'container_of' macro are safe because it
>>>> relies on
>>>> +       the standardized and well-defined 'offsetof' macro to
>>>> calculate the memory
>>> 
>>> Actually another nit: Here as well as in the description, it would be
>>> nice
>>> to add parentheses, so indicate the function-ness of both macros 
>>> (i.e.
>>> container_of() and offsetof()).
>>> 
>>> Jan

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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From: Dmytro Prokopchuk1 
To: Jan Beulich , Stefano Stabellini
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CC: Doug Goldstein , Andrew Cooper
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	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH] misra: add deviation for MISRA C Rule 11.3
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Date: Thu, 21 Aug 2025 14:51:16 +0000
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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RFC=20PATCH=201/9]=20x86/hvm:=20Use=20direct=20structures=20instead=20of=20guest=20handles?=
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To: xen-devel@lists.xenproject.org
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Make these functions work with hypervisor-owned pointer rather than
guest handles, so the function parameters don't have to live in guest memory.

No functional changes intended.

Signed-off-by: Teddy Astie 
---
 xen/arch/x86/hvm/hvm.c | 126 +++++++++++++++++++++++------------------
 1 file changed, 70 insertions(+), 56 deletions(-)

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 56c7de3977..8bf59c63fe 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4142,19 +4142,14 @@ static int hvmop_flush_tlb_all(void)
     return paging_flush_tlb(NULL) ? 0 : -ERESTART;
 }
 
-static int hvmop_set_evtchn_upcall_vector(
-    XEN_GUEST_HANDLE_PARAM(xen_hvm_evtchn_upcall_vector_t) uop)
+static int hvmop_set_evtchn_upcall_vector(xen_hvm_evtchn_upcall_vector_t op)
 {
-    xen_hvm_evtchn_upcall_vector_t op;
     struct domain *d = current->domain;
     struct vcpu *v;
 
     if ( !is_hvm_domain(d) )
         return -EINVAL;
 
-    if ( copy_from_guest(&op, uop, 1) )
-        return -EFAULT;
-
     if ( op.vector < 0x10 )
         return -EINVAL;
 
@@ -4434,26 +4429,21 @@ static int hvm_set_param(struct domain *d, uint32_t index, uint64_t value)
     return rc;
 }
 
-static int hvmop_set_param(
-    XEN_GUEST_HANDLE_PARAM(xen_hvm_param_t) arg)
+static int hvmop_set_param(struct xen_hvm_param op)
 {
-    struct xen_hvm_param a;
     struct domain *d;
     int rc;
 
-    if ( copy_from_guest(&a, arg, 1) )
-        return -EFAULT;
-
-    if ( a.index >= HVM_NR_PARAMS )
+    if ( op.index >= HVM_NR_PARAMS )
         return -EINVAL;
 
-    d = rcu_lock_domain_by_any_id(a.domid);
+    d = rcu_lock_domain_by_any_id(op.domid);
     if ( d == NULL )
         return -ESRCH;
 
     rc = -EINVAL;
     if ( is_hvm_domain(d) )
-        rc = hvm_set_param(d, a.index, a.value);
+        rc = hvm_set_param(d, op.index, op.value);
 
     rcu_unlock_domain(d);
     return rc;
@@ -4544,31 +4534,21 @@ int hvm_get_param(struct domain *d, uint32_t index, uint64_t *value)
     return 0;
 };
 
-static int hvmop_get_param(
-    XEN_GUEST_HANDLE_PARAM(xen_hvm_param_t) arg)
+static int hvmop_get_param(struct xen_hvm_param *op)
 {
-    struct xen_hvm_param a;
     struct domain *d;
     int rc;
 
-    if ( copy_from_guest(&a, arg, 1) )
-        return -EFAULT;
-
-    if ( a.index >= HVM_NR_PARAMS )
+    if ( op->index >= HVM_NR_PARAMS )
         return -EINVAL;
 
-    d = rcu_lock_domain_by_any_id(a.domid);
+    d = rcu_lock_domain_by_any_id(op->domid);
     if ( d == NULL )
         return -ESRCH;
 
     rc = -EINVAL;
-    if ( is_hvm_domain(d) && !(rc = hvm_get_param(d, a.index, &a.value)) )
-    {
-        rc = __copy_to_guest(arg, &a, 1) ? -EFAULT : 0;
-
-        HVM_DBG_LOG(DBG_LEVEL_HCALL, "get param %u = %"PRIx64,
-                    a.index, a.value);
-    }
+    if ( is_hvm_domain(d) && !(rc = hvm_get_param(d, op->index, &op->value)) )
+        HVM_DBG_LOG(DBG_LEVEL_HCALL, "get param %u = %"PRIx64, a.index, a.value);
 
     rcu_unlock_domain(d);
     return rc;
@@ -5046,18 +5026,13 @@ static int compat_altp2m_op(
     return rc;
 }
 
-static int hvmop_get_mem_type(
-    XEN_GUEST_HANDLE_PARAM(xen_hvm_get_mem_type_t) arg)
+static int hvmop_get_mem_type(struct xen_hvm_get_mem_type *op)
 {
-    struct xen_hvm_get_mem_type a;
     struct domain *d;
     p2m_type_t t;
     int rc;
 
-    if ( copy_from_guest(&a, arg, 1) )
-        return -EFAULT;
-
-    d = rcu_lock_domain_by_any_id(a.domid);
+    d = rcu_lock_domain_by_any_id(op->domid);
     if ( d == NULL )
         return -ESRCH;
 
@@ -5074,25 +5049,22 @@ static int hvmop_get_mem_type(
      * type, not in allocating or unsharing. That'll happen
      * on access.
      */
-    get_gfn_query_unlocked(d, a.pfn, &t);
+    get_gfn_query_unlocked(d, op->pfn, &t);
     if ( p2m_is_mmio(t) )
-        a.mem_type =  HVMMEM_mmio_dm;
+        op->mem_type =  HVMMEM_mmio_dm;
     else if ( t == p2m_ioreq_server )
-        a.mem_type = HVMMEM_ioreq_server;
+        op->mem_type = HVMMEM_ioreq_server;
     else if ( p2m_is_readonly(t) )
-        a.mem_type =  HVMMEM_ram_ro;
+        op->mem_type =  HVMMEM_ram_ro;
     else if ( p2m_is_ram(t) )
-        a.mem_type =  HVMMEM_ram_rw;
+        op->mem_type =  HVMMEM_ram_rw;
     else if ( p2m_is_pod(t) )
-        a.mem_type =  HVMMEM_ram_rw;
+        op->mem_type =  HVMMEM_ram_rw;
     else if ( p2m_is_grant(t) )
-        a.mem_type =  HVMMEM_ram_rw;
+        op->mem_type =  HVMMEM_ram_rw;
     else
-        a.mem_type =  HVMMEM_mmio_dm;
+        op->mem_type =  HVMMEM_mmio_dm;
 
-    rc = -EFAULT;
-    if ( __copy_to_guest(arg, &a, 1) )
-        goto out;
     rc = 0;
 
  out:
@@ -5115,28 +5087,70 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE_PARAM(void) arg)
     switch ( op )
     {
     case HVMOP_set_evtchn_upcall_vector:
-        rc = hvmop_set_evtchn_upcall_vector(
-            guest_handle_cast(arg, xen_hvm_evtchn_upcall_vector_t));
+    {
+        struct xen_hvm_evtchn_upcall_vector op;
+
+        if ( copy_from_guest(&op, arg, 1) )
+        {
+            rc = -EFAULT;
+            break;
+        }
+
+        rc = hvmop_set_evtchn_upcall_vector(op);
         break;
+    }
     
     case HVMOP_set_param:
-        rc = hvmop_set_param(
-            guest_handle_cast(arg, xen_hvm_param_t));
+    {
+        struct xen_hvm_param op;
+        
+        if ( copy_from_guest(&op, arg, 1) )
+        {
+            rc = -EFAULT;
+            break;
+        }
+
+        rc = hvmop_set_param(op);
         break;
+    }
 
     case HVMOP_get_param:
-        rc = hvmop_get_param(
-            guest_handle_cast(arg, xen_hvm_param_t));
+    {
+        struct xen_hvm_param op;
+        
+        if ( copy_from_guest(&op, arg, 1) )
+        {
+            rc = -EFAULT;
+            break;
+        }
+
+        rc = hvmop_get_param(&op);
+
+        if ( !rc && copy_to_guest(arg, &op, 1) )
+            rc = -EFAULT;
         break;
+    }
 
     case HVMOP_flush_tlbs:
         rc = guest_handle_is_null(arg) ? hvmop_flush_tlb_all() : -EINVAL;
         break;
 
     case HVMOP_get_mem_type:
-        rc = hvmop_get_mem_type(
-            guest_handle_cast(arg, xen_hvm_get_mem_type_t));
+    {
+        struct xen_hvm_get_mem_type op;
+
+        if ( copy_from_guest(&op, arg, 1) )
+        {
+            rc = -EFAULT;
+            break;
+        }
+        
+        rc = hvmop_get_mem_type(&op);
+
+        if ( !rc && copy_to_guest(arg, &op, 1) )
+            rc = -EFAULT;
         break;
+    }
 
     case HVMOP_pagetable_dying:
     {
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RFC=20PATCH=207/9]=20x86/hvm:=20Introduce=20FastABI=20implementation?=
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To: xen-devel@lists.xenproject.org
Cc: "Teddy Astie" , "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "Stefano Stabellini" , "Dario Faggioli" , "Juergen Gross" , "George Dunlap" , "Daniel P. Smith" 
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Implement FastABI basing on docs/guest-guide/x86/fastabi.pandoc and defined ABI.

Signed-off-by: Teddy Astie 
---
 xen/arch/x86/cpuid.c               |   3 +
 xen/arch/x86/domain.c              |  71 ++++++++++
 xen/arch/x86/hvm/hvm.c             |  81 +++++++++++-
 xen/arch/x86/hvm/hypercall.c       |  22 ++++
 xen/arch/x86/include/asm/fastabi.h |  17 +++
 xen/common/Kconfig                 |   6 +
 xen/common/Makefile                |   1 +
 xen/common/domain.c                | 179 ++++++++++++++++++++++++++
 xen/common/event_channel.c         | 199 +++++++++++++++++++++++++++++
 xen/common/fastabi.c               |  49 +++++++
 xen/common/grant_table.c           |  44 +++++++
 xen/common/kernel.c                |  33 +++++
 xen/common/memory.c                | 110 ++++++++++++++++
 xen/common/sched/core.c            | 109 +++++++++++++++-
 xen/include/public/event_channel.h |   7 +
 xen/include/public/fastabi.h       |  20 +++
 xen/include/xen/fastabi.h          |  21 +++
 17 files changed, 970 insertions(+), 2 deletions(-)
 create mode 100644 xen/arch/x86/include/asm/fastabi.h
 create mode 100644 xen/common/fastabi.c
 create mode 100644 xen/include/public/fastabi.h
 create mode 100644 xen/include/xen/fastabi.h

diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 8dc68945f7..b1f90c1d91 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -153,6 +153,9 @@ static void cpuid_hypervisor_leaves(const struct vcpu *v, uint32_t leaf,
          */
         res->a |= XEN_HVM_CPUID_UPCALL_VECTOR;
 
+        if ( IS_ENABLED(CONFIG_FASTABI) && is_hvm_vcpu(v) )
+            res->a |= XEN_HVM_CPUID_FASTABI;
+
         break;
 
     case 5: /* PV-specific parameters */
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 56c3816187..44416869a3 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -71,6 +71,10 @@
 #include 
 #include 
 
+#ifdef CONFIG_FASTABI
+#include 
+#endif
+
 #ifdef CONFIG_COMPAT
 #include 
 #endif
@@ -1695,6 +1699,73 @@ long do_vcpu_op(int cmd, unsigned int vcpuid, XEN_GUEST_HANDLE_PARAM(void) arg)
     return rc;
 }
 
+#ifdef CONFIG_FASTABI
+void do_vcpu_fast_op(struct cpu_user_regs *regs)
+{
+    long rc = 0;
+    struct domain *d = current->domain;
+    struct vcpu *v;
+
+    unsigned long cmd = fastabi_value_n(regs, 1);
+    unsigned long vcpuid = fastabi_value_n(regs, 2);
+
+    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
+    {
+        fastabi_value_n(regs, 0) = -ENOENT;
+        return;
+    }
+
+    switch ( cmd )
+    {
+    case VCPUOP_send_nmi:
+        if ( !test_and_set_bool(v->arch.nmi_pending) )
+            vcpu_kick(v);
+        break;
+
+
+    case VCPUOP_register_vcpu_time_phys_area:
+    {
+        struct vcpu_register_time_memory_area area = {
+            .addr.p = fastabi_value_n(regs, 3)
+        };
+
+        rc = -ENOSYS;
+        if ( 0 /* TODO: Dom's XENFEAT_vcpu_time_phys_area setting */ )
+            break;
+
+        rc = map_guest_area(v, area.addr.p,
+                            sizeof(vcpu_time_info_t),
+                            &v->arch.time_guest_area,
+                            time_area_populate);
+        break;
+    }
+
+    case VCPUOP_get_physid:
+    {
+        rc = -EINVAL;
+        if ( !is_hwdom_pinned_vcpu(v) )
+            break;
+
+        fastabi_value_n(regs, 3) =
+            (uint64_t)x86_cpu_to_apicid[v->vcpu_id] |
+            ((uint64_t)acpi_get_processor_id(v->vcpu_id) << 32);
+
+        rc = 0;
+        break;
+    }
+
+    default:
+        rc = common_vcpu_fast_op(regs, cmd, v);
+        break;
+    }
+
+    if ( rc == -ERESTART )
+        fastabi_make_continuation();
+    else
+        fastabi_value_n(regs, 0) = rc;
+}
+#endif
+
 /*
  * Notes on PV segment handling:
  *  - 32bit: All data from the GDT/LDT.
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 8bf59c63fe..eca052e109 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -68,6 +68,10 @@
 
 #include 
 
+#ifdef CONFIG_FASTABI
+#include 
+#endif
+
 bool __read_mostly hvm_enabled;
 
 #ifdef DBG_LEVEL_0
@@ -4548,7 +4552,7 @@ static int hvmop_get_param(struct xen_hvm_param *op)
 
     rc = -EINVAL;
     if ( is_hvm_domain(d) && !(rc = hvm_get_param(d, op->index, &op->value)) )
-        HVM_DBG_LOG(DBG_LEVEL_HCALL, "get param %u = %"PRIx64, a.index, a.value);
+        HVM_DBG_LOG(DBG_LEVEL_HCALL, "get param %u = %"PRIx64, op->index, op->value);
 
     rcu_unlock_domain(d);
     return rc;
@@ -5224,6 +5228,81 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE_PARAM(void) arg)
     return rc;
 }
 
+#ifdef CONFIG_FASTABI
+void do_hvm_fast_op(struct cpu_user_regs *regs)
+{
+    long rc = 0;
+    unsigned long op = fastabi_value_n(regs, 1);
+
+    switch ( op )
+    {
+    case HVMOP_set_evtchn_upcall_vector:
+    {
+        struct xen_hvm_evtchn_upcall_vector op = {
+            .vcpu = fastabi_value_n(regs, 2),
+            .vector = fastabi_value_n(regs, 3),
+        };
+
+        rc = hvmop_set_evtchn_upcall_vector(op);
+        break;
+    }
+
+    case HVMOP_set_param:
+    {
+        struct xen_hvm_param op = {
+            .domid = fastabi_value_n(regs, 2),
+            .index = fastabi_value_n(regs, 3),
+            .value = fastabi_value_n(regs, 4),
+        };
+
+        rc = hvmop_set_param(op);
+        break;
+    }
+
+    case HVMOP_get_param:
+    {
+        struct xen_hvm_param op = {
+            .domid = fastabi_value_n(regs, 2),
+            .index = fastabi_value_n(regs, 3),
+        };
+
+        rc = hvmop_get_param(&op);
+        if ( !rc )
+            fastabi_value_n(regs, 4) = op.value;
+        break;
+    }
+
+    case HVMOP_flush_tlbs:
+        rc = hvmop_flush_tlb_all();
+        break;
+
+    case HVMOP_get_time:
+        fastabi_value_n(regs, 2) = NOW();
+        break;
+    
+    case HVMOP_get_mem_type:
+    {
+        struct xen_hvm_get_mem_type op = {
+            .domid = fastabi_value_n(regs, 2),
+            .pfn = fastabi_value_n(regs, 3),
+        };
+
+        rc = hvmop_get_mem_type(&op);
+
+        if ( !rc )
+            fastabi_value_n(regs, 4) = op.mem_type;
+        break;
+    }
+
+    default:
+        rc = -ENOSYS;
+        break;
+    }
+
+    fastabi_value_n(regs, 0) = rc;
+}
+#endif
+
 int hvm_debug_op(struct vcpu *v, int32_t op)
 {
     int rc = 0;
diff --git a/xen/arch/x86/hvm/hypercall.c b/xen/arch/x86/hvm/hypercall.c
index 6f8dfdff4a..3759a1aa58 100644
--- a/xen/arch/x86/hvm/hypercall.c
+++ b/xen/arch/x86/hvm/hypercall.c
@@ -19,6 +19,10 @@
 #include 
 #include 
 
+#ifdef CONFIG_FASTABI
+#include 
+#endif
+
 long hvm_memory_op(unsigned long cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
 {
     long rc;
@@ -155,6 +159,24 @@ int hvm_hypercall(struct cpu_user_regs *regs)
 
     curr->hcall_preempted = false;
 
+    #ifdef CONFIG_FASTABI
+    if ( eax & 0x40000000U && is_hvm_domain(currd) && mode == X86_MODE_64BIT )
+    {
+        unsigned long index = eax & ~0x40000000U;
+        HVM_DBG_LOG(DBG_LEVEL_HCALL,
+                    "fasthcall%lu(%lx, %lx, %lx, %lx, %lx, %lx, %lx)",
+                    index, fastabi_value_n(regs, 1), fastabi_value_n(regs, 2),
+                    fastabi_value_n(regs, 3), fastabi_value_n(regs, 4),
+                    fastabi_value_n(regs, 5), fastabi_value_n(regs, 6),
+                    fastabi_value_n(regs, 7));
+
+        fastabi_dispatch(index, regs);
+
+        hvmemul_cache_restore(curr, token);
+        return HVM_HCALL_completed;
+    }
+    #endif
+
     if ( mode == 8 )
     {
         HVM_DBG_LOG(DBG_LEVEL_HCALL, "hcall%lu(%lx, %lx, %lx, %lx, %lx)",
diff --git a/xen/arch/x86/include/asm/fastabi.h b/xen/arch/x86/include/asm/fastabi.h
new file mode 100644
index 0000000000..914504c63d
--- /dev/null
+++ b/xen/arch/x86/include/asm/fastabi.h
@@ -0,0 +1,17 @@
+#ifndef XEN_ASM_FASTABI_H
+#define XEN_ASM_FASTABI_H
+
+#include 
+
+#define fastabi_param_reg0 rax
+#define fastabi_param_reg1 rdi
+#define fastabi_param_reg2 rsi
+#define fastabi_param_reg3 r8
+#define fastabi_param_reg4 r9
+#define fastabi_param_reg5 r10
+#define fastabi_param_reg6 r11
+#define fastabi_param_reg7 r12
+
+#define fastabi_value_n(regs, n) (regs)->fastabi_param_reg##n
+
+#endif /* XEN_ASM_FASTABI_H */
\ No newline at end of file
diff --git a/xen/common/Kconfig b/xen/common/Kconfig
index 65f07289dd..71bb4e4f2d 100644
--- a/xen/common/Kconfig
+++ b/xen/common/Kconfig
@@ -636,4 +636,10 @@ config PM_STATS
 	  Enable collection of performance management statistics to aid in
 	  analyzing and tuning power/performance characteristics of the system
 
+config FASTABI
+	depends on X86 && HVM
+	bool "Fast HVM ABI (unsupported)"
+	help
+		Add support for a alternative fast HVM ABI.
+
 endmenu
diff --git a/xen/common/Makefile b/xen/common/Makefile
index 98f0873056..362e8f61d7 100644
--- a/xen/common/Makefile
+++ b/xen/common/Makefile
@@ -62,6 +62,7 @@ obj-y += wait.o
 obj-bin-y += warning.init.o
 obj-$(CONFIG_XENOPROF) += xenoprof.o
 obj-y += xmalloc_tlsf.o
+obj-$(CONFIG_FASTABI) += fastabi.o
 
 obj-bin-$(CONFIG_X86) += $(foreach n,decompress bunzip2 unxz unlzma lzo unlzo unlz4 unzstd earlycpio,$(n).init.o)
 
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 303c338ef2..5a641403b9 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -45,6 +45,10 @@
 #include 
 #include 
 
+#ifdef CONFIG_FASTABI
+#include 
+#endif
+
 #ifdef CONFIG_X86
 #include 
 #endif
@@ -2266,6 +2270,181 @@ long common_vcpu_op(int cmd, struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg)
     return rc;
 }
 
+#ifdef CONFIG_FASTABI
+long common_vcpu_fast_op(struct cpu_user_regs *regs, int cmd, struct vcpu *v)
+{
+    long rc = 0;
+    struct domain *d = v->domain;
+    unsigned int vcpuid = v->vcpu_id;
+
+    switch ( cmd )
+    {
+    case VCPUOP_initialise:
+        rc = arch_initialise_vcpu(v, (XEN_GUEST_HANDLE(void)) { 
+            (void *)fastabi_value_n(regs, 2) });
+        break;
+
+    case VCPUOP_up:
+    {
+        bool wake = false;
+
+        domain_lock(d);
+        if ( !v->is_initialised )
+            rc = -EINVAL;
+        else
+            wake = test_and_clear_bit(_VPF_down, &v->pause_flags);
+        domain_unlock(d);
+        if ( wake )
+            vcpu_wake(v);
+    }
+
+        break;
+
+    case VCPUOP_down:
+        for_each_vcpu ( d, v )
+            if ( !test_bit(_VPF_down, &v->pause_flags) )
+            {
+               rc = 1;
+               break;
+            }
+
+        if ( !rc ) /* Last vcpu going down? */
+        {
+            domain_shutdown(d, SHUTDOWN_poweroff);
+            break;
+        }
+
+        rc = 0;
+        v = d->vcpu[vcpuid];
+
+        if ( !test_and_set_bit(_VPF_down, &v->pause_flags) )
+            vcpu_sleep_nosync(v);
+
+        break;
+
+    case VCPUOP_is_up:
+        rc = !(v->pause_flags & VPF_down);
+        break;
+
+    case VCPUOP_get_runstate_info:
+    {
+        struct vcpu_runstate_info runstate;
+        vcpu_runstate_get(v, &runstate);
+
+        fastabi_value_n(regs, 2) = runstate.state;
+        fastabi_value_n(regs, 3) = runstate.state_entry_time;
+        fastabi_value_n(regs, 4) = runstate.time[0];
+        fastabi_value_n(regs, 5) = runstate.time[1];
+        fastabi_value_n(regs, 6) = runstate.time[2];
+        fastabi_value_n(regs, 7) = runstate.time[3];
+        break;
+    }
+
+    case VCPUOP_set_periodic_timer:
+    {
+        uint64_t period_ns = fastabi_value_n(regs, 3);
+
+        if ( period_ns < MILLISECS(1) )
+            return -EINVAL;
+
+        if ( period_ns > STIME_DELTA_MAX )
+            return -EINVAL;
+
+        vcpu_set_periodic_timer(v, period_ns);
+
+        break;
+    }
+
+    case VCPUOP_stop_periodic_timer:
+        vcpu_set_periodic_timer(v, 0);
+        break;
+
+    case VCPUOP_set_singleshot_timer:
+    {
+        struct vcpu_set_singleshot_timer set = {
+            .timeout_abs_ns = fastabi_value_n(regs, 3),
+            .flags = fastabi_value_n(regs, 4),
+        };
+
+        if ( v != current )
+            return -EINVAL;
+
+        if ( set.timeout_abs_ns < NOW() )
+        {
+            /*
+             * Simplify the logic if the timeout has already expired and just
+             * inject the event.
+             */
+            stop_timer(&v->singleshot_timer);
+            send_timer_event(v);
+            break;
+        }
+
+        migrate_timer(&v->singleshot_timer, smp_processor_id());
+        set_timer(&v->singleshot_timer, set.timeout_abs_ns);
+
+        break;
+    }
+
+    case VCPUOP_stop_singleshot_timer:
+        if ( v != current )
+            return -EINVAL;
+
+        stop_timer(&v->singleshot_timer);
+
+        break;
+
+    case VCPUOP_register_vcpu_info:
+    {
+        struct vcpu_register_vcpu_info info = {
+            .mfn = fastabi_value_n(regs, 3),
+            .offset = fastabi_value_n(regs, 4)
+        };
+        paddr_t gaddr;
+
+        rc = -EINVAL;
+        gaddr = gfn_to_gaddr(_gfn(info.mfn)) + info.offset;
+        if ( !~gaddr ||
+             gfn_x(gaddr_to_gfn(gaddr)) != info.mfn )
+            break;
+
+        /* Preliminary check only; see map_guest_area(). */
+        rc = -EBUSY;
+        if ( v->vcpu_info_area.pg )
+            break;
+
+        /* See the BUILD_BUG_ON() in vcpu_info_populate(). */
+        rc = map_guest_area(v, gaddr, sizeof(vcpu_info_t),
+                            &v->vcpu_info_area, vcpu_info_populate);
+        break;
+    }
+
+    case VCPUOP_register_runstate_phys_area:
+    {
+        struct vcpu_register_runstate_memory_area area = {
+            .addr.p = fastabi_value_n(regs, 3)
+        };
+
+        rc = -ENOSYS;
+        if ( 0 /* TODO: Dom's XENFEAT_runstate_phys_area setting */ )
+            break;
+
+        rc = map_guest_area(v, area.addr.p,
+                            sizeof(struct vcpu_runstate_info),
+                            &v->runstate_guest_area,
+                            runstate_area_populate);
+        break;
+    }
+
+    default:
+        rc = -ENOSYS;
+        break;
+    }
+
+    return rc;
+}
+#endif
+
 #ifdef arch_vm_assist_valid_mask
 long do_vm_assist(unsigned int cmd, unsigned int type)
 {
diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index c8c1bfa615..9c8bc0f354 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -34,6 +34,10 @@
 #include 
 #include 
 
+#ifdef CONFIG_FASTABI
+#include 
+#endif
+
 #ifdef CONFIG_PV_SHIM
 #include 
 #endif
@@ -1507,6 +1511,201 @@ long do_event_channel_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
     return rc;
 }
 
+#ifdef CONFIG_FASTABI
+void do_event_channel_fast_op(struct cpu_user_regs *regs)
+{
+    long rc;
+    uint64_t cmd = fastabi_value_n(regs, 1);
+
+    switch ( cmd )
+    {
+    case EVTCHNOP_alloc_unbound: {
+        struct evtchn_alloc_unbound alloc_unbound = {
+            .dom = fastabi_value_n(regs, 2),
+            .remote_dom = fastabi_value_n(regs, 3),
+            .port = 0,
+        };
+        rc = evtchn_alloc_unbound(&alloc_unbound, 0);
+
+        if ( !rc )
+            fastabi_value_n(regs, 4) = alloc_unbound.port;
+        break;
+    }
+
+    case EVTCHNOP_bind_interdomain: {
+        struct evtchn_bind_interdomain bind_interdomain = {
+            .remote_dom = fastabi_value_n(regs, 2),
+            .remote_port = fastabi_value_n(regs, 3),
+            .local_port = 0,
+        };
+        rc = evtchn_bind_interdomain(&bind_interdomain, current->domain, 0);
+
+        if ( !rc )
+            fastabi_value_n(regs, 4) = bind_interdomain.local_port;
+        break;
+    }
+
+    case EVTCHNOP_bind_virq: {
+        struct evtchn_bind_virq bind_virq = {
+            .virq = fastabi_value_n(regs, 2),
+            .vcpu = fastabi_value_n(regs, 3),
+            .port = 0,
+        };
+        rc = evtchn_bind_virq(&bind_virq, 0);
+
+        if ( !rc )
+            fastabi_value_n(regs, 4) = bind_virq.port;
+        break;
+    }
+
+    case EVTCHNOP_bind_ipi: {
+        struct evtchn_bind_ipi bind_ipi = {
+            .vcpu = fastabi_value_n(regs, 2),
+            .port = 0,
+        };
+        rc = evtchn_bind_ipi(&bind_ipi);
+
+        if ( !rc )
+            fastabi_value_n(regs, 4) = bind_ipi.port;
+        break;
+    }
+
+    case EVTCHNOP_bind_pirq: {
+        struct evtchn_bind_pirq bind_pirq = {
+            .pirq = fastabi_value_n(regs, 2),
+            .flags = fastabi_value_n(regs, 3),
+        };
+        rc = evtchn_bind_pirq(&bind_pirq);
+
+        if ( !rc )
+            fastabi_value_n(regs, 4) = bind_pirq.port;
+        break;
+    }
+
+    case EVTCHNOP_close: {
+        struct evtchn_close close = { .port = fastabi_value_n(regs, 2) };
+        rc = evtchn_close(current->domain, close.port, 1);
+        break;
+    }
+
+    case EVTCHNOP_send: {
+        struct evtchn_send send = { .port = fastabi_value_n(regs, 2) };
+        rc = evtchn_send(current->domain, send.port);
+        break;
+    }
+
+    case EVTCHNOP_status: {
+        struct evtchn_status status = {
+            .dom = fastabi_value_n(regs, 2),
+            .port = fastabi_value_n(regs, 3),
+        };
+        rc = evtchn_status(&status);
+
+        if ( !rc )
+        {
+            fastabi_value_n(regs, 4) = status.status;
+            fastabi_value_n(regs, 5) = status.vcpu;
+
+            switch (status.status)
+            {
+            case EVTCHNSTAT_unbound:
+                fastabi_value_n(regs, 6) = status.u.unbound.dom;
+                break;
+            case EVTCHNSTAT_interdomain:
+                fastabi_value_n(regs, 6) = status.u.interdomain.dom;
+                fastabi_value_n(regs, 7) = status.u.interdomain.port;
+                break;
+            case EVTCHNSTAT_pirq:
+                fastabi_value_n(regs, 6) = status.u.pirq;
+                break;
+            case EVTCHNSTAT_virq:
+                fastabi_value_n(regs, 6) = status.u.virq;
+                break;
+            default:
+                break;
+            }
+        }
+        break;
+    }
+
+    case EVTCHNOP_bind_vcpu: {
+        struct evtchn_bind_vcpu bind_vcpu = {
+            .vcpu = fastabi_value_n(regs, 2),
+            .port = fastabi_value_n(regs, 3)
+        };
+        rc = evtchn_bind_vcpu(bind_vcpu.port, bind_vcpu.vcpu);
+        break;
+    }
+
+    case EVTCHNOP_unmask: {
+        struct evtchn_unmask unmask = { .port = fastabi_value_n(regs, 2) };
+        rc = evtchn_unmask(unmask.port);
+        break;
+    }
+
+    case EVTCHNOP_reset:
+    case EVTCHNOP_reset_cont: {
+        struct evtchn_reset reset = { .dom = fastabi_value_n(regs, 2) };
+        struct domain *d;
+
+        d = rcu_lock_domain_by_any_id(reset.dom);
+        if ( d == NULL )
+        {
+            rc = -ESRCH;
+            break;
+        }
+
+        rc = xsm_evtchn_reset(XSM_TARGET, current->domain, d);
+        if ( !rc )
+            rc = evtchn_reset(d, cmd == EVTCHNOP_reset_cont);
+
+        rcu_unlock_domain(d);
+
+        if ( rc == -ERESTART )
+        {
+            fastabi_value_n(regs, 1) = EVTCHNOP_reset_cont;
+            fastabi_make_continuation();
+            return;
+        }
+        break;
+    }
+
+    case EVTCHNOP_init_control: {
+        struct evtchn_init_control init_control = {
+            .control_gfn = fastabi_value_n(regs, 2),
+            .offset = fastabi_value_n(regs, 3),
+            .vcpu = fastabi_value_n(regs, 4)
+        };
+        rc = evtchn_fifo_init_control(&init_control);
+
+        if ( !rc )
+            fastabi_value_n(regs, 5) = init_control.link_bits;
+        break;
+    }
+
+    case EVTCHNOP_expand_array: {
+        struct evtchn_expand_array expand_array = { .array_gfn = fastabi_value_n(regs, 2) };
+        rc = evtchn_fifo_expand_array(&expand_array);
+        break;
+    }
+
+    case EVTCHNOP_set_priority: {
+        struct evtchn_set_priority set_priority = {
+            .port = fastabi_value_n(regs, 2),
+            .priority = fastabi_value_n(regs, 3),
+        };
+        rc = evtchn_set_priority(&set_priority);
+        break;
+    }
+
+    default:
+        rc = -ENOSYS;
+        break;
+    }
+
+    fastabi_value_n(regs, 0) = rc;
+}
+#endif
 
 int alloc_unbound_xen_event_channel(
     struct domain *ld, unsigned int lvcpu, domid_t remote_domid,
diff --git a/xen/common/fastabi.c b/xen/common/fastabi.c
new file mode 100644
index 0000000000..96a3b05ee7
--- /dev/null
+++ b/xen/common/fastabi.c
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include 
+#include 
+#include 
+
+#include 
+
+void fastabi_make_continuation(void)
+{
+    current->hcall_preempted = true;
+}
+
+void fastabi_dispatch(unsigned long index, struct cpu_user_regs *regs)
+{
+    switch (index) {
+    case __HYPERVISOR_memory_op:
+        do_memory_fast_op(regs);
+        break;
+
+    case __HYPERVISOR_xen_version:
+        do_xen_version_fast_op(regs);
+        break;
+    
+    case __HYPERVISOR_grant_table_op:
+        do_grant_table_fast_op(regs);
+        break;
+
+    case __HYPERVISOR_vcpu_op:
+        do_vcpu_fast_op(regs);
+        break;
+
+    case __HYPERVISOR_sched_op:
+        do_sched_fast_op(regs);
+        break;
+
+    case __HYPERVISOR_event_channel_op:
+        do_event_channel_fast_op(regs);
+        break;
+
+    case __HYPERVISOR_hvm_op:
+        do_hvm_fast_op(regs);
+        break;
+
+    default:
+        fastabi_value_n(regs, 0) = -ENOSYS;
+        break;
+    }
+}
\ No newline at end of file
diff --git a/xen/common/grant_table.c b/xen/common/grant_table.c
index 3c3bbca2fc..1476e5e5ca 100644
--- a/xen/common/grant_table.c
+++ b/xen/common/grant_table.c
@@ -45,6 +45,10 @@
 #include 
 #include 
 
+#ifdef CONFIG_FASTABI
+#include 
+#endif
+
 #ifdef CONFIG_PV_SHIM
 #include 
 #endif
@@ -3826,6 +3830,46 @@ long do_grant_table_op(
     return rc;
 }
 
+#ifdef CONFIG_FASTABI
+void do_grant_table_fast_op(struct cpu_user_regs *regs)
+{
+    long rc = 0;
+    unsigned int cmd = fastabi_value_n(regs, 1);
+
+    switch (cmd)
+    {
+    case GNTTABOP_query_size:
+    {
+        struct grant_table *gt = current->domain->grant_table;
+
+        grant_read_lock(gt);
+        fastabi_value_n(regs, 2) = nr_grant_frames(gt);
+        fastabi_value_n(regs, 3) = gt->max_grant_frames;
+        grant_read_unlock(gt);
+        break;
+    }
+    case GNTTABOP_get_version:
+    {
+        struct grant_table *gt = current->domain->grant_table;
+
+        fastabi_value_n(regs, 2) = gt->gt_version;
+        break;
+    }
+    case GNTTABOP_set_version:
+    {
+        gnttab_set_version_t op = { .version = fastabi_value_n(regs, 2) };
+        rc = gnttab_set_version(&op);
+        break;
+    }
+    default:
+        rc = -ENOSYS;
+        break;
+    }
+
+    fastabi_value_n(regs, 0) = rc;
+}
+#endif
+
 #ifdef CONFIG_COMPAT
 #include "compat/grant_table.c"
 #endif
diff --git a/xen/common/kernel.c b/xen/common/kernel.c
index eff6db6c8f..2230ccdcaf 100644
--- a/xen/common/kernel.c
+++ b/xen/common/kernel.c
@@ -18,6 +18,10 @@
 #include 
 #include 
 
+#ifdef CONFIG_FASTABI
+#include 
+#endif
+
 #ifdef CONFIG_COMPAT
 #include 
 
@@ -772,6 +776,35 @@ long do_xen_version(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
     return -ENOSYS;
 }
 
+#ifdef CONFIG_FASTABI
+void do_xen_version_fast_op(struct cpu_user_regs *regs)
+{
+    long cmd = fastabi_value_n(regs, 1);
+    long rc = 0;
+
+    switch ( cmd ) {
+    case XENVER_version:
+        rc = (xen_major_version() << 16) | xen_minor_version();
+        break;
+    case XENVER_get_features:
+    {
+        uint32_t submap = 0, submap_idx = fastabi_value_n(regs, 2);
+
+        rc = xenver_get_features(current->domain, submap_idx, &submap);
+
+        if ( !rc )
+            fastabi_value_n(regs, 3) = submap;
+        break;
+    }
+    default:
+        rc = -ENOSYS;
+        break;
+    }
+
+    fastabi_value_n(regs, 0) = rc;
+}
+#endif
+
 /*
  * Local variables:
  * mode: C
diff --git a/xen/common/memory.c b/xen/common/memory.c
index 3688e6dd50..689218390e 100644
--- a/xen/common/memory.c
+++ b/xen/common/memory.c
@@ -35,6 +35,10 @@
 #include 
 #include 
 
+#ifdef CONFIG_FASTABI
+#include 
+#endif
+
 #ifdef CONFIG_X86
 #include 
 #endif
@@ -1864,6 +1868,112 @@ long do_memory_op(unsigned long cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
     return rc;
 }
 
+#ifdef CONFIG_FASTABI
+void do_memory_fast_op(struct cpu_user_regs *regs)
+{
+    unsigned long cmd = fastabi_value_n(regs, 1);
+    unsigned long start_extent = cmd >> MEMOP_EXTENT_SHIFT;
+    long rc;
+    int op = cmd & MEMOP_CMD_MASK;
+
+    switch ( op ) {
+    case XENMEM_add_to_physmap:
+    {
+        struct xen_add_to_physmap xatp = {
+            .size = fastabi_value_n(regs, 2),
+            .space = fastabi_value_n(regs, 3),
+            .idx = fastabi_value_n(regs, 4),
+            .gpfn = fastabi_value_n(regs, 5)
+        };
+
+        BUILD_BUG_ON((typeof(xatp.size))-1 > (UINT_MAX >> MEMOP_EXTENT_SHIFT));
+
+        /* Check for malicious or buggy input. */
+        if ( start_extent != (typeof(xatp.size))start_extent )
+        {
+            rc = -EDOM;
+            break;
+        }
+
+        /* Foreign mapping is only possible via add_to_physmap_batch. */
+        if ( xatp.space == XENMAPSPACE_gmfn_foreign )
+        {
+            rc = -ENOSYS;
+            break;
+        }
+
+        rc = xatp_permission_check(current->domain, xatp.space);
+        if ( rc )
+            break;
+
+        rc = xenmem_add_to_physmap(current->domain, &xatp, start_extent);
+
+        if ( xatp.space == XENMAPSPACE_gmfn_range && rc > 0 )
+            panic("TODO");
+            //rc = hypercall_create_continuation(
+            //         __HYPERVISOR_memory_op, "lh",
+            //         op | (rc << MEMOP_EXTENT_SHIFT), arg);
+        break;
+    }
+    
+    case XENMEM_remove_from_physmap:
+    {
+        unsigned long gpfn = fastabi_value_n(regs, 5);
+        struct page_info *page;
+
+        if ( unlikely(start_extent) )
+        {
+            rc = -EINVAL;
+            break;
+        }
+
+        if ( !paging_mode_translate(current->domain) )
+        {
+            rc = -EACCES;
+            break;
+        }
+
+        page = get_page_from_gfn(current->domain, gpfn, NULL, P2M_ALLOC);
+        if ( page )
+        {
+            rc = guest_physmap_remove_page(current->domain, _gfn(gpfn),
+                                           page_to_mfn(page), 0);
+            put_page(page);
+        }
+        else
+            rc = -ENOENT;
+
+        break;
+    }
+    
+    case XENMEM_memory_map:
+    {
+        struct domain *d = current->domain;
+        unsigned long nr_entries = fastabi_value_n(regs, 2);
+        paddr_t buffer_addr = fastabi_value_n(regs, 3);
+
+        spin_lock(&d->arch.e820_lock);
+
+        if ( nr_entries > d->arch.nr_e820 )
+            nr_entries = d->arch.nr_e820;
+
+        if ( hvm_copy_to_guest_phys(buffer_addr, d->arch.e820,
+                                    nr_entries * sizeof(struct e820entry), current) )
+            rc = -EFAULT;
+
+        spin_unlock(&d->arch.e820_lock);
+        break;
+    }
+
+    default:
+        rc = -ENOSYS;
+        break;
+    }
+
+    fastabi_value_n(regs, 0) = rc;
+}
+#endif
+
 void clear_domain_page(mfn_t mfn)
 {
     void *ptr = map_domain_page(mfn);
diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c
index b2c784c60e..51b2fbc00a 100644
--- a/xen/common/sched/core.c
+++ b/xen/common/sched/core.c
@@ -41,6 +41,10 @@
 
 #include "private.h"
 
+#ifdef CONFIG_FASTABI
+#include 
+#endif
+
 #ifdef CONFIG_XEN_GUEST
 #include 
 #else
@@ -1896,6 +1900,110 @@ void domain_update_node_aff(struct domain *d, struct affinity_masks *affinity)
 
 typedef long ret_t;
 
+#ifdef CONFIG_FASTABI
+void do_sched_fast_op(struct cpu_user_regs *regs)
+{
+    long ret = 0;
+    unsigned long cmd = fastabi_value_n(regs, 1);
+
+    switch ( cmd )
+    {
+    case SCHEDOP_yield:
+    {
+        ret = vcpu_yield();
+        break;
+    }
+
+    case SCHEDOP_block:
+    {
+        vcpu_block_enable_events();
+        break;
+    }
+
+    case SCHEDOP_shutdown:
+    {
+        struct sched_shutdown sched_shutdown = {
+            .reason = fastabi_value_n(regs, 2)
+        };
+
+        TRACE_TIME(TRC_SCHED_SHUTDOWN, current->domain->domain_id,
+                   current->vcpu_id, sched_shutdown.reason);
+        ret = domain_shutdown(current->domain, (u8)sched_shutdown.reason);
+
+        break;
+    }
+
+    case SCHEDOP_shutdown_code:
+    {
+        struct sched_shutdown sched_shutdown = {
+            .reason = fastabi_value_n(regs, 2)
+        };
+        struct domain *d = current->domain;
+
+        TRACE_TIME(TRC_SCHED_SHUTDOWN_CODE, d->domain_id, current->vcpu_id,
+                   sched_shutdown.reason);
+
+        spin_lock(&d->shutdown_lock);
+        if ( d->shutdown_code == SHUTDOWN_CODE_INVALID )
+            d->shutdown_code = (u8)sched_shutdown.reason;
+        spin_unlock(&d->shutdown_lock);
+
+        ret = 0;
+        break;
+    }
+
+    case SCHEDOP_poll:
+    {
+        uint64_t timeout = fastabi_value_n(regs, 2);
+        evtchn_port_t port = fastabi_value_n(regs, 3);
+
+        ret = vcpu_poll(1, timeout, &port);
+
+        break;
+    }
+
+    case SCHEDOP_watchdog:
+    {
+        struct sched_watchdog sched_watchdog = {
+            .id = fastabi_value_n(regs, 2),
+            .timeout = fastabi_value_n(regs, 3)
+        };
+
+        ret = domain_watchdog(
+            current->domain, sched_watchdog.id, sched_watchdog.timeout);
+        break;
+    }
+
+    case SCHEDOP_pin_override:
+    {
+        struct sched_pin_override sched_pin_override = {
+            .pcpu = fastabi_value_n(regs, 2),
+        };
+        unsigned int cpu;
+
+        ret = -EPERM;
+        if ( !is_hardware_domain(current->domain) )
+            break;
+
+        ret = -EINVAL;
+        if ( sched_pin_override.pcpu >= NR_CPUS )
+           break;
+
+        cpu = sched_pin_override.pcpu < 0 ? NR_CPUS : sched_pin_override.pcpu;
+        ret = vcpu_temporary_affinity(current, cpu, VCPU_AFFINITY_OVERRIDE);
+
+        break;
+    }
+
+    default:
+        ret = -ENOSYS;
+        break;
+    }
+
+    fastabi_value_n(regs, 0) = ret;
+}
+#endif
+
 #endif /* !COMPAT */
 
 ret_t do_sched_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
@@ -1961,7 +2069,6 @@ ret_t do_sched_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
             break;
 
         ret = do_poll(&sched_poll);
-
         break;
     }
 
diff --git a/xen/include/public/event_channel.h b/xen/include/public/event_channel.h
index c5548d206c..969c9ec264 100644
--- a/xen/include/public/event_channel.h
+++ b/xen/include/public/event_channel.h
@@ -208,10 +208,17 @@ struct evtchn_status {
         } unbound;                 /* EVTCHNSTAT_unbound */
         struct {
             domid_t dom;
+            uint16_t _pad;
             evtchn_port_t port;
         } interdomain;             /* EVTCHNSTAT_interdomain */
         uint32_t pirq;             /* EVTCHNSTAT_pirq        */
         uint32_t virq;             /* EVTCHNSTAT_virq        */
+#ifndef __XEN__
+        struct {
+            uint32_t _output1;
+            uint32_t _output2;
+        };
+#endif
     } u;
 };
 typedef struct evtchn_status evtchn_status_t;
diff --git a/xen/include/public/fastabi.h b/xen/include/public/fastabi.h
new file mode 100644
index 0000000000..51f5085ce6
--- /dev/null
+++ b/xen/include/public/fastabi.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+#ifndef __XEN_PUBLIC_FASTABI_H__
+#define __XEN_PUBLIC_FASTABI_H__
+
+#if defined(__x86_64__)
+#define __HYPERVISOR_FASTABI_MASK 0x40000000U
+
+enum xen_hypercall_vendor {
+    Intel,
+    Amd
+};
+#else
+#define __HYPERVISOR_FASTABI_MASK 0
+
+enum xen_hypercall_vendor {
+    Native
+};
+#endif
+
+#endif
diff --git a/xen/include/xen/fastabi.h b/xen/include/xen/fastabi.h
new file mode 100644
index 0000000000..83ede943e0
--- /dev/null
+++ b/xen/include/xen/fastabi.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef XEN_FASTABI_H
+#define XEN_FASTABI_H
+
+#include 
+
+void fastabi_dispatch(unsigned long index, struct cpu_user_regs *regs);
+void fastabi_make_continuation(void);
+
+void do_event_channel_fast_op(struct cpu_user_regs *regs);
+
+long common_vcpu_fast_op(struct cpu_user_regs *regs, int cmd, struct vcpu *v);
+void do_vcpu_fast_op(struct cpu_user_regs *regs);
+void do_hvm_fast_op(struct cpu_user_regs *regs);
+void do_memory_fast_op(struct cpu_user_regs *regs);
+void do_grant_table_fast_op(struct cpu_user_regs *regs);
+void do_sched_fast_op(struct cpu_user_regs *regs);
+void do_xen_version_fast_op(struct cpu_user_regs *regs);
+
+#endif /* XEN_FASTABI_H */
\ No newline at end of file
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RFC=20PATCH=200/9]=20x86/hvm:=20New=20Xen=20HVM=20ABI=20proposal=20("HVMv2"=20part=201)?=
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Hello, this series introduce a new hypercall ABI proposal (x86 only for now).

The current Xen ABI has some shortcommings :

First, the hypercall parameters are usually pointers that point to a structure
in guest memory, this pointer is usually a virtual address. 
It causes various issues as :
 - you need to define a format for these structures which is currently C
   structures, but it complicates support with non LP64 platforms (e.g Windows)
   or other programming languages (e.g Rust, where solutions are hard to come with)
 - the translation from virtual address to machine physical address is very expensive
   as you need to translate the GVA to GPA, and then GPA to HPA each time you want to
   access a virtual address
 - such virtual addresses are not readable under confidential computing guests which
   makes such new ABI required.

Another issue is that all possible Xen hypercalls are exposed through this
single interface, it makes hardening the hypervisor more complicated as you
need to permission check on a per-hypercall basis (e.g through XSM) instead
of having a minimal strict safe-for-guest-use set of operations.

The current ABI allows the guest to modify its physmap; this is notably used for
mapping the shared info, grant table and ballooning. While we could make that work
for confidential guests. It comes with its own set of problems, and in order to
simplify the memory management, this series come with a proposal for mapping these
specific pages in advance and telling the guest the location. That helps reducing
the scope of this new ABI. Ballooning implementation hasn't been fully considered yet.

This series propose a new hypercall interface designed for use by guests kernels
with high performance (low hypercall overhead) and confidential computing environments
(notably AMD SEV) compatibility in mind. It currently only supports x86 long mode
(64-bits) due to specific register requirements.

It doesn't aim to entirely replace the current ABI, but to propose a alternative
one that could be used by guests as a fast-path ABI or for confidential computing
guests.

This new ABI maps into current many operations (with some limitations), a tool is
provided to generate C stubs using the yaml specification.
These C stubs reuse the existing hypercall structures to ease adding support
for this ABI in guests.

You can find some example generated headers in Linux SEV WIP branch [1].

[1] https://github.com/xcp-ng/linux/tree/xen-sev-6.14/include/xen/interface/fastabi

Teddy Astie (9):
  x86/hvm: Use direct structures instead of guest handles
  common: Isolate XENVER_get_features into a separate function
  common/grant_table: Use direct structures instead of guest handles
  hvm: Introduce "fixed memory layout" feature
  docs/x86: Introduce FastABI
  sched: Extract do_poll main logic into vcpu_poll
  x86/hvm: Introduce FastABI implementation
  hvm: Introduce XEN_HVM_MEMMAP_TYPE_HOTPLUG_ZONE
  tools: Introduce abi-tool

 docs/guest-guide/x86/fastabi.pandoc           |  50 +++++
 .../x86/fixed-memory-layout.pandoc            |  24 ++
 docs/guest-guide/x86/index.rst                |   2 +
 tools/include/xen-tools/common-macros.h       |   4 +
 tools/libs/guest/xg_dom_x86.c                 |  84 +++++++
 tools/libs/light/libxl_create.c               |   1 +
 tools/libs/light/libxl_types.idl              |   1 +
 tools/libs/light/libxl_x86.c                  |  71 ++++++
 tools/xl/xl_parse.c                           |   1 +
 xen/abi/event_channel.yml                     | 130 +++++++++++
 xen/abi/grant_table.yml                       |  46 ++++
 xen/abi/hvm.yml                               |  50 +++++
 xen/abi/memory.yml                            |  11 +
 xen/abi/sched.yml                             |  48 ++++
 xen/abi/vcpu.yml                              | 139 ++++++++++++
 xen/abi/version.yml                           |  15 ++
 xen/arch/x86/cpuid.c                          |   3 +
 xen/arch/x86/domain.c                         |  71 ++++++
 xen/arch/x86/hvm/hvm.c                        | 205 +++++++++++++-----
 xen/arch/x86/hvm/hypercall.c                  |  22 ++
 xen/arch/x86/include/asm/fastabi.h            |  17 ++
 xen/common/Kconfig                            |   6 +
 xen/common/Makefile                           |   1 +
 xen/common/domain.c                           | 179 +++++++++++++++
 xen/common/event_channel.c                    | 199 +++++++++++++++++
 xen/common/fastabi.c                          |  49 +++++
 xen/common/grant_table.c                      | 112 +++++++---
 xen/common/kernel.c                           | 117 ++++++----
 xen/common/memory.c                           | 110 ++++++++++
 xen/common/sched/core.c                       | 149 +++++++++++--
 xen/include/public/arch-x86/cpuid.h           |   4 +
 xen/include/public/arch-x86/hvm/start_info.h  |   8 +
 xen/include/public/event_channel.h            |   7 +
 xen/include/public/fastabi.h                  |  20 ++
 xen/include/xen/fastabi.h                     |  21 ++
 xen/tools/abi-tool/.gitignore                 |   1 +
 xen/tools/abi-tool/Cargo.lock                 | 145 +++++++++++++
 xen/tools/abi-tool/Cargo.toml                 |  11 +
 xen/tools/abi-tool/src/abi.rs                 |  23 ++
 xen/tools/abi-tool/src/c_lang.rs              | 173 +++++++++++++++
 xen/tools/abi-tool/src/main.rs                |  17 ++
 xen/tools/abi-tool/src/spec.rs                |  61 ++++++
 42 files changed, 2265 insertions(+), 143 deletions(-)
 create mode 100644 docs/guest-guide/x86/fastabi.pandoc
 create mode 100644 docs/guest-guide/x86/fixed-memory-layout.pandoc
 create mode 100644 xen/abi/event_channel.yml
 create mode 100644 xen/abi/grant_table.yml
 create mode 100644 xen/abi/hvm.yml
 create mode 100644 xen/abi/memory.yml
 create mode 100644 xen/abi/sched.yml
 create mode 100644 xen/abi/vcpu.yml
 create mode 100644 xen/abi/version.yml
 create mode 100644 xen/arch/x86/include/asm/fastabi.h
 create mode 100644 xen/common/fastabi.c
 create mode 100644 xen/include/public/fastabi.h
 create mode 100644 xen/include/xen/fastabi.h
 create mode 100644 xen/tools/abi-tool/.gitignore
 create mode 100644 xen/tools/abi-tool/Cargo.lock
 create mode 100644 xen/tools/abi-tool/Cargo.toml
 create mode 100644 xen/tools/abi-tool/src/abi.rs
 create mode 100644 xen/tools/abi-tool/src/c_lang.rs
 create mode 100644 xen/tools/abi-tool/src/main.rs
 create mode 100644 xen/tools/abi-tool/src/spec.rs

-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[PATCH=208/9]=20RFC:=20hvm:=20Introduce=20XEN=5FHVM=5FMEMMAP=5FTYPE=5FHOTPLUG=5FZONE?=
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Allow specifying in memory map a region which can be hotplugged.

This will be used by a future memory hotplug feature.

Signed-off-by: Teddy Astie 
---
 xen/include/public/arch-x86/hvm/start_info.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/include/public/arch-x86/hvm/start_info.h b/xen/include/public/arch-x86/hvm/start_info.h
index 0b3dfe91af..bdae8371d6 100644
--- a/xen/include/public/arch-x86/hvm/start_info.h
+++ b/xen/include/public/arch-x86/hvm/start_info.h
@@ -105,6 +105,7 @@
 #define XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS 0xF0000003 /* Grant table status page (v2) */
 #define XEN_HVM_MEMMAP_TYPE_FOREIGN_REG   0xF0000004 /* Suitable region for grant mappings */
                                                      /* and foreign mappings */
+#define XEN_HVM_MEMMAP_TYPE_HOTPLUG_ZONE  0xF0000005 /* Memory hotpluggable zone */
 
 /*
  * C representation of the x86/HVM start info layout.
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RFC=20PATCH=206/9]=20sched:=20Extract=20do=5Fpoll=20main=20logic=20into=20vcpu=5Fpoll?=
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do_poll takes sched_poll* as parameter, but that's actually in guest memory
(so it's more a guest handle). Split its copy from/to guest logic from
the main logic, so that we have a separate vcpu_poll which takes the sched_poll
parameters directly.

Signed-off-by: Teddy Astie 
---
 xen/common/sched/core.c | 40 +++++++++++++++++++++-------------------
 1 file changed, 21 insertions(+), 19 deletions(-)

diff --git a/xen/common/sched/core.c b/xen/common/sched/core.c
index 13fdf57e57..b2c784c60e 100644
--- a/xen/common/sched/core.c
+++ b/xen/common/sched/core.c
@@ -1437,21 +1437,13 @@ static void vcpu_block_enable_events(void)
     vcpu_block();
 }
 
-static long do_poll(const struct sched_poll *sched_poll)
+static long vcpu_poll(unsigned int nr_ports, uint64_t timeout, evtchn_port_t *ports)
 {
     struct vcpu   *v = current;
     struct domain *d = v->domain;
-    evtchn_port_t  port = 0;
     long           rc;
     unsigned int   i;
 
-    /* Fairly arbitrary limit. */
-    if ( sched_poll->nr_ports > 128 )
-        return -EINVAL;
-
-    if ( !guest_handle_okay(sched_poll->ports, sched_poll->nr_ports) )
-        return -EFAULT;
-
     set_bit(_VPF_blocked, &v->pause_flags);
     v->poll_evtchn = -1;
     set_bit(v->vcpu_id, d->poll_mask);
@@ -1478,13 +1470,9 @@ static long do_poll(const struct sched_poll *sched_poll)
     if ( local_events_need_delivery() )
         goto out;
 
-    for ( i = 0; i < sched_poll->nr_ports; i++ )
+    for ( i = 0; i < nr_ports; i++ )
     {
-        rc = -EFAULT;
-        if ( __copy_from_guest_offset(&port, sched_poll->ports, i, 1) )
-            goto out;
-
-        rc = evtchn_port_poll(d, port);
+        rc = evtchn_port_poll(d, ports[i]);
         if ( rc )
         {
             if ( rc > 0 )
@@ -1493,11 +1481,11 @@ static long do_poll(const struct sched_poll *sched_poll)
         }
     }
 
-    if ( sched_poll->nr_ports == 1 )
-        v->poll_evtchn = port;
+    if ( nr_ports == 1 )
+        v->poll_evtchn = ports[0];
 
-    if ( sched_poll->timeout != 0 )
-        set_timer(&v->poll_timer, sched_poll->timeout);
+    if ( timeout != 0 )
+        set_timer(&v->poll_timer, timeout);
 
     TRACE_TIME(TRC_SCHED_BLOCK, d->domain_id, v->vcpu_id);
     raise_softirq(SCHEDULE_SOFTIRQ);
@@ -1511,6 +1499,20 @@ static long do_poll(const struct sched_poll *sched_poll)
     return rc;
 }
 
+static long do_poll(struct sched_poll *sched_poll)
+{
+    evtchn_port_t ports[128];
+
+    /* Fairly arbitrary limit */
+    if ( sched_poll->nr_ports > 128 )
+        return -EINVAL;
+
+    if ( copy_from_guest(ports, sched_poll->ports, sched_poll->nr_ports) )
+        return -EFAULT;
+
+    return vcpu_poll(sched_poll->nr_ports, sched_poll->timeout, ports);
+}
+
 /* Voluntarily yield the processor for this allocation. */
 long vcpu_yield(void)
 {
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RFC=20PATCH=208/9]=20hvm:=20Introduce=20XEN=5FHVM=5FMEMMAP=5FTYPE=5FHOTPLUG=5FZONE?=
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Allow specifying in memory map a region which can be hotplugged.

This will be used by a future memory hotplug feature.

Signed-off-by: Teddy Astie 
---
 xen/include/public/arch-x86/hvm/start_info.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/include/public/arch-x86/hvm/start_info.h b/xen/include/public/arch-x86/hvm/start_info.h
index 0b3dfe91af..bdae8371d6 100644
--- a/xen/include/public/arch-x86/hvm/start_info.h
+++ b/xen/include/public/arch-x86/hvm/start_info.h
@@ -105,6 +105,7 @@
 #define XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS 0xF0000003 /* Grant table status page (v2) */
 #define XEN_HVM_MEMMAP_TYPE_FOREIGN_REG   0xF0000004 /* Suitable region for grant mappings */
                                                      /* and foreign mappings */
+#define XEN_HVM_MEMMAP_TYPE_HOTPLUG_ZONE  0xF0000005 /* Memory hotpluggable zone */
 
 /*
  * C representation of the x86/HVM start info layout.
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RFC=20PATCH=204/9]=20hvm:=20Introduce=20"fixed=20memory=20layout"=20feature?=
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Currently, guests needs to explicitely map their shared info and
grant table through hypercalls. It has proved to be complicated
and had been traditionally placed in the Xen PCI Platform device
BAR, but has caused confusions regarding MTRR [1].

Introduce a optional feature to let the toolstack map these pages in
advance, and exposing their location through the memory map (i.e E820).

When this feature is active, guests are expected to not invalidate such
mappings (e.g by calling xen_remove_from_physmap); as they may be used
by the operating system or firmware (i.e OVMF).

Moreover, this feature is useful to allow having a working guest without
having to expose to it physmap manipulation.

[1] https://lore.kernel.org/xen-devel/20250610162930.89055-1-roger.pau@citrix.com/

Signed-off-by: Teddy Astie 
---
 .../x86/fixed-memory-layout.pandoc            | 24 ++++++
 docs/guest-guide/x86/index.rst                |  1 +
 tools/include/xen-tools/common-macros.h       |  4 +
 tools/libs/guest/xg_dom_x86.c                 | 84 +++++++++++++++++++
 tools/libs/light/libxl_create.c               |  1 +
 tools/libs/light/libxl_types.idl              |  1 +
 tools/libs/light/libxl_x86.c                  | 71 ++++++++++++++++
 tools/xl/xl_parse.c                           |  1 +
 xen/include/public/arch-x86/hvm/start_info.h  |  7 ++
 9 files changed, 194 insertions(+)
 create mode 100644 docs/guest-guide/x86/fixed-memory-layout.pandoc

diff --git a/docs/guest-guide/x86/fixed-memory-layout.pandoc b/docs/guest-guide/x86/fixed-memory-layout.pandoc
new file mode 100644
index 0000000000..b394dc1cff
--- /dev/null
+++ b/docs/guest-guide/x86/fixed-memory-layout.pandoc
@@ -0,0 +1,24 @@
+# Fixed memory layout
+
+When creating a guest with "fixed_mem_layout", the guest has additional special
+pages mapped in advance. These mappings may be required in some cases due to FastABI
+not providing the ability for the guest to modify its physical memory layout (which is
+usually used to map the shared info page or the grant table).
+
+The guest is informed of such mappings and their location through the memory map using
+Xen specific memory map types (in the OEM range of ACPI specification).
+
+It's expected that these mappings stay stable, therefore, the guest shouldn't try to
+modify such mappings as it may be actively used by guest firmware or operating system.
+
+    /* Xen-specific types (OEM-specific range of the ACPI spec) */
+    #define XEN_HVM_MEMMAP_TYPE_SHARED_INFO   0xF0000001 /* Shared info page */
+    #define XEN_HVM_MEMMAP_TYPE_GRANT_TABLE   0xF0000002 /* Grant table pages */
+    #define XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS 0xF0000003 /* Grant table status page (v2) */
+    #define XEN_HVM_MEMMAP_TYPE_FOREIGN_REG   0xF0000004 /* Suitable region for grant mappings */
+                                                         /* and foreign mappings */
+
+These mappings are likely to be placed outside the 4G range.
+
+XEN_HVM_MEMMAP_TYPE_FOREIGN_REG is a special region which doesn't contain any mapping,
+but is safe to use for placing grant and foreign mappings.
diff --git a/docs/guest-guide/x86/index.rst b/docs/guest-guide/x86/index.rst
index 502968490d..6927271e53 100644
--- a/docs/guest-guide/x86/index.rst
+++ b/docs/guest-guide/x86/index.rst
@@ -7,3 +7,4 @@ x86
    :maxdepth: 2
 
    hypercall-abi
+   fixed-memory-layout
diff --git a/tools/include/xen-tools/common-macros.h b/tools/include/xen-tools/common-macros.h
index 0088208c2e..8b286b3da5 100644
--- a/tools/include/xen-tools/common-macros.h
+++ b/tools/include/xen-tools/common-macros.h
@@ -72,6 +72,10 @@
 #define ROUNDUP(_x,_w) (((unsigned long)(_x)+(1UL<<(_w))-1) & ~((1UL<<(_w))-1))
 #endif
 
+#ifndef DIV_ROUNDUP
+#define DIV_ROUNDUP(n, d) (((n) + (d) - 1) / (d))
+#endif
+
 #define MASK_EXTR(v, m) (((v) & (m)) / ((m) & -(m)))
 #define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m))
 
diff --git a/tools/libs/guest/xg_dom_x86.c b/tools/libs/guest/xg_dom_x86.c
index cba01384ae..ab1c5063a4 100644
--- a/tools/libs/guest/xg_dom_x86.c
+++ b/tools/libs/guest/xg_dom_x86.c
@@ -624,6 +624,82 @@ static void build_hvm_info(void *hvm_info_page, struct xc_dom_image *dom)
     hvm_info->checksum = -sum;
 }
 
+/* Prepare special (shared_info, grant table, ...) regions marked in E820. */
+static int prepare_fixed_special_regions(xc_interface *xch, struct xc_dom_image *dom)
+{
+    int rc = 0; unsigned int i;
+    uint32_t domid = dom->guest_domid;
+    gnttab_query_size_t gnttab_query;
+    size_t gnttab_frame_count, gnttab_status_frame_count;
+    
+    gnttab_query.dom = domid;
+    rc = xc_gnttab_query_size(xch, &gnttab_query);
+
+    if ( rc != 0 || gnttab_query.status != GNTST_okay )
+    {
+        DOMPRINTF("Unable to query grant table size.");
+        return rc;
+    }
+
+    gnttab_frame_count = gnttab_query.max_nr_frames;
+    gnttab_status_frame_count = DIV_ROUNDUP(
+        gnttab_frame_count * (XC_DOM_PAGE_SIZE(dom) / sizeof(grant_entry_v2_t)),
+        XC_DOM_PAGE_SIZE(dom) / sizeof(grant_status_t));
+
+    for ( i = 0; i < dom->e820_entries; i++ )
+    {
+        struct e820entry entry = dom->e820[i];
+        rc = 0;
+
+        switch ( entry.type ) {
+        case XEN_HVM_MEMMAP_TYPE_SHARED_INFO:
+            rc = xc_domain_add_to_physmap(xch, domid, XENMAPSPACE_shared_info,
+                                          0, entry.addr >> PAGE_SHIFT);
+            break;
+        case XEN_HVM_MEMMAP_TYPE_GRANT_TABLE:
+            if ( gnttab_frame_count != entry.size >> PAGE_SHIFT )
+            {
+                DOMPRINTF("Invalid grant table memmap region size");
+                return -EINVAL;
+            }
+
+            for ( i = 0; i < gnttab_frame_count; i++ )
+            {
+                rc = xc_domain_add_to_physmap(xch, domid, XENMAPSPACE_grant_table, i,
+                                              (entry.addr >> PAGE_SHIFT) + i);
+                
+                if ( rc !=  0 )
+                    break;
+            }
+            break;
+        case XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS:
+        {
+            if ( gnttab_status_frame_count != entry.size >> PAGE_SHIFT )
+            {
+                DOMPRINTF("Invalid grant table status memmap region size");
+                return -EINVAL;
+            }
+
+            for ( i = 0; i < gnttab_status_frame_count; i++ )
+            {
+                rc = xc_domain_add_to_physmap(xch, domid, XENMAPSPACE_grant_table,
+                                              i | XENMAPIDX_grant_table_status,
+                                              (entry.addr >> PAGE_SHIFT) + i);
+                
+                if ( rc !=  0 )
+                    break;
+            }
+            break;
+        }
+        }
+
+        if ( rc != 0 )
+            break;
+    }
+
+    return rc;
+}
+
 static int alloc_magic_pages_hvm(struct xc_dom_image *dom)
 {
     unsigned long i;
@@ -718,6 +794,14 @@ static int alloc_magic_pages_hvm(struct xc_dom_image *dom)
         goto out;
     }
 
+    rc = prepare_fixed_special_regions(xch, dom);
+
+    if ( rc != 0 )
+    {
+        DOMPRINTF("Unable to prepare fixed special regions");
+        goto out;
+    }
+
     /*
      * Identity-map page table is required for running with CR0.PG=0 when
      * using Intel EPT. Create a 32-bit non-PAE page directory of superpages.
diff --git a/tools/libs/light/libxl_create.c b/tools/libs/light/libxl_create.c
index 8a85fba1cf..5e23e122fc 100644
--- a/tools/libs/light/libxl_create.c
+++ b/tools/libs/light/libxl_create.c
@@ -2363,6 +2363,7 @@ int libxl_domain_create_restore(libxl_ctx *ctx, libxl_domain_config *d_config,
      * configuration.
      */
     libxl_defbool_setdefault(&d_config->b_info.arch_x86.msr_relaxed, true);
+    libxl_defbool_setdefault(&d_config->b_info.arch_x86.fixed_mem_layout, false);
     libxl_defbool_setdefault(&d_config->b_info.u.hvm.pirq, true);
 
     return do_domain_create(ctx, d_config, domid, restore_fd, send_back_fd,
diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl
index a3a79d12b2..74edfdebc1 100644
--- a/tools/libs/light/libxl_types.idl
+++ b/tools/libs/light/libxl_types.idl
@@ -727,6 +727,7 @@ libxl_domain_build_info = Struct("domain_build_info",[
                                ("nr_spis", uint32, {'init_val': 'LIBXL_NR_SPIS_DEFAULT'}),
                               ])),
     ("arch_x86", Struct(None, [("msr_relaxed", libxl_defbool),
+                               ("fixed_mem_layout", libxl_defbool),
                               ])),
     # Alternate p2m is not bound to any architecture or guest type, as it is
     # supported by x86 HVM and ARM support is planned.
diff --git a/tools/libs/light/libxl_x86.c b/tools/libs/light/libxl_x86.c
index 60d4e8661c..de19f722ab 100644
--- a/tools/libs/light/libxl_x86.c
+++ b/tools/libs/light/libxl_x86.c
@@ -1,6 +1,7 @@
 #include "libxl_internal.h"
 #include "libxl_arch.h"
 #include 
+#include 
 
 int libxl__arch_domain_prepare_config(libxl__gc *gc,
                                       libxl_domain_config *d_config,
@@ -50,6 +51,10 @@ static const char *e820_names(int type)
         case E820_ACPI: return "ACPI";
         case E820_NVS: return "ACPI NVS";
         case E820_UNUSABLE: return "Unusable";
+        case XEN_HVM_MEMMAP_TYPE_SHARED_INFO: return "HVM Shared Info";
+        case XEN_HVM_MEMMAP_TYPE_GRANT_TABLE: return "HVM Grant Table";
+        case XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS: return "HVM Grant Status";
+        case XEN_HVM_MEMMAP_TYPE_FOREIGN_REG: return "HVM Foreign mapping region";
         default: break;
     }
     return "Unknown";
@@ -686,10 +691,31 @@ static int domain_construct_memmap(libxl__gc *gc,
     /* We always own at least one lowmem entry. */
     unsigned int e820_entries = 1;
     struct e820entry *e820 = NULL;
+    uint64_t highmem_start = ((uint64_t)1 << 32);
     uint64_t highmem_size =
                     dom->highmem_end ? dom->highmem_end - (1ull << 32) : 0;
     uint32_t lowmem_start = dom->device_model ? GUEST_LOW_MEM_START_DEFAULT : 0;
     unsigned page_size = XC_DOM_PAGE_SIZE(dom);
+    /* Special region starts at the first 1G boundary after the highmem */
+    uint64_t special_region_start =
+        (highmem_start + highmem_size + GB(1) - 1) & ~(GB(1) - 1);
+    uint64_t special_region_offset = special_region_start;
+    size_t gnttab_frame_count, gnttab_status_frame_count;
+    gnttab_query_size_t gnttab_query;
+
+    gnttab_query.dom = domid;
+    rc = xc_gnttab_query_size(dom->xch, &gnttab_query);
+
+    if (rc != 0 || gnttab_query.status != GNTST_okay)
+    {
+        gnttab_frame_count = 0;
+        gnttab_status_frame_count = 0;
+    }
+
+    gnttab_frame_count = gnttab_query.max_nr_frames;
+    gnttab_status_frame_count = DIV_ROUNDUP(
+        gnttab_frame_count * (page_size / sizeof(grant_entry_v2_t)),
+        page_size / sizeof(grant_status_t));
 
     /* Add all rdm entries. */
     for (i = 0; i < d_config->num_rdms; i++)
@@ -703,6 +729,16 @@ static int domain_construct_memmap(libxl__gc *gc,
     /* If we should have a highmem range. */
     if (highmem_size)
         e820_entries++;
+    
+    if (libxl_defbool_val(d_config->b_info.arch_x86.fixed_mem_layout))
+    {
+        e820_entries++; /* XEN_HVM_MEMMAP_TYPE_SHARED_INFO */
+        if ( gnttab_frame_count )
+            e820_entries++; /* XEN_HVM_MEMMAP_TYPE_GRANT_TABLE */
+        if (d_config->b_info.max_grant_version >= 2 && gnttab_status_frame_count)
+            e820_entries++; /* XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS status */
+        e820_entries++; /* XEN_HVM_MEMMAP_TYPE_FOREIGN_REG */
+    }
 
     for (i = 0; i < MAX_ACPI_MODULES; i++)
         if (dom->acpi_modules[i].length)
@@ -769,6 +805,40 @@ static int domain_construct_memmap(libxl__gc *gc,
         e820[nr].type = E820_RAM;
     }
 
+    /* Special regions */
+    if (libxl_defbool_val(d_config->b_info.arch_x86.fixed_mem_layout))
+    {
+        e820[nr].type = XEN_HVM_MEMMAP_TYPE_SHARED_INFO;
+        e820[nr].addr = special_region_offset;
+        e820[nr].size = page_size;
+        special_region_offset += e820[nr].size;
+        nr++;
+
+        if ( gnttab_frame_count )
+        {
+            e820[nr].type = XEN_HVM_MEMMAP_TYPE_GRANT_TABLE;
+            e820[nr].addr = special_region_offset;
+            e820[nr].size = gnttab_frame_count * page_size;
+            special_region_offset += e820[nr].size;
+            nr++;
+        }
+
+        if (d_config->b_info.max_grant_version >= 2 && gnttab_status_frame_count)
+        {
+            e820[nr].type = XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS;
+            e820[nr].addr = special_region_offset;
+            e820[nr].size = gnttab_status_frame_count * page_size;
+            special_region_offset += e820[nr].size;
+            nr++;
+        }
+
+        e820[nr].type = XEN_HVM_MEMMAP_TYPE_FOREIGN_REG;
+        e820[nr].addr = special_region_offset;
+        e820[nr].size = MB(512);
+        special_region_offset += e820[nr].size;
+        nr++;
+    }
+
     if (xc_domain_set_memory_map(CTX->xch, domid, e820, e820_entries) != 0) {
         rc = ERROR_FAIL;
         goto out;
@@ -819,6 +889,7 @@ int libxl__arch_domain_build_info_setdefault(libxl__gc *gc,
     libxl_defbool_setdefault(&b_info->acpi, true);
     libxl_defbool_setdefault(&b_info->arch_x86.msr_relaxed, false);
     libxl_defbool_setdefault(&b_info->trap_unmapped_accesses, false);
+    libxl_defbool_setdefault(&b_info->arch_x86.fixed_mem_layout, false);
 
     if (b_info->type == LIBXL_DOMAIN_TYPE_HVM) {
         /*
diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
index 7e11c62ba0..a74cc577e9 100644
--- a/tools/xl/xl_parse.c
+++ b/tools/xl/xl_parse.c
@@ -2992,6 +2992,7 @@ skip_usbdev:
                     "WARNING: msr_relaxed will be removed in future versions.\n"
                     "If it fixes an issue you are having please report to "
                     "xen-devel@lists.xenproject.org.\n");
+    xlu_cfg_get_defbool(config, "fixed_mem_layout", &b_info->arch_x86.fixed_mem_layout, 0);
 
     xlu_cfg_get_defbool(config, "vpmu", &b_info->vpmu, 0);
 
diff --git a/xen/include/public/arch-x86/hvm/start_info.h b/xen/include/public/arch-x86/hvm/start_info.h
index e33557c0b4..0b3dfe91af 100644
--- a/xen/include/public/arch-x86/hvm/start_info.h
+++ b/xen/include/public/arch-x86/hvm/start_info.h
@@ -99,6 +99,13 @@
 #define XEN_HVM_MEMMAP_TYPE_DISABLED  6
 #define XEN_HVM_MEMMAP_TYPE_PMEM      7
 
+/* Xen-specific types (OEM-specific range of the ACPI spec) */
+#define XEN_HVM_MEMMAP_TYPE_SHARED_INFO   0xF0000001 /* Shared info page */
+#define XEN_HVM_MEMMAP_TYPE_GRANT_TABLE   0xF0000002 /* Grant table pages */
+#define XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS 0xF0000003 /* Grant table status page (v2) */
+#define XEN_HVM_MEMMAP_TYPE_FOREIGN_REG   0xF0000004 /* Suitable region for grant mappings */
+                                                     /* and foreign mappings */
+
 /*
  * C representation of the x86/HVM start info layout.
  *
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RFC=20PATCH=203/9]=20common/grant=5Ftable:=20Use=20direct=20structures=20instead=20of=20guest=20handles?=
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Make these functions work with hypervisor-owned pointer rather than
guest handles, so the function parameters don't have to live in guest memory.

No functional changes.

Signed-off-by: Teddy Astie 
---
 xen/common/grant_table.c | 68 +++++++++++++++++++++++-----------------
 1 file changed, 39 insertions(+), 29 deletions(-)

diff --git a/xen/common/grant_table.c b/xen/common/grant_table.c
index cf131c43a1..3c3bbca2fc 100644
--- a/xen/common/grant_table.c
+++ b/xen/common/grant_table.c
@@ -3164,29 +3164,24 @@ static long gnttab_copy(
     return rc;
 }
 
-static long
-gnttab_set_version(XEN_GUEST_HANDLE_PARAM(gnttab_set_version_t) uop)
+static long gnttab_set_version(gnttab_set_version_t *op)
 {
-    gnttab_set_version_t op;
     struct domain *currd = current->domain;
     struct grant_table *gt = currd->grant_table;
     grant_entry_v1_t reserved_entries[GNTTAB_NR_RESERVED_ENTRIES];
     int res;
     unsigned int i, nr_ents;
 
-    if ( copy_from_guest(&op, uop, 1) )
-        return -EFAULT;
-
     res = -EINVAL;
-    if ( op.version != 1 && op.version != 2 )
+    if ( op->version != 1 && op->version != 2 )
         goto out;
 
     res = -ENOSYS;
-    if ( op.version == 2 && gt->max_version == 1 )
+    if ( op->version == 2 && gt->max_version == 1 )
         goto out; /* Behave as before set_version was introduced. */
 
     res = 0;
-    if ( gt->gt_version == op.version )
+    if ( gt->gt_version == op->version )
         goto out;
 
     grant_write_lock(gt);
@@ -3203,7 +3198,7 @@ gnttab_set_version(XEN_GUEST_HANDLE_PARAM(gnttab_set_version_t) uop)
         {
             gdprintk(XENLOG_WARNING,
                      "tried to change grant table version from %u to %u, but some grant entries still in use\n",
-                     gt->gt_version, op.version);
+                     gt->gt_version, op->version);
             res = -EBUSY;
             goto out_unlock;
         }
@@ -3268,7 +3263,7 @@ gnttab_set_version(XEN_GUEST_HANDLE_PARAM(gnttab_set_version_t) uop)
         break;
     }
 
-    if ( op.version < 2 && gt->gt_version == 2 &&
+    if ( op->version < 2 && gt->gt_version == 2 &&
          (res = gnttab_unpopulate_status_frames(currd, gt)) != 0 )
         goto out_unlock;
 
@@ -3279,7 +3274,7 @@ gnttab_set_version(XEN_GUEST_HANDLE_PARAM(gnttab_set_version_t) uop)
     /* Restore the first 8 entries (toolstack reserved grants). */
     if ( gt->gt_version )
     {
-        switch ( op.version )
+        switch ( op->version )
         {
         case 1:
             memcpy(&shared_entry_v1(gt, 0), reserved_entries, sizeof(reserved_entries));
@@ -3300,16 +3295,14 @@ gnttab_set_version(XEN_GUEST_HANDLE_PARAM(gnttab_set_version_t) uop)
         }
     }
 
-    gt->gt_version = op.version;
+    gt->gt_version = op->version;
 
  out_unlock:
     grant_write_unlock(gt);
 
  out:
-    op.version = gt->gt_version;
+    op->version = gt->gt_version;
 
-    if ( __copy_to_guest(uop, &op, 1) )
-        res = -EFAULT;
 
     return res;
 }
@@ -3387,17 +3380,12 @@ gnttab_get_status_frames(XEN_GUEST_HANDLE_PARAM(gnttab_get_status_frames_t) uop,
     return 0;
 }
 
-static long
-gnttab_get_version(XEN_GUEST_HANDLE_PARAM(gnttab_get_version_t) uop)
+static long gnttab_get_version(gnttab_get_version_t *op)
 {
-    gnttab_get_version_t op;
     struct domain *d;
     int rc;
 
-    if ( copy_from_guest(&op, uop, 1) )
-        return -EFAULT;
-
-    d = rcu_lock_domain_by_any_id(op.dom);
+    d = rcu_lock_domain_by_any_id(op->dom);
     if ( d == NULL )
         return -ESRCH;
 
@@ -3408,13 +3396,10 @@ gnttab_get_version(XEN_GUEST_HANDLE_PARAM(gnttab_get_version_t) uop)
         return rc;
     }
 
-    op.version = d->grant_table->gt_version;
+    op->version = d->grant_table->gt_version;
 
     rcu_unlock_domain(d);
 
-    if ( __copy_field_to_guest(uop, &op, version) )
-        return -EFAULT;
-
     return 0;
 }
 
@@ -3749,8 +3734,20 @@ long do_grant_table_op(
         break;
 
     case GNTTABOP_set_version:
-        rc = gnttab_set_version(guest_handle_cast(uop, gnttab_set_version_t));
+    {
+        gnttab_set_version_t op;
+        if ( copy_from_guest(&op, uop, 1) )
+        {
+            rc = -EFAULT;
+            break;
+        }
+
+        rc = gnttab_set_version(&op);
+
+        if ( copy_to_guest(uop, &op, 1) )
+            rc = -EFAULT;
         break;
+    }
 
     case GNTTABOP_get_status_frames:
         rc = gnttab_get_status_frames(
@@ -3758,8 +3755,21 @@ long do_grant_table_op(
         break;
 
     case GNTTABOP_get_version:
-        rc = gnttab_get_version(guest_handle_cast(uop, gnttab_get_version_t));
+    {
+        gnttab_get_version_t op;
+
+        if ( copy_from_guest(&op, uop, 1) )
+        {
+            rc = -EFAULT;
+            break;
+        }
+
+        rc = gnttab_get_version(&op);
+
+        if ( copy_to_guest(uop, &op, 1) )
+            rc = -EFAULT;
         break;
+    }
 
     case GNTTABOP_swap_grant_ref:
     {
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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Make do_xen_version more readable by moving the main XENVER_get_features
into a separate function.

No functional changes intended.

Signed-off-by: Teddy Astie 
---
 xen/common/kernel.c | 84 +++++++++++++++++++++++++--------------------
 1 file changed, 46 insertions(+), 38 deletions(-)

diff --git a/xen/common/kernel.c b/xen/common/kernel.c
index 5be668ba85..eff6db6c8f 100644
--- a/xen/common/kernel.c
+++ b/xen/common/kernel.c
@@ -569,6 +569,50 @@ static long xenver_varbuf_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
     return sz;
 }
 
+static long xenver_get_features(struct domain *d, uint32_t submap_idx, uint32_t *submap)
+{
+    switch ( submap_idx )
+    {
+    case 0:
+        *submap = (1U << XENFEAT_memory_op_vnode_supported) |
+#ifdef CONFIG_X86
+                  (1U << XENFEAT_vcpu_time_phys_area) |
+#endif
+                  (1U << XENFEAT_runstate_phys_area);
+        if ( VM_ASSIST(d, pae_extended_cr3) )
+            *submap |= (1U << XENFEAT_pae_pgdir_above_4gb);
+        if ( paging_mode_translate(d) )
+            *submap |=
+                (1U << XENFEAT_writable_page_tables) |
+                (1U << XENFEAT_auto_translated_physmap);
+        if ( is_hardware_domain(d) )
+            *submap |= 1U << XENFEAT_dom0;
+#ifdef CONFIG_ARM
+        *submap |= (1U << XENFEAT_ARM_SMCCC_supported);
+#endif
+#ifdef CONFIG_X86
+        if ( is_pv_domain(d) )
+            *submap |= (1U << XENFEAT_mmu_pt_update_preserve_ad) |
+                      (1U << XENFEAT_highmem_assist) |
+                      (1U << XENFEAT_gnttab_map_avail_bits);
+        else
+            *submap |= (1U << XENFEAT_hvm_safe_pvclock) |
+                       (1U << XENFEAT_hvm_callback_vector) |
+                       (has_pirq(d) ? (1U << XENFEAT_hvm_pirqs) : 0);
+        *submap |= (1U << XENFEAT_dm_msix_all_writes);
+#endif
+        if ( !paging_mode_translate(d) || is_domain_direct_mapped(d) )
+            *submap |= (1U << XENFEAT_direct_mapped);
+        else
+            *submap |= (1U << XENFEAT_not_direct_mapped);
+        break;
+    default:
+        return -EINVAL;
+    }
+
+    return 0;
+}
+
 long do_xen_version(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
 {
     bool deny = xsm_xen_version(XSM_OTHER, cmd);
@@ -675,45 +719,9 @@ long do_xen_version(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
         if ( copy_from_guest(&fi, arg, 1) )
             return -EFAULT;
 
-        switch ( fi.submap_idx )
-        {
-        case 0:
-            fi.submap = (1U << XENFEAT_memory_op_vnode_supported) |
-#ifdef CONFIG_X86
-                        (1U << XENFEAT_vcpu_time_phys_area) |
-#endif
-                        (1U << XENFEAT_runstate_phys_area);
-            if ( VM_ASSIST(d, pae_extended_cr3) )
-                fi.submap |= (1U << XENFEAT_pae_pgdir_above_4gb);
-            if ( paging_mode_translate(d) )
-                fi.submap |=
-                    (1U << XENFEAT_writable_page_tables) |
-                    (1U << XENFEAT_auto_translated_physmap);
-            if ( is_hardware_domain(d) )
-                fi.submap |= 1U << XENFEAT_dom0;
-#ifdef CONFIG_ARM
-            fi.submap |= (1U << XENFEAT_ARM_SMCCC_supported);
-#endif
-#ifdef CONFIG_X86
-            if ( is_pv_domain(d) )
-                fi.submap |= (1U << XENFEAT_mmu_pt_update_preserve_ad) |
-                             (1U << XENFEAT_highmem_assist) |
-                             (1U << XENFEAT_gnttab_map_avail_bits);
-            else
-                fi.submap |= (1U << XENFEAT_hvm_safe_pvclock) |
-                             (1U << XENFEAT_hvm_callback_vector) |
-                             (has_pirq(d) ? (1U << XENFEAT_hvm_pirqs) : 0);
-            fi.submap |= (1U << XENFEAT_dm_msix_all_writes);
-#endif
-            if ( !paging_mode_translate(d) || is_domain_direct_mapped(d) )
-                fi.submap |= (1U << XENFEAT_direct_mapped);
-            else
-                fi.submap |= (1U << XENFEAT_not_direct_mapped);
-            break;
-        default:
+        if ( xenver_get_features(d, fi.submap_idx, &fi.submap) )
             return -EINVAL;
-        }
-
+            
         if ( __copy_to_guest(arg, &fi, 1) )
             return -EFAULT;
         return 0;
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RFC=20PATCH=205/9]=20docs/x86:=20Introduce=20FastABI?=
X-Mailer: git-send-email 2.50.1
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To: xen-devel@lists.xenproject.org
Cc: "Teddy Astie" , "Andrew Cooper" , "Anthony PERARD" , "Michal Orzel" , "Jan Beulich" , "Julien Grall" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Stefano Stabellini" 
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FastABI is a alternative ABI designed with performance and coco-enabled
guest in mind. It is register-oriented instead of refering to C structures
in the guest memory (through a virtual memory pointer).

It only focuses on kernel-side hypercalls, it doesn't aim to provide toolstack
operations.

Signed-off-by: Teddy Astie 
---
 docs/guest-guide/x86/fastabi.pandoc |  50 ++++++++++
 docs/guest-guide/x86/index.rst      |   1 +
 xen/abi/event_channel.yml           | 130 ++++++++++++++++++++++++++
 xen/abi/grant_table.yml             |  46 +++++++++
 xen/abi/hvm.yml                     |  50 ++++++++++
 xen/abi/memory.yml                  |  11 +++
 xen/abi/sched.yml                   |  48 ++++++++++
 xen/abi/vcpu.yml                    | 139 ++++++++++++++++++++++++++++
 xen/abi/version.yml                 |  15 +++
 xen/include/public/arch-x86/cpuid.h |   4 +
 10 files changed, 494 insertions(+)
 create mode 100644 docs/guest-guide/x86/fastabi.pandoc
 create mode 100644 xen/abi/event_channel.yml
 create mode 100644 xen/abi/grant_table.yml
 create mode 100644 xen/abi/hvm.yml
 create mode 100644 xen/abi/memory.yml
 create mode 100644 xen/abi/sched.yml
 create mode 100644 xen/abi/vcpu.yml
 create mode 100644 xen/abi/version.yml

diff --git a/docs/guest-guide/x86/fastabi.pandoc b/docs/guest-guide/x86/fastabi.pandoc
new file mode 100644
index 0000000000..8ff8609f37
--- /dev/null
+++ b/docs/guest-guide/x86/fastabi.pandoc
@@ -0,0 +1,50 @@
+# x86 FastABI
+
+## Introduction
+
+FastABI is a alternative hypercall ABI designed with performance and confidential
+computing enabled guests (AMD SEV, Intel TDX, ...) in mind. It provides a minimal
+subset of the traditional ABI that is sufficient for having a working guest.
+
+This hypercall interface is designed around using registers for passing hypercall
+parameters and outputs rather than using pointer to C structures, thus it avoids
+potentially complicated or expensive memory copies from/to the guest.
+
+This ABI currently only supports HVM/PVH and x86 long mode.
+
+Each hypercall operation interface is described in a parsable yaml file, which
+defines each hypercall suboperation inputs and outputs and eventual metadata for
+code generation (e.g C stubs).
+
+## Support
+
+This interface is only supported if XEN_HVM_CPUID_FASTABI is set.
+
+## Semantics
+
+8 registers can be used as either input or output.
+
+Each hypercall operation (or sub-operation) defines its own set of used input and
+output registers. There is no implicit clobbering of unused registers, i.e input
+registers are not allowed to be modified by the hypervisor unless it is explicitely
+also marked as a output (or cloberred register).
+
+- reg0: `rax`: IN: hypercall operation index, OUT: error code
+- reg1: `rdi`: (if operation has sub-operations) IN: hypercall sub-operation index
+- reg2: `rsi`
+- reg3: `r8`
+- reg4: `r9`
+- reg5: `r10`
+- reg6: `r11`
+- reg7: `r12`
+
+`reg0` input is reserved for hypercall index.
+In order to distinguish FastABI with traditional hypercalls or viridian hypercalls,
+reg0 input needs to be OR-ed with 0x40000000 (__HYPERVISOR_FASTABI_MASK).
+
+`reg0` output is reserved for standard hypercall return code (errno) or returned value.
+
+`reg1` input can be used for identifying a sub-operation. output is available for use.
+
+The hypercall uses the native hypercall instruction, which is `vmcall` on Intel platforms
+and `vmmcall` on AMD platforms.
\ No newline at end of file
diff --git a/docs/guest-guide/x86/index.rst b/docs/guest-guide/x86/index.rst
index 6927271e53..aaae42da5a 100644
--- a/docs/guest-guide/x86/index.rst
+++ b/docs/guest-guide/x86/index.rst
@@ -7,4 +7,5 @@ x86
    :maxdepth: 2
 
    hypercall-abi
+   fastabi
    fixed-memory-layout
diff --git a/xen/abi/event_channel.yml b/xen/abi/event_channel.yml
new file mode 100644
index 0000000000..44a769cdbb
--- /dev/null
+++ b/xen/abi/event_channel.yml
@@ -0,0 +1,130 @@
+name: event_channel
+hypercall_index: 32
+
+subops:
+  alloc_unbound:
+    index: 6
+    input:
+      dom: 2
+      remote_dom: 3
+    output:
+      port: 4
+    c_lang:
+      struct: evtchn_alloc_unbound
+
+  bind_interdomain:
+    index: 0
+    input:
+      remote_dom: 2
+      remote_port: 3
+    output:
+      local_port: 4
+    c_lang:
+      struct: evtchn_bind_interdomain
+
+  bind_virq:
+    index: 1
+    input:
+      virq: 2
+      vcpu: 3
+    output:
+      port: 4
+    c_lang:
+      struct: evtchn_bind_virq
+
+  bind_ipi:
+    index: 7
+    input:
+      vcpu: 2
+    output:
+      port: 4
+    c_lang:
+      struct: evtchn_bind_ipi
+
+  bind_pirq:
+    index: 2
+    input:
+      pirq: 2
+      flags: 3
+    output:
+      port: 4
+    c_lang:
+      struct: evtchn_bind_pirq
+  
+  close:
+    index: 3
+    input:
+      port: 2
+    c_lang:
+      struct: evtchn_close
+  
+  send:
+    index: 4
+    input:
+      port: 2
+    c_lang:
+      struct: evtchn_send
+
+  status:
+    index: 5
+    input:
+      dom: 2
+      port: 3
+    output:
+      status: 4
+      vcpu: 5
+      output1: 6
+      output2: 7
+    c_lang:
+      struct: evtchn_status
+      mapping:
+        output1: u._output1
+        output2: u._output2
+  
+  bind_vcpu:
+    index: 8
+    input:
+      vcpu: 2
+      port: 3
+    c_lang:
+      struct: evtchn_bind_vcpu
+  
+  unmask:
+    index: 9
+    input:
+      port: 2
+    c_lang:
+      struct: evtchn_unmask
+  
+  reset:
+    index: 10
+    input:
+      dom: 2
+    c_lang:
+      struct: evtchn_reset
+
+  init_control:
+    index: 11
+    input:
+      control_gfn: 2
+      offset: 3
+      vcpu: 4
+    output:
+      link_bits: 5
+    c_lang:
+      struct: evtchn_init_control
+  
+  expand_array:
+    index: 12
+    input:
+      array_gfn: 2
+    c_lang:
+      struct: evtchn_expand_array
+
+  set_priority:
+    index: 13
+    input:
+      port: 2
+      priority: 3
+    c_lang:
+      struct: evtchn_set_priority
diff --git a/xen/abi/grant_table.yml b/xen/abi/grant_table.yml
new file mode 100644
index 0000000000..bcedaa966b
--- /dev/null
+++ b/xen/abi/grant_table.yml
@@ -0,0 +1,46 @@
+name: grant_table
+hypercall_index: 20
+
+subops:
+  map_grant_ref:
+    index: 0
+    input:
+      dom: 2
+      host_addr: 3
+      flags: 4
+      ref: 5
+    output:
+      handle: 6
+      status: 7
+    c_lang:
+      struct: gnttab_map_grant_ref
+  
+  unmap_grant_ref:
+    index: 1
+    input:
+      host_addr: 3
+      handle: 6
+    c_lang:
+      struct: gnttab_unmap_grant_ref
+  
+  query_size:
+    index: 6
+    output:
+      nr_frames: 2
+      max_nr_frames: 3
+    c_lang:
+      struct: gnttab_query_size
+
+  set_version:
+    index: 8
+    input:
+      version: 2
+    c_lang:
+      struct: gnttab_set_version
+
+  get_version:
+    index: 10
+    output:
+      version: 2
+    c_lang:
+      struct: gnttab_get_version
diff --git a/xen/abi/hvm.yml b/xen/abi/hvm.yml
new file mode 100644
index 0000000000..20c2421bdf
--- /dev/null
+++ b/xen/abi/hvm.yml
@@ -0,0 +1,50 @@
+name: hvm
+hypercall_index: 34
+
+subops:
+  set_param:
+    index: 0
+    input:
+      domid: 2
+      index: 3
+      value: 4
+    c_lang:
+      struct: xen_hvm_param
+
+  get_param:
+    index: 1
+    input:
+      domid: 2
+      index: 3
+    output:
+      value: 4
+    c_lang:
+      struct: xen_hvm_param
+
+  flush_tlbs:
+    index: 5
+
+  get_time:
+    index: 10
+    output:
+      now: 2
+    c_lang:
+      struct: xen_hvm_get_time
+
+  get_mem_type:
+    index: 15
+    input:
+      domid: 2
+      pfn: 3
+    output:
+      mem_type: 4
+    c_lang:
+      struct: xen_hvm_get_mem_type
+
+  set_evtchn_upcall_vector:
+    index: 23
+    input:
+      vcpu: 2
+      vector: 3
+    c_lang:
+      struct: xen_hvm_evtchn_upcall_vector
diff --git a/xen/abi/memory.yml b/xen/abi/memory.yml
new file mode 100644
index 0000000000..8b51490f8a
--- /dev/null
+++ b/xen/abi/memory.yml
@@ -0,0 +1,11 @@
+name: memory
+hypercall_index: 12
+
+subops:
+  memory_map:
+    index: 9
+    input:
+      nr_entries: 2
+      buffer: 3
+    c_lang:
+      struct: xen_memory_map
diff --git a/xen/abi/sched.yml b/xen/abi/sched.yml
new file mode 100644
index 0000000000..1b1ef50c7a
--- /dev/null
+++ b/xen/abi/sched.yml
@@ -0,0 +1,48 @@
+name: sched
+hypercall_index: 29
+
+subops:
+  yield:
+    index: 0
+
+  block:
+    index: 1
+
+  shutdown:
+    index: 2
+    input:
+      reason: 2
+    c_lang:
+      struct: sched_shutdown
+
+  poll:
+    index: 3
+    input:
+      timeout: 2
+      port: 3
+    c_lang:
+      params:
+        timeout: uint64_t
+        port: evtchn_port_t
+
+  shutdown_code:
+    index: 5
+    input:
+      reason: 2
+    c_lang:
+      struct: sched_shutdown
+
+  watchdog:
+    index: 6
+    input:
+      id: 2
+      timeout: 3
+    c_lang:
+      struct: sched_watchdog
+
+  pin_override:
+    index: 7
+    input:
+      pcpu: 2
+    c_lang:
+      struct: sched_pin_override
diff --git a/xen/abi/vcpu.yml b/xen/abi/vcpu.yml
new file mode 100644
index 0000000000..0b4fe4ea1f
--- /dev/null
+++ b/xen/abi/vcpu.yml
@@ -0,0 +1,139 @@
+name: vcpu
+hypercall_index: 24
+
+subops:
+  initialise:
+    index: 0
+    input:
+      vcpuid: 2
+      context_gfn: 3
+    c_lang:
+      params:
+        vcpuid: uint32_t
+        context_gfn: uint64_t
+
+  up:
+    index: 1
+    input:
+      vcpuid: 2
+    c_lang:
+      params:
+        vcpuid: uint32_t
+
+  down:
+    index: 2
+    input:
+      vcpuid: 2
+    c_lang:
+      params:
+        vcpuid: uint32_t
+
+  is_up:
+    index: 3
+    input:
+      vcpuid: 2
+    c_lang:
+      params:
+        vcpuid: uint32_t
+
+  get_runstate_info:
+    index: 4
+    input:
+      vcpuid: 2
+    output:
+      state: 2
+      state_entry_time: 3
+      time[0]: 4
+      time[1]: 5
+      time[2]: 6
+      time[3]: 7
+    c_lang:
+      struct: vcpu_runstate_info
+      params:
+        vcpuid: uint32_t
+
+  register_runstate_phys_area:
+    index: 14
+    input:
+      vcpuid: 2
+      addr.p: 3
+    c_lang:
+      struct: vcpu_register_time_memory_area
+      params:
+        vcpuid: uint32_t
+
+  set_periodic_timer:
+    index: 6
+    input:
+      vcpuid: 2
+      period_ns: 3
+    c_lang:
+      struct: vcpu_set_periodic_timer
+      params:
+        vcpuid: uint32_t
+
+  stop_periodic_timer:
+    index: 7
+    input:
+      vcpuid: 2
+    c_lang:
+      params:
+        vcpuid: uint32_t
+  
+  set_singleshot_timer:
+    index: 8
+    input:
+      vcpuid: 2
+      timeout_abs_ns: 3
+      flags: 4
+    c_lang:
+      struct: vcpu_set_singleshot_timer
+      params:
+        vcpuid: uint32_t
+
+  stop_singleshot_timer:
+    index: 9
+    input:
+      vcpuid: 2
+    c_lang:
+      params:
+        vcpuid: uint32_t
+
+  register_vcpu_info:
+    index: 10
+    input:
+      vcpuid: 2
+      mfn: 3
+      offset: 4
+    c_lang:
+      struct: vcpu_register_vcpu_info
+      params:
+        vcpuid: uint32_t
+
+  send_nmi:
+    index: 11
+    input:
+      vcpuid: 2
+    c_lang:
+      params:
+        vcpuid: uint32_t
+
+  get_physid:
+    index: 12
+    input:
+      vcpuid: 2
+      phys_id: 3
+    c_lang:
+      struct: vcpu_get_physid
+      params:
+        vcpuid: uint32_t
+
+  register_vcpu_time_phys_area:
+    index: 15
+    input:
+      vcpuid: 2
+      addr.p: 3
+    c_lang:
+      struct: vcpu_register_time_memory_area
+      params:
+        vcpuid: uint32_t
diff --git a/xen/abi/version.yml b/xen/abi/version.yml
new file mode 100644
index 0000000000..bce64a4d69
--- /dev/null
+++ b/xen/abi/version.yml
@@ -0,0 +1,15 @@
+name: version
+hypercall_index: 17
+
+subops:
+  version:
+    index: 0
+
+  get_features:
+    index: 6
+    input:
+      submap_idx: 2
+    output:
+      submap: 3
+    c_lang:
+      struct: xen_feature_info
diff --git a/xen/include/public/arch-x86/cpuid.h b/xen/include/public/arch-x86/cpuid.h
index 3bb0dd249f..ff44ce0e7b 100644
--- a/xen/include/public/arch-x86/cpuid.h
+++ b/xen/include/public/arch-x86/cpuid.h
@@ -106,6 +106,10 @@
  * bound to event channels.
  */
 #define XEN_HVM_CPUID_UPCALL_VECTOR    (1u << 6)
+/*
+ * Support for fast HVM ABI.
+ */
+#define XEN_HVM_CPUID_FASTABI          (1u << 7)
 
 /*
  * Leaf 6 (0x40000x05)
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RFC=20PATCH=209/9]=20tools:=20Introduce=20abi-tool?=
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Cc: "Teddy Astie" , "Andrew Cooper" , "Anthony PERARD" , "Michal Orzel" , "Jan Beulich" , "Julien Grall" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Stefano Stabellini" 
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abi-tool is a small Rust tool that is able to parse ABI yaml
files and generate C stubs for performing hypercalls.

Signed-off-by: Teddy Astie 
---
Usage :
./abi-tool < abi.yaml  > abi.h
---
 xen/tools/abi-tool/.gitignore    |   1 +
 xen/tools/abi-tool/Cargo.lock    | 145 ++++++++++++++++++++++++++
 xen/tools/abi-tool/Cargo.toml    |  11 ++
 xen/tools/abi-tool/src/abi.rs    |  23 ++++
 xen/tools/abi-tool/src/c_lang.rs | 173 +++++++++++++++++++++++++++++++
 xen/tools/abi-tool/src/main.rs   |  17 +++
 xen/tools/abi-tool/src/spec.rs   |  61 +++++++++++
 7 files changed, 431 insertions(+)
 create mode 100644 xen/tools/abi-tool/.gitignore
 create mode 100644 xen/tools/abi-tool/Cargo.lock
 create mode 100644 xen/tools/abi-tool/Cargo.toml
 create mode 100644 xen/tools/abi-tool/src/abi.rs
 create mode 100644 xen/tools/abi-tool/src/c_lang.rs
 create mode 100644 xen/tools/abi-tool/src/main.rs
 create mode 100644 xen/tools/abi-tool/src/spec.rs

diff --git a/xen/tools/abi-tool/.gitignore b/xen/tools/abi-tool/.gitignore
new file mode 100644
index 0000000000..1de565933b
--- /dev/null
+++ b/xen/tools/abi-tool/.gitignore
@@ -0,0 +1 @@
+target
\ No newline at end of file
diff --git a/xen/tools/abi-tool/Cargo.lock b/xen/tools/abi-tool/Cargo.lock
new file mode 100644
index 0000000000..056a68f20f
--- /dev/null
+++ b/xen/tools/abi-tool/Cargo.lock
@@ -0,0 +1,145 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+version = 4
+
+[[package]]
+name = "abi-tool"
+version = "0.1.0"
+dependencies = [
+ "anyhow",
+ "bimap",
+ "indexmap",
+ "serde",
+ "serde_yaml",
+]
+
+[[package]]
+name = "anyhow"
+version = "1.0.98"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e16d2d3311acee920a9eb8d33b8cbc1787ce4a264e85f964c2404b969bdcd487"
+
+[[package]]
+name = "arbitrary"
+version = "1.4.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "dde20b3d026af13f561bdd0f15edf01fc734f0dafcedbaf42bba506a9517f223"
+
+[[package]]
+name = "bimap"
+version = "0.6.3"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "230c5f1ca6a325a32553f8640d31ac9b49f2411e901e427570154868b46da4f7"
+dependencies = [
+ "serde",
+]
+
+[[package]]
+name = "equivalent"
+version = "1.0.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f"
+
+[[package]]
+name = "hashbrown"
+version = "0.15.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5971ac85611da7067dbfcabef3c70ebb5606018acd9e2a3903a0da507521e0d5"
+
+[[package]]
+name = "indexmap"
+version = "2.10.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "fe4cd85333e22411419a0bcae1297d25e58c9443848b11dc6a86fefe8c78a661"
+dependencies = [
+ "arbitrary",
+ "equivalent",
+ "hashbrown",
+ "serde",
+]
+
+[[package]]
+name = "itoa"
+version = "1.0.15"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "4a5f13b858c8d314ee3e8f639011f7ccefe71f97f96e50151fb991f267928e2c"
+
+[[package]]
+name = "proc-macro2"
+version = "1.0.95"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "02b3e5e68a3a1a02aad3ec490a98007cbc13c37cbe84a3cd7b8e406d76e7f778"
+dependencies = [
+ "unicode-ident",
+]
+
+[[package]]
+name = "quote"
+version = "1.0.40"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1885c039570dc00dcb4ff087a89e185fd56bae234ddc7f056a945bf36467248d"
+dependencies = [
+ "proc-macro2",
+]
+
+[[package]]
+name = "ryu"
+version = "1.0.20"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "28d3b2b1366ec20994f1fd18c3c594f05c5dd4bc44d8bb0c1c632c8d6829481f"
+
+[[package]]
+name = "serde"
+version = "1.0.219"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5f0e2c6ed6606019b4e29e69dbaba95b11854410e5347d525002456dbbb786b6"
+dependencies = [
+ "serde_derive",
+]
+
+[[package]]
+name = "serde_derive"
+version = "1.0.219"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5b0276cf7f2c73365f7157c8123c21cd9a50fbbd844757af28ca1f5925fc2a00"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "serde_yaml"
+version = "0.9.34+deprecated"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6a8b1a1a2ebf674015cc02edccce75287f1a0130d394307b36743c2f5d504b47"
+dependencies = [
+ "indexmap",
+ "itoa",
+ "ryu",
+ "serde",
+ "unsafe-libyaml",
+]
+
+[[package]]
+name = "syn"
+version = "2.0.104"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "17b6f705963418cdb9927482fa304bc562ece2fdd4f616084c50b7023b435a40"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "unicode-ident",
+]
+
+[[package]]
+name = "unicode-ident"
+version = "1.0.18"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5a5f39404a5da50712a4c1eecf25e90dd62b613502b7e925fd4e4d19b5c96512"
+
+[[package]]
+name = "unsafe-libyaml"
+version = "0.2.11"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "673aac59facbab8a9007c7f6108d11f63b603f7cabff99fabf650fea5c32b861"
diff --git a/xen/tools/abi-tool/Cargo.toml b/xen/tools/abi-tool/Cargo.toml
new file mode 100644
index 0000000000..eee8ad18a9
--- /dev/null
+++ b/xen/tools/abi-tool/Cargo.toml
@@ -0,0 +1,11 @@
+[package]
+name = "abi-tool"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+anyhow = "1.0.98"
+bimap = { version = "0.6.3", features = ["serde"] }
+indexmap = { version = "2.10.0", features = ["arbitrary", "serde"] }
+serde = { version = "1.0.219", features = ["derive"] }
+serde_yaml = "0.9.34"
diff --git a/xen/tools/abi-tool/src/abi.rs b/xen/tools/abi-tool/src/abi.rs
new file mode 100644
index 0000000000..9ca427e821
--- /dev/null
+++ b/xen/tools/abi-tool/src/abi.rs
@@ -0,0 +1,23 @@
+pub trait XenABI {
+    fn get_register_name(id: u8) -> &'static str;
+}
+
+pub struct Amd64ABI;
+
+impl XenABI for Amd64ABI {
+    fn get_register_name(id: u8) -> &'static str {
+        match id {
+            0 => "rax",
+            1 => "rdi",
+            2 => "rsi",
+            3 => "r8",
+            4 => "r9",
+            5 => "r10",
+            6 => "r11",
+            7 => "r12",
+            8 => "r13",
+
+            _ => panic!("Unexpected register id: {id}"),
+        }
+    }
+}
diff --git a/xen/tools/abi-tool/src/c_lang.rs b/xen/tools/abi-tool/src/c_lang.rs
new file mode 100644
index 0000000000..20389d305d
--- /dev/null
+++ b/xen/tools/abi-tool/src/c_lang.rs
@@ -0,0 +1,173 @@
+use std::{collections::HashMap, fmt::Write};
+
+use crate::{
+    abi::{Amd64ABI, XenABI},
+    spec::{AbiSpec, CType, HypercallOp},
+};
+
+fn emit_register_variable(
+    w: &mut impl Write,
+    id: u8,
+    value: Option<&str>,
+) -> anyhow::Result<()> {
+    write!(
+        w,
+        "    register {ctype} reg{id} __asm__(\"{reg}\")",
+        ctype = if id == 0 { "long" } else { "uint64_t" },
+        reg = ABI::get_register_name(id)
+    )?;
+    if let Some(value) = value {
+        write!(w, " = {value}")?;
+    }
+    writeln!(w, ";")?;
+
+    Ok(())
+}
+
+fn emit_hypercall(
+    w: &mut impl Write,
+    op: &HypercallOp,
+    ident: usize,
+    instruction: &str,
+) -> anyhow::Result<()> {
+    let start = format!("{:ident$}__asm__ volatile (\"{instruction}\" ", "");
+    let pad = start.len();
+
+    /* All the exclusive inputs. */
+    let reg_input = op
+        .input
+        .right_values()
+        .filter(|&input| !op.output.contains_right(input))
+        .map(|input| format!("\"r\"(reg{input})"))
+        .collect::>()
+        .join(", ");
+
+    /* Outputs that are also inputs are transformed into +r, the rest is =r */
+    let reg_output = op
+        .output
+        .right_values()
+        .chain(&[0]) /* 0 is always a input/output */
+        .map(|output| {
+            if *output == 0 || op.input.contains_right(output) {
+                format!("\"+r\"(reg{output})")
+            } else {
+                format!("\"=r\"(reg{output})")
+            }
+        })
+        .collect::>()
+        .join(", ");
+
+    writeln!(w, "{:ident$}{start}: {reg_output}", "")?;
+    writeln!(w, "{:ident$}{:pad$}: {reg_input}", "", "")?;
+    writeln!(w, "{:ident$}{:pad$}: \"memory\");", "", "")?;
+
+    Ok(())
+}
+
+fn generate_hypercall_function(
+    w: &mut impl Write,
+    hypercall_name: &str,
+    op: &HypercallOp,
+    function_name: &str,
+    subop_index: Option,
+) -> anyhow::Result<()> {
+    writeln!(w, "static inline")?;
+
+    eprintln!("Processing {hypercall_name}.{function_name}");
+    let annotations = op.c_lang.clone().unwrap_or_default();
+
+    assert!(
+        annotations.cstruct.is_some() || op.output.is_empty(),
+        "struct-less wrappers doesn't allow outputs, please use a C structure"
+    );
+
+    // Match each input register with its C value.
+    let input_map: HashMap = op
+        .input
+        .iter()
+        .map(|(name, &id)| {
+            if annotations.params.contains_key(name) {
+                (id, name.clone())
+            } else {
+                // Struct may have a custom mapping
+                let field = annotations.mapping.get(name).unwrap_or(name);
+
+                (id, format!("param->{field}"))
+            }
+        })
+        .collect();
+
+    write!(w, "long {function_name}(enum xen_hypercall_vendor vendor")?;
+    let pad = 6 + function_name.len();
+
+    if let Some(cstruct) = &annotations.cstruct {
+        write!(w, ",\n{:pad$}struct {cstruct} *param", "",)?;
+    }
+
+    for (name, CType(ctype)) in &annotations.params {
+        write!(w, ",\n{:pad$}{ctype} {name}", "",)?;
+    }
+
+    writeln!(w, ")")?;
+
+    writeln!(w, "{{")?;
+
+    for id in op.used_registers() {
+        // If it is a input, we need to set it here.
+        let value = match (id, subop_index) {
+            /* Hypercall index */
+            (0, _) => Some(format!(
+                "__HYPERVISOR_FASTABI_MASK | __HYPERVISOR_{hypercall_name}_op"
+            )),
+            /* Sub-operation index */
+            (1, Some(subop_index)) => Some(format!("{subop_index}")),
+            /* Other input parameter */
+            (id, _) => input_map.get(&id).cloned(),
+        };
+
+        emit_register_variable::(w, id, value.as_deref())?;
+    }
+    writeln!(w)?;
+
+    writeln!(w, "    if ( vendor == Intel )")?;
+    emit_hypercall::(w, op, 4, "vmcall")?;
+    writeln!(w, "    else")?;
+    emit_hypercall::(w, op, 4, "vmmcall")?;
+
+    writeln!(w, "")?;
+
+    for (field, output) in &op.output {
+        let field = annotations.mapping.get(field).unwrap_or(field);
+
+        writeln!(w, "    param->{field} = reg{output};")?;
+    }
+
+    writeln!(w, "    return reg0;")?;
+
+    writeln!(w, "}}")?;
+
+    Ok(())
+}
+
+pub fn generate_code(w: &mut impl Write, spec: AbiSpec) -> anyhow::Result<()> {
+    writeln!(w, "/* SPDX-License-Identifier: MIT */")?;
+    writeln!(w, "/* AUTOGENERATED. DO NOT MODIFY */")?;
+    writeln!(w)?;
+
+    if let Some(op) = spec.direct {
+        let function_name = ["xen_hypercall", &spec.name].join("_");
+
+        generate_hypercall_function(w, &spec.name, &op, &function_name, None)?;
+        writeln!(w)?;
+    }
+
+    for (name, mut subop) in spec.subops {
+        let function_name = ["xen_hypercall", &spec.name, &name].join("_");
+        subop.op.input.insert("subop_index".to_string(), 1);
+
+        generate_hypercall_function(w, &spec.name, &subop.op, &function_name, Some(subop.index))?;
+        writeln!(w)?;
+    }
+
+    Ok(())
+}
diff --git a/xen/tools/abi-tool/src/main.rs b/xen/tools/abi-tool/src/main.rs
new file mode 100644
index 0000000000..dda85c24d5
--- /dev/null
+++ b/xen/tools/abi-tool/src/main.rs
@@ -0,0 +1,17 @@
+use std::io::{Read, stdin};
+
+pub mod abi;
+pub mod c_lang;
+pub mod spec;
+
+fn main() {
+    let mut buffer = String::new();
+    stdin().read_to_string(&mut buffer).unwrap();
+
+    let abi_spec: spec::AbiSpec = serde_yaml::from_str(&buffer).unwrap();
+
+    let mut buffer = String::new();
+
+    c_lang::generate_code(&mut buffer, abi_spec).unwrap();
+    print!("{buffer}");
+}
diff --git a/xen/tools/abi-tool/src/spec.rs b/xen/tools/abi-tool/src/spec.rs
new file mode 100644
index 0000000000..e5fb2c85d2
--- /dev/null
+++ b/xen/tools/abi-tool/src/spec.rs
@@ -0,0 +1,61 @@
+use std::collections::{BTreeSet, HashMap};
+
+use bimap::BiBTreeMap;
+use indexmap::IndexMap; /* use indexmap to keep consistent ordering */
+use serde::Deserialize;
+
+fn default_ctype() -> String {
+    "uint64_t".into()
+}
+
+#[derive(Clone, Debug, Deserialize, PartialEq, Eq, Hash)]
+pub struct CType(#[serde(default = "default_ctype")] pub String);
+
+#[derive(Clone, Debug, Default, Deserialize)]
+pub struct CAnnotations {
+    #[serde(rename = "struct")]
+    pub cstruct: Option,
+    #[serde(default)]
+    pub mapping: HashMap,
+    #[serde(default)]
+    pub params: HashMap,
+}
+
+#[derive(Debug, Deserialize)]
+pub struct HypercallOp {
+    #[serde(default)]
+    pub input: BiBTreeMap,
+    #[serde(default)]
+    pub output: BiBTreeMap,
+
+    pub c_lang: Option,
+}
+
+impl HypercallOp {
+    pub fn used_registers(&self) -> BTreeSet {
+        self.input
+            .right_values()
+            .chain(self.output.right_values())
+            .chain(&[0])
+            .cloned()
+            .collect()
+    }
+}
+
+#[derive(Debug, Deserialize)]
+pub struct HypercallSubOp {
+    pub index: u32,
+    #[serde(flatten)]
+    pub op: HypercallOp,
+}
+
+#[derive(Debug, Deserialize)]
+pub struct AbiSpec {
+    pub hypercall_index: u32,
+    pub name: String,
+
+    pub direct: Option,
+
+    #[serde(default)]
+    pub subops: IndexMap,
+}
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 02/10] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Topic: [PATCH v2 02/10] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Index: AQHcB5d7oc7jtkgiGki3l7l8xwTnbg==
Date: Thu, 21 Aug 2025 15:39:13 +0000
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References:
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
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Hi Leonid,

Leonid Komarianskyi  writes:

> Introduced two new helper functions: gic_is_valid_irq and
> gic_is_shared_irq. The first function helps determine whether an IRQ
> number is less than the number of lines supported by hardware. The
> second function additionally checks if the IRQ number falls within the
> SPI range. Also, updated the appropriate checks to use these new helper
> functions.
>
> The current checks for the real GIC are very similar to those for the
> vGIC but serve a different purpose. For GIC-related code, the interrupt
> numbers should be validated based on whether the hardware can operate
> with such interrupts. On the other hand, for the vGIC, the indexes must
> also be verified to ensure they are available for a specific domain. The
> first reason for introducing these helper functions is to avoid
> potential confusion with vGIC-related checks. The second reason is to
> consolidate similar code into separate functions, which can be more
> easily extended by additional conditions, e.g., when implementing
> extended SPI interrupts.
>
> The changes, which replace open-coded checks with the use of the new
> helper functions, do not introduce any functional changes, as the helper
> functions follow the current IRQ index verification logic.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - introduced this patch
> ---
>  xen/arch/arm/gic.c             | 2 +-
>  xen/arch/arm/include/asm/gic.h | 9 +++++++++
>  xen/arch/arm/irq.c             | 2 +-
>  3 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index e80fe0ca24..eb0346a898 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -111,7 +111,7 @@ static void gic_set_irq_priority(struct irq_desc *des=
c, unsigned int priority)
>  void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority)
>  {
>      ASSERT(priority <=3D 0xff);     /* Only 8 bits of priority */
> -    ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts tha=
t don't exist */
> +    ASSERT(gic_is_valid_irq(desc->irq));/* Can't route interrupts that d=
on't exist */
>      ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
>      ASSERT(spin_is_locked(&desc->lock));
> =20
> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gi=
c.h
> index 541f0eeb80..ac0b7b783e 100644
> --- a/xen/arch/arm/include/asm/gic.h
> +++ b/xen/arch/arm/include/asm/gic.h
> @@ -306,6 +306,15 @@ extern void gic_dump_vgic_info(struct vcpu *v);
> =20
>  /* Number of interrupt lines */
>  extern unsigned int gic_number_lines(void);
> +static inline bool gic_is_valid_irq(unsigned int irq)

We need to do something about naming, because this function completely
ignores presence of LPIs. What I mean, that it will return "false" for
any LPI, while you can't argue that LPI is a valid interrupt :)
I understand that this is expected behavior by current callers, but the
function name is misleading.

Name like "gic_is_valid_non_lpi()" seems to mouthful, but it is the best
I can come up with.

> +{
> +    return irq < gic_number_lines();
> +}
> +
> +static inline bool gic_is_shared_irq(unsigned int irq)
> +{
> +    return (irq >=3D NR_LOCAL_IRQS && gic_is_valid_irq(irq));

Again, because of misleading name of gic_is_valid_irq() it may seem that
this function will return "true" for LPIs as well...

> +}
> =20
>  /* IRQ translation function for the device tree */
>  int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 03fbb90c6c..12c70d02cc 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -415,7 +415,7 @@ err:
>  bool is_assignable_irq(unsigned int irq)
>  {
>      /* For now, we can only route SPIs to the guest */
> -    return (irq >=3D NR_LOCAL_IRQS) && (irq < gic_number_lines());
> +    return gic_is_shared_irq(irq);
>  }
> =20
>  /*

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Topic: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Index: AQHcB5d76MRh/Swq2EGu624C+G/Fbw==
Date: Thu, 21 Aug 2025 15:46:39 +0000
Message-ID: <87y0rcekyo.fsf@epam.com>
References:
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
	
In-Reply-To:
 
	(Leonid Komarianskyi's message of "Thu, 7 Aug 2025 12:33:30 +0000")
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Leonid Komarianskyi  writes:

> Introduced two new helper functions for vGIC: vgic_is_valid_irq and
> vgic_is_shared_irq. The functions are similar to the newly introduced
> gic_is_valid_irq and gic_is_shared_irq, but they verify whether a vIRQ
> is available for a specific domain, while GIC-specific functions
> validate INTIDs for the real GIC hardware. For example, the GIC may
> support all 992 SPI lines, but the domain may use only some part of them
> (e.g., 640), depending on the highest IRQ number defined in the domain
> configuration. Therefore, for vGIC-related code and checks, the
> appropriate functions should be used. Also, updated the appropriate
> checks to use these new helper functions.
>
> The purpose of introducing new helper functions for vGIC is essentially
> the same as for GIC: to avoid potential confusion with GIC-related
> checks and to consolidate similar code into separate functions, which
> can be more easily extended by additional conditions, e.g., when
> implementing extended SPI interrupts.
>
> Only the validation change in vgic_inject_irq may affect existing
> functionality, as it currently checks whether the vIRQ is less than or
> equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
> first SPI), the check should behave consistently with similar logic in
> other places and should check if the vIRQ number is less than
> vgic_num_irqs. The remaining changes, which replace open-coded checks
> with the use of these new helper functions, do not introduce any
> functional changes, as the helper functions follow the current vIRQ
> index verification logic.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - introduced this patch
> ---
>  xen/arch/arm/gic.c              |  3 +--
>  xen/arch/arm/include/asm/vgic.h |  7 +++++++
>  xen/arch/arm/irq.c              |  4 ++--
>  xen/arch/arm/vgic.c             | 10 ++++++++--
>  4 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index eb0346a898..47fccf21d8 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -133,8 +133,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned=
 int virq,
> =20
>      ASSERT(spin_is_locked(&desc->lock));
>      /* Caller has already checked that the IRQ is an SPI */
> -    ASSERT(virq >=3D 32);
> -    ASSERT(virq < vgic_num_irqs(d));
> +    ASSERT(vgic_is_shared_irq(d, virq));
>      ASSERT(!is_lpi(virq));
> =20
>      ret =3D vgic_connect_hw_irq(d, NULL, virq, desc, true);
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 35c0c6a8b0..45201f4ca5 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -335,6 +335,13 @@ extern void vgic_check_inflight_irqs_pending(struct =
vcpu *v,
>  /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. =
*/
>  #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
> =20
> +extern bool vgic_is_valid_irq(struct domain *d, unsigned int virq);
> +
> +static inline bool vgic_is_shared_irq(struct domain *d, unsigned int vir=
q)
> +{
> +    return (virq >=3D NR_LOCAL_IRQS && vgic_is_valid_irq(d, virq));
> +}
> +
>  /*
>   * Allocate a guest VIRQ
>   *  - spi =3D=3D 0 =3D> allocate a PPI. It will be the same on every vCP=
U
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 12c70d02cc..50e57aaea7 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -442,7 +442,7 @@ int route_irq_to_guest(struct domain *d, unsigned int=
 virq,
>      unsigned long flags;
>      int retval =3D 0;
> =20
> -    if ( virq >=3D vgic_num_irqs(d) )
> +    if ( !vgic_is_valid_irq(d, virq) )
>      {
>          printk(XENLOG_G_ERR
>                 "the vIRQ number %u is too high for domain %u (max =3D %u=
)\n",
> @@ -560,7 +560,7 @@ int release_guest_irq(struct domain *d, unsigned int =
virq)
>      int ret;
> =20
>      /* Only SPIs are supported */
> -    if ( virq < NR_LOCAL_IRQS || virq >=3D vgic_num_irqs(d) )
> +    if ( !vgic_is_shared_irq(d, virq) )
>          return -EINVAL;
> =20
>      desc =3D vgic_get_hw_irq_desc(d, NULL, virq);
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index c563ba93af..48fbaf56fb 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -24,6 +24,12 @@
>  #include 
>  #include 
> =20
> +
> +bool vgic_is_valid_irq(struct domain *d, unsigned int virq)

I have the same comment as for the previous patch. This function
completely ignores LPIs presence, while you can't argue that LPIs as
valid. Again, function callers are expecting this behavior, so this is
fine, but function name should better reflect its behavior.

[...]

--=20
WBR, Volodymyr=


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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 1/2] x86/mce: Sort headers
Date: Thu, 21 Aug 2025 16:48:24 +0100
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No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/cpu/mcheck/mce_intel.c | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 1e52b1ac25a4..d1d61bc95069 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -1,29 +1,30 @@
+#include 
+#include 
+#include 
 #include 
-#include 
 #include 
-#include 
 #include 
-#include 
+#include 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
+
+#include 
+#include 
 #include 
 #include 
-#include 
-#include 
+#include 
+#include 
 
 #include 
 
-#include "mce.h"
-#include "x86_mca.h"
+#include 
+
 #include "barrier.h"
+#include "mcaction.h"
+#include "mce.h"
 #include "util.h"
 #include "vmce.h"
-#include "mcaction.h"
+#include "x86_mca.h"
 
 static DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, mce_banks_owned);
 static bool __read_mostly ser_support;
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 2/2] x86/mce: Adjustments to intel_init_ppin()
Date: Thu, 21 Aug 2025 16:48:25 +0100
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There's no family check gating intel_init_ppin(), making it incorrect to use
on non Fam6 CPUs.  Switch to using VFM.

Emerald Rapids is the final CPU to have PPIN but lack the the architectural
enumeration, so include it too.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/cpu/mcheck/mce_intel.c | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index d1d61bc95069..16f286566ce7 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -9,6 +9,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -859,7 +860,7 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
      * other purposes.  Despite the late addition of a CPUID bit (rendering
      * the MSR architectural), keep using the same detection logic there.
      */
-    switch ( c->x86_model )
+    switch ( c->vfm )
     {
         uint64_t val;
 
@@ -870,14 +871,15 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c)
             return;
         }
         fallthrough;
-    case 0x3e: /* IvyBridge X */
-    case 0x3f: /* Haswell X */
-    case 0x4f: /* Broadwell X */
-    case 0x55: /* Skylake X */
-    case 0x56: /* Broadwell Xeon D */
-    case 0x6a: /* Icelake X */
-    case 0x6c: /* Icelake D */
-    case 0x8f: /* Sapphire Rapids X */
+    case INTEL_IVYBRIDGE_X:
+    case INTEL_HASWELL_X:
+    case INTEL_BROADWELL_X:
+    case INTEL_BROADWELL_D:
+    case INTEL_SKYLAKE_X:
+    case INTEL_ICELAKE_X:
+    case INTEL_ICELAKE_D:
+    case INTEL_SAPPHIRERAPIDS_X:
+    case INTEL_EMERALDRAPIDS_X:
 
         if ( (c != &boot_cpu_data && !ppin_msr) ||
              rdmsr_safe(MSR_PPIN_CTL, val) )
-- 
2.39.5



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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Topic: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcB5d7kgaRrTB4eUK2JDUmO9y7Hw==
Date: Thu, 21 Aug 2025 15:59:07 +0000
Message-ID: <87ms7sekdx.fsf@epam.com>
References:
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
	<418e7e8082fa8f7b6659ff8cae3beb773803ca47.1754568795.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <418e7e8082fa8f7b6659ff8cae3beb773803ca47.1754568795.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Thu, 7 Aug 2025 12:33:31 +0000")
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Leonid Komarianskyi  writes:

> Currently, Xen does not support eSPI interrupts, leading
> to a data abort when such interrupts are defined in the DTS.
>
> This patch introduces a separate array to initialize up to
> 1024 interrupt descriptors in the eSPI range and adds the
> necessary defines and helper function. These changes lay the
> groundwork for future implementation of full eSPI interrupt
> support. As this GICv3.1 feature is not required by all vendors,
> all changes are guarded by ifdefs, depending on the corresponding
> Kconfig option.

I don't think that it is a good idea to hide this feature under Kconfig
option, as this will increase number of different build variants.
I believe that runtime check for GICD_TYPER.ESPI should be sufficient,
but maintainers can correct me there.

>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
> - remove unnecessary comment for nr_irqs initialization
> ---
>  xen/arch/arm/Kconfig           |  9 +++++++++
>  xen/arch/arm/include/asm/irq.h | 25 +++++++++++++++++++++++++
>  xen/arch/arm/irq.c             | 26 ++++++++++++++++++++++++++
>  3 files changed, 60 insertions(+)
>
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index 17df147b25..08073ece1f 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -135,6 +135,15 @@ config GICV3
>  	  Driver for the ARM Generic Interrupt Controller v3.
>  	  If unsure, use the default setting.
> =20
> +config GICV3_ESPI
> +	bool "Extended SPI range support"
> +	depends on GICV3 && !NEW_VGIC
> +	default y
> +	help
> +	  Allow Xen and domains to use interrupt numbers from the extended SPI
> +	  range, from 4096 to 5119. This feature is introduced in GICv3.1
> +	  architecture.
> +
>  config HAS_ITS
>          bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPO=
RTED
>          depends on GICV3 && !NEW_VGIC && !ARM_32
> diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/ir=
q.h
> index 5bc6475eb4..acebc3d42f 100644
> --- a/xen/arch/arm/include/asm/irq.h
> +++ b/xen/arch/arm/include/asm/irq.h
> @@ -32,6 +32,14 @@ struct arch_irq_desc {
>  #define SPI_MAX_INTID   1019
>  #define LPI_OFFSET      8192
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +#define ESPI_BASE_INTID 4096
> +#define ESPI_MAX_INTID  5119
> +
> +#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
> +#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
> +#endif
> +
>  /* LPIs are always numbered starting at 8192, so 0 is a good invalid cas=
e. */
>  #define INVALID_LPI     0
> =20
> @@ -39,7 +47,15 @@ struct arch_irq_desc {
>  #define INVALID_IRQ     1023
> =20
>  extern const unsigned int nr_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * This will also cover the eSPI range, as some critical devices
> + * for booting Xen (e.g., serial) may use this type of interrupts.
> + */
> +#define nr_static_irqs (ESPI_MAX_INTID + 1)
> +#else
>  #define nr_static_irqs NR_IRQS
> +#endif

Don't introduce defines that look like variables. I am sure that MISRA
team will be unhappy about that. But what you can really do is to
introduce variable nr_static_irqs, which value will depend on
GICD_TYPER.ESPI and GICD_TYPER.ESPI_range

> =20
>  struct irq_desc;
>  struct irqaction;
> @@ -55,6 +71,15 @@ static inline bool is_lpi(unsigned int irq)
>      return irq >=3D LPI_OFFSET;
>  }
> =20
> +static inline bool is_espi(unsigned int irq)
> +{
> +#ifdef CONFIG_GICV3_ESPI
> +    return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID);
> +#else
> +    return false;
> +#endif
> +}
> +
>  #define domain_pirq_to_irq(d, pirq) (pirq)
> =20
>  bool is_assignable_irq(unsigned int irq);
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 50e57aaea7..9bc72fbbc9 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -19,7 +19,11 @@
>  #include 
>  #include 
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1;
> +#else
>  const unsigned int nr_irqs =3D NR_IRQS;
> +#endif
> =20
>  static unsigned int local_irqs_type[NR_LOCAL_IRQS];
>  static DEFINE_SPINLOCK(local_irqs_type_lock);
> @@ -46,6 +50,9 @@ void irq_end_none(struct irq_desc *irq)
>  }
> =20
>  static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
> +#ifdef CONFIG_GICV3_ESPI
> +static irq_desc_t espi_desc[NR_IRQS];

This is really confusing. Should it be something like espi_desc[NR_ESPI_IRQ=
S]?

> +#endif

>  static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc);
> =20
>  struct irq_desc *__irq_to_desc(unsigned int irq)
> @@ -53,6 +60,11 @@ struct irq_desc *__irq_to_desc(unsigned int irq)
>      if ( irq < NR_LOCAL_IRQS )
>          return &this_cpu(local_irq_desc)[irq];
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( is_espi(irq) )
> +        return &espi_desc[ESPI_INTID2IDX(irq)];
> +#endif
> +
>      return &irq_desc[irq-NR_LOCAL_IRQS];
>  }
> =20
> @@ -79,6 +91,20 @@ static int __init init_irq_data(void)
>          desc->action  =3D NULL;
>      }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( irq =3D ESPI_BASE_INTID; irq <=3D ESPI_MAX_INTID; irq++ )
> +    {
> +        struct irq_desc *desc =3D irq_to_desc(irq);
> +        int rc =3D init_one_irq_desc(desc);
> +
> +        if ( rc )
> +            return rc;
> +
> +        desc->irq =3D irq;
> +        desc->action  =3D NULL;
> +    }
> +#endif
> +
>      return 0;
>  }

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC addresses
 for common operations
Thread-Topic: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC
 addresses for common operations
Thread-Index: AQHcB5d7cCAQRdJCgUKSzBGsZt4ytQ==
Date: Thu, 21 Aug 2025 16:00:34 +0000
Message-ID: <87h5y0ekbi.fsf@epam.com>
References: 
	<7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
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 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Thu, 7 Aug 2025 12:33:30 +0000")
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Hi,

Leonid Komarianskyi  writes:

> Currently, many common functions perform the same operations to calculate
> GIC register addresses. This patch consolidates the similar code into
> a separate helper function to improve maintainability and reduce duplicat=
ion.
> This refactoring also simplifies the implementation of eSPI support in fu=
ture
> changes.
>
> Signed-off-by: Leonid Komarianskyi 

Reviewed-by: Volodymyr Babchuk 

>
> ---
> Changes in V2:
> - no changes
> ---
>  xen/arch/arm/gic-v3.c          | 99 ++++++++++++++++++++++------------
>  xen/arch/arm/include/asm/irq.h |  1 +
>  2 files changed, 67 insertions(+), 33 deletions(-)
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index cd3e1acf79..8fd78aba44 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -445,17 +445,62 @@ static void gicv3_dump_state(const struct vcpu *v)
>      }
>  }
> =20
> +static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offse=
t)
> +{
> +    switch ( irqd->irq )
> +    {
> +    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD_RDIST_SGI_BASE + offset);
> +        case GICD_ICFGR:
> +            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
> +        case GICD_IPRIORITYR:
> +            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
> +        default:
> +            break;
> +        }
> +    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD + offset + (irqd->irq / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTER + irqd->irq * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYR + irqd->irq);
> +        default:
> +            break;
> +        }
> +    default:
> +        break;
> +    }
> +
> +    /* Something went wrong, we shouldn't be able to reach here */
> +    panic("Invalid offset 0x%x for IRQ#%d", offset, irqd->irq);
> +
> +    return NULL;
> +}
> +
>  static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_=
for_rwp)
>  {
>      u32 mask =3D 1U << (irqd->irq % 32);
> -    void __iomem *base;
> -
> -    if ( irqd->irq < NR_GIC_LOCAL_IRQS )
> -        base =3D GICD_RDIST_SGI_BASE;
> -    else
> -        base =3D GICD;
> +    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
> =20
> -    writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
> +    writel_relaxed(mask, addr);
> =20
>      if ( wait_for_rwp )
>          gicv3_wait_for_rwp(irqd->irq);
> @@ -463,15 +508,9 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u3=
2 offset, bool wait_for_rwp)
> =20
>  static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset)
>  {
> -    void __iomem *base;
> -    unsigned int irq =3D irqd->irq;
> -
> -    if ( irq >=3D NR_GIC_LOCAL_IRQS)
> -        base =3D GICD + (irq / 32) * 4;
> -    else
> -        base =3D GICD_RDIST_SGI_BASE;
> +    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
> =20
> -    return !!(readl(base + offset) & (1U << (irq % 32)));
> +    return !!(readl(addr) & (1U << (irqd->irq % 32)));
>  }
> =20
>  static void gicv3_unmask_irq(struct irq_desc *irqd)
> @@ -558,30 +597,26 @@ static inline uint64_t gicv3_mpidr_to_affinity(int =
cpu)
>  static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type)
>  {
>      uint32_t cfg, actual, edgebit;
> -    void __iomem *base;
> -    unsigned int irq =3D desc->irq;
> +    void __iomem *addr;
> =20
>      /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
> -    ASSERT(irq >=3D NR_GIC_SGI);
> +    ASSERT(desc->irq >=3D NR_GIC_SGI);
> =20
>      spin_lock(&gicv3.lock);
> =20
> -    if ( irq >=3D NR_GIC_LOCAL_IRQS)
> -        base =3D GICD + GICD_ICFGR + (irq / 16) * 4;
> -    else
> -        base =3D GICD_RDIST_SGI_BASE + GICR_ICFGR1;
> +    addr =3D get_addr_by_offset(desc, GICD_ICFGR);
> =20
> -    cfg =3D readl_relaxed(base);
> +    cfg =3D readl_relaxed(addr);
> =20
> -    edgebit =3D 2u << (2 * (irq % 16));
> +    edgebit =3D 2u << (2 * (desc->irq % 16));
>      if ( type & IRQ_TYPE_LEVEL_MASK )
>          cfg &=3D ~edgebit;
>      else if ( type & IRQ_TYPE_EDGE_BOTH )
>          cfg |=3D edgebit;
> =20
> -    writel_relaxed(cfg, base);
> +    writel_relaxed(cfg, addr);
> =20
> -    actual =3D readl_relaxed(base);
> +    actual =3D readl_relaxed(addr);
>      if ( ( cfg & edgebit ) ^ ( actual & edgebit ) )
>      {
>          printk(XENLOG_WARNING "GICv3: WARNING: "
> @@ -600,15 +635,12 @@ static void gicv3_set_irq_type(struct irq_desc *des=
c, unsigned int type)
>  static void gicv3_set_irq_priority(struct irq_desc *desc,
>                                     unsigned int priority)
>  {
> -    unsigned int irq =3D desc->irq;
> +    void __iomem *addr;
> =20
>      spin_lock(&gicv3.lock);
> =20
> -    /* Set priority */
> -    if ( irq < NR_GIC_LOCAL_IRQS )
> -        writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 =
+ irq);
> -    else
> -        writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
> +    addr =3D get_addr_by_offset(desc, GICD_IPRIORITYR);
> +    writeb_relaxed(priority, addr);
> =20
>      spin_unlock(&gicv3.lock);
>  }
> @@ -1273,6 +1305,7 @@ static void gicv3_irq_set_affinity(struct irq_desc =
*desc, const cpumask_t *mask)
>  {
>      unsigned int cpu;
>      uint64_t affinity;
> +    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IROUTER);
> =20
>      ASSERT(!cpumask_empty(mask));
> =20
> @@ -1284,7 +1317,7 @@ static void gicv3_irq_set_affinity(struct irq_desc =
*desc, const cpumask_t *mask)
>      affinity &=3D ~GICD_IROUTER_SPI_MODE_ANY;
> =20
>      if ( desc->irq >=3D NR_GIC_LOCAL_IRQS )
> -        writeq_relaxed_non_atomic(affinity, (GICD + GICD_IROUTER + desc-=
>irq * 8));
> +        writeq_relaxed_non_atomic(affinity, addr);
> =20
>      spin_unlock(&gicv3.lock);
>  }
> diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/ir=
q.h
> index fce7e42a33..5bc6475eb4 100644
> --- a/xen/arch/arm/include/asm/irq.h
> +++ b/xen/arch/arm/include/asm/irq.h
> @@ -29,6 +29,7 @@ struct arch_irq_desc {
>   */
>  #define NR_IRQS		1024
> =20
> +#define SPI_MAX_INTID   1019
>  #define LPI_OFFSET      8192
> =20
>  /* LPIs are always numbered starting at 8192, so 0 is a good invalid cas=
e. */

--=20
WBR, Volodymyr=


From xen-devel-bounces@lists.xenproject.org Thu Aug 21 16:14:23 2025
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Date: Thu, 21 Aug 2025 17:14:15 +0100
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC addresses
 for common operations
Content-Language: en-GB
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
From: Julien Grall 
In-Reply-To: <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
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Hi Leonid,

On 07/08/2025 13:33, Leonid Komarianskyi wrote:
> Currently, many common functions perform the same operations to calculate
> GIC register addresses. This patch consolidates the similar code into
> a separate helper function to improve maintainability and reduce duplication.
> This refactoring also simplifies the implementation of eSPI support in future
> changes.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V2:
> - no changes

I am a bit surprised this is just saying no changes given the discussion 
in v1. I feel you should have pinged on the v1 to close off the 
discussion before sending v2.

While I understand your point and could accept we consolidate the code...


> ---
>   xen/arch/arm/gic-v3.c          | 99 ++++++++++++++++++++++------------
>   xen/arch/arm/include/asm/irq.h |  1 +
>   2 files changed, 67 insertions(+), 33 deletions(-)
> 
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index cd3e1acf79..8fd78aba44 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -445,17 +445,62 @@ static void gicv3_dump_state(const struct vcpu *v)
>       }
>   }
>   
> +static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
> +{
> +    switch ( irqd->irq )
> +    {
> +    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD_RDIST_SGI_BASE + offset);
> +        case GICD_ICFGR:
> +            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
> +        case GICD_IPRIORITYR:
> +            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
> +        default:
> +            break;
> +        }
> +    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD + offset + (irqd->irq / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTER + irqd->irq * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYR + irqd->irq);
> +        default:
> +            break;
> +        }
> +    default:
> +        break;
> +    }
> +
> +    /* Something went wrong, we shouldn't be able to reach here */
 > +    panic("Invalid offset 0x%x for IRQ#%d", offset, irqd->irq);

... I still quite concerned about using panic here. We need to try to 
handle the error more gracefully in production.

Cheers,

-- 
Julien Grall



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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 05/10] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Topic: [PATCH v2 05/10] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcB5d9H9bLPDmInkebrBgUpOnx8g==
Date: Thu, 21 Aug 2025 16:16:33 +0000
Message-ID: <878qjcejkv.fsf@epam.com>
References:
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
	<2491bee7441f13a3c1a01fd77ece1749e7276352.1754568795.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <2491bee7441f13a3c1a01fd77ece1749e7276352.1754568795.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Thu, 7 Aug 2025 12:33:31 +0000")
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Hi,

Leonid Komarianskyi  writes:

> Introduced appropriate register definitions, helper macros,
> and initialization of required GICv3.1 distributor registers
> to support eSPI. This type of interrupt is handled in the
> same way as regular SPI interrupts, with the following
> differences:
>
> 1) eSPIs can have up to 1024 interrupts, starting from the
> beginning of the range, whereas regular SPIs use INTIDs from
> 32 to 1019, totaling 988 interrupts;
> 2) eSPIs start at INTID 4096, necessitating additional interrupt
> index conversion during register operations.
>
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - move gic_number_espis function from
>   [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
>   to use it in the newly introduced gic_is_valid_espi
> - add gic_is_valid_espi which checks if IRQ number is in supported
>   by HW eSPI range
> - update gic_is_valid_irq conditions to allow operations with eSPIs
> ---
>  xen/arch/arm/gic-v3.c                  | 73 ++++++++++++++++++++++++++
>  xen/arch/arm/include/asm/gic.h         | 17 ++++++
>  xen/arch/arm/include/asm/gic_v3_defs.h | 33 ++++++++++++
>  3 files changed, 123 insertions(+)
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 8fd78aba44..a0e8ee1a1e 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_d=
esc *irqd, u32 offset)
>          default:
>              break;
>          }
> +#ifdef CONFIG_GICV3_ESPI
> +    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
> +    {
> +        u32 irq_index =3D ESPI_INTID2IDX(irqd->irq);
> +
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ICENABLER:
> +            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ISPENDR:
> +            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ICPENDR:
> +            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ISACTIVER:
> +            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICACTIVER:
> +            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTERnE + irq_index * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYRnE + irq_index);
> +        default:
> +            break;
> +        }
> +    }
> +#endif
>      default:
>          break;
>      }
> @@ -645,6 +675,40 @@ static void gicv3_set_irq_priority(struct irq_desc *=
desc,
>      spin_unlock(&gicv3.lock);
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +unsigned int gic_number_espis(void)
> +{
> +    return gic_hw_ops->info->nr_espi;
> +}
> +
> +static void gicv3_dist_espi_common_init(uint32_t type)
> +{
> +    unsigned int espi_nr;
> +    int i;
> +
> +    espi_nr =3D min(1024U, GICD_TYPER_ESPIS_NUM(type));
> +    gicv3_info.nr_espi =3D espi_nr;
> +    /* The GIC HW doesn't support eSPI, so we can leave from here */
> +    if ( gicv3_info.nr_espi =3D=3D 0 )
> +        return;
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 16 )
> +        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 4 )
> +        writel_relaxed(GIC_PRI_IRQ_ALL, GICD + GICD_IPRIORITYRnE + (i / =
4) * 4);
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 32 )
> +    {
> +        writel_relaxed(0xffffffffU, GICD + GICD_ICENABLERnE + (i / 32) *=
 4);

Is there are particular reason why you use GENMASK(31,0) below, but
open-coded 0xffffffff here?

> +        writel_relaxed(0xffffffffU, GICD + GICD_ICACTIVERnE + (i / 32) *=
 4);

... and here?

> +    }
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 32 )
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) =
* 4);
> +}
> +#endif
> +
>  static void __init gicv3_dist_init(void)
>  {
>      uint32_t type;
> @@ -690,6 +754,10 @@ static void __init gicv3_dist_init(void)
>      for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i +=3D 32 )
>          writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * =
4);
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    gicv3_dist_espi_common_init(type);
> +#endif
> +
>      gicv3_dist_wait_for_rwp();
> =20
>      /* Turn on the distributor */
> @@ -703,6 +771,11 @@ static void __init gicv3_dist_init(void)
> =20
>      for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
>          writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8)=
;
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i =3D 0; i < gicv3_info.nr_espi; i++ )
> +        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * =
8);
> +#endif
>  }
> =20
>  static int gicv3_enable_redist(void)
> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gi=
c.h
> index ac0b7b783e..2f570abf70 100644
> --- a/xen/arch/arm/include/asm/gic.h
> +++ b/xen/arch/arm/include/asm/gic.h
> @@ -306,8 +306,21 @@ extern void gic_dump_vgic_info(struct vcpu *v);
> =20
>  /* Number of interrupt lines */
>  extern unsigned int gic_number_lines(void);
> +#ifdef CONFIG_GICV3_ESPI
> +extern unsigned int gic_number_espis(void);
> +
> +static inline bool gic_is_valid_espi(unsigned int irq)
> +{
> +    return (irq >=3D ESPI_BASE_INTID && irq < ESPI_IDX2INTID(gic_number_=
espis()));
> +}
> +#endif
> +
>  static inline bool gic_is_valid_irq(unsigned int irq)
>  {
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( gic_is_valid_espi(irq) )
> +        return true;
> +#endif
>      return irq < gic_number_lines();
>  }
> =20
> @@ -325,6 +338,10 @@ struct gic_info {
>      enum gic_version hw_version;
>      /* Number of GIC lines supported */
>      unsigned int nr_lines;
> +#ifdef CONFIG_GICV3_ESPI
> +    /* Number of GIC eSPI supported */
> +    unsigned int nr_espi;
> +#endif
>      /* Number of LR registers */
>      uint8_t nr_lrs;
>      /* Maintenance irq number */
> diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/includ=
e/asm/gic_v3_defs.h
> index 2af093e774..7f769b38e3 100644
> --- a/xen/arch/arm/include/asm/gic_v3_defs.h
> +++ b/xen/arch/arm/include/asm/gic_v3_defs.h
> @@ -37,6 +37,39 @@
>  #define GICD_IROUTER1019             (0x7FD8)
>  #define GICD_PIDR2                   (0xFFE8)
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/* Additional registers for GICv3.1 */
> +#define GICD_IGROUPRnE               (0x1000)
> +#define GICD_IGROUPRnEN              (0x107C)
> +#define GICD_ISENABLERnE             (0x1200)
> +#define GICD_ISENABLERnEN            (0x127C)
> +#define GICD_ICENABLERnE             (0x1400)
> +#define GICD_ICENABLERnEN            (0x147C)
> +#define GICD_ISPENDRnE               (0x1600)
> +#define GICD_ISPENDRnEN              (0x167C)
> +#define GICD_ICPENDRnE               (0x1800)
> +#define GICD_ICPENDRnEN              (0x187C)
> +#define GICD_ISACTIVERnE             (0x1A00)
> +#define GICD_ISACTIVERnEN            (0x1A7C)
> +#define GICD_ICACTIVERnE             (0x1C00)
> +#define GICD_ICACTIVERnEN            (0x1C7C)
> +#define GICD_IPRIORITYRnE            (0x2000)
> +#define GICD_IPRIORITYRnEN           (0x23FC)
> +#define GICD_ICFGRnE                 (0x3000)
> +#define GICD_ICFGRnEN                (0x30FC)
> +#define GICD_IROUTERnE               (0x8000)
> +#define GICD_IROUTERnEN              (0x9FFC)
> +
> +#define GICD_TYPER_ESPI_SHIFT        8
> +#define GICD_TYPER_ESPI_RANGE_SHIFT  27
> +#define GICD_TYPER_ESPI_RANGE_MASK   (0x1F)
> +#define GICD_TYPER_ESPI              (1U << GICD_TYPER_ESPI_SHIFT)
> +#define GICD_TYPER_ESPI_RANGE(typer) ((((typer) & GICD_TYPER_ESPI_RANGE_=
MASK) + 1) * 32)

Isn't this line a bit long?

> +#define GICD_TYPER_ESPIS_NUM(typer)    \
> +        (((typer) & GICD_TYPER_ESPI) ? \
> +        GICD_TYPER_ESPI_RANGE((typer) >> GICD_TYPER_ESPI_RANGE_SHIFT) : =
0)

I am not sure that this is correct.

Probably you wanted to write
+        GICD_TYPER_ESPI_RANGE((typer >> GICD_TYPER_ESPI_RANGE_SHIFT)) : 0)


> +#endif
> +
>  /* Common between GICD_PIDR2 and GICR_PIDR2 */
>  #define GIC_PIDR2_ARCH_MASK         (0xf0)
>  #define GIC_PIDR2_ARCH_GICv3        (0x30)

--=20
WBR, Volodymyr=


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Subject: Re: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 <3ba2381b4c782a5187161f9418e5a35e7916c752.1754568795.git.leonid_komarianskyi@epam.com>
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From: Oleksandr Tyshchenko 
In-Reply-To: <3ba2381b4c782a5187161f9418e5a35e7916c752.1754568795.git.leonid_komarianskyi@epam.com>
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On 07.08.25 15:33, Leonid Komarianskyi wrote:

Hello Leonid


> Implemented support for GICv3.1 extended SPI registers for vGICv3,
> allowing the emulation of eSPI-specific behavior for guest domains.
> The implementation includes read and write emulation for eSPI-related
> registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
> following a similar approach to the handling of regular SPIs.
> 
> The eSPI registers, previously located in reserved address ranges,
> are now adjusted to support MMIO read and write operations correctly
> when CONFIG_GICV3_ESPI is enabled.
> 
> The availability of eSPIs and the number of emulated extended SPIs
> for guest domains is reported by setting the appropriate bits in the
> GICD_TYPER register, based on the number of eSPIs requested by the
> domain and supported by the hardware. In cases where the configuration
> option is disabled, the hardware does not support eSPIs, or the domain
> does not request such interrupts, the functionality remains unchanged.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V2:
> - add missing rank index conversion for pending and inflight irqs
> ---
>   xen/arch/arm/vgic-v3.c | 248 ++++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 245 insertions(+), 3 deletions(-)
> 
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index 4369c55177..1cacbb6e43 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -111,7 +111,7 @@ static uint64_t vgic_fetch_irouter(struct vgic_irq_rank *rank,
>    * Note the offset will be aligned to the appropriate boundary.
>    */
>   static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *rank,
> -                               unsigned int offset, uint64_t irouter)
> +                               unsigned int offset, uint64_t irouter, bool espi)
>   {
>       struct vcpu *new_vcpu, *old_vcpu;
>       unsigned int virq;
> @@ -123,7 +123,8 @@ static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *rank,
>        * The IROUTER0-31, used for SGIs/PPIs, are reserved and should
>        * never call this function.
>        */
> -    ASSERT(virq >= 32);
> +    if ( !espi )
> +        ASSERT(virq >= 32);
>   
>       /* Get the index in the rank */
>       offset = virq & INTERRUPT_RANK_MASK;
> @@ -146,6 +147,11 @@ static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *rank,
>       /* Only migrate the IRQ if the target vCPU has changed */
>       if ( new_vcpu != old_vcpu )
>       {
> +#ifdef CONFIG_GICV3_ESPI
> +        /* Convert virq index to eSPI range */
> +        if ( espi )
> +            virq = ESPI_IDX2INTID(virq);
> +#endif
>           if ( vgic_migrate_irq(old_vcpu, new_vcpu, virq) )
>               write_atomic(&rank->vcpu[offset], new_vcpu->vcpu_id);
>       }
> @@ -685,6 +691,9 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v,
>       {
>       case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>       case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +#endif
>           /* We do not implement security extensions for guests, read zero */
>           if ( dabt.size != DABT_WORD ) goto bad_width;
>           goto read_as_zero;
> @@ -710,11 +719,19 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v,
>       /* Read the pending status of an IRQ via GICD/GICR is not supported */
>       case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
>       case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +#endif
>           goto read_as_zero;
>   
>       /* Read the active status of an IRQ via GICD/GICR is not supported */
>       case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
>       case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +#endif
>           goto read_as_zero;
>   
>       case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
> @@ -752,6 +769,61 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v,
>           return 1;
>       }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +        if ( dabt.size != DABT_WORD ) goto bad_width;


NIT: If I am not mistaken, the goto should be on the next line (here and 
in similar places throughout the added code).

> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_WORD);
> +        if ( rank == NULL ) goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        *r = vreg_reg32_extract(rank->ienable, info);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +        if ( dabt.size != DABT_WORD ) goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_WORD);
> +        if ( rank == NULL ) goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        *r = vreg_reg32_extract(rank->ienable, info);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    {
> +        uint32_t ipriorityr;
> +        uint8_t rank_index;
> +
> +        if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD ) goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DABT_WORD);
> +        if ( rank == NULL ) goto read_as_zero;
> +        rank_index = REG_RANK_INDEX(8, reg - GICD_IPRIORITYRnE, DABT_WORD);
> +
> +        vgic_lock_rank(v, rank, flags);
> +        ipriorityr = ACCESS_ONCE(rank->ipriorityr[rank_index]);
> +        vgic_unlock_rank(v, rank, flags);
> +
> +        *r = vreg_reg32_extract(ipriorityr, info);
> +
> +        return 1;
> +    }
> +
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +    {
> +        uint32_t icfgr;
> +
> +        if ( dabt.size != DABT_WORD ) goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WORD);
> +        if ( rank == NULL ) goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        icfgr = rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE, DABT_WORD)];
> +        vgic_unlock_rank(v, rank, flags);
> +
> +        *r = vreg_reg32_extract(icfgr, info);
> +
> +        return 1;
> +    }
> +#endif
> +
>       default:
>           printk(XENLOG_G_ERR
>                  "%pv: %s: unhandled read r%d offset %#08x\n",
> @@ -782,6 +854,9 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v,
>       {
>       case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>       case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +#endif
>           /* We do not implement security extensions for guests, write ignore */
>           goto write_ignore_32;
>   
> @@ -871,6 +946,87 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v,
>           vgic_unlock_rank(v, rank, flags);
>           return 1;
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +        if ( dabt.size != DABT_WORD ) goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_WORD);
> +        if ( rank == NULL ) goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        tr = rank->ienable;
> +        vreg_reg32_setbits(&rank->ienable, r, info);
> +        vgic_enable_irqs(v, (rank->ienable) & (~tr), EXT_RANK_IDX2NUM(rank->index));
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +        if ( dabt.size != DABT_WORD ) goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_WORD);
> +        if ( rank == NULL ) goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        tr = rank->ienable;
> +        vreg_reg32_clearbits(&rank->ienable, r, info);
> +        vgic_disable_irqs(v, (~rank->ienable) & tr, EXT_RANK_IDX2NUM(rank->index));
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +        if ( dabt.size != DABT_WORD ) goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ISPENDRnE, DABT_WORD);
> +        if ( rank == NULL ) goto write_ignore;
> +
> +        vgic_set_irqs_pending(v, r, EXT_RANK_IDX2NUM(rank->index));
> +
> +        return 1;
> +
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +        if ( dabt.size != DABT_WORD ) goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ICPENDRnE, DABT_WORD);
> +        if ( rank == NULL ) goto write_ignore;
> +
> +        vgic_check_inflight_irqs_pending(v, EXT_RANK_IDX2NUM(rank->index), r);
> +
> +        goto write_ignore;
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +        if ( dabt.size != DABT_WORD ) goto bad_width;
> +        printk(XENLOG_G_ERR
> +               "%pv: %s: unhandled word write %#"PRIregister" to ISACTIVER%d\n",

I would use ISACTIVER%dE in the printed message to distinguish between 
normal and "extended" registers (here and in similar places throughout 
the added code).

> +               v, name, r, reg - GICD_ISACTIVERnE);
> +        return 0;
> +
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +        printk(XENLOG_G_ERR
> +               "%pv: %s: unhandled word write %#"PRIregister" to ICACTIVER%d\n",
> +               v, name, r, reg - GICD_ICACTIVER);

s/GICD_ICACTIVER/GICD_ICACTIVERnE


[snip]


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On 19/08/2025 5:23 pm, Jan Beulich wrote:
> On 19.08.2025 15:52, Andrew Cooper wrote:
>> On 18/08/2025 12:27 pm, Jan Beulich wrote:
>>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>>> ... on capable toolchains.
>>>>
>>>> This avoids needing to hold rc in a register across the RDMSR, and in most
>>>> cases removes direct testing and branching based on rc, as the fault label can
>>>> be rearranged to directly land on the out-of-line block.
>>>>
>>>> There is a subtle difference in behaviour.  The old behaviour would, on fault,
>>>> still produce 0's and write to val.
>>>>
>>>> The new behaviour only writes val on success, and write_msr() is the only
>>>> place where this matters.  Move temp out of switch() scope and initialise it
>>>> to 0.
>>> But what's the motivation behind making this behavioral change? At least in
>>> the cases where the return value isn't checked, it would feel safer if we
>>> continued clearing the value. Even if in all cases where this could matter
>>> (besides the one you cover here) one can prove correctness by looking at
>>> surrounding code.
>> I didn't realise I'd made a change at first, but it's a consequence of
>> the compiler's ability to rearrange basic blocks.
>>
>> It can be fixed with ...
>>
>>>> --- a/xen/arch/x86/include/asm/msr.h
>>>> +++ b/xen/arch/x86/include/asm/msr.h
>>>> @@ -55,6 +55,24 @@ static inline void wrmsrns(uint32_t msr, uint64_t val)
>>>>  /* rdmsr with exception handling */
>>>>  static inline int rdmsr_safe(unsigned int msr, uint64_t *val)
>>>>  {
>>>> +#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
>>>> +    uint64_t lo, hi;
>>>> +    asm_inline goto (
>>>> +        "1: rdmsr\n\t"
>>>> +        _ASM_EXTABLE(1b, %l[fault])
>>>> +        : "=a" (lo), "=d" (hi)
>>>> +        : "c" (msr)
>>>> +        :
>>>> +        : fault );
>>>> +
>>>> +    *val = lo | (hi << 32);
>>>> +
>>>> +    return 0;
>>>> +
>>>> + fault:
>>     *val = 0;
>>
>> here, but I don't want to do this.  Because val is by pointer and
>> generally spilled to the stack, the compiler can't optimise away the store.
> But the compiler is dealing with such indirection in inline functions just
> fine. I don't expect it would typically spill val to the stack. Is there
> anything specific here that you think would make this more likely?

Yes.  The design of the functions they're used in.  Adding this line
results in:

add/remove: 0/0 grow/shrink: 7/2 up/down: 109/-36 (73)
Function                                     old     new   delta
read_msr                                    1243    1307     +64
resource_access                              326     341     +15
hwp_init_msrs.cold                           297     308     +11
probe_cpuid_faulting                         168     175      +7
svm_msr_read_intercept                      1034    1039      +5
hwp_write_request                            113     117      +4
hwp_init_msrs                                371     374      +3
amd_log_freq                                 844     828     -16
guest_rdmsr                                 2168    2148     -20

Taking read_msr() as a concrete example, this is because it's a store
into a parent functions variable, not into a local variable, and cannot
be elided.


>
>> I'd far rather get a real compiler error, than to have logic relying on
>> the result of a faulting MSR read.
> A compiler error? (Hmm, perhaps you think of uninitialized variable
> diagnostics. That may or may not trigger, depending on how else the
> caller's variable is used.)

Yes I was referring to the uninitialised variable diagnostic.  *_safe()
are fairly rare, and we've got plenty of coverage in CI.

~Andrew


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Subject: Re: [PATCH v2 02/10] xen/arm: gic: implement helper functions for
 INTID checks
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To: Volodymyr Babchuk ,
 Leonid Komarianskyi 
Cc: "xen-devel@lists.xenproject.org" ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel 
References: <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 <51a017aeab39af14ba40ab76b56f317270c7afaa.1754568795.git.leonid_komarianskyi@epam.com>
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Hi,

On 21/08/2025 16:39, Volodymyr Babchuk wrote:
> Leonid Komarianskyi  writes:
> 
>> Introduced two new helper functions: gic_is_valid_irq and
>> gic_is_shared_irq. The first function helps determine whether an IRQ
>> number is less than the number of lines supported by hardware. The
>> second function additionally checks if the IRQ number falls within the
>> SPI range. Also, updated the appropriate checks to use these new helper
>> functions.
>>
>> The current checks for the real GIC are very similar to those for the
>> vGIC but serve a different purpose. For GIC-related code, the interrupt
>> numbers should be validated based on whether the hardware can operate
>> with such interrupts. On the other hand, for the vGIC, the indexes must
>> also be verified to ensure they are available for a specific domain. The
>> first reason for introducing these helper functions is to avoid
>> potential confusion with vGIC-related checks. The second reason is to
>> consolidate similar code into separate functions, which can be more
>> easily extended by additional conditions, e.g., when implementing
>> extended SPI interrupts.
>>
>> The changes, which replace open-coded checks with the use of the new
>> helper functions, do not introduce any functional changes, as the helper
>> functions follow the current IRQ index verification logic.
>>
>> Signed-off-by: Leonid Komarianskyi 
>>
>> ---
>> Changes in V2:
>> - introduced this patch
>> ---
>>   xen/arch/arm/gic.c             | 2 +-
>>   xen/arch/arm/include/asm/gic.h | 9 +++++++++
>>   xen/arch/arm/irq.c             | 2 +-
>>   3 files changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
>> index e80fe0ca24..eb0346a898 100644
>> --- a/xen/arch/arm/gic.c
>> +++ b/xen/arch/arm/gic.c
>> @@ -111,7 +111,7 @@ static void gic_set_irq_priority(struct irq_desc *desc, unsigned int priority)
>>   void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority)
>>   {
>>       ASSERT(priority <= 0xff);     /* Only 8 bits of priority */
>> -    ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that don't exist */
>> +    ASSERT(gic_is_valid_irq(desc->irq));/* Can't route interrupts that don't exist */
>>       ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
>>       ASSERT(spin_is_locked(&desc->lock));
>>   
>> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h
>> index 541f0eeb80..ac0b7b783e 100644
>> --- a/xen/arch/arm/include/asm/gic.h
>> +++ b/xen/arch/arm/include/asm/gic.h
>> @@ -306,6 +306,15 @@ extern void gic_dump_vgic_info(struct vcpu *v);
>>   
>>   /* Number of interrupt lines */
>>   extern unsigned int gic_number_lines(void);
>> +static inline bool gic_is_valid_irq(unsigned int irq)
> 
> We need to do something about naming, because this function completely
> ignores presence of LPIs. What I mean, that it will return "false" for
> any LPI, while you can't argue that LPI is a valid interrupt :)
> I understand that this is expected behavior by current callers, but the
> function name is misleading.
> 
> Name like "gic_is_valid_non_lpi()" seems to mouthful, but it is the best
> I can come up with.

AFAIU, there is no interrupt lines for LPIs. So what about 
gic_is_valid_line()?

> 
>> +{
>> +    return irq < gic_number_lines();
>> +}
>> +
>> +static inline bool gic_is_shared_irq(unsigned int irq)
>> +{
>> +    return (irq >= NR_LOCAL_IRQS && gic_is_valid_irq(irq));
> 
> Again, because of misleading name of gic_is_valid_irq() it may seem that
> this function will return "true" for LPIs as well...

Even if we rename gic_is_valid_irq(), the function name would be 
misleading because LPIs are shared. I think it would be better named
gic_is_spi(...);

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v8 5/8] entry: Add arch_irqentry_exit_need_resched() for
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To: Jinjie Ruan 
References: <20250815030633.448613-1-ruanjinjie@huawei.com>
 <20250815030633.448613-6-ruanjinjie@huawei.com>
From: Ada Couprie Diaz 
Cc: catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com,
 sstabellini@kernel.org, mark.rutland@arm.com, mbenes@suse.cz,
 broonie@kernel.org, anshuman.khandual@arm.com, ryan.roberts@arm.com,
 chenl311@chinatelecom.cn, liaochang1@huawei.com, kristina.martsenko@arm.com,
 leitao@debian.org, ardb@kernel.org, linux-arm-kernel@lists.infradead.org,
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 Ada Couprie Diaz 
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Hello,

On 15/08/2025 04:06, Jinjie Ruan wrote:
> Compared to the generic entry code, ARM64 does additional checks
> when deciding to reschedule on return from interrupt. So introduce
> arch_irqentry_exit_need_resched() in the need_resched()
> condition of the generic raw_irqentry_exit_cond_resched(), with
> a NOP default. This will allow ARM64 to implement the architecture
> specific version for switching over to the generic entry code.
>
> Suggested-by: Ada Couprie Diaz 
> Suggested-by: Mark Rutland 
> Suggested-by: Kevin Brodsky 
> Suggested-by: Thomas Gleixner 
> Signed-off-by: Jinjie Ruan 
> ---
Looks good to me, thanks for the changes ! Reviewed-by: Ada Couprie Diaz 



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Subject: Re: [PATCH v8 6/8] arm64: entry: Refactor preempt_schedule_irq()
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To: Jinjie Ruan 
References: <20250815030633.448613-1-ruanjinjie@huawei.com>
 <20250815030633.448613-7-ruanjinjie@huawei.com>
From: Ada Couprie Diaz 
Cc: catalin.marinas@arm.com, will@kernel.org, oleg@redhat.com,
 sstabellini@kernel.org, mark.rutland@arm.com, mbenes@suse.cz,
 broonie@kernel.org, anshuman.khandual@arm.com, ryan.roberts@arm.com,
 chenl311@chinatelecom.cn, liaochang1@huawei.com, kristina.martsenko@arm.com,
 leitao@debian.org, ardb@kernel.org, linux-arm-kernel@lists.infradead.org,
 linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org,
 Ada Couprie Diaz 
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Hello,

On 15/08/2025 04:06, Jinjie Ruan wrote:
> To align the structure of the code with irqentry_exit_cond_resched()
> from the generic entry code, hoist the need_irq_preemption()
> and IS_ENABLED() check earlier. And different preemption check functions
> are defined based on whether dynamic preemption is enabled.
>
> Signed-off-by: Jinjie Ruan 
> ---

That looks good to me as well, thanks for the changes !
Reviewed-by: Ada Couprie Diaz 



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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 07/10] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
 allow eSPI processing
Thread-Topic: [PATCH v2 07/10] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
 allow eSPI processing
Thread-Index: AQHcB5d+mzEvAktxmEWCQ8jbw0fsdA==
Date: Thu, 21 Aug 2025 16:27:26 +0000
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References:
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
	
In-Reply-To:
 
	(Leonid Komarianskyi's message of "Thu, 7 Aug 2025 12:33:32 +0000")
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Hi Leonid,


Leonid Komarianskyi  writes:

> To properly deactivate guest interrupts and allow them to be retriggered
> after the initial trigger, the LR needs to be updated. The current
> implementation ignores interrupts outside the range specified by the mask
> 0x3FF, which only covers IRQ numbers up to 1023. To enable processing of
> eSPI interrupts, this patch updates the mask to 0x13FF.

I am not sure how this supposed to work. According to the arch
specification, pINTID field in ICH_LR_EL2 is only 12 bits wide.


--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 08/10] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Topic: [PATCH v2 08/10] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcB5d/ZFUghU0g3UyhcWfovVArTw==
Date: Thu, 21 Aug 2025 16:43:25 +0000
Message-ID: <87tt20d3rn.fsf@epam.com>
References:
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
	
In-Reply-To:
 
	(Leonid Komarianskyi's message of "Thu, 7 Aug 2025 12:33:33 +0000")
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Leonid Komarianskyi  writes:

> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
> requested by the guest. A new field, ext_shared_irqs, is added
> to the VGIC structure to store information about eSPIs, similar
> to how shared_irqs is used for regular SPIs.
>
> Since the eSPI range starts at INTID 4096 and INTIDs between 1025
> and 4095 are reserved, helper macros are introduced to simplify the
> transformation of indices and to enable easier access to eSPI-specific
> resources. These changes prepare the VGIC for processing eSPIs as
> required by future functionality.
>
> The initialization and deinitialization paths for vgic have been updated
> to allocate and free these resources appropriately. Additionally,
> updated handling of INTIDs greater than 1024, passed from the toolstack
> during domain creation, and verification logic ensures only valid SPI or
> eSPI INTIDs are used.
>
> The existing SPI behavior remains unaffected when guests do not request
> eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
> option is disabled.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - change is_espi_rank to is_valid_espi_rank to verify whether the array
>   element ext_shared_irqs exists. The previous version, is_espi_rank,
>   only checked if the rank index was less than the maximum possible eSPI
>   rank index, but this could potentially result in accessing a
>   non-existing array element. To address this, is_valid_espi_rank was
>   introduced, which ensures that the required eSPI rank exists
> - move gic_number_espis to
>   xen/arm: gicv3: implement handling of GICv3.1 eSPI
> - update vgic_is_valid_irq checks to allow operating with eSPIs
> - remove redundant newline in vgic_allocate_virq
> ---
>  xen/arch/arm/include/asm/vgic.h |  18 ++++
>  xen/arch/arm/vgic.c             | 145 ++++++++++++++++++++++++++++++++
>  2 files changed, 163 insertions(+)
>
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 45201f4ca5..9fa4523018 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -146,6 +146,10 @@ struct vgic_dist {
>      int nr_spis; /* Number of SPIs */
>      unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
>      struct vgic_irq_rank *shared_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +    struct vgic_irq_rank *ext_shared_irqs;
> +    int nr_espis; /* Number of extended SPIs */
> +#endif
>      /*
>       * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
>       * struct arch_vcpu.
> @@ -243,6 +247,14 @@ struct vgic_ops {
>  /* Number of ranks of interrupt registers for a domain */
>  #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
> +#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
> +#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
> +#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
> +#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
> +#endif
> +
>  #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
>  #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
> =20
> @@ -302,6 +314,12 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct=
 vcpu *v,
>                                                unsigned int b,
>                                                unsigned int n,
>                                                unsigned int s);
> +#ifdef CONFIG_GICV3_ESPI
> +extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
> +                                                  unsigned int b,
> +                                                  unsigned int n,
> +                                                  unsigned int s);
> +#endif
>  extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int =
irq);
>  extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n=
);
>  extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n)=
;
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 48fbaf56fb..1a6c765af9 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -27,9 +27,26 @@
> =20
>  bool vgic_is_valid_irq(struct domain *d, unsigned int virq)
>  {
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( virq >=3D ESPI_BASE_INTID && virq < ESPI_IDX2INTID(d->arch.vgic=
.nr_espis) )
> +        return true;
> +#endif
> +
>      return virq < vgic_num_irqs(d);
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * Since eSPI indexes start from 4096 and numbers from 1024 to
> + * 4095 are forbidden, we need to check both lower and upper
> + * limits for ranks.
> + */
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int ran=
k)
> +{
> +    return ( rank >=3D EXT_RANK_MIN && EXT_RANK_NUM2IDX(rank) < DOMAIN_N=
R_EXT_RANKS(d) );

I am pretty sure that max line length in 80 symbols, and here you have
more. As well in couple of other places below.

> +}
> +#endif
> +
>  static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>                                                    unsigned int rank)
>  {
> @@ -37,6 +54,10 @@ static inline struct vgic_irq_rank *vgic_get_rank(stru=
ct vcpu *v,
>          return v->arch.vgic.private_irqs;
>      else if ( rank <=3D DOMAIN_NR_RANKS(v->domain) )
>          return &v->domain->arch.vgic.shared_irqs[rank - 1];
> +#ifdef CONFIG_GICV3_ESPI
> +    else if ( is_valid_espi_rank(v->domain, rank) )
> +        return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(ra=
nk)];
> +#endif
>      else
>          return NULL;
>  }
> @@ -53,6 +74,16 @@ struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v,=
 unsigned int b,
>      return vgic_get_rank(v, rank);
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int =
b,
> +                                           unsigned int n, unsigned int =
s)
> +{
> +    unsigned int rank =3D REG_RANK_NR(b, (n >> s));
> +
> +    return vgic_get_rank(v, rank + EXT_RANK_MIN);
> +}
> +#endif
> +
>  struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq)
>  {
>      unsigned int rank =3D irq / 32;
> @@ -117,6 +148,29 @@ int domain_vgic_register(struct domain *d, unsigned =
int *mmio_count)
>      return 0;
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +static int init_vgic_espi(struct domain *d)
> +{
> +    int i;
> +
> +    if ( d->arch.vgic.nr_espis =3D=3D 0 )
> +        return 0;
> +
> +    d->arch.vgic.ext_shared_irqs =3D
> +        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
> +    if ( d->arch.vgic.ext_shared_irqs =3D=3D NULL )
> +        return -ENOMEM;
> +
> +    for ( i =3D 0; i < d->arch.vgic.nr_espis; i++ )
> +        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i + d->arch.vgi=
c.nr_spis], ESPI_IDX2INTID(i));
> +
> +    for ( i =3D 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
> +        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
> +
> +    return 0;
> +}
> +#endif
> +
>  int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>  {
>      int i;
> @@ -131,6 +185,30 @@ int domain_vgic_init(struct domain *d, unsigned int =
nr_spis)
>       */
>      nr_spis =3D ROUNDUP(nr_spis, 32);
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( nr_spis > ESPI_MAX_INTID )
> +        return -EINVAL;
> +
> +    if ( is_espi(nr_spis) )
> +    {
> +        /*
> +         * During domain creation, the toolstack specifies the maximum I=
NTID,
> +         * which is defined in the domain config subtracted by 32. To co=
mpute the
> +         * actual number of eSPI that will be usable for, add back 32.

I think, according to this, your if ( is_espi() ) check is wrong. Should
you add 32 here as well?

> +         */
> +        d->arch.vgic.nr_espis =3D min(nr_spis - ESPI_BASE_INTID + 32, 10=
24U);
> +        /* Verify if GIC HW can handle provided INTID */
> +        if ( d->arch.vgic.nr_espis > gic_number_espis() )
> +            return -EINVAL;
> +        /* Set the maximum available number for defult SPI to pass the n=
ext check */
> +        nr_spis =3D VGIC_DEF_NR_SPIS;
> +    } else
> +    {
> +        /* Domain will use the regular SPI range */
> +        d->arch.vgic.nr_espis =3D 0;
> +    }
> +#endif
> +
>      /* Limit the number of virtual SPIs supported to (1020 - 32) =3D 988=
  */
>      if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
>          return -EINVAL;
> @@ -145,7 +223,12 @@ int domain_vgic_init(struct domain *d, unsigned int =
nr_spis)
>          return -ENOMEM;
> =20
>      d->arch.vgic.pending_irqs =3D
> +#ifdef CONFIG_GICV3_ESPI
> +        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis +
> +                      d->arch.vgic.nr_espis);
> +#else
>          xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
> +#endif
>      if ( d->arch.vgic.pending_irqs =3D=3D NULL )
>          return -ENOMEM;
> =20
> @@ -156,12 +239,23 @@ int domain_vgic_init(struct domain *d, unsigned int=
 nr_spis)
>      for ( i =3D 0; i < DOMAIN_NR_RANKS(d); i++ )
>          vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    ret =3D init_vgic_espi(d);
> +    if ( ret )
> +        return ret;
> +#endif
> +
>      ret =3D d->arch.vgic.handler->domain_init(d);
>      if ( ret )
>          return ret;
> =20
>      d->arch.vgic.allocated_irqs =3D
> +#ifdef CONFIG_GICV3_ESPI
> +        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d) +
> +                      d->arch.vgic.nr_espis));
> +#else
>          xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
> +#endif
>      if ( !d->arch.vgic.allocated_irqs )
>          return -ENOMEM;
> =20
> @@ -195,9 +289,27 @@ void domain_vgic_free(struct domain *d)
>          }
>      }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i =3D 0; i < (d->arch.vgic.nr_espis); i++ )
> +    {
> +        struct pending_irq *p =3D spi_to_pending(d, ESPI_IDX2INTID(i));
> +
> +        if ( p->desc )
> +        {
> +            ret =3D release_guest_irq(d, p->irq);
> +            if ( ret )
> +                dprintk(XENLOG_G_WARNING, "d%u: Failed to release virq %=
u ret =3D %d\n",
> +                        d->domain_id, p->irq, ret);
> +        }
> +    }
> +#endif
> +
>      if ( d->arch.vgic.handler )
>          d->arch.vgic.handler->domain_free(d);
>      xfree(d->arch.vgic.shared_irqs);
> +#ifdef CONFIG_GICV3_ESPI
> +    xfree(d->arch.vgic.ext_shared_irqs);
> +#endif
>      xfree(d->arch.vgic.pending_irqs);
>      xfree(d->arch.vgic.allocated_irqs);
>  }
> @@ -331,6 +443,17 @@ void arch_move_irqs(struct vcpu *v)
>          if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-=
>status) )
>              irq_set_affinity(p->desc, cpu_mask);
>      }
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i =3D ESPI_BASE_INTID; i < (d)->arch.vgic.nr_espis; i++ )
> +    {
> +        v_target =3D vgic_get_target_vcpu(v, i);
> +        p =3D irq_to_pending(v_target, i);
> +
> +        if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-=
>status) )
> +            irq_set_affinity(p->desc, cpu_mask);
> +    }
> +#endif
>  }
> =20
>  void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
> @@ -538,6 +661,10 @@ struct pending_irq *irq_to_pending(struct vcpu *v, u=
nsigned int irq)
>          n =3D &v->arch.vgic.pending_irqs[irq];
>      else if ( is_lpi(irq) )
>          n =3D v->domain->arch.vgic.handler->lpi_to_pending(v->domain, ir=
q);
> +#ifdef CONFIG_GICV3_ESPI
> +    else if ( is_espi(irq) )
> +        n =3D &v->domain->arch.vgic.pending_irqs[ESPI_INTID2IDX(irq) + v=
->domain->arch.vgic.nr_spis];
> +#endif
>      else
>          n =3D &v->domain->arch.vgic.pending_irqs[irq - 32];
>      return n;
> @@ -547,6 +674,14 @@ struct pending_irq *spi_to_pending(struct domain *d,=
 unsigned int irq)
>  {
>      ASSERT(irq >=3D NR_LOCAL_IRQS);
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( is_espi(irq) )
> +    {
> +        irq =3D ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
> +        return &d->arch.vgic.pending_irqs[irq];
> +    }
> +#endif
> +
>      return &d->arch.vgic.pending_irqs[irq - 32];
>  }
> =20
> @@ -668,6 +803,11 @@ bool vgic_reserve_virq(struct domain *d, unsigned in=
t virq)
>      if ( !vgic_is_valid_irq(d, virq) )
>          return false;
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( is_espi(virq) )
> +        return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d)=
, d->arch.vgic.allocated_irqs);
> +#endif
> +
>      return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
>  }
> =20
> @@ -686,6 +826,11 @@ int vgic_allocate_virq(struct domain *d, bool spi)
>      {
>          first =3D 32;
>          end =3D vgic_num_irqs(d);
> +#ifdef CONFIG_GICV3_ESPI
> +        /* Take into account extended SPI range */
> +        end +=3D d->arch.vgic.nr_espis;
> +#endif
> +
>      }
> =20
>      /*

--=20
WBR, Volodymyr=


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Date: Thu, 21 Aug 2025 17:46:31 +0100
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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Content-Language: en-GB
To: Volodymyr Babchuk ,
 Leonid Komarianskyi 
Cc: "xen-devel@lists.xenproject.org" ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel 
References: <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 <418e7e8082fa8f7b6659ff8cae3beb773803ca47.1754568795.git.leonid_komarianskyi@epam.com>
 <87ms7sekdx.fsf@epam.com>
From: Julien Grall 
In-Reply-To: <87ms7sekdx.fsf@epam.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit

Hi,

On 21/08/2025 16:59, Volodymyr Babchuk wrote:
> Leonid Komarianskyi  writes:
> 
>> Currently, Xen does not support eSPI interrupts, leading
>> to a data abort when such interrupts are defined in the DTS.
>>
>> This patch introduces a separate array to initialize up to
>> 1024 interrupt descriptors in the eSPI range and adds the
>> necessary defines and helper function. These changes lay the
>> groundwork for future implementation of full eSPI interrupt
>> support. As this GICv3.1 feature is not required by all vendors,
>> all changes are guarded by ifdefs, depending on the corresponding
>> Kconfig option.
> 
> I don't think that it is a good idea to hide this feature under Kconfig
> option, as this will increase number of different build variants.
 > I believe that runtime check for GICD_TYPER.ESPI should be 
sufficient,> but maintainers can correct me there.

I haven't seen many board with ESPI available. So I think it would be 
better if this is under a Kconfig because not everyone may want to have 
the code.

[...]

>>   struct irq_desc;
>>   struct irqaction;
>> @@ -55,6 +71,15 @@ static inline bool is_lpi(unsigned int irq)
>>       return irq >= LPI_OFFSET;
>>   }
>>   
>> +static inline bool is_espi(unsigned int irq)
>> +{
>> +#ifdef CONFIG_GICV3_ESPI
>> +    return (irq >= ESPI_BASE_INTID && irq <= ESPI_MAX_INTID);
>> +#else
>> +    return false;
>> +#endif
>> +}
>> +
>>   #define domain_pirq_to_irq(d, pirq) (pirq)
>>   
>>   bool is_assignable_irq(unsigned int irq);
>> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
>> index 50e57aaea7..9bc72fbbc9 100644
>> --- a/xen/arch/arm/irq.c
>> +++ b/xen/arch/arm/irq.c
>> @@ -19,7 +19,11 @@
>>   #include 
>>   #include 
>>   
>> +#ifdef CONFIG_GICV3_ESPI
>> +const unsigned int nr_irqs = ESPI_MAX_INTID + 1;
>> +#else
>>   const unsigned int nr_irqs = NR_IRQS;
>> +#endif
>>   
>>   static unsigned int local_irqs_type[NR_LOCAL_IRQS];
>>   static DEFINE_SPINLOCK(local_irqs_type_lock);
>> @@ -46,6 +50,9 @@ void irq_end_none(struct irq_desc *irq)
>>   }
>>   
>>   static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
>> +#ifdef CONFIG_GICV3_ESPI
>> +static irq_desc_t espi_desc[NR_IRQS];

By how much will this increase the Xen binary?

> 
> This is really confusing. Should it be something like espi_desc[NR_ESPI_IRQS]?

+1.

Cheers,

-- 
Julien Grall



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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
 to support eSPIs
Thread-Topic: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
 to support eSPIs
Thread-Index: AQHcB5d/fLeRBY0aQE6DC46DWY0Ygw==
Date: Thu, 21 Aug 2025 16:46:47 +0000
Message-ID: <87o6s8d3m1.fsf@epam.com>
References:
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
	
In-Reply-To:
 
	(Leonid Komarianskyi's message of "Thu, 7 Aug 2025 12:33:34 +0000")
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Leonid Komarianskyi  writes:

> The Dom0 configuration logic in create_dom0() has been updated
> to account for extended SPIs when supported by the hardware and
> enabled with CONFIG_GICV3_ESPI. These changes ensure the proper
> calculation of the maximum number of SPIs and eSPIs available for Dom0.
>
> When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is
> enabled, the maximum number of eSPI interrupts is calculated using
> the ESPI_BASE_INTID offset (4096) and limited at 1024, with 32 IRQs
> subtracted. To ensure compatibility with non-Dom0 domains, this
> adjustment is applied by the toolstack during domain creation, while
> for Dom0 it is handled directly during VGIC initialization. If eSPIs
> are not supported, the calculation defaults to using the standard SPI
> range, with a maximum value of 992 interrupt lines as it works now.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - no changes
> ---
>  xen/arch/arm/domain_build.c     | 10 ++++++++++
>  xen/arch/arm/include/asm/vgic.h | 11 +++++++++++
>  2 files changed, 21 insertions(+)
>
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index d91a71acfd..fa5abf2dfb 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -2055,6 +2055,16 @@ void __init create_dom0(void)
>      /* The vGIC for DOM0 is exactly emulating the hardware GIC */
>      dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
>      dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS;
> +#ifdef CONFIG_GICV3_ESPI
> +    /*
> +     * Check if the hardware supports extended SPIs (even if the appropr=
iate config is set).
> +     * If not, the common SPI range will be used. Otherwise overwrite th=
e nr_spis with the
> +     * maximum available INTID from eSPI range. In that case, the number=
 of regular SPIs will
> +     * be adjusted to the maximum value during vGIC initialization.
> +     */
> +    if ( gic_number_espis() > 0 )
> +        dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_ESPIS;
> +#endif
>      dom0_cfg.arch.tee_type =3D tee_get_type();
>      dom0_cfg.max_vcpus =3D dom0_max_vcpus();
> =20
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 9fa4523018..117b3aa92c 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -353,6 +353,17 @@ extern void vgic_check_inflight_irqs_pending(struct =
vcpu *v,
>  /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. =
*/
>  #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * Returns the maximum eSPI INTID subtracted by 32. For non-Dom0 domains=
, the
> + * toolstack applies the same adjustment to cover local IRQs. We will ad=
d back
> + * this value during VGIC initialization. This ensures consistent handli=
ng for Dom0
> + * and other domains. For the regular SPI range interrupts in this case,=
 the maximum
> + * value of VGIC_DEF_NR_SPIS will be used.
> + */
> +#define VGIC_DEF_NR_ESPIS (ESPI_BASE_INTID + min(gic_number_espis(), 102=
4U) - 32)
Name of the define is wrong, as it is not number of eSPIs. Actually, this i=
s
maximum SPI (including eSPIs) number.

> +#endif
> +
>  extern bool vgic_is_valid_irq(struct domain *d, unsigned int virq);
> =20
>  static inline bool vgic_is_shared_irq(struct domain *d, unsigned int vir=
q)

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Julien Grall 
CC: Leonid Komarianskyi ,
	"xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Topic: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcB5d7kgaRrTB4eUK2JDUmO9y7Hw==
Date: Thu, 21 Aug 2025 16:59:01 +0000
Message-ID: <87frdkd31m.fsf@epam.com>
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	<87ms7sekdx.fsf@epam.com>	<9922f7f1-7249-424e-9bab-3aee2ce3b813@xen.org>
In-Reply-To: <9922f7f1-7249-424e-9bab-3aee2ce3b813@xen.org> (Julien Grall's
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Hi Julien,

Julien Grall  writes:

> Hi,
>
> On 21/08/2025 16:59, Volodymyr Babchuk wrote:
>> Leonid Komarianskyi  writes:
>>=20
>>> Currently, Xen does not support eSPI interrupts, leading
>>> to a data abort when such interrupts are defined in the DTS.
>>>
>>> This patch introduces a separate array to initialize up to
>>> 1024 interrupt descriptors in the eSPI range and adds the
>>> necessary defines and helper function. These changes lay the
>>> groundwork for future implementation of full eSPI interrupt
>>> support. As this GICv3.1 feature is not required by all vendors,
>>> all changes are guarded by ifdefs, depending on the corresponding
>>> Kconfig option.
>> I don't think that it is a good idea to hide this feature under
>> Kconfig
>> option, as this will increase number of different build variants.
>> I believe that runtime check for GICD_TYPER.ESPI should be
>   sufficient,> but maintainers can correct me there.
>
> I haven't seen many board with ESPI available. So I think it would be
> better if this is under a Kconfig because not everyone may want to
> have the code.

Probably, we can expect more in the future... Anyways, after reviewing
all patches in the series, I can see that code will be littered with
#ifdef CONFIG_GICV3_ESPI, which, probably, not a good thing.

>
> [...]
>
>>>   struct irq_desc;
>>>   struct irqaction;
>>> @@ -55,6 +71,15 @@ static inline bool is_lpi(unsigned int irq)
>>>       return irq >=3D LPI_OFFSET;
>>>   }
>>>   +static inline bool is_espi(unsigned int irq)
>>> +{
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID);
>>> +#else
>>> +    return false;
>>> +#endif
>>> +}
>>> +
>>>   #define domain_pirq_to_irq(d, pirq) (pirq)
>>>     bool is_assignable_irq(unsigned int irq);
>>> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
>>> index 50e57aaea7..9bc72fbbc9 100644
>>> --- a/xen/arch/arm/irq.c
>>> +++ b/xen/arch/arm/irq.c
>>> @@ -19,7 +19,11 @@
>>>   #include 
>>>   #include 
>>>   +#ifdef CONFIG_GICV3_ESPI
>>> +const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1;
>>> +#else
>>>   const unsigned int nr_irqs =3D NR_IRQS;
>>> +#endif
>>>     static unsigned int local_irqs_type[NR_LOCAL_IRQS];
>>>   static DEFINE_SPINLOCK(local_irqs_type_lock);
>>> @@ -46,6 +50,9 @@ void irq_end_none(struct irq_desc *irq)
>>>   }
>>>     static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +static irq_desc_t espi_desc[NR_IRQS];
>
> By how much will this increase the Xen binary?

I am wondering this also. The struct is cache aligned, so it will take
at least 128 bytes. The whole array will take at least 128kb. Not
great, not terrible. As this should go to .bss, it should not increase
the binary itself.

Maybe it is better to allocate this dynamically? I do understand that we
want to get rid of as many dynamic allocs as possible, but maybe in this
case it will be okay. As a bonus point, we can't leave this pointer
present even if CONFIG_GICV3_ESPI=3Dn, which will simplify some code in
latter patches.

[...]

--=20
WBR, Volodymyr=


From xen-devel-bounces@lists.xenproject.org Thu Aug 21 17:13:50 2025
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Subject: Re: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Content-Language: en-GB
To: Volodymyr Babchuk 
Cc: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel 
References: <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 <418e7e8082fa8f7b6659ff8cae3beb773803ca47.1754568795.git.leonid_komarianskyi@epam.com>
 <87ms7sekdx.fsf@epam.com> <9922f7f1-7249-424e-9bab-3aee2ce3b813@xen.org>
 <87frdkd31m.fsf@epam.com>
From: Julien Grall 
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On 21/08/2025 17:59, Volodymyr Babchuk wrote:
> Julien Grall  writes:
> 
>> Hi,
>>
>> On 21/08/2025 16:59, Volodymyr Babchuk wrote:
>>> Leonid Komarianskyi  writes:
>>>
>>>> Currently, Xen does not support eSPI interrupts, leading
>>>> to a data abort when such interrupts are defined in the DTS.
>>>>
>>>> This patch introduces a separate array to initialize up to
>>>> 1024 interrupt descriptors in the eSPI range and adds the
>>>> necessary defines and helper function. These changes lay the
>>>> groundwork for future implementation of full eSPI interrupt
>>>> support. As this GICv3.1 feature is not required by all vendors,
>>>> all changes are guarded by ifdefs, depending on the corresponding
>>>> Kconfig option.
>>> I don't think that it is a good idea to hide this feature under
>>> Kconfig
>>> option, as this will increase number of different build variants.
>>> I believe that runtime check for GICD_TYPER.ESPI should be
>>    sufficient,> but maintainers can correct me there.
>>
>> I haven't seen many board with ESPI available. So I think it would be
>> better if this is under a Kconfig because not everyone may want to
>> have the code.
> 
> Probably, we can expect more in the future...

Well yes. But I was under the impression this the preferred approach. 
See the discussion about disabling 32-bit support on 64-bit:

20250723075835.3993182-1-grygorii_strashko@epam.com

  Anyways, after reviewing
> all patches in the series, I can see that code will be littered with
> #ifdef CONFIG_GICV3_ESPI, which, probably, not a good thing.

The solution is to provide wrappers to reduce the number of #ifdef. I 
haven't checked all the places.
> 
>>
>> [...]
>>
>>>>    struct irq_desc;
>>>>    struct irqaction;
>>>> @@ -55,6 +71,15 @@ static inline bool is_lpi(unsigned int irq)
>>>>        return irq >= LPI_OFFSET;
>>>>    }
>>>>    +static inline bool is_espi(unsigned int irq)
>>>> +{
>>>> +#ifdef CONFIG_GICV3_ESPI
>>>> +    return (irq >= ESPI_BASE_INTID && irq <= ESPI_MAX_INTID);
>>>> +#else
>>>> +    return false;
>>>> +#endif
>>>> +}
>>>> +
>>>>    #define domain_pirq_to_irq(d, pirq) (pirq)
>>>>      bool is_assignable_irq(unsigned int irq);
>>>> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
>>>> index 50e57aaea7..9bc72fbbc9 100644
>>>> --- a/xen/arch/arm/irq.c
>>>> +++ b/xen/arch/arm/irq.c
>>>> @@ -19,7 +19,11 @@
>>>>    #include 
>>>>    #include 
>>>>    +#ifdef CONFIG_GICV3_ESPI
>>>> +const unsigned int nr_irqs = ESPI_MAX_INTID + 1;
>>>> +#else
>>>>    const unsigned int nr_irqs = NR_IRQS;
>>>> +#endif
>>>>      static unsigned int local_irqs_type[NR_LOCAL_IRQS];
>>>>    static DEFINE_SPINLOCK(local_irqs_type_lock);
>>>> @@ -46,6 +50,9 @@ void irq_end_none(struct irq_desc *irq)
>>>>    }
>>>>      static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
>>>> +#ifdef CONFIG_GICV3_ESPI
>>>> +static irq_desc_t espi_desc[NR_IRQS];
>>
>> By how much will this increase the Xen binary?
> 
> I am wondering this also. The struct is cache aligned, so it will take
> at least 128 bytes. The whole array will take at least 128kb. Not
> great, not terrible. As this should go to .bss, it should not increase
> the binary itself.

I guess "binary" was the wrong word. I was referring to the size of the 
Xen in memory. On my setup Xen is 1448kb. Here you would increase ~9% of 
resident size. This seems quite steep for a feature that is not often used.

> 
> Maybe it is better to allocate this dynamically? I do understand that we
> want to get rid of as many dynamic allocs as possible, but maybe in this
> case it will be okay.

This is up to Leonid. I don't think this is strictly necessary in order 
to get the eSPI support. However, until this is solved CONFIG_GICV3_EPSI 
*must not* be on by default as this is done in this patch.

> As a bonus point, we can't leave this pointer
> present even if CONFIG_GICV3_ESPI=n, which will simplify some code in
> latter patches.

Did you intend to say "We can leave" rather than "we can't leave"?

Cheers,

-- 
Julien Grall



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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Index: AQHcB5d/vX6zkEc6YU++KKhW5OV9og==
Date: Thu, 21 Aug 2025 17:26:26 +0000
Message-ID: <87a53sd1ry.fsf@epam.com>
References:
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
	<3ba2381b4c782a5187161f9418e5a35e7916c752.1754568795.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <3ba2381b4c782a5187161f9418e5a35e7916c752.1754568795.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Thu, 7 Aug 2025 12:33:34 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> Implemented support for GICv3.1 extended SPI registers for vGICv3,
> allowing the emulation of eSPI-specific behavior for guest domains.
> The implementation includes read and write emulation for eSPI-related
> registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
> following a similar approach to the handling of regular SPIs.
>
> The eSPI registers, previously located in reserved address ranges,
> are now adjusted to support MMIO read and write operations correctly
> when CONFIG_GICV3_ESPI is enabled.
>
> The availability of eSPIs and the number of emulated extended SPIs
> for guest domains is reported by setting the appropriate bits in the
> GICD_TYPER register, based on the number of eSPIs requested by the
> domain and supported by the hardware. In cases where the configuration
> option is disabled, the hardware does not support eSPIs, or the domain
> does not request such interrupts, the functionality remains unchanged.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - add missing rank index conversion for pending and inflight irqs
> ---
>  xen/arch/arm/vgic-v3.c | 248 ++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 245 insertions(+), 3 deletions(-)
>
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index 4369c55177..1cacbb6e43 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -111,7 +111,7 @@ static uint64_t vgic_fetch_irouter(struct vgic_irq_ra=
nk *rank,
>   * Note the offset will be aligned to the appropriate boundary.
>   */
>  static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *r=
ank,
> -                               unsigned int offset, uint64_t irouter)
> +                               unsigned int offset, uint64_t irouter, bo=
ol espi)

I am wondering: maybe it is better to pass virq instead of offset into
this function? In that case you can get rid of espi parameter.

>  {
>      struct vcpu *new_vcpu, *old_vcpu;
>      unsigned int virq;
> @@ -123,7 +123,8 @@ static void vgic_store_irouter(struct domain *d, stru=
ct vgic_irq_rank *rank,
>       * The IROUTER0-31, used for SGIs/PPIs, are reserved and should
>       * never call this function.
>       */
> -    ASSERT(virq >=3D 32);
> +    if ( !espi )
> +        ASSERT(virq >=3D 32);

better to write
ASSERT (!espi & (virq>=3D32))

and probably you need symmetrical ASSERT for espi =3D=3D true

>      /* Get the index in the rank */
>      offset =3D virq & INTERRUPT_RANK_MASK;
> @@ -146,6 +147,11 @@ static void vgic_store_irouter(struct domain *d, str=
uct vgic_irq_rank *rank,
>      /* Only migrate the IRQ if the target vCPU has changed */
>      if ( new_vcpu !=3D old_vcpu )
>      {
> +#ifdef CONFIG_GICV3_ESPI
> +        /* Convert virq index to eSPI range */
> +        if ( espi )
> +            virq =3D ESPI_IDX2INTID(virq);
> +#endif

If you define ESPI_IDX2INTID() uncoditionally, you can get rid of #ifdef
CONFIG_GICV3_ESPI here

>          if ( vgic_migrate_irq(old_vcpu, new_vcpu, virq) )
>              write_atomic(&rank->vcpu[offset], new_vcpu->vcpu_id);
>      }
> @@ -685,6 +691,9 @@ static int __vgic_v3_distr_common_mmio_read(const cha=
r *name, struct vcpu *v,
>      {
>      case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>      case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +#ifdef CONFIG_GICV3_ESPI

Do you really need ifdef here?

> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +#endif


>          /* We do not implement security extensions for guests, read zero=
 */
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
>          goto read_as_zero;
> @@ -710,11 +719,19 @@ static int __vgic_v3_distr_common_mmio_read(const c=
har *name, struct vcpu *v,
>      /* Read the pending status of an IRQ via GICD/GICR is not supported =
*/
>      case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
>      case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
> +#ifdef CONFIG_GICV3_ESPI

Same as here

> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +#endif
>          goto read_as_zero;
> =20
>      /* Read the active status of an IRQ via GICD/GICR is not supported *=
/
>      case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
>      case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
> +#ifdef CONFIG_GICV3_ESPI

... and here and in all other places

> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +#endif
>          goto read_as_zero;
> =20
>      case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
> @@ -752,6 +769,61 @@ static int __vgic_v3_distr_common_mmio_read(const ch=
ar *name, struct vcpu *v,
>          return 1;
>      }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT=
_WORD);
> +        if ( rank =3D=3D NULL ) goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        *r =3D vreg_reg32_extract(rank->ienable, info);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT=
_WORD);
> +        if ( rank =3D=3D NULL ) goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        *r =3D vreg_reg32_extract(rank->ienable, info);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    {
> +        uint32_t ipriorityr;
> +        uint8_t rank_index;
> +
> +        if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD ) goto=
 bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DAB=
T_WORD);
> +        if ( rank =3D=3D NULL ) goto read_as_zero;
> +        rank_index =3D REG_RANK_INDEX(8, reg - GICD_IPRIORITYRnE, DABT_W=
ORD);
> +
> +        vgic_lock_rank(v, rank, flags);
> +        ipriorityr =3D ACCESS_ONCE(rank->ipriorityr[rank_index]);
> +        vgic_unlock_rank(v, rank, flags);
> +
> +        *r =3D vreg_reg32_extract(ipriorityr, info);
> +
> +        return 1;
> +    }
> +
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +    {
> +        uint32_t icfgr;
> +
> +        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WOR=
D);
> +        if ( rank =3D=3D NULL ) goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        icfgr =3D rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE, DABT_=
WORD)];
> +        vgic_unlock_rank(v, rank, flags);
> +
> +        *r =3D vreg_reg32_extract(icfgr, info);
> +
> +        return 1;
> +    }
> +#endif
> +
>      default:
>          printk(XENLOG_G_ERR
>                 "%pv: %s: unhandled read r%d offset %#08x\n",
> @@ -782,6 +854,9 @@ static int __vgic_v3_distr_common_mmio_write(const ch=
ar *name, struct vcpu *v,
>      {
>      case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>      case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +#endif
>          /* We do not implement security extensions for guests, write ign=
ore */
>          goto write_ignore_32;
> =20
> @@ -871,6 +946,87 @@ static int __vgic_v3_distr_common_mmio_write(const c=
har *name, struct vcpu *v,
>          vgic_unlock_rank(v, rank, flags);
>          return 1;
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT=
_WORD);
> +        if ( rank =3D=3D NULL ) goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        tr =3D rank->ienable;
> +        vreg_reg32_setbits(&rank->ienable, r, info);
> +        vgic_enable_irqs(v, (rank->ienable) & (~tr), EXT_RANK_IDX2NUM(ra=
nk->index));
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT=
_WORD);
> +        if ( rank =3D=3D NULL ) goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        tr =3D rank->ienable;
> +        vreg_reg32_clearbits(&rank->ienable, r, info);
> +        vgic_disable_irqs(v, (~rank->ienable) & tr, EXT_RANK_IDX2NUM(ran=
k->index));
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISPENDRnE, DABT_W=
ORD);
> +        if ( rank =3D=3D NULL ) goto write_ignore;
> +
> +        vgic_set_irqs_pending(v, r, EXT_RANK_IDX2NUM(rank->index));
> +
> +        return 1;
> +
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICPENDRnE, DABT_W=
ORD);
> +        if ( rank =3D=3D NULL ) goto write_ignore;
> +
> +        vgic_check_inflight_irqs_pending(v, EXT_RANK_IDX2NUM(rank->index=
), r);
> +
> +        goto write_ignore;
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> +        printk(XENLOG_G_ERR
> +               "%pv: %s: unhandled word write %#"PRIregister" to ISACTIV=
ER%d\n",
> +               v, name, r, reg - GICD_ISACTIVERnE);
> +        return 0;
> +
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +        printk(XENLOG_G_ERR
> +               "%pv: %s: unhandled word write %#"PRIregister" to ICACTIV=
ER%d\n",
> +               v, name, r, reg - GICD_ICACTIVER);
> +        goto write_ignore_32;
> +
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    {
> +        uint32_t *ipriorityr, priority;
> +
> +        if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD ) goto=
 bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DAB=
T_WORD);
> +        if ( rank =3D=3D NULL ) goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        ipriorityr =3D &rank->ipriorityr[REG_RANK_INDEX(8, reg - GICD_IP=
RIORITYRnE,
> +                                                      DABT_WORD)];
> +        priority =3D ACCESS_ONCE(*ipriorityr);
> +        vreg_reg32_update(&priority, r, info);
> +        ACCESS_ONCE(*ipriorityr) =3D priority;
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +    }
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +        if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WOR=
D);
> +        if ( rank =3D=3D NULL ) goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR=
nE,
> +                                                     DABT_WORD)],
> +                          r, info);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +#endif
> +
>      default:
>          printk(XENLOG_G_ERR
>                 "%pv: %s: unhandled write r%d=3D%"PRIregister" offset %#0=
8x\n",
> @@ -1129,6 +1285,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v,=
 mmio_info_t *info,
>              typer |=3D GICD_TYPE_LPIS;
> =20
>          typer |=3D (v->domain->arch.vgic.intid_bits - 1) << GICD_TYPE_ID=
_BITS_SHIFT;
> +#ifdef CONFIG_GICV3_ESPI
> +        if ( v->domain->arch.vgic.nr_espis > 0 )
> +        {
> +            /* Set eSPI support bit for the domain */
> +            typer |=3D GICD_TYPER_ESPI;
> +            /* Set ESPI range bits */
> +            typer |=3D (DIV_ROUND_UP(v->domain->arch.vgic.nr_espis, 32) =
- 1)
> +                       << GICD_TYPER_ESPI_RANGE_SHIFT;
> +        }
> +#endif
> =20
>          *r =3D vreg_reg32_extract(typer, info);
> =20
> @@ -1194,6 +1360,18 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v,=
 mmio_info_t *info,
>      case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
>      case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
>      case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +#endif
>          /*
>           * Above all register are common with GICR and GICD
>           * Manage in common
> @@ -1216,7 +1394,11 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v,=
 mmio_info_t *info,
>          /* Replaced with GICR_ISPENDR0. So ignore write */
>          goto read_as_zero_32;
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(0x3100, 0x60FC):
> +#else
>      case VRANGE32(0x0F30, 0x60FC):
> +#endif
>          goto read_reserved;
> =20
>      case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
> @@ -1235,8 +1417,30 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v,=
 mmio_info_t *info,
> =20
>          return 1;
>      }
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
> +    {
> +        uint64_t irouter;
> +
> +        if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 64, gicd_reg - GICD_IROUTERnE,
> +                                DABT_DOUBLE_WORD);
> +        if ( rank =3D=3D NULL ) goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTERnE);
> +        vgic_unlock_rank(v, rank, flags);
> +
> +        *r =3D vreg_reg64_extract(irouter, info);
> +
> +        return 1;
> +    }
> +#endif
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(0xA004, 0xBFFC):
> +#else
>      case VRANGE32(0x7FE0, 0xBFFC):
> +#endif
>          goto read_reserved;
> =20
>      case VRANGE32(0xC000, 0xFFCC):
> @@ -1382,6 +1586,18 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v=
, mmio_info_t *info,
>      case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
>      case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
>      case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +#endif
>          /* Above registers are common with GICR and GICD
>           * Manage in common */
>          return __vgic_v3_distr_common_mmio_write("vGICD", v, info,
> @@ -1405,7 +1621,11 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v=
, mmio_info_t *info,
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
>          return 0;
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(0x3100, 0x60FC):
> +#else
>      case VRANGE32(0x0F30, 0x60FC):
> +#endif
>          goto write_reserved;
> =20
>      case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
> @@ -1419,12 +1639,34 @@ static int vgic_v3_distr_mmio_write(struct vcpu *=
v, mmio_info_t *info,
>          vgic_lock_rank(v, rank, flags);
>          irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTER);
>          vreg_reg64_update(&irouter, r, info);
> -        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTER, iro=
uter);
> +        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTER, iro=
uter, false);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +    }
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
> +    {
> +        uint64_t irouter;
> +
> +        if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
> +        rank =3D vgic_ext_rank_offset(v, 64, gicd_reg - GICD_IROUTERnE,
> +                                DABT_DOUBLE_WORD);
> +        if ( rank =3D=3D NULL ) goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTERnE);
> +        vreg_reg64_update(&irouter, r, info);
> +        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTERnE, i=
router, true);
>          vgic_unlock_rank(v, rank, flags);
>          return 1;
>      }
> +#endif
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(0xA004, 0xBFFC):
> +#else
>      case VRANGE32(0x7FE0, 0xBFFC):
> +#endif
>          goto write_reserved;
> =20
>      case VRANGE32(0xC000, 0xFFCC):

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Julien Grall 
CC: Leonid Komarianskyi ,
	"xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Topic: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcB5d7kgaRrTB4eUK2JDUmO9y7Hw==
Date: Thu, 21 Aug 2025 17:38:52 +0000
Message-ID: <874iu0d178.fsf@epam.com>
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In-Reply-To: <20328499-772c-4b32-815e-7527aa6b2cc7@xen.org> (Julien Grall's
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Julien Grall  writes:

> On 21/08/2025 17:59, Volodymyr Babchuk wrote:
>> Julien Grall  writes:
>>=20
>>> Hi,
>>>
>>> On 21/08/2025 16:59, Volodymyr Babchuk wrote:
>>>> Leonid Komarianskyi  writes:
>>>>
>>>>> Currently, Xen does not support eSPI interrupts, leading
>>>>> to a data abort when such interrupts are defined in the DTS.
>>>>>
>>>>> This patch introduces a separate array to initialize up to
>>>>> 1024 interrupt descriptors in the eSPI range and adds the
>>>>> necessary defines and helper function. These changes lay the
>>>>> groundwork for future implementation of full eSPI interrupt
>>>>> support. As this GICv3.1 feature is not required by all vendors,
>>>>> all changes are guarded by ifdefs, depending on the corresponding
>>>>> Kconfig option.
>>>> I don't think that it is a good idea to hide this feature under
>>>> Kconfig
>>>> option, as this will increase number of different build variants.
>>>> I believe that runtime check for GICD_TYPER.ESPI should be
>>>    sufficient,> but maintainers can correct me there.
>>>
>>> I haven't seen many board with ESPI available. So I think it would be
>>> better if this is under a Kconfig because not everyone may want to
>>> have the code.
>> Probably, we can expect more in the future...
>
> Well yes. But I was under the impression this the preferred
> approach. See the discussion about disabling 32-bit support on 64-bit:
>
> 20250723075835.3993182-1-grygorii_strashko@epam.com

Ah yes, safety certification. Welp, can't argue with that.

>
>>  Anyways, after reviewing
>> all patches in the series, I can see that code will be littered with
>> #ifdef CONFIG_GICV3_ESPI, which, probably, not a good thing.
>
> The solution is to provide wrappers to reduce the number of #ifdef. I
> haven't checked all the places.

Yes, I was also thinking about that, but I got an impression, that in
many cases it will be hard to provide such wrappers. Anyways, something
is needs to be done here.

[...]


>
>> As a bonus point, we can't leave this pointer
>> present even if CONFIG_GICV3_ESPI=3Dn, which will simplify some code in
>> latter patches.
>
> Did you intend to say "We can leave" rather than "we can't leave"?

Correct

--=20
WBR, Volodymyr=


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To: Jan Beulich 
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 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 19/08/2025 1:38 pm, Jan Beulich wrote:
> On 15.08.2025 22:41, Andrew Cooper wrote:
>> --- a/xen/arch/x86/nmi.c
>> +++ b/xen/arch/x86/nmi.c
>> @@ -218,16 +218,16 @@ void disable_lapic_nmi_watchdog(void)
>>          return;
>>      switch (boot_cpu_data.x86_vendor) {
>>      case X86_VENDOR_AMD:
>> -        wrmsr(MSR_K7_EVNTSEL0, 0, 0);
>> +        wrmsrns(MSR_K7_EVNTSEL0, 0);
> Since you switch to non-serializing here, ...
>
>> @@ -308,11 +308,11 @@ static void setup_k7_watchdog(void)
>>          | K7_EVNTSEL_USR
>>          | K7_NMI_EVENT;
>>  
>> -    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
>> +    wrmsr(MSR_K7_EVNTSEL0, evntsel);
>>      write_watchdog_counter("K7_PERFCTR0");
>>      apic_write(APIC_LVTPC, APIC_DM_NMI);
>>      evntsel |= K7_EVNTSEL_ENABLE;
>> -    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
>> +    wrmsr(MSR_K7_EVNTSEL0, evntsel);
>>  }
> ... why not also here?

An oversight.  Fixed.

>
>> --- a/xen/arch/x86/oprofile/op_model_athlon.c
>> +++ b/xen/arch/x86/oprofile/op_model_athlon.c
>> @@ -34,7 +34,7 @@
>>  #define MAX_COUNTERS FAM15H_NUM_COUNTERS
>>  
>>  #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, (msr_content));} while (0)
>> -#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1);} while (0)
>> +#define CTR_WRITE(l,msrs,c) do { wrmsr(msrs->counters[(c)].addr, -l); } while (0)
> This isn't obviously correct (as in: no functional change): The macro is,
> for example, passed reset_value[] contents, which is of type unsigned long.
> Quite possible that the original code was wrong, though.

I'm pretty sure the change is correct.

Perf counters get programmed to -(count), as they generate an interrupt
when they overflow.  The K8 is the oldest BKDG I can easily access, and
the counters are 48 bits wide.  The same is true of Intel systems of of
the same age.

Interestingly, it is the singular omission from b5103d692aa7 which
converts everything including the Intel version of CTR_WRITE() of this
to use wrmsrl().

While looking at the mail list archives for b5103d692aa7, I found
https://lists.xenproject.org/archives/html/xen-devel/2010-06/msg01660.html
which shows that it was Christoph's attempt to turn rdmsr() and wrmsr()
into a real C functions, so I'm pretty certain that CTR_WRITE() was an
omission in b5103d692aa7.

Only 15 years late on that todo...

> In any event l wants parenthesizing.

Oh, so it does.  Fixed.

~Andrew


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On 19/08/2025 1:55 pm, Jan Beulich wrote:
> On 15.08.2025 22:41, Andrew Cooper wrote:
>> Most MSR accesses have compile time constant indexes.  By using the immediate
>> form when available, the decoder can start issuing uops directly for the
>> relevant MSR, rather than having to issue uops to implement "switch (%ecx)".
>> Modern CPUs have tens of thousands of MSRs, so that's quite an if/else chain.
>>
>> Create __{rdmsr,wrmsrns}_imm() helpers and use them from {rdmsr,wrmsrns}()
>> when the compiler can determine that the msr index is known at compile time.
>>
>> At the instruction level, the combined ABI is awkward.  Explain our choices in
>> detail.
>>
>> Signed-off-by: Andrew Cooper 
>> ---
>> CC: Jan Beulich 
>> CC: Roger Pau Monné 
>>
>> The expression wrmsrns(MSR_STAR, rdmsr(MSR_STAR)) now yields:
>>
>>   :
>>       b9 81 00 00 c0          mov    $0xc0000081,%ecx
>>       0f 32                   rdmsr
>>       48 c1 e2 20             shl    $0x20,%rdx
>>       48 09 d0                or     %rdx,%rax
>>       48 89 c2                mov    %rax,%rdx
>>       48 c1 ea 20             shr    $0x20,%rdx
>>       2e 0f 30                cs wrmsr
>>       e9 a3 84 e8 ff          jmp    ffff82d040204260 <__x86_return_thunk>
>>
>> which is as good as we can manage.  The alternative form of this looks like:
>>
>>   :
>>       b9 81 00 00 c0          mov    $0xc0000081,%ecx
>>       c4 e7 7b f6 c0 81 00    rdmsr  $0xc0000081,%rax
>>       00 c0
>>       2e c4 e7 7a f6 c0 81    cs wrmsrns %rax,$0xc0000081
>>       00 00 c0
>>       e9 xx xx xx xx          jmp    ffff82d040204260 <__x86_return_thunk>
>>
>> Still TBD.  We ought to update the *_safe() forms too.  rdmsr_safe() is easier
>> because the potential #GP locations line up, but there need to be two variants
>> because of
> Because of ...?

Oh.  I guess I didn't finish that.  Because of asm goto with outputs.

The WRMSR side is harder because there are two different fault locations.

>
>> --- a/xen/arch/x86/include/asm/alternative.h
>> +++ b/xen/arch/x86/include/asm/alternative.h
>> @@ -151,6 +151,13 @@ extern void alternative_instructions(void);
>>          ALTERNATIVE(oldinstr, newinstr, feature)                        \
>>          :: input )
>>  
>> +#define alternative_input_2(oldinstr, newinstr1, feature1,              \
>> +                            newinstr2, feature2, input...)              \
>> +    asm_inline volatile (                                               \
>> +        ALTERNATIVE_2(oldinstr, newinstr1, feature1,                    \
>> +                      newinstr2, feature2)                              \
>> +        :: input )
>> +
>>  /* Like alternative_input, but with a single output argument */
>>  #define alternative_io(oldinstr, newinstr, feature, output, input...)   \
>>      asm_inline volatile (                                               \
>> diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h
>> index 1bd27b989a4d..2ceff6cca8bb 100644
>> --- a/xen/arch/x86/include/asm/msr.h
>> +++ b/xen/arch/x86/include/asm/msr.h
>> @@ -29,10 +29,52 @@
>>   *  wrmsrl(MSR_FOO, val);
>>   */
>>  
>> -static inline uint64_t rdmsr(unsigned int msr)
>> +/*
>> + * RDMSR with a compile-time constant index, when available.  Falls back to
>> + * plain RDMSR.
>> + */
>> +static always_inline uint64_t __rdmsr_imm(uint32_t msr)
>> +{
>> +    uint64_t val;
>> +
>> +    /*
>> +     * For best performance, RDMSR $msr, %r64 is recommended.  For
>> +     * compatibility, we need to fall back to plain RDMSR.
>> +     *
>> +     * The combined ABI is awkward, because RDMSR $imm produces an r64,
>> +     * whereas WRMSR{,NS} produces a split edx:eax pair.
>> +     *
>> +     * Always use RDMSR $imm, %rax, because it has the most in common with the
>> +     * legacy form.  When MSR_IMM isn't available, emit logic to fold %edx
>> +     * back into %rax.
>> +     *
>> +     * Let the compiler do %ecx setup.  This does mean there's a useless `mov
>> +     * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it means
>> +     * the compiler can de-duplicate the setup in the common case of reading
>> +     * and writing the same MSR.
>> +     */
>> +    alternative_io(
>> +        "rdmsr\n\t"
>> +        "shl $32, %%rdx\n\t"
>> +        "or %%rdx, %%rax\n\t",
>> +
>> +        /* RDMSR $msr, %rax */
>> +        ".byte 0xc4,0xe7,0x7b,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
>> +
>> +        "=a" (val),
> Strictly speaking "=&a". Not that it matters much here; just to not
> set a bad precedent.

Why?  A is not written to until after all inputs are consumed.

I don't see how it can qualify for being early-clobber.

>
>> @@ -55,11 +97,51 @@ static inline void wrmsr(unsigned int msr, uint64_t val)
>>  }
>>  #define wrmsrl(msr, val) wrmsr(msr, val)
>>  
>> +/*
>> + * Non-serialising WRMSR with a compile-time constant index, when available.
>> + * Falls back to plain WRMSRNS, or to a serialising WRMSR.
>> + */
>> +static always_inline void __wrmsrns_imm(uint32_t msr, uint64_t val)
>> +{
>> +    /*
>> +     * For best performance, WRMSRNS %r64, $msr is recommended.  For
>> +     * compatibility, we need to fall back to plain WRMSRNS, or to WRMSR.
>> +     *
>> +     * The combined ABI is awkward, because WRMSRNS $imm takes a single r64,
>> +     * whereas WRMSR{,NS} takes a split edx:eax pair.
>> +     *
>> +     * Always use WRMSRNS %rax, $imm, because it has the most in common with
>> +     * the legacy forms.  When MSR_IMM isn't available, emit setup logic for
>> +     * %edx.
>> +     *
>> +     * Let the compiler do %ecx setup.  This does mean there's a useless `mov
>> +     * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it means
>> +     * the compiler can de-duplicate the setup in the common case of reading
>> +     * and writing the same MSR.
>> +     */
>> +    alternative_input_2(
>> +        "mov %%rax, %%rdx\n\t"
>> +        "shr $32, %%rdx\n\t"
>> +        ".byte 0x2e; wrmsr",
>> +
>> +        /* CS WRMSRNS %rax, $msr */
>> +        ".byte 0x2e,0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
>> +
>> +        "mov %%rax, %%rdx\n\t"
>> +        "shr $32, %%rdx\n\t"
>> +        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
> Isn't this the wrong way round for hardware which has both features? The
> last active alternative wins, iirc.

Bah - fooled once again by the nop optimisation.  I'll reorder.

But, we really should swap the order.  Especially now that you've
inserted serialisation, it's an expensive waste of time patching the
same site multiple times.

~Andrew


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On 8/21/2025 6:15 AM, David Woodhouse wrote:

> Hm. My test host is INTEL_HASWELL_X (0x63f). For reasons which are
> unclear to me, QEMU doesn't set bit 8 of 0x80000007 EDX unless I
> explicitly append ',+invtsc' to the existing '-cpu host' on its command
> line. So now my guest doesn't think it has X86_FEATURE_CONSTANT_TSC.
> 

Haswell should have X86_FEATURE_CONSTANT_TSC, so I would have expected
the guest bit to be set. Until now, X86_FEATURE_CONSTANT_TSC was set
based on the Family-model instead of the CPUID enumeration which may
have hid the issue.

>From my initial look at the QEMU implementation, this seems intentional.

QEMU considers Invariant TSC as un-migratable which prevents it from
being exposed to migratable guests (default).
target/i386/cpu.c:
[FEAT_8000_0007_EDX]
         .unmigratable_flags = CPUID_APM_INVTSC,

Can you please try '-cpu host,migratable=off'?


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To: David Woodhouse , , Dave Hansen
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CC: Peter Zijlstra , Ingo Molnar ,
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References: <20250219184133.816753-1-sohil.mehta@intel.com>
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On 8/21/2025 12:34 PM, Sohil Mehta wrote:
> On 8/21/2025 6:15 AM, David Woodhouse wrote:
> 
>> Hm. My test host is INTEL_HASWELL_X (0x63f). For reasons which are
>> unclear to me, QEMU doesn't set bit 8 of 0x80000007 EDX unless I
>> explicitly append ',+invtsc' to the existing '-cpu host' on its command
>> line. So now my guest doesn't think it has X86_FEATURE_CONSTANT_TSC.
>>
> 
> Haswell should have X86_FEATURE_CONSTANT_TSC, so I would have expected
> the guest bit to be set. Until now, X86_FEATURE_CONSTANT_TSC was set
> based on the Family-model instead of the CPUID enumeration which may
> have hid the issue.
> 

Correction:
s/instead/as well as

> From my initial look at the QEMU implementation, this seems intentional.
> 
> QEMU considers Invariant TSC as un-migratable which prevents it from
> being exposed to migratable guests (default).
> target/i386/cpu.c:
> [FEAT_8000_0007_EDX]
>          .unmigratable_flags = CPUID_APM_INVTSC,
> 
> Can you please try '-cpu host,migratable=off'?

This is mainly to verify. If confirmed, I am not sure what the long term
solution should be.


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Subject: Re: [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural
 constant_tsc model checks
From: David Woodhouse 
To: Sohil Mehta , x86@kernel.org, Dave Hansen
	 , Tony Luck , 
 =?ISO-8859-1?Q?J=FCrgen?= Gross
	 , Boris Ostrovsky , xen-devel
	 
Cc: Peter Zijlstra , Ingo Molnar , 
 Arnaldo Carvalho de Melo , Namhyung Kim
 , Mark Rutland , Alexander
 Shishkin ,  Jiri Olsa
 , Ian Rogers , Adrian Hunter
 ,  Kan Liang , Thomas
 Gleixner , Borislav Petkov , "H . Peter
 Anvin" , "Rafael J . Wysocki" , Len Brown
 , Andy Lutomirski , Viresh Kumar
 , Jean Delvare , Guenter Roeck
 , Zhang Rui , Andrew Cooper
 , David Laight ,
 Dapeng Mi ,  linux-perf-users@vger.kernel.org,
 linux-kernel@vger.kernel.org,  linux-acpi@vger.kernel.org,
 linux-pm@vger.kernel.org, kvm@vger.kernel.org,  xiaoyao.li@intel.com, Xin
 Li 
Date: Thu, 21 Aug 2025 21:09:16 +0100
In-Reply-To: <5f5f1230-f373-469c-b0d9-abc80199886e@intel.com>
References: <20250219184133.816753-1-sohil.mehta@intel.com>
	 <20250219184133.816753-14-sohil.mehta@intel.com>
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On Thu, 2025-08-21 at 12:43 -0700, Sohil Mehta wrote:
> On 8/21/2025 12:34 PM, Sohil Mehta wrote:
> > On 8/21/2025 6:15 AM, David Woodhouse wrote:
> >=20
> > > Hm. My test host is INTEL_HASWELL_X (0x63f). For reasons which are
> > > unclear to me, QEMU doesn't set bit 8 of 0x80000007 EDX unless I
> > > explicitly append ',+invtsc' to the existing '-cpu host' on its comma=
nd
> > > line. So now my guest doesn't think it has X86_FEATURE_CONSTANT_TSC.
> > >=20
> >=20
> > Haswell should have X86_FEATURE_CONSTANT_TSC, so I would have expected
> > the guest bit to be set. Until now, X86_FEATURE_CONSTANT_TSC was set
> > based on the Family-model instead of the CPUID enumeration which may
> > have hid the issue.
> >=20
>=20
> Correction:
> s/instead/as well as
>=20
> > From my initial look at the QEMU implementation, this seems intentional=
.
> >=20
> > QEMU considers Invariant TSC as un-migratable which prevents it from
> > being exposed to migratable guests (default).
> > target/i386/cpu.c:
> > [FEAT_8000_0007_EDX]
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .unmigratable_flags =
=3D CPUID_APM_INVTSC,
> >=20
> > Can you please try '-cpu host,migratable=3Doff'?
>=20
> This is mainly to verify. If confirmed, I am not sure what the long term
> solution should be.

Yes, explicitly turning it on with -cpu host,+invtsc does work.

I've been looking into why it takes a Xen guest four seconds per vCPU
in this case, but not a KVM guest.

When running as a KVM guest, Linux will infer the TSC frequency from
the KVM clock =E2=80=94 or better still, from CPUID; see
https://lore.kernel.org/all/20250816101308.2594298-1-dwmw2@infradead.org
and/or
https://lore.kernel.org/all/20250227021855.3257188-36-seanjc@google.com

As a Xen guest though, Linux doesn't do that. This patch in the guest
should make it work without recalibrating the TSC for each vCPU...

--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -489,7 +489,15 @@ static void xen_setup_vsyscall_time_info(void)
  */
 static int __init xen_tsc_safe_clocksource(void)
 {
-       u32 eax, ebx, ecx, edx;
+       u32 eax, ebx, ecx, edx;
+       u64 lpj;
+
+       /* Leaf 4, sub-leaf 0 (0x40000x03) */
+       cpuid_count(xen_cpuid_base() + 3, 0, &eax, &ebx, &ecx, &edx);
+
+       lpj =3D ((u64)ecx * 1000);
+       do_div(lpj, HZ);
+       preset_lpj =3D lpj;
=20
        if (!(boot_cpu_has(X86_FEATURE_CONSTANT_TSC)))
                return 0;
@@ -500,9 +508,6 @@ static int __init xen_tsc_safe_clocksource(void)
        if (check_tsc_unstable())
                return 0;
=20
-       /* Leaf 4, sub-leaf 0 (0x40000x03) */
-       cpuid_count(xen_cpuid_base() + 3, 0, &eax, &ebx, &ecx, &edx);
-
        return ebx =3D=3D XEN_CPUID_TSC_MODE_NEVER_EMULATE;
 }
=20

... but then I got slightly distracted by the question of why I was
getting *nonsense* in those values, and why KVM is 'correcting' EAX in
subleaf 2 which is supposed to be the *host* TSC, not ECX in subleaf
zero...

Under the Fedora 6.13.8-200 kernel I'm fairly sure the guest was seeing
values in subleaf 0 ECX/EDX that *should* have been in subleaf 1
ECX/EDX, and that problem went away when I rebooted the host into a
mainline kernel. Will have to go back and retest that part...

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Subject: Re: [PATCH v2 14/16] x86/fsgsbase: Split out __{rd,wr}gskern()
 helpers
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 19/08/2025 2:01 pm, Jan Beulich wrote:
> On 15.08.2025 22:41, Andrew Cooper wrote:
>> Right now they're inline in {read,write}_gs_shadow(), but we're going to need
>> to use these elsewhere to support FRED.
> But why "kern"? We're not dealing with GS in kernel / user terms, but in
> real / shadow ones.

Because it's a common name that also has the property of aligning nicely
when used beside GS_BASE.

But fine, I'll rename it.

>  I'm also not quite happy with the double leading
> underscores, fwiw.

Consistency with the similar logic.

>
>> --- a/xen/arch/x86/include/asm/fsgsbase.h
>> +++ b/xen/arch/x86/include/asm/fsgsbase.h
>> @@ -32,6 +32,17 @@ static inline unsigned long __rdgsbase(void)
>>      return base;
>>  }
>>  
>> +static inline unsigned long __rdgskern(void)
>> +{
>> +    unsigned long base;
>> +
>> +    asm_inline volatile ( "swapgs\n\t"
>> +                          "rdgsbase %0\n\t"
>> +                          "swapgs" : "=r" (base) );
> Again strictly speaking "=&r", if already you open-code rdgsbase() now.

As before, why?   There are no inputs to be clobbered, early or otherwise.

~Andrew


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Subject: Re: [PATCH v2 15/16] x86/fsgsbase: Update fs/gs helpers to use
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To: Jan Beulich 
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 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 19/08/2025 2:09 pm, Jan Beulich wrote:
> On 15.08.2025 22:41, Andrew Cooper wrote:
>> --- a/xen/arch/x86/hvm/vmx/vmx.c
>> +++ b/xen/arch/x86/hvm/vmx/vmx.c
>> @@ -2733,8 +2733,8 @@ static uint64_t cf_check vmx_get_reg(struct vcpu *v, unsigned int reg)
>>      case MSR_SHADOW_GS_BASE:
>>          if ( v != curr )
>>              return v->arch.hvm.vmx.shadow_gs;
>> -        rdmsrl(MSR_SHADOW_GS_BASE, val);
>> -        return val;
>> +        else
>> +            return rdmsr(MSR_SHADOW_GS_BASE);
>>      }
> Here and below, can we please do without the pointless "else"? Strictly
> speaking in Misra's terms that's "dead code" (things working identically
> without), and I'm quite happy that I can now use this argument to
> support my personal antipathy to this style of coding. Or else use the
> conditional operator in such cases (where applicable).

No.  I have always, and will always prioritise readability first and
foremost.

I do not agree with your interpretation of MISRA in this case.

~Andrew


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Subject: Re: [PATCH v2 16/16] x86/fsgsbase: Improve code generation in
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To: Jan Beulich 
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 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 19/08/2025 2:19 pm, Jan Beulich wrote:
> On 15.08.2025 22:41, Andrew Cooper wrote:
>> It turns out that using the higher level helpers adjacent like this leads to
>> terrible code generation.  Due to -fno-strict-alising, the store into state->
>> invalidates the read_cr4() address calculation (which is really cpu_info->cr4
>> under the hood), meaning that it can't be hoisted.
>>
>> As a result we get "locate the top of stack block, get cr4, and see if
>> FSGSBASE is set" repeated 3 times, and an unreasoanble number of basic blocks.
>>
>> Hoist the calculation manually, which results in two basic blocks.
>>
>> Signed-off-by: Andrew Cooper 
> Otoh the function here isn't really performance or size critical. I'm undecided
> whether the undesirable open-coding or the bad code gen are the lesser evil.

This function no, but every other place touching FS and GS is
performance critical.  They're all messy to start with, and get worse
under FRED.

~Andrew


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Subject: Re: [PATCH 13/22] x86: FRED enumerations
To: Jan Beulich 
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 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 14/08/2025 12:20 pm, Jan Beulich wrote:
> On 08.08.2025 22:23, Andrew Cooper wrote:
>> Of note, CR4.FRED is bit 32 and cannot enabled outside of 64bit mode.
>>
>> Most supported toolchains don't understand the FRED instructions yet.  ERETU
>> and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC), while LKGS is
>> more complicated and deferred for now.
>>
>> I have intentionally named the FRED MSRs differently to the spec.  In the
>> spec, the stack pointer names alias the TSS fields of the same name, despite
>> very different semantics.
>>
>> Signed-off-by: Andrew Cooper 
> Acked-by: Jan Beulich 
> with ...
>
>> --- a/xen/arch/x86/Kconfig
>> +++ b/xen/arch/x86/Kconfig
>> @@ -57,6 +57,10 @@ config HAS_CC_CET_IBT
>>  	# Retpoline check to work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654
>>  	def_bool $(cc-option,-fcf-protection=branch -mmanual-endbr -mindirect-branch=thunk-extern) && $(as-instr,endbr64)
>>  
>> +config HAS_AS_FRED
>> +	# binutils >= 2.41 or LLVM >= 19
>> +	def_bool $(as-instr,eretu;lkgs %ax)
> ..., as per your reply, this preferably dropped

Having now got the PV side complete (I think), I can indeed drop this,
but I need

diff --git a/xen/arch/x86/include/asm/cpufeatures.h b/xen/arch/x86/include/asm/cpufeatures.h
index 71308d9dafc8..0a98676c1604 100644
--- a/xen/arch/x86/include/asm/cpufeatures.h
+++ b/xen/arch/x86/include/asm/cpufeatures.h
@@ -18,7 +18,7 @@ XEN_CPUFEATURE(ARCH_PERFMON,      X86_SYNTH( 3)) /* Intel Architectural PerfMon
 XEN_CPUFEATURE(TSC_RELIABLE,      X86_SYNTH( 4)) /* TSC is known to be reliable */
 XEN_CPUFEATURE(XTOPOLOGY,         X86_SYNTH( 5)) /* cpu topology enum extensions */
 XEN_CPUFEATURE(CPUID_FAULTING,    X86_SYNTH( 6)) /* cpuid faulting */
-/* Bit 7 unused */
+XEN_CPUFEATURE(XEN_FRED,          X86_SYNTH( 7)) /* Xen uses FRED */
 XEN_CPUFEATURE(APERFMPERF,        X86_SYNTH( 8)) /* APERFMPERF */
 XEN_CPUFEATURE(MFENCE_RDTSC,      X86_SYNTH( 9)) /* MFENCE synchronizes RDTSC */
 XEN_CPUFEATURE(XEN_SMEP,          X86_SYNTH(10)) /* SMEP gets used by Xen itself */


too for a fastpath in assembly.  I've folded it into this patch.

~Andrew


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Date: Thu, 21 Aug 2025 14:45:51 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Jan Beulich 
cc: Mykyta Poturai , 
    Stefano Stabellini , Julien Grall , 
    Bertrand Marquis , 
    Michal Orzel , 
    Volodymyr Babchuk , 
    "xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH v2] iommu/ipmmu-vmsa: Fix build with HAS_PCI=n
In-Reply-To: <267bd33a-70d4-417f-b26f-32de863f1d2d@suse.com>
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On Thu, 21 Aug 2025, Jan Beulich wrote:
> On 21.08.2025 13:23, Mykyta Poturai wrote:
> > With PCI disabled the build fails due to undefined struct
> > pci_host_bridge.
> > 
> > Add ifdef guard to pci-host-rcar4.h to not require the stuct being
> > defined when PCI support is disabled. All call sites are already covered
> > by HAS_PCI check, so no dummy implementations are needed.
> > 
> > Also move includes under the header guard to not break MISRA rules.
> > 
> > Reported-by: Jan Beulich 
> > Signed-off-by: Mykyta Poturai 
> 
> Along with the Reported-by I thought a Fixes: tag would go without saying.
> Can likely be added while committing.

I added Fixes and my Reviewed-by


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Subject: Re: [PATCH 15/22] x86/traps: Introduce opt_fred
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On 15/08/2025 9:37 am, Jan Beulich wrote:
> On 14.08.2025 21:16, Andrew Cooper wrote:
>> On 14/08/2025 2:30 pm, Jan Beulich wrote:
>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>> ... disabled by default.  There is a lot of work before FRED can be enabled by
>>>> default.
>>>>
>>>> One part of FRED, the LKGS (Load Kernel GS) instruction, is enumerated
>>>> separately but is mandatory as FRED disallows the SWAPGS instruction.
>>>> Therefore, both CPUID bits must be checked.
>>> See my (further) reply to patch 13 - I think FRED simply ought to depend on
>>> LKGS.
>>>
>>>> @@ -20,6 +22,9 @@ unsigned int __ro_after_init ler_msr;
>>>>  static bool __initdata opt_ler;
>>>>  boolean_param("ler", opt_ler);
>>>>  
>>>> +int8_t __ro_after_init opt_fred = 0; /* -1 when supported. */
>>> I'm a little puzzled by the comment? DYM "once default-enabled"?
>> Well, I have this temporary patch
>> https://gitlab.com/xen-project/hardware/xen-staging/-/commit/70ef6a1178a411a29b7b1745a1112e267ffb6245
>> that will turn into a real patch when we enable FRED by default.
>>
>> As much as anything else, it was just a TODO.
>>
>>
>>>  Then ...
>>>
>>>> @@ -305,6 +310,32 @@ void __init traps_init(void)
>>>>      /* Replace early pagefault with real pagefault handler. */
>>>>      _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF);
>>>>  
>>>> +    if ( !cpu_has_fred || !cpu_has_lkgs )
>>>> +    {
>>>> +        if ( opt_fred )
>>> ... this won't work anymore once the initializer is changed.
>> Hmm yes.  That wants to be an == 1 check.  Fixed.
>>
>>>> +            printk(XENLOG_WARNING "FRED not available, ignoring\n");
>>>> +        opt_fred = false;
>>> Better use 0 here?
>>>
>>>> +    }
>>>> +
>>>> +    if ( opt_fred == -1 )
>>>> +        opt_fred = !pv_shim;
>>> Imo it would be better to have the initializer be -1 right away, and comment
>>> out the "!pv_shim" here, until we mean it to be default-enabled.
>> It cannot be -1, or Xen will fail spectacularly on any FRED capable
>> hardware.  Setting to -1 is the point at which FRED becomes security
>> supported.
> I guess I'm not following: If it was -1, and if the code here was
>
>     if ( opt_fred < 0 )
>         opt_fred = 0 /* !pv_shim */;
>
> why would things "fail spectacularly" unless someone passed "fred" on
> the command line?

Oh, that would work, but why bother?  It's simply a less readable form
of mine, and if we're going to nitpick, it's commented out code.

~Andrew


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Subject: Re: [PATCH 19/22] x86/boot: Use RSTORSSP to establish SSP
To: Jan Beulich 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
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On 15/08/2025 10:03 am, Jan Beulich wrote:
> On 14.08.2025 22:09, Andrew Cooper wrote:
>> On 14/08/2025 4:11 pm, Jan Beulich wrote:
>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>> Under FRED, SETSSBSY is unavailable, and we want to be setting up FRED prior
>>>> to setting up shadow stacks.  As we still need Supervisor Tokens in IDT mode,
>>>> we need mode-specific logic to establish SSP.
>>>>
>>>> In FRED mode, write a Restore Token, RSTORSSP it, and discard the resulting
>>>> Previous-SSP token.
>>>>
>>>> No change outside of FRED mode.
>>>>
>>>> Signed-off-by: Andrew Cooper 
>>> Why is it that in patch 17 you could use identical code, but here you can't?
>> This caught me out at first too.
>>
>> For S3, we're going from "no shadow stack" to "back to where we were on
>> an active shadow stack".  All we need to do is get saved_ssp back into
>> the SSP register.
>>
>> Here, we're going from "no shadow stack" to "on a good, empty, shadow
>> stack".  For FRED we only need to load a value into SSP, but in IDT mode
>> we must also arrange to create a busy Supervisor Token on the base of
>> the stack.
>>
>> We could in principle conditionally write a busy supervisor token, then
>> unconditionally RSTORSSP, but that's even more complicated to follow IMO.
> Why would the write need to be conditional?

Because the tokens are different.  One has the value &addr, and one has
&addr + 9.

The Supervisor Shadow Stack Token for IDT needs to survive for the
lifetime of Xen, while the Restore Token for FRED is temporary and
discarded by the logic added in this patch.

>  Can't we write what effectively
> is already there? Or is it more a safety measure to avoid the write when
> it's supposed to be unnecessary, to avoid papering over bugs?

I genuinely don't understand what you're trying to suggest here.

~Andrew


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On 15/08/2025 10:10 am, Jan Beulich wrote:
> On 14.08.2025 22:55, Andrew Cooper wrote:
>> On 14/08/2025 4:35 pm, Jan Beulich wrote:
>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>> FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
>>>> means that switch_stack_and_jump() needs to discard one extra word when FRED
>>>> is active.
>>>>
>>>> Signed-off-by: Andrew Cooper 
>>>> ---
>>>> CC: Jan Beulich 
>>>> CC: Roger Pau Monné 
>>>>
>>>> RFC.  I don't like this, but it does work.
>>>>
>>>> This emits opt_fred logic outside of CONFIG_XEN_SHSTK.
>>> opt_fred and XEN_SHSTK are orthogonal, so that's fine anyway. What I guess
>>> you may mean is that you now have a shstk-related calculation outside of
>>> a respective #ifdef.
>> I really mean "outside of the path where shadow stacks are known to be
>> active", i.e. inside the middle of SHADOW_STACK_WORK
>>
>>>  Given the simplicity of the calculation, ...
>>>
>>>>  But frankly, the
>>>> construct is already too unweildly, and all options I can think of make it
>>>> moreso.
>>> ... I agree having it like this is okay.
>> Yes, but it is a read of a global even when it's not used.
>>
>> And as a tangent, we probably want __ro_after_init_read_mostly too.  The
>> read mostly is about cache locality, and is applicable even to the
>> __ro_after_init section.
> Not really: __read_mostly is to keep stuff rarely written apart from stuff
> more frequently written (cache locality, yes). There's not going to be any
> frequently written data next to a __ro_after_init item; it's all r/o post-
> boot. And I don't think we care much during boot.

It's not about boot, but hot variables do need grouping.  opt_fred is
read on fastpaths, whereas trampoline_phys is not.

>
>>>> @@ -154,7 +155,6 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>>>      "rdsspd %[ssp];"                                            \
>>>>      "cmp $1, %[ssp];"                                           \
>>>>      "je .L_shstk_done.%=;" /* CET not active?  Skip. */         \
>>>> -    "mov $%c[skstk_base], %[val];"                              \
>>>>      "and $%c[stack_mask], %[ssp];"                              \
>>>>      "sub %[ssp], %[val];"                                       \
>>>>      "shr $3, %[val];"                                           \
>>> With the latter two insns here, ...
>>>
>>>> @@ -177,6 +177,8 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>>>  
>>>>  #define switch_stack_and_jump(fn, instr, constr)                        \
>>>>      ({                                                                  \
>>>> +        unsigned int token_offset =                                     \
>>>> +            (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - (opt_fred ? 0 : 8);  \
>>>>          unsigned int tmp;                                               \
>>>>          BUILD_BUG_ON(!ssaj_has_attr_noreturn(fn));                      \
>>>>          __asm__ __volatile__ (                                          \
>>>> @@ -184,12 +186,11 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>>>              "mov %[stk], %%rsp;"                                        \
>>>>              CHECK_FOR_LIVEPATCH_WORK                                    \
>>>>              instr "[fun]"                                               \
>>>> -            : [val] "=&r" (tmp),                                        \
>>>> +            : [val] "=r" (tmp),                                         \
>>> ... I don't think you can legitimately drop the & from here? With it
>>> retained:
>>> Reviewed-by: Jan Beulich 
>> You chopped the bit which has an explicit input for "[val]", making the
>> earlyclobber incorrect.
> I was wondering whether there was a connection there, but ...
>
>> IIRC, one version of Clang complained.
> ... that's not good. Without the early-clobber the asm() isn't quite
> correct imo. If the same value appeared as another input, the compiler
> may validly tie both together, assuming the register stays intact until
> the very last insn (and hence even that last insn could still use the
> register as an input). IOW if there's a Clang issue here, I think it
> may need working around explicitly.

Given that I need an alternative anyway, this becomes much easier, and
shrinks to this single hunk:

diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index c1eb27b1c4c2..35cc61fa88e7 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -154,7 +154,9 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
     "rdsspd %[ssp];"                                            \
     "cmp $1, %[ssp];"                                           \
     "je .L_shstk_done.%=;" /* CET not active?  Skip. */         \
-    "mov $%c[skstk_base], %[val];"                              \
+    ALTERNATIVE("mov $%c[skstk_base], %[val];",                 \
+                "mov $%c[skstk_base] + 8, %[val];",             \
+                X86_FEATURE_XEN_FRED)                           \
     "and $%c[stack_mask], %[ssp];"                              \
     "sub %[ssp], %[val];"                                       \
     "shr $3, %[val];"                                           \



~Andrew


From xen-devel-bounces@lists.xenproject.org Fri Aug 22 00:09:59 2025
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Date: Thu, 21 Aug 2025 17:09:38 -0700 (PDT)
From: Stefano Stabellini 
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To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?= 
cc: Andrew Cooper , 
    Xen-devel , 
    Anthony PERARD , 
    Jan Beulich , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini 
Subject: Re: [PATCH] CI: Use 'watchdog' for x86 hardware
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On Thu, 21 Aug 2025, Marek Marczykowski-Górecki wrote:
> On Thu, Aug 21, 2025 at 01:06:52PM +0100, Andrew Cooper wrote:
> > This detects various hangs and turns them into a crash with backtrace.
> > 
> > Signed-off-by: Andrew Cooper 
> 
> Should it also apply to in-QEMU tests?
> 
> Anyway:
> 
> Reviewed-by: Marek Marczykowski-Górecki 

Acked-by: Stefano Stabellini 
--8323329-1136081158-1755821381=:2743087--


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    Anthony PERARD , 
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    "xen-devel@lists.xenproject.org" , 
    Oleksii Kurochko 
Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
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On Thu, 21 Aug 2025, Jan Beulich wrote:
> On 20.08.2025 05:12, Penny, Zheng wrote:
> > [Public]
> > 
> >> -----Original Message-----
> >> From: Jan Beulich 
> >> Sent: Monday, August 18, 2025 4:31 PM
> >> To: Penny, Zheng ; Oleksii Kurochko
> >> 
> >> Cc: Huang, Ray ; Andrew Cooper
> >> ; Roger Pau Monné ;
> >> Anthony PERARD ; Orzel, Michal
> >> ; Julien Grall ; Stefano Stabellini
> >> ; xen-devel@lists.xenproject.org
> >> Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
> >>
> >> On 15.08.2025 12:27, Penny Zheng wrote:
> >>> In order to fix CI error of a randconfig picking both
> >>> PV_SHIM_EXCLUSIVE=y and HVM=y results in hvm.c being built, but
> >>> domctl.c not being built, which leaves a few functions, like
> >>> domctl_lock_acquire/release() undefined, causing linking to fail.
> >>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE
> >>> Makefile /hypercall-defs section, with this adjustment, we also need
> >>> to release redundant vnuma_destroy() stub definition from
> >>> PV_SHIM_EXCLUSIVE guardian, to not break compilation Above change will
> >>> leave dead code in the shim binary temporarily and will be fixed with
> >>> the introduction of domctl-op wrapping.
> >>
> >> Well, "temporarily" is now getting interesting. While v1 of "Introduce
> >> CONFIG_DOMCTL" was submitted in time to still be eligible for taking into 4.21,
> >> that - as indicated elsewhere - is moving us further in an unwanted direction. Hence
> >> I'm not sure this can even be counted as an in-time submission. Plus it looks to be
> >> pretty extensive re-work in some areas.
> >> Hence I'm somewhat weary as to 4.21 here. IOW question, mainly to Oleksii, is
> >> whether to
> >> 1) strive to complete that work in time (and hence take the patch here),
> >> 2) take the patch here, accepting the size regression for the shim, or
> >> 3) revert what has caused the randconfig issues, and retry the effort in
> >>    4.22.
> >>
> >>> Fixes: 568f806cba4c ("xen/x86: remove "depends on
> >>> !PV_SHIM_EXCLUSIVE"")
> >>> Reported-by: Jan Beulich 
> >>> Signed-off-by: Penny Zheng 
> >>
> >> My earlier question (when the patch still was part of a series) sadly has remained
> >> unanswered: You've run this through a full round of testing this time?
> > 
> > Sorry, missed that, yes, it has been tested with both default defconfig and allyesconfig.
> 
> I'm sorry if my request was unclear, but with "full round of testing" I in particular
> meant a full CI pipeline, plus (given the issue that's being fixed) some extra
> randconfig testing.

https://gitlab.com/xen-project/people/sstabellini/xen/-/pipelines/1997431361

I ran a few tests myself changing config options on purpose trying to
break it, and so far they were all successful.
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Feedback-ID: i1568416f:Fastmail
Date: Fri, 22 Aug 2025 02:53:33 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Andrew Cooper ,
	Jan Beulich ,
	xen-devel 
Subject: Re: S3 regression related to XSA-471 patches
Message-ID: 
References: 
 
 
 
 <4fb544d7-fede-46b8-950e-f9c4af1cb04f@citrix.com>
 
 
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Date: Fri, 22 Aug 2025 02:53:33 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Andrew Cooper ,
	Jan Beulich ,
	xen-devel 
Subject: Re: S3 regression related to XSA-471 patches

On Wed, Aug 13, 2025 at 09:26:09AM +0200, Roger Pau Monn=C3=A9 wrote:
> On Wed, Aug 13, 2025 at 04:53:53AM +0200, Marek Marczykowski-G=C3=B3recki=
 wrote:
> >=20
> >=20
> > On August 11, 2025 3:16:46 PM GMT+02:00, Andrew Cooper  wrote:
> > >On 07/08/2025 6:29 pm, Marek Marczykowski-G=C3=B3recki wrote:
> > >> On Wed, Aug 06, 2025 at 12:46:36PM +0200, Marek Marczykowski-G=C3=B3=
recki wrote:
> > >>> On Wed, Aug 06, 2025 at 12:36:56PM +0200, Jan Beulich wrote:
> > >>>> On 06.08.2025 12:23, Marek Marczykowski-G=C3=B3recki wrote:
> > >>>>> We've got several reports that S3 reliability recently regressed.=
 We
> > >>>>> identified it's definitely related to XSA-471 patches, and bisect=
ion
> > >>>>> points at "x86/idle: Remove broken MWAIT implementation". I don't=
 have
> > >>>>> reliable reproduction steps, so I'm not 100% sure if it's really =
this
> > >>>>> patch, or maybe an earlier one - but it's definitely already brok=
en at
> > >>>>> this point in the series. Most reports are about Xen 4.17 (as tha=
t's
> > >>>>> what stable Qubes OS version currently use), but I think I've seen
> > >>>>> somebody reporting the issue on 4.19 too (but I don't have clear
> > >>>>> evidence, especially if it's the same issue).
> > >>>> At the time we've been discussing the explicit raising of TIMER_SO=
FTIRQ
> > >>>> in mwait_idle_with_hints() a lot. If it was now truly missing, tha=
t imo
> > >>>> shouldn't cause problems only after resume, but then it may have c=
overed
> > >>>> for some omission during resume. As a far-fetched experiment, coul=
d you
> > >>>> try putting that back (including the calculation of the "expires" =
local
> > >>>> variable)?
> > >>> Sure, I'll try.
> > >> It appears this fixes the issue, at least in ~10 attempts so far
> > >> (usually I could reproduce the issue after 2-3 attempts).
> > >>
> > >
> > >Can you show the exact code which seems to have made this stable?
> >=20
> > This patch: https://github.com/marmarek/qubes-vmm-xen/blob/7c9e9e312948=
c772d9a68090109964121c1d16fe/0001-DEBUG-S3.patch
>=20
> Hello,
>=20
> Can you test if the patch below in isolation makes any difference?

Seems to help too. At least a test similar as before did not hit the
issue anymore.

> Thanks, Roger.
> ---
> diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c
> index 2ac162c997fe..27d672ad5dbb 100644
> --- a/xen/arch/x86/acpi/power.c
> +++ b/xen/arch/x86/acpi/power.c
> @@ -19,6 +19,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
> =20
> @@ -310,6 +311,7 @@ static int enter_state(u32 state)
>      thaw_domains();
>      system_state =3D SYS_STATE_active;
>      spin_unlock(&pm_lock);
> +    raise_softirq(TIMER_SOFTIRQ);
>      return error;
>  }
> =20
> diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
> index 0fd8bdba7067..9d66db861b74 100644
> --- a/xen/arch/x86/apic.c
> +++ b/xen/arch/x86/apic.c
> @@ -65,7 +65,6 @@ static struct {
>      unsigned int apic_lvt0;
>      unsigned int apic_lvt1;
>      unsigned int apic_lvterr;
> -    unsigned int apic_tmict;
>      unsigned int apic_tdcr;
>      unsigned int apic_thmr;
>  } apic_pm_state;
> @@ -658,7 +657,6 @@ int lapic_suspend(void)
>      apic_pm_state.apic_lvt0 =3D apic_read(APIC_LVT0);
>      apic_pm_state.apic_lvt1 =3D apic_read(APIC_LVT1);
>      apic_pm_state.apic_lvterr =3D apic_read(APIC_LVTERR);
> -    apic_pm_state.apic_tmict =3D apic_read(APIC_TMICT);
>      apic_pm_state.apic_tdcr =3D apic_read(APIC_TDCR);
>      if (maxlvt >=3D 5)
>          apic_pm_state.apic_thmr =3D apic_read(APIC_LVTTHMR);
> @@ -718,7 +716,7 @@ int lapic_resume(void)
>          apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
>      apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
>      apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
> -    apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
> +    apic_write(APIC_TMICT, 0);
>      apic_write(APIC_ESR, 0);
>      apic_read(APIC_ESR);
>      apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
>=20

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Subject: Re: [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural
 constant_tsc model checks
To: Sohil Mehta , David Woodhouse
 , x86@kernel.org,
 Dave Hansen , Tony Luck ,
 =?UTF-8?Q?J=C3=BCrgen_Gross?= ,
 Boris Ostrovsky ,
 xen-devel 
Cc: Peter Zijlstra , Ingo Molnar ,
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 linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
 linux-pm@vger.kernel.org, kvm@vger.kernel.org, Xin Li 
References: <20250219184133.816753-1-sohil.mehta@intel.com>
 <20250219184133.816753-14-sohil.mehta@intel.com>
 <6f05a6849fb7b22db35216dcf12bf537f8a43a92.camel@infradead.org>
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On 8/22/2025 3:43 AM, Sohil Mehta wrote:
> On 8/21/2025 12:34 PM, Sohil Mehta wrote:
>> On 8/21/2025 6:15 AM, David Woodhouse wrote:
>>
>>> Hm. My test host is INTEL_HASWELL_X (0x63f). For reasons which are
>>> unclear to me, QEMU doesn't set bit 8 of 0x80000007 EDX unless I
>>> explicitly append ',+invtsc' to the existing '-cpu host' on its command
>>> line. So now my guest doesn't think it has X86_FEATURE_CONSTANT_TSC.
>>>
>>
>> Haswell should have X86_FEATURE_CONSTANT_TSC, so I would have expected
>> the guest bit to be set. Until now, X86_FEATURE_CONSTANT_TSC was set
>> based on the Family-model instead of the CPUID enumeration which may
>> have hid the issue.
>>
> 
> Correction:
> s/instead/as well as
> 
>>  From my initial look at the QEMU implementation, this seems intentional.
>>
>> QEMU considers Invariant TSC as un-migratable which prevents it from
>> being exposed to migratable guests (default).
>> target/i386/cpu.c:
>> [FEAT_8000_0007_EDX]
>>           .unmigratable_flags = CPUID_APM_INVTSC,
>>
>> Can you please try '-cpu host,migratable=off'?
> 
> This is mainly to verify. If confirmed, I am not sure what the long term
> solution should be.

yeah. It's the intentional behavior of QEMU.

Invariant TSC is ummigratable unless users explicitly configures the TSC 
frequency, e.g., "-cpu host,tsc-frequency=xxx". Because the TSC 
frequency is by default the host's frequency if no "tsc-frequency" 
specified, and it will change when the VM is migrated to a host with a 
different TSC frequency.

It's the specific behavior/rule of QEMU. We just need to keep it in 
mind. If we want to expose invariant TSC to the guest with QEMU's "-cpu 
host", we can either:
1) explicitly configure the "tsc-frequency", or
2) explicitly turn off "migratable"


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From: Juergen Gross 
To: torvalds@linux-foundation.org
Cc: linux-kernel@vger.kernel.org,
	xen-devel@lists.xenproject.org,
	sstabellini@kernel.org
Subject: [GIT PULL] xen: branch for v6.17-rc3
Date: Fri, 22 Aug 2025 07:31:20 +0200
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Linus,

Please git pull the following tag:

 git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git for-linus-6.17-rc3-tag

xen: branch for v6.17-rc3

It contains 2 small cleanups which are both relevant only when running as
a Xen guest.


Thanks.

Juergen

 arch/x86/include/asm/xen/hypercall.h |  5 +++--
 drivers/xen/xenbus/xenbus_xs.c       | 23 -----------------------
 include/linux/compiler.h             |  8 --------
 3 files changed, 3 insertions(+), 33 deletions(-)

Jan Beulich (1):
      compiler: remove __ADDRESSABLE_ASM{_STR,}() again

Juergen Gross (1):
      drivers/xen/xenbus: remove quirk for Xen 3.x


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Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
To: Stefano Stabellini 
Cc: "Penny, Zheng" , "Huang, Ray" ,
 Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 "Orzel, Michal" , Julien Grall ,
 "xen-devel@lists.xenproject.org" ,
 Oleksii Kurochko 
References: <20250815102728.1340505-1-Penny.Zheng@amd.com>
 
 
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From: Jan Beulich 
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On 22.08.2025 02:10, Stefano Stabellini wrote:
> On Thu, 21 Aug 2025, Jan Beulich wrote:
>> On 20.08.2025 05:12, Penny, Zheng wrote:
>>> [Public]
>>>
>>>> -----Original Message-----
>>>> From: Jan Beulich 
>>>> Sent: Monday, August 18, 2025 4:31 PM
>>>> To: Penny, Zheng ; Oleksii Kurochko
>>>> 
>>>> Cc: Huang, Ray ; Andrew Cooper
>>>> ; Roger Pau Monné ;
>>>> Anthony PERARD ; Orzel, Michal
>>>> ; Julien Grall ; Stefano Stabellini
>>>> ; xen-devel@lists.xenproject.org
>>>> Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
>>>>
>>>> On 15.08.2025 12:27, Penny Zheng wrote:
>>>>> In order to fix CI error of a randconfig picking both
>>>>> PV_SHIM_EXCLUSIVE=y and HVM=y results in hvm.c being built, but
>>>>> domctl.c not being built, which leaves a few functions, like
>>>>> domctl_lock_acquire/release() undefined, causing linking to fail.
>>>>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE
>>>>> Makefile /hypercall-defs section, with this adjustment, we also need
>>>>> to release redundant vnuma_destroy() stub definition from
>>>>> PV_SHIM_EXCLUSIVE guardian, to not break compilation Above change will
>>>>> leave dead code in the shim binary temporarily and will be fixed with
>>>>> the introduction of domctl-op wrapping.
>>>>
>>>> Well, "temporarily" is now getting interesting. While v1 of "Introduce
>>>> CONFIG_DOMCTL" was submitted in time to still be eligible for taking into 4.21,
>>>> that - as indicated elsewhere - is moving us further in an unwanted direction. Hence
>>>> I'm not sure this can even be counted as an in-time submission. Plus it looks to be
>>>> pretty extensive re-work in some areas.
>>>> Hence I'm somewhat weary as to 4.21 here. IOW question, mainly to Oleksii, is
>>>> whether to
>>>> 1) strive to complete that work in time (and hence take the patch here),
>>>> 2) take the patch here, accepting the size regression for the shim, or
>>>> 3) revert what has caused the randconfig issues, and retry the effort in
>>>>    4.22.
>>>>
>>>>> Fixes: 568f806cba4c ("xen/x86: remove "depends on
>>>>> !PV_SHIM_EXCLUSIVE"")
>>>>> Reported-by: Jan Beulich 
>>>>> Signed-off-by: Penny Zheng 
>>>>
>>>> My earlier question (when the patch still was part of a series) sadly has remained
>>>> unanswered: You've run this through a full round of testing this time?
>>>
>>> Sorry, missed that, yes, it has been tested with both default defconfig and allyesconfig.
>>
>> I'm sorry if my request was unclear, but with "full round of testing" I in particular
>> meant a full CI pipeline, plus (given the issue that's being fixed) some extra
>> randconfig testing.
> 
> https://gitlab.com/xen-project/people/sstabellini/xen/-/pipelines/1997431361
> 
> I ran a few tests myself changing config options on purpose trying to
> break it, and so far they were all successful.

Should I translate this to Tested-by: then?

Jan


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Subject: Re: [PATCH v2 02/16] x86/msr: Rework rdmsr_safe() using asm goto()
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 21.08.2025 18:20, Andrew Cooper wrote:
> On 19/08/2025 5:23 pm, Jan Beulich wrote:
>> On 19.08.2025 15:52, Andrew Cooper wrote:
>>> On 18/08/2025 12:27 pm, Jan Beulich wrote:
>>>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>>>> ... on capable toolchains.
>>>>>
>>>>> This avoids needing to hold rc in a register across the RDMSR, and in most
>>>>> cases removes direct testing and branching based on rc, as the fault label can
>>>>> be rearranged to directly land on the out-of-line block.
>>>>>
>>>>> There is a subtle difference in behaviour.  The old behaviour would, on fault,
>>>>> still produce 0's and write to val.
>>>>>
>>>>> The new behaviour only writes val on success, and write_msr() is the only
>>>>> place where this matters.  Move temp out of switch() scope and initialise it
>>>>> to 0.
>>>> But what's the motivation behind making this behavioral change? At least in
>>>> the cases where the return value isn't checked, it would feel safer if we
>>>> continued clearing the value. Even if in all cases where this could matter
>>>> (besides the one you cover here) one can prove correctness by looking at
>>>> surrounding code.
>>> I didn't realise I'd made a change at first, but it's a consequence of
>>> the compiler's ability to rearrange basic blocks.
>>>
>>> It can be fixed with ...
>>>
>>>>> --- a/xen/arch/x86/include/asm/msr.h
>>>>> +++ b/xen/arch/x86/include/asm/msr.h
>>>>> @@ -55,6 +55,24 @@ static inline void wrmsrns(uint32_t msr, uint64_t val)
>>>>>  /* rdmsr with exception handling */
>>>>>  static inline int rdmsr_safe(unsigned int msr, uint64_t *val)
>>>>>  {
>>>>> +#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
>>>>> +    uint64_t lo, hi;
>>>>> +    asm_inline goto (
>>>>> +        "1: rdmsr\n\t"
>>>>> +        _ASM_EXTABLE(1b, %l[fault])
>>>>> +        : "=a" (lo), "=d" (hi)
>>>>> +        : "c" (msr)
>>>>> +        :
>>>>> +        : fault );
>>>>> +
>>>>> +    *val = lo | (hi << 32);
>>>>> +
>>>>> +    return 0;
>>>>> +
>>>>> + fault:
>>>     *val = 0;
>>>
>>> here, but I don't want to do this.  Because val is by pointer and
>>> generally spilled to the stack, the compiler can't optimise away the store.
>> But the compiler is dealing with such indirection in inline functions just
>> fine. I don't expect it would typically spill val to the stack. Is there
>> anything specific here that you think would make this more likely?
> 
> Yes.  The design of the functions they're used in.  Adding this line
> results in:
> 
> add/remove: 0/0 grow/shrink: 7/2 up/down: 109/-36 (73)
> Function                                     old     new   delta
> read_msr                                    1243    1307     +64
> resource_access                              326     341     +15
> hwp_init_msrs.cold                           297     308     +11
> probe_cpuid_faulting                         168     175      +7
> svm_msr_read_intercept                      1034    1039      +5
> hwp_write_request                            113     117      +4
> hwp_init_msrs                                371     374      +3
> amd_log_freq                                 844     828     -16
> guest_rdmsr                                 2168    2148     -20
> 
> Taking read_msr() as a concrete example, this is because it's a store
> into a parent functions variable, not into a local variable, and cannot
> be elided.
> 
> 
>>
>>> I'd far rather get a real compiler error, than to have logic relying on
>>> the result of a faulting MSR read.
>> A compiler error? (Hmm, perhaps you think of uninitialized variable
>> diagnostics. That may or may not trigger, depending on how else the
>> caller's variable is used.)
> 
> Yes I was referring to the uninitialised variable diagnostic.  *_safe()
> are fairly rare, and we've got plenty of coverage in CI.

Well, okay, slightly hesitantly
Reviewed-by: Jan Beulich 
preferably with the paragraph in the description that I commented on
slightly expanded to cover the "why" aspect.

Jan


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Subject: Re: [PATCH v2 12/16] x86/msr: Change wrmsr() to take a single
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To: Andrew Cooper 
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On 21.08.2025 20:47, Andrew Cooper wrote:
> On 19/08/2025 1:38 pm, Jan Beulich wrote:
>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/nmi.c
>>> +++ b/xen/arch/x86/nmi.c
>>> @@ -218,16 +218,16 @@ void disable_lapic_nmi_watchdog(void)
>>>          return;
>>>      switch (boot_cpu_data.x86_vendor) {
>>>      case X86_VENDOR_AMD:
>>> -        wrmsr(MSR_K7_EVNTSEL0, 0, 0);
>>> +        wrmsrns(MSR_K7_EVNTSEL0, 0);
>> Since you switch to non-serializing here, ...
>>
>>> @@ -308,11 +308,11 @@ static void setup_k7_watchdog(void)
>>>          | K7_EVNTSEL_USR
>>>          | K7_NMI_EVENT;
>>>  
>>> -    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
>>> +    wrmsr(MSR_K7_EVNTSEL0, evntsel);
>>>      write_watchdog_counter("K7_PERFCTR0");
>>>      apic_write(APIC_LVTPC, APIC_DM_NMI);
>>>      evntsel |= K7_EVNTSEL_ENABLE;
>>> -    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
>>> +    wrmsr(MSR_K7_EVNTSEL0, evntsel);
>>>  }
>> ... why not also here?
> 
> An oversight.  Fixed.
> 
>>
>>> --- a/xen/arch/x86/oprofile/op_model_athlon.c
>>> +++ b/xen/arch/x86/oprofile/op_model_athlon.c
>>> @@ -34,7 +34,7 @@
>>>  #define MAX_COUNTERS FAM15H_NUM_COUNTERS
>>>  
>>>  #define CTR_READ(msr_content,msrs,c) do {rdmsrl(msrs->counters[(c)].addr, (msr_content));} while (0)
>>> -#define CTR_WRITE(l,msrs,c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1);} while (0)
>>> +#define CTR_WRITE(l,msrs,c) do { wrmsr(msrs->counters[(c)].addr, -l); } while (0)
>> This isn't obviously correct (as in: no functional change): The macro is,
>> for example, passed reset_value[] contents, which is of type unsigned long.
>> Quite possible that the original code was wrong, though.
> 
> I'm pretty sure the change is correct.
> 
> Perf counters get programmed to -(count), as they generate an interrupt
> when they overflow.  The K8 is the oldest BKDG I can easily access, and
> the counters are 48 bits wide.  The same is true of Intel systems of of
> the same age.
> 
> Interestingly, it is the singular omission from b5103d692aa7 which
> converts everything including the Intel version of CTR_WRITE() of this
> to use wrmsrl().
> 
> While looking at the mail list archives for b5103d692aa7, I found
> https://lists.xenproject.org/archives/html/xen-devel/2010-06/msg01660.html
> which shows that it was Christoph's attempt to turn rdmsr() and wrmsr()
> into a real C functions, so I'm pretty certain that CTR_WRITE() was an
> omission in b5103d692aa7.

Okay, so mainly in need of having the description point out there is actually
a correction of something in here. Then:
Acked-by: Jan Beulich 

Jan


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Subject: Re: [PATCH v2 13/16] x86/msr: Use MSR_IMM when available
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 21.08.2025 20:59, Andrew Cooper wrote:
> On 19/08/2025 1:55 pm, Jan Beulich wrote:
>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/include/asm/msr.h
>>> +++ b/xen/arch/x86/include/asm/msr.h
>>> @@ -29,10 +29,52 @@
>>>   *  wrmsrl(MSR_FOO, val);
>>>   */
>>>  
>>> -static inline uint64_t rdmsr(unsigned int msr)
>>> +/*
>>> + * RDMSR with a compile-time constant index, when available.  Falls back to
>>> + * plain RDMSR.
>>> + */
>>> +static always_inline uint64_t __rdmsr_imm(uint32_t msr)
>>> +{
>>> +    uint64_t val;
>>> +
>>> +    /*
>>> +     * For best performance, RDMSR $msr, %r64 is recommended.  For
>>> +     * compatibility, we need to fall back to plain RDMSR.
>>> +     *
>>> +     * The combined ABI is awkward, because RDMSR $imm produces an r64,
>>> +     * whereas WRMSR{,NS} produces a split edx:eax pair.
>>> +     *
>>> +     * Always use RDMSR $imm, %rax, because it has the most in common with the
>>> +     * legacy form.  When MSR_IMM isn't available, emit logic to fold %edx
>>> +     * back into %rax.
>>> +     *
>>> +     * Let the compiler do %ecx setup.  This does mean there's a useless `mov
>>> +     * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it means
>>> +     * the compiler can de-duplicate the setup in the common case of reading
>>> +     * and writing the same MSR.
>>> +     */
>>> +    alternative_io(
>>> +        "rdmsr\n\t"
>>> +        "shl $32, %%rdx\n\t"
>>> +        "or %%rdx, %%rax\n\t",
>>> +
>>> +        /* RDMSR $msr, %rax */
>>> +        ".byte 0xc4,0xe7,0x7b,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
>>> +
>>> +        "=a" (val),
>> Strictly speaking "=&a". Not that it matters much here; just to not
>> set a bad precedent.
> 
> Why?  A is not written to until after all inputs are consumed.
> 
> I don't see how it can qualify for being early-clobber.

Because the very first insn already writes to the register.

>>> @@ -55,11 +97,51 @@ static inline void wrmsr(unsigned int msr, uint64_t val)
>>>  }
>>>  #define wrmsrl(msr, val) wrmsr(msr, val)
>>>  
>>> +/*
>>> + * Non-serialising WRMSR with a compile-time constant index, when available.
>>> + * Falls back to plain WRMSRNS, or to a serialising WRMSR.
>>> + */
>>> +static always_inline void __wrmsrns_imm(uint32_t msr, uint64_t val)
>>> +{
>>> +    /*
>>> +     * For best performance, WRMSRNS %r64, $msr is recommended.  For
>>> +     * compatibility, we need to fall back to plain WRMSRNS, or to WRMSR.
>>> +     *
>>> +     * The combined ABI is awkward, because WRMSRNS $imm takes a single r64,
>>> +     * whereas WRMSR{,NS} takes a split edx:eax pair.
>>> +     *
>>> +     * Always use WRMSRNS %rax, $imm, because it has the most in common with
>>> +     * the legacy forms.  When MSR_IMM isn't available, emit setup logic for
>>> +     * %edx.
>>> +     *
>>> +     * Let the compiler do %ecx setup.  This does mean there's a useless `mov
>>> +     * $imm, %ecx` in the instruction stream in the MSR_IMM case, but it means
>>> +     * the compiler can de-duplicate the setup in the common case of reading
>>> +     * and writing the same MSR.
>>> +     */
>>> +    alternative_input_2(
>>> +        "mov %%rax, %%rdx\n\t"
>>> +        "shr $32, %%rdx\n\t"
>>> +        ".byte 0x2e; wrmsr",
>>> +
>>> +        /* CS WRMSRNS %rax, $msr */
>>> +        ".byte 0x2e,0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]", X86_FEATURE_MSR_IMM,
>>> +
>>> +        "mov %%rax, %%rdx\n\t"
>>> +        "shr $32, %%rdx\n\t"
>>> +        ".byte 0x0f,0x01,0xc6", X86_FEATURE_WRMSRNS,
>> Isn't this the wrong way round for hardware which has both features? The
>> last active alternative wins, iirc.
> 
> Bah - fooled once again by the nop optimisation.  I'll reorder.
> 
> But, we really should swap the order.  Especially now that you've
> inserted serialisation, it's an expensive waste of time patching the
> same site multiple times.

I'm not convinced swapping the order would be a good thing. Nor do I
see how it would (easily) help here: When both features are present,
we always patch twice. To avoid that, while patching one location we
would need to peek ahead into the next table entry to see whether
that's going to patch the same location, same (or bigger) size.

Jan


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Subject: Re: [PATCH v2 14/16] x86/fsgsbase: Split out __{rd,wr}gskern()
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On 21.08.2025 22:20, Andrew Cooper wrote:
> On 19/08/2025 2:01 pm, Jan Beulich wrote:
>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>> Right now they're inline in {read,write}_gs_shadow(), but we're going to need
>>> to use these elsewhere to support FRED.
>> But why "kern"? We're not dealing with GS in kernel / user terms, but in
>> real / shadow ones.
> 
> Because it's a common name that also has the property of aligning nicely
> when used beside GS_BASE.
> 
> But fine, I'll rename it.
> 
>>  I'm also not quite happy with the double leading
>> underscores, fwiw.
> 
> Consistency with the similar logic.

Yet making for more changes later, once we mean to strictly follow the
respective Misra rule.

>>> --- a/xen/arch/x86/include/asm/fsgsbase.h
>>> +++ b/xen/arch/x86/include/asm/fsgsbase.h
>>> @@ -32,6 +32,17 @@ static inline unsigned long __rdgsbase(void)
>>>      return base;
>>>  }
>>>  
>>> +static inline unsigned long __rdgskern(void)
>>> +{
>>> +    unsigned long base;
>>> +
>>> +    asm_inline volatile ( "swapgs\n\t"
>>> +                          "rdgsbase %0\n\t"
>>> +                          "swapgs" : "=r" (base) );
>> Again strictly speaking "=&r", if already you open-code rdgsbase() now.
> 
> As before, why?   There are no inputs to be clobbered, early or otherwise.

Hence why I said "strictly speaking". Inputs or not imo doesn't matter in
such a decision; that merely makes using the early-clobber form benign.
The sole criteria by which I think one ought to go is whether a register
is altered solely by the last (often: only) insn. IOW it's again more to
prevent setting a bad precedent. Here things are easy to see, so a
hypothetical future change isn't at much of a risk of breaking things. The
more complex asm()-s get, the easier it is to overlook a missing early-
clobber when making some change.

Jan


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Subject: Re: [PATCH v2 15/16] x86/fsgsbase: Update fs/gs helpers to use
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To: Andrew Cooper 
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 Xen-devel 
References: <20250815204117.3312742-1-andrew.cooper3@citrix.com>
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On 21.08.2025 22:49, Andrew Cooper wrote:
> On 19/08/2025 2:09 pm, Jan Beulich wrote:
>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/hvm/vmx/vmx.c
>>> +++ b/xen/arch/x86/hvm/vmx/vmx.c
>>> @@ -2733,8 +2733,8 @@ static uint64_t cf_check vmx_get_reg(struct vcpu *v, unsigned int reg)
>>>      case MSR_SHADOW_GS_BASE:
>>>          if ( v != curr )
>>>              return v->arch.hvm.vmx.shadow_gs;
>>> -        rdmsrl(MSR_SHADOW_GS_BASE, val);
>>> -        return val;
>>> +        else
>>> +            return rdmsr(MSR_SHADOW_GS_BASE);
>>>      }
>> Here and below, can we please do without the pointless "else"? Strictly
>> speaking in Misra's terms that's "dead code" (things working identically
>> without), and I'm quite happy that I can now use this argument to
>> support my personal antipathy to this style of coding. Or else use the
>> conditional operator in such cases (where applicable).
> 
> No.  I have always, and will always prioritise readability first and
> foremost.

But my preference is precisely because of readability. The excess "else"
gives a wrong impression to the reader, when not looking closely enough.
(And I [now] expect you might say the opposite.)

> I do not agree with your interpretation of MISRA in this case.

Something to discuss in a broader group then, I suppose.

Jan


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On 21.08.2025 22:52, Andrew Cooper wrote:
> On 19/08/2025 2:19 pm, Jan Beulich wrote:
>> On 15.08.2025 22:41, Andrew Cooper wrote:
>>> It turns out that using the higher level helpers adjacent like this leads to
>>> terrible code generation.  Due to -fno-strict-alising, the store into state->
>>> invalidates the read_cr4() address calculation (which is really cpu_info->cr4
>>> under the hood), meaning that it can't be hoisted.
>>>
>>> As a result we get "locate the top of stack block, get cr4, and see if
>>> FSGSBASE is set" repeated 3 times, and an unreasoanble number of basic blocks.
>>>
>>> Hoist the calculation manually, which results in two basic blocks.
>>>
>>> Signed-off-by: Andrew Cooper 
>> Otoh the function here isn't really performance or size critical. I'm undecided
>> whether the undesirable open-coding or the bad code gen are the lesser evil.
> 
> This function no, but every other place touching FS and GS is
> performance critical.  They're all messy to start with, and get worse
> under FRED.

Is there any (further) bad effect to the function here by the time all of the
FRED bits are in?

Jan


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CC: "xen-devel@lists.xenproject.org" , Stefano
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Subject: Re: [PATCH v2 07/10] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
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Thread-Topic: [PATCH v2 07/10] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
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To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" , Stefano
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Subject: Re: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
 to support eSPIs
Thread-Topic: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
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From: Leonid Komarianskyi 
To: Julien Grall , Volodymyr Babchuk
	
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v2 02/10] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Topic: [PATCH v2 02/10] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Index: AQHcB5d7oc7jtkgiGki3l7l8xwTnbrRtYNMAgAD9SwA=
Date: Fri, 22 Aug 2025 07:30:37 +0000
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Subject: Re: [PATCH 4/5] arm/mpu: Implement ioremap_attr for MPU
To: Hari Limaye , 
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On 30/07/2025 10:45, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Introduce helpers (un)map_mm_range() in order to allow the temporary
> mapping of a range of memory, and use these to implement the function
> `ioremap_attr` for MPU systems.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
> ---
>  xen/arch/arm/include/asm/mpu/mm.h |  22 +++++
>  xen/arch/arm/mpu/mm.c             | 150 ++++++++++++++++++++++++++++--
>  2 files changed, 163 insertions(+), 9 deletions(-)
> 
> diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
> index 56ca411af4..177550f5bd 100644
> --- a/xen/arch/arm/include/asm/mpu/mm.h
> +++ b/xen/arch/arm/include/asm/mpu/mm.h
> @@ -106,6 +106,28 @@ int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
>   */
>  pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags);
>  
> +/*
> + * Maps a temporary range of memory with attributes `flags`; if the range is
Why do you always mention 'temporary' in the context of these functions? What
prevents us from using them to map a region for a longer period of time?
Also, temporary range is a bit confusing term and should better be replaced with
'Maps temporarily a range of memory ...'

> + * already mapped with the same attributes, including an inclusive match, the
> + * existing mapping is returned. This API is intended for mappings that exist
What are the use cases you want to cover to try to map the same range with the
same attributes more than once (without unmapping in the meantime)?

> + * transiently for a short period between calls to this function and
> + * `unmap_mm_range`.
> + *
> + * @param start     Base address of the range to map (inclusive).
> + * @param end       Limit address of the range to map (exclusive).
> + * @param flags     Flags for the memory range to map.
> + * @return          Pointer to start of region on success, NULL on error.
> + */
> +void *map_mm_range(paddr_t start, paddr_t end, unsigned int flags);
So far, all the MPU related functions use [base, limit) instead of [start, end).
Do we see the benefit of diverging here?

~Michal




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Subject: Re: [PATCH 5/5] xen/arm: map static memory on demand
To: Hari Limaye , 
CC: , Penny Zheng , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Volodymyr Babchuk
	, Andrew Cooper ,
	Anthony PERARD , Jan Beulich ,
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Wei Chen
	
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On 30/07/2025 10:45, Hari Limaye wrote:
> From: Penny Zheng 
> 
> In the function `init_staticmem_pages` we need to have mapped static
> memory banks for initialization. Unlike on an MMU system, we cannot map
> the entire RAM on an MPU system as we have a limited number of MPU
> memory regions. To solve this, transiently map the static memory banks
> for initialization.
How does this correspond to Arm32 MPU (R52), where all of the RAM will be
covered? I don't think 'transient' mappings will be needed there but all of your
work targets common (i.e. not only Arm64) MPU code.

~Michal



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Subject: Re: [PATCH] xen/dom0less: Clear xenstore page
To: Jason Andryuk , 
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On 20/08/2025 23:12, Jason Andryuk wrote:
> C Xenstored was seen failing to map a domU's event channel.  Enhancing
> Xen's error messages shows:
> common/event_channel.c:427:d0v0 EVTCHNOP failure: d1, port 3267543746 error -22
> 
> Port 3267543746 is 0xc2c2c2c2 - SCRUB_PATTERN.
> 
> Xenstore expects a non-zero evtchn_port to be valid.  Explicitly zero
> the page to avoid this.
> 
> Fixes: f78895ad78c9 ("tools/xenstored: Read event channel from xenstored page")
> Signed-off-by: Jason Andryuk 
Acked-by: Michal Orzel 

~Michal



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From: Mykyta Poturai 
To: Jan Beulich 
CC: Luca Fancellu , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Volodymyr
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	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , "Daniel P.
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Subject: Re: [PATCH v2 3/3] xen/pci: add discovered PCI device at boot
Thread-Topic: [PATCH v2 3/3] xen/pci: add discovered PCI device at boot
Thread-Index: AQHcEc3mKXITpUZcl0ea3L2+fX5U/bRs0pmAgAGAWAA=
Date: Fri, 22 Aug 2025 08:03:43 +0000
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Subject: Re: [PATCH] xen/arm: smmuv3: Add cache maintenance for non-coherent
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To: Dmytro Firsov , "xen-devel@lists.xenproject.org"
	
CC: Bertrand Marquis , Rahul Singh
	, Stefano Stabellini , Julien
 Grall , Volodymyr Babchuk 
References: <24567cc1630b1577c33939ff71d67fb2ebe5572f.1754491424.git.dmytro_firsov@epam.com>
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On 06/08/2025 16:58, Dmytro Firsov wrote:
> According to the Arm SMMUv3 spec (ARM IHI 0070), a system may have
> SMMU(s) that is/are non-coherent to the PE (processing element). In such
> cases, memory accesses from the PE should be either non-cached or be
> augmented with manual cache maintenance. SMMU cache coherency is reported
> by bit 4 (COHACC) of the SMMU_IDR0 register and is already present in the
> Xen driver. However, the current implementation is not aware of cache
> maintenance for memory that is shared between the PE and non-coherent
> SMMUs. It contains dmam_alloc_coherent() function, that is added during
> Linux driver porting. But it is actually a wrapper for _xzalloc(), that
> returns normal writeback memory (which is OK for coherent SMMUs).
> 
> During Xen bring-up on a system with non-coherent SMMUs, the driver did
> not work properly - the SMMU was not functional and halted initialization
> at the very beginning due to a timeout while waiting for CMD_SYNC
> completion:
> 
>   (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
>   (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
> 
> To properly handle such scenarios, add the non_coherent flag to the
> arm_smmu_queue struct. It is initialized using features reported by the
> SMMU HW and will be used for triggering cache clean/invalidate operations.
> This flag is not queue-specific (it is applicable to the whole SMMU), but
> adding it to arm_smmu_queue allows us to not change function signatures
> and simplify the patch (smmu->features, which contains the required flag,
> are not available in code parts that require cache maintenance).
There are already a few places advertising the SMMU coherency:
1) smmu->features
2) d->iommu->features
3) platform_features

All of them are better places than queue struct (that as you pointed out is not
specific to coherency). I'd suggest maybe to use 3) and removing ro_after_init
if you don't have access to 1) and 2). All in all, providing yet another place
for coherency flag seems a bit too much.

> 
> Signed-off-by: Dmytro Firsov 
> ---
>  xen/drivers/passthrough/arm/smmu-v3.c | 27 +++++++++++++++++++++++----
>  xen/drivers/passthrough/arm/smmu-v3.h |  7 +++++++
>  2 files changed, 30 insertions(+), 4 deletions(-)
> 
> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c
> index 5e9e3e048e..bf153227db 100644
> --- a/xen/drivers/passthrough/arm/smmu-v3.c
> +++ b/xen/drivers/passthrough/arm/smmu-v3.c
> @@ -346,10 +346,14 @@ static void queue_write(__le64 *dst, u64 *src, size_t n_dwords)
>  
>  static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent)
>  {
> +	__le64 *q_addr = Q_ENT(q, q->llq.prod);
> +
>  	if (queue_full(&q->llq))
>  		return -ENOSPC;
>  
> -	queue_write(Q_ENT(q, q->llq.prod), ent, q->ent_dwords);
> +	queue_write(q_addr, ent, q->ent_dwords);
> +	if (q->non_coherent)
> +		clean_dcache_va_range(q_addr, q->ent_dwords * sizeof(*q_addr));
I think it would be better to move the cache operation to queue_{write,read} to
avoid having to repeat them at each occurence of the helpers.

~Michal



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Date: Fri, 22 Aug 2025 10:19:27 +0200
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Subject: Re: [PATCH v2 3/3] xen/pci: add discovered PCI device at boot
To: Mykyta Poturai 
Cc: Luca Fancellu ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "Daniel P. Smith" ,
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On 22.08.2025 10:03, Mykyta Poturai wrote:
> On 21.08.25 12:08, Jan Beulich wrote:
>> On 20.08.2025 14:28, Mykyta Poturai wrote:
>>> From: Luca Fancellu 
>>>
>>> In dom0less mode, there is no dom0 that can call PCI physdev ops to
>>> register PCI devices to iommu, so it needs to be done by Xen.
>>> pci_add_device requires some default domain, we don't have hwdom, and
>>> the guests are not yet created during the PCI init phase, so use dom_io
>>> as a temporary sentinel before devices are assigned to their target
>>> domains.
>>>
>>> Rename setup_hwdom_pci_devices to setup_pci_devices and add dom0less
>>> handling to it.
>>>
>>> In pci_add_device there is a call to xsm that doesn't consider the
>>> requester of the function to be Xen itself, so add a check to skip
>>> the call if the owner domain is dom_io, since it means the call is
>>> coming directly from Xen.
>>>
>>> Signed-off-by: Luca Fancellu 
>>> Signed-off-by: Mykyta Poturai 
>>> ---
>>> (cherry picked from commit eff51e50021b75f5a50533f7de681b2ce044f5bd from
>>>   the downstream branch poc/pci-passthrough from
>>>   https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git
>>>
>>> v1->v2:
>>> * integrate add_discovered_pci_devices into existing routines
>>> * better explain the need for dom_io
>>
>> What I continue to miss is an explanation of why devices can't go to their
>> ultimate "destination" domain right away (once those have been created),
>> i.e. why the dom_io intermediary is necessary in the first place.
> 
> I've done some testing and indeed everything seems to work if we call 
> pci_add_device directly during domain construction instead of 
> reassigning them. Do you think this would be a better approach?

I think so, yes, but first and foremost you'll need Arm maintainer buyoff
on either approach (or yet another one).

Jan

> If so 
> then I guess this series needs to be dropped, and I will prepare a new 
> one with direct device assignment to DomUs.




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To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" , Stefano
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Subject: Re: [PATCH v2 08/10] xen/arm: vgic: add resource management for
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Subject: Re: [PATCH v3 19/20] xen/riscv: add support of page lookup by GFN
To: Jan Beulich 
Cc: Alistair Francis ,
 Bob Eshleman , Connor Davis
 , Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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This is a multi-part message in MIME format.
--------------LP3v1KWXJU2q3MxAZtuUzQJ3
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On 8/11/25 3:25 PM, Jan Beulich wrote:
>> + * The page_order will correspond to the order of the mapping in the page
>> + * table (i.e it could be a superpage).
>> + *
>> + * If the entry is not present, INVALID_MFN will be returned and the
>> + * page_order will be set according to the order of the invalid range.
>> + *
>> + * valid will contain the value of bit[0] (e.g valid bit) of the
>> + * entry.
>> + */
>> +static mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn,
>> +                           p2m_type_t *t,
>> +                           unsigned int *page_order,
>> +                           bool *valid)
>> +{
>> +    unsigned int level = 0;
>> +    pte_t entry, *table;
>> +    int rc;
>> +    mfn_t mfn = INVALID_MFN;
>> +    DECLARE_OFFSETS(offsets, gfn_to_gaddr(gfn));
>> +
>> +    ASSERT(p2m_is_locked(p2m));
>> +    BUILD_BUG_ON(XEN_PT_LEVEL_MAP_MASK(0) != PAGE_MASK);
> What function-wide property is this check about? Even when moved ...
>
>> +    if ( valid )
>> +        *valid = false;
>> +
>> +    /* XXX: Check if the mapping is lower than the mapped gfn */
> (Nested: What is this about?)
>
>> +    /* This gfn is higher than the highest the p2m map currently holds */
>> +    if ( gfn_x(gfn) > gfn_x(p2m->max_mapped_gfn) )
>> +    {
>> +        for ( level = P2M_ROOT_LEVEL; level; level-- )
>> +            if ( (gfn_x(gfn) & (XEN_PT_LEVEL_MASK(level) >> PAGE_SHIFT)) >
> ... into the more narrow scope where another XEN_PT_LEVEL_MASK() exists I
> can't really spot what the check is to guard against.

Missed to answer in my prev. reply to this and noticed that only during
start of reworking it.

I think it makes sense to update the comment above if condition, this is needed
to find the highest possible order by checking the base of the block mapping
is greater than the max mapped gfn as it is mentioned in the description of the
function, if the entry is not present, the function will return the order of
the invalid range.

I expect that probably it makes sense to do something similar for ->lowest_mapped_gfn
and it is a reason why /* XXX: ... */ comment exist.

~ Oleksii

>
>> +                 gfn_x(p2m->max_mapped_gfn) )
>> +                break;
>> +
>> +        goto out;
>> +    }
--------------LP3v1KWXJU2q3MxAZtuUzQJ3
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 7bit



  
    
  
  
    

    
    
    
    
    On 8/11/25 3:25 PM, Jan Beulich wrote:
    
    
    
    
    
      
    + * The page_order will correspond to the order of the mapping in the page
+ * table (i.e it could be a superpage).
+ *
+ * If the entry is not present, INVALID_MFN will be returned and the
+ * page_order will be set according to the order of the invalid range.
+ *
+ * valid will contain the value of bit[0] (e.g valid bit) of the
+ * entry.
+ */
+static mfn_t p2m_get_entry(struct p2m_domain *p2m, gfn_t gfn,
+                           p2m_type_t *t,
+                           unsigned int *page_order,
+                           bool *valid)
+{
+    unsigned int level = 0;
+    pte_t entry, *table;
+    int rc;
+    mfn_t mfn = INVALID_MFN;
+    DECLARE_OFFSETS(offsets, gfn_to_gaddr(gfn));
+
+    ASSERT(p2m_is_locked(p2m));
+    BUILD_BUG_ON(XEN_PT_LEVEL_MAP_MASK(0) != PAGE_MASK);

    What function-wide property is this check about? Even when moved ...


    +    if ( valid )
+        *valid = false;
+
+    /* XXX: Check if the mapping is lower than the mapped gfn */

    (Nested: What is this about?)


    +    /* This gfn is higher than the highest the p2m map currently holds */
+    if ( gfn_x(gfn) > gfn_x(p2m->max_mapped_gfn) )
+    {
+        for ( level = P2M_ROOT_LEVEL; level; level-- )
+            if ( (gfn_x(gfn) & (XEN_PT_LEVEL_MASK(level) >> PAGE_SHIFT)) >

    ... into the more narrow scope where another XEN_PT_LEVEL_MASK() exists I
can't really spot what the check is to guard against.
    
    
    
    
    Missed to answer in my prev. reply to this and noticed that only during
start of reworking it.

I think it makes sense to update the comment above if condition, this is needed
to find the highest possible order by checking the base of the block mapping
is greater than the max mapped gfn as it is mentioned in the description of the
function, if the entry is not present, the function will return the order of
the invalid range.

I expect that probably it makes sense to do something similar for ->lowest_mapped_gfn
and it is a reason why /* XXX: ... */ comment exist.

~ Oleksii

    
    
    
      
    

    +                 gfn_x(p2m->max_mapped_gfn) )
+                break;
+
+        goto out;
+    }
    
    
    
  


--------------LP3v1KWXJU2q3MxAZtuUzQJ3--


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CC: Stefano Stabellini , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: Re: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC addresses
 for common operations
Thread-Topic: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC
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Date: Fri, 22 Aug 2025 10:38:51 +0100
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Subject: Re: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC addresses
 for common operations
Content-Language: en-GB
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 <915641a6-8cc6-45bf-a1ee-d69b286e7d30@xen.org>
 
From: Julien Grall 
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Hi Leonid,

On 22/08/2025 10:09, Leonid Komarianskyi wrote:
 > Thank you for your close review.>>> ---
>>>    xen/arch/arm/gic-v3.c          | 99 ++++++++++++++++++++++------------
>>>    xen/arch/arm/include/asm/irq.h |  1 +
>>>    2 files changed, 67 insertions(+), 33 deletions(-)
>>>
>>> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
>>> index cd3e1acf79..8fd78aba44 100644
>>> --- a/xen/arch/arm/gic-v3.c
>>> +++ b/xen/arch/arm/gic-v3.c
>>> @@ -445,17 +445,62 @@ static void gicv3_dump_state(const struct vcpu *v)
>>>        }
>>>    }
>>> +static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32
>>> offset)
>>> +{
>>> +    switch ( irqd->irq )
>>> +    {
>>> +    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
>>> +        switch ( offset )
>>> +        {
>>> +        case GICD_ISENABLER:
>>> +        case GICD_ICENABLER:
>>> +        case GICD_ISPENDR:
>>> +        case GICD_ICPENDR:
>>> +        case GICD_ISACTIVER:
>>> +        case GICD_ICACTIVER:
>>> +            return (GICD_RDIST_SGI_BASE + offset);
>>> +        case GICD_ICFGR:
>>> +            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
>>> +        case GICD_IPRIORITYR:
>>> +            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
>>> +        default:
>>> +            break;
>>> +        }
>>> +    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
>>> +        switch ( offset )
>>> +        {
>>> +        case GICD_ISENABLER:
>>> +        case GICD_ICENABLER:
>>> +        case GICD_ISPENDR:
>>> +        case GICD_ICPENDR:
>>> +        case GICD_ISACTIVER:
>>> +        case GICD_ICACTIVER:
>>> +            return (GICD + offset + (irqd->irq / 32) * 4);
>>> +        case GICD_ICFGR:
>>> +            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
>>> +        case GICD_IROUTER:
>>> +            return (GICD + GICD_IROUTER + irqd->irq * 8);
>>> +        case GICD_IPRIORITYR:
>>> +            return (GICD + GICD_IPRIORITYR + irqd->irq);
>>> +        default:
>>> +            break;
>>> +        }
>>> +    default:
>>> +        break;
>>> +    }
>>> +
>>> +    /* Something went wrong, we shouldn't be able to reach here */
>>   > +    panic("Invalid offset 0x%x for IRQ#%d", offset, irqd->irq);
>>
>> ... I still quite concerned about using panic here. We need to try to
>> handle the error more gracefully in production.
>>
>> Cheers,
>>
> 
> I was thinking about this again, and maybe it would be better to change
> the panic into simply printing an error using printk(XENLOG_G_ERR ...)
> and adding proper checks to ensure the return value is not NULL in the
> callers.

Given the error is not meant to happen, after the printk() I would add 
an ASSERT_UNREACHABLE() so we can catch issue in DEBUG build more easily.

> Also, in the case of gicv3_peek_irq, which must return a boolean value
> (due to the generic API for gicv3_read_pending_state), we could return
> false with an additional warning message that we are unable to read the
> actual value due to incorrect parameters; therefore, we return false.
> What do you think about this approach?

It makes sense to read false as the interrupt technically doesn't exist. 
But I don't think we should add an extra warning. The one in 
get_addr_by_offset() should be sufficient.

Cheers,

-- 
Julien Grall



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Feedback-ID: i5de959fc:Fastmail
From: Sergiy Kibrik 
To: xen-devel@lists.xenproject.org
Cc: Sergiy Kibrik ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	"Daniel P. Smith" ,
	Stefano Stabellini ,
	Jan Beulich 
Subject: [XEN PATCH v1] xen/flask: limit sidtable size
Date: Fri, 22 Aug 2025 12:51:23 +0300
Message-Id: <20250822095123.998313-1-Sergiy_Kibrik@epam.com>
X-Mailer: git-send-email 2.25.1
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Currently Xen lacks a defined largest number of security IDs it can potentially
use. The number of SIDs are naturally limited by number of security contexts
provided by a given security policy, i.e. how many combination of user, role
and type there can be, and is dependant on the policy being used.
Since the policy is generally not known in advance the size of sidtable in Xen
has a rather high limit of UINT_MAX entries.

However in the embedded environment configured for safety it is desirable to
avoid guest-triggered dynamic memory allocations at runtime, or at least limit
them to some decent and predictable amounts. This patch provides a configuration
option to impose such a limit.

Signed-off-by: Sergiy Kibrik 
CC: Jan Beulich 
---
After RFC patch discussion it's been suggested to use Kconfig option
instead of estimation of sidtable size at build time:

   https://lore.kernel.org/xen-devel/20250630085559.554334-1-Sergiy_Kibrik@epam.com/

 -Sergiy
---
 xen/common/Kconfig        | 19 +++++++++++++++++++
 xen/xsm/flask/ss/sidtab.c |  8 +++++++-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/xen/common/Kconfig b/xen/common/Kconfig
index 76f9ce705f..f956a93fb3 100644
--- a/xen/common/Kconfig
+++ b/xen/common/Kconfig
@@ -418,6 +418,25 @@ config XSM_FLASK_AVC_STATS
 
 	  If unsure, say Y.
 
+config XSM_FLASK_SIDTABLE_LIMIT
+	def_bool n
+	prompt "Limit the size of SID table" if EXPERT
+	depends on XSM_FLASK
+	---help---
+	  Limit the number of security identifiers allocated and operated by Xen.
+	  This will limit the number of security contexts and heap memory
+	  allocated for SID table entries.
+
+	  If unsure, say N.
+
+config XSM_FLASK_MAX_SID
+	int "Max SID table size" if XSM_FLASK_SIDTABLE_LIMIT
+	default 512
+	help
+	  The maximum amount of SIDs allocated by Xen. Default value is
+	  approximately double the size of contexts that default Xen policy can
+	  potentially have.
+
 config XSM_FLASK_POLICY
 	bool "Compile Xen with a built-in FLASK security policy"
 	default y if "$(XEN_HAS_CHECKPOLICY)" = "y"
diff --git a/xen/xsm/flask/ss/sidtab.c b/xen/xsm/flask/ss/sidtab.c
index 69fc3389b3..1dd0700b8c 100644
--- a/xen/xsm/flask/ss/sidtab.c
+++ b/xen/xsm/flask/ss/sidtab.c
@@ -14,6 +14,12 @@
 #include "security.h"
 #include "sidtab.h"
 
+#ifdef CONFIG_XSM_FLASK_SIDTABLE_LIMIT
+#define SID_LIMIT CONFIG_XSM_FLASK_MAX_SID
+#else
+#define SID_LIMIT UINT_MAX
+#endif
+
 #define SIDTAB_HASH(sid) ((sid) & SIDTAB_HASH_MASK)
 
 #define INIT_SIDTAB_LOCK(s) spin_lock_init(&(s)->lock)
@@ -228,7 +234,7 @@ int sidtab_context_to_sid(struct sidtab *s, struct context *context,
         if ( sid )
             goto unlock_out;
         /* No SID exists for the context.  Allocate a new one. */
-        if ( s->next_sid == UINT_MAX || s->shutdown )
+        if ( s->next_sid == SID_LIMIT || s->shutdown )
         {
             ret = -ENOMEM;
             goto unlock_out;
-- 
2.25.1



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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Index: AQHcB5d9o2YugLH3UUKTUBQVCD+iyrRuh/gA
Date: Fri, 22 Aug 2025 10:00:25 +0000
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From: Leonid Komarianskyi 
To: Julien Grall , "xen-devel@lists.xenproject.org"
	
CC: Stefano Stabellini , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk 
Subject: Re: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC addresses
 for common operations
Thread-Topic: [PATCH v2 01/10] xen/arm: gicv3: refactor obtaining GIC
 addresses for common operations
Thread-Index: AQHcB5d7cCAQRdJCgUKSzBGsZt4ytbRtXheAgAEbjYCAAAhPgIAACIOA
Date: Fri, 22 Aug 2025 10:09:20 +0000
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 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 <915641a6-8cc6-45bf-a1ee-d69b286e7d30@xen.org>
 
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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Index: AQHcB5d9o2YugLH3UUKTUBQVCD+iyrRtXvkAgAE2CIA=
Date: Fri, 22 Aug 2025 10:47:03 +0000
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From: Penny Zheng 
To: 
CC: , Penny Zheng , Anthony PERARD
	, Juergen Gross , Andrew Cooper
	, Michal Orzel , Jan Beulich
	, Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , "Stefano
 Stabellini" 
Subject: [PATCH v7 02/13] cpufreq: rename "xen_cppc_para" to "xen_get_cppc_para"
Date: Fri, 22 Aug 2025 18:52:07 +0800
Message-ID: <20250822105218.3601273-3-Penny.Zheng@amd.com>
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As we are going to add "struct xen_cppc_para" in "struct xen_sysctl_pm_op" as
a new xenpm sub-op later to specifically dealing with CPPC-info, we need to
follow the naming pattern, to change the struct name to "xen_get_cppc_para",
which is more suitable than "xen_cppc_para".

Signed-off-by: Penny Zheng 
Acked-by: Jan Beulich 
Acked-by: Anthony PERARD 
---
v5 -> v6:
- new commit
---
 tools/include/xenctrl.h            | 2 +-
 xen/arch/x86/acpi/cpufreq/hwp.c    | 2 +-
 xen/include/acpi/cpufreq/cpufreq.h | 2 +-
 xen/include/public/sysctl.h        | 6 +++---
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h
index 4955981231..965d3b585a 100644
--- a/tools/include/xenctrl.h
+++ b/tools/include/xenctrl.h
@@ -1906,7 +1906,7 @@ int xc_smt_disable(xc_interface *xch);
  */
 typedef struct xen_userspace xc_userspace_t;
 typedef struct xen_ondemand xc_ondemand_t;
-typedef struct xen_cppc_para xc_cppc_para_t;
+typedef struct xen_get_cppc_para xc_cppc_para_t;
 
 struct xc_get_cpufreq_para {
     /* IN/OUT variable */
diff --git a/xen/arch/x86/acpi/cpufreq/hwp.c b/xen/arch/x86/acpi/cpufreq/hwp.c
index 36ecb0ed9d..7d14a4abd5 100644
--- a/xen/arch/x86/acpi/cpufreq/hwp.c
+++ b/xen/arch/x86/acpi/cpufreq/hwp.c
@@ -529,7 +529,7 @@ hwp_cpufreq_driver = {
 
 #ifdef CONFIG_PM_OP
 int get_hwp_para(unsigned int cpu,
-                 struct xen_cppc_para *cppc_para)
+                 struct xen_get_cppc_para *cppc_para)
 {
     const struct hwp_drv_data *data = per_cpu(hwp_drv_data, cpu);
 
diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h
index 0742aa9f44..fd530632b4 100644
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -266,7 +266,7 @@ static inline bool hwp_active(void) { return false; }
 #endif
 
 int get_hwp_para(unsigned int cpu,
-                 struct xen_cppc_para *cppc_para);
+                 struct xen_get_cppc_para *cppc_para);
 int set_hwp_para(struct cpufreq_policy *policy,
                  struct xen_set_cppc_para *set_cppc);
 
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index b7325b0f72..aafa7fcf2b 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -336,7 +336,7 @@ struct xen_ondemand {
     uint32_t up_threshold;
 };
 
-struct xen_cppc_para {
+struct xen_get_cppc_para {
     /* OUT */
     /* activity_window supported if set */
 #define XEN_SYSCTL_CPPC_FEAT_ACT_WINDOW  (1 << 0)
@@ -442,7 +442,7 @@ struct xen_set_cppc_para {
          XEN_SYSCTL_CPPC_SET_ACT_WINDOW  )
     /* IN/OUT */
     uint32_t set_params; /* bitflags for valid values */
-    /* See comments in struct xen_cppc_para. */
+    /* See comments in struct xen_get_cppc_para. */
     /* IN */
     uint32_t minimum;
     uint32_t maximum;
@@ -490,7 +490,7 @@ struct xen_get_cpufreq_para {
                 struct  xen_ondemand ondemand;
             } u;
         } s;
-        struct xen_cppc_para cppc_para;
+        struct xen_get_cppc_para cppc_para;
     } u;
 
     int32_t turbo_enabled;
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Anthony PERARD
	
Subject: [PATCH v7 03/13] tools: fix help info for "xenpm set-cpufreq-cppc"
Date: Fri, 22 Aug 2025 18:52:08 +0800
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Change "balance" to "ondemand" in help info for "xenpm set-cpufreq-cppc"

Fixes: 81ce87fc5e36 (xen/cpufreq: rename cppc preset name to "XEN_SYSCTL_CPPC_SET_PRESET_ONDEMAND")
Signed-off-by: Penny Zheng 
---
v6 -> v7:
- new commit
---
 tools/misc/xenpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
index 6ba7cb2302..6b054b10a4 100644
--- a/tools/misc/xenpm.c
+++ b/tools/misc/xenpm.c
@@ -69,7 +69,7 @@ void show_help(void)
             " set-max-cstate        |'unlimited' [|'unlimited']\n"
             "                                     set the C-State limitation ( >= 0) and\n"
             "                                     optionally the C-sub-state limitation ( >= 0)\n"
-            " set-cpufreq-cppc      [cpuid] [balance|performance|powersave] *\n"
+            " set-cpufreq-cppc      [cpuid] [ondemand|performance|powersave] *\n"
             "                                     set Hardware P-State (HWP) parameters\n"
             "                                     on CPU  or all if omitted.\n"
             "                                     optionally a preset of one of:\n"
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Anthony PERARD
	, Juergen Gross , Andrew Cooper
	, Michal Orzel , Jan Beulich
	, Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , "Stefano
 Stabellini" 
Subject: [PATCH v7 00/13] amd-cppc CPU Performance Scaling Driver
Date: Fri, 22 Aug 2025 18:52:05 +0800
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amd-cppc is the AMD CPU performance scaling driver that introduces a
new CPU frequency control mechanism on modern AMD APU and CPU series in
Xen. The new mechanism is based on Collaborative Processor Performance
Control (CPPC) which provides finer grain frequency management than
legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using
the ACPI P-states driver to manage CPU frequency and clocks with
switching only in 3 P-states. CPPC replaces the ACPI P-states controls
and allows a flexible, low-latency interface for Xen to directly
communicate the performance hints to hardware.

amd_cppc driver has 2 operation modes: autonomous (active) mode,
and non-autonomous (passive) mode. We register different CPUFreq driver
for different modes, "amd-cppc" for passive mode and "amd-cppc-epp"
for active mode.

The passive mode leverages common governors such as *ondemand*,
*performance*, etc, to manage the performance tuning. While the active mode
uses epp to provides a hint to the hardware if software wants to bias
toward performance (0x0) or energy efficiency (0xff). CPPC power algorithm
in hardware will automatically calculate the runtime workload and adjust the
realtime cpu cores frequency according to the power supply and thermal, core
voltage and some other hardware conditions.

amd-cppc is enabled on passive mode with a top-level `cpufreq=amd-cppc` option,
while users add extra `active` flag to select active mode.

With `cpufreq=amd-cppc,active`, we did a 60s sampling test to see the CPU
frequency change, through tweaking the energy_perf preference from
`xenpm set-cpufreq-cppc powersave` to `xenpm set-cpufreq-cppc performance`.
The outputs are as follows:
```
Setting CPU in powersave mode
Sampling and Outputs:
  Avg freq      580000 KHz
  Avg freq      580000 KHz
  Avg freq      580000 KHz
Setting CPU in performance mode
Sampling and Outputs:
  Avg freq      4640000 KHz
  Avg freq      4220000 KHz
  Avg freq      4640000 KHz

Penny Zheng (13):
  tools: drop "has_num" condition check for cppc mode
  cpufreq: rename "xen_cppc_para" to "xen_get_cppc_para"
  tools: fix help info for "xenpm set-cpufreq-cppc"
  xen/cpufreq: add missing default: case for x86 vendor
  xen/cpufreq: refactor cmdline "cpufreq=xxx"
  xen/cpufreq: introduce new sub-hypercall to propagate CPPC data
  xen/cpufreq: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc
    driver
  xen/cpufreq: implement amd-cppc driver for CPPC in passive mode
  xen/cpufreq: implement amd-cppc-epp driver for CPPC in active mode
  xen/cpufreq: get performance policy from governor set via xenpm
  tools/cpufreq: extract CPPC para from cpufreq para
  xen/cpufreq: bypass governor-related para for amd-cppc-epp
  xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC xen_sysctl_pm_op for amd-cppc
    driver

 docs/misc/xen-command-line.pandoc         |  14 +-
 tools/include/xenctrl.h                   |   5 +-
 tools/libs/ctrl/xc_pm.c                   |  69 +-
 tools/misc/xenpm.c                        | 104 ++-
 xen/arch/x86/acpi/cpufreq/Makefile        |   1 +
 xen/arch/x86/acpi/cpufreq/amd-cppc.c      | 774 ++++++++++++++++++++++
 xen/arch/x86/acpi/cpufreq/cpufreq.c       |  76 ++-
 xen/arch/x86/acpi/cpufreq/hwp.c           |   2 +-
 xen/arch/x86/cpu/amd.c                    |   8 +-
 xen/arch/x86/include/asm/amd.h            |   2 +
 xen/arch/x86/include/asm/msr-index.h      |   6 +
 xen/arch/x86/platform_hypercall.c         |  19 +
 xen/arch/x86/x86_64/cpufreq.c             |  19 +
 xen/arch/x86/x86_64/platform_hypercall.c  |   3 +
 xen/drivers/acpi/pm-op.c                  |  48 +-
 xen/drivers/acpi/pmstat.c                 |   4 +
 xen/drivers/cpufreq/cpufreq.c             | 204 +++++-
 xen/drivers/cpufreq/utility.c             |  15 +
 xen/include/acpi/cpufreq/cpufreq.h        |  28 +-
 xen/include/acpi/cpufreq/processor_perf.h |  14 +-
 xen/include/public/platform.h             |  26 +
 xen/include/public/sysctl.h               |  15 +-
 xen/include/xen/pmstat.h                  |   5 +
 xen/include/xlat.lst                      |   1 +
 24 files changed, 1368 insertions(+), 94 deletions(-)
 create mode 100644 xen/arch/x86/acpi/cpufreq/amd-cppc.c

-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Anthony PERARD
	, Juergen Gross , Jan Beulich
	
Subject: [PATCH v7 01/13] tools: drop "has_num" condition check for cppc mode
Date: Fri, 22 Aug 2025 18:52:06 +0800
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In `xenpm get-cpufreq-para `, ->freq_num and ->cpu_num checking are
tied together via variable "has_num", while ->freq_num only has non-zero value
when cpufreq driver in legacy P-states mode.

So we drop the "has_num" condition check, and mirror the ->gov_num check for
both ->freq_num and ->cpu_num in xc_get_cpufreq_para().

Signed-off-by: Penny Zheng 
Reviewed-by: Jan Beulich 
Reviewed-by: Anthony PERARD 
---
v3 -> v4:
- drop the "has_num" condition check
---
v4 -> v5:
- refactor title and commit
- make all three pieces (xc_hypercall_bounce_pre()) be as similar as possible
---
v5 -> v6:
- move set_xen_guest_handle() up to the bottom of the identical conditional
---
 tools/libs/ctrl/xc_pm.c | 41 +++++++++++++++++++++--------------------
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/tools/libs/ctrl/xc_pm.c b/tools/libs/ctrl/xc_pm.c
index 1f2430cac2..6fda973f1f 100644
--- a/tools/libs/ctrl/xc_pm.c
+++ b/tools/libs/ctrl/xc_pm.c
@@ -210,33 +210,36 @@ int xc_get_cpufreq_para(xc_interface *xch, int cpuid,
     DECLARE_NAMED_HYPERCALL_BOUNCE(scaling_available_governors,
 			 user_para->scaling_available_governors,
 			 user_para->gov_num * CPUFREQ_NAME_LEN * sizeof(char), XC_HYPERCALL_BUFFER_BOUNCE_BOTH);
-    bool has_num = user_para->cpu_num && user_para->freq_num;
 
-    if ( has_num )
+    if ( (user_para->cpu_num && !user_para->affected_cpus) ||
+         (user_para->freq_num && !user_para->scaling_available_frequencies) ||
+         (user_para->gov_num && !user_para->scaling_available_governors) )
+    {
+        errno = EINVAL;
+        return -1;
+    }
+    if ( user_para->cpu_num )
     {
-        if ( (!user_para->affected_cpus)                    ||
-             (!user_para->scaling_available_frequencies)    ||
-             (user_para->gov_num && !user_para->scaling_available_governors) )
-        {
-            errno = EINVAL;
-            return -1;
-        }
         ret = xc_hypercall_bounce_pre(xch, affected_cpus);
         if ( ret )
             return ret;
+        set_xen_guest_handle(sys_para->affected_cpus, affected_cpus);
+    }
+    if ( user_para->freq_num )
+    {
         ret = xc_hypercall_bounce_pre(xch, scaling_available_frequencies);
         if ( ret )
             goto unlock_2;
-        if ( user_para->gov_num )
-            ret = xc_hypercall_bounce_pre(xch, scaling_available_governors);
+        set_xen_guest_handle(sys_para->scaling_available_frequencies,
+                             scaling_available_frequencies);
+    }
+    if ( user_para->gov_num )
+    {
+        ret = xc_hypercall_bounce_pre(xch, scaling_available_governors);
         if ( ret )
             goto unlock_3;
-
-        set_xen_guest_handle(sys_para->affected_cpus, affected_cpus);
-        set_xen_guest_handle(sys_para->scaling_available_frequencies, scaling_available_frequencies);
-        if ( user_para->gov_num )
-            set_xen_guest_handle(sys_para->scaling_available_governors,
-                                 scaling_available_governors);
+        set_xen_guest_handle(sys_para->scaling_available_governors,
+                             scaling_available_governors);
     }
 
     sysctl.cmd = XEN_SYSCTL_pm_op;
@@ -256,9 +259,7 @@ int xc_get_cpufreq_para(xc_interface *xch, int cpuid,
             user_para->gov_num  = sys_para->gov_num;
         }
 
-        if ( has_num )
-            goto unlock_4;
-        return ret;
+        goto unlock_4;
     }
     else
     {
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	
Subject: [PATCH v7 05/13] xen/cpufreq: refactor cmdline "cpufreq=xxx"
Date: Fri, 22 Aug 2025 18:52:10 +0800
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A helper function handle_cpufreq_cmdline() is introduced to tidy different
handling pathes.
We also add a new helper cpufreq_opts_contain() to ignore redundant setting,
like "cpufreq=hwp;hwp;xen"
As only slot 0 of cpufreq_xen_opts[] needs explicit initializing with
non-zero CPUFREQ_xen, dropping full array initializer could avoid touching
initializer every time it grows

Signed-off-by: Penny Zheng 
---
v2 -> v3:
- new commit
---
v3 -> v4:
- add one single helper to do the tidy work
- ignore and warn user redundant setting
---
v4 -> v5:
- make "cpufreq_opts_str" static and the string literals end up in
  .init.rodata.
- use "CPUFREQ_xxx" as array slot index
- blank line between non-fall-through case blocks
---
v5 -> v6:
- change to "while ( count-- )"
- remove unnecessary warning
- add an assertion to ensure not overruning the array
- add ASSERT_UNREACHABLE()
- check ret of handle_cpufreq_cmdline() and error out
---
v6 -> v7:
- remove overrun assertion as we already have check in setup_cpufreq_option()
- drop full array initializer
---
 xen/drivers/cpufreq/cpufreq.c | 55 +++++++++++++++++++++++++++--------
 1 file changed, 43 insertions(+), 12 deletions(-)

diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c
index efba141418..de17e53708 100644
--- a/xen/drivers/cpufreq/cpufreq.c
+++ b/xen/drivers/cpufreq/cpufreq.c
@@ -64,12 +64,49 @@ LIST_HEAD_READ_MOSTLY(cpufreq_governor_list);
 /* set xen as default cpufreq */
 enum cpufreq_controller cpufreq_controller = FREQCTL_xen;
 
-enum cpufreq_xen_opt __initdata cpufreq_xen_opts[2] = { CPUFREQ_xen,
-                                                        CPUFREQ_none };
+enum cpufreq_xen_opt __initdata cpufreq_xen_opts[2] = { CPUFREQ_xen };
 unsigned int __initdata cpufreq_xen_cnt = 1;
 
 static int __init cpufreq_cmdline_parse(const char *s, const char *e);
 
+static bool __init cpufreq_opts_contain(enum cpufreq_xen_opt option)
+{
+    unsigned int count = cpufreq_xen_cnt;
+
+    while ( count-- )
+    {
+        if ( cpufreq_xen_opts[count] == option )
+            return true;
+    }
+
+    return false;
+}
+
+static int __init handle_cpufreq_cmdline(enum cpufreq_xen_opt option)
+{
+    int ret = 0;
+
+    if ( cpufreq_opts_contain(option) )
+        return 0;
+
+    cpufreq_controller = FREQCTL_xen;
+    cpufreq_xen_opts[cpufreq_xen_cnt++] = option;
+    switch ( option )
+    {
+    case CPUFREQ_hwp:
+    case CPUFREQ_xen:
+        xen_processor_pmbits |= XEN_PROCESSOR_PM_PX;
+        break;
+
+    default:
+        ASSERT_UNREACHABLE();
+        ret = -EINVAL;
+        break;
+    }
+
+    return ret;
+}
+
 static int __init cf_check setup_cpufreq_option(const char *str)
 {
     const char *arg = strpbrk(str, ",:;");
@@ -113,21 +150,15 @@ static int __init cf_check setup_cpufreq_option(const char *str)
 
         if ( choice > 0 || !cmdline_strcmp(str, "xen") )
         {
-            xen_processor_pmbits |= XEN_PROCESSOR_PM_PX;
-            cpufreq_controller = FREQCTL_xen;
-            cpufreq_xen_opts[cpufreq_xen_cnt++] = CPUFREQ_xen;
-            ret = 0;
-            if ( arg[0] && arg[1] )
+            ret = handle_cpufreq_cmdline(CPUFREQ_xen);
+            if ( !ret && arg[0] && arg[1] )
                 ret = cpufreq_cmdline_parse(arg + 1, end);
         }
         else if ( IS_ENABLED(CONFIG_INTEL) && choice < 0 &&
                   !cmdline_strcmp(str, "hwp") )
         {
-            xen_processor_pmbits |= XEN_PROCESSOR_PM_PX;
-            cpufreq_controller = FREQCTL_xen;
-            cpufreq_xen_opts[cpufreq_xen_cnt++] = CPUFREQ_hwp;
-            ret = 0;
-            if ( arg[0] && arg[1] )
+            ret = handle_cpufreq_cmdline(CPUFREQ_hwp);
+            if ( !ret && arg[0] && arg[1] )
                 ret = hwp_cmdline_parse(arg + 1, end);
         }
         else
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	, Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v7 04/13] xen/cpufreq: add missing default: case for x86 vendor
Date: Fri, 22 Aug 2025 18:52:09 +0800
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Since we are missing default case for x86 vendor, there is possibility (i.e.
new vendor introduced) that we will return successfully while missing the
whole cpufreq driver initialization process.
Move "ret = -ENOENTRY" forward to cover default case for x86 vendor, and
add error log

Signed-off-by: Penny Zheng 
---
v6 -> v7:
- new commit
---
 xen/arch/x86/acpi/cpufreq/cpufreq.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c
index d18735c7ae..e227376bab 100644
--- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
+++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
@@ -131,11 +131,11 @@ static int __init cf_check cpufreq_driver_init(void)
 
     if ( cpufreq_controller == FREQCTL_xen )
     {
+        ret = -ENOENT;
+
         switch ( boot_cpu_data.x86_vendor )
         {
         case X86_VENDOR_INTEL:
-            ret = -ENOENT;
-
             for ( unsigned int i = 0; i < cpufreq_xen_cnt; i++ )
             {
                 switch ( cpufreq_xen_opts[i] )
@@ -162,6 +162,10 @@ static int __init cf_check cpufreq_driver_init(void)
         case X86_VENDOR_HYGON:
             ret = IS_ENABLED(CONFIG_AMD) ? powernow_register_driver() : -ENODEV;
             break;
+
+        default:
+            printk(XENLOG_ERR "Cpufreq: unsupported x86 vendor\n");
+            break;
         }
     }
 
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , "Julien
 Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?=
	, Stefano Stabellini 
Subject: [PATCH v7 07/13] xen/cpufreq: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc driver
Date: Fri, 22 Aug 2025 18:52:12 +0800
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Users need to set "cpufreq=amd-cppc" in xen cmdline to enable amd-cppc driver,
which selects ACPI Collaborative Performance and Power Control (CPPC) on
supported AMD hardware to provide a finer grained frequency control mechanism.
`verbose` option can also be included to support verbose print.

When users setting "cpufreq=amd-cppc", a new amd-cppc driver
shall be registered and used. All hooks for amd-cppc driver are transiently
missing, and we temporarily make registration fail with -EOPNOTSUPP here. It
will be fixed along with the implementation.

New xen-pm internal flag XEN_PROCESSOR_PM_CPPC is introduced, to stand for
cpufreq driver in CPPC mode. We define XEN_PROCESSOR_PM_CPPC 0x100, as it is
the next value to use after 8-bits wide public xen-pm options. We also add
sanity check on compile time. All XEN_PROCESSOR_PM_xxx checking shall be
updated to consider "XEN_PROCESSOR_PM_CPPC" too.

XEN_PROCESSOR_PM_CPPC and XEN_PROCESSOR_PM_PX are firstly set when Xen parsed
relative driver signature from xen cmdline, and will become exclusive after
cpufreq driver registration. It is because that platform could not support
both or mixed mode (CPPC & legacy Px) operations, and only one cpufreq driver
could be registerd in Xen at one time, such as on AMD, it is either amd-cppc
or legacy P-states driver.
Xen rely on XEN_PROCESSOR_PM_CPPC flag to tell current cpufreq driver is in
CPPC mode, and accepts relative hypercall. It will neglect Px request and
yields success.

Signed-off-by: Penny Zheng 
---
v1 -> v2:
- Obey to alphabetic sorting and also strict it with CONFIG_AMD
- Remove unnecessary empty comment line
- Use __initconst_cf_clobber for pre-filled structure cpufreq_driver
- Make new switch-case code apply to Hygon CPUs too
- Change ENOSYS with EOPNOTSUPP
- Blanks around binary operator
- Change all amd_/-pstate defined values to amd_/-cppc
---
v2 -> v3
- refactor too long lines
- Make sure XEN_PROCESSOR_PM_PX and XEN_PROCESSOR_PM_CPPC incompatible flags
after cpufreq register registrantion
---
v3 -> v4:
- introduce XEN_PROCESSOR_PM_CPPC in xen internal header
- complement "Hygon" in log message
- remove unnecessary if()
- grow cpufreq_xen_opts[] array
---
v4 -> v5:
- remove XEN_PROCESSOR_PM_xxx flag sanitization from individual driver
- prefer ! over "== 0" in purely boolean contexts
- Blank line between non-fall-through case blocks
- add build-time checking between internal and public XEN_PROCESSOR_PM_*
values
- define XEN_PROCESSOR_PM_CPPC with 0x100, as it is the next value to use
after public interface, and public mask SIF_PM_MASK is 8 bits wide.
- as Dom0 will send the CPPC/Px data whenever it could, the return value shall
be 0 instead of -ENOSYS/EOPNOTSUP when platform doesn't require these data.
---
v5 -> v6:
- do not register the driver when all hooks are NULL
- refactor the subject and commit message
- move pruning of xen_processor_pmbits into generic space
- add comment and build-time check for XEN_PROCESSOR_PM_CPPC
---
v6 -> v7:
- reomove pointless initializer for "unsigned int i"
- move closing brace into its own line
- insertion always at the bottom
- change to use #ifdef CONFIG_AMD code wrapping
---
 docs/misc/xen-command-line.pandoc         |  7 ++-
 xen/arch/x86/acpi/cpufreq/Makefile        |  1 +
 xen/arch/x86/acpi/cpufreq/amd-cppc.c      | 59 ++++++++++++++++++++
 xen/arch/x86/acpi/cpufreq/cpufreq.c       | 68 ++++++++++++++++++++++-
 xen/arch/x86/platform_hypercall.c         | 14 +++++
 xen/drivers/acpi/pm-op.c                  |  3 +-
 xen/drivers/cpufreq/cpufreq.c             | 13 ++++-
 xen/include/acpi/cpufreq/cpufreq.h        |  6 +-
 xen/include/acpi/cpufreq/processor_perf.h | 10 ++++
 9 files changed, 174 insertions(+), 7 deletions(-)
 create mode 100644 xen/arch/x86/acpi/cpufreq/amd-cppc.c

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index a75b6c9301..3916cc81f6 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -515,7 +515,7 @@ If set, force use of the performance counters for oprofile, rather than detectin
 available support.
 
 ### cpufreq
-> `= none | {{  | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]]`
+> `= none | {{  | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[verbose]]`
 
 > Default: `xen`
 
@@ -526,7 +526,7 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels.
 * `` and `` are integers which represent max and min processor frequencies
   respectively.
 * `verbose` option can be included as a string or also as `verbose=`
-  for `xen`.  It is a boolean for `hwp`.
+  for `xen`.  It is a boolean for `hwp` and `amd-cppc`.
 * `hwp` selects Hardware-Controlled Performance States (HWP) on supported Intel
   hardware.  HWP is a Skylake+ feature which provides better CPU power
   management.  The default is disabled.  If `hwp` is selected, but hardware
@@ -534,6 +534,9 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels.
 * `` is a boolean to enable Hardware Duty Cycling (HDC).  HDC enables the
   processor to autonomously force physical package components into idle state.
   The default is enabled, but the option only applies when `hwp` is enabled.
+* `amd-cppc` selects ACPI Collaborative Performance and Power Control (CPPC)
+  on supported AMD hardware to provide finer grained frequency control
+  mechanism. The default is disabled.
 
 There is also support for `;`-separated fallback options:
 `cpufreq=hwp;xen,verbose`.  This first tries `hwp` and falls back to `xen` if
diff --git a/xen/arch/x86/acpi/cpufreq/Makefile b/xen/arch/x86/acpi/cpufreq/Makefile
index e7dbe434a8..a2ba34bda0 100644
--- a/xen/arch/x86/acpi/cpufreq/Makefile
+++ b/xen/arch/x86/acpi/cpufreq/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_INTEL) += acpi.o
+obj-$(CONFIG_AMD) += amd-cppc.o
 obj-y += cpufreq.o
 obj-$(CONFIG_INTEL) += hwp.o
 obj-$(CONFIG_AMD) += powernow.o
diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
new file mode 100644
index 0000000000..3377783f7e
--- /dev/null
+++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * amd-cppc.c - AMD Processor CPPC Frequency Driver
+ *
+ * Copyright (C) 2025 Advanced Micro Devices, Inc. All Rights Reserved.
+ *
+ * Author: Penny Zheng 
+ *
+ * AMD CPPC cpufreq driver introduces a new CPU performance scaling design
+ * for AMD processors using the ACPI Collaborative Performance and Power
+ * Control (CPPC) feature which provides finer grained frequency control range.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static bool __init amd_cppc_handle_option(const char *s, const char *end)
+{
+    int ret;
+
+    ret = parse_boolean("verbose", s, end);
+    if ( ret >= 0 )
+    {
+        cpufreq_verbose = ret;
+        return true;
+    }
+
+    return false;
+}
+
+int __init amd_cppc_cmdline_parse(const char *s, const char *e)
+{
+    do {
+        const char *end = strpbrk(s, ",;");
+
+        if ( !amd_cppc_handle_option(s, end) )
+        {
+            printk(XENLOG_WARNING
+                   "cpufreq/amd-cppc: option '%.*s' not recognized\n",
+                   (int)((end ?: e) - s), s);
+
+            return -EINVAL;
+        }
+
+        s = end ? end + 1 : NULL;
+    } while ( s && s < e );
+
+    return 0;
+}
+
+int __init amd_cppc_register_driver(void)
+{
+    if ( !cpu_has_cppc )
+        return -ENODEV;
+
+    return -EOPNOTSUPP;
+}
diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c
index e227376bab..6a0d9b1092 100644
--- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
+++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
@@ -131,12 +131,13 @@ static int __init cf_check cpufreq_driver_init(void)
 
     if ( cpufreq_controller == FREQCTL_xen )
     {
+        unsigned int i;
         ret = -ENOENT;
 
         switch ( boot_cpu_data.x86_vendor )
         {
         case X86_VENDOR_INTEL:
-            for ( unsigned int i = 0; i < cpufreq_xen_cnt; i++ )
+            for ( i = 0; i < cpufreq_xen_cnt; i++ )
             {
                 switch ( cpufreq_xen_opts[i] )
                 {
@@ -151,6 +152,11 @@ static int __init cf_check cpufreq_driver_init(void)
                 case CPUFREQ_none:
                     ret = 0;
                     break;
+
+                default:
+                    printk(XENLOG_WARNING
+                           "Unsupported cpufreq driver for vendor Intel\n");
+                    break;
                 }
 
                 if ( !ret || ret == -EBUSY )
@@ -160,13 +166,71 @@ static int __init cf_check cpufreq_driver_init(void)
 
         case X86_VENDOR_AMD:
         case X86_VENDOR_HYGON:
-            ret = IS_ENABLED(CONFIG_AMD) ? powernow_register_driver() : -ENODEV;
+#ifdef CONFIG_AMD
+            for ( i = 0; i < cpufreq_xen_cnt; i++ )
+            {
+                switch ( cpufreq_xen_opts[i] )
+                {
+                case CPUFREQ_xen:
+                    ret = powernow_register_driver();
+                    break;
+
+                case CPUFREQ_amd_cppc:
+                    ret = amd_cppc_register_driver();
+                    break;
+
+                case CPUFREQ_none:
+                    ret = 0;
+                    break;
+
+                default:
+                    printk(XENLOG_WARNING
+                           "Unsupported cpufreq driver for vendor AMD or Hygon\n");
+                    break;
+                }
+
+                if ( !ret || ret == -EBUSY )
+                    break;
+            }
+#else
+            ret = -ENODEV;
+#endif /* CONFIG_AMD */
             break;
 
         default:
             printk(XENLOG_ERR "Cpufreq: unsupported x86 vendor\n");
             break;
         }
+
+        /*
+         * After successful cpufreq driver registeration, XEN_PROCESSOR_PM_CPPC
+         * and XEN_PROCESSOR_PM_PX shall become exclusive flags.
+         */
+        if ( !ret )
+        {
+            ASSERT(i < cpufreq_xen_cnt);
+            switch ( cpufreq_xen_opts[i] )
+            {
+            case CPUFREQ_amd_cppc:
+                xen_processor_pmbits &= ~XEN_PROCESSOR_PM_PX;
+                break;
+
+            case CPUFREQ_hwp:
+            case CPUFREQ_xen:
+                xen_processor_pmbits &= ~XEN_PROCESSOR_PM_CPPC;
+                break;
+
+            default:
+                break;
+            }
+        }
+        else if ( ret != -EBUSY )
+            /*
+             * No cpufreq driver gets registered, clear both
+             * XEN_PROCESSOR_PM_CPPC and XEN_PROCESSOR_PM_PX
+             */
+             xen_processor_pmbits &= ~(XEN_PROCESSOR_PM_CPPC |
+                                       XEN_PROCESSOR_PM_PX);
     }
 
     return ret;
diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c
index 42b3b8b95a..cf64b8a622 100644
--- a/xen/arch/x86/platform_hypercall.c
+++ b/xen/arch/x86/platform_hypercall.c
@@ -546,6 +546,8 @@ ret_t do_platform_op(
                 ret = 0;
                 break;
             }
+            /* Xen doesn't support mixed mode */
+            ASSERT(!(xen_processor_pmbits & XEN_PROCESSOR_PM_CPPC));
 
             ret = set_px_pminfo(op->u.set_pminfo.id, &op->u.set_pminfo.u.perf);
             break;
@@ -578,6 +580,18 @@ ret_t do_platform_op(
         }
 
         case XEN_PM_CPPC:
+            if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_CPPC) )
+            {
+                /*
+                 * Neglect CPPC-info when registered cpufreq driver
+                 * isn't in CPPC mode
+                 */
+                ret = 0;
+                break;
+            }
+            /* Xen doesn't support mixed mode */
+            ASSERT(!(xen_processor_pmbits & XEN_PROCESSOR_PM_PX));
+
             ret = set_cppc_pminfo(op->u.set_pminfo.id,
                                   &op->u.set_pminfo.u.cppc_data);
             break;
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index eab64bb46e..427656c48c 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -351,7 +351,8 @@ int do_pm_op(struct xen_sysctl_pm_op *op)
     switch ( op->cmd & PM_PARA_CATEGORY_MASK )
     {
     case CPUFREQ_PARA:
-        if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_PX) )
+        if ( !(xen_processor_pmbits & (XEN_PROCESSOR_PM_PX |
+                                       XEN_PROCESSOR_PM_CPPC)) )
             return -ENODEV;
         if ( !pmpt || !(pmpt->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
             return -EINVAL;
diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c
index 046a366d7f..41e0da3b77 100644
--- a/xen/drivers/cpufreq/cpufreq.c
+++ b/xen/drivers/cpufreq/cpufreq.c
@@ -65,7 +65,7 @@ LIST_HEAD_READ_MOSTLY(cpufreq_governor_list);
 /* set xen as default cpufreq */
 enum cpufreq_controller cpufreq_controller = FREQCTL_xen;
 
-enum cpufreq_xen_opt __initdata cpufreq_xen_opts[2] = { CPUFREQ_xen };
+enum cpufreq_xen_opt __initdata cpufreq_xen_opts[3] = { CPUFREQ_xen };
 unsigned int __initdata cpufreq_xen_cnt = 1;
 
 static int __init cpufreq_cmdline_parse(const char *s, const char *e);
@@ -99,6 +99,10 @@ static int __init handle_cpufreq_cmdline(enum cpufreq_xen_opt option)
         xen_processor_pmbits |= XEN_PROCESSOR_PM_PX;
         break;
 
+    case CPUFREQ_amd_cppc:
+        xen_processor_pmbits |= XEN_PROCESSOR_PM_CPPC;
+        break;
+
     default:
         ASSERT_UNREACHABLE();
         ret = -EINVAL;
@@ -162,6 +166,13 @@ static int __init cf_check setup_cpufreq_option(const char *str)
             if ( !ret && arg[0] && arg[1] )
                 ret = hwp_cmdline_parse(arg + 1, end);
         }
+        else if ( IS_ENABLED(CONFIG_AMD) && choice < 0 &&
+                  !cmdline_strcmp(str, "amd-cppc") )
+        {
+            ret = handle_cpufreq_cmdline(CPUFREQ_amd_cppc);
+            if ( !ret && arg[0] && arg[1] )
+                ret = amd_cppc_cmdline_parse(arg + 1, end);
+        }
         else
             ret = -EINVAL;
 
diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h
index fd530632b4..5d4881eea8 100644
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -26,8 +26,9 @@ enum cpufreq_xen_opt {
     CPUFREQ_none,
     CPUFREQ_xen,
     CPUFREQ_hwp,
+    CPUFREQ_amd_cppc,
 };
-extern enum cpufreq_xen_opt cpufreq_xen_opts[2];
+extern enum cpufreq_xen_opt cpufreq_xen_opts[3];
 extern unsigned int cpufreq_xen_cnt;
 struct cpufreq_governor;
 
@@ -272,4 +273,7 @@ int set_hwp_para(struct cpufreq_policy *policy,
 
 int acpi_cpufreq_register(void);
 
+int amd_cppc_cmdline_parse(const char *s, const char *e);
+int amd_cppc_register_driver(void);
+
 #endif /* __XEN_CPUFREQ_PM_H__ */
diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/cpufreq/processor_perf.h
index e6576314f0..0a87bc0384 100644
--- a/xen/include/acpi/cpufreq/processor_perf.h
+++ b/xen/include/acpi/cpufreq/processor_perf.h
@@ -5,6 +5,16 @@
 #include 
 #include 
 
+/*
+ * Internal xen-pm options
+ * They are extension to public xen-pm options (XEN_PROCESSOR_PM_xxx) defined
+ * in public/platform.h, guarded by SIF_PM_MASK
+ */
+#define XEN_PROCESSOR_PM_CPPC   0x100
+#if XEN_PROCESSOR_PM_CPPC & MASK_EXTR(~0, SIF_PM_MASK)
+# error "XEN_PROCESSOR_PM_CPPC shall not occupy bits reserved for public xen-pm options"
+#endif
+
 #define XEN_CPPC_INIT 0x40000000U
 #define XEN_PX_INIT   0x80000000U
 
-- 
2.34.1



From xen-devel-bounces@lists.xenproject.org Fri Aug 22 10:53:03 2025
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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	, Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD
	, Michal Orzel , "Julien
 Grall" , Stefano Stabellini 
Subject: [PATCH v7 06/13] xen/cpufreq: introduce new sub-hypercall to propagate CPPC data
Date: Fri, 22 Aug 2025 18:52:11 +0800
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In order to provide backward compatibility with existing governors
that represent performance as frequency, like ondemand, the _CPC
table can optionally provide processor frequency range values, Lowest
frequency and Nominal frequency, to let OS use Lowest Frequency/
Performance and Nominal Frequency/Performance as anchor points to
create linear mapping of CPPC performance to CPU frequency.

As Xen is uncapable of parsing the ACPI dynamic table, we'd like to
introduce a new sub-hypercall "XEN_PM_CPPC" to propagate required CPPC
data from dom0 kernel to Xen.
In the according handler set_cppc_pminfo(), we do _CPC and _PSD
sanitization check, as both _PSD and _CPC info are necessary for correctly
initializing cpufreq cores in CPPC mode.
Users shall be warned that if we failed at this point,
no fallback scheme, like legacy P-state could be switched to.

A new flag "XEN_CPPC_INIT" is also introduced for cpufreq core initialised in
CPPC mode. Then all .init flag checking shall be updated to
consider "XEN_CPPC_INIT" too.

We want to bypass construction of px statistic info in cpufreq_statistic_init()
for CPPC mode, while not bypassing cpufreq_statistic_lock initialization for a
good reason. The same check is unnecessary for cpufreq_statistic_exit(),
since it has already been covered by px statistic variable
"cpufreq_statistic_data" check

Signed-off-by: Penny Zheng 
---
v1 -> v2:
- Remove unnecessary figure braces
- Pointer-to-const for print_CPPC and set_cppc_pminfo
- Structure allocation shall use xvzalloc()
- Unnecessary memcpy(), and change it to a (type safe) structure assignment
- Add comment for struct xen_processor_cppc, and keep the chosen fields
in the order _CPC has them
- Obey to alphabetic sorting, and prefix compat structures with ? instead
of !
---
v2 -> v3:
- Trim too long line
- Re-place set_cppc_pminfo() past set_px_pminfo()
- Fix Misra violations: Declaration and definition ought to agree
in parameter names
- Introduce a new flag XEN_PM_CPPC to reflect processor initialised in CPPC
mode
---
v3 -> v4:
- Refactor commit message
- make "acpi_id" unsigned int
- Add warning message when cpufreq_cpu_init() failed only under debug mode
- Expand "struct xen_processor_cppc" to include _PSD and shared type
- add sanity check for ACPI CPPC data
---
v4 -> v5:
- remove the ordering check between lowest_nonlinear_perf and lowest_perf
- use printk_once() for cppc perf value warning
- complement comment for cppc perf value check
- remove redundant check and pointless parenthesizing
- use dprintk() for warning under #ifndef NDEBUG
- refactor warning message when having non-zero ret of cpufreq_cpu_init()
- With introduction of "struct xen_psd_package" in "struct xen_processor_cppc",
use ! and the respective XLAT_* macro(s) to wrap.
---
v5 -> v6:
- remove unnecessary input parameter check
- use print_once() instead of dprintk() and reword the log message
- adhere to designated comment style
- relative ordering shall be consistent between different declaration groups
- add alphabetically in xlat.lst
- in get_cpufreq_para(), add must-zero check for ->perf.state_count in CPPC mode
---
v6 -> v7:
- move XEN_PX_INIT to its own line to be neater
- change to "Set CPU%d (ACPI ID %u) CPPC state info:\n"
- convert two-if()s into a single one
- make the extra indentation a proper level (i.e. 4 blanks)
- only both lowest_mhz and nominal_mhz provided, the check is meaningful
- as cpuid is int, so print with %d
- only need to make sure the maximum value highest_perf is smaller than
UINT8_MAX
- make XEN_CPPC_* definition show how it works
- add code comment
---
 xen/arch/x86/platform_hypercall.c         |   5 +
 xen/arch/x86/x86_64/cpufreq.c             |  19 ++++
 xen/arch/x86/x86_64/platform_hypercall.c  |   3 +
 xen/drivers/acpi/pm-op.c                  |   6 +-
 xen/drivers/acpi/pmstat.c                 |   4 +
 xen/drivers/cpufreq/cpufreq.c             | 124 +++++++++++++++++++++-
 xen/include/acpi/cpufreq/processor_perf.h |   4 +-
 xen/include/public/platform.h             |  26 +++++
 xen/include/xen/pmstat.h                  |   5 +
 xen/include/xlat.lst                      |   1 +
 10 files changed, 192 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c
index 3eba791889..42b3b8b95a 100644
--- a/xen/arch/x86/platform_hypercall.c
+++ b/xen/arch/x86/platform_hypercall.c
@@ -577,6 +577,11 @@ ret_t do_platform_op(
             break;
         }
 
+        case XEN_PM_CPPC:
+            ret = set_cppc_pminfo(op->u.set_pminfo.id,
+                                  &op->u.set_pminfo.u.cppc_data);
+            break;
+
         default:
             ret = -EINVAL;
             break;
diff --git a/xen/arch/x86/x86_64/cpufreq.c b/xen/arch/x86/x86_64/cpufreq.c
index e4f3d5b436..8d57f67c2e 100644
--- a/xen/arch/x86/x86_64/cpufreq.c
+++ b/xen/arch/x86/x86_64/cpufreq.c
@@ -54,3 +54,22 @@ int compat_set_px_pminfo(uint32_t acpi_id,
 
     return set_px_pminfo(acpi_id, xen_perf);
 }
+
+int compat_set_cppc_pminfo(unsigned int acpi_id,
+                           const struct compat_processor_cppc *cppc_data)
+
+{
+    struct xen_processor_cppc *xen_cppc;
+    unsigned long xlat_page_current;
+
+    xlat_malloc_init(xlat_page_current);
+
+    xen_cppc = xlat_malloc_array(xlat_page_current,
+                                 struct xen_processor_cppc, 1);
+    if ( unlikely(xen_cppc == NULL) )
+        return -EFAULT;
+
+    XLAT_processor_cppc(xen_cppc, cppc_data);
+
+    return set_cppc_pminfo(acpi_id, xen_cppc);
+}
diff --git a/xen/arch/x86/x86_64/platform_hypercall.c b/xen/arch/x86/x86_64/platform_hypercall.c
index 9ab631c17f..0288f68df9 100644
--- a/xen/arch/x86/x86_64/platform_hypercall.c
+++ b/xen/arch/x86/x86_64/platform_hypercall.c
@@ -14,6 +14,9 @@ EMIT_FILE;
 #define efi_get_info        efi_compat_get_info
 #define efi_runtime_call(x) efi_compat_runtime_call(x)
 
+#define xen_processor_cppc  compat_processor_cppc
+#define set_cppc_pminfo     compat_set_cppc_pminfo
+
 #define xen_processor_performance compat_processor_performance
 #define set_px_pminfo       compat_set_px_pminfo
 
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index 9a1970df34..eab64bb46e 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -91,7 +91,9 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
     pmpt = processor_pminfo[op->cpuid];
     policy = per_cpu(cpufreq_cpu_policy, op->cpuid);
 
-    if ( !pmpt || !pmpt->perf.states ||
+    if ( !pmpt ||
+         ((pmpt->init & XEN_PX_INIT) && !pmpt->perf.states) ||
+         ((pmpt->init & XEN_CPPC_INIT) && pmpt->perf.state_count) ||
          !policy || !policy->governor )
         return -EINVAL;
 
@@ -351,7 +353,7 @@ int do_pm_op(struct xen_sysctl_pm_op *op)
     case CPUFREQ_PARA:
         if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_PX) )
             return -ENODEV;
-        if ( !pmpt || !(pmpt->init & XEN_PX_INIT) )
+        if ( !pmpt || !(pmpt->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
             return -EINVAL;
         break;
     }
diff --git a/xen/drivers/acpi/pmstat.c b/xen/drivers/acpi/pmstat.c
index 4fae0c14af..0f31736df2 100644
--- a/xen/drivers/acpi/pmstat.c
+++ b/xen/drivers/acpi/pmstat.c
@@ -108,6 +108,10 @@ int cpufreq_statistic_init(unsigned int cpu)
     if ( !pmpt )
         return -EINVAL;
 
+    /* Only need to initialize in Px mode */
+    if ( !(pmpt->init & XEN_PX_INIT) )
+        return 0;
+
     spin_lock(cpufreq_statistic_lock);
 
     pxpt = per_cpu(cpufreq_statistic_data, cpu);
diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c
index de17e53708..046a366d7f 100644
--- a/xen/drivers/cpufreq/cpufreq.c
+++ b/xen/drivers/cpufreq/cpufreq.c
@@ -40,6 +40,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -234,6 +235,11 @@ static int get_psd_info(unsigned int cpu, unsigned int *shared_type,
         *domain_info = &processor_pminfo[cpu]->perf.domain_info;
         break;
 
+    case XEN_CPPC_INIT:
+        *shared_type = processor_pminfo[cpu]->cppc_data.shared_type;
+        *domain_info = &processor_pminfo[cpu]->cppc_data.domain_info;
+        break;
+
     default:
         ret = -EINVAL;
         break;
@@ -259,7 +265,7 @@ int cpufreq_add_cpu(unsigned int cpu)
     if ( !processor_pminfo[cpu] || !cpu_online(cpu) )
         return -EINVAL;
 
-    if ( !(processor_pminfo[cpu]->init & XEN_PX_INIT) )
+    if ( !(processor_pminfo[cpu]->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
         return -EINVAL;
 
     if (!cpufreq_driver.init)
@@ -434,7 +440,7 @@ int cpufreq_del_cpu(unsigned int cpu)
     if ( !processor_pminfo[cpu] || !cpu_online(cpu) )
         return -EINVAL;
 
-    if ( !(processor_pminfo[cpu]->init & XEN_PX_INIT) )
+    if ( !(processor_pminfo[cpu]->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
         return -EINVAL;
 
     if (!per_cpu(cpufreq_cpu_policy, cpu))
@@ -693,6 +699,120 @@ int acpi_set_pdc_bits(unsigned int acpi_id, XEN_GUEST_HANDLE(uint32) pdc)
     return ret;
 }
 
+static void print_CPPC(const struct xen_processor_cppc *cppc_data)
+{
+    printk("\t_CPC: highest_perf=%u, lowest_perf=%u, "
+           "nominal_perf=%u, lowest_nonlinear_perf=%u, "
+           "nominal_mhz=%uMHz, lowest_mhz=%uMHz\n",
+           cppc_data->cpc.highest_perf, cppc_data->cpc.lowest_perf,
+           cppc_data->cpc.nominal_perf, cppc_data->cpc.lowest_nonlinear_perf,
+           cppc_data->cpc.nominal_mhz, cppc_data->cpc.lowest_mhz);
+}
+
+int set_cppc_pminfo(unsigned int acpi_id,
+                    const struct xen_processor_cppc *cppc_data)
+{
+    int ret = 0, cpuid;
+    struct processor_pminfo *pm_info;
+
+    cpuid = get_cpu_id(acpi_id);
+    if ( cpuid < 0 )
+    {
+        ret = -EINVAL;
+        goto out;
+    }
+
+    if ( cppc_data->pad[0] || cppc_data->pad[1] || cppc_data->pad[2] )
+    {
+        ret = -EINVAL;
+        goto out;
+    }
+
+    if ( cpufreq_verbose )
+        printk("Set CPU%d (ACPI ID %u) CPPC state info:\n",
+               cpuid, acpi_id);
+
+    pm_info = processor_pminfo[cpuid];
+    if ( !pm_info )
+    {
+        pm_info = xvzalloc(struct processor_pminfo);
+        if ( !pm_info )
+        {
+            ret = -ENOMEM;
+            goto out;
+        }
+        processor_pminfo[cpuid] = pm_info;
+    }
+    pm_info->acpi_id = acpi_id;
+    pm_info->id = cpuid;
+    pm_info->cppc_data = *cppc_data;
+
+    if ( (cppc_data->flags & XEN_CPPC_PSD) &&
+         !check_psd_pminfo(cppc_data->shared_type) )
+    {
+            ret = -EINVAL;
+            goto out;
+    }
+
+    if ( cppc_data->flags & XEN_CPPC_CPC )
+    {
+        if ( cppc_data->cpc.highest_perf == 0 ||
+             cppc_data->cpc.highest_perf > UINT8_MAX ||
+             cppc_data->cpc.nominal_perf == 0 ||
+             cppc_data->cpc.lowest_nonlinear_perf == 0 ||
+             cppc_data->cpc.lowest_perf == 0 ||
+             cppc_data->cpc.lowest_perf >
+                 cppc_data->cpc.lowest_nonlinear_perf ||
+             cppc_data->cpc.lowest_nonlinear_perf >
+                 cppc_data->cpc.nominal_perf ||
+             cppc_data->cpc.nominal_perf > cppc_data->cpc.highest_perf )
+            /*
+             * Right now, Xen doesn't actually use highest_perf/nominal_perf/
+             * lowest_nonlinear_perf/lowest_perf values read from ACPI _CPC
+             * table. Xen reads CPPC capability MSR to get these four values.
+             * So warning is enough.
+             */
+            printk_once(XENLOG_WARNING
+                        "Broken CPPC perf values: lowest(%u), nonlinear_lowest(%u), nominal(%u), highest(%u)\n",
+                        cppc_data->cpc.lowest_perf,
+                        cppc_data->cpc.lowest_nonlinear_perf,
+                        cppc_data->cpc.nominal_perf,
+                        cppc_data->cpc.highest_perf);
+
+        /* lowest_mhz and nominal_mhz are optional value */
+        if ( cppc_data->cpc.nominal_mhz &&
+             cppc_data->cpc.lowest_mhz > cppc_data->cpc.nominal_mhz )
+        {
+            printk_once(XENLOG_WARNING
+                        "Broken CPPC freq values: lowest(%u), nominal(%u)\n",
+                        cppc_data->cpc.lowest_mhz,
+                        cppc_data->cpc.nominal_mhz);
+            /* Re-set with zero values, instead of keeping invalid values */
+            pm_info->cppc_data.cpc.nominal_mhz = 0;
+            pm_info->cppc_data.cpc.lowest_mhz = 0;
+        }
+    }
+
+    if ( cppc_data->flags == (XEN_CPPC_PSD | XEN_CPPC_CPC) )
+    {
+        if ( cpufreq_verbose )
+        {
+            print_PSD(&pm_info->cppc_data.domain_info);
+            print_CPPC(&pm_info->cppc_data);
+        }
+
+        pm_info->init = XEN_CPPC_INIT;
+        ret = cpufreq_cpu_init(cpuid);
+        if ( ret )
+            printk_once(XENLOG_WARNING
+                        "CPU%d failed amd-cppc mode init; use \"cpufreq=xen\" instead",
+                        cpuid);
+    }
+
+ out:
+    return ret;
+}
+
 static void cpufreq_cmdline_common_para(struct cpufreq_policy *new_policy)
 {
     if (usr_max_freq)
diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/cpufreq/processor_perf.h
index 4e045da983..e6576314f0 100644
--- a/xen/include/acpi/cpufreq/processor_perf.h
+++ b/xen/include/acpi/cpufreq/processor_perf.h
@@ -5,7 +5,8 @@
 #include 
 #include 
 
-#define XEN_PX_INIT 0x80000000U
+#define XEN_CPPC_INIT 0x40000000U
+#define XEN_PX_INIT   0x80000000U
 
 unsigned int powernow_register_driver(void);
 unsigned int get_measured_perf(unsigned int cpu, unsigned int flag);
@@ -43,6 +44,7 @@ struct processor_pminfo {
     uint32_t acpi_id;
     uint32_t id;
     struct processor_performance    perf;
+    struct xen_processor_cppc cppc_data;
 
     uint32_t init;
 };
diff --git a/xen/include/public/platform.h b/xen/include/public/platform.h
index 2725b8d104..94349fc5f5 100644
--- a/xen/include/public/platform.h
+++ b/xen/include/public/platform.h
@@ -363,6 +363,7 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t);
 #define XEN_PM_PX   1
 #define XEN_PM_TX   2
 #define XEN_PM_PDC  3
+#define XEN_PM_CPPC 4
 
 /* Px sub info type */
 #define XEN_PX_PCT   1
@@ -370,6 +371,10 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t);
 #define XEN_PX_PPC   4
 #define XEN_PX_PSD   8
 
+/* CPPC sub info type */
+#define XEN_CPPC_PSD   (1U << 0)
+#define XEN_CPPC_CPC   (1U << 1)
+
 struct xen_power_register {
     uint32_t     space_id;
     uint32_t     bit_width;
@@ -457,6 +462,26 @@ struct xen_processor_performance {
 typedef struct xen_processor_performance xen_processor_performance_t;
 DEFINE_XEN_GUEST_HANDLE(xen_processor_performance_t);
 
+struct xen_processor_cppc {
+    uint8_t flags; /* IN: XEN_CPPC_xxx */
+    uint8_t pad[3];
+    /*
+     * IN: Subset _CPC fields useful for CPPC-compatible cpufreq
+     * driver's initialization
+     */
+    struct {
+        uint32_t highest_perf;
+        uint32_t nominal_perf;
+        uint32_t lowest_nonlinear_perf;
+        uint32_t lowest_perf;
+        uint32_t lowest_mhz;
+        uint32_t nominal_mhz;
+    } cpc;
+    uint32_t shared_type; /* IN: XEN_CPUPERF_SHARED_TYPE_xxx */
+    struct xen_psd_package domain_info; /* IN: _PSD */
+};
+typedef struct xen_processor_cppc xen_processor_cppc_t;
+
 struct xenpf_set_processor_pminfo {
     /* IN variables */
     uint32_t id;    /* ACPI CPU ID */
@@ -465,6 +490,7 @@ struct xenpf_set_processor_pminfo {
         struct xen_processor_power          power;/* Cx: _CST/_CSD */
         struct xen_processor_performance    perf; /* Px: _PPC/_PCT/_PSS/_PSD */
         XEN_GUEST_HANDLE(uint32)            pdc;  /* _PDC */
+        xen_processor_cppc_t                cppc_data; /* CPPC: _CPC and _PSD */
     } u;
 };
 typedef struct xenpf_set_processor_pminfo xenpf_set_processor_pminfo_t;
diff --git a/xen/include/xen/pmstat.h b/xen/include/xen/pmstat.h
index 8350403e95..6096560d3c 100644
--- a/xen/include/xen/pmstat.h
+++ b/xen/include/xen/pmstat.h
@@ -7,12 +7,17 @@
 
 int set_px_pminfo(uint32_t acpi_id, struct xen_processor_performance *perf);
 long set_cx_pminfo(uint32_t acpi_id, struct xen_processor_power *power);
+int set_cppc_pminfo(unsigned int acpi_id,
+                    const struct xen_processor_cppc *cppc_data);
 
 #ifdef CONFIG_COMPAT
 struct compat_processor_performance;
 int compat_set_px_pminfo(uint32_t acpi_id, struct compat_processor_performance *perf);
 struct compat_processor_power;
 long compat_set_cx_pminfo(uint32_t acpi_id, struct compat_processor_power *power);
+struct compat_processor_cppc;
+int compat_set_cppc_pminfo(unsigned int acpi_id,
+                           const struct compat_processor_cppc *cppc_data);
 #endif
 
 uint32_t pmstat_get_cx_nr(unsigned int cpu);
diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst
index 6d6c6cfab2..9d08dcc4bb 100644
--- a/xen/include/xlat.lst
+++ b/xen/include/xlat.lst
@@ -160,6 +160,7 @@
 
 !	pct_register			platform.h
 !	power_register			platform.h
+!	processor_cppc			platform.h
 ?	processor_csd			platform.h
 !	processor_cx			platform.h
 !	processor_flags			platform.h
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	, Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD
	, Michal Orzel , "Julien
 Grall" , Stefano Stabellini 
Subject: [PATCH v7 08/13] xen/cpufreq: implement amd-cppc driver for CPPC in passive mode
Date: Fri, 22 Aug 2025 18:52:13 +0800
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amd-cppc is the AMD CPU performance scaling driver that introduces a
new CPU frequency control mechanism. The new mechanism is based on
Collaborative Processor Performance Control (CPPC) which is a finer grain
frequency management than legacy ACPI hardware P-States.
Current AMD CPU platforms are using the ACPI P-states driver to
manage CPU frequency and clocks with switching only in 3 P-states, while the
new amd-cppc allows a more flexible, low-latency interface for Xen
to directly communicate the performance hints to hardware.

"amd-cppc" driver is responsible for implementing CPPC in passive mode, which
still leverages Xen governors such as *ondemand*, *performance*, etc, to
calculate the performance hints. In the future, we will introduce an advanced
active mode to enable autonomous performence level selection.

Field epp, energy performance preference, which only has meaning when active
mode is enabled and will be introduced later in details, so we read
pre-defined BIOS value for it in passive mode.

Signed-off-by: Penny Zheng 
---
v1 -> v2:
- re-construct union caps and req to have anonymous struct instead
- avoid "else" when the earlier if() ends in an unconditional control flow statement
- Add check to avoid chopping off set bits from cast
- make pointers pointer-to-const wherever possible
- remove noisy log
- exclude families before 0x17 before CPPC-feature MSR op
- remove useless variable helpers
- use xvzalloc and XVFREE
- refactor error handling as ENABLE bit can only be cleared by reset
---
v2 -> v3:
- Move all MSR-definations to msr-index.h and follow the required style
- Refactor opening figure braces for struct/union
- Sort overlong lines throughout the series
- Make offset/res int covering underflow scenario
- Error out when amd_max_freq_mhz isn't set
- Introduce amd_get_freq(name) macro to decrease redundancy
- Supported CPU family checked ahead of smp-function
- Nominal freq shall be checked between the [min, max]
- Use APERF/MPREF to calculate current frequency
- Use amd_cppc_cpufreq_cpu_exit() to tidy error path
---
v3 -> v4:
- verbose print shall come with a CPU number
- deal with res <= 0 in amd_cppc_khz_to_perf()
- introduce a single helper amd_get_lowest_or_nominal_freq() to cover both
lowest and nominal scenario
- reduce abuse of wrmsr_safe()/rdmsr_safe() with wrmsrl()/rdmsrl()
- move cf_check from amd_cppc_write_request() to amd_cppc_write_request_msrs()
- add comment to explain why setting non_linear_lowest in passive mode
- add check to ensure perf values in
lowest <= non_linear_lowest <= nominal <= highset
- refactor comment for "data->err != 0" scenario
- use "data->err" instead of -ENODEV
- add U suffixes for all msr macro
---
v4 -> v5:
- all freq-values shall be unsigned int type
- remove shortcuts as it is rarely taken
- checking cpc.nominal_mhz and cpc.lowest_mhz are non-zero values is enough
- drop the explicit type cast
- null pointer check is in no need for internal functions
- change amd_get_lowest_or_nominal_freq() to amd_get_cpc_freq()
- clarifying function-wide that the calculated frequency result is to be in kHz
- use array notation
- with cpu_has_cppc check, no need to do cpu family check
---
v5 -> v6
- replace "AMD_CPPC" with "AMD-CPPC" in message
- add equation(mul,div) non-zero check
- replace -EINVAL with -EOPNOTSUPP
- refactor comment
---
v6 -> v7
- used > in place of !=, to not only serve a doc aspect, but also allow to
drop one part
- unify with UINT8_MAX
- return -ERANGE as we reject perf values of 0 as invalid
- replace uint32_t with unsigned int
- Move some epp introduction here, otherwise we will mis-handle this field here
by always clearing it
---
 xen/arch/x86/acpi/cpufreq/amd-cppc.c | 418 ++++++++++++++++++++++++++-
 xen/arch/x86/cpu/amd.c               |   8 +-
 xen/arch/x86/include/asm/amd.h       |   2 +
 xen/arch/x86/include/asm/msr-index.h |   6 +
 xen/include/public/sysctl.h          |   1 +
 5 files changed, 430 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
index 3377783f7e..df9ed52237 100644
--- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c
+++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
@@ -14,7 +14,98 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
+#include 
+#include 
+
+#define amd_cppc_err(cpu, fmt, args...)                             \
+    printk(XENLOG_ERR "AMD-CPPC: CPU%u error: " fmt, cpu, ## args)
+#define amd_cppc_warn(cpu, fmt, args...)                            \
+    printk(XENLOG_WARNING "AMD-CPPC: CPU%u warning: " fmt, cpu, ## args)
+#define amd_cppc_verbose(cpu, fmt, args...)                         \
+({                                                                  \
+    if ( cpufreq_verbose )                                          \
+        printk(XENLOG_DEBUG "AMD-CPPC: CPU%u " fmt, cpu, ## args);  \
+})
+
+/*
+ * Field highest_perf, nominal_perf, lowest_nonlinear_perf, and lowest_perf
+ * contain the values read from CPPC capability MSR. They represent the limits
+ * of managed performance range as well as the dynamic capability, which may
+ * change during processor operation
+ * Field highest_perf represents highest performance, which is the absolute
+ * maximum performance an individual processor may reach, assuming ideal
+ * conditions. This performance level may not be sustainable for long
+ * durations and may only be achievable if other platform components
+ * are in a specific state; for example, it may require other processors be
+ * in an idle state. This would be equivalent to the highest frequencies
+ * supported by the processor.
+ * Field nominal_perf represents maximum sustained performance level of the
+ * processor, assuming ideal operating conditions. All cores/processors are
+ * expected to be able to sustain their nominal performance state
+ * simultaneously.
+ * Field lowest_nonlinear_perf represents Lowest Nonlinear Performance, which
+ * is the lowest performance level at which nonlinear power savings are
+ * achieved. Above this threshold, lower performance levels should be
+ * generally more energy efficient than higher performance levels. So in
+ * traditional terms, this represents the P-state range of performance levels.
+ * Field lowest_perf represents the absolute lowest performance level of the
+ * platform. Selecting it may cause an efficiency penalty but should reduce
+ * the instantaneous power consumption of the processor. So in traditional
+ * terms, this represents the T-state range of performance levels.
+ *
+ * Field max_perf, min_perf, des_perf store the values for CPPC request MSR.
+ * Software passes performance goals through these fields.
+ * Field max_perf conveys the maximum performance level at which the platform
+ * may run. And it may be set to any performance value in the range
+ * [lowest_perf, highest_perf], inclusive.
+ * Field min_perf conveys the minimum performance level at which the platform
+ * may run. And it may be set to any performance value in the range
+ * [lowest_perf, highest_perf], inclusive but must be less than or equal to
+ * max_perf.
+ * Field des_perf conveys performance level Xen governor is requesting. And it
+ * may be set to any performance value in the range [min_perf, max_perf],
+ * inclusive.
+ * Field epp represents energy performance preference, which only has meaning
+ * when active mode is enabled.
+ */
+struct amd_cppc_drv_data
+{
+    const struct xen_processor_cppc *cppc_data;
+    union {
+        uint64_t raw;
+        struct {
+            unsigned int lowest_perf:8;
+            unsigned int lowest_nonlinear_perf:8;
+            unsigned int nominal_perf:8;
+            unsigned int highest_perf:8;
+            unsigned int :32;
+        };
+    } caps;
+    union {
+        uint64_t raw;
+        struct {
+            unsigned int max_perf:8;
+            unsigned int min_perf:8;
+            unsigned int des_perf:8;
+            unsigned int epp:8;
+            unsigned int :32;
+        };
+    } req;
+
+    int err;
+};
+
+static DEFINE_PER_CPU_READ_MOSTLY(struct amd_cppc_drv_data *,
+                                  amd_cppc_drv_data);
+/*
+ * Core max frequency read from PstateDef as anchor point
+ * for freq-to-perf transition
+ */
+static DEFINE_PER_CPU_READ_MOSTLY(unsigned int, pxfreq_mhz);
+static DEFINE_PER_CPU_READ_MOSTLY(uint8_t, epp_init);
 
 static bool __init amd_cppc_handle_option(const char *s, const char *end)
 {
@@ -50,10 +141,335 @@ int __init amd_cppc_cmdline_parse(const char *s, const char *e)
     return 0;
 }
 
+/*
+ * If CPPC lowest_freq and nominal_freq registers are exposed then we can
+ * use them to convert perf to freq and vice versa. The conversion is
+ * extrapolated as an linear function passing by the 2 points:
+ *  - (Low perf, Low freq)
+ *  - (Nominal perf, Nominal freq)
+ * Parameter freq is always in kHz.
+ */
+static int amd_cppc_khz_to_perf(const struct amd_cppc_drv_data *data,
+                                unsigned int freq, uint8_t *perf)
+{
+    const struct xen_processor_cppc *cppc_data = data->cppc_data;
+    unsigned int mul, div;
+    int offset = 0, res;
+
+    if ( cppc_data->cpc.lowest_mhz &&
+         data->caps.nominal_perf > data->caps.lowest_perf &&
+         cppc_data->cpc.nominal_mhz > cppc_data->cpc.lowest_mhz )
+    {
+        mul = data->caps.nominal_perf - data->caps.lowest_perf;
+        div = cppc_data->cpc.nominal_mhz - cppc_data->cpc.lowest_mhz;
+
+        /*
+         * We don't need to convert to kHz for computing offset and can
+         * directly use nominal_mhz and lowest_mhz as the division
+         * will remove the frequency unit.
+         */
+        offset = data->caps.nominal_perf -
+                 (mul * cppc_data->cpc.nominal_mhz) / div;
+    }
+    else
+    {
+        /* Read Processor Max Speed(MHz) as anchor point */
+        mul = data->caps.highest_perf;
+        div = this_cpu(pxfreq_mhz);
+        if ( !div )
+            return -EOPNOTSUPP;
+    }
+
+    res = offset + (mul * freq) / (div * 1000);
+    if ( res > UINT8_MAX )
+    {
+        printk_once(XENLOG_WARNING
+                    "Perf value exceeds maximum value 255: %d\n", res);
+        *perf = UINT8_MAX;
+        return 0;
+    }
+    if ( res <= 0 )
+    {
+        printk_once(XENLOG_WARNING
+                    "Perf value smaller than minimum value 0: %d\n", res);
+        return -ERANGE;
+    }
+    *perf = res;
+
+    return 0;
+}
+
+/*
+ * _CPC may define nominal frequecy and lowest frequency, if not, use
+ * Processor Max Speed as anchor point to calculate.
+ * Output freq stores cpc frequency in kHz
+ */
+static int amd_get_cpc_freq(const struct amd_cppc_drv_data *data,
+                            unsigned int cpc_mhz, uint8_t perf,
+                            unsigned int *freq)
+{
+    unsigned int mul, div, res;
+
+    if ( cpc_mhz )
+    {
+        /* Switch to kHz */
+        *freq = cpc_mhz * 1000;
+        return 0;
+    }
+
+    /* Read Processor Max Speed(MHz) as anchor point */
+    mul = this_cpu(pxfreq_mhz);
+    if ( !mul )
+        return -EOPNOTSUPP;
+    div = data->caps.highest_perf;
+    res = (mul * perf * 1000) / div;
+    if ( unlikely(!res) )
+        return -EOPNOTSUPP;
+
+    return 0;
+}
+
+/* Output max_freq stores calculated maximum frequency in kHz */
+static int amd_get_max_freq(const struct amd_cppc_drv_data *data,
+                            unsigned int *max_freq)
+{
+    unsigned int nom_freq = 0;
+    int res;
+
+    res = amd_get_cpc_freq(data, data->cppc_data->cpc.nominal_mhz,
+                           data->caps.nominal_perf, &nom_freq);
+    if ( res )
+        return res;
+
+    *max_freq = (data->caps.highest_perf * nom_freq) / data->caps.nominal_perf;
+
+    return 0;
+}
+
+static int cf_check amd_cppc_cpufreq_verify(struct cpufreq_policy *policy)
+{
+    cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
+                                 policy->cpuinfo.max_freq);
+
+    return 0;
+}
+
+static void cf_check amd_cppc_write_request_msrs(void *info)
+{
+    const struct amd_cppc_drv_data *data = info;
+
+    wrmsrl(MSR_AMD_CPPC_REQ, data->req.raw);
+}
+
+static void amd_cppc_write_request(unsigned int cpu, uint8_t min_perf,
+                                   uint8_t des_perf, uint8_t max_perf,
+                                   uint8_t epp)
+{
+    struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);
+    uint64_t prev = data->req.raw;
+
+    data->req.min_perf = min_perf;
+    data->req.max_perf = max_perf;
+    data->req.des_perf = des_perf;
+    data->req.epp = epp;
+
+    if ( prev == data->req.raw )
+        return;
+
+    on_selected_cpus(cpumask_of(cpu), amd_cppc_write_request_msrs, data, 1);
+}
+
+static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy,
+                                            unsigned int target_freq,
+                                            unsigned int relation)
+{
+    unsigned int cpu = policy->cpu;
+    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);
+    uint8_t des_perf;
+    int res;
+
+    if ( unlikely(!target_freq) )
+        return 0;
+
+    res = amd_cppc_khz_to_perf(data, target_freq, &des_perf);
+    if ( res )
+        return res;
+
+    /*
+     * Having a performance level lower than the lowest nonlinear
+     * performance level, such as, lowest_perf <= perf <= lowest_nonliner_perf,
+     * may actually cause an efficiency penalty, So when deciding the min_perf
+     * value, we prefer lowest nonlinear performance over lowest performance.
+     */
+    amd_cppc_write_request(policy->cpu, data->caps.lowest_nonlinear_perf,
+                           des_perf, data->caps.highest_perf,
+                           /* Pre-defined BIOS value for passive mode */
+                           per_cpu(epp_init, policy->cpu));
+    return 0;
+}
+
+static void cf_check amd_cppc_init_msrs(void *info)
+{
+    struct cpufreq_policy *policy = info;
+    struct amd_cppc_drv_data *data = this_cpu(amd_cppc_drv_data);
+    uint64_t val;
+    unsigned int min_freq = 0, nominal_freq = 0, max_freq;
+
+    /* Package level MSR */
+    rdmsrl(MSR_AMD_CPPC_ENABLE, val);
+    /*
+     * Only when Enable bit is on, the hardware will calculate the processor’s
+     * performance capabilities and initialize the performance level fields in
+     * the CPPC capability registers.
+     */
+    if ( !(val & AMD_CPPC_ENABLE) )
+    {
+        val |= AMD_CPPC_ENABLE;
+        wrmsrl(MSR_AMD_CPPC_ENABLE, val);
+    }
+
+    rdmsrl(MSR_AMD_CPPC_CAP1, data->caps.raw);
+
+    if ( data->caps.highest_perf == 0 || data->caps.lowest_perf == 0 ||
+         data->caps.nominal_perf == 0 || data->caps.lowest_nonlinear_perf == 0 ||
+         data->caps.lowest_perf > data->caps.lowest_nonlinear_perf ||
+         data->caps.lowest_nonlinear_perf > data->caps.nominal_perf ||
+         data->caps.nominal_perf > data->caps.highest_perf )
+    {
+        amd_cppc_err(policy->cpu,
+                     "Out of range values: highest(%u), lowest(%u), nominal(%u), lowest_nonlinear(%u)\n",
+                     data->caps.highest_perf, data->caps.lowest_perf,
+                     data->caps.nominal_perf, data->caps.lowest_nonlinear_perf);
+        goto err;
+    }
+
+    amd_process_freq(&cpu_data[policy->cpu],
+                     NULL, NULL, &this_cpu(pxfreq_mhz));
+
+    data->err = amd_get_cpc_freq(data, data->cppc_data->cpc.lowest_mhz,
+                                 data->caps.lowest_perf, &min_freq);
+    if ( data->err )
+        return;
+
+    data->err = amd_get_cpc_freq(data, data->cppc_data->cpc.nominal_mhz,
+                                 data->caps.nominal_perf, &nominal_freq);
+    if ( data->err )
+        return;
+
+    data->err = amd_get_max_freq(data, &max_freq);
+    if ( data->err )
+        return;
+
+    if ( min_freq > nominal_freq || nominal_freq > max_freq )
+    {
+        amd_cppc_err(policy->cpu,
+                     "min(%u), or max(%u), or nominal(%u) freq value is incorrect\n",
+                     min_freq, max_freq, nominal_freq);
+        goto err;
+    }
+
+    policy->min = min_freq;
+    policy->max = max_freq;
+
+    policy->cpuinfo.min_freq = min_freq;
+    policy->cpuinfo.max_freq = max_freq;
+    policy->cpuinfo.perf_freq = nominal_freq;
+    /*
+     * Set after policy->cpuinfo.perf_freq, as we are taking
+     * APERF/MPERF average frequency as current frequency.
+     */
+    policy->cur = cpufreq_driver_getavg(policy->cpu, GOV_GETAVG);
+
+    /* Store pre-defined BIOS value for passive mode */
+    rdmsrl(MSR_AMD_CPPC_REQ, val);
+    this_cpu(epp_init) = MASK_EXTR(val, AMD_CPPC_EPP_MASK);
+
+    return;
+
+ err:
+    /*
+     * No fallback shceme is available here, see more explanation at call
+     * site in amd_cppc_cpufreq_cpu_init().
+     */
+    data->err = -EINVAL;
+}
+
+/*
+ * AMD CPPC driver is different than legacy ACPI hardware P-State,
+ * which has a finer grain frequency range between the highest and lowest
+ * frequency. And boost frequency is actually the frequency which is mapped on
+ * highest performance ratio. The legacy P0 frequency is actually mapped on
+ * nominal performance ratio.
+ */
+static void amd_cppc_boost_init(struct cpufreq_policy *policy,
+                                const struct amd_cppc_drv_data *data)
+{
+    if ( data->caps.highest_perf <= data->caps.nominal_perf )
+        return;
+
+    policy->turbo = CPUFREQ_TURBO_ENABLED;
+}
+
+static int cf_check amd_cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy)
+{
+    XVFREE(per_cpu(amd_cppc_drv_data, policy->cpu));
+
+    return 0;
+}
+
+static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+    unsigned int cpu = policy->cpu;
+    struct amd_cppc_drv_data *data;
+
+    data = xvzalloc(struct amd_cppc_drv_data);
+    if ( !data )
+        return -ENOMEM;
+
+    data->cppc_data = &processor_pminfo[cpu]->cppc_data;
+
+    per_cpu(amd_cppc_drv_data, cpu) = data;
+
+    on_selected_cpus(cpumask_of(cpu), amd_cppc_init_msrs, policy, 1);
+
+    /*
+     * The enable bit is sticky, as we need to enable it at the very first
+     * begining, before CPPC capability values sanity check.
+     * If error path is taken effective, not only amd-cppc cpufreq core fails
+     * to initialize, but also we could not fall back to legacy P-states
+     * driver, irrespective of the command line specifying a fallback option.
+     */
+    if ( data->err )
+    {
+        amd_cppc_err(cpu, "Could not initialize cpufreq core in CPPC mode\n");
+        amd_cppc_cpufreq_cpu_exit(policy);
+        return data->err;
+    }
+
+    policy->governor = cpufreq_opt_governor ? : CPUFREQ_DEFAULT_GOVERNOR;
+
+    amd_cppc_boost_init(policy, data);
+
+    amd_cppc_verbose(policy->cpu,
+                     "CPU initialized with amd-cppc passive mode\n");
+
+    return 0;
+}
+
+static const struct cpufreq_driver __initconst_cf_clobber
+amd_cppc_cpufreq_driver =
+{
+    .name   = XEN_AMD_CPPC_DRIVER_NAME,
+    .verify = amd_cppc_cpufreq_verify,
+    .target = amd_cppc_cpufreq_target,
+    .init   = amd_cppc_cpufreq_cpu_init,
+    .exit   = amd_cppc_cpufreq_cpu_exit,
+};
+
 int __init amd_cppc_register_driver(void)
 {
     if ( !cpu_has_cppc )
         return -ENODEV;
 
-    return -EOPNOTSUPP;
+    return cpufreq_register_driver(&amd_cppc_cpufreq_driver);
 }
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index eb428f284e..1b9af1270c 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -613,10 +613,10 @@ static unsigned int attr_const amd_parse_freq(unsigned int family,
 	return freq;
 }
 
-static void amd_process_freq(const struct cpuinfo_x86 *c,
-			     unsigned int *low_mhz,
-			     unsigned int *nom_mhz,
-			     unsigned int *hi_mhz)
+void amd_process_freq(const struct cpuinfo_x86 *c,
+		      unsigned int *low_mhz,
+		      unsigned int *nom_mhz,
+		      unsigned int *hi_mhz)
 {
 	unsigned int idx = 0, h;
 	uint64_t hi, lo, val;
diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h
index 9c9599a622..72df42a6f6 100644
--- a/xen/arch/x86/include/asm/amd.h
+++ b/xen/arch/x86/include/asm/amd.h
@@ -173,5 +173,7 @@ extern bool amd_virt_spec_ctrl;
 bool amd_setup_legacy_ssbd(void);
 void amd_set_legacy_ssbd(bool enable);
 void amd_set_cpuid_user_dis(bool enable);
+void amd_process_freq(const struct cpuinfo_x86 *c, unsigned int *low_mhz,
+                      unsigned int *nom_mhz, unsigned int *hi_mhz);
 
 #endif /* __AMD_H__ */
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 428d993ee8..6abf154887 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -241,6 +241,12 @@
 
 #define MSR_AMD_CSTATE_CFG                  0xc0010296U
 
+#define MSR_AMD_CPPC_CAP1                   0xc00102b0U
+#define MSR_AMD_CPPC_ENABLE                 0xc00102b1U
+#define  AMD_CPPC_ENABLE                    (_AC(1, ULL) << 0)
+#define MSR_AMD_CPPC_REQ                    0xc00102b3U
+#define  AMD_CPPC_EPP_MASK                  (_AC(0xff, ULL) << 24)
+
 /*
  * Legacy MSR constants in need of cleanup.  No new MSRs below this comment.
  */
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index aafa7fcf2b..aa29a5401c 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -453,6 +453,7 @@ struct xen_set_cppc_para {
     uint32_t activity_window;
 };
 
+#define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc"
 #define XEN_HWP_DRIVER_NAME "hwp"
 
 /*
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	
Subject: [PATCH v7 10/13] xen/cpufreq: get performance policy from governor set via xenpm
Date: Fri, 22 Aug 2025 18:52:15 +0800
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Even if Xen governor is not used in amd-cppc active mode, we could
somehow deduce which performance policy (CPUFREQ_POLICY_xxx) user wants to
apply through which governor they choose, such as:
If user chooses performance governor, they want maximum performance, then
the policy shall be CPUFREQ_POLICY_PERFORMANCE
If user chooses powersave governor, they want the least power consumption,
then the policy shall be CPUFREQ_POLICY_POWERSAVE
Function cpufreq_policy_from_governor() is responsible for above transition,
and it shall be also effective when users setting new governor through xenpm.

userspace are forbidden choices, and if users specify such options, we shall
not only give warning message to suggest using "xenpm set-cpufreq-cppc", but
also error out.

Signed-off-by: Penny Zheng 
---
v4 -> v5:
- new commit
---
v5 -> v6:
- refactor warning message
---
v6 -> v7:
- move policy->policy set where it firstly gets introduced
- refactor commit message
---
 xen/drivers/acpi/pm-op.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index 427656c48c..6991616c1d 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -206,6 +206,14 @@ static int set_cpufreq_gov(struct xen_sysctl_pm_op *op)
     if ( new_policy.governor == NULL )
         return -EINVAL;
 
+    new_policy.policy = cpufreq_policy_from_governor(new_policy.governor);
+    if ( new_policy.policy == CPUFREQ_POLICY_UNKNOWN )
+    {
+        printk("Failed to get performance policy from %s, Try \"xenpm set-cpufreq-cppc\"\n",
+               new_policy.governor->name);
+        return -EINVAL;
+    }
+
     return __cpufreq_set_policy(old_policy, &new_policy);
 }
 
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Anthony PERARD
	, Juergen Gross , Andrew Cooper
	, Michal Orzel , Jan Beulich
	, Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , "Stefano
 Stabellini" 
Subject: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq para
Date: Fri, 22 Aug 2025 18:52:16 +0800
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We extract cppc info from "struct xen_get_cpufreq_para", where it acts as
a member of union, and share the space with governor info.
However, it may fail in amd-cppc passive mode, in which governor info and
CPPC info could co-exist, and both need to be printed together via xenpm tool.
If we tried to still put it in "struct xen_get_cpufreq_para" (e.g. just move
out of union), "struct xen_get_cpufreq_para" will enlarge too much to further
make xen_sysctl.u exceed 128 bytes.

So we introduce a new sub-field GET_CPUFREQ_CPPC to dedicatedly acquire
CPPC-related para, and make get-cpufreq-para invoke GET_CPUFREQ_CPPC
if available.
New helpers print_cppc_para() and get_cpufreq_cppc() are introduced to
extract CPPC-related parameters process from cpufreq para.

Signed-off-by: Penny Zheng 
---
v4 -> v5:
- new commit
---
v5 -> v6:
- remove the changes for get-cpufreq-para
---
v6 -> v7:
- make get-cpufreq-para invoke GET_CPUFREQ_CPPC
---
 tools/include/xenctrl.h     |  3 +-
 tools/libs/ctrl/xc_pm.c     | 28 ++++++++++++-
 tools/misc/xenpm.c          | 78 ++++++++++++++++++++++++-------------
 xen/drivers/acpi/pm-op.c    | 19 +++++++--
 xen/include/public/sysctl.h |  3 +-
 5 files changed, 98 insertions(+), 33 deletions(-)

diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h
index 965d3b585a..e5103453a9 100644
--- a/tools/include/xenctrl.h
+++ b/tools/include/xenctrl.h
@@ -1938,7 +1938,6 @@ struct xc_get_cpufreq_para {
                 xc_ondemand_t ondemand;
             } u;
         } s;
-        xc_cppc_para_t cppc_para;
     } u;
 
     int32_t turbo_enabled;
@@ -1953,6 +1952,8 @@ int xc_set_cpufreq_para(xc_interface *xch, int cpuid,
                         int ctrl_type, int ctrl_value);
 int xc_set_cpufreq_cppc(xc_interface *xch, int cpuid,
                         xc_set_cppc_para_t *set_cppc);
+int xc_get_cppc_para(xc_interface *xch, unsigned int cpuid,
+                     xc_cppc_para_t *cppc_para);
 int xc_get_cpufreq_avgfreq(xc_interface *xch, int cpuid, int *avg_freq);
 
 int xc_set_sched_opt_smt(xc_interface *xch, uint32_t value);
diff --git a/tools/libs/ctrl/xc_pm.c b/tools/libs/ctrl/xc_pm.c
index 6fda973f1f..446ac0b911 100644
--- a/tools/libs/ctrl/xc_pm.c
+++ b/tools/libs/ctrl/xc_pm.c
@@ -288,7 +288,6 @@ int xc_get_cpufreq_para(xc_interface *xch, int cpuid,
         CHK_FIELD(s.scaling_min_freq);
         CHK_FIELD(s.u.userspace);
         CHK_FIELD(s.u.ondemand);
-        CHK_FIELD(cppc_para);
 
 #undef CHK_FIELD
 
@@ -366,6 +365,33 @@ int xc_set_cpufreq_cppc(xc_interface *xch, int cpuid,
     return ret;
 }
 
+int xc_get_cppc_para(xc_interface *xch, unsigned int cpuid,
+                     xc_cppc_para_t *cppc_para)
+{
+    int ret;
+    struct xen_sysctl sysctl = {};
+    struct xen_get_cppc_para *sys_cppc_para = &sysctl.u.pm_op.u.get_cppc;
+
+    if ( !xch  || !cppc_para )
+    {
+        errno = EINVAL;
+        return -1;
+    }
+
+    sysctl.cmd = XEN_SYSCTL_pm_op;
+    sysctl.u.pm_op.cmd = GET_CPUFREQ_CPPC;
+    sysctl.u.pm_op.cpuid = cpuid;
+
+    ret = xc_sysctl(xch, &sysctl);
+    if ( ret )
+        return ret;
+
+    BUILD_BUG_ON(sizeof(*cppc_para) != sizeof(*sys_cppc_para));
+    memcpy(cppc_para, sys_cppc_para, sizeof(*sys_cppc_para));
+
+    return ret;
+}
+
 int xc_get_cpufreq_avgfreq(xc_interface *xch, int cpuid, int *avg_freq)
 {
     int ret = 0;
diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
index 6b054b10a4..8fc1d7cc65 100644
--- a/tools/misc/xenpm.c
+++ b/tools/misc/xenpm.c
@@ -801,6 +801,34 @@ static unsigned int calculate_activity_window(const xc_cppc_para_t *cppc,
     return mantissa * multiplier;
 }
 
+/* print out parameters about cpu cppc */
+static void print_cppc_para(unsigned int cpuid,
+                            const xc_cppc_para_t *cppc)
+{
+    printf("cppc variables       :\n");
+    printf("  hardware limits    : lowest [%"PRIu32"] lowest nonlinear [%"PRIu32"]\n",
+           cppc->lowest, cppc->lowest_nonlinear);
+    printf("                     : nominal [%"PRIu32"] highest [%"PRIu32"]\n",
+           cppc->nominal, cppc->highest);
+    printf("  configured limits  : min [%"PRIu32"] max [%"PRIu32"] energy perf [%"PRIu32"]\n",
+           cppc->minimum, cppc->maximum, cppc->energy_perf);
+
+    if ( cppc->features & XEN_SYSCTL_CPPC_FEAT_ACT_WINDOW )
+    {
+        unsigned int activity_window;
+        const char *units;
+
+        activity_window = calculate_activity_window(cppc, &units);
+        printf("                     : activity_window [%"PRIu32" %s]\n",
+               activity_window, units);
+    }
+
+    printf("                     : desired [%"PRIu32"%s]\n",
+           cppc->desired,
+           cppc->desired ? "" : " hw autonomous");
+    printf("\n");
+}
+
 /* print out parameters about cpu frequency */
 static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
 {
@@ -826,33 +854,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
 
     printf("scaling_driver       : %s\n", p_cpufreq->scaling_driver);
 
-    if ( hwp )
-    {
-        const xc_cppc_para_t *cppc = &p_cpufreq->u.cppc_para;
-
-        printf("cppc variables       :\n");
-        printf("  hardware limits    : lowest [%"PRIu32"] lowest nonlinear [%"PRIu32"]\n",
-               cppc->lowest, cppc->lowest_nonlinear);
-        printf("                     : nominal [%"PRIu32"] highest [%"PRIu32"]\n",
-               cppc->nominal, cppc->highest);
-        printf("  configured limits  : min [%"PRIu32"] max [%"PRIu32"] energy perf [%"PRIu32"]\n",
-               cppc->minimum, cppc->maximum, cppc->energy_perf);
-
-        if ( cppc->features & XEN_SYSCTL_CPPC_FEAT_ACT_WINDOW )
-        {
-            unsigned int activity_window;
-            const char *units;
-
-            activity_window = calculate_activity_window(cppc, &units);
-            printf("                     : activity_window [%"PRIu32" %s]\n",
-                   activity_window, units);
-        }
-
-        printf("                     : desired [%"PRIu32"%s]\n",
-               cppc->desired,
-               cppc->desired ? "" : " hw autonomous");
-    }
-    else
+    if ( !hwp )
     {
         if ( p_cpufreq->gov_num )
             printf("scaling_avail_gov    : %s\n",
@@ -898,6 +900,23 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
     printf("\n");
 }
 
+/* show cpu cppc parameters information on CPU cpuid */
+static int show_cppc_para_by_cpuid(xc_interface *xc_handle, unsigned int cpuid)
+{
+    int ret;
+    xc_cppc_para_t cppc_para;
+
+    ret = xc_get_cppc_para(xc_handle, cpuid, &cppc_para);
+    if ( !ret )
+        print_cppc_para(cpuid, &cppc_para);
+    else if ( errno == ENODEV )
+        ret = 0; /* Ignore unsupported platform */
+    else
+        fprintf(stderr, "[CPU%u] failed to get cppc parameter\n", cpuid);
+
+    return ret;
+}
+
 /* show cpu frequency parameters information on CPU cpuid */
 static int show_cpufreq_para_by_cpuid(xc_interface *xc_handle, int cpuid)
 {
@@ -957,7 +976,12 @@ static int show_cpufreq_para_by_cpuid(xc_interface *xc_handle, int cpuid)
     } while ( ret && errno == EAGAIN );
 
     if ( ret == 0 )
+    {
         print_cpufreq_para(cpuid, p_cpufreq);
+
+        /* Show CPPC parameters if available */
+        ret = show_cppc_para_by_cpuid(xc_handle, cpuid);
+    }
     else if ( errno == ENODEV )
     {
         ret = -ENODEV;
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index 6991616c1d..bf4638927f 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -77,6 +77,17 @@ static int read_scaling_available_governors(char *scaling_available_governors,
     return 0;
 }
 
+static int get_cpufreq_cppc(unsigned int cpu,
+                            struct xen_get_cppc_para *cppc_para)
+{
+    int ret = -ENODEV;
+
+    if ( hwp_active() )
+        ret = get_hwp_para(cpu, cppc_para);
+
+    return ret;
+}
+
 static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
 {
     uint32_t ret = 0;
@@ -142,9 +153,7 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
     else
         strlcpy(op->u.get_para.scaling_driver, "Unknown", CPUFREQ_NAME_LEN);
 
-    if ( hwp_active() )
-        ret = get_hwp_para(policy->cpu, &op->u.get_para.u.cppc_para);
-    else
+    if ( !hwp_active() )
     {
         if ( !(scaling_available_governors =
                xzalloc_array(char, gov_num * CPUFREQ_NAME_LEN)) )
@@ -381,6 +390,10 @@ int do_pm_op(struct xen_sysctl_pm_op *op)
         ret = set_cpufreq_para(op);
         break;
 
+    case GET_CPUFREQ_CPPC:
+        ret = get_cpufreq_cppc(op->cpuid, &op->u.get_cppc);
+        break;
+
     case SET_CPUFREQ_CPPC:
         ret = set_cpufreq_cppc(op);
         break;
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index eb3a23b038..3f654f98ab 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -492,7 +492,6 @@ struct xen_get_cpufreq_para {
                 struct  xen_ondemand ondemand;
             } u;
         } s;
-        struct xen_get_cppc_para cppc_para;
     } u;
 
     int32_t turbo_enabled;
@@ -523,6 +522,7 @@ struct xen_sysctl_pm_op {
     #define SET_CPUFREQ_PARA           (CPUFREQ_PARA | 0x03)
     #define GET_CPUFREQ_AVGFREQ        (CPUFREQ_PARA | 0x04)
     #define SET_CPUFREQ_CPPC           (CPUFREQ_PARA | 0x05)
+    #define GET_CPUFREQ_CPPC           (CPUFREQ_PARA | 0x06)
 
     /* set/reset scheduler power saving option */
     #define XEN_SYSCTL_pm_op_set_sched_opt_smt    0x21
@@ -547,6 +547,7 @@ struct xen_sysctl_pm_op {
     uint32_t cpuid;
     union {
         struct xen_get_cpufreq_para get_para;
+        struct xen_get_cppc_para    get_cppc;
         struct xen_set_cpufreq_gov  set_gov;
         struct xen_set_cpufreq_para set_para;
         struct xen_set_cppc_para    set_cppc;
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , "Julien
 Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?=
	, Stefano Stabellini 
Subject: [PATCH v7 09/13] xen/cpufreq: implement amd-cppc-epp driver for CPPC in active mode
Date: Fri, 22 Aug 2025 18:52:14 +0800
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amd-cppc has 2 operation modes: autonomous (active) mode and
non-autonomous (passive) mode.
In active mode, we don't need Xen governor to calculate and tune the cpu
frequency, while hardware built-in CPPC power algorithm will calculate the
runtime workload and adjust cores frequency automatically according to the
power supply, thermal, core voltage and some other hardware conditions.
In active mode, CPPC ignores requests done in the desired performance field,
and takes into account only the values set to the minimum performance, maximum
performance, and energy performance preference registers.

A new field EPP (energy performance preference), in CPPC request register, is
introduced. It will be used in the CCLK DPM controller to drive the frequency
that a core is going to operate during short periods of activity, called
minimum active frequency, It could contatin a range of values from 0 to 0xff.
An EPP of zero sets the min active frequency to maximum frequency, while
an EPP of 0xff sets the min active frequency to approxiately Idle frequency.

We implement a new AMD CPU frequency driver `amd-cppc-epp` for active mode.
It requires `active` tag in Xen cmdline for users to explicitly select active
mode.
In driver `active-cppc-epp`, ->setpolicy() is hooked, not the ->target(), as
it does not depend on xen governor to do performance tuning.

We also introduce a new field "policy" (CPUFREQ_POLICY_xxx) to represent
performance policy. Right now, it supports three values:
CPUFREQ_POLICY_PERFORMANCE as maximum performance, CPUFREQ_POLICY_POWERSAVE
as the least power consumption, and CPUFREQ_POLICY_ONDEMAND as no preference,
just corresponding to "performance", "powersave" and "ondemand" Xen governor,
which benefit users from re-using "governor" in Xen cmdline to deliver
which performance policy they want to apply.

Signed-off-by: Penny Zheng 
---
v1 -> v2:
- Remove redundant epp_mode
- Remove pointless initializer
- Define sole caller read_epp_init_once and epp_init value to read
pre-defined BIOS epp value only once
- Combine the commit "xen/cpufreq: introduce policy type when
cpufreq_driver->setpolicy exists"
---
v2 -> v3:
- Combined with commit "x86/cpufreq: add "cpufreq=amd-cppc,active" para"
- Refactor doc about "active mode"
- Change opt_cpufreq_active to opt_active_mode
- Let caller pass epp_init when unspecified to allow the function parameter
to be of uint8_t
- Make epp_init per-cpu value
---
v3 -> v4:
- doc refinement
- use MASK_EXTR() to get epp value
- fix indentation
- replace if-else() with switch()
- combine successive comments and do refinement
- no need to introduce amd_cppc_epp_update_limit() as a wrapper
- rename cpufreq_parse_policy() with cpufreq_policy_from_governor()
- no need to use case-insensitive comparison
---
v4 -> v5:
- refine doc to state what the default is for "active" sub-option and it's of
boolean nature
- excess blank after << for AMD_CPPC_EPP_MASK
- set max_perf with lowest_perf to get utmost powersave
- refine commit message to include description about relation between "policy"
and "governor"
---
v5 -> v6:
- expand comment for "epp" field
- let min_perf set with lowest_nonliner_perf, not lowest_perf, to constrain
  performance tuning in P-states range
- refactor doc and comments
- blank lines between non-fall-through case blocks
- introduce and add entry for "CPUFREQ_POLICY_ONDEMAND"
---
v6 -> v7
- make opt_active_mode __initdata when NDEBUG=y
- add assertion check for must-zero des_perf in active mode
- use the local variable max_perf and min_perf
- read_epp_init() doesn't worth a separate function
---
 docs/misc/xen-command-line.pandoc    |   9 +-
 xen/arch/x86/acpi/cpufreq/amd-cppc.c | 126 ++++++++++++++++++++++++++-
 xen/drivers/cpufreq/utility.c        |  15 ++++
 xen/include/acpi/cpufreq/cpufreq.h   |  18 ++++
 xen/include/public/sysctl.h          |   1 +
 5 files changed, 164 insertions(+), 5 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 3916cc81f6..c029a6e053 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -515,7 +515,7 @@ If set, force use of the performance counters for oprofile, rather than detectin
 available support.
 
 ### cpufreq
-> `= none | {{  | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[verbose]]`
+> `= none | {{  | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[active][,verbose]]`
 
 > Default: `xen`
 
@@ -537,6 +537,13 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels.
 * `amd-cppc` selects ACPI Collaborative Performance and Power Control (CPPC)
   on supported AMD hardware to provide finer grained frequency control
   mechanism. The default is disabled.
+* `active` is a boolean to enable amd-cppc driver in active(autonomous) mode.
+  In this mode, users don't rely on Xen governor to do performance monitoring
+  and tuning. Hardware built-in CPPC power algorithm will calculate the runtime
+  workload and adjust cores frequency automatically according to the power
+  supply, thermal, core voltage and some other hardware conditions.
+  The default is disabled, and the option only applies when `amd-cppc` is
+  enabled.
 
 There is also support for `;`-separated fallback options:
 `cpufreq=hwp;xen,verbose`.  This first tries `hwp` and falls back to `xen` if
diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
index df9ed52237..1b4753a062 100644
--- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c
+++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
@@ -67,9 +67,14 @@
  * max_perf.
  * Field des_perf conveys performance level Xen governor is requesting. And it
  * may be set to any performance value in the range [min_perf, max_perf],
- * inclusive.
+ * inclusive. In active mode, des_perf must be zero.
  * Field epp represents energy performance preference, which only has meaning
- * when active mode is enabled.
+ * when active mode is enabled. The EPP is used in the CCLK DPM controller
+ * to drive the frequency that a core is going to operate during short periods
+ * of activity, called minimum active frequency, It could contatin a range of
+ * values from 0 to 0xff. An EPP of zero sets the min active frequency to
+ * maximum frequency, while an EPP of 0xff sets the min active frequency to
+ * approxiately Idle frequency.
  */
 struct amd_cppc_drv_data
 {
@@ -106,6 +111,12 @@ static DEFINE_PER_CPU_READ_MOSTLY(struct amd_cppc_drv_data *,
  */
 static DEFINE_PER_CPU_READ_MOSTLY(unsigned int, pxfreq_mhz);
 static DEFINE_PER_CPU_READ_MOSTLY(uint8_t, epp_init);
+#ifndef NDEBUG
+static bool __ro_after_init opt_active_mode;
+#else
+static bool __initdata opt_active_mode;
+#endif
+
 
 static bool __init amd_cppc_handle_option(const char *s, const char *end)
 {
@@ -118,6 +129,13 @@ static bool __init amd_cppc_handle_option(const char *s, const char *end)
         return true;
     }
 
+    ret = parse_boolean("active", s, end);
+    if ( ret >= 0 )
+    {
+        opt_active_mode = ret;
+        return true;
+    }
+
     return false;
 }
 
@@ -270,6 +288,10 @@ static void amd_cppc_write_request(unsigned int cpu, uint8_t min_perf,
 
     data->req.min_perf = min_perf;
     data->req.max_perf = max_perf;
+#ifndef NDEBUG
+    if ( opt_active_mode )
+        ASSERT(!des_perf);
+#endif
     data->req.des_perf = des_perf;
     data->req.epp = epp;
 
@@ -417,7 +439,7 @@ static int cf_check amd_cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy)
     return 0;
 }
 
-static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
+static int amd_cppc_cpufreq_init_perf(struct cpufreq_policy *policy)
 {
     unsigned int cpu = policy->cpu;
     struct amd_cppc_drv_data *data;
@@ -450,12 +472,91 @@ static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
 
     amd_cppc_boost_init(policy, data);
 
+    return 0;
+}
+
+static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+    int ret;
+
+    ret = amd_cppc_cpufreq_init_perf(policy);
+    if ( ret )
+        return ret;
+
     amd_cppc_verbose(policy->cpu,
                      "CPU initialized with amd-cppc passive mode\n");
 
     return 0;
 }
 
+static int cf_check amd_cppc_epp_cpu_init(struct cpufreq_policy *policy)
+{
+    int ret;
+
+    ret = amd_cppc_cpufreq_init_perf(policy);
+    if ( ret )
+        return ret;
+
+    policy->policy = cpufreq_policy_from_governor(policy->governor);
+
+    amd_cppc_verbose(policy->cpu,
+                     "CPU initialized with amd-cppc active mode\n");
+
+    return 0;
+}
+
+static int cf_check amd_cppc_epp_set_policy(struct cpufreq_policy *policy)
+{
+    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data,
+                                                   policy->cpu);
+    uint8_t max_perf, min_perf, epp;
+
+    /*
+     * On default, set min_perf with lowest_nonlinear_perf, and max_perf
+     * with the highest, to ensure performance scaling in P-states range.
+     */
+    max_perf = data->caps.highest_perf;
+    min_perf = data->caps.lowest_nonlinear_perf;
+
+    /*
+     * In policy CPUFREQ_POLICY_PERFORMANCE, increase min_perf to
+     * highest_perf to achieve ultmost performance.
+     * In policy CPUFREQ_POLICY_POWERSAVE, decrease max_perf to
+     * lowest_nonlinear_perf to achieve ultmost power saving.
+     */
+    switch ( policy->policy )
+    {
+    case CPUFREQ_POLICY_PERFORMANCE:
+        /* Force the epp value to be zero for performance policy */
+        epp = CPPC_ENERGY_PERF_MAX_PERFORMANCE;
+        min_perf = max_perf;
+        break;
+
+    case CPUFREQ_POLICY_POWERSAVE:
+        /* Force the epp value to be 0xff for powersave policy */
+        epp = CPPC_ENERGY_PERF_MAX_POWERSAVE;
+        max_perf = min_perf;
+        break;
+
+    case CPUFREQ_POLICY_ONDEMAND:
+        /*
+         * Set epp with medium value to show no preference over performance
+         * or powersave
+         */
+        epp = CPPC_ENERGY_PERF_BALANCE;
+        break;
+
+    default:
+        epp = per_cpu(epp_init, policy->cpu);
+        break;
+    }
+
+    amd_cppc_write_request(policy->cpu, min_perf,
+                           0 /* no des_perf in active mode */,
+                           max_perf, epp);
+    return 0;
+}
+
 static const struct cpufreq_driver __initconst_cf_clobber
 amd_cppc_cpufreq_driver =
 {
@@ -466,10 +567,27 @@ amd_cppc_cpufreq_driver =
     .exit   = amd_cppc_cpufreq_cpu_exit,
 };
 
+static const struct cpufreq_driver __initconst_cf_clobber
+amd_cppc_epp_driver =
+{
+    .name       = XEN_AMD_CPPC_EPP_DRIVER_NAME,
+    .verify     = amd_cppc_cpufreq_verify,
+    .setpolicy  = amd_cppc_epp_set_policy,
+    .init       = amd_cppc_epp_cpu_init,
+    .exit       = amd_cppc_cpufreq_cpu_exit,
+};
+
 int __init amd_cppc_register_driver(void)
 {
+    int ret;
+
     if ( !cpu_has_cppc )
         return -ENODEV;
 
-    return cpufreq_register_driver(&amd_cppc_cpufreq_driver);
+    if ( opt_active_mode )
+        ret = cpufreq_register_driver(&amd_cppc_epp_driver);
+    else
+        ret = cpufreq_register_driver(&amd_cppc_cpufreq_driver);
+
+    return ret;
 }
diff --git a/xen/drivers/cpufreq/utility.c b/xen/drivers/cpufreq/utility.c
index 987c3b5929..e2cc9ff2af 100644
--- a/xen/drivers/cpufreq/utility.c
+++ b/xen/drivers/cpufreq/utility.c
@@ -250,6 +250,7 @@ int __cpufreq_set_policy(struct cpufreq_policy *data,
     data->min = policy->min;
     data->max = policy->max;
     data->limits = policy->limits;
+    data->policy = policy->policy;
     if (cpufreq_driver.setpolicy)
         return alternative_call(cpufreq_driver.setpolicy, data);
 
@@ -281,3 +282,17 @@ int __cpufreq_set_policy(struct cpufreq_policy *data,
 
     return __cpufreq_governor(data, CPUFREQ_GOV_LIMITS);
 }
+
+unsigned int cpufreq_policy_from_governor(const struct cpufreq_governor *gov)
+{
+    if ( !strncmp(gov->name, "performance", CPUFREQ_NAME_LEN) )
+        return CPUFREQ_POLICY_PERFORMANCE;
+
+    if ( !strncmp(gov->name, "powersave", CPUFREQ_NAME_LEN) )
+        return CPUFREQ_POLICY_POWERSAVE;
+
+    if ( !strncmp(gov->name, "ondemand", CPUFREQ_NAME_LEN) )
+        return CPUFREQ_POLICY_ONDEMAND;
+
+    return CPUFREQ_POLICY_UNKNOWN;
+}
diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h
index 5d4881eea8..9ef7c4683a 100644
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -81,6 +81,7 @@ struct cpufreq_policy {
     int8_t              turbo;  /* tristate flag: 0 for unsupported
                                  * -1 for disable, 1 for enabled
                                  * See CPUFREQ_TURBO_* below for defines */
+    unsigned int        policy; /* CPUFREQ_POLICY_* */
 };
 DECLARE_PER_CPU(struct cpufreq_policy *, cpufreq_cpu_policy);
 
@@ -131,6 +132,23 @@ extern int cpufreq_register_governor(struct cpufreq_governor *governor);
 extern struct cpufreq_governor *__find_governor(const char *governor);
 #define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_dbs
 
+/*
+ * Performance Policy
+ * If cpufreq_driver->target() exists, the ->governor decides what frequency
+ * within the limits is used. If cpufreq_driver->setpolicy() exists, these
+ * following policies are available:
+ * CPUFREQ_POLICY_PERFORMANCE represents maximum performance
+ * CPUFREQ_POLICY_POWERSAVE represents least power consumption
+ * CPUFREQ_POLICY_ONDEMAND represents no preference over performance or
+ * powersave
+ */
+#define CPUFREQ_POLICY_UNKNOWN      0
+#define CPUFREQ_POLICY_POWERSAVE    1
+#define CPUFREQ_POLICY_PERFORMANCE  2
+#define CPUFREQ_POLICY_ONDEMAND     3
+
+unsigned int cpufreq_policy_from_governor(const struct cpufreq_governor *gov);
+
 /* pass a target to the cpufreq driver */
 extern int __cpufreq_driver_target(struct cpufreq_policy *policy,
                                    unsigned int target_freq,
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index aa29a5401c..eb3a23b038 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -454,6 +454,7 @@ struct xen_set_cppc_para {
 };
 
 #define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc"
+#define XEN_AMD_CPPC_EPP_DRIVER_NAME "amd-cppc-epp"
 #define XEN_HWP_DRIVER_NAME "hwp"
 
 /*
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Anthony PERARD
	, Jan Beulich 
Subject: [PATCH v7 12/13] xen/cpufreq: bypass governor-related para for amd-cppc-epp
Date: Fri, 22 Aug 2025 18:52:17 +0800
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HWP and amd-cppc-epp are both governor-less driver, so we introduce
"is_goverless" flag and cpufreq_is_governorless() to help bypass
governor-related info on dealing with cpufreq para.

Signed-off-by: Penny Zheng 
---
v3 -> v4:
- Include validation check fix here
---
v4 -> v5:
- validation check has beem moved to where XEN_PROCESSOR_PM_CPPC and
XEN_CPPC_INIT have been firstly introduced
- adding "cpufreq_driver.setpolicy == NULL" check to exclude governor-related
para for amd-cppc-epp driver in get/set_cpufreq_para()
---
v5 -> v6:
- add helper cpufreq_is_governorless() to tell whether cpufreq driver is
governor-less
---
v6 -> v7:
- change "hw_auto" to "is_goverless"
- complement comment
- wrap around with PM_OP to avoid violating Misra rule 2.1
---
 tools/misc/xenpm.c                 | 10 +++++++---
 xen/drivers/acpi/pm-op.c           |  4 ++--
 xen/drivers/cpufreq/cpufreq.c      | 14 ++++++++++++++
 xen/include/acpi/cpufreq/cpufreq.h |  2 ++
 4 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
index 8fc1d7cc65..02981c4583 100644
--- a/tools/misc/xenpm.c
+++ b/tools/misc/xenpm.c
@@ -832,9 +832,13 @@ static void print_cppc_para(unsigned int cpuid,
 /* print out parameters about cpu frequency */
 static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
 {
-    bool hwp = strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) == 0;
+    bool is_goverless = false;
     int i;
 
+    if ( !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) ||
+         !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) )
+        is_goverless = true;
+
     printf("cpu id               : %d\n", cpuid);
 
     printf("affected_cpus        :");
@@ -842,7 +846,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
         printf(" %d", p_cpufreq->affected_cpus[i]);
     printf("\n");
 
-    if ( hwp )
+    if ( is_goverless )
         printf("cpuinfo frequency    : base [%"PRIu32"] max [%"PRIu32"]\n",
                p_cpufreq->cpuinfo_min_freq,
                p_cpufreq->cpuinfo_max_freq);
@@ -854,7 +858,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
 
     printf("scaling_driver       : %s\n", p_cpufreq->scaling_driver);
 
-    if ( !hwp )
+    if ( !is_goverless )
     {
         if ( p_cpufreq->gov_num )
             printf("scaling_avail_gov    : %s\n",
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index bf4638927f..2b4c8070aa 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -153,7 +153,7 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
     else
         strlcpy(op->u.get_para.scaling_driver, "Unknown", CPUFREQ_NAME_LEN);
 
-    if ( !hwp_active() )
+    if ( !cpufreq_is_governorless(op->cpuid) )
     {
         if ( !(scaling_available_governors =
                xzalloc_array(char, gov_num * CPUFREQ_NAME_LEN)) )
@@ -236,7 +236,7 @@ static int set_cpufreq_para(struct xen_sysctl_pm_op *op)
     if ( !policy || !policy->governor )
         return -EINVAL;
 
-    if ( hwp_active() )
+    if ( cpufreq_is_governorless(op->cpuid) )
         return -EOPNOTSUPP;
 
     switch( op->u.set_para.ctrl_type )
diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c
index 41e0da3b77..871fe33681 100644
--- a/xen/drivers/cpufreq/cpufreq.c
+++ b/xen/drivers/cpufreq/cpufreq.c
@@ -956,3 +956,17 @@ int __init cpufreq_register_driver(const struct cpufreq_driver *driver_data)
 
     return 0;
 }
+
+#ifdef CONFIG_PM_OP
+/*
+ * Governor-less cpufreq driver indicates the driver doesn't rely on Xen
+ * governor to do performance tuning, mostly it has hardware built-in
+ * algorithm to calculate runtime workload and adjust cores frequency
+ * automatically. like Intel HWP, or CPPC in AMD.
+ */
+bool cpufreq_is_governorless(unsigned int cpuid)
+{
+    return processor_pminfo[cpuid]->init && (hwp_active() ||
+                                             cpufreq_driver.setpolicy);
+}
+#endif /* CONFIG_PM_OP */
diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h
index 9ef7c4683a..babc4a1a2c 100644
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -294,4 +294,6 @@ int acpi_cpufreq_register(void);
 int amd_cppc_cmdline_parse(const char *s, const char *e);
 int amd_cppc_register_driver(void);
 
+bool cpufreq_is_governorless(unsigned int cpuid);
+
 #endif /* __XEN_CPUFREQ_PM_H__ */
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Anthony PERARD
	, Andrew Cooper ,
	Michal Orzel , Jan Beulich , "Julien
 Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?=
	, Stefano Stabellini 
Subject: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC xen_sysctl_pm_op for amd-cppc driver
Date: Fri, 22 Aug 2025 18:52:18 +0800
Message-ID: <20250822105218.3601273-14-Penny.Zheng@amd.com>
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Introduce helper set_amd_cppc_para() and get_amd_cppc_para() to
SET/GET CPPC-related para for amd-cppc/amd-cppc-epp driver.

In get_cpufreq_cppc()/set_cpufreq_cppc(), we include
"processor_pminfo[cpuid]->init & XEN_CPPC_INIT" condition check to deal with
cpufreq driver in amd-cppc.

Also, a new field "policy" has also been added in "struct xen_get_cppc_para"
to describe performance policy in active mode. It gets printed with other
cppc paras. Move manifest constants "XEN_CPUFREQ_POLICY_xxx" to public header
to let it be used in user space tools.

Signed-off-by: Penny Zheng 
---
v1 -> v2:
- Give the variable des_perf an initializer of 0
- Use the strncmp()s directly in the if()
---
v3 -> v4
- refactor comments
- remove double blank lines
- replace amd_cppc_in_use flag with XEN_PROCESSOR_PM_CPPC
---
v4 -> v5:
- add new field "policy" in "struct xen_cppc_para"
- add new performamce policy XEN_CPUFREQ_POLICY_BALANCE
- drop string comparisons with "processor_pminfo[cpuid]->init & XEN_CPPC_INIT"
and "cpufreq.setpolicy == NULL"
- Blank line ahead of the main "return" of a function
- refactor comments, commit message and title
---
v5 -> v6:
- remove duplicated manifest constants, and just move it to public header
- use "else if" to avoid confusion that it looks as if both paths could be taken
- add check for legitimate perf values
- use "unknown" instead of "none"
- introduce "CPUFREQ_POLICY_END" for array overrun check in user space tools
---
v6 -> v7:
- use ARRAY_SIZE() instead
- ->policy print is avoided in passive mode and print "unknown" in invalid
cases
- let cpufreq_is_governorless() being the variable's initializer
- refactor with the conditional operator to increase readability
- move duplicated defination ahead and use local variable
- avoid using "else-condition" to bring "dead code" in Misra's nomeclature
- move the comment out of public header and into the respective internal
struct field
- wrap set{,get}_amd_cppc_para() with CONFIG_PM_OP
- add symmetry scenario for maximum check
---
 tools/misc/xenpm.c                   |  16 +++
 xen/arch/x86/acpi/cpufreq/amd-cppc.c | 181 +++++++++++++++++++++++++++
 xen/drivers/acpi/pm-op.c             |  10 +-
 xen/include/acpi/cpufreq/cpufreq.h   |  32 ++---
 xen/include/public/sysctl.h          |   6 +
 5 files changed, 226 insertions(+), 19 deletions(-)

diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
index 02981c4583..eedb745a46 100644
--- a/tools/misc/xenpm.c
+++ b/tools/misc/xenpm.c
@@ -38,6 +38,13 @@
 static xc_interface *xc_handle;
 static unsigned int max_cpu_nr;
 
+static const char cpufreq_policy_str[][12] = {
+    [CPUFREQ_POLICY_UNKNOWN] = "unknown",
+    [CPUFREQ_POLICY_POWERSAVE] = "powersave",
+    [CPUFREQ_POLICY_PERFORMANCE] = "performance",
+    [CPUFREQ_POLICY_ONDEMAND] = "ondemand",
+};
+
 /* help message */
 void show_help(void)
 {
@@ -826,6 +833,15 @@ static void print_cppc_para(unsigned int cpuid,
     printf("                     : desired [%"PRIu32"%s]\n",
            cppc->desired,
            cppc->desired ? "" : " hw autonomous");
+
+    if ( !cppc->desired )
+    {
+        if ( cppc->policy < ARRAY_SIZE(cpufreq_policy_str) )
+            printf("  performance policy : %s\n",
+                   cpufreq_policy_str[cppc->policy]);
+        else
+            printf("  performance policy : unknown\n");
+    }
     printf("\n");
 }
 
diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
index 1b4753a062..493550bbb3 100644
--- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c
+++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
@@ -557,6 +557,187 @@ static int cf_check amd_cppc_epp_set_policy(struct cpufreq_policy *policy)
     return 0;
 }
 
+#ifdef CONFIG_PM_OP
+int get_amd_cppc_para(const struct cpufreq_policy *policy,
+                      struct xen_get_cppc_para *cppc_para)
+{
+    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data,
+                                                   policy->cpu);
+
+    if ( data == NULL )
+        return -ENODATA;
+
+    cppc_para->policy           = policy->policy;
+    cppc_para->lowest           = data->caps.lowest_perf;
+    cppc_para->lowest_nonlinear = data->caps.lowest_nonlinear_perf;
+    cppc_para->nominal          = data->caps.nominal_perf;
+    cppc_para->highest          = data->caps.highest_perf;
+    cppc_para->minimum          = data->req.min_perf;
+    cppc_para->maximum          = data->req.max_perf;
+    cppc_para->desired          = data->req.des_perf;
+    cppc_para->energy_perf      = data->req.epp;
+
+    return 0;
+}
+
+int set_amd_cppc_para(struct cpufreq_policy *policy,
+                      const struct xen_set_cppc_para *set_cppc)
+{
+    unsigned int cpu = policy->cpu;
+    struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);
+    uint8_t max_perf, min_perf, des_perf, epp;
+    bool active_mode = cpufreq_is_governorless(cpu);
+
+    if ( data == NULL )
+        return -ENOENT;
+
+    /* Return if there is nothing to do. */
+    if ( set_cppc->set_params == 0 )
+        return 0;
+
+    /* Only allow values if params bit is set. */
+    if ( (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED) &&
+          set_cppc->desired) ||
+         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) &&
+          set_cppc->minimum) ||
+         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
+          set_cppc->maximum) ||
+         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF) &&
+          set_cppc->energy_perf) )
+        return -EINVAL;
+
+    /*
+     * Validate all parameters
+     * Maximum performance may be set to any performance value in the range
+     * [Nonlinear Lowest Performance, Highest Performance], inclusive but must
+     * be set to a value that is larger than or equal to minimum Performance.
+     */
+    if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
+         (set_cppc->maximum > data->caps.highest_perf ||
+          set_cppc->maximum <
+                        (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM
+                         ? set_cppc->minimum
+                         : data->req.min_perf)) )
+        return -EINVAL;
+    /*
+     * Minimum performance may be set to any performance value in the range
+     * [Nonlinear Lowest Performance, Highest Performance], inclusive but must
+     * be set to a value that is less than or equal to Maximum Performance.
+     */
+    if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) &&
+         (set_cppc->minimum < data->caps.lowest_nonlinear_perf ||
+          (set_cppc->minimum >
+                        (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM
+                         ? set_cppc->maximum
+                         : data->req.max_perf))) )
+        return -EINVAL;
+    /*
+     * Desired performance may be set to any performance value in the range
+     * [Minimum Performance, Maximum Performance], inclusive.
+     */
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED )
+    {
+        if ( active_mode )
+            return -EOPNOTSUPP;
+
+        if ( (set_cppc->desired >
+                        (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM
+                         ? set_cppc->maximum
+                         : data->req.max_perf)) ||
+             (set_cppc->desired <
+                        (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM
+                         ? set_cppc->minimum
+                         : data->req.min_perf)) )
+            return -EINVAL;
+    }
+    /*
+     * Energy Performance Preference may be set with a range of values
+     * from 0 to 0xFF
+     */
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF )
+    {
+        if ( !active_mode )
+            return -EOPNOTSUPP;
+
+        if ( set_cppc->energy_perf > UINT8_MAX )
+            return -EINVAL;
+    }
+
+    /* Activity window not supported in MSR */
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ACT_WINDOW )
+        return -EOPNOTSUPP;
+
+    epp = per_cpu(epp_init, cpu);
+    min_perf = data->caps.lowest_nonlinear_perf;
+    max_perf = data->caps.highest_perf;
+    des_perf = data->req.des_perf;
+    /*
+     * Apply presets:
+     * XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE/PERFORMANCE/ONDEMAND are
+     * only available when CPPC in active mode
+     */
+    switch ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_PRESET_MASK )
+    {
+    case XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE:
+        if ( !active_mode )
+            return -EINVAL;
+        policy->policy = CPUFREQ_POLICY_POWERSAVE;
+        /*
+         * Lower max_perf to nonlinear_lowest to achieve
+         * ultmost power saviongs
+         */
+        max_perf = min_perf;
+        epp = CPPC_ENERGY_PERF_MAX_POWERSAVE;
+        break;
+
+    case XEN_SYSCTL_CPPC_SET_PRESET_PERFORMANCE:
+        if ( !active_mode )
+            return -EINVAL;
+        policy->policy = CPUFREQ_POLICY_PERFORMANCE;
+        /* Increase min_perf to highest to achieve ultmost performance */
+        min_perf = max_perf;
+        epp = CPPC_ENERGY_PERF_MAX_PERFORMANCE;
+        break;
+
+    case XEN_SYSCTL_CPPC_SET_PRESET_ONDEMAND:
+        if ( !active_mode )
+            return -EINVAL;
+        policy->policy = CPUFREQ_POLICY_ONDEMAND;
+        /*
+         * Take medium value to show no preference over
+         * performance or powersave
+         */
+        epp = CPPC_ENERGY_PERF_BALANCE;
+        break;
+
+    case XEN_SYSCTL_CPPC_SET_PRESET_NONE:
+        if ( active_mode )
+            policy->policy = CPUFREQ_POLICY_UNKNOWN;
+        break;
+
+    default:
+        return -EINVAL;
+    }
+
+    /* Further customize presets if needed */
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM )
+        min_perf = set_cppc->minimum;
+
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM )
+        max_perf = set_cppc->maximum;
+
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF )
+        epp = set_cppc->energy_perf;
+
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED )
+        des_perf = set_cppc->desired;
+
+    amd_cppc_write_request(cpu, min_perf, des_perf, max_perf, epp);
+
+    return 0;
+}
+#endif /* CONFIG_PM_OP */
+
 static const struct cpufreq_driver __initconst_cf_clobber
 amd_cppc_cpufreq_driver =
 {
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index 2b4c8070aa..195dcb88b5 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -84,6 +84,8 @@ static int get_cpufreq_cppc(unsigned int cpu,
 
     if ( hwp_active() )
         ret = get_hwp_para(cpu, cppc_para);
+    else if ( processor_pminfo[cpu]->init & XEN_CPPC_INIT )
+        ret = get_amd_cppc_para(per_cpu(cpufreq_cpu_policy, cpu), cppc_para);
 
     return ret;
 }
@@ -317,10 +319,12 @@ static int set_cpufreq_cppc(struct xen_sysctl_pm_op *op)
     if ( !policy || !policy->governor )
         return -ENOENT;
 
-    if ( !hwp_active() )
-        return -EOPNOTSUPP;
+    if ( hwp_active() )
+        return set_hwp_para(policy, &op->u.set_cppc);
+    if ( processor_pminfo[op->cpuid]->init & XEN_CPPC_INIT )
+        return set_amd_cppc_para(policy, &op->u.set_cppc);
 
-    return set_hwp_para(policy, &op->u.set_cppc);
+    return -EOPNOTSUPP;
 }
 
 int do_pm_op(struct xen_sysctl_pm_op *op)
diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h
index babc4a1a2c..6ca686c4b2 100644
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -81,7 +81,18 @@ struct cpufreq_policy {
     int8_t              turbo;  /* tristate flag: 0 for unsupported
                                  * -1 for disable, 1 for enabled
                                  * See CPUFREQ_TURBO_* below for defines */
-    unsigned int        policy; /* CPUFREQ_POLICY_* */
+    unsigned int        policy; /* Performance Policy
+                                 * If cpufreq_driver->target() exists,
+                                 * the ->governor decides what frequency
+                                 * within the limits is used.
+                                 * If cpufreq_driver->setpolicy() exists, these
+                                 * following policies are available:
+                                 * CPUFREQ_POLICY_PERFORMANCE represents
+                                 * maximum performance
+                                 * CPUFREQ_POLICY_POWERSAVE represents least
+                                 * power consumption
+                                 * CPUFREQ_POLICY_ONDEMAND represents no
+                                 * preference over performance or powersave */
 };
 DECLARE_PER_CPU(struct cpufreq_policy *, cpufreq_cpu_policy);
 
@@ -132,21 +143,6 @@ extern int cpufreq_register_governor(struct cpufreq_governor *governor);
 extern struct cpufreq_governor *__find_governor(const char *governor);
 #define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_dbs
 
-/*
- * Performance Policy
- * If cpufreq_driver->target() exists, the ->governor decides what frequency
- * within the limits is used. If cpufreq_driver->setpolicy() exists, these
- * following policies are available:
- * CPUFREQ_POLICY_PERFORMANCE represents maximum performance
- * CPUFREQ_POLICY_POWERSAVE represents least power consumption
- * CPUFREQ_POLICY_ONDEMAND represents no preference over performance or
- * powersave
- */
-#define CPUFREQ_POLICY_UNKNOWN      0
-#define CPUFREQ_POLICY_POWERSAVE    1
-#define CPUFREQ_POLICY_PERFORMANCE  2
-#define CPUFREQ_POLICY_ONDEMAND     3
-
 unsigned int cpufreq_policy_from_governor(const struct cpufreq_governor *gov);
 
 /* pass a target to the cpufreq driver */
@@ -293,6 +289,10 @@ int acpi_cpufreq_register(void);
 
 int amd_cppc_cmdline_parse(const char *s, const char *e);
 int amd_cppc_register_driver(void);
+int get_amd_cppc_para(const struct cpufreq_policy *policy,
+                      struct xen_get_cppc_para *cppc_para);
+int set_amd_cppc_para(struct cpufreq_policy *policy,
+                      const struct xen_set_cppc_para *set_cppc);
 
 bool cpufreq_is_governorless(unsigned int cpuid);
 
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index 3f654f98ab..c50fa7bb3c 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -336,8 +336,14 @@ struct xen_ondemand {
     uint32_t up_threshold;
 };
 
+#define CPUFREQ_POLICY_UNKNOWN      0
+#define CPUFREQ_POLICY_POWERSAVE    1
+#define CPUFREQ_POLICY_PERFORMANCE  2
+#define CPUFREQ_POLICY_ONDEMAND     3
+
 struct xen_get_cppc_para {
     /* OUT */
+    uint32_t policy; /* CPUFREQ_POLICY_xxx */
     /* activity_window supported if set */
 #define XEN_SYSCTL_CPPC_FEAT_ACT_WINDOW  (1 << 0)
     uint32_t features; /* bit flags for features */
-- 
2.34.1



From xen-devel-bounces@lists.xenproject.org Fri Aug 22 12:22:30 2025
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Date: Fri, 22 Aug 2025 14:22:09 +0200
From: Anthony PERARD 
To: Andrew Cooper 
Cc: =?iso-8859-1?Q?J=FCrgen_Gro=DF?= ,
	xen-devel@lists.xenproject.org,
	Anthony PERARD 
Subject: Re: [PATCH] tools/xl: hide xenstore-features behind option
Message-ID: 
References: <20250815143236.27641-1-jgross@suse.com>
 <3ef1fc73-601c-4de0-b94e-bbf9cc27d081@citrix.com>
 <1704c30a-49fc-49fd-bb2f-a90f7f834761@suse.com>
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On Fri, Aug 15, 2025 at 03:40:28PM +0100, Andrew Cooper wrote:
> On 15/08/2025 3:39 pm, Jürgen Groß wrote:
> > On 15.08.25 16:36, Andrew Cooper wrote:
> >> On 15/08/2025 3:32 pm, Juergen Gross wrote:
> >>> In order to be able to use "xl info" before Xenstore has been started
> >>> or after it has crashed, hide obtaining the available Xenstore features
> >>> behind the new option "-x".
> >>>
> >>> Fixes: ecce7970cfe7 ("tools/xl: add available Xenstore features to
> >>> xl info output")
> >>> Reported-by: Andrew Cooper 
> >>> Signed-off-by: Juergen Gross 
> >>
> >> Probably ought to be Reported-by Ross Lagerwall.  He did all the hard
> >> work debugging this; I just insisted that the conversation move onto
> >> Matrix.
> >>
> >> For the change itself, Reviewed-by: Andrew Cooper
> >> 
> >
> > Thanks.
> >
> > Should I send V2 with the "Reported-by" corrected, or can this be done
> > when committing?
> 
> Happy to fix on commit.

Acked-by: Anthony PERARD 

Thanks,

-- 
Anthony PERARD


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Hi Leonid,

Leonid Komarianskyi  writes:

> Hi Volodymyr,
>
> On 21.08.25 19:46, Volodymyr Babchuk wrote:
>>=20
>>=20
>>=20
>> Leonid Komarianskyi  writes:
>>=20
>>> The Dom0 configuration logic in create_dom0() has been updated
>>> to account for extended SPIs when supported by the hardware and
>>> enabled with CONFIG_GICV3_ESPI. These changes ensure the proper
>>> calculation of the maximum number of SPIs and eSPIs available for Dom0.
>>>
>>> When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is
>>> enabled, the maximum number of eSPI interrupts is calculated using
>>> the ESPI_BASE_INTID offset (4096) and limited at 1024, with 32 IRQs
>>> subtracted. To ensure compatibility with non-Dom0 domains, this
>>> adjustment is applied by the toolstack during domain creation, while
>>> for Dom0 it is handled directly during VGIC initialization. If eSPIs
>>> are not supported, the calculation defaults to using the standard SPI
>>> range, with a maximum value of 992 interrupt lines as it works now.
>>>
>>> Signed-off-by: Leonid Komarianskyi 
>>>
>>> ---
>>> Changes in V2:
>>> - no changes
>>> ---
>>>   xen/arch/arm/domain_build.c     | 10 ++++++++++
>>>   xen/arch/arm/include/asm/vgic.h | 11 +++++++++++
>>>   2 files changed, 21 insertions(+)
>>>
>>> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
>>> index d91a71acfd..fa5abf2dfb 100644
>>> --- a/xen/arch/arm/domain_build.c
>>> +++ b/xen/arch/arm/domain_build.c
>>> @@ -2055,6 +2055,16 @@ void __init create_dom0(void)
>>>       /* The vGIC for DOM0 is exactly emulating the hardware GIC */
>>>       dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
>>>       dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS;
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    /*
>>> +     * Check if the hardware supports extended SPIs (even if the appro=
priate config is set).
>>> +     * If not, the common SPI range will be used. Otherwise overwrite =
the nr_spis with the
>>> +     * maximum available INTID from eSPI range. In that case, the numb=
er of regular SPIs will
>>> +     * be adjusted to the maximum value during vGIC initialization.
>>> +     */
>>> +    if ( gic_number_espis() > 0 )
>>> +        dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_ESPIS;
>>> +#endif
>>>       dom0_cfg.arch.tee_type =3D tee_get_type();
>>>       dom0_cfg.max_vcpus =3D dom0_max_vcpus();
>>>  =20
>>> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm=
/vgic.h
>>> index 9fa4523018..117b3aa92c 100644
>>> --- a/xen/arch/arm/include/asm/vgic.h
>>> +++ b/xen/arch/arm/include/asm/vgic.h
>>> @@ -353,6 +353,17 @@ extern void vgic_check_inflight_irqs_pending(struc=
t vcpu *v,
>>>   /* Default number of vGIC SPIs. 32 are substracted to cover local IRQ=
s. */
>>>   #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32=
)
>>>  =20
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +/*
>>> + * Returns the maximum eSPI INTID subtracted by 32. For non-Dom0 domai=
ns, the
>>> + * toolstack applies the same adjustment to cover local IRQs. We will =
add back
>>> + * this value during VGIC initialization. This ensures consistent hand=
ling for Dom0
>>> + * and other domains. For the regular SPI range interrupts in this cas=
e, the maximum
>>> + * value of VGIC_DEF_NR_SPIS will be used.
>>> + */
>>> +#define VGIC_DEF_NR_ESPIS (ESPI_BASE_INTID + min(gic_number_espis(), 1=
024U) - 32)
>> Name of the define is wrong, as it is not number of eSPIs. Actually, thi=
s is
>> maximum SPI (including eSPIs) number.
>
>
> Thank you for your review.
> Would it be okay if I rename this macro to VGIC_DEF_MAX_SPI?

Yes, I think this is better name.

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Topic: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Index: AQHcB5d76MRh/Swq2EGu624C+G/Fbw==
Date: Fri, 22 Aug 2025 12:28:08 +0000
Message-ID: <87sehjbkx4.fsf@epam.com>
References:
 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
	
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Leonid,

Leonid Komarianskyi  writes:

> Hi Volodymyr,
>
> Thank you for you comment.
>
> On 21.08.25 18:46, Volodymyr Babchuk wrote:
>>=20
>> Leonid Komarianskyi  writes:
>>=20
>>> Introduced two new helper functions for vGIC: vgic_is_valid_irq and
>>> vgic_is_shared_irq. The functions are similar to the newly introduced
>>> gic_is_valid_irq and gic_is_shared_irq, but they verify whether a vIRQ
>>> is available for a specific domain, while GIC-specific functions
>>> validate INTIDs for the real GIC hardware. For example, the GIC may
>>> support all 992 SPI lines, but the domain may use only some part of the=
m
>>> (e.g., 640), depending on the highest IRQ number defined in the domain
>>> configuration. Therefore, for vGIC-related code and checks, the
>>> appropriate functions should be used. Also, updated the appropriate
>>> checks to use these new helper functions.
>>>
>>> The purpose of introducing new helper functions for vGIC is essentially
>>> the same as for GIC: to avoid potential confusion with GIC-related
>>> checks and to consolidate similar code into separate functions, which
>>> can be more easily extended by additional conditions, e.g., when
>>> implementing extended SPI interrupts.
>>>
>>> Only the validation change in vgic_inject_irq may affect existing
>>> functionality, as it currently checks whether the vIRQ is less than or
>>> equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
>>> first SPI), the check should behave consistently with similar logic in
>>> other places and should check if the vIRQ number is less than
>>> vgic_num_irqs. The remaining changes, which replace open-coded checks
>>> with the use of these new helper functions, do not introduce any
>>> functional changes, as the helper functions follow the current vIRQ
>>> index verification logic.
>>>
>>> Signed-off-by: Leonid Komarianskyi 
>>>
>>> ---
>>> Changes in V2:
>>> - introduced this patch
>>> ---
>>>   xen/arch/arm/gic.c              |  3 +--
>>>   xen/arch/arm/include/asm/vgic.h |  7 +++++++
>>>   xen/arch/arm/irq.c              |  4 ++--
>>>   xen/arch/arm/vgic.c             | 10 ++++++++--
>>>   4 files changed, 18 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
>>> index eb0346a898..47fccf21d8 100644
>>> --- a/xen/arch/arm/gic.c
>>> +++ b/xen/arch/arm/gic.c
>>> @@ -133,8 +133,7 @@ int gic_route_irq_to_guest(struct domain *d, unsign=
ed int virq,
>>>  =20
>>>       ASSERT(spin_is_locked(&desc->lock));
>>>       /* Caller has already checked that the IRQ is an SPI */
>>> -    ASSERT(virq >=3D 32);
>>> -    ASSERT(virq < vgic_num_irqs(d));
>>> +    ASSERT(vgic_is_shared_irq(d, virq));
>>>       ASSERT(!is_lpi(virq));
>>>  =20
>>>       ret =3D vgic_connect_hw_irq(d, NULL, virq, desc, true);
>>> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm=
/vgic.h
>>> index 35c0c6a8b0..45201f4ca5 100644
>>> --- a/xen/arch/arm/include/asm/vgic.h
>>> +++ b/xen/arch/arm/include/asm/vgic.h
>>> @@ -335,6 +335,13 @@ extern void vgic_check_inflight_irqs_pending(struc=
t vcpu *v,
>>>   /* Default number of vGIC SPIs. 32 are substracted to cover local IRQ=
s. */
>>>   #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32=
)
>>>  =20
>>> +extern bool vgic_is_valid_irq(struct domain *d, unsigned int virq);
>>> +
>>> +static inline bool vgic_is_shared_irq(struct domain *d, unsigned int v=
irq)
>>> +{
>>> +    return (virq >=3D NR_LOCAL_IRQS && vgic_is_valid_irq(d, virq));
>>> +}
>>> +
>>>   /*
>>>    * Allocate a guest VIRQ
>>>    *  - spi =3D=3D 0 =3D> allocate a PPI. It will be the same on every =
vCPU
>>> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
>>> index 12c70d02cc..50e57aaea7 100644
>>> --- a/xen/arch/arm/irq.c
>>> +++ b/xen/arch/arm/irq.c
>>> @@ -442,7 +442,7 @@ int route_irq_to_guest(struct domain *d, unsigned i=
nt virq,
>>>       unsigned long flags;
>>>       int retval =3D 0;
>>>  =20
>>> -    if ( virq >=3D vgic_num_irqs(d) )
>>> +    if ( !vgic_is_valid_irq(d, virq) )
>>>       {
>>>           printk(XENLOG_G_ERR
>>>                  "the vIRQ number %u is too high for domain %u (max =3D=
 %u)\n",
>>> @@ -560,7 +560,7 @@ int release_guest_irq(struct domain *d, unsigned in=
t virq)
>>>       int ret;
>>>  =20
>>>       /* Only SPIs are supported */
>>> -    if ( virq < NR_LOCAL_IRQS || virq >=3D vgic_num_irqs(d) )
>>> +    if ( !vgic_is_shared_irq(d, virq) )
>>>           return -EINVAL;
>>>  =20
>>>       desc =3D vgic_get_hw_irq_desc(d, NULL, virq);
>>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
>>> index c563ba93af..48fbaf56fb 100644
>>> --- a/xen/arch/arm/vgic.c
>>> +++ b/xen/arch/arm/vgic.c
>>> @@ -24,6 +24,12 @@
>>>   #include 
>>>   #include 
>>>  =20
>>> +
>>> +bool vgic_is_valid_irq(struct domain *d, unsigned int virq)
>>=20
>> I have the same comment as for the previous patch. This function
>> completely ignores LPIs presence, while you can't argue that LPIs as
>> valid. Again, function callers are expecting this behavior, so this is
>> fine, but function name should better reflect its behavior.
>>=20
>> [...]
>>=20
>
> Would it be okay to rename these functions as proposed in the previous=20
> patch discussion:
> vgic_is_valid_irq -> vgic_is_valid_line
> vgic_is_shared_irq -> vgic_is_spi?
>
> Or, in the case of vgic, is it not a good idea to use the "line" suffix=20
> because vgic does not have physical interrupt lines? Would it be better=20
> to rename it to vgic_is_valid_non_lpi instead?

I think it is better to follow the pGIC naming convention. While there
is no physical IRQ lines in vGIC, it emulates real GIC anyways.

--=20
WBR, Volodymyr=


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From: Leonid Komarianskyi 
To: Julien Grall , Volodymyr Babchuk
	
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Topic: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcB5d7kgaRrTB4eUK2JDUmO9y7H7RtbrKAgAFGNYA=
Date: Fri, 22 Aug 2025 12:41:14 +0000
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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Topic: [PATCH v2 04/10] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcB5d7kgaRrTB4eUK2JDUmO9y7H7Ruud8A
Date: Fri, 22 Aug 2025 12:59:00 +0000
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To: Jan Beulich ,
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CC: "xen-devel@lists.xenproject.org" , "Daniel
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Subject: Re: [PATCH v3] common/efi: fix Rule 2.1 violation in read_file()
Thread-Topic: [PATCH v3] common/efi: fix Rule 2.1 violation in read_file()
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Date: Fri, 22 Aug 2025 13:14:24 +0000
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From: Dmytro Prokopchuk1 
To: Jan Beulich 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH] misra: fix Rule 11.3 violation in
 'vcpu_mark_events_pending'
Thread-Topic: [PATCH] misra: fix Rule 11.3 violation in
 'vcpu_mark_events_pending'
Thread-Index: AQHcEahzo6Ns4M/vpkyFl3Gc8+EN0rRs2qIAgAHTq4A=
Date: Fri, 22 Aug 2025 13:29:39 +0000
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From: "Teddy Astie" 
Subject: =?utf-8?Q?[PATCH]=20hvmloader:=20Update=20to=20SMBIOS=202.6?=
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Cc: "Teddy Astie" , "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" 
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Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).

In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
(undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
you have a endian mismatch causing the UUIDs to mismatch in the guest.

$ cat /sys/hypervisor/uuid
e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
$ cat /sys/devices/virtual/dmi/id/product_uuid
3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
$ cat /sys/devices/virtual/dmi/id/product_serial
e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7

This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
written in the table; which effectively fix this endianness mismatch with
OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.

Signed-off-by: Teddy Astie 
---
This effectively changes the UUID seen with UEFI guests as it was
actually inconsistent with SeaBIOS and SMBIOS expectations.
---
 tools/firmware/hvmloader/smbios.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/tools/firmware/hvmloader/smbios.c b/tools/firmware/hvmloader/smbios.c
index 6bcdcc233a..f4822ae6f8 100644
--- a/tools/firmware/hvmloader/smbios.c
+++ b/tools/firmware/hvmloader/smbios.c
@@ -352,7 +352,7 @@ smbios_entry_point_init(void *start,
     memcpy(ep->anchor_string, "_SM_", 4);
     ep->length = 0x1f;
     ep->smbios_major_version = 2;
-    ep->smbios_minor_version = 4;
+    ep->smbios_minor_version = 6;
     ep->max_structure_size = max_structure_size;
     ep->entry_point_revision = 0;
     memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
@@ -462,7 +462,23 @@ smbios_type_1_init(void *start, const char *xen_version,
     p->version_str = 3;
     p->serial_number_str = 4;
 
-    memcpy(p->uuid, uuid, 16);
+    /*
+     * Xen uses OSF DCE UUIDs which is fully big endian, however,
+     * GUIDs (which requirement is clarified by SMBIOS >= 2.6) has the
+     * first 3 components appearing as being little endian and the rest
+     * as still being big endian.
+     */
+    /* First component */
+    for ( unsigned int i = 0; i < 4; i++ )
+        p->uuid[i] = uuid[4 - i - 1];
+    /* Second component */
+    p->uuid[4] = uuid[5];
+    p->uuid[5] = uuid[4];
+    /* Third component */
+    p->uuid[6] = uuid[7];
+    p->uuid[7] = uuid[6];
+    /* Rest */
+    memcpy(p->uuid + 8, uuid + 8, 8);
 
     p->wake_up_type = 0x06; /* power switch */
     p->sku_str = 0;
-- 
2.50.1



 | Vates

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



From xen-devel-bounces@lists.xenproject.org Fri Aug 22 14:07:47 2025
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Date: Fri, 22 Aug 2025 16:07:37 +0200
From: Anthony PERARD 
To: Penny Zheng 
Cc: xen-devel@lists.xenproject.org, ray.huang@amd.com,
	Edgar.Iglesias@amd.com, Anthony PERARD ,
	Juergen Gross 
Subject: Re: [PATCH v1] tools: make "opengl" generic
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In-Reply-To: <20250728044007.4026420-1-Penny.Zheng@amd.com>

On Mon, Jul 28, 2025 at 12:40:07PM +0800, Penny Zheng wrote:
> Display option, like vnc, sdl, etc, will be checked against in latest QEMU
> whether it is compatile with opengl context. And vnc is incompatible with GL
> context.
> Now, when running hvm domain with gl context on, such as
> "device_model_args_hvm = ["-display", "sdl,gl=on"]", we will fail with
> the error of "qemu-system-i386: -vnc 127.0.0.1:0,to=99: Display vnc is
> incompatible with the GL context", as vnc is set enabled on default
> for HVM domain.
> 
> We shall move "opengl" option out of specifc sdl display, to make it

Unfurtunatly, we can't remove field from a struct in the public API of
libxl. You'll find some explanation about the "libxl API compatibility"
in "libxl.h". It's not well explain but "libxl_types.idl" is part of the
public API.

> generic. Then when users explicitly set "opengl = 1", default values for
> vnc shall be changed to disabled and libxl__dm_vnc() needs to return NULL
> indicating vnc being disabled.

> If users select both vnc and opengl in xl configuration, creation
> will fail and error out incompatible info.
> To keep consistency, we also make "opengl" generic for vfb[] options
> 
> Signed-off-by: Penny Zheng 

This patch description is a bit confusing to read to me. Right now, there's no
mention of "opengl" in the docs, or in `man xl.cfg`, even if "opengl=1"
seems to be a thing for `xl`.

In libxl code, it seems "opengl" is only an option for the PV display
interface, or VFB. So what I'm guessing is you want to add support to
HVM guest to have the opengl option working.

The patch description mention "-display sdl,gl=on", yet the patch itself
doesn't modify "-display sdl" to enable the gl context. Why?

The xl.cfg man page isn't forthcoming about it but the use of
"device_model_args*" is mainly useful for debugging, to allow to add
extra option without having to change libxl. If an option added there is
incompatible with the command line generated by libxl, then it would be
better to teach libxl to generate that option.


> diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
> index 28cdbf07c2..9e9adcec77 100644
> --- a/tools/xl/xl_parse.c
> +++ b/tools/xl/xl_parse.c
> @@ -2791,14 +2790,16 @@ skip_usbdev:
>  
>  #undef parse_extra_args
>  
> +    if (!xlu_cfg_get_long (config, "vnc", &l, 0))
> +        vnc_enabled = l;
> +    xlu_cfg_get_defbool(config, "opengl", &b_info->u.hvm.opengl, 0);
> +    if (vnc_enabled && libxl_defbool_val(b_info->u.hvm.opengl)) {
> +        fprintf(stderr, "vnc is incompatible with opengl\n");
> +        exit(1);

This sort of incompatibility need to at least live in libxl
(tools/libs/light). `xl` is only one of several users of `libxl`.


Thanks,

-- 
Anthony PERARD


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Subject: Re: [GIT PULL] xen: branch for v6.17-rc3
From: pr-tracker-bot@kernel.org
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The pull request you sent on Fri, 22 Aug 2025 07:31:20 +0200:

> git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git for-linus-6.17-rc3-tag

has been merged into torvalds/linux.git:
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Feedback-ID: i1568416f:Fastmail
Date: Fri, 22 Aug 2025 16:39:33 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: xen-devel 
Cc: Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	Boris Ostrovsky 
Subject: domU suspend issue - freeze processes failed - Linux 6.16
Message-ID: 
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	protocol="application/pgp-signature"; boundary="7NZxyHlq/zTlJ7mI"
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--7NZxyHlq/zTlJ7mI
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Date: Fri, 22 Aug 2025 16:39:33 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: xen-devel 
Cc: Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	Boris Ostrovsky 
Subject: domU suspend issue - freeze processes failed - Linux 6.16

Hi,

When suspending domU I get the following issue:

    Freezing user space processes
    Freezing user space processes failed after 20.004 seconds (1 tasks refu=
sing to freeze, wq_busy=3D0):
    task:xl              state:D stack:0     pid:466   tgid:466   ppid:1   =
   task_flags:0x400040 flags:0x00004006
    Call Trace:
     
     __schedule+0x2f3/0x780
     schedule+0x27/0x80
     schedule_preempt_disabled+0x15/0x30
     __mutex_lock.constprop.0+0x49f/0x880
     unregister_xenbus_watch+0x216/0x230
     xenbus_write_watch+0xb9/0x220
     xenbus_file_write+0x131/0x1b0
     vfs_writev+0x26c/0x3d0
     ? do_writev+0xeb/0x110
     do_writev+0xeb/0x110
     do_syscall_64+0x84/0x2c0
     ? do_syscall_64+0x200/0x2c0
     ? generic_handle_irq+0x3f/0x60
     ? syscall_exit_work+0x108/0x140
     ? do_syscall_64+0x200/0x2c0
     ? __irq_exit_rcu+0x4c/0xe0
     entry_SYSCALL_64_after_hwframe+0x76/0x7e
    RIP: 0033:0x79b618138642
    RSP: 002b:00007fff9a192fc8 EFLAGS: 00000246 ORIG_RAX: 0000000000000014
    RAX: ffffffffffffffda RBX: 00000000024fd490 RCX: 000079b618138642
    RDX: 0000000000000003 RSI: 00007fff9a193120 RDI: 0000000000000014
    RBP: 00007fff9a193000 R08: 0000000000000000 R09: 0000000000000000
    R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000014
    R13: 00007fff9a193120 R14: 0000000000000003 R15: 0000000000000000
     
    OOM killer enabled.
    Restarting tasks: Starting
    Restarting tasks: Done
    xen:manage: do_suspend: freeze processes failed -16

The process in question is `xl devd` daemon. It's a domU serving a
xenvif backend.

I noticed it on 6.16.1, but looking at earlier test logs I see it with
6.16-rc6 already (but interestingly, not 6.16-rc2 yet? feels weird given
seemingly no relevant changes between rc2 and rc6).

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

--7NZxyHlq/zTlJ7mI
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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[PATCH=20v1]=20tools:=20make=20"opengl"=20generic?=
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To: "Penny Zheng" , xen-devel@lists.xenproject.org
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Hello,

Le 28/07/2025 =C3=A0 06:45, Penny Zheng a =C3=A9crit=C2=A0:
> Display option, like vnc, sdl, etc, will be checked against in latest QEM=
U
> whether it is compatile with opengl context. And vnc is incompatible with=
 GL
> context.
> Now, when running hvm domain with gl context on, such as
> "device_model_args_hvm =3D ["-display", "sdl,gl=3Don"]", we will fail wit=
h
> the error of "qemu-system-i386: -vnc 127.0.0.1:0,to=3D99: Display vnc is
> incompatible with the GL context", as vnc is set enabled on default
> for HVM domain.
> 
> We shall move "opengl" option out of specifc sdl display, to make it
> generic. Then when users explicitly set "opengl =3D 1", default values fo=
r
> vnc shall be changed to disabled and libxl__dm_vnc() needs to return NULL
> indicating vnc being disabled.
> 
> If users select both vnc and opengl in xl configuration, creation
> will fail and error out incompatible info.
> To keep consistency, we also make "opengl" generic for vfb[] options
> 
> Signed-off-by: Penny Zheng 

There is a way to make vnc work with opengl by using the egl-headless 
display (-display egl-headless,gl=3Don), which can coexist along vnc. So 
that we could avoid having "opengl" as a sdl-specific option.

> ---
>   tools/libs/light/libxl_console.c |  4 ++--
>   tools/libs/light/libxl_create.c  | 10 ++++++----
>   tools/libs/light/libxl_dm.c      |  7 ++++++-
>   tools/libs/light/libxl_types.idl |  3 ++-
>   tools/xl/xl_parse.c              | 17 +++++++++--------
>   tools/xl/xl_sxp.c                |  6 +++---
>   6 files changed, 28 insertions(+), 19 deletions(-)
> 
> diff --git a/tools/libs/light/libxl_console.c b/tools/libs/light/libxl_co=
nsole.c
> index 044ca64676..fc3dfddc4d 100644
> --- a/tools/libs/light/libxl_console.c
> +++ b/tools/libs/light/libxl_console.c
> @@ -694,7 +694,7 @@ static int libxl__device_vfb_setdefault(libxl__gc *gc=
, uint32_t domid,
>       }
>   
>       libxl_defbool_setdefault(&vfb->sdl.enable, false);
> -    libxl_defbool_setdefault(&vfb->sdl.opengl, false);
> +    libxl_defbool_setdefault(&vfb->opengl, false);
>   
>       rc =3D libxl__resolve_domid(gc, vfb->backend_domname, &vfb->backend=
_domid);
>       return rc;
> @@ -733,7 +733,7 @@ static int libxl__set_xenstore_vfb(libxl__gc *gc, uin=
t32_t domid,
>       flexarray_append_pair(back, "sdl",
>                             libxl_defbool_val(vfb->sdl.enable) ? "1" : "0=
");
>       flexarray_append_pair(back, "opengl",
> -                          libxl_defbool_val(vfb->sdl.opengl) ? "1" : "0"=
);
> +                          libxl_defbool_val(vfb->opengl) ? "1" : "0");
>       if (vfb->sdl.xauthority) {
>           flexarray_append_pair(back, "xauthority", vfb->sdl.xauthority);
>       }
> diff --git a/tools/libs/light/libxl_create.c b/tools/libs/light/libxl_cre=
ate.c
> index 4301f17f90..7bbd1ff9b4 100644
> --- a/tools/libs/light/libxl_create.c
> +++ b/tools/libs/light/libxl_create.c
> @@ -339,7 +339,12 @@ int libxl__domain_build_info_setdefault(libxl__gc *g=
c,
>           if (!b_info->u.hvm.boot)
>               b_info->u.hvm.boot =3D libxl__strdup(NOGC, "cda");
>   
> -        libxl_defbool_setdefault(&b_info->u.hvm.vnc.enable, true);
> +        libxl_defbool_setdefault(&b_info->u.hvm.opengl, false);
> +
> +        if (libxl_defbool_val(b_info->u.hvm.opengl))
> +            libxl_defbool_setdefault(&b_info->u.hvm.vnc.enable, false);
> +        else
> +            libxl_defbool_setdefault(&b_info->u.hvm.vnc.enable, true);
>           if (libxl_defbool_val(b_info->u.hvm.vnc.enable)) {
>               libxl_defbool_setdefault(&b_info->u.hvm.vnc.findunused, tru=
e);
>               if (!b_info->u.hvm.vnc.listen)
> @@ -347,9 +352,6 @@ int libxl__domain_build_info_setdefault(libxl__gc *gc=
,
>           }
>   
>           libxl_defbool_setdefault(&b_info->u.hvm.sdl.enable, false);
> -        if (libxl_defbool_val(b_info->u.hvm.sdl.enable)) {
> -            libxl_defbool_setdefault(&b_info->u.hvm.sdl.opengl, false);
> -        }
>   
>           if (libxl_defbool_val(b_info->u.hvm.spice.enable)) {
>               libxl_defbool_setdefault(&b_info->u.hvm.spice.disable_ticke=
ting,
> diff --git a/tools/libs/light/libxl_dm.c b/tools/libs/light/libxl_dm.c
> index 511ec76a65..7adf473c81 100644
> --- a/tools/libs/light/libxl_dm.c
> +++ b/tools/libs/light/libxl_dm.c
> @@ -672,6 +672,10 @@ int libxl__domain_device_construct_rdm(libxl__gc *gc=
,
>   const libxl_vnc_info *libxl__dm_vnc(const libxl_domain_config *guest_co=
nfig)
>   {
>       const libxl_vnc_info *vnc =3D NULL;
> +
> +    if (libxl_defbool_val(guest_config->b_info.u.hvm.opengl))
> +        return NULL;
> +
>       if (guest_config->b_info.type =3D=3D LIBXL_DOMAIN_TYPE_HVM) {
>           vnc =3D &guest_config->b_info.u.hvm.vnc;
>       } else if (guest_config->num_vfbs > 0) {
> @@ -955,6 +959,7 @@ static int libxl__build_device_model_args_new(libxl__=
gc *gc,
>       const char *path, *chardev;
>       bool is_stubdom =3D libxl_defbool_val(b_info->device_model_stubdoma=
in);
>       int rc;
> +    bool has_opengl =3D libxl_defbool_val(b_info->u.hvm.opengl);
>   
>       dm_args =3D flexarray_make(gc, 16, 1);
>       dm_envs =3D flexarray_make(gc, 16, 1);
> @@ -1084,7 +1089,7 @@ static int libxl__build_device_model_args_new(libxl=
__gc *gc,
>           }
>   
>           flexarray_append(dm_args, vncarg);
> -    } else if (!is_stubdom) {
> +    } else if (!is_stubdom && !has_opengl) {
>           /*
>            * Ensure that by default no vnc server is created.
>            */
> diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_ty=
pes.idl
> index fe251649f3..ab768381ce 100644
> --- a/tools/libs/light/libxl_types.idl
> +++ b/tools/libs/light/libxl_types.idl
> @@ -349,7 +349,6 @@ libxl_spice_info =3D Struct("spice_info", [
>   
>   libxl_sdl_info =3D Struct("sdl_info", [
>       ("enable",        libxl_defbool),
> -    ("opengl",        libxl_defbool),
>       ("display",       string),
>       ("xauthority",    string),
>       ])
> @@ -670,6 +669,7 @@ libxl_domain_build_info =3D Struct("domain_build_info=
",[
>                                          ("acpi_firmware",    string),
>                                          ("hdtype",           libxl_hdtyp=
e),
>                                          ("nographic",        libxl_defbo=
ol),
> +                                       ("opengl",           libxl_defboo=
l),
>                                          ("vga",              libxl_vga_i=
nterface_info),
>                                          ("vnc",              libxl_vnc_i=
nfo),
>                                          # keyboard layout, default is en=
-us keyboard
> @@ -748,6 +748,7 @@ libxl_device_vfb =3D Struct("device_vfb", [
>       ("backend_domid", libxl_domid),
>       ("backend_domname",string),
>       ("devid",         libxl_devid),
> +    ("opengl",        libxl_defbool),
>       ("vnc",           libxl_vnc_info),
>       ("sdl",           libxl_sdl_info),
>       # set keyboard layout, default is en-us keyboard
> diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
> index 28cdbf07c2..9e9adcec77 100644
> --- a/tools/xl/xl_parse.c
> +++ b/tools/xl/xl_parse.c
> @@ -272,7 +272,6 @@ static void parse_top_level_sdl_options(XLU_Config *c=
onfig,
>                                           libxl_sdl_info *sdl)
>   {
>       xlu_cfg_get_defbool(config, "sdl", &sdl->enable, 0);
> -    xlu_cfg_get_defbool(config, "opengl", &sdl->opengl, 0);
>       xlu_cfg_replace_string (config, "display", &sdl->display, 0);
>       xlu_cfg_replace_string (config, "xauthority", &sdl->xauthority, 0);
>   }
> @@ -1291,7 +1290,7 @@ void parse_config_data(const char *config_source,
>   {
>       libxl_physinfo physinfo;
>       const char *buf;
> -    long l, vcpus =3D 0;
> +    long l, vcpus =3D 0, vnc_enabled =3D 0;
>       XLU_Config *config;
>       XLU_ConfigList *cpus, *vbds, *nics, *pcis, *cvfbs, *cpuids, *vtpms,
>                      *usbctrls, *usbdevs, *p9devs, *vdispls, *pvcallsifs_=
devs;
> @@ -2572,7 +2571,7 @@ skip_nic:
>                   } else if (!strcmp(p, "sdl")) {
>                       libxl_defbool_set(&vfb->sdl.enable, atoi(p2 + 1));
>                   } else if (!strcmp(p, "opengl")) {
> -                    libxl_defbool_set(&vfb->sdl.opengl, atoi(p2 + 1));
> +                    libxl_defbool_set(&vfb->opengl, atoi(p2 + 1));
>                   } else if (!strcmp(p, "display")) {
>                       free(vfb->sdl.display);
>                       vfb->sdl.display =3D strdup(p2 + 1);
> @@ -2791,14 +2790,16 @@ skip_usbdev:
>   
>   #undef parse_extra_args
>   
> +    if (!xlu_cfg_get_long (config, "vnc", &l, 0))
> +        vnc_enabled =3D l;
> +    xlu_cfg_get_defbool(config, "opengl", &b_info->u.hvm.opengl, 0);
> +    if (vnc_enabled && libxl_defbool_val(b_info->u.hvm.opengl)) {
> +        fprintf(stderr, "vnc is incompatible with opengl\n");
> +        exit(1);
> +    }
>       /* If we've already got vfb=3D[] for PV guest then ignore top level
>        * VNC config. */
>       if (c_info->type =3D=3D LIBXL_DOMAIN_TYPE_PV && !d_config->num_vfbs=
) {
> -        long vnc_enabled =3D 0;
> -
> -        if (!xlu_cfg_get_long (config, "vnc", &l, 0))
> -            vnc_enabled =3D l;
> -
>           if (vnc_enabled) {
>               libxl_device_vfb *vfb;
>               libxl_device_vkb *vkb;
> diff --git a/tools/xl/xl_sxp.c b/tools/xl/xl_sxp.c
> index 4383ad177a..62a1d012c6 100644
> --- a/tools/xl/xl_sxp.c
> +++ b/tools/xl/xl_sxp.c
> @@ -120,7 +120,7 @@ void printf_info_sexp(int domid, libxl_domain_config =
*d_config, FILE *fh)
>           fprintf(fh, "\t\t\t(sdl %s)\n",
>                  libxl_defbool_to_string(b_info->u.hvm.sdl.enable));
>           fprintf(fh, "\t\t\t(opengl %s)\n",
> -               libxl_defbool_to_string(b_info->u.hvm.sdl.opengl));
> +               libxl_defbool_to_string(b_info->u.hvm.opengl));
>           fprintf(fh, "\t\t\t(nographic %s)\n",
>                  libxl_defbool_to_string(b_info->u.hvm.nographic));
>           fprintf(fh, "\t\t\t(spice %s)\n",
> @@ -219,10 +219,10 @@ void printf_info_sexp(int domid, libxl_domain_confi=
g *d_config, FILE *fh)
>           fprintf(fh, "\t\t\t(vncunused %s)\n",
>                  libxl_defbool_to_string(d_config->vfbs[i].vnc.findunused=
));
>           fprintf(fh, "\t\t\t(keymap %s)\n", d_config->vfbs[i].keymap);
> +        fprintf(fh, "\t\t\t(opengl %s)\n",
> +               libxl_defbool_to_string(d_config->vfbs[i].opengl));
>           fprintf(fh, "\t\t\t(sdl %s)\n",
>                  libxl_defbool_to_string(d_config->vfbs[i].sdl.enable));
> -        fprintf(fh, "\t\t\t(opengl %s)\n",
> -               libxl_defbool_to_string(d_config->vfbs[i].sdl.opengl));
>           fprintf(fh, "\t\t\t(display %s)\n", d_config->vfbs[i].sdl.displ=
ay);
>           fprintf(fh, "\t\t\t(xauthority %s)\n", d_config->vfbs[i].sdl.xa=
uthority);
>           fprintf(fh, "\t\t)\n");



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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Feedback-ID: i1568416f:Fastmail
Date: Fri, 22 Aug 2025 16:42:08 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: xen-devel 
Cc: Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	Boris Ostrovsky 
Subject: Re: domU suspend issue - freeze processes failed - Linux 6.16
Message-ID: 
References: 
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--clAqg1t6X9s2sdLz
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Date: Fri, 22 Aug 2025 16:42:08 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: xen-devel 
Cc: Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	Boris Ostrovsky 
Subject: Re: domU suspend issue - freeze processes failed - Linux 6.16

On Fri, Aug 22, 2025 at 04:39:33PM +0200, Marek Marczykowski-G=C3=B3recki w=
rote:
> Hi,
>=20
> When suspending domU I get the following issue:
>=20
>     Freezing user space processes
>     Freezing user space processes failed after 20.004 seconds (1 tasks re=
fusing to freeze, wq_busy=3D0):
>     task:xl              state:D stack:0     pid:466   tgid:466   ppid:1 =
     task_flags:0x400040 flags:0x00004006
>     Call Trace:
>      
>      __schedule+0x2f3/0x780
>      schedule+0x27/0x80
>      schedule_preempt_disabled+0x15/0x30
>      __mutex_lock.constprop.0+0x49f/0x880
>      unregister_xenbus_watch+0x216/0x230
>      xenbus_write_watch+0xb9/0x220
>      xenbus_file_write+0x131/0x1b0
>      vfs_writev+0x26c/0x3d0
>      ? do_writev+0xeb/0x110
>      do_writev+0xeb/0x110
>      do_syscall_64+0x84/0x2c0
>      ? do_syscall_64+0x200/0x2c0
>      ? generic_handle_irq+0x3f/0x60
>      ? syscall_exit_work+0x108/0x140
>      ? do_syscall_64+0x200/0x2c0
>      ? __irq_exit_rcu+0x4c/0xe0
>      entry_SYSCALL_64_after_hwframe+0x76/0x7e
>     RIP: 0033:0x79b618138642
>     RSP: 002b:00007fff9a192fc8 EFLAGS: 00000246 ORIG_RAX: 0000000000000014
>     RAX: ffffffffffffffda RBX: 00000000024fd490 RCX: 000079b618138642
>     RDX: 0000000000000003 RSI: 00007fff9a193120 RDI: 0000000000000014
>     RBP: 00007fff9a193000 R08: 0000000000000000 R09: 0000000000000000
>     R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000014
>     R13: 00007fff9a193120 R14: 0000000000000003 R15: 0000000000000000
>      
>     OOM killer enabled.
>     Restarting tasks: Starting
>     Restarting tasks: Done
>     xen:manage: do_suspend: freeze processes failed -16
>=20
> The process in question is `xl devd` daemon. It's a domU serving a
> xenvif backend.
>=20
> I noticed it on 6.16.1, but looking at earlier test logs I see it with
> 6.16-rc6 already (but interestingly, not 6.16-rc2 yet? feels weird given
> seemingly no relevant changes between rc2 and rc6).

I forgot to include link for (a little) more details:
https://github.com/QubesOS/qubes-linux-kernel/pull/1157

Especially, there is another call trace with panic_on_warn enabled -
slightly different, but looks related.

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Date: Fri, 22 Aug 2025 07:53:59 -0700 (PDT)
From: Stefano Stabellini 
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To: Jan Beulich 
cc: Stefano Stabellini , 
    "Penny, Zheng" , "Huang, Ray" , 
    Andrew Cooper , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Anthony PERARD , 
    "Orzel, Michal" , Julien Grall , 
    "xen-devel@lists.xenproject.org" , 
    Oleksii Kurochko 
Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
In-Reply-To: 
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References: <20250815102728.1340505-1-Penny.Zheng@amd.com>   <43f0c9a6-a4f3-44e0-959f-a021ae3b0466@suse.com>
  
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On Fri, 22 Aug 2025, Jan Beulich wrote:
> >> I'm sorry if my request was unclear, but with "full round of testing" I in particular
> >> meant a full CI pipeline, plus (given the issue that's being fixed) some extra
> >> randconfig testing.
> > 
> > https://gitlab.com/xen-project/people/sstabellini/xen/-/pipelines/1997431361
> > 
> > I ran a few tests myself changing config options on purpose trying to
> > break it, and so far they were all successful.
> 
> Should I translate this to Tested-by: then?

Yes


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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
 to support eSPIs
Thread-Topic: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
 to support eSPIs
Thread-Index: AQHcB5d9D2bB2ytT+0KvuTkMlpIiH7Ru3KEA
Date: Fri, 22 Aug 2025 15:03:25 +0000
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References:
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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Topic: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Index: AQHcB5d76MRh/Swq2EGu624C+G/Fb7Ru3gyA
Date: Fri, 22 Aug 2025 15:08:30 +0000
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 <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 
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Message-ID: <05e9628d-83e5-4feb-881d-5854b72bd560@suse.com>
Date: Fri, 22 Aug 2025 17:27:20 +0200
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Subject: Re: domU suspend issue - freeze processes failed - Linux 6.16
To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , xen-devel 
Cc: Stefano Stabellini ,
 Oleksandr Tyshchenko ,
 Boris Ostrovsky 
References:  
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From: =?UTF-8?B?SsO8cmdlbiBHcm/Dnw==?= 
To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , xen-devel 
Cc: Stefano Stabellini ,
 Oleksandr Tyshchenko ,
 Boris Ostrovsky 
Message-ID: <05e9628d-83e5-4feb-881d-5854b72bd560@suse.com>
Subject: Re: domU suspend issue - freeze processes failed - Linux 6.16
References:  
In-Reply-To: 

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From: Dmytro Prokopchuk1 
To: Nicola Vetrini , Jan Beulich
	
CC: Doug Goldstein , Stefano Stabellini
	, Andrew Cooper , Anthony
 PERARD , Michal Orzel ,
	Julien Grall , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, "xen-devel@lists.xenproject.org"
	
Subject: Re: [PATCH] misra: consider conversion from UL or (void*) to function
 pointer as safe
Thread-Topic: [PATCH] misra: consider conversion from UL or (void*) to
 function pointer as safe
Thread-Index: AQHcETrg9Y9S2hDXvUqVfYmm522krbRswSIAgAAGvACAAhrPAA==
Date: Fri, 22 Aug 2025 16:34:02 +0000
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Feedback-ID: i1568416f:Fastmail
Date: Fri, 22 Aug 2025 20:42:30 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= 
Cc: xen-devel ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	Boris Ostrovsky 
Subject: Re: domU suspend issue - freeze processes failed - Linux 6.16
Message-ID: 
References: 
 
 <05e9628d-83e5-4feb-881d-5854b72bd560@suse.com>
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--awCzYWA5QtUvFfQA
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Date: Fri, 22 Aug 2025 20:42:30 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= 
Cc: xen-devel ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	Boris Ostrovsky 
Subject: Re: domU suspend issue - freeze processes failed - Linux 6.16

On Fri, Aug 22, 2025 at 05:27:20PM +0200, J=C3=BCrgen Gro=C3=9F wrote:
> On 22.08.25 16:42, Marek Marczykowski-G=C3=B3recki wrote:
> > On Fri, Aug 22, 2025 at 04:39:33PM +0200, Marek Marczykowski-G=C3=B3rec=
ki wrote:
> > > Hi,
> > >=20
> > > When suspending domU I get the following issue:
> > >=20
> > >      Freezing user space processes
> > >      Freezing user space processes failed after 20.004 seconds (1 tas=
ks refusing to freeze, wq_busy=3D0):
> > >      task:xl              state:D stack:0     pid:466   tgid:466   pp=
id:1      task_flags:0x400040 flags:0x00004006
> > >      Call Trace:
> > >       
> > >       __schedule+0x2f3/0x780
> > >       schedule+0x27/0x80
> > >       schedule_preempt_disabled+0x15/0x30
> > >       __mutex_lock.constprop.0+0x49f/0x880
> > >       unregister_xenbus_watch+0x216/0x230
> > >       xenbus_write_watch+0xb9/0x220
> > >       xenbus_file_write+0x131/0x1b0
> > >       vfs_writev+0x26c/0x3d0
> > >       ? do_writev+0xeb/0x110
> > >       do_writev+0xeb/0x110
> > >       do_syscall_64+0x84/0x2c0
> > >       ? do_syscall_64+0x200/0x2c0
> > >       ? generic_handle_irq+0x3f/0x60
> > >       ? syscall_exit_work+0x108/0x140
> > >       ? do_syscall_64+0x200/0x2c0
> > >       ? __irq_exit_rcu+0x4c/0xe0
> > >       entry_SYSCALL_64_after_hwframe+0x76/0x7e
> > >      RIP: 0033:0x79b618138642
> > >      RSP: 002b:00007fff9a192fc8 EFLAGS: 00000246 ORIG_RAX: 0000000000=
000014
> > >      RAX: ffffffffffffffda RBX: 00000000024fd490 RCX: 000079b618138642
> > >      RDX: 0000000000000003 RSI: 00007fff9a193120 RDI: 0000000000000014
> > >      RBP: 00007fff9a193000 R08: 0000000000000000 R09: 0000000000000000
> > >      R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000014
> > >      R13: 00007fff9a193120 R14: 0000000000000003 R15: 0000000000000000
> > >       
> > >      OOM killer enabled.
> > >      Restarting tasks: Starting
> > >      Restarting tasks: Done
> > >      xen:manage: do_suspend: freeze processes failed -16
> > >=20
> > > The process in question is `xl devd` daemon. It's a domU serving a
> > > xenvif backend.
> > >=20
> > > I noticed it on 6.16.1, but looking at earlier test logs I see it with
> > > 6.16-rc6 already (but interestingly, not 6.16-rc2 yet? feels weird gi=
ven
> > > seemingly no relevant changes between rc2 and rc6).
> >=20
> > I forgot to include link for (a little) more details:
> > https://github.com/QubesOS/qubes-linux-kernel/pull/1157
> >=20
> > Especially, there is another call trace with panic_on_warn enabled -
> > slightly different, but looks related.
> >=20
>=20
> I'm pretty sure the PV variant for suspending is just wrong: it is calling
> dpm_suspend_start() from do_suspend() without taking the required
> system_transition_mutex, resulting in the WARN() in pm_restrict_gfp_mask(=
).
>=20
> It might be as easy as just adding the mutex() call to do_suspend(), but =
I'm
> really not sure that will be a proper fix.

Hm, this might explain the second call trace, but not the freeze failure
quoted here above, I think?


--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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From xen-devel-bounces@lists.xenproject.org Fri Aug 22 20:10:05 2025
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Date: Fri, 22 Aug 2025 13:09:13 -0700
From: Elliott Mitchell 
To: Jan Beulich 
Cc: Demi Marie Obenour , xen-users@lists.xenproject.org,
        xen-devel@lists.xenproject.org,
        Stefano Stabellini ,
        Julien Grall ,
        Bertrand Marquis ,
        Michal Orzel ,
        Volodymyr Babchuk ,
        Paul Leiber 
Subject: Re: Consider changing CONFIG_ACPI default on ARM?
Message-ID: 
References: 
 
 
 <1b96f2f3-55a2-4b33-84b1-a7c18d38d10c@suse.com>
 <6e9b5265-7a3b-4fd5-b14e-0e60a8b49833@gmail.com>
 
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On Fri, Aug 15, 2025 at 10:14:42AM +0200, Jan Beulich wrote:
> On 14.08.2025 23:27, Demi Marie Obenour wrote:
> > On 8/14/25 02:55, Jan Beulich wrote:
> >> On 06.08.2025 06:30, Elliott Mitchell wrote:
> >>> On Tue, Jul 01, 2025 at 10:01:13PM +0200, Paul Leiber wrote:
> >>>>
> >>>> Unfortunately, I don't have a direct answer to the question (as is so often
> >>>> the case, due to my limited knowledge and experience). However, I am
> >>>> successfully running Xen on a RPi 4 (mostly, except for some VLAN related
> >>>> networking issues).
> >>>>
> >>>> I used instructions in [1] to install vanilla Debian on the RPi, including
> >>>> UEFI boot and grub. I then compiled Xen with expert options and ACPI
> >>>> enabled.
> >>>>
> >>>> I don't know if there are better solutions. For example, I suffer from the
> >>>> fact that I2C doesn't work when using UEFI boot on a RPi. Nowadays, Debian
> >>>> provides their own vanilla Debian images for RPi and with working I2C, but
> >>>> these images are using a different boot method that I didn't know how to use
> >>>> with Xen.  So far, the procedure described above seems to be the easiest
> >>>> solution for me.
> >>>
> >>>
> >>>> [1] https://forums.raspberrypi.com/viewtopic.php?t=282839
> >>>>
> >>>> Am 30.06.2025 um 12:35 schrieb Sumit Semwal:
> >>>>>
> >>>>> I've just begun to experiment with the Raspberry Pi 5, trying to run a
> >>>>> simple xen + Dom0 setup, using uBoot, and the bookworm based Rpi
> >>>>> distro.
> >>>>>
> >>>>> I've tried combinations of the following setup:
> >>>>>
> >>>>> 1. prebuilt Rpi5 kernel + dtbs, and have also tried to build them from
> >>>>> source [1]
> >>>>> 2. Xen from upstream [2] and xen-troops [3]
> >>>>> 3. upstream uBoot from [4]
> >>>>>
> >>>>> but with the same result: [short log below; I can provide a fuller log
> >>>>> if needed]
> >>>>>
> >>>>> (XEN) DT: ** translation for device /axi/msi-controller@1000130000 **
> >>>>> (XEN) DT: bus is default (na=2, ns=2) on /axi
> >>>>> (XEN) DT: translating address:<3> 000000ff<3> fffff000<3>
> >>>>> (XEN) DT: parent bus is default (na=2, ns=1) on /
> >>>>> (XEN) DT: walking ranges...
> >>>>> (XEN) DT: default map, cp=0, s=1000000000, da=fffffff000
> >>>>> (XEN) DT: default map, cp=1000000000, s=100000000, da=fffffff000
> >>>>> (XEN) DT: default map, cp=1400000000, s=400000000, da=fffffff000
> >>>>> (XEN) DT: default map, cp=1800000000, s=400000000, da=fffffff000
> >>>>> (XEN) DT: default map, cp=1c00000000, s=400000000, da=fffffff000
> >>>>> (XEN) DT: not found !
> >>>>> (XEN) Unable to retrieve address 1 for /axi/msi-controller@1000130000
> >>>>> (XEN) Device tree generation failed (-22).
> >>>>> (XEN) debugtrace_dump() global buffer starting
> >>>>> 1 cpupool_create(pool=0,sched=6)
> >>>>> 2 Created cpupool 0 with scheduler SMP Credit Scheduler rev2 (credit2)
> >>>>> 3 cpupool_add_domain(dom=0,pool=0) n_dom 1 rc 0
> >>>>> (XEN) wrap: 0
> >>>>> (XEN) debugtrace_dump() global buffer finished
> >>>>> (XEN)
> >>>>> (XEN) ****************************************
> >>>>> (XEN) Panic on CPU 0:
> >>>>> (XEN) Could not set up DOM0 guest OS (rc = -22)
> >>>>> (XEN) ****************************************
> >>>>>
> >>>>>
> >>>>> I'm certain I'm missing something, but before I delve deeper, I just
> >>>>> wanted to ask if this is a known issue, and if so, are there any
> >>>>> workarounds or solutions available for this?
> >>>>>
> >>>>> Any help about this is highly appreciated!
> >>>>>
> >>>>> Thanks and Best regards,
> >>>>> Sumit.
> >>>>>
> >>>>> [1]:  https://github.com/raspberrypi/linux rpi-6.12.y branch
> >>>>> [2]: git://xenbits.xen.org/xen.git - main branch
> >>>>> [3] xen-troops https://github.com/xen-troops/xen - rpi5_dev branch
> >>>>> [4]: https://github.com/u-boot/u-boot.git master branch
> >>>
> >>> Ultimately Debian is choosing to leave most defaults alone.  So far the
> >>> Xen developers have left CONFIG_ACPI defaulting to off on ARM*.  The
> >>> Debian project doesn't have paid people to support Raspberry PI hardware,
> >>> despite being rather common.  As a result there aren't any official
> >>> Raspberry PI images, but people associated with Tianocore have gotten
> >>> generic images to boot on Raspberry PI hardware.
> >>>
> >>> I'm unsure of the likelihood of getting the Debian maintainers to
> >>> override the default.  Yet due being by far the simplest way to install
> >>> Debian and Xen on a very common ARM64 platform, perhaps the Xen
> >>> developers should consider changing?
> >>
> >> In an open source project everyone is a developer. There is a
> >> significant amount of work someone needs to pick up to change this
> >> SUPPORT.md entry:
> >>
> >> ### Host ACPI (via Domain 0)
> >>
> >>     Status, x86 PV: Supported
> >>     Status, ARM: Experimental
> >>
> >> Parties interested in changing the support status of any component are the
> >> primary candidates to actually carry out the necessary work.
> > 
> > What is that work?
> 
> To determine what exactly needs doing is part of the exercise. I, for one, am
> unaware of a concrete written down set of things which need doing.

Since you're not pointing to anything definite, could it be everything
has been resolved?  We've got at least two people for whom ACPI on ARM
works pretty well.  There may be many more using it.  Perhaps this
should even be done on the 4.20 branch given how long this has been
working?

The one remaining major issue was the state of EFI-FB support.  There
was a patch which had that working for Linux kernel 5.10, but that might
need more work for a proper solution.


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Initialize xencons_interface's connection field to
XENCONSOLE_DISCONNECTED.  xenconsoled will mark the page as connected
when it establishes the connection.

Signed-off-by: Jason Andryuk 
---
xc_dom_console_init() seems closer to the functionality of the gnttab
functions, so I put it in xg_dom_boot.c.  It can't take a struct
xc_dom_image pointer when used with save/restore.

v2:
New
---
 tools/include/xenguest.h       |  2 ++
 tools/libs/guest/xg_dom_arm.c  |  2 +-
 tools/libs/guest/xg_dom_boot.c | 20 ++++++++++++++++++++
 tools/libs/guest/xg_dom_x86.c  |  6 +++---
 4 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/tools/include/xenguest.h b/tools/include/xenguest.h
index e01f494b77..1d5a6d3509 100644
--- a/tools/include/xenguest.h
+++ b/tools/include/xenguest.h
@@ -335,6 +335,8 @@ void *xc_dom_boot_domU_map(struct xc_dom_image *dom, xen_pfn_t pfn,
                            xen_pfn_t count);
 int xc_dom_boot_image(struct xc_dom_image *dom);
 int xc_dom_compat_check(struct xc_dom_image *dom);
+int xc_dom_console_init(xc_interface *xch, uint32_t guest_domid,
+                        xen_pfn_t console_gfn);
 int xc_dom_gnttab_init(struct xc_dom_image *dom);
 int xc_dom_gnttab_seed(xc_interface *xch, uint32_t guest_domid,
                        bool is_hvm,
diff --git a/tools/libs/guest/xg_dom_arm.c b/tools/libs/guest/xg_dom_arm.c
index 2fd8ee7ad4..c8d0918506 100644
--- a/tools/libs/guest/xg_dom_arm.c
+++ b/tools/libs/guest/xg_dom_arm.c
@@ -70,7 +70,7 @@ static int alloc_magic_pages(struct xc_dom_image *dom)
     dom->xenstore_pfn = base + XENSTORE_PFN_OFFSET;
     dom->vuart_gfn = base + VUART_PFN_OFFSET;
 
-    xc_clear_domain_page(dom->xch, dom->guest_domid, dom->console_pfn);
+    xc_dom_console_init(dom->xch, dom->guest_domid, dom->console_pfn);
     xc_clear_domain_page(dom->xch, dom->guest_domid, dom->xenstore_pfn);
     xc_clear_domain_page(dom->xch, dom->guest_domid, base + MEMACCESS_PFN_OFFSET);
     xc_clear_domain_page(dom->xch, dom->guest_domid, dom->vuart_gfn);
diff --git a/tools/libs/guest/xg_dom_boot.c b/tools/libs/guest/xg_dom_boot.c
index 5c7e12221d..b5f248e642 100644
--- a/tools/libs/guest/xg_dom_boot.c
+++ b/tools/libs/guest/xg_dom_boot.c
@@ -34,6 +34,7 @@
 #include "xg_core.h"
 #include 
 #include 
+#include 
 
 /* ------------------------------------------------------------------------ */
 
@@ -427,6 +428,25 @@ int xc_dom_gnttab_init(struct xc_dom_image *dom)
                               dom->console_domid, dom->xenstore_domid);
 }
 
+int xc_dom_console_init(xc_interface *xch,
+                        uint32_t domid,
+                        unsigned long dst_pfn)
+{
+    const size_t size = PAGE_SIZE;
+    struct xencons_interface *xencons = xc_map_foreign_range(
+        xch, domid, size, PROT_WRITE, dst_pfn);
+
+    if ( xencons == NULL )
+        return -1;
+
+    memset(xencons, 0, size);
+    xencons->connection = XENCONSOLE_DISCONNECTED;
+
+    munmap(xencons, size);
+    xc_domain_cacheflush(xch, domid, dst_pfn, 1);
+    return 0;
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/tools/libs/guest/xg_dom_x86.c b/tools/libs/guest/xg_dom_x86.c
index cba01384ae..a82b481a12 100644
--- a/tools/libs/guest/xg_dom_x86.c
+++ b/tools/libs/guest/xg_dom_x86.c
@@ -587,8 +587,8 @@ static int alloc_magic_pages_pv(struct xc_dom_image *dom)
     dom->console_pfn = xc_dom_alloc_page(dom, "console");
     if ( dom->console_pfn == INVALID_PFN )
         return -1;
-    xc_clear_domain_page(dom->xch, dom->guest_domid,
-                         xc_dom_p2m(dom, dom->console_pfn));
+    xc_dom_console_init(dom->xch, dom->guest_domid,
+                        xc_dom_p2m(dom, dom->console_pfn));
 
     dom->alloc_bootstack = 1;
 
@@ -734,7 +734,7 @@ static int alloc_magic_pages_hvm(struct xc_dom_image *dom)
                      special_pfn(SPECIALPAGE_IDENT_PT) << PAGE_SHIFT);
 
     dom->console_pfn = special_pfn(SPECIALPAGE_CONSOLE);
-    xc_clear_domain_page(dom->xch, dom->guest_domid, dom->console_pfn);
+    xc_dom_console_init(dom->xch, dom->guest_domid, dom->console_pfn);
 
     dom->xenstore_pfn = special_pfn(SPECIALPAGE_XENSTORE);
     xc_clear_domain_page(dom->xch, dom->guest_domid, dom->xenstore_pfn);
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Alejandro Vallejo , Jason Andryuk
	, Anthony PERARD , "Juergen
 Gross" 
Subject: [PATCH v2 3/3] libs/guest: Set console as disconnected on resume
Date: Fri, 22 Aug 2025 17:39:45 -0400
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There is currently an asymmetry between HVM where the page is cleared
and PV where the contents are restored.

Add xc_dom_console_set_disconnected() to only set the connection flag
for PV guests.

xenconsoled is responsible for setting the console connected when it
attaches.

Signed-off-by: Jason Andryuk 
---
v2:
New
---
 tools/include/xenguest.h                 |  2 ++
 tools/libs/guest/xg_dom_boot.c           | 24 ++++++++++++++++++++----
 tools/libs/guest/xg_sr_restore_x86_hvm.c |  2 +-
 tools/libs/guest/xg_sr_restore_x86_pv.c  |  1 +
 4 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/tools/include/xenguest.h b/tools/include/xenguest.h
index 1d5a6d3509..c88958faa9 100644
--- a/tools/include/xenguest.h
+++ b/tools/include/xenguest.h
@@ -337,6 +337,8 @@ int xc_dom_boot_image(struct xc_dom_image *dom);
 int xc_dom_compat_check(struct xc_dom_image *dom);
 int xc_dom_console_init(xc_interface *xch, uint32_t guest_domid,
                         xen_pfn_t console_gfn);
+int xc_dom_console_set_disconnected(xc_interface *xch, uint32_t guest_domid,
+                                    xen_pfn_t console_gfn);
 int xc_dom_gnttab_init(struct xc_dom_image *dom);
 int xc_dom_gnttab_seed(xc_interface *xch, uint32_t guest_domid,
                        bool is_hvm,
diff --git a/tools/libs/guest/xg_dom_boot.c b/tools/libs/guest/xg_dom_boot.c
index b5f248e642..f51b6a78c8 100644
--- a/tools/libs/guest/xg_dom_boot.c
+++ b/tools/libs/guest/xg_dom_boot.c
@@ -428,9 +428,10 @@ int xc_dom_gnttab_init(struct xc_dom_image *dom)
                               dom->console_domid, dom->xenstore_domid);
 }
 
-int xc_dom_console_init(xc_interface *xch,
-                        uint32_t domid,
-                        unsigned long dst_pfn)
+static int dom_console_init(xc_interface *xch,
+                            uint32_t domid,
+                            unsigned long dst_pfn,
+                            bool clear)
 {
     const size_t size = PAGE_SIZE;
     struct xencons_interface *xencons = xc_map_foreign_range(
@@ -439,7 +440,8 @@ int xc_dom_console_init(xc_interface *xch,
     if ( xencons == NULL )
         return -1;
 
-    memset(xencons, 0, size);
+    if (clear)
+        memset(xencons, 0, size);
     xencons->connection = XENCONSOLE_DISCONNECTED;
 
     munmap(xencons, size);
@@ -447,6 +449,20 @@ int xc_dom_console_init(xc_interface *xch,
     return 0;
 }
 
+int xc_dom_console_init(xc_interface *xch,
+                        uint32_t domid,
+                        unsigned long dst_pfn)
+{
+    return dom_console_init(xch, domid, dst_pfn, true);
+}
+
+int xc_dom_console_set_disconnected(xc_interface *xch,
+                                    uint32_t domid,
+                                    unsigned long dst_pfn)
+{
+    return dom_console_init(xch, domid, dst_pfn, false);
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/tools/libs/guest/xg_sr_restore_x86_hvm.c b/tools/libs/guest/xg_sr_restore_x86_hvm.c
index d6ea6f3012..a5d1511fde 100644
--- a/tools/libs/guest/xg_sr_restore_x86_hvm.c
+++ b/tools/libs/guest/xg_sr_restore_x86_hvm.c
@@ -62,7 +62,7 @@ static int handle_hvm_params(struct xc_sr_context *ctx,
         {
         case HVM_PARAM_CONSOLE_PFN:
             ctx->restore.console_gfn = entry->value;
-            xc_clear_domain_page(xch, ctx->domid, entry->value);
+            xc_dom_console_init(xch, ctx->domid, entry->value);
             break;
         case HVM_PARAM_STORE_PFN:
             ctx->restore.xenstore_gfn = entry->value;
diff --git a/tools/libs/guest/xg_sr_restore_x86_pv.c b/tools/libs/guest/xg_sr_restore_x86_pv.c
index 9cd6a88022..876748c11e 100644
--- a/tools/libs/guest/xg_sr_restore_x86_pv.c
+++ b/tools/libs/guest/xg_sr_restore_x86_pv.c
@@ -208,6 +208,7 @@ static int process_start_info(struct xc_sr_context *ctx,
         goto err;
     }
 
+    xc_dom_console_set_disconnected(xch, ctx->domid, mfn);
     ctx->restore.console_gfn = mfn;
     SET_FIELD(guest_start_info, console.domU.mfn, mfn, ctx->x86.pv.width);
     SET_FIELD(guest_start_info, console.domU.evtchn,
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Alejandro Vallejo , Jason Andryuk
	, Anthony PERARD , "Juergen
 Gross" 
Subject: [PATCH v2 0/3] xenconsole: Add connection flag
Date: Fri, 22 Aug 2025 17:39:42 -0400
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Add a connection flag to the console interface page so a domain can tell
if it is connected or not.  This became a series in v2 to add flag
setting to libxenguest.

Jason Andryuk (3):
  xenconsole: Add connection flag
  libs/guest: Set console page to disconnected
  libs/guest: Set console as disconnected on resume

 tools/console/daemon/io.c                |  4 +++
 tools/include/xenguest.h                 |  4 +++
 tools/libs/guest/xg_dom_arm.c            |  2 +-
 tools/libs/guest/xg_dom_boot.c           | 36 ++++++++++++++++++++++++
 tools/libs/guest/xg_dom_x86.c            |  6 ++--
 tools/libs/guest/xg_sr_restore_x86_hvm.c |  2 +-
 tools/libs/guest/xg_sr_restore_x86_pv.c  |  1 +
 xen/include/public/io/console.h          | 13 +++++++++
 8 files changed, 63 insertions(+), 5 deletions(-)

-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Alejandro Vallejo , Jason Andryuk
	, Anthony PERARD , "Juergen
 Gross" 
Subject: [PATCH v2 1/3] xenconsole: Add connection flag
Date: Fri, 22 Aug 2025 17:39:43 -0400
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With hyperlaunch, a domU can start before its console ring is connected
by xenconsoled.  With nothing emptying the ring, it can quickly fill
during boot.  In domU_write_console(), __write_console() returns 0 when
the ring is full.  This loops spins until xenconsoled starts emptying
the ring:

        while (len) {
                ssize_t sent = __write_console(cons, data, len);

                if (sent < 0)
                        return sent;

                data += sent;
                len -= sent;

                if (unlikely(len))
                        HYPERVISOR_sched_op(SCHEDOP_yield, NULL);
        }

The goal of this patch is to add a way for the frontend to know when a
console is connected.  This patch adds a new flag to the end of the
console ring structure.  It is used for the backend to indicate that it
has connected and started servicing the page.

The two values are
XENCONSOLE_DISCONNECTED 1
XENCONSOLE_CONNECTED    0

XENCONSOLE_DISCONNECTED indicates to the guest that ring is
disconnected, so it will not be serviced.  The guest can avoid writing
into it in that case.  A domU can use console hypercalls and only
transition to the ring when it is connected and won't fill and block.

Once the backend (xenconsoled) maps and starts servicing the
console, the flag will be set to XENCONSOLE_CONNECTED (0) to indicate
the backend state to the frontend.

The connected value as 0 will be match the default of a zero-ed console
page.  Hyperlaunch can set the flag to XENCONSOLE_DISCONNECTED and let
xenconsoled set to XENCONSOLE_CONNECTED.

Old domU hvc_xen drivers won't check the flag.
New domU hvc_xen running on a new xen/xenconsoled will work properly.
New domU hvc_xen on old xen/xenconsoled should only see a 0 for the flag
and behave as if connected.

Signed-off-by: Jason Andryuk 
---
v2:
Rename "connection"
Use uint8_t

v1:
Remove evtchn notify call
Set connected later when there is no error

RFC v3:
Flip flag values so 0 is connected.

The other option would be to add:
uint32_t features
uint32_t connected

New domUs would check features for a magic value and/or flag to know
they can rely on connected transitioning.

I think making XENCONSOLE_CONNECTED == 0 side steps the need for
an additional features field.  As long as assuming zero-ed memory is
acceptable.  However, this only matters for a hyperlaunched guest -
xenconsoled will normally readily connect the console and set the value.

This assumes that existing frontends are not using the flag space for
some other use.
---
 tools/console/daemon/io.c       |  4 ++++
 xen/include/public/io/console.h | 13 +++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/tools/console/daemon/io.c b/tools/console/daemon/io.c
index bb739bdb8c..43d4973c24 100644
--- a/tools/console/daemon/io.c
+++ b/tools/console/daemon/io.c
@@ -781,6 +781,10 @@ static int console_create_ring(struct console *con)
 		con->log_fd = create_console_log(con);
 
  out:
+	/* Mark the console connected. */
+	if (!err && con->interface)
+		con->interface->connection = XENCONSOLE_CONNECTED;
+
 	return err;
 }
 
diff --git a/xen/include/public/io/console.h b/xen/include/public/io/console.h
index 4509b4b689..b9ebfaff3f 100644
--- a/xen/include/public/io/console.h
+++ b/xen/include/public/io/console.h
@@ -19,6 +19,19 @@ struct xencons_interface {
     char out[2048];
     XENCONS_RING_IDX in_cons, in_prod;
     XENCONS_RING_IDX out_cons, out_prod;
+/*
+ * Flag values signaling from backend to frontend whether the console is
+ * connected.  i.e. Whether it will be serviced and emptied.
+ *
+ * The flag starts as disconnected.
+ */
+#define XENCONSOLE_DISCONNECTED 1
+/*
+ * The flag is set to connected when the backend connects and the console
+ * will be serviced.
+ */
+#define XENCONSOLE_CONNECTED    0
+    uint8_t connection;
 };
 
 #ifdef XEN_WANT_FLEX_CONSOLE_RING
-- 
2.50.1



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From: Tamas K Lengyel 
Date: Fri, 22 Aug 2025 19:01:35 -0400
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Subject: Re: [PATCH v12 1/6] altp2m: Drop p2m_altp2m_check() stubs on non-x86,
 move prototype, and guard uses
To: =?UTF-8?Q?Petr_Bene=C5=A1?= 
Cc: xen-devel@lists.xenproject.org, 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Volodymyr Babchuk , Andrew Cooper , 
	Anthony PERARD , Jan Beulich , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Shawn Anastasio , 
	Alistair Francis , Bob Eshleman , 
	Connor Davis , Oleksii Kurochko , 
	Alexandru Isaila , Petre Pircalabu 
Content-Type: text/plain; charset="UTF-8"
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On Thu, Jul 31, 2025 at 5:28=E2=80=AFAM Petr Bene=C5=A1 =
 wrote:
>
> From: Petr Bene=C5=A1 
>
> Remove the no=E2=80=91op stubs from the ARM, PPC, and RISC=E2=80=91V p2m =
headers and stop
> providing a stub in arch/x86/include/asm/p2m.h.
>
> Declare p2m_altp2m_check() in xen/include/xen/p2m-common.h and gate all
> call sites with CONFIG_ALTP2M:
>  - wrap the fast_single_step block in hvm/monitor.c with #ifdef CONFIG_AL=
TP2M
>    (IS_ENABLED(CONFIG_ALTP2M) is not used here, because in the subsequent=
 commit
>    hvm_vcpu::fast_single_step will be guarded by CONFIG_ALTP2M)
>  - make the vm_event.c path conditional via IS_ENABLED(CONFIG_ALTP2M)
>
> No functional change intended: on builds without ALTP2M the calls are
> compiled out; on builds with ALTP2M behavior is unchanged.
>
> Signed-off-by: Petr Bene=C5=A1 
> Reviewed-by: Jan Beulich 

vm_event/monitor bits:
Acked-by: Tamas K Lengyel 


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In-Reply-To: 
From: Tamas K Lengyel 
Date: Fri, 22 Aug 2025 19:02:56 -0400
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Message-ID: 
Subject: Re: [PATCH v12 2/6] x86/altp2m: Wrap altp2m-specific code in #ifdef CONFIG_ALTP2M
To: Jan Beulich 
Cc: =?UTF-8?Q?Petr_Bene=C5=A1?= , 
	Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Alexandru Isaila , Petre Pircalabu , 
	xen-devel@lists.xenproject.org
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On Thu, Jul 31, 2025 at 5:33=E2=80=AFAM Jan Beulich  wro=
te:
>
> On 31.07.2025 11:27, Petr Bene=C5=A1 wrote:
> > From: Petr Bene=C5=A1 
> >
> > This change consistently guards all altp2m-related functionality
> > behind #ifdef CONFIG_ALTP2M, so that code and data structures related
> > to alternate p2m views are only included when the feature is enabled.
> >
> > Apart from that:
> > - hvmemul_vmfunc() returns X86EMUL_UNHANDLEABLE when altp2m is disabled=
.
> > - do_altp2m_op() returns EOPNOTSUPP when altp2m is disabled.
> > - struct hvm_vcpu, arch_domain, and hvm_function_table only define altp=
2m
> >   fields when the feature is enabled.
> > - Moved several declarations under #ifdef CONFIG_ALTP2M in p2m.h to avo=
id
> >   polluting builds that don't require the feature.
> >
> > Signed-off-by: Petr Bene=C5=A1 
>
> Reviewed-by: Jan Beulich 
>

For mem_access bits:
Acked-by: Tamas K Lengyel 


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Subject: Re: [PATCH v12 3/6] xen: Make the maximum number of altp2m views
 configurable for x86
To: =?UTF-8?Q?Petr_Bene=C5=A1?= 
Cc: xen-devel@lists.xenproject.org, 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Volodymyr Babchuk , Andrew Cooper , 
	Anthony PERARD , Jan Beulich , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Alexandru Isaila , Petre Pircalabu 
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On Thu, Jul 31, 2025 at 5:28=E2=80=AFAM Petr Bene=C5=A1 =
 wrote:
>
> From: Petr Bene=C5=A1 
>
> This commit introduces the ability to configure the maximum number of alt=
p2m
> views for the domain during its creation. Previously, the limits were har=
dcoded
> to a maximum of 10. This change allows for greater flexibility in environ=
ments
> that require more or fewer altp2m views.
>
> The maximum configurable limit for nr_altp2m on x86 is now set to
> MAX_NR_ALTP2M (which currently holds the MAX_EPTP value - 512). This cap =
is
> linked to the architectural limit of the EPTP-switching VMFUNC, which sup=
ports
> up to 512 entries. Despite there being no inherent need for limiting nr_a=
ltp2m
> in scenarios not utilizing VMFUNC, decoupling these components would nece=
ssitate
> substantial code changes.
>
> xen_domctl_createdomain::altp2m is extended for a new field `nr`, that wi=
ll
> configure this limit for a domain. Additionally, previous altp2m.opts val=
ue
> has been reduced from uint32_t to uint16_t so that both of these fields o=
ccupy
> as little space as possible.
>
> Accesses to the altp2m_p2m array are modified to respect the new nr_altp2=
m
> value. Accesses to the altp2m_(visible_)eptp arrays are unmodified, since
> these arrays always have fixed size of MAX_EPTP.
>
> Additional sanitization is introduced in the x86/arch_sanitise_domain_con=
fig
> to fix the altp2m.nr value to 10 if it is previously set to 0. This behav=
ior
> is only temporary and immediately removed in the upcoming commit (which w=
ill
> disallow creating a domain with enabled altp2m with zero nr_altp2m).
>
> The reason for this temporary workaround is to retain the legacy behavior
> until the feature is fully activated in libxl.
>
> Also, arm/arch_sanitise_domain_config is extended to not allow requesting
> non-zero altp2ms.
>
> Signed-off-by: Petr Bene=C5=A1 
> Acked-by: Jan Beulich 

For mem_access/mem_sharing bits:
Acked-by: Tamas K Lengyel 


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To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mykola
 Kvach , Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Andrew Cooper
	, Anthony PERARD , Jan
 Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: Re: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
Thread-Topic: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
Thread-Index: AQHcEB0Xn+shUJCmLkyEBRYwomJTeg==
Date: Fri, 22 Aug 2025 23:30:19 +0000
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Hi Mykola,

Mykola Kvach  writes:

> From: Mykola Kvach 
>
> This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPSCI
> (virtual PSCI) interface, allowing guests to request suspend via the PSCI
> v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).
>
> The implementation:
> - Adds SYSTEM_SUSPEND function IDs to PSCI definitions
> - Implements trapping and handling of SYSTEM_SUSPEND in vPSCI
> - Allows only non-hardware domains to invoke SYSTEM_SUSPEND; for the
>   hardware domain, PSCI_NOT_SUPPORTED is returned to avoid halting the
>   system in hwdom_shutdown() called from domain_shutdown
> - Ensures all secondary VCPUs of the calling domain are offline before
>   allowing suspend due to PSCI spec
>
> GIC and virtual timer context must be saved when the domain suspends.
> This is done by moving the respective code in ctxt_switch_from
> before the return that happens if the domain suspended.
>
> domain_resume_nopause() is introduced to allow resuming a domain from
> SYSTEM_SUSPEND without pausing it first. This avoids problematic
> domain_pause() calls when resuming from suspend on Arm, particularly
> in error paths. The function is only used on Arm; other architectures
> continue to use the original domain_resume().
>
> Usage:
>
> For Linux-based guests, suspend can be initiated with:
>     echo mem > /sys/power/state
> or via:
>     systemctl suspend
>
> Resuming the guest is performed from control domain using:
>       xl resume 
>
> Signed-off-by: Mykola Kvach 
> ---
> Changes in V9:
> - no functional changes
> - cosmetic chnages after review
> - enhance commit message and add extra comment to the code after review
>
> Changes in V8:
> - GIC and virtual timer context must be saved when the domain suspends
> - rework locking
> - minor changes after code review
>
> Changes in V7:
> - add proper locking
> - minor changes after code review
>
> Changes in V6:
> - skip execution of ctxt_switch_from for vcpu that is in paused domain
> - add implementation of domain_resume without domain_pause
> - add helper function to determine if vcpu is suspended or not
> - ignore upper 32 bits of argument values when the domain is 64-bit
>   and calls the SMC32 SYSTEM_SUSPEND function
> - cosmetic changes after review
>
> Changes in V5:
> - don't use standby mode, restore execution in a provided by guest point
> - move checking that all CPUs, except current one, are offline to after
>   pausing the vCPUs
> - provide ret status from arch_domain_shutdown and handle it in
>   domain_shutdown
> - adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI functio=
ns
>
> Changes in V4:
> Dropped all changes related to watchdog, domain is marked as shutting
> down in domain_shutdown and watchdog timeout handler won't trigger
> because of it.
>
> Previous versions included code to manage Xen watchdog timers during susp=
end,
> but this was removed. When a guest OS starts the Xen watchdog (either via=
 the
> kernel driver or xenwatchdogd), it is responsible for managing that state
> across suspend/resume. On Linux, the Xen kernel driver properly stops the
> watchdog during suspend. However, when xenwatchdogd is used instead, susp=
end
> handling is incomplete, potentially leading to watchdog-triggered resets =
on
> resume. Xen leaves watchdog handling to the guest OS and its services.
>
> Dropped all changes related to VCPU context, because instead domain_shutd=
own
> is used, so we don't need any extra changes for suspending domain.
>
> Changes in V3:
> Dropped all domain flags and related code (which touched common functions=
 like
> vcpu_unblock), keeping only the necessary changes for Xen suspend/resume,=
 i.e.
> suspend/resume is now fully supported only for the hardware domain.
> Proper support for domU suspend/resume will be added in a future patch.
> This patch does not yet include VCPU context reset or domain context
> restoration in VCPU.
> ---
>  xen/arch/arm/domain.c                 |  17 +++--
>  xen/arch/arm/include/asm/perfc_defn.h |   1 +
>  xen/arch/arm/include/asm/psci.h       |   2 +
>  xen/arch/arm/include/asm/vpsci.h      |   2 +-
>  xen/arch/arm/vpsci.c                  | 101 ++++++++++++++++++++++----
>  xen/common/domain.c                   |  31 ++++++--
>  xen/include/xen/sched.h               |   6 ++
>  7 files changed, 131 insertions(+), 29 deletions(-)
>
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index 310c578909..9e9649c4e2 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -90,6 +90,16 @@ static void ctxt_switch_from(struct vcpu *p)
>      if ( is_idle_vcpu(p) )
>          return;
> =20
> +    /* Arch timer */
> +    p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1);
> +    virt_timer_save(p);
> +
> +    /* VGIC */
> +    gic_save_state(p);
> +

I'd like to see comment here on why we don't need to do rest of the
ctx save code. I saw that this is described in the commit message, but
comment there will be very helpful for future contributors.

> +    if ( test_bit(_VPF_suspended, &p->pause_flags) )
> +        return;
> +
>      p2m_save_state(p);
> =20
>      /* CP 15 */
> @@ -106,10 +116,6 @@ static void ctxt_switch_from(struct vcpu *p)
>      p->arch.tpidrro_el0 =3D READ_SYSREG(TPIDRRO_EL0);
>      p->arch.tpidr_el1 =3D READ_SYSREG(TPIDR_EL1);
> =20
> -    /* Arch timer */
> -    p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1);
> -    virt_timer_save(p);
> -
>      if ( is_32bit_domain(p->domain) && cpu_has_thumbee )
>      {
>          p->arch.teecr =3D READ_SYSREG(TEECR32_EL1);
> @@ -158,9 +164,6 @@ static void ctxt_switch_from(struct vcpu *p)
> =20
>      /* XXX MPU */
> =20
> -    /* VGIC */
> -    gic_save_state(p);
> -
>      isb();
>  }
> =20
> diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/include=
/asm/perfc_defn.h
> index effd25b69e..8dfcac7e3b 100644
> --- a/xen/arch/arm/include/asm/perfc_defn.h
> +++ b/xen/arch/arm/include/asm/perfc_defn.h
> @@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system_r=
eset")
>  PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
>  PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
>  PERFCOUNTER(vpsci_features,            "vpsci: features")
> +PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
> =20
>  PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
> =20
> diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/p=
sci.h
> index 4780972621..48a93e6b79 100644
> --- a/xen/arch/arm/include/asm/psci.h
> +++ b/xen/arch/arm/include/asm/psci.h
> @@ -47,10 +47,12 @@ void call_psci_system_reset(void);
>  #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
>  #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
>  #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
> +#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
> =20
>  #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
>  #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
>  #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
> +#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
> =20
>  /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
>  #define PSCI_0_2_AFFINITY_LEVEL_ON      0
> diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/asm/=
vpsci.h
> index 0cca5e6830..69d40f9d7f 100644
> --- a/xen/arch/arm/include/asm/vpsci.h
> +++ b/xen/arch/arm/include/asm/vpsci.h
> @@ -23,7 +23,7 @@
>  #include 
> =20
>  /* Number of function implemented by virtual PSCI (only 0.2 or later) */
> -#define VPSCI_NR_FUNCS  12
> +#define VPSCI_NR_FUNCS  14
> =20
>  /* Functions handle PSCI calls from the guests */
>  bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
> diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
> index 7ba9ccd94b..67d369a8a2 100644
> --- a/xen/arch/arm/vpsci.c
> +++ b/xen/arch/arm/vpsci.c
> @@ -10,28 +10,18 @@
> =20
>  #include 
> =20
> -static int do_common_cpu_on(register_t target_cpu, register_t entry_poin=
t,
> -                            register_t context_id)
> +static int do_setup_vcpu_ctx(struct vcpu *v, register_t entry_point,
> +                      register_t context_id)
>  {
> -    struct vcpu *v;
>      struct domain *d =3D current->domain;
>      struct vcpu_guest_context *ctxt;
>      int rc;
>      bool is_thumb =3D entry_point & 1;
> -    register_t vcpuid;
> -
> -    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> -
> -    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> -        return PSCI_INVALID_PARAMETERS;
> =20
>      /* THUMB set is not allowed with 64-bit domain */
>      if ( is_64bit_domain(d) && is_thumb )
>          return PSCI_INVALID_ADDRESS;
> =20
> -    if ( !test_bit(_VPF_down, &v->pause_flags) )
> -        return PSCI_ALREADY_ON;
> -
>      if ( (ctxt =3D alloc_vcpu_guest_context()) =3D=3D NULL )
>          return PSCI_DENIED;
> =20
> @@ -78,11 +68,32 @@ static int do_common_cpu_on(register_t target_cpu, re=
gister_t entry_point,
>      if ( rc < 0 )
>          return PSCI_DENIED;
> =20
> -    vcpu_wake(v);
> -
>      return PSCI_SUCCESS;
>  }
> =20
> +static int do_common_cpu_on(register_t target_cpu, register_t entry_poin=
t,
> +                            register_t context_id)
> +{
> +    int rc;
> +    struct vcpu *v;
> +    struct domain *d =3D current->domain;
> +    register_t vcpuid;
> +
> +    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> +
> +    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> +        return PSCI_INVALID_PARAMETERS;
> +
> +    if ( !test_bit(_VPF_down, &v->pause_flags) )
> +        return PSCI_ALREADY_ON;
> +
> +    rc =3D do_setup_vcpu_ctx(v, entry_point, context_id);
> +    if ( rc =3D=3D PSCI_SUCCESS )
> +        vcpu_wake(v);
> +
> +    return rc;
> +}
> +
>  static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
>  {
>      int32_t ret;
> @@ -197,6 +208,48 @@ static void do_psci_0_2_system_reset(void)
>      domain_shutdown(d,SHUTDOWN_reboot);
>  }
> =20
> +static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t =
cid)
> +{
> +    int32_t rc;
> +    struct vcpu *v;
> +    struct domain *d =3D current->domain;
> +
> +    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> +    if ( is_hardware_domain(d) )
> +        return PSCI_NOT_SUPPORTED;
> +
> +    /* Ensure that all CPUs other than the calling one are offline */
> +    domain_lock(d);
> +    for_each_vcpu ( d, v )
> +    {
> +        if ( v !=3D current && is_vcpu_online(v) )
> +        {
> +            domain_unlock(d);
> +            return PSCI_DENIED;
> +        }
> +    }
> +    domain_unlock(d);
> +
> +    rc =3D domain_shutdown(d, SHUTDOWN_suspend);
> +    if ( rc )
> +        return PSCI_DENIED;
> +
> +    rc =3D do_setup_vcpu_ctx(current, epoint, cid);
> +    if ( rc !=3D PSCI_SUCCESS )
> +    {
> +        domain_resume_nopause(d);
> +        return rc;
> +    }
> +
> +    set_bit(_VPF_suspended, ¤t->pause_flags);
> +
> +    dprintk(XENLOG_DEBUG,
> +            "Dom %u: SYSTEM_SUSPEND requested, epoint=3D%#lx, cid=3D%#lx=
\n",
> +            d->domain_id, epoint, cid);
> +
> +    return rc;
> +}
> +
>  static int32_t do_psci_1_0_features(uint32_t psci_func_id)
>  {
>      /* /!\ Ordered by function ID and not name */
> @@ -214,6 +267,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_fun=
c_id)
>      case PSCI_0_2_FN32_SYSTEM_OFF:
>      case PSCI_0_2_FN32_SYSTEM_RESET:
>      case PSCI_1_0_FN32_PSCI_FEATURES:
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
>      case ARM_SMCCC_VERSION_FID:
>          return 0;
>      default:
> @@ -344,6 +399,24 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, u=
int32_t fid)
>          return true;
>      }
> =20
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> +    {
> +        register_t epoint =3D PSCI_ARG(regs, 1);
> +        register_t cid =3D PSCI_ARG(regs, 2);
> +
> +        if ( is_64bit_domain(current->domain) &&
> +             fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND )
> +        {
> +            epoint &=3D GENMASK(31, 0);
> +            cid &=3D GENMASK(31, 0);
> +        }
> +
> +        perfc_incr(vpsci_system_suspend);
> +        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
> +        return true;
> +    }
> +
>      default:
>          return false;
>      }
> diff --git a/xen/common/domain.c b/xen/common/domain.c
> index 5241a1629e..624c3e2c27 100644
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -1343,16 +1343,13 @@ int domain_shutdown(struct domain *d, u8 reason)
>      return 0;
>  }
> =20
> -void domain_resume(struct domain *d)
> +#ifndef CONFIG_ARM
> +static
> +#endif
> +void domain_resume_nopause(struct domain *d)

It took me some time to understand that this function makes assumption
that domain is already paused. As it behaves like *_unlocked()
functions, maybe it is better to call it something like domain_resume_pause=
d() ?

>  {
>      struct vcpu *v;
> =20
> -    /*
> -     * Some code paths assume that shutdown status does not get reset un=
der
> -     * their feet (e.g., some assertions make this assumption).
> -     */
> -    domain_pause(d);
> -
>      spin_lock(&d->shutdown_lock);
> =20
>      d->is_shutting_down =3D d->is_shut_down =3D 0;
> @@ -1360,13 +1357,33 @@ void domain_resume(struct domain *d)
> =20
>      for_each_vcpu ( d, v )
>      {
> +        /*
> +         * No need to conditionally clear _VPF_suspended here:
> +         * - This bit is only set on Arm64, and only after a successful =
suspend.
> +         * - domain_resume_nopause() may also be called from paths other=
 than
> +         *   the suspend/resume flow, such as "soft-reset" actions (e.g.=
,
> +         *   on_poweroff), as part of the Xenstore control/shutdown prot=
ocol.
> +         *   These require guest acknowledgement to complete the operati=
on.
> +         * So clearing the bit unconditionally is safe.
> +         */
> +        clear_bit(_VPF_suspended, &v->pause_flags);
> +
>          if ( v->paused_for_shutdown )
>              vcpu_unpause(v);
>          v->paused_for_shutdown =3D 0;
>      }
> =20
>      spin_unlock(&d->shutdown_lock);
> +}
> =20
> +void domain_resume(struct domain *d)
> +{
> +    /*
> +     * Some code paths assume that shutdown status does not get reset un=
der
> +     * their feet (e.g., some assertions make this assumption).
> +     */
> +    domain_pause(d);
> +    domain_resume_nopause(d);
>      domain_unpause(d);
>  }
> =20
> diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
> index fd5c9f9333..c1848d8ea6 100644
> --- a/xen/include/xen/sched.h
> +++ b/xen/include/xen/sched.h
> @@ -814,6 +814,9 @@ void domain_destroy(struct domain *d);
>  int domain_kill(struct domain *d);
>  int domain_shutdown(struct domain *d, u8 reason);
>  void domain_resume(struct domain *d);
> +#ifdef CONFIG_ARM
> +void domain_resume_nopause(struct domain *d);
> +#endif

Probably I need comment from other reviewers here. Do we really need to
make this ARM-specific? I understand that right now it will be used only
by ARM, but still... Also, I am not big fan of that

> +#ifndef CONFIG_ARM
> +static
> +#endif

in the function definition.


--=20
WBR, Volodymyr=


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Date: Fri, 22 Aug 2025 16:31:37 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Jan Beulich 
cc: Mykyta Poturai , 
    Luca Fancellu , 
    Stefano Stabellini , Julien Grall , 
    Bertrand Marquis , 
    Michal Orzel , 
    Volodymyr Babchuk , 
    Andrew Cooper , 
    Anthony PERARD , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    "Daniel P. Smith" , 
    "xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH v2 3/3] xen/pci: add discovered PCI device at boot
In-Reply-To: <2ba28d38-3251-492e-b7d8-a626dcaa1035@suse.com>
Message-ID: 
References:   <26bad9fb-3c4b-4423-a443-3406d07d56e0@suse.com> 
 <2ba28d38-3251-492e-b7d8-a626dcaa1035@suse.com>
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On Fri, 22 Aug 2025, Jan Beulich wrote:
> On 22.08.2025 10:03, Mykyta Poturai wrote:
> > On 21.08.25 12:08, Jan Beulich wrote:
> >> On 20.08.2025 14:28, Mykyta Poturai wrote:
> >>> From: Luca Fancellu 
> >>>
> >>> In dom0less mode, there is no dom0 that can call PCI physdev ops to
> >>> register PCI devices to iommu, so it needs to be done by Xen.
> >>> pci_add_device requires some default domain, we don't have hwdom, and
> >>> the guests are not yet created during the PCI init phase, so use dom_io
> >>> as a temporary sentinel before devices are assigned to their target
> >>> domains.
> >>>
> >>> Rename setup_hwdom_pci_devices to setup_pci_devices and add dom0less
> >>> handling to it.
> >>>
> >>> In pci_add_device there is a call to xsm that doesn't consider the
> >>> requester of the function to be Xen itself, so add a check to skip
> >>> the call if the owner domain is dom_io, since it means the call is
> >>> coming directly from Xen.
> >>>
> >>> Signed-off-by: Luca Fancellu 
> >>> Signed-off-by: Mykyta Poturai 
> >>> ---
> >>> (cherry picked from commit eff51e50021b75f5a50533f7de681b2ce044f5bd from
> >>>   the downstream branch poc/pci-passthrough from
> >>>   https://gitlab.com/xen-project/people/bmarquis/xen-arm-poc.git
> >>>
> >>> v1->v2:
> >>> * integrate add_discovered_pci_devices into existing routines
> >>> * better explain the need for dom_io
> >>
> >> What I continue to miss is an explanation of why devices can't go to their
> >> ultimate "destination" domain right away (once those have been created),
> >> i.e. why the dom_io intermediary is necessary in the first place.
> > 
> > I've done some testing and indeed everything seems to work if we call 
> > pci_add_device directly during domain construction instead of 
> > reassigning them. Do you think this would be a better approach?
> 
> I think so, yes, but first and foremost you'll need Arm maintainer buyoff
> on either approach (or yet another one).

I am OK with that in principle


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mirela
 Simonovic , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Saeed
 Nowshadi , Mykyta Poturai
	, Mykola Kvach 
Subject: Re: [PATCH v5 02/12] xen/arm: gic-v2: Implement GIC suspend/resume
 functions
Thread-Topic: [PATCH v5 02/12] xen/arm: gic-v2: Implement GIC suspend/resume
 functions
Thread-Index: AQHcCwFbbjjfZY2kcU62fZWRWGuXGg==
Date: Sat, 23 Aug 2025 00:01:16 +0000
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Hi Mykola,

Mykola Kvach  writes:

> From: Mirela Simonovic 
>
> System suspend may lead to a state where GIC would be powered down.
> Therefore, Xen should save/restore the context of GIC on suspend/resume.
>
> Note that the context consists of states of registers which are
> controlled by the hypervisor. Other GIC registers which are accessible
> by guests are saved/restored on context switch.
>
> Tested on Xilinx Ultrascale+ MPSoC with (and without) powering down
> the GIC.

I think you can drop this sentence, as I am pretty sure this patch
wasn't tested on Ultrascale+ for last five(?) years..

>
> Signed-off-by: Mirela Simonovic 
> Signed-off-by: Saeed Nowshadi 
> Signed-off-by: Mykyta Poturai 
> Signed-off-by: Mykola Kvach 
> ---
> Changes in v4:
>   - Add error logging for allocation failures
>
> Changes in v3:
>   - Drop asserts and return error codes instead.
>   - Wrap code with CONFIG_SYSTEM_SUSPEND.
>
> Changes in v2:
>   - Minor fixes after review.
> ---
>  xen/arch/arm/gic-v2.c          | 154 +++++++++++++++++++++++++++++++++
>  xen/arch/arm/gic.c             |  29 +++++++
>  xen/arch/arm/include/asm/gic.h |  12 +++
>  3 files changed, 195 insertions(+)
>
> diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
> index b23e72a3d0..dce8f5e924 100644
> --- a/xen/arch/arm/gic-v2.c
> +++ b/xen/arch/arm/gic-v2.c
> @@ -1098,6 +1098,151 @@ static int gicv2_iomem_deny_access(struct domain =
*d)
>      return iomem_deny_access(d, mfn, mfn + nr);
>  }
> =20
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +
> +/* GICv2 registers to be saved/restored on system suspend/resume */
> +struct gicv2_context {
> +    /* GICC context */
> +    uint32_t gicc_ctlr;
> +    uint32_t gicc_pmr;
> +    uint32_t gicc_bpr;
> +    /* GICD context */
> +    uint32_t gicd_ctlr;
> +    uint32_t *gicd_isenabler;
> +    uint32_t *gicd_isactiver;
> +    uint32_t *gicd_ipriorityr;
> +    uint32_t *gicd_itargetsr;
> +    uint32_t *gicd_icfgr;
> +};
> +
> +static struct gicv2_context gicv2_context;
> +
> +static int gicv2_suspend(void)
> +{
> +    unsigned int i;
> +
> +    if ( !gicv2_context.gicd_isenabler )
> +    {
> +        dprintk(XENLOG_WARNING, "%s:%d: GICv2 suspend context not alloca=
ted!\n",
> +            __func__, __LINE__);

Should this be ASSERT(gicv2_context.gicd_isenabler) ? Or do we expect
that this can happen during normal runtime?

Also, you don't need to print __func__ and __LINE__ as dprintk does this
for you already:

#define dprintk(lvl, fmt, args...) \
    printk(lvl "%s:%d: " fmt, __FILE__, __LINE__, ## args)



> +        return -ENOMEM;
> +    }
> +
> +    /* Save GICC configuration */
> +    gicv2_context.gicc_ctlr =3D readl_gicc(GICC_CTLR);
> +    gicv2_context.gicc_pmr =3D readl_gicc(GICC_PMR);
> +    gicv2_context.gicc_bpr =3D readl_gicc(GICC_BPR);
> +
> +    /* Save GICD configuration */
> +    gicv2_context.gicd_ctlr =3D readl_gicd(GICD_CTLR);
> +
> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ )
> +        gicv2_context.gicd_isenabler[i] =3D readl_gicd(GICD_ISENABLER + =
i * 4);
> +
> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ )
> +        gicv2_context.gicd_isactiver[i] =3D readl_gicd(GICD_ISACTIVER + =
i * 4);
> +

I think you can merge this two loops

> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
> +        gicv2_context.gicd_ipriorityr[i] =3D readl_gicd(GICD_IPRIORITYR =
+ i * 4);
> +
> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
> +        gicv2_context.gicd_itargetsr[i] =3D readl_gicd(GICD_ITARGETSR + =
i * 4);
> +

And this two as well

> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 16); i++ )
> +        gicv2_context.gicd_icfgr[i] =3D readl_gicd(GICD_ICFGR + i * 4);
> +
> +    return 0;
> +}
> +
> +static void gicv2_resume(void)
> +{
> +    unsigned int i;
> +
> +    if ( !gicv2_context.gicd_isenabler )
> +    {
> +        dprintk(XENLOG_WARNING, "%s:%d: GICv2 suspend context not alloca=
ted!\n",
> +            __func__, __LINE__);

the same comment as for gicv2_suspend(). Actually, we should not reach
here in any case.

> +        return;
> +    }
> +
> +    gicv2_cpu_disable();
> +    /* Disable distributor */
> +    writel_gicd(0, GICD_CTLR);
> +
> +    /* Restore GICD configuration */
> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ ) {
> +        writel_gicd(0xffffffff, GICD_ICENABLER + i * 4);
> +        writel_gicd(gicv2_context.gicd_isenabler[i], GICD_ISENABLER + i =
* 4);
> +    }
> +
> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ ) {
> +        writel_gicd(0xffffffff, GICD_ICACTIVER + i * 4);
> +        writel_gicd(gicv2_context.gicd_isactiver[i], GICD_ISACTIVER + i =
* 4);
> +    }
> +
> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
> +        writel_gicd(gicv2_context.gicd_ipriorityr[i], GICD_IPRIORITYR + =
i * 4);
> +
> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
> +        writel_gicd(gicv2_context.gicd_itargetsr[i], GICD_ITARGETSR + i =
* 4);
> +
> +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 16); i++ )
> +        writel_gicd(gicv2_context.gicd_icfgr[i], GICD_ICFGR + i * 4);
> +
> +    /* Make sure all registers are restored and enable distributor */
> +    writel_gicd(gicv2_context.gicd_ctlr | GICD_CTL_ENABLE, GICD_CTLR);
> +
> +    /* Restore GIC CPU interface configuration */
> +    writel_gicc(gicv2_context.gicc_pmr, GICC_PMR);
> +    writel_gicc(gicv2_context.gicc_bpr, GICC_BPR);
> +
> +    /* Enable GIC CPU interface */
> +    writel_gicc(gicv2_context.gicc_ctlr | GICC_CTL_ENABLE | GICC_CTL_EOI=
,
> +                GICC_CTLR);
> +}
> +
> +static void gicv2_alloc_context(struct gicv2_context *gc)
> +{
> +    uint32_t n =3D gicv2_info.nr_lines;
> +
> +    gc->gicd_isenabler =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 32));
> +    if ( !gc->gicd_isenabler )
> +        goto err_free;
> +
> +    gc->gicd_isactiver =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 32));
> +    if ( !gc->gicd_isactiver )
> +        goto err_free;
> +
> +    gc->gicd_itargetsr =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 4));
> +    if ( !gc->gicd_itargetsr )
> +        goto err_free;
> +
> +    gc->gicd_ipriorityr =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 4));
> +    if ( !gc->gicd_ipriorityr )
> +        goto err_free;
> +
> +    gc->gicd_icfgr =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 16));
> +    if ( !gc->gicd_icfgr )
> +        goto err_free;
> +
> +    return;
> +
> + err_free:
> +    dprintk(XENLOG_ERR,
> +            "%s:%d: failed to allocate memory for GICv2 suspend context\=
n",
> +            __func__, __LINE__);

Okay, this partially answers to my previous question about memory
allocation. So it is possible to have active system without space for
GIC context... But this basically renders system un-suspendable. I think
this warrants non-debug print to warn user that suspend will be not
available.=20

[...]

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mykola
 Kvach , Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel 
Subject: Re: [PATCH v5 03/12] xen/arm: gic-v3: Implement GICv3 suspend/resume
 functions
Thread-Topic: [PATCH v5 03/12] xen/arm: gic-v3: Implement GICv3 suspend/resume
 functions
Thread-Index: AQHcCwFbPuGIvhJksU2gYmOTRYiYRQ==
Date: Sat, 23 Aug 2025 00:20:55 +0000
Message-ID: <87zfbqanx5.fsf@epam.com>
References: 
	<451b8a0527a6193b6687e1c85bd254b4dfda142d.1754943874.git.mykola_kvach@epam.com>
In-Reply-To:
 <451b8a0527a6193b6687e1c85bd254b4dfda142d.1754943874.git.mykola_kvach@epam.com>
	(Mykola Kvach's message of "Mon, 11 Aug 2025 23:47:59 +0300")
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Hi,

Mykola Kvach  writes:

> From: Mykola Kvach 
>
> System suspend may lead to a state where GIC would be powered down.
> Therefore, Xen should save/restore the context of GIC on suspend/resume.
>
> Note that the context consists of states of registers which are
> controlled by the hypervisor. Other GIC registers which are accessible
> by guests are saved/restored on context switch.
>
> Signed-off-by: Mykola Kvach 
> ---
>  xen/arch/arm/gic-v3.c | 233 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 233 insertions(+)
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index cd3e1acf79..a9b65ff5d4 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -1776,6 +1776,231 @@ static bool gic_dist_supports_lpis(void)
>      return (readl_relaxed(GICD + GICD_TYPER) & GICD_TYPE_LPIS);
>  }
> =20
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +
> +/* GICv3 registers to be saved/restored on system suspend/resume */
> +struct gicv3_ctx {
> +    struct dist_ctx {
> +        uint32_t ctlr;
> +        /*
> +         * This struct represent block of 32 IRQs
> +         * TODO: store extended SPI configuration (GICv3.1+)
> +         */
> +        struct irq_regs {
> +            uint32_t icfgr[2];
> +            uint32_t ipriorityr[8];
> +            uint64_t irouter[32];
> +            uint32_t isactiver;
> +            uint32_t isenabler;
> +        } *irqs;
> +    } dist;
> +
> +    /* have only one rdist structure for last running CPU during suspend=
 */
> +    struct redist_ctx {
> +        uint32_t ctlr;
> +        /* TODO: handle case when we have more than 16 PPIs (GICv3.1+) *=
/
> +        uint32_t icfgr[2];
> +        uint32_t igroupr;
> +        uint32_t ipriorityr[8];
> +        uint32_t isactiver;
> +        uint32_t isenabler;
> +    } rdist;
> +
> +    struct cpu_ctx {
> +        uint32_t ctlr;
> +        uint32_t pmr;
> +        uint32_t bpr;
> +        uint32_t sre_el2;
> +        uint32_t grpen;
> +    } cpu;
> +};
> +
> +static struct gicv3_ctx gicv3_ctx;
> +
> +static void __init gicv3_alloc_context(void)
> +{
> +    uint32_t blocks =3D DIV_ROUND_UP(gicv3_info.nr_lines, 32);
> +
> +    if ( gicv3_its_host_has_its() )
> +        return;

I think this needs a comment at least. And/or printk() message. Because
for it is unclear why we are doing nothing if host has ITS

> +
> +    /* according to spec it is possible don't have SPIs */
> +    if ( blocks =3D=3D 1 )
> +        return;
> +
> +    gicv3_ctx.dist.irqs =3D xzalloc_array(typeof(*gicv3_ctx.dist.irqs), =
blocks - 1);
> +    if ( !gicv3_ctx.dist.irqs )
> +        dprintk(XENLOG_ERR,
> +                "%s:%d: failed to allocate memory for GICv3 suspend cont=
ext\n",
> +                __func__, __LINE__);

dprintk() already prints function and line. Here and everywhere in this
patch.

> +}
> +
> +static void gicv3_disable_redist(void)
> +{
> +    void __iomem* waker =3D GICD_RDIST_BASE + GICR_WAKER;
> +
> +    writel_relaxed(readl_relaxed(waker) | GICR_WAKER_ProcessorSleep, wak=
er);
> +    while ( (readl_relaxed(waker) & GICR_WAKER_ChildrenAsleep) =3D=3D 0 =
);
> +}
> +
> +static int gicv3_suspend(void)
> +{
> +    unsigned int i;
> +    void __iomem *base;
> +    typeof(gicv3_ctx.rdist)* rdist =3D &gicv3_ctx.rdist;
> +
> +    /* TODO: implement support for ITS */
> +    if ( gicv3_its_host_has_its() )
> +        return -EOPNOTSUPP;
> +
> +    if ( !gicv3_ctx.dist.irqs && gicv3_info.nr_lines > NR_GIC_LOCAL_IRQS=
 )
> +    {
> +        dprintk(XENLOG_WARNING,
> +                "%s:%d: GICv3 suspend context is not allocated!\n",
> +                __func__, __LINE__);
> +        return -ENOMEM;
> +    }
> +
> +    gicv3_save_state(current);
> +
> +    /* Save GICC configuration */
> +    gicv3_ctx.cpu.ctlr     =3D READ_SYSREG(ICC_CTLR_EL1);
> +    gicv3_ctx.cpu.pmr      =3D READ_SYSREG(ICC_PMR_EL1);
> +    gicv3_ctx.cpu.bpr      =3D READ_SYSREG(ICC_BPR1_EL1);
> +    gicv3_ctx.cpu.sre_el2  =3D READ_SYSREG(ICC_SRE_EL2);
> +    gicv3_ctx.cpu.grpen    =3D READ_SYSREG(ICC_IGRPEN1_EL1);
> +
> +    gicv3_disable_interface();
> +    gicv3_disable_redist();
> +
> +    /* Save GICR configuration */
> +    gicv3_redist_wait_for_rwp();
> +
> +    base =3D GICD_RDIST_SGI_BASE;
> +
> +    rdist->ctlr =3D readl_relaxed(base + GICR_CTLR);
> +
> +    /* Set priority on PPI and SGI interrupts */

Probably you wanted to say "Save priority..."

> +    for (i =3D 0; i < NR_GIC_LOCAL_IRQS / 4; i +=3D 4)
> +        rdist->ipriorityr[i] =3D readl_relaxed(base + GICR_IPRIORITYR0 +=
 4 * i);

Is this correct? You are writing to every 4th rdist->ipriorityr and
reading every 4th GICR_IPRIORITYR

> +
> +    rdist->isactiver =3D readl_relaxed(base + GICR_ISACTIVER0);
> +    rdist->isenabler =3D readl_relaxed(base + GICR_ISENABLER0);
> +    rdist->igroupr   =3D readl_relaxed(base + GICR_IGROUPR0);
> +    rdist->icfgr[0]  =3D readl_relaxed(base + GICR_ICFGR0);
> +    rdist->icfgr[1]  =3D readl_relaxed(base + GICR_ICFGR1);
> +
> +    /* Save GICD configuration */
> +    gicv3_dist_wait_for_rwp();
> +    gicv3_ctx.dist.ctlr =3D readl_relaxed(GICD + GICD_CTLR);
> +
> +    for ( i =3D 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ )
> +    {
> +        typeof(gicv3_ctx.dist.irqs) irqs =3D gicv3_ctx.dist.irqs + i - 1=
;
> +        unsigned int irq;
> +
> +        base =3D GICD + GICD_ICFGR + 8 * i;
> +        irqs->icfgr[0] =3D readl_relaxed(base);
> +        irqs->icfgr[1] =3D readl_relaxed(base + 4);
> +
> +        base =3D GICD + GICD_IPRIORITYR + 32 * i;
> +        for ( irq =3D 0; irq < 8; irq++ )
> +            irqs->ipriorityr[irq] =3D readl_relaxed(base + 4 * irq);
> +
> +        base =3D GICD + GICD_IROUTER + 32 * i;
> +        for ( irq =3D 0; irq < 32; irq++ )
> +            irqs->irouter[irq] =3D readq_relaxed_non_atomic(base + 8 * i=
rq);
> +
> +        irqs->isactiver =3D readl_relaxed(GICD + GICD_ISACTIVER + 4 * i)=
;
> +        irqs->isenabler =3D readl_relaxed(GICD + GICD_ISENABLER + 4 * i)=
;
> +    }
> +
> +    return 0;
> +}
> +
> +static void gicv3_resume(void)
> +{
> +    unsigned int i;
> +    void __iomem *base;
> +    typeof(gicv3_ctx.rdist)* rdist =3D &gicv3_ctx.rdist;
> +
> +    if ( !gicv3_ctx.dist.irqs && gicv3_info.nr_lines > NR_GIC_LOCAL_IRQS=
 )
> +    {
> +        dprintk(XENLOG_WARNING, "%s:%d: GICv3 suspend context not alloca=
ted!\n",
> +            __func__, __LINE__);
> +        return;
> +    }
> +
> +    writel_relaxed(0, GICD + GICD_CTLR);
> +
> +    for ( i =3D NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i +=3D 32 )
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * =
4);
> +
> +    for ( i =3D 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ )
> +    {
> +        typeof(gicv3_ctx.dist.irqs) irqs =3D gicv3_ctx.dist.irqs + i - 1=
;
> +        unsigned int irq;
> +
> +        base =3D GICD + GICD_ICFGR + 8 * i;
> +        writel_relaxed(irqs->icfgr[0], base);
> +        writel_relaxed(irqs->icfgr[1], base + 4);
> +
> +        base =3D GICD + GICD_IPRIORITYR + 32 * i;
> +        for ( irq =3D 0; irq < 8; irq++ )
> +            writel_relaxed(irqs->ipriorityr[irq], base + 4 * irq );

style: space before )

> +
> +        base =3D GICD + GICD_IROUTER + 32 * i;
> +        for ( irq =3D 0; irq < 32; irq++ )
> +            writeq_relaxed_non_atomic(irqs->irouter[irq], base + 8 * irq=
);
> +
> +        writel_relaxed(irqs->isenabler, GICD + GICD_ISENABLER + i * 4);
> +        writel_relaxed(irqs->isactiver, GICD + GICD_ISACTIVER + i * 4);
> +    }
> +
> +    writel_relaxed(gicv3_ctx.dist.ctlr, GICD + GICD_CTLR);
> +    gicv3_dist_wait_for_rwp();
> +
> +    /* Restore GICR (Redistributor) configuration */
> +    gicv3_enable_redist();
> +
> +    base =3D GICD_RDIST_SGI_BASE;
> +
> +    writel_relaxed(0xffffffff, base + GICR_ICENABLER0);
> +    gicv3_redist_wait_for_rwp();
> +
> +    for (i =3D 0; i < NR_GIC_LOCAL_IRQS / 4; i +=3D 4)
> +        writel_relaxed(rdist->ipriorityr[i], base + GICR_IPRIORITYR0 + i=
 * 4);

Is this correct? You are writing to every 4th GICR_IPRIORITYR

> +
> +    writel_relaxed(rdist->isactiver, base + GICR_ISACTIVER0);
> +
> +    writel_relaxed(rdist->igroupr,  base + GICR_IGROUPR0);
> +    writel_relaxed(rdist->icfgr[0], base + GICR_ICFGR0);
> +    writel_relaxed(rdist->icfgr[1], base + GICR_ICFGR1);
> +
> +    gicv3_redist_wait_for_rwp();
> +
> +    writel_relaxed(rdist->isenabler, base + GICR_ISENABLER0);
> +    writel_relaxed(rdist->ctlr, GICD_RDIST_BASE + GICR_CTLR);
> +
> +    gicv3_redist_wait_for_rwp();
> +
> +    WRITE_SYSREG(gicv3_ctx.cpu.sre_el2, ICC_SRE_EL2);
> +    isb();
> +
> +    /* Restore CPU interface (System registers) */
> +    WRITE_SYSREG(gicv3_ctx.cpu.pmr,   ICC_PMR_EL1);
> +    WRITE_SYSREG(gicv3_ctx.cpu.bpr,   ICC_BPR1_EL1);
> +    WRITE_SYSREG(gicv3_ctx.cpu.ctlr,  ICC_CTLR_EL1);
> +    WRITE_SYSREG(gicv3_ctx.cpu.grpen, ICC_IGRPEN1_EL1);
> +    isb();
> +
> +    gicv3_hyp_init();
> +
> +    gicv3_restore_state(current);
> +}
> +
> +#endif /* CONFIG_SYSTEM_SUSPEND */
> +
>  /* Set up the GIC */
>  static int __init gicv3_init(void)
>  {
> @@ -1850,6 +2075,10 @@ static int __init gicv3_init(void)
> =20
>      gicv3_hyp_init();
> =20
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +    gicv3_alloc_context();
> +#endif
> +
>  out:
>      spin_unlock(&gicv3.lock);
> =20
> @@ -1889,6 +2118,10 @@ static const struct gic_hw_operations gicv3_ops =
=3D {
>  #endif
>      .iomem_deny_access   =3D gicv3_iomem_deny_access,
>      .do_LPI              =3D gicv3_do_LPI,
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +    .suspend             =3D gicv3_suspend,
> +    .resume              =3D gicv3_resume,
> +#endif
>  };
> =20
>  static int __init gicv3_dt_preinit(struct dt_device_node *node, const vo=
id *data)

--=20
WBR, Volodymyr=


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Date: Fri, 22 Aug 2025 17:22:15 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 03/10] xen/arm: scmi-smc: passthrough SCMI SMC to
 domain, single agent
In-Reply-To: <3c8b292b345d81cd20ce260d45d3d7aac6d98702.1753184487.git.oleksii_moisieiev@epam.com>
Message-ID: 
References:  <3c8b292b345d81cd20ce260d45d3d7aac6d98702.1753184487.git.oleksii_moisieiev@epam.com>
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On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> From: Grygorii Strashko 
> 
> The commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI over SMC calls
> handling layer") introduces simple driver which forwards SCMI over SMC
> calls from hwdom/dom0 to EL3 firmware (TF-A) with a single SCMI OSPM agent
> support. While it is working gracefully for hwdom/dom0 use case it doesn't
> cover "thin Dom0 with guest domain, which serves as Driver domain"
> use-case. In this case HW need to be enable in Driver domain and dom0 is
> performing only control functions.
> 
> The EL3 SCMI firmware (TF-A) with a single SCMI OSPM agent support is
> pretty generic case for the default vendors SDK and new platforms.
> 
> This patch enables passthrough of SCMI SMC single agent interface to the
> one guest domain serving as Driver domain.
> 
> Configure Dom0 to enable SCMI passthrough:
> 
>  - dom0: add scmi_smc_passthrough to the Xen Command Line
> 
> Enabled SCMI passthrough for guest using toolstack in the following way:
> 
>  - domD: xl.cfg add "arm_sci" option as below
> 
>    arm_sci = "type=scmi_smc"
> 
>  - domD: xl.cfg enable access to the "arm,scmi-shmem"
> 
> iomem = [
>     "47ff0,1@22001",
> ]
> 
>  - domD: add SCMI nodes to the Driver domain partial device tree as in the
>  below example:
> 
> passthrough {
>    scmi_shm_0: sram@22001000 {
>        compatible = "arm,scmi-shmem";
>        reg = <0x0 0x22001000 0x0 0x1000>;
>    };
> 
>    firmware {
>         compatible = "simple-bus";
>             scmi: scmi {
>                 compatible = "arm,scmi-smc";
>                 shmem = <&scmi_shm_0>;
>                 ...
>             }
>     }
> }
> 
> dom0less case configuration:
> 
> - add "xen,sci_type" property for required DomU ("xen,domain") node
> 
>    xen,sci_type="scmi_smc"
> 
> - add scmi nodes to the Driver domain partial device tree the same way
> as above and enable access to the "arm,scmi-shmem" according to
> dom0less documentation. For example:
> 
>   scmi_shm_0: sram@22001000 {
>         compatible = "arm,scmi-shmem";
>         reg = <0x00 0x22001000 0x00 0x1000>;
> ->        xen,reg = <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
> ->        xen,force-assign-without-iommu;
>   };
> 
> The SCMI SMC single agent interface can be enabled for one and only one
> domain. In general, the configuration is similar to any other HW
> passthrough, except explicitly enabling SCMI with "arm_sci" xl.cfg option.
> 
> Note that "arm,scmi-smc" and "arm,scmi-shmem" nodes will be removed from
> dom0/hwdom DT in case of

This patch needs to be rebased, other than that, it is OK



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Date: Fri, 22 Aug 2025 17:26:10 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 01/10] xen/arm: add generic SCI subsystem
In-Reply-To: 
Message-ID: 
References:  
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On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> This patch adds the basic framework for ARM SCI mediator. SCI is System
> Control Interface, which is designed to redirect requests from the Domains
> to ARM specific Firmware (for example SCMI). This will allow the devices,
> passed-through to the different Domains, to access to the System resources
> (such as clocks/resets etc) by sending requests to the firmware.
> 
> ARM SCI subsystem allows to implement different SCI drivers to handle
> specific ARM firmware interfaces (like ARM SCMI) and mediate requests
> -between the Domains and the Firmware. Also it allows SCI drivers to perform
> proper action during Domain creation/destruction which is vital for
> handling use cases like Domain reboot.
> 
> This patch introduces new DEVICE_FIRMWARE device subclass for probing SCI
> drivers basing on device tree, SCI drivers register itself with
> DT_DEVICE_START/END macro. On init - the SCI drivers should register its
> SCI ops with sci_register(). Only one SCI driver can be supported.
> 
> At run-time, the following SCI API calls are introduced:
> 
> - sci_domain_sanitise_config() called from arch_sanitise_domain_config()
> - sci_domain_init() called from arch_domain_create()
> - sci_relinquish_resources() called from domain_relinquish_resources()
> - sci_domain_destroy() called from arch_domain_destroy()
> - sci_handle_call() called from vsmccc_handle_call()
> - sci_dt_handle_node()
> - sci_dt_finalize() called from handle_node() (Dom0 DT)
> 
> Signed-off-by: Oleksii Moisieiev 
> Signed-off-by: Grygorii Strashko 

The patch needs rebasing


> ---
> 
> Changes in v5:
> - update Maintainers file. Set role as a Reviewer
> - rebased on the latest master branch
> - Introduce arch_handle_passthrough_prop call to handle arm specific nodes
> 
> Changes in v4:
> - fix SPDX-License
> - rename DEVICE_ARM_SCI DT device class to FIRMWARE_DEVICE
> - move XEN_DOMCTL_assign_device code in separate patch
> - Add documentation for SCI SCMI drivers
> 
>  MAINTAINERS                              |   6 +
>  xen/arch/arm/device.c                    |   5 +
>  xen/arch/arm/dom0less-build.c            |   8 +
>  xen/arch/arm/domain.c                    |  12 +-
>  xen/arch/arm/domain_build.c              |   8 +
>  xen/arch/arm/firmware/Kconfig            |   8 +
>  xen/arch/arm/firmware/Makefile           |   1 +
>  xen/arch/arm/firmware/sci.c              | 154 +++++++++++++++++
>  xen/arch/arm/include/asm/domain.h        |   5 +
>  xen/arch/arm/include/asm/firmware/sci.h  | 200 +++++++++++++++++++++++
>  xen/arch/arm/vsmc.c                      |   3 +
>  xen/common/device-tree/dom0less-build.c  |   4 +
>  xen/include/asm-generic/device.h         |   1 +
>  xen/include/asm-generic/dom0less-build.h |   9 +
>  xen/include/public/arch-arm.h            |   4 +
>  15 files changed, 427 insertions(+), 1 deletion(-)
>  create mode 100644 xen/arch/arm/firmware/sci.c
>  create mode 100644 xen/arch/arm/include/asm/firmware/sci.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c4886c1159..31dbba54bb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -509,6 +509,12 @@ R:	George Dunlap 
>  S:	Supported
>  F:	xen/common/sched/
>  
> +SCI MEDIATORS
> +R:	Oleksii Moisieiev 
> +S:	Supported
> +F:	xen/arch/arm/firmware/sci.c
> +F:	xen/arch/arm/include/asm/firmware/sci.h
> +
>  SEABIOS UPSTREAM
>  M:	Wei Liu 
>  S:	Supported
> diff --git a/xen/arch/arm/device.c b/xen/arch/arm/device.c
> index 11523750ae..74b54cad34 100644
> --- a/xen/arch/arm/device.c
> +++ b/xen/arch/arm/device.c
> @@ -13,6 +13,7 @@
>  #include 
>  #include 
>  
> +#include 
>  #include 
>  
>  int map_irq_to_domain(struct domain *d, unsigned int irq,
> @@ -303,6 +304,10 @@ int handle_device(struct domain *d, struct dt_device_node *dev, p2m_type_t p2mt,
>                  return res;
>              }
>          }
> +
> +        res = sci_assign_dt_device(d, dev);
> +        if ( res )
> +            return res;
>      }
>  
>      res = map_device_irqs_to_domain(d, dev, own_device, irq_ranges);
> diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
> index 4b285cff5e..2a0bf817ba 100644
> --- a/xen/arch/arm/dom0less-build.c
> +++ b/xen/arch/arm/dom0less-build.c
> @@ -22,6 +22,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  
> @@ -272,6 +273,12 @@ int __init init_vuart(struct domain *d, struct kernel_info *kinfo,
>      return rc;
>  }
>  
> +int __init arch_handle_passthrough_prop(struct kernel_info *kinfo,
> +                                        struct dt_device_node *node)
> +{
> +    return sci_assign_dt_device(kinfo->d, node);
> +}
> +
>  void __init arch_create_domUs(struct dt_device_node *node,
>                         struct xen_domctl_createdomain *d_cfg,
>                         unsigned int flags)
> @@ -280,6 +287,7 @@ void __init arch_create_domUs(struct dt_device_node *node,
>  
>      d_cfg->arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE;
>      d_cfg->flags |= XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap;
> +    d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
>  
>      if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) )
>      {
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index 79a144e61b..d0146da5da 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -24,6 +24,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -699,7 +700,7 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config)
>          return -EINVAL;
>      }
>  
> -    return 0;
> +    return sci_domain_sanitise_config(config);
>  }
>  
>  int arch_domain_create(struct domain *d,
> @@ -791,6 +792,9 @@ int arch_domain_create(struct domain *d,
>      d->arch.sve_vl = config->arch.sve_vl;
>  #endif
>  
> +    if ( (rc = sci_domain_init(d, config)) != 0 )
> +        goto fail;
> +
>      return 0;
>  
>  fail:
> @@ -851,6 +855,7 @@ void arch_domain_destroy(struct domain *d)
>      domain_vgic_free(d);
>      domain_vuart_free(d);
>      free_xenheap_page(d->shared_info);
> +    sci_domain_destroy(d);
>  #ifdef CONFIG_ACPI
>      free_xenheap_pages(d->arch.efi_acpi_table,
>                         get_order_from_bytes(d->arch.efi_acpi_len));
> @@ -1044,6 +1049,7 @@ enum {
>      PROG_p2m_root,
>      PROG_p2m,
>      PROG_p2m_pool,
> +    PROG_sci,
>      PROG_done,
>  };
>  
> @@ -1103,6 +1109,10 @@ int domain_relinquish_resources(struct domain *d)
>          ret = relinquish_p2m_mapping(d);
>          if ( ret )
>              return ret;
> +    PROGRESS(sci):
> +        ret = sci_relinquish_resources(d);
> +        if ( ret )
> +            return ret;
>  
>      PROGRESS(p2m_root):
>          /*
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index ed668bd61c..92039cf213 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -26,6 +26,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -1639,6 +1640,9 @@ static int __init handle_node(struct domain *d, struct kernel_info *kinfo,
>          return 0;
>      }
>  
> +    if ( sci_dt_handle_node(d, node) )
> +        return 0;
> +
>      /*
>       * The vGIC does not support routing hardware PPIs to guest. So
>       * we need to skip any node using PPIs.
> @@ -1739,6 +1743,10 @@ static int __init handle_node(struct domain *d, struct kernel_info *kinfo,
>          if ( res )
>              return res;
>  
> +        res = sci_dt_finalize(d, kinfo->fdt);
> +        if ( res )
> +            return res;
> +
>          /*
>           * Create a second memory node to store the ranges covering
>           * reserved-memory regions.
> diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig
> index 817da745fd..fc7918c7fc 100644
> --- a/xen/arch/arm/firmware/Kconfig
> +++ b/xen/arch/arm/firmware/Kconfig
> @@ -1,3 +1,11 @@
> +config ARM_SCI
> +	bool
> +	depends on ARM
> +	help
> +	  This option enables generic Arm SCI (System Control Interface) mediators
> +	  support. It allows domains to control system resources via one of
> +	  Arm SCI mediators drivers implemented in XEN, like SCMI.
> +
>  menu "Firmware Drivers"
>  
>  config SCMI_SMC
> diff --git a/xen/arch/arm/firmware/Makefile b/xen/arch/arm/firmware/Makefile
> index a5e4542666..71bdefc24a 100644
> --- a/xen/arch/arm/firmware/Makefile
> +++ b/xen/arch/arm/firmware/Makefile
> @@ -1 +1,2 @@
> +obj-$(CONFIG_ARM_SCI) += sci.o
>  obj-$(CONFIG_SCMI_SMC) += scmi-smc.o
> diff --git a/xen/arch/arm/firmware/sci.c b/xen/arch/arm/firmware/sci.c
> new file mode 100644
> index 0000000000..e1522e10e2
> --- /dev/null
> +++ b/xen/arch/arm/firmware/sci.c
> @@ -0,0 +1,154 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Generic part of the SCI (System Control Interface) subsystem.
> + *
> + * Oleksii Moisieiev 
> + * Copyright (c) 2025 EPAM Systems
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +static const struct sci_mediator_ops __read_mostly *cur_mediator;
> +
> +int sci_register(const struct sci_mediator_ops *ops)
> +{
> +    if ( cur_mediator )
> +        return -EEXIST;
> +
> +    if ( !ops->domain_init || !ops->domain_destroy || !ops->handle_call )
> +        return -EINVAL;
> +
> +    cur_mediator = ops;
> +
> +    return 0;
> +};
> +
> +bool sci_handle_call(struct cpu_user_regs *args)
> +{
> +    if ( unlikely(!cur_mediator) )
> +        return false;

should we check that sci_domain_is_enabled ?


> +    return cur_mediator->handle_call(args);
> +}
> +
> +int sci_domain_init(struct domain *d, struct xen_domctl_createdomain *config)
> +{
> +    if ( !cur_mediator )
> +        return 0;
> +
> +    return cur_mediator->domain_init(d, config);
> +}
> +
> +int sci_domain_sanitise_config(struct xen_domctl_createdomain *config)
> +{
> +    if ( !cur_mediator )
> +        return 0;
> +
> +    if ( !cur_mediator->domain_sanitise_config )
> +        return 0;
> +
> +    return cur_mediator->domain_sanitise_config(config);
> +}
> +
> +void sci_domain_destroy(struct domain *d)
> +{
> +    if ( !cur_mediator )
> +        return;
> +
> +    cur_mediator->domain_destroy(d);
> +}
> +
> +int sci_relinquish_resources(struct domain *d)
> +{
> +    if ( !cur_mediator )
> +        return 0;
> +
> +    if ( !cur_mediator->relinquish_resources )
> +        return 0;
> +
> +    return cur_mediator->relinquish_resources(d);
> +}
> +
> +bool sci_dt_handle_node(struct domain *d, struct dt_device_node *node)
> +{
> +    if ( !cur_mediator )
> +        return 0;
> +
> +    if ( !cur_mediator->dom0_dt_handle_node )
> +        return 0;
> +
> +    return cur_mediator->dom0_dt_handle_node(d, node);
> +}
> +
> +int sci_dt_finalize(struct domain *d, void *fdt)
> +{
> +    if ( !cur_mediator )
> +        return 0;
> +
> +    if ( !cur_mediator->dom0_dt_finalize )
> +        return 0;
> +
> +    return cur_mediator->dom0_dt_finalize(d, fdt);
> +}
> +
> +int sci_assign_dt_device(struct domain *d, struct dt_device_node *dev)
> +{
> +    struct dt_phandle_args ac_spec;
> +    int index = 0;
> +    int ret;
> +
> +    if ( !cur_mediator )
> +        return 0;
> +
> +    if ( !cur_mediator->assign_dt_device )
> +        return 0;
> +
> +    while ( !dt_parse_phandle_with_args(dev, "access-controllers",
> +                                        "#access-controller-cells", index,
> +                                        &ac_spec) )
> +    {
> +        printk(XENLOG_DEBUG "sci: assign device %s to %pd\n",
> +               dt_node_full_name(dev), d);
> +
> +        ret = cur_mediator->assign_dt_device(d, &ac_spec);
> +        if ( ret )
> +            return ret;
> +
> +        index++;
> +    }
> +
> +    return 0;
> +}
> +
> +static int __init sci_init(void)
> +{
> +    struct dt_device_node *np;
> +    unsigned int num_sci = 0;
> +    int rc;
> +
> +    dt_for_each_device_node(dt_host, np)
> +    {
> +        rc = device_init(np, DEVICE_FIRMWARE, NULL);
> +        if ( !rc && num_sci )
> +        {
> +            printk(XENLOG_ERR
> +                   "SCMI: Only one SCI controller is supported. found second %s\n",
> +                   np->name);
> +            return -EOPNOTSUPP;
> +        }
> +        else if ( !rc )
> +            num_sci++;
> +        else if ( rc != -EBADF && rc != -ENODEV )
> +            return rc;
> +    }
> +
> +    return 0;
> +}
> +
> +__initcall(sci_init);
> diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
> index a3487ca713..af3e168374 100644
> --- a/xen/arch/arm/include/asm/domain.h
> +++ b/xen/arch/arm/include/asm/domain.h
> @@ -120,6 +120,11 @@ struct arch_domain
>  #ifdef CONFIG_TEE
>      void *tee;
>  #endif
> +#ifdef CONFIG_ARM_SCI
> +    bool sci_enabled;
> +    /* ARM SCI driver's specific data */
> +    void *sci_data;
> +#endif
>  
>  }  __cacheline_aligned;
>  
> diff --git a/xen/arch/arm/include/asm/firmware/sci.h b/xen/arch/arm/include/asm/firmware/sci.h
> new file mode 100644
> index 0000000000..71fb54852e
> --- /dev/null
> +++ b/xen/arch/arm/include/asm/firmware/sci.h
> @@ -0,0 +1,200 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Generic ARM SCI (System Control Interface) subsystem.
> + *
> + * Oleksii Moisieiev 
> + * Copyright (c) 2025 EPAM Systems
> + */
> +
> +#ifndef __ASM_ARM_SCI_H
> +#define __ASM_ARM_SCI_H
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#ifdef CONFIG_ARM_SCI
> +
> +struct sci_mediator_ops {
> +    /*
> +     * Called during domain construction. If it is requested to enable
> +     * SCI support, so SCI driver can create own structures for the new domain
> +     * and inform firmware about new domain (if required).
> +     * Mandatory.
> +     */
> +    int (*domain_init)(struct domain *d,
> +                       struct xen_domctl_createdomain *config);
> +
> +    /*
> +     * Called during domain construction. The SCI driver uses
> +     * it to sanitize domain SCI configuration parameters.
> +     * Optional.
> +     */
> +    int (*domain_sanitise_config)(struct xen_domctl_createdomain *config);
> +
> +    /*
> +     * Called during domain destruction, releases all resources, that
> +     * were allocated for domain.
> +     * Mandatory.
> +     */
> +    void (*domain_destroy)(struct domain *d);
> +
> +    /*
> +     * Called during domain destruction to relinquish resources used
> +     * by SCI driver itself and request resources releasing from firmware.
> +     * Optional.
> +     */
> +    int (*relinquish_resources)(struct domain *d);
> +
> +    /* SMC/HVC Handle callback */
> +    bool (*handle_call)(struct cpu_user_regs *regs);
> +
> +    /*
> +     * Dom0 DT nodes handling callback so SCI driver can detect DT nodes it
> +     * need to handle and decide if those nodes need to be provided to Dom0.
> +     * Optional.
> +     */
> +    bool (*dom0_dt_handle_node)(struct domain *d, struct dt_device_node *node);
> +
> +    /*
> +     * SCI driver callback called at the end of Dom0 DT generation, so
> +     * it can perform steps to modify DT to enable/disable SCI
> +     * functionality for Dom0.
> +     */
> +    int (*dom0_dt_finalize)(struct domain *d, void *fdt);
> +
> +    /*
> +     * SCI driver callback called when DT device is passed through to guest,
> +     * so SCI driver can enable device access to the domain if SCI FW provides
> +     * Device specific access control functionality.
> +     * Optional.
> +     */
> +    int (*assign_dt_device)(struct domain *d, struct dt_phandle_args *ac_spec);
> +};
> +
> +
> +static inline bool sci_domain_is_enabled(struct domain *d)
> +{
> +    return d->arch.sci_enabled;
> +}
> +
> +/*
> + * Register SCI subsystem ops.
> + *
> + * Register SCI drivers operation and so enable SCI functionality.
> + * Only one SCI driver is supported.
> + */
> +int sci_register(const struct sci_mediator_ops *ops);
> +
> +/*
> + * Initialize SCI functionality for domain if configured.
> + *
> + * Initialization routine to enable SCI functionality for the domain.
> + * The SCI configuration data and decision about enabling SCI functionality
> + * for the domain is SCI driver specific.
> + */
> +int sci_domain_init(struct domain *d, struct xen_domctl_createdomain *config);
> +
> +/*
> + * Sanitise domain configuration parameters.
> + *
> + */
> +int sci_domain_sanitise_config(struct xen_domctl_createdomain *config);
> +
> +/*
> + * Destroy SCI domain instance.
> + */
> +void sci_domain_destroy(struct domain *d);
> +
> +/*
> + * Free resources assigned to the certain domain.
> + */
> +int sci_relinquish_resources(struct domain *d);
> +
> +/*
> + * SMC/HVC Handle callback.
> + *
> + * SCI driver acts as SMC/HVC server for the registered domains and
> + * does redirection of the domain calls to the SCI firmware,
> + * such as ARM TF-A or similar.
> + */
> +bool sci_handle_call(struct cpu_user_regs *regs);
> +
> +/*
> + * Dom0 DT nodes handling function.
> + *
> + * Allows SCI driver to detect DT nodes it need to handle and decide if
> + * those nodes need to be provided to Dom0.
> + */
> +bool sci_dt_handle_node(struct domain *d, struct dt_device_node *node);
> +
> +/*
> + * Dom0 DT generation finalize.
> + *
> + * Called at the end of Dom0 DT generation, so SCI driver can perform steps
> + * to modify DT to enable/disable SCI functionality for Dom0.
> + */
> +int sci_dt_finalize(struct domain *d, void *fdt);
> +
> +/*
> + * Assign DT device to domain.
> + *
> + * Called when DT device is passed through to guest, so SCI driver can enable
> + * device access to the domain if SCI FW provides "Device specific access
> + * control" functionality.
> + */
> +int sci_assign_dt_device(struct domain *d, struct dt_device_node *dev);
> +#else
> +
> +static inline bool sci_domain_is_enabled(struct domain *d)
> +{
> +    return false;
> +}
> +
> +static inline int sci_domain_init(struct domain *d,
> +                                  struct xen_domctl_createdomain *config)
> +{
> +    return 0;
> +}
> +
> +static inline int
> +sci_domain_sanitise_config(struct xen_domctl_createdomain *config)
> +{
> +    return 0;
> +}
> +
> +static inline void sci_domain_destroy(struct domain *d)
> +{}
> +
> +static inline int sci_relinquish_resources(struct domain *d)
> +{
> +    return 0;
> +}
> +
> +static inline bool sci_handle_call(struct cpu_user_regs *args)
> +{
> +    return false;
> +}
> +
> +static inline bool sci_dt_handle_node(struct domain *d,
> +                                      struct dt_device_node *node)
> +{
> +    return false;
> +}
> +
> +static inline int sci_dt_finalize(struct domain *d, void *fdt)
> +{
> +    return false;

should return int, not bool


> +}
> +
> +static inline int sci_assign_dt_device(struct domain *d,
> +                                       struct dt_device_node *dev)
> +{
> +    return 0;
> +}
> +
> +#endif /* CONFIG_ARM_SCI */
> +
> +#endif /* __ASM_ARM_SCI_H */
> diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c
> index 6081f14ed0..2469738fcc 100644
> --- a/xen/arch/arm/vsmc.c
> +++ b/xen/arch/arm/vsmc.c
> @@ -12,6 +12,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -300,6 +301,8 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs)
>              break;
>          case ARM_SMCCC_OWNER_SIP:
>              handled = handle_sip(regs);
> +            if ( !handled )
> +                handled = sci_handle_call(regs);
>              break;
>          case ARM_SMCCC_OWNER_TRUSTED_APP ... ARM_SMCCC_OWNER_TRUSTED_APP_END:
>          case ARM_SMCCC_OWNER_TRUSTED_OS ... ARM_SMCCC_OWNER_TRUSTED_OS_END:
> diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c
> index 0012046574..f29656a27e 100644
> --- a/xen/common/device-tree/dom0less-build.c
> +++ b/xen/common/device-tree/dom0less-build.c
> @@ -228,6 +228,10 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo,
>      if ( res < 0 )
>          return res;
>  
> +    res = arch_handle_passthrough_prop(kinfo, node);
> +    if ( res )
> +        return res;
> +
>      /* If xen_force, we allow assignment of devices without IOMMU protection. */
>      if ( xen_force && !dt_device_is_protected(node) )
>          return 0;
> diff --git a/xen/include/asm-generic/device.h b/xen/include/asm-generic/device.h
> index 1acd1ba1d8..e96c5558c2 100644
> --- a/xen/include/asm-generic/device.h
> +++ b/xen/include/asm-generic/device.h
> @@ -18,6 +18,7 @@ enum device_class
>      DEVICE_IOMMU,
>      DEVICE_INTERRUPT_CONTROLLER,
>      DEVICE_PCI_HOSTBRIDGE,
> +    DEVICE_FIRMWARE,
>      /* Use for error */
>      DEVICE_UNKNOWN,
>  };
> diff --git a/xen/include/asm-generic/dom0less-build.h b/xen/include/asm-generic/dom0less-build.h
> index e0ad0429ec..1c56441c33 100644
> --- a/xen/include/asm-generic/dom0less-build.h
> +++ b/xen/include/asm-generic/dom0less-build.h
> @@ -61,6 +61,9 @@ void set_domain_type(struct domain *d, struct kernel_info *kinfo);
>  int init_intc_phandle(struct kernel_info *kinfo, const char *name,
>                        const int node_next, const void *pfdt);
>  
> +int arch_handle_passthrough_prop(struct kernel_info *kinfo,
> +                                 struct dt_device_node *node);
> +
>  #else /* !CONFIG_DOM0LESS_BOOT */
>  
>  static inline void create_domUs(void) {}
> @@ -70,6 +73,12 @@ static inline bool is_dom0less_mode(void)
>  }
>  static inline void set_xs_domain(struct domain *d) {}
>  
> +static inline int arch_handle_passthrough_prop(struct kernel_info *kinfo,
> +                                               struct dt_device_node *node)
> +{
> +    return 0;
> +}
> +
>  #endif /* CONFIG_DOM0LESS_BOOT */
>  
>  #endif /* __ASM_GENERIC_DOM0LESS_BUILD_H__ */
> diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
> index 24840eeaa6..55eed9992c 100644
> --- a/xen/include/public/arch-arm.h
> +++ b/xen/include/public/arch-arm.h
> @@ -327,6 +327,8 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
>  #define XEN_DOMCTL_CONFIG_TEE_OPTEE     1
>  #define XEN_DOMCTL_CONFIG_TEE_FFA       2
>  
> +#define XEN_DOMCTL_CONFIG_ARM_SCI_NONE      0
> +
>  struct xen_arch_domainconfig {
>      /* IN/OUT */
>      uint8_t gic_version;
> @@ -350,6 +352,8 @@ struct xen_arch_domainconfig {
>       *
>       */
>      uint32_t clock_frequency;
> +    /* IN */
> +    uint8_t arm_sci_type;
>  };
>  #endif /* __XEN__ || __XEN_TOOLS__ */
>  
> -- 
> 2.34.1
> 


From xen-devel-bounces@lists.xenproject.org Sat Aug 23 00:26:24 2025
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Date: Fri, 22 Aug 2025 17:26:16 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 02/10] xen/arm: scmi-smc: update to be used under
 sci subsystem
In-Reply-To: 
Message-ID: 
References:  
User-Agent: Alpine 2.22 (DEB 394 2020-01-19)
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Content-Type: text/plain; charset=US-ASCII

On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> From: Grygorii Strashko 
> 
> The introduced SCI (System Control Interface) subsystem provides unified
> interface to integrate in Xen SCI drivers which adds support for ARM
> firmware (EL3, SCP) based software interfaces (like SCMI) that are used in
> system management. The SCI subsystem allows to add drivers for different FW
> interfaces or have different drivers for the same FW interface (for example,
> SCMI with different transports).
> 
> This patch updates SCMI over SMC calls handling layer, introduced by
> commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI over SMC calls handling
> layer"), to be SCI driver:
> - convert to DT device;
> - convert to SCI Xen interface.
> 
> There are no functional changes in general, the driver is just adopted
> to the SCI interface.
> 
> Signed-off-by: Grygorii Strashko 
> Signed-off-by: Oleksii Moisieiev 
> ---
> 
> 
> 
>  xen/arch/arm/firmware/Kconfig                | 13 ++-
>  xen/arch/arm/firmware/scmi-smc.c             | 93 +++++++++++---------
>  xen/arch/arm/include/asm/firmware/scmi-smc.h | 41 ---------
>  xen/arch/arm/vsmc.c                          |  5 +-
>  xen/include/public/arch-arm.h                |  1 +
>  5 files changed, 64 insertions(+), 89 deletions(-)
>  delete mode 100644 xen/arch/arm/include/asm/firmware/scmi-smc.h
> 
> diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig
> index fc7918c7fc..bbf88fbb9a 100644
> --- a/xen/arch/arm/firmware/Kconfig
> +++ b/xen/arch/arm/firmware/Kconfig
> @@ -8,9 +8,18 @@ config ARM_SCI
>  
>  menu "Firmware Drivers"
>  
> +choice
> +	prompt "ARM SCI driver type"
> +	default SCMI_SMC
> +	help
> +	Choose which ARM SCI driver to enable.
> +
> +config ARM_SCI_NONE
> +	bool "none"
> +
>  config SCMI_SMC
>  	bool "Forward SCMI over SMC calls from hwdom to EL3 firmware"
> -	default y
> +	select ARM_SCI
>  	help
>  	  This option enables basic awareness for SCMI calls using SMC as
>  	  doorbell mechanism and Shared Memory for transport ("arm,scmi-smc"
> @@ -18,4 +27,6 @@ config SCMI_SMC
>  	  firmware node is used to trap and forward corresponding SCMI SMCs
>  	  to firmware running at EL3, for calls coming from the hardware domain.
>  
> +endchoice
> +
>  endmenu
> diff --git a/xen/arch/arm/firmware/scmi-smc.c b/xen/arch/arm/firmware/scmi-smc.c
> index 33473c04b1..13d1137592 100644
> --- a/xen/arch/arm/firmware/scmi-smc.c
> +++ b/xen/arch/arm/firmware/scmi-smc.c
> @@ -9,6 +9,7 @@
>   * Copyright 2024 NXP
>   */
>  
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -16,12 +17,11 @@
>  #include 
>  #include 
>  
> +#include 
>  #include 
> -#include 
>  
>  #define SCMI_SMC_ID_PROP   "arm,smc-id"
>  
> -static bool __ro_after_init scmi_enabled;
>  static uint32_t __ro_after_init scmi_smc_id;
>  
>  /*
> @@ -41,14 +41,11 @@ static bool scmi_is_valid_smc_id(uint32_t fid)
>   *
>   * Returns true if SMC was handled (regardless of response), false otherwise.
>   */
> -bool scmi_handle_smc(struct cpu_user_regs *regs)
> +static bool scmi_handle_smc(struct cpu_user_regs *regs)
>  {
>      uint32_t fid = (uint32_t)get_user_reg(regs, 0);
>      struct arm_smccc_res res;
>  
> -    if ( !scmi_enabled )
> -        return false;
> -
>      if ( !scmi_is_valid_smc_id(fid) )
>          return false;
>  
> @@ -78,49 +75,45 @@ bool scmi_handle_smc(struct cpu_user_regs *regs)
>      return true;
>  }
>  
> -static int __init scmi_check_smccc_ver(void)
> +static int scmi_smc_domain_init(struct domain *d,
> +                                struct xen_domctl_createdomain *config)
>  {
> -    if ( smccc_ver < ARM_SMCCC_VERSION_1_1 )
> -    {
> -        printk(XENLOG_WARNING
> -               "SCMI: No SMCCC 1.1 support, SCMI calls forwarding disabled\n");
> -        return -ENOSYS;
> -    }
> +    if ( !is_hardware_domain(d) )
> +        return 0;

Should we also check for config->arch.sci_type ==
XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC ?


> +    d->arch.sci_enabled = true;
> +    printk(XENLOG_DEBUG "SCMI: %pd init\n", d);
>      return 0;
>  }



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Date: Fri, 22 Aug 2025 17:30:10 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 04/10] docs: arm: add docs for SCMI over SMC calls
 forwarding driver
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On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> From: Grygorii Strashko 
> 
> Add documentation section for Simple Arm SCMI over SMC/HVC calls forwarding
> driver (EL3).
> 
> Signed-off-by: Grygorii Strashko 
> Signed-off-by: Oleksii Moisieiev 

This doc looks good, a couple of minor suggestions:
- briefly document the bindings expected as input (e.g. compatible
  "arm,scmi-smc" and "arm,scmi-shmem") or simply provide links to official docs
- it says "SCMI over SMC/HVC" but I am not sure if HVC would actually
  work


> ---
> 
> Changes in v5:
> - rename dom0_scmi_smc_passthrough in documentation
> 
>  .../arm/firmware/arm-scmi.rst                 | 177 ++++++++++++++++++
>  docs/hypervisor-guide/arm/index.rst           |   9 +
>  docs/hypervisor-guide/index.rst               |   1 +
>  3 files changed, 187 insertions(+)
>  create mode 100644 docs/hypervisor-guide/arm/firmware/arm-scmi.rst
>  create mode 100644 docs/hypervisor-guide/arm/index.rst
> 
> diff --git a/docs/hypervisor-guide/arm/firmware/arm-scmi.rst b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> new file mode 100644
> index 0000000000..a084c0caa3
> --- /dev/null
> +++ b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> @@ -0,0 +1,177 @@
> +.. SPDX-License-Identifier: CC-BY-4.0
> +
> +ARM System Control and Management Interface (SCMI)
> +==================================================
> +
> +The System Control and Management Interface (SCMI) [1], which is a set of operating
> +system-independent software interfaces that are used in system management. SCMI currently
> +provides interfaces for:
> +
> +- Discovery and self-description of the interfaces it supports
> +- Power domain management
> +- Clock management
> +- Reset domain management
> +- Voltage domain management
> +- Sensor management
> +- Performance management
> +- Power capping and monitoring
> +- Pin control protocol.
> +
> +The SCMI compliant firmware could run:
> +
> +- as part of EL3 secure world software (like Trusted Firmware-A) with
> +  ARM SMC/HVC shared-memory transport;
> +- on dedicated System Control Processor (SCP) with HW mailbox shared-memory transport
> +
> +The major purpose of enabling SCMI support in Xen is to enable guest domains access to the SCMI
> +interfaces for performing management actions on passed-through devices (such as clocks/resets etc)
> +without accessing directly to the System control HW (like clock controllers) which in most cases
> +can't shared/split between domains. Or, at minimum, allow SCMI access for dom0/hwdom (or guest
> +domain serving as Driver domain).
> +
> +The below sections describe SCMI support options available for Xen.
> +
> +[1] `Arm SCMI `_
> +
> +Simple SCMI over SMC/HVC calls forwarding driver (EL3)
> +------------------------------------------------------
> +
> +The EL3 SCMI firmware (TF-A) with a single SCMI OSPM agent support is pretty generic case for
> +the default vendors SDK and new platforms with SCMI support. Such EL3 SCMI firmware supports only
> +single SCMI OSPM transport (agent) with Shared memory based transport and SMC/HVC calls as doorbell.
> +
> +The SCMI over SMC/HVC calls forwarding driver solves major problem for this case by allowing
> +SMC/HVC calls to be forwarded form guest to the EL3 SCMI firmware.
> +
> +By default, the SCMI over SMC/HVC calls forwarding is enabled for Dom0/hwdom.
> +
> +::
> +
> +    +--------------------------+
> +    |                          |
> +    | EL3 SCMI FW (TF-A)       |
> +    ++-------+--^--------------+
> +     |shmem  |  | smc-id
> +     +----^--+  |
> +          |     |
> +     +----|-+---+---+----------+
> +     |    | |  FWD  |      Xen |
> +     |    | +---^---+          |
> +     +----|-----|--------------+
> +          |     | smc-id
> +     +----v-----+--+ +---------+
> +     |             | |         |
> +     | Dom0/hwdom  | | DomU    |
> +     |             | |         |
> +     |             | |         |
> +     +-------------+ +---------+
> +
> +
> +The SCMI messages are passed directly through SCMI shared-memory (zero-copy) and driver only
> +forwards SMC/HVC calls.
> +
> +Compiling
> +^^^^^^^^^
> +
> +To build with the SCMI over SMC/HVC calls forwarding enabled support, enable Kconfig option
> +
> +::
> +
> +    CONFIG_SCMI_SMC
> +
> +The ``CONFIG_SCMI_SMC`` is enabled by default.
> +
> +Pass-through SCMI SMC to domain which serves as Driver domain
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +This section describes how to configure the SCMI over SMC/HVC calls forwarding driver to handle use
> +case "thin Dom0 with guest domain, which serves as Driver domain". In this case HW need to be
> +enabled in Driver domain and dom0 is performing only control functions (without accessing FW) and so,
> +the SCMI need to be enabled in Driver domain.
> +
> +::
> +
> +     +--------------------------+
> +     |EL3 SCMI FW (TF-A)        |
> +     |                          |
> +     +-------------^--+-------+-+
> +             smc-id|  |shmem0 |
> +                   |  +----^--+
> +    +-------------++------+|----+
> +    |Xen          |  FWD  ||    |
> +    |             +--^----+|    |
> +    +----------------|-----|----+
> +              smc-id |     |
> +    +-----------+ +--+-----v-----+
> +    |           | |              |
> +    | Dom0      | |    Driver    |
> +    | Control   | |    domain    |
> +    |           | |              |
> +    +-----------+ +--------------+
> +
> +The SCMI can be enabled for one and only one guest domain.
> +
> +First. configure Dom0 to enable SCMI pass-through using Xen Command Line
> +**"scmi_smc_passthrough"** option. This will disable SCMI for Dom0/hwdom and SCMI nodes will
> +be removed from Dom0/hwdom device tree.
> +
> +**Configure SCMI pass-through for guest domain with toolstack**
> +
> +* In domain's xl.cfg file add **"arm_sci"** option as below
> +
> +::
> +
> +    arm_sci = "type=scmi_smc"
> +
> +* In domain's xl.cfg file enable access to the "arm,scmi-shmem"
> +
> +::
> +
> +    iomem = [
> +        "47ff0,1@22001",
> +    ]
> +
> +.. note:: It's up to the user to select guest IPA for mapping SCMI shared-memory.
> +
> +* Add SCMI nodes to the Driver domain partial device tree as in the below example:
> +
> +.. code::
> +
> +    passthrough {
> +       scmi_shm_0: sram@22001000 {
> +           compatible = "arm,scmi-shmem";
> +           reg = <0x0 0x22001000 0x0 0x1000>;
> +       };
> +
> +       firmware {
> +            compatible = "simple-bus";
> +                scmi: scmi {
> +                    compatible = "arm,scmi-smc";
> +                    shmem = <&scmi_shm_0>;
> +                    ...
> +                }
> +        }
> +    }
> +
> +In general, the configuration is similar to any other HW pass-through, except explicitly
> +enabling SCMI with "arm_sci" xl.cfg option.
> +
> +**Configure SCMI pass-through for predefined domain (dom0less)**
> +
> +* add "xen,sci_type" property for required DomU ("xen,domain") node
> +
> +::
> +
> +       xen,sci_type="scmi_smc"
> +
> +* add scmi nodes to the Driver domain partial device tree the same way as above and enable access
> +  to the "arm,scmi-shmem" according to  dom0less documentation. For example:
> +
> +.. code::
> +
> +      scmi_shm_0: sram@22001000 {
> +            compatible = "arm,scmi-shmem";
> +            reg = <0x00 0x22001000 0x00 0x1000>;
> +    ->        xen,reg = <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
> +    ->        xen,force-assign-without-iommu;
> +      };
> diff --git a/docs/hypervisor-guide/arm/index.rst b/docs/hypervisor-guide/arm/index.rst
> new file mode 100644
> index 0000000000..7aae4a0a03
> --- /dev/null
> +++ b/docs/hypervisor-guide/arm/index.rst
> @@ -0,0 +1,9 @@
> +.. SPDX-License-Identifier: CC-BY-4.0
> +
> +ARM
> +===
> +
> +.. toctree::
> +   :maxdepth: 2
> +
> +   firmware/arm-scmi
> diff --git a/docs/hypervisor-guide/index.rst b/docs/hypervisor-guide/index.rst
> index e4393b0697..520fe01554 100644
> --- a/docs/hypervisor-guide/index.rst
> +++ b/docs/hypervisor-guide/index.rst
> @@ -9,3 +9,4 @@ Hypervisor documentation
>     code-coverage
>  
>     x86/index
> +   arm/index
> \ No newline at end of file
> -- 
> 2.34.1
> 


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Date: Fri, 22 Aug 2025 17:33:10 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 07/10] xen: arm: smccc: add INVALID_PARAMETER
 error code
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On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> According to the "7.1 Return Codes" section of DEN0028 [1]
> INVALID_PARAMETER code (-3) is returned when one of the call
> parameters has a non-supported value.
> Adding this error code to the common smccc header file.
> 
> [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6
> 
> Signed-off-by: Oleksii Moisieiev 

Acked-by: Stefano Stabellini 

> ---
> 
> 
> 
>  xen/arch/arm/include/asm/smccc.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/smccc.h
> index a289c48b7f..dc6af94db1 100644
> --- a/xen/arch/arm/include/asm/smccc.h
> +++ b/xen/arch/arm/include/asm/smccc.h
> @@ -381,6 +381,7 @@ void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
>                         0x3FFF)
>  
>  /* SMCCC error codes */
> +#define ARM_SMCCC_INVALID_PARAMETER     (-3)
>  #define ARM_SMCCC_NOT_REQUIRED          (-2)
>  #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION  (-1)
>  #define ARM_SMCCC_NOT_SUPPORTED         (-1)
> -- 
> 2.34.1
> 


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Date: Fri, 22 Aug 2025 17:34:07 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 00/10] xen/arm: scmi: introduce SCI SCMI SMC
 multi-agent support
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I think it should be feasible to commit at least patches 1-4 in time for
the release

On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> Inroducing V4 RFC patch series  on top of the Xen version 4.20-rc2
> which includes implementation of the SCI SCMI SMC multi-agent support.
> 
> Patch 1 "xen/arm: add generic SCI subsystem"
> - rebased and refactored
> - introduced DEVICE_ARM_SCI DT device class and used for SCI drivers probing
> instead of custom,
>   linker sections based implementation.
> - added SCI API for Dom0 DT handling, instead of manipulating with ARM arch
> dom0 code directly.
> - RFC changes in XEN_DOMCTL_assign_device OP processing
> - Introduce arch_handle_passthrough_prop call to handle arm specific
> nodes
> 
> Patch 2 "xen/arm: scmi-smc: update to be used under sci subsystem"
> - update driver introduced by commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI
> over SMC calls
> handling layer") be used under sci subsystem.
> - no functional changes in general
> 
> Patch 3 "xen/arm: scmi-smc: passthrough SCMI SMC to guest domain
> This is new change which allows passthrough SCMI SMC, single agent interface to
> guest domain
> cover use case "thin Dom0 with guest domain, which serves as Driver domain".
> See patch commit message for full description.
> 
> Patch 4 - docs: arm: add docs for SCMI over SMC calls forwarding
> driver
> - add documentation section for Simple Arm SCMI over SMC/HVC calls
> forwarding driver.
> 
> Patch 6 - xen/domctl: extend XEN_DOMCTL_assign_device to handle not
> only iommu
> - add chainged handling of assigned DT devices to support
> access-controller functionality through SCI framework.
> Change was done in two parts:
>  - update iommu_do_dt_domctl() to check for dt_device_is_protected()
>  and not fail if DT device is not protected by IOMMU
>  -add chained call to sci_do_domctl() to do_domctl()
> 
> Patch 9 - xen/arm: scmi: introduce SCI SCMI SMC multi-agent driver
> - added "scmi-secondary-agents" and "#scmi-secondary-agent-cells"
>   property to "xen,config" node in "chosen" to inform SCI SCMI
>   multi-agent driver about available agents and their
>   configuration. It defines  to  map.
>   This option is Xen specific as Xen is the only one entry in the
>   system which need to know about SCMI multi-agent support and configuration.
> - each guest using SCMI should be configured with SCMI agent_id, so SCMI
>   FW can implement Agent-specific permission policy.
>   -- dom0: dom0_scmi_agent_id= in Xen command line option
>   -- toolstack: arm_sci = "type=scmi_smc_multiagent,agent_id="
>   -- dom0less: "xen,sci_type", "xen,sci_agent_id" properties in
> "xen,domain" nodes.
> - factored out SCMI generic definitions (re-usable)
> - factored out SCMI shmem code (re-usable)
> - the SCMI passthrough configuration for guest domains is similar to any other
> HW passthrough cfg.
> 
> Patch 10 - docs: arm: add SCI SCMI SMC multi-agent driver docs
> - add SCI SCMI SMC multi-agent driver documentation.
> 
> Add separate SCMI DT node for Xen management agent under "xen,config"
> node under chosen.
> 
> All Xen-specific configuration provided under "/chosen" node. This
> approach allows to isolate modifications to Host DT only under
> "/chosen" node.
> 
> This approach provides the following device tree (DT)
> parameters (placed under xen,config node):
> 
> - "scmi-secondary-agents": A Xen-specific parameter under the
>   "/chosen" node, which describes the SCMI agent configuration for
>   the domains.
> - the SCMI configuration for Xen (privileged agent) and the shared
>   memory configuration for all agents are provided under the "/chosen"
>   node and are used strictly by Xen for its initial configuration.
> - the scmi_shm and SCMI configuration for Dom0 are placed in the
>   "/firmware/scmi" node so that they can be moved to Dom0 without
>   any changes.
> 
> This configuration allows the use of Xen-specific nodes to provide
> information strictly needed by Xen while using the default SCMI
> configuration for Dom0 and other domains. As a result, no additional
> bindings need to be introduced to the device tree.
> This simplifies the Xen SCMI multi-agent configuration and utilizes
> generic device tree bindings for the domains.
> 
> NOTE: Haven't added RB tags for patch 1 and 2 because rebase and some
> minor changes were done.
> 
> Code can be found at:
> https://github.com/oleksiimoisieiev/xen/tree/scmi_upstrv5
> 
> [1] RFC v2:
> http://patchwork.kernel.org/project/xen-devel/cover/cover.1644341635.git.oleksii_moisieiev@epam.com/
> [2] RFC v3:
> https://patchwork.kernel.org/project/xen-devel/patch/20250311111618.1850927-1-grygorii_strashko@epam.com
> SCMI spec:
> https://developer.arm.com/documentation/den0056/e/?lang=en
> 
> SCMI bindings:
> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml
> 
> Reference EL3 FW:
> RPI5: https://github.com/xen-troops/arm-trusted-firmware/commits/rpi5_dev/
> Renesas v4h:
> https://github.com/GrygiriiS/arm-trusted-firmware/commits/rcar_gen4_v2.7_v4x-scmi_upd/
> 
> base-commit: dbe60f244c (Update Xen to 4.21, 2025-02-21)
> 
> Changes in v5:
> - update Maintainers file. Set role as a Reviewer
> - rebased on the latest master branch
> - Introduce arch_handle_passthrough_prop call to handle arm specific nodes
> - rename dom0_scmi_smc_passthrough to scmi_smc_passthrough
> - rename dom0_scmi_smc_passthrough in documentation
> - set error code to -ENXIO when iommu is disabled
> - return -EINVAL if mediator without assign_dt_device was provided
> - invert return code check for iommu_do_domctl in
> XEN_DOMCTL_assign_device domctl processing to make cleaner code
> - change -ENOTSUPP error code to -ENXIO in sci_do_domctl
> - handle -ENXIO return comde of iommu_do_domctl
> - leave !dt_device_is_protected check in iommu_do_dt_domctl to make
> code work the same way it's done in "handle_device" call while
> creating hwdom(dom0) and "handle_passthrough_prop" call for dom0less
> creation
> - drop return check from sci_assign_dt_device call as not needed
> - do not return EINVAL when addign_dt_device is not set. That is
> because this callback is optional and not implemented in single-agent driver
> - move memcpy_toio/fromio to the generic place
> - fix device-tree example format in booting.txt, added ";" after "}".
> - update define in scmi-proto.h
> - update define in scmi-shmem.h file
> - scmi_assign_device - do not ignore -EOPNOTSUPP return
> code of the do_smc_xfer
> - remove overwriting agent_channel->agent_id after
> SCMI_BASE_DISCOVER_AGENT call
> - add multi-agent files to the MAINTAINERS
> - add SCMI multi-agent description to the SUPPORT.md
> - handle ARM_SMCCC_INVALID_PARAMETER return code and return -EINVAL
> for smc call
> - updated collect_agents function. Set agent_id parameter as optional
> in scmi-secondary-agents device-tree property
> - introduce "#scmi-secondary-agents-cells" parameter to set if
> agent_id was provided
> - reanme xen,scmi-secondary-agents property to scmi-secondary-agents
> - move memcpu_toio/fromio for the generic place
> - update Xen to get management channel from /chosen/xen,config node
> - get hypervisor channnel from node instead of using hardcoded
> - update handling scmi and shmem nodes for the domain
> - Set multi-agent driver to support only Arm64
> - rework multi-agent driver to leave Host Device-tree unmodified
> 
> Changes in v4:
> - fix SPDX-License
> - rename DEVICE_ARM_SCI DT device class to FIRMWARE_DEVICE
> - move XEN_DOMCTL_assign_device code in separate patch
> - Add documentation for SCI SCMI drivers
> - xl.cfg doc
> - fix comments from Stefano Stabellini
> - fix toolstack code as sugested by Anthony PERARD
>   - use MATCH_OPTION()
>   - move arm_sci struct and cfg params in "arch_arm"
> - add SCMI passthrough for dom0less case
> - toolstack comments from Anthony PERARD
> - added dom0less support
> - added doc for "xen,scmi-secondary-agents"
> 
> Grygorii Strashko (5):
>   xen/arm: scmi-smc: update to be used under sci subsystem
>   xen/arm: scmi-smc: passthrough SCMI SMC to domain, single agent
>   docs: arm: add docs for SCMI over SMC calls forwarding driver
>   xen/domctl: extend XEN_DOMCTL_assign_device to handle not only iommu
>   docs: arm: add SCI SCMI SMC multi-agent driver docs
> 
> Oleksii Moisieiev (5):
>   xen/arm: add generic SCI subsystem
>   drivers: iommu: change error code when iommu is disabled
>   xen: arm: smccc: add INVALID_PARAMETER error code
>   lib/arm: Add I/O memory copy helpers
>   xen/arm: scmi: introduce SCI SCMI SMC multi-agent driver
> 
>  MAINTAINERS                                   |  10 +
>  SUPPORT.md                                    |  11 +
>  .../arm/firmware/arm-scmi.rst                 | 516 +++++++++++
>  docs/hypervisor-guide/arm/index.rst           |   9 +
>  docs/hypervisor-guide/index.rst               |   1 +
>  docs/man/xl.cfg.5.pod.in                      |  47 +
>  docs/misc/arm/device-tree/booting.txt         | 103 +++
>  docs/misc/xen-command-line.pandoc             |  18 +
>  tools/include/libxl.h                         |   5 +
>  tools/libs/light/libxl_arm.c                  |  18 +
>  tools/libs/light/libxl_types.idl              |  12 +
>  tools/xl/xl_parse.c                           |  48 ++
>  xen/arch/arm/device.c                         |   5 +
>  xen/arch/arm/dom0less-build.c                 |  51 ++
>  xen/arch/arm/domain.c                         |  12 +-
>  xen/arch/arm/domain_build.c                   |  11 +-
>  xen/arch/arm/firmware/Kconfig                 |  37 +-
>  xen/arch/arm/firmware/Makefile                |   2 +
>  xen/arch/arm/firmware/sci.c                   | 189 +++++
>  xen/arch/arm/firmware/scmi-proto.h            | 164 ++++
>  xen/arch/arm/firmware/scmi-shmem.c            | 112 +++
>  xen/arch/arm/firmware/scmi-shmem.h            |  45 +
>  xen/arch/arm/firmware/scmi-smc-multiagent.c   | 803 ++++++++++++++++++
>  xen/arch/arm/firmware/scmi-smc.c              | 191 ++++-
>  xen/arch/arm/include/asm/domain.h             |   5 +
>  xen/arch/arm/include/asm/firmware/sci.h       | 214 +++++
>  xen/arch/arm/include/asm/firmware/scmi-smc.h  |  41 -
>  xen/arch/arm/include/asm/smccc.h              |   1 +
>  xen/arch/arm/vsmc.c                           |   4 +-
>  xen/common/device-tree/dom0less-build.c       |   4 +
>  xen/common/domctl.c                           |  19 +
>  xen/drivers/passthrough/device_tree.c         |   6 +
>  xen/drivers/passthrough/iommu.c               |   2 +-
>  xen/include/asm-generic/device.h              |   1 +
>  xen/include/asm-generic/dom0less-build.h      |   9 +
>  xen/include/public/arch-arm.h                 |   8 +
>  xen/include/xen/lib/arm/io.h                  |  15 +
>  xen/lib/Makefile                              |   1 +
>  xen/lib/arm/Makefile                          |   1 +
>  xen/lib/arm/io.c                              |  80 ++
>  40 files changed, 2744 insertions(+), 87 deletions(-)
>  create mode 100644 docs/hypervisor-guide/arm/firmware/arm-scmi.rst
>  create mode 100644 docs/hypervisor-guide/arm/index.rst
>  create mode 100644 xen/arch/arm/firmware/sci.c
>  create mode 100644 xen/arch/arm/firmware/scmi-proto.h
>  create mode 100644 xen/arch/arm/firmware/scmi-shmem.c
>  create mode 100644 xen/arch/arm/firmware/scmi-shmem.h
>  create mode 100644 xen/arch/arm/firmware/scmi-smc-multiagent.c
>  create mode 100644 xen/arch/arm/include/asm/firmware/sci.h
>  delete mode 100644 xen/arch/arm/include/asm/firmware/scmi-smc.h
>  create mode 100644 xen/include/xen/lib/arm/io.h
>  create mode 100644 xen/lib/arm/Makefile
>  create mode 100644 xen/lib/arm/io.c
> 
> -- 
> 2.34.1
> 


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CC: "xen-devel@lists.xenproject.org" , Mykola
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Subject: Re: [PATCH v5 04/12] xen/arm: Prevent crash during
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Thread-Topic: [PATCH v5 04/12] xen/arm: Prevent crash during
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Hi Mykola,

Mykola Kvach  writes:

While I approve the change, the commit message is somewhat
unclear. Maybe "Don't release IRQs on suspend" will be better?

> From: Mykola Kvach 
>
> If we call disable_nonboot_cpus on ARM64 with system_state set
> to SYS_STATE_suspend, the following assertion will be triggered:
>
> ```
> (XEN) [   25.582712] Disabling non-boot CPUs ...
> (XEN) [   25.587032] Assertion '!in_irq() && (local_irq_is_enabled() || n=
um_online_cpus() <=3D 1)' failed at common/xmalloc_tlsf.c:714
> [...]
> (XEN) [   25.975069] Xen call trace:
> (XEN) [   25.978353]    [<00000a000022e098>] xfree+0x130/0x1a4 (PC)
> (XEN) [   25.984314]    [<00000a000022e08c>] xfree+0x124/0x1a4 (LR)
> (XEN) [   25.990276]    [<00000a00002747d4>] release_irq+0xe4/0xe8
> (XEN) [   25.996152]    [<00000a0000278588>] time.c#cpu_time_callback+0x4=
4/0x60
> (XEN) [   26.003150]    [<00000a000021d678>] notifier_call_chain+0x7c/0xa=
0
> (XEN) [   26.009717]    [<00000a00002018e0>] cpu.c#cpu_notifier_call_chai=
n+0x24/0x48
> (XEN) [   26.017148]    [<00000a000020192c>] cpu.c#_take_cpu_down+0x28/0x=
34
> (XEN) [   26.023801]    [<00000a0000201944>] cpu.c#take_cpu_down+0xc/0x18
> (XEN) [   26.030281]    [<00000a0000225c5c>] stop_machine.c#stopmachine_a=
ction+0xbc/0xe4
> (XEN) [   26.038057]    [<00000a00002264bc>] tasklet.c#do_tasklet_work+0x=
b8/0x100
> (XEN) [   26.045229]    [<00000a00002268a4>] do_tasklet+0x68/0xb0
> (XEN) [   26.051018]    [<00000a000026e120>] domain.c#idle_loop+0x7c/0x19=
4
> (XEN) [   26.057585]    [<00000a0000277e30>] start_secondary+0x21c/0x220
> (XEN) [   26.063978]    [<00000a0000361258>] 00000a0000361258
> ```
>
> This happens because before invoking take_cpu_down via the stop_machine_r=
un
> function on the target CPU, stop_machine_run requests
> the STOPMACHINE_DISABLE_IRQ state on that CPU. Releasing memory in
> the release_irq function then triggers the assertion:
>
> /*
>  * Heap allocations may need TLB flushes which may require IRQs to be
>  * enabled (except when only 1 PCPU is online).
>  */
>
> This patch adds system state checks to guard calls to request_irq
> and release_irq. These calls are now skipped when system_state is
> SYS_STATE_{resume,suspend}, preventing unsafe operations during
> suspend/resume handling.

If any call to release_irq() during suspend will trigger ASSERT, and it
is fine to leave IRQs as is during suspend, maybe it will be easier to
put

+        if ( system_state =3D=3D SYS_STATE_suspend )
+            return;

straight into release_irq() code? This will be easier than playing
whack-a-mole when some other patch will add another release_irq() call
somewhere.


>
> Signed-off-by: Mykola Kvach 
> ---
> Changes in V4:
>   - removed the prior tasklet-based workaround in favor of a more
>     straightforward and safer solution
>   - reworked the approach by adding explicit system state checks around
>     request_irq and release_irq calls, skips these calls during suspend
>     and resume states to avoid unsafe memory operations when IRQs are
>     disabled
> ---
>  xen/arch/arm/gic.c           |  6 ++++++
>  xen/arch/arm/tee/ffa_notif.c |  2 +-
>  xen/arch/arm/time.c          | 18 ++++++++++++------
>  3 files changed, 19 insertions(+), 7 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index a018bd7715..9856cb1592 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -388,6 +388,9 @@ void gic_dump_info(struct vcpu *v)
> =20
>  void init_maintenance_interrupt(void)
>  {
> +    if ( system_state =3D=3D SYS_STATE_resume )
> +        return;
> +
>      request_irq(gic_hw_ops->info->maintenance_irq, 0, maintenance_interr=
upt,
>                  "irq-maintenance", NULL);
>  }
> @@ -461,6 +464,9 @@ static int cpu_gic_callback(struct notifier_block *nf=
b,
>      switch ( action )
>      {
>      case CPU_DYING:
> +        if ( system_state =3D=3D SYS_STATE_suspend )
> +            break;
> +
>          /* This is reverting the work done in init_maintenance_interrupt=
 */
>          release_irq(gic_hw_ops->info->maintenance_irq, NULL);
>          break;
> diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.c
> index 00efaf8f73..06f715a82b 100644
> --- a/xen/arch/arm/tee/ffa_notif.c
> +++ b/xen/arch/arm/tee/ffa_notif.c
> @@ -347,7 +347,7 @@ void ffa_notif_init_interrupt(void)
>  {
>      int ret;
> =20
> -    if ( notif_enabled && notif_sri_irq < NR_GIC_SGI )
> +    if ( notif_enabled && notif_sri_irq < NR_GIC_SGI && system_state !=
=3D SYS_STATE_resume )
>      {
>          /*
>           * An error here is unlikely since the primary CPU has already
> diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
> index ad984fdfdd..b2e07ade43 100644
> --- a/xen/arch/arm/time.c
> +++ b/xen/arch/arm/time.c
> @@ -320,10 +320,13 @@ void init_timer_interrupt(void)
>      WRITE_SYSREG(CNTHCTL_EL2_EL1PCTEN, CNTHCTL_EL2);
>      disable_physical_timers();
> =20
> -    request_irq(timer_irq[TIMER_HYP_PPI], 0, htimer_interrupt,
> -                "hyptimer", NULL);
> -    request_irq(timer_irq[TIMER_VIRT_PPI], 0, vtimer_interrupt,
> -                   "virtimer", NULL);
> +    if ( system_state !=3D SYS_STATE_resume )
> +    {
> +        request_irq(timer_irq[TIMER_HYP_PPI], 0, htimer_interrupt,
> +                    "hyptimer", NULL);
> +        request_irq(timer_irq[TIMER_VIRT_PPI], 0, vtimer_interrupt,
> +                    "virtimer", NULL);
> +    }
> =20
>      check_timer_irq_cfg(timer_irq[TIMER_HYP_PPI], "hypervisor");
>      check_timer_irq_cfg(timer_irq[TIMER_VIRT_PPI], "virtual");
> @@ -338,8 +341,11 @@ static void deinit_timer_interrupt(void)
>  {
>      disable_physical_timers();
> =20
> -    release_irq(timer_irq[TIMER_HYP_PPI], NULL);
> -    release_irq(timer_irq[TIMER_VIRT_PPI], NULL);
> +    if ( system_state !=3D SYS_STATE_suspend )
> +    {
> +        release_irq(timer_irq[TIMER_HYP_PPI], NULL);
> +        release_irq(timer_irq[TIMER_VIRT_PPI], NULL);
> +    }
>  }
> =20
>  /* Wait a set number of microseconds */

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mykola
 Kvach , Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel 
Subject: Re: [PATCH v5 05/12] xen/arm: irq: avoid local IRQ descriptors reinit
 on system resume
Thread-Topic: [PATCH v5 05/12] xen/arm: irq: avoid local IRQ descriptors
 reinit on system resume
Thread-Index: AQHcCwFcU6YHlfOU1EaGDcY/uk86oQ==
Date: Sat, 23 Aug 2025 00:37:45 +0000
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References: 
	<7686bc019f0c0eff94720e4ca16e00f895819087.1754943874.git.mykola_kvach@epam.com>
In-Reply-To:
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	(Mykola Kvach's message of "Mon, 11 Aug 2025 23:48:01 +0300")
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Mykola Kvach  writes:

> From: Mykola Kvach 
>
> On ARM, during system resume, CPUs are brought online again. This normall=
y
> triggers init_local_irq_data, which reinitializes IRQ descriptors for
> banked interrupts (SGIs and PPIs).
>
> These descriptors are statically allocated per CPU and retain valid
> state across suspend/resume cycles. Re-initializing them on resume is
> unnecessary and may result in loss of interrupt configuration or
> restored state.
>
> This patch skips init_local_irq_data when system_state is set to
> SYS_STATE_resume to preserve banked IRQ descs state during resume.
>
> Signed-off-by: Mykola Kvach 

Reviewed-by: Volodymyr Babchuk 

> ---
>  xen/arch/arm/irq.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 4bbf0b0664..148f184f8b 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -122,6 +122,10 @@ static int cpu_callback(struct notifier_block *nfb, =
unsigned long action,
>      switch ( action )
>      {
>      case CPU_UP_PREPARE:
> +        /* Skip local IRQ cleanup on resume */
> +        if ( system_state =3D=3D SYS_STATE_resume )
> +            break;
> +
>          rc =3D init_local_irq_data(cpu);
>          if ( rc )
>              printk(XENLOG_ERR "Unable to allocate local IRQ for CPU%u\n"=
,

--=20
WBR, Volodymyr=


From xen-devel-bounces@lists.xenproject.org Sat Aug 23 00:40:12 2025
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Date: Fri, 22 Aug 2025 17:40:00 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 08/10] lib/arm: Add I/O memory copy helpers
In-Reply-To: <6df9b5bbeae12a74397d72d53c530313f0778025.1753184487.git.oleksii_moisieiev@epam.com>
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On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> This commit introduces two helper functions, `__memcpy_fromio` and
> `__memcpy_toio`, to provide a robust mechanism for copying data between
> standard memory and memory-mapped I/O (MMIO) space for the ARM
> architecture.
> 
> These functions are designed to handle memory transfers safely,
> accounting for potential address alignment issues to ensure correctness
> and improve performance where possible. The implementation is specific
> to ARM and uses relaxed I/O accessors.
> 
> __memcpy_fromio:
> Copies a block of data from an I/O memory source to a destination in
> standard ("real") memory. The implementation first handles any unaligned
> bytes at the beginning of the source buffer individually using byte-wise
> reads. It then copies the bulk of the data using 32-bit reads for
> efficiency, and finally processes any remaining bytes at the end of the
> buffer.
> 
> __memcpy_toio:
> Copies a block of data from standard memory to a destination in I/O
> memory space. It follows a similar strategy, handling any initial
> unaligned portion of the destination buffer byte-by-byte before using
> more efficient 32-bit writes for the main, aligned part of the transfer.
> Any trailing bytes are also handled individually.
> xen/include/xen/lib/arm/io.h
> 
> Signed-off-by: Oleksii Moisieiev 
> ---
> 
> Changes in v5:
> - move memcpy_toio/fromio to the generic place
> 
>  xen/include/xen/lib/arm/io.h | 15 +++++++
>  xen/lib/Makefile             |  1 +
>  xen/lib/arm/Makefile         |  1 +
>  xen/lib/arm/io.c             | 80 ++++++++++++++++++++++++++++++++++++
>  4 files changed, 97 insertions(+)
>  create mode 100644 xen/include/xen/lib/arm/io.h
>  create mode 100644 xen/lib/arm/Makefile
>  create mode 100644 xen/lib/arm/io.c
> 
> diff --git a/xen/include/xen/lib/arm/io.h b/xen/include/xen/lib/arm/io.h
> new file mode 100644
> index 0000000000..86973660ba
> --- /dev/null
> +++ b/xen/include/xen/lib/arm/io.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +#ifndef _XEN_LIB_ARM_IO_H
> +#define _XEN_LIB_ARM_IO_H
> +
> +#include 
> +
> +/*
> + * Prototypes for I/O memory access functions.
> + */
> +extern void __memcpy_fromio(void *to, const volatile void __iomem *from,
> +                     size_t count);
> +extern void __memcpy_toio(volatile void __iomem *to, const void *from,
> +                   size_t count);
> +
> +#endif /* _XEN_LIB_ARM_IO_H */
> diff --git a/xen/lib/Makefile b/xen/lib/Makefile
> index 5ccb1e5241..efa8157a72 100644
> --- a/xen/lib/Makefile
> +++ b/xen/lib/Makefile
> @@ -1,4 +1,5 @@
>  obj-$(CONFIG_X86) += x86/
> +obj-$(CONFIG_ARM) += arm/
>  
>  lib-y += bsearch.o
>  lib-y += ctors.o
> diff --git a/xen/lib/arm/Makefile b/xen/lib/arm/Makefile
> new file mode 100644
> index 0000000000..87250b3822
> --- /dev/null
> +++ b/xen/lib/arm/Makefile
> @@ -0,0 +1 @@
> +obj-y += io.o
> \ No newline at end of file
> diff --git a/xen/lib/arm/io.c b/xen/lib/arm/io.c
> new file mode 100644
> index 0000000000..d267bd28e4
> --- /dev/null
> +++ b/xen/lib/arm/io.c
> @@ -0,0 +1,80 @@
> +#include 
> +#include 

Please add the SPDX tag


> +/*
> + * memcpy_fromio - Copy data from IO memory space to "real" memory space.
> + * @to: Where to copy to
> + * @from: Where to copy from
> + * @count: The size of the area.
> + */
> +void __memcpy_fromio(void *to, const volatile void __iomem *from,
> +                     size_t count)
> +{
> +    while ( count && !IS_ALIGNED((unsigned long)from, 4) )
> +    {
> +        *(u8 *)to = readb_relaxed(from);
> +        from++;
> +        to++;
> +        count--;
> +    }
> +
> +    while ( count >= 4 )
> +    {
> +        *(u32 *)to = readl_relaxed(from);
> +        from += 4;
> +        to += 4;
> +        count -= 4;
> +    }
> +
> +    while ( count )
> +    {
> +        *(u8 *)to = readb_relaxed(from);
> +        from++;
> +        to++;
> +        count--;
> +    }
> +}
> +
> +/*
> + * memcpy_toio - Copy data from "real" memory space to IO memory space.
> + * @to: Where to copy to
> + * @from: Where to copy from
> + * @count: The size of the area.
> + */
> +void __memcpy_toio(volatile void __iomem *to, const void *from,
> +                   size_t count)
> +{
> +    while ( count && !IS_ALIGNED((unsigned long)to, 4) )
> +    {
> +        writeb_relaxed(*(u8 *)from, to);
> +        from++;
> +        to++;
> +        count--;
> +    }
> +
> +    while ( count >= 4 )
> +    {
> +        writel_relaxed(*(u32 *)from, to);
> +        from += 4;
> +        to += 4;
> +        count -= 4;
> +    }
> +
> +    while ( count )
> +    {
> +        writeb_relaxed(*(u8 *)from, to);
> +        from++;
> +        to++;
> +        count--;
> +    }
> +}
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 8
> + * tab-width: 8
> + * indent-tabs-mode: t
> + * End:
> + */
> -- 
> 2.34.1
> 


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mykola
 Kvach , Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel 
Subject: Re: [PATCH v5 06/12] xen/arm: irq: Restore state of local IRQs during
 system resume
Thread-Topic: [PATCH v5 06/12] xen/arm: irq: Restore state of local IRQs
 during system resume
Thread-Index: AQHcCwFdbnxcOkUsNEeOVZH7G9fkwg==
Date: Sat, 23 Aug 2025 00:45:50 +0000
Message-ID: <877byuamrm.fsf@epam.com>
References: 
	<779a90853f249f8d8c4973874baeee1f787e92e0.1754943875.git.mykola_kvach@epam.com>
In-Reply-To:
 <779a90853f249f8d8c4973874baeee1f787e92e0.1754943875.git.mykola_kvach@epam.com>
	(Mykola Kvach's message of "Mon, 11 Aug 2025 23:48:02 +0300")
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Hi Mykola,

Mykola Kvach  writes:

> From: Mykola Kvach 
>
> On ARM, the first 32 interrupts (SGIs and PPIs) are banked per-CPU
> and not restored by gic_resume (for secondary cpus).
>
> This patch introduces restore_local_irqs_on_resume, a function that
> restores the state of local interrupts on the target CPU during
> system resume.
>
> It iterates over all local IRQs and re-enables those that were not
> disabled, reprogramming their routing and affinity accordingly.
>
> The function is invoked from start_secondary, ensuring that local IRQ
> state is restored early during CPU bring-up after suspend.
>
> Signed-off-by: Mykola Kvach 
> ---
>  xen/arch/arm/irq.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 148f184f8b..b3ff38dc27 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -113,6 +113,47 @@ static int init_local_irq_data(unsigned int cpu)
>      return 0;
>  }
> =20
> +/*
> + * The first 32 interrupts (PPIs and SGIs) are per-CPU,
> + * so call this function on the target CPU to restore them.
> + *
> + * SPIs are restored via gic_resume.
> + */
> +static void restore_local_irqs_on_resume(void)
> +{
> +    int irq;
> +
> +    if ( system_state !=3D SYS_STATE_resume )
> +        return;

Maybe it is better to move this check to restore_local_irqs_on_resume()
caller? You can put ASSERT(system_state =3D=3D SYS_STATE_resume) there
instead.

I am saying this because name of restore_local_irqs_on_resume() implies tha=
t it
should be called only on resume.

> +
> +    spin_lock(&local_irqs_type_lock);
> +
> +    for ( irq =3D 0; irq < NR_LOCAL_IRQS; irq++ )
> +    {
> +        struct irq_desc *desc =3D irq_to_desc(irq);
> +
> +        spin_lock(&desc->lock);
> +
> +        if ( test_bit(_IRQ_DISABLED, &desc->status) )
> +        {
> +            spin_unlock(&desc->lock);
> +            continue;
> +        }
> +
> +        /* it is needed to avoid asserts in below calls */
> +        set_bit(_IRQ_DISABLED, &desc->status);

Assert in the call below isn't just because. You need to either call
desc->handler->disable() to properly disable the IRQ or justify why it
is fine to just set the bit.

> +
> +        gic_route_irq_to_xen(desc, GIC_PRI_IRQ);
> +
> +        /* _IRQ_DISABLED is cleared by below call */
> +        desc->handler->startup(desc);
> +
> +        spin_unlock(&desc->lock);
> +    }
> +
> +    spin_unlock(&local_irqs_type_lock);
> +}
> +
>  static int cpu_callback(struct notifier_block *nfb, unsigned long action=
,
>                          void *hcpu)
>  {
> @@ -131,6 +172,9 @@ static int cpu_callback(struct notifier_block *nfb, u=
nsigned long action,
>              printk(XENLOG_ERR "Unable to allocate local IRQ for CPU%u\n"=
,
>                     cpu);
>          break;
> +    case CPU_STARTING:
> +        restore_local_irqs_on_resume();
> +        break;
>      }
> =20
>      return notifier_from_errno(rc);

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Jan Beulich 
CC: Mykola Kvach , Stefano Stabellini
	, Mirela Simonovic ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Andrew Cooper
	, Anthony PERARD ,
	=?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Saeed Nowshadi
	, Mykyta Poturai , Mykola
 Kvach , "xen-devel@lists.xenproject.org"
	
Subject: Re: [PATCH v5 07/12] xen/arm: Add support for system suspend
 triggered by hardware domain
Thread-Topic: [PATCH v5 07/12] xen/arm: Add support for system suspend
 triggered by hardware domain
Thread-Index: AQHcCwFfU+9GQNRu4k2nrD5uWqCz7A==
Date: Sat, 23 Aug 2025 00:53:14 +0000
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Hi Jan,

Jan Beulich  writes:

> On 11.08.2025 22:48, Mykola Kvach wrote:
>> --- a/xen/common/domain.c
>> +++ b/xen/common/domain.c
>> @@ -1311,7 +1311,11 @@ int domain_shutdown(struct domain *d, u8 reason)
>>          d->shutdown_code =3D reason;
>>      reason =3D d->shutdown_code;
>> =20
>> +#if defined(CONFIG_SYSTEM_SUSPEND) && defined(CONFIG_ARM)
>> +    if ( reason !=3D SHUTDOWN_suspend && is_hardware_domain(d) )
>> +#else
>>      if ( is_hardware_domain(d) )
>> +#endif
>>          hwdom_shutdown(reason);
>
> There better wouldn't be any #ifdef here. Afaict you can easily use
> IS_ENABLED(CONFIG_SYSTEM_SUSPEND). For CONFIG_ARM, though, I think some
> new abstraction will need adding. E.g. HAS_HWDOM_SUSPEND (with want for
> a better, yet not overly long name).
>
> With the hwdom / ctldom separation work in mind I wonder though if it's
> really hwdom to be in charge of initiating system suspend. Imo
> conceptually that rather would want to be ctldom. Stefano?

I am not Stefano, but IMO, this should be ctldom. But only after hwdom
is already suspended, otherwise we'll have problems with devices.

It is unclear which entity should check if hwdom is already suspended,
though. Should be it be ctldom or Xen itself?

And if we already speaking of devices... There can be domains with
passed-through devices. Those domains should be suspended properly, not
just freezed. I think this requires another TODO.

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mirela
 Simonovic , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Andrew
 Cooper , Anthony PERARD
	, Jan Beulich ,
	=?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Saeed Nowshadi
	, Mykyta Poturai , Mykola
 Kvach 
Subject: Re: [PATCH v5 07/12] xen/arm: Add support for system suspend
 triggered by hardware domain
Thread-Topic: [PATCH v5 07/12] xen/arm: Add support for system suspend
 triggered by hardware domain
Thread-Index: AQHcCwFfU+9GQNRu4k2nrD5uWqCz7A==
Date: Sat, 23 Aug 2025 01:00:11 +0000
Message-ID: <87ms7q97j9.fsf@epam.com>
References: 
	
In-Reply-To:
 
	(Mykola Kvach's message of "Mon, 11 Aug 2025 23:48:03 +0300")
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Hi Mykola,

Mykola Kvach  writes:

> From: Mirela Simonovic 
>
> Trigger Xen suspend when the hardware domain initiates suspend via
> SHUTDOWN_suspend. Redirect system suspend to CPU#0 to ensure the
> suspend logic runs on the boot CPU, as required.
>
> Introduce full suspend/resume infrastructure gated by CONFIG_SYSTEM_SUSPE=
ND,
> including logic to:
>  - disable and enable non-boot physical CPUs
>  - freeze and thaw domains
>  - suspend and resume the GIC, timer and console
>  - maintain system state before and after suspend
>
> Remove the restriction in the PSCI interface preventing suspend from the
> hardware domain.
>
> Select HAS_SYSTEM_SUSPEND for ARM_64.
>
> Signed-off-by: Mirela Simonovic 
> Signed-off-by: Saeed Nowshadi 
> Signed-off-by: Mykyta Poturai 
> Signed-off-by: Mykola Kvach 
> ---
> Changes in v5:
> - select HAS_SYSTEM_SUSPEND in ARM_64 instead of ARM
> - check llc_coloring_enabled instead of LLC_COLORING during the selection
>   of HAS_SYSTEM_SUSPEND config
> - call host_system_suspend from guest PSCI system suspend instead of
>   arch_domain_shutdown, reducing the complexity of the new code
> - update some comments
>
> Changes introduced in V4:
>   - drop code for saving and restoring VCPU context (for more information
>     refer part 1 of patch series)
>   - remove IOMMU suspend and resume calls until they will be implemented
>   - move system suspend logic to arch_domain_shutdown, invoked from
>     domain_shutdown
>   - apply minor fixes such as renaming functions, updating comments, and
>     modifying the commit message to reflect these changes
>   - add console_end_sync to resume path after system suspend
>
> Changes introduced in V3:
>   - merge changes from other commits into this patch (previously stashed)=
:
>     1) disable/enable non-boot physical CPUs and freeze/thaw domains duri=
ng
>        suspend/resume
>     2) suspend/resume the timer, GIC, console, IOMMU, and hardware domain
> ---
>  xen/arch/arm/Kconfig               |   1 +
>  xen/arch/arm/Makefile              |   1 +
>  xen/arch/arm/include/asm/suspend.h |  22 +++++
>  xen/arch/arm/suspend.c             | 151 +++++++++++++++++++++++++++++
>  xen/arch/arm/vpsci.c               |  12 ++-
>  xen/common/domain.c                |   4 +
>  6 files changed, 190 insertions(+), 1 deletion(-)
>  create mode 100644 xen/arch/arm/include/asm/suspend.h
>  create mode 100644 xen/arch/arm/suspend.c
>
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index a0c8160474..ccdbaa5bc3 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -8,6 +8,7 @@ config ARM_64
>  	depends on !ARM_32
>  	select 64BIT
>  	select HAS_FAST_MULTIPLY
> +	select HAS_SYSTEM_SUSPEND if UNSUPPORTED
>  	select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH
> =20
>  config ARM
> diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
> index f833cdf207..3f6247adee 100644
> --- a/xen/arch/arm/Makefile
> +++ b/xen/arch/arm/Makefile
> @@ -51,6 +51,7 @@ obj-y +=3D setup.o
>  obj-y +=3D shutdown.o
>  obj-y +=3D smp.o
>  obj-y +=3D smpboot.o
> +obj-$(CONFIG_SYSTEM_SUSPEND) +=3D suspend.o
>  obj-$(CONFIG_SYSCTL) +=3D sysctl.o
>  obj-y +=3D time.o
>  obj-y +=3D traps.o
> diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/as=
m/suspend.h
> new file mode 100644
> index 0000000000..78d0e2383b
> --- /dev/null
> +++ b/xen/arch/arm/include/asm/suspend.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __ASM_ARM_SUSPEND_H__
> +#define __ASM_ARM_SUSPEND_H__
> +
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +
> +int host_system_suspend(void);
> +
> +#endif /* CONFIG_SYSTEM_SUSPEND */
> +
> +#endif /* __ASM_ARM_SUSPEND_H__ */
> +
> + /*
> +  * Local variables:
> +  * mode: C
> +  * c-file-style: "BSD"
> +  * c-basic-offset: 4
> +  * tab-width: 4
> +  * indent-tabs-mode: nil
> +  * End:
> +  */
> diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
> new file mode 100644
> index 0000000000..abf4b928ce
> --- /dev/null
> +++ b/xen/arch/arm/suspend.c
> @@ -0,0 +1,151 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/*
> + * TODO list:
> + *  - Test system suspend with LLC_COLORING enabled and verify functiona=
lity
> + *  - Implement IOMMU suspend/resume handlers and integrate them
> + *    into the suspend/resume path (IPMMU and SMMU)
> + *  - Enable "xl suspend" support on ARM architecture
> + *  - Properly disable Xen timer watchdog from relevant services
> + *  - Add suspend/resume CI test for ARM (QEMU if feasible)
> + *  - Investigate feasibility and need for implementing system suspend o=
n ARM32
> + */
> +
> +/* Xen suspend. Note: data is not used (suspend is the suspend to RAM) *=
/
> +static long system_suspend(void *data)
> +{
> +    int status;
> +    unsigned long flags;
> +
> +    BUG_ON(system_state !=3D SYS_STATE_active);
> +
> +    system_state =3D SYS_STATE_suspend;
> +    freeze_domains();
> +    scheduler_disable();
> +
> +    /*
> +     * Non-boot CPUs have to be disabled on suspend and enabled on resum=
e
> +     * (hotplug-based mechanism). Disabling non-boot CPUs will lead to P=
SCI
> +     * CPU_OFF to be called by each non-boot CPU. Depending on the under=
lying
> +     * platform capabilities, this may lead to the physical powering dow=
n of
> +     * CPUs. Tested on Xilinx Zynq Ultrascale+ MPSoC (including power do=
wn of
> +     * each non-boot CPU).

I don't think that the last part of the comment is relevant in upstream.

> +     */
> +    status =3D disable_nonboot_cpus();
> +    if ( status )
> +    {
> +        system_state =3D SYS_STATE_resume;
> +        goto resume_nonboot_cpus;
> +    }
> +
> +    time_suspend();
> +
> +    local_irq_save(flags);
> +    status =3D gic_suspend();
> +    if ( status )
> +    {
> +        system_state =3D SYS_STATE_resume;
> +        goto resume_irqs;
> +    }
> +
> +    printk("Xen suspending...\n");
> +
> +    console_start_sync();
> +    status =3D console_suspend();
> +    if ( status )
> +    {
> +        dprintk(XENLOG_ERR, "Failed to suspend the console, err=3D%d\n",=
 status);
> +        system_state =3D SYS_STATE_resume;
> +        goto resume_console;
> +    }
> +
> +    /*
> +     * Enable identity mapping before entering suspend to simplify
> +     * the resume path
> +     */
> +    update_boot_mapping(true);
> +

This puzzles me. I expected actually PSCI suspend call here.

> +    system_state =3D SYS_STATE_resume;
> +    update_boot_mapping(false);
> +
> + resume_console:
> +    console_resume();
> +    console_end_sync();
> +
> +    gic_resume();
> +
> + resume_irqs:
> +    local_irq_restore(flags);
> +    time_resume();
> +
> + resume_nonboot_cpus:
> +    /*
> +     * The rcu_barrier() has to be added to ensure that the per cpu area=
 is
> +     * freed before a non-boot CPU tries to initialize it (_free_percpu_=
area()
> +     * has to be called before the init_percpu_area()). This scenario oc=
curs
> +     * when non-boot CPUs are hot-unplugged on suspend and hotplugged on=
 resume.
> +     */
> +    rcu_barrier();
> +    enable_nonboot_cpus();
> +    scheduler_enable();
> +    thaw_domains();
> +
> +    system_state =3D SYS_STATE_active;
> +
> +    /* The resume of hardware domain should always follow Xen's resume. =
*/
> +    domain_resume(hardware_domain);
> +
> +    printk("Resume (status %d)\n", status);
> +    return status;
> +}
> +
> +int host_system_suspend(void)
> +{
> +    int status;
> +
> +    /* TODO: drop check after verification that features can work togeth=
er */
> +    if ( llc_coloring_enabled )
> +    {
> +        dprintk(XENLOG_ERR,
> +                "System suspend is not supported with LLC_COLORING enabl=
ed\n");
> +        return -ENOSYS;
> +    }
> +
> +    /*
> +     * system_suspend should be called when Dom0 finalizes the suspend
> +     * procedure from its boot core (VCPU#0). However, Dom0's VCPU#0 cou=
ld
> +     * be mapped to any PCPU (this function could be executed by any PCP=
U).
> +     * The suspend procedure has to be finalized by the PCPU#0 (non-boot
> +     * PCPUs will be disabled during the suspend).
> +     */
> +    status =3D continue_hypercall_on_cpu(0, system_suspend, NULL);
> +
> +    /*
> +     * If an error happened, there is nothing that needs to be done here
> +     * because the system_suspend always returns in fully functional sta=
te
> +     * no matter what the outcome of suspend procedure is. If the system
> +     * suspended successfully the function will return 0 after the resum=
e.
> +     * Otherwise, if an error is returned it means Xen did not suspended=
,
> +     * but it is still in the same state as if the system_suspend was ne=
ver
> +     * called. We dump a debug message in case of an error for debugging=
/
> +     * logging purpose.
> +     */
> +    if ( status )
> +        dprintk(XENLOG_ERR, "Failed to suspend, errno=3D%d\n", status);
> +
> +    return status;
> +}
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
> index 67d369a8a2..757e719ea7 100644
> --- a/xen/arch/arm/vpsci.c
> +++ b/xen/arch/arm/vpsci.c
> @@ -4,6 +4,7 @@
>  #include 
> =20
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -214,9 +215,10 @@ static int32_t do_psci_1_0_system_suspend(register_t=
 epoint, register_t cid)
>      struct vcpu *v;
>      struct domain *d =3D current->domain;
> =20
> -    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> +#ifndef CONFIG_SYSTEM_SUSPEND
>      if ( is_hardware_domain(d) )
>          return PSCI_NOT_SUPPORTED;
> +#endif
> =20
>      /* Ensure that all CPUs other than the calling one are offline */
>      domain_lock(d);
> @@ -234,6 +236,14 @@ static int32_t do_psci_1_0_system_suspend(register_t=
 epoint, register_t cid)
>      if ( rc )
>          return PSCI_DENIED;
> =20
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +    if ( is_hardware_domain(d) && host_system_suspend() )
> +    {
> +        domain_resume_nopause(d);
> +        return PSCI_DENIED;
> +    }
> +#endif
> +
>      rc =3D do_setup_vcpu_ctx(current, epoint, cid);
>      if ( rc !=3D PSCI_SUCCESS )
>      {
> diff --git a/xen/common/domain.c b/xen/common/domain.c
> index c3609b0cb0..414a691242 100644
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -1311,7 +1311,11 @@ int domain_shutdown(struct domain *d, u8 reason)
>          d->shutdown_code =3D reason;
>      reason =3D d->shutdown_code;
> =20
> +#if defined(CONFIG_SYSTEM_SUSPEND) && defined(CONFIG_ARM)
> +    if ( reason !=3D SHUTDOWN_suspend && is_hardware_domain(d) )
> +#else
>      if ( is_hardware_domain(d) )
> +#endif
>          hwdom_shutdown(reason);
> =20
>      if ( d->is_shutting_down )

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mirela
 Simonovic , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Saeed
 Nowshadi , Mykyta Poturai
	, Mykola Kvach 
Subject: Re: [PATCH v5 08/12] xen/arm: Implement PSCI SYSTEM_SUSPEND call
 (host interface)
Thread-Topic: [PATCH v5 08/12] xen/arm: Implement PSCI SYSTEM_SUSPEND call
 (host interface)
Thread-Index: AQHcCwFjs9ljm00LWEeeve/MOeNYjg==
Date: Sat, 23 Aug 2025 01:06:38 +0000
Message-ID: <875xee978i.fsf@epam.com>
References: 
	
In-Reply-To:
 
	(Mykola Kvach's message of "Mon, 11 Aug 2025 23:48:04 +0300")
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Hi Mykola,

Sequence of next 3 patches (and previous one) really puzzles me. Can you
first implement hyp_resume() function, then add PSCI_SYSTEM_SUSPEND call
and only then implement system_suspend() function? Why do this backwards?

Mykola Kvach  writes:

> From: Mirela Simonovic 
>
> Invoke PSCI SYSTEM_SUSPEND to finalize Xen's suspend sequence on ARM64 pl=
atforms.
> Pass the resume entry point (hyp_resume) as the first argument to EL3. Th=
e resume
> handler is currently a stub and will be implemented later in assembly. Ig=
nore the
> context ID argument, as is done in Linux.
>
> Only enable this path when CONFIG_SYSTEM_SUSPEND is set and
> PSCI version is >=3D 1.0.
>
> Signed-off-by: Mirela Simonovic 
> Signed-off-by: Saeed Nowshadi 
> Signed-off-by: Mykyta Poturai 
> Signed-off-by: Mykola Kvach 
> ---
> Changes in v4:
>   - select the appropriate PSCI SYSTEM_SUSPEND function ID based on platf=
orm
>   - update comments and commit message to reflect recent changes
>
> Changes in v3:
>   - return PSCI_NOT_SUPPORTED instead of a hardcoded 1 on ARM32
>   - check PSCI version before invoking SYSTEM_SUSPEND in call_psci_system=
_suspend
> ---
>  xen/arch/arm/arm64/head.S          |  8 ++++++++
>  xen/arch/arm/include/asm/psci.h    |  1 +
>  xen/arch/arm/include/asm/suspend.h |  2 ++
>  xen/arch/arm/psci.c                | 23 ++++++++++++++++++++++-
>  xen/arch/arm/suspend.c             |  5 +++++
>  5 files changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index 72c7b24498..3522c497c5 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -561,6 +561,14 @@ END(efi_xen_start)
> =20
>  #endif /* CONFIG_ARM_EFI */
> =20
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +
> +FUNC(hyp_resume)
> +        b .
> +END(hyp_resume)
> +
> +#endif /* CONFIG_SYSTEM_SUSPEND */
> +
>  /*
>   * Local variables:
>   * mode: ASM
> diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/p=
sci.h
> index 48a93e6b79..bb3c73496e 100644
> --- a/xen/arch/arm/include/asm/psci.h
> +++ b/xen/arch/arm/include/asm/psci.h
> @@ -23,6 +23,7 @@ int call_psci_cpu_on(int cpu);
>  void call_psci_cpu_off(void);
>  void call_psci_system_off(void);
>  void call_psci_system_reset(void);
> +int call_psci_system_suspend(void);
> =20
>  /* Range of allocated PSCI function numbers */
>  #define	PSCI_FNUM_MIN_VALUE                 _AC(0,U)
> diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/as=
m/suspend.h
> index 78d0e2383b..55041a5d06 100644
> --- a/xen/arch/arm/include/asm/suspend.h
> +++ b/xen/arch/arm/include/asm/suspend.h
> @@ -7,6 +7,8 @@
> =20
>  int host_system_suspend(void);
> =20
> +void hyp_resume(void);
> +
>  #endif /* CONFIG_SYSTEM_SUSPEND */
> =20
>  #endif /* __ASM_ARM_SUSPEND_H__ */
> diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c
> index b6860a7760..c9d126b195 100644
> --- a/xen/arch/arm/psci.c
> +++ b/xen/arch/arm/psci.c
> @@ -17,17 +17,20 @@
>  #include 
>  #include 
>  #include 
> +#include 
> =20
>  /*
>   * While a 64-bit OS can make calls with SMC32 calling conventions, for
>   * some calls it is necessary to use SMC64 to pass or return 64-bit valu=
es.
> - * For such calls PSCI_0_2_FN_NATIVE(x) will choose the appropriate
> + * For such calls PSCI_*_FN_NATIVE(x) will choose the appropriate
>   * (native-width) function ID.
>   */
>  #ifdef CONFIG_ARM_64
>  #define PSCI_0_2_FN_NATIVE(name)    PSCI_0_2_FN64_##name
> +#define PSCI_1_0_FN_NATIVE(name)    PSCI_1_0_FN64_##name
>  #else
>  #define PSCI_0_2_FN_NATIVE(name)    PSCI_0_2_FN32_##name
> +#define PSCI_1_0_FN_NATIVE(name)    PSCI_1_0_FN32_##name
>  #endif
> =20
>  uint32_t psci_ver;
> @@ -60,6 +63,24 @@ void call_psci_cpu_off(void)
>      }
>  }
> =20
> +int call_psci_system_suspend(void)
> +{
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +    struct arm_smccc_res res;
> +
> +    if ( psci_ver < PSCI_VERSION(1, 0) )
> +        return PSCI_NOT_SUPPORTED;
> +
> +    /* 2nd argument (context ID) is not used */
> +    arm_smccc_smc(PSCI_1_0_FN_NATIVE(SYSTEM_SUSPEND), __pa(hyp_resume), =
&res);
> +    return PSCI_RET(res);
> +#else
> +    dprintk(XENLOG_WARNING,
> +            "SYSTEM_SUSPEND not supported (CONFIG_SYSTEM_SUSPEND disable=
d)\n");
> +    return PSCI_NOT_SUPPORTED;
> +#endif
> +}
> +
>  void call_psci_system_off(void)
>  {
>      if ( psci_ver > PSCI_VERSION(0, 1) )
> diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
> index abf4b928ce..11e86b7f51 100644
> --- a/xen/arch/arm/suspend.c
> +++ b/xen/arch/arm/suspend.c
> @@ -1,5 +1,6 @@
>  /* SPDX-License-Identifier: GPL-2.0-only */
> =20
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -70,6 +71,10 @@ static long system_suspend(void *data)
>       */
>      update_boot_mapping(true);
> =20
> +    status =3D call_psci_system_suspend();
> +    if ( status )
> +        dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=3D%d\n"=
, status);

So this is where missing call to PSCI_SYSTEM_SUSPEND is...=20

> +
>      system_state =3D SYS_STATE_resume;
>      update_boot_mapping(false);

--=20
WBR, Volodymyr=


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Date: Sat, 23 Aug 2025 08:59:13 +0100
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User-Agent: Mozilla Thunderbird
Subject: Re: Consider changing CONFIG_ACPI default on ARM?
Content-Language: en-GB
To: Elliott Mitchell , Jan Beulich 
Cc: Demi Marie Obenour ,
 xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Paul Leiber 
References: 
 
 
 <1b96f2f3-55a2-4b33-84b1-a7c18d38d10c@suse.com>
 <6e9b5265-7a3b-4fd5-b14e-0e60a8b49833@gmail.com>
 
 
From: Julien Grall 
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Content-Transfer-Encoding: 7bit

Hi Elliott,

On 22/08/2025 21:09, Elliott Mitchell wrote:
> Since you're not pointing to anything definite, could it be everything
> has been resolved?

Unfortunately, the situation has not changed since your last thread 
about enabling CONFIG_ACPI=y a couple of years ago. The main feature we 
are lacking is the parsing the IORT (used to discover SMMUs and MSI 
controllers). Without this...

>  We've got at least two people for whom ACPI on ARM
> works pretty well.

... Xen will only properly boot on "simple" case like the Raspberry PI. 
Also, IIRC Xen would use ACPI rather than Device-Tree by default.

> There may be many more using it.  Perhaps this
> should even be done on the 4.20 branch given how long this has been
> working?

I am guessing you mean 4.21 which will be released in a couple of months 
time, correct?

We have been discussing among the committers on whether we are ok to 
enable ACPI despite the fact it is still not feature complete (see 
above). The discussion is not fully finalized but if we were to enable 
CONFIG_ACPI=y by default then I think we would need the following:

  * Select device-tree by default rather than ACPI
  * Go through SUPPORT.MD and check what features we marked as 
SUPPORTED.md but doesn't work on ACPI.

Maybe you can help with that?

Out of interest, sorry if this was already mentioned before, is there 
any reason ACPI is used on the Raspberry PI over Device-Tree? Is there 
any issue with the latter on Xen?

> 
> The one remaining major issue was the state of EFI-FB support.  There
> was a patch which had that working for Linux kernel 5.10, but that might
> need more work for a proper solution.

Yes. And there was no interest from the other members to fix it 
properly. So I gave up that on that work as I don't have a particular 
interest of using FrameBuffer on the raspberry PI. Feel free to revive 
it and I would be happy to review them.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
 virq checks
To: xen-devel@lists.xenproject.org,
 Leonid Komarianskyi 
References: <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 
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On 07.08.25 15:33, Leonid Komarianskyi wrote:

Hello Leonid


> Introduced two new helper functions for vGIC: vgic_is_valid_irq and
> vgic_is_shared_irq. The functions are similar to the newly introduced
> gic_is_valid_irq and gic_is_shared_irq, but they verify whether a vIRQ
> is available for a specific domain, while GIC-specific functions
> validate INTIDs for the real GIC hardware. For example, the GIC may
> support all 992 SPI lines, but the domain may use only some part of them
> (e.g., 640), depending on the highest IRQ number defined in the domain
> configuration. Therefore, for vGIC-related code and checks, the
> appropriate functions should be used. Also, updated the appropriate
> checks to use these new helper functions.
> 
> The purpose of introducing new helper functions for vGIC is essentially
> the same as for GIC: to avoid potential confusion with GIC-related
> checks and to consolidate similar code into separate functions, which
> can be more easily extended by additional conditions, e.g., when
> implementing extended SPI interrupts.
> 
> Only the validation change in vgic_inject_irq may affect existing
> functionality, as it currently checks whether the vIRQ is less than or
> equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
> first SPI), the check should behave consistently with similar logic in
> other places and should check if the vIRQ number is less than
> vgic_num_irqs. The remaining changes, which replace open-coded checks
> with the use of these new helper functions, do not introduce any
> functional changes, as the helper functions follow the current vIRQ
> index verification logic.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V2:
> - introduced this patch
> ---
>   xen/arch/arm/gic.c              |  3 +--
>   xen/arch/arm/include/asm/vgic.h |  7 +++++++
>   xen/arch/arm/irq.c              |  4 ++--
>   xen/arch/arm/vgic.c             | 10 ++++++++--
>   4 files changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index eb0346a898..47fccf21d8 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -133,8 +133,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq,
>   
>       ASSERT(spin_is_locked(&desc->lock));
>       /* Caller has already checked that the IRQ is an SPI */
> -    ASSERT(virq >= 32);
> -    ASSERT(virq < vgic_num_irqs(d));
> +    ASSERT(vgic_is_shared_irq(d, virq));
>       ASSERT(!is_lpi(virq));
>   
>       ret = vgic_connect_hw_irq(d, NULL, virq, desc, true);
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h
> index 35c0c6a8b0..45201f4ca5 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -335,6 +335,13 @@ extern void vgic_check_inflight_irqs_pending(struct vcpu *v,
>   /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
>   #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
>   
> +extern bool vgic_is_valid_irq(struct domain *d, unsigned int virq);
> +
> +static inline bool vgic_is_shared_irq(struct domain *d, unsigned int virq)
> +{
> +    return (virq >= NR_LOCAL_IRQS && vgic_is_valid_irq(d, virq));
> +}
> +
>   /*
>    * Allocate a guest VIRQ
>    *  - spi == 0 => allocate a PPI. It will be the same on every vCPU
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 12c70d02cc..50e57aaea7 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -442,7 +442,7 @@ int route_irq_to_guest(struct domain *d, unsigned int virq,
>       unsigned long flags;
>       int retval = 0;
>   
> -    if ( virq >= vgic_num_irqs(d) )
> +    if ( !vgic_is_valid_irq(d, virq) )


This file is common for all VGIC implementations, so 
route_irq_to_guest() is used with CONFIG_NEW_VGIC=y as well.

If your series is built with CONFIG_NEW_VGIC=y (I know, that NEW_VGIC 
does not support GICV3 HW) I have got the following error:


aarch64-poky-linux-ld: prelink.o: in function `route_irq_to_guest':
/usr/src/debug/xen/4.18.0+gitAUTOINC+ce58f56108-r0/git/xen/arch/arm/irq.c:445: 
undefined reference to `vgic_is_valid_irq'
/usr/src/debug/xen/4.18.0+gitAUTOINC+ce58f56108-r0/git/xen/arch/arm/irq.c:445:(.text+0x5e2f8): 
relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol 
`vgic_is_valid_irq'
...

 From the quick look, vgic_is_valid_irq() needs a stub (or NEW_VGIC's 
counterpart).

[snip]


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Date: Sat, 23 Aug 2025 16:02:11 +0300
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Subject: Re: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
 to support eSPIs
To: xen-devel@lists.xenproject.org,
 Leonid Komarianskyi 
References: <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 
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On 07.08.25 15:33, Leonid Komarianskyi wrote:

Hello Leonid

> The Dom0 configuration logic in create_dom0() has been updated
> to account for extended SPIs when supported by the hardware and
> enabled with CONFIG_GICV3_ESPI. These changes ensure the proper
> calculation of the maximum number of SPIs and eSPIs available for Dom0.
> 
> When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is
> enabled, the maximum number of eSPI interrupts is calculated using
> the ESPI_BASE_INTID offset (4096) and limited at 1024, with 32 IRQs
> subtracted. To ensure compatibility with non-Dom0 domains, this
> adjustment is applied by the toolstack during domain creation, while
> for Dom0 it is handled directly during VGIC initialization. If eSPIs
> are not supported, the calculation defaults to using the standard SPI
> range, with a maximum value of 992 interrupt lines as it works now.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V2:
> - no changes
> ---
>   xen/arch/arm/domain_build.c     | 10 ++++++++++
>   xen/arch/arm/include/asm/vgic.h | 11 +++++++++++
>   2 files changed, 21 insertions(+)
> 
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index d91a71acfd..fa5abf2dfb 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -2055,6 +2055,16 @@ void __init create_dom0(void)
>       /* The vGIC for DOM0 is exactly emulating the hardware GIC */
>       dom0_cfg.arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE;
>       dom0_cfg.arch.nr_spis = VGIC_DEF_NR_SPIS;
> +#ifdef CONFIG_GICV3_ESPI
> +    /*
> +     * Check if the hardware supports extended SPIs (even if the appropriate config is set).
> +     * If not, the common SPI range will be used. Otherwise overwrite the nr_spis with the
> +     * maximum available INTID from eSPI range. In that case, the number of regular SPIs will
> +     * be adjusted to the maximum value during vGIC initialization.
> +     */
> +    if ( gic_number_espis() > 0 )
> +        dom0_cfg.arch.nr_spis = VGIC_DEF_NR_ESPIS;
> +#endif

I might miss something, but within the whole series, you seem not to 
update "nr_spis" field for dom0less DomUs (in dom0less-build.c). Please 
clarify the reason?

>       dom0_cfg.arch.tee_type = tee_get_type();
>       dom0_cfg.max_vcpus = dom0_max_vcpus();
>   

[snip]


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Subject: Re: [PATCH v2 05/10] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
To: xen-devel@lists.xenproject.org,
 Leonid Komarianskyi 
References: <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 <2491bee7441f13a3c1a01fd77ece1749e7276352.1754568795.git.leonid_komarianskyi@epam.com>
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On 07.08.25 15:33, Leonid Komarianskyi wrote:

Hello Leonid


> Introduced appropriate register definitions, helper macros,
> and initialization of required GICv3.1 distributor registers
> to support eSPI. This type of interrupt is handled in the
> same way as regular SPI interrupts, with the following
> differences:
> 
> 1) eSPIs can have up to 1024 interrupts, starting from the
> beginning of the range, whereas regular SPIs use INTIDs from
> 32 to 1019, totaling 988 interrupts;
> 2) eSPIs start at INTID 4096, necessitating additional interrupt
> index conversion during register operations.
> 
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V2:
> - move gic_number_espis function from
>    [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
>    to use it in the newly introduced gic_is_valid_espi
> - add gic_is_valid_espi which checks if IRQ number is in supported
>    by HW eSPI range
> - update gic_is_valid_irq conditions to allow operations with eSPIs
> ---
>   xen/arch/arm/gic-v3.c                  | 73 ++++++++++++++++++++++++++
>   xen/arch/arm/include/asm/gic.h         | 17 ++++++
>   xen/arch/arm/include/asm/gic_v3_defs.h | 33 ++++++++++++
>   3 files changed, 123 insertions(+)
> 
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 8fd78aba44..a0e8ee1a1e 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
>           default:
>               break;
>           }
> +#ifdef CONFIG_GICV3_ESPI
> +    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
> +    {
> +        u32 irq_index = ESPI_INTID2IDX(irqd->irq);
> +
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ICENABLER:
> +            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ISPENDR:
> +            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ICPENDR:
> +            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ISACTIVER:
> +            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICACTIVER:
> +            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTERnE + irq_index * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYRnE + irq_index);
> +        default:
> +            break;
> +        }
> +    }
> +#endif
>       default:
>           break;
>       }
> @@ -645,6 +675,40 @@ static void gicv3_set_irq_priority(struct irq_desc *desc,
>       spin_unlock(&gicv3.lock);
>   }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +unsigned int gic_number_espis(void)
> +{
> +    return gic_hw_ops->info->nr_espi;
> +}
> +
> +static void gicv3_dist_espi_common_init(uint32_t type)

missing __init ?

> +{
> +    unsigned int espi_nr;
> +    int i;

please use unsigned int if "i" cannot be negative

> +
> +    espi_nr = min(1024U, GICD_TYPER_ESPIS_NUM(type));
> +    gicv3_info.nr_espi = espi_nr;
> +    /* The GIC HW doesn't support eSPI, so we can leave from here */
> +    if ( gicv3_info.nr_espi == 0 )
> +        return;
> +
> +    for ( i = 0; i < espi_nr; i += 16 )
> +        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
> +
> +    for ( i = 0; i < espi_nr; i += 4 )
> +        writel_relaxed(GIC_PRI_IRQ_ALL, GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
> +
> +    for ( i = 0; i < espi_nr; i += 32 )
> +    {
> +        writel_relaxed(0xffffffffU, GICD + GICD_ICENABLERnE + (i / 32) * 4);
> +        writel_relaxed(0xffffffffU, GICD + GICD_ICACTIVERnE + (i / 32) * 4);
> +    }
> +
> +    for ( i = 0; i < espi_nr; i += 32 )
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) * 4);
> +}
> +#endif
> +
>   static void __init gicv3_dist_init(void)
>   {
>       uint32_t type;
> @@ -690,6 +754,10 @@ static void __init gicv3_dist_init(void)
>       for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
>           writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4);
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    gicv3_dist_espi_common_init(type);
> +#endif
> +
>       gicv3_dist_wait_for_rwp();
>   
>       /* Turn on the distributor */
> @@ -703,6 +771,11 @@ static void __init gicv3_dist_init(void)
>   
>       for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
>           writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8);
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i = 0; i < gicv3_info.nr_espi; i++ )
> +        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * 8);
> +#endif
>   }
>   
>   static int gicv3_enable_redist(void)


[snip]



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Subject: Re: [PATCH v2 08/10] xen/arm: vgic: add resource management for
 extended SPIs
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: <7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com>
 
Content-Language: en-US
From: Oleksandr Tyshchenko 
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On 07.08.25 15:33, Leonid Komarianskyi wrote:


Hello Leonid

> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
> requested by the guest. A new field, ext_shared_irqs, is added
> to the VGIC structure to store information about eSPIs, similar
> to how shared_irqs is used for regular SPIs.
> 
> Since the eSPI range starts at INTID 4096 and INTIDs between 1025
> and 4095 are reserved, helper macros are introduced to simplify the
> transformation of indices and to enable easier access to eSPI-specific
> resources. These changes prepare the VGIC for processing eSPIs as
> required by future functionality.
> 
> The initialization and deinitialization paths for vgic have been updated
> to allocate and free these resources appropriately. Additionally,
> updated handling of INTIDs greater than 1024, passed from the toolstack
> during domain creation, and verification logic ensures only valid SPI or
> eSPI INTIDs are used.
> 
> The existing SPI behavior remains unaffected when guests do not request
> eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
> option is disabled.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V2:
> - change is_espi_rank to is_valid_espi_rank to verify whether the array
>    element ext_shared_irqs exists. The previous version, is_espi_rank,
>    only checked if the rank index was less than the maximum possible eSPI
>    rank index, but this could potentially result in accessing a
>    non-existing array element. To address this, is_valid_espi_rank was
>    introduced, which ensures that the required eSPI rank exists
> - move gic_number_espis to
>    xen/arm: gicv3: implement handling of GICv3.1 eSPI
> - update vgic_is_valid_irq checks to allow operating with eSPIs
> - remove redundant newline in vgic_allocate_virq
> ---
>   xen/arch/arm/include/asm/vgic.h |  18 ++++
>   xen/arch/arm/vgic.c             | 145 ++++++++++++++++++++++++++++++++
>   2 files changed, 163 insertions(+)
> 
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h
> index 45201f4ca5..9fa4523018 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -146,6 +146,10 @@ struct vgic_dist {
>       int nr_spis; /* Number of SPIs */
>       unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
>       struct vgic_irq_rank *shared_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +    struct vgic_irq_rank *ext_shared_irqs;
> +    int nr_espis; /* Number of extended SPIs */
> +#endif
>       /*
>        * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
>        * struct arch_vcpu.
> @@ -243,6 +247,14 @@ struct vgic_ops {
>   /* Number of ranks of interrupt registers for a domain */
>   #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
>   
> +#ifdef CONFIG_GICV3_ESPI
> +#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
> +#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
> +#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
> +#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
> +#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
> +#endif
> +
>   #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
>   #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
>   
> @@ -302,6 +314,12 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v,
>                                                 unsigned int b,
>                                                 unsigned int n,
>                                                 unsigned int s);
> +#ifdef CONFIG_GICV3_ESPI
> +extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
> +                                                  unsigned int b,
> +                                                  unsigned int n,
> +                                                  unsigned int s);
> +#endif
>   extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq);
>   extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
>   extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 48fbaf56fb..1a6c765af9 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -27,9 +27,26 @@
>   
>   bool vgic_is_valid_irq(struct domain *d, unsigned int virq)
>   {
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( virq >= ESPI_BASE_INTID && virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
> +        return true;
> +#endif
> +
>       return virq < vgic_num_irqs(d);
>   }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * Since eSPI indexes start from 4096 and numbers from 1024 to
> + * 4095 are forbidden, we need to check both lower and upper
> + * limits for ranks.
> + */
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
> +{
> +    return ( rank >= EXT_RANK_MIN && EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d) );
> +}
> +#endif
> +
>   static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>                                                     unsigned int rank)
>   {
> @@ -37,6 +54,10 @@ static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>           return v->arch.vgic.private_irqs;
>       else if ( rank <= DOMAIN_NR_RANKS(v->domain) )
>           return &v->domain->arch.vgic.shared_irqs[rank - 1];
> +#ifdef CONFIG_GICV3_ESPI
> +    else if ( is_valid_espi_rank(v->domain, rank) )
> +        return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)];
> +#endif
>       else
>           return NULL;
>   }
> @@ -53,6 +74,16 @@ struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v, unsigned int b,
>       return vgic_get_rank(v, rank);
>   }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int b,
> +                                           unsigned int n, unsigned int s)
> +{
> +    unsigned int rank = REG_RANK_NR(b, (n >> s));
> +
> +    return vgic_get_rank(v, rank + EXT_RANK_MIN);
> +}
> +#endif
> +
>   struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq)
>   {
>       unsigned int rank = irq / 32;
> @@ -117,6 +148,29 @@ int domain_vgic_register(struct domain *d, unsigned int *mmio_count)
>       return 0;
>   }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +static int init_vgic_espi(struct domain *d)
> +{
> +    int i;

please use unsigned int if "i" cannot be negative

> +
> +    if ( d->arch.vgic.nr_espis == 0 )
> +        return 0;
> +
> +    d->arch.vgic.ext_shared_irqs =
> +        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
> +    if ( d->arch.vgic.ext_shared_irqs == NULL )
> +        return -ENOMEM;
> +
> +    for ( i = 0; i < d->arch.vgic.nr_espis; i++ )
> +        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i + d->arch.vgic.nr_spis], ESPI_IDX2INTID(i));
> +
> +    for ( i = 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
> +        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
> +
> +    return 0;
> +}
> +#endif
> +
>   int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>   {
>       int i;
> @@ -131,6 +185,30 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>        */
>       nr_spis = ROUNDUP(nr_spis, 32);
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( nr_spis > ESPI_MAX_INTID )
> +        return -EINVAL;
> +
> +    if ( is_espi(nr_spis) )
> +    {
> +        /*
> +         * During domain creation, the toolstack specifies the maximum INTID,

domain_vgic_init() is also called for dom0less DomUs (if present), which 
are created at Xen boot. So the toolstack might even be absent on the 
target system.

> +         * which is defined in the domain config subtracted by 32. To compute the
> +         * actual number of eSPI that will be usable for, add back 32.
> +         */
> +        d->arch.vgic.nr_espis = min(nr_spis - ESPI_BASE_INTID + 32, 1024U);
> +        /* Verify if GIC HW can handle provided INTID */
> +        if ( d->arch.vgic.nr_espis > gic_number_espis() )
> +            return -EINVAL;
> +        /* Set the maximum available number for defult SPI to pass the next check */
> +        nr_spis = VGIC_DEF_NR_SPIS;
> +    } else
> +    {
> +        /* Domain will use the regular SPI range */
> +        d->arch.vgic.nr_espis = 0;
> +    }
> +#endif
> +
>       /* Limit the number of virtual SPIs supported to (1020 - 32) = 988  */
>       if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
>           return -EINVAL;
> @@ -145,7 +223,12 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>           return -ENOMEM;
>   
>       d->arch.vgic.pending_irqs =
> +#ifdef CONFIG_GICV3_ESPI
> +        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis +
> +                      d->arch.vgic.nr_espis);
> +#else
>           xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
> +#endif
>       if ( d->arch.vgic.pending_irqs == NULL )
>           return -ENOMEM;
>   
> @@ -156,12 +239,23 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>       for ( i = 0; i < DOMAIN_NR_RANKS(d); i++ )
>           vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    ret = init_vgic_espi(d);
> +    if ( ret )
> +        return ret;
> +#endif
> +
>       ret = d->arch.vgic.handler->domain_init(d);
>       if ( ret )
>           return ret;
>   
>       d->arch.vgic.allocated_irqs =
> +#ifdef CONFIG_GICV3_ESPI
> +        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d) +
> +                      d->arch.vgic.nr_espis));
> +#else
>           xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
> +#endif
>       if ( !d->arch.vgic.allocated_irqs )
>           return -ENOMEM;
>   
> @@ -195,9 +289,27 @@ void domain_vgic_free(struct domain *d)
>           }
>       }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i = 0; i < (d->arch.vgic.nr_espis); i++ )

NIT: no need for () around d->arch.vgic.nr_espis

> +    {
> +        struct pending_irq *p = spi_to_pending(d, ESPI_IDX2INTID(i));
> +
> +        if ( p->desc )
> +        {
> +            ret = release_guest_irq(d, p->irq);
> +            if ( ret )
> +                dprintk(XENLOG_G_WARNING, "d%u: Failed to release virq %u ret = %d\n",
> +                        d->domain_id, p->irq, ret);
> +        }
> +    }
> +#endif
> +
>       if ( d->arch.vgic.handler )
>           d->arch.vgic.handler->domain_free(d);
>       xfree(d->arch.vgic.shared_irqs);
> +#ifdef CONFIG_GICV3_ESPI
> +    xfree(d->arch.vgic.ext_shared_irqs);
> +#endif
>       xfree(d->arch.vgic.pending_irqs);
>       xfree(d->arch.vgic.allocated_irqs);
>   }
> @@ -331,6 +443,17 @@ void arch_move_irqs(struct vcpu *v)
>           if ( v_target == v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) )
>               irq_set_affinity(p->desc, cpu_mask);
>       }
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i = ESPI_BASE_INTID; i < (d)->arch.vgic.nr_espis; i++ )

NIT: no need for () around d

[snip]


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mirela
 Simonovic , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Saeed
 Nowshadi , Mykyta Poturai
	, Mykola Kvach 
Subject: Re: [PATCH v5 10/12] xen/arm: Save/restore context on suspend/resume
Thread-Topic: [PATCH v5 10/12] xen/arm: Save/restore context on suspend/resume
Thread-Index: AQHcCwFhwpLsP6pw2kWs0ShQW6gF5Q==
Date: Sat, 23 Aug 2025 17:34:12 +0000
Message-ID: <87zfbq6iy5.fsf@epam.com>
References: 
	<5441d6712a4ca0e61fd066606b9a96414123aaad.1754943875.git.mykola_kvach@epam.com>
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Hi Mykola,

Mykola Kvach  writes:

> From: Mirela Simonovic 
>
> The context of CPU general purpose and system control registers
> has to be saved on suspend and restored on resume. This is
> implemented in hyp_suspend and before the return from hyp_resume
> function. The hyp_suspend is invoked just before the PSCI system
> suspend call is issued to the ATF. The hyp_suspend has to return a
> non-zero value so that the calling 'if' statement evaluates to true,
> causing the system suspend to be invoked. Upon the resume, context
> saved on suspend will be restored, including the link register.
> Therefore, after restoring the context the control flow will
> return to the address pointed by the saved link register, which
> is the place from which the hyp_suspend was called. To ensure
> that the calling 'if' statement doesn't again evaluate to true
> and initiate system suspend, hyp_resume has to return a zero value
> after restoring the context.
>
> Note that the order of saving register context into cpu_context
> structure has to match the order of restoring.
>
> Support for ARM32 is not implemented. Instead, compilation fails with a
> build-time error if suspend is enabled for ARM32.
>
> Signed-off-by: Mirela Simonovic 
> Signed-off-by: Saeed Nowshadi 
> Signed-off-by: Mykyta Poturai 
> Signed-off-by: Mykola Kvach 
> ---
> Changes in v4:
> - produce build-time error for ARM32 when CONFIG_SYSTEM_SUSPEND is enable=
d
> - use register_t instead of uint64_t in cpu_context structure
> ---
>  xen/arch/arm/arm64/head.S          | 91 +++++++++++++++++++++++++++++-
>  xen/arch/arm/include/asm/suspend.h | 20 +++++++
>  xen/arch/arm/suspend.c             | 23 +++++++-
>  3 files changed, 130 insertions(+), 4 deletions(-)
>
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index 596e960152..ad8b48de3a 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -562,6 +562,52 @@ END(efi_xen_start)
>  #endif /* CONFIG_ARM_EFI */
> =20
>  #ifdef CONFIG_SYSTEM_SUSPEND
> +/*
> + * int hyp_suspend(struct cpu_context *ptr)
> + *
> + * x0 - pointer to the storage where callee's context will be saved
> + *
> + * CPU context saved here will be restored on resume in hyp_resume funct=
ion.
> + * hyp_suspend shall return a non-zero value. Upon restoring context
> + * hyp_resume shall return value zero instead. From C code that invokes
> + * hyp_suspend, the return value is interpreted to determine whether the=
 context
> + * is saved (hyp_suspend) or restored (hyp_resume).
> + */
> +FUNC(hyp_suspend)

I don't think that hyp_suspend is the correct name, as this function in
fact suspend_nothing. Maybe "prepare_resume_ctx" will be better?

> +        /* Store callee-saved registers */
> +        stp     x19, x20, [x0], #16

If you have struct cpu_context defined, then you probably should use
define provided by  to access struct fields. Otherwise,
it will be really easy to get desync between struct definition and this
asm code.

> +        stp     x21, x22, [x0], #16
> +        stp     x23, x24, [x0], #16
> +        stp     x25, x26, [x0], #16
> +        stp     x27, x28, [x0], #16
> +        stp     x29, lr, [x0], #16
> +
> +        /* Store stack-pointer */
> +        mov     x2, sp
> +        str     x2, [x0], #8
> +
> +        /* Store system control registers */
> +        mrs     x2, VBAR_EL2
> +        str     x2, [x0], #8
> +        mrs     x2, VTCR_EL2
> +        str     x2, [x0], #8
> +        mrs     x2, VTTBR_EL2
> +        str     x2, [x0], #8
> +        mrs     x2, TPIDR_EL2
> +        str     x2, [x0], #8
> +        mrs     x2, MDCR_EL2
> +        str     x2, [x0], #8
> +        mrs     x2, HSTR_EL2
> +        str     x2, [x0], #8
> +        mrs     x2, CPTR_EL2
> +        str     x2, [x0], #8
> +        mrs     x2, HCR_EL2
> +        str     x2, [x0], #8
> +
> +        /* hyp_suspend must return a non-zero value */
> +        mov     x0, #1
> +        ret
> +END(hyp_suspend)
> =20
>  FUNC(hyp_resume)
>          /* Initialize the UART if earlyprintk has been enabled. */
> @@ -580,7 +626,50 @@ FUNC(hyp_resume)
>          b     enable_secondary_cpu_mm
> =20
>  mmu_resumed:
> -        b .
> +        /*
> +         * Now we can access the cpu_context, so restore the context her=
e
> +         * TODO: can we reuse __context_switch and saved_context struct =
here ?
> +         */

This is a great idea and I like it very much, but sadly saved_context
struct has no fields for system _EL2 registers.

> +        ldr     x0, =3Dcpu_context
> +
> +        /* Restore callee-saved registers */
> +        ldp     x19, x20, [x0], #16
> +        ldp     x21, x22, [x0], #16
> +        ldp     x23, x24, [x0], #16
> +        ldp     x25, x26, [x0], #16
> +        ldp     x27, x28, [x0], #16
> +        ldp     x29, lr, [x0], #16
> +
> +        /* Restore stack pointer */
> +        ldr     x2, [x0], #8
> +        mov     sp, x2
> +
> +        /* Restore system control registers */
> +        ldr     x2, [x0], #8
> +        msr     VBAR_EL2, x2
> +        ldr     x2, [x0], #8
> +        msr     VTCR_EL2, x2
> +        ldr     x2, [x0], #8
> +        msr     VTTBR_EL2, x2
> +        ldr     x2, [x0], #8
> +        msr     TPIDR_EL2, x2
> +        ldr     x2, [x0], #8
> +        msr     MDCR_EL2, x2
> +        ldr     x2, [x0], #8
> +        msr     HSTR_EL2, x2
> +        ldr     x2, [x0], #8
> +        msr     CPTR_EL2, x2
> +        ldr     x2, [x0], #8
> +        msr     HCR_EL2, x2
> +        isb
> +
> +        /* Since context is restored return from this function will appe=
ar as
> +         * return from hyp_suspend. To distinguish a return from hyp_sus=
pend
> +         * which is called upon finalizing the suspend, as opposed to re=
turn
> +         * from this function which executes on resume, we need to retur=
n zero
> +         * value here. */
> +        mov x0, #0
> +        ret
>  END(hyp_resume)
> =20
>  #endif /* CONFIG_SYSTEM_SUSPEND */
> diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/as=
m/suspend.h
> index 55041a5d06..ae71ccb87b 100644
> --- a/xen/arch/arm/include/asm/suspend.h
> +++ b/xen/arch/arm/include/asm/suspend.h
> @@ -5,9 +5,29 @@
> =20
>  #ifdef CONFIG_SYSTEM_SUSPEND
> =20
> +#ifdef CONFIG_ARM_64
> +struct cpu_context {
> +    register_t callee_regs[12];
> +    register_t sp;
> +    register_t vbar_el2;
> +    register_t vtcr_el2;
> +    register_t vttbr_el2;
> +    register_t tpidr_el2;
> +    register_t mdcr_el2;
> +    register_t hstr_el2;
> +    register_t cptr_el2;
> +    register_t hcr_el2;
> +} __aligned(16);
> +#else
> +#error "Define cpu_context structure for arm32"
> +#endif
> +
> +extern struct cpu_context cpu_context;
> +
>  int host_system_suspend(void);
> =20
>  void hyp_resume(void);
> +int hyp_suspend(struct cpu_context *ptr);
> =20
>  #endif /* CONFIG_SYSTEM_SUSPEND */
> =20
> diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
> index 08b6acaede..b5398e5ca6 100644
> --- a/xen/arch/arm/suspend.c
> +++ b/xen/arch/arm/suspend.c
> @@ -1,6 +1,7 @@
>  /* SPDX-License-Identifier: GPL-2.0-only */
> =20
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -17,6 +18,8 @@
>   *  - Investigate feasibility and need for implementing system suspend o=
n ARM32
>   */
> =20
> +struct cpu_context cpu_context;
> +
>  /* Xen suspend. Note: data is not used (suspend is the suspend to RAM) *=
/
>  static long system_suspend(void *data)
>  {
> @@ -73,9 +76,23 @@ static long system_suspend(void *data)
>       */
>      update_boot_mapping(true);
> =20
> -    status =3D call_psci_system_suspend();
> -    if ( status )
> -        dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=3D%d\n"=
, status);
> +    if ( hyp_suspend(&cpu_context) )
> +    {
> +        status =3D call_psci_system_suspend();
> +        /*
> +         * If suspend is finalized properly by above system suspend PSCI=
 call,
> +         * the code below in this 'if' branch will never execute. Execut=
ion
> +         * will continue from hyp_resume which is the hypervisor's resum=
e point.
> +         * In hyp_resume CPU context will be restored and since link-reg=
ister is
> +         * restored as well, it will appear to return from hyp_suspend. =
The
> +         * difference in returning from hyp_suspend on system suspend ve=
rsus
> +         * resume is in function's return value: on suspend, the return =
value is
> +         * a non-zero value, on resume it is zero. That is why the contr=
ol flow
> +         * will not re-enter this 'if' branch on resume.
> +         */

Looks like this comment is misplaced. It should be before "if (
hyp_suspend() )", right?

> +        if ( status )
> +            dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=3D%=
d\n", status);
> +    }
> =20
>      system_state =3D SYS_STATE_resume;
>      update_boot_mapping(false);

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" ,
	Oleksandr Tyshchenko , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Mykola Kvach
	
Subject: Re: [PATCH v5 11/12] iommu/ipmmu-vmsa: Implement suspend/resume
 callbacks
Thread-Topic: [PATCH v5 11/12] iommu/ipmmu-vmsa: Implement suspend/resume
 callbacks
Thread-Index: AQHcCwFkX4gJFYauN0Oe6YQWa2GY2g==
Date: Sat, 23 Aug 2025 17:48:32 +0000
Message-ID: <87ldna6ia8.fsf@epam.com>
References: 
	<1689d707b930b1ea4f63cc150810e548962cda81.1754943875.git.mykola_kvach@epam.com>
In-Reply-To:
 <1689d707b930b1ea4f63cc150810e548962cda81.1754943875.git.mykola_kvach@epam.com>
	(Mykola Kvach's message of "Mon, 11 Aug 2025 23:48:07 +0300")
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Hi Mykola,

Mykola Kvach  writes:

> From: Oleksandr Tyshchenko 
>
> Store and restore active context and micro-TLB registers.
>
> Tested on R-Car H3 Starter Kit.
>
> Signed-off-by: Oleksandr Tyshchenko 
> Signed-off-by: Mykola Kvach 
> ---
>  xen/drivers/passthrough/arm/ipmmu-vmsa.c | 269 +++++++++++++++++++++++
>  1 file changed, 269 insertions(+)
>
> diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passt=
hrough/arm/ipmmu-vmsa.c
> index dac0dd6d46..ced762657a 100644
> --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> @@ -58,6 +58,8 @@
>  #define dev_print(dev, lvl, fmt, ...)    \
>      printk(lvl "ipmmu: %s: " fmt, dev_name(dev), ## __VA_ARGS__)
> =20
> +#define dev_dbg(dev, fmt, ...)    \
> +    dev_print(dev, XENLOG_DEBUG, fmt, ## __VA_ARGS__)
>  #define dev_info(dev, fmt, ...)    \
>      dev_print(dev, XENLOG_INFO, fmt, ## __VA_ARGS__)
>  #define dev_warn(dev, fmt, ...)    \
> @@ -117,6 +119,23 @@ struct ipmmu_features {
>      unsigned int imuctr_ttsel_mask;
>  };
> =20
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +
> +struct hw_register {
> +    const char *reg_name;

Do you really need to store register name? It is not used anywhere.

> +    unsigned int reg_offset;
> +    unsigned int reg_data;
> +};
> +
> +struct ipmmu_vmsa_backup {
> +    struct device *dev;
> +    unsigned int *utlbs_val;
> +    unsigned int *asids_val;
> +    struct list_head list;
> +};
> +
> +#endif
> +
>  /* Root/Cache IPMMU device's information */
>  struct ipmmu_vmsa_device {
>      struct device *dev;
> @@ -129,6 +148,9 @@ struct ipmmu_vmsa_device {
>      struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
>      unsigned int utlb_refcount[IPMMU_UTLB_MAX];
>      const struct ipmmu_features *features;
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +    struct hw_register *reg_backup[IPMMU_CTX_MAX];
> +#endif
>  };
> =20
>  /*
> @@ -534,6 +556,235 @@ static void ipmmu_domain_free_context(struct ipmmu_=
vmsa_device *mmu,
>      spin_unlock_irqrestore(&mmu->lock, flags);
>  }
> =20
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +
> +static DEFINE_SPINLOCK(ipmmu_devices_backup_lock);
> +static LIST_HEAD(ipmmu_devices_backup);
> +
> +#define HW_REGISTER_BACKUP_SIZE 4
> +
> +static struct hw_register root_pgtable[IPMMU_CTX_MAX][HW_REGISTER_BACKUP=
_SIZE] =3D {
> +    [0 ... (IPMMU_CTX_MAX - 1)] =3D {
> +        {"IMTTLBR0", IMTTLBR0, 0},
> +        {"IMTTUBR0", IMTTUBR0, 0},
> +        {"IMTTBCR",  IMTTBCR,  0},
> +        {"IMCTR",    IMCTR,    0},

Taking into account that only 4 registers needs to be saved, will it be
easier and more efficient to have a hardcoded struct like this?

struct ipmmu_reg_ctx {
    unsigned int imttlbr0;
    unsigned int imttubr0;
    unsigned int imttbcr;
    unsigned int imctr;
}

instead of hw_register[] ?

Especially taking into account that struct ipmmu_vmsa_backup{} does
exactly this.


> +    }
> +};
> +
> +static uint32_t ipmmu_imuasid_read(struct ipmmu_vmsa_device *mmu,
> +                                   unsigned int utlb)
> +{
> +    return ipmmu_read(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)));
> +}
> +
> +static void ipmmu_utlbs_backup(struct ipmmu_vmsa_device *mmu)
> +{
> +    struct ipmmu_vmsa_backup *backup_data;
> +
> +    dev_dbg(mmu->dev, "Handle micro-TLBs backup\n");
> +
> +    spin_lock(&ipmmu_devices_backup_lock);
> +
> +    list_for_each_entry( backup_data, &ipmmu_devices_backup, list )
> +    {
> +        struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(backup_data=
->dev);
> +        unsigned int i;
> +
> +        if ( to_ipmmu(backup_data->dev) !=3D mmu )
> +            continue;
> +
> +        for ( i =3D 0; i < fwspec->num_ids; i++ )
> +        {
> +            unsigned int utlb =3D fwspec->ids[i];
> +
> +            backup_data->asids_val[i] =3D ipmmu_imuasid_read(mmu, utlb);
> +            backup_data->utlbs_val[i] =3D ipmmu_imuctr_read(mmu, utlb);
> +        }
> +    }
> +
> +    spin_unlock(&ipmmu_devices_backup_lock);
> +}
> +
> +static void ipmmu_utlbs_restore(struct ipmmu_vmsa_device *mmu)
> +{
> +    struct ipmmu_vmsa_backup *backup_data;
> +
> +    dev_dbg(mmu->dev, "Handle micro-TLBs restore\n");
> +
> +    spin_lock(&ipmmu_devices_backup_lock);
> +
> +    list_for_each_entry( backup_data, &ipmmu_devices_backup, list )
> +    {
> +        struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(backup_data=
->dev);
> +        unsigned int i;
> +
> +        if ( to_ipmmu(backup_data->dev) !=3D mmu )
> +            continue;
> +
> +        for ( i =3D 0; i < fwspec->num_ids; i++ )
> +        {
> +            unsigned int utlb =3D fwspec->ids[i];
> +
> +            ipmmu_imuasid_write(mmu, utlb, backup_data->asids_val[i]);
> +            ipmmu_imuctr_write(mmu, utlb, backup_data->utlbs_val[i]);
> +        }
> +    }
> +
> +    spin_unlock(&ipmmu_devices_backup_lock);
> +}
> +
> +static void ipmmu_domain_backup_context(struct ipmmu_vmsa_domain *domain=
)
> +{
> +    struct ipmmu_vmsa_device *mmu =3D domain->mmu->root;
> +    struct hw_register *reg =3D mmu->reg_backup[domain->context_id];
> +    unsigned int i;
> +
> +    dev_dbg(mmu->dev, "Handle domain context %u backup\n", domain->conte=
xt_id);
> +
> +    for ( i =3D 0; i < HW_REGISTER_BACKUP_SIZE; i++ )
> +        reg[i].reg_data =3D ipmmu_ctx_read_root(domain, reg[i].reg_offse=
t);
> +}
> +
> +static void ipmmu_domain_restore_context(struct ipmmu_vmsa_domain *domai=
n)
> +{
> +    struct ipmmu_vmsa_device *mmu =3D domain->mmu->root;
> +    struct hw_register *reg =3D mmu->reg_backup[domain->context_id];
> +    unsigned int i;
> +
> +    dev_dbg(mmu->dev, "Handle domain context %u restore\n", domain->cont=
ext_id);
> +
> +    for ( i =3D 0; i < HW_REGISTER_BACKUP_SIZE; i++ )
> +    {
> +        if ( reg[i].reg_offset !=3D IMCTR )
> +            ipmmu_ctx_write_root(domain, reg[i].reg_offset, reg[i].reg_d=
ata);
> +        else
> +            ipmmu_ctx_write_all(domain, reg[i].reg_offset,
> +                                reg[i].reg_data | IMCTR_FLUSH);
> +    }
> +}
> +
> +/*
> + * Xen: Unlike Linux implementation, Xen uses a single driver instance
> + * for handling all IPMMUs. There is no framework for ipmmu_suspend/resu=
me
> + * callbacks to be invoked for each IPMMU device. So, we need to iterate
> + * through all registered IPMMUs performing required actions.
> + *
> + * Also take care of restoring special settings, such as translation
> + * table format, etc.
> + */
> +static int __must_check ipmmu_suspend(void)
> +{
> +    struct ipmmu_vmsa_device *mmu;
> +
> +    if ( !iommu_enabled )
> +        return 0;
> +
> +    printk(XENLOG_DEBUG "ipmmu: Suspending ...\n");
> +
> +    spin_lock(&ipmmu_devices_lock);
> +
> +    list_for_each_entry( mmu, &ipmmu_devices, list )
> +    {
> +        if ( ipmmu_is_root(mmu) )
> +        {
> +            unsigned int i;
> +
> +            for ( i =3D 0; i < mmu->num_ctx; i++ )
> +            {
> +                if ( !mmu->domains[i] )
> +                    continue;
> +                ipmmu_domain_backup_context(mmu->domains[i]);
> +            }
> +        }
> +        else
> +            ipmmu_utlbs_backup(mmu);
> +    }
> +
> +    spin_unlock(&ipmmu_devices_lock);
> +
> +    return 0;
> +}
> +
> +static void ipmmu_resume(void)
> +{
> +    struct ipmmu_vmsa_device *mmu;
> +
> +    if ( !iommu_enabled )
> +        return;
> +
> +    printk(XENLOG_DEBUG "ipmmu: Resuming ...\n");
> +
> +    spin_lock(&ipmmu_devices_lock);
> +
> +    list_for_each_entry( mmu, &ipmmu_devices, list )
> +    {
> +        uint32_t reg;
> +
> +        /* Do not use security group function */
> +        reg =3D IMSCTLR + mmu->features->control_offset_base;
> +        ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) & ~IMSCTLR_USE_SECGRP=
);
> +
> +        if ( ipmmu_is_root(mmu) )
> +        {
> +            unsigned int i;
> +
> +            /* Use stage 2 translation table format */
> +            reg =3D IMSAUXCTLR + mmu->features->control_offset_base;
> +            ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) | IMSAUXCTLR_S2PT=
E);
> +
> +            for ( i =3D 0; i < mmu->num_ctx; i++ )
> +            {
> +                if ( !mmu->domains[i] )
> +                    continue;
> +                ipmmu_domain_restore_context(mmu->domains[i]);
> +            }
> +        }
> +        else
> +            ipmmu_utlbs_restore(mmu);
> +    }
> +
> +    spin_unlock(&ipmmu_devices_lock);
> +}
> +
> +static int ipmmu_alloc_ctx_suspend(struct device *dev)
> +{
> +    struct ipmmu_vmsa_backup *backup_data;
> +    unsigned int *utlbs_val, *asids_val;
> +    struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev);
> +
> +    utlbs_val =3D xzalloc_array(unsigned int, fwspec->num_ids);
> +    if ( !utlbs_val )
> +        return -ENOMEM;
> +
> +    asids_val =3D xzalloc_array(unsigned int, fwspec->num_ids);
> +    if ( !asids_val )
> +    {
> +        xfree(utlbs_val);
> +        return -ENOMEM;
> +    }
> +
> +    backup_data =3D xzalloc(struct ipmmu_vmsa_backup);
> +    if ( !backup_data )
> +    {
> +        xfree(utlbs_val);
> +        xfree(asids_val);
> +        return -ENOMEM;
> +    }
> +
> +    backup_data->dev =3D dev;
> +    backup_data->utlbs_val =3D utlbs_val;
> +    backup_data->asids_val =3D asids_val;
> +
> +    spin_lock(&ipmmu_devices_backup_lock);
> +    list_add(&backup_data->list, &ipmmu_devices_backup);
> +    spin_unlock(&ipmmu_devices_backup_lock);
> +
> +    return 0;
> +}
> +
> +#endif /* CONFIG_SYSTEM_SUSPEND */
> +
>  static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
>  {
>      uint64_t ttbr;
> @@ -546,6 +797,9 @@ static int ipmmu_domain_init_context(struct ipmmu_vms=
a_domain *domain)
>          return ret;
> =20
>      domain->context_id =3D ret;
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +    domain->mmu->root->reg_backup[ret] =3D root_pgtable[ret];
> +#endif
> =20
>      /*
>       * TTBR0
> @@ -602,6 +856,9 @@ static void ipmmu_domain_destroy_context(struct ipmmu=
_vmsa_domain *domain)
>      ipmmu_ctx_write_root(domain, IMCTR, IMCTR_FLUSH);
>      ipmmu_tlb_sync(domain);
> =20
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +    domain->mmu->root->reg_backup[domain->context_id] =3D NULL;
> +#endif
>      ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
>  }
> =20
> @@ -1307,6 +1564,14 @@ static int ipmmu_add_device(u8 devfn, struct devic=
e *dev)
>      /* Let Xen know that the master device is protected by an IOMMU. */
>      dt_device_set_protected(dev_to_dt(dev));
> =20
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +    if ( ipmmu_alloc_ctx_suspend(dev) )
> +    {
> +        dev_err(dev, "Failed to allocate context for suspend\n");
> +        return -ENOMEM;
> +    }
> +#endif
> +
>      dev_info(dev, "Added master device (IPMMU %s micro-TLBs %u)\n",
>               dev_name(fwspec->iommu_dev), fwspec->num_ids);
> =20
> @@ -1372,6 +1637,10 @@ static const struct iommu_ops ipmmu_iommu_ops =3D
>      .unmap_page      =3D arm_iommu_unmap_page,
>      .dt_xlate        =3D ipmmu_dt_xlate,
>      .add_device      =3D ipmmu_add_device,
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +    .suspend         =3D ipmmu_suspend,
> +    .resume          =3D ipmmu_resume,
> +#endif
>  };
> =20
>  static __init int ipmmu_init(struct dt_device_node *node, const void *da=
ta)

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" ,
	Oleksandr Tyshchenko , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel , Mykola Kvach
	, Oleksandr Andrushchenko
	
Subject: Re: [PATCH v5 12/12] xen/arm: Suspend/resume IOMMU on Xen
 suspend/resume
Thread-Topic: [PATCH v5 12/12] xen/arm: Suspend/resume IOMMU on Xen
 suspend/resume
Thread-Index: AQHcCwFkkQdjEXTsbESLorqeX+r1kg==
Date: Sat, 23 Aug 2025 17:54:56 +0000
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Hi,

Mykola Kvach  writes:

> From: Oleksandr Tyshchenko 
>
> This is done using generic iommu_suspend/resume functions that cause
> IOMMU driver specific suspend/resume handlers to be called for enabled
> IOMMU (if one has suspend/resume driver handlers implemented).
>
> These handlers work only when IPMMU-VMSA is used; otherwise,
> we return an error during system suspend requests.
>
> Signed-off-by: Oleksandr Tyshchenko 
> Signed-off-by: Mykola Kvach 
> Tested-by: Oleksandr Andrushchenko 
> ---
>  xen/arch/arm/suspend.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
> index b5398e5ca6..cb86426ebd 100644
> --- a/xen/arch/arm/suspend.c
> +++ b/xen/arch/arm/suspend.c
> @@ -4,6 +4,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
> =20
> @@ -49,6 +50,13 @@ static long system_suspend(void *data)
> =20
>      time_suspend();
> =20
> +    status =3D iommu_suspend();
> +    if ( status )
> +    {
> +        system_state =3D SYS_STATE_resume;
> +        goto resume_time;
> +    }
> +
>      local_irq_save(flags);
>      status =3D gic_suspend();
>      if ( status )
> @@ -105,6 +113,10 @@ static long system_suspend(void *data)
> =20
>   resume_irqs:
>      local_irq_restore(flags);
> +
> +    iommu_resume();
> +
> + resume_time:
>      time_resume();
> =20
>   resume_nonboot_cpus:
> @@ -140,6 +152,15 @@ int host_system_suspend(void)
>          return -ENOSYS;
>      }
> =20
> +    /* TODO: drop check once suspend/resume support for SMMU is implemen=
ted */
> +#ifndef CONFIG_IPMMU_VMSA

This check is meaningless, as you can have CONFIG_IPMMU_VMSA enabled
along with CONFIG_ARM_SMMU on a system with SMMU. I think it is enough
that iommu_suspend() will fail during system_suspend(), isn't it?


> +    if ( iommu_enabled )
> +    {
> +        dprintk(XENLOG_ERR, "IOMMU is enabled, suspend not supported yet=
\n");
> +        return -ENOSYS;
> +    }
> +#endif
> +
>      /*
>       * system_suspend should be called when Dom0 finalizes the suspend
>       * procedure from its boot core (VCPU#0). However, Dom0's VCPU#0 cou=
ld

--=20
WBR, Volodymyr=


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Date: Sat, 23 Aug 2025 22:26:36 +0100
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Subject: Re: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
Content-Language: en-GB
To: Mykola Kvach , xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: 
 <205b2b354ff1d34d0e9ec4777ca3c94492f6d9d1.1755506449.git.mykola_kvach@epam.com>
From: Julien Grall 
In-Reply-To: <205b2b354ff1d34d0e9ec4777ca3c94492f6d9d1.1755506449.git.mykola_kvach@epam.com>
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Hi Mykola,

On 18/08/2025 09:49, Mykola Kvach wrote:
> From: Mykola Kvach 
> 
> This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPSCI
> (virtual PSCI) interface, allowing guests to request suspend via the PSCI
> v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).
> 
> The implementation:
> - Adds SYSTEM_SUSPEND function IDs to PSCI definitions
> - Implements trapping and handling of SYSTEM_SUSPEND in vPSCI
> - Allows only non-hardware domains to invoke SYSTEM_SUSPEND; for the
>    hardware domain, PSCI_NOT_SUPPORTED is returned to avoid halting the
>    system in hwdom_shutdown() called from domain_shutdown
> - Ensures all secondary VCPUs of the calling domain are offline before
>    allowing suspend due to PSCI spec
> 
> GIC and virtual timer context must be saved when the domain suspends.

Can you expand a bit more on this? Is this a requirement from the Arm 
Arm? If so, please specify the specification so we can easily check.

> This is done by moving the respective code in ctxt_switch_from
> before the return that happens if the domain suspended.

 From the commit message, it is unclear why we want to skip the save part.

[...]

> ---
>   xen/arch/arm/domain.c                 |  17 +++--
>   xen/arch/arm/include/asm/perfc_defn.h |   1 +
>   xen/arch/arm/include/asm/psci.h       |   2 +
>   xen/arch/arm/include/asm/vpsci.h      |   2 +-
>   xen/arch/arm/vpsci.c                  | 101 ++++++++++++++++++++++----
>   xen/common/domain.c                   |  31 ++++++--
>   xen/include/xen/sched.h               |   6 ++
>   7 files changed, 131 insertions(+), 29 deletions(-)
> 
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index 310c578909..9e9649c4e2 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -90,6 +90,16 @@ static void ctxt_switch_from(struct vcpu *p)
>       if ( is_idle_vcpu(p) )
>           return;
>   

It would be good to have a comment explaining what (and why) we need to 
save only partially the state while the VCPU is suspended.

> +    /* Arch timer */
> +    p->arch.cntkctl = READ_SYSREG(CNTKCTL_EL1);
> +    virt_timer_save(p);
> +
> +    /* VGIC */
> +    gic_save_state(p);
> +
> +    if ( test_bit(_VPF_suspended, &p->pause_flags) )
> +        return;

Can you explain why we don't need an isb()?

> +
>       p2m_save_state(p);
At least part of p2m_save_state() can't be skipped because it is 
applying a workaround on platform where AT mistakenly speculate.

[...]

>   
> +static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid)
> +{
> +    int32_t rc;
> +    struct vcpu *v;
> +    struct domain *d = current->domain;
> +
> +    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> +    if ( is_hardware_domain(d) )
> +        return PSCI_NOT_SUPPORTED;
> +
> +    /* Ensure that all CPUs other than the calling one are offline */
> +    domain_lock(d);
> +    for_each_vcpu ( d, v )
> +    {
> +        if ( v != current && is_vcpu_online(v) )
> +        {
> +            domain_unlock(d);
> +            return PSCI_DENIED;
> +        }
> +    }
> +    domain_unlock(d);
> +
> +    rc = domain_shutdown(d, SHUTDOWN_suspend);
> +    if ( rc )
> +        return PSCI_DENIED;
> +
> +    rc = do_setup_vcpu_ctx(current, epoint, cid);
> +    if ( rc != PSCI_SUCCESS )
> +    {
> +        domain_resume_nopause(d);
> +        return rc;
> +    }
> +
> +    set_bit(_VPF_suspended, ¤t->pause_flags);
> +
> +    dprintk(XENLOG_DEBUG,

I think you should use gdprintk() which will print the domain for you as 
well as appropriately ratelimit the message.

That said, I would consider using gprintk() so the message can also be 
printed in a debug build.

> +            "Dom %u: SYSTEM_SUSPEND requested, epoint=%#lx, cid=%#lx\n",

For both of them you technically want to use PRIregister rather than lx.

Lastly, we prefer to use %pd when printing a domain. The argument is 
'd'. But this should not be necessary if you use gprintk().


> +            d->domain_id, epoint, cid);
> +
> +    return rc;
> +}
> +
>   static int32_t do_psci_1_0_features(uint32_t psci_func_id)
>   {
>       /* /!\ Ordered by function ID and not name */
> @@ -214,6 +267,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id)
>       case PSCI_0_2_FN32_SYSTEM_OFF:
>       case PSCI_0_2_FN32_SYSTEM_RESET:
>       case PSCI_1_0_FN32_PSCI_FEATURES:
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
>       case ARM_SMCCC_VERSION_FID:
>           return 0;
>       default:
> @@ -344,6 +399,24 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
>           return true;
>       }
>   
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> +    {
> +        register_t epoint = PSCI_ARG(regs, 1);
> +        register_t cid = PSCI_ARG(regs, 2);
> +
> +        if ( is_64bit_domain(current->domain) &&

Shouldn't this be removed so the check also apply for 32-bit domain on 
64-bit system?

> +             fid == PSCI_1_0_FN32_SYSTEM_SUSPEND )
 > +        {> +            epoint &= GENMASK(31, 0);
> +            cid &= GENMASK(31, 0);
> +        }
> +
> +        perfc_incr(vpsci_system_suspend);
> +        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
> +        return true;
> +    }
> +
>       default:
>           return false;
>       }
> diff --git a/xen/common/domain.c b/xen/common/domain.c
> index 5241a1629e..624c3e2c27 100644
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -1343,16 +1343,13 @@ int domain_shutdown(struct domain *d, u8 reason)
>       return 0;
>   }
>   
> -void domain_resume(struct domain *d)
> +#ifndef CONFIG_ARM
> +static
> +#endif

I am not sure who suggests this but personally, I dislike using 
CONFIG_ in common code. I also think this is worse for hiding the 
"static" keyword.

For the latter, I think it would be better to provide a separate helper 
that can be #ifdef.

[...]

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v9 3/4] SUPPORT.md: Document PSCI SYSTEM_SUSPEND support
 for guests
Content-Language: en-GB
To: Mykola Kvach , xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini 
References: 
 <433d74567cabf33c2a672afc0f96e58efec75c54.1755506449.git.mykola_kvach@epam.com>
From: Julien Grall 
In-Reply-To: <433d74567cabf33c2a672afc0f96e58efec75c54.1755506449.git.mykola_kvach@epam.com>
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Hi Mykola,

On 18/08/2025 09:49, Mykola Kvach wrote:
> From: Mykola Kvach 
> 
> Add a new entry under the "Virtual Hardware, QEMU" section documenting
> support for the optional PSCI SYSTEM_SUSPEND function exposed to guests.
> 
> This function is available via the virtual PSCI (vPSCI) interface and
> allows guest domains (domUs) to initiate system suspend operations.
> 
> The feature is currently marked as Experimental.
> 
> Signed-off-by: Mykola Kvach 
> ---
> Changes in v6:
> - Dropped the generic guest PSCI support entry (merged in a separate patch)
> - This patch now documents only the SYSTEM_SUSPEND optional function
> - Reworded commit message to match the final form after rebase
> 
> Changes in v5:
> - Dropped ARM/PSCI entry: this refers to internal use of PSCI SMC calls,
>    which is not relevant for SUPPORT.md
> - Added a dedicated entry for PSCI SYSTEM_SUSPEND instead of generic guest
>    PSCI info; guest PSCI support was documented in a separate patch
> ---
>   SUPPORT.md | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/SUPPORT.md b/SUPPORT.md
> index 6a82a92189..b5ab049b52 100644
> --- a/SUPPORT.md
> +++ b/SUPPORT.md
> @@ -962,8 +962,9 @@ Emulated PSCI interface exposed to guests. We support all mandatory
>   functions of PSCI 1.1. See below for the list of optional PSCI call
>   implemented and their status.
>   
> -   Status, Mandatory: Supported
> -   Status, MIGRATE_INFO_TYPE: Supported
> +    Status, Mandatory: Supported
> +    Status, MIGRATE_INFO_TYPE: Supported
> +    Status, SYSTEM_SUSPEND: Experimental

Experimental implies the feature is not complete. But it is unclear to 
me what is missing (or I probably forgotten). Can this be clarified in 
the commit message?

If there is nothing, then I think it can be a tech preview.

Cheers,

-- 
Julien Grall



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	Anthony PERARD 
Subject: [PATCH v5 1/4] tools: add sizeof_field and endof_field macros
Date: Sat, 23 Aug 2025 22:26:49 +0000
Message-Id: <8dd6b217fbde427407113fedabb70f54d12aed61.1755987697.git.w1benny@gmail.com>
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From: Petr Beneš 

* `sizeof_field` returns the size of a specific struct member
* `endof_field` returns the offset to the end of the member within the struct

It will be useful in upcoming layout checks of SMBIOS structs.

Signed-off-by: Petr Beneš 
---
 tools/include/xen-tools/common-macros.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/tools/include/xen-tools/common-macros.h b/tools/include/xen-tools/common-macros.h
index 0088208c2e..9838a108aa 100644
--- a/tools/include/xen-tools/common-macros.h
+++ b/tools/include/xen-tools/common-macros.h
@@ -83,6 +83,11 @@
 #define __packed __attribute__((__packed__))
 #endif
 
+#define sizeof_field(type, member) sizeof(((type *)NULL)->member)
+
+#define endof_field(type, member) \
+    (offsetof(type, member) + sizeof_field(type, member))
+
 #define container_of(ptr, type, member) ({              \
     typeof(((type *)0)->member) *mptr__ = (ptr);        \
     (type *)((char *)mptr__ - offsetof(type, member));  \
-- 
2.34.1



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To: xen-devel@lists.xenproject.org
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	Anthony PERARD ,
	Jan Beulich ,
	Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v5 0/4] hvmloader: add new SMBIOS tables (7,8,9,26,27,28)
Date: Sat, 23 Aug 2025 22:26:48 +0000
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From: Petr Beneš 

Changes since v4:
- Renamed offsetof_end macro to endof_field.
- Added mention in CHANGELOG.md.

- hvmloader: fix SMBIOS table length checks
  - Changed `table_size` parameter name to `min_size` in the `smbios_pt_copy`
    function.
  - Fixed typo in `smbios_type_2_init` function where `smbios_type_3` was
    mistyped.

Changes since v3:
- Renamed offsetofend macro to offsetof_end.

Changes since v2:
- Added sizeof_field and offsetofend macros to common-macros.h.
- Used offsetofend macro everywhere to make semantically sense.
- Added BUILD_BUG_ON to ensure offsets are correct based on the SMBIOS
  specification (with explanation in the comments).
- Fixed commit message of the second patch to mention the new smbios_pt_copy
  function.
- Fixed nits (empty lines, misplaced *).
- Retained the original comment "Only present when passed in" + added it to
  the new tables where applicable.
- Replaced hardcoded offset for chassis_handle in smbios_type_2_init.

Changes since v1:
- Swapped the order of S-o-b in the last commit message.

Resubmitting patch from Anton Belousov and addressing review comments
from Jan: https://old-list-archives.xen.org/archives/html/xen-devel/2022-01/msg00725.html

Original message:
> SMBIOS tables like 7,8,9,26,27,28 are neccessary to prevent sandbox detection
> by malware using WMI-queries. New tables can be mapped to memory from binary
> file specified in "smbios_firmware" parameter of domain configuration.
> If particular table is absent in binary file, then it will not be mapped to
> memory. This method works for Windows domains as tables 7,8,9,26,27,28 are not
> critical for OS boot and runtime. Also if "smbios_firmware" parameter is not
> provided, these tables will be skipped in write_smbios_tables function.

Further explanation:
Some malware samples are known to check presence of various hardware components
(like CPU fan, CPU temperature sensor, etc.) by WMI queries. If these components
are not present, then malware can assume that it is running in a sandbox and
will not execute its payload.

This patch will allow security researchers to create a custom SMBIOS
firmware binary file that contains these tables.

Petr Beneš (4):
  tools: add sizeof_field and endof_field macros
  hvmloader: fix SMBIOS table length checks
  hvmloader: add new SMBIOS tables (7, 8, 9, 26, 27, 28)
  CHANGELOG.md: add new SMBIOS tables (7, 8, 9, 26, 27, 28)

 CHANGELOG.md                            |   1 +
 tools/firmware/hvmloader/smbios.c       | 289 ++++++++++++++++++------
 tools/firmware/hvmloader/smbios_types.h | 109 +++++++--
 tools/include/xen-tools/common-macros.h |   5 +
 4 files changed, 317 insertions(+), 87 deletions(-)

-- 
2.34.1



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To: xen-devel@lists.xenproject.org
Cc: =?UTF-8?q?Petr=20Bene=C5=A1?= ,
	Jan Beulich ,
	Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Anthony PERARD 
Subject: [PATCH v5 2/4] hvmloader: fix SMBIOS table length checks
Date: Sat, 23 Aug 2025 22:26:50 +0000
Message-Id: <58f42aaaf460c33d9d0935d670aab9f54eb184b8.1755987697.git.w1benny@gmail.com>
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From: Petr Beneš 

SMBIOS specification dictates that tables should have a minimal length.
This commit introduces further validation for user-input SMBIOS tables.

As per SMBIOS Reference Specification:
* Type 0: For version 2.3 and later implementations, the length is at least 14h
* Type 1: 1Bh for 2.4 and later
* Type 2: at least 08h
* Type 3: 0Dh for version 2.1 and later
* Type 11: 5h (+ strings)
* Type 22: 1Ah (+ strings)
* Type 39: a minimum of 10h

Notably, this also fixes previously incorrect check for chassis handle in
smbios_type_2_init. Chassis handle is a WORD, therefore, the condition now
correctly checks for >= 13 instead of > 13.

hvmloader currently implements version 2.4

Furthermore, this commit introduces smbios_pt_copy helper function to substitute
previously repeating pattern of locating the struct in physical memory (via
get_smbios_pt_struct), checking the length and copying it into SMBIOS region.

Signed-off-by: Petr Beneš 
Acked-by: Jan Beulich 
---
 tools/firmware/hvmloader/smbios.c       | 178 ++++++++++++++----------
 tools/firmware/hvmloader/smbios_types.h |  32 ++---
 2 files changed, 123 insertions(+), 87 deletions(-)

diff --git a/tools/firmware/hvmloader/smbios.c b/tools/firmware/hvmloader/smbios.c
index 6bcdcc233a..de3ba78e87 100644
--- a/tools/firmware/hvmloader/smbios.c
+++ b/tools/firmware/hvmloader/smbios.c
@@ -47,6 +47,8 @@ static void
 smbios_pt_init(void);
 static void*
 get_smbios_pt_struct(uint8_t type, uint32_t *length_out);
+static void *
+smbios_pt_copy(void *start, uint8_t type, uint16_t handle, size_t table_size);
 static void
 get_cpu_manufacturer(char *buf, int len);
 static int
@@ -154,6 +156,24 @@ get_smbios_pt_struct(uint8_t type, uint32_t *length_out)
     return NULL;
 }
 
+static void *
+smbios_pt_copy(void *start, uint8_t type, uint16_t handle, size_t min_size)
+{
+    struct smbios_structure_header *header = start;
+    void *pts;
+    uint32_t length;
+
+    pts = get_smbios_pt_struct(type, &length);
+    if ( pts != NULL && length >= min_size )
+    {
+        memcpy(start, pts, length);
+        header->handle = handle;
+        return start + length;
+    }
+
+    return start;
+}
+
 static void
 get_cpu_manufacturer(char *buf, int len)
 {
@@ -381,16 +401,17 @@ smbios_type_0_init(void *start, const char *xen_version,
     struct smbios_type_0 *p = start;
     static const char *smbios_release_date = __SMBIOS_DATE__;
     const char *s;
-    void *pts;
-    uint32_t length;
+    void *next;
 
-    pts = get_smbios_pt_struct(0, &length);
-    if ( pts != NULL && length > 0 )
-    {
-        memcpy(start, pts, length);
-        p->header.handle = SMBIOS_HANDLE_TYPE0;
-        return start + length;
-    }
+    /*
+     * Specification says Type 0 table has length of at least 18h for v2.4-3.0.
+     */
+
+    BUILD_BUG_ON(sizeof(*p) != 24);
+
+    next = smbios_pt_copy(start, 0, SMBIOS_HANDLE_TYPE0, sizeof(*p));
+    if ( next != start )
+        return next;
 
     memset(p, 0, sizeof(*p));
 
@@ -440,16 +461,14 @@ smbios_type_1_init(void *start, const char *xen_version,
     char uuid_str[37];
     struct smbios_type_1 *p = start;
     const char *s;
-    void *pts;
-    uint32_t length;
+    void *next;
 
-    pts = get_smbios_pt_struct(1, &length);
-    if ( pts != NULL && length > 0 )
-    {
-        memcpy(start, pts, length);
-        p->header.handle = SMBIOS_HANDLE_TYPE1;
-        return start + length;
-    }
+    /* Specification says Type 1 table has length of 1Bh for v2.4 and later. */
+    BUILD_BUG_ON(sizeof(*p) != 27);
+
+    next = smbios_pt_copy(start, 1, SMBIOS_HANDLE_TYPE1, sizeof(*p));
+    if ( next != start )
+        return next;
 
     memset(p, 0, sizeof(*p));
 
@@ -498,26 +517,29 @@ smbios_type_2_init(void *start)
 {
     struct smbios_type_2 *p = start;
     const char *s;
-    uint8_t *ptr;
-    void *pts;
-    uint32_t length;
+    void *next;
     unsigned int counter = 0;
 
-    pts = get_smbios_pt_struct(2, &length);
-    if ( pts != NULL && length > 0 )
-    {
-        memcpy(start, pts, length);
-        p->header.handle = SMBIOS_HANDLE_TYPE2;
+    /*
+     * Specification says Type 2 table has length of at least 08h,
+     * which corresponds with the end of the "Serial Number" field.
+     */
+
+    BUILD_BUG_ON(endof_field(struct smbios_type_2, serial_number_str) != 8);
 
+    next = smbios_pt_copy(start, 2, SMBIOS_HANDLE_TYPE2,
+                          endof_field(struct smbios_type_2, serial_number_str));
+    if ( next != start )
+    {
         /* Set current chassis handle if present */
-        if ( p->header.length > 13 )
+        if ( p->header.length >= endof_field(struct smbios_type_2,
+                                             chassis_handle) )
         {
-            ptr = ((uint8_t*)start) + 11;            
-            if ( *((uint16_t*)ptr) != 0 )
-                *((uint16_t*)ptr) = SMBIOS_HANDLE_TYPE3;
+            if ( p->chassis_handle != 0 )
+                p->chassis_handle = SMBIOS_HANDLE_TYPE3;
         }
 
-        return start + length;
+        return next;
     }
 
     memset(p, 0, sizeof(*p));
@@ -593,18 +615,21 @@ smbios_type_3_init(void *start)
 {
     struct smbios_type_3 *p = start;
     const char *s;
-    void *pts;
-    uint32_t length;
+    void *next;
     uint32_t counter = 0;
 
-    pts = get_smbios_pt_struct(3, &length);
-    if ( pts != NULL && length > 0 )
-    {
-        memcpy(start, pts, length);
-        p->header.handle = SMBIOS_HANDLE_TYPE3;
-        return start + length;
-    }
-    
+    /*
+     * Specification says Type 3 table has length of at least 0Dh (for v2.1+),
+     * which corresponds with the end of the "Security Status" field.
+     */
+
+    BUILD_BUG_ON(endof_field(struct smbios_type_3, security_status) != 13);
+
+    next = smbios_pt_copy(start, 3, SMBIOS_HANDLE_TYPE3,
+                          offsetof(struct smbios_type_3, security_status));
+    if ( next != start )
+        return next;
+
     memset(p, 0, sizeof(*p));
 
     p->header.type = 3;
@@ -656,6 +681,9 @@ smbios_type_4_init(
     struct smbios_type_4 *p = start;
     uint32_t eax, ebx, ecx, edx;
 
+    /* Specification says Type 4 table has length of 23h for v2.3+. */
+    BUILD_BUG_ON(sizeof(*p) != 35);
+
     memset(p, 0, sizeof(*p));
 
     p->header.type = 4;
@@ -707,17 +735,15 @@ smbios_type_11_init(void *start)
     struct smbios_type_11 *p = start;
     char path[20];
     const char *s;
+    void *next;
     int i;
-    void *pts;
-    uint32_t length;
 
-    pts = get_smbios_pt_struct(11, &length);
-    if ( pts != NULL && length > 0 )
-    {
-        memcpy(start, pts, length);
-        p->header.handle = SMBIOS_HANDLE_TYPE11;
-        return start + length;
-    }
+    /* Specification says Type 11 table has length of 05h. */
+    BUILD_BUG_ON(sizeof(*p) != 5);
+    
+    next = smbios_pt_copy(start, 11, SMBIOS_HANDLE_TYPE11, sizeof(*p));
+    if ( next != start )
+        return next;
 
     p->header.type = 11;
     p->header.length = sizeof(*p);
@@ -756,6 +782,9 @@ smbios_type_16_init(void *start, uint32_t memsize, int nr_mem_devs)
 {
     struct smbios_type_16 *p = start;
 
+    /* Specification says Type 16 table has length of 0Fh for v2.1-2.7. */
+    BUILD_BUG_ON(sizeof(*p) != 15);
+
     memset(p, 0, sizeof(*p));
 
     p->header.type = 16;
@@ -781,6 +810,9 @@ smbios_type_17_init(void *start, uint32_t memory_size_mb, int instance)
     char buf[16];
     struct smbios_type_17 *p = start;
 
+    /* Specification says Type 17 table has length of 1Bh for v2.3-2.6. */
+    BUILD_BUG_ON(sizeof(*p) != 27);
+
     memset(p, 0, sizeof(*p));
 
     p->header.type = 17;
@@ -816,6 +848,9 @@ smbios_type_19_init(void *start, uint32_t memory_size_mb, int instance)
 {
     struct smbios_type_19 *p = start;
 
+    /* Specification says Type 19 table has length of 0Fh for v2.1-2.7. */
+    BUILD_BUG_ON(sizeof(*p) != 15);
+
     memset(p, 0, sizeof(*p));
 
     p->header.type = 19;
@@ -838,6 +873,9 @@ smbios_type_20_init(void *start, uint32_t memory_size_mb, int instance)
 {
     struct smbios_type_20 *p = start;
 
+    /* Specification says Type 20 table has length of 13h for v2.1-2.7. */
+    BUILD_BUG_ON(sizeof(*p) != 19);
+
     memset(p, 0, sizeof(*p));
 
     p->header.type = 20;
@@ -865,16 +903,14 @@ smbios_type_22_init(void *start)
     struct smbios_type_22 *p = start;
     static const char *smbios_release_date = __SMBIOS_DATE__;
     const char *s;
-    void *pts;
-    uint32_t length;
+    void *next;
 
-    pts = get_smbios_pt_struct(22, &length);
-    if ( pts != NULL && length > 0 )
-    {
-        memcpy(start, pts, length);
-        p->header.handle = SMBIOS_HANDLE_TYPE22;
-        return start + length;
-    }
+    /* Specification says Type 22 table has length of 1Ah. */
+    BUILD_BUG_ON(sizeof(*p) != 26);
+
+    next = smbios_pt_copy(start, 22, SMBIOS_HANDLE_TYPE22, sizeof(*p));
+    if ( next != start )
+        return next;
 
     s = xenstore_read(HVM_XS_SMBIOS_DEFAULT_BATTERY, "0");
     if ( strncmp(s, "1", 1) != 0 )
@@ -929,6 +965,9 @@ smbios_type_32_init(void *start)
 {
     struct smbios_type_32 *p = start;
 
+    /* Specification says Type 32 table has length of at least 0Bh. */
+    BUILD_BUG_ON(sizeof(*p) != 11);
+
     memset(p, 0, sizeof(*p));
 
     p->header.type = 32;
@@ -946,20 +985,17 @@ smbios_type_32_init(void *start)
 static void *
 smbios_type_39_init(void *start)
 {
-    struct smbios_type_39 *p = start;
-    void *pts;
-    uint32_t length;
+    /*
+     * Specification says Type 39 table has length of at least 10h,
+     * which corresponds with the end of the "Characteristics" field.
+     *
+     * Only present when passed in.
+     */
 
-    pts = get_smbios_pt_struct(39, &length);
-    if ( pts != NULL && length > 0 )
-    {
-        memcpy(start, pts, length);
-        p->header.handle = SMBIOS_HANDLE_TYPE39;
-        return start + length;
-    }
+    BUILD_BUG_ON(endof_field(struct smbios_type_39, characteristics) != 16);
 
-    /* Only present when passed in */
-    return start;
+    return smbios_pt_copy(start, 39, SMBIOS_HANDLE_TYPE39,
+                          endof_field(struct smbios_type_39, characteristics));
 }
 
 static void *
diff --git a/tools/firmware/hvmloader/smbios_types.h b/tools/firmware/hvmloader/smbios_types.h
index 7c648ece71..a04d194975 100644
--- a/tools/firmware/hvmloader/smbios_types.h
+++ b/tools/firmware/hvmloader/smbios_types.h
@@ -90,13 +90,13 @@ struct smbios_type_2 {
     uint8_t product_name_str;
     uint8_t version_str;
     uint8_t serial_number_str;
-    uint8_t asset_tag_str;
-    uint8_t feature_flags;
-    uint8_t location_in_chassis_str;
-    uint16_t chassis_handle;
-    uint8_t board_type;
-    uint8_t contained_handle_count;
-    uint16_t contained_handles[];
+    uint8_t asset_tag_str;                  /* Optional */
+    uint8_t feature_flags;                  /* Optional */
+    uint8_t location_in_chassis_str;        /* Optional */
+    uint16_t chassis_handle;                /* Optional */
+    uint8_t board_type;                     /* Optional */
+    uint8_t contained_handle_count;         /* Optional */
+    uint16_t contained_handles[];           /* Optional */
 } __attribute__ ((packed));
 
 /* System Enclosure - Contained Elements */
@@ -118,12 +118,12 @@ struct smbios_type_3 {
     uint8_t power_supply_state;
     uint8_t thermal_state;
     uint8_t security_status;
-    uint32_t oem_specific;
-    uint8_t height;
-    uint8_t number_of_power_cords;
-    uint8_t contained_element_count;
-    uint8_t contained_element_length;
-    struct smbios_contained_element contained_elements[];
+    uint32_t oem_specific;                  /* Optional */
+    uint8_t height;                         /* Optional */
+    uint8_t number_of_power_cords;          /* Optional */
+    uint8_t contained_element_count;        /* Optional */
+    uint8_t contained_element_length;       /* Optional */
+    struct smbios_contained_element contained_elements[]; /* Optional */
 } __attribute__ ((packed));
 
 /* SMBIOS type 4 - Processor Information */
@@ -252,9 +252,9 @@ struct smbios_type_39 {
     uint8_t revision_level_str;
     uint16_t max_capacity;
     uint16_t characteristics;
-    uint16_t input_voltage_probe_handle;
-    uint16_t cooling_device_handle;
-    uint16_t input_current_probe_handle;
+    uint16_t input_voltage_probe_handle;    /* Optional */
+    uint16_t cooling_device_handle;         /* Optional */
+    uint16_t input_current_probe_handle;    /* Optional */
 } __attribute__ ((packed));
 
 /* SMBIOS type 127 -- End-of-table */
-- 
2.34.1



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To: xen-devel@lists.xenproject.org
Cc: =?UTF-8?q?Petr=20Bene=C5=A1?= ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v5 4/4] CHANGELOG.md: add new SMBIOS tables (7, 8, 9, 26, 27, 28)
Date: Sat, 23 Aug 2025 22:26:52 +0000
Message-Id: <3c9c7c48c9d8633b4c36bb0bb91fab88c03ae279.1755987697.git.w1benny@gmail.com>
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From: Petr Beneš 

Signed-off-by: Petr Beneš 
---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 271ac73a0a..2fd65b90a9 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -32,6 +32,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
      capability usage is not yet supported on PVH dom0).
    - Smoke tests for the FreeBSD Xen builds in Cirrus CI.
    - PVH xenstore-stubdom now supports Live Update.
+   - Support for new SMBIOS tables: 7, 8, 9, 26, 27, 28.
 
  - On Arm:
     - Ability to enable stack protector
-- 
2.34.1



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From: "=?UTF-8?q?Petr=20Bene=C5=A1?=" 
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To: xen-devel@lists.xenproject.org
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	Jan Beulich ,
	Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Anthony PERARD 
Subject: [PATCH v5 3/4] hvmloader: add new SMBIOS tables (7, 8, 9, 26, 27, 28)
Date: Sat, 23 Aug 2025 22:26:51 +0000
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From: Petr Beneš 

Some SMBIOS tables are used by certain malware families to detect virtualized
environments via WMI queries.

To improve stealth for sandboxing purposes, this patch adds support
for populating these SMBIOS tables from an external binary specified
via the "smbios_firmware" domain config option:

* 7 - Cache Info
* 8 - Port Connector
* 9 - System Slots
* 26 - Voltage Probe
* 27 - Cooling Device
* 28 - Temperature Probe

If particular table is absent in binary file, then it will not be mapped to
memory. This method works for Windows domains as tables 7,8,9,26,27,28 are not
critical for OS boot and runtime. Also if "smbios_firmware" parameter is not
provided, these tables will be skipped in write_smbios_tables function.

From: Anton Belousov 
Signed-off-by: Petr Beneš 
Acked-by: Jan Beulich 
---
 tools/firmware/hvmloader/smbios.c       | 111 ++++++++++++++++++++++++
 tools/firmware/hvmloader/smbios_types.h |  77 ++++++++++++++++
 2 files changed, 188 insertions(+)

diff --git a/tools/firmware/hvmloader/smbios.c b/tools/firmware/hvmloader/smbios.c
index de3ba78e87..76c7090d16 100644
--- a/tools/firmware/hvmloader/smbios.c
+++ b/tools/firmware/hvmloader/smbios.c
@@ -33,12 +33,18 @@
 #define SMBIOS_HANDLE_TYPE2   0x0200
 #define SMBIOS_HANDLE_TYPE3   0x0300
 #define SMBIOS_HANDLE_TYPE4   0x0400
+#define SMBIOS_HANDLE_TYPE7   0x0700
+#define SMBIOS_HANDLE_TYPE8   0x0800
+#define SMBIOS_HANDLE_TYPE9   0x0900
 #define SMBIOS_HANDLE_TYPE11  0x0B00
 #define SMBIOS_HANDLE_TYPE16  0x1000
 #define SMBIOS_HANDLE_TYPE17  0x1100
 #define SMBIOS_HANDLE_TYPE19  0x1300
 #define SMBIOS_HANDLE_TYPE20  0x1400
 #define SMBIOS_HANDLE_TYPE22  0x1600
+#define SMBIOS_HANDLE_TYPE26  0x1A00
+#define SMBIOS_HANDLE_TYPE27  0x1B00
+#define SMBIOS_HANDLE_TYPE28  0x1C00
 #define SMBIOS_HANDLE_TYPE32  0x2000
 #define SMBIOS_HANDLE_TYPE39  0x2700
 #define SMBIOS_HANDLE_TYPE127 0x7f00
@@ -79,6 +85,12 @@ static void *
 smbios_type_4_init(void *start, unsigned int cpu_number,
                    char *cpu_manufacturer);
 static void *
+smbios_type_7_init(void *start);
+static void *
+smbios_type_8_init(void *start);
+static void *
+smbios_type_9_init(void *start);
+static void *
 smbios_type_11_init(void *start);
 static void *
 smbios_type_16_init(void *start, uint32_t memory_size_mb, int nr_mem_devs);
@@ -91,6 +103,12 @@ smbios_type_20_init(void *start, uint32_t memory_size_mb, int instance);
 static void *
 smbios_type_22_init(void *start);
 static void *
+smbios_type_26_init(void *start);
+static void *
+smbios_type_27_init(void *start);
+static void *
+smbios_type_28_init(void *start);
+static void *
 smbios_type_32_init(void *start);
 static void *
 smbios_type_39_init(void *start);
@@ -225,6 +243,9 @@ write_smbios_tables(void *ep, void *start,
     do_struct(smbios_type_3_init(p));
     for ( cpu_num = 1; cpu_num <= vcpus; cpu_num++ )
         do_struct(smbios_type_4_init(p, cpu_num, cpu_manufacturer));
+    do_struct(smbios_type_7_init(p));
+    do_struct(smbios_type_8_init(p));
+    do_struct(smbios_type_9_init(p));
     do_struct(smbios_type_11_init(p));
 
     /* Each 'memory device' covers up to 16GB of address space. */
@@ -241,6 +262,9 @@ write_smbios_tables(void *ep, void *start,
     }
 
     do_struct(smbios_type_22_init(p));
+    do_struct(smbios_type_26_init(p));
+    do_struct(smbios_type_27_init(p));
+    do_struct(smbios_type_28_init(p));
     do_struct(smbios_type_32_init(p));
     do_struct(smbios_type_39_init(p));
     do_struct(smbios_type_vendor_oem_init(p));
@@ -728,6 +752,42 @@ smbios_type_4_init(
     return start+1;
 }
 
+/* Type 7 -- Cache Information */
+static void *
+smbios_type_7_init(void *start)
+{
+    /* Specification says Type 7 table has length of 13h for v2.1+. */
+    BUILD_BUG_ON(sizeof(struct smbios_type_7) != 19);
+
+    /* Only present when passed in. */
+    return smbios_pt_copy(start, 7, SMBIOS_HANDLE_TYPE7,
+                          sizeof(struct smbios_type_7));
+}
+
+/* Type 8 -- Port Connector Information */
+static void *
+smbios_type_8_init(void *start)
+{
+    /* Specification says Type 8 table has length of 09h. */
+    BUILD_BUG_ON(sizeof(struct smbios_type_8) != 9);
+
+    /* Only present when passed in. */
+    return smbios_pt_copy(start, 8, SMBIOS_HANDLE_TYPE8,
+                          sizeof(struct smbios_type_8));
+}
+
+/* Type 9 -- System Slots */
+static void *
+smbios_type_9_init(void *start)
+{
+    /* Specification says Type 9 table has length of 0Dh for v2.1-2.5. */
+    BUILD_BUG_ON(sizeof(struct smbios_type_9) != 13);
+
+    /* Only present when passed in. */
+    return smbios_pt_copy(start, 9, SMBIOS_HANDLE_TYPE9,
+                          sizeof(struct smbios_type_9));
+}
+
 /* Type 11 -- OEM Strings */
 static void *
 smbios_type_11_init(void *start)
@@ -959,6 +1019,57 @@ smbios_type_22_init(void *start)
     return start + 1;
 }
 
+/* Type 26 -- Voltage Probe */
+static void *
+smbios_type_26_init(void *start)
+{
+    /*
+     * Specification says Type 26 table has length of at least 14h,
+     * which corresponds with the end of the "OEM-defined" field.
+     *
+     * Only present when passed in.
+     */
+
+    BUILD_BUG_ON(endof_field(struct smbios_type_26, oem_defined) != 20);
+
+    return smbios_pt_copy(start, 26, SMBIOS_HANDLE_TYPE26,
+                          endof_field(struct smbios_type_26, oem_defined));
+}
+
+/* Type 27 -- Cooling Device */
+static void *
+smbios_type_27_init(void *start)
+{
+    /*
+     * Specification says Type 27 table has length of at least 0Ch,
+     * which corresponds with the end of the "OEM-defined" field.
+     *
+     * Only present when passed in.
+     */
+
+    BUILD_BUG_ON(endof_field(struct smbios_type_27, oem_defined) != 12);
+ 
+    return smbios_pt_copy(start, 27, SMBIOS_HANDLE_TYPE27,
+                          endof_field(struct smbios_type_27, oem_defined));
+}
+
+/* Type 28 -- Temperature Probe */
+static void *
+smbios_type_28_init(void *start)
+{
+    /*
+     * Specification says Type 28 table has length of at least 14h,
+     * which corresponds with the end of the "OEM-defined" field.
+     *
+     * Only present when passed in.
+     */
+
+    BUILD_BUG_ON(endof_field(struct smbios_type_28, oem_defined) != 20);
+
+    return smbios_pt_copy(start, 28, SMBIOS_HANDLE_TYPE28,
+                          endof_field(struct smbios_type_28, oem_defined));
+}
+
 /* Type 32 -- System Boot Information */
 static void *
 smbios_type_32_init(void *start)
diff --git a/tools/firmware/hvmloader/smbios_types.h b/tools/firmware/hvmloader/smbios_types.h
index a04d194975..c04b435d31 100644
--- a/tools/firmware/hvmloader/smbios_types.h
+++ b/tools/firmware/hvmloader/smbios_types.h
@@ -149,6 +149,44 @@ struct smbios_type_4 {
     uint8_t part_number_str;
 } __attribute__ ((packed));
 
+/* SMBIOS type 7 - Cache Information */
+struct smbios_type_7 {
+    struct smbios_structure_header header;
+    uint8_t socket_designation_str;
+    uint16_t cache_configuration;
+    uint16_t maximum_cache_size;
+    uint16_t installed_size;
+    uint16_t supported_SRAM_type;
+    uint16_t current_SRAM_type;
+    uint8_t cache_speed;
+    uint8_t error_connection_type;
+    uint8_t system_cache_type;
+    uint8_t associativity;
+} __attribute__ ((packed));
+
+/* SMBIOS type 8 - Port Connector Information */
+struct smbios_type_8 {
+    struct smbios_structure_header header;
+    uint8_t internal_reference_designator_str;
+    uint8_t internal_connector_type;
+    uint8_t external_reference_designator_str;
+    uint8_t external_connector_type;
+    uint8_t port_type;
+} __attribute__ ((packed));
+
+/* SMBIOS type 9 - System Slots */
+struct smbios_type_9 {
+    struct smbios_structure_header header;
+    uint8_t slot_designation_str;
+    uint8_t slot_type;
+    uint8_t slot_data_bus_width;
+    uint8_t current_usage;
+    uint8_t slot_length;
+    uint16_t slot_id;
+    uint8_t slot_characteristics_1;
+    uint8_t slot_characteristics_2;
+} __attribute__ ((packed));
+
 /* SMBIOS type 11 - OEM Strings */
 struct smbios_type_11 {
     struct smbios_structure_header header;
@@ -232,6 +270,45 @@ struct smbios_type_22 {
     uint32_t oem_specific;
 } __attribute__ ((packed));
 
+/* SMBIOS type 26 - Voltage Probe */
+struct smbios_type_26 {
+    struct smbios_structure_header header;
+    uint8_t description_str;
+    uint8_t location_and_status;
+    uint16_t maximum_value;
+    uint16_t minimum_value;
+    uint16_t resolution;
+    uint16_t tolerance;
+    uint16_t accuracy;
+    uint32_t oem_defined;
+    uint16_t nominal_value;                 /* Optional */
+} __attribute__ ((packed));
+
+/* SMBIOS type 27 - Cooling Device */
+struct smbios_type_27 {
+    struct smbios_structure_header header;
+    uint16_t temperature_probe_handle;
+    uint8_t device_type_and_status;
+    uint8_t cooling_unit_group;
+    uint32_t oem_defined;
+    uint16_t nominal_speed;                 /* Optional */
+    uint8_t description_str;                /* Optional */
+} __attribute__ ((packed));
+
+/* SMBIOS type 28 - Temperature Probe */
+struct smbios_type_28 {
+    struct smbios_structure_header header;
+    uint8_t description_str;
+    uint8_t location_and_status;
+    uint16_t maximum_value;
+    uint16_t minimum_value;
+    uint16_t resolution;
+    uint16_t tolerance;
+    uint16_t accuracy;
+    uint32_t oem_defined;
+    uint16_t nominal_value;                 /* Optional */
+} __attribute__ ((packed));
+
 /* SMBIOS type 32 - System Boot Information */
 struct smbios_type_32 {
     struct smbios_structure_header header;
-- 
2.34.1



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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[PATCH=20v5=202/4]=20hvmloader:=20fix=20SMBIOS=20table=20length=20checks?=
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Cc: "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" 
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Hello,

Le 24/08/2025 =C3=A0 00:29, Petr Bene=C5=A1 a =C3=A9crit=C2=A0:
> From: Petr Bene=C5=A1 
> 
> SMBIOS specification dictates that tables should have a minimal length.
> This commit introduces further validation for user-input SMBIOS tables.
> 
> As per SMBIOS Reference Specification:
> * Type 0: For version 2.3 and later implementations, the length is at lea=
st 14h
> * Type 1: 1Bh for 2.4 and later
> * Type 2: at least 08h
> * Type 3: 0Dh for version 2.1 and later
> * Type 11: 5h (+ strings)
> * Type 22: 1Ah (+ strings)
> * Type 39: a minimum of 10h
> 
> Notably, this also fixes previously incorrect check for chassis handle in
> smbios_type_2_init. Chassis handle is a WORD, therefore, the condition no=
w
> correctly checks for >=3D 13 instead of > 13.
> 
> hvmloader currently implements version 2.4
> 
> Furthermore, this commit introduces smbios_pt_copy helper function to sub=
stitute
> previously repeating pattern of locating the struct in physical memory (v=
ia
> get_smbios_pt_struct), checking the length and copying it into SMBIOS reg=
ion.
> 
> Signed-off-by: Petr Bene=C5=A1 
> Acked-by: Jan Beulich 
> ---
>   tools/firmware/hvmloader/smbios.c       | 178 ++++++++++++++----------
>   tools/firmware/hvmloader/smbios_types.h |  32 ++---
>   2 files changed, 123 insertions(+), 87 deletions(-)
> 
> diff --git a/tools/firmware/hvmloader/smbios.c b/tools/firmware/hvmloader=
/smbios.c
> index 6bcdcc233a..de3ba78e87 100644
> --- a/tools/firmware/hvmloader/smbios.c
> +++ b/tools/firmware/hvmloader/smbios.c
> @@ -47,6 +47,8 @@ static void
>   smbios_pt_init(void);
>   static void*
>   get_smbios_pt_struct(uint8_t type, uint32_t *length_out);
> +static void *
> +smbios_pt_copy(void *start, uint8_t type, uint16_t handle, size_t table_=
size);
>   static void
>   get_cpu_manufacturer(char *buf, int len);
>   static int
> @@ -154,6 +156,24 @@ get_smbios_pt_struct(uint8_t type, uint32_t *length_=
out)
>       return NULL;
>   }
>   
> +static void *
> +smbios_pt_copy(void *start, uint8_t type, uint16_t handle, size_t min_si=
ze)
> +{
> +    struct smbios_structure_header *header =3D start;
> +    void *pts;
> +    uint32_t length;
> +
> +    pts =3D get_smbios_pt_struct(type, &length);
> +    if ( pts !=3D NULL && length >=3D min_size )
> +    {
> +        memcpy(start, pts, length);
> +        header->handle =3D handle;
> +        return start + length;
> +    }
> +
> +    return start;
> +}
> +
>   static void
>   get_cpu_manufacturer(char *buf, int len)
>   {
> @@ -381,16 +401,17 @@ smbios_type_0_init(void *start, const char *xen_ver=
sion,
>       struct smbios_type_0 *p =3D start;
>       static const char *smbios_release_date =3D __SMBIOS_DATE__;
>       const char *s;
> -    void *pts;
> -    uint32_t length;
> +    void *next;
>   
> -    pts =3D get_smbios_pt_struct(0, &length);
> -    if ( pts !=3D NULL && length > 0 )
> -    {
> -        memcpy(start, pts, length);
> -        p->header.handle =3D SMBIOS_HANDLE_TYPE0;
> -        return start + length;
> -    }
> +    /*
> +     * Specification says Type 0 table has length of at least 18h for v2=
.4-3.0.
> +     */
> +
> +    BUILD_BUG_ON(sizeof(*p) !=3D 24);
> +
> +    next =3D smbios_pt_copy(start, 0, SMBIOS_HANDLE_TYPE0, sizeof(*p));
> +    if ( next !=3D start )
> +        return next;
>   
>       memset(p, 0, sizeof(*p));
>   
> @@ -440,16 +461,14 @@ smbios_type_1_init(void *start, const char *xen_ver=
sion,
>       char uuid_str[37];
>       struct smbios_type_1 *p =3D start;
>       const char *s;
> -    void *pts;
> -    uint32_t length;
> +    void *next;
>   
> -    pts =3D get_smbios_pt_struct(1, &length);
> -    if ( pts !=3D NULL && length > 0 )
> -    {
> -        memcpy(start, pts, length);
> -        p->header.handle =3D SMBIOS_HANDLE_TYPE1;
> -        return start + length;
> -    }
> +    /* Specification says Type 1 table has length of 1Bh for v2.4 and la=
ter. */
> +    BUILD_BUG_ON(sizeof(*p) !=3D 27);
> +
> +    next =3D smbios_pt_copy(start, 1, SMBIOS_HANDLE_TYPE1, sizeof(*p));
> +    if ( next !=3D start )
> +        return next;
>   
>       memset(p, 0, sizeof(*p));
>   
> @@ -498,26 +517,29 @@ smbios_type_2_init(void *start)
>   {
>       struct smbios_type_2 *p =3D start;
>       const char *s;
> -    uint8_t *ptr;
> -    void *pts;
> -    uint32_t length;
> +    void *next;
>       unsigned int counter =3D 0;
>   
> -    pts =3D get_smbios_pt_struct(2, &length);
> -    if ( pts !=3D NULL && length > 0 )
> -    {
> -        memcpy(start, pts, length);
> -        p->header.handle =3D SMBIOS_HANDLE_TYPE2;
> +    /*
> +     * Specification says Type 2 table has length of at least 08h,
> +     * which corresponds with the end of the "Serial Number" field.
> +     */
> +
> +    BUILD_BUG_ON(endof_field(struct smbios_type_2, serial_number_str) !=
=3D 8);
>   
> +    next =3D smbios_pt_copy(start, 2, SMBIOS_HANDLE_TYPE2,
> +                          endof_field(struct smbios_type_2, serial_numbe=
r_str));
> +    if ( next !=3D start )
> +    {
>           /* Set current chassis handle if present */
> -        if ( p->header.length > 13 )
> +        if ( p->header.length >=3D endof_field(struct smbios_type_2,
> +                                             chassis_handle) )
>           {
> -            ptr =3D ((uint8_t*)start) + 11;
> -            if ( *((uint16_t*)ptr) !=3D 0 )
> -                *((uint16_t*)ptr) =3D SMBIOS_HANDLE_TYPE3;
> +            if ( p->chassis_handle !=3D 0 )
> +                p->chassis_handle =3D SMBIOS_HANDLE_TYPE3;
>           }
>   
> -        return start + length;
> +        return next;
>       }
>   
>       memset(p, 0, sizeof(*p));
> @@ -593,18 +615,21 @@ smbios_type_3_init(void *start)
>   {
>       struct smbios_type_3 *p =3D start;
>       const char *s;
> -    void *pts;
> -    uint32_t length;
> +    void *next;
>       uint32_t counter =3D 0;
>   
> -    pts =3D get_smbios_pt_struct(3, &length);
> -    if ( pts !=3D NULL && length > 0 )
> -    {
> -        memcpy(start, pts, length);
> -        p->header.handle =3D SMBIOS_HANDLE_TYPE3;
> -        return start + length;
> -    }
> -
> +    /*
> +     * Specification says Type 3 table has length of at least 0Dh (for v=
2.1+),
> +     * which corresponds with the end of the "Security Status" field.
> +     */
> +
> +    BUILD_BUG_ON(endof_field(struct smbios_type_3, security_status) !=3D=
 13);
> +
> +    next =3D smbios_pt_copy(start, 3, SMBIOS_HANDLE_TYPE3,
> +                          offsetof(struct smbios_type_3, security_status=
));
> +    if ( next !=3D start )
> +        return next;
> +
>       memset(p, 0, sizeof(*p));
>   
>       p->header.type =3D 3;
> @@ -656,6 +681,9 @@ smbios_type_4_init(
>       struct smbios_type_4 *p =3D start;
>       uint32_t eax, ebx, ecx, edx;
>   
> +    /* Specification says Type 4 table has length of 23h for v2.3+. */
> +    BUILD_BUG_ON(sizeof(*p) !=3D 35);
> +
>       memset(p, 0, sizeof(*p));
>   
>       p->header.type =3D 4;
> @@ -707,17 +735,15 @@ smbios_type_11_init(void *start)
>       struct smbios_type_11 *p =3D start;
>       char path[20];
>       const char *s;
> +    void *next;
>       int i;
> -    void *pts;
> -    uint32_t length;
>   
> -    pts =3D get_smbios_pt_struct(11, &length);
> -    if ( pts !=3D NULL && length > 0 )
> -    {
> -        memcpy(start, pts, length);
> -        p->header.handle =3D SMBIOS_HANDLE_TYPE11;
> -        return start + length;
> -    }
> +    /* Specification says Type 11 table has length of 05h. */
> +    BUILD_BUG_ON(sizeof(*p) !=3D 5);
> +
> +    next =3D smbios_pt_copy(start, 11, SMBIOS_HANDLE_TYPE11, sizeof(*p))=
;
> +    if ( next !=3D start )
> +        return next;
>   
>       p->header.type =3D 11;
>       p->header.length =3D sizeof(*p);
> @@ -756,6 +782,9 @@ smbios_type_16_init(void *start, uint32_t memsize, in=
t nr_mem_devs)
>   {
>       struct smbios_type_16 *p =3D start;
>   
> +    /* Specification says Type 16 table has length of 0Fh for v2.1-2.7. =
*/
> +    BUILD_BUG_ON(sizeof(*p) !=3D 15);
> +
>       memset(p, 0, sizeof(*p));
>   
>       p->header.type =3D 16;
> @@ -781,6 +810,9 @@ smbios_type_17_init(void *start, uint32_t memory_size=
_mb, int instance)
>       char buf[16];
>       struct smbios_type_17 *p =3D start;
>   
> +    /* Specification says Type 17 table has length of 1Bh for v2.3-2.6. =
*/
> +    BUILD_BUG_ON(sizeof(*p) !=3D 27);
> +
>       memset(p, 0, sizeof(*p));
>   
>       p->header.type =3D 17;
> @@ -816,6 +848,9 @@ smbios_type_19_init(void *start, uint32_t memory_size=
_mb, int instance)
>   {
>       struct smbios_type_19 *p =3D start;
>   
> +    /* Specification says Type 19 table has length of 0Fh for v2.1-2.7. =
*/
> +    BUILD_BUG_ON(sizeof(*p) !=3D 15);
> +
>       memset(p, 0, sizeof(*p));
>   
>       p->header.type =3D 19;
> @@ -838,6 +873,9 @@ smbios_type_20_init(void *start, uint32_t memory_size=
_mb, int instance)
>   {
>       struct smbios_type_20 *p =3D start;
>   
> +    /* Specification says Type 20 table has length of 13h for v2.1-2.7. =
*/
> +    BUILD_BUG_ON(sizeof(*p) !=3D 19);

Note that OVMF does replace the SMBIOS version to 2.8 which may 
eventually invalidate what you expect (assuming the length only holds 
for the versions you give in your comments).

I don't know enough SMBIOS and OVMF to know if it can be a problem (OVMF 
may do some conversions in these cases).

> +
>       memset(p, 0, sizeof(*p));
>   
>       p->header.type =3D 20;
> @@ -865,16 +903,14 @@ smbios_type_22_init(void *start)
>       struct smbios_type_22 *p =3D start;
>       static const char *smbios_release_date =3D __SMBIOS_DATE__;
>       const char *s;
> -    void *pts;
> -    uint32_t length;
> +    void *next;
>   
> -    pts =3D get_smbios_pt_struct(22, &length);
> -    if ( pts !=3D NULL && length > 0 )
> -    {
> -        memcpy(start, pts, length);
> -        p->header.handle =3D SMBIOS_HANDLE_TYPE22;
> -        return start + length;
> -    }
> +    /* Specification says Type 22 table has length of 1Ah. */
> +    BUILD_BUG_ON(sizeof(*p) !=3D 26);
> +
> +    next =3D smbios_pt_copy(start, 22, SMBIOS_HANDLE_TYPE22, sizeof(*p))=
;
> +    if ( next !=3D start )
> +        return next;
>   
>       s =3D xenstore_read(HVM_XS_SMBIOS_DEFAULT_BATTERY, "0");
>       if ( strncmp(s, "1", 1) !=3D 0 )
> @@ -929,6 +965,9 @@ smbios_type_32_init(void *start)
>   {
>       struct smbios_type_32 *p =3D start;
>   
> +    /* Specification says Type 32 table has length of at least 0Bh. */
> +    BUILD_BUG_ON(sizeof(*p) !=3D 11);
> +
>       memset(p, 0, sizeof(*p));
>   
>       p->header.type =3D 32;
> @@ -946,20 +985,17 @@ smbios_type_32_init(void *start)
>   static void *
>   smbios_type_39_init(void *start)
>   {
> -    struct smbios_type_39 *p =3D start;
> -    void *pts;
> -    uint32_t length;
> +    /*
> +     * Specification says Type 39 table has length of at least 10h,
> +     * which corresponds with the end of the "Characteristics" field.
> +     *
> +     * Only present when passed in.
> +     */
>   
> -    pts =3D get_smbios_pt_struct(39, &length);
> -    if ( pts !=3D NULL && length > 0 )
> -    {
> -        memcpy(start, pts, length);
> -        p->header.handle =3D SMBIOS_HANDLE_TYPE39;
> -        return start + length;
> -    }
> +    BUILD_BUG_ON(endof_field(struct smbios_type_39, characteristics) !=
=3D 16);
>   
> -    /* Only present when passed in */
> -    return start;
> +    return smbios_pt_copy(start, 39, SMBIOS_HANDLE_TYPE39,
> +                          endof_field(struct smbios_type_39, characteris=
tics));
>   }
>   
>   static void *
> diff --git a/tools/firmware/hvmloader/smbios_types.h b/tools/firmware/hvm=
loader/smbios_types.h
> index 7c648ece71..a04d194975 100644
> --- a/tools/firmware/hvmloader/smbios_types.h
> +++ b/tools/firmware/hvmloader/smbios_types.h
> @@ -90,13 +90,13 @@ struct smbios_type_2 {
>       uint8_t product_name_str;
>       uint8_t version_str;
>       uint8_t serial_number_str;
> -    uint8_t asset_tag_str;
> -    uint8_t feature_flags;
> -    uint8_t location_in_chassis_str;
> -    uint16_t chassis_handle;
> -    uint8_t board_type;
> -    uint8_t contained_handle_count;
> -    uint16_t contained_handles[];
> +    uint8_t asset_tag_str;                  /* Optional */
> +    uint8_t feature_flags;                  /* Optional */
> +    uint8_t location_in_chassis_str;        /* Optional */
> +    uint16_t chassis_handle;                /* Optional */
> +    uint8_t board_type;                     /* Optional */
> +    uint8_t contained_handle_count;         /* Optional */
> +    uint16_t contained_handles[];           /* Optional */
>   } __attribute__ ((packed));
>   
>   /* System Enclosure - Contained Elements */
> @@ -118,12 +118,12 @@ struct smbios_type_3 {
>       uint8_t power_supply_state;
>       uint8_t thermal_state;
>       uint8_t security_status;
> -    uint32_t oem_specific;
> -    uint8_t height;
> -    uint8_t number_of_power_cords;
> -    uint8_t contained_element_count;
> -    uint8_t contained_element_length;
> -    struct smbios_contained_element contained_elements[];
> +    uint32_t oem_specific;                  /* Optional */
> +    uint8_t height;                         /* Optional */
> +    uint8_t number_of_power_cords;          /* Optional */
> +    uint8_t contained_element_count;        /* Optional */
> +    uint8_t contained_element_length;       /* Optional */
> +    struct smbios_contained_element contained_elements[]; /* Optional */
>   } __attribute__ ((packed));
>   
>   /* SMBIOS type 4 - Processor Information */
> @@ -252,9 +252,9 @@ struct smbios_type_39 {
>       uint8_t revision_level_str;
>       uint16_t max_capacity;
>       uint16_t characteristics;
> -    uint16_t input_voltage_probe_handle;
> -    uint16_t cooling_device_handle;
> -    uint16_t input_current_probe_handle;
> +    uint16_t input_voltage_probe_handle;    /* Optional */
> +    uint16_t cooling_device_handle;         /* Optional */
> +    uint16_t input_current_probe_handle;    /* Optional */
>   } __attribute__ ((packed));
>   
>   /* SMBIOS type 127 -- End-of-table */



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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Cc: Jan Beulich ,
        Demi Marie Obenour ,
        xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org,
        Stefano Stabellini ,
        Bertrand Marquis ,
        Michal Orzel ,
        Volodymyr Babchuk ,
        Paul Leiber 
Subject: Re: Consider changing CONFIG_ACPI default on ARM?
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On Sat, Aug 23, 2025 at 08:59:13AM +0100, Julien Grall wrote:
> 
> On 22/08/2025 21:09, Elliott Mitchell wrote:
> > Since you're not pointing to anything definite, could it be everything
> > has been resolved?
> 
> Unfortunately, the situation has not changed since your last thread about
> enabling CONFIG_ACPI=y a couple of years ago. The main feature we are
> lacking is the parsing the IORT (used to discover SMMUs and MSI
> controllers). Without this...

No one to sponsor this work?  Disappointing with how far ACPI support had
gotten.  Surprising the funding ended here.

> >  We've got at least two people for whom ACPI on ARM
> > works pretty well.
> 
> ... Xen will only properly boot on "simple" case like the Raspberry PI.
> Also, IIRC Xen would use ACPI rather than Device-Tree by default.

What is the "improper" booting on non-simple cases like?  panic()?
Domain 0 boots, but the system isn't properly protected by the SMMU?
Ideally it would be runtime configurable with the former being the
default, but the panic message indicating how to override to produce the
latter.  Perhaps even accompanied by an invitation for sponsorship.

Yet handling those simple cases would help many people.  For a long time
IO-MMUs were rare, yet the world did not end.

> > There may be many more using it.  Perhaps this
> > should even be done on the 4.20 branch given how long this has been
> > working?
> 
> I am guessing you mean 4.21 which will be released in a couple of months
> time, correct?

As it is very simple to flip the default, I was thinking it might be
worthwhile to change it on earlier versions too.  After all it has
actually been known to work for kind of a long time.

> We have been discussing among the committers on whether we are ok to enable
> ACPI despite the fact it is still not feature complete (see above). The
> discussion is not fully finalized but if we were to enable CONFIG_ACPI=y by
> default then I think we would need the following:
> 
>  * Select device-tree by default rather than ACPI
>  * Go through SUPPORT.MD and check what features we marked as SUPPORTED.md
> but doesn't work on ACPI.
> 
> Maybe you can help with that?

I'm not sure this is a good role for me.  I suppose I could do a first
pass marking everything as non-ACPI.  Problem is most recently I've been
focussing on another aspect and I would mostly be guessing about things.

> Out of interest, sorry if this was already mentioned before, is there any
> reason ACPI is used on the Raspberry PI over Device-Tree? Is there any issue
> with the latter on Xen?

Issue is various Linux distributions have differing levels of support for
various targets.  Nearly everyone has some degree of support for
Raspberry PI (even Tianocore!), but the quality does vary from
distribution to distribution.

My favored distribution is rather limited in what it does for !x86.
Everything gets built for !x86, but things such as booting hasn't been
heavily looked at.  There is agreement using U-Boot/UEFI => GRUB would
likely be a Good Thing, but there is a shortage of people with the right
expertise to get that working.  As a result booting Xen is troublesome.

Whereas copying the Tianocore firmware into place and getting it booting
is *extremely* simple.  Further this has very few restrictions (GPT and
a ~200MB FAT filesystem).  Better yet once in place this is extremely
robust.

The only argument in favor of device-trees I've seen is that they're easy
to deal with.  Certainly they need little runtime processing.  Yet they
come with a major weakness that they're really part of the kernel.  When
the Linux kernel is replaced (even patch-level differences) you pretty
well always need to replace the device-trees.  Once you've done that it
is quite difficult to go back to the earlier kernel.

New device-trees often cause older kernels to panic or malfunction.  If
storage is on USB you can unplug and adjust on a nearby desktop, but this
means you need to keep another system handy.  Whereas due to being well
isolated from the OS, the same set of ACPI tables works for many OSes and
nearly all versions of Linux.

The instances of ACPI tables which worked with Windows, but failed for
other operating systems are quite famous.  The instances where a given
set of device-trees work with Linux, but then fail with other OSes
(or even merely different version of Linux) are not notable.  In fact
instances where device-trees *don't* change drastically between kernel
minor versions are newsworthy.


> > The one remaining major issue was the state of EFI-FB support.  There
> > was a patch which had that working for Linux kernel 5.10, but that might
> > need more work for a proper solution.
> 
> Yes. And there was no interest from the other members to fix it properly. So
> I gave up that on that work as I don't have a particular interest of using
> FrameBuffer on the raspberry PI. Feel free to revive it and I would be happy
> to review them.

Uhm, I thought I had expressed a strong desire to have it operational.
My knowledge of ACPI is rather limited, but I am well-setup for debugging
ARM (unlike x86 which is intended for serious work).

As mentioned by others it is kind of a popular platform.  I dislike the
thought of giving it special status merely due to that, but it is rather
readily available.


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Subject: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
Thread-Topic: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
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MISRA C Rule 2.1 states: "A project shall not contain unreachable code".
Functions that are non-returning and are not explicitly annotated with
the 'noreturn' attribute are considered a violation of this rule.

In certain cases, some functions might be non-returning in specific build
configurations due to call to '__builtin_unreachable()' in the expansion
of the macro 'BUG()':
 - functions 'gicv3_do_LPI()' and 'gicv3_its_setup_collection()' when the
config CONFIG_HAS_ITS is not defined, it is intentionally used to catch
and prevent any unintended execution of code that should only run when
ITS is available;
 - function 'prepare_acpi()' when the config CONFIG_ACPI is not defined,
to trigger an error if ACPI-related features are used incorrectly.

To account for that in specific builds, update the ECLAIR configuration
to deviate these violations. Update deviations.rst file accordingly.
No functional changes.

Signed-off-by: Dmytro Prokopchuk 
---
Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/2000738682
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 11 +++++++++++
 docs/misra/deviations.rst                        | 13 +++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index 7f3fd35a33..336aec58c2 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -41,6 +41,17 @@ not executable, and therefore it is safe for them to be =
unreachable."
 -call_properties+=3D{"name(__builtin_unreachable)&&stmt(begin(any_exp(macr=
o(name(ASSERT_UNREACHABLE)))))", {"noreturn(false)"}}
 -doc_end
=20
+-doc_begin=3D"The 'BUG()' macro is intentionally used in the 'prepare_acpi=
()' function in specific build configuration
+(when the config CONFIG_ACPI is not defined) to trigger an error if ACPI-r=
elated features are used incorrectly."
+-config=3DMC3A2.R2.1,reports+=3D{deliberate, "any_area(any_loc(file(^xen/a=
rch/arm/include/asm/domain_build\\.h$))&&context(name(prepare_acpi)))"}
+-doc_end
+
+-doc_begin=3D"The 'BUG()' macro is intentionally used in 'gicv3_do_LPI'() =
and 'gicv3_its_setup_collection()' functions
+in specific build configuration (when the config CONFIG_HAS_ITS is not def=
ined) to catch and prevent any unintended
+execution of code that should only run when ITS is available."
+-config=3DMC3A2.R2.1,reports+=3D{deliberate, "any_area(any_loc(file(^xen/a=
rch/arm/include/asm/gic_v3_its\\.h$))&&context(name(gicv3_do_LPI||gicv3_its=
_setup_collection)))"}
+-doc_end
+
 -doc_begin=3D"Proving compliance with respect to Rule 2.2 is generally imp=
ossible:
 see https://arxiv.org/abs/2212.13933 for details. Moreover, peer review gi=
ves us
 confidence that no evidence of errors in the program's logic has been miss=
ed due
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..96eb202502 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -97,6 +97,19 @@ Deviations related to MISRA C:2012 Rules:
        Xen expects developers to ensure code remains safe and reliable in =
builds,
        even when debug-only assertions like `ASSERT_UNREACHABLE() are remo=
ved.
=20
+   * - R2.1
+     - The 'BUG()' macro is intentionally used in the 'prepare_acpi()' fun=
ction
+       in specific build configuration (when the config CONFIG_ACPI is not
+       defined) to trigger an error if ACPI-related features are used inco=
rrectly.
+     - Tagged as `deliberate` for ECLAIR.
+
+   * - R2.1
+     - The 'BUG()' macro is intentionally used in 'gicv3_do_LPI'() and
+       'gicv3_its_setup_collection()' functions in specific build configur=
ation
+       (when the config CONFIG_HAS_ITS is not defined) to catch and preven=
t any
+       unintended execution of code that should only run when ITS is avail=
able.
+     - Tagged as `deliberate` for ECLAIR.
+
    * - R2.2
      - Proving compliance with respect to Rule 2.2 is generally impossible=
:
        see ``_ for details. Moreover, pe=
er
--=20
2.43.0


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , "Daniel P. Smith"
	,
	=?utf-8?B?TWFyZWsgTWFyY3p5a293c2tpLUfDs3JlY2tp?=
	, Jan Beulich 
Subject: [PATCH v4] common/efi: fix Rule 2.1 violation in read_file()
Thread-Topic: [PATCH v4] common/efi: fix Rule 2.1 violation in read_file()
Thread-Index: AQHcFQlF20ah2tP5uUOdXQ1Ea/l40w==
Date: Sun, 24 Aug 2025 15:10:47 +0000
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MIME-Version: 1.0
Date: Sun, 24 Aug 2025 17:29:58 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, Doug Goldstein ,
 Stefano Stabellini , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Jan Beulich , Julien
 Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
Subject: Re: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
In-Reply-To: 
References: 
Message-ID: <7d0b9e8e296ea07b966832b9a047baa7@bugseng.com>
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On 2025-08-24 16:56, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 2.1 states: "A project shall not contain unreachable 
> code".
> Functions that are non-returning and are not explicitly annotated with
> the 'noreturn' attribute are considered a violation of this rule.
> 
> In certain cases, some functions might be non-returning in specific 
> build
> configurations due to call to '__builtin_unreachable()' in the 
> expansion
> of the macro 'BUG()':
>  - functions 'gicv3_do_LPI()' and 'gicv3_its_setup_collection()' when 
> the
> config CONFIG_HAS_ITS is not defined, it is intentionally used to catch
> and prevent any unintended execution of code that should only run when
> ITS is available;
>  - function 'prepare_acpi()' when the config CONFIG_ACPI is not 
> defined,
> to trigger an error if ACPI-related features are used incorrectly.
> 
> To account for that in specific builds, update the ECLAIR configuration
> to deviate these violations. Update deviations.rst file accordingly.
> No functional changes.
> 
> Signed-off-by: Dmytro Prokopchuk 
> ---
> Test CI pipeline:
> https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/2000738682
> ---

https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/jobs/11119212994

Build failure here

>  automation/eclair_analysis/ECLAIR/deviations.ecl | 11 +++++++++++
>  docs/misra/deviations.rst                        | 13 +++++++++++++
>  2 files changed, 24 insertions(+)
> 
> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl 
> b/automation/eclair_analysis/ECLAIR/deviations.ecl
> index 7f3fd35a33..336aec58c2 100644
> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -41,6 +41,17 @@ not executable, and therefore it is safe for them to 
> be unreachable."
>  
> -call_properties+={"name(__builtin_unreachable)&&stmt(begin(any_exp(macro(name(ASSERT_UNREACHABLE)))))", 
> {"noreturn(false)"}}
>  -doc_end
> 
> +-doc_begin="The 'BUG()' macro is intentionally used in the 
> 'prepare_acpi()' function in specific build configuration
> +(when the config CONFIG_ACPI is not defined) to trigger an error if 
> ACPI-related features are used incorrectly."
> +-config=MC3A2.R2.1,reports+={deliberate, 
> "any_area(any_loc(file(^xen/arch/arm/include/asm/domain_build\\.h$))&&context(name(prepare_acpi)))"}
> +-doc_end
> +
> +-doc_begin="The 'BUG()' macro is intentionally used in 
> 'gicv3_do_LPI'() and 'gicv3_its_setup_collection()' functions
> +in specific build configuration (when the config CONFIG_HAS_ITS is not 
> defined) to catch and prevent any unintended
> +execution of code that should only run when ITS is available."
> +-config=MC3A2.R2.1,reports+={deliberate, 
> "any_area(any_loc(file(^xen/arch/arm/include/asm/gic_v3_its\\.h$))&&context(name(gicv3_do_LPI||gicv3_its_setup_collection)))"}
> +-doc_end
> +
>  -doc_begin="Proving compliance with respect to Rule 2.2 is generally 
> impossible:
>  see https://arxiv.org/abs/2212.13933 for details. Moreover, peer 
> review gives us
>  confidence that no evidence of errors in the program's logic has been 
> missed due
> diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
> index 2119066531..96eb202502 100644
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -97,6 +97,19 @@ Deviations related to MISRA C:2012 Rules:
>         Xen expects developers to ensure code remains safe and reliable 
> in builds,
>         even when debug-only assertions like `ASSERT_UNREACHABLE() are 
> removed.
> 
> +   * - R2.1
> +     - The 'BUG()' macro is intentionally used in the 'prepare_acpi()' 
> function
> +       in specific build configuration (when the config CONFIG_ACPI is 
> not
> +       defined) to trigger an error if ACPI-related features are used 
> incorrectly.
> +     - Tagged as `deliberate` for ECLAIR.
> +
> +   * - R2.1
> +     - The 'BUG()' macro is intentionally used in 'gicv3_do_LPI'() and
> +       'gicv3_its_setup_collection()' functions in specific build 
> configuration
> +       (when the config CONFIG_HAS_ITS is not defined) to catch and 
> prevent any
> +       unintended execution of code that should only run when ITS is 
> available.
> +     - Tagged as `deliberate` for ECLAIR.
> +
>     * - R2.2
>       - Proving compliance with respect to Rule 2.2 is generally 
> impossible:
>         see ``_ for details. 
> Moreover, peer

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Sun, 24 Aug 2025 20:21:08 +0300
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Subject: Re: [PATCH v2 00/10] Introduce eSPI support
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: 
Content-Language: en-US
From: Oleksandr Tyshchenko 
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On 07.08.25 15:33, Leonid Komarianskyi wrote:
> Hello everyone!

Hello Leonid,

> 
> ### Background
> Unlike the Linux kernel, which has supported extended shared peripheral
> interrupts (eSPIs) since 2019 [1], Xen currently lacks support for this
> interrupt range. For SoCs with GICv3.1+, this feature may be essential
> because critical devices, such as consoles required for booting Xen
> itself, may rely on eSPIs. Additionally, these platforms require eSPI
> support for fully functional domains, as any device using eSPIs cannot
> currently be used with Xen setups. Without eSPI support, Xen cannot run
> properly on these platforms, significantly limiting its usability on
> modern ARM hardware.
> 
> This patch series adds support for the extended shared peripheral
> interrupt (eSPI) range (INTIDs 4096-5119 [2](ranges of INTIDs)) for Xen
> and guest domains. The implementation uses a generic approach to handle
> eSPIs, similar to regular SPIs, while maintaining compatibility with the
> existing SPI range. Functionality remains unchanged for setups that do
> not require eSPIs.


I have lightly re-checked the simple Arm64 Xen environment (dom0less 
DomU under QEMU) with your series applied. To be clear, I did not really 
test the eSPI support (the underlying GICv3 HW does support it); I just 
wanted to ensure that your series would not break anything. So, in both 
cases (CONFIG_GICV3_ESPI=y and CONFIG_GICV3_ESPI=n), I did not notice 
any issues (at least obvious) related to GICv3 emulation and SPI 
injection for the passed-through device.

Also, I think you want to describe the eSPI feature in the CHANGELOG.md.


[snip]


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MISRA C Rule 11.3 states: "A cast shall not be performed between a pointer
to object type and a pointer to a different object type."

Violations of this rule arise due to the 'container_of()' macro, which cast=
s
a member of a structure to its containing structure:
    container_of(ptr, type, member) ({                             \
           typeof_field(type, member) *__mptr =3D (ptr);             \
           (type *)( (char *)__mptr - offsetof(type,member) );})

The 'container_of()' macro is safe because it relies on the standardized an=
d
well-defined 'offsetof()' macro to calculate the memory address of the
containing structure, while assuming proper alignment and ensuring no
undefined behavior, provided that the input pointer is valid and points to
the specified member.

Configure Eclair to suppress violation reports related to 'container_of()'
macro. Update 'deviations.rst' file accordingly.
No functional changes.

Signed-off-by: Dmytro Prokopchuk 
---
Changes in v2:
- removed '-enable=3DMC3A2.R11.3' from the monitored.ecl file
- fixed typo: "Convesions" -> "Conversions"
- added parentheses for macros container_of() and offsetof()

Link to v1:
https://patchew.org/Xen/d6a8682c98880d66ea99f882520b3defda0e3fe0.1755672275=
.git.dmytro._5Fprokopchuk1@epam.com/
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 8 ++++++++
 docs/misra/deviations.rst                        | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index 7f3fd35a33..42b84429f0 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -403,6 +403,14 @@ because the semantics of the 'noreturn' attribute do n=
ot alter the calling conve
 }
 -doc_end
=20
+-doc_begin=3D"Conversions in the 'container_of()' macro are safe because i=
t relies on
+the standardized and well-defined 'offsetof()' macro to calculate the memo=
ry address
+of the containing structure, while assuming proper alignment and ensuring =
no
+undefined behavior, provided that the input pointer is valid and points to=
 the
+specified member."
+-config=3DMC3A2.R11.3,reports+=3D{safe,"any_area(any_loc(any_exp(macro(^co=
ntainer_of$))))"}
+-doc_end
+
 -doc_begin=3D"Conversions from and to integral types are safe, in the assu=
mption that the target type has enough bits to store the value.
 See also Section \"4.7 Arrays and Pointers\" of \"GCC_MANUAL\""
 -config=3DMC3A2.R11.6,casts+=3D{safe,
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..db9e09c3cb 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -393,6 +393,14 @@ Deviations related to MISRA C:2012 Rules:
        (i.e., less strict) alignment requirement are safe.
      - Tagged as `safe` for ECLAIR.
=20
+   * - R11.3
+     - Conversions in the 'container_of()' macro are safe because it relie=
s on
+       the standardized and well-defined 'offsetof()' macro to calculate t=
he
+       memory address of the containing structure, while assuming proper
+       alignment and ensuring no undefined behavior, provided that the inp=
ut
+       pointer is valid and points to the specified member.
+     - Tagged as `safe` for ECLAIR.
+
    * - R11.6
      - Conversions from and to integral types are safe, in the assumption =
that
        the target type has enough bits to store the value.
--=20
2.43.0


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini , Nicola
 Vetrini 
Subject: [PATCH v3] docs/misra: fix sphinx-build issues
Thread-Topic: [PATCH v3] docs/misra: fix sphinx-build issues
Thread-Index: AQHcFR/6qKs/+WblEk+6G3rdASWMgg==
Date: Sun, 24 Aug 2025 17:53:20 +0000
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From: Dmytro Prokopchuk1 

Fix the following issues:
1. xen/docs/misra/deviations.rst:90: WARNING: Inline interpreted text or
phrase reference start-string without end-string. [docutils]
2. xen/docs/misra/deviations.rst:54: ERROR: Error parsing content block
for the "list-table" directive: uniform two-level bullet list expected,
but row 6 does not contain the same number of items as row 1 (2 vs 3).
* - R2.1
  - Calls to the `__builtin_unreachable()` function inside the expansion of
    the `ASSERT_UNREACHABLE()` macro may cause a function to be marked as
    non-returning. This behavior occurs only in configurations where
    assertions are enabled. To address this, the `noreturn` property for
    `__builtin_unreachable()` is overridden in these contexts, resulting in
    the absence of reports that do not have an impact on safety, despite
    being true positives.
    Xen expects developers to ensure code remains safe and reliable in buil=
ds,
    even when debug-only assertions like `ASSERT_UNREACHABLE() are removed.
3. xen/docs/misra/rules.rst:127: WARNING: Inline interpreted text or phrase
reference start-string without end-string. [docutils]

Signed-off-by: Dmytro Prokopchuk 
Reviewed-by: Nicola Vetrini 
Reviewed-by: Andrew Cooper 
---
Changes in v3:
- removed item #4 from commit message
- set backticks for macro ASSERT_UNREACHABLE() in deviations.rst and rules.=
rst

Link to v2:
https://patchew.org/Xen/f31b8d62f16bd272114276f53db842101cd53e52.1755266805=
.git.dmytro._5Fprokopchuk1@epam.com/
---
 docs/misra/deviations.rst | 3 ++-
 docs/misra/rules.rst      | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..3271317206 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -95,7 +95,8 @@ Deviations related to MISRA C:2012 Rules:
        the absence of reports that do not have an impact on safety, despit=
e
        being true positives.
        Xen expects developers to ensure code remains safe and reliable in =
builds,
-       even when debug-only assertions like `ASSERT_UNREACHABLE() are remo=
ved.
+       even when debug-only assertions like `ASSERT_UNREACHABLE()` are rem=
oved.
+     - ECLAIR has been configured to ignore those statements.
=20
    * - R2.2
      - Proving compliance with respect to Rule 2.2 is generally impossible=
:
diff --git a/docs/misra/rules.rst b/docs/misra/rules.rst
index a2e4e9f4ff..4388010ec9 100644
--- a/docs/misra/rules.rst
+++ b/docs/misra/rules.rst
@@ -124,7 +124,7 @@ maintainers if you want to suggest a change.
            they are used to generate definitions for asm modules
          - Declarations without initializer are safe, as they are not
            executed
-         - Functions that are no-return due to calls to the `ASSERT_UNREAC=
HABLE()'
+         - Functions that are no-return due to calls to the `ASSERT_UNREAC=
HABLE()`
            macro in debug build configurations are not considered violatio=
ns::
=20
               static inline bool
--=20
2.43.0


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To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Topic: [PATCH v2 03/10] xen/arm: vgic: implement helper functions for
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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH v2 05/10] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Topic: [PATCH v2 05/10] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
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Date: Sun, 24 Aug 2025 18:17:39 +0000
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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v2 08/10] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Topic: [PATCH v2 08/10] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcB5d8BuZ0dq8rx0Owht+h5hVtIrRwaE6AgAHSZwA=
Date: Sun, 24 Aug 2025 18:28:55 +0000
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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
 to support eSPIs
Thread-Topic: [PATCH v2 09/10] xen/arm: domain_build: adjust Dom0 IRQ handling
 to support eSPIs
Thread-Index: AQHcB5d9D2bB2ytT+0KvuTkMlpIiH7RwTReAgAHy1IA=
Date: Sun, 24 Aug 2025 18:47:33 +0000
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Message-ID: <66e689fd-53b1-4f8a-bd1c-2c91738f8d74@gmail.com>
Date: Sun, 24 Aug 2025 18:36:33 -0400
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Subject: Re: [RFC PATCH 9/9] tools: Introduce abi-tool
To: Teddy Astie , xen-devel@lists.xenproject.org
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini 
References: 
 <20b01deb2f53351103fce2e36a586a6a996a841b.1755785258.git.teddy.astie@vates.tech>
Content-Language: en-US
From: Demi Marie Obenour 
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In-Reply-To: <20b01deb2f53351103fce2e36a586a6a996a841b.1755785258.git.teddy.astie@vates.tech>
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 protected-headers="v1"
From: Demi Marie Obenour 
To: Teddy Astie , xen-devel@lists.xenproject.org
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Jan Beulich ,
 Julien Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini 
Message-ID: <66e689fd-53b1-4f8a-bd1c-2c91738f8d74@gmail.com>
Subject: Re: [RFC PATCH 9/9] tools: Introduce abi-tool
References: 
 <20b01deb2f53351103fce2e36a586a6a996a841b.1755785258.git.teddy.astie@vates.tech>
In-Reply-To: <20b01deb2f53351103fce2e36a586a6a996a841b.1755785258.git.teddy.astie@vates.tech>

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On 8/21/25 11:25, Teddy Astie wrote:
> abi-tool is a small Rust tool that is able to parse ABI yaml
> files and generate C stubs for performing hypercalls.
>=20
> Signed-off-by: Teddy Astie 
Would it make sense to generate the hypervisor side of the
interface in this way as well?
--=20
Sincerely,
Demi Marie Obenour (she/her/hers)
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Date: Sun, 24 Aug 2025 18:39:05 -0400
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Subject: Re: [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural
 constant_tsc model checks
To: Xiaoyao Li , Sohil Mehta ,
 David Woodhouse , x86@kernel.org,
 Dave Hansen , Tony Luck ,
 =?UTF-8?Q?J=C3=BCrgen_Gross?= ,
 Boris Ostrovsky ,
 xen-devel 
Cc: Peter Zijlstra , Ingo Molnar ,
 Arnaldo Carvalho de Melo ,
 Namhyung Kim , Mark Rutland ,
 Alexander Shishkin ,
 Jiri Olsa , Ian Rogers ,
 Adrian Hunter ,
 Kan Liang , Thomas Gleixner ,
 Borislav Petkov , "H . Peter Anvin" ,
 "Rafael J . Wysocki" , Len Brown ,
 Andy Lutomirski , Viresh Kumar ,
 Jean Delvare , Guenter Roeck ,
 Zhang Rui , Andrew Cooper ,
 David Laight ,
 Dapeng Mi , linux-perf-users@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
 linux-pm@vger.kernel.org, kvm@vger.kernel.org, Xin Li 
References: <20250219184133.816753-1-sohil.mehta@intel.com>
 <20250219184133.816753-14-sohil.mehta@intel.com>
 <6f05a6849fb7b22db35216dcf12bf537f8a43a92.camel@infradead.org>
 <968a179f-3da7-4c69-b798-357ea8d759eb@intel.com>
 <5f5f1230-f373-469c-b0d9-abc80199886e@intel.com>
 <03ac8bac-c8d1-4a3b-a07f-2bbf04e726b6@intel.com>
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In-Reply-To: <03ac8bac-c8d1-4a3b-a07f-2bbf04e726b6@intel.com>
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From: Demi Marie Obenour 
To: Xiaoyao Li , Sohil Mehta ,
 David Woodhouse , x86@kernel.org,
 Dave Hansen , Tony Luck ,
 =?UTF-8?Q?J=C3=BCrgen_Gross?= ,
 Boris Ostrovsky ,
 xen-devel 
Cc: Peter Zijlstra , Ingo Molnar ,
 Arnaldo Carvalho de Melo ,
 Namhyung Kim , Mark Rutland ,
 Alexander Shishkin ,
 Jiri Olsa , Ian Rogers ,
 Adrian Hunter ,
 Kan Liang , Thomas Gleixner ,
 Borislav Petkov , "H . Peter Anvin" ,
 "Rafael J . Wysocki" , Len Brown ,
 Andy Lutomirski , Viresh Kumar ,
 Jean Delvare , Guenter Roeck ,
 Zhang Rui , Andrew Cooper ,
 David Laight ,
 Dapeng Mi , linux-perf-users@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
 linux-pm@vger.kernel.org, kvm@vger.kernel.org, Xin Li 
Message-ID: 
Subject: Re: [PATCH v3 13/15] x86/cpu/intel: Bound the non-architectural
 constant_tsc model checks
References: <20250219184133.816753-1-sohil.mehta@intel.com>
 <20250219184133.816753-14-sohil.mehta@intel.com>
 <6f05a6849fb7b22db35216dcf12bf537f8a43a92.camel@infradead.org>
 <968a179f-3da7-4c69-b798-357ea8d759eb@intel.com>
 <5f5f1230-f373-469c-b0d9-abc80199886e@intel.com>
 <03ac8bac-c8d1-4a3b-a07f-2bbf04e726b6@intel.com>
In-Reply-To: <03ac8bac-c8d1-4a3b-a07f-2bbf04e726b6@intel.com>
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On 8/21/25 21:46, Xiaoyao Li wrote:
> On 8/22/2025 3:43 AM, Sohil Mehta wrote:
>> On 8/21/2025 12:34 PM, Sohil Mehta wrote:
>>> On 8/21/2025 6:15 AM, David Woodhouse wrote:
>>>
>>>> Hm. My test host is INTEL_HASWELL_X (0x63f). For reasons which are
>>>> unclear to me, QEMU doesn't set bit 8 of 0x80000007 EDX unless I
>>>> explicitly append ',+invtsc' to the existing '-cpu host' on its comm=
and
>>>> line. So now my guest doesn't think it has X86_FEATURE_CONSTANT_TSC.=

>>>>
>>>
>>> Haswell should have X86_FEATURE_CONSTANT_TSC, so I would have expecte=
d
>>> the guest bit to be set. Until now, X86_FEATURE_CONSTANT_TSC was set
>>> based on the Family-model instead of the CPUID enumeration which may
>>> have hid the issue.
>>>
>>
>> Correction:
>> s/instead/as well as
>>
>>>  From my initial look at the QEMU implementation, this seems intentio=
nal.
>>>
>>> QEMU considers Invariant TSC as un-migratable which prevents it from
>>> being exposed to migratable guests (default).
>>> target/i386/cpu.c:
>>> [FEAT_8000_0007_EDX]
>>>           .unmigratable_flags =3D CPUID_APM_INVTSC,
>>>
>>> Can you please try '-cpu host,migratable=3Doff'?
>>
>> This is mainly to verify. If confirmed, I am not sure what the long te=
rm
>> solution should be.
>=20
> yeah. It's the intentional behavior of QEMU.
>=20
> Invariant TSC is ummigratable unless users explicitly configures the TS=
C=20
> frequency, e.g., "-cpu host,tsc-frequency=3Dxxx". Because the TSC=20
> frequency is by default the host's frequency if no "tsc-frequency"=20
> specified, and it will change when the VM is migrated to a host with a =

> different TSC frequency.
>=20
> It's the specific behavior/rule of QEMU. We just need to keep it in=20
> mind. If we want to expose invariant TSC to the guest with QEMU's "-cpu=
=20
> host", we can either:
> 1) explicitly configure the "tsc-frequency", or
> 2) explicitly turn off "migratable"

Could the TSC frequency be included in the migration stream?
--=20
Sincerely,
Demi Marie Obenour (she/her/hers)
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Subject: Re: Consider changing CONFIG_ACPI default on ARM?
To: Elliott Mitchell , Julien Grall 
Cc: Jan Beulich , xen-users@lists.xenproject.org,
 xen-devel@lists.xenproject.org, Stefano Stabellini ,
 Bertrand Marquis ,
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From: Demi Marie Obenour 
To: Elliott Mitchell , Julien Grall 
Cc: Jan Beulich , xen-users@lists.xenproject.org,
 xen-devel@lists.xenproject.org, Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Paul Leiber 
Message-ID: <15024e7a-f5e2-43df-8de8-e4da200e7ee6@gmail.com>
Subject: Re: Consider changing CONFIG_ACPI default on ARM?
References: 
 
 
 <1b96f2f3-55a2-4b33-84b1-a7c18d38d10c@suse.com>
 <6e9b5265-7a3b-4fd5-b14e-0e60a8b49833@gmail.com>
 
 
 <2f11b8ea-a386-4c2a-afe6-c7e57d1d7f75@xen.org>
 
In-Reply-To: 

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On 8/23/25 22:06, Elliott Mitchell wrote:
> On Sat, Aug 23, 2025 at 08:59:13AM +0100, Julien Grall wrote:
>>
>> On 22/08/2025 21:09, Elliott Mitchell wrote:
>>> Since you're not pointing to anything definite, could it be everythin=
g
>>> has been resolved?
>>
>> Unfortunately, the situation has not changed since your last thread ab=
out
>> enabling CONFIG_ACPI=3Dy a couple of years ago. The main feature we ar=
e
>> lacking is the parsing the IORT (used to discover SMMUs and MSI
>> controllers). Without this...
>=20
> No one to sponsor this work?  Disappointing with how far ACPI support h=
ad
> gotten.  Surprising the funding ended here.
>=20
>>>  We've got at least two people for whom ACPI on ARM
>>> works pretty well.
>>
>> ... Xen will only properly boot on "simple" case like the Raspberry PI=
=2E
>> Also, IIRC Xen would use ACPI rather than Device-Tree by default.
>=20
> What is the "improper" booting on non-simple cases like?  panic()?
> Domain 0 boots, but the system isn't properly protected by the SMMU?
> Ideally it would be runtime configurable with the former being the
> default, but the panic message indicating how to override to produce th=
e
> latter.  Perhaps even accompanied by an invitation for sponsorship.
>=20
> Yet handling those simple cases would help many people.  For a long tim=
e
> IO-MMUs were rare, yet the world did not end.
>=20
>>> There may be many more using it.  Perhaps this
>>> should even be done on the 4.20 branch given how long this has been
>>> working?
>>
>> I am guessing you mean 4.21 which will be released in a couple of mont=
hs
>> time, correct?
>=20
> As it is very simple to flip the default, I was thinking it might be
> worthwhile to change it on earlier versions too.  After all it has
> actually been known to work for kind of a long time.
>=20
>> We have been discussing among the committers on whether we are ok to e=
nable
>> ACPI despite the fact it is still not feature complete (see above). Th=
e
>> discussion is not fully finalized but if we were to enable CONFIG_ACPI=
=3Dy by
>> default then I think we would need the following:
>>
>>  * Select device-tree by default rather than ACPI
>>  * Go through SUPPORT.MD and check what features we marked as SUPPORTE=
D.md
>> but doesn't work on ACPI.
>>
>> Maybe you can help with that?
>=20
> I'm not sure this is a good role for me.  I suppose I could do a first
> pass marking everything as non-ACPI.  Problem is most recently I've bee=
n
> focussing on another aspect and I would mostly be guessing about things=
=2E
>=20
>> Out of interest, sorry if this was already mentioned before, is there =
any
>> reason ACPI is used on the Raspberry PI over Device-Tree? Is there any=
 issue
>> with the latter on Xen?
>=20
> Issue is various Linux distributions have differing levels of support f=
or
> various targets.  Nearly everyone has some degree of support for
> Raspberry PI (even Tianocore!), but the quality does vary from
> distribution to distribution.
>=20
> My favored distribution is rather limited in what it does for !x86.
> Everything gets built for !x86, but things such as booting hasn't been
> heavily looked at.  There is agreement using U-Boot/UEFI =3D> GRUB woul=
d
> likely be a Good Thing, but there is a shortage of people with the righ=
t
> expertise to get that working.  As a result booting Xen is troublesome.=

>=20
> Whereas copying the Tianocore firmware into place and getting it bootin=
g
> is *extremely* simple.  Further this has very few restrictions (GPT and=

> a ~200MB FAT filesystem).  Better yet once in place this is extremely
> robust.
>=20
> The only argument in favor of device-trees I've seen is that they're ea=
sy
> to deal with.  Certainly they need little runtime processing.  Yet they=

> come with a major weakness that they're really part of the kernel.  Whe=
n
> the Linux kernel is replaced (even patch-level differences) you pretty
> well always need to replace the device-trees.  Once you've done that it=

> is quite difficult to go back to the earlier kernel.
>=20
> New device-trees often cause older kernels to panic or malfunction.  If=

> storage is on USB you can unplug and adjust on a nearby desktop, but th=
is
> means you need to keep another system handy.  Whereas due to being well=

> isolated from the OS, the same set of ACPI tables works for many OSes a=
nd
> nearly all versions of Linux.
>=20
> The instances of ACPI tables which worked with Windows, but failed for
> other operating systems are quite famous.  The instances where a given
> set of device-trees work with Linux, but then fail with other OSes
> (or even merely different version of Linux) are not notable.  In fact
> instances where device-trees *don't* change drastically between kernel
> minor versions are newsworthy.

I think one proper answer is to bundle the device trees with the kernel,
and to make sure Xen uses the same code to handle it as Linux does.
Both are GPLv2 so it is fine to move code back and forth between them.
--=20
Sincerely,
Demi Marie Obenour (she/her/hers)
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From: Xin Li 
Subject: Re: [PATCH 5/6] x86/paravirt: Switch MSR access pv_ops functions to
 instruction interfaces
To: Juergen Gross , linux-kernel@vger.kernel.org,
        x86@kernel.org, virtualization@lists.linux.dev
Cc: Ajay Kaher ,
        Broadcom internal kernel review list
 ,
        Thomas Gleixner
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On 6/11/2025 5:58 AM, Juergen Gross wrote:
> I'm just doing a V2 of my series, but this time including the additional
> support of the non-serializing and immediate forms. Lets see how this will
> look like. I will drop using the EAX_EDX_* macros, but due to the reason
> mentioned above I won't switch to your variant completely.

Hi Juergen,

Do you have any update on this?

Thanks!
     Xin



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Date: Mon, 25 Aug 2025 09:46:10 +0200
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Subject: Re: [PATCH v5 4/4] CHANGELOG.md: add new SMBIOS tables (7, 8, 9, 26,
 27, 28)
To: =?UTF-8?Q?Petr_Bene=C5=A1?= ,
 xen-devel@lists.xenproject.org
Cc: Community Manager 
References: 
 <3c9c7c48c9d8633b4c36bb0bb91fab88c03ae279.1755987697.git.w1benny@gmail.com>
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From: Oleksii Kurochko 
In-Reply-To: <3c9c7c48c9d8633b4c36bb0bb91fab88c03ae279.1755987697.git.w1benny@gmail.com>

This is a multi-part message in MIME format.
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On 8/24/25 12:26 AM, Petr Beneš wrote:
> From: Petr Beneš
>
> Signed-off-by: Petr Beneš

Acked-by: Oleksii Kurochko

Thanks.

~ Oleksii

> ---
>   CHANGELOG.md | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/CHANGELOG.md b/CHANGELOG.md
> index 271ac73a0a..2fd65b90a9 100644
> --- a/CHANGELOG.md
> +++ b/CHANGELOG.md
> @@ -32,6 +32,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
>        capability usage is not yet supported on PVH dom0).
>      - Smoke tests for the FreeBSD Xen builds in Cirrus CI.
>      - PVH xenstore-stubdom now supports Live Update.
> +   - Support for new SMBIOS tables: 7, 8, 9, 26, 27, 28.
>   
>    - On Arm:
>       - Ability to enable stack protector
--------------UB3wZH0rfXp3zSfM0QrrAFCK
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    On 8/24/25 12:26 AM, Petr Beneš wrote:
    
    
    
    
    
      
    From: Petr Beneš <w1benny@gmail.com>

Signed-off-by: Petr Beneš <w1benny@gmail.com>
    
    
    
    
    Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Thanks.

~ Oleksii

    
    
    
      
    ---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 271ac73a0a..2fd65b90a9 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -32,6 +32,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
      capability usage is not yet supported on PVH dom0).
    - Smoke tests for the FreeBSD Xen builds in Cirrus CI.
    - PVH xenstore-stubdom now supports Live Update.
+   - Support for new SMBIOS tables: 7, 8, 9, 26, 27, 28.
 
  - On Arm:
     - Ability to enable stack protector

    
    
    
  


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Subject: Re: Consider changing CONFIG_ACPI default on ARM?
To: Elliott Mitchell 
Cc: Demi Marie Obenour ,
 xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Paul Leiber 
References: 
 
 
 <1b96f2f3-55a2-4b33-84b1-a7c18d38d10c@suse.com>
 <6e9b5265-7a3b-4fd5-b14e-0e60a8b49833@gmail.com>
 
 
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On 22.08.2025 22:09, Elliott Mitchell wrote:
> On Fri, Aug 15, 2025 at 10:14:42AM +0200, Jan Beulich wrote:
>> On 14.08.2025 23:27, Demi Marie Obenour wrote:
>>> On 8/14/25 02:55, Jan Beulich wrote:
>>>> On 06.08.2025 06:30, Elliott Mitchell wrote:
>>>>> On Tue, Jul 01, 2025 at 10:01:13PM +0200, Paul Leiber wrote:
>>>>>>
>>>>>> Unfortunately, I don't have a direct answer to the question (as is so often
>>>>>> the case, due to my limited knowledge and experience). However, I am
>>>>>> successfully running Xen on a RPi 4 (mostly, except for some VLAN related
>>>>>> networking issues).
>>>>>>
>>>>>> I used instructions in [1] to install vanilla Debian on the RPi, including
>>>>>> UEFI boot and grub. I then compiled Xen with expert options and ACPI
>>>>>> enabled.
>>>>>>
>>>>>> I don't know if there are better solutions. For example, I suffer from the
>>>>>> fact that I2C doesn't work when using UEFI boot on a RPi. Nowadays, Debian
>>>>>> provides their own vanilla Debian images for RPi and with working I2C, but
>>>>>> these images are using a different boot method that I didn't know how to use
>>>>>> with Xen.  So far, the procedure described above seems to be the easiest
>>>>>> solution for me.
>>>>>
>>>>>
>>>>>> [1] https://forums.raspberrypi.com/viewtopic.php?t=282839
>>>>>>
>>>>>> Am 30.06.2025 um 12:35 schrieb Sumit Semwal:
>>>>>>>
>>>>>>> I've just begun to experiment with the Raspberry Pi 5, trying to run a
>>>>>>> simple xen + Dom0 setup, using uBoot, and the bookworm based Rpi
>>>>>>> distro.
>>>>>>>
>>>>>>> I've tried combinations of the following setup:
>>>>>>>
>>>>>>> 1. prebuilt Rpi5 kernel + dtbs, and have also tried to build them from
>>>>>>> source [1]
>>>>>>> 2. Xen from upstream [2] and xen-troops [3]
>>>>>>> 3. upstream uBoot from [4]
>>>>>>>
>>>>>>> but with the same result: [short log below; I can provide a fuller log
>>>>>>> if needed]
>>>>>>>
>>>>>>> (XEN) DT: ** translation for device /axi/msi-controller@1000130000 **
>>>>>>> (XEN) DT: bus is default (na=2, ns=2) on /axi
>>>>>>> (XEN) DT: translating address:<3> 000000ff<3> fffff000<3>
>>>>>>> (XEN) DT: parent bus is default (na=2, ns=1) on /
>>>>>>> (XEN) DT: walking ranges...
>>>>>>> (XEN) DT: default map, cp=0, s=1000000000, da=fffffff000
>>>>>>> (XEN) DT: default map, cp=1000000000, s=100000000, da=fffffff000
>>>>>>> (XEN) DT: default map, cp=1400000000, s=400000000, da=fffffff000
>>>>>>> (XEN) DT: default map, cp=1800000000, s=400000000, da=fffffff000
>>>>>>> (XEN) DT: default map, cp=1c00000000, s=400000000, da=fffffff000
>>>>>>> (XEN) DT: not found !
>>>>>>> (XEN) Unable to retrieve address 1 for /axi/msi-controller@1000130000
>>>>>>> (XEN) Device tree generation failed (-22).
>>>>>>> (XEN) debugtrace_dump() global buffer starting
>>>>>>> 1 cpupool_create(pool=0,sched=6)
>>>>>>> 2 Created cpupool 0 with scheduler SMP Credit Scheduler rev2 (credit2)
>>>>>>> 3 cpupool_add_domain(dom=0,pool=0) n_dom 1 rc 0
>>>>>>> (XEN) wrap: 0
>>>>>>> (XEN) debugtrace_dump() global buffer finished
>>>>>>> (XEN)
>>>>>>> (XEN) ****************************************
>>>>>>> (XEN) Panic on CPU 0:
>>>>>>> (XEN) Could not set up DOM0 guest OS (rc = -22)
>>>>>>> (XEN) ****************************************
>>>>>>>
>>>>>>>
>>>>>>> I'm certain I'm missing something, but before I delve deeper, I just
>>>>>>> wanted to ask if this is a known issue, and if so, are there any
>>>>>>> workarounds or solutions available for this?
>>>>>>>
>>>>>>> Any help about this is highly appreciated!
>>>>>>>
>>>>>>> Thanks and Best regards,
>>>>>>> Sumit.
>>>>>>>
>>>>>>> [1]:  https://github.com/raspberrypi/linux rpi-6.12.y branch
>>>>>>> [2]: git://xenbits.xen.org/xen.git - main branch
>>>>>>> [3] xen-troops https://github.com/xen-troops/xen - rpi5_dev branch
>>>>>>> [4]: https://github.com/u-boot/u-boot.git master branch
>>>>>
>>>>> Ultimately Debian is choosing to leave most defaults alone.  So far the
>>>>> Xen developers have left CONFIG_ACPI defaulting to off on ARM*.  The
>>>>> Debian project doesn't have paid people to support Raspberry PI hardware,
>>>>> despite being rather common.  As a result there aren't any official
>>>>> Raspberry PI images, but people associated with Tianocore have gotten
>>>>> generic images to boot on Raspberry PI hardware.
>>>>>
>>>>> I'm unsure of the likelihood of getting the Debian maintainers to
>>>>> override the default.  Yet due being by far the simplest way to install
>>>>> Debian and Xen on a very common ARM64 platform, perhaps the Xen
>>>>> developers should consider changing?
>>>>
>>>> In an open source project everyone is a developer. There is a
>>>> significant amount of work someone needs to pick up to change this
>>>> SUPPORT.md entry:
>>>>
>>>> ### Host ACPI (via Domain 0)
>>>>
>>>>     Status, x86 PV: Supported
>>>>     Status, ARM: Experimental
>>>>
>>>> Parties interested in changing the support status of any component are the
>>>> primary candidates to actually carry out the necessary work.
>>>
>>> What is that work?
>>
>> To determine what exactly needs doing is part of the exercise. I, for one, am
>> unaware of a concrete written down set of things which need doing.
> 
> Since you're not pointing to anything definite, could it be everything
> has been resolved?

Possible. Yet even then the state of things needs fully writing down, perhaps
in a commit message for the patch changing the support status. That's likely
still a time consuming job.

Jan


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Date: Mon, 25 Aug 2025 10:39:01 +0200
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Subject: Re: [PATCH] misra: consider conversion from UL or (void*) to function
 pointer as safe
To: Dmytro Prokopchuk1 
Cc: Doug Goldstein ,
 Stefano Stabellini ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "xen-devel@lists.xenproject.org" ,
 Nicola Vetrini 
References: <9e5e4ff2c7ba0a90a6ac403e2de9318e18949274.1755628705.git.dmytro_prokopchuk1@epam.com>
 <90fb95a3-4b32-4785-a77c-373e5b9da6ed@suse.com>
 
 <6b912698-b871-4819-ac30-14325d0be146@epam.com>
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On 22.08.2025 18:34, Dmytro Prokopchuk1 wrote:
> On 8/21/25 11:25, Nicola Vetrini wrote:
>> On 2025-08-21 10:01, Jan Beulich wrote:
>>> On 19.08.2025 20:55, Dmytro Prokopchuk1 wrote:
>>>> Rule 11.1 states as following: "Conversions shall not be performed
>>>> between a pointer to a function and any other type."
>>>>
>>>> The conversion from unsigned long or (void *) to a function pointer
>>>> is safe in Xen because the architectures it supports (e.g., x86 and
>>>> ARM) guarantee compatible representations between these types.
>>>
>>> I think we need to be as precise as possible here. The architectures
>>> guarantee nothing, they only offer necessary fundamentals. In the
>>> Windows x86 ABI, for example, you can't convert pointers to/from longs
>>> without losing data. What we build upon is what respective ABIs say,
>>> possibly in combination of implementation specifics left to compilers.
>>>
>>
>> +1, a mention of the compilers and targets this deviation relies upon is 
>> needed.
> 
> Maybe with this wording:
> 
> This deviation is based on the guarantees provided by the specific ABIs
> (e.g., ARM AAPCS) and compilers (e.g., GCC) supported in Xen. These ABIs
> guarantee compatible representations for 'void *', 'unsigned long' and
> function pointers for the supported target platforms. This behavior is
> architecture-specific and may not be portable outside of supported
> environments.

Reads okay to me; for Arm64 I can only assume the psABI indeed makes this
guarantee.

>>>> --- a/docs/misra/deviations.rst
>>>> +++ b/docs/misra/deviations.rst
>>>> @@ -370,6 +370,16 @@ Deviations related to MISRA C:2012 Rules:
>>>>         to store it.
>>>>       - Tagged as `safe` for ECLAIR.
>>>>
>>>> +   * - R11.1
>>>> +     - The conversion from unsigned long or (void \*) to a function 
>>>> pointer does
>>>> +       not lose any information or violate type safety assumptions 
>>>> if unsigned
>>>> +       long or (void \*) type is guaranteed to be the same bit size 
>>>> as a
>>>> +       function pointer. This ensures that the function pointer can 
>>>> be fully
>>>> +       represented without truncation or corruption. The macro 
>>>> BUILD_BUG_ON is
>>>> +       integrated into xen/common/version.c to confirm conversion 
>>>> compatibility
>>>> +       across all target platforms.
>>>> +     - Tagged as `safe` for ECLAIR.
>>>
>>> Why the escaping of * here, when ...
>>>
>>>> --- a/docs/misra/rules.rst
>>>> +++ b/docs/misra/rules.rst
>>>> @@ -431,7 +431,13 @@ maintainers if you want to suggest a change.
>>>>       - All conversions to integer types are permitted if the 
>>>> destination
>>>>         type has enough bits to hold the entire value. Conversions to 
>>>> bool
>>>>         and void* are permitted. Conversions from 'void noreturn (*) 
>>>> (...)'
>>>> -       to 'void (*)(...)' are permitted.
>>>> +       to 'void (*)(...)' are permitted. Conversions from unsigned 
>>>> long or
>>>> +       (void \*) to a function pointer are permitted if the source 
>>>> type has
>>>> +       enough bits to restore function pointer without truncation or 
>>>> corruption.
>>>> +       Example::
>>>> +
>>>> +           unsigned long func_addr = (unsigned long)&some_function;
>>>> +           void (*restored_func)(void) = (void (*)(void))func_addr;
>>>
>>> ... context here suggests they work fine un-escaped, and you even add 
>>> some un-
>>> escaped instances as well. Perhaps I'm simply unaware of some 
>>> peculiarity?
>>>
>>
>> This is a literal rst block, while the other is not (* acts as a bullet 
>> point in rst iirc)
> 
> This is how "sphinx-build" tool interprets this.
> 1. * inside single quotes '' -> looks normal, e.g. ‘void (*)(…)’
> 2. * without quotes -> warning
> deviations.rst:369: WARNING: Inline emphasis start-string without 
> end-string. [docutils]
> 3. \* -> looks normal, e.g. (void *)
> 
> Because that we need such format: \*

Yet under "Example::" there's no quotation and no escaping. The one
"(void \*)" earlier in the text I'd suggest to replace by a quoted
form anyway, matching the rest of the text.

Jan


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Nicola Vetrini
	, Doug Goldstein , Stefano
 Stabellini , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: [PATCH] misra: add deviation of Rule 17.7
Thread-Topic: [PATCH] misra: add deviation of Rule 17.7
Thread-Index: AQHcFZ9zsboRH18vd0iLUvum4pfwBQ==
Date: Mon, 25 Aug 2025 09:05:48 +0000
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MISRA C Rule 17.7 states: "The value returned by a function having
non-void return type shall be used."

Deviate functions like 'memcpy()', 'memset()', 'memmove()', 'snprintf()',
'strlcpy()', 'strlcat()', as they return a value purely for convenience,
their primary functionality (e.g., memory or string operations) remains
unaffected, and their return values are generally non-critical and seldom
relied upon. Update 'deviations.rst' file accordingly.

No functional changes.

Signed-off-by: Dmytro Prokopchuk 
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 6 ++++++
 docs/misra/deviations.rst                        | 8 ++++++++
 2 files changed, 14 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index 7f3fd35a33..23f62ef646 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -575,6 +575,12 @@ safe."
 -config=3DMC3A2.R17.7,calls+=3D{safe, "any()", "decl(name(__builtin_memcpy=
||__builtin_memmove||__builtin_memset||cpumask_check))"}
 -doc_end
=20
+-doc_begin=3D"It is safe to deviate functions like 'memcpy()', 'memset()',=
 'memmove()', 'snprintf()', 'strlcpy()', 'strlcat()',
+as they return a value purely for convenience, their primary functionality=
 (e.g., memory manipulation or string operations)
+remains unaffected, and their return values are generally non-critical and=
 seldom relied upon."
+-config=3DMC3A2.R17.7,calls+=3D{safe, "any()", "decl(name(memcpy||memset||=
memmove||snprintf||strlcpy||strlcat))"}
+-doc_end
+
 #
 # Series 18.
 #
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..ec98366aa5 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -576,6 +576,14 @@ Deviations related to MISRA C:2012 Rules:
          - __builtin_memset()
          - cpumask_check()
=20
+   * - R17.7
+     - It is safe to deviate functions like 'memcpy()', 'memset()', 'memmo=
ve()',
+       'snprintf()', 'strlcpy()', 'strlcat()', as they return a value pure=
ly for
+       convenience, their primary functionality (e.g., memory manipulation=
 or
+       string operations) remains unaffected, and their return values are
+       generally non-critical and seldom relied upon.
+     - Tagged as `safe` for ECLAIR.
+
    * - R18.2
      - Subtractions between pointers where at least one of the operand is =
a
        pointer to a symbol defined by the linker are safe.
--=20
2.43.0


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Date: Mon, 25 Aug 2025 11:08:32 +0200
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Subject: Re: [PATCH 15/22] x86/traps: Introduce opt_fred
To: Andrew Cooper 
Cc: Xen-devel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: <20250808202314.1045968-1-andrew.cooper3@citrix.com>
 <20250808202314.1045968-16-andrew.cooper3@citrix.com>
 <0a6b6fce-2cc8-4933-8703-399e4a4fdad6@suse.com>
 <8adbd032-9da2-481d-8d98-30c9a605ec46@citrix.com>
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From: Jan Beulich 
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In-Reply-To: <56532672-d28e-4c3c-9b4b-e038c9a5e341@citrix.com>
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On 21.08.2025 23:52, Andrew Cooper wrote:
> On 15/08/2025 9:37 am, Jan Beulich wrote:
>> On 14.08.2025 21:16, Andrew Cooper wrote:
>>> On 14/08/2025 2:30 pm, Jan Beulich wrote:
>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>> ... disabled by default.  There is a lot of work before FRED can be enabled by
>>>>> default.
>>>>>
>>>>> One part of FRED, the LKGS (Load Kernel GS) instruction, is enumerated
>>>>> separately but is mandatory as FRED disallows the SWAPGS instruction.
>>>>> Therefore, both CPUID bits must be checked.
>>>> See my (further) reply to patch 13 - I think FRED simply ought to depend on
>>>> LKGS.
>>>>
>>>>> @@ -20,6 +22,9 @@ unsigned int __ro_after_init ler_msr;
>>>>>  static bool __initdata opt_ler;
>>>>>  boolean_param("ler", opt_ler);
>>>>>  
>>>>> +int8_t __ro_after_init opt_fred = 0; /* -1 when supported. */
>>>> I'm a little puzzled by the comment? DYM "once default-enabled"?
>>> Well, I have this temporary patch
>>> https://gitlab.com/xen-project/hardware/xen-staging/-/commit/70ef6a1178a411a29b7b1745a1112e267ffb6245
>>> that will turn into a real patch when we enable FRED by default.
>>>
>>> As much as anything else, it was just a TODO.
>>>
>>>
>>>>  Then ...
>>>>
>>>>> @@ -305,6 +310,32 @@ void __init traps_init(void)
>>>>>      /* Replace early pagefault with real pagefault handler. */
>>>>>      _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF);
>>>>>  
>>>>> +    if ( !cpu_has_fred || !cpu_has_lkgs )
>>>>> +    {
>>>>> +        if ( opt_fred )
>>>> ... this won't work anymore once the initializer is changed.
>>> Hmm yes.  That wants to be an == 1 check.  Fixed.
>>>
>>>>> +            printk(XENLOG_WARNING "FRED not available, ignoring\n");
>>>>> +        opt_fred = false;
>>>> Better use 0 here?
>>>>
>>>>> +    }
>>>>> +
>>>>> +    if ( opt_fred == -1 )
>>>>> +        opt_fred = !pv_shim;
>>>> Imo it would be better to have the initializer be -1 right away, and comment
>>>> out the "!pv_shim" here, until we mean it to be default-enabled.
>>> It cannot be -1, or Xen will fail spectacularly on any FRED capable
>>> hardware.  Setting to -1 is the point at which FRED becomes security
>>> supported.
>> I guess I'm not following: If it was -1, and if the code here was
>>
>>     if ( opt_fred < 0 )
>>         opt_fred = 0 /* !pv_shim */;
>>
>> why would things "fail spectacularly" unless someone passed "fred" on
>> the command line?
> 
> Oh, that would work, but why bother?  It's simply a less readable form
> of mine, and if we're going to nitpick, it's commented out code.

Indeed, I was aware of Misra's dislike when writing the reply.

In any event - I'm okay with about any approach as long as the adjustment
to make (once FRED becomes supported) is both clear upfront and simple to
make (read: preferably a single line change). Readability is, as we know
from other recent instances, subjective. In the case here I think it
follows from my original comment that things weren't quite clear according
to my reading.

Jan


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Subject: Re: [PATCH 19/22] x86/boot: Use RSTORSSP to establish SSP
To: Andrew Cooper 
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On 22.08.2025 00:09, Andrew Cooper wrote:
> On 15/08/2025 10:03 am, Jan Beulich wrote:
>> On 14.08.2025 22:09, Andrew Cooper wrote:
>>> On 14/08/2025 4:11 pm, Jan Beulich wrote:
>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>> Under FRED, SETSSBSY is unavailable, and we want to be setting up FRED prior
>>>>> to setting up shadow stacks.  As we still need Supervisor Tokens in IDT mode,
>>>>> we need mode-specific logic to establish SSP.
>>>>>
>>>>> In FRED mode, write a Restore Token, RSTORSSP it, and discard the resulting
>>>>> Previous-SSP token.
>>>>>
>>>>> No change outside of FRED mode.
>>>>>
>>>>> Signed-off-by: Andrew Cooper 
>>>> Why is it that in patch 17 you could use identical code, but here you can't?
>>> This caught me out at first too.
>>>
>>> For S3, we're going from "no shadow stack" to "back to where we were on
>>> an active shadow stack".  All we need to do is get saved_ssp back into
>>> the SSP register.
>>>
>>> Here, we're going from "no shadow stack" to "on a good, empty, shadow
>>> stack".  For FRED we only need to load a value into SSP, but in IDT mode
>>> we must also arrange to create a busy Supervisor Token on the base of
>>> the stack.
>>>
>>> We could in principle conditionally write a busy supervisor token, then
>>> unconditionally RSTORSSP, but that's even more complicated to follow IMO.
>> Why would the write need to be conditional?
> 
> Because the tokens are different.  One has the value &addr, and one has
> &addr + 9.
> 
> The Supervisor Shadow Stack Token for IDT needs to survive for the
> lifetime of Xen, while the Restore Token for FRED is temporary and
> discarded by the logic added in this patch.
> 
>>  Can't we write what effectively
>> is already there? Or is it more a safety measure to avoid the write when
>> it's supposed to be unnecessary, to avoid papering over bugs?
> 
> I genuinely don't understand what you're trying to suggest here.

I think I misunderstood your earlier reply, so the questions probably
indeed didn't make a while lot of sense.

Jan


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In-Reply-To: <8229c4f7-e1ca-4d79-9131-df5d74e464bc@citrix.com>
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On 22.08.2025 00:56, Andrew Cooper wrote:
> On 15/08/2025 10:10 am, Jan Beulich wrote:
>> On 14.08.2025 22:55, Andrew Cooper wrote:
>>> On 14/08/2025 4:35 pm, Jan Beulich wrote:
>>>> On 08.08.2025 22:23, Andrew Cooper wrote:
>>>>> @@ -154,7 +155,6 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>>>>      "rdsspd %[ssp];"                                            \
>>>>>      "cmp $1, %[ssp];"                                           \
>>>>>      "je .L_shstk_done.%=;" /* CET not active?  Skip. */         \
>>>>> -    "mov $%c[skstk_base], %[val];"                              \
>>>>>      "and $%c[stack_mask], %[ssp];"                              \
>>>>>      "sub %[ssp], %[val];"                                       \
>>>>>      "shr $3, %[val];"                                           \
>>>> With the latter two insns here, ...
>>>>
>>>>> @@ -177,6 +177,8 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>>>>  
>>>>>  #define switch_stack_and_jump(fn, instr, constr)                        \
>>>>>      ({                                                                  \
>>>>> +        unsigned int token_offset =                                     \
>>>>> +            (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - (opt_fred ? 0 : 8);  \
>>>>>          unsigned int tmp;                                               \
>>>>>          BUILD_BUG_ON(!ssaj_has_attr_noreturn(fn));                      \
>>>>>          __asm__ __volatile__ (                                          \
>>>>> @@ -184,12 +186,11 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>>>>>              "mov %[stk], %%rsp;"                                        \
>>>>>              CHECK_FOR_LIVEPATCH_WORK                                    \
>>>>>              instr "[fun]"                                               \
>>>>> -            : [val] "=&r" (tmp),                                        \
>>>>> +            : [val] "=r" (tmp),                                         \
>>>> ... I don't think you can legitimately drop the & from here? With it
>>>> retained:
>>>> Reviewed-by: Jan Beulich 
>>> You chopped the bit which has an explicit input for "[val]", making the
>>> earlyclobber incorrect.
>> I was wondering whether there was a connection there, but ...
>>
>>> IIRC, one version of Clang complained.
>> ... that's not good. Without the early-clobber the asm() isn't quite
>> correct imo. If the same value appeared as another input, the compiler
>> may validly tie both together, assuming the register stays intact until
>> the very last insn (and hence even that last insn could still use the
>> register as an input). IOW if there's a Clang issue here, I think it
>> may need working around explicitly.
> 
> Given that I need an alternative anyway, this becomes much easier, and
> shrinks to this single hunk:
> 
> diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
> index c1eb27b1c4c2..35cc61fa88e7 100644
> --- a/xen/arch/x86/include/asm/current.h
> +++ b/xen/arch/x86/include/asm/current.h
> @@ -154,7 +154,9 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
>      "rdsspd %[ssp];"                                            \
>      "cmp $1, %[ssp];"                                           \
>      "je .L_shstk_done.%=;" /* CET not active?  Skip. */         \
> -    "mov $%c[skstk_base], %[val];"                              \
> +    ALTERNATIVE("mov $%c[skstk_base], %[val];",                 \
> +                "mov $%c[skstk_base] + 8, %[val];",             \
> +                X86_FEATURE_XEN_FRED)                           \
>      "and $%c[stack_mask], %[ssp];"                              \
>      "sub %[ssp], %[val];"                                       \
>      "shr $3, %[val];"                                           \

Oh, okay. But then please again without unnecessary use of $%c constructs,
when just % will do.

Tangential: Now that I look at this again, what's the 1st 'k' standing
for in skstk_base? Was that maybe meant to be 'h'?

Jan

Jan


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Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
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On 31/07/2025 10:27, Petr Beneš wrote:
> From: Petr Beneš 
> 
> This commit introduces the ability to configure the maximum number of altp2m
> views for the domain during its creation. Previously, the limits were hardcoded
> to a maximum of 10. This change allows for greater flexibility in environments
> that require more or fewer altp2m views.
> 
> The maximum configurable limit for nr_altp2m on x86 is now set to
> MAX_NR_ALTP2M (which currently holds the MAX_EPTP value - 512). This cap is
> linked to the architectural limit of the EPTP-switching VMFUNC, which supports
> up to 512 entries. Despite there being no inherent need for limiting nr_altp2m
> in scenarios not utilizing VMFUNC, decoupling these components would necessitate
> substantial code changes.
> 
> xen_domctl_createdomain::altp2m is extended for a new field `nr`, that will
> configure this limit for a domain. Additionally, previous altp2m.opts value
> has been reduced from uint32_t to uint16_t so that both of these fields occupy
> as little space as possible.
> 
> Accesses to the altp2m_p2m array are modified to respect the new nr_altp2m
> value. Accesses to the altp2m_(visible_)eptp arrays are unmodified, since
> these arrays always have fixed size of MAX_EPTP.
> 
> Additional sanitization is introduced in the x86/arch_sanitise_domain_config
> to fix the altp2m.nr value to 10 if it is previously set to 0. This behavior
> is only temporary and immediately removed in the upcoming commit (which will
> disallow creating a domain with enabled altp2m with zero nr_altp2m).
> 
> The reason for this temporary workaround is to retain the legacy behavior
> until the feature is fully activated in libxl.
> 
> Also, arm/arch_sanitise_domain_config is extended to not allow requesting
> non-zero altp2ms.
> 
> Signed-off-by: Petr Beneš 
> Acked-by: Jan Beulich 

Acked-by: Julien Grall 

Cheers,

-- 
Julien Grall



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In-Reply-To: <3c9c7c48c9d8633b4c36bb0bb91fab88c03ae279.1755987697.git.w1benny@gmail.com>
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On 24.08.2025 00:26, Petr Beneš wrote:
> From: Petr Beneš 
> 
> Signed-off-by: Petr Beneš 
> ---
>  CHANGELOG.md | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/CHANGELOG.md b/CHANGELOG.md
> index 271ac73a0a..2fd65b90a9 100644
> --- a/CHANGELOG.md
> +++ b/CHANGELOG.md
> @@ -32,6 +32,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
>       capability usage is not yet supported on PVH dom0).
>     - Smoke tests for the FreeBSD Xen builds in Cirrus CI.
>     - PVH xenstore-stubdom now supports Live Update.
> +   - Support for new SMBIOS tables: 7, 8, 9, 26, 27, 28.

This way it reads as if you mean in Xen, when the change is entirely
contained to hvmloader (and hence affecting only HVM guests). In
something (imo) not primarily targeted at developers I also wonder
whether identifying the tables by number is going to be useful.

Jan


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Date: Mon, 25 Aug 2025 11:30:20 +0200
From: Anthony PERARD 
To: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
	dmukhin@ford.com
Subject: Re: [PATCH v16 2/4] tools/include: move xc_bitops.h to
 xen-tools/bitops.h
Message-ID: 
References: <20250812223024.2364749-1-dmukhin@ford.com>
 <20250812223024.2364749-3-dmukhin@ford.com>
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In-Reply-To: <20250812223024.2364749-3-dmukhin@ford.com>

On Tue, Aug 12, 2025 at 10:30:45PM +0000, dmkhn@proton.me wrote:
> diff --git a/tools/libs/guest/xg_dom_elfloader.c b/tools/libs/guest/xg_dom_elfloader.c
> index f17930d98bf7..8531e90f8e21 100644
> --- a/tools/libs/guest/xg_dom_elfloader.c
> +++ b/tools/libs/guest/xg_dom_elfloader.c
> @@ -25,8 +25,9 @@
>  #include 
>  #include 
>  
> +#include 

It doesn't looks like xg_dom_elfloader.c is using anything from
bitops.h. The last use of it was probably removed in ed04ca95981f
("libelf: rewrite symtab/strtab loading")

> +
>  #include "xg_private.h"
> -#include "xc_bitops.h"
>  
>  #define XEN_VER "xen-3.0"
>  
> diff --git a/tools/libs/guest/xg_dom_hvmloader.c b/tools/libs/guest/xg_dom_hvmloader.c
> index 39e1e5f579a7..0f569c20c522 100644
> --- a/tools/libs/guest/xg_dom_hvmloader.c
> +++ b/tools/libs/guest/xg_dom_hvmloader.c
> @@ -24,8 +24,9 @@
>  #include 
>  #include 
>  
> +#include 
> +

I think there's two reason to remove this include:
- it doesn't looks like xg_dom_hvmloader.c is using any macro from it.
- bitops.h is already included by xg_private.h.


>  #include "xg_private.h"
> -#include "xc_bitops.h"
>  
>  /* ------------------------------------------------------------------------ */
>  /* parse elf binary                                                         */
> diff --git a/tools/libs/guest/xg_sr_common.h b/tools/libs/guest/xg_sr_common.h
> index 2f058ee3a6ff..2e583f2eac72 100644
> --- a/tools/libs/guest/xg_sr_common.h
> +++ b/tools/libs/guest/xg_sr_common.h
> @@ -2,11 +2,10 @@
>  #define __COMMON__H
>  
>  #include 
> +#include 

It's already included in xg_private.h, so this feels unnecessary.
>  
>  #include "xg_private.h"
>  #include "xg_save_restore.h"
> -#include "xc_bitops.h"
> -


If the extraneous includes could be removed, that would be nice. In
anycase:
Acked-by: Anthony PERARD 

Thanks,

-- 
Anthony PERARD


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On 21.08.2025 17:48, Andrew Cooper wrote:
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Acked-by: Jan Beulich 



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Subject: Re: [PATCH 2/2] x86/mce: Adjustments to intel_init_ppin()
To: Andrew Cooper 
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On 21.08.2025 17:48, Andrew Cooper wrote:
> There's no family check gating intel_init_ppin(), making it incorrect to use
> on non Fam6 CPUs.  Switch to using VFM.
> 
> Emerald Rapids is the final CPU to have PPIN but lack the the architectural
> enumeration, so include it too.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 



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Subject: Re: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
To: Dmytro Prokopchuk1 
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On 24.08.2025 16:56, Dmytro Prokopchuk1 wrote:
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -97,6 +97,19 @@ Deviations related to MISRA C:2012 Rules:
>         Xen expects developers to ensure code remains safe and reliable in builds,
>         even when debug-only assertions like `ASSERT_UNREACHABLE() are removed.
>  
> +   * - R2.1
> +     - The 'BUG()' macro is intentionally used in the 'prepare_acpi()' function
> +       in specific build configuration (when the config CONFIG_ACPI is not
> +       defined) to trigger an error if ACPI-related features are used incorrectly.
> +     - Tagged as `deliberate` for ECLAIR.

With

#define acpi_disabled true

in xen/acpi.h I don't see why we even have that inline stub. When it's dropped
and the declaration left in place without #ifdef CONFIG_ACPI around it, the
compiler will DCE the code (much like we arrange for in many other places). No
deviation needed then.

If such a deviation was to be added, it would need disambiguating. A function
of the given name could appear in x86 as well. That wouldn't be covered by the
Eclair config then, but it would be covered by the text here.

> +   * - R2.1
> +     - The 'BUG()' macro is intentionally used in 'gicv3_do_LPI'() and
> +       'gicv3_its_setup_collection()' functions in specific build configuration
> +       (when the config CONFIG_HAS_ITS is not defined) to catch and prevent any
> +       unintended execution of code that should only run when ITS is available.
> +     - Tagged as `deliberate` for ECLAIR.

I didn't look at this, but I would very much hope that something similar could
be done there as well.

Jan


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On 24.08.2025 17:10, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 2.1 states: "A project shall not contain unreachable code."
> 
> The return statements in the 'read_file()' function is unreachable due

Especially due to the (imo wrong) use of plural, this continues to be
ambiguous. I'd suggest switching to singular and inserting "final" or
"main". Happy to adjust while committing, provided you agree.

Jan


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Subject: Re: [PATCH v2] misra: add deviation for MISRA C Rule 11.3
To: Dmytro Prokopchuk1 ,
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 Stefano Stabellini 
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On 24.08.2025 19:27, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 11.3 states: "A cast shall not be performed between a pointer
> to object type and a pointer to a different object type."
> 
> Violations of this rule arise due to the 'container_of()' macro, which casts
> a member of a structure to its containing structure:
>     container_of(ptr, type, member) ({                             \
>            typeof_field(type, member) *__mptr = (ptr);             \
>            (type *)( (char *)__mptr - offsetof(type,member) );})
> 
> The 'container_of()' macro is safe because it relies on the standardized and
> well-defined 'offsetof()' macro to calculate the memory address of the
> containing structure, while assuming proper alignment and ensuring no
> undefined behavior, provided that the input pointer is valid and points to
> the specified member.

I may have said so before: This all reads okay to me, just that I'm unsure
it would actually be convincing to an assessor. The "provided that ..." is
a pretty strong requirement, which isn't overly hard to get wrong. Stefano,
Nicola - what's your take here?

Jan


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To: Jan Beulich 
CC: Nicola Vetrini , Doug Goldstein
	, Stefano Stabellini , Andrew
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	, Michal Orzel , Julien
 Grall , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
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Subject: Re: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
Thread-Topic: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
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Subject: Re: [PATCH v4] common/efi: fix Rule 2.1 violation in read_file()
Thread-Topic: [PATCH v4] common/efi: fix Rule 2.1 violation in read_file()
Thread-Index: AQHcFQlF20ah2tP5uUOdXQ1Ea/l407RzJ1sAgAAEg4A=
Date: Mon, 25 Aug 2025 10:28:18 +0000
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Subject: Re: [PATCH] misra: add deviation of Rule 17.7
To: Dmytro Prokopchuk1 
Cc: Nicola Vetrini ,
 Doug Goldstein ,
 Stefano Stabellini ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
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On 25.08.2025 11:05, Dmytro Prokopchuk1 wrote:
> MISRA C Rule 17.7 states: "The value returned by a function having
> non-void return type shall be used."
> 
> Deviate functions like 'memcpy()', 'memset()', 'memmove()', 'snprintf()',
> 'strlcpy()', 'strlcat()', as they return a value purely for convenience,
> their primary functionality (e.g., memory or string operations) remains
> unaffected, and their return values are generally non-critical and seldom
> relied upon. Update 'deviations.rst' file accordingly.

How come snprintf() is among this set? Its return value isn't quite just
for convenience, imo.

Jan


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From: Dmytro Prokopchuk1 
To: Jan Beulich 
CC: Nicola Vetrini , Doug Goldstein
	, Stefano Stabellini , Andrew
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	, Michal Orzel , Julien
 Grall , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, "xen-devel@lists.xenproject.org"
	
Subject: Re: [PATCH] misra: add deviation of Rule 17.7
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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[PATCH=20v5=203/4]=20hvmloader:=20add=20new=20SMBIOS=20tables=20(7,=208,=209,=2026,=2027,=2028)?=
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To: "=?utf-8?Q?Petr=20Bene=C5=A1?=" , xen-devel@lists.xenproject.org
Cc: "Jan Beulich" , "Andrew Cooper" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Anthony PERARD" 
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Hello,

Le 24/08/2025 =C3=A0 00:29, Petr Bene=C5=A1 a =C3=A9crit=C2=A0:
> +/* Type 7 -- Cache Information */
> +static void *
> +smbios_type_7_init(void *start)
> +{
> +    /* Specification says Type 7 table has length of 13h for v2.1+. */
> +    BUILD_BUG_ON(sizeof(struct smbios_type_7) !=3D 19);
> +

I would prefer having hex constants (so that it matches the number 
format the specification gives).

e.g
BUILD_BUG_ON(sizeof(struct smbios_type_7) !=3D 0x13);

(same for other checks)

Teddy


Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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On 14.08.2025 08:46, Jan Beulich wrote:
> On 14.08.2025 02:29, Daniel P. Smith wrote:
>> On 8/12/25 02:12, Jan Beulich wrote:
>>> On 12.08.2025 02:19, Daniel P. Smith wrote:
>>>> On 7/23/25 09:39, Jan Beulich wrote:
>>>>> Use the more "modern" form, thus doing away with effectively open-coding
>>>>> xmalloc_array() at the same time. While there is a difference in
>>>>> generated code, as xmalloc_bytes() forces SMP_CACHE_BYTES alignment, if
>>>>> code really cared about such higher than default alignment, it should
>>>>> request so explicitly.
>>>>
>>>> While I don't object to the change itself, I think this description is a
>>>> bit over simplification of the change. If the allocation is under
>>>> PAGE_SIZE, then they are equivalent, but if it is over the page size
>>>> there are a few more differences than just cache alignment. It
>>>> completely changes the underlying allocator. I personally also find it a
>>>> bit of a stretch to call xmalloc_bytes(size) an open coded version of
>>>> xmalloc_array(char, size).
>>>
>>> My take is that xmalloc_bytes() should never have existed. Hence why I
>>> didn't add xzmalloc_bytes() when introducing that family of interfaces.
>>
>> Right, which would be a valid argument for replacing it with 
>> xmalloc_array(). Though, I would note that there is an xzalloc_bytes(). 
>> My concern was that you stated there was an open coding, which had me 
>> expecting there was a line of the form, xmanlloc_bytes(count * 
>> size_of_something bigger), being replaced by 
>> xvmalloc_arryay(something_bigger, count).
> 
> Both fir this and ...
> 
>> IMHO, while the C spec does specify char as 1 byte and thus 
>> interchangeable, I would agree that from a contextual perspective, 
>> xmalloc_array() is the more appropriate call. The use of the allocation 
>> is a character array and not a chunk of bytes for an arbitrary buffer.
> 
> ... for this: Hence my wording using "effectively".
> 
>>>> With a stronger description of the change,
>>>
>>> So what exactly do you mean by "stronger"? I can add that in the unlikely
>>> event that one of the allocations is (near) PAGE_SIZE or larger, we now
>>> wouldn't require contiguous memory anymore. Yet based on your comment at
>>> the top I'm not quite sure if that's what you're after and/or enough to
>>> satisfy your request.
>>
>> The phrasing stronger was meant to be more clear on the change/effect, 
>> specifically that the underlying allocator is being changed when the 
>> allocation is greater than a PAGE_SIZE. Not necessarily a long 
>> explanation, just the fact that the allocation will be coming from the 
>> dom heap allocator as opposed to the xen heap allocator. There are 
>> implications to changing the allocater, e.g.,  at a minimum the 
>> allocation order and nonphysical vs. physically contiguous effects. 
>> Having it noted in the commit makes it more obvious what this change is 
>> actually doing. Which may not be obvious when seeing the simple line 
>> changes occurring in the diff. Later, if there is an unexpected 
>> consequence caused by this change, a stronger commit will be helpful 
>> with the bisection investigations.
> 
> First: I don't think each and every such change (there are going to be many)
> should re-explain the switch to the xvmalloc() family of functions. This is
> already stated clearly at the top of xvmalloc.h: Over time, the entire code
> base is meant to be switched.
> 
> Beyond that, to achieve the stronger wording you're after, would it perhaps
> suffice to have the first sentence say "..., thus also doing away ..."?
> Otherwise, may I ask that you please make a more concrete suggestion?

Ping. I'd like to get this in, yet I still don't know how exactly to satisfy
your request for a stronger description.

Jan


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Subject: Re: [PATCH] misra: add deviation of Rule 17.7
To: Dmytro Prokopchuk1 
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On 25.08.2025 12:58, Dmytro Prokopchuk1 wrote:
> On 8/25/25 13:30, Jan Beulich wrote:
>> On 25.08.2025 11:05, Dmytro Prokopchuk1 wrote:
>>> MISRA C Rule 17.7 states: "The value returned by a function having
>>> non-void return type shall be used."
>>>
>>> Deviate functions like 'memcpy()', 'memset()', 'memmove()', 'snprintf()',
>>> 'strlcpy()', 'strlcat()', as they return a value purely for convenience,
>>> their primary functionality (e.g., memory or string operations) remains
>>> unaffected, and their return values are generally non-critical and seldom
>>> relied upon. Update 'deviations.rst' file accordingly.
>>
>> How come snprintf() is among this set? Its return value isn't quite just
>> for convenience, imo.
> 
> Yes, snprintf()'s return value isn't just for convenience. The deviation 
> justification is primarily based on the fact that its return value is 
> rarely used in the Xen source base. Most callers of snprintf() don't 
> care about return value. So, snprintf() is in this list.
> 
> Maybe separate wording is required for the snprintf() ?

Minimally. Personally I don't think it should be deviated globally.

Jan


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Subject: Re: [PATCH v5 3/4] hvmloader: add new SMBIOS tables (7, 8, 9, 26, 27,
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On 25.08.2025 13:04, Teddy Astie wrote:
> Le 24/08/2025 à 00:29, Petr Beneš a écrit :
>> +/* Type 7 -- Cache Information */
>> +static void *
>> +smbios_type_7_init(void *start)
>> +{
>> +    /* Specification says Type 7 table has length of 13h for v2.1+. */
>> +    BUILD_BUG_ON(sizeof(struct smbios_type_7) != 19);
>> +
> 
> I would prefer having hex constants (so that it matches the number 
> format the specification gives).
> 
> e.g
> BUILD_BUG_ON(sizeof(struct smbios_type_7) != 0x13);
> 
> (same for other checks)

While reviewing I was first inclined to ask the same, but then though that
with the hex values stated in comments it would be fine either way.

Jan


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Subject: [PATCH] Arm/platforms: fix build with gcc15
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For two of the headers gcc15 complains "header guard ... followed by
'#define' of a different macro". Misra certainly wouldn't have liked
this either, if these headers were covered by a scan.

Signed-off-by: Jan Beulich 

--- a/xen/arch/arm/include/asm/platforms/midway.h
+++ b/xen/arch/arm/include/asm/platforms/midway.h
@@ -1,5 +1,5 @@
 #ifndef __ASM_ARM_PLATFORMS_MIDWAY_H
-#define __ASM_ASM_PLATFORMS_MIDWAY_H
+#define __ASM_ARM_PLATFORMS_MIDWAY_H
 
 /* addresses of SREG registers for resetting the SoC */
 #define MW_SREG_PWR_REQ             0xfff3cf00
--- a/xen/arch/arm/include/asm/platforms/omap5.h
+++ b/xen/arch/arm/include/asm/platforms/omap5.h
@@ -1,5 +1,5 @@
 #ifndef __ASM_ARM_PLATFORMS_OMAP5_H
-#define __ASM_ASM_PLATFORMS_OMAP5_H
+#define __ASM_ARM_PLATFORMS_OMAP5_H
 
 #define REALTIME_COUNTER_BASE                   0x48243200
 #define INCREMENTER_NUMERATOR_OFFSET            0x10


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Subject: Re: [PATCH 4/5] vpci/msix: move MSI-X hole punching as a result of
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To: Roger Pau Monne 
Cc: stewart.hildebrand@amd.com, Jiqian.Chen@amd.com,
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References: <20250814160358.95543-1-roger.pau@citrix.com>
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On 14.08.2025 18:03, Roger Pau Monne wrote:
> Deferring the p2m unpopulate of the MSI-X table region to after the BAR are
> mapped in the p2m is not needed.

For my own understanding: This is because we would never actively map such a
region; we always subtract it out of what is going to be mapped. If so ...

>  The aim of vpci_make_msix_hole() is to
> cope with the BAR containing the MSI-X table being positioned over a
> reserved e820 region, by making sure the MSI-X table region is
> unpopulated on the p2m. Note that reserved e820 regions are identity mapped
> in the hardware domain p2m by default.
> 
> Doing it before or after the BAR p2m changes are done is irrelevant, hence
> do it ahead of the p2m changes, as that's simpler.
> 
> Signed-off-by: Roger Pau Monné 

Reviewed-by: Jan Beulich 

Jan


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CC: Julien Grall , Stefano Stabellini
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On 18/08/2025 09:55, Jan Beulich wrote:
> Its uses in offline_page() and query_page_offline() make it reachable on
> Arm, as long as XEN_SYSCTL_page_offline_op doesn't have any Arm-specific
> code added. It being reachable was even mentioned in the commit
> introducing it, claiming it "clearly shouldn't be called on ARM just
> yet".
> 
> However, dropping the assertion from a function of this name is deemed
> problematic. Rename it to better reflect its sole purpose outside of
> x86-specific code.
> 
> Fixes: 214c4cd94a80 ("xen: arm: stub page_is_ram_type")
> Signed-off-by: Jan Beulich 
Acked-by: Michal Orzel 

~Michal



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To: Jan Beulich , "xen-devel@lists.xenproject.org"
	
CC: Julien Grall , Stefano Stabellini
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On 25/08/2025 13:14, Jan Beulich wrote:
> For two of the headers gcc15 complains "header guard ... followed by
> '#define' of a different macro". Misra certainly wouldn't have liked
> this either, if these headers were covered by a scan.
> 
> Signed-off-by: Jan Beulich 
Acked-by: Michal Orzel 

~Michal



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Subject: Re: [PATCH 5/5] xen/vpci: only check BAR validity once
To: Roger Pau Monne 
Cc: stewart.hildebrand@amd.com, Jiqian.Chen@amd.com,
 Andrew Cooper , xen-devel@lists.xenproject.org
References: <20250814160358.95543-1-roger.pau@citrix.com>
 <20250814160358.95543-6-roger.pau@citrix.com>
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On 14.08.2025 18:03, Roger Pau Monne wrote:
> Avoid multiple calls to pci_check_bar() for the same memory decoding
> related operation, as each call can possibly print a warning message avoid
> a BAR being in an invalid position.

s/avoid/about/ ?

> @@ -217,13 +179,13 @@ bool vpci_process_pending(struct vcpu *v)
>           * rangeset_consume_ranges() itself doesn't generate any errors.
>           */
>          rangeset_purge(bar->mem);
> +
> + next:
> +        if ( bar->valid )
> +            bar->enabled = v->vpci.cmd & PCI_COMMAND_MEMORY;

Isn't it at least latently risky to possibly leave ->enabled set to true
when ->valid is false?

> @@ -243,10 +205,8 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev,
>          struct vpci_bar *bar = &header->bars[i];
>          struct map_data data = { .d = d, .map = true, .bar = bar };
>  
> -        if ( rangeset_is_empty(bar->mem) )
> -            continue;
> -
> -        while ( (rc = rangeset_consume_ranges(bar->mem, map_range,
> +        while ( bar->mem &&
> +                (rc = rangeset_consume_ranges(bar->mem, map_range,
>                                                &data)) == -ERESTART )
>          {
>              /*
> @@ -258,9 +218,10 @@ static int __init apply_map(struct domain *d, const struct pci_dev *pdev,
>              process_pending_softirqs();
>              write_lock(&d->pci_lock);
>          }
> +
> +        if ( bar->valid )
> +            bar->enabled = true;
>      }
> -    if ( !rc )
> -        modify_decoding(pdev, cmd, false);
>  
>      return rc;
>  }
> @@ -326,6 +287,9 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only)
>           */
>          rangeset_purge(bar->mem);
>  
> +        /* Reset whether the BAR is valid, will be checked below. */
> +        bar->valid = false;

Just that I can't spot any check further down. It's only ...

> @@ -341,6 +305,8 @@ static int modify_bars(const struct pci_dev *pdev, uint16_t cmd, bool rom_only)
>              continue;
>          }
>  
> +        bar->valid = true;

... this setting to true.

> @@ -539,6 +505,7 @@ static void cf_check cmd_write(
>      if ( (cmd & PCI_COMMAND_MEMORY) && vpci_make_msix_hole(pdev) )
>          return;
>  #endif
> +
>      /*
>       * FIXME: for domUs we don't want the guest toggling the memory decoding
>       * bit.  It should be set in vpci_init_header() and guest attempts to

This change was probably meant to go into an earlier patch?

Jan


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Subject: Re: [XEN PATCH v1] xen/flask: limit sidtable size
To: Sergiy Kibrik 
Cc: Andrew Cooper ,
 Anthony PERARD ,
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 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 22.08.2025 11:51, Sergiy Kibrik wrote:
> --- a/xen/common/Kconfig
> +++ b/xen/common/Kconfig

I wonder whether we wouldn't better move XSM's controls to a dedicated Kconfig
file there.

> @@ -418,6 +418,25 @@ config XSM_FLASK_AVC_STATS
>  
>  	  If unsure, say Y.
>  
> +config XSM_FLASK_SIDTABLE_LIMIT
> +	def_bool n

This makes little sense; just "bool" would have the same effect. Yet then
you can combine that with ...

> +	prompt "Limit the size of SID table" if EXPERT

... this line.

> +	depends on XSM_FLASK
> +	---help---

No triple dashes around "help" anymore, please.

> +	  Limit the number of security identifiers allocated and operated by Xen.
> +	  This will limit the number of security contexts and heap memory
> +	  allocated for SID table entries.
> +
> +	  If unsure, say N.
> +
> +config XSM_FLASK_MAX_SID
> +	int "Max SID table size" if XSM_FLASK_SIDTABLE_LIMIT
> +	default 512

Hmm, wouldn't the default better be what we had so far? As per the justification
you aim at a special case (embedded) with this limit.

> +	help
> +	  The maximum amount of SIDs allocated by Xen. Default value is
> +	  approximately double the size of contexts that default Xen policy can
> +	  potentially have.

Do we need two controls? Can't 0 mean "no limit"? Or else what use is permitting
0 here as a value?

Jan


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Subject: Re: [PATCH v3 08/11] mm/memory: convert print_bad_pte() to
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To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org, xen-devel@lists.xenproject.org,
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References: <20250811112631.759341-1-david@redhat.com>
 <20250811112631.759341-9-david@redhat.com>
From: David Hildenbrand 
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On 11.08.25 13:26, David Hildenbrand wrote:
> print_bad_pte() looks like something that should actually be a WARN
> or similar, but historically it apparently has proven to be useful to
> detect corruption of page tables even on production systems -- report
> the issue and keep the system running to make it easier to actually detect
> what is going wrong (e.g., multiple such messages might shed a light).
> 
> As we want to unify vm_normal_page_*() handling for PTE/PMD/PUD, we'll have
> to take care of print_bad_pte() as well.
> 
> Let's prepare for using print_bad_pte() also for non-PTEs by adjusting the
> implementation and renaming the function to print_bad_page_map().
> Provide print_bad_pte() as a simple wrapper.
> 
> Document the implicit locking requirements for the page table re-walk.
> 
> To make the function a bit more readable, factor out the ratelimit check
> into is_bad_page_map_ratelimited() and place the printing of page
> table content into __print_bad_page_map_pgtable(). We'll now dump
> information from each level in a single line, and just stop the table
> walk once we hit something that is not a present page table.
> 
> The report will now look something like (dumping pgd to pmd values):
> 
> [   77.943408] BUG: Bad page map in process XXX  pte:80000001233f5867
> [   77.944077] addr:00007fd84bb1c000 vm_flags:08100071 anon_vma: ...
> [   77.945186] pgd:10a89f067 p4d:10a89f067 pud:10e5a2067 pmd:105327067
> 
> Not using pgdp_get(), because that does not work properly on some arm
> configs where pgd_t is an array. Note that we are dumping all levels
> even when levels are folded for simplicity.
> 
> Signed-off-by: David Hildenbrand 
> ---
>   include/linux/pgtable.h |  19 ++++++++
>   mm/memory.c             | 104 ++++++++++++++++++++++++++++++++--------
>   2 files changed, 103 insertions(+), 20 deletions(-)
> 
> diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
> index bff5c4241bf2e..33c84b38b7ec6 100644
> --- a/include/linux/pgtable.h
> +++ b/include/linux/pgtable.h
> @@ -1966,6 +1966,25 @@ enum pgtable_level {
>   	PGTABLE_LEVEL_PGD,
>   };
>   
> +static inline const char *pgtable_level_to_str(enum pgtable_level level)
> +{
> +	switch (level) {
> +	case PGTABLE_LEVEL_PTE:
> +		return "pte";
> +	case PGTABLE_LEVEL_PMD:
> +		return "pmd";
> +	case PGTABLE_LEVEL_PUD:
> +		return "pud";
> +	case PGTABLE_LEVEL_P4D:
> +		return "p4d";
> +	case PGTABLE_LEVEL_PGD:
> +		return "pgd";
> +	default:
> +		VM_WARN_ON_ONCE(1);
> +		return "unknown";
> +	}
> +}

One kernel config doesn't like the VM_WARN_ON_ONCE here, and I don't think we
really need it. @Andrew can you squash:

 From 0b8f6cdfe2c9d96393e7da1772e82048e096a903 Mon Sep 17 00:00:00 2001
From: David Hildenbrand 
Date: Mon, 25 Aug 2025 14:25:59 +0200
Subject: [PATCH] fixup: mm/memory: convert print_bad_pte() to
  print_bad_page_map()

Let's just drop the warning, it's highly unlikely that we ever run into
this, and if so, there is serious stuff going wrong elsewhere.

Signed-off-by: David Hildenbrand 
---
  include/linux/pgtable.h | 1 -
  1 file changed, 1 deletion(-)

diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
index 9f0329d45b1e1..94249e671a7e8 100644
--- a/include/linux/pgtable.h
+++ b/include/linux/pgtable.h
@@ -1997,7 +1997,6 @@ static inline const char *pgtable_level_to_str(enum pgtable_level level)
  	case PGTABLE_LEVEL_PGD:
  		return "pgd";
  	default:
-		VM_WARN_ON_ONCE(1);
  		return "unknown";
  	}
  }
-- 
2.50.1


-- 
Cheers

David / dhildenb



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Date: Mon, 25 Aug 2025 14:53:41 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: Jan Beulich , Doug Goldstein ,
 Stefano Stabellini , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 xen-devel@lists.xenproject.org
Subject: Re: [PATCH] misra: consider conversion from UL or (void*) to function
 pointer as safe
In-Reply-To: <6b912698-b871-4819-ac30-14325d0be146@epam.com>
References: <9e5e4ff2c7ba0a90a6ac403e2de9318e18949274.1755628705.git.dmytro_prokopchuk1@epam.com>
 <90fb95a3-4b32-4785-a77c-373e5b9da6ed@suse.com>
 
 <6b912698-b871-4819-ac30-14325d0be146@epam.com>
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On 2025-08-22 18:34, Dmytro Prokopchuk1 wrote:
> On 8/21/25 11:25, Nicola Vetrini wrote:
>> On 2025-08-21 10:01, Jan Beulich wrote:
>>> On 19.08.2025 20:55, Dmytro Prokopchuk1 wrote:
>>>> Rule 11.1 states as following: "Conversions shall not be performed
>>>> between a pointer to a function and any other type."
>>>> 
>>>> The conversion from unsigned long or (void *) to a function pointer
>>>> is safe in Xen because the architectures it supports (e.g., x86 and
>>>> ARM) guarantee compatible representations between these types.
>>> 
>>> I think we need to be as precise as possible here. The architectures
>>> guarantee nothing, they only offer necessary fundamentals. In the
>>> Windows x86 ABI, for example, you can't convert pointers to/from 
>>> longs
>>> without losing data. What we build upon is what respective ABIs say,
>>> possibly in combination of implementation specifics left to 
>>> compilers.
>>> 
>> 
>> +1, a mention of the compilers and targets this deviation relies upon 
>> is
>> needed.
> 
> Maybe with this wording:
> 
> This deviation is based on the guarantees provided by the specific ABIs
> (e.g., ARM AAPCS) and compilers (e.g., GCC) supported in Xen. These 
> ABIs

s/supported in/supported by/

> guarantee compatible representations for 'void *', 'unsigned long' and
> function pointers for the supported target platforms. This behavior is

It's not just about the guarantees of the ABIs: it's the behavior of the 
compiler for those ABIs that makes this safe or unsafe. If present, such 
documentation should be included

> architecture-specific and may not be portable outside of supported
> environments.
> 
>> 
>>>> --- a/docs/misra/deviations.rst
>>>> +++ b/docs/misra/deviations.rst
>>>> @@ -370,6 +370,16 @@ Deviations related to MISRA C:2012 Rules:
>>>>         to store it.
>>>>       - Tagged as `safe` for ECLAIR.
>>>> 
>>>> +   * - R11.1
>>>> +     - The conversion from unsigned long or (void \*) to a function
>>>> pointer does
>>>> +       not lose any information or violate type safety assumptions
>>>> if unsigned
>>>> +       long or (void \*) type is guaranteed to be the same bit size
>>>> as a
>>>> +       function pointer. This ensures that the function pointer can
>>>> be fully
>>>> +       represented without truncation or corruption. The macro
>>>> BUILD_BUG_ON is
>>>> +       integrated into xen/common/version.c to confirm conversion
>>>> compatibility
>>>> +       across all target platforms.
>>>> +     - Tagged as `safe` for ECLAIR.
>>> 
>>> Why the escaping of * here, when ...
>>> 
>>>> --- a/docs/misra/rules.rst
>>>> +++ b/docs/misra/rules.rst
>>>> @@ -431,7 +431,13 @@ maintainers if you want to suggest a change.
>>>>       - All conversions to integer types are permitted if the
>>>> destination
>>>>         type has enough bits to hold the entire value. Conversions 
>>>> to
>>>> bool
>>>>         and void* are permitted. Conversions from 'void noreturn (*)
>>>> (...)'
>>>> -       to 'void (*)(...)' are permitted.
>>>> +       to 'void (*)(...)' are permitted. Conversions from unsigned
>>>> long or
>>>> +       (void \*) to a function pointer are permitted if the source
>>>> type has
>>>> +       enough bits to restore function pointer without truncation 
>>>> or
>>>> corruption.
>>>> +       Example::
>>>> +
>>>> +           unsigned long func_addr = (unsigned long)&some_function;
>>>> +           void (*restored_func)(void) = (void (*)(void))func_addr;
>>> 
>>> ... context here suggests they work fine un-escaped, and you even add
>>> some un-
>>> escaped instances as well. Perhaps I'm simply unaware of some
>>> peculiarity?
>>> 
>> 
>> This is a literal rst block, while the other is not (* acts as a 
>> bullet
>> point in rst iirc)
> 
> This is how "sphinx-build" tool interprets this.
> 1. * inside single quotes '' -> looks normal, e.g. ‘void (*)(…)’
> 2. * without quotes -> warning
> deviations.rst:369: WARNING: Inline emphasis start-string without
> end-string. [docutils]
> 3. \* -> looks normal, e.g. (void *)
> 
> Because that we need such format: \*
> 
> Dmytro.
> 
>> 
>>> Jan
>> 

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Mon, 25 Aug 2025 15:08:10 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: Jan Beulich , Doug Goldstein ,
 Stefano Stabellini , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 xen-devel@lists.xenproject.org
Subject: Re: [PATCH] misra: consider conversion from UL or (void*) to function
 pointer as safe
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 <90fb95a3-4b32-4785-a77c-373e5b9da6ed@suse.com>
 
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On 2025-08-25 14:53, Nicola Vetrini wrote:
> On 2025-08-22 18:34, Dmytro Prokopchuk1 wrote:
>> On 8/21/25 11:25, Nicola Vetrini wrote:
>>> On 2025-08-21 10:01, Jan Beulich wrote:
>>>> On 19.08.2025 20:55, Dmytro Prokopchuk1 wrote:
>>>>> Rule 11.1 states as following: "Conversions shall not be performed
>>>>> between a pointer to a function and any other type."
>>>>> 
>>>>> The conversion from unsigned long or (void *) to a function pointer
>>>>> is safe in Xen because the architectures it supports (e.g., x86 and
>>>>> ARM) guarantee compatible representations between these types.
>>>> 
>>>> I think we need to be as precise as possible here. The architectures
>>>> guarantee nothing, they only offer necessary fundamentals. In the
>>>> Windows x86 ABI, for example, you can't convert pointers to/from 
>>>> longs
>>>> without losing data. What we build upon is what respective ABIs say,
>>>> possibly in combination of implementation specifics left to 
>>>> compilers.
>>>> 
>>> 
>>> +1, a mention of the compilers and targets this deviation relies upon 
>>> is
>>> needed.
>> 
>> Maybe with this wording:
>> 
>> This deviation is based on the guarantees provided by the specific 
>> ABIs
>> (e.g., ARM AAPCS) and compilers (e.g., GCC) supported in Xen. These 
>> ABIs
> 
> s/supported in/supported by/
> 
>> guarantee compatible representations for 'void *', 'unsigned long' and
>> function pointers for the supported target platforms. This behavior is
> 
> It's not just about the guarantees of the ABIs: it's the behavior of 
> the compiler for those ABIs that makes this safe or unsafe. If present, 
> such documentation should be included
> 

In any case, provided that the wording can be adjusted:

Reviewed-by: Nicola Vetrini 

>> architecture-specific and may not be portable outside of supported
>> environments.
>> 
>>> 
>>>>> --- a/docs/misra/deviations.rst
>>>>> +++ b/docs/misra/deviations.rst
>>>>> @@ -370,6 +370,16 @@ Deviations related to MISRA C:2012 Rules:
>>>>>         to store it.
>>>>>       - Tagged as `safe` for ECLAIR.
>>>>> 
>>>>> +   * - R11.1
>>>>> +     - The conversion from unsigned long or (void \*) to a 
>>>>> function
>>>>> pointer does
>>>>> +       not lose any information or violate type safety assumptions
>>>>> if unsigned
>>>>> +       long or (void \*) type is guaranteed to be the same bit 
>>>>> size
>>>>> as a
>>>>> +       function pointer. This ensures that the function pointer 
>>>>> can
>>>>> be fully
>>>>> +       represented without truncation or corruption. The macro
>>>>> BUILD_BUG_ON is
>>>>> +       integrated into xen/common/version.c to confirm conversion
>>>>> compatibility
>>>>> +       across all target platforms.
>>>>> +     - Tagged as `safe` for ECLAIR.
>>>> 
>>>> Why the escaping of * here, when ...
>>>> 
>>>>> --- a/docs/misra/rules.rst
>>>>> +++ b/docs/misra/rules.rst
>>>>> @@ -431,7 +431,13 @@ maintainers if you want to suggest a change.
>>>>>       - All conversions to integer types are permitted if the
>>>>> destination
>>>>>         type has enough bits to hold the entire value. Conversions 
>>>>> to
>>>>> bool
>>>>>         and void* are permitted. Conversions from 'void noreturn 
>>>>> (*)
>>>>> (...)'
>>>>> -       to 'void (*)(...)' are permitted.
>>>>> +       to 'void (*)(...)' are permitted. Conversions from unsigned
>>>>> long or
>>>>> +       (void \*) to a function pointer are permitted if the source
>>>>> type has
>>>>> +       enough bits to restore function pointer without truncation 
>>>>> or
>>>>> corruption.
>>>>> +       Example::
>>>>> +
>>>>> +           unsigned long func_addr = (unsigned 
>>>>> long)&some_function;
>>>>> +           void (*restored_func)(void) = (void 
>>>>> (*)(void))func_addr;
>>>> 
>>>> ... context here suggests they work fine un-escaped, and you even 
>>>> add
>>>> some un-
>>>> escaped instances as well. Perhaps I'm simply unaware of some
>>>> peculiarity?
>>>> 
>>> 
>>> This is a literal rst block, while the other is not (* acts as a 
>>> bullet
>>> point in rst iirc)
>> 
>> This is how "sphinx-build" tool interprets this.
>> 1. * inside single quotes '' -> looks normal, e.g. ‘void (*)(…)’
>> 2. * without quotes -> warning
>> deviations.rst:369: WARNING: Inline emphasis start-string without
>> end-string. [docutils]
>> 3. \* -> looks normal, e.g. (void *)
>> 
>> Because that we need such format: \*
>> 
>> Dmytro.
>> 
>>> 
>>>> Jan
>>> 

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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From: Dmytro Prokopchuk1 
To: Jan Beulich 
CC: Nicola Vetrini , Doug Goldstein
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Subject: Re: [PATCH] misra: add deviation of Rule 17.7
Thread-Topic: [PATCH] misra: add deviation of Rule 17.7
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Date: Mon, 25 Aug 2025 13:27:44 +0000
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Date: Mon, 25 Aug 2025 15:47:39 +0200
From: Anthony PERARD 
To: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
	dmukhin@ford.com, Julien Grall 
Subject: Re: [PATCH v16 3/4] tools/tests: introduce unit tests for domain ID
 allocator
Message-ID: 
References: <20250812223024.2364749-1-dmukhin@ford.com>
 <20250812223024.2364749-4-dmukhin@ford.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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In-Reply-To: <20250812223024.2364749-4-dmukhin@ford.com>

On Tue, Aug 12, 2025 at 10:30:50PM +0000, dmkhn@proton.me wrote:
> diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignore
> new file mode 100644
> index 000000000000..0e02715159c2
> --- /dev/null
> +++ b/tools/tests/domid/.gitignore
> @@ -0,0 +1,3 @@
> +*.o

"*.o" is already in the .gitignore at the root of the project. I don't
think it's useful here.

> +generated
> +test-domid
> diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile
> new file mode 100644
> index 000000000000..0a124a8bfc76
> --- /dev/null
> +++ b/tools/tests/domid/Makefile
> @@ -0,0 +1,84 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# Unit tests for domain ID allocator.
> +#
> +# Copyright 2025 Ford Motor Company
> +
> +XEN_ROOT=$(CURDIR)/../../..
> +include $(XEN_ROOT)/tools/Rules.mk
> +
> +TESTS := test-domid
> +
> +strip-list = $(sort $(strip $(foreach x,$(1),$(strip $(x)))))

What's that macro for? Also, what's a "list"?

> +define list-c-headers
> +$(shell sed -n -r \

Could you use "-E" instead of "-r"? (-r might not work on FreeBSD)

> +    's/^[ \t]*# *include[ \t]*[<"]([^">]+)[">].*/\1/p' $(1) 2>/dev/null)
> +endef
> +
> +define emit-harness-nested-rule
> +$(1): $(CURDIR)/harness.h
> +	mkdir -p $$(dir $$@)

You can use $(@D) instead of $(dir $@). The only difference is a /
not present at the end. 

> +	ln -sf $$^ $$@

This should use $<, I don't think the command is going to work if
there's multiple prerequisite.

> +endef
> +
> +define emit-harness-rules
> +ifneq ($(strip $(3)),)

How many time do you need to call $(strip) ?
Also, I think I would prefer to have $(if $(strip $(3)), [the rest])
rather than actually evaluating code and generating code that we already
know is isn't going to be executed.

> +$(foreach h,$(3),$(call emit-harness-nested-rule,$(CURDIR)/generated/$(h)))
> +vpath $(1) $(2)
> +$(1:.c=.o): $(addprefix $(CURDIR)/generated/,$(3))
> +endif
> +endef

This macro fails if there's more than one "#include" in "domid.c".

And if there's no "#include" in "domid.c", then Make doesn't know how to
make "domid.o" for "test-domid".

> +
> +define vpath-with-harness-deps
> +$(call emit-harness-rules,$(1),$(2),\
> +    $(call strip-list,$(call list-c-headers,$(2)$(1))))
> +endef
> +
> +.PHONY: all
> +all: $(TESTS)
> +
> +.PHONY: run
> +run: $(TESTS)
> +	$(foreach t,$(TESTS),./$(t);)

This recipe doesn't work as expected. You need `set -e` or only the last
tests count.

> +
> +.PHONY: clean
> +clean:
> +	$(RM) -rf $(CURDIR)/generated

$(RM) already contain the '-f' option, no need to add it a second time.

Also, we expected Make to run all commands in recipe from $(CURDIR), so
adding $(CURDIR) is unnecessary, could potentially be an issue.

> +	$(RM) -- *.o $(TESTS) $(DEPS_RM)
> +
> +.PHONY: distclean
> +distclean: clean
> +	$(RM) -- *~
> +
> +.PHONY: install
> +install: all
> +	$(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests
> +	$(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests
> +
> +.PHONY: uninstall
> +uninstall:
> +	$(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid
> +
> +CFLAGS += -D__XEN_TOOLS__
> +# find-next-bit.c
> +CFLAGS += '-DEXPORT_SYMBOL(x)=' \
> +          -Dfind_first_bit \
> +          -Dfind_first_zero_bit \
> +          -Dfind_next_bit \
> +          -Dfind_next_bit_le \
> +          -Dfind_next_zero_bit_le
> +CFLAGS += $(APPEND_CFLAGS)
> +CFLAGS += $(CFLAGS_xeninclude)
> +CFLAGS += -I./generated/
> +
> +LDFLAGS += $(APPEND_LDFLAGS)
> +
> +vpath find-next-bit.c $(XEN_ROOT)/xen/lib/
> +# Ubuntu {16,18}.04 need single eval at the call site.

I'd rather see a comment about what's the macro is about rather that a
comment some Linux distribution. Our target is GNU Make 3.80, without
regards to a particular distribution. (Also I don't think it's useful to
point out that `eval` is needed for older version of Make, at least in
our project.)

> +$(eval $(call vpath-with-harness-deps,domid.c,$(XEN_ROOT)/xen/common/))
> +
> +test-domid: domid.o find-next-bit.o test-domid.o
> +	$(CC) $^ -o $@ $(LDFLAGS)
> +
> +-include $(DEPS_INCLUDE)
> diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-domid.c
> new file mode 100644
> index 000000000000..51a88a6a9550
> --- /dev/null
> +++ b/tools/tests/domid/test-domid.c
> @@ -0,0 +1,93 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Unit tests for domain ID allocator.
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#include "harness.h"
> +
> +#define verify(exp, fmt, args...) do { \
> +    if ( !(exp) ) \
> +        printf(fmt, ## args); \
> +    assert(exp); \

Relying on assert() for the test isn't wise. It's useful for developing
and debugging because it calls abort(), but they can easily be get rid of,
by simply building with -DNDEBUG. Could you maybe replace it with exit()
since you already check the condition?


Thanks,

-- 
Anthony PERARD


From xen-devel-bounces@lists.xenproject.org Mon Aug 25 13:54:40 2025
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Date: Mon, 25 Aug 2025 15:54:30 +0200
MIME-Version: 1.0
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From: Jan Beulich 
Subject: [PATCH v2] releases: use newer compression methods for tarballs
To: "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper , Julien Grall ,
 Stefano Stabellini ,
 Anthony PERARD ,
 Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
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Other projects have long switched to xz and/or lzip.

Tidy things some as well: With the removal of qemu from the tarball,
intermediately extracting the tarball again has become wasteful. Drop
that. Invoke compressors using asynchronous lists, to reduce overall
latency. Drop the -v option from the (previously implicit) gzip
invocation.

Signed-off-by: Jan Beulich 
---
v2: Don't expand intermediate uncompressed tarball. Don't check for
    commands' availablity. Don't request statistics. Use async lists.

--- a/docs/process/release-technician-checklist.txt
+++ b/docs/process/release-technician-checklist.txt
@@ -119,7 +119,7 @@ RELEASE TARBALL
        make src-tarball           # uses git-describe (best for RCs)
         # ^find some way to add git-cache-proxy to this (done in ~iwj/.gitconfig)
        mkdir /volatile/iwj/website-thing/xen.org/oss-xen/release/$v
-       mv dist/xen-$v.tar.gz /volatile/iwj/website-thing/xen.org/oss-xen/release/$v/.
+       mv dist/xen-$v.tar.[glx]z /volatile/iwj/website-thing/xen.org/oss-xen/release/$v/.
 
        # website-thing/xen.org is cvs -d mail.xenproject.org:/home/downloads-cvs/cvs-repos co xen.org
 	cd /volatile/iwj/website-thing/xen.org
@@ -139,9 +139,12 @@ RELEASE TARBALL
 	cvs add -kb oss-xen/release/$v/
 
         cd oss-xen/release/$v
-        gpg --digest-algo=SHA256 --detach-sign -u 'xen tree' xen-$v.tar.gz
-	cvs add -kb xen-$v.tar.gz
-        cvs add -kb xen-$v.tar.gz.sig
+        for t in xen-$v.tar.[glx]z
+        do
+            gpg --digest-algo=SHA256 --detach-sign -u 'xen tree' $t
+            cvs add -kb $t
+            cvs add -kb $t.sig
+        done
         cd ../../..
 
 	cvs ci -m $v
@@ -152,6 +155,10 @@ RELEASE TARBALL
 	# should show something like
 	#   U oss-xen/release/4.8.0-rc2/xen-4.8.0-rc2.tar.gz
 	#   U oss-xen/release/4.8.0-rc2/xen-4.8.0-rc2.tar.gz.sig
+	#   U oss-xen/release/4.8.0-rc2/xen-4.8.0-rc2.tar.lz
+	#   U oss-xen/release/4.8.0-rc2/xen-4.8.0-rc2.tar.lz.sig
+	#   U oss-xen/release/4.8.0-rc2/xen-4.8.0-rc2.tar.xz
+	#   U oss-xen/release/4.8.0-rc2/xen-4.8.0-rc2.tar.xz.sig
 
 After a .0 release, update XEN_EXTRAVERSION again (to .1-pre, see above).
 
--- a/docs/process/xen-release-management.pandoc
+++ b/docs/process/xen-release-management.pandoc
@@ -274,10 +274,10 @@ Xen X.Y rcZ is tagged. You can check tha
 https://xenbits.xen.org/git-http/xen.git X.Y.0-rcZ
 
 For your convenience there is also a tarball at:
-https://downloads.xenproject.org/release/xen/X.Y.0-rcZ/xen-X.Y.0-rcZ.tar.gz
+https://downloads.xenproject.org/release/xen/X.Y.0-rcZ/xen-X.Y.0-rcZ.tar.[glx]z
 
 And the signature is at:
-https://downloads.xenproject.org/release/xen/X.Y.0-rcZ/xen-X.Y.0-rcZ.tar.gz.sig
+https://downloads.xenproject.org/release/xen/X.Y.0-rcZ/xen-X.Y.0-rcZ.tar.[glx]z.sig
 
 Please send bug reports and test reports to xen-devel@lists.xenproject.org.
 When sending bug reports, please CC relevant maintainers and me
--- a/tools/misc/mktarball
+++ b/tools/misc/mktarball
@@ -5,14 +5,6 @@
 # Takes 2 arguments, the path to the dist directory and the version
 set -ex
 
-function git_archive_into {
-    mkdir -p "$2"
-
-    git --git-dir="$1"/.git \
-	archive --format=tar HEAD | \
-	tar Cxf "$2" -
-}
-
 if [[ -z "$1" || -z "$2" ]] ; then
   echo "usage: $0 path-to-XEN_ROOT xen-version"
   exit 1
@@ -21,14 +13,20 @@ fi
 xen_root="$1"
 desc="$2"
 
-tdir="$xen_root/dist/tmp.src-tarball"
+tdir="$xen_root/dist"
 
-rm -rf $tdir
+rm -f $tdir/xen-$desc.tar.[glx]z
 
 mkdir -p $tdir
 
-git_archive_into $xen_root $tdir/xen-$desc
+git --git-dir="$xen_root/.git" archive --format=tar HEAD --prefix=xen-$desc/ \
+    >"$tdir/xen-$desc.tar"
+
+gzip -9k "$tdir/xen-$desc.tar" &
+xz -9k "$tdir/xen-$desc.tar" &
+lzip -9k "$tdir/xen-$desc.tar" &
+wait
 
-GZIP=-9v tar cz -f $xen_root/dist/xen-$desc.tar.gz -C $tdir xen-$desc
+rm -f $tdir/xen-$desc.tar
 
-echo "Source tarball in $xen_root/dist/xen-$desc.tar.gz"
+echo "Source tarball in" $tdir/xen-$desc.tar.[glx]z


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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
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Thread-Topic: [PATCH v2 10/10] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
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On 25.08.2025 15:27, Dmytro Prokopchuk1 wrote:
> 
> 
> On 8/25/25 14:07, Jan Beulich wrote:
>> On 25.08.2025 12:58, Dmytro Prokopchuk1 wrote:
>>> On 8/25/25 13:30, Jan Beulich wrote:
>>>> On 25.08.2025 11:05, Dmytro Prokopchuk1 wrote:
>>>>> MISRA C Rule 17.7 states: "The value returned by a function having
>>>>> non-void return type shall be used."
>>>>>
>>>>> Deviate functions like 'memcpy()', 'memset()', 'memmove()', 'snprintf()',
>>>>> 'strlcpy()', 'strlcat()', as they return a value purely for convenience,
>>>>> their primary functionality (e.g., memory or string operations) remains
>>>>> unaffected, and their return values are generally non-critical and seldom
>>>>> relied upon. Update 'deviations.rst' file accordingly.
>>>>
>>>> How come snprintf() is among this set? Its return value isn't quite just
>>>> for convenience, imo.
>>>
>>> Yes, snprintf()'s return value isn't just for convenience. The deviation
>>> justification is primarily based on the fact that its return value is
>>> rarely used in the Xen source base. Most callers of snprintf() don't
>>> care about return value. So, snprintf() is in this list.
>>>
>>> Maybe separate wording is required for the snprintf() ?
>>
>> Minimally. Personally I don't think it should be deviated globally.
> 
> There are approximately 230 instances of snprintf() being used without 
> checking its return value (across ARM and x86) in around 20 different 
> source files. Deviation each of them could be complicated.

My grep yields somewhere between 50 and 60 hits in xen/, among them about 15
in xen/tools/kconfig/, which I expect we can ignore. I also didn't mean to
suggest to deviate them all individually. Some may actually want to use the
return value, and I wouldn't be surprised if this ended up fixing a bug or
two.

Jan


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From: "Yann Sionneau" 
Subject: =?utf-8?Q?Re:=20[PATCH=20v2]=20xen/x86:=20fix=20xen.efi=20boot=20crash=20from=20some=20bootloaders?=
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On 8/4/25 11:34, Jan Beulich wrote:
> On 24.07.2025 16:07, Yann Sionneau wrote:
>> xen.efi PE does not boot when loaded from shim or some patched
>> downstream grub2.
>>
>> What happens is the bootloader would honour the MEM_DISCARDABLE
>> flag of the .reloc section meaning it would not load its content
>> into memory.
>>
>> But Xen is parsing the .reloc section content twice at boot:
>> * https://elixir.bootlin.com/xen/v4.20.1/source/xen/common/efi/boot.c#L1362
>> * https://elixir.bootlin.com/xen/v4.20.1/source/xen/arch/x86/efi/efi-boot.h#L237
>>
>> Therefore it would crash with the following message:
>> "Unsupported relocation type" as reported there:
>>
>> * https://github.com/QubesOS/qubes-issues/issues/8206#issuecomment-2619048838
>> * https://lore.kernel.org/xen-devel/7e039262-1f54-46e1-8f70-ac3f03607d5a@suse.com/T/#me122b9e6c27cd98db917da2c9f67e74a2c6ad7a5
>>
>> This commit adds a small C host tool named keeprelocs
>> that is called after xen.efi is produced by the build system
>> in order to remove this bit from its .reloc section header.
>>
>> Signed-off-by: Yann Sionneau 
> 
> So I found a way to deal with this at the linker side, without any new command
> line options. Behavior is solely driven by the attributes of any incoming .reloc
> sections (of which there would be none by default, retaining original behavior).
> The important patch is [1], but at least the first patch of the series [2] would
> in most cases also be wanted/needed (patch 04 is obviously a mechanical prereq
> for the main patch). Need for other of the prereqs there depends on the scope
> and purpose of one's binutils build(s).
> 
> Jan
> 
> [1] https://sourceware.org/pipermail/binutils/2025-August/143153.html
> [2] https://sourceware.org/pipermail/binutils/2025-August/143141.html

That sounds great!
It's clearly better to fix the issue by changing/improving binutils.
Let's drop my patch in Xen if this gets accepted in binutils!
It would be nice if you could keep us posted in xen-devel of the 
status/progress of the binutils patches.

By the number of patches needed for binutils it seems you opened a can 
of worms/pandora box with this issue ^^

Also, in patch 12/17, you state that the logic would be that if .reloc 
is generated partly by the code itself instead of solely by the linker 
this means we want to use the section at runtime.
While I kind of understand this idea, it also feels a bit as a hack, 
doesn't it?
One could argue that even if .reloc is just generated by the linker, the
program could still want to access it at runtime.
I've looked at Xen code to see if it does put something in .reloc itself 
and it seems so: 
https://elixir.bootlin.com/xen/v4.20.1/source/xen/arch/x86/efi/relocs-dummy.S
The "code puts data in .reloc section" would just serve as a "hint" for 
the linker if I understand your patch well, just as well as a 
`--keep-reloc` command line option would.

Anyway, I won't comment much further on the binutils patchset since I'm 
not well versed in linker black magic.

Thanks for the patchset!

Yann

-- 


Yann Sionneau | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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On 19.08.2025 01:51, Stefano Stabellini wrote:
> On Mon, 18 Aug 2025, Jan Beulich wrote:
>> On 18.08.2025 15:28, Oleksii Kurochko wrote:
>>> On 8/18/25 10:31 AM, Jan Beulich wrote:
>>>> On 15.08.2025 12:27, Penny Zheng wrote:
>>>>> In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and
>>>>> HVM=y results in hvm.c being built, but domctl.c not being built, which leaves
>>>>> a few functions, like domctl_lock_acquire/release() undefined, causing linking
>>>>> to fail.
>>>>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile
>>>>> /hypercall-defs section, with this adjustment, we also need to release
>>>>> redundant vnuma_destroy() stub definition from PV_SHIM_EXCLUSIVE guardian,
>>>>> to not break compilation
>>>>> Above change will leave dead code in the shim binary temporarily and will be
>>>>> fixed with the introduction of domctl-op wrapping.
>>>> Well, "temporarily" is now getting interesting. While v1 of "Introduce
>>>> CONFIG_DOMCTL" was submitted in time to still be eligible for taking into
>>>> 4.21, that - as indicated elsewhere - is moving us further in an unwanted
>>>> direction.
>>>
>>> Do you mean that specifically this patch or the whole patch series is moving us
>>> in unwanted direction? (1)
>>
>> That series. We said we don't want individual CONFIG_SYSCTL, CONFIG_DOMCTL, etc.
>> Instead a single umbrella option wants introducing. Which means there series
>> doesn't need re-doing from scratch, but it may end up being a significant re-
>> work, especially considering that CONFIG_SYSCTL is already in the codebase and
>> hence now also needs replacing.
> 
> I would not characterize this series as "moving us in an unwanted
> direction". Yes, it introduces a separate CONFIG_DOMCTL, which we
> agreed we do not want. However, simplifying it to reuse a single
> CONFIG is a minor improvement that can be addressed in v2. The main
> challenge in this series is adding the #ifdef in the appropriate
> places, and using a single CONFIG for domctl and sysctl would
> actually help.

Well, when are we going to see a v2 then which does this? Of the three
options I mentioned in the earlier reply, Oleksii favored the revert
path, leaving open the get-everything-in one. For the latter, however,
we need to see relatively constant progress now, or else time will run
out. Whether to commit the patch here really depends on what route we
settle on for 4.21.

Jan


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Subject: Re: [PATCH v2] xen/x86: fix xen.efi boot crash from some bootloaders
To: Yann Sionneau 
Cc: Andrew Cooper ,
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 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
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On 25.08.2025 16:17, Yann Sionneau wrote:
> On 8/4/25 11:34, Jan Beulich wrote:
>> On 24.07.2025 16:07, Yann Sionneau wrote:
>>> xen.efi PE does not boot when loaded from shim or some patched
>>> downstream grub2.
>>>
>>> What happens is the bootloader would honour the MEM_DISCARDABLE
>>> flag of the .reloc section meaning it would not load its content
>>> into memory.
>>>
>>> But Xen is parsing the .reloc section content twice at boot:
>>> * https://elixir.bootlin.com/xen/v4.20.1/source/xen/common/efi/boot.c#L1362
>>> * https://elixir.bootlin.com/xen/v4.20.1/source/xen/arch/x86/efi/efi-boot.h#L237
>>>
>>> Therefore it would crash with the following message:
>>> "Unsupported relocation type" as reported there:
>>>
>>> * https://github.com/QubesOS/qubes-issues/issues/8206#issuecomment-2619048838
>>> * https://lore.kernel.org/xen-devel/7e039262-1f54-46e1-8f70-ac3f03607d5a@suse.com/T/#me122b9e6c27cd98db917da2c9f67e74a2c6ad7a5
>>>
>>> This commit adds a small C host tool named keeprelocs
>>> that is called after xen.efi is produced by the build system
>>> in order to remove this bit from its .reloc section header.
>>>
>>> Signed-off-by: Yann Sionneau 
>>
>> So I found a way to deal with this at the linker side, without any new command
>> line options. Behavior is solely driven by the attributes of any incoming .reloc
>> sections (of which there would be none by default, retaining original behavior).
>> The important patch is [1], but at least the first patch of the series [2] would
>> in most cases also be wanted/needed (patch 04 is obviously a mechanical prereq
>> for the main patch). Need for other of the prereqs there depends on the scope
>> and purpose of one's binutils build(s).
>>
>> [1] https://sourceware.org/pipermail/binutils/2025-August/143153.html
>> [2] https://sourceware.org/pipermail/binutils/2025-August/143141.html
> 
> That sounds great!
> It's clearly better to fix the issue by changing/improving binutils.
> Let's drop my patch in Xen if this gets accepted in binutils!

Luckily I'm in a position where I don't need "acceptance", but merely
"absence of objections". The sole reason for the present delay is with
a colliding MIPS patch, which I'd rather see go in first.

> It would be nice if you could keep us posted in xen-devel of the 
> status/progress of the binutils patches.

I'll try to remember.

> By the number of patches needed for binutils it seems you opened a can 
> of worms/pandora box with this issue ^^

Well, that's been only one of the tinier cans.

> Also, in patch 12/17, you state that the logic would be that if .reloc 
> is generated partly by the code itself instead of solely by the linker 
> this means we want to use the section at runtime.
> While I kind of understand this idea, it also feels a bit as a hack, 
> doesn't it?

Yes and no. Assigning purpose to sections merely from their names is
already a hack. Yet since we need to live with that concept on PE/COFF
(and even ELF is quite far from being free of such), making this small
extra distinction feels quite acceptable to me.

> One could argue that even if .reloc is just generated by the linker, the
> program could still want to access it at runtime.

Not really, no. Ordinary programs hardly have a need to access their
own .reloc. And if so, having a simple, command-line-option-less way
to distinguish both intentions is probably the best we can have for
both worlds.

> I've looked at Xen code to see if it does put something in .reloc itself 
> and it seems so: 
> https://elixir.bootlin.com/xen/v4.20.1/source/xen/arch/x86/efi/relocs-dummy.S
> The "code puts data in .reloc section" would just serve as a "hint" for 
> the linker if I understand your patch well, just as well as a 
> `--keep-reloc` command line option would.

And something similar would then be needed for the other two linking
steps, just that there would be no actual data in that .reloc section
"contribution".

Jan


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Subject: Re: [PATCH v7 03/13] tools: fix help info for "xenpm
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To: Penny Zheng 
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On 22.08.2025 12:52, Penny Zheng wrote:
> Change "balance" to "ondemand" in help info for "xenpm set-cpufreq-cppc"
> 
> Fixes: 81ce87fc5e36 (xen/cpufreq: rename cppc preset name to "XEN_SYSCTL_CPPC_SET_PRESET_ONDEMAND")
> Signed-off-by: Penny Zheng 

Acked-by: Jan Beulich 



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Subject: Re: [PATCH v7 04/13] xen/cpufreq: add missing default: case for x86
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On 22.08.2025 12:52, Penny Zheng wrote:
> Since we are missing default case for x86 vendor, there is possibility (i.e.
> new vendor introduced) that we will return successfully while missing the
> whole cpufreq driver initialization process.
> Move "ret = -ENOENTRY" forward to cover default case for x86 vendor, and
> add error log

Requested-by: Jan Beulich 
(or Suggested-by: if you like that better)

> Signed-off-by: Penny Zheng 

Reviewed-by: Jan Beulich 

Jan


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Date: Mon, 25 Aug 2025 16:45:07 +0200
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Subject: Re: [PATCH v7 05/13] xen/cpufreq: refactor cmdline "cpufreq=xxx"
To: Penny Zheng 
Cc: ray.huang@amd.com, xen-devel@lists.xenproject.org
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-6-Penny.Zheng@amd.com>
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On 22.08.2025 12:52, Penny Zheng wrote:
> A helper function handle_cpufreq_cmdline() is introduced to tidy different
> handling pathes.
> We also add a new helper cpufreq_opts_contain() to ignore redundant setting,
> like "cpufreq=hwp;hwp;xen"
> As only slot 0 of cpufreq_xen_opts[] needs explicit initializing with
> non-zero CPUFREQ_xen, dropping full array initializer could avoid touching
> initializer every time it grows
> 
> Signed-off-by: Penny Zheng 

Reviewed-by: Jan Beulich 



From xen-devel-bounces@lists.xenproject.org Mon Aug 25 14:50:14 2025
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Date: Mon, 25 Aug 2025 16:49:58 +0200
From: Anthony PERARD 
To: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
	michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org,
	dmukhin@ford.com
Subject: Re: [PATCH v4 6/8] tools/xl: enable NS16550-compatible UART emulator
 for HVM (x86)
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-7-dmukhin@ford.com>
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In-Reply-To: <20250731192130.3948419-7-dmukhin@ford.com>

On Thu, Jul 31, 2025 at 07:22:12PM +0000, dmkhn@proton.me wrote:
> diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
> index 5362fb0e9a6f..e1d012274eaf 100644
> --- a/docs/man/xl.cfg.5.pod.in
> +++ b/docs/man/xl.cfg.5.pod.in
> @@ -3032,14 +3032,17 @@ the domain was created.
>  This requires hardware compatibility with the requested version, either
>  natively or via hardware backwards compatibility support.
>  
> -=item B
> +=item B

This syntax here would inditace that `vuart` takes a list of items. You
could write instead:

    vuart="UART"

which seems more in line with the rest of the man page. Then you can add
some thing like "with UART been one of "sbsa_uart" or "ns16550". It's
possible to also have a sublist, like the `tee` option have.


>  To enable vuart console, user must specify the following option in the
> -VM config file:
> +VM config file, e.g:
>  
> +```

This file isn't in markdown, it's in perlpod.

>  vuart = "sbsa_uart"
> +```
>  
> -Currently, only the "sbsa_uart" model is supported for ARM.
> +Currently, "sbsa_uart" (ARM) and "ns16550" (x86) are the only supported
> +UART models.
>  
>  =back
>  
> diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c
> index 4a19a8d22bdf..f4721b24763c 100644
> --- a/tools/libs/light/libxl_arm.c
> +++ b/tools/libs/light/libxl_arm.c
> @@ -92,14 +92,26 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
>      uint32_t virtio_mmio_irq = GUEST_VIRTIO_MMIO_SPI_FIRST;
>      int rc;
>  
> -    /*
> -     * If pl011 vuart is enabled then increment the nr_spis to allow allocation
> -     * of SPI VIRQ for pl011.
> -     */
> -    if (d_config->b_info.arch_arm.vuart == LIBXL_VUART_TYPE_SBSA_UART) {
> +    switch ( d_config->b_info.vuart )
> +    {
> +    case LIBXL_VUART_TYPE_SBSA_UART:
> +        /*
> +         * If pl011 vuart is enabled then increment the nr_spis to allow
> +         * allocation of SPI VIRQ for pl011.
> +         */
>          nr_spis += (GUEST_VPL011_SPI - 32) + 1;
>          vuart_irq = GUEST_VPL011_SPI;
>          vuart_enabled = true;
> +        break;
> +
> +    case LIBXL_VUART_TYPE_NS16550:
> +        LOG(ERROR, "unsupported UART emulator %d\n", d_config->b_info.vuart);

This seems too late in libxl.  I think checking if the config value is
correct could be done in one of the *_setdefault() like many other
config check are done. There's
libxl__arch_domain_build_info_setdefault() that could be used.

> +        abort();
> +        break;
> +
> +    case LIBXL_VUART_TYPE_UNKNOWN:
> +    default:
> +        break;
>      }
>  
>      for (i = 0; i < d_config->num_disks; i++) {
> diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl
> index fe251649f346..fd60c2b26764 100644
> --- a/tools/libs/light/libxl_types.idl
> +++ b/tools/libs/light/libxl_types.idl
> @@ -276,6 +276,7 @@ libxl_checkpointed_stream = Enumeration("checkpointed_stream", [
>  libxl_vuart_type = Enumeration("vuart_type", [
>      (0, "unknown"),
>      (1, "sbsa_uart"),
> +    (2, "ns16550"),
>      ])
>  
>  libxl_vkb_backend = Enumeration("vkb_backend", [
> @@ -722,7 +723,6 @@ libxl_domain_build_info = Struct("domain_build_info",[
>  
>  
>      ("arch_arm", Struct(None, [("gic_version", libxl_gic_version),
> -                               ("vuart", libxl_vuart_type),

arch_arm.vuart is part of libxl's API, it can't be removed. There's some
explanation about "libxl API compatibility" at the top of "libxl.h".
But for this change, you could add `vuart` to `arch_x86`, or if you want
to add `vuart` at the root like you did, you'll need to check that both
`arch_arm.vuart` and `vuart` aren't set at the same time, and have one
of the *_setdefault() function do the work of migrating the option.

You'll need also a LIBXL_HAVE_* macro in libxl.h, probably named
LIBXL_HAVE_VUART_NS16550.

>                                 ("sve_vl", libxl_sve_type),
>                                 ("nr_spis", uint32, {'init_val': 'LIBXL_NR_SPIS_DEFAULT'}),
>                                ])),
> @@ -739,6 +739,7 @@ libxl_domain_build_info = Struct("domain_build_info",[
>  
>      ("vpmu", libxl_defbool),
>      ("trap_unmapped_accesses", libxl_defbool),
> +    ("vuart", libxl_vuart_type),
>  
>      ], dir=DIR_IN,
>         copy_deprecated_fn="libxl__domain_build_info_copy_deprecated",
> diff --git a/tools/libs/light/libxl_x86.c b/tools/libs/light/libxl_x86.c
> index 60d4e8661c93..0f039ca65a88 100644
> --- a/tools/libs/light/libxl_x86.c
> +++ b/tools/libs/light/libxl_x86.c
> @@ -2,6 +2,45 @@
>  #include "libxl_arch.h"
>  #include 
>  
> +static void libxl__arch_domain_vuart_assert(
> +    libxl__gc *gc,
> +    libxl_domain_config *d_config,
> +    struct xen_domctl_createdomain *config)
> +{
> +    LOG(ERROR, "unsupported UART emulator %d\n", d_config->b_info.vuart);
> +    abort();

The name of the function is wrong. It doens't assert anything, and just
abort...
I don't think this function is useful.

Also, don't abort() for configuration error, you need to return an error
instead.

> +}
> +
> +static void libxl__arch_domain_vuart_unsupported(
> +    libxl__gc *gc,
> +    libxl_domain_config *d_config,
> +    struct xen_domctl_createdomain *config)
> +{
> +    if ( d_config->b_info.vuart != LIBXL_VUART_TYPE_UNKNOWN )
> +        libxl__arch_domain_vuart_assert(gc, d_config, config);

This function have also a bad name, it doesn't check if a uart is
unsupported.

> +}
> +
> +static void libxl__arch_domain_vuart_enable(
> +    libxl__gc *gc,
> +    libxl_domain_config *d_config,
> +    struct xen_domctl_createdomain *config)
> +{
> +    switch ( d_config->b_info.vuart )
> +    {
> +    case LIBXL_VUART_TYPE_SBSA_UART:
> +        libxl__arch_domain_vuart_assert(gc, d_config, config);
> +        break;
> +
> +    case LIBXL_VUART_TYPE_NS16550:
> +        config->arch.emulation_flags |= XEN_X86_EMU_NS16550;
> +        break;
> +
> +    case LIBXL_VUART_TYPE_UNKNOWN:
> +    default:
> +        break;
> +    }
> +}
> +
>  int libxl__arch_domain_prepare_config(libxl__gc *gc,
>                                        libxl_domain_config *d_config,
>                                        struct xen_domctl_createdomain *config)
> @@ -9,14 +48,17 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
>      switch(d_config->c_info.type) {
>      case LIBXL_DOMAIN_TYPE_HVM:
>          config->arch.emulation_flags = (XEN_X86_EMU_ALL & ~XEN_X86_EMU_VPCI);
> +        libxl__arch_domain_vuart_enable(gc, d_config, config);
>          if (!libxl_defbool_val(d_config->b_info.u.hvm.pirq))
>              config->arch.emulation_flags &= ~XEN_X86_EMU_USE_PIRQ;
>          break;
>      case LIBXL_DOMAIN_TYPE_PVH:
>          config->arch.emulation_flags = XEN_X86_EMU_LAPIC;
> +        libxl__arch_domain_vuart_unsupported(gc, d_config, config);
>          break;
>      case LIBXL_DOMAIN_TYPE_PV:
>          config->arch.emulation_flags = 0;
> +        libxl__arch_domain_vuart_unsupported(gc, d_config, config);
>          break;
>      default:
>          abort();

Thanks,

-- 
Anthony PERARD


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Date: Mon, 25 Aug 2025 17:01:55 +0200
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Subject: Re: [PATCH v7 06/13] xen/cpufreq: introduce new sub-hypercall to
 propagate CPPC data
To: Penny Zheng 
Cc: ray.huang@amd.com, Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-7-Penny.Zheng@amd.com>
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From: Jan Beulich 
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On 22.08.2025 12:52, Penny Zheng wrote:
> --- a/xen/arch/x86/x86_64/cpufreq.c
> +++ b/xen/arch/x86/x86_64/cpufreq.c
> @@ -54,3 +54,22 @@ int compat_set_px_pminfo(uint32_t acpi_id,
>  
>      return set_px_pminfo(acpi_id, xen_perf);
>  }
> +
> +int compat_set_cppc_pminfo(unsigned int acpi_id,
> +                           const struct compat_processor_cppc *cppc_data)
> +
> +{
> +    struct xen_processor_cppc *xen_cppc;
> +    unsigned long xlat_page_current;
> +
> +    xlat_malloc_init(xlat_page_current);
> +
> +    xen_cppc = xlat_malloc_array(xlat_page_current,
> +                                 struct xen_processor_cppc, 1);
> +    if ( unlikely(xen_cppc == NULL) )
> +        return -EFAULT;

I think we want to avoid repeating the earlier mistake with using a wrong
error code. It's ENOMEM or ENOSPC or some such.

> --- a/xen/drivers/acpi/pm-op.c
> +++ b/xen/drivers/acpi/pm-op.c
> @@ -91,7 +91,9 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
>      pmpt = processor_pminfo[op->cpuid];
>      policy = per_cpu(cpufreq_cpu_policy, op->cpuid);
>  
> -    if ( !pmpt || !pmpt->perf.states ||
> +    if ( !pmpt ||
> +         ((pmpt->init & XEN_PX_INIT) && !pmpt->perf.states) ||
> +         ((pmpt->init & XEN_CPPC_INIT) && pmpt->perf.state_count) ||

I fear I don't understand this: In the PX case we check whether necessary
data is lacking. In the CPPC case you check that some data was provided
that we don't want to use? Why not similarly check that data we need was
provided?

> @@ -693,6 +699,120 @@ int acpi_set_pdc_bits(unsigned int acpi_id, XEN_GUEST_HANDLE(uint32) pdc)
>      return ret;
>  }
>  
> +static void print_CPPC(const struct xen_processor_cppc *cppc_data)
> +{
> +    printk("\t_CPC: highest_perf=%u, lowest_perf=%u, "
> +           "nominal_perf=%u, lowest_nonlinear_perf=%u, "
> +           "nominal_mhz=%uMHz, lowest_mhz=%uMHz\n",
> +           cppc_data->cpc.highest_perf, cppc_data->cpc.lowest_perf,
> +           cppc_data->cpc.nominal_perf, cppc_data->cpc.lowest_nonlinear_perf,
> +           cppc_data->cpc.nominal_mhz, cppc_data->cpc.lowest_mhz);
> +}
> +
> +int set_cppc_pminfo(unsigned int acpi_id,
> +                    const struct xen_processor_cppc *cppc_data)
> +{
> +    int ret = 0, cpuid;
> +    struct processor_pminfo *pm_info;
> +
> +    cpuid = get_cpu_id(acpi_id);
> +    if ( cpuid < 0 )
> +    {
> +        ret = -EINVAL;
> +        goto out;
> +    }
> +
> +    if ( cppc_data->pad[0] || cppc_data->pad[1] || cppc_data->pad[2] )
> +    {
> +        ret = -EINVAL;
> +        goto out;
> +    }
> +
> +    if ( cpufreq_verbose )
> +        printk("Set CPU%d (ACPI ID %u) CPPC state info:\n",
> +               cpuid, acpi_id);
> +
> +    pm_info = processor_pminfo[cpuid];
> +    if ( !pm_info )
> +    {
> +        pm_info = xvzalloc(struct processor_pminfo);
> +        if ( !pm_info )
> +        {
> +            ret = -ENOMEM;
> +            goto out;
> +        }
> +        processor_pminfo[cpuid] = pm_info;
> +    }
> +    pm_info->acpi_id = acpi_id;
> +    pm_info->id = cpuid;
> +    pm_info->cppc_data = *cppc_data;
> +
> +    if ( (cppc_data->flags & XEN_CPPC_PSD) &&
> +         !check_psd_pminfo(cppc_data->shared_type) )
> +    {
> +            ret = -EINVAL;
> +            goto out;

Indentation.

Jan


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To: Anthony PERARD , dmkhn@proton.me
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On 25.08.2025 16:49, Anthony PERARD wrote:
> On Thu, Jul 31, 2025 at 07:22:12PM +0000, dmkhn@proton.me wrote:
>> diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
>> index 5362fb0e9a6f..e1d012274eaf 100644
>> --- a/docs/man/xl.cfg.5.pod.in
>> +++ b/docs/man/xl.cfg.5.pod.in
>> @@ -3032,14 +3032,17 @@ the domain was created.
>>  This requires hardware compatibility with the requested version, either
>>  natively or via hardware backwards compatibility support.
>>  
>> -=item B
>> +=item B
> 
> This syntax here would inditace that `vuart` takes a list of items. You
> could write instead:
> 
>     vuart="UART"
> 
> which seems more in line with the rest of the man page. Then you can add
> some thing like "with UART been one of "sbsa_uart" or "ns16550". It's
> possible to also have a sublist, like the `tee` option have.

But shouldn't the syntax already now allow for multiple items? Possibly
even multiple ones of the same kind?

Jan


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Subject: Re: [PATCH v7 07/13] xen/cpufreq: introduce "cpufreq=amd-cppc" xen
 cmdline and amd-cppc driver
To: Penny Zheng 
Cc: ray.huang@amd.com, Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-8-Penny.Zheng@amd.com>
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On 22.08.2025 12:52, Penny Zheng wrote:
> --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
> +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
> @@ -131,12 +131,13 @@ static int __init cf_check cpufreq_driver_init(void)
>  
>      if ( cpufreq_controller == FREQCTL_xen )
>      {
> +        unsigned int i;
>          ret = -ENOENT;

Blank line between declaration(s) and statement(s) please.

Then:
Acked-by: Jan Beulich 

Jan


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Date: Mon, 25 Aug 2025 17:13:14 +0200
From: Anthony PERARD 
To: Jan Beulich 
Cc: dmkhn@proton.me, xen-devel@lists.xenproject.org,
	andrew.cooper3@citrix.com, anthony.perard@vates.tech,
	julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com,
	sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 6/8] tools/xl: enable NS16550-compatible UART emulator
 for HVM (x86)
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-7-dmukhin@ford.com>
 
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On Mon, Aug 25, 2025 at 05:03:40PM +0200, Jan Beulich wrote:
> On 25.08.2025 16:49, Anthony PERARD wrote:
> > On Thu, Jul 31, 2025 at 07:22:12PM +0000, dmkhn@proton.me wrote:
> >> -=item B
> >> +=item B
> > 
> > This syntax here would inditace that `vuart` takes a list of items. You
> > could write instead:
> > 
> >     vuart="UART"
> > 
> > which seems more in line with the rest of the man page. Then you can add
> > some thing like "with UART been one of "sbsa_uart" or "ns16550". It's
> > possible to also have a sublist, like the `tee` option have.
> 
> But shouldn't the syntax already now allow for multiple items? Possibly
> even multiple ones of the same kind?

How does `vuart="uart"` allow for multiple items?

-- 
Anthony PERARD


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Date: Mon, 25 Aug 2025 17:14:35 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v7 08/13] xen/cpufreq: implement amd-cppc driver for CPPC
 in passive mode
To: Penny Zheng 
Cc: ray.huang@amd.com, Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-9-Penny.Zheng@amd.com>
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From: Jan Beulich 
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On 22.08.2025 12:52, Penny Zheng wrote:
> @@ -50,10 +141,335 @@ int __init amd_cppc_cmdline_parse(const char *s, const char *e)
>      return 0;
>  }
>  
> +/*
> + * If CPPC lowest_freq and nominal_freq registers are exposed then we can
> + * use them to convert perf to freq and vice versa. The conversion is
> + * extrapolated as an linear function passing by the 2 points:
> + *  - (Low perf, Low freq)
> + *  - (Nominal perf, Nominal freq)
> + * Parameter freq is always in kHz.
> + */
> +static int amd_cppc_khz_to_perf(const struct amd_cppc_drv_data *data,
> +                                unsigned int freq, uint8_t *perf)
> +{
> +    const struct xen_processor_cppc *cppc_data = data->cppc_data;
> +    unsigned int mul, div;
> +    int offset = 0, res;
> +
> +    if ( cppc_data->cpc.lowest_mhz &&
> +         data->caps.nominal_perf > data->caps.lowest_perf &&
> +         cppc_data->cpc.nominal_mhz > cppc_data->cpc.lowest_mhz )
> +    {
> +        mul = data->caps.nominal_perf - data->caps.lowest_perf;
> +        div = cppc_data->cpc.nominal_mhz - cppc_data->cpc.lowest_mhz;
> +
> +        /*
> +         * We don't need to convert to kHz for computing offset and can
> +         * directly use nominal_mhz and lowest_mhz as the division
> +         * will remove the frequency unit.
> +         */
> +        offset = data->caps.nominal_perf -
> +                 (mul * cppc_data->cpc.nominal_mhz) / div;
> +    }
> +    else
> +    {
> +        /* Read Processor Max Speed(MHz) as anchor point */
> +        mul = data->caps.highest_perf;
> +        div = this_cpu(pxfreq_mhz);
> +        if ( !div )
> +            return -EOPNOTSUPP;
> +    }
> +
> +    res = offset + (mul * freq) / (div * 1000);
> +    if ( res > UINT8_MAX )
> +    {
> +        printk_once(XENLOG_WARNING
> +                    "Perf value exceeds maximum value 255: %d\n", res);
> +        *perf = UINT8_MAX;
> +        return 0;
> +    }
> +    if ( res <= 0 )
> +    {
> +        printk_once(XENLOG_WARNING
> +                    "Perf value smaller than minimum value 0: %d\n", res);

The message text doesn't fit the if() condition anymore. Perhaps simply
omit the "0" from the text? Then:
Acked-by: Jan Beulich 

Jan


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        Mon, 25 Aug 2025 08:15:50 -0700 (PDT)
From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: Roger Pau Monne ,
	Jan Beulich ,
	Andrew Cooper ,
	=?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= 
Subject: [PATCH] x86/suspend: unconditionally raise a timer softirq on resume
Date: Mon, 25 Aug 2025 17:15:15 +0200
Message-ID: <20250825151515.39177-1-roger.pau@citrix.com>
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The current code to restore the timer state on resume is incomplete.  While
the local APIC Initial Count Register is saved and restored across
suspension (even if possibly no longer accurate since it's not adjusted to
account for the time spent in suspension), the TSC deadline MSR is not
saved and restored, hence hosts using the TSC deadline timer will likely
get stuck when resuming from suspension.

The lack of restoring of the TSC deadline MSR was mitigated by the raising
of a timer softirq in mwait_idle_with_hints() if the timer had expired,
previous to commit 3faf0866a33070b926ab78e6298290403f85e76c, which removed
that logic.

This patch fixes the usage of the TSC deadline timer with suspension, by
unconditionally raising a timer softirq on resume, that will take care of
rearming the hardware timer.  Given that a timer softirq will be
unconditionally risen, there's no need to save and restore the APIC Initial
Count Register anymore either.

Note that secondary processors don't need this special treatment when
resuming, since they are offlined before suspension and brought back up
during resume, the first timer that gets setup will trigger a timer softirq
unconditionally, for example from sched_migrate_timers() that gets called
for each secondary processor.

Reported-by: Marek Marczykowski-Górecki 
Fixes: fd1291a826e1 ('X86: Prefer TSC-deadline timer in Xen')
Signed-off-by: Roger Pau Monné 
---
 xen/arch/x86/acpi/power.c | 2 ++
 xen/arch/x86/apic.c       | 3 ---
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c
index 2ac162c997fe..27d672ad5dbb 100644
--- a/xen/arch/x86/acpi/power.c
+++ b/xen/arch/x86/acpi/power.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -310,6 +311,7 @@ static int enter_state(u32 state)
     thaw_domains();
     system_state = SYS_STATE_active;
     spin_unlock(&pm_lock);
+    raise_softirq(TIMER_SOFTIRQ);
     return error;
 }
 
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index cac5ba39e615..e3a2b84f1aae 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -65,7 +65,6 @@ static struct {
     unsigned int apic_lvt0;
     unsigned int apic_lvt1;
     unsigned int apic_lvterr;
-    unsigned int apic_tmict;
     unsigned int apic_tdcr;
     unsigned int apic_thmr;
 } apic_pm_state;
@@ -658,7 +657,6 @@ int lapic_suspend(void)
     apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
     apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
     apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
-    apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
     apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
     if (maxlvt >= 5)
         apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
@@ -718,7 +716,6 @@ int lapic_resume(void)
         apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
     apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
     apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
-    apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
     apic_write(APIC_ESR, 0);
     apic_read(APIC_ESR);
     apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
-- 
2.49.0



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Subject: Re: [PATCH v7 09/13] xen/cpufreq: implement amd-cppc-epp driver for
 CPPC in active mode
To: Penny Zheng 
Cc: ray.huang@amd.com, Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-10-Penny.Zheng@amd.com>
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On 22.08.2025 12:52, Penny Zheng wrote:
> @@ -270,6 +288,10 @@ static void amd_cppc_write_request(unsigned int cpu, uint8_t min_perf,
>  
>      data->req.min_perf = min_perf;
>      data->req.max_perf = max_perf;
> +#ifndef NDEBUG
> +    if ( opt_active_mode )
> +        ASSERT(!des_perf);
> +#endif

Simply

    ASSERT(!opt_active_mode || !des_perf);

(without any #ifndef)? Then once again:
Acked-by: Jan Beulich 

Jan


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Date: Mon, 25 Aug 2025 17:23:58 +0200
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Subject: Re: [PATCH v7 10/13] xen/cpufreq: get performance policy from
 governor set via xenpm
To: Penny Zheng 
Cc: ray.huang@amd.com, xen-devel@lists.xenproject.org
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-11-Penny.Zheng@amd.com>
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On 22.08.2025 12:52, Penny Zheng wrote:
> Even if Xen governor is not used in amd-cppc active mode, we could
> somehow deduce which performance policy (CPUFREQ_POLICY_xxx) user wants to
> apply through which governor they choose, such as:
> If user chooses performance governor, they want maximum performance, then
> the policy shall be CPUFREQ_POLICY_PERFORMANCE
> If user chooses powersave governor, they want the least power consumption,
> then the policy shall be CPUFREQ_POLICY_POWERSAVE
> Function cpufreq_policy_from_governor() is responsible for above transition,
> and it shall be also effective when users setting new governor through xenpm.
> 
> userspace are forbidden choices, and if users specify such options,

Odd use of plural here, when only one bad variant is named.

> --- a/xen/drivers/acpi/pm-op.c
> +++ b/xen/drivers/acpi/pm-op.c
> @@ -206,6 +206,14 @@ static int set_cpufreq_gov(struct xen_sysctl_pm_op *op)
>      if ( new_policy.governor == NULL )
>          return -EINVAL;
>  
> +    new_policy.policy = cpufreq_policy_from_governor(new_policy.governor);
> +    if ( new_policy.policy == CPUFREQ_POLICY_UNKNOWN )
> +    {
> +        printk("Failed to get performance policy from %s, Try \"xenpm set-cpufreq-cppc\"\n",
> +               new_policy.governor->name);
> +        return -EINVAL;
> +    }

Don't you also need to check for CPPC mode, or else you reject "userspace" for
other drivers as well?

Jan


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Date: Mon, 25 Aug 2025 17:25:36 +0200
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Subject: Re: [PATCH] x86/suspend: unconditionally raise a timer softirq on
 resume
To: Roger Pau Monne 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 , xen-devel@lists.xenproject.org
References: <20250825151515.39177-1-roger.pau@citrix.com>
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From: Jan Beulich 
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On 25.08.2025 17:15, Roger Pau Monne wrote:
> The current code to restore the timer state on resume is incomplete.  While
> the local APIC Initial Count Register is saved and restored across
> suspension (even if possibly no longer accurate since it's not adjusted to
> account for the time spent in suspension), the TSC deadline MSR is not
> saved and restored, hence hosts using the TSC deadline timer will likely
> get stuck when resuming from suspension.
> 
> The lack of restoring of the TSC deadline MSR was mitigated by the raising
> of a timer softirq in mwait_idle_with_hints() if the timer had expired,
> previous to commit 3faf0866a33070b926ab78e6298290403f85e76c, which removed
> that logic.
> 
> This patch fixes the usage of the TSC deadline timer with suspension, by
> unconditionally raising a timer softirq on resume, that will take care of
> rearming the hardware timer.  Given that a timer softirq will be
> unconditionally risen, there's no need to save and restore the APIC Initial
> Count Register anymore either.
> 
> Note that secondary processors don't need this special treatment when
> resuming, since they are offlined before suspension and brought back up
> during resume, the first timer that gets setup will trigger a timer softirq
> unconditionally, for example from sched_migrate_timers() that gets called
> for each secondary processor.
> 
> Reported-by: Marek Marczykowski-Górecki 
> Fixes: fd1291a826e1 ('X86: Prefer TSC-deadline timer in Xen')
> Signed-off-by: Roger Pau Monné 

Reviewed-by: Jan Beulich 



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Date: Mon, 25 Aug 2025 17:26:28 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau Monne 
Cc: xen-devel@lists.xenproject.org, Jan Beulich ,
	Andrew Cooper 
Subject: Re: [PATCH] x86/suspend: unconditionally raise a timer softirq on
 resume
Message-ID: 
References: <20250825151515.39177-1-roger.pau@citrix.com>
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Date: Mon, 25 Aug 2025 17:26:28 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau Monne 
Cc: xen-devel@lists.xenproject.org, Jan Beulich ,
	Andrew Cooper 
Subject: Re: [PATCH] x86/suspend: unconditionally raise a timer softirq on
 resume

On Mon, Aug 25, 2025 at 05:15:15PM +0200, Roger Pau Monne wrote:
> The current code to restore the timer state on resume is incomplete.  Whi=
le
> the local APIC Initial Count Register is saved and restored across
> suspension (even if possibly no longer accurate since it's not adjusted to
> account for the time spent in suspension), the TSC deadline MSR is not
> saved and restored, hence hosts using the TSC deadline timer will likely
> get stuck when resuming from suspension.
>=20
> The lack of restoring of the TSC deadline MSR was mitigated by the raising
> of a timer softirq in mwait_idle_with_hints() if the timer had expired,
> previous to commit 3faf0866a33070b926ab78e6298290403f85e76c, which removed
> that logic.
>=20
> This patch fixes the usage of the TSC deadline timer with suspension, by
> unconditionally raising a timer softirq on resume, that will take care of
> rearming the hardware timer.  Given that a timer softirq will be
> unconditionally risen, there's no need to save and restore the APIC Initi=
al
> Count Register anymore either.
>=20
> Note that secondary processors don't need this special treatment when
> resuming, since they are offlined before suspension and brought back up
> during resume, the first timer that gets setup will trigger a timer softi=
rq
> unconditionally, for example from sched_migrate_timers() that gets called
> for each secondary processor.
>=20
> Reported-by: Marek Marczykowski-G=C3=B3recki 
> Fixes: fd1291a826e1 ('X86: Prefer TSC-deadline timer in Xen')
> Signed-off-by: Roger Pau Monn=C3=A9 

Tested-by: Marek Marczykowski-G=C3=B3recki 

> ---
>  xen/arch/x86/acpi/power.c | 2 ++
>  xen/arch/x86/apic.c       | 3 ---
>  2 files changed, 2 insertions(+), 3 deletions(-)
>=20
> diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c
> index 2ac162c997fe..27d672ad5dbb 100644
> --- a/xen/arch/x86/acpi/power.c
> +++ b/xen/arch/x86/acpi/power.c
> @@ -19,6 +19,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
> =20
> @@ -310,6 +311,7 @@ static int enter_state(u32 state)
>      thaw_domains();
>      system_state =3D SYS_STATE_active;
>      spin_unlock(&pm_lock);
> +    raise_softirq(TIMER_SOFTIRQ);
>      return error;
>  }
> =20
> diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
> index cac5ba39e615..e3a2b84f1aae 100644
> --- a/xen/arch/x86/apic.c
> +++ b/xen/arch/x86/apic.c
> @@ -65,7 +65,6 @@ static struct {
>      unsigned int apic_lvt0;
>      unsigned int apic_lvt1;
>      unsigned int apic_lvterr;
> -    unsigned int apic_tmict;
>      unsigned int apic_tdcr;
>      unsigned int apic_thmr;
>  } apic_pm_state;
> @@ -658,7 +657,6 @@ int lapic_suspend(void)
>      apic_pm_state.apic_lvt0 =3D apic_read(APIC_LVT0);
>      apic_pm_state.apic_lvt1 =3D apic_read(APIC_LVT1);
>      apic_pm_state.apic_lvterr =3D apic_read(APIC_LVTERR);
> -    apic_pm_state.apic_tmict =3D apic_read(APIC_TMICT);
>      apic_pm_state.apic_tdcr =3D apic_read(APIC_TDCR);
>      if (maxlvt >=3D 5)
>          apic_pm_state.apic_thmr =3D apic_read(APIC_LVTTHMR);
> @@ -718,7 +716,6 @@ int lapic_resume(void)
>          apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
>      apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
>      apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
> -    apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
>      apic_write(APIC_ESR, 0);
>      apic_read(APIC_ESR);
>      apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
> --=20
> 2.49.0
>=20

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Date: Mon, 25 Aug 2025 17:27:41 +0200
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Subject: Re: [PATCH v4 6/8] tools/xl: enable NS16550-compatible UART emulator
 for HVM (x86)
To: Anthony PERARD 
Cc: dmkhn@proton.me, xen-devel@lists.xenproject.org,
 andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org,
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On 25.08.2025 17:13, Anthony PERARD wrote:
> On Mon, Aug 25, 2025 at 05:03:40PM +0200, Jan Beulich wrote:
>> On 25.08.2025 16:49, Anthony PERARD wrote:
>>> On Thu, Jul 31, 2025 at 07:22:12PM +0000, dmkhn@proton.me wrote:
>>>> -=item B
>>>> +=item B
>>>
>>> This syntax here would inditace that `vuart` takes a list of items. You
>>> could write instead:
>>>
>>>     vuart="UART"
>>>
>>> which seems more in line with the rest of the man page. Then you can add
>>> some thing like "with UART been one of "sbsa_uart" or "ns16550". It's
>>> possible to also have a sublist, like the `tee` option have.
>>
>> But shouldn't the syntax already now allow for multiple items? Possibly
>> even multiple ones of the same kind?
> 
> How does `vuart="uart"` allow for multiple items?

Precisely. I would have expected it to be e.g.

vuart = [ "ns16550", "ns16550", "sbsa-uart" ]

(i.e. the square brackets are part of the necessary syntax).

Jan


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Date: Mon, 25 Aug 2025 17:28:44 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: Andrew Cooper ,
	Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH] x86/suspend: unconditionally raise a timer softirq on
 resume
Message-ID: 
References: <20250825151515.39177-1-roger.pau@citrix.com>
 
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On Mon, Aug 25, 2025 at 05:25:36PM +0200, Jan Beulich wrote:
> On 25.08.2025 17:15, Roger Pau Monne wrote:
> > The current code to restore the timer state on resume is incomplete.  While
> > the local APIC Initial Count Register is saved and restored across
> > suspension (even if possibly no longer accurate since it's not adjusted to
> > account for the time spent in suspension), the TSC deadline MSR is not
> > saved and restored, hence hosts using the TSC deadline timer will likely
> > get stuck when resuming from suspension.
> > 
> > The lack of restoring of the TSC deadline MSR was mitigated by the raising
> > of a timer softirq in mwait_idle_with_hints() if the timer had expired,
> > previous to commit 3faf0866a33070b926ab78e6298290403f85e76c, which removed
> > that logic.
> > 
> > This patch fixes the usage of the TSC deadline timer with suspension, by
> > unconditionally raising a timer softirq on resume, that will take care of
> > rearming the hardware timer.  Given that a timer softirq will be
> > unconditionally risen, there's no need to save and restore the APIC Initial
> > Count Register anymore either.
> > 
> > Note that secondary processors don't need this special treatment when
> > resuming, since they are offlined before suspension and brought back up
> > during resume, the first timer that gets setup will trigger a timer softirq
> > unconditionally, for example from sched_migrate_timers() that gets called
> > for each secondary processor.
> > 
> > Reported-by: Marek Marczykowski-Górecki 
> > Fixes: fd1291a826e1 ('X86: Prefer TSC-deadline timer in Xen')
> > Signed-off-by: Roger Pau Monné 
> 
> Reviewed-by: Jan Beulich 

Thanks, I've also added:

Link: https://github.com/QubesOS/qubes-issues/issues/10110

To the tags.

Roger.


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Subject: Re: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq
 para
To: Penny Zheng 
Cc: ray.huang@amd.com, Anthony PERARD ,
 Juergen Gross , Andrew Cooper ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-12-Penny.Zheng@amd.com>
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On 22.08.2025 12:52, Penny Zheng wrote:
> We extract cppc info from "struct xen_get_cpufreq_para", where it acts as
> a member of union, and share the space with governor info.
> However, it may fail in amd-cppc passive mode, in which governor info and
> CPPC info could co-exist, and both need to be printed together via xenpm tool.
> If we tried to still put it in "struct xen_get_cpufreq_para" (e.g. just move
> out of union), "struct xen_get_cpufreq_para" will enlarge too much to further
> make xen_sysctl.u exceed 128 bytes.
> 
> So we introduce a new sub-field GET_CPUFREQ_CPPC to dedicatedly acquire
> CPPC-related para, and make get-cpufreq-para invoke GET_CPUFREQ_CPPC
> if available.
> New helpers print_cppc_para() and get_cpufreq_cppc() are introduced to
> extract CPPC-related parameters process from cpufreq para.
> 
> Signed-off-by: Penny Zheng 

Acked-by: Jan Beulich  # hypervisor

> --- a/tools/libs/ctrl/xc_pm.c
> +++ b/tools/libs/ctrl/xc_pm.c
> @@ -288,7 +288,6 @@ int xc_get_cpufreq_para(xc_interface *xch, int cpuid,
>          CHK_FIELD(s.scaling_min_freq);
>          CHK_FIELD(s.u.userspace);
>          CHK_FIELD(s.u.ondemand);
> -        CHK_FIELD(cppc_para);
>  
>  #undef CHK_FIELD

What is done here is already less than what could be done; I think ...

> @@ -366,6 +365,33 @@ int xc_set_cpufreq_cppc(xc_interface *xch, int cpuid,
>      return ret;
>  }
>  
> +int xc_get_cppc_para(xc_interface *xch, unsigned int cpuid,
> +                     xc_cppc_para_t *cppc_para)
> +{
> +    int ret;
> +    struct xen_sysctl sysctl = {};
> +    struct xen_get_cppc_para *sys_cppc_para = &sysctl.u.pm_op.u.get_cppc;
> +
> +    if ( !xch  || !cppc_para )
> +    {
> +        errno = EINVAL;
> +        return -1;
> +    }
> +
> +    sysctl.cmd = XEN_SYSCTL_pm_op;
> +    sysctl.u.pm_op.cmd = GET_CPUFREQ_CPPC;
> +    sysctl.u.pm_op.cpuid = cpuid;
> +
> +    ret = xc_sysctl(xch, &sysctl);
> +    if ( ret )
> +        return ret;
> +
> +    BUILD_BUG_ON(sizeof(*cppc_para) != sizeof(*sys_cppc_para));
> +    memcpy(cppc_para, sys_cppc_para, sizeof(*sys_cppc_para));

... you minimally want to apply as much checking here.

Jan


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Date: Mon, 25 Aug 2025 17:39:06 +0200
From: Anthony PERARD 
To: Jan Beulich 
Cc: dmkhn@proton.me, xen-devel@lists.xenproject.org,
	andrew.cooper3@citrix.com, anthony.perard@vates.tech,
	julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com,
	sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 6/8] tools/xl: enable NS16550-compatible UART emulator
 for HVM (x86)
Message-ID: 
References: <20250731192130.3948419-1-dmukhin@ford.com>
 <20250731192130.3948419-7-dmukhin@ford.com>
 
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On Mon, Aug 25, 2025 at 05:27:41PM +0200, Jan Beulich wrote:
> On 25.08.2025 17:13, Anthony PERARD wrote:
> > On Mon, Aug 25, 2025 at 05:03:40PM +0200, Jan Beulich wrote:
> >> On 25.08.2025 16:49, Anthony PERARD wrote:
> >>> On Thu, Jul 31, 2025 at 07:22:12PM +0000, dmkhn@proton.me wrote:
> >>>> -=item B
> >>>> +=item B
> >>>
> >>> This syntax here would inditace that `vuart` takes a list of items. You
> >>> could write instead:
> >>>
> >>>     vuart="UART"
> >>>
> >>> which seems more in line with the rest of the man page. Then you can add
> >>> some thing like "with UART been one of "sbsa_uart" or "ns16550". It's
> >>> possible to also have a sublist, like the `tee` option have.
> >>
> >> But shouldn't the syntax already now allow for multiple items? Possibly
> >> even multiple ones of the same kind?
> > 
> > How does `vuart="uart"` allow for multiple items?
> 
> Precisely. I would have expected it to be e.g.
> 
> vuart = [ "ns16550", "ns16550", "sbsa-uart" ]

This is not an option.

Having mutliple ns16550 would do exactly the same thing as having a
single one. It's not possible to have both ns16550 and sbsa_uart at the
same time, one is for x86, one is for Arm. I don't know if it's possible
to have several sbsa_uart but the code in libxl doesn't have the
capability.

So overall, I don't think having a list in the xl.cfg syntax is useful
right now. It's easy to change later, I think.

> (i.e. the square brackets are part of the necessary syntax).
> 
> Jan

-- 
Anthony PERARD


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Subject: Re: [PATCH v7 12/13] xen/cpufreq: bypass governor-related para for
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To: Penny Zheng 
Cc: ray.huang@amd.com, Anthony PERARD ,
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On 22.08.2025 12:52, Penny Zheng wrote:
> --- a/tools/misc/xenpm.c
> +++ b/tools/misc/xenpm.c
> @@ -832,9 +832,13 @@ static void print_cppc_para(unsigned int cpuid,
>  /* print out parameters about cpu frequency */
>  static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
>  {
> -    bool hwp = strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) == 0;
> +    bool is_goverless = false;

I first thought this would be a typo just in the description. Please make
this is_governor_less, or - if you absolutely want to have a shorter
identifier - is_govless (albeit then you might also consider to drop the
is_ prefix).

> --- a/xen/drivers/cpufreq/cpufreq.c
> +++ b/xen/drivers/cpufreq/cpufreq.c
> @@ -956,3 +956,17 @@ int __init cpufreq_register_driver(const struct cpufreq_driver *driver_data)
>  
>      return 0;
>  }
> +
> +#ifdef CONFIG_PM_OP
> +/*
> + * Governor-less cpufreq driver indicates the driver doesn't rely on Xen
> + * governor to do performance tuning, mostly it has hardware built-in
> + * algorithm to calculate runtime workload and adjust cores frequency
> + * automatically. like Intel HWP, or CPPC in AMD.

Nit: Capital letter please at the start of a sentence.

> + */
> +bool cpufreq_is_governorless(unsigned int cpuid)
> +{
> +    return processor_pminfo[cpuid]->init && (hwp_active() ||
> +                                             cpufreq_driver.setpolicy);
> +}
> +#endif /* CONFIG_PM_OP */

Aiui the #ifdef is to please Misra, but that's not very nice to have. Does
any of the constituents stand in the way of this becoming an inline function
in a suitable header file?

Jan


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Subject: Re: [PATCH v4 6/8] tools/xl: enable NS16550-compatible UART emulator
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To: Anthony PERARD 
Cc: dmkhn@proton.me, xen-devel@lists.xenproject.org,
 andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org,
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On 25.08.2025 17:39, Anthony PERARD wrote:
> On Mon, Aug 25, 2025 at 05:27:41PM +0200, Jan Beulich wrote:
>> On 25.08.2025 17:13, Anthony PERARD wrote:
>>> On Mon, Aug 25, 2025 at 05:03:40PM +0200, Jan Beulich wrote:
>>>> On 25.08.2025 16:49, Anthony PERARD wrote:
>>>>> On Thu, Jul 31, 2025 at 07:22:12PM +0000, dmkhn@proton.me wrote:
>>>>>> -=item B
>>>>>> +=item B
>>>>>
>>>>> This syntax here would inditace that `vuart` takes a list of items. You
>>>>> could write instead:
>>>>>
>>>>>     vuart="UART"
>>>>>
>>>>> which seems more in line with the rest of the man page. Then you can add
>>>>> some thing like "with UART been one of "sbsa_uart" or "ns16550". It's
>>>>> possible to also have a sublist, like the `tee` option have.
>>>>
>>>> But shouldn't the syntax already now allow for multiple items? Possibly
>>>> even multiple ones of the same kind?
>>>
>>> How does `vuart="uart"` allow for multiple items?
>>
>> Precisely. I would have expected it to be e.g.
>>
>> vuart = [ "ns16550", "ns16550", "sbsa-uart" ]
> 
> This is not an option.
> 
> Having mutliple ns16550 would do exactly the same thing as having a
> single one. It's not possible to have both ns16550 and sbsa_uart at the
> same time, one is for x86, one is for Arm. I don't know if it's possible
> to have several sbsa_uart but the code in libxl doesn't have the
> capability.
> 
> So overall, I don't think having a list in the xl.cfg syntax is useful
> right now. It's easy to change later, I think.

Well, never mind then.

Jan


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Message-ID: <07fc7122-d0ac-4dbe-800d-89086a07005b@gmail.com>
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To: Xen-devel ,
 Community Manager ,
 "committers@xenproject.org" 
From: Oleksii Kurochko 
Subject: [Reminder] Feature Freeze is Fri Aug 29, 2025

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--------------rqeomJbHqoerFSMl0BcNalTV
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Hello community,

I’d like to remind everyone that the Feature Freeze deadline is approaching,
and we still have some outstanding requests from the community for patch series
to be merged into 4.21:

1. Enable guest suspend/resume support on ARM via vPSCI [1]
2. Introduce SCI SCMI SMC multi-agent support [2]
3. Introduce eSPI support [3]
4. FRED work: [4], [5], possibly others (?)
5. Introduce CONFIG_DOMCTL [6]
6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
7. Some other patch series I missed.

It looks like some of these patch series still require additional work,
and I’m not sure there is enough time left before the end of this week.

Could I kindly ask for an estimation of whether these tasks can be completed in time?

[1]https://lore.kernel.org/xen-devel/87jz2vaq9h.fsf@epam.com/
[2]https://lore.kernel.org/xen-devel/cover.1753184487.git.oleksii_moisieiev@epam.com/
[3]https://lore.kernel.org/xen-devel/7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com/

[4]https://lore.kernel.org/xen-devel/20250808202314.1045968-1-andrew.cooper3@citrix.com/
[5]https://lore.kernel.org/xen-devel/20250815204117.3312742-1-andrew.cooper3@citrix.com/

[6]https://lore.kernel.org/xen-devel/20250803094738.3625269-6-Penny.Zheng@amd.com/
[7]https://lore.kernel.org/xen-devel/20250815102728.1340505-1-Penny.Zheng@amd.com/

Thanks in advance.

Best regards,
   Oleksii

--------------rqeomJbHqoerFSMl0BcNalTV
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 8bit



  

    
  
  
    
    Hello community,

I’d like to remind everyone that the Feature Freeze deadline is approaching,
and we still have some outstanding requests from the community for patch series
to be merged into 4.21:

1. Enable guest suspend/resume support on ARM via vPSCI [1]
2. Introduce SCI SCMI SMC multi-agent support [2]
3. Introduce eSPI support [3]
4. FRED work: [4], [5], possibly others (?)
5. Introduce CONFIG_DOMCTL [6]
6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
7. Some other patch series I missed.

It looks like some of these patch series still require additional work,
and I’m not sure there is enough time left before the end of this week.

Could I kindly ask for an estimation of whether these tasks can be completed in time?

[1] https://lore.kernel.org/xen-devel/87jz2vaq9h.fsf@epam.com/
[2] https://lore.kernel.org/xen-devel/cover.1753184487.git.oleksii_moisieiev@epam.com/
[3] https://lore.kernel.org/xen-devel/7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com/

[4] https://lore.kernel.org/xen-devel/20250808202314.1045968-1-andrew.cooper3@citrix.com/
[5] https://lore.kernel.org/xen-devel/20250815204117.3312742-1-andrew.cooper3@citrix.com/

[6] https://lore.kernel.org/xen-devel/20250803094738.3625269-6-Penny.Zheng@amd.com/
[7] https://lore.kernel.org/xen-devel/20250815102728.1340505-1-Penny.Zheng@amd.com/

Thanks in advance.

Best regards,
  Oleksii

    
  


--------------rqeomJbHqoerFSMl0BcNalTV--


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Subject: Re: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
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To: Penny Zheng 
Cc: ray.huang@amd.com, Anthony PERARD ,
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On 22.08.2025 12:52, Penny Zheng wrote:
> --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c
> +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
> @@ -557,6 +557,187 @@ static int cf_check amd_cppc_epp_set_policy(struct cpufreq_policy *policy)
>      return 0;
>  }
>  
> +#ifdef CONFIG_PM_OP
> +int get_amd_cppc_para(const struct cpufreq_policy *policy,
> +                      struct xen_get_cppc_para *cppc_para)

amd_cppc_get_para() and ...

> +{
> +    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data,
> +                                                   policy->cpu);
> +
> +    if ( data == NULL )
> +        return -ENODATA;
> +
> +    cppc_para->policy           = policy->policy;
> +    cppc_para->lowest           = data->caps.lowest_perf;
> +    cppc_para->lowest_nonlinear = data->caps.lowest_nonlinear_perf;
> +    cppc_para->nominal          = data->caps.nominal_perf;
> +    cppc_para->highest          = data->caps.highest_perf;
> +    cppc_para->minimum          = data->req.min_perf;
> +    cppc_para->maximum          = data->req.max_perf;
> +    cppc_para->desired          = data->req.des_perf;
> +    cppc_para->energy_perf      = data->req.epp;
> +
> +    return 0;
> +}
> +
> +int set_amd_cppc_para(struct cpufreq_policy *policy,
> +                      const struct xen_set_cppc_para *set_cppc)

... amd_cppc_set_para() would imo be more consistent names, considering how
other functions are named.

> +{
> +    unsigned int cpu = policy->cpu;
> +    struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);
> +    uint8_t max_perf, min_perf, des_perf, epp;
> +    bool active_mode = cpufreq_is_governorless(cpu);
> +
> +    if ( data == NULL )
> +        return -ENOENT;
> +
> +    /* Return if there is nothing to do. */
> +    if ( set_cppc->set_params == 0 )
> +        return 0;

That is ...

> +    /* Only allow values if params bit is set. */
> +    if ( (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED) &&
> +          set_cppc->desired) ||
> +         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) &&
> +          set_cppc->minimum) ||
> +         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
> +          set_cppc->maximum) ||
> +         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF) &&
> +          set_cppc->energy_perf) )
> +        return -EINVAL;

... all the errors checked here are to be ignored when no flag is set at
all?

> +    /*
> +     * Validate all parameters
> +     * Maximum performance may be set to any performance value in the range
> +     * [Nonlinear Lowest Performance, Highest Performance], inclusive but must
> +     * be set to a value that is larger than or equal to minimum Performance.
> +     */
> +    if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
> +         (set_cppc->maximum > data->caps.highest_perf ||
> +          set_cppc->maximum <
> +                        (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM
> +                         ? set_cppc->minimum
> +                         : data->req.min_perf)) )

Too deep indentation (more of this throughout the function), and seeing ...

> +        return -EINVAL;
> +    /*
> +     * Minimum performance may be set to any performance value in the range
> +     * [Nonlinear Lowest Performance, Highest Performance], inclusive but must
> +     * be set to a value that is less than or equal to Maximum Performance.
> +     */
> +    if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) &&
> +         (set_cppc->minimum < data->caps.lowest_nonlinear_perf ||
> +          (set_cppc->minimum >

... this, one more pair of parentheses may also help there. (Recall:
symmetry where possible.)

> +                        (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM
> +                         ? set_cppc->maximum
> +                         : data->req.max_perf))) )
> +        return -EINVAL;
> +    /*
> +     * Desired performance may be set to any performance value in the range
> +     * [Minimum Performance, Maximum Performance], inclusive.
> +     */
> +    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED )
> +    {
> +        if ( active_mode )
> +            return -EOPNOTSUPP;
> +
> +        if ( (set_cppc->desired >
> +                        (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM
> +                         ? set_cppc->maximum
> +                         : data->req.max_perf)) ||
> +             (set_cppc->desired <
> +                        (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM
> +                         ? set_cppc->minimum
> +                         : data->req.min_perf)) )
> +            return -EINVAL;
> +    }
> +    /*
> +     * Energy Performance Preference may be set with a range of values
> +     * from 0 to 0xFF
> +     */
> +    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF )
> +    {
> +        if ( !active_mode )
> +            return -EOPNOTSUPP;
> +
> +        if ( set_cppc->energy_perf > UINT8_MAX )
> +            return -EINVAL;
> +    }
> +
> +    /* Activity window not supported in MSR */
> +    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ACT_WINDOW )
> +        return -EOPNOTSUPP;
> +
> +    epp = per_cpu(epp_init, cpu);
> +    min_perf = data->caps.lowest_nonlinear_perf;
> +    max_perf = data->caps.highest_perf;
> +    des_perf = data->req.des_perf;
> +    /*
> +     * Apply presets:
> +     * XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE/PERFORMANCE/ONDEMAND are
> +     * only available when CPPC in active mode
> +     */
> +    switch ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_PRESET_MASK )
> +    {
> +    case XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE:
> +        if ( !active_mode )
> +            return -EINVAL;
> +        policy->policy = CPUFREQ_POLICY_POWERSAVE;
> +        /*
> +         * Lower max_perf to nonlinear_lowest to achieve
> +         * ultmost power saviongs
> +         */
> +        max_perf = min_perf;
> +        epp = CPPC_ENERGY_PERF_MAX_POWERSAVE;
> +        break;
> +
> +    case XEN_SYSCTL_CPPC_SET_PRESET_PERFORMANCE:
> +        if ( !active_mode )
> +            return -EINVAL;
> +        policy->policy = CPUFREQ_POLICY_PERFORMANCE;
> +        /* Increase min_perf to highest to achieve ultmost performance */
> +        min_perf = max_perf;
> +        epp = CPPC_ENERGY_PERF_MAX_PERFORMANCE;
> +        break;
> +
> +    case XEN_SYSCTL_CPPC_SET_PRESET_ONDEMAND:
> +        if ( !active_mode )
> +            return -EINVAL;
> +        policy->policy = CPUFREQ_POLICY_ONDEMAND;
> +        /*
> +         * Take medium value to show no preference over
> +         * performance or powersave
> +         */
> +        epp = CPPC_ENERGY_PERF_BALANCE;
> +        break;
> +
> +    case XEN_SYSCTL_CPPC_SET_PRESET_NONE:
> +        if ( active_mode )
> +            policy->policy = CPUFREQ_POLICY_UNKNOWN;
> +        break;
> +
> +    default:
> +        return -EINVAL;
> +    }

Much of this looks very similar to what patch 09 introduces in
amd_cppc_epp_set_policy(). Is it not possible to reduce the redundancy?

> --- a/xen/include/acpi/cpufreq/cpufreq.h
> +++ b/xen/include/acpi/cpufreq/cpufreq.h
> @@ -81,7 +81,18 @@ struct cpufreq_policy {
>      int8_t              turbo;  /* tristate flag: 0 for unsupported
>                                   * -1 for disable, 1 for enabled
>                                   * See CPUFREQ_TURBO_* below for defines */
> -    unsigned int        policy; /* CPUFREQ_POLICY_* */
> +    unsigned int        policy; /* Performance Policy
> +                                 * If cpufreq_driver->target() exists,
> +                                 * the ->governor decides what frequency
> +                                 * within the limits is used.
> +                                 * If cpufreq_driver->setpolicy() exists, these
> +                                 * following policies are available:
> +                                 * CPUFREQ_POLICY_PERFORMANCE represents
> +                                 * maximum performance
> +                                 * CPUFREQ_POLICY_POWERSAVE represents least
> +                                 * power consumption
> +                                 * CPUFREQ_POLICY_ONDEMAND represents no
> +                                 * preference over performance or powersave */

Besides not being a well-formed comment, this is close to unreadable in this
shape. This much text wants putting ahead of the field.

> --- a/xen/include/public/sysctl.h
> +++ b/xen/include/public/sysctl.h
> @@ -336,8 +336,14 @@ struct xen_ondemand {
>      uint32_t up_threshold;
>  };
>  
> +#define CPUFREQ_POLICY_UNKNOWN      0
> +#define CPUFREQ_POLICY_POWERSAVE    1
> +#define CPUFREQ_POLICY_PERFORMANCE  2
> +#define CPUFREQ_POLICY_ONDEMAND     3

Without XEN_ prefixes they shouldn't appear in a public header. But do
we need ...

>  struct xen_get_cppc_para {
>      /* OUT */
> +    uint32_t policy; /* CPUFREQ_POLICY_xxx */

... the new field at all? Can't you synthesize the kind-of-governor into
struct xen_get_cpufreq_para's respective field? You invoke both sub-ops
from xenpm now anyway ...

Jan


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Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Oleksii Kurochko 
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On 25.08.2025 17:50, Oleksii Kurochko wrote:
> Hello community,
> 
> I’d like to remind everyone that the Feature Freeze deadline is approaching,
> and we still have some outstanding requests from the community for patch series
> to be merged into 4.21:
> 
> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
> 2. Introduce SCI SCMI SMC multi-agent support [2]
> 3. Introduce eSPI support [3]
> 4. FRED work: [4], [5], possibly others (?)
> 5. Introduce CONFIG_DOMCTL [6]
> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]

As per a mail sent earlier today, for these two we will need to settle on
which route to take, including the consideration of whether the work can
realistically be completed in time (or whether an upfront exception could
be granted).

Jan

> 7. Some other patch series I missed.
> 
> It looks like some of these patch series still require additional work,
> and I’m not sure there is enough time left before the end of this week.
> 
> Could I kindly ask for an estimation of whether these tasks can be completed in time?
> 
> [1]https://lore.kernel.org/xen-devel/87jz2vaq9h.fsf@epam.com/
> [2]https://lore.kernel.org/xen-devel/cover.1753184487.git.oleksii_moisieiev@epam.com/
> [3]https://lore.kernel.org/xen-devel/7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com/
> 
> [4]https://lore.kernel.org/xen-devel/20250808202314.1045968-1-andrew.cooper3@citrix.com/
> [5]https://lore.kernel.org/xen-devel/20250815204117.3312742-1-andrew.cooper3@citrix.com/
> 
> [6]https://lore.kernel.org/xen-devel/20250803094738.3625269-6-Penny.Zheng@amd.com/
> [7]https://lore.kernel.org/xen-devel/20250815102728.1340505-1-Penny.Zheng@amd.com/
> 
> Thanks in advance.
> 
> Best regards,
>    Oleksii
> 



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Subject: Re: [PATCH] misra: add deviation of Rule 17.7
Thread-Topic: [PATCH] misra: add deviation of Rule 17.7
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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Andrew Cooper , Jan Beulich
	, =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Anthony PERARD , Michal
 Orzel , Julien Grall , Stefano
 Stabellini , Dmytro Prokopchuk1
	
Subject: [PATCH v3] xen/irq: Delete the pirq_cleanup_check() macro
Thread-Topic: [PATCH v3] xen/irq: Delete the pirq_cleanup_check() macro
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Date: Mon, 25 Aug 2025 19:22:44 +0000
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From: Andrew Cooper 

MISRA Rule 5.5 objects to a macro aliasing a function, which is what
pirq_cleanup_check() does. The macro was originally intended to ensure
the condition 'if (!pirq->evtchn)' is always checked before invoking
the function, avoiding errors across call sites.

There are only a handful of users, so expand it inline to be plain
regular C. Doing this shows one path now needing braces, and one path
in 'evtchn_bind_pirq()' where the expanded form simplies back to no
delta, as it follows an unconditional clear of 'info->evtchn'.

While this complies with MISRA, it shifts the responsibility to
developers to check 'if (!pirq->evtchn)' at call sites.

No functional changes.

Signed-off-by: Andrew Cooper 
Signed-off-by: Dmytro Prokopchuk 
---
Changes in v3:
- added back wording from v1, originally written by Andrew.

Link to v2:
https://patchew.org/Xen/ce37bdf7b5189d314c0f41628dbfb3281358bcf4.1755361782=
.git.dmytro._5Fprokopchuk1@epam.com/

Link to v1:
https://patchew.org/Xen/20250729223110.3404441-1-andrew.cooper3@citrix.com/
---
 xen/arch/x86/irq.c                | 11 +++++++----
 xen/common/event_channel.c        |  5 ++++-
 xen/drivers/passthrough/x86/hvm.c |  9 ++++++---
 xen/include/xen/irq.h             |  3 ---
 4 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c
index 556134f85a..1ed85c0c11 100644
--- a/xen/arch/x86/irq.c
+++ b/xen/arch/x86/irq.c
@@ -1325,7 +1325,8 @@ static void clear_domain_irq_pirq(struct domain *d, i=
nt irq, struct pirq *pirq)
 static void cleanup_domain_irq_pirq(struct domain *d, int irq,
                                     struct pirq *pirq)
 {
-    pirq_cleanup_check(pirq, d);
+    if ( !pirq->evtchn )
+        pirq_cleanup_check(pirq, d);
     radix_tree_delete(&d->arch.irq_pirq, irq);
 }
=20
@@ -1383,7 +1384,7 @@ struct pirq *alloc_pirq_struct(struct domain *d)
     return pirq;
 }
=20
-void (pirq_cleanup_check)(struct pirq *pirq, struct domain *d)
+void pirq_cleanup_check(struct pirq *pirq, struct domain *d)
 {
     /*
      * Check whether all fields have their default values, and delete
@@ -2823,7 +2824,8 @@ int map_domain_emuirq_pirq(struct domain *d, int pirq=
, int emuirq)
                 radix_tree_int_to_ptr(pirq));
             break;
         default:
-            pirq_cleanup_check(info, d);
+            if ( !info->evtchn )
+                pirq_cleanup_check(info, d);
             return err;
         }
     }
@@ -2858,7 +2860,8 @@ int unmap_domain_pirq_emuirq(struct domain *d, int pi=
rq)
     if ( info )
     {
         info->arch.hvm.emuirq =3D IRQ_UNBOUND;
-        pirq_cleanup_check(info, d);
+        if ( !info->evtchn )
+            pirq_cleanup_check(info, d);
     }
     if ( emuirq !=3D IRQ_PT )
         radix_tree_delete(&d->arch.hvm.emuirq_pirq, emuirq);
diff --git a/xen/common/event_channel.c b/xen/common/event_channel.c
index 67700b050a..a3d18bc464 100644
--- a/xen/common/event_channel.c
+++ b/xen/common/event_channel.c
@@ -741,11 +741,14 @@ int evtchn_close(struct domain *d1, int port1, bool g=
uest)
             if ( !is_hvm_domain(d1) ||
                  domain_pirq_to_irq(d1, pirq->pirq) <=3D 0 ||
                  unmap_domain_pirq_emuirq(d1, pirq->pirq) < 0 )
+            {
                 /*
                  * The successful path of unmap_domain_pirq_emuirq() will =
have
                  * called pirq_cleanup_check() already.
                  */
-                pirq_cleanup_check(pirq, d1);
+                if ( !pirq->evtchn )
+                    pirq_cleanup_check(pirq, d1);
+            }
         }
         unlink_pirq_port(chn1, d1->vcpu[chn1->notify_vcpu_id]);
         break;
diff --git a/xen/drivers/passthrough/x86/hvm.c b/xen/drivers/passthrough/x8=
6/hvm.c
index a2ca7e0e57..b73bb55055 100644
--- a/xen/drivers/passthrough/x86/hvm.c
+++ b/xen/drivers/passthrough/x86/hvm.c
@@ -329,7 +329,8 @@ int pt_irq_create_bind(
                 pirq_dpci->gmsi.gvec =3D 0;
                 pirq_dpci->dom =3D NULL;
                 pirq_dpci->flags =3D 0;
-                pirq_cleanup_check(info, d);
+                if ( !info->evtchn )
+                    pirq_cleanup_check(info, d);
                 write_unlock(&d->event_lock);
                 return rc;
             }
@@ -536,7 +537,8 @@ int pt_irq_create_bind(
                     hvm_irq_dpci->link_cnt[link]--;
                 }
                 pirq_dpci->flags =3D 0;
-                pirq_cleanup_check(info, d);
+                if ( !info->evtchn )
+                    pirq_cleanup_check(info, d);
                 write_unlock(&d->event_lock);
                 xfree(girq);
                 xfree(digl);
@@ -693,7 +695,8 @@ int pt_irq_destroy_bind(
          */
         pt_pirq_softirq_reset(pirq_dpci);
=20
-        pirq_cleanup_check(pirq, d);
+        if ( !pirq->evtchn )
+            pirq_cleanup_check(pirq, d);
     }
=20
     write_unlock(&d->event_lock);
diff --git a/xen/include/xen/irq.h b/xen/include/xen/irq.h
index 95034c0d6b..6071b00f62 100644
--- a/xen/include/xen/irq.h
+++ b/xen/include/xen/irq.h
@@ -185,9 +185,6 @@ extern struct pirq *pirq_get_info(struct domain *d, int=
 pirq);
=20
 void pirq_cleanup_check(struct pirq *pirq, struct domain *d);
=20
-#define pirq_cleanup_check(pirq, d) \
-    (!(pirq)->evtchn ? pirq_cleanup_check(pirq, d) : (void)0)
-
 extern void pirq_guest_eoi(struct pirq *pirq);
 extern void desc_guest_eoi(struct irq_desc *desc, struct pirq *pirq);
 extern int pirq_guest_unmask(struct domain *d);
--=20
2.43.0


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Message-ID: 
Date: Mon, 25 Aug 2025 17:30:20 -0400
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Oleksii Kurochko , Xen-devel
	, Community Manager
	, "committers@xenproject.org"
	
References: <07fc7122-d0ac-4dbe-800d-89086a07005b@gmail.com>
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On 2025-08-25 11:50, Oleksii Kurochko wrote:
> Hello community,
> 
> I’d like to remind everyone that the Feature Freeze deadline is approaching,
> and we still have some outstanding requests from the community for patch series
> to be merged into 4.21:
> 
> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
> 2. Introduce SCI SCMI SMC multi-agent support [2]
> 3. Introduce eSPI support [3]
> 4. FRED work: [4], [5], possibly others (?)
> 5. Introduce CONFIG_DOMCTL [6]
> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
> 7. Some other patch series I missed.

Hi Oleksii,

I'd like to get 
https://lore.kernel.org/xen-devel/20250822213946.245307-1-jason.andryuk@amd.com/T/#t 
in if possible.

It's v2, and there were 3 RFC postings before the v1 as well.

Thanks,
Jason


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Date: Mon, 25 Aug 2025 17:37:56 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 09/10] xen/arm: scmi: introduce SCI SCMI SMC
 multi-agent driver
In-Reply-To: <9f4a137980a0ee72f0f03d55176ca178c4b90126.1753184487.git.oleksii_moisieiev@epam.com>
Message-ID: 
References:  <9f4a137980a0ee72f0f03d55176ca178c4b90126.1753184487.git.oleksii_moisieiev@epam.com>
User-Agent: Alpine 2.22 (DEB 394 2020-01-19)
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On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> This patch introduces SCI driver to support for ARM EL3 Trusted Firmware-A
> (TF-A) which provides SCMI interface with multi-agnet support, as shown

multi-agent


> below.
> 
>   +-----------------------------------------+
>   |                                         |
>   | EL3 TF-A SCMI                           |
>   +-------+--+-------+--+-------+--+-------++
>   |shmem1 |  |shmem0 |  |shmem2 |  |shmemX |
>   +-----+-+  +---+---+  +--+----+  +---+---+
> smc-id1 |        |         |           |
> agent1  |        |         |           |
>   +-----v--------+---------+-----------+----+
>   |              |         |           |    |
>   |              |         |           |    |
>   +--------------+---------+-----------+----+
>          smc-id0 |  smc-id2|    smc-idX|
>          agent0  |  agent2 |    agentX |
>                  |         |           |
>             +----v---+  +--v-----+  +--v-----+
>             |        |  |        |  |        |
>             | Dom0   |  | Dom1   |  | DomX   |
>             |        |  |        |  |        |
>             |        |  |        |  |        |
>             +--------+  +--------+  +--------+
> 
> The EL3 SCMI multi-agent firmware expected to provide SCMI SMC/HVC shared
> memory transport for every Agent in the system.
> 
> The SCMI Agent transport channel defined by pair:
>  - smc-id: SMC/HVC id used for Doorbell
>  - shmem: shared memory for messages transfer, Xen page
>  aligned. Shared memort is mapped with the following flags:
>  MT_DEVICE_nGnRE.
> 
> The follwoing SCMI Agents expected to be defined by SCMI FW to enable SCMI
> multi-agent functionality under Xen:
> - Xen manegement agent: trusted agents that accesses to the Base Protocol

management


> commands to configure agent specific permissions
> - OSPM VM agents: non-trusted agent, one for each Guest domain which is
>   allowed direct HW access. At least one OSPM VM agent has to be provided
>   by FW if HW is handled only by Dom0 or Driver Domain.
> 
> The EL3 SCMI FW expected to implement following Base protocol messages:
> - BASE_DISCOVER_AGENT (optional if agent_id was provided)
> - BASE_RESET_AGENT_CONFIGURATION (optional)
> - BASE_SET_DEVICE_PERMISSIONS (optional)
> 
> The SCI SCMI SMC multi-agent driver implements following
> functionality:
> - The driver is initialized based on the ``xen,config`` node under ``chosen``
>   (only one SCMI interface is supported), which describes the Xen management
>   agent SCMI interface.
> 
> scmi_shm_1: sram@47ff1000 {
>           compatible = "arm,scmi-shmem";
>           reg = <0x0 0x47ff1000 0x0 0x1000>;
> };
> scmi_xen: scmi {
>         compatible = "arm,scmi-smc";
>         arm,smc-id = <0x82000003>; <--- Xen manegement agent smc-id
>         #address-cells = < 1>;
>         #size-cells = < 0>;
>         #access-controller-cells = < 1>;
>         shmem = <&scmi_shm_1>; <--- Xen manegement agent shmem
> };
> 
> - The driver obtains Xen specific SCMI Agent's configuration from the Host DT, probes Agents and
>   builds SCMI Agents list. The Agents configuration is taken from "scmi-secondary-agents"
>   property where first item is "arm,smc-id", second - "arm,scmi-shmem" phandle and third is
>   optional "agent_id":
> 
> chosen {
>   ranges;
>   xen,config {

The node name could be xen-config, but it doesn't matter because we
should check for the compatible string instead (no check on node name).

We need to add a compatible string here, I would use "xen,scmi":

    compatible = "xen,scmi";


>     ranges;
>     scmi-secondary-agents = <
>                   0x82000003 &scmi_shm_0 0
>                   0x82000004 &scmi_shm_2 2
>                   0x82000005 &scmi_shm_3 3
>                   0x82000006 &scmi_shm_4 4>;
>     #scmi-secondary-agents-cells = <3>; <--- optional, default 3
> 
>     scmi_shm_0 : sram@47ff0000 {
>         compatible = "arm,scmi-shmem";
>         reg = <0x0 0x47ff0000 0x0 0x1000>;
>     };
> 
>     scmi_shm_2: sram@47ff2000 {
>             compatible = "arm,scmi-shmem";
>             reg = <0x0 0x47ff2000 0x0 0x1000>;
>     };
>     scmi_shm_3: sram@47ff3000 {
>             compatible = "arm,scmi-shmem";
>             reg = <0x0 0x47ff3000 0x0 0x1000>;
>     };
>     scmi_shm_4: sram@47ff4000 {
>             compatible = "arm,scmi-shmem";
>             reg = <0x0 0x47ff4000 0x0 0x1000>;
>     };
> 
>     // Xen SCMI management channel
>     scmi_shm_1: sram@47ff1000 {
>             compatible = "arm,scmi-shmem";
>             reg = <0x0 0x47ff1000 0x0 0x1000>;
>     };
> 
>     scmi_xen: scmi {
>         compatible = "arm,scmi-smc";
>         arm,smc-id = <0x82000002>; <--- Xen manegement agent smc-id
>         #address-cells = < 1>;
>         #size-cells = < 0>;
>         #access-controller-cells = < 1>;
>         shmem = <&scmi_shm_1>; <--- Xen manegement agent shmem
>     };
>   };
> };
> 
> /{
>     // Host SCMI OSPM channel - provided to the Dom0 as is if SCMI enabled for it
>     scmi_shm: sram@47ff0000 {
>             compatible = "arm,scmi-shmem";
>             reg = <0x0 0x47ff0000 0x0 0x1000>;
>     };
> 
>     firmware {
>         scmi: scmi {
>             compatible = "arm,scmi-smc";
>             arm,smc-id = <0x82000002>; <--- Host OSPM agent smc-id
>             #address-cells = < 1>;
>             #size-cells = < 0>;
>             shmem = <&scmi_shm>; <--- Host OSPM agent shmem
> 
>             protocol@X{
>             };
>         };
>     };
> };
> 
> This approach allows defining multiple SCMI Agents by adding Xen-specific properties under
> the ``/chosen`` node to the Host Device Tree, leaving the main part unchanged. The Host DT
> SCMI channel will be passed to Dom0.
> 
> The Xen management agent is described as a ``scmi_xen`` node under the ``/chosen`` node, which
> is used by Xen to control other SCMI Agents in the system.
> 
> All secondary agents' configurations are provided in the ``scmi-secondary-agents`` property with
> an optional ``agent_id`` field.
> 
> The ``agent_id`` from the ``scmi-secondary-agents`` property is used to identify the agent in the
> system and can be omitted by setting ``#scmi-secondary-agents-cells = <2>``, so the Secondary
> Agents configuration will look like this:
> 
> chosen {
>   xen,config {
>     scmi-secondary-agents = <
>                   0x82000003 &scmi_shm_0
>                   0x82000004 &scmi_shm_2
>                   0x82000005 &scmi_shm_3
>                   0x82000006 &scmi_shm_4>;
>     #scmi-secondary-agents-cells = <2>;
>   };
> }
> 
> In this case, Xen will use the ``SCMI_BASE_DISCOVER_AGENT`` call to discover the ``agent_id``
> for each secondary agent. Providing the ``agent_id`` in the ``scmi-secondary-agents`` property
> allows skipping the discovery call, which is useful when the secondary agent's shared memory is
> not accessible by Xen or when boot time is important because it allows skipping the agent
> discovery procedure.
> 
>   Note that Xen is the only one entry in the system which need to know
>   about SCMI multi-agent support.
> 
> - It implements the SCI subsystem interface required for configuring and
> enabling SCMI functionality for Dom0/hwdom and Guest domains. To enable
> SCMI functionality for domain it has to be configured with unique supported
> SCMI Agent_id and use corresponding SCMI SMC/HVC shared memory transport
> [smc-id, shmem] defined for this SCMI Agent_id.
> - Once Xen domain is configured it can communicate with EL3 SCMI FW:
>   -- zero-copy, the guest domain puts SCMI message in shmem;
>   -- the guest triggers SMC/HVC exception with smc-id (doorbell);
>   -- the Xen driver catches exception, do checks and synchronously forwards
>   it to EL3 FW.
> - the Xen driver sends BASE_RESET_AGENT_CONFIGURATION message to Xen
>   management agent channel on domain destroy event. This allows to reset
>   resources used by domain and so implement use-case like domain reboot.
> 
> Dom0 Enable SCMI SMC:
>  - pass dom0_scmi_agent_id= in Xen command line. if not provided
>    SCMI will be disabled for Dom0 and all SCMI nodes removed from Dom0 DT.
>    The driver updates Dom0 DT SCMI node "arm,smc-id" value and fix up shmem
>    node according to assigned agent_id.
> 
> Guest domains enable SCMI SMC:
>  - xl.cfg: add configuration option as below
> 
>    arm_sci = "type=scmi_smc_multiagent,agent_id=2"
> 
>  - xl.cfg: enable access to the "arm,scmi-shmem" which should correspond assigned agent_id for
>    the domain, for example:
> 
> iomem = [
>     "47ff2,1@22001",
> ]
> 
>  - DT: add SCMI nodes to the Driver domain partial device tree as in the
>  below example. The "arm,smc-id" should correspond assigned agent_id for the domain:
> 
> passthrough {
>    scmi_shm_0: sram@22001000 {
>        compatible = "arm,scmi-shmem";
>        reg = <0x0 0x22001000 0x0 0x1000>;
>    };
> 
>    firmware {
>         compatible = "simple-bus";
>             scmi: scmi {
>                 compatible = "arm,scmi-smc";
>                 arm,smc-id = <0x82000004>;
>                 shmem = <&scmi_shm_0>;
>                 ...
>             }
>     }
> }
> 
> SCMI "4.2.1.1 Device specific access control"
> 
> The XEN SCI SCMI SMC multi-agent driver performs "access-controller" provider function
> in case EL3 SCMI FW implements SCMI "4.2.1.1 Device specific access control" and provides the
> BASE_SET_DEVICE_PERMISSIONS command to configure the devices that an agents have access to.
> The DT SCMI node should "#access-controller-cells=<1>" property and DT devices should be bound
> to the Xen SCMI.
> 
> &i2c1 {
> 	access-controllers = <&scmi 0>;
> };
> 
> The Dom0 and dom0less domains DT devices will be processed automatically through
> sci_assign_dt_device() call, but to assign SCMI devices from toolstack the xl.cfg:"dtdev" property
> shell be used:

shall

> 
> dtdev = [
>     "/soc/i2c@e6508000",
> ]
> 
> xl.cfg:dtdev will contain all nodes which are under SCMI management (not only those which are behind IOMMU).
> 
> [1] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> [2] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml
> 
> Signed-off-by: Oleksii Moisieiev 
> Signed-off-by: Grygorii Strashko 
> ---
> 
> Changes in v5:
> - fix device-tree example format in booting.txt, added ";" after "}".
> - update define in scmi-proto.h
> - update define in scmi-shmem.h file
> - scmi_assign_device - do not ignore -EOPNOTSUPP return
> code of the do_smc_xfer
> - remove overwriting agent_channel->agent_id after
> SCMI_BASE_DISCOVER_AGENT call
> - add multi-agent files to the MAINTAINERS
> - add SCMI multi-agent description to the SUPPORT.md
> - handle ARM_SMCCC_INVALID_PARAMETER return code and return -EINVAL
> for smc call
> - updated collect_agents function. Set agent_id parameter as optional
> in scmi-secondary-agents device-tree property
> - introduce "#scmi-secondary-agents-cells" parameter to set if
> agent_id was provided
> - reanme xen,scmi-secondary-agents property to scmi-secondary-agents
> - move memcpu_toio/fromio for the generic place
> - update Xen to get management channel from /chosen/xen,config node
> - get hypervisor channnel from node instead of using hardcoded
> - update handling scmi and shmem nodes for the domain
> - Set multi-agent driver to support only Arm64
> 
> Changes in v4:
> - toolstack comments from Anthony PERARD
> - added dom0less support
> - added doc for "xen,scmi-secondary-agents"
> 
>  MAINTAINERS                                 |   4 +
>  SUPPORT.md                                  |  11 +
>  docs/man/xl.cfg.5.pod.in                    |  13 +
>  docs/misc/arm/device-tree/booting.txt       |  88 +++
>  docs/misc/xen-command-line.pandoc           |   9 +
>  tools/libs/light/libxl_arm.c                |   4 +
>  tools/libs/light/libxl_types.idl            |   4 +-
>  tools/xl/xl_parse.c                         |  12 +
>  xen/arch/arm/dom0less-build.c               |  11 +
>  xen/arch/arm/domain_build.c                 |   3 +-
>  xen/arch/arm/firmware/Kconfig               |  12 +
>  xen/arch/arm/firmware/Makefile              |   1 +
>  xen/arch/arm/firmware/scmi-proto.h          | 164 ++++
>  xen/arch/arm/firmware/scmi-shmem.c          | 112 +++
>  xen/arch/arm/firmware/scmi-shmem.h          |  45 ++
>  xen/arch/arm/firmware/scmi-smc-multiagent.c | 803 ++++++++++++++++++++
>  xen/include/public/arch-arm.h               |   3 +
>  17 files changed, 1297 insertions(+), 2 deletions(-)
>  create mode 100644 xen/arch/arm/firmware/scmi-proto.h
>  create mode 100644 xen/arch/arm/firmware/scmi-shmem.c
>  create mode 100644 xen/arch/arm/firmware/scmi-shmem.h
>  create mode 100644 xen/arch/arm/firmware/scmi-smc-multiagent.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 31dbba54bb..1b6b58cbb7 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -514,6 +514,10 @@ R:	Oleksii Moisieiev 
>  S:	Supported
>  F:	xen/arch/arm/firmware/sci.c
>  F:	xen/arch/arm/include/asm/firmware/sci.h
> +F:	xen/arch/arm/firmware/scmi-smc-multiagent.c
> +F:	xen/arch/arm/firmware/scmi-shmem.c
> +F:	xen/arch/arm/firmware/scmi-shmem.h
> +F:	xen/arch/arm/firmware/scmi-proto.h
>  
>  SEABIOS UPSTREAM
>  M:	Wei Liu 
> diff --git a/SUPPORT.md b/SUPPORT.md
> index 6a82a92189..9d7857d953 100644
> --- a/SUPPORT.md
> +++ b/SUPPORT.md
> @@ -956,6 +956,17 @@ by hwdom. Some platforms use SCMI for access to system-level resources.
>  
>      Status: Supported
>  
> +### Arm: SCMI SMC multi-agent support
> +
> +Enable support for the multi-agent configuration of the EL3 Firmware, which
> +allows Xen to provide an SCMI interface to the Domains.
> +Xen manages access permissions to the HW resources and provides an SCMI interface
> +to the Domains. Each Domain is represented as a separate Agent, which can
> +communicate with EL3 Firmware using a dedicated shared memory region, and
> +notifications are passed through by Xen.
> +
> +    Status, ARM64: Tech Preview
> +
>  ### ARM: Guest PSCI support
>  
>  Emulated PSCI interface exposed to guests. We support all mandatory
> diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
> index 8f1a203e21..f6cf2d4567 100644
> --- a/docs/man/xl.cfg.5.pod.in
> +++ b/docs/man/xl.cfg.5.pod.in
> @@ -3103,8 +3103,21 @@ single SCMI OSPM agent support.
>  Should be used together with B Xen command line
>  option.
>  
> +=item B
> +
> +Enables ARM SCMI SMC multi-agent support for the guest by enabling SCMI over
> +SMC calls forwarding from domain to the EL3 firmware (like Trusted Firmware-A)
> +with a multi SCMI OSPM agent support. The SCMI B should be
> +specified for the guest.
> +
>  =back
>  
> +=item B
> +
> +Specifies a non-zero ARM SCI agent id for the guest. This option is mandatory
> +if the SCMI SMC support is enabled for the guest. The agent ids of domains
> +existing on a single host must be unique and in the range [1..255].

Why is the option mandatory if the commit description explains that the
agent_id can be probed by Xen? In the commit message, the mandatory
field is smc-id instead?

I guess it is because we expect Xen to have already the agent_id->smc-id
mapping and we expect the agent_id to be easier to remember and to write
in the config file?


>  =back
>  
>  =back
> diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-tree/booting.txt
> index 8ea11c1551..10a99cfd15 100644
> --- a/docs/misc/arm/device-tree/booting.txt
> +++ b/docs/misc/arm/device-tree/booting.txt
> @@ -322,6 +322,20 @@ with the following properties:
>      Should be used together with scmi_smc_passthrough Xen command line
>      option.
>  
> +    - "scmi_smc_multiagent"
> +
> +    Enables ARM SCMI SMC multi-agent support for the guest by enabling SCMI over
> +    SMC calls forwarding from domain to the EL3 firmware (like ARM
> +    Trusted Firmware-A) with a multi SCMI OSPM agent support.
> +    The SCMI agent_id should be specified for the guest with "xen,sci_agent_id"
> +    property.
> +
> +- "xen,sci_agent_id"
> +
> +    Specifies a non-zero ARM SCI agent id for the guest. This option is
> +    mandatory if the SCMI SMC "scmi_smc_multiagent" support is enabled for
> +    the guest. The agent ids of guest must be unique and in the range [1..255].

same question


>  Under the "xen,domain" compatible node, one or more sub-nodes are present
>  for the DomU kernel and ramdisk.
>  
> @@ -824,3 +838,77 @@ The automatically allocated static shared memory will get mapped at
>  0x80000000 in DomU1 guest physical address space, and at 0x90000000 in DomU2
>  guest physical address space. DomU1 is explicitly defined as the owner domain,
>  and DomU2 is the borrower domain.
> +
> +SCMI SMC multi-agent support
> +============================
> +
> +For enabling the ARM SCMI SMC multi-agent support (enabled by CONFIG_SCMI_SMC_MA)
> +the Xen specific SCMI Agent's configuration shell be provided in the Host DT

shall


> +according to the SCMI compliant EL3 Firmware specification with
> +ARM SMC/HVC transport using property "scmi-secondary-agents" placed in "xen,config"
> +node under "chosen" node:
> +
> +- scmi-secondary-agents
> +
> +    Defines a set of SCMI agents configuration supported by SCMI EL3 FW and
> +    available for Xen. Each Agent defined as triple consisting of:
> +    SMC/HVC function_id assigned for the agent transport ("arm,smc-id"),
> +    phandle to SCMI SHM assigned for the agent transport ("arm,scmi-shmem"),
> +    SCMI agent_id (optional) if not set - Xen will determine Agent ID for
> +    each provided channel using BASE_DISCOVER_AGENT message.
> +
> +As an example:
> +
> +/{
> +chosen {
> +    xen,config {

same comment about node name and compatible string


> +        scmi_shm_1: sram@47ff1000 {
> +                compatible = "arm,scmi-shmem";
> +                reg = <0x0 0x47ff1000 0x0 0x1000>;
> +        };
> +        scmi_shm_2: sram@47ff2000 {
> +                compatible = "arm,scmi-shmem";
> +                reg = <0x0 0x47ff2000 0x0 0x1000>;
> +        };
> +        scmi_shm_3: sram@47ff3000 {
> +                compatible = "arm,scmi-shmem";
> +                reg = <0x0 0x47ff3000 0x0 0x1000>;
> +        };
> +        scmi_shm_3: sram@47ff4000 {
> +                compatible = "arm,scmi-shmem";
> +                reg = <0x0 0x47ff4000 0x0 0x1000>;
> +        };
> +        scmi-secondary-agents = <
> +            0x82000003 &scmi_shm_1 1
> +            0x82000004 &scmi_shm_2 2
> +            0x82000005 &scmi_shm_3 3
> +            0x82000006 &scmi_shm_4 4>;
> +            #scmi-secondary-agents-cells = <3>;
> +        };
> +    };
> +};
> +
> +- #scmi-secondary-agents-cells
> +
> +    Defines whether Agent_id is set in the "scmi-secondary-agents" property.
> +    Possible values are: 2, 3.
> +    When set to 3 (the default), expect agent_id to be present in the secondary
> +    agents list.
> +    When set to 2, agent_id will be discovered for each channel using
> +    BASE_DISCOVER_AGENT message.
> +
> +
> +Example:
> +
> +/{
> +chosen {
> +    xen,config {
> +        scmi-secondary-agents = <
> +            0x82000003 &scmi_shm_1
> +            0x82000004 &scmi_shm_2
> +            0x82000005 &scmi_shm_3
> +            0x82000006 &scmi_shm_4>;
> +            #scmi-secondary-agents-cells = <2>;


In the example we should also add Xen own nodes like you did in the
commit message.


> +        };
> +    };
> +};
> diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
> index 7a1f723e63..5a1c1e072c 100644
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -1105,6 +1105,15 @@ which serves as Driver domain. The SCMI will be disabled for Dom0/hwdom and
>  SCMI nodes removed from Dom0/hwdom device tree.
>  (for example, thin Dom0 with Driver domain use-case).
>  
> +### dom0_scmi_agent_id (ARM)
> +> `= `
> +
> +The option is available when `CONFIG_SCMI_SMC_MA` is compiled in, and allows to
> +enable SCMI functionality for Dom0 by specifying a non-zero ARM SCMI agent id.
> +The SCMI will be disabled for Dom0 if this option is not specified
> +(for example, thin Dom0 or dom0less use-cases).
> +The agent ids of domains existing on a single host must be unique.

Same question about agent id vs. smc-id


>  ### dtuart (ARM)
>  > `= path [:options]`
>  
> diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c
> index e4407d6e3f..be0e6263ae 100644
> --- a/tools/libs/light/libxl_arm.c
> +++ b/tools/libs/light/libxl_arm.c
> @@ -240,6 +240,10 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
>      case LIBXL_ARM_SCI_TYPE_SCMI_SMC:
>          config->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC;
>          break;
> +    case LIBXL_ARM_SCI_TYPE_SCMI_SMC_MULTIAGENT:
> +        config->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA;
> +        config->arch.arm_sci_agent_id = d_config->b_info.arch_arm.arm_sci.agent_id;
> +        break;
>      default:
>          LOG(ERROR, "Unknown ARM_SCI type %d",
>              d_config->b_info.arch_arm.arm_sci.type);
> diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl
> index c8bc0f8521..da7f87cd0c 100644
> --- a/tools/libs/light/libxl_types.idl
> +++ b/tools/libs/light/libxl_types.idl
> @@ -553,11 +553,13 @@ libxl_sve_type = Enumeration("sve_type", [
>  
>  libxl_arm_sci_type = Enumeration("arm_sci_type", [
>      (0, "none"),
> -    (1, "scmi_smc")
> +    (1, "scmi_smc"),
> +    (2, "scmi_smc_multiagent")
>      ], init_val = "LIBXL_ARM_SCI_TYPE_NONE")
>  
>  libxl_arm_sci = Struct("arm_sci", [
>      ("type", libxl_arm_sci_type),
> +    ("agent_id", uint8)
>      ])
>  
>  libxl_rdm_reserve = Struct("rdm_reserve", [
> diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
> index 68d2ebeb9f..4c05b20c06 100644
> --- a/tools/xl/xl_parse.c
> +++ b/tools/xl/xl_parse.c
> @@ -1306,6 +1306,18 @@ static int parse_arm_sci_config(XLU_Config *cfg, libxl_arm_sci *arm_sci,
>              }
>          }
>  
> +        if (MATCH_OPTION("agent_id", ptr, oparg)) {
> +            unsigned long val = parse_ulong(oparg);
> +
> +            if (!val || val > 255) {
> +                fprintf(stderr, "An invalid ARM_SCI agent_id specified (%lu). Valid range [1..255]\n",
> +                        val);
> +                ret = ERROR_INVAL;
> +                goto parse_error;
> +            }
> +            arm_sci->agent_id = val;
> +        }
> +
>          ptr = strtok(NULL, ",");
>      }
>  
> diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
> index d28143f98b..6ca17b0ce6 100644
> --- a/xen/arch/arm/dom0less-build.c
> +++ b/xen/arch/arm/dom0less-build.c
> @@ -299,6 +299,17 @@ int __init domu_dt_sci_parse(struct dt_device_node *node,
>          d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
>      else if ( !strcmp(sci_type, "scmi_smc") )
>          d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC;
> +    else if ( !strcmp(sci_type, "scmi_smc_multiagent") )
> +    {
> +        uint32_t agent_id = 0;
> +
> +        if ( !dt_property_read_u32(node, "xen,sci_agent_id", &agent_id) ||
> +             !agent_id )
> +            return -EINVAL;
> +
> +        d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA;
> +        d_cfg->arch.arm_sci_agent_id = agent_id;
> +    }
>      else
>      {
>          printk(XENLOG_ERR "xen,sci_type in not valid (%s) for domain %s\n",
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index 92039cf213..ea13e374a0 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -508,7 +508,8 @@ static int __init write_properties(struct domain *d, struct kernel_info *kinfo,
>                   dt_property_name_is_equal(prop, "linux,uefi-mmap-start") ||
>                   dt_property_name_is_equal(prop, "linux,uefi-mmap-size") ||
>                   dt_property_name_is_equal(prop, "linux,uefi-mmap-desc-size") ||
> -                 dt_property_name_is_equal(prop, "linux,uefi-mmap-desc-ver"))
> +                 dt_property_name_is_equal(prop, "linux,uefi-mmap-desc-ver") ||
> +                 dt_property_name_is_equal(prop, "xen,config") )
>                  continue;

please match by compatible string rather than by node name


>              if ( dt_property_name_is_equal(prop, "xen,dom0-bootargs") )
> diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig
> index 5c5f0880c4..972cd9b173 100644
> --- a/xen/arch/arm/firmware/Kconfig
> +++ b/xen/arch/arm/firmware/Kconfig
> @@ -29,6 +29,18 @@ config SCMI_SMC
>  	  driver domain.
>  	  Use with EL3 firmware which supports only single SCMI OSPM agent.
>  
> +config SCMI_SMC_MA
> +	bool "Enable ARM SCMI SMC multi-agent driver"
> +	depends on ARM_64
> +	select ARM_SCI
> +	help
> +	  Enables SCMI SMC/HVC multi-agent in XEN to pass SCMI requests from Domains
> +	  to EL3 firmware (TF-A) which supports multi-agent feature.
> +	  This feature allows to enable SCMI per Domain using unique SCMI agent_id,
> +	  so Domain is identified by EL3 firmware as an SCMI Agent and can access
> +	  allowed platform resources through dedicated SMC/HVC Shared memory based
> +	  transport.
> +
>  endchoice
>  
>  endmenu
> diff --git a/xen/arch/arm/firmware/Makefile b/xen/arch/arm/firmware/Makefile
> index 71bdefc24a..37927e690e 100644
> --- a/xen/arch/arm/firmware/Makefile
> +++ b/xen/arch/arm/firmware/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_ARM_SCI) += sci.o
>  obj-$(CONFIG_SCMI_SMC) += scmi-smc.o
> +obj-$(CONFIG_SCMI_SMC_MA) += scmi-shmem.o scmi-smc-multiagent.o
> diff --git a/xen/arch/arm/firmware/scmi-proto.h b/xen/arch/arm/firmware/scmi-proto.h
> new file mode 100644
> index 0000000000..e290d6630d
> --- /dev/null
> +++ b/xen/arch/arm/firmware/scmi-proto.h
> @@ -0,0 +1,164 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Arm System Control and Management Interface definitions
> + * Version 3.0 (DEN0056C)
> + *
> + * Copyright (c) 2024 EPAM Systems
> + */
> +
> +#ifndef ARM_FIRMWARE_SCMI_PROTO_H_
> +#define ARM_FIRMWARE_SCMI_PROTO_H_
> +
> +#include 
> +
> +#define SCMI_SHORT_NAME_MAX_SIZE 16
> +
> +/* SCMI status codes. See section 4.1.4 */
> +#define SCMI_SUCCESS              0
> +#define SCMI_NOT_SUPPORTED      (-1)
> +#define SCMI_INVALID_PARAMETERS (-2)
> +#define SCMI_DENIED             (-3)
> +#define SCMI_NOT_FOUND          (-4)
> +#define SCMI_OUT_OF_RANGE       (-5)
> +#define SCMI_BUSY               (-6)
> +#define SCMI_COMMS_ERROR        (-7)
> +#define SCMI_GENERIC_ERROR      (-8)
> +#define SCMI_HARDWARE_ERROR     (-9)
> +#define SCMI_PROTOCOL_ERROR     (-10)
> +
> +/* Protocol IDs */
> +#define SCMI_BASE_PROTOCOL 0x10
> +
> +/* Base protocol message IDs */
> +#define SCMI_BASE_PROTOCOL_VERSION            0x0
> +#define SCMI_BASE_PROTOCOL_ATTIBUTES          0x1
> +#define SCMI_BASE_PROTOCOL_MESSAGE_ATTRIBUTES 0x2
> +#define SCMI_BASE_DISCOVER_AGENT              0x7
> +#define SCMI_BASE_SET_DEVICE_PERMISSIONS      0x9
> +#define SCMI_BASE_RESET_AGENT_CONFIGURATION   0xB
> +
> +typedef struct scmi_msg_header {
> +    uint8_t id;
> +    uint8_t type;
> +    uint8_t protocol;
> +    uint32_t status;
> +} scmi_msg_header_t;
> +
> +/* Table 2 Message header format */
> +#define SCMI_HDR_ID    GENMASK(7, 0)
> +#define SCMI_HDR_TYPE  GENMASK(9, 8)
> +#define SCMI_HDR_PROTO GENMASK(17, 10)
> +
> +#define SCMI_FIELD_GET(_mask, _reg)                                            \
> +    ((typeof(_mask))(((_reg) & (_mask)) >> (ffs64(_mask) - 1)))

ffs64 is declared in xen/bitops.h


> +#define SCMI_FIELD_PREP(_mask, _val)                                           \
> +    (((typeof(_mask))(_val) << (ffs64(_mask) - 1)) & (_mask))
> +
> +static inline uint32_t pack_scmi_header(scmi_msg_header_t *hdr)
> +{
> +    return SCMI_FIELD_PREP(SCMI_HDR_ID, hdr->id) |
> +           SCMI_FIELD_PREP(SCMI_HDR_TYPE, hdr->type) |
> +           SCMI_FIELD_PREP(SCMI_HDR_PROTO, hdr->protocol);
> +}
> +
> +static inline void unpack_scmi_header(uint32_t msg_hdr, scmi_msg_header_t *hdr)
> +{
> +    hdr->id = SCMI_FIELD_GET(SCMI_HDR_ID, msg_hdr);
> +    hdr->type = SCMI_FIELD_GET(SCMI_HDR_TYPE, msg_hdr);
> +    hdr->protocol = SCMI_FIELD_GET(SCMI_HDR_PROTO, msg_hdr);
> +}
> +
> +static inline int scmi_to_xen_errno(int scmi_status)
> +{
> +    if ( scmi_status == SCMI_SUCCESS )
> +        return 0;
> +
> +    switch ( scmi_status )
> +    {
> +    case SCMI_NOT_SUPPORTED:
> +        return -EOPNOTSUPP;
> +    case SCMI_INVALID_PARAMETERS:
> +        return -EINVAL;
> +    case SCMI_DENIED:
> +        return -EACCES;
> +    case SCMI_NOT_FOUND:
> +        return -ENOENT;
> +    case SCMI_OUT_OF_RANGE:
> +        return -ERANGE;
> +    case SCMI_BUSY:
> +        return -EBUSY;
> +    case SCMI_COMMS_ERROR:
> +        return -ENOTCONN;
> +    case SCMI_GENERIC_ERROR:
> +        return -EIO;
> +    case SCMI_HARDWARE_ERROR:
> +        return -ENXIO;
> +    case SCMI_PROTOCOL_ERROR:
> +        return -EBADMSG;
> +    default:
> +        return -EINVAL;
> +    }
> +}
> +
> +/* PROTOCOL_VERSION */
> +#define SCMI_VERSION_MINOR GENMASK(15, 0)
> +#define SCMI_VERSION_MAJOR GENMASK(31, 16)
> +
> +struct scmi_msg_prot_version_p2a {
> +    uint32_t version;
> +} __packed;
> +
> +/* BASE PROTOCOL_ATTRIBUTES */
> +#define SCMI_BASE_ATTR_NUM_PROTO GENMASK(7, 0)
> +#define SCMI_BASE_ATTR_NUM_AGENT GENMASK(15, 8)
> +
> +struct scmi_msg_base_attributes_p2a {
> +    uint32_t attributes;
> +} __packed;
> +
> +/*
> + * BASE_DISCOVER_AGENT
> + */
> +#define SCMI_BASE_AGENT_ID_OWN 0xFFFFFFFF
> +
> +struct scmi_msg_base_discover_agent_a2p {
> +    uint32_t agent_id;
> +} __packed;
> +
> +struct scmi_msg_base_discover_agent_p2a {
> +    uint32_t agent_id;
> +    char name[SCMI_SHORT_NAME_MAX_SIZE];
> +} __packed;
> +
> +/*
> + * BASE_SET_DEVICE_PERMISSIONS
> + */
> +#define SCMI_BASE_DEVICE_ACCESS_ALLOW           BIT(0, UL)
> +
> +struct scmi_msg_base_set_device_permissions_a2p {
> +    uint32_t agent_id;
> +    uint32_t device_id;
> +    uint32_t flags;
> +} __packed;
> +
> +/*
> + * BASE_RESET_AGENT_CONFIGURATION
> + */
> +#define SCMI_BASE_AGENT_PERMISSIONS_RESET       BIT(0, UL)
> +
> +struct scmi_msg_base_reset_agent_cfg_a2p {
> +    uint32_t agent_id;
> +    uint32_t flags;
> +} __packed;
> +
> +#endif /* ARM_FIRMWARE_SCMI_PROTO_H_ */
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * tab-width: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/firmware/scmi-shmem.c b/xen/arch/arm/firmware/scmi-shmem.c
> new file mode 100644
> index 0000000000..8fc8ca356b
> --- /dev/null
> +++ b/xen/arch/arm/firmware/scmi-shmem.c
> @@ -0,0 +1,112 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * SCI SCMI multi-agent driver, using SMC/HVC shmem as transport.
> + *
> + * Oleksii Moisieiev 
> + * Copyright (c) 2025 EPAM Systems
> + */
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#include 
> +#include 
> +#include 
> +
> +#include "scmi-proto.h"
> +#include "scmi-shmem.h"
> +
> +static inline int
> +shmem_channel_is_free(const volatile struct scmi_shared_mem __iomem *shmem)
> +{
> +    return (readl(&shmem->channel_status) &
> +            SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE) ? 0 : -EBUSY;
> +}
> +
> +int shmem_put_message(volatile struct scmi_shared_mem __iomem *shmem,
> +                      scmi_msg_header_t *hdr, void *data, int len)
> +{
> +    int ret;
> +
> +    if ( (len + sizeof(shmem->msg_header)) > SCMI_SHMEM_MAPPED_SIZE )

shouldn't this take into account offsetof(struct scmi_shared_mem,
msg_header) ?




> +    {
> +        printk(XENLOG_ERR "scmi: Wrong size of smc message. Data is invalid\n");
> +        return -EINVAL;
> +    }
> +
> +    ret = shmem_channel_is_free(shmem);
> +    if ( ret )
> +        return ret;
> +
> +    writel_relaxed(0x0, &shmem->channel_status);
> +    /* Writing 0x0 right now, but "shmem"_FLAG_INTR_ENABLED can be set */
> +    writel_relaxed(0x0, &shmem->flags);
> +    writel_relaxed(sizeof(shmem->msg_header) + len, &shmem->length);
> +    writel(pack_scmi_header(hdr), &shmem->msg_header);
> +
> +    if ( len > 0 && data )
> +        __memcpy_toio(shmem->msg_payload, data, len);
> +
> +    return 0;
> +}
> +
> +int shmem_get_response(const volatile struct scmi_shared_mem __iomem *shmem,
> +                       scmi_msg_header_t *hdr, void *data, int len)
> +{
> +    int recv_len;
> +    int ret;
> +    int pad = sizeof(hdr->status);
> +
> +    if ( len >= SCMI_SHMEM_MAPPED_SIZE - sizeof(shmem) )

should this be sizeof(*shmem) ?


> +    {
> +        printk(XENLOG_ERR
> +               "scmi: Wrong size of input smc message. Data may be invalid\n");
> +        return -EINVAL;
> +    }
> +
> +    ret = shmem_channel_is_free(shmem);
> +    if ( ret )
> +        return ret;
> +
> +    recv_len = readl(&shmem->length) - sizeof(shmem->msg_header);
> +
> +    if ( recv_len < 0 )
> +    {
> +        printk(XENLOG_ERR
> +               "scmi: Wrong size of smc message. Data may be invalid\n");
> +        return -EINVAL;
> +    }
> +
> +    unpack_scmi_header(readl(&shmem->msg_header), hdr);
> +
> +    hdr->status = readl(&shmem->msg_payload);
> +    recv_len = recv_len > pad ? recv_len - pad : 0;
> +
> +    ret = scmi_to_xen_errno(hdr->status);
> +    if ( ret )
> +    {
> +        printk(XENLOG_DEBUG "scmi: Error received: %d\n", ret);
> +        return ret;
> +    }
> +
> +    if ( recv_len > len )
> +    {
> +        printk(XENLOG_ERR
> +               "scmi: Not enough buffer for message %d, expecting %d\n",
> +               recv_len, len);
> +        return -EINVAL;
> +    }
> +
> +    if ( recv_len > 0 )
> +        __memcpy_fromio(data, shmem->msg_payload + pad, recv_len);
> +
> +    return 0;
> +}
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * tab-width: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/firmware/scmi-shmem.h b/xen/arch/arm/firmware/scmi-shmem.h
> new file mode 100644
> index 0000000000..7313cb6b26
> --- /dev/null
> +++ b/xen/arch/arm/firmware/scmi-shmem.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Arm System Control and Management Interface definitions
> + * Version 3.0 (DEN0056C)
> + * Shared Memory based Transport
> + *
> + * Copyright (c) 2024 EPAM Systems
> + */
> +
> +#ifndef ARM_FIRMWARE_SCMI_SHMEM_H_
> +#define ARM_FIRMWARE_SCMI_SHMEM_H_
> +
> +#include 
> +
> +#define SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE  BIT(0, UL)
> +#define SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR BIT(1, UL)
> +
> +struct scmi_shared_mem {
> +    uint32_t reserved;
> +    uint32_t channel_status;
> +    uint32_t reserved1[2];
> +    uint32_t flags;
> +    uint32_t length;
> +    uint32_t msg_header;
> +    uint8_t msg_payload[];
> +};
> +
> +#define SCMI_SHMEM_MAPPED_SIZE PAGE_SIZE
> +
> +int shmem_put_message(volatile struct scmi_shared_mem __iomem *shmem,
> +                      scmi_msg_header_t *hdr, void *data, int len);
> +
> +int shmem_get_response(const volatile struct scmi_shared_mem __iomem *shmem,
> +                       scmi_msg_header_t *hdr, void *data, int len);
> +#endif /* ARM_FIRMWARE_SCMI_SHMEM_H_ */
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * tab-width: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/firmware/scmi-smc-multiagent.c b/xen/arch/arm/firmware/scmi-smc-multiagent.c
> new file mode 100644
> index 0000000000..9f839147d4
> --- /dev/null
> +++ b/xen/arch/arm/firmware/scmi-smc-multiagent.c
> @@ -0,0 +1,803 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * SCI SCMI multi-agent driver, using SMC/HVC shmem as transport.
> + *
> + * Oleksii Moisieiev 
> + * Copyright (c) 2025 EPAM Systems
> + */
> +
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +#include "scmi-proto.h"
> +#include "scmi-shmem.h"
> +
> +#define SCMI_AGENT_ID_INVALID 0xFF
> +
> +static uint8_t __initdata opt_dom0_scmi_agent_id = SCMI_AGENT_ID_INVALID;
> +integer_param("dom0_scmi_agent_id", opt_dom0_scmi_agent_id);
> +
> +#define SCMI_SECONDARY_AGENTS "scmi-secondary-agents"
> +
> +struct scmi_channel {
> +    uint32_t agent_id;
> +    uint32_t func_id;
> +    domid_t domain_id;
> +    uint64_t paddr;
> +    uint64_t len;

doesn't seem to be used


> +    struct scmi_shared_mem __iomem *shmem;
> +    spinlock_t lock;
> +    struct list_head list;
> +};
> +
> +struct scmi_data {
> +    struct list_head channel_list;
> +    spinlock_t channel_list_lock;
> +    uint32_t func_id;
> +    bool initialized;
> +    uint32_t shmem_phandle;
> +    uint32_t hyp_channel_agent_id;
> +    struct dt_device_node *dt_dev;
> +};
> +
> +static struct scmi_data scmi_data;
> +
> +static int send_smc_message(struct scmi_channel *chan_info,
> +                            scmi_msg_header_t *hdr, void *data, int len)
> +{
> +    struct arm_smccc_res resp;
> +    int ret;
> +
> +    ret = shmem_put_message(chan_info->shmem, hdr, data, len);
> +    if ( ret )
> +        return ret;
> +
> +    arm_smccc_1_1_smc(chan_info->func_id, 0, 0, 0, 0, 0, 0, 0, &resp);
> +
> +    if ( resp.a0 == ARM_SMCCC_INVALID_PARAMETER )
> +        return -EINVAL;
> +
> +    if ( resp.a0 )
> +        return -EOPNOTSUPP;
> +
> +    return 0;
> +}
> +
> +static int do_smc_xfer(struct scmi_channel *chan_info, scmi_msg_header_t *hdr,
> +                       void *tx_data, int tx_size, void *rx_data, int rx_size)
> +{
> +    int ret = 0;
> +
> +    ASSERT(chan_info && chan_info->shmem);
> +
> +    if ( !hdr )
> +        return -EINVAL;
> +
> +    spin_lock(&chan_info->lock);
> +
> +    printk(XENLOG_DEBUG
> +           "scmi: agent_id = %d msg_id = %x type = %d, proto = %x\n",
> +           chan_info->agent_id, hdr->id, hdr->type, hdr->protocol);
> +
> +    ret = send_smc_message(chan_info, hdr, tx_data, tx_size);
> +    if ( ret )
> +        goto clean;
> +
> +    ret = shmem_get_response(chan_info->shmem, hdr, rx_data, rx_size);
> +
> +clean:
> +    printk(XENLOG_DEBUG
> +           "scmi: get smc response agent_id = %d msg_id = %x proto = %x res=%d\n",
> +           chan_info->agent_id, hdr->id, hdr->protocol, ret);
> +
> +    spin_unlock(&chan_info->lock);
> +
> +    return ret;
> +}
> +
> +static struct scmi_channel *get_channel_by_id(uint32_t agent_id)
> +{
> +    struct scmi_channel *curr;
> +    bool found = false;
> +
> +    spin_lock(&scmi_data.channel_list_lock);
> +    list_for_each_entry(curr, &scmi_data.channel_list, list)
> +    {
> +        if ( curr->agent_id == agent_id )
> +        {
> +            found = true;
> +            break;
> +        }
> +    }
> +
> +    spin_unlock(&scmi_data.channel_list_lock);
> +    if ( found )
> +        return curr;
> +
> +    return NULL;
> +}
> +
> +static struct scmi_channel *acquire_scmi_channel(struct domain *d,
> +                                                 uint32_t agent_id)
> +{
> +    struct scmi_channel *curr;
> +    struct scmi_channel *ret = ERR_PTR(-ENOENT);
> +
> +    spin_lock(&scmi_data.channel_list_lock);
> +    list_for_each_entry(curr, &scmi_data.channel_list, list)
> +    {
> +        if ( curr->agent_id == agent_id )
> +        {
> +            if ( curr->domain_id != DOMID_INVALID )
> +            {
> +                ret = ERR_PTR(-EEXIST);
> +                break;
> +            }
> +
> +            curr->domain_id = d->domain_id;
> +            ret = curr;
> +            break;
> +        }
> +    }
> +
> +    spin_unlock(&scmi_data.channel_list_lock);
> +
> +    return ret;
> +}
> +
> +static void relinquish_scmi_channel(struct scmi_channel *channel)
> +{
> +    ASSERT(channel != NULL);
> +
> +    spin_lock(&scmi_data.channel_list_lock);
> +    channel->domain_id = DOMID_INVALID;
> +    spin_unlock(&scmi_data.channel_list_lock);
> +}
> +
> +static int map_channel_memory(struct scmi_channel *channel)
> +{
> +    ASSERT(channel && channel->paddr);
> +    channel->shmem = ioremap_nocache(channel->paddr, SCMI_SHMEM_MAPPED_SIZE);
> +    if ( !channel->shmem )
> +        return -ENOMEM;
> +
> +    channel->shmem->channel_status = SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE;
> +    printk(XENLOG_DEBUG "scmi: Got shmem %lx after vmap %p\n", channel->paddr,
> +           channel->shmem);
> +
> +    return 0;
> +}
> +
> +static void unmap_channel_memory(struct scmi_channel *channel)
> +{
> +    ASSERT(channel && channel->shmem);
> +    iounmap(channel->shmem);
> +    channel->shmem = NULL;
> +}
> +
> +static struct scmi_channel *smc_create_channel(uint32_t agent_id,
> +                                               uint32_t func_id, uint64_t addr)
> +{
> +    struct scmi_channel *channel;
> +
> +    channel = get_channel_by_id(agent_id);
> +    if ( channel )
> +        return ERR_PTR(EEXIST);
> +
> +    channel = xmalloc(struct scmi_channel);
> +    if ( !channel )
> +        return ERR_PTR(ENOMEM);
> +
> +    spin_lock_init(&channel->lock);
> +    channel->agent_id = agent_id;
> +    channel->func_id = func_id;
> +    channel->domain_id = DOMID_INVALID;
> +    channel->shmem = NULL;
> +    channel->paddr = addr;
> +    list_add_tail(&channel->list, &scmi_data.channel_list);
> +    return channel;
> +}
> +
> +static void free_channel_list(void)
> +{
> +    struct scmi_channel *curr, *_curr;
> +
> +    list_for_each_entry_safe(curr, _curr, &scmi_data.channel_list, list)
> +    {
> +        list_del(&curr->list);
> +        xfree(curr);
> +    }
> +}
> +
> +static int __init
> +scmi_dt_read_hyp_channel_addr(struct dt_device_node *scmi_node, u64 *addr,
> +                              u64 *size)
> +{
> +    struct dt_device_node *shmem_node;
> +    const __be32 *prop;
> +
> +    prop = dt_get_property(scmi_node, "shmem", NULL);
> +    if ( !prop )
> +        return -EINVAL;
> +
> +    shmem_node = dt_find_node_by_phandle(be32_to_cpu(*prop));
> +    if ( IS_ERR_OR_NULL(shmem_node) )
> +    {
> +        printk(XENLOG_ERR
> +               "scmi: Device tree error, can't parse reserved memory %ld\n",
> +               PTR_ERR(shmem_node));
> +        return PTR_ERR(shmem_node);
> +    }
> +
> +    return dt_device_get_address(shmem_node, 0, addr, size);
> +}
> +
> +/*
> + * Handle Dom0 SCMI specific DT nodes
> + *
> + * Make a decision on copying SCMI specific nodes into Dom0 device tree.
> + * For SCMI multi-agent case:
> + * - shmem nodes will not be copied and generated instead if SCMI
> + *   is enabled for Dom0
> + * - scmi node will be copied if SCMI is enabled for Dom0
> + */
> +static bool scmi_dt_handle_node(struct domain *d, struct dt_device_node *node)
> +{
> +    static const struct dt_device_match shmem_matches[] __initconst = {
> +        DT_MATCH_COMPATIBLE("arm,scmi-shmem"),
> +        { /* sentinel */ },
> +    };
> +    static const struct dt_device_match scmi_matches[] __initconst = {
> +        DT_MATCH_PATH("/firmware/scmi"),
> +        { /* sentinel */ },
> +    };
> +
> +    if ( !scmi_data.initialized )
> +        return false;
> +
> +    /* skip scmi shmem node for dom0 if scmi not enabled */
> +    if ( dt_match_node(shmem_matches, node) && !sci_domain_is_enabled(d) )
> +    {
> +        dt_dprintk("  Skip scmi shmem node\n");
> +        return true;
> +    }
> +
> +    /* drop scmi if not enabled */
> +    if ( dt_match_node(scmi_matches, node) && !sci_domain_is_enabled(d) )
> +    {
> +        dt_dprintk("  Skip scmi node\n");
> +        return true;
> +    }
> +
> +    return false;
> +}
> +
> +static int scmi_assign_device(uint32_t agent_id, uint32_t device_id,
> +                              uint32_t flags)
> +{
> +    struct scmi_msg_base_set_device_permissions_a2p tx;
> +    struct scmi_channel *channel;
> +    scmi_msg_header_t hdr;
> +
> +    channel = get_channel_by_id(scmi_data.hyp_channel_agent_id);
> +    if ( !channel )
> +        return -EINVAL;
> +
> +    hdr.id = SCMI_BASE_SET_DEVICE_PERMISSIONS;
> +    hdr.type = 0;
> +    hdr.protocol = SCMI_BASE_PROTOCOL;
> +
> +    tx.agent_id = agent_id;
> +    tx.device_id = device_id;
> +    tx.flags = flags;
> +
> +    return do_smc_xfer(channel, &hdr, &tx, sizeof(tx), NULL, 0);
> +}
> +
> +static int scmi_dt_assign_device(struct domain *d,
> +                                 struct dt_phandle_args *ac_spec)
> +{
> +    struct scmi_channel *agent_channel;
> +    uint32_t scmi_device_id = ac_spec->args[0];
> +    int ret;
> +
> +    if ( !d->arch.sci_data )
> +        return 0;
> +
> +    /* The access-controllers is specified for DT dev, but it's not a SCMI */
> +    if ( ac_spec->np != scmi_data.dt_dev )
> +        return 0;
> +
> +    agent_channel = d->arch.sci_data;
> +
> +    spin_lock(&agent_channel->lock);
> +
> +    ret = scmi_assign_device(agent_channel->agent_id, scmi_device_id,
> +                             SCMI_BASE_DEVICE_ACCESS_ALLOW);
> +    if ( ret )
> +    {
> +        printk(XENLOG_ERR
> +               "scmi: could not assign dev for %pd agent:%d dev_id:%u (%d)",
> +               d, agent_channel->agent_id, scmi_device_id, ret);
> +    }
> +
> +    spin_unlock(&agent_channel->lock);
> +    return ret;
> +}
> +
> +static int collect_agent_id(struct scmi_channel *agent_channel)
> +{
> +    int ret;
> +    scmi_msg_header_t hdr;
> +    struct scmi_msg_base_discover_agent_p2a da_rx;
> +    struct scmi_msg_base_discover_agent_a2p da_tx;
> +
> +    ret = map_channel_memory(agent_channel);
> +    if ( ret )
> +        return ret;
> +
> +    hdr.id = SCMI_BASE_DISCOVER_AGENT;
> +    hdr.type = 0;
> +    hdr.protocol = SCMI_BASE_PROTOCOL;
> +
> +    da_tx.agent_id = agent_channel->agent_id;
> +
> +    ret = do_smc_xfer(agent_channel, &hdr, &da_tx, sizeof(da_tx), &da_rx,
> +                        sizeof(da_rx));
> +    if ( agent_channel->domain_id != DOMID_XEN )
> +        unmap_channel_memory(agent_channel);
> +    if ( ret )
> +        return ret;
> +
> +    printk(XENLOG_DEBUG "id=0x%x name=%s\n", da_rx.agent_id, da_rx.name);
> +    agent_channel->agent_id = da_rx.agent_id;
> +    return 0;
> +}
> +
> +static __init int collect_agents(struct dt_device_node *scmi_node)
> +{
> +    const struct dt_device_node *config_node;
> +    const __be32 *prop;
> +    uint32_t len;
> +    const __be32 *end;
> +    uint32_t cells_per_entry = 3; /* Default to 3 cells if property is absent. */
> +
> +    config_node = dt_find_node_by_path("/chosen/xen,config");

Please use compatible strings, not paths


> +    if ( !config_node )
> +    {
> +        printk(XENLOG_WARNING "scmi: /chosen/xen,config node not found, no agents to collect.\n");
> +        return -ENOENT;
> +    }
> +
> +    /* Check for the optional '#scmi-secondary-agents-cells' property. */
> +    if ( dt_property_read_u32(config_node, "#scmi-secondary-agents-cells",
> +                              &cells_per_entry) )
> +    {
> +        if ( cells_per_entry != 2 && cells_per_entry != 3 )
> +        {
> +            printk(XENLOG_ERR "scmi: Invalid #scmi-secondary-agents-cells value: %u\n",
> +                   cells_per_entry);
> +            return -EINVAL;
> +        }
> +    }
> +
> +    prop = dt_get_property(config_node, SCMI_SECONDARY_AGENTS, &len);
> +    if ( !prop )
> +    {
> +        /* This is not an error, as there may be no secondary agents. */
> +        printk(XENLOG_WARNING "scmi: No %s property found, no agents to collect.\n",
> +               SCMI_SECONDARY_AGENTS);
> +        return -EINVAL;

While the comment says this is not a fatal error, returning -EINVAL
leads to scmi_probe taking the error path

> +    }
> +
> +    /* Validate that the property length is a multiple of the cell size. */
> +    if ( len == 0 || len % (cells_per_entry * sizeof(uint32_t)) != 0 )
> +    {
> +        printk(XENLOG_ERR "scmi: Invalid length of %s property: %u for %u cells per entry\n",
> +               SCMI_SECONDARY_AGENTS, len, cells_per_entry);
> +        return -EINVAL;
> +    }
> +
> +    end = (const __be32 *)((const u8 *)prop + len);
> +
> +    for ( ; prop < end; )
> +    {
> +        uint32_t agent_id;
> +        uint32_t smc_id;
> +        uint32_t shmem_phandle;
> +        struct dt_device_node *node;
> +        u64 addr, size;
> +        int ret;
> +        struct scmi_channel *agent_channel;
> +
> +        smc_id = be32_to_cpu(*prop++);
> +        shmem_phandle = be32_to_cpu(*prop++);
> +
> +        if ( cells_per_entry == 3 )
> +            agent_id = be32_to_cpu(*prop++);
> +        else
> +            agent_id = SCMI_BASE_AGENT_ID_OWN;
> +
> +        node = dt_find_node_by_phandle(shmem_phandle);
> +        if ( !node )
> +        {
> +            printk(XENLOG_ERR "scmi: Could not find shmem node for agent %u\n",
> +                   agent_id);
> +            return -EINVAL;
> +        }
> +
> +        ret = dt_device_get_address(node, 0, &addr, &size);
> +        if ( ret )
> +        {
> +            printk(XENLOG_ERR
> +                   "scmi: Could not read shmem address for agent %u: %d\n",
> +                   agent_id, ret);
> +            return ret;

why no "goto error" ?

> +        }
> +
> +        if ( !IS_ALIGNED(size, SCMI_SHMEM_MAPPED_SIZE) )

should we also check that size % SCMI_SHMEM_MAPPED_SIZE == 0 ?


> +        {
> +            printk(XENLOG_ERR "scmi: shmem memory is not aligned\n");
> +            return -EINVAL;
> +        }
> +
> +        agent_channel = smc_create_channel(agent_id, smc_id, addr);
> +        if ( IS_ERR(agent_channel) )
> +        {
> +            printk(XENLOG_ERR "scmi: Could not create channel for agent %u: %ld\n",
> +                   agent_id, PTR_ERR(agent_channel));
> +            return PTR_ERR(agent_channel);
> +        }
> +
> +        if ( cells_per_entry == 2 )
> +        {
> +            ret = collect_agent_id(agent_channel);
> +            if ( ret )
> +                return ret;
> +        }
> +
> +        printk(XENLOG_DEBUG "scmi: Agent %u SMC %X addr %lx\n", agent_channel->agent_id,
> +               smc_id, (unsigned long)addr);
> +    }
> +
> +    return 0;
> +}
> +
> +static int scmi_domain_init(struct domain *d,
> +                            struct xen_domctl_createdomain *config)
> +{
> +    struct scmi_channel *channel;
> +    int ret;
> +
> +    if ( !scmi_data.initialized )
> +        return 0;
> +
> +    /*
> +     * Special case for Dom0 - the SCMI support is enabled basing on
> +     * "dom0_sci_agent_id" Xen command line parameter
> +     */
> +    if ( is_hardware_domain(d) )
> +    {
> +        if ( opt_dom0_scmi_agent_id != SCMI_AGENT_ID_INVALID )
> +        {
> +            config->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA;
> +            config->arch.arm_sci_agent_id = opt_dom0_scmi_agent_id;
> +        }
> +        else
> +            config->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
> +    }
> +
> +    if ( config->arch.arm_sci_type == XEN_DOMCTL_CONFIG_ARM_SCI_NONE )
> +        return 0;
> +
> +    channel = acquire_scmi_channel(d, config->arch.arm_sci_agent_id);
> +    if ( IS_ERR(channel) )
> +    {
> +        printk(XENLOG_ERR
> +               "scmi: Failed to acquire SCMI channel for agent_id %u: %ld\n",
> +               config->arch.arm_sci_agent_id, PTR_ERR(channel));
> +        return PTR_ERR(channel);
> +    }
> +
> +    printk(XENLOG_INFO
> +           "scmi: Acquire channel id = 0x%x, domain_id = %d paddr = 0x%lx\n",
> +           channel->agent_id, channel->domain_id, channel->paddr);
> +
> +    /*
> +     * Dom0 (if present) needs to have an access to the guest memory range
> +     * to satisfy iomem_access_permitted() check in XEN_DOMCTL_iomem_permission
> +     * domctl.
> +     */
> +    if ( hardware_domain && !is_hardware_domain(d) )
> +    {
> +        ret = iomem_permit_access(hardware_domain, paddr_to_pfn(channel->paddr),
> +                                  paddr_to_pfn(channel->paddr + PAGE_SIZE - 1));
> +        if ( ret )
> +            goto error;
> +    }
> +
> +    d->arch.sci_data = channel;
> +    d->arch.sci_enabled = true;
> +
> +    return 0;
> +
> +error:
> +    relinquish_scmi_channel(channel);
> +    return ret;
> +}
> +
> +int scmi_domain_sanitise_config(struct xen_domctl_createdomain *config)
> +{
> +    if ( config->arch.arm_sci_type != XEN_DOMCTL_CONFIG_ARM_SCI_NONE &&
> +         config->arch.arm_sci_type != XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA )
> +    {
> +        dprintk(XENLOG_INFO, "scmi: Unsupported ARM_SCI type\n");
> +        return -EINVAL;
> +    }
> +    else if ( config->arch.arm_sci_type ==
> +              XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA &&
> +              config->arch.arm_sci_agent_id == 0 )
> +    {
> +        dprintk(XENLOG_INFO,
> +                "scmi: A zero ARM SCMI agent_id is not supported\n");
> +        return -EINVAL;
> +    }
> +
> +    return 0;
> +}
> +
> +static int scmi_relinquish_resources(struct domain *d)
> +{
> +    int ret;
> +    struct scmi_channel *channel, *agent_channel;
> +    scmi_msg_header_t hdr;
> +    struct scmi_msg_base_reset_agent_cfg_a2p tx;
> +
> +    if ( !d->arch.sci_data )
> +        return 0;
> +
> +    agent_channel = d->arch.sci_data;
> +
> +    spin_lock(&agent_channel->lock);
> +    tx.agent_id = agent_channel->agent_id;
> +    spin_unlock(&agent_channel->lock);
> +
> +    channel = get_channel_by_id(scmi_data.hyp_channel_agent_id);
> +    if ( !channel )
> +    {
> +        printk(XENLOG_ERR
> +               "scmi: Unable to get Hypervisor scmi channel for domain %d\n",
> +               d->domain_id);
> +        return -EINVAL;
> +    }
> +
> +    hdr.id = SCMI_BASE_RESET_AGENT_CONFIGURATION;
> +    hdr.type = 0;
> +    hdr.protocol = SCMI_BASE_PROTOCOL;
> +
> +    tx.flags = 0;
> +
> +    ret = do_smc_xfer(channel, &hdr, &tx, sizeof(tx), NULL, 0);
> +    if ( ret == -EOPNOTSUPP )
> +        return 0;
> +
> +    return ret;
> +}
> +
> +static void scmi_domain_destroy(struct domain *d)
> +{
> +    struct scmi_channel *channel;
> +
> +    if ( !d->arch.sci_data )
> +        return;
> +
> +    channel = d->arch.sci_data;
> +    spin_lock(&channel->lock);
> +
> +    relinquish_scmi_channel(channel);
> +    printk(XENLOG_DEBUG "scmi: Free domain %d\n", d->domain_id);
> +
> +    d->arch.sci_data = NULL;
> +    d->arch.sci_enabled = true;

Should this be false?


> +    spin_unlock(&channel->lock);
> +}
> +
> +static bool scmi_handle_call(struct cpu_user_regs *regs)
> +{
> +    uint32_t fid = (uint32_t)get_user_reg(regs, 0);
> +    struct scmi_channel *agent_channel;
> +    struct domain *d = current->domain;
> +    struct arm_smccc_res resp;
> +    bool res = false;
> +
> +    if ( !sci_domain_is_enabled(d) )
> +        return false;
> +
> +    agent_channel = d->arch.sci_data;
> +    spin_lock(&agent_channel->lock);
> +
> +    if ( agent_channel->func_id != fid )
> +    {
> +        res = false;
> +        goto unlock;
> +    }
> +
> +    arm_smccc_1_1_smc(fid,
> +                      get_user_reg(regs, 1),
> +                      get_user_reg(regs, 2),
> +                      get_user_reg(regs, 3),
> +                      get_user_reg(regs, 4),
> +                      get_user_reg(regs, 5),
> +                      get_user_reg(regs, 6),
> +                      get_user_reg(regs, 7),
> +                      &resp);
> +
> +    set_user_reg(regs, 0, resp.a0);
> +    set_user_reg(regs, 1, resp.a1);
> +    set_user_reg(regs, 2, resp.a2);
> +    set_user_reg(regs, 3, resp.a3);
> +    res = true;
> +unlock:
> +    spin_unlock(&agent_channel->lock);
> +
> +    return res;
> +}
> +
> +static const struct sci_mediator_ops scmi_ops = {
> +    .domain_init = scmi_domain_init,
> +    .domain_destroy = scmi_domain_destroy,
> +    .relinquish_resources = scmi_relinquish_resources,
> +    .handle_call = scmi_handle_call,
> +    .dom0_dt_handle_node = scmi_dt_handle_node,
> +    .domain_sanitise_config = scmi_domain_sanitise_config,
> +    .assign_dt_device = scmi_dt_assign_device,
> +};
> +
> +static int __init scmi_check_smccc_ver(void)
> +{
> +    if ( smccc_ver < ARM_SMCCC_VERSION_1_1 )
> +    {
> +        printk(XENLOG_WARNING
> +               "scmi: No SMCCC 1.1 support, SCMI calls forwarding disabled\n");
> +        return -ENOSYS;
> +    }
> +
> +    return 0;
> +}
> +
> +static int scmi_dt_hyp_channel_read(struct dt_device_node *scmi_node, struct scmi_data *scmi_data,
> +                                    u64 *addr)
> +{
> +    int ret;
> +    u64 size;
> +
> +    if ( !dt_property_read_u32(scmi_node, "arm,smc-id", &scmi_data->func_id) )
> +    {
> +        printk(XENLOG_ERR "scmi: unable to read smc-id from DT\n");
> +        return -ENOENT;
> +    }
> +
> +    ret = scmi_dt_read_hyp_channel_addr(scmi_node, addr, &size);
> +    if ( IS_ERR_VALUE(ret) )
> +        return -ENOENT;
> +
> +    if ( !IS_ALIGNED(size, SCMI_SHMEM_MAPPED_SIZE) )
> +    {
> +        printk(XENLOG_ERR "scmi: shmem memory is not aligned\n");
> +        return -EINVAL;
> +    }
> +
> +    return 0;
> +}
> +
> +static __init int scmi_probe(struct dt_device_node *scmi_node, const void *data)
> +{
> +    u64 addr;
> +    int ret;
> +    struct scmi_channel *channel;
> +    int n_agents;
> +    scmi_msg_header_t hdr;
> +    struct scmi_msg_base_attributes_p2a rx;
> +
> +    ASSERT(scmi_node != NULL);
> +
> +    INIT_LIST_HEAD(&scmi_data.channel_list);
> +    spin_lock_init(&scmi_data.channel_list_lock);
> +
> +    if ( !acpi_disabled )
> +    {
> +        printk(XENLOG_WARNING "scmi: is not supported when using ACPI\n");
> +        return -EINVAL;
> +    }
> +
> +    ret = scmi_check_smccc_ver();
> +    if ( ret )
> +        return ret;
> +
> +    ret = scmi_dt_hyp_channel_read(scmi_node, &scmi_data, &addr);
> +    if ( ret )
> +        return ret;
> +
> +    scmi_data.dt_dev = scmi_node;
> +
> +    channel = smc_create_channel(SCMI_BASE_AGENT_ID_OWN, scmi_data.func_id, addr);

Should we call this with channel_list_lock held?


> +    if ( IS_ERR(channel) )
> +        goto out;
> +
> +    /* Request agent id for Xen management channel  */

At this poing channel->domain_id == DOMID_INVALID but collect_agent_id
checks for agent_channel->domain_id != DOMID_XEN

> +    ret = collect_agent_id(channel);
> +    if ( ret )
> +        return ret;
> +
> +    /* Save the agent id for Xen management channel */
> +    scmi_data.hyp_channel_agent_id = channel->agent_id;
> +
> +    ret = map_channel_memory(channel);
> +    if ( ret )
> +        goto out;

collect_agent_id already called map_channel_memory it looks like the
code was supposed to not unmap it the memory if domain_id == DOMID_XEN,
although the check doesn't work as expected.


> +    channel->domain_id = DOMID_XEN;
> +
> +    hdr.id = SCMI_BASE_PROTOCOL_ATTIBUTES;
> +    hdr.type = 0;
> +    hdr.protocol = SCMI_BASE_PROTOCOL;
> +
> +    ret = do_smc_xfer(channel, &hdr, NULL, 0, &rx, sizeof(rx));
> +    if ( ret )
> +        goto error;
> +
> +    n_agents = SCMI_FIELD_GET(SCMI_BASE_ATTR_NUM_AGENT, rx.attributes);
> +    printk(XENLOG_DEBUG "scmi: Got agent count %d\n", n_agents);
> +    ret = collect_agents(scmi_node);
> +    if ( ret )
> +        goto error;
> +
> +    ret = sci_register(&scmi_ops);
> +    if ( ret )
> +    {
> +        printk(XENLOG_ERR "SCMI: mediator already registered (ret = %d)\n",
> +               ret);
> +        return ret;
> +    }
> +
> +    scmi_data.initialized = true;
> +    goto out;
> +
> +error:
> +    unmap_channel_memory(channel);
> +    free_channel_list();
> +out:
> +    return ret;
> +}
> +
> +static const struct dt_device_match scmi_smc_match[] __initconst = {
> +    DT_MATCH_PATH("/chosen/xen,config/scmi"),

We should match by compatible string, not by path

> +    { /* sentinel */ },
> +};
> +
> +DT_DEVICE_START(scmi_smc_ma, "SCMI SMC MEDIATOR", DEVICE_FIRMWARE)
> +        .dt_match = scmi_smc_match,
> +        .init = scmi_probe,
> +DT_DEVICE_END
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * tab-width: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
> index 095b1a23e3..30e46de6d7 100644
> --- a/xen/include/public/arch-arm.h
> +++ b/xen/include/public/arch-arm.h
> @@ -329,6 +329,7 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
>  
>  #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE      0
>  #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC  1
> +#define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA  2
>  
>  struct xen_arch_domainconfig {
>      /* IN/OUT */
> @@ -355,6 +356,8 @@ struct xen_arch_domainconfig {
>      uint32_t clock_frequency;
>      /* IN */
>      uint8_t arm_sci_type;
> +    /* IN */
> +    uint8_t arm_sci_agent_id;
>  };
>  #endif /* __XEN__ || __XEN_TOOLS__ */
>  
> -- 
> 2.34.1
> 


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Date: Mon, 25 Aug 2025 17:44:02 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 10/10] docs: arm: add SCI SCMI SMC multi-agent
 driver docs
In-Reply-To: <79e357dbe97fbb8c8148e75fa65182e611665695.1753184487.git.oleksii_moisieiev@epam.com>
Message-ID: 
References:  <79e357dbe97fbb8c8148e75fa65182e611665695.1753184487.git.oleksii_moisieiev@epam.com>
User-Agent: Alpine 2.22 (DEB 394 2020-01-19)
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On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> From: Grygorii Strashko 
> 
> Add SCI SCMI SMC multi-agent driver documentation.
> It includes a detailed description of the SCMI multi-agent driver.
> This document explains the driver's functionality, configuration,
> and the compilation process. The Xen SCMI multi-agent driver is
> designed to provide SCMI access to system resources from different
> domains.
> 
> Signed-off-by: Oleksii Moisieiev 

missing Grygorii's signed-off-by


> ---
> 
> Changes in v5:
> - rework multi-agent driver to leave Host Device-tree unmodified
> 
>  .../arm/firmware/arm-scmi.rst                 | 341 +++++++++++++++++-
>  1 file changed, 340 insertions(+), 1 deletion(-)
> 
> diff --git a/docs/hypervisor-guide/arm/firmware/arm-scmi.rst b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> index a084c0caa3..2ab56af879 100644
> --- a/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> +++ b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> @@ -31,7 +31,10 @@ domain serving as Driver domain).
>  
>  The below sections describe SCMI support options available for Xen.
>  
> -[1] `Arm SCMI `_
> +| [1] `Arm SCMI `_
> +| [2] `System Control and Management Interface (SCMI) bindings `_
> +| [3] `Generic Domain Access Controllers bindings `_
> +
>  
>  Simple SCMI over SMC/HVC calls forwarding driver (EL3)
>  ------------------------------------------------------
> @@ -175,3 +178,339 @@ enabling SCMI with "arm_sci" xl.cfg option.
>      ->        xen,reg = <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
>      ->        xen,force-assign-without-iommu;
>        };
> +
> +SCMI SMC/HVC multi-agent driver (EL3)
> +-------------------------------------
> +
> +The SCMI SMC/HVC multi-agent driver enables support for ARM EL3 Trusted Firmware-A (TF-A) which
> +provides SCMI interface with multi-agnet support, as shown below.

multi-agent

> +
> +::
> +
> +      +-----------------------------------------+
> +      |                                         |
> +      | EL3 TF-A SCMI                           |
> +      +-------+--+-------+--+-------+--+-------++
> +      |shmem1 |  |shmem0 |  |shmem2 |  |shmemX |
> +      +-----+-+  +---+---+  +--+----+  +---+---+
> +    smc-id1 |        |         |           |
> +    agent1  |        |         |           |
> +      +-----v--------+---------+-----------+----+
> +      |              |         |           |    |
> +      |              |         |           |    |
> +      +--------------+---------+-----------+----+
> +             smc-id0 |  smc-id2|    smc-idX|
> +             agent0  |  agent2 |    agentX |
> +                     |         |           |
> +                +----v---+  +--v-----+  +--v-----+
> +                |        |  |        |  |        |
> +                | Dom0   |  | Dom1   |  | DomX   |
> +                |        |  |        |  |        |
> +                |        |  |        |  |        |
> +                +--------+  +--------+  +--------+
> +
> +The EL3 SCMI multi-agent firmware expected to provide SCMI SMC/HVC shared-memory transport

is expected to provide


> +for every Agent in the system. The SCMI Agent transport channel defined by pair:
> +
> +- smc-id: SMC/HVC function id used for Doorbell
> +- shmem: shared memory for messages transfer, **Xen page aligned**.
> +  Shared memory is mapped with the following flags: MT_DEVICE_nGnRE and _PAGE_DEVICE, indicating that this
> +  memory is mapped as device memory.
> +
> +The following SCMI Agents expected to be defined by SCMI FW to enable SCMI multi-agent functionality

is expected to

> +under Xen:
> +
> +- Xen management agent: trusted agents that accesses to the Base Protocol commands to configure
> +  agent specific permissions
> +- OSPM VM agents: non-trusted agent, one for each Guest domain which is  allowed direct HW access.
> +  At least one OSPM VM agent has to be provided by FW if HW is handled only by Dom0 or Driver Domain.
> +
> +The EL3 SCMI FW expected to implement following Base protocol messages:

is expected to

> +
> +- BASE_DISCOVER_AGENT (optional if agent_id was provided)
> +- BASE_RESET_AGENT_CONFIGURATION (optional)
> +- BASE_SET_DEVICE_PERMISSIONS (optional)
> +
> +The number of supported SCMI agents and their transport specifications are SCMI FW implementation
> +specific.
> +
> +Compiling with multi-agent support
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +To build with the SCMI SMC/HVC multi-agent driver support, enable Kconfig option:
> +
> +::
> +
> +    CONFIG_SCMI_SMC_MA
> +
> +
> +Driver functionality
> +^^^^^^^^^^^^^^^^^^^^
> +
> +The SCI SCMI SMC multi-agent driver implements following functionality:
> +
> +- The driver is initialized based on the ``xen,config`` node under ``chosen``
> +  (only one SCMI interface is supported), which describes the Xen management
> +  agent SCMI interface.
> +
> +.. code::
> +
> +    scmi_shm_1: sram@47ff1000 {
> +              compatible = "arm,scmi-shmem";
> +              reg = <0x0 0x47ff1000 0x0 0x1000>;
> +    };
> +    scmi_xen: scmi {
> +            compatible = "arm,scmi-smc";
> +            arm,smc-id = <0x82000002>; <--- Xen manegement agent smc-id
> +            #address-cells = < 1>;
> +            #size-cells = < 0>;
> +            #access-controller-cells = < 1>;
> +            shmem = <&scmi_shm_1>; <--- Xen manegement agent shmem
> +    };
> +
> +- The driver obtains Xen specific SCMI Agent's configuration from the Host DT, probes Agents and
> +  builds SCMI Agents list. The Agents configuration is taken from "scmi-secondary-agents"
> +  property where first item is "arm,smc-id", second - "arm,scmi-shmem" phandle and third is
> +  optional "agent_id":
> +
> +.. code::

.. code-block:: dts


> +    chosen {
> +      ranges; <--- set default ranges so address can be translated when parsing scmi_shm node
> +      xen,config {
> +        ranges; <--- set default ranges so address can be translated when parsing scmi_shm node
> +        scmi-secondary-agents = <
> +                      0x82000003 &scmi_shm_0 0
> +                      0x82000004 &scmi_shm_2 2
> +                      0x82000005 &scmi_shm_3 3
> +                      0x82000006 &scmi_shm_4 4>;
> +        #scmi-secondary-agents-cells = <3>; <--- optional, default 3
> +
> +        scmi_shm_0 : sram@47ff0000 {
> +            compatible = "arm,scmi-shmem";
> +            reg = <0x0 0x47ff0000 0x0 0x1000>;
> +        };
> +
> +        scmi_shm_2: sram@47ff2000 {
> +                compatible = "arm,scmi-shmem";
> +                reg = <0x0 0x47ff2000 0x0 0x1000>;
> +        };
> +        scmi_shm_3: sram@47ff3000 {
> +                compatible = "arm,scmi-shmem";
> +                reg = <0x0 0x47ff3000 0x0 0x1000>;
> +        };
> +        scmi_shm_4: sram@47ff4000 {
> +                compatible = "arm,scmi-shmem";
> +                reg = <0x0 0x47ff4000 0x0 0x1000>;
> +        };
> +
> +        // Xen SCMI management channel
> +        scmi_shm_1: sram@47ff1000 {
> +                compatible = "arm,scmi-shmem";
> +                reg = <0x0 0x47ff1000 0x0 0x1000>;
> +        };
> +
> +        scmi_xen: scmi {
> +            compatible = "arm,scmi-smc";
> +            arm,smc-id = <0x82000002>; <--- Xen manegement agent smc-id
> +            #address-cells = < 1>;
> +            #size-cells = < 0>;
> +            #access-controller-cells = < 1>;
> +            shmem = <&scmi_shm_1>; <--- Xen manegement agent shmem
> +        };
> +      };
> +    };
> +
> +    /{
> +        // Host SCMI OSPM channel - provided to the Dom0 as is if SCMI enabled for it
> +        scmi_shm: sram@47ff1000 {
> +                compatible = "arm,scmi-shmem";
> +                reg = <0x0 0x47ff1000 0x0 0x1000>;
> +        };
> +
> +        firmware {
> +            scmi: scmi {
> +                compatible = "arm,scmi-smc";
> +                arm,smc-id = <0x82000003>; <--- Host OSPM agent smc-id
> +                #address-cells = < 1>;
> +                #size-cells = < 0>;
> +                shmem = <&scmi_shm>; <--- Host OSPM agent shmem
> +
> +                protocol@X{
> +                };
> +            };
> +        };
> +    };
> +
> +  This approach allows defining multiple SCMI Agents by adding Xen-specific properties under
> +  the ``/chosen`` node to the Host Device Tree, leaving the main part unchanged. The Host DT
> +  SCMI channel will be passed to Dom0.
> +
> +  The Xen management agent is described as a ``scmi_xen`` node under the ``/chosen`` node, which
> +  is used by Xen to control other SCMI Agents in the system.
> +
> +  All secondary agents' configurations are provided in the ``scmi-secondary-agents`` property with
> +  an optional ``agent_id`` field.
> +
> +  The ``agent_id`` from the ``scmi-secondary-agents`` property is used to identify the agent in the
> +  system and can be omitted by setting ``#scmi-secondary-agents-cells = <2>``, so the Secondary
> +  Agents configuration will look like this:
> +
> +.. code::

.. code-block:: dts


> +    chosen {
> +      xen,config {
> +        scmi-secondary-agents = <
> +                      0x82000003 &scmi_shm_0
> +                      0x82000004 &scmi_shm_2
> +                      0x82000005 &scmi_shm_3
> +                      0x82000006 &scmi_shm_4>;
> +        #scmi-secondary-agents-cells = <2>;
> +      };
> +    }
> +
> +  In this case, Xen will use the ``SCMI_BASE_DISCOVER_AGENT`` call to discover the ``agent_id``
> +  for each secondary agent. Providing the ``agent_id`` in the ``scmi-secondary-agents`` property
> +  allows skipping the discovery call, which is useful when the secondary agent's shared memory is
> +  not accessible by Xen or when boot time is important because it allows skipping the agent
> +  discovery procedure.
> +
> +.. note::
> +
> +    Note that Xen is the only one entry in the system which need to know about SCMI multi-agent support.
> +
> +- The driver implements the SCI subsystem interface required for configuring and enabling SCMI
> +  functionality for Dom0/hwdom and Guest domains. To enable SCMI functionality for guest domain
> +  it has to be configured with unique supported SCMI Agent_id and use corresponding SCMI SMC/HVC
> +  shared-memory transport ``[smc-id, shmem]`` defined for this SCMI Agent_id.
> +
> +- Once Xen domain is configured it can communicate with EL3 SCMI FW:
> +
> +  - zero-copy, the guest domain puts/gets SCMI message in/from shmem;
> +  - the guest triggers SMC/HVC exception with agent "smc-id" (doorbell);
> +  - the Xen driver catches exception, do checks and synchronously forwards it to EL3 FW.
> +
> +- the Xen driver sends BASE_RESET_AGENT_CONFIGURATION message to Xen management agent channel on
> +  domain destroy event. This allows to reset resources used by domain and so implement use-case
> +  like domain reboot.
> +
> +
> +Configure SCMI for Dom0
> +^^^^^^^^^^^^^^^^^^^^^^^
> +The **"dom0_scmi_agent_id="** Xen command line is used to enable SCMI functionality for
> +Dom0. if not provided SCMI will be disabled for Dom0 and all SCMI nodes removed from Dom0 DT.
> +
> +Xen utilizes Host DT SCMI node to configure Dom0 SCMI Agent so the device-tree remains unchanged
> +except for the Xen specific properties under ``/chosen`` node. If Xen device-tree doesn't include
> +``/firmware/scmi`` node or it's disabled, the Dom0 SCMI Agent will not be configured.
> +
> +.. note::
> +
> +    The **dom0_scmi_agent_id** value should match the ``func_id`` and ``shmem`` in the ``/firmware/scmi`` node
> +    to set the correct Dom0 SCMI Agent.
> +
> +Configure SCMI for for guest domain with toolstack
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +* In domain's xl.cfg file add **"arm_sci"** option as below
> +
> +::
> +
> +    arm_sci = "type=scmi_smc_multiagent,agent_id=2"
> +
> +* In domain's xl.cfg file enable access to the "arm,scmi-shmem" which should correspond
> +  assigned "agent_id" for the domain, for example:
> +
> +::
> +
> +    iomem = [
> +        "47ff2,1@22001",
> +    ]
> +
> +.. note:: It's up to the user to select guest IPA for mapping SCMI shared-memory.
> +
> +* Add SCMI nodes to the Driver domain partial device tree as in the below example.
> +  The "arm,smc-id" should correspond assigned agent_id for the domain:
> +
> +.. code::
> +
> +    passthrough {
> +       scmi_shm_0: sram@22001000 {
> +           compatible = "arm,scmi-shmem";
> +           reg = <0x0 0x22001000 0x0 0x1000>;
> +       };
> +
> +       firmware {
> +            compatible = "simple-bus";
> +                scmi: scmi {
> +                    compatible = "arm,scmi-smc";
> +                    arm,smc-id = <0x82000004>;
> +                    shmem = <&scmi_shm_0>;
> +                    ...
> +                }
> +        }
> +    }
> +
> +**Device specific access control**
> +
> +The XEN SCMI SMC/HVC multi-agent driver performs "access-controller" provider function in case
> +EL3 SCMI FW implements SCMI "4.2.1.1 Device specific access control" and provides the
> +BASE_SET_DEVICE_PERMISSIONS command to configure the devices that an agents have access to.
> +The Host DT SCMI node should have "#access-controller-cells=<1>" property and DT devices should
> +be bound to the SCMI node using Access Controllers bindings [3].
> +
> +For example:
> +
> +.. code::
> +
> +    &i2c1 {
> +            access-controllers = <&scmi 0>;
> +    };
> +
> +Use domain's xl.cfg file **"dtdev"** property to assign SCMI devices from toolstack to the guest:
> +
> +::
> +
> +    dtdev = [
> +        "/soc/i2c@e6508000",
> +    ]
> +
> +.. note::
> +
> +    xl.cfg:"dtdev" need contain all nodes which are under SCMI management (not only those which are
> +    behind IOMMU) and passed-through to the guest domain.
> +
> +Configure SCMI for predefined domains (dom0less)
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +* add "xen,sci_type" and "xen,sci_agent_id" properties for required DomU ("xen,domain") node
> +
> +::
> +
> +    xen,sci_type="scmi_smc_multiagent"
> +    xen,sci_agent_id=2
> +
> +* add scmi nodes to the Driver domain partial device tree the same way as above (toolstack case) and
> +  enable access to the "arm,scmi-shmem" according to the dom0less documentation. For example:
> +
> +.. code::
> +
> +      scmi_shm_0: sram@22001000 {
> +            compatible = "arm,scmi-shmem";
> +            reg = <0x00 0x22001000 0x00 0x1000>;
> +    ->        xen,reg = <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
> +    ->        xen,force-assign-without-iommu;
> +      };
> +
> +* For SCMI device access control configure pass-through devices in the guest partial DT according to
> +  the dom0less documentation and ensure that devices SCMI management has "xen,path" property set:
> +
> +.. code::
> +
> +		i2c@e6508000 {
> +            ...
> +			reg = <0x00 0xe6508000 0x00 0x1000>;
> +    ->        xen,path = "/soc/i2c@e6508000"
> +    ->        xen,reg = <0x0 0xe6508000 0x0 0x1000 0x0 0xe6508000>;
> +    ->        xen,force-assign-without-iommu;
> +        };
> -- 
> 2.34.1
> 


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From: Jason Andryuk 
To: Juergen Gross , Stefano Stabellini
	, Oleksandr Tyshchenko
	
CC: Jason Andryuk , ,
	
Subject: [PATCH v2 2/3] xen/events: Return -EEXIST for bound VIRQs
Date: Mon, 25 Aug 2025 20:55:14 -0400
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Change find_virq() to return -EEXIST when a VIRQ is bound to a
different CPU than the one passed in.  With that, remove the BUG_ON()
from bind_virq_to_irq() to propogate the error upwards.

Some VIRQs are per-cpu, but others are per-domain or global.  Those must
be bound to CPU0 and can then migrate elsewhere.  The lookup for
per-domain and global will probably fail when migrated off CPU 0,
especially when the current CPU is tracked.  This now returns -EEXIST
instead of BUG_ON().

A second call to bind a per-domain or global VIRQ is not expected, but
make it non-fatal to avoid trying to look up the irq, since we don't
know which per_cpu(virq_to_irq) it will be in.

Signed-off-by: Jason Andryuk 
---
V2:
New
---
 drivers/xen/events/events_base.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index 199afe59f357..a85bc43f4344 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -1314,10 +1314,12 @@ int bind_interdomain_evtchn_to_irq_lateeoi(struct xenbus_device *dev,
 }
 EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irq_lateeoi);
 
-static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
+static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn,
+		     bool percpu)
 {
 	struct evtchn_status status;
 	evtchn_port_t port;
+	bool exists = false;
 	int rc;
 
 	memset(&status, 0, sizeof(status));
@@ -1329,12 +1331,16 @@ static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
 			continue;
 		if (status.status != EVTCHNSTAT_virq)
 			continue;
-		if (status.u.virq == virq && status.vcpu == xen_vcpu_nr(cpu)) {
+		if (status.u.virq != virq)
+			continue;
+		if (status.vcpu == xen_vcpu_nr(cpu)) {
 			*evtchn = port;
 			return 0;
+		} else if (!percpu) {
+			exists = true;
 		}
 	}
-	return -ENOENT;
+	return exists ? -EEXIST : -ENOENT;
 }
 
 /**
@@ -1381,8 +1387,9 @@ int bind_virq_to_irq(unsigned int virq, unsigned int cpu, bool percpu)
 			evtchn = bind_virq.port;
 		else {
 			if (ret == -EEXIST)
-				ret = find_virq(virq, cpu, &evtchn);
-			BUG_ON(ret < 0);
+				ret = find_virq(virq, cpu, &evtchn, percpu);
+			if (ret)
+				goto out;
 		}
 
 		ret = xen_irq_info_virq_setup(info, cpu, evtchn, virq);
-- 
2.50.1



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From: Jason Andryuk 
To: Juergen Gross , Stefano Stabellini
	, Oleksandr Tyshchenko
	
CC: Jason Andryuk , ,
	
Subject: [PATCH v2 1/3] xen/events: Cleanup find_virq() return codes
Date: Mon, 25 Aug 2025 20:55:13 -0400
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rc is overwritten by the evtchn_status hypercall in each iteration, so
the return value will be whatever the last iteration is.  Change to an
explicit -ENOENT for an un-found virq and return 0 on a successful
match.

Signed-off-by: Jason Andryuk 
---
v2:
New
---
 drivers/xen/events/events_base.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index 41309d38f78c..199afe59f357 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -1318,7 +1318,7 @@ static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
 {
 	struct evtchn_status status;
 	evtchn_port_t port;
-	int rc = -ENOENT;
+	int rc;
 
 	memset(&status, 0, sizeof(status));
 	for (port = 0; port < xen_evtchn_max_channels(); port++) {
@@ -1331,10 +1331,10 @@ static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
 			continue;
 		if (status.u.virq == virq && status.vcpu == xen_vcpu_nr(cpu)) {
 			*evtchn = port;
-			break;
+			return 0;
 		}
 	}
-	return rc;
+	return -ENOENT;
 }
 
 /**
-- 
2.50.1



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From: Jason Andryuk 
To: Juergen Gross , Stefano Stabellini
	, Oleksandr Tyshchenko
	
CC: Jason Andryuk , ,
	
Subject: [PATCH v2 0/3] xen/events: Fix Global and Domain VIRQ tracking
Date: Mon, 25 Aug 2025 20:55:12 -0400
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v2 is now a series first changing find_virq() to return -EEXIST in some
cases, and then tracking cpu movement of VIRQs.  This keeps ensures the
cpu is correct when calling unbind_from_irq().

Jason Andryuk (3):
  xen/events: Cleanup find_virq() return codes
  xen/events: Return -EEXIST for bound VIRQs
  xen/events: Update virq_to_irq on migration

 drivers/xen/events/events_base.c | 32 +++++++++++++++++++++++++-------
 1 file changed, 25 insertions(+), 7 deletions(-)

-- 
2.50.1



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From: Jason Andryuk 
To: Juergen Gross , Stefano Stabellini
	, Oleksandr Tyshchenko
	, Chris Wright , "Jeremy
 Fitzhardinge" 
CC: Jason Andryuk , ,
	, 
Subject: [PATCH v2 3/3] xen/events: Update virq_to_irq on migration
Date: Mon, 25 Aug 2025 20:55:15 -0400
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VIRQs come in 3 flavors, per-VPU, per-domain, and global, and the VIRQs
are tracked in per-cpu virq_to_irq arrays.

Per-domain and global VIRQs must be bound on CPU 0, and
bind_virq_to_irq() sets the per_cpu virq_to_irq at registration time
Later, the interrupt can migrate, and info->cpu is updated.  When
calling __unbind_from_irq(), the per-cpu virq_to_irq is cleared for a
different cpu.  If bind_virq_to_irq() is called again with CPU 0, the
stale irq is returned.  There won't be any irq_info for the irq, so
things break.

Make xen_rebind_evtchn_to_cpu() update the per_cpu virq_to_irq mappings
to keep them update to date with the current cpu.  This ensures the
correct virq_to_irq is cleared in __unbind_from_irq().

Fixes: e46cdb66c8fc ("xen: event channels")
Cc: stable@vger.kernel.org
Signed-off-by: Jason Andryuk 
---
V2:
Different approach changing virq_to_irq
---
 drivers/xen/events/events_base.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index a85bc43f4344..4e9db7b92dde 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -1772,6 +1772,7 @@ static int xen_rebind_evtchn_to_cpu(struct irq_info *info, unsigned int tcpu)
 {
 	struct evtchn_bind_vcpu bind_vcpu;
 	evtchn_port_t evtchn = info ? info->evtchn : 0;
+	int old_cpu = info ? info->cpu : tcpu;
 
 	if (!VALID_EVTCHN(evtchn))
 		return -1;
@@ -1795,8 +1796,18 @@ static int xen_rebind_evtchn_to_cpu(struct irq_info *info, unsigned int tcpu)
 	 * it, but don't do the xenlinux-level rebind in that case.
 	 */
 	if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
+	{
 		bind_evtchn_to_cpu(info, tcpu, false);
 
+		if (info->type == IRQT_VIRQ) {
+			int virq = info->u.virq;
+			int irq = per_cpu(virq_to_irq, old_cpu)[virq];
+
+			per_cpu(virq_to_irq, old_cpu)[virq] = -1;
+			per_cpu(virq_to_irq, tcpu)[virq] = irq;
+		}
+	}
+
 	do_unmask(info, EVT_MASK_REASON_TEMPORARY);
 
 	return 0;
-- 
2.50.1



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Date: Tue, 26 Aug 2025 03:49:43 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: xen-devel 
Cc: Roger Pau =?utf-8?B?TW9ubsOp?= 
Subject: MSI-X cleanup(?) issue with passthrough after domU restart

Hi,

I'm hitting an MSI-X issue after rebooting the domU. The symptoms are
rather boring: on initial domU start the device (realtek eth card) works
fine, but after domU restart, the link doesn't come up (there is no
"Link is Up" message anymore). No errors from domU driver or Xen. I
tracked it down to MSI-X - if I force INTx (via pci=3Dnomsi on domU
cmdline) it works fine. Convincing the driver to poll instead of waiting
for an interrupt also workarounds the issue.

I noticed also some interrupts are not cleaned up on restart. The list
of MSIs in 'Q' debug key output grows:

    (XEN) 0000:03:00.0 - d22 - node -1  - MSIs < 41 42 43 44 45 46 47 >
    restart sys-net domU
    (XEN) 0000:03:00.0 - d24 - node -1  - MSIs < 41 42 43 44 45 46 47 48 >
    restart sys-net domU
    (XEN) 0000:03:00.0 - d26 - node -1  - MSIs < 41 42 43 44 45 46 47 48 49=
 >

and 'M' output is:

    (XEN)  MSI-X   41 vec=3Db1 lowest  edge   assert  log lowest dest=3D000=
00001 mask=3D1/H /1
    (XEN)  MSI-X   42 vec=3Db9 lowest  edge   assert  log lowest dest=3D000=
00004 mask=3D1/HG/1
    (XEN)  MSI-X   43 vec=3Dc1 lowest  edge   assert  log lowest dest=3D000=
00010 mask=3D1/HG/1
    (XEN)  MSI-X   44 vec=3Dd9 lowest  edge   assert  log lowest dest=3D000=
00001 mask=3D1/HG/1
    (XEN)  MSI-X   45 vec=3De1 lowest  edge   assert  log lowest dest=3D000=
00001 mask=3D1/HG/1
    (XEN)  MSI-X   46 vec=3De9 lowest  edge   assert  log lowest dest=3D000=
00040 mask=3D1/HG/1
    (XEN)  MSI-X   47 vec=3D32 lowest  edge   assert  log lowest dest=3D000=
00004 mask=3D1/HG/1
    (XEN)  MSI-X   48 vec=3D3a lowest  edge   assert  log lowest dest=3D000=
00040 mask=3D1/HG/1
    (XEN)  MSI-X   49 vec=3D42 lowest  edge   assert  log lowest dest=3D000=
00010 mask=3D1/ G/1

And also, after starting and stopping the domU, `xl pci-assignable-remove 0=
3:00.0`
makes pciback to complain:

    [ 1180.919874] pciback 0000:03:00.0: xen_pciback: MSI-X release failed =
(-16)

This is all running on Xen 4.19.3, but I don't see much changes in this
area since then.

Some more info collected at https://github.com/QubesOS/qubes-issues/issues/=
9335

My question is: what should be responsible for this cleanup on domain
destroy? Xen, or maybe device model (which is QEMU in stubdomain here)?
I see some cleanup (apparently not enough) happening via QEMU when the
domU driver is unloaded, but logically correct cleanup shouldn't depend
on correct domU operation...

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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From xen-devel-bounces@lists.xenproject.org Tue Aug 26 02:57:26 2025
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Date: Mon, 25 Aug 2025 19:57:00 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Jan Beulich 
cc: Stefano Stabellini , 
    Oleksii Kurochko , ray.huang@amd.com, 
    Andrew Cooper , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Anthony PERARD , 
    Michal Orzel , Julien Grall , 
    xen-devel@lists.xenproject.org, Penny Zheng 
Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
In-Reply-To: <49416df6-83c8-4fa3-bf81-2d1e504ef31b@suse.com>
Message-ID: 
References: <20250815102728.1340505-1-Penny.Zheng@amd.com>   <2035b14e-3836-4e80-9dad-8a49ca90864a@suse.com> 
 <49416df6-83c8-4fa3-bf81-2d1e504ef31b@suse.com>
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On Mon, 25 Aug 2025, Jan Beulich wrote:
> On 19.08.2025 01:51, Stefano Stabellini wrote:
> > On Mon, 18 Aug 2025, Jan Beulich wrote:
> >> On 18.08.2025 15:28, Oleksii Kurochko wrote:
> >>> On 8/18/25 10:31 AM, Jan Beulich wrote:
> >>>> On 15.08.2025 12:27, Penny Zheng wrote:
> >>>>> In order to fix CI error of a randconfig picking both PV_SHIM_EXCLUSIVE=y and
> >>>>> HVM=y results in hvm.c being built, but domctl.c not being built, which leaves
> >>>>> a few functions, like domctl_lock_acquire/release() undefined, causing linking
> >>>>> to fail.
> >>>>> To fix that, we intend to move domctl.o out of the PV_SHIM_EXCLUSIVE Makefile
> >>>>> /hypercall-defs section, with this adjustment, we also need to release
> >>>>> redundant vnuma_destroy() stub definition from PV_SHIM_EXCLUSIVE guardian,
> >>>>> to not break compilation
> >>>>> Above change will leave dead code in the shim binary temporarily and will be
> >>>>> fixed with the introduction of domctl-op wrapping.
> >>>> Well, "temporarily" is now getting interesting. While v1 of "Introduce
> >>>> CONFIG_DOMCTL" was submitted in time to still be eligible for taking into
> >>>> 4.21, that - as indicated elsewhere - is moving us further in an unwanted
> >>>> direction.
> >>>
> >>> Do you mean that specifically this patch or the whole patch series is moving us
> >>> in unwanted direction? (1)
> >>
> >> That series. We said we don't want individual CONFIG_SYSCTL, CONFIG_DOMCTL, etc.
> >> Instead a single umbrella option wants introducing. Which means there series
> >> doesn't need re-doing from scratch, but it may end up being a significant re-
> >> work, especially considering that CONFIG_SYSCTL is already in the codebase and
> >> hence now also needs replacing.
> > 
> > I would not characterize this series as "moving us in an unwanted
> > direction". Yes, it introduces a separate CONFIG_DOMCTL, which we
> > agreed we do not want. However, simplifying it to reuse a single
> > CONFIG is a minor improvement that can be addressed in v2. The main
> > challenge in this series is adding the #ifdef in the appropriate
> > places, and using a single CONFIG for domctl and sysctl would
> > actually help.
> 
> Well, when are we going to see a v2 then which does this? Of the three
> options I mentioned in the earlier reply, Oleksii favored the revert
> path, leaving open the get-everything-in one. For the latter, however,
> we need to see relatively constant progress now, or else time will run
> out. Whether to commit the patch here really depends on what route we
> settle on for 4.21.

While I share Jan's view that now is a good time to make progress on
"Introduce CONFIG_DOMCTL", and I also believe that this is the best
course of action, I would like to share a few thoughts on the other
alternatives.

My understanding is that the PV_SHIM_EXCLUSIVE option is no longer
widely used, and a small size increase would not compromise its
functionality and should be tolerable.

In general, we are slow at getting larger series reviewed and committed,
and choosing to revert rather than accept fixes tends to make us even
slower, which is undesirable.



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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Andrew Cooper
	, =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v7 04/13] xen/cpufreq: add missing default: case for x86
 vendor
Thread-Topic: [PATCH v7 04/13] xen/cpufreq: add missing default: case for x86
 vendor
Thread-Index: AQHcE1LnYk6aQ+tCsUqjAHtQXx8uFLRzdoWAgADk8hA=
Date: Tue, 26 Aug 2025 04:23:43 +0000
Message-ID:
 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-5-Penny.Zheng@amd.com>
 
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Date: Tue, 26 Aug 2025 06:25:27 +0100
From: Lorenzo Stoakes 
To: David Hildenbrand 
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
        xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org,
        nvdimm@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
        Andrew Morton ,
        Madhavan Srinivasan ,
        Michael Ellerman ,
        Nicholas Piggin ,
        Christophe Leroy ,
        Juergen Gross ,
        Stefano Stabellini ,
        Oleksandr Tyshchenko ,
        Dan Williams ,
        Matthew Wilcox , Jan Kara ,
        Alexander Viro ,
        Christian Brauner ,
        "Liam R. Howlett" ,
        Vlastimil Babka , Mike Rapoport ,
        Suren Baghdasaryan , Michal Hocko ,
        Zi Yan , Baolin Wang ,
        Nico Pache , Ryan Roberts ,
        Dev Jain , Barry Song ,
        Jann Horn , Pedro Falcato ,
        Hugh Dickins , Oscar Salvador ,
        Lance Yang 
Subject: Re: [PATCH v3 08/11] mm/memory: convert print_bad_pte() to
 print_bad_page_map()
Message-ID: <9ad69d4f-69b7-4998-9639-4e8f679a2d9d@lucifer.local>
References: <20250811112631.759341-1-david@redhat.com>
 <20250811112631.759341-9-david@redhat.com>
 <923b279c-de33-44dd-a923-2959afad8626@redhat.com>
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On Mon, Aug 25, 2025 at 02:31:00PM +0200, David Hildenbrand wrote:
> On 11.08.25 13:26, David Hildenbrand wrote:
> > print_bad_pte() looks like something that should actually be a WARN
> > or similar, but historically it apparently has proven to be useful to
> > detect corruption of page tables even on production systems -- report
> > the issue and keep the system running to make it easier to actually detect
> > what is going wrong (e.g., multiple such messages might shed a light).
> >
> > As we want to unify vm_normal_page_*() handling for PTE/PMD/PUD, we'll have
> > to take care of print_bad_pte() as well.
> >
> > Let's prepare for using print_bad_pte() also for non-PTEs by adjusting the
> > implementation and renaming the function to print_bad_page_map().
> > Provide print_bad_pte() as a simple wrapper.
> >
> > Document the implicit locking requirements for the page table re-walk.
> >
> > To make the function a bit more readable, factor out the ratelimit check
> > into is_bad_page_map_ratelimited() and place the printing of page
> > table content into __print_bad_page_map_pgtable(). We'll now dump
> > information from each level in a single line, and just stop the table
> > walk once we hit something that is not a present page table.
> >
> > The report will now look something like (dumping pgd to pmd values):
> >
> > [   77.943408] BUG: Bad page map in process XXX  pte:80000001233f5867
> > [   77.944077] addr:00007fd84bb1c000 vm_flags:08100071 anon_vma: ...
> > [   77.945186] pgd:10a89f067 p4d:10a89f067 pud:10e5a2067 pmd:105327067
> >
> > Not using pgdp_get(), because that does not work properly on some arm
> > configs where pgd_t is an array. Note that we are dumping all levels
> > even when levels are folded for simplicity.
> >
> > Signed-off-by: David Hildenbrand 
> > ---
> >   include/linux/pgtable.h |  19 ++++++++
> >   mm/memory.c             | 104 ++++++++++++++++++++++++++++++++--------
> >   2 files changed, 103 insertions(+), 20 deletions(-)
> >
> > diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
> > index bff5c4241bf2e..33c84b38b7ec6 100644
> > --- a/include/linux/pgtable.h
> > +++ b/include/linux/pgtable.h
> > @@ -1966,6 +1966,25 @@ enum pgtable_level {
> >   	PGTABLE_LEVEL_PGD,
> >   };
> > +static inline const char *pgtable_level_to_str(enum pgtable_level level)
> > +{
> > +	switch (level) {
> > +	case PGTABLE_LEVEL_PTE:
> > +		return "pte";
> > +	case PGTABLE_LEVEL_PMD:
> > +		return "pmd";
> > +	case PGTABLE_LEVEL_PUD:
> > +		return "pud";
> > +	case PGTABLE_LEVEL_P4D:
> > +		return "p4d";
> > +	case PGTABLE_LEVEL_PGD:
> > +		return "pgd";
> > +	default:
> > +		VM_WARN_ON_ONCE(1);
> > +		return "unknown";
> > +	}
> > +}
>
> One kernel config doesn't like the VM_WARN_ON_ONCE here, and I don't think we
> really need it. @Andrew can you squash:

Out of interest do you know why this is happening? xtensa right? Does
xtensa not like CONFIG_DEBUG_VM?


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Andrew Cooper
	, =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Anthony PERARD , "Orzel,
 Michal" , Julien Grall , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v7 06/13] xen/cpufreq: introduce new sub-hypercall to
 propagate CPPC data
Thread-Topic: [PATCH v7 06/13] xen/cpufreq: introduce new sub-hypercall to
 propagate CPPC data
Thread-Index: AQHcE1LptmiQN44PAkOVJ+f0CssQOrRze76AgADdVjA=
Date: Tue, 26 Aug 2025 05:53:55 +0000
Message-ID:
 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-7-Penny.Zheng@amd.com>
 
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Date: Tue, 26 Aug 2025 07:55:05 +0200
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Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Oleksii Kurochko 
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Cc: Xen-devel ,
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From: Jan Beulich 
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On 25.08.2025 17:50, Oleksii Kurochko wrote:
> Hello community,
> 
> I’d like to remind everyone that the Feature Freeze deadline is approaching,
> and we still have some outstanding requests from the community for patch series
> to be merged into 4.21:
> 
> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
> 2. Introduce SCI SCMI SMC multi-agent support [2]
> 3. Introduce eSPI support [3]
> 4. FRED work: [4], [5], possibly others (?)
> 5. Introduce CONFIG_DOMCTL [6]
> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
> 7. Some other patch series I missed.

"amd-cppc CPU Performance Scaling Driver" has been pending for quite a while,
and really ought to make it imo. I'm inclined to say even if an exception was
needed. Parts have gone in, I'm about to commit more parts, but whether
everything would be in by Friday I can't predict.

Jan


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Subject: Re: [PATCH v7 06/13] xen/cpufreq: introduce new sub-hypercall to
 propagate CPPC data
To: "Penny, Zheng" 
Cc: "Huang, Ray" ,
 Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 "Orzel, Michal" , Julien Grall ,
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From: Jan Beulich 
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On 26.08.2025 07:53, Penny, Zheng wrote:
> [Public]
> 
>> -----Original Message-----
>> From: Jan Beulich 
>> Sent: Monday, August 25, 2025 11:02 PM
>> To: Penny, Zheng 
>> Cc: Huang, Ray ; Andrew Cooper
>> ; Roger Pau Monné ;
>> Anthony PERARD ; Orzel, Michal
>> ; Julien Grall ; Stefano Stabellini
>> ; xen-devel@lists.xenproject.org
>> Subject: Re: [PATCH v7 06/13] xen/cpufreq: introduce new sub-hypercall to
>> propagate CPPC data
>>
>> On 22.08.2025 12:52, Penny Zheng wrote:
>>> --- a/xen/arch/x86/x86_64/cpufreq.c
>>> +++ b/xen/arch/x86/x86_64/cpufreq.c
>>> @@ -54,3 +54,22 @@ int compat_set_px_pminfo(uint32_t acpi_id,
>>>
>>>      return set_px_pminfo(acpi_id, xen_perf);  }
>>> +
>>> +int compat_set_cppc_pminfo(unsigned int acpi_id,
>>> +                           const struct compat_processor_cppc
>>> +*cppc_data)
>>> +
>>> +{
>>> +    struct xen_processor_cppc *xen_cppc;
>>> +    unsigned long xlat_page_current;
>>> +
>>> +    xlat_malloc_init(xlat_page_current);
>>> +
>>> +    xen_cppc = xlat_malloc_array(xlat_page_current,
>>> +                                 struct xen_processor_cppc, 1);
>>> +    if ( unlikely(xen_cppc == NULL) )
>>> +        return -EFAULT;
>>
>> I think we want to avoid repeating the earlier mistake with using a wrong error code.
>> It's ENOMEM or ENOSPC or some such.
>>
> 
> Understood, I'll change it to -ENOMEM
> 
>>> --- a/xen/drivers/acpi/pm-op.c
>>> +++ b/xen/drivers/acpi/pm-op.c
>>> @@ -91,7 +91,9 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
>>>      pmpt = processor_pminfo[op->cpuid];
>>>      policy = per_cpu(cpufreq_cpu_policy, op->cpuid);
>>>
>>> -    if ( !pmpt || !pmpt->perf.states ||
>>> +    if ( !pmpt ||
>>> +         ((pmpt->init & XEN_PX_INIT) && !pmpt->perf.states) ||
>>> +         ((pmpt->init & XEN_CPPC_INIT) && pmpt->perf.state_count) ||
>>
>> I fear I don't understand this: In the PX case we check whether necessary data is
>> lacking. In the CPPC case you check that some data was provided that we don't
>> want to use? Why not similarly check that data we need was provided?
>>
> 
> We are introducing another checking line for CPPC is actually to avoid NULL deref of state[i]:
> ```
>         for ( i = 0; i < op->u.get_para.freq_num; i++ )
>                 data[i] = pmpt->perf.states[i].core_frequency * 1000;
> ```
> We want to ensure "op->u.get_para.freq_num" is always zero in CPPC mode, which is validated against pmpt->perf.state_count.
> We have similar discussion in here https://old-list-archives.xen.org/archives/html/xen-devel/2025-06/msg01160.html

Indeed I was thinking that we would have touched this before. As to your reply:
This explains the .state_count check (which imo wants a comment). It doesn't,
however, explain the absence of a "have we got the data we need" part. Unless
of course there simply isn't anything to check for.

Jan


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Subject: Re: [PATCH] misra: add deviation of Rule 17.7
To: Dmytro Prokopchuk1 
Cc: Nicola Vetrini ,
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On 25.08.2025 19:33, Dmytro Prokopchuk1 wrote:
> 
> 
> On 8/25/25 17:12, Jan Beulich wrote:
>> On 25.08.2025 15:27, Dmytro Prokopchuk1 wrote:
>>>
>>>
>>> On 8/25/25 14:07, Jan Beulich wrote:
>>>> On 25.08.2025 12:58, Dmytro Prokopchuk1 wrote:
>>>>> On 8/25/25 13:30, Jan Beulich wrote:
>>>>>> On 25.08.2025 11:05, Dmytro Prokopchuk1 wrote:
>>>>>>> MISRA C Rule 17.7 states: "The value returned by a function having
>>>>>>> non-void return type shall be used."
>>>>>>>
>>>>>>> Deviate functions like 'memcpy()', 'memset()', 'memmove()', 'snprintf()',
>>>>>>> 'strlcpy()', 'strlcat()', as they return a value purely for convenience,
>>>>>>> their primary functionality (e.g., memory or string operations) remains
>>>>>>> unaffected, and their return values are generally non-critical and seldom
>>>>>>> relied upon. Update 'deviations.rst' file accordingly.
>>>>>>
>>>>>> How come snprintf() is among this set? Its return value isn't quite just
>>>>>> for convenience, imo.
>>>>>
>>>>> Yes, snprintf()'s return value isn't just for convenience. The deviation
>>>>> justification is primarily based on the fact that its return value is
>>>>> rarely used in the Xen source base. Most callers of snprintf() don't
>>>>> care about return value. So, snprintf() is in this list.
>>>>>
>>>>> Maybe separate wording is required for the snprintf() ?
>>>>
>>>> Minimally. Personally I don't think it should be deviated globally.
>>>
>>> There are approximately 230 instances of snprintf() being used without
>>> checking its return value (across ARM and x86) in around 20 different
>>> source files. Deviation each of them could be complicated.
>>
>> My grep yields somewhere between 50 and 60 hits in xen/, among them about 15
>> in xen/tools/kconfig/, which I expect we can ignore. I also didn't mean to
>> suggest to deviate them all individually. Some may actually want to use the
>> return value, and I wouldn't be surprised if this ended up fixing a bug or
>> two.
> 
> For memory-related functions (memcpy, memset, memmove), ignoring the 
> return value is almost always safe, so I propose to leave these 
> functions in the patch, remove snprintf, strlcpy, strlcat so far, and
> precisely check usage of the last functions.
> 
> Is it OK?

Fine with me, yes.

Jan


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Subject: Re: [PATCH v3] xen/irq: Delete the pirq_cleanup_check() macro
To: Dmytro Prokopchuk1 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" 
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On 25.08.2025 21:22, Dmytro Prokopchuk1 wrote:
> From: Andrew Cooper 
> 
> MISRA Rule 5.5 objects to a macro aliasing a function, which is what
> pirq_cleanup_check() does. The macro was originally intended to ensure
> the condition 'if (!pirq->evtchn)' is always checked before invoking
> the function, avoiding errors across call sites.
> 
> There are only a handful of users, so expand it inline to be plain
> regular C. Doing this shows one path now needing braces, and one path
> in 'evtchn_bind_pirq()' where the expanded form simplies back to no
> delta, as it follows an unconditional clear of 'info->evtchn'.
> 
> While this complies with MISRA, it shifts the responsibility to
> developers to check 'if (!pirq->evtchn)' at call sites.
> 
> No functional changes.
> 
> Signed-off-by: Andrew Cooper 
> Signed-off-by: Dmytro Prokopchuk 
> ---
> Changes in v3:
> - added back wording from v1, originally written by Andrew.

Thanks. Just to mention, though - you copied it verbatim, including the
typo (simplifies). Can surely be adjusted while committing, if and when
somebody acks this. (I think it has become sufficiently clear that I'm
not going to.)

Jan


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Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart
To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 
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 xen-devel 
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On 26.08.2025 03:49, Marek Marczykowski-Górecki wrote:
> Hi,
> 
> I'm hitting an MSI-X issue after rebooting the domU. The symptoms are
> rather boring: on initial domU start the device (realtek eth card) works
> fine, but after domU restart, the link doesn't come up (there is no
> "Link is Up" message anymore). No errors from domU driver or Xen. I
> tracked it down to MSI-X - if I force INTx (via pci=nomsi on domU
> cmdline) it works fine. Convincing the driver to poll instead of waiting
> for an interrupt also workarounds the issue.
> 
> I noticed also some interrupts are not cleaned up on restart. The list
> of MSIs in 'Q' debug key output grows:
> 
>     (XEN) 0000:03:00.0 - d22 - node -1  - MSIs < 41 42 43 44 45 46 47 >
>     restart sys-net domU
>     (XEN) 0000:03:00.0 - d24 - node -1  - MSIs < 41 42 43 44 45 46 47 48 >
>     restart sys-net domU
>     (XEN) 0000:03:00.0 - d26 - node -1  - MSIs < 41 42 43 44 45 46 47 48 49 >
> 
> and 'M' output is:
> 
>     (XEN)  MSI-X   41 vec=b1 lowest  edge   assert  log lowest dest=00000001 mask=1/H /1
>     (XEN)  MSI-X   42 vec=b9 lowest  edge   assert  log lowest dest=00000004 mask=1/HG/1
>     (XEN)  MSI-X   43 vec=c1 lowest  edge   assert  log lowest dest=00000010 mask=1/HG/1
>     (XEN)  MSI-X   44 vec=d9 lowest  edge   assert  log lowest dest=00000001 mask=1/HG/1
>     (XEN)  MSI-X   45 vec=e1 lowest  edge   assert  log lowest dest=00000001 mask=1/HG/1
>     (XEN)  MSI-X   46 vec=e9 lowest  edge   assert  log lowest dest=00000040 mask=1/HG/1
>     (XEN)  MSI-X   47 vec=32 lowest  edge   assert  log lowest dest=00000004 mask=1/HG/1
>     (XEN)  MSI-X   48 vec=3a lowest  edge   assert  log lowest dest=00000040 mask=1/HG/1
>     (XEN)  MSI-X   49 vec=42 lowest  edge   assert  log lowest dest=00000010 mask=1/ G/1
> 
> And also, after starting and stopping the domU, `xl pci-assignable-remove 03:00.0`
> makes pciback to complain:
> 
>     [ 1180.919874] pciback 0000:03:00.0: xen_pciback: MSI-X release failed (-16)
> 
> This is all running on Xen 4.19.3, but I don't see much changes in this
> area since then.
> 
> Some more info collected at https://github.com/QubesOS/qubes-issues/issues/9335
> 
> My question is: what should be responsible for this cleanup on domain
> destroy? Xen, or maybe device model (which is QEMU in stubdomain here)?

The expectation is that qemu invokes the necessary cleanup, but of course ...

> I see some cleanup (apparently not enough) happening via QEMU when the
> domU driver is unloaded, but logically correct cleanup shouldn't depend
> on correct domU operation...

... Xen may not make itself dependent upon either DomU or QEMU.

What I find puzzling (assuming I can take the quoted output plus your annotations
verbatim) is that the device apparently uses multiple vectors, and we're leaking
exactly one of them. Also, since reboot is generally nothing else than shutdown
and immediate relaunch, is there a leak also after shutdown? I ask because it
might help to know which of the multiple vectors is leaked (first, last, random).

Jan


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Date: Tue, 26 Aug 2025 08:17:14 +0200
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Subject: Re: [PATCH v3 08/11] mm/memory: convert print_bad_pte() to
 print_bad_page_map()
To: Lorenzo Stoakes 
Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org,
 xen-devel@lists.xenproject.org, linux-fsdevel@vger.kernel.org,
 nvdimm@lists.linux.dev, linuxppc-dev@lists.ozlabs.org,
 Andrew Morton ,
 Madhavan Srinivasan ,
 Michael Ellerman , Nicholas Piggin ,
 Christophe Leroy ,
 Juergen Gross , Stefano Stabellini
 ,
 Oleksandr Tyshchenko ,
 Dan Williams , Matthew Wilcox
 , Jan Kara ,
 Alexander Viro ,
 Christian Brauner ,
 "Liam R. Howlett" , Vlastimil Babka
 , Mike Rapoport ,
 Suren Baghdasaryan , Michal Hocko ,
 Zi Yan , Baolin Wang ,
 Nico Pache , Ryan Roberts ,
 Dev Jain , Barry Song ,
 Jann Horn , Pedro Falcato ,
 Hugh Dickins , Oscar Salvador ,
 Lance Yang 
References: <20250811112631.759341-1-david@redhat.com>
 <20250811112631.759341-9-david@redhat.com>
 <923b279c-de33-44dd-a923-2959afad8626@redhat.com>
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On 26.08.25 07:25, Lorenzo Stoakes wrote:
> On Mon, Aug 25, 2025 at 02:31:00PM +0200, David Hildenbrand wrote:
>> On 11.08.25 13:26, David Hildenbrand wrote:
>>> print_bad_pte() looks like something that should actually be a WARN
>>> or similar, but historically it apparently has proven to be useful to
>>> detect corruption of page tables even on production systems -- report
>>> the issue and keep the system running to make it easier to actually detect
>>> what is going wrong (e.g., multiple such messages might shed a light).
>>>
>>> As we want to unify vm_normal_page_*() handling for PTE/PMD/PUD, we'll have
>>> to take care of print_bad_pte() as well.
>>>
>>> Let's prepare for using print_bad_pte() also for non-PTEs by adjusting the
>>> implementation and renaming the function to print_bad_page_map().
>>> Provide print_bad_pte() as a simple wrapper.
>>>
>>> Document the implicit locking requirements for the page table re-walk.
>>>
>>> To make the function a bit more readable, factor out the ratelimit check
>>> into is_bad_page_map_ratelimited() and place the printing of page
>>> table content into __print_bad_page_map_pgtable(). We'll now dump
>>> information from each level in a single line, and just stop the table
>>> walk once we hit something that is not a present page table.
>>>
>>> The report will now look something like (dumping pgd to pmd values):
>>>
>>> [   77.943408] BUG: Bad page map in process XXX  pte:80000001233f5867
>>> [   77.944077] addr:00007fd84bb1c000 vm_flags:08100071 anon_vma: ...
>>> [   77.945186] pgd:10a89f067 p4d:10a89f067 pud:10e5a2067 pmd:105327067
>>>
>>> Not using pgdp_get(), because that does not work properly on some arm
>>> configs where pgd_t is an array. Note that we are dumping all levels
>>> even when levels are folded for simplicity.
>>>
>>> Signed-off-by: David Hildenbrand 
>>> ---
>>>    include/linux/pgtable.h |  19 ++++++++
>>>    mm/memory.c             | 104 ++++++++++++++++++++++++++++++++--------
>>>    2 files changed, 103 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h
>>> index bff5c4241bf2e..33c84b38b7ec6 100644
>>> --- a/include/linux/pgtable.h
>>> +++ b/include/linux/pgtable.h
>>> @@ -1966,6 +1966,25 @@ enum pgtable_level {
>>>    	PGTABLE_LEVEL_PGD,
>>>    };
>>> +static inline const char *pgtable_level_to_str(enum pgtable_level level)
>>> +{
>>> +	switch (level) {
>>> +	case PGTABLE_LEVEL_PTE:
>>> +		return "pte";
>>> +	case PGTABLE_LEVEL_PMD:
>>> +		return "pmd";
>>> +	case PGTABLE_LEVEL_PUD:
>>> +		return "pud";
>>> +	case PGTABLE_LEVEL_P4D:
>>> +		return "p4d";
>>> +	case PGTABLE_LEVEL_PGD:
>>> +		return "pgd";
>>> +	default:
>>> +		VM_WARN_ON_ONCE(1);
>>> +		return "unknown";
>>> +	}
>>> +}
>>
>> One kernel config doesn't like the VM_WARN_ON_ONCE here, and I don't think we
>> really need it. @Andrew can you squash:
> 
> Out of interest do you know why this is happening? xtensa right? Does
> xtensa not like CONFIG_DEBUG_VM?

We don't happen to include mmdebug.h in a xtensa configuration.

Briefly thought about using a BUILD_BUG_ON_INVALID(), but decided to 
just drop it completely.

-- 
Cheers

David / dhildenb



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	, Anthony PERARD , "Orzel,
 Michal" , Julien Grall , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v7 06/13] xen/cpufreq: introduce new sub-hypercall to
 propagate CPPC data
Thread-Topic: [PATCH v7 06/13] xen/cpufreq: introduce new sub-hypercall to
 propagate CPPC data
Thread-Index: AQHcE1LptmiQN44PAkOVJ+f0CssQOrRze76AgADdVjCAAB1GgIAABDZw
Date: Tue, 26 Aug 2025 06:38:14 +0000
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Subject: Re: [PATCH v2 1/3] xen/events: Cleanup find_virq() return codes
To: Jason Andryuk 
Cc: xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org,
 Juergen Gross , Stefano Stabellini
 ,
 Oleksandr Tyshchenko 
References: <20250826005517.41547-1-jason.andryuk@amd.com>
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On 26.08.2025 02:55, Jason Andryuk wrote:
> rc is overwritten by the evtchn_status hypercall in each iteration, so
> the return value will be whatever the last iteration is.

Which may even be a false "success". Especially for that it feels like ...

>  Change to an
> explicit -ENOENT for an un-found virq and return 0 on a successful
> match.
> 
> Signed-off-by: Jason Andryuk 

... this also wants a Fixes: tag and perhaps a Cc: to stable@.

> --- a/drivers/xen/events/events_base.c
> +++ b/drivers/xen/events/events_base.c
> @@ -1318,7 +1318,7 @@ static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
>  {
>  	struct evtchn_status status;
>  	evtchn_port_t port;
> -	int rc = -ENOENT;
> +	int rc;

Maybe best to also move this into the more narrow scope (loop body)?
Either way:
Reviewed-by: Jan Beulich 

>  	memset(&status, 0, sizeof(status));

Having this outside of the loop is a little odd, too: It makes assumptions
on the behavior of the hypervisor (like not altering the structure upon
error). Yet likely not something to deal with right here.

Jan


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MISRA C Rule 17.7 states: "The value returned by a function having
non-void return type shall be used."

Deviate functions like 'memcpy()', 'memset()', 'memmove()', as they
return a value purely for convenience, their primary functionality
(memory manipulation) remains unaffected, and their return values
are generally non-critical and seldom relied upon.

Update 'deviations.rst' file accordingly. No functional changes.

Signed-off-by: Dmytro Prokopchuk 
---
Changes in v2:
- removed snprintf(), strlcpy(), strlcat() from the patch scope

Test CI pipeline:
https://gitlab.com/xen-project/people/dimaprkp4k/xen/-/pipelines/2003537146

Link to v1:
https://patchew.org/Xen/ad15582787e675fadf92502f85041c3232749a99.1756112701=
.git.dmytro._5Fprokopchuk1@epam.com/
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 5 +++++
 docs/misra/deviations.rst                        | 7 +++++++
 2 files changed, 12 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index 7f3fd35a33..8335af1bce 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -575,6 +575,11 @@ safe."
 -config=3DMC3A2.R17.7,calls+=3D{safe, "any()", "decl(name(__builtin_memcpy=
||__builtin_memmove||__builtin_memset||cpumask_check))"}
 -doc_end
=20
+-doc_begin=3D"It is safe to deviate functions like 'memcpy()', 'memset()',=
 'memmove()', as they return a value purely for convenience,
+their primary functionality (memory manipulation) remains unaffected, and =
their return values are generally non-critical and seldom relied upon."
+-config=3DMC3A2.R17.7,calls+=3D{safe, "any()", "decl(name(memcpy||memset||=
memmove))"}
+-doc_end
+
 #
 # Series 18.
 #
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..5ee97f41e8 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -576,6 +576,13 @@ Deviations related to MISRA C:2012 Rules:
          - __builtin_memset()
          - cpumask_check()
=20
+   * - R17.7
+     - It is safe to deviate functions like 'memcpy()', 'memset()', 'memmo=
ve()',
+       as they return a value purely for convenience, their primary functi=
onality
+       (memory manipulation) remains unaffected, and their return values a=
re
+       generally non-critical and seldom relied upon.
+     - Tagged as `safe` for ECLAIR.
+
    * - R18.2
      - Subtractions between pointers where at least one of the operand is =
a
        pointer to a symbol defined by the linker are safe.
--=20
2.43.0


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On 22.08.2025 12:52, Penny Zheng wrote:
> --- a/xen/drivers/cpufreq/cpufreq.c
> +++ b/xen/drivers/cpufreq/cpufreq.c
> @@ -64,12 +64,49 @@ LIST_HEAD_READ_MOSTLY(cpufreq_governor_list);
>  /* set xen as default cpufreq */
>  enum cpufreq_controller cpufreq_controller = FREQCTL_xen;
>  
> -enum cpufreq_xen_opt __initdata cpufreq_xen_opts[2] = { CPUFREQ_xen,
> -                                                        CPUFREQ_none };
> +enum cpufreq_xen_opt __initdata cpufreq_xen_opts[2] = { CPUFREQ_xen };

The pre-push pipeline flagged a Misra rule 9.3 violation here: A dedicated
initializer is needed to have the intended effect. I've fixed this up for
you.

Jan


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Subject: Re: [PATCH v2] misra: add deviation of Rule 17.7
To: Dmytro Prokopchuk1 
Cc: Nicola Vetrini ,
 Doug Goldstein ,
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 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
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On 26.08.2025 09:36, Dmytro Prokopchuk1 wrote:
> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
> @@ -575,6 +575,11 @@ safe."
>  -config=MC3A2.R17.7,calls+={safe, "any()", "decl(name(__builtin_memcpy||__builtin_memmove||__builtin_memset||cpumask_check))"}
>  -doc_end
>  
> +-doc_begin="It is safe to deviate functions like 'memcpy()', 'memset()', 'memmove()', as they return a value purely for convenience,
> +their primary functionality (memory manipulation) remains unaffected, and their return values are generally non-critical and seldom relied upon."
> +-config=MC3A2.R17.7,calls+={safe, "any()", "decl(name(memcpy||memset||memmove))"}
> +-doc_end
> +
>  #
>  # Series 18.
>  #
> --- a/docs/misra/deviations.rst
> +++ b/docs/misra/deviations.rst
> @@ -576,6 +576,13 @@ Deviations related to MISRA C:2012 Rules:
>           - __builtin_memset()
>           - cpumask_check()
>  
> +   * - R17.7
> +     - It is safe to deviate functions like 'memcpy()', 'memset()', 'memmove()',
> +       as they return a value purely for convenience, their primary functionality
> +       (memory manipulation) remains unaffected, and their return values are
> +       generally non-critical and seldom relied upon.
> +     - Tagged as `safe` for ECLAIR.

I realize I may be overly nitpicky here, but in files named deviations.* I find it
odd to read "It is safe to deviate ...". I further find the use of "like" odd when
you enumerate the complete set anyway.

I wonder whether the deviation wants generalizing anyway: Informational return
values are generally okay to ignore. That is, the Eclair configuration would be
limited to the three functions for now, but the text / comment could already be
broader. Then, for example, open-coded uses of the corresponding builtin functions
would also be covered right away.

Jan


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From: Dmytro Prokopchuk1 
To: Jan Beulich 
CC: Nicola Vetrini , Stefano Stabellini
	, Doug Goldstein , Andrew Cooper
	, Anthony PERARD ,
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Subject: Re: [PATCH v2] misra: add deviation of Rule 17.7
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Date: Tue, 26 Aug 2025 09:56:25 +0200
From: Nicola Vetrini 
To: Jan Beulich 
Cc: Dmytro Prokopchuk1 , Doug Goldstein
 , Stefano Stabellini , Andrew
 Cooper , Anthony PERARD
 , Michal Orzel , Julien
 Grall , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , xen-devel@lists.xenproject.org
Subject: Re: [PATCH v2] misra: add deviation of Rule 17.7
In-Reply-To: <204a1526-7e3f-4b91-b1ee-95f3d89ff756@suse.com>
References: <812b78119cee801662a31d39b556cb453aa69508.1756192362.git.dmytro_prokopchuk1@epam.com>
 <204a1526-7e3f-4b91-b1ee-95f3d89ff756@suse.com>
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On 2025-08-26 09:45, Jan Beulich wrote:
> On 26.08.2025 09:36, Dmytro Prokopchuk1 wrote:
>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>> @@ -575,6 +575,11 @@ safe."
>>  -config=MC3A2.R17.7,calls+={safe, "any()", 
>> "decl(name(__builtin_memcpy||__builtin_memmove||__builtin_memset||cpumask_check))"}
>>  -doc_end
>> 
>> +-doc_begin="It is safe to deviate functions like 'memcpy()', 
>> 'memset()', 'memmove()', as they return a value purely for 
>> convenience,
>> +their primary functionality (memory manipulation) remains unaffected, 
>> and their return values are generally non-critical and seldom relied 
>> upon."
>> +-config=MC3A2.R17.7,calls+={safe, "any()", 
>> "decl(name(memcpy||memset||memmove))"}
>> +-doc_end
>> +
>>  #
>>  # Series 18.
>>  #
>> --- a/docs/misra/deviations.rst
>> +++ b/docs/misra/deviations.rst
>> @@ -576,6 +576,13 @@ Deviations related to MISRA C:2012 Rules:
>>           - __builtin_memset()
>>           - cpumask_check()
>> 
>> +   * - R17.7
>> +     - It is safe to deviate functions like 'memcpy()', 'memset()', 
>> 'memmove()',
>> +       as they return a value purely for convenience, their primary 
>> functionality
>> +       (memory manipulation) remains unaffected, and their return 
>> values are
>> +       generally non-critical and seldom relied upon.
>> +     - Tagged as `safe` for ECLAIR.
> 
> I realize I may be overly nitpicky here, but in files named 
> deviations.* I find it
> odd to read "It is safe to deviate ...". I further find the use of 
> "like" odd when
> you enumerate the complete set anyway.
> 
> I wonder whether the deviation wants generalizing anyway: Informational 
> return
> values are generally okay to ignore. That is, the Eclair configuration 
> would be
> limited to the three functions for now, but the text / comment could 
> already be
> broader. Then, for example, open-coded uses of the corresponding 
> builtin functions
> would also be covered right away.
> 

While I understand the pragmatic reasoning, from a MISRA compliance 
standpoint it would be better not to make the written justification and 
the actual deviation diverge, and then wide both the ECLAIR 
configuration and its justification suitably once new cases want to be 
deviated. Other than that,

Reviewed-by: Nicola Vetrini 

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [PATCH v2 1/7] xen/page_alloc: Simplify domain_adjust_tot_pages
 for future changes
To: Bernhard Kaindl 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Alejandro Vallejo ,
 xen-devel@lists.xenproject.org
References: 
 <5f417fea5ca8e4da0d4b9679103c3eff4bc92900.1755341947.git.bernhard.kaindl@cloud.com>
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On 16.08.2025 13:19, Bernhard Kaindl wrote:
> --- a/xen/common/page_alloc.c
> +++ b/xen/common/page_alloc.c
> @@ -510,8 +510,14 @@ static unsigned long avail_heap_pages(
>      return free_pages;
>  }
>  
> +/*
> + * Update the total number of pages and outstanding claims of a domain.
> + * - When pages were freed, we do not increase outstanding claims.
> + */

If already you add such a comment, please have it be complete: There's
also an update to the global "outstanding_claims" in here.

>  unsigned long domain_adjust_tot_pages(struct domain *d, long pages)
>  {
> +    unsigned long adjustment;
> +
>      ASSERT(rspin_is_locked(&d->page_alloc_lock));
>      d->tot_pages += pages;
>  
> @@ -519,23 +525,22 @@ unsigned long domain_adjust_tot_pages(struct domain *d, long pages)
>       * can test d->outstanding_pages race-free because it can only change
>       * if d->page_alloc_lock and heap_lock are both held, see also
>       * domain_set_outstanding_pages below
> +     *
> +     * If the domain has no outstanding claims (or we freed pages instead),
> +     * we don't update outstanding claims and skip the claims adjustment.
>       */
>      if ( !d->outstanding_pages || pages <= 0 )
>          goto out;
>  
>      spin_lock(&heap_lock);
>      BUG_ON(outstanding_claims < d->outstanding_pages);
> -    if ( d->outstanding_pages < pages )
> -    {
> -        /* `pages` exceeds the domain's outstanding count. Zero it out. */
> -        outstanding_claims -= d->outstanding_pages;
> -        d->outstanding_pages = 0;
> -    }
> -    else
> -    {
> -        outstanding_claims -= pages;
> -        d->outstanding_pages -= pages;
> -    }
> +    /*
> +     * Reduce claims by outstanding claims or pages (whichever is smaller):
> +     * If allocated > outstanding, reduce the claims only by outstanding pages.
> +     */
> +    adjustment = min(d->outstanding_pages, (unsigned int)pages);

This would be all fine if there wasn't the cast. It's only a latent problem,
yes, but I think we still would better avoid introducing such. Imo this wants
to be

    adjustment = min_t(unsigned long, d->outstanding_pages, pages);

or the equivalent

    adjustment = min(d->outstanding_pages + 0UL, pages + 0UL);

(personally I'd prefer the latter despite its odd look, for not involving
any casts).

Jan


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Subject: Re: [PATCH v2 0/7] xen/page_alloc: Add NUMA-node specific memory
 claims
To: Bernhard Kaindl 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Tamas K Lengyel ,
 "Daniel P. Smith" ,
 Juergen Gross ,
 Christian Lindig , David Scott
 , Alejandro Vallejo ,
 xen-devel@lists.xenproject.org
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On 16.08.2025 13:19, Bernhard Kaindl wrote:
> Xen supports claiming an amount of memory ahead of allocating it to
> ensure that the memory for the domain is available for allocation.
> 
> On NUMA hosts, the same assurance is needed on a per-NUMA-node basis
> to ensure optimal placement of domain memory on the correct NUMA node:
> 
> Add per-NUMA-node claims and add a new Hypercall to claim memory for
> a domain using XEN_DOMCTL_claim_memory and xc_domain_claim_memory().
> 
> As we will implement multi-node claims as well, we updated the design
> to be flexible for multi-node claims, so that a 2nd series can build
> upon it without changing the hypercall API.
> 
> Bernhard Kaindl (6):
>   xen/page_alloc: Simplify domain_adjust_tot_pages for future changes
>   xen: New API to claim memory for a domain using XEN_DOMCTL_claim_memory
> 
> Alejandro Vallejo (1):
>   xen/page_alloc: Remove `claim` from domain_set_outstanding_pages()
> 
> Alejandro Vallejo and Bernhard Kaindl (5):
>   xen/page_alloc: Add static per-NUMA-node counts of free pages
>   xen: Add node argument to
>     domain_{adjust_tot_pages,set_outstanding_pages}()
>   xen/page_alloc.c: Create per-node outstanding claims
>   xen/page_alloc: Check per-node claims in alloc_heap_pages()
> 
>  tools/flask/policy/modules/dom0.te  |   1 +
>  tools/flask/policy/modules/xen.if   |   1 +
>  tools/include/xenctrl.h             |   4 +
>  tools/libs/ctrl/xc_domain.c         |  42 ++++++++
>  tools/ocaml/libs/xc/xenctrl.ml      |   9 ++
>  tools/ocaml/libs/xc/xenctrl.mli     |   9 ++
>  tools/ocaml/libs/xc/xenctrl_stubs.c |  21 ++++
>  xen/arch/x86/mm.c                   |   3 +-
>  xen/arch/x86/mm/mem_sharing.c       |   4 +-
>  xen/common/domain.c                 |  32 +++++-
>  xen/common/domctl.c                 |   8 ++
>  xen/common/grant_table.c            |   4 +-
>  xen/common/memory.c                 |   6 +-
>  xen/common/page_alloc.c             | 154 ++++++++++++++++++++++------
>  xen/include/public/domctl.h         |  17 +++
>  xen/include/xen/domain.h            |   2 +
>  xen/include/xen/mm.h                |   6 +-
>  xen/include/xen/sched.h             |   1 +
>  xen/xsm/flask/hooks.c               |   3 +
>  xen/xsm/flask/policy/access_vectors |   2 +
>  20 files changed, 285 insertions(+), 44 deletions(-)

Having looked at only patch 1 so far, it already becomes clear that revision
information is lacking here. This is more important than usual for this series
because (a) a patch with a pretty similar title as patch 1 here has was
submitted by (and meanwhile committed for) Alejandro and (b) you picked up
earlier work by him. In fact I first thought you lost his S-o-b on patch 1.
That would have been easily clarified by indicating in the patch that it is
new in v2.

Jan


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Subject: Re: [PATCH v2 2/7] xen/page_alloc: Remove `claim` from
 domain_set_outstanding_pages()
To: Bernhard Kaindl 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
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On 16.08.2025 13:19, Bernhard Kaindl wrote:
> With a single global count for the claims it is easy to substract
> domain_tot_pages() from the claim so the number given in the hypercall
> is the real reservation of the domain. This is the current behaviour.
> 
> However, a later patch introduces node-specific claims and those interact
> very poorly with such a scheme. Since accounting domain_tot_pages() in
> one case but not the other seems strictly worse than not accounting them
> at all (which is at least consistent), this patch stops substracting
> tot_pages from the claim and instead checks that claimed memory +
> allocated memory don't exceed max_mem.
> 
> Arguably it's also clearer for the caller to align the amount of claimed
> memory with that of the requested claim. xl/libxenguest code never updated
> an existing claim: It stakes a claim, allocates all domain memory, cancels
> a possible leftover claim, finishes building the domain and unpauses it.
> 
> Signed-off-by: Bernhard Kaindl 
> Signed-off-by: Alejandro Vallejo 

Is this order (and the lack of From:) correct? A patch of the same title was
submitted by Alejandro at some point. Additionally the cover letter lists
this one patch as the sole Alejandro-only one. I'm also uncertain if you may
freely alter the original S-o-b, which was still having his @cloud.com email
address afaict.

> ---
>  xen/common/page_alloc.c | 19 ++++++-------------
>  1 file changed, 6 insertions(+), 13 deletions(-)

>From eyeballing both patches nothing has changed. That would support the
tagging as Alejandro-only in the cover letter, but it also means review
comments weren't addressed. Such non-addressing would, however, require a
verbal reply to those review comments, which I can't find any record of.
Instead in a reply to Roger's comments Alejandro indicated that there
indeed was an oversight on his part. My separate comment wasn't replied to
at all.

Jan


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, Juergen Gross , Andrew Cooper
	, "Orzel, Michal" , Julien
 Grall , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Stefano Stabellini ,
	"xen-devel@lists.xenproject.org" 
Subject: RE: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq
 para
Thread-Topic: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq
 para
Thread-Index: AQHcE1LyQ0lYyaNtv02FRdV+NHpcFrRzhX0AgAESjyA=
Date: Tue, 26 Aug 2025 08:21:54 +0000
Message-ID:
 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-12-Penny.Zheng@amd.com>
 
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Subject: Re: [PATCH v2 3/7] xen/page_alloc: Add static per-NUMA-node counts of
 free pages
To: Bernhard Kaindl 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
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On 16.08.2025 13:19, Bernhard Kaindl wrote:
> The static per-NUMA-node count of free pages is the sum of free memory
> in all zones of a node. It's an optimisation to avoid doing that operation
> frequently in the following patches that introduce per-NUMA-node claims.
> 
> ---
> Changed since v1:
> - Added ASSERT(per_node_avail_pages[node] >= request) as requested
>   during review by Roger: Comment by me: As we have
>   ASSERT(avail[node][zone] >= request);
>   directly before it, request is already valid, so this checks
>   that per_node_avail_pages[node] is not mis-accounted too low.

Okay, this addresses Roger's comment. What about mine, though?

> Signed-off-by: Bernhard Kaindl 
> Signed-off-by: Alejandro Vallejo 

Apart from similar concerns as for patch 2, these come too late. They
wouldn't end up in the commit message, due to the earlier --- separator.

Given the problems with the first three patches I'm going to stop review
here, expecting a tidied v3 to be submitted with all prior review
comments addressed (verbally or by respective adjustments).

Jan


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Date: Tue, 26 Aug 2025 10:28:56 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= ,
	Jan Beulich 
Cc: xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart
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On Tue, Aug 26, 2025 at 08:16:56AM +0200, Jan Beulich wrote:
> On 26.08.2025 03:49, Marek Marczykowski-Górecki wrote:
> > Hi,
> > 
> > I'm hitting an MSI-X issue after rebooting the domU. The symptoms are
> > rather boring: on initial domU start the device (realtek eth card) works
> > fine, but after domU restart, the link doesn't come up (there is no
> > "Link is Up" message anymore). No errors from domU driver or Xen. I
> > tracked it down to MSI-X - if I force INTx (via pci=nomsi on domU
> > cmdline) it works fine. Convincing the driver to poll instead of waiting
> > for an interrupt also workarounds the issue.
> > 
> > I noticed also some interrupts are not cleaned up on restart. The list
> > of MSIs in 'Q' debug key output grows:
> > 
> >     (XEN) 0000:03:00.0 - d22 - node -1  - MSIs < 41 42 43 44 45 46 47 >
> >     restart sys-net domU
> >     (XEN) 0000:03:00.0 - d24 - node -1  - MSIs < 41 42 43 44 45 46 47 48 >
> >     restart sys-net domU
> >     (XEN) 0000:03:00.0 - d26 - node -1  - MSIs < 41 42 43 44 45 46 47 48 49 >
> > 
> > and 'M' output is:
> > 
> >     (XEN)  MSI-X   41 vec=b1 lowest  edge   assert  log lowest dest=00000001 mask=1/H /1
> >     (XEN)  MSI-X   42 vec=b9 lowest  edge   assert  log lowest dest=00000004 mask=1/HG/1
> >     (XEN)  MSI-X   43 vec=c1 lowest  edge   assert  log lowest dest=00000010 mask=1/HG/1
> >     (XEN)  MSI-X   44 vec=d9 lowest  edge   assert  log lowest dest=00000001 mask=1/HG/1
> >     (XEN)  MSI-X   45 vec=e1 lowest  edge   assert  log lowest dest=00000001 mask=1/HG/1
> >     (XEN)  MSI-X   46 vec=e9 lowest  edge   assert  log lowest dest=00000040 mask=1/HG/1
> >     (XEN)  MSI-X   47 vec=32 lowest  edge   assert  log lowest dest=00000004 mask=1/HG/1
> >     (XEN)  MSI-X   48 vec=3a lowest  edge   assert  log lowest dest=00000040 mask=1/HG/1
> >     (XEN)  MSI-X   49 vec=42 lowest  edge   assert  log lowest dest=00000010 mask=1/ G/1
> > 
> > And also, after starting and stopping the domU, `xl pci-assignable-remove 03:00.0`
> > makes pciback to complain:
> > 
> >     [ 1180.919874] pciback 0000:03:00.0: xen_pciback: MSI-X release failed (-16)
> > 
> > This is all running on Xen 4.19.3, but I don't see much changes in this
> > area since then.
> > 
> > Some more info collected at https://github.com/QubesOS/qubes-issues/issues/9335
> > 
> > My question is: what should be responsible for this cleanup on domain
> > destroy? Xen, or maybe device model (which is QEMU in stubdomain here)?
> 
> The expectation is that qemu invokes the necessary cleanup, but of course ...
> 
> > I see some cleanup (apparently not enough) happening via QEMU when the
> > domU driver is unloaded, but logically correct cleanup shouldn't depend
> > on correct domU operation...
> 
> ... Xen may not make itself dependent upon either DomU or QEMU.

AFAICT free_domain_pirqs() called by arch_domain_destroy() should take
care of unbinding and freeing pirqs (but obviously not in this case).
Can you repeat the test with a debug=y hypervisor and post the
resulting serial or dmesg here?  Some of the errors on those paths are
printed with dprintk() and won't be visible unless using a Xen debug
build.

> What I find puzzling (assuming I can take the quoted output plus your annotations
> verbatim) is that the device apparently uses multiple vectors, and we're leaking
> exactly one of them. Also, since reboot is generally nothing else than shutdown
> and immediate relaunch, is there a leak also after shutdown? I ask because it
> might help to know which of the multiple vectors is leaked (first, last, random).

Can we maybe get the output of `lspci -vv` when the device is
attached?

Thanks, Roger.


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Subject: Re: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq
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To: "Penny, Zheng" 
Cc: "Huang, Ray" ,
 Anthony PERARD , Juergen Gross ,
 Andrew Cooper ,
 "Orzel, Michal" , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
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On 26.08.2025 10:21, Penny, Zheng wrote:
>> -----Original Message-----
>> From: Jan Beulich 
>> Sent: Monday, August 25, 2025 11:37 PM
>>
>> On 22.08.2025 12:52, Penny Zheng wrote:
>>> --- a/tools/libs/ctrl/xc_pm.c
>>> +++ b/tools/libs/ctrl/xc_pm.c
>>> @@ -288,7 +288,6 @@ int xc_get_cpufreq_para(xc_interface *xch, int cpuid,
>>>          CHK_FIELD(s.scaling_min_freq);
>>>          CHK_FIELD(s.u.userspace);
>>>          CHK_FIELD(s.u.ondemand);
>>> -        CHK_FIELD(cppc_para);
>>>
>>>  #undef CHK_FIELD
>>
>> What is done here is already less than what could be done; I think ...
>>
> 
> Emm, maybe because we define two different cpufreq para structures for user space and sysctl, struct xc_get_cpufreq_para and struct xen_get_cppc_para.
> But for cppc para, it is an alias:
> typedef struct xen_get_cppc_para xc_cppc_para_t;

Oh. Then ...

> So ...
> 
>>> @@ -366,6 +365,33 @@ int xc_set_cpufreq_cppc(xc_interface *xch, int cpuid,
>>>      return ret;
>>>  }
>>>
>>> +int xc_get_cppc_para(xc_interface *xch, unsigned int cpuid,
>>> +                     xc_cppc_para_t *cppc_para) {
>>> +    int ret;
>>> +    struct xen_sysctl sysctl = {};
>>> +    struct xen_get_cppc_para *sys_cppc_para =
>>> +&sysctl.u.pm_op.u.get_cppc;
>>> +
>>> +    if ( !xch  || !cppc_para )
>>> +    {
>>> +        errno = EINVAL;
>>> +        return -1;
>>> +    }
>>> +
>>> +    sysctl.cmd = XEN_SYSCTL_pm_op;
>>> +    sysctl.u.pm_op.cmd = GET_CPUFREQ_CPPC;
>>> +    sysctl.u.pm_op.cpuid = cpuid;
>>> +
>>> +    ret = xc_sysctl(xch, &sysctl);
>>> +    if ( ret )
>>> +        return ret;
>>> +
>>> +    BUILD_BUG_ON(sizeof(*cppc_para) != sizeof(*sys_cppc_para));

... why is this here, when ...

>>> +    memcpy(cppc_para, sys_cppc_para, sizeof(*sys_cppc_para));
>>
>> ... you minimally want to apply as much checking here.

... a better effect can be had by

    cppc_para = sys_cppc_para;

?

Jan


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From: Mykola Kvach 
Date: Tue, 26 Aug 2025 12:08:53 +0300
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Subject: Re: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , Mykola Kvach , 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Andrew Cooper , Anthony PERARD , 
	Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Content-Type: text/plain; charset="UTF-8"
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Hi Volodymyr,


On Sat, Aug 23, 2025 at 2:30=E2=80=AFAM Volodymyr Babchuk
 wrote:
>
>
> Hi Mykola,
>
> Mykola Kvach  writes:
>
> > From: Mykola Kvach 
> >
> > This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPS=
CI
> > (virtual PSCI) interface, allowing guests to request suspend via the PS=
CI
> > v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).
> >
> > The implementation:
> > - Adds SYSTEM_SUSPEND function IDs to PSCI definitions
> > - Implements trapping and handling of SYSTEM_SUSPEND in vPSCI
> > - Allows only non-hardware domains to invoke SYSTEM_SUSPEND; for the
> >   hardware domain, PSCI_NOT_SUPPORTED is returned to avoid halting the
> >   system in hwdom_shutdown() called from domain_shutdown
> > - Ensures all secondary VCPUs of the calling domain are offline before
> >   allowing suspend due to PSCI spec
> >
> > GIC and virtual timer context must be saved when the domain suspends.
> > This is done by moving the respective code in ctxt_switch_from
> > before the return that happens if the domain suspended.
> >
> > domain_resume_nopause() is introduced to allow resuming a domain from
> > SYSTEM_SUSPEND without pausing it first. This avoids problematic
> > domain_pause() calls when resuming from suspend on Arm, particularly
> > in error paths. The function is only used on Arm; other architectures
> > continue to use the original domain_resume().
> >
> > Usage:
> >
> > For Linux-based guests, suspend can be initiated with:
> >     echo mem > /sys/power/state
> > or via:
> >     systemctl suspend
> >
> > Resuming the guest is performed from control domain using:
> >       xl resume 
> >
> > Signed-off-by: Mykola Kvach 
> > ---
> > Changes in V9:
> > - no functional changes
> > - cosmetic chnages after review
> > - enhance commit message and add extra comment to the code after review
> >
> > Changes in V8:
> > - GIC and virtual timer context must be saved when the domain suspends
> > - rework locking
> > - minor changes after code review
> >
> > Changes in V7:
> > - add proper locking
> > - minor changes after code review
> >
> > Changes in V6:
> > - skip execution of ctxt_switch_from for vcpu that is in paused domain
> > - add implementation of domain_resume without domain_pause
> > - add helper function to determine if vcpu is suspended or not
> > - ignore upper 32 bits of argument values when the domain is 64-bit
> >   and calls the SMC32 SYSTEM_SUSPEND function
> > - cosmetic changes after review
> >
> > Changes in V5:
> > - don't use standby mode, restore execution in a provided by guest poin=
t
> > - move checking that all CPUs, except current one, are offline to after
> >   pausing the vCPUs
> > - provide ret status from arch_domain_shutdown and handle it in
> >   domain_shutdown
> > - adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI funct=
ions
> >
> > Changes in V4:
> > Dropped all changes related to watchdog, domain is marked as shutting
> > down in domain_shutdown and watchdog timeout handler won't trigger
> > because of it.
> >
> > Previous versions included code to manage Xen watchdog timers during su=
spend,
> > but this was removed. When a guest OS starts the Xen watchdog (either v=
ia the
> > kernel driver or xenwatchdogd), it is responsible for managing that sta=
te
> > across suspend/resume. On Linux, the Xen kernel driver properly stops t=
he
> > watchdog during suspend. However, when xenwatchdogd is used instead, su=
spend
> > handling is incomplete, potentially leading to watchdog-triggered reset=
s on
> > resume. Xen leaves watchdog handling to the guest OS and its services.
> >
> > Dropped all changes related to VCPU context, because instead domain_shu=
tdown
> > is used, so we don't need any extra changes for suspending domain.
> >
> > Changes in V3:
> > Dropped all domain flags and related code (which touched common functio=
ns like
> > vcpu_unblock), keeping only the necessary changes for Xen suspend/resum=
e, i.e.
> > suspend/resume is now fully supported only for the hardware domain.
> > Proper support for domU suspend/resume will be added in a future patch.
> > This patch does not yet include VCPU context reset or domain context
> > restoration in VCPU.
> > ---
> >  xen/arch/arm/domain.c                 |  17 +++--
> >  xen/arch/arm/include/asm/perfc_defn.h |   1 +
> >  xen/arch/arm/include/asm/psci.h       |   2 +
> >  xen/arch/arm/include/asm/vpsci.h      |   2 +-
> >  xen/arch/arm/vpsci.c                  | 101 ++++++++++++++++++++++----
> >  xen/common/domain.c                   |  31 ++++++--
> >  xen/include/xen/sched.h               |   6 ++
> >  7 files changed, 131 insertions(+), 29 deletions(-)
> >
> > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> > index 310c578909..9e9649c4e2 100644
> > --- a/xen/arch/arm/domain.c
> > +++ b/xen/arch/arm/domain.c
> > @@ -90,6 +90,16 @@ static void ctxt_switch_from(struct vcpu *p)
> >      if ( is_idle_vcpu(p) )
> >          return;
> >
> > +    /* Arch timer */
> > +    p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1);
> > +    virt_timer_save(p);
> > +
> > +    /* VGIC */
> > +    gic_save_state(p);
> > +
>
> I'd like to see comment here on why we don't need to do rest of the
> ctx save code. I saw that this is described in the commit message, but
> comment there will be very helpful for future contributors.

Honestly, regarding the vCPU context, the only thing we need to
prevent from being saved (overwritten) in this call is the SCTLR_EL1
register. This was already handled in one of the previous patches,
but the change was not accepted during review.

As for other registers, saving them is not strictly required
according to the PSCI specification. It states that at startup we
must set the AIF or DAIF bits for AArch32 or AArch64, respectively
(DEN0022F.b 1.3, "6.4.3.3 Exceptions"). SCTLR.{I, C, M} must be set
to {0, 0, 0} (DEN0022F.b 1.3, "6.4.3.4 MMU, cache and branch
predictor enable").

Finally, the context ID and the entry point must also be saved in
the guest registers, but in this function they are not modified.

I'll add a comment as you proposed, to make this clearer for future
contributors.

>
> > +    if ( test_bit(_VPF_suspended, &p->pause_flags) )
> > +        return;
> > +
> >      p2m_save_state(p);
> >
> >      /* CP 15 */
> > @@ -106,10 +116,6 @@ static void ctxt_switch_from(struct vcpu *p)
> >      p->arch.tpidrro_el0 =3D READ_SYSREG(TPIDRRO_EL0);
> >      p->arch.tpidr_el1 =3D READ_SYSREG(TPIDR_EL1);
> >
> > -    /* Arch timer */
> > -    p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1);
> > -    virt_timer_save(p);
> > -
> >      if ( is_32bit_domain(p->domain) && cpu_has_thumbee )
> >      {
> >          p->arch.teecr =3D READ_SYSREG(TEECR32_EL1);
> > @@ -158,9 +164,6 @@ static void ctxt_switch_from(struct vcpu *p)
> >
> >      /* XXX MPU */
> >
> > -    /* VGIC */
> > -    gic_save_state(p);
> > -
> >      isb();
> >  }
> >
> > diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/inclu=
de/asm/perfc_defn.h
> > index effd25b69e..8dfcac7e3b 100644
> > --- a/xen/arch/arm/include/asm/perfc_defn.h
> > +++ b/xen/arch/arm/include/asm/perfc_defn.h
> > @@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system=
_reset")
> >  PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
> >  PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
> >  PERFCOUNTER(vpsci_features,            "vpsci: features")
> > +PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
> >
> >  PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
> >
> > diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm=
/psci.h
> > index 4780972621..48a93e6b79 100644
> > --- a/xen/arch/arm/include/asm/psci.h
> > +++ b/xen/arch/arm/include/asm/psci.h
> > @@ -47,10 +47,12 @@ void call_psci_system_reset(void);
> >  #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
> >  #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
> >  #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
> > +#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
> >
> >  #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
> >  #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
> >  #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
> > +#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
> >
> >  /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
> >  #define PSCI_0_2_AFFINITY_LEVEL_ON      0
> > diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/as=
m/vpsci.h
> > index 0cca5e6830..69d40f9d7f 100644
> > --- a/xen/arch/arm/include/asm/vpsci.h
> > +++ b/xen/arch/arm/include/asm/vpsci.h
> > @@ -23,7 +23,7 @@
> >  #include 
> >
> >  /* Number of function implemented by virtual PSCI (only 0.2 or later) =
*/
> > -#define VPSCI_NR_FUNCS  12
> > +#define VPSCI_NR_FUNCS  14
> >
> >  /* Functions handle PSCI calls from the guests */
> >  bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
> > diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
> > index 7ba9ccd94b..67d369a8a2 100644
> > --- a/xen/arch/arm/vpsci.c
> > +++ b/xen/arch/arm/vpsci.c
> > @@ -10,28 +10,18 @@
> >
> >  #include 
> >
> > -static int do_common_cpu_on(register_t target_cpu, register_t entry_po=
int,
> > -                            register_t context_id)
> > +static int do_setup_vcpu_ctx(struct vcpu *v, register_t entry_point,
> > +                      register_t context_id)
> >  {
> > -    struct vcpu *v;
> >      struct domain *d =3D current->domain;
> >      struct vcpu_guest_context *ctxt;
> >      int rc;
> >      bool is_thumb =3D entry_point & 1;
> > -    register_t vcpuid;
> > -
> > -    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> > -
> > -    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> > -        return PSCI_INVALID_PARAMETERS;
> >
> >      /* THUMB set is not allowed with 64-bit domain */
> >      if ( is_64bit_domain(d) && is_thumb )
> >          return PSCI_INVALID_ADDRESS;
> >
> > -    if ( !test_bit(_VPF_down, &v->pause_flags) )
> > -        return PSCI_ALREADY_ON;
> > -
> >      if ( (ctxt =3D alloc_vcpu_guest_context()) =3D=3D NULL )
> >          return PSCI_DENIED;
> >
> > @@ -78,11 +68,32 @@ static int do_common_cpu_on(register_t target_cpu, =
register_t entry_point,
> >      if ( rc < 0 )
> >          return PSCI_DENIED;
> >
> > -    vcpu_wake(v);
> > -
> >      return PSCI_SUCCESS;
> >  }
> >
> > +static int do_common_cpu_on(register_t target_cpu, register_t entry_po=
int,
> > +                            register_t context_id)
> > +{
> > +    int rc;
> > +    struct vcpu *v;
> > +    struct domain *d =3D current->domain;
> > +    register_t vcpuid;
> > +
> > +    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> > +
> > +    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> > +        return PSCI_INVALID_PARAMETERS;
> > +
> > +    if ( !test_bit(_VPF_down, &v->pause_flags) )
> > +        return PSCI_ALREADY_ON;
> > +
> > +    rc =3D do_setup_vcpu_ctx(v, entry_point, context_id);
> > +    if ( rc =3D=3D PSCI_SUCCESS )
> > +        vcpu_wake(v);
> > +
> > +    return rc;
> > +}
> > +
> >  static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
> >  {
> >      int32_t ret;
> > @@ -197,6 +208,48 @@ static void do_psci_0_2_system_reset(void)
> >      domain_shutdown(d,SHUTDOWN_reboot);
> >  }
> >
> > +static int32_t do_psci_1_0_system_suspend(register_t epoint, register_=
t cid)
> > +{
> > +    int32_t rc;
> > +    struct vcpu *v;
> > +    struct domain *d =3D current->domain;
> > +
> > +    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> > +    if ( is_hardware_domain(d) )
> > +        return PSCI_NOT_SUPPORTED;
> > +
> > +    /* Ensure that all CPUs other than the calling one are offline */
> > +    domain_lock(d);
> > +    for_each_vcpu ( d, v )
> > +    {
> > +        if ( v !=3D current && is_vcpu_online(v) )
> > +        {
> > +            domain_unlock(d);
> > +            return PSCI_DENIED;
> > +        }
> > +    }
> > +    domain_unlock(d);
> > +
> > +    rc =3D domain_shutdown(d, SHUTDOWN_suspend);
> > +    if ( rc )
> > +        return PSCI_DENIED;
> > +
> > +    rc =3D do_setup_vcpu_ctx(current, epoint, cid);
> > +    if ( rc !=3D PSCI_SUCCESS )
> > +    {
> > +        domain_resume_nopause(d);
> > +        return rc;
> > +    }
> > +
> > +    set_bit(_VPF_suspended, ¤t->pause_flags);
> > +
> > +    dprintk(XENLOG_DEBUG,
> > +            "Dom %u: SYSTEM_SUSPEND requested, epoint=3D%#lx, cid=3D%#=
lx\n",
> > +            d->domain_id, epoint, cid);
> > +
> > +    return rc;
> > +}
> > +
> >  static int32_t do_psci_1_0_features(uint32_t psci_func_id)
> >  {
> >      /* /!\ Ordered by function ID and not name */
> > @@ -214,6 +267,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_f=
unc_id)
> >      case PSCI_0_2_FN32_SYSTEM_OFF:
> >      case PSCI_0_2_FN32_SYSTEM_RESET:
> >      case PSCI_1_0_FN32_PSCI_FEATURES:
> > +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> > +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> >      case ARM_SMCCC_VERSION_FID:
> >          return 0;
> >      default:
> > @@ -344,6 +399,24 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs,=
 uint32_t fid)
> >          return true;
> >      }
> >
> > +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> > +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> > +    {
> > +        register_t epoint =3D PSCI_ARG(regs, 1);
> > +        register_t cid =3D PSCI_ARG(regs, 2);
> > +
> > +        if ( is_64bit_domain(current->domain) &&
> > +             fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND )
> > +        {
> > +            epoint &=3D GENMASK(31, 0);
> > +            cid &=3D GENMASK(31, 0);
> > +        }
> > +
> > +        perfc_incr(vpsci_system_suspend);
> > +        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid))=
;
> > +        return true;
> > +    }
> > +
> >      default:
> >          return false;
> >      }
> > diff --git a/xen/common/domain.c b/xen/common/domain.c
> > index 5241a1629e..624c3e2c27 100644
> > --- a/xen/common/domain.c
> > +++ b/xen/common/domain.c
> > @@ -1343,16 +1343,13 @@ int domain_shutdown(struct domain *d, u8 reason=
)
> >      return 0;
> >  }
> >
> > -void domain_resume(struct domain *d)
> > +#ifndef CONFIG_ARM
> > +static
> > +#endif
> > +void domain_resume_nopause(struct domain *d)
>
> It took me some time to understand that this function makes assumption
> that domain is already paused. As it behaves like *_unlocked()
> functions, maybe it is better to call it something like domain_resume_pau=
sed() ?

Thank you for your suggestion.

The "nopause" in the function name is intended to highlight the
difference from the previous implementation, where domain_resume()
would explicitly pause the domain before resuming it.

Pausing the domain is not required here. This function is executed on the
last running virtual CPU of the domain, so there is no need to wait for
other vCPUs to finish execution in order to perform a safe operation.
Since we are already inside the HVC trap handler, it is not possible for
other code to run or for race conditions to occur in shutdown states.
The state of other vCPUs cannot change at this point.

For other parts of the code that do not execute in the context of the
current domain, a domain pause is performed before such operations to
ensure that all virtual CPUs are blocked and not running. This guarantees
that operations which require all vCPUs to be paused/unpaused are
performed safely.

>
> >  {
> >      struct vcpu *v;
> >
> > -    /*
> > -     * Some code paths assume that shutdown status does not get reset =
under
> > -     * their feet (e.g., some assertions make this assumption).
> > -     */
> > -    domain_pause(d);
> > -
> >      spin_lock(&d->shutdown_lock);
> >
> >      d->is_shutting_down =3D d->is_shut_down =3D 0;
> > @@ -1360,13 +1357,33 @@ void domain_resume(struct domain *d)
> >
> >      for_each_vcpu ( d, v )
> >      {
> > +        /*
> > +         * No need to conditionally clear _VPF_suspended here:
> > +         * - This bit is only set on Arm64, and only after a successfu=
l suspend.
> > +         * - domain_resume_nopause() may also be called from paths oth=
er than
> > +         *   the suspend/resume flow, such as "soft-reset" actions (e.=
g.,
> > +         *   on_poweroff), as part of the Xenstore control/shutdown pr=
otocol.
> > +         *   These require guest acknowledgement to complete the opera=
tion.
> > +         * So clearing the bit unconditionally is safe.
> > +         */
> > +        clear_bit(_VPF_suspended, &v->pause_flags);
> > +
> >          if ( v->paused_for_shutdown )
> >              vcpu_unpause(v);
> >          v->paused_for_shutdown =3D 0;
> >      }
> >
> >      spin_unlock(&d->shutdown_lock);
> > +}
> >
> > +void domain_resume(struct domain *d)
> > +{
> > +    /*
> > +     * Some code paths assume that shutdown status does not get reset =
under
> > +     * their feet (e.g., some assertions make this assumption).
> > +     */
> > +    domain_pause(d);
> > +    domain_resume_nopause(d);
> >      domain_unpause(d);
> >  }
> >
> > diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
> > index fd5c9f9333..c1848d8ea6 100644
> > --- a/xen/include/xen/sched.h
> > +++ b/xen/include/xen/sched.h
> > @@ -814,6 +814,9 @@ void domain_destroy(struct domain *d);
> >  int domain_kill(struct domain *d);
> >  int domain_shutdown(struct domain *d, u8 reason);
> >  void domain_resume(struct domain *d);
> > +#ifdef CONFIG_ARM
> > +void domain_resume_nopause(struct domain *d);
> > +#endif
>
> Probably I need comment from other reviewers here. Do we really need to
> make this ARM-specific? I understand that right now it will be used only

It is done to avoid violation of MISRA C Rule 8.7:
Functions and objects should not be defined with external linkage if
they are referenced in only one translation unit

> by ARM, but still... Also, I am not big fan of that
>
> > +#ifndef CONFIG_ARM
> > +static
> > +#endif
>
> in the function definition.

This is done to avoid violation of MISRA C Rule 8.8:
The static storage class specifier shall be used in all declarations of
objects and functions that have internal linkage

>
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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From: Mykola Kvach 
Date: Tue, 26 Aug 2025 12:09:07 +0300
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Message-ID: 
Subject: Re: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Julien Grall 
Cc: xen-devel@lists.xenproject.org, Mykola Kvach , 
	Stefano Stabellini , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Andrew Cooper , Anthony PERARD , 
	Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

Hi Julien,

On Sun, Aug 24, 2025 at 12:26=E2=80=AFAM Julien Grall  wrot=
e:
>
> Hi Mykola,
>
> On 18/08/2025 09:49, Mykola Kvach wrote:
> > From: Mykola Kvach 
> >
> > This patch adds support for the PSCI SYSTEM_SUSPEND function in the vPS=
CI
> > (virtual PSCI) interface, allowing guests to request suspend via the PS=
CI
> > v1.0 SYSTEM_SUSPEND call (both 32-bit and 64-bit variants).
> >
> > The implementation:
> > - Adds SYSTEM_SUSPEND function IDs to PSCI definitions
> > - Implements trapping and handling of SYSTEM_SUSPEND in vPSCI
> > - Allows only non-hardware domains to invoke SYSTEM_SUSPEND; for the
> >    hardware domain, PSCI_NOT_SUPPORTED is returned to avoid halting the
> >    system in hwdom_shutdown() called from domain_shutdown
> > - Ensures all secondary VCPUs of the calling domain are offline before
> >    allowing suspend due to PSCI spec
> >
> > GIC and virtual timer context must be saved when the domain suspends.
>
> Can you expand a bit more on this? Is this a requirement from the Arm
> Arm? If so, please specify the specification so we can easily check.
>
> > This is done by moving the respective code in ctxt_switch_from
> > before the return that happens if the domain suspended.
>
>  From the commit message, it is unclear why we want to skip the save part=
.

I'll add extra information to the commit message.

>
> [...]
>
> > ---
> >   xen/arch/arm/domain.c                 |  17 +++--
> >   xen/arch/arm/include/asm/perfc_defn.h |   1 +
> >   xen/arch/arm/include/asm/psci.h       |   2 +
> >   xen/arch/arm/include/asm/vpsci.h      |   2 +-
> >   xen/arch/arm/vpsci.c                  | 101 ++++++++++++++++++++++---=
-
> >   xen/common/domain.c                   |  31 ++++++--
> >   xen/include/xen/sched.h               |   6 ++
> >   7 files changed, 131 insertions(+), 29 deletions(-)
> >
> > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> > index 310c578909..9e9649c4e2 100644
> > --- a/xen/arch/arm/domain.c
> > +++ b/xen/arch/arm/domain.c
> > @@ -90,6 +90,16 @@ static void ctxt_switch_from(struct vcpu *p)
> >       if ( is_idle_vcpu(p) )
> >           return;
> >
>
> It would be good to have a comment explaining what (and why) we need to
> save only partially the state while the VCPU is suspended.

Actually, nothing bad happens if we save everything except SCTLR_EL1,
which is modified in PSCI SYSTEM_SUSPEND. The only downside might be
losing some CPU cycles.

If we talk just about GIC and the Arch timer state, the relevant guidance
can be found in the Power State Coordination Interface
(DEN0022F.b, 6.8 Preserving the execution context).

Even if the guest saves the context it has access to and restores it on
resume, we only need to save the transient state. Looks like we can
do nothing with the arch timer here. And gic save function can be called
from PSCI SYSTEM_SUSPEND.

>
> > +    /* Arch timer */
> > +    p->arch.cntkctl =3D READ_SYSREG(CNTKCTL_EL1);
> > +    virt_timer_save(p);
> > +
> > +    /* VGIC */
> > +    gic_save_state(p);
> > +
> > +    if ( test_bit(_VPF_suspended, &p->pause_flags) )
> > +        return;
>
> Can you explain why we don't need an isb()?
>
> > +
> >       p2m_save_state(p);
> At least part of p2m_save_state() can't be skipped because it is
> applying a workaround on platform where AT mistakenly speculate.

Thank you for pointing that out, we need it here.

>
> [...]
>
> >
> > +static int32_t do_psci_1_0_system_suspend(register_t epoint, register_=
t cid)
> > +{
> > +    int32_t rc;
> > +    struct vcpu *v;
> > +    struct domain *d =3D current->domain;
> > +
> > +    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> > +    if ( is_hardware_domain(d) )
> > +        return PSCI_NOT_SUPPORTED;
> > +
> > +    /* Ensure that all CPUs other than the calling one are offline */
> > +    domain_lock(d);
> > +    for_each_vcpu ( d, v )
> > +    {
> > +        if ( v !=3D current && is_vcpu_online(v) )
> > +        {
> > +            domain_unlock(d);
> > +            return PSCI_DENIED;
> > +        }
> > +    }
> > +    domain_unlock(d);
> > +
> > +    rc =3D domain_shutdown(d, SHUTDOWN_suspend);
> > +    if ( rc )
> > +        return PSCI_DENIED;
> > +
> > +    rc =3D do_setup_vcpu_ctx(current, epoint, cid);
> > +    if ( rc !=3D PSCI_SUCCESS )
> > +    {
> > +        domain_resume_nopause(d);
> > +        return rc;
> > +    }
> > +
> > +    set_bit(_VPF_suspended, ¤t->pause_flags);
> > +
> > +    dprintk(XENLOG_DEBUG,
>
> I think you should use gdprintk() which will print the domain for you as
> well as appropriately ratelimit the message.
>
> That said, I would consider using gprintk() so the message can also be
> printed in a debug build.

Got it, I will use gprintk() instead as suggested. Thank you for the
recommendation.

>
> > +            "Dom %u: SYSTEM_SUSPEND requested, epoint=3D%#lx, cid=3D%#=
lx\n",
>
> For both of them you technically want to use PRIregister rather than lx.

Got it, I will use PRIregister instead as suggested. Thank you for the
recommendation.

>
> Lastly, we prefer to use %pd when printing a domain. The argument is
> 'd'. But this should not be necessary if you use gprintk().

Ok.

>
>
> > +            d->domain_id, epoint, cid);
> > +
> > +    return rc;
> > +}
> > +
> >   static int32_t do_psci_1_0_features(uint32_t psci_func_id)
> >   {
> >       /* /!\ Ordered by function ID and not name */
> > @@ -214,6 +267,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_f=
unc_id)
> >       case PSCI_0_2_FN32_SYSTEM_OFF:
> >       case PSCI_0_2_FN32_SYSTEM_RESET:
> >       case PSCI_1_0_FN32_PSCI_FEATURES:
> > +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> > +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> >       case ARM_SMCCC_VERSION_FID:
> >           return 0;
> >       default:
> > @@ -344,6 +399,24 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs,=
 uint32_t fid)
> >           return true;
> >       }
> >
> > +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> > +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> > +    {
> > +        register_t epoint =3D PSCI_ARG(regs, 1);
> > +        register_t cid =3D PSCI_ARG(regs, 2);
> > +
> > +        if ( is_64bit_domain(current->domain) &&
>
> Shouldn't this be removed so the check also apply for 32-bit domain on
> 64-bit system?

AFAIK, this question was already addressed in a previous version of
this patch series:
https://patchew.org/Xen/cover.1751020456.git.mykola._5Fkvach@epam.com/07227=
0e0940b6bcc2743d56a336363f4719ba60a.1751020456.git.mykola._5Fkvach@epam.com=
/#7070f416-119c-49f8-acd0-82c6e31f0fc6@xen.org

>
> > +             fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND )
>  > +        {> +            epoint &=3D GENMASK(31, 0);
> > +            cid &=3D GENMASK(31, 0);
> > +        }
> > +
> > +        perfc_incr(vpsci_system_suspend);
> > +        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid))=
;
> > +        return true;
> > +    }
> > +
> >       default:
> >           return false;
> >       }
> > diff --git a/xen/common/domain.c b/xen/common/domain.c
> > index 5241a1629e..624c3e2c27 100644
> > --- a/xen/common/domain.c
> > +++ b/xen/common/domain.c
> > @@ -1343,16 +1343,13 @@ int domain_shutdown(struct domain *d, u8 reason=
)
> >       return 0;
> >   }
> >
> > -void domain_resume(struct domain *d)
> > +#ifndef CONFIG_ARM
> > +static
> > +#endif
>
> I am not sure who suggests this but personally, I dislike using
> CONFIG_ in common code. I also think this is worse for hiding the
> "static" keyword.
>
> For the latter, I think it would be better to provide a separate helper
> that can be #ifdef.

Will do. I will provide a separate helper as suggested.


>
> [...]
>
> Cheers,
>
> --
> Julien Grall
>

Best regards,
Mykola


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In-Reply-To: 
From: Mykola Kvach 
Date: Tue, 26 Aug 2025 12:09:34 +0300
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Message-ID: 
Subject: Re: [PATCH v9 3/4] SUPPORT.md: Document PSCI SYSTEM_SUSPEND support
 for guests
To: Julien Grall 
Cc: xen-devel@lists.xenproject.org, Mykola Kvach , 
	Andrew Cooper , Anthony PERARD , 
	Michal Orzel , Jan Beulich , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Stefano Stabellini 
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

Hi Julien,

On Sun, Aug 24, 2025 at 12:31=E2=80=AFAM Julien Grall  wrot=
e:
>
> Hi Mykola,
>
> On 18/08/2025 09:49, Mykola Kvach wrote:
> > From: Mykola Kvach 
> >
> > Add a new entry under the "Virtual Hardware, QEMU" section documenting
> > support for the optional PSCI SYSTEM_SUSPEND function exposed to guests=
.
> >
> > This function is available via the virtual PSCI (vPSCI) interface and
> > allows guest domains (domUs) to initiate system suspend operations.
> >
> > The feature is currently marked as Experimental.
> >
> > Signed-off-by: Mykola Kvach 
> > ---
> > Changes in v6:
> > - Dropped the generic guest PSCI support entry (merged in a separate pa=
tch)
> > - This patch now documents only the SYSTEM_SUSPEND optional function
> > - Reworded commit message to match the final form after rebase
> >
> > Changes in v5:
> > - Dropped ARM/PSCI entry: this refers to internal use of PSCI SMC calls=
,
> >    which is not relevant for SUPPORT.md
> > - Added a dedicated entry for PSCI SYSTEM_SUSPEND instead of generic gu=
est
> >    PSCI info; guest PSCI support was documented in a separate patch
> > ---
> >   SUPPORT.md | 5 +++--
> >   1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/SUPPORT.md b/SUPPORT.md
> > index 6a82a92189..b5ab049b52 100644
> > --- a/SUPPORT.md
> > +++ b/SUPPORT.md
> > @@ -962,8 +962,9 @@ Emulated PSCI interface exposed to guests. We suppo=
rt all mandatory
> >   functions of PSCI 1.1. See below for the list of optional PSCI call
> >   implemented and their status.
> >
> > -   Status, Mandatory: Supported
> > -   Status, MIGRATE_INFO_TYPE: Supported
> > +    Status, Mandatory: Supported
> > +    Status, MIGRATE_INFO_TYPE: Supported
> > +    Status, SYSTEM_SUSPEND: Experimental
>
> Experimental implies the feature is not complete. But it is unclear to
> me what is missing (or I probably forgotten). Can this be clarified in
> the commit message?
>
> If there is nothing, then I think it can be a tech preview.

I initially thought that we would need to add a "xl suspend" command
in order to allow suspending another domain via the control/hardware
domain. However, after your question I reconsidered it and realized
that this functionality is not directly related to vPSCI, but rather
to Xen system suspend support.

So, I will change it to "Tech Preview" as you proposed. Thank you!

>
> Cheers,
>
> --
> Julien Grall
>

Best regards,
Mykola


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, Juergen Gross , Andrew Cooper
	, "Orzel, Michal" , Julien
 Grall , =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Stefano Stabellini ,
	"xen-devel@lists.xenproject.org" 
Subject: RE: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq
 para
Thread-Topic: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq
 para
Thread-Index: AQHcE1LyQ0lYyaNtv02FRdV+NHpcFrRzhX0AgAESjyCAAAlHgIAACnwg
Date: Tue, 26 Aug 2025 09:12:42 +0000
Message-ID:
 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-12-Penny.Zheng@amd.com>
 
 
 
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Subject: Re: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
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To: Mykola Kvach 
Cc: xen-devel@lists.xenproject.org, Mykola Kvach ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: 
 <205b2b354ff1d34d0e9ec4777ca3c94492f6d9d1.1755506449.git.mykola_kvach@epam.com>
 <9ab99307-9594-4cbc-9c7a-b1221575d41c@xen.org>
 
From: Julien Grall 
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Hi Mykola,

On 26/08/2025 10:09, Mykola Kvach wrote:
>> Shouldn't this be removed so the check also apply for 32-bit domain on
>> 64-bit system?
> 
> AFAIK, this question was already addressed in a previous version of
> this patch series:
> https://patchew.org/Xen/cover.1751020456.git.mykola._5Fkvach@epam.com/072270e0940b6bcc2743d56a336363f4719ba60a.1751020456.git.mykola._5Fkvach@epam.com/#7070f416-119c-49f8-acd0-82c6e31f0fc6@xen.org

Sure. For 32-bit domain, in theory the top bits should be zeroed. But 
AFAIK, there is no harm to zero them again and it would avoid someone to 
wonder why this is protected by is_64bit_domain().

So unless there is a strong reason to keep, I would rather prefer if we 
remove the 64-bit.

Cheers,

-- 
Julien Grall



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Date: Tue, 26 Aug 2025 09:26:46 +0000
To: Anthony PERARD 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v4 6/8] tools/xl: enable NS16550-compatible UART emulator for HVM (x86)
Message-ID: 
In-Reply-To: 
References: <20250731192130.3948419-1-dmukhin@ford.com> <20250731192130.3948419-7-dmukhin@ford.com> 
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On Mon, Aug 25, 2025 at 04:49:58PM +0200, Anthony PERARD wrote:
> On Thu, Jul 31, 2025 at 07:22:12PM +0000, dmkhn@proton.me wrote:
> > diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
> > index 5362fb0e9a6f..e1d012274eaf 100644
> > --- a/docs/man/xl.cfg.5.pod.in
> > +++ b/docs/man/xl.cfg.5.pod.in
> > @@ -3032,14 +3032,17 @@ the domain was created.
> >  This requires hardware compatibility with the requested version, eithe=
r
> >  natively or via hardware backwards compatibility support.
> >
> > -=3Ditem B
> > +=3Ditem B
>=20
> This syntax here would inditace that `vuart` takes a list of items. You
> could write instead:
>=20
>     vuart=3D"UART"
>=20
> which seems more in line with the rest of the man page. Then you can add
> some thing like "with UART been one of "sbsa_uart" or "ns16550". It's
> possible to also have a sublist, like the `tee` option have.

OK, will do.

>=20
>=20
> >  To enable vuart console, user must specify the following option in the
> > -VM config file:
> > +VM config file, e.g:
> >
> > +```
>=20
> This file isn't in markdown, it's in perlpod.

Whoops, muscle memory. Thanks.

>=20
> >  vuart =3D "sbsa_uart"
> > +```
> >
> > -Currently, only the "sbsa_uart" model is supported for ARM.
> > +Currently, "sbsa_uart" (ARM) and "ns16550" (x86) are the only supporte=
d
> > +UART models.
> >
> >  =3Dback
> >
> > diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.=
c
> > index 4a19a8d22bdf..f4721b24763c 100644
> > --- a/tools/libs/light/libxl_arm.c
> > +++ b/tools/libs/light/libxl_arm.c
> > @@ -92,14 +92,26 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc=
,
> >      uint32_t virtio_mmio_irq =3D GUEST_VIRTIO_MMIO_SPI_FIRST;
> >      int rc;
> >
> > -    /*
> > -     * If pl011 vuart is enabled then increment the nr_spis to allow a=
llocation
> > -     * of SPI VIRQ for pl011.
> > -     */
> > -    if (d_config->b_info.arch_arm.vuart =3D=3D LIBXL_VUART_TYPE_SBSA_U=
ART) {
> > +    switch ( d_config->b_info.vuart )
> > +    {
> > +    case LIBXL_VUART_TYPE_SBSA_UART:
> > +        /*
> > +         * If pl011 vuart is enabled then increment the nr_spis to all=
ow
> > +         * allocation of SPI VIRQ for pl011.
> > +         */
> >          nr_spis +=3D (GUEST_VPL011_SPI - 32) + 1;
> >          vuart_irq =3D GUEST_VPL011_SPI;
> >          vuart_enabled =3D true;
> > +        break;
> > +
> > +    case LIBXL_VUART_TYPE_NS16550:
> > +        LOG(ERROR, "unsupported UART emulator %d\n", d_config->b_info.=
vuart);
>=20
> This seems too late in libxl.  I think checking if the config value is
> correct could be done in one of the *_setdefault() like many other
> config check are done. There's
> libxl__arch_domain_build_info_setdefault() that could be used.

Thanks for the pointer.

>=20
> > +        abort();
> > +        break;
> > +
> > +    case LIBXL_VUART_TYPE_UNKNOWN:
> > +    default:
> > +        break;
> >      }
> >
> >      for (i =3D 0; i < d_config->num_disks; i++) {
> > diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_=
types.idl
> > index fe251649f346..fd60c2b26764 100644
> > --- a/tools/libs/light/libxl_types.idl
> > +++ b/tools/libs/light/libxl_types.idl
> > @@ -276,6 +276,7 @@ libxl_checkpointed_stream =3D Enumeration("checkpoi=
nted_stream", [
> >  libxl_vuart_type =3D Enumeration("vuart_type", [
> >      (0, "unknown"),
> >      (1, "sbsa_uart"),
> > +    (2, "ns16550"),
> >      ])
> >
> >  libxl_vkb_backend =3D Enumeration("vkb_backend", [
> > @@ -722,7 +723,6 @@ libxl_domain_build_info =3D Struct("domain_build_in=
fo",[
> >
> >
> >      ("arch_arm", Struct(None, [("gic_version", libxl_gic_version),
> > -                               ("vuart", libxl_vuart_type),
>=20
> arch_arm.vuart is part of libxl's API, it can't be removed. There's some
> explanation about "libxl API compatibility" at the top of "libxl.h".
> But for this change, you could add `vuart` to `arch_x86`, or if you want
> to add `vuart` at the root like you did, you'll need to check that both
> `arch_arm.vuart` and `vuart` aren't set at the same time, and have one
> of the *_setdefault() function do the work of migrating the option.
>=20
> You'll need also a LIBXL_HAVE_* macro in libxl.h, probably named
> LIBXL_HAVE_VUART_NS16550.

Thanks for details, I will proceed with option 2, adding `vuart` at the roo=
t.

>=20
> >                                 ("sve_vl", libxl_sve_type),
> >                                 ("nr_spis", uint32, {'init_val': 'LIBXL=
_NR_SPIS_DEFAULT'}),
> >                                ])),
> > @@ -739,6 +739,7 @@ libxl_domain_build_info =3D Struct("domain_build_in=
fo",[
> >
> >      ("vpmu", libxl_defbool),
> >      ("trap_unmapped_accesses", libxl_defbool),
> > +    ("vuart", libxl_vuart_type),
> >
> >      ], dir=3DDIR_IN,
> >         copy_deprecated_fn=3D"libxl__domain_build_info_copy_deprecated"=
,
> > diff --git a/tools/libs/light/libxl_x86.c b/tools/libs/light/libxl_x86.=
c
> > index 60d4e8661c93..0f039ca65a88 100644
> > --- a/tools/libs/light/libxl_x86.c
> > +++ b/tools/libs/light/libxl_x86.c
> > @@ -2,6 +2,45 @@
> >  #include "libxl_arch.h"
> >  #include 
> >
> > +static void libxl__arch_domain_vuart_assert(
> > +    libxl__gc *gc,
> > +    libxl_domain_config *d_config,
> > +    struct xen_domctl_createdomain *config)
> > +{
> > +    LOG(ERROR, "unsupported UART emulator %d\n", d_config->b_info.vuar=
t);
> > +    abort();
>=20
> The name of the function is wrong. It doens't assert anything, and just
> abort...
> I don't think this function is useful.

Yeah, I mostly added it to avoid typing the same error message several time=
s.=20
Will remove.

>=20
> Also, don't abort() for configuration error, you need to return an error
> instead.

Ack.

>=20
> > +}
> > +
> > +static void libxl__arch_domain_vuart_unsupported(
> > +    libxl__gc *gc,
> > +    libxl_domain_config *d_config,
> > +    struct xen_domctl_createdomain *config)
> > +{
> > +    if ( d_config->b_info.vuart !=3D LIBXL_VUART_TYPE_UNKNOWN )
> > +        libxl__arch_domain_vuart_assert(gc, d_config, config);
>=20
> This function have also a bad name, it doesn't check if a uart is
> unsupported.

Will rework.

>=20
> > +}
> > +
> > +static void libxl__arch_domain_vuart_enable(
> > +    libxl__gc *gc,
> > +    libxl_domain_config *d_config,
> > +    struct xen_domctl_createdomain *config)
> > +{
> > +    switch ( d_config->b_info.vuart )
> > +    {
> > +    case LIBXL_VUART_TYPE_SBSA_UART:
> > +        libxl__arch_domain_vuart_assert(gc, d_config, config);
> > +        break;
> > +
> > +    case LIBXL_VUART_TYPE_NS16550:
> > +        config->arch.emulation_flags |=3D XEN_X86_EMU_NS16550;
> > +        break;
> > +
> > +    case LIBXL_VUART_TYPE_UNKNOWN:
> > +    default:
> > +        break;
> > +    }
> > +}
> > +
> >  int libxl__arch_domain_prepare_config(libxl__gc *gc,
> >                                        libxl_domain_config *d_config,
> >                                        struct xen_domctl_createdomain *=
config)
> > @@ -9,14 +48,17 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
> >      switch(d_config->c_info.type) {
> >      case LIBXL_DOMAIN_TYPE_HVM:
> >          config->arch.emulation_flags =3D (XEN_X86_EMU_ALL & ~XEN_X86_E=
MU_VPCI);
> > +        libxl__arch_domain_vuart_enable(gc, d_config, config);
> >          if (!libxl_defbool_val(d_config->b_info.u.hvm.pirq))
> >              config->arch.emulation_flags &=3D ~XEN_X86_EMU_USE_PIRQ;
> >          break;
> >      case LIBXL_DOMAIN_TYPE_PVH:
> >          config->arch.emulation_flags =3D XEN_X86_EMU_LAPIC;
> > +        libxl__arch_domain_vuart_unsupported(gc, d_config, config);
> >          break;
> >      case LIBXL_DOMAIN_TYPE_PV:
> >          config->arch.emulation_flags =3D 0;
> > +        libxl__arch_domain_vuart_unsupported(gc, d_config, config);
> >          break;
> >      default:
> >          abort();
>=20
> Thanks,

Thanks for review!

--
Denis

>=20
> --
> Anthony PERARD



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Date: Tue, 26 Aug 2025 09:28:52 +0000
To: Anthony PERARD 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v16 2/4] tools/include: move xc_bitops.h to xen-tools/bitops.h
Message-ID: 
In-Reply-To: 
References: <20250812223024.2364749-1-dmukhin@ford.com> <20250812223024.2364749-3-dmukhin@ford.com> 
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On Mon, Aug 25, 2025 at 11:30:20AM +0200, Anthony PERARD wrote:
> On Tue, Aug 12, 2025 at 10:30:45PM +0000, dmkhn@proton.me wrote:
> > diff --git a/tools/libs/guest/xg_dom_elfloader.c b/tools/libs/guest/xg_=
dom_elfloader.c
> > index f17930d98bf7..8531e90f8e21 100644
> > --- a/tools/libs/guest/xg_dom_elfloader.c
> > +++ b/tools/libs/guest/xg_dom_elfloader.c
> > @@ -25,8 +25,9 @@
> >  #include 
> >  #include 
> >
> > +#include 
>=20
> It doesn't looks like xg_dom_elfloader.c is using anything from
> bitops.h. The last use of it was probably removed in ed04ca95981f
> ("libelf: rewrite symtab/strtab loading")

Ack.

>=20
> > +
> >  #include "xg_private.h"
> > -#include "xc_bitops.h"
> >
> >  #define XEN_VER "xen-3.0"
> >
> > diff --git a/tools/libs/guest/xg_dom_hvmloader.c b/tools/libs/guest/xg_=
dom_hvmloader.c
> > index 39e1e5f579a7..0f569c20c522 100644
> > --- a/tools/libs/guest/xg_dom_hvmloader.c
> > +++ b/tools/libs/guest/xg_dom_hvmloader.c
> > @@ -24,8 +24,9 @@
> >  #include 
> >  #include 
> >
> > +#include 
> > +
>=20
> I think there's two reason to remove this include:
> - it doesn't looks like xg_dom_hvmloader.c is using any macro from it.
> - bitops.h is already included by xg_private.h.

Will remove.

>=20
>=20
> >  #include "xg_private.h"
> > -#include "xc_bitops.h"
> >
> >  /* -------------------------------------------------------------------=
----- */
> >  /* parse elf binary                                                   =
      */
> > diff --git a/tools/libs/guest/xg_sr_common.h b/tools/libs/guest/xg_sr_c=
ommon.h
> > index 2f058ee3a6ff..2e583f2eac72 100644
> > --- a/tools/libs/guest/xg_sr_common.h
> > +++ b/tools/libs/guest/xg_sr_common.h
> > @@ -2,11 +2,10 @@
> >  #define __COMMON__H
> >
> >  #include 
> > +#include 
>=20
> It's already included in xg_private.h, so this feels unnecessary.

Ack.

> >
> >  #include "xg_private.h"
> >  #include "xg_save_restore.h"
> > -#include "xc_bitops.h"
> > -
>=20
>=20
> If the extraneous includes could be removed, that would be nice. In
> anycase:
> Acked-by: Anthony PERARD 

Thanks

>=20
> Thanks,
>=20
> --
> Anthony PERARD
>=20



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From: Dmytro Firsov 
To: "Orzel, Michal" , "xen-devel@lists.xenproject.org"
	
CC: Bertrand Marquis , Rahul Singh
	, Stefano Stabellini , Julien
 Grall , Volodymyr Babchuk 
Subject: Re: [PATCH] xen/arm: smmuv3: Add cache maintenance for non-coherent
 SMMU queues
Thread-Topic: [PATCH] xen/arm: smmuv3: Add cache maintenance for non-coherent
 SMMU queues
Thread-Index: AQHcBuKhRQAjcpitXUCHafCQJ8zznbRuazEAgAZj94A=
Date: Tue, 26 Aug 2025 09:47:54 +0000
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References:
 <24567cc1630b1577c33939ff71d67fb2ebe5572f.1754491424.git.dmytro_firsov@epam.com>
 
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References:  <205b2b354ff1d34d0e9ec4777ca3c94492f6d9d1.1755506449.git.mykola_kvach@epam.com>
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In-Reply-To: <67d58304-146e-480e-a689-440afe7828aa@xen.org>
From: Mykola Kvach 
Date: Tue, 26 Aug 2025 12:48:17 +0300
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Message-ID: 
Subject: Re: [PATCH v9 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Julien Grall 
Cc: xen-devel@lists.xenproject.org, Mykola Kvach , 
	Stefano Stabellini , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Andrew Cooper , Anthony PERARD , 
	Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
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On Tue, Aug 26, 2025 at 12:26=E2=80=AFPM Julien Grall  wrot=
e:
>
> Hi Mykola,
>
> On 26/08/2025 10:09, Mykola Kvach wrote:
> >> Shouldn't this be removed so the check also apply for 32-bit domain on
> >> 64-bit system?
> >
> > AFAIK, this question was already addressed in a previous version of
> > this patch series:
> > https://patchew.org/Xen/cover.1751020456.git.mykola._5Fkvach@epam.com/0=
72270e0940b6bcc2743d56a336363f4719ba60a.1751020456.git.mykola._5Fkvach@epam=
.com/#7070f416-119c-49f8-acd0-82c6e31f0fc6@xen.org
>
> Sure. For 32-bit domain, in theory the top bits should be zeroed. But
> AFAIK, there is no harm to zero them again and it would avoid someone to
> wonder why this is protected by is_64bit_domain().
>
> So unless there is a strong reason to keep, I would rather prefer if we
> remove the 64-bit.

Understood, I=E2=80=99ll remove the 64-bit domain check as suggested.

>
> Cheers,
>
> --
> Julien Grall
>

Best Regards,
Mykola


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Date: Tue, 26 Aug 2025 09:48:38 +0000
To: Anthony PERARD 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall 
Subject: Re: [PATCH v16 3/4] tools/tests: introduce unit tests for domain ID allocator
Message-ID: 
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References: <20250812223024.2364749-1-dmukhin@ford.com> <20250812223024.2364749-4-dmukhin@ford.com> 
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On Mon, Aug 25, 2025 at 03:47:39PM +0200, Anthony PERARD wrote:

Thanks for review!

Will address in the next revision.
Please see some responses below.

> On Tue, Aug 12, 2025 at 10:30:50PM +0000, dmkhn@proton.me wrote:
> > diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignor=
e
> > new file mode 100644
> > index 000000000000..0e02715159c2
> > --- /dev/null
> > +++ b/tools/tests/domid/.gitignore
> > @@ -0,0 +1,3 @@
> > +*.o
>=20
> "*.o" is already in the .gitignore at the root of the project. I don't
> think it's useful here.

Ack.

>=20
> > +generated
> > +test-domid
> > diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile
> > new file mode 100644
> > index 000000000000..0a124a8bfc76
> > --- /dev/null
> > +++ b/tools/tests/domid/Makefile
> > @@ -0,0 +1,84 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +#
> > +# Unit tests for domain ID allocator.
> > +#
> > +# Copyright 2025 Ford Motor Company
> > +
> > +XEN_ROOT=3D$(CURDIR)/../../..
> > +include $(XEN_ROOT)/tools/Rules.mk
> > +
> > +TESTS :=3D test-domid
> > +
> > +strip-list =3D $(sort $(strip $(foreach x,$(1),$(strip $(x)))))
>=20
> What's that macro for? Also, what's a "list"?
>=20
> > +define list-c-headers
> > +$(shell sed -n -r \
>=20
> Could you use "-E" instead of "-r"? (-r might not work on FreeBSD)

re: FreeBSD: I've found there's a dedicated pipeline for Xen on FreeBSD
(cirrus CI), but I did not figure how to trigger it, will appreciate help
with that.

>=20
> > +    's/^[ \t]*# *include[ \t]*[<"]([^">]+)[">].*/\1/p' $(1) 2>/dev/nul=
l)
> > +endef
> > +
> > +define emit-harness-nested-rule
> > +$(1): $(CURDIR)/harness.h
> > +=09mkdir -p $$(dir $$@)
>=20
> You can use $(@D) instead of $(dir $@). The only difference is a /
> not present at the end.
>=20
> > +=09ln -sf $$^ $$@
>=20
> This should use $<, I don't think the command is going to work if
> there's multiple prerequisite.
>=20
> > +endef
> > +
> > +define emit-harness-rules
> > +ifneq ($(strip $(3)),)
>=20
> How many time do you need to call $(strip) ?
> Also, I think I would prefer to have $(if $(strip $(3)), [the rest])
> rather than actually evaluating code and generating code that we already
> know is isn't going to be executed.
>=20
> > +$(foreach h,$(3),$(call emit-harness-nested-rule,$(CURDIR)/generated/$=
(h)))
> > +vpath $(1) $(2)
> > +$(1:.c=3D.o): $(addprefix $(CURDIR)/generated/,$(3))
> > +endif
> > +endef
>=20
> This macro fails if there's more than one "#include" in "domid.c".
>=20
> And if there's no "#include" in "domid.c", then Make doesn't know how to
> make "domid.o" for "test-domid".
>=20
> > +
> > +define vpath-with-harness-deps
> > +$(call emit-harness-rules,$(1),$(2),\
> > +    $(call strip-list,$(call list-c-headers,$(2)$(1))))
> > +endef
> > +
> > +.PHONY: all
> > +all: $(TESTS)
> > +
> > +.PHONY: run
> > +run: $(TESTS)
> > +=09$(foreach t,$(TESTS),./$(t);)
>=20
> This recipe doesn't work as expected. You need `set -e` or only the last
> tests count.
>=20
> > +
> > +.PHONY: clean
> > +clean:
> > +=09$(RM) -rf $(CURDIR)/generated
>=20
> $(RM) already contain the '-f' option, no need to add it a second time.
>=20
> Also, we expected Make to run all commands in recipe from $(CURDIR), so
> adding $(CURDIR) is unnecessary, could potentially be an issue.
>=20
> > +=09$(RM) -- *.o $(TESTS) $(DEPS_RM)
> > +
> > +.PHONY: distclean
> > +distclean: clean
> > +=09$(RM) -- *~
> > +
> > +.PHONY: install
> > +install: all
> > +=09$(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests
> > +=09$(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests
> > +
> > +.PHONY: uninstall
> > +uninstall:
> > +=09$(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid
> > +
> > +CFLAGS +=3D -D__XEN_TOOLS__
> > +# find-next-bit.c
> > +CFLAGS +=3D '-DEXPORT_SYMBOL(x)=3D' \
> > +          -Dfind_first_bit \
> > +          -Dfind_first_zero_bit \
> > +          -Dfind_next_bit \
> > +          -Dfind_next_bit_le \
> > +          -Dfind_next_zero_bit_le
> > +CFLAGS +=3D $(APPEND_CFLAGS)
> > +CFLAGS +=3D $(CFLAGS_xeninclude)
> > +CFLAGS +=3D -I./generated/
> > +
> > +LDFLAGS +=3D $(APPEND_LDFLAGS)
> > +
> > +vpath find-next-bit.c $(XEN_ROOT)/xen/lib/
> > +# Ubuntu {16,18}.04 need single eval at the call site.
>=20
> I'd rather see a comment about what's the macro is about rather that a
> comment some Linux distribution. Our target is GNU Make 3.80, without
> regards to a particular distribution. (Also I don't think it's useful to
> point out that `eval` is needed for older version of Make, at least in
> our project.)

Ack.

>=20
> > +$(eval $(call vpath-with-harness-deps,domid.c,$(XEN_ROOT)/xen/common/)=
)
> > +
> > +test-domid: domid.o find-next-bit.o test-domid.o
> > +=09$(CC) $^ -o $@ $(LDFLAGS)
> > +
> > +-include $(DEPS_INCLUDE)
> > diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-do=
mid.c
> > new file mode 100644
> > index 000000000000..51a88a6a9550
> > --- /dev/null
> > +++ b/tools/tests/domid/test-domid.c
> > @@ -0,0 +1,93 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Unit tests for domain ID allocator.
> > + *
> > + * Copyright 2025 Ford Motor Company
> > + */
> > +
> > +#include "harness.h"
> > +
> > +#define verify(exp, fmt, args...) do { \
> > +    if ( !(exp) ) \
> > +        printf(fmt, ## args); \
> > +    assert(exp); \
>=20
> Relying on assert() for the test isn't wise. It's useful for developing
> and debugging because it calls abort(), but they can easily be get rid of=
,
> by simply building with -DNDEBUG. Could you maybe replace it with exit()
> since you already check the condition?

Yep, will do.

>=20
>=20
> Thanks,
>=20
> --
> Anthony PERARD
>=20



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Date: Tue, 26 Aug 2025 09:51:17 +0000
To: Julien Grall 
From: dmkhn@proton.me
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, anthony.perard@vates.tech, jbeulich@suse.com, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall , Alejandro Vallejo 
Subject: Re: [PATCH v16 1/4] xen/domain: unify domain ID allocation
Message-ID: 
In-Reply-To: <304cffd8-498d-447f-a8b0-cda694393ec8@xen.org>
References: <20250812223024.2364749-1-dmukhin@ford.com> <20250812223024.2364749-2-dmukhin@ford.com> <304cffd8-498d-447f-a8b0-cda694393ec8@xen.org>
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On Wed, Aug 20, 2025 at 10:33:16PM +0100, Julien Grall wrote:
> Hi Denis,
>=20
> On 12/08/2025 23:30, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Currently, there are two different domain ID allocation implementations=
:
> >
> >    1) Sequential IDs allocation in dom0less Arm code based on max_init_=
domid;
> >
> >    2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not us=
e
> >       max_init_domid (both Arm and x86).
> >
> > The domain ID allocation covers dom0 or late hwdom, predefined domains,
> > post-boot domains, excluding Xen system domains (domid >=3D
> > DOMID_FIRST_RESERVED).
> >
> > It makes sense to have a common helper code for such task across archit=
ectures
> > (Arm and x86) and between dom0less / toolstack domU allocation.
> >
> > Note, fixing dependency on max_init_domid is out of scope of this patch=
.
> >
> > Wrap the domain ID allocation as an arch-independent function domid_all=
oc() in
> > new common/domid.c based on the bitmap.
> >
> > Allocation algorithm:
> > - If an explicit domain ID is provided, verify its availability and use=
 it if
> >    ID is not used;
> > - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERV=
ED-1],
> >    starting from the last used ID.
> >    Implementation guarantees that two consecutive calls will never retu=
rn the
> >    same ID. ID#0 is reserved for the first boot domain (currently, dom0=
) and
> >    excluded from the allocation range.
> >
> > Remove is_free_domid() helper as it is not needed now.
> >
> > No functional change intended.
> >
> > Signed-off-by: Denis Mukhin 
> > Reviewed-by: Julien Grall 
>  > Reviewed-by: Alejandro Vallejo 
>  > ---> Changes since v15:
> > - fixup for check after the first pass in the bitarray in domid_alloc()
>=20
> This was a good catch from Jan. Has a unit-test been added for this issue=
?

No, I did not update the test suite, will do.

>=20
> Anyway, my reviewed-by holds.

Thanks.

>=20
> Cheers,
>=20
> --
> Julien Grall
>=20



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Date: Tue, 26 Aug 2025 09:52:00 +0000
To: Alejandro Vallejo 
From: dmkhn@proton.me
Cc: Jan Beulich , andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall , xen-devel@lists.xenproject.org
Subject: Re: [PATCH v16 1/4] xen/domain: unify domain ID allocation
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On Thu, Aug 21, 2025 at 12:29:23PM +0200, Alejandro Vallejo wrote:
> On Thu Aug 21, 2025 at 9:16 AM CEST, Jan Beulich wrote:
> > On 20.08.2025 01:58, dmkhn@proton.me wrote:
> >> On Thu, Aug 14, 2025 at 09:11:11AM +0200, Jan Beulich wrote:
> >>> On 13.08.2025 00:30, dmkhn@proton.me wrote:
> >>>> From: Denis Mukhin 
> >>>>
> >>>> Currently, there are two different domain ID allocation implementati=
ons:
> >>>>
> >>>>   1) Sequential IDs allocation in dom0less Arm code based on max_ini=
t_domid;
> >>>>
> >>>>   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not =
use
> >>>>      max_init_domid (both Arm and x86).
> >>>>
> >>>> The domain ID allocation covers dom0 or late hwdom, predefined domai=
ns,
> >>>> post-boot domains, excluding Xen system domains (domid >=3D
> >>>> DOMID_FIRST_RESERVED).
> >>>>
> >>>> It makes sense to have a common helper code for such task across arc=
hitectures
> >>>> (Arm and x86) and between dom0less / toolstack domU allocation.
> >>>>
> >>>> Note, fixing dependency on max_init_domid is out of scope of this pa=
tch.
> >>>>
> >>>> Wrap the domain ID allocation as an arch-independent function domid_=
alloc() in
> >>>> new common/domid.c based on the bitmap.
> >>>>
> >>>> Allocation algorithm:
> >>>> - If an explicit domain ID is provided, verify its availability and =
use it if
> >>>>   ID is not used;
> >>>> - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RES=
ERVED-1],
> >>>>   starting from the last used ID.
> >>>>   Implementation guarantees that two consecutive calls will never re=
turn the
> >>>>   same ID. ID#0 is reserved for the first boot domain (currently, do=
m0) and
> >>>>   excluded from the allocation range.
> >>>>
> >>>> Remove is_free_domid() helper as it is not needed now.
> >>>>
> >>>> No functional change intended.
> >>>>
> >>>> Signed-off-by: Denis Mukhin 
> >>>> Reviewed-by: Julien Grall 
> >>>> Reviewed-by: Alejandro Vallejo 
> >>>> ---
> >>>> Changes since v15:
> >>>> - fixup for check after the first pass in the bitarray in domid_allo=
c()
> >>>> - trivial renaming for the local variable in domid_alloc()
> >>>> - kept Julien's R-b, added Alejandro's R-b
> >>>
> >>> Just to mention: My take is that this kind of a fix ought to invalida=
te all
> >>> earlier R-b. It's not just a cosmetic change, after all.
> >>
> >> Sorry for the hiccup here, did not mean to overrule the review process=
.
> >>
> >> My bold assumption was that in case of small fixups like this it is
> >> satisfactory to carry over previous acks.
> >
> > Acks may be okay to keep, but imo R-b need dropping when an actual bug =
was
> > fixed.
>=20
> I don't know. Unless the bugfix involves a change in the code with wide r=
eaching
> consequences I'd say it's reasonable to keep them. But that's something f=
or you
> (the committers) to decide, and this just my .02 cents.
>=20
> > Irrespective of how severe the bug was.
>=20
> It's not so much about the severity (imo), as the behavioural differences
> involved in the fixup. In this case (afaics?) it's a straight s/=3D=3D/>=
=3D/, which is
> self-contained and has no wide-reaching side effects at all.
>=20
> >
> >> I asked (matrix) both Julien and Alejandro to re-review and confirm.
> >
> > While good to ask, that's of limited use. It'll be impossible later on =
to
> > figure whether such a confirmation was given. Decisions (and acks and a=
like
> > effectively fall into that category) need to be on the list, to be able=
 to
> > locate them later on.
> >
> > Jan
>=20
> He meant he reached out to ask for an in-list confirmation. As far as I'm
> concerned, my R-by still holds.

Thanks

>=20
> Cheers,
> Alejandro



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Date: Tue, 26 Aug 2025 09:53:07 +0000
To: Alejandro Vallejo 
From: dmkhn@proton.me
Cc: Jan Beulich , andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall , xen-devel@lists.xenproject.org
Subject: Re: [PATCH v16 1/4] xen/domain: unify domain ID allocation
Message-ID: 
In-Reply-To: 
References: <20250812223024.2364749-1-dmukhin@ford.com> <20250812223024.2364749-2-dmukhin@ford.com>    
Feedback-ID: 123220910:user:proton
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On Thu, Aug 21, 2025 at 12:29:23PM +0200, Alejandro Vallejo wrote:
> On Thu Aug 21, 2025 at 9:16 AM CEST, Jan Beulich wrote:
> > On 20.08.2025 01:58, dmkhn@proton.me wrote:
> >> On Thu, Aug 14, 2025 at 09:11:11AM +0200, Jan Beulich wrote:
> >>> On 13.08.2025 00:30, dmkhn@proton.me wrote:
> >>>> From: Denis Mukhin 
> >>>>
> >>>> Currently, there are two different domain ID allocation implementati=
ons:
> >>>>
> >>>>   1) Sequential IDs allocation in dom0less Arm code based on max_ini=
t_domid;
> >>>>
> >>>>   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not =
use
> >>>>      max_init_domid (both Arm and x86).
> >>>>
> >>>> The domain ID allocation covers dom0 or late hwdom, predefined domai=
ns,
> >>>> post-boot domains, excluding Xen system domains (domid >=3D
> >>>> DOMID_FIRST_RESERVED).
> >>>>
> >>>> It makes sense to have a common helper code for such task across arc=
hitectures
> >>>> (Arm and x86) and between dom0less / toolstack domU allocation.
> >>>>
> >>>> Note, fixing dependency on max_init_domid is out of scope of this pa=
tch.
> >>>>
> >>>> Wrap the domain ID allocation as an arch-independent function domid_=
alloc() in
> >>>> new common/domid.c based on the bitmap.
> >>>>
> >>>> Allocation algorithm:
> >>>> - If an explicit domain ID is provided, verify its availability and =
use it if
> >>>>   ID is not used;
> >>>> - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RES=
ERVED-1],
> >>>>   starting from the last used ID.
> >>>>   Implementation guarantees that two consecutive calls will never re=
turn the
> >>>>   same ID. ID#0 is reserved for the first boot domain (currently, do=
m0) and
> >>>>   excluded from the allocation range.
> >>>>
> >>>> Remove is_free_domid() helper as it is not needed now.
> >>>>
> >>>> No functional change intended.
> >>>>
> >>>> Signed-off-by: Denis Mukhin 
> >>>> Reviewed-by: Julien Grall 
> >>>> Reviewed-by: Alejandro Vallejo 
> >>>> ---
> >>>> Changes since v15:
> >>>> - fixup for check after the first pass in the bitarray in domid_allo=
c()
> >>>> - trivial renaming for the local variable in domid_alloc()
> >>>> - kept Julien's R-b, added Alejandro's R-b
> >>>
> >>> Just to mention: My take is that this kind of a fix ought to invalida=
te all
> >>> earlier R-b. It's not just a cosmetic change, after all.
> >>
> >> Sorry for the hiccup here, did not mean to overrule the review process=
.
> >>
> >> My bold assumption was that in case of small fixups like this it is
> >> satisfactory to carry over previous acks.
> >
> > Acks may be okay to keep, but imo R-b need dropping when an actual bug =
was
> > fixed.
>=20
> I don't know. Unless the bugfix involves a change in the code with wide r=
eaching
> consequences I'd say it's reasonable to keep them. But that's something f=
or you
> (the committers) to decide, and this just my .02 cents.
>=20
> > Irrespective of how severe the bug was.
>=20
> It's not so much about the severity (imo), as the behavioural differences
> involved in the fixup. In this case (afaics?) it's a straight s/=3D=3D/>=
=3D/, which is
> self-contained and has no wide-reaching side effects at all.
>=20
> >
> >> I asked (matrix) both Julien and Alejandro to re-review and confirm.
> >
> > While good to ask, that's of limited use. It'll be impossible later on =
to
> > figure whether such a confirmation was given. Decisions (and acks and a=
like
> > effectively fall into that category) need to be on the list, to be able=
 to
> > locate them later on.
> >
> > Jan
>=20
> He meant he reached out to ask for an in-list confirmation. As far as I'm
> concerned, my R-by still holds.

Thanks

>=20
> Cheers,
> Alejandro



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Date: Tue, 26 Aug 2025 09:53:48 +0000
To: Jan Beulich 
From: dmkhn@proton.me
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech, julien@xen.org, michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com, Julien Grall , Alejandro Vallejo , xen-devel@lists.xenproject.org
Subject: Re: [PATCH v16 1/4] xen/domain: unify domain ID allocation
Message-ID: 
In-Reply-To: 
References: <20250812223024.2364749-1-dmukhin@ford.com> <20250812223024.2364749-2-dmukhin@ford.com>   
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On Thu, Aug 21, 2025 at 09:16:16AM +0200, Jan Beulich wrote:
> On 20.08.2025 01:58, dmkhn@proton.me wrote:
> > On Thu, Aug 14, 2025 at 09:11:11AM +0200, Jan Beulich wrote:
> >> On 13.08.2025 00:30, dmkhn@proton.me wrote:
> >>> From: Denis Mukhin 
> >>>
> >>> Currently, there are two different domain ID allocation implementatio=
ns:
> >>>
> >>>   1) Sequential IDs allocation in dom0less Arm code based on max_init=
_domid;
> >>>
> >>>   2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not u=
se
> >>>      max_init_domid (both Arm and x86).
> >>>
> >>> The domain ID allocation covers dom0 or late hwdom, predefined domain=
s,
> >>> post-boot domains, excluding Xen system domains (domid >=3D
> >>> DOMID_FIRST_RESERVED).
> >>>
> >>> It makes sense to have a common helper code for such task across arch=
itectures
> >>> (Arm and x86) and between dom0less / toolstack domU allocation.
> >>>
> >>> Note, fixing dependency on max_init_domid is out of scope of this pat=
ch.
> >>>
> >>> Wrap the domain ID allocation as an arch-independent function domid_a=
lloc() in
> >>> new common/domid.c based on the bitmap.
> >>>
> >>> Allocation algorithm:
> >>> - If an explicit domain ID is provided, verify its availability and u=
se it if
> >>>   ID is not used;
> >>> - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESE=
RVED-1],
> >>>   starting from the last used ID.
> >>>   Implementation guarantees that two consecutive calls will never ret=
urn the
> >>>   same ID. ID#0 is reserved for the first boot domain (currently, dom=
0) and
> >>>   excluded from the allocation range.
> >>>
> >>> Remove is_free_domid() helper as it is not needed now.
> >>>
> >>> No functional change intended.
> >>>
> >>> Signed-off-by: Denis Mukhin 
> >>> Reviewed-by: Julien Grall 
> >>> Reviewed-by: Alejandro Vallejo 
> >>> ---
> >>> Changes since v15:
> >>> - fixup for check after the first pass in the bitarray in domid_alloc=
()
> >>> - trivial renaming for the local variable in domid_alloc()
> >>> - kept Julien's R-b, added Alejandro's R-b
> >>
> >> Just to mention: My take is that this kind of a fix ought to invalidat=
e all
> >> earlier R-b. It's not just a cosmetic change, after all.
> >
> > Sorry for the hiccup here, did not mean to overrule the review process.
> >
> > My bold assumption was that in case of small fixups like this it is
> > satisfactory to carry over previous acks.
>=20
> Acks may be okay to keep, but imo R-b need dropping when an actual bug wa=
s
> fixed. Irrespective of how severe the bug was.
>=20
> > I asked (matrix) both Julien and Alejandro to re-review and confirm.
>=20
> While good to ask, that's of limited use. It'll be impossible later on to
> figure whether such a confirmation was given. Decisions (and acks and ali=
ke
> effectively fall into that category) need to be on the list, to be able t=
o
> locate them later on.

Got it, thanks.

>=20
> Jan
>=20



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Subject: Re: [PATCH 5/6] x86/paravirt: Switch MSR access pv_ops functions to
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To: Xin Li , linux-kernel@vger.kernel.org, x86@kernel.org,
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Cc: Ajay Kaher ,
 Broadcom internal kernel review list
 , Thomas Gleixner
 , Ingo Molnar ,
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 xen-devel@lists.xenproject.org, Andrew Cooper 
References: <20250506092015.1849-1-jgross@suse.com>
 <20250506092015.1849-6-jgross@suse.com>
 <722f5b30-20e9-4540-98e4-d211d7c44cbe@zytor.com>
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To: Xin Li , linux-kernel@vger.kernel.org, x86@kernel.org,
 virtualization@lists.linux.dev
Cc: Ajay Kaher ,
 Broadcom internal kernel review list
 , Thomas Gleixner
 , Ingo Molnar ,
 Borislav Petkov , Dave Hansen ,
 "H. Peter Anvin" ,
 Boris Ostrovsky ,
 xen-devel@lists.xenproject.org, Andrew Cooper 
Message-ID: <6eb60b62-bd3a-4a64-9665-fc911cc7d869@suse.com>
Subject: Re: [PATCH 5/6] x86/paravirt: Switch MSR access pv_ops functions to
 instruction interfaces
References: <20250506092015.1849-1-jgross@suse.com>
 <20250506092015.1849-6-jgross@suse.com>
 <722f5b30-20e9-4540-98e4-d211d7c44cbe@zytor.com>
 <9f4e33d5-9cb3-4079-b764-87a15265fd52@suse.com>
 <2365af70-d36f-4663-b819-59d886936ef5@zytor.com>
 <8a82946a-6c3e-41d1-b3bd-be164dc6eeba@suse.com>
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In-Reply-To: <7047440a-0419-4982-961b-46f9b90a86e9@zytor.com>

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Date: Tue, 26 Aug 2025 11:48:15 +0100
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Subject: Re: [PATCH] xen/arm: smmuv3: Add cache maintenance for non-coherent
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To: Dmytro Firsov ,
 "Orzel, Michal" ,
 "xen-devel@lists.xenproject.org" 
Cc: Bertrand Marquis ,
 Rahul Singh ,
 Stefano Stabellini ,
 Volodymyr Babchuk 
References: <24567cc1630b1577c33939ff71d67fb2ebe5572f.1754491424.git.dmytro_firsov@epam.com>
 
 <5d48d927-7e1e-4b11-b429-0b94259154ab@epam.com>
From: Julien Grall 
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Hi,

On 26/08/2025 10:47, Dmytro Firsov wrote:
> On 22.08.25 11:12, Orzel, Michal wrote:
> On 06/08/2025 16:58, Dmytro Firsov wrote:
> 
> 
> According to the Arm SMMUv3 spec (ARM IHI 0070), a system may have
> SMMU(s) that is/are non-coherent to the PE (processing element). In such
> cases, memory accesses from the PE should be either non-cached or be
> augmented with manual cache maintenance. SMMU cache coherency is reported
> by bit 4 (COHACC) of the SMMU_IDR0 register and is already present in the
> Xen driver. However, the current implementation is not aware of cache
> maintenance for memory that is shared between the PE and non-coherent
> SMMUs. It contains dmam_alloc_coherent() function, that is added during
> Linux driver porting. But it is actually a wrapper for _xzalloc(), that
> returns normal writeback memory (which is OK for coherent SMMUs).
> 
> During Xen bring-up on a system with non-coherent SMMUs, the driver did
> not work properly - the SMMU was not functional and halted initialization
> at the very beginning due to a timeout while waiting for CMD_SYNC
> completion:
> 
>    (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
>    (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
> 
> To properly handle such scenarios, add the non_coherent flag to the
> arm_smmu_queue struct. It is initialized using features reported by the
> SMMU HW and will be used for triggering cache clean/invalidate operations.
> This flag is not queue-specific (it is applicable to the whole SMMU), but
> adding it to arm_smmu_queue allows us to not change function signatures
> and simplify the patch (smmu->features, which contains the required flag,
> are not available in code parts that require cache maintenance).
> 
> 
> There are already a few places advertising the SMMU coherency:
> 1) smmu->features
> 2) d->iommu->features
> 3) platform_features
> 
> All of them are better places than queue struct (that as you pointed out is not
> specific to coherency). I'd suggest maybe to use 3) and removing ro_after_init
> if you don't have access to 1) and 2). All in all, providing yet another place
> for coherency flag seems a bit too much.
 > >
> First of all, thank you very much for review! I will consider using
> "platform_features" in next patch version, it looks more appropriate and
> should be available within the whole driver. Also, I believe "ro_after_init"
> is also OK, since I have no need to change it (only check if cache
> maintenance should be performed).

I have to disagree with using "platform_features". Flushing the queue is 
a per-SMMU decision. But looking at the code, I think passing the SMMU 
to the caller would look wrong (what if you mistakenly pass the wrong 
SMMU?). So I think a boolean per queue is the right appraoch.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH] xen/arm: smmuv3: Add cache maintenance for non-coherent
 SMMU queues
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To: Dmytro Firsov ,
 "xen-devel@lists.xenproject.org" 
Cc: Bertrand Marquis ,
 Rahul Singh ,
 Stefano Stabellini ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: <24567cc1630b1577c33939ff71d67fb2ebe5572f.1754491424.git.dmytro_firsov@epam.com>
From: Julien Grall 
In-Reply-To: <24567cc1630b1577c33939ff71d67fb2ebe5572f.1754491424.git.dmytro_firsov@epam.com>
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Hi,

On 06/08/2025 15:58, Dmytro Firsov wrote:
> According to the Arm SMMUv3 spec (ARM IHI 0070), a system may have
> SMMU(s) that is/are non-coherent to the PE (processing element). In such
> cases, memory accesses from the PE should be either non-cached or be
> augmented with manual cache maintenance. SMMU cache coherency is reported
> by bit 4 (COHACC) of the SMMU_IDR0 register and is already present in the
> Xen driver. However, the current implementation is not aware of cache
> maintenance for memory that is shared between the PE and non-coherent
> SMMUs. It contains dmam_alloc_coherent() function, that is added during
> Linux driver porting. But it is actually a wrapper for _xzalloc(), that
> returns normal writeback memory (which is OK for coherent SMMUs).
> 
> During Xen bring-up on a system with non-coherent SMMUs, the driver did
> not work properly - the SMMU was not functional and halted initialization
> at the very beginning due to a timeout while waiting for CMD_SYNC
> completion:
> 
>    (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
>    (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
> 
> To properly handle such scenarios, add the non_coherent flag to the
> arm_smmu_queue struct. It is initialized using features reported by the
> SMMU HW and will be used for triggering cache clean/invalidate operations.
> This flag is not queue-specific (it is applicable to the whole SMMU), but
> adding it to arm_smmu_queue allows us to not change function signatures
> and simplify the patch (smmu->features, which contains the required flag,
> are not available in code parts that require cache maintenance).
> 
> Signed-off-by: Dmytro Firsov 


With one remark below:

Reviewed-by: Julien Grall 


> diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h
> index f09048812c..db936b9bd4 100644
> --- a/xen/drivers/passthrough/arm/smmu-v3.h
> +++ b/xen/drivers/passthrough/arm/smmu-v3.h
> @@ -522,6 +522,13 @@ struct arm_smmu_queue {
>   
>   	u32 __iomem			*prod_reg;
>   	u32 __iomem			*cons_reg;
> +
> +	/*
> +	 * According to SMMU spec section 3.16, some systems may have
> +	 * SMMUs, that are non-coherent to PE (processing elements).
> +	 * In such case manual cache management is needed.
> +	 */

Please mention the specification version because section numbers are not 
stable. That said, I am not sure I see the value to mention the spec 
here. I think it would be sufficient to say:

"Is the memory access coherent?"


Cheers,

> +	bool				non_coherent;
>   };
>   
>   struct arm_smmu_cmdq {

-- 
Julien Grall



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Date: Tue, 26 Aug 2025 12:57:50 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Jan Beulich ,
	xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart
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References: 
 <2aafbace-3aa2-4f58-8f6c-2815cd2315ad@suse.com>
 
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From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Jan Beulich ,
	xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart

On Tue, Aug 26, 2025 at 10:28:56AM +0200, Roger Pau Monn=C3=A9 wrote:
> On Tue, Aug 26, 2025 at 08:16:56AM +0200, Jan Beulich wrote:
> > On 26.08.2025 03:49, Marek Marczykowski-G=C3=B3recki wrote:
> > > Hi,
> > >=20
> > > I'm hitting an MSI-X issue after rebooting the domU. The symptoms are
> > > rather boring: on initial domU start the device (realtek eth card) wo=
rks
> > > fine, but after domU restart, the link doesn't come up (there is no
> > > "Link is Up" message anymore). No errors from domU driver or Xen. I
> > > tracked it down to MSI-X - if I force INTx (via pci=3Dnomsi on domU
> > > cmdline) it works fine. Convincing the driver to poll instead of wait=
ing
> > > for an interrupt also workarounds the issue.
> > >=20
> > > I noticed also some interrupts are not cleaned up on restart. The list
> > > of MSIs in 'Q' debug key output grows:
> > >=20
> > >     (XEN) 0000:03:00.0 - d22 - node -1  - MSIs < 41 42 43 44 45 46 47=
 >
> > >     restart sys-net domU
> > >     (XEN) 0000:03:00.0 - d24 - node -1  - MSIs < 41 42 43 44 45 46 47=
 48 >
> > >     restart sys-net domU
> > >     (XEN) 0000:03:00.0 - d26 - node -1  - MSIs < 41 42 43 44 45 46 47=
 48 49 >
> > >=20
> > > and 'M' output is:
> > >=20
> > >     (XEN)  MSI-X   41 vec=3Db1 lowest  edge   assert  log lowest dest=
=3D00000001 mask=3D1/H /1
> > >     (XEN)  MSI-X   42 vec=3Db9 lowest  edge   assert  log lowest dest=
=3D00000004 mask=3D1/HG/1
> > >     (XEN)  MSI-X   43 vec=3Dc1 lowest  edge   assert  log lowest dest=
=3D00000010 mask=3D1/HG/1
> > >     (XEN)  MSI-X   44 vec=3Dd9 lowest  edge   assert  log lowest dest=
=3D00000001 mask=3D1/HG/1
> > >     (XEN)  MSI-X   45 vec=3De1 lowest  edge   assert  log lowest dest=
=3D00000001 mask=3D1/HG/1
> > >     (XEN)  MSI-X   46 vec=3De9 lowest  edge   assert  log lowest dest=
=3D00000040 mask=3D1/HG/1
> > >     (XEN)  MSI-X   47 vec=3D32 lowest  edge   assert  log lowest dest=
=3D00000004 mask=3D1/HG/1
> > >     (XEN)  MSI-X   48 vec=3D3a lowest  edge   assert  log lowest dest=
=3D00000040 mask=3D1/HG/1
> > >     (XEN)  MSI-X   49 vec=3D42 lowest  edge   assert  log lowest dest=
=3D00000010 mask=3D1/ G/1
> > >=20
> > > And also, after starting and stopping the domU, `xl pci-assignable-re=
move 03:00.0`
> > > makes pciback to complain:
> > >=20
> > >     [ 1180.919874] pciback 0000:03:00.0: xen_pciback: MSI-X release f=
ailed (-16)
> > >=20
> > > This is all running on Xen 4.19.3, but I don't see much changes in th=
is
> > > area since then.
> > >=20
> > > Some more info collected at https://github.com/QubesOS/qubes-issues/i=
ssues/9335
> > >=20
> > > My question is: what should be responsible for this cleanup on domain
> > > destroy? Xen, or maybe device model (which is QEMU in stubdomain here=
)?
> >=20
> > The expectation is that qemu invokes the necessary cleanup, but of cour=
se ...
> >=20
> > > I see some cleanup (apparently not enough) happening via QEMU when the
> > > domU driver is unloaded, but logically correct cleanup shouldn't depe=
nd
> > > on correct domU operation...
> >=20
> > ... Xen may not make itself dependent upon either DomU or QEMU.
>=20
> AFAICT free_domain_pirqs() called by arch_domain_destroy() should take
> care of unbinding and freeing pirqs (but obviously not in this case).
> Can you repeat the test with a debug=3Dy hypervisor and post the
> resulting serial or dmesg here?  Some of the errors on those paths are
> printed with dprintk() and won't be visible unless using a Xen debug
> build.

Sure, will do.

> > What I find puzzling (assuming I can take the quoted output plus your a=
nnotations
> > verbatim) is that the device apparently uses multiple vectors,=20

No, that was not the first domU restart before I started collecting this
output. At fresh boot there is just one vector.

> > and we're leaking
> > exactly one of them. Also, since reboot is generally nothing else than =
shutdown
> > and immediate relaunch, is there a leak also after shutdown? I ask beca=
use it
> > might help to know which of the multiple vectors is leaked (first, last=
, random).
>=20
> Can we maybe get the output of `lspci -vv` when the device is
> attached?

Both below on first domU start, when the device still works, but when it
breaks it's identical.

Collected in dom0:
03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8=
211/8411 PCI Express Gigabit Ethernet Controller (rev 06)
	Subsystem: Gigabyte Technology Co., Ltd Onboard Ethernet
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Steppi=
ng- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=3Dfast >TAbort- SERR- TAbort- SERR- 
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Subject: Re: [PATCH] xen/arm: smmuv3: Add cache maintenance for non-coherent
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To: Julien Grall , Dmytro Firsov ,
	"xen-devel@lists.xenproject.org" 
CC: Bertrand Marquis , Rahul Singh
	, Stefano Stabellini , Volodymyr
 Babchuk 
References: <24567cc1630b1577c33939ff71d67fb2ebe5572f.1754491424.git.dmytro_firsov@epam.com>
 
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On 26/08/2025 12:48, Julien Grall wrote:
> Hi,
> 
> On 26/08/2025 10:47, Dmytro Firsov wrote:
>> On 22.08.25 11:12, Orzel, Michal wrote:
>> On 06/08/2025 16:58, Dmytro Firsov wrote:
>>
>>
>> According to the Arm SMMUv3 spec (ARM IHI 0070), a system may have
>> SMMU(s) that is/are non-coherent to the PE (processing element). In such
>> cases, memory accesses from the PE should be either non-cached or be
>> augmented with manual cache maintenance. SMMU cache coherency is reported
>> by bit 4 (COHACC) of the SMMU_IDR0 register and is already present in the
>> Xen driver. However, the current implementation is not aware of cache
>> maintenance for memory that is shared between the PE and non-coherent
>> SMMUs. It contains dmam_alloc_coherent() function, that is added during
>> Linux driver porting. But it is actually a wrapper for _xzalloc(), that
>> returns normal writeback memory (which is OK for coherent SMMUs).
>>
>> During Xen bring-up on a system with non-coherent SMMUs, the driver did
>> not work properly - the SMMU was not functional and halted initialization
>> at the very beginning due to a timeout while waiting for CMD_SYNC
>> completion:
>>
>>    (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
>>    (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
>>
>> To properly handle such scenarios, add the non_coherent flag to the
>> arm_smmu_queue struct. It is initialized using features reported by the
>> SMMU HW and will be used for triggering cache clean/invalidate operations.
>> This flag is not queue-specific (it is applicable to the whole SMMU), but
>> adding it to arm_smmu_queue allows us to not change function signatures
>> and simplify the patch (smmu->features, which contains the required flag,
>> are not available in code parts that require cache maintenance).
>>
>>
>> There are already a few places advertising the SMMU coherency:
>> 1) smmu->features
>> 2) d->iommu->features
>> 3) platform_features
>>
>> All of them are better places than queue struct (that as you pointed out is not
>> specific to coherency). I'd suggest maybe to use 3) and removing ro_after_init
>> if you don't have access to 1) and 2). All in all, providing yet another place
>> for coherency flag seems a bit too much.
>  > >
>> First of all, thank you very much for review! I will consider using
>> "platform_features" in next patch version, it looks more appropriate and
>> should be available within the whole driver. Also, I believe "ro_after_init"
>> is also OK, since I have no need to change it (only check if cache
>> maintenance should be performed).
> 
> I have to disagree with using "platform_features". Flushing the queue is 
> a per-SMMU decision. But looking at the code, I think passing the SMMU 
> to the caller would look wrong (what if you mistakenly pass the wrong 
> SMMU?). So I think a boolean per queue is the right appraoch.
For my own understanding: don't we consider SMMU coherency globally, not per
SMMU (hence why I suggested re-using the global flag)? We set the coherency
feature in the flags if all SMMUs support it. Do we want to diverge now and do
the flushing per SMMU?

~Michal



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From: Dmytro Prokopchuk1 
To: Nicola Vetrini , Jan Beulich
	
CC: Doug Goldstein , Stefano Stabellini
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Subject: Re: [PATCH v2] misra: add deviation of Rule 17.7
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MIME-Version: 1.0
Date: Tue, 26 Aug 2025 15:18:48 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: Jan Beulich , Doug Goldstein ,
 Stefano Stabellini , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 xen-devel@lists.xenproject.org
Subject: Re: [PATCH v2] misra: add deviation of Rule 17.7
In-Reply-To: 
References: <812b78119cee801662a31d39b556cb453aa69508.1756192362.git.dmytro_prokopchuk1@epam.com>
 <204a1526-7e3f-4b91-b1ee-95f3d89ff756@suse.com>
 <112a4ab83bf2abce09d4ff1b67671847@bugseng.com>
 
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On 2025-08-26 15:14, Dmytro Prokopchuk1 wrote:
> On 8/26/25 10:56, Nicola Vetrini wrote:
>> On 2025-08-26 09:45, Jan Beulich wrote:
>>> On 26.08.2025 09:36, Dmytro Prokopchuk1 wrote:
>>>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>>>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>>>> @@ -575,6 +575,11 @@ safe."
>>>>  -config=MC3A2.R17.7,calls+={safe, "any()",
>>>> "decl(name(__builtin_memcpy||__builtin_memmove||__builtin_memset||
>>>> cpumask_check))"}
>>>>  -doc_end
>>>> 
>>>> +-doc_begin="It is safe to deviate functions like 'memcpy()',
>>>> 'memset()', 'memmove()', as they return a value purely for 
>>>> convenience,
>>>> +their primary functionality (memory manipulation) remains
>>>> unaffected, and their return values are generally non-critical and
>>>> seldom relied upon."
>>>> +-config=MC3A2.R17.7,calls+={safe, "any()", "decl(name(memcpy||
>>>> memset||memmove))"}
>>>> +-doc_end
>>>> +
>>>>  #
>>>>  # Series 18.
>>>>  #
>>>> --- a/docs/misra/deviations.rst
>>>> +++ b/docs/misra/deviations.rst
>>>> @@ -576,6 +576,13 @@ Deviations related to MISRA C:2012 Rules:
>>>>           - __builtin_memset()
>>>>           - cpumask_check()
>>>> 
>>>> +   * - R17.7
>>>> +     - It is safe to deviate functions like 'memcpy()', 'memset()',
>>>> 'memmove()',
>>>> +       as they return a value purely for convenience, their primary
>>>> functionality
>>>> +       (memory manipulation) remains unaffected, and their return
>>>> values are
>>>> +       generally non-critical and seldom relied upon.
>>>> +     - Tagged as `safe` for ECLAIR.
>>> 
>>> I realize I may be overly nitpicky here, but in files named
>>> deviations.* I find it
>>> odd to read "It is safe to deviate ...". I further find the use of
>>> "like" odd when
>>> you enumerate the complete set anyway.
> 
> Updated wording (probably for the v3, if it's fine):
> 
> The functions 'memcpy()', 'memset()', and 'memmove()' return values
> primarily for convenience.
> The core functionality of these functions (memory manipulation) remains
> unaffected, and their return values
> are generally non-critical and seldom relied upon. Therefore, 
> deviations
> from this rule regarding their use
> can be considered safe.
> 

The last sentence reads a little strangely. I would write: "Therefore, 
violations of this rule due to these functions are deemed safe."

> Dmytro.
> 
>>> 
>>> I wonder whether the deviation wants generalizing anyway:
>>> Informational return
>>> values are generally okay to ignore. That is, the Eclair 
>>> configuration
>>> would be
>>> limited to the three functions for now, but the text / comment could
>>> already be
>>> broader. Then, for example, open-coded uses of the corresponding
>>> builtin functions
>>> would also be covered right away.
>>> 
>> 
>> While I understand the pragmatic reasoning, from a MISRA compliance
>> standpoint it would be better not to make the written justification 
>> and
>> the actual deviation diverge, and then wide both the ECLAIR
>> configuration and its justification suitably once new cases want to be
>> deviated. Other than that,
>> 
>> Reviewed-by: Nicola Vetrini 
>> 

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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From: Mykola Kvach 
Date: Tue, 26 Aug 2025 16:41:41 +0300
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Subject: Re: [PATCH v5 02/12] xen/arm: gic-v2: Implement GIC suspend/resume functions
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , 
	Mirela Simonovic , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Saeed Nowshadi , 
	Mykyta Poturai , Mykola Kvach 
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Hi Volodymyr,

On Sat, Aug 23, 2025 at 3:01=E2=80=AFAM Volodymyr Babchuk
 wrote:
>
> Hi Mykola,
>
> Mykola Kvach  writes:
>
> > From: Mirela Simonovic 
> >
> > System suspend may lead to a state where GIC would be powered down.
> > Therefore, Xen should save/restore the context of GIC on suspend/resume=
.
> >
> > Note that the context consists of states of registers which are
> > controlled by the hypervisor. Other GIC registers which are accessible
> > by guests are saved/restored on context switch.
> >
> > Tested on Xilinx Ultrascale+ MPSoC with (and without) powering down
> > the GIC.
>
> I think you can drop this sentence, as I am pretty sure this patch
> wasn't tested on Ultrascale+ for last five(?) years..

Ok, I=E2=80=99ll drop that sentence.

>
> >
> > Signed-off-by: Mirela Simonovic 
> > Signed-off-by: Saeed Nowshadi 
> > Signed-off-by: Mykyta Poturai 
> > Signed-off-by: Mykola Kvach 
> > ---
> > Changes in v4:
> >   - Add error logging for allocation failures
> >
> > Changes in v3:
> >   - Drop asserts and return error codes instead.
> >   - Wrap code with CONFIG_SYSTEM_SUSPEND.
> >
> > Changes in v2:
> >   - Minor fixes after review.
> > ---
> >  xen/arch/arm/gic-v2.c          | 154 +++++++++++++++++++++++++++++++++
> >  xen/arch/arm/gic.c             |  29 +++++++
> >  xen/arch/arm/include/asm/gic.h |  12 +++
> >  3 files changed, 195 insertions(+)
> >
> > diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
> > index b23e72a3d0..dce8f5e924 100644
> > --- a/xen/arch/arm/gic-v2.c
> > +++ b/xen/arch/arm/gic-v2.c
> > @@ -1098,6 +1098,151 @@ static int gicv2_iomem_deny_access(struct domai=
n *d)
> >      return iomem_deny_access(d, mfn, mfn + nr);
> >  }
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +
> > +/* GICv2 registers to be saved/restored on system suspend/resume */
> > +struct gicv2_context {
> > +    /* GICC context */
> > +    uint32_t gicc_ctlr;
> > +    uint32_t gicc_pmr;
> > +    uint32_t gicc_bpr;
> > +    /* GICD context */
> > +    uint32_t gicd_ctlr;
> > +    uint32_t *gicd_isenabler;
> > +    uint32_t *gicd_isactiver;
> > +    uint32_t *gicd_ipriorityr;
> > +    uint32_t *gicd_itargetsr;
> > +    uint32_t *gicd_icfgr;
> > +};
> > +
> > +static struct gicv2_context gicv2_context;
> > +
> > +static int gicv2_suspend(void)
> > +{
> > +    unsigned int i;
> > +
> > +    if ( !gicv2_context.gicd_isenabler )
> > +    {
> > +        dprintk(XENLOG_WARNING, "%s:%d: GICv2 suspend context not allo=
cated!\n",
> > +            __func__, __LINE__);
>
> Should this be ASSERT(gicv2_context.gicd_isenabler) ? Or do we expect
> that this can happen during normal runtime?
>
> Also, you don't need to print __func__ and __LINE__ as dprintk does this
> for you already:
>
> #define dprintk(lvl, fmt, args...) \
>     printk(lvl "%s:%d: " fmt, __FILE__, __LINE__, ## args)
>
>
>
> > +        return -ENOMEM;
> > +    }
> > +
> > +    /* Save GICC configuration */
> > +    gicv2_context.gicc_ctlr =3D readl_gicc(GICC_CTLR);
> > +    gicv2_context.gicc_pmr =3D readl_gicc(GICC_PMR);
> > +    gicv2_context.gicc_bpr =3D readl_gicc(GICC_BPR);
> > +
> > +    /* Save GICD configuration */
> > +    gicv2_context.gicd_ctlr =3D readl_gicd(GICD_CTLR);
> > +
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ )
> > +        gicv2_context.gicd_isenabler[i] =3D readl_gicd(GICD_ISENABLER =
+ i * 4);
> > +
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ )
> > +        gicv2_context.gicd_isactiver[i] =3D readl_gicd(GICD_ISACTIVER =
+ i * 4);
> > +
>
> I think you can merge this two loops

Ok, I'll do it

>
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
> > +        gicv2_context.gicd_ipriorityr[i] =3D readl_gicd(GICD_IPRIORITY=
R + i * 4);
> > +
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
> > +        gicv2_context.gicd_itargetsr[i] =3D readl_gicd(GICD_ITARGETSR =
+ i * 4);
> > +
>
> And this two as well

Ok

>
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 16); i++ )
> > +        gicv2_context.gicd_icfgr[i] =3D readl_gicd(GICD_ICFGR + i * 4)=
;
> > +
> > +    return 0;
> > +}
> > +
> > +static void gicv2_resume(void)
> > +{
> > +    unsigned int i;
> > +
> > +    if ( !gicv2_context.gicd_isenabler )
> > +    {
> > +        dprintk(XENLOG_WARNING, "%s:%d: GICv2 suspend context not allo=
cated!\n",
> > +            __func__, __LINE__);
>
> the same comment as for gicv2_suspend(). Actually, we should not reach
> here in any case.

You mean we should just drop the check, right?

>
> > +        return;
> > +    }
> > +
> > +    gicv2_cpu_disable();
> > +    /* Disable distributor */
> > +    writel_gicd(0, GICD_CTLR);
> > +
> > +    /* Restore GICD configuration */
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ ) {
> > +        writel_gicd(0xffffffff, GICD_ICENABLER + i * 4);
> > +        writel_gicd(gicv2_context.gicd_isenabler[i], GICD_ISENABLER + =
i * 4);
> > +    }
> > +
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 32); i++ ) {
> > +        writel_gicd(0xffffffff, GICD_ICACTIVER + i * 4);
> > +        writel_gicd(gicv2_context.gicd_isactiver[i], GICD_ISACTIVER + =
i * 4);
> > +    }
> > +
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
> > +        writel_gicd(gicv2_context.gicd_ipriorityr[i], GICD_IPRIORITYR =
+ i * 4);
> > +
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 4); i++ )
> > +        writel_gicd(gicv2_context.gicd_itargetsr[i], GICD_ITARGETSR + =
i * 4);
> > +
> > +    for ( i =3D 0; i < DIV_ROUND_UP(gicv2_info.nr_lines, 16); i++ )
> > +        writel_gicd(gicv2_context.gicd_icfgr[i], GICD_ICFGR + i * 4);
> > +
> > +    /* Make sure all registers are restored and enable distributor */
> > +    writel_gicd(gicv2_context.gicd_ctlr | GICD_CTL_ENABLE, GICD_CTLR);
> > +
> > +    /* Restore GIC CPU interface configuration */
> > +    writel_gicc(gicv2_context.gicc_pmr, GICC_PMR);
> > +    writel_gicc(gicv2_context.gicc_bpr, GICC_BPR);
> > +
> > +    /* Enable GIC CPU interface */
> > +    writel_gicc(gicv2_context.gicc_ctlr | GICC_CTL_ENABLE | GICC_CTL_E=
OI,
> > +                GICC_CTLR);
> > +}
> > +
> > +static void gicv2_alloc_context(struct gicv2_context *gc)
> > +{
> > +    uint32_t n =3D gicv2_info.nr_lines;
> > +
> > +    gc->gicd_isenabler =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 32)=
);
> > +    if ( !gc->gicd_isenabler )
> > +        goto err_free;
> > +
> > +    gc->gicd_isactiver =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 32)=
);
> > +    if ( !gc->gicd_isactiver )
> > +        goto err_free;
> > +
> > +    gc->gicd_itargetsr =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 4))=
;
> > +    if ( !gc->gicd_itargetsr )
> > +        goto err_free;
> > +
> > +    gc->gicd_ipriorityr =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 4)=
);
> > +    if ( !gc->gicd_ipriorityr )
> > +        goto err_free;
> > +
> > +    gc->gicd_icfgr =3D xzalloc_array(uint32_t, DIV_ROUND_UP(n, 16));
> > +    if ( !gc->gicd_icfgr )
> > +        goto err_free;
> > +
> > +    return;
> > +
> > + err_free:
> > +    dprintk(XENLOG_ERR,
> > +            "%s:%d: failed to allocate memory for GICv2 suspend contex=
t\n",
> > +            __func__, __LINE__);
>
> Okay, this partially answers to my previous question about memory
> allocation. So it is possible to have active system without space for
> GIC context... But this basically renders system un-suspendable. I think
> this warrants non-debug print to warn user that suspend will be not
> available.

Ok, I=E2=80=99ll add a regular print instead. So your comments about assert=
s are
irrelevant in this case, right?

>
> [...]
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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From: Mykola Kvach 
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Message-ID: 
Subject: Re: [PATCH v5 03/12] xen/arm: gic-v3: Implement GICv3 suspend/resume functions
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , Mykola Kvach , 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel 
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Hi Volodymyr,

On Sat, Aug 23, 2025 at 3:20=E2=80=AFAM Volodymyr Babchuk
 wrote:
>
>
> Hi,
>
> Mykola Kvach  writes:
>
> > From: Mykola Kvach 
> >
> > System suspend may lead to a state where GIC would be powered down.
> > Therefore, Xen should save/restore the context of GIC on suspend/resume=
.
> >
> > Note that the context consists of states of registers which are
> > controlled by the hypervisor. Other GIC registers which are accessible
> > by guests are saved/restored on context switch.
> >
> > Signed-off-by: Mykola Kvach 
> > ---
> >  xen/arch/arm/gic-v3.c | 233 ++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 233 insertions(+)
> >
> > diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> > index cd3e1acf79..a9b65ff5d4 100644
> > --- a/xen/arch/arm/gic-v3.c
> > +++ b/xen/arch/arm/gic-v3.c
> > @@ -1776,6 +1776,231 @@ static bool gic_dist_supports_lpis(void)
> >      return (readl_relaxed(GICD + GICD_TYPER) & GICD_TYPE_LPIS);
> >  }
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +
> > +/* GICv3 registers to be saved/restored on system suspend/resume */
> > +struct gicv3_ctx {
> > +    struct dist_ctx {
> > +        uint32_t ctlr;
> > +        /*
> > +         * This struct represent block of 32 IRQs
> > +         * TODO: store extended SPI configuration (GICv3.1+)
> > +         */
> > +        struct irq_regs {
> > +            uint32_t icfgr[2];
> > +            uint32_t ipriorityr[8];
> > +            uint64_t irouter[32];
> > +            uint32_t isactiver;
> > +            uint32_t isenabler;
> > +        } *irqs;
> > +    } dist;
> > +
> > +    /* have only one rdist structure for last running CPU during suspe=
nd */
> > +    struct redist_ctx {
> > +        uint32_t ctlr;
> > +        /* TODO: handle case when we have more than 16 PPIs (GICv3.1+)=
 */
> > +        uint32_t icfgr[2];
> > +        uint32_t igroupr;
> > +        uint32_t ipriorityr[8];
> > +        uint32_t isactiver;
> > +        uint32_t isenabler;
> > +    } rdist;
> > +
> > +    struct cpu_ctx {
> > +        uint32_t ctlr;
> > +        uint32_t pmr;
> > +        uint32_t bpr;
> > +        uint32_t sre_el2;
> > +        uint32_t grpen;
> > +    } cpu;
> > +};
> > +
> > +static struct gicv3_ctx gicv3_ctx;
> > +
> > +static void __init gicv3_alloc_context(void)
> > +{
> > +    uint32_t blocks =3D DIV_ROUND_UP(gicv3_info.nr_lines, 32);
> > +
> > +    if ( gicv3_its_host_has_its() )
> > +        return;
>
> I think this needs a comment at least. And/or printk() message. Because
> for it is unclear why we are doing nothing if host has ITS

Got it, I'll add log message

>
> > +
> > +    /* according to spec it is possible don't have SPIs */
> > +    if ( blocks =3D=3D 1 )
> > +        return;
> > +
> > +    gicv3_ctx.dist.irqs =3D xzalloc_array(typeof(*gicv3_ctx.dist.irqs)=
, blocks - 1);
> > +    if ( !gicv3_ctx.dist.irqs )
> > +        dprintk(XENLOG_ERR,
> > +                "%s:%d: failed to allocate memory for GICv3 suspend co=
ntext\n",
> > +                __func__, __LINE__);
>
> dprintk() already prints function and line. Here and everywhere in this
> patch.

Thanks for noticing this. I=E2=80=99ll update the code accordingly.

>
> > +}
> > +
> > +static void gicv3_disable_redist(void)
> > +{
> > +    void __iomem* waker =3D GICD_RDIST_BASE + GICR_WAKER;
> > +
> > +    writel_relaxed(readl_relaxed(waker) | GICR_WAKER_ProcessorSleep, w=
aker);
> > +    while ( (readl_relaxed(waker) & GICR_WAKER_ChildrenAsleep) =3D=3D =
0 );
> > +}
> > +
> > +static int gicv3_suspend(void)
> > +{
> > +    unsigned int i;
> > +    void __iomem *base;
> > +    typeof(gicv3_ctx.rdist)* rdist =3D &gicv3_ctx.rdist;
> > +
> > +    /* TODO: implement support for ITS */
> > +    if ( gicv3_its_host_has_its() )
> > +        return -EOPNOTSUPP;
> > +
> > +    if ( !gicv3_ctx.dist.irqs && gicv3_info.nr_lines > NR_GIC_LOCAL_IR=
QS )
> > +    {
> > +        dprintk(XENLOG_WARNING,
> > +                "%s:%d: GICv3 suspend context is not allocated!\n",
> > +                __func__, __LINE__);
> > +        return -ENOMEM;
> > +    }
> > +
> > +    gicv3_save_state(current);
> > +
> > +    /* Save GICC configuration */
> > +    gicv3_ctx.cpu.ctlr     =3D READ_SYSREG(ICC_CTLR_EL1);
> > +    gicv3_ctx.cpu.pmr      =3D READ_SYSREG(ICC_PMR_EL1);
> > +    gicv3_ctx.cpu.bpr      =3D READ_SYSREG(ICC_BPR1_EL1);
> > +    gicv3_ctx.cpu.sre_el2  =3D READ_SYSREG(ICC_SRE_EL2);
> > +    gicv3_ctx.cpu.grpen    =3D READ_SYSREG(ICC_IGRPEN1_EL1);
> > +
> > +    gicv3_disable_interface();
> > +    gicv3_disable_redist();
> > +
> > +    /* Save GICR configuration */
> > +    gicv3_redist_wait_for_rwp();
> > +
> > +    base =3D GICD_RDIST_SGI_BASE;
> > +
> > +    rdist->ctlr =3D readl_relaxed(base + GICR_CTLR);
> > +
> > +    /* Set priority on PPI and SGI interrupts */
>
> Probably you wanted to say "Save priority..."

Yes, thank you!
I forgot to change it after copy-pasting.

>
> > +    for (i =3D 0; i < NR_GIC_LOCAL_IRQS / 4; i +=3D 4)
> > +        rdist->ipriorityr[i] =3D readl_relaxed(base + GICR_IPRIORITYR0=
 + 4 * i);
>
> Is this correct? You are writing to every 4th rdist->ipriorityr and
> reading every 4th GICR_IPRIORITYR

Definitely not -- thank you for catching this!

>
> > +
> > +    rdist->isactiver =3D readl_relaxed(base + GICR_ISACTIVER0);
> > +    rdist->isenabler =3D readl_relaxed(base + GICR_ISENABLER0);
> > +    rdist->igroupr   =3D readl_relaxed(base + GICR_IGROUPR0);
> > +    rdist->icfgr[0]  =3D readl_relaxed(base + GICR_ICFGR0);
> > +    rdist->icfgr[1]  =3D readl_relaxed(base + GICR_ICFGR1);
> > +
> > +    /* Save GICD configuration */
> > +    gicv3_dist_wait_for_rwp();
> > +    gicv3_ctx.dist.ctlr =3D readl_relaxed(GICD + GICD_CTLR);
> > +
> > +    for ( i =3D 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ )
> > +    {
> > +        typeof(gicv3_ctx.dist.irqs) irqs =3D gicv3_ctx.dist.irqs + i -=
 1;
> > +        unsigned int irq;
> > +
> > +        base =3D GICD + GICD_ICFGR + 8 * i;
> > +        irqs->icfgr[0] =3D readl_relaxed(base);
> > +        irqs->icfgr[1] =3D readl_relaxed(base + 4);
> > +
> > +        base =3D GICD + GICD_IPRIORITYR + 32 * i;
> > +        for ( irq =3D 0; irq < 8; irq++ )
> > +            irqs->ipriorityr[irq] =3D readl_relaxed(base + 4 * irq);
> > +
> > +        base =3D GICD + GICD_IROUTER + 32 * i;
> > +        for ( irq =3D 0; irq < 32; irq++ )
> > +            irqs->irouter[irq] =3D readq_relaxed_non_atomic(base + 8 *=
 irq);
> > +
> > +        irqs->isactiver =3D readl_relaxed(GICD + GICD_ISACTIVER + 4 * =
i);
> > +        irqs->isenabler =3D readl_relaxed(GICD + GICD_ISENABLER + 4 * =
i);
> > +    }
> > +
> > +    return 0;
> > +}
> > +
> > +static void gicv3_resume(void)
> > +{
> > +    unsigned int i;
> > +    void __iomem *base;
> > +    typeof(gicv3_ctx.rdist)* rdist =3D &gicv3_ctx.rdist;
> > +
> > +    if ( !gicv3_ctx.dist.irqs && gicv3_info.nr_lines > NR_GIC_LOCAL_IR=
QS )
> > +    {
> > +        dprintk(XENLOG_WARNING, "%s:%d: GICv3 suspend context not allo=
cated!\n",
> > +            __func__, __LINE__);
> > +        return;
> > +    }
> > +
> > +    writel_relaxed(0, GICD + GICD_CTLR);
> > +
> > +    for ( i =3D NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i +=3D 32 =
)
> > +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) =
* 4);
> > +
> > +    for ( i =3D 1; i < DIV_ROUND_UP(gicv3_info.nr_lines, 32); i++ )
> > +    {
> > +        typeof(gicv3_ctx.dist.irqs) irqs =3D gicv3_ctx.dist.irqs + i -=
 1;
> > +        unsigned int irq;
> > +
> > +        base =3D GICD + GICD_ICFGR + 8 * i;
> > +        writel_relaxed(irqs->icfgr[0], base);
> > +        writel_relaxed(irqs->icfgr[1], base + 4);
> > +
> > +        base =3D GICD + GICD_IPRIORITYR + 32 * i;
> > +        for ( irq =3D 0; irq < 8; irq++ )
> > +            writel_relaxed(irqs->ipriorityr[irq], base + 4 * irq );
>
> style: space before )

I'll fix it, thank you

>
> > +
> > +        base =3D GICD + GICD_IROUTER + 32 * i;
> > +        for ( irq =3D 0; irq < 32; irq++ )
> > +            writeq_relaxed_non_atomic(irqs->irouter[irq], base + 8 * i=
rq);
> > +
> > +        writel_relaxed(irqs->isenabler, GICD + GICD_ISENABLER + i * 4)=
;
> > +        writel_relaxed(irqs->isactiver, GICD + GICD_ISACTIVER + i * 4)=
;
> > +    }
> > +
> > +    writel_relaxed(gicv3_ctx.dist.ctlr, GICD + GICD_CTLR);
> > +    gicv3_dist_wait_for_rwp();
> > +
> > +    /* Restore GICR (Redistributor) configuration */
> > +    gicv3_enable_redist();
> > +
> > +    base =3D GICD_RDIST_SGI_BASE;
> > +
> > +    writel_relaxed(0xffffffff, base + GICR_ICENABLER0);
> > +    gicv3_redist_wait_for_rwp();
> > +
> > +    for (i =3D 0; i < NR_GIC_LOCAL_IRQS / 4; i +=3D 4)
> > +        writel_relaxed(rdist->ipriorityr[i], base + GICR_IPRIORITYR0 +=
 i * 4);
>
> Is this correct? You are writing to every 4th GICR_IPRIORITYR

Definitely not -- thank you for catching this!

>
> > +
> > +    writel_relaxed(rdist->isactiver, base + GICR_ISACTIVER0);
> > +
> > +    writel_relaxed(rdist->igroupr,  base + GICR_IGROUPR0);
> > +    writel_relaxed(rdist->icfgr[0], base + GICR_ICFGR0);
> > +    writel_relaxed(rdist->icfgr[1], base + GICR_ICFGR1);
> > +
> > +    gicv3_redist_wait_for_rwp();
> > +
> > +    writel_relaxed(rdist->isenabler, base + GICR_ISENABLER0);
> > +    writel_relaxed(rdist->ctlr, GICD_RDIST_BASE + GICR_CTLR);
> > +
> > +    gicv3_redist_wait_for_rwp();
> > +
> > +    WRITE_SYSREG(gicv3_ctx.cpu.sre_el2, ICC_SRE_EL2);
> > +    isb();
> > +
> > +    /* Restore CPU interface (System registers) */
> > +    WRITE_SYSREG(gicv3_ctx.cpu.pmr,   ICC_PMR_EL1);
> > +    WRITE_SYSREG(gicv3_ctx.cpu.bpr,   ICC_BPR1_EL1);
> > +    WRITE_SYSREG(gicv3_ctx.cpu.ctlr,  ICC_CTLR_EL1);
> > +    WRITE_SYSREG(gicv3_ctx.cpu.grpen, ICC_IGRPEN1_EL1);
> > +    isb();
> > +
> > +    gicv3_hyp_init();
> > +
> > +    gicv3_restore_state(current);
> > +}
> > +
> > +#endif /* CONFIG_SYSTEM_SUSPEND */
> > +
> >  /* Set up the GIC */
> >  static int __init gicv3_init(void)
> >  {
> > @@ -1850,6 +2075,10 @@ static int __init gicv3_init(void)
> >
> >      gicv3_hyp_init();
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +    gicv3_alloc_context();
> > +#endif
> > +
> >  out:
> >      spin_unlock(&gicv3.lock);
> >
> > @@ -1889,6 +2118,10 @@ static const struct gic_hw_operations gicv3_ops =
=3D {
> >  #endif
> >      .iomem_deny_access   =3D gicv3_iomem_deny_access,
> >      .do_LPI              =3D gicv3_do_LPI,
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +    .suspend             =3D gicv3_suspend,
> > +    .resume              =3D gicv3_resume,
> > +#endif
> >  };
> >
> >  static int __init gicv3_dt_preinit(struct dt_device_node *node, const =
void *data)
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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From: Mykola Kvach 
Date: Tue, 26 Aug 2025 16:42:04 +0300
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Message-ID: 
Subject: Re: [PATCH v5 04/12] xen/arm: Prevent crash during
 disable_nonboot_cpus on suspend
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , Mykola Kvach , 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel 
Content-Type: text/plain; charset="UTF-8"
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Hi Volodymyr,

On Sat, Aug 23, 2025 at 3:36=E2=80=AFAM Volodymyr Babchuk
 wrote:
>
>
> Hi Mykola,
>
> Mykola Kvach  writes:
>
> While I approve the change, the commit message is somewhat
> unclear. Maybe "Don't release IRQs on suspend" will be better?

Do you mean commit message title ?

>
> > From: Mykola Kvach 
> >
> > If we call disable_nonboot_cpus on ARM64 with system_state set
> > to SYS_STATE_suspend, the following assertion will be triggered:
> >
> > ```
> > (XEN) [   25.582712] Disabling non-boot CPUs ...
> > (XEN) [   25.587032] Assertion '!in_irq() && (local_irq_is_enabled() ||=
 num_online_cpus() <=3D 1)' failed at common/xmalloc_tlsf.c:714
> > [...]
> > (XEN) [   25.975069] Xen call trace:
> > (XEN) [   25.978353]    [<00000a000022e098>] xfree+0x130/0x1a4 (PC)
> > (XEN) [   25.984314]    [<00000a000022e08c>] xfree+0x124/0x1a4 (LR)
> > (XEN) [   25.990276]    [<00000a00002747d4>] release_irq+0xe4/0xe8
> > (XEN) [   25.996152]    [<00000a0000278588>] time.c#cpu_time_callback+0=
x44/0x60
> > (XEN) [   26.003150]    [<00000a000021d678>] notifier_call_chain+0x7c/0=
xa0
> > (XEN) [   26.009717]    [<00000a00002018e0>] cpu.c#cpu_notifier_call_ch=
ain+0x24/0x48
> > (XEN) [   26.017148]    [<00000a000020192c>] cpu.c#_take_cpu_down+0x28/=
0x34
> > (XEN) [   26.023801]    [<00000a0000201944>] cpu.c#take_cpu_down+0xc/0x=
18
> > (XEN) [   26.030281]    [<00000a0000225c5c>] stop_machine.c#stopmachine=
_action+0xbc/0xe4
> > (XEN) [   26.038057]    [<00000a00002264bc>] tasklet.c#do_tasklet_work+=
0xb8/0x100
> > (XEN) [   26.045229]    [<00000a00002268a4>] do_tasklet+0x68/0xb0
> > (XEN) [   26.051018]    [<00000a000026e120>] domain.c#idle_loop+0x7c/0x=
194
> > (XEN) [   26.057585]    [<00000a0000277e30>] start_secondary+0x21c/0x22=
0
> > (XEN) [   26.063978]    [<00000a0000361258>] 00000a0000361258
> > ```
> >
> > This happens because before invoking take_cpu_down via the stop_machine=
_run
> > function on the target CPU, stop_machine_run requests
> > the STOPMACHINE_DISABLE_IRQ state on that CPU. Releasing memory in
> > the release_irq function then triggers the assertion:
> >
> > /*
> >  * Heap allocations may need TLB flushes which may require IRQs to be
> >  * enabled (except when only 1 PCPU is online).
> >  */
> >
> > This patch adds system state checks to guard calls to request_irq
> > and release_irq. These calls are now skipped when system_state is
> > SYS_STATE_{resume,suspend}, preventing unsafe operations during
> > suspend/resume handling.
>
> If any call to release_irq() during suspend will trigger ASSERT, and it
> is fine to leave IRQs as is during suspend, maybe it will be easier to
> put
>
> +        if ( system_state =3D=3D SYS_STATE_suspend )
> +            return;
>
> straight into release_irq() code? This will be easier than playing
> whack-a-mole when some other patch will add another release_irq() call
> somewhere.

I=E2=80=99m fine with adding this check directly into release_irq(), as lon=
g as
the other maintainers agree with this approach.

>
>
> >
> > Signed-off-by: Mykola Kvach 
> > ---
> > Changes in V4:
> >   - removed the prior tasklet-based workaround in favor of a more
> >     straightforward and safer solution
> >   - reworked the approach by adding explicit system state checks around
> >     request_irq and release_irq calls, skips these calls during suspend
> >     and resume states to avoid unsafe memory operations when IRQs are
> >     disabled
> > ---
> >  xen/arch/arm/gic.c           |  6 ++++++
> >  xen/arch/arm/tee/ffa_notif.c |  2 +-
> >  xen/arch/arm/time.c          | 18 ++++++++++++------
> >  3 files changed, 19 insertions(+), 7 deletions(-)
> >
> > diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> > index a018bd7715..9856cb1592 100644
> > --- a/xen/arch/arm/gic.c
> > +++ b/xen/arch/arm/gic.c
> > @@ -388,6 +388,9 @@ void gic_dump_info(struct vcpu *v)
> >
> >  void init_maintenance_interrupt(void)
> >  {
> > +    if ( system_state =3D=3D SYS_STATE_resume )
> > +        return;
> > +
> >      request_irq(gic_hw_ops->info->maintenance_irq, 0, maintenance_inte=
rrupt,
> >                  "irq-maintenance", NULL);
> >  }
> > @@ -461,6 +464,9 @@ static int cpu_gic_callback(struct notifier_block *=
nfb,
> >      switch ( action )
> >      {
> >      case CPU_DYING:
> > +        if ( system_state =3D=3D SYS_STATE_suspend )
> > +            break;
> > +
> >          /* This is reverting the work done in init_maintenance_interru=
pt */
> >          release_irq(gic_hw_ops->info->maintenance_irq, NULL);
> >          break;
> > diff --git a/xen/arch/arm/tee/ffa_notif.c b/xen/arch/arm/tee/ffa_notif.=
c
> > index 00efaf8f73..06f715a82b 100644
> > --- a/xen/arch/arm/tee/ffa_notif.c
> > +++ b/xen/arch/arm/tee/ffa_notif.c
> > @@ -347,7 +347,7 @@ void ffa_notif_init_interrupt(void)
> >  {
> >      int ret;
> >
> > -    if ( notif_enabled && notif_sri_irq < NR_GIC_SGI )
> > +    if ( notif_enabled && notif_sri_irq < NR_GIC_SGI && system_state !=
=3D SYS_STATE_resume )
> >      {
> >          /*
> >           * An error here is unlikely since the primary CPU has already
> > diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
> > index ad984fdfdd..b2e07ade43 100644
> > --- a/xen/arch/arm/time.c
> > +++ b/xen/arch/arm/time.c
> > @@ -320,10 +320,13 @@ void init_timer_interrupt(void)
> >      WRITE_SYSREG(CNTHCTL_EL2_EL1PCTEN, CNTHCTL_EL2);
> >      disable_physical_timers();
> >
> > -    request_irq(timer_irq[TIMER_HYP_PPI], 0, htimer_interrupt,
> > -                "hyptimer", NULL);
> > -    request_irq(timer_irq[TIMER_VIRT_PPI], 0, vtimer_interrupt,
> > -                   "virtimer", NULL);
> > +    if ( system_state !=3D SYS_STATE_resume )
> > +    {
> > +        request_irq(timer_irq[TIMER_HYP_PPI], 0, htimer_interrupt,
> > +                    "hyptimer", NULL);
> > +        request_irq(timer_irq[TIMER_VIRT_PPI], 0, vtimer_interrupt,
> > +                    "virtimer", NULL);
> > +    }
> >
> >      check_timer_irq_cfg(timer_irq[TIMER_HYP_PPI], "hypervisor");
> >      check_timer_irq_cfg(timer_irq[TIMER_VIRT_PPI], "virtual");
> > @@ -338,8 +341,11 @@ static void deinit_timer_interrupt(void)
> >  {
> >      disable_physical_timers();
> >
> > -    release_irq(timer_irq[TIMER_HYP_PPI], NULL);
> > -    release_irq(timer_irq[TIMER_VIRT_PPI], NULL);
> > +    if ( system_state !=3D SYS_STATE_suspend )
> > +    {
> > +        release_irq(timer_irq[TIMER_HYP_PPI], NULL);
> > +        release_irq(timer_irq[TIMER_VIRT_PPI], NULL);
> > +    }
> >  }
> >
> >  /* Wait a set number of microseconds */
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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From: Mykola Kvach 
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Message-ID: 
Subject: Re: [PATCH v5 06/12] xen/arm: irq: Restore state of local IRQs during
 system resume
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , Mykola Kvach , 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel 
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Hi Volodymyr,

On Sat, Aug 23, 2025 at 3:45=E2=80=AFAM Volodymyr Babchuk
 wrote:
>
> Hi Mykola,
>
> Mykola Kvach  writes:
>
> > From: Mykola Kvach 
> >
> > On ARM, the first 32 interrupts (SGIs and PPIs) are banked per-CPU
> > and not restored by gic_resume (for secondary cpus).
> >
> > This patch introduces restore_local_irqs_on_resume, a function that
> > restores the state of local interrupts on the target CPU during
> > system resume.
> >
> > It iterates over all local IRQs and re-enables those that were not
> > disabled, reprogramming their routing and affinity accordingly.
> >
> > The function is invoked from start_secondary, ensuring that local IRQ
> > state is restored early during CPU bring-up after suspend.
> >
> > Signed-off-by: Mykola Kvach 
> > ---
> >  xen/arch/arm/irq.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 44 insertions(+)
> >
> > diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> > index 148f184f8b..b3ff38dc27 100644
> > --- a/xen/arch/arm/irq.c
> > +++ b/xen/arch/arm/irq.c
> > @@ -113,6 +113,47 @@ static int init_local_irq_data(unsigned int cpu)
> >      return 0;
> >  }
> >
> > +/*
> > + * The first 32 interrupts (PPIs and SGIs) are per-CPU,
> > + * so call this function on the target CPU to restore them.
> > + *
> > + * SPIs are restored via gic_resume.
> > + */
> > +static void restore_local_irqs_on_resume(void)
> > +{
> > +    int irq;
> > +
> > +    if ( system_state !=3D SYS_STATE_resume )
> > +        return;
>
> Maybe it is better to move this check to restore_local_irqs_on_resume()
> caller? You can put ASSERT(system_state =3D=3D SYS_STATE_resume) there
> instead.
>
> I am saying this because name of restore_local_irqs_on_resume() implies t=
hat it
> should be called only on resume.

Not a problem.
I'll move checking outside the function.

>
> > +
> > +    spin_lock(&local_irqs_type_lock);
> > +
> > +    for ( irq =3D 0; irq < NR_LOCAL_IRQS; irq++ )
> > +    {
> > +        struct irq_desc *desc =3D irq_to_desc(irq);
> > +
> > +        spin_lock(&desc->lock);
> > +
> > +        if ( test_bit(_IRQ_DISABLED, &desc->status) )
> > +        {
> > +            spin_unlock(&desc->lock);
> > +            continue;
> > +        }
> > +
> > +        /* it is needed to avoid asserts in below calls */
> > +        set_bit(_IRQ_DISABLED, &desc->status);
>
> Assert in the call below isn't just because. You need to either call
> desc->handler->disable() to properly disable the IRQ or justify why it
> is fine to just set the bit.

Got it. I=E2=80=99ll call the disable handler here instead.

>
> > +
> > +        gic_route_irq_to_xen(desc, GIC_PRI_IRQ);
> > +
> > +        /* _IRQ_DISABLED is cleared by below call */
> > +        desc->handler->startup(desc);
> > +
> > +        spin_unlock(&desc->lock);
> > +    }
> > +
> > +    spin_unlock(&local_irqs_type_lock);
> > +}
> > +
> >  static int cpu_callback(struct notifier_block *nfb, unsigned long acti=
on,
> >                          void *hcpu)
> >  {
> > @@ -131,6 +172,9 @@ static int cpu_callback(struct notifier_block *nfb,=
 unsigned long action,
> >              printk(XENLOG_ERR "Unable to allocate local IRQ for CPU%u\=
n",
> >                     cpu);
> >          break;
> > +    case CPU_STARTING:
> > +        restore_local_irqs_on_resume();
> > +        break;
> >      }
> >
> >      return notifier_from_errno(rc);
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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From: Mykola Kvach 
Date: Tue, 26 Aug 2025 16:42:16 +0300
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Message-ID: 
Subject: Re: [PATCH v5 07/12] xen/arm: Add support for system suspend
 triggered by hardware domain
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , 
	Mirela Simonovic , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Andrew Cooper , 
	Anthony PERARD , Jan Beulich , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Saeed Nowshadi , Mykyta Poturai , 
	Mykola Kvach 
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

Hi Volodymyr,

On Sat, Aug 23, 2025 at 4:00=E2=80=AFAM Volodymyr Babchuk
 wrote:
>
> Hi Mykola,
>
> Mykola Kvach  writes:
>
> > From: Mirela Simonovic 
> >
> > Trigger Xen suspend when the hardware domain initiates suspend via
> > SHUTDOWN_suspend. Redirect system suspend to CPU#0 to ensure the
> > suspend logic runs on the boot CPU, as required.
> >
> > Introduce full suspend/resume infrastructure gated by CONFIG_SYSTEM_SUS=
PEND,
> > including logic to:
> >  - disable and enable non-boot physical CPUs
> >  - freeze and thaw domains
> >  - suspend and resume the GIC, timer and console
> >  - maintain system state before and after suspend
> >
> > Remove the restriction in the PSCI interface preventing suspend from th=
e
> > hardware domain.
> >
> > Select HAS_SYSTEM_SUSPEND for ARM_64.
> >
> > Signed-off-by: Mirela Simonovic 
> > Signed-off-by: Saeed Nowshadi 
> > Signed-off-by: Mykyta Poturai 
> > Signed-off-by: Mykola Kvach 
> > ---
> > Changes in v5:
> > - select HAS_SYSTEM_SUSPEND in ARM_64 instead of ARM
> > - check llc_coloring_enabled instead of LLC_COLORING during the selecti=
on
> >   of HAS_SYSTEM_SUSPEND config
> > - call host_system_suspend from guest PSCI system suspend instead of
> >   arch_domain_shutdown, reducing the complexity of the new code
> > - update some comments
> >
> > Changes introduced in V4:
> >   - drop code for saving and restoring VCPU context (for more informati=
on
> >     refer part 1 of patch series)
> >   - remove IOMMU suspend and resume calls until they will be implemente=
d
> >   - move system suspend logic to arch_domain_shutdown, invoked from
> >     domain_shutdown
> >   - apply minor fixes such as renaming functions, updating comments, an=
d
> >     modifying the commit message to reflect these changes
> >   - add console_end_sync to resume path after system suspend
> >
> > Changes introduced in V3:
> >   - merge changes from other commits into this patch (previously stashe=
d):
> >     1) disable/enable non-boot physical CPUs and freeze/thaw domains du=
ring
> >        suspend/resume
> >     2) suspend/resume the timer, GIC, console, IOMMU, and hardware doma=
in
> > ---
> >  xen/arch/arm/Kconfig               |   1 +
> >  xen/arch/arm/Makefile              |   1 +
> >  xen/arch/arm/include/asm/suspend.h |  22 +++++
> >  xen/arch/arm/suspend.c             | 151 +++++++++++++++++++++++++++++
> >  xen/arch/arm/vpsci.c               |  12 ++-
> >  xen/common/domain.c                |   4 +
> >  6 files changed, 190 insertions(+), 1 deletion(-)
> >  create mode 100644 xen/arch/arm/include/asm/suspend.h
> >  create mode 100644 xen/arch/arm/suspend.c
> >
> > diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> > index a0c8160474..ccdbaa5bc3 100644
> > --- a/xen/arch/arm/Kconfig
> > +++ b/xen/arch/arm/Kconfig
> > @@ -8,6 +8,7 @@ config ARM_64
> >       depends on !ARM_32
> >       select 64BIT
> >       select HAS_FAST_MULTIPLY
> > +     select HAS_SYSTEM_SUSPEND if UNSUPPORTED
> >       select HAS_VPCI_GUEST_SUPPORT if PCI_PASSTHROUGH
> >
> >  config ARM
> > diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile
> > index f833cdf207..3f6247adee 100644
> > --- a/xen/arch/arm/Makefile
> > +++ b/xen/arch/arm/Makefile
> > @@ -51,6 +51,7 @@ obj-y +=3D setup.o
> >  obj-y +=3D shutdown.o
> >  obj-y +=3D smp.o
> >  obj-y +=3D smpboot.o
> > +obj-$(CONFIG_SYSTEM_SUSPEND) +=3D suspend.o
> >  obj-$(CONFIG_SYSCTL) +=3D sysctl.o
> >  obj-y +=3D time.o
> >  obj-y +=3D traps.o
> > diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/=
asm/suspend.h
> > new file mode 100644
> > index 0000000000..78d0e2383b
> > --- /dev/null
> > +++ b/xen/arch/arm/include/asm/suspend.h
> > @@ -0,0 +1,22 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __ASM_ARM_SUSPEND_H__
> > +#define __ASM_ARM_SUSPEND_H__
> > +
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +
> > +int host_system_suspend(void);
> > +
> > +#endif /* CONFIG_SYSTEM_SUSPEND */
> > +
> > +#endif /* __ASM_ARM_SUSPEND_H__ */
> > +
> > + /*
> > +  * Local variables:
> > +  * mode: C
> > +  * c-file-style: "BSD"
> > +  * c-basic-offset: 4
> > +  * tab-width: 4
> > +  * indent-tabs-mode: nil
> > +  * End:
> > +  */
> > diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
> > new file mode 100644
> > index 0000000000..abf4b928ce
> > --- /dev/null
> > +++ b/xen/arch/arm/suspend.c
> > @@ -0,0 +1,151 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/*
> > + * TODO list:
> > + *  - Test system suspend with LLC_COLORING enabled and verify functio=
nality
> > + *  - Implement IOMMU suspend/resume handlers and integrate them
> > + *    into the suspend/resume path (IPMMU and SMMU)
> > + *  - Enable "xl suspend" support on ARM architecture
> > + *  - Properly disable Xen timer watchdog from relevant services
> > + *  - Add suspend/resume CI test for ARM (QEMU if feasible)
> > + *  - Investigate feasibility and need for implementing system suspend=
 on ARM32
> > + */
> > +
> > +/* Xen suspend. Note: data is not used (suspend is the suspend to RAM)=
 */
> > +static long system_suspend(void *data)
> > +{
> > +    int status;
> > +    unsigned long flags;
> > +
> > +    BUG_ON(system_state !=3D SYS_STATE_active);
> > +
> > +    system_state =3D SYS_STATE_suspend;
> > +    freeze_domains();
> > +    scheduler_disable();
> > +
> > +    /*
> > +     * Non-boot CPUs have to be disabled on suspend and enabled on res=
ume
> > +     * (hotplug-based mechanism). Disabling non-boot CPUs will lead to=
 PSCI
> > +     * CPU_OFF to be called by each non-boot CPU. Depending on the und=
erlying
> > +     * platform capabilities, this may lead to the physical powering d=
own of
> > +     * CPUs. Tested on Xilinx Zynq Ultrascale+ MPSoC (including power =
down of
> > +     * each non-boot CPU).
>
> I don't think that the last part of the comment is relevant in upstream.

I=E2=80=99ll drop that part, as it=E2=80=99s not relevant for upstream.

>
> > +     */
> > +    status =3D disable_nonboot_cpus();
> > +    if ( status )
> > +    {
> > +        system_state =3D SYS_STATE_resume;
> > +        goto resume_nonboot_cpus;
> > +    }
> > +
> > +    time_suspend();
> > +
> > +    local_irq_save(flags);
> > +    status =3D gic_suspend();
> > +    if ( status )
> > +    {
> > +        system_state =3D SYS_STATE_resume;
> > +        goto resume_irqs;
> > +    }
> > +
> > +    printk("Xen suspending...\n");
> > +
> > +    console_start_sync();
> > +    status =3D console_suspend();
> > +    if ( status )
> > +    {
> > +        dprintk(XENLOG_ERR, "Failed to suspend the console, err=3D%d\n=
", status);
> > +        system_state =3D SYS_STATE_resume;
> > +        goto resume_console;
> > +    }
> > +
> > +    /*
> > +     * Enable identity mapping before entering suspend to simplify
> > +     * the resume path
> > +     */
> > +    update_boot_mapping(true);
> > +
>
> This puzzles me. I expected actually PSCI suspend call here.
>
> > +    system_state =3D SYS_STATE_resume;
> > +    update_boot_mapping(false);
> > +
> > + resume_console:
> > +    console_resume();
> > +    console_end_sync();
> > +
> > +    gic_resume();
> > +
> > + resume_irqs:
> > +    local_irq_restore(flags);
> > +    time_resume();
> > +
> > + resume_nonboot_cpus:
> > +    /*
> > +     * The rcu_barrier() has to be added to ensure that the per cpu ar=
ea is
> > +     * freed before a non-boot CPU tries to initialize it (_free_percp=
u_area()
> > +     * has to be called before the init_percpu_area()). This scenario =
occurs
> > +     * when non-boot CPUs are hot-unplugged on suspend and hotplugged =
on resume.
> > +     */
> > +    rcu_barrier();
> > +    enable_nonboot_cpus();
> > +    scheduler_enable();
> > +    thaw_domains();
> > +
> > +    system_state =3D SYS_STATE_active;
> > +
> > +    /* The resume of hardware domain should always follow Xen's resume=
. */
> > +    domain_resume(hardware_domain);
> > +
> > +    printk("Resume (status %d)\n", status);
> > +    return status;
> > +}
> > +
> > +int host_system_suspend(void)
> > +{
> > +    int status;
> > +
> > +    /* TODO: drop check after verification that features can work toge=
ther */
> > +    if ( llc_coloring_enabled )
> > +    {
> > +        dprintk(XENLOG_ERR,
> > +                "System suspend is not supported with LLC_COLORING ena=
bled\n");
> > +        return -ENOSYS;
> > +    }
> > +
> > +    /*
> > +     * system_suspend should be called when Dom0 finalizes the suspend
> > +     * procedure from its boot core (VCPU#0). However, Dom0's VCPU#0 c=
ould
> > +     * be mapped to any PCPU (this function could be executed by any P=
CPU).
> > +     * The suspend procedure has to be finalized by the PCPU#0 (non-bo=
ot
> > +     * PCPUs will be disabled during the suspend).
> > +     */
> > +    status =3D continue_hypercall_on_cpu(0, system_suspend, NULL);
> > +
> > +    /*
> > +     * If an error happened, there is nothing that needs to be done he=
re
> > +     * because the system_suspend always returns in fully functional s=
tate
> > +     * no matter what the outcome of suspend procedure is. If the syst=
em
> > +     * suspended successfully the function will return 0 after the res=
ume.
> > +     * Otherwise, if an error is returned it means Xen did not suspend=
ed,
> > +     * but it is still in the same state as if the system_suspend was =
never
> > +     * called. We dump a debug message in case of an error for debuggi=
ng/
> > +     * logging purpose.
> > +     */
> > +    if ( status )
> > +        dprintk(XENLOG_ERR, "Failed to suspend, errno=3D%d\n", status)=
;
> > +
> > +    return status;
> > +}
> > +
> > +/*
> > + * Local variables:
> > + * mode: C
> > + * c-file-style: "BSD"
> > + * c-basic-offset: 4
> > + * indent-tabs-mode: nil
> > + * End:
> > + */
> > diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
> > index 67d369a8a2..757e719ea7 100644
> > --- a/xen/arch/arm/vpsci.c
> > +++ b/xen/arch/arm/vpsci.c
> > @@ -4,6 +4,7 @@
> >  #include 
> >
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -214,9 +215,10 @@ static int32_t do_psci_1_0_system_suspend(register=
_t epoint, register_t cid)
> >      struct vcpu *v;
> >      struct domain *d =3D current->domain;
> >
> > -    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> > +#ifndef CONFIG_SYSTEM_SUSPEND
> >      if ( is_hardware_domain(d) )
> >          return PSCI_NOT_SUPPORTED;
> > +#endif
> >
> >      /* Ensure that all CPUs other than the calling one are offline */
> >      domain_lock(d);
> > @@ -234,6 +236,14 @@ static int32_t do_psci_1_0_system_suspend(register=
_t epoint, register_t cid)
> >      if ( rc )
> >          return PSCI_DENIED;
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +    if ( is_hardware_domain(d) && host_system_suspend() )
> > +    {
> > +        domain_resume_nopause(d);
> > +        return PSCI_DENIED;
> > +    }
> > +#endif
> > +
> >      rc =3D do_setup_vcpu_ctx(current, epoint, cid);
> >      if ( rc !=3D PSCI_SUCCESS )
> >      {
> > diff --git a/xen/common/domain.c b/xen/common/domain.c
> > index c3609b0cb0..414a691242 100644
> > --- a/xen/common/domain.c
> > +++ b/xen/common/domain.c
> > @@ -1311,7 +1311,11 @@ int domain_shutdown(struct domain *d, u8 reason)
> >          d->shutdown_code =3D reason;
> >      reason =3D d->shutdown_code;
> >
> > +#if defined(CONFIG_SYSTEM_SUSPEND) && defined(CONFIG_ARM)
> > +    if ( reason !=3D SHUTDOWN_suspend && is_hardware_domain(d) )
> > +#else
> >      if ( is_hardware_domain(d) )
> > +#endif
> >          hwdom_shutdown(reason);
> >
> >      if ( d->is_shutting_down )
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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From: Mykola Kvach 
Date: Tue, 26 Aug 2025 16:42:21 +0300
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Message-ID: 
Subject: Re: [PATCH v5 08/12] xen/arm: Implement PSCI SYSTEM_SUSPEND call
 (host interface)
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , 
	Mirela Simonovic , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Saeed Nowshadi , 
	Mykyta Poturai , Mykola Kvach 
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Hi Volodymyr,

On Sat, Aug 23, 2025 at 4:06=E2=80=AFAM Volodymyr Babchuk
 wrote:
>
>
> Hi Mykola,
>
> Sequence of next 3 patches (and previous one) really puzzles me. Can you
> first implement hyp_resume() function, then add PSCI_SYSTEM_SUSPEND call
> and only then implement system_suspend() function? Why do this backwards?

This order comes from the first version of the patch series.
I'll reorder the commits in the next version.

>
> Mykola Kvach  writes:
>
> > From: Mirela Simonovic 
> >
> > Invoke PSCI SYSTEM_SUSPEND to finalize Xen's suspend sequence on ARM64 =
platforms.
> > Pass the resume entry point (hyp_resume) as the first argument to EL3. =
The resume
> > handler is currently a stub and will be implemented later in assembly. =
Ignore the
> > context ID argument, as is done in Linux.
> >
> > Only enable this path when CONFIG_SYSTEM_SUSPEND is set and
> > PSCI version is >=3D 1.0.
> >
> > Signed-off-by: Mirela Simonovic 
> > Signed-off-by: Saeed Nowshadi 
> > Signed-off-by: Mykyta Poturai 
> > Signed-off-by: Mykola Kvach 
> > ---
> > Changes in v4:
> >   - select the appropriate PSCI SYSTEM_SUSPEND function ID based on pla=
tform
> >   - update comments and commit message to reflect recent changes
> >
> > Changes in v3:
> >   - return PSCI_NOT_SUPPORTED instead of a hardcoded 1 on ARM32
> >   - check PSCI version before invoking SYSTEM_SUSPEND in call_psci_syst=
em_suspend
> > ---
> >  xen/arch/arm/arm64/head.S          |  8 ++++++++
> >  xen/arch/arm/include/asm/psci.h    |  1 +
> >  xen/arch/arm/include/asm/suspend.h |  2 ++
> >  xen/arch/arm/psci.c                | 23 ++++++++++++++++++++++-
> >  xen/arch/arm/suspend.c             |  5 +++++
> >  5 files changed, 38 insertions(+), 1 deletion(-)
> >
> > diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> > index 72c7b24498..3522c497c5 100644
> > --- a/xen/arch/arm/arm64/head.S
> > +++ b/xen/arch/arm/arm64/head.S
> > @@ -561,6 +561,14 @@ END(efi_xen_start)
> >
> >  #endif /* CONFIG_ARM_EFI */
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +
> > +FUNC(hyp_resume)
> > +        b .
> > +END(hyp_resume)
> > +
> > +#endif /* CONFIG_SYSTEM_SUSPEND */
> > +
> >  /*
> >   * Local variables:
> >   * mode: ASM
> > diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm=
/psci.h
> > index 48a93e6b79..bb3c73496e 100644
> > --- a/xen/arch/arm/include/asm/psci.h
> > +++ b/xen/arch/arm/include/asm/psci.h
> > @@ -23,6 +23,7 @@ int call_psci_cpu_on(int cpu);
> >  void call_psci_cpu_off(void);
> >  void call_psci_system_off(void);
> >  void call_psci_system_reset(void);
> > +int call_psci_system_suspend(void);
> >
> >  /* Range of allocated PSCI function numbers */
> >  #define      PSCI_FNUM_MIN_VALUE                 _AC(0,U)
> > diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/=
asm/suspend.h
> > index 78d0e2383b..55041a5d06 100644
> > --- a/xen/arch/arm/include/asm/suspend.h
> > +++ b/xen/arch/arm/include/asm/suspend.h
> > @@ -7,6 +7,8 @@
> >
> >  int host_system_suspend(void);
> >
> > +void hyp_resume(void);
> > +
> >  #endif /* CONFIG_SYSTEM_SUSPEND */
> >
> >  #endif /* __ASM_ARM_SUSPEND_H__ */
> > diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c
> > index b6860a7760..c9d126b195 100644
> > --- a/xen/arch/arm/psci.c
> > +++ b/xen/arch/arm/psci.c
> > @@ -17,17 +17,20 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  /*
> >   * While a 64-bit OS can make calls with SMC32 calling conventions, fo=
r
> >   * some calls it is necessary to use SMC64 to pass or return 64-bit va=
lues.
> > - * For such calls PSCI_0_2_FN_NATIVE(x) will choose the appropriate
> > + * For such calls PSCI_*_FN_NATIVE(x) will choose the appropriate
> >   * (native-width) function ID.
> >   */
> >  #ifdef CONFIG_ARM_64
> >  #define PSCI_0_2_FN_NATIVE(name)    PSCI_0_2_FN64_##name
> > +#define PSCI_1_0_FN_NATIVE(name)    PSCI_1_0_FN64_##name
> >  #else
> >  #define PSCI_0_2_FN_NATIVE(name)    PSCI_0_2_FN32_##name
> > +#define PSCI_1_0_FN_NATIVE(name)    PSCI_1_0_FN32_##name
> >  #endif
> >
> >  uint32_t psci_ver;
> > @@ -60,6 +63,24 @@ void call_psci_cpu_off(void)
> >      }
> >  }
> >
> > +int call_psci_system_suspend(void)
> > +{
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +    struct arm_smccc_res res;
> > +
> > +    if ( psci_ver < PSCI_VERSION(1, 0) )
> > +        return PSCI_NOT_SUPPORTED;
> > +
> > +    /* 2nd argument (context ID) is not used */
> > +    arm_smccc_smc(PSCI_1_0_FN_NATIVE(SYSTEM_SUSPEND), __pa(hyp_resume)=
, &res);
> > +    return PSCI_RET(res);
> > +#else
> > +    dprintk(XENLOG_WARNING,
> > +            "SYSTEM_SUSPEND not supported (CONFIG_SYSTEM_SUSPEND disab=
led)\n");
> > +    return PSCI_NOT_SUPPORTED;
> > +#endif
> > +}
> > +
> >  void call_psci_system_off(void)
> >  {
> >      if ( psci_ver > PSCI_VERSION(0, 1) )
> > diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
> > index abf4b928ce..11e86b7f51 100644
> > --- a/xen/arch/arm/suspend.c
> > +++ b/xen/arch/arm/suspend.c
> > @@ -1,5 +1,6 @@
> >  /* SPDX-License-Identifier: GPL-2.0-only */
> >
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -70,6 +71,10 @@ static long system_suspend(void *data)
> >       */
> >      update_boot_mapping(true);
> >
> > +    status =3D call_psci_system_suspend();
> > +    if ( status )
> > +        dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=3D%d\=
n", status);
>
> So this is where missing call to PSCI_SYSTEM_SUSPEND is...
>
> > +
> >      system_state =3D SYS_STATE_resume;
> >      update_boot_mapping(false);
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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From: Mykola Kvach 
Date: Tue, 26 Aug 2025 16:42:26 +0300
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Subject: Re: [PATCH v5 10/12] xen/arm: Save/restore context on suspend/resume
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , 
	Mirela Simonovic , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Saeed Nowshadi , 
	Mykyta Poturai , Mykola Kvach 
Content-Type: text/plain; charset="UTF-8"
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Hi Volodymyr,

On Sat, Aug 23, 2025 at 8:34=E2=80=AFPM Volodymyr Babchuk
 wrote:
>
>
> Hi Mykola,
>
> Mykola Kvach  writes:
>
> > From: Mirela Simonovic 
> >
> > The context of CPU general purpose and system control registers
> > has to be saved on suspend and restored on resume. This is
> > implemented in hyp_suspend and before the return from hyp_resume
> > function. The hyp_suspend is invoked just before the PSCI system
> > suspend call is issued to the ATF. The hyp_suspend has to return a
> > non-zero value so that the calling 'if' statement evaluates to true,
> > causing the system suspend to be invoked. Upon the resume, context
> > saved on suspend will be restored, including the link register.
> > Therefore, after restoring the context the control flow will
> > return to the address pointed by the saved link register, which
> > is the place from which the hyp_suspend was called. To ensure
> > that the calling 'if' statement doesn't again evaluate to true
> > and initiate system suspend, hyp_resume has to return a zero value
> > after restoring the context.
> >
> > Note that the order of saving register context into cpu_context
> > structure has to match the order of restoring.
> >
> > Support for ARM32 is not implemented. Instead, compilation fails with a
> > build-time error if suspend is enabled for ARM32.
> >
> > Signed-off-by: Mirela Simonovic 
> > Signed-off-by: Saeed Nowshadi 
> > Signed-off-by: Mykyta Poturai 
> > Signed-off-by: Mykola Kvach 
> > ---
> > Changes in v4:
> > - produce build-time error for ARM32 when CONFIG_SYSTEM_SUSPEND is enab=
led
> > - use register_t instead of uint64_t in cpu_context structure
> > ---
> >  xen/arch/arm/arm64/head.S          | 91 +++++++++++++++++++++++++++++-
> >  xen/arch/arm/include/asm/suspend.h | 20 +++++++
> >  xen/arch/arm/suspend.c             | 23 +++++++-
> >  3 files changed, 130 insertions(+), 4 deletions(-)
> >
> > diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> > index 596e960152..ad8b48de3a 100644
> > --- a/xen/arch/arm/arm64/head.S
> > +++ b/xen/arch/arm/arm64/head.S
> > @@ -562,6 +562,52 @@ END(efi_xen_start)
> >  #endif /* CONFIG_ARM_EFI */
> >
> >  #ifdef CONFIG_SYSTEM_SUSPEND
> > +/*
> > + * int hyp_suspend(struct cpu_context *ptr)
> > + *
> > + * x0 - pointer to the storage where callee's context will be saved
> > + *
> > + * CPU context saved here will be restored on resume in hyp_resume fun=
ction.
> > + * hyp_suspend shall return a non-zero value. Upon restoring context
> > + * hyp_resume shall return value zero instead. From C code that invoke=
s
> > + * hyp_suspend, the return value is interpreted to determine whether t=
he context
> > + * is saved (hyp_suspend) or restored (hyp_resume).
> > + */
> > +FUNC(hyp_suspend)
>
> I don't think that hyp_suspend is the correct name, as this function in
> fact suspend_nothing. Maybe "prepare_resume_ctx" will be better?

Not a problem to rename it.

>
> > +        /* Store callee-saved registers */
> > +        stp     x19, x20, [x0], #16
>
> If you have struct cpu_context defined, then you probably should use
> define provided by  to access struct fields. Otherwise,
> it will be really easy to get desync between struct definition and this
> asm code.
>
> > +        stp     x21, x22, [x0], #16
> > +        stp     x23, x24, [x0], #16
> > +        stp     x25, x26, [x0], #16
> > +        stp     x27, x28, [x0], #16
> > +        stp     x29, lr, [x0], #16
> > +
> > +        /* Store stack-pointer */
> > +        mov     x2, sp
> > +        str     x2, [x0], #8
> > +
> > +        /* Store system control registers */
> > +        mrs     x2, VBAR_EL2
> > +        str     x2, [x0], #8
> > +        mrs     x2, VTCR_EL2
> > +        str     x2, [x0], #8
> > +        mrs     x2, VTTBR_EL2
> > +        str     x2, [x0], #8
> > +        mrs     x2, TPIDR_EL2
> > +        str     x2, [x0], #8
> > +        mrs     x2, MDCR_EL2
> > +        str     x2, [x0], #8
> > +        mrs     x2, HSTR_EL2
> > +        str     x2, [x0], #8
> > +        mrs     x2, CPTR_EL2
> > +        str     x2, [x0], #8
> > +        mrs     x2, HCR_EL2
> > +        str     x2, [x0], #8
> > +
> > +        /* hyp_suspend must return a non-zero value */
> > +        mov     x0, #1
> > +        ret
> > +END(hyp_suspend)
> >
> >  FUNC(hyp_resume)
> >          /* Initialize the UART if earlyprintk has been enabled. */
> > @@ -580,7 +626,50 @@ FUNC(hyp_resume)
> >          b     enable_secondary_cpu_mm
> >
> >  mmu_resumed:
> > -        b .
> > +        /*
> > +         * Now we can access the cpu_context, so restore the context h=
ere
> > +         * TODO: can we reuse __context_switch and saved_context struc=
t here ?
> > +         */
>
> This is a great idea and I like it very much, but sadly saved_context
> struct has no fields for system _EL2 registers.
>
> > +        ldr     x0, =3Dcpu_context
> > +
> > +        /* Restore callee-saved registers */
> > +        ldp     x19, x20, [x0], #16
> > +        ldp     x21, x22, [x0], #16
> > +        ldp     x23, x24, [x0], #16
> > +        ldp     x25, x26, [x0], #16
> > +        ldp     x27, x28, [x0], #16
> > +        ldp     x29, lr, [x0], #16
> > +
> > +        /* Restore stack pointer */
> > +        ldr     x2, [x0], #8
> > +        mov     sp, x2
> > +
> > +        /* Restore system control registers */
> > +        ldr     x2, [x0], #8
> > +        msr     VBAR_EL2, x2
> > +        ldr     x2, [x0], #8
> > +        msr     VTCR_EL2, x2
> > +        ldr     x2, [x0], #8
> > +        msr     VTTBR_EL2, x2
> > +        ldr     x2, [x0], #8
> > +        msr     TPIDR_EL2, x2
> > +        ldr     x2, [x0], #8
> > +        msr     MDCR_EL2, x2
> > +        ldr     x2, [x0], #8
> > +        msr     HSTR_EL2, x2
> > +        ldr     x2, [x0], #8
> > +        msr     CPTR_EL2, x2
> > +        ldr     x2, [x0], #8
> > +        msr     HCR_EL2, x2
> > +        isb
> > +
> > +        /* Since context is restored return from this function will ap=
pear as
> > +         * return from hyp_suspend. To distinguish a return from hyp_s=
uspend
> > +         * which is called upon finalizing the suspend, as opposed to =
return
> > +         * from this function which executes on resume, we need to ret=
urn zero
> > +         * value here. */
> > +        mov x0, #0
> > +        ret
> >  END(hyp_resume)
> >
> >  #endif /* CONFIG_SYSTEM_SUSPEND */
> > diff --git a/xen/arch/arm/include/asm/suspend.h b/xen/arch/arm/include/=
asm/suspend.h
> > index 55041a5d06..ae71ccb87b 100644
> > --- a/xen/arch/arm/include/asm/suspend.h
> > +++ b/xen/arch/arm/include/asm/suspend.h
> > @@ -5,9 +5,29 @@
> >
> >  #ifdef CONFIG_SYSTEM_SUSPEND
> >
> > +#ifdef CONFIG_ARM_64
> > +struct cpu_context {
> > +    register_t callee_regs[12];
> > +    register_t sp;
> > +    register_t vbar_el2;
> > +    register_t vtcr_el2;
> > +    register_t vttbr_el2;
> > +    register_t tpidr_el2;
> > +    register_t mdcr_el2;
> > +    register_t hstr_el2;
> > +    register_t cptr_el2;
> > +    register_t hcr_el2;
> > +} __aligned(16);
> > +#else
> > +#error "Define cpu_context structure for arm32"
> > +#endif
> > +
> > +extern struct cpu_context cpu_context;
> > +
> >  int host_system_suspend(void);
> >
> >  void hyp_resume(void);
> > +int hyp_suspend(struct cpu_context *ptr);
> >
> >  #endif /* CONFIG_SYSTEM_SUSPEND */
> >
> > diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
> > index 08b6acaede..b5398e5ca6 100644
> > --- a/xen/arch/arm/suspend.c
> > +++ b/xen/arch/arm/suspend.c
> > @@ -1,6 +1,7 @@
> >  /* SPDX-License-Identifier: GPL-2.0-only */
> >
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -17,6 +18,8 @@
> >   *  - Investigate feasibility and need for implementing system suspend=
 on ARM32
> >   */
> >
> > +struct cpu_context cpu_context;
> > +
> >  /* Xen suspend. Note: data is not used (suspend is the suspend to RAM)=
 */
> >  static long system_suspend(void *data)
> >  {
> > @@ -73,9 +76,23 @@ static long system_suspend(void *data)
> >       */
> >      update_boot_mapping(true);
> >
> > -    status =3D call_psci_system_suspend();
> > -    if ( status )
> > -        dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=3D%d\=
n", status);
> > +    if ( hyp_suspend(&cpu_context) )
> > +    {
> > +        status =3D call_psci_system_suspend();
> > +        /*
> > +         * If suspend is finalized properly by above system suspend PS=
CI call,
> > +         * the code below in this 'if' branch will never execute. Exec=
ution
> > +         * will continue from hyp_resume which is the hypervisor's res=
ume point.
> > +         * In hyp_resume CPU context will be restored and since link-r=
egister is
> > +         * restored as well, it will appear to return from hyp_suspend=
. The
> > +         * difference in returning from hyp_suspend on system suspend =
versus
> > +         * resume is in function's return value: on suspend, the retur=
n value is
> > +         * a non-zero value, on resume it is zero. That is why the con=
trol flow
> > +         * will not re-enter this 'if' branch on resume.
> > +         */
>
> Looks like this comment is misplaced. It should be before "if (
> hyp_suspend() )", right?

Actually, the comment is correctly placed here and does not need to be move=
d.

>
> > +        if ( status )
> > +            dprintk(XENLOG_WARNING, "PSCI system suspend failed, err=
=3D%d\n", status);
> > +    }
> >
> >      system_state =3D SYS_STATE_resume;
> >      update_boot_mapping(false);
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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From: Mykola Kvach 
Date: Tue, 26 Aug 2025 16:42:49 +0300
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Subject: Re: [PATCH v5 12/12] xen/arm: Suspend/resume IOMMU on Xen suspend/resume
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , 
	Oleksandr Tyshchenko , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Mykola Kvach , 
	Oleksandr Andrushchenko 
Content-Type: text/plain; charset="UTF-8"
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Hi Volodymyr,

On Sat, Aug 23, 2025 at 8:55=E2=80=AFPM Volodymyr Babchuk
 wrote:
>
> Hi,
>
> Mykola Kvach  writes:
>
> > From: Oleksandr Tyshchenko 
> >
> > This is done using generic iommu_suspend/resume functions that cause
> > IOMMU driver specific suspend/resume handlers to be called for enabled
> > IOMMU (if one has suspend/resume driver handlers implemented).
> >
> > These handlers work only when IPMMU-VMSA is used; otherwise,
> > we return an error during system suspend requests.
> >
> > Signed-off-by: Oleksandr Tyshchenko 
> > Signed-off-by: Mykola Kvach 
> > Tested-by: Oleksandr Andrushchenko 
> > ---
> >  xen/arch/arm/suspend.c | 21 +++++++++++++++++++++
> >  1 file changed, 21 insertions(+)
> >
> > diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
> > index b5398e5ca6..cb86426ebd 100644
> > --- a/xen/arch/arm/suspend.c
> > +++ b/xen/arch/arm/suspend.c
> > @@ -4,6 +4,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >
> > @@ -49,6 +50,13 @@ static long system_suspend(void *data)
> >
> >      time_suspend();
> >
> > +    status =3D iommu_suspend();
> > +    if ( status )
> > +    {
> > +        system_state =3D SYS_STATE_resume;
> > +        goto resume_time;
> > +    }
> > +
> >      local_irq_save(flags);
> >      status =3D gic_suspend();
> >      if ( status )
> > @@ -105,6 +113,10 @@ static long system_suspend(void *data)
> >
> >   resume_irqs:
> >      local_irq_restore(flags);
> > +
> > +    iommu_resume();
> > +
> > + resume_time:
> >      time_resume();
> >
> >   resume_nonboot_cpus:
> > @@ -140,6 +152,15 @@ int host_system_suspend(void)
> >          return -ENOSYS;
> >      }
> >
> > +    /* TODO: drop check once suspend/resume support for SMMU is implem=
ented */
> > +#ifndef CONFIG_IPMMU_VMSA
>
> This check is meaningless, as you can have CONFIG_IPMMU_VMSA enabled
> along with CONFIG_ARM_SMMU on a system with SMMU. I think it is enough
> that iommu_suspend() will fail during system_suspend(), isn't it?

Not exactly. In the case of SMMU, we don=E2=80=99t have valid iommu_suspend=
/iommu_resume
handlers. So it=E2=80=99s possible to have CONFIG_ARM_SMMU enabled and iomm=
u_enabled
set, but without the appropriate suspend handlers. This could lead to
a crash during
system_suspend().


>
>
> > +    if ( iommu_enabled )
> > +    {
> > +        dprintk(XENLOG_ERR, "IOMMU is enabled, suspend not supported y=
et\n");
> > +        return -ENOSYS;
> > +    }
> > +#endif
> > +
> >      /*
> >       * system_suspend should be called when Dom0 finalizes the suspend
> >       * procedure from its boot core (VCPU#0). However, Dom0's VCPU#0 c=
ould
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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From: Mykola Kvach 
Date: Tue, 26 Aug 2025 16:42:31 +0300
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Subject: Re: [PATCH v5 11/12] iommu/ipmmu-vmsa: Implement suspend/resume callbacks
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , 
	Oleksandr Tyshchenko , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Mykola Kvach 
Content-Type: text/plain; charset="UTF-8"
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Hi Volodymyr,

On Sat, Aug 23, 2025 at 8:48=E2=80=AFPM Volodymyr Babchuk
 wrote:
>
>
> Hi Mykola,
>
> Mykola Kvach  writes:
>
> > From: Oleksandr Tyshchenko 
> >
> > Store and restore active context and micro-TLB registers.
> >
> > Tested on R-Car H3 Starter Kit.
> >
> > Signed-off-by: Oleksandr Tyshchenko 
> > Signed-off-by: Mykola Kvach 
> > ---
> >  xen/drivers/passthrough/arm/ipmmu-vmsa.c | 269 +++++++++++++++++++++++
> >  1 file changed, 269 insertions(+)
> >
> > diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/pas=
sthrough/arm/ipmmu-vmsa.c
> > index dac0dd6d46..ced762657a 100644
> > --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> > +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c
> > @@ -58,6 +58,8 @@
> >  #define dev_print(dev, lvl, fmt, ...)    \
> >      printk(lvl "ipmmu: %s: " fmt, dev_name(dev), ## __VA_ARGS__)
> >
> > +#define dev_dbg(dev, fmt, ...)    \
> > +    dev_print(dev, XENLOG_DEBUG, fmt, ## __VA_ARGS__)
> >  #define dev_info(dev, fmt, ...)    \
> >      dev_print(dev, XENLOG_INFO, fmt, ## __VA_ARGS__)
> >  #define dev_warn(dev, fmt, ...)    \
> > @@ -117,6 +119,23 @@ struct ipmmu_features {
> >      unsigned int imuctr_ttsel_mask;
> >  };
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +
> > +struct hw_register {
> > +    const char *reg_name;
>
> Do you really need to store register name? It is not used anywhere.

No, it=E2=80=99s not needed. We can remove it.
Thank you for catching that.

>
> > +    unsigned int reg_offset;
> > +    unsigned int reg_data;
> > +};
> > +
> > +struct ipmmu_vmsa_backup {
> > +    struct device *dev;
> > +    unsigned int *utlbs_val;
> > +    unsigned int *asids_val;
> > +    struct list_head list;
> > +};
> > +
> > +#endif
> > +
> >  /* Root/Cache IPMMU device's information */
> >  struct ipmmu_vmsa_device {
> >      struct device *dev;
> > @@ -129,6 +148,9 @@ struct ipmmu_vmsa_device {
> >      struct ipmmu_vmsa_domain *domains[IPMMU_CTX_MAX];
> >      unsigned int utlb_refcount[IPMMU_UTLB_MAX];
> >      const struct ipmmu_features *features;
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +    struct hw_register *reg_backup[IPMMU_CTX_MAX];
> > +#endif
> >  };
> >
> >  /*
> > @@ -534,6 +556,235 @@ static void ipmmu_domain_free_context(struct ipmm=
u_vmsa_device *mmu,
> >      spin_unlock_irqrestore(&mmu->lock, flags);
> >  }
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +
> > +static DEFINE_SPINLOCK(ipmmu_devices_backup_lock);
> > +static LIST_HEAD(ipmmu_devices_backup);
> > +
> > +#define HW_REGISTER_BACKUP_SIZE 4
> > +
> > +static struct hw_register root_pgtable[IPMMU_CTX_MAX][HW_REGISTER_BACK=
UP_SIZE] =3D {
> > +    [0 ... (IPMMU_CTX_MAX - 1)] =3D {
> > +        {"IMTTLBR0", IMTTLBR0, 0},
> > +        {"IMTTUBR0", IMTTUBR0, 0},
> > +        {"IMTTBCR",  IMTTBCR,  0},
> > +        {"IMCTR",    IMCTR,    0},
>
> Taking into account that only 4 registers needs to be saved, will it be
> easier and more efficient to have a hardcoded struct like this?
>
> struct ipmmu_reg_ctx {
>     unsigned int imttlbr0;
>     unsigned int imttubr0;
>     unsigned int imttbcr;
>     unsigned int imctr;
> }
>
> instead of hw_register[] ?
>
> Especially taking into account that struct ipmmu_vmsa_backup{} does
> exactly this.

I see no problem with doing that.

>
>
> > +    }
> > +};
> > +
> > +static uint32_t ipmmu_imuasid_read(struct ipmmu_vmsa_device *mmu,
> > +                                   unsigned int utlb)
> > +{
> > +    return ipmmu_read(mmu, ipmmu_utlb_reg(mmu, IMUASID(utlb)));
> > +}
> > +
> > +static void ipmmu_utlbs_backup(struct ipmmu_vmsa_device *mmu)
> > +{
> > +    struct ipmmu_vmsa_backup *backup_data;
> > +
> > +    dev_dbg(mmu->dev, "Handle micro-TLBs backup\n");
> > +
> > +    spin_lock(&ipmmu_devices_backup_lock);
> > +
> > +    list_for_each_entry( backup_data, &ipmmu_devices_backup, list )
> > +    {
> > +        struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(backup_da=
ta->dev);
> > +        unsigned int i;
> > +
> > +        if ( to_ipmmu(backup_data->dev) !=3D mmu )
> > +            continue;
> > +
> > +        for ( i =3D 0; i < fwspec->num_ids; i++ )
> > +        {
> > +            unsigned int utlb =3D fwspec->ids[i];
> > +
> > +            backup_data->asids_val[i] =3D ipmmu_imuasid_read(mmu, utlb=
);
> > +            backup_data->utlbs_val[i] =3D ipmmu_imuctr_read(mmu, utlb)=
;
> > +        }
> > +    }
> > +
> > +    spin_unlock(&ipmmu_devices_backup_lock);
> > +}
> > +
> > +static void ipmmu_utlbs_restore(struct ipmmu_vmsa_device *mmu)
> > +{
> > +    struct ipmmu_vmsa_backup *backup_data;
> > +
> > +    dev_dbg(mmu->dev, "Handle micro-TLBs restore\n");
> > +
> > +    spin_lock(&ipmmu_devices_backup_lock);
> > +
> > +    list_for_each_entry( backup_data, &ipmmu_devices_backup, list )
> > +    {
> > +        struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(backup_da=
ta->dev);
> > +        unsigned int i;
> > +
> > +        if ( to_ipmmu(backup_data->dev) !=3D mmu )
> > +            continue;
> > +
> > +        for ( i =3D 0; i < fwspec->num_ids; i++ )
> > +        {
> > +            unsigned int utlb =3D fwspec->ids[i];
> > +
> > +            ipmmu_imuasid_write(mmu, utlb, backup_data->asids_val[i]);
> > +            ipmmu_imuctr_write(mmu, utlb, backup_data->utlbs_val[i]);
> > +        }
> > +    }
> > +
> > +    spin_unlock(&ipmmu_devices_backup_lock);
> > +}
> > +
> > +static void ipmmu_domain_backup_context(struct ipmmu_vmsa_domain *doma=
in)
> > +{
> > +    struct ipmmu_vmsa_device *mmu =3D domain->mmu->root;
> > +    struct hw_register *reg =3D mmu->reg_backup[domain->context_id];
> > +    unsigned int i;
> > +
> > +    dev_dbg(mmu->dev, "Handle domain context %u backup\n", domain->con=
text_id);
> > +
> > +    for ( i =3D 0; i < HW_REGISTER_BACKUP_SIZE; i++ )
> > +        reg[i].reg_data =3D ipmmu_ctx_read_root(domain, reg[i].reg_off=
set);
> > +}
> > +
> > +static void ipmmu_domain_restore_context(struct ipmmu_vmsa_domain *dom=
ain)
> > +{
> > +    struct ipmmu_vmsa_device *mmu =3D domain->mmu->root;
> > +    struct hw_register *reg =3D mmu->reg_backup[domain->context_id];
> > +    unsigned int i;
> > +
> > +    dev_dbg(mmu->dev, "Handle domain context %u restore\n", domain->co=
ntext_id);
> > +
> > +    for ( i =3D 0; i < HW_REGISTER_BACKUP_SIZE; i++ )
> > +    {
> > +        if ( reg[i].reg_offset !=3D IMCTR )
> > +            ipmmu_ctx_write_root(domain, reg[i].reg_offset, reg[i].reg=
_data);
> > +        else
> > +            ipmmu_ctx_write_all(domain, reg[i].reg_offset,
> > +                                reg[i].reg_data | IMCTR_FLUSH);
> > +    }
> > +}
> > +
> > +/*
> > + * Xen: Unlike Linux implementation, Xen uses a single driver instance
> > + * for handling all IPMMUs. There is no framework for ipmmu_suspend/re=
sume
> > + * callbacks to be invoked for each IPMMU device. So, we need to itera=
te
> > + * through all registered IPMMUs performing required actions.
> > + *
> > + * Also take care of restoring special settings, such as translation
> > + * table format, etc.
> > + */
> > +static int __must_check ipmmu_suspend(void)
> > +{
> > +    struct ipmmu_vmsa_device *mmu;
> > +
> > +    if ( !iommu_enabled )
> > +        return 0;
> > +
> > +    printk(XENLOG_DEBUG "ipmmu: Suspending ...\n");
> > +
> > +    spin_lock(&ipmmu_devices_lock);
> > +
> > +    list_for_each_entry( mmu, &ipmmu_devices, list )
> > +    {
> > +        if ( ipmmu_is_root(mmu) )
> > +        {
> > +            unsigned int i;
> > +
> > +            for ( i =3D 0; i < mmu->num_ctx; i++ )
> > +            {
> > +                if ( !mmu->domains[i] )
> > +                    continue;
> > +                ipmmu_domain_backup_context(mmu->domains[i]);
> > +            }
> > +        }
> > +        else
> > +            ipmmu_utlbs_backup(mmu);
> > +    }
> > +
> > +    spin_unlock(&ipmmu_devices_lock);
> > +
> > +    return 0;
> > +}
> > +
> > +static void ipmmu_resume(void)
> > +{
> > +    struct ipmmu_vmsa_device *mmu;
> > +
> > +    if ( !iommu_enabled )
> > +        return;
> > +
> > +    printk(XENLOG_DEBUG "ipmmu: Resuming ...\n");
> > +
> > +    spin_lock(&ipmmu_devices_lock);
> > +
> > +    list_for_each_entry( mmu, &ipmmu_devices, list )
> > +    {
> > +        uint32_t reg;
> > +
> > +        /* Do not use security group function */
> > +        reg =3D IMSCTLR + mmu->features->control_offset_base;
> > +        ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) & ~IMSCTLR_USE_SECG=
RP);
> > +
> > +        if ( ipmmu_is_root(mmu) )
> > +        {
> > +            unsigned int i;
> > +
> > +            /* Use stage 2 translation table format */
> > +            reg =3D IMSAUXCTLR + mmu->features->control_offset_base;
> > +            ipmmu_write(mmu, reg, ipmmu_read(mmu, reg) | IMSAUXCTLR_S2=
PTE);
> > +
> > +            for ( i =3D 0; i < mmu->num_ctx; i++ )
> > +            {
> > +                if ( !mmu->domains[i] )
> > +                    continue;
> > +                ipmmu_domain_restore_context(mmu->domains[i]);
> > +            }
> > +        }
> > +        else
> > +            ipmmu_utlbs_restore(mmu);
> > +    }
> > +
> > +    spin_unlock(&ipmmu_devices_lock);
> > +}
> > +
> > +static int ipmmu_alloc_ctx_suspend(struct device *dev)
> > +{
> > +    struct ipmmu_vmsa_backup *backup_data;
> > +    unsigned int *utlbs_val, *asids_val;
> > +    struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(dev);
> > +
> > +    utlbs_val =3D xzalloc_array(unsigned int, fwspec->num_ids);
> > +    if ( !utlbs_val )
> > +        return -ENOMEM;
> > +
> > +    asids_val =3D xzalloc_array(unsigned int, fwspec->num_ids);
> > +    if ( !asids_val )
> > +    {
> > +        xfree(utlbs_val);
> > +        return -ENOMEM;
> > +    }
> > +
> > +    backup_data =3D xzalloc(struct ipmmu_vmsa_backup);
> > +    if ( !backup_data )
> > +    {
> > +        xfree(utlbs_val);
> > +        xfree(asids_val);
> > +        return -ENOMEM;
> > +    }
> > +
> > +    backup_data->dev =3D dev;
> > +    backup_data->utlbs_val =3D utlbs_val;
> > +    backup_data->asids_val =3D asids_val;
> > +
> > +    spin_lock(&ipmmu_devices_backup_lock);
> > +    list_add(&backup_data->list, &ipmmu_devices_backup);
> > +    spin_unlock(&ipmmu_devices_backup_lock);
> > +
> > +    return 0;
> > +}
> > +
> > +#endif /* CONFIG_SYSTEM_SUSPEND */
> > +
> >  static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
> >  {
> >      uint64_t ttbr;
> > @@ -546,6 +797,9 @@ static int ipmmu_domain_init_context(struct ipmmu_v=
msa_domain *domain)
> >          return ret;
> >
> >      domain->context_id =3D ret;
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +    domain->mmu->root->reg_backup[ret] =3D root_pgtable[ret];
> > +#endif
> >
> >      /*
> >       * TTBR0
> > @@ -602,6 +856,9 @@ static void ipmmu_domain_destroy_context(struct ipm=
mu_vmsa_domain *domain)
> >      ipmmu_ctx_write_root(domain, IMCTR, IMCTR_FLUSH);
> >      ipmmu_tlb_sync(domain);
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +    domain->mmu->root->reg_backup[domain->context_id] =3D NULL;
> > +#endif
> >      ipmmu_domain_free_context(domain->mmu->root, domain->context_id);
> >  }
> >
> > @@ -1307,6 +1564,14 @@ static int ipmmu_add_device(u8 devfn, struct dev=
ice *dev)
> >      /* Let Xen know that the master device is protected by an IOMMU. *=
/
> >      dt_device_set_protected(dev_to_dt(dev));
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +    if ( ipmmu_alloc_ctx_suspend(dev) )
> > +    {
> > +        dev_err(dev, "Failed to allocate context for suspend\n");
> > +        return -ENOMEM;
> > +    }
> > +#endif
> > +
> >      dev_info(dev, "Added master device (IPMMU %s micro-TLBs %u)\n",
> >               dev_name(fwspec->iommu_dev), fwspec->num_ids);
> >
> > @@ -1372,6 +1637,10 @@ static const struct iommu_ops ipmmu_iommu_ops =
=3D
> >      .unmap_page      =3D arm_iommu_unmap_page,
> >      .dt_xlate        =3D ipmmu_dt_xlate,
> >      .add_device      =3D ipmmu_add_device,
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +    .suspend         =3D ipmmu_suspend,
> > +    .resume          =3D ipmmu_resume,
> > +#endif
> >  };
> >
> >  static __init int ipmmu_init(struct dt_device_node *node, const void *=
data)
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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Feedback-ID: i1568416f:Fastmail
Date: Tue, 26 Aug 2025 15:55:05 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Jan Beulich ,
	xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart
Message-ID: 
References: 
 <2aafbace-3aa2-4f58-8f6c-2815cd2315ad@suse.com>
 
 
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Date: Tue, 26 Aug 2025 15:55:05 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Jan Beulich ,
	xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart

On Tue, Aug 26, 2025 at 12:57:50PM +0200, Marek Marczykowski-G=C3=B3recki w=
rote:
> On Tue, Aug 26, 2025 at 10:28:56AM +0200, Roger Pau Monn=C3=A9 wrote:
> > On Tue, Aug 26, 2025 at 08:16:56AM +0200, Jan Beulich wrote:
> > > On 26.08.2025 03:49, Marek Marczykowski-G=C3=B3recki wrote:
> > > > Hi,
> > > >=20
> > > > I'm hitting an MSI-X issue after rebooting the domU. The symptoms a=
re
> > > > rather boring: on initial domU start the device (realtek eth card) =
works
> > > > fine, but after domU restart, the link doesn't come up (there is no
> > > > "Link is Up" message anymore). No errors from domU driver or Xen. I
> > > > tracked it down to MSI-X - if I force INTx (via pci=3Dnomsi on domU
> > > > cmdline) it works fine. Convincing the driver to poll instead of wa=
iting
> > > > for an interrupt also workarounds the issue.
> > > >=20
> > > > I noticed also some interrupts are not cleaned up on restart. The l=
ist
> > > > of MSIs in 'Q' debug key output grows:
> > > >=20
> > > >     (XEN) 0000:03:00.0 - d22 - node -1  - MSIs < 41 42 43 44 45 46 =
47 >
> > > >     restart sys-net domU
> > > >     (XEN) 0000:03:00.0 - d24 - node -1  - MSIs < 41 42 43 44 45 46 =
47 48 >
> > > >     restart sys-net domU
> > > >     (XEN) 0000:03:00.0 - d26 - node -1  - MSIs < 41 42 43 44 45 46 =
47 48 49 >
> > > >=20
> > > > and 'M' output is:
> > > >=20
> > > >     (XEN)  MSI-X   41 vec=3Db1 lowest  edge   assert  log lowest de=
st=3D00000001 mask=3D1/H /1
> > > >     (XEN)  MSI-X   42 vec=3Db9 lowest  edge   assert  log lowest de=
st=3D00000004 mask=3D1/HG/1
> > > >     (XEN)  MSI-X   43 vec=3Dc1 lowest  edge   assert  log lowest de=
st=3D00000010 mask=3D1/HG/1
> > > >     (XEN)  MSI-X   44 vec=3Dd9 lowest  edge   assert  log lowest de=
st=3D00000001 mask=3D1/HG/1
> > > >     (XEN)  MSI-X   45 vec=3De1 lowest  edge   assert  log lowest de=
st=3D00000001 mask=3D1/HG/1
> > > >     (XEN)  MSI-X   46 vec=3De9 lowest  edge   assert  log lowest de=
st=3D00000040 mask=3D1/HG/1
> > > >     (XEN)  MSI-X   47 vec=3D32 lowest  edge   assert  log lowest de=
st=3D00000004 mask=3D1/HG/1
> > > >     (XEN)  MSI-X   48 vec=3D3a lowest  edge   assert  log lowest de=
st=3D00000040 mask=3D1/HG/1
> > > >     (XEN)  MSI-X   49 vec=3D42 lowest  edge   assert  log lowest de=
st=3D00000010 mask=3D1/ G/1
> > > >=20
> > > > And also, after starting and stopping the domU, `xl pci-assignable-=
remove 03:00.0`
> > > > makes pciback to complain:
> > > >=20
> > > >     [ 1180.919874] pciback 0000:03:00.0: xen_pciback: MSI-X release=
 failed (-16)
> > > >=20
> > > > This is all running on Xen 4.19.3, but I don't see much changes in =
this
> > > > area since then.
> > > >=20
> > > > Some more info collected at https://github.com/QubesOS/qubes-issues=
/issues/9335
> > > >=20
> > > > My question is: what should be responsible for this cleanup on doma=
in
> > > > destroy? Xen, or maybe device model (which is QEMU in stubdomain he=
re)?
> > >=20
> > > The expectation is that qemu invokes the necessary cleanup, but of co=
urse ...
> > >=20
> > > > I see some cleanup (apparently not enough) happening via QEMU when =
the
> > > > domU driver is unloaded, but logically correct cleanup shouldn't de=
pend
> > > > on correct domU operation...
> > >=20
> > > ... Xen may not make itself dependent upon either DomU or QEMU.
> >=20
> > AFAICT free_domain_pirqs() called by arch_domain_destroy() should take
> > care of unbinding and freeing pirqs (but obviously not in this case).
> > Can you repeat the test with a debug=3Dy hypervisor and post the
> > resulting serial or dmesg here?  Some of the errors on those paths are
> > printed with dprintk() and won't be visible unless using a Xen debug
> > build.
>=20
> Sure, will do.

Output collected during domU shutdown and subsequent startup (dom0 logs
to Xen console here too):
https://gist.github.com/marmarek/6dc3ac14d3ba840482e6361fcbd37c30

I don't see any errors there...

As for the domU-triggered cleanup, I just checked - if I unload the
driver in domU before restarting, it works fine on subsequent startup.

Relevant QEMU/stubdomain log parts (initial startup + shutdown, when
device still works):

1. Without unloading the driver:

[2025-08-26 12:57:42] [00:06.0] xen_pt_realize: Assigning real physical dev=
ice 03:00.0 to devfn 0x30
[2025-08-26 12:57:42] [00:06.0] xen_pt_register_regions: IO region 0 regist=
ered (size=3D0x00000100 base_addr=3D0x0000e000 type: 0x1)
[2025-08-26 12:57:42] [00:06.0] xen_pt_register_regions: IO region 2 regist=
ered (size=3D0x00001000 base_addr=3D0xf7c00000 type: 0x4)
[2025-08-26 12:57:42] [00:06.0] xen_pt_register_regions: IO region 4 regist=
ered (size=3D0x00004000 base_addr=3D0xf0000000 type: 0x4)
[2025-08-26 12:57:42] [00:06.0] xen_pt_config_reg_init: Offset 0x0010 misma=
tch! Emulated=3D0x0000, host=3D0xe001, syncing to 0xe001.
[2025-08-26 12:57:42] [00:06.0] xen_pt_config_reg_init: Offset 0x0018 misma=
tch! Emulated=3D0x0000, host=3D0xf7c00004, syncing to 0xf7c00004.
[2025-08-26 12:57:42] [00:06.0] xen_pt_config_reg_init: Offset 0x0020 misma=
tch! Emulated=3D0x0000, host=3D0xf000000c, syncing to 0xf000000c.
[2025-08-26 12:57:42] [00:06.0] xen_pt_config_reg_init: Offset 0x0042 misma=
tch! Emulated=3D0x0000, host=3D0x07c3, syncing to 0x0603.
[2025-08-26 12:57:42] [00:06.0] xen_pt_pm_ctrl_reg_init_on: PCI power manag=
ement control passthrough is on
[2025-08-26 12:57:42] [00:06.0] xen_pt_config_reg_init: Offset 0x0052 misma=
tch! Emulated=3D0x0000, host=3D0x0080, syncing to 0x0080.
[2025-08-26 12:57:42] [00:06.0] xen_pt_config_reg_init: Offset 0x0074 misma=
tch! Emulated=3D0x0000, host=3D0x5908cc0, syncing to 0x5908cc0.
[2025-08-26 12:57:42] [00:06.0] xen_pt_config_reg_init: Offset 0x007a misma=
tch! Emulated=3D0x0000, host=3D0x0010, syncing to 0x0010.
[2025-08-26 12:57:42] [00:06.0] xen_pt_config_reg_init: Offset 0x0082 misma=
tch! Emulated=3D0x0000, host=3D0x1011, syncing to 0x1011.
[2025-08-26 12:57:42] [00:06.0] xen_pt_msix_init: get MSI-X table BAR base =
0xf0000000
[2025-08-26 12:57:42] [00:06.0] xen_pt_config_reg_init: Offset 0x00b2 misma=
tch! Emulated=3D0x0000, host=3D0x0003, syncing to 0x0003.
[2025-08-26 12:57:42] [00:06.0] xen_pt_pci_intx: intx=3D1
[2025-08-26 12:57:42] [00:06.0] xen_pt_realize: Real physical device 03:00.=
0 registered successfully
[2025-08-26 12:57:42] from-unix: {"return": {}, "id": 2020372736}
[2025-08-26 12:57:42]=20
[2025-08-26 12:57:42] wrote 34 bytes to vchan
[2025-08-26 12:57:42] from-vchan: {"execute":"query-pci","id":2020372738}
[2025-08-26 12:57:42]=20
[2025-08-26 12:57:42] from-unix: {"return": [{"bus": 0, "devices": [{"irq_p=
in": 0, "bus": 0, "qdev_id": "", "slot": 0, "class_info": {"class": 1536, "=
desc": "Host bridge"}, "id": {"device": 4663, "subsystem-vendor": 6900, "ve=
ndor": 32902, "subsystem": 4352}, "function": 0, "regions": []}, {"irq_pin"=
: 0, "bus": 0, "qdev_id": "", "slot": 1, "class_info": {"class": 1537, "des=
c": "ISA bridge"}, "id": {"device": 28672, "subsystem-vendor": 6900, "vendo=
r": 32902, "subsystem": 4352}, "function": 0, "regions": []}, {"irq_pin": 0=
, "bus": 0, "qdev_id": "", "slot": 1, "class_info": {"class": 257, "desc": =
"IDE controller"}, "id": {"device": 28688, "subsystem-vendor": 6900, "vendo=
r": 32902, "subsystem": 4352}, "function": 1, "regions": [{"bar": 4, "size"=
: 16, "address": -1, "type": "io"}]}, {"irq_pin": 1, "bus": 0, "qdev_id": "=
", "irq": 0, "slot": 1, "class_info": {"class": 1664, "desc": "Bridge"}, "i=
d": {"device": 28947, "subsystem-vendor": 6900, "vendor": 32902, "subsystem=
": 4352}, "function": 3, "regions": []}, {"irq_pin": 1, "bus": 0, "qdev_id"=
: "", "irq": 0, "slot": 2, "class_info": {"class": 65408}, "id": {"device":=
 1, "subsystem-vendor": 22611, "vendor": 22611, "subsystem": 1}, "function"=
: 0, "regions": [{"bar": 0, "size": 256, "address": -1, "type": "io"}, {"pr=
efetch": true, "mem_type_64": false, "bar": 1, "size": 16777216, "address":=
 -1, "type": "memory"}]}, {"irq_pin": 1, "bus": 0, "qdev_id": "", "irq": 0,=
 "slot": 3, "class_info": {"class": 256, "desc": "SCSI controller"}, "id": =
{"device": 18, "subsystem-vendor": 0, "vendor": 4096, "subsystem": 4096}, "=
function": 0, "regions": [{"bar": 0, "size": 256, "address": -1, "type": "i=
o"}, {"prefetch": false, "mem_type_64": false, "bar": 1, "size": 1024, "add=
ress": -1, "type": "memory"}, {"prefetch": false, "mem_type_64": false, "ba=
r": 2, "size": 8192, "address": -1, "type": "memory"}]}, {"irq_pin": 0, "bu=
s": 0, "qdev_id": "", "slot": 4, "class_info": {"class": 768, "desc": "VGA =
controller"}, "id": {"device": 4369, "subsystem-vendor": 6900, "vendor": 46=
60, "subsystem": 4352}, "function": 0, "regions": [{"prefetch": true, "mem_=
type_64": false, "bar": 0, "size": 16777216, "address": -1, "type": "memory=
"}, {"prefetch": false, "mem_type_64": false, "bar": 2, "size": 4096, "addr=
ess": -1, "type": "memory"}, {"prefetch": false, "mem_type_64": false, "bar=
": 6, "size": 65536, "address": -1, "type": "memory"}]}, {"irq_pin": 4, "bu=
s": 0, "qdev_id": "ehci", "irq": 0, "slot": 5, "class_info": {"class": 3075=
, "desc": "USB controller"}, "id": {"device": 9421, "subsystem-vendor": 690=
0, "vendor": 32902, "subsystem": 4352}, "function": 0, "regions": [{"prefet=
ch": false, "mem_type_64": false, "bar": 0, "size": 4096, "address": -1, "t=
ype": "memory"}]}, {"irq_pin": 1, "bus": 0, "qdev_id": "pci-pt-03_00.0", "i=
rq": 0, "slot": 6, "class_info": {"class": 0}, "id": {"device": 33128, "sub=
system-vendor": 0, "vendor": 4332, "subsystem": 0}, "function": 0, "regions=
": [{"bar": 0, "size": 256, "address": -1, "type": "io"}, {"prefetch": fals=
e, "mem_type_64": true, "bar": 2, "size": 4096, "address": -1, "type": "mem=
ory"}, {"prefetch": false, "mem_type_64": true, "bar": 4, "size": 16384, "a=
ddress": -1, "type": "memory"}]}]}], "id": 2020372738}
[2025-08-26 12:57:42]=20
[2025-08-26 12:57:42] wrote 2048 bytes to vchan
[2025-08-26 12:57:42] wrote 1125 bytes to vchan
[2025-08-26 12:57:42] vchan client disconnected
[2025-08-26 12:57:42] [00:06.0] xen_pt_check_bar_overlap: Warning: Overlapp=
ed to device [00:02.0] Region: 1 (addr: 0xf0000000, len: 0x1000000)
[2025-08-26 12:57:42] [00:06.0] xen_pt_region_update: Warning: Region: 4 (a=
ddr: 0xf0001000, len: 0x3000) is overlapped.
[2025-08-26 12:57:44] {"timestamp": {"seconds": 1756213064, "microseconds":=
 412107}, "event": "DEVICE_DELETED", "data": {"path": "/machine/unattached/=
device[8]"}}
[2025-08-26 12:57:44] {"timestamp": {"seconds": 1756213064, "microseconds":=
 416176}, "event": "DEVICE_DELETED", "data": {"path": "/machine/unattached/=
device[7]"}}
[2025-08-26 12:57:44] {"timestamp": {"seconds": 1756213064, "microseconds":=
 416244}, "event": "DEVICE_DELETED", "data": {"path": "/machine/unattached/=
device[6]"}}
[2025-08-26 12:57:44] {"timestamp": {"seconds": 1756213064, "microseconds":=
 416653}, "event": "DEVICE_DELETED", "data": {"path": "/machine/peripheral-=
anon/device[3]"}}
[2025-08-26 12:57:44] {"timestamp": {"seconds": 1756213064, "microseconds":=
 416694}, "event": "DEVICE_DELETED", "data": {"path": "/machine/peripheral-=
anon/device[0]"}}
[2025-08-26 12:57:48] [00:06.0] xen_pt_msixctrl_reg_write: enable MSI-X
[2025-08-26 12:57:48] [00:06.0] msi_msix_update: Updating MSI-X with pirq 5=
5 gvec 0xef gflags 0x0 (entry: 0x0)
[2025-08-26 12:57:49] [00:06.0] msi_msix_update: Updating MSI-X with pirq 5=
5 gvec 0x23 gflags 0x0 (entry: 0x0)
[2025-08-26 13:21:03] {"timestamp": {"seconds": 1756214457, "microseconds":=
 588341}, "event": "SHUTDOWN", "data": {"guest": true, "reason": "guest-shu=
tdown"}}
[2025-08-26 13:21:03] {"timestamp": {"seconds": 1756214457, "microseconds":=
 588579}, "event": "STOP"}
[2025-08-26 13:21:03] pcifront pci-0: Rescanning PCI Frontend Bus 0000:00
[2025-08-26 13:21:03] pci_bus 0000:00: busn_res: [bus 00-ff] is released
[2025-08-26 13:21:03] ------------[ cut here ]------------
[2025-08-26 13:21:03] sysfs group 'power' not found for kobject '0000:00'
[2025-08-26 13:21:03] WARNING: CPU: 0 PID: 13 at fs/sysfs/group.c:282 sysfs=
_remove_group+0x3a/0x6f


2. With unloading the driver before shutdown:
[2025-08-26 13:21:07] [00:06.0] xen_pt_realize: Assigning real physical dev=
ice 03:00.0 to devfn 0x30
[2025-08-26 13:21:07] [00:06.0] xen_pt_register_regions: IO region 0 regist=
ered (size=3D0x00000100 base_addr=3D0x0000e000 type: 0x1)
[2025-08-26 13:21:07] [00:06.0] xen_pt_register_regions: IO region 2 regist=
ered (size=3D0x00001000 base_addr=3D0xf7c00000 type: 0x4)
[2025-08-26 13:21:07] [00:06.0] xen_pt_register_regions: IO region 4 regist=
ered (size=3D0x00004000 base_addr=3D0xf0000000 type: 0x4)
[2025-08-26 13:21:07] [00:06.0] xen_pt_config_reg_init: Offset 0x0010 misma=
tch! Emulated=3D0x0000, host=3D0xe001, syncing to 0xe001.
[2025-08-26 13:21:07] [00:06.0] xen_pt_config_reg_init: Offset 0x0018 misma=
tch! Emulated=3D0x0000, host=3D0xf7c00004, syncing to 0xf7c00004.
[2025-08-26 13:21:07] [00:06.0] xen_pt_config_reg_init: Offset 0x0020 misma=
tch! Emulated=3D0x0000, host=3D0xf000000c, syncing to 0xf000000c.
[2025-08-26 13:21:07] [00:06.0] xen_pt_config_reg_init: Offset 0x0042 misma=
tch! Emulated=3D0x0000, host=3D0x07c3, syncing to 0x0603.
[2025-08-26 13:21:07] [00:06.0] xen_pt_pm_ctrl_reg_init_on: PCI power manag=
ement control passthrough is on
[2025-08-26 13:21:07] [00:06.0] xen_pt_config_reg_init: Offset 0x0052 misma=
tch! Emulated=3D0x0000, host=3D0x0080, syncing to 0x0080.
[2025-08-26 13:21:07] [00:06.0] xen_pt_config_reg_init: Offset 0x0074 misma=
tch! Emulated=3D0x0000, host=3D0x5908cc0, syncing to 0x5908cc0.
[2025-08-26 13:21:07] [00:06.0] xen_pt_config_reg_init: Offset 0x007a misma=
tch! Emulated=3D0x0000, host=3D0x0010, syncing to 0x0010.
[2025-08-26 13:21:07] [00:06.0] xen_pt_config_reg_init: Offset 0x0082 misma=
tch! Emulated=3D0x0000, host=3D0x1011, syncing to 0x1011.
[2025-08-26 13:21:07] [00:06.0] xen_pt_msix_init: get MSI-X table BAR base =
0xf0000000
[2025-08-26 13:21:07] [00:06.0] xen_pt_config_reg_init: Offset 0x00b2 misma=
tch! Emulated=3D0x0000, host=3D0x0003, syncing to 0x0003.
[2025-08-26 13:21:07] [00:06.0] xen_pt_pci_intx: intx=3D1
[2025-08-26 13:21:07] [00:06.0] xen_pt_realize: Real physical device 03:00.=
0 registered successfully
[2025-08-26 13:21:07] from-unix: {"return": {}, "id": 2020372736}
[2025-08-26 13:21:07]=20
[2025-08-26 13:21:07] wrote 34 bytes to vchan
[2025-08-26 13:21:07] from-vchan: {"execute":"query-pci","id":2020372738}
[2025-08-26 13:21:07]=20
[2025-08-26 13:21:07] from-unix: {"return": [{"bus": 0, "devices": [{"irq_p=
in": 0, "bus": 0, "qdev_id": "", "slot": 0, "class_info": {"class": 1536, "=
desc": "Host bridge"}, "id": {"device": 4663, "subsystem-vendor": 6900, "ve=
ndor": 32902, "subsystem": 4352}, "function": 0, "regions": []}, {"irq_pin"=
: 0, "bus": 0, "qdev_id": "", "slot": 1, "class_info": {"class": 1537, "des=
c": "ISA bridge"}, "id": {"device": 28672, "subsystem-vendor": 6900, "vendo=
r": 32902, "subsystem": 4352}, "function": 0, "regions": []}, {"irq_pin": 0=
, "bus": 0, "qdev_id": "", "slot": 1, "class_info": {"class": 257, "desc": =
"IDE controller"}, "id": {"device": 28688, "subsystem-vendor": 6900, "vendo=
r": 32902, "subsystem": 4352}, "function": 1, "regions": [{"bar": 4, "size"=
: 16, "address": -1, "type": "io"}]}, {"irq_pin": 1, "bus": 0, "qdev_id": "=
", "irq": 0, "slot": 1, "class_info": {"class": 1664, "desc": "Bridge"}, "i=
d": {"device": 28947, "subsystem-vendor": 6900, "vendor": 32902, "subsystem=
": 4352}, "function": 3, "regions": []}, {"irq_pin": 1, "bus": 0, "qdev_id"=
: "", "irq": 0, "slot": 2, "class_info": {"class": 65408}, "id": {"device":=
 1, "subsystem-vendor": 22611, "vendor": 22611, "subsystem": 1}, "function"=
: 0, "regions": [{"bar": 0, "size": 256, "address": -1, "type": "io"}, {"pr=
efetch": true, "mem_type_64": false, "bar": 1, "size": 16777216, "address":=
 -1, "type": "memory"}]}, {"irq_pin": 1, "bus": 0, "qdev_id": "", "irq": 0,=
 "slot": 3, "class_info": {"class": 256, "desc": "SCSI controller"}, "id": =
{"device": 18, "subsystem-vendor": 0, "vendor": 4096, "subsystem": 4096}, "=
function": 0, "regions": [{"bar": 0, "size": 256, "address": -1, "type": "i=
o"}, {"prefetch": false, "mem_type_64": false, "bar": 1, "size": 1024, "add=
ress": -1, "type": "memory"}, {"prefetch": false, "mem_type_64": false, "ba=
r": 2, "size": 8192, "address": -1, "type": "memory"}]}, {"irq_pin": 0, "bu=
s": 0, "qdev_id": "", "slot": 4, "class_info": {"class": 768, "desc": "VGA =
controller"}, "id": {"device": 4369, "subsystem-vendor": 6900, "vendor": 46=
60, "subsystem": 4352}, "function": 0, "regions": [{"prefetch": true, "mem_=
type_64": false, "bar": 0, "size": 16777216, "address": -1, "type": "memory=
"}, {"prefetch": false, "mem_type_64": false, "bar": 2, "size": 4096, "addr=
ess": -1, "type": "memory"}, {"prefetch": false, "mem_type_64": false, "bar=
": 6, "size": 65536, "address": -1, "type": "memory"}]}, {"irq_pin": 4, "bu=
s": 0, "qdev_id": "ehci", "irq": 0, "slot": 5, "class_info": {"class": 3075=
, "desc": "USB controller"}, "id": {"device": 9421, "subsystem-vendor": 690=
0, "vendor": 32902, "subsystem": 4352}, "function": 0, "regions": [{"prefet=
ch": false, "mem_type_64": false, "bar": 0, "size": 4096, "address": -1, "t=
ype": "memory"}]}, {"irq_pin": 1, "bus": 0, "qdev_id": "pci-pt-03_00.0", "i=
rq": 0, "slot": 6, "class_info": {"class": 0}, "id": {"device": 33128, "sub=
system-vendor": 0, "vendor": 4332, "subsystem": 0}, "function": 0, "regions=
": [{"bar": 0, "size": 256, "address": -1, "type": "io"}, {"prefetch": fals=
e, "mem_type_64": true, "bar": 2, "size": 4096, "address": -1, "type": "mem=
ory"}, {"prefetch": false, "mem_type_64": true, "bar": 4, "size": 16384, "a=
ddress": -1, "type": "memory"}]}]}], "id": 2020372738}
[2025-08-26 13:21:07]=20
[2025-08-26 13:21:07] wrote 2048 bytes to vchan
[2025-08-26 13:21:07] wrote 1125 bytes to vchan
[2025-08-26 13:21:07] vchan client disconnected
[2025-08-26 13:21:07] [00:06.0] xen_pt_check_bar_overlap: Warning: Overlapp=
ed to device [00:02.0] Region: 1 (addr: 0xf0000000, len: 0x1000000)
[2025-08-26 13:21:07] [00:06.0] xen_pt_region_update: Warning: Region: 4 (a=
ddr: 0xf0001000, len: 0x3000) is overlapped.
[2025-08-26 13:21:09] {"timestamp": {"seconds": 1756214469, "microseconds":=
 28994}, "event": "DEVICE_DELETED", "data": {"path": "/machine/unattached/d=
evice[8]"}}
[2025-08-26 13:21:09] {"timestamp": {"seconds": 1756214469, "microseconds":=
 32958}, "event": "DEVICE_DELETED", "data": {"path": "/machine/unattached/d=
evice[7]"}}
[2025-08-26 13:21:09] {"timestamp": {"seconds": 1756214469, "microseconds":=
 33004}, "event": "DEVICE_DELETED", "data": {"path": "/machine/unattached/d=
evice[6]"}}
[2025-08-26 13:21:09] {"timestamp": {"seconds": 1756214469, "microseconds":=
 33261}, "event": "DEVICE_DELETED", "data": {"path": "/machine/peripheral-a=
non/device[3]"}}
[2025-08-26 13:21:09] {"timestamp": {"seconds": 1756214469, "microseconds":=
 33296}, "event": "DEVICE_DELETED", "data": {"path": "/machine/peripheral-a=
non/device[0]"}}
[2025-08-26 13:21:12] [00:06.0] xen_pt_msixctrl_reg_write: enable MSI-X
[2025-08-26 13:21:12] [00:06.0] msi_msix_update: Updating MSI-X with pirq 5=
5 gvec 0xef gflags 0x0 (entry: 0x0)
[2025-08-26 13:21:13] [00:06.0] msi_msix_update: Updating MSI-X with pirq 5=
5 gvec 0x23 gflags 0x0 (entry: 0x0)
[2025-08-26 13:41:45] [00:06.0] msix_set_enable: disabling MSI-X.
[2025-08-26 13:41:45] [00:06.0] msi_msix_disable: Unbind MSI-X with pirq 55=
, gvec 0x23
[2025-08-26 13:41:45] [00:06.0] msi_msix_disable: Unmap MSI-X pirq 55
[2025-08-26 13:41:45] [00:06.0] xen_pt_msixctrl_reg_write: disable MSI-X
{"timestamp": {"seconds": 1756215718, "microseconds": 455554}, "event": "SH=
UTDOWN", "data": {"guest": true, "reason": "guest-shutdown"}}
[2025-08-26 13:41:58] {"timestamp": {"seconds": 1756215718, "microseconds":=
 456438}, "event": "STOP"}
[2025-08-26 13:41:58] pcifront pci-0: Rescanning PCI Frontend Bus 0000:00
[2025-08-26 13:41:58] pci_bus 0000:00: busn_res: [bus 00-ff] is released
[2025-08-26 13:41:58] ------------[ cut here ]------------
[2025-08-26 13:41:58] sysfs group 'power' not found for kobject '0000:00'
[2025-08-26 13:41:58] WARNING: CPU: 0 PID: 13 at fs/sysfs/group.c:282 sysfs=
_remove_group+0x3a/0x6f



--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

--SPDx3WFh/ytkDTPC
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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v3 06/11] xen/arm/irq: allow eSPI processing in the do_IRQ
 function
Thread-Topic: [PATCH v3 06/11] xen/arm/irq: allow eSPI processing in the
 do_IRQ function
Thread-Index: AQHcFpJ/78TDbVIRnkOE9iNbqduJVA==
Date: Tue, 26 Aug 2025 14:05:37 +0000
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The do_IRQ() function is the main handler for processing IRQs.
Currently, due to restrictive checks, it does not process interrupt
numbers greater than 1024. This patch updates the condition to allow
the handling of interrupts from the eSPI range.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- no changes

Changes in V3:
- no changes
---
 xen/arch/arm/gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index b88237ccda..634b77c987 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -341,7 +341,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_f=
iq)
         /* Reading IRQ will ACK it */
         irq =3D gic_hw_ops->read_irq();
=20
-        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) )
+        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) || is_espi(=
irq) )
         {
             isb();
             do_IRQ(regs, irq, is_fiq);
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1 eSPI
Thread-Topic: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcFpJ/0RYrIev2JkmWYheOK3kVZw==
Date: Tue, 26 Aug 2025 14:05:37 +0000
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 <398ad09617f4f97d57d13fa9f3771bd2db83916b.1756216943.git.leonid_komarianskyi@epam.com>
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Introduced appropriate register definitions, helper macros,
and initialization of required GICv3.1 distributor registers
to support eSPI. This type of interrupt is handled in the
same way as regular SPI interrupts, with the following
differences:

1) eSPIs can have up to 1024 interrupts, starting from the
beginning of the range, whereas regular SPIs use INTIDs from
32 to 1019, totaling 988 interrupts;
2) eSPIs start at INTID 4096, necessitating additional interrupt
index conversion during register operations.

In case if appropriate config is disabled, or GIC HW doesn't
support eSPI, the existing functionality will remain the same.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- move gic_number_espis function from
  [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
  to use it in the newly introduced gic_is_valid_espi
- add gic_is_valid_espi which checks if IRQ number is in supported
  by HW eSPI range
- update gic_is_valid_irq conditions to allow operations with eSPIs

Changes in V3:
- add __init attribute to gicv3_dist_espi_common_init
- change open-codded eSPI register initialization to the appropriate
  gen-mask macro
- fixed formatting for lines with more than 80 symbols
- introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
  CONFIG_GICV3_ESPI disabled
- renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
  (name was taken from GIC specification) to avoid confusion
- changed type for i variable to unsigned int since it cannot be
  negative
---
 xen/arch/arm/gic-v3.c                  | 80 ++++++++++++++++++++++++++
 xen/arch/arm/include/asm/gic.h         | 21 +++++++
 xen/arch/arm/include/asm/gic_v3_defs.h | 34 +++++++++++
 3 files changed, 135 insertions(+)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index a959fefebe..3aa5cc1765 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_des=
c *irqd, u32 offset)
         default:
             break;
         }
+#ifdef CONFIG_GICV3_ESPI
+    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
+    {
+        u32 irq_index =3D ESPI_INTID2IDX(irqd->irq);
+
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
+        case GICD_ICENABLER:
+            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
+        case GICD_ISPENDR:
+            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
+        case GICD_ICPENDR:
+            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
+        case GICD_ISACTIVER:
+            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
+        case GICD_ICACTIVER:
+            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
+        case GICD_ICFGR:
+            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
+        case GICD_IROUTER:
+            return (GICD + GICD_IROUTERnE + irq_index * 8);
+        case GICD_IPRIORITYR:
+            return (GICD + GICD_IPRIORITYRnE + irq_index);
+        default:
+            break;
+        }
+    }
+#endif
     default:
         break;
     }
@@ -655,6 +685,52 @@ static void gicv3_set_irq_priority(struct irq_desc *de=
sc,
     spin_unlock(&gicv3.lock);
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+unsigned int gic_number_espis(void)
+{
+    return gic_hw_ops->info->nr_espi;
+}
+
+static void __init gicv3_dist_espi_common_init(uint32_t type)
+{
+    unsigned int espi_nr, i;
+
+    espi_nr =3D min(1024U, GICD_TYPER_ESPIS_NUM(type));
+    gicv3_info.nr_espi =3D espi_nr;
+    /* The GIC HW doesn't support eSPI, so we can leave from here */
+    if ( gicv3_info.nr_espi =3D=3D 0 )
+        return;
+
+    for ( i =3D 0; i < espi_nr; i +=3D 16 )
+        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
+
+    for ( i =3D 0; i < espi_nr; i +=3D 4 )
+        writel_relaxed(GIC_PRI_IRQ_ALL,
+                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
+
+    for ( i =3D 0; i < espi_nr; i +=3D 32 )
+    {
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i / 32) =
* 4);
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i / 32) =
* 4);
+    }
+
+    for ( i =3D 0; i < espi_nr; i +=3D 32 )
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) * =
4);
+}
+
+static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
+{
+    unsigned int i;
+
+    for ( i =3D 0; i < gicv3_info.nr_espi; i++ )
+        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * 8)=
;
+}
+#else
+static void __init gicv3_dist_espi_common_init(uint32_t type) { }
+
+static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
+#endif
+
 static void __init gicv3_dist_init(void)
 {
     uint32_t type;
@@ -700,6 +776,8 @@ static void __init gicv3_dist_init(void)
     for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i +=3D 32 )
         writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4)=
;
=20
+    gicv3_dist_espi_common_init(type);
+
     gicv3_dist_wait_for_rwp();
=20
     /* Turn on the distributor */
@@ -713,6 +791,8 @@ static void __init gicv3_dist_init(void)
=20
     for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
         writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8);
+
+    gicv3_dist_espi_init_aff(affinity);
 }
=20
 static int gicv3_enable_redist(void)
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.=
h
index c7e3b4ff0d..3f1269f0c8 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -306,8 +306,25 @@ extern void gic_dump_vgic_info(struct vcpu *v);
=20
 /* Number of interrupt lines */
 extern unsigned int gic_number_lines(void);
+#ifdef CONFIG_GICV3_ESPI
+extern unsigned int gic_number_espis(void);
+
+static inline bool gic_is_valid_espi(unsigned int irq)
+{
+    return (irq >=3D ESPI_BASE_INTID &&
+            irq < ESPI_IDX2INTID(gic_number_espis()));
+}
+#else
+static inline bool gic_is_valid_espi(unsigned int irq)
+{
+    return false;
+}
+#endif
 static inline bool gic_is_valid_line(unsigned int irq)
 {
+    if ( gic_is_valid_espi(irq) )
+        return true;
+
     return irq < gic_number_lines();
 }
=20
@@ -325,6 +342,10 @@ struct gic_info {
     enum gic_version hw_version;
     /* Number of GIC lines supported */
     unsigned int nr_lines;
+#ifdef CONFIG_GICV3_ESPI
+    /* Number of GIC eSPI supported */
+    unsigned int nr_espi;
+#endif
     /* Number of LR registers */
     uint8_t nr_lrs;
     /* Maintenance irq number */
diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/=
asm/gic_v3_defs.h
index 2af093e774..d38a3d08c7 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -37,6 +37,40 @@
 #define GICD_IROUTER1019             (0x7FD8)
 #define GICD_PIDR2                   (0xFFE8)
=20
+#ifdef CONFIG_GICV3_ESPI
+/* Additional registers for GICv3.1 */
+#define GICD_IGROUPRnE               (0x1000)
+#define GICD_IGROUPRnEN              (0x107C)
+#define GICD_ISENABLERnE             (0x1200)
+#define GICD_ISENABLERnEN            (0x127C)
+#define GICD_ICENABLERnE             (0x1400)
+#define GICD_ICENABLERnEN            (0x147C)
+#define GICD_ISPENDRnE               (0x1600)
+#define GICD_ISPENDRnEN              (0x167C)
+#define GICD_ICPENDRnE               (0x1800)
+#define GICD_ICPENDRnEN              (0x187C)
+#define GICD_ISACTIVERnE             (0x1A00)
+#define GICD_ISACTIVERnEN            (0x1A7C)
+#define GICD_ICACTIVERnE             (0x1C00)
+#define GICD_ICACTIVERnEN            (0x1C7C)
+#define GICD_IPRIORITYRnE            (0x2000)
+#define GICD_IPRIORITYRnEN           (0x23FC)
+#define GICD_ICFGRnE                 (0x3000)
+#define GICD_ICFGRnEN                (0x30FC)
+#define GICD_IROUTERnE               (0x8000)
+#define GICD_IROUTERnEN              (0x9FFC)
+
+#define GICD_TYPER_ESPI_SHIFT        8
+#define GICD_TYPER_ESPI_RANGE_SHIFT  27
+#define GICD_TYPER_ESPI_RANGE_MASK   (0x1F)
+#define GICD_TYPER_ESPI              (1U << GICD_TYPER_ESPI_SHIFT)
+#define GICD_TYPER_ESPI_RANGE(espi_range) ((((espi_range) & \
+        GICD_TYPER_ESPI_RANGE_MASK) + 1) * 32)
+#define GICD_TYPER_ESPIS_NUM(typer)    \
+        (((typer) & GICD_TYPER_ESPI) ? \
+        GICD_TYPER_ESPI_RANGE((typer) >> GICD_TYPER_ESPI_RANGE_SHIFT) : 0)
+#endif
+
 /* Common between GICD_PIDR2 and GICR_PIDR2 */
 #define GIC_PIDR2_ARCH_MASK         (0xf0)
 #define GIC_PIDR2_ARCH_GICv3        (0x30)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v3 04/11] xen/arm/irq: add handling for IRQs in the eSPI range
Thread-Topic: [PATCH v3 04/11] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcFpJ/t39ssss6a0y8SPAQeD5PEA==
Date: Tue, 26 Aug 2025 14:05:37 +0000
Message-ID:
 <8b42416d779537d6a0ac4902cabc549253b9da9d.1756216943.git.leonid_komarianskyi@epam.com>
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Currently, Xen does not support eSPI interrupts, leading
to a data abort when such interrupts are defined in the DTS.

This patch introduces a separate array to initialize up to
1024 interrupt descriptors in the eSPI range and adds the
necessary defines and helper function. These changes lay the
groundwork for future implementation of full eSPI interrupt
support. As this GICv3.1 feature is not required by all vendors,
all changes are guarded by ifdefs, depending on the corresponding
Kconfig option.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
- remove unnecessary comment for nr_irqs initialization

Changes in V3:
- introduced a new define NR_ESPI_IRQS to avoid confusion, like in the
  case of using NR_IRQS for espi_desc array
- implemented helper functions espi_to_desc and init_espi_data to make
  it possible to add stubs with the same name, and as a result, reduce
  the number of #ifdefs
- change CONFIG_GICV3_ESPI default value to n
---
 xen/arch/arm/Kconfig           |  9 ++++++
 xen/arch/arm/include/asm/irq.h | 26 +++++++++++++++++
 xen/arch/arm/irq.c             | 52 +++++++++++++++++++++++++++++++++-
 3 files changed, 86 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 17df147b25..5813e5b267 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -135,6 +135,15 @@ config GICV3
 	  Driver for the ARM Generic Interrupt Controller v3.
 	  If unsure, use the default setting.
=20
+config GICV3_ESPI
+	bool "Extended SPI range support"
+	depends on GICV3 && !NEW_VGIC
+	default n
+	help
+	  Allow Xen and domains to use interrupt numbers from the extended SPI
+	  range, from 4096 to 5119. This feature is introduced in GICv3.1
+	  architecture.
+
 config HAS_ITS
         bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORT=
ED
         depends on GICV3 && !NEW_VGIC && !ARM_32
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.=
h
index 5bc6475eb4..221dbf23a2 100644
--- a/xen/arch/arm/include/asm/irq.h
+++ b/xen/arch/arm/include/asm/irq.h
@@ -32,6 +32,15 @@ struct arch_irq_desc {
 #define SPI_MAX_INTID   1019
 #define LPI_OFFSET      8192
=20
+#ifdef CONFIG_GICV3_ESPI
+#define ESPI_BASE_INTID 4096
+#define ESPI_MAX_INTID  5119
+#define NR_ESPI_IRQS    1024
+
+#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
+#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
+#endif
+
 /* LPIs are always numbered starting at 8192, so 0 is a good invalid case.=
 */
 #define INVALID_LPI     0
=20
@@ -39,7 +48,15 @@ struct arch_irq_desc {
 #define INVALID_IRQ     1023
=20
 extern const unsigned int nr_irqs;
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * This will also cover the eSPI range, as some critical devices
+ * for booting Xen (e.g., serial) may use this type of interrupts.
+ */
+#define nr_static_irqs (ESPI_MAX_INTID + 1)
+#else
 #define nr_static_irqs NR_IRQS
+#endif
=20
 struct irq_desc;
 struct irqaction;
@@ -55,6 +72,15 @@ static inline bool is_lpi(unsigned int irq)
     return irq >=3D LPI_OFFSET;
 }
=20
+static inline bool is_espi(unsigned int irq)
+{
+#ifdef CONFIG_GICV3_ESPI
+    return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID);
+#else
+    return false;
+#endif
+}
+
 #define domain_pirq_to_irq(d, pirq) (pirq)
=20
 bool is_assignable_irq(unsigned int irq);
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index b8eccfc924..adb5e49ea3 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -19,7 +19,11 @@
 #include 
 #include 
=20
+#ifdef CONFIG_GICV3_ESPI
+const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1;
+#else
 const unsigned int nr_irqs =3D NR_IRQS;
+#endif
=20
 static unsigned int local_irqs_type[NR_LOCAL_IRQS];
 static DEFINE_SPINLOCK(local_irqs_type_lock);
@@ -46,6 +50,49 @@ void irq_end_none(struct irq_desc *irq)
 }
=20
 static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
+#ifdef CONFIG_GICV3_ESPI
+static irq_desc_t espi_desc[NR_ESPI_IRQS];
+
+static struct irq_desc *espi_to_desc(unsigned int irq)
+{
+    return &espi_desc[ESPI_INTID2IDX(irq)];
+}
+
+static int __init init_espi_data(void)
+{
+    int irq;
+
+    for ( irq =3D ESPI_BASE_INTID; irq <=3D ESPI_MAX_INTID; irq++ )
+    {
+        struct irq_desc *desc =3D irq_to_desc(irq);
+        int rc =3D init_one_irq_desc(desc);
+
+        if ( rc )
+            return rc;
+
+        desc->irq =3D irq;
+        desc->action  =3D NULL;
+    }
+
+    return 0;
+}
+#else
+/*
+ * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn,
+ * because in this case, is_espi will always return false.
+ */
+static struct irq_desc *espi_to_desc(unsigned int irq)
+{
+    ASSERT_UNREACHABLE();
+    return NULL;
+}
+
+static int __init init_espi_data(void)
+{
+    return 0;
+}
+#endif
+
 static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc);
=20
 struct irq_desc *__irq_to_desc(unsigned int irq)
@@ -53,6 +100,9 @@ struct irq_desc *__irq_to_desc(unsigned int irq)
     if ( irq < NR_LOCAL_IRQS )
         return &this_cpu(local_irq_desc)[irq];
=20
+    if ( is_espi(irq) )
+        return espi_to_desc(irq);
+
     return &irq_desc[irq-NR_LOCAL_IRQS];
 }
=20
@@ -79,7 +129,7 @@ static int __init init_irq_data(void)
         desc->action  =3D NULL;
     }
=20
-    return 0;
+    return init_espi_data();
 }
=20
 static int init_local_irq_data(unsigned int cpu)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v3 02/11] xen/arm: gic: implement helper functions for INTID
 checks
Thread-Topic: [PATCH v3 02/11] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Index: AQHcFpJ/l4cyfmMsSUSuASmV+4e1mw==
Date: Tue, 26 Aug 2025 14:05:36 +0000
Message-ID:
 <4a865061abcfe626ffb8c134fe2353fb5675dc86.1756216943.git.leonid_komarianskyi@epam.com>
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Introduced two new helper functions: gic_is_valid_line and
gic_is_spi. The first function helps determine whether an IRQ
number is less than the number of lines supported by hardware. The
second function additionally checks if the IRQ number falls within the
SPI range. Also, updated the appropriate checks to use these new helper
functions.

The current checks for the real GIC are very similar to those for the
vGIC but serve a different purpose. For GIC-related code, the interrupt
numbers should be validated based on whether the hardware can operate
with such interrupts. On the other hand, for the vGIC, the indexes must
also be verified to ensure they are available for a specific domain. The
first reason for introducing these helper functions is to avoid
potential confusion with vGIC-related checks. The second reason is to
consolidate similar code into separate functions, which can be more
easily extended by additional conditions, e.g., when implementing
extended SPI interrupts.

The changes, which replace open-coded checks with the use of the new
helper functions, do not introduce any functional changes, as the helper
functions follow the current IRQ index verification logic.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- introduced this patch

Changes in V3:
- renamed gic_is_valid_irq to gic_is_valid_line and gic_is_shared_irq to
  gic_is_spi
- updated commit message
---
 xen/arch/arm/gic.c             | 2 +-
 xen/arch/arm/include/asm/gic.h | 9 +++++++++
 xen/arch/arm/irq.c             | 2 +-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index e80fe0ca24..9220eef6ea 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -111,7 +111,7 @@ static void gic_set_irq_priority(struct irq_desc *desc,=
 unsigned int priority)
 void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority)
 {
     ASSERT(priority <=3D 0xff);     /* Only 8 bits of priority */
-    ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that =
don't exist */
+    ASSERT(gic_is_valid_line(desc->irq));/* Can't route interrupts that do=
n't exist */
     ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
     ASSERT(spin_is_locked(&desc->lock));
=20
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.=
h
index 541f0eeb80..c7e3b4ff0d 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -306,6 +306,15 @@ extern void gic_dump_vgic_info(struct vcpu *v);
=20
 /* Number of interrupt lines */
 extern unsigned int gic_number_lines(void);
+static inline bool gic_is_valid_line(unsigned int irq)
+{
+    return irq < gic_number_lines();
+}
+
+static inline bool gic_is_spi(unsigned int irq)
+{
+    return (irq >=3D NR_LOCAL_IRQS && gic_is_valid_line(irq));
+}
=20
 /* IRQ translation function for the device tree */
 int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 03fbb90c6c..7dd5a2a453 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -415,7 +415,7 @@ err:
 bool is_assignable_irq(unsigned int irq)
 {
     /* For now, we can only route SPIs to the guest */
-    return (irq >=3D NR_LOCAL_IRQS) && (irq < gic_number_lines());
+    return gic_is_spi(irq);
 }
=20
 /*
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v3 00/11] Subject: [PATCH v3 00/11] Introduce eSPI support
Thread-Topic: [PATCH v3 00/11] Subject: [PATCH v3 00/11] Introduce eSPI
 support
Thread-Index: AQHcFpJ+lDNT/UIVbEmkb1HdVv/B7Q==
Date: Tue, 26 Aug 2025 14:05:35 +0000
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Hello everyone!

Dear Julien and Volodymyr,

Thank you for your review and suggestions in V2.

Following our discussion about memory overhead when eSPI support is
enabled by default, I have changed the default value to 'n' in Kconfig.
Since implementing dynamic allocation for the IRQ descriptors array may
require more time, I decided to go with this solution for now and plan
to prepare the next patch series with dynamic allocation later.

Additionally, I have added stubs for non-eSPI builds where possible and
reorganized some code to reduce the number of #ifdefs.

Dear Oleksandr,

First of all, thank you for your review and for verifying the build on
the dom0less setup. I rechecked the dom0less code and added the
necessary changes to support eSPI in these setups as well.

I also want to mention that I verified the build with Dom0 and DomUs and
checked eSPI functionality on real hardware (e.g., passthrough devices,
changing IRQ affinity in DomU, etc.). Everything works as expected for
devices with eSPIs and regular SPIs. Unfortunately, I don't have setup
with Dom0less + eSPI to check it quickly, but Oleksandr has confirmed
that at least regular SPIs work fine with and without eSPI enabled on a
non-eSPI Dom0less setup (with V2):

> I have lightly re-checked the simple Arm64 Xen environment (dom0less=20
> DomU under QEMU) with your series applied. To be clear, I did not really=
=20
> test the eSPI support (the underlying GICv3 HW does support it); I just=20
> wanted to ensure that your series would not break anything. So, in both=20
> cases (CONFIG_GICV3_ESPI=3Dy and CONFIG_GICV3_ESPI=3Dn), I did not notice=
=20
> any issues (at least obvious) related to GICv3 emulation and SPI=20
> injection for the passed-through device.

Summarized description:
This patch series adds support for the extended shared peripheral
interrupt (eSPI) range (INTIDs 4096-5119 [2](ranges of INTIDs)) for Xen
and guest domains. The implementation uses a generic approach to handle
eSPIs, similar to regular SPIs, while maintaining compatibility with the
existing SPI range. Functionality remains unchanged for setups that do
not require eSPIs.

The series includes:
1) General refactoring of common IRQ operations with GIC registers to
improve code readability, simplify further maintenance and prepare the
key functions for eSPI implementation.
2) Introducing a new Kconfig option (default n) to enable or disable
eSPI support. Disabling this option prevents unnecessary resource
allocation for setups that do not require eSPIs.
3) Adding additional resources to store required information and operate
with up to 1024 interrupts from eSPI range.
4) Adjusting assertions and checks to pass verification for INTIDs in
the eSPI range.
5) Configuration of eSPI-specific registers during GIC initialization
for systems with GICv3.1+ hardware.
6) Enables eSPI MMIO emulation for vGIC, allowing guest domains to
access and operate within the eSPI's INTIDs.


Changes in V2:
- added 2 more patches to implement helper
  functions for gic/vgic:
  xen/arm: gic: implement helper functions for INTID checks
  xen/arm: vgic: implement helper functions for virq checks
- removed 2 patches:
  xen/arm/irq: allow assignment/releasing of eSPI interrupts
  xen/arm: gic/irq: permit routing of eSPI interrupts to Xen and domains
  since their functionality can be moved to appropriate patches after
  introducing patches with helper functions
- individual changes in patches

Link on V1:
- https://lists.xenproject.org/archives/html/xen-devel/2025-07/msg01809.htm=
l


Changes in V3:
- added a patch to update CHANGELOG.md
- individual changes in patches

Link on V2:
- https://lists.xenproject.org/archives/html/xen-devel/2025-08/msg00372.htm=
l

Leonid Komarianskyi (11):
  xen/arm: gicv3: refactor obtaining GIC addresses for common operations
  xen/arm: gic: implement helper functions for INTID checks
  xen/arm: vgic: implement helper functions for virq checks
  xen/arm/irq: add handling for IRQs in the eSPI range
  xen/arm: gicv3: implement handling of GICv3.1 eSPI
  xen/arm/irq: allow eSPI processing in the do_IRQ function
  xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow eSPI processing
  xen/arm: vgic: add resource management for extended SPIs
  xen/arm: domain_build/dom0less-build: adjust domains config to support
    eSPIs
  xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers
  CHANGELOG.md: add mention of GICv3.1 eSPI support

 CHANGELOG.md                           |   1 +
 xen/arch/arm/Kconfig                   |   9 +
 xen/arch/arm/dom0less-build.c          |  12 ++
 xen/arch/arm/domain_build.c            |  11 +
 xen/arch/arm/gic-v3.c                  | 192 ++++++++++++++---
 xen/arch/arm/gic.c                     |   7 +-
 xen/arch/arm/include/asm/gic.h         |  30 +++
 xen/arch/arm/include/asm/gic_v3_defs.h |  36 +++-
 xen/arch/arm/include/asm/irq.h         |  27 +++
 xen/arch/arm/include/asm/vgic.h        |  39 ++++
 xen/arch/arm/irq.c                     |  58 +++++-
 xen/arch/arm/vgic-v3.c                 | 275 ++++++++++++++++++++++++-
 xen/arch/arm/vgic.c                    | 222 +++++++++++++++++++-
 xen/arch/arm/vgic/vgic.c               |   5 +
 14 files changed, 868 insertions(+), 56 deletions(-)

--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v3 03/11] xen/arm: vgic: implement helper functions for virq
 checks
Thread-Topic: [PATCH v3 03/11] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Index: AQHcFpJ/eek3/DqJlE2eNsEQLkbJqg==
Date: Tue, 26 Aug 2025 14:05:37 +0000
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Introduced two new helper functions for vGIC: vgic_is_valid_line and
vgic_is_spi. The functions are similar to the newly introduced
gic_is_valid_line and gic_is_spi, but they verify whether a vIRQ
is available for a specific domain, while GIC-specific functions
validate INTIDs for the real GIC hardware. For example, the GIC may
support all 992 SPI lines, but the domain may use only some part of them
(e.g., 640), depending on the highest IRQ number defined in the domain
configuration. Therefore, for vGIC-related code and checks, the
appropriate functions should be used. Also, updated the appropriate
checks to use these new helper functions.

The purpose of introducing new helper functions for vGIC is essentially
the same as for GIC: to avoid potential confusion with GIC-related
checks and to consolidate similar code into separate functions, which
can be more easily extended by additional conditions, e.g., when
implementing extended SPI interrupts.

Only the validation change in vgic_inject_irq may affect existing
functionality, as it currently checks whether the vIRQ is less than or
equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
first SPI), the check should behave consistently with similar logic in
other places and should check if the vIRQ number is less than
vgic_num_irqs. The remaining changes, which replace open-coded checks
with the use of these new helper functions, do not introduce any
functional changes, as the helper functions follow the current vIRQ
index verification logic.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- introduced this patch

Changes in V3:
- renamed vgic_is_valid_irq to vgic_is_valid_line and vgic_is_shared_irq
  to vgic_is_spi
- added vgic_is_valid_line implementation for new-vgic, because
  vgic_is_valid_line is called from generic code. It is necessary to fix
  the build for new-vgic.
- updated commit message
---
 xen/arch/arm/gic.c              |  3 +--
 xen/arch/arm/include/asm/vgic.h |  7 +++++++
 xen/arch/arm/irq.c              |  4 ++--
 xen/arch/arm/vgic.c             | 10 ++++++++--
 xen/arch/arm/vgic/vgic.c        |  5 +++++
 5 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 9220eef6ea..b88237ccda 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -133,8 +133,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned i=
nt virq,
=20
     ASSERT(spin_is_locked(&desc->lock));
     /* Caller has already checked that the IRQ is an SPI */
-    ASSERT(virq >=3D 32);
-    ASSERT(virq < vgic_num_irqs(d));
+    ASSERT(vgic_is_spi(d, virq));
     ASSERT(!is_lpi(virq));
=20
     ret =3D vgic_connect_hw_irq(d, NULL, virq, desc, true);
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 35c0c6a8b0..9f437e9838 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -335,6 +335,13 @@ extern void vgic_check_inflight_irqs_pending(struct vc=
pu *v,
 /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
 #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
=20
+extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
+
+static inline bool vgic_is_spi(struct domain *d, unsigned int virq)
+{
+    return (virq >=3D NR_LOCAL_IRQS && vgic_is_valid_line(d, virq));
+}
+
 /*
  * Allocate a guest VIRQ
  *  - spi =3D=3D 0 =3D> allocate a PPI. It will be the same on every vCPU
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 7dd5a2a453..b8eccfc924 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -442,7 +442,7 @@ int route_irq_to_guest(struct domain *d, unsigned int v=
irq,
     unsigned long flags;
     int retval =3D 0;
=20
-    if ( virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_valid_line(d, virq) )
     {
         printk(XENLOG_G_ERR
                "the vIRQ number %u is too high for domain %u (max =3D %u)\=
n",
@@ -560,7 +560,7 @@ int release_guest_irq(struct domain *d, unsigned int vi=
rq)
     int ret;
=20
     /* Only SPIs are supported */
-    if ( virq < NR_LOCAL_IRQS || virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_spi(d, virq) )
         return -EINVAL;
=20
     desc =3D vgic_get_hw_irq_desc(d, NULL, virq);
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index c563ba93af..2bbf4d99aa 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -24,6 +24,12 @@
 #include 
 #include 
=20
+
+bool vgic_is_valid_line(struct domain *d, unsigned int virq)
+{
+    return virq < vgic_num_irqs(d);
+}
+
 static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
                                                   unsigned int rank)
 {
@@ -582,7 +588,7 @@ void vgic_inject_irq(struct domain *d, struct vcpu *v, =
unsigned int virq,
     if ( !v )
     {
         /* The IRQ needs to be an SPI if no vCPU is specified. */
-        ASSERT(virq >=3D 32 && virq <=3D vgic_num_irqs(d));
+        ASSERT(vgic_is_spi(d, virq));
=20
         v =3D vgic_get_target_vcpu(d->vcpu[0], virq);
     };
@@ -659,7 +665,7 @@ bool vgic_emulate(struct cpu_user_regs *regs, union hsr=
 hsr)
=20
 bool vgic_reserve_virq(struct domain *d, unsigned int virq)
 {
-    if ( virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_valid_line(d, virq) )
         return false;
=20
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index 6cabd0496d..b2c0e1873a 100644
--- a/xen/arch/arm/vgic/vgic.c
+++ b/xen/arch/arm/vgic/vgic.c
@@ -718,6 +718,11 @@ bool vgic_reserve_virq(struct domain *d, unsigned int =
virq)
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
 }
=20
+bool vgic_is_valid_line(struct domain *d, unsigned int virq)
+{
+    return virq < vgic_num_irqs(d);
+}
+
 int vgic_allocate_virq(struct domain *d, bool spi)
 {
     int first, end;
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk 
Subject: [PATCH v3 01/11] xen/arm: gicv3: refactor obtaining GIC addresses for
 common operations
Thread-Topic: [PATCH v3 01/11] xen/arm: gicv3: refactor obtaining GIC
 addresses for common operations
Thread-Index: AQHcFpJ+etlgg3EWd0CB0IzwgFrWeQ==
Date: Tue, 26 Aug 2025 14:05:36 +0000
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Currently, many common functions perform the same operations to calculate
GIC register addresses. This patch consolidates the similar code into
a separate helper function to improve maintainability and reduce duplicatio=
n.
This refactoring also simplifies the implementation of eSPI support in futu=
re
changes.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 

---
Changes in V2:
- no changes

Changes in V3:
- changed panic() in get_addr_by_offset() to printing warning and
  ASSERT_UNREACHABLE()
- added verification of return pointer from get_addr_by_offset() in the
  callers
- moved invocation of get_addr_by_offset() from spinlock guards, since
  it is not necessarry
- added RB from Volodymyr Babchuk
---
 xen/arch/arm/gic-v3.c          | 114 +++++++++++++++++++++++----------
 xen/arch/arm/include/asm/irq.h |   1 +
 2 files changed, 81 insertions(+), 34 deletions(-)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index cd3e1acf79..a959fefebe 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -445,17 +445,67 @@ static void gicv3_dump_state(const struct vcpu *v)
     }
 }
=20
+static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
+{
+    switch ( irqd->irq )
+    {
+    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+        case GICD_ICENABLER:
+        case GICD_ISPENDR:
+        case GICD_ICPENDR:
+        case GICD_ISACTIVER:
+        case GICD_ICACTIVER:
+            return (GICD_RDIST_SGI_BASE + offset);
+        case GICD_ICFGR:
+            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
+        case GICD_IPRIORITYR:
+            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
+        default:
+            break;
+        }
+    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+        case GICD_ICENABLER:
+        case GICD_ISPENDR:
+        case GICD_ICPENDR:
+        case GICD_ISACTIVER:
+        case GICD_ICACTIVER:
+            return (GICD + offset + (irqd->irq / 32) * 4);
+        case GICD_ICFGR:
+            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
+        case GICD_IROUTER:
+            return (GICD + GICD_IROUTER + irqd->irq * 8);
+        case GICD_IPRIORITYR:
+            return (GICD + GICD_IPRIORITYR + irqd->irq);
+        default:
+            break;
+        }
+    default:
+        break;
+    }
+
+    /* Something went wrong, we shouldn't be able to reach here */
+    printk(XENLOG_WARNING "GICv3: WARNING: Invalid offset 0x%x for IRQ#%d"=
,
+           offset, irqd->irq);
+    ASSERT_UNREACHABLE();
+
+    return NULL;
+}
+
 static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_fo=
r_rwp)
 {
     u32 mask =3D 1U << (irqd->irq % 32);
-    void __iomem *base;
+    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
=20
-    if ( irqd->irq < NR_GIC_LOCAL_IRQS )
-        base =3D GICD_RDIST_SGI_BASE;
-    else
-        base =3D GICD;
+    if ( addr =3D=3D NULL )
+        return;
=20
-    writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
+    writel_relaxed(mask, addr);
=20
     if ( wait_for_rwp )
         gicv3_wait_for_rwp(irqd->irq);
@@ -463,15 +513,12 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u32=
 offset, bool wait_for_rwp)
=20
 static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset)
 {
-    void __iomem *base;
-    unsigned int irq =3D irqd->irq;
+    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
=20
-    if ( irq >=3D NR_GIC_LOCAL_IRQS)
-        base =3D GICD + (irq / 32) * 4;
-    else
-        base =3D GICD_RDIST_SGI_BASE;
+    if ( addr =3D=3D NULL )
+        return false;
=20
-    return !!(readl(base + offset) & (1U << (irq % 32)));
+    return !!(readl(addr) & (1U << (irqd->irq % 32)));
 }
=20
 static void gicv3_unmask_irq(struct irq_desc *irqd)
@@ -558,30 +605,28 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cp=
u)
 static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type)
 {
     uint32_t cfg, actual, edgebit;
-    void __iomem *base;
-    unsigned int irq =3D desc->irq;
+    void __iomem *addr;
=20
     /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
-    ASSERT(irq >=3D NR_GIC_SGI);
+    ASSERT(desc->irq >=3D NR_GIC_SGI);
=20
-    spin_lock(&gicv3.lock);
+    addr =3D get_addr_by_offset(desc, GICD_ICFGR);
+    if ( addr =3D=3D NULL )
+        return;
=20
-    if ( irq >=3D NR_GIC_LOCAL_IRQS)
-        base =3D GICD + GICD_ICFGR + (irq / 16) * 4;
-    else
-        base =3D GICD_RDIST_SGI_BASE + GICR_ICFGR1;
+    spin_lock(&gicv3.lock);
=20
-    cfg =3D readl_relaxed(base);
+    cfg =3D readl_relaxed(addr);
=20
-    edgebit =3D 2u << (2 * (irq % 16));
+    edgebit =3D 2u << (2 * (desc->irq % 16));
     if ( type & IRQ_TYPE_LEVEL_MASK )
         cfg &=3D ~edgebit;
     else if ( type & IRQ_TYPE_EDGE_BOTH )
         cfg |=3D edgebit;
=20
-    writel_relaxed(cfg, base);
+    writel_relaxed(cfg, addr);
=20
-    actual =3D readl_relaxed(base);
+    actual =3D readl_relaxed(addr);
     if ( ( cfg & edgebit ) ^ ( actual & edgebit ) )
     {
         printk(XENLOG_WARNING "GICv3: WARNING: "
@@ -600,16 +645,13 @@ static void gicv3_set_irq_type(struct irq_desc *desc,=
 unsigned int type)
 static void gicv3_set_irq_priority(struct irq_desc *desc,
                                    unsigned int priority)
 {
-    unsigned int irq =3D desc->irq;
+    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IPRIORITYR);
=20
-    spin_lock(&gicv3.lock);
-
-    /* Set priority */
-    if ( irq < NR_GIC_LOCAL_IRQS )
-        writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + =
irq);
-    else
-        writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
+    if ( addr =3D=3D NULL )
+        return;
=20
+    spin_lock(&gicv3.lock);
+    writeb_relaxed(priority, addr);
     spin_unlock(&gicv3.lock);
 }
=20
@@ -1273,6 +1315,10 @@ static void gicv3_irq_set_affinity(struct irq_desc *=
desc, const cpumask_t *mask)
 {
     unsigned int cpu;
     uint64_t affinity;
+    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IROUTER);
+
+    if ( addr =3D=3D NULL )
+        return;
=20
     ASSERT(!cpumask_empty(mask));
=20
@@ -1284,7 +1330,7 @@ static void gicv3_irq_set_affinity(struct irq_desc *d=
esc, const cpumask_t *mask)
     affinity &=3D ~GICD_IROUTER_SPI_MODE_ANY;
=20
     if ( desc->irq >=3D NR_GIC_LOCAL_IRQS )
-        writeq_relaxed_non_atomic(affinity, (GICD + GICD_IROUTER + desc->i=
rq * 8));
+        writeq_relaxed_non_atomic(affinity, addr);
=20
     spin_unlock(&gicv3.lock);
 }
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.=
h
index fce7e42a33..5bc6475eb4 100644
--- a/xen/arch/arm/include/asm/irq.h
+++ b/xen/arch/arm/include/asm/irq.h
@@ -29,6 +29,7 @@ struct arch_irq_desc {
  */
 #define NR_IRQS		1024
=20
+#define SPI_MAX_INTID   1019
 #define LPI_OFFSET      8192
=20
 /* LPIs are always numbered starting at 8192, so 0 is a good invalid case.=
 */
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v3 07/11] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow
 eSPI processing
Thread-Topic: [PATCH v3 07/11] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
 allow eSPI processing
Thread-Index: AQHcFpKAYFxN4fU1Wk6sdm7zcMlbgA==
Date: Tue, 26 Aug 2025 14:05:38 +0000
Message-ID:
 <20a8af6879ef06af92d3cd1e0519c406792ca088.1756216943.git.leonid_komarianskyi@epam.com>
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To properly deactivate guest interrupts and allow them to be retriggered
after the initial trigger, the LR needs to be updated. The current
implementation ignores interrupts outside the range specified by the mask
0x3FF, which only covers IRQ numbers up to 1023. To enable processing of
eSPI interrupts, this patch updates the mask to 0x13FF.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- remove unnecessary CONFIG_GICV3_ESPI ifdef guard

Changes in V3:
- no changes
---
 xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/=
asm/gic_v3_defs.h
index d38a3d08c7..ca403131bd 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -207,7 +207,7 @@
 #define ICH_LR_VIRTUAL_SHIFT         0
 #define ICH_LR_CPUID_MASK            0x7
 #define ICH_LR_CPUID_SHIFT           10
-#define ICH_LR_PHYSICAL_MASK         0x3ff
+#define ICH_LR_PHYSICAL_MASK         0x13ff
 #define ICH_LR_PHYSICAL_SHIFT        32
 #define ICH_LR_STATE_MASK            0x3
 #define ICH_LR_STATE_SHIFT           62
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v3 09/11] xen/arm: domain_build/dom0less-build: adjust domains
 config to support eSPIs
Thread-Topic: [PATCH v3 09/11] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Index: AQHcFpKAZWUsU5Sz9EWrJGvlceTbIw==
Date: Tue, 26 Aug 2025 14:05:38 +0000
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The Dom0 and DomUs logic for the dom0less configuration in create_dom0()
and arch_create_domUs() has been updated to account for extended SPIs
when supported by the hardware and enabled with CONFIG_GICV3_ESPI. These
changes ensure the proper calculation of the maximum number of SPIs and
eSPIs available to Dom0 and DomUs in dom0less setups.

When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is
enabled, the maximum number of eSPI interrupts is calculated using the
ESPI_BASE_INTID offset (4096) and is limited to 1024, with 32 IRQs
subtracted. To ensure compatibility with DomUs (Dom0 setups) domains,
where this adjustment is applied by the toolstack during domain
creation, while for Dom0 or DomUs in Dom0, it is handled directly during
VGIC initialization. If eSPIs are not supported, the calculation
defaults to using the standard SPI range, with a maximum value of
960 interrupt lines, as it works currently.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- no changes

Changes in V3:
- renamed macro VGIC_DEF_NR_ESPIS to more appropriate VGIC_DEF_MAX_SPI
- added eSPI initialization for dom0less setups
- fixed comment with mentions about dom0less builds
- fixed formatting for lines with more than 80 symbols
- updated commit message
---
 xen/arch/arm/dom0less-build.c   | 12 ++++++++++++
 xen/arch/arm/domain_build.c     | 11 +++++++++++
 xen/arch/arm/include/asm/vgic.h | 14 ++++++++++++++
 3 files changed, 37 insertions(+)

diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 69b9ea22ce..f4f9077db5 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -286,6 +286,18 @@ void __init arch_create_domUs(struct dt_device_node *n=
ode,
         int vpl011_virq =3D GUEST_VPL011_SPI;
=20
         d_cfg->arch.nr_spis =3D VGIC_DEF_NR_SPIS;
+#ifdef CONFIG_GICV3_ESPI
+        /*
+         * Check if the hardware supports extended SPIs (even if the
+         * appropriate config is set). If not, the common SPI range
+         * will be used. Otherwise overwrite the nr_spis with the maximum
+         * available INTID from eSPI range. In that case, the number of
+         * regular SPIs will be adjusted to the maximum value during vGIC
+         * initialization.
+         */
+        if ( gic_number_espis() > 0 )
+            d_cfg->arch.nr_spis =3D VGIC_DEF_MAX_SPI;
+#endif
=20
         /*
          * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index d91a71acfd..148a8bdb60 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2055,6 +2055,17 @@ void __init create_dom0(void)
     /* The vGIC for DOM0 is exactly emulating the hardware GIC */
     dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
     dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS;
+#ifdef CONFIG_GICV3_ESPI
+    /*
+     * Check if the hardware supports extended SPIs (even if the appropria=
te
+     * config is set). If not, the common SPI range will be used. Otherwis=
e
+     * overwrite the nr_spis with the maximum available INTID from eSPI ra=
nge.
+     * In that case, the number of regular SPIs will be adjusted to the ma=
ximum
+     * value during vGIC initialization.
+     */
+    if ( gic_number_espis() > 0 )
+        dom0_cfg.arch.nr_spis =3D VGIC_DEF_MAX_SPI;
+#endif
     dom0_cfg.arch.tee_type =3D tee_get_type();
     dom0_cfg.max_vcpus =3D dom0_max_vcpus();
=20
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 248b5869e1..0bb025f5d5 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -353,6 +353,20 @@ extern void vgic_check_inflight_irqs_pending(struct vc=
pu *v,
 /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
 #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
=20
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * Returns the maximum eSPI INTID, supported by HW GIC, subtracted by 32. =
For
+ * non-Dom0 domains, the toolstack or arch_create_domUs function applies t=
he
+ * same adjustment to cover local IRQs (please, see comment for macro that=
 is
+ * used for regular SPIs - VGIC_DEF_NR_SPIS). We will add back this value
+ * during VGIC initialization. This ensures consistent handling for Dom0 a=
nd
+ * other domains. For the regular SPI range interrupts in this case, the
+ * maximum value of VGIC_DEF_NR_SPIS will be used.
+ */
+#define VGIC_DEF_MAX_SPI (ESPI_BASE_INTID + \
+                          min(gic_number_espis(), 1024U) - 32)
+#endif
+
 extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
=20
 static inline bool vgic_is_spi(struct domain *d, unsigned int virq)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v3 08/11] xen/arm: vgic: add resource management for extended
 SPIs
Thread-Topic: [PATCH v3 08/11] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcFpKACzOaRjOW50q/bIpnflDhkw==
Date: Tue, 26 Aug 2025 14:05:38 +0000
Message-ID:
 <88254ec24a25e3d99950fb5041ac6b050aaa1e4a.1756216943.git.leonid_komarianskyi@epam.com>
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This change introduces resource management in the VGIC to handle
extended SPIs introduced in GICv3.1. The pending_irqs and
allocated_irqs arrays are resized to support the required
number of eSPIs, based on what is supported by the hardware and
requested by the guest. A new field, ext_shared_irqs, is added
to the VGIC structure to store information about eSPIs, similar
to how shared_irqs is used for regular SPIs.

Since the eSPI range starts at INTID 4096 and INTIDs between 1025
and 4095 are reserved, helper macros are introduced to simplify the
transformation of indices and to enable easier access to eSPI-specific
resources. These changes prepare the VGIC for processing eSPIs as
required by future functionality.

The initialization and deinitialization paths for vgic have been updated
to allocate and free these resources appropriately. Additionally,
updated handling of INTIDs greater than 1024, passed from the toolstack
during domain creation, and verification logic ensures only valid SPI or
eSPI INTIDs are used.

The existing SPI behavior remains unaffected when guests do not request
eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
option is disabled.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- change is_espi_rank to is_valid_espi_rank to verify whether the array
  element ext_shared_irqs exists. The previous version, is_espi_rank,
  only checked if the rank index was less than the maximum possible eSPI
  rank index, but this could potentially result in accessing a
  non-existing array element. To address this, is_valid_espi_rank was
  introduced, which ensures that the required eSPI rank exists
- move gic_number_espis to
  xen/arm: gicv3: implement handling of GICv3.1 eSPI
- update vgic_is_valid_irq checks to allow operating with eSPIs
- remove redundant newline in vgic_allocate_virq

Changes in V3:
- fixed formatting for lines with more than 80 symbols
- introduced helper functions to be able to use stubs in case of
  CONFIG_GICV3_ESPI disabled, and as a result, reduce the number of
  #ifdefs
- fixed checks for nr_spis in domain_vgic_init
- updated comment about nr_spis adjustments with dom0less mention
- moved comment with additional explanations before checks
- used unsigned int for indexes since they cannot be negative
- removed unnecessary parentheses
- move vgic_ext_rank_offset to the below ifdef guard, to reduce the
  number of ifdefs
---
 xen/arch/arm/include/asm/vgic.h |  18 +++
 xen/arch/arm/vgic.c             | 212 +++++++++++++++++++++++++++++++-
 2 files changed, 227 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 9f437e9838..248b5869e1 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -146,6 +146,10 @@ struct vgic_dist {
     int nr_spis; /* Number of SPIs */
     unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
     struct vgic_irq_rank *shared_irqs;
+#ifdef CONFIG_GICV3_ESPI
+    struct vgic_irq_rank *ext_shared_irqs;
+    int nr_espis; /* Number of extended SPIs */
+#endif
     /*
      * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
      * struct arch_vcpu.
@@ -243,6 +247,14 @@ struct vgic_ops {
 /* Number of ranks of interrupt registers for a domain */
 #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
=20
+#ifdef CONFIG_GICV3_ESPI
+#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
+#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
+#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
+#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
+#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
+#endif
+
 #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
 #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
=20
@@ -302,6 +314,12 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct v=
cpu *v,
                                               unsigned int b,
                                               unsigned int n,
                                               unsigned int s);
+#ifdef CONFIG_GICV3_ESPI
+extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
+                                                  unsigned int b,
+                                                  unsigned int n,
+                                                  unsigned int s);
+#endif
 extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int ir=
q);
 extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
 extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 2bbf4d99aa..ae4119316f 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -27,9 +27,82 @@
=20
 bool vgic_is_valid_line(struct domain *d, unsigned int virq)
 {
+#ifdef CONFIG_GICV3_ESPI
+    if ( virq >=3D ESPI_BASE_INTID &&
+         virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
+        return true;
+#endif
+
     return virq < vgic_num_irqs(d);
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * Since eSPI indexes start from 4096 and numbers from 1024 to
+ * 4095 are forbidden, we need to check both lower and upper
+ * limits for ranks.
+ */
+static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
+{
+    return ( rank >=3D EXT_RANK_MIN &&
+             EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d) );
+}
+
+static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
+                                                       unsigned int rank)
+{
+    return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)];
+}
+
+static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int v=
irq)
+{
+    return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d),
+                             d->arch.vgic.allocated_irqs);
+}
+
+static void arch_move_espis(struct vcpu *v)
+{
+    const cpumask_t *cpu_mask =3D cpumask_of(v->processor);
+    struct domain *d =3D v->domain;
+    struct pending_irq *p;
+    struct vcpu *v_target;
+    unsigned int i;
+
+    for ( i =3D ESPI_BASE_INTID;
+          i < EXT_RANK_IDX2NUM(d->arch.vgic.nr_espis); i++ )
+    {
+        v_target =3D vgic_get_target_vcpu(v, i);
+        p =3D irq_to_pending(v_target, i);
+
+        if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->s=
tatus) )
+            irq_set_affinity(p->desc, cpu_mask);
+    }
+}
+#else
+static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
+{
+    return false;
+}
+
+/*
+ * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn,
+ * because in this case, is_valid_espi_rank will always return false.
+ */
+static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
+                                                       unsigned int rank)
+{
+    ASSERT_UNREACHABLE();
+    return NULL;
+}
+
+static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int v=
irq)
+{
+    return false;
+}
+
+static void arch_move_espis(struct vcpu *v) { }
+#endif
+
 static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
                                                   unsigned int rank)
 {
@@ -37,6 +110,8 @@ static inline struct vgic_irq_rank *vgic_get_rank(struct=
 vcpu *v,
         return v->arch.vgic.private_irqs;
     else if ( rank <=3D DOMAIN_NR_RANKS(v->domain) )
         return &v->domain->arch.vgic.shared_irqs[rank - 1];
+    else if ( is_valid_espi_rank(v->domain, rank) )
+        return vgic_get_espi_rank(v, rank);
     else
         return NULL;
 }
@@ -117,6 +192,76 @@ int domain_vgic_register(struct domain *d, unsigned in=
t *mmio_count)
     return 0;
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * The function behaviur is the same as for regular SPIs (vgic_rank_offset=
),
+ * but it operates with extended SPI ranks.
+ */
+struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int b,
+                                           unsigned int n, unsigned int s)
+{
+    unsigned int rank =3D REG_RANK_NR(b, (n >> s));
+
+    return vgic_get_rank(v, rank + EXT_RANK_MIN);
+}
+
+static unsigned int vgic_num_spi_lines(struct domain *d)
+{
+    return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
+}
+
+static int init_vgic_espi(struct domain *d)
+{
+    unsigned int i, idx;
+
+    if ( d->arch.vgic.nr_espis =3D=3D 0 )
+        return 0;
+
+    d->arch.vgic.ext_shared_irqs =3D
+        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
+    if ( d->arch.vgic.ext_shared_irqs =3D=3D NULL )
+        return -ENOMEM;
+
+    for ( i =3D d->arch.vgic.nr_spis, idx =3D 0;
+          i < vgic_num_spi_lines(d); i++, idx++ )
+    {
+        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i],
+                              ESPI_IDX2INTID(idx));
+    }
+
+    for ( i =3D 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
+        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
+
+    return 0;
+}
+
+struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
+{
+    irq =3D ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
+    return &d->arch.vgic.pending_irqs[irq];
+}
+#else
+static unsigned int init_vgic_espi(struct domain *d)
+{
+    return 0;
+}
+
+static unsigned int vgic_num_spi_lines(struct domain *d)
+{
+    return d->arch.vgic.nr_spis;
+}
+
+struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
+{
+    return NULL;
+}
+#endif
+
+static unsigned int vgic_num_alloc_irqs(struct domain *d)
+{
+    return vgic_num_spi_lines(d) + NR_LOCAL_IRQS;
+}
+
 int domain_vgic_init(struct domain *d, unsigned int nr_spis)
 {
     int i;
@@ -131,6 +276,35 @@ int domain_vgic_init(struct domain *d, unsigned int nr=
_spis)
      */
     nr_spis =3D ROUNDUP(nr_spis, 32);
=20
+#ifdef CONFIG_GICV3_ESPI
+    /*
+     * During domain creation, the dom0less DomUs code or toolstack specif=
ies
+     * the maximum INTID, which is defined in the domain config subtracted=
 by
+     * 32 to cover the local IRQs (please see the comment to VGIC_DEF_NR_S=
PIS).
+     * To compute the actual number of eSPI that will be usable for,
+     * add back 32.
+     */
+    if ( (nr_spis + 32) > ESPI_IDX2INTID(NR_ESPI_IRQS) )
+        return -EINVAL;
+
+    if ( (nr_spis + 32) >=3D ESPI_BASE_INTID )
+    {
+        d->arch.vgic.nr_espis =3D min(nr_spis - ESPI_BASE_INTID + 32, 1024=
U);
+        /* Verify if GIC HW can handle provided INTID */
+        if ( d->arch.vgic.nr_espis > gic_number_espis() )
+            return -EINVAL;
+        /*
+         * Set the maximum available number for regular
+         * SPI to pass the next check
+         */
+        nr_spis =3D VGIC_DEF_NR_SPIS;
+    } else
+    {
+        /* Domain will use the regular SPI range */
+        d->arch.vgic.nr_espis =3D 0;
+    }
+#endif
+
     /* Limit the number of virtual SPIs supported to (1020 - 32) =3D 988  =
*/
     if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
         return -EINVAL;
@@ -145,7 +319,7 @@ int domain_vgic_init(struct domain *d, unsigned int nr_=
spis)
         return -ENOMEM;
=20
     d->arch.vgic.pending_irqs =3D
-        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
+        xzalloc_array(struct pending_irq, vgic_num_spi_lines(d));
     if ( d->arch.vgic.pending_irqs =3D=3D NULL )
         return -ENOMEM;
=20
@@ -156,12 +330,16 @@ int domain_vgic_init(struct domain *d, unsigned int n=
r_spis)
     for ( i =3D 0; i < DOMAIN_NR_RANKS(d); i++ )
         vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
=20
+    ret =3D init_vgic_espi(d);
+    if ( ret )
+        return ret;
+
     ret =3D d->arch.vgic.handler->domain_init(d);
     if ( ret )
         return ret;
=20
     d->arch.vgic.allocated_irqs =3D
-        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
+        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_alloc_irqs(d))=
);
     if ( !d->arch.vgic.allocated_irqs )
         return -ENOMEM;
=20
@@ -195,9 +373,27 @@ void domain_vgic_free(struct domain *d)
         }
     }
=20
+#ifdef CONFIG_GICV3_ESPI
+    for ( i =3D 0; i < d->arch.vgic.nr_espis; i++ )
+    {
+        struct pending_irq *p =3D spi_to_pending(d, ESPI_IDX2INTID(i));
+
+        if ( p->desc )
+        {
+            ret =3D release_guest_irq(d, p->irq);
+            if ( ret )
+                dprintk(XENLOG_G_WARNING, "d%u: Failed to release virq %u =
ret =3D %d\n",
+                        d->domain_id, p->irq, ret);
+        }
+    }
+#endif
+
     if ( d->arch.vgic.handler )
         d->arch.vgic.handler->domain_free(d);
     xfree(d->arch.vgic.shared_irqs);
+#ifdef CONFIG_GICV3_ESPI
+    xfree(d->arch.vgic.ext_shared_irqs);
+#endif
     xfree(d->arch.vgic.pending_irqs);
     xfree(d->arch.vgic.allocated_irqs);
 }
@@ -331,6 +527,8 @@ void arch_move_irqs(struct vcpu *v)
         if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->s=
tatus) )
             irq_set_affinity(p->desc, cpu_mask);
     }
+
+    arch_move_espis(v);
 }
=20
 void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
@@ -538,6 +736,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v, unsi=
gned int irq)
         n =3D &v->arch.vgic.pending_irqs[irq];
     else if ( is_lpi(irq) )
         n =3D v->domain->arch.vgic.handler->lpi_to_pending(v->domain, irq)=
;
+    else if ( is_espi(irq) )
+        n =3D espi_to_pending(v->domain, irq);
     else
         n =3D &v->domain->arch.vgic.pending_irqs[irq - 32];
     return n;
@@ -547,6 +747,9 @@ struct pending_irq *spi_to_pending(struct domain *d, un=
signed int irq)
 {
     ASSERT(irq >=3D NR_LOCAL_IRQS);
=20
+    if ( is_espi(irq) )
+        return espi_to_pending(d, irq);
+
     return &d->arch.vgic.pending_irqs[irq - 32];
 }
=20
@@ -668,6 +871,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned int v=
irq)
     if ( !vgic_is_valid_line(d, virq) )
         return false;
=20
+    if ( is_espi(virq) )
+        return vgic_reserve_espi_virq(d, virq);
+
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
 }
=20
@@ -685,7 +891,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
     else
     {
         first =3D 32;
-        end =3D vgic_num_irqs(d);
+        end =3D vgic_num_alloc_irqs(d);
     }
=20
     /*
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v3 10/11] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v3 10/11] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Index: AQHcFpKAKCVIbYC3hEGAz+VsUD3/gQ==
Date: Tue, 26 Aug 2025 14:05:39 +0000
Message-ID:
 <642a994d712a8c9df7aed9dec22124564db83c7e.1756216943.git.leonid_komarianskyi@epam.com>
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Implemented support for GICv3.1 extended SPI registers for vGICv3,
allowing the emulation of eSPI-specific behavior for guest domains.
The implementation includes read and write emulation for eSPI-related
registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
following a similar approach to the handling of regular SPIs.

The eSPI registers, previously located in reserved address ranges,
are now adjusted to support MMIO read and write operations correctly
when CONFIG_GICV3_ESPI is enabled.

The availability of eSPIs and the number of emulated extended SPIs
for guest domains is reported by setting the appropriate bits in the
GICD_TYPER register, based on the number of eSPIs requested by the
domain and supported by the hardware. In cases where the configuration
option is disabled, the hardware does not support eSPIs, or the domain
does not request such interrupts, the functionality remains unchanged.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V2:
- add missing rank index conversion for pending and inflight irqs

Changes in V3:
- changed vgic_store_irouter parameters - instead of offset virq is
  used, to remove the additional bool espi parameter and simplify
  checks. Also, adjusted parameters for regular SPI. Since the offset
  parameter was used only for calculating virq number and then reused for
  finding rank offset, it will not affect functionality.
- fixed formatting for goto lables - added newlines after condition
- fixed logs for GICD_ISACTIVERnE and GICD_ICACTIVERnE handlers
- removed #ifdefs in 2 places where they were adjacent and could be merged
---
 xen/arch/arm/vgic-v3.c | 275 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 266 insertions(+), 9 deletions(-)

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 4369c55177..56c539bb1b 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -111,13 +111,10 @@ static uint64_t vgic_fetch_irouter(struct vgic_irq_ra=
nk *rank,
  * Note the offset will be aligned to the appropriate boundary.
  */
 static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *ran=
k,
-                               unsigned int offset, uint64_t irouter)
+                               unsigned int virq, uint64_t irouter)
 {
     struct vcpu *new_vcpu, *old_vcpu;
-    unsigned int virq;
-
-    /* There is 1 vIRQ per IROUTER */
-    virq =3D offset / NR_BYTES_PER_IROUTER;
+    unsigned int offset;
=20
     /*
      * The IROUTER0-31, used for SGIs/PPIs, are reserved and should
@@ -685,6 +682,9 @@ static int __vgic_v3_distr_common_mmio_read(const char =
*name, struct vcpu *v,
     {
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+#endif
         /* We do not implement security extensions for guests, read zero *=
/
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
         goto read_as_zero;
@@ -710,11 +710,19 @@ static int __vgic_v3_distr_common_mmio_read(const cha=
r *name, struct vcpu *v,
     /* Read the pending status of an IRQ via GICD/GICR is not supported */
     case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
     case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+#endif
         goto read_as_zero;
=20
     /* Read the active status of an IRQ via GICD/GICR is not supported */
     case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
     case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+#endif
         goto read_as_zero;
=20
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
@@ -752,6 +760,69 @@ static int __vgic_v3_distr_common_mmio_read(const char=
 *name, struct vcpu *v,
         return 1;
     }
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        *r =3D vreg_reg32_extract(rank->ienable, info);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        *r =3D vreg_reg32_extract(rank->ienable, info);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    {
+        uint32_t ipriorityr;
+        uint8_t rank_index;
+
+        if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DABT_=
WORD);
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        rank_index =3D REG_RANK_INDEX(8, reg - GICD_IPRIORITYRnE, DABT_WOR=
D);
+
+        vgic_lock_rank(v, rank, flags);
+        ipriorityr =3D ACCESS_ONCE(rank->ipriorityr[rank_index]);
+        vgic_unlock_rank(v, rank, flags);
+
+        *r =3D vreg_reg32_extract(ipriorityr, info);
+
+        return 1;
+    }
+
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+    {
+        uint32_t icfgr;
+
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WORD)=
;
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        icfgr =3D rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE, DABT_WO=
RD)];
+        vgic_unlock_rank(v, rank, flags);
+
+        *r =3D vreg_reg32_extract(icfgr, info);
+
+        return 1;
+    }
+#endif
+
     default:
         printk(XENLOG_G_ERR
                "%pv: %s: unhandled read r%d offset %#08x\n",
@@ -782,6 +853,9 @@ static int __vgic_v3_distr_common_mmio_write(const char=
 *name, struct vcpu *v,
     {
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+#endif
         /* We do not implement security extensions for guests, write ignor=
e */
         goto write_ignore_32;
=20
@@ -871,6 +945,99 @@ static int __vgic_v3_distr_common_mmio_write(const cha=
r *name, struct vcpu *v,
         vgic_unlock_rank(v, rank, flags);
         return 1;
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        tr =3D rank->ienable;
+        vreg_reg32_setbits(&rank->ienable, r, info);
+        vgic_enable_irqs(v, (rank->ienable) & (~tr), EXT_RANK_IDX2NUM(rank=
->index));
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        tr =3D rank->ienable;
+        vreg_reg32_clearbits(&rank->ienable, r, info);
+        vgic_disable_irqs(v, (~rank->ienable) & tr, EXT_RANK_IDX2NUM(rank-=
>index));
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISPENDRnE, DABT_WOR=
D);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+
+        vgic_set_irqs_pending(v, r, EXT_RANK_IDX2NUM(rank->index));
+
+        return 1;
+
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICPENDRnE, DABT_WOR=
D);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+
+        vgic_check_inflight_irqs_pending(v, EXT_RANK_IDX2NUM(rank->index),=
 r);
+
+        goto write_ignore;
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        printk(XENLOG_G_ERR
+               "%pv: %s: unhandled word write %#"PRIregister" to ISACTIVER=
%dE\n",
+               v, name, r, reg - GICD_ISACTIVERnE);
+        return 0;
+
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+        printk(XENLOG_G_ERR
+               "%pv: %s: unhandled word write %#"PRIregister" to ICACTIVER=
%dE\n",
+               v, name, r, reg - GICD_ICACTIVER);
+        goto write_ignore_32;
+
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    {
+        uint32_t *ipriorityr, priority;
+
+        if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DABT_=
WORD);
+        if ( rank =3D=3D NULL ) goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        ipriorityr =3D &rank->ipriorityr[REG_RANK_INDEX(8, reg - GICD_IPRI=
ORITYRnE,
+                                                      DABT_WORD)];
+        priority =3D ACCESS_ONCE(*ipriorityr);
+        vreg_reg32_update(&priority, r, info);
+        ACCESS_ONCE(*ipriorityr) =3D priority;
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+    }
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WORD)=
;
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE=
,
+                                                     DABT_WORD)],
+                          r, info);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+#endif
+
     default:
         printk(XENLOG_G_ERR
                "%pv: %s: unhandled write r%d=3D%"PRIregister" offset %#08x=
\n",
@@ -1129,6 +1296,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
             typer |=3D GICD_TYPE_LPIS;
=20
         typer |=3D (v->domain->arch.vgic.intid_bits - 1) << GICD_TYPE_ID_B=
ITS_SHIFT;
+#ifdef CONFIG_GICV3_ESPI
+        if ( v->domain->arch.vgic.nr_espis > 0 )
+        {
+            /* Set eSPI support bit for the domain */
+            typer |=3D GICD_TYPER_ESPI;
+            /* Set ESPI range bits */
+            typer |=3D (DIV_ROUND_UP(v->domain->arch.vgic.nr_espis, 32) - =
1)
+                       << GICD_TYPER_ESPI_RANGE_SHIFT;
+        }
+#endif
=20
         *r =3D vreg_reg32_extract(typer, info);
=20
@@ -1194,6 +1371,18 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
     case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+#endif
         /*
          * Above all register are common with GICR and GICD
          * Manage in common
@@ -1216,7 +1405,11 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
         /* Replaced with GICR_ISPENDR0. So ignore write */
         goto read_as_zero_32;
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(0x3100, 0x60FC):
+#else
     case VRANGE32(0x0F30, 0x60FC):
+#endif
         goto read_reserved;
=20
     case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
@@ -1235,8 +1428,30 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
=20
         return 1;
     }
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
+    {
+        uint64_t irouter;
+
+        if ( !vgic_reg64_check_access(dabt) )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 64, gicd_reg - GICD_IROUTERnE,
+                                DABT_DOUBLE_WORD);
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTERnE);
+        vgic_unlock_rank(v, rank, flags);
=20
+        *r =3D vreg_reg64_extract(irouter, info);
+
+        return 1;
+    }
+
+    case VRANGE32(0xA004, 0xBFFC):
+#else
     case VRANGE32(0x7FE0, 0xBFFC):
+#endif
         goto read_reserved;
=20
     case VRANGE32(0xC000, 0xFFCC):
@@ -1382,6 +1597,18 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, =
mmio_info_t *info,
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
     case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+#endif
         /* Above registers are common with GICR and GICD
          * Manage in common */
         return __vgic_v3_distr_common_mmio_write("vGICD", v, info,
@@ -1405,26 +1632,56 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v,=
 mmio_info_t *info,
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
         return 0;
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(0x3100, 0x60FC):
+#else
     case VRANGE32(0x0F30, 0x60FC):
+#endif
         goto write_reserved;
=20
     case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
     {
         uint64_t irouter;
+        unsigned int offset, virq;
=20
         if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
-                                DABT_DOUBLE_WORD);
+        offset =3D gicd_reg - GICD_IROUTER;
+        rank =3D vgic_rank_offset(v, 64, offset, DABT_DOUBLE_WORD);
         if ( rank =3D=3D NULL ) goto write_ignore;
         vgic_lock_rank(v, rank, flags);
-        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTER);
+        irouter =3D vgic_fetch_irouter(rank, offset);
+        vreg_reg64_update(&irouter, r, info);
+        virq =3D offset / NR_BYTES_PER_IROUTER;
+        vgic_store_irouter(v->domain, rank, virq, irouter);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+    }
+
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
+    {
+        uint64_t irouter;
+        unsigned int offset, virq;
+
+        if ( !vgic_reg64_check_access(dabt) )
+            goto bad_width;
+        offset =3D gicd_reg - GICD_IROUTERnE;
+        rank =3D vgic_ext_rank_offset(v, 64, offset, DABT_DOUBLE_WORD);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        irouter =3D vgic_fetch_irouter(rank, offset);
         vreg_reg64_update(&irouter, r, info);
-        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTER, irout=
er);
+        virq =3D ESPI_IDX2INTID(offset / NR_BYTES_PER_IROUTER);
+        vgic_store_irouter(v->domain, rank, virq, irouter);
         vgic_unlock_rank(v, rank, flags);
         return 1;
     }
=20
+    case VRANGE32(0xA004, 0xBFFC):
+#else
     case VRANGE32(0x7FE0, 0xBFFC):
+#endif
         goto write_reserved;
=20
     case VRANGE32(0xC000, 0xFFCC):
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Oleksii Kurochko
	, Community Manager
	
Subject: [PATCH v3 11/11] CHANGELOG.md: add mention of GICv3.1 eSPI support
Thread-Topic: [PATCH v3 11/11] CHANGELOG.md: add mention of GICv3.1 eSPI
 support
Thread-Index: AQHcFpKAJEYb0CN0HkuGQwymf9ybDQ==
Date: Tue, 26 Aug 2025 14:05:39 +0000
Message-ID:
 <9dc68c29751aeacf37b51d3bd345e87e9a0f0ccf.1756216943.git.leonid_komarianskyi@epam.com>
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The GICv3.1 eSPI (Extended Shared Peripheral Interrupts) range is
already supported with CONFIG_GICV3_ESPI enabled, so this feature should
be mentioned in CHANGELOG.md.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V3:
- introduced this patch
---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe..dc34d29d99 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -29,6 +29,7 @@ The format is based on [Keep a Changelog](https://keepach=
angelog.com/en/1.0.0/)
=20
  - On Arm:
     - Ability to enable stack protector
+    - GICv3.1 eSPI support
=20
 ### Removed
  - On x86:
--=20
2.34.1


From xen-devel-bounces@lists.xenproject.org Tue Aug 26 14:42:57 2025
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Date: Tue, 26 Aug 2025 16:42:42 +0200
From: Anthony PERARD 
To: Petr =?utf-8?B?QmVuZcWh?= 
Cc: xen-devel@lists.xenproject.org,
	Anthony PERARD 
Subject: Re: [PATCH v5 1/4] tools: add sizeof_field and endof_field macros
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 <8dd6b217fbde427407113fedabb70f54d12aed61.1755987697.git.w1benny@gmail.com>
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On Sat, Aug 23, 2025 at 10:26:49PM +0000, Petr Beneš wrote:
> From: Petr Beneš 
> 
> * `sizeof_field` returns the size of a specific struct member
> * `endof_field` returns the offset to the end of the member within the struct
> 
> It will be useful in upcoming layout checks of SMBIOS structs.
> 
> Signed-off-by: Petr Beneš 

Acked-by: Anthony PERARD 

-- 
Anthony PERARD


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From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
Cc: Jan Beulich ,
	xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart
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On Tue, Aug 26, 2025 at 03:55:05PM +0200, Marek Marczykowski-Górecki wrote:
> On Tue, Aug 26, 2025 at 12:57:50PM +0200, Marek Marczykowski-Górecki wrote:
> > On Tue, Aug 26, 2025 at 10:28:56AM +0200, Roger Pau Monné wrote:
> > > On Tue, Aug 26, 2025 at 08:16:56AM +0200, Jan Beulich wrote:
> > > > On 26.08.2025 03:49, Marek Marczykowski-Górecki wrote:
> > > > > Hi,
> > > > > 
> > > > > I'm hitting an MSI-X issue after rebooting the domU. The symptoms are
> > > > > rather boring: on initial domU start the device (realtek eth card) works
> > > > > fine, but after domU restart, the link doesn't come up (there is no
> > > > > "Link is Up" message anymore). No errors from domU driver or Xen. I
> > > > > tracked it down to MSI-X - if I force INTx (via pci=nomsi on domU
> > > > > cmdline) it works fine. Convincing the driver to poll instead of waiting
> > > > > for an interrupt also workarounds the issue.
> > > > > 
> > > > > I noticed also some interrupts are not cleaned up on restart. The list
> > > > > of MSIs in 'Q' debug key output grows:
> > > > > 
> > > > >     (XEN) 0000:03:00.0 - d22 - node -1  - MSIs < 41 42 43 44 45 46 47 >
> > > > >     restart sys-net domU
> > > > >     (XEN) 0000:03:00.0 - d24 - node -1  - MSIs < 41 42 43 44 45 46 47 48 >
> > > > >     restart sys-net domU
> > > > >     (XEN) 0000:03:00.0 - d26 - node -1  - MSIs < 41 42 43 44 45 46 47 48 49 >
> > > > > 
> > > > > and 'M' output is:
> > > > > 
> > > > >     (XEN)  MSI-X   41 vec=b1 lowest  edge   assert  log lowest dest=00000001 mask=1/H /1
> > > > >     (XEN)  MSI-X   42 vec=b9 lowest  edge   assert  log lowest dest=00000004 mask=1/HG/1
> > > > >     (XEN)  MSI-X   43 vec=c1 lowest  edge   assert  log lowest dest=00000010 mask=1/HG/1
> > > > >     (XEN)  MSI-X   44 vec=d9 lowest  edge   assert  log lowest dest=00000001 mask=1/HG/1
> > > > >     (XEN)  MSI-X   45 vec=e1 lowest  edge   assert  log lowest dest=00000001 mask=1/HG/1
> > > > >     (XEN)  MSI-X   46 vec=e9 lowest  edge   assert  log lowest dest=00000040 mask=1/HG/1
> > > > >     (XEN)  MSI-X   47 vec=32 lowest  edge   assert  log lowest dest=00000004 mask=1/HG/1
> > > > >     (XEN)  MSI-X   48 vec=3a lowest  edge   assert  log lowest dest=00000040 mask=1/HG/1
> > > > >     (XEN)  MSI-X   49 vec=42 lowest  edge   assert  log lowest dest=00000010 mask=1/ G/1
> > > > > 
> > > > > And also, after starting and stopping the domU, `xl pci-assignable-remove 03:00.0`
> > > > > makes pciback to complain:
> > > > > 
> > > > >     [ 1180.919874] pciback 0000:03:00.0: xen_pciback: MSI-X release failed (-16)
> > > > > 
> > > > > This is all running on Xen 4.19.3, but I don't see much changes in this
> > > > > area since then.
> > > > > 
> > > > > Some more info collected at https://github.com/QubesOS/qubes-issues/issues/9335
> > > > > 
> > > > > My question is: what should be responsible for this cleanup on domain
> > > > > destroy? Xen, or maybe device model (which is QEMU in stubdomain here)?
> > > > 
> > > > The expectation is that qemu invokes the necessary cleanup, but of course ...
> > > > 
> > > > > I see some cleanup (apparently not enough) happening via QEMU when the
> > > > > domU driver is unloaded, but logically correct cleanup shouldn't depend
> > > > > on correct domU operation...
> > > > 
> > > > ... Xen may not make itself dependent upon either DomU or QEMU.
> > > 
> > > AFAICT free_domain_pirqs() called by arch_domain_destroy() should take
> > > care of unbinding and freeing pirqs (but obviously not in this case).
> > > Can you repeat the test with a debug=y hypervisor and post the
> > > resulting serial or dmesg here?  Some of the errors on those paths are
> > > printed with dprintk() and won't be visible unless using a Xen debug
> > > build.
> > 
> > Sure, will do.
> 
> Output collected during domU shutdown and subsequent startup (dom0 logs
> to Xen console here too):
> https://gist.github.com/marmarek/6dc3ac14d3ba840482e6361fcbd37c30
> 
> I don't see any errors there...

Hm, yes, I don't see any errors either.  Do you think you could
instrument unmap_domain_pirq() and figure out whether it gets called,
and if such call to unmap the PIRQ succeeds?

There's one silent error path in the return value of
xsm_unmap_domain_irq(), but that shouldn't be taken since the call to
unmap_domain_pirq() executed when destroying the domain is done with
d->is_dying == true.

> As for the domU-triggered cleanup, I just checked - if I unload the
> driver in domU before restarting, it works fine on subsequent startup.

Yeah, the unbind an unmap is then done by QEMU, and that seems to
work fine.  What doesn't seem to work fine is the cleanup done as part
of domain destroy.

Don't we have any Gitlab tests that do PCI passthrough?  Maybe those
don't do any domU resets?

Thanks, Roger.


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Feedback-ID: i1568416f:Fastmail
Date: Tue, 26 Aug 2025 16:52:17 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Jan Beulich ,
	xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart
Message-ID: 
References: 
 <2aafbace-3aa2-4f58-8f6c-2815cd2315ad@suse.com>
 
 
 
 
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Date: Tue, 26 Aug 2025 16:52:17 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Jan Beulich ,
	xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart

On Tue, Aug 26, 2025 at 04:47:50PM +0200, Roger Pau Monn=C3=A9 wrote:
> On Tue, Aug 26, 2025 at 03:55:05PM +0200, Marek Marczykowski-G=C3=B3recki=
 wrote:
> > On Tue, Aug 26, 2025 at 12:57:50PM +0200, Marek Marczykowski-G=C3=B3rec=
ki wrote:
> > > On Tue, Aug 26, 2025 at 10:28:56AM +0200, Roger Pau Monn=C3=A9 wrote:
> > > > On Tue, Aug 26, 2025 at 08:16:56AM +0200, Jan Beulich wrote:
> > > > > On 26.08.2025 03:49, Marek Marczykowski-G=C3=B3recki wrote:
> > > > > > Hi,
> > > > > >=20
> > > > > > I'm hitting an MSI-X issue after rebooting the domU. The sympto=
ms are
> > > > > > rather boring: on initial domU start the device (realtek eth ca=
rd) works
> > > > > > fine, but after domU restart, the link doesn't come up (there i=
s no
> > > > > > "Link is Up" message anymore). No errors from domU driver or Xe=
n. I
> > > > > > tracked it down to MSI-X - if I force INTx (via pci=3Dnomsi on =
domU
> > > > > > cmdline) it works fine. Convincing the driver to poll instead o=
f waiting
> > > > > > for an interrupt also workarounds the issue.
> > > > > >=20
> > > > > > I noticed also some interrupts are not cleaned up on restart. T=
he list
> > > > > > of MSIs in 'Q' debug key output grows:
> > > > > >=20
> > > > > >     (XEN) 0000:03:00.0 - d22 - node -1  - MSIs < 41 42 43 44 45=
 46 47 >
> > > > > >     restart sys-net domU
> > > > > >     (XEN) 0000:03:00.0 - d24 - node -1  - MSIs < 41 42 43 44 45=
 46 47 48 >
> > > > > >     restart sys-net domU
> > > > > >     (XEN) 0000:03:00.0 - d26 - node -1  - MSIs < 41 42 43 44 45=
 46 47 48 49 >
> > > > > >=20
> > > > > > and 'M' output is:
> > > > > >=20
> > > > > >     (XEN)  MSI-X   41 vec=3Db1 lowest  edge   assert  log lowes=
t dest=3D00000001 mask=3D1/H /1
> > > > > >     (XEN)  MSI-X   42 vec=3Db9 lowest  edge   assert  log lowes=
t dest=3D00000004 mask=3D1/HG/1
> > > > > >     (XEN)  MSI-X   43 vec=3Dc1 lowest  edge   assert  log lowes=
t dest=3D00000010 mask=3D1/HG/1
> > > > > >     (XEN)  MSI-X   44 vec=3Dd9 lowest  edge   assert  log lowes=
t dest=3D00000001 mask=3D1/HG/1
> > > > > >     (XEN)  MSI-X   45 vec=3De1 lowest  edge   assert  log lowes=
t dest=3D00000001 mask=3D1/HG/1
> > > > > >     (XEN)  MSI-X   46 vec=3De9 lowest  edge   assert  log lowes=
t dest=3D00000040 mask=3D1/HG/1
> > > > > >     (XEN)  MSI-X   47 vec=3D32 lowest  edge   assert  log lowes=
t dest=3D00000004 mask=3D1/HG/1
> > > > > >     (XEN)  MSI-X   48 vec=3D3a lowest  edge   assert  log lowes=
t dest=3D00000040 mask=3D1/HG/1
> > > > > >     (XEN)  MSI-X   49 vec=3D42 lowest  edge   assert  log lowes=
t dest=3D00000010 mask=3D1/ G/1
> > > > > >=20
> > > > > > And also, after starting and stopping the domU, `xl pci-assigna=
ble-remove 03:00.0`
> > > > > > makes pciback to complain:
> > > > > >=20
> > > > > >     [ 1180.919874] pciback 0000:03:00.0: xen_pciback: MSI-X rel=
ease failed (-16)
> > > > > >=20
> > > > > > This is all running on Xen 4.19.3, but I don't see much changes=
 in this
> > > > > > area since then.
> > > > > >=20
> > > > > > Some more info collected at https://github.com/QubesOS/qubes-is=
sues/issues/9335
> > > > > >=20
> > > > > > My question is: what should be responsible for this cleanup on =
domain
> > > > > > destroy? Xen, or maybe device model (which is QEMU in stubdomai=
n here)?
> > > > >=20
> > > > > The expectation is that qemu invokes the necessary cleanup, but o=
f course ...
> > > > >=20
> > > > > > I see some cleanup (apparently not enough) happening via QEMU w=
hen the
> > > > > > domU driver is unloaded, but logically correct cleanup shouldn'=
t depend
> > > > > > on correct domU operation...
> > > > >=20
> > > > > ... Xen may not make itself dependent upon either DomU or QEMU.
> > > >=20
> > > > AFAICT free_domain_pirqs() called by arch_domain_destroy() should t=
ake
> > > > care of unbinding and freeing pirqs (but obviously not in this case=
).
> > > > Can you repeat the test with a debug=3Dy hypervisor and post the
> > > > resulting serial or dmesg here?  Some of the errors on those paths =
are
> > > > printed with dprintk() and won't be visible unless using a Xen debug
> > > > build.
> > >=20
> > > Sure, will do.
> >=20
> > Output collected during domU shutdown and subsequent startup (dom0 logs
> > to Xen console here too):
> > https://gist.github.com/marmarek/6dc3ac14d3ba840482e6361fcbd37c30
> >=20
> > I don't see any errors there...
>=20
> Hm, yes, I don't see any errors either.  Do you think you could
> instrument unmap_domain_pirq() and figure out whether it gets called,
> and if such call to unmap the PIRQ succeeds?

Sure, now that I know where to look at, I'll try to find out what goes
wrong.

> There's one silent error path in the return value of
> xsm_unmap_domain_irq(), but that shouldn't be taken since the call to
> unmap_domain_pirq() executed when destroying the domain is done with
> d->is_dying =3D=3D true.
>=20
> > As for the domU-triggered cleanup, I just checked - if I unload the
> > driver in domU before restarting, it works fine on subsequent startup.
>=20
> Yeah, the unbind an unmap is then done by QEMU, and that seems to
> work fine.  What doesn't seem to work fine is the cleanup done as part
> of domain destroy.
>=20
> Don't we have any Gitlab tests that do PCI passthrough?  Maybe those
> don't do any domU resets?

Yeah, it's a single boot and that's it. I can improve that (and double
check if MSI-X is covered too).

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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	xen-devel@lists.xenproject.org
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Rework xen_pv_domain() to no longer use the xen_domain_type variable,
but the artificial X86_FEATURE_XENPV cpu feature.

On non-x86 architectures xen_pv_domain() can be defined as "0".

This has the advantage that a kernel not built with CONFIG_XEN_PV
will be smaller due to dead code elimination.

Set the X86_FEATURE_XENPV feature very early, as xen_pv_domain() is
used rather early, too.

Signed-off-by: Juergen Gross 
---
 arch/x86/xen/enlighten_pv.c | 2 +-
 include/xen/xen.h           | 9 ++++++++-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index 26bbaf4b7330..4806cc28d7ca 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -382,7 +382,6 @@ static bool __init xen_check_xsave(void)
 
 static void __init xen_init_capabilities(void)
 {
-	setup_force_cpu_cap(X86_FEATURE_XENPV);
 	setup_clear_cpu_cap(X86_FEATURE_DCA);
 	setup_clear_cpu_cap(X86_FEATURE_APERFMPERF);
 	setup_clear_cpu_cap(X86_FEATURE_MTRR);
@@ -1402,6 +1401,7 @@ asmlinkage __visible void __init xen_start_kernel(struct start_info *si)
 			JMP32_INSN_SIZE);
 
 	xen_domain_type = XEN_PV_DOMAIN;
+	setup_force_cpu_cap(X86_FEATURE_XENPV);
 	xen_start_flags = xen_start_info->flags;
 	/* Interrupts are guaranteed to be off initially. */
 	early_boot_irqs_disabled = true;
diff --git a/include/xen/xen.h b/include/xen/xen.h
index a1e5b3f18d69..61854e3f2837 100644
--- a/include/xen/xen.h
+++ b/include/xen/xen.h
@@ -22,8 +22,15 @@ extern bool xen_pvh;
 #define xen_pvh			0
 #endif
 
+#ifdef CONFIG_X86
+#include 
+
+#define xen_pv_domain()		(cpu_feature_enabled(X86_FEATURE_XENPV))
+#else
+#define xen_pv_domain()		0
+#endif
+
 #define xen_domain()		(xen_domain_type != XEN_NATIVE)
-#define xen_pv_domain()		(xen_domain_type == XEN_PV_DOMAIN)
 #define xen_hvm_domain()	(xen_domain_type == XEN_HVM_DOMAIN)
 #define xen_pvh_domain()	(xen_pvh)
 
-- 
2.43.0



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From: Juergen Gross 
To: linux-kernel@vger.kernel.org,
	x86@kernel.org
Cc: Juergen Gross ,
	Boris Ostrovsky ,
	Thomas Gleixner ,
	Ingo Molnar ,
	Borislav Petkov ,
	Dave Hansen ,
	"H. Peter Anvin" ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	xen-devel@lists.xenproject.org
Subject: [PATCH 0/3] xen: use X86_FEATURE_XENPV for PV specific code
Date: Tue, 26 Aug 2025 16:56:05 +0200
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Instead of using a global variable with the current guest type or the
XENFEAT_auto_translated_physmap Xen feature, use the already existing
X86_FEATURE_XENPV for guarding PV mode specific code.

This has the advantage of compile time code elimination in case of the
kernel having been configured without CONFIG_XEN_PV, and the usage of
static-keys for selecting the correct code path otherwise.

Juergen Gross (3):
  xen: rework xen_pv_domain()
  xen: replace XENFEAT_auto_translated_physmap with xen_pv_domain()
  drivers/xen/gntdev: use xen_pv_domain() instead of cached value

 arch/x86/include/asm/xen/page.h    | 14 ++++++-------
 arch/x86/xen/enlighten_pv.c        |  2 +-
 arch/x86/xen/mmu.c                 |  2 +-
 arch/x86/xen/p2m.c                 |  4 ++--
 drivers/xen/balloon.c              |  4 ++--
 drivers/xen/gntdev-dmabuf.c        |  7 +++----
 drivers/xen/gntdev-dmabuf.h        |  2 +-
 drivers/xen/gntdev.c               | 33 +++++++++++++-----------------
 drivers/xen/grant-table.c          |  6 +++---
 drivers/xen/privcmd.c              | 14 ++++++-------
 drivers/xen/unpopulated-alloc.c    |  4 ++--
 drivers/xen/xenbus/xenbus_client.c |  2 +-
 include/xen/grant_table.h          |  4 ++--
 include/xen/mem-reservation.h      |  4 ++--
 include/xen/xen-ops.h              |  7 ++++---
 include/xen/xen.h                  |  9 +++++++-
 16 files changed, 59 insertions(+), 59 deletions(-)

-- 
2.43.0



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From: Juergen Gross 
To: linux-kernel@vger.kernel.org,
	x86@kernel.org
Cc: Juergen Gross ,
	Boris Ostrovsky ,
	Thomas Gleixner ,
	Ingo Molnar ,
	Borislav Petkov ,
	Dave Hansen ,
	"H. Peter Anvin" ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	xen-devel@lists.xenproject.org
Subject: [PATCH 2/3] xen: replace XENFEAT_auto_translated_physmap with xen_pv_domain()
Date: Tue, 26 Aug 2025 16:56:07 +0200
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Instead of testing the XENFEAT_auto_translated_physmap feature, just
use !xen_pv_domain() which is equivalent.

This has the advantage that a kernel not built with CONFIG_XEN_PV
will be smaller due to dead code elimination.

Signed-off-by: Juergen Gross 
---
 arch/x86/include/asm/xen/page.h    | 14 +++++++-------
 arch/x86/xen/mmu.c                 |  2 +-
 arch/x86/xen/p2m.c                 |  4 ++--
 drivers/xen/balloon.c              |  4 ++--
 drivers/xen/gntdev.c               |  2 +-
 drivers/xen/grant-table.c          |  6 +++---
 drivers/xen/privcmd.c              | 14 ++++++--------
 drivers/xen/unpopulated-alloc.c    |  4 ++--
 drivers/xen/xenbus/xenbus_client.c |  2 +-
 include/xen/grant_table.h          |  4 ++--
 include/xen/mem-reservation.h      |  4 ++--
 include/xen/xen-ops.h              |  7 ++++---
 12 files changed, 33 insertions(+), 34 deletions(-)

diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h
index 85e63d58c074..59f642a94b9d 100644
--- a/arch/x86/include/asm/xen/page.h
+++ b/arch/x86/include/asm/xen/page.h
@@ -12,9 +12,9 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
-#include 
 
 /* Xen machine address */
 typedef struct xmaddr {
@@ -162,7 +162,7 @@ static inline unsigned long pfn_to_mfn(unsigned long pfn)
 	 * pfn_to_mfn. This will have to be removed when we figured
 	 * out which call.
 	 */
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return pfn;
 
 	mfn = __pfn_to_mfn(pfn);
@@ -175,7 +175,7 @@ static inline unsigned long pfn_to_mfn(unsigned long pfn)
 
 static inline int phys_to_machine_mapping_valid(unsigned long pfn)
 {
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return 1;
 
 	return __pfn_to_mfn(pfn) != INVALID_P2M_ENTRY;
@@ -210,7 +210,7 @@ static inline unsigned long mfn_to_pfn(unsigned long mfn)
 	 * gfn_to_pfn. This will have to be removed when we figure
 	 * out which call.
 	 */
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return mfn;
 
 	pfn = mfn_to_pfn_no_overrides(mfn);
@@ -242,7 +242,7 @@ static inline xpaddr_t machine_to_phys(xmaddr_t machine)
 /* Pseudo-physical <-> Guest conversion */
 static inline unsigned long pfn_to_gfn(unsigned long pfn)
 {
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return pfn;
 	else
 		return pfn_to_mfn(pfn);
@@ -250,7 +250,7 @@ static inline unsigned long pfn_to_gfn(unsigned long pfn)
 
 static inline unsigned long gfn_to_pfn(unsigned long gfn)
 {
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return gfn;
 	else
 		return mfn_to_pfn(gfn);
@@ -284,7 +284,7 @@ static inline unsigned long bfn_to_local_pfn(unsigned long mfn)
 {
 	unsigned long pfn;
 
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return mfn;
 
 	pfn = mfn_to_pfn(mfn);
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index c4c479373249..3be45bf4bc79 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -41,7 +41,7 @@ EXPORT_SYMBOL_GPL(arbitrary_virt_to_machine);
 int xen_unmap_domain_gfn_range(struct vm_area_struct *vma,
 			       int nr, struct page **pages)
 {
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return xen_xlate_unmap_gfn_range(vma, nr, pages);
 
 	if (!pages)
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c
index 56914e21e303..2dd12b61a230 100644
--- a/arch/x86/xen/p2m.c
+++ b/arch/x86/xen/p2m.c
@@ -686,7 +686,7 @@ int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops,
 	int i, ret = 0;
 	pte_t *pte;
 
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return 0;
 
 	if (kmap_ops) {
@@ -769,7 +769,7 @@ int clear_foreign_p2m_mapping(struct gnttab_unmap_grant_ref *unmap_ops,
 {
 	int i, ret = 0;
 
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return 0;
 
 	for (i = 0; i < count; i++) {
diff --git a/drivers/xen/balloon.c b/drivers/xen/balloon.c
index 2de37dcd7556..49c3f9926394 100644
--- a/drivers/xen/balloon.c
+++ b/drivers/xen/balloon.c
@@ -302,7 +302,7 @@ static enum bp_state reserve_additional_memory(void)
          * are not restored since this region is now known not to
          * conflict with any devices.
          */ 
-	if (!xen_feature(XENFEAT_auto_translated_physmap)) {
+	if (xen_pv_domain()) {
 		unsigned long pfn, i;
 
 		pfn = PFN_DOWN(resource->start);
@@ -626,7 +626,7 @@ int xen_alloc_ballooned_pages(unsigned int nr_pages, struct page **pages)
 			 */
 			BUILD_BUG_ON(XEN_PAGE_SIZE != PAGE_SIZE);
 
-			if (!xen_feature(XENFEAT_auto_translated_physmap)) {
+			if (xen_pv_domain()) {
 				ret = xen_alloc_p2m_entry(page_to_pfn(page));
 				if (ret < 0)
 					goto out_undo;
diff --git a/drivers/xen/gntdev.c b/drivers/xen/gntdev.c
index 1f2160765618..74491967f2ae 100644
--- a/drivers/xen/gntdev.c
+++ b/drivers/xen/gntdev.c
@@ -1183,7 +1183,7 @@ static int __init gntdev_init(void)
 	if (!xen_domain())
 		return -ENODEV;
 
-	use_ptemod = !xen_feature(XENFEAT_auto_translated_physmap);
+	use_ptemod = xen_pv_domain();
 
 	err = misc_register(&gntdev_miscdev);
 	if (err != 0) {
diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c
index 04a6b470b15d..478d2ad725ac 100644
--- a/drivers/xen/grant-table.c
+++ b/drivers/xen/grant-table.c
@@ -1449,7 +1449,7 @@ static int gnttab_map(unsigned int start_idx, unsigned int end_idx)
 	unsigned int nr_gframes = end_idx + 1;
 	int rc;
 
-	if (xen_feature(XENFEAT_auto_translated_physmap)) {
+	if (!xen_pv_domain()) {
 		struct xen_add_to_physmap xatp;
 		unsigned int i = end_idx;
 		rc = 0;
@@ -1570,7 +1570,7 @@ static int gnttab_setup(void)
 	if (max_nr_gframes < nr_grant_frames)
 		return -ENOSYS;
 
-	if (xen_feature(XENFEAT_auto_translated_physmap) && gnttab_shared.addr == NULL) {
+	if (!xen_pv_domain() && gnttab_shared.addr == NULL) {
 		gnttab_shared.addr = xen_auto_xlat_grant_frames.vaddr;
 		if (gnttab_shared.addr == NULL) {
 			pr_warn("gnttab share frames is not mapped!\n");
@@ -1588,7 +1588,7 @@ int gnttab_resume(void)
 
 int gnttab_suspend(void)
 {
-	if (!xen_feature(XENFEAT_auto_translated_physmap))
+	if (xen_pv_domain())
 		gnttab_interface->unmap_frames();
 	return 0;
 }
diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
index 13a10f3294a8..f52a457b302d 100644
--- a/drivers/xen/privcmd.c
+++ b/drivers/xen/privcmd.c
@@ -271,7 +271,7 @@ static long privcmd_ioctl_mmap(struct file *file, void __user *udata)
 	struct mmap_gfn_state state;
 
 	/* We only support privcmd_ioctl_mmap_batch for non-auto-translated. */
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return -ENOSYS;
 
 	if (copy_from_user(&mmapcmd, udata, sizeof(mmapcmd)))
@@ -353,7 +353,7 @@ static int mmap_batch_fn(void *data, int nr, void *state)
 	struct page **cur_pages = NULL;
 	int ret;
 
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		cur_pages = &pages[st->index];
 
 	BUG_ON(nr < 0);
@@ -535,7 +535,7 @@ static long privcmd_ioctl_mmap_batch(
 			ret = -EINVAL;
 			goto out_unlock;
 		}
-		if (xen_feature(XENFEAT_auto_translated_physmap)) {
+		if (!xen_pv_domain()) {
 			ret = alloc_empty_pages(vma, nr_pages);
 			if (ret < 0)
 				goto out_unlock;
@@ -779,8 +779,7 @@ static long privcmd_ioctl_mmap_resource(struct file *file,
 		goto out;
 	}
 
-	if (IS_ENABLED(CONFIG_XEN_AUTO_XLATE) &&
-	    xen_feature(XENFEAT_auto_translated_physmap)) {
+	if (IS_ENABLED(CONFIG_XEN_AUTO_XLATE) && !xen_pv_domain()) {
 		unsigned int nr = DIV_ROUND_UP(kdata.num, XEN_PFN_PER_PAGE);
 		struct page **pages;
 		unsigned int i;
@@ -811,8 +810,7 @@ static long privcmd_ioctl_mmap_resource(struct file *file,
 	if (rc)
 		goto out;
 
-	if (IS_ENABLED(CONFIG_XEN_AUTO_XLATE) &&
-	    xen_feature(XENFEAT_auto_translated_physmap)) {
+	if (IS_ENABLED(CONFIG_XEN_AUTO_XLATE) && !xen_pv_domain()) {
 		rc = xen_remap_vma_range(vma, kdata.addr, kdata.num << PAGE_SHIFT);
 	} else {
 		unsigned int domid =
@@ -1591,7 +1589,7 @@ static void privcmd_close(struct vm_area_struct *vma)
 	int numgfns = (vma->vm_end - vma->vm_start) >> XEN_PAGE_SHIFT;
 	int rc;
 
-	if (!xen_feature(XENFEAT_auto_translated_physmap) || !numpgs || !pages)
+	if (xen_pv_domain() || !numpgs || !pages)
 		return;
 
 	rc = xen_unmap_domain_gfn_range(vma, numgfns, pages);
diff --git a/drivers/xen/unpopulated-alloc.c b/drivers/xen/unpopulated-alloc.c
index a39f2d36dd9c..d6fc2aefe264 100644
--- a/drivers/xen/unpopulated-alloc.c
+++ b/drivers/xen/unpopulated-alloc.c
@@ -105,7 +105,7 @@ static int fill_list(unsigned int nr_pages)
          * are not restored since this region is now known not to
          * conflict with any devices.
          */
-	if (!xen_feature(XENFEAT_auto_translated_physmap)) {
+	if (xen_pv_domain()) {
 		xen_pfn_t pfn = PFN_DOWN(res->start);
 
 		for (i = 0; i < alloc_pages; i++) {
@@ -184,7 +184,7 @@ int xen_alloc_unpopulated_pages(unsigned int nr_pages, struct page **pages)
 		pages[i] = pg;
 
 #ifdef CONFIG_XEN_HAVE_PVMMU
-		if (!xen_feature(XENFEAT_auto_translated_physmap)) {
+		if (xen_pv_domain()) {
 			ret = xen_alloc_p2m_entry(page_to_pfn(pg));
 			if (ret < 0) {
 				unsigned int j;
diff --git a/drivers/xen/xenbus/xenbus_client.c b/drivers/xen/xenbus/xenbus_client.c
index e73ec225d4a6..2dc874fb5506 100644
--- a/drivers/xen/xenbus/xenbus_client.c
+++ b/drivers/xen/xenbus/xenbus_client.c
@@ -955,7 +955,7 @@ static const struct xenbus_ring_ops ring_ops_hvm = {
 void __init xenbus_ring_ops_init(void)
 {
 #ifdef CONFIG_XEN_PV
-	if (!xen_feature(XENFEAT_auto_translated_physmap))
+	if (xen_pv_domain())
 		ring_ops = &ring_ops_pv;
 	else
 #endif
diff --git a/include/xen/grant_table.h b/include/xen/grant_table.h
index e279be353e3f..69ac6d80a006 100644
--- a/include/xen/grant_table.h
+++ b/include/xen/grant_table.h
@@ -164,7 +164,7 @@ gnttab_set_map_op(struct gnttab_map_grant_ref *map, phys_addr_t addr,
 {
 	if (flags & GNTMAP_contains_pte)
 		map->host_addr = addr;
-	else if (xen_feature(XENFEAT_auto_translated_physmap))
+	else if (!xen_pv_domain())
 		map->host_addr = __pa(addr);
 	else
 		map->host_addr = addr;
@@ -181,7 +181,7 @@ gnttab_set_unmap_op(struct gnttab_unmap_grant_ref *unmap, phys_addr_t addr,
 {
 	if (flags & GNTMAP_contains_pte)
 		unmap->host_addr = addr;
-	else if (xen_feature(XENFEAT_auto_translated_physmap))
+	else if (!xen_pv_domain())
 		unmap->host_addr = __pa(addr);
 	else
 		unmap->host_addr = addr;
diff --git a/include/xen/mem-reservation.h b/include/xen/mem-reservation.h
index a2ab516fcd2c..3cbe3df0dfd4 100644
--- a/include/xen/mem-reservation.h
+++ b/include/xen/mem-reservation.h
@@ -39,7 +39,7 @@ static inline void xenmem_reservation_va_mapping_update(unsigned long count,
 							xen_pfn_t *frames)
 {
 #ifdef CONFIG_XEN_HAVE_PVMMU
-	if (!xen_feature(XENFEAT_auto_translated_physmap))
+	if (xen_pv_domain())
 		__xenmem_reservation_va_mapping_update(count, pages, frames);
 #endif
 }
@@ -48,7 +48,7 @@ static inline void xenmem_reservation_va_mapping_reset(unsigned long count,
 						       struct page **pages)
 {
 #ifdef CONFIG_XEN_HAVE_PVMMU
-	if (!xen_feature(XENFEAT_auto_translated_physmap))
+	if (xen_pv_domain())
 		__xenmem_reservation_va_mapping_reset(count, pages);
 #endif
 }
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index 9e2a769b0d96..496e6013c689 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -116,7 +117,7 @@ static inline int xen_remap_domain_gfn_array(struct vm_area_struct *vma,
 					     unsigned int domid,
 					     struct page **pages)
 {
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return xen_xlate_remap_gfn_array(vma, addr, gfn, nr, err_ptr,
 						 prot, domid, pages);
 
@@ -150,7 +151,7 @@ static inline int xen_remap_domain_mfn_array(struct vm_area_struct *vma,
 					     int nr, int *err_ptr,
 					     pgprot_t prot, unsigned int domid)
 {
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return -EOPNOTSUPP;
 
 	return xen_remap_pfn(vma, addr, mfn, nr, err_ptr, prot, domid,
@@ -175,7 +176,7 @@ static inline int xen_remap_domain_gfn_range(struct vm_area_struct *vma,
 					     pgprot_t prot, unsigned int domid,
 					     struct page **pages)
 {
-	if (xen_feature(XENFEAT_auto_translated_physmap))
+	if (!xen_pv_domain())
 		return -EOPNOTSUPP;
 
 	return xen_remap_pfn(vma, addr, &gfn, nr, NULL, prot, domid, false);
-- 
2.43.0



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From: Juergen Gross 
To: linux-kernel@vger.kernel.org
Cc: Juergen Gross ,
	Stefano Stabellini ,
	Oleksandr Tyshchenko ,
	xen-devel@lists.xenproject.org
Subject: [PATCH 3/3] drivers/xen/gntdev: use xen_pv_domain() instead of cached value
Date: Tue, 26 Aug 2025 16:56:08 +0200
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Eliminate the use_ptemod variable by replacing its use cases with
xen_pv_domain().

Instead of passing the xen_pv_domain() return value to
gntdev_ioctl_dmabuf_exp_from_refs(), use xen_pv_domain() in that
function.

Signed-off-by: Juergen Gross 
---
 drivers/xen/gntdev-dmabuf.c |  7 +++----
 drivers/xen/gntdev-dmabuf.h |  2 +-
 drivers/xen/gntdev.c        | 33 ++++++++++++++-------------------
 3 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/drivers/xen/gntdev-dmabuf.c b/drivers/xen/gntdev-dmabuf.c
index 82855105ab85..550980dd3b0b 100644
--- a/drivers/xen/gntdev-dmabuf.c
+++ b/drivers/xen/gntdev-dmabuf.c
@@ -720,16 +720,15 @@ static void dmabuf_imp_release_all(struct gntdev_dmabuf_priv *priv)
 
 /* DMA buffer IOCTL support. */
 
-long gntdev_ioctl_dmabuf_exp_from_refs(struct gntdev_priv *priv, int use_ptemod,
+long gntdev_ioctl_dmabuf_exp_from_refs(struct gntdev_priv *priv,
 				       struct ioctl_gntdev_dmabuf_exp_from_refs __user *u)
 {
 	struct ioctl_gntdev_dmabuf_exp_from_refs op;
 	u32 *refs;
 	long ret;
 
-	if (use_ptemod) {
-		pr_debug("Cannot provide dma-buf: use_ptemode %d\n",
-			 use_ptemod);
+	if (xen_pv_domain()) {
+		pr_debug("Cannot provide dma-buf in a PV domain\n");
 		return -EINVAL;
 	}
 
diff --git a/drivers/xen/gntdev-dmabuf.h b/drivers/xen/gntdev-dmabuf.h
index 3d9b9cf9d5a1..9adf96ac74d3 100644
--- a/drivers/xen/gntdev-dmabuf.h
+++ b/drivers/xen/gntdev-dmabuf.h
@@ -18,7 +18,7 @@ struct gntdev_dmabuf_priv *gntdev_dmabuf_init(struct file *filp);
 
 void gntdev_dmabuf_fini(struct gntdev_dmabuf_priv *priv);
 
-long gntdev_ioctl_dmabuf_exp_from_refs(struct gntdev_priv *priv, int use_ptemod,
+long gntdev_ioctl_dmabuf_exp_from_refs(struct gntdev_priv *priv,
 				       struct ioctl_gntdev_dmabuf_exp_from_refs __user *u);
 
 long gntdev_ioctl_dmabuf_exp_wait_released(struct gntdev_priv *priv,
diff --git a/drivers/xen/gntdev.c b/drivers/xen/gntdev.c
index 74491967f2ae..91ba5078c9d9 100644
--- a/drivers/xen/gntdev.c
+++ b/drivers/xen/gntdev.c
@@ -73,9 +73,6 @@ module_param(limit, uint, 0644);
 MODULE_PARM_DESC(limit,
 	"Maximum number of grants that may be mapped by one mapping request");
 
-/* True in PV mode, false otherwise */
-static int use_ptemod;
-
 static void unmap_grant_pages(struct gntdev_grant_map *map,
 			      int offset, int pages);
 
@@ -163,7 +160,7 @@ struct gntdev_grant_map *gntdev_alloc_map(struct gntdev_priv *priv, int count,
 	    NULL == add->pages     ||
 	    NULL == add->being_removed)
 		goto err;
-	if (use_ptemod) {
+	if (xen_pv_domain()) {
 		add->kmap_ops   = kvmalloc_array(count, sizeof(add->kmap_ops[0]),
 						 GFP_KERNEL);
 		add->kunmap_ops = kvmalloc_array(count, sizeof(add->kunmap_ops[0]),
@@ -211,7 +208,7 @@ struct gntdev_grant_map *gntdev_alloc_map(struct gntdev_priv *priv, int count,
 		add->grants[i].ref = INVALID_GRANT_REF;
 		add->map_ops[i].handle = INVALID_GRANT_HANDLE;
 		add->unmap_ops[i].handle = INVALID_GRANT_HANDLE;
-		if (use_ptemod) {
+		if (xen_pv_domain()) {
 			add->kmap_ops[i].handle = INVALID_GRANT_HANDLE;
 			add->kunmap_ops[i].handle = INVALID_GRANT_HANDLE;
 		}
@@ -268,7 +265,7 @@ void gntdev_put_map(struct gntdev_priv *priv, struct gntdev_grant_map *map)
 	if (!refcount_dec_and_test(&map->users))
 		return;
 
-	if (map->pages && !use_ptemod) {
+	if (map->pages && !xen_pv_domain()) {
 		/*
 		 * Increment the reference count.  This ensures that the
 		 * subsequent call to unmap_grant_pages() will not wind up
@@ -298,7 +295,7 @@ void gntdev_put_map(struct gntdev_priv *priv, struct gntdev_grant_map *map)
 		 */
 	}
 
-	if (use_ptemod && map->notifier_init)
+	if (xen_pv_domain() && map->notifier_init)
 		mmu_interval_notifier_remove(&map->notifier);
 
 	if (map->notify.flags & UNMAP_NOTIFY_SEND_EVENT) {
@@ -334,7 +331,7 @@ int gntdev_map_grant_pages(struct gntdev_grant_map *map)
 	size_t alloced = 0;
 	int i, err = 0;
 
-	if (!use_ptemod) {
+	if (!xen_pv_domain()) {
 		/* Note: it could already be mapped */
 		if (map->map_ops[0].handle != INVALID_GRANT_HANDLE)
 			return 0;
@@ -389,7 +386,7 @@ int gntdev_map_grant_pages(struct gntdev_grant_map *map)
 		if (map->flags & GNTMAP_device_map)
 			map->unmap_ops[i].dev_bus_addr = map->map_ops[i].dev_bus_addr;
 
-		if (use_ptemod) {
+		if (xen_pv_domain()) {
 			if (map->kmap_ops[i].status == GNTST_okay) {
 				alloced++;
 				map->kunmap_ops[i].handle = map->kmap_ops[i].handle;
@@ -421,7 +418,7 @@ static void __unmap_grant_pages_done(int result,
 			map->unmap_ops[offset+i].handle,
 			map->unmap_ops[offset+i].status);
 		map->unmap_ops[offset+i].handle = INVALID_GRANT_HANDLE;
-		if (use_ptemod) {
+		if (xen_pv_domain()) {
 			if (map->kunmap_ops[offset + i].status == GNTST_okay &&
 			    map->kunmap_ops[offset + i].handle != INVALID_GRANT_HANDLE)
 				successful_unmaps++;
@@ -464,7 +461,7 @@ static void __unmap_grant_pages(struct gntdev_grant_map *map, int offset,
 	}
 
 	map->unmap_data.unmap_ops = map->unmap_ops + offset;
-	map->unmap_data.kunmap_ops = use_ptemod ? map->kunmap_ops + offset : NULL;
+	map->unmap_data.kunmap_ops = xen_pv_domain() ? map->kunmap_ops + offset : NULL;
 	map->unmap_data.pages = map->pages + offset;
 	map->unmap_data.count = pages;
 	map->unmap_data.done = __unmap_grant_pages_done;
@@ -1039,7 +1036,7 @@ static long gntdev_ioctl(struct file *flip,
 
 #ifdef CONFIG_XEN_GNTDEV_DMABUF
 	case IOCTL_GNTDEV_DMABUF_EXP_FROM_REFS:
-		return gntdev_ioctl_dmabuf_exp_from_refs(priv, use_ptemod, ptr);
+		return gntdev_ioctl_dmabuf_exp_from_refs(priv, ptr);
 
 	case IOCTL_GNTDEV_DMABUF_EXP_WAIT_RELEASED:
 		return gntdev_ioctl_dmabuf_exp_wait_released(priv, ptr);
@@ -1086,7 +1083,7 @@ static int gntdev_mmap(struct file *flip, struct vm_area_struct *vma)
 
 	vm_flags_set(vma, VM_DONTEXPAND | VM_DONTDUMP | VM_MIXEDMAP);
 
-	if (use_ptemod)
+	if (xen_pv_domain())
 		vm_flags_set(vma, VM_DONTCOPY);
 
 	vma->vm_private_data = map;
@@ -1102,7 +1099,7 @@ static int gntdev_mmap(struct file *flip, struct vm_area_struct *vma)
 
 	map->pages_vm_start = vma->vm_start;
 
-	if (use_ptemod) {
+	if (xen_pv_domain()) {
 		err = mmu_interval_notifier_insert_locked(
 			&map->notifier, vma->vm_mm, vma->vm_start,
 			vma->vm_end - vma->vm_start, &gntdev_mmu_ops);
@@ -1113,7 +1110,7 @@ static int gntdev_mmap(struct file *flip, struct vm_area_struct *vma)
 	}
 	mutex_unlock(&priv->lock);
 
-	if (use_ptemod) {
+	if (xen_pv_domain()) {
 		/*
 		 * gntdev takes the address of the PTE in find_grant_ptes() and
 		 * passes it to the hypervisor in gntdev_map_grant_pages(). The
@@ -1139,7 +1136,7 @@ static int gntdev_mmap(struct file *flip, struct vm_area_struct *vma)
 	if (err)
 		goto out_put_map;
 
-	if (!use_ptemod) {
+	if (!xen_pv_domain()) {
 		err = vm_map_pages_zero(vma, map->pages, map->count);
 		if (err)
 			goto out_put_map;
@@ -1154,7 +1151,7 @@ static int gntdev_mmap(struct file *flip, struct vm_area_struct *vma)
 out_unlock_put:
 	mutex_unlock(&priv->lock);
 out_put_map:
-	if (use_ptemod)
+	if (xen_pv_domain())
 		unmap_grant_pages(map, 0, map->count);
 	gntdev_put_map(priv, map);
 	return err;
@@ -1183,8 +1180,6 @@ static int __init gntdev_init(void)
 	if (!xen_domain())
 		return -ENODEV;
 
-	use_ptemod = xen_pv_domain();
-
 	err = misc_register(&gntdev_miscdev);
 	if (err != 0) {
 		pr_err("Could not register gntdev device\n");
-- 
2.43.0



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Date: Tue, 26 Aug 2025 18:01:55 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v5 12/12] xen/arm: Suspend/resume IOMMU on Xen
 suspend/resume
To: Mykola Kvach ,
 Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" ,
 Oleksandr Tyshchenko ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel , Mykola Kvach ,
 Oleksandr Andrushchenko 
References: 
 <821e0762f64c8b33260a59c672eabf1da5fb4dd4.1754943875.git.mykola_kvach@epam.com>
 <87frdh7wk0.fsf@epam.com>
 
Content-Language: en-US
From: Oleksandr Tyshchenko 
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Content-Type: text/plain; charset=UTF-8; format=flowed
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On 26.08.25 16:42, Mykola Kvach wrote:

Hello Mykola, Volodymyr


> Hi Volodymyr,
> 
> On Sat, Aug 23, 2025 at 8:55 PM Volodymyr Babchuk
>  wrote:
>>
>> Hi,
>>
>> Mykola Kvach  writes:
>>
>>> From: Oleksandr Tyshchenko 
>>>
>>> This is done using generic iommu_suspend/resume functions that cause
>>> IOMMU driver specific suspend/resume handlers to be called for enabled
>>> IOMMU (if one has suspend/resume driver handlers implemented).
>>>
>>> These handlers work only when IPMMU-VMSA is used; otherwise,
>>> we return an error during system suspend requests.
>>>
>>> Signed-off-by: Oleksandr Tyshchenko 
>>> Signed-off-by: Mykola Kvach 
>>> Tested-by: Oleksandr Andrushchenko 

I think, the Tested-by here should be dropped. A lot of time has passed 
since Oleksandr provided the tag, and the code has changed a bit (I am 
afraid, the tag is now stale).


>>> ---
>>>   xen/arch/arm/suspend.c | 21 +++++++++++++++++++++
>>>   1 file changed, 21 insertions(+)
>>>
>>> diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
>>> index b5398e5ca6..cb86426ebd 100644
>>> --- a/xen/arch/arm/suspend.c
>>> +++ b/xen/arch/arm/suspend.c
>>> @@ -4,6 +4,7 @@
>>>   #include 
>>>   #include 
>>>   #include 
>>> +#include 
>>>   #include 
>>>   #include 
>>>
>>> @@ -49,6 +50,13 @@ static long system_suspend(void *data)
>>>
>>>       time_suspend();
>>>
>>> +    status = iommu_suspend();
>>> +    if ( status )
>>> +    {
>>> +        system_state = SYS_STATE_resume;
>>> +        goto resume_time;
>>> +    }
>>> +
>>>       local_irq_save(flags);
>>>       status = gic_suspend();
>>>       if ( status )
>>> @@ -105,6 +113,10 @@ static long system_suspend(void *data)
>>>
>>>    resume_irqs:
>>>       local_irq_restore(flags);
>>> +
>>> +    iommu_resume();
>>> +
>>> + resume_time:
>>>       time_resume();
>>>
>>>    resume_nonboot_cpus:
>>> @@ -140,6 +152,15 @@ int host_system_suspend(void)
>>>           return -ENOSYS;
>>>       }
>>>
>>> +    /* TODO: drop check once suspend/resume support for SMMU is implemented */
>>> +#ifndef CONFIG_IPMMU_VMSA

The original patch did not seem to have this check...

>>
>> This check is meaningless, as you can have CONFIG_IPMMU_VMSA enabled
>> along with CONFIG_ARM_SMMU on a system with SMMU. I think it is enough
>> that iommu_suspend() will fail during system_suspend(), isn't it?
> 
> Not exactly. In the case of SMMU, we don’t have valid iommu_suspend/iommu_resume
> handlers. So it’s possible to have CONFIG_ARM_SMMU enabled and iommu_enabled
> set, but without the appropriate suspend handlers. This could lead to
> a crash during
> system_suspend().

  ... I also have doubts whether this check is needed (at least in its 
current shape). Xen has 2 SMMU drivers at the moment. Lets imagine that 
S2R for SMMUv3 is implemented, so we will need to extend #ifndef above 
to cover CONFIG_ARM_SMMU_V3 as well, right (otherwise an attempt to 
suspend SMMUv2-powered system will lead to crash)? Or there is a plan to 
implement S2R for both SMMU implementations?

***

If we care for possible crash because iommu_suspend is NULL for 
SMMUv2/SMMUv3, maybe we should consider adding stub callbacks to the 
both SMMU drivers, just returning -ENOSYS?

Let's see what other people's opinions are.

> 
> 
>>
>>
>>> +    if ( iommu_enabled )
>>> +    {
>>> +        dprintk(XENLOG_ERR, "IOMMU is enabled, suspend not supported yet\n");
>>> +        return -ENOSYS;
>>> +    }
>>> +#endif
>>> +
>>>       /*
>>>        * system_suspend should be called when Dom0 finalizes the suspend
>>>        * procedure from its boot core (VCPU#0). However, Dom0's VCPU#0 could
>>
>> --
>> WBR, Volodymyr
> 
> Best regards,
> Mykola
> 



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Date: Tue, 26 Aug 2025 11:03:12 -0400
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Subject: Re: [PATCH v2 1/3] xen/events: Cleanup find_virq() return codes
To: Jan Beulich 
CC: , , "Juergen
 Gross" , Stefano Stabellini ,
	Oleksandr Tyshchenko 
References: <20250826005517.41547-1-jason.andryuk@amd.com>
 <20250826005517.41547-2-jason.andryuk@amd.com>
 
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On 2025-08-26 03:22, Jan Beulich wrote:
> On 26.08.2025 02:55, Jason Andryuk wrote:
>> rc is overwritten by the evtchn_status hypercall in each iteration, so
>> the return value will be whatever the last iteration is.
> 
> Which may even be a false "success". Especially for that it feels like ...

I'll state that here...

> 
>>   Change to an
>> explicit -ENOENT for an un-found virq and return 0 on a successful
>> match.
>>
>> Signed-off-by: Jason Andryuk 
> 
> ... this also wants a Fixes: tag and perhaps a Cc: to stable@.

and add these.

> 
>> --- a/drivers/xen/events/events_base.c
>> +++ b/drivers/xen/events/events_base.c
>> @@ -1318,7 +1318,7 @@ static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
>>   {
>>   	struct evtchn_status status;
>>   	evtchn_port_t port;
>> -	int rc = -ENOENT;
>> +	int rc;
> 
> Maybe best to also move this into the more narrow scope (loop body)?

Sounds good.

> Either way:
> Reviewed-by: Jan Beulich 

Thanks.

> 
>>   	memset(&status, 0, sizeof(status));
> 
> Having this outside of the loop is a little odd, too: It makes assumptions
> on the behavior of the hypervisor (like not altering the structure upon
> error). Yet likely not something to deal with right here.

Agreed.

Thanks,
Jason


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To: "xen-devel@lists.xenproject.org" 
Cc: Anthony PERARD ,
 Juergen Gross , Stefano Stabellini 
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Hello,

the other day I observed a strange issue with XTF's selftest failing to
have its VMs created, when running all flavors in a group. (Other tests
look to be similarly affected, it's just the selftest that I run most
frequently.) Originally I suspected a PVH-specific issue, but the
problem surfacing only there is because with PVH Dom0 I have less free
memory left after boot than with PV Dom0. Beyond that, both
configurations use the same hypervisor, with built-in DOM0_MEM="-255M".

The issue looks to be further affected (but not caused) by domain
cleanup being quite a bit slower under PVH Dom0, compared to PV. I.e.
by the time the 2nd test is started, memory from the 1st one still
wasn't completely freed. The result is that randomly one of the latter
(batched) tests fails at domain creation ("failed to free memory for
the domain").

xl's freemem() calls libxl_set_memory_target() followed by
libxl_wait_for_memory_target(). The latter function expects the domain
to balloon down enough for its ->tot_pages (in the hypervisor) to be
at or below the previously set target. However, already immediately
after boot "xl list -l" and "xs ls /" show target values which are 1
page below the hypervisor's record. With libxl_set_memory_target()
requesting relative adjustment, the Dom0 kernel will balloon out the
requested number of pages, but ->tot_pages going down by as many pages
isn't enough to please libxl_wait_for_memory_target().

I'm not even close to having an opinion as to where the problem is: It
could be that the kernel's balloon driver is off by a page. I'm more
inclined though to think that it is entirely unrealistic to expect the
kernel's balloon driver and Xen to have an exactly matching view of
the memory owned by the domain. Yet then it is simply invalid to
compare values taken from Xenstore against values taken from Xen. While
problematic for absolute requests, for relative ones it should be
possible apply the decrement to the source later used to compare
against while waiting.

Jan


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Subject: Re: [PATCH v5] xen/char: implement suspend/resume calls for SCIF
 driver
To: Mykola Kvach , xen-devel@lists.xenproject.org
Cc: Volodymyr Babchuk ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Oleksandr Andrushchenko ,
 Mykola Kvach 
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On 07.08.25 08:16, Mykola Kvach wrote:


Hello Mykola,

In general patch looks good to me, just one question below ...

> From: Volodymyr Babchuk 
> 
> Implement suspend and resume callbacks for the SCIF UART driver,
> enabled when CONFIG_SYSTEM_SUSPEND is set. This allows proper
> handling of UART state across system suspend/resume cycles.
> 
> Tested on Renesas R-Car H3 Starter Kit.
> 
> Signed-off-by: Volodymyr Babchuk 
> Signed-off-by: Oleksandr Andrushchenko 
> Signed-off-by: Mykola Kvach 
> ---
> In patch v5, there are no changes at all;
> it was done just to trigger a review.

I think, you could ping on V4.


> 
> In patch v4, enhance commit message, no functional changes
> 
> In patch v2, I just added a CONFIG_SYSTEM_SUSPEND check around
> the suspend/resume functions in the SCIF driver.
> ---
>   xen/drivers/char/scif-uart.c | 40 ++++++++++++++++++++++++++++++++++--
>   1 file changed, 38 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c
> index 757793ca45..888821a3b8 100644
> --- a/xen/drivers/char/scif-uart.c
> +++ b/xen/drivers/char/scif-uart.c
> @@ -139,9 +139,8 @@ static void scif_uart_interrupt(int irq, void *data)
>       }
>   }
>   
> -static void __init scif_uart_init_preirq(struct serial_port *port)
> +static void scif_uart_disable(struct scif_uart *uart)
>   {
> -    struct scif_uart *uart = port->uart;
>       const struct port_params *params = uart->params;
>   
>       /*
> @@ -155,6 +154,14 @@ static void __init scif_uart_init_preirq(struct serial_port *port)
>   
>       /* Reset TX/RX FIFOs */
>       scif_writew(uart, SCIF_SCFCR, SCFCR_RFRST | SCFCR_TFRST);
> +}
> +
> +static void scif_uart_init_preirq(struct serial_port *port)
> +{
> +    struct scif_uart *uart = port->uart;
> +    const struct port_params *params = uart->params;
> +
> +    scif_uart_disable(uart);
>   
>       /* Clear all errors and flags */
>       scif_readw(uart, params->status_reg);
> @@ -271,6 +278,31 @@ static void scif_uart_stop_tx(struct serial_port *port)
>       scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) & ~SCSCR_TIE);
>   }
>   
> +#ifdef CONFIG_SYSTEM_SUSPEND
> +
> +static void scif_uart_suspend(struct serial_port *port)
> +{
> +    struct scif_uart *uart = port->uart;
> +
> +    scif_uart_stop_tx(port);

  ... I wonder, whether the call above (that disables Transmit 
interrupt) is really needed as the call below disables all interrupts 
anyway?


> +    scif_uart_disable(uart);
> +}

[snip]


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Subject: Re: [PATCH v5 00/11] xenstored patches from split hardware control
To: Jason Andryuk 
Cc: Andrew Cooper ,
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 Stefano Stabellini , Juergen Gross
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On 26.07.2025 01:58, Jason Andryuk wrote:
> This is a subset of patches focusing on xenstored changes from my split
> hardware control domain series.
> 
> It should address the stubdom breakage from the previous series.
> stubdom was tested in gitlab-ci - xl list shows Domain-0 and Xenstore.
> 
> "tools/xenstored: Use priv_domid for manual nodes and permission" is an
> interesting result of looking to rename some internal variables to
> better align their purpose.
> 
> Any review or guidance on the approach is appreciated.
> 
> Jason Andryuk (11):
>   xen: Add capabilities to get_domain_state
>   tools/manage: Expose domain capabilities
>   public/io: xs_wire: Include event channel in interface page
>   xen/dom0less: store xenstore event channel in page
>   tools/xenstored: Read event channel from xenstored page
>   tools/xenstored: Add get_domain_evtchn() to find evtchn
>   tools/xenstored: Auto-introduce domains
>   tools/xenstored: Use priv_domid for manual nodes and permission
>   tools/xenstored: Rename dom0_domid to store_domid
>   tools/xenstored: Remove stubdom special casing
>   tools/xenstored: Remove hardcoded implicit path

To allow more of this to go in, you'll need to chase an ack for patch 4.
Of course you could also indicate if committing any later changes ahead
of patch 4 would be possible / sensible.

Jan


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Date: Tue, 26 Aug 2025 17:56:52 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Jan Beulich , Penny Zheng 
Cc: Xen-devel ,
 Community Manager ,
 "committers@xenproject.org" 
References: <07fc7122-d0ac-4dbe-800d-89086a07005b@gmail.com>
 
Content-Language: en-US
From: Oleksii Kurochko 
In-Reply-To: 

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+ Penny Zheng

On 8/26/25 7:55 AM, Jan Beulich wrote:
> On 25.08.2025 17:50, Oleksii Kurochko wrote:
>> Hello community,
>>
>> I’d like to remind everyone that the Feature Freeze deadline is approaching,
>> and we still have some outstanding requests from the community for patch series
>> to be merged into 4.21:
>>
>> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
>> 2. Introduce SCI SCMI SMC multi-agent support [2]
>> 3. Introduce eSPI support [3]
>> 4. FRED work: [4], [5], possibly others (?)
>> 5. Introduce CONFIG_DOMCTL [6]
>> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
>> 7. Some other patch series I missed.
> "amd-cppc CPU Performance Scaling Driver" has been pending for quite a while,
> and really ought to make it imo. I'm inclined to say even if an exception was
> needed. Parts have gone in, I'm about to commit more parts, but whether
> everything would be in by Friday I can't predict.

Considering that only a few patches are required to receive Ack/Reviewed-by,
this could be considered for inclusion in 4.21.

Penny, do you have some time to provide a new version of the "amd-cppc CPU
Performance Scaling Driver" patch series?

~ Oleksii

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    + Penny Zheng
    
    
    
    
    On 8/26/25 7:55 AM, Jan Beulich wrote:
    
    
    
    
    
      
    On 25.08.2025 17:50, Oleksii Kurochko wrote:

    
      
    
        
    Hello community,

I’d like to remind everyone that the Feature Freeze deadline is approaching,
and we still have some outstanding requests from the community for patch series
to be merged into 4.21:

1. Enable guest suspend/resume support on ARM via vPSCI [1]
2. Introduce SCI SCMI SMC multi-agent support [2]
3. Introduce eSPI support [3]
4. FRED work: [4], [5], possibly others (?)
5. Introduce CONFIG_DOMCTL [6]
6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
7. Some other patch series I missed.

    
      
    
      
    "amd-cppc CPU Performance Scaling Driver" has been pending for quite a while,
and really ought to make it imo. I'm inclined to say even if an exception was
needed. Parts have gone in, I'm about to commit more parts, but whether
everything would be in by Friday I can't predict.
    
    
    
    
    Considering that only a few patches are required to receive Ack/Reviewed-by,
this could be considered for inclusion in 4.21.
    
    
    Penny, do you have some time to provide a new version of the "amd-cppc CPU
Performance Scaling Driver" patch series?
    
    
    ~ Oleksii

    
  


--------------sgoe41cxqyZJkWMG0C15P3z8--


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In-Reply-To: 
From: Mykola Kvach 
Date: Tue, 26 Aug 2025 19:17:42 +0300
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Message-ID: 
Subject: Re: [PATCH v5 12/12] xen/arm: Suspend/resume IOMMU on Xen suspend/resume
To: Oleksandr Tyshchenko 
Cc: Volodymyr Babchuk , 
	"xen-devel@lists.xenproject.org" , 
	Oleksandr Tyshchenko , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Mykola Kvach , 
	Oleksandr Andrushchenko 
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Hi Oleksandr,

On Tue, Aug 26, 2025 at 6:01=E2=80=AFPM Oleksandr Tyshchenko
 wrote:
>
>
>
> On 26.08.25 16:42, Mykola Kvach wrote:
>
> Hello Mykola, Volodymyr
>
>
> > Hi Volodymyr,
> >
> > On Sat, Aug 23, 2025 at 8:55=E2=80=AFPM Volodymyr Babchuk
> >  wrote:
> >>
> >> Hi,
> >>
> >> Mykola Kvach  writes:
> >>
> >>> From: Oleksandr Tyshchenko 
> >>>
> >>> This is done using generic iommu_suspend/resume functions that cause
> >>> IOMMU driver specific suspend/resume handlers to be called for enable=
d
> >>> IOMMU (if one has suspend/resume driver handlers implemented).
> >>>
> >>> These handlers work only when IPMMU-VMSA is used; otherwise,
> >>> we return an error during system suspend requests.
> >>>
> >>> Signed-off-by: Oleksandr Tyshchenko 
> >>> Signed-off-by: Mykola Kvach 
> >>> Tested-by: Oleksandr Andrushchenko 
>
> I think, the Tested-by here should be dropped. A lot of time has passed
> since Oleksandr provided the tag, and the code has changed a bit (I am
> afraid, the tag is now stale).

Got it, I=E2=80=99ll drop the Tested-by tag in the next version.

>
>
> >>> ---
> >>>   xen/arch/arm/suspend.c | 21 +++++++++++++++++++++
> >>>   1 file changed, 21 insertions(+)
> >>>
> >>> diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
> >>> index b5398e5ca6..cb86426ebd 100644
> >>> --- a/xen/arch/arm/suspend.c
> >>> +++ b/xen/arch/arm/suspend.c
> >>> @@ -4,6 +4,7 @@
> >>>   #include 
> >>>   #include 
> >>>   #include 
> >>> +#include 
> >>>   #include 
> >>>   #include 
> >>>
> >>> @@ -49,6 +50,13 @@ static long system_suspend(void *data)
> >>>
> >>>       time_suspend();
> >>>
> >>> +    status =3D iommu_suspend();
> >>> +    if ( status )
> >>> +    {
> >>> +        system_state =3D SYS_STATE_resume;
> >>> +        goto resume_time;
> >>> +    }
> >>> +
> >>>       local_irq_save(flags);
> >>>       status =3D gic_suspend();
> >>>       if ( status )
> >>> @@ -105,6 +113,10 @@ static long system_suspend(void *data)
> >>>
> >>>    resume_irqs:
> >>>       local_irq_restore(flags);
> >>> +
> >>> +    iommu_resume();
> >>> +
> >>> + resume_time:
> >>>       time_resume();
> >>>
> >>>    resume_nonboot_cpus:
> >>> @@ -140,6 +152,15 @@ int host_system_suspend(void)
> >>>           return -ENOSYS;
> >>>       }
> >>>
> >>> +    /* TODO: drop check once suspend/resume support for SMMU is impl=
emented */
> >>> +#ifndef CONFIG_IPMMU_VMSA
>
> The original patch did not seem to have this check...
>
> >>
> >> This check is meaningless, as you can have CONFIG_IPMMU_VMSA enabled
> >> along with CONFIG_ARM_SMMU on a system with SMMU. I think it is enough
> >> that iommu_suspend() will fail during system_suspend(), isn't it?
> >
> > Not exactly. In the case of SMMU, we don=E2=80=99t have valid iommu_sus=
pend/iommu_resume
> > handlers. So it=E2=80=99s possible to have CONFIG_ARM_SMMU enabled and =
iommu_enabled
> > set, but without the appropriate suspend handlers. This could lead to
> > a crash during
> > system_suspend().
>
>   ... I also have doubts whether this check is needed (at least in its
> current shape). Xen has 2 SMMU drivers at the moment. Lets imagine that
> S2R for SMMUv3 is implemented, so we will need to extend #ifndef above
> to cover CONFIG_ARM_SMMU_V3 as well, right (otherwise an attempt to
> suspend SMMUv2-powered system will lead to crash)? Or there is a plan to
> implement S2R for both SMMU implementations?
>
> ***
>
> If we care for possible crash because iommu_suspend is NULL for
> SMMUv2/SMMUv3, maybe we should consider adding stub callbacks to the
> both SMMU drivers, just returning -ENOSYS?

I=E2=80=99m fine with that proposal, adding stub callbacks sounds like a cl=
ean
solution.

>
> Let's see what other people's opinions are.
>
> >
> >
> >>
> >>
> >>> +    if ( iommu_enabled )
> >>> +    {
> >>> +        dprintk(XENLOG_ERR, "IOMMU is enabled, suspend not supported=
 yet\n");
> >>> +        return -ENOSYS;
> >>> +    }
> >>> +#endif
> >>> +
> >>>       /*
> >>>        * system_suspend should be called when Dom0 finalizes the susp=
end
> >>>        * procedure from its boot core (VCPU#0). However, Dom0's VCPU#=
0 could
> >>
> >> --
> >> WBR, Volodymyr
> >
> > Best regards,
> > Mykola
> >
>

Best regards,
Mykola


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Message-ID: <74dced99-e48c-4b74-8383-afc353d58dae@amd.com>
Date: Tue, 26 Aug 2025 12:24:49 -0400
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Subject: Re: [PATCH v5 00/11] xenstored patches from split hardware control
To: Jan Beulich 
CC: Andrew Cooper , Anthony PERARD
	, Michal Orzel , "Julien
 Grall" , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
	, Stefano Stabellini , "Juergen
 Gross" , Bertrand Marquis ,
	
References: <20250725235858.666813-1-jason.andryuk@amd.com>
 <698b0944-0be3-4c04-ba97-a8ef55ebd826@suse.com>
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On 2025-08-26 11:53, Jan Beulich wrote:
> On 26.07.2025 01:58, Jason Andryuk wrote:
>> This is a subset of patches focusing on xenstored changes from my split
>> hardware control domain series.
>>
>> It should address the stubdom breakage from the previous series.
>> stubdom was tested in gitlab-ci - xl list shows Domain-0 and Xenstore.
>>
>> "tools/xenstored: Use priv_domid for manual nodes and permission" is an
>> interesting result of looking to rename some internal variables to
>> better align their purpose.
>>
>> Any review or guidance on the approach is appreciated.
>>
>> Jason Andryuk (11):
>>    xen: Add capabilities to get_domain_state
>>    tools/manage: Expose domain capabilities
>>    public/io: xs_wire: Include event channel in interface page
>>    xen/dom0less: store xenstore event channel in page
>>    tools/xenstored: Read event channel from xenstored page
>>    tools/xenstored: Add get_domain_evtchn() to find evtchn
>>    tools/xenstored: Auto-introduce domains
>>    tools/xenstored: Use priv_domid for manual nodes and permission
>>    tools/xenstored: Rename dom0_domid to store_domid
>>    tools/xenstored: Remove stubdom special casing
>>    tools/xenstored: Remove hardcoded implicit path
> 
> To allow more of this to go in, you'll need to chase an ack for patch 4.
> Of course you could also indicate if committing any later changes ahead
> of patch 4 would be possible / sensible.

I re-posted the xenstored changes separately and they have gone in, 
thanks.  Yes, I need to follow up on patch 4.

Thanks,
Jason


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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2] x86/bitops: Optimise arch_ffs{,l}() some more on AMD
Date: Tue, 26 Aug 2025 18:41:35 +0100
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One aspect of the old ffs() infrastructure was the use of TZCNT without a
CPUID check.  Given no obvious justification, I dropped it during the cleanup.

It turns out there is a good reason, on all but the most recent AMD CPUs.

Reinstate the use of "blind" TZCNT when safe to do so.  This happens to be
preferentially in loops where a repeated saving of 5-6 uops becomes far more
relevant than a one-off scenario.  Leave an explanation of why.

It is not safe to perform this transformation for BSR and LZCNT, because they
count from opposite ends of the input operand.  Furthermore, this incorrect
transform was not caught by the selftests.

Extend the selftests with test_for_each_set_bit_reverse() as that exercises
the "x known non-zero" optimsiation path in x86's helpers.  Adjust the
existing test_for_each_set_bit() to intentionally use an asymmetric input bit
pattern, otherwise "counting from the wrong end" bugs continue to slip by.

No functional change.

Fixes: 989e5f08d33e ("x86/bitops: Improve arch_ffs() in the general case")
Fixes: 5ed26fc0768d ("xen/bitops: Implement ffsl() in common logic")
Signed-off-by: Andrew Cooper 
Reviewed-by: Jan Beulich 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Use TZCNT mnemonic given the updated toolchain baseline
 * Do not convert LZCNT.
 * Extend selftests.

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/2004918013

I've kept Jan's R-by as this is a subset of what was previously reviewed, but
I'm posting it for clarity as there are a lot of selftest changes.
---
 xen/arch/x86/include/asm/bitops.h | 13 ++++--
 xen/common/bitops.c               | 78 ++++++++++++++++++++++++++++++-
 2 files changed, 86 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/include/asm/bitops.h b/xen/arch/x86/include/asm/bitops.h
index 87eac7782f10..b17d67e8ca61 100644
--- a/xen/arch/x86/include/asm/bitops.h
+++ b/xen/arch/x86/include/asm/bitops.h
@@ -399,9 +399,16 @@ static always_inline unsigned int arch_ffs(unsigned int x)
          *
          * and the optimiser really can work with the knowledge of x being
          * non-zero without knowing it's exact value, in which case we don't
-         * need to compensate for BSF's corner cases.  Otherwise...
+         * need to compensate for BSF's corner cases.
+         *
+         * That said, we intentionally use TZCNT on capable hardware when the
+         * behaviour for the 0 case doesn't matter.  On AMD CPUs prior to
+         * Zen4, TZCNT is 1-2 uops while BSF is 6-8 with a latency to match.
+         * Intel CPUs don't suffer this discrepancy.
+         *
+         * Otherwise...
          */
-        asm ( "bsf %[val], %[res]"
+        asm ( "tzcnt %[val], %[res]"
               : [res] "=r" (r)
               : [val] "rm" (x) );
     }
@@ -428,7 +435,7 @@ static always_inline unsigned int arch_ffsl(unsigned long x)
 
     /* See arch_ffs() for safety discussions. */
     if ( __builtin_constant_p(x > 0) && x > 0 )
-        asm ( "bsf %[val], %q[res]"
+        asm ( "tzcnt %[val], %q[res]"
               : [res] "=r" (r)
               : [val] "rm" (x) );
     else
diff --git a/xen/common/bitops.c b/xen/common/bitops.c
index bd17ddef5700..14e6265037f1 100644
--- a/xen/common/bitops.c
+++ b/xen/common/bitops.c
@@ -97,14 +97,14 @@ static void __init test_for_each_set_bit(void)
     if ( ui != ui_res )
         panic("for_each_set_bit(uint) expected %#x, got %#x\n", ui, ui_res);
 
-    ul = HIDE(1UL << (BITS_PER_LONG - 1) | 1);
+    ul = HIDE(1UL << (BITS_PER_LONG - 1) | 0x11);
     for_each_set_bit ( i, ul )
         ul_res |= 1UL << i;
 
     if ( ul != ul_res )
         panic("for_each_set_bit(ulong) expected %#lx, got %#lx\n", ul, ul_res);
 
-    ull = HIDE(0x8000000180000001ULL);
+    ull = HIDE(0x8000000180000011ULL);
     for_each_set_bit ( i, ull )
         ull_res |= 1ULL << i;
 
@@ -127,6 +127,79 @@ static void __init test_for_each_set_bit(void)
         panic("for_each_set_bit(break) expected 0x1008, got %#x\n", ui_res);
 }
 
+/*
+ * A type-generic fls() which picks the appropriate fls{,l,64}() based on it's
+ * argument.
+ */
+#define fls_g(x)                                        \
+    (sizeof(x) <= sizeof(int)      ? fls(x) :           \
+     sizeof(x) <= sizeof(long)     ? flsl(x) :          \
+     sizeof(x) <= sizeof(uint64_t) ? fls64(x) :         \
+     ({ BUILD_ERROR("fls_g() Bad input type"); 0; }))
+
+/*
+ * for_each_set_bit_reverse() - Iterate over all set bits in a scalar value,
+ * from MSB to LSB.
+ *
+ * @iter An iterator name.  Scoped is within the loop only.
+ * @val  A scalar value to iterate over.
+ *
+ * A copy of @val is taken internally.
+ */
+#define for_each_set_bit_reverse(iter, val)             \
+    for ( typeof(val) __v = (val); __v; __v = 0 )       \
+        for ( unsigned int (iter);                      \
+              __v && ((iter) = fls_g(__v) - 1, true);   \
+              __clear_bit(iter, &__v) )
+
+/*
+ * Xen doesn't have need of for_each_set_bit_reverse() at present, but the
+ * construct does exercise a case of arch_fls*() not covered anywhere else by
+ * these tests.
+ */
+static void __init test_for_each_set_bit_reverse(void)
+{
+    unsigned int  ui,  ui_res = 0, tmp;
+    unsigned long ul,  ul_res = 0;
+    uint64_t      ull, ull_res = 0;
+
+    ui = HIDE(0x80008001U);
+    for_each_set_bit_reverse ( i, ui )
+        ui_res |= 1U << i;
+
+    if ( ui != ui_res )
+        panic("for_each_set_bit_reverse(uint) expected %#x, got %#x\n", ui, ui_res);
+
+    ul = HIDE(1UL << (BITS_PER_LONG - 1) | 0x11);
+    for_each_set_bit_reverse ( i, ul )
+        ul_res |= 1UL << i;
+
+    if ( ul != ul_res )
+        panic("for_each_set_bit_reverse(ulong) expected %#lx, got %#lx\n", ul, ul_res);
+
+    ull = HIDE(0x8000000180000011ULL);
+    for_each_set_bit_reverse ( i, ull )
+        ull_res |= 1ULL << i;
+
+    if ( ull != ull_res )
+        panic("for_each_set_bit_reverse(uint64) expected %#"PRIx64", got %#"PRIx64"\n", ull, ull_res);
+
+    /* Check that we can break from the middle of the loop. */
+    ui = HIDE(0x80001008U);
+    tmp = 0;
+    ui_res = 0;
+    for_each_set_bit_reverse ( i, ui )
+    {
+        if ( tmp++ > 1 )
+            break;
+
+        ui_res |= 1U << i;
+    }
+
+    if ( ui_res != 0x80001000U )
+        panic("for_each_set_bit_reverse(break) expected 0x80001000, got %#x\n", ui_res);
+}
+
 static void __init test_multiple_bits_set(void)
 {
     /*
@@ -169,6 +242,7 @@ static void __init __constructor test_bitops(void)
     test_ffs();
     test_fls();
     test_for_each_set_bit();
+    test_for_each_set_bit_reverse();
 
     test_multiple_bits_set();
     test_hweight();
-- 
2.39.5



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From: Ritesh Harjani (IBM) 
To: David Hildenbrand , linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org, xen-devel@lists.xenproject.org, 
	linux-fsdevel@vger.kernel.org, nvdimm@lists.linux.dev, 
	linuxppc-dev@lists.ozlabs.org, David Hildenbrand , 
	Andrew Morton , Madhavan Srinivasan , 
	Michael Ellerman , Nicholas Piggin , 
	Christophe Leroy , Juergen Gross , 
	Stefano Stabellini , 
	Oleksandr Tyshchenko , Dan Williams , 
	Matthew Wilcox , Jan Kara , 
	Alexander Viro , Christian Brauner , 
	Lorenzo Stoakes , "Liam R. Howlett" , 
	Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , 
	Michal Hocko , Zi Yan , 
	Baolin Wang , Nico Pache , 
	Ryan Roberts , Dev Jain , Barry Song , 
	Jann Horn , Pedro Falcato , Hugh Dickins , 
	Oscar Salvador , Lance Yang 
Subject: Re: [PATCH v3 06/11] powerpc/ptdump: rename "struct pgtable_level" to "struct ptdump_pglevel"
In-Reply-To: <20250811112631.759341-7-david@redhat.com>
Date: Tue, 26 Aug 2025 21:58:09 +0530
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References: <20250811112631.759341-1-david@redhat.com> <20250811112631.759341-7-david@redhat.com>
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David Hildenbrand  writes:

> We want to make use of "pgtable_level" for an enum in core-mm. Other
> architectures seem to call "struct pgtable_level" either:
> * "struct pg_level" when not exposed in a header (riscv, arm)
> * "struct ptdump_pg_level" when expose in a header (arm64)
>
> So let's follow what arm64 does.
>
> Signed-off-by: David Hildenbrand 
> ---
>  arch/powerpc/mm/ptdump/8xx.c      | 2 +-
>  arch/powerpc/mm/ptdump/book3s64.c | 2 +-
>  arch/powerpc/mm/ptdump/ptdump.h   | 4 ++--
>  arch/powerpc/mm/ptdump/shared.c   | 2 +-
>  4 files changed, 5 insertions(+), 5 deletions(-)


As mentioned in commit msg mostly a mechanical change to convert 
"struct pgtable_level" to "struct ptdump_pg_level" for aforementioned purpose.. 

The patch looks ok and compiles fine on my book3s64 and ppc32 platform. 

I think we should fix the subject line.. s/ptdump_pglevel/ptdump_pg_level

Otherwise the changes looks good to me. So please feel free to add - 
Reviewed-by: Ritesh Harjani (IBM) 



>
> diff --git a/arch/powerpc/mm/ptdump/8xx.c b/arch/powerpc/mm/ptdump/8xx.c
> index b5c79b11ea3c2..4ca9cf7a90c9e 100644
> --- a/arch/powerpc/mm/ptdump/8xx.c
> +++ b/arch/powerpc/mm/ptdump/8xx.c
> @@ -69,7 +69,7 @@ static const struct flag_info flag_array[] = {
>  	}
>  };
>  
> -struct pgtable_level pg_level[5] = {
> +struct ptdump_pg_level pg_level[5] = {
>  	{ /* pgd */
>  		.flag	= flag_array,
>  		.num	= ARRAY_SIZE(flag_array),
> diff --git a/arch/powerpc/mm/ptdump/book3s64.c b/arch/powerpc/mm/ptdump/book3s64.c
> index 5ad92d9dc5d10..6b2da9241d4c4 100644
> --- a/arch/powerpc/mm/ptdump/book3s64.c
> +++ b/arch/powerpc/mm/ptdump/book3s64.c
> @@ -102,7 +102,7 @@ static const struct flag_info flag_array[] = {
>  	}
>  };
>  
> -struct pgtable_level pg_level[5] = {
> +struct ptdump_pg_level pg_level[5] = {
>  	{ /* pgd */
>  		.flag	= flag_array,
>  		.num	= ARRAY_SIZE(flag_array),
> diff --git a/arch/powerpc/mm/ptdump/ptdump.h b/arch/powerpc/mm/ptdump/ptdump.h
> index 154efae96ae09..4232aa4b57eae 100644
> --- a/arch/powerpc/mm/ptdump/ptdump.h
> +++ b/arch/powerpc/mm/ptdump/ptdump.h
> @@ -11,12 +11,12 @@ struct flag_info {
>  	int		shift;
>  };
>  
> -struct pgtable_level {
> +struct ptdump_pg_level {
>  	const struct flag_info *flag;
>  	size_t num;
>  	u64 mask;
>  };
>  
> -extern struct pgtable_level pg_level[5];
> +extern struct ptdump_pg_level pg_level[5];
>  
>  void pt_dump_size(struct seq_file *m, unsigned long delta);
> diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
> index 39c30c62b7ea7..58998960eb9a4 100644
> --- a/arch/powerpc/mm/ptdump/shared.c
> +++ b/arch/powerpc/mm/ptdump/shared.c
> @@ -67,7 +67,7 @@ static const struct flag_info flag_array[] = {
>  	}
>  };
>  
> -struct pgtable_level pg_level[5] = {
> +struct ptdump_pg_level pg_level[5] = {
>  	{ /* pgd */
>  		.flag	= flag_array,
>  		.num	= ARRAY_SIZE(flag_array),
> -- 
> 2.50.1


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Feedback-ID: i1568416f:Fastmail
Date: Tue, 26 Aug 2025 20:14:47 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Jan Beulich ,
	xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart
Message-ID: 
References: 
 <2aafbace-3aa2-4f58-8f6c-2815cd2315ad@suse.com>
 
 
 
 
 
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--XYjHLFKe6qQk+9uo
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Date: Tue, 26 Aug 2025 20:14:47 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Roger Pau =?utf-8?B?TW9ubsOp?= 
Cc: Jan Beulich ,
	xen-devel 
Subject: Re: MSI-X cleanup(?) issue with passthrough after domU restart

On Tue, Aug 26, 2025 at 04:52:17PM +0200, Marek Marczykowski-G=C3=B3recki w=
rote:
> On Tue, Aug 26, 2025 at 04:47:50PM +0200, Roger Pau Monn=C3=A9 wrote:
> > On Tue, Aug 26, 2025 at 03:55:05PM +0200, Marek Marczykowski-G=C3=B3rec=
ki wrote:
> > > On Tue, Aug 26, 2025 at 12:57:50PM +0200, Marek Marczykowski-G=C3=B3r=
ecki wrote:
> > > > On Tue, Aug 26, 2025 at 10:28:56AM +0200, Roger Pau Monn=C3=A9 wrot=
e:
> > > > > On Tue, Aug 26, 2025 at 08:16:56AM +0200, Jan Beulich wrote:
> > > > > > On 26.08.2025 03:49, Marek Marczykowski-G=C3=B3recki wrote:
> > > > > > > Hi,
> > > > > > >=20
> > > > > > > I'm hitting an MSI-X issue after rebooting the domU. The symp=
toms are
> > > > > > > rather boring: on initial domU start the device (realtek eth =
card) works
> > > > > > > fine, but after domU restart, the link doesn't come up (there=
 is no
> > > > > > > "Link is Up" message anymore). No errors from domU driver or =
Xen. I
> > > > > > > tracked it down to MSI-X - if I force INTx (via pci=3Dnomsi o=
n domU
> > > > > > > cmdline) it works fine. Convincing the driver to poll instead=
 of waiting
> > > > > > > for an interrupt also workarounds the issue.
> > > > > > >=20
> > > > > > > I noticed also some interrupts are not cleaned up on restart.=
 The list
> > > > > > > of MSIs in 'Q' debug key output grows:
> > > > > > >=20
> > > > > > >     (XEN) 0000:03:00.0 - d22 - node -1  - MSIs < 41 42 43 44 =
45 46 47 >
> > > > > > >     restart sys-net domU
> > > > > > >     (XEN) 0000:03:00.0 - d24 - node -1  - MSIs < 41 42 43 44 =
45 46 47 48 >
> > > > > > >     restart sys-net domU
> > > > > > >     (XEN) 0000:03:00.0 - d26 - node -1  - MSIs < 41 42 43 44 =
45 46 47 48 49 >
> > > > > > >=20
> > > > > > > and 'M' output is:
> > > > > > >=20
> > > > > > >     (XEN)  MSI-X   41 vec=3Db1 lowest  edge   assert  log low=
est dest=3D00000001 mask=3D1/H /1
> > > > > > >     (XEN)  MSI-X   42 vec=3Db9 lowest  edge   assert  log low=
est dest=3D00000004 mask=3D1/HG/1
> > > > > > >     (XEN)  MSI-X   43 vec=3Dc1 lowest  edge   assert  log low=
est dest=3D00000010 mask=3D1/HG/1
> > > > > > >     (XEN)  MSI-X   44 vec=3Dd9 lowest  edge   assert  log low=
est dest=3D00000001 mask=3D1/HG/1
> > > > > > >     (XEN)  MSI-X   45 vec=3De1 lowest  edge   assert  log low=
est dest=3D00000001 mask=3D1/HG/1
> > > > > > >     (XEN)  MSI-X   46 vec=3De9 lowest  edge   assert  log low=
est dest=3D00000040 mask=3D1/HG/1
> > > > > > >     (XEN)  MSI-X   47 vec=3D32 lowest  edge   assert  log low=
est dest=3D00000004 mask=3D1/HG/1
> > > > > > >     (XEN)  MSI-X   48 vec=3D3a lowest  edge   assert  log low=
est dest=3D00000040 mask=3D1/HG/1
> > > > > > >     (XEN)  MSI-X   49 vec=3D42 lowest  edge   assert  log low=
est dest=3D00000010 mask=3D1/ G/1
> > > > > > >=20
> > > > > > > And also, after starting and stopping the domU, `xl pci-assig=
nable-remove 03:00.0`
> > > > > > > makes pciback to complain:
> > > > > > >=20
> > > > > > >     [ 1180.919874] pciback 0000:03:00.0: xen_pciback: MSI-X r=
elease failed (-16)
> > > > > > >=20
> > > > > > > This is all running on Xen 4.19.3, but I don't see much chang=
es in this
> > > > > > > area since then.
> > > > > > >=20
> > > > > > > Some more info collected at https://github.com/QubesOS/qubes-=
issues/issues/9335
> > > > > > >=20
> > > > > > > My question is: what should be responsible for this cleanup o=
n domain
> > > > > > > destroy? Xen, or maybe device model (which is QEMU in stubdom=
ain here)?
> > > > > >=20
> > > > > > The expectation is that qemu invokes the necessary cleanup, but=
 of course ...
> > > > > >=20
> > > > > > > I see some cleanup (apparently not enough) happening via QEMU=
 when the
> > > > > > > domU driver is unloaded, but logically correct cleanup should=
n't depend
> > > > > > > on correct domU operation...
> > > > > >=20
> > > > > > ... Xen may not make itself dependent upon either DomU or QEMU.
> > > > >=20
> > > > > AFAICT free_domain_pirqs() called by arch_domain_destroy() should=
 take
> > > > > care of unbinding and freeing pirqs (but obviously not in this ca=
se).
> > > > > Can you repeat the test with a debug=3Dy hypervisor and post the
> > > > > resulting serial or dmesg here?  Some of the errors on those path=
s are
> > > > > printed with dprintk() and won't be visible unless using a Xen de=
bug
> > > > > build.
> > > >=20
> > > > Sure, will do.
> > >=20
> > > Output collected during domU shutdown and subsequent startup (dom0 lo=
gs
> > > to Xen console here too):
> > > https://gist.github.com/marmarek/6dc3ac14d3ba840482e6361fcbd37c30
> > >=20
> > > I don't see any errors there...
> >=20
> > Hm, yes, I don't see any errors either.  Do you think you could
> > instrument unmap_domain_pirq() and figure out whether it gets called,
> > and if such call to unmap the PIRQ succeeds?
>=20
> Sure, now that I know where to look at, I'll try to find out what goes
> wrong.

Ok, after adding several debug prints there and looking why it's not
called, I found it's a completely different issue. arch_domain_destroy()
is not called, because there was a dom0 userspace process still having a
page mapped of that domain, and indeed there was a zombie on xl list.
Killing that process fixes it.

Sorry for the noise...

> Yeah, it's a single boot and that's it. I can improve that (and double
> check if MSI-X is covered too).

But this might be a good idea anyway.

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Oleksii Kurochko ,
 Xen-devel ,
 Community Manager ,
 "committers@xenproject.org" 
References: <07fc7122-d0ac-4dbe-800d-89086a07005b@gmail.com>
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From: Andrew Cooper 
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On 25/08/2025 4:50 pm, Oleksii Kurochko wrote:
> Hello community,
>
> I’d like to remind everyone that the Feature Freeze deadline is approaching,
> and we still have some outstanding requests from the community for patch series
> to be merged into 4.21:
>
> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
> 2. Introduce SCI SCMI SMC multi-agent support [2]
> 3. Introduce eSPI support [3]
> 4. FRED work: [4], [5], possibly others (?)

For FRED, That's all that's out on the list.

I've got an update to 4 almost ready to post, this time getting to dev
complete.

Unfortunately, I've still not managed to get any time on real hardware
yet, so FRED will still be experimental in my series.  (The timelines
were originally compatible with Xen 4.21, but access to hardware has not
been as forthcoming as hoped.)

When I can test on real hardware, there may be bugfixes, and I may be
able to upgrade the status if we're not too far into the RCs.

~Andrew


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Date: Tue, 26 Aug 2025 21:15:32 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: Jan Beulich , Stefano Stabellini
 , Doug Goldstein , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 xen-devel@lists.xenproject.org
Subject: Re: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
In-Reply-To: 
References: 
 <60022d5c-1a9f-4a6d-8df2-bca57cefcf59@suse.com>
 
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On 2025-08-26 20:07, Dmytro Prokopchuk1 wrote:
> On 8/25/25 13:07, Jan Beulich wrote:
>> On 24.08.2025 16:56, Dmytro Prokopchuk1 wrote:
>>> --- a/docs/misra/deviations.rst
>>> +++ b/docs/misra/deviations.rst
>>> @@ -97,6 +97,19 @@ Deviations related to MISRA C:2012 Rules:
>>>          Xen expects developers to ensure code remains safe and 
>>> reliable in builds,
>>>          even when debug-only assertions like `ASSERT_UNREACHABLE() 
>>> are removed.
>>> 
>>> +   * - R2.1
>>> +     - The 'BUG()' macro is intentionally used in the 
>>> 'prepare_acpi()' function
>>> +       in specific build configuration (when the config CONFIG_ACPI 
>>> is not
>>> +       defined) to trigger an error if ACPI-related features are 
>>> used incorrectly.
>>> +     - Tagged as `deliberate` for ECLAIR.
>> 
>> With
>> 
>> #define acpi_disabled true
>> 
>> in xen/acpi.h I don't see why we even have that inline stub. When it's 
>> dropped
>> and the declaration left in place without #ifdef CONFIG_ACPI around 
>> it, the
>> compiler will DCE the code (much like we arrange for in many other 
>> places). No
>> deviation needed then.
>> 
>> If such a deviation was to be added, it would need disambiguating. A 
>> function
>> of the given name could appear in x86 as well. That wouldn't be 
>> covered by the
>> Eclair config then, but it would be covered by the text here.
>> 
>>> +   * - R2.1
>>> +     - The 'BUG()' macro is intentionally used in 'gicv3_do_LPI'() 
>>> and
>>> +       'gicv3_its_setup_collection()' functions in specific build 
>>> configuration
>>> +       (when the config CONFIG_HAS_ITS is not defined) to catch and 
>>> prevent any
>>> +       unintended execution of code that should only run when ITS is 
>>> available.
>>> +     - Tagged as `deliberate` for ECLAIR.
>> 
>> I didn't look at this, but I would very much hope that something 
>> similar could
>> be done there as well.
>> 
>> Jan
> 
> After small changes related to prepare_acpi() function, Misra R2.1
> violation has gone. The compiler really does DCE:
> 
>      if ( acpi_disabled <<< this is TRUE )
>      {
>          rc = prepare_dtb_hwdom(d, kinfo);
>          if ( rc < 0 )
>              return rc;
> #ifdef CONFIG_HAS_PCI
>          rc = pci_host_bridge_mappings(d);
> #endif
>      }
>      else
>          rc = prepare_acpi(d, kinfo); <<< DCE
> 
> I will publish it as separate patch.
> Thanks to Jan, I really appreciate his help.
> 
> 
> The situation with functions gicv3_do_LPI(),
> gicv3_its_setup_collection() and config CONFIG_HAS_ITS is little bit
> different.
> The compiler can do DCE in case when config CONFIG_HAS_ITS is "y", and
> Misra R2.1 violation related to these functions also can be resolved.
> Actually, no changes in source code need for that.
> But Eclair detects these violations because config CONFIG_HAS_ITS is
> "n", and source code is really compiled with inline stub functions 
> (with
> BUG() macro).
> This is because config CONFIG_HAS_ITS is "experimental/unsupported"
> 
>      config HAS_ITS
>              bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if
>   UNSUPPORTED
>          depends on GICV3 && !NEW_VGIC && !ARM_32
> 
> and to enable it need to set additional config: "CONFIG_UNSUPPORTED=y".
> 
> I tried to test it (added "CONFIG_UNSUPPORTED=y" into
> automation/gitlab-ci/analyze.yaml file). You can see my CI pipeline:
> https://eclair-analysis-logs.xenproject.org/fs/var/local/eclair/xen-project.ecdf/xen-project/people/dimaprkp4k/xen/ECLAIR_normal/rule_2.1_gicv3_its_host_has_its_v2/ARM64/11144854092/PROJECT.ecd;/by_service.html#service&kind
> 
> Unfortunately, I observed +6 new violations with that additional config
> "CONFIG_UNSUPPORTED=y".
> 
> I don't know how and why these EXTRA_XEN_CONFIG were selected in the
> file 'automation/gitlab-ci/analyze.yaml'. And are we able to add new
> configs here ?....
> 

You'll have to ask Stefano about that, but I doubt at this stage. Those 
set of configs for Arm and X86 has been selected ~2 years ago.

> So, I see the next plan (just from my point of view):
> 1. Add "CONFIG_UNSUPPORTED=y" and resolve new violations.
> 2. Continue with proposed deviation
> 3. ... ?
> 
> Thank you in advance.
> Dmytro.

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Oleksii Kurochko ,
 Xen-devel ,
 Community Manager ,
 "committers@xenproject.org" 
References: <07fc7122-d0ac-4dbe-800d-89086a07005b@gmail.com>
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From: Andrew Cooper 
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On 25/08/2025 4:50 pm, Oleksii Kurochko wrote:
> Hello community,
>
> I’d like to remind everyone that the Feature Freeze deadline is approaching,
> and we still have some outstanding requests from the community for patch series
> to be merged into 4.21:
>
> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
> 2. Introduce SCI SCMI SMC multi-agent support [2]
> 3. Introduce eSPI support [3]
> 4. FRED work: [4], [5], possibly others (?)
> 5. Introduce CONFIG_DOMCTL [6]
> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
> 7. Some other patch series I missed.

There's still a pile of CI bugfixes (de-root the ARM containers, fix
tools-tests) and improvements (Debian Trixie, Alpine), as well as bugs
that need fixing which aren't complete yet (fixes for the de-rooted x86
containers, see if we can do something about the KBL console problem).

Adding Trixie, and moving off an obsolete version of Alpine are critical
for the release, but I need to get FRED more done before I can come back
to this.

~Andrew


From xen-devel-bounces@lists.xenproject.org Tue Aug 26 19:47:45 2025
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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 01/11] xen/arm: gicv3: refactor obtaining GIC addresses
 for common operations
Thread-Topic: [PATCH v3 01/11] xen/arm: gicv3: refactor obtaining GIC
 addresses for common operations
Thread-Index: AQHcFpJ+etlgg3EWd0CB0IzwgFrWeQ==
Date: Tue, 26 Aug 2025 19:47:30 +0000
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Hi Leonid,

Leonid Komarianskyi  writes:

> Currently, many common functions perform the same operations to calculate
> GIC register addresses. This patch consolidates the similar code into
> a separate helper function to improve maintainability and reduce duplicat=
ion.
> This refactoring also simplifies the implementation of eSPI support in fu=
ture
> changes.
>
> Signed-off-by: Leonid Komarianskyi 
> Reviewed-by: Volodymyr Babchuk 
>
> ---
> Changes in V2:
> - no changes
>
> Changes in V3:
> - changed panic() in get_addr_by_offset() to printing warning and
>   ASSERT_UNREACHABLE()
> - added verification of return pointer from get_addr_by_offset() in the
>   callers
> - moved invocation of get_addr_by_offset() from spinlock guards, since
>   it is not necessarry

... with these changes, still:

Reviewed-by: Volodymyr Babchuk 


> - added RB from Volodymyr Babchuk
> ---
>  xen/arch/arm/gic-v3.c          | 114 +++++++++++++++++++++++----------
>  xen/arch/arm/include/asm/irq.h |   1 +
>  2 files changed, 81 insertions(+), 34 deletions(-)
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index cd3e1acf79..a959fefebe 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -445,17 +445,67 @@ static void gicv3_dump_state(const struct vcpu *v)
>      }
>  }
> =20
> +static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offse=
t)
> +{
> +    switch ( irqd->irq )
> +    {
> +    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD_RDIST_SGI_BASE + offset);
> +        case GICD_ICFGR:
> +            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
> +        case GICD_IPRIORITYR:
> +            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
> +        default:
> +            break;
> +        }
> +    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD + offset + (irqd->irq / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTER + irqd->irq * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYR + irqd->irq);
> +        default:
> +            break;
> +        }
> +    default:
> +        break;
> +    }
> +
> +    /* Something went wrong, we shouldn't be able to reach here */
> +    printk(XENLOG_WARNING "GICv3: WARNING: Invalid offset 0x%x for IRQ#%=
d",
> +           offset, irqd->irq);
> +    ASSERT_UNREACHABLE();
> +
> +    return NULL;
> +}
> +
>  static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_=
for_rwp)
>  {
>      u32 mask =3D 1U << (irqd->irq % 32);
> -    void __iomem *base;
> +    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
> =20
> -    if ( irqd->irq < NR_GIC_LOCAL_IRQS )
> -        base =3D GICD_RDIST_SGI_BASE;
> -    else
> -        base =3D GICD;
> +    if ( addr =3D=3D NULL )
> +        return;
> =20
> -    writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
> +    writel_relaxed(mask, addr);
> =20
>      if ( wait_for_rwp )
>          gicv3_wait_for_rwp(irqd->irq);
> @@ -463,15 +513,12 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u=
32 offset, bool wait_for_rwp)
> =20
>  static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset)
>  {
> -    void __iomem *base;
> -    unsigned int irq =3D irqd->irq;
> +    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
> =20
> -    if ( irq >=3D NR_GIC_LOCAL_IRQS)
> -        base =3D GICD + (irq / 32) * 4;
> -    else
> -        base =3D GICD_RDIST_SGI_BASE;
> +    if ( addr =3D=3D NULL )
> +        return false;
> =20
> -    return !!(readl(base + offset) & (1U << (irq % 32)));
> +    return !!(readl(addr) & (1U << (irqd->irq % 32)));
>  }
> =20
>  static void gicv3_unmask_irq(struct irq_desc *irqd)
> @@ -558,30 +605,28 @@ static inline uint64_t gicv3_mpidr_to_affinity(int =
cpu)
>  static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type)
>  {
>      uint32_t cfg, actual, edgebit;
> -    void __iomem *base;
> -    unsigned int irq =3D desc->irq;
> +    void __iomem *addr;
> =20
>      /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
> -    ASSERT(irq >=3D NR_GIC_SGI);
> +    ASSERT(desc->irq >=3D NR_GIC_SGI);
> =20
> -    spin_lock(&gicv3.lock);
> +    addr =3D get_addr_by_offset(desc, GICD_ICFGR);
> +    if ( addr =3D=3D NULL )
> +        return;
> =20
> -    if ( irq >=3D NR_GIC_LOCAL_IRQS)
> -        base =3D GICD + GICD_ICFGR + (irq / 16) * 4;
> -    else
> -        base =3D GICD_RDIST_SGI_BASE + GICR_ICFGR1;
> +    spin_lock(&gicv3.lock);
> =20
> -    cfg =3D readl_relaxed(base);
> +    cfg =3D readl_relaxed(addr);
> =20
> -    edgebit =3D 2u << (2 * (irq % 16));
> +    edgebit =3D 2u << (2 * (desc->irq % 16));
>      if ( type & IRQ_TYPE_LEVEL_MASK )
>          cfg &=3D ~edgebit;
>      else if ( type & IRQ_TYPE_EDGE_BOTH )
>          cfg |=3D edgebit;
> =20
> -    writel_relaxed(cfg, base);
> +    writel_relaxed(cfg, addr);
> =20
> -    actual =3D readl_relaxed(base);
> +    actual =3D readl_relaxed(addr);
>      if ( ( cfg & edgebit ) ^ ( actual & edgebit ) )
>      {
>          printk(XENLOG_WARNING "GICv3: WARNING: "
> @@ -600,16 +645,13 @@ static void gicv3_set_irq_type(struct irq_desc *des=
c, unsigned int type)
>  static void gicv3_set_irq_priority(struct irq_desc *desc,
>                                     unsigned int priority)
>  {
> -    unsigned int irq =3D desc->irq;
> +    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IPRIORITYR);
> =20
> -    spin_lock(&gicv3.lock);
> -
> -    /* Set priority */
> -    if ( irq < NR_GIC_LOCAL_IRQS )
> -        writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 =
+ irq);
> -    else
> -        writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
> +    if ( addr =3D=3D NULL )
> +        return;
> =20
> +    spin_lock(&gicv3.lock);
> +    writeb_relaxed(priority, addr);
>      spin_unlock(&gicv3.lock);
>  }
> =20
> @@ -1273,6 +1315,10 @@ static void gicv3_irq_set_affinity(struct irq_desc=
 *desc, const cpumask_t *mask)
>  {
>      unsigned int cpu;
>      uint64_t affinity;
> +    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IROUTER);
> +
> +    if ( addr =3D=3D NULL )
> +        return;
> =20
>      ASSERT(!cpumask_empty(mask));
> =20
> @@ -1284,7 +1330,7 @@ static void gicv3_irq_set_affinity(struct irq_desc =
*desc, const cpumask_t *mask)
>      affinity &=3D ~GICD_IROUTER_SPI_MODE_ANY;
> =20
>      if ( desc->irq >=3D NR_GIC_LOCAL_IRQS )
> -        writeq_relaxed_non_atomic(affinity, (GICD + GICD_IROUTER + desc-=
>irq * 8));
> +        writeq_relaxed_non_atomic(affinity, addr);
> =20
>      spin_unlock(&gicv3.lock);
>  }
> diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/ir=
q.h
> index fce7e42a33..5bc6475eb4 100644
> --- a/xen/arch/arm/include/asm/irq.h
> +++ b/xen/arch/arm/include/asm/irq.h
> @@ -29,6 +29,7 @@ struct arch_irq_desc {
>   */
>  #define NR_IRQS		1024
> =20
> +#define SPI_MAX_INTID   1019
>  #define LPI_OFFSET      8192
> =20
>  /* LPIs are always numbered starting at 8192, so 0 is a good invalid cas=
e. */

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 02/11] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Topic: [PATCH v3 02/11] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Index: AQHcFpJ/l4cyfmMsSUSuASmV+4e1mw==
Date: Tue, 26 Aug 2025 19:49:14 +0000
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References: 
	<4a865061abcfe626ffb8c134fe2353fb5675dc86.1756216943.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <4a865061abcfe626ffb8c134fe2353fb5675dc86.1756216943.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Tue, 26 Aug 2025 14:05:36 +0000")
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Leonid Komarianskyi  writes:

> Introduced two new helper functions: gic_is_valid_line and
> gic_is_spi. The first function helps determine whether an IRQ
> number is less than the number of lines supported by hardware. The
> second function additionally checks if the IRQ number falls within the
> SPI range. Also, updated the appropriate checks to use these new helper
> functions.
>
> The current checks for the real GIC are very similar to those for the
> vGIC but serve a different purpose. For GIC-related code, the interrupt
> numbers should be validated based on whether the hardware can operate
> with such interrupts. On the other hand, for the vGIC, the indexes must
> also be verified to ensure they are available for a specific domain. The
> first reason for introducing these helper functions is to avoid
> potential confusion with vGIC-related checks. The second reason is to
> consolidate similar code into separate functions, which can be more
> easily extended by additional conditions, e.g., when implementing
> extended SPI interrupts.
>
> The changes, which replace open-coded checks with the use of the new
> helper functions, do not introduce any functional changes, as the helper
> functions follow the current IRQ index verification logic.
>
> Signed-off-by: Leonid Komarianskyi 

Reviewed-by: Volodymyr Babchuk 

>
> ---
> Changes in V2:
> - introduced this patch
>
> Changes in V3:
> - renamed gic_is_valid_irq to gic_is_valid_line and gic_is_shared_irq to
>   gic_is_spi
> - updated commit message
> ---
>  xen/arch/arm/gic.c             | 2 +-
>  xen/arch/arm/include/asm/gic.h | 9 +++++++++
>  xen/arch/arm/irq.c             | 2 +-
>  3 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index e80fe0ca24..9220eef6ea 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -111,7 +111,7 @@ static void gic_set_irq_priority(struct irq_desc *des=
c, unsigned int priority)
>  void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority)
>  {
>      ASSERT(priority <=3D 0xff);     /* Only 8 bits of priority */
> -    ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts tha=
t don't exist */
> +    ASSERT(gic_is_valid_line(desc->irq));/* Can't route interrupts that =
don't exist */
>      ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
>      ASSERT(spin_is_locked(&desc->lock));
> =20
> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gi=
c.h
> index 541f0eeb80..c7e3b4ff0d 100644
> --- a/xen/arch/arm/include/asm/gic.h
> +++ b/xen/arch/arm/include/asm/gic.h
> @@ -306,6 +306,15 @@ extern void gic_dump_vgic_info(struct vcpu *v);
> =20
>  /* Number of interrupt lines */
>  extern unsigned int gic_number_lines(void);
> +static inline bool gic_is_valid_line(unsigned int irq)
> +{
> +    return irq < gic_number_lines();
> +}
> +
> +static inline bool gic_is_spi(unsigned int irq)
> +{
> +    return (irq >=3D NR_LOCAL_IRQS && gic_is_valid_line(irq));
> +}
> =20
>  /* IRQ translation function for the device tree */
>  int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 03fbb90c6c..7dd5a2a453 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -415,7 +415,7 @@ err:
>  bool is_assignable_irq(unsigned int irq)
>  {
>      /* For now, we can only route SPIs to the guest */
> -    return (irq >=3D NR_LOCAL_IRQS) && (irq < gic_number_lines());
> +    return gic_is_spi(irq);
>  }
> =20
>  /*

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 02/11] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Topic: [PATCH v3 02/11] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Index: AQHcFpJ/l4cyfmMsSUSuASmV+4e1mw==
Date: Tue, 26 Aug 2025 19:53:53 +0000
Message-ID: <87h5xt6er3.fsf@epam.com>
References: 
	<4a865061abcfe626ffb8c134fe2353fb5675dc86.1756216943.git.leonid_komarianskyi@epam.com>
	<87ms7l6eyt.fsf@epam.com>
In-Reply-To: <87ms7l6eyt.fsf@epam.com> (Volodymyr Babchuk's message of "Tue,
	26 Aug 2025 22:49:14 +0300")
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Hello, sorry for the noise,

But I noticed small nick when reviewing next patch, which is very similar.

Volodymyr Babchuk  writes:

> Leonid Komarianskyi  writes:
>
>> Introduced two new helper functions: gic_is_valid_line and
>> gic_is_spi. The first function helps determine whether an IRQ
>> number is less than the number of lines supported by hardware. The
>> second function additionally checks if the IRQ number falls within the
>> SPI range. Also, updated the appropriate checks to use these new helper
>> functions.
>>
>> The current checks for the real GIC are very similar to those for the
>> vGIC but serve a different purpose. For GIC-related code, the interrupt
>> numbers should be validated based on whether the hardware can operate
>> with such interrupts. On the other hand, for the vGIC, the indexes must
>> also be verified to ensure they are available for a specific domain. The
>> first reason for introducing these helper functions is to avoid
>> potential confusion with vGIC-related checks. The second reason is to
>> consolidate similar code into separate functions, which can be more
>> easily extended by additional conditions, e.g., when implementing
>> extended SPI interrupts.
>>
>> The changes, which replace open-coded checks with the use of the new
>> helper functions, do not introduce any functional changes, as the helper
>> functions follow the current IRQ index verification logic.
>>
>> Signed-off-by: Leonid Komarianskyi 
>
> Reviewed-by: Volodymyr Babchuk 

... but with a small fix, see below

>>
>> ---
>> Changes in V2:
>> - introduced this patch
>>
>> Changes in V3:
>> - renamed gic_is_valid_irq to gic_is_valid_line and gic_is_shared_irq to
>>   gic_is_spi
>> - updated commit message
>> ---
>>  xen/arch/arm/gic.c             | 2 +-
>>  xen/arch/arm/include/asm/gic.h | 9 +++++++++
>>  xen/arch/arm/irq.c             | 2 +-
>>  3 files changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
>> index e80fe0ca24..9220eef6ea 100644
>> --- a/xen/arch/arm/gic.c
>> +++ b/xen/arch/arm/gic.c
>> @@ -111,7 +111,7 @@ static void gic_set_irq_priority(struct irq_desc *de=
sc, unsigned int priority)
>>  void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority)
>>  {
>>      ASSERT(priority <=3D 0xff);     /* Only 8 bits of priority */
>> -    ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts th=
at don't exist */
>> +    ASSERT(gic_is_valid_line(desc->irq));/* Can't route interrupts that=
 don't exist */
>>      ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
>>      ASSERT(spin_is_locked(&desc->lock));
>> =20
>> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/g=
ic.h
>> index 541f0eeb80..c7e3b4ff0d 100644
>> --- a/xen/arch/arm/include/asm/gic.h
>> +++ b/xen/arch/arm/include/asm/gic.h
>> @@ -306,6 +306,15 @@ extern void gic_dump_vgic_info(struct vcpu *v);
>> =20
>>  /* Number of interrupt lines */
>>  extern unsigned int gic_number_lines(void);
>> +static inline bool gic_is_valid_line(unsigned int irq)
>> +{
>> +    return irq < gic_number_lines();
>> +}
>> +
>> +static inline bool gic_is_spi(unsigned int irq)
>> +{
>> +    return (irq >=3D NR_LOCAL_IRQS && gic_is_valid_line(irq));

you don't need parentheses here

[...]

--=20
WBR, Volodymyr=


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        Tue, 26 Aug 2025 12:57:37 -0700 (PDT)
Message-ID: <5a84d20c-5136-4151-8801-b0fbccaf23d7@gmail.com>
Date: Tue, 26 Aug 2025 22:57:35 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3 10/11] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <642a994d712a8c9df7aed9dec22124564db83c7e.1756216943.git.leonid_komarianskyi@epam.com>
Content-Language: en-US
From: Oleksandr Tyshchenko 
In-Reply-To: <642a994d712a8c9df7aed9dec22124564db83c7e.1756216943.git.leonid_komarianskyi@epam.com>
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On 26.08.25 17:05, Leonid Komarianskyi wrote:

Hello Leonid


> Implemented support for GICv3.1 extended SPI registers for vGICv3,
> allowing the emulation of eSPI-specific behavior for guest domains.
> The implementation includes read and write emulation for eSPI-related
> registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
> following a similar approach to the handling of regular SPIs.
> 
> The eSPI registers, previously located in reserved address ranges,
> are now adjusted to support MMIO read and write operations correctly
> when CONFIG_GICV3_ESPI is enabled.
> 
> The availability of eSPIs and the number of emulated extended SPIs
> for guest domains is reported by setting the appropriate bits in the
> GICD_TYPER register, based on the number of eSPIs requested by the
> domain and supported by the hardware. In cases where the configuration
> option is disabled, the hardware does not support eSPIs, or the domain
> does not request such interrupts, the functionality remains unchanged.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V2:
> - add missing rank index conversion for pending and inflight irqs
> 
> Changes in V3:
> - changed vgic_store_irouter parameters - instead of offset virq is
>    used, to remove the additional bool espi parameter and simplify
>    checks. Also, adjusted parameters for regular SPI. Since the offset
>    parameter was used only for calculating virq number and then reused for
>    finding rank offset, it will not affect functionality.
> - fixed formatting for goto lables - added newlines after condition
> - fixed logs for GICD_ISACTIVERnE and GICD_ICACTIVERnE handlers
> - removed #ifdefs in 2 places where they were adjacent and could be merged
> ---
>   xen/arch/arm/vgic-v3.c | 275 +++++++++++++++++++++++++++++++++++++++--
>   1 file changed, 266 insertions(+), 9 deletions(-)
> 
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index 4369c55177..56c539bb1b 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -111,13 +111,10 @@ static uint64_t vgic_fetch_irouter(struct vgic_irq_rank *rank,
>    * Note the offset will be aligned to the appropriate boundary.
>    */
>   static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *rank,
> -                               unsigned int offset, uint64_t irouter)
> +                               unsigned int virq, uint64_t irouter)
>   {
>       struct vcpu *new_vcpu, *old_vcpu;
> -    unsigned int virq;
> -
> -    /* There is 1 vIRQ per IROUTER */
> -    virq = offset / NR_BYTES_PER_IROUTER;
> +    unsigned int offset;
>   
>       /*
>        * The IROUTER0-31, used for SGIs/PPIs, are reserved and should
> @@ -685,6 +682,9 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v,
>       {
>       case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>       case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +#endif
>           /* We do not implement security extensions for guests, read zero */
>           if ( dabt.size != DABT_WORD ) goto bad_width;
>           goto read_as_zero;
> @@ -710,11 +710,19 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v,
>       /* Read the pending status of an IRQ via GICD/GICR is not supported */
>       case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
>       case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +#endif
>           goto read_as_zero;
>   
>       /* Read the active status of an IRQ via GICD/GICR is not supported */
>       case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
>       case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +#endif
>           goto read_as_zero;
>   
>       case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
> @@ -752,6 +760,69 @@ static int __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v,
>           return 1;
>       }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +        if ( dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_WORD);
> +        if ( rank == NULL )
> +            goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        *r = vreg_reg32_extract(rank->ienable, info);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +        if ( dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_WORD);
> +        if ( rank == NULL )
> +            goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        *r = vreg_reg32_extract(rank->ienable, info);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    {
> +        uint32_t ipriorityr;
> +        uint8_t rank_index;
> +
> +        if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DABT_WORD);
> +        if ( rank == NULL )
> +            goto read_as_zero;
> +        rank_index = REG_RANK_INDEX(8, reg - GICD_IPRIORITYRnE, DABT_WORD);
> +
> +        vgic_lock_rank(v, rank, flags);
> +        ipriorityr = ACCESS_ONCE(rank->ipriorityr[rank_index]);
> +        vgic_unlock_rank(v, rank, flags);
> +
> +        *r = vreg_reg32_extract(ipriorityr, info);
> +
> +        return 1;
> +    }
> +
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +    {
> +        uint32_t icfgr;
> +
> +        if ( dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WORD);
> +        if ( rank == NULL )
> +            goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        icfgr = rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE, DABT_WORD)];
> +        vgic_unlock_rank(v, rank, flags);
> +
> +        *r = vreg_reg32_extract(icfgr, info);
> +
> +        return 1;
> +    }
> +#endif
> +
>       default:
>           printk(XENLOG_G_ERR
>                  "%pv: %s: unhandled read r%d offset %#08x\n",
> @@ -782,6 +853,9 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v,
>       {
>       case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>       case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +#endif
>           /* We do not implement security extensions for guests, write ignore */
>           goto write_ignore_32;
>   
> @@ -871,6 +945,99 @@ static int __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v,
>           vgic_unlock_rank(v, rank, flags);
>           return 1;
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +        if ( dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_WORD);
> +        if ( rank == NULL )
> +            goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        tr = rank->ienable;
> +        vreg_reg32_setbits(&rank->ienable, r, info);
> +        vgic_enable_irqs(v, (rank->ienable) & (~tr), EXT_RANK_IDX2NUM(rank->index));
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +        if ( dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_WORD);
> +        if ( rank == NULL )
> +            goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        tr = rank->ienable;
> +        vreg_reg32_clearbits(&rank->ienable, r, info);
> +        vgic_disable_irqs(v, (~rank->ienable) & tr, EXT_RANK_IDX2NUM(rank->index));
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +        if ( dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ISPENDRnE, DABT_WORD);
> +        if ( rank == NULL )
> +            goto write_ignore;
> +
> +        vgic_set_irqs_pending(v, r, EXT_RANK_IDX2NUM(rank->index));
> +
> +        return 1;
> +
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +        if ( dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ICPENDRnE, DABT_WORD);
> +        if ( rank == NULL )
> +            goto write_ignore;
> +
> +        vgic_check_inflight_irqs_pending(v, EXT_RANK_IDX2NUM(rank->index), r);
> +
> +        goto write_ignore;
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +        if ( dabt.size != DABT_WORD )
> +            goto bad_width;
> +        printk(XENLOG_G_ERR
> +               "%pv: %s: unhandled word write %#"PRIregister" to ISACTIVER%dE\n",
> +               v, name, r, reg - GICD_ISACTIVERnE);
> +        return 0;

Guest write access to GICD_ISACTIVERE will lead to abort. But, I know 
you just repeated the logic for regular GICD_ISACTIVER.


> +
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +        printk(XENLOG_G_ERR
> +               "%pv: %s: unhandled word write %#"PRIregister" to ICACTIVER%dE\n",
> +               v, name, r, reg - GICD_ICACTIVER);

s/GICD_ICACTIVER/GICD_ICACTIVERnE


> +        goto write_ignore_32;
> +
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    {
> +        uint32_t *ipriorityr, priority;
> +
> +        if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DABT_WORD);
> +        if ( rank == NULL ) goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        ipriorityr = &rank->ipriorityr[REG_RANK_INDEX(8, reg - GICD_IPRIORITYRnE,
> +                                                      DABT_WORD)];
> +        priority = ACCESS_ONCE(*ipriorityr);
> +        vreg_reg32_update(&priority, r, info);
> +        ACCESS_ONCE(*ipriorityr) = priority;
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +    }

NIT: emply line please (and in similar places)

> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +        if ( dabt.size != DABT_WORD )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WORD);
> +        if ( rank == NULL )
> +            goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE,
> +                                                     DABT_WORD)],
> +                          r, info);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +#endif
> +
>       default:
>           printk(XENLOG_G_ERR
>                  "%pv: %s: unhandled write r%d=%"PRIregister" offset %#08x\n",
> @@ -1129,6 +1296,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info,
>               typer |= GICD_TYPE_LPIS;
>   
>           typer |= (v->domain->arch.vgic.intid_bits - 1) << GICD_TYPE_ID_BITS_SHIFT;
> +#ifdef CONFIG_GICV3_ESPI
> +        if ( v->domain->arch.vgic.nr_espis > 0 )
> +        {
> +            /* Set eSPI support bit for the domain */
> +            typer |= GICD_TYPER_ESPI;
> +            /* Set ESPI range bits */
> +            typer |= (DIV_ROUND_UP(v->domain->arch.vgic.nr_espis, 32) - 1)
> +                       << GICD_TYPER_ESPI_RANGE_SHIFT;
> +        }
> +#endif
>   
>           *r = vreg_reg32_extract(typer, info);
>   
> @@ -1194,6 +1371,18 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info,
>       case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
>       case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
>       case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +#endif

GICD_IGRPMODRE is missed? I guess, it should be RAZ as regular 
GICD_IGRPMODR.

Also GICD_NSACRE is missed, although the case for regular 
GICD_NSACR is present (not visible in patch context).

>           /*
>            * Above all register are common with GICR and GICD
>            * Manage in common
> @@ -1216,7 +1405,11 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info,
>           /* Replaced with GICR_ISPENDR0. So ignore write */
>           goto read_as_zero_32;
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(0x3100, 0x60FC):
> +#else
>       case VRANGE32(0x0F30, 0x60FC):
> +#endif
>           goto read_reserved;
>   
>       case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
> @@ -1235,8 +1428,30 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mmio_info_t *info,
>   
>           return 1;
>       }
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
> +    {
> +        uint64_t irouter;
> +
> +        if ( !vgic_reg64_check_access(dabt) )
> +            goto bad_width;
> +        rank = vgic_ext_rank_offset(v, 64, gicd_reg - GICD_IROUTERnE,
> +                                DABT_DOUBLE_WORD);
> +        if ( rank == NULL )
> +            goto read_as_zero;
> +        vgic_lock_rank(v, rank, flags);
> +        irouter = vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTERnE);
> +        vgic_unlock_rank(v, rank, flags);
>   
> +        *r = vreg_reg64_extract(irouter, info);
> +
> +        return 1;
> +    }
> +
> +    case VRANGE32(0xA004, 0xBFFC):
> +#else
>       case VRANGE32(0x7FE0, 0xBFFC):
> +#endif
>           goto read_reserved;
>   
>       case VRANGE32(0xC000, 0xFFCC):
> @@ -1382,6 +1597,18 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info,
>       case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
>       case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
>       case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +#endif

GICD_IGRPMODRE is missed? I guess, it should be WI as regular 
GICD_IGRPMODR.


Also GICD_NSACRE is missed, although the case for regular 
GICD_NSACR is present (not visible in patch context).

>           /* Above registers are common with GICR and GICD
>            * Manage in common */
>           return __vgic_v3_distr_common_mmio_write("vGICD", v, info,
> @@ -1405,26 +1632,56 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, mmio_info_t *info,
>           if ( dabt.size != DABT_WORD ) goto bad_width;
>           return 0;
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE32(0x3100, 0x60FC):
> +#else
>       case VRANGE32(0x0F30, 0x60FC):
> +#endif

I wonder, can we have #defines for these magics (at least for the start 
of the reserved range)?

>           goto write_reserved;
>   
>       case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
>       {
>           uint64_t irouter;
> +        unsigned int offset, virq;
>   
>           if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
> -        rank = vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
> -                                DABT_DOUBLE_WORD);
> +        offset = gicd_reg - GICD_IROUTER;
> +        rank = vgic_rank_offset(v, 64, offset, DABT_DOUBLE_WORD);
>           if ( rank == NULL ) goto write_ignore;
>           vgic_lock_rank(v, rank, flags);
> -        irouter = vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTER);
> +        irouter = vgic_fetch_irouter(rank, offset);
> +        vreg_reg64_update(&irouter, r, info);
> +        virq = offset / NR_BYTES_PER_IROUTER;
> +        vgic_store_irouter(v->domain, rank, virq, irouter);
> +        vgic_unlock_rank(v, rank, flags);
> +        return 1;
> +    }
> +
> +#ifdef CONFIG_GICV3_ESPI
> +    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
> +    {
> +        uint64_t irouter;
> +        unsigned int offset, virq;
> +
> +        if ( !vgic_reg64_check_access(dabt) )
> +            goto bad_width;
> +        offset = gicd_reg - GICD_IROUTERnE;
> +        rank = vgic_ext_rank_offset(v, 64, offset, DABT_DOUBLE_WORD);
> +        if ( rank == NULL )
> +            goto write_ignore;
> +        vgic_lock_rank(v, rank, flags);
> +        irouter = vgic_fetch_irouter(rank, offset);
>           vreg_reg64_update(&irouter, r, info);
> -        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTER, irouter);
> +        virq = ESPI_IDX2INTID(offset / NR_BYTES_PER_IROUTER);
> +        vgic_store_irouter(v->domain, rank, virq, irouter);
>           vgic_unlock_rank(v, rank, flags);
>           return 1;
>       }
>   
> +    case VRANGE32(0xA004, 0xBFFC):
> +#else
>       case VRANGE32(0x7FE0, 0xBFFC):
> +#endif
>           goto write_reserved;
>   
>       case VRANGE32(0xC000, 0xFFCC):



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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 03/11] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Topic: [PATCH v3 03/11] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Index: AQHcFpJ/eek3/DqJlE2eNsEQLkbJqg==
Date: Tue, 26 Aug 2025 20:02:18 +0000
Message-ID: <875xe96ed2.fsf@epam.com>
References: 
	
In-Reply-To:
 
	(Leonid Komarianskyi's message of "Tue, 26 Aug 2025 14:05:37 +0000")
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Hi Leonid,


Leonid Komarianskyi  writes:

> Introduced two new helper functions for vGIC: vgic_is_valid_line and
> vgic_is_spi. The functions are similar to the newly introduced
> gic_is_valid_line and gic_is_spi, but they verify whether a vIRQ
> is available for a specific domain, while GIC-specific functions
> validate INTIDs for the real GIC hardware. For example, the GIC may
> support all 992 SPI lines, but the domain may use only some part of them
> (e.g., 640), depending on the highest IRQ number defined in the domain
> configuration. Therefore, for vGIC-related code and checks, the
> appropriate functions should be used. Also, updated the appropriate
> checks to use these new helper functions.
>
> The purpose of introducing new helper functions for vGIC is essentially
> the same as for GIC: to avoid potential confusion with GIC-related
> checks and to consolidate similar code into separate functions, which
> can be more easily extended by additional conditions, e.g., when
> implementing extended SPI interrupts.
>
> Only the validation change in vgic_inject_irq may affect existing
> functionality, as it currently checks whether the vIRQ is less than or
> equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
> first SPI), the check should behave consistently with similar logic in
> other places and should check if the vIRQ number is less than
> vgic_num_irqs. The remaining changes, which replace open-coded checks
> with the use of these new helper functions, do not introduce any
> functional changes, as the helper functions follow the current vIRQ
> index verification logic.
>
> Signed-off-by: Leonid Komarianskyi 
> ---
> Changes in V2:
> - introduced this patch
>
> Changes in V3:
> - renamed vgic_is_valid_irq to vgic_is_valid_line and vgic_is_shared_irq
>   to vgic_is_spi
> - added vgic_is_valid_line implementation for new-vgic, because
>   vgic_is_valid_line is called from generic code. It is necessary to fix
>   the build for new-vgic.
> - updated commit message
> ---
>  xen/arch/arm/gic.c              |  3 +--
>  xen/arch/arm/include/asm/vgic.h |  7 +++++++
>  xen/arch/arm/irq.c              |  4 ++--
>  xen/arch/arm/vgic.c             | 10 ++++++++--
>  xen/arch/arm/vgic/vgic.c        |  5 +++++
>  5 files changed, 23 insertions(+), 6 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index 9220eef6ea..b88237ccda 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -133,8 +133,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned=
 int virq,
> =20
>      ASSERT(spin_is_locked(&desc->lock));
>      /* Caller has already checked that the IRQ is an SPI */
> -    ASSERT(virq >=3D 32);
> -    ASSERT(virq < vgic_num_irqs(d));
> +    ASSERT(vgic_is_spi(d, virq));
>      ASSERT(!is_lpi(virq));
> =20
>      ret =3D vgic_connect_hw_irq(d, NULL, virq, desc, true);
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 35c0c6a8b0..9f437e9838 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -335,6 +335,13 @@ extern void vgic_check_inflight_irqs_pending(struct =
vcpu *v,
>  /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. =
*/
>  #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
> =20
> +extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);

Why you can't have inline implementation for vgic_is_valid_line() right her=
e?

> +
> +static inline bool vgic_is_spi(struct domain *d, unsigned int virq)
> +{
> +    return (virq >=3D NR_LOCAL_IRQS && vgic_is_valid_line(d, virq));

You don't need parentheses here.

> +}
> +
>  /*
>   * Allocate a guest VIRQ
>   *  - spi =3D=3D 0 =3D> allocate a PPI. It will be the same on every vCP=
U
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 7dd5a2a453..b8eccfc924 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -442,7 +442,7 @@ int route_irq_to_guest(struct domain *d, unsigned int=
 virq,
>      unsigned long flags;
>      int retval =3D 0;
> =20
> -    if ( virq >=3D vgic_num_irqs(d) )
> +    if ( !vgic_is_valid_line(d, virq) )
>      {
>          printk(XENLOG_G_ERR
>                 "the vIRQ number %u is too high for domain %u (max =3D %u=
)\n",
> @@ -560,7 +560,7 @@ int release_guest_irq(struct domain *d, unsigned int =
virq)
>      int ret;
> =20
>      /* Only SPIs are supported */
> -    if ( virq < NR_LOCAL_IRQS || virq >=3D vgic_num_irqs(d) )
> +    if ( !vgic_is_spi(d, virq) )
>          return -EINVAL;
> =20
>      desc =3D vgic_get_hw_irq_desc(d, NULL, virq);
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index c563ba93af..2bbf4d99aa 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -24,6 +24,12 @@
>  #include 
>  #include 
> =20
> +
> +bool vgic_is_valid_line(struct domain *d, unsigned int virq)

Implementation of this function here in for new vgic is basically the
same and depends only on vgic_num_irqs() which is macro defined in
vgic.h and used by both implementations.

> +{
> +    return virq < vgic_num_irqs(d);
> +}
> +
>  static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>                                                    unsigned int rank)
>  {
> @@ -582,7 +588,7 @@ void vgic_inject_irq(struct domain *d, struct vcpu *v=
, unsigned int virq,
>      if ( !v )
>      {
>          /* The IRQ needs to be an SPI if no vCPU is specified. */
> -        ASSERT(virq >=3D 32 && virq <=3D vgic_num_irqs(d));
> +        ASSERT(vgic_is_spi(d, virq));
> =20
>          v =3D vgic_get_target_vcpu(d->vcpu[0], virq);
>      };
> @@ -659,7 +665,7 @@ bool vgic_emulate(struct cpu_user_regs *regs, union h=
sr hsr)
> =20
>  bool vgic_reserve_virq(struct domain *d, unsigned int virq)
>  {
> -    if ( virq >=3D vgic_num_irqs(d) )
> +    if ( !vgic_is_valid_line(d, virq) )
>          return false;
> =20
>      return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
> diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
> index 6cabd0496d..b2c0e1873a 100644
> --- a/xen/arch/arm/vgic/vgic.c
> +++ b/xen/arch/arm/vgic/vgic.c
> @@ -718,6 +718,11 @@ bool vgic_reserve_virq(struct domain *d, unsigned in=
t virq)
>      return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
>  }
> =20
> +bool vgic_is_valid_line(struct domain *d, unsigned int virq)
> +{
> +    return virq < vgic_num_irqs(d);
> +}

> +
>  int vgic_allocate_virq(struct domain *d, bool spi)
>  {
>      int first, end;

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 04/11] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Topic: [PATCH v3 04/11] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcFpJ/t39ssss6a0y8SPAQeD5PEA==
Date: Tue, 26 Aug 2025 20:16:39 +0000
Message-ID: <87zfbl4z4p.fsf@epam.com>
References: 
	<8b42416d779537d6a0ac4902cabc549253b9da9d.1756216943.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <8b42416d779537d6a0ac4902cabc549253b9da9d.1756216943.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Tue, 26 Aug 2025 14:05:37 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> Currently, Xen does not support eSPI interrupts, leading
> to a data abort when such interrupts are defined in the DTS.
>
> This patch introduces a separate array to initialize up to
> 1024 interrupt descriptors in the eSPI range and adds the
> necessary defines and helper function. These changes lay the
> groundwork for future implementation of full eSPI interrupt
> support. As this GICv3.1 feature is not required by all vendors,
> all changes are guarded by ifdefs, depending on the corresponding
> Kconfig option.
>
> Signed-off-by: Leonid Komarianskyi 

Reviewed-by: Volodymyr Babchuk 

>
> ---
> Changes in V2:
> - use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
> - remove unnecessary comment for nr_irqs initialization
>
> Changes in V3:
> - introduced a new define NR_ESPI_IRQS to avoid confusion, like in the
>   case of using NR_IRQS for espi_desc array
> - implemented helper functions espi_to_desc and init_espi_data to make
>   it possible to add stubs with the same name, and as a result, reduce
>   the number of #ifdefs
> - change CONFIG_GICV3_ESPI default value to n
> ---
>  xen/arch/arm/Kconfig           |  9 ++++++
>  xen/arch/arm/include/asm/irq.h | 26 +++++++++++++++++
>  xen/arch/arm/irq.c             | 52 +++++++++++++++++++++++++++++++++-
>  3 files changed, 86 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index 17df147b25..5813e5b267 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -135,6 +135,15 @@ config GICV3
>  	  Driver for the ARM Generic Interrupt Controller v3.
>  	  If unsure, use the default setting.
> =20
> +config GICV3_ESPI
> +	bool "Extended SPI range support"
> +	depends on GICV3 && !NEW_VGIC
> +	default n
> +	help
> +	  Allow Xen and domains to use interrupt numbers from the extended SPI
> +	  range, from 4096 to 5119. This feature is introduced in GICv3.1
> +	  architecture.
> +
>  config HAS_ITS
>          bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPO=
RTED
>          depends on GICV3 && !NEW_VGIC && !ARM_32
> diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/ir=
q.h
> index 5bc6475eb4..221dbf23a2 100644
> --- a/xen/arch/arm/include/asm/irq.h
> +++ b/xen/arch/arm/include/asm/irq.h
> @@ -32,6 +32,15 @@ struct arch_irq_desc {
>  #define SPI_MAX_INTID   1019
>  #define LPI_OFFSET      8192
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +#define ESPI_BASE_INTID 4096
> +#define ESPI_MAX_INTID  5119
> +#define NR_ESPI_IRQS    1024
> +
> +#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
> +#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
> +#endif
> +
>  /* LPIs are always numbered starting at 8192, so 0 is a good invalid cas=
e. */
>  #define INVALID_LPI     0
> =20
> @@ -39,7 +48,15 @@ struct arch_irq_desc {
>  #define INVALID_IRQ     1023
> =20
>  extern const unsigned int nr_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * This will also cover the eSPI range, as some critical devices
> + * for booting Xen (e.g., serial) may use this type of interrupts.
> + */
> +#define nr_static_irqs (ESPI_MAX_INTID + 1)
> +#else
>  #define nr_static_irqs NR_IRQS
> +#endif
> =20
>  struct irq_desc;
>  struct irqaction;
> @@ -55,6 +72,15 @@ static inline bool is_lpi(unsigned int irq)
>      return irq >=3D LPI_OFFSET;
>  }
> =20
> +static inline bool is_espi(unsigned int irq)
> +{
> +#ifdef CONFIG_GICV3_ESPI
> +    return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID);
> +#else
> +    return false;
> +#endif
> +}
> +
>  #define domain_pirq_to_irq(d, pirq) (pirq)
> =20
>  bool is_assignable_irq(unsigned int irq);
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index b8eccfc924..adb5e49ea3 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -19,7 +19,11 @@
>  #include 
>  #include 
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1;
> +#else
>  const unsigned int nr_irqs =3D NR_IRQS;
> +#endif
> =20
>  static unsigned int local_irqs_type[NR_LOCAL_IRQS];
>  static DEFINE_SPINLOCK(local_irqs_type_lock);
> @@ -46,6 +50,49 @@ void irq_end_none(struct irq_desc *irq)
>  }
> =20
>  static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
> +#ifdef CONFIG_GICV3_ESPI
> +static irq_desc_t espi_desc[NR_ESPI_IRQS];
> +
> +static struct irq_desc *espi_to_desc(unsigned int irq)
> +{
> +    return &espi_desc[ESPI_INTID2IDX(irq)];
> +}
> +
> +static int __init init_espi_data(void)
> +{
> +    int irq;
> +
> +    for ( irq =3D ESPI_BASE_INTID; irq <=3D ESPI_MAX_INTID; irq++ )
> +    {
> +        struct irq_desc *desc =3D irq_to_desc(irq);
> +        int rc =3D init_one_irq_desc(desc);
> +
> +        if ( rc )
> +            return rc;
> +
> +        desc->irq =3D irq;
> +        desc->action  =3D NULL;
> +    }
> +
> +    return 0;
> +}
> +#else
> +/*
> + * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn=
,
> + * because in this case, is_espi will always return false.
> + */
> +static struct irq_desc *espi_to_desc(unsigned int irq)
> +{
> +    ASSERT_UNREACHABLE();
> +    return NULL;
> +}
> +
> +static int __init init_espi_data(void)
> +{
> +    return 0;
> +}
> +#endif
> +
>  static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc);
> =20
>  struct irq_desc *__irq_to_desc(unsigned int irq)
> @@ -53,6 +100,9 @@ struct irq_desc *__irq_to_desc(unsigned int irq)
>      if ( irq < NR_LOCAL_IRQS )
>          return &this_cpu(local_irq_desc)[irq];
> =20
> +    if ( is_espi(irq) )
> +        return espi_to_desc(irq);
> +
>      return &irq_desc[irq-NR_LOCAL_IRQS];
>  }
> =20
> @@ -79,7 +129,7 @@ static int __init init_irq_data(void)
>          desc->action  =3D NULL;
>      }
> =20
> -    return 0;
> +    return init_espi_data();
>  }
> =20
>  static int init_local_irq_data(unsigned int cpu)

--=20
WBR, Volodymyr=


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From: Elliott Mitchell 
To: Jan Beulich 
Cc: Demi Marie Obenour , xen-users@lists.xenproject.org,
        xen-devel@lists.xenproject.org,
        Stefano Stabellini ,
        Julien Grall ,
        Bertrand Marquis ,
        Michal Orzel ,
        Volodymyr Babchuk ,
        Paul Leiber 
Subject: Re: Consider changing CONFIG_ACPI default on ARM?
Message-ID: 
References: 
 
 
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On Mon, Aug 25, 2025 at 10:07:18AM +0200, Jan Beulich wrote:
> On 22.08.2025 22:09, Elliott Mitchell wrote:
> > On Fri, Aug 15, 2025 at 10:14:42AM +0200, Jan Beulich wrote:
> >> On 14.08.2025 23:27, Demi Marie Obenour wrote:
> >>> On 8/14/25 02:55, Jan Beulich wrote:
> >>>>
> >>>> Parties interested in changing the support status of any component are the
> >>>> primary candidates to actually carry out the necessary work.
> >>>
> >>> What is that work?
> >>
> >> To determine what exactly needs doing is part of the exercise. I, for one, am
> >> unaware of a concrete written down set of things which need doing.
> > 
> > Since you're not pointing to anything definite, could it be everything
> > has been resolved?
> 
> Possible. Yet even then the state of things needs fully writing down, perhaps
> in a commit message for the patch changing the support status. That's likely
> still a time consuming job.

Issue is much of this is better done by the people doing those projects.
Most of what I've done is checking a real hardware/software platform and
confirmed functionality.  Presently it boots, but the framebuffer doesn't
work.  VMs appear to work fine though.

How does the attached patch look for enabling ACPI?


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	filename="0001-xen-arm-ACPI-Change-default-configuration.patch"

>From 492ea48f537934e7b54de66c5018c349c0123c9a Mon Sep 17 00:00:00 2001
Message-Id: <492ea48f537934e7b54de66c5018c349c0123c9a.1756239431.git.ehem+xen@m5p.com>
From: Elliott Mitchell 
Date: Wed, 22 Jul 2020 10:43:57 -0700
Subject: [PATCH] xen/arm: ACPI: Change default configuration

Xen/ARM64 support for ACPI has been mostly implemented.  The remaining
issue is handling the IORT table for proper IOMMU support.  This means
systems booting with ACPI will not be protected from misbehaving or
misprogrammed hardware.  Pass-through of hardware will be unsafe.

Systems without an IOMMU are already unsafe so there is no additional
warning.  For such systems defaulting ACPI enabled may allow easier
setup, so change the default.

Presently device-trees are honored before ACPI tables are.  This seems
the best default balance right now.

Signed-off-by: Elliott Mitchell 
---
 xen/arch/arm/Kconfig                  |  7 ++++++-
 xen/drivers/passthrough/arm/smmu-v3.c | 25 +++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 5355534f3d..a420889eb9 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -100,13 +100,18 @@ endchoice
 source "arch/Kconfig"
 
 config ACPI
-	bool "ACPI (Advanced Configuration and Power Interface) Support (UNSUPPORTED)" if UNSUPPORTED
+	bool "ACPI (Advanced Configuration and Power Interface) Support (UNSUPPORTED)"
 	depends on ARM_64 && ARM_EFI
+	default y
 	help
 
 	  Advanced Configuration and Power Interface (ACPI) support for Xen is
 	  an alternative to device tree on ARM64. This requires UEFI.
 
+	  Note this is presently EXPERIMENTAL.  If a given device has both
+	  device-tree and ACPI support, it is presently (September 2025)
+	  recommended to boot using the device-tree.
+
 config ARM_EFI
 	bool "UEFI boot service support"
 	depends on ARM_64 && !MPU
diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c
index 5e9e3e048e..580da2e210 100644
--- a/xen/drivers/passthrough/arm/smmu-v3.c
+++ b/xen/drivers/passthrough/arm/smmu-v3.c
@@ -82,6 +82,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -2364,6 +2365,9 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
 	return 0;
 }
 
+static bool allow_ignore_iort = false;
+boolean_param("allow_ignore_iort", allow_ignore_iort);
+
 #ifdef CONFIG_ACPI
 static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu)
 {
@@ -2386,6 +2390,23 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
 	struct device *dev = smmu->dev;
 	struct acpi_iort_node *node;
 
+	if (!allow_ignore_iort) {
+		printk(XENLOG_ERR
+"A SMMUv3 is present, but only ACPI support is present in firmware.  At this\n"
+"time Xen's ACPI support is incomplete.  In particular Xen is unable to make\n"
+"use of IORT tables and is thus unable to make use of IOMMU functionality.\n"
+"Booting in this configuration disables protection against malicious or\n"
+"malfunctioning hardware.  This also compromises pass-through of hardware.\n"
+"\n"
+"If you accept the risks of booting without IOMMU support, you can add\n"
+"\"allow_ignore_iort=true\" to Xen's command-line.  You are also welcome to\n"
+"sponsor implementing support for IORT tables.\n");
+
+		panic("SMMUv3 is present, but IORT support is incomplete\n");
+	}
+
+	printk(XENLOG_ERR "using incomplete IORT due to command-line param\n");
+
 	node = *(struct acpi_iort_node **)dev_get_platdata(dev);
 
 	/* Retrieve SMMUv3 specific data */
@@ -2402,6 +2423,10 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
 static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev,
 					     struct arm_smmu_device *smmu)
 {
+	if (allow_ignore_iort)
+		printk(XENLOG_INFO "allow_ignore_iort has been set, but ACPI "
+			"support is absent\n");
+
 	return -ENODEV;
 }
 #endif
-- 
2.39.5


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init-dom0less passes the assorted xen library handles from main
downward.  This is a little excessive in places with 4 handles passed
into configure_xenstore().

Replace the handle passing with file-scoped variables.

The xenstore helpers are not changed.  This keeps their implementation
common with the libxenstore functions that take a handle, transation,
and then additional arguments.

Suggested-by: Juergen Gross 
Signed-off-by: Jason Andryuk 
---
v3:
New
---
 tools/helpers/init-dom0less.c | 37 +++++++++++++++--------------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/tools/helpers/init-dom0less.c b/tools/helpers/init-dom0less.c
index a182dce563..0b0be08449 100644
--- a/tools/helpers/init-dom0less.c
+++ b/tools/helpers/init-dom0less.c
@@ -18,8 +18,12 @@
 #define XENSTORE_PFN_OFFSET 1
 #define STR_MAX_LENGTH 128
 
-static int alloc_xs_page(struct xc_interface_core *xch,
-                         libxl_dominfo *info,
+static libxl_ctx *ctx;
+static struct xs_handle *xsh;
+static struct xc_interface_core *xch;
+static xenforeignmemory_handle *xfh;
+
+static int alloc_xs_page(libxl_dominfo *info,
                          uint64_t *xenstore_pfn)
 {
     int rc;
@@ -43,8 +47,7 @@ static int alloc_xs_page(struct xc_interface_core *xch,
     return 0;
 }
 
-static int get_xs_page(struct xc_interface_core *xch, libxl_dominfo *info,
-                       uint64_t *xenstore_pfn)
+static int get_xs_page(libxl_dominfo *info, uint64_t *xenstore_pfn)
 {
     int rc;
 
@@ -111,8 +114,7 @@ static bool do_xs_write_vm(struct xs_handle *xsh, xs_transaction_t t,
  * The list was retrieved by running xenstore-ls on a corresponding
  * domain started by xl/libxl.
  */
-static int create_xenstore(struct xs_handle *xsh,
-                           libxl_dominfo *info, libxl_uuid uuid,
+static int create_xenstore(libxl_dominfo *info, libxl_uuid uuid,
                            uint64_t xenstore_pfn,
                            evtchn_port_t xenstore_port)
 {
@@ -235,10 +237,7 @@ err:
     return rc;
 }
 
-static int init_domain(struct xs_handle *xsh,
-                       struct xc_interface_core *xch,
-                       xenforeignmemory_handle *xfh,
-                       libxl_dominfo *info)
+static int init_domain(libxl_dominfo *info)
 {
     libxl_uuid uuid;
     uint64_t xenstore_evtchn, xenstore_pfn;
@@ -258,13 +257,13 @@ static int init_domain(struct xs_handle *xsh,
         return 0;
 
     /* Get xenstore page */
-    if (get_xs_page(xch, info, &xenstore_pfn) != 0)
+    if (get_xs_page(info, &xenstore_pfn) != 0)
         return 1;
 
     if (xenstore_pfn == ~0ULL) {
         struct xenstore_domain_interface *intf;
 
-        rc = alloc_xs_page(xch, info, &xenstore_pfn);
+        rc = alloc_xs_page(info, &xenstore_pfn);
         if (rc != 0) {
             printf("Error on getting xenstore page\n");
             return 1;
@@ -299,7 +298,7 @@ static int init_domain(struct xs_handle *xsh,
     if (rc)
         err(1, "gen_stub_json_config");
 
-    rc = create_xenstore(xsh, info, uuid, xenstore_pfn, xenstore_evtchn);
+    rc = create_xenstore(info, uuid, xenstore_pfn, xenstore_evtchn);
     if (rc)
         err(1, "writing to xenstore");
 
@@ -310,7 +309,7 @@ static int init_domain(struct xs_handle *xsh,
 }
 
 /* Check if domain has been configured in XS */
-static bool domain_exists(struct xs_handle *xsh, int domid)
+static bool domain_exists(int domid)
 {
     return xs_is_domain_introduced(xsh, domid);
 }
@@ -318,11 +317,7 @@ static bool domain_exists(struct xs_handle *xsh, int domid)
 int main(int argc, char **argv)
 {
     libxl_dominfo *info = NULL;
-    libxl_ctx *ctx;
     int nb_vm = 0, rc = 0, i;
-    struct xs_handle *xsh = NULL;
-    struct xc_interface_core *xch = NULL;
-    xenforeignmemory_handle *xfh = NULL;
 
     /* TODO reuse libxl xsh connection */
     xsh = xs_open(0);
@@ -355,9 +350,9 @@ int main(int argc, char **argv)
             continue;
 
         printf("Checking domid: %u\n", domid);
-        if (!domain_exists(xsh, domid)) {
-            rc = init_domain(xsh, xch, xfh, &info[i]);
-            if (rc < 0) {
+        if (!domain_exists(domid)) {
+            rc = init_domain(&info[i]);
+            if (rc) {
                 fprintf(stderr, "init_domain failed.\n");
                 goto out;
             }
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Anthony PERARD
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel 
Subject: [PATCH v3 0/8] init-dom0less and dom0less xenstore evtchn
Date: Tue, 26 Aug 2025 17:08:39 -0400
Message-ID: <20250826210847.126015-1-jason.andryuk@amd.com>
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These are the init-dom0less and dom0less xenstore evtchn changes split
from https://lore.kernel.org/xen-devel/20250716211504.291104-1-jason.andryuk@amd.com/

The xenstored changes have already gone in.

init-dom0less needs to be changed to handle auto-introduced domains,
which this series does.  Once that is done, dom0less code can populate
the event channel in the xenstore page (which triggers the
auto-population).  The previous posting's ordering of "xen/dom0less:
store xenstore event channel in page" before init-dom0less changes would
have been broken.

Jason Andryuk (8):
  tools/init-dom0less: Make handles global
  tools/init-dom0less: Factor out xenstore setup
  tools/init-dom0less: Only introduce un-introduced domains
  tools/init-dom0less: Switch domain_exists to check xenstore name
  tools/init-dom0less: Use introduced to determine no-enhanced
  tools/init-dom0less: Remove use of err()
  tools/init-dom0less: Continue on error
  xen/dom0less: store xenstore event channel in page

 tools/helpers/init-dom0less.c           | 127 ++++++++++++++++--------
 xen/common/device-tree/dom0less-build.c |   7 ++
 2 files changed, 95 insertions(+), 39 deletions(-)

-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Anthony PERARD
	
Subject: [PATCH v3 3/8] tools/init-dom0less: Only introduce un-introduced domains
Date: Tue, 26 Aug 2025 17:08:42 -0400
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In preparation for supporting already-introduced domain, only call
xs_introduce_domain() if a domain is not already introduced.  Their
xenstore entries will be written, but the xenstore introduction is
skipped.

Signed-off-by: Jason Andryuk 
---
v3:
Reordered
---
 tools/helpers/init-dom0less.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/tools/helpers/init-dom0less.c b/tools/helpers/init-dom0less.c
index 8de8e44ad3..3906c4b61a 100644
--- a/tools/helpers/init-dom0less.c
+++ b/tools/helpers/init-dom0less.c
@@ -319,9 +319,13 @@ static int init_domain(libxl_dominfo *info)
     if (rc)
         err(1, "writing to xenstore");
 
-    rc = xs_introduce_domain(xsh, info->domid, xenstore_pfn, xenstore_evtchn);
-    if (!rc)
-        err(1, "xs_introduce_domain");
+    if (!xs_is_domain_introduced(xsh, info->domid)) {
+        rc = xs_introduce_domain(xsh, info->domid, xenstore_pfn,
+                                 xenstore_evtchn);
+        if (!rc)
+            err(1, "xs_introduce_domain");
+    }
+
     return 0;
 }
 
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Anthony PERARD
	
Subject: [PATCH v3 6/8] tools/init-dom0less: Remove use of err()
Date: Tue, 26 Aug 2025 17:08:45 -0400
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err() is fatal - print a message and exit.  We want init-dom0less to
continue on as much as possible, so replace with returning an error.

Signed-off-by: Jason Andryuk 
---
v3:
New
---
 tools/helpers/init-dom0less.c | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/tools/helpers/init-dom0less.c b/tools/helpers/init-dom0less.c
index a4de40aeac..d08b0b1362 100644
--- a/tools/helpers/init-dom0less.c
+++ b/tools/helpers/init-dom0less.c
@@ -300,8 +300,10 @@ static int configure_xenstore(libxl_dominfo *info,
 
         rc = xc_dom_gnttab_seed(xch, info->domid, true,
                                 (xen_pfn_t)-1, *xenstore_pfn, 0, 0);
-        if (rc)
-               err(1, "xc_dom_gnttab_seed");
+        if (rc) {
+            printf("xc_dom_gnttab_seed");
+            return 1;
+        }
     }
 
     return 0;
@@ -329,18 +331,24 @@ static int init_domain(libxl_dominfo *info)
     xc_domain_sethandle(xch, info->domid, libxl_uuid_bytearray(&uuid));
 
     rc = gen_stub_json_config(info->domid, &uuid);
-    if (rc)
-        err(1, "gen_stub_json_config");
+    if (rc) {
+        printf("gen_stub_json_config");
+        return 1;
+    }
 
     rc = create_xenstore(info, uuid, xenstore_pfn, xenstore_evtchn);
-    if (rc)
-        err(1, "writing to xenstore");
+    if (rc) {
+        printf("writing to xenstore");
+        return 1;
+    }
 
     if (!introduced) {
         rc = xs_introduce_domain(xsh, info->domid, xenstore_pfn,
                                  xenstore_evtchn);
-        if (!rc)
-            err(1, "xs_introduce_domain");
+        if (!rc) {
+            printf("xs_introduce_domain");
+            return 1;
+        }
     }
 
     return 0;
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Anthony PERARD
	
Subject: [PATCH v3 5/8] tools/init-dom0less: Use introduced to determine no-enhanced
Date: Tue, 26 Aug 2025 17:08:44 -0400
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A hardware+xenstore domain will not be able to read HVM params, and
init-dom0less reads HVM_PARAM_STORE_EVTCHN to determine whether or not
a domain has xenstore.

xenstored had a similar issue, and it just tries to map a domain's
reserved grant, GNTTAB_RESERVED_XENSTORE, to see if it is accessible.
If successful, xenstored introduces the domain.  Use the existing
introduced state to determine if init-dom0less should try and read the
param.  If already introduced, initialization (and reading the
HVM_PARAM) is skipped.

This allows for running init-dom0less from a xenstored+hardware domain.
It relies on the local socket xenstore connections being considered
privileged.

oxenstored has not been updated, so the exist code remains for backwards
compatibility.

Signed-off-by: Jason Andryuk 
---
v3:
New
---
 tools/helpers/init-dom0less.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/tools/helpers/init-dom0less.c b/tools/helpers/init-dom0less.c
index eb793c7aab..a4de40aeac 100644
--- a/tools/helpers/init-dom0less.c
+++ b/tools/helpers/init-dom0less.c
@@ -309,16 +309,20 @@ static int configure_xenstore(libxl_dominfo *info,
 
 static int init_domain(libxl_dominfo *info)
 {
-    uint64_t xenstore_evtchn, xenstore_pfn = 0;
+    uint64_t xenstore_evtchn = 0, xenstore_pfn = 0;
+    bool introduced;
     libxl_uuid uuid;
     int rc;
 
-    rc = configure_xenstore(info, &xenstore_evtchn, &xenstore_pfn);
-    if (rc)
-        return rc;
+    introduced = xs_is_domain_introduced(xsh, info->domid);
+    if (!introduced) {
+        rc = configure_xenstore(info, &xenstore_evtchn, &xenstore_pfn);
+        if (rc)
+            return rc;
 
-    if (xenstore_evtchn == 0) {
-        return 0;
+        if (xenstore_evtchn == 0) {
+            return 0;
+        }
     }
 
     libxl_uuid_generate(&uuid);
@@ -332,7 +336,7 @@ static int init_domain(libxl_dominfo *info)
     if (rc)
         err(1, "writing to xenstore");
 
-    if (!xs_is_domain_introduced(xsh, info->domid)) {
+    if (!introduced) {
         rc = xs_introduce_domain(xsh, info->domid, xenstore_pfn,
                                  xenstore_evtchn);
         if (!rc)
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Anthony PERARD
	
Subject: [PATCH v3 2/8] tools/init-dom0less: Factor out xenstore setup
Date: Tue, 26 Aug 2025 17:08:41 -0400
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Factor out the xenstore setup code into configure_xenstore().  This is
in preparation for handling already-introduced domains.

Signed-off-by: Jason Andryuk 
---
v3:
Remove handle passing
---
 tools/helpers/init-dom0less.c | 39 +++++++++++++++++++++++++----------
 1 file changed, 28 insertions(+), 11 deletions(-)

diff --git a/tools/helpers/init-dom0less.c b/tools/helpers/init-dom0less.c
index 0b0be08449..8de8e44ad3 100644
--- a/tools/helpers/init-dom0less.c
+++ b/tools/helpers/init-dom0less.c
@@ -237,40 +237,40 @@ err:
     return rc;
 }
 
-static int init_domain(libxl_dominfo *info)
+static int configure_xenstore(libxl_dominfo *info,
+                              uint64_t *xenstore_evtchn,
+                              uint64_t *xenstore_pfn)
 {
-    libxl_uuid uuid;
-    uint64_t xenstore_evtchn, xenstore_pfn;
     int rc;
 
     printf("Init dom0less domain: %u\n", info->domid);
 
     rc = xc_hvm_param_get(xch, info->domid, HVM_PARAM_STORE_EVTCHN,
-                          &xenstore_evtchn);
+                          xenstore_evtchn);
     if (rc != 0) {
         printf("Failed to get HVM_PARAM_STORE_EVTCHN\n");
         return 1;
     }
 
     /* no xen,enhanced; nothing to do */
-    if (!xenstore_evtchn)
+    if (!*xenstore_evtchn)
         return 0;
 
     /* Get xenstore page */
-    if (get_xs_page(info, &xenstore_pfn) != 0)
+    if (get_xs_page(info, xenstore_pfn) != 0)
         return 1;
 
-    if (xenstore_pfn == ~0ULL) {
+    if (*xenstore_pfn == ~0ULL) {
         struct xenstore_domain_interface *intf;
 
-        rc = alloc_xs_page(info, &xenstore_pfn);
+        rc = alloc_xs_page(info, xenstore_pfn);
         if (rc != 0) {
             printf("Error on getting xenstore page\n");
             return 1;
         }
 
         intf = xenforeignmemory_map(xfh, info->domid, PROT_READ | PROT_WRITE, 1,
-                                    &xenstore_pfn, NULL);
+                                    xenstore_pfn, NULL);
         if (!intf) {
             printf("Error mapping xenstore page\n");
             return 1;
@@ -281,16 +281,33 @@ static int init_domain(libxl_dominfo *info)
 
         /* Now everything is ready: set HVM_PARAM_STORE_PFN */
         rc = xc_hvm_param_set(xch, info->domid, HVM_PARAM_STORE_PFN,
-                xenstore_pfn);
+                              *xenstore_pfn);
         if (rc < 0)
             return rc;
 
         rc = xc_dom_gnttab_seed(xch, info->domid, true,
-                                (xen_pfn_t)-1, xenstore_pfn, 0, 0);
+                                (xen_pfn_t)-1, *xenstore_pfn, 0, 0);
         if (rc)
                err(1, "xc_dom_gnttab_seed");
     }
 
+    return 0;
+}
+
+static int init_domain(libxl_dominfo *info)
+{
+    uint64_t xenstore_evtchn, xenstore_pfn = 0;
+    libxl_uuid uuid;
+    int rc;
+
+    rc = configure_xenstore(info, &xenstore_evtchn, &xenstore_pfn);
+    if (rc)
+        return rc;
+
+    if (xenstore_evtchn == 0) {
+        return 0;
+    }
+
     libxl_uuid_generate(&uuid);
     xc_domain_sethandle(xch, info->domid, libxl_uuid_bytearray(&uuid));
 
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Anthony PERARD
	
Subject: [PATCH v3 4/8] tools/init-dom0less: Switch domain_exists to check xenstore name
Date: Tue, 26 Aug 2025 17:08:43 -0400
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Previously, the xenstore "introduced" state was used to avoid running
init-dom0less twice on the same domain.  With xenstored
auto-introduction, that can no longer be used.  Instead check of the
domain's name has been set and use that to determine whether or not to
bail out.

Signed-off-by: Jason Andryuk 
---
v3:
Move xenstore reading into domain_exists()
Reorder
---
 tools/helpers/init-dom0less.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/tools/helpers/init-dom0less.c b/tools/helpers/init-dom0less.c
index 3906c4b61a..eb793c7aab 100644
--- a/tools/helpers/init-dom0less.c
+++ b/tools/helpers/init-dom0less.c
@@ -60,6 +60,19 @@ static int get_xs_page(libxl_dominfo *info, uint64_t *xenstore_pfn)
     return 0;
 }
 
+static char *do_xs_read_dom(struct xs_handle *xsh, xs_transaction_t t,
+                            domid_t domid, char *path)
+{
+    char full_path[STR_MAX_LENGTH];
+    int rc;
+
+    rc = snprintf(full_path, STR_MAX_LENGTH,
+                  "/local/domain/%u/%s", domid, path);
+    if (rc < 0 || rc >= STR_MAX_LENGTH)
+        return NULL;
+    return xs_read(xsh, t, full_path, NULL);
+}
+
 static bool do_xs_write_dom(struct xs_handle *xsh, xs_transaction_t t,
                             domid_t domid, char *path, char *val)
 {
@@ -332,7 +345,13 @@ static int init_domain(libxl_dominfo *info)
 /* Check if domain has been configured in XS */
 static bool domain_exists(int domid)
 {
-    return xs_is_domain_introduced(xsh, domid);
+    char *name = do_xs_read_dom(xsh, XBT_NULL, domid, "name");
+    if (name) {
+        free(name);
+        return true;
+    }
+
+    return false;
 }
 
 int main(int argc, char **argv)
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Anthony PERARD
	
Subject: [PATCH v3 7/8] tools/init-dom0less: Continue on error
Date: Tue, 26 Aug 2025 17:08:46 -0400
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An error on one domain doesn't apply to others.  Continue the loop over
all domains if init_domain() fails.

There is a mix of positive and negative errors.  0 is success, so just
check for that.

The last rc value is used as the exit value, so clear it before the end.
This avoids a stale rc value indicating failure.

Signed-off-by: Jason Andryuk 
---
v3:
Use != 0 since there are both positive and negative errors
---
 tools/helpers/init-dom0less.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tools/helpers/init-dom0less.c b/tools/helpers/init-dom0less.c
index d08b0b1362..ce70ddee29 100644
--- a/tools/helpers/init-dom0less.c
+++ b/tools/helpers/init-dom0less.c
@@ -406,12 +406,14 @@ int main(int argc, char **argv)
             rc = init_domain(&info[i]);
             if (rc) {
                 fprintf(stderr, "init_domain failed.\n");
-                goto out;
             }
         } else {
             printf("Domain %u has already been initialized\n", domid);
         }
     }
+
+    rc = 0;
+
 out:
     libxl_dominfo_list_free(info, nb_vm);
     return rc;
-- 
2.50.1



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From: Jason Andryuk 
To: 
CC: Jason Andryuk , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: [PATCH v3 8/8] xen/dom0less: store xenstore event channel in page
Date: Tue, 26 Aug 2025 17:08:47 -0400
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Write the associated event channel into the xenstore page so xenstored
can read it.  xenstored can map the grant by the reserved grant table
entry, and then read out the event channel and bind it.  This eliminates
the need for an additional mechanism to discover the event channel.

Signed-off-by: Jason Andryuk 
---
v2:
No change

This should go in after the init-dom0less changes so init-dom0less is
ready for xenstored automatically introducing domains.

I'm looking for feedback.  This is ARM-only for the time being, but that
is the only in-tree user of this code.  From the perspective, it is okay
to go in.

If we want a cross-arch approach, a common function to write to guest
physical addresses would be needed for additional arches, but they
aren't available yet.

Oleksii added a function pointer to dtb_load() and initrd_load() when
moving dom0less to common, but I think that isn't necessary.  Just
having a common helper would be sufficient.

copy_to_guest_phys() or something_copy_to_guest_phys() could be defined
or a wrapper for ARM's copy_to_guest_phys_flush_dcache().  Other arches
could need to implement it when using dom0less.

I'm not an ARM expert, but Stefano said
copy_to_guest_phys_flush_dcache() is not necessary since this xenstore
page isn't expected to be accessed without caches enabled.
---
 xen/common/device-tree/dom0less-build.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c
index badc227031..1a40f68837 100644
--- a/xen/common/device-tree/dom0less-build.c
+++ b/xen/common/device-tree/dom0less-build.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 
+#include 
 #include 
 
 #include 
@@ -120,8 +121,14 @@ static void __init initialize_domU_xenstore(void)
 
         if ( gfn != XENSTORE_PFN_LATE_ALLOC && IS_ENABLED(CONFIG_GRANT_TABLE) )
         {
+            evtchn_port_t port = d->arch.hvm.params[HVM_PARAM_STORE_EVTCHN];
+            paddr_t evtchn_gaddr = gfn_to_gaddr(_gfn(gfn)) +
+                offsetof(struct xenstore_domain_interface, evtchn_port);
+
             ASSERT(gfn < UINT32_MAX);
             gnttab_seed_entry(d, GNTTAB_RESERVED_XENSTORE, xs_domid, gfn);
+            access_guest_memory_by_gpa(d, evtchn_gaddr, &port, sizeof(port),
+                                       true /* is_write */);
         }
     }
 }
-- 
2.50.1



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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Topic: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcFpJ/0RYrIev2JkmWYheOK3kVZw==
Date: Tue, 26 Aug 2025 22:25:01 +0000
Message-ID: <87tt1t4t6s.fsf@epam.com>
References: 
	<398ad09617f4f97d57d13fa9f3771bd2db83916b.1756216943.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <398ad09617f4f97d57d13fa9f3771bd2db83916b.1756216943.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Tue, 26 Aug 2025 14:05:37 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> Introduced appropriate register definitions, helper macros,
> and initialization of required GICv3.1 distributor registers
> to support eSPI. This type of interrupt is handled in the
> same way as regular SPI interrupts, with the following
> differences:
>
> 1) eSPIs can have up to 1024 interrupts, starting from the
> beginning of the range, whereas regular SPIs use INTIDs from
> 32 to 1019, totaling 988 interrupts;
> 2) eSPIs start at INTID 4096, necessitating additional interrupt
> index conversion during register operations.
>
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
>
> Signed-off-by: Leonid Komarianskyi 

With nit fixed:

Reviewed-by: Volodymyr Babchuk 

>
> ---
> Changes in V2:
> - move gic_number_espis function from
>   [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
>   to use it in the newly introduced gic_is_valid_espi
> - add gic_is_valid_espi which checks if IRQ number is in supported
>   by HW eSPI range
> - update gic_is_valid_irq conditions to allow operations with eSPIs
>
> Changes in V3:
> - add __init attribute to gicv3_dist_espi_common_init
> - change open-codded eSPI register initialization to the appropriate
>   gen-mask macro
> - fixed formatting for lines with more than 80 symbols
> - introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
>   CONFIG_GICV3_ESPI disabled
> - renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
>   (name was taken from GIC specification) to avoid confusion
> - changed type for i variable to unsigned int since it cannot be
>   negative
> ---
>  xen/arch/arm/gic-v3.c                  | 80 ++++++++++++++++++++++++++
>  xen/arch/arm/include/asm/gic.h         | 21 +++++++
>  xen/arch/arm/include/asm/gic_v3_defs.h | 34 +++++++++++
>  3 files changed, 135 insertions(+)
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index a959fefebe..3aa5cc1765 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_d=
esc *irqd, u32 offset)
>          default:
>              break;
>          }
> +#ifdef CONFIG_GICV3_ESPI
> +    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
> +    {
> +        u32 irq_index =3D ESPI_INTID2IDX(irqd->irq);
> +
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ICENABLER:
> +            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ISPENDR:
> +            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ICPENDR:
> +            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ISACTIVER:
> +            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICACTIVER:
> +            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTERnE + irq_index * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYRnE + irq_index);
> +        default:
> +            break;
> +        }
> +    }
> +#endif
>      default:
>          break;
>      }
> @@ -655,6 +685,52 @@ static void gicv3_set_irq_priority(struct irq_desc *=
desc,
>      spin_unlock(&gicv3.lock);
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +unsigned int gic_number_espis(void)
> +{
> +    return gic_hw_ops->info->nr_espi;
> +}
> +
> +static void __init gicv3_dist_espi_common_init(uint32_t type)
> +{
> +    unsigned int espi_nr, i;
> +
> +    espi_nr =3D min(1024U, GICD_TYPER_ESPIS_NUM(type));
> +    gicv3_info.nr_espi =3D espi_nr;
> +    /* The GIC HW doesn't support eSPI, so we can leave from here */
> +    if ( gicv3_info.nr_espi =3D=3D 0 )
> +        return;
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 16 )
> +        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 4 )
> +        writel_relaxed(GIC_PRI_IRQ_ALL,
> +                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 32 )
> +    {
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i / 32=
) * 4);
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i / 32=
) * 4);
> +    }
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 32 )
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) =
* 4);
> +}
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
> +{
> +    unsigned int i;
> +
> +    for ( i =3D 0; i < gicv3_info.nr_espi; i++ )
> +        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * =
8);
> +}
> +#else
> +static void __init gicv3_dist_espi_common_init(uint32_t type) { }
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
> +#endif
> +
>  static void __init gicv3_dist_init(void)
>  {
>      uint32_t type;
> @@ -700,6 +776,8 @@ static void __init gicv3_dist_init(void)
>      for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i +=3D 32 )
>          writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * =
4);
> =20
> +    gicv3_dist_espi_common_init(type);
> +
>      gicv3_dist_wait_for_rwp();
> =20
>      /* Turn on the distributor */
> @@ -713,6 +791,8 @@ static void __init gicv3_dist_init(void)
> =20
>      for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
>          writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8)=
;
> +
> +    gicv3_dist_espi_init_aff(affinity);
>  }
> =20
>  static int gicv3_enable_redist(void)
> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gi=
c.h
> index c7e3b4ff0d..3f1269f0c8 100644
> --- a/xen/arch/arm/include/asm/gic.h
> +++ b/xen/arch/arm/include/asm/gic.h
> @@ -306,8 +306,25 @@ extern void gic_dump_vgic_info(struct vcpu *v);
> =20
>  /* Number of interrupt lines */
>  extern unsigned int gic_number_lines(void);
> +#ifdef CONFIG_GICV3_ESPI
> +extern unsigned int gic_number_espis(void);
> +
> +static inline bool gic_is_valid_espi(unsigned int irq)
> +{
> +    return (irq >=3D ESPI_BASE_INTID &&
> +            irq < ESPI_IDX2INTID(gic_number_espis()));
> +}
> +#else
> +static inline bool gic_is_valid_espi(unsigned int irq)
> +{
> +    return false;
> +}
> +#endif

You need an empty line here

>  static inline bool gic_is_valid_line(unsigned int irq)
>  {
> +    if ( gic_is_valid_espi(irq) )
> +        return true;
> +
>      return irq < gic_number_lines();
>  }
> =20
> @@ -325,6 +342,10 @@ struct gic_info {
>      enum gic_version hw_version;
>      /* Number of GIC lines supported */
>      unsigned int nr_lines;
> +#ifdef CONFIG_GICV3_ESPI
> +    /* Number of GIC eSPI supported */
> +    unsigned int nr_espi;
> +#endif
>      /* Number of LR registers */
>      uint8_t nr_lrs;
>      /* Maintenance irq number */
> diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/includ=
e/asm/gic_v3_defs.h
> index 2af093e774..d38a3d08c7 100644
> --- a/xen/arch/arm/include/asm/gic_v3_defs.h
> +++ b/xen/arch/arm/include/asm/gic_v3_defs.h
> @@ -37,6 +37,40 @@
>  #define GICD_IROUTER1019             (0x7FD8)
>  #define GICD_PIDR2                   (0xFFE8)
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/* Additional registers for GICv3.1 */
> +#define GICD_IGROUPRnE               (0x1000)
> +#define GICD_IGROUPRnEN              (0x107C)
> +#define GICD_ISENABLERnE             (0x1200)
> +#define GICD_ISENABLERnEN            (0x127C)
> +#define GICD_ICENABLERnE             (0x1400)
> +#define GICD_ICENABLERnEN            (0x147C)
> +#define GICD_ISPENDRnE               (0x1600)
> +#define GICD_ISPENDRnEN              (0x167C)
> +#define GICD_ICPENDRnE               (0x1800)
> +#define GICD_ICPENDRnEN              (0x187C)
> +#define GICD_ISACTIVERnE             (0x1A00)
> +#define GICD_ISACTIVERnEN            (0x1A7C)
> +#define GICD_ICACTIVERnE             (0x1C00)
> +#define GICD_ICACTIVERnEN            (0x1C7C)
> +#define GICD_IPRIORITYRnE            (0x2000)
> +#define GICD_IPRIORITYRnEN           (0x23FC)
> +#define GICD_ICFGRnE                 (0x3000)
> +#define GICD_ICFGRnEN                (0x30FC)
> +#define GICD_IROUTERnE               (0x8000)
> +#define GICD_IROUTERnEN              (0x9FFC)
> +
> +#define GICD_TYPER_ESPI_SHIFT        8
> +#define GICD_TYPER_ESPI_RANGE_SHIFT  27
> +#define GICD_TYPER_ESPI_RANGE_MASK   (0x1F)
> +#define GICD_TYPER_ESPI              (1U << GICD_TYPER_ESPI_SHIFT)
> +#define GICD_TYPER_ESPI_RANGE(espi_range) ((((espi_range) & \
> +        GICD_TYPER_ESPI_RANGE_MASK) + 1) * 32)
> +#define GICD_TYPER_ESPIS_NUM(typer)    \
> +        (((typer) & GICD_TYPER_ESPI) ? \
> +        GICD_TYPER_ESPI_RANGE((typer) >> GICD_TYPER_ESPI_RANGE_SHIFT) : =
0)
> +#endif
> +
>  /* Common between GICD_PIDR2 and GICR_PIDR2 */
>  #define GIC_PIDR2_ARCH_MASK         (0xf0)
>  #define GIC_PIDR2_ARCH_GICv3        (0x30)

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 06/11] xen/arm/irq: allow eSPI processing in the do_IRQ
 function
Thread-Topic: [PATCH v3 06/11] xen/arm/irq: allow eSPI processing in the
 do_IRQ function
Thread-Index: AQHcFpJ/78TDbVIRnkOE9iNbqduJVA==
Date: Tue, 26 Aug 2025 22:30:35 +0000
Message-ID: <87ldn54sxh.fsf@epam.com>
References: 
	
In-Reply-To:
 
	(Leonid Komarianskyi's message of "Tue, 26 Aug 2025 14:05:37 +0000")
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Hi,

Leonid Komarianskyi  writes:

> The do_IRQ() function is the main handler for processing IRQs.

but you are making change to gic_interrupt() function... I think you
need to update the commit message and subject.

> Currently, due to restrictive checks, it does not process interrupt
> numbers greater than 1024. This patch updates the condition to allow

But check reads "irq < 1020"...

> the handling of interrupts from the eSPI range.
>

With commit message fixed:

Reviewed-by: Volodymyr Babchuk 

> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - no changes
>
> Changes in V3:
> - no changes
> ---
>  xen/arch/arm/gic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index b88237ccda..634b77c987 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -341,7 +341,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is=
_fiq)
>          /* Reading IRQ will ACK it */
>          irq =3D gic_hw_ops->read_irq();
> =20
> -        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) )
> +        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) || is_esp=
i(irq) )
>          {
>              isb();
>              do_IRQ(regs, irq, is_fiq);

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 07/11] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
 allow eSPI processing
Thread-Topic: [PATCH v3 07/11] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
 allow eSPI processing
Thread-Index: AQHcFpKAYFxN4fU1Wk6sdm7zcMlbgA==
Date: Tue, 26 Aug 2025 22:40:59 +0000
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References: 
	<20a8af6879ef06af92d3cd1e0519c406792ca088.1756216943.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <20a8af6879ef06af92d3cd1e0519c406792ca088.1756216943.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Tue, 26 Aug 2025 14:05:38 +0000")
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Leonid Komarianskyi  writes:

> To properly deactivate guest interrupts and allow them to be retriggered
> after the initial trigger, the LR needs to be updated. The current
> implementation ignores interrupts outside the range specified by the mask
> 0x3FF, which only covers IRQ numbers up to 1023. To enable processing of
> eSPI interrupts, this patch updates the mask to 0x13FF.
>
> Signed-off-by: Leonid Komarianskyi 

Reviewed-by: Volodymyr Babchuk 

>
> ---
> Changes in V2:
> - remove unnecessary CONFIG_GICV3_ESPI ifdef guard
>
> Changes in V3:
> - no changes
> ---
>  xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/includ=
e/asm/gic_v3_defs.h
> index d38a3d08c7..ca403131bd 100644
> --- a/xen/arch/arm/include/asm/gic_v3_defs.h
> +++ b/xen/arch/arm/include/asm/gic_v3_defs.h
> @@ -207,7 +207,7 @@
>  #define ICH_LR_VIRTUAL_SHIFT         0
>  #define ICH_LR_CPUID_MASK            0x7
>  #define ICH_LR_CPUID_SHIFT           10
> -#define ICH_LR_PHYSICAL_MASK         0x3ff
> +#define ICH_LR_PHYSICAL_MASK         0x13ff
>  #define ICH_LR_PHYSICAL_SHIFT        32
>  #define ICH_LR_STATE_MASK            0x3
>  #define ICH_LR_STATE_SHIFT           62

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 08/11] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Topic: [PATCH v3 08/11] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcFpKACzOaRjOW50q/bIpnflDhkw==
Date: Tue, 26 Aug 2025 23:00:40 +0000
Message-ID: <87a53l4rjb.fsf@epam.com>
References: 
	<88254ec24a25e3d99950fb5041ac6b050aaa1e4a.1756216943.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <88254ec24a25e3d99950fb5041ac6b050aaa1e4a.1756216943.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Tue, 26 Aug 2025 14:05:38 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
> requested by the guest. A new field, ext_shared_irqs, is added
> to the VGIC structure to store information about eSPIs, similar
> to how shared_irqs is used for regular SPIs.
>
> Since the eSPI range starts at INTID 4096 and INTIDs between 1025
> and 4095 are reserved, helper macros are introduced to simplify the
> transformation of indices and to enable easier access to eSPI-specific
> resources. These changes prepare the VGIC for processing eSPIs as
> required by future functionality.
>
> The initialization and deinitialization paths for vgic have been updated
> to allocate and free these resources appropriately. Additionally,
> updated handling of INTIDs greater than 1024, passed from the toolstack
> during domain creation, and verification logic ensures only valid SPI or
> eSPI INTIDs are used.
>
> The existing SPI behavior remains unaffected when guests do not request
> eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
> option is disabled.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - change is_espi_rank to is_valid_espi_rank to verify whether the array
>   element ext_shared_irqs exists. The previous version, is_espi_rank,
>   only checked if the rank index was less than the maximum possible eSPI
>   rank index, but this could potentially result in accessing a
>   non-existing array element. To address this, is_valid_espi_rank was
>   introduced, which ensures that the required eSPI rank exists
> - move gic_number_espis to
>   xen/arm: gicv3: implement handling of GICv3.1 eSPI
> - update vgic_is_valid_irq checks to allow operating with eSPIs
> - remove redundant newline in vgic_allocate_virq
>
> Changes in V3:
> - fixed formatting for lines with more than 80 symbols
> - introduced helper functions to be able to use stubs in case of
>   CONFIG_GICV3_ESPI disabled, and as a result, reduce the number of
>   #ifdefs
> - fixed checks for nr_spis in domain_vgic_init
> - updated comment about nr_spis adjustments with dom0less mention
> - moved comment with additional explanations before checks
> - used unsigned int for indexes since they cannot be negative
> - removed unnecessary parentheses
> - move vgic_ext_rank_offset to the below ifdef guard, to reduce the
>   number of ifdefs
> ---
>  xen/arch/arm/include/asm/vgic.h |  18 +++
>  xen/arch/arm/vgic.c             | 212 +++++++++++++++++++++++++++++++-
>  2 files changed, 227 insertions(+), 3 deletions(-)
>
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 9f437e9838..248b5869e1 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -146,6 +146,10 @@ struct vgic_dist {
>      int nr_spis; /* Number of SPIs */
>      unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
>      struct vgic_irq_rank *shared_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +    struct vgic_irq_rank *ext_shared_irqs;
> +    int nr_espis; /* Number of extended SPIs */
> +#endif
>      /*
>       * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
>       * struct arch_vcpu.
> @@ -243,6 +247,14 @@ struct vgic_ops {
>  /* Number of ranks of interrupt registers for a domain */
>  #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
> +#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
> +#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
> +#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
> +#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
> +#endif
> +
>  #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
>  #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
> =20
> @@ -302,6 +314,12 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct=
 vcpu *v,
>                                                unsigned int b,
>                                                unsigned int n,
>                                                unsigned int s);
> +#ifdef CONFIG_GICV3_ESPI
> +extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
> +                                                  unsigned int b,
> +                                                  unsigned int n,
> +                                                  unsigned int s);
> +#endif
>  extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int =
irq);
>  extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n=
);
>  extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n)=
;
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 2bbf4d99aa..ae4119316f 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -27,9 +27,82 @@
> =20
>  bool vgic_is_valid_line(struct domain *d, unsigned int virq)
>  {
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( virq >=3D ESPI_BASE_INTID &&
> +         virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
> +        return true;
> +#endif
> +
>      return virq < vgic_num_irqs(d);
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * Since eSPI indexes start from 4096 and numbers from 1024 to
> + * 4095 are forbidden, we need to check both lower and upper
> + * limits for ranks.
> + */
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int ran=
k)
> +{
> +    return ( rank >=3D EXT_RANK_MIN &&
> +             EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d) );

Looks like you still have unneeded parentheses :)

> +}
> +
> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
> +                                                       unsigned int rank=
)
> +{
> +    return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)]=
;
> +}
> +
> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int=
 virq)
> +{
> +    return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d),
> +                             d->arch.vgic.allocated_irqs);
> +}
> +
> +static void arch_move_espis(struct vcpu *v)
> +{
> +    const cpumask_t *cpu_mask =3D cpumask_of(v->processor);
> +    struct domain *d =3D v->domain;
> +    struct pending_irq *p;
> +    struct vcpu *v_target;
> +    unsigned int i;
> +
> +    for ( i =3D ESPI_BASE_INTID;
> +          i < EXT_RANK_IDX2NUM(d->arch.vgic.nr_espis); i++ )
> +    {
> +        v_target =3D vgic_get_target_vcpu(v, i);
> +        p =3D irq_to_pending(v_target, i);
> +
> +        if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-=
>status) )
> +            irq_set_affinity(p->desc, cpu_mask);
> +    }
> +}
> +#else
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int ran=
k)
> +{
> +    return false;
> +}
> +
> +/*
> + * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn=
,
> + * because in this case, is_valid_espi_rank will always return false.
> + */
> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
> +                                                       unsigned int rank=
)
> +{
> +    ASSERT_UNREACHABLE();
> +    return NULL;
> +}
> +
> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int=
 virq)
> +{
> +    return false;
> +}
> +
> +static void arch_move_espis(struct vcpu *v) { }
> +#endif
> +
>  static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>                                                    unsigned int rank)
>  {
> @@ -37,6 +110,8 @@ static inline struct vgic_irq_rank *vgic_get_rank(stru=
ct vcpu *v,
>          return v->arch.vgic.private_irqs;
>      else if ( rank <=3D DOMAIN_NR_RANKS(v->domain) )
>          return &v->domain->arch.vgic.shared_irqs[rank - 1];
> +    else if ( is_valid_espi_rank(v->domain, rank) )
> +        return vgic_get_espi_rank(v, rank);
>      else
>          return NULL;
>  }
> @@ -117,6 +192,76 @@ int domain_vgic_register(struct domain *d, unsigned =
int *mmio_count)
>      return 0;
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * The function behaviur is the same as for regular SPIs (vgic_rank_offs=
et),

s/behaviur/behavior

> + * but it operates with extended SPI ranks.
> + */
> +struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int =
b,
> +                                           unsigned int n, unsigned int =
s)
> +{
> +    unsigned int rank =3D REG_RANK_NR(b, (n >> s));
> +
> +    return vgic_get_rank(v, rank + EXT_RANK_MIN);
> +}
> +
> +static unsigned int vgic_num_spi_lines(struct domain *d)
> +{
> +    return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
> +}
> +
> +static int init_vgic_espi(struct domain *d)
> +{
> +    unsigned int i, idx;
> +
> +    if ( d->arch.vgic.nr_espis =3D=3D 0 )
> +        return 0;
> +
> +    d->arch.vgic.ext_shared_irqs =3D
> +        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
> +    if ( d->arch.vgic.ext_shared_irqs =3D=3D NULL )
> +        return -ENOMEM;
> +
> +    for ( i =3D d->arch.vgic.nr_spis, idx =3D 0;
> +          i < vgic_num_spi_lines(d); i++, idx++ )
> +    {

CODING_STYLE says that braces should be omitted for single statements

> +        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i],
> +                              ESPI_IDX2INTID(idx));
> +    }
> +
> +    for ( i =3D 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
> +        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
> +
> +    return 0;
> +}
> +
> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
> +{
> +    irq =3D ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
> +    return &d->arch.vgic.pending_irqs[irq];
> +}
> +#else
> +static unsigned int init_vgic_espi(struct domain *d)
> +{
> +    return 0;
> +}
> +
> +static unsigned int vgic_num_spi_lines(struct domain *d)
> +{
> +    return d->arch.vgic.nr_spis;
> +}
> +
> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
> +{
> +    return NULL;
> +}
> +#endif
> +
> +static unsigned int vgic_num_alloc_irqs(struct domain *d)
> +{
> +    return vgic_num_spi_lines(d) + NR_LOCAL_IRQS;
> +}
> +
>  int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>  {
>      int i;
> @@ -131,6 +276,35 @@ int domain_vgic_init(struct domain *d, unsigned int =
nr_spis)
>       */
>      nr_spis =3D ROUNDUP(nr_spis, 32);
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    /*
> +     * During domain creation, the dom0less DomUs code or toolstack spec=
ifies
> +     * the maximum INTID, which is defined in the domain config subtract=
ed by
> +     * 32 to cover the local IRQs (please see the comment to VGIC_DEF_NR=
_SPIS).
> +     * To compute the actual number of eSPI that will be usable for,
> +     * add back 32.
> +     */
> +    if ( (nr_spis + 32) > ESPI_IDX2INTID(NR_ESPI_IRQS) )
> +        return -EINVAL;

Parentheses around nr_spis + 32 are not required

> +
> +    if ( (nr_spis + 32) >=3D ESPI_BASE_INTID )

The same

> +    {
> +        d->arch.vgic.nr_espis =3D min(nr_spis - ESPI_BASE_INTID + 32, 10=
24U);
> +        /* Verify if GIC HW can handle provided INTID */
> +        if ( d->arch.vgic.nr_espis > gic_number_espis() )
> +            return -EINVAL;
> +        /*
> +         * Set the maximum available number for regular
> +         * SPI to pass the next check
> +         */
> +        nr_spis =3D VGIC_DEF_NR_SPIS;
> +    } else

this "else" should be on separate line

> +    {
> +        /* Domain will use the regular SPI range */
> +        d->arch.vgic.nr_espis =3D 0;
> +    }
> +#endif
> +
>      /* Limit the number of virtual SPIs supported to (1020 - 32) =3D 988=
  */
>      if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
>          return -EINVAL;
> @@ -145,7 +319,7 @@ int domain_vgic_init(struct domain *d, unsigned int n=
r_spis)
>          return -ENOMEM;
> =20
>      d->arch.vgic.pending_irqs =3D
> -        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
> +        xzalloc_array(struct pending_irq, vgic_num_spi_lines(d));
>      if ( d->arch.vgic.pending_irqs =3D=3D NULL )
>          return -ENOMEM;
> =20
> @@ -156,12 +330,16 @@ int domain_vgic_init(struct domain *d, unsigned int=
 nr_spis)
>      for ( i =3D 0; i < DOMAIN_NR_RANKS(d); i++ )
>          vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
> =20
> +    ret =3D init_vgic_espi(d);
> +    if ( ret )
> +        return ret;
> +
>      ret =3D d->arch.vgic.handler->domain_init(d);
>      if ( ret )
>          return ret;
> =20
>      d->arch.vgic.allocated_irqs =3D
> -        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
> +        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_alloc_irqs(d=
)));
>      if ( !d->arch.vgic.allocated_irqs )
>          return -ENOMEM;
> =20
> @@ -195,9 +373,27 @@ void domain_vgic_free(struct domain *d)
>          }
>      }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i =3D 0; i < d->arch.vgic.nr_espis; i++ )
> +    {
> +        struct pending_irq *p =3D spi_to_pending(d, ESPI_IDX2INTID(i));
> +
> +        if ( p->desc )
> +        {
> +            ret =3D release_guest_irq(d, p->irq);
> +            if ( ret )
> +                dprintk(XENLOG_G_WARNING, "d%u: Failed to release virq %=
u ret =3D %d\n",
> +                        d->domain_id, p->irq, ret);
> +        }
> +    }
> +#endif
> +
>      if ( d->arch.vgic.handler )
>          d->arch.vgic.handler->domain_free(d);
>      xfree(d->arch.vgic.shared_irqs);
> +#ifdef CONFIG_GICV3_ESPI
> +    xfree(d->arch.vgic.ext_shared_irqs);
> +#endif
>      xfree(d->arch.vgic.pending_irqs);
>      xfree(d->arch.vgic.allocated_irqs);
>  }
> @@ -331,6 +527,8 @@ void arch_move_irqs(struct vcpu *v)
>          if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-=
>status) )
>              irq_set_affinity(p->desc, cpu_mask);
>      }
> +
> +    arch_move_espis(v);
>  }
> =20
>  void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
> @@ -538,6 +736,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v, un=
signed int irq)
>          n =3D &v->arch.vgic.pending_irqs[irq];
>      else if ( is_lpi(irq) )
>          n =3D v->domain->arch.vgic.handler->lpi_to_pending(v->domain, ir=
q);
> +    else if ( is_espi(irq) )
> +        n =3D espi_to_pending(v->domain, irq);
>      else
>          n =3D &v->domain->arch.vgic.pending_irqs[irq - 32];
>      return n;
> @@ -547,6 +747,9 @@ struct pending_irq *spi_to_pending(struct domain *d, =
unsigned int irq)
>  {
>      ASSERT(irq >=3D NR_LOCAL_IRQS);
> =20
> +    if ( is_espi(irq) )
> +        return espi_to_pending(d, irq);
> +
>      return &d->arch.vgic.pending_irqs[irq - 32];
>  }
> =20
> @@ -668,6 +871,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned int=
 virq)
>      if ( !vgic_is_valid_line(d, virq) )
>          return false;
> =20
> +    if ( is_espi(virq) )
> +        return vgic_reserve_espi_virq(d, virq);
> +
>      return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
>  }
> =20
> @@ -685,7 +891,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
>      else
>      {
>          first =3D 32;
> -        end =3D vgic_num_irqs(d);
> +        end =3D vgic_num_alloc_irqs(d);
>      }
> =20
>      /*

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 09/11] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Topic: [PATCH v3 09/11] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Index: AQHcFpKC3tlPpRwHYEC6FSrd1NYk4Q==
Date: Tue, 26 Aug 2025 23:08:46 +0000
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References: 
	
In-Reply-To:
 
	(Leonid Komarianskyi's message of "Tue, 26 Aug 2025 14:05:38 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> The Dom0 and DomUs logic for the dom0less configuration in create_dom0()
> and arch_create_domUs() has been updated to account for extended SPIs
> when supported by the hardware and enabled with CONFIG_GICV3_ESPI. These
> changes ensure the proper calculation of the maximum number of SPIs and
> eSPIs available to Dom0 and DomUs in dom0less setups.
>
> When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is
> enabled, the maximum number of eSPI interrupts is calculated using the
> ESPI_BASE_INTID offset (4096) and is limited to 1024, with 32 IRQs
> subtracted. To ensure compatibility with DomUs (Dom0 setups) domains,
> where this adjustment is applied by the toolstack during domain
> creation, while for Dom0 or DomUs in Dom0, it is handled directly during
> VGIC initialization. If eSPIs are not supported, the calculation
> defaults to using the standard SPI range, with a maximum value of
> 960 interrupt lines, as it works currently.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V2:
> - no changes
>
> Changes in V3:
> - renamed macro VGIC_DEF_NR_ESPIS to more appropriate VGIC_DEF_MAX_SPI

Will VGIC_DEF_MAX_ESPI be better? When other code refer to "SPI" it mean
"common SPI" (less than 1022), while ESPI is used for extended SPI. So,
naturally it feels that VGIC_DEF_MAX_SPI should be equal to 1022...

> - added eSPI initialization for dom0less setups
> - fixed comment with mentions about dom0less builds
> - fixed formatting for lines with more than 80 symbols
> - updated commit message
> ---
>  xen/arch/arm/dom0less-build.c   | 12 ++++++++++++
>  xen/arch/arm/domain_build.c     | 11 +++++++++++
>  xen/arch/arm/include/asm/vgic.h | 14 ++++++++++++++
>  3 files changed, 37 insertions(+)
>
> diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.=
c
> index 69b9ea22ce..f4f9077db5 100644
> --- a/xen/arch/arm/dom0less-build.c
> +++ b/xen/arch/arm/dom0less-build.c
> @@ -286,6 +286,18 @@ void __init arch_create_domUs(struct dt_device_node =
*node,
>          int vpl011_virq =3D GUEST_VPL011_SPI;
> =20
>          d_cfg->arch.nr_spis =3D VGIC_DEF_NR_SPIS;
> +#ifdef CONFIG_GICV3_ESPI
> +        /*
> +         * Check if the hardware supports extended SPIs (even if the
> +         * appropriate config is set). If not, the common SPI range
> +         * will be used. Otherwise overwrite the nr_spis with the maximu=
m
> +         * available INTID from eSPI range. In that case, the number of
> +         * regular SPIs will be adjusted to the maximum value during vGI=
C
> +         * initialization.
> +         */
> +        if ( gic_number_espis() > 0 )
> +            d_cfg->arch.nr_spis =3D VGIC_DEF_MAX_SPI;
> +#endif
> =20
>          /*
>           * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index d91a71acfd..148a8bdb60 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -2055,6 +2055,17 @@ void __init create_dom0(void)
>      /* The vGIC for DOM0 is exactly emulating the hardware GIC */
>      dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
>      dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS;
> +#ifdef CONFIG_GICV3_ESPI
> +    /*
> +     * Check if the hardware supports extended SPIs (even if the appropr=
iate
> +     * config is set). If not, the common SPI range will be used. Otherw=
ise
> +     * overwrite the nr_spis with the maximum available INTID from eSPI =
range.
> +     * In that case, the number of regular SPIs will be adjusted to the =
maximum
> +     * value during vGIC initialization.
> +     */
> +    if ( gic_number_espis() > 0 )
> +        dom0_cfg.arch.nr_spis =3D VGIC_DEF_MAX_SPI;
> +#endif
>      dom0_cfg.arch.tee_type =3D tee_get_type();
>      dom0_cfg.max_vcpus =3D dom0_max_vcpus();
> =20
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 248b5869e1..0bb025f5d5 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -353,6 +353,20 @@ extern void vgic_check_inflight_irqs_pending(struct =
vcpu *v,
>  /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. =
*/
>  #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * Returns the maximum eSPI INTID, supported by HW GIC, subtracted by 32=
. For
> + * non-Dom0 domains, the toolstack or arch_create_domUs function applies=
 the
> + * same adjustment to cover local IRQs (please, see comment for macro th=
at is
> + * used for regular SPIs - VGIC_DEF_NR_SPIS). We will add back this valu=
e
> + * during VGIC initialization. This ensures consistent handling for Dom0=
 and
> + * other domains. For the regular SPI range interrupts in this case, the
> + * maximum value of VGIC_DEF_NR_SPIS will be used.
> + */
> +#define VGIC_DEF_MAX_SPI (ESPI_BASE_INTID + \
> +                          min(gic_number_espis(), 1024U) - 32)
> +#endif
> +
>  extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
> =20
>  static inline bool vgic_is_spi(struct domain *d, unsigned int virq)

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Milan Djokic 
CC: Julien Grall , Julien Grall ,
	"xen-devel@lists.xenproject.org" , Bertrand
 Marquis , Rahul Singh ,
	Stefano Stabellini , Michal Orzel
	, Jan Beulich ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Anthony PERARD
	, Nick Rosbrook , George Dunlap
	, Juergen Gross , Andrew Cooper
	
Subject: Re: [PATCH 00/20] Add SMMUv3 Stage 1 Support for XEN guests
Thread-Topic: [PATCH 00/20] Add SMMUv3 Stage 1 Support for XEN guests
Thread-Index: AQHcB7wdmg15F24Gc0ClRsxpCVedRA==
Date: Tue, 26 Aug 2025 23:28:48 +0000
Message-ID: <87v7m93bo0.fsf@epam.com>
References: 
	
	<12ba4388-ee23-4e17-910f-9702271865ad@epam.com>
	
	
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Date: Tue, 26 Aug 2025 16:51:05 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Nicola Vetrini 
cc: Dmytro Prokopchuk1 , 
    Jan Beulich , 
    Stefano Stabellini , 
    Doug Goldstein , 
    Andrew Cooper , 
    Anthony PERARD , 
    Michal Orzel , Julien Grall , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    xen-devel@lists.xenproject.org
Subject: Re: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
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References:  <60022d5c-1a9f-4a6d-8df2-bca57cefcf59@suse.com>  <97fe4a398af94ee08a15a586ac4a6b4e@bugseng.com>
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On Tue, 26 Aug 2025, Nicola Vetrini wrote:
> On 2025-08-26 20:07, Dmytro Prokopchuk1 wrote:
> > On 8/25/25 13:07, Jan Beulich wrote:
> > > On 24.08.2025 16:56, Dmytro Prokopchuk1 wrote:
> > > > --- a/docs/misra/deviations.rst
> > > > +++ b/docs/misra/deviations.rst
> > > > @@ -97,6 +97,19 @@ Deviations related to MISRA C:2012 Rules:
> > > >          Xen expects developers to ensure code remains safe and reliable
> > > > in builds,
> > > >          even when debug-only assertions like `ASSERT_UNREACHABLE() are
> > > > removed.
> > > > 
> > > > +   * - R2.1
> > > > +     - The 'BUG()' macro is intentionally used in the 'prepare_acpi()'
> > > > function
> > > > +       in specific build configuration (when the config CONFIG_ACPI is
> > > > not
> > > > +       defined) to trigger an error if ACPI-related features are used
> > > > incorrectly.
> > > > +     - Tagged as `deliberate` for ECLAIR.
> > > 
> > > With
> > > 
> > > #define acpi_disabled true
> > > 
> > > in xen/acpi.h I don't see why we even have that inline stub. When it's
> > > dropped
> > > and the declaration left in place without #ifdef CONFIG_ACPI around it,
> > > the
> > > compiler will DCE the code (much like we arrange for in many other
> > > places). No
> > > deviation needed then.
> > > 
> > > If such a deviation was to be added, it would need disambiguating. A
> > > function
> > > of the given name could appear in x86 as well. That wouldn't be covered by
> > > the
> > > Eclair config then, but it would be covered by the text here.
> > > 
> > > > +   * - R2.1
> > > > +     - The 'BUG()' macro is intentionally used in 'gicv3_do_LPI'() and
> > > > +       'gicv3_its_setup_collection()' functions in specific build
> > > > configuration
> > > > +       (when the config CONFIG_HAS_ITS is not defined) to catch and
> > > > prevent any
> > > > +       unintended execution of code that should only run when ITS is
> > > > available.
> > > > +     - Tagged as `deliberate` for ECLAIR.
> > > 
> > > I didn't look at this, but I would very much hope that something similar
> > > could
> > > be done there as well.
> > > 
> > > Jan
> > 
> > After small changes related to prepare_acpi() function, Misra R2.1
> > violation has gone. The compiler really does DCE:
> > 
> >      if ( acpi_disabled <<< this is TRUE )
> >      {
> >          rc = prepare_dtb_hwdom(d, kinfo);
> >          if ( rc < 0 )
> >              return rc;
> > #ifdef CONFIG_HAS_PCI
> >          rc = pci_host_bridge_mappings(d);
> > #endif
> >      }
> >      else
> >          rc = prepare_acpi(d, kinfo); <<< DCE
> > 
> > I will publish it as separate patch.
> > Thanks to Jan, I really appreciate his help.
> > 
> > 
> > The situation with functions gicv3_do_LPI(),
> > gicv3_its_setup_collection() and config CONFIG_HAS_ITS is little bit
> > different.
> > The compiler can do DCE in case when config CONFIG_HAS_ITS is "y", and
> > Misra R2.1 violation related to these functions also can be resolved.
> > Actually, no changes in source code need for that.
> > But Eclair detects these violations because config CONFIG_HAS_ITS is
> > "n", and source code is really compiled with inline stub functions (with
> > BUG() macro).
> > This is because config CONFIG_HAS_ITS is "experimental/unsupported"
> > 
> >      config HAS_ITS
> >              bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if
> >   UNSUPPORTED
> >          depends on GICV3 && !NEW_VGIC && !ARM_32
> > 
> > and to enable it need to set additional config: "CONFIG_UNSUPPORTED=y".
> > 
> > I tried to test it (added "CONFIG_UNSUPPORTED=y" into
> > automation/gitlab-ci/analyze.yaml file). You can see my CI pipeline:
> > https://eclair-analysis-logs.xenproject.org/fs/var/local/eclair/xen-project.ecdf/xen-project/people/dimaprkp4k/xen/ECLAIR_normal/rule_2.1_gicv3_its_host_has_its_v2/ARM64/11144854092/PROJECT.ecd;/by_service.html#service&kind
> > 
> > Unfortunately, I observed +6 new violations with that additional config
> > "CONFIG_UNSUPPORTED=y".
> > 
> > I don't know how and why these EXTRA_XEN_CONFIG were selected in the
> > file 'automation/gitlab-ci/analyze.yaml'. And are we able to add new
> > configs here ?....
> > 
> 
> You'll have to ask Stefano about that, but I doubt at this stage. Those set of
> configs for Arm and X86 has been selected ~2 years ago.

We have migrated to a new faster ECLAIR runner.

I do not think we should change the existing configuration. If anything,
I would remove options from it rather than add more.

However, we can add additional configurations by creating more ECLAIR
jobs, and thanks to the new runner we should be able to keep up.


From xen-devel-bounces@lists.xenproject.org Wed Aug 27 00:16:44 2025
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Subject: Re: [PATCH v2 3/4] xen/arm64: allow to make aarch32 support optional
Thread-Topic: [PATCH v2 3/4] xen/arm64: allow to make aarch32 support optional
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Hi Grygorii,

Grygorii Strashko  writes:

> From: Grygorii Strashko 
>
> Now Arm64 AArch32 guest support is always enabled and built-in while not
> all Arm64 platforms supports AArch32 (for exmaple on Armv9A) or this
> support might not be needed (Arm64 AArch32 is used quite rarely in embedd=
ed
> systems). More over, when focusing on safety certification, AArch32 relat=
ed
> code in Xen leaves a gap in terms of coverage that cannot really be
> justified in words. This leaves two options: either support it (lots of
> additional testing, requirements and documents would be needed) or compil=
e
> it out.
>
> Hence, this patch introduces basic support to allow make Arm64
> AArch32 guest support optional. The following changes are introduced:
>
> - Introduce Kconfig option CONFIG_ARM64_AARCH32 to allow enable/disable
>   Arm64 AArch32 guest support (default y)
>
> - Introduce is_aarch32_enabled() helper which accounts Arm64 HW capabilit=
y
>   and CONFIG_ARM64_AARCH32 setting
>
> - Introduce arm64_set_domain_type() to configure Arm64 domain type in
>   unified way instead of open coding (d)->arch.type, and account
>   CONFIG_ARM64_AARCH32 configuration.
>
> - toolstack: do not advertise "xen-3.0-armv7l " capability if AArch32 is
>   disabled.
>
> - do not expose EL1 AArch32 support to guest in ID_AA64PFR0_EL1 reg if
>   AArch32 is disabled.
>
> - Set Arm64 domain type to DOMAIN_64BIT by default.
>   - the Arm Xen boot code is handling this case properly already;
>   - for toolstack case the XEN_DOMCTL_set_address_size hypercall handling
>     updated to forcibly configure domain type regardless of current domai=
n
>     type configuration, so toolstack behavior is unchanged.
>
> With CONFIG_ARM64_AARCH32=3Dn the Xen will reject AArch32 guests (kernels=
) if
> configured by user in the following way:
> - Xen boot will fail with panic during dom0 or dom0less domains creation
> - toolstack domain creation will be rejected due to xc_dom_compat_check()
>   failure.
>
> Making Arm64 AArch32 guest support open further possibilities for build
> optimizations of Arm64 AArch32 guest support code.
>
> Signed-off-by: Grygorii Strashko 
> ---
> changes in v2:
> - use Arm64 "cpu_has_el1_32" in all places to check if HW has AArch32 sup=
port
> - rework Arm64 XEN_DOMCTL_set_address_size hypercall handling to work wit=
h any
>   initial domain type set (32bit or 64 bit)
> - fix comments related to macro parameters evaluation issues
> - do not expose EL1 AArch32 support to guest in ID_AA64PFR0_EL1 reg if
>   AArch32 is disabled
>
>  xen/arch/arm/Kconfig                    |  7 ++++
>  xen/arch/arm/arm64/domain-build.c       | 46 +++++++++++++++++++++++--
>  xen/arch/arm/arm64/domctl.c             | 16 +++++----
>  xen/arch/arm/arm64/vsysreg.c            |  9 +++++
>  xen/arch/arm/domain.c                   |  9 +++++
>  xen/arch/arm/domain_build.c             | 21 +++--------
>  xen/arch/arm/include/asm/arm32/domain.h | 12 +++++++
>  xen/arch/arm/include/asm/arm64/domain.h | 23 +++++++++++++
>  xen/arch/arm/setup.c                    |  2 +-
>  9 files changed, 119 insertions(+), 26 deletions(-)
>
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index a0c816047427..bf6dd73caf73 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -266,6 +266,13 @@ config PCI_PASSTHROUGH
>  	help
>  	  This option enables PCI device passthrough
> =20
> +config ARM64_AARCH32
> +	bool "AArch32 Guests support on on ARM64 (UNSUPPORTED)" if UNSUPPORTED

But aarch32 guests are supported... I understand that you wanted to say
"Disabling aarch32 support is unsupported". But currently this entry
reads backwards. I think it should be reworded better. But I have no
idea - how to do this.

> +	depends on ARM_64
> +	default y
> +	help
> +	  This option enables AArch32 Guests on ARM64.
> +
>  endmenu
> =20
>  menu "ARM errata workaround via the alternative framework"
> diff --git a/xen/arch/arm/arm64/domain-build.c b/xen/arch/arm/arm64/domai=
n-build.c
> index 3a89ee46b8c6..5951f002e3af 100644
> --- a/xen/arch/arm/arm64/domain-build.c
> +++ b/xen/arch/arm/arm64/domain-build.c
> @@ -4,13 +4,55 @@
>  #include 
> =20
>  #include 
> +#include 
> +
> +int __init arm64_set_domain_type(struct kernel_info *kinfo)
> +{
> +    struct domain *d =3D kinfo->bd.d;
> +    enum domain_type type;
> +
> +    ASSERT(d);
> +    ASSERT(kinfo);

I don't think there is a sense in asserting that kinfo !=3D NULL after you
dereferenced it retrieve "d"

> +
> +    type =3D kinfo->arch.type;
> +
> +    if ( !is_aarch32_enabled() )
> +    {
> +        ASSERT(d->arch.type =3D=3D DOMAIN_64BIT);
> +
> +        if ( type =3D=3D DOMAIN_32BIT )
> +        {
> +            const char *str =3D "not available";
> +
> +            if ( !IS_ENABLED(CONFIG_ARM64_AARCH32) )
> +                str =3D "disabled";
> +            printk("aarch32 guests support is %s\n", str);

XENLOG_ERROR?

> +            return -EINVAL;
> +        }
> +
> +        return 0;
> +    }
> +
> +    if ( is_sve_domain(d) && type =3D=3D DOMAIN_32BIT )
> +    {
> +        printk("SVE is not available for 32-bit domain\n");

XENLOG_ERROR?

> +        return -EINVAL;
> +    }
> +
> +    d->arch.type =3D type;
> +
> +    return 0;
> +}
> =20
>  #ifdef CONFIG_DOM0LESS_BOOT
>  /* TODO: make arch.type generic ? */
>  void __init set_domain_type(struct domain *d, struct kernel_info *kinfo)
>  {
> -    /* type must be set before allocate memory */
> -    d->arch.type =3D kinfo->arch.type;
> +    int rc;
> +
> +    rc =3D arm64_set_domain_type(kinfo);
> +    if ( rc < 0 )
> +        panic("Unsupported guest type\n");
>  }
>  #endif
> =20
> diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c
> index 8720d126c97d..4f0f143daef8 100644
> --- a/xen/arch/arm/arm64/domctl.c
> +++ b/xen/arch/arm/arm64/domctl.c
> @@ -13,6 +13,11 @@
>  #include 
>  #include 
> =20
> +static void vcpu_switch_to_aarch32_mode(struct vcpu *v)
> +{
> +    v->arch.hcr_el2 &=3D ~HCR_RW;
> +}
> +
>  static long switch_mode(struct domain *d, enum domain_type type)
>  {
>      struct vcpu *v;
> @@ -21,14 +26,14 @@ static long switch_mode(struct domain *d, enum domain=
_type type)
>          return -EINVAL;
>      if ( domain_tot_pages(d) !=3D 0 )
>          return -EBUSY;
> -    if ( d->arch.type =3D=3D type )
> -        return 0;
> =20
>      d->arch.type =3D type;
> =20
> -    if ( is_64bit_domain(d) )
> -        for_each_vcpu(d, v)
> +    for_each_vcpu(d, v)
> +        if ( is_64bit_domain(d) )

Do you really need to check domain type for every vCPU? I think that
original variant was better.

>              vcpu_switch_to_aarch64_mode(v);
> +        else
> +            vcpu_switch_to_aarch32_mode(v);
> =20
>      return 0;
>  }
> @@ -38,7 +43,7 @@ static long set_address_size(struct domain *d, uint32_t=
 address_size)
>      switch ( address_size )
>      {
>      case 32:
> -        if ( !cpu_has_el1_32 )
> +        if ( !is_aarch32_enabled() )
>              return -EINVAL;
>          /* SVE is not supported for 32 bit domain */
>          if ( is_sve_domain(d) )
> @@ -58,7 +63,6 @@ long subarch_do_domctl(struct xen_domctl *domctl, struc=
t domain *d,
>      {
>      case XEN_DOMCTL_set_address_size:
>          return set_address_size(d, domctl->u.address_size.size);
> -

Stray change?

>      default:
>          return -ENOSYS;
>      }
> diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
> index d14258290ff0..9f7e735c9b74 100644
> --- a/xen/arch/arm/arm64/vsysreg.c
> +++ b/xen/arch/arm/arm64/vsysreg.c
> @@ -330,6 +330,15 @@ void do_sysreg(struct cpu_user_regs *regs,
>      {
>          register_t guest_reg_value =3D domain_cpuinfo.pfr64.bits[0];
> =20
> +        if ( !is_aarch32_enabled() )
> +        {
> +            /* do not expose EL1 AArch32 support if disabled */
> +            register_t mask =3D GENMASK(ID_AA64PFR0_EL1_SHIFT + 4 - 1,
> +                                      ID_AA64PFR0_EL1_SHIFT);
> +            guest_reg_value &=3D ~mask;
> +            guest_reg_value |=3D (1 << ID_AA64PFR0_EL1_SHIFT) & mask;

Why do you need to apply mask here?

> +        }
> +
>          if ( is_sve_domain(v->domain) )
>          {
>              /* 4 is the SVE field width in id_aa64pfr0_el1 */
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index 310c5789096d..544d1422a793 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -791,6 +791,15 @@ int arch_domain_create(struct domain *d,
>      d->arch.sve_vl =3D config->arch.sve_vl;
>  #endif
> =20
> +#ifdef CONFIG_ARM_64
> +    /*
> +     * Set default Execution State to AArch64 (64bit)
> +     * - Xen will reconfigure it properly at boot time
> +     * - toolstack will reconfigure it properly by XEN_DOMCTL_set_addres=
s_size
> +     */
> +    d->arch.type =3D DOMAIN_64BIT;
> +#endif
> +
>      return 0;
> =20
>  fail:
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index 47ba920fc6b0..c616127e8da5 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -1873,19 +1873,6 @@ int __init construct_domain(struct domain *d, stru=
ct kernel_info *kinfo)
>      BUG_ON(v->is_initialised);
> =20
>  #ifdef CONFIG_ARM_64
> -    /* if aarch32 mode is not supported at EL1 do not allow 32-bit domai=
n */
> -    if ( !(cpu_has_el1_32) && kinfo->arch.type =3D=3D DOMAIN_32BIT )
> -    {
> -        printk("Platform does not support 32-bit domain\n");
> -        return -EINVAL;
> -    }
> -
> -    if ( is_sve_domain(d) && (kinfo->arch.type =3D=3D DOMAIN_32BIT) )
> -    {
> -        printk("SVE is not available for 32-bit domain\n");
> -        return -EINVAL;
> -    }
> -
>      if ( is_64bit_domain(d) )
>          vcpu_switch_to_aarch64_mode(v);
> =20
> @@ -1983,6 +1970,10 @@ static int __init construct_dom0(struct domain *d)
>      if ( rc < 0 )
>          return rc;
> =20
> +    rc =3D arm64_set_domain_type(&kinfo);
> +    if ( rc < 0 )
> +        return rc;
> +
>      return construct_hwdom(&kinfo, NULL);
>  }
> =20
> @@ -1994,10 +1985,6 @@ int __init construct_hwdom(struct kernel_info *kin=
fo,
> =20
>      iommu_hwdom_init(d);
> =20
> -#ifdef CONFIG_ARM_64
> -    /* type must be set before allocate_memory */
> -    d->arch.type =3D kinfo->arch.type;
> -#endif
>      find_gnttab_region(d, kinfo);
>      if ( is_domain_direct_mapped(d) )
>          allocate_memory_11(d, kinfo);
> diff --git a/xen/arch/arm/include/asm/arm32/domain.h b/xen/arch/arm/inclu=
de/asm/arm32/domain.h
> index 1bd0735c9194..30e8818ff2ae 100644
> --- a/xen/arch/arm/include/asm/arm32/domain.h
> +++ b/xen/arch/arm/include/asm/arm32/domain.h
> @@ -3,11 +3,23 @@
>  #ifndef ARM_ARM32_DOMAIN_H
>  #define ARM_ARM32_DOMAIN_H
> =20
> +struct kernel_info;
> +
>  /* Arm32 always runs guests in AArch32 mode */
> =20
>  #define is_32bit_domain(d) ((void)(d), 1)
>  #define is_64bit_domain(d) ((void)(d), 0)
> =20
> +static inline bool is_aarch32_enabled(void)
> +{
> +    return true;
> +}
> +
> +static inline int arm64_set_domain_type(struct kernel_info *kinfo)
> +{
> +    return 0;
> +}
> +
>  #endif /* ARM_ARM32_DOMAIN_H */
> =20
>  /*
> diff --git a/xen/arch/arm/include/asm/arm64/domain.h b/xen/arch/arm/inclu=
de/asm/arm64/domain.h
> index 1a2d73950bf0..bebcbc582f97 100644
> --- a/xen/arch/arm/include/asm/arm64/domain.h
> +++ b/xen/arch/arm/include/asm/arm64/domain.h
> @@ -3,6 +3,10 @@
>  #ifndef ARM_ARM64_DOMAIN_H
>  #define ARM_ARM64_DOMAIN_H
> =20
> +#include 
> +
> +struct kernel_info;
> +
>  /*
>   * Returns true if guest execution state is AArch32
>   *
> @@ -17,6 +21,25 @@
>   */
>  #define is_64bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_64BIT)
> =20
> +/*
> + * Arm64 declares AArch32 (32bit) Execution State support in the
> + * Processor Feature Registers (PFR0), but also can be disabled manually=
.
> + */
> +static inline bool is_aarch32_enabled(void)
> +{
> +    return IS_ENABLED(CONFIG_ARM64_AARCH32) && cpu_has_el1_32;
> +}
> +
> +/*
> + * Set domain type from struct kernel_info which defines guest Execution
> + * State AArch32/AArch64 during regular dom0 or predefined (dom0less)
> + * domains creation .

Extra space before full stop

> + * Type must be set before allocate_memory or create vcpus.
> + *
> + * @kinfo: pointer to the kinfo structure.
> + */
> +int arm64_set_domain_type(struct kernel_info *kinfo);
> +
>  #endif /* ARM_ARM64_DOMAIN_H */
> =20
>  /*
> diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
> index bb35afe56cec..c29573f0ffec 100644
> --- a/xen/arch/arm/setup.c
> +++ b/xen/arch/arm/setup.c
> @@ -530,7 +530,7 @@ static int __init init_xen_cap_info(void)
>  #ifdef CONFIG_ARM_64
>      safe_strcat(xen_cap_info, "xen-3.0-aarch64 ");
>  #endif
> -    if ( cpu_has_aarch32 )
> +    if ( is_aarch32_enabled() )
>          safe_strcat(xen_cap_info, "xen-3.0-armv7l ");
> =20
>      return 0;

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Grygorii Strashko 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 4/4] xen/arm64: constify is_32/64bit_domain() macro for
 CONFIG_ARM64_AARCH32=n
Thread-Topic: [PATCH v2 4/4] xen/arm64: constify is_32/64bit_domain() macro
 for CONFIG_ARM64_AARCH32=n
Thread-Index: AQHcBrdwDd4mYDTTDkqkhQfu8XlSDA==
Date: Wed, 27 Aug 2025 00:19:07 +0000
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	Strashko's message of "Wed, 6 Aug 2025 09:49:43 +0000")
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Hi,

Grygorii Strashko  writes:

> From: Grygorii Strashko 
>
> Constify is_32/64bit_domain() macro for the case CONFIG_ARM64_AARCH32=3Dn=
 and
> so allow compiler to opt out Aarch32 specific code.
>
> Before (CONFIG_ARM64_AARCH32=3Dy):
>    text	   data	    bss	    dec	    hex	filename
>  859212	 322404	 270880	1452496	 1629d0	xen-syms-before
>
> After (CONFIG_ARM64_AARCH32=3Dn):
>    text	   data	    bss	    dec	    hex	filename
>  851256	 322404	 270880	1444540	 160abc	xen-syms-after
>
> Signed-off-by: Grygorii Strashko 

Reviewed-by: Volodymyr Babchuk 

> ---
> v2:
> - use IS_ENABLED(CONFIG_ARM64_AARCH32) instead of ifdefs
>
>  xen/arch/arm/include/asm/arm64/domain.h | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/xen/arch/arm/include/asm/arm64/domain.h b/xen/arch/arm/inclu=
de/asm/arm64/domain.h
> index bebcbc582f97..70dfbeac7443 100644
> --- a/xen/arch/arm/include/asm/arm64/domain.h
> +++ b/xen/arch/arm/include/asm/arm64/domain.h
> @@ -12,14 +12,16 @@ struct kernel_info;
>   *
>   * @d: pointer to the domain structure
>   */
> -#define is_32bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_32BIT)
> +#define is_32bit_domain(d)                                              =
       \
> +        (IS_ENABLED(CONFIG_ARM64_AARCH32) && (d)->arch.type =3D=3D DOMAI=
N_32BIT)
> =20
>  /*
>   * Returns true if guest execution state is AArch64
>   *
>   * @d: pointer to the domain structure
>   */
> -#define is_64bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_64BIT)
> +#define is_64bit_domain(d)                                              =
       \
> +        (!IS_ENABLED(CONFIG_ARM64_AARCH32) || (d)->arch.type =3D=3D DOMA=
IN_64BIT)
> =20
>  /*
>   * Arm64 declares AArch32 (32bit) Execution State support in the

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Grygorii Strashko 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel ,
	Andrew Cooper , Anthony PERARD
	, Jan Beulich ,
	=?iso-8859-1?Q?Roger_Pau_Monn=E9?= 
Subject: Re: [PATCH v2 1/4] xen/arm: split set_domain_type() between
 arm64/arm32
Thread-Topic: [PATCH v2 1/4] xen/arm: split set_domain_type() between
 arm64/arm32
Thread-Index: AQHcBrdwRN56SCuvyEipomT5fYlVlA==
Date: Wed, 27 Aug 2025 00:22:05 +0000
Message-ID: <87bjo13976.fsf@epam.com>
References: <20250806094929.293658-1-grygorii_strashko@epam.com>
	<20250806094929.293658-2-grygorii_strashko@epam.com>
In-Reply-To: <20250806094929.293658-2-grygorii_strashko@epam.com> (Grygorii
	Strashko's message of "Wed, 6 Aug 2025 09:49:42 +0000")
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Hi,

Grygorii Strashko  writes:

> From: Grygorii Strashko 
>
> Split set_domain_type() between Arm64/Arm32 sub-arches as
> set_domain_type() implementation is going to be extended for Arm64.
>
> Signed-off-by: Grygorii Strashko 
> ---
> v2:
> - no changes, rebase
>
>  xen/arch/arm/arm32/Makefile       |  1 +
>  xen/arch/arm/arm32/domain-build.c | 22 ++++++++++++++++++++++
>  xen/arch/arm/arm64/Makefile       |  1 +
>  xen/arch/arm/arm64/domain-build.c | 24 ++++++++++++++++++++++++
>  xen/arch/arm/dom0less-build.c     | 14 --------------
>  xen/include/xen/dom0less-build.h  |  8 ++++++++
>  6 files changed, 56 insertions(+), 14 deletions(-)
>  create mode 100644 xen/arch/arm/arm32/domain-build.c
>  create mode 100644 xen/arch/arm/arm64/domain-build.c

Is it really worth to create two more source files just for one
function? Maybe it is better to use already existing
xen/arch/arm/arm*/domain.c ?

>
> diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile
> index 531168f58a0a..0fd3f5272361 100644
> --- a/xen/arch/arm/arm32/Makefile
> +++ b/xen/arch/arm/arm32/Makefile
> @@ -6,6 +6,7 @@ obj-y +=3D cache.o
>  obj-$(CONFIG_EARLY_PRINTK) +=3D debug.o
>  obj-y +=3D domctl.o
>  obj-y +=3D domain.o
> +obj-y +=3D domain-build.o
>  obj-y +=3D entry.o
>  obj-y +=3D head.o
>  obj-y +=3D insn.o
> diff --git a/xen/arch/arm/arm32/domain-build.c b/xen/arch/arm/arm32/domai=
n-build.c
> new file mode 100644
> index 000000000000..e34261e4a2ad
> --- /dev/null
> +++ b/xen/arch/arm/arm32/domain-build.c
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#include 
> +#include 
> +
> +#include 
> +
> +#ifdef CONFIG_DOM0LESS_BOOT
> +void __init set_domain_type(struct domain *d, struct kernel_info *kinfo)
> +{
> +    /* Nothing to do */
> +}
> +#endif
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile
> index 6491c5350b2e..3272fe7e4ca2 100644
> --- a/xen/arch/arm/arm64/Makefile
> +++ b/xen/arch/arm/arm64/Makefile
> @@ -8,6 +8,7 @@ obj-$(CONFIG_HARDEN_BRANCH_PREDICTOR) +=3D bpi.o
>  obj-$(CONFIG_EARLY_PRINTK) +=3D debug.o
>  obj-y +=3D domctl.o
>  obj-y +=3D domain.o
> +obj-y +=3D domain-build.o
>  obj-y +=3D entry.o
>  obj-y +=3D head.o
>  obj-y +=3D insn.o
> diff --git a/xen/arch/arm/arm64/domain-build.c b/xen/arch/arm/arm64/domai=
n-build.c
> new file mode 100644
> index 000000000000..3a89ee46b8c6
> --- /dev/null
> +++ b/xen/arch/arm/arm64/domain-build.c
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#include 
> +#include 
> +
> +#include 
> +
> +#ifdef CONFIG_DOM0LESS_BOOT
> +/* TODO: make arch.type generic ? */
> +void __init set_domain_type(struct domain *d, struct kernel_info *kinfo)
> +{
> +    /* type must be set before allocate memory */
> +    d->arch.type =3D kinfo->arch.type;
> +}
> +#endif
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.=
c
> index c8d07213e247..58f77628df1f 100644
> --- a/xen/arch/arm/dom0less-build.c
> +++ b/xen/arch/arm/dom0less-build.c
> @@ -236,20 +236,6 @@ int __init make_arch_nodes(struct kernel_info *kinfo=
)
>      return 0;
>  }
> =20
> -/* TODO: make arch.type generic ? */
> -#ifdef CONFIG_ARM_64
> -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo)
> -{
> -    /* type must be set before allocate memory */
> -    d->arch.type =3D kinfo->arch.type;
> -}
> -#else
> -void __init set_domain_type(struct domain *d, struct kernel_info *kinfo)
> -{
> -    /* Nothing to do */
> -}
> -#endif
> -
>  int __init init_vuart(struct domain *d, struct kernel_info *kinfo,
>                        const struct dt_device_node *node)
>  {
> diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-=
build.h
> index 408859e3255a..3e81d8ba3a47 100644
> --- a/xen/include/xen/dom0less-build.h
> +++ b/xen/include/xen/dom0less-build.h
> @@ -57,6 +57,14 @@ int init_vuart(struct domain *d, struct kernel_info *k=
info,
>  int make_intc_domU_node(struct kernel_info *kinfo);
>  int make_arch_nodes(struct kernel_info *kinfo);
> =20
> +/*
> + * Set domain type from struct kernel_info which defines guest Execution
> + * State 32-bit/64-bit (for Arm AArch32/AArch64).
> + * The domain type must be set before allocate_memory.
> + *
> + * @d: pointer to the domain structure.
> + * @kinfo: pointer to the kinfo structure.
> + */
>  void set_domain_type(struct domain *d, struct kernel_info *kinfo);
> =20
>  int init_intc_phandle(struct kernel_info *kinfo, const char *name,

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Grygorii Strashko 
CC: "xen-devel@lists.xenproject.org" , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Michal Orzel 
Subject: Re: [PATCH v2 2/4] xen/arm: split is_32bit/64bit_domain() between
 arm64/arm32
Thread-Topic: [PATCH v2 2/4] xen/arm: split is_32bit/64bit_domain() between
 arm64/arm32
Thread-Index: AQHcBrdwbCiaA0DkGUiaPFn5+2VGXA==
Date: Wed, 27 Aug 2025 00:23:13 +0000
Message-ID: <875xe9395b.fsf@epam.com>
References: <20250806094929.293658-1-grygorii_strashko@epam.com>
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	Strashko's message of "Wed, 6 Aug 2025 09:49:42 +0000")
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Grygorii Strashko  writes:

> From: Grygorii Strashko 
>
> Split is_32bit/64bit_domain() macro implementations between arm64/arm32.
>
> Signed-off-by: Grygorii Strashko 

Reviewed-by: Volodymyr Babchuk 

> ---
> v2:
> - fix comments related to macro parameters evaluation issues
>
>  xen/arch/arm/include/asm/arm32/domain.h | 20 +++++++++++++++++
>  xen/arch/arm/include/asm/arm64/domain.h | 29 +++++++++++++++++++++++++
>  xen/arch/arm/include/asm/domain.h       |  7 +++---
>  3 files changed, 52 insertions(+), 4 deletions(-)
>  create mode 100644 xen/arch/arm/include/asm/arm32/domain.h
>  create mode 100644 xen/arch/arm/include/asm/arm64/domain.h
>
> diff --git a/xen/arch/arm/include/asm/arm32/domain.h b/xen/arch/arm/inclu=
de/asm/arm32/domain.h
> new file mode 100644
> index 000000000000..1bd0735c9194
> --- /dev/null
> +++ b/xen/arch/arm/include/asm/arm32/domain.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef ARM_ARM32_DOMAIN_H
> +#define ARM_ARM32_DOMAIN_H
> +
> +/* Arm32 always runs guests in AArch32 mode */
> +
> +#define is_32bit_domain(d) ((void)(d), 1)
> +#define is_64bit_domain(d) ((void)(d), 0)
> +
> +#endif /* ARM_ARM32_DOMAIN_H */
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/include/asm/arm64/domain.h b/xen/arch/arm/inclu=
de/asm/arm64/domain.h
> new file mode 100644
> index 000000000000..1a2d73950bf0
> --- /dev/null
> +++ b/xen/arch/arm/include/asm/arm64/domain.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef ARM_ARM64_DOMAIN_H
> +#define ARM_ARM64_DOMAIN_H
> +
> +/*
> + * Returns true if guest execution state is AArch32
> + *
> + * @d: pointer to the domain structure
> + */
> +#define is_32bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_32BIT)
> +
> +/*
> + * Returns true if guest execution state is AArch64
> + *
> + * @d: pointer to the domain structure
> + */
> +#define is_64bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_64BIT)
> +
> +#endif /* ARM_ARM64_DOMAIN_H */
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm=
/domain.h
> index a3487ca71303..dde48178b857 100644
> --- a/xen/arch/arm/include/asm/domain.h
> +++ b/xen/arch/arm/include/asm/domain.h
> @@ -22,11 +22,10 @@ enum domain_type {
>      DOMAIN_32BIT,
>      DOMAIN_64BIT,
>  };
> -#define is_32bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_32BIT)
> -#define is_64bit_domain(d) ((d)->arch.type =3D=3D DOMAIN_64BIT)
> +
> +# include 
>  #else
> -#define is_32bit_domain(d) (1)
> -#define is_64bit_domain(d) (0)
> +# include 
>  #endif
> =20
>  /*

--=20
WBR, Volodymyr=


From xen-devel-bounces@lists.xenproject.org Wed Aug 27 00:33:59 2025
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Date: Tue, 26 Aug 2025 17:33:22 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: jbeulich@suse.com
cc: Oleksii Kurochko , ray.huang@amd.com, 
    Andrew Cooper , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Anthony PERARD , 
    Michal Orzel , Julien Grall , 
    xen-devel@lists.xenproject.org, Penny Zheng , 
    sstabellini@kernel.org
Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
In-Reply-To: 
Message-ID: 
References: <20250815102728.1340505-1-Penny.Zheng@amd.com>   <2035b14e-3836-4e80-9dad-8a49ca90864a@suse.com> 
 <49416df6-83c8-4fa3-bf81-2d1e504ef31b@suse.com> 
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Hi all,

So I ran a test and the appended change, which is based on [1] and
renaming CONFIG_DOMCTL to CONFIG_SYSCTL, is sufficient to resolve the
build issue.

For 4.21, I suggest we go with two patches:
1) global rename of CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
2) stub domctl_lock_acquire/release based on CONFIG_MGMT_HYPERCALLS

Jan, are you OK with this?

Cheers,

Stefano

[1] https://marc.info/?l=xen-devel&m=175421457323598

diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615..dedc73412f 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -148,8 +148,17 @@ void arch_dump_domain_info(struct domain *d);
 
 int arch_vcpu_reset(struct vcpu *v);
 
+#ifdef CONFIG_SYSCTL
 bool domctl_lock_acquire(void);
 void domctl_lock_release(void);
+#else
+static inline bool domctl_lock_acquire(void)
+{
+    return false;
+}
+
+static inline void domctl_lock_release(void) {}
+#endif /* CONFIG_DOMCTL */
 
 /*
  * Continue the current hypercall via func(data) on specified cpu.


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From: "Penny, Zheng" 
To: Oleksii Kurochko , Jan Beulich
	
CC: Xen-devel , Community Manager
	, "committers@xenproject.org"
	, "Huang, Ray" 
Subject: RE: [Reminder] Feature Freeze is Fri Aug 29, 2025
Thread-Topic: [Reminder] Feature Freeze is Fri Aug 29, 2025
Thread-Index: AQHcFqINFTgBbfc5NEmJc3GDXmqQpbR1wBqg
Date: Wed, 27 Aug 2025 02:05:12 +0000
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Date: Tue, 26 Aug 2025 19:09:09 -0700
From: Stefano Stabellini 
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To: Stefano Stabellini 
CC: , Oleksii Kurochko ,
	, Andrew Cooper ,
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Anthony PERARD
	, Michal Orzel , "Julien
 Grall" , , Penny Zheng
	
Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
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On Tue, 26 Aug 2025, Stefano Stabellini wrote:
> Hi all,
> 
> So I ran a test and the appended change, which is based on [1] and
> renaming CONFIG_DOMCTL to CONFIG_SYSCTL, is sufficient to resolve the
> build issue.
> 
> For 4.21, I suggest we go with two patches:
> 1) global rename of CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
> 2) stub domctl_lock_acquire/release based on CONFIG_MGMT_HYPERCALLS
> 
> Jan, are you OK with this?

The other patch doesn't work in the regular case but this patch does. I
ran it through 60+ randconfigs and so far so good. The strategy is still
the same I suggested above for 4.21: global rename, plus one more patch
(this one).


diff --git a/xen/common/Makefile b/xen/common/Makefile
index c316957fcb..352f004a2c 100644
--- a/xen/common/Makefile
+++ b/xen/common/Makefile
@@ -50,7 +50,6 @@ obj-y += spinlock.o
 obj-$(CONFIG_STACK_PROTECTOR) += stack-protector.o
 obj-y += stop_machine.o
 obj-y += symbols.o
-obj-$(CONFIG_SYSCTL) += sysctl.o
 obj-y += tasklet.o
 obj-y += time.o
 obj-y += timer.o
@@ -70,7 +69,10 @@ obj-bin-$(CONFIG_X86) += $(foreach n,decompress bunzip2 unxz unlzma lzo unlzo un
 obj-$(CONFIG_COMPAT) += $(addprefix compat/,domain.o memory.o multicall.o xlat.o)
 
 ifneq ($(CONFIG_PV_SHIM_EXCLUSIVE),y)
+ifeq ($(CONFIG_SYSCTL),y)
 obj-y += domctl.o
+obj-y += sysctl.o
+endif
 endif
 
 extra-y := symbols-dummy.o
diff --git a/xen/include/hypercall-defs.c b/xen/include/hypercall-defs.c
index 8370b4b289..18ab294f94 100644
--- a/xen/include/hypercall-defs.c
+++ b/xen/include/hypercall-defs.c
@@ -194,14 +194,16 @@ kexec_op(unsigned long op, void *uarg)
 #ifdef CONFIG_IOREQ_SERVER
 dm_op(domid_t domid, unsigned int nr_bufs, xen_dm_op_buf_t *bufs)
 #endif
-#ifdef CONFIG_SYSCTL
+#if !defined(CONFIG_PV_SHIM_EXCLUSIVE) && defined(CONFIG_SYSCTL)
 sysctl(xen_sysctl_t *u_sysctl)
 #endif
 #if defined(CONFIG_X86) && defined(CONFIG_PAGING)
 paging_domctl_cont(xen_domctl_t *u_domctl)
 #endif
 #ifndef CONFIG_PV_SHIM_EXCLUSIVE
+#ifdef CONFIG_SYSCTL
 domctl(xen_domctl_t *u_domctl)
+#endif
 platform_op(xen_platform_op_t *u_xenpf_op)
 #endif
 #ifdef CONFIG_HVM
@@ -277,10 +279,8 @@ physdev_op                         compat   do       hvm      hvm      do_arm
 #ifdef CONFIG_HVM
 hvm_op                             do       do       do       do       do
 #endif
-#ifdef CONFIG_SYSCTL
+#if !defined(CONFIG_PV_SHIM_EXCLUSIVE) && defined(CONFIG_SYSCTL)
 sysctl                             do       do       do       do       do
-#endif
-#ifndef CONFIG_PV_SHIM_EXCLUSIVE
 domctl                             do       do       do       do       do
 #endif
 #ifdef CONFIG_KEXEC
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615..cb80e49de1 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -148,8 +148,17 @@ void arch_dump_domain_info(struct domain *d);
 
 int arch_vcpu_reset(struct vcpu *v);
 
+#if !defined(CONFIG_PV_SHIM_EXCLUSIVE) && defined(CONFIG_SYSCTL)
 bool domctl_lock_acquire(void);
 void domctl_lock_release(void);
+#else
+static inline bool domctl_lock_acquire(void)
+{
+    return false;
+}
+
+static inline void domctl_lock_release(void) {}
+#endif /* CONFIG_DOMCTL */
 
 /*
  * Continue the current hypercall via func(data) on specified cpu.
@@ -182,7 +191,7 @@ struct vnuma_info {
     struct xen_vmemrange *vmemrange;
 };
 
-#ifndef CONFIG_PV_SHIM_EXCLUSIVE
+#if !defined(CONFIG_PV_SHIM_EXCLUSIVE) && defined(CONFIG_SYSCTL)
 void vnuma_destroy(struct vnuma_info *vnuma);
 #else
 static inline void vnuma_destroy(struct vnuma_info *vnuma) { ASSERT(!vnuma); }


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To: "xen-devel@lists.xenproject.org" 
Cc: Anthony PERARD 
From: Jan Beulich 
Subject: [PATCH] libxl: except Dom0 from setting PoD target
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Dom0 is never started in PoD mode, and hence it can at "best" do harm if
we try to set a PoD target for it.

Signed-off-by: Jan Beulich 

--- a/tools/libs/light/libxl_mem.c
+++ b/tools/libs/light/libxl_mem.c
@@ -306,7 +306,7 @@ retry_transaction:
         }
     }
 
-    if (d_config.c_info.type != LIBXL_DOMAIN_TYPE_PV) {
+    if (domid && d_config.c_info.type != LIBXL_DOMAIN_TYPE_PV) {
         r = xc_domain_set_pod_target(ctx->xch, domid,
                 (new_target_memkb + size) / 4, NULL, NULL, NULL);
         if (r != 0) {


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Subject: [PATCH] libxl: respect unset video_memkb for Dom0
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Without this, Dom0 will have have a curiously off-by-1 target_memkb
value displayed by "xl list -l".

Signed-off-by: Jan Beulich 
---
In retrieve_domain_configuration_end(), isn't it the wrong way round to
set both ->b_info.target_memkb and ->b_info.max_memkb only after calling
libxl__get_targetmem_fudge(), when that uses the two fields? This way we
could as well use ->b_info->video_memkb directly there.

Of course this may point at a bigger problem, as other fields may
similarly never be set for Dom0.

--- a/tools/libs/light/libxl_internal.h
+++ b/tools/libs/light/libxl_internal.h
@@ -4685,7 +4685,10 @@ uint64_t libxl__get_targetmem_fudge(libx
                                 info->max_memkb > info->target_memkb)
                                 ? LIBXL_MAXMEM_CONSTANT : 0;
 
-    return info->video_memkb + mem_target_fudge;
+    if (info->video_memkb != LIBXL_MEMKB_DEFAULT)
+        mem_target_fudge += info->video_memkb;
+
+    return mem_target_fudge;
 }
 
 int libxl__get_memory_target(libxl__gc *gc, uint32_t domid,


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Callers observing errors elsewhere may be confused by the ENOSYS that
the Flask operation would yield on a Flask-disabled hypervisor.

Signed-off-by: Jan Beulich 
---
Of course I don't know whether clobbering errno is perhaps deemed "fine"
in libxl.

--- a/tools/libs/light/libxl_domain.c
+++ b/tools/libs/light/libxl_domain.c
@@ -277,6 +277,7 @@ void libxl__xcinfo2xlinfo(libxl_ctx *ctx
                           libxl_dominfo *xlinfo)
 {
     size_t size;
+    int saved_errno = errno;
 
     memcpy(&(xlinfo->uuid), xcinfo->handle, sizeof(xen_domain_handle_t));
     xlinfo->domid = xcinfo->domain;
@@ -284,6 +285,7 @@ void libxl__xcinfo2xlinfo(libxl_ctx *ctx
     if (libxl_flask_sid_to_context(ctx, xlinfo->ssidref,
                                    &xlinfo->ssid_label, &size) < 0)
         xlinfo->ssid_label = NULL;
+    errno = saved_errno;
 
     xlinfo->dying      = !!(xcinfo->flags&XEN_DOMINF_dying);
     xlinfo->shutdown   = !!(xcinfo->flags&XEN_DOMINF_shutdown);


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From: Vyacheslav Legoshin 
To: xen-devel@lists.xenproject.org
Cc: Vyacheslav Legoshin ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini 
Subject: [XEN PATCH] x86/vhpet: Add option to always fire hpet timer on resume
Date: Wed, 27 Aug 2025 09:01:08 +0300
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The following issue was observed on Windows 10 21H2 x64+: when the domain state
is saved while all cores are executing the 'halt' instruction, and the memory
save takes a relatively long time (tens of seconds), the HPET counter may
overflow as follows:
counter  = 11243f3e4a
comparator = 910cb70f

In such cases, the fix implemented in commit
b144cf45d50b603c2909fc32c6abf7359f86f1aa does not work (because the 'diff' is
not negative), resulting in the guest VM becoming unresponsive for
approximately 30 seconds.

This patch adds an option to always adjust the HPET timer to fire immediately
after restore.
---
 docs/misc/xen-command-line.pandoc |  9 +++++++++
 xen/arch/x86/hvm/hpet.c           | 21 ++++++++++++++++-----
 2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index a75b6c9301..b28610918f 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -1461,6 +1461,15 @@ HPET can be disabled by specifying `hpet=0`.
 
 Deprecated alternative of `hpet=broadcast`.
 
+### hpet_drift_fix (x86)
+> `= `
+
+> Default: `false`
+
+Always set HPET timer to fire immediately after domain restore.
+This option can be used to fix unresponsive snapshots with modern x64 Windows
+systems (21H2+) which use non-periodic timers.
+
 ### hvm_debug (x86)
 > `= `
 
diff --git a/xen/arch/x86/hvm/hpet.c b/xen/arch/x86/hvm/hpet.c
index f0e5f877f4..5b9e38bd9b 100644
--- a/xen/arch/x86/hvm/hpet.c
+++ b/xen/arch/x86/hvm/hpet.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -222,6 +223,9 @@ static void cf_check hpet_timer_fired(struct vcpu *v, void *data)
  * 1/(2^10) second, namely, 0.9765625 milliseconds */
 #define  HPET_TINY_TIME_SPAN  ((h->stime_freq >> 10) / STIME_PER_HPET_TICK)
 
+bool hpet_drift_fix;
+boolean_param("hpet_drift_fix", hpet_drift_fix);
+
 static void hpet_set_timer(HPETState *h, unsigned int tn,
                            uint64_t guest_time)
 {
@@ -268,11 +272,18 @@ static void hpet_set_timer(HPETState *h, unsigned int tn,
      * are restoring after migrate, treat any wrap as past since the value
      * is unlikely to be 'small'.
      */
-    if ( (int64_t)diff < 0 )
-        diff = (timer_is_32bit(h, tn) &&
-                vhpet_domain(h)->creation_finished &&
-                (-diff > HPET_TINY_TIME_SPAN))
-            ? (uint32_t)diff : 0;
+    if (hpet_drift_fix && !vhpet_domain(h)->creation_finished)
+    {
+        diff = 0;
+    }
+    else
+    {
+        if ( (int64_t)diff < 0 )
+            diff = (timer_is_32bit(h, tn) &&
+                    vhpet_domain(h)->creation_finished &&
+                    (-diff > HPET_TINY_TIME_SPAN))
+                ? (uint32_t)diff : 0;
+    }
 
     destroy_periodic_time(&h->pt[tn]);
     if ( (tn <= 1) && (h->hpet.config & HPET_CFG_LEGACY) )
-- 
2.42.1



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Subject: Re: [PATCH v3 04/11] xen/arm/irq: add handling for IRQs in the eSPI
 range
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <8b42416d779537d6a0ac4902cabc549253b9da9d.1756216943.git.leonid_komarianskyi@epam.com>
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On 26.08.25 17:05, Leonid Komarianskyi wrote:

Hello Leonid


> Currently, Xen does not support eSPI interrupts, leading
> to a data abort when such interrupts are defined in the DTS.
> 
> This patch introduces a separate array to initialize up to
> 1024 interrupt descriptors in the eSPI range and adds the
> necessary defines and helper function. These changes lay the
> groundwork for future implementation of full eSPI interrupt
> support. As this GICv3.1 feature is not required by all vendors,
> all changes are guarded by ifdefs, depending on the corresponding
> Kconfig option.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V2:
> - use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
> - remove unnecessary comment for nr_irqs initialization
> 
> Changes in V3:
> - introduced a new define NR_ESPI_IRQS to avoid confusion, like in the
>    case of using NR_IRQS for espi_desc array
> - implemented helper functions espi_to_desc and init_espi_data to make
>    it possible to add stubs with the same name, and as a result, reduce
>    the number of #ifdefs
> - change CONFIG_GICV3_ESPI default value to n
> ---
>   xen/arch/arm/Kconfig           |  9 ++++++
>   xen/arch/arm/include/asm/irq.h | 26 +++++++++++++++++
>   xen/arch/arm/irq.c             | 52 +++++++++++++++++++++++++++++++++-
>   3 files changed, 86 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index 17df147b25..5813e5b267 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -135,6 +135,15 @@ config GICV3
>   	  Driver for the ARM Generic Interrupt Controller v3.
>   	  If unsure, use the default setting.
>   
> +config GICV3_ESPI
> +	bool "Extended SPI range support"
> +	depends on GICV3 && !NEW_VGIC
> +	default n

Please omit redundant line

> +	help
> +	  Allow Xen and domains to use interrupt numbers from the extended SPI
> +	  range, from 4096 to 5119. This feature is introduced in GICv3.1
> +	  architecture.
> +

[snip]




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Date: Wed, 27 Aug 2025 08:43:57 +0200
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Subject: Re: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
To: Dmytro Prokopchuk1 ,
 Stefano Stabellini 
Cc: Doug Goldstein ,
 Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "xen-devel@lists.xenproject.org" ,
 Nicola Vetrini 
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On 26.08.2025 20:07, Dmytro Prokopchuk1 wrote:
> The situation with functions gicv3_do_LPI(), 
> gicv3_its_setup_collection() and config CONFIG_HAS_ITS is little bit 
> different.
> The compiler can do DCE in case when config CONFIG_HAS_ITS is "y", and 
> Misra R2.1 violation related to these functions also can be resolved.
> Actually, no changes in source code need for that.
> But Eclair detects these violations because config CONFIG_HAS_ITS is 
> "n", and source code is really compiled with inline stub functions (with 
> BUG() macro).
> This is because config CONFIG_HAS_ITS is "experimental/unsupported"
> 
>      config HAS_ITS
>              bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if 
>   UNSUPPORTED
>          depends on GICV3 && !NEW_VGIC && !ARM_32
> 
> and to enable it need to set additional config: "CONFIG_UNSUPPORTED=y".
> 
> I tried to test it (added "CONFIG_UNSUPPORTED=y" into 
> automation/gitlab-ci/analyze.yaml file). You can see my CI pipeline:
> https://eclair-analysis-logs.xenproject.org/fs/var/local/eclair/xen-project.ecdf/xen-project/people/dimaprkp4k/xen/ECLAIR_normal/rule_2.1_gicv3_its_host_has_its_v2/ARM64/11144854092/PROJECT.ecd;/by_service.html#service&kind
> 
> Unfortunately, I observed +6 new violations with that additional config 
> "CONFIG_UNSUPPORTED=y".
> 
> I don't know how and why these EXTRA_XEN_CONFIG were selected in the 
> file 'automation/gitlab-ci/analyze.yaml'. And are we able to add new 
> configs here ?....

This has been a repeated source for discussion. The present selection,
afaict, is pretty arbitrary. However, in your considerations on how to
address an issue, imo you should not look at the present config. Whatever
the solution would better fit all possible settings.

Jan


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From: Dmytro Prokopchuk1 
To: Stefano Stabellini , Nicola Vetrini
	, Jan Beulich 
CC: Doug Goldstein , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= ,
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Subject: Re: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
Thread-Topic: [PATCH] misra: add deviation of Rule 2.1 for BUG() macro
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Subject: Re: Consider changing CONFIG_ACPI default on ARM?
To: Elliott Mitchell 
Cc: Demi Marie Obenour ,
 xen-devel@lists.xenproject.org, Stefano Stabellini ,
 Julien Grall , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Paul Leiber 
References: 
 
 
 <1b96f2f3-55a2-4b33-84b1-a7c18d38d10c@suse.com>
 <6e9b5265-7a3b-4fd5-b14e-0e60a8b49833@gmail.com>
 
 
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On 26.08.2025 22:31, Elliott Mitchell wrote:
> On Mon, Aug 25, 2025 at 10:07:18AM +0200, Jan Beulich wrote:
>> On 22.08.2025 22:09, Elliott Mitchell wrote:
>>> On Fri, Aug 15, 2025 at 10:14:42AM +0200, Jan Beulich wrote:
>>>> On 14.08.2025 23:27, Demi Marie Obenour wrote:
>>>>> On 8/14/25 02:55, Jan Beulich wrote:
>>>>>>
>>>>>> Parties interested in changing the support status of any component are the
>>>>>> primary candidates to actually carry out the necessary work.
>>>>>
>>>>> What is that work?
>>>>
>>>> To determine what exactly needs doing is part of the exercise. I, for one, am
>>>> unaware of a concrete written down set of things which need doing.
>>>
>>> Since you're not pointing to anything definite, could it be everything
>>> has been resolved?
>>
>> Possible. Yet even then the state of things needs fully writing down, perhaps
>> in a commit message for the patch changing the support status. That's likely
>> still a time consuming job.
> 
> Issue is much of this is better done by the people doing those projects.
> Most of what I've done is checking a real hardware/software platform and
> confirmed functionality.  Presently it boots, but the framebuffer doesn't
> work.  VMs appear to work fine though.
> 
> How does the attached patch look for enabling ACPI?

The main (Arm) effect of it I can't judge on. I don't, however, think that
an experimental option can be default-on. That would effectively make it
(security-)supported. And of course there are a few formal issues with the
patch.

Jan


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Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
To: Stefano Stabellini 
Cc: Oleksii Kurochko , ray.huang@amd.com,
 Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
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References: <20250815102728.1340505-1-Penny.Zheng@amd.com>
 
 
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On 27.08.2025 02:33, Stefano Stabellini wrote:
> So I ran a test and the appended change, which is based on [1] and
> renaming CONFIG_DOMCTL to CONFIG_SYSCTL, is sufficient to resolve the
> build issue.
> 
> For 4.21, I suggest we go with two patches:
> 1) global rename of CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
> 2) stub domctl_lock_acquire/release based on CONFIG_MGMT_HYPERCALLS
> 
> Jan, are you OK with this?

Naming if the option aside, no, I fear I dislike the stubbing. What's
worse though, ...

> --- a/xen/include/xen/domain.h
> +++ b/xen/include/xen/domain.h
> @@ -148,8 +148,17 @@ void arch_dump_domain_info(struct domain *d);
>  
>  int arch_vcpu_reset(struct vcpu *v);
>  
> +#ifdef CONFIG_SYSCTL
>  bool domctl_lock_acquire(void);
>  void domctl_lock_release(void);
> +#else
> +static inline bool domctl_lock_acquire(void)
> +{
> +    return false;

... this will break x86'es HVM_PARAM_IDENT_PT handling. That is, in
principle I would agree that returning false here is appropriate. But
for the specific case there it's wrong.

As said on the call yesterday, until what you call MGMT_HYPERCALLS is
completely done, the option needs to be prompt-less, always-on. Adding
a prompt was necessary to be the last thing on the SYSCTL series, and
it'll need to be last on the follow-on one masking out further
hypercalls. IOW my take is that 34317c508294 and 568f806cba4c will
need reverting (the latter being what caused the regression, and the
former depending on the latter), to allow to cleanly continue that
work after the rename. If we don't do the reverts now (and take either
Penny's patch or what you propose), imo we'll need to do them later.
Else we're risking to introduce new randconfig breakages while the
further conversion work is ongoing.

Jan


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Subject: Re: [PATCH v2] x86/bitops: Optimise arch_ffs{,l}() some more on AMD
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250527222930.1452674-1-andrew.cooper3@citrix.com>
 <20250826174135.605220-1-andrew.cooper3@citrix.com>
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From: Jan Beulich 
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On 26.08.2025 19:41, Andrew Cooper wrote:
> --- a/xen/common/bitops.c
> +++ b/xen/common/bitops.c
> @@ -97,14 +97,14 @@ static void __init test_for_each_set_bit(void)
>      if ( ui != ui_res )
>          panic("for_each_set_bit(uint) expected %#x, got %#x\n", ui, ui_res);
>  
> -    ul = HIDE(1UL << (BITS_PER_LONG - 1) | 1);
> +    ul = HIDE(1UL << (BITS_PER_LONG - 1) | 0x11);
>      for_each_set_bit ( i, ul )
>          ul_res |= 1UL << i;
>  
>      if ( ul != ul_res )
>          panic("for_each_set_bit(ulong) expected %#lx, got %#lx\n", ul, ul_res);
>  
> -    ull = HIDE(0x8000000180000001ULL);
> +    ull = HIDE(0x8000000180000011ULL);
>      for_each_set_bit ( i, ull )
>          ull_res |= 1ULL << i;

How do these changes make a difference? Apart from ffs() using TZCNT, ...

> @@ -127,6 +127,79 @@ static void __init test_for_each_set_bit(void)
>          panic("for_each_set_bit(break) expected 0x1008, got %#x\n", ui_res);
>  }
>  
> +/*
> + * A type-generic fls() which picks the appropriate fls{,l,64}() based on it's
> + * argument.
> + */
> +#define fls_g(x)                                        \
> +    (sizeof(x) <= sizeof(int)      ? fls(x) :           \
> +     sizeof(x) <= sizeof(long)     ? flsl(x) :          \
> +     sizeof(x) <= sizeof(uint64_t) ? fls64(x) :         \
> +     ({ BUILD_ERROR("fls_g() Bad input type"); 0; }))
> +
> +/*
> + * for_each_set_bit_reverse() - Iterate over all set bits in a scalar value,
> + * from MSB to LSB.
> + *
> + * @iter An iterator name.  Scoped is within the loop only.
> + * @val  A scalar value to iterate over.
> + *
> + * A copy of @val is taken internally.
> + */
> +#define for_each_set_bit_reverse(iter, val)             \
> +    for ( typeof(val) __v = (val); __v; __v = 0 )       \
> +        for ( unsigned int (iter);                      \
> +              __v && ((iter) = fls_g(__v) - 1, true);   \
> +              __clear_bit(iter, &__v) )
> +
> +/*
> + * Xen doesn't have need of for_each_set_bit_reverse() at present, but the
> + * construct does exercise a case of arch_fls*() not covered anywhere else by
> + * these tests.
> + */
> +static void __init test_for_each_set_bit_reverse(void)
> +{
> +    unsigned int  ui,  ui_res = 0, tmp;
> +    unsigned long ul,  ul_res = 0;
> +    uint64_t      ull, ull_res = 0;
> +
> +    ui = HIDE(0x80008001U);
> +    for_each_set_bit_reverse ( i, ui )
> +        ui_res |= 1U << i;
> +
> +    if ( ui != ui_res )
> +        panic("for_each_set_bit_reverse(uint) expected %#x, got %#x\n", ui, ui_res);
> +
> +    ul = HIDE(1UL << (BITS_PER_LONG - 1) | 0x11);
> +    for_each_set_bit_reverse ( i, ul )
> +        ul_res |= 1UL << i;
> +
> +    if ( ul != ul_res )
> +        panic("for_each_set_bit_reverse(ulong) expected %#lx, got %#lx\n", ul, ul_res);
> +
> +    ull = HIDE(0x8000000180000011ULL);
> +    for_each_set_bit_reverse ( i, ull )
> +        ull_res |= 1ULL << i;

... even here the need for the extra setting of bit 4 remains unclear to
me: The thing that was missing was the testing of the reverse for-each.
You mention the need for an asymmetric input in the description, but isn't
that covered already by the first test using 0x80008001U?

That said, I certainly don't mind the change, it just isn't quite clear to
me whether I'm missing something crucial.

Jan


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To: Jason Andryuk 
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From: Jan Beulich 
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On 26.08.2025 23:08, Jason Andryuk wrote:
> --- a/xen/common/device-tree/dom0less-build.c
> +++ b/xen/common/device-tree/dom0less-build.c
> @@ -26,6 +26,7 @@
>  #include 
>  #include 
>  
> +#include 
>  #include 
>  
>  #include 
> @@ -120,8 +121,14 @@ static void __init initialize_domU_xenstore(void)
>  
>          if ( gfn != XENSTORE_PFN_LATE_ALLOC && IS_ENABLED(CONFIG_GRANT_TABLE) )
>          {
> +            evtchn_port_t port = d->arch.hvm.params[HVM_PARAM_STORE_EVTCHN];
> +            paddr_t evtchn_gaddr = gfn_to_gaddr(_gfn(gfn)) +
> +                offsetof(struct xenstore_domain_interface, evtchn_port);
> +
>              ASSERT(gfn < UINT32_MAX);
>              gnttab_seed_entry(d, GNTTAB_RESERVED_XENSTORE, xs_domid, gfn);
> +            access_guest_memory_by_gpa(d, evtchn_gaddr, &port, sizeof(port),
> +                                       true /* is_write */);

Isn't the use of an arch-specific function going to pose yet another issue
for making this code usable on x86? Can't you use copy_to_guest_phys() here?
Which may in turn need to be passed in by the caller, see e.g. dtb_load()
and initrd_load() (i.e. cache flushing may also be necessary for Arm).

Jan


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Subject: Re: [PATCH v3 8/8] xen/dom0less: store xenstore event channel in page
To: Jason Andryuk , 
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	, Bertrand Marquis 
References: <20250826210847.126015-1-jason.andryuk@amd.com>
 <20250826210847.126015-9-jason.andryuk@amd.com>
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On 26/08/2025 23:08, Jason Andryuk wrote:
> Write the associated event channel into the xenstore page so xenstored
> can read it.  xenstored can map the grant by the reserved grant table
> entry, and then read out the event channel and bind it.  This eliminates
> the need for an additional mechanism to discover the event channel.
> 
> Signed-off-by: Jason Andryuk 
> ---
> v2:
> No change
> 
> This should go in after the init-dom0less changes so init-dom0less is
> ready for xenstored automatically introducing domains.
> 
> I'm looking for feedback.  This is ARM-only for the time being, but that
> is the only in-tree user of this code.  From the perspective, it is okay
> to go in.
> 
> If we want a cross-arch approach, a common function to write to guest
> physical addresses would be needed for additional arches, but they
> aren't available yet.
> 
> Oleksii added a function pointer to dtb_load() and initrd_load() when
> moving dom0less to common, but I think that isn't necessary.  Just
> having a common helper would be sufficient.
> 
> copy_to_guest_phys() or something_copy_to_guest_phys() could be defined
> or a wrapper for ARM's copy_to_guest_phys_flush_dcache().  Other arches
> could need to implement it when using dom0less.
> 
> I'm not an ARM expert, but Stefano said
> copy_to_guest_phys_flush_dcache() is not necessary since this xenstore
> page isn't expected to be accessed without caches enabled.
I'm not sure I understand this point. When copying data *to* the guest, cleaning
is about Xen's cache, not guest's...

~Michal



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Date: Wed, 27 Aug 2025 10:05:04 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Stefano Stabellini 
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
	anthony.perard@vates.tech, michal.orzel@amd.com, jbeulich@suse.com,
	julien@xen.org
Subject: Re: [PATCH v2] docs/sending-patches: add GitLab pipeline link
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On Mon, Aug 18, 2025 at 04:00:11PM -0700, Stefano Stabellini wrote:
> When submitting patches to xen-devel, add a link to a successful
> pipeline run.
> 
> Signed-off-by: Stefano Stabellini 
> ---
> Changes in v2:
> - address Julien's comments
> 
> diff --git a/docs/process/sending-patches.pandoc b/docs/process/sending-patches.pandoc
> index 1991932b68..13bb3bf47a 100644
> --- a/docs/process/sending-patches.pandoc
> +++ b/docs/process/sending-patches.pandoc
> @@ -314,3 +314,38 @@ A patch should always be sent **to** the xen-devel mailing list
>  of all touched code areas should get a copy of the mail via **Cc**. In case
>  some other recipients are known to be interested in the patch, they can be
>  added via **Cc**, too.
> +
> +## Testing

Should this be placed immediately after the "Patch version history
(change log), further comments" section, so that the order of the
document matches the order of the described elements in the patch
itself?

> +
> +Xen Project uses a GitLab-based CI infrastructure. You can request to
> +have your GitLab account added to the Xen Project organization on GitLab
> +(https://gitlab.com/xen-project) by reaching out to THE REST maintainers
> +via xen-devel or Matrix. Once your account is added to the Xen Project
> +organization on GitLab, also a personal Xen repository will be created
> +for you under https://gitlab.com/xen-project/people//xen.
> +You will be able to trigger a GitLab testing pipeline with a single git
> +push to your personal Xen repository.
> +
> +When submitting a patch or patch series, please include a link to the
> +successful GitLab pipeline run on your personal branch. The branch
> +should be based on a recent version of the "master" branch, ideally not
> +older than two days.
> +
> +This information can be added after the `---` line.  For example:
> +
> +    ---
> +    Test CI pipeline:
> +    https://gitlab.com/xen-project/people/your-username/xen/-/pipelines/1980129839

FTAOD, should this also mention that for patch series the link should
be added to the cover letter and without any dashes?

Also FTAOD, should the link to the pipeline results be placed before
or after the "Changes since vX:" entries?

I don't care much whether it's before or after TBH, but we should
likely clarify that it either doesn't matter, or provide a suggested
order.

> +While it is technically possible to implement an automated system that
> +picks up patches and patch series from xen-devel and runs the GitLab
> +pipeline on them automatically, doing so would consume a significant
> +amount of resources on the testing infrastructure. There is no reliable
> +way to automatically determine whether a patch is close to being
> +committed or still undergoing substantial review. By having users submit
> +the link to the pipeline manually, we can manage testing resources much
> +more efficiently.
> +
> +When submitting new features, please also consider whether you can add a
> +GitLab test for the feature to ensure it continues to work correctly in
> +the future.

Not sure whether it's worth explicitly mentioning here, but it's not
strictly needed to add a new GitLab test, just adding a test to
tools/tests/ that's properly hooked up (like all test that reside
there) will get it automatically executed by GitLab.

Thanks, Roger.


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Date: Wed, 27 Aug 2025 10:07:26 +0200
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Subject: Re: [XEN PATCH] x86/vhpet: Add option to always fire hpet timer on
 resume
To: Vyacheslav Legoshin 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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On 27.08.2025 08:01, Vyacheslav Legoshin wrote:
> The following issue was observed on Windows 10 21H2 x64+: when the domain state
> is saved while all cores are executing the 'halt' instruction, and the memory
> save takes a relatively long time (tens of seconds), the HPET counter may
> overflow as follows:
> counter  = 11243f3e4a
> comparator = 910cb70f
> 
> In such cases, the fix implemented in commit
> b144cf45d50b603c2909fc32c6abf7359f86f1aa does not work (because the 'diff' is
> not negative), resulting in the guest VM becoming unresponsive for
> approximately 30 seconds.
> 
> This patch adds an option to always adjust the HPET timer to fire immediately
> after restore.

Thanks for the patch, but issues already start here: There's no Signed-off-by:.

> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -1461,6 +1461,15 @@ HPET can be disabled by specifying `hpet=0`.
>  
>  Deprecated alternative of `hpet=broadcast`.
>  
> +### hpet_drift_fix (x86)
> +> `= `
> +
> +> Default: `false`
> +
> +Always set HPET timer to fire immediately after domain restore.
> +This option can be used to fix unresponsive snapshots with modern x64 Windows
> +systems (21H2+) which use non-periodic timers.

I'm not convinced making this a global option is appropriate. If an option is
needed, it would better be a per-domain setting. Whether an option is needed
in the first place is tbd.

And then, if a global option was used, then please with dashes in favor of
underscores in its name.

> --- a/xen/arch/x86/hvm/hpet.c
> +++ b/xen/arch/x86/hvm/hpet.c
> @@ -11,6 +11,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -222,6 +223,9 @@ static void cf_check hpet_timer_fired(struct vcpu *v, void *data)
>   * 1/(2^10) second, namely, 0.9765625 milliseconds */
>  #define  HPET_TINY_TIME_SPAN  ((h->stime_freq >> 10) / STIME_PER_HPET_TICK)
>  
> +bool hpet_drift_fix;

static and __ro_after_init.

> @@ -268,11 +272,18 @@ static void hpet_set_timer(HPETState *h, unsigned int tn,
>       * are restoring after migrate, treat any wrap as past since the value
>       * is unlikely to be 'small'.
>       */
> -    if ( (int64_t)diff < 0 )
> -        diff = (timer_is_32bit(h, tn) &&
> -                vhpet_domain(h)->creation_finished &&
> -                (-diff > HPET_TINY_TIME_SPAN))
> -            ? (uint32_t)diff : 0;
> +    if (hpet_drift_fix && !vhpet_domain(h)->creation_finished)

Nit (style): Missing blanks (see e.g. the other if() you're altering).

> +    {
> +        diff = 0;
> +    }

No real need for figure braces here.

The comment ahead of the construct also wants amending / updating.

> +    else
> +    {
> +        if ( (int64_t)diff < 0 )

"else if()" please, reducing the diff quite a bit.

Jan


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To: "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
From: Jan Beulich 
Subject: [PATCH] x86/PSR: move CPUID level check
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At the first (and maybe second) glance the call to setup_clear_cpu_cap()
(which is __init) from psr_cpu_init() (which isn't) looks wrong. The
earlier cpu_has_pqe makes it safe, though. Nevertheless we can do better,
by simply moving the check ahead of the BSP invocation of the function.

Signed-off-by: Jan Beulich 

--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -1583,12 +1583,6 @@ static void psr_cpu_init(void)
     if ( !psr_alloc_feat_enabled() || !cpu_has_pqe )
         goto assoc_init;
 
-    if ( boot_cpu_data.cpuid_level < PSR_CPUID_LEVEL_CAT )
-    {
-        setup_clear_cpu_cap(X86_FEATURE_PQE);
-        goto assoc_init;
-    }
-
     socket = cpu_to_socket(cpu);
     info = socket_info + socket;
     if ( info->feat_init )
@@ -1708,6 +1702,9 @@ static int __init cf_check psr_presmp_in
     if ( psr_cpu_prepare() )
         psr_free();
 
+    if ( boot_cpu_data.cpuid_level < PSR_CPUID_LEVEL_CAT )
+        setup_clear_cpu_cap(X86_FEATURE_PQE);
+
     psr_cpu_init();
     if ( psr_cmt_enabled() || psr_alloc_feat_enabled() )
         register_cpu_notifier(&cpu_nfb);


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Subject: Re: [PATCH v5 2/4] hvmloader: fix SMBIOS table length checks
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On 24.08.2025 00:26, Petr Beneš wrote:
> From: Petr Beneš 
> 
> SMBIOS specification dictates that tables should have a minimal length.
> This commit introduces further validation for user-input SMBIOS tables.
> 
> As per SMBIOS Reference Specification:
> * Type 0: For version 2.3 and later implementations, the length is at least 14h
> * Type 1: 1Bh for 2.4 and later
> * Type 2: at least 08h
> * Type 3: 0Dh for version 2.1 and later
> * Type 11: 5h (+ strings)
> * Type 22: 1Ah (+ strings)
> * Type 39: a minimum of 10h
> 
> Notably, this also fixes previously incorrect check for chassis handle in
> smbios_type_2_init. Chassis handle is a WORD, therefore, the condition now
> correctly checks for >= 13 instead of > 13.
> 
> hvmloader currently implements version 2.4
> 
> Furthermore, this commit introduces smbios_pt_copy helper function to substitute
> previously repeating pattern of locating the struct in physical memory (via
> get_smbios_pt_struct), checking the length and copying it into SMBIOS region.

I've added
Fixes: 4d23036e7096 ("HVM firmware passthrough SMBIOS processing")
here.

Jan

> Signed-off-by: Petr Beneš 
> Acked-by: Jan Beulich 




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From: Oleksii Moisieiev 
To: Stefano Stabellini 
CC: "xen-devel@lists.xenproject.org" , Andrew
 Cooper , Anthony PERARD
	, Bertrand Marquis , Jan
 Beulich , Juergen Gross , Julien Grall
	, Michal Orzel ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Volodymyr
 Babchuk , Grygorii Strashko
	
Subject: Re: [RFC PATCH v5 02/10] xen/arm: scmi-smc: update to be used under
 sci subsystem
Thread-Topic: [RFC PATCH v5 02/10] xen/arm: scmi-smc: update to be used under
 sci subsystem
Thread-Index: AQHb+v2VN6PNmY5o9E6echLDtYWg47RvkxgAgAbZdoA=
Date: Wed, 27 Aug 2025 09:02:20 +0000
Message-ID: <1f64aa13-d9d3-4b58-9581-a45f7173430b@epam.com>
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Date: Wed, 27 Aug 2025 11:09:32 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Vyacheslav Legoshin 
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich , Julien Grall ,
	Stefano Stabellini 
Subject: Re: [XEN PATCH] x86/vhpet: Add option to always fire hpet timer on
 resume
Message-ID: 
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On Wed, Aug 27, 2025 at 09:01:08AM +0300, Vyacheslav Legoshin wrote:
> The following issue was observed on Windows 10 21H2 x64+: when the domain state
> is saved while all cores are executing the 'halt' instruction,

I assume this when executing `xl save` or equivalent command from a
different toolstack?

IIRC in that case the guest would be paused while the memory dump to
disk is done, and hence guest vCPUs won't be executing the `halt`
instruction, they wouldn't be executing at all.

> and the memory
> save takes a relatively long time (tens of seconds), the HPET counter may
> overflow as follows:
> counter  = 11243f3e4a
> comparator = 910cb70f
> 
> In such cases, the fix implemented in commit
> b144cf45d50b603c2909fc32c6abf7359f86f1aa does not work (because the 'diff' is
> not negative), resulting in the guest VM becoming unresponsive for
> approximately 30 seconds.
> 
> This patch adds an option to always adjust the HPET timer to fire immediately
> after restore.

What happens if the guest is left running after the save?  I assume
that using `xl save -c ` would leave the domain in a similarly
wedged state, and your proposed workaround won't be effective there,
since there's no restoring process?  Or that's not the case there
because Xen is still keeping track of the internal timer, and would
set an interrupt as pending anyway?

Should we maybe store the last guest time at context save, and check
against that to see whether comparators should have triggered, instead
of playing this games?

Thanks, Roger.


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From: Oleksii Moisieiev 
To: Stefano Stabellini 
CC: "xen-devel@lists.xenproject.org" , Andrew
 Cooper , Anthony PERARD
	, Bertrand Marquis , Jan
 Beulich , Juergen Gross , Julien Grall
	, Michal Orzel ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Volodymyr
 Babchuk , Grygorii Strashko
	
Subject: Re: [RFC PATCH v5 00/10] xen/arm: scmi: introduce SCI SCMI SMC
 multi-agent support
Thread-Topic: [RFC PATCH v5 00/10] xen/arm: scmi: introduce SCI SCMI SMC
 multi-agent support
Thread-Index: AQHb+v2VYJM++98Y2ku7DWB5wHJSn7RvlUmAgAbZoQA=
Date: Wed, 27 Aug 2025 09:10:37 +0000
Message-ID: <2eb538a8-aaf6-4d71-9379-40ae0351f0c6@epam.com>
References: 
 
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Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Oleksii Kurochko 
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On 25.08.2025 17:50, Oleksii Kurochko wrote:
> Hello community,
> 
> I’d like to remind everyone that the Feature Freeze deadline is approaching,
> and we still have some outstanding requests from the community for patch series
> to be merged into 4.21:
> 
> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
> 2. Introduce SCI SCMI SMC multi-agent support [2]
> 3. Introduce eSPI support [3]
> 4. FRED work: [4], [5], possibly others (?)
> 5. Introduce CONFIG_DOMCTL [6]
> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
> 7. Some other patch series I missed.

"symbols: assorted adjustments" plus the later "symbols: discard stray file
symbols", provided someone would take the time to actually look at the patches?

Jan


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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Topic: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcFpJ/0RYrIev2JkmWYheOK3kVZ7R2RJKA
Date: Wed, 27 Aug 2025 09:56:30 +0000
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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 06/11] xen/arm/irq: allow eSPI processing in the do_IRQ
 function
Thread-Topic: [PATCH v3 06/11] xen/arm/irq: allow eSPI processing in the
 do_IRQ function
Thread-Index: AQHcFpJ/78TDbVIRnkOE9iNbqduJVLR2RaCA
Date: Wed, 27 Aug 2025 10:00:15 +0000
Message-ID: <6ba907e2-924f-4f7a-bb05-54f1d00f3f1c@epam.com>
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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 08/11] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Topic: [PATCH v3 08/11] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcFpKACzOaRjOW50q/bIpnflDhk7R2SLeA
Date: Wed, 27 Aug 2025 10:11:19 +0000
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To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 09/11] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Topic: [PATCH v3 09/11] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Index: AQHcFpKAZWUsU5Sz9EWrJGvlceTbI7R2TLcA
Date: Wed, 27 Aug 2025 10:25:38 +0000
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Date: Wed, 27 Aug 2025 13:25:55 +0300
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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <398ad09617f4f97d57d13fa9f3771bd2db83916b.1756216943.git.leonid_komarianskyi@epam.com>
Content-Language: en-US
From: Oleksandr Tyshchenko 
In-Reply-To: <398ad09617f4f97d57d13fa9f3771bd2db83916b.1756216943.git.leonid_komarianskyi@epam.com>
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On 26.08.25 17:05, Leonid Komarianskyi wrote:


Hello Leonid,

In general patch looks good to me, just one question below ...

> Introduced appropriate register definitions, helper macros,
> and initialization of required GICv3.1 distributor registers
> to support eSPI. This type of interrupt is handled in the
> same way as regular SPI interrupts, with the following
> differences:
> 
> 1) eSPIs can have up to 1024 interrupts, starting from the
> beginning of the range, whereas regular SPIs use INTIDs from
> 32 to 1019, totaling 988 interrupts;
> 2) eSPIs start at INTID 4096, necessitating additional interrupt
> index conversion during register operations.
> 
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V2:
> - move gic_number_espis function from
>    [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
>    to use it in the newly introduced gic_is_valid_espi
> - add gic_is_valid_espi which checks if IRQ number is in supported
>    by HW eSPI range
> - update gic_is_valid_irq conditions to allow operations with eSPIs
> 
> Changes in V3:
> - add __init attribute to gicv3_dist_espi_common_init
> - change open-codded eSPI register initialization to the appropriate
>    gen-mask macro
> - fixed formatting for lines with more than 80 symbols
> - introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
>    CONFIG_GICV3_ESPI disabled
> - renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
>    (name was taken from GIC specification) to avoid confusion
> - changed type for i variable to unsigned int since it cannot be
>    negative
> ---
>   xen/arch/arm/gic-v3.c                  | 80 ++++++++++++++++++++++++++
>   xen/arch/arm/include/asm/gic.h         | 21 +++++++
>   xen/arch/arm/include/asm/gic_v3_defs.h | 34 +++++++++++
>   3 files changed, 135 insertions(+)
> 
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index a959fefebe..3aa5cc1765 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
>           default:
>               break;
>           }
> +#ifdef CONFIG_GICV3_ESPI
> +    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
> +    {
> +        u32 irq_index = ESPI_INTID2IDX(irqd->irq);
> +
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ICENABLER:
> +            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ISPENDR:
> +            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ICPENDR:
> +            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ISACTIVER:
> +            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICACTIVER:
> +            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTERnE + irq_index * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYRnE + irq_index);
> +        default:
> +            break;
> +        }
> +    }
> +#endif
>       default:
>           break;
>       }
> @@ -655,6 +685,52 @@ static void gicv3_set_irq_priority(struct irq_desc *desc,
>       spin_unlock(&gicv3.lock);
>   }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +unsigned int gic_number_espis(void)
> +{
> +    return gic_hw_ops->info->nr_espi;
> +}
> +
> +static void __init gicv3_dist_espi_common_init(uint32_t type)
> +{
> +    unsigned int espi_nr, i;
> +
> +    espi_nr = min(1024U, GICD_TYPER_ESPIS_NUM(type));
> +    gicv3_info.nr_espi = espi_nr;
> +    /* The GIC HW doesn't support eSPI, so we can leave from here */
> +    if ( gicv3_info.nr_espi == 0 )
> +        return;
> +
> +    for ( i = 0; i < espi_nr; i += 16 )
> +        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
> +
> +    for ( i = 0; i < espi_nr; i += 4 )
> +        writel_relaxed(GIC_PRI_IRQ_ALL,
> +                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
> +
> +    for ( i = 0; i < espi_nr; i += 32 )
> +    {
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i / 32) * 4);
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i / 32) * 4);
> +    }
> +
> +    for ( i = 0; i < espi_nr; i += 32 )
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) * 4);
> +}
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
> +{
> +    unsigned int i;
> +
> +    for ( i = 0; i < gicv3_info.nr_espi; i++ )
> +        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * 8);
> +}
> +#else
> +static void __init gicv3_dist_espi_common_init(uint32_t type) { }
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
> +#endif
> +
>   static void __init gicv3_dist_init(void)
>   {
>       uint32_t type;
> @@ -700,6 +776,8 @@ static void __init gicv3_dist_init(void)
>       for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
>           writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4);


There is a banner in this function (not visible from the patch context), 
that prints nr_lines, etc.

E.g.:
(XEN) GICv3: 288 lines, (IID 0000043b).

What do you think, would it be important/valuable to also print nr_espi 
if non-zero (extended SPI range is supported)?


>   
> +    gicv3_dist_espi_common_init(type);
> +
>       gicv3_dist_wait_for_rwp();
>   
>       /* Turn on the distributor *
> @@ -713,6 +791,8 @@ static void __init gicv3_dist_init(void)
>   
>       for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
>           writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8);
> +
> +    gicv3_dist_espi_init_aff(affinity);
>   }
> 


[snip]





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Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Oleksii Kurochko ,
 Xen-devel ,
 Community Manager ,
 "committers@xenproject.org" 
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On 25/08/2025 4:50 pm, Oleksii Kurochko wrote:
> Hello community,
>
> I’d like to remind everyone that the Feature Freeze deadline is approaching,
> and we still have some outstanding requests from the community for patch series
> to be merged into 4.21:
>
> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
> 2. Introduce SCI SCMI SMC multi-agent support [2]
> 3. Introduce eSPI support [3]
> 4. FRED work: [4], [5], possibly others (?)
> 5. Introduce CONFIG_DOMCTL [6]
> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
> 7. Some other patch series I missed.

Fixes for Intel Fam18/19.  These are partly done, with some work
remaining.  These are more of a bugfix than a feature anyway, and needed
in order for Xen to function on CPUs being released this year (i.e.
fairly critical for 4.21.)

Cleanup/etc for new toolchains.  There's been a lot of work done
already, with a few already-posted patches needing a refresh.

Both of these areas are low risk changes and have been going on (at a
background priority) for most of 4.21.  They should be safe into the
first few RCs.

~Andrew


From xen-devel-bounces@lists.xenproject.org Wed Aug 27 11:13:23 2025
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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v3 10/11] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v3 10/11] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
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Date: Wed, 27 Aug 2025 11:13:07 +0000
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Date: Wed, 27 Aug 2025 15:01:01 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3 09/11] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
To: Leonid Komarianskyi 
Cc: "xen-devel@lists.xenproject.org" ,
 Volodymyr Babchuk ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel 
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 <874itt4r5t.fsf@epam.com> <1cf0a662-b717-458c-8174-6b03187b4b6c@epam.com>
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From: Oleksandr Tyshchenko 
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On 27.08.25 13:25, Leonid Komarianskyi wrote:

Hello Leonid

> Hello Volodymyr,
> 
> Thank you for your suggestion.
> 
> On 27.08.25 02:08, Volodymyr Babchuk wrote:
>> Hi Leonid,
>>
>> Leonid Komarianskyi  writes:
>>
>>> The Dom0 and DomUs logic for the dom0less configuration in create_dom0()
>>> and arch_create_domUs() has been updated to account for extended SPIs
>>> when supported by the hardware and enabled with CONFIG_GICV3_ESPI. These
>>> changes ensure the proper calculation of the maximum number of SPIs and
>>> eSPIs available to Dom0 and DomUs in dom0less setups.
>>>
>>> When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is
>>> enabled, the maximum number of eSPI interrupts is calculated using the
>>> ESPI_BASE_INTID offset (4096) and is limited to 1024, with 32 IRQs
>>> subtracted. To ensure compatibility with DomUs (Dom0 setups) domains,
>>> where this adjustment is applied by the toolstack during domain
>>> creation, while for Dom0 or DomUs in Dom0, it is handled directly during
>>> VGIC initialization. If eSPIs are not supported, the calculation
>>> defaults to using the standard SPI range, with a maximum value of
>>> 960 interrupt lines, as it works currently.
>>>
>>> Signed-off-by: Leonid Komarianskyi 
>>>
>>> ---
>>> Changes in V2:
>>> - no changes
>>>
>>> Changes in V3:
>>> - renamed macro VGIC_DEF_NR_ESPIS to more appropriate VGIC_DEF_MAX_SPI
>>
>> Will VGIC_DEF_MAX_ESPI be better? When other code refer to "SPI" it mean
>> "common SPI" (less than 1022), while ESPI is used for extended SPI. So,
>> naturally it feels that VGIC_DEF_MAX_SPI should be equal to 1022...
>>
> 
> Yes, I agree with that - VGIC_DEF_MAX_ESPI sounds more appropriate in
> this case. I will rename it in V4.
> 
>>> - added eSPI initialization for dom0less setups
>>> - fixed comment with mentions about dom0less builds
>>> - fixed formatting for lines with more than 80 symbols
>>> - updated commit message
>>> ---
>>>    xen/arch/arm/dom0less-build.c   | 12 ++++++++++++
>>>    xen/arch/arm/domain_build.c     | 11 +++++++++++
>>>    xen/arch/arm/include/asm/vgic.h | 14 ++++++++++++++
>>>    3 files changed, 37 insertions(+)
>>>
>>> diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
>>> index 69b9ea22ce..f4f9077db5 100644
>>> --- a/xen/arch/arm/dom0less-build.c
>>> +++ b/xen/arch/arm/dom0less-build.c
>>> @@ -286,6 +286,18 @@ void __init arch_create_domUs(struct dt_device_node *node,
>>>            int vpl011_virq = GUEST_VPL011_SPI;
>>>    
>>>            d_cfg->arch.nr_spis = VGIC_DEF_NR_SPIS;
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +        /*
>>> +         * Check if the hardware supports extended SPIs (even if the
>>> +         * appropriate config is set). If not, the common SPI range
>>> +         * will be used. Otherwise overwrite the nr_spis with the maximum
>>> +         * available INTID from eSPI range. In that case, the number of
>>> +         * regular SPIs will be adjusted to the maximum value during vGIC
>>> +         * initialization.
>>> +         */
>>> +        if ( gic_number_espis() > 0 )
>>> +            d_cfg->arch.nr_spis = VGIC_DEF_MAX_SPI;
>>> +#endif
>>>    
>>>            /*
>>>             * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is
>>> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
>>> index d91a71acfd..148a8bdb60 100644
>>> --- a/xen/arch/arm/domain_build.c
>>> +++ b/xen/arch/arm/domain_build.c
>>> @@ -2055,6 +2055,17 @@ void __init create_dom0(void)
>>>        /* The vGIC for DOM0 is exactly emulating the hardware GIC */
>>>        dom0_cfg.arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE;
>>>        dom0_cfg.arch.nr_spis = VGIC_DEF_NR_SPIS;
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    /*
>>> +     * Check if the hardware supports extended SPIs (even if the appropriate
>>> +     * config is set). If not, the common SPI range will be used. Otherwise
>>> +     * overwrite the nr_spis with the maximum available INTID from eSPI range.
>>> +     * In that case, the number of regular SPIs will be adjusted to the maximum
>>> +     * value during vGIC initialization.
>>> +     */
>>> +    if ( gic_number_espis() > 0 )
>>> +        dom0_cfg.arch.nr_spis = VGIC_DEF_MAX_SPI;
>>> +#endif

So we have almost (?) identical code and big comments in both 
create_dom0() and arch_create_domUs().

I was thinking, wouldn't it be better if we put this into a helper? This 
way, I think, we will reduce the number of GICv3-specific #ifdef-s in 
common domain construction code and will not need to worry about keeping 
these places in sync when updating the check/comment.

Something like below to be applied on top of your patch (not build-tested):

diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index f4f9077db5..02d5559102 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -285,19 +285,7 @@ void __init arch_create_domUs(struct dt_device_node 
*node,
      {
          int vpl011_virq = GUEST_VPL011_SPI;

-        d_cfg->arch.nr_spis = VGIC_DEF_NR_SPIS;
-#ifdef CONFIG_GICV3_ESPI
-        /*
-         * Check if the hardware supports extended SPIs (even if the
-         * appropriate config is set). If not, the common SPI range
-         * will be used. Otherwise overwrite the nr_spis with the maximum
-         * available INTID from eSPI range. In that case, the number of
-         * regular SPIs will be adjusted to the maximum value during vGIC
-         * initialization.
-         */
-        if ( gic_number_espis() > 0 )
-            d_cfg->arch.nr_spis = VGIC_DEF_MAX_SPI;
-#endif
+        d_cfg->arch.nr_spis = vgic_def_nr_spis();

          /*
           * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 148a8bdb60..39eea0be00 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2054,18 +2054,7 @@ void __init create_dom0(void)

      /* The vGIC for DOM0 is exactly emulating the hardware GIC */
      dom0_cfg.arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE;
-    dom0_cfg.arch.nr_spis = VGIC_DEF_NR_SPIS;
-#ifdef CONFIG_GICV3_ESPI
-    /*
-     * Check if the hardware supports extended SPIs (even if the 
appropriate
-     * config is set). If not, the common SPI range will be used. Otherwise
-     * overwrite the nr_spis with the maximum available INTID from eSPI 
range.
-     * In that case, the number of regular SPIs will be adjusted to the 
maximum
-     * value during vGIC initialization.
-     */
-    if ( gic_number_espis() > 0 )
-        dom0_cfg.arch.nr_spis = VGIC_DEF_MAX_SPI;
-#endif
+    dom0_cfg.arch.nr_spis = vgic_def_nr_spis();
      dom0_cfg.arch.tee_type = tee_get_type();
      dom0_cfg.max_vcpus = dom0_max_vcpus();

diff --git a/xen/arch/arm/include/asm/vgic.h 
b/xen/arch/arm/include/asm/vgic.h
index 0bb025f5d5..0350122a74 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -367,6 +367,24 @@ extern void vgic_check_inflight_irqs_pending(struct 
vcpu *v,
                            min(gic_number_espis(), 1024U) - 32)
  #endif

+static inline unsigned int vgic_def_nr_spis(void)
+{
+#ifdef CONFIG_GICV3_ESPI
+    /*
+     * Check if the hardware supports extended SPIs (even if the
+     * appropriate config is set). If not, the common SPI range
+     * will be used. Otherwise overwrite the nr_spis with the maximum
+     * available INTID from eSPI range. In that case, the number of
+     * regular SPIs will be adjusted to the maximum value during vGIC
+     * initialization.
+     */
+    if ( gic_number_espis() > 0 )
+        return VGIC_DEF_MAX_SPI;
+#endif
+
+    return VGIC_DEF_NR_SPIS;
+}
+
  extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);

  static inline bool vgic_is_spi(struct domain *d, unsigned int virq)

******

Also, if VGIC_DEF_MAX_SPI (or whatever name you agreed on) is not 
supposed to be used outside of vgic.h, I would even consider dropping it
and using "ESPI_BASE_INTID + min(gic_number_espis(), 1024U) - 32" (to 
reduce one more #ifdef in the header).


P.S. I might be wrong, but it feels to me, that description for 
"nr_spis" in docs/man/xl.cfg.5.pod.in needs a update within your series 
(it mentions that "Max is 960 SPIs").


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From: Hari Limaye 
To: "Orzel, Michal" 
CC: "xen-devel@lists.xenproject.org" , Luca
 Fancellu , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Volodymyr Babchuk 
Subject: Re: [PATCH 4/5] arm/mpu: Implement ioremap_attr for MPU
Thread-Topic: [PATCH 4/5] arm/mpu: Implement ioremap_attr for MPU
Thread-Index: AQHcEzkCJOS9/PWe+UmuJdsGAsOPLbR2dO0A
Date: Wed, 27 Aug 2025 12:25:44 +0000
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From: Hari Limaye 
To: "Orzel, Michal" 
CC: "xen-devel@lists.xenproject.org" , Luca
 Fancellu , Penny Zheng , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Volodymyr Babchuk
	, Andrew Cooper ,
	Anthony PERARD , Jan Beulich ,
	=?iso-8859-1?Q?Roger_Pau_Monn=E9?= , Wei Chen
	
Subject: Re: [PATCH 5/5] xen/arm: map static memory on demand
Thread-Topic: [PATCH 5/5] xen/arm: map static memory on demand
Thread-Index: AQHcEzlqos7dHoCXP0W7s7Rjj8N/SbR2dmwA
Date: Wed, 27 Aug 2025 12:31:07 +0000
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Hi Michal,

> On 22 Aug 2025, at 08:50, Orzel, Michal  wrote:
>=20
>=20
>=20
> On 30/07/2025 10:45, Hari Limaye wrote:
>> From: Penny Zheng 
>>=20
>> In the function `init_staticmem_pages` we need to have mapped static
>> memory banks for initialization. Unlike on an MMU system, we cannot map
>> the entire RAM on an MPU system as we have a limited number of MPU
>> memory regions. To solve this, transiently map the static memory banks
>> for initialization.
> How does this correspond to Arm32 MPU (R52), where all of the RAM will be
> covered? I don't think 'transient' mappings will be needed there but all =
of your
> work targets common (i.e. not only Arm64) MPU code.
>=20
> ~Michal
>=20

Hm fair point - when this series was submitted to the ML, I had no knowledg=
e of the intention for all of the RAM to be mapped on Arm32 MPU systems and=
 imagined that things would be more aligned here.=20

Are happy for this to remain common for now? Or would you prefer it to be s=
plit off?

Many thanks,
Hari=


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From: Frediano Ziglio 
To: xen-devel@lists.xenproject.org
Cc: Frediano Ziglio ,
	Anthony PERARD ,
	Juergen Gross ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Andrew Cooper 
Subject: [PATCH] Optimise restore memory allocation
Date: Wed, 27 Aug 2025 13:33:04 +0100
Message-ID: <20250827123309.39699-1-frediano.ziglio@cloud.com>
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Try to allocate larger order pages.
With some test memory program stressing TLB (many small random
memory accesses) you can get 15% performance improves.
On the first memory iteration the sender is currently sending
memory in 4mb aligned chunks which allows the receiver to
allocate most pages as 2mb superpages instead of single 4kb pages.

Signed-off-by: Frediano Ziglio 
---
 tools/libs/guest/xg_sr_restore.c | 39 ++++++++++++++++++++++++++++----
 1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/tools/libs/guest/xg_sr_restore.c b/tools/libs/guest/xg_sr_restore.c
index 06231ca826..8dcb1b19c5 100644
--- a/tools/libs/guest/xg_sr_restore.c
+++ b/tools/libs/guest/xg_sr_restore.c
@@ -129,6 +129,8 @@ static int pfn_set_populated(struct xc_sr_context *ctx, xen_pfn_t pfn)
     return 0;
 }
 
+#define IS_POWER_OF_2(n) (((n) & ((n) - 1)) == 0)
+
 /*
  * Given a set of pfns, obtain memory from Xen to fill the physmap for the
  * unpopulated subset.  If types is NULL, no page type checking is performed
@@ -141,6 +143,7 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
     xen_pfn_t *mfns = malloc(count * sizeof(*mfns)),
         *pfns = malloc(count * sizeof(*pfns));
     unsigned int i, nr_pfns = 0;
+    bool contiguous = true;
     int rc = -1;
 
     if ( !mfns || !pfns )
@@ -159,18 +162,46 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
             if ( rc )
                 goto err;
             pfns[nr_pfns] = mfns[nr_pfns] = original_pfns[i];
+            if ( pfns[nr_pfns] != pfns[0] + nr_pfns )
+                contiguous = false;
             ++nr_pfns;
         }
     }
 
     if ( nr_pfns )
     {
-        rc = xc_domain_populate_physmap_exact(
-            xch, ctx->domid, nr_pfns, 0, 0, mfns);
+        /* try optimizing using larger order */
+        rc = -1;
+        /*
+         * The "nr_pfns <= (1 << 18)" check is mainly for paranoia, it should
+         * never happen, the sender would have to send a really large packet.
+         */
+        if ( contiguous && nr_pfns <= (1 << 18) &&
+             IS_POWER_OF_2(nr_pfns) && (pfns[0] & (nr_pfns - 1)) == 0 )
+        {
+            const unsigned int extent_order = __builtin_ffs(nr_pfns) - 1;
+
+            rc = xc_domain_populate_physmap_exact(
+                xch, ctx->domid, 1, extent_order, 0, mfns);
+            if ( rc )
+                mfns[0] = pfns[0];
+            else
+            {
+                for ( i = 1; i < nr_pfns; ++i )
+                    mfns[i] = mfns[0] + i;
+            }
+        }
+
+        /* if using larger order fails fall back to single pages */
         if ( rc )
         {
-            PERROR("Failed to populate physmap");
-            goto err;
+            rc = xc_domain_populate_physmap_exact(
+                xch, ctx->domid, nr_pfns, 0, 0, mfns);
+            if ( rc )
+            {
+                PERROR("Failed to populate physmap");
+                goto err;
+            }
         }
 
         for ( i = 0; i < nr_pfns; ++i )
-- 
2.43.0



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Date: Wed, 27 Aug 2025 09:19:42 -0400
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Subject: Re: [PATCH v3 8/8] xen/dom0less: store xenstore event channel in page
To: Jan Beulich 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, 
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On 2025-08-27 03:58, Jan Beulich wrote:
> On 26.08.2025 23:08, Jason Andryuk wrote:
>> --- a/xen/common/device-tree/dom0less-build.c
>> +++ b/xen/common/device-tree/dom0less-build.c
>> @@ -26,6 +26,7 @@
>>   #include 
>>   #include 
>>   
>> +#include 
>>   #include 
>>   
>>   #include 
>> @@ -120,8 +121,14 @@ static void __init initialize_domU_xenstore(void)
>>   
>>           if ( gfn != XENSTORE_PFN_LATE_ALLOC && IS_ENABLED(CONFIG_GRANT_TABLE) )
>>           {
>> +            evtchn_port_t port = d->arch.hvm.params[HVM_PARAM_STORE_EVTCHN];
>> +            paddr_t evtchn_gaddr = gfn_to_gaddr(_gfn(gfn)) +
>> +                offsetof(struct xenstore_domain_interface, evtchn_port);
>> +
>>               ASSERT(gfn < UINT32_MAX);
>>               gnttab_seed_entry(d, GNTTAB_RESERVED_XENSTORE, xs_domid, gfn);
>> +            access_guest_memory_by_gpa(d, evtchn_gaddr, &port, sizeof(port),
>> +                                       true /* is_write */);
> 
> Isn't the use of an arch-specific function going to pose yet another issue
> for making this code usable on x86? Can't you use copy_to_guest_phys() here?
> Which may in turn need to be passed in by the caller, see e.g. dtb_load()
> and initrd_load() (i.e. cache flushing may also be necessary for Arm).

Yes, that could be done, but it's not my preferred approach.  Using a 
function pointer to pass a compile time constant seems to me like a 
misuse of a function pointer.

I'd rather each arch using dom0less define:
unsigned long copy_to_guest_phys(struct domain *d,
                                  paddr_t gpa,
                                  void *buf,
                                  unsigned int len);

Which does the correct thing for the arch.

Alejandro was able to re-work things to re-use the dom0less parsing code 
(dom0less-bindings.c), but he has so far kept the x86 domain 
construction separate such that it does not use dom0less-build.c.  So I 
don't know how that will shake out.

But, yeah, I can just pass in a function pointer if that is what is 
agreed upon.

Regards,
Jason


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	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v3 04/11] xen/arm/irq: add handling for IRQs in the eSPI
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Thread-Topic: [PATCH v3 04/11] xen/arm/irq: add handling for IRQs in the eSPI
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Subject: Re: [PATCH v3 8/8] xen/dom0less: store xenstore event channel in page
To: "Orzel, Michal" , 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis 
References: <20250826210847.126015-1-jason.andryuk@amd.com>
 <20250826210847.126015-9-jason.andryuk@amd.com>
 
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On 2025-08-27 04:03, Orzel, Michal wrote:
> 
> 
> On 26/08/2025 23:08, Jason Andryuk wrote:
>> Write the associated event channel into the xenstore page so xenstored
>> can read it.  xenstored can map the grant by the reserved grant table
>> entry, and then read out the event channel and bind it.  This eliminates
>> the need for an additional mechanism to discover the event channel.
>>
>> Signed-off-by: Jason Andryuk 
>> ---
>> v2:
>> No change
>>
>> This should go in after the init-dom0less changes so init-dom0less is
>> ready for xenstored automatically introducing domains.
>>
>> I'm looking for feedback.  This is ARM-only for the time being, but that
>> is the only in-tree user of this code.  From the perspective, it is okay
>> to go in.
>>
>> If we want a cross-arch approach, a common function to write to guest
>> physical addresses would be needed for additional arches, but they
>> aren't available yet.
>>
>> Oleksii added a function pointer to dtb_load() and initrd_load() when
>> moving dom0less to common, but I think that isn't necessary.  Just
>> having a common helper would be sufficient.
>>
>> copy_to_guest_phys() or something_copy_to_guest_phys() could be defined
>> or a wrapper for ARM's copy_to_guest_phys_flush_dcache().  Other arches
>> could need to implement it when using dom0less.
>>
>> I'm not an ARM expert, but Stefano said
>> copy_to_guest_phys_flush_dcache() is not necessary since this xenstore
>> page isn't expected to be accessed without caches enabled.
> I'm not sure I understand this point. When copying data *to* the guest, cleaning
> is about Xen's cache, not guest's...

I was trying to highlight that the patch is using 
access_guest_memory_by_gpa(), but dtb_load() and initrd_load() use 
copy_to_guest_phys_flush_dcache().

I assumed from the name, and Stefano's comment, that 
copy_to_guest_phys_flush_dcache() was about ensuring the CPU's cache is 
flushed to RAM.  That way a guest starting with cache disabled would see 
the correct contents.  But I don't really know how it works and may be 
wrong.

Thanks,
Jason


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Subject: Re: [PATCH 5/5] xen/arm: map static memory on demand
To: Hari Limaye , "Orzel, Michal" 
CC: "xen-devel@lists.xenproject.org" , "Luca
 Fancellu" , Penny Zheng , Stefano
 Stabellini , Julien Grall , Bertrand
 Marquis , Volodymyr Babchuk
	, Andrew Cooper ,
	Anthony PERARD , Jan Beulich ,
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Wei Chen
	
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On 27/08/2025 13:31, Hari Limaye wrote:
> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email.
>
>
> Hi Michal,
Hi Hari, Michal,
>
>> On 22 Aug 2025, at 08:50, Orzel, Michal  wrote:
>>
>>
>>
>> On 30/07/2025 10:45, Hari Limaye wrote:
>>> From: Penny Zheng 
>>>
>>> In the function `init_staticmem_pages` we need to have mapped static
>>> memory banks for initialization. Unlike on an MMU system, we cannot map
>>> the entire RAM on an MPU system as we have a limited number of MPU
>>> memory regions. To solve this, transiently map the static memory banks
>>> for initialization.
>> How does this correspond to Arm32 MPU (R52), where all of the RAM will be
>> covered? I don't think 'transient' mappings will be needed there but all of your
>> work targets common (i.e. not only Arm64) MPU code.
>>
>> ~Michal
>>
> Hm fair point - when this series was submitted to the ML, I had no knowledge of the intention for all of the RAM to be mapped on Arm32 MPU systems and imagined that things would be more aligned here.
>
> Are happy for this to remain common for now? Or would you prefer it to be split off?

Let's split here between Arm_32 and Arm_64.

As discussed on Matrix, for Arm_32 we are mapping the entire static 
memory as a permanent MPU region. In light of Julien's comments and 
Alejandro's patch, I will revisit the approach in some time.
However, I don't want to create a dependency for this series.

We can realign later if needed. :)

- Ayan

>
> Many thanks,
> Hari


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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Topic: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcFpJ/0RYrIev2JkmWYheOK3kVZ7R2TMyAgAA17oA=
Date: Wed, 27 Aug 2025 13:38:57 +0000
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Date: Wed, 27 Aug 2025 16:44:23 +0300
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Subject: Re: [PATCH v3 10/11] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <642a994d712a8c9df7aed9dec22124564db83c7e.1756216943.git.leonid_komarianskyi@epam.com>
 <5a84d20c-5136-4151-8801-b0fbccaf23d7@gmail.com>
 
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From: Oleksandr Tyshchenko 
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On 27.08.25 14:13, Leonid Komarianskyi wrote:
> Hello Oleksandr,

Hello Leonid

> 
> Thank you for your close review.
> 
> On 26.08.25 22:57, Oleksandr Tyshchenko wrote:
>>
>>
>> On 26.08.25 17:05, Leonid Komarianskyi wrote:
>>
>> Hello Leonid
>>
>>
>>> Implemented support for GICv3.1 extended SPI registers for vGICv3,
>>> allowing the emulation of eSPI-specific behavior for guest domains.
>>> The implementation includes read and write emulation for eSPI-related
>>> registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
>>> following a similar approach to the handling of regular SPIs.
>>>
>>> The eSPI registers, previously located in reserved address ranges,
>>> are now adjusted to support MMIO read and write operations correctly
>>> when CONFIG_GICV3_ESPI is enabled.
>>>
>>> The availability of eSPIs and the number of emulated extended SPIs
>>> for guest domains is reported by setting the appropriate bits in the
>>> GICD_TYPER register, based on the number of eSPIs requested by the
>>> domain and supported by the hardware. In cases where the configuration
>>> option is disabled, the hardware does not support eSPIs, or the domain
>>> does not request such interrupts, the functionality remains unchanged.
>>>
>>> Signed-off-by: Leonid Komarianskyi 
>>>
>>> ---
>>> Changes in V2:
>>> - add missing rank index conversion for pending and inflight irqs
>>>
>>> Changes in V3:
>>> - changed vgic_store_irouter parameters - instead of offset virq is
>>>     used, to remove the additional bool espi parameter and simplify
>>>     checks. Also, adjusted parameters for regular SPI. Since the offset
>>>     parameter was used only for calculating virq number and then reused
>>> for
>>>     finding rank offset, it will not affect functionality.
>>> - fixed formatting for goto lables - added newlines after condition
>>> - fixed logs for GICD_ISACTIVERnE and GICD_ICACTIVERnE handlers
>>> - removed #ifdefs in 2 places where they were adjacent and could be
>>> merged
>>> ---
>>>    xen/arch/arm/vgic-v3.c | 275 +++++++++++++++++++++++++++++++++++++++--
>>>    1 file changed, 266 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
>>> index 4369c55177..56c539bb1b 100644
>>> --- a/xen/arch/arm/vgic-v3.c
>>> +++ b/xen/arch/arm/vgic-v3.c
>>> @@ -111,13 +111,10 @@ static uint64_t vgic_fetch_irouter(struct
>>> vgic_irq_rank *rank,
>>>     * Note the offset will be aligned to the appropriate boundary.
>>>     */
>>>    static void vgic_store_irouter(struct domain *d, struct
>>> vgic_irq_rank *rank,
>>> -                               unsigned int offset, uint64_t irouter)
>>> +                               unsigned int virq, uint64_t irouter)
>>>    {
>>>        struct vcpu *new_vcpu, *old_vcpu;
>>> -    unsigned int virq;
>>> -
>>> -    /* There is 1 vIRQ per IROUTER */
>>> -    virq = offset / NR_BYTES_PER_IROUTER;
>>> +    unsigned int offset;
>>>        /*
>>>         * The IROUTER0-31, used for SGIs/PPIs, are reserved and should
>>> @@ -685,6 +682,9 @@ static int __vgic_v3_distr_common_mmio_read(const
>>> char *name, struct vcpu *v,
>>>        {
>>>        case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>>>        case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
>>> +#endif
>>>            /* We do not implement security extensions for guests, read
>>> zero */
>>>            if ( dabt.size != DABT_WORD ) goto bad_width;
>>>            goto read_as_zero;
>>> @@ -710,11 +710,19 @@ static int
>>> __vgic_v3_distr_common_mmio_read(const char *name, struct vcpu *v,
>>>        /* Read the pending status of an IRQ via GICD/GICR is not
>>> supported */
>>>        case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
>>>        case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
>>> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
>>> +#endif
>>>            goto read_as_zero;
>>>        /* Read the active status of an IRQ via GICD/GICR is not
>>> supported */
>>>        case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
>>>        case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
>>> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
>>> +#endif
>>>            goto read_as_zero;
>>>        case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
>>> @@ -752,6 +760,69 @@ static int __vgic_v3_distr_common_mmio_read(const
>>> char *name, struct vcpu *v,
>>>            return 1;
>>>        }
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
>>> +        if ( dabt.size != DABT_WORD )
>>> +            goto bad_width;
>>> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE,
>>> DABT_WORD);
>>> +        if ( rank == NULL )
>>> +            goto read_as_zero;
>>> +        vgic_lock_rank(v, rank, flags);
>>> +        *r = vreg_reg32_extract(rank->ienable, info);
>>> +        vgic_unlock_rank(v, rank, flags);
>>> +        return 1;
>>> +
>>> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
>>> +        if ( dabt.size != DABT_WORD )
>>> +            goto bad_width;
>>> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE,
>>> DABT_WORD);
>>> +        if ( rank == NULL )
>>> +            goto read_as_zero;
>>> +        vgic_lock_rank(v, rank, flags);
>>> +        *r = vreg_reg32_extract(rank->ienable, info);
>>> +        vgic_unlock_rank(v, rank, flags);
>>> +        return 1;
>>> +
>>> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
>>> +    {
>>> +        uint32_t ipriorityr;
>>> +        uint8_t rank_index;
>>> +
>>> +        if ( dabt.size != DABT_BYTE && dabt.size != DABT_WORD )
>>> +            goto bad_width;
>>> +        rank = vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE,
>>> DABT_WORD);
>>> +        if ( rank == NULL )
>>> +            goto read_as_zero;
>>> +        rank_index = REG_RANK_INDEX(8, reg - GICD_IPRIORITYRnE,
>>> DABT_WORD);
>>> +
>>> +        vgic_lock_rank(v, rank, flags);
>>> +        ipriorityr = ACCESS_ONCE(rank->ipriorityr[rank_index]);
>>> +        vgic_unlock_rank(v, rank, flags);
>>> +
>>> +        *r = vreg_reg32_extract(ipriorityr, info);
>>> +
>>> +        return 1;
>>> +    }
>>> +
>>> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
>>> +    {
>>> +        uint32_t icfgr;
>>> +
>>> +        if ( dabt.size != DABT_WORD )
>>> +            goto bad_width;
>>> +        rank = vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE,
>>> DABT_WORD);
>>> +        if ( rank == NULL )
>>> +            goto read_as_zero;
>>> +        vgic_lock_rank(v, rank, flags);
>>> +        icfgr = rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE,
>>> DABT_WORD)];
>>> +        vgic_unlock_rank(v, rank, flags);
>>> +
>>> +        *r = vreg_reg32_extract(icfgr, info);
>>> +
>>> +        return 1;
>>> +    }
>>> +#endif
>>> +
>>>        default:
>>>            printk(XENLOG_G_ERR
>>>                   "%pv: %s: unhandled read r%d offset %#08x\n",
>>> @@ -782,6 +853,9 @@ static int __vgic_v3_distr_common_mmio_write(const
>>> char *name, struct vcpu *v,
>>>        {
>>>        case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>>>        case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
>>> +#endif
>>>            /* We do not implement security extensions for guests, write
>>> ignore */
>>>            goto write_ignore_32;
>>> @@ -871,6 +945,99 @@ static int
>>> __vgic_v3_distr_common_mmio_write(const char *name, struct vcpu *v,
>>>            vgic_unlock_rank(v, rank, flags);
>>>            return 1;
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
>>> +        if ( dabt.size != DABT_WORD )
>>> +            goto bad_width;
>>> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE,
>>> DABT_WORD);
>>> +        if ( rank == NULL )
>>> +            goto write_ignore;
>>> +        vgic_lock_rank(v, rank, flags);
>>> +        tr = rank->ienable;
>>> +        vreg_reg32_setbits(&rank->ienable, r, info);
>>> +        vgic_enable_irqs(v, (rank->ienable) & (~tr),
>>> EXT_RANK_IDX2NUM(rank->index));
>>> +        vgic_unlock_rank(v, rank, flags);
>>> +        return 1;
>>> +
>>> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
>>> +        if ( dabt.size != DABT_WORD )
>>> +            goto bad_width;
>>> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE,
>>> DABT_WORD);
>>> +        if ( rank == NULL )
>>> +            goto write_ignore;
>>> +        vgic_lock_rank(v, rank, flags);
>>> +        tr = rank->ienable;
>>> +        vreg_reg32_clearbits(&rank->ienable, r, info);
>>> +        vgic_disable_irqs(v, (~rank->ienable) & tr,
>>> EXT_RANK_IDX2NUM(rank->index));
>>> +        vgic_unlock_rank(v, rank, flags);
>>> +        return 1;
>>> +
>>> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
>>> +        if ( dabt.size != DABT_WORD )
>>> +            goto bad_width;
>>> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ISPENDRnE,
>>> DABT_WORD);
>>> +        if ( rank == NULL )
>>> +            goto write_ignore;
>>> +
>>> +        vgic_set_irqs_pending(v, r, EXT_RANK_IDX2NUM(rank->index));
>>> +
>>> +        return 1;
>>> +
>>> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
>>> +        if ( dabt.size != DABT_WORD )
>>> +            goto bad_width;
>>> +        rank = vgic_ext_rank_offset(v, 1, reg - GICD_ICPENDRnE,
>>> DABT_WORD);
>>> +        if ( rank == NULL )
>>> +            goto write_ignore;
>>> +
>>> +        vgic_check_inflight_irqs_pending(v, EXT_RANK_IDX2NUM(rank-
>>>> index), r);
>>> +
>>> +        goto write_ignore;
>>> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
>>> +        if ( dabt.size != DABT_WORD )
>>> +            goto bad_width;
>>> +        printk(XENLOG_G_ERR
>>> +               "%pv: %s: unhandled word write %#"PRIregister" to
>>> ISACTIVER%dE\n",
>>> +               v, name, r, reg - GICD_ISACTIVERnE);
>>> +        return 0;
>>
>> Guest write access to GICD_ISACTIVERE will lead to abort. But, I know
>> you just repeated the logic for regular GICD_ISACTIVER.
>>
>>
> 
> Could you please clarify the scenario in which it leads to an abort?
> Since it is actually a stub case, it should just print an error message
> and that's it..

"return 0;" will lead to injecting a fault into the guest.

  Do you mean that, in this case, we need to goto
> write_ignore_32 label instead of returning 0?

My comment was not a direct request to change anything, but rather 
thinking out loud.

Unfortunally, I cannot answer why regular GICD_ISACTIVER is emulated
in that way, but perhaps the injecting fault into the guest is the 
lesser evil than emulating it incorrectly...

Interestingly, for GICv2 we have a slighly relaxed version; it looks 
like writing 0 will not cause an abort and will be WI.
25f9e80201f3688e0c4d5c4e43e4b6143b441c52
xen/arm: Ignore write to GICD_ISACTIVERn registers (vgic-v2)

Now, with the introduction of extended GICD_ISACTIVERE you retained 
the logic. One thing that needs mentioning is that before your series,
guest write access to extended GICD_ISACTIVERE would be WI, but
with your series and CONFIG_GICV3_ESPI=y it will be an abort even
if running on GIC3 HW where eSPI is not supported.

At least, I would mention that in the patch description.


> 
>>> +
>>> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
>>> +        printk(XENLOG_G_ERR
>>> +               "%pv: %s: unhandled word write %#"PRIregister" to
>>> ICACTIVER%dE\n",
>>> +               v, name, r, reg - GICD_ICACTIVER);
>>
>> s/GICD_ICACTIVER/GICD_ICACTIVERnE
>>
>>
> 
> I will fix that in V4.
> 
>>> +        goto write_ignore_32;


[snip]


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CC: "xen-devel@lists.xenproject.org" ,
	Volodymyr Babchuk , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v3 09/11] xen/arm: domain_build/dom0less-build: adjust
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Thread-Topic: [PATCH v3 09/11] xen/arm: domain_build/dom0less-build: adjust
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Date: Wed, 27 Aug 2025 16:57:21 +0300
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Subject: Re: [PATCH v3 05/11] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <398ad09617f4f97d57d13fa9f3771bd2db83916b.1756216943.git.leonid_komarianskyi@epam.com>
 
 
Content-Language: en-US
From: Oleksandr Tyshchenko 
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On 27.08.25 16:38, Leonid Komarianskyi wrote:
> Hello Oleksandr,

Hello Leonid

> 
> Thank you for your good question, I was thinking about that as well.
> 
> On 27.08.25 13:25, Oleksandr Tyshchenko wrote:
>>
>>
>> On 26.08.25 17:05, Leonid Komarianskyi wrote:
>>
>>
>> Hello Leonid,
>>
>> In general patch looks good to me, just one question below ...
>>
>>> Introduced appropriate register definitions, helper macros,
>>> and initialization of required GICv3.1 distributor registers
>>> to support eSPI. This type of interrupt is handled in the
>>> same way as regular SPI interrupts, with the following
>>> differences:
>>>
>>> 1) eSPIs can have up to 1024 interrupts, starting from the
>>> beginning of the range, whereas regular SPIs use INTIDs from
>>> 32 to 1019, totaling 988 interrupts;
>>> 2) eSPIs start at INTID 4096, necessitating additional interrupt
>>> index conversion during register operations.
>>>
>>> In case if appropriate config is disabled, or GIC HW doesn't
>>> support eSPI, the existing functionality will remain the same.
>>>
>>> Signed-off-by: Leonid Komarianskyi 
>>>
>>> ---
>>> Changes in V2:
>>> - move gic_number_espis function from
>>>     [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
>>>     to use it in the newly introduced gic_is_valid_espi
>>> - add gic_is_valid_espi which checks if IRQ number is in supported
>>>     by HW eSPI range
>>> - update gic_is_valid_irq conditions to allow operations with eSPIs
>>>
>>> Changes in V3:
>>> - add __init attribute to gicv3_dist_espi_common_init
>>> - change open-codded eSPI register initialization to the appropriate
>>>     gen-mask macro
>>> - fixed formatting for lines with more than 80 symbols
>>> - introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
>>>     CONFIG_GICV3_ESPI disabled
>>> - renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
>>>     (name was taken from GIC specification) to avoid confusion
>>> - changed type for i variable to unsigned int since it cannot be
>>>     negative
>>> ---
>>>    xen/arch/arm/gic-v3.c                  | 80 ++++++++++++++++++++++++++
>>>    xen/arch/arm/include/asm/gic.h         | 21 +++++++
>>>    xen/arch/arm/include/asm/gic_v3_defs.h | 34 +++++++++++
>>>    3 files changed, 135 insertions(+)
>>>
>>> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
>>> index a959fefebe..3aa5cc1765 100644
>>> --- a/xen/arch/arm/gic-v3.c
>>> +++ b/xen/arch/arm/gic-v3.c
>>> @@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct
>>> irq_desc *irqd, u32 offset)
>>>            default:
>>>                break;
>>>            }
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
>>> +    {
>>> +        u32 irq_index = ESPI_INTID2IDX(irqd->irq);
>>> +
>>> +        switch ( offset )
>>> +        {
>>> +        case GICD_ISENABLER:
>>> +            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
>>> +        case GICD_ICENABLER:
>>> +            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
>>> +        case GICD_ISPENDR:
>>> +            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
>>> +        case GICD_ICPENDR:
>>> +            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
>>> +        case GICD_ISACTIVER:
>>> +            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
>>> +        case GICD_ICACTIVER:
>>> +            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
>>> +        case GICD_ICFGR:
>>> +            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
>>> +        case GICD_IROUTER:
>>> +            return (GICD + GICD_IROUTERnE + irq_index * 8);
>>> +        case GICD_IPRIORITYR:
>>> +            return (GICD + GICD_IPRIORITYRnE + irq_index);
>>> +        default:
>>> +            break;
>>> +        }
>>> +    }
>>> +#endif
>>>        default:
>>>            break;
>>>        }
>>> @@ -655,6 +685,52 @@ static void gicv3_set_irq_priority(struct
>>> irq_desc *desc,
>>>        spin_unlock(&gicv3.lock);
>>>    }
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +unsigned int gic_number_espis(void)
>>> +{
>>> +    return gic_hw_ops->info->nr_espi;
>>> +}
>>> +
>>> +static void __init gicv3_dist_espi_common_init(uint32_t type)
>>> +{
>>> +    unsigned int espi_nr, i;
>>> +
>>> +    espi_nr = min(1024U, GICD_TYPER_ESPIS_NUM(type));
>>> +    gicv3_info.nr_espi = espi_nr;
>>> +    /* The GIC HW doesn't support eSPI, so we can leave from here */
>>> +    if ( gicv3_info.nr_espi == 0 )
>>> +        return;
>>> +
>>> +    for ( i = 0; i < espi_nr; i += 16 )
>>> +        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
>>> +
>>> +    for ( i = 0; i < espi_nr; i += 4 )
>>> +        writel_relaxed(GIC_PRI_IRQ_ALL,
>>> +                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
>>> +
>>> +    for ( i = 0; i < espi_nr; i += 32 )
>>> +    {
>>> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i /
>>> 32) * 4);
>>> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i /
>>> 32) * 4);
>>> +    }
>>> +
>>> +    for ( i = 0; i < espi_nr; i += 32 )
>>> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i /
>>> 32) * 4);
>>> +}
>>> +
>>> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
>>> +{
>>> +    unsigned int i;
>>> +
>>> +    for ( i = 0; i < gicv3_info.nr_espi; i++ )
>>> +        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i
>>> * 8);
>>> +}
>>> +#else
>>> +static void __init gicv3_dist_espi_common_init(uint32_t type) { }
>>> +
>>> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
>>> +#endif
>>> +
>>>    static void __init gicv3_dist_init(void)
>>>    {
>>>        uint32_t type;
>>> @@ -700,6 +776,8 @@ static void __init gicv3_dist_init(void)
>>>        for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
>>>            writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i /
>>> 32) * 4);
>>
>>
>> There is a banner in this function (not visible from the patch context),
>> that prints nr_lines, etc.
>>
>> E.g.:
>> (XEN) GICv3: 288 lines, (IID 0000043b).
>>
>> What do you think, would it be important/valuable to also print nr_espi
>> if non-zero (extended SPI range is supported)?
>>
>>
> 
> I think so, it will be useful. By the way, native Linux prints this
> information, so I would prefer to add a message right after checking if
> the hardware supports eSPI:
>       /* The GIC HW doesn't support eSPI, so we can leave from here */
>       if ( gicv3_info.nr_espi == 0 )
>           return;
> 
>       printk("GICv3: %d eSPI lines\n", gicv3_info.nr_espi);
> 
> This log will appear right after the common one and will look like this:
> (XEN) GICv3: 988 lines, (IID 0000043b)
> (XEN) GICv3: 1024 eSPI lines

Looks very good!

> 
>>> +    gicv3_dist_espi_common_init(type);
>>> +
>>>        gicv3_dist_wait_for_rwp();
>>>        /* Turn on the distributor *
>>> @@ -713,6 +791,8 @@ static void __init gicv3_dist_init(void)
>>>        for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
>>>            writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i
>>> * 8);
>>> +
>>> +    gicv3_dist_espi_init_aff(affinity);
>>>    }
>>>
>>
>>
>> [snip]
>>
>>
>>
> 
> Best regards,
> Leonid.



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To: "Ritesh Harjani (IBM)" ,
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Cc: linux-mm@kvack.org, xen-devel@lists.xenproject.org,
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On 26.08.25 18:28, Ritesh Harjani (IBM) wrote:
> David Hildenbrand  writes:
> 
>> We want to make use of "pgtable_level" for an enum in core-mm. Other
>> architectures seem to call "struct pgtable_level" either:
>> * "struct pg_level" when not exposed in a header (riscv, arm)
>> * "struct ptdump_pg_level" when expose in a header (arm64)
>>
>> So let's follow what arm64 does.
>>
>> Signed-off-by: David Hildenbrand 
>> ---
>>   arch/powerpc/mm/ptdump/8xx.c      | 2 +-
>>   arch/powerpc/mm/ptdump/book3s64.c | 2 +-
>>   arch/powerpc/mm/ptdump/ptdump.h   | 4 ++--
>>   arch/powerpc/mm/ptdump/shared.c   | 2 +-
>>   4 files changed, 5 insertions(+), 5 deletions(-)
> 
> 
> As mentioned in commit msg mostly a mechanical change to convert
> "struct pgtable_level" to "struct ptdump_pg_level" for aforementioned purpose..
> 
> The patch looks ok and compiles fine on my book3s64 and ppc32 platform.
> 
> I think we should fix the subject line.. s/ptdump_pglevel/ptdump_pg_level
> 

Ahh, yes thanks.

@Andrew, can you fix that up?

> Otherwise the changes looks good to me. So please feel free to add -
> Reviewed-by: Ritesh Harjani (IBM) 

Thanks!

-- 
Cheers

David / dhildenb



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Subject: Re: [PATCH 1/3] xen: rework xen_pv_domain()
To: Juergen Gross , ,
	
CC: Boris Ostrovsky , Thomas Gleixner
	, Ingo Molnar , Borislav Petkov
	, Dave Hansen , "H. Peter Anvin"
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On 2025-08-26 10:56, Juergen Gross wrote:
> Rework xen_pv_domain() to no longer use the xen_domain_type variable,
> but the artificial X86_FEATURE_XENPV cpu feature.
> 
> On non-x86 architectures xen_pv_domain() can be defined as "0".
> 
> This has the advantage that a kernel not built with CONFIG_XEN_PV
> will be smaller due to dead code elimination.
> 
> Set the X86_FEATURE_XENPV feature very early, as xen_pv_domain() is
> used rather early, too.
> 
> Signed-off-by: Juergen Gross 

Reviewed-by: Jason Andryuk 


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Subject: Re: [PATCH 2/3] xen: replace XENFEAT_auto_translated_physmap with
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To: Juergen Gross , ,
	
CC: Boris Ostrovsky , Thomas Gleixner
	, Ingo Molnar , Borislav Petkov
	, Dave Hansen , "H. Peter Anvin"
	, Stefano Stabellini , Oleksandr
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On 2025-08-26 10:56, Juergen Gross wrote:
> Instead of testing the XENFEAT_auto_translated_physmap feature, just
> use !xen_pv_domain() which is equivalent.
> 
> This has the advantage that a kernel not built with CONFIG_XEN_PV
> will be smaller due to dead code elimination.
> 
> Signed-off-by: Juergen Gross 

Reviewed-by: Jason Andryuk 


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On 27.08.2025 15:19, Jason Andryuk wrote:
> On 2025-08-27 03:58, Jan Beulich wrote:
>> On 26.08.2025 23:08, Jason Andryuk wrote:
>>> --- a/xen/common/device-tree/dom0less-build.c
>>> +++ b/xen/common/device-tree/dom0less-build.c
>>> @@ -26,6 +26,7 @@
>>>   #include 
>>>   #include 
>>>   
>>> +#include 
>>>   #include 
>>>   
>>>   #include 
>>> @@ -120,8 +121,14 @@ static void __init initialize_domU_xenstore(void)
>>>   
>>>           if ( gfn != XENSTORE_PFN_LATE_ALLOC && IS_ENABLED(CONFIG_GRANT_TABLE) )
>>>           {
>>> +            evtchn_port_t port = d->arch.hvm.params[HVM_PARAM_STORE_EVTCHN];
>>> +            paddr_t evtchn_gaddr = gfn_to_gaddr(_gfn(gfn)) +
>>> +                offsetof(struct xenstore_domain_interface, evtchn_port);
>>> +
>>>               ASSERT(gfn < UINT32_MAX);
>>>               gnttab_seed_entry(d, GNTTAB_RESERVED_XENSTORE, xs_domid, gfn);
>>> +            access_guest_memory_by_gpa(d, evtchn_gaddr, &port, sizeof(port),
>>> +                                       true /* is_write */);
>>
>> Isn't the use of an arch-specific function going to pose yet another issue
>> for making this code usable on x86? Can't you use copy_to_guest_phys() here?
>> Which may in turn need to be passed in by the caller, see e.g. dtb_load()
>> and initrd_load() (i.e. cache flushing may also be necessary for Arm).
> 
> Yes, that could be done, but it's not my preferred approach.  Using a 
> function pointer to pass a compile time constant seems to me like a 
> misuse of a function pointer.
> 
> I'd rather each arch using dom0less define:
> unsigned long copy_to_guest_phys(struct domain *d,
>                                   paddr_t gpa,
>                                   void *buf,
>                                   unsigned int len);
> 
> Which does the correct thing for the arch.

That would be even better, just that I don't know whether Arm folks would
like it.

Jan

> Alejandro was able to re-work things to re-use the dom0less parsing code 
> (dom0less-bindings.c), but he has so far kept the x86 domain 
> construction separate such that it does not use dom0less-build.c.  So I 
> don't know how that will shake out.
> 
> But, yeah, I can just pass in a function pointer if that is what is 
> agreed upon.
> 
> Regards,
> Jason



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Date: Wed, 27 Aug 2025 10:01:23 -0400
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Subject: Re: [PATCH 3/3] drivers/xen/gntdev: use xen_pv_domain() instead of
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	, 
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On 2025-08-26 10:56, Juergen Gross wrote:
> Eliminate the use_ptemod variable by replacing its use cases with
> xen_pv_domain().
> 
> Instead of passing the xen_pv_domain() return value to
> gntdev_ioctl_dmabuf_exp_from_refs(), use xen_pv_domain() in that
> function.
> 
> Signed-off-by: Juergen Gross 

Reviewed-by: Jason Andryuk 


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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v3 10/11] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v3 10/11] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Index: AQHcFpKAKCVIbYC3hEGAz+VsUD3/gbR1WjCAgAD/ygCAACpFgIAAD94A
Date: Wed, 27 Aug 2025 14:41:11 +0000
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From xen-devel-bounces@lists.xenproject.org Wed Aug 27 14:46:39 2025
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Date: Wed, 27 Aug 2025 16:46:26 +0200
From: Anthony PERARD 
To: Oleksii Kurochko 
Cc: Xen-devel ,
	Community Manager ,
	"committers@xenproject.org" 
Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
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References: <07fc7122-d0ac-4dbe-800d-89086a07005b@gmail.com>
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On Mon, Aug 25, 2025 at 05:50:02PM +0200, Oleksii Kurochko wrote:
> Hello community,
> 
> I’d like to remind everyone that the Feature Freeze deadline is approaching,
> and we still have some outstanding requests from the community for patch series
> to be merged into 4.21:
> 
> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
> 2. Introduce SCI SCMI SMC multi-agent support [2]
> 3. Introduce eSPI support [3]
> 4. FRED work: [4], [5], possibly others (?)
> 5. Introduce CONFIG_DOMCTL [6]
> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
> 7. Some other patch series I missed.

Do we want to add this following one to the list?
- Allow to build libxl and other tools with json-c instead of yajl
https://lore.kernel.org/xen-devel/20250808145602.41716-1-anthony@xenproject.org/

Cheers,

-- 
Anthony PERARD


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Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Anthony PERARD ,
 Oleksii Kurochko 
Cc: Xen-devel ,
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On 27/08/2025 3:46 pm, Anthony PERARD wrote:
> On Mon, Aug 25, 2025 at 05:50:02PM +0200, Oleksii Kurochko wrote:
>> Hello community,
>>
>> I’d like to remind everyone that the Feature Freeze deadline is approaching,
>> and we still have some outstanding requests from the community for patch series
>> to be merged into 4.21:
>>
>> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
>> 2. Introduce SCI SCMI SMC multi-agent support [2]
>> 3. Introduce eSPI support [3]
>> 4. FRED work: [4], [5], possibly others (?)
>> 5. Introduce CONFIG_DOMCTL [6]
>> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
>> 7. Some other patch series I missed.
> Do we want to add this following one to the list?
> - Allow to build libxl and other tools with json-c instead of yajl
> https://lore.kernel.org/xen-devel/20250808145602.41716-1-anthony@xenproject.org/

Yes.  That was requested by downstreams, and is also bordering on a bugfix.

~Andrew


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On 2025-08-08 10:55, Anthony PERARD wrote:
> From: Anthony PERARD 
> 
> In a single place.
> 
> Signed-off-by: Anthony PERARD 

Reviewed-by: Jason Andryuk 


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Subject: Re: [XEN PATCH 02/11] libxl: Remove duplicate
 libxl_domain_config_gen_json prototype
To: Anthony PERARD , 
CC: Anthony PERARD , Juergen Gross
	
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-3-anthony@xenproject.org>
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On 2025-08-08 10:55, Anthony PERARD wrote:
> From: Anthony PERARD 
> 
> Since f9e681d3d1b8, the prototype of libxl_domain_config_gen_json is
> generated from IDL in _libxl_types_json.h.
> 
> Fixes: f9e681d3d1b8 ("libxl: move definition of libxl_domain_config into the IDL")
> Signed-off-by: Anthony PERARD 

Reviewed-by: Jason Andryuk 


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Subject: Re: [XEN PATCH 03/11] libxl: remove duplicated
 libxl__yajl_gen_asciiz() prototype
To: Anthony PERARD , 
CC: Anthony PERARD , Juergen Gross
	
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-4-anthony@xenproject.org>
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On 2025-08-08 10:55, Anthony PERARD wrote:
> From: Anthony PERARD 
> 
> Signed-off-by: Anthony PERARD 

Reviewed-by: Jason Andryuk 


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To: Anthony PERARD , 
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References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-5-anthony@xenproject.org>
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On 2025-08-08 10:55, Anthony PERARD wrote:
> From: Anthony PERARD 
> 
> To replace yajl.
> 
> Introduce YAJL_LIBS variable, to be able to remove "-lyajl" later.
> 
> Signed-off-by: Anthony PERARD 

Should the two configure changes be merged and placed at the end of the 
series?  That avoids a half implemented conversion in between.

I think Andrew's XEN_JSON_LIBS suggestion is a good one.

Regards,
Jason


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Subject: Re: [PATCH v2 1/3] xen/events: Cleanup find_virq() return codes
To: Jason Andryuk , Jan Beulich 
Cc: xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org,
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 Oleksandr Tyshchenko 
References: <20250826005517.41547-1-jason.andryuk@amd.com>
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To: Jason Andryuk , Jan Beulich 
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 Stefano Stabellini ,
 Oleksandr Tyshchenko 
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Subject: Re: [PATCH v2 1/3] xen/events: Cleanup find_virq() return codes
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 <20250826005517.41547-2-jason.andryuk@amd.com>
 
 
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On 2025-08-08 10:55, Anthony PERARD wrote:
> From: Anthony PERARD 
> 
> This reuse the "json_callback_*" implemented for the yajl parser as
> they don't really need to be changed. It's just awkward to have to
> cast between `unsigned char` and `char.`
> 
> Replace few strncpy() by memcpy() to let the compiler know we want to
> copy the string without the terminating nul, as we are adding it just
> after.
> 
> Also, it should be possible to keep using YAJL parser when json-c
> library isn't available.
> 
> Signed-off-by: Anthony PERARD 

Reviewed-by: Jason Andryuk 


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From xen-devel-bounces@lists.xenproject.org Wed Aug 27 15:22:34 2025
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Date: Wed, 27 Aug 2025 17:22:29 +0200
From: Anthony PERARD 
To: Penny Zheng 
Cc: xen-devel@lists.xenproject.org, ray.huang@amd.com,
	Anthony PERARD ,
	Juergen Gross ,
	Andrew Cooper ,
	Michal Orzel ,
	Jan Beulich , Julien Grall ,
	Roger Pau =?iso-8859-1?Q?Monn=E9?= ,
	Stefano Stabellini 
Subject: Re: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq
 para
Message-ID: 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-12-Penny.Zheng@amd.com>
MIME-Version: 1.0
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In-Reply-To: <20250822105218.3601273-12-Penny.Zheng@amd.com>

On Fri, Aug 22, 2025 at 06:52:16PM +0800, Penny Zheng wrote:
> diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
> index 6b054b10a4..8fc1d7cc65 100644
> --- a/tools/misc/xenpm.c
> +++ b/tools/misc/xenpm.c
> @@ -898,6 +900,23 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
>      printf("\n");
>  }
>  
> +/* show cpu cppc parameters information on CPU cpuid */
> +static int show_cppc_para_by_cpuid(xc_interface *xc_handle, unsigned int cpuid)
> +{
> +    int ret;
> +    xc_cppc_para_t cppc_para;
> +
> +    ret = xc_get_cppc_para(xc_handle, cpuid, &cppc_para);
> +    if ( !ret )
> +        print_cppc_para(cpuid, &cppc_para);
> +    else if ( errno == ENODEV )
> +        ret = 0; /* Ignore unsupported platform */
> +    else
> +        fprintf(stderr, "[CPU%u] failed to get cppc parameter\n", cpuid);

You might want to add ": %s" strerror(errno) to the error printed, which
could help figure out why we failed to get the parameters.


The rest of the tool side of the patch, with Jan suggestion, looks good
to me, so Acked-by: Anthony PERARD  for the
next round.

Thanks,

-- 
Anthony PERARD


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Date: Wed, 27 Aug 2025 17:28:25 +0200
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Subject: Re: [PATCH v2 3/3] xen/events: Update virq_to_irq on migration
To: Jason Andryuk ,
 Stefano Stabellini ,
 Oleksandr Tyshchenko ,
 Chris Wright ,
 Jeremy Fitzhardinge 
Cc: stable@vger.kernel.org, xen-devel@lists.xenproject.org,
 linux-kernel@vger.kernel.org
References: <20250826005517.41547-1-jason.andryuk@amd.com>
 <20250826005517.41547-4-jason.andryuk@amd.com>
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To: Jason Andryuk ,
 Stefano Stabellini ,
 Oleksandr Tyshchenko ,
 Chris Wright ,
 Jeremy Fitzhardinge 
Cc: stable@vger.kernel.org, xen-devel@lists.xenproject.org,
 linux-kernel@vger.kernel.org
Message-ID: 
Subject: Re: [PATCH v2 3/3] xen/events: Update virq_to_irq on migration
References: <20250826005517.41547-1-jason.andryuk@amd.com>
 <20250826005517.41547-4-jason.andryuk@amd.com>
In-Reply-To: <20250826005517.41547-4-jason.andryuk@amd.com>

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To: Anthony PERARD , 
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On 2025-08-08 10:55, Anthony PERARD wrote:
> From: Anthony PERARD 
> 
> Convert yajl_gen to json_object from lib json-c.
> 
> And make use of it in qmp_prepare_cmd(), which can be compiled with
> either lib.
> 
> Signed-off-by: Anthony PERARD 
> ---

> diff --git a/tools/libs/light/libxl_json.c b/tools/libs/light/libxl_json.c
> index 44ee6e213f..b26ac901d6 100644
> --- a/tools/libs/light/libxl_json.c
> +++ b/tools/libs/light/libxl_json.c
> @@ -631,6 +631,100 @@ const libxl__json_object *libxl__json_map_get(const char *key,
>       return NULL;
>   }
>   
> +#ifdef HAVE_LIBJSONC
> +int libxl__json_object_to_json_object(libxl__gc *gc,
> +                                      json_object **jso_out,
> +                                      const libxl__json_object *obj)
> +{
> +    int idx = 0;
> +    int rc, r;
> +
> +    switch (obj->type) {
> +    case JSON_NULL:
> +        *jso_out = json_object_new_null();
> +        return 0;
> +    case JSON_BOOL:
> +        *jso_out = json_object_new_boolean(obj->u.b);
> +        if (!*jso_out)
> +            return ERROR_NOMEM;
> +        return 0;
> +    case JSON_INTEGER:
> +        *jso_out = json_object_new_int64(obj->u.i);
> +        if (!*jso_out)
> +            return ERROR_NOMEM;
> +        return 0;
> +    case JSON_DOUBLE:
> +        *jso_out = json_object_new_double(obj->u.d);
> +        if (!*jso_out)
> +            return ERROR_NOMEM;
> +        return 0;
> +    case JSON_NUMBER:
> +        *jso_out = json_object_new_string(obj->u.string);

Is JSON_NUMBER calling json_object_new_string() correct?  It looks like 
the yajl code falls back to a string, so that is okay but surprising.

So I just want to double check.  If so:

Reviewed-by: Jason Andryuk 

Thanks,
Jason

> +        if (!*jso_out)
> +            return ERROR_NOMEM;
> +        return 0;


From xen-devel-bounces@lists.xenproject.org Wed Aug 27 15:38:04 2025
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From: Stefano Stabellini 
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To: Oleksii Moisieiev 
cc: Stefano Stabellini , 
    "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 00/10] xen/arm: scmi: introduce SCI SCMI SMC
 multi-agent support
In-Reply-To: <2eb538a8-aaf6-4d71-9379-40ae0351f0c6@epam.com>
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I completed the review of the patch series but as you could see from the
comments, the first few patches are far better along than the last two.

The current deadline is on Friday this week. I am happy to review this
series as promptly as I can but I am not sure we'll be able to complete
the last two patches.

Cheers,

Stefano


On Wed, 27 Aug 2025, Oleksii Moisieiev wrote:
> Hi Stefano,
> 
> Our use-case imply using scmi-smc-multiagent to be able to split scmi
> between the domains,
> so we would like to apply all patch series in the release.
> 
> On 23/08/2025 03:34, Stefano Stabellini wrote:
> > I think it should be feasible to commit at least patches 1-4 in time for
> > the release
> >
> > On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> >> Inroducing V4 RFC patch series  on top of the Xen version 4.20-rc2
> >> which includes implementation of the SCI SCMI SMC multi-agent support.
> >>
> >> Patch 1 "xen/arm: add generic SCI subsystem"
> >> - rebased and refactored
> >> - introduced DEVICE_ARM_SCI DT device class and used for SCI drivers probing
> >> instead of custom,
> >>    linker sections based implementation.
> >> - added SCI API for Dom0 DT handling, instead of manipulating with ARM arch
> >> dom0 code directly.
> >> - RFC changes in XEN_DOMCTL_assign_device OP processing
> >> - Introduce arch_handle_passthrough_prop call to handle arm specific
> >> nodes
> >>
> >> Patch 2 "xen/arm: scmi-smc: update to be used under sci subsystem"
> >> - update driver introduced by commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI
> >> over SMC calls
> >> handling layer") be used under sci subsystem.
> >> - no functional changes in general
> >>
> >> Patch 3 "xen/arm: scmi-smc: passthrough SCMI SMC to guest domain
> >> This is new change which allows passthrough SCMI SMC, single agent interface to
> >> guest domain
> >> cover use case "thin Dom0 with guest domain, which serves as Driver domain".
> >> See patch commit message for full description.
> >>
> >> Patch 4 - docs: arm: add docs for SCMI over SMC calls forwarding
> >> driver
> >> - add documentation section for Simple Arm SCMI over SMC/HVC calls
> >> forwarding driver.
> >>
> >> Patch 6 - xen/domctl: extend XEN_DOMCTL_assign_device to handle not
> >> only iommu
> >> - add chainged handling of assigned DT devices to support
> >> access-controller functionality through SCI framework.
> >> Change was done in two parts:
> >>   - update iommu_do_dt_domctl() to check for dt_device_is_protected()
> >>   and not fail if DT device is not protected by IOMMU
> >>   -add chained call to sci_do_domctl() to do_domctl()
> >>
> >> Patch 9 - xen/arm: scmi: introduce SCI SCMI SMC multi-agent driver
> >> - added "scmi-secondary-agents" and "#scmi-secondary-agent-cells"
> >>    property to "xen,config" node in "chosen" to inform SCI SCMI
> >>    multi-agent driver about available agents and their
> >>    configuration. It defines  to  map.
> >>    This option is Xen specific as Xen is the only one entry in the
> >>    system which need to know about SCMI multi-agent support and configuration.
> >> - each guest using SCMI should be configured with SCMI agent_id, so SCMI
> >>    FW can implement Agent-specific permission policy.
> >>    -- dom0: dom0_scmi_agent_id= in Xen command line option
> >>    -- toolstack: arm_sci = "type=scmi_smc_multiagent,agent_id="
> >>    -- dom0less: "xen,sci_type", "xen,sci_agent_id" properties in
> >> "xen,domain" nodes.
> >> - factored out SCMI generic definitions (re-usable)
> >> - factored out SCMI shmem code (re-usable)
> >> - the SCMI passthrough configuration for guest domains is similar to any other
> >> HW passthrough cfg.
> >>
> >> Patch 10 - docs: arm: add SCI SCMI SMC multi-agent driver docs
> >> - add SCI SCMI SMC multi-agent driver documentation.
> >>
> >> Add separate SCMI DT node for Xen management agent under "xen,config"
> >> node under chosen.
> >>
> >> All Xen-specific configuration provided under "/chosen" node. This
> >> approach allows to isolate modifications to Host DT only under
> >> "/chosen" node.
> >>
> >> This approach provides the following device tree (DT)
> >> parameters (placed under xen,config node):
> >>
> >> - "scmi-secondary-agents": A Xen-specific parameter under the
> >>    "/chosen" node, which describes the SCMI agent configuration for
> >>    the domains.
> >> - the SCMI configuration for Xen (privileged agent) and the shared
> >>    memory configuration for all agents are provided under the "/chosen"
> >>    node and are used strictly by Xen for its initial configuration.
> >> - the scmi_shm and SCMI configuration for Dom0 are placed in the
> >>    "/firmware/scmi" node so that they can be moved to Dom0 without
> >>    any changes.
> >>
> >> This configuration allows the use of Xen-specific nodes to provide
> >> information strictly needed by Xen while using the default SCMI
> >> configuration for Dom0 and other domains. As a result, no additional
> >> bindings need to be introduced to the device tree.
> >> This simplifies the Xen SCMI multi-agent configuration and utilizes
> >> generic device tree bindings for the domains.
> >>
> >> NOTE: Haven't added RB tags for patch 1 and 2 because rebase and some
> >> minor changes were done.
> >>
> >> Code can be found at:
> >> https://github.com/oleksiimoisieiev/xen/tree/scmi_upstrv5
> >>
> >> [1] RFC v2:
> >> http://patchwork.kernel.org/project/xen-devel/cover/cover.1644341635.git.oleksii_moisieiev@epam.com/
> >> [2] RFC v3:
> >> https://patchwork.kernel.org/project/xen-devel/patch/20250311111618.1850927-1-grygorii_strashko@epam.com
> >> SCMI spec:
> >> https://developer.arm.com/documentation/den0056/e/?lang=en
> >>
> >> SCMI bindings:
> >> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> >> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml
> >>
> >> Reference EL3 FW:
> >> RPI5: https://github.com/xen-troops/arm-trusted-firmware/commits/rpi5_dev/
> >> Renesas v4h:
> >> https://github.com/GrygiriiS/arm-trusted-firmware/commits/rcar_gen4_v2.7_v4x-scmi_upd/
> >>
> >> base-commit: dbe60f244c (Update Xen to 4.21, 2025-02-21)
> >>
> >> Changes in v5:
> >> - update Maintainers file. Set role as a Reviewer
> >> - rebased on the latest master branch
> >> - Introduce arch_handle_passthrough_prop call to handle arm specific nodes
> >> - rename dom0_scmi_smc_passthrough to scmi_smc_passthrough
> >> - rename dom0_scmi_smc_passthrough in documentation
> >> - set error code to -ENXIO when iommu is disabled
> >> - return -EINVAL if mediator without assign_dt_device was provided
> >> - invert return code check for iommu_do_domctl in
> >> XEN_DOMCTL_assign_device domctl processing to make cleaner code
> >> - change -ENOTSUPP error code to -ENXIO in sci_do_domctl
> >> - handle -ENXIO return comde of iommu_do_domctl
> >> - leave !dt_device_is_protected check in iommu_do_dt_domctl to make
> >> code work the same way it's done in "handle_device" call while
> >> creating hwdom(dom0) and "handle_passthrough_prop" call for dom0less
> >> creation
> >> - drop return check from sci_assign_dt_device call as not needed
> >> - do not return EINVAL when addign_dt_device is not set. That is
> >> because this callback is optional and not implemented in single-agent driver
> >> - move memcpy_toio/fromio to the generic place
> >> - fix device-tree example format in booting.txt, added ";" after "}".
> >> - update define in scmi-proto.h
> >> - update define in scmi-shmem.h file
> >> - scmi_assign_device - do not ignore -EOPNOTSUPP return
> >> code of the do_smc_xfer
> >> - remove overwriting agent_channel->agent_id after
> >> SCMI_BASE_DISCOVER_AGENT call
> >> - add multi-agent files to the MAINTAINERS
> >> - add SCMI multi-agent description to the SUPPORT.md
> >> - handle ARM_SMCCC_INVALID_PARAMETER return code and return -EINVAL
> >> for smc call
> >> - updated collect_agents function. Set agent_id parameter as optional
> >> in scmi-secondary-agents device-tree property
> >> - introduce "#scmi-secondary-agents-cells" parameter to set if
> >> agent_id was provided
> >> - reanme xen,scmi-secondary-agents property to scmi-secondary-agents
> >> - move memcpu_toio/fromio for the generic place
> >> - update Xen to get management channel from /chosen/xen,config node
> >> - get hypervisor channnel from node instead of using hardcoded
> >> - update handling scmi and shmem nodes for the domain
> >> - Set multi-agent driver to support only Arm64
> >> - rework multi-agent driver to leave Host Device-tree unmodified
> >>
> >> Changes in v4:
> >> - fix SPDX-License
> >> - rename DEVICE_ARM_SCI DT device class to FIRMWARE_DEVICE
> >> - move XEN_DOMCTL_assign_device code in separate patch
> >> - Add documentation for SCI SCMI drivers
> >> - xl.cfg doc
> >> - fix comments from Stefano Stabellini
> >> - fix toolstack code as sugested by Anthony PERARD
> >>    - use MATCH_OPTION()
> >>    - move arm_sci struct and cfg params in "arch_arm"
> >> - add SCMI passthrough for dom0less case
> >> - toolstack comments from Anthony PERARD
> >> - added dom0less support
> >> - added doc for "xen,scmi-secondary-agents"
> >>
> >> Grygorii Strashko (5):
> >>    xen/arm: scmi-smc: update to be used under sci subsystem
> >>    xen/arm: scmi-smc: passthrough SCMI SMC to domain, single agent
> >>    docs: arm: add docs for SCMI over SMC calls forwarding driver
> >>    xen/domctl: extend XEN_DOMCTL_assign_device to handle not only iommu
> >>    docs: arm: add SCI SCMI SMC multi-agent driver docs
> >>
> >> Oleksii Moisieiev (5):
> >>    xen/arm: add generic SCI subsystem
> >>    drivers: iommu: change error code when iommu is disabled
> >>    xen: arm: smccc: add INVALID_PARAMETER error code
> >>    lib/arm: Add I/O memory copy helpers
> >>    xen/arm: scmi: introduce SCI SCMI SMC multi-agent driver
> >>
> >>   MAINTAINERS                                   |  10 +
> >>   SUPPORT.md                                    |  11 +
> >>   .../arm/firmware/arm-scmi.rst                 | 516 +++++++++++
> >>   docs/hypervisor-guide/arm/index.rst           |   9 +
> >>   docs/hypervisor-guide/index.rst               |   1 +
> >>   docs/man/xl.cfg.5.pod.in                      |  47 +
> >>   docs/misc/arm/device-tree/booting.txt         | 103 +++
> >>   docs/misc/xen-command-line.pandoc             |  18 +
> >>   tools/include/libxl.h                         |   5 +
> >>   tools/libs/light/libxl_arm.c                  |  18 +
> >>   tools/libs/light/libxl_types.idl              |  12 +
> >>   tools/xl/xl_parse.c                           |  48 ++
> >>   xen/arch/arm/device.c                         |   5 +
> >>   xen/arch/arm/dom0less-build.c                 |  51 ++
> >>   xen/arch/arm/domain.c                         |  12 +-
> >>   xen/arch/arm/domain_build.c                   |  11 +-
> >>   xen/arch/arm/firmware/Kconfig                 |  37 +-
> >>   xen/arch/arm/firmware/Makefile                |   2 +
> >>   xen/arch/arm/firmware/sci.c                   | 189 +++++
> >>   xen/arch/arm/firmware/scmi-proto.h            | 164 ++++
> >>   xen/arch/arm/firmware/scmi-shmem.c            | 112 +++
> >>   xen/arch/arm/firmware/scmi-shmem.h            |  45 +
> >>   xen/arch/arm/firmware/scmi-smc-multiagent.c   | 803 ++++++++++++++++++
> >>   xen/arch/arm/firmware/scmi-smc.c              | 191 ++++-
> >>   xen/arch/arm/include/asm/domain.h             |   5 +
> >>   xen/arch/arm/include/asm/firmware/sci.h       | 214 +++++
> >>   xen/arch/arm/include/asm/firmware/scmi-smc.h  |  41 -
> >>   xen/arch/arm/include/asm/smccc.h              |   1 +
> >>   xen/arch/arm/vsmc.c                           |   4 +-
> >>   xen/common/device-tree/dom0less-build.c       |   4 +
> >>   xen/common/domctl.c                           |  19 +
> >>   xen/drivers/passthrough/device_tree.c         |   6 +
> >>   xen/drivers/passthrough/iommu.c               |   2 +-
> >>   xen/include/asm-generic/device.h              |   1 +
> >>   xen/include/asm-generic/dom0less-build.h      |   9 +
> >>   xen/include/public/arch-arm.h                 |   8 +
> >>   xen/include/xen/lib/arm/io.h                  |  15 +
> >>   xen/lib/Makefile                              |   1 +
> >>   xen/lib/arm/Makefile                          |   1 +
> >>   xen/lib/arm/io.c                              |  80 ++
> >>   40 files changed, 2744 insertions(+), 87 deletions(-)
> >>   create mode 100644 docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> >>   create mode 100644 docs/hypervisor-guide/arm/index.rst
> >>   create mode 100644 xen/arch/arm/firmware/sci.c
> >>   create mode 100644 xen/arch/arm/firmware/scmi-proto.h
> >>   create mode 100644 xen/arch/arm/firmware/scmi-shmem.c
> >>   create mode 100644 xen/arch/arm/firmware/scmi-shmem.h
> >>   create mode 100644 xen/arch/arm/firmware/scmi-smc-multiagent.c
> >>   create mode 100644 xen/arch/arm/include/asm/firmware/sci.h
> >>   delete mode 100644 xen/arch/arm/include/asm/firmware/scmi-smc.h
> >>   create mode 100644 xen/include/xen/lib/arm/io.h
> >>   create mode 100644 xen/lib/arm/Makefile
> >>   create mode 100644 xen/lib/arm/io.c
> >>
> >> --
> >> 2.34.1
> >>
> 


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Date: Wed, 27 Aug 2025 17:58:03 +0200
From: Anthony PERARD 
To: Penny Zheng 
Cc: xen-devel@lists.xenproject.org, ray.huang@amd.com,
	Anthony PERARD ,
	Andrew Cooper ,
	Michal Orzel ,
	Jan Beulich , Julien Grall ,
	Roger Pau =?iso-8859-1?Q?Monn=E9?= ,
	Stefano Stabellini 
Subject: Re: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Message-ID: 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-14-Penny.Zheng@amd.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20250822105218.3601273-14-Penny.Zheng@amd.com>

On Fri, Aug 22, 2025 at 06:52:18PM +0800, Penny Zheng wrote:
> diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
> index 02981c4583..eedb745a46 100644
> --- a/tools/misc/xenpm.c
> +++ b/tools/misc/xenpm.c
> @@ -38,6 +38,13 @@
>  static xc_interface *xc_handle;
>  static unsigned int max_cpu_nr;
>  
> +static const char cpufreq_policy_str[][12] = {

Is it necessary to hard-code an hand calculated size of the literal
strings? Can't we let the compiler do that for us? With this as type:

    static const char *cpufreq_policy_str[] = {

The compiler might not detect an issue if we write "11" instead of "12",
for example.

> +    [CPUFREQ_POLICY_UNKNOWN] = "unknown",
> +    [CPUFREQ_POLICY_POWERSAVE] = "powersave",
> +    [CPUFREQ_POLICY_PERFORMANCE] = "performance",
> +    [CPUFREQ_POLICY_ONDEMAND] = "ondemand",
> +};
> +
>  /* help message */
>  void show_help(void)
>  {

Otherwise the tool side of the patch looks fine to me,
so: Acked-by: Anthony PERARD 

Thanks,

-- 
Anthony PERARD


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Date: Wed, 27 Aug 2025 18:07:06 +0200
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Subject: Re: [PATCH 5/5] xen/arm: map static memory on demand
To: Hari Limaye 
CC: "xen-devel@lists.xenproject.org" , "Luca
 Fancellu" , Penny Zheng ,
	"Stefano Stabellini" , Julien Grall ,
	"Bertrand Marquis" , Volodymyr Babchuk
	, Andrew Cooper ,
	Anthony PERARD , Jan Beulich ,
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Wei Chen
	
References: 
 
 
 <7EDCD060-4EC7-4727-B524-225A5FB7A0B7@arm.com>
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On 27/08/2025 14:31, Hari Limaye wrote:
> Hi Michal,
> 
>> On 22 Aug 2025, at 08:50, Orzel, Michal  wrote:
>>
>>
>>
>> On 30/07/2025 10:45, Hari Limaye wrote:
>>> From: Penny Zheng 
>>>
>>> In the function `init_staticmem_pages` we need to have mapped static
>>> memory banks for initialization. Unlike on an MMU system, we cannot map
>>> the entire RAM on an MPU system as we have a limited number of MPU
>>> memory regions. To solve this, transiently map the static memory banks
>>> for initialization.
>> How does this correspond to Arm32 MPU (R52), where all of the RAM will be
>> covered? I don't think 'transient' mappings will be needed there but all of your
>> work targets common (i.e. not only Arm64) MPU code.
>>
>> ~Michal
>>
> 
> Hm fair point - when this series was submitted to the ML, I had no knowledge of the intention for all of the RAM to be mapped on Arm32 MPU systems and imagined that things would be more aligned here. 
> 
> Are happy for this to remain common for now? Or would you prefer it to be split off?
Let it be common for now. We can revisit it after the release to align on the
final approach.

~Michal



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To: Anthony PERARD 
Cc: xen-devel@lists.xenproject.org, ray.huang@amd.com,
 Anthony PERARD ,
 Andrew Cooper ,
 Michal Orzel , Julien Grall ,
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On 27.08.2025 17:58, Anthony PERARD wrote:
> On Fri, Aug 22, 2025 at 06:52:18PM +0800, Penny Zheng wrote:
>> diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
>> index 02981c4583..eedb745a46 100644
>> --- a/tools/misc/xenpm.c
>> +++ b/tools/misc/xenpm.c
>> @@ -38,6 +38,13 @@
>>  static xc_interface *xc_handle;
>>  static unsigned int max_cpu_nr;
>>  
>> +static const char cpufreq_policy_str[][12] = {
> 
> Is it necessary to hard-code an hand calculated size of the literal
> strings? Can't we let the compiler do that for us? With this as type:
> 
>     static const char *cpufreq_policy_str[] = {

I think it was me to request this. Your approach has an extra level of
indirection (perhaps not a big problem here), and requires runtime
relocations when building as PIE (maybe also not a big problem here).
The 2nd const that's wanted is also, as can be seen, frequently
omitted. Overall I'm generally striving towards using more efficient
code also where efficiency isn't of primary concern, simply because
code is being copied, often without looking very closely.

What we may want to do is bump to 12 to 16, adding some leeway and
making calculations a little easier.

Jan


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From: Mark Syms 
To: qemu-devel@nongnu.org,
	xen-devel@lists.xenproject.org
Cc: sstabellini@kernel.org,
	anthony@xenproject.org,
	paul@xen.org,
	Mark Syms 
Subject: [PATCH] [xen-block] Return BLKIF_RSP_EOPNOTSUPP for unknown operation
Date: Wed, 27 Aug 2025 17:08:41 +0100
Message-ID: <20250827160841.351707-1-mark.syms@cloud.com>
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Returning BLKIF_RSP_ERROR if an operation is not supoprted does not
allow the frontend to exercise any discretion on how to handle the
response and may lead to an operating system crash. As different
backends may support different feature sets and we might, during a
migration, switch backends, an in-flight request might be issued (or
reissued) which is then not supported by this backend.

Signed-off-by: Mark Syms 
---
 hw/block/dataplane/xen-block.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/block/dataplane/xen-block.c b/hw/block/dataplane/xen-block.c
index 48c2e315f3..32cf919a97 100644
--- a/hw/block/dataplane/xen-block.c
+++ b/hw/block/dataplane/xen-block.c
@@ -167,7 +167,8 @@ static int xen_block_parse_request(XenBlockRequest *request)
         return 0;
     default:
         error_report("error: unknown operation (%d)", request->req.operation);
-        goto err;
+        request->status = BLKIF_RSP_EOPNOTSUPP;
+        return -1;
     };
 
     if (request->req.operation != BLKIF_OP_READ &&
-- 
2.50.1



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Cc: luca.fancellu@arm.com,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v2 1/5] arm/mpu: Implement setup_frametable_mappings for MPU systems
Date: Wed, 27 Aug 2025 17:35:09 +0100
Message-ID: <99af1bac04c89a0c912f7f9c7e134ce79049e2a3.1756312498.git.hari.limaye@arm.com>
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From: Luca Fancellu 

Implement the MPU variant of `setup_frametable_mappings`. This function
will be called by `setup_mm` when an implementation for MPU systems is
added in a follow up commit.

Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
Reviewed-by: Michal Orzel 
---
Changes from v1:
- Align ps and pe to page size
- Add sanity checking for frametable size, as in MMU version
- Add Michal's R-b
---
 xen/arch/arm/mpu/mm.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index c6891607ec..3f155b7db2 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -168,6 +168,39 @@ int mpumap_contains_region(pr_t *table, uint8_t nr_regions, paddr_t base,
     return MPUMAP_REGION_NOTFOUND;
 }
 
+/* Map a frame table to cover physical addresses ps through pe */
+void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
+{
+    mfn_t base_mfn;
+    paddr_t aligned_ps = ROUNDUP(ps, PAGE_SIZE);
+    paddr_t aligned_pe = ROUNDDOWN(pe, PAGE_SIZE);
+
+    unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(aligned_pe), -1)) -
+                            mfn_to_pdx(maddr_to_mfn(aligned_ps)) + 1;
+    unsigned long frametable_size = nr_pdxs * sizeof(struct page_info);
+
+    /*
+     * The size of paddr_t should be sufficient for the complete range of
+     * physical address.
+     */
+    BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS);
+    BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE);
+
+    if ( frametable_size > FRAMETABLE_SIZE )
+        panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n",
+              ps, pe);
+
+    frametable_base_pdx = paddr_to_pdx(aligned_ps);
+    frametable_size = ROUNDUP(frametable_size, PAGE_SIZE);
+
+    base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1);
+    frame_table = (struct page_info *)mfn_to_virt(mfn_x(base_mfn));
+
+    memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info));
+    memset(&frame_table[nr_pdxs], -1,
+           frametable_size - (nr_pdxs * sizeof(struct page_info)));
+}
+
 /*
  * Allocate an entry for a new EL2 MPU region in the bitmap xen_mpumap_mask.
  * @param idx   Set to the index of the allocated EL2 MPU region on success.
-- 
2.34.1



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	Stefano Stabellini ,
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	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 0/5] Third series for R82 MPU support
Date: Wed, 27 Aug 2025 17:35:08 +0100
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Hi all,

This series is the third set of patches in the ongoing work to
introduce support for MPU systems and Cortex R82 in Xen.

The patches in this series implement the necessary logic to transiently
map and unmap the static memory banks for initialization.

Changes from v1:
- Changes mentioned in individual patches

Cheers,
Hari

Luca Fancellu (4):
  arm/mpu: Implement setup_frametable_mappings for MPU systems
  arm/mpu: Implement setup_mm for MPU systems
  arm/mpu: Implement transient mapping
  arm/mpu: Implement ioremap_attr for MPU

Penny Zheng (1):
  xen/arm: map static memory on demand

 xen/arch/arm/include/asm/arm32/mpu.h     |   2 +
 xen/arch/arm/include/asm/arm64/mpu.h     |   2 +
 xen/arch/arm/include/asm/mmu/mm.h        |   3 +
 xen/arch/arm/include/asm/mpu/mm.h        |  40 +++-
 xen/arch/arm/include/asm/mpu/regions.inc |  19 +-
 xen/arch/arm/mpu/mm.c                    | 262 +++++++++++++++++++++--
 xen/arch/arm/mpu/setup.c                 |  11 +
 xen/include/xen/static-memory.h          |   8 +
 8 files changed, 328 insertions(+), 19 deletions(-)

-- 
2.34.1



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	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v2 2/5] arm/mpu: Implement setup_mm for MPU systems
Date: Wed, 27 Aug 2025 17:35:10 +0100
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From: Luca Fancellu 

Implement `setup_mm` for MPU systems. This variant doesn't need to set
up the direct map.

Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
---
Changes from v1:
- Fix total_pages dead assignment
- Remove extraneous space
- Remove redundant max_page assignment
---
 xen/arch/arm/mpu/mm.c | 62 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index 3f155b7db2..4c517d6e43 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -8,9 +8,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 
 struct page_info *frame_table;
@@ -378,9 +381,66 @@ int map_pages_to_xen(unsigned long virt, mfn_t mfn, unsigned long nr_mfns,
     return xen_mpumap_update(virt, mfn_to_maddr(mfn_add(mfn, nr_mfns)), flags);
 }
 
+/*
+ * Heap must be statically configured in Device Tree through "xen,static-heap"
+ * on MPU systems.
+ */
+static void __init setup_staticheap_mappings(void)
+{
+    const struct membanks *reserved_mem = bootinfo_get_reserved_mem();
+    unsigned int bank = 0;
+
+    for ( ; bank < reserved_mem->nr_banks; bank++ )
+    {
+        if ( reserved_mem->bank[bank].type == MEMBANK_STATIC_HEAP )
+        {
+            paddr_t bank_start = round_pgup(reserved_mem->bank[bank].start);
+            paddr_t bank_size = round_pgdown(reserved_mem->bank[bank].size);
+            paddr_t bank_end = bank_start + bank_size;
+
+            /* Map static heap with one MPU protection region */
+            if ( xen_mpumap_update(bank_start, bank_end, PAGE_HYPERVISOR) )
+                panic("Failed to map static heap\n");
+
+            break;
+        }
+    }
+
+    if ( bank == reserved_mem->nr_banks )
+        panic("No static heap memory bank found\n");
+}
+
 void __init setup_mm(void)
 {
-    BUG_ON("unimplemented");
+    const struct membanks *mem = bootinfo_get_mem();
+    paddr_t ram_start = INVALID_PADDR, ram_end = 0, ram_size = 0;
+
+    if ( !mem->nr_banks )
+        panic("No memory bank\n");
+
+    init_pdx();
+
+    populate_boot_allocator();
+
+    for ( unsigned int bank = 0; bank < mem->nr_banks; bank++ )
+    {
+        paddr_t bank_start = round_pgup(mem->bank[bank].start);
+        paddr_t bank_size = round_pgdown(mem->bank[bank].size);
+        paddr_t bank_end = bank_start + bank_size;
+
+        ram_size = ram_size + bank_size;
+        ram_start = min(ram_start, bank_start);
+        ram_end = max(ram_end, bank_end);
+    }
+
+    setup_staticheap_mappings();
+
+    total_pages = ram_size >> PAGE_SHIFT;
+
+    setup_frametable_mappings(ram_start, ram_end);
+
+    init_staticmem_pages();
+    init_sharedmem_pages();
 }
 
 int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int nf)
-- 
2.34.1



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	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v2 3/5] arm/mpu: Implement transient mapping
Date: Wed, 27 Aug 2025 17:35:11 +0100
Message-ID: <80b0b3f84ae73f7d92d1b1cfe057ffc438882725.1756312498.git.hari.limaye@arm.com>
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From: Luca Fancellu 

Add a scheme to distinguish transient MPU regions, to identify MPU
regions which will be mapped for a short period of time. This is needed
for the functions which transiently map and unmap memory ranges on
demand which will be introduced in a future commit.

Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
---
Changes from v1:
- Improve commit message
- Mark parameter in read helper as const
---
 xen/arch/arm/include/asm/arm32/mpu.h     |  2 ++
 xen/arch/arm/include/asm/arm64/mpu.h     |  2 ++
 xen/arch/arm/include/asm/mpu/mm.h        | 14 +++++++++++++-
 xen/arch/arm/include/asm/mpu/regions.inc | 19 +++++++++++++++++--
 xen/arch/arm/mpu/mm.c                    | 23 ++++++++++++++---------
 5 files changed, 48 insertions(+), 12 deletions(-)

diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/asm/arm32/mpu.h
index 0a6930b3a0..9906d98809 100644
--- a/xen/arch/arm/include/asm/arm32/mpu.h
+++ b/xen/arch/arm/include/asm/arm32/mpu.h
@@ -39,6 +39,8 @@ typedef union {
 typedef struct {
     prbar_t prbar;
     prlar_t prlar;
+    bool transient;
+    uint8_t pad[7]; /* Pad structure to 16 Bytes */
 } pr_t;
 
 #endif /* __ASSEMBLY__ */
diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/asm/arm64/mpu.h
index f0ce344e78..1d1843eda0 100644
--- a/xen/arch/arm/include/asm/arm64/mpu.h
+++ b/xen/arch/arm/include/asm/arm64/mpu.h
@@ -38,6 +38,8 @@ typedef union {
 typedef struct {
     prbar_t prbar;
     prlar_t prlar;
+    bool transient;
+    uint8_t pad[15]; /* Pad structure to 32 Bytes */
 } pr_t;
 
 #endif /* __ASSEMBLY__ */
diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
index e1ded6521d..566d338986 100644
--- a/xen/arch/arm/include/asm/mpu/mm.h
+++ b/xen/arch/arm/include/asm/mpu/mm.h
@@ -55,6 +55,16 @@ static inline void context_sync_mpu(void)
     isb();
 }
 
+static inline bool region_is_transient(const pr_t *pr)
+{
+    return pr->transient;
+}
+
+static inline void region_set_transient(pr_t *pr, bool transient)
+{
+    pr->transient = transient;
+}
+
 /*
  * The following API requires context_sync_mpu() after being used to modify MPU
  * regions:
@@ -75,9 +85,11 @@ void write_protection_region(const pr_t *pr_write, uint8_t sel);
  * @param base      Base address of the range to map (inclusive).
  * @param limit     Limit address of the range to map (exclusive).
  * @param flags     Flags for the memory range to map.
+ * @param transient True for a transient mapping, otherwise False.
  * @return          0 on success, negative on error.
  */
-int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags);
+int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
+                      bool transient);
 
 /*
  * Creates a pr_t structure describing a protection region.
diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/include/asm/mpu/regions.inc
index 23fead3b21..f9892fe3d8 100644
--- a/xen/arch/arm/include/asm/mpu/regions.inc
+++ b/xen/arch/arm/include/asm/mpu/regions.inc
@@ -14,19 +14,31 @@
 #define PRLAR_ELx_EN            0x1
 
 #ifdef CONFIG_ARM_64
-#define XEN_MPUMAP_ENTRY_SHIFT  0x4     /* 16 byte structure */
+#define XEN_MPUMAP_ENTRY_SHIFT        0x5   /* 32 byte structure */
+#define XEN_MPUMAP_ENTRY_ZERO_OFFSET  0x10  /* {PRBAR, PRLAR} is 16 bytes  */
 
 .macro store_pair reg1, reg2, dst
     stp \reg1, \reg2, [\dst]
 .endm
 
+.macro zero_pair dst, offset, tmp1, tmp2
+    stp xzr, xzr, [\dst, \offset]
+.endm
+
 #else
-#define XEN_MPUMAP_ENTRY_SHIFT  0x3     /* 8 byte structure */
+#define XEN_MPUMAP_ENTRY_SHIFT        0x4   /* 16 byte structure */
+#define XEN_MPUMAP_ENTRY_ZERO_OFFSET  0x8   /* {PRBAR, PRLAR} is 8 bytes  */
 
 .macro store_pair reg1, reg2, dst
     strd  \reg1, \reg2, [\dst]
 .endm
 
+.macro zero_pair dst, offset, tmp1, tmp2
+    mov \tmp1, #0
+    mov \tmp2, #0
+    strd \tmp1, \tmp2, [\dst, \offset]
+.endm
+
 #endif
 
 /*
@@ -97,6 +109,9 @@
 
 3:
 
+    /* Clear the rest of the xen_mpumap entry. Clobbers prbar and prlar. */
+    zero_pair \base, #XEN_MPUMAP_ENTRY_ZERO_OFFSET, \prbar, \prlar
+
     add   \sel, \sel, #1
 
 1:
diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index 4c517d6e43..33333181d5 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -265,13 +265,14 @@ static void disable_mpu_region_from_index(uint8_t index)
  * Update the entry in the MPU memory region mapping table (xen_mpumap) for the
  * given memory range and flags, creating one if none exists.
  *
- * @param base  Base address (inclusive).
- * @param limit Limit address (exclusive).
- * @param flags Region attributes (a combination of PAGE_HYPERVISOR_XXX)
+ * @param base      Base address (inclusive).
+ * @param limit     Limit address (exclusive).
+ * @param flags     Region attributes (a combination of PAGE_HYPERVISOR_XXX)
+ * @param transient True for a transient mapping, otherwise False.
  * @return      0 on success, otherwise negative on error.
  */
 static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
-                                   unsigned int flags)
+                                   unsigned int flags, bool transient)
 {
     bool flags_has_page_present;
     uint8_t idx;
@@ -311,6 +312,7 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
             return -ENOENT;
 
         xen_mpumap[idx] = pr_of_addr(base, limit, flags);
+        region_set_transient(&xen_mpumap[idx], transient);
 
         write_protection_region(&xen_mpumap[idx], idx);
     }
@@ -330,7 +332,8 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
     return 0;
 }
 
-int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags)
+int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
+                      bool transient)
 {
     int rc;
 
@@ -356,7 +359,7 @@ int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags)
 
     spin_lock(&xen_mpumap_lock);
 
-    rc = xen_mpumap_update_entry(base, limit, flags);
+    rc = xen_mpumap_update_entry(base, limit, flags, transient);
     if ( !rc )
         context_sync_mpu();
 
@@ -371,14 +374,15 @@ int destroy_xen_mappings(unsigned long s, unsigned long e)
     ASSERT(IS_ALIGNED(e, PAGE_SIZE));
     ASSERT(s < e);
 
-    return xen_mpumap_update(s, e, 0);
+    return xen_mpumap_update(s, e, 0, false);
 }
 
 int map_pages_to_xen(unsigned long virt, mfn_t mfn, unsigned long nr_mfns,
                      unsigned int flags)
 {
     /* MPU systems have no translation, ma == va, so pass virt directly */
-    return xen_mpumap_update(virt, mfn_to_maddr(mfn_add(mfn, nr_mfns)), flags);
+    return xen_mpumap_update(virt, mfn_to_maddr(mfn_add(mfn, nr_mfns)), flags,
+                             false);
 }
 
 /*
@@ -399,7 +403,8 @@ static void __init setup_staticheap_mappings(void)
             paddr_t bank_end = bank_start + bank_size;
 
             /* Map static heap with one MPU protection region */
-            if ( xen_mpumap_update(bank_start, bank_end, PAGE_HYPERVISOR) )
+            if ( xen_mpumap_update(bank_start, bank_end, PAGE_HYPERVISOR,
+                                   false) )
                 panic("Failed to map static heap\n");
 
             break;
-- 
2.34.1



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From: Hari Limaye 
To: xen-devel@lists.xenproject.org
Cc: luca.fancellu@arm.com,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v2 4/5] arm/mpu: Implement ioremap_attr for MPU
Date: Wed, 27 Aug 2025 17:35:12 +0100
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From: Luca Fancellu 

Introduce helpers (un)map_mm_range() in order to allow the transient
mapping of a range of memory, and use these to implement the function
`ioremap_attr` for MPU systems.

Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
---
Changes from v1:
- Use transient instead of temporary, and improve wording of comments
  regarding transient mapping
- Rename start, end -> base, limit
---
 xen/arch/arm/include/asm/mpu/mm.h |  22 +++++
 xen/arch/arm/mpu/mm.c             | 150 ++++++++++++++++++++++++++++--
 2 files changed, 163 insertions(+), 9 deletions(-)

diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
index 566d338986..efb0680e39 100644
--- a/xen/arch/arm/include/asm/mpu/mm.h
+++ b/xen/arch/arm/include/asm/mpu/mm.h
@@ -101,6 +101,28 @@ int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
  */
 pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags);
 
+/*
+ * Maps transiently a range of memory with attributes `flags`; if the range is
+ * already mapped with the same attributes, including an inclusive match, the
+ * existing mapping is returned. This API is intended for mappings that exist
+ * transiently for a short period between calls to this function and
+ * `unmap_mm_range`.
+ *
+ * @param base      Base address of the range to map (inclusive).
+ * @param limit     Limit address of the range to map (exclusive).
+ * @param flags     Flags for the memory range to map.
+ * @return          Pointer to base of region on success, NULL on error.
+ */
+void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags);
+
+/*
+ * Unmaps a range of memory if it was previously mapped by map_mm_range,
+ * otherwise it does not remove the mapping.
+ *
+ * @param base     Base address of the range to map (inclusive).
+ */
+void unmap_mm_range(paddr_t base);
+
 /*
  * Checks whether a given memory range is present in the provided table of
  * MPU protection regions.
diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index 33333181d5..52c4c43827 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -332,31 +332,39 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
     return 0;
 }
 
-int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
-                      bool transient)
+static bool check_mpu_mapping(paddr_t base, paddr_t limit, unsigned int flags)
 {
-    int rc;
-
     if ( flags_has_rwx(flags) )
     {
         printk("Mappings should not be both Writeable and Executable\n");
-        return -EINVAL;
+        return false;
     }
 
     if ( base >= limit )
     {
         printk("Base address %#"PRIpaddr" must be smaller than limit address %#"PRIpaddr"\n",
                base, limit);
-        return -EINVAL;
+        return false;
     }
 
     if ( !IS_ALIGNED(base, PAGE_SIZE) || !IS_ALIGNED(limit, PAGE_SIZE) )
     {
         printk("base address %#"PRIpaddr", or limit address %#"PRIpaddr" is not page aligned\n",
                base, limit);
-        return -EINVAL;
+        return false;
     }
 
+    return true;
+}
+
+int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
+                      bool transient)
+{
+    int rc;
+
+    if ( !check_mpu_mapping(base, limit, flags) )
+        return -EINVAL;
+
     spin_lock(&xen_mpumap_lock);
 
     rc = xen_mpumap_update_entry(base, limit, flags, transient);
@@ -465,10 +473,134 @@ void free_init_memory(void)
     BUG_ON("unimplemented");
 }
 
+static uint8_t is_mm_range_mapped(paddr_t start, paddr_t end)
+{
+    int rc;
+    uint8_t idx;
+
+    ASSERT(spin_is_locked(&xen_mpumap_lock));
+
+    rc = mpumap_contains_region(xen_mpumap, max_mpu_regions, start, end, &idx);
+    if ( rc < 0 )
+         panic("Cannot handle overlapping MPU memory protection regions\n");
+
+    /*
+     * 'idx' will be INVALID_REGION_IDX for rc == MPUMAP_REGION_NOTFOUND and
+     * it will be a proper region index when rc >= MPUMAP_REGION_FOUND.
+     */
+    return idx;
+}
+
+static bool is_mm_attr_match(pr_t *region, unsigned int attributes)
+{
+    bool ret = true;
+
+    if ( region->prbar.reg.ro != PAGE_RO_MASK(attributes) )
+    {
+        printk(XENLOG_WARNING
+               "Mismatched Access Permission attributes (%#x0 instead of %#x0)\n",
+               region->prbar.reg.ro, PAGE_RO_MASK(attributes));
+        ret = false;
+    }
+
+    if ( region->prbar.reg.xn != PAGE_XN_MASK(attributes) )
+    {
+        printk(XENLOG_WARNING
+               "Mismatched Execute Never attributes (%#x instead of %#x)\n",
+               region->prbar.reg.xn, PAGE_XN_MASK(attributes));
+        ret = false;
+    }
+
+    if ( region->prlar.reg.ai != PAGE_AI_MASK(attributes) )
+    {
+        printk(XENLOG_WARNING
+               "Mismatched Memory Attribute Index (%#x instead of %#x)\n",
+               region->prlar.reg.ai, PAGE_AI_MASK(attributes));
+        ret = false;
+    }
+
+    return ret;
+}
+
+void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags)
+{
+    paddr_t start_pg = round_pgdown(base);
+    paddr_t end_pg = round_pgup(limit);
+    void *ret = NULL;
+    uint8_t idx;
+
+    if ( !check_mpu_mapping(start_pg, end_pg, flags) )
+        return NULL;
+
+    spin_lock(&xen_mpumap_lock);
+
+    idx = is_mm_range_mapped(start_pg, end_pg);
+    if ( idx != INVALID_REGION_IDX )
+    {
+        /* Already mapped with different attributes */
+        if ( !is_mm_attr_match(&xen_mpumap[idx], flags) )
+        {
+            printk(XENLOG_WARNING
+                   "Range %#"PRIpaddr"-%#"PRIpaddr" already mapped with different flags\n",
+                   start_pg, end_pg);
+            goto out;
+        }
+
+        /* Already mapped with same attributes */
+        ret = maddr_to_virt(base);
+        goto out;
+    }
+
+    if ( !xen_mpumap_update_entry(start_pg, end_pg, flags, true) )
+    {
+        context_sync_mpu();
+        ret = maddr_to_virt(base);
+    }
+
+ out:
+    spin_unlock(&xen_mpumap_lock);
+
+    return ret;
+}
+
+void unmap_mm_range(paddr_t base)
+{
+    uint8_t idx;
+
+    spin_lock(&xen_mpumap_lock);
+
+    /*
+     * Mappings created via map_mm_range are at least PAGE_SIZE. Find the idx
+     * of the MPU memory region containing `start` mapped through map_mm_range.
+     */
+    idx = is_mm_range_mapped(base, base + PAGE_SIZE);
+    if ( idx == INVALID_REGION_IDX )
+    {
+        printk(XENLOG_ERR
+               "Failed to unmap_mm_range MPU memory region at %#"PRIpaddr"\n",
+               base);
+        goto out;
+    }
+
+    /* This API is only meant to unmap transient regions */
+    if ( !region_is_transient(&xen_mpumap[idx]) )
+        goto out;
+
+    /* Disable MPU memory region and clear the associated entry in xen_mpumap */
+    disable_mpu_region_from_index(idx);
+    context_sync_mpu();
+
+ out:
+    spin_unlock(&xen_mpumap_lock);
+}
+
 void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int flags)
 {
-    BUG_ON("unimplemented");
-    return NULL;
+    if ( !map_mm_range(start, start + len, flags) )
+        return NULL;
+
+    /* Mapped or already mapped */
+    return maddr_to_virt(start);
 }
 
 /*
-- 
2.34.1



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To: xen-devel@lists.xenproject.org
Cc: luca.fancellu@arm.com,
	Penny Zheng ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Penny Zheng ,
	Wei Chen 
Subject: [PATCH v2 5/5] xen/arm: map static memory on demand
Date: Wed, 27 Aug 2025 17:35:13 +0100
Message-ID: <6408f218f3075acd43f5563bff26165091d9f184.1756312498.git.hari.limaye@arm.com>
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From: Penny Zheng 

In the function `init_staticmem_pages` we need to have mapped static
memory banks for initialization. Unlike on an MMU system, we cannot map
the entire RAM on an MPU system as we have a limited number of MPU
memory regions. To solve this, transiently map the static memory banks
for initialization.

Signed-off-by: Penny Zheng 
Signed-off-by: Wei Chen 
Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
---
 xen/arch/arm/include/asm/mmu/mm.h |  3 +++
 xen/arch/arm/include/asm/mpu/mm.h |  4 ++++
 xen/arch/arm/mpu/setup.c          | 11 +++++++++++
 xen/include/xen/static-memory.h   |  8 ++++++++
 4 files changed, 26 insertions(+)

diff --git a/xen/arch/arm/include/asm/mmu/mm.h b/xen/arch/arm/include/asm/mmu/mm.h
index 7f4d59137d..645a0ea3cb 100644
--- a/xen/arch/arm/include/asm/mmu/mm.h
+++ b/xen/arch/arm/include/asm/mmu/mm.h
@@ -110,6 +110,9 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr,
 extern void switch_ttbr(uint64_t ttbr);
 extern void relocate_and_switch_ttbr(uint64_t ttbr);
 
+static inline void map_staticmem_pages_to_xen(paddr_t start, paddr_t end) {}
+static inline void unmap_staticmem_pages_to_xen(paddr_t start, paddr_t end) {}
+
 #endif /* __ARM_MMU_MM_H__ */
 
 /*
diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
index efb0680e39..4cc769418e 100644
--- a/xen/arch/arm/include/asm/mpu/mm.h
+++ b/xen/arch/arm/include/asm/mpu/mm.h
@@ -123,6 +123,10 @@ void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags);
  */
 void unmap_mm_range(paddr_t base);
 
+/* {un}map_staticmem_pages_to_xen used while initializing static memory banks */
+void map_staticmem_pages_to_xen(paddr_t start, paddr_t end);
+void unmap_staticmem_pages_to_xen(paddr_t start, paddr_t end);
+
 /*
  * Checks whether a given memory range is present in the provided table of
  * MPU protection regions.
diff --git a/xen/arch/arm/mpu/setup.c b/xen/arch/arm/mpu/setup.c
index 163573b932..dbc3107333 100644
--- a/xen/arch/arm/mpu/setup.c
+++ b/xen/arch/arm/mpu/setup.c
@@ -83,6 +83,17 @@ void * __init early_fdt_map(paddr_t fdt_paddr)
     return fdt_virt;
 }
 
+void __init map_staticmem_pages_to_xen(paddr_t start, paddr_t end)
+{
+    if ( !map_mm_range(start, end, PAGE_HYPERVISOR) )
+        panic("Unable to map staticmem pages to Xen!");
+}
+
+void __init unmap_staticmem_pages_to_xen(paddr_t start, paddr_t end)
+{
+    unmap_mm_range(start);
+}
+
 /*
  * copy_from_paddr - copy data from a physical address
  * @dst: destination virtual address
diff --git a/xen/include/xen/static-memory.h b/xen/include/xen/static-memory.h
index e445aa8057..d99abac113 100644
--- a/xen/include/xen/static-memory.h
+++ b/xen/include/xen/static-memory.h
@@ -18,7 +18,15 @@ static inline void init_staticmem_bank(const struct membank *bank)
     if ( mfn_x(bank_end) <= mfn_x(bank_start) )
         return;
 
+    /* Map temporarily before initialization */
+    map_staticmem_pages_to_xen(mfn_to_maddr(bank_start),
+                               mfn_to_maddr(bank_end));
+
     unprepare_staticmem_pages(mfn_to_page(bank_start), bank_pages, false);
+
+    /* Unmap immediately after initialization */
+    unmap_staticmem_pages_to_xen(mfn_to_maddr(bank_start),
+                                 mfn_to_maddr(bank_end));
 }
 
 void allocate_static_memory(struct domain *d, struct kernel_info *kinfo,
-- 
2.34.1



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From: Hari Limaye 
To: "Orzel, Michal" 
CC: "xen-devel@lists.xenproject.org" , Luca
 Fancellu , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Volodymyr Babchuk 
Subject: Re: [PATCH 2/5] arm/mpu: Implement setup_mm for MPU systems
Thread-Topic: [PATCH 2/5] arm/mpu: Implement setup_mm for MPU systems
Thread-Index: AQHcEooIjidLhuh6q0+7EX7Ktw8WQ7R2xAoA
Date: Wed, 27 Aug 2025 17:04:01 +0000
Message-ID: <3D9F906F-83FE-47A8-A1FC-A871C1DE069F@arm.com>
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 <68a74142-667b-4b8e-8340-fd41ec15046c@amd.com>
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Hi Michal,

> And actually, this could be calculated
> in init_pdx() next to max_page to avoid requiring each arch (arm32, arm64=
, mpu)
> to set it exactly the same.

I have not implemented this in this series, as it seems like an unrelated c=
hange that should go separately. However if you prefer I can re-spin with t=
his change also?

Cheers,
Hari =


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Message-ID: <3cf8eef1-04e6-44b9-ad41-144de9cbf1d7@citrix.com>
Date: Wed, 27 Aug 2025 18:23:03 +0100
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Subject: Re: [PATCH] Optimise restore memory allocation
To: Frediano Ziglio ,
 xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Juergen Gross , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
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Subject wants to be at least tools/libxc, and probably "Use superpages
where possible on migrate/resume"


On 27/08/2025 1:33 pm, Frediano Ziglio wrote:
> Try to allocate larger order pages.
> With some test memory program stressing TLB (many small random
> memory accesses) you can get 15% performance improves.
> On the first memory iteration the sender is currently sending
> memory in 4mb aligned chunks which allows the receiver to
> allocate most pages as 2mb superpages instead of single 4kb pages.

It's critical to say somewhere that this is applicable to HVM guests.

You've eluded to it, but it's important to state clearly that, for HVM
guests, PAGE_DATA records contain metadata about GFNs in aligned 4M
blocks.  This is why we don't even need to buffer a second record.

It's also worth stating that 1G superpages are left for later.


CC-ing Oleksii as release manager.  This is a fix for a (mis)feature
which has been known for a decade (since Xen 4.6), and for which two
series have been posted but not managed to get in.  Unlike those series,
this is a very surgical fix that gets the majority of the perf win back,
without the complexity of trying to guess at 1G pages.

Therefore I'd like to request that it be considered for 4.21 at this
juncture.

>
> Signed-off-by: Frediano Ziglio 
> ---
>  tools/libs/guest/xg_sr_restore.c | 39 ++++++++++++++++++++++++++++----
>  1 file changed, 35 insertions(+), 4 deletions(-)
>
> diff --git a/tools/libs/guest/xg_sr_restore.c b/tools/libs/guest/xg_sr_restore.c
> index 06231ca826..8dcb1b19c5 100644
> --- a/tools/libs/guest/xg_sr_restore.c
> +++ b/tools/libs/guest/xg_sr_restore.c
> @@ -129,6 +129,8 @@ static int pfn_set_populated(struct xc_sr_context *ctx, xen_pfn_t pfn)
>      return 0;
>  }
>  
> +#define IS_POWER_OF_2(n) (((n) & ((n) - 1)) == 0)
> +
>  /*
>   * Given a set of pfns, obtain memory from Xen to fill the physmap for the
>   * unpopulated subset.  If types is NULL, no page type checking is performed
> @@ -141,6 +143,7 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
>      xen_pfn_t *mfns = malloc(count * sizeof(*mfns)),
>          *pfns = malloc(count * sizeof(*pfns));
>      unsigned int i, nr_pfns = 0;
> +    bool contiguous = true;
>      int rc = -1;
>  
>      if ( !mfns || !pfns )
> @@ -159,18 +162,46 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
>              if ( rc )
>                  goto err;
>              pfns[nr_pfns] = mfns[nr_pfns] = original_pfns[i];
> +            if ( pfns[nr_pfns] != pfns[0] + nr_pfns )
> +                contiguous = false;
>              ++nr_pfns;
>          }
>      }
>  
>      if ( nr_pfns )
>      {
> -        rc = xc_domain_populate_physmap_exact(
> -            xch, ctx->domid, nr_pfns, 0, 0, mfns);
> +        /* try optimizing using larger order */
> +        rc = -1;
> +        /*
> +         * The "nr_pfns <= (1 << 18)" check is mainly for paranoia, it should
> +         * never happen, the sender would have to send a really large packet.
> +         */
> +        if ( contiguous && nr_pfns <= (1 << 18) &&

This is an arbitrary limit, and to contradict the prior feedback given
in private, the domain's MAX_ORDER isn't relevant here.  It's the
toolstack's choice how to lay out the guest in memory.

> +             IS_POWER_OF_2(nr_pfns) && (pfns[0] & (nr_pfns - 1)) == 0 )
> +        {
> +            const unsigned int extent_order = __builtin_ffs(nr_pfns) - 1;

This (non-)loop isn't great.  You'll e.g. use 4k pages for the second 2M
page of an HVM guest simply because the VGA hole exists in the first.

I think you probably want something like:

int populate_physmap_4k(ctx, nr, mfns);
int populate_physmap_2M(ctx, nr, mfns);

as simple wrappers around the raw hypercalls including transforming back
the mfns[] array, and:

int populate_phymap(...);

with logic of the form:

    while ( nr )
    {
        if ( nr < 512 ) /* Can't be a superpage */
        {
            populate_physmap_4k(ctx, i, mfns);
            mfns += i;
            nr -= i;
            continue;
        }

        if ( !ALIGNED_2M(mfn) ) /* Populate up until a point that could be a superpage */
        {
            while ( !ALIGNED_2M(mfn + i) )
                i++;
            populate_physmap_4k(ctx, i, mfns);
            mfns += i;
            nr -= i;
        }

        if ( nr >= 512 )
        {
            for ( i = 1; i < 512; ++i )
                if ( mfns[i] != mfns[0] + i )
                    break;
            if ( i == 512 )
                populate_physmap_2M(ctx, i, mfns);
            else
                populate_physmap_4k(...);

            mfns += i;
            nr -= i;
        }
    }



Obviously with error handling, and whatever boundary conditions I've got
wrong.

2M is the only size that matters (ignoring 1G which we've excluded for
now), and this form will reconstruct more superpages for the guest than
trying to do 4M allocations will.

~Andrew


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Date: Wed, 27 Aug 2025 18:47:27 +0100
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Subject: Re: [PATCH] hvmloader: Update to SMBIOS 2.6
To: Teddy Astie , xen-devel@lists.xenproject.org
Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
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References: 
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From: Andrew Cooper 
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On 22/08/2025 2:47 pm, Teddy Astie wrote:
> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
>
> In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
> (undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
> you have a endian mismatch causing the UUIDs to mismatch in the guest.
>
> $ cat /sys/hypervisor/uuid
> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
> $ cat /sys/devices/virtual/dmi/id/product_uuid
> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
> $ cat /sys/devices/virtual/dmi/id/product_serial
> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>
> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
> written in the table; which effectively fix this endianness mismatch with
> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.
>
> Signed-off-by: Teddy Astie 
> ---
> This effectively changes the UUID seen with UEFI guests as it was
> actually inconsistent with SeaBIOS and SMBIOS expectations.
> ---

I agree this is a real bug and needs fixing.  However, ...


>  tools/firmware/hvmloader/smbios.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/tools/firmware/hvmloader/smbios.c b/tools/firmware/hvmloader/smbios.c
> index 6bcdcc233a..f4822ae6f8 100644
> --- a/tools/firmware/hvmloader/smbios.c
> +++ b/tools/firmware/hvmloader/smbios.c
> @@ -352,7 +352,7 @@ smbios_entry_point_init(void *start,
>      memcpy(ep->anchor_string, "_SM_", 4);
>      ep->length = 0x1f;
>      ep->smbios_major_version = 2;
> -    ep->smbios_minor_version = 4;
> +    ep->smbios_minor_version = 6;
>      ep->max_structure_size = max_structure_size;
>      ep->entry_point_revision = 0;
>      memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
> @@ -462,7 +462,23 @@ smbios_type_1_init(void *start, const char *xen_version,
>      p->version_str = 3;
>      p->serial_number_str = 4;
>  
> -    memcpy(p->uuid, uuid, 16);
> +    /*
> +     * Xen uses OSF DCE UUIDs which is fully big endian, however,
> +     * GUIDs (which requirement is clarified by SMBIOS >= 2.6) has the
> +     * first 3 components appearing as being little endian and the rest
> +     * as still being big endian.

... this is not an accurate statement.

Xen specifically tries to treat a xen_domain_handle_t as an opaque blob.

The only two areas I can see ascribing any structure are the 'q'
debugkey (not exactly a strong ABI statement), and the arinc635
scheduler whose use is buggy (uuids are not unique in Xen; it's the
domid which is).

It is an error that a format isn't stated, but the format comes from the
toolstack.  We'd better hope that all toolstacks use OSF DCE UUIDs, or
this is going to badly wrong.

And on that note, the toolstacks are not the same.  Xapi for example
uses reads 16 bytes out of /dev/urandom.

Whatever we end up doing, the fix must include a change to
xen/include/public/version.h stating the format of the UUID.

~Andrew


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Subject: Re: [XEN PATCH 07/11] libxl: libxl__object_to_json() to json-c
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References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-8-anthony@xenproject.org>
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On 2025-08-08 10:55, Anthony PERARD wrote:
> From: Anthony PERARD 
> 
> - libxl changes:
> 
> While doing so, we rename all "*_gen_json" function to "*_gen_jso" as
> they have different prototype. All the function pointer are been cast
> to (libxl__gen_json_callback) by "gentypes.py" when generating
> "*_to_json()" functions.
> 
> We also introduce a few more "*_gen_jso" functions for "int" and
> "bool" because we can't use json_object_*() functions from json-c
> directly like it's done with yajl.
> 
> To make the generation of _libxl_types*json.[ch] with both YAJL and
> json-c we add "--libjsonc" to gentypes.py so it can generate
> functions/types for both.
> 
> Also introducing "jsonc_json_gen_fn" in the IDL, to be able to point
> to a different function when using json-c.
> 
> Also, don't export any of the new *_gen_jso() function, at the cost of
> having "_hidden" macro in semi-public headers.
> 
> - xl changes:
> 
> Also, rework the implementation of printf_info() in `xl` to avoid
> using libxl_domain_config_gen_json() which isn't available without
> YAJL. The implementation using "json_object" call
> libxl_domain_config_to_json() which generate a plain string of JSON,
> which we parse to add it to our own json; this avoid a dependency on
> the json library used by libxl.
> 
> Signed-off-by: Anthony PERARD 

> @@ -358,6 +535,36 @@ int libxl__mac_parse_json(libxl__gc *gc, const libxl__json_object *o,
>       return libxl__parse_mac(libxl__json_object_get_string(o), *p);
>   }
>   
> +#ifdef HAVE_LIBJSONC
> +int libxl_hwcap_gen_jso(json_object **jso_r, libxl_hwcap *p)
> +{
> +    json_object *jso;
> +    int i;
> +    int rc = ERROR_FAIL;
> +
> +    jso = json_object_new_array();
> +    if (!jso) goto out;
> +
> +    for(i=0; i<4; i++) {

typedef uint32_t libxl_hwcap[8];

I see this is the same as the yajl implementation, but should this be 8?

The remainder looks good:

Reviewed-by: Jason Andryuk 

Thanks,
Jason

> +        json_object *jso_value = json_object_new_int((*p)[i]);
> +        if (!jso_value)
> +            goto out;
> +        int r = json_object_array_add(jso, jso_value);
> +        if (r) {
> +            json_object_put(jso_value);
> +            goto out;
> +        }
> +    }
> +    *jso_r = jso;
> +    jso = NULL;
> +    rc = 0;
> +out:
> +    json_object_put(jso);
> +    return rc;
> +}
> +#endif
> +
> +#ifdef HAVE_LIBYAJL
>   yajl_gen_status libxl_hwcap_gen_json(yajl_gen hand,
>                                        libxl_hwcap *p)
>   {


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Subject: Re: [XEN PATCH 08/11] libxl: convert libxl__json_object_to_json() to
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To: Anthony PERARD , 
CC: Anthony PERARD , Juergen Gross
	
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-9-anthony@xenproject.org>
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On 2025-08-08 10:55, Anthony PERARD wrote:
> From: Anthony PERARD 
> 
> But keep the implementation done for YAJL.
> 
> Signed-off-by: Anthony PERARD 

Reviewed-by: Jason Andryuk 


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Subject: Re: [XEN PATCH 07/11] libxl: libxl__object_to_json() to json-c
To: Jason Andryuk ,
 Anthony PERARD , xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Juergen Gross 
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-8-anthony@xenproject.org>
 <05c49cee-d783-40e3-a4ce-da724c308a21@amd.com>
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On 27/08/2025 6:51 pm, Jason Andryuk wrote:
> On 2025-08-08 10:55, Anthony PERARD wrote:
>> From: Anthony PERARD 
>>
>> - libxl changes:
>>
>> While doing so, we rename all "*_gen_json" function to "*_gen_jso" as
>> they have different prototype. All the function pointer are been cast
>> to (libxl__gen_json_callback) by "gentypes.py" when generating
>> "*_to_json()" functions.
>>
>> We also introduce a few more "*_gen_jso" functions for "int" and
>> "bool" because we can't use json_object_*() functions from json-c
>> directly like it's done with yajl.
>>
>> To make the generation of _libxl_types*json.[ch] with both YAJL and
>> json-c we add "--libjsonc" to gentypes.py so it can generate
>> functions/types for both.
>>
>> Also introducing "jsonc_json_gen_fn" in the IDL, to be able to point
>> to a different function when using json-c.
>>
>> Also, don't export any of the new *_gen_jso() function, at the cost of
>> having "_hidden" macro in semi-public headers.
>>
>> - xl changes:
>>
>> Also, rework the implementation of printf_info() in `xl` to avoid
>> using libxl_domain_config_gen_json() which isn't available without
>> YAJL. The implementation using "json_object" call
>> libxl_domain_config_to_json() which generate a plain string of JSON,
>> which we parse to add it to our own json; this avoid a dependency on
>> the json library used by libxl.
>>
>> Signed-off-by: Anthony PERARD 
>
>> @@ -358,6 +535,36 @@ int libxl__mac_parse_json(libxl__gc *gc, const
>> libxl__json_object *o,
>>       return libxl__parse_mac(libxl__json_object_get_string(o), *p);
>>   }
>>   +#ifdef HAVE_LIBJSONC
>> +int libxl_hwcap_gen_jso(json_object **jso_r, libxl_hwcap *p)
>> +{
>> +    json_object *jso;
>> +    int i;
>> +    int rc = ERROR_FAIL;
>> +
>> +    jso = json_object_new_array();
>> +    if (!jso) goto out;
>> +
>> +    for(i=0; i<4; i++) {
>
> typedef uint32_t libxl_hwcap[8];
>
> I see this is the same as the yajl implementation, but should this be 8?
>
> The remainder looks good:
>
> Reviewed-by: Jason Andryuk 

A tangent, but physinfo.hw_cap (which libxl_hwcap wraps) is as good as
stack rubble.  It's not exactly random data, but it is a view of an
internal Xen structure which has been reformatted multiple times before
we even realised it was exported, then continued being reformatting it
because it's a gross laying violation that noone could possibly be using
anyway.

It needs purging from libxl and the sysctl interface, and if that makes
JSON easier, then lets get it done.

~Andrew


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Subject: Re: [XEN PATCH 09/11] tools/libxenstat: Use json-c when available
To: Anthony PERARD , 
CC: Anthony PERARD , Juergen Gross
	
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-10-anthony@xenproject.org>
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On 2025-08-08 10:56, Anthony PERARD wrote:
> From: Anthony PERARD 
> 
> This is mainly a copy of the existing code in yajl and use json-c
> instead.
> 
> Signed-off-by: Anthony PERARD 

Reviewed-by: Jason Andryuk 


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	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Anthony PERARD ,
	Oleksii Kurochko , Community Manager
	
Subject: [PATCH v4 00/12] Introduce eSPI support
Thread-Topic: [PATCH v4 00/12] Introduce eSPI support
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Hello everyone!

This is the fourth version of the patch series to introduce support, which
contains fixes and improvements based on the feedback received in V3.
Mostly, these are minor changes in individual patches, except for the follo=
wing:
xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers

Now includes additional checks for domains without eSPI support to ensure t=
hey
behave as they currently do when reading or writing eSPI registers - RAZ or=
 WI
as it also described in the GICv3.1 documentation, when GICD_TYPER.ESPI=3D=
=3D0.

Summarized description:
This patch series adds support for the extended shared peripheral
interrupt (eSPI) range (INTIDs 4096-5119 [2](ranges of INTIDs)) for Xen
and guest domains. The implementation uses a generic approach to handle
eSPIs, similar to regular SPIs, while maintaining compatibility with the
existing SPI range. Functionality remains unchanged for setups that do
not require eSPIs.

The series includes:
1) General refactoring of common IRQ operations with GIC registers to
improve code readability, simplify further maintenance and prepare the
key functions for eSPI implementation.
2) Introducing a new Kconfig option (default n) to enable or disable
eSPI support. Disabling this option prevents unnecessary resource
allocation for setups that do not require eSPIs.
3) Adding additional resources to store required information and operate
with up to 1024 interrupts from eSPI range.
4) Adjusting assertions and checks to pass verification for INTIDs in
the eSPI range.
5) Configuration of eSPI-specific registers during GIC initialization
for systems with GICv3.1+ hardware.
6) Enables eSPI MMIO emulation for vGIC, allowing guest domains to
access and operate within the eSPI's INTIDs.
7) Updating documentation and CHANGELOG to reflect the changes made for eSP=
I
support.

Also, to simplify reviewing, please find below link to unsquashed patches, =
that
are on top of every patch, that is changed in the series, compared to V3:
https://github.com/LKomaryanskiy/xen/commits/espi-support-master-upstream-v=
4-unsquashed/


Changes in V4:
- added a patch for documentation
- individual changes in patches

Link on V3:
- https://lists.xenproject.org/archives/html/xen-devel/2025-08/msg01628.htm=
l

Changes in V3:
- added a patch to update CHANGELOG.md
- individual changes in patches

Link on V2:
- https://lists.xenproject.org/archives/html/xen-devel/2025-08/msg00372.htm=
l

Changes in V2:
- added 2 more patches to implement helper
  functions for gic/vgic:
  xen/arm: gic: implement helper functions for INTID checks
  xen/arm: vgic: implement helper functions for virq checks
- removed 2 patches:
  xen/arm/irq: allow assignment/releasing of eSPI interrupts
  xen/arm: gic/irq: permit routing of eSPI interrupts to Xen and domains
  since their functionality can be moved to appropriate patches after
  introducing patches with helper functions
- individual changes in patches

Link on V1:
- https://lists.xenproject.org/archives/html/xen-devel/2025-07/msg01809.htm=
l


Leonid Komarianskyi (12):
  xen/arm: gicv3: refactor obtaining GIC addresses for common operations
  xen/arm: gic: implement helper functions for INTID checks
  xen/arm: vgic: implement helper functions for virq checks
  xen/arm/irq: add handling for IRQs in the eSPI range
  xen/arm: gicv3: implement handling of GICv3.1 eSPI
  xen/arm/irq: allow eSPI processing in the gic_interrupt function
  xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow eSPI processing
  xen/arm: vgic: add resource management for extended SPIs
  xen/arm: domain_build/dom0less-build: adjust domains config to support
    eSPIs
  xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers
  doc/man: update description for nr_spis with eSPI
  CHANGELOG.md: add mention of GICv3.1 eSPI support

 CHANGELOG.md                           |   1 +
 docs/man/xl.cfg.5.pod.in               |  13 +-
 xen/arch/arm/Kconfig                   |   8 +
 xen/arch/arm/dom0less-build.c          |   2 +-
 xen/arch/arm/domain_build.c            |   2 +-
 xen/arch/arm/gic-v3.c                  | 194 +++++++++++---
 xen/arch/arm/gic.c                     |   7 +-
 xen/arch/arm/include/asm/gic.h         |  31 +++
 xen/arch/arm/include/asm/gic_v3_defs.h |  40 ++-
 xen/arch/arm/include/asm/irq.h         |  27 ++
 xen/arch/arm/include/asm/vgic.h        |  48 ++++
 xen/arch/arm/irq.c                     |  58 ++++-
 xen/arch/arm/vgic-v3.c                 | 333 +++++++++++++++++++++++--
 xen/arch/arm/vgic.c                    | 223 ++++++++++++++++-
 xen/arch/arm/vgic/vgic.c               |   5 +
 15 files changed, 924 insertions(+), 68 deletions(-)

--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk 
Subject: [PATCH v4 01/12] xen/arm: gicv3: refactor obtaining GIC addresses for
 common operations
Thread-Topic: [PATCH v4 01/12] xen/arm: gicv3: refactor obtaining GIC
 addresses for common operations
Thread-Index: AQHcF3/CtR1KedyUO0e9jC2sdgHn6g==
Date: Wed, 27 Aug 2025 18:24:01 +0000
Message-ID:
 <5f511d386c7f20b09106aa0202e0989477eff498.1756317702.git.leonid_komarianskyi@epam.com>
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Currently, many common functions perform the same operations to calculate
GIC register addresses. This patch consolidates the similar code into
a separate helper function to improve maintainability and reduce duplicatio=
n.
This refactoring also simplifies the implementation of eSPI support in futu=
re
changes.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 

---
Changes in V4:
- no changes

Changes in V3:
- changed panic() in get_addr_by_offset() to printing warning and
  ASSERT_UNREACHABLE()
- added verification of return pointer from get_addr_by_offset() in the
  callers
- moved invocation of get_addr_by_offset() from spinlock guards, since
  it is not necessarry
- added RB from Volodymyr Babchuk

Changes in V2:
- no changes
---
 xen/arch/arm/gic-v3.c          | 114 +++++++++++++++++++++++----------
 xen/arch/arm/include/asm/irq.h |   1 +
 2 files changed, 81 insertions(+), 34 deletions(-)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index cd3e1acf79..a959fefebe 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -445,17 +445,67 @@ static void gicv3_dump_state(const struct vcpu *v)
     }
 }
=20
+static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
+{
+    switch ( irqd->irq )
+    {
+    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+        case GICD_ICENABLER:
+        case GICD_ISPENDR:
+        case GICD_ICPENDR:
+        case GICD_ISACTIVER:
+        case GICD_ICACTIVER:
+            return (GICD_RDIST_SGI_BASE + offset);
+        case GICD_ICFGR:
+            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
+        case GICD_IPRIORITYR:
+            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
+        default:
+            break;
+        }
+    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+        case GICD_ICENABLER:
+        case GICD_ISPENDR:
+        case GICD_ICPENDR:
+        case GICD_ISACTIVER:
+        case GICD_ICACTIVER:
+            return (GICD + offset + (irqd->irq / 32) * 4);
+        case GICD_ICFGR:
+            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
+        case GICD_IROUTER:
+            return (GICD + GICD_IROUTER + irqd->irq * 8);
+        case GICD_IPRIORITYR:
+            return (GICD + GICD_IPRIORITYR + irqd->irq);
+        default:
+            break;
+        }
+    default:
+        break;
+    }
+
+    /* Something went wrong, we shouldn't be able to reach here */
+    printk(XENLOG_WARNING "GICv3: WARNING: Invalid offset 0x%x for IRQ#%d"=
,
+           offset, irqd->irq);
+    ASSERT_UNREACHABLE();
+
+    return NULL;
+}
+
 static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_fo=
r_rwp)
 {
     u32 mask =3D 1U << (irqd->irq % 32);
-    void __iomem *base;
+    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
=20
-    if ( irqd->irq < NR_GIC_LOCAL_IRQS )
-        base =3D GICD_RDIST_SGI_BASE;
-    else
-        base =3D GICD;
+    if ( addr =3D=3D NULL )
+        return;
=20
-    writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
+    writel_relaxed(mask, addr);
=20
     if ( wait_for_rwp )
         gicv3_wait_for_rwp(irqd->irq);
@@ -463,15 +513,12 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u32=
 offset, bool wait_for_rwp)
=20
 static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset)
 {
-    void __iomem *base;
-    unsigned int irq =3D irqd->irq;
+    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
=20
-    if ( irq >=3D NR_GIC_LOCAL_IRQS)
-        base =3D GICD + (irq / 32) * 4;
-    else
-        base =3D GICD_RDIST_SGI_BASE;
+    if ( addr =3D=3D NULL )
+        return false;
=20
-    return !!(readl(base + offset) & (1U << (irq % 32)));
+    return !!(readl(addr) & (1U << (irqd->irq % 32)));
 }
=20
 static void gicv3_unmask_irq(struct irq_desc *irqd)
@@ -558,30 +605,28 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cp=
u)
 static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type)
 {
     uint32_t cfg, actual, edgebit;
-    void __iomem *base;
-    unsigned int irq =3D desc->irq;
+    void __iomem *addr;
=20
     /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
-    ASSERT(irq >=3D NR_GIC_SGI);
+    ASSERT(desc->irq >=3D NR_GIC_SGI);
=20
-    spin_lock(&gicv3.lock);
+    addr =3D get_addr_by_offset(desc, GICD_ICFGR);
+    if ( addr =3D=3D NULL )
+        return;
=20
-    if ( irq >=3D NR_GIC_LOCAL_IRQS)
-        base =3D GICD + GICD_ICFGR + (irq / 16) * 4;
-    else
-        base =3D GICD_RDIST_SGI_BASE + GICR_ICFGR1;
+    spin_lock(&gicv3.lock);
=20
-    cfg =3D readl_relaxed(base);
+    cfg =3D readl_relaxed(addr);
=20
-    edgebit =3D 2u << (2 * (irq % 16));
+    edgebit =3D 2u << (2 * (desc->irq % 16));
     if ( type & IRQ_TYPE_LEVEL_MASK )
         cfg &=3D ~edgebit;
     else if ( type & IRQ_TYPE_EDGE_BOTH )
         cfg |=3D edgebit;
=20
-    writel_relaxed(cfg, base);
+    writel_relaxed(cfg, addr);
=20
-    actual =3D readl_relaxed(base);
+    actual =3D readl_relaxed(addr);
     if ( ( cfg & edgebit ) ^ ( actual & edgebit ) )
     {
         printk(XENLOG_WARNING "GICv3: WARNING: "
@@ -600,16 +645,13 @@ static void gicv3_set_irq_type(struct irq_desc *desc,=
 unsigned int type)
 static void gicv3_set_irq_priority(struct irq_desc *desc,
                                    unsigned int priority)
 {
-    unsigned int irq =3D desc->irq;
+    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IPRIORITYR);
=20
-    spin_lock(&gicv3.lock);
-
-    /* Set priority */
-    if ( irq < NR_GIC_LOCAL_IRQS )
-        writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + =
irq);
-    else
-        writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
+    if ( addr =3D=3D NULL )
+        return;
=20
+    spin_lock(&gicv3.lock);
+    writeb_relaxed(priority, addr);
     spin_unlock(&gicv3.lock);
 }
=20
@@ -1273,6 +1315,10 @@ static void gicv3_irq_set_affinity(struct irq_desc *=
desc, const cpumask_t *mask)
 {
     unsigned int cpu;
     uint64_t affinity;
+    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IROUTER);
+
+    if ( addr =3D=3D NULL )
+        return;
=20
     ASSERT(!cpumask_empty(mask));
=20
@@ -1284,7 +1330,7 @@ static void gicv3_irq_set_affinity(struct irq_desc *d=
esc, const cpumask_t *mask)
     affinity &=3D ~GICD_IROUTER_SPI_MODE_ANY;
=20
     if ( desc->irq >=3D NR_GIC_LOCAL_IRQS )
-        writeq_relaxed_non_atomic(affinity, (GICD + GICD_IROUTER + desc->i=
rq * 8));
+        writeq_relaxed_non_atomic(affinity, addr);
=20
     spin_unlock(&gicv3.lock);
 }
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.=
h
index fce7e42a33..5bc6475eb4 100644
--- a/xen/arch/arm/include/asm/irq.h
+++ b/xen/arch/arm/include/asm/irq.h
@@ -29,6 +29,7 @@ struct arch_irq_desc {
  */
 #define NR_IRQS		1024
=20
+#define SPI_MAX_INTID   1019
 #define LPI_OFFSET      8192
=20
 /* LPIs are always numbered starting at 8192, so 0 is a good invalid case.=
 */
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk 
Subject: [PATCH v4 02/12] xen/arm: gic: implement helper functions for INTID
 checks
Thread-Topic: [PATCH v4 02/12] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Index: AQHcF3/Ff+oSmGvjakq9bpLMhjgPlA==
Date: Wed, 27 Aug 2025 18:24:04 +0000
Message-ID:
 <684757e6710826200bcc153e4c711b27483ee796.1756317702.git.leonid_komarianskyi@epam.com>
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Introduced two new helper functions: gic_is_valid_line and
gic_is_spi. The first function helps determine whether an IRQ
number is less than the number of lines supported by hardware. The
second function additionally checks if the IRQ number falls within the
SPI range. Also, updated the appropriate checks to use these new helper
functions.

The current checks for the real GIC are very similar to those for the
vGIC but serve a different purpose. For GIC-related code, the interrupt
numbers should be validated based on whether the hardware can operate
with such interrupts. On the other hand, for the vGIC, the indexes must
also be verified to ensure they are available for a specific domain. The
first reason for introducing these helper functions is to avoid
potential confusion with vGIC-related checks. The second reason is to
consolidate similar code into separate functions, which can be more
easily extended by additional conditions, e.g., when implementing
extended SPI interrupts.

The changes, which replace open-coded checks with the use of the new
helper functions, do not introduce any functional changes, as the helper
functions follow the current IRQ index verification logic.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 

---
Changes in V4:
- removed redundant parentheses
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- renamed gic_is_valid_irq to gic_is_valid_line and gic_is_shared_irq to
  gic_is_spi
- updated commit message

Changes in V2:
- introduced this patch

Changes for V4:

Changes in V4:
- removed redundant parentheses
- added reviewed-by from Volodymyr Babchuk
---
 xen/arch/arm/gic.c             | 2 +-
 xen/arch/arm/include/asm/gic.h | 9 +++++++++
 xen/arch/arm/irq.c             | 2 +-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index e80fe0ca24..9220eef6ea 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -111,7 +111,7 @@ static void gic_set_irq_priority(struct irq_desc *desc,=
 unsigned int priority)
 void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority)
 {
     ASSERT(priority <=3D 0xff);     /* Only 8 bits of priority */
-    ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that =
don't exist */
+    ASSERT(gic_is_valid_line(desc->irq));/* Can't route interrupts that do=
n't exist */
     ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
     ASSERT(spin_is_locked(&desc->lock));
=20
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.=
h
index 541f0eeb80..3fcee42675 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -306,6 +306,15 @@ extern void gic_dump_vgic_info(struct vcpu *v);
=20
 /* Number of interrupt lines */
 extern unsigned int gic_number_lines(void);
+static inline bool gic_is_valid_line(unsigned int irq)
+{
+    return irq < gic_number_lines();
+}
+
+static inline bool gic_is_spi(unsigned int irq)
+{
+    return irq >=3D NR_LOCAL_IRQS && gic_is_valid_line(irq);
+}
=20
 /* IRQ translation function for the device tree */
 int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 03fbb90c6c..7dd5a2a453 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -415,7 +415,7 @@ err:
 bool is_assignable_irq(unsigned int irq)
 {
     /* For now, we can only route SPIs to the guest */
-    return (irq >=3D NR_LOCAL_IRQS) && (irq < gic_number_lines());
+    return gic_is_spi(irq);
 }
=20
 /*
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v4 03/12] xen/arm: vgic: implement helper functions for virq
 checks
Thread-Topic: [PATCH v4 03/12] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Index: AQHcF3/Ha+nKa9jlz0+nkOWkY9CitQ==
Date: Wed, 27 Aug 2025 18:24:08 +0000
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 <65b148aea56b1a35fa061b0d8284584da97153a9.1756317702.git.leonid_komarianskyi@epam.com>
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Introduced two new helper functions for vGIC: vgic_is_valid_line and
vgic_is_spi. The functions are similar to the newly introduced
gic_is_valid_line and gic_is_spi, but they verify whether a vIRQ
is available for a specific domain, while GIC-specific functions
validate INTIDs for the real GIC hardware. For example, the GIC may
support all 992 SPI lines, but the domain may use only some part of them
(e.g., 640), depending on the highest IRQ number defined in the domain
configuration. Therefore, for vGIC-related code and checks, the
appropriate functions should be used. Also, updated the appropriate
checks to use these new helper functions.

The purpose of introducing new helper functions for vGIC is essentially
the same as for GIC: to avoid potential confusion with GIC-related
checks and to consolidate similar code into separate functions, which
can be more easily extended by additional conditions, e.g., when
implementing extended SPI interrupts.

Only the validation change in vgic_inject_irq may affect existing
functionality, as it currently checks whether the vIRQ is less than or
equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
first SPI), the check should behave consistently with similar logic in
other places and should check if the vIRQ number is less than
vgic_num_irqs. The remaining changes, which replace open-coded checks
with the use of these new helper functions, do not introduce any
functional changes, as the helper functions follow the current vIRQ
index verification logic.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V4:
- removed redundant parentheses

Changes in V3:
- renamed vgic_is_valid_irq to vgic_is_valid_line and vgic_is_shared_irq
  to vgic_is_spi
- added vgic_is_valid_line implementation for new-vgic, because
  vgic_is_valid_line is called from generic code. It is necessary to fix
  the build for new-vgic.
- updated commit message

Changes in V2:
- introduced this patch
---
 xen/arch/arm/gic.c              |  3 +--
 xen/arch/arm/include/asm/vgic.h |  7 +++++++
 xen/arch/arm/irq.c              |  4 ++--
 xen/arch/arm/vgic.c             | 10 ++++++++--
 xen/arch/arm/vgic/vgic.c        |  5 +++++
 5 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 9220eef6ea..b88237ccda 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -133,8 +133,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned i=
nt virq,
=20
     ASSERT(spin_is_locked(&desc->lock));
     /* Caller has already checked that the IRQ is an SPI */
-    ASSERT(virq >=3D 32);
-    ASSERT(virq < vgic_num_irqs(d));
+    ASSERT(vgic_is_spi(d, virq));
     ASSERT(!is_lpi(virq));
=20
     ret =3D vgic_connect_hw_irq(d, NULL, virq, desc, true);
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 35c0c6a8b0..3e7cbbb196 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -335,6 +335,13 @@ extern void vgic_check_inflight_irqs_pending(struct vc=
pu *v,
 /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
 #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
=20
+extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
+
+static inline bool vgic_is_spi(struct domain *d, unsigned int virq)
+{
+    return virq >=3D NR_LOCAL_IRQS && vgic_is_valid_line(d, virq);
+}
+
 /*
  * Allocate a guest VIRQ
  *  - spi =3D=3D 0 =3D> allocate a PPI. It will be the same on every vCPU
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 7dd5a2a453..b8eccfc924 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -442,7 +442,7 @@ int route_irq_to_guest(struct domain *d, unsigned int v=
irq,
     unsigned long flags;
     int retval =3D 0;
=20
-    if ( virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_valid_line(d, virq) )
     {
         printk(XENLOG_G_ERR
                "the vIRQ number %u is too high for domain %u (max =3D %u)\=
n",
@@ -560,7 +560,7 @@ int release_guest_irq(struct domain *d, unsigned int vi=
rq)
     int ret;
=20
     /* Only SPIs are supported */
-    if ( virq < NR_LOCAL_IRQS || virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_spi(d, virq) )
         return -EINVAL;
=20
     desc =3D vgic_get_hw_irq_desc(d, NULL, virq);
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index c563ba93af..2bbf4d99aa 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -24,6 +24,12 @@
 #include 
 #include 
=20
+
+bool vgic_is_valid_line(struct domain *d, unsigned int virq)
+{
+    return virq < vgic_num_irqs(d);
+}
+
 static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
                                                   unsigned int rank)
 {
@@ -582,7 +588,7 @@ void vgic_inject_irq(struct domain *d, struct vcpu *v, =
unsigned int virq,
     if ( !v )
     {
         /* The IRQ needs to be an SPI if no vCPU is specified. */
-        ASSERT(virq >=3D 32 && virq <=3D vgic_num_irqs(d));
+        ASSERT(vgic_is_spi(d, virq));
=20
         v =3D vgic_get_target_vcpu(d->vcpu[0], virq);
     };
@@ -659,7 +665,7 @@ bool vgic_emulate(struct cpu_user_regs *regs, union hsr=
 hsr)
=20
 bool vgic_reserve_virq(struct domain *d, unsigned int virq)
 {
-    if ( virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_valid_line(d, virq) )
         return false;
=20
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index 6cabd0496d..b2c0e1873a 100644
--- a/xen/arch/arm/vgic/vgic.c
+++ b/xen/arch/arm/vgic/vgic.c
@@ -718,6 +718,11 @@ bool vgic_reserve_virq(struct domain *d, unsigned int =
virq)
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
 }
=20
+bool vgic_is_valid_line(struct domain *d, unsigned int virq)
+{
+    return virq < vgic_num_irqs(d);
+}
+
 int vgic_allocate_virq(struct domain *d, bool spi)
 {
     int first, end;
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk 
Subject: [PATCH v4 04/12] xen/arm/irq: add handling for IRQs in the eSPI range
Thread-Topic: [PATCH v4 04/12] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcF3/JNF+Qat2pckartE+JXKhKmg==
Date: Wed, 27 Aug 2025 18:24:12 +0000
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Currently, Xen does not support eSPI interrupts, leading
to a data abort when such interrupts are defined in the DTS.

This patch introduces a separate array to initialize up to
1024 interrupt descriptors in the eSPI range and adds the
necessary defines and helper function. These changes lay the
groundwork for future implementation of full eSPI interrupt
support. As this GICv3.1 feature is not required by all vendors,
all changes are guarded by ifdefs, depending on the corresponding
Kconfig option.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 

---
Changes in V4:
- removed redundant line with 'default n' in Kconfig, as it is disabled
  by default, without explicit specification
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- introduced a new define NR_ESPI_IRQS to avoid confusion, like in the
  case of using NR_IRQS for espi_desc array
- implemented helper functions espi_to_desc and init_espi_data to make
  it possible to add stubs with the same name, and as a result, reduce
  the number of #ifdefs
- disable CONFIG_GICV3_ESPI default value to n

Changes in V2:
- use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
- remove unnecessary comment for nr_irqs initialization
---
 xen/arch/arm/Kconfig           |  8 ++++++
 xen/arch/arm/include/asm/irq.h | 26 +++++++++++++++++
 xen/arch/arm/irq.c             | 52 +++++++++++++++++++++++++++++++++-
 3 files changed, 85 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 17df147b25..43b05533b1 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -135,6 +135,14 @@ config GICV3
 	  Driver for the ARM Generic Interrupt Controller v3.
 	  If unsure, use the default setting.
=20
+config GICV3_ESPI
+	bool "Extended SPI range support"
+	depends on GICV3 && !NEW_VGIC
+	help
+	  Allow Xen and domains to use interrupt numbers from the extended SPI
+	  range, from 4096 to 5119. This feature is introduced in GICv3.1
+	  architecture.
+
 config HAS_ITS
         bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORT=
ED
         depends on GICV3 && !NEW_VGIC && !ARM_32
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.=
h
index 5bc6475eb4..221dbf23a2 100644
--- a/xen/arch/arm/include/asm/irq.h
+++ b/xen/arch/arm/include/asm/irq.h
@@ -32,6 +32,15 @@ struct arch_irq_desc {
 #define SPI_MAX_INTID   1019
 #define LPI_OFFSET      8192
=20
+#ifdef CONFIG_GICV3_ESPI
+#define ESPI_BASE_INTID 4096
+#define ESPI_MAX_INTID  5119
+#define NR_ESPI_IRQS    1024
+
+#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
+#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
+#endif
+
 /* LPIs are always numbered starting at 8192, so 0 is a good invalid case.=
 */
 #define INVALID_LPI     0
=20
@@ -39,7 +48,15 @@ struct arch_irq_desc {
 #define INVALID_IRQ     1023
=20
 extern const unsigned int nr_irqs;
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * This will also cover the eSPI range, as some critical devices
+ * for booting Xen (e.g., serial) may use this type of interrupts.
+ */
+#define nr_static_irqs (ESPI_MAX_INTID + 1)
+#else
 #define nr_static_irqs NR_IRQS
+#endif
=20
 struct irq_desc;
 struct irqaction;
@@ -55,6 +72,15 @@ static inline bool is_lpi(unsigned int irq)
     return irq >=3D LPI_OFFSET;
 }
=20
+static inline bool is_espi(unsigned int irq)
+{
+#ifdef CONFIG_GICV3_ESPI
+    return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID);
+#else
+    return false;
+#endif
+}
+
 #define domain_pirq_to_irq(d, pirq) (pirq)
=20
 bool is_assignable_irq(unsigned int irq);
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index b8eccfc924..adb5e49ea3 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -19,7 +19,11 @@
 #include 
 #include 
=20
+#ifdef CONFIG_GICV3_ESPI
+const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1;
+#else
 const unsigned int nr_irqs =3D NR_IRQS;
+#endif
=20
 static unsigned int local_irqs_type[NR_LOCAL_IRQS];
 static DEFINE_SPINLOCK(local_irqs_type_lock);
@@ -46,6 +50,49 @@ void irq_end_none(struct irq_desc *irq)
 }
=20
 static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
+#ifdef CONFIG_GICV3_ESPI
+static irq_desc_t espi_desc[NR_ESPI_IRQS];
+
+static struct irq_desc *espi_to_desc(unsigned int irq)
+{
+    return &espi_desc[ESPI_INTID2IDX(irq)];
+}
+
+static int __init init_espi_data(void)
+{
+    int irq;
+
+    for ( irq =3D ESPI_BASE_INTID; irq <=3D ESPI_MAX_INTID; irq++ )
+    {
+        struct irq_desc *desc =3D irq_to_desc(irq);
+        int rc =3D init_one_irq_desc(desc);
+
+        if ( rc )
+            return rc;
+
+        desc->irq =3D irq;
+        desc->action  =3D NULL;
+    }
+
+    return 0;
+}
+#else
+/*
+ * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn,
+ * because in this case, is_espi will always return false.
+ */
+static struct irq_desc *espi_to_desc(unsigned int irq)
+{
+    ASSERT_UNREACHABLE();
+    return NULL;
+}
+
+static int __init init_espi_data(void)
+{
+    return 0;
+}
+#endif
+
 static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc);
=20
 struct irq_desc *__irq_to_desc(unsigned int irq)
@@ -53,6 +100,9 @@ struct irq_desc *__irq_to_desc(unsigned int irq)
     if ( irq < NR_LOCAL_IRQS )
         return &this_cpu(local_irq_desc)[irq];
=20
+    if ( is_espi(irq) )
+        return espi_to_desc(irq);
+
     return &irq_desc[irq-NR_LOCAL_IRQS];
 }
=20
@@ -79,7 +129,7 @@ static int __init init_irq_data(void)
         desc->action  =3D NULL;
     }
=20
-    return 0;
+    return init_espi_data();
 }
=20
 static int init_local_irq_data(unsigned int cpu)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk 
Subject: [PATCH v4 05/12] xen/arm: gicv3: implement handling of GICv3.1 eSPI
Thread-Topic: [PATCH v4 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcF3/KB15KvpnNkEu7nU8vywEQ/Q==
Date: Wed, 27 Aug 2025 18:24:13 +0000
Message-ID:
 <864522724dd6058952cad8b505b0589750b7f8d7.1756317702.git.leonid_komarianskyi@epam.com>
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Introduced appropriate register definitions, helper macros,
and initialization of required GICv3.1 distributor registers
to support eSPI. This type of interrupt is handled in the
same way as regular SPI interrupts, with the following
differences:

1) eSPIs can have up to 1024 interrupts, starting from the
beginning of the range, whereas regular SPIs use INTIDs from
32 to 1019, totaling 988 interrupts;
2) eSPIs start at INTID 4096, necessitating additional interrupt
index conversion during register operations.

In case if appropriate config is disabled, or GIC HW doesn't
support eSPI, the existing functionality will remain the same.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 

---
Changes in V4:
- added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
  for vGIC emulation
- added a log banner with eSPI information, similar to the one for
  regular SPI
- added newline after ifdef and before gic_is_valid_line
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- add __init attribute to gicv3_dist_espi_common_init
- change open-codded eSPI register initialization to the appropriate
  gen-mask macro
- fixed formatting for lines with more than 80 symbols
- introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
  CONFIG_GICV3_ESPI disabled
- renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
  (name was taken from GIC specification) to avoid confusion
- changed type for i variable to unsigned int since it cannot be
  negative

Changes in V2:
- move gic_number_espis function from
  [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
  to use it in the newly introduced gic_is_valid_espi
- add gic_is_valid_espi which checks if IRQ number is in supported
  by HW eSPI range
- update gic_is_valid_irq conditions to allow operations with eSPIs

Changes for V4:

Changes in V4:
- added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
  for vGIC emulation
- added newline after ifdef and before gic_is_valid_line
- added reviewed-by from Volodymyr Babchuk
- added a log banner with eSPI information, similar to the one for
  regular SPI
---
 xen/arch/arm/gic-v3.c                  | 82 ++++++++++++++++++++++++++
 xen/arch/arm/include/asm/gic.h         | 22 +++++++
 xen/arch/arm/include/asm/gic_v3_defs.h | 38 ++++++++++++
 3 files changed, 142 insertions(+)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index a959fefebe..b939a1f490 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_des=
c *irqd, u32 offset)
         default:
             break;
         }
+#ifdef CONFIG_GICV3_ESPI
+    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
+    {
+        u32 irq_index =3D ESPI_INTID2IDX(irqd->irq);
+
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
+        case GICD_ICENABLER:
+            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
+        case GICD_ISPENDR:
+            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
+        case GICD_ICPENDR:
+            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
+        case GICD_ISACTIVER:
+            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
+        case GICD_ICACTIVER:
+            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
+        case GICD_ICFGR:
+            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
+        case GICD_IROUTER:
+            return (GICD + GICD_IROUTERnE + irq_index * 8);
+        case GICD_IPRIORITYR:
+            return (GICD + GICD_IPRIORITYRnE + irq_index);
+        default:
+            break;
+        }
+    }
+#endif
     default:
         break;
     }
@@ -655,6 +685,54 @@ static void gicv3_set_irq_priority(struct irq_desc *de=
sc,
     spin_unlock(&gicv3.lock);
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+unsigned int gic_number_espis(void)
+{
+    return gic_hw_ops->info->nr_espi;
+}
+
+static void __init gicv3_dist_espi_common_init(uint32_t type)
+{
+    unsigned int espi_nr, i;
+
+    espi_nr =3D min(1024U, GICD_TYPER_ESPIS_NUM(type));
+    gicv3_info.nr_espi =3D espi_nr;
+    /* The GIC HW doesn't support eSPI, so we can leave from here */
+    if ( gicv3_info.nr_espi =3D=3D 0 )
+        return;
+
+    printk("GICv3: %d eSPI lines\n", gicv3_info.nr_espi);
+
+    for ( i =3D 0; i < espi_nr; i +=3D 16 )
+        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
+
+    for ( i =3D 0; i < espi_nr; i +=3D 4 )
+        writel_relaxed(GIC_PRI_IRQ_ALL,
+                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
+
+    for ( i =3D 0; i < espi_nr; i +=3D 32 )
+    {
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i / 32) =
* 4);
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i / 32) =
* 4);
+    }
+
+    for ( i =3D 0; i < espi_nr; i +=3D 32 )
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) * =
4);
+}
+
+static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
+{
+    unsigned int i;
+
+    for ( i =3D 0; i < gicv3_info.nr_espi; i++ )
+        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * 8)=
;
+}
+#else
+static void __init gicv3_dist_espi_common_init(uint32_t type) { }
+
+static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
+#endif
+
 static void __init gicv3_dist_init(void)
 {
     uint32_t type;
@@ -700,6 +778,8 @@ static void __init gicv3_dist_init(void)
     for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i +=3D 32 )
         writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4)=
;
=20
+    gicv3_dist_espi_common_init(type);
+
     gicv3_dist_wait_for_rwp();
=20
     /* Turn on the distributor */
@@ -713,6 +793,8 @@ static void __init gicv3_dist_init(void)
=20
     for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
         writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8);
+
+    gicv3_dist_espi_init_aff(affinity);
 }
=20
 static int gicv3_enable_redist(void)
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.=
h
index 3fcee42675..1e747dcd99 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -306,8 +306,26 @@ extern void gic_dump_vgic_info(struct vcpu *v);
=20
 /* Number of interrupt lines */
 extern unsigned int gic_number_lines(void);
+#ifdef CONFIG_GICV3_ESPI
+extern unsigned int gic_number_espis(void);
+
+static inline bool gic_is_valid_espi(unsigned int irq)
+{
+    return (irq >=3D ESPI_BASE_INTID &&
+            irq < ESPI_IDX2INTID(gic_number_espis()));
+}
+#else
+static inline bool gic_is_valid_espi(unsigned int irq)
+{
+    return false;
+}
+#endif
+
 static inline bool gic_is_valid_line(unsigned int irq)
 {
+    if ( gic_is_valid_espi(irq) )
+        return true;
+
     return irq < gic_number_lines();
 }
=20
@@ -325,6 +343,10 @@ struct gic_info {
     enum gic_version hw_version;
     /* Number of GIC lines supported */
     unsigned int nr_lines;
+#ifdef CONFIG_GICV3_ESPI
+    /* Number of GIC eSPI supported */
+    unsigned int nr_espi;
+#endif
     /* Number of LR registers */
     uint8_t nr_lrs;
     /* Maintenance irq number */
diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/=
asm/gic_v3_defs.h
index 2af093e774..c10db9bd05 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -37,6 +37,44 @@
 #define GICD_IROUTER1019             (0x7FD8)
 #define GICD_PIDR2                   (0xFFE8)
=20
+#ifdef CONFIG_GICV3_ESPI
+/* Additional registers for GICv3.1 */
+#define GICD_IGROUPRnE               (0x1000)
+#define GICD_IGROUPRnEN              (0x107C)
+#define GICD_ISENABLERnE             (0x1200)
+#define GICD_ISENABLERnEN            (0x127C)
+#define GICD_ICENABLERnE             (0x1400)
+#define GICD_ICENABLERnEN            (0x147C)
+#define GICD_ISPENDRnE               (0x1600)
+#define GICD_ISPENDRnEN              (0x167C)
+#define GICD_ICPENDRnE               (0x1800)
+#define GICD_ICPENDRnEN              (0x187C)
+#define GICD_ISACTIVERnE             (0x1A00)
+#define GICD_ISACTIVERnEN            (0x1A7C)
+#define GICD_ICACTIVERnE             (0x1C00)
+#define GICD_ICACTIVERnEN            (0x1C7C)
+#define GICD_IPRIORITYRnE            (0x2000)
+#define GICD_IPRIORITYRnEN           (0x23FC)
+#define GICD_ICFGRnE                 (0x3000)
+#define GICD_ICFGRnEN                (0x30FC)
+#define GICD_IGRPMODRnE              (0x3400)
+#define GICD_IGRPMODRnEN             (0x347C)
+#define GICD_NSACRnE                 (0x3600)
+#define GICD_NSACRnEN                (0x36FC)
+#define GICD_IROUTERnE               (0x8000)
+#define GICD_IROUTERnEN              (0x9FFC)
+
+#define GICD_TYPER_ESPI_SHIFT        8
+#define GICD_TYPER_ESPI_RANGE_SHIFT  27
+#define GICD_TYPER_ESPI_RANGE_MASK   (0x1F)
+#define GICD_TYPER_ESPI              (1U << GICD_TYPER_ESPI_SHIFT)
+#define GICD_TYPER_ESPI_RANGE(espi_range) ((((espi_range) & \
+        GICD_TYPER_ESPI_RANGE_MASK) + 1) * 32)
+#define GICD_TYPER_ESPIS_NUM(typer)    \
+        (((typer) & GICD_TYPER_ESPI) ? \
+        GICD_TYPER_ESPI_RANGE((typer) >> GICD_TYPER_ESPI_RANGE_SHIFT) : 0)
+#endif
+
 /* Common between GICD_PIDR2 and GICR_PIDR2 */
 #define GIC_PIDR2_ARCH_MASK         (0xf0)
 #define GIC_PIDR2_ARCH_GICv3        (0x30)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk 
Subject: [PATCH v4 06/12] xen/arm/irq: allow eSPI processing in the
 gic_interrupt function
Thread-Topic: [PATCH v4 06/12] xen/arm/irq: allow eSPI processing in the
 gic_interrupt function
Thread-Index: AQHcF3/Loedl2G5iukGvdwDJKvr6zw==
Date: Wed, 27 Aug 2025 18:24:16 +0000
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The gic_interrupt function is the main handler for processing IRQs.
Currently, due to restrictive checks, it does not process interrupt
numbers greater than 1019. This patch updates the condition to allow
the handling of interrupts from the eSPI range.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 

---
Changes in V4:
- fixed commit message
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- no changes

Changes in V2:
- no changes
---
 xen/arch/arm/gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index b88237ccda..634b77c987 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -341,7 +341,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_f=
iq)
         /* Reading IRQ will ACK it */
         irq =3D gic_hw_ops->read_irq();
=20
-        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) )
+        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) || is_espi(=
irq) )
         {
             isb();
             do_IRQ(regs, irq, is_fiq);
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk 
Subject: [PATCH v4 07/12] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow
 eSPI processing
Thread-Topic: [PATCH v4 07/12] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
 allow eSPI processing
Thread-Index: AQHcF3/M1ETcfpgi90idtTPd2WZvfg==
Date: Wed, 27 Aug 2025 18:24:18 +0000
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 <2252a686e800a9752cb22473c68236cb27734c26.1756317702.git.leonid_komarianskyi@epam.com>
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To properly deactivate guest interrupts and allow them to be retriggered
after the initial trigger, the LR needs to be updated. The current
implementation ignores interrupts outside the range specified by the mask
0x3FF, which only covers IRQ numbers up to 1023. To enable processing of
eSPI interrupts, this patch updates the mask to 0x13FF.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 

---
Changes in V4:
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- no changes

Changes in V2:
- remove unnecessary CONFIG_GICV3_ESPI ifdef guard
---
 xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/=
asm/gic_v3_defs.h
index c10db9bd05..eedb7af1fe 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -211,7 +211,7 @@
 #define ICH_LR_VIRTUAL_SHIFT         0
 #define ICH_LR_CPUID_MASK            0x7
 #define ICH_LR_CPUID_SHIFT           10
-#define ICH_LR_PHYSICAL_MASK         0x3ff
+#define ICH_LR_PHYSICAL_MASK         0x13ff
 #define ICH_LR_PHYSICAL_SHIFT        32
 #define ICH_LR_STATE_MASK            0x3
 #define ICH_LR_STATE_SHIFT           62
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v4 08/12] xen/arm: vgic: add resource management for extended
 SPIs
Thread-Topic: [PATCH v4 08/12] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcF3/NodAFMh424U2CquWmKsv0JA==
Date: Wed, 27 Aug 2025 18:24:19 +0000
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This change introduces resource management in the VGIC to handle
extended SPIs introduced in GICv3.1. The pending_irqs and
allocated_irqs arrays are resized to support the required
number of eSPIs, based on what is supported by the hardware and
requested by the guest. A new field, ext_shared_irqs, is added
to the VGIC structure to store information about eSPIs, similar
to how shared_irqs is used for regular SPIs.

Since the eSPI range starts at INTID 4096 and INTIDs between 1025
and 4095 are reserved, helper macros are introduced to simplify the
transformation of indices and to enable easier access to eSPI-specific
resources. These changes prepare the VGIC for processing eSPIs as
required by future functionality.

The initialization and deinitialization paths for vgic have been updated
to allocate and free these resources appropriately. Additionally,
updated handling of INTIDs greater than 1024, passed from the toolstack
during domain creation, and verification logic ensures only valid SPI or
eSPI INTIDs are used.

The existing SPI behavior remains unaffected when guests do not request
eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
option is disabled.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V4:
- added has_espi field to simplify determining whether a domain is able
  to operate with eSPI
- fixed formatting issues and misspellings

Changes in V3:
- fixed formatting for lines with more than 80 symbols
- introduced helper functions to be able to use stubs in case of
  CONFIG_GICV3_ESPI disabled, and as a result, reduce the number of
  #ifdefs
- fixed checks for nr_spis in domain_vgic_init
- updated comment about nr_spis adjustments with dom0less mention
- moved comment with additional explanations before checks
- used unsigned int for indexes since they cannot be negative
- removed unnecessary parentheses
- move vgic_ext_rank_offset to the below ifdef guard, to reduce the
  number of ifdefs

Changes in V2:
- change is_espi_rank to is_valid_espi_rank to verify whether the array
  element ext_shared_irqs exists. The previous version, is_espi_rank,
  only checked if the rank index was less than the maximum possible eSPI
  rank index, but this could potentially result in accessing a
  non-existing array element. To address this, is_valid_espi_rank was
  introduced, which ensures that the required eSPI rank exists
- move gic_number_espis to
  xen/arm: gicv3: implement handling of GICv3.1 eSPI
- update vgic_is_valid_irq checks to allow operating with eSPIs
- remove redundant newline in vgic_allocate_virq
---
 xen/arch/arm/include/asm/vgic.h |  20 +++
 xen/arch/arm/vgic.c             | 213 +++++++++++++++++++++++++++++++-
 2 files changed, 230 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 3e7cbbb196..fb4cea73eb 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -146,6 +146,12 @@ struct vgic_dist {
     int nr_spis; /* Number of SPIs */
     unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
     struct vgic_irq_rank *shared_irqs;
+#ifdef CONFIG_GICV3_ESPI
+    struct vgic_irq_rank *ext_shared_irqs;
+    int nr_espis; /* Number of extended SPIs */
+    /* To simplify determining whether a domain is able to operate with eS=
PI */
+    bool has_espi;
+#endif
     /*
      * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
      * struct arch_vcpu.
@@ -243,6 +249,14 @@ struct vgic_ops {
 /* Number of ranks of interrupt registers for a domain */
 #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
=20
+#ifdef CONFIG_GICV3_ESPI
+#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
+#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
+#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
+#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
+#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
+#endif
+
 #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
 #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
=20
@@ -302,6 +316,12 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct v=
cpu *v,
                                               unsigned int b,
                                               unsigned int n,
                                               unsigned int s);
+#ifdef CONFIG_GICV3_ESPI
+extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
+                                                  unsigned int b,
+                                                  unsigned int n,
+                                                  unsigned int s);
+#endif
 extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int ir=
q);
 extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
 extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 2bbf4d99aa..f4b80cb05f 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -27,9 +27,82 @@
=20
 bool vgic_is_valid_line(struct domain *d, unsigned int virq)
 {
+#ifdef CONFIG_GICV3_ESPI
+    if ( virq >=3D ESPI_BASE_INTID &&
+         virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
+        return true;
+#endif
+
     return virq < vgic_num_irqs(d);
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * Since eSPI indexes start from 4096 and numbers from 1024 to
+ * 4095 are forbidden, we need to check both lower and upper
+ * limits for ranks.
+ */
+static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
+{
+    return rank >=3D EXT_RANK_MIN &&
+           EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d);
+}
+
+static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
+                                                       unsigned int rank)
+{
+    return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)];
+}
+
+static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int v=
irq)
+{
+    return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d),
+                             d->arch.vgic.allocated_irqs);
+}
+
+static void arch_move_espis(struct vcpu *v)
+{
+    const cpumask_t *cpu_mask =3D cpumask_of(v->processor);
+    struct domain *d =3D v->domain;
+    struct pending_irq *p;
+    struct vcpu *v_target;
+    unsigned int i;
+
+    for ( i =3D ESPI_BASE_INTID;
+          i < EXT_RANK_IDX2NUM(d->arch.vgic.nr_espis); i++ )
+    {
+        v_target =3D vgic_get_target_vcpu(v, i);
+        p =3D irq_to_pending(v_target, i);
+
+        if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->s=
tatus) )
+            irq_set_affinity(p->desc, cpu_mask);
+    }
+}
+#else
+static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
+{
+    return false;
+}
+
+/*
+ * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn,
+ * because in this case, is_valid_espi_rank will always return false.
+ */
+static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
+                                                       unsigned int rank)
+{
+    ASSERT_UNREACHABLE();
+    return NULL;
+}
+
+static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int v=
irq)
+{
+    return false;
+}
+
+static void arch_move_espis(struct vcpu *v) { }
+#endif
+
 static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
                                                   unsigned int rank)
 {
@@ -37,6 +110,8 @@ static inline struct vgic_irq_rank *vgic_get_rank(struct=
 vcpu *v,
         return v->arch.vgic.private_irqs;
     else if ( rank <=3D DOMAIN_NR_RANKS(v->domain) )
         return &v->domain->arch.vgic.shared_irqs[rank - 1];
+    else if ( is_valid_espi_rank(v->domain, rank) )
+        return vgic_get_espi_rank(v, rank);
     else
         return NULL;
 }
@@ -117,6 +192,74 @@ int domain_vgic_register(struct domain *d, unsigned in=
t *mmio_count)
     return 0;
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * The function behavior is the same as for regular SPIs (vgic_rank_offset=
),
+ * but it operates with extended SPI ranks.
+ */
+struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int b,
+                                           unsigned int n, unsigned int s)
+{
+    unsigned int rank =3D REG_RANK_NR(b, (n >> s));
+
+    return vgic_get_rank(v, rank + EXT_RANK_MIN);
+}
+
+static unsigned int vgic_num_spi_lines(struct domain *d)
+{
+    return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
+}
+
+static int init_vgic_espi(struct domain *d)
+{
+    unsigned int i, idx;
+
+    if ( d->arch.vgic.nr_espis =3D=3D 0 )
+        return 0;
+
+    d->arch.vgic.ext_shared_irqs =3D
+        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
+    if ( d->arch.vgic.ext_shared_irqs =3D=3D NULL )
+        return -ENOMEM;
+
+    for ( i =3D d->arch.vgic.nr_spis, idx =3D 0;
+          i < vgic_num_spi_lines(d); i++, idx++ )
+        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i],
+                              ESPI_IDX2INTID(idx));
+
+    for ( i =3D 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
+        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
+
+    return 0;
+}
+
+struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
+{
+    irq =3D ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
+    return &d->arch.vgic.pending_irqs[irq];
+}
+#else
+static unsigned int init_vgic_espi(struct domain *d)
+{
+    return 0;
+}
+
+static unsigned int vgic_num_spi_lines(struct domain *d)
+{
+    return d->arch.vgic.nr_spis;
+}
+
+struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
+{
+    return NULL;
+}
+#endif
+
+static unsigned int vgic_num_alloc_irqs(struct domain *d)
+{
+    return vgic_num_spi_lines(d) + NR_LOCAL_IRQS;
+}
+
 int domain_vgic_init(struct domain *d, unsigned int nr_spis)
 {
     int i;
@@ -131,6 +274,38 @@ int domain_vgic_init(struct domain *d, unsigned int nr=
_spis)
      */
     nr_spis =3D ROUNDUP(nr_spis, 32);
=20
+#ifdef CONFIG_GICV3_ESPI
+    /*
+     * During domain creation, the dom0less DomUs code or toolstack specif=
ies
+     * the maximum INTID, which is defined in the domain config subtracted=
 by
+     * 32 to cover the local IRQs (please see the comment to VGIC_DEF_NR_S=
PIS).
+     * To compute the actual number of eSPI that will be usable for,
+     * add back 32.
+     */
+    if ( nr_spis + 32 > ESPI_IDX2INTID(NR_ESPI_IRQS) )
+        return -EINVAL;
+
+    if ( nr_spis + 32 >=3D ESPI_BASE_INTID )
+    {
+        d->arch.vgic.nr_espis =3D min(nr_spis - ESPI_BASE_INTID + 32, 1024=
U);
+        /* Verify if GIC HW can handle provided INTID */
+        if ( d->arch.vgic.nr_espis > gic_number_espis() )
+            return -EINVAL;
+        /*
+         * Set the maximum available number for regular
+         * SPI to pass the next check
+         */
+        nr_spis =3D VGIC_DEF_NR_SPIS;
+        d->arch.vgic.has_espi =3D true;
+    }
+    else
+    {
+        /* Domain will use the regular SPI range */
+        d->arch.vgic.nr_espis =3D 0;
+        d->arch.vgic.has_espi =3D false;
+    }
+#endif
+
     /* Limit the number of virtual SPIs supported to (1020 - 32) =3D 988  =
*/
     if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
         return -EINVAL;
@@ -145,7 +320,7 @@ int domain_vgic_init(struct domain *d, unsigned int nr_=
spis)
         return -ENOMEM;
=20
     d->arch.vgic.pending_irqs =3D
-        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
+        xzalloc_array(struct pending_irq, vgic_num_spi_lines(d));
     if ( d->arch.vgic.pending_irqs =3D=3D NULL )
         return -ENOMEM;
=20
@@ -156,12 +331,16 @@ int domain_vgic_init(struct domain *d, unsigned int n=
r_spis)
     for ( i =3D 0; i < DOMAIN_NR_RANKS(d); i++ )
         vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
=20
+    ret =3D init_vgic_espi(d);
+    if ( ret )
+        return ret;
+
     ret =3D d->arch.vgic.handler->domain_init(d);
     if ( ret )
         return ret;
=20
     d->arch.vgic.allocated_irqs =3D
-        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
+        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_alloc_irqs(d))=
);
     if ( !d->arch.vgic.allocated_irqs )
         return -ENOMEM;
=20
@@ -195,9 +374,27 @@ void domain_vgic_free(struct domain *d)
         }
     }
=20
+#ifdef CONFIG_GICV3_ESPI
+    for ( i =3D 0; i < d->arch.vgic.nr_espis; i++ )
+    {
+        struct pending_irq *p =3D spi_to_pending(d, ESPI_IDX2INTID(i));
+
+        if ( p->desc )
+        {
+            ret =3D release_guest_irq(d, p->irq);
+            if ( ret )
+                dprintk(XENLOG_G_WARNING, "d%u: Failed to release virq %u =
ret =3D %d\n",
+                        d->domain_id, p->irq, ret);
+        }
+    }
+#endif
+
     if ( d->arch.vgic.handler )
         d->arch.vgic.handler->domain_free(d);
     xfree(d->arch.vgic.shared_irqs);
+#ifdef CONFIG_GICV3_ESPI
+    xfree(d->arch.vgic.ext_shared_irqs);
+#endif
     xfree(d->arch.vgic.pending_irqs);
     xfree(d->arch.vgic.allocated_irqs);
 }
@@ -331,6 +528,8 @@ void arch_move_irqs(struct vcpu *v)
         if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->s=
tatus) )
             irq_set_affinity(p->desc, cpu_mask);
     }
+
+    arch_move_espis(v);
 }
=20
 void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
@@ -538,6 +737,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v, unsi=
gned int irq)
         n =3D &v->arch.vgic.pending_irqs[irq];
     else if ( is_lpi(irq) )
         n =3D v->domain->arch.vgic.handler->lpi_to_pending(v->domain, irq)=
;
+    else if ( is_espi(irq) )
+        n =3D espi_to_pending(v->domain, irq);
     else
         n =3D &v->domain->arch.vgic.pending_irqs[irq - 32];
     return n;
@@ -547,6 +748,9 @@ struct pending_irq *spi_to_pending(struct domain *d, un=
signed int irq)
 {
     ASSERT(irq >=3D NR_LOCAL_IRQS);
=20
+    if ( is_espi(irq) )
+        return espi_to_pending(d, irq);
+
     return &d->arch.vgic.pending_irqs[irq - 32];
 }
=20
@@ -668,6 +872,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned int v=
irq)
     if ( !vgic_is_valid_line(d, virq) )
         return false;
=20
+    if ( is_espi(virq) )
+        return vgic_reserve_espi_virq(d, virq);
+
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
 }
=20
@@ -685,7 +892,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
     else
     {
         first =3D 32;
-        end =3D vgic_num_irqs(d);
+        end =3D vgic_num_alloc_irqs(d);
     }
=20
     /*
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v4 09/12] xen/arm: domain_build/dom0less-build: adjust domains
 config to support eSPIs
Thread-Topic: [PATCH v4 09/12] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Index: AQHcF3/Ont2iCNudZU+HGYrvI6u3EQ==
Date: Wed, 27 Aug 2025 18:24:21 +0000
Message-ID:
 <66b39c4ba25e7a19beeca62ab23f5d3ab3cbae52.1756317702.git.leonid_komarianskyi@epam.com>
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The Dom0 and DomUs logic for the dom0less configuration in create_dom0() an=
d
arch_create_domUs() has been updated to account for extended SPIs when
supported by the hardware and enabled with CONFIG_GICV3_ESPI. These changes
ensure the proper calculation of the maximum number of SPIs and eSPIs avail=
able
to Dom0 and DomUs in dom0less setups.

When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is enabled, =
the
maximum number of eSPI interrupts is calculated using the ESPI_BASE_INTID
offset (4096) and is limited to 1024, with 32 IRQs subtracted. To ensure
compatibility with non-Dom0 domains, this adjustment is applied by the
toolstack during domain creation, while for Dom0 or DomUs in Dom0, it is
handled directly during VGIC initialization. If eSPIs are not supported, th=
e
calculation defaults to using the standard SPI range, with a maximum value =
of
992 interrupt lines, as it works currently.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V4:
- consolidated the eSPI and SPI logic into a new inline function,
  vgic_def_nr_spis. Without eSPI support (either due to config being
  disabled or hardware not supporting it), it will return the regular SPI
  range, as it works currently. There are no functional changes compared
  with the previous patch version
- removed VGIC_DEF_MAX_SPI macro, to reduce the number of ifdefs

Changes in V3:
- renamed macro VGIC_DEF_NR_ESPIS to more appropriate VGIC_DEF_MAX_SPI
- added eSPI initialization for dom0less setups
- fixed comment with mentions about dom0less builds
- fixed formatting for lines with more than 80 symbols
- updated commit message

Changes in V2:
- no changes
---
 xen/arch/arm/dom0less-build.c   |  2 +-
 xen/arch/arm/domain_build.c     |  2 +-
 xen/arch/arm/include/asm/vgic.h | 21 +++++++++++++++++++++
 3 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 69b9ea22ce..02d5559102 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -285,7 +285,7 @@ void __init arch_create_domUs(struct dt_device_node *no=
de,
     {
         int vpl011_virq =3D GUEST_VPL011_SPI;
=20
-        d_cfg->arch.nr_spis =3D VGIC_DEF_NR_SPIS;
+        d_cfg->arch.nr_spis =3D vgic_def_nr_spis();
=20
         /*
          * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index d91a71acfd..39eea0be00 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2054,7 +2054,7 @@ void __init create_dom0(void)
=20
     /* The vGIC for DOM0 is exactly emulating the hardware GIC */
     dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
-    dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS;
+    dom0_cfg.arch.nr_spis =3D vgic_def_nr_spis();
     dom0_cfg.arch.tee_type =3D tee_get_type();
     dom0_cfg.max_vcpus =3D dom0_max_vcpus();
=20
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index fb4cea73eb..11f9d216eb 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -355,6 +355,27 @@ extern void vgic_check_inflight_irqs_pending(struct vc=
pu *v,
 /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
 #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
=20
+static inline unsigned int vgic_def_nr_spis(void)
+{
+#ifdef CONFIG_GICV3_ESPI
+    /*
+     * Check if the hardware supports extended SPIs (even if the appropria=
te
+     * config is set). If not, the common SPI range will be used. Otherwis=
e
+     * returns the maximum eSPI INTID, supported by HW GIC, subtracted by =
32.
+     * For non-Dom0 domains, the toolstack or arch_create_domUs function
+     * applies the same adjustment to cover local IRQs (please, see commen=
t
+     * for macro that is used for regular SPIs - VGIC_DEF_NR_SPIS). We wil=
l
+     * add back this value during VGIC initialization. This ensures consis=
tent
+     * handling for Dom0 and other domains. For the regular SPI range inte=
rrupts
+     * in this case, the maximum value of VGIC_DEF_NR_SPIS will be used.
+     */
+    if ( gic_number_espis() > 0 )
+        return ESPI_BASE_INTID + min(gic_number_espis(), 1024U) - 32;
+#endif
+
+    return VGIC_DEF_NR_SPIS;
+}
+
 extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
=20
 static inline bool vgic_is_spi(struct domain *d, unsigned int virq)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v4 10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v4 10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Index: AQHcF3/PMGQJ9ZKjmEOWPrVRdE59HQ==
Date: Wed, 27 Aug 2025 18:24:22 +0000
Message-ID:
 <6b312e1997da5abdf592f66d16067f4330431ded.1756317702.git.leonid_komarianskyi@epam.com>
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Implemented support for GICv3.1 extended SPI registers for vGICv3,
allowing the emulation of eSPI-specific behavior for guest domains.
The implementation includes read and write emulation for eSPI-related
registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
following a similar approach to the handling of regular SPIs.

The eSPI registers, previously located in reserved address ranges,
are now adjusted to support MMIO read and write operations correctly
when CONFIG_GICV3_ESPI is enabled.

The availability of eSPIs and the number of emulated extended SPIs
for guest domains is reported by setting the appropriate bits in the
GICD_TYPER register, based on the number of eSPIs requested by the
domain and supported by the hardware. In cases where the configuration
option is disabled, the hardware does not support eSPIs, or the domain
does not request such interrupts, the functionality remains unchanged.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V4:
- added missing RAZ and write ignore eSPI-specific registers ranges:
  GICD_NSACRnE and GICD_IGRPMODRnE
- changed previously reserved range to cover GICD_NSACRnE and
  GICD_IGRPMODRnE
- introduced GICD_RESERVED_RANGE_START/END defines to remove
  hardcoded values and reduce the number of ifdefs
- fixed reserved ranges with eSPI option enabled: added missing range
  0x0F30-0x0F7C
- updated the logic for domains that do not support eSPI, but Xen is
  compiled with the eSPI option. Now, prior to other MMIO checks, we
  verify whether eSPI is available for the domain or not. If not, it
  behaves as it does currently - RAZ and WI
- fixed print for GICD_ICACTIVERnE
- fixed new lines formatting for switch-case

Changes in V3:
- changed vgic_store_irouter parameters - instead of offset virq is
  used, to remove the additional bool espi parameter and simplify
  checks. Also, adjusted parameters for regular SPI. Since the offset
  parameter was used only for calculating virq number and then reused for
  finding rank offset, it will not affect functionality.
- fixed formatting for goto lables - added newlines after condition
- fixed logs for GICD_ISACTIVERnE and GICD_ICACTIVERnE handlers
- removed #ifdefs in 2 places where they were adjacent and could be merged

Changes in V2:
- add missing rank index conversion for pending and inflight irqs
---
 xen/arch/arm/vgic-v3.c | 333 +++++++++++++++++++++++++++++++++++++++--
 1 file changed, 319 insertions(+), 14 deletions(-)

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 4369c55177..ca19f24634 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -42,6 +42,36 @@
  */
 #define VGICD_CTLR_DEFAULT  (GICD_CTLR_ARE_NS)
=20
+/*
+ * Common start and end of reserved ranges for
+ * both eSPI and non-eSPI builds
+ */
+#define GICD_RESERVED_RANGE1_START (0x0F30)
+#define GICD_RESERVED_RANGE2_END   (0xBFFC)
+
+#ifdef CONFIG_GICV3_ESPI
+
+#define GICD_RESERVED_RANGE1_END   (0x0F7C)
+
+#define GICD_RESERVED_RANGE2_START (0xA004)
+
+/*
+ * In case eSPI is enabled, there is an additional
+ * reserved range after the eSPI-specific registers
+ */
+#define GICD_RESERVED_RANGE3_START (0x3700)
+#define GICD_RESERVED_RANGE3_END   (0x60FC)
+#else
+
+/*
+ * In case eSPI is disabled, the range with eSPI-specific
+ * registers is marked as reserved
+ */
+#define GICD_RESERVED_RANGE1_END   (0x60FC)
+
+#define GICD_RESERVED_RANGE2_START (0x7FE0)
+#endif
+
 static struct {
     bool enabled;
     /* Distributor interface address */
@@ -111,13 +141,10 @@ static uint64_t vgic_fetch_irouter(struct vgic_irq_ra=
nk *rank,
  * Note the offset will be aligned to the appropriate boundary.
  */
 static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *ran=
k,
-                               unsigned int offset, uint64_t irouter)
+                               unsigned int virq, uint64_t irouter)
 {
     struct vcpu *new_vcpu, *old_vcpu;
-    unsigned int virq;
-
-    /* There is 1 vIRQ per IROUTER */
-    virq =3D offset / NR_BYTES_PER_IROUTER;
+    unsigned int offset;
=20
     /*
      * The IROUTER0-31, used for SGIs/PPIs, are reserved and should
@@ -685,6 +712,10 @@ static int __vgic_v3_distr_common_mmio_read(const char=
 *name, struct vcpu *v,
     {
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
+#endif
         /* We do not implement security extensions for guests, read zero *=
/
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
         goto read_as_zero;
@@ -710,11 +741,19 @@ static int __vgic_v3_distr_common_mmio_read(const cha=
r *name, struct vcpu *v,
     /* Read the pending status of an IRQ via GICD/GICR is not supported */
     case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
     case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+#endif
         goto read_as_zero;
=20
     /* Read the active status of an IRQ via GICD/GICR is not supported */
     case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
     case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+#endif
         goto read_as_zero;
=20
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
@@ -752,6 +791,69 @@ static int __vgic_v3_distr_common_mmio_read(const char=
 *name, struct vcpu *v,
         return 1;
     }
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        *r =3D vreg_reg32_extract(rank->ienable, info);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        *r =3D vreg_reg32_extract(rank->ienable, info);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    {
+        uint32_t ipriorityr;
+        uint8_t rank_index;
+
+        if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DABT_=
WORD);
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        rank_index =3D REG_RANK_INDEX(8, reg - GICD_IPRIORITYRnE, DABT_WOR=
D);
+
+        vgic_lock_rank(v, rank, flags);
+        ipriorityr =3D ACCESS_ONCE(rank->ipriorityr[rank_index]);
+        vgic_unlock_rank(v, rank, flags);
+
+        *r =3D vreg_reg32_extract(ipriorityr, info);
+
+        return 1;
+    }
+
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+    {
+        uint32_t icfgr;
+
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WORD)=
;
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        icfgr =3D rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE, DABT_WO=
RD)];
+        vgic_unlock_rank(v, rank, flags);
+
+        *r =3D vreg_reg32_extract(icfgr, info);
+
+        return 1;
+    }
+#endif
+
     default:
         printk(XENLOG_G_ERR
                "%pv: %s: unhandled read r%d offset %#08x\n",
@@ -782,6 +884,10 @@ static int __vgic_v3_distr_common_mmio_write(const cha=
r *name, struct vcpu *v,
     {
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
+#endif
         /* We do not implement security extensions for guests, write ignor=
e */
         goto write_ignore_32;
=20
@@ -871,6 +977,102 @@ static int __vgic_v3_distr_common_mmio_write(const ch=
ar *name, struct vcpu *v,
         vgic_unlock_rank(v, rank, flags);
         return 1;
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        tr =3D rank->ienable;
+        vreg_reg32_setbits(&rank->ienable, r, info);
+        vgic_enable_irqs(v, (rank->ienable) & (~tr), EXT_RANK_IDX2NUM(rank=
->index));
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE, DABT_W=
ORD);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        tr =3D rank->ienable;
+        vreg_reg32_clearbits(&rank->ienable, r, info);
+        vgic_disable_irqs(v, (~rank->ienable) & tr, EXT_RANK_IDX2NUM(rank-=
>index));
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISPENDRnE, DABT_WOR=
D);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+
+        vgic_set_irqs_pending(v, r, EXT_RANK_IDX2NUM(rank->index));
+
+        return 1;
+
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICPENDRnE, DABT_WOR=
D);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+
+        vgic_check_inflight_irqs_pending(v, EXT_RANK_IDX2NUM(rank->index),=
 r);
+
+        goto write_ignore;
+
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        printk(XENLOG_G_ERR
+               "%pv: %s: unhandled word write %#"PRIregister" to ISACTIVER=
%dE\n",
+               v, name, r, reg - GICD_ISACTIVERnE);
+        return 0;
+
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+        printk(XENLOG_G_ERR
+               "%pv: %s: unhandled word write %#"PRIregister" to ICACTIVER=
%dE\n",
+               v, name, r, reg - GICD_ICACTIVERnE);
+        goto write_ignore_32;
+
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    {
+        uint32_t *ipriorityr, priority;
+
+        if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE, DABT_=
WORD);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        ipriorityr =3D &rank->ipriorityr[REG_RANK_INDEX(8, reg - GICD_IPRI=
ORITYRnE,
+                                                      DABT_WORD)];
+        priority =3D ACCESS_ONCE(*ipriorityr);
+        vreg_reg32_update(&priority, r, info);
+        ACCESS_ONCE(*ipriorityr) =3D priority;
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+    }
+
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_WORD)=
;
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGRnE=
,
+                                                     DABT_WORD)],
+                          r, info);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+#endif
+
     default:
         printk(XENLOG_G_ERR
                "%pv: %s: unhandled write r%d=3D%"PRIregister" offset %#08x=
\n",
@@ -1129,6 +1331,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
             typer |=3D GICD_TYPE_LPIS;
=20
         typer |=3D (v->domain->arch.vgic.intid_bits - 1) << GICD_TYPE_ID_B=
ITS_SHIFT;
+#ifdef CONFIG_GICV3_ESPI
+        if ( v->domain->arch.vgic.has_espi )
+        {
+            /* Set eSPI support bit for the domain */
+            typer |=3D GICD_TYPER_ESPI;
+            /* Set ESPI range bits */
+            typer |=3D (DIV_ROUND_UP(v->domain->arch.vgic.nr_espis, 32) - =
1)
+                       << GICD_TYPER_ESPI_RANGE_SHIFT;
+        }
+#endif
=20
         *r =3D vreg_reg32_extract(typer, info);
=20
@@ -1184,6 +1396,21 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
     case VRANGE32(0x005C, 0x007C):
         goto read_reserved;
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
+        if ( !v->domain->arch.vgic.has_espi )
+            goto read_reserved;
+        return __vgic_v3_distr_common_mmio_read("vGICD", v, info, gicd_reg=
, r);
+#endif
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN):
     case VRANGE32(GICD_ICENABLER, GICD_ICENABLERN):
@@ -1200,6 +1427,11 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
          */
         return __vgic_v3_distr_common_mmio_read("vGICD", v, info, gicd_reg=
, r);
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_NSACRnE, GICD_NSACRnEN):
+        if ( !v->domain->arch.vgic.has_espi )
+            goto read_reserved;
+#endif
     case VRANGE32(GICD_NSACR, GICD_NSACRN):
         /* We do not implement security extensions for guests, read zero *=
/
         goto read_as_zero_32;
@@ -1216,7 +1448,7 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mm=
io_info_t *info,
         /* Replaced with GICR_ISPENDR0. So ignore write */
         goto read_as_zero_32;
=20
-    case VRANGE32(0x0F30, 0x60FC):
+    case VRANGE32(GICD_RESERVED_RANGE1_START, GICD_RESERVED_RANGE1_END):
         goto read_reserved;
=20
     case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
@@ -1235,8 +1467,32 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
=20
         return 1;
     }
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
+    {
+        uint64_t irouter;
=20
-    case VRANGE32(0x7FE0, 0xBFFC):
+        if ( !v->domain->arch.vgic.has_espi )
+            goto read_reserved;
+
+        if ( !vgic_reg64_check_access(dabt) )
+            goto bad_width;
+        rank =3D vgic_ext_rank_offset(v, 64, gicd_reg - GICD_IROUTERnE,
+                                DABT_DOUBLE_WORD);
+        if ( rank =3D=3D NULL )
+            goto read_as_zero;
+        vgic_lock_rank(v, rank, flags);
+        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTERnE);
+        vgic_unlock_rank(v, rank, flags);
+
+        *r =3D vreg_reg64_extract(irouter, info);
+
+        return 1;
+    }
+
+    case VRANGE32(GICD_RESERVED_RANGE3_START, GICD_RESERVED_RANGE3_END):
+#endif
+    case VRANGE32(GICD_RESERVED_RANGE2_START, GICD_RESERVED_RANGE2_END):
         goto read_reserved;
=20
     case VRANGE32(0xC000, 0xFFCC):
@@ -1372,6 +1628,23 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, =
mmio_info_t *info,
     case VRANGE32(0x005C, 0x007C):
         goto write_reserved;
=20
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
+        if ( !v->domain->arch.vgic.has_espi )
+            goto write_reserved;
+        return __vgic_v3_distr_common_mmio_write("vGICD", v, info,
+                                                 gicd_reg, r);
+#endif
+
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN):
     case VRANGE32(GICD_ICENABLER, GICD_ICENABLERN):
@@ -1386,7 +1659,11 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v, =
mmio_info_t *info,
          * Manage in common */
         return __vgic_v3_distr_common_mmio_write("vGICD", v, info,
                                                  gicd_reg, r);
-
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE32(GICD_NSACRnE, GICD_NSACRnEN):
+        if ( !v->domain->arch.vgic.has_espi )
+            goto write_reserved;
+#endif
     case VRANGE32(GICD_NSACR, GICD_NSACRN):
         /* We do not implement security extensions for guests, write ignor=
e */
         goto write_ignore_32;
@@ -1405,26 +1682,54 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v,=
 mmio_info_t *info,
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
         return 0;
=20
-    case VRANGE32(0x0F30, 0x60FC):
+    case VRANGE32(GICD_RESERVED_RANGE1_START, GICD_RESERVED_RANGE1_END):
         goto write_reserved;
=20
     case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
     {
         uint64_t irouter;
+        unsigned int offset, virq;
=20
         if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
-                                DABT_DOUBLE_WORD);
+        offset =3D gicd_reg - GICD_IROUTER;
+        rank =3D vgic_rank_offset(v, 64, offset, DABT_DOUBLE_WORD);
         if ( rank =3D=3D NULL ) goto write_ignore;
         vgic_lock_rank(v, rank, flags);
-        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTER);
+        irouter =3D vgic_fetch_irouter(rank, offset);
         vreg_reg64_update(&irouter, r, info);
-        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTER, irout=
er);
+        virq =3D offset / NR_BYTES_PER_IROUTER;
+        vgic_store_irouter(v->domain, rank, virq, irouter);
         vgic_unlock_rank(v, rank, flags);
         return 1;
     }
=20
-    case VRANGE32(0x7FE0, 0xBFFC):
+#ifdef CONFIG_GICV3_ESPI
+    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
+    {
+        uint64_t irouter;
+        unsigned int offset, virq;
+
+        if ( !v->domain->arch.vgic.has_espi )
+            goto write_reserved;
+
+        if ( !vgic_reg64_check_access(dabt) )
+            goto bad_width;
+        offset =3D gicd_reg - GICD_IROUTERnE;
+        rank =3D vgic_ext_rank_offset(v, 64, offset, DABT_DOUBLE_WORD);
+        if ( rank =3D=3D NULL )
+            goto write_ignore;
+        vgic_lock_rank(v, rank, flags);
+        irouter =3D vgic_fetch_irouter(rank, offset);
+        vreg_reg64_update(&irouter, r, info);
+        virq =3D ESPI_IDX2INTID(offset / NR_BYTES_PER_IROUTER);
+        vgic_store_irouter(v->domain, rank, virq, irouter);
+        vgic_unlock_rank(v, rank, flags);
+        return 1;
+    }
+
+    case VRANGE32(GICD_RESERVED_RANGE3_START, GICD_RESERVED_RANGE3_END):
+#endif
+    case VRANGE32(GICD_RESERVED_RANGE2_START, GICD_RESERVED_RANGE2_END):
         goto write_reserved;
=20
     case VRANGE32(0xC000, 0xFFCC):
--=20
2.34.1


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To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Oleksii Kurochko
	, Community Manager
	
Subject: [PATCH v4 12/12] CHANGELOG.md: add mention of GICv3.1 eSPI support
Thread-Topic: [PATCH v4 12/12] CHANGELOG.md: add mention of GICv3.1 eSPI
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The GICv3.1 eSPI (Extended Shared Peripheral Interrupts) range is
already supported with CONFIG_GICV3_ESPI enabled, so this feature should
be mentioned in CHANGELOG.md.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V3:
- introduced this patch
---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe..dc34d29d99 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -29,6 +29,7 @@ The format is based on [Keep a Changelog](https://keepach=
angelog.com/en/1.0.0/)
=20
  - On Arm:
     - Ability to enable stack protector
+    - GICv3.1 eSPI support
=20
 ### Removed
  - On x86:
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Anthony PERARD 
Subject: [PATCH v4 11/12] doc/man: update description for nr_spis with eSPI
Thread-Topic: [PATCH v4 11/12] doc/man: update description for nr_spis with
 eSPI
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Date: Wed, 27 Aug 2025 18:24:24 +0000
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Since eSPI support has been introduced, update the documentation with
the appropriate description.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V4:
- introduced this patch
---
 docs/man/xl.cfg.5.pod.in | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
index 5362fb0e9a..292ab10331 100644
--- a/docs/man/xl.cfg.5.pod.in
+++ b/docs/man/xl.cfg.5.pod.in
@@ -3072,11 +3072,14 @@ interval of colors (such as "0-4").
 =3Ditem B
=20
 An optional integer parameter specifying the number of SPIs (Shared
-Peripheral Interrupts) to allocate for the domain. Max is 960 SPIs. If
-the `nr_spis` parameter is not specified, the value calculated by the tool=
stack
-will be used for the domain. Otherwise, the value specified by the `nr_spi=
s`
-parameter will be used. The number of SPIs should match the highest interr=
upt
-ID that will be assigned to the domain.
+Peripheral Interrupts) to allocate for the domain. Max is 960 for regular =
SPIs
+or 5088 for eSPIs (Extended SPIs). The eSPIs includes an additional 1024 S=
PIs
+from the eSPI range (4096 to 5119) if the hardware supports extended SPIs
+(GICv3.1+) and CONFIG_GICV3_ESPI is enabled. If the `nr_spis` parameter is=
 not
+specified, the value calculated by the toolstack will be used for the doma=
in.
+Otherwise, the value specified by the `nr_spis` parameter will be used. Th=
e
+number of SPIs should match the highest interrupt ID that will be assigned=
 to
+the domain.
=20
 =3Ditem B
=20
--=20
2.34.1


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Subject: Re: [RFC PATCH v5 09/10] xen/arm: scmi: introduce SCI SCMI SMC
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To: Oleksii Moisieiev ,
 "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Bertrand Marquis , Jan Beulich
 , Juergen Gross ,
 Julien Grall , Michal Orzel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Volodymyr Babchuk ,
 Grygorii Strashko 
References: 
 <9f4a137980a0ee72f0f03d55176ca178c4b90126.1753184487.git.oleksii_moisieiev@epam.com>
Content-Language: en-US
From: Oleksandr Tyshchenko 
In-Reply-To: <9f4a137980a0ee72f0f03d55176ca178c4b90126.1753184487.git.oleksii_moisieiev@epam.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit



On 22.07.25 14:41, Oleksii Moisieiev wrote:

Hello Oleksii

[I will try to not repeat comments provided by Stefano in separate letter]


> This patch introduces SCI driver to support for ARM EL3 Trusted Firmware-A
> (TF-A) which provides SCMI interface with multi-agnet support, as shown
> below.
> 
>    +-----------------------------------------+
>    |                                         |
>    | EL3 TF-A SCMI                           |
>    +-------+--+-------+--+-------+--+-------++
>    |shmem1 |  |shmem0 |  |shmem2 |  |shmemX |
>    +-----+-+  +---+---+  +--+----+  +---+---+
> smc-id1 |        |         |           |
> agent1  |        |         |           |
>    +-----v--------+---------+-----------+----+
>    |              |         |           |    |
>    |              |         |           |    |
>    +--------------+---------+-----------+----+
>           smc-id0 |  smc-id2|    smc-idX|
>           agent0  |  agent2 |    agentX |
>                   |         |           |
>              +----v---+  +--v-----+  +--v-----+
>              |        |  |        |  |        |
>              | Dom0   |  | Dom1   |  | DomX   |
>              |        |  |        |  |        |
>              |        |  |        |  |        |
>              +--------+  +--------+  +--------+
> 
> The EL3 SCMI multi-agent firmware expected to provide SCMI SMC/HVC shared
> memory transport for every Agent in the system.
> 
> The SCMI Agent transport channel defined by pair:
>   - smc-id: SMC/HVC id used for Doorbell
>   - shmem: shared memory for messages transfer, Xen page
>   aligned. Shared memort is mapped with the following flags:
>   MT_DEVICE_nGnRE.
> 
> The follwoing SCMI Agents expected to be defined by SCMI FW to enable SCMI
> multi-agent functionality under Xen:
> - Xen manegement agent: trusted agents that accesses to the Base Protocol
> commands to configure agent specific permissions
> - OSPM VM agents: non-trusted agent, one for each Guest domain which is
>    allowed direct HW access. At least one OSPM VM agent has to be provided
>    by FW if HW is handled only by Dom0 or Driver Domain.
> 
> The EL3 SCMI FW expected to implement following Base protocol messages:
> - BASE_DISCOVER_AGENT (optional if agent_id was provided)
> - BASE_RESET_AGENT_CONFIGURATION (optional)
> - BASE_SET_DEVICE_PERMISSIONS (optional)
> 
> The SCI SCMI SMC multi-agent driver implements following
> functionality:
> - The driver is initialized based on the ``xen,config`` node under ``chosen``
>    (only one SCMI interface is supported), which describes the Xen management
>    agent SCMI interface.
> 
> scmi_shm_1: sram@47ff1000 {
>            compatible = "arm,scmi-shmem";
>            reg = <0x0 0x47ff1000 0x0 0x1000>;
> };
> scmi_xen: scmi {
>          compatible = "arm,scmi-smc";
>          arm,smc-id = <0x82000003>; <--- Xen manegement agent smc-id
>          #address-cells = < 1>;
>          #size-cells = < 0>;
>          #access-controller-cells = < 1>;
>          shmem = <&scmi_shm_1>; <--- Xen manegement agent shmem
> };
> 
> - The driver obtains Xen specific SCMI Agent's configuration from the Host DT, probes Agents and
>    builds SCMI Agents list. The Agents configuration is taken from "scmi-secondary-agents"
>    property where first item is "arm,smc-id", second - "arm,scmi-shmem" phandle and third is
>    optional "agent_id":
> 
> chosen {
>    ranges;
>    xen,config {
>      ranges;
>      scmi-secondary-agents = <
>                    0x82000003 &scmi_shm_0 0
>                    0x82000004 &scmi_shm_2 2
>                    0x82000005 &scmi_shm_3 3
>                    0x82000006 &scmi_shm_4 4>;
>      #scmi-secondary-agents-cells = <3>; <--- optional, default 3
> 
>      scmi_shm_0 : sram@47ff0000 {
>          compatible = "arm,scmi-shmem";
>          reg = <0x0 0x47ff0000 0x0 0x1000>;
>      };
> 
>      scmi_shm_2: sram@47ff2000 {
>              compatible = "arm,scmi-shmem";
>              reg = <0x0 0x47ff2000 0x0 0x1000>;
>      };
>      scmi_shm_3: sram@47ff3000 {
>              compatible = "arm,scmi-shmem";
>              reg = <0x0 0x47ff3000 0x0 0x1000>;
>      };
>      scmi_shm_4: sram@47ff4000 {
>              compatible = "arm,scmi-shmem";
>              reg = <0x0 0x47ff4000 0x0 0x1000>;
>      };
> 
>      // Xen SCMI management channel
>      scmi_shm_1: sram@47ff1000 {
>              compatible = "arm,scmi-shmem";
>              reg = <0x0 0x47ff1000 0x0 0x1000>;
>      };
> 
>      scmi_xen: scmi {
>          compatible = "arm,scmi-smc";
>          arm,smc-id = <0x82000002>; <--- Xen manegement agent smc-id
>          #address-cells = < 1>;
>          #size-cells = < 0>;
>          #access-controller-cells = < 1>;
>          shmem = <&scmi_shm_1>; <--- Xen manegement agent shmem
>      };
>    };
> };
> 
> /{
>      // Host SCMI OSPM channel - provided to the Dom0 as is if SCMI enabled for it
>      scmi_shm: sram@47ff0000 {
>              compatible = "arm,scmi-shmem";
>              reg = <0x0 0x47ff0000 0x0 0x1000>;
>      };
> 
>      firmware {
>          scmi: scmi {
>              compatible = "arm,scmi-smc";
>              arm,smc-id = <0x82000002>; <--- Host OSPM agent smc-id
>              #address-cells = < 1>;
>              #size-cells = < 0>;
>              shmem = <&scmi_shm>; <--- Host OSPM agent shmem
> 
>              protocol@X{
>              };
>          };
>      };
> };
> 
> This approach allows defining multiple SCMI Agents by adding Xen-specific properties under
> the ``/chosen`` node to the Host Device Tree, leaving the main part unchanged. The Host DT
> SCMI channel will be passed to Dom0.
> 
> The Xen management agent is described as a ``scmi_xen`` node under the ``/chosen`` node, which
> is used by Xen to control other SCMI Agents in the system.
> 
> All secondary agents' configurations are provided in the ``scmi-secondary-agents`` property with
> an optional ``agent_id`` field.
> 
> The ``agent_id`` from the ``scmi-secondary-agents`` property is used to identify the agent in the
> system and can be omitted by setting ``#scmi-secondary-agents-cells = <2>``, so the Secondary
> Agents configuration will look like this:
> 
> chosen {
>    xen,config {
>      scmi-secondary-agents = <
>                    0x82000003 &scmi_shm_0
>                    0x82000004 &scmi_shm_2
>                    0x82000005 &scmi_shm_3
>                    0x82000006 &scmi_shm_4>;
>      #scmi-secondary-agents-cells = <2>;
>    };
> }
> 
> In this case, Xen will use the ``SCMI_BASE_DISCOVER_AGENT`` call to discover the ``agent_id``
> for each secondary agent. Providing the ``agent_id`` in the ``scmi-secondary-agents`` property
> allows skipping the discovery call, which is useful when the secondary agent's shared memory is
> not accessible by Xen or when boot time is important because it allows skipping the agent
> discovery procedure.
> 
>    Note that Xen is the only one entry in the system which need to know
>    about SCMI multi-agent support.
> 
> - It implements the SCI subsystem interface required for configuring and
> enabling SCMI functionality for Dom0/hwdom and Guest domains. To enable
> SCMI functionality for domain it has to be configured with unique supported
> SCMI Agent_id and use corresponding SCMI SMC/HVC shared memory transport
> [smc-id, shmem] defined for this SCMI Agent_id.
> - Once Xen domain is configured it can communicate with EL3 SCMI FW:
>    -- zero-copy, the guest domain puts SCMI message in shmem;
>    -- the guest triggers SMC/HVC exception with smc-id (doorbell);
>    -- the Xen driver catches exception, do checks and synchronously forwards
>    it to EL3 FW.
> - the Xen driver sends BASE_RESET_AGENT_CONFIGURATION message to Xen
>    management agent channel on domain destroy event. This allows to reset
>    resources used by domain and so implement use-case like domain reboot.
> 
> Dom0 Enable SCMI SMC:
>   - pass dom0_scmi_agent_id= in Xen command line. if not provided
>     SCMI will be disabled for Dom0 and all SCMI nodes removed from Dom0 DT.
>     The driver updates Dom0 DT SCMI node "arm,smc-id" value and fix up shmem
>     node according to assigned agent_id.
> 
> Guest domains enable SCMI SMC:
>   - xl.cfg: add configuration option as below
> 
>     arm_sci = "type=scmi_smc_multiagent,agent_id=2"
> 
>   - xl.cfg: enable access to the "arm,scmi-shmem" which should correspond assigned agent_id for
>     the domain, for example:
> 
> iomem = [
>      "47ff2,1@22001",
> ]
> 
>   - DT: add SCMI nodes to the Driver domain partial device tree as in the
>   below example. The "arm,smc-id" should correspond assigned agent_id for the domain:
> 
> passthrough {
>     scmi_shm_0: sram@22001000 {
>         compatible = "arm,scmi-shmem";
>         reg = <0x0 0x22001000 0x0 0x1000>;
>     };
> 
>     firmware {
>          compatible = "simple-bus";
>              scmi: scmi {
>                  compatible = "arm,scmi-smc";
>                  arm,smc-id = <0x82000004>;
>                  shmem = <&scmi_shm_0>;
>                  ...
>              }
>      }
> }
> 
> SCMI "4.2.1.1 Device specific access control"
> 
> The XEN SCI SCMI SMC multi-agent driver performs "access-controller" provider function
> in case EL3 SCMI FW implements SCMI "4.2.1.1 Device specific access control" and provides the
> BASE_SET_DEVICE_PERMISSIONS command to configure the devices that an agents have access to.
> The DT SCMI node should "#access-controller-cells=<1>" property and DT devices should be bound
> to the Xen SCMI.
> 
> &i2c1 {
> 	access-controllers = <&scmi 0>;
> };
> 
> The Dom0 and dom0less domains DT devices will be processed automatically through
> sci_assign_dt_device() call, but to assign SCMI devices from toolstack the xl.cfg:"dtdev" property
> shell be used:
> 
> dtdev = [
>      "/soc/i2c@e6508000",
> ]
> 
> xl.cfg:dtdev will contain all nodes which are under SCMI management (not only those which are behind IOMMU).
> 
> [1] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> [2] https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml
> 
> Signed-off-by: Oleksii Moisieiev 
> Signed-off-by: Grygorii Strashko 
> ---
> 
> Changes in v5:
> - fix device-tree example format in booting.txt, added ";" after "}".
> - update define in scmi-proto.h
> - update define in scmi-shmem.h file
> - scmi_assign_device - do not ignore -EOPNOTSUPP return
> code of the do_smc_xfer
> - remove overwriting agent_channel->agent_id after
> SCMI_BASE_DISCOVER_AGENT call
> - add multi-agent files to the MAINTAINERS
> - add SCMI multi-agent description to the SUPPORT.md
> - handle ARM_SMCCC_INVALID_PARAMETER return code and return -EINVAL
> for smc call
> - updated collect_agents function. Set agent_id parameter as optional
> in scmi-secondary-agents device-tree property
> - introduce "#scmi-secondary-agents-cells" parameter to set if
> agent_id was provided
> - reanme xen,scmi-secondary-agents property to scmi-secondary-agents
> - move memcpu_toio/fromio for the generic place
> - update Xen to get management channel from /chosen/xen,config node
> - get hypervisor channnel from node instead of using hardcoded
> - update handling scmi and shmem nodes for the domain
> - Set multi-agent driver to support only Arm64
> 
> Changes in v4:
> - toolstack comments from Anthony PERARD
> - added dom0less support
> - added doc for "xen,scmi-secondary-agents"
> 
>   MAINTAINERS                                 |   4 +
>   SUPPORT.md                                  |  11 +
>   docs/man/xl.cfg.5.pod.in                    |  13 +
>   docs/misc/arm/device-tree/booting.txt       |  88 +++
>   docs/misc/xen-command-line.pandoc           |   9 +
>   tools/libs/light/libxl_arm.c                |   4 +
>   tools/libs/light/libxl_types.idl            |   4 +-
>   tools/xl/xl_parse.c                         |  12 +
>   xen/arch/arm/dom0less-build.c               |  11 +
>   xen/arch/arm/domain_build.c                 |   3 +-
>   xen/arch/arm/firmware/Kconfig               |  12 +
>   xen/arch/arm/firmware/Makefile              |   1 +
>   xen/arch/arm/firmware/scmi-proto.h          | 164 ++++
>   xen/arch/arm/firmware/scmi-shmem.c          | 112 +++
>   xen/arch/arm/firmware/scmi-shmem.h          |  45 ++
>   xen/arch/arm/firmware/scmi-smc-multiagent.c | 803 ++++++++++++++++++++
>   xen/include/public/arch-arm.h               |   3 +
>   17 files changed, 1297 insertions(+), 2 deletions(-)
>   create mode 100644 xen/arch/arm/firmware/scmi-proto.h
>   create mode 100644 xen/arch/arm/firmware/scmi-shmem.c
>   create mode 100644 xen/arch/arm/firmware/scmi-shmem.h
>   create mode 100644 xen/arch/arm/firmware/scmi-smc-multiagent.c
> 

[snip]

> diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
> index 68d2ebeb9f..4c05b20c06 100644
> --- a/tools/xl/xl_parse.c
> +++ b/tools/xl/xl_parse.c
> @@ -1306,6 +1306,18 @@ static int parse_arm_sci_config(XLU_Config *cfg, libxl_arm_sci *arm_sci,
>               }
>           }
>   
> +        if (MATCH_OPTION("agent_id", ptr, oparg)) {
> +            unsigned long val = parse_ulong(oparg);
> +
> +            if (!val || val > 255) {
> +                fprintf(stderr, "An invalid ARM_SCI agent_id specified (%lu). Valid range [1..255]\n",
> +                        val);
> +                ret = ERROR_INVAL;
> +                goto parse_error;
> +            }
> +            arm_sci->agent_id = val;
> +        }
> +
>           ptr = strtok(NULL, ",");
>       }
>   
> diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
> index d28143f98b..6ca17b0ce6 100644
> --- a/xen/arch/arm/dom0less-build.c
> +++ b/xen/arch/arm/dom0less-build.c
> @@ -299,6 +299,17 @@ int __init domu_dt_sci_parse(struct dt_device_node *node,
>           d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
>       else if ( !strcmp(sci_type, "scmi_smc") )
>           d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC;
> +    else if ( !strcmp(sci_type, "scmi_smc_multiagent") )
> +    {
> +        uint32_t agent_id = 0;
> +
> +        if ( !dt_property_read_u32(node, "xen,sci_agent_id", &agent_id) ||
> +             !agent_id )
> +            return -EINVAL;

In toolstack you keep the check for agent_id to be in the range of 1 to 
255. Why do not check here as well?


> +
> +        d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC_MA;
> +        d_cfg->arch.arm_sci_agent_id = agent_id;
> +    }
>       else
>       {
>           printk(XENLOG_ERR "xen,sci_type in not valid (%s) for domain %s\n",


[snip]

> diff --git a/xen/arch/arm/firmware/scmi-proto.h b/xen/arch/arm/firmware/scmi-proto.h
> new file mode 100644
> index 0000000000..e290d6630d
> --- /dev/null
> +++ b/xen/arch/arm/firmware/scmi-proto.h
> @@ -0,0 +1,164 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Arm System Control and Management Interface definitions
> + * Version 3.0 (DEN0056C)
> + *
> + * Copyright (c) 2024 EPAM Systems

2025


[snip]


> diff --git a/xen/arch/arm/firmware/scmi-shmem.c b/xen/arch/arm/firmware/scmi-shmem.c
> new file mode 100644
> index 0000000000..8fc8ca356b
> --- /dev/null
> +++ b/xen/arch/arm/firmware/scmi-shmem.c
> @@ -0,0 +1,112 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * SCI SCMI multi-agent driver, using SMC/HVC shmem as transport.

NIT: Is this really a multi-agent driver?

(scmi-smc-multiagent.c has exact the same description).

> + *
> + * Oleksii Moisieiev 
> + * Copyright (c) 2025 EPAM Systems
> + */
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#include 
> +#include 
> +#include 

NIT: AFAIK, "asm" should be included after "xen"

> +
> +#include "scmi-proto.h"
> +#include "scmi-shmem.h"
> +

[snip]

> +
> +static struct scmi_channel *smc_create_channel(uint32_t agent_id,
> +                                               uint32_t func_id, uint64_t addr)
> +{
> +    struct scmi_channel *channel;
> +
> +    channel = get_channel_by_id(agent_id);
> +    if ( channel )
> +        return ERR_PTR(EEXIST);

missing "-" before EEXIST


> +
> +    channel = xmalloc(struct scmi_channel);
> +    if ( !channel )
> +        return ERR_PTR(ENOMEM);

missing "-" before ENOMEM

> +
> +    spin_lock_init(&channel->lock);
> +    channel->agent_id = agent_id;
> +    channel->func_id = func_id;
> +    channel->domain_id = DOMID_INVALID;
> +    channel->shmem = NULL;
> +    channel->paddr = addr;
> +    list_add_tail(&channel->list, &scmi_data.channel_list);
> +    return channel;
> +}
> +

[snip]

> +
> +static int scmi_dt_hyp_channel_read(struct dt_device_node *scmi_node, struct scmi_data *scmi_data,
> +                                    u64 *addr)

Missing __init?

> +{
> +    int ret;
> +    u64 size;
> +
> +    if ( !dt_property_read_u32(scmi_node, "arm,smc-id", &scmi_data->func_id) )
> +    {
> +        printk(XENLOG_ERR "scmi: unable to read smc-id from DT\n");
> +        return -ENOENT;
> +    }
> +
> +    ret = scmi_dt_read_hyp_channel_addr(scmi_node, addr, &size);
> +    if ( IS_ERR_VALUE(ret) )
> +        return -ENOENT;
> +
> +    if ( !IS_ALIGNED(size, SCMI_SHMEM_MAPPED_SIZE) )
> +    {
> +        printk(XENLOG_ERR "scmi: shmem memory is not aligned\n");
> +        return -EINVAL;
> +    }
> +
> +    return 0;
> +}
> +
> +static __init int scmi_probe(struct dt_device_node *scmi_node, const void *data)
> +{
> +    u64 addr;
> +    int ret;
> +    struct scmi_channel *channel;
> +    int n_agents;

unsigned int please if n_agents cannot be negative

> +    scmi_msg_header_t hdr;
> +    struct scmi_msg_base_attributes_p2a rx;
> +
> +    ASSERT(scmi_node != NULL);
> +
> +    INIT_LIST_HEAD(&scmi_data.channel_list);
> +    spin_lock_init(&scmi_data.channel_list_lock);
> +
> +    if ( !acpi_disabled )
> +    {
> +        printk(XENLOG_WARNING "scmi: is not supported when using ACPI\n");
> +        return -EINVAL;
> +    }
> +
> +    ret = scmi_check_smccc_ver();
> +    if ( ret )
> +        return ret;
> +
> +    ret = scmi_dt_hyp_channel_read(scmi_node, &scmi_data, &addr);
> +    if ( ret )
> +        return ret;
> +
> +    scmi_data.dt_dev = scmi_node;
> +
> +    channel = smc_create_channel(SCMI_BASE_AGENT_ID_OWN, scmi_data.func_id, addr);
> +    if ( IS_ERR(channel) )
> +        goto out;
> +
> +    /* Request agent id for Xen management channel  */
> +    ret = collect_agent_id(channel);
> +    if ( ret )
> +        return ret;

Why just ret? You seem to allocate memory in smc_create_channel() which
needs to be freed. I guess, free_channel_list() is needed.

> +
> +    /* Save the agent id for Xen management channel */
> +    scmi_data.hyp_channel_agent_id = channel->agent_id;
> +
> +    ret = map_channel_memory(channel);
> +    if ( ret )
> +        goto out;

The same question as above, as "goto out;" in your case is equivalent of 
"return ret;"

> +
> +    channel->domain_id = DOMID_XEN;
> +
> +    hdr.id = SCMI_BASE_PROTOCOL_ATTIBUTES;
> +    hdr.type = 0;
> +    hdr.protocol = SCMI_BASE_PROTOCOL;
> +
> +    ret = do_smc_xfer(channel, &hdr, NULL, 0, &rx, sizeof(rx));
> +    if ( ret )
> +        goto error;
> +
> +    n_agents = SCMI_FIELD_GET(SCMI_BASE_ATTR_NUM_AGENT, rx.attributes);
> +    printk(XENLOG_DEBUG "scmi: Got agent count %d\n", n_agents);
> +    ret = collect_agents(scmi_node);
> +    if ( ret )
> +        goto error;
> +
> +    ret = sci_register(&scmi_ops);
> +    if ( ret )
> +    {
> +        printk(XENLOG_ERR "SCMI: mediator already registered (ret = %d)\n",
> +               ret);
> +        return ret;
> +    }
> +
> +    scmi_data.initialized = true;
> +    goto out;
> +
> +error:
> +    unmap_channel_memory(channel);
> +    free_channel_list();
> +out:
> +    return ret;
> +}

[snip]




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Date: Wed, 27 Aug 2025 12:39:06 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: Stefano Stabellini , 
    "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [RFC PATCH v5 02/10] xen/arm: scmi-smc: update to be used under
 sci subsystem
In-Reply-To: <1f64aa13-d9d3-4b58-9581-a45f7173430b@epam.com>
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 <1f64aa13-d9d3-4b58-9581-a45f7173430b@epam.com>
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On Wed, 27 Aug 2025, Oleksii Moisieiev wrote:
> On 23/08/2025 03:26, Stefano Stabellini wrote:
> > On Tue, 22 Jul 2025, Oleksii Moisieiev wrote:
> >> From: Grygorii Strashko 
> >>
> >> The introduced SCI (System Control Interface) subsystem provides unified
> >> interface to integrate in Xen SCI drivers which adds support for ARM
> >> firmware (EL3, SCP) based software interfaces (like SCMI) that are used in
> >> system management. The SCI subsystem allows to add drivers for different FW
> >> interfaces or have different drivers for the same FW interface (for example,
> >> SCMI with different transports).
> >>
> >> This patch updates SCMI over SMC calls handling layer, introduced by
> >> commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI over SMC calls handling
> >> layer"), to be SCI driver:
> >> - convert to DT device;
> >> - convert to SCI Xen interface.
> >>
> >> There are no functional changes in general, the driver is just adopted
> >> to the SCI interface.
> >>
> >> Signed-off-by: Grygorii Strashko 
> >> Signed-off-by: Oleksii Moisieiev 
> >> ---
> >>
> >>
> >>
> >>   xen/arch/arm/firmware/Kconfig                | 13 ++-
> >>   xen/arch/arm/firmware/scmi-smc.c             | 93 +++++++++++---------
> >>   xen/arch/arm/include/asm/firmware/scmi-smc.h | 41 ---------
> >>   xen/arch/arm/vsmc.c                          |  5 +-
> >>   xen/include/public/arch-arm.h                |  1 +
> >>   5 files changed, 64 insertions(+), 89 deletions(-)
> >>   delete mode 100644 xen/arch/arm/include/asm/firmware/scmi-smc.h
> >>
> >> diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig
> >> index fc7918c7fc..bbf88fbb9a 100644
> >> --- a/xen/arch/arm/firmware/Kconfig
> >> +++ b/xen/arch/arm/firmware/Kconfig
> >> @@ -8,9 +8,18 @@ config ARM_SCI
> >>   
> >>   menu "Firmware Drivers"
> >>   
> >> +choice
> >> +	prompt "ARM SCI driver type"
> >> +	default SCMI_SMC
> >> +	help
> >> +	Choose which ARM SCI driver to enable.
> >> +
> >> +config ARM_SCI_NONE
> >> +	bool "none"
> >> +
> >>   config SCMI_SMC
> >>   	bool "Forward SCMI over SMC calls from hwdom to EL3 firmware"
> >> -	default y
> >> +	select ARM_SCI
> >>   	help
> >>   	  This option enables basic awareness for SCMI calls using SMC as
> >>   	  doorbell mechanism and Shared Memory for transport ("arm,scmi-smc"
> >> @@ -18,4 +27,6 @@ config SCMI_SMC
> >>   	  firmware node is used to trap and forward corresponding SCMI SMCs
> >>   	  to firmware running at EL3, for calls coming from the hardware domain.
> >>   
> >> +endchoice
> >> +
> >>   endmenu
> >> diff --git a/xen/arch/arm/firmware/scmi-smc.c b/xen/arch/arm/firmware/scmi-smc.c
> >> index 33473c04b1..13d1137592 100644
> >> --- a/xen/arch/arm/firmware/scmi-smc.c
> >> +++ b/xen/arch/arm/firmware/scmi-smc.c
> >> @@ -9,6 +9,7 @@
> >>    * Copyright 2024 NXP
> >>    */
> >>   
> >> +#include 
> >>   #include 
> >>   #include 
> >>   #include 
> >> @@ -16,12 +17,11 @@
> >>   #include 
> >>   #include 
> >>   
> >> +#include 
> >>   #include 
> >> -#include 
> >>   
> >>   #define SCMI_SMC_ID_PROP   "arm,smc-id"
> >>   
> >> -static bool __ro_after_init scmi_enabled;
> >>   static uint32_t __ro_after_init scmi_smc_id;
> >>   
> >>   /*
> >> @@ -41,14 +41,11 @@ static bool scmi_is_valid_smc_id(uint32_t fid)
> >>    *
> >>    * Returns true if SMC was handled (regardless of response), false otherwise.
> >>    */
> >> -bool scmi_handle_smc(struct cpu_user_regs *regs)
> >> +static bool scmi_handle_smc(struct cpu_user_regs *regs)
> >>   {
> >>       uint32_t fid = (uint32_t)get_user_reg(regs, 0);
> >>       struct arm_smccc_res res;
> >>   
> >> -    if ( !scmi_enabled )
> >> -        return false;
> >> -
> >>       if ( !scmi_is_valid_smc_id(fid) )
> >>           return false;
> >>   
> >> @@ -78,49 +75,45 @@ bool scmi_handle_smc(struct cpu_user_regs *regs)
> >>       return true;
> >>   }
> >>   
> >> -static int __init scmi_check_smccc_ver(void)
> >> +static int scmi_smc_domain_init(struct domain *d,
> >> +                                struct xen_domctl_createdomain *config)
> >>   {
> >> -    if ( smccc_ver < ARM_SMCCC_VERSION_1_1 )
> >> -    {
> >> -        printk(XENLOG_WARNING
> >> -               "SCMI: No SMCCC 1.1 support, SCMI calls forwarding disabled\n");
> >> -        return -ENOSYS;
> >> -    }
> >> +    if ( !is_hardware_domain(d) )
> >> +        return 0;
> > Should we also check for config->arch.sci_type ==
> > XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC ?
> >
> Current changes assume that only SCMI_SMC is present. This check was 
> added in the subsequent patch when multiagent was introduced.

In theory ARM_SCI_NONE is possible?



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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[PATCH]=20hvmloader:=20Update=20to=20SMBIOS=202.6?=
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Le 27/08/2025 =C3=A0 19:49, Andrew Cooper a =C3=A9crit=C2=A0:
> On 22/08/2025 2:47 pm, Teddy Astie wrote:
>> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
>> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
>>
>> In Linux, if the SMBIOS version is >=3D 2.6, the GUID format is used, el=
se
>> (undefined as per SMBIOS spec), big endian is used (used by Xen). Theref=
ore,
>> you have a endian mismatch causing the UUIDs to mismatch in the guest.
>>
>> $ cat /sys/hypervisor/uuid
>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>> $ cat /sys/devices/virtual/dmi/id/product_uuid
>> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
>> $ cat /sys/devices/virtual/dmi/id/product_serial
>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>
>> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
>> written in the table; which effectively fix this endianness mismatch wit=
h
>> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.
>>
>> Signed-off-by: Teddy Astie 
>> ---
>> This effectively changes the UUID seen with UEFI guests as it was
>> actually inconsistent with SeaBIOS and SMBIOS expectations.
>> ---
> 
> I agree this is a real bug and needs fixing.=C2=A0 However, ...
> 
> 
>>   tools/firmware/hvmloader/smbios.c | 20 ++++++++++++++++++--
>>   1 file changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/tools/firmware/hvmloader/smbios.c b/tools/firmware/hvmloade=
r/smbios.c
>> index 6bcdcc233a..f4822ae6f8 100644
>> --- a/tools/firmware/hvmloader/smbios.c
>> +++ b/tools/firmware/hvmloader/smbios.c
>> @@ -352,7 +352,7 @@ smbios_entry_point_init(void *start,
>>       memcpy(ep->anchor_string, "_SM_", 4);
>>       ep->length =3D 0x1f;
>>       ep->smbios_major_version =3D 2;
>> -    ep->smbios_minor_version =3D 4;
>> +    ep->smbios_minor_version =3D 6;
>>       ep->max_structure_size =3D max_structure_size;
>>       ep->entry_point_revision =3D 0;
>>       memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
>> @@ -462,7 +462,23 @@ smbios_type_1_init(void *start, const char *xen_ver=
sion,
>>       p->version_str =3D 3;
>>       p->serial_number_str =3D 4;
>>   
>> -    memcpy(p->uuid, uuid, 16);
>> +    /*
>> +     * Xen uses OSF DCE UUIDs which is fully big endian, however,
>> +     * GUIDs (which requirement is clarified by SMBIOS >=3D 2.6) has th=
e
>> +     * first 3 components appearing as being little endian and the rest
>> +     * as still being big endian.
> 
> ... this is not an accurate statement.
> 
> Xen specifically tries to treat a xen_domain_handle_t as an opaque blob.
> 
> The only two areas I can see ascribing any structure are the 'q'
> debugkey (not exactly a strong ABI statement), and the arinc635
> scheduler whose use is buggy (uuids are not unique in Xen; it's the
> domid which is).
> 
> It is an error that a format isn't stated, but the format comes from the
> toolstack.=C2=A0 We'd better hope that all toolstacks use OSF DCE UUIDs, =
or
> this is going to badly wrong.
> 

I agree in principle. maybe OSF DCE UUID is not the proper definition 
(even though it implies the same) but I should rather use RFC 9562 UUIDs 
but refering to the string representation rather than the UUID meaning 
itself.

The RFC 9562 defines the UUID as being sequenced as big endian and 
string represented as > UUID     =3D 4hexOctet "-"
>            2hexOctet "-"
>            2hexOctet "-"
>            2hexOctet "-"
>            6hexOctet
> hexOctet =3D HEXDIG HEXDIG
> DIGIT    =3D %x30-39
> HEXDIG   =3D DIGIT / "A" / "B" / "C" / "D" / "E" / "F"

This matches the UUID encoding provided by XEN_DEFINE_UUID and is used 
by libxl, libvirt and XAPI and considered by Linux when reading the 
UUID. However, it may always not be a "valid" UUID strictly speaking but 
it doesn't really matter since we only care about its binary/string 
representation.

> And on that note, the toolstacks are not the same.=C2=A0 Xapi for example
> uses reads 16 bytes out of /dev/urandom.
> 
> Whatever we end up doing, the fix must include a change to
> xen/include/public/version.h stating the format of the UUID.
> 
Something like

diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
index 04fc891353..3241e8dd2b 100644
--- a/xen/include/public/xen.h
+++ b/xen/include/public/xen.h
@@ -975,6 +975,10 @@ typedef struct dom0_vga_console_info {
  #define xen_vga_console_info dom0_vga_console_info
  #define xen_vga_console_info_t dom0_vga_console_info_t

+/*
+ * The guest handled provided by toolstack encoded as a UUID in
+ * big-endian order. Its string representation follows RFC 9562.
+ */
  typedef uint8_t xen_domain_handle_t[16];

  __DEFINE_XEN_GUEST_HANDLE(uint8,  uint8_t);

?

So that we're converting between big-endian encoded UUID (RFC 9562) and 
Microsoft GUID (which doesn't care about its content but only about its 
endianness regarding formatting).

> ~Andrew
> 

Teddy


Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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        Wed, 27 Aug 2025 14:23:21 -0700 (PDT)
From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v10 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
Date: Thu, 28 Aug 2025 00:21:33 +0300
Message-ID: <55ff99acd69f9eaf20f077e6b453b54931b541d4.1756329091.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

Add support for the PSCI SYSTEM_SUSPEND function in the vPSCI interface,
allowing guests to request suspend via the PSCI v1.0 SYSTEM_SUSPEND call
(both 32-bit and 64-bit variants).

Implementation details:
- Add SYSTEM_SUSPEND function IDs to PSCI definitions
- Trap and handle SYSTEM_SUSPEND in vPSCI
- Allow only non-hardware domains to invoke SYSTEM_SUSPEND; return
  PSCI_NOT_SUPPORTED for the hardware domain to avoid halting the system
  in hwdom_shutdown() via domain_shutdown
- Require all secondary VCPUs of the calling domain to be offline before
  suspend, as mandated by the PSCI specification

Additionally, GIC context must be saved when a domain suspends.
LRs are not architecturally preserved across suspend/resume or context
switches, so Xen must explicitly save and restore them. This requirement
is specified in the PSCI specification (DEN0022F.b, section 6.8 "Preserving
the execution context"). The fix is implemented by moving the respective
code in ctxt_switch_from() before the return path taken when the domain
suspends.

Introduce domain_resume_nopause/_helper() to allow resuming a domain from
SYSTEM_SUSPEND without pausing it first. This avoids problematic
domain_pause() calls when resuming from suspend on Arm, particularly in error
paths. The helper is Arm-specific; other architectures continue to use the
original domain_resume().

Usage:

For Linux-based guests, suspend can be initiated with:
    echo mem > /sys/power/state
or via:
    systemctl suspend

Resuming the guest is performed from control domain using:
      xl resume 

Signed-off-by: Mykola Kvach 
---
Changes in V10:
- small changes to the commit message reflect updates introduced in this
  version of the patch.
- Comments are improved, clarified, and expanded, especially regarding PSCI
  requirements and context handling.
- An ARM-specific helper (domain_resume_nopause_helper)
- gprintk() and PRIregister are used for logging in vPSCI code.
- An isb() is added before p2m_save_state
- The is_64bit_domain check is dropped when masking the upper part of entry
  point and cid for SMC32 SYSTEM_SUSPEND PSCI calls

Changes in V9:
- no functional changes
- cosmetic chnages after review
- enhance commit message and add extra comment to the code after review

Changes in V8:
- GIC and virtual timer context must be saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Changes in V6:
- skip execution of ctxt_switch_from for vcpu that is in paused domain
- add implementation of domain_resume without domain_pause
- add helper function to determine if vcpu is suspended or not
- ignore upper 32 bits of argument values when the domain is 64-bit
  and calls the SMC32 SYSTEM_SUSPEND function
- cosmetic changes after review

Changes in V5:
- don't use standby mode, restore execution in a provided by guest point
- move checking that all CPUs, except current one, are offline to after
  pausing the vCPUs
- provide ret status from arch_domain_shutdown and handle it in
  domain_shutdown
- adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI functions

Changes in V4:
Dropped all changes related to watchdog, domain is marked as shutting
down in domain_shutdown and watchdog timeout handler won't trigger
because of it.

Previous versions included code to manage Xen watchdog timers during suspend,
but this was removed. When a guest OS starts the Xen watchdog (either via the
kernel driver or xenwatchdogd), it is responsible for managing that state
across suspend/resume. On Linux, the Xen kernel driver properly stops the
watchdog during suspend. However, when xenwatchdogd is used instead, suspend
handling is incomplete, potentially leading to watchdog-triggered resets on
resume. Xen leaves watchdog handling to the guest OS and its services.

Dropped all changes related to VCPU context, because instead domain_shutdown
is used, so we don't need any extra changes for suspending domain.

Changes in V3:
Dropped all domain flags and related code (which touched common functions like
vcpu_unblock), keeping only the necessary changes for Xen suspend/resume, i.e.
suspend/resume is now fully supported only for the hardware domain.
Proper support for domU suspend/resume will be added in a future patch.
This patch does not yet include VCPU context reset or domain context
restoration in VCPU.
---
 xen/arch/arm/domain.c                 |  21 +++++-
 xen/arch/arm/include/asm/domain.h     |   2 +
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   2 +-
 xen/arch/arm/vpsci.c                  | 100 ++++++++++++++++++++++----
 xen/common/domain.c                   |  35 +++++++--
 xen/include/xen/sched.h               |   3 +
 8 files changed, 141 insertions(+), 25 deletions(-)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 863ae18157..401106fd67 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -90,6 +90,24 @@ static void ctxt_switch_from(struct vcpu *p)
     if ( is_idle_vcpu(p) )
         return;
 
+    /*
+     * Even if the guest saves and restores its own context, Xen must save
+     * the transient state (such as List Registers) that is not preserved
+     * by hardware across suspend. See PSCI DEN0022F.b, section 6.8
+     * "Preserving the execution context".
+     */
+    gic_save_state(p);
+
+    /*
+     * Skip saving the rest of the context if the VCPU is suspended,
+     * to avoid modifying SCTLR_EL1. This is required by the PSCI
+     * specification, which manages SCTLR_EL1 during SYSTEM_SUSPEND flow.
+     */
+    if ( test_bit(_VPF_suspended, &p->pause_flags) )
+        return;
+
+    isb();
+
     p2m_save_state(p);
 
     /* CP 15 */
@@ -158,9 +176,6 @@ static void ctxt_switch_from(struct vcpu *p)
 
     /* XXX MPU */
 
-    /* VGIC */
-    gic_save_state(p);
-
     isb();
 }
 
diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
index a3487ca713..f9577bc9ae 100644
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -312,6 +312,8 @@ static inline void update_guest_memory_policy(struct vcpu *v,
                                               struct guest_memory_policy *gmp)
 {}
 
+void domain_resume_nopause_helper(struct domain *d);
+
 #endif /* __ASM_DOMAIN_H__ */
 
 /*
diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/include/asm/perfc_defn.h
index effd25b69e..8dfcac7e3b 100644
--- a/xen/arch/arm/include/asm/perfc_defn.h
+++ b/xen/arch/arm/include/asm/perfc_defn.h
@@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system_reset")
 PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
 PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
 PERFCOUNTER(vpsci_features,            "vpsci: features")
+PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
 
 PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
 
diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/psci.h
index 4780972621..48a93e6b79 100644
--- a/xen/arch/arm/include/asm/psci.h
+++ b/xen/arch/arm/include/asm/psci.h
@@ -47,10 +47,12 @@ void call_psci_system_reset(void);
 #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
 #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
 #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
+#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
 
 #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
 #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
 #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
+#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
 
 /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
 #define PSCI_0_2_AFFINITY_LEVEL_ON      0
diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/asm/vpsci.h
index 0cca5e6830..69d40f9d7f 100644
--- a/xen/arch/arm/include/asm/vpsci.h
+++ b/xen/arch/arm/include/asm/vpsci.h
@@ -23,7 +23,7 @@
 #include 
 
 /* Number of function implemented by virtual PSCI (only 0.2 or later) */
-#define VPSCI_NR_FUNCS  12
+#define VPSCI_NR_FUNCS  14
 
 /* Functions handle PSCI calls from the guests */
 bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index 7ba9ccd94b..3371f33b81 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -10,28 +10,18 @@
 
 #include 
 
-static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
-                            register_t context_id)
+static int do_setup_vcpu_ctx(struct vcpu *v, register_t entry_point,
+                      register_t context_id)
 {
-    struct vcpu *v;
     struct domain *d = current->domain;
     struct vcpu_guest_context *ctxt;
     int rc;
     bool is_thumb = entry_point & 1;
-    register_t vcpuid;
-
-    vcpuid = vaffinity_to_vcpuid(target_cpu);
-
-    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
-        return PSCI_INVALID_PARAMETERS;
 
     /* THUMB set is not allowed with 64-bit domain */
     if ( is_64bit_domain(d) && is_thumb )
         return PSCI_INVALID_ADDRESS;
 
-    if ( !test_bit(_VPF_down, &v->pause_flags) )
-        return PSCI_ALREADY_ON;
-
     if ( (ctxt = alloc_vcpu_guest_context()) == NULL )
         return PSCI_DENIED;
 
@@ -78,11 +68,32 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
     if ( rc < 0 )
         return PSCI_DENIED;
 
-    vcpu_wake(v);
-
     return PSCI_SUCCESS;
 }
 
+static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
+                            register_t context_id)
+{
+    int rc;
+    struct vcpu *v;
+    struct domain *d = current->domain;
+    register_t vcpuid;
+
+    vcpuid = vaffinity_to_vcpuid(target_cpu);
+
+    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
+        return PSCI_INVALID_PARAMETERS;
+
+    if ( !test_bit(_VPF_down, &v->pause_flags) )
+        return PSCI_ALREADY_ON;
+
+    rc = do_setup_vcpu_ctx(v, entry_point, context_id);
+    if ( rc == PSCI_SUCCESS )
+        vcpu_wake(v);
+
+    return rc;
+}
+
 static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
 {
     int32_t ret;
@@ -197,6 +208,48 @@ static void do_psci_0_2_system_reset(void)
     domain_shutdown(d,SHUTDOWN_reboot);
 }
 
+static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid)
+{
+    int32_t rc;
+    struct vcpu *v;
+    struct domain *d = current->domain;
+
+    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
+    if ( is_hardware_domain(d) )
+        return PSCI_NOT_SUPPORTED;
+
+    /* Ensure that all CPUs other than the calling one are offline */
+    domain_lock(d);
+    for_each_vcpu ( d, v )
+    {
+        if ( v != current && is_vcpu_online(v) )
+        {
+            domain_unlock(d);
+            return PSCI_DENIED;
+        }
+    }
+    domain_unlock(d);
+
+    rc = domain_shutdown(d, SHUTDOWN_suspend);
+    if ( rc )
+        return PSCI_DENIED;
+
+    rc = do_setup_vcpu_ctx(current, epoint, cid);
+    if ( rc != PSCI_SUCCESS )
+    {
+        domain_resume_nopause_helper(d);
+        return rc;
+    }
+
+    set_bit(_VPF_suspended, ¤t->pause_flags);
+
+    gprintk(XENLOG_DEBUG,
+            "SYSTEM_SUSPEND requested, epoint=0x%"PRIregister", cid=0x%"PRIregister,
+            epoint, cid);
+
+    return rc;
+}
+
 static int32_t do_psci_1_0_features(uint32_t psci_func_id)
 {
     /* /!\ Ordered by function ID and not name */
@@ -214,6 +267,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id)
     case PSCI_0_2_FN32_SYSTEM_OFF:
     case PSCI_0_2_FN32_SYSTEM_RESET:
     case PSCI_1_0_FN32_PSCI_FEATURES:
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
     case ARM_SMCCC_VERSION_FID:
         return 0;
     default:
@@ -344,6 +399,23 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
         return true;
     }
 
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
+    {
+        register_t epoint = PSCI_ARG(regs, 1);
+        register_t cid = PSCI_ARG(regs, 2);
+
+        if ( fid == PSCI_1_0_FN32_SYSTEM_SUSPEND )
+        {
+            epoint &= GENMASK(31, 0);
+            cid &= GENMASK(31, 0);
+        }
+
+        perfc_incr(vpsci_system_suspend);
+        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
+        return true;
+    }
+
     default:
         return false;
     }
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 104e917f07..e2371549a0 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -1349,16 +1349,10 @@ int domain_shutdown(struct domain *d, u8 reason)
     return 0;
 }
 
-void domain_resume(struct domain *d)
+static void domain_resume_nopause(struct domain *d)
 {
     struct vcpu *v;
 
-    /*
-     * Some code paths assume that shutdown status does not get reset under
-     * their feet (e.g., some assertions make this assumption).
-     */
-    domain_pause(d);
-
     spin_lock(&d->shutdown_lock);
 
     d->is_shutting_down = d->is_shut_down = 0;
@@ -1366,13 +1360,40 @@ void domain_resume(struct domain *d)
 
     for_each_vcpu ( d, v )
     {
+        /*
+         * No need to conditionally clear _VPF_suspended here:
+         * - This bit is only set on Arm, and only after a successful suspend.
+         * - domain_resume_nopause() may also be called from paths other than
+         *   the suspend/resume flow, such as "soft-reset" actions (e.g.,
+         *   on_poweroff), as part of the Xenstore control/shutdown protocol.
+         *   These require guest acknowledgement to complete the operation.
+         * So clearing the bit unconditionally is safe.
+         */
+        clear_bit(_VPF_suspended, &v->pause_flags);
+
         if ( v->paused_for_shutdown )
             vcpu_unpause(v);
         v->paused_for_shutdown = 0;
     }
 
     spin_unlock(&d->shutdown_lock);
+}
 
+#ifdef CONFIG_ARM
+void domain_resume_nopause_helper(struct domain *d)
+{
+    domain_resume_nopause(d);
+}
+#endif
+
+void domain_resume(struct domain *d)
+{
+    /*
+     * Some code paths assume that shutdown status does not get reset under
+     * their feet (e.g., some assertions make this assumption).
+     */
+    domain_pause(d);
+    domain_resume_nopause(d);
     domain_unpause(d);
 }
 
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index 02bdc256ce..12429d16b9 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -1014,6 +1014,9 @@ static inline struct domain *next_domain_in_cpupool(
 /* VCPU is parked. */
 #define _VPF_parked          8
 #define VPF_parked           (1UL<<_VPF_parked)
+/* VCPU is suspended. */
+#define _VPF_suspended       9
+#define VPF_suspended        (1UL << _VPF_suspended)
 
 static inline bool vcpu_runnable(const struct vcpu *v)
 {
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Anthony PERARD ,
	Juergen Gross 
Subject: [PATCH v10 2/4] tools/xl: Allow compilation of 'xl resume' command on Arm
Date: Thu, 28 Aug 2025 00:21:34 +0300
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From: Mykola Kvach 

The "xl resume" command was previously excluded from Arm builds because
system suspend/resume (e.g., SYSTEM_SUSPEND via vPSCI) was not
implemented. On x86, this command is used for resume.

This change enables compilation of `xl resume` on Arm regardless of the
underlying implementation status, making the tool available for testing
and future feature support. The relevant libxl infrastructure and handler
functions are already present and usable.

Note: This does not imply full system suspend/resume support on Arm.
      The `xl suspend` command still does not work on Arm platforms.

Signed-off-by: Mykola Kvach 
Acked-by: Anthony PERARD 
---
Changes in v7:
- dropped renaming of LIBXL_HAVE_NO_SUSPEND_RESUME macro

Changes in v6:
- Renamed macro from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND
  to better reflect the scope of this change
- Applied cosmetic changes based on review feedback
---
 tools/include/libxl.h     |  1 -
 tools/xl/xl.h             |  4 ++--
 tools/xl/xl_cmdtable.c    |  4 ++--
 tools/xl/xl_migrate.c     |  2 +-
 tools/xl/xl_saverestore.c |  2 +-
 tools/xl/xl_vmcontrol.c   | 12 ++++++------
 6 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/tools/include/libxl.h b/tools/include/libxl.h
index 185f74d8a8..b204fc5e2e 100644
--- a/tools/include/libxl.h
+++ b/tools/include/libxl.h
@@ -1140,7 +1140,6 @@ typedef struct libxl__ctx libxl_ctx;
  * restoring or migrating a domain. In this case the related functions
  * should be expected to return failure. That is:
  *  - libxl_domain_suspend
- *  - libxl_domain_resume
  *  - libxl_domain_remus_start
  */
 #if defined(__arm__) || defined(__aarch64__)
diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index 45745f0dbb..9233b73f85 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -65,7 +65,7 @@ static const char migrate_permission_to_go[]=
     "domain is yours, you are cleared to unpause";
 static const char migrate_report[]=
     "my copy unpause results are as follows";
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
   /* followed by one byte:
    *     0: everything went well, domain is running
@@ -130,8 +130,8 @@ int main_migrate_receive(int argc, char **argv);
 int main_save(int argc, char **argv);
 int main_migrate(int argc, char **argv);
 int main_suspend(int argc, char **argv);
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 int main_resume(int argc, char **argv);
-#endif
 int main_dump_core(int argc, char **argv);
 int main_pause(int argc, char **argv);
 int main_unpause(int argc, char **argv);
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 06a0039718..bcb2d233cc 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -198,12 +198,12 @@ const struct cmd_spec cmd_table[] = {
       "Suspend a domain to RAM",
       "",
     },
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "resume",
       &main_resume, 0, 1,
       "Resume a domain from RAM",
       "",
     },
-#endif
     { "dump-core",
       &main_dump_core, 0, 1,
       "Core dump a domain",
@@ -548,7 +548,7 @@ const struct cmd_spec cmd_table[] = {
       "                        checkpoint must be disabled.\n"
       "-p                      Use COLO userspace proxy."
     },
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "devd",
       &main_devd, 0, 1,
       "Daemon that listens for devices and launches backends",
diff --git a/tools/xl/xl_migrate.c b/tools/xl/xl_migrate.c
index b8594f44a5..4b4a379aa1 100644
--- a/tools/xl/xl_migrate.c
+++ b/tools/xl/xl_migrate.c
@@ -767,7 +767,7 @@ int main_remus(int argc, char **argv)
     close(send_fd);
     return EXIT_FAILURE;
 }
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 /*
diff --git a/tools/xl/xl_saverestore.c b/tools/xl/xl_saverestore.c
index 953d791d1a..747094ec7b 100644
--- a/tools/xl/xl_saverestore.c
+++ b/tools/xl/xl_saverestore.c
@@ -270,7 +270,7 @@ int main_save(int argc, char **argv)
     return EXIT_SUCCESS;
 }
 
-#endif /* LIBXL_HAVE_NO_SUSPEND_RESUME */
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 
diff --git a/tools/xl/xl_vmcontrol.c b/tools/xl/xl_vmcontrol.c
index c813732838..93766f631b 100644
--- a/tools/xl/xl_vmcontrol.c
+++ b/tools/xl/xl_vmcontrol.c
@@ -38,11 +38,6 @@ static void suspend_domain(uint32_t domid)
     libxl_domain_suspend_only(ctx, domid, NULL);
 }
 
-static void resume_domain(uint32_t domid)
-{
-    libxl_domain_resume(ctx, domid, 1, NULL);
-}
-
 int main_suspend(int argc, char **argv)
 {
     int opt;
@@ -55,6 +50,12 @@ int main_suspend(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
+
+static void resume_domain(uint32_t domid)
+{
+    libxl_domain_resume(ctx, domid, 1, NULL);
+}
 
 int main_resume(int argc, char **argv)
 {
@@ -68,7 +69,6 @@ int main_resume(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
-#endif
 
 static void pause_domain(uint32_t domid)
 {
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v10 4/4] CHANGELOG: Document guest suspend/resume to RAM support on Arm
Date: Thu, 28 Aug 2025 00:21:36 +0300
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From: Mykola Kvach 

Mention the newly added support for guest suspend and resume to/from
RAM via vPSCI on Arm platforms.

This support is limited to non-hardware domain guests.

Signed-off-by: Mykola Kvach 
Acked-by: Oleksii Kurochko 
---
Chnages in v6:
- removed reduntand explanation that thi support added for
  both arm32 and arm64.

Changes in v5:
- adjustments to the commit title and message
- expanded the changelog entry to include more context about
  suspend/resume support introduced in this patch series
---
 CHANGELOG.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index cd34ea87b8..7a75bd37cb 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -36,6 +36,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 
  - On Arm:
     - Ability to enable stack protector
+    - Support for guest suspend and resume to/from RAM via vPSCI.
+      Applies only to non-hardware domain guests.
 
 ### Removed
  - On x86:
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini 
Subject: [PATCH v10 3/4] SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
Date: Thu, 28 Aug 2025 00:21:35 +0300
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From: Mykola Kvach 

Add a new entry under the "Virtual Hardware, QEMU" section documenting
support for the optional PSCI SYSTEM_SUSPEND function exposed to guests.

This function is available via the virtual PSCI (vPSCI) interface and
allows guest domains (domUs) to initiate system suspend operations.

The feature is currently marked as "Tech Preview".

Signed-off-by: Mykola Kvach 
---
Changes in V10:
- Status of vPSCI SYSTEM_SUSPEND changed from "Experimental" to
  "Tech Preview"

Changes in v6:
- Dropped the generic guest PSCI support entry (merged in a separate patch)
- This patch now documents only the SYSTEM_SUSPEND optional function
- Reworded commit message to match the final form after rebase

Changes in v5:
- Dropped ARM/PSCI entry: this refers to internal use of PSCI SMC calls,
  which is not relevant for SUPPORT.md
- Added a dedicated entry for PSCI SYSTEM_SUSPEND instead of generic guest
  PSCI info; guest PSCI support was documented in a separate patch
---
 SUPPORT.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/SUPPORT.md b/SUPPORT.md
index 6a82a92189..0ce0903cb1 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -962,8 +962,9 @@ Emulated PSCI interface exposed to guests. We support all mandatory
 functions of PSCI 1.1. See below for the list of optional PSCI call
 implemented and their status.
 
-   Status, Mandatory: Supported
-   Status, MIGRATE_INFO_TYPE: Supported
+    Status, Mandatory: Supported
+    Status, MIGRATE_INFO_TYPE: Supported
+    Status, SYSTEM_SUSPEND: Tech Preview
 
 ## Virtual Hardware, QEMU
 
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Juergen Gross ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v10 0/4] Enable guest suspend/resume support on ARM via vPSCI
Date: Thu, 28 Aug 2025 00:21:32 +0300
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From: Mykola Kvach 

This patch series introduces the initial support for guest suspend
and resume on ARM platforms using the PSCI SYSTEM_SUSPEND interface. The main
goal is to allow ARM guests to request suspension using PSCI and be resumed
by the control domain (e.g., via "xl resume").

### Background

The PSCI SYSTEM_SUSPEND call is part of the PSCI v1.0+ specification and is
used by guests to enter the deepest possible power state. On Xen/ARM, we
emulate this interface in the virtual PSCI (vPSCI) layer for guests.

This series includes:

1. A new vPSCI implementation of the PSCI SYSTEM_SUSPEND function for guests
2. Documentation updates to SUPPORT.md to reflect PSCI and vPSCI support status
3. Enabling "xl resume" command compilation for ARM, which was previously disabled

### Usage

For Linux-based guests:
  - Suspend can be triggered using: "echo mem > /sys/power/state" or "systemctl suspend"
  - Resume can be performed from control domain using: "xl resume "

For more information, refer to the official Linux kernel documentation on power management.

Note that currently, SYSTEM_SUSPEND is supported only for guest domains (not for
the hardware domain).
---

This is the first part of previous patch series and originally consist only
with necessary changes needed for guest domain suspend.

The second part can be found here:
    https://patchew.org/Xen/cover.1754943874.git.mykola._5Fkvach@epam.com/

Changes in V10:
- An ARM-specific helper (domain_resume_nopause_helper)
- An isb() is added before p2m_save_state
- The is_64bit_domain check is dropped when masking the upper part of entry
  point and cid for SMC32 SYSTEM_SUSPEND PSCI calls
- Status of vPSCI SYSTEM_SUSPEND changed from "Experimental" to "Tech Preview"

Changes in V9:
- no functional changes
- enhance commit message and add extra comment to the code after review

Changes in V8:
- GIC and virtual timer context saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Main changes in V6:
- Skip execution of ctxt_switch_from for VCPUs in paused domains.
- Implement domain_resume_nopause
- Add a helper to determine if a VCPU is in suspended domain.
- Ignore upper 32 bits of arguments for 64-bit domains calling SMC32 SYSTEM_SUSPEND.
- Macro renamed from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND for clarity.
- Documentation now focuses only on the SYSTEM_SUSPEND function, with improved wording and structure.
- Changelog and commit messages refined for clarity and to remove redundant explanations.

Main change in V5:
  - Reverted the logic related to suspending domains. Instead of the standby
    mode introduced in v4, domains now resume execution at the point provided
    during suspend

The rest of the minor changes are described in the changelog of each commit.

Previous versions of this patch series:
  V1: https://lists.xenproject.org/archives/html/xen-devel/2018-11/msg01093.html
  V2: https://marc.info/?l=xen-devel&m=166514782207736&w=2
  V3: https://lists.xenproject.org/archives/html/xen-devel/2025-03/msg00168.html

Mykola Kvach (4):
  xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
  tools/xl: Allow compilation of 'xl resume' command on Arm
  SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
  CHANGELOG: Document guest suspend/resume to RAM support on Arm

 CHANGELOG.md                          |   2 +
 SUPPORT.md                            |   5 +-
 tools/include/libxl.h                 |   1 -
 tools/xl/xl.h                         |   4 +-
 tools/xl/xl_cmdtable.c                |   4 +-
 tools/xl/xl_migrate.c                 |   2 +-
 tools/xl/xl_saverestore.c             |   2 +-
 tools/xl/xl_vmcontrol.c               |  12 ++--
 xen/arch/arm/domain.c                 |  21 +++++-
 xen/arch/arm/include/asm/domain.h     |   2 +
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   2 +-
 xen/arch/arm/vpsci.c                  | 100 ++++++++++++++++++++++----
 xen/common/domain.c                   |  35 +++++++--
 xen/include/xen/sched.h               |   3 +
 16 files changed, 158 insertions(+), 40 deletions(-)

-- 
2.48.1



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Subject: Re: [PATCH] xen/arm: smmuv3: Add cache maintenance for non-coherent
 SMMU queues
Content-Language: en-GB
To: "Orzel, Michal" ,
 Dmytro Firsov ,
 "xen-devel@lists.xenproject.org" 
Cc: Bertrand Marquis ,
 Rahul Singh ,
 Stefano Stabellini ,
 Volodymyr Babchuk 
References: <24567cc1630b1577c33939ff71d67fb2ebe5572f.1754491424.git.dmytro_firsov@epam.com>
 
 <5d48d927-7e1e-4b11-b429-0b94259154ab@epam.com>
 
 <474bffdc-f42e-4727-ab69-b11a67430adf@amd.com>
From: Julien Grall 
In-Reply-To: <474bffdc-f42e-4727-ab69-b11a67430adf@amd.com>
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Hi Michal,

On 26/08/2025 12:44, Orzel, Michal wrote:
> 
> 
> On 26/08/2025 12:48, Julien Grall wrote:
>> Hi,
>>
>> On 26/08/2025 10:47, Dmytro Firsov wrote:
>>> On 22.08.25 11:12, Orzel, Michal wrote:
>>> On 06/08/2025 16:58, Dmytro Firsov wrote:
>>>
>>>
>>> According to the Arm SMMUv3 spec (ARM IHI 0070), a system may have
>>> SMMU(s) that is/are non-coherent to the PE (processing element). In such
>>> cases, memory accesses from the PE should be either non-cached or be
>>> augmented with manual cache maintenance. SMMU cache coherency is reported
>>> by bit 4 (COHACC) of the SMMU_IDR0 register and is already present in the
>>> Xen driver. However, the current implementation is not aware of cache
>>> maintenance for memory that is shared between the PE and non-coherent
>>> SMMUs. It contains dmam_alloc_coherent() function, that is added during
>>> Linux driver porting. But it is actually a wrapper for _xzalloc(), that
>>> returns normal writeback memory (which is OK for coherent SMMUs).
>>>
>>> During Xen bring-up on a system with non-coherent SMMUs, the driver did
>>> not work properly - the SMMU was not functional and halted initialization
>>> at the very beginning due to a timeout while waiting for CMD_SYNC
>>> completion:
>>>
>>>     (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
>>>     (XEN) SMMUv3: /soc/iommu@fa000000: CMD_SYNC timeout
>>>
>>> To properly handle such scenarios, add the non_coherent flag to the
>>> arm_smmu_queue struct. It is initialized using features reported by the
>>> SMMU HW and will be used for triggering cache clean/invalidate operations.
>>> This flag is not queue-specific (it is applicable to the whole SMMU), but
>>> adding it to arm_smmu_queue allows us to not change function signatures
>>> and simplify the patch (smmu->features, which contains the required flag,
>>> are not available in code parts that require cache maintenance).
>>>
>>>
>>> There are already a few places advertising the SMMU coherency:
>>> 1) smmu->features
>>> 2) d->iommu->features
>>> 3) platform_features
>>>
>>> All of them are better places than queue struct (that as you pointed out is not
>>> specific to coherency). I'd suggest maybe to use 3) and removing ro_after_init
>>> if you don't have access to 1) and 2). All in all, providing yet another place
>>> for coherency flag seems a bit too much.
>>   > >
>>> First of all, thank you very much for review! I will consider using
>>> "platform_features" in next patch version, it looks more appropriate and
>>> should be available within the whole driver. Also, I believe "ro_after_init"
>>> is also OK, since I have no need to change it (only check if cache
>>> maintenance should be performed).
>>
>> I have to disagree with using "platform_features". Flushing the queue is
>> a per-SMMU decision. But looking at the code, I think passing the SMMU
>> to the caller would look wrong (what if you mistakenly pass the wrong
>> SMMU?). So I think a boolean per queue is the right appraoch.
> For my own understanding: don't we consider SMMU coherency globally, not per
> SMMU (hence why I suggested re-using the global flag)?
 > We set the coherency> feature in the flags if all SMMUs support it. 
Do we want to diverge now and do
> the flushing per SMMU?

The two contexts are quite different.

We need the global flag when cleaning the stage-2 page-tables because we 
don't always know at boot which SMMUs will be used for the devices 
attached (think PCI hotplug).

In the context of this patch, we know the queue is only used by a given 
SMMU. So i tis better to take this decision per-SMMU/queue to reduce the 
number of cache flush. This will be particularly important for the 
2-stage SMMU work because there will be a lot of commands sent on behalf 
of the guest (every TLB flushes will be command).

Cheers,

-- 
Julien Grall



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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v4 03/12] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Topic: [PATCH v4 03/12] xen/arm: vgic: implement helper functions for
 virq checks
Thread-Index: AQHcF3/Hllj5Y0qHEkeemv3U6Hra1A==
Date: Wed, 27 Aug 2025 22:49:16 +0000
Message-ID: <87o6s01itx.fsf@epam.com>
References: 
	<65b148aea56b1a35fa061b0d8284584da97153a9.1756317702.git.leonid_komarianskyi@epam.com>
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 <65b148aea56b1a35fa061b0d8284584da97153a9.1756317702.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Wed, 27 Aug 2025 18:24:08 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> Introduced two new helper functions for vGIC: vgic_is_valid_line and
> vgic_is_spi. The functions are similar to the newly introduced
> gic_is_valid_line and gic_is_spi, but they verify whether a vIRQ
> is available for a specific domain, while GIC-specific functions
> validate INTIDs for the real GIC hardware. For example, the GIC may
> support all 992 SPI lines, but the domain may use only some part of them
> (e.g., 640), depending on the highest IRQ number defined in the domain
> configuration. Therefore, for vGIC-related code and checks, the
> appropriate functions should be used. Also, updated the appropriate
> checks to use these new helper functions.
>
> The purpose of introducing new helper functions for vGIC is essentially
> the same as for GIC: to avoid potential confusion with GIC-related
> checks and to consolidate similar code into separate functions, which
> can be more easily extended by additional conditions, e.g., when
> implementing extended SPI interrupts.
>
> Only the validation change in vgic_inject_irq may affect existing
> functionality, as it currently checks whether the vIRQ is less than or
> equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
> first SPI), the check should behave consistently with similar logic in
> other places and should check if the vIRQ number is less than
> vgic_num_irqs. The remaining changes, which replace open-coded checks
> with the use of these new helper functions, do not introduce any
> functional changes, as the helper functions follow the current vIRQ
> index verification logic.
>
> Signed-off-by: Leonid Komarianskyi 

Reviewed-by: Volodymyr Babchuk 

>
> ---
> Changes in V4:
> - removed redundant parentheses
>
> Changes in V3:
> - renamed vgic_is_valid_irq to vgic_is_valid_line and vgic_is_shared_irq
>   to vgic_is_spi
> - added vgic_is_valid_line implementation for new-vgic, because
>   vgic_is_valid_line is called from generic code. It is necessary to fix
>   the build for new-vgic.
> - updated commit message
>
> Changes in V2:
> - introduced this patch
> ---
>  xen/arch/arm/gic.c              |  3 +--
>  xen/arch/arm/include/asm/vgic.h |  7 +++++++
>  xen/arch/arm/irq.c              |  4 ++--
>  xen/arch/arm/vgic.c             | 10 ++++++++--
>  xen/arch/arm/vgic/vgic.c        |  5 +++++
>  5 files changed, 23 insertions(+), 6 deletions(-)
>
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index 9220eef6ea..b88237ccda 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -133,8 +133,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned=
 int virq,
> =20
>      ASSERT(spin_is_locked(&desc->lock));
>      /* Caller has already checked that the IRQ is an SPI */
> -    ASSERT(virq >=3D 32);
> -    ASSERT(virq < vgic_num_irqs(d));
> +    ASSERT(vgic_is_spi(d, virq));
>      ASSERT(!is_lpi(virq));
> =20
>      ret =3D vgic_connect_hw_irq(d, NULL, virq, desc, true);
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 35c0c6a8b0..3e7cbbb196 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -335,6 +335,13 @@ extern void vgic_check_inflight_irqs_pending(struct =
vcpu *v,
>  /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. =
*/
>  #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
> =20
> +extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
> +
> +static inline bool vgic_is_spi(struct domain *d, unsigned int virq)
> +{
> +    return virq >=3D NR_LOCAL_IRQS && vgic_is_valid_line(d, virq);
> +}
> +
>  /*
>   * Allocate a guest VIRQ
>   *  - spi =3D=3D 0 =3D> allocate a PPI. It will be the same on every vCP=
U
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index 7dd5a2a453..b8eccfc924 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -442,7 +442,7 @@ int route_irq_to_guest(struct domain *d, unsigned int=
 virq,
>      unsigned long flags;
>      int retval =3D 0;
> =20
> -    if ( virq >=3D vgic_num_irqs(d) )
> +    if ( !vgic_is_valid_line(d, virq) )
>      {
>          printk(XENLOG_G_ERR
>                 "the vIRQ number %u is too high for domain %u (max =3D %u=
)\n",
> @@ -560,7 +560,7 @@ int release_guest_irq(struct domain *d, unsigned int =
virq)
>      int ret;
> =20
>      /* Only SPIs are supported */
> -    if ( virq < NR_LOCAL_IRQS || virq >=3D vgic_num_irqs(d) )
> +    if ( !vgic_is_spi(d, virq) )
>          return -EINVAL;
> =20
>      desc =3D vgic_get_hw_irq_desc(d, NULL, virq);
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index c563ba93af..2bbf4d99aa 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -24,6 +24,12 @@
>  #include 
>  #include 
> =20
> +
> +bool vgic_is_valid_line(struct domain *d, unsigned int virq)
> +{
> +    return virq < vgic_num_irqs(d);
> +}
> +
>  static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>                                                    unsigned int rank)
>  {
> @@ -582,7 +588,7 @@ void vgic_inject_irq(struct domain *d, struct vcpu *v=
, unsigned int virq,
>      if ( !v )
>      {
>          /* The IRQ needs to be an SPI if no vCPU is specified. */
> -        ASSERT(virq >=3D 32 && virq <=3D vgic_num_irqs(d));
> +        ASSERT(vgic_is_spi(d, virq));
> =20
>          v =3D vgic_get_target_vcpu(d->vcpu[0], virq);
>      };
> @@ -659,7 +665,7 @@ bool vgic_emulate(struct cpu_user_regs *regs, union h=
sr hsr)
> =20
>  bool vgic_reserve_virq(struct domain *d, unsigned int virq)
>  {
> -    if ( virq >=3D vgic_num_irqs(d) )
> +    if ( !vgic_is_valid_line(d, virq) )
>          return false;
> =20
>      return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
> diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
> index 6cabd0496d..b2c0e1873a 100644
> --- a/xen/arch/arm/vgic/vgic.c
> +++ b/xen/arch/arm/vgic/vgic.c
> @@ -718,6 +718,11 @@ bool vgic_reserve_virq(struct domain *d, unsigned in=
t virq)
>      return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
>  }
> =20
> +bool vgic_is_valid_line(struct domain *d, unsigned int virq)
> +{
> +    return virq < vgic_num_irqs(d);
> +}
> +
>  int vgic_allocate_virq(struct domain *d, bool spi)
>  {
>      int first, end;

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v4 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Topic: [PATCH v4 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcF3/LXs7cVtiGJ0aCgPbYXhN1bw==
Date: Wed, 27 Aug 2025 22:55:15 +0000
Message-ID: <87iki81ijx.fsf@epam.com>
References: 
	<864522724dd6058952cad8b505b0589750b7f8d7.1756317702.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <864522724dd6058952cad8b505b0589750b7f8d7.1756317702.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Wed, 27 Aug 2025 18:24:13 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> Introduced appropriate register definitions, helper macros,
> and initialization of required GICv3.1 distributor registers
> to support eSPI. This type of interrupt is handled in the
> same way as regular SPI interrupts, with the following
> differences:
>
> 1) eSPIs can have up to 1024 interrupts, starting from the
> beginning of the range, whereas regular SPIs use INTIDs from
> 32 to 1019, totaling 988 interrupts;
> 2) eSPIs start at INTID 4096, necessitating additional interrupt
> index conversion during register operations.
>
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
>
> Signed-off-by: Leonid Komarianskyi 
> Reviewed-by: Volodymyr Babchuk 

With latest changes:

Reviewed-by: Volodymyr Babchuk 

>
> ---
> Changes in V4:
> - added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
>   for vGIC emulation
> - added a log banner with eSPI information, similar to the one for
>   regular SPI
> - added newline after ifdef and before gic_is_valid_line
> - added reviewed-by from Volodymyr Babchuk
>
> Changes in V3:
> - add __init attribute to gicv3_dist_espi_common_init
> - change open-codded eSPI register initialization to the appropriate
>   gen-mask macro
> - fixed formatting for lines with more than 80 symbols
> - introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
>   CONFIG_GICV3_ESPI disabled
> - renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
>   (name was taken from GIC specification) to avoid confusion
> - changed type for i variable to unsigned int since it cannot be
>   negative
>
> Changes in V2:
> - move gic_number_espis function from
>   [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
>   to use it in the newly introduced gic_is_valid_espi
> - add gic_is_valid_espi which checks if IRQ number is in supported
>   by HW eSPI range
> - update gic_is_valid_irq conditions to allow operations with eSPIs
>
> Changes for V4:
>
> Changes in V4:
> - added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
>   for vGIC emulation
> - added newline after ifdef and before gic_is_valid_line
> - added reviewed-by from Volodymyr Babchuk
> - added a log banner with eSPI information, similar to the one for
>   regular SPI

Looks like your changelog is doubled :)

> ---
>  xen/arch/arm/gic-v3.c                  | 82 ++++++++++++++++++++++++++
>  xen/arch/arm/include/asm/gic.h         | 22 +++++++
>  xen/arch/arm/include/asm/gic_v3_defs.h | 38 ++++++++++++
>  3 files changed, 142 insertions(+)
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index a959fefebe..b939a1f490 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_d=
esc *irqd, u32 offset)
>          default:
>              break;
>          }
> +#ifdef CONFIG_GICV3_ESPI
> +    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
> +    {
> +        u32 irq_index =3D ESPI_INTID2IDX(irqd->irq);
> +
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ICENABLER:
> +            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ISPENDR:
> +            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ICPENDR:
> +            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ISACTIVER:
> +            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICACTIVER:
> +            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTERnE + irq_index * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYRnE + irq_index);
> +        default:
> +            break;
> +        }
> +    }
> +#endif
>      default:
>          break;
>      }
> @@ -655,6 +685,54 @@ static void gicv3_set_irq_priority(struct irq_desc *=
desc,
>      spin_unlock(&gicv3.lock);
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +unsigned int gic_number_espis(void)
> +{
> +    return gic_hw_ops->info->nr_espi;
> +}
> +
> +static void __init gicv3_dist_espi_common_init(uint32_t type)
> +{
> +    unsigned int espi_nr, i;
> +
> +    espi_nr =3D min(1024U, GICD_TYPER_ESPIS_NUM(type));
> +    gicv3_info.nr_espi =3D espi_nr;
> +    /* The GIC HW doesn't support eSPI, so we can leave from here */
> +    if ( gicv3_info.nr_espi =3D=3D 0 )
> +        return;
> +
> +    printk("GICv3: %d eSPI lines\n", gicv3_info.nr_espi);
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 16 )
> +        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 4 )
> +        writel_relaxed(GIC_PRI_IRQ_ALL,
> +                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 32 )
> +    {
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i / 32=
) * 4);
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i / 32=
) * 4);
> +    }
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 32 )
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) =
* 4);
> +}
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
> +{
> +    unsigned int i;
> +
> +    for ( i =3D 0; i < gicv3_info.nr_espi; i++ )
> +        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * =
8);
> +}
> +#else
> +static void __init gicv3_dist_espi_common_init(uint32_t type) { }
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
> +#endif
> +
>  static void __init gicv3_dist_init(void)
>  {
>      uint32_t type;
> @@ -700,6 +778,8 @@ static void __init gicv3_dist_init(void)
>      for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i +=3D 32 )
>          writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * =
4);
> =20
> +    gicv3_dist_espi_common_init(type);
> +
>      gicv3_dist_wait_for_rwp();
> =20
>      /* Turn on the distributor */
> @@ -713,6 +793,8 @@ static void __init gicv3_dist_init(void)
> =20
>      for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
>          writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8)=
;
> +
> +    gicv3_dist_espi_init_aff(affinity);
>  }
> =20
>  static int gicv3_enable_redist(void)
> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gi=
c.h
> index 3fcee42675..1e747dcd99 100644
> --- a/xen/arch/arm/include/asm/gic.h
> +++ b/xen/arch/arm/include/asm/gic.h
> @@ -306,8 +306,26 @@ extern void gic_dump_vgic_info(struct vcpu *v);
> =20
>  /* Number of interrupt lines */
>  extern unsigned int gic_number_lines(void);
> +#ifdef CONFIG_GICV3_ESPI
> +extern unsigned int gic_number_espis(void);
> +
> +static inline bool gic_is_valid_espi(unsigned int irq)
> +{
> +    return (irq >=3D ESPI_BASE_INTID &&
> +            irq < ESPI_IDX2INTID(gic_number_espis()));
> +}
> +#else
> +static inline bool gic_is_valid_espi(unsigned int irq)
> +{
> +    return false;
> +}
> +#endif
> +
>  static inline bool gic_is_valid_line(unsigned int irq)
>  {
> +    if ( gic_is_valid_espi(irq) )
> +        return true;
> +
>      return irq < gic_number_lines();
>  }
> =20
> @@ -325,6 +343,10 @@ struct gic_info {
>      enum gic_version hw_version;
>      /* Number of GIC lines supported */
>      unsigned int nr_lines;
> +#ifdef CONFIG_GICV3_ESPI
> +    /* Number of GIC eSPI supported */
> +    unsigned int nr_espi;
> +#endif
>      /* Number of LR registers */
>      uint8_t nr_lrs;
>      /* Maintenance irq number */
> diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/includ=
e/asm/gic_v3_defs.h
> index 2af093e774..c10db9bd05 100644
> --- a/xen/arch/arm/include/asm/gic_v3_defs.h
> +++ b/xen/arch/arm/include/asm/gic_v3_defs.h
> @@ -37,6 +37,44 @@
>  #define GICD_IROUTER1019             (0x7FD8)
>  #define GICD_PIDR2                   (0xFFE8)
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/* Additional registers for GICv3.1 */
> +#define GICD_IGROUPRnE               (0x1000)
> +#define GICD_IGROUPRnEN              (0x107C)
> +#define GICD_ISENABLERnE             (0x1200)
> +#define GICD_ISENABLERnEN            (0x127C)
> +#define GICD_ICENABLERnE             (0x1400)
> +#define GICD_ICENABLERnEN            (0x147C)
> +#define GICD_ISPENDRnE               (0x1600)
> +#define GICD_ISPENDRnEN              (0x167C)
> +#define GICD_ICPENDRnE               (0x1800)
> +#define GICD_ICPENDRnEN              (0x187C)
> +#define GICD_ISACTIVERnE             (0x1A00)
> +#define GICD_ISACTIVERnEN            (0x1A7C)
> +#define GICD_ICACTIVERnE             (0x1C00)
> +#define GICD_ICACTIVERnEN            (0x1C7C)
> +#define GICD_IPRIORITYRnE            (0x2000)
> +#define GICD_IPRIORITYRnEN           (0x23FC)
> +#define GICD_ICFGRnE                 (0x3000)
> +#define GICD_ICFGRnEN                (0x30FC)
> +#define GICD_IGRPMODRnE              (0x3400)
> +#define GICD_IGRPMODRnEN             (0x347C)
> +#define GICD_NSACRnE                 (0x3600)
> +#define GICD_NSACRnEN                (0x36FC)
> +#define GICD_IROUTERnE               (0x8000)
> +#define GICD_IROUTERnEN              (0x9FFC)
> +
> +#define GICD_TYPER_ESPI_SHIFT        8
> +#define GICD_TYPER_ESPI_RANGE_SHIFT  27
> +#define GICD_TYPER_ESPI_RANGE_MASK   (0x1F)
> +#define GICD_TYPER_ESPI              (1U << GICD_TYPER_ESPI_SHIFT)
> +#define GICD_TYPER_ESPI_RANGE(espi_range) ((((espi_range) & \
> +        GICD_TYPER_ESPI_RANGE_MASK) + 1) * 32)
> +#define GICD_TYPER_ESPIS_NUM(typer)    \
> +        (((typer) & GICD_TYPER_ESPI) ? \
> +        GICD_TYPER_ESPI_RANGE((typer) >> GICD_TYPER_ESPI_RANGE_SHIFT) : =
0)
> +#endif
> +
>  /* Common between GICD_PIDR2 and GICR_PIDR2 */
>  #define GIC_PIDR2_ARCH_MASK         (0xf0)
>  #define GIC_PIDR2_ARCH_GICv3        (0x30)

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v4 08/12] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Topic: [PATCH v4 08/12] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcF3/OB02ss8SP00K1+48v78FFnQ==
Date: Wed, 27 Aug 2025 23:01:59 +0000
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Hi Leonid,

Leonid Komarianskyi  writes:

> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
> requested by the guest. A new field, ext_shared_irqs, is added
> to the VGIC structure to store information about eSPIs, similar
> to how shared_irqs is used for regular SPIs.
>
> Since the eSPI range starts at INTID 4096 and INTIDs between 1025
> and 4095 are reserved, helper macros are introduced to simplify the
> transformation of indices and to enable easier access to eSPI-specific
> resources. These changes prepare the VGIC for processing eSPIs as
> required by future functionality.
>
> The initialization and deinitialization paths for vgic have been updated
> to allocate and free these resources appropriately. Additionally,
> updated handling of INTIDs greater than 1024, passed from the toolstack
> during domain creation, and verification logic ensures only valid SPI or
> eSPI INTIDs are used.
>
> The existing SPI behavior remains unaffected when guests do not request
> eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
> option is disabled.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V4:
> - added has_espi field to simplify determining whether a domain is able
>   to operate with eSPI

I don't think that this is a good idea. You already have an invariant that
tells if domain has eSPIs: d->nr_espis !=3D 0. If you introduce a new
field, you now have to keep these two values coherent or deal with possible=
 cases
like d->nr_espis =3D=3D 0 && d->has_espi =3D=3D true

Also, this new field is not used anywhere, so why adding it in the first
place?

> - fixed formatting issues and misspellings
>
> Changes in V3:
> - fixed formatting for lines with more than 80 symbols
> - introduced helper functions to be able to use stubs in case of
>   CONFIG_GICV3_ESPI disabled, and as a result, reduce the number of
>   #ifdefs
> - fixed checks for nr_spis in domain_vgic_init
> - updated comment about nr_spis adjustments with dom0less mention
> - moved comment with additional explanations before checks
> - used unsigned int for indexes since they cannot be negative
> - removed unnecessary parentheses
> - move vgic_ext_rank_offset to the below ifdef guard, to reduce the
>   number of ifdefs
>
> Changes in V2:
> - change is_espi_rank to is_valid_espi_rank to verify whether the array
>   element ext_shared_irqs exists. The previous version, is_espi_rank,
>   only checked if the rank index was less than the maximum possible eSPI
>   rank index, but this could potentially result in accessing a
>   non-existing array element. To address this, is_valid_espi_rank was
>   introduced, which ensures that the required eSPI rank exists
> - move gic_number_espis to
>   xen/arm: gicv3: implement handling of GICv3.1 eSPI
> - update vgic_is_valid_irq checks to allow operating with eSPIs
> - remove redundant newline in vgic_allocate_virq
> ---
>  xen/arch/arm/include/asm/vgic.h |  20 +++
>  xen/arch/arm/vgic.c             | 213 +++++++++++++++++++++++++++++++-
>  2 files changed, 230 insertions(+), 3 deletions(-)
>
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 3e7cbbb196..fb4cea73eb 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -146,6 +146,12 @@ struct vgic_dist {
>      int nr_spis; /* Number of SPIs */
>      unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
>      struct vgic_irq_rank *shared_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +    struct vgic_irq_rank *ext_shared_irqs;
> +    int nr_espis; /* Number of extended SPIs */
> +    /* To simplify determining whether a domain is able to operate with =
eSPI */
> +    bool has_espi;
> +#endif
>      /*
>       * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
>       * struct arch_vcpu.
> @@ -243,6 +249,14 @@ struct vgic_ops {
>  /* Number of ranks of interrupt registers for a domain */
>  #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
> +#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
> +#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
> +#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
> +#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
> +#endif
> +
>  #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
>  #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
> =20
> @@ -302,6 +316,12 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct=
 vcpu *v,
>                                                unsigned int b,
>                                                unsigned int n,
>                                                unsigned int s);
> +#ifdef CONFIG_GICV3_ESPI
> +extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
> +                                                  unsigned int b,
> +                                                  unsigned int n,
> +                                                  unsigned int s);
> +#endif
>  extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int =
irq);
>  extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n=
);
>  extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n)=
;
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 2bbf4d99aa..f4b80cb05f 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -27,9 +27,82 @@
> =20
>  bool vgic_is_valid_line(struct domain *d, unsigned int virq)
>  {
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( virq >=3D ESPI_BASE_INTID &&
> +         virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
> +        return true;
> +#endif
> +
>      return virq < vgic_num_irqs(d);
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * Since eSPI indexes start from 4096 and numbers from 1024 to
> + * 4095 are forbidden, we need to check both lower and upper
> + * limits for ranks.
> + */
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int ran=
k)
> +{
> +    return rank >=3D EXT_RANK_MIN &&
> +           EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d);
> +}
> +
> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
> +                                                       unsigned int rank=
)
> +{
> +    return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)]=
;
> +}
> +
> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int=
 virq)
> +{
> +    return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d),
> +                             d->arch.vgic.allocated_irqs);
> +}
> +
> +static void arch_move_espis(struct vcpu *v)
> +{
> +    const cpumask_t *cpu_mask =3D cpumask_of(v->processor);
> +    struct domain *d =3D v->domain;
> +    struct pending_irq *p;
> +    struct vcpu *v_target;
> +    unsigned int i;
> +
> +    for ( i =3D ESPI_BASE_INTID;
> +          i < EXT_RANK_IDX2NUM(d->arch.vgic.nr_espis); i++ )
> +    {
> +        v_target =3D vgic_get_target_vcpu(v, i);
> +        p =3D irq_to_pending(v_target, i);
> +
> +        if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-=
>status) )
> +            irq_set_affinity(p->desc, cpu_mask);
> +    }
> +}
> +#else
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int ran=
k)
> +{
> +    return false;
> +}
> +
> +/*
> + * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn=
,
> + * because in this case, is_valid_espi_rank will always return false.
> + */
> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
> +                                                       unsigned int rank=
)
> +{
> +    ASSERT_UNREACHABLE();
> +    return NULL;
> +}
> +
> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int=
 virq)
> +{
> +    return false;
> +}
> +
> +static void arch_move_espis(struct vcpu *v) { }
> +#endif
> +
>  static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>                                                    unsigned int rank)
>  {
> @@ -37,6 +110,8 @@ static inline struct vgic_irq_rank *vgic_get_rank(stru=
ct vcpu *v,
>          return v->arch.vgic.private_irqs;
>      else if ( rank <=3D DOMAIN_NR_RANKS(v->domain) )
>          return &v->domain->arch.vgic.shared_irqs[rank - 1];
> +    else if ( is_valid_espi_rank(v->domain, rank) )
> +        return vgic_get_espi_rank(v, rank);
>      else
>          return NULL;
>  }
> @@ -117,6 +192,74 @@ int domain_vgic_register(struct domain *d, unsigned =
int *mmio_count)
>      return 0;
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * The function behavior is the same as for regular SPIs (vgic_rank_offs=
et),
> + * but it operates with extended SPI ranks.
> + */
> +struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int =
b,
> +                                           unsigned int n, unsigned int =
s)
> +{
> +    unsigned int rank =3D REG_RANK_NR(b, (n >> s));
> +
> +    return vgic_get_rank(v, rank + EXT_RANK_MIN);
> +}
> +
> +static unsigned int vgic_num_spi_lines(struct domain *d)
> +{
> +    return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
> +}
> +
> +static int init_vgic_espi(struct domain *d)
> +{
> +    unsigned int i, idx;
> +
> +    if ( d->arch.vgic.nr_espis =3D=3D 0 )
> +        return 0;
> +
> +    d->arch.vgic.ext_shared_irqs =3D
> +        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
> +    if ( d->arch.vgic.ext_shared_irqs =3D=3D NULL )
> +        return -ENOMEM;
> +
> +    for ( i =3D d->arch.vgic.nr_spis, idx =3D 0;
> +          i < vgic_num_spi_lines(d); i++, idx++ )
> +        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i],
> +                              ESPI_IDX2INTID(idx));
> +
> +    for ( i =3D 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
> +        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
> +
> +    return 0;
> +}
> +
> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
> +{
> +    irq =3D ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
> +    return &d->arch.vgic.pending_irqs[irq];
> +}
> +#else
> +static unsigned int init_vgic_espi(struct domain *d)
> +{
> +    return 0;
> +}
> +
> +static unsigned int vgic_num_spi_lines(struct domain *d)
> +{
> +    return d->arch.vgic.nr_spis;
> +}
> +
> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
> +{
> +    return NULL;
> +}
> +#endif
> +
> +static unsigned int vgic_num_alloc_irqs(struct domain *d)
> +{
> +    return vgic_num_spi_lines(d) + NR_LOCAL_IRQS;
> +}
> +
>  int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>  {
>      int i;
> @@ -131,6 +274,38 @@ int domain_vgic_init(struct domain *d, unsigned int =
nr_spis)
>       */
>      nr_spis =3D ROUNDUP(nr_spis, 32);
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    /*
> +     * During domain creation, the dom0less DomUs code or toolstack spec=
ifies
> +     * the maximum INTID, which is defined in the domain config subtract=
ed by
> +     * 32 to cover the local IRQs (please see the comment to VGIC_DEF_NR=
_SPIS).
> +     * To compute the actual number of eSPI that will be usable for,
> +     * add back 32.
> +     */
> +    if ( nr_spis + 32 > ESPI_IDX2INTID(NR_ESPI_IRQS) )
> +        return -EINVAL;
> +
> +    if ( nr_spis + 32 >=3D ESPI_BASE_INTID )
> +    {
> +        d->arch.vgic.nr_espis =3D min(nr_spis - ESPI_BASE_INTID + 32, 10=
24U);
> +        /* Verify if GIC HW can handle provided INTID */
> +        if ( d->arch.vgic.nr_espis > gic_number_espis() )
> +            return -EINVAL;
> +        /*
> +         * Set the maximum available number for regular
> +         * SPI to pass the next check
> +         */
> +        nr_spis =3D VGIC_DEF_NR_SPIS;
> +        d->arch.vgic.has_espi =3D true;
> +    }
> +    else
> +    {
> +        /* Domain will use the regular SPI range */
> +        d->arch.vgic.nr_espis =3D 0;
> +        d->arch.vgic.has_espi =3D false;
> +    }
> +#endif
> +
>      /* Limit the number of virtual SPIs supported to (1020 - 32) =3D 988=
  */
>      if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
>          return -EINVAL;
> @@ -145,7 +320,7 @@ int domain_vgic_init(struct domain *d, unsigned int n=
r_spis)
>          return -ENOMEM;
> =20
>      d->arch.vgic.pending_irqs =3D
> -        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
> +        xzalloc_array(struct pending_irq, vgic_num_spi_lines(d));
>      if ( d->arch.vgic.pending_irqs =3D=3D NULL )
>          return -ENOMEM;
> =20
> @@ -156,12 +331,16 @@ int domain_vgic_init(struct domain *d, unsigned int=
 nr_spis)
>      for ( i =3D 0; i < DOMAIN_NR_RANKS(d); i++ )
>          vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
> =20
> +    ret =3D init_vgic_espi(d);
> +    if ( ret )
> +        return ret;
> +
>      ret =3D d->arch.vgic.handler->domain_init(d);
>      if ( ret )
>          return ret;
> =20
>      d->arch.vgic.allocated_irqs =3D
> -        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
> +        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_alloc_irqs(d=
)));
>      if ( !d->arch.vgic.allocated_irqs )
>          return -ENOMEM;
> =20
> @@ -195,9 +374,27 @@ void domain_vgic_free(struct domain *d)
>          }
>      }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i =3D 0; i < d->arch.vgic.nr_espis; i++ )
> +    {
> +        struct pending_irq *p =3D spi_to_pending(d, ESPI_IDX2INTID(i));
> +
> +        if ( p->desc )
> +        {
> +            ret =3D release_guest_irq(d, p->irq);
> +            if ( ret )
> +                dprintk(XENLOG_G_WARNING, "d%u: Failed to release virq %=
u ret =3D %d\n",
> +                        d->domain_id, p->irq, ret);
> +        }
> +    }
> +#endif
> +
>      if ( d->arch.vgic.handler )
>          d->arch.vgic.handler->domain_free(d);
>      xfree(d->arch.vgic.shared_irqs);
> +#ifdef CONFIG_GICV3_ESPI
> +    xfree(d->arch.vgic.ext_shared_irqs);
> +#endif
>      xfree(d->arch.vgic.pending_irqs);
>      xfree(d->arch.vgic.allocated_irqs);
>  }
> @@ -331,6 +528,8 @@ void arch_move_irqs(struct vcpu *v)
>          if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-=
>status) )
>              irq_set_affinity(p->desc, cpu_mask);
>      }
> +
> +    arch_move_espis(v);
>  }
> =20
>  void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
> @@ -538,6 +737,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v, un=
signed int irq)
>          n =3D &v->arch.vgic.pending_irqs[irq];
>      else if ( is_lpi(irq) )
>          n =3D v->domain->arch.vgic.handler->lpi_to_pending(v->domain, ir=
q);
> +    else if ( is_espi(irq) )
> +        n =3D espi_to_pending(v->domain, irq);
>      else
>          n =3D &v->domain->arch.vgic.pending_irqs[irq - 32];
>      return n;
> @@ -547,6 +748,9 @@ struct pending_irq *spi_to_pending(struct domain *d, =
unsigned int irq)
>  {
>      ASSERT(irq >=3D NR_LOCAL_IRQS);
> =20
> +    if ( is_espi(irq) )
> +        return espi_to_pending(d, irq);
> +
>      return &d->arch.vgic.pending_irqs[irq - 32];
>  }
> =20
> @@ -668,6 +872,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned int=
 virq)
>      if ( !vgic_is_valid_line(d, virq) )
>          return false;
> =20
> +    if ( is_espi(virq) )
> +        return vgic_reserve_espi_virq(d, virq);
> +
>      return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
>  }
> =20
> @@ -685,7 +892,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
>      else
>      {
>          first =3D 32;
> -        end =3D vgic_num_irqs(d);
> +        end =3D vgic_num_alloc_irqs(d);
>      }
> =20
>      /*

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v4 09/12] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Topic: [PATCH v4 09/12] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Index: AQHcF3/PBFIJhCUS+Eih9nfOZZJmpg==
Date: Wed, 27 Aug 2025 23:03:37 +0000
Message-ID: <877byo1i5y.fsf@epam.com>
References: 
	<66b39c4ba25e7a19beeca62ab23f5d3ab3cbae52.1756317702.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <66b39c4ba25e7a19beeca62ab23f5d3ab3cbae52.1756317702.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Wed, 27 Aug 2025 18:24:21 +0000")
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Hi Loenid,

Leonid Komarianskyi  writes:

> The Dom0 and DomUs logic for the dom0less configuration in create_dom0() =
and
> arch_create_domUs() has been updated to account for extended SPIs when
> supported by the hardware and enabled with CONFIG_GICV3_ESPI. These chang=
es
> ensure the proper calculation of the maximum number of SPIs and eSPIs ava=
ilable
> to Dom0 and DomUs in dom0less setups.
>
> When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is enabled=
, the
> maximum number of eSPI interrupts is calculated using the ESPI_BASE_INTID
> offset (4096) and is limited to 1024, with 32 IRQs subtracted. To ensure
> compatibility with non-Dom0 domains, this adjustment is applied by the
> toolstack during domain creation, while for Dom0 or DomUs in Dom0, it is
> handled directly during VGIC initialization. If eSPIs are not supported, =
the
> calculation defaults to using the standard SPI range, with a maximum valu=
e of
> 992 interrupt lines, as it works currently.
>
> Signed-off-by: Leonid Komarianskyi 

Reviewed-by: Volodymyr Babchuk 

>
> ---
> Changes in V4:
> - consolidated the eSPI and SPI logic into a new inline function,
>   vgic_def_nr_spis. Without eSPI support (either due to config being
>   disabled or hardware not supporting it), it will return the regular SPI
>   range, as it works currently. There are no functional changes compared
>   with the previous patch version
> - removed VGIC_DEF_MAX_SPI macro, to reduce the number of ifdefs
>
> Changes in V3:
> - renamed macro VGIC_DEF_NR_ESPIS to more appropriate VGIC_DEF_MAX_SPI
> - added eSPI initialization for dom0less setups
> - fixed comment with mentions about dom0less builds
> - fixed formatting for lines with more than 80 symbols
> - updated commit message
>
> Changes in V2:
> - no changes
> ---
>  xen/arch/arm/dom0less-build.c   |  2 +-
>  xen/arch/arm/domain_build.c     |  2 +-
>  xen/arch/arm/include/asm/vgic.h | 21 +++++++++++++++++++++
>  3 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.=
c
> index 69b9ea22ce..02d5559102 100644
> --- a/xen/arch/arm/dom0less-build.c
> +++ b/xen/arch/arm/dom0less-build.c
> @@ -285,7 +285,7 @@ void __init arch_create_domUs(struct dt_device_node *=
node,
>      {
>          int vpl011_virq =3D GUEST_VPL011_SPI;
> =20
> -        d_cfg->arch.nr_spis =3D VGIC_DEF_NR_SPIS;
> +        d_cfg->arch.nr_spis =3D vgic_def_nr_spis();
> =20
>          /*
>           * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index d91a71acfd..39eea0be00 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -2054,7 +2054,7 @@ void __init create_dom0(void)
> =20
>      /* The vGIC for DOM0 is exactly emulating the hardware GIC */
>      dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
> -    dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS;
> +    dom0_cfg.arch.nr_spis =3D vgic_def_nr_spis();
>      dom0_cfg.arch.tee_type =3D tee_get_type();
>      dom0_cfg.max_vcpus =3D dom0_max_vcpus();
> =20
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index fb4cea73eb..11f9d216eb 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -355,6 +355,27 @@ extern void vgic_check_inflight_irqs_pending(struct =
vcpu *v,
>  /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. =
*/
>  #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
> =20
> +static inline unsigned int vgic_def_nr_spis(void)
> +{
> +#ifdef CONFIG_GICV3_ESPI
> +    /*
> +     * Check if the hardware supports extended SPIs (even if the appropr=
iate
> +     * config is set). If not, the common SPI range will be used. Otherw=
ise
> +     * returns the maximum eSPI INTID, supported by HW GIC, subtracted b=
y 32.
> +     * For non-Dom0 domains, the toolstack or arch_create_domUs function
> +     * applies the same adjustment to cover local IRQs (please, see comm=
ent
> +     * for macro that is used for regular SPIs - VGIC_DEF_NR_SPIS). We w=
ill
> +     * add back this value during VGIC initialization. This ensures cons=
istent
> +     * handling for Dom0 and other domains. For the regular SPI range in=
terrupts
> +     * in this case, the maximum value of VGIC_DEF_NR_SPIS will be used.
> +     */
> +    if ( gic_number_espis() > 0 )
> +        return ESPI_BASE_INTID + min(gic_number_espis(), 1024U) - 32;
> +#endif
> +
> +    return VGIC_DEF_NR_SPIS;
> +}
> +
>  extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
> =20
>  static inline bool vgic_is_spi(struct domain *d, unsigned int virq)

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Anthony PERARD
	
Subject: Re: [PATCH v4 11/12] doc/man: update description for nr_spis with
 eSPI
Thread-Topic: [PATCH v4 11/12] doc/man: update description for nr_spis with
 eSPI
Thread-Index: AQHcF4DXobE1p0eyakyyCN/Uk7KDQg==
Date: Wed, 27 Aug 2025 23:20:04 +0000
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References: 
	<50cd1899b328e82bd517ae0dd0e400e9cfee0999.1756317702.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <50cd1899b328e82bd517ae0dd0e400e9cfee0999.1756317702.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Wed, 27 Aug 2025 18:24:24 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> Since eSPI support has been introduced, update the documentation with
> the appropriate description.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V4:
> - introduced this patch
> ---
>  docs/man/xl.cfg.5.pod.in | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
> index 5362fb0e9a..292ab10331 100644
> --- a/docs/man/xl.cfg.5.pod.in
> +++ b/docs/man/xl.cfg.5.pod.in
> @@ -3072,11 +3072,14 @@ interval of colors (such as "0-4").
>  =3Ditem B
> =20
>  An optional integer parameter specifying the number of SPIs (Shared
> -Peripheral Interrupts) to allocate for the domain. Max is 960 SPIs. If
> -the `nr_spis` parameter is not specified, the value calculated by the to=
olstack
> -will be used for the domain. Otherwise, the value specified by the `nr_s=
pis`
> -parameter will be used. The number of SPIs should match the highest inte=
rrupt
> -ID that will be assigned to the domain.
> +Peripheral Interrupts) to allocate for the domain. Max is 960 for regula=
r SPIs
> +or 5088 for eSPIs (Extended SPIs). The eSPIs includes an additional 1024=
 SPIs

Well, this is awkward and confusing now. You can't allocate 5088 SPIs,
because no GIC does not support this. Number of SPIs is
960 (regular SPIs) + 1024 (eSPIs) =3D 1984.

What you are describing is "max SPI number", but the parameter is called
"nr_spis". If we want to leave things consistent, we either need to
deprecate nr_spis in favor of max_spi_nr, or severely rework nr_spi
logic, so it can have values from 0 to 1984...

Personally, I'd prefer max_spi_nr approach, because it will be less
confusing for a user. I am curios what ARM maintainers think about this.


> +from the eSPI range (4096 to 5119) if the hardware supports extended SPI=
s
> +(GICv3.1+) and CONFIG_GICV3_ESPI is enabled. If the `nr_spis` parameter =
is not
> +specified, the value calculated by the toolstack will be used for the do=
main.
> +Otherwise, the value specified by the `nr_spis` parameter will be used. =
The
> +number of SPIs should match the highest interrupt ID that will be assign=
ed to
> +the domain.
> =20
>  =3Ditem B

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mykola
 Kvach , Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Andrew Cooper
	, Anthony PERARD , Jan
 Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: Re: [PATCH v10 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
Thread-Topic: [PATCH v10 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
Thread-Index: AQHcF5jU8coYEy0ljUKI31cktWj1qA==
Date: Wed, 27 Aug 2025 23:41:07 +0000
Message-ID: <87ms7kz625.fsf@epam.com>
References: 
	<55ff99acd69f9eaf20f077e6b453b54931b541d4.1756329091.git.mykola_kvach@epam.com>
In-Reply-To:
 <55ff99acd69f9eaf20f077e6b453b54931b541d4.1756329091.git.mykola_kvach@epam.com>
	(Mykola Kvach's message of "Thu, 28 Aug 2025 00:21:33 +0300")
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Hi Mykola,

Mykola Kvach  writes:

> From: Mykola Kvach 
>
> Add support for the PSCI SYSTEM_SUSPEND function in the vPSCI interface,
> allowing guests to request suspend via the PSCI v1.0 SYSTEM_SUSPEND call
> (both 32-bit and 64-bit variants).
>
> Implementation details:
> - Add SYSTEM_SUSPEND function IDs to PSCI definitions
> - Trap and handle SYSTEM_SUSPEND in vPSCI
> - Allow only non-hardware domains to invoke SYSTEM_SUSPEND; return
>   PSCI_NOT_SUPPORTED for the hardware domain to avoid halting the system
>   in hwdom_shutdown() via domain_shutdown
> - Require all secondary VCPUs of the calling domain to be offline before
>   suspend, as mandated by the PSCI specification
>
> Additionally, GIC context must be saved when a domain suspends.
> LRs are not architecturally preserved across suspend/resume or context
> switches, so Xen must explicitly save and restore them. This requirement
> is specified in the PSCI specification (DEN0022F.b, section 6.8 "Preservi=
ng
> the execution context"). The fix is implemented by moving the respective
> code in ctxt_switch_from() before the return path taken when the domain
> suspends.
>
> Introduce domain_resume_nopause/_helper() to allow resuming a domain from
> SYSTEM_SUSPEND without pausing it first. This avoids problematic
> domain_pause() calls when resuming from suspend on Arm, particularly in e=
rror
> paths. The helper is Arm-specific; other architectures continue to use th=
e
> original domain_resume().
>
> Usage:
>
> For Linux-based guests, suspend can be initiated with:
>     echo mem > /sys/power/state
> or via:
>     systemctl suspend
>
> Resuming the guest is performed from control domain using:
>       xl resume 
>
> Signed-off-by: Mykola Kvach 
> ---
> Changes in V10:
> - small changes to the commit message reflect updates introduced in this
>   version of the patch.
> - Comments are improved, clarified, and expanded, especially regarding PS=
CI
>   requirements and context handling.
> - An ARM-specific helper (domain_resume_nopause_helper)
> - gprintk() and PRIregister are used for logging in vPSCI code.
> - An isb() is added before p2m_save_state
> - The is_64bit_domain check is dropped when masking the upper part of ent=
ry
>   point and cid for SMC32 SYSTEM_SUSPEND PSCI calls
>
> Changes in V9:
> - no functional changes
> - cosmetic chnages after review
> - enhance commit message and add extra comment to the code after review
>
> Changes in V8:
> - GIC and virtual timer context must be saved when the domain suspends
> - rework locking
> - minor changes after code review
>
> Changes in V7:
> - add proper locking
> - minor changes after code review
>
> Changes in V6:
> - skip execution of ctxt_switch_from for vcpu that is in paused domain
> - add implementation of domain_resume without domain_pause
> - add helper function to determine if vcpu is suspended or not
> - ignore upper 32 bits of argument values when the domain is 64-bit
>   and calls the SMC32 SYSTEM_SUSPEND function
> - cosmetic changes after review
>
> Changes in V5:
> - don't use standby mode, restore execution in a provided by guest point
> - move checking that all CPUs, except current one, are offline to after
>   pausing the vCPUs
> - provide ret status from arch_domain_shutdown and handle it in
>   domain_shutdown
> - adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI functio=
ns
>
> Changes in V4:
> Dropped all changes related to watchdog, domain is marked as shutting
> down in domain_shutdown and watchdog timeout handler won't trigger
> because of it.
>
> Previous versions included code to manage Xen watchdog timers during susp=
end,
> but this was removed. When a guest OS starts the Xen watchdog (either via=
 the
> kernel driver or xenwatchdogd), it is responsible for managing that state
> across suspend/resume. On Linux, the Xen kernel driver properly stops the
> watchdog during suspend. However, when xenwatchdogd is used instead, susp=
end
> handling is incomplete, potentially leading to watchdog-triggered resets =
on
> resume. Xen leaves watchdog handling to the guest OS and its services.
>
> Dropped all changes related to VCPU context, because instead domain_shutd=
own
> is used, so we don't need any extra changes for suspending domain.
>
> Changes in V3:
> Dropped all domain flags and related code (which touched common functions=
 like
> vcpu_unblock), keeping only the necessary changes for Xen suspend/resume,=
 i.e.
> suspend/resume is now fully supported only for the hardware domain.
> Proper support for domU suspend/resume will be added in a future patch.
> This patch does not yet include VCPU context reset or domain context
> restoration in VCPU.
> ---
>  xen/arch/arm/domain.c                 |  21 +++++-
>  xen/arch/arm/include/asm/domain.h     |   2 +
>  xen/arch/arm/include/asm/perfc_defn.h |   1 +
>  xen/arch/arm/include/asm/psci.h       |   2 +
>  xen/arch/arm/include/asm/vpsci.h      |   2 +-
>  xen/arch/arm/vpsci.c                  | 100 ++++++++++++++++++++++----
>  xen/common/domain.c                   |  35 +++++++--
>  xen/include/xen/sched.h               |   3 +
>  8 files changed, 141 insertions(+), 25 deletions(-)
>
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index 863ae18157..401106fd67 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -90,6 +90,24 @@ static void ctxt_switch_from(struct vcpu *p)
>      if ( is_idle_vcpu(p) )
>          return;
> =20
> +    /*
> +     * Even if the guest saves and restores its own context, Xen must sa=
ve
> +     * the transient state (such as List Registers) that is not preserve=
d
> +     * by hardware across suspend. See PSCI DEN0022F.b, section 6.8
> +     * "Preserving the execution context".
> +     */
> +    gic_save_state(p);
> +
> +    /*
> +     * Skip saving the rest of the context if the VCPU is suspended,
> +     * to avoid modifying SCTLR_EL1. This is required by the PSCI
> +     * specification, which manages SCTLR_EL1 during SYSTEM_SUSPEND flow=
.
> +     */
> +    if ( test_bit(_VPF_suspended, &p->pause_flags) )
> +        return;
> +
> +    isb();
> +
>      p2m_save_state(p);

I am pretty sure that Julien told you that you can't skip p2m due to
to some workarounds regarding CPU speculation.

> =20
>      /* CP 15 */
> @@ -158,9 +176,6 @@ static void ctxt_switch_from(struct vcpu *p)
> =20
>      /* XXX MPU */
> =20
> -    /* VGIC */
> -    gic_save_state(p);
> -
>      isb();
>  }
> =20
> diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm=
/domain.h
> index a3487ca713..f9577bc9ae 100644
> --- a/xen/arch/arm/include/asm/domain.h
> +++ b/xen/arch/arm/include/asm/domain.h
> @@ -312,6 +312,8 @@ static inline void update_guest_memory_policy(struct =
vcpu *v,
>                                                struct guest_memory_policy=
 *gmp)
>  {}
> =20
> +void domain_resume_nopause_helper(struct domain *d);

If I am not mistaken, function declarations for xen/common/domain.c
should go into include/xen/domain.h, not arch/arm/include/asm/domain.h

Also, I am honestly don't know is it a good way to expose internal
function from xen/common/domain.c. I do understand why do you need this,
but function naming becomes more and more confusing. I had my
considerations against domain_resume_nopause(), but
domain_resume_nopause_helper() is even worse, because it sounds to
generic.

Lastly, I checked docs/misra/rules.rst. There is no mention of Rule
8.7. So why you can't just make domain_resume_nopause() externally
available?

> +
>  #endif /* __ASM_DOMAIN_H__ */
> =20
>  /*
> diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/include=
/asm/perfc_defn.h
> index effd25b69e..8dfcac7e3b 100644
> --- a/xen/arch/arm/include/asm/perfc_defn.h
> +++ b/xen/arch/arm/include/asm/perfc_defn.h
> @@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system_r=
eset")
>  PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
>  PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
>  PERFCOUNTER(vpsci_features,            "vpsci: features")
> +PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
> =20
>  PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
> =20
> diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/p=
sci.h
> index 4780972621..48a93e6b79 100644
> --- a/xen/arch/arm/include/asm/psci.h
> +++ b/xen/arch/arm/include/asm/psci.h
> @@ -47,10 +47,12 @@ void call_psci_system_reset(void);
>  #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
>  #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
>  #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
> +#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
> =20
>  #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
>  #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
>  #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
> +#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
> =20
>  /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
>  #define PSCI_0_2_AFFINITY_LEVEL_ON      0
> diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/asm/=
vpsci.h
> index 0cca5e6830..69d40f9d7f 100644
> --- a/xen/arch/arm/include/asm/vpsci.h
> +++ b/xen/arch/arm/include/asm/vpsci.h
> @@ -23,7 +23,7 @@
>  #include 
> =20
>  /* Number of function implemented by virtual PSCI (only 0.2 or later) */
> -#define VPSCI_NR_FUNCS  12
> +#define VPSCI_NR_FUNCS  14
> =20
>  /* Functions handle PSCI calls from the guests */
>  bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
> diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
> index 7ba9ccd94b..3371f33b81 100644
> --- a/xen/arch/arm/vpsci.c
> +++ b/xen/arch/arm/vpsci.c
> @@ -10,28 +10,18 @@
> =20
>  #include 
> =20
> -static int do_common_cpu_on(register_t target_cpu, register_t entry_poin=
t,
> -                            register_t context_id)
> +static int do_setup_vcpu_ctx(struct vcpu *v, register_t entry_point,
> +                      register_t context_id)
>  {
> -    struct vcpu *v;
>      struct domain *d =3D current->domain;
>      struct vcpu_guest_context *ctxt;
>      int rc;
>      bool is_thumb =3D entry_point & 1;
> -    register_t vcpuid;
> -
> -    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> -
> -    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> -        return PSCI_INVALID_PARAMETERS;
> =20
>      /* THUMB set is not allowed with 64-bit domain */
>      if ( is_64bit_domain(d) && is_thumb )
>          return PSCI_INVALID_ADDRESS;
> =20
> -    if ( !test_bit(_VPF_down, &v->pause_flags) )
> -        return PSCI_ALREADY_ON;
> -
>      if ( (ctxt =3D alloc_vcpu_guest_context()) =3D=3D NULL )
>          return PSCI_DENIED;
> =20
> @@ -78,11 +68,32 @@ static int do_common_cpu_on(register_t target_cpu, re=
gister_t entry_point,
>      if ( rc < 0 )
>          return PSCI_DENIED;
> =20
> -    vcpu_wake(v);
> -
>      return PSCI_SUCCESS;
>  }
> =20
> +static int do_common_cpu_on(register_t target_cpu, register_t entry_poin=
t,
> +                            register_t context_id)
> +{
> +    int rc;
> +    struct vcpu *v;
> +    struct domain *d =3D current->domain;
> +    register_t vcpuid;
> +
> +    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> +
> +    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> +        return PSCI_INVALID_PARAMETERS;
> +
> +    if ( !test_bit(_VPF_down, &v->pause_flags) )
> +        return PSCI_ALREADY_ON;
> +
> +    rc =3D do_setup_vcpu_ctx(v, entry_point, context_id);
> +    if ( rc =3D=3D PSCI_SUCCESS )
> +        vcpu_wake(v);
> +
> +    return rc;
> +}
> +
>  static int32_t do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
>  {
>      int32_t ret;
> @@ -197,6 +208,48 @@ static void do_psci_0_2_system_reset(void)
>      domain_shutdown(d,SHUTDOWN_reboot);
>  }
> =20
> +static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t =
cid)
> +{
> +    int32_t rc;
> +    struct vcpu *v;
> +    struct domain *d =3D current->domain;
> +
> +    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> +    if ( is_hardware_domain(d) )
> +        return PSCI_NOT_SUPPORTED;
> +
> +    /* Ensure that all CPUs other than the calling one are offline */
> +    domain_lock(d);
> +    for_each_vcpu ( d, v )
> +    {
> +        if ( v !=3D current && is_vcpu_online(v) )
> +        {
> +            domain_unlock(d);
> +            return PSCI_DENIED;
> +        }
> +    }
> +    domain_unlock(d);
> +
> +    rc =3D domain_shutdown(d, SHUTDOWN_suspend);
> +    if ( rc )
> +        return PSCI_DENIED;
> +
> +    rc =3D do_setup_vcpu_ctx(current, epoint, cid);
> +    if ( rc !=3D PSCI_SUCCESS )
> +    {
> +        domain_resume_nopause_helper(d);
> +        return rc;
> +    }
> +
> +    set_bit(_VPF_suspended, ¤t->pause_flags);
> +
> +    gprintk(XENLOG_DEBUG,
> +            "SYSTEM_SUSPEND requested, epoint=3D0x%"PRIregister", cid=3D=
0x%"PRIregister,
> +            epoint, cid);
> +
> +    return rc;
> +}
> +
>  static int32_t do_psci_1_0_features(uint32_t psci_func_id)
>  {
>      /* /!\ Ordered by function ID and not name */
> @@ -214,6 +267,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_fun=
c_id)
>      case PSCI_0_2_FN32_SYSTEM_OFF:
>      case PSCI_0_2_FN32_SYSTEM_RESET:
>      case PSCI_1_0_FN32_PSCI_FEATURES:
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
>      case ARM_SMCCC_VERSION_FID:
>          return 0;
>      default:
> @@ -344,6 +399,23 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, u=
int32_t fid)
>          return true;
>      }
> =20
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> +    {
> +        register_t epoint =3D PSCI_ARG(regs, 1);
> +        register_t cid =3D PSCI_ARG(regs, 2);
> +
> +        if ( fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND )
> +        {
> +            epoint &=3D GENMASK(31, 0);
> +            cid &=3D GENMASK(31, 0);
> +        }
> +
> +        perfc_incr(vpsci_system_suspend);
> +        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
> +        return true;
> +    }
> +
>      default:
>          return false;
>      }
> diff --git a/xen/common/domain.c b/xen/common/domain.c
> index 104e917f07..e2371549a0 100644
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -1349,16 +1349,10 @@ int domain_shutdown(struct domain *d, u8 reason)
>      return 0;
>  }
> =20
> -void domain_resume(struct domain *d)
> +static void domain_resume_nopause(struct domain *d)
>  {
>      struct vcpu *v;
> =20
> -    /*
> -     * Some code paths assume that shutdown status does not get reset un=
der
> -     * their feet (e.g., some assertions make this assumption).
> -     */
> -    domain_pause(d);
> -
>      spin_lock(&d->shutdown_lock);
> =20
>      d->is_shutting_down =3D d->is_shut_down =3D 0;
> @@ -1366,13 +1360,40 @@ void domain_resume(struct domain *d)
> =20
>      for_each_vcpu ( d, v )
>      {
> +        /*
> +         * No need to conditionally clear _VPF_suspended here:
> +         * - This bit is only set on Arm, and only after a successful su=
spend.
> +         * - domain_resume_nopause() may also be called from paths other=
 than
> +         *   the suspend/resume flow, such as "soft-reset" actions (e.g.=
,
> +         *   on_poweroff), as part of the Xenstore control/shutdown prot=
ocol.
> +         *   These require guest acknowledgement to complete the operati=
on.
> +         * So clearing the bit unconditionally is safe.
> +         */
> +        clear_bit(_VPF_suspended, &v->pause_flags);
> +
>          if ( v->paused_for_shutdown )
>              vcpu_unpause(v);
>          v->paused_for_shutdown =3D 0;
>      }
> =20
>      spin_unlock(&d->shutdown_lock);
> +}
> =20
> +#ifdef CONFIG_ARM
> +void domain_resume_nopause_helper(struct domain *d)
> +{
> +    domain_resume_nopause(d);
> +}
> +#endif
> +
> +void domain_resume(struct domain *d)
> +{
> +    /*
> +     * Some code paths assume that shutdown status does not get reset un=
der
> +     * their feet (e.g., some assertions make this assumption).
> +     */
> +    domain_pause(d);
> +    domain_resume_nopause(d);
>      domain_unpause(d);
>  }
> =20
> diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
> index 02bdc256ce..12429d16b9 100644
> --- a/xen/include/xen/sched.h
> +++ b/xen/include/xen/sched.h
> @@ -1014,6 +1014,9 @@ static inline struct domain *next_domain_in_cpupool=
(
>  /* VCPU is parked. */
>  #define _VPF_parked          8
>  #define VPF_parked           (1UL<<_VPF_parked)
> +/* VCPU is suspended. */
> +#define _VPF_suspended       9
> +#define VPF_suspended        (1UL << _VPF_suspended)
> =20
>  static inline bool vcpu_runnable(const struct vcpu *v)
>  {

--=20
WBR, Volodymyr=


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On 2025-08-27 11:21, Jürgen Groß wrote:
> On 26.08.25 02:55, Jason Andryuk wrote:
>> Change find_virq() to return -EEXIST when a VIRQ is bound to a
>> different CPU than the one passed in.  With that, remove the BUG_ON()
>> from bind_virq_to_irq() to propogate the error upwards.
>>
>> Some VIRQs are per-cpu, but others are per-domain or global.  Those must
>> be bound to CPU0 and can then migrate elsewhere.  The lookup for
>> per-domain and global will probably fail when migrated off CPU 0,
>> especially when the current CPU is tracked.  This now returns -EEXIST
>> instead of BUG_ON().
>>
>> A second call to bind a per-domain or global VIRQ is not expected, but
>> make it non-fatal to avoid trying to look up the irq, since we don't
>> know which per_cpu(virq_to_irq) it will be in.
>>
>> Signed-off-by: Jason Andryuk 
>
>> @@ -1381,8 +1387,9 @@ int bind_virq_to_irq(unsigned int virq, unsigned 
>> int cpu, bool percpu)
>>               evtchn = bind_virq.port;
>>           else {
>>               if (ret == -EEXIST)
>> -                ret = find_virq(virq, cpu, &evtchn);
>> -            BUG_ON(ret < 0);
>> +                ret = find_virq(virq, cpu, &evtchn, percpu);
>> +            if (ret)
>> +                goto out;
> 
> I think you are leaking info here. I guess a call of __unbind_from_irq() is
> wanted like in the error case below (note that the case of no valid 
> evtchn is
> handled there just fine).

Ok, thanks for catching that.

I'm going to add Cc: stable to the next version of this.  While it 
doesn't have a Fixes associated, we want this as a prerequisite for patch 3.

Regards,
Jason


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From: Jason Andryuk 
To: Juergen Gross , Stefano Stabellini
	, Oleksandr Tyshchenko
	
CC: Jason Andryuk , ,
	
Subject: [PATCH v3 0/3] xen/events: Fix Global and Domain VIRQ tracking
Date: Wed, 27 Aug 2025 20:36:00 -0400
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v2 and v3 are now series first changing find_virq() to return -EEXIST in
some cases, and then tracking cpu movement of VIRQs.  This keeps ensures
the cpu is correct when calling unbind_from_irq().

I'm adding Cc stable to all patches.  Patch 2 doesn't have a Fixes, but
it goes together with patch 3.

Jason Andryuk (3):
  xen/events: Cleanup find_virq() return codes
  xen/events: Return -EEXIST for bound VIRQs
  xen/events: Update virq_to_irq on migration

 drivers/xen/events/events_base.c | 37 +++++++++++++++++++++++++-------
 1 file changed, 29 insertions(+), 8 deletions(-)

-- 
2.34.1



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From: Jason Andryuk 
To: Juergen Gross , Stefano Stabellini
	, Oleksandr Tyshchenko
	
CC: Jason Andryuk , ,
	, 
Subject: [PATCH v3 2/3] xen/events: Return -EEXIST for bound VIRQs
Date: Wed, 27 Aug 2025 20:36:02 -0400
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Change find_virq() to return -EEXIST when a VIRQ is bound to a
different CPU than the one passed in.  With that, remove the BUG_ON()
from bind_virq_to_irq() to propogate the error upwards.

Some VIRQs are per-cpu, but others are per-domain or global.  Those must
be bound to CPU0 and can then migrate elsewhere.  The lookup for
per-domain and global will probably fail when migrated off CPU 0,
especially when the current CPU is tracked.  This now returns -EEXIST
instead of BUG_ON().

A second call to bind a per-domain or global VIRQ is not expected, but
make it non-fatal to avoid trying to look up the irq, since we don't
know which per_cpu(virq_to_irq) it will be in.

Cc: stable@vger.kernel.org
Signed-off-by: Jason Andryuk 
---
v3:
Cc: stable as a pre-req for the subsequent virg tracking change
Call __unbind_from_irq() on error ro avoid leaking info

v2:
New
---
 drivers/xen/events/events_base.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index 374231d84e4f..b060b5a95f45 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -1314,10 +1314,12 @@ int bind_interdomain_evtchn_to_irq_lateeoi(struct xenbus_device *dev,
 }
 EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irq_lateeoi);
 
-static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
+static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn,
+		     bool percpu)
 {
 	struct evtchn_status status;
 	evtchn_port_t port;
+	bool exists = false;
 
 	memset(&status, 0, sizeof(status));
 	for (port = 0; port < xen_evtchn_max_channels(); port++) {
@@ -1330,12 +1332,16 @@ static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
 			continue;
 		if (status.status != EVTCHNSTAT_virq)
 			continue;
-		if (status.u.virq == virq && status.vcpu == xen_vcpu_nr(cpu)) {
+		if (status.u.virq != virq)
+			continue;
+		if (status.vcpu == xen_vcpu_nr(cpu)) {
 			*evtchn = port;
 			return 0;
+		} else if (!percpu) {
+			exists = true;
 		}
 	}
-	return -ENOENT;
+	return exists ? -EEXIST : -ENOENT;
 }
 
 /**
@@ -1382,8 +1388,11 @@ int bind_virq_to_irq(unsigned int virq, unsigned int cpu, bool percpu)
 			evtchn = bind_virq.port;
 		else {
 			if (ret == -EEXIST)
-				ret = find_virq(virq, cpu, &evtchn);
-			BUG_ON(ret < 0);
+				ret = find_virq(virq, cpu, &evtchn, percpu);
+			if (ret) {
+				__unbind_from_irq(info, info->irq);
+				goto out;
+			}
 		}
 
 		ret = xen_irq_info_virq_setup(info, cpu, evtchn, virq);
-- 
2.34.1



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From: Jason Andryuk 
To: Juergen Gross , Stefano Stabellini
	, Oleksandr Tyshchenko
	, Konrad Rzeszutek Wilk
	, Olaf Hering 
CC: Jason Andryuk , , "Jan
 Beulich" , ,
	
Subject: [PATCH v3 1/3] xen/events: Cleanup find_virq() return codes
Date: Wed, 27 Aug 2025 20:36:01 -0400
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rc is overwritten by the evtchn_status hypercall in each iteration, so
the return value will be whatever the last iteration is.  This could
incorrectly return success even if the event channel was not found.
Change to an explicit -ENOENT for an un-found virq and return 0 on a
successful match.

Fixes: 62cc5fc7b2e0 ("xen/pv-on-hvm kexec: rebind virqs to existing eventchannel ports")
Cc: stable@vger.kernel.org
Signed-off-by: Jason Andryuk 
Reviewed-by: Jan Beulich 
Reviewed-by: Juergen Gross 
---
v3:
Reduce rc's scope
Add R-b: Jan
Mention false success in commit message
Add Fixes
Cc: stable
Add R-b: Juergen

v2:
New
---
 drivers/xen/events/events_base.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index 41309d38f78c..374231d84e4f 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -1318,10 +1318,11 @@ static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
 {
 	struct evtchn_status status;
 	evtchn_port_t port;
-	int rc = -ENOENT;
 
 	memset(&status, 0, sizeof(status));
 	for (port = 0; port < xen_evtchn_max_channels(); port++) {
+		int rc;
+
 		status.dom = DOMID_SELF;
 		status.port = port;
 		rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
@@ -1331,10 +1332,10 @@ static int find_virq(unsigned int virq, unsigned int cpu, evtchn_port_t *evtchn)
 			continue;
 		if (status.u.virq == virq && status.vcpu == xen_vcpu_nr(cpu)) {
 			*evtchn = port;
-			break;
+			return 0;
 		}
 	}
-	return rc;
+	return -ENOENT;
 }
 
 /**
-- 
2.34.1



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On 2025-04-02 09:57, Jan Beulich wrote:
> ... before making changes to the involved logic.
> 
> Signed-off-by: Jan Beulich 

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Date: Wed, 27 Aug 2025 18:20:30 -0400
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Subject: Re: [PATCH v2 2/5] symbols: split symbols_num_syms
To: Jan Beulich , "xen-devel@lists.xenproject.org"
	
CC: Andrew Cooper , Julien Grall ,
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	, Michal Orzel ,
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On 2025-04-02 09:58, Jan Beulich wrote:
> In preparation for inserting address entries into symbols_addresses[] /
> symbols_offsets[] without enlarging symbols_sorted_offsets[], split
> symbols_num_syms into symbols_num_addrs (counting entries in the former
> plus symbols_names[] as well as, less directly, symbols_markers[]) and
> symbols_num_names (counting entries in the latter).
> 
> While doing the adjustment move declarations to a new private symbols.h,
> to be used by both symbols.c and symbols-dummy.c. Replace u8/u16 while
> doing so.
> 
> Signed-off-by: Jan Beulich 
> Acked-by: Andrew Cooper 

Reviewed-by: Jason Andryuk 


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From: Jason Andryuk 
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	Chris Wright 
CC: Jason Andryuk , ,
	, 
Subject: [PATCH v3 3/3] xen/events: Update virq_to_irq on migration
Date: Wed, 27 Aug 2025 20:36:03 -0400
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VIRQs come in 3 flavors, per-VPU, per-domain, and global, and the VIRQs
are tracked in per-cpu virq_to_irq arrays.

Per-domain and global VIRQs must be bound on CPU 0, and
bind_virq_to_irq() sets the per_cpu virq_to_irq at registration time
Later, the interrupt can migrate, and info->cpu is updated.  When
calling __unbind_from_irq(), the per-cpu virq_to_irq is cleared for a
different cpu.  If bind_virq_to_irq() is called again with CPU 0, the
stale irq is returned.  There won't be any irq_info for the irq, so
things break.

Make xen_rebind_evtchn_to_cpu() update the per_cpu virq_to_irq mappings
to keep them update to date with the current cpu.  This ensures the
correct virq_to_irq is cleared in __unbind_from_irq().

Fixes: e46cdb66c8fc ("xen: event channels")
Cc: stable@vger.kernel.org
Signed-off-by: Jason Andryuk 
---
v3:
Kernel style brace placement
Delay setting old_cpu and tighten scope of variable

v2:
Different approach changing virq_to_irq
---
 drivers/xen/events/events_base.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index b060b5a95f45..9478fae014e5 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -1797,9 +1797,20 @@ static int xen_rebind_evtchn_to_cpu(struct irq_info *info, unsigned int tcpu)
 	 * virq or IPI channel, which don't actually need to be rebound. Ignore
 	 * it, but don't do the xenlinux-level rebind in that case.
 	 */
-	if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
+	if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) {
+		int old_cpu = info->cpu;
+
 		bind_evtchn_to_cpu(info, tcpu, false);
 
+		if (info->type == IRQT_VIRQ) {
+			int virq = info->u.virq;
+			int irq = per_cpu(virq_to_irq, old_cpu)[virq];
+
+			per_cpu(virq_to_irq, old_cpu)[virq] = -1;
+			per_cpu(virq_to_irq, tcpu)[virq] = irq;
+		}
+	}
+
 	do_unmask(info, EVT_MASK_REASON_TEMPORARY);
 
 	return 0;
-- 
2.34.1



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From: Stefano Stabellini 
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To: Jan Beulich 
cc: Stefano Stabellini , 
    Oleksii Kurochko , ray.huang@amd.com, 
    Andrew Cooper , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Anthony PERARD , 
    Michal Orzel , Julien Grall , 
    xen-devel@lists.xenproject.org, Penny Zheng 
Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
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References: <20250815102728.1340505-1-Penny.Zheng@amd.com>   <2035b14e-3836-4e80-9dad-8a49ca90864a@suse.com> 
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On Wed, 27 Aug 2025, Jan Beulich wrote:
> On 27.08.2025 02:33, Stefano Stabellini wrote:
> > So I ran a test and the appended change, which is based on [1] and
> > renaming CONFIG_DOMCTL to CONFIG_SYSCTL, is sufficient to resolve the
> > build issue.
> > 
> > For 4.21, I suggest we go with two patches:
> > 1) global rename of CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
> > 2) stub domctl_lock_acquire/release based on CONFIG_MGMT_HYPERCALLS
> > 
> > Jan, are you OK with this?
> 
> Naming if the option aside, no, I fear I dislike the stubbing. What's
> worse though, ...
> 
> > --- a/xen/include/xen/domain.h
> > +++ b/xen/include/xen/domain.h
> > @@ -148,8 +148,17 @@ void arch_dump_domain_info(struct domain *d);
> >  
> >  int arch_vcpu_reset(struct vcpu *v);
> >  
> > +#ifdef CONFIG_SYSCTL
> >  bool domctl_lock_acquire(void);
> >  void domctl_lock_release(void);
> > +#else
> > +static inline bool domctl_lock_acquire(void)
> > +{
> > +    return false;
> 
> ... this will break x86'es HVM_PARAM_IDENT_PT handling. That is, in
> principle I would agree that returning false here is appropriate. But
> for the specific case there it's wrong.

Uhm, that is a good point actually. And while in principle "false"
sounds appropriate, in practice there is no domctl.c to worry about
concurrency so "true" is what we want.


> As said on the call yesterday, until what you call MGMT_HYPERCALLS is
> completely done, the option needs to be prompt-less, always-on.

I do not think this is a good idea, because we would be unable to test
the configuration. Although we have been accepting code without tests,
that is not a good principle. At least with the current approach we can
run manual tests if automated tests are not available. If we make it
silent, we risk introducing broken code, or code soon-to-become broken.

In my view, we need to make gradual progress toward the goal. In this
case, we should move incrementally toward compiling out all the
"management" hypercalls. Also the alternative of waiting until all
patches are ready before committing them is not feasible. An incremental
approach reduces risk, preserves testability, and makes regressions
easier to identify.

An extreme example is that I could write:

static inline bool domctl_lock_acquire(void)
{
    obviously broken
}

and no tests would catch it.

So in short, I think we need to keep the prompt.


> Adding
> a prompt was necessary to be the last thing on the SYSCTL series, and
> it'll need to be last on the follow-on one masking out further
> hypercalls. IOW my take is that 34317c508294 and 568f806cba4c will
> need reverting (the latter being what caused the regression, and the
> former depending on the latter), to allow to cleanly continue that
> work after the rename. If we don't do the reverts now (and take either
> Penny's patch or what you propose), imo we'll need to do them later.
> Else we're risking to introduce new randconfig breakages while the
> further conversion work is ongoing.

My suggestion remains to go forward with 2 patches:
0) keep both 568f806cba4c and 34317c508294
1) rename CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
2) this patch with return true from domctl_lock_acquire

I am open to reverting 568f806cba4c but I don't think it would improve
things. I definitely don't think we should revert 34317c508294. We need
34317c508294 otherwise this patch doesn't fix the build.

This is why I think we need the prompt: otherwise we would not discover
even very basic important build breakages.


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Subject: Re: [PATCH v2 3/5] symbols: arrange to know where functions end
To: Jan Beulich , "xen-devel@lists.xenproject.org"
	
CC: Andrew Cooper , Julien Grall ,
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On 2025-04-02 09:58, Jan Beulich wrote:
> When determining the symbol for a given address (e.g. for the %pS
> logging format specifier), so far the size of a symbol (function) was
> assumed to be everything until the next symbol. There may be gaps
> though, which would better be recognizable in output (often suggesting
> something odd is going on).
> 
> Insert "fake" end symbols in the address table, accompanied by zero-
> length type/name entries (to keep lookup reasonably close to how it
> was).
> 
> Note however that this, with present GNU binutils, won't work for
> xen.efi: The linker loses function sizes (they're not part of a normal
> symbol table entry), and hence nm has no way of reporting them.
> 
> The address table growth is quite significant on x86 release builds (due
> to functions being aligned to 16-byte boundaries), though: Its size
> almost doubles.
> 
> Requested-by: Andrew Cooper 
> Signed-off-by: Jan Beulich 
> ---
> Note: Style-wise this is a horrible mix. I'm trying to match styles with
>        what's used in the respective functions.
> 
> Older GNU ld retains section symbols, which nm then also lists. Should
> we perhaps strip those as we read in nm's output? They don't provide any
> useful extra information, as our linker scripts add section start
> symbols anyway. (For the purposes here, luckily such section symbols are
> at least emitted without size.)
> 
> Even for section start symbols there is the question of whether they
> really need retaining (except perhaps when producing a map file). The
> main question here likely is whether livepatch may have a need to look
> them up by name. (Section end symbols may actually be slightly more
> useful to keep, but that may also want considering more closely.)
> ---

> --- a/xen/tools/symbols.c
> +++ b/xen/tools/symbols.c

> @@ -318,24 +334,42 @@ static void write_src(void)
>   	printf("#else\n");
>   	output_label("symbols_offsets");
>   	printf("#endif\n");
> -	for (i = 0; i < table_cnt; i++) {
> +	for (i = 0, ends = 0; i < table_cnt; i++) {
>   		printf("\tPTR\t%#llx - SYMBOLS_ORIGIN\n", table[i].addr);
> +
> +		table[i].addr_idx = i + ends;
> +
> +		if (!want_symbol_end(i)) {
> +			/* If there's another symbol at the same address,
> +			 * propagate this symbol's size if the next one has
> +			 * no size, or if the next one's size is larger. */

Why do we want to shrink the next symbol's size?

The code looks good - I just don't understand this condition.

Thanks,
Jason

> +			if (table[i].size &&
> +			    i + 1 < table_cnt &&
> +			    table[i + 1].addr == table[i].addr &&
> +			    (!table[i + 1].size ||
> +			     table[i + 1].size > table[i].size))
> +				table[i + 1].size = table[i].size;
> +			continue;
> +		}
> +
> +		++ends;
> +		printf("\tPTR\t%#llx - SYMBOLS_ORIGIN\n",
> +		       table[i].addr + table[i].size);
>   	}
>   	printf("\n");
>   
>   	output_label("symbols_num_addrs");
> -	printf("\t.long\t%d\n", table_cnt);
> +	printf("\t.long\t%d\n", table_cnt + ends);
>   	printf("\n");
>   
>   	/* table of offset markers, that give the offset in the compressed stream
>   	 * every 256 symbols */
> -	markers = (unsigned int *) malloc(sizeof(unsigned int) * ((table_cnt + 255) / 256));
> +	markers = malloc(sizeof(*markers) * ((table_cnt + ends + 255) >> 8));
>   
>   	output_label("symbols_names");
> -	off = 0;
> -	for (i = 0; i < table_cnt; i++) {
> -		if ((i & 0xFF) == 0)
> -			markers[i >> 8] = off;
> +	for (i = 0, off = 0, ends = 0; i < table_cnt; i++) {
> +		if (((i + ends) & 0xFF) == 0)
> +			markers[(i + ends) >> 8] = off;
>   
>   		printf("\t.byte 0x%02x", table[i].len);
>   		for (k = 0; k < table[i].len; k++)


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Subject: Re: [PATCH v2 4/5] symbols: centralize and re-arrange $(all_symbols)
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To: Jan Beulich , "xen-devel@lists.xenproject.org"
	
CC: Andrew Cooper , Julien Grall ,
	Stefano Stabellini , Anthony PERARD
	, Michal Orzel ,
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Bertrand Marquis
	, Volodymyr Babchuk 
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On 2025-04-02 09:59, Jan Beulich wrote:
> For one there's no need for each architecture to have the same logic.
> Move to the root Makefile, also to calculate just once.
> 
> And then re-arrange to permit FAST_SYMBOL_LOOKUP to be independent of
> LIVEPATCH, which may be useful in (at least) debugging.
> 
> Signed-off-by: Jan Beulich 

Reviewed-by: Jason Andryuk 


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On 2025-04-02 10:00, Jan Beulich wrote:
> ... and thus typically also a size. Using global vs local is undesirable
> in certain situations, e.g. when a "real" symbol is local and at the
> same address as a section start/end one (which are all global).
> 
> Note that for xen.efi the checking for "Function" is only forward-
> looking at this point: The function-ness of symbols (much like their
> size) is lost when linking PE/COFF binaries from ELF objects with GNU ld
> up to at least 2.44.
> 
> Signed-off-by: Jan Beulich 

Reviewed-by: Jason Andryuk 


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Subject: Re: [PATCH] libxl: except Dom0 from setting PoD target
To: Jan Beulich , "xen-devel@lists.xenproject.org"
	
CC: Anthony PERARD 
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On 2025-08-27 01:53, Jan Beulich wrote:
> Dom0 is never started in PoD mode, and hence it can at "best" do harm if
> we try to set a PoD target for it.
> 
> Signed-off-by: Jan Beulich 

Reviewed-by: Jason Andryuk 

Did you observe an issue, or just notice this when inspecting the code? 
If an issue, please add to the commit message.

Thanks,
Jason


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Subject: Re: [PATCH] libxl: respect unset video_memkb for Dom0
To: Jan Beulich , "xen-devel@lists.xenproject.org"
	
CC: Anthony PERARD , Juergen Gross
	
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On 2025-08-27 01:56, Jan Beulich wrote:
> Without this, Dom0 will have have a curiously off-by-1 target_memkb
> value displayed by "xl list -l".
> 
> Signed-off-by: Jan Beulich 

Reviewed-by: Jason Andryuk 

In theory, b_info->video_memkb should have been defaulted to 0.  In 
practice you found it isn't.  xen-init-dom0 could probably use some fixing.

> ---
> In retrieve_domain_configuration_end(), isn't it the wrong way round to
> set both ->b_info.target_memkb and ->b_info.max_memkb only after calling
> libxl__get_targetmem_fudge(), when that uses the two fields? This way we
> could as well use ->b_info->video_memkb directly there.

I think it's attempting to read the current values from xenstore, in 
case they changed via xl mem-set, and then putting them into the d_config.

Regards,
Jason

> Of course this may point at a bigger problem, as other fields may
> similarly never be set for Dom0.


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On 2025-08-27 01:57, Jan Beulich wrote:
> Callers observing errors elsewhere may be confused by the ENOSYS that
> the Flask operation would yield on a Flask-disabled hypervisor.
> 
> Signed-off-by: Jan Beulich 
> ---
> Of course I don't know whether clobbering errno is perhaps deemed "fine"
> in libxl.

I wonder if it would be better to special case 
libxl_flask_sid_to_context() to preserve errno on ENOSYS.  flask 
returning ENOSYS is common, but libxl_flask_sid_to_context() can 
legitimately have error.

I guess this is fine if we want to use this approach:

Reviewed-by: Jason Andryuk 

> --- a/tools/libs/light/libxl_domain.c
> +++ b/tools/libs/light/libxl_domain.c
> @@ -277,6 +277,7 @@ void libxl__xcinfo2xlinfo(libxl_ctx *ctx
>                             libxl_dominfo *xlinfo)
>   {
>       size_t size;
> +    int saved_errno = errno;
>   
>       memcpy(&(xlinfo->uuid), xcinfo->handle, sizeof(xen_domain_handle_t));
>       xlinfo->domid = xcinfo->domain;
> @@ -284,6 +285,7 @@ void libxl__xcinfo2xlinfo(libxl_ctx *ctx
>       if (libxl_flask_sid_to_context(ctx, xlinfo->ssidref,
>                                      &xlinfo->ssid_label, &size) < 0)
>           xlinfo->ssid_label = NULL;
> +    errno = saved_errno;
>   
>       xlinfo->dying      = !!(xcinfo->flags&XEN_DOMINF_dying);
>       xlinfo->shutdown   = !!(xcinfo->flags&XEN_DOMINF_shutdown);
> 



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Date: Wed, 27 Aug 2025 21:22:13 -0400
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To: Xen-devel 
From: Jason Andryuk 
Subject: MCA hypercall with PVH
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Hi,

The MCA hypercall, do_mca(), is only available for PV.  That is, it's 
only added to the hypercall table for PV.  Is there a particular reason 
it was omitted from PVH, or did PVH dom0 just not exist?

Thanks,
Jason


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, Andrew Cooper ,
	"Orzel, Michal" , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Topic: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Index: AQHcE1L0WO8OIJho60KGV8JFR/QspLRzjMCAgAJSvzA=
Date: Thu, 28 Aug 2025 04:06:32 +0000
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References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-14-Penny.Zheng@amd.com>
 
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From: "Penny, Zheng" 
To: Anthony PERARD 
CC: "xen-devel@lists.xenproject.org" , "Huang,
 Ray" , Anthony PERARD , Juergen
 Gross , Andrew Cooper , "Orzel,
 Michal" , Jan Beulich , Julien Grall
	, =?iso-8859-1?Q?Roger_Pau_Monn=E9?= ,
	Stefano Stabellini 
Subject: RE: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq
 para
Thread-Topic: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufreq
 para
Thread-Index: AQHcE1LyQ0lYyaNtv02FRdV+NHpcFrR2pieAgADXRwA=
Date: Thu, 28 Aug 2025 04:14:10 +0000
Message-ID:
 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-12-Penny.Zheng@amd.com> 
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[Public]

> -----Original Message-----
> From: Anthony PERARD 
> Sent: Wednesday, August 27, 2025 11:22 PM
> To: Penny, Zheng 
> Cc: xen-devel@lists.xenproject.org; Huang, Ray ; Antho=
ny
> PERARD ; Juergen Gross ;
> Andrew Cooper ; Orzel, Michal
> ; Jan Beulich ; Julien Grall
> ; Roger Pau Monn=E9 ; Stefano Stabe=
llini
> 
> Subject: Re: [PATCH v7 11/13] tools/cpufreq: extract CPPC para from cpufr=
eq para
>
> On Fri, Aug 22, 2025 at 06:52:16PM +0800, Penny Zheng wrote:
> > diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c index
> > 6b054b10a4..8fc1d7cc65 100644
> > --- a/tools/misc/xenpm.c
> > +++ b/tools/misc/xenpm.c
> > @@ -898,6 +900,23 @@ static void print_cpufreq_para(int cpuid, struct
> xc_get_cpufreq_para *p_cpufreq)
> >      printf("\n");
> >  }
> >
> > +/* show cpu cppc parameters information on CPU cpuid */ static int
> > +show_cppc_para_by_cpuid(xc_interface *xc_handle, unsigned int cpuid)
> > +{
> > +    int ret;
> > +    xc_cppc_para_t cppc_para;
> > +
> > +    ret =3D xc_get_cppc_para(xc_handle, cpuid, &cppc_para);
> > +    if ( !ret )
> > +        print_cppc_para(cpuid, &cppc_para);
> > +    else if ( errno =3D=3D ENODEV )
> > +        ret =3D 0; /* Ignore unsupported platform */
> > +    else
> > +        fprintf(stderr, "[CPU%u] failed to get cppc parameter\n",
> > + cpuid);
>
> You might want to add ": %s" strerror(errno) to the error printed, which =
could help
> figure out why we failed to get the parameters.
>

Ack

>
> The rest of the tool side of the patch, with Jan suggestion, looks good t=
o me, so
> Acked-by: Anthony PERARD  for the next round.
>

Thanks

> Thanks,
>
> --
> Anthony PERARD


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From: Oleksii Moisieiev 
To: Jan Beulich 
CC: Andrew Cooper , Anthony PERARD
	, Bertrand Marquis ,
	Juergen Gross , Julien Grall , Michal Orzel
	, =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Stefano Stabellini ,
	Volodymyr Babchuk , Grygorii Strashko
	, "xen-devel@lists.xenproject.org"
	
Subject: Re: [RFC PATCH v5 06/10] xen/domctl: extend XEN_DOMCTL_assign_device
 to handle not only iommu
Thread-Topic: [RFC PATCH v5 06/10] xen/domctl: extend XEN_DOMCTL_assign_device
 to handle not only iommu
Thread-Index: AQHb+v2XIf5rVjN6B0ydmKskjXCNlrQ+E9WAgDm1BAA=
Date: Thu, 28 Aug 2025 05:48:45 +0000
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Subject: Re: [PATCH] libxl: except Dom0 from setting PoD target
To: Jason Andryuk 
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On 28.08.2025 03:08, Jason Andryuk wrote:
> On 2025-08-27 01:53, Jan Beulich wrote:
>> Dom0 is never started in PoD mode, and hence it can at "best" do harm if
>> we try to set a PoD target for it.
>>
>> Signed-off-by: Jan Beulich 
> 
> Reviewed-by: Jason Andryuk 

Thanks.

> Did you observe an issue, or just notice this when inspecting the code? 

It simply caught my eye while investigating the ballooning issue I sent
a mail about.

> If an issue, please add to the commit message.

I would have, sure.

Jan


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Subject: Re: [PATCH] libxl: respect unset video_memkb for Dom0
To: Jason Andryuk 
Cc: Anthony PERARD ,
 Juergen Gross ,
 "xen-devel@lists.xenproject.org" 
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On 28.08.2025 03:12, Jason Andryuk wrote:
> On 2025-08-27 01:56, Jan Beulich wrote:
>> Without this, Dom0 will have have a curiously off-by-1 target_memkb
>> value displayed by "xl list -l".
>>
>> Signed-off-by: Jan Beulich 
> 
> Reviewed-by: Jason Andryuk 

Thanks.

> In theory, b_info->video_memkb should have been defaulted to 0.

I don't think 0 would be a legitimate default; it might be for Dom0, but
not generally.

>  In 
> practice you found it isn't.  xen-init-dom0 could probably use some fixing.

Right, kind of as per the latter of the two post-commit-message remarks.

>> ---
>> In retrieve_domain_configuration_end(), isn't it the wrong way round to
>> set both ->b_info.target_memkb and ->b_info.max_memkb only after calling
>> libxl__get_targetmem_fudge(), when that uses the two fields? This way we
>> could as well use ->b_info->video_memkb directly there.
> 
> I think it's attempting to read the current values from xenstore, in 
> case they changed via xl mem-set, and then putting them into the d_config.

That's my understanding too, yet it still makes little sense to me to
invoke a function when data it consumes isn't set (yet).

Jan

>> Of course this may point at a bigger problem, as other fields may
>> similarly never be set for Dom0.



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Subject: Re: [PATCH] libxl: preserve errno in libxl__xcinfo2xlinfo()
To: Jason Andryuk 
Cc: Anthony PERARD ,
 Juergen Gross ,
 "xen-devel@lists.xenproject.org" 
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On 28.08.2025 03:16, Jason Andryuk wrote:
> On 2025-08-27 01:57, Jan Beulich wrote:
>> Callers observing errors elsewhere may be confused by the ENOSYS that
>> the Flask operation would yield on a Flask-disabled hypervisor.
>>
>> Signed-off-by: Jan Beulich 
>> ---
>> Of course I don't know whether clobbering errno is perhaps deemed "fine"
>> in libxl.
> 
> I wonder if it would be better to special case 
> libxl_flask_sid_to_context() to preserve errno on ENOSYS.  flask 
> returning ENOSYS is common, but libxl_flask_sid_to_context() can 
> legitimately have error.

But then libxl__xcinfo2xlinfo() also shouldn't (effectively) ignore such
other errors? Question is what it should do in such an event.

> I guess this is fine if we want to use this approach:
> 
> Reviewed-by: Jason Andryuk 

Thanks.

Jan


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Date: Thu, 28 Aug 2025 08:17:27 +0200
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Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
To: Stefano Stabellini 
Cc: Oleksii Kurochko , ray.huang@amd.com,
 Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 xen-devel@lists.xenproject.org, Penny Zheng 
References: <20250815102728.1340505-1-Penny.Zheng@amd.com>
 
 
 <2035b14e-3836-4e80-9dad-8a49ca90864a@suse.com>
 
 <49416df6-83c8-4fa3-bf81-2d1e504ef31b@suse.com>
 
 
 
 
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From: Jan Beulich 
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On 28.08.2025 02:52, Stefano Stabellini wrote:
> On Wed, 27 Aug 2025, Jan Beulich wrote:
>> On 27.08.2025 02:33, Stefano Stabellini wrote:
>>> So I ran a test and the appended change, which is based on [1] and
>>> renaming CONFIG_DOMCTL to CONFIG_SYSCTL, is sufficient to resolve the
>>> build issue.
>>>
>>> For 4.21, I suggest we go with two patches:
>>> 1) global rename of CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
>>> 2) stub domctl_lock_acquire/release based on CONFIG_MGMT_HYPERCALLS
>>>
>>> Jan, are you OK with this?
>>
>> Naming if the option aside, no, I fear I dislike the stubbing. What's
>> worse though, ...
>>
>>> --- a/xen/include/xen/domain.h
>>> +++ b/xen/include/xen/domain.h
>>> @@ -148,8 +148,17 @@ void arch_dump_domain_info(struct domain *d);
>>>  
>>>  int arch_vcpu_reset(struct vcpu *v);
>>>  
>>> +#ifdef CONFIG_SYSCTL
>>>  bool domctl_lock_acquire(void);
>>>  void domctl_lock_release(void);
>>> +#else
>>> +static inline bool domctl_lock_acquire(void)
>>> +{
>>> +    return false;
>>
>> ... this will break x86'es HVM_PARAM_IDENT_PT handling. That is, in
>> principle I would agree that returning false here is appropriate. But
>> for the specific case there it's wrong.
> 
> Uhm, that is a good point actually. And while in principle "false"
> sounds appropriate, in practice there is no domctl.c to worry about
> concurrency so "true" is what we want.

Except that, as said, conceptually "true" is the wrong value to use in
such a stub.

>> As said on the call yesterday, until what you call MGMT_HYPERCALLS is
>> completely done, the option needs to be prompt-less, always-on.
> 
> I do not think this is a good idea, because we would be unable to test
> the configuration. Although we have been accepting code without tests,
> that is not a good principle. At least with the current approach we can
> run manual tests if automated tests are not available. If we make it
> silent, we risk introducing broken code, or code soon-to-become broken.
> 
> In my view, we need to make gradual progress toward the goal. In this
> case, we should move incrementally toward compiling out all the
> "management" hypercalls. Also the alternative of waiting until all
> patches are ready before committing them is not feasible. An incremental
> approach reduces risk, preserves testability, and makes regressions
> easier to identify.

If that's your view, then why did you not comment on the SYSCTL series,
when I asked the prompt to appear last?

> An extreme example is that I could write:
> 
> static inline bool domctl_lock_acquire(void)
> {
>     obviously broken
> }
> 
> and no tests would catch it.

Tests would catch it at the point the prompt is added. Much like it was
with the SYSCTL series (and why, with the prompt removed, the rest of
the series can stay in).

>> Adding
>> a prompt was necessary to be the last thing on the SYSCTL series, and
>> it'll need to be last on the follow-on one masking out further
>> hypercalls. IOW my take is that 34317c508294 and 568f806cba4c will
>> need reverting (the latter being what caused the regression, and the
>> former depending on the latter), to allow to cleanly continue that
>> work after the rename. If we don't do the reverts now (and take either
>> Penny's patch or what you propose), imo we'll need to do them later.
>> Else we're risking to introduce new randconfig breakages while the
>> further conversion work is ongoing.
> 
> My suggestion remains to go forward with 2 patches:
> 0) keep both 568f806cba4c and 34317c508294
> 1) rename CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
> 2) this patch with return true from domctl_lock_acquire
> 
> I am open to reverting 568f806cba4c but I don't think it would improve
> things. I definitely don't think we should revert 34317c508294. We need
> 34317c508294 otherwise this patch doesn't fix the build.

If "this patch" is the one outlined here, then with the reverts we wouldn't
need it at all. The reverts alone will fix the build issue, according to my
understanding.

Jan


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Date: Thu, 28 Aug 2025 08:35:51 +0200
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Subject: Re: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
To: "Penny, Zheng" 
Cc: "Huang, Ray" ,
 Anthony PERARD ,
 Andrew Cooper ,
 "Orzel, Michal" , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-14-Penny.Zheng@amd.com>
 
 
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On 28.08.2025 06:06, Penny, Zheng wrote:
>> -----Original Message-----
>> From: Jan Beulich 
>> Sent: Tuesday, August 26, 2025 12:03 AM
>>
>> On 22.08.2025 12:52, Penny Zheng wrote:
>>> --- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c
>>> +++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
>>> +    /* Only allow values if params bit is set. */
>>> +    if ( (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED) &&
>>> +          set_cppc->desired) ||
>>> +         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) &&
>>> +          set_cppc->minimum) ||
>>> +         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
>>> +          set_cppc->maximum) ||
>>> +         (!(set_cppc->set_params &
>> XEN_SYSCTL_CPPC_SET_ENERGY_PERF) &&
>>> +          set_cppc->energy_perf) )
>>> +        return -EINVAL;
>>
>> ... all the errors checked here are to be ignored when no flag is set at all?
> 
> Yes, values are only meaningful when according flag is properly set, which has been described in the comment for "struct xen_set_cppc_para"

Especially since you stripped the initial part of this comment of mine, it feels
as if you misunderstood my request. What it boils down to is the question whether
"if ( set_cppc->set_params == 0 )" shouldn't move after the if() you left in
context above.

>>> +    /*
>>> +     * Validate all parameters
>>> +     * Maximum performance may be set to any performance value in the range
>>> +     * [Nonlinear Lowest Performance, Highest Performance], inclusive but
>> must
>>> +     * be set to a value that is larger than or equal to minimum Performance.
>>> +     */
>>> +    if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
>>> +         (set_cppc->maximum > data->caps.highest_perf ||
>>> +          set_cppc->maximum <
>>> +                        (set_cppc->set_params &
>> XEN_SYSCTL_CPPC_SET_MINIMUM
>>> +                         ? set_cppc->minimum
>>> +                         : data->req.min_perf)) )
>>
>> Too deep indentation (more of this throughout the function), and seeing ...
> 
> Maybe four indention is more proper
> ```
>         if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
>              (set_cppc->maximum > data->caps.highest_perf ||
>               (set_cppc->maximum <
>                           (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM
>                     ? set_cppc->minimum
>                     : data->req.min_perf))) )
> ```

No. In expressions you always want to indent according to pending open
parentheses:

        if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
             (set_cppc->maximum > data->caps.highest_perf ||
              (set_cppc->maximum <
               (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM
                ? set_cppc->minimum
                : data->req.min_perf))) )

>>> +    case XEN_SYSCTL_CPPC_SET_PRESET_NONE:
>>> +        if ( active_mode )
>>> +            policy->policy = CPUFREQ_POLICY_UNKNOWN;
>>> +        break;
>>> +
>>> +    default:
>>> +        return -EINVAL;
>>> +    }
>>
>> Much of this looks very similar to what patch 09 introduces in
>> amd_cppc_epp_set_policy(). Is it not possible to reduce the redundancy?
>>
> 
> I'll add a new helper to amd_cppc_prepare_policy() to extract common
> 
>>> --- a/xen/include/public/sysctl.h
>>> +++ b/xen/include/public/sysctl.h
>>> @@ -336,8 +336,14 @@ struct xen_ondemand {
>>>      uint32_t up_threshold;
>>>  };
>>>
>>> +#define CPUFREQ_POLICY_UNKNOWN      0
>>> +#define CPUFREQ_POLICY_POWERSAVE    1
>>> +#define CPUFREQ_POLICY_PERFORMANCE  2
>>> +#define CPUFREQ_POLICY_ONDEMAND     3
>>
>> Without XEN_ prefixes they shouldn't appear in a public header. But do we
>> need ...
>>
>>>  struct xen_get_cppc_para {
>>>      /* OUT */
>>> +    uint32_t policy; /* CPUFREQ_POLICY_xxx */
>>
>> ... the new field at all? Can't you synthesize the kind-of-governor into struct
>> xen_get_cpufreq_para's respective field? You invoke both sub-ops from xenpm
>> now anyway ...
>>
> 
> Maybe I could borrow governor field to indicate policy info, like the following in print_cpufreq_para(), then we don't need to add the new filed "policy"
> ```
> +    /* Translate governor info to policy info in CPPC active mode */
> +    if ( is_cppc_active )
> +    {
> +        if ( !strncmp(p_cpufreq->u.s.scaling_governor,
> +                      "ondemand", CPUFREQ_NAME_LEN) )
> +            printf("cppc policy           : ondemand\n");
> +        else if ( !strncmp(p_cpufreq->u.s.scaling_governor,
> +                           "performance", CPUFREQ_NAME_LEN) )
> +            printf("cppc policy           : performance\n");
> +
> +        else if ( !strncmp(p_cpufreq->u.s.scaling_governor,
> +                           "powersave", CPUFREQ_NAME_LEN) )
> +            printf("cppc policy           : powersave\n");
> +        else
> +            printf("cppc policy           : unknown\n");
> +    }
> +
> ```

Something like this is what I was thinking of, yes.

Jan


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Message-ID: 
Date: Thu, 28 Aug 2025 08:37:33 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
From: Jan Beulich 
To: "Penny, Zheng" 
Cc: "Huang, Ray" ,
 Anthony PERARD ,
 Andrew Cooper ,
 "Orzel, Michal" , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-14-Penny.Zheng@amd.com>
 
 
 
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On 28.08.2025 08:35, Jan Beulich wrote:
> On 28.08.2025 06:06, Penny, Zheng wrote:
>>> -----Original Message-----
>>> From: Jan Beulich 
>>> Sent: Tuesday, August 26, 2025 12:03 AM
>>>
>>> On 22.08.2025 12:52, Penny Zheng wrote:
>>>> --- a/xen/include/public/sysctl.h
>>>> +++ b/xen/include/public/sysctl.h
>>>> @@ -336,8 +336,14 @@ struct xen_ondemand {
>>>>      uint32_t up_threshold;
>>>>  };
>>>>
>>>> +#define CPUFREQ_POLICY_UNKNOWN      0
>>>> +#define CPUFREQ_POLICY_POWERSAVE    1
>>>> +#define CPUFREQ_POLICY_PERFORMANCE  2
>>>> +#define CPUFREQ_POLICY_ONDEMAND     3
>>>
>>> Without XEN_ prefixes they shouldn't appear in a public header. But do we
>>> need ...
>>>
>>>>  struct xen_get_cppc_para {
>>>>      /* OUT */
>>>> +    uint32_t policy; /* CPUFREQ_POLICY_xxx */
>>>
>>> ... the new field at all? Can't you synthesize the kind-of-governor into struct
>>> xen_get_cpufreq_para's respective field? You invoke both sub-ops from xenpm
>>> now anyway ...
>>>
>>
>> Maybe I could borrow governor field to indicate policy info, like the following in print_cpufreq_para(), then we don't need to add the new filed "policy"
>> ```
>> +    /* Translate governor info to policy info in CPPC active mode */
>> +    if ( is_cppc_active )
>> +    {
>> +        if ( !strncmp(p_cpufreq->u.s.scaling_governor,
>> +                      "ondemand", CPUFREQ_NAME_LEN) )
>> +            printf("cppc policy           : ondemand\n");
>> +        else if ( !strncmp(p_cpufreq->u.s.scaling_governor,
>> +                           "performance", CPUFREQ_NAME_LEN) )
>> +            printf("cppc policy           : performance\n");
>> +
>> +        else if ( !strncmp(p_cpufreq->u.s.scaling_governor,
>> +                           "powersave", CPUFREQ_NAME_LEN) )
>> +            printf("cppc policy           : powersave\n");
>> +        else
>> +            printf("cppc policy           : unknown\n");
>> +    }
>> +
>> ```
> 
> Something like this is what I was thinking of, yes.

Albeit - why the complicated if/else sequence? Why not simply print
the field the hypercall returned?

Jan


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Subject: Re: [RFC PATCH v5 06/10] xen/domctl: extend XEN_DOMCTL_assign_device
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To: Oleksii Moisieiev 
Cc: Andrew Cooper ,
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On 28.08.2025 07:48, Oleksii Moisieiev wrote:
> 
> 
> On 22/07/2025 15:34, Jan Beulich wrote:
>> On 22.07.2025 13:41, Oleksii Moisieiev wrote:
>>> @@ -859,7 +860,25 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl)
>>>       case XEN_DOMCTL_test_assign_device:
>>>       case XEN_DOMCTL_deassign_device:
>>>       case XEN_DOMCTL_get_device_group:
>>> +        int ret1;
>>> +
>>>           ret = iommu_do_domctl(op, d, u_domctl);
>>> +        if ( ret < 0 && ret != -ENXIO )
>>> +            return ret;
>> If this is where you want the ENXIO for that the previous patch switched to,
>> then I see no reason for that earlier change at all. Inside the hypervisor
>> you can simply figure out what the right thing to do is; you could avoid
>> calling iommu_do_domctl() altogether and call ...
> 
> My point was to leave the decision making to the calls themselves.
> So iommu_do_domctl will make a decision whether to process the node or 
> not, same for the scmi call.
> I can figure out if there is a need to call iommu_do_domctl or 
> sci_do_domctl here but this means moving
> part of the logic from specific calls to the common code.

To avoid that, maybe it needs doing the other way around? I.e. try ...

>>> +        /*
>>> +         * Add chained handling of assigned DT devices to support
>>> +         * access-controller functionality through SCI framework, so
>>> +         * DT device assign request can be passed to FW for processing and
>>> +         * enabling VM access to requested device.
>>> +         * The access-controller DT device processing is chained after IOMMU
>>> +         * processing and expected to be executed for any DT device
>>> +         * regardless if DT device is protected by IOMMU or not (or IOMMU
>>> +         * is disabled).
>>> +         */
>>> +        ret1 = sci_do_domctl(op, d, u_domctl);

... this first?

Jan


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To: Teddy Astie 
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 Anthony PERARD ,
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On 27.08.2025 22:27, Teddy Astie wrote:
> --- a/xen/include/public/xen.h
> +++ b/xen/include/public/xen.h
> @@ -975,6 +975,10 @@ typedef struct dom0_vga_console_info {
>   #define xen_vga_console_info dom0_vga_console_info
>   #define xen_vga_console_info_t dom0_vga_console_info_t
> 
> +/*
> + * The guest handled provided by toolstack encoded as a UUID in
> + * big-endian order. Its string representation follows RFC 9562.
> + */
>   typedef uint8_t xen_domain_handle_t[16];

Imo at most "is intended to follow".

Jan


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, Andrew Cooper ,
	"Orzel, Michal" , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Topic: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Index: AQHcE1L0WO8OIJho60KGV8JFR/QspLRzjMCAgAJSvzCAAcXZgIAAAHmAgAACEFA=
Date: Thu, 28 Aug 2025 06:54:51 +0000
Message-ID:
 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-14-Penny.Zheng@amd.com>
 
 
 
 
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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Nicola Vetrini
	, Doug Goldstein , Stefano
 Stabellini , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , Julien
 Grall , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	
Subject: [PATCH v3] misra: add deviation of Rule 17.7
Thread-Topic: [PATCH v3] misra: add deviation of Rule 17.7
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MISRA C Rule 17.7 states: "The value returned by a function having
non-void return type shall be used."

The functions 'memcpy()', 'memset()', and 'memmove()' return values
primarily for convenience. The core functionality of these functions
(memory manipulation) remains unaffected, and their return values
are generally non-critical and seldom relied upon. Therefore,
violations of this rule due to these functions are deemed safe.

Update 'deviations.rst' file accordingly. No functional changes.

Signed-off-by: Dmytro Prokopchuk 
Reviewed-by: Nicola Vetrini 
---
Changes in v3:
- changed the last sentence in wording
- added Nicola's Reviewed-by tag

Link to v2:
https://patchew.org/Xen/812b78119cee801662a31d39b556cb453aa69508.1756192362=
.git.dmytro._5Fprokopchuk1@epam.com/
---
 automation/eclair_analysis/ECLAIR/deviations.ecl | 7 +++++++
 docs/misra/deviations.rst                        | 8 ++++++++
 2 files changed, 15 insertions(+)

diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl b/automation/=
eclair_analysis/ECLAIR/deviations.ecl
index 7f3fd35a33..f410eafad6 100644
--- a/automation/eclair_analysis/ECLAIR/deviations.ecl
+++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
@@ -575,6 +575,13 @@ safe."
 -config=3DMC3A2.R17.7,calls+=3D{safe, "any()", "decl(name(__builtin_memcpy=
||__builtin_memmove||__builtin_memset||cpumask_check))"}
 -doc_end
=20
+-doc_begin=3D"The functions 'memcpy()', 'memset()', and 'memmove()' return=
 values primarily for convenience.
+The core functionality of these functions (memory manipulation) remains un=
affected, and their return values
+are generally non-critical and seldom relied upon. Therefore, violations o=
f this rule due to these functions
+are deemed safe."
+-config=3DMC3A2.R17.7,calls+=3D{safe, "any()", "decl(name(memcpy||memset||=
memmove))"}
+-doc_end
+
 #
 # Series 18.
 #
diff --git a/docs/misra/deviations.rst b/docs/misra/deviations.rst
index 2119066531..8e086d989f 100644
--- a/docs/misra/deviations.rst
+++ b/docs/misra/deviations.rst
@@ -576,6 +576,14 @@ Deviations related to MISRA C:2012 Rules:
          - __builtin_memset()
          - cpumask_check()
=20
+   * - R17.7
+     - The functions 'memcpy()', 'memset()', and 'memmove()' return values
+       primarily for convenience. The core functionality of these function=
s
+       (memory manipulation) remains unaffected, and their return values a=
re
+       generally non-critical and seldom relied upon. Therefore, violation=
s
+       of this rule due to these functions are deemed safe.
+     - Tagged as `safe` for ECLAIR.
+
    * - R18.2
      - Subtractions between pointers where at least one of the operand is =
a
        pointer to a symbol defined by the linker are safe.
--=20
2.43.0


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Subject: Re: [PATCH v4 2/3] hvmloader: fix SMBIOS table length checks
To: =?UTF-8?Q?Petr_Bene=C5=A1?= 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD , xen-devel@lists.xenproject.org
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From: Jan Beulich 
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In-Reply-To: <1f452cde49cd9cfa949affe6061fc628de434e18.1753869323.git.w1benny@gmail.com>
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On 30.07.2025 11:56, Petr Beneš wrote:
> --- a/tools/firmware/hvmloader/smbios_types.h
> +++ b/tools/firmware/hvmloader/smbios_types.h
> @@ -90,13 +90,13 @@ struct smbios_type_2 {
>      uint8_t product_name_str;
>      uint8_t version_str;
>      uint8_t serial_number_str;
> -    uint8_t asset_tag_str;
> -    uint8_t feature_flags;
> -    uint8_t location_in_chassis_str;
> -    uint16_t chassis_handle;
> -    uint8_t board_type;
> -    uint8_t contained_handle_count;
> -    uint16_t contained_handles[];
> +    uint8_t asset_tag_str;                  /* Optional */
> +    uint8_t feature_flags;                  /* Optional */
> +    uint8_t location_in_chassis_str;        /* Optional */
> +    uint16_t chassis_handle;                /* Optional */
> +    uint8_t board_type;                     /* Optional */
> +    uint8_t contained_handle_count;         /* Optional */
> +    uint16_t contained_handles[];           /* Optional */
>  } __attribute__ ((packed));
>  
>  /* System Enclosure - Contained Elements */
> @@ -118,12 +118,12 @@ struct smbios_type_3 {
>      uint8_t power_supply_state;
>      uint8_t thermal_state;
>      uint8_t security_status;
> -    uint32_t oem_specific;
> -    uint8_t height;
> -    uint8_t number_of_power_cords;
> -    uint8_t contained_element_count;
> -    uint8_t contained_element_length;
> -    struct smbios_contained_element contained_elements[];
> +    uint32_t oem_specific;                  /* Optional */
> +    uint8_t height;                         /* Optional */
> +    uint8_t number_of_power_cords;          /* Optional */
> +    uint8_t contained_element_count;        /* Optional */
> +    uint8_t contained_element_length;       /* Optional */
> +    struct smbios_contained_element contained_elements[]; /* Optional */
>  } __attribute__ ((packed));
>  
>  /* SMBIOS type 4 - Processor Information */
> @@ -252,9 +252,9 @@ struct smbios_type_39 {
>      uint8_t revision_level_str;
>      uint16_t max_capacity;
>      uint16_t characteristics;
> -    uint16_t input_voltage_probe_handle;
> -    uint16_t cooling_device_handle;
> -    uint16_t input_current_probe_handle;
> +    uint16_t input_voltage_probe_handle;    /* Optional */
> +    uint16_t cooling_device_handle;         /* Optional */
> +    uint16_t input_current_probe_handle;    /* Optional */
>  } __attribute__ ((packed));
>  
>  /* SMBIOS type 127 -- End-of-table */

I regret now that I didn't look more closely before offering my ack. May I
ask where these "Optional" (and also the ones in patch 3) are taken from?
While looking at Teddy's patch to bump the version to 2.6 I considered it
necessary to check whether other adjustments (fields becoming non-optional
for example) would be required, and to my surprise and couldn't find proof
of any of the above being optional in 2.4.

Jan


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Subject: Re: [PATCH] hvmloader: Update to SMBIOS 2.6
To: Teddy Astie 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD , xen-devel@lists.xenproject.org
References: 
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On 22.08.2025 15:47, Teddy Astie wrote:
> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
> 
> In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
> (undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
> you have a endian mismatch causing the UUIDs to mismatch in the guest.
> 
> $ cat /sys/hypervisor/uuid
> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
> $ cat /sys/devices/virtual/dmi/id/product_uuid
> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
> $ cat /sys/devices/virtual/dmi/id/product_serial
> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
> 
> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
> written in the table; which effectively fix this endianness mismatch with
> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.

To update to 2.6, fields new in 2.6 (compared to 2.4) need adding to the
various structures. First example I ran into is type 4, gaining 5 new
fields in 2.5.

Jan


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Subject: Re: [PATCH] hvmloader: Update to SMBIOS 2.6
To: Andrew Cooper ,
 Teddy Astie 
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On 27.08.2025 19:47, Andrew Cooper wrote:
> On 22/08/2025 2:47 pm, Teddy Astie wrote:
>> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
>> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
>>
>> In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
>> (undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
>> you have a endian mismatch causing the UUIDs to mismatch in the guest.
>>
>> $ cat /sys/hypervisor/uuid
>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>> $ cat /sys/devices/virtual/dmi/id/product_uuid
>> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
>> $ cat /sys/devices/virtual/dmi/id/product_serial
>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>
>> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
>> written in the table; which effectively fix this endianness mismatch with
>> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.
>>
>> Signed-off-by: Teddy Astie 
>> ---
>> This effectively changes the UUID seen with UEFI guests as it was
>> actually inconsistent with SeaBIOS and SMBIOS expectations.
>> ---
> 
> I agree this is a real bug and needs fixing.

Hmm, I didn't realize this is a bug, and hence put the patch off as 4.22
material. If there is a bug being fixed: Teddy, please add a Fixes: tag.

Jan


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Subject: Re: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
To: "Penny, Zheng" 
Cc: "Huang, Ray" ,
 Anthony PERARD ,
 Andrew Cooper ,
 "Orzel, Michal" , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-14-Penny.Zheng@amd.com>
 
 
 
 
 
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From: Jan Beulich 
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On 28.08.2025 08:54, Penny, Zheng wrote:
> [Public]
> 
>> -----Original Message-----
>> From: Jan Beulich 
>> Sent: Thursday, August 28, 2025 2:38 PM
>> To: Penny, Zheng 
>> Cc: Huang, Ray ; Anthony PERARD
>> ; Andrew Cooper ;
>> Orzel, Michal ; Julien Grall ; Roger Pau
>> Monné ; Stefano Stabellini ; xen-
>> devel@lists.xenproject.org
>> Subject: Re: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
>> xen_sysctl_pm_op for amd-cppc driver
>>
>> On 28.08.2025 08:35, Jan Beulich wrote:
>>> On 28.08.2025 06:06, Penny, Zheng wrote:
>>>>> -----Original Message-----
>>>>> From: Jan Beulich 
>>>>> Sent: Tuesday, August 26, 2025 12:03 AM
>>>>>
>>>>> On 22.08.2025 12:52, Penny Zheng wrote:
>>>>>> --- a/xen/include/public/sysctl.h
>>>>>> +++ b/xen/include/public/sysctl.h
>>>>>> @@ -336,8 +336,14 @@ struct xen_ondemand {
>>>>>>      uint32_t up_threshold;
>>>>>>  };
>>>>>>
>>>>>> +#define CPUFREQ_POLICY_UNKNOWN      0
>>>>>> +#define CPUFREQ_POLICY_POWERSAVE    1
>>>>>> +#define CPUFREQ_POLICY_PERFORMANCE  2
>>>>>> +#define CPUFREQ_POLICY_ONDEMAND     3
>>>>>
>>>>> Without XEN_ prefixes they shouldn't appear in a public header. But
>>>>> do we need ...
>>>>>
>>>>>>  struct xen_get_cppc_para {
>>>>>>      /* OUT */
>>>>>> +    uint32_t policy; /* CPUFREQ_POLICY_xxx */
>>>>>
>>>>> ... the new field at all? Can't you synthesize the kind-of-governor
>>>>> into struct xen_get_cpufreq_para's respective field? You invoke both
>>>>> sub-ops from xenpm now anyway ...
>>>>>
>>>>
>>>> Maybe I could borrow governor field to indicate policy info, like the following in
>> print_cpufreq_para(), then we don't need to add the new filed "policy"
>>>> ```
>>>> +    /* Translate governor info to policy info in CPPC active mode */
>>>> +    if ( is_cppc_active )
>>>> +    {
>>>> +        if ( !strncmp(p_cpufreq->u.s.scaling_governor,
>>>> +                      "ondemand", CPUFREQ_NAME_LEN) )
>>>> +            printf("cppc policy           : ondemand\n");
>>>> +        else if ( !strncmp(p_cpufreq->u.s.scaling_governor,
>>>> +                           "performance", CPUFREQ_NAME_LEN) )
>>>> +            printf("cppc policy           : performance\n");
>>>> +
>>>> +        else if ( !strncmp(p_cpufreq->u.s.scaling_governor,
>>>> +                           "powersave", CPUFREQ_NAME_LEN) )
>>>> +            printf("cppc policy           : powersave\n");
>>>> +        else
>>>> +            printf("cppc policy           : unknown\n");
>>>> +    }
>>>> +
>>>> ```
>>>
>>> Something like this is what I was thinking of, yes.
>>
>> Albeit - why the complicated if/else sequence? Why not simply print the field the
>> hypercall returned?
> 
> userspace governor doesn't have according policy. I could simplify it to
> ```
>         if ( !strncmp(p_cpufreq->u.s.scaling_governor,
>              "userspace", CPUFREQ_NAME_LEN) )
>                 printf("policy               : unknown\n");
>         else
>                 printf("policy               : %s\n",
>                           p_cpufreq->u.s.scaling_governor);
> ```

But the hypervisor shouldn't report back "userspace" when the CPPC driver
is in use. ANd I think the tool is okay to trust the hypervisor.

Jan


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Subject: Re: [PATCH v2 3/5] symbols: arrange to know where functions end
To: Jason Andryuk 
Cc: Andrew Cooper , Julien Grall ,
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On 28.08.2025 03:03, Jason Andryuk wrote:
> On 2025-04-02 09:58, Jan Beulich wrote:
>> When determining the symbol for a given address (e.g. for the %pS
>> logging format specifier), so far the size of a symbol (function) was
>> assumed to be everything until the next symbol. There may be gaps
>> though, which would better be recognizable in output (often suggesting
>> something odd is going on).
>>
>> Insert "fake" end symbols in the address table, accompanied by zero-
>> length type/name entries (to keep lookup reasonably close to how it
>> was).
>>
>> Note however that this, with present GNU binutils, won't work for

Btw, I've updated this to say "with GNU binutils prior to 2.45".

>> --- a/xen/tools/symbols.c
>> +++ b/xen/tools/symbols.c
> 
>> @@ -318,24 +334,42 @@ static void write_src(void)
>>   	printf("#else\n");
>>   	output_label("symbols_offsets");
>>   	printf("#endif\n");
>> -	for (i = 0; i < table_cnt; i++) {
>> +	for (i = 0, ends = 0; i < table_cnt; i++) {
>>   		printf("\tPTR\t%#llx - SYMBOLS_ORIGIN\n", table[i].addr);
>> +
>> +		table[i].addr_idx = i + ends;
>> +
>> +		if (!want_symbol_end(i)) {
>> +			/* If there's another symbol at the same address,
>> +			 * propagate this symbol's size if the next one has
>> +			 * no size, or if the next one's size is larger. */
> 
> Why do we want to shrink the next symbol's size?

First (see related post-commit-message remarks): In principle section symbols
could come with a size, too. That would break everything as long as we don't
strip those.

The main reason though is that imo smallest granularity is what we want here,
together with predictability. One symbol with a huge size could cover
multiple other symbols with smaller sizes. We could omit that part of the
change here, but then the processing in the hypervisor would need to change,
to fish out the "best suitable" symbol when dealing with multiple ones at the
same address. Other changes may then also be needed to the tool, to have such
symbols come in a well-defined order (to keep the then-new code in the
hypervisor as simple as possible). Look for "aliased symbol" in
common/symbols.c to see how simplistic respective code is right now.

Jan


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Date: Thu, 28 Aug 2025 09:39:13 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Mark Syms 
Cc: qemu-devel@nongnu.org, xen-devel@lists.xenproject.org,
	sstabellini@kernel.org, anthony@xenproject.org, paul@xen.org
Subject: Re: [PATCH] [xen-block] Return BLKIF_RSP_EOPNOTSUPP for unknown
 operation
Message-ID: 
References: <20250827160841.351707-1-mark.syms@cloud.com>
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In-Reply-To: <20250827160841.351707-1-mark.syms@cloud.com>

On Wed, Aug 27, 2025 at 05:08:41PM +0100, Mark Syms via wrote:
> Returning BLKIF_RSP_ERROR if an operation is not supoprted does not
> allow the frontend to exercise any discretion on how to handle the
> response and may lead to an operating system crash. As different
> backends may support different feature sets and we might, during a
> migration, switch backends, an in-flight request might be issued (or
> reissued) which is then not supported by this backend.

Linux blkfront at least will empty the ring on resume, and re-process
and queue the requests after having negotiated the (possibly) new set
of features with the backend.  That however doesn't avoid finding
flush requests that might not longer be supported by the new backend,
in which case Linux blkfront will drop such requests.

I assume the fixes done here are not targeted at dealing with a Linux
blkfront?

> Signed-off-by: Mark Syms 
> ---
>  hw/block/dataplane/xen-block.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/block/dataplane/xen-block.c b/hw/block/dataplane/xen-block.c
> index 48c2e315f3..32cf919a97 100644
> --- a/hw/block/dataplane/xen-block.c
> +++ b/hw/block/dataplane/xen-block.c
> @@ -167,7 +167,8 @@ static int xen_block_parse_request(XenBlockRequest *request)
>          return 0;
>      default:
>          error_report("error: unknown operation (%d)", request->req.operation);
> -        goto err;
> +        request->status = BLKIF_RSP_EOPNOTSUPP;
> +        return -1;

The comment in blkif.h contains:

 /* Operation not supported (only happens on barrier writes). */
#define BLKIF_RSP_EOPNOTSUPP  -2

So in principle BLKIF_RSP_EOPNOTSUPP is only to be used as a response
for BLKIF_OP_WRITE_BARRIER or BLKIF_OP_FLUSH_DISKCACHE requests,
however blkback already uses it as a response to unknown request
types (like you propose here).

Would you mind also sending a patch to adjust blkif.h in Xen to remove
the "(only happens on barrier writes)" part of the comment?

Thanks Roger.


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Date: Thu, 28 Aug 2025 09:40:26 +0200
MIME-Version: 1.0
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Subject: Re: [PATCH v10 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
To: Mykola Kvach 
Cc: Mykola Kvach ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 xen-devel@lists.xenproject.org
References: 
 <55ff99acd69f9eaf20f077e6b453b54931b541d4.1756329091.git.mykola_kvach@epam.com>
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From: Jan Beulich 
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On 27.08.2025 23:21, Mykola Kvach wrote:
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -1349,16 +1349,10 @@ int domain_shutdown(struct domain *d, u8 reason)
>      return 0;
>  }
>  
> -void domain_resume(struct domain *d)
> +static void domain_resume_nopause(struct domain *d)
>  {
>      struct vcpu *v;
>  
> -    /*
> -     * Some code paths assume that shutdown status does not get reset under
> -     * their feet (e.g., some assertions make this assumption).
> -     */
> -    domain_pause(d);
> -
>      spin_lock(&d->shutdown_lock);
>  
>      d->is_shutting_down = d->is_shut_down = 0;
> @@ -1366,13 +1360,40 @@ void domain_resume(struct domain *d)
>  
>      for_each_vcpu ( d, v )
>      {
> +        /*
> +         * No need to conditionally clear _VPF_suspended here:
> +         * - This bit is only set on Arm, and only after a successful suspend.

How likely do you think it is that, if e.g. RISC-V or PPC clone Arm's
code, this comment would then be updated accordingly? IOW I don't think
a justification like this one should be written in such terms.

> +         * - domain_resume_nopause() may also be called from paths other than
> +         *   the suspend/resume flow, such as "soft-reset" actions (e.g.,
> +         *   on_poweroff), as part of the Xenstore control/shutdown protocol.
> +         *   These require guest acknowledgement to complete the operation.

I'm having trouble connecting "require guest acknowledgement" to ...

> +         * So clearing the bit unconditionally is safe.

... the safety of the unconditional clearing.

> +         */
> +        clear_bit(_VPF_suspended, &v->pause_flags);
> +
>          if ( v->paused_for_shutdown )
>              vcpu_unpause(v);
>          v->paused_for_shutdown = 0;
>      }
>  
>      spin_unlock(&d->shutdown_lock);
> +}
>  
> +#ifdef CONFIG_ARM
> +void domain_resume_nopause_helper(struct domain *d)

This is an odd name to use from code meaning to invoke domain_resume_nopause().
Why isn't this called domain_resume_nopause(), and ...

> +{
> +    domain_resume_nopause(d);

... the static function simply _domain_resume_nopause() (in full accordance
to the C standard's naming rules)?

> +}
> +#endif
> +
> +void domain_resume(struct domain *d)
> +{
> +    /*
> +     * Some code paths assume that shutdown status does not get reset under
> +     * their feet (e.g., some assertions make this assumption).
> +     */
> +    domain_pause(d);

As you move the comment - no such assumptions exist when the code path
through domain_resume_nopause_helper() is taken?

Jan


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From: "Penny, Zheng" 
To: Jan Beulich 
CC: "Huang, Ray" , Anthony PERARD
	, Andrew Cooper ,
	"Orzel, Michal" , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Topic: [PATCH v7 13/13] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
Thread-Index:
 AQHcE1L0WO8OIJho60KGV8JFR/QspLRzjMCAgAJSvzCAAcXZgIAAAHmAgAACEFCAAAa+gIAAC74w
Date: Thu, 28 Aug 2025 07:52:14 +0000
Message-ID:
 
References: <20250822105218.3601273-1-Penny.Zheng@amd.com>
 <20250822105218.3601273-14-Penny.Zheng@amd.com>
 
 
 
 
 
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Date: Thu, 28 Aug 2025 10:01:15 +0200
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Subject: Re: [PATCH v4 2/3] hvmloader: fix SMBIOS table length checks
From: Jan Beulich 
To: =?UTF-8?Q?Petr_Bene=C5=A1?= 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD , xen-devel@lists.xenproject.org
References: 
 <1f452cde49cd9cfa949affe6061fc628de434e18.1753869323.git.w1benny@gmail.com>
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On 28.08.2025 09:03, Jan Beulich wrote:
> On 30.07.2025 11:56, Petr Beneš wrote:
>> --- a/tools/firmware/hvmloader/smbios_types.h
>> +++ b/tools/firmware/hvmloader/smbios_types.h
>> @@ -90,13 +90,13 @@ struct smbios_type_2 {
>>      uint8_t product_name_str;
>>      uint8_t version_str;
>>      uint8_t serial_number_str;
>> -    uint8_t asset_tag_str;
>> -    uint8_t feature_flags;
>> -    uint8_t location_in_chassis_str;
>> -    uint16_t chassis_handle;
>> -    uint8_t board_type;
>> -    uint8_t contained_handle_count;
>> -    uint16_t contained_handles[];
>> +    uint8_t asset_tag_str;                  /* Optional */
>> +    uint8_t feature_flags;                  /* Optional */
>> +    uint8_t location_in_chassis_str;        /* Optional */
>> +    uint16_t chassis_handle;                /* Optional */
>> +    uint8_t board_type;                     /* Optional */
>> +    uint8_t contained_handle_count;         /* Optional */
>> +    uint16_t contained_handles[];           /* Optional */
>>  } __attribute__ ((packed));
>>  
>>  /* System Enclosure - Contained Elements */
>> @@ -118,12 +118,12 @@ struct smbios_type_3 {
>>      uint8_t power_supply_state;
>>      uint8_t thermal_state;
>>      uint8_t security_status;
>> -    uint32_t oem_specific;
>> -    uint8_t height;
>> -    uint8_t number_of_power_cords;
>> -    uint8_t contained_element_count;
>> -    uint8_t contained_element_length;
>> -    struct smbios_contained_element contained_elements[];
>> +    uint32_t oem_specific;                  /* Optional */
>> +    uint8_t height;                         /* Optional */
>> +    uint8_t number_of_power_cords;          /* Optional */
>> +    uint8_t contained_element_count;        /* Optional */
>> +    uint8_t contained_element_length;       /* Optional */
>> +    struct smbios_contained_element contained_elements[]; /* Optional */
>>  } __attribute__ ((packed));
>>  
>>  /* SMBIOS type 4 - Processor Information */
>> @@ -252,9 +252,9 @@ struct smbios_type_39 {
>>      uint8_t revision_level_str;
>>      uint16_t max_capacity;
>>      uint16_t characteristics;
>> -    uint16_t input_voltage_probe_handle;
>> -    uint16_t cooling_device_handle;
>> -    uint16_t input_current_probe_handle;
>> +    uint16_t input_voltage_probe_handle;    /* Optional */
>> +    uint16_t cooling_device_handle;         /* Optional */
>> +    uint16_t input_current_probe_handle;    /* Optional */
>>  } __attribute__ ((packed));
>>  
>>  /* SMBIOS type 127 -- End-of-table */
> 
> I regret now that I didn't look more closely before offering my ack. May I
> ask where these "Optional" (and also the ones in patch 3) are taken from?
> While looking at Teddy's patch to bump the version to 2.6 I considered it
> necessary to check whether other adjustments (fields becoming non-optional
> for example) would be required, and to my surprise and couldn't find proof
> of any of the above being optional in 2.4.

I take this back. This is written down in the spec, just not as clearly and
uniformly as one might wish.

Jan


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From: Dmytro Prokopchuk1 
To: "xen-devel@lists.xenproject.org" 
CC: Dmytro Prokopchuk1 , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: [PATCH] device-tree: fix infinite loop issue in
 'assign_shared_memory()'
Thread-Topic: [PATCH] device-tree: fix infinite loop issue in
 'assign_shared_memory()'
Thread-Index: AQHcF/Q482rbLahQD0qhywmRaenDcQ==
Date: Thu, 28 Aug 2025 08:17:40 +0000
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Resolve infinite loop issue in the 'fail:' cleanup path of the function
'assign_shared_memory()'. The issue was caused by an 'unsigned long' type
for the loop counter 'i', which could underflow and wrap around, violating
termination conditions.
Change 'i' to a signed data type ('long') to ensure safe termination of
the 'while (--i >=3D 0)' loop.

This change adheres to MISRA Rule R14.3: "Controlling expressions shall
not be invariant."

Signed-off-by: Dmytro Prokopchuk 
---
 xen/common/device-tree/static-shmem.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/xen/common/device-tree/static-shmem.c b/xen/common/device-tree=
/static-shmem.c
index 8023c0a484..b4c772466c 100644
--- a/xen/common/device-tree/static-shmem.c
+++ b/xen/common/device-tree/static-shmem.c
@@ -134,7 +134,8 @@ static int __init assign_shared_memory(struct domain *d=
, paddr_t gbase,
 {
     mfn_t smfn;
     int ret =3D 0;
-    unsigned long nr_pages, nr_borrowers, i;
+    unsigned long nr_pages, nr_borrowers;
+    long i;
     struct page_info *page;
     paddr_t pbase, psize;
=20
--=20
2.43.0


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MIME-Version: 1.0
Date: Thu, 28 Aug 2025 10:31:17 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, Stefano Stabellini
 , Julien Grall , Bertrand Marquis
 , Michal Orzel 
Subject: Re: [PATCH] device-tree: fix infinite loop issue in
 'assign_shared_memory()'
In-Reply-To: 
References: 
Message-ID: <185dce3ba4762d4528866f2e50e45371@bugseng.com>
X-Sender: nicola.vetrini@bugseng.com
Organization: BUGSENG s.r.l.
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 format=flowed
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On 2025-08-28 10:17, Dmytro Prokopchuk1 wrote:
> Resolve infinite loop issue in the 'fail:' cleanup path of the function
> 'assign_shared_memory()'. The issue was caused by an 'unsigned long' 
> type
> for the loop counter 'i', which could underflow and wrap around, 
> violating
> termination conditions.
> Change 'i' to a signed data type ('long') to ensure safe termination of
> the 'while (--i >= 0)' loop.
> 

Then this likely should have Fixes tag. The R14.3 violation was found 
after adding CONFIG_UNSUPPORTED=y to analyze.yaml?

> This change adheres to MISRA Rule R14.3: "Controlling expressions shall
> not be invariant."
> 
> Signed-off-by: Dmytro Prokopchuk 
> ---
>  xen/common/device-tree/static-shmem.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/common/device-tree/static-shmem.c 
> b/xen/common/device-tree/static-shmem.c
> index 8023c0a484..b4c772466c 100644
> --- a/xen/common/device-tree/static-shmem.c
> +++ b/xen/common/device-tree/static-shmem.c
> @@ -134,7 +134,8 @@ static int __init assign_shared_memory(struct 
> domain *d, paddr_t gbase,
>  {
>      mfn_t smfn;
>      int ret = 0;
> -    unsigned long nr_pages, nr_borrowers, i;
> +    unsigned long nr_pages, nr_borrowers;
> +    long i;
>      struct page_info *page;
>      paddr_t pbase, psize;

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [PATCH] device-tree: fix infinite loop issue in
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To: Dmytro Prokopchuk1 
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On 28.08.2025 10:17, Dmytro Prokopchuk1 wrote:
> Resolve infinite loop issue in the 'fail:' cleanup path of the function
> 'assign_shared_memory()'. The issue was caused by an 'unsigned long' type
> for the loop counter 'i', which could underflow and wrap around, violating
> termination conditions.
> Change 'i' to a signed data type ('long') to ensure safe termination of
> the 'while (--i >= 0)' loop.

If I was a maintainer of this code, I would strongly object to such a change.
A signed type variable used as (effectively) an array index is almost always
conceptually wrong. Plus i continues to be compared to nr_pages, which still
is of an unsigned type.

What imo wants changing instead is the use of the variable:

 fail:
    while ( i-- > 0 )
        put_page_nr(page + i, nr_borrowers);

or yet more simply

 fail:
    while ( i-- )
        put_page_nr(page + i, nr_borrowers);

See e.g. prepare_staticmem_pages() for a similar case.

Jan


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Subject: Re: MCA hypercall with PVH
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On 28.08.2025 03:22, Jason Andryuk wrote:
> The MCA hypercall, do_mca(), is only available for PV.  That is, it's 
> only added to the hypercall table for PV.  Is there a particular reason 
> it was omitted from PVH, or did PVH dom0 just not exist?

PVH Dom0 didn't exist back at the time, yes, but it's more than this. The
hypercall, in some places, deals with MFNs, which aren't "visible" to PVH
Dom0. IOW enabling it (perhaps just partly) would need to be done with
extra care.

Jan


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Subject: Re: [PATCH] device-tree: fix infinite loop issue in
 'assign_shared_memory()'
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To: Jan Beulich ,
 Dmytro Prokopchuk1 
Cc: Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 "xen-devel@lists.xenproject.org" 
References: 
 <72b403be-bfaf-497f-90c8-d1cc9ff84ce8@suse.com>
From: Julien Grall 
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On 28/08/2025 09:42, Jan Beulich wrote:
> On 28.08.2025 10:17, Dmytro Prokopchuk1 wrote:
>> Resolve infinite loop issue in the 'fail:' cleanup path of the function
>> 'assign_shared_memory()'. The issue was caused by an 'unsigned long' type
>> for the loop counter 'i', which could underflow and wrap around, violating
>> termination conditions.
>> Change 'i' to a signed data type ('long') to ensure safe termination of
>> the 'while (--i >= 0)' loop.
> 
> If I was a maintainer of this code, I would strongly object to such a change.
> A signed type variable used as (effectively) an array index is almost always
> conceptually wrong. Plus i continues to be compared to nr_pages, which still
> is of an unsigned type.
> 
> What imo wants changing instead is the use of the variable:
> 
>   fail:
>      while ( i-- > 0 )
>          put_page_nr(page + i, nr_borrowers);
> 
> or yet more simply
> 
>   fail:
>      while ( i-- )
>          put_page_nr(page + i, nr_borrowers);
> 
> See e.g. prepare_staticmem_pages() for a similar case.

+1 with Jan's comment.

Cheers,

-- 
Julien Grall



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From: Dmytro Prokopchuk1 
To: Jan Beulich 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, "xen-devel@lists.xenproject.org"
	
Subject: Re: [PATCH] device-tree: fix infinite loop issue in
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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v4 08/12] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Topic: [PATCH v4 08/12] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcF3/NodAFMh424U2CquWmKsv0JLR3ycWA
Date: Thu, 28 Aug 2025 09:16:08 +0000
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Message-ID: <3f59b4ff-31f0-4801-96ba-83df139af081@amd.com>
Date: Thu, 28 Aug 2025 10:35:42 +0200
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Subject: Re: [PATCH v2 4/5] arm/mpu: Implement ioremap_attr for MPU
To: Hari Limaye , 
CC: , Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Volodymyr Babchuk 
References: 
 
From: "Orzel, Michal" 
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On 27/08/2025 18:35, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Introduce helpers (un)map_mm_range() in order to allow the transient
> mapping of a range of memory, and use these to implement the function
> `ioremap_attr` for MPU systems.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
> ---
> Changes from v1:
> - Use transient instead of temporary, and improve wording of comments
>   regarding transient mapping
> - Rename start, end -> base, limit
> ---
>  xen/arch/arm/include/asm/mpu/mm.h |  22 +++++
>  xen/arch/arm/mpu/mm.c             | 150 ++++++++++++++++++++++++++++--
>  2 files changed, 163 insertions(+), 9 deletions(-)
> 
> diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
> index 566d338986..efb0680e39 100644
> --- a/xen/arch/arm/include/asm/mpu/mm.h
> +++ b/xen/arch/arm/include/asm/mpu/mm.h
> @@ -101,6 +101,28 @@ int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
>   */
>  pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags);
>  
> +/*
> + * Maps transiently a range of memory with attributes `flags`; if the range is
> + * already mapped with the same attributes, including an inclusive match, the
> + * existing mapping is returned. This API is intended for mappings that exist
> + * transiently for a short period between calls to this function and
> + * `unmap_mm_range`.
> + *
> + * @param base      Base address of the range to map (inclusive).
> + * @param limit     Limit address of the range to map (exclusive).
> + * @param flags     Flags for the memory range to map.
> + * @return          Pointer to base of region on success, NULL on error.
> + */
> +void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags);
> +
> +/*
> + * Unmaps a range of memory if it was previously mapped by map_mm_range,
> + * otherwise it does not remove the mapping.
> + *
> + * @param base     Base address of the range to map (inclusive).
> + */
> +void unmap_mm_range(paddr_t base);
> +
>  /*
>   * Checks whether a given memory range is present in the provided table of
>   * MPU protection regions.
> diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
> index 33333181d5..52c4c43827 100644
> --- a/xen/arch/arm/mpu/mm.c
> +++ b/xen/arch/arm/mpu/mm.c
> @@ -332,31 +332,39 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
>      return 0;
>  }
>  
> -int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
> -                      bool transient)
> +static bool check_mpu_mapping(paddr_t base, paddr_t limit, unsigned int flags)
>  {
> -    int rc;
> -
>      if ( flags_has_rwx(flags) )
>      {
>          printk("Mappings should not be both Writeable and Executable\n");
> -        return -EINVAL;
> +        return false;
>      }
>  
>      if ( base >= limit )
>      {
>          printk("Base address %#"PRIpaddr" must be smaller than limit address %#"PRIpaddr"\n",
>                 base, limit);
> -        return -EINVAL;
> +        return false;
>      }
>  
>      if ( !IS_ALIGNED(base, PAGE_SIZE) || !IS_ALIGNED(limit, PAGE_SIZE) )
>      {
>          printk("base address %#"PRIpaddr", or limit address %#"PRIpaddr" is not page aligned\n",
>                 base, limit);
> -        return -EINVAL;
> +        return false;
>      }
>  
> +    return true;
> +}
> +
> +int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
> +                      bool transient)
> +{
> +    int rc;
> +
> +    if ( !check_mpu_mapping(base, limit, flags) )
> +        return -EINVAL;
> +
>      spin_lock(&xen_mpumap_lock);
>  
>      rc = xen_mpumap_update_entry(base, limit, flags, transient);
> @@ -465,10 +473,134 @@ void free_init_memory(void)
>      BUG_ON("unimplemented");
>  }
>  
> +static uint8_t is_mm_range_mapped(paddr_t start, paddr_t end)
> +{
> +    int rc;
> +    uint8_t idx;
> +
> +    ASSERT(spin_is_locked(&xen_mpumap_lock));
> +
> +    rc = mpumap_contains_region(xen_mpumap, max_mpu_regions, start, end, &idx);
> +    if ( rc < 0 )
> +         panic("Cannot handle overlapping MPU memory protection regions\n");
Why panic? This function is not used only at boot time and should propagate
error to the caller, it's also within a spin lock.

> +
> +    /*
> +     * 'idx' will be INVALID_REGION_IDX for rc == MPUMAP_REGION_NOTFOUND and
> +     * it will be a proper region index when rc >= MPUMAP_REGION_FOUND.
> +     */
> +    return idx;
> +}
> +
> +static bool is_mm_attr_match(pr_t *region, unsigned int attributes)
> +{
> +    bool ret = true;
> +
> +    if ( region->prbar.reg.ro != PAGE_RO_MASK(attributes) )
> +    {
> +        printk(XENLOG_WARNING
> +               "Mismatched Access Permission attributes (%#x0 instead of %#x0)\n",
> +               region->prbar.reg.ro, PAGE_RO_MASK(attributes));
> +        ret = false;
> +    }
> +
> +    if ( region->prbar.reg.xn != PAGE_XN_MASK(attributes) )
> +    {
> +        printk(XENLOG_WARNING
> +               "Mismatched Execute Never attributes (%#x instead of %#x)\n",
> +               region->prbar.reg.xn, PAGE_XN_MASK(attributes));
> +        ret = false;
> +    }
> +
> +    if ( region->prlar.reg.ai != PAGE_AI_MASK(attributes) )
> +    {
> +        printk(XENLOG_WARNING
> +               "Mismatched Memory Attribute Index (%#x instead of %#x)\n",
> +               region->prlar.reg.ai, PAGE_AI_MASK(attributes));
> +        ret = false;
> +    }
> +
> +    return ret;
> +}
> +
> +void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags)
> +{
> +    paddr_t start_pg = round_pgdown(base);
> +    paddr_t end_pg = round_pgup(limit);
> +    void *ret = NULL;
> +    uint8_t idx;
> +
> +    if ( !check_mpu_mapping(start_pg, end_pg, flags) )
> +        return NULL;
> +
> +    spin_lock(&xen_mpumap_lock);
> +
> +    idx = is_mm_range_mapped(start_pg, end_pg);
> +    if ( idx != INVALID_REGION_IDX )
> +    {
> +        /* Already mapped with different attributes */
> +        if ( !is_mm_attr_match(&xen_mpumap[idx], flags) )
> +        {
> +            printk(XENLOG_WARNING
> +                   "Range %#"PRIpaddr"-%#"PRIpaddr" already mapped with different flags\n",
> +                   start_pg, end_pg);
> +            goto out;
> +        }
> +
> +        /* Already mapped with same attributes */
> +        ret = maddr_to_virt(base);
> +        goto out;
> +    }
> +
> +    if ( !xen_mpumap_update_entry(start_pg, end_pg, flags, true) )
> +    {
> +        context_sync_mpu();
> +        ret = maddr_to_virt(base);
> +    }
> +
> + out:
> +    spin_unlock(&xen_mpumap_lock);
> +
> +    return ret;
> +}
> +
> +void unmap_mm_range(paddr_t base)
> +{
> +    uint8_t idx;
> +
> +    spin_lock(&xen_mpumap_lock);
> +
> +    /*
> +     * Mappings created via map_mm_range are at least PAGE_SIZE. Find the idx
> +     * of the MPU memory region containing `start` mapped through map_mm_range.
> +     */
> +    idx = is_mm_range_mapped(base, base + PAGE_SIZE);
> +    if ( idx == INVALID_REGION_IDX )
> +    {
> +        printk(XENLOG_ERR
> +               "Failed to unmap_mm_range MPU memory region at %#"PRIpaddr"\n",
> +               base);
> +        goto out;
> +    }
> +
> +    /* This API is only meant to unmap transient regions */
> +    if ( !region_is_transient(&xen_mpumap[idx]) )
So is this the only purpose of the transient flag? To check that unmap_mm_range
is used on the range that was mapped with map_mm_range? What would happen
without introducing this flag? You already check for the matching attributes.

~Michal



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To: "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
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From: Jan Beulich 
Subject: [PATCH] x86: introduce "hot" and "cold" page copying functions
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The present copy_page_sse2() is useful in case the destination page isn't
going to get touched again soon, or if we want to limit churn on the
caches. Just rename it, to fit the corresponding {clear,scrub}_page_*()
naming scheme.

For cases where latency is the most important aspect, or when it is
expected that sufficiently large parts of a destination page will get
accessed again soon after the copying, introduce a "hot" alternative.
Again use alternatives patching to select between a "legacy" and an ERMS
variant.

Don't switch any callers just yet - this will be the subject of subsequent
changes.

Signed-off-by: Jan Beulich 
---
Of course both pages can be independently hot/cold, and hence more flavors
may be necessary here.

To avoid the NOP padding (also in clear_page_hot()) we could use a double
REP prefix in the replacement code (accounting for the REX one in the code
being replaced).

--- a/xen/arch/x86/copy_page.S
+++ b/xen/arch/x86/copy_page.S
@@ -13,7 +13,7 @@
 #define tmp3_reg %r10
 #define tmp4_reg %r11
 
-FUNC(copy_page_sse2)
+FUNC(copy_page_cold)
         mov     $PAGE_SIZE/(4*WORD_SIZE)-3, %ecx
 
         prefetchnta 2*4*WORD_SIZE(src_reg)
@@ -44,4 +44,19 @@ FUNC(copy_page_sse2)
 
         sfence
         RET
-END(copy_page_sse2)
+END(copy_page_cold)
+
+        .macro copy_page_movsb
+        mov     $PAGE_SIZE, %ecx
+        rep movsb
+        .endm
+
+        .macro copy_page_movsq
+        mov     $PAGE_SIZE/8, %ecx
+        rep movsq
+        .endm
+
+FUNC(copy_page_hot)
+        ALTERNATIVE copy_page_movsq, copy_page_movsb, X86_FEATURE_ERMS
+        RET
+END(copy_page_hot)
--- a/xen/arch/x86/include/asm/page.h
+++ b/xen/arch/x86/include/asm/page.h
@@ -221,10 +221,11 @@ typedef struct { u64 pfn; } pagetable_t;
 
 void clear_page_hot(void *pg);
 void clear_page_cold(void *pg);
-void copy_page_sse2(void *to, const void *from);
+void copy_page_hot(void *to, const void *from);
+void copy_page_cold(void *to, const void *from);
 
 #define clear_page(_p)      clear_page_cold(_p)
-#define copy_page(_t, _f)   copy_page_sse2(_t, _f)
+#define copy_page(_t, _f)   copy_page_cold(_t, _f)
 
 #ifdef CONFIG_DEBUG
 void scrub_page_hot(void *ptr);


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On 27/08/2025 19:04, Hari Limaye wrote:
> Hi Michal,
> 
>> And actually, this could be calculated
>> in init_pdx() next to max_page to avoid requiring each arch (arm32, arm64, mpu)
>> to set it exactly the same.
> 
> I have not implemented this in this series, as it seems like an unrelated change that should go separately. However if you prefer I can re-spin with this change also?
No need, it can be done in the future.

~Michal



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On 28.08.2025 11:17, Jan Beulich wrote:
> The present copy_page_sse2() is useful in case the destination page isn't
> going to get touched again soon, or if we want to limit churn on the
> caches. Just rename it, to fit the corresponding {clear,scrub}_page_*()
> naming scheme.
> 
> For cases where latency is the most important aspect, or when it is
> expected that sufficiently large parts of a destination page will get
> accessed again soon after the copying, introduce a "hot" alternative.
> Again use alternatives patching to select between a "legacy" and an ERMS
> variant.
> 
> Don't switch any callers just yet - this will be the subject of subsequent
> changes.
> 
> Signed-off-by: Jan Beulich 

The ERMS series had been pending for so long that I had forgotten that this
further change was yet to be done. I think this patch should be considered
part of that earlier series. Yet then it may of course require some more
discussion to get it into final shape. Would be nice though to have a
consistent set in 4.21 ...

Jan


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On 27/08/2025 18:35, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Implement `setup_mm` for MPU systems. This variant doesn't need to set
> up the direct map.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
Reviewed-by: Michal Orzel 

~Michal



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Subject: Re: [PATCH v2 3/5] arm/mpu: Implement transient mapping
To: Hari Limaye , 
CC: , Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Volodymyr Babchuk 
References: 
 <80b0b3f84ae73f7d92d1b1cfe057ffc438882725.1756312498.git.hari.limaye@arm.com>
From: "Orzel, Michal" 
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On 27/08/2025 18:35, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Add a scheme to distinguish transient MPU regions, to identify MPU
> regions which will be mapped for a short period of time. This is needed
> for the functions which transiently map and unmap memory ranges on
> demand which will be introduced in a future commit.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
> ---
> Changes from v1:
> - Improve commit message
> - Mark parameter in read helper as const
> ---
>  xen/arch/arm/include/asm/arm32/mpu.h     |  2 ++
>  xen/arch/arm/include/asm/arm64/mpu.h     |  2 ++
>  xen/arch/arm/include/asm/mpu/mm.h        | 14 +++++++++++++-
>  xen/arch/arm/include/asm/mpu/regions.inc | 19 +++++++++++++++++--
>  xen/arch/arm/mpu/mm.c                    | 23 ++++++++++++++---------
>  5 files changed, 48 insertions(+), 12 deletions(-)
> 
> diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/asm/arm32/mpu.h
> index 0a6930b3a0..9906d98809 100644
> --- a/xen/arch/arm/include/asm/arm32/mpu.h
> +++ b/xen/arch/arm/include/asm/arm32/mpu.h
> @@ -39,6 +39,8 @@ typedef union {
>  typedef struct {
>      prbar_t prbar;
>      prlar_t prlar;
> +    bool transient;
Do we expect to have any other flags? If so, it could make sense to use a
bitfield right away.

> +    uint8_t pad[7]; /* Pad structure to 16 Bytes */
>  } pr_t;
>  
>  #endif /* __ASSEMBLY__ */
> diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/asm/arm64/mpu.h
> index f0ce344e78..1d1843eda0 100644
> --- a/xen/arch/arm/include/asm/arm64/mpu.h
> +++ b/xen/arch/arm/include/asm/arm64/mpu.h
> @@ -38,6 +38,8 @@ typedef union {
>  typedef struct {
>      prbar_t prbar;
>      prlar_t prlar;
> +    bool transient;
> +    uint8_t pad[15]; /* Pad structure to 32 Bytes */
>  } pr_t;
>  
>  #endif /* __ASSEMBLY__ */
> diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
> index e1ded6521d..566d338986 100644
> --- a/xen/arch/arm/include/asm/mpu/mm.h
> +++ b/xen/arch/arm/include/asm/mpu/mm.h
> @@ -55,6 +55,16 @@ static inline void context_sync_mpu(void)
>      isb();
>  }
>  
> +static inline bool region_is_transient(const pr_t *pr)
> +{
> +    return pr->transient;
> +}
> +
> +static inline void region_set_transient(pr_t *pr, bool transient)
> +{
> +    pr->transient = transient;
> +}
> +
>  /*
>   * The following API requires context_sync_mpu() after being used to modify MPU
>   * regions:
> @@ -75,9 +85,11 @@ void write_protection_region(const pr_t *pr_write, uint8_t sel);
>   * @param base      Base address of the range to map (inclusive).
>   * @param limit     Limit address of the range to map (exclusive).
>   * @param flags     Flags for the memory range to map.
> + * @param transient True for a transient mapping, otherwise False.
>   * @return          0 on success, negative on error.
>   */
> -int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags);
> +int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
> +                      bool transient);
>  
>  /*
>   * Creates a pr_t structure describing a protection region.
> diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/include/asm/mpu/regions.inc
> index 23fead3b21..f9892fe3d8 100644
> --- a/xen/arch/arm/include/asm/mpu/regions.inc
> +++ b/xen/arch/arm/include/asm/mpu/regions.inc
> @@ -14,19 +14,31 @@
>  #define PRLAR_ELx_EN            0x1
>  
>  #ifdef CONFIG_ARM_64
> -#define XEN_MPUMAP_ENTRY_SHIFT  0x4     /* 16 byte structure */
> +#define XEN_MPUMAP_ENTRY_SHIFT        0x5   /* 32 byte structure */
> +#define XEN_MPUMAP_ENTRY_ZERO_OFFSET  0x10  /* {PRBAR, PRLAR} is 16 bytes  */
To avoid having to update this over and over again, maybe define a macro using
OFFSET?

Other than that:
Reviewed-by: Michal Orzel 

~Michal


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Date: Thu, 28 Aug 2025 10:51:51 +0200
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Subject: Re: [PATCH v2 5/5] xen/arm: map static memory on demand
To: Hari Limaye , 
CC: , Penny Zheng , "Stefano
 Stabellini" , Julien Grall ,
	"Bertrand Marquis" , Volodymyr Babchuk
	, Andrew Cooper ,
	Anthony PERARD , Jan Beulich ,
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Wei Chen
	
References: 
 <6408f218f3075acd43f5563bff26165091d9f184.1756312498.git.hari.limaye@arm.com>
From: "Orzel, Michal" 
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On 27/08/2025 18:35, Hari Limaye wrote:
> From: Penny Zheng 
> 
> In the function `init_staticmem_pages` we need to have mapped static
> memory banks for initialization. Unlike on an MMU system, we cannot map
> the entire RAM on an MPU system as we have a limited number of MPU
> memory regions. To solve this, transiently map the static memory banks
> for initialization.
> 
> Signed-off-by: Penny Zheng 
> Signed-off-by: Wei Chen 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
Reviewed-by: Michal Orzel 

~Michal



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Subject: Re: [PATCH] x86/PSR: move CPUID level check
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On 27/08/2025 9:16 am, Jan Beulich wrote:
> At the first (and maybe second) glance the call to setup_clear_cpu_cap()
> (which is __init) from psr_cpu_init() (which isn't) looks wrong. The
> earlier cpu_has_pqe makes it safe, though. Nevertheless we can do better,
> by simply moving the check ahead of the BSP invocation of the function.
>
> Signed-off-by: Jan Beulich 

Acked-by: Andrew Cooper 

This is still terribly convoluted code.


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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[PATCH]=20hvmloader:=20Update=20to=20SMBIOS=202.6?=
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Le 28/08/2025 =C3=A0 09:08, Jan Beulich a =C3=A9crit=C2=A0:
> On 22.08.2025 15:47, Teddy Astie wrote:
>> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
>> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
>>
>> In Linux, if the SMBIOS version is >=3D 2.6, the GUID format is used, el=
se
>> (undefined as per SMBIOS spec), big endian is used (used by Xen). Theref=
ore,
>> you have a endian mismatch causing the UUIDs to mismatch in the guest.
>>
>> $ cat /sys/hypervisor/uuid
>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>> $ cat /sys/devices/virtual/dmi/id/product_uuid
>> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
>> $ cat /sys/devices/virtual/dmi/id/product_serial
>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>
>> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
>> written in the table; which effectively fix this endianness mismatch wit=
h
>> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.
> 
> To update to 2.6, fields new in 2.6 (compared to 2.4) need adding to the
> various structures. First example I ran into is type 4, gaining 5 new
> fields in 2.5.
> 

Yes, I add them in a new version along with 2.6 entries for the newly 
introduced SMBIOS tables (notably type 9).

> Jan
> 

Teddy


Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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In-Reply-To: 
From: Mark Syms 
Date: Thu, 28 Aug 2025 10:28:44 +0100
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Subject: Re: [PATCH] [xen-block] Return BLKIF_RSP_EOPNOTSUPP for unknown operation
Cc: qemu-devel@nongnu.org, xen-devel@lists.xenproject.org, 
	sstabellini@kernel.org, anthony@xenproject.org, paul@xen.org
Content-Type: text/plain; charset="UTF-8"

> The comment in blkif.h contains:
>
>  /* Operation not supported (only happens on barrier writes). */
> #define BLKIF_RSP_EOPNOTSUPP  -2
>
> So in principle BLKIF_RSP_EOPNOTSUPP is only to be used as a response
> for BLKIF_OP_WRITE_BARRIER or BLKIF_OP_FLUSH_DISKCACHE requests,
> however blkback already uses it as a response to unknown request
> types (like you propose here).
>
> Would you mind also sending a patch to adjust blkif.h in Xen to remove
> the "(only happens on barrier writes)" part of the comment?

Sure, no problem


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Hi Michal,

>>=20
>> +    rc =3D mpumap_contains_region(xen_mpumap, max_mpu_regions, start, e=
nd, &idx);
>> +    if ( rc < 0 )
>> +         panic("Cannot handle overlapping MPU memory protection regions=
\n");
> Why panic? This function is not used only at boot time and should propaga=
te
> error to the caller, it's also within a spin lock.

Good point - I will update this to propagate the error in the next version =
of the series.

>> +    /* This API is only meant to unmap transient regions */
>> +    if ( !region_is_transient(&xen_mpumap[idx]) )
> So is this the only purpose of the transient flag? To check that unmap_mm=
_range
> is used on the range that was mapped with map_mm_range? What would happen
> without introducing this flag? You already check for the matching attribu=
tes.
>=20
> ~Michal
>=20

Yes this is the purpose of the transient flag - we want to ensure that a ca=
ll to unmap_mm_range only destroys a mapping that was created by a matching=
 call to map_mm_range. Due to the fact that map_mm_range may not create a m=
apping in the instance that one already exists - `/* Already mapped with sa=
me attributes */` - we need this check to ensure that unmap_mm_range will n=
ot destroy a pre-existing mapping.

Many thanks,
Hari



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	roger.pau@citrix.com,
	andrew.cooper3@citrix.com,
	xen-devel@lists.xenproject.org
Cc: Mark Syms 
Subject: [PATCH] Clarify the cases where BLKIF_RSP_EOPNOTSUPP can be returned.
Date: Thu, 28 Aug 2025 10:38:21 +0100
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Previously this said it would only happen on barrier writes. Except
the documentation blocks for
 * feature-flush-cache
 * feature-discard

Also say that they can return this error.

Signed-off-by: Mark Syms 
---
 xen/include/public/io/blkif.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/include/public/io/blkif.h b/xen/include/public/io/blkif.h
index 8407453324..5e617b0c67 100644
--- a/xen/include/public/io/blkif.h
+++ b/xen/include/public/io/blkif.h
@@ -710,7 +710,7 @@ typedef struct blkif_response blkif_response_t;
 /*
  * STATUS RETURN CODES.
  */
- /* Operation not supported (only happens on barrier writes). */
+ /* Operation not supported, see feature-barrier, feature-flush-cache, feature-discard. */
 #define BLKIF_RSP_EOPNOTSUPP  -2
  /* Operation failed for some unspecified reason (-EIO). */
 #define BLKIF_RSP_ERROR       -1
-- 
2.50.1



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Fix an issue in the 'fail:' cleanup path of the 'assign_shared_memory()'
function where the use of an unsigned long 'i' with the condition
'--i >=3D 0' caused an infinite loop. Update the loop to use 'i--',
ensuring correct loop termination.

This change adheres to MISRA C Rule 14.3: "Controlling expressions shall
not be invariant."

Fixes: 72c5fa2208 (device-tree: Move Arm's static-shmem feature to common, =
2025-06-03)
Signed-off-by: Dmytro Prokopchuk 
---
Changes to v2:
- added Fixes tag
- updated the loop to use 'i--'
- updated commit message accordingly

Link to v1:
https://patchew.org/Xen/d7768394209c65cfef4006c3ffc0a0f5d82c4c18.1756368997=
.git.dmytro._5Fprokopchuk1@epam.com/
---
 xen/common/device-tree/static-shmem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/common/device-tree/static-shmem.c b/xen/common/device-tree=
/static-shmem.c
index 8023c0a484..79f23caa77 100644
--- a/xen/common/device-tree/static-shmem.c
+++ b/xen/common/device-tree/static-shmem.c
@@ -185,7 +185,7 @@ static int __init assign_shared_memory(struct domain *d=
, paddr_t gbase,
     return 0;
=20
  fail:
-    while ( --i >=3D 0 )
+    while ( i-- )
         put_page_nr(page + i, nr_borrowers);
     return ret;
 }
--=20
2.43.0


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From: Hari Limaye 
To: "Orzel, Michal" 
CC: "xen-devel@lists.xenproject.org" , Luca
 Fancellu , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Volodymyr Babchuk 
Subject: Re: [PATCH v2 3/5] arm/mpu: Implement transient mapping
Thread-Topic: [PATCH v2 3/5] arm/mpu: Implement transient mapping
Thread-Index: AQHcF/1H84gXhbGzU0K5yIusBBold7R3z2EA
Date: Thu, 28 Aug 2025 09:40:19 +0000
Message-ID: <4FA3E89D-A3F1-4A80-9E76-CF7544FD5795@arm.com>
References: 
 <80b0b3f84ae73f7d92d1b1cfe057ffc438882725.1756312498.git.hari.limaye@arm.com>
 
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Hi Michal,

>> +++ b/xen/arch/arm/include/asm/arm32/mpu.h
>> @@ -39,6 +39,8 @@ typedef union {
>> typedef struct {
>>     prbar_t prbar;
>>     prlar_t prlar;
>> +    bool transient;
> Do we expect to have any other flags? If so, it could make sense to use a
> bitfield right away.
Yes, at least one more flag at present - I will update this to use a bitfie=
ld in the next version of the series.


>> #ifdef CONFIG_ARM_64
>> -#define XEN_MPUMAP_ENTRY_SHIFT  0x4     /* 16 byte structure */
>> +#define XEN_MPUMAP_ENTRY_SHIFT        0x5   /* 32 byte structure */
>> +#define XEN_MPUMAP_ENTRY_ZERO_OFFSET  0x10  /* {PRBAR, PRLAR} is 16 byt=
es  */
> To avoid having to update this over and over again, maybe define a macro =
using
> OFFSET?
>=20
> Other than that:
> Reviewed-by: Michal Orzel 
>=20
> ~Michal

Good point - I will do this in the next version of the series.

Many thanks,
Hari=


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Subject: Re: [PATCH v2 4/5] arm/mpu: Implement ioremap_attr for MPU
To: Hari Limaye 
CC: "xen-devel@lists.xenproject.org" , "Luca
 Fancellu" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Volodymyr Babchuk 
References: 
 
 <3f59b4ff-31f0-4801-96ba-83df139af081@amd.com>
 
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On 28/08/2025 11:37, Hari Limaye wrote:
> Hi Michal,
> 
>>>
>>> +    rc = mpumap_contains_region(xen_mpumap, max_mpu_regions, start, end, &idx);
>>> +    if ( rc < 0 )
>>> +         panic("Cannot handle overlapping MPU memory protection regions\n");
>> Why panic? This function is not used only at boot time and should propagate
>> error to the caller, it's also within a spin lock.
> 
> Good point - I will update this to propagate the error in the next version of the series.
> 
>>> +    /* This API is only meant to unmap transient regions */
>>> +    if ( !region_is_transient(&xen_mpumap[idx]) )
>> So is this the only purpose of the transient flag? To check that unmap_mm_range
>> is used on the range that was mapped with map_mm_range? What would happen
>> without introducing this flag? You already check for the matching attributes.
>>
>> ~Michal
>>
> 
> Yes this is the purpose of the transient flag - we want to ensure that a call to unmap_mm_range only destroys a mapping that was created by a matching call to map_mm_range. Due to the fact that map_mm_range may not create a mapping in the instance that one already exists - `/* Already mapped with same attributes */` - we need this check to ensure that unmap_mm_range will not destroy a pre-existing mapping.
Ok, understood.

~Michal



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MIME-Version: 1.0
Date: Thu, 28 Aug 2025 11:47:05 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org, Stefano Stabellini
 , Julien Grall , Bertrand Marquis
 , Michal Orzel 
Subject: Re: [PATCH v2] device-tree: fix infinite loop issue in
 'assign_shared_memory()'
In-Reply-To: <0e562f695e5db87ab80dde69cbcc0cfa14f94b21.1756373770.git.dmytro_prokopchuk1@epam.com>
References: <0e562f695e5db87ab80dde69cbcc0cfa14f94b21.1756373770.git.dmytro_prokopchuk1@epam.com>
Message-ID: <861c88c005b041fa622310d6bef63c25@bugseng.com>
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On 2025-08-28 11:39, Dmytro Prokopchuk1 wrote:
> Fix an issue in the 'fail:' cleanup path of the 
> 'assign_shared_memory()'
> function where the use of an unsigned long 'i' with the condition
> '--i >= 0' caused an infinite loop. Update the loop to use 'i--',
> ensuring correct loop termination.
> 
> This change adheres to MISRA C Rule 14.3: "Controlling expressions 
> shall
> not be invariant."
> 
> Fixes: 72c5fa2208 (device-tree: Move Arm's static-shmem feature to 
> common, 2025-06-03)

The format should be

Fixes: 72c5fa220804 ("device-tree: Move Arm's static-shmem feature to 
common")

can be fixed on commit probably

> Signed-off-by: Dmytro Prokopchuk 
> ---
> Changes to v2:
> - added Fixes tag
> - updated the loop to use 'i--'
> - updated commit message accordingly
> 
> Link to v1:
> https://patchew.org/Xen/d7768394209c65cfef4006c3ffc0a0f5d82c4c18.1756368997.git.dmytro._5Fprokopchuk1@epam.com/
> ---
>  xen/common/device-tree/static-shmem.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/xen/common/device-tree/static-shmem.c 
> b/xen/common/device-tree/static-shmem.c
> index 8023c0a484..79f23caa77 100644
> --- a/xen/common/device-tree/static-shmem.c
> +++ b/xen/common/device-tree/static-shmem.c
> @@ -185,7 +185,7 @@ static int __init assign_shared_memory(struct 
> domain *d, paddr_t gbase,
>      return 0;
> 
>   fail:
> -    while ( --i >= 0 )
> +    while ( i-- )
>          put_page_nr(page + i, nr_borrowers);
>      return ret;
>  }

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Date: Thu, 28 Aug 2025 11:50:28 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich , Jason Andryuk 
Cc: Xen-devel 
Subject: Re: MCA hypercall with PVH
Message-ID: 
References: <318f8ef3-aa52-421b-b9cb-6cd6139e1dd1@amd.com>
 
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In-Reply-To: 

On Thu, Aug 28, 2025 at 10:48:49AM +0200, Jan Beulich wrote:
> On 28.08.2025 03:22, Jason Andryuk wrote:
> > The MCA hypercall, do_mca(), is only available for PV.  That is, it's 
> > only added to the hypercall table for PV.  Is there a particular reason 
> > it was omitted from PVH, or did PVH dom0 just not exist?
> 
> PVH Dom0 didn't exist back at the time, yes, but it's more than this. The
> hypercall, in some places, deals with MFNs, which aren't "visible" to PVH
> Dom0. IOW enabling it (perhaps just partly) would need to be done with
> extra care.

I think there's also a question of whether we want to use a PV
interface here, or try for Xen to mediate between the hardware domain
and the native interface, possibly exposing some kind of partially
emulated view that matches the native interface, and thus avoids
having to use a PV driver in the hardware domain.

I've opened a GitLab ticket long ago about MCE:

https://gitlab.com/xen-project/xen/-/issues/101

But didn't look into it.  I think we need some prior investigation to
figure out whether it would be feasible to expose a native MCA
interface to the hardware domain, as that would be the preference for
PVH (rather than re-using the classic PV interfaces).

The main barrier here is the disassociation between the hardware
domain physical memory map versus the host one, as the MCE/MCA
drivers will need to operate based on the host memory map, not the
one used by the hardware domain.

I think (some?) of the MSRs also contain CPU specific status/errors,
and hence using a native interface would require the hardware domain
vCPU count to be equal to the host pCPU count.

Nit: I've just taken a quick look at do_mca() but it looked like the
sharing of the data would be better done using acquire_resource if
possible, as to avoid repeated hypercalls.

Thanks, Roger.


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Subject: Re: [PATCH v2] device-tree: fix infinite loop issue in
 'assign_shared_memory()'
To: Nicola Vetrini ,
 Dmytro Prokopchuk1 
Cc: xen-devel@lists.xenproject.org,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel 
References: <0e562f695e5db87ab80dde69cbcc0cfa14f94b21.1756373770.git.dmytro_prokopchuk1@epam.com>
 <861c88c005b041fa622310d6bef63c25@bugseng.com>
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From: Andrew Cooper 
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On 28/08/2025 10:47 am, Nicola Vetrini wrote:
> On 2025-08-28 11:39, Dmytro Prokopchuk1 wrote:
>> Fix an issue in the 'fail:' cleanup path of the 'assign_shared_memory()'
>> function where the use of an unsigned long 'i' with the condition
>> '--i >= 0' caused an infinite loop. Update the loop to use 'i--',
>> ensuring correct loop termination.
>>
>> This change adheres to MISRA C Rule 14.3: "Controlling expressions shall
>> not be invariant."
>>
>> Fixes: 72c5fa2208 (device-tree: Move Arm's static-shmem feature to
>> common, 2025-06-03)
>
> The format should be
>
> Fixes: 72c5fa220804 ("device-tree: Move Arm's static-shmem feature to
> common")
>
> can be fixed on commit probably

It can, but that's the wrong Fixes tag.  That commit simply moved the
bad logic.

Commit 041957bad382 ("xen/arm: Add additional reference to owner domain
when the owner is allocated") is the one that introduced the bad expression.

~Andrew


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Date: Thu, 28 Aug 2025 11:01:21 +0100
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Subject: Re: [PATCH] hvmloader: Update to SMBIOS 2.6
To: Jan Beulich , Teddy Astie 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD , xen-devel@lists.xenproject.org
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On 28/08/2025 8:07 am, Jan Beulich wrote:
> On 27.08.2025 19:47, Andrew Cooper wrote:
>> On 22/08/2025 2:47 pm, Teddy Astie wrote:
>>> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
>>> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
>>>
>>> In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
>>> (undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
>>> you have a endian mismatch causing the UUIDs to mismatch in the guest.
>>>
>>> $ cat /sys/hypervisor/uuid
>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>> $ cat /sys/devices/virtual/dmi/id/product_uuid
>>> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
>>> $ cat /sys/devices/virtual/dmi/id/product_serial
>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>>
>>> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
>>> written in the table; which effectively fix this endianness mismatch with
>>> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.
>>>
>>> Signed-off-by: Teddy Astie 
>>> ---
>>> This effectively changes the UUID seen with UEFI guests as it was
>>> actually inconsistent with SeaBIOS and SMBIOS expectations.
>>> ---
>> I agree this is a real bug and needs fixing.
> Hmm, I didn't realize this is a bug, and hence put the patch off as 4.22
> material. If there is a bug being fixed: Teddy, please add a Fixes: tag.

I'm not sure if this has a reasonable Fixes tag.

It's a combination of an ill-specified domain handle format, and using
an ill-specified version of the SMBios spec.

~Andrew


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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	, Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD
	, Michal Orzel , "Julien
 Grall" , Stefano Stabellini 
Subject: [PATCH v8 1/8] xen/cpufreq: introduce new sub-hypercall to propagate CPPC data
Date: Thu, 28 Aug 2025 18:01:58 +0800
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In order to provide backward compatibility with existing governors
that represent performance as frequency, like ondemand, the _CPC
table can optionally provide processor frequency range values, Lowest
frequency and Nominal frequency, to let OS use Lowest Frequency/
Performance and Nominal Frequency/Performance as anchor points to
create linear mapping of CPPC performance to CPU frequency.

As Xen is uncapable of parsing the ACPI dynamic table, we'd like to
introduce a new sub-hypercall "XEN_PM_CPPC" to propagate required CPPC
data from dom0 kernel to Xen.
In the according handler set_cppc_pminfo(), we do _CPC and _PSD
sanitization check, as both _PSD and _CPC info are necessary for correctly
initializing cpufreq cores in CPPC mode.
Users shall be warned that if we failed at this point,
no fallback scheme, like legacy P-state could be switched to.

A new flag "XEN_CPPC_INIT" is also introduced for cpufreq core initialised in
CPPC mode. Then all .init flag checking shall be updated to
consider "XEN_CPPC_INIT" too.

We want to bypass construction of px statistic info in cpufreq_statistic_init()
for CPPC mode, while not bypassing cpufreq_statistic_lock initialization for a
good reason. The same check is unnecessary for cpufreq_statistic_exit(),
since it has already been covered by px statistic variable
"cpufreq_statistic_data" check

Signed-off-by: Penny Zheng 
---
v1 -> v2:
- Give the variable des_perf an initializer of 0
- Use the strncmp()s directly in the if()
---
v3 -> v4
- refactor comments
- remove double blank lines
- replace amd_cppc_in_use flag with XEN_PROCESSOR_PM_CPPC
---
v4 -> v5:
- add new field "policy" in "struct xen_cppc_para"
- add new performamce policy XEN_CPUFREQ_POLICY_BALANCE
- drop string comparisons with "processor_pminfo[cpuid]->init & XEN_CPPC_INIT"
and "cpufreq.setpolicy == NULL"
- Blank line ahead of the main "return" of a function
- refactor comments, commit message and title
---
v5 -> v6:
- remove duplicated manifest constants, and just move it to public header
- use "else if" to avoid confusion that it looks as if both paths could be taken
- add check for legitimate perf values
- use "unknown" instead of "none"
- introduce "CPUFREQ_POLICY_END" for array overrun check in user space tools
---
v6 -> v7:
- use ARRAY_SIZE() instead
- ->policy print is avoided in passive mode and print "unknown" in invalid
cases
- let cpufreq_is_governorless() being the variable's initializer
- refactor with the conditional operator to increase readability
- move duplicated defination ahead and use local variable
- avoid using "else-condition" to bring "dead code" in Misra's nomeclature
- move the comment out of public header and into the respective internal
struct field
- wrap set{,get}_amd_cppc_para() with CONFIG_PM_OP
- add symmetry scenario for maximum check
---
v7 -> v8:
- replace -EFAULT with -ENOMEM
- indent fix
- add comment for state_count check for CPPC mode
---
 xen/arch/x86/platform_hypercall.c         |   5 +
 xen/arch/x86/x86_64/cpufreq.c             |  19 ++++
 xen/arch/x86/x86_64/platform_hypercall.c  |   3 +
 xen/drivers/acpi/pm-op.c                  |   7 +-
 xen/drivers/acpi/pmstat.c                 |   4 +
 xen/drivers/cpufreq/cpufreq.c             | 124 +++++++++++++++++++++-
 xen/include/acpi/cpufreq/processor_perf.h |   4 +-
 xen/include/public/platform.h             |  26 +++++
 xen/include/xen/pmstat.h                  |   5 +
 xen/include/xlat.lst                      |   1 +
 10 files changed, 193 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c
index 21f9f795c1..fafc176475 100644
--- a/xen/arch/x86/platform_hypercall.c
+++ b/xen/arch/x86/platform_hypercall.c
@@ -577,6 +577,11 @@ ret_t do_platform_op(
             break;
         }
 
+        case XEN_PM_CPPC:
+            ret = set_cppc_pminfo(op->u.set_pminfo.id,
+                                  &op->u.set_pminfo.u.cppc_data);
+            break;
+
         default:
             ret = -EINVAL;
             break;
diff --git a/xen/arch/x86/x86_64/cpufreq.c b/xen/arch/x86/x86_64/cpufreq.c
index e4f3d5b436..525b29da71 100644
--- a/xen/arch/x86/x86_64/cpufreq.c
+++ b/xen/arch/x86/x86_64/cpufreq.c
@@ -54,3 +54,22 @@ int compat_set_px_pminfo(uint32_t acpi_id,
 
     return set_px_pminfo(acpi_id, xen_perf);
 }
+
+int compat_set_cppc_pminfo(unsigned int acpi_id,
+                           const struct compat_processor_cppc *cppc_data)
+
+{
+    struct xen_processor_cppc *xen_cppc;
+    unsigned long xlat_page_current;
+
+    xlat_malloc_init(xlat_page_current);
+
+    xen_cppc = xlat_malloc_array(xlat_page_current,
+                                 struct xen_processor_cppc, 1);
+    if ( unlikely(xen_cppc == NULL) )
+        return -ENOMEM;
+
+    XLAT_processor_cppc(xen_cppc, cppc_data);
+
+    return set_cppc_pminfo(acpi_id, xen_cppc);
+}
diff --git a/xen/arch/x86/x86_64/platform_hypercall.c b/xen/arch/x86/x86_64/platform_hypercall.c
index 9ab631c17f..0288f68df9 100644
--- a/xen/arch/x86/x86_64/platform_hypercall.c
+++ b/xen/arch/x86/x86_64/platform_hypercall.c
@@ -14,6 +14,9 @@ EMIT_FILE;
 #define efi_get_info        efi_compat_get_info
 #define efi_runtime_call(x) efi_compat_runtime_call(x)
 
+#define xen_processor_cppc  compat_processor_cppc
+#define set_cppc_pminfo     compat_set_cppc_pminfo
+
 #define xen_processor_performance compat_processor_performance
 #define set_px_pminfo       compat_set_px_pminfo
 
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index 9a1970df34..e3b5c8bcaa 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -91,7 +91,10 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
     pmpt = processor_pminfo[op->cpuid];
     policy = per_cpu(cpufreq_cpu_policy, op->cpuid);
 
-    if ( !pmpt || !pmpt->perf.states ||
+    if ( !pmpt ||
+         ((pmpt->init & XEN_PX_INIT) && !pmpt->perf.states) ||
+         /* Avoid NULL deref of pmpt->perf.states[] */
+         ((pmpt->init & XEN_CPPC_INIT) && pmpt->perf.state_count) ||
          !policy || !policy->governor )
         return -EINVAL;
 
@@ -351,7 +354,7 @@ int do_pm_op(struct xen_sysctl_pm_op *op)
     case CPUFREQ_PARA:
         if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_PX) )
             return -ENODEV;
-        if ( !pmpt || !(pmpt->init & XEN_PX_INIT) )
+        if ( !pmpt || !(pmpt->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
             return -EINVAL;
         break;
     }
diff --git a/xen/drivers/acpi/pmstat.c b/xen/drivers/acpi/pmstat.c
index 4fae0c14af..0f31736df2 100644
--- a/xen/drivers/acpi/pmstat.c
+++ b/xen/drivers/acpi/pmstat.c
@@ -108,6 +108,10 @@ int cpufreq_statistic_init(unsigned int cpu)
     if ( !pmpt )
         return -EINVAL;
 
+    /* Only need to initialize in Px mode */
+    if ( !(pmpt->init & XEN_PX_INIT) )
+        return 0;
+
     spin_lock(cpufreq_statistic_lock);
 
     pxpt = per_cpu(cpufreq_statistic_data, cpu);
diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c
index 267e4d3f3b..c6ce31c0ac 100644
--- a/xen/drivers/cpufreq/cpufreq.c
+++ b/xen/drivers/cpufreq/cpufreq.c
@@ -40,6 +40,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -234,6 +235,11 @@ static int get_psd_info(unsigned int cpu, unsigned int *shared_type,
         *domain_info = &processor_pminfo[cpu]->perf.domain_info;
         break;
 
+    case XEN_CPPC_INIT:
+        *shared_type = processor_pminfo[cpu]->cppc_data.shared_type;
+        *domain_info = &processor_pminfo[cpu]->cppc_data.domain_info;
+        break;
+
     default:
         ret = -EINVAL;
         break;
@@ -259,7 +265,7 @@ int cpufreq_add_cpu(unsigned int cpu)
     if ( !processor_pminfo[cpu] || !cpu_online(cpu) )
         return -EINVAL;
 
-    if ( !(processor_pminfo[cpu]->init & XEN_PX_INIT) )
+    if ( !(processor_pminfo[cpu]->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
         return -EINVAL;
 
     if (!cpufreq_driver.init)
@@ -434,7 +440,7 @@ int cpufreq_del_cpu(unsigned int cpu)
     if ( !processor_pminfo[cpu] || !cpu_online(cpu) )
         return -EINVAL;
 
-    if ( !(processor_pminfo[cpu]->init & XEN_PX_INIT) )
+    if ( !(processor_pminfo[cpu]->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
         return -EINVAL;
 
     if (!per_cpu(cpufreq_cpu_policy, cpu))
@@ -693,6 +699,120 @@ int acpi_set_pdc_bits(unsigned int acpi_id, XEN_GUEST_HANDLE(uint32) pdc)
     return ret;
 }
 
+static void print_CPPC(const struct xen_processor_cppc *cppc_data)
+{
+    printk("\t_CPC: highest_perf=%u, lowest_perf=%u, "
+           "nominal_perf=%u, lowest_nonlinear_perf=%u, "
+           "nominal_mhz=%uMHz, lowest_mhz=%uMHz\n",
+           cppc_data->cpc.highest_perf, cppc_data->cpc.lowest_perf,
+           cppc_data->cpc.nominal_perf, cppc_data->cpc.lowest_nonlinear_perf,
+           cppc_data->cpc.nominal_mhz, cppc_data->cpc.lowest_mhz);
+}
+
+int set_cppc_pminfo(unsigned int acpi_id,
+                    const struct xen_processor_cppc *cppc_data)
+{
+    int ret = 0, cpuid;
+    struct processor_pminfo *pm_info;
+
+    cpuid = get_cpu_id(acpi_id);
+    if ( cpuid < 0 )
+    {
+        ret = -EINVAL;
+        goto out;
+    }
+
+    if ( cppc_data->pad[0] || cppc_data->pad[1] || cppc_data->pad[2] )
+    {
+        ret = -EINVAL;
+        goto out;
+    }
+
+    if ( cpufreq_verbose )
+        printk("Set CPU%d (ACPI ID %u) CPPC state info:\n",
+               cpuid, acpi_id);
+
+    pm_info = processor_pminfo[cpuid];
+    if ( !pm_info )
+    {
+        pm_info = xvzalloc(struct processor_pminfo);
+        if ( !pm_info )
+        {
+            ret = -ENOMEM;
+            goto out;
+        }
+        processor_pminfo[cpuid] = pm_info;
+    }
+    pm_info->acpi_id = acpi_id;
+    pm_info->id = cpuid;
+    pm_info->cppc_data = *cppc_data;
+
+    if ( (cppc_data->flags & XEN_CPPC_PSD) &&
+          !check_psd_pminfo(cppc_data->shared_type) )
+    {
+            ret = -EINVAL;
+            goto out;
+    }
+
+    if ( cppc_data->flags & XEN_CPPC_CPC )
+    {
+        if ( cppc_data->cpc.highest_perf == 0 ||
+             cppc_data->cpc.highest_perf > UINT8_MAX ||
+             cppc_data->cpc.nominal_perf == 0 ||
+             cppc_data->cpc.lowest_nonlinear_perf == 0 ||
+             cppc_data->cpc.lowest_perf == 0 ||
+             cppc_data->cpc.lowest_perf >
+                 cppc_data->cpc.lowest_nonlinear_perf ||
+             cppc_data->cpc.lowest_nonlinear_perf >
+                 cppc_data->cpc.nominal_perf ||
+             cppc_data->cpc.nominal_perf > cppc_data->cpc.highest_perf )
+            /*
+             * Right now, Xen doesn't actually use highest_perf/nominal_perf/
+             * lowest_nonlinear_perf/lowest_perf values read from ACPI _CPC
+             * table. Xen reads CPPC capability MSR to get these four values.
+             * So warning is enough.
+             */
+            printk_once(XENLOG_WARNING
+                        "Broken CPPC perf values: lowest(%u), nonlinear_lowest(%u), nominal(%u), highest(%u)\n",
+                        cppc_data->cpc.lowest_perf,
+                        cppc_data->cpc.lowest_nonlinear_perf,
+                        cppc_data->cpc.nominal_perf,
+                        cppc_data->cpc.highest_perf);
+
+        /* lowest_mhz and nominal_mhz are optional value */
+        if ( cppc_data->cpc.nominal_mhz &&
+             cppc_data->cpc.lowest_mhz > cppc_data->cpc.nominal_mhz )
+        {
+            printk_once(XENLOG_WARNING
+                        "Broken CPPC freq values: lowest(%u), nominal(%u)\n",
+                        cppc_data->cpc.lowest_mhz,
+                        cppc_data->cpc.nominal_mhz);
+            /* Re-set with zero values, instead of keeping invalid values */
+            pm_info->cppc_data.cpc.nominal_mhz = 0;
+            pm_info->cppc_data.cpc.lowest_mhz = 0;
+        }
+    }
+
+    if ( cppc_data->flags == (XEN_CPPC_PSD | XEN_CPPC_CPC) )
+    {
+        if ( cpufreq_verbose )
+        {
+            print_PSD(&pm_info->cppc_data.domain_info);
+            print_CPPC(&pm_info->cppc_data);
+        }
+
+        pm_info->init = XEN_CPPC_INIT;
+        ret = cpufreq_cpu_init(cpuid);
+        if ( ret )
+            printk_once(XENLOG_WARNING
+                        "CPU%d failed amd-cppc mode init; use \"cpufreq=xen\" instead",
+                        cpuid);
+    }
+
+ out:
+    return ret;
+}
+
 static void cpufreq_cmdline_common_para(struct cpufreq_policy *new_policy)
 {
     if (usr_max_freq)
diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/cpufreq/processor_perf.h
index 4e045da983..e6576314f0 100644
--- a/xen/include/acpi/cpufreq/processor_perf.h
+++ b/xen/include/acpi/cpufreq/processor_perf.h
@@ -5,7 +5,8 @@
 #include 
 #include 
 
-#define XEN_PX_INIT 0x80000000U
+#define XEN_CPPC_INIT 0x40000000U
+#define XEN_PX_INIT   0x80000000U
 
 unsigned int powernow_register_driver(void);
 unsigned int get_measured_perf(unsigned int cpu, unsigned int flag);
@@ -43,6 +44,7 @@ struct processor_pminfo {
     uint32_t acpi_id;
     uint32_t id;
     struct processor_performance    perf;
+    struct xen_processor_cppc cppc_data;
 
     uint32_t init;
 };
diff --git a/xen/include/public/platform.h b/xen/include/public/platform.h
index 2725b8d104..94349fc5f5 100644
--- a/xen/include/public/platform.h
+++ b/xen/include/public/platform.h
@@ -363,6 +363,7 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t);
 #define XEN_PM_PX   1
 #define XEN_PM_TX   2
 #define XEN_PM_PDC  3
+#define XEN_PM_CPPC 4
 
 /* Px sub info type */
 #define XEN_PX_PCT   1
@@ -370,6 +371,10 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t);
 #define XEN_PX_PPC   4
 #define XEN_PX_PSD   8
 
+/* CPPC sub info type */
+#define XEN_CPPC_PSD   (1U << 0)
+#define XEN_CPPC_CPC   (1U << 1)
+
 struct xen_power_register {
     uint32_t     space_id;
     uint32_t     bit_width;
@@ -457,6 +462,26 @@ struct xen_processor_performance {
 typedef struct xen_processor_performance xen_processor_performance_t;
 DEFINE_XEN_GUEST_HANDLE(xen_processor_performance_t);
 
+struct xen_processor_cppc {
+    uint8_t flags; /* IN: XEN_CPPC_xxx */
+    uint8_t pad[3];
+    /*
+     * IN: Subset _CPC fields useful for CPPC-compatible cpufreq
+     * driver's initialization
+     */
+    struct {
+        uint32_t highest_perf;
+        uint32_t nominal_perf;
+        uint32_t lowest_nonlinear_perf;
+        uint32_t lowest_perf;
+        uint32_t lowest_mhz;
+        uint32_t nominal_mhz;
+    } cpc;
+    uint32_t shared_type; /* IN: XEN_CPUPERF_SHARED_TYPE_xxx */
+    struct xen_psd_package domain_info; /* IN: _PSD */
+};
+typedef struct xen_processor_cppc xen_processor_cppc_t;
+
 struct xenpf_set_processor_pminfo {
     /* IN variables */
     uint32_t id;    /* ACPI CPU ID */
@@ -465,6 +490,7 @@ struct xenpf_set_processor_pminfo {
         struct xen_processor_power          power;/* Cx: _CST/_CSD */
         struct xen_processor_performance    perf; /* Px: _PPC/_PCT/_PSS/_PSD */
         XEN_GUEST_HANDLE(uint32)            pdc;  /* _PDC */
+        xen_processor_cppc_t                cppc_data; /* CPPC: _CPC and _PSD */
     } u;
 };
 typedef struct xenpf_set_processor_pminfo xenpf_set_processor_pminfo_t;
diff --git a/xen/include/xen/pmstat.h b/xen/include/xen/pmstat.h
index 8350403e95..6096560d3c 100644
--- a/xen/include/xen/pmstat.h
+++ b/xen/include/xen/pmstat.h
@@ -7,12 +7,17 @@
 
 int set_px_pminfo(uint32_t acpi_id, struct xen_processor_performance *perf);
 long set_cx_pminfo(uint32_t acpi_id, struct xen_processor_power *power);
+int set_cppc_pminfo(unsigned int acpi_id,
+                    const struct xen_processor_cppc *cppc_data);
 
 #ifdef CONFIG_COMPAT
 struct compat_processor_performance;
 int compat_set_px_pminfo(uint32_t acpi_id, struct compat_processor_performance *perf);
 struct compat_processor_power;
 long compat_set_cx_pminfo(uint32_t acpi_id, struct compat_processor_power *power);
+struct compat_processor_cppc;
+int compat_set_cppc_pminfo(unsigned int acpi_id,
+                           const struct compat_processor_cppc *cppc_data);
 #endif
 
 uint32_t pmstat_get_cx_nr(unsigned int cpu);
diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst
index 6d6c6cfab2..9d08dcc4bb 100644
--- a/xen/include/xlat.lst
+++ b/xen/include/xlat.lst
@@ -160,6 +160,7 @@
 
 !	pct_register			platform.h
 !	power_register			platform.h
+!	processor_cppc			platform.h
 ?	processor_csd			platform.h
 !	processor_cx			platform.h
 !	processor_flags			platform.h
-- 
2.34.1



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Subject: [PATCH v8 0/8] amd-cppc CPU Performance Scaling Driver
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amd-cppc is the AMD CPU performance scaling driver that introduces a
new CPU frequency control mechanism on modern AMD APU and CPU series in
Xen. The new mechanism is based on Collaborative Processor Performance
Control (CPPC) which provides finer grain frequency management than
legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using
the ACPI P-states driver to manage CPU frequency and clocks with
switching only in 3 P-states. CPPC replaces the ACPI P-states controls
and allows a flexible, low-latency interface for Xen to directly
communicate the performance hints to hardware.

amd_cppc driver has 2 operation modes: autonomous (active) mode,
and non-autonomous (passive) mode. We register different CPUFreq driver
for different modes, "amd-cppc" for passive mode and "amd-cppc-epp"
for active mode.

The passive mode leverages common governors such as *ondemand*,
*performance*, etc, to manage the performance tuning. While the active mode
uses epp to provides a hint to the hardware if software wants to bias
toward performance (0x0) or energy efficiency (0xff). CPPC power algorithm
in hardware will automatically calculate the runtime workload and adjust the
realtime cpu cores frequency according to the power supply and thermal, core
voltage and some other hardware conditions.

amd-cppc is enabled on passive mode with a top-level `cpufreq=amd-cppc` option,
while users add extra `active` flag to select active mode.

With `cpufreq=amd-cppc,active`, we did a 60s sampling test to see the CPU
frequency change, through tweaking the energy_perf preference from
`xenpm set-cpufreq-cppc powersave` to `xenpm set-cpufreq-cppc performance`.
The outputs are as follows:
```
Setting CPU in powersave mode
Sampling and Outputs:
  Avg freq      580000 KHz
  Avg freq      580000 KHz
  Avg freq      580000 KHz
Setting CPU in performance mode
Sampling and Outputs:
  Avg freq      4640000 KHz
  Avg freq      4220000 KHz
  Avg freq      4640000 KHz
```

Penny Zheng (8):
  xen/cpufreq: introduce new sub-hypercall to propagate CPPC data
  xen/cpufreq: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc
    driver
  xen/cpufreq: implement amd-cppc driver for CPPC in passive mode
  xen/cpufreq: implement amd-cppc-epp driver for CPPC in active mode
  xen/cpufreq: get performance policy from governor set via xenpm
  tools/cpufreq: extract CPPC para from cpufreq para
  xen/cpufreq: bypass governor-related para for amd-cppc-epp
  xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC xen_sysctl_pm_op for amd-cppc
    driver

 docs/misc/xen-command-line.pandoc         |  14 +-
 tools/include/xenctrl.h                   |   3 +-
 tools/libs/ctrl/xc_pm.c                   |  25 +-
 tools/misc/xenpm.c                        |  94 ++-
 xen/arch/x86/acpi/cpufreq/Makefile        |   1 +
 xen/arch/x86/acpi/cpufreq/amd-cppc.c      | 766 ++++++++++++++++++++++
 xen/arch/x86/acpi/cpufreq/cpufreq.c       |  69 +-
 xen/arch/x86/cpu/amd.c                    |   8 +-
 xen/arch/x86/include/asm/amd.h            |   2 +
 xen/arch/x86/include/asm/msr-index.h      |   6 +
 xen/arch/x86/platform_hypercall.c         |  19 +
 xen/arch/x86/x86_64/cpufreq.c             |  19 +
 xen/arch/x86/x86_64/platform_hypercall.c  |   3 +
 xen/drivers/acpi/pm-op.c                  |  68 +-
 xen/drivers/acpi/pmstat.c                 |   4 +
 xen/drivers/cpufreq/cpufreq.c             | 137 +++-
 xen/drivers/cpufreq/utility.c             |  15 +
 xen/include/acpi/cpufreq/cpufreq.h        |  40 +-
 xen/include/acpi/cpufreq/processor_perf.h |  14 +-
 xen/include/public/platform.h             |  26 +
 xen/include/public/sysctl.h               |   5 +-
 xen/include/xen/pmstat.h                  |   5 +
 xen/include/xlat.lst                      |   1 +
 23 files changed, 1283 insertions(+), 61 deletions(-)
 create mode 100644 xen/arch/x86/acpi/cpufreq/amd-cppc.c

-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	, Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD
	, Michal Orzel , "Julien
 Grall" , Stefano Stabellini , Juergen
 Gross 
Subject: [PATCH v8 0/8] amd-cppc CPU Performance Scaling Driver
Date: Thu, 28 Aug 2025 18:02:58 +0800
Message-ID: <20250828100306.1776031-1-Penny.Zheng@amd.com>
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amd-cppc is the AMD CPU performance scaling driver that introduces a
new CPU frequency control mechanism on modern AMD APU and CPU series in
Xen. The new mechanism is based on Collaborative Processor Performance
Control (CPPC) which provides finer grain frequency management than
legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using
the ACPI P-states driver to manage CPU frequency and clocks with
switching only in 3 P-states. CPPC replaces the ACPI P-states controls
and allows a flexible, low-latency interface for Xen to directly
communicate the performance hints to hardware.

amd_cppc driver has 2 operation modes: autonomous (active) mode,
and non-autonomous (passive) mode. We register different CPUFreq driver
for different modes, "amd-cppc" for passive mode and "amd-cppc-epp"
for active mode.

The passive mode leverages common governors such as *ondemand*,
*performance*, etc, to manage the performance tuning. While the active mode
uses epp to provides a hint to the hardware if software wants to bias
toward performance (0x0) or energy efficiency (0xff). CPPC power algorithm
in hardware will automatically calculate the runtime workload and adjust the
realtime cpu cores frequency according to the power supply and thermal, core
voltage and some other hardware conditions.

amd-cppc is enabled on passive mode with a top-level `cpufreq=amd-cppc` option,
while users add extra `active` flag to select active mode.

With `cpufreq=amd-cppc,active`, we did a 60s sampling test to see the CPU
frequency change, through tweaking the energy_perf preference from
`xenpm set-cpufreq-cppc powersave` to `xenpm set-cpufreq-cppc performance`.
The outputs are as follows:
```
Setting CPU in powersave mode
Sampling and Outputs:
  Avg freq      580000 KHz
  Avg freq      580000 KHz
  Avg freq      580000 KHz
Setting CPU in performance mode
Sampling and Outputs:
  Avg freq      4640000 KHz
  Avg freq      4220000 KHz
  Avg freq      4640000 KHz
```

Penny Zheng (8):
  xen/cpufreq: introduce new sub-hypercall to propagate CPPC data
  xen/cpufreq: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc
    driver
  xen/cpufreq: implement amd-cppc driver for CPPC in passive mode
  xen/cpufreq: implement amd-cppc-epp driver for CPPC in active mode
  xen/cpufreq: get performance policy from governor set via xenpm
  tools/cpufreq: extract CPPC para from cpufreq para
  xen/cpufreq: bypass governor-related para for amd-cppc-epp
  xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC xen_sysctl_pm_op for amd-cppc
    driver

 docs/misc/xen-command-line.pandoc         |  14 +-
 tools/include/xenctrl.h                   |   3 +-
 tools/libs/ctrl/xc_pm.c                   |  25 +-
 tools/misc/xenpm.c                        |  94 ++-
 xen/arch/x86/acpi/cpufreq/Makefile        |   1 +
 xen/arch/x86/acpi/cpufreq/amd-cppc.c      | 766 ++++++++++++++++++++++
 xen/arch/x86/acpi/cpufreq/cpufreq.c       |  69 +-
 xen/arch/x86/cpu/amd.c                    |   8 +-
 xen/arch/x86/include/asm/amd.h            |   2 +
 xen/arch/x86/include/asm/msr-index.h      |   6 +
 xen/arch/x86/platform_hypercall.c         |  19 +
 xen/arch/x86/x86_64/cpufreq.c             |  19 +
 xen/arch/x86/x86_64/platform_hypercall.c  |   3 +
 xen/drivers/acpi/pm-op.c                  |  68 +-
 xen/drivers/acpi/pmstat.c                 |   4 +
 xen/drivers/cpufreq/cpufreq.c             | 137 +++-
 xen/drivers/cpufreq/utility.c             |  15 +
 xen/include/acpi/cpufreq/cpufreq.h        |  40 +-
 xen/include/acpi/cpufreq/processor_perf.h |  14 +-
 xen/include/public/platform.h             |  26 +
 xen/include/public/sysctl.h               |   5 +-
 xen/include/xen/pmstat.h                  |   5 +
 xen/include/xlat.lst                      |   1 +
 23 files changed, 1283 insertions(+), 61 deletions(-)
 create mode 100644 xen/arch/x86/acpi/cpufreq/amd-cppc.c

-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	, Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD
	, Michal Orzel , "Julien
 Grall" , Stefano Stabellini 
Subject: [PATCH v8 1/8] xen/cpufreq: introduce new sub-hypercall to propagate CPPC data
Date: Thu, 28 Aug 2025 18:02:59 +0800
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In order to provide backward compatibility with existing governors
that represent performance as frequency, like ondemand, the _CPC
table can optionally provide processor frequency range values, Lowest
frequency and Nominal frequency, to let OS use Lowest Frequency/
Performance and Nominal Frequency/Performance as anchor points to
create linear mapping of CPPC performance to CPU frequency.

As Xen is uncapable of parsing the ACPI dynamic table, we'd like to
introduce a new sub-hypercall "XEN_PM_CPPC" to propagate required CPPC
data from dom0 kernel to Xen.
In the according handler set_cppc_pminfo(), we do _CPC and _PSD
sanitization check, as both _PSD and _CPC info are necessary for correctly
initializing cpufreq cores in CPPC mode.
Users shall be warned that if we failed at this point,
no fallback scheme, like legacy P-state could be switched to.

A new flag "XEN_CPPC_INIT" is also introduced for cpufreq core initialised in
CPPC mode. Then all .init flag checking shall be updated to
consider "XEN_CPPC_INIT" too.

We want to bypass construction of px statistic info in cpufreq_statistic_init()
for CPPC mode, while not bypassing cpufreq_statistic_lock initialization for a
good reason. The same check is unnecessary for cpufreq_statistic_exit(),
since it has already been covered by px statistic variable
"cpufreq_statistic_data" check

Signed-off-by: Penny Zheng 
---
v1 -> v2:
- Give the variable des_perf an initializer of 0
- Use the strncmp()s directly in the if()
---
v3 -> v4
- refactor comments
- remove double blank lines
- replace amd_cppc_in_use flag with XEN_PROCESSOR_PM_CPPC
---
v4 -> v5:
- add new field "policy" in "struct xen_cppc_para"
- add new performamce policy XEN_CPUFREQ_POLICY_BALANCE
- drop string comparisons with "processor_pminfo[cpuid]->init & XEN_CPPC_INIT"
and "cpufreq.setpolicy == NULL"
- Blank line ahead of the main "return" of a function
- refactor comments, commit message and title
---
v5 -> v6:
- remove duplicated manifest constants, and just move it to public header
- use "else if" to avoid confusion that it looks as if both paths could be taken
- add check for legitimate perf values
- use "unknown" instead of "none"
- introduce "CPUFREQ_POLICY_END" for array overrun check in user space tools
---
v6 -> v7:
- use ARRAY_SIZE() instead
- ->policy print is avoided in passive mode and print "unknown" in invalid
cases
- let cpufreq_is_governorless() being the variable's initializer
- refactor with the conditional operator to increase readability
- move duplicated defination ahead and use local variable
- avoid using "else-condition" to bring "dead code" in Misra's nomeclature
- move the comment out of public header and into the respective internal
struct field
- wrap set{,get}_amd_cppc_para() with CONFIG_PM_OP
- add symmetry scenario for maximum check
---
v7 -> v8:
- replace -EFAULT with -ENOMEM
- indent fix
- add comment for state_count check for CPPC mode
---
 xen/arch/x86/platform_hypercall.c         |   5 +
 xen/arch/x86/x86_64/cpufreq.c             |  19 ++++
 xen/arch/x86/x86_64/platform_hypercall.c  |   3 +
 xen/drivers/acpi/pm-op.c                  |   7 +-
 xen/drivers/acpi/pmstat.c                 |   4 +
 xen/drivers/cpufreq/cpufreq.c             | 124 +++++++++++++++++++++-
 xen/include/acpi/cpufreq/processor_perf.h |   4 +-
 xen/include/public/platform.h             |  26 +++++
 xen/include/xen/pmstat.h                  |   5 +
 xen/include/xlat.lst                      |   1 +
 10 files changed, 193 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c
index 21f9f795c1..fafc176475 100644
--- a/xen/arch/x86/platform_hypercall.c
+++ b/xen/arch/x86/platform_hypercall.c
@@ -577,6 +577,11 @@ ret_t do_platform_op(
             break;
         }
 
+        case XEN_PM_CPPC:
+            ret = set_cppc_pminfo(op->u.set_pminfo.id,
+                                  &op->u.set_pminfo.u.cppc_data);
+            break;
+
         default:
             ret = -EINVAL;
             break;
diff --git a/xen/arch/x86/x86_64/cpufreq.c b/xen/arch/x86/x86_64/cpufreq.c
index e4f3d5b436..525b29da71 100644
--- a/xen/arch/x86/x86_64/cpufreq.c
+++ b/xen/arch/x86/x86_64/cpufreq.c
@@ -54,3 +54,22 @@ int compat_set_px_pminfo(uint32_t acpi_id,
 
     return set_px_pminfo(acpi_id, xen_perf);
 }
+
+int compat_set_cppc_pminfo(unsigned int acpi_id,
+                           const struct compat_processor_cppc *cppc_data)
+
+{
+    struct xen_processor_cppc *xen_cppc;
+    unsigned long xlat_page_current;
+
+    xlat_malloc_init(xlat_page_current);
+
+    xen_cppc = xlat_malloc_array(xlat_page_current,
+                                 struct xen_processor_cppc, 1);
+    if ( unlikely(xen_cppc == NULL) )
+        return -ENOMEM;
+
+    XLAT_processor_cppc(xen_cppc, cppc_data);
+
+    return set_cppc_pminfo(acpi_id, xen_cppc);
+}
diff --git a/xen/arch/x86/x86_64/platform_hypercall.c b/xen/arch/x86/x86_64/platform_hypercall.c
index 9ab631c17f..0288f68df9 100644
--- a/xen/arch/x86/x86_64/platform_hypercall.c
+++ b/xen/arch/x86/x86_64/platform_hypercall.c
@@ -14,6 +14,9 @@ EMIT_FILE;
 #define efi_get_info        efi_compat_get_info
 #define efi_runtime_call(x) efi_compat_runtime_call(x)
 
+#define xen_processor_cppc  compat_processor_cppc
+#define set_cppc_pminfo     compat_set_cppc_pminfo
+
 #define xen_processor_performance compat_processor_performance
 #define set_px_pminfo       compat_set_px_pminfo
 
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index 9a1970df34..e3b5c8bcaa 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -91,7 +91,10 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
     pmpt = processor_pminfo[op->cpuid];
     policy = per_cpu(cpufreq_cpu_policy, op->cpuid);
 
-    if ( !pmpt || !pmpt->perf.states ||
+    if ( !pmpt ||
+         ((pmpt->init & XEN_PX_INIT) && !pmpt->perf.states) ||
+         /* Avoid NULL deref of pmpt->perf.states[] */
+         ((pmpt->init & XEN_CPPC_INIT) && pmpt->perf.state_count) ||
          !policy || !policy->governor )
         return -EINVAL;
 
@@ -351,7 +354,7 @@ int do_pm_op(struct xen_sysctl_pm_op *op)
     case CPUFREQ_PARA:
         if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_PX) )
             return -ENODEV;
-        if ( !pmpt || !(pmpt->init & XEN_PX_INIT) )
+        if ( !pmpt || !(pmpt->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
             return -EINVAL;
         break;
     }
diff --git a/xen/drivers/acpi/pmstat.c b/xen/drivers/acpi/pmstat.c
index 4fae0c14af..0f31736df2 100644
--- a/xen/drivers/acpi/pmstat.c
+++ b/xen/drivers/acpi/pmstat.c
@@ -108,6 +108,10 @@ int cpufreq_statistic_init(unsigned int cpu)
     if ( !pmpt )
         return -EINVAL;
 
+    /* Only need to initialize in Px mode */
+    if ( !(pmpt->init & XEN_PX_INIT) )
+        return 0;
+
     spin_lock(cpufreq_statistic_lock);
 
     pxpt = per_cpu(cpufreq_statistic_data, cpu);
diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c
index 267e4d3f3b..c6ce31c0ac 100644
--- a/xen/drivers/cpufreq/cpufreq.c
+++ b/xen/drivers/cpufreq/cpufreq.c
@@ -40,6 +40,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -234,6 +235,11 @@ static int get_psd_info(unsigned int cpu, unsigned int *shared_type,
         *domain_info = &processor_pminfo[cpu]->perf.domain_info;
         break;
 
+    case XEN_CPPC_INIT:
+        *shared_type = processor_pminfo[cpu]->cppc_data.shared_type;
+        *domain_info = &processor_pminfo[cpu]->cppc_data.domain_info;
+        break;
+
     default:
         ret = -EINVAL;
         break;
@@ -259,7 +265,7 @@ int cpufreq_add_cpu(unsigned int cpu)
     if ( !processor_pminfo[cpu] || !cpu_online(cpu) )
         return -EINVAL;
 
-    if ( !(processor_pminfo[cpu]->init & XEN_PX_INIT) )
+    if ( !(processor_pminfo[cpu]->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
         return -EINVAL;
 
     if (!cpufreq_driver.init)
@@ -434,7 +440,7 @@ int cpufreq_del_cpu(unsigned int cpu)
     if ( !processor_pminfo[cpu] || !cpu_online(cpu) )
         return -EINVAL;
 
-    if ( !(processor_pminfo[cpu]->init & XEN_PX_INIT) )
+    if ( !(processor_pminfo[cpu]->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
         return -EINVAL;
 
     if (!per_cpu(cpufreq_cpu_policy, cpu))
@@ -693,6 +699,120 @@ int acpi_set_pdc_bits(unsigned int acpi_id, XEN_GUEST_HANDLE(uint32) pdc)
     return ret;
 }
 
+static void print_CPPC(const struct xen_processor_cppc *cppc_data)
+{
+    printk("\t_CPC: highest_perf=%u, lowest_perf=%u, "
+           "nominal_perf=%u, lowest_nonlinear_perf=%u, "
+           "nominal_mhz=%uMHz, lowest_mhz=%uMHz\n",
+           cppc_data->cpc.highest_perf, cppc_data->cpc.lowest_perf,
+           cppc_data->cpc.nominal_perf, cppc_data->cpc.lowest_nonlinear_perf,
+           cppc_data->cpc.nominal_mhz, cppc_data->cpc.lowest_mhz);
+}
+
+int set_cppc_pminfo(unsigned int acpi_id,
+                    const struct xen_processor_cppc *cppc_data)
+{
+    int ret = 0, cpuid;
+    struct processor_pminfo *pm_info;
+
+    cpuid = get_cpu_id(acpi_id);
+    if ( cpuid < 0 )
+    {
+        ret = -EINVAL;
+        goto out;
+    }
+
+    if ( cppc_data->pad[0] || cppc_data->pad[1] || cppc_data->pad[2] )
+    {
+        ret = -EINVAL;
+        goto out;
+    }
+
+    if ( cpufreq_verbose )
+        printk("Set CPU%d (ACPI ID %u) CPPC state info:\n",
+               cpuid, acpi_id);
+
+    pm_info = processor_pminfo[cpuid];
+    if ( !pm_info )
+    {
+        pm_info = xvzalloc(struct processor_pminfo);
+        if ( !pm_info )
+        {
+            ret = -ENOMEM;
+            goto out;
+        }
+        processor_pminfo[cpuid] = pm_info;
+    }
+    pm_info->acpi_id = acpi_id;
+    pm_info->id = cpuid;
+    pm_info->cppc_data = *cppc_data;
+
+    if ( (cppc_data->flags & XEN_CPPC_PSD) &&
+          !check_psd_pminfo(cppc_data->shared_type) )
+    {
+            ret = -EINVAL;
+            goto out;
+    }
+
+    if ( cppc_data->flags & XEN_CPPC_CPC )
+    {
+        if ( cppc_data->cpc.highest_perf == 0 ||
+             cppc_data->cpc.highest_perf > UINT8_MAX ||
+             cppc_data->cpc.nominal_perf == 0 ||
+             cppc_data->cpc.lowest_nonlinear_perf == 0 ||
+             cppc_data->cpc.lowest_perf == 0 ||
+             cppc_data->cpc.lowest_perf >
+                 cppc_data->cpc.lowest_nonlinear_perf ||
+             cppc_data->cpc.lowest_nonlinear_perf >
+                 cppc_data->cpc.nominal_perf ||
+             cppc_data->cpc.nominal_perf > cppc_data->cpc.highest_perf )
+            /*
+             * Right now, Xen doesn't actually use highest_perf/nominal_perf/
+             * lowest_nonlinear_perf/lowest_perf values read from ACPI _CPC
+             * table. Xen reads CPPC capability MSR to get these four values.
+             * So warning is enough.
+             */
+            printk_once(XENLOG_WARNING
+                        "Broken CPPC perf values: lowest(%u), nonlinear_lowest(%u), nominal(%u), highest(%u)\n",
+                        cppc_data->cpc.lowest_perf,
+                        cppc_data->cpc.lowest_nonlinear_perf,
+                        cppc_data->cpc.nominal_perf,
+                        cppc_data->cpc.highest_perf);
+
+        /* lowest_mhz and nominal_mhz are optional value */
+        if ( cppc_data->cpc.nominal_mhz &&
+             cppc_data->cpc.lowest_mhz > cppc_data->cpc.nominal_mhz )
+        {
+            printk_once(XENLOG_WARNING
+                        "Broken CPPC freq values: lowest(%u), nominal(%u)\n",
+                        cppc_data->cpc.lowest_mhz,
+                        cppc_data->cpc.nominal_mhz);
+            /* Re-set with zero values, instead of keeping invalid values */
+            pm_info->cppc_data.cpc.nominal_mhz = 0;
+            pm_info->cppc_data.cpc.lowest_mhz = 0;
+        }
+    }
+
+    if ( cppc_data->flags == (XEN_CPPC_PSD | XEN_CPPC_CPC) )
+    {
+        if ( cpufreq_verbose )
+        {
+            print_PSD(&pm_info->cppc_data.domain_info);
+            print_CPPC(&pm_info->cppc_data);
+        }
+
+        pm_info->init = XEN_CPPC_INIT;
+        ret = cpufreq_cpu_init(cpuid);
+        if ( ret )
+            printk_once(XENLOG_WARNING
+                        "CPU%d failed amd-cppc mode init; use \"cpufreq=xen\" instead",
+                        cpuid);
+    }
+
+ out:
+    return ret;
+}
+
 static void cpufreq_cmdline_common_para(struct cpufreq_policy *new_policy)
 {
     if (usr_max_freq)
diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/cpufreq/processor_perf.h
index 4e045da983..e6576314f0 100644
--- a/xen/include/acpi/cpufreq/processor_perf.h
+++ b/xen/include/acpi/cpufreq/processor_perf.h
@@ -5,7 +5,8 @@
 #include 
 #include 
 
-#define XEN_PX_INIT 0x80000000U
+#define XEN_CPPC_INIT 0x40000000U
+#define XEN_PX_INIT   0x80000000U
 
 unsigned int powernow_register_driver(void);
 unsigned int get_measured_perf(unsigned int cpu, unsigned int flag);
@@ -43,6 +44,7 @@ struct processor_pminfo {
     uint32_t acpi_id;
     uint32_t id;
     struct processor_performance    perf;
+    struct xen_processor_cppc cppc_data;
 
     uint32_t init;
 };
diff --git a/xen/include/public/platform.h b/xen/include/public/platform.h
index 2725b8d104..94349fc5f5 100644
--- a/xen/include/public/platform.h
+++ b/xen/include/public/platform.h
@@ -363,6 +363,7 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t);
 #define XEN_PM_PX   1
 #define XEN_PM_TX   2
 #define XEN_PM_PDC  3
+#define XEN_PM_CPPC 4
 
 /* Px sub info type */
 #define XEN_PX_PCT   1
@@ -370,6 +371,10 @@ DEFINE_XEN_GUEST_HANDLE(xenpf_getidletime_t);
 #define XEN_PX_PPC   4
 #define XEN_PX_PSD   8
 
+/* CPPC sub info type */
+#define XEN_CPPC_PSD   (1U << 0)
+#define XEN_CPPC_CPC   (1U << 1)
+
 struct xen_power_register {
     uint32_t     space_id;
     uint32_t     bit_width;
@@ -457,6 +462,26 @@ struct xen_processor_performance {
 typedef struct xen_processor_performance xen_processor_performance_t;
 DEFINE_XEN_GUEST_HANDLE(xen_processor_performance_t);
 
+struct xen_processor_cppc {
+    uint8_t flags; /* IN: XEN_CPPC_xxx */
+    uint8_t pad[3];
+    /*
+     * IN: Subset _CPC fields useful for CPPC-compatible cpufreq
+     * driver's initialization
+     */
+    struct {
+        uint32_t highest_perf;
+        uint32_t nominal_perf;
+        uint32_t lowest_nonlinear_perf;
+        uint32_t lowest_perf;
+        uint32_t lowest_mhz;
+        uint32_t nominal_mhz;
+    } cpc;
+    uint32_t shared_type; /* IN: XEN_CPUPERF_SHARED_TYPE_xxx */
+    struct xen_psd_package domain_info; /* IN: _PSD */
+};
+typedef struct xen_processor_cppc xen_processor_cppc_t;
+
 struct xenpf_set_processor_pminfo {
     /* IN variables */
     uint32_t id;    /* ACPI CPU ID */
@@ -465,6 +490,7 @@ struct xenpf_set_processor_pminfo {
         struct xen_processor_power          power;/* Cx: _CST/_CSD */
         struct xen_processor_performance    perf; /* Px: _PPC/_PCT/_PSS/_PSD */
         XEN_GUEST_HANDLE(uint32)            pdc;  /* _PDC */
+        xen_processor_cppc_t                cppc_data; /* CPPC: _CPC and _PSD */
     } u;
 };
 typedef struct xenpf_set_processor_pminfo xenpf_set_processor_pminfo_t;
diff --git a/xen/include/xen/pmstat.h b/xen/include/xen/pmstat.h
index 8350403e95..6096560d3c 100644
--- a/xen/include/xen/pmstat.h
+++ b/xen/include/xen/pmstat.h
@@ -7,12 +7,17 @@
 
 int set_px_pminfo(uint32_t acpi_id, struct xen_processor_performance *perf);
 long set_cx_pminfo(uint32_t acpi_id, struct xen_processor_power *power);
+int set_cppc_pminfo(unsigned int acpi_id,
+                    const struct xen_processor_cppc *cppc_data);
 
 #ifdef CONFIG_COMPAT
 struct compat_processor_performance;
 int compat_set_px_pminfo(uint32_t acpi_id, struct compat_processor_performance *perf);
 struct compat_processor_power;
 long compat_set_cx_pminfo(uint32_t acpi_id, struct compat_processor_power *power);
+struct compat_processor_cppc;
+int compat_set_cppc_pminfo(unsigned int acpi_id,
+                           const struct compat_processor_cppc *cppc_data);
 #endif
 
 uint32_t pmstat_get_cx_nr(unsigned int cpu);
diff --git a/xen/include/xlat.lst b/xen/include/xlat.lst
index 6d6c6cfab2..9d08dcc4bb 100644
--- a/xen/include/xlat.lst
+++ b/xen/include/xlat.lst
@@ -160,6 +160,7 @@
 
 !	pct_register			platform.h
 !	power_register			platform.h
+!	processor_cppc			platform.h
 ?	processor_csd			platform.h
 !	processor_cx			platform.h
 !	processor_flags			platform.h
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , "Julien
 Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?=
	, Stefano Stabellini 
Subject: [PATCH v8 2/8] xen/cpufreq: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc driver
Date: Thu, 28 Aug 2025 18:03:00 +0800
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Users need to set "cpufreq=amd-cppc" in xen cmdline to enable amd-cppc driver,
which selects ACPI Collaborative Performance and Power Control (CPPC) on
supported AMD hardware to provide a finer grained frequency control mechanism.
`verbose` option can also be included to support verbose print.

When users setting "cpufreq=amd-cppc", a new amd-cppc driver
shall be registered and used. All hooks for amd-cppc driver are transiently
missing, and we temporarily make registration fail with -EOPNOTSUPP here. It
will be fixed along with the implementation.

New xen-pm internal flag XEN_PROCESSOR_PM_CPPC is introduced, to stand for
cpufreq driver in CPPC mode. We define XEN_PROCESSOR_PM_CPPC 0x100, as it is
the next value to use after 8-bits wide public xen-pm options. We also add
sanity check on compile time. All XEN_PROCESSOR_PM_xxx checking shall be
updated to consider "XEN_PROCESSOR_PM_CPPC" too.

XEN_PROCESSOR_PM_CPPC and XEN_PROCESSOR_PM_PX are firstly set when Xen parsed
relative driver signature from xen cmdline, and will become exclusive after
cpufreq driver registration. It is because that platform could not support
both or mixed mode (CPPC & legacy Px) operations, and only one cpufreq driver
could be registerd in Xen at one time, such as on AMD, it is either amd-cppc
or legacy P-states driver.
Xen rely on XEN_PROCESSOR_PM_CPPC flag to tell current cpufreq driver is in
CPPC mode, and accepts relative hypercall. It will neglect Px request and
yields success.

Signed-off-by: Penny Zheng 
Acked-by: Jan Beulich 
---
---
v1 -> v2:
- Obey to alphabetic sorting and also strict it with CONFIG_AMD
- Remove unnecessary empty comment line
- Use __initconst_cf_clobber for pre-filled structure cpufreq_driver
- Make new switch-case code apply to Hygon CPUs too
- Change ENOSYS with EOPNOTSUPP
- Blanks around binary operator
- Change all amd_/-pstate defined values to amd_/-cppc
---
v2 -> v3
- refactor too long lines
- Make sure XEN_PROCESSOR_PM_PX and XEN_PROCESSOR_PM_CPPC incompatible flags
after cpufreq register registrantion
---
v3 -> v4:
- introduce XEN_PROCESSOR_PM_CPPC in xen internal header
- complement "Hygon" in log message
- remove unnecessary if()
- grow cpufreq_xen_opts[] array
---
v4 -> v5:
- remove XEN_PROCESSOR_PM_xxx flag sanitization from individual driver
- prefer ! over "== 0" in purely boolean contexts
- Blank line between non-fall-through case blocks
- add build-time checking between internal and public XEN_PROCESSOR_PM_*
values
- define XEN_PROCESSOR_PM_CPPC with 0x100, as it is the next value to use
after public interface, and public mask SIF_PM_MASK is 8 bits wide.
- as Dom0 will send the CPPC/Px data whenever it could, the return value shall
be 0 instead of -ENOSYS/EOPNOTSUP when platform doesn't require these data.
---
v5 -> v6:
- do not register the driver when all hooks are NULL
- refactor the subject and commit message
- move pruning of xen_processor_pmbits into generic space
- add comment and build-time check for XEN_PROCESSOR_PM_CPPC
---
v6 -> v7:
- reomove pointless initializer for "unsigned int i"
- move closing brace into its own line
- insertion always at the bottom
- change to use #ifdef CONFIG_AMD code wrapping
---
v7 -> v8:
- Blank line between declaration(s) and statement(s)
---
 docs/misc/xen-command-line.pandoc         |  7 ++-
 xen/arch/x86/acpi/cpufreq/Makefile        |  1 +
 xen/arch/x86/acpi/cpufreq/amd-cppc.c      | 59 +++++++++++++++++++
 xen/arch/x86/acpi/cpufreq/cpufreq.c       | 69 ++++++++++++++++++++++-
 xen/arch/x86/platform_hypercall.c         | 14 +++++
 xen/drivers/acpi/pm-op.c                  |  3 +-
 xen/drivers/cpufreq/cpufreq.c             | 13 ++++-
 xen/include/acpi/cpufreq/cpufreq.h        |  6 +-
 xen/include/acpi/cpufreq/processor_perf.h | 10 ++++
 9 files changed, 175 insertions(+), 7 deletions(-)
 create mode 100644 xen/arch/x86/acpi/cpufreq/amd-cppc.c

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index a75b6c9301..3916cc81f6 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -515,7 +515,7 @@ If set, force use of the performance counters for oprofile, rather than detectin
 available support.
 
 ### cpufreq
-> `= none | {{  | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]]`
+> `= none | {{  | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[verbose]]`
 
 > Default: `xen`
 
@@ -526,7 +526,7 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels.
 * `` and `` are integers which represent max and min processor frequencies
   respectively.
 * `verbose` option can be included as a string or also as `verbose=`
-  for `xen`.  It is a boolean for `hwp`.
+  for `xen`.  It is a boolean for `hwp` and `amd-cppc`.
 * `hwp` selects Hardware-Controlled Performance States (HWP) on supported Intel
   hardware.  HWP is a Skylake+ feature which provides better CPU power
   management.  The default is disabled.  If `hwp` is selected, but hardware
@@ -534,6 +534,9 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels.
 * `` is a boolean to enable Hardware Duty Cycling (HDC).  HDC enables the
   processor to autonomously force physical package components into idle state.
   The default is enabled, but the option only applies when `hwp` is enabled.
+* `amd-cppc` selects ACPI Collaborative Performance and Power Control (CPPC)
+  on supported AMD hardware to provide finer grained frequency control
+  mechanism. The default is disabled.
 
 There is also support for `;`-separated fallback options:
 `cpufreq=hwp;xen,verbose`.  This first tries `hwp` and falls back to `xen` if
diff --git a/xen/arch/x86/acpi/cpufreq/Makefile b/xen/arch/x86/acpi/cpufreq/Makefile
index e7dbe434a8..a2ba34bda0 100644
--- a/xen/arch/x86/acpi/cpufreq/Makefile
+++ b/xen/arch/x86/acpi/cpufreq/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_INTEL) += acpi.o
+obj-$(CONFIG_AMD) += amd-cppc.o
 obj-y += cpufreq.o
 obj-$(CONFIG_INTEL) += hwp.o
 obj-$(CONFIG_AMD) += powernow.o
diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
new file mode 100644
index 0000000000..3377783f7e
--- /dev/null
+++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * amd-cppc.c - AMD Processor CPPC Frequency Driver
+ *
+ * Copyright (C) 2025 Advanced Micro Devices, Inc. All Rights Reserved.
+ *
+ * Author: Penny Zheng 
+ *
+ * AMD CPPC cpufreq driver introduces a new CPU performance scaling design
+ * for AMD processors using the ACPI Collaborative Performance and Power
+ * Control (CPPC) feature which provides finer grained frequency control range.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static bool __init amd_cppc_handle_option(const char *s, const char *end)
+{
+    int ret;
+
+    ret = parse_boolean("verbose", s, end);
+    if ( ret >= 0 )
+    {
+        cpufreq_verbose = ret;
+        return true;
+    }
+
+    return false;
+}
+
+int __init amd_cppc_cmdline_parse(const char *s, const char *e)
+{
+    do {
+        const char *end = strpbrk(s, ",;");
+
+        if ( !amd_cppc_handle_option(s, end) )
+        {
+            printk(XENLOG_WARNING
+                   "cpufreq/amd-cppc: option '%.*s' not recognized\n",
+                   (int)((end ?: e) - s), s);
+
+            return -EINVAL;
+        }
+
+        s = end ? end + 1 : NULL;
+    } while ( s && s < e );
+
+    return 0;
+}
+
+int __init amd_cppc_register_driver(void)
+{
+    if ( !cpu_has_cppc )
+        return -ENODEV;
+
+    return -EOPNOTSUPP;
+}
diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufreq/cpufreq.c
index e227376bab..94e8e11c15 100644
--- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
+++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
@@ -131,12 +131,14 @@ static int __init cf_check cpufreq_driver_init(void)
 
     if ( cpufreq_controller == FREQCTL_xen )
     {
+        unsigned int i;
+
         ret = -ENOENT;
 
         switch ( boot_cpu_data.x86_vendor )
         {
         case X86_VENDOR_INTEL:
-            for ( unsigned int i = 0; i < cpufreq_xen_cnt; i++ )
+            for ( i = 0; i < cpufreq_xen_cnt; i++ )
             {
                 switch ( cpufreq_xen_opts[i] )
                 {
@@ -151,6 +153,11 @@ static int __init cf_check cpufreq_driver_init(void)
                 case CPUFREQ_none:
                     ret = 0;
                     break;
+
+                default:
+                    printk(XENLOG_WARNING
+                           "Unsupported cpufreq driver for vendor Intel\n");
+                    break;
                 }
 
                 if ( !ret || ret == -EBUSY )
@@ -160,13 +167,71 @@ static int __init cf_check cpufreq_driver_init(void)
 
         case X86_VENDOR_AMD:
         case X86_VENDOR_HYGON:
-            ret = IS_ENABLED(CONFIG_AMD) ? powernow_register_driver() : -ENODEV;
+#ifdef CONFIG_AMD
+            for ( i = 0; i < cpufreq_xen_cnt; i++ )
+            {
+                switch ( cpufreq_xen_opts[i] )
+                {
+                case CPUFREQ_xen:
+                    ret = powernow_register_driver();
+                    break;
+
+                case CPUFREQ_amd_cppc:
+                    ret = amd_cppc_register_driver();
+                    break;
+
+                case CPUFREQ_none:
+                    ret = 0;
+                    break;
+
+                default:
+                    printk(XENLOG_WARNING
+                           "Unsupported cpufreq driver for vendor AMD or Hygon\n");
+                    break;
+                }
+
+                if ( !ret || ret == -EBUSY )
+                    break;
+            }
+#else
+            ret = -ENODEV;
+#endif /* CONFIG_AMD */
             break;
 
         default:
             printk(XENLOG_ERR "Cpufreq: unsupported x86 vendor\n");
             break;
         }
+
+        /*
+         * After successful cpufreq driver registeration, XEN_PROCESSOR_PM_CPPC
+         * and XEN_PROCESSOR_PM_PX shall become exclusive flags.
+         */
+        if ( !ret )
+        {
+            ASSERT(i < cpufreq_xen_cnt);
+            switch ( cpufreq_xen_opts[i] )
+            {
+            case CPUFREQ_amd_cppc:
+                xen_processor_pmbits &= ~XEN_PROCESSOR_PM_PX;
+                break;
+
+            case CPUFREQ_hwp:
+            case CPUFREQ_xen:
+                xen_processor_pmbits &= ~XEN_PROCESSOR_PM_CPPC;
+                break;
+
+            default:
+                break;
+            }
+        }
+        else if ( ret != -EBUSY )
+            /*
+             * No cpufreq driver gets registered, clear both
+             * XEN_PROCESSOR_PM_CPPC and XEN_PROCESSOR_PM_PX
+             */
+             xen_processor_pmbits &= ~(XEN_PROCESSOR_PM_CPPC |
+                                       XEN_PROCESSOR_PM_PX);
     }
 
     return ret;
diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hypercall.c
index fafc176475..79bb99e0b6 100644
--- a/xen/arch/x86/platform_hypercall.c
+++ b/xen/arch/x86/platform_hypercall.c
@@ -546,6 +546,8 @@ ret_t do_platform_op(
                 ret = 0;
                 break;
             }
+            /* Xen doesn't support mixed mode */
+            ASSERT(!(xen_processor_pmbits & XEN_PROCESSOR_PM_CPPC));
 
             ret = set_px_pminfo(op->u.set_pminfo.id, &op->u.set_pminfo.u.perf);
             break;
@@ -578,6 +580,18 @@ ret_t do_platform_op(
         }
 
         case XEN_PM_CPPC:
+            if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_CPPC) )
+            {
+                /*
+                 * Neglect CPPC-info when registered cpufreq driver
+                 * isn't in CPPC mode
+                 */
+                ret = 0;
+                break;
+            }
+            /* Xen doesn't support mixed mode */
+            ASSERT(!(xen_processor_pmbits & XEN_PROCESSOR_PM_PX));
+
             ret = set_cppc_pminfo(op->u.set_pminfo.id,
                                   &op->u.set_pminfo.u.cppc_data);
             break;
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index e3b5c8bcaa..2f516e62b1 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -352,7 +352,8 @@ int do_pm_op(struct xen_sysctl_pm_op *op)
     switch ( op->cmd & PM_PARA_CATEGORY_MASK )
     {
     case CPUFREQ_PARA:
-        if ( !(xen_processor_pmbits & XEN_PROCESSOR_PM_PX) )
+        if ( !(xen_processor_pmbits & (XEN_PROCESSOR_PM_PX |
+                                       XEN_PROCESSOR_PM_CPPC)) )
             return -ENODEV;
         if ( !pmpt || !(pmpt->init & (XEN_PX_INIT | XEN_CPPC_INIT)) )
             return -EINVAL;
diff --git a/xen/drivers/cpufreq/cpufreq.c b/xen/drivers/cpufreq/cpufreq.c
index c6ce31c0ac..52b7ff71ad 100644
--- a/xen/drivers/cpufreq/cpufreq.c
+++ b/xen/drivers/cpufreq/cpufreq.c
@@ -65,7 +65,7 @@ LIST_HEAD_READ_MOSTLY(cpufreq_governor_list);
 /* set xen as default cpufreq */
 enum cpufreq_controller cpufreq_controller = FREQCTL_xen;
 
-enum cpufreq_xen_opt __initdata cpufreq_xen_opts[2] = { [0] = CPUFREQ_xen };
+enum cpufreq_xen_opt __initdata cpufreq_xen_opts[3] = { [0] = CPUFREQ_xen };
 unsigned int __initdata cpufreq_xen_cnt = 1;
 
 static int __init cpufreq_cmdline_parse(const char *s, const char *e);
@@ -99,6 +99,10 @@ static int __init handle_cpufreq_cmdline(enum cpufreq_xen_opt option)
         xen_processor_pmbits |= XEN_PROCESSOR_PM_PX;
         break;
 
+    case CPUFREQ_amd_cppc:
+        xen_processor_pmbits |= XEN_PROCESSOR_PM_CPPC;
+        break;
+
     default:
         ASSERT_UNREACHABLE();
         ret = -EINVAL;
@@ -162,6 +166,13 @@ static int __init cf_check setup_cpufreq_option(const char *str)
             if ( !ret && arg[0] && arg[1] )
                 ret = hwp_cmdline_parse(arg + 1, end);
         }
+        else if ( IS_ENABLED(CONFIG_AMD) && choice < 0 &&
+                  !cmdline_strcmp(str, "amd-cppc") )
+        {
+            ret = handle_cpufreq_cmdline(CPUFREQ_amd_cppc);
+            if ( !ret && arg[0] && arg[1] )
+                ret = amd_cppc_cmdline_parse(arg + 1, end);
+        }
         else
             ret = -EINVAL;
 
diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h
index fd530632b4..5d4881eea8 100644
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -26,8 +26,9 @@ enum cpufreq_xen_opt {
     CPUFREQ_none,
     CPUFREQ_xen,
     CPUFREQ_hwp,
+    CPUFREQ_amd_cppc,
 };
-extern enum cpufreq_xen_opt cpufreq_xen_opts[2];
+extern enum cpufreq_xen_opt cpufreq_xen_opts[3];
 extern unsigned int cpufreq_xen_cnt;
 struct cpufreq_governor;
 
@@ -272,4 +273,7 @@ int set_hwp_para(struct cpufreq_policy *policy,
 
 int acpi_cpufreq_register(void);
 
+int amd_cppc_cmdline_parse(const char *s, const char *e);
+int amd_cppc_register_driver(void);
+
 #endif /* __XEN_CPUFREQ_PM_H__ */
diff --git a/xen/include/acpi/cpufreq/processor_perf.h b/xen/include/acpi/cpufreq/processor_perf.h
index e6576314f0..0a87bc0384 100644
--- a/xen/include/acpi/cpufreq/processor_perf.h
+++ b/xen/include/acpi/cpufreq/processor_perf.h
@@ -5,6 +5,16 @@
 #include 
 #include 
 
+/*
+ * Internal xen-pm options
+ * They are extension to public xen-pm options (XEN_PROCESSOR_PM_xxx) defined
+ * in public/platform.h, guarded by SIF_PM_MASK
+ */
+#define XEN_PROCESSOR_PM_CPPC   0x100
+#if XEN_PROCESSOR_PM_CPPC & MASK_EXTR(~0, SIF_PM_MASK)
+# error "XEN_PROCESSOR_PM_CPPC shall not occupy bits reserved for public xen-pm options"
+#endif
+
 #define XEN_CPPC_INIT 0x40000000U
 #define XEN_PX_INIT   0x80000000U
 
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	, Andrew Cooper ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Anthony PERARD
	, Michal Orzel , "Julien
 Grall" , Stefano Stabellini 
Subject: [PATCH v8 3/8] xen/cpufreq: implement amd-cppc driver for CPPC in passive mode
Date: Thu, 28 Aug 2025 18:03:01 +0800
Message-ID: <20250828100306.1776031-4-Penny.Zheng@amd.com>
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amd-cppc is the AMD CPU performance scaling driver that introduces a
new CPU frequency control mechanism. The new mechanism is based on
Collaborative Processor Performance Control (CPPC) which is a finer grain
frequency management than legacy ACPI hardware P-States.
Current AMD CPU platforms are using the ACPI P-states driver to
manage CPU frequency and clocks with switching only in 3 P-states, while the
new amd-cppc allows a more flexible, low-latency interface for Xen
to directly communicate the performance hints to hardware.

"amd-cppc" driver is responsible for implementing CPPC in passive mode, which
still leverages Xen governors such as *ondemand*, *performance*, etc, to
calculate the performance hints. In the future, we will introduce an advanced
active mode to enable autonomous performence level selection.

Field epp, energy performance preference, which only has meaning when active
mode is enabled and will be introduced later in details, so we read
pre-defined BIOS value for it in passive mode.

Signed-off-by: Penny Zheng 
Acked-by: Jan Beulich 
---
---
v1 -> v2:
- re-construct union caps and req to have anonymous struct instead
- avoid "else" when the earlier if() ends in an unconditional control flow statement
- Add check to avoid chopping off set bits from cast
- make pointers pointer-to-const wherever possible
- remove noisy log
- exclude families before 0x17 before CPPC-feature MSR op
- remove useless variable helpers
- use xvzalloc and XVFREE
- refactor error handling as ENABLE bit can only be cleared by reset
---
v2 -> v3:
- Move all MSR-definations to msr-index.h and follow the required style
- Refactor opening figure braces for struct/union
- Sort overlong lines throughout the series
- Make offset/res int covering underflow scenario
- Error out when amd_max_freq_mhz isn't set
- Introduce amd_get_freq(name) macro to decrease redundancy
- Supported CPU family checked ahead of smp-function
- Nominal freq shall be checked between the [min, max]
- Use APERF/MPREF to calculate current frequency
- Use amd_cppc_cpufreq_cpu_exit() to tidy error path
---
v3 -> v4:
- verbose print shall come with a CPU number
- deal with res <= 0 in amd_cppc_khz_to_perf()
- introduce a single helper amd_get_lowest_or_nominal_freq() to cover both
lowest and nominal scenario
- reduce abuse of wrmsr_safe()/rdmsr_safe() with wrmsrl()/rdmsrl()
- move cf_check from amd_cppc_write_request() to amd_cppc_write_request_msrs()
- add comment to explain why setting non_linear_lowest in passive mode
- add check to ensure perf values in
lowest <= non_linear_lowest <= nominal <= highset
- refactor comment for "data->err != 0" scenario
- use "data->err" instead of -ENODEV
- add U suffixes for all msr macro
---
v4 -> v5:
- all freq-values shall be unsigned int type
- remove shortcuts as it is rarely taken
- checking cpc.nominal_mhz and cpc.lowest_mhz are non-zero values is enough
- drop the explicit type cast
- null pointer check is in no need for internal functions
- change amd_get_lowest_or_nominal_freq() to amd_get_cpc_freq()
- clarifying function-wide that the calculated frequency result is to be in kHz
- use array notation
- with cpu_has_cppc check, no need to do cpu family check
---
v5 -> v6
- replace "AMD_CPPC" with "AMD-CPPC" in message
- add equation(mul,div) non-zero check
- replace -EINVAL with -EOPNOTSUPP
- refactor comment
---
v6 -> v7
- used > in place of !=, to not only serve a doc aspect, but also allow to
drop one part
- unify with UINT8_MAX
- return -ERANGE as we reject perf values of 0 as invalid
- replace uint32_t with unsigned int
- Move some epp introduction here, otherwise we will mis-handle this field here
by always clearing it
---
v7 -> v8:
- refine message text by removing 0
---
 xen/arch/x86/acpi/cpufreq/amd-cppc.c | 418 ++++++++++++++++++++++++++-
 xen/arch/x86/cpu/amd.c               |   8 +-
 xen/arch/x86/include/asm/amd.h       |   2 +
 xen/arch/x86/include/asm/msr-index.h |   6 +
 xen/include/public/sysctl.h          |   1 +
 5 files changed, 430 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
index 3377783f7e..5b99b86fb7 100644
--- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c
+++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
@@ -14,7 +14,98 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
+#include 
+#include 
+
+#define amd_cppc_err(cpu, fmt, args...)                             \
+    printk(XENLOG_ERR "AMD-CPPC: CPU%u error: " fmt, cpu, ## args)
+#define amd_cppc_warn(cpu, fmt, args...)                            \
+    printk(XENLOG_WARNING "AMD-CPPC: CPU%u warning: " fmt, cpu, ## args)
+#define amd_cppc_verbose(cpu, fmt, args...)                         \
+({                                                                  \
+    if ( cpufreq_verbose )                                          \
+        printk(XENLOG_DEBUG "AMD-CPPC: CPU%u " fmt, cpu, ## args);  \
+})
+
+/*
+ * Field highest_perf, nominal_perf, lowest_nonlinear_perf, and lowest_perf
+ * contain the values read from CPPC capability MSR. They represent the limits
+ * of managed performance range as well as the dynamic capability, which may
+ * change during processor operation
+ * Field highest_perf represents highest performance, which is the absolute
+ * maximum performance an individual processor may reach, assuming ideal
+ * conditions. This performance level may not be sustainable for long
+ * durations and may only be achievable if other platform components
+ * are in a specific state; for example, it may require other processors be
+ * in an idle state. This would be equivalent to the highest frequencies
+ * supported by the processor.
+ * Field nominal_perf represents maximum sustained performance level of the
+ * processor, assuming ideal operating conditions. All cores/processors are
+ * expected to be able to sustain their nominal performance state
+ * simultaneously.
+ * Field lowest_nonlinear_perf represents Lowest Nonlinear Performance, which
+ * is the lowest performance level at which nonlinear power savings are
+ * achieved. Above this threshold, lower performance levels should be
+ * generally more energy efficient than higher performance levels. So in
+ * traditional terms, this represents the P-state range of performance levels.
+ * Field lowest_perf represents the absolute lowest performance level of the
+ * platform. Selecting it may cause an efficiency penalty but should reduce
+ * the instantaneous power consumption of the processor. So in traditional
+ * terms, this represents the T-state range of performance levels.
+ *
+ * Field max_perf, min_perf, des_perf store the values for CPPC request MSR.
+ * Software passes performance goals through these fields.
+ * Field max_perf conveys the maximum performance level at which the platform
+ * may run. And it may be set to any performance value in the range
+ * [lowest_perf, highest_perf], inclusive.
+ * Field min_perf conveys the minimum performance level at which the platform
+ * may run. And it may be set to any performance value in the range
+ * [lowest_perf, highest_perf], inclusive but must be less than or equal to
+ * max_perf.
+ * Field des_perf conveys performance level Xen governor is requesting. And it
+ * may be set to any performance value in the range [min_perf, max_perf],
+ * inclusive.
+ * Field epp represents energy performance preference, which only has meaning
+ * when active mode is enabled.
+ */
+struct amd_cppc_drv_data
+{
+    const struct xen_processor_cppc *cppc_data;
+    union {
+        uint64_t raw;
+        struct {
+            unsigned int lowest_perf:8;
+            unsigned int lowest_nonlinear_perf:8;
+            unsigned int nominal_perf:8;
+            unsigned int highest_perf:8;
+            unsigned int :32;
+        };
+    } caps;
+    union {
+        uint64_t raw;
+        struct {
+            unsigned int max_perf:8;
+            unsigned int min_perf:8;
+            unsigned int des_perf:8;
+            unsigned int epp:8;
+            unsigned int :32;
+        };
+    } req;
+
+    int err;
+};
+
+static DEFINE_PER_CPU_READ_MOSTLY(struct amd_cppc_drv_data *,
+                                  amd_cppc_drv_data);
+/*
+ * Core max frequency read from PstateDef as anchor point
+ * for freq-to-perf transition
+ */
+static DEFINE_PER_CPU_READ_MOSTLY(unsigned int, pxfreq_mhz);
+static DEFINE_PER_CPU_READ_MOSTLY(uint8_t, epp_init);
 
 static bool __init amd_cppc_handle_option(const char *s, const char *end)
 {
@@ -50,10 +141,335 @@ int __init amd_cppc_cmdline_parse(const char *s, const char *e)
     return 0;
 }
 
+/*
+ * If CPPC lowest_freq and nominal_freq registers are exposed then we can
+ * use them to convert perf to freq and vice versa. The conversion is
+ * extrapolated as an linear function passing by the 2 points:
+ *  - (Low perf, Low freq)
+ *  - (Nominal perf, Nominal freq)
+ * Parameter freq is always in kHz.
+ */
+static int amd_cppc_khz_to_perf(const struct amd_cppc_drv_data *data,
+                                unsigned int freq, uint8_t *perf)
+{
+    const struct xen_processor_cppc *cppc_data = data->cppc_data;
+    unsigned int mul, div;
+    int offset = 0, res;
+
+    if ( cppc_data->cpc.lowest_mhz &&
+         data->caps.nominal_perf > data->caps.lowest_perf &&
+         cppc_data->cpc.nominal_mhz > cppc_data->cpc.lowest_mhz )
+    {
+        mul = data->caps.nominal_perf - data->caps.lowest_perf;
+        div = cppc_data->cpc.nominal_mhz - cppc_data->cpc.lowest_mhz;
+
+        /*
+         * We don't need to convert to kHz for computing offset and can
+         * directly use nominal_mhz and lowest_mhz as the division
+         * will remove the frequency unit.
+         */
+        offset = data->caps.nominal_perf -
+                 (mul * cppc_data->cpc.nominal_mhz) / div;
+    }
+    else
+    {
+        /* Read Processor Max Speed(MHz) as anchor point */
+        mul = data->caps.highest_perf;
+        div = this_cpu(pxfreq_mhz);
+        if ( !div )
+            return -EOPNOTSUPP;
+    }
+
+    res = offset + (mul * freq) / (div * 1000);
+    if ( res > UINT8_MAX )
+    {
+        printk_once(XENLOG_WARNING
+                    "Perf value exceeds maximum value 255: %d\n", res);
+        *perf = UINT8_MAX;
+        return 0;
+    }
+    if ( res <= 0 )
+    {
+        printk_once(XENLOG_WARNING
+                    "Perf value smaller than minimum value: %d\n", res);
+        return -ERANGE;
+    }
+    *perf = res;
+
+    return 0;
+}
+
+/*
+ * _CPC may define nominal frequecy and lowest frequency, if not, use
+ * Processor Max Speed as anchor point to calculate.
+ * Output freq stores cpc frequency in kHz
+ */
+static int amd_get_cpc_freq(const struct amd_cppc_drv_data *data,
+                            unsigned int cpc_mhz, uint8_t perf,
+                            unsigned int *freq)
+{
+    unsigned int mul, div, res;
+
+    if ( cpc_mhz )
+    {
+        /* Switch to kHz */
+        *freq = cpc_mhz * 1000;
+        return 0;
+    }
+
+    /* Read Processor Max Speed(MHz) as anchor point */
+    mul = this_cpu(pxfreq_mhz);
+    if ( !mul )
+        return -EOPNOTSUPP;
+    div = data->caps.highest_perf;
+    res = (mul * perf * 1000) / div;
+    if ( unlikely(!res) )
+        return -EOPNOTSUPP;
+
+    return 0;
+}
+
+/* Output max_freq stores calculated maximum frequency in kHz */
+static int amd_get_max_freq(const struct amd_cppc_drv_data *data,
+                            unsigned int *max_freq)
+{
+    unsigned int nom_freq = 0;
+    int res;
+
+    res = amd_get_cpc_freq(data, data->cppc_data->cpc.nominal_mhz,
+                           data->caps.nominal_perf, &nom_freq);
+    if ( res )
+        return res;
+
+    *max_freq = (data->caps.highest_perf * nom_freq) / data->caps.nominal_perf;
+
+    return 0;
+}
+
+static int cf_check amd_cppc_cpufreq_verify(struct cpufreq_policy *policy)
+{
+    cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
+                                 policy->cpuinfo.max_freq);
+
+    return 0;
+}
+
+static void cf_check amd_cppc_write_request_msrs(void *info)
+{
+    const struct amd_cppc_drv_data *data = info;
+
+    wrmsrl(MSR_AMD_CPPC_REQ, data->req.raw);
+}
+
+static void amd_cppc_write_request(unsigned int cpu, uint8_t min_perf,
+                                   uint8_t des_perf, uint8_t max_perf,
+                                   uint8_t epp)
+{
+    struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);
+    uint64_t prev = data->req.raw;
+
+    data->req.min_perf = min_perf;
+    data->req.max_perf = max_perf;
+    data->req.des_perf = des_perf;
+    data->req.epp = epp;
+
+    if ( prev == data->req.raw )
+        return;
+
+    on_selected_cpus(cpumask_of(cpu), amd_cppc_write_request_msrs, data, 1);
+}
+
+static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy,
+                                            unsigned int target_freq,
+                                            unsigned int relation)
+{
+    unsigned int cpu = policy->cpu;
+    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);
+    uint8_t des_perf;
+    int res;
+
+    if ( unlikely(!target_freq) )
+        return 0;
+
+    res = amd_cppc_khz_to_perf(data, target_freq, &des_perf);
+    if ( res )
+        return res;
+
+    /*
+     * Having a performance level lower than the lowest nonlinear
+     * performance level, such as, lowest_perf <= perf <= lowest_nonliner_perf,
+     * may actually cause an efficiency penalty, So when deciding the min_perf
+     * value, we prefer lowest nonlinear performance over lowest performance.
+     */
+    amd_cppc_write_request(policy->cpu, data->caps.lowest_nonlinear_perf,
+                           des_perf, data->caps.highest_perf,
+                           /* Pre-defined BIOS value for passive mode */
+                           per_cpu(epp_init, policy->cpu));
+    return 0;
+}
+
+static void cf_check amd_cppc_init_msrs(void *info)
+{
+    struct cpufreq_policy *policy = info;
+    struct amd_cppc_drv_data *data = this_cpu(amd_cppc_drv_data);
+    uint64_t val;
+    unsigned int min_freq = 0, nominal_freq = 0, max_freq;
+
+    /* Package level MSR */
+    rdmsrl(MSR_AMD_CPPC_ENABLE, val);
+    /*
+     * Only when Enable bit is on, the hardware will calculate the processor’s
+     * performance capabilities and initialize the performance level fields in
+     * the CPPC capability registers.
+     */
+    if ( !(val & AMD_CPPC_ENABLE) )
+    {
+        val |= AMD_CPPC_ENABLE;
+        wrmsrl(MSR_AMD_CPPC_ENABLE, val);
+    }
+
+    rdmsrl(MSR_AMD_CPPC_CAP1, data->caps.raw);
+
+    if ( data->caps.highest_perf == 0 || data->caps.lowest_perf == 0 ||
+         data->caps.nominal_perf == 0 || data->caps.lowest_nonlinear_perf == 0 ||
+         data->caps.lowest_perf > data->caps.lowest_nonlinear_perf ||
+         data->caps.lowest_nonlinear_perf > data->caps.nominal_perf ||
+         data->caps.nominal_perf > data->caps.highest_perf )
+    {
+        amd_cppc_err(policy->cpu,
+                     "Out of range values: highest(%u), lowest(%u), nominal(%u), lowest_nonlinear(%u)\n",
+                     data->caps.highest_perf, data->caps.lowest_perf,
+                     data->caps.nominal_perf, data->caps.lowest_nonlinear_perf);
+        goto err;
+    }
+
+    amd_process_freq(&cpu_data[policy->cpu],
+                     NULL, NULL, &this_cpu(pxfreq_mhz));
+
+    data->err = amd_get_cpc_freq(data, data->cppc_data->cpc.lowest_mhz,
+                                 data->caps.lowest_perf, &min_freq);
+    if ( data->err )
+        return;
+
+    data->err = amd_get_cpc_freq(data, data->cppc_data->cpc.nominal_mhz,
+                                 data->caps.nominal_perf, &nominal_freq);
+    if ( data->err )
+        return;
+
+    data->err = amd_get_max_freq(data, &max_freq);
+    if ( data->err )
+        return;
+
+    if ( min_freq > nominal_freq || nominal_freq > max_freq )
+    {
+        amd_cppc_err(policy->cpu,
+                     "min(%u), or max(%u), or nominal(%u) freq value is incorrect\n",
+                     min_freq, max_freq, nominal_freq);
+        goto err;
+    }
+
+    policy->min = min_freq;
+    policy->max = max_freq;
+
+    policy->cpuinfo.min_freq = min_freq;
+    policy->cpuinfo.max_freq = max_freq;
+    policy->cpuinfo.perf_freq = nominal_freq;
+    /*
+     * Set after policy->cpuinfo.perf_freq, as we are taking
+     * APERF/MPERF average frequency as current frequency.
+     */
+    policy->cur = cpufreq_driver_getavg(policy->cpu, GOV_GETAVG);
+
+    /* Store pre-defined BIOS value for passive mode */
+    rdmsrl(MSR_AMD_CPPC_REQ, val);
+    this_cpu(epp_init) = MASK_EXTR(val, AMD_CPPC_EPP_MASK);
+
+    return;
+
+ err:
+    /*
+     * No fallback shceme is available here, see more explanation at call
+     * site in amd_cppc_cpufreq_cpu_init().
+     */
+    data->err = -EINVAL;
+}
+
+/*
+ * AMD CPPC driver is different than legacy ACPI hardware P-State,
+ * which has a finer grain frequency range between the highest and lowest
+ * frequency. And boost frequency is actually the frequency which is mapped on
+ * highest performance ratio. The legacy P0 frequency is actually mapped on
+ * nominal performance ratio.
+ */
+static void amd_cppc_boost_init(struct cpufreq_policy *policy,
+                                const struct amd_cppc_drv_data *data)
+{
+    if ( data->caps.highest_perf <= data->caps.nominal_perf )
+        return;
+
+    policy->turbo = CPUFREQ_TURBO_ENABLED;
+}
+
+static int cf_check amd_cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy)
+{
+    XVFREE(per_cpu(amd_cppc_drv_data, policy->cpu));
+
+    return 0;
+}
+
+static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+    unsigned int cpu = policy->cpu;
+    struct amd_cppc_drv_data *data;
+
+    data = xvzalloc(struct amd_cppc_drv_data);
+    if ( !data )
+        return -ENOMEM;
+
+    data->cppc_data = &processor_pminfo[cpu]->cppc_data;
+
+    per_cpu(amd_cppc_drv_data, cpu) = data;
+
+    on_selected_cpus(cpumask_of(cpu), amd_cppc_init_msrs, policy, 1);
+
+    /*
+     * The enable bit is sticky, as we need to enable it at the very first
+     * begining, before CPPC capability values sanity check.
+     * If error path is taken effective, not only amd-cppc cpufreq core fails
+     * to initialize, but also we could not fall back to legacy P-states
+     * driver, irrespective of the command line specifying a fallback option.
+     */
+    if ( data->err )
+    {
+        amd_cppc_err(cpu, "Could not initialize cpufreq core in CPPC mode\n");
+        amd_cppc_cpufreq_cpu_exit(policy);
+        return data->err;
+    }
+
+    policy->governor = cpufreq_opt_governor ? : CPUFREQ_DEFAULT_GOVERNOR;
+
+    amd_cppc_boost_init(policy, data);
+
+    amd_cppc_verbose(policy->cpu,
+                     "CPU initialized with amd-cppc passive mode\n");
+
+    return 0;
+}
+
+static const struct cpufreq_driver __initconst_cf_clobber
+amd_cppc_cpufreq_driver =
+{
+    .name   = XEN_AMD_CPPC_DRIVER_NAME,
+    .verify = amd_cppc_cpufreq_verify,
+    .target = amd_cppc_cpufreq_target,
+    .init   = amd_cppc_cpufreq_cpu_init,
+    .exit   = amd_cppc_cpufreq_cpu_exit,
+};
+
 int __init amd_cppc_register_driver(void)
 {
     if ( !cpu_has_cppc )
         return -ENODEV;
 
-    return -EOPNOTSUPP;
+    return cpufreq_register_driver(&amd_cppc_cpufreq_driver);
 }
diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 567b992a9f..9767f63539 100644
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -613,10 +613,10 @@ static unsigned int attr_const amd_parse_freq(unsigned int family,
 	return freq;
 }
 
-static void amd_process_freq(const struct cpuinfo_x86 *c,
-			     unsigned int *low_mhz,
-			     unsigned int *nom_mhz,
-			     unsigned int *hi_mhz)
+void amd_process_freq(const struct cpuinfo_x86 *c,
+		      unsigned int *low_mhz,
+		      unsigned int *nom_mhz,
+		      unsigned int *hi_mhz)
 {
 	unsigned int idx = 0, h;
 	uint64_t hi, lo, val;
diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h
index 9c9599a622..72df42a6f6 100644
--- a/xen/arch/x86/include/asm/amd.h
+++ b/xen/arch/x86/include/asm/amd.h
@@ -173,5 +173,7 @@ extern bool amd_virt_spec_ctrl;
 bool amd_setup_legacy_ssbd(void);
 void amd_set_legacy_ssbd(bool enable);
 void amd_set_cpuid_user_dis(bool enable);
+void amd_process_freq(const struct cpuinfo_x86 *c, unsigned int *low_mhz,
+                      unsigned int *nom_mhz, unsigned int *hi_mhz);
 
 #endif /* __AMD_H__ */
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 428d993ee8..6abf154887 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -241,6 +241,12 @@
 
 #define MSR_AMD_CSTATE_CFG                  0xc0010296U
 
+#define MSR_AMD_CPPC_CAP1                   0xc00102b0U
+#define MSR_AMD_CPPC_ENABLE                 0xc00102b1U
+#define  AMD_CPPC_ENABLE                    (_AC(1, ULL) << 0)
+#define MSR_AMD_CPPC_REQ                    0xc00102b3U
+#define  AMD_CPPC_EPP_MASK                  (_AC(0xff, ULL) << 24)
+
 /*
  * Legacy MSR constants in need of cleanup.  No new MSRs below this comment.
  */
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index aafa7fcf2b..aa29a5401c 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -453,6 +453,7 @@ struct xen_set_cppc_para {
     uint32_t activity_window;
 };
 
+#define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc"
 #define XEN_HWP_DRIVER_NAME "hwp"
 
 /*
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Jan Beulich
	
Subject: [PATCH v8 5/8] xen/cpufreq: get performance policy from governor set via xenpm
Date: Thu, 28 Aug 2025 18:04:43 +0800
Message-ID: <20250828100443.1776675-1-Penny.Zheng@amd.com>
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Even if Xen governor is not used in amd-cppc active mode, we could
somehow deduce which performance policy (CPUFREQ_POLICY_xxx) user wants to
apply through which governor they choose, such as:
If user chooses performance governor, they want maximum performance, then
the policy shall be CPUFREQ_POLICY_PERFORMANCE
If user chooses powersave governor, they want the least power consumption,
then the policy shall be CPUFREQ_POLICY_POWERSAVE
Function cpufreq_policy_from_governor() is responsible for above transition,
and it shall be also effective when users setting new governor through xenpm.

Userspace is a forbidden choice, and if users specify such option, we shall
not only give warning message to suggest using "xenpm set-cpufreq-cppc", but
also error out.

Signed-off-by: Penny Zheng 
---
v4 -> v5:
- new commit
---
v5 -> v6:
- refactor warning message
---
v6 -> v7:
- move policy->policy set where it firstly gets introduced
- refactor commit message
---
v7 -> v8:
- policy transition is only limited in CPPC mode
---
 xen/drivers/acpi/pm-op.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index 2f516e62b1..a7eaf29c31 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -207,6 +207,17 @@ static int set_cpufreq_gov(struct xen_sysctl_pm_op *op)
     if ( new_policy.governor == NULL )
         return -EINVAL;
 
+    if ( processor_pminfo[op->cpuid]->init & XEN_CPPC_INIT )
+    {
+        new_policy.policy = cpufreq_policy_from_governor(new_policy.governor);
+        if ( new_policy.policy == CPUFREQ_POLICY_UNKNOWN )
+        {
+            printk("Failed to get performance policy from %s, Try \"xenpm set-cpufreq-cppc\"\n",
+                   new_policy.governor->name);
+            return -EINVAL;
+        }
+    }
+
     return __cpufreq_set_policy(old_policy, &new_policy);
 }
 
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Anthony PERARD
	, Juergen Gross , Andrew Cooper
	, Michal Orzel , Jan Beulich
	, Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , "Stefano
 Stabellini" 
Subject: [PATCH v8 6/8] tools/cpufreq: extract CPPC para from cpufreq para
Date: Thu, 28 Aug 2025 18:05:10 +0800
Message-ID: <20250828100510.1776855-1-Penny.Zheng@amd.com>
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We extract cppc info from "struct xen_get_cpufreq_para", where it acts as
a member of union, and share the space with governor info.
However, it may fail in amd-cppc passive mode, in which governor info and
CPPC info could co-exist, and both need to be printed together via xenpm tool.
If we tried to still put it in "struct xen_get_cpufreq_para" (e.g. just move
out of union), "struct xen_get_cpufreq_para" will enlarge too much to further
make xen_sysctl.u exceed 128 bytes.

So we introduce a new sub-field GET_CPUFREQ_CPPC to dedicatedly acquire
CPPC-related para, and make get-cpufreq-para invoke GET_CPUFREQ_CPPC
if available.
New helpers print_cppc_para() and get_cpufreq_cppc() are introduced to
extract CPPC-related parameters process from cpufreq para.

Signed-off-by: Penny Zheng 
Acked-by: Jan Beulich  # hypervisor
Acked-by: Anthony PERARD 
---
v4 -> v5:
- new commit
---
v5 -> v6:
- remove the changes for get-cpufreq-para
---
v6 -> v7:
- make get-cpufreq-para invoke GET_CPUFREQ_CPPC
---
v7 -> v8:
- use structure assignment as it is a alias
- add errno info to the error print
---
 tools/include/xenctrl.h     |  3 +-
 tools/libs/ctrl/xc_pm.c     | 25 +++++++++++-
 tools/misc/xenpm.c          | 79 ++++++++++++++++++++++++-------------
 xen/drivers/acpi/pm-op.c    | 19 +++++++--
 xen/include/public/sysctl.h |  3 +-
 5 files changed, 96 insertions(+), 33 deletions(-)

diff --git a/tools/include/xenctrl.h b/tools/include/xenctrl.h
index 965d3b585a..e5103453a9 100644
--- a/tools/include/xenctrl.h
+++ b/tools/include/xenctrl.h
@@ -1938,7 +1938,6 @@ struct xc_get_cpufreq_para {
                 xc_ondemand_t ondemand;
             } u;
         } s;
-        xc_cppc_para_t cppc_para;
     } u;
 
     int32_t turbo_enabled;
@@ -1953,6 +1952,8 @@ int xc_set_cpufreq_para(xc_interface *xch, int cpuid,
                         int ctrl_type, int ctrl_value);
 int xc_set_cpufreq_cppc(xc_interface *xch, int cpuid,
                         xc_set_cppc_para_t *set_cppc);
+int xc_get_cppc_para(xc_interface *xch, unsigned int cpuid,
+                     xc_cppc_para_t *cppc_para);
 int xc_get_cpufreq_avgfreq(xc_interface *xch, int cpuid, int *avg_freq);
 
 int xc_set_sched_opt_smt(xc_interface *xch, uint32_t value);
diff --git a/tools/libs/ctrl/xc_pm.c b/tools/libs/ctrl/xc_pm.c
index 6fda973f1f..56e213018a 100644
--- a/tools/libs/ctrl/xc_pm.c
+++ b/tools/libs/ctrl/xc_pm.c
@@ -288,7 +288,6 @@ int xc_get_cpufreq_para(xc_interface *xch, int cpuid,
         CHK_FIELD(s.scaling_min_freq);
         CHK_FIELD(s.u.userspace);
         CHK_FIELD(s.u.ondemand);
-        CHK_FIELD(cppc_para);
 
 #undef CHK_FIELD
 
@@ -366,6 +365,30 @@ int xc_set_cpufreq_cppc(xc_interface *xch, int cpuid,
     return ret;
 }
 
+int xc_get_cppc_para(xc_interface *xch, unsigned int cpuid,
+                     xc_cppc_para_t *cppc_para)
+{
+    int ret;
+    struct xen_sysctl sysctl = {};
+
+    if ( !xch  || !cppc_para )
+    {
+        errno = EINVAL;
+        return -1;
+    }
+
+    sysctl.cmd = XEN_SYSCTL_pm_op;
+    sysctl.u.pm_op.cmd = GET_CPUFREQ_CPPC;
+    sysctl.u.pm_op.cpuid = cpuid;
+
+    ret = xc_sysctl(xch, &sysctl);
+    if ( ret )
+        return ret;
+
+    *cppc_para = sysctl.u.pm_op.u.get_cppc;
+    return ret;
+}
+
 int xc_get_cpufreq_avgfreq(xc_interface *xch, int cpuid, int *avg_freq)
 {
     int ret = 0;
diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
index 6b054b10a4..e83dd0d80c 100644
--- a/tools/misc/xenpm.c
+++ b/tools/misc/xenpm.c
@@ -801,6 +801,34 @@ static unsigned int calculate_activity_window(const xc_cppc_para_t *cppc,
     return mantissa * multiplier;
 }
 
+/* print out parameters about cpu cppc */
+static void print_cppc_para(unsigned int cpuid,
+                            const xc_cppc_para_t *cppc)
+{
+    printf("cppc variables       :\n");
+    printf("  hardware limits    : lowest [%"PRIu32"] lowest nonlinear [%"PRIu32"]\n",
+           cppc->lowest, cppc->lowest_nonlinear);
+    printf("                     : nominal [%"PRIu32"] highest [%"PRIu32"]\n",
+           cppc->nominal, cppc->highest);
+    printf("  configured limits  : min [%"PRIu32"] max [%"PRIu32"] energy perf [%"PRIu32"]\n",
+           cppc->minimum, cppc->maximum, cppc->energy_perf);
+
+    if ( cppc->features & XEN_SYSCTL_CPPC_FEAT_ACT_WINDOW )
+    {
+        unsigned int activity_window;
+        const char *units;
+
+        activity_window = calculate_activity_window(cppc, &units);
+        printf("                     : activity_window [%"PRIu32" %s]\n",
+               activity_window, units);
+    }
+
+    printf("                     : desired [%"PRIu32"%s]\n",
+           cppc->desired,
+           cppc->desired ? "" : " hw autonomous");
+    printf("\n");
+}
+
 /* print out parameters about cpu frequency */
 static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
 {
@@ -826,33 +854,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
 
     printf("scaling_driver       : %s\n", p_cpufreq->scaling_driver);
 
-    if ( hwp )
-    {
-        const xc_cppc_para_t *cppc = &p_cpufreq->u.cppc_para;
-
-        printf("cppc variables       :\n");
-        printf("  hardware limits    : lowest [%"PRIu32"] lowest nonlinear [%"PRIu32"]\n",
-               cppc->lowest, cppc->lowest_nonlinear);
-        printf("                     : nominal [%"PRIu32"] highest [%"PRIu32"]\n",
-               cppc->nominal, cppc->highest);
-        printf("  configured limits  : min [%"PRIu32"] max [%"PRIu32"] energy perf [%"PRIu32"]\n",
-               cppc->minimum, cppc->maximum, cppc->energy_perf);
-
-        if ( cppc->features & XEN_SYSCTL_CPPC_FEAT_ACT_WINDOW )
-        {
-            unsigned int activity_window;
-            const char *units;
-
-            activity_window = calculate_activity_window(cppc, &units);
-            printf("                     : activity_window [%"PRIu32" %s]\n",
-                   activity_window, units);
-        }
-
-        printf("                     : desired [%"PRIu32"%s]\n",
-               cppc->desired,
-               cppc->desired ? "" : " hw autonomous");
-    }
-    else
+    if ( !hwp )
     {
         if ( p_cpufreq->gov_num )
             printf("scaling_avail_gov    : %s\n",
@@ -898,6 +900,24 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
     printf("\n");
 }
 
+/* show cpu cppc parameters information on CPU cpuid */
+static int show_cppc_para_by_cpuid(xc_interface *xc_handle, unsigned int cpuid)
+{
+    int ret;
+    xc_cppc_para_t cppc_para;
+
+    ret = xc_get_cppc_para(xc_handle, cpuid, &cppc_para);
+    if ( !ret )
+        print_cppc_para(cpuid, &cppc_para);
+    else if ( errno == ENODEV )
+        ret = 0; /* Ignore unsupported platform */
+    else
+        fprintf(stderr, "[CPU%u] failed to get cppc parameter: %s\n",
+                cpuid, strerror(errno));
+
+    return ret;
+}
+
 /* show cpu frequency parameters information on CPU cpuid */
 static int show_cpufreq_para_by_cpuid(xc_interface *xc_handle, int cpuid)
 {
@@ -957,7 +977,12 @@ static int show_cpufreq_para_by_cpuid(xc_interface *xc_handle, int cpuid)
     } while ( ret && errno == EAGAIN );
 
     if ( ret == 0 )
+    {
         print_cpufreq_para(cpuid, p_cpufreq);
+
+        /* Show CPPC parameters if available */
+        ret = show_cppc_para_by_cpuid(xc_handle, cpuid);
+    }
     else if ( errno == ENODEV )
     {
         ret = -ENODEV;
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index a7eaf29c31..19aedf6b0b 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -77,6 +77,17 @@ static int read_scaling_available_governors(char *scaling_available_governors,
     return 0;
 }
 
+static int get_cpufreq_cppc(unsigned int cpu,
+                            struct xen_get_cppc_para *cppc_para)
+{
+    int ret = -ENODEV;
+
+    if ( hwp_active() )
+        ret = get_hwp_para(cpu, cppc_para);
+
+    return ret;
+}
+
 static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
 {
     uint32_t ret = 0;
@@ -143,9 +154,7 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
     else
         strlcpy(op->u.get_para.scaling_driver, "Unknown", CPUFREQ_NAME_LEN);
 
-    if ( hwp_active() )
-        ret = get_hwp_para(policy->cpu, &op->u.get_para.u.cppc_para);
-    else
+    if ( !hwp_active() )
     {
         if ( !(scaling_available_governors =
                xzalloc_array(char, gov_num * CPUFREQ_NAME_LEN)) )
@@ -385,6 +394,10 @@ int do_pm_op(struct xen_sysctl_pm_op *op)
         ret = set_cpufreq_para(op);
         break;
 
+    case GET_CPUFREQ_CPPC:
+        ret = get_cpufreq_cppc(op->cpuid, &op->u.get_cppc);
+        break;
+
     case SET_CPUFREQ_CPPC:
         ret = set_cpufreq_cppc(op);
         break;
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index eb3a23b038..3f654f98ab 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -492,7 +492,6 @@ struct xen_get_cpufreq_para {
                 struct  xen_ondemand ondemand;
             } u;
         } s;
-        struct xen_get_cppc_para cppc_para;
     } u;
 
     int32_t turbo_enabled;
@@ -523,6 +522,7 @@ struct xen_sysctl_pm_op {
     #define SET_CPUFREQ_PARA           (CPUFREQ_PARA | 0x03)
     #define GET_CPUFREQ_AVGFREQ        (CPUFREQ_PARA | 0x04)
     #define SET_CPUFREQ_CPPC           (CPUFREQ_PARA | 0x05)
+    #define GET_CPUFREQ_CPPC           (CPUFREQ_PARA | 0x06)
 
     /* set/reset scheduler power saving option */
     #define XEN_SYSCTL_pm_op_set_sched_opt_smt    0x21
@@ -547,6 +547,7 @@ struct xen_sysctl_pm_op {
     uint32_t cpuid;
     union {
         struct xen_get_cpufreq_para get_para;
+        struct xen_get_cppc_para    get_cppc;
         struct xen_set_cpufreq_gov  set_gov;
         struct xen_set_cpufreq_para set_para;
         struct xen_set_cppc_para    set_cppc;
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Anthony PERARD
	, Jan Beulich 
Subject: [PATCH v8 7/8] xen/cpufreq: bypass governor-related para for amd-cppc-epp
Date: Thu, 28 Aug 2025 18:05:34 +0800
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HWP and amd-cppc-epp are both governor-less driver, so we introduce
"is_governor_less" flag and cpufreq_is_governorless() to help bypass
governor-related info on dealing with cpufreq para.

Signed-off-by: Penny Zheng 
---
v3 -> v4:
- Include validation check fix here
---
v4 -> v5:
- validation check has beem moved to where XEN_PROCESSOR_PM_CPPC and
XEN_CPPC_INIT have been firstly introduced
- adding "cpufreq_driver.setpolicy == NULL" check to exclude governor-related
para for amd-cppc-epp driver in get/set_cpufreq_para()
---
v5 -> v6:
- add helper cpufreq_is_governorless() to tell whether cpufreq driver is
governor-less
---
v6 -> v7:
- change "hw_auto" to "is_goverless"
- complement comment
- wrap around with PM_OP to avoid violating Misra rule 2.1
---
v7 -> v8:
- change "is_goverless" to "is_governor_less"
- make cpufreq_is_governorless() inline function
---
 tools/misc/xenpm.c                 | 10 +++++++---
 xen/drivers/acpi/pm-op.c           |  4 ++--
 xen/include/acpi/cpufreq/cpufreq.h | 12 ++++++++++++
 3 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
index e83dd0d80c..893a0afe11 100644
--- a/tools/misc/xenpm.c
+++ b/tools/misc/xenpm.c
@@ -832,9 +832,13 @@ static void print_cppc_para(unsigned int cpuid,
 /* print out parameters about cpu frequency */
 static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
 {
-    bool hwp = strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) == 0;
+    bool is_governor_less = false;
     int i;
 
+    if ( !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) ||
+         !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) )
+        is_governor_less = true;
+
     printf("cpu id               : %d\n", cpuid);
 
     printf("affected_cpus        :");
@@ -842,7 +846,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
         printf(" %d", p_cpufreq->affected_cpus[i]);
     printf("\n");
 
-    if ( hwp )
+    if ( is_governor_less )
         printf("cpuinfo frequency    : base [%"PRIu32"] max [%"PRIu32"]\n",
                p_cpufreq->cpuinfo_min_freq,
                p_cpufreq->cpuinfo_max_freq);
@@ -854,7 +858,7 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
 
     printf("scaling_driver       : %s\n", p_cpufreq->scaling_driver);
 
-    if ( !hwp )
+    if ( !is_governor_less )
     {
         if ( p_cpufreq->gov_num )
             printf("scaling_avail_gov    : %s\n",
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index 19aedf6b0b..371deaf678 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -154,7 +154,7 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
     else
         strlcpy(op->u.get_para.scaling_driver, "Unknown", CPUFREQ_NAME_LEN);
 
-    if ( !hwp_active() )
+    if ( !cpufreq_is_governorless(op->cpuid) )
     {
         if ( !(scaling_available_governors =
                xzalloc_array(char, gov_num * CPUFREQ_NAME_LEN)) )
@@ -240,7 +240,7 @@ static int set_cpufreq_para(struct xen_sysctl_pm_op *op)
     if ( !policy || !policy->governor )
         return -EINVAL;
 
-    if ( hwp_active() )
+    if ( cpufreq_is_governorless(op->cpuid) )
         return -EOPNOTSUPP;
 
     switch( op->u.set_para.ctrl_type )
diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h
index 9ef7c4683a..7caeae26cf 100644
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -294,4 +294,16 @@ int acpi_cpufreq_register(void);
 int amd_cppc_cmdline_parse(const char *s, const char *e);
 int amd_cppc_register_driver(void);
 
+/*
+ * Governor-less cpufreq driver indicates the driver doesn't rely on Xen
+ * governor to do performance tuning, mostly it has hardware built-in
+ * algorithm to calculate runtime workload and adjust cores frequency
+ * automatically, like Intel HWP, or CPPC in AMD.
+ */
+static inline bool cpufreq_is_governorless(unsigned int cpuid)
+{
+    return processor_pminfo[cpuid]->init && (hwp_active() ||
+                                             cpufreq_driver.setpolicy);
+}
+
 #endif /* __XEN_CPUFREQ_PM_H__ */
-- 
2.34.1



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From: Penny Zheng 
To: 
CC: , Penny Zheng , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Jan Beulich , "Julien
 Grall" , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?=
	, Stefano Stabellini 
Subject: [PATCH v8 4/8] xen/cpufreq: implement amd-cppc-epp driver for CPPC in active mode
Date: Thu, 28 Aug 2025 18:04:16 +0800
Message-ID: <20250828100416.1776501-1-Penny.Zheng@amd.com>
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amd-cppc has 2 operation modes: autonomous (active) mode and
non-autonomous (passive) mode.
In active mode, we don't need Xen governor to calculate and tune the cpu
frequency, while hardware built-in CPPC power algorithm will calculate the
runtime workload and adjust cores frequency automatically according to the
power supply, thermal, core voltage and some other hardware conditions.
In active mode, CPPC ignores requests done in the desired performance field,
and takes into account only the values set to the minimum performance, maximum
performance, and energy performance preference registers.

A new field EPP (energy performance preference), in CPPC request register, is
introduced. It will be used in the CCLK DPM controller to drive the frequency
that a core is going to operate during short periods of activity, called
minimum active frequency, It could contatin a range of values from 0 to 0xff.
An EPP of zero sets the min active frequency to maximum frequency, while
an EPP of 0xff sets the min active frequency to approxiately Idle frequency.

We implement a new AMD CPU frequency driver `amd-cppc-epp` for active mode.
It requires `active` tag in Xen cmdline for users to explicitly select active
mode.
In driver `active-cppc-epp`, ->setpolicy() is hooked, not the ->target(), as
it does not depend on xen governor to do performance tuning.

We also introduce a new field "policy" (CPUFREQ_POLICY_xxx) to represent
performance policy. Right now, it supports three values:
CPUFREQ_POLICY_PERFORMANCE as maximum performance, CPUFREQ_POLICY_POWERSAVE
as the least power consumption, and CPUFREQ_POLICY_ONDEMAND as no preference,
just corresponding to "performance", "powersave" and "ondemand" Xen governor,
which benefit users from re-using "governor" in Xen cmdline to deliver
which performance policy they want to apply.

Signed-off-by: Penny Zheng 
Acked-by: Jan Beulich 
---
v1 -> v2:
- Remove redundant epp_mode
- Remove pointless initializer
- Define sole caller read_epp_init_once and epp_init value to read
pre-defined BIOS epp value only once
- Combine the commit "xen/cpufreq: introduce policy type when
cpufreq_driver->setpolicy exists"
---
v2 -> v3:
- Combined with commit "x86/cpufreq: add "cpufreq=amd-cppc,active" para"
- Refactor doc about "active mode"
- Change opt_cpufreq_active to opt_active_mode
- Let caller pass epp_init when unspecified to allow the function parameter
to be of uint8_t
- Make epp_init per-cpu value
---
v3 -> v4:
- doc refinement
- use MASK_EXTR() to get epp value
- fix indentation
- replace if-else() with switch()
- combine successive comments and do refinement
- no need to introduce amd_cppc_epp_update_limit() as a wrapper
- rename cpufreq_parse_policy() with cpufreq_policy_from_governor()
- no need to use case-insensitive comparison
---
v4 -> v5:
- refine doc to state what the default is for "active" sub-option and it's of
boolean nature
- excess blank after << for AMD_CPPC_EPP_MASK
- set max_perf with lowest_perf to get utmost powersave
- refine commit message to include description about relation between "policy"
and "governor"
---
v5 -> v6:
- expand comment for "epp" field
- let min_perf set with lowest_nonliner_perf, not lowest_perf, to constrain
  performance tuning in P-states range
- refactor doc and comments
- blank lines between non-fall-through case blocks
- introduce and add entry for "CPUFREQ_POLICY_ONDEMAND"
---
v6 -> v7
- make opt_active_mode __initdata when NDEBUG=y
- add assertion check for must-zero des_perf in active mode
- use the local variable max_perf and min_perf
- read_epp_init() doesn't worth a separate function
---
v7 -> v8:
- use "ASSERT(!opt_active_mode || !des_perf);" to remove #ifndef NDEBUG
- add a new helper amd_cppc_prepare_policy()
---
 docs/misc/xen-command-line.pandoc    |   9 +-
 xen/arch/x86/acpi/cpufreq/amd-cppc.c | 135 ++++++++++++++++++++++++++-
 xen/drivers/cpufreq/utility.c        |  15 +++
 xen/include/acpi/cpufreq/cpufreq.h   |  18 ++++
 xen/include/public/sysctl.h          |   1 +
 5 files changed, 173 insertions(+), 5 deletions(-)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index 3916cc81f6..c029a6e053 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -515,7 +515,7 @@ If set, force use of the performance counters for oprofile, rather than detectin
 available support.
 
 ### cpufreq
-> `= none | {{  | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[verbose]]`
+> `= none | {{  | xen } { [:[powersave|performance|ondemand|userspace][,[]][,[]]] } [,verbose]} | dom0-kernel | hwp[:[][,verbose]] | amd-cppc[:[active][,verbose]]`
 
 > Default: `xen`
 
@@ -537,6 +537,13 @@ choice of `dom0-kernel` is deprecated and not supported by all Dom0 kernels.
 * `amd-cppc` selects ACPI Collaborative Performance and Power Control (CPPC)
   on supported AMD hardware to provide finer grained frequency control
   mechanism. The default is disabled.
+* `active` is a boolean to enable amd-cppc driver in active(autonomous) mode.
+  In this mode, users don't rely on Xen governor to do performance monitoring
+  and tuning. Hardware built-in CPPC power algorithm will calculate the runtime
+  workload and adjust cores frequency automatically according to the power
+  supply, thermal, core voltage and some other hardware conditions.
+  The default is disabled, and the option only applies when `amd-cppc` is
+  enabled.
 
 There is also support for `;`-separated fallback options:
 `cpufreq=hwp;xen,verbose`.  This first tries `hwp` and falls back to `xen` if
diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
index 5b99b86fb7..bb7f4e4a9e 100644
--- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c
+++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
@@ -67,9 +67,14 @@
  * max_perf.
  * Field des_perf conveys performance level Xen governor is requesting. And it
  * may be set to any performance value in the range [min_perf, max_perf],
- * inclusive.
+ * inclusive. In active mode, des_perf must be zero.
  * Field epp represents energy performance preference, which only has meaning
- * when active mode is enabled.
+ * when active mode is enabled. The EPP is used in the CCLK DPM controller
+ * to drive the frequency that a core is going to operate during short periods
+ * of activity, called minimum active frequency, It could contatin a range of
+ * values from 0 to 0xff. An EPP of zero sets the min active frequency to
+ * maximum frequency, while an EPP of 0xff sets the min active frequency to
+ * approxiately Idle frequency.
  */
 struct amd_cppc_drv_data
 {
@@ -106,6 +111,12 @@ static DEFINE_PER_CPU_READ_MOSTLY(struct amd_cppc_drv_data *,
  */
 static DEFINE_PER_CPU_READ_MOSTLY(unsigned int, pxfreq_mhz);
 static DEFINE_PER_CPU_READ_MOSTLY(uint8_t, epp_init);
+#ifndef NDEBUG
+static bool __ro_after_init opt_active_mode;
+#else
+static bool __initdata opt_active_mode;
+#endif
+
 
 static bool __init amd_cppc_handle_option(const char *s, const char *end)
 {
@@ -118,6 +129,13 @@ static bool __init amd_cppc_handle_option(const char *s, const char *end)
         return true;
     }
 
+    ret = parse_boolean("active", s, end);
+    if ( ret >= 0 )
+    {
+        opt_active_mode = ret;
+        return true;
+    }
+
     return false;
 }
 
@@ -270,6 +288,7 @@ static void amd_cppc_write_request(unsigned int cpu, uint8_t min_perf,
 
     data->req.min_perf = min_perf;
     data->req.max_perf = max_perf;
+    ASSERT(!opt_active_mode || !des_perf);
     data->req.des_perf = des_perf;
     data->req.epp = epp;
 
@@ -417,7 +436,7 @@ static int cf_check amd_cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy)
     return 0;
 }
 
-static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
+static int amd_cppc_cpufreq_init_perf(struct cpufreq_policy *policy)
 {
     unsigned int cpu = policy->cpu;
     struct amd_cppc_drv_data *data;
@@ -450,12 +469,103 @@ static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
 
     amd_cppc_boost_init(policy, data);
 
+    return 0;
+}
+
+static int cf_check amd_cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+    int ret;
+
+    ret = amd_cppc_cpufreq_init_perf(policy);
+    if ( ret )
+        return ret;
+
     amd_cppc_verbose(policy->cpu,
                      "CPU initialized with amd-cppc passive mode\n");
 
     return 0;
 }
 
+static int cf_check amd_cppc_epp_cpu_init(struct cpufreq_policy *policy)
+{
+    int ret;
+
+    ret = amd_cppc_cpufreq_init_perf(policy);
+    if ( ret )
+        return ret;
+
+    policy->policy = cpufreq_policy_from_governor(policy->governor);
+
+    amd_cppc_verbose(policy->cpu,
+                     "CPU initialized with amd-cppc active mode\n");
+
+    return 0;
+}
+
+static void amd_cppc_prepare_policy(struct cpufreq_policy *policy,
+                                    uint8_t *max_perf, uint8_t *min_perf,
+                                    uint8_t *epp)
+{
+    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data,
+                                                   policy->cpu);
+
+    /*
+     * On default, set min_perf with lowest_nonlinear_perf, and max_perf
+     * with the highest, to ensure performance scaling in P-states range.
+     */
+    *max_perf = data->caps.highest_perf;
+    *min_perf = data->caps.lowest_nonlinear_perf;
+
+    /*
+     * In policy CPUFREQ_POLICY_PERFORMANCE, increase min_perf to
+     * highest_perf to achieve ultmost performance.
+     * In policy CPUFREQ_POLICY_POWERSAVE, decrease max_perf to
+     * lowest_nonlinear_perf to achieve ultmost power saving.
+     * Set governor only to help print proper policy info to users.
+     */
+    switch ( policy->policy )
+    {
+    case CPUFREQ_POLICY_PERFORMANCE:
+        /* Force the epp value to be zero for performance policy */
+        *epp = CPPC_ENERGY_PERF_MAX_PERFORMANCE;
+        *min_perf = *max_perf;
+        policy->governor = &cpufreq_gov_performance;
+        break;
+
+    case CPUFREQ_POLICY_POWERSAVE:
+        /* Force the epp value to be 0xff for powersave policy */
+        *epp = CPPC_ENERGY_PERF_MAX_POWERSAVE;
+        *max_perf = *min_perf;
+        policy->governor = &cpufreq_gov_powersave;
+        break;
+
+    case CPUFREQ_POLICY_ONDEMAND:
+        /*
+         * Set epp with medium value to show no preference over performance
+         * or powersave
+         */
+        *epp = CPPC_ENERGY_PERF_BALANCE;
+        policy->governor = &cpufreq_gov_dbs;
+        break;
+
+    default:
+        *epp = per_cpu(epp_init, policy->cpu);
+        break;
+    }
+}
+
+static int cf_check amd_cppc_epp_set_policy(struct cpufreq_policy *policy)
+{
+    uint8_t max_perf, min_perf, epp;
+
+    amd_cppc_prepare_policy(policy, &max_perf, &min_perf, &epp);
+
+    amd_cppc_write_request(policy->cpu, min_perf,
+                           0 /* no des_perf in active mode */,
+                           max_perf, epp);
+    return 0;
+}
+
 static const struct cpufreq_driver __initconst_cf_clobber
 amd_cppc_cpufreq_driver =
 {
@@ -466,10 +576,27 @@ amd_cppc_cpufreq_driver =
     .exit   = amd_cppc_cpufreq_cpu_exit,
 };
 
+static const struct cpufreq_driver __initconst_cf_clobber
+amd_cppc_epp_driver =
+{
+    .name       = XEN_AMD_CPPC_EPP_DRIVER_NAME,
+    .verify     = amd_cppc_cpufreq_verify,
+    .setpolicy  = amd_cppc_epp_set_policy,
+    .init       = amd_cppc_epp_cpu_init,
+    .exit       = amd_cppc_cpufreq_cpu_exit,
+};
+
 int __init amd_cppc_register_driver(void)
 {
+    int ret;
+
     if ( !cpu_has_cppc )
         return -ENODEV;
 
-    return cpufreq_register_driver(&amd_cppc_cpufreq_driver);
+    if ( opt_active_mode )
+        ret = cpufreq_register_driver(&amd_cppc_epp_driver);
+    else
+        ret = cpufreq_register_driver(&amd_cppc_cpufreq_driver);
+
+    return ret;
 }
diff --git a/xen/drivers/cpufreq/utility.c b/xen/drivers/cpufreq/utility.c
index 987c3b5929..e2cc9ff2af 100644
--- a/xen/drivers/cpufreq/utility.c
+++ b/xen/drivers/cpufreq/utility.c
@@ -250,6 +250,7 @@ int __cpufreq_set_policy(struct cpufreq_policy *data,
     data->min = policy->min;
     data->max = policy->max;
     data->limits = policy->limits;
+    data->policy = policy->policy;
     if (cpufreq_driver.setpolicy)
         return alternative_call(cpufreq_driver.setpolicy, data);
 
@@ -281,3 +282,17 @@ int __cpufreq_set_policy(struct cpufreq_policy *data,
 
     return __cpufreq_governor(data, CPUFREQ_GOV_LIMITS);
 }
+
+unsigned int cpufreq_policy_from_governor(const struct cpufreq_governor *gov)
+{
+    if ( !strncmp(gov->name, "performance", CPUFREQ_NAME_LEN) )
+        return CPUFREQ_POLICY_PERFORMANCE;
+
+    if ( !strncmp(gov->name, "powersave", CPUFREQ_NAME_LEN) )
+        return CPUFREQ_POLICY_POWERSAVE;
+
+    if ( !strncmp(gov->name, "ondemand", CPUFREQ_NAME_LEN) )
+        return CPUFREQ_POLICY_ONDEMAND;
+
+    return CPUFREQ_POLICY_UNKNOWN;
+}
diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h
index 5d4881eea8..9ef7c4683a 100644
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -81,6 +81,7 @@ struct cpufreq_policy {
     int8_t              turbo;  /* tristate flag: 0 for unsupported
                                  * -1 for disable, 1 for enabled
                                  * See CPUFREQ_TURBO_* below for defines */
+    unsigned int        policy; /* CPUFREQ_POLICY_* */
 };
 DECLARE_PER_CPU(struct cpufreq_policy *, cpufreq_cpu_policy);
 
@@ -131,6 +132,23 @@ extern int cpufreq_register_governor(struct cpufreq_governor *governor);
 extern struct cpufreq_governor *__find_governor(const char *governor);
 #define CPUFREQ_DEFAULT_GOVERNOR &cpufreq_gov_dbs
 
+/*
+ * Performance Policy
+ * If cpufreq_driver->target() exists, the ->governor decides what frequency
+ * within the limits is used. If cpufreq_driver->setpolicy() exists, these
+ * following policies are available:
+ * CPUFREQ_POLICY_PERFORMANCE represents maximum performance
+ * CPUFREQ_POLICY_POWERSAVE represents least power consumption
+ * CPUFREQ_POLICY_ONDEMAND represents no preference over performance or
+ * powersave
+ */
+#define CPUFREQ_POLICY_UNKNOWN      0
+#define CPUFREQ_POLICY_POWERSAVE    1
+#define CPUFREQ_POLICY_PERFORMANCE  2
+#define CPUFREQ_POLICY_ONDEMAND     3
+
+unsigned int cpufreq_policy_from_governor(const struct cpufreq_governor *gov);
+
 /* pass a target to the cpufreq driver */
 extern int __cpufreq_driver_target(struct cpufreq_policy *policy,
                                    unsigned int target_freq,
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index aa29a5401c..eb3a23b038 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -454,6 +454,7 @@ struct xen_set_cppc_para {
 };
 
 #define XEN_AMD_CPPC_DRIVER_NAME "amd-cppc"
+#define XEN_AMD_CPPC_EPP_DRIVER_NAME "amd-cppc-epp"
 #define XEN_HWP_DRIVER_NAME "hwp"
 
 /*
-- 
2.34.1



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Subject: [PATCH v8 8/8] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC xen_sysctl_pm_op for amd-cppc driver
Date: Thu, 28 Aug 2025 18:06:01 +0800
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Introduce helper set_amd_cppc_para() and get_amd_cppc_para() to
SET/GET CPPC-related para for amd-cppc/amd-cppc-epp driver.

In get_cpufreq_cppc()/set_cpufreq_cppc(), we include
"processor_pminfo[cpuid]->init & XEN_CPPC_INIT" condition check to deal with
cpufreq driver in amd-cppc.
We also borrow governor field to indicate policy info for CPPC active mode.

Signed-off-by: Penny Zheng 
Acked-by: Anthony PERARD 
---
v1 -> v2:
- Give the variable des_perf an initializer of 0
- Use the strncmp()s directly in the if()
---
v3 -> v4
- refactor comments
- remove double blank lines
- replace amd_cppc_in_use flag with XEN_PROCESSOR_PM_CPPC
---
v4 -> v5:
- add new field "policy" in "struct xen_cppc_para"
- add new performamce policy XEN_CPUFREQ_POLICY_BALANCE
- drop string comparisons with "processor_pminfo[cpuid]->init & XEN_CPPC_INIT"
and "cpufreq.setpolicy == NULL"
- Blank line ahead of the main "return" of a function
- refactor comments, commit message and title
---
v5 -> v6:
- remove duplicated manifest constants, and just move it to public header
- use "else if" to avoid confusion that it looks as if both paths could be taken
- add check for legitimate perf values
- use "unknown" instead of "none"
- introduce "CPUFREQ_POLICY_END" for array overrun check in user space tools
---
v6 -> v7:
- use ARRAY_SIZE() instead
- ->policy print is avoided in passive mode and print "unknown" in invalid
cases
- let cpufreq_is_governorless() being the variable's initializer
- refactor with the conditional operator to increase readability
- move duplicated defination ahead and use local variable
- avoid using "else-condition" to bring "dead code" in Misra's nomeclature
- move the comment out of public header and into the respective internal
struct field
- wrap set{,get}_amd_cppc_para() with CONFIG_PM_OP
- add symmetry scenario for maximum check
---
v7 -> v8:
- change function name to amd_cppc_get{,set}_para()
- fix too deep indentation, and indent according to pending open parentheses
- missing -EINVAL when no flag is set at all
- use new helper amd_cppc_prepare_policy() to reduce redundancy
- borrow governor field to indicate policy info
---
 tools/misc/xenpm.c                   |  13 ++-
 xen/arch/x86/acpi/cpufreq/amd-cppc.c | 164 +++++++++++++++++++++++++++
 xen/drivers/acpi/pm-op.c             |  28 +++--
 xen/include/acpi/cpufreq/cpufreq.h   |   4 +
 4 files changed, 196 insertions(+), 13 deletions(-)

diff --git a/tools/misc/xenpm.c b/tools/misc/xenpm.c
index 893a0afe11..bda9c62aa0 100644
--- a/tools/misc/xenpm.c
+++ b/tools/misc/xenpm.c
@@ -832,11 +832,14 @@ static void print_cppc_para(unsigned int cpuid,
 /* print out parameters about cpu frequency */
 static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
 {
-    bool is_governor_less = false;
+    bool is_governor_less = false, is_cppc_active = false;
     int i;
 
-    if ( !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) ||
-         !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) )
+    if ( !strcmp(p_cpufreq->scaling_driver, XEN_AMD_CPPC_EPP_DRIVER_NAME) )
+        is_cppc_active = true;
+
+    if ( is_cppc_active ||
+         !strcmp(p_cpufreq->scaling_driver, XEN_HWP_DRIVER_NAME) )
         is_governor_less = true;
 
     printf("cpu id               : %d\n", cpuid);
@@ -899,6 +902,10 @@ static void print_cpufreq_para(int cpuid, struct xc_get_cpufreq_para *p_cpufreq)
                p_cpufreq->u.s.scaling_cur_freq);
     }
 
+    /* Translate governor info to policy info in CPPC active mode */
+    if ( is_cppc_active )
+        printf("policy               : %s\n", p_cpufreq->u.s.scaling_governor);
+
     printf("turbo mode           : %s\n",
            p_cpufreq->turbo_enabled ? "enabled" : "disabled or n/a");
     printf("\n");
diff --git a/xen/arch/x86/acpi/cpufreq/amd-cppc.c b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
index bb7f4e4a9e..eca455240f 100644
--- a/xen/arch/x86/acpi/cpufreq/amd-cppc.c
+++ b/xen/arch/x86/acpi/cpufreq/amd-cppc.c
@@ -566,6 +566,170 @@ static int cf_check amd_cppc_epp_set_policy(struct cpufreq_policy *policy)
     return 0;
 }
 
+#ifdef CONFIG_PM_OP
+int amd_cppc_get_para(const struct cpufreq_policy *policy,
+                      struct xen_get_cppc_para *cppc_para)
+{
+    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data,
+                                                   policy->cpu);
+
+    if ( data == NULL )
+        return -ENODATA;
+
+    cppc_para->lowest           = data->caps.lowest_perf;
+    cppc_para->lowest_nonlinear = data->caps.lowest_nonlinear_perf;
+    cppc_para->nominal          = data->caps.nominal_perf;
+    cppc_para->highest          = data->caps.highest_perf;
+    cppc_para->minimum          = data->req.min_perf;
+    cppc_para->maximum          = data->req.max_perf;
+    cppc_para->desired          = data->req.des_perf;
+    cppc_para->energy_perf      = data->req.epp;
+
+    return 0;
+}
+
+int amd_cppc_set_para(struct cpufreq_policy *policy,
+                      const struct xen_set_cppc_para *set_cppc)
+{
+    unsigned int cpu = policy->cpu;
+    struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);
+    uint8_t max_perf, min_perf, des_perf, epp;
+    bool active_mode = cpufreq_is_governorless(cpu);
+
+    if ( data == NULL )
+        return -ENOENT;
+
+    /* Only allow values if params bit is set. */
+    if ( (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED) &&
+          set_cppc->desired) ||
+         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) &&
+          set_cppc->minimum) ||
+         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
+          set_cppc->maximum) ||
+         (!(set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF) &&
+          set_cppc->energy_perf) )
+        return -EINVAL;
+
+    /* Return if there is nothing to do. */
+    if ( set_cppc->set_params == 0 )
+        return 0;
+
+    /*
+     * Validate all parameters
+     * Maximum performance may be set to any performance value in the range
+     * [Nonlinear Lowest Performance, Highest Performance], inclusive but must
+     * be set to a value that is larger than or equal to minimum Performance.
+     */
+    if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM) &&
+         (set_cppc->maximum > data->caps.highest_perf ||
+          (set_cppc->maximum <
+           (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM
+            ? set_cppc->minimum
+            : data->req.min_perf))) )
+        return -EINVAL;
+    /*
+     * Minimum performance may be set to any performance value in the range
+     * [Nonlinear Lowest Performance, Highest Performance], inclusive but must
+     * be set to a value that is less than or equal to Maximum Performance.
+     */
+    if ( (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM) &&
+         (set_cppc->minimum < data->caps.lowest_nonlinear_perf ||
+          (set_cppc->minimum >
+           (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM
+            ? set_cppc->maximum
+            : data->req.max_perf))) )
+        return -EINVAL;
+    /*
+     * Desired performance may be set to any performance value in the range
+     * [Minimum Performance, Maximum Performance], inclusive.
+     */
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED )
+    {
+        if ( active_mode )
+            return -EOPNOTSUPP;
+
+        if ( (set_cppc->desired >
+              (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM
+               ? set_cppc->maximum
+               : data->req.max_perf)) ||
+             (set_cppc->desired <
+              (set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM
+               ? set_cppc->minimum
+               : data->req.min_perf)) )
+            return -EINVAL;
+    }
+    /*
+     * Energy Performance Preference may be set with a range of values
+     * from 0 to 0xFF
+     */
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF )
+    {
+        if ( !active_mode )
+            return -EOPNOTSUPP;
+
+        if ( set_cppc->energy_perf > UINT8_MAX )
+            return -EINVAL;
+    }
+
+    /* Activity window not supported in MSR */
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ACT_WINDOW )
+        return -EOPNOTSUPP;
+
+    des_perf = data->req.des_perf;
+    /*
+     * Apply presets:
+     * XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE/PERFORMANCE/ONDEMAND are
+     * only available when CPPC in active mode
+     */
+    switch ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_PRESET_MASK )
+    {
+    case XEN_SYSCTL_CPPC_SET_PRESET_POWERSAVE:
+        if ( !active_mode )
+            return -EINVAL;
+        policy->policy = CPUFREQ_POLICY_POWERSAVE;
+        break;
+
+    case XEN_SYSCTL_CPPC_SET_PRESET_PERFORMANCE:
+        if ( !active_mode )
+            return -EINVAL;
+        policy->policy = CPUFREQ_POLICY_PERFORMANCE;
+        break;
+
+    case XEN_SYSCTL_CPPC_SET_PRESET_ONDEMAND:
+        if ( !active_mode )
+            return -EINVAL;
+        policy->policy = CPUFREQ_POLICY_ONDEMAND;
+        break;
+
+    case XEN_SYSCTL_CPPC_SET_PRESET_NONE:
+        if ( active_mode )
+            policy->policy = CPUFREQ_POLICY_UNKNOWN;
+        break;
+
+    default:
+        return -EINVAL;
+    }
+    amd_cppc_prepare_policy(policy, &max_perf, &min_perf, &epp);
+
+    /* Further customize presets if needed */
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MINIMUM )
+        min_perf = set_cppc->minimum;
+
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_MAXIMUM )
+        max_perf = set_cppc->maximum;
+
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_ENERGY_PERF )
+        epp = set_cppc->energy_perf;
+
+    if ( set_cppc->set_params & XEN_SYSCTL_CPPC_SET_DESIRED )
+        des_perf = set_cppc->desired;
+
+    amd_cppc_write_request(cpu, min_perf, des_perf, max_perf, epp);
+
+    return 0;
+}
+#endif /* CONFIG_PM_OP */
+
 static const struct cpufreq_driver __initconst_cf_clobber
 amd_cppc_cpufreq_driver =
 {
diff --git a/xen/drivers/acpi/pm-op.c b/xen/drivers/acpi/pm-op.c
index 371deaf678..bcb3b9b2a7 100644
--- a/xen/drivers/acpi/pm-op.c
+++ b/xen/drivers/acpi/pm-op.c
@@ -84,6 +84,8 @@ static int get_cpufreq_cppc(unsigned int cpu,
 
     if ( hwp_active() )
         ret = get_hwp_para(cpu, cppc_para);
+    else if ( processor_pminfo[cpu]->init & XEN_CPPC_INIT )
+        ret = amd_cppc_get_para(per_cpu(cpufreq_cpu_policy, cpu), cppc_para);
 
     return ret;
 }
@@ -154,6 +156,17 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
     else
         strlcpy(op->u.get_para.scaling_driver, "Unknown", CPUFREQ_NAME_LEN);
 
+    /*
+     * In CPPC active mode, we are borrowing governor field to indicate
+     * policy info.
+     */
+    if ( policy->governor->name[0] )
+        strlcpy(op->u.get_para.u.s.scaling_governor,
+                policy->governor->name, CPUFREQ_NAME_LEN);
+    else
+        strlcpy(op->u.get_para.u.s.scaling_governor, "Unknown",
+                CPUFREQ_NAME_LEN);
+
     if ( !cpufreq_is_governorless(op->cpuid) )
     {
         if ( !(scaling_available_governors =
@@ -178,13 +191,6 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
         op->u.get_para.u.s.scaling_max_freq = policy->max;
         op->u.get_para.u.s.scaling_min_freq = policy->min;
 
-        if ( policy->governor->name[0] )
-            strlcpy(op->u.get_para.u.s.scaling_governor,
-                    policy->governor->name, CPUFREQ_NAME_LEN);
-        else
-            strlcpy(op->u.get_para.u.s.scaling_governor, "Unknown",
-                    CPUFREQ_NAME_LEN);
-
         /* governor specific para */
         if ( !strncasecmp(op->u.get_para.u.s.scaling_governor,
                           "userspace", CPUFREQ_NAME_LEN) )
@@ -321,10 +327,12 @@ static int set_cpufreq_cppc(struct xen_sysctl_pm_op *op)
     if ( !policy || !policy->governor )
         return -ENOENT;
 
-    if ( !hwp_active() )
-        return -EOPNOTSUPP;
+    if ( hwp_active() )
+        return set_hwp_para(policy, &op->u.set_cppc);
+    if ( processor_pminfo[op->cpuid]->init & XEN_CPPC_INIT )
+        return amd_cppc_set_para(policy, &op->u.set_cppc);
 
-    return set_hwp_para(policy, &op->u.set_cppc);
+    return -EOPNOTSUPP;
 }
 
 int do_pm_op(struct xen_sysctl_pm_op *op)
diff --git a/xen/include/acpi/cpufreq/cpufreq.h b/xen/include/acpi/cpufreq/cpufreq.h
index 7caeae26cf..e8b4e955a2 100644
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -293,6 +293,10 @@ int acpi_cpufreq_register(void);
 
 int amd_cppc_cmdline_parse(const char *s, const char *e);
 int amd_cppc_register_driver(void);
+int amd_cppc_get_para(const struct cpufreq_policy *policy,
+                      struct xen_get_cppc_para *cppc_para);
+int amd_cppc_set_para(struct cpufreq_policy *policy,
+                      const struct xen_set_cppc_para *set_cppc);
 
 /*
  * Governor-less cpufreq driver indicates the driver doesn't rely on Xen
-- 
2.34.1



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Subject: Re: MCA hypercall with PVH
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Cc: Xen-devel ,
 Jason Andryuk 
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On 28.08.2025 11:50, Roger Pau Monné wrote:
> On Thu, Aug 28, 2025 at 10:48:49AM +0200, Jan Beulich wrote:
>> On 28.08.2025 03:22, Jason Andryuk wrote:
>>> The MCA hypercall, do_mca(), is only available for PV.  That is, it's 
>>> only added to the hypercall table for PV.  Is there a particular reason 
>>> it was omitted from PVH, or did PVH dom0 just not exist?
>>
>> PVH Dom0 didn't exist back at the time, yes, but it's more than this. The
>> hypercall, in some places, deals with MFNs, which aren't "visible" to PVH
>> Dom0. IOW enabling it (perhaps just partly) would need to be done with
>> extra care.
> 
> I think there's also a question of whether we want to use a PV
> interface here, or try for Xen to mediate between the hardware domain
> and the native interface, possibly exposing some kind of partially
> emulated view that matches the native interface, and thus avoids
> having to use a PV driver in the hardware domain.
> 
> I've opened a GitLab ticket long ago about MCE:
> 
> https://gitlab.com/xen-project/xen/-/issues/101
> 
> But didn't look into it.  I think we need some prior investigation to
> figure out whether it would be feasible to expose a native MCA
> interface to the hardware domain, as that would be the preference for
> PVH (rather than re-using the classic PV interfaces).
> 
> The main barrier here is the disassociation between the hardware
> domain physical memory map versus the host one, as the MCE/MCA
> drivers will need to operate based on the host memory map, not the
> one used by the hardware domain.

Right. Obtaining the host memory map alone already requires some level
of PV-ness. Associating memory addresses (necessarily surfaced as MFNs,
as not all MFNs have an associated GFN in Dom0) back to Dom0's own
memory would further require exposure of the M2P. That's getting pretty
heavily PV already, imo. And we haven't arrived at DomU-owned pages,
yet.

Jan

> I think (some?) of the MSRs also contain CPU specific status/errors,
> and hence using a native interface would require the hardware domain
> vCPU count to be equal to the host pCPU count.
> 
> Nit: I've just taken a quick look at do_mca() but it looked like the
> sharing of the data would be better done using acquire_resource if
> possible, as to avoid repeated hypercalls.
> 
> Thanks, Roger.



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Message-ID: <8e126855-ed0b-4046-a018-8fca6d20db49@citrix.com>
Date: Thu, 28 Aug 2025 11:22:35 +0100
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Subject: Re: [PATCH] hvmloader: Update to SMBIOS 2.6
To: Teddy Astie , xen-devel@lists.xenproject.org
Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Anthony PERARD 
References: 
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In-Reply-To: <74665857-3f0b-43e6-b31f-d498d9e7fdc3@vates.tech>
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On 27/08/2025 9:27 pm, Teddy Astie wrote:
> Le 27/08/2025 à 19:49, Andrew Cooper a écrit :
>> On 22/08/2025 2:47 pm, Teddy Astie wrote:
>>> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
>>> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
>>>
>>> In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
>>> (undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
>>> you have a endian mismatch causing the UUIDs to mismatch in the guest.
>>>
>>> $ cat /sys/hypervisor/uuid
>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>> $ cat /sys/devices/virtual/dmi/id/product_uuid
>>> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
>>> $ cat /sys/devices/virtual/dmi/id/product_serial
>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>>
>>> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
>>> written in the table; which effectively fix this endianness mismatch with
>>> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.
>>>
>>> Signed-off-by: Teddy Astie 
>>> ---
>>> This effectively changes the UUID seen with UEFI guests as it was
>>> actually inconsistent with SeaBIOS and SMBIOS expectations.
>>> ---
>> I agree this is a real bug and needs fixing.  However, ...
>>
>>
>>>   tools/firmware/hvmloader/smbios.c | 20 ++++++++++++++++++--
>>>   1 file changed, 18 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/tools/firmware/hvmloader/smbios.c b/tools/firmware/hvmloader/smbios.c
>>> index 6bcdcc233a..f4822ae6f8 100644
>>> --- a/tools/firmware/hvmloader/smbios.c
>>> +++ b/tools/firmware/hvmloader/smbios.c
>>> @@ -352,7 +352,7 @@ smbios_entry_point_init(void *start,
>>>       memcpy(ep->anchor_string, "_SM_", 4);
>>>       ep->length = 0x1f;
>>>       ep->smbios_major_version = 2;
>>> -    ep->smbios_minor_version = 4;
>>> +    ep->smbios_minor_version = 6;
>>>       ep->max_structure_size = max_structure_size;
>>>       ep->entry_point_revision = 0;
>>>       memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
>>> @@ -462,7 +462,23 @@ smbios_type_1_init(void *start, const char *xen_version,
>>>       p->version_str = 3;
>>>       p->serial_number_str = 4;
>>>   
>>> -    memcpy(p->uuid, uuid, 16);
>>> +    /*
>>> +     * Xen uses OSF DCE UUIDs which is fully big endian, however,
>>> +     * GUIDs (which requirement is clarified by SMBIOS >= 2.6) has the
>>> +     * first 3 components appearing as being little endian and the rest
>>> +     * as still being big endian.
>> ... this is not an accurate statement.
>>
>> Xen specifically tries to treat a xen_domain_handle_t as an opaque blob.
>>
>> The only two areas I can see ascribing any structure are the 'q'
>> debugkey (not exactly a strong ABI statement), and the arinc635
>> scheduler whose use is buggy (uuids are not unique in Xen; it's the
>> domid which is).
>>
>> It is an error that a format isn't stated, but the format comes from the
>> toolstack.  We'd better hope that all toolstacks use OSF DCE UUIDs, or
>> this is going to badly wrong.
>>
> I agree in principle. maybe OSF DCE UUID is not the proper definition 
> (even though it implies the same) but I should rather use RFC 9562 UUIDs 
> but refering to the string representation rather than the UUID meaning 
> itself.
>
> The RFC 9562 defines the UUID as being sequenced as big endian and 
> string represented as > UUID     = 4hexOctet "-"
>>            2hexOctet "-"
>>            2hexOctet "-"
>>            2hexOctet "-"
>>            6hexOctet
>> hexOctet = HEXDIG HEXDIG
>> DIGIT    = %x30-39
>> HEXDIG   = DIGIT / "A" / "B" / "C" / "D" / "E" / "F"
> This matches the UUID encoding provided by XEN_DEFINE_UUID and is used 
> by libxl, libvirt and XAPI and considered by Linux when reading the 
> UUID. However, it may always not be a "valid" UUID strictly speaking but 
> it doesn't really matter since we only care about its binary/string 
> representation.
>
>> And on that note, the toolstacks are not the same.  Xapi for example
>> uses reads 16 bytes out of /dev/urandom.
>>
>> Whatever we end up doing, the fix must include a change to
>> xen/include/public/version.h stating the format of the UUID.
>>
> Something like
>
> diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
> index 04fc891353..3241e8dd2b 100644
> --- a/xen/include/public/xen.h
> +++ b/xen/include/public/xen.h
> @@ -975,6 +975,10 @@ typedef struct dom0_vga_console_info {
>   #define xen_vga_console_info dom0_vga_console_info
>   #define xen_vga_console_info_t dom0_vga_console_info_t
>
> +/*
> + * The guest handled provided by toolstack encoded as a UUID in
> + * big-endian order. Its string representation follows RFC 9562.
> + */
>   typedef uint8_t xen_domain_handle_t[16];
>
>   __DEFINE_XEN_GUEST_HANDLE(uint8,  uint8_t);
>
> ?
>
> So that we're converting between big-endian encoded UUID (RFC 9562) and 
> Microsoft GUID (which doesn't care about its content but only about its 
> endianness regarding formatting).

I'd be tempted to be rather more explicit.

diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
index 82b9c05a76b7..f1592dc059e2 100644
--- a/xen/include/public/xen.h
+++ b/xen/include/public/xen.h
@@ -973,6 +973,13 @@ typedef struct dom0_vga_console_info {
 #define xen_vga_console_info dom0_vga_console_info
 #define xen_vga_console_info_t dom0_vga_console_info_t
 
+/*
+ * The domain handle is chosen by the toolstack, and intended to hold a UUID
+ * conforming to RFC 9562 (i.e. big endian).
+ *
+ * Certain cases (e.g. SMBios) transform it to a Microsoft GUID (little
+ * endian) for presentation to the guest.
+ */
 typedef uint8_t xen_domain_handle_t[16];
 
 __DEFINE_XEN_GUEST_HANDLE(uint8,  uint8_t);


~Andrew


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Date: Thu, 28 Aug 2025 12:22:49 +0200
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Subject: Re: [PATCH] hvmloader: Update to SMBIOS 2.6
To: Andrew Cooper ,
 Teddy Astie 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD , xen-devel@lists.xenproject.org
References: 
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On 28.08.2025 12:01, Andrew Cooper wrote:
> On 28/08/2025 8:07 am, Jan Beulich wrote:
>> On 27.08.2025 19:47, Andrew Cooper wrote:
>>> On 22/08/2025 2:47 pm, Teddy Astie wrote:
>>>> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
>>>> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
>>>>
>>>> In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
>>>> (undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
>>>> you have a endian mismatch causing the UUIDs to mismatch in the guest.
>>>>
>>>> $ cat /sys/hypervisor/uuid
>>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>>> $ cat /sys/devices/virtual/dmi/id/product_uuid
>>>> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
>>>> $ cat /sys/devices/virtual/dmi/id/product_serial
>>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>>>
>>>> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
>>>> written in the table; which effectively fix this endianness mismatch with
>>>> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.
>>>>
>>>> Signed-off-by: Teddy Astie 
>>>> ---
>>>> This effectively changes the UUID seen with UEFI guests as it was
>>>> actually inconsistent with SeaBIOS and SMBIOS expectations.
>>>> ---
>>> I agree this is a real bug and needs fixing.
>> Hmm, I didn't realize this is a bug, and hence put the patch off as 4.22
>> material. If there is a bug being fixed: Teddy, please add a Fixes: tag.
> 
> I'm not sure if this has a reasonable Fixes tag.
> 
> It's a combination of an ill-specified domain handle format, and using
> an ill-specified version of the SMBios spec.

But the problem was still introduced into the code base at some point. Afaict
in c683914ef913 ("Add code to generate SMBIOS tables to hvmloader"), i.e. when
smbios.c was first added.

Jan


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Subject: Re: [PATCH v8 0/8] amd-cppc CPU Performance Scaling Driver
To: Penny Zheng 
Cc: ray.huang@amd.com, Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , Juergen Gross
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On 28.08.2025 12:02, Penny Zheng wrote:
> amd-cppc is the AMD CPU performance scaling driver that introduces a
> new CPU frequency control mechanism on modern AMD APU and CPU series in
> Xen. The new mechanism is based on Collaborative Processor Performance
> Control (CPPC) which provides finer grain frequency management than
> legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using
> the ACPI P-states driver to manage CPU frequency and clocks with
> switching only in 3 P-states. CPPC replaces the ACPI P-states controls
> and allows a flexible, low-latency interface for Xen to directly
> communicate the performance hints to hardware.
> 
> amd_cppc driver has 2 operation modes: autonomous (active) mode,
> and non-autonomous (passive) mode. We register different CPUFreq driver
> for different modes, "amd-cppc" for passive mode and "amd-cppc-epp"
> for active mode.
> 
> The passive mode leverages common governors such as *ondemand*,
> *performance*, etc, to manage the performance tuning. While the active mode
> uses epp to provides a hint to the hardware if software wants to bias
> toward performance (0x0) or energy efficiency (0xff). CPPC power algorithm
> in hardware will automatically calculate the runtime workload and adjust the
> realtime cpu cores frequency according to the power supply and thermal, core
> voltage and some other hardware conditions.
> 
> amd-cppc is enabled on passive mode with a top-level `cpufreq=amd-cppc` option,
> while users add extra `active` flag to select active mode.
> 
> With `cpufreq=amd-cppc,active`, we did a 60s sampling test to see the CPU
> frequency change, through tweaking the energy_perf preference from
> `xenpm set-cpufreq-cppc powersave` to `xenpm set-cpufreq-cppc performance`.
> The outputs are as follows:
> ```
> Setting CPU in powersave mode
> Sampling and Outputs:
>   Avg freq      580000 KHz
>   Avg freq      580000 KHz
>   Avg freq      580000 KHz
> Setting CPU in performance mode
> Sampling and Outputs:
>   Avg freq      4640000 KHz
>   Avg freq      4220000 KHz
>   Avg freq      4640000 KHz
> ```
> 
> Penny Zheng (8):
>   xen/cpufreq: introduce new sub-hypercall to propagate CPPC data
>   xen/cpufreq: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc
>     driver
>   xen/cpufreq: implement amd-cppc driver for CPPC in passive mode
>   xen/cpufreq: implement amd-cppc-epp driver for CPPC in active mode
>   xen/cpufreq: get performance policy from governor set via xenpm
>   tools/cpufreq: extract CPPC para from cpufreq para
>   xen/cpufreq: bypass governor-related para for amd-cppc-epp
>   xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC xen_sysctl_pm_op for amd-cppc
>     driver

I'm somewhat confused by the submission: Both my mailbox and
https://lists.xen.org/archives/html/xen-devel/2025-08/threads.html agree that
cover letter and patch 1 were submitted twice, while patches 4 through 8 came
through un-threaded. I can only assume that the duplicates are identical.

Jan


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Date: Thu, 28 Aug 2025 11:31:01 +0100
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Subject: Re: [PATCH] hvmloader: Update to SMBIOS 2.6
To: Jan Beulich , Teddy Astie 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD , xen-devel@lists.xenproject.org
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On 28/08/2025 11:22 am, Jan Beulich wrote:
> On 28.08.2025 12:01, Andrew Cooper wrote:
>> On 28/08/2025 8:07 am, Jan Beulich wrote:
>>> On 27.08.2025 19:47, Andrew Cooper wrote:
>>>> On 22/08/2025 2:47 pm, Teddy Astie wrote:
>>>>> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
>>>>> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
>>>>>
>>>>> In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
>>>>> (undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
>>>>> you have a endian mismatch causing the UUIDs to mismatch in the guest.
>>>>>
>>>>> $ cat /sys/hypervisor/uuid
>>>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>>>> $ cat /sys/devices/virtual/dmi/id/product_uuid
>>>>> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
>>>>> $ cat /sys/devices/virtual/dmi/id/product_serial
>>>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>>>>
>>>>> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
>>>>> written in the table; which effectively fix this endianness mismatch with
>>>>> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.
>>>>>
>>>>> Signed-off-by: Teddy Astie 
>>>>> ---
>>>>> This effectively changes the UUID seen with UEFI guests as it was
>>>>> actually inconsistent with SeaBIOS and SMBIOS expectations.
>>>>> ---
>>>> I agree this is a real bug and needs fixing.
>>> Hmm, I didn't realize this is a bug, and hence put the patch off as 4.22
>>> material. If there is a bug being fixed: Teddy, please add a Fixes: tag.
>> I'm not sure if this has a reasonable Fixes tag.
>>
>> It's a combination of an ill-specified domain handle format, and using
>> an ill-specified version of the SMBios spec.
> But the problem was still introduced into the code base at some point. Afaict
> in c683914ef913 ("Add code to generate SMBIOS tables to hvmloader"), i.e. when
> smbios.c was first added.

The thing that changed was the SMBios spec, in version 2.6.  It went
from having an ill-defined statement of what a UUID was (and for which
Xen's code was a valid interpretation), to stating a MSFT GUID format.

~Andrew


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Date: Thu, 28 Aug 2025 12:37:34 +0200
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Subject: Re: [PATCH] hvmloader: Update to SMBIOS 2.6
To: Andrew Cooper ,
 Teddy Astie 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD , xen-devel@lists.xenproject.org
References: 
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On 28.08.2025 12:31, Andrew Cooper wrote:
> On 28/08/2025 11:22 am, Jan Beulich wrote:
>> On 28.08.2025 12:01, Andrew Cooper wrote:
>>> On 28/08/2025 8:07 am, Jan Beulich wrote:
>>>> On 27.08.2025 19:47, Andrew Cooper wrote:
>>>>> On 22/08/2025 2:47 pm, Teddy Astie wrote:
>>>>>> Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
>>>>>> SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).
>>>>>>
>>>>>> In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
>>>>>> (undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
>>>>>> you have a endian mismatch causing the UUIDs to mismatch in the guest.
>>>>>>
>>>>>> $ cat /sys/hypervisor/uuid
>>>>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>>>>> $ cat /sys/devices/virtual/dmi/id/product_uuid
>>>>>> 3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
>>>>>> $ cat /sys/devices/virtual/dmi/id/product_serial
>>>>>> e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
>>>>>>
>>>>>> This patch updates the SMBIOS version from 2.4 to 2.6 and fixup the UUID
>>>>>> written in the table; which effectively fix this endianness mismatch with
>>>>>> OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.
>>>>>>
>>>>>> Signed-off-by: Teddy Astie 
>>>>>> ---
>>>>>> This effectively changes the UUID seen with UEFI guests as it was
>>>>>> actually inconsistent with SeaBIOS and SMBIOS expectations.
>>>>>> ---
>>>>> I agree this is a real bug and needs fixing.
>>>> Hmm, I didn't realize this is a bug, and hence put the patch off as 4.22
>>>> material. If there is a bug being fixed: Teddy, please add a Fixes: tag.
>>> I'm not sure if this has a reasonable Fixes tag.
>>>
>>> It's a combination of an ill-specified domain handle format, and using
>>> an ill-specified version of the SMBios spec.
>> But the problem was still introduced into the code base at some point. Afaict
>> in c683914ef913 ("Add code to generate SMBIOS tables to hvmloader"), i.e. when
>> smbios.c was first added.
> 
> The thing that changed was the SMBios spec, in version 2.6.  It went
> from having an ill-defined statement of what a UUID was (and for which
> Xen's code was a valid interpretation), to stating a MSFT GUID format.

Fair enough. I'd still prefer to have the (slightly questionable) Fixes:
tag, to serve as an indication that there will be a need for backporting.
Or else at the very least a statement to the effect of there not being
any good Fixes: tag to use.

Jan


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Date: Thu, 28 Aug 2025 12:51:58 +0200
MIME-Version: 1.0
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Subject: Re: [PATCH v8 1/8] xen/cpufreq: introduce new sub-hypercall to
 propagate CPPC data
To: Penny Zheng 
Cc: ray.huang@amd.com, Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: <20250828100306.1776031-1-Penny.Zheng@amd.com>
 <20250828100306.1776031-2-Penny.Zheng@amd.com>
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On 28.08.2025 12:02, Penny Zheng wrote:
> In order to provide backward compatibility with existing governors
> that represent performance as frequency, like ondemand, the _CPC
> table can optionally provide processor frequency range values, Lowest
> frequency and Nominal frequency, to let OS use Lowest Frequency/
> Performance and Nominal Frequency/Performance as anchor points to
> create linear mapping of CPPC performance to CPU frequency.
> 
> As Xen is uncapable of parsing the ACPI dynamic table, we'd like to
> introduce a new sub-hypercall "XEN_PM_CPPC" to propagate required CPPC
> data from dom0 kernel to Xen.
> In the according handler set_cppc_pminfo(), we do _CPC and _PSD
> sanitization check, as both _PSD and _CPC info are necessary for correctly
> initializing cpufreq cores in CPPC mode.
> Users shall be warned that if we failed at this point,
> no fallback scheme, like legacy P-state could be switched to.
> 
> A new flag "XEN_CPPC_INIT" is also introduced for cpufreq core initialised in
> CPPC mode. Then all .init flag checking shall be updated to
> consider "XEN_CPPC_INIT" too.
> 
> We want to bypass construction of px statistic info in cpufreq_statistic_init()
> for CPPC mode, while not bypassing cpufreq_statistic_lock initialization for a
> good reason. The same check is unnecessary for cpufreq_statistic_exit(),
> since it has already been covered by px statistic variable
> "cpufreq_statistic_data" check
> 
> Signed-off-by: Penny Zheng 

Acked-by: Jan Beulich 
with two cosmetic issues taken care of (which I'll do while committing):

> @@ -693,6 +699,120 @@ int acpi_set_pdc_bits(unsigned int acpi_id, XEN_GUEST_HANDLE(uint32) pdc)
>      return ret;
>  }
>  
> +static void print_CPPC(const struct xen_processor_cppc *cppc_data)
> +{
> +    printk("\t_CPC: highest_perf=%u, lowest_perf=%u, "
> +           "nominal_perf=%u, lowest_nonlinear_perf=%u, "
> +           "nominal_mhz=%uMHz, lowest_mhz=%uMHz\n",
> +           cppc_data->cpc.highest_perf, cppc_data->cpc.lowest_perf,
> +           cppc_data->cpc.nominal_perf, cppc_data->cpc.lowest_nonlinear_perf,
> +           cppc_data->cpc.nominal_mhz, cppc_data->cpc.lowest_mhz);
> +}
> +
> +int set_cppc_pminfo(unsigned int acpi_id,
> +                    const struct xen_processor_cppc *cppc_data)
> +{
> +    int ret = 0, cpuid;
> +    struct processor_pminfo *pm_info;
> +
> +    cpuid = get_cpu_id(acpi_id);
> +    if ( cpuid < 0 )
> +    {
> +        ret = -EINVAL;
> +        goto out;
> +    }
> +
> +    if ( cppc_data->pad[0] || cppc_data->pad[1] || cppc_data->pad[2] )
> +    {
> +        ret = -EINVAL;
> +        goto out;
> +    }
> +
> +    if ( cpufreq_verbose )
> +        printk("Set CPU%d (ACPI ID %u) CPPC state info:\n",
> +               cpuid, acpi_id);
> +
> +    pm_info = processor_pminfo[cpuid];
> +    if ( !pm_info )
> +    {
> +        pm_info = xvzalloc(struct processor_pminfo);
> +        if ( !pm_info )
> +        {
> +            ret = -ENOMEM;
> +            goto out;
> +        }
> +        processor_pminfo[cpuid] = pm_info;
> +    }
> +    pm_info->acpi_id = acpi_id;
> +    pm_info->id = cpuid;
> +    pm_info->cppc_data = *cppc_data;
> +
> +    if ( (cppc_data->flags & XEN_CPPC_PSD) &&
> +          !check_psd_pminfo(cppc_data->shared_type) )

Nit: Indentation is off by 1.

> +    {
> +            ret = -EINVAL;
> +            goto out;

Indentation is still wrong here.

Jan


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Subject: Re: [PATCH v8 5/8] xen/cpufreq: get performance policy from governor
 set via xenpm
To: Penny Zheng 
Cc: ray.huang@amd.com, xen-devel@lists.xenproject.org
References: <20250828100443.1776675-1-Penny.Zheng@amd.com>
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On 28.08.2025 12:04, Penny Zheng wrote:
> Even if Xen governor is not used in amd-cppc active mode, we could
> somehow deduce which performance policy (CPUFREQ_POLICY_xxx) user wants to
> apply through which governor they choose, such as:
> If user chooses performance governor, they want maximum performance, then
> the policy shall be CPUFREQ_POLICY_PERFORMANCE
> If user chooses powersave governor, they want the least power consumption,
> then the policy shall be CPUFREQ_POLICY_POWERSAVE
> Function cpufreq_policy_from_governor() is responsible for above transition,
> and it shall be also effective when users setting new governor through xenpm.
> 
> Userspace is a forbidden choice, and if users specify such option, we shall
> not only give warning message to suggest using "xenpm set-cpufreq-cppc", but
> also error out.
> 
> Signed-off-by: Penny Zheng 

Acked-by: Jan Beulich 



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Subject: Re: [PATCH v8 7/8] xen/cpufreq: bypass governor-related para for
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To: Penny Zheng 
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On 28.08.2025 12:05, Penny Zheng wrote:
> HWP and amd-cppc-epp are both governor-less driver, so we introduce
> "is_governor_less" flag and cpufreq_is_governorless() to help bypass
> governor-related info on dealing with cpufreq para.
> 
> Signed-off-by: Penny Zheng 

Acked-by: Jan Beulich 



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Subject: Re: [PATCH v8 8/8] xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC
 xen_sysctl_pm_op for amd-cppc driver
To: Penny Zheng 
Cc: ray.huang@amd.com, Anthony PERARD ,
 Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 xen-devel@lists.xenproject.org
References: <20250828100601.1777197-1-Penny.Zheng@amd.com>
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From: Jan Beulich 
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On 28.08.2025 12:06, Penny Zheng wrote:
> @@ -154,6 +156,17 @@ static int get_cpufreq_para(struct xen_sysctl_pm_op *op)
>      else
>          strlcpy(op->u.get_para.scaling_driver, "Unknown", CPUFREQ_NAME_LEN);
>  
> +    /*
> +     * In CPPC active mode, we are borrowing governor field to indicate
> +     * policy info.
> +     */
> +    if ( policy->governor->name[0] )
> +        strlcpy(op->u.get_para.u.s.scaling_governor,
> +                policy->governor->name, CPUFREQ_NAME_LEN);
> +    else
> +        strlcpy(op->u.get_para.u.s.scaling_governor, "Unknown",
> +                CPUFREQ_NAME_LEN);

Isn't pulling this ...

>      if ( !cpufreq_is_governorless(op->cpuid) )
>      {
>          if ( !(scaling_available_governors =

... out of this if()'s body going to affect HWP? It's not clear to me whether
that would be entirely benign.

Jan


From xen-devel-bounces@lists.xenproject.org Thu Aug 28 11:13:40 2025
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From: Hari Limaye 
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Cc: luca.fancellu@arm.com,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v3 1/5] arm/mpu: Implement setup_frametable_mappings for MPU systems
Date: Thu, 28 Aug 2025 12:12:03 +0100
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From: Luca Fancellu 

Implement the MPU variant of `setup_frametable_mappings`. This function
will be called by `setup_mm` when an implementation for MPU systems is
added in a follow up commit.

Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
Reviewed-by: Michal Orzel 
---
Changes from v1:
- Align ps and pe to page size
- Add sanity checking for frametable size, as in MMU version
- Add Michal's R-b
---
 xen/arch/arm/mpu/mm.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index c6891607ec..3f155b7db2 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -168,6 +168,39 @@ int mpumap_contains_region(pr_t *table, uint8_t nr_regions, paddr_t base,
     return MPUMAP_REGION_NOTFOUND;
 }
 
+/* Map a frame table to cover physical addresses ps through pe */
+void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
+{
+    mfn_t base_mfn;
+    paddr_t aligned_ps = ROUNDUP(ps, PAGE_SIZE);
+    paddr_t aligned_pe = ROUNDDOWN(pe, PAGE_SIZE);
+
+    unsigned long nr_pdxs = mfn_to_pdx(mfn_add(maddr_to_mfn(aligned_pe), -1)) -
+                            mfn_to_pdx(maddr_to_mfn(aligned_ps)) + 1;
+    unsigned long frametable_size = nr_pdxs * sizeof(struct page_info);
+
+    /*
+     * The size of paddr_t should be sufficient for the complete range of
+     * physical address.
+     */
+    BUILD_BUG_ON((sizeof(paddr_t) * BITS_PER_BYTE) < PADDR_BITS);
+    BUILD_BUG_ON(sizeof(struct page_info) != PAGE_INFO_SIZE);
+
+    if ( frametable_size > FRAMETABLE_SIZE )
+        panic("The frametable cannot cover the physical region %#"PRIpaddr" - %#"PRIpaddr"\n",
+              ps, pe);
+
+    frametable_base_pdx = paddr_to_pdx(aligned_ps);
+    frametable_size = ROUNDUP(frametable_size, PAGE_SIZE);
+
+    base_mfn = alloc_boot_pages(frametable_size >> PAGE_SHIFT, 1);
+    frame_table = (struct page_info *)mfn_to_virt(mfn_x(base_mfn));
+
+    memset(&frame_table[0], 0, nr_pdxs * sizeof(struct page_info));
+    memset(&frame_table[nr_pdxs], -1,
+           frametable_size - (nr_pdxs * sizeof(struct page_info)));
+}
+
 /*
  * Allocate an entry for a new EL2 MPU region in the bitmap xen_mpumap_mask.
  * @param idx   Set to the index of the allocated EL2 MPU region on success.
-- 
2.34.1



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From: Hari Limaye 
To: xen-devel@lists.xenproject.org
Cc: luca.fancellu@arm.com,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v3 0/5] Third series for R82 MPU support
Date: Thu, 28 Aug 2025 12:12:02 +0100
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Hi all,

This series is the third set of patches in the ongoing work to
introduce support for MPU systems and Cortex R82 in Xen.

The patches in this series implement the necessary logic to transiently
map and unmap the static memory banks for initialization.

Changes from v2:
- Changes mentioned in individual patches

Cheers,
Hari

Luca Fancellu (4):
  arm/mpu: Implement setup_frametable_mappings for MPU systems
  arm/mpu: Implement setup_mm for MPU systems
  arm/mpu: Implement transient mapping
  arm/mpu: Implement ioremap_attr for MPU

Penny Zheng (1):
  xen/arm: map static memory on demand

 xen/arch/arm/arm32/asm-offsets.c         |   3 +-
 xen/arch/arm/arm64/asm-offsets.c         |   2 +
 xen/arch/arm/include/asm/arm32/mpu.h     |   2 +
 xen/arch/arm/include/asm/arm64/mpu.h     |   2 +
 xen/arch/arm/include/asm/mmu/mm.h        |   3 +
 xen/arch/arm/include/asm/mpu/mm.h        |  40 +++-
 xen/arch/arm/include/asm/mpu/regions.inc |  17 +-
 xen/arch/arm/mpu/mm.c                    | 269 +++++++++++++++++++++--
 xen/arch/arm/mpu/setup.c                 |  11 +
 xen/include/xen/static-memory.h          |   8 +
 10 files changed, 335 insertions(+), 22 deletions(-)

-- 
2.34.1



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Cc: luca.fancellu@arm.com,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v3 2/5] arm/mpu: Implement setup_mm for MPU systems
Date: Thu, 28 Aug 2025 12:12:04 +0100
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From: Luca Fancellu 

Implement `setup_mm` for MPU systems. This variant doesn't need to set
up the direct map.

Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
Reviewed-by: Michal Orzel 
---
Changes from v2:
- Add Michal's R-b

Changes from v1:
- Fix total_pages dead assignment
- Remove extraneous space
- Remove redundant max_page assignment
---
 xen/arch/arm/mpu/mm.c | 62 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index 3f155b7db2..4c517d6e43 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -8,9 +8,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 
 struct page_info *frame_table;
@@ -378,9 +381,66 @@ int map_pages_to_xen(unsigned long virt, mfn_t mfn, unsigned long nr_mfns,
     return xen_mpumap_update(virt, mfn_to_maddr(mfn_add(mfn, nr_mfns)), flags);
 }
 
+/*
+ * Heap must be statically configured in Device Tree through "xen,static-heap"
+ * on MPU systems.
+ */
+static void __init setup_staticheap_mappings(void)
+{
+    const struct membanks *reserved_mem = bootinfo_get_reserved_mem();
+    unsigned int bank = 0;
+
+    for ( ; bank < reserved_mem->nr_banks; bank++ )
+    {
+        if ( reserved_mem->bank[bank].type == MEMBANK_STATIC_HEAP )
+        {
+            paddr_t bank_start = round_pgup(reserved_mem->bank[bank].start);
+            paddr_t bank_size = round_pgdown(reserved_mem->bank[bank].size);
+            paddr_t bank_end = bank_start + bank_size;
+
+            /* Map static heap with one MPU protection region */
+            if ( xen_mpumap_update(bank_start, bank_end, PAGE_HYPERVISOR) )
+                panic("Failed to map static heap\n");
+
+            break;
+        }
+    }
+
+    if ( bank == reserved_mem->nr_banks )
+        panic("No static heap memory bank found\n");
+}
+
 void __init setup_mm(void)
 {
-    BUG_ON("unimplemented");
+    const struct membanks *mem = bootinfo_get_mem();
+    paddr_t ram_start = INVALID_PADDR, ram_end = 0, ram_size = 0;
+
+    if ( !mem->nr_banks )
+        panic("No memory bank\n");
+
+    init_pdx();
+
+    populate_boot_allocator();
+
+    for ( unsigned int bank = 0; bank < mem->nr_banks; bank++ )
+    {
+        paddr_t bank_start = round_pgup(mem->bank[bank].start);
+        paddr_t bank_size = round_pgdown(mem->bank[bank].size);
+        paddr_t bank_end = bank_start + bank_size;
+
+        ram_size = ram_size + bank_size;
+        ram_start = min(ram_start, bank_start);
+        ram_end = max(ram_end, bank_end);
+    }
+
+    setup_staticheap_mappings();
+
+    total_pages = ram_size >> PAGE_SHIFT;
+
+    setup_frametable_mappings(ram_start, ram_end);
+
+    init_staticmem_pages();
+    init_sharedmem_pages();
 }
 
 int modify_xen_mappings(unsigned long s, unsigned long e, unsigned int nf)
-- 
2.34.1



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	Stefano Stabellini ,
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	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v3 3/5] arm/mpu: Implement transient mapping
Date: Thu, 28 Aug 2025 12:12:05 +0100
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From: Luca Fancellu 

Add a scheme to distinguish transient MPU regions, to identify MPU
regions which will be mapped for a short period of time. This is needed
for the functions which transiently map and unmap memory ranges on
demand which will be introduced in a future commit.

Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
Reviewed-by: Michal Orzel 
---
Changes from v2:
- Define offsets programmatically, rather than hard-coding these
- Add Michal's R-b

Changes from v1:
- Improve commit message
- Mark parameter in read helper as const
---
 xen/arch/arm/arm32/asm-offsets.c         |  3 ++-
 xen/arch/arm/arm64/asm-offsets.c         |  2 ++
 xen/arch/arm/include/asm/arm32/mpu.h     |  2 ++
 xen/arch/arm/include/asm/arm64/mpu.h     |  2 ++
 xen/arch/arm/include/asm/mpu/mm.h        | 14 +++++++++++++-
 xen/arch/arm/include/asm/mpu/regions.inc | 17 +++++++++++++----
 xen/arch/arm/mpu/mm.c                    | 23 ++++++++++++++---------
 7 files changed, 48 insertions(+), 15 deletions(-)

diff --git a/xen/arch/arm/arm32/asm-offsets.c b/xen/arch/arm/arm32/asm-offsets.c
index c203ce269d..f354bf374d 100644
--- a/xen/arch/arm/arm32/asm-offsets.c
+++ b/xen/arch/arm/arm32/asm-offsets.c
@@ -43,7 +43,6 @@ void __dummy__(void)
    OFFSET(UREGS_SP_und, struct cpu_user_regs, sp_und);
    OFFSET(UREGS_LR_und, struct cpu_user_regs, lr_und);
    OFFSET(UREGS_SPSR_und, struct cpu_user_regs, spsr_und);
-
    OFFSET(UREGS_SP_irq, struct cpu_user_regs, sp_irq);
    OFFSET(UREGS_LR_irq, struct cpu_user_regs, lr_irq);
    OFFSET(UREGS_SPSR_irq, struct cpu_user_regs, spsr_irq);
@@ -79,6 +78,8 @@ void __dummy__(void)
 #ifdef CONFIG_MPU
    DEFINE(XEN_MPUMAP_MASK_sizeof, sizeof(xen_mpumap_mask));
    DEFINE(XEN_MPUMAP_sizeof, sizeof(xen_mpumap));
+   DEFINE(XEN_MPUMAP_ENTRY_SHIFT, ilog2(sizeof(pr_t)));
+   DEFINE(XEN_MPUMAP_ENTRY_ZERO_OFFSET, sizeof(prbar_t) + sizeof(prlar_t));
    BLANK();
 #endif
 }
diff --git a/xen/arch/arm/arm64/asm-offsets.c b/xen/arch/arm/arm64/asm-offsets.c
index 320289b281..38a3894a3b 100644
--- a/xen/arch/arm/arm64/asm-offsets.c
+++ b/xen/arch/arm/arm64/asm-offsets.c
@@ -73,6 +73,8 @@ void __dummy__(void)
 #ifdef CONFIG_MPU
    DEFINE(XEN_MPUMAP_MASK_sizeof, sizeof(xen_mpumap_mask));
    DEFINE(XEN_MPUMAP_sizeof, sizeof(xen_mpumap));
+   DEFINE(XEN_MPUMAP_ENTRY_SHIFT, ilog2(sizeof(pr_t)));
+   DEFINE(XEN_MPUMAP_ENTRY_ZERO_OFFSET, sizeof(prbar_t) + sizeof(prlar_t));
    BLANK();
 #endif
 }
diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/asm/arm32/mpu.h
index 0a6930b3a0..9906d98809 100644
--- a/xen/arch/arm/include/asm/arm32/mpu.h
+++ b/xen/arch/arm/include/asm/arm32/mpu.h
@@ -39,6 +39,8 @@ typedef union {
 typedef struct {
     prbar_t prbar;
     prlar_t prlar;
+    bool transient;
+    uint8_t pad[7]; /* Pad structure to 16 Bytes */
 } pr_t;
 
 #endif /* __ASSEMBLY__ */
diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/asm/arm64/mpu.h
index f0ce344e78..1d1843eda0 100644
--- a/xen/arch/arm/include/asm/arm64/mpu.h
+++ b/xen/arch/arm/include/asm/arm64/mpu.h
@@ -38,6 +38,8 @@ typedef union {
 typedef struct {
     prbar_t prbar;
     prlar_t prlar;
+    bool transient;
+    uint8_t pad[15]; /* Pad structure to 32 Bytes */
 } pr_t;
 
 #endif /* __ASSEMBLY__ */
diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
index e1ded6521d..566d338986 100644
--- a/xen/arch/arm/include/asm/mpu/mm.h
+++ b/xen/arch/arm/include/asm/mpu/mm.h
@@ -55,6 +55,16 @@ static inline void context_sync_mpu(void)
     isb();
 }
 
+static inline bool region_is_transient(const pr_t *pr)
+{
+    return pr->transient;
+}
+
+static inline void region_set_transient(pr_t *pr, bool transient)
+{
+    pr->transient = transient;
+}
+
 /*
  * The following API requires context_sync_mpu() after being used to modify MPU
  * regions:
@@ -75,9 +85,11 @@ void write_protection_region(const pr_t *pr_write, uint8_t sel);
  * @param base      Base address of the range to map (inclusive).
  * @param limit     Limit address of the range to map (exclusive).
  * @param flags     Flags for the memory range to map.
+ * @param transient True for a transient mapping, otherwise False.
  * @return          0 on success, negative on error.
  */
-int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags);
+int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
+                      bool transient);
 
 /*
  * Creates a pr_t structure describing a protection region.
diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/include/asm/mpu/regions.inc
index 23fead3b21..09e1dcf03f 100644
--- a/xen/arch/arm/include/asm/mpu/regions.inc
+++ b/xen/arch/arm/include/asm/mpu/regions.inc
@@ -14,19 +14,25 @@
 #define PRLAR_ELx_EN            0x1
 
 #ifdef CONFIG_ARM_64
-#define XEN_MPUMAP_ENTRY_SHIFT  0x4     /* 16 byte structure */
-
 .macro store_pair reg1, reg2, dst
     stp \reg1, \reg2, [\dst]
 .endm
 
-#else
-#define XEN_MPUMAP_ENTRY_SHIFT  0x3     /* 8 byte structure */
+.macro zero_pair dst, offset, tmp1, tmp2
+    stp xzr, xzr, [\dst, \offset]
+.endm
 
+#else
 .macro store_pair reg1, reg2, dst
     strd  \reg1, \reg2, [\dst]
 .endm
 
+.macro zero_pair dst, offset, tmp1, tmp2
+    mov \tmp1, #0
+    mov \tmp2, #0
+    strd \tmp1, \tmp2, [\dst, \offset]
+.endm
+
 #endif
 
 /*
@@ -97,6 +103,9 @@
 
 3:
 
+    /* Clear the rest of the xen_mpumap entry. Clobbers prbar and prlar. */
+    zero_pair \base, #XEN_MPUMAP_ENTRY_ZERO_OFFSET, \prbar, \prlar
+
     add   \sel, \sel, #1
 
 1:
diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index 4c517d6e43..33333181d5 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -265,13 +265,14 @@ static void disable_mpu_region_from_index(uint8_t index)
  * Update the entry in the MPU memory region mapping table (xen_mpumap) for the
  * given memory range and flags, creating one if none exists.
  *
- * @param base  Base address (inclusive).
- * @param limit Limit address (exclusive).
- * @param flags Region attributes (a combination of PAGE_HYPERVISOR_XXX)
+ * @param base      Base address (inclusive).
+ * @param limit     Limit address (exclusive).
+ * @param flags     Region attributes (a combination of PAGE_HYPERVISOR_XXX)
+ * @param transient True for a transient mapping, otherwise False.
  * @return      0 on success, otherwise negative on error.
  */
 static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
-                                   unsigned int flags)
+                                   unsigned int flags, bool transient)
 {
     bool flags_has_page_present;
     uint8_t idx;
@@ -311,6 +312,7 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
             return -ENOENT;
 
         xen_mpumap[idx] = pr_of_addr(base, limit, flags);
+        region_set_transient(&xen_mpumap[idx], transient);
 
         write_protection_region(&xen_mpumap[idx], idx);
     }
@@ -330,7 +332,8 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
     return 0;
 }
 
-int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags)
+int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
+                      bool transient)
 {
     int rc;
 
@@ -356,7 +359,7 @@ int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags)
 
     spin_lock(&xen_mpumap_lock);
 
-    rc = xen_mpumap_update_entry(base, limit, flags);
+    rc = xen_mpumap_update_entry(base, limit, flags, transient);
     if ( !rc )
         context_sync_mpu();
 
@@ -371,14 +374,15 @@ int destroy_xen_mappings(unsigned long s, unsigned long e)
     ASSERT(IS_ALIGNED(e, PAGE_SIZE));
     ASSERT(s < e);
 
-    return xen_mpumap_update(s, e, 0);
+    return xen_mpumap_update(s, e, 0, false);
 }
 
 int map_pages_to_xen(unsigned long virt, mfn_t mfn, unsigned long nr_mfns,
                      unsigned int flags)
 {
     /* MPU systems have no translation, ma == va, so pass virt directly */
-    return xen_mpumap_update(virt, mfn_to_maddr(mfn_add(mfn, nr_mfns)), flags);
+    return xen_mpumap_update(virt, mfn_to_maddr(mfn_add(mfn, nr_mfns)), flags,
+                             false);
 }
 
 /*
@@ -399,7 +403,8 @@ static void __init setup_staticheap_mappings(void)
             paddr_t bank_end = bank_start + bank_size;
 
             /* Map static heap with one MPU protection region */
-            if ( xen_mpumap_update(bank_start, bank_end, PAGE_HYPERVISOR) )
+            if ( xen_mpumap_update(bank_start, bank_end, PAGE_HYPERVISOR,
+                                   false) )
                 panic("Failed to map static heap\n");
 
             break;
-- 
2.34.1



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To: xen-devel@lists.xenproject.org
Cc: luca.fancellu@arm.com,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk 
Subject: [PATCH v3 4/5] arm/mpu: Implement ioremap_attr for MPU
Date: Thu, 28 Aug 2025 12:12:06 +0100
Message-ID: <53c6aa61bc0cefce369ffc3a9ff5a7060b5f4b20.1756379422.git.hari.limaye@arm.com>
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From: Luca Fancellu 

Introduce helpers (un)map_mm_range() in order to allow the transient
mapping of a range of memory, and use these to implement the function
`ioremap_attr` for MPU systems.

Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
---
Changes from v2:
- Propagate error to caller of is_mm_range_mapped, rather than panic

Changes from v1:
- Use transient instead of temporary, and improve wording of comments
  regarding transient mapping
- Rename start, end -> base, limit
---
 xen/arch/arm/include/asm/mpu/mm.h |  22 +++++
 xen/arch/arm/mpu/mm.c             | 157 ++++++++++++++++++++++++++++--
 2 files changed, 170 insertions(+), 9 deletions(-)

diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
index 566d338986..efb0680e39 100644
--- a/xen/arch/arm/include/asm/mpu/mm.h
+++ b/xen/arch/arm/include/asm/mpu/mm.h
@@ -101,6 +101,28 @@ int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
  */
 pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags);
 
+/*
+ * Maps transiently a range of memory with attributes `flags`; if the range is
+ * already mapped with the same attributes, including an inclusive match, the
+ * existing mapping is returned. This API is intended for mappings that exist
+ * transiently for a short period between calls to this function and
+ * `unmap_mm_range`.
+ *
+ * @param base      Base address of the range to map (inclusive).
+ * @param limit     Limit address of the range to map (exclusive).
+ * @param flags     Flags for the memory range to map.
+ * @return          Pointer to base of region on success, NULL on error.
+ */
+void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags);
+
+/*
+ * Unmaps a range of memory if it was previously mapped by map_mm_range,
+ * otherwise it does not remove the mapping.
+ *
+ * @param base     Base address of the range to map (inclusive).
+ */
+void unmap_mm_range(paddr_t base);
+
 /*
  * Checks whether a given memory range is present in the provided table of
  * MPU protection regions.
diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
index 33333181d5..337573f9d7 100644
--- a/xen/arch/arm/mpu/mm.c
+++ b/xen/arch/arm/mpu/mm.c
@@ -332,31 +332,39 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
     return 0;
 }
 
-int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
-                      bool transient)
+static bool check_mpu_mapping(paddr_t base, paddr_t limit, unsigned int flags)
 {
-    int rc;
-
     if ( flags_has_rwx(flags) )
     {
         printk("Mappings should not be both Writeable and Executable\n");
-        return -EINVAL;
+        return false;
     }
 
     if ( base >= limit )
     {
         printk("Base address %#"PRIpaddr" must be smaller than limit address %#"PRIpaddr"\n",
                base, limit);
-        return -EINVAL;
+        return false;
     }
 
     if ( !IS_ALIGNED(base, PAGE_SIZE) || !IS_ALIGNED(limit, PAGE_SIZE) )
     {
         printk("base address %#"PRIpaddr", or limit address %#"PRIpaddr" is not page aligned\n",
                base, limit);
-        return -EINVAL;
+        return false;
     }
 
+    return true;
+}
+
+int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
+                      bool transient)
+{
+    int rc;
+
+    if ( !check_mpu_mapping(base, limit, flags) )
+        return -EINVAL;
+
     spin_lock(&xen_mpumap_lock);
 
     rc = xen_mpumap_update_entry(base, limit, flags, transient);
@@ -465,10 +473,141 @@ void free_init_memory(void)
     BUG_ON("unimplemented");
 }
 
+static int is_mm_range_mapped(paddr_t start, paddr_t end, uint8_t *idx)
+{
+    ASSERT(spin_is_locked(&xen_mpumap_lock));
+
+    /*
+     * 'idx' will be INVALID_REGION_IDX for rc == MPUMAP_REGION_NOTFOUND and
+     * it will be a proper region index when rc >= MPUMAP_REGION_FOUND.
+     */
+    return mpumap_contains_region(xen_mpumap, max_mpu_regions, start, end, idx);
+}
+
+static bool is_mm_attr_match(pr_t *region, unsigned int attributes)
+{
+    bool ret = true;
+
+    if ( region->prbar.reg.ro != PAGE_RO_MASK(attributes) )
+    {
+        printk(XENLOG_WARNING
+               "Mismatched Access Permission attributes (%#x0 instead of %#x0)\n",
+               region->prbar.reg.ro, PAGE_RO_MASK(attributes));
+        ret = false;
+    }
+
+    if ( region->prbar.reg.xn != PAGE_XN_MASK(attributes) )
+    {
+        printk(XENLOG_WARNING
+               "Mismatched Execute Never attributes (%#x instead of %#x)\n",
+               region->prbar.reg.xn, PAGE_XN_MASK(attributes));
+        ret = false;
+    }
+
+    if ( region->prlar.reg.ai != PAGE_AI_MASK(attributes) )
+    {
+        printk(XENLOG_WARNING
+               "Mismatched Memory Attribute Index (%#x instead of %#x)\n",
+               region->prlar.reg.ai, PAGE_AI_MASK(attributes));
+        ret = false;
+    }
+
+    return ret;
+}
+
+void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags)
+{
+    paddr_t start_pg = round_pgdown(base);
+    paddr_t end_pg = round_pgup(limit);
+    void *ret = NULL;
+    uint8_t idx;
+    int rc;
+
+    if ( !check_mpu_mapping(start_pg, end_pg, flags) )
+        return NULL;
+
+    spin_lock(&xen_mpumap_lock);
+
+    rc = is_mm_range_mapped(start_pg, end_pg, &idx);
+    if ( rc < 0 ) {
+        printk(XENLOG_WARNING
+               "Cannot handle overlapping MPU memory protection regions\n");
+        goto out;
+    }
+
+    if ( idx != INVALID_REGION_IDX )
+    {
+        /* Already mapped with different attributes */
+        if ( !is_mm_attr_match(&xen_mpumap[idx], flags) )
+        {
+            printk(XENLOG_WARNING
+                   "Range %#"PRIpaddr"-%#"PRIpaddr" already mapped with different flags\n",
+                   start_pg, end_pg);
+            goto out;
+        }
+
+        /* Already mapped with same attributes */
+        ret = maddr_to_virt(base);
+        goto out;
+    }
+
+    if ( !xen_mpumap_update_entry(start_pg, end_pg, flags, true) )
+    {
+        context_sync_mpu();
+        ret = maddr_to_virt(base);
+    }
+
+ out:
+    spin_unlock(&xen_mpumap_lock);
+
+    return ret;
+}
+
+void unmap_mm_range(paddr_t base)
+{
+    uint8_t idx;
+    int rc;
+
+    spin_lock(&xen_mpumap_lock);
+
+    /*
+     * Mappings created via map_mm_range are at least PAGE_SIZE. Find the idx
+     * of the MPU memory region containing `start` mapped through map_mm_range.
+     */
+    rc = is_mm_range_mapped(base, base + PAGE_SIZE, &idx);
+    if ( rc < 0 ) {
+        printk(XENLOG_WARNING
+               "Cannot handle overlapping MPU memory protection regions\n");
+        goto out;
+    }
+
+    if ( idx == INVALID_REGION_IDX )
+    {
+        printk(XENLOG_ERR
+               "Failed to unmap_mm_range MPU memory region at %#"PRIpaddr"\n",
+               base);
+        goto out;
+    }
+
+    /* This API is only meant to unmap transient regions */
+    if ( !region_is_transient(&xen_mpumap[idx]) )
+        goto out;
+
+    /* Disable MPU memory region and clear the associated entry in xen_mpumap */
+    disable_mpu_region_from_index(idx);
+    context_sync_mpu();
+
+ out:
+    spin_unlock(&xen_mpumap_lock);
+}
+
 void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int flags)
 {
-    BUG_ON("unimplemented");
-    return NULL;
+    if ( !map_mm_range(start, start + len, flags) )
+        return NULL;
+
+    /* Mapped or already mapped */
+    return maddr_to_virt(start);
 }
 
 /*
-- 
2.34.1



From xen-devel-bounces@lists.xenproject.org Thu Aug 28 11:13:51 2025
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From: Hari Limaye 
To: xen-devel@lists.xenproject.org
Cc: luca.fancellu@arm.com,
	Penny Zheng ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Penny Zheng ,
	Wei Chen 
Subject: [PATCH v3 5/5] xen/arm: map static memory on demand
Date: Thu, 28 Aug 2025 12:12:07 +0100
Message-ID: <30cbc79f765c21759d74377e55cc471210fc2575.1756379422.git.hari.limaye@arm.com>
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From: Penny Zheng 

In the function `init_staticmem_pages` we need to have mapped static
memory banks for initialization. Unlike on an MMU system, we cannot map
the entire RAM on an MPU system as we have a limited number of MPU
memory regions. To solve this, transiently map the static memory banks
for initialization.

Signed-off-by: Penny Zheng 
Signed-off-by: Wei Chen 
Signed-off-by: Luca Fancellu 
Signed-off-by: Hari Limaye 
Reviewed-by: Michal Orzel 
---
Changes from v2:
- Add Michal's R-b
---
 xen/arch/arm/include/asm/mmu/mm.h |  3 +++
 xen/arch/arm/include/asm/mpu/mm.h |  4 ++++
 xen/arch/arm/mpu/setup.c          | 11 +++++++++++
 xen/include/xen/static-memory.h   |  8 ++++++++
 4 files changed, 26 insertions(+)

diff --git a/xen/arch/arm/include/asm/mmu/mm.h b/xen/arch/arm/include/asm/mmu/mm.h
index 7f4d59137d..645a0ea3cb 100644
--- a/xen/arch/arm/include/asm/mmu/mm.h
+++ b/xen/arch/arm/include/asm/mmu/mm.h
@@ -110,6 +110,9 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr,
 extern void switch_ttbr(uint64_t ttbr);
 extern void relocate_and_switch_ttbr(uint64_t ttbr);
 
+static inline void map_staticmem_pages_to_xen(paddr_t start, paddr_t end) {}
+static inline void unmap_staticmem_pages_to_xen(paddr_t start, paddr_t end) {}
+
 #endif /* __ARM_MMU_MM_H__ */
 
 /*
diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
index efb0680e39..4cc769418e 100644
--- a/xen/arch/arm/include/asm/mpu/mm.h
+++ b/xen/arch/arm/include/asm/mpu/mm.h
@@ -123,6 +123,10 @@ void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags);
  */
 void unmap_mm_range(paddr_t base);
 
+/* {un}map_staticmem_pages_to_xen used while initializing static memory banks */
+void map_staticmem_pages_to_xen(paddr_t start, paddr_t end);
+void unmap_staticmem_pages_to_xen(paddr_t start, paddr_t end);
+
 /*
  * Checks whether a given memory range is present in the provided table of
  * MPU protection regions.
diff --git a/xen/arch/arm/mpu/setup.c b/xen/arch/arm/mpu/setup.c
index 163573b932..dbc3107333 100644
--- a/xen/arch/arm/mpu/setup.c
+++ b/xen/arch/arm/mpu/setup.c
@@ -83,6 +83,17 @@ void * __init early_fdt_map(paddr_t fdt_paddr)
     return fdt_virt;
 }
 
+void __init map_staticmem_pages_to_xen(paddr_t start, paddr_t end)
+{
+    if ( !map_mm_range(start, end, PAGE_HYPERVISOR) )
+        panic("Unable to map staticmem pages to Xen!");
+}
+
+void __init unmap_staticmem_pages_to_xen(paddr_t start, paddr_t end)
+{
+    unmap_mm_range(start);
+}
+
 /*
  * copy_from_paddr - copy data from a physical address
  * @dst: destination virtual address
diff --git a/xen/include/xen/static-memory.h b/xen/include/xen/static-memory.h
index e445aa8057..d99abac113 100644
--- a/xen/include/xen/static-memory.h
+++ b/xen/include/xen/static-memory.h
@@ -18,7 +18,15 @@ static inline void init_staticmem_bank(const struct membank *bank)
     if ( mfn_x(bank_end) <= mfn_x(bank_start) )
         return;
 
+    /* Map temporarily before initialization */
+    map_staticmem_pages_to_xen(mfn_to_maddr(bank_start),
+                               mfn_to_maddr(bank_end));
+
     unprepare_staticmem_pages(mfn_to_page(bank_start), bank_pages, false);
+
+    /* Unmap immediately after initialization */
+    unmap_staticmem_pages_to_xen(mfn_to_maddr(bank_start),
+                                 mfn_to_maddr(bank_end));
 }
 
 void allocate_static_memory(struct domain *d, struct kernel_info *kinfo,
-- 
2.34.1



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Subject: Re: [PATCH v8 3/8] xen/cpufreq: implement amd-cppc driver for CPPC in
 passive mode
To: Penny Zheng , Jason Andryuk 
Cc: ray.huang@amd.com, Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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In-Reply-To: <20250828100306.1776031-4-Penny.Zheng@amd.com>
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On 28.08.2025 12:03, Penny Zheng wrote:
> +static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy,
> +                                            unsigned int target_freq,
> +                                            unsigned int relation)
> +{
> +    unsigned int cpu = policy->cpu;
> +    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);

I fear there's a problem here that I so far overlooked. As it happens, just
yesterday I made a patch to eliminate cpufreq_drv_data[] global. In the
course of doing so it became clear that in principle the CPU denoted by
policy->cpu can be offline. Hence its per-CPU data is also unavailable. See
cpufreq_add_cpu()'s invocation of .init() and cpufreq_del_cpu()'s invocation
of .exit(). Is there anything well-hidden (and likely lacking some suitable
comment) which guarantees that no two CPUs (threads) will be in the same
domain? If not, I fear you simply can't use per-CPU data here.

Since initially I was thinking of using per-CPU data also in my patch, I'm
reproducing this in raw form below, for your reference. It's generally only
4.22 material now, of course. Yet in turn for your driver the new drv_data
field may want to become a union, with an "acpi" and a "cppc" sub-struct.
And possibly a "hwp" one: Jason, looks like the HWP driver has a similar
issue (unless again something guarantees that no two CPUs / threads will
be in the same domain).

Jan

cpufreq: eliminate cpufreq_drv_data[]

Possibly many slots of it may be unused (all of them when the HWP or CPPC
drivers are in use), as it's always strictly associated with the CPU
recorded in a policy (irrespective of that CPU intermediately being taken
offline). It is shared by all CPUs sharing a policy. We could therefore
put the respective pointers in struct cpufreq_policy, but even that level
of indirection is pointless. Embed the driver data structure directly in
the policy one.

Signed-off-by: Jan Beulich 

--- a/xen/arch/x86/acpi/cpufreq/acpi.c
+++ b/xen/arch/x86/acpi/cpufreq/acpi.c
@@ -174,17 +174,18 @@ static u32 get_cur_val(const cpumask_t *
         return 0;
 
     policy = per_cpu(cpufreq_cpu_policy, cpu);
-    if (!policy || !cpufreq_drv_data[policy->cpu])
+    if ( !policy )
         return 0;
 
-    switch (cpufreq_drv_data[policy->cpu]->arch_cpu_flags) {
+    switch ( policy->drv_data.arch_cpu_flags )
+    {
     case SYSTEM_INTEL_MSR_CAPABLE:
         cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
         cmd.addr.msr.reg = MSR_IA32_PERF_STATUS;
         break;
     case SYSTEM_IO_CAPABLE:
         cmd.type = SYSTEM_IO_CAPABLE;
-        perf = cpufreq_drv_data[policy->cpu]->acpi_data;
+        perf = policy->drv_data.acpi_data;
         cmd.addr.io.port = perf->control_register.address;
         cmd.addr.io.bit_width = perf->control_register.bit_width;
         break;
@@ -210,9 +211,8 @@ static unsigned int cf_check get_cur_fre
     if (!policy)
         return 0;
 
-    data = cpufreq_drv_data[policy->cpu];
-    if (unlikely(data == NULL ||
-        data->acpi_data == NULL || data->freq_table == NULL))
+    data = &policy->drv_data;
+    if ( !data->acpi_data || !data->freq_table )
         return 0;
 
     return extract_freq(get_cur_val(cpumask_of(cpu)), data);
@@ -255,7 +255,7 @@ static int cf_check acpi_cpufreq_target(
     struct cpufreq_policy *policy,
     unsigned int target_freq, unsigned int relation)
 {
-    struct acpi_cpufreq_data *data = cpufreq_drv_data[policy->cpu];
+    struct acpi_cpufreq_data *data = &policy->drv_data;
     struct processor_performance *perf;
     struct cpufreq_freqs freqs;
     cpumask_t online_policy_cpus;
@@ -265,10 +265,8 @@ static int cf_check acpi_cpufreq_target(
     unsigned int j;
     int result = 0;
 
-    if (unlikely(data == NULL ||
-        data->acpi_data == NULL || data->freq_table == NULL)) {
+    if ( !data->acpi_data || !data->freq_table )
         return -ENODEV;
-    }
 
     if (policy->turbo == CPUFREQ_TURBO_DISABLED)
         if (target_freq > policy->cpuinfo.second_max_freq)
@@ -334,11 +332,9 @@ static int cf_check acpi_cpufreq_target(
 
 static int cf_check acpi_cpufreq_verify(struct cpufreq_policy *policy)
 {
-    struct acpi_cpufreq_data *data;
     struct processor_performance *perf;
 
-    if (!policy || !(data = cpufreq_drv_data[policy->cpu]) ||
-        !processor_pminfo[policy->cpu])
+    if ( !policy || !processor_pminfo[policy->cpu] )
         return -EINVAL;
 
     perf = &processor_pminfo[policy->cpu]->perf;
@@ -346,7 +342,7 @@ static int cf_check acpi_cpufreq_verify(
     cpufreq_verify_within_limits(policy, 0,
         perf->states[perf->platform_limit].core_frequency * 1000);
 
-    return cpufreq_frequency_table_verify(policy, data->freq_table);
+    return cpufreq_frequency_table_verify(policy, policy->drv_data.freq_table);
 }
 
 static unsigned long
@@ -382,17 +378,11 @@ static int cf_check acpi_cpufreq_cpu_ini
     unsigned int i;
     unsigned int valid_states = 0;
     unsigned int cpu = policy->cpu;
-    struct acpi_cpufreq_data *data;
+    struct acpi_cpufreq_data *data = &policy->drv_data;
     unsigned int result = 0;
     struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
     struct processor_performance *perf;
 
-    data = xzalloc(struct acpi_cpufreq_data);
-    if (!data)
-        return -ENOMEM;
-
-    cpufreq_drv_data[cpu] = data;
-
     data->acpi_data = &processor_pminfo[cpu]->perf;
 
     perf = data->acpi_data;
@@ -409,23 +399,18 @@ static int cf_check acpi_cpufreq_cpu_ini
         if (cpufreq_verbose)
             printk("xen_pminfo: @acpi_cpufreq_cpu_init,"
                    "HARDWARE addr space\n");
-        if (!cpu_has(c, X86_FEATURE_EIST)) {
-            result = -ENODEV;
-            goto err_unreg;
-        }
+        if ( !cpu_has(c, X86_FEATURE_EIST) )
+            return -ENODEV;
         data->arch_cpu_flags = SYSTEM_INTEL_MSR_CAPABLE;
         break;
     default:
-        result = -ENODEV;
-        goto err_unreg;
+        return -ENODEV;
     }
 
     data->freq_table = xmalloc_array(struct cpufreq_frequency_table,
                                     (perf->state_count+1));
-    if (!data->freq_table) {
-        result = -ENOMEM;
-        goto err_unreg;
-    }
+    if ( !data->freq_table )
+        return -ENOMEM;
 
     /* detect transition latency */
     policy->cpuinfo.transition_latency = 0;
@@ -483,23 +468,14 @@ static int cf_check acpi_cpufreq_cpu_ini
     return result;
 
 err_freqfree:
-    xfree(data->freq_table);
-err_unreg:
-    xfree(data);
-    cpufreq_drv_data[cpu] = NULL;
+    XFREE(data->freq_table);
 
     return result;
 }
 
 static int cf_check acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy)
 {
-    struct acpi_cpufreq_data *data = cpufreq_drv_data[policy->cpu];
-
-    if (data) {
-        cpufreq_drv_data[policy->cpu] = NULL;
-        xfree(data->freq_table);
-        xfree(data);
-    }
+    XFREE(policy->drv_data.freq_table);
 
     return 0;
 }
--- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
+++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
@@ -35,8 +35,6 @@
 
 #include 
 
-struct acpi_cpufreq_data *cpufreq_drv_data[NR_CPUS];
-
 struct perf_pair {
     union {
         struct {
--- a/xen/arch/x86/acpi/cpufreq/powernow.c
+++ b/xen/arch/x86/acpi/cpufreq/powernow.c
@@ -84,16 +84,14 @@ static int cf_check powernow_cpufreq_tar
     struct cpufreq_policy *policy,
     unsigned int target_freq, unsigned int relation)
 {
-    struct acpi_cpufreq_data *data = cpufreq_drv_data[policy->cpu];
+    struct acpi_cpufreq_data *data = &policy->drv_data;
     struct processor_performance *perf;
     unsigned int next_state; /* Index into freq_table */
     unsigned int next_perf_state; /* Index into perf table */
     int result;
 
-    if (unlikely(data == NULL ||
-        data->acpi_data == NULL || data->freq_table == NULL)) {
+    if ( !data->acpi_data || !data->freq_table )
         return -ENODEV;
-    }
 
     perf = data->acpi_data;
     result = cpufreq_frequency_table_target(policy,
@@ -185,11 +183,9 @@ static void cf_check get_cpu_data(void *
 
 static int cf_check powernow_cpufreq_verify(struct cpufreq_policy *policy)
 {
-    struct acpi_cpufreq_data *data;
     struct processor_performance *perf;
 
-    if (!policy || !(data = cpufreq_drv_data[policy->cpu]) ||
-        !processor_pminfo[policy->cpu])
+    if ( !policy || !processor_pminfo[policy->cpu] )
         return -EINVAL;
 
     perf = &processor_pminfo[policy->cpu]->perf;
@@ -197,7 +193,7 @@ static int cf_check powernow_cpufreq_ver
     cpufreq_verify_within_limits(policy, 0, 
         perf->states[perf->platform_limit].core_frequency * 1000);
 
-    return cpufreq_frequency_table_verify(policy, data->freq_table);
+    return cpufreq_frequency_table_verify(policy, policy->drv_data.freq_table);
 }
 
 static int cf_check powernow_cpufreq_cpu_init(struct cpufreq_policy *policy)
@@ -205,18 +201,12 @@ static int cf_check powernow_cpufreq_cpu
     unsigned int i;
     unsigned int valid_states = 0;
     unsigned int cpu = policy->cpu;
-    struct acpi_cpufreq_data *data;
+    struct acpi_cpufreq_data *data = &policy->drv_data;
     unsigned int result = 0;
     struct processor_performance *perf;
     struct amd_cpu_data info;
     struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
 
-    data = xzalloc(struct acpi_cpufreq_data);
-    if (!data)
-        return -ENOMEM;
-
-    cpufreq_drv_data[cpu] = data;
-
     data->acpi_data = &processor_pminfo[cpu]->perf;
 
     info.perf = perf = data->acpi_data;
@@ -228,8 +218,7 @@ static int cf_check powernow_cpufreq_cpu
         if (cpumask_weight(policy->cpus) != 1) {
             printk(XENLOG_WARNING "Unsupported sharing type %d (%u CPUs)\n",
                    policy->shared_type, cpumask_weight(policy->cpus));
-            result = -ENODEV;
-            goto err_unreg;
+            return -ENODEV;
         }
     } else {
         cpumask_copy(policy->cpus, cpumask_of(cpu));
@@ -238,21 +227,16 @@ static int cf_check powernow_cpufreq_cpu
     /* capability check */
     if (perf->state_count <= 1) {
         printk("No P-States\n");
-        result = -ENODEV;
-        goto err_unreg;
+        return -ENODEV;
     }
 
-    if (perf->control_register.space_id != perf->status_register.space_id) {
-        result = -ENODEV;
-        goto err_unreg;
-    }
+    if ( perf->control_register.space_id != perf->status_register.space_id )
+        return -ENODEV;
 
     data->freq_table = xmalloc_array(struct cpufreq_frequency_table, 
                                     (perf->state_count+1));
-    if (!data->freq_table) {
-        result = -ENOMEM;
-        goto err_unreg;
-    }
+    if ( !data->freq_table )
+        return -ENOMEM;
 
     /* detect transition latency */
     policy->cpuinfo.transition_latency = 0;
@@ -298,23 +282,14 @@ static int cf_check powernow_cpufreq_cpu
     return result;
 
 err_freqfree:
-    xfree(data->freq_table);
-err_unreg:
-    xfree(data);
-    cpufreq_drv_data[cpu] = NULL;
+    XFREE(data->freq_table);
 
     return result;
 }
 
 static int cf_check powernow_cpufreq_cpu_exit(struct cpufreq_policy *policy)
 {
-    struct acpi_cpufreq_data *data = cpufreq_drv_data[policy->cpu];
-
-    if (data) {
-        cpufreq_drv_data[policy->cpu] = NULL;
-        xfree(data->freq_table);
-        xfree(data);
-    }
+    XFREE(policy->drv_data.freq_table);
 
     return 0;
 }
--- a/xen/include/acpi/cpufreq/cpufreq.h
+++ b/xen/include/acpi/cpufreq/cpufreq.h
@@ -37,8 +37,6 @@ struct acpi_cpufreq_data {
     unsigned int arch_cpu_flags;
 };
 
-extern struct acpi_cpufreq_data *cpufreq_drv_data[NR_CPUS];
-
 struct cpufreq_cpuinfo {
     unsigned int        max_freq;
     unsigned int        second_max_freq;    /* P1 if Turbo Mode is on */
@@ -80,6 +78,8 @@ struct cpufreq_policy {
     int8_t              turbo;  /* tristate flag: 0 for unsupported
                                  * -1 for disable, 1 for enabled
                                  * See CPUFREQ_TURBO_* below for defines */
+
+    struct acpi_cpufreq_data drv_data;
 };
 DECLARE_PER_CPU(struct cpufreq_policy *, cpufreq_cpu_policy);
 



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Date: Thu, 28 Aug 2025 14:57:29 +0300
From: Leon Romanovsky 
To: Marek Szyprowski 
Cc: Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 00/16] dma-mapping: migrate to physical address-based
 API
Message-ID: <20250828115729.GA10073@unreal>
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In-Reply-To: 

On Tue, Aug 19, 2025 at 08:36:44PM +0300, Leon Romanovsky wrote:
> Changelog:
> v4:
>  * Fixed kbuild error with mismatch in kmsan function declaration due to
>    rebase error.
> v3: https://lore.kernel.org/all/cover.1755193625.git.leon@kernel.org
>  * Fixed typo in "cacheable" word
>  * Simplified kmsan patch a lot to be simple argument refactoring
> v2: https://lore.kernel.org/all/cover.1755153054.git.leon@kernel.org
>  * Used commit messages and cover letter from Jason
>  * Moved setting IOMMU_MMIO flag to dma_info_to_prot function
>  * Micro-optimized the code
>  * Rebased code on v6.17-rc1
> v1: https://lore.kernel.org/all/cover.1754292567.git.leon@kernel.org
>  * Added new DMA_ATTR_MMIO attribute to indicate
>    PCI_P2PDMA_MAP_THRU_HOST_BRIDGE path.
>  * Rewrote dma_map_* functions to use thus new attribute
> v0: https://lore.kernel.org/all/cover.1750854543.git.leon@kernel.org/
> ------------------------------------------------------------------------
> 
> This series refactors the DMA mapping to use physical addresses
> as the primary interface instead of page+offset parameters. This
> change aligns the DMA API with the underlying hardware reality where
> DMA operations work with physical addresses, not page structures.
> 
> The series maintains export symbol backward compatibility by keeping
> the old page-based API as wrapper functions around the new physical
> address-based implementations.
> 
> This series refactors the DMA mapping API to provide a phys_addr_t
> based, and struct-page free, external API that can handle all the
> mapping cases we want in modern systems:
> 
>  - struct page based cachable DRAM
>  - struct page MEMORY_DEVICE_PCI_P2PDMA PCI peer to peer non-cachable
>    MMIO
>  - struct page-less PCI peer to peer non-cachable MMIO
>  - struct page-less "resource" MMIO
> 
> Overall this gets much closer to Matthew's long term wish for
> struct-pageless IO to cachable DRAM. The remaining primary work would
> be in the mm side to allow kmap_local_pfn()/phys_to_virt() to work on
> phys_addr_t without a struct page.
> 
> The general design is to remove struct page usage entirely from the
> DMA API inner layers. For flows that need to have a KVA for the
> physical address they can use kmap_local_pfn() or phys_to_virt(). This
> isolates the struct page requirements to MM code only. Long term all
> removals of struct page usage are supporting Matthew's memdesc
> project which seeks to substantially transform how struct page works.
> 
> Instead make the DMA API internals work on phys_addr_t. Internally
> there are still dedicated 'page' and 'resource' flows, except they are
> now distinguished by a new DMA_ATTR_MMIO instead of by callchain. Both
> flows use the same phys_addr_t.
> 
> When DMA_ATTR_MMIO is specified things work similar to the existing
> 'resource' flow. kmap_local_pfn(), phys_to_virt(), phys_to_page(),
> pfn_valid(), etc are never called on the phys_addr_t. This requires
> rejecting any configuration that would need swiotlb. CPU cache
> flushing is not required, and avoided, as ATTR_MMIO also indicates the
> address have no cachable mappings. This effectively removes any
> DMA API side requirement to have struct page when DMA_ATTR_MMIO is
> used.
> 
> In the !DMA_ATTR_MMIO mode things work similarly to the 'page' flow,
> except on the common path of no cache flush, no swiotlb it never
> touches a struct page. When cache flushing or swiotlb copying
> kmap_local_pfn()/phys_to_virt() are used to get a KVA for CPU
> usage. This was already the case on the unmap side, now the map side
> is symmetric.
> 
> Callers are adjusted to set DMA_ATTR_MMIO. Existing 'resource' users
> must set it. The existing struct page based MEMORY_DEVICE_PCI_P2PDMA
> path must also set it. This corrects some existing bugs where iommu
> mappings for P2P MMIO were improperly marked IOMMU_CACHE.
> 
> Since ATTR_MMIO is made to work with all the existing DMA map entry
> points, particularly dma_iova_link(), this finally allows a way to use
> the new DMA API to map PCI P2P MMIO without creating struct page. The
> VFIO DMABUF series demonstrates how this works. This is intended to
> replace the incorrect driver use of dma_map_resource() on PCI BAR
> addresses.
> 
> This series does the core code and modern flows. A followup series
> will give the same treatment to the legacy dma_ops implementation.
> 
> Thanks
> 
> Leon Romanovsky (16):
>   dma-mapping: introduce new DMA attribute to indicate MMIO memory
>   iommu/dma: implement DMA_ATTR_MMIO for dma_iova_link().
>   dma-debug: refactor to use physical addresses for page mapping
>   dma-mapping: rename trace_dma_*map_page to trace_dma_*map_phys
>   iommu/dma: rename iommu_dma_*map_page to iommu_dma_*map_phys
>   iommu/dma: extend iommu_dma_*map_phys API to handle MMIO memory
>   dma-mapping: convert dma_direct_*map_page to be phys_addr_t based
>   kmsan: convert kmsan_handle_dma to use physical addresses
>   dma-mapping: handle MMIO flow in dma_map|unmap_page
>   xen: swiotlb: Open code map_resource callback
>   dma-mapping: export new dma_*map_phys() interface
>   mm/hmm: migrate to physical address-based DMA mapping API
>   mm/hmm: properly take MMIO path
>   block-dma: migrate to dma_map_phys instead of map_page
>   block-dma: properly take MMIO path
>   nvme-pci: unmap MMIO pages with appropriate interface
> 
>  Documentation/core-api/dma-api.rst        |   4 +-
>  Documentation/core-api/dma-attributes.rst |  18 ++++
>  arch/powerpc/kernel/dma-iommu.c           |   4 +-
>  block/blk-mq-dma.c                        |  15 ++-
>  drivers/iommu/dma-iommu.c                 |  61 +++++------
>  drivers/nvme/host/pci.c                   |  18 +++-
>  drivers/virtio/virtio_ring.c              |   4 +-
>  drivers/xen/swiotlb-xen.c                 |  21 +++-
>  include/linux/blk-mq-dma.h                |   6 +-
>  include/linux/blk_types.h                 |   2 +
>  include/linux/dma-direct.h                |   2 -
>  include/linux/dma-map-ops.h               |   8 +-
>  include/linux/dma-mapping.h               |  33 ++++++
>  include/linux/iommu-dma.h                 |  11 +-
>  include/linux/kmsan.h                     |   9 +-
>  include/trace/events/dma.h                |   9 +-
>  kernel/dma/debug.c                        |  71 ++++---------
>  kernel/dma/debug.h                        |  37 ++-----
>  kernel/dma/direct.c                       |  22 +---
>  kernel/dma/direct.h                       |  52 ++++++----
>  kernel/dma/mapping.c                      | 117 +++++++++++++---------
>  kernel/dma/ops_helpers.c                  |   6 +-
>  mm/hmm.c                                  |  19 ++--
>  mm/kmsan/hooks.c                          |   5 +-
>  rust/kernel/dma.rs                        |   3 +
>  tools/virtio/linux/kmsan.h                |   2 +-
>  26 files changed, 305 insertions(+), 254 deletions(-)

Marek,

So what are the next steps here? This series is pre-requirement for the
VFIO MMIO patches.

Thanks

> 
> -- 
> 2.50.1
> 
> 


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Hello Julien, Volodymyr

On 8/27/25 01:28, Volodymyr Babchuk wrote:
> 
> Hi Milan,
> 
> Milan Djokic  writes:
> 
>> Hello Julien,
>>
>> On 8/13/25 14:11, Julien Grall wrote:
>>> On 13/08/2025 11:04, Milan Djokic wrote:
>>>> Hello Julien,
>>> Hi Milan,
>>>
>>>>
>>>> We have prepared a design document and it will be part of the updated
>>>> patch series (added in docs/design). I'll also extend cover letter with
>>>> details on implementation structure to make review easier.
>>> I would suggest to just iterate on the design document for now.
>>>
>>>> Following is the design document content which will be provided in
>>>> updated patch series:
>>>>
>>>> Design Proposal: Add SMMUv3 Stage-1 Support for XEN Guests
>>>> ==========================================================
>>>>
>>>> Author: Milan Djokic 
>>>> Date:   2025-08-07
>>>> Status: Draft
>>>>
>>>> Introduction
>>>> ------------
>>>>
>>>> The SMMUv3 supports two stages of translation. Each stage of translation
>>>> can be independently enabled. An incoming address is logically
>>>> translated from VA to IPA in stage 1, then the IPA is input to stage 2
>>>> which translates the IPA to the output PA. Stage 1 translation support
>>>> is required to provide isolation between different devices within the OS.
>>>>
>>>> Xen already supports Stage 2 translation but there is no support for
>>>> Stage 1 translation. This design proposal outlines the introduction of
>>>> Stage-1 SMMUv3 support in Xen for ARM guests.
>>>>
>>>> Motivation
>>>> ----------
>>>>
>>>> ARM systems utilizing SMMUv3 require Stage-1 address translation to
>>>> ensure correct and secure DMA behavior inside guests.
>>> Can you clarify what you mean by "correct"? DMA would still work
>>> without
>>> stage-1.
>>
>> Correct in terms of working with guest managed I/O space. I'll
>> rephrase this statement, it seems ambiguous.
>>
>>>>
>>>> This feature enables:
>>>> - Stage-1 translation in guest domain
>>>> - Safe device passthrough under secure memory translation
>>>>
>>>> Design Overview
>>>> ---------------
>>>>
>>>> These changes provide emulated SMMUv3 support:
>>>>
>>>> - SMMUv3 Stage-1 Translation: stage-1 and nested translation support in
>>>>      SMMUv3 driver
>>>> - vIOMMU Abstraction: virtual IOMMU framework for guest Stage-1 handling
>>> So what are you planning to expose to a guest? Is it one vIOMMU per
>>> pIOMMU? Or a single one?
>>
>> Single vIOMMU model is used in this design.
>>
>>> Have you considered the pros/cons for both?
>>>> - Register/Command Emulation: SMMUv3 register emulation and command
>>>>      queue handling
>>>
>>
>> That's a point for consideration.
>> single vIOMMU prevails in terms of less complex implementation and a
>> simple guest iommmu model - single vIOMMU node, one interrupt path,
>> event queue, single set of trap handlers for emulation, etc.
>> Cons for a single vIOMMU model could be less accurate hw
>> representation and a potential bottleneck with one emulated queue and
>> interrupt path.
>> On the other hand, vIOMMU per pIOMMU provides more accurate hw
>> modeling and offers better scalability in case of many IOMMUs in the
>> system, but this comes with more complex emulation logic and device
>> tree, also handling multiple vIOMMUs on guest side.
>> IMO, single vIOMMU model seems like a better option mostly because
>> it's less complex, easier to maintain and debug. Of course, this
>> decision can and should be discussed.
>>
> 
> Well, I am not sure that this is possible, because of StreamID
> allocation. The biggest offender is of course PCI, as each Root PCI
> bridge will require own SMMU instance with own StreamID space. But even
> without PCI you'll need some mechanism to map vStremID to
> , because there will be overlaps in SID space.
> 
> 
> Actually, PCI/vPCI with vSMMU is its own can of worms...
> 
>>> For each pSMMU, we have a single command queue that will receive command
>>> from all the guests. How do you plan to prevent a guest hogging the
>>> command queue?
>>> In addition to that, AFAIU, the size of the virtual command queue is
>>> fixed by the guest rather than Xen. If a guest is filling up the queue
>>> with commands before notifying Xen, how do you plan to ensure we don't
>>> spend too much time in Xen (which is not preemptible)?
>>>
>>
>> We'll have to do a detailed analysis on these scenarios, they are not
>> covered by the design (as well as some others which is clear after
>> your comments). I'll come back with an updated design.
> 
> I think that can be handled akin to hypercall continuation, which is
> used in similar places, like P2M code
> 
> [...]
> 

I have updated vIOMMU design document with additional security topics 
covered and performance impact results. Also added some additional 
explanations for vIOMMU components following your comments.
Updated document content:

===============================================
Design Proposal: Add SMMUv3 Stage-1 Support for XEN Guests
===============================================

:Author:     Milan Djokic 
:Date:       2025-08-07
:Status:     Draft

Introduction
========

The SMMUv3 supports two stages of translation. Each stage of translation 
can be
independently enabled. An incoming address is logically translated from 
VA to
IPA in stage 1, then the IPA is input to stage 2 which translates the IPA to
the output PA. Stage 1 translation support is required to provide 
isolation between different
devices within OS. XEN already supports Stage 2 translation but there is no
support for Stage 1 translation.
This design proposal outlines the introduction of Stage-1 SMMUv3 support 
in Xen for ARM guests.

Motivation
==========

ARM systems utilizing SMMUv3 require stage-1 address translation to 
ensure secure DMA and guest managed I/O memory mappings.
This feature enables:

- Stage-1 translation in guest domain
- Safe device passthrough under secure memory translation

Design Overview
===============

These changes provide emulated SMMUv3 support:

- **SMMUv3 Stage-1 Translation**: stage-1 and nested translation support 
in SMMUv3 driver.
- **vIOMMU Abstraction**: Virtual IOMMU framework for guest stage-1 
handling.
- **Register/Command Emulation**: SMMUv3 register emulation and command 
queue handling.
- **Device Tree Extensions**: Adds `iommus` and virtual SMMUv3 nodes to 
device trees for dom0 and dom0less scenarios.
- **Runtime Configuration**: Introduces a `viommu` boot parameter for 
dynamic enablement.

vIOMMU is exposed to guest as a single device with predefined 
capabilities and commands supported. Single vIOMMU model abstracts the 
details of an actual IOMMU hardware, simplifying usage from the guest 
point of view. Guest OS handles only a single IOMMU, even if multiple 
IOMMU units are available on the host system.

Security Considerations
=======================

**viommu security benefits:**

- Stage-1 translation ensures guest devices cannot perform unauthorized DMA.
- Emulated IOMMU removes guest dependency on IOMMU hardware while 
maintaining domains isolation.


1. Observation:
---------------
Support for Stage-1 translation in SMMUv3 introduces new data structures 
(`s1_cfg` alongside `s2_cfg`) and logic to write both Stage-1 and 
Stage-2 entries in the Stream Table Entry (STE), including an `abort` 
field to handle partial configuration states.

**Risk:**
Without proper handling, a partially applied Stage-1 configuration might 
leave guest DMA mappings in an inconsistent state, potentially enabling 
unauthorized access or causing cross-domain interference.

**Mitigation:** *(Handled by design)*
This feature introduces logic that writes both `s1_cfg` and `s2_cfg` to 
STE and manages the `abort` field-only considering Stage-1 configuration 
if fully attached. This ensures incomplete or invalid guest 
configurations are safely ignored by the hypervisor.

2. Observation:
---------------
Guests can now invalidate Stage-1 caches; invalidation needs forwarding 
to SMMUv3 hardware to maintain coherence.

**Risk:**
Failing to propagate cache invalidation could allow stale mappings, 
enabling access to old mappings and possibly data leakage or misrouting.

**Mitigation:** *(Handled by design)*
This feature ensures that guest-initiated invalidations are correctly 
forwarded to the hardware, preserving IOMMU coherency.

3. Observation:
---------------
This design introduces substantial new functionality, including the 
`vIOMMU` framework, virtual SMMUv3 devices (`vsmmuv3`), command queues, 
event queues, domain management, and Device Tree modifications (e.g., 
`iommus` nodes and `libxl` integration).

**Risk:**
Large feature expansions increase the attack surface—potential for race 
conditions, unchecked command inputs, or Device Tree-based 
misconfigurations.

**Mitigation:**

- Sanity checks and error-handling improvements have been introduced in 
this feature.
- Further audits have to be performed for this feature and its 
dependencies in this area. Currently, feature is marked as *Tech 
Preview* and is self-contained, reducing the risk to unrelated components.

4. Observation:
---------------
The code includes transformations to handle nested translation versus 
standard modes and uses guest-configured command queues (e.g., 
`CMD_CFGI_STE`) and event notifications.

**Risk:**
Malicious or malformed queue commands from guests could bypass 
validation, manipulate SMMUv3 state, or cause Dom0 instability.

**Mitigation:** *(Handled by design)*
Built-in validation of command queue entries and sanitization mechanisms 
ensure only permitted configurations are applied. This is supported via 
additions in `vsmmuv3` and `cmdqueue` handling code.

5. Observation:
---------------
Device Tree modifications enable device assignment and 
configuration—guest DT fragments (e.g., `iommus`) are added via `libxl`.

**Risk:**
Erroneous or malicious Device Tree injection could result in device 
misbinding or guest access to unauthorized hardware.

**Mitigation:**

- `libxl` perform checks of guest configuration and parse only 
predefined dt fragments and nodes, reducing risc.
- The system integrator must ensure correct resource mapping in the 
guest Device Tree (DT) fragments.

6. Observation:
---------------
Introducing optional per-guest enabled features (`viommu` argument in xl 
guest config) means some guests may opt-out.

**Risk:**
Differences between guests with and without `viommu` may cause 
unexpected behavior or privilege drift.

**Mitigation:**
Verify that downgrade paths are safe and well-isolated; ensure missing 
support doesn't cause security issues. Additional audits on emulation 
paths and domains interference need to be performed in a multi-guest 
environment.

7. Observation:
---------------
Guests have the ability to issue Stage-1 IOMMU commands like cache 
invalidation, stream table entries configuration, etc. An adversarial 
guest may issue a high volume of commands in rapid succession.

**Risk**
Excessive commands requests can cause high hypervisor CPU consumption 
and disrupt scheduling, leading to degraded system responsiveness and 
potential denial-of-service scenarios.

**Mitigation**

- Xen credit scheduler limits guest vCPU execution time, securing basic 
guest rate-limiting.
- Batch multiple commands of same type to reduce overhead on the virtual 
SMMUv3 hardware emulation.
- Implement vIOMMU commands execution restart and continuation support

8. Observation:
---------------
Some guest commands issued towards vIOMMU are propagated to pIOMMU 
command queue (e.g. TLB invalidate). For each pIOMMU, only one command 
queue is
available for all domains.

**Risk**
Excessive commands requests from abusive guest can cause flooding of 
physical IOMMU command queue, leading to degraded pIOMMU responsivness 
on commands issued from other guests.

**Mitigation**

- Xen credit scheduler limits guest vCPU execution time, securing basic 
guest rate-limiting.
- Batch commands which should be propagated towards pIOMMU cmd queue and 
enable support for batch execution pause/continuation
- If possible, implement domain penalization by adding a per-domain cost 
counter for vIOMMU/pIOMMU usage.

9. Observation:
---------------
vIOMMU feature includes event queue used for forwarding IOMMU events to 
guest (e.g. translation faults, invalid stream IDs, permission errors). 
A malicious guest can misconfigure its SMMU state or intentionally 
trigger faults with high frequency.

**Risk**
Occurance of IOMMU events with high frequency can cause Xen to flood the 
event queue and disrupt scheduling with high hypervisor CPU load for 
events handling.

**Mitigation**

- Implement fail-safe state by disabling events forwarding when faults 
are occured with high frequency and not processed by guest.
- Batch multiple events of same type to reduce overhead on the virtual 
SMMUv3 hardware emulation.
- Consider disabling event queue for untrusted guests

Performance Impact
==================

With iommu stage-1 and nested translation inclusion, performance 
overhead is introduced comparing to existing, stage-2 only usage in Xen.
Once mappings are established, translations should not introduce 
significant overhead.
Emulated paths may introduce moderate overhead, primarily affecting 
device initialization and event handling.
Performance impact highly depends on target CPU capabilities. Testing is 
performed on cortex-a53 based platform.
Performance is mostly impacted by emulated vIOMMU operations, results 
shown in the following table.

+-------------------------------+---------------------------------+
| vIOMMU Operation              | Execution time in guest         |
+===============================+=================================+
| Reg read                      | median: 30μs, worst-case: 250μs |
+-------------------------------+---------------------------------+
| Reg write                     | median: 35μs, worst-case: 280μs |
+-------------------------------+---------------------------------+
| Invalidate TLB                | median: 90μs, worst-case: 1ms+  |
+-------------------------------+---------------------------------+
| Invalidate STE                | median: 450μs worst_case: 7ms+  |
+-------------------------------+---------------------------------+

With vIOMMU exposed to guest, guest OS has to initialize IOMMU device 
and configure stage-1 mappings for devices attached to it.
Following table shows initialization stages which impact stage-1 enabled 
guest boot time and compares it with stage-1 disabled guest.

"NOTE: Device probe execution time varies significantly depending on 
device complexity. virtio-gpu was selected as a test case due to its 
extensive use of dynamic DMA allocations and IOMMU mappings, making it a 
suitable candidate for benchmarking stage-1 vIOMMU behavior."

+---------------------+-----------------------+------------------------+
| Stage               | Stage-1 Enabled Guest | Stage-1 Disabled Guest |
+=====================+=======================+========================+
| IOMMU Init          | ~25ms                 | /                      |
+---------------------+-----------------------+------------------------+
| Dev Attach / Mapping| ~220ms                | ~200ms                 |
+---------------------+-----------------------+------------------------+

For devices configured with dynamic DMA mappings, DMA allocate/map/unmap 
operations performance is also impacted on stage-1 enabled guests.
Dynamic DMA mapping operation issues emulated IOMMU functions like mmio 
write/read and TLB invalidations.
As a reference, following table shows performance results for runtime 
dma operations for virtio-gpu device.

+---------------+-------------------------+----------------------------+
| DMA Op        | Stage-1 Enabled Guest   | Stage-1 Disabled Guest     |
+===============+=========================+============================+
| dma_alloc     | median: 27μs, worst: 7ms| median: 2.5μs, worst: 360μs|
+---------------+-------------------------+----------------------------+
| dma_free      | median: 1ms, worst: 14ms| median: 2.2μs, worst: 85μs |
+---------------+-------------------------+----------------------------+
| dma_map       | median: 25μs, worst: 7ms| median: 1.5μs, worst: 336μs|
+---------------+-------------------------+----------------------------+
| dma_unmap     | median: 1ms, worst: 13ms| median: 1.3μs, worst: 65μs |
+---------------+-------------------------+----------------------------+

Testing
============

- QEMU-based ARM system tests for Stage-1 translation and nested 
virtualization.
- Actual hardware validation on platforms such as Renesas to ensure 
compatibility with real SMMUv3 implementations.
- Unit/Functional tests validating correct translations (not implemented).

Migration and Compatibility
===========================

This optional feature defaults to disabled (`viommu=""`) for backward 
compatibility.

References
==========

- Original feature implemented by Rahul Singh: 
https://patchwork.kernel.org/project/xen-devel/cover/cover.1669888522.git.rahul.singh@arm.com/ 

- SMMUv3 architecture documentation
- Existing vIOMMU code patterns








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Date: Thu, 28 Aug 2025 13:00:15 +0100
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User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v4 01/12] xen/arm: gicv3: refactor obtaining GIC addresses
 for common operations
Content-Language: en-GB
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: "olekstysh@gmail.com" ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <5f511d386c7f20b09106aa0202e0989477eff498.1756317702.git.leonid_komarianskyi@epam.com>
From: Julien Grall 
In-Reply-To: <5f511d386c7f20b09106aa0202e0989477eff498.1756317702.git.leonid_komarianskyi@epam.com>
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Hi Leonid,

On 27/08/2025 19:24, Leonid Komarianskyi wrote:
> Currently, many common functions perform the same operations to calculate
> GIC register addresses. This patch consolidates the similar code into
> a separate helper function to improve maintainability and reduce duplication.
> This refactoring also simplifies the implementation of eSPI support in future
> changes.
> 
> Signed-off-by: Leonid Komarianskyi 
> Reviewed-by: Volodymyr Babchuk 
> 
> ---
> Changes in V4:
> - no changes
> 
> Changes in V3:
> - changed panic() in get_addr_by_offset() to printing warning and
>    ASSERT_UNREACHABLE()
> - added verification of return pointer from get_addr_by_offset() in the
>    callers
> - moved invocation of get_addr_by_offset() from spinlock guards, since
>    it is not necessarry
> - added RB from Volodymyr Babchuk

Procces remark, here you said the Reviewed-by from Volodymyr was added 
in v3. However, given the changes you made this should have been 
invalidated (reviewed-by means the person read the code and confirmed it 
is correct).

I see Volodymyr confirmed his reviewed-by on v3. So no issue, but this 
should have been clarified in the changelog.

> 
> Changes in V2:
> - no changes
> ---
>   xen/arch/arm/gic-v3.c          | 114 +++++++++++++++++++++++----------
>   xen/arch/arm/include/asm/irq.h |   1 +
>   2 files changed, 81 insertions(+), 34 deletions(-)
> 
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index cd3e1acf79..a959fefebe 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -445,17 +445,67 @@ static void gicv3_dump_state(const struct vcpu *v)
>       }
>   }
>   
> +static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
> +{
> +    switch ( irqd->irq )
> +    {
> +    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD_RDIST_SGI_BASE + offset);
> +        case GICD_ICFGR:
> +            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
> +        case GICD_IPRIORITYR:
> +            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
> +        default:
> +            break;
> +        }
> +    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD + offset + (irqd->irq / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTER + irqd->irq * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYR + irqd->irq);
> +        default:
> +            break;
> +        }
> +    default:
> +        break;
> +    }
> +
> +    /* Something went wrong, we shouldn't be able to reach here */
> +    printk(XENLOG_WARNING "GICv3: WARNING: Invalid offset 0x%x for IRQ#%d",

NIT: I am not expecting the interrupt to be < 0. So it would be 
preferable to use %u.

Acked-by: Julien Grall 

Cheers,

-- 
Julien Grall



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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[PATCH]=20hvmloader:=20Update=20to=20SMBIOS=202.6?=
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To: "Andrew Cooper" , xen-devel@lists.xenproject.org
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Le 28/08/2025 =C3=A0 12:24, Andrew Cooper a =C3=A9crit=C2=A0:
> I'd be tempted to be rather more explicit.
> 
> diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
> index 82b9c05a76b7..f1592dc059e2 100644
> --- a/xen/include/public/xen.h
> +++ b/xen/include/public/xen.h
> @@ -973,6 +973,13 @@ typedef struct dom0_vga_console_info {
>  =C2=A0#define xen_vga_console_info dom0_vga_console_info
>  =C2=A0#define xen_vga_console_info_t dom0_vga_console_info_t
>   
> +/*
> + * The domain handle is chosen by the toolstack, and intended to hold a =
UUID
> + * conforming to RFC 9562 (i.e. big endian).
> + *
> + * Certain cases (e.g. SMBios) transform it to a Microsoft GUID (little
> + * endian) for presentation to the guest.
> + */
>  =C2=A0typedef uint8_t xen_domain_handle_t[16];
>   
>  =C2=A0__DEFINE_XEN_GUEST_HANDLE(uint8,=C2=A0 uint8_t);

I'm ok with it, although it sounds a bit like this UUID could be a 
little endian GUID in some cases.


Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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Subject: Re: [RFC PATCH v1 05/10] pmu.h: introduce a stacktrace area
To: =?UTF-8?B?RWR3aW4gVMO2csO2aw==?= 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Volodymyr Babchuk , andriy.sultanov@vates.tech,
 boris.ostrovsky@oracle.com, xen-devel@lists.xenproject.org
References: 
 <49cbbacdc5f4fec624ae164a01eaa574aa771854.1753372928.git.edwin.torok@cloud.com>
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In-Reply-To: <49cbbacdc5f4fec624ae164a01eaa574aa771854.1753372928.git.edwin.torok@cloud.com>
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On 25.07.2025 17:06, Edwin Török wrote:
> The guest always allocates a full page that is mapped for 'struct
> xen_pmu_data' (there is no smaller mapping granularity).
> 
> The existing struct contains a flexible array member that is used to
> store architectural performance counters on Intel (their number is
> dynamically determined from CPUID).
> 
> AFAICT their number is currently limited to 32 due to the bitmap in the
> CPUID only having 32 bits defined for this, although the cpuid has 8
> bits reserved to specify the number of these counters, so this may grow.
> 
> For backwards compatibility and to leave as much room for future growth
> in these counters as possible: the newly introduced hypervisor
> stacktrace area will be stored at the end of the page.
> 
> Conceptually this would've been:
> ```
> struct xen_pmu_data_v2 {
>     union {
>         struct xen_pmu_data v1;
>         uint8_t pad[PAGE_SIZE - sizeof(struct xen_pmu_hv_stacktrace)];
>     };
>     struct xen_pmu_hv_stacktrace pmu_stack;
> };
> ```
> 
> But that is not valid C due to the flexible array member in v1.

And I fear it's not a good interface anyway. What's wrong with the caller
dedicating another page to holding the stack trace related data?

> There is code duplication in 'struct xen_pmu_arch_guest',
> but xlat.h checker fails if I try to reuse that in the definition of
> xen_pmu_arch_t.

What exactly is this referring to?

> --- a/xen/include/public/arch-x86/pmu.h
> +++ b/xen/include/public/arch-x86/pmu.h
> @@ -74,6 +74,23 @@ DEFINE_XEN_GUEST_HANDLE(xen_pmu_regs_t);
>  #define PMU_SAMPLE_REAL    (1<<2) /* Sample is from realmode */
>  #define PMU_SAMPLE_PV      (1<<3) /* Sample from a PV guest */
>  
> +/*
> + * Architecture-specific information describing the state of the guest at
> + * the time of a PMU interrupt.
> + */
> +struct xen_pmu_arch_guest {
> +    union {
> +        /*
> +         * Processor's registers at the time of interrupt.
> +         * WO for hypervisor, RO for guests.
> +         */
> +        xen_pmu_regs_t regs;

How's this related to stack traces?

> @@ -129,67 +146,86 @@ struct xen_pmu_arch {
>  typedef struct xen_pmu_arch xen_pmu_arch_t;
>  DEFINE_XEN_GUEST_HANDLE(xen_pmu_arch_t);
>  
> +

Stray double blank lines.

>  /* Memory layout:
> -*                ╭─────────────────────╮
> -*                │ struct xen_pmu_data │
> -* â•’â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•§â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•§â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•• â—â•®
> -* │ vcpu_id                                                    │  │
> -* ├────────────────────────────────────────────────────────────┤  │
> -* │ pcpu_id                                                    │  │
> -* ├────────────────────────────────────────────────────────────┤  │
> -* │ domain_id                                                  │  │
> -* ├────────────────────────────────────────────────────────────┤  │
> -* │██pad███████████████████████████████████████████████████████│  │
> -* â•žâ•â•â•â•â•¤â•â•¤â•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> -* │ pmu│ │ r │ regs             │██pad█████████████████████████│  │
> -* ├────╯ ├───╯ (xen or guest)   │██████████████████████████████│  │
> -* │      â•žâ•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•§â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> -* │      │ pmu_flags                                           │  │
> -* │      â•žâ•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> -* │      │ l │ lapic_lvtpc        │████████████████████████████│  │
> -* │      ├───╯ ███████████████████│██pad███████████████████████│  │
> -* │      │     ███████████████████│████████████████████████████│  │
> -* │      â•žâ•â•â•â•¤â•â•¤â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•¤â•â•â•â•â•ªâ•â•â•â•â•¤â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> -* │      │ c │ │       │ amd │    │    │ intel │         │█████│  │
> -* │      ├───┘ │       ╰─────╯    │    ╰───────╯         │█████│  │
> -* │      │     │ counter          │ fixed_counters       │█████│  │
> -* │      │     ├──────────────────┼──────────────────────┤█████│  │
> -* │      │     │ ctrls            │ arch_counters        │█████│  │
> -* │      │     â•žâ•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•¤â•â•â•â”œâ”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”¤â–ˆâ–ˆâ–ˆâ–ˆâ–ˆâ”‚  │
> -* │      │     │     │ regs[] │  ┆│ global_ctrl          │█████│  │
> -* │      │     │     └────────╯  ┆├──────────────────────┤█████│  │
> -* │      │     │struct           ┆│ global_ovf_ctrl      │█████│  │
> -* │      │     │xen_pmu_cntr_pair┆├──────────────────────┤█████│  │
> -* │      │     │[counters]       ┆│ global_status        │█████│  │
> -* │      │     │                 ┆├──────────────────────┤█████│  │
> -* │      │     │                 ┆│ fixed_ctrl           │█████│  │
> -* │      │     │                 ┆├──────────────────────┤█████│  │
> -* │      │     │                 ┆│ ds_area              │█████│  │
> -* │      │     │                 ┆├──────────────────────┤█████│  │
> -* │      │     │                 ┆│ pebs_enable          │█pad█│  │
> -* │      │     │                 ┆├──────────────────────┤█████│  │
> -* │      │     │                 ▽│ debugctl             │█████│  │
> -* │      │     │██████████████████╞â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•¡â–ˆâ–ˆâ–ˆâ–ˆâ–ˆâ”‚  │
> -* │      │     │██████████████████│       │ regs[] │ ┆[0]│█████│  │
> -* │      │     │██████████████████│       └────────╯ ┆   │█████│  │
> -* │      │     │██████████████████│ uint64_t         ┆   │█████│  │
> -* │      │     │██████████████████│ [fixed_counters] ┆   │█████│  │
> -* │      │     │██████████████████│                  ┆   │█████│  │
> -* │      │     │██████████████████│                  ┆   │█████│  │
> -* │      │     │██████████████████│ ─────────────────┆   │█████│  │
> -* │      │     │██████████████████│  struct          ┆   │█████│  │
> -* │      │     │██████████████████│ xen_pmu_cntr_pair┆   │█████│  │
> -* │      │     ╘â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡ [arch_counters]  ┆   â•žâ•â•â•â•â•â•¡  │
> -* │      │                        │                  ┆   │     │  │
> -* │      │                        │                  ▽   │     │  │
> -* │      │                        ╘â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•›     │  │
> -* │      ╘â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> -* â•žâ•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> -* │████████████████████████████████████████████████████████████│  │
> -* ┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆  ┆
> -* ┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆  ┆
> -* │████████████████████████████████████████████████████████████│  │ PAGE_SIZE
> -* ╘â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•› â—╯
> + *                ╭─────────────────────╮
> + *                │ struct xen_pmu_data │
> + * â•’â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•§â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•§â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•• â—â•®
> + * │ vcpu_id                                                    │  │
> + * ├────────────────────────────────────────────────────────────┤  │
> + * │ pcpu_id                                                    │  │
> + * ├────────────────────────────────────────────────────────────┤  │
> + * │ domain_id                                                  │  │
> + * ├────────────────────────────────────────────────────────────┤  │
> + * │██pad███████████████████████████████████████████████████████│  │
> + * â•žâ•â•â•â•â•¤â•â•¤â•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> + * │ pmu│ │ r │ regs             │██pad█████████████████████████│  │
> + * ├────╯ ├───╯ (xen or guest)   │██████████████████████████████│  │
> + * │      â•žâ•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•§â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> + * │      │ pmu_flags                                           │  │
> + * │      â•žâ•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> + * │      │ l │ lapic_lvtpc        │████████████████████████████│  │
> + * │      ├───╯ ███████████████████│██pad███████████████████████│  │
> + * │      │     ███████████████████│████████████████████████████│  │
> + * │      â•žâ•â•â•â•¤â•â•¤â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•¤â•â•â•â•â•ªâ•â•â•â•â•¤â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> + * │      │ c │ │       │ amd │    │    │ intel │         │█████│  │
> + * │      ├───┘ │       ╰─────╯    │    ╰───────╯         │█████│  │
> + * │      │     │ counter          │ fixed_counters       │█████│  │
> + * │      │     ├──────────────────┼──────────────────────┤█████│  │
> + * │      │     │ ctrls            │ arch_counters        │█████│  │
> + * │      │     â•žâ•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•¤â•â•â•â”œâ”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”€â”¤â–ˆâ–ˆâ–ˆâ–ˆâ–ˆâ”‚  │
> + * │      │     │     │ regs[] │  ┆│ global_ctrl          │█████│  │
> + * │      │     │     └────────╯  ┆├──────────────────────┤█████│  │
> + * │      │     │struct           ┆│ global_ovf_ctrl      │█████│  │
> + * │      │     │xen_pmu_cntr_pair┆├──────────────────────┤█████│  │
> + * │      │     │[counters]       ┆│ global_status        │█████│  │
> + * │      │     │                 ┆├──────────────────────┤█████│  │
> + * │      │     │                 ┆│ fixed_ctrl           │█████│  │
> + * │      │     │                 ┆├──────────────────────┤█████│  │
> + * │      │     │                 ┆│ ds_area              │█████│  │
> + * │      │     │                 ┆├──────────────────────┤█████│  │
> + * │      │     │                 ┆│ pebs_enable          │█pad█│  │
> + * │      │     │                 ┆├──────────────────────┤█████│  │
> + * │      │     │                 ▽│ debugctl             │█████│  │
> + * │      │     │██████████████████╞â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•â•â•â•¤â•â•â•â•â•â•¡â–ˆâ–ˆâ–ˆâ–ˆâ–ˆâ”‚  │
> + * │      │     │██████████████████│       │ regs[] │ ┆[0]│█████│  │
> + * │      │     │██████████████████│       └────────╯ ┆   │█████│  │
> + * │      │     │██████████████████│ uint64_t         ┆   │█████│  │
> + * │      │     │██████████████████│ [fixed_counters] ┆   │█████│  │
> + * │      │     │██████████████████│                  ┆   │█████│  │
> + * │      │     │██████████████████│                  ┆   │█████│  │
> + * │      │     │██████████████████│ ─────────────────┆   │█████│  │
> + * │      │     │██████████████████│  struct          ┆   │█████│  │
> + * │      │     │██████████████████│ xen_pmu_cntr_pair┆   │█████│  │
> + * │      │     ╘â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡ [arch_counters]  ┆   â•žâ•â•â•â•â•â•¡  │
> + * │      │                        │                  ┆   │     │  │
> + * │      │                        │                  ▽   │     │  │
> + * │      │                        ╘â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•›     │  │
> + * │      ╘â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> + * â•žâ•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•â•¡  │
> + * │████████████████████████████████████████████████████████████│  │
> + * ┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆  ┆
> + * ┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆┆  ┆
> + * │████████████████████████████████████████████████████████████│  │
> + * |############################################################|  |
> + * |##########.------------------------------.##################|  |
> + * |##########| struct xen_pmu_hv_stacktrace |##################|  |
> + * +==========+==============================+==================+  |
> + * |                              ^ [stacktrace_nr-1]           |  |
> + * |                              :                             |  |
> + * | stacktrace[stacktrace_nr]    : [0]                         |  |
> + * +------------------------------------------------------------+  |
> + * | stacktrace_nr                                              |  |
> + * +------------------------------------------------------------+  |
> + * | guest_domain_id                                            |  |
> + * +------------------------------------------------------------+  |
> + * |##pad#######################################################|  |
> + * +=======+=+===+==================+===========================+  |
> + * | guest | | r | regs             |##pad######################|  |
> + * +-------. +---. (xen or guest)   |###########################|  |
> + * |         +======================+===========================+  |
> + * |         |##pad2############################################|  | PAGE_SIZE
> + * +=========+==================================================+ <.
>  */
>  
>  #endif /* __XEN_PUBLIC_ARCH_X86_PMU_H__ */
> @@ -202,4 +238,3 @@ DEFINE_XEN_GUEST_HANDLE(xen_pmu_arch_t);
>   * indent-tabs-mode: nil
>   * End:
>   */
> -

Stray change?

> @@ -120,6 +120,40 @@ struct xen_pmu_data {
>      xen_pmu_arch_t pmu;
>  };
>  
> +/* stacktrace entry populated from the end,
> + * so stacktrace_nr == 1, means that stacktrace[PMU_MAX_STACKTRCE-1] is valid.
> + * This is done, so that PMU_MAX_STACKTRACE can be changed in the future, without breaking the ABI.
> + * The struct itself (and thus the stacktrace_nr field) will always be placed at the end of a page.
> + *
> + * See arch-x86/pmu.h for an example memory layout on x86.
> + *
> + * */
> +#define PMU_MAX_STACKTRACE 127
> +
> +/* WO for hypervisor, RO for guest */
> +struct xen_pmu_hv_stacktrace {
> +    uint64_t stacktrace[PMU_MAX_STACKTRACE];
> +    uint64_t stacktrace_nr;
> +
> +    /* Like xen_pmu_data.domain_id, but instead of DOMID_XEN always contains the
> +     * domain that was interrupted (DOMID_SELF if it matches the sampling
> +     * domain).
> +     */
> +    domid_t guest_domain_id;

How's this related to stack traces? And how would it help associating back
what vCPU the data belongs to?

> +    uint8_t pad[6];
> +
> +    /* When xen_pmu_data.domain_id == DOMID_XEN, this will contain
> +    * the registers of the guest that was interrupted.
> +    * This is useful for Dom0 kernel stacktraces, even if the interrupt
> +    * arrives while in Xen.
> +    * */

Nit: Indentation.

Jan


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From: Leonid Komarianskyi 
To: Volodymyr Babchuk 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Anthony PERARD
	
Subject: Re: [PATCH v4 11/12] doc/man: update description for nr_spis with
 eSPI
Thread-Topic: [PATCH v4 11/12] doc/man: update description for nr_spis with
 eSPI
Thread-Index: AQHcF3/Q0bamE1jhy06ZtBrEohbyn7R3+QgA
Date: Thu, 28 Aug 2025 12:05:16 +0000
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Subject: Re: [PATCH v3 4/5] arm/mpu: Implement ioremap_attr for MPU
To: Hari Limaye , 
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	Julien Grall , Bertrand Marquis ,
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 <53c6aa61bc0cefce369ffc3a9ff5a7060b5f4b20.1756379422.git.hari.limaye@arm.com>
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On 28/08/2025 13:12, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Introduce helpers (un)map_mm_range() in order to allow the transient
> mapping of a range of memory, and use these to implement the function
> `ioremap_attr` for MPU systems.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
Reviewed-by: Michal Orzel 

~Michal



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Subject: Re: [PATCH v8 0/8] amd-cppc CPU Performance Scaling Driver
To: Penny Zheng 
Cc: ray.huang@amd.com, Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini , Juergen Gross
 , xen-devel@lists.xenproject.org
References: <20250828100306.1776031-1-Penny.Zheng@amd.com>
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From: Jan Beulich 
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On 28.08.2025 12:02, Penny Zheng wrote:
> amd-cppc is the AMD CPU performance scaling driver that introduces a
> new CPU frequency control mechanism on modern AMD APU and CPU series in
> Xen. The new mechanism is based on Collaborative Processor Performance
> Control (CPPC) which provides finer grain frequency management than
> legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using
> the ACPI P-states driver to manage CPU frequency and clocks with
> switching only in 3 P-states. CPPC replaces the ACPI P-states controls
> and allows a flexible, low-latency interface for Xen to directly
> communicate the performance hints to hardware.
> 
> amd_cppc driver has 2 operation modes: autonomous (active) mode,
> and non-autonomous (passive) mode. We register different CPUFreq driver
> for different modes, "amd-cppc" for passive mode and "amd-cppc-epp"
> for active mode.
> 
> The passive mode leverages common governors such as *ondemand*,
> *performance*, etc, to manage the performance tuning. While the active mode
> uses epp to provides a hint to the hardware if software wants to bias
> toward performance (0x0) or energy efficiency (0xff). CPPC power algorithm
> in hardware will automatically calculate the runtime workload and adjust the
> realtime cpu cores frequency according to the power supply and thermal, core
> voltage and some other hardware conditions.
> 
> amd-cppc is enabled on passive mode with a top-level `cpufreq=amd-cppc` option,
> while users add extra `active` flag to select active mode.
> 
> With `cpufreq=amd-cppc,active`, we did a 60s sampling test to see the CPU
> frequency change, through tweaking the energy_perf preference from
> `xenpm set-cpufreq-cppc powersave` to `xenpm set-cpufreq-cppc performance`.
> The outputs are as follows:
> ```
> Setting CPU in powersave mode
> Sampling and Outputs:
>   Avg freq      580000 KHz
>   Avg freq      580000 KHz
>   Avg freq      580000 KHz
> Setting CPU in performance mode
> Sampling and Outputs:
>   Avg freq      4640000 KHz
>   Avg freq      4220000 KHz
>   Avg freq      4640000 KHz
> ```
> 
> Penny Zheng (8):
>   xen/cpufreq: introduce new sub-hypercall to propagate CPPC data
>   xen/cpufreq: introduce "cpufreq=amd-cppc" xen cmdline and amd-cppc
>     driver
>   xen/cpufreq: implement amd-cppc driver for CPPC in passive mode
>   xen/cpufreq: implement amd-cppc-epp driver for CPPC in active mode
>   xen/cpufreq: get performance policy from governor set via xenpm
>   tools/cpufreq: extract CPPC para from cpufreq para
>   xen/cpufreq: bypass governor-related para for amd-cppc-epp
>   xen/cpufreq: Adapt SET/GET_CPUFREQ_CPPC xen_sysctl_pm_op for amd-cppc
>     driver
> 
>  docs/misc/xen-command-line.pandoc         |  14 +-
>  tools/include/xenctrl.h                   |   3 +-
>  tools/libs/ctrl/xc_pm.c                   |  25 +-
>  tools/misc/xenpm.c                        |  94 ++-
>  xen/arch/x86/acpi/cpufreq/Makefile        |   1 +
>  xen/arch/x86/acpi/cpufreq/amd-cppc.c      | 766 ++++++++++++++++++++++
>  xen/arch/x86/acpi/cpufreq/cpufreq.c       |  69 +-
>  xen/arch/x86/cpu/amd.c                    |   8 +-
>  xen/arch/x86/include/asm/amd.h            |   2 +
>  xen/arch/x86/include/asm/msr-index.h      |   6 +
>  xen/arch/x86/platform_hypercall.c         |  19 +
>  xen/arch/x86/x86_64/cpufreq.c             |  19 +
>  xen/arch/x86/x86_64/platform_hypercall.c  |   3 +
>  xen/drivers/acpi/pm-op.c                  |  68 +-
>  xen/drivers/acpi/pmstat.c                 |   4 +
>  xen/drivers/cpufreq/cpufreq.c             | 137 +++-
>  xen/drivers/cpufreq/utility.c             |  15 +
>  xen/include/acpi/cpufreq/cpufreq.h        |  40 +-
>  xen/include/acpi/cpufreq/processor_perf.h |  14 +-
>  xen/include/public/platform.h             |  26 +
>  xen/include/public/sysctl.h               |   5 +-
>  xen/include/xen/pmstat.h                  |   5 +
>  xen/include/xlat.lst                      |   1 +
>  23 files changed, 1283 insertions(+), 61 deletions(-)
>  create mode 100644 xen/arch/x86/acpi/cpufreq/amd-cppc.c

Oh, and - what is still missing is a CHANGELOG.md entry.

Jan


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Date: Thu, 28 Aug 2025 13:10:46 +0100
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v4 02/12] xen/arm: gic: implement helper functions for
 INTID checks
Content-Language: en-GB
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: "olekstysh@gmail.com" ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <684757e6710826200bcc153e4c711b27483ee796.1756317702.git.leonid_komarianskyi@epam.com>
From: Julien Grall 
In-Reply-To: <684757e6710826200bcc153e4c711b27483ee796.1756317702.git.leonid_komarianskyi@epam.com>
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Hi Leonid,

On 27/08/2025 19:24, Leonid Komarianskyi wrote:
> Introduced two new helper functions: gic_is_valid_line and
> gic_is_spi. The first function helps determine whether an IRQ
> number is less than the number of lines supported by hardware. The
> second function additionally checks if the IRQ number falls within the
> SPI range. Also, updated the appropriate checks to use these new helper
> functions.
> 
> The current checks for the real GIC are very similar to those for the
> vGIC but serve a different purpose. For GIC-related code, the interrupt
> numbers should be validated based on whether the hardware can operate
> with such interrupts. On the other hand, for the vGIC, the indexes must
> also be verified to ensure they are available for a specific domain. The
> first reason for introducing these helper functions is to avoid
> potential confusion with vGIC-related checks. The second reason is to
> consolidate similar code into separate functions, which can be more
> easily extended by additional conditions, e.g., when implementing
> extended SPI interrupts.
> 
> The changes, which replace open-coded checks with the use of the new
> helper functions, do not introduce any functional changes, as the helper
> functions follow the current IRQ index verification logic.
> 
> Signed-off-by: Leonid Komarianskyi 
> Reviewed-by: Volodymyr Babchuk 

With one remark below:

Acked-by: Julien Grall 

> ---
> Changes in V4:
> - removed redundant parentheses
> - added reviewed-by from Volodymyr Babchuk
> 
> Changes in V3:
> - renamed gic_is_valid_irq to gic_is_valid_line and gic_is_shared_irq to
>    gic_is_spi
> - updated commit message
> 
> Changes in V2:
> - introduced this patch
> 
> Changes for V4:
> 
> Changes in V4:
> - removed redundant parentheses
> - added reviewed-by from Volodymyr Babchuk
> ---
>   xen/arch/arm/gic.c             | 2 +-
>   xen/arch/arm/include/asm/gic.h | 9 +++++++++
>   xen/arch/arm/irq.c             | 2 +-
>   3 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
> index e80fe0ca24..9220eef6ea 100644
> --- a/xen/arch/arm/gic.c
> +++ b/xen/arch/arm/gic.c
> @@ -111,7 +111,7 @@ static void gic_set_irq_priority(struct irq_desc *desc, unsigned int priority)
>   void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority)
>   {
>       ASSERT(priority <= 0xff);     /* Only 8 bits of priority */
> -    ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that don't exist */
> +    ASSERT(gic_is_valid_line(desc->irq));/* Can't route interrupts that don't exist */

As you are touching the line. It is over 80 characters. Can you move the 
command in a separate line?

>       ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
>       ASSERT(spin_is_locked(&desc->lock));

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v4 03/12] xen/arm: vgic: implement helper functions for
 virq checks
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To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: "olekstysh@gmail.com" ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <65b148aea56b1a35fa061b0d8284584da97153a9.1756317702.git.leonid_komarianskyi@epam.com>
From: Julien Grall 
In-Reply-To: <65b148aea56b1a35fa061b0d8284584da97153a9.1756317702.git.leonid_komarianskyi@epam.com>
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Hi Leonid,

On 27/08/2025 19:24, Leonid Komarianskyi wrote:
> Introduced two new helper functions for vGIC: vgic_is_valid_line and
> vgic_is_spi. The functions are similar to the newly introduced
> gic_is_valid_line and gic_is_spi, but they verify whether a vIRQ
> is available for a specific domain, while GIC-specific functions
> validate INTIDs for the real GIC hardware. For example, the GIC may
> support all 992 SPI lines, but the domain may use only some part of them
> (e.g., 640), depending on the highest IRQ number defined in the domain
> configuration. Therefore, for vGIC-related code and checks, the
> appropriate functions should be used. Also, updated the appropriate
> checks to use these new helper functions.
> 
> The purpose of introducing new helper functions for vGIC is essentially
> the same as for GIC: to avoid potential confusion with GIC-related
> checks and to consolidate similar code into separate functions, which
> can be more easily extended by additional conditions, e.g., when
> implementing extended SPI interrupts.
> 
> Only the validation change in vgic_inject_irq may affect existing
> functionality, as it currently checks whether the vIRQ is less than or
> equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
> first SPI), the check should behave consistently with similar logic in
> other places and should check if the vIRQ number is less than
> vgic_num_irqs. The remaining changes, which replace open-coded checks
> with the use of these new helper functions, do not introduce any
> functional changes, as the helper functions follow the current vIRQ
> index verification logic.
> 
> Signed-off-by: Leonid Komarianskyi 

Acked-by: Julien Grall 

Cheers,

-- 
Julien Grall



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Subject: Re: [RFC PATCH 1/9] x86/hvm: Use direct structures instead of guest
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To: Teddy Astie 
Cc: Andrew Cooper ,
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On 21.08.2025 17:25, Teddy Astie wrote:
> Make these functions work with hypervisor-owned pointer rather than
> guest handles, so the function parameters don't have to live in guest memory.

This is odd to read - the function parameters (arguments) didn't live in
guest memory before either.

> No functional changes intended.
> 
> Signed-off-by: Teddy Astie 
> ---
>  xen/arch/x86/hvm/hvm.c | 126 +++++++++++++++++++++++------------------
>  1 file changed, 70 insertions(+), 56 deletions(-)
> 
> diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
> index 56c7de3977..8bf59c63fe 100644
> --- a/xen/arch/x86/hvm/hvm.c
> +++ b/xen/arch/x86/hvm/hvm.c
> @@ -4142,19 +4142,14 @@ static int hvmop_flush_tlb_all(void)
>      return paging_flush_tlb(NULL) ? 0 : -ERESTART;
>  }
>  
> -static int hvmop_set_evtchn_upcall_vector(
> -    XEN_GUEST_HANDLE_PARAM(xen_hvm_evtchn_upcall_vector_t) uop)
> +static int hvmop_set_evtchn_upcall_vector(xen_hvm_evtchn_upcall_vector_t op)

Please can we avoid passing structures by value?

More generally: This one-by-one adjustment is what I'd really like to avoid
with any new interface. It would be far better if ...

>  {
> -    xen_hvm_evtchn_upcall_vector_t op;
>      struct domain *d = current->domain;
>      struct vcpu *v;
>  
>      if ( !is_hvm_domain(d) )
>          return -EINVAL;
>  
> -    if ( copy_from_guest(&op, uop, 1) )
> -        return -EFAULT;

... copy_from_guest() could transparantly handle both cases (virtual and
physical addresses being used). And yes, this would exclude an "everying in
registers" approach.

> @@ -5115,28 +5087,70 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE_PARAM(void) arg)
>      switch ( op )
>      {
>      case HVMOP_set_evtchn_upcall_vector:
> -        rc = hvmop_set_evtchn_upcall_vector(
> -            guest_handle_cast(arg, xen_hvm_evtchn_upcall_vector_t));
> +    {
> +        struct xen_hvm_evtchn_upcall_vector op;
> +
> +        if ( copy_from_guest(&op, arg, 1) )
> +        {
> +            rc = -EFAULT;
> +            break;
> +        }
> +
> +        rc = hvmop_set_evtchn_upcall_vector(op);
>          break;
> +    }
>      
>      case HVMOP_set_param:
> -        rc = hvmop_set_param(
> -            guest_handle_cast(arg, xen_hvm_param_t));
> +    {
> +        struct xen_hvm_param op;
> +        
> +        if ( copy_from_guest(&op, arg, 1) )
> +        {
> +            rc = -EFAULT;
> +            break;
> +        }
> +
> +        rc = hvmop_set_param(op);
>          break;
> +    }
>  
>      case HVMOP_get_param:
> -        rc = hvmop_get_param(
> -            guest_handle_cast(arg, xen_hvm_param_t));
> +    {
> +        struct xen_hvm_param op;
> +        
> +        if ( copy_from_guest(&op, arg, 1) )
> +        {
> +            rc = -EFAULT;
> +            break;
> +        }
> +
> +        rc = hvmop_get_param(&op);
> +
> +        if ( !rc && copy_to_guest(arg, &op, 1) )

Why would the original __copy_to_guest() need to change to copy_to_guest()?

Jan


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Subject: Re: [RFC PATCH 2/9] common: Isolate XENVER_get_features into a
 separate function
To: Teddy Astie 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
References: 
 <0bbc0f2df1853bb60f4e93c55d1a0953c6a72496.1755785258.git.teddy.astie@vates.tech>
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From: Jan Beulich 
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On 21.08.2025 17:25, Teddy Astie wrote:
> Make do_xen_version more readable by moving the main XENVER_get_features
> into a separate function.

I can't spot much of a readability gain, to be honest.

> --- a/xen/common/kernel.c
> +++ b/xen/common/kernel.c
> @@ -569,6 +569,50 @@ static long xenver_varbuf_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
>      return sz;
>  }
>  
> +static long xenver_get_features(struct domain *d, uint32_t submap_idx, uint32_t *submap)

Why "long", when you only return "int" -errno values?

Speaking of "long", why such long a line?

Jan


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Subject: Re: [RFC PATCH 3/9] common/grant_table: Use direct structures instead
 of guest handles
To: Teddy Astie 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , xen-devel@lists.xenproject.org
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On 21.08.2025 17:25, Teddy Astie wrote:
> Make these functions work with hypervisor-owned pointer rather than
> guest handles, so the function parameters don't have to live in guest memory.
> 
> No functional changes.
> 
> Signed-off-by: Teddy Astie 

Unlike title/description suggest, this only touched two out of many sub-ops.
As others don't lend themselves to your goal, that makes things overall
inconsistent, for a questionable gain.

Jan


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Subject: Re: [PATCH v4 03/12] xen/arm: vgic: implement helper functions for
 virq checks
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
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 <65b148aea56b1a35fa061b0d8284584da97153a9.1756317702.git.leonid_komarianskyi@epam.com>
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From: Oleksandr Tyshchenko 
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On 27.08.25 21:24, Leonid Komarianskyi wrote:

Hello Leonid


> Introduced two new helper functions for vGIC: vgic_is_valid_line and
> vgic_is_spi. The functions are similar to the newly introduced
> gic_is_valid_line and gic_is_spi, but they verify whether a vIRQ
> is available for a specific domain, while GIC-specific functions
> validate INTIDs for the real GIC hardware. For example, the GIC may
> support all 992 SPI lines, but the domain may use only some part of them
> (e.g., 640), depending on the highest IRQ number defined in the domain
> configuration. Therefore, for vGIC-related code and checks, the
> appropriate functions should be used. Also, updated the appropriate
> checks to use these new helper functions.
> 
> The purpose of introducing new helper functions for vGIC is essentially
> the same as for GIC: to avoid potential confusion with GIC-related
> checks and to consolidate similar code into separate functions, which
> can be more easily extended by additional conditions, e.g., when
> implementing extended SPI interrupts.
> 
> Only the validation change in vgic_inject_irq may affect existing
> functionality, as it currently checks whether the vIRQ is less than or
> equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
> first SPI), the check should behave consistently with similar logic in
> other places and should check if the vIRQ number is less than
> vgic_num_irqs. The remaining changes, which replace open-coded checks
> with the use of these new helper functions, do not introduce any
> functional changes, as the helper functions follow the current vIRQ
> index verification logic.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V4:
> - removed redundant parentheses
> 
> Changes in V3:
> - renamed vgic_is_valid_irq to vgic_is_valid_line and vgic_is_shared_irq
>    to vgic_is_spi
> - added vgic_is_valid_line implementation for new-vgic, because
>    vgic_is_valid_line is called from generic code. It is necessary to fix
>    the build for new-vgic.

The comments I provided are addressed (thanks), so you can add my:

Reviewed-by: Oleksandr Tyshchenko 

[snip]


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Subject: Re: [RFC PATCH 4/9] hvm: Introduce "fixed memory layout" feature
To: Teddy Astie 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini , Juergen Gross
 , xen-devel@lists.xenproject.org
References: 
 <640223e5e7ee18a73f62152dd27883bf5978fbfe.1755785258.git.teddy.astie@vates.tech>
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On 21.08.2025 17:25, Teddy Astie wrote:
> @@ -686,10 +691,31 @@ static int domain_construct_memmap(libxl__gc *gc,
>      /* We always own at least one lowmem entry. */
>      unsigned int e820_entries = 1;
>      struct e820entry *e820 = NULL;
> +    uint64_t highmem_start = ((uint64_t)1 << 32);
>      uint64_t highmem_size =
>                      dom->highmem_end ? dom->highmem_end - (1ull << 32) : 0;
>      uint32_t lowmem_start = dom->device_model ? GUEST_LOW_MEM_START_DEFAULT : 0;
>      unsigned page_size = XC_DOM_PAGE_SIZE(dom);
> +    /* Special region starts at the first 1G boundary after the highmem */
> +    uint64_t special_region_start =
> +        (highmem_start + highmem_size + GB(1) - 1) & ~(GB(1) - 1);

That is, inaccessible before entering PAE mode?

The open-coding of ROUNDUP() also isn't nice, but sadly unavoidable as long
the the macro works in terms of unsigned long.

> @@ -769,6 +805,40 @@ static int domain_construct_memmap(libxl__gc *gc,
>          e820[nr].type = E820_RAM;
>      }
>  
> +    /* Special regions */
> +    if (libxl_defbool_val(d_config->b_info.arch_x86.fixed_mem_layout))
> +    {
> +        e820[nr].type = XEN_HVM_MEMMAP_TYPE_SHARED_INFO;
> +        e820[nr].addr = special_region_offset;
> +        e820[nr].size = page_size;
> +        special_region_offset += e820[nr].size;
> +        nr++;
> +
> +        if ( gnttab_frame_count )
> +        {
> +            e820[nr].type = XEN_HVM_MEMMAP_TYPE_GRANT_TABLE;
> +            e820[nr].addr = special_region_offset;
> +            e820[nr].size = gnttab_frame_count * page_size;
> +            special_region_offset += e820[nr].size;
> +            nr++;
> +        }
> +
> +        if (d_config->b_info.max_grant_version >= 2 && gnttab_status_frame_count)
> +        {
> +            e820[nr].type = XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS;
> +            e820[nr].addr = special_region_offset;
> +            e820[nr].size = gnttab_status_frame_count * page_size;
> +            special_region_offset += e820[nr].size;
> +            nr++;
> +        }
> +
> +        e820[nr].type = XEN_HVM_MEMMAP_TYPE_FOREIGN_REG;
> +        e820[nr].addr = special_region_offset;
> +        e820[nr].size = MB(512);

Can we really know this is going to be enough for all use cases?

> --- a/xen/include/public/arch-x86/hvm/start_info.h
> +++ b/xen/include/public/arch-x86/hvm/start_info.h
> @@ -99,6 +99,13 @@
>  #define XEN_HVM_MEMMAP_TYPE_DISABLED  6
>  #define XEN_HVM_MEMMAP_TYPE_PMEM      7
>  
> +/* Xen-specific types (OEM-specific range of the ACPI spec) */
> +#define XEN_HVM_MEMMAP_TYPE_SHARED_INFO   0xF0000001 /* Shared info page */
> +#define XEN_HVM_MEMMAP_TYPE_GRANT_TABLE   0xF0000002 /* Grant table pages */
> +#define XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS 0xF0000003 /* Grant table status page (v2) */
> +#define XEN_HVM_MEMMAP_TYPE_FOREIGN_REG   0xF0000004 /* Suitable region for grant mappings */
> +                                                     /* and foreign mappings */

I question it being legitimate for us to introduce new E820 types.

Jan


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Subject: Re: [RFC PATCH 5/9] docs/x86: Introduce FastABI
To: Teddy Astie 
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On 21.08.2025 17:25, Teddy Astie wrote:
> FastABI is a alternative ABI designed with performance and coco-enabled
> guest in mind. It is register-oriented instead of refering to C structures
> in the guest memory (through a virtual memory pointer).
> 
> It only focuses on kernel-side hypercalls, it doesn't aim to provide toolstack
> operations.

And even there it excludes certain pretty relevant ones, like many of the
gnttabop sub-ops. As alluded to by a reply to an earlier patch, I don't
think having an ABI for just a subset of the hypercalls is going to help.

Jan


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Subject: Re: [RFC PATCH 6/9] sched: Extract do_poll main logic into vcpu_poll
To: Teddy Astie 
Cc: Dario Faggioli , Juergen Gross ,
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On 21.08.2025 17:25, Teddy Astie wrote:
> do_poll takes sched_poll* as parameter, but that's actually in guest memory
> (so it's more a guest handle).

No, it's not, or else ...

> --- a/xen/common/sched/core.c
> +++ b/xen/common/sched/core.c
> @@ -1437,21 +1437,13 @@ static void vcpu_block_enable_events(void)
>      vcpu_block();
>  }
>  
> -static long do_poll(const struct sched_poll *sched_poll)
> +static long vcpu_poll(unsigned int nr_ports, uint64_t timeout, evtchn_port_t *ports)
>  {
>      struct vcpu   *v = current;
>      struct domain *d = v->domain;
> -    evtchn_port_t  port = 0;
>      long           rc;
>      unsigned int   i;
>  
> -    /* Fairly arbitrary limit. */
> -    if ( sched_poll->nr_ports > 128 )

... this access would be a security issue. The handle is ...

> -        return -EINVAL;
> -
> -    if ( !guest_handle_okay(sched_poll->ports, sched_poll->nr_ports) )

... seen here, the ->ports member.

Here as well as for patch 1 and 3 what is entirely lacking from the description
is the mentioning of why the change is actually going to be useful.

Jan


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Subject: Re: [RFC PATCH 8/9] hvm: Introduce XEN_HVM_MEMMAP_TYPE_HOTPLUG_ZONE
To: Teddy Astie 
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On 21.08.2025 17:25, Teddy Astie wrote:
> Allow specifying in memory map a region which can be hotplugged.
> 
> This will be used by a future memory hotplug feature.

Why could this not be done the ACPI way, with the regions properly specified
in SRAT?

Jan


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Subject: Re: [PATCH v8 1/8] xen/cpufreq: introduce new sub-hypercall to
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On 28.08.2025 12:02, Penny Zheng wrote:
> @@ -693,6 +699,120 @@ int acpi_set_pdc_bits(unsigned int acpi_id, XEN_GUEST_HANDLE(uint32) pdc)
>      return ret;
>  }
>  
> +static void print_CPPC(const struct xen_processor_cppc *cppc_data)
> +{
> +    printk("\t_CPC: highest_perf=%u, lowest_perf=%u, "
> +           "nominal_perf=%u, lowest_nonlinear_perf=%u, "
> +           "nominal_mhz=%uMHz, lowest_mhz=%uMHz\n",
> +           cppc_data->cpc.highest_perf, cppc_data->cpc.lowest_perf,
> +           cppc_data->cpc.nominal_perf, cppc_data->cpc.lowest_nonlinear_perf,
> +           cppc_data->cpc.nominal_mhz, cppc_data->cpc.lowest_mhz);
> +}
> +
> +int set_cppc_pminfo(unsigned int acpi_id,
> +                    const struct xen_processor_cppc *cppc_data)
> +{
> +    int ret = 0, cpuid;

Eclair doesn't like this:

Reports for service MC3A2.R5.3

service MC3A2.R5.3: (required) An identifier declared in an inner scope shall not hide an identifier declared in an outer scope (1 of 1 violation)

 violation for MC3A2.R5.3 untagged
xen/arch/x86/include/asm/processor.h:130.20-130.24:
non-compliant function `cpuid(unsigned, unsigned*, unsigned*, unsigned*, unsigned*)' (unit `xen/drivers/cpufreq/cpufreq.c' with target `xen/drivers/cpufreq/.cpufreq.o.tmp'): there is another identifier `cpuid'
xen/drivers/cpufreq/cpufreq.c:726.18-726.22:
non-compliant local variable `cpuid': there is another identifier `cpuid'

I'm fixing this up for you, but I have to admit that I'm getting tired of
doing such cleanups for supposedly-ready-to-commit patches.

Jan


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Date: Thu, 28 Aug 2025 15:02:41 +0200
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Subject: Re: [RFC PATCH v3 3/3] x86/hvm: Introduce Xen-wide ASID allocator
To: Teddy Astie 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 Stefano Stabellini ,
 Vaishali Thakkar ,
 Oleksii Kurochko , xen-devel@lists.xenproject.org
References: 
 <81169a40fdc8c124b1656e451ac2e81f4e8edd2d.1750770621.git.teddy.astie@vates.tech>
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On 26.06.2025 16:01, Teddy Astie wrote:
> From: Vaishali Thakkar  (formely vates.tech)
> 
> Currently ASID generation and management is done per-PCPU. This
> scheme is incompatible with SEV technologies as SEV VMs need to
> have a fixed ASID associated with all vcpus of the VM throughout
> it's lifetime.
> 
> This commit introduces a Xen-wide allocator which initializes
> the asids at the start of xen and allows to have a fixed asids
> throughout the lifecycle of all domains. Having a fixed asid
> for non-SEV domains also presents us with the opportunity to
> further take use of AMD instructions like TLBSYNC and INVLPGB
> for broadcasting the TLB invalidations.
> 
> Introduce vcpu->needs_tlb_flush attribute to schedule a guest TLB
> flush for the next VMRUN/VMENTER. This will be later be done using
> either TLB_CONTROL field (AMD) or INVEPT (Intel). This flush method
> is used in place of the current ASID swapping logic.
> 
> Signed-off-by: Teddy Astie 
> Signed-off-by: Vaishali Thakkar  (formely vates.tech)

Not sure whether you may legitimately alter pre-existing S-o-b. In
any event the two S-o-b looks to be in the wrong order; like most
other tags they want to be sorted chronologically.

> ---
> CC: Oleksii Kurochko 
> 
> Should the ASID/VPID/VMID management logic code being shared accross
> x86/ARM/RISC-V ?

If all present and future architectures agree on how exactly they want
to use these IDs. Which I'm unsure of. RISC-V is now vaguely following
the original x86 model.

> Is it possible to have multiples vCPUs of a same domain simultaneously
> scheduled on top of a single pCPU ? If so, it would need a special
> consideration for this corner case, such as we don't miss a TLB flush
> in such cases.

No, how would two entities be able to run on a single pCPU at any single
point in time?

> I get various stability when testing shadow paging in these patches, unsure
> what's the exact root case. HAP works perfectly fine though.
> 
> TODO:
> - Intel: Don't assign the VPID at each VMENTER, though we need
>   to rethink how we manage VMCS with nested virtualization / altp2m
>   for changing this behavior.
> - AMD: Consider hot-plug of CPU with ERRATA_170. (is it possible ?)
> - Consider cases where we don't have enough ASIDs (e.g Xen as nested guest)
> - Nested virtualization ASID management

For these last two points - maybe we really need a mixed model?

> ---
>  xen/arch/x86/flushtlb.c                |  31 +++---
>  xen/arch/x86/hvm/asid.c                | 148 +++++++++----------------
>  xen/arch/x86/hvm/emulate.c             |   2 +-
>  xen/arch/x86/hvm/hvm.c                 |  14 ++-
>  xen/arch/x86/hvm/nestedhvm.c           |   6 +-
>  xen/arch/x86/hvm/svm/asid.c            |  77 ++++++++-----
>  xen/arch/x86/hvm/svm/nestedsvm.c       |   1 -
>  xen/arch/x86/hvm/svm/svm.c             |  36 +++---
>  xen/arch/x86/hvm/svm/svm.h             |   4 -
>  xen/arch/x86/hvm/vmx/vmcs.c            |   5 +-
>  xen/arch/x86/hvm/vmx/vmx.c             |  68 ++++++------
>  xen/arch/x86/hvm/vmx/vvmx.c            |   5 +-
>  xen/arch/x86/include/asm/flushtlb.h    |   7 --
>  xen/arch/x86/include/asm/hvm/asid.h    |  25 ++---
>  xen/arch/x86/include/asm/hvm/domain.h  |   1 +
>  xen/arch/x86/include/asm/hvm/hvm.h     |  15 +--
>  xen/arch/x86/include/asm/hvm/svm/svm.h |   5 +
>  xen/arch/x86/include/asm/hvm/vcpu.h    |  10 +-
>  xen/arch/x86/include/asm/hvm/vmx/vmx.h |   4 +-
>  xen/arch/x86/mm/hap/hap.c              |   6 +-
>  xen/arch/x86/mm/p2m.c                  |   7 +-
>  xen/arch/x86/mm/paging.c               |   2 +-
>  xen/arch/x86/mm/shadow/hvm.c           |   1 +
>  xen/arch/x86/mm/shadow/multi.c         |  12 +-
>  xen/include/xen/sched.h                |   2 +
>  25 files changed, 227 insertions(+), 267 deletions(-)

I think I said this to Vaishali already: This really wants splitting up some,
to become halfway reviewable.

Jan


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Date: Thu, 28 Aug 2025 10:03:29 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
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	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 01/16] dma-mapping: introduce new DMA attribute to
 indicate MMIO memory
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On Tue, Aug 19, 2025 at 08:36:45PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> This patch introduces the DMA_ATTR_MMIO attribute to mark DMA buffers
> that reside in memory-mapped I/O (MMIO) regions, such as device BARs
> exposed through the host bridge, which are accessible for peer-to-peer
> (P2P) DMA.
> 
> This attribute is especially useful for exporting device memory to other
> devices for DMA without CPU involvement, and avoids unnecessary or
> potentially detrimental CPU cache maintenance calls.
> 
> DMA_ATTR_MMIO is supposed to provide dma_map_resource() functionality
> without need to call to special function and perform branching by
> the callers.

'branching when processing generic containers like bio_vec by the callers'

Many of the existing dma_map_resource() users already know the thing
is MMIO and don't have branching..

> Signed-off-by: Leon Romanovsky 
> ---
>  Documentation/core-api/dma-attributes.rst | 18 ++++++++++++++++++
>  include/linux/dma-mapping.h               | 20 ++++++++++++++++++++
>  include/trace/events/dma.h                |  3 ++-
>  rust/kernel/dma.rs                        |  3 +++
>  4 files changed, 43 insertions(+), 1 deletion(-)

Reviewed-by: Jason Gunthorpe 

Jason


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From: "Anthony PERARD" 
Subject: =?utf-8?Q?Re:=20[PATCH=20v8=207/8]=20xen/cpufreq:=20bypass=20governor-related=20para=20for=20amd-cppc-epp?=
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On Thu, Aug 28, 2025 at 06:05:34PM +0800, Penny Zheng wrote:
> HWP and amd-cppc-epp are both governor-less driver, so we introduce
> "is_governor_less" flag and cpufreq_is_governorless() to help bypass
> governor-related info on dealing with cpufreq para.
> 
> Signed-off-by: Penny Zheng 

Acked-by: Anthony PERARD 

Thanks,

-- 

 | Vates

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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Date: Thu, 28 Aug 2025 10:19:54 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 03/16] dma-debug: refactor to use physical addresses
 for page mapping
Message-ID: <20250828131954.GB9469@nvidia.com>
References: 
 <478d5b7135008b3c82f100faa9d3830839fc6562.1755624249.git.leon@kernel.org>
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On Tue, Aug 19, 2025 at 08:36:47PM +0300, Leon Romanovsky wrote:
> @@ -1218,19 +1219,24 @@ void debug_dma_map_page(struct device *dev, struct page *page, size_t offset,
>  		return;
>  
>  	entry->dev       = dev;
> -	entry->type      = dma_debug_single;
> -	entry->paddr	 = page_to_phys(page) + offset;
> +	entry->type      = dma_debug_phy;
> +	entry->paddr	 = phys;
>  	entry->dev_addr  = dma_addr;
>  	entry->size      = size;
>  	entry->direction = direction;
>  	entry->map_err_type = MAP_ERR_NOT_CHECKED;
>  
> -	check_for_stack(dev, page, offset);
> +	if (!(attrs & DMA_ATTR_MMIO)) {
> +		struct page *page = phys_to_page(phys);
> +		size_t offset = offset_in_page(page);
>  
> -	if (!PageHighMem(page)) {
> -		void *addr = page_address(page) + offset;
> +		check_for_stack(dev, page, offset);
>  
> -		check_for_illegal_area(dev, addr, size);
> +		if (!PageHighMem(page)) {
> +			void *addr = page_address(page) + offset;
> +
> +			check_for_illegal_area(dev, addr, size);
> +		}
>  	}

Not anything to change in this series, but I was looking at what it
would take to someday remove the struct page here and it looks
reasonable.

diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c
index 06e31fd216e38e..0d6dd3eb9860ac 100644
--- a/kernel/dma/debug.c
+++ b/kernel/dma/debug.c
@@ -1051,28 +1051,28 @@ static void check_unmap(struct dma_debug_entry *ref)
 	dma_entry_free(entry);
 }
 
-static void check_for_stack(struct device *dev,
-			    struct page *page, size_t offset)
+static void check_for_stack(struct device *dev, phys_addr_t phys)
 {
 	void *addr;
 	struct vm_struct *stack_vm_area = task_stack_vm_area(current);
 
 	if (!stack_vm_area) {
 		/* Stack is direct-mapped. */
-		if (PageHighMem(page))
+		if (PhysHighMem(phys))
 			return;
-		addr = page_address(page) + offset;
+		addr = phys_to_virt(phys);
 		if (object_is_on_stack(addr))
 			err_printk(dev, NULL, "device driver maps memory from stack [addr=%p]\n", addr);
 	} else {
 		/* Stack is vmalloced. */
+		unsigned long pfn = phys >> PAGE_SHIFT;
 		int i;
 
 		for (i = 0; i < stack_vm_area->nr_pages; i++) {
-			if (page != stack_vm_area->pages[i])
+			if (pfn != page_to_pfn(stack_vm_area->pages[i]))
 				continue;
 
-			addr = (u8 *)current->stack + i * PAGE_SIZE + offset;
+			addr = (u8 *)current->stack + i * PAGE_SIZE + (phys % PAGE_SIZE);
 			err_printk(dev, NULL, "device driver maps memory from stack [probable addr=%p]\n", addr);
 			break;
 		}
@@ -1225,16 +1225,10 @@ void debug_dma_map_phys(struct device *dev, phys_addr_t phys, size_t size,
 	entry->map_err_type = MAP_ERR_NOT_CHECKED;
 
 	if (!(attrs & DMA_ATTR_MMIO)) {
-		struct page *page = phys_to_page(phys);
-		size_t offset = offset_in_page(page);
+		check_for_stack(dev, phys);
 
-		check_for_stack(dev, page, offset);
-
-		if (!PageHighMem(page)) {
-			void *addr = page_address(page) + offset;
-
-			check_for_illegal_area(dev, addr, size);
-		}
+		if (!PhysHighMem(phys))
+			check_for_illegal_area(dev, phys_to_virt(phys), size);
 	}
 
 	add_dma_entry(entry, attrs);


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Subject: Re: [PATCH v4 09/12] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
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 <66b39c4ba25e7a19beeca62ab23f5d3ab3cbae52.1756317702.git.leonid_komarianskyi@epam.com>
Content-Language: en-US
From: Oleksandr Tyshchenko 
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On 27.08.25 21:24, Leonid Komarianskyi wrote:

Hello Leonid

> The Dom0 and DomUs logic for the dom0less configuration in create_dom0() and
> arch_create_domUs() has been updated to account for extended SPIs when
> supported by the hardware and enabled with CONFIG_GICV3_ESPI. These changes
> ensure the proper calculation of the maximum number of SPIs and eSPIs available
> to Dom0 and DomUs in dom0less setups.
> 
> When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is enabled, the
> maximum number of eSPI interrupts is calculated using the ESPI_BASE_INTID
> offset (4096) and is limited to 1024, with 32 IRQs subtracted. To ensure
> compatibility with non-Dom0 domains, this adjustment is applied by the
> toolstack during domain creation, while for Dom0 or DomUs in Dom0, it is
> handled directly during VGIC initialization. If eSPIs are not supported, the
> calculation defaults to using the standard SPI range, with a maximum value of
> 992 interrupt lines, as it works currently.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V4:
> - consolidated the eSPI and SPI logic into a new inline function,
>    vgic_def_nr_spis. Without eSPI support (either due to config being
>    disabled or hardware not supporting it), it will return the regular SPI
>    range, as it works currently. There are no functional changes compared
>    with the previous patch version
> - removed VGIC_DEF_MAX_SPI macro, to reduce the number of ifdefs

very good, thanks, only NIT below

Reviewed-by: Oleksandr Tyshchenko 



> 
> Changes in V3:
> - renamed macro VGIC_DEF_NR_ESPIS to more appropriate VGIC_DEF_MAX_SPI
> - added eSPI initialization for dom0less setups
> - fixed comment with mentions about dom0less builds
> - fixed formatting for lines with more than 80 symbols
> - updated commit message
> 
> Changes in V2:
> - no changes
> ---
>   xen/arch/arm/dom0less-build.c   |  2 +-
>   xen/arch/arm/domain_build.c     |  2 +-
>   xen/arch/arm/include/asm/vgic.h | 21 +++++++++++++++++++++
>   3 files changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
> index 69b9ea22ce..02d5559102 100644
> --- a/xen/arch/arm/dom0less-build.c
> +++ b/xen/arch/arm/dom0less-build.c
> @@ -285,7 +285,7 @@ void __init arch_create_domUs(struct dt_device_node *node,
>       {
>           int vpl011_virq = GUEST_VPL011_SPI;
>   
> -        d_cfg->arch.nr_spis = VGIC_DEF_NR_SPIS;
> +        d_cfg->arch.nr_spis = vgic_def_nr_spis();
>   
>           /*
>            * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index d91a71acfd..39eea0be00 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -2054,7 +2054,7 @@ void __init create_dom0(void)
>   
>       /* The vGIC for DOM0 is exactly emulating the hardware GIC */
>       dom0_cfg.arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE;
> -    dom0_cfg.arch.nr_spis = VGIC_DEF_NR_SPIS;
> +    dom0_cfg.arch.nr_spis = vgic_def_nr_spis();
>       dom0_cfg.arch.tee_type = tee_get_type();
>       dom0_cfg.max_vcpus = dom0_max_vcpus();
>   
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h
> index fb4cea73eb..11f9d216eb 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -355,6 +355,27 @@ extern void vgic_check_inflight_irqs_pending(struct vcpu *v,
>   /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
>   #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
>   
> +static inline unsigned int vgic_def_nr_spis(void)
> +{
> +#ifdef CONFIG_GICV3_ESPI
> +    /*
> +     * Check if the hardware supports extended SPIs (even if the appropriate
> +     * config is set). If not, the common SPI range will be used. Otherwise
> +     * returns the maximum eSPI INTID, supported by HW GIC, subtracted by 32.

NIT: s/returns/return ...


> +     * For non-Dom0 domains, the toolstack or arch_create_domUs function
> +     * applies the same adjustment to cover local IRQs (please, see comment
> +     * for macro that is used for regular SPIs - VGIC_DEF_NR_SPIS).

  ... I am not 100% sure, that I follow the wording "For non-Dom0 
domains, the toolstack or arch_create_domUs ...". Did you perhaps mean:

For Dom0 and started at boot time DomUs ...?

  We will
> +     * add back this value during VGIC initialization. This ensures consistent
> +     * handling for Dom0 and other domains. For the regular SPI range interrupts
> +     * in this case, the maximum value of VGIC_DEF_NR_SPIS will be used.
> +     */
> +    if ( gic_number_espis() > 0 )
> +        return ESPI_BASE_INTID + min(gic_number_espis(), 1024U) - 32;
> +#endif
> +
> +    return VGIC_DEF_NR_SPIS;
> +}
> +
>   extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
>   
>   static inline bool vgic_is_spi(struct domain *d, unsigned int virq)



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On Tue, Aug 19, 2025 at 08:36:48PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> As a preparation for following map_page -> map_phys API conversion,
> let's rename trace_dma_*map_page() to be trace_dma_*map_phys().
> 
> Signed-off-by: Leon Romanovsky 
> ---
>  include/trace/events/dma.h | 4 ++--
>  kernel/dma/mapping.c       | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)

Reviewed-by: Jason Gunthorpe 

Jason


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To: Stefano Stabellini 
CC: "xen-devel@lists.xenproject.org" , Andrew
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	, Michal Orzel ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Volodymyr
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Subject: Re: [RFC PATCH v5 02/10] xen/arm: scmi-smc: update to be used under
 sci subsystem
Thread-Topic: [RFC PATCH v5 02/10] xen/arm: scmi-smc: update to be used under
 sci subsystem
Thread-Index: AQHb+v2VN6PNmY5o9E6echLDtYWg47RvkxgAgAbZdoCAALH2AIABK1sA
Date: Thu, 28 Aug 2025 13:30:34 +0000
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Subject: Re: [PATCH] Optimise restore memory allocation
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On 8/27/25 7:23 PM, Andrew Cooper wrote:
> Subject wants to be at least tools/libxc, and probably "Use superpages
> where possible on migrate/resume"
>
>
> On 27/08/2025 1:33 pm, Frediano Ziglio wrote:
>> Try to allocate larger order pages.
>> With some test memory program stressing TLB (many small random
>> memory accesses) you can get 15% performance improves.
>> On the first memory iteration the sender is currently sending
>> memory in 4mb aligned chunks which allows the receiver to
>> allocate most pages as 2mb superpages instead of single 4kb pages.
> It's critical to say somewhere that this is applicable to HVM guests.
>
> You've eluded to it, but it's important to state clearly that, for HVM
> guests, PAGE_DATA records contain metadata about GFNs in aligned 4M
> blocks.  This is why we don't even need to buffer a second record.
>
> It's also worth stating that 1G superpages are left for later.
>
>
> CC-ing Oleksii as release manager.  This is a fix for a (mis)feature
> which has been known for a decade (since Xen 4.6), and for which two
> series have been posted but not managed to get in.  Unlike those series,
> this is a very surgical fix that gets the majority of the perf win back,
> without the complexity of trying to guess at 1G pages.
>
> Therefore I'd like to request that it be considered for 4.21 at this
> juncture.
>
Such a significant performance increase is a good reason to include this
in 4.21. We also still have enough time to test it properly.

If there are no objections:Release-Acked-by: Oleksii Kurochko  Thanks. 
~ Oleksii

>> Signed-off-by: Frediano Ziglio
>> ---
>>   tools/libs/guest/xg_sr_restore.c | 39 ++++++++++++++++++++++++++++----
>>   1 file changed, 35 insertions(+), 4 deletions(-)
>>
>> diff --git a/tools/libs/guest/xg_sr_restore.c b/tools/libs/guest/xg_sr_restore.c
>> index 06231ca826..8dcb1b19c5 100644
>> --- a/tools/libs/guest/xg_sr_restore.c
>> +++ b/tools/libs/guest/xg_sr_restore.c
>> @@ -129,6 +129,8 @@ static int pfn_set_populated(struct xc_sr_context *ctx, xen_pfn_t pfn)
>>       return 0;
>>   }
>>   
>> +#define IS_POWER_OF_2(n) (((n) & ((n) - 1)) == 0)
>> +
>>   /*
>>    * Given a set of pfns, obtain memory from Xen to fill the physmap for the
>>    * unpopulated subset.  If types is NULL, no page type checking is performed
>> @@ -141,6 +143,7 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
>>       xen_pfn_t *mfns = malloc(count * sizeof(*mfns)),
>>           *pfns = malloc(count * sizeof(*pfns));
>>       unsigned int i, nr_pfns = 0;
>> +    bool contiguous = true;
>>       int rc = -1;
>>   
>>       if ( !mfns || !pfns )
>> @@ -159,18 +162,46 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
>>               if ( rc )
>>                   goto err;
>>               pfns[nr_pfns] = mfns[nr_pfns] = original_pfns[i];
>> +            if ( pfns[nr_pfns] != pfns[0] + nr_pfns )
>> +                contiguous = false;
>>               ++nr_pfns;
>>           }
>>       }
>>   
>>       if ( nr_pfns )
>>       {
>> -        rc = xc_domain_populate_physmap_exact(
>> -            xch, ctx->domid, nr_pfns, 0, 0, mfns);
>> +        /* try optimizing using larger order */
>> +        rc = -1;
>> +        /*
>> +         * The "nr_pfns <= (1 << 18)" check is mainly for paranoia, it should
>> +         * never happen, the sender would have to send a really large packet.
>> +         */
>> +        if ( contiguous && nr_pfns <= (1 << 18) &&
> This is an arbitrary limit, and to contradict the prior feedback given
> in private, the domain's MAX_ORDER isn't relevant here.  It's the
> toolstack's choice how to lay out the guest in memory.
>
>> +             IS_POWER_OF_2(nr_pfns) && (pfns[0] & (nr_pfns - 1)) == 0 )
>> +        {
>> +            const unsigned int extent_order = __builtin_ffs(nr_pfns) - 1;
> This (non-)loop isn't great.  You'll e.g. use 4k pages for the second 2M
> page of an HVM guest simply because the VGA hole exists in the first.
>
> I think you probably want something like:
>
> int populate_physmap_4k(ctx, nr, mfns);
> int populate_physmap_2M(ctx, nr, mfns);
>
> as simple wrappers around the raw hypercalls including transforming back
> the mfns[] array, and:
>
> int populate_phymap(...);
>
> with logic of the form:
>
>      while ( nr )
>      {
>          if ( nr < 512 ) /* Can't be a superpage */
>          {
>              populate_physmap_4k(ctx, i, mfns);
>              mfns += i;
>              nr -= i;
>              continue;
>          }
>
>          if ( !ALIGNED_2M(mfn) ) /* Populate up until a point that could be a superpage */
>          {
>              while ( !ALIGNED_2M(mfn + i) )
>                  i++;
>              populate_physmap_4k(ctx, i, mfns);
>              mfns += i;
>              nr -= i;
>          }
>
>          if ( nr >= 512 )
>          {
>              for ( i = 1; i < 512; ++i )
>                  if ( mfns[i] != mfns[0] + i )
>                      break;
>              if ( i == 512 )
>                  populate_physmap_2M(ctx, i, mfns);
>              else
>                  populate_physmap_4k(...);
>
>              mfns += i;
>              nr -= i;
>          }
>      }
>
>
>
> Obviously with error handling, and whatever boundary conditions I've got
> wrong.
>
> 2M is the only size that matters (ignoring 1G which we've excluded for
> now), and this form will reconstruct more superpages for the guest than
> trying to do 4M allocations will.
>
> ~Andrew
--------------UE91rRe1RLfqhJu1GwWz81oz
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 8bit



  
    
  
  
    

    
    
    
    
    On 8/27/25 7:23 PM, Andrew Cooper
      wrote:
    
    
    
    
    
      
    Subject wants to be at least tools/libxc, and probably "Use superpages
where possible on migrate/resume"


On 27/08/2025 1:33 pm, Frediano Ziglio wrote:

    
      
    
        
    Try to allocate larger order pages.
With some test memory program stressing TLB (many small random
memory accesses) you can get 15% performance improves.
On the first memory iteration the sender is currently sending
memory in 4mb aligned chunks which allows the receiver to
allocate most pages as 2mb superpages instead of single 4kb pages.

    
      
    
      
    It's critical to say somewhere that this is applicable to HVM guests.

You've eluded to it, but it's important to state clearly that, for HVM
guests, PAGE_DATA records contain metadata about GFNs in aligned 4M
blocks.  This is why we don't even need to buffer a second record.

It's also worth stating that 1G superpages are left for later.


CC-ing Oleksii as release manager.  This is a fix for a (mis)feature
which has been known for a decade (since Xen 4.6), and for which two
series have been posted but not managed to get in.  Unlike those series,
this is a very surgical fix that gets the majority of the perf win back,
without the complexity of trying to guess at 1G pages.

Therefore I'd like to request that it be considered for 4.21 at this
juncture.


    
    
    
    
    Such a significant performance increase is a good reason to include this
in 4.21. We also still have enough time to test it properly.

If there are no objections:
 Release-Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Thanks.

~ Oleksii

    
    
    
      
    
        
    Signed-off-by: Frediano Ziglio <frediano.ziglio@cloud.com>
---
 tools/libs/guest/xg_sr_restore.c | 39 ++++++++++++++++++++++++++++----
 1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/tools/libs/guest/xg_sr_restore.c b/tools/libs/guest/xg_sr_restore.c
index 06231ca826..8dcb1b19c5 100644
--- a/tools/libs/guest/xg_sr_restore.c
+++ b/tools/libs/guest/xg_sr_restore.c
@@ -129,6 +129,8 @@ static int pfn_set_populated(struct xc_sr_context *ctx, xen_pfn_t pfn)
     return 0;
 }
 
+#define IS_POWER_OF_2(n) (((n) & ((n) - 1)) == 0)
+
 /*
  * Given a set of pfns, obtain memory from Xen to fill the physmap for the
  * unpopulated subset.  If types is NULL, no page type checking is performed
@@ -141,6 +143,7 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
     xen_pfn_t *mfns = malloc(count * sizeof(*mfns)),
         *pfns = malloc(count * sizeof(*pfns));
     unsigned int i, nr_pfns = 0;
+    bool contiguous = true;
     int rc = -1;
 
     if ( !mfns || !pfns )
@@ -159,18 +162,46 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
             if ( rc )
                 goto err;
             pfns[nr_pfns] = mfns[nr_pfns] = original_pfns[i];
+            if ( pfns[nr_pfns] != pfns[0] + nr_pfns )
+                contiguous = false;
             ++nr_pfns;
         }
     }
 
     if ( nr_pfns )
     {
-        rc = xc_domain_populate_physmap_exact(
-            xch, ctx->domid, nr_pfns, 0, 0, mfns);
+        /* try optimizing using larger order */
+        rc = -1;
+        /*
+         * The "nr_pfns <= (1 << 18)" check is mainly for paranoia, it should
+         * never happen, the sender would have to send a really large packet.
+         */
+        if ( contiguous && nr_pfns <= (1 << 18) &&

    
      
    
      
    This is an arbitrary limit, and to contradict the prior feedback given
in private, the domain's MAX_ORDER isn't relevant here.  It's the
toolstack's choice how to lay out the guest in memory.


    
      
    
        
    +             IS_POWER_OF_2(nr_pfns) && (pfns[0] & (nr_pfns - 1)) == 0 )
+        {
+            const unsigned int extent_order = __builtin_ffs(nr_pfns) - 1;

    
      
    
      
    This (non-)loop isn't great.  You'll e.g. use 4k pages for the second 2M
page of an HVM guest simply because the VGA hole exists in the first.

I think you probably want something like:

int populate_physmap_4k(ctx, nr, mfns);
int populate_physmap_2M(ctx, nr, mfns);

as simple wrappers around the raw hypercalls including transforming back
the mfns[] array, and:

int populate_phymap(...);

with logic of the form:

    while ( nr )
    {
        if ( nr < 512 ) /* Can't be a superpage */
        {
            populate_physmap_4k(ctx, i, mfns);
            mfns += i;
            nr -= i;
            continue;
        }

        if ( !ALIGNED_2M(mfn) ) /* Populate up until a point that could be a superpage */
        {
            while ( !ALIGNED_2M(mfn + i) )
                i++;
            populate_physmap_4k(ctx, i, mfns);
            mfns += i;
            nr -= i;
        }

        if ( nr >= 512 )
        {
            for ( i = 1; i < 512; ++i )
                if ( mfns[i] != mfns[0] + i )
                    break;
            if ( i == 512 )
                populate_physmap_2M(ctx, i, mfns);
            else
                populate_physmap_4k(...);

            mfns += i;
            nr -= i;
        }
    }



Obviously with error handling, and whatever boundary conditions I've got
wrong.

2M is the only size that matters (ignoring 1G which we've excluded for
now), and this form will reconstruct more superpages for the guest than
trying to do 4M allocations will.

~Andrew

    
    
    
  


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Message-ID: 
Date: Thu, 28 Aug 2025 15:37:56 +0200
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v3 11/11] CHANGELOG.md: add mention of GICv3.1 eSPI
 support
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: "olekstysh@gmail.com" ,
 Community Manager 
References: 
 <9dc68c29751aeacf37b51d3bd345e87e9a0f0ccf.1756216943.git.leonid_komarianskyi@epam.com>
Content-Language: en-US
From: Oleksii Kurochko 
In-Reply-To: <9dc68c29751aeacf37b51d3bd345e87e9a0f0ccf.1756216943.git.leonid_komarianskyi@epam.com>

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On 8/26/25 4:05 PM, Leonid Komarianskyi wrote:
> The GICv3.1 eSPI (Extended Shared Peripheral Interrupts) range is
> already supported with CONFIG_GICV3_ESPI enabled, so this feature should
> be mentioned in CHANGELOG.md.
>
> Signed-off-by: Leonid Komarianskyi
>
> ---
> Changes in V3:
> - introduced this patch
> ---
>   CHANGELOG.md | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/CHANGELOG.md b/CHANGELOG.md
> index 5f31ca08fe..dc34d29d99 100644
> --- a/CHANGELOG.md
> +++ b/CHANGELOG.md
> @@ -29,6 +29,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
>   
>    - On Arm:
>       - Ability to enable stack protector
> +    - GICv3.1 eSPI support

For clarity, I think it would be helpful to add a brief explanation of what eSPI is
(as you did in the commit message) and also mention “for Xen and guest domains†or
something similar.

With that:
  Acked-by: Oleksii Kurochko

Thanks.

~ Oleksii


>   
>   ### Removed
>    - On x86:
--------------Gzdbc9YdzMmQLtURME1Zr1r0
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    On 8/26/25 4:05 PM, Leonid Komarianskyi
      wrote:
    
    
    
    
    
      
    The GICv3.1 eSPI (Extended Shared Peripheral Interrupts) range is
already supported with CONFIG_GICV3_ESPI enabled, so this feature should
be mentioned in CHANGELOG.md.

Signed-off-by: Leonid Komarianskyi <leonid_komarianskyi@epam.com>

---
Changes in V3:
- introduced this patch
---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe..dc34d29d99 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -29,6 +29,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 
  - On Arm:
     - Ability to enable stack protector
+    - GICv3.1 eSPI support
    
    
    
    
    For clarity, I think it would be helpful to add a brief explanation of what eSPI is
(as you did in the commit message) and also mention “for Xen and guest domains†or
something similar.

With that:
 Acked-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>

Thanks.

~ Oleksii


    
    

    
    
    
    
    
      
     
 ### Removed
  - On x86:

    
    
    
  


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Date: Thu, 28 Aug 2025 10:38:57 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 05/16] iommu/dma: rename iommu_dma_*map_page to
 iommu_dma_*map_phys
Message-ID: <20250828133857.GD9469@nvidia.com>
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On Tue, Aug 19, 2025 at 08:36:49PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Rename the IOMMU DMA mapping functions to better reflect their actual
> calling convention. The functions iommu_dma_map_page() and
> iommu_dma_unmap_page() are renamed to iommu_dma_map_phys() and
> iommu_dma_unmap_phys() respectively, as they already operate on physical
> addresses rather than page structures.
> 
> The calling convention changes from accepting (struct page *page,
> unsigned long offset) to (phys_addr_t phys), which eliminates the need
> for page-to-physical address conversion within the functions. This
> renaming prepares for the broader DMA API conversion from page-based
> to physical address-based mapping throughout the kernel.
> 
> All callers are updated to pass physical addresses directly, including
> dma_map_page_attrs(), scatterlist mapping functions, and DMA page
> allocation helpers. The change simplifies the code by removing the
> page_to_phys() + offset calculation that was previously done inside
> the IOMMU functions.
> 
> Signed-off-by: Leon Romanovsky 
> ---
>  drivers/iommu/dma-iommu.c | 14 ++++++--------
>  include/linux/iommu-dma.h |  7 +++----
>  kernel/dma/mapping.c      |  4 ++--
>  kernel/dma/ops_helpers.c  |  6 +++---
>  4 files changed, 14 insertions(+), 17 deletions(-)

This looks fine

Reviewed-by: Jason Gunthorpe 

But related to other patches..

iommu_dma_map_phys() ends up like this:

	if (dev_use_swiotlb(dev, size, dir) &&
	    iova_unaligned(iovad, phys, size)) {
		if (attrs & DMA_ATTR_MMIO)
			return DMA_MAPPING_ERROR;

		phys = iommu_dma_map_swiotlb(dev, phys, size, dir, attrs);

But attrs is passed all the way down to swiotlb_tbl_map_single(),
maybe the DMA_ATTR_MMIO check should be moved there?

There are a few call chains with this redundancy:

dma_iova_link()
 -> iommu_dma_iova_link_swiotlb
  -> iommu_dma_iova_bounce_and_link
   -> iommu_dma_map_swiotlb
    -> swiotlb_tbl_map_single()

iommu_dma_map_phys() 
   -> iommu_dma_map_swiotlb
    -> swiotlb_tbl_map_single()

dma_direct_map_phys()
 -> swiotlb_map()
  -> swiotlb_tbl_map_single()

It makes alot of sense to put the check for MMIO when
slots[].orig_addr is stored because that is the point where we start
to require a pfn_to_page().

Jason


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Date: Thu, 28 Aug 2025 15:43:03 +0200
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User-Agent: Mozilla Thunderbird
Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
To: Andrew Cooper ,
 Xen-devel ,
 Community Manager ,
 "committers@xenproject.org" 
References: <07fc7122-d0ac-4dbe-800d-89086a07005b@gmail.com>
 
Content-Language: en-US
From: Oleksii Kurochko 
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On 8/26/25 9:12 PM, Andrew Cooper wrote:
> On 25/08/2025 4:50 pm, Oleksii Kurochko wrote:
>> Hello community,
>>
>> I’d like to remind everyone that the Feature Freeze deadline is approaching,
>> and we still have some outstanding requests from the community for patch series
>> to be merged into 4.21:
>>
>> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
>> 2. Introduce SCI SCMI SMC multi-agent support [2]
>> 3. Introduce eSPI support [3]
>> 4. FRED work: [4], [5], possibly others (?)
> For FRED, That's all that's out on the list.
>
> I've got an update to 4 almost ready to post, this time getting to dev
> complete.
>
> Unfortunately, I've still not managed to get any time on real hardware
> yet, so FRED will still be experimental in my series.  (The timelines
> were originally compatible with Xen 4.21, but access to hardware has not
> been as forthcoming as hoped.)
>
> When I can test on real hardware, there may be bugfixes, and I may be
> able to upgrade the status if we're not too far into the RCs.

Sounds good to me. Let’s wait until you’re able to test it on real hardware.
We’ll have some extra time during the Feature Freeze period, and the RCs
will be moved as well. I’ll announce this a little later today.

~ Oleksii

>
> ~Andrew
--------------mvC54Y60ARKGqTcDKCs3snMe
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    On 8/26/25 9:12 PM, Andrew Cooper
      wrote:
    
    
    
    
    
      
    On 25/08/2025 4:50 pm, Oleksii Kurochko wrote:

    
      
    
        
    Hello community,

I’d like to remind everyone that the Feature Freeze deadline is approaching,
and we still have some outstanding requests from the community for patch series
to be merged into 4.21:

1. Enable guest suspend/resume support on ARM via vPSCI [1]
2. Introduce SCI SCMI SMC multi-agent support [2]
3. Introduce eSPI support [3]
4. FRED work: [4], [5], possibly others (?)

    
      
    
      
    For FRED, That's all that's out on the list.

I've got an update to 4 almost ready to post, this time getting to dev
complete.

Unfortunately, I've still not managed to get any time on real hardware
yet, so FRED will still be experimental in my series.  (The timelines
were originally compatible with Xen 4.21, but access to hardware has not
been as forthcoming as hoped.)

When I can test on real hardware, there may be bugfixes, and I may be
able to upgrade the status if we're not too far into the RCs.
    
    
    
    
    Sounds good to me. Let’s wait until you’re able to test it on real hardware.
We’ll have some extra time during the Feature Freeze period, and the RCs
will be moved as well. I’ll announce this a little later today.

~ Oleksii


    
    
    
      
    
~Andrew

    
    
    
  


--------------mvC54Y60ARKGqTcDKCs3snMe--


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From: "Teddy Astie" 
Subject: =?utf-8?Q?[PATCH=20v2=200/3]=20Update=20to=20SMBIOS=202.6?=
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First patch clarify the Xen guest handle definition as being a big
endian UUID. The second does update to SMBIOS 2.6, writing a proper
UUID in the table.

Teddy Astie (3):
  xen: Define xen_domain_handle_t encoding and formatting
  hvmloader: Update to SMBIOS 2.6
  CHANGELOG.md: Add SMBIOS 2.6 update statement

 CHANGELOG.md                            |  2 +
 tools/firmware/hvmloader/smbios.c       | 50 ++++++++++++++++++++-----
 tools/firmware/hvmloader/smbios_types.h |  9 +++++
 xen/include/public/xen.h                |  7 ++++
 4 files changed, 59 insertions(+), 9 deletions(-)

-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[PATCH=20v2=201/3]=20xen:=20Define=20xen=5Fdomain=5Fhandle=5Ft=20encoding=20and=20formatting?=
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xen_domain_handle_t is defined as a opaque 16-bytes blob, but is
commonly used by toolstack and guest as a big-endian encoded and
formatted UUID (alike RFC 9562).

Clarify the definition of the type to ensure the guest and toolstack
interprets this value correctly in a way consistent with existing users
(at least with XAPI, xl, libvirt, hvmloader and Linux).

Fixes: 30ce2a9295a5 ("Store an opaque handle (tools uuid) in the domain structure")
Suggested-by: Andrew Cooper 
Signed-off-by: Teddy Astie 
---
v2:
 - introduced
---
 CHANGELOG.md             | 1 +
 xen/include/public/xen.h | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index cd34ea87b8..8c4435c181 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -11,6 +11,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - For x86, GCC 5.1 and Binutils 2.25, or Clang/LLVM 11
    - For ARM32 and ARM64, GCC 5.1 and Binutils 2.25
  - Linux based device model stubdomains are now fully supported.
+ - Clarify guest UUIDs as being big-endian encoded.
 
  - On x86:
    - Restrict the cache flushing done as a result of guest physical memory map
diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
index 82b9c05a76..a219ef870f 100644
--- a/xen/include/public/xen.h
+++ b/xen/include/public/xen.h
@@ -973,6 +973,13 @@ typedef struct dom0_vga_console_info {
 #define xen_vga_console_info dom0_vga_console_info
 #define xen_vga_console_info_t dom0_vga_console_info_t
 
+/*
+ * The domain handle is chosen by the toolstack, and intended to hold a UUID
+ * conforming to RFC 9562 (i.e. big endian).
+ *
+ * Certain cases (e.g. SMBios) transform it to a Microsoft GUID (little
+ * endian) for presentation to the guest.
+ */
 typedef uint8_t xen_domain_handle_t[16];
 
 __DEFINE_XEN_GUEST_HANDLE(uint8,  uint8_t);
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[PATCH=20v2=202/3]=20hvmloader:=20Update=20to=20SMBIOS=202.6?=
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Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).

In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
(undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
you have a endian mismatch causing the UUIDs to mismatch in the guest.

$ cat /sys/hypervisor/uuid
e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
$ cat /sys/devices/virtual/dmi/id/product_uuid
3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
$ cat /sys/devices/virtual/dmi/id/product_serial
e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7

This patch updates the SMBIOS version from 2.4 to 2.6 and does the appropriate
modifications of the table. This effectively fix this endianness mismatch with
OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.

Fixes: c683914ef913 ("Add code to generate SMBIOS tables to hvmloader.")
(SMBIOS versions before 2.6 has a ill-defined UUID definition)
Signed-off-by: Teddy Astie 
---
v2:
 - rebase onto staging
 - introduce missing SMBIOS 2.5-2.6 fields
 - check for new SMBIOS 2.6 table lengths
 - update UUID conversion comment
 - add Fixes: note
---
 tools/firmware/hvmloader/smbios.c       | 50 ++++++++++++++++++++-----
 tools/firmware/hvmloader/smbios_types.h |  9 +++++
 2 files changed, 50 insertions(+), 9 deletions(-)

diff --git a/tools/firmware/hvmloader/smbios.c b/tools/firmware/hvmloader/smbios.c
index 76c7090d16..e445475d78 100644
--- a/tools/firmware/hvmloader/smbios.c
+++ b/tools/firmware/hvmloader/smbios.c
@@ -396,7 +396,7 @@ smbios_entry_point_init(void *start,
     memcpy(ep->anchor_string, "_SM_", 4);
     ep->length = 0x1f;
     ep->smbios_major_version = 2;
-    ep->smbios_minor_version = 4;
+    ep->smbios_minor_version = 6;
     ep->max_structure_size = max_structure_size;
     ep->entry_point_revision = 0;
     memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
@@ -505,7 +505,22 @@ smbios_type_1_init(void *start, const char *xen_version,
     p->version_str = 3;
     p->serial_number_str = 4;
 
-    memcpy(p->uuid, uuid, 16);
+    /*
+     * Xen toolstack uses big endian UUIDs, however GUIDs (which requirement
+     * is clarified by SMBIOS >= 2.6) has the first 3 components appearing as
+     * being little endian and the rest as still being big endian.
+     */
+    /* First component */
+    for ( unsigned int i = 0; i < 4; i++ )
+        p->uuid[i] = uuid[4 - i - 1];
+    /* Second component */
+    p->uuid[4] = uuid[5];
+    p->uuid[5] = uuid[4];
+    /* Third component */
+    p->uuid[6] = uuid[7];
+    p->uuid[7] = uuid[6];
+    /* Rest */
+    memcpy(p->uuid + 8, uuid + 8, 8);
 
     p->wake_up_type = 0x06; /* power switch */
     p->sku_str = 0;
@@ -705,8 +720,8 @@ smbios_type_4_init(
     struct smbios_type_4 *p = start;
     uint32_t eax, ebx, ecx, edx;
 
-    /* Specification says Type 4 table has length of 23h for v2.3+. */
-    BUILD_BUG_ON(sizeof(*p) != 35);
+    /* Specification says Type 4 table has length of 2Ah for v2.6. */
+    BUILD_BUG_ON(sizeof(*p) != 42);
 
     memset(p, 0, sizeof(*p));
 
@@ -716,7 +731,7 @@ smbios_type_4_init(
 
     p->socket_designation_str = 1;
     p->processor_type = 0x03; /* CPU */
-    p->processor_family = 0x01; /* other */
+    p->processor_family = p->processor_family_2 = 0x01; /* other */
     p->manufacturer_str = 2;
 
     cpuid(1, &eax, &ebx, &ecx, &edx);
@@ -736,6 +751,22 @@ smbios_type_4_init(
     p->l2_cache_handle = 0xffff; /* No cache information structure provided. */
     p->l3_cache_handle = 0xffff; /* No cache information structure provided. */
 
+    /*
+     * We have a smbios type 4 table per vCPU (which is per socket),
+     * which means here that we have 1 socket per vCPU.
+     */
+    p->core_count = p->core_enabled = p->thread_count = 1;
+
+    /*
+     * We set 64-bits, execute protection and enhanced virtualization.
+     * We don't set Multi-Core (bit 3) because this individual processor
+     * (as being a single vCPU) is only having one core.
+     *
+     * SMBIOS specification says that these bits don't state anything
+     * regarding the actual availability of such features.
+     */
+    p->processor_characteristics = 0x64;
+
     start += sizeof(*p);
 
     strncpy(buf, "CPU ", sizeof(buf));
@@ -780,8 +811,8 @@ smbios_type_8_init(void *start)
 static void *
 smbios_type_9_init(void *start)
 {
-    /* Specification says Type 9 table has length of 0Dh for v2.1-2.5. */
-    BUILD_BUG_ON(sizeof(struct smbios_type_9) != 13);
+    /* Specification says Type 9 table has length of 11h for v2.6+. */
+    BUILD_BUG_ON(sizeof(struct smbios_type_9) != 17);
 
     /* Only present when passed in. */
     return smbios_pt_copy(start, 9, SMBIOS_HANDLE_TYPE9,
@@ -870,8 +901,8 @@ smbios_type_17_init(void *start, uint32_t memory_size_mb, int instance)
     char buf[16];
     struct smbios_type_17 *p = start;
 
-    /* Specification says Type 17 table has length of 1Bh for v2.3-2.6. */
-    BUILD_BUG_ON(sizeof(*p) != 27);
+    /* Specification says Type 17 table has length of 1Ch for v2.6. */
+    BUILD_BUG_ON(sizeof(*p) != 28);
 
     memset(p, 0, sizeof(*p));
 
@@ -890,6 +921,7 @@ smbios_type_17_init(void *start, uint32_t memory_size_mb, int instance)
     p->bank_locator_str = 0;
     p->memory_type = 0x07; /* RAM */
     p->type_detail = 0;
+    p->attributes = 0;
 
     start += sizeof(*p);
     strcpy(start, "DIMM ");
diff --git a/tools/firmware/hvmloader/smbios_types.h b/tools/firmware/hvmloader/smbios_types.h
index c04b435d31..860617d86a 100644
--- a/tools/firmware/hvmloader/smbios_types.h
+++ b/tools/firmware/hvmloader/smbios_types.h
@@ -147,6 +147,11 @@ struct smbios_type_4 {
     uint8_t serial_number_str;
     uint8_t asset_tag_str;
     uint8_t part_number_str;
+    uint8_t core_count;
+    uint8_t core_enabled;
+    uint8_t thread_count;
+    uint16_t processor_characteristics;
+    uint16_t processor_family_2;
 } __attribute__ ((packed));
 
 /* SMBIOS type 7 - Cache Information */
@@ -185,6 +190,9 @@ struct smbios_type_9 {
     uint16_t slot_id;
     uint8_t slot_characteristics_1;
     uint8_t slot_characteristics_2;
+    uint16_t sgn_base;
+    uint8_t bus_number_base;
+    uint8_t devfn_base;
 } __attribute__ ((packed));
 
 /* SMBIOS type 11 - OEM Strings */
@@ -227,6 +235,7 @@ struct smbios_type_17 {
     uint8_t serial_number_str;
     uint8_t asset_tag_str;
     uint8_t part_number_str;
+    uint8_t attributes;
 } __attribute__ ((packed));
 
 /* SMBIOS type 19 - Memory Array Mapped Address */
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[PATCH=20v2=203/3]=20CHANGELOG.md:=20Add=20SMBIOS=202.6=20update=20statement?=
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Signed-off-by: Teddy Astie 
---
v2:
 - introduced
---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8c4435c181..80a8273d7e 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -34,6 +34,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - Support in hvmloader for new SMBIOS tables: 7 (Cache Info), 8 (Port
      Connector), 9 (System Slots), 26 (Voltage Probe), 27 (Cooling Device),
      and 28 (Temperature Probe).
+   - Updated SMBIOS version to 2.6.
 
  - On Arm:
     - Ability to enable stack protector
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: Oleksii Moisieiev 
To: Stefano Stabellini 
CC: "xen-devel@lists.xenproject.org" , Andrew
 Cooper , Anthony PERARD
	, Bertrand Marquis , Jan
 Beulich , Juergen Gross , Julien Grall
	, Michal Orzel ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Volodymyr
 Babchuk , Grygorii Strashko
	
Subject: Re: [RFC PATCH v5 01/10] xen/arm: add generic SCI subsystem
Thread-Topic: [RFC PATCH v5 01/10] xen/arm: add generic SCI subsystem
Thread-Index: AQHb+v2VIVqDwzw580eWg2MNhp5UUrRvkxEAgAi7TgA=
Date: Thu, 28 Aug 2025 13:46:38 +0000
Message-ID: <6d0cf3fb-2e51-491f-98a3-94d7ee48f881@epam.com>
References: 
 
 
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Date: Thu, 28 Aug 2025 10:49:27 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 06/16] iommu/dma: extend iommu_dma_*map_phys API to
 handle MMIO memory
Message-ID: <20250828134927.GE9469@nvidia.com>
References: 
 <4f84639baf6d5d0e107fd2001dff91b6538ff9ae.1755624249.git.leon@kernel.org>
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On Tue, Aug 19, 2025 at 08:36:50PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Combine iommu_dma_*map_phys with iommu_dma_*map_resource interfaces in
> order to allow single phys_addr_t flow.
> 
> In the following patches, the iommu_dma_map_resource() will be removed
> in favour of iommu_dma_map_phys(..., attrs | DMA_ATTR_MMIO) flow.

I would reword this a little bit

iommu/dma: implement DMA_ATTR_MMIO for iommu_dma_(un)map_phys()

Make iommu_dma_map_phys() and iommu_dma_unmap_phys() respect
DMA_ATTR_MMIO.

DMA_ATTR_MMIO makes the functions behave the same as
iommu_dma_(un)map_resource():
 - No swiotlb is possible
 - No cache flushing is done (ATTR_MMIO should not be cached memory)
 - prot for iommu_map() has IOMMU_MMIO not IOMMU_CACHE 

This is preperation for replacing iommu_dma_map_resource() callers
with iommu_dma_map_phys(DMA_ATTR_MMIO) and removing
iommu_dma_(un)map_resource().

Reviewed-by: Jason Gunthorpe 

Jason


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Subject: Re: [Reminder] Feature Freeze is Fri Aug 29, 2025
From: Oleksii Kurochko 
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Hello Community,

Considering the number of requests in this mailing thread,
I think it makes sense to extend the Feature Freeze period
by at least one week, moving the deadline to September 5th.

I will send a separate e-mail with that information.

Thanks, everyone, for your responses.

~ Oleksii

On 8/25/25 5:50 PM, Oleksii Kurochko wrote:
> Hello community,
>
> I’d like to remind everyone that the Feature Freeze deadline is approaching,
> and we still have some outstanding requests from the community for patch series
> to be merged into 4.21:
>
> 1. Enable guest suspend/resume support on ARM via vPSCI [1]
> 2. Introduce SCI SCMI SMC multi-agent support [2]
> 3. Introduce eSPI support [3]
> 4. FRED work: [4], [5], possibly others (?)
> 5. Introduce CONFIG_DOMCTL [6]
> 6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
> 7. Some other patch series I missed.
>
> It looks like some of these patch series still require additional work,
> and I’m not sure there is enough time left before the end of this week.
>
> Could I kindly ask for an estimation of whether these tasks can be completed in time?
>
> [1]https://lore.kernel.org/xen-devel/87jz2vaq9h.fsf@epam.com/
> [2]https://lore.kernel.org/xen-devel/cover.1753184487.git.oleksii_moisieiev@epam.com/
> [3]https://lore.kernel.org/xen-devel/7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com/
>
> [4]https://lore.kernel.org/xen-devel/20250808202314.1045968-1-andrew.cooper3@citrix.com/
> [5]https://lore.kernel.org/xen-devel/20250815204117.3312742-1-andrew.cooper3@citrix.com/
>
> [6]https://lore.kernel.org/xen-devel/20250803094738.3625269-6-Penny.Zheng@amd.com/
> [7]https://lore.kernel.org/xen-devel/20250815102728.1340505-1-Penny.Zheng@amd.com/
>
> Thanks in advance.
>
> Best regards,
>    Oleksii
--------------lvBzz3KMKY0YXl6XLxXq5XHg
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: 8bit



  
    
  
  
    
    Hello Community,
    
    
    Considering the number of requests in this mailing thread,
I think it makes sense to extend the Feature Freeze period
by at least one week, moving the deadline to September 5th.
    
    
    I will send a separate e-mail with that information.
    
    
    Thanks, everyone, for your responses.
    
    
    ~ Oleksii
    
    
    
    
    On 8/25/25 5:50 PM, Oleksii Kurochko
      wrote:
    
    
    
    
    
      
      
    Hello community,

I’d like to remind everyone that the Feature Freeze deadline is approaching,
and we still have some outstanding requests from the community for patch series
to be merged into 4.21:

1. Enable guest suspend/resume support on ARM via vPSCI [1]
2. Introduce SCI SCMI SMC multi-agent support [2]
3. Introduce eSPI support [3]
4. FRED work: [4], [5], possibly others (?)
5. Introduce CONFIG_DOMCTL [6]
6. xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE [7]
7. Some other patch series I missed.

It looks like some of these patch series still require additional work,
and I’m not sure there is enough time left before the end of this week.

Could I kindly ask for an estimation of whether these tasks can be completed in time?

[1] https://lore.kernel.org/xen-devel/87jz2vaq9h.fsf@epam.com/
[2] https://lore.kernel.org/xen-devel/cover.1753184487.git.oleksii_moisieiev@epam.com/
[3] https://lore.kernel.org/xen-devel/7e6477a83ab65220ef1c5dd22f4ef3536fbbdd5c.1754568795.git.leonid_komarianskyi@epam.com/

[4] https://lore.kernel.org/xen-devel/20250808202314.1045968-1-andrew.cooper3@citrix.com/
[5] https://lore.kernel.org/xen-devel/20250815204117.3312742-1-andrew.cooper3@citrix.com/

[6] https://lore.kernel.org/xen-devel/20250803094738.3625269-6-Penny.Zheng@amd.com/
[7] https://lore.kernel.org/xen-devel/20250815102728.1340505-1-Penny.Zheng@amd.com/

Thanks in advance.

Best regards,
  Oleksii

    
    
    
  


--------------lvBzz3KMKY0YXl6XLxXq5XHg--


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Subject: Re: [PATCH v4 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
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 <864522724dd6058952cad8b505b0589750b7f8d7.1756317702.git.leonid_komarianskyi@epam.com>
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From: Oleksandr Tyshchenko 
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On 27.08.25 21:24, Leonid Komarianskyi wrote:

Hello Leonid


> Introduced appropriate register definitions, helper macros,
> and initialization of required GICv3.1 distributor registers
> to support eSPI. This type of interrupt is handled in the
> same way as regular SPI interrupts, with the following
> differences:
> 
> 1) eSPIs can have up to 1024 interrupts, starting from the
> beginning of the range, whereas regular SPIs use INTIDs from
> 32 to 1019, totaling 988 interrupts;
> 2) eSPIs start at INTID 4096, necessitating additional interrupt
> index conversion during register operations.
> 
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
> 
> Signed-off-by: Leonid Komarianskyi 
> Reviewed-by: Volodymyr Babchuk 
> 
> ---
> Changes in V4:
> - added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
>    for vGIC emulation
> - added a log banner with eSPI information, similar to the one for
>    regular SPI
> - added newline after ifdef and before gic_is_valid_line
> - added reviewed-by from Volodymyr Babchuk

only NITs below

Reviewed-by: Oleksandr Tyshchenko 

> 
> Changes in V3:
> - add __init attribute to gicv3_dist_espi_common_init
> - change open-codded eSPI register initialization to the appropriate
>    gen-mask macro
> - fixed formatting for lines with more than 80 symbols
> - introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
>    CONFIG_GICV3_ESPI disabled
> - renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
>    (name was taken from GIC specification) to avoid confusion
> - changed type for i variable to unsigned int since it cannot be
>    negative
> 
> Changes in V2:
> - move gic_number_espis function from
>    [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
>    to use it in the newly introduced gic_is_valid_espi
> - add gic_is_valid_espi which checks if IRQ number is in supported
>    by HW eSPI range
> - update gic_is_valid_irq conditions to allow operations with eSPIs
> 
> Changes for V4:
> 
> Changes in V4:
> - added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
>    for vGIC emulation
> - added newline after ifdef and before gic_is_valid_line
> - added reviewed-by from Volodymyr Babchuk
> - added a log banner with eSPI information, similar to the one for
>    regular SPI
> ---
>   xen/arch/arm/gic-v3.c                  | 82 ++++++++++++++++++++++++++
>   xen/arch/arm/include/asm/gic.h         | 22 +++++++
>   xen/arch/arm/include/asm/gic_v3_defs.h | 38 ++++++++++++
>   3 files changed, 142 insertions(+)
> 
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index a959fefebe..b939a1f490 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
>           default:
>               break;
>           }
> +#ifdef CONFIG_GICV3_ESPI
> +    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
> +    {
> +        u32 irq_index = ESPI_INTID2IDX(irqd->irq);

NIT: I have heard that no uN for new code, but uintN_t (sorry for didn't 
spot this before), so I would use uint32_t


> +
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ICENABLER:
> +            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ISPENDR:
> +            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ICPENDR:
> +            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ISACTIVER:
> +            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICACTIVER:
> +            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTERnE + irq_index * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYRnE + irq_index);
> +        default:
> +            break;
> +        }
> +    }
> +#endif
>       default:
>           break;
>       }
> @@ -655,6 +685,54 @@ static void gicv3_set_irq_priority(struct irq_desc *desc,
>       spin_unlock(&gicv3.lock);
>   }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +unsigned int gic_number_espis(void)
> +{
> +    return gic_hw_ops->info->nr_espi;
> +}
> +
> +static void __init gicv3_dist_espi_common_init(uint32_t type)
> +{
> +    unsigned int espi_nr, i;
> +
> +    espi_nr = min(1024U, GICD_TYPER_ESPIS_NUM(type));
> +    gicv3_info.nr_espi = espi_nr;
> +    /* The GIC HW doesn't support eSPI, so we can leave from here */
> +    if ( gicv3_info.nr_espi == 0 )
> +        return;
> +
> +    printk("GICv3: %d eSPI lines\n", gicv3_info.nr_espi);
> +
> +    for ( i = 0; i < espi_nr; i += 16 )
> +        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
> +
> +    for ( i = 0; i < espi_nr; i += 4 )
> +        writel_relaxed(GIC_PRI_IRQ_ALL,
> +                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
> +
> +    for ( i = 0; i < espi_nr; i += 32 )
> +    {
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i / 32) * 4);
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i / 32) * 4);
> +    }
> +
> +    for ( i = 0; i < espi_nr; i += 32 )
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) * 4);

NIT: From what I see, the eSPIs are configured exactly as regular SPIs 
in gicv3_dist_init() (i.e. the eSPIs are level-triggered, disabled and 
deactivated, belong to the same group, etc). In gicv3_dist_init() we 
have comments clarying the actions, but here we do not. I would at least 
write a sentence in patch description/in-code comment saying that eSPIs 
configuration is the same as for regular SPIs.


> +}
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
> +{
> +    unsigned int i;
> +
> +    for ( i = 0; i < gicv3_info.nr_espi; i++ )
> +        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * 8);
> +}
> +#else
> +static void __init gicv3_dist_espi_common_init(uint32_t type) { }
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
> +#endif
> +
>   static void __init gicv3_dist_init(void)
>   {
>       uint32_t type;
> @@ -700,6 +778,8 @@ static void __init gicv3_dist_init(void)
>       for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
>           writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4);
>   
> +    gicv3_dist_espi_common_init(type);
> +
>       gicv3_dist_wait_for_rwp();
>   
>       /* Turn on the distributor */
> @@ -713,6 +793,8 @@ static void __init gicv3_dist_init(void)
>   
>       for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
>           writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8);
> +
> +    gicv3_dist_espi_init_aff(affinity);
>   }
>   
>   static int gicv3_enable_redist(void)


[snip]



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Date: Thu, 28 Aug 2025 11:19:58 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky ,
	Suzuki K Poulose ,
	Alexey Kardashevskiy 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 07/16] dma-mapping: convert dma_direct_*map_page to be
 phys_addr_t based
Message-ID: <20250828141958.GF9469@nvidia.com>
References: 
 <3faa9c978e243a904ffe01496148c4563dc9274e.1755624249.git.leon@kernel.org>
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On Tue, Aug 19, 2025 at 08:36:51PM +0300, Leon Romanovsky wrote:
> +static inline dma_addr_t dma_direct_map_phys(struct device *dev,
> +		phys_addr_t phys, size_t size, enum dma_data_direction dir,
> +		unsigned long attrs)
>  {
> -	phys_addr_t phys = page_to_phys(page) + offset;
> -	dma_addr_t dma_addr = phys_to_dma(dev, phys);
> +	dma_addr_t dma_addr;
> +	bool capable;
>  
>  	if (is_swiotlb_force_bounce(dev)) {
> -		if (is_pci_p2pdma_page(page))
> -			return DMA_MAPPING_ERROR;
> +		if (attrs & DMA_ATTR_MMIO)
> +			goto err_overflow;
> +
>  		return swiotlb_map(dev, phys, size, dir, attrs);
>  	}
>  
> -	if (unlikely(!dma_capable(dev, dma_addr, size, true)) ||
> -	    dma_kmalloc_needs_bounce(dev, size, dir)) {
> -		if (is_pci_p2pdma_page(page))
> -			return DMA_MAPPING_ERROR;
> -		if (is_swiotlb_active(dev))
> +	if (attrs & DMA_ATTR_MMIO)
> +		dma_addr = phys;
> +	else
> +		dma_addr = phys_to_dma(dev, phys);

I've been trying to unpuzzle this CC related mess for a while and
still am unsure what is right here... But judging from the comments I
think this should always call phys_to_dma(). Though I understand the
existing map_resource path didn't call it so it would also be fine to
leave it like this..

Alexey do you know?

The only time this seems to do anything is on AMD and I have no idea
what AMD has done to their CC memory map with the iommu..

On ARM at least I would expect the DMA API to be dealing only with
canonical IPA, ie if the memory is encrpyted it is in the protect IPA
region, if it is decrypted then it is in the unprotected IPA region.

I think some of this 'dma encrypted' 'dma unencrypted' stuff is a bit
confused, at least on ARM, as I would expect the caller to have a
correct phys_addr_t with the correct IPA aliases already. Passing in
an ambiguous struct page for DMA mapping and then magically fixing it
seems really weird to me. I would expect that a correct phys_addr_t
should just translate 1:1 to a dma_addr_t or an iopte. Suzuki is that
the right idea for ARM?

To that end this series seems like a big improvment for CCA as the
caller can now specify either the protected or unprotected IPA
directly instead of an ambiguous struct page.

One of the things we are going to need for bounce buffering devices
like RDMA is to be able to allocate unencrypted folios, mmap them to
userspace, come back and then dma map them as unencrypted into a
MR.

So it looks to me like this series will be important for this use case
as well.

It looks OK though:

Reviewed-by: Jason Gunthorpe 

Jason


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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Anthony PERARD ,
	Juergen Gross 
Subject: [PATCH v11 2/4] tools/xl: Allow compilation of 'xl resume' command on Arm
Date: Thu, 28 Aug 2025 17:54:05 +0300
Message-ID: <71189bf8f220b678829b8d58f4aa9a4877156eb4.1756392094.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

The "xl resume" command was previously excluded from Arm builds because
system suspend/resume (e.g., SYSTEM_SUSPEND via vPSCI) was not
implemented. On x86, this command is used for resume.

This change enables compilation of `xl resume` on Arm regardless of the
underlying implementation status, making the tool available for testing
and future feature support. The relevant libxl infrastructure and handler
functions are already present and usable.

Note: This does not imply full system suspend/resume support on Arm.
      The `xl suspend` command still does not work on Arm platforms.

Signed-off-by: Mykola Kvach 
Acked-by: Anthony PERARD 
---
Changes in v7:
- dropped renaming of LIBXL_HAVE_NO_SUSPEND_RESUME macro

Changes in v6:
- Renamed macro from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND
  to better reflect the scope of this change
- Applied cosmetic changes based on review feedback
---
 tools/include/libxl.h     |  1 -
 tools/xl/xl.h             |  4 ++--
 tools/xl/xl_cmdtable.c    |  4 ++--
 tools/xl/xl_migrate.c     |  2 +-
 tools/xl/xl_saverestore.c |  2 +-
 tools/xl/xl_vmcontrol.c   | 12 ++++++------
 6 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/tools/include/libxl.h b/tools/include/libxl.h
index 185f74d8a8..b204fc5e2e 100644
--- a/tools/include/libxl.h
+++ b/tools/include/libxl.h
@@ -1140,7 +1140,6 @@ typedef struct libxl__ctx libxl_ctx;
  * restoring or migrating a domain. In this case the related functions
  * should be expected to return failure. That is:
  *  - libxl_domain_suspend
- *  - libxl_domain_resume
  *  - libxl_domain_remus_start
  */
 #if defined(__arm__) || defined(__aarch64__)
diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index 45745f0dbb..9233b73f85 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -65,7 +65,7 @@ static const char migrate_permission_to_go[]=
     "domain is yours, you are cleared to unpause";
 static const char migrate_report[]=
     "my copy unpause results are as follows";
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
   /* followed by one byte:
    *     0: everything went well, domain is running
@@ -130,8 +130,8 @@ int main_migrate_receive(int argc, char **argv);
 int main_save(int argc, char **argv);
 int main_migrate(int argc, char **argv);
 int main_suspend(int argc, char **argv);
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 int main_resume(int argc, char **argv);
-#endif
 int main_dump_core(int argc, char **argv);
 int main_pause(int argc, char **argv);
 int main_unpause(int argc, char **argv);
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 06a0039718..bcb2d233cc 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -198,12 +198,12 @@ const struct cmd_spec cmd_table[] = {
       "Suspend a domain to RAM",
       "",
     },
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "resume",
       &main_resume, 0, 1,
       "Resume a domain from RAM",
       "",
     },
-#endif
     { "dump-core",
       &main_dump_core, 0, 1,
       "Core dump a domain",
@@ -548,7 +548,7 @@ const struct cmd_spec cmd_table[] = {
       "                        checkpoint must be disabled.\n"
       "-p                      Use COLO userspace proxy."
     },
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "devd",
       &main_devd, 0, 1,
       "Daemon that listens for devices and launches backends",
diff --git a/tools/xl/xl_migrate.c b/tools/xl/xl_migrate.c
index b8594f44a5..4b4a379aa1 100644
--- a/tools/xl/xl_migrate.c
+++ b/tools/xl/xl_migrate.c
@@ -767,7 +767,7 @@ int main_remus(int argc, char **argv)
     close(send_fd);
     return EXIT_FAILURE;
 }
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 /*
diff --git a/tools/xl/xl_saverestore.c b/tools/xl/xl_saverestore.c
index 953d791d1a..747094ec7b 100644
--- a/tools/xl/xl_saverestore.c
+++ b/tools/xl/xl_saverestore.c
@@ -270,7 +270,7 @@ int main_save(int argc, char **argv)
     return EXIT_SUCCESS;
 }
 
-#endif /* LIBXL_HAVE_NO_SUSPEND_RESUME */
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 
diff --git a/tools/xl/xl_vmcontrol.c b/tools/xl/xl_vmcontrol.c
index c813732838..93766f631b 100644
--- a/tools/xl/xl_vmcontrol.c
+++ b/tools/xl/xl_vmcontrol.c
@@ -38,11 +38,6 @@ static void suspend_domain(uint32_t domid)
     libxl_domain_suspend_only(ctx, domid, NULL);
 }
 
-static void resume_domain(uint32_t domid)
-{
-    libxl_domain_resume(ctx, domid, 1, NULL);
-}
-
 int main_suspend(int argc, char **argv)
 {
     int opt;
@@ -55,6 +50,12 @@ int main_suspend(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
+
+static void resume_domain(uint32_t domid)
+{
+    libxl_domain_resume(ctx, domid, 1, NULL);
+}
 
 int main_resume(int argc, char **argv)
 {
@@ -68,7 +69,6 @@ int main_resume(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
-#endif
 
 static void pause_domain(uint32_t domid)
 {
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Shawn Anastasio ,
	Alistair Francis ,
	Bob Eshleman ,
	Connor Davis ,
	Oleksii Kurochko 
Subject: [PATCH v11 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
Date: Thu, 28 Aug 2025 17:54:04 +0300
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From: Mykola Kvach 

Add support for the PSCI SYSTEM_SUSPEND function in the vPSCI interface,
allowing guests to request suspend via the PSCI v1.0 SYSTEM_SUSPEND call
(both 32-bit and 64-bit variants).

Implementation details:
- Add SYSTEM_SUSPEND function IDs to PSCI definitions
- Trap and handle SYSTEM_SUSPEND in vPSCI
- Allow only non-hardware domains to invoke SYSTEM_SUSPEND; return
  PSCI_NOT_SUPPORTED for the hardware domain to avoid halting the system
  in hwdom_shutdown() via domain_shutdown
- Require all secondary VCPUs of the calling domain to be offline before
  suspend, as mandated by the PSCI specification

The arch_domain_resume() function is an architecture-specific hook that is
invoked during domain resume to perform any necessary setup or restoration
steps required by the platform.

The new vpsci_vcpu_up_prepare() helper is called on the resume path to set up
the vCPU context (such as entry point, some system regs and context ID) before
resuming a suspended guest. This keeps ARM/vPSCI-specific logic out of common
code and avoids intrusive changes to the generic resume flow.

Usage:

For Linux-based guests, suspend can be initiated with:
    echo mem > /sys/power/state
or via:
    systemctl suspend

Resuming the guest is performed from control domain using:
      xl resume 

Signed-off-by: Mykola Kvach 
---
Changes in V11:
- introduce arch_domain_resume() and vpsci_vcpu_up_prepare(), which are now
called on the resume path to avoid extra modifications to common code.
The vCPU context is now updated during domain resume.

Changes in V10:
- small changes to the commit message reflect updates introduced in this
  version of the patch.
- Comments are improved, clarified, and expanded, especially regarding PSCI
  requirements and context handling.
- An ARM-specific helper (domain_resume_nopause_helper)
- gprintk() and PRIregister are used for logging in vPSCI code.
- An isb() is added before p2m_save_state
- The is_64bit_domain check is dropped when masking the upper part of entry
  point and cid for SMC32 SYSTEM_SUSPEND PSCI calls

Changes in V9:
- no functional changes
- cosmetic chnages after review
- enhance commit message and add extra comment to the code after review

Changes in V8:
- GIC and virtual timer context must be saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Changes in V6:
- skip execution of ctxt_switch_from for vcpu that is in paused domain
- add implementation of domain_resume without domain_pause
- add helper function to determine if vcpu is suspended or not
- ignore upper 32 bits of argument values when the domain is 64-bit
  and calls the SMC32 SYSTEM_SUSPEND function
- cosmetic changes after review

Changes in V5:
- don't use standby mode, restore execution in a provided by guest point
- move checking that all CPUs, except current one, are offline to after
  pausing the vCPUs
- provide ret status from arch_domain_shutdown and handle it in
  domain_shutdown
- adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI functions

Changes in V4:
Dropped all changes related to watchdog, domain is marked as shutting
down in domain_shutdown and watchdog timeout handler won't trigger
because of it.

Previous versions included code to manage Xen watchdog timers during suspend,
but this was removed. When a guest OS starts the Xen watchdog (either via the
kernel driver or xenwatchdogd), it is responsible for managing that state
across suspend/resume. On Linux, the Xen kernel driver properly stops the
watchdog during suspend. However, when xenwatchdogd is used instead, suspend
handling is incomplete, potentially leading to watchdog-triggered resets on
resume. Xen leaves watchdog handling to the guest OS and its services.

Dropped all changes related to VCPU context, because instead domain_shutdown
is used, so we don't need any extra changes for suspending domain.

Changes in V3:
Dropped all domain flags and related code (which touched common functions like
vcpu_unblock), keeping only the necessary changes for Xen suspend/resume, i.e.
suspend/resume is now fully supported only for the hardware domain.
Proper support for domU suspend/resume will be added in a future patch.
This patch does not yet include VCPU context reset or domain context
restoration in VCPU.
---
 xen/arch/arm/domain.c                 |  22 +++++
 xen/arch/arm/include/asm/domain.h     |   6 ++
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   5 +-
 xen/arch/arm/vpsci.c                  | 114 +++++++++++++++++++++-----
 xen/arch/ppc/stubs.c                  |   5 ++
 xen/arch/riscv/stubs.c                |   5 ++
 xen/arch/x86/domain.c                 |   5 ++
 xen/common/domain.c                   |   9 ++
 xen/include/xen/domain.h              |   2 +
 11 files changed, 156 insertions(+), 20 deletions(-)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 863ae18157..6fd73eedde 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -12,6 +12,8 @@
 #include 
 #include 
 
+#include 
+
 #include 
 #include 
 #include 
@@ -27,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "vpci.h"
@@ -880,6 +883,25 @@ void arch_domain_creation_finished(struct domain *d)
     p2m_domain_creation_finished(d);
 }
 
+int arch_domain_resume(struct domain *d)
+{
+    int rc;
+    typeof(d->arch.resume_ctx) *ctx = &d->arch.resume_ctx;
+
+    if ( !d->is_shutting_down || d->shutdown_code != SHUTDOWN_suspend )
+    {
+        dprintk(XENLOG_WARNING,
+                "%pd: Invalid domain state for resume: is_shutting_down=%d, shutdown_code=%d\n",
+                d, d->is_shutting_down, d->shutdown_code);
+        return -EINVAL;
+    }
+
+    rc = vpsci_vcpu_up_prepare(ctx->wake_cpu , ctx->ep, ctx->cid);
+    memset(ctx, 0, sizeof(*ctx));
+
+    return rc;
+}
+
 static int is_guest_pv32_psr(uint32_t psr)
 {
     switch (psr & PSR_MODE_MASK)
diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
index a3487ca713..68185fc4d6 100644
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -121,6 +121,12 @@ struct arch_domain
     void *tee;
 #endif
 
+    struct resume_info {
+        register_t ep;
+        register_t cid;
+        struct vcpu *wake_cpu;
+    } resume_ctx;
+
 }  __cacheline_aligned;
 
 struct arch_vcpu
diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/include/asm/perfc_defn.h
index effd25b69e..8dfcac7e3b 100644
--- a/xen/arch/arm/include/asm/perfc_defn.h
+++ b/xen/arch/arm/include/asm/perfc_defn.h
@@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system_reset")
 PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
 PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
 PERFCOUNTER(vpsci_features,            "vpsci: features")
+PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
 
 PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
 
diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/psci.h
index 4780972621..48a93e6b79 100644
--- a/xen/arch/arm/include/asm/psci.h
+++ b/xen/arch/arm/include/asm/psci.h
@@ -47,10 +47,12 @@ void call_psci_system_reset(void);
 #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
 #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
 #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
+#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
 
 #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
 #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
 #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
+#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
 
 /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
 #define PSCI_0_2_AFFINITY_LEVEL_ON      0
diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/asm/vpsci.h
index 0cca5e6830..d790ab3715 100644
--- a/xen/arch/arm/include/asm/vpsci.h
+++ b/xen/arch/arm/include/asm/vpsci.h
@@ -23,12 +23,15 @@
 #include 
 
 /* Number of function implemented by virtual PSCI (only 0.2 or later) */
-#define VPSCI_NR_FUNCS  12
+#define VPSCI_NR_FUNCS  14
 
 /* Functions handle PSCI calls from the guests */
 bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
 bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid);
 
+int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
+                          register_t context_id);
+
 #endif /* __ASM_VPSCI_H__ */
 
 /*
diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index 7ba9ccd94b..50cf5fd96c 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -10,30 +10,16 @@
 
 #include 
 
-static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
-                            register_t context_id)
+int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
+                   register_t context_id)
 {
-    struct vcpu *v;
-    struct domain *d = current->domain;
-    struct vcpu_guest_context *ctxt;
     int rc;
+    struct domain *d = current->domain;
     bool is_thumb = entry_point & 1;
-    register_t vcpuid;
-
-    vcpuid = vaffinity_to_vcpuid(target_cpu);
-
-    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
-        return PSCI_INVALID_PARAMETERS;
-
-    /* THUMB set is not allowed with 64-bit domain */
-    if ( is_64bit_domain(d) && is_thumb )
-        return PSCI_INVALID_ADDRESS;
-
-    if ( !test_bit(_VPF_down, &v->pause_flags) )
-        return PSCI_ALREADY_ON;
+    struct vcpu_guest_context *ctxt;
 
     if ( (ctxt = alloc_vcpu_guest_context()) == NULL )
-        return PSCI_DENIED;
+        return -ENOMEM;
 
     vgic_clear_pending_irqs(v);
 
@@ -76,8 +62,37 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
     free_vcpu_guest_context(ctxt);
 
     if ( rc < 0 )
+        return rc;
+
+    return 0;
+}
+
+static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
+                            register_t context_id)
+{
+    struct vcpu *v;
+    struct domain *d = current->domain;
+    int rc;
+    bool is_thumb = entry_point & 1;
+    register_t vcpuid;
+
+    vcpuid = vaffinity_to_vcpuid(target_cpu);
+
+    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
+        return PSCI_INVALID_PARAMETERS;
+
+    /* THUMB set is not allowed with 64-bit domain */
+    if ( is_64bit_domain(d) && is_thumb )
+        return PSCI_INVALID_ADDRESS;
+
+    if ( !test_bit(_VPF_down, &v->pause_flags) )
+        return PSCI_ALREADY_ON;
+
+    rc = vpsci_vcpu_up_prepare(v, entry_point, context_id);
+    if ( rc )
         return PSCI_DENIED;
 
+    vgic_clear_pending_irqs(v);
     vcpu_wake(v);
 
     return PSCI_SUCCESS;
@@ -197,6 +212,48 @@ static void do_psci_0_2_system_reset(void)
     domain_shutdown(d,SHUTDOWN_reboot);
 }
 
+static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid)
+{
+    int32_t rc;
+    struct vcpu *v;
+    struct domain *d = current->domain;
+    bool is_thumb = epoint & 1;
+
+    /* THUMB set is not allowed with 64-bit domain */
+    if ( is_64bit_domain(d) && is_thumb )
+        return PSCI_INVALID_ADDRESS;
+
+    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
+    if ( is_hardware_domain(d) )
+        return PSCI_NOT_SUPPORTED;
+
+    /* Ensure that all CPUs other than the calling one are offline */
+    domain_lock(d);
+    for_each_vcpu ( d, v )
+    {
+        if ( v != current && is_vcpu_online(v) )
+        {
+            domain_unlock(d);
+            return PSCI_DENIED;
+        }
+    }
+    domain_unlock(d);
+
+    rc = domain_shutdown(d, SHUTDOWN_suspend);
+    if ( rc )
+        return PSCI_DENIED;
+
+    d->arch.resume_ctx.ep = epoint;
+    d->arch.resume_ctx.cid = cid;
+    d->arch.resume_ctx.wake_cpu = current;
+
+    gprintk(XENLOG_DEBUG,
+            "SYSTEM_SUSPEND requested, epoint=0x%"PRIregister", cid=0x%"PRIregister,
+            epoint, cid);
+
+    return rc;
+}
+
 static int32_t do_psci_1_0_features(uint32_t psci_func_id)
 {
     /* /!\ Ordered by function ID and not name */
@@ -214,6 +271,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id)
     case PSCI_0_2_FN32_SYSTEM_OFF:
     case PSCI_0_2_FN32_SYSTEM_RESET:
     case PSCI_1_0_FN32_PSCI_FEATURES:
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
     case ARM_SMCCC_VERSION_FID:
         return 0;
     default:
@@ -344,6 +403,23 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
         return true;
     }
 
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
+    {
+        register_t epoint = PSCI_ARG(regs, 1);
+        register_t cid = PSCI_ARG(regs, 2);
+
+        if ( fid == PSCI_1_0_FN32_SYSTEM_SUSPEND )
+        {
+            epoint &= GENMASK(31, 0);
+            cid &= GENMASK(31, 0);
+        }
+
+        perfc_incr(vpsci_system_suspend);
+        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
+        return true;
+    }
+
     default:
         return false;
     }
diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c
index bdaf474c5c..0db0627b5c 100644
--- a/xen/arch/ppc/stubs.c
+++ b/xen/arch/ppc/stubs.c
@@ -224,6 +224,11 @@ void arch_domain_creation_finished(struct domain *d)
     BUG_ON("unimplemented");
 }
 
+int arch_domain_resume(struct domain *d)
+{
+    return 0;
+}
+
 int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
 {
     BUG_ON("unimplemented");
diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c
index 1a8c86cd8d..52532ae14d 100644
--- a/xen/arch/riscv/stubs.c
+++ b/xen/arch/riscv/stubs.c
@@ -198,6 +198,11 @@ void arch_domain_creation_finished(struct domain *d)
     BUG_ON("unimplemented");
 }
 
+int arch_domain_resume(struct domain *d)
+{
+    return 0;
+}
+
 int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
 {
     BUG_ON("unimplemented");
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 19fd86ce88..94a06bc697 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1138,6 +1138,11 @@ void arch_domain_creation_finished(struct domain *d)
         hvm_domain_creation_finished(d);
 }
 
+int arch_domain_resume(struct domain *d)
+{
+    return 0;
+}
+
 #ifdef CONFIG_COMPAT
 #define xen_vcpu_guest_context vcpu_guest_context
 #define fpu_ctxt fpu_ctxt.x
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 104e917f07..d73a88ced5 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -1352,6 +1352,7 @@ int domain_shutdown(struct domain *d, u8 reason)
 void domain_resume(struct domain *d)
 {
     struct vcpu *v;
+    int rc;
 
     /*
      * Some code paths assume that shutdown status does not get reset under
@@ -1359,6 +1360,14 @@ void domain_resume(struct domain *d)
      */
     domain_pause(d);
 
+    rc = arch_domain_resume(d);
+    if ( rc )
+    {
+        domain_unpause(d);
+        printk("%pd: Failed to resume domain (ret %d)\n", d, rc);
+        return;
+    }
+
     spin_lock(&d->shutdown_lock);
 
     d->is_shutting_down = d->is_shut_down = 0;
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615..5f77ffadf1 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -109,6 +109,8 @@ int arch_domain_soft_reset(struct domain *d);
 
 void arch_domain_creation_finished(struct domain *d);
 
+int arch_domain_resume(struct domain *d);
+
 void arch_p2m_set_access_required(struct domain *d, bool access_required);
 
 int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c);
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini 
Subject: [PATCH v11 3/4] SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
Date: Thu, 28 Aug 2025 17:54:06 +0300
Message-ID: <9173ec351b88ad04e6ea13053dd785eb7f0e9b53.1756392094.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

Add a new entry under the "Virtual Hardware, QEMU" section documenting
support for the optional PSCI SYSTEM_SUSPEND function exposed to guests.

This function is available via the virtual PSCI (vPSCI) interface and
allows guest domains (domUs) to initiate system suspend operations.

The feature is currently marked as "Tech Preview".

Signed-off-by: Mykola Kvach 
---
Changes in V10:
- Status of vPSCI SYSTEM_SUSPEND changed from "Experimental" to
  "Tech Preview"

Changes in v6:
- Dropped the generic guest PSCI support entry (merged in a separate patch)
- This patch now documents only the SYSTEM_SUSPEND optional function
- Reworded commit message to match the final form after rebase

Changes in v5:
- Dropped ARM/PSCI entry: this refers to internal use of PSCI SMC calls,
  which is not relevant for SUPPORT.md
- Added a dedicated entry for PSCI SYSTEM_SUSPEND instead of generic guest
  PSCI info; guest PSCI support was documented in a separate patch
---
 SUPPORT.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/SUPPORT.md b/SUPPORT.md
index 6a82a92189..0ce0903cb1 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -962,8 +962,9 @@ Emulated PSCI interface exposed to guests. We support all mandatory
 functions of PSCI 1.1. See below for the list of optional PSCI call
 implemented and their status.
 
-   Status, Mandatory: Supported
-   Status, MIGRATE_INFO_TYPE: Supported
+    Status, Mandatory: Supported
+    Status, MIGRATE_INFO_TYPE: Supported
+    Status, SYSTEM_SUSPEND: Tech Preview
 
 ## Virtual Hardware, QEMU
 
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Shawn Anastasio ,
	Alistair Francis ,
	Bob Eshleman ,
	Connor Davis ,
	Oleksii Kurochko ,
	Juergen Gross ,
	Community Manager 
Subject: [PATCH v11 0/4] Enable guest suspend/resume support on ARM via vPSCI
Date: Thu, 28 Aug 2025 17:54:03 +0300
Message-ID: 
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From: Mykola Kvach 

This patch series introduces the initial support for guest suspend
and resume on ARM platforms using the PSCI SYSTEM_SUSPEND interface. The main
goal is to allow ARM guests to request suspension using PSCI and be resumed
by the control domain (e.g., via "xl resume").

### Background

The PSCI SYSTEM_SUSPEND call is part of the PSCI v1.0+ specification and is
used by guests to enter the deepest possible power state. On Xen/ARM, we
emulate this interface in the virtual PSCI (vPSCI) layer for guests.

This series includes:

1. A new vPSCI implementation of the PSCI SYSTEM_SUSPEND function for guests
2. Documentation updates to SUPPORT.md to reflect PSCI and vPSCI support status
3. Enabling "xl resume" command compilation for ARM, which was previously disabled

### Usage

For Linux-based guests:
  - Suspend can be triggered using: "echo mem > /sys/power/state" or "systemctl suspend"
  - Resume can be performed from control domain using: "xl resume "

For more information, refer to the official Linux kernel documentation on power management.

Note that currently, SYSTEM_SUSPEND is supported only for guest domains (not for
the hardware domain).
---

This is the first part of previous patch series and originally consist only
with necessary changes needed for guest domain suspend.

The second part can be found here:
    https://patchew.org/Xen/cover.1754943874.git.mykola._5Fkvach@epam.com/

Changes in V11:
- introduce arch_domain_resume() and vpsci_vcpu_up_prepare(), which are now
called on the resume path to avoid extra modifications to common code.
The vCPU context is now updated during domain resume.

Changes in V10:
- An ARM-specific helper (domain_resume_nopause_helper)
- An isb() is added before p2m_save_state
- The is_64bit_domain check is dropped when masking the upper part of entry
  point and cid for SMC32 SYSTEM_SUSPEND PSCI calls
- Status of vPSCI SYSTEM_SUSPEND changed from "Experimental" to "Tech Preview"

Changes in V9:
- no functional changes
- enhance commit message and add extra comment to the code after review

Changes in V8:
- GIC and virtual timer context saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Main changes in V6:
- Skip execution of ctxt_switch_from for VCPUs in paused domains.
- Implement domain_resume_nopause
- Add a helper to determine if a VCPU is in suspended domain.
- Ignore upper 32 bits of arguments for 64-bit domains calling SMC32 SYSTEM_SUSPEND.
- Macro renamed from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND for clarity.
- Documentation now focuses only on the SYSTEM_SUSPEND function, with improved wording and structure.
- Changelog and commit messages refined for clarity and to remove redundant explanations.

Main change in V5:
  - Reverted the logic related to suspending domains. Instead of the standby
    mode introduced in v4, domains now resume execution at the point provided
    during suspend

The rest of the minor changes are described in the changelog of each commit.

Previous versions of this patch series:
  V1: https://lists.xenproject.org/archives/html/xen-devel/2018-11/msg01093.html
  V2: https://marc.info/?l=xen-devel&m=166514782207736&w=2
  V3: https://lists.xenproject.org/archives/html/xen-devel/2025-03/msg00168.html

Mykola Kvach (4):
  xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
  tools/xl: Allow compilation of 'xl resume' command on Arm
  SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
  CHANGELOG: Document guest suspend/resume to RAM support on Arm

 CHANGELOG.md                          |   2 +
 SUPPORT.md                            |   5 +-
 tools/include/libxl.h                 |   1 -
 tools/xl/xl.h                         |   4 +-
 tools/xl/xl_cmdtable.c                |   4 +-
 tools/xl/xl_migrate.c                 |   2 +-
 tools/xl/xl_saverestore.c             |   2 +-
 tools/xl/xl_vmcontrol.c               |  12 +--
 xen/arch/arm/domain.c                 |  22 +++++
 xen/arch/arm/include/asm/domain.h     |   6 ++
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   5 +-
 xen/arch/arm/vpsci.c                  | 114 +++++++++++++++++++++-----
 xen/arch/ppc/stubs.c                  |   5 ++
 xen/arch/riscv/stubs.c                |   5 ++
 xen/arch/x86/domain.c                 |   5 ++
 xen/common/domain.c                   |   9 ++
 xen/include/xen/domain.h              |   2 +
 19 files changed, 173 insertions(+), 35 deletions(-)

-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v11 4/4] CHANGELOG: Document guest suspend/resume to RAM support on Arm
Date: Thu, 28 Aug 2025 17:54:07 +0300
Message-ID: <6fa6038c90109a2e9990a691fbcf2aceb5aa9694.1756392094.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

Mention the newly added support for guest suspend and resume to/from
RAM via vPSCI on Arm platforms.

This support is limited to non-hardware domain guests.

Signed-off-by: Mykola Kvach 
Acked-by: Oleksii Kurochko 
---
Chnages in v6:
- removed reduntand explanation that thi support added for
  both arm32 and arm64.

Changes in v5:
- adjustments to the commit title and message
- expanded the changelog entry to include more context about
  suspend/resume support introduced in this patch series
---
 CHANGELOG.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index cd34ea87b8..7a75bd37cb 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -36,6 +36,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 
  - On Arm:
     - Ability to enable stack protector
+    - Support for guest suspend and resume to/from RAM via vPSCI.
+      Applies only to non-hardware domain guests.
 
 ### Removed
  - On x86:
-- 
2.48.1



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Date: Thu, 28 Aug 2025 12:00:49 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
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	Christoph Hellwig , Danilo Krummrich ,
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	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 08/16] kmsan: convert kmsan_handle_dma to use physical
 addresses
Message-ID: <20250828150049.GG9469@nvidia.com>
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On Tue, Aug 19, 2025 at 08:36:52PM +0300, Leon Romanovsky wrote:
>  /* Helper function to handle DMA data transfers. */
> -void kmsan_handle_dma(struct page *page, size_t offset, size_t size,
> +void kmsan_handle_dma(phys_addr_t phys, size_t size,
>  		      enum dma_data_direction dir)
>  {
> +	struct page *page = phys_to_page(phys);
>  	u64 page_offset, to_go, addr;
>  
>  	if (PageHighMem(page))
>  		return;
> -	addr = (u64)page_address(page) + offset;
> +	addr = (u64)page_address(page) + offset_in_page(phys);

addr = phys_to_virt(phys);

And make addr a void *

Otherwise looks fine

Reviewed-by: Jason Gunthorpe 

Jason


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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 00/23] x86: FRED support
Date: Thu, 28 Aug 2025 16:03:46 +0100
Message-Id: <20250828150409.901315-1-andrew.cooper3@citrix.com>
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This is now everything to get to tech preview, except for the caveat that it's
still not been tried on real hardware yet, so is staying experimental for now.

The first few patches have been seen before but the latter half of the series
is new, adding support for running PV guests when Xen is using FRED.  Some
work here has influenced earlier patches.

See patches for details.

https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/2009286102

This series is still based on the MSR cleaup series posted previously.

Andrew Cooper (23):
  x86: FRED enumerations
  x86/traps: Extend struct cpu_user_regs/cpu_info with FRED fields
  x86/traps: Introduce opt_fred
  x86/boot: Adjust CR4 handling around percpu_early_traps_init()
  x86/S3: Switch to using RSTORSSP to recover SSP on resume
  x86/traps: Set MSR_PL0_SSP in load_system_tables()
  x86/boot: Use RSTORSSP to establish SSP
  x86/traps: Alter switch_stack_and_jump() for FRED mode
  x86/traps: Skip Supervisor Shadow Stack tokens in FRED mode
  x86/traps: Make an IDT-specific #DB helper
  x86/traps: Make an IDT-specific #PF helper
  x86/fsgsbase: Make gskern accesses safe under FRED
  x86/traps: Introduce FRED entrypoints
  x86/traps: Enable FRED when requested
  x86/pv: Deduplicate is_canonical_address() in do_set_segment_base()
  x86/entry: Alter how IRET faults are recognised
  x86/entry: Drop the pre exception table infrastructure
  x86/entry: Rework the comment about SYSCALL and DF
  x86/pv: Adjust GS handling for FRED mode
  x86/pv: Exception handling in FRED mode
  x86/pv: ERETU error handling
  x86/pv: System call handling in FRED mode
  x86/pv: Adjust eflags handling for FRED mode

 docs/misc/xen-command-line.pandoc           |  10 +
 xen/arch/x86/acpi/wakeup_prot.S             |  52 +-
 xen/arch/x86/boot/x86_64.S                  |  48 +-
 xen/arch/x86/domain.c                       |  26 +-
 xen/arch/x86/extable.c                      |  14 -
 xen/arch/x86/hvm/domain.c                   |   4 +-
 xen/arch/x86/include/asm/asm-defns.h        |   8 +
 xen/arch/x86/include/asm/asm_defns.h        |  76 ++-
 xen/arch/x86/include/asm/cpu-user-regs.h    |  71 ++-
 xen/arch/x86/include/asm/cpufeature.h       |   3 +
 xen/arch/x86/include/asm/cpufeatures.h      |   2 +-
 xen/arch/x86/include/asm/current.h          |   9 +-
 xen/arch/x86/include/asm/domain.h           |   5 +
 xen/arch/x86/include/asm/fsgsbase.h         |   8 +-
 xen/arch/x86/include/asm/hypercall.h        |   5 +
 xen/arch/x86/include/asm/msr-index.h        |  11 +
 xen/arch/x86/include/asm/traps.h            |   6 +
 xen/arch/x86/include/asm/uaccess.h          |   2 -
 xen/arch/x86/include/asm/x86-defns.h        |   8 +
 xen/arch/x86/mm.c                           |  12 +-
 xen/arch/x86/pv/dom0_build.c                |   2 +-
 xen/arch/x86/pv/domain.c                    |  22 +-
 xen/arch/x86/pv/iret.c                      |   8 +-
 xen/arch/x86/pv/misc-hypercalls.c           |  42 +-
 xen/arch/x86/pv/traps.c                     |  33 ++
 xen/arch/x86/setup.c                        |  35 +-
 xen/arch/x86/traps-setup.c                  | 127 ++++-
 xen/arch/x86/traps.c                        | 511 ++++++++++++++++++--
 xen/arch/x86/x86_64/Makefile                |   1 +
 xen/arch/x86/x86_64/compat/entry.S          |   3 +-
 xen/arch/x86/x86_64/entry-fred.S            |  57 +++
 xen/arch/x86/x86_64/entry.S                 |  46 +-
 xen/arch/x86/xen.lds.S                      |   5 -
 xen/include/public/arch-x86/cpufeatureset.h |   3 +
 34 files changed, 1106 insertions(+), 169 deletions(-)
 create mode 100644 xen/arch/x86/x86_64/entry-fred.S

-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 01/23] x86: FRED enumerations
Date: Thu, 28 Aug 2025 16:03:47 +0100
Message-Id: <20250828150409.901315-2-andrew.cooper3@citrix.com>
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Of note, CR4.FRED is bit 32 and cannot enabled outside of 64bit mode.

Most supported toolchains don't understand the FRED instructions yet.  ERETU
and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC), while LKGS is
more complicated and deferred for now.

I have intentionally named the FRED MSRs differently to the spec.  In the
spec, the stack pointer names alias the TSS fields of the same name, despite
very different semantics.

Signed-off-by: Andrew Cooper 
Acked-by: Jan Beulich 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Drop CONFIG_HAS_AS_FRED
---
 xen/arch/x86/include/asm/asm-defns.h        |  8 ++++++++
 xen/arch/x86/include/asm/cpufeature.h       |  3 +++
 xen/arch/x86/include/asm/cpufeatures.h      |  2 +-
 xen/arch/x86/include/asm/msr-index.h        | 11 +++++++++++
 xen/arch/x86/include/asm/x86-defns.h        |  1 +
 xen/include/public/arch-x86/cpufeatureset.h |  3 +++
 6 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/include/asm/asm-defns.h b/xen/arch/x86/include/asm/asm-defns.h
index 61a5faf90446..239dc3af096c 100644
--- a/xen/arch/x86/include/asm/asm-defns.h
+++ b/xen/arch/x86/include/asm/asm-defns.h
@@ -4,6 +4,14 @@
     .byte 0x0f, 0x01, 0xfc
 .endm
 
+/* binutils >= 2.41 or LLVM >= 19 */
+.macro eretu
+    .byte 0xf3, 0x0f, 0x01, 0xca
+.endm
+.macro erets
+    .byte 0xf2, 0x0f, 0x01, 0xca
+.endm
+
 /*
  * Call a noreturn function.  This could be JMP, but CALL results in a more
  * helpful backtrace.  BUG is to catch functions which do decide to return...
diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h
index 441a7ecc494b..b6cf0c8dfc7c 100644
--- a/xen/arch/x86/include/asm/cpufeature.h
+++ b/xen/arch/x86/include/asm/cpufeature.h
@@ -246,6 +246,9 @@ static inline bool boot_cpu_has(unsigned int feat)
 #define cpu_has_avx_vnni        boot_cpu_has(X86_FEATURE_AVX_VNNI)
 #define cpu_has_avx512_bf16     boot_cpu_has(X86_FEATURE_AVX512_BF16)
 #define cpu_has_cmpccxadd       boot_cpu_has(X86_FEATURE_CMPCCXADD)
+#define cpu_has_fred            boot_cpu_has(X86_FEATURE_FRED)
+#define cpu_has_lkgs            boot_cpu_has(X86_FEATURE_LKGS)
+#define cpu_has_nmi_src         boot_cpu_has(X86_FEATURE_NMI_SRC)
 #define cpu_has_avx_ifma        boot_cpu_has(X86_FEATURE_AVX_IFMA)
 
 /* CPUID level 0x80000021.eax */
diff --git a/xen/arch/x86/include/asm/cpufeatures.h b/xen/arch/x86/include/asm/cpufeatures.h
index 71308d9dafc8..0a98676c1604 100644
--- a/xen/arch/x86/include/asm/cpufeatures.h
+++ b/xen/arch/x86/include/asm/cpufeatures.h
@@ -18,7 +18,7 @@ XEN_CPUFEATURE(ARCH_PERFMON,      X86_SYNTH( 3)) /* Intel Architectural PerfMon
 XEN_CPUFEATURE(TSC_RELIABLE,      X86_SYNTH( 4)) /* TSC is known to be reliable */
 XEN_CPUFEATURE(XTOPOLOGY,         X86_SYNTH( 5)) /* cpu topology enum extensions */
 XEN_CPUFEATURE(CPUID_FAULTING,    X86_SYNTH( 6)) /* cpuid faulting */
-/* Bit 7 unused */
+XEN_CPUFEATURE(XEN_FRED,          X86_SYNTH( 7)) /* Xen uses FRED */
 XEN_CPUFEATURE(APERFMPERF,        X86_SYNTH( 8)) /* APERFMPERF */
 XEN_CPUFEATURE(MFENCE_RDTSC,      X86_SYNTH( 9)) /* MFENCE synchronizes RDTSC */
 XEN_CPUFEATURE(XEN_SMEP,          X86_SYNTH(10)) /* SMEP gets used by Xen itself */
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 428d993ee89b..bb48d16f0c6d 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -115,6 +115,17 @@
 #define  MCU_OPT_CTRL_GDS_MIT_DIS           (_AC(1, ULL) <<  4)
 #define  MCU_OPT_CTRL_GDS_MIT_LOCK          (_AC(1, ULL) <<  5)
 
+#define MSR_FRED_RSP_SL0                    0x000001cc
+#define MSR_FRED_RSP_SL1                    0x000001cd
+#define MSR_FRED_RSP_SL2                    0x000001ce
+#define MSR_FRED_RSP_SL3                    0x000001cf
+#define MSR_FRED_STK_LVLS                   0x000001d0
+#define MSR_FRED_SSP_SL0                    MSR_PL0_SSP
+#define MSR_FRED_SSP_SL1                    0x000001d1
+#define MSR_FRED_SSP_SL2                    0x000001d2
+#define MSR_FRED_SSP_SL3                    0x000001d3
+#define MSR_FRED_CONFIG                     0x000001d4
+
 #define MSR_RTIT_OUTPUT_BASE                0x00000560
 #define MSR_RTIT_OUTPUT_MASK                0x00000561
 #define MSR_RTIT_CTL                        0x00000570
diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h
index 23579c471f4a..0a0ba83de786 100644
--- a/xen/arch/x86/include/asm/x86-defns.h
+++ b/xen/arch/x86/include/asm/x86-defns.h
@@ -75,6 +75,7 @@
 #define X86_CR4_PKE        0x00400000 /* enable PKE */
 #define X86_CR4_CET        0x00800000 /* Control-flow Enforcement Technology */
 #define X86_CR4_PKS        0x01000000 /* Protection Key Supervisor */
+#define X86_CR4_FRED       (_AC(1, ULL) << 32) /* Fast Return and Event Delivery */
 
 #define X86_CR8_VALID_MASK 0xf
 
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 990b1d13f301..af69cf3822eb 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -310,7 +310,10 @@ XEN_CPUFEATURE(ARCH_PERF_MON, 10*32+8) /*   Architectural Perfmon */
 XEN_CPUFEATURE(FZRM,         10*32+10) /*A  Fast Zero-length REP MOVSB */
 XEN_CPUFEATURE(FSRS,         10*32+11) /*A  Fast Short REP STOSB */
 XEN_CPUFEATURE(FSRCS,        10*32+12) /*A  Fast Short REP CMPSB/SCASB */
+XEN_CPUFEATURE(FRED,         10*32+17) /*   Fast Return and Event Delivery */
+XEN_CPUFEATURE(LKGS,         10*32+18) /*   Load Kernel GS instruction */
 XEN_CPUFEATURE(WRMSRNS,      10*32+19) /*S  WRMSR Non-Serialising */
+XEN_CPUFEATURE(NMI_SRC,      10*32+20) /*   NMI-Source Reporting */
 XEN_CPUFEATURE(AMX_FP16,     10*32+21) /*   AMX FP16 instruction */
 XEN_CPUFEATURE(AVX_IFMA,     10*32+23) /*A  AVX-IFMA Instructions */
 XEN_CPUFEATURE(LAM,          10*32+26) /*   Linear Address Masking */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 02/23] x86/traps: Extend struct cpu_user_regs/cpu_info with FRED fields
Date: Thu, 28 Aug 2025 16:03:48 +0100
Message-Id: <20250828150409.901315-3-andrew.cooper3@citrix.com>
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The FRED on-stack format is larger than the IDT format, but is by and large
compatible.  FRED reuses space above cs and ss for extra metadata, some of
which is purely informational, and some of which causes additional effects in
ERET{U,S}.

Follow Linux's choice of naming for fred_{c,s}s structures, to make it very
clear at the point of use that it's dependent on FRED.

There is also the event data field and reserved fields, but we cannot include
these in struct cpu_user_regs without reintroducing OoB structure accesses in
the non-FRED case.  See commit 6065a05adf15 ("x86/traps: 'Fix' safety of
read_registers() in #DF path"). for more details.

Instead, use a new struct fred_info and position it suitably in struct
cpu_info.  This boundary will be loaded into MSR_FRED_RSP_SL0, and must be
64-byte aligned.

This does add 16 bytes back into struct cpu_info, undoing the saving we made
by dropping the vm86 data segment selectors.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * .lm -> .l
 * Tweak comments
---
 xen/arch/x86/include/asm/cpu-user-regs.h | 71 ++++++++++++++++++++++--
 xen/arch/x86/include/asm/current.h       |  2 +
 xen/arch/x86/traps-setup.c               |  5 ++
 3 files changed, 74 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/include/asm/cpu-user-regs.h b/xen/arch/x86/include/asm/cpu-user-regs.h
index 5b283a2f6d02..92aeca0aaa88 100644
--- a/xen/arch/x86/include/asm/cpu-user-regs.h
+++ b/xen/arch/x86/include/asm/cpu-user-regs.h
@@ -30,6 +30,10 @@ struct cpu_user_regs
     /*
      * During IDT delivery for exceptions with an error code, hardware pushes
      * to this point.  Entry_vector is filled in by software.
+     *
+     * During FRED delivery, hardware always pushes to this point.  Software
+     * copies fred_ss.vector into entry_vector so most interrupt/exception
+     * handling can be FRED-agnostic.
      */
 
     uint32_t error_code;
@@ -42,18 +46,77 @@ struct cpu_user_regs
      */
 
     union { uint64_t rip;    uint32_t eip;    uint16_t ip; };
-    uint16_t cs, _pad0[1];
-    uint8_t  saved_upcall_mask; /* PV (v)rflags.IF == !saved_upcall_mask */
-    uint8_t  _pad1[3];
+    union {
+        struct {
+            uint16_t      cs;
+            unsigned long :16;
+            uint8_t       saved_upcall_mask; /* PV (v)rflags.IF == !saved_upcall_mask */
+        };
+        unsigned long     csx;
+        struct {
+            /*
+             * Bits 0 to 31 control ERET{U,S} behaviour, and are state of the
+             * interrupted context.
+             */
+            uint16_t      cs;
+            unsigned int  sl:2;      /* Stack Level */
+            bool          wfe:1;     /* Wait-for-ENDBRANCH state */
+        } fred_cs;
+    };
     union { uint64_t rflags; uint32_t eflags; uint16_t flags; };
     union { uint64_t rsp;    uint32_t esp;    uint16_t sp;    uint8_t spl; };
-    uint16_t ss, _pad2[3];
+    union {
+        uint16_t          ss;
+        unsigned long     ssx;
+        struct {
+            /*
+             * Bits 0 to 31 control ERET{U,S} behaviour, and are state about
+             * the event which occured.
+             */
+            uint16_t      ss;
+            bool          sti:1;     /* Was blocked-by-STI, and not cancelled */
+            bool          swint:1;   /* Was a SYSCALL/SYSENTER/INT $N.  On ERETx, pend_DB iff TF */
+            bool          nmi:1;     /* Was an NMI. */
+            unsigned long :13;
+
+            /*
+             * Bits 32 to 63 are ignored by ERET{U,S} and are informative
+             * only.
+             */
+            uint8_t       vector;
+            unsigned long :8;
+            unsigned int  type:4;    /* X86_ET_* */
+            unsigned long :4;
+            bool          enclave:1; /* Event taken in SGX mode */
+            bool          l:1;       /* Event taken in 64bit mode (old %cs.l) */
+            bool          nested:1;  /* Exception during event delivery (clear for #DF) */
+            unsigned long :1;
+            unsigned int  insnlen:4; /* .type >= SW_INT */
+        } fred_ss;
+    };
 
     /*
      * For IDT delivery, tss->rsp0 points to this boundary as embedded within
      * struct cpu_info.  It must be 16-byte aligned.
      */
 };
+struct fred_info
+{
+    /*
+     * Event Data.  For:
+     *   #DB: PENDING_DBG (%dr6 with positive polarity)
+     *   NMI: NMI-Source Bitmap (on capable hardware)
+     *   #PF: %cr2
+     *   #NM: MSR_XFD_ERR (only XFD-induced #NMs)
+     */
+    uint64_t edata;
+    uint64_t _rsvd;
+
+    /*
+     * For FRED delivery, MSR_FRED_RSP_SL0 points to this boundary as embedded
+     * within struct cpu_info.  It must be 64-byte aligned.
+     */
+};
 
 static inline uint64_t msr_fold(const struct cpu_user_regs *regs)
 {
diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index fd30422707d9..c1eb27b1c4c2 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -38,6 +38,8 @@ struct vcpu;
 
 struct cpu_info {
     struct cpu_user_regs guest_cpu_user_regs;
+    struct fred_info _fred; /* Only used when FRED is active. */
+
     unsigned int processor_id;
     unsigned int verw_sel;
     struct vcpu *current_vcpu;
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index 25581acf1158..c89280270fbb 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -354,7 +354,12 @@ static void __init __maybe_unused build_assertions(void)
      *
      * tss->rsp0, pointing at the end of cpu_info.guest_cpu_user_regs, must be
      * 16-byte aligned.
+     *
+     * MSR_FRED_RSP_SL0, pointing to the end of cpu_info._fred must be 64-byte
+     * aligned.
      */
     BUILD_BUG_ON((sizeof(struct cpu_info) -
                   endof_field(struct cpu_info, guest_cpu_user_regs)) & 15);
+    BUILD_BUG_ON((sizeof(struct cpu_info) -
+                  endof_field(struct cpu_info, _fred)) & 63);
 }
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 22/23] x86/pv: System call handling in FRED mode
Date: Thu, 28 Aug 2025 16:04:08 +0100
Message-Id: <20250828150409.901315-23-andrew.cooper3@citrix.com>
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Under FRED, entry_from_pv() handles everything, even system calls.  This means
more of our logic is written in C now, rather than assembly.

In order to facilitate this, introduce pv_inject_callback(), which reuses
struct trap_bounce infrastructure to inject the syscall/sysenter callbacks.
This in turns requires some !PV compatibility for pv_inject_callback() and
pv_hypercall() which can both be ASSERT_UNREACHABLE().

For each of INT $N, SYSCALL and SYSENTER, FRED gives us interrupted context
which was previously lost.  As the guest can't see FRED, Xen has to lose state
in the same way to maintain the prior behaviour.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New
---
 xen/arch/x86/include/asm/domain.h    |   5 ++
 xen/arch/x86/include/asm/hypercall.h |   5 ++
 xen/arch/x86/pv/traps.c              |  33 +++++++++
 xen/arch/x86/traps.c                 | 107 +++++++++++++++++++++++++++
 4 files changed, 150 insertions(+)

diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/domain.h
index 5df8c7825333..b374decccc9c 100644
--- a/xen/arch/x86/include/asm/domain.h
+++ b/xen/arch/x86/include/asm/domain.h
@@ -712,11 +712,16 @@ int arch_set_info_hvm_guest(struct vcpu *v, const struct vcpu_hvm_context *ctx);
 
 #ifdef CONFIG_PV
 void pv_inject_event(const struct x86_event *event);
+void pv_inject_callback(unsigned int type);
 #else
 static inline void pv_inject_event(const struct x86_event *event)
 {
     ASSERT_UNREACHABLE();
 }
+static inline void pv_inject_callback(unsigned int type)
+{
+    ASSERT_UNREACHABLE();
+}
 #endif
 
 static inline void pv_inject_hw_exception(unsigned int vector, int errcode)
diff --git a/xen/arch/x86/include/asm/hypercall.h b/xen/arch/x86/include/asm/hypercall.h
index f6e9e2313b3c..1010332a47e9 100644
--- a/xen/arch/x86/include/asm/hypercall.h
+++ b/xen/arch/x86/include/asm/hypercall.h
@@ -20,6 +20,11 @@
 
 #ifdef CONFIG_PV
 void pv_hypercall(struct cpu_user_regs *regs);
+#else
+static inline void pv_hypercall(struct cpu_user_regs *regs)
+{
+    ASSERT_UNREACHABLE();
+}
 #endif
 
 void pv_ring1_init_hypercall_page(void *ptr);
diff --git a/xen/arch/x86/pv/traps.c b/xen/arch/x86/pv/traps.c
index c3c0976c440f..e7314d8703d9 100644
--- a/xen/arch/x86/pv/traps.c
+++ b/xen/arch/x86/pv/traps.c
@@ -19,6 +19,8 @@
 #include 
 #include 
 
+#include 
+
 void pv_inject_event(const struct x86_event *event)
 {
     struct vcpu *curr = current;
@@ -95,6 +97,37 @@ void pv_inject_event(const struct x86_event *event)
     }
 }
 
+void pv_inject_callback(unsigned int type)
+{
+    struct vcpu *curr = current;
+    struct trap_bounce *tb = &curr->arch.pv.trap_bounce;
+    unsigned long rip = 0;
+    bool irq = false;
+
+    ASSERT(is_pv_64bit_vcpu(curr));
+
+    switch ( type )
+    {
+    case CALLBACKTYPE_syscall:
+        rip = curr->arch.pv.syscall_callback_eip;
+        irq = curr->arch.pv.vgc_flags & VGCF_syscall_disables_events;
+        break;
+
+    case CALLBACKTYPE_syscall32:
+        rip = curr->arch.pv.syscall32_callback_eip;
+        irq = curr->arch.pv.syscall32_disables_events;
+        break;
+
+    case CALLBACKTYPE_sysenter:
+        rip = curr->arch.pv.sysenter_callback_eip;
+        irq = curr->arch.pv.sysenter_disables_events;
+        break;
+    }
+
+    tb->flags = TBF_EXCEPTION | (irq ? TBF_INTERRUPT : 0);
+    tb->eip = rip;
+}
+
 /*
  * Called from asm to set up the MCE trapbounce info.
  * Returns false no callback is set up, else true.
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index e10b4e771824..9211067cd688 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -52,6 +53,8 @@
 #include 
 #include 
 
+#include 
+
 /*
  * opt_nmi: one of 'ignore', 'dom0', or 'fatal'.
  *  fatal:  Xen prints diagnostic message and then hangs.
@@ -2266,6 +2269,7 @@ void asmlinkage check_ist_exit(const struct cpu_user_regs *regs, bool ist_exit)
 void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
 {
     struct fred_info *fi = cpu_regs_fred_info(regs);
+    struct vcpu *curr = current;
     uint8_t type = regs->fred_ss.type;
     uint8_t vec = regs->fred_ss.vector;
 
@@ -2305,6 +2309,27 @@ void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
 
     switch ( type )
     {
+    case X86_ET_SW_INT:
+        /*
+         * INT $3/4 are indistinguishable from INT3/INTO under IDT, and are
+         * permitted by Xen without the guest kernel having a choice.  Let
+         * them fall through into X86_ET_HW_EXC, as #BP in particular needs
+         * handling by do_int3() in case an external debugger is attached.
+         */
+        if ( vec != X86_EXC_BP && vec != X86_EXC_OF )
+        {
+            const struct trap_info *ti = &curr->arch.pv.trap_ctxt[vec];
+
+            if ( permit_softint(TI_GET_DPL(ti), curr, regs) )
+                pv_inject_sw_interrupt(vec);
+            else
+            {
+                regs->rip -= 2;
+                pv_inject_hw_exception(X86_EXC_GP, (vec << 3) | X86_XEC_IDT);
+            }
+            break;
+        }
+        fallthrough;
     case X86_ET_HW_EXC:
     case X86_ET_PRIV_SW_EXC:
     case X86_ET_SW_EXC:
@@ -2335,6 +2360,88 @@ void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
         }
         break;
 
+    case X86_ET_OTHER:
+        switch ( regs->fred_ss.vector )
+        {
+        case 1: /* SYSCALL */
+        {
+            /*
+             * FRED delivery preserves the interrupted %cs/%ss, but previously
+             * SYSCALL lost the interrupted selectors, and SYSRET forced the
+             * use of the ones in MSR_STAR.
+             *
+             * The guest isn't aware of FRED, so recreate the legacy
+             * behaviour, including the guess of instruction length for
+             * faults.
+             *
+             * The non-FRED SYSCALL path sets TRAP_syscall in entry_vector to
+             * signal that SYSRET can be used, but this isn't relevant in FRED
+             * mode.
+             *
+             * When setting the selectors, clear all upper metadata again for
+             * backwards compatibility.  In particular fred_ss.swint becomes
+             * pend_DB on ERETx, and nothing else in the pv_hypercall() would
+             * clean up.
+             */
+            bool l = regs->fred_ss.l;
+
+            regs->ssx = l ? FLAT_KERNEL_SS   : FLAT_USER_SS32;
+            regs->csx = l ? FLAT_KERNEL_CS64 : FLAT_USER_CS32;
+
+            if ( guest_kernel_mode(curr, regs) )
+                pv_hypercall(regs);
+            else if ( (l ? curr->arch.pv.syscall_callback_eip
+                         : curr->arch.pv.syscall32_callback_eip) == 0 )
+            {
+                regs->rip -= 2;
+                pv_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC);
+            }
+            else
+            {
+                /*
+                 * The PV ABI, given no virtual SYSCALL_MASK, hardcodes that
+                 * DF is cleared.  Other flags are handled in the same way as
+                 * interrupts and exceptions in create_bounce_frame().
+                 */
+                regs->eflags &= ~X86_EFLAGS_DF;
+                pv_inject_callback(l ? CALLBACKTYPE_syscall
+                                     : CALLBACKTYPE_syscall32);
+            }
+            break;
+        }
+
+        case 2: /* SYSENTER */
+            /*
+             * FRED delivery preserves the interrupted state, but previously
+             * SYSENTER discarded almost everything.
+             *
+             * The guest isn't aware of FRED, so recreate the legacy
+             * behaviour, including the guess of instruction length for
+             * faults.
+             *
+             * When setting the selectors, clear all upper metadata.  In
+             * particular fred_ss.swint becomes pend_DB on ERETx.
+             */
+            regs->ssx = FLAT_USER_SS;
+            regs->rsp = 0;
+            regs->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
+            regs->csx = 3;
+            regs->rip = 0;
+
+            if ( !curr->arch.pv.sysenter_callback_eip )
+            {
+                regs->rip -= 2;
+                pv_inject_hw_exception(X86_EXC_GP, 0);
+            }
+            else
+                pv_inject_callback(CALLBACKTYPE_sysenter);
+            break;
+
+        default:
+            goto fatal;
+        }
+        break;
+
     default:
         goto fatal;
     }
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 11/23] x86/traps: Make an IDT-specific #PF helper
Date: Thu, 28 Aug 2025 16:03:57 +0100
Message-Id: <20250828150409.901315-12-andrew.cooper3@citrix.com>
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FRED provides %cr2 in the the stack frame, avoiding the need to read %cr2
manually.

Rename do_page_fault() to handle_PF(), and update it to take cr2, still named
addr for consistency.

Introduce a new handle_PF_IDT() which reads %cr2 and conditionally re-enables
interrupts.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New
---
 xen/arch/x86/traps.c        | 26 ++++++++++++++------------
 xen/arch/x86/x86_64/entry.S |  2 +-
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 0372f1c386a8..c11d72d47027 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1670,21 +1670,10 @@ static int fixup_page_fault(unsigned long addr, struct cpu_user_regs *regs)
     return 0;
 }
 
-void asmlinkage do_page_fault(struct cpu_user_regs *regs)
+static void handle_PF(struct cpu_user_regs *regs, unsigned long addr /* cr2 */)
 {
-    unsigned long addr;
     unsigned int error_code;
 
-    addr = read_cr2();
-
-    /*
-     * Don't re-enable interrupts if we were running an IRQ-off region when
-     * we hit the page fault, or we'll break that code.
-     */
-    ASSERT(!local_irq_is_enabled());
-    if ( regs->flags & X86_EFLAGS_IF )
-        local_irq_enable();
-
     /* fixup_page_fault() might change regs->error_code, so cache it here. */
     error_code = regs->error_code;
 
@@ -1745,6 +1734,19 @@ void asmlinkage do_page_fault(struct cpu_user_regs *regs)
     pv_inject_page_fault(regs->error_code, addr);
 }
 
+/*
+ * When using IDT delivery, it is our responsibility to read %cr2.
+ */
+void asmlinkage handle_PF_IDT(struct cpu_user_regs *regs)
+{
+    unsigned long addr = read_cr2();
+
+    if ( regs->flags & X86_EFLAGS_IF )
+        local_irq_enable();
+
+    handle_PF(regs, addr);
+}
+
 /*
  * Early #PF handler to print CR2, error code, and stack.
  *
diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
index 789687488c5f..c02245ac064c 100644
--- a/xen/arch/x86/x86_64/entry.S
+++ b/xen/arch/x86/x86_64/entry.S
@@ -871,7 +871,7 @@ handle_exception_saved:
          * reading %cr2. Otherwise a page fault in the nested interrupt handler
          * would corrupt %cr2.
          */
-        DISPATCH(X86_EXC_PF, do_page_fault)
+        DISPATCH(X86_EXC_PF, handle_PF_IDT)
 
         /* Only re-enable IRQs if they were active before taking the fault */
         testb $X86_EFLAGS_IF >> 8, UREGS_eflags + 1(%rsp)
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 19/23] x86/pv: Adjust GS handling for FRED mode
Date: Thu, 28 Aug 2025 16:04:05 +0100
Message-Id: <20250828150409.901315-20-andrew.cooper3@citrix.com>
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When FRED is active, hardware automatically swaps GS when changing privilege,
and the SWAPGS instruction is disallowed.

For native OSes using GS as the thread local pointer this is a massive
improvement on the pre-FRED architecture, but under Xen it makes handling PV
guests more complicated.  Specifically, it means that GS_BASE and GS_SHADOW
are the opposite way around in FRED mode, as opposed to IDT mode.

This leads to the following changes:

  * In load_segments(), we have to load both GSes.  Account for this in the
    SWAP() condition and avoid the path with SWAGS.

  * In save_segments(), we need to read GS_KERN rather than GS_BASE.

  * In toggle_guest_mode(), we need to emulate SWAPGS.

  * In do_set_segment_base(), merge the SEGBASE_GS_{USER,KERNEL} cases and
    take FRED into account when choosing which base to update.

    SEGBASE_GS_USER_SEL was already an LKGS invocation (decades before FRED)
    so under FRED needs to be a simple MOV %gs.  Simply skip the SWAPGSes.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New

I think this functions, but it's not ideal.  The conditions are asymmetric and
awkward.

In principle, MSR_IMM can be as performant as FSGSBASE.  They can literally be
the the same microcode if the microline indexing allows.

Otherwise, the FSGSBASE instructions will be more performant than MSR
accesses (no need to decode %ecx), even with non-serialising writes (which all
FRED hardware should have).  However, use of FSGSBASE often comes with SWAPGS
and that can't be used under FRED.
---
 xen/arch/x86/domain.c             | 22 +++++++++++++++++-----
 xen/arch/x86/pv/domain.c          | 22 ++++++++++++++++++++--
 xen/arch/x86/pv/misc-hypercalls.c | 16 ++++++++++------
 3 files changed, 47 insertions(+), 13 deletions(-)

diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 8089ff929bf7..64922869a625 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1819,9 +1819,10 @@ static void load_segments(struct vcpu *n)
 
         /*
          * Figure out which way around gsb/gss want to be.  gsb needs to be
-         * the active context, and gss needs to be the inactive context.
+         * the active context, and gss needs to be the inactive context,
+         * unless we're in FRED mode where they're reversed.
          */
-        if ( !(n->arch.flags & TF_kernel_mode) )
+        if ( !(n->arch.flags & TF_kernel_mode) ^ opt_fred )
             SWAP(gsb, gss);
 
         if ( using_svm() && (n->arch.pv.fs | n->arch.pv.gs) <= 3 )
@@ -1842,7 +1843,9 @@ static void load_segments(struct vcpu *n)
 
     if ( !fs_gs_done && !compat )
     {
-        if ( read_cr4() & X86_CR4_FSGSBASE )
+        unsigned long cr4 = read_cr4();
+
+        if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
         {
             __wrgsbase(gss);
             __wrfsbase(n->arch.pv.fs_base);
@@ -1959,6 +1962,9 @@ static void load_segments(struct vcpu *n)
  * Guests however cannot use SWAPGS, so there is no mechanism to modify the
  * inactive GS base behind Xen's back.  Therefore, Xen's copy of the inactive
  * GS base is still accurate, and doesn't need reading back from hardware.
+ *
+ * Under FRED, hardware automatically swaps GS for us, so GS_KERN is the
+ * active GS from the guest's point of view.
  */
 static void save_segments(struct vcpu *v)
 {
@@ -1974,12 +1980,18 @@ static void save_segments(struct vcpu *v)
         if ( read_cr4() & X86_CR4_FSGSBASE )
         {
             fs_base = __rdfsbase();
-            gs_base = __rdgsbase();
+            if ( opt_fred )
+                gs_base = rdmsr(MSR_SHADOW_GS_BASE);
+            else
+                gs_base = __rdgsbase();
         }
         else
         {
             fs_base = rdmsr(MSR_FS_BASE);
-            gs_base = rdmsr(MSR_GS_BASE);
+            if ( opt_fred )
+                gs_base = rdmsr(MSR_SHADOW_GS_BASE);
+            else
+                gs_base = rdmsr(MSR_GS_BASE);
         }
 
         v->arch.pv.fs_base = fs_base;
diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c
index 9c4785c187dd..5a7b69da5000 100644
--- a/xen/arch/x86/pv/domain.c
+++ b/xen/arch/x86/pv/domain.c
@@ -14,9 +14,10 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
+#include 
+#include 
 
 #ifdef CONFIG_PV32
 int8_t __read_mostly opt_pv32 = -1;
@@ -480,11 +481,28 @@ void toggle_guest_mode(struct vcpu *v)
      * subsequent context switch won't bother re-reading it.
      */
     gs_base = read_gs_base();
+
+    /*
+     * In FRED mode, not only are the two GSes the other way around (i.e. we
+     * want to read GS_KERN here), the SWAPGS instruction is disallowed so we
+     * have to emulate it.
+     */
+    if ( opt_fred )
+    {
+        unsigned long gs_kern = rdmsr(MSR_SHADOW_GS_BASE);
+
+        wrmsrns(MSR_SHADOW_GS_BASE, gs_base);
+        write_gs_base(gs_kern);
+
+        gs_base = gs_kern;
+    }
+    else
+        asm volatile ( "swapgs" );
+
     if ( v->arch.flags & TF_kernel_mode )
         v->arch.pv.gs_base_kernel = gs_base;
     else
         v->arch.pv.gs_base_user = gs_base;
-    asm volatile ( "swapgs" );
 
     _toggle_guest_pt(v);
 
diff --git a/xen/arch/x86/pv/misc-hypercalls.c b/xen/arch/x86/pv/misc-hypercalls.c
index 4c2abeb4add8..2c9cf50638db 100644
--- a/xen/arch/x86/pv/misc-hypercalls.c
+++ b/xen/arch/x86/pv/misc-hypercalls.c
@@ -11,6 +11,7 @@
 
 #include 
 #include 
+#include 
 
 long do_set_debugreg(int reg, unsigned long value)
 {
@@ -192,11 +193,12 @@ long do_set_segment_base(unsigned int which, unsigned long base)
 
         case SEGBASE_GS_USER:
             v->arch.pv.gs_base_user = base;
-            write_gs_shadow(base);
-            break;
-
+            fallthrough;
         case SEGBASE_GS_KERNEL:
-            write_gs_base(base);
+            if ( (which == SEGBASE_GS_KERNEL) ^ opt_fred )
+                write_gs_base(base);
+            else
+                write_gs_shadow(base);
             break;
         }
         break;
@@ -209,7 +211,8 @@ long do_set_segment_base(unsigned int which, unsigned long base)
          * We wish to update the user %gs from the GDT/LDT.  Currently, the
          * guest kernel's GS_BASE is in context.
          */
-        asm volatile ( "swapgs" );
+        if ( !opt_fred )
+            asm volatile ( "swapgs" );
 
         if ( sel > 3 )
             /* Fix up RPL for non-NUL selectors. */
@@ -247,7 +250,8 @@ long do_set_segment_base(unsigned int which, unsigned long base)
         /* Update the cache of the inactive base, as read from the GDT/LDT. */
         v->arch.pv.gs_base_user = read_gs_base();
 
-        asm volatile ( safe_swapgs );
+        if ( !opt_fred )
+            asm volatile ( safe_swapgs );
         break;
     }
 
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 23/23] x86/pv: Adjust eflags handling for FRED mode
Date: Thu, 28 Aug 2025 16:04:09 +0100
Message-Id: <20250828150409.901315-24-andrew.cooper3@citrix.com>
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ERETU, unlike IRET, requires the sticky-1 bit (bit 2) be set, and reserved
bits to be clear.  Notably this means that dom0_construct() must set
X86_EFLAGS_MBS it in order for a PV dom0 to start.

Adjust arch_set_info_guest*() and hypercall_iret() which consume flags to
clamp the reserved bits.

This is a minor ABI change, but by the same argument as commit
9f892f84c279 ("x86/domctl: Stop using XLAT_cpu_user_regs()"), this change will
happen naturally when the vCPU schedules.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New

The handling of VM is complicated.

It turns out that it's simply ignored by IRET in Long Mode (i.e. clearing it
commit 0e47f92b0725 ("x86: force EFLAGS.IF on when exiting to PV guests")
wasn't actually necessary) but ERETU does care.

But, it's unclear how to handle this in in arch_set_info().  We must preserve
it for HVM guests (whih can use vm86 mode).  PV32 has special handling but
only in hypercall_iret(), not in arch_set_info().
---
 xen/arch/x86/domain.c                | 4 ++--
 xen/arch/x86/hvm/domain.c            | 4 ++--
 xen/arch/x86/include/asm/x86-defns.h | 7 +++++++
 xen/arch/x86/pv/dom0_build.c         | 2 +-
 xen/arch/x86/pv/iret.c               | 8 +++++---
 5 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 64922869a625..c1880324f7a9 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1273,7 +1273,7 @@ int arch_set_info_guest(
         v->arch.user_regs.rax               = c.nat->user_regs.rax;
         v->arch.user_regs.rip               = c.nat->user_regs.rip;
         v->arch.user_regs.cs                = c.nat->user_regs.cs;
-        v->arch.user_regs.rflags            = c.nat->user_regs.rflags;
+        v->arch.user_regs.rflags            = (c.nat->user_regs.rflags & X86_EFLAGS_ALL) | X86_EFLAGS_MBS;
         v->arch.user_regs.rsp               = c.nat->user_regs.rsp;
         v->arch.user_regs.ss                = c.nat->user_regs.ss;
         v->arch.pv.es                       = c.nat->user_regs.es;
@@ -1297,7 +1297,7 @@ int arch_set_info_guest(
         v->arch.user_regs.eax               = c.cmp->user_regs.eax;
         v->arch.user_regs.eip               = c.cmp->user_regs.eip;
         v->arch.user_regs.cs                = c.cmp->user_regs.cs;
-        v->arch.user_regs.eflags            = c.cmp->user_regs.eflags;
+        v->arch.user_regs.eflags            = (c.cmp->user_regs.eflags & X86_EFLAGS_ALL) | X86_EFLAGS_MBS;
         v->arch.user_regs.esp               = c.cmp->user_regs.esp;
         v->arch.user_regs.ss                = c.cmp->user_regs.ss;
         v->arch.pv.es                       = c.cmp->user_regs.es;
diff --git a/xen/arch/x86/hvm/domain.c b/xen/arch/x86/hvm/domain.c
index 048f29ae4911..1e874d598952 100644
--- a/xen/arch/x86/hvm/domain.c
+++ b/xen/arch/x86/hvm/domain.c
@@ -194,7 +194,7 @@ int arch_set_info_hvm_guest(struct vcpu *v, const struct vcpu_hvm_context *ctx)
         uregs->rsi    = regs->esi;
         uregs->rdi    = regs->edi;
         uregs->rip    = regs->eip;
-        uregs->rflags = regs->eflags;
+        uregs->rflags = (regs->eflags & X86_EFLAGS_ALL) | X86_EFLAGS_MBS;
 
         v->arch.hvm.guest_cr[0] = regs->cr0;
         v->arch.hvm.guest_cr[3] = regs->cr3;
@@ -245,7 +245,7 @@ int arch_set_info_hvm_guest(struct vcpu *v, const struct vcpu_hvm_context *ctx)
         uregs->rsi    = regs->rsi;
         uregs->rdi    = regs->rdi;
         uregs->rip    = regs->rip;
-        uregs->rflags = regs->rflags;
+        uregs->rflags = (regs->rflags & X86_EFLAGS_ALL) | X86_EFLAGS_MBS;
 
         v->arch.hvm.guest_cr[0] = regs->cr0;
         v->arch.hvm.guest_cr[3] = regs->cr3;
diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h
index 0a0ba83de786..edeb0b4ff95a 100644
--- a/xen/arch/x86/include/asm/x86-defns.h
+++ b/xen/arch/x86/include/asm/x86-defns.h
@@ -27,6 +27,13 @@
     (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |   \
      X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF)
 
+#define X86_EFLAGS_ALL                                          \
+    (X86_EFLAGS_ARITH_MASK | X86_EFLAGS_TF | X86_EFLAGS_IF |    \
+     X86_EFLAGS_DF | X86_EFLAGS_OF | X86_EFLAGS_IOPL |          \
+     X86_EFLAGS_NT | X86_EFLAGS_RF | X86_EFLAGS_VM |            \
+     X86_EFLAGS_AC | X86_EFLAGS_VIF | X86_EFLAGS_VIP |          \
+     X86_EFLAGS_ID)
+
 /*
  * Intel CPU flags in CR0
  */
diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c
index 21158ce1812e..f9bbbea2ff70 100644
--- a/xen/arch/x86/pv/dom0_build.c
+++ b/xen/arch/x86/pv/dom0_build.c
@@ -1021,7 +1021,7 @@ static int __init dom0_construct(const struct boot_domain *bd)
     regs->rip = parms.virt_entry;
     regs->rsp = vstack_end;
     regs->rsi = vstartinfo_start;
-    regs->eflags = X86_EFLAGS_IF;
+    regs->eflags = X86_EFLAGS_IF | X86_EFLAGS_MBS;
 
     /*
      * We don't call arch_set_info_guest(), so some initialisation needs doing
diff --git a/xen/arch/x86/pv/iret.c b/xen/arch/x86/pv/iret.c
index d3a1fb2c685b..39ce316b8d91 100644
--- a/xen/arch/x86/pv/iret.c
+++ b/xen/arch/x86/pv/iret.c
@@ -80,8 +80,9 @@ long do_iret(void)
 
     regs->rip    = iret_saved.rip;
     regs->cs     = iret_saved.cs | 3; /* force guest privilege */
-    regs->rflags = ((iret_saved.rflags & ~(X86_EFLAGS_IOPL|X86_EFLAGS_VM))
-                    | X86_EFLAGS_IF);
+    regs->rflags = ((iret_saved.rflags & X86_EFLAGS_ALL &
+                     ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) |
+                    X86_EFLAGS_IF | X86_EFLAGS_MBS);
     regs->rsp    = iret_saved.rsp;
     regs->ss     = iret_saved.ss | 3; /* force guest privilege */
 
@@ -143,7 +144,8 @@ int compat_iret(void)
     if ( VM_ASSIST(v->domain, architectural_iopl) )
         v->arch.pv.iopl = eflags & X86_EFLAGS_IOPL;
 
-    regs->eflags = (eflags & ~X86_EFLAGS_IOPL) | X86_EFLAGS_IF;
+    regs->eflags = ((eflags & X86_EFLAGS_ALL & ~X86_EFLAGS_IOPL) |
+                    X86_EFLAGS_IF | X86_EFLAGS_MBS);
 
     if ( unlikely(eflags & X86_EFLAGS_VM) )
     {
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 20/23] x86/pv: Exception handling in FRED mode
Date: Thu, 28 Aug 2025 16:04:06 +0100
Message-Id: <20250828150409.901315-21-andrew.cooper3@citrix.com>
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Under FRED, entry_from_pv() handles everything.  To start with, implement
exception handling in the same manner as entry_from_xen(), although we can
unconditionally enable interrupts after the async/fatal events.

After entry_from_pv() returns, test_all_events() needs to run to perform
exception and interrupt injection.  Split entry_FRED_R3() into two and
introduce eretu_exit_to_guest() as the latter half, coming unilaterally from
restore_all_guest().

For all of this, there is a slightly complicated relationship with CONFIG_PV.
entry_FRED_R3() must exist irrespective of CONFIG_PV, because it's the
entrypoint registered with hardware.  For simplicity, entry_from_pv() is
always called, but it collapses into fatal_trap() in the !PV case.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New
---
 xen/arch/x86/traps.c             | 76 +++++++++++++++++++++++++++++++-
 xen/arch/x86/x86_64/entry-fred.S | 13 +++++-
 xen/arch/x86/x86_64/entry.S      |  4 +-
 3 files changed, 90 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 67763bec0dc5..72df446a6a78 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2265,9 +2265,83 @@ void asmlinkage check_ist_exit(const struct cpu_user_regs *regs, bool ist_exit)
 
 void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
 {
+    struct fred_info *fi = cpu_regs_fred_info(regs);
+    uint8_t type = regs->fred_ss.type;
+    uint8_t vec = regs->fred_ss.vector;
+
     /* Copy fred_ss.vector into entry_vector as IDT delivery would have done. */
-    regs->entry_vector = regs->fred_ss.vector;
+    regs->entry_vector = vec;
+
+    if ( !IS_ENABLED(CONFIG_PV) )
+        goto fatal;
+
+    /*
+     * First, handle the asynchronous or fatal events.  These are either
+     * unrelated to the interrupted context, or may not have valid context
+     * recorded, and all have special rules on how/whether to re-enable IRQs.
+     */
+    switch ( type )
+    {
+    case X86_ET_EXT_INTR:
+        return do_IRQ(regs);
 
+    case X86_ET_NMI:
+        return do_nmi(regs);
+
+    case X86_ET_HW_EXC:
+        switch ( vec )
+        {
+        case X86_EXC_DF: return do_double_fault(regs);
+        case X86_EXC_MC: return do_machine_check(regs);
+        }
+        break;
+    }
+
+    /*
+     * With the asynchronous events handled, what remains are the synchronous
+     * ones.  Guest context always had interrupts enabled.
+     */
+    local_irq_enable();
+
+    switch ( type )
+    {
+    case X86_ET_HW_EXC:
+    case X86_ET_PRIV_SW_EXC:
+    case X86_ET_SW_EXC:
+        switch ( vec )
+        {
+        case X86_EXC_PF:  handle_PF(regs, fi->edata); break;
+        case X86_EXC_GP:  do_general_protection(regs); break;
+        case X86_EXC_UD:  do_invalid_op(regs); break;
+        case X86_EXC_NM:  do_device_not_available(regs); break;
+        case X86_EXC_BP:  do_int3(regs); break;
+        case X86_EXC_DB:  handle_DB(regs, fi->edata); break;
+
+        case X86_EXC_DE:
+        case X86_EXC_OF:
+        case X86_EXC_BR:
+        case X86_EXC_NP:
+        case X86_EXC_SS:
+        case X86_EXC_MF:
+        case X86_EXC_AC:
+        case X86_EXC_XM:
+            do_trap(regs);
+            break;
+
+        case X86_EXC_CP:  do_entry_CP(regs); break;
+
+        default:
+            goto fatal;
+        }
+        break;
+
+    default:
+        goto fatal;
+    }
+
+    return;
+
+ fatal:
     fatal_trap(regs, false);
 }
 
diff --git a/xen/arch/x86/x86_64/entry-fred.S b/xen/arch/x86/x86_64/entry-fred.S
index 3c3320df22cb..07684f38a078 100644
--- a/xen/arch/x86/x86_64/entry-fred.S
+++ b/xen/arch/x86/x86_64/entry-fred.S
@@ -15,9 +15,20 @@ FUNC(entry_FRED_R3, 4096)
         mov     %rsp, %rdi
         call    entry_from_pv
 
+#ifndef CONFIG_PV
+        BUG     /* Not Reached */
+#else
+        GET_STACK_END(14)
+        movq    STACK_CPUINFO_FIELD(current_vcpu)(%r14), %rbx
+
+        jmp     test_all_events
+#endif
+END(entry_FRED_R3)
+
+FUNC(eretu_exit_to_guest)
         POP_GPRS
         eretu
-END(entry_FRED_R3)
+END(eretu_exit_to_guest)
 
         /* The Ring0 entrypoint is at Ring3 + 0x100. */
         .org entry_FRED_R3 + 0x100, 0xcc
diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
index ca446c6ff0ce..0692163faa44 100644
--- a/xen/arch/x86/x86_64/entry.S
+++ b/xen/arch/x86/x86_64/entry.S
@@ -63,7 +63,7 @@ UNLIKELY_END(syscall_no_callback)
         /* Conditionally clear DF */
         and   %esi, UREGS_eflags(%rsp)
 /* %rbx: struct vcpu */
-test_all_events:
+LABEL(test_all_events, 0)
         ASSERT_NOT_IN_ATOMIC
         cli                             # tests must not race interrupts
 /*test_softirqs:*/
@@ -152,6 +152,8 @@ END(switch_to_kernel)
 FUNC_LOCAL(restore_all_guest)
         ASSERT_INTERRUPTS_DISABLED
 
+        ALTERNATIVE "", "jmp eretu_exit_to_guest", X86_FEATURE_XEN_FRED
+
         /* Stash guest SPEC_CTRL value while we can read struct vcpu. */
         mov VCPU_arch_msrs(%rbx), %rdx
         mov VCPUMSR_spec_ctrl_raw(%rdx), %r15d
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 05/23] x86/S3: Switch to using RSTORSSP to recover SSP on resume
Date: Thu, 28 Aug 2025 16:03:51 +0100
Message-Id: <20250828150409.901315-6-andrew.cooper3@citrix.com>
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Under FRED, SETSSBSY is disallowed, and we want to be setting up FRED prior to
setting up shadow stacks.  Luckily, RSTORSSP will also work in this case.

This involves a new type of shadow stack token, the Restore Token, which is
distinguished from the Supervisor Token by pointing to the adjacent slot on
the shadow stack rather than pointing at itself.

In the short term, this logic still needs to load MSR_PL0_SSP.

No functional change.

Signed-off-by: Andrew Cooper 
Reviewed-by: Jan Beulich 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/arch/x86/acpi/wakeup_prot.S | 31 +++++++++++++++----------------
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/xen/arch/x86/acpi/wakeup_prot.S b/xen/arch/x86/acpi/wakeup_prot.S
index 0f02ea7b4b9a..fceb4ca353f7 100644
--- a/xen/arch/x86/acpi/wakeup_prot.S
+++ b/xen/arch/x86/acpi/wakeup_prot.S
@@ -90,7 +90,7 @@ LABEL(s3_resume)
         mov     %rcx, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rcx, %cr4
 
-        /* WARNING! call/ret now fatal (iff SHSTK) until SETSSBSY loads SSP */
+        /* WARNING! CALL/RET now fatal (iff SHSTK) until RSTORSSP loads SSP */
 
 #if defined(CONFIG_XEN_SHSTK)
         test    $CET_SHSTK_EN, %al
@@ -98,32 +98,31 @@ LABEL(s3_resume)
 
         /*
          * Restoring SSP is a little complicated, because we are intercepting
-         * an in-use shadow stack.  Write a temporary token under the stack,
-         * so SETSSBSY will successfully load a value useful for us, then
-         * reset MSR_PL0_SSP to its usual value and pop the temporary token.
+         * an in-use shadow stack.  Write a Restore Token under the stack, and
+         * use RSTORSSP to load it.  RSTORSSP converts the token to a
+         * Previous-SSP Token, which we discard.
          */
         mov     saved_ssp(%rip), %rdi
 
-        /* Construct the temporary supervisor token under SSP. */
-        sub     $8, %rdi
-
-        /* Load it into MSR_PL0_SSP. */
+        /* Calculate MSR_PL0_SSP from SSP. */
         mov     $MSR_PL0_SSP, %ecx
         mov     %rdi, %rdx
         shr     $32, %rdx
         mov     %edi, %eax
-        wrmsr
-
-        /* Write the temporary token onto the shadow stack, and activate it. */
-        wrssq   %rdi, (%rdi)
-        setssbsy
-
-        /* Reset MSR_PL0_SSP back to its normal value. */
         and     $~(STACK_SIZE - 1), %eax
         or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %eax
         wrmsr
 
-        /* Pop the temporary token off the stack. */
+        /*
+         * A Restore Token's value is &token + 8 + 64BIT (bit 0).
+         * We want to put this on the shstk at SSP - 8.
+         */
+        lea     1(%rdi), %rax
+        sub     $8, %rdi
+        wrssq   %rax, (%rdi)
+        rstorssp (%rdi)
+
+        /* Discard the Previous-SSP Token from the shstk. */
         mov     $2, %eax
         incsspd %eax
 #endif /* CONFIG_XEN_SHSTK */
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 14/23] x86/traps: Enable FRED when requested
Date: Thu, 28 Aug 2025 16:04:00 +0100
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With the shadow stack and exception handling adjustements in place, we can now
activate FRED when appropriate.  Note that opt_fred is still disabled by
default.

Introduce init_fred() to set up all the MSRs relevant for FRED.  FRED uses
MSR_STAR (entries from Ring3 only), and MSR_FRED_SSP_SL0 aliases MSR_PL0_SSP
when CET-SS is active.  Otherwise, they're all new MSRs.

With init_fred() existing, load_system_tables() and legacy_syscall_init()
should only be used when setting up IDT delivery.  Insert ASSERT()s to this
effect, and adjust the various *_init() functions to make this property true.

Per the documentation, ap_early_traps_init() is responsible for switching off
the boot GDT, which needs doing even in FRED mode.

Finally, set CR4.FRED in {bsp,ap}_early_traps_init().

Xen can now boot in FRED mode up until starting a PV guest, where it faults
because IRET is not permitted to change privilege.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Explain the lack of BUG_ON()
 * Posion SL1

In principle we can stop allocating the IDT and TSS for CPUs now, although I
want to get shutdown and kexec working before making this optimisation, in
case there's something I've overlooked.
---
 xen/arch/x86/include/asm/current.h |  3 ++
 xen/arch/x86/include/asm/traps.h   |  2 +
 xen/arch/x86/traps-setup.c         | 86 +++++++++++++++++++++++++++---
 3 files changed, 85 insertions(+), 6 deletions(-)

diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index 35cc61fa88e7..53b0d3cf143d 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -23,6 +23,9 @@
  * 2 - NMI IST stack
  * 1 - #MC IST stack
  * 0 - IST Shadow Stacks (4x 1k, read-only)
+ *
+ * In FRED mode, #DB and NMI do not need special stacks, so their IST stacks
+ * are unused.
  */
 
 /*
diff --git a/xen/arch/x86/include/asm/traps.h b/xen/arch/x86/include/asm/traps.h
index 73097e957d05..5d7504bc44d1 100644
--- a/xen/arch/x86/include/asm/traps.h
+++ b/xen/arch/x86/include/asm/traps.h
@@ -16,6 +16,8 @@ void traps_init(void);
 void bsp_traps_reinit(void);
 void percpu_traps_init(void);
 
+void nocall entry_FRED_R3(void);
+
 extern unsigned int ler_msr;
 
 const char *vector_name(unsigned int vec);
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index d77be8f83921..535b53969678 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -59,6 +59,8 @@ static void load_system_tables(void)
         .limit = sizeof(bsp_idt) - 1,
     };
 
+    ASSERT(opt_fred == 0);
+
     /*
      * Set up the TSS.  Warning - may be live, and the NMI/#MC must remain
      * valid on every instruction boundary.  (Note: these are all
@@ -191,6 +193,8 @@ static void legacy_syscall_init(void)
     unsigned char *stub_page;
     unsigned int offset;
 
+    ASSERT(opt_fred == 0);
+
     /* No PV guests?  No need to set up SYSCALL/SYSENTER infrastructure. */
     if ( !IS_ENABLED(CONFIG_PV) )
         return;
@@ -268,6 +272,52 @@ static void __init init_ler(void)
     setup_force_cpu_cap(X86_FEATURE_XEN_LBR);
 }
 
+/*
+ * Set up all MSRs relevant for FRED event delivery.
+ *
+ * Xen does not use any of the optional config in MSR_FRED_CONFIG, so all that
+ * is needed is the entrypoint.
+ *
+ * Because FRED always provides a good stack, NMI and #DB do not need any
+ * special treatment.  Only #DF needs another stack level, and #MC for the
+ * offchance that Xen's main stack suffers an uncorrectable error.
+ *
+ * This makes Stack Level 1 unused, but we use #DB's stacks, and with the
+ * regular and shadow stacks reversed as posion to guarantee that any use
+ * escalates to #DF.
+ *
+ * FRED reuses MSR_STAR to provide the segment selector values to load on
+ * entry from Ring3.  Entry from Ring0 leave %cs and %ss unmodified.
+ */
+static void init_fred(void)
+{
+    unsigned long stack_top = get_stack_bottom() & ~(STACK_SIZE - 1);
+
+    ASSERT(opt_fred == 1);
+
+    wrmsrns(MSR_STAR, XEN_MSR_STAR);
+    wrmsrns(MSR_FRED_CONFIG, (unsigned long)entry_FRED_R3);
+
+    /*
+     * MSR_FRED_RSP_* all come with an 64-byte alignment check, avoiding the
+     * need for an explicit BUG_ON().
+     */
+    wrmsrns(MSR_FRED_RSP_SL0, (unsigned long)(&get_cpu_info()->_fred + 1));
+    wrmsrns(MSR_FRED_RSP_SL1, stack_top + (IST_DB * IST_SHSTK_SIZE)); /* Poison */
+    wrmsrns(MSR_FRED_RSP_SL2, stack_top + (1 + IST_MCE)  * PAGE_SIZE);
+    wrmsrns(MSR_FRED_RSP_SL3, stack_top + (1 + IST_DF)   * PAGE_SIZE);
+    wrmsrns(MSR_FRED_STK_LVLS, ((2UL << (X86_EXC_MC * 2)) |
+                                (3UL << (X86_EXC_DF * 2))));
+
+    if ( cpu_has_xen_shstk )
+    {
+        wrmsrns(MSR_FRED_SSP_SL0, stack_top + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE);
+        wrmsrns(MSR_FRED_RSP_SL1, stack_top + (1 + IST_DF)  * PAGE_SIZE); /* Poison */
+        wrmsrns(MSR_FRED_SSP_SL2, stack_top + (IST_MCE * IST_SHSTK_SIZE));
+        wrmsrns(MSR_FRED_SSP_SL3, stack_top + (IST_DF  * IST_SHSTK_SIZE));
+    }
+}
+
 /*
  * Configure basic exception handling.  This is prior to parsing the command
  * line or configuring a console, and needs to be as simple as possible.
@@ -329,16 +379,20 @@ void __init traps_init(void)
             printk(XENLOG_INFO "Disabling PV32 due to FRED\n");
         }
 #endif
+
+        init_fred();
+        set_in_cr4(X86_CR4_FRED);
+
         setup_force_cpu_cap(X86_FEATURE_XEN_FRED);
         printk("Using FRED event delivery\n");
     }
     else
     {
+        load_system_tables();
+
         printk("Using IDT event delivery\n");
     }
 
-    load_system_tables();
-
     init_ler();
 
     /* Cache {,compat_}gdt_l1e now that physically relocation is done. */
@@ -356,8 +410,13 @@ void __init traps_init(void)
  */
 void __init bsp_traps_reinit(void)
 {
-    load_system_tables();
-    percpu_traps_init();
+    if ( opt_fred )
+        init_fred();
+    else
+    {
+        load_system_tables();
+        percpu_traps_init();
+    }
 }
 
 /*
@@ -366,7 +425,8 @@ void __init bsp_traps_reinit(void)
  */
 void percpu_traps_init(void)
 {
-    legacy_syscall_init();
+    if ( !opt_fred )
+        legacy_syscall_init();
 
     if ( cpu_has_xen_lbr )
         wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR);
@@ -381,7 +441,21 @@ void percpu_traps_init(void)
  */
 void asmlinkage percpu_early_traps_init(void)
 {
-    load_system_tables();
+    if ( opt_fred )
+    {
+        const seg_desc_t *gdt = this_cpu(gdt) - FIRST_RESERVED_GDT_ENTRY;
+        const struct desc_ptr gdtr = {
+            .base = (unsigned long)gdt,
+            .limit = LAST_RESERVED_GDT_BYTE,
+        };
+
+        lgdt(&gdtr);
+
+        init_fred();
+        write_cr4(read_cr4() | X86_CR4_FRED);
+    }
+    else
+        load_system_tables();
 }
 
 static void __init __maybe_unused build_assertions(void)
-- 
2.39.5



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        Thu, 28 Aug 2025 08:05:56 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 07/23] x86/boot: Use RSTORSSP to establish SSP
Date: Thu, 28 Aug 2025 16:03:53 +0100
Message-Id: <20250828150409.901315-8-andrew.cooper3@citrix.com>
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Under FRED, SETSSBSY is disallowed, and we want to be setting up FRED prior to
setting up shadow stacks.  As we still need Supervisor Tokens in IDT mode, we
need mode-specific logic to establish SSP.

In FRED mode, write a Restore Token, RSTORSSP it, and discard the resulting
Previous-SSP token.

No change outside of FRED mode.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Some logic moved into prior patch.
---
 xen/arch/x86/boot/x86_64.S | 23 +++++++++++++++++++++--
 xen/arch/x86/setup.c       | 25 ++++++++++++++++++++++++-
 2 files changed, 45 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 11a7e9d3bd23..9705d03f849c 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -53,17 +53,21 @@ ENTRY(__high_start)
         mov     %rcx, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rcx, %cr4
 
-        /* WARNING! call/ret now fatal (iff SHSTK) until SETSSBSY loads SSP */
+        /* WARNING! CALL/RET now fatal (iff SHSTK) until SETSSBSY/RSTORSSP loads SSP */
 
 #if defined(CONFIG_XEN_SHSTK)
         test    $CET_SHSTK_EN, %al
         jz      .L_ap_cet_done
 
-        /* Derive the supervisor token address from %rsp. */
+        /* Derive the token address from %rsp. */
         mov     %rsp, %rdx
         and     $~(STACK_SIZE - 1), %rdx
         or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %rdx
 
+        /* Establishing SSP differs between IDT or FRED mode. */
+        bt      $32 /* ilog2(X86_CR4_FRED) */, %rcx
+        jc      .L_fred_shstk
+
         /*
          * Write a new Supervisor Token.  It doesn't matter the first time a
          * CPU boots, but for S3 resume or hotplug this clears the busy bit so
@@ -71,6 +75,21 @@ ENTRY(__high_start)
          */
         wrssq   %rdx, (%rdx)
         setssbsy
+        jmp     .L_ap_cet_done
+
+.L_fred_shstk:
+
+        /*
+         * Write a Restore Token, value: &token + 8 + 64BIT (bit 0) at the
+         * base of the shstk (which isn't in use yet).
+         */
+        lea     9(%rdx), %rdi
+        wrssq   %rdi, (%rdx)
+        rstorssp (%rdx)
+
+        /* Discard the Previous-SSP Token from the shstk. */
+        mov     $2, %edx
+        incsspd %edx
 
 #endif /* CONFIG_XEN_SHSTK */
 .L_ap_cet_done:
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index a810bdf6d352..73799fcc684c 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -49,6 +49,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -908,7 +909,29 @@ static void __init noreturn reinit_bsp_stack(void)
     if ( cpu_has_xen_shstk )
     {
         wrmsrl(MSR_S_CET, xen_msr_s_cet_value());
-        asm volatile ("setssbsy" ::: "memory");
+
+        /*
+         * IDT and FRED differ by a Supervisor Token on the shadow stack, and
+         * therefore by the value in MSR_PL0_SSP.
+         *
+         * In IDT mode, we use SETSSBSY to mark the Supervisor Token as busy.
+         * In FRED mode, there is no token, so we need to create a temporary
+         * Restore Token to establish SSP.
+         */
+        if ( opt_fred )
+        {
+            unsigned long *token =
+                (void *)stack + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8;
+
+            wrss((unsigned long)token + 9, token);
+            asm volatile ( "rstorssp %0" : "+m" (*token) );
+            /*
+             * We need to discard the resulting Previous-SSP Token, but
+             * reset_stack_and_jump() will do that for us.
+             */
+        }
+        else
+            asm volatile ( "setssbsy" ::: "memory" );
     }
 
     reset_stack_and_jump(init_done);
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 08/23] x86/traps: Alter switch_stack_and_jump() for FRED mode
Date: Thu, 28 Aug 2025 16:03:54 +0100
Message-Id: <20250828150409.901315-9-andrew.cooper3@citrix.com>
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FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
means that switch_stack_and_jump() needs to discard one extra word when FRED
is active.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Use X86_FEATURE_XEN_FRED
---
 xen/arch/x86/include/asm/current.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/xen/arch/x86/include/asm/current.h b/xen/arch/x86/include/asm/current.h
index c1eb27b1c4c2..35cc61fa88e7 100644
--- a/xen/arch/x86/include/asm/current.h
+++ b/xen/arch/x86/include/asm/current.h
@@ -154,7 +154,9 @@ unsigned long get_stack_dump_bottom (unsigned long sp);
     "rdsspd %[ssp];"                                            \
     "cmp $1, %[ssp];"                                           \
     "je .L_shstk_done.%=;" /* CET not active?  Skip. */         \
-    "mov $%c[skstk_base], %[val];"                              \
+    ALTERNATIVE("mov $%c[skstk_base], %[val];",                 \
+                "mov $%c[skstk_base] + 8, %[val];",             \
+                X86_FEATURE_XEN_FRED)                           \
     "and $%c[stack_mask], %[ssp];"                              \
     "sub %[ssp], %[val];"                                       \
     "shr $3, %[val];"                                           \
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 13/23] x86/traps: Introduce FRED entrypoints
Date: Thu, 28 Aug 2025 16:03:59 +0100
Message-Id: <20250828150409.901315-14-andrew.cooper3@citrix.com>
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Under FRED, there's one entrypoint from Ring 3, and one from Ring 0.

FRED gives us a good stack (even for SYSCALL/SYSENTER), and a unified event
frame on the stack, meaing that all software needs to do is spill the GPRs
with a line of PUSHes.  Introduce PUSH_AND_CLEAR_GPRS and POP_GPRS for this
purpose.

Introduce entry_FRED_R0() which to a first appoximation is complete for all
event handling within Xen.

entry_FRED_R0() needs deriving from entry_FRED_R3(), so introduce a basic
handler.  There is more work required to make the return-to-guest path work
under FRED, so leave a BUG clearly in place.

Also introduce entry_from_{xen,pv}() to be the C level handlers.  By simply
copying regs->fred_ss.vector into regs->entry_vector, we can reuse all the
existing fault handlers.

Extend fatal_trap() to render the event type, including by name, when FRED is
active.  This is slightly complicated, because X86_ET_OTHER must not use
vector_name() or SYSCALL and SYSENTER get rendered as #BP and #DB.  Also,
{read,write}_gs_shadow() needs modifying to avoid the SWAPGS instruction,
which is disallowed in FRED mode.

This is sufficient to handle all interrupts and exceptions encountered during
development, including plenty of Double Faults.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Don't render a vector name for X86_ET_SW_INT
 * Fix typos in names[]
 * Link entry-fred.o first

SIMICS hasn't been updated to the FRED v9, and still wants ENDBR instructions
at the entrypoints.
---
 xen/arch/x86/include/asm/asm_defns.h |  65 +++++++++++
 xen/arch/x86/traps.c                 | 159 ++++++++++++++++++++++++++-
 xen/arch/x86/x86_64/Makefile         |   1 +
 xen/arch/x86/x86_64/entry-fred.S     |  33 ++++++
 4 files changed, 255 insertions(+), 3 deletions(-)
 create mode 100644 xen/arch/x86/x86_64/entry-fred.S

diff --git a/xen/arch/x86/include/asm/asm_defns.h b/xen/arch/x86/include/asm/asm_defns.h
index 72a0082d319d..a81a4043d0f1 100644
--- a/xen/arch/x86/include/asm/asm_defns.h
+++ b/xen/arch/x86/include/asm/asm_defns.h
@@ -315,6 +315,71 @@ static always_inline void stac(void)
         subq  $-(UREGS_error_code-UREGS_r15+\adj), %rsp
 .endm
 
+/*
+ * Push and clear GPRs
+ */
+.macro PUSH_AND_CLEAR_GPRS
+        push  %rdi
+        xor   %edi, %edi
+        push  %rsi
+        xor   %esi, %esi
+        push  %rdx
+        xor   %edx, %edx
+        push  %rcx
+        xor   %ecx, %ecx
+        push  %rax
+        xor   %eax, %eax
+        push  %r8
+        xor   %r8d, %r8d
+        push  %r9
+        xor   %r9d, %r9d
+        push  %r10
+        xor   %r10d, %r10d
+        push  %r11
+        xor   %r11d, %r11d
+        push  %rbx
+        xor   %ebx, %ebx
+        push  %rbp
+#ifdef CONFIG_FRAME_POINTER
+/* Indicate special exception stack frame by inverting the frame pointer. */
+        mov   %rsp, %rbp
+        notq  %rbp
+#else
+        xor   %ebp, %ebp
+#endif
+        push  %r12
+        xor   %r12d, %r12d
+        push  %r13
+        xor   %r13d, %r13d
+        push  %r14
+        xor   %r14d, %r14d
+        push  %r15
+        xor   %r15d, %r15d
+.endm
+
+/*
+ * POP GPRs from a UREGS_* frame on the stack.  Does not modify flags.
+ *
+ * @rax: Alternative destination for the %rax value on the stack.
+ */
+.macro POP_GPRS rax=%rax
+        pop   %r15
+        pop   %r14
+        pop   %r13
+        pop   %r12
+        pop   %rbp
+        pop   %rbx
+        pop   %r11
+        pop   %r10
+        pop   %r9
+        pop   %r8
+        pop   \rax
+        pop   %rcx
+        pop   %rdx
+        pop   %rsi
+        pop   %rdi
+.endm
+
 #ifdef CONFIG_PV32
 #define CR4_PV32_RESTORE                               \
     ALTERNATIVE_2 "",                                  \
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 66308e7c9edf..67763bec0dc5 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -89,6 +89,13 @@ const unsigned int nmi_cpu;
 #define stack_words_per_line 4
 #define ESP_BEFORE_EXCEPTION(regs) ((unsigned long *)(regs)->rsp)
 
+/* Only valid to use when FRED is active. */
+static inline struct fred_info *cpu_regs_fred_info(struct cpu_user_regs *regs)
+{
+    ASSERT(read_cr4() & X86_CR4_FRED);
+    return (void *)(regs + 1);
+}
+
 struct extra_state
 {
     unsigned long cr0, cr2, cr3, cr4;
@@ -1023,6 +1030,32 @@ void show_execution_state_nmi(const cpumask_t *mask, bool show_all)
         printk("Non-responding CPUs: {%*pbl}\n", CPUMASK_PR(&show_state_mask));
 }
 
+static const char *x86_et_name(unsigned int type)
+{
+    static const char *const names[] = {
+        [X86_ET_EXT_INTR]    = "EXT_INTR",
+        [X86_ET_NMI]         = "NMI",
+        [X86_ET_HW_EXC]      = "HW_EXC",
+        [X86_ET_SW_INT]      = "SW_INT",
+        [X86_ET_PRIV_SW_EXC] = "PRIV_SW_EXC",
+        [X86_ET_SW_EXC]      = "SW_EXC",
+        [X86_ET_OTHER]       = "OTHER",
+    };
+
+    return (type < ARRAY_SIZE(names) && names[type]) ? names[type] : "???";
+}
+
+static const char *x86_et_other_name(unsigned int what)
+{
+    static const char *const names[] = {
+        [0] = "MTF",
+        [1] = "SYSCALL",
+        [2] = "SYSENTER",
+    };
+
+    return (what < ARRAY_SIZE(names) && names[what]) ? names[what] : "???";
+}
+
 const char *vector_name(unsigned int vec)
 {
     static const char names[][4] = {
@@ -1101,9 +1134,41 @@ void fatal_trap(const struct cpu_user_regs *regs, bool show_remote)
         }
     }
 
-    panic("FATAL TRAP: vec %u, %s[%04x]%s\n",
-          trapnr, vector_name(trapnr), regs->error_code,
-          (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
+    if ( read_cr4() & X86_CR4_FRED )
+    {
+        bool render_ec = false;
+        const char *vec_name = NULL;
+
+        switch ( regs->fred_ss.type )
+        {
+        case X86_ET_HW_EXC:
+        case X86_ET_PRIV_SW_EXC:
+        case X86_ET_SW_EXC:
+            render_ec = true;
+            vec_name = vector_name(regs->fred_ss.vector);
+            break;
+
+        case X86_ET_OTHER:
+            vec_name = x86_et_other_name(regs->fred_ss.vector);
+            break;
+        }
+
+        if ( render_ec )
+            panic("Fatal TRAP: type %u, %s, vec %u, %s[%04x]%s\n",
+                  regs->fred_ss.type, x86_et_name(regs->fred_ss.type),
+                  regs->fred_ss.vector, vec_name ?: "",
+                  regs->error_code,
+                  (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
+        else
+            panic("Fatal TRAP: type %u, %s, vec %u, %s%s\n",
+                  regs->fred_ss.type, x86_et_name(regs->fred_ss.type),
+                  regs->fred_ss.vector, vec_name ?: "",
+                  (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
+    }
+    else
+        panic("FATAL TRAP: vec %u, %s[%04x]%s\n",
+              trapnr, vector_name(trapnr), regs->error_code,
+              (regs->eflags & X86_EFLAGS_IF) ? "" : " IN INTERRUPT CONTEXT");
 }
 
 void asmlinkage noreturn do_unhandled_trap(struct cpu_user_regs *regs)
@@ -2198,6 +2263,94 @@ void asmlinkage check_ist_exit(const struct cpu_user_regs *regs, bool ist_exit)
 }
 #endif
 
+void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
+{
+    /* Copy fred_ss.vector into entry_vector as IDT delivery would have done. */
+    regs->entry_vector = regs->fred_ss.vector;
+
+    fatal_trap(regs, false);
+}
+
+void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
+{
+    struct fred_info *fi = cpu_regs_fred_info(regs);
+    uint8_t type = regs->fred_ss.type;
+
+    /* Copy fred_ss.vector into entry_vector as IDT delivery would have done. */
+    regs->entry_vector = regs->fred_ss.vector;
+
+    /*
+     * First, handle the asynchronous or fatal events.  These are either
+     * unrelated to the interrupted context, or may not have valid context
+     * recorded, and all have special rules on how/whether to re-enable IRQs.
+     */
+    switch ( type )
+    {
+    case X86_ET_EXT_INTR:
+        return do_IRQ(regs);
+
+    case X86_ET_NMI:
+        return do_nmi(regs);
+
+    case X86_ET_HW_EXC:
+        switch ( regs->fred_ss.vector )
+        {
+        case X86_EXC_DF: return do_double_fault(regs);
+        case X86_EXC_MC: return do_machine_check(regs);
+        }
+        break;
+    }
+
+    /*
+     * With the asynchronous events handled, what remains are the synchronous
+     * ones.  If we interrupted an IRQs-on region, we should re-enable IRQs
+     * now; for #PF and #DB, %cr2 and %dr6 are on the stack in edata.
+     */
+    if ( regs->eflags & X86_EFLAGS_IF )
+        local_irq_enable();
+
+    switch ( type )
+    {
+    case X86_ET_HW_EXC:
+    case X86_ET_PRIV_SW_EXC:
+    case X86_ET_SW_EXC:
+        switch ( regs->fred_ss.vector )
+        {
+        case X86_EXC_PF:  handle_PF(regs, fi->edata); break;
+        case X86_EXC_GP:  do_general_protection(regs); break;
+        case X86_EXC_UD:  do_invalid_op(regs); break;
+        case X86_EXC_NM:  do_device_not_available(regs); break;
+        case X86_EXC_BP:  do_int3(regs); break;
+        case X86_EXC_DB:  handle_DB(regs, fi->edata); break;
+
+        case X86_EXC_DE:
+        case X86_EXC_OF:
+        case X86_EXC_BR:
+        case X86_EXC_NP:
+        case X86_EXC_SS:
+        case X86_EXC_MF:
+        case X86_EXC_AC:
+        case X86_EXC_XM:
+            do_trap(regs);
+            break;
+
+        case X86_EXC_CP:  do_entry_CP(regs); break;
+
+        default:
+            goto fatal;
+        }
+        break;
+
+    default:
+        goto fatal;
+    }
+
+    return;
+
+ fatal:
+    fatal_trap(regs, false);
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/xen/arch/x86/x86_64/Makefile b/xen/arch/x86/x86_64/Makefile
index f20763088740..c0a0b6603221 100644
--- a/xen/arch/x86/x86_64/Makefile
+++ b/xen/arch/x86/x86_64/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_PV32) += compat/
 
+obj-bin-y += entry-fred.o
 obj-bin-y += entry.o
 obj-$(CONFIG_KEXEC) += machine_kexec.o
 obj-y += pci.o
diff --git a/xen/arch/x86/x86_64/entry-fred.S b/xen/arch/x86/x86_64/entry-fred.S
new file mode 100644
index 000000000000..3c3320df22cb
--- /dev/null
+++ b/xen/arch/x86/x86_64/entry-fred.S
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+        .file "x86_64/entry-fred.S"
+
+#include 
+#include 
+
+        .section .text.entry, "ax", @progbits
+
+        /* The Ring3 entry point is required to be 4k aligned. */
+
+FUNC(entry_FRED_R3, 4096)
+        PUSH_AND_CLEAR_GPRS
+
+        mov     %rsp, %rdi
+        call    entry_from_pv
+
+        POP_GPRS
+        eretu
+END(entry_FRED_R3)
+
+        /* The Ring0 entrypoint is at Ring3 + 0x100. */
+        .org entry_FRED_R3 + 0x100, 0xcc
+
+FUNC_LOCAL(entry_FRED_R0, 0)
+        PUSH_AND_CLEAR_GPRS
+
+        mov     %rsp, %rdi
+        call    entry_from_xen
+
+        POP_GPRS
+        erets
+END(entry_FRED_R0)
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 09/23] x86/traps: Skip Supervisor Shadow Stack tokens in FRED mode
Date: Thu, 28 Aug 2025 16:03:55 +0100
Message-Id: <20250828150409.901315-10-andrew.cooper3@citrix.com>
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FRED doesn't use Supervisor Shadow Stack tokens.  Skip setting them up.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New
---
 xen/arch/x86/mm.c    | 12 +++++++++---
 xen/arch/x86/setup.c |  8 ++++----
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c
index b929d15d0050..043e6aa9d73a 100644
--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -129,6 +129,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -6441,8 +6442,13 @@ static void write_sss_token(unsigned long *ptr)
 
 void memguard_guard_stack(void *p)
 {
-    /* IST Shadow stacks.  4x 1k in stack page 0. */
-    if ( IS_ENABLED(CONFIG_XEN_SHSTK) )
+    /*
+     * IST Shadow stacks.  4x 1k in stack page 0.
+     *
+     * With IDT delivery, we need Supervisor Shadow Stack tokens at the base
+     * of each stack.  With FRED delivery, these no longer exist.
+     */
+    if ( IS_ENABLED(CONFIG_XEN_SHSTK) && !opt_fred )
     {
         write_sss_token(p + (IST_MCE * IST_SHSTK_SIZE) - 8);
         write_sss_token(p + (IST_NMI * IST_SHSTK_SIZE) - 8);
@@ -6453,7 +6459,7 @@ void memguard_guard_stack(void *p)
 
     /* Primary Shadow Stack.  1x 4k in stack page 5. */
     p += PRIMARY_SHSTK_SLOT * PAGE_SIZE;
-    if ( IS_ENABLED(CONFIG_XEN_SHSTK) )
+    if ( IS_ENABLED(CONFIG_XEN_SHSTK) && !opt_fred )
         write_sss_token(p + PAGE_SIZE - 8);
 
     map_pages_to_xen((unsigned long)p, virt_to_mfn(p), 1, PAGE_HYPERVISOR_SHSTK);
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 73799fcc684c..c767d0451574 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1920,10 +1920,6 @@ void asmlinkage __init noreturn __start_xen(void)
 
     system_state = SYS_STATE_boot;
 
-    bsp_stack = cpu_alloc_stack(0);
-    if ( !bsp_stack )
-        panic("No memory for BSP stack\n");
-
     console_init_ring();
     vesa_init();
 
@@ -2077,6 +2073,10 @@ void asmlinkage __init noreturn __start_xen(void)
 
     traps_init(); /* Needs stubs allocated. */
 
+    bsp_stack = cpu_alloc_stack(0); /* Needs to know IDT vs FRED */
+    if ( !bsp_stack )
+        panic("No memory for BSP stack\n");
+
     cpu_init();
 
     rcu_init();
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 16/23] x86/entry: Alter how IRET faults are recognised
Date: Thu, 28 Aug 2025 16:04:02 +0100
Message-Id: <20250828150409.901315-17-andrew.cooper3@citrix.com>
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Right now we have two IRET instructions that can fault for guest reasons, and
the pre exception table gives handle_exception as the fixup for both.

Instead, we can have compat_restore_all_guest() use restore_all_guest()'s IRET
which gives us just a single position to handle specially.

In exception_with_ints_disabled(), remove search_pre_exception_table() and use
a simpler check.  Explain how the recovery works, because this isn't the first
time I've had to figure it out.

The reference to iret_to_guest highlights that any checking here is specific
to CONFIG_PV, so exclude it in !PV builds.

Later in exception_with_ints_disabled(), it suffices to load %ecx rather than
%rcx, and remove a stray semi-colon from the rep movsq.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New
---
 xen/arch/x86/x86_64/compat/entry.S |  3 +--
 xen/arch/x86/x86_64/entry.S        | 31 ++++++++++++++++++++++--------
 2 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/xen/arch/x86/x86_64/compat/entry.S b/xen/arch/x86/x86_64/compat/entry.S
index d7b381ea546d..39925d80a677 100644
--- a/xen/arch/x86/x86_64/compat/entry.S
+++ b/xen/arch/x86/x86_64/compat/entry.S
@@ -167,8 +167,7 @@ FUNC(compat_restore_all_guest)
             scf=STK_REL(CPUINFO_scf,      CPUINFO_rip), \
             sel=STK_REL(CPUINFO_verw_sel, CPUINFO_rip)
 
-.Lft0:  iretq
-        _ASM_PRE_EXTABLE(.Lft0, handle_exception)
+        jmp     iret_to_guest
 END(compat_restore_all_guest)
 
 /* Callers can cope with both %rax and %rcx being clobbered. */
diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
index c02245ac064c..01b431793b7b 100644
--- a/xen/arch/x86/x86_64/entry.S
+++ b/xen/arch/x86/x86_64/entry.S
@@ -241,8 +241,9 @@ iret_exit_to_guest:
         SPEC_CTRL_COND_VERW     /* Req: %rsp=eframe                    Clob: efl */
 
         addq  $8,%rsp
-.Lft0:  iretq
-        _ASM_PRE_EXTABLE(.Lft0, handle_exception)
+
+LABEL(iret_to_guest, 0)
+        iretq
 END(restore_all_guest)
 
 /*
@@ -920,10 +921,23 @@ handle_exception_saved:
 exception_with_ints_disabled:
         testb $3,UREGS_cs(%rsp)         # interrupts disabled outside Xen?
         jnz   FATAL_exception_with_ints_disabled
-        movq  %rsp,%rdi
-        call  search_pre_exception_table
-        testq %rax,%rax                 # no fixup code for faulting EIP?
-        jz    .Ldispatch_exceptions
+
+#ifndef CONFIG_PV
+        /* No PV?  No IRETs-to-guest to worry about. */
+        jmp .Ldispatch_exceptions
+#else
+        /* Check to see if the exception was on the IRET to guest context. */
+        lea   iret_to_guest(%rip), %rax
+        cmp   %rax, UREGS_rip(%rsp)
+        jne   .Ldispatch_exceptions
+
+        /*
+         * Recovery is at handle_exception.  It may be necessary to make space
+         * on the interrupted stack for ec/ev, after which the current ec/ev
+         * is copied to make it appear as if this exception occurred in guest
+         * context.
+         */
+        lea   handle_exception(%rip), %rax
         movq  %rax,UREGS_rip(%rsp)      # fixup regular stack
 
 #ifdef CONFIG_XEN_SHSTK
@@ -940,13 +954,14 @@ exception_with_ints_disabled:
         movq  %rsp,%rsi
         subq  $8,%rsp
         movq  %rsp,%rdi
-        movq  $UREGS_kernel_sizeof/8,%rcx
-        rep;  movsq                     # make room for ec/ev
+        mov   $UREGS_kernel_sizeof/8, %ecx
+        rep movsq                       # make room for ec/ev
 1:      movq  UREGS_error_code(%rsp),%rax # ec/ev
         movq  %rax,UREGS_kernel_sizeof(%rsp)
         mov   %r15, STACK_CPUINFO_FIELD(xen_cr3)(%r14)
         mov   %r13b, STACK_CPUINFO_FIELD(use_pv_cr3)(%r14)
         jmp   restore_all_xen           # return to fixup code
+#endif /* !CONFIG_PV */
 
 /* No special register assumptions. */
 FATAL_exception_with_ints_disabled:
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 03/23] x86/traps: Introduce opt_fred
Date: Thu, 28 Aug 2025 16:03:49 +0100
Message-Id: <20250828150409.901315-4-andrew.cooper3@citrix.com>
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... disabled by default.  There is a lot of work before FRED can be enabled by
default.

One part of FRED, the LKGS (Load Kernel GS) instruction, is enumerated
separately but is mandatory as FRED disallows the SWAPGS instruction.
Normally, we'd have to check both CPUID bits, but Xen does not use GS like
most other software, and can manage without the LKGS instruction.

FRED formally removes the use of Ring1 and Ring2, meaning we cannot run 32bit
PV guests.  Therefore, don't enable FRED by default in shim mode.  OTOH, if
FRED is active, then PV32 needs disabling like with CET.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Fix check for warning.
 * Drop check for LKGS.
---
 docs/misc/xen-command-line.pandoc | 10 +++++++++
 xen/arch/x86/include/asm/traps.h  |  4 ++++
 xen/arch/x86/traps-setup.c        | 36 +++++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index a75b6c930195..25cebdc1110f 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -1284,6 +1284,16 @@ requirement can be relaxed.  This option is particularly useful for nested
 virtualization, to allow the L1 hypervisor to use EPT even if the L0 hypervisor
 does not provide `VM_ENTRY_LOAD_GUEST_PAT`.
 
+### fred (x86)
+> `= `
+
+> Default: `false`
+
+Flexible Return and Event Delivery is an overhaul of interrupt, exception and
+system call handling, fixing many corner cases in the x86 architecture, and
+expected in hardware from 2025.  Support in Xen is a work in progress and
+disabled by default.
+
 ### gnttab
 > `= List of [ max-ver:, transitive=, transfer= ]`
 
diff --git a/xen/arch/x86/include/asm/traps.h b/xen/arch/x86/include/asm/traps.h
index 6ae451d3fc70..73097e957d05 100644
--- a/xen/arch/x86/include/asm/traps.h
+++ b/xen/arch/x86/include/asm/traps.h
@@ -7,6 +7,10 @@
 #ifndef ASM_TRAP_H
 #define ASM_TRAP_H
 
+#include 
+
+extern int8_t opt_fred;
+
 void bsp_early_traps_init(void);
 void traps_init(void);
 void bsp_traps_reinit(void);
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index c89280270fbb..6e2af58ba0a5 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -9,6 +9,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -20,6 +22,9 @@ unsigned int __ro_after_init ler_msr;
 static bool __initdata opt_ler;
 boolean_param("ler", opt_ler);
 
+int8_t __ro_after_init opt_fred = 0;
+boolean_param("fred", opt_fred);
+
 void nocall entry_PF(void);
 void nocall lstar_enter(void);
 void nocall cstar_enter(void);
@@ -299,6 +304,37 @@ void __init traps_init(void)
     /* Replace early pagefault with real pagefault handler. */
     _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF);
 
+    /*
+     * Xen doesn't use GS like most software does, and doesn't need the LKGS
+     * instruction in order to manage PV guests.  No need to check for it.
+     */
+    if ( !cpu_has_fred )
+    {
+        if ( opt_fred == 1 )
+            printk(XENLOG_WARNING "FRED not available, ignoring\n");
+        opt_fred = 0;
+    }
+
+    if ( opt_fred == -1 )
+        opt_fred = !pv_shim;
+
+    if ( opt_fred )
+    {
+#ifdef CONFIG_PV32
+        if ( opt_pv32 )
+        {
+            opt_pv32 = 0;
+            printk(XENLOG_INFO "Disabling PV32 due to FRED\n");
+        }
+#endif
+        setup_force_cpu_cap(X86_FEATURE_XEN_FRED);
+        printk("Using FRED event delivery\n");
+    }
+    else
+    {
+        printk("Using IDT event delivery\n");
+    }
+
     load_system_tables();
 
     init_ler();
-- 
2.39.5



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        Thu, 28 Aug 2025 08:06:24 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 21/23] x86/pv: ERETU error handling
Date: Thu, 28 Aug 2025 16:04:07 +0100
Message-Id: <20250828150409.901315-22-andrew.cooper3@citrix.com>
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ERETU can fault for guest reasons, and like IRET needs special handling to
forward the error into the guest.

As this is largely written in C, take the opportunity to better classify the
sources of error, and in particilar, not forward errors that are actually
Xen's fault into the guest, opting for a domain crash instead.

Because ERETU does not enable NMIs if it faults, a corner case exists if an
NMI was taken while in guest context, and the ERETU back out faults.  Recovery
must involve an ERETS with the interrupted context's NMI flag.

See the comments for full details.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New
---
 xen/arch/x86/traps.c             | 115 +++++++++++++++++++++++++++++++
 xen/arch/x86/x86_64/entry-fred.S |  13 ++++
 2 files changed, 128 insertions(+)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 72df446a6a78..e10b4e771824 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2345,6 +2345,113 @@ void asmlinkage entry_from_pv(struct cpu_user_regs *regs)
     fatal_trap(regs, false);
 }
 
+void nocall eretu_error_dom_crash(void);
+
+/*
+ * Classify an event at the ERETU instruction, and handle if possible.
+ * Returns @true if handled, @false if the event should continue down the
+ * normal handlers.
+ */
+static bool handle_eretu_event(struct cpu_user_regs *regs)
+{
+    unsigned long recover;
+
+    /*
+     * WARNING: The GPRs in gregs overlaps with regs.  Only gregs->error_code
+     *          and later are legitimate to access.
+     */
+    struct cpu_user_regs *gregs =
+        _p(regs->rsp - offsetof(struct cpu_user_regs, error_code));
+
+    /*
+     * The asynchronous or fatal events (INTR, NMI, #MC, #DF) have been dealt
+     * with, meaning we only have syncrhonous ones to consider.  Anything
+     * which isn't a hardware exception wants handling normally.
+     */
+    if ( regs->fred_ss.type != X86_ET_HW_EXC )
+        return false;
+
+    /*
+     * Guests are permitted to write non-present GDT/LDT entries.  Therefore
+     * #NP[sel] (%cs) and #SS[sel] (%ss) must be handled as guest errors.  The
+     * only other source of #SS is for a bad %ss-relative memory access in
+     * Xen, and if the stack is that bad, we'll have escalated to #DF.
+     *
+     * #PF can happen from ERETU accessing the GDT/LDT.  Xen may translate
+     * these into #GP for the guest, so must be handled as guest errors.  In
+     * theory we can get #PF for a bad instruction fetch or bad stack access,
+     * but either of these will be fatal and not end up here.
+     */
+    switch ( regs->fred_ss.vector )
+    {
+    case X86_EXC_GP:
+        /*
+         * #GP[0] can occur because of a NULL %cs or %ss (which are a guest
+         * error), but some #GP[0]'s are errors in Xen (ERETU at SL != 0), or
+         * errors of Xen handling guest state (bad metadata).  These magic
+         * numbers came from the FRED Spec; they check that ERETU is trying to
+         * return to Ring 3, and that reserved or inapplicable bits are 0.
+         */
+        if ( regs->error_code == 0 && (gregs->cs & ~3) && (gregs->ss & ~3) &&
+             (regs->fred_cs.sl != 0 ||
+              (gregs->csx    & 0xffffffffffff0003UL) != 3 ||
+              (gregs->rflags & 0xffffffffffc2b02aUL) != 2 ||
+              (gregs->ssx    &         0xfff80003UL) != 3) )
+        {
+            recover = (unsigned long)eretu_error_dom_crash;
+
+            if ( regs->fred_cs.sl )
+                gprintk(XENLOG_ERR, "ERETU at SL %u\n", regs->fred_cs.sl);
+            else
+                gprintk(XENLOG_ERR, "Bad return state: csx %#lx, rflags %#lx, ssx %#x\n",
+                        gregs->csx, gregs->rflags, (unsigned int)gregs->ssx);
+            break;
+        }
+        fallthrough;
+    case X86_EXC_NP:
+    case X86_EXC_SS:
+    case X86_EXC_PF:
+        recover = (unsigned long)entry_FRED_R3;
+        break;
+
+        /*
+         * Handle everything else normally.  #BP and #DB would be debugging
+         * activities in Xen.  In theory we can get #UD if CR4.FRED gets
+         * cleared, but in practice if that were the case we wouldn't be here
+         * handling the result.
+         */
+    default:
+        return false;
+    }
+
+    this_cpu(last_extable_addr) = regs->rip;
+
+    /*
+     * Everything else is recoverable, one way or another.
+     *
+     * If an NMI was taken in guest context and the ERETU faulted, NMIs will
+     * still be blocked.  Therefore we copy the interrupted frame's NMI status
+     * into our own, and must ERETS as part of recovery.
+     */
+    regs->fred_ss.nmi = gregs->fred_ss.nmi;
+
+    /*
+     * Next, copy the exception information from the current frame back onto
+     * the interrupted frame, preserving the interrupted frame's %cs and %ss.
+     */
+    *cpu_regs_fred_info(regs) = *cpu_regs_fred_info(gregs);
+    gregs->ssx = (regs->ssx & ~0xffff) | gregs->ss;
+    gregs->csx = (regs->csx & ~0xffff) | gregs->cs;
+    gregs->error_code   = regs->error_code;
+    gregs->entry_vector = regs->entry_vector;
+
+    fixup_exception_return(regs, recover, 0);
+
+    return true;
+}
+
+void nocall eretu(void);
+
 void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
 {
     struct fred_info *fi = cpu_regs_fred_info(regs);
@@ -2383,6 +2490,14 @@ void asmlinkage entry_from_xen(struct cpu_user_regs *regs)
     if ( regs->eflags & X86_EFLAGS_IF )
         local_irq_enable();
 
+    /*
+     * An event taken at the ERETU instruction may be because of guest state
+     * and in that case will need special handling.
+     */
+    if ( unlikely(regs->rip == (unsigned long)eretu) &&
+         handle_eretu_event(regs) )
+        return;
+
     switch ( type )
     {
     case X86_ET_HW_EXC:
diff --git a/xen/arch/x86/x86_64/entry-fred.S b/xen/arch/x86/x86_64/entry-fred.S
index 07684f38a078..8b5cafb866e2 100644
--- a/xen/arch/x86/x86_64/entry-fred.S
+++ b/xen/arch/x86/x86_64/entry-fred.S
@@ -27,9 +27,22 @@ END(entry_FRED_R3)
 
 FUNC(eretu_exit_to_guest)
         POP_GPRS
+
+        /*
+         * Exceptions here are handled by redirecting either to
+         * entry_FRED_R3() (for an error to be passed to the guest), or to
+         * eretu_error_dom_crash() (for a Xen error handling guest state).
+         */
+LABEL(eretu, 0)
         eretu
 END(eretu_exit_to_guest)
 
+FUNC(eretu_error_dom_crash)
+        PUSH_AND_CLEAR_GPRS
+        sti
+        call    asm_domain_crash_synchronous  /* Does not return */
+END(eretu_error_dom_crash)
+
         /* The Ring0 entrypoint is at Ring3 + 0x100. */
         .org entry_FRED_R3 + 0x100, 0xcc
 
-- 
2.39.5



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        Thu, 28 Aug 2025 08:06:13 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 15/23] x86/pv: Deduplicate is_canonical_address() in do_set_segment_base()
Date: Thu, 28 Aug 2025 16:04:01 +0100
Message-Id: <20250828150409.901315-16-andrew.cooper3@citrix.com>
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This is really a rearrangement to make adding FRED support easier.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New

There is a marginal code size improvement:

  add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-46 (-46)
  Function                                     old     new   delta
  do_set_segment_base                          496     450     -46

but it does get undone by the FRED support.
---
 xen/arch/x86/pv/misc-hypercalls.c | 32 ++++++++++++++++---------------
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/xen/arch/x86/pv/misc-hypercalls.c b/xen/arch/x86/pv/misc-hypercalls.c
index 7a37f16bf038..4c2abeb4add8 100644
--- a/xen/arch/x86/pv/misc-hypercalls.c
+++ b/xen/arch/x86/pv/misc-hypercalls.c
@@ -176,27 +176,29 @@ long do_set_segment_base(unsigned int which, unsigned long base)
     switch ( which )
     {
     case SEGBASE_FS:
-        if ( is_canonical_address(base) )
-            write_fs_base(base);
-        else
+    case SEGBASE_GS_USER:
+    case SEGBASE_GS_KERNEL:
+        if ( !is_canonical_address(base) )
+        {
             ret = -EINVAL;
-        break;
+            break;
+        }
 
-    case SEGBASE_GS_USER:
-        if ( is_canonical_address(base) )
+        switch ( which )
         {
-            write_gs_shadow(base);
+        case SEGBASE_FS:
+            write_fs_base(base);
+            break;
+
+        case SEGBASE_GS_USER:
             v->arch.pv.gs_base_user = base;
-        }
-        else
-            ret = -EINVAL;
-        break;
+            write_gs_shadow(base);
+            break;
 
-    case SEGBASE_GS_KERNEL:
-        if ( is_canonical_address(base) )
+        case SEGBASE_GS_KERNEL:
             write_gs_base(base);
-        else
-            ret = -EINVAL;
+            break;
+        }
         break;
 
     case SEGBASE_GS_USER_SEL:
-- 
2.39.5



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        Thu, 28 Aug 2025 08:06:16 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 17/23] x86/entry: Drop the pre exception table infrastructure
Date: Thu, 28 Aug 2025 16:04:03 +0100
Message-Id: <20250828150409.901315-18-andrew.cooper3@citrix.com>
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It is no longer used.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New
---
 xen/arch/x86/extable.c               | 14 --------------
 xen/arch/x86/include/asm/asm_defns.h | 11 ++++-------
 xen/arch/x86/include/asm/uaccess.h   |  2 --
 xen/arch/x86/xen.lds.S               |  5 -----
 4 files changed, 4 insertions(+), 28 deletions(-)

diff --git a/xen/arch/x86/extable.c b/xen/arch/x86/extable.c
index cf637d0921e4..a9b6c6b904f5 100644
--- a/xen/arch/x86/extable.c
+++ b/xen/arch/x86/extable.c
@@ -61,7 +61,6 @@ void init_or_livepatch sort_exception_table(struct exception_table_entry *start,
 void __init sort_exception_tables(void)
 {
     sort_exception_table(__start___ex_table, __stop___ex_table);
-    sort_exception_table(__start___pre_ex_table, __stop___pre_ex_table);
 }
 
 static unsigned long
@@ -219,16 +218,3 @@ int __init cf_check stub_selftest(void)
 }
 __initcall(stub_selftest);
 #endif /* CONFIG_SELF_TESTS */
-
-unsigned long asmlinkage search_pre_exception_table(struct cpu_user_regs *regs)
-{
-    unsigned long addr = regs->rip;
-    unsigned long fixup = search_one_extable(
-        __start___pre_ex_table, __stop___pre_ex_table, addr);
-    if ( fixup )
-    {
-        dprintk(XENLOG_INFO, "Pre-exception: %p -> %p\n", _p(addr), _p(fixup));
-        perfc_incr(exception_fixed);
-    }
-    return fixup;
-}
diff --git a/xen/arch/x86/include/asm/asm_defns.h b/xen/arch/x86/include/asm/asm_defns.h
index a81a4043d0f1..d7eafedf0e4c 100644
--- a/xen/arch/x86/include/asm/asm_defns.h
+++ b/xen/arch/x86/include/asm/asm_defns.h
@@ -65,22 +65,19 @@ register unsigned long current_stack_pointer asm("rsp");
 
 /* Exception table entry */
 #ifdef __ASSEMBLY__
-# define _ASM__EXTABLE(sfx, from, to)             \
-    .section .ex_table##sfx, "a" ;                \
+# define _ASM_EXTABLE(from, to)                   \
+    .section .ex_table, "a" ;                     \
     .balign 4 ;                                   \
     .long _ASM_EX(from), _ASM_EX(to) ;            \
     .previous
 #else
-# define _ASM__EXTABLE(sfx, from, to)             \
-    " .section .ex_table" #sfx ",\"a\"\n"         \
+# define _ASM_EXTABLE(from, to)                   \
+    " .section .ex_table,\"a\"\n"                 \
     " .balign 4\n"                                \
     " .long " _ASM_EX(from) ", " _ASM_EX(to) "\n" \
     " .previous\n"
 #endif
 
-#define _ASM_EXTABLE(from, to)     _ASM__EXTABLE(, from, to)
-#define _ASM_PRE_EXTABLE(from, to) _ASM__EXTABLE(.pre, from, to)
-
 #ifdef __ASSEMBLY__
 
 .macro BUILD_BUG_ON condstr, cond:vararg
diff --git a/xen/arch/x86/include/asm/uaccess.h b/xen/arch/x86/include/asm/uaccess.h
index 719d053936b9..4c41a0fe0426 100644
--- a/xen/arch/x86/include/asm/uaccess.h
+++ b/xen/arch/x86/include/asm/uaccess.h
@@ -410,8 +410,6 @@ struct exception_table_entry
 };
 extern struct exception_table_entry __start___ex_table[];
 extern struct exception_table_entry __stop___ex_table[];
-extern struct exception_table_entry __start___pre_ex_table[];
-extern struct exception_table_entry __stop___pre_ex_table[];
 
 union stub_exception_token {
     struct {
diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S
index 966e514f2034..66075bc0ae6d 100644
--- a/xen/arch/x86/xen.lds.S
+++ b/xen/arch/x86/xen.lds.S
@@ -119,11 +119,6 @@ SECTIONS
        *(.ex_table)
        __stop___ex_table = .;
 
-       /* Pre-exception table */
-       __start___pre_ex_table = .;
-       *(.ex_table.pre)
-       __stop___pre_ex_table = .;
-
        . = ALIGN(PAGE_SIZE);
        __ro_after_init_end = .;
 
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 06/23] x86/traps: Set MSR_PL0_SSP in load_system_tables()
Date: Thu, 28 Aug 2025 16:03:52 +0100
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FRED and IDT differ by a Supervisor Token on the base of the shstk.  This
means that the value they load into MSR_PL0_SSP differs by 8.

s3_resume() in particular has logic which is otherwise invariant of FRED mode,
and must not clobber a FRED MSR_PL0_SSP with an IDT one.

This also simplifies the AP path too.  Updating reinit_bsp_stack() is deferred
until later.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Extend comment about clearing the busy bit.
 * Move reinit_bsp_stack() hunk into this patch.
---
 xen/arch/x86/acpi/wakeup_prot.S |  9 ---------
 xen/arch/x86/boot/x86_64.S      | 12 +++---------
 xen/arch/x86/setup.c            |  2 --
 xen/arch/x86/traps-setup.c      |  2 ++
 4 files changed, 5 insertions(+), 20 deletions(-)

diff --git a/xen/arch/x86/acpi/wakeup_prot.S b/xen/arch/x86/acpi/wakeup_prot.S
index fceb4ca353f7..ba0bd77806b8 100644
--- a/xen/arch/x86/acpi/wakeup_prot.S
+++ b/xen/arch/x86/acpi/wakeup_prot.S
@@ -104,15 +104,6 @@ LABEL(s3_resume)
          */
         mov     saved_ssp(%rip), %rdi
 
-        /* Calculate MSR_PL0_SSP from SSP. */
-        mov     $MSR_PL0_SSP, %ecx
-        mov     %rdi, %rdx
-        shr     $32, %rdx
-        mov     %edi, %eax
-        and     $~(STACK_SIZE - 1), %eax
-        or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %eax
-        wrmsr
-
         /*
          * A Restore Token's value is &token + 8 + 64BIT (bit 0).
          * We want to put this on the shstk at SSP - 8.
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index 3a5ad2764448..11a7e9d3bd23 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -65,17 +65,11 @@ ENTRY(__high_start)
         or      $(PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8, %rdx
 
         /*
-         * Write a new supervisor token.  Doesn't matter on boot, but for S3
-         * resume this clears the busy bit.
+         * Write a new Supervisor Token.  It doesn't matter the first time a
+         * CPU boots, but for S3 resume or hotplug this clears the busy bit so
+         * SETSSBSY can set it again.
          */
         wrssq   %rdx, (%rdx)
-
-        /* Point MSR_PL0_SSP at the token. */
-        mov     $MSR_PL0_SSP, %ecx
-        mov     %edx, %eax
-        shr     $32, %rdx
-        wrmsr
-
         setssbsy
 
 #endif /* CONFIG_XEN_SHSTK */
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 6c81841426a4..a810bdf6d352 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -907,8 +907,6 @@ static void __init noreturn reinit_bsp_stack(void)
 
     if ( cpu_has_xen_shstk )
     {
-        wrmsrl(MSR_PL0_SSP,
-               (unsigned long)stack + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8);
         wrmsrl(MSR_S_CET, xen_msr_s_cet_value());
         asm volatile ("setssbsy" ::: "memory");
     }
diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c
index 6e2af58ba0a5..d77be8f83921 100644
--- a/xen/arch/x86/traps-setup.c
+++ b/xen/arch/x86/traps-setup.c
@@ -92,6 +92,7 @@ static void load_system_tables(void)
     {
         volatile uint64_t *ist_ssp = tss_page->ist_ssp;
         unsigned long
+            ssp = stack_top + (PRIMARY_SHSTK_SLOT + 1) * PAGE_SIZE - 8,
             mce_ssp = stack_top + (IST_MCE * IST_SHSTK_SIZE) - 8,
             nmi_ssp = stack_top + (IST_NMI * IST_SHSTK_SIZE) - 8,
             db_ssp  = stack_top + (IST_DB  * IST_SHSTK_SIZE) - 8,
@@ -118,6 +119,7 @@ static void load_system_tables(void)
         }
 
         wrmsrns(MSR_ISST, (unsigned long)ist_ssp);
+        wrmsrns(MSR_PL0_SSP, (unsigned long)ssp);
     }
 
     _set_tssldt_desc(gdt + TSS_ENTRY, (unsigned long)tss,
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 12/23] x86/fsgsbase: Make gskern accesses safe under FRED
Date: Thu, 28 Aug 2025 16:03:58 +0100
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Under FRED, the SWAPGS instructions is disallowed.  Therefore we must use the
MSR path instead.

read_registers() is in the show_registers() path, so this allows Xen to render
it's current state without suffering #UD (and recursing until the stack guard
page is hit).

All hardware with FRED is expected to have some kind of non-serialising access
to these registers.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Broken out of subsequent patch.  Rebased over MSR cleanup.

In principle, the following can also be used for read_registers()

    diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
    index 5799770a2f71..0b0fdf2c5ac4 100644
    --- a/xen/arch/x86/traps.c
    +++ b/xen/arch/x86/traps.c
    @@ -125,16 +125,21 @@ static void read_registers(struct extra_state *state)
         state->cr3 = read_cr3();
         state->cr4 = read_cr4();

    -    if ( !(state->cr4 & X86_CR4_FRED) && (state->cr4 & X86_CR4_FSGSBASE) )
    +    if ( state->cr4 & X86_CR4_FSGSBASE )
         {
             state->fsb = __rdfsbase();
             state->gsb = __rdgsbase();
    +
    +        if ( state->cr4 & X86_CR4_FRED )
    +            goto gskern_fred;
    +
             state->gss = __rdgskern();
         }
         else
         {
             state->fsb = rdmsr(MSR_FS_BASE);
             state->gsb = rdmsr(MSR_GS_BASE);
    +    gskern_fred:
             state->gss = rdmsr(MSR_SHADOW_GS_BASE);
         }

but I'm not sure that it's a good enough improvement to warrant the
complexity.
---
 xen/arch/x86/include/asm/fsgsbase.h | 8 ++++++--
 xen/arch/x86/traps.c                | 2 +-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/include/asm/fsgsbase.h b/xen/arch/x86/include/asm/fsgsbase.h
index 24862a6bfea7..5faa3a324332 100644
--- a/xen/arch/x86/include/asm/fsgsbase.h
+++ b/xen/arch/x86/include/asm/fsgsbase.h
@@ -79,7 +79,9 @@ static inline unsigned long read_gs_base(void)
 
 static inline unsigned long read_gs_shadow(void)
 {
-    if ( read_cr4() & X86_CR4_FSGSBASE )
+    unsigned long cr4 = read_cr4();
+
+    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
         return __rdgs_shadow();
     else
         return rdmsr(MSR_SHADOW_GS_BASE);
@@ -103,7 +105,9 @@ static inline void write_gs_base(unsigned long base)
 
 static inline void write_gs_shadow(unsigned long base)
 {
-    if ( read_cr4() & X86_CR4_FSGSBASE )
+    unsigned long cr4 = read_cr4();
+
+    if ( !(cr4 & X86_CR4_FRED) && (cr4 & X86_CR4_FSGSBASE) )
         __wrgs_shadow(base);
     else
         wrmsrns(MSR_SHADOW_GS_BASE, base);
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index c11d72d47027..66308e7c9edf 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -118,7 +118,7 @@ static void read_registers(struct extra_state *state)
     state->cr3 = read_cr3();
     state->cr4 = read_cr4();
 
-    if ( state->cr4 & X86_CR4_FSGSBASE )
+    if ( !(state->cr4 & X86_CR4_FRED) && (state->cr4 & X86_CR4_FSGSBASE) )
     {
         state->fsb = __rdfsbase();
         state->gsb = __rdgsbase();
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 18/23] x86/entry: Rework the comment about SYSCALL and DF
Date: Thu, 28 Aug 2025 16:04:04 +0100
Message-Id: <20250828150409.901315-19-andrew.cooper3@citrix.com>
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It's soon going to be needed in a second location.

Right now it's misleading saying that nothing else would be cleared.  It's
missing the more important point that SYSCALLs are treated like all other
interrupts and exceptions, and undergo normal flags handling there.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New
---
 xen/arch/x86/x86_64/entry.S | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
index 01b431793b7b..ca446c6ff0ce 100644
--- a/xen/arch/x86/x86_64/entry.S
+++ b/xen/arch/x86/x86_64/entry.S
@@ -39,10 +39,9 @@ FUNC_LOCAL(switch_to_kernel)
         leal  (,%rcx,TBF_INTERRUPT),%ecx
 
         /*
-         * The PV ABI hardcodes the (guest-inaccessible and virtual)
-         * SYSCALL_MASK MSR such that DF (and nothing else) would be cleared.
-         * Note that the equivalent of IF (VGCF_syscall_disables_events) is
-         * dealt with separately above.
+         * The PV ABI, given no virtual SYSCALL_MASK, hardcodes that DF is
+         * cleared.  Other flags are handled in the same way as interrupts and
+         * exceptions in create_bounce_frame().
          */
         mov   $~X86_EFLAGS_DF, %esi
 
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 10/23] x86/traps: Make an IDT-specific #DB helper
Date: Thu, 28 Aug 2025 16:03:56 +0100
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FRED provides PENDING_DBG in the the stack frame, avoiding the need to read
%dr6 manually.

Rename do_debug() to handle_DB(), and update it to take a dbg field using
positive polarity.

Introduce a new handle_DB_IDT() which reads %dr6.

No functional change.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * New
---
 xen/arch/x86/traps.c        | 28 +++++++++++++++++-----------
 xen/arch/x86/x86_64/entry.S |  2 +-
 2 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 7ae46ae20f98..0372f1c386a8 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1992,14 +1992,11 @@ void asmlinkage do_device_not_available(struct cpu_user_regs *regs)
 
 void nocall sysenter_eflags_saved(void);
 
-void asmlinkage do_debug(struct cpu_user_regs *regs)
+/* Handle #DB.  @dbg is PENDING_DBG, a.k.a. %dr6 with positive polarity. */
+static void handle_DB(struct cpu_user_regs *regs, unsigned long dbg)
 {
-    unsigned long dr6;
     struct vcpu *v = current;
 
-    /* Stash dr6 as early as possible. */
-    dr6 = read_debugreg(6);
-
     /*
      * At the time of writing (March 2018), on the subject of %dr6:
      *
@@ -2066,13 +2063,13 @@ void asmlinkage do_debug(struct cpu_user_regs *regs)
          * If however we do, safety measures need to be enacted.  Use a big
          * hammer and clear all debug settings.
          */
-        if ( dr6 & (DR_TRAP3 | DR_TRAP2 | DR_TRAP1 | DR_TRAP0) )
+        if ( dbg & (DR_TRAP3 | DR_TRAP2 | DR_TRAP1 | DR_TRAP0) )
         {
             unsigned int bp, dr7 = read_debugreg(7);
 
             for ( bp = 0; bp < 4; ++bp )
             {
-                if ( (dr6 & (1u << bp)) && /* Breakpoint triggered? */
+                if ( (dbg & (1u << bp)) && /* Breakpoint triggered? */
                      (dr7 & (3u << (bp * DR_ENABLE_SIZE))) && /* Enabled? */
                      ((dr7 & (3u << ((bp * DR_CONTROL_SIZE) + /* Insn? */
                                      DR_CONTROL_SHIFT))) == DR_RW_EXECUTE) )
@@ -2093,9 +2090,9 @@ void asmlinkage do_debug(struct cpu_user_regs *regs)
          * so ensure the message is ratelimited.
          */
         gprintk(XENLOG_WARNING,
-                "Hit #DB in Xen context: %04x:%p [%ps], stk %04x:%p, dr6 %lx\n",
+                "Hit #DB in Xen context: %04x:%p [%ps], stk %04x:%p, dbg %lx\n",
                 regs->cs, _p(regs->rip), _p(regs->rip),
-                regs->ss, _p(regs->rsp), dr6);
+                regs->ss, _p(regs->rsp), dbg);
 
         return;
     }
@@ -2107,7 +2104,7 @@ void asmlinkage do_debug(struct cpu_user_regs *regs)
      * by debugging actions completed behind it's back.
      */
     v->arch.dr6 = x86_merge_dr6(v->domain->arch.cpu_policy,
-                                v->arch.dr6, dr6 ^ X86_DR6_DEFAULT);
+                                v->arch.dr6, dbg);
 
     if ( guest_kernel_mode(v, regs) && v->domain->debugger_attached )
     {
@@ -2115,7 +2112,16 @@ void asmlinkage do_debug(struct cpu_user_regs *regs)
         return;
     }
 
-    pv_inject_DB(dr6 ^ X86_DR6_DEFAULT);
+    pv_inject_DB(dbg);
+}
+
+/*
+ * When using IDT delivery, it is our responsibility to read %dr6.  Convert it
+ * to positive polarity.
+ */
+void asmlinkage handle_DB_IDT(struct cpu_user_regs *regs)
+{
+    handle_DB(regs, read_debugreg(6) ^ X86_DR6_DEFAULT);
 }
 
 void asmlinkage do_entry_CP(struct cpu_user_regs *regs)
diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
index 39c7b9d17f9e..789687488c5f 100644
--- a/xen/arch/x86/x86_64/entry.S
+++ b/xen/arch/x86/x86_64/entry.S
@@ -1171,7 +1171,7 @@ FUNC(handle_ist_exception)
 .L_ ## vec ## _done:
 
         DISPATCH(X86_EXC_NMI, do_nmi)
-        DISPATCH(X86_EXC_DB,  do_debug)
+        DISPATCH(X86_EXC_DB,  handle_DB_IDT)
         DISPATCH(X86_EXC_MC,  do_machine_check)
 #undef DISPATCH
 
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH v2 04/23] x86/boot: Adjust CR4 handling around percpu_early_traps_init()
Date: Thu, 28 Aug 2025 16:03:50 +0100
Message-Id: <20250828150409.901315-5-andrew.cooper3@citrix.com>
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percpu_early_traps_init() will shortly be setting CR4.FRED.  This requires that
cpu_info->cr4 is already set up, and that the enablement of CET doesn't
truncate X86_CR4_FRED back out because of 32bit logic.

For __high_start(), defer re-loading XEN_MINIMAL_CR4 until after %rsp is set
up and we can store the result in the cr4 field too.

For s3_resume(), explicitly re-load XEN_MINIMAL_CR4.  Later when loading all
features, use the mmu_cr4_features variable which is how the rest of Xen
performs this operation.

No functional change, yet.

Signed-off-by: Andrew Cooper 
Reviewed-by: Jan Beulich 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

v2:
 * Extend comments
---
 xen/arch/x86/acpi/wakeup_prot.S | 18 ++++++++++++++----
 xen/arch/x86/boot/x86_64.S      | 15 ++++++++++-----
 2 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/xen/arch/x86/acpi/wakeup_prot.S b/xen/arch/x86/acpi/wakeup_prot.S
index cc40fddc38d4..0f02ea7b4b9a 100644
--- a/xen/arch/x86/acpi/wakeup_prot.S
+++ b/xen/arch/x86/acpi/wakeup_prot.S
@@ -63,6 +63,14 @@ LABEL(s3_resume)
         pushq   %rax
         lretq
 1:
+
+        GET_STACK_END(15)
+
+        /* Enable minimal CR4 features, sync cached state. */
+        mov     $XEN_MINIMAL_CR4, %eax
+        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
+        mov     %rax, %cr4
+
         /* Set up early exceptions and CET before entering C properly. */
         call    percpu_early_traps_init
 
@@ -77,7 +85,9 @@ LABEL(s3_resume)
         wrmsr
 
         /* Enable CR4.CET. */
-        mov     $XEN_MINIMAL_CR4 | X86_CR4_CET, %ecx
+        mov     $X86_CR4_CET, %ecx
+        or      STACK_CPUINFO_FIELD(cr4)(%r15), %rcx
+        mov     %rcx, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rcx, %cr4
 
         /* WARNING! call/ret now fatal (iff SHSTK) until SETSSBSY loads SSP */
@@ -120,9 +130,9 @@ LABEL(s3_resume)
 .L_cet_done:
 #endif /* CONFIG_XEN_SHSTK || CONFIG_XEN_IBT */
 
-        /* Restore CR4 from the cpuinfo block. */
-        GET_STACK_END(bx)
-        mov     STACK_CPUINFO_FIELD(cr4)(%rbx), %rax
+        /* Load all CR4 settings. */
+        mov     mmu_cr4_features(%rip), %rax
+        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rax, %cr4
 
         call    mtrr_bp_restore
diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index d0e7449a149f..3a5ad2764448 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -11,16 +11,19 @@ ENTRY(__high_start)
         mov     %ecx,%gs
         mov     %ecx,%ss
 
-        /* Enable minimal CR4 features. */
-        mov     $XEN_MINIMAL_CR4,%rcx
-        mov     %rcx,%cr4
-
         mov     stack_start(%rip),%rsp
 
         /* Reset EFLAGS (subsumes CLI and CLD). */
         pushq   $0
         popf
 
+        GET_STACK_END(15)
+
+        /* Enable minimal CR4 features, sync cached state. */
+        mov     $XEN_MINIMAL_CR4, %eax
+        mov     %rax, STACK_CPUINFO_FIELD(cr4)(%r15)
+        mov     %rax, %cr4
+
         /* Reload code selector. */
         pushq   $__HYPERVISOR_CS
         leaq    1f(%rip),%rax
@@ -45,7 +48,9 @@ ENTRY(__high_start)
         wrmsr
 
         /* Enable CR4.CET. */
-        mov     $XEN_MINIMAL_CR4 | X86_CR4_CET, %ecx
+        mov     $X86_CR4_CET, %ecx
+        or      STACK_CPUINFO_FIELD(cr4)(%r15), %rcx
+        mov     %rcx, STACK_CPUINFO_FIELD(cr4)(%r15)
         mov     %rcx, %cr4
 
         /* WARNING! call/ret now fatal (iff SHSTK) until SETSSBSY loads SSP */
-- 
2.39.5



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Date: Thu, 28 Aug 2025 12:17:30 -0300
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	Alexander Potapenko ,
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On Tue, Aug 19, 2025 at 08:36:53PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> Extend base DMA page API to handle MMIO flow and follow
> existing dma_map_resource() implementation to rely on dma_map_direct()
> only to take DMA direct path.

I would reword this a little bit too

dma-mapping: implement DMA_ATTR_MMIO for dma_(un)map_page_attrs()

Make dma_map_page_attrs() and dma_map_page_attrs() respect
DMA_ATTR_MMIO.

DMA_ATR_MMIO makes the functions behave the same as dma_(un)map_resource():
 - No swiotlb is possible
 - Legacy dma_ops arches use ops->map_resource()
 - No kmsan
 - No arch_dma_map_phys_direct()

The prior patches have made the internl funtions called here support
DMA_ATTR_MMIO.

This is also preparation for turning dma_map_resource() into an inline
calling dma_map_phys(DMA_ATTR_MMIO) to consolidate the flows.

> @@ -166,14 +167,25 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
>  		return DMA_MAPPING_ERROR;
>  
>  	if (dma_map_direct(dev, ops) ||
> -	    arch_dma_map_phys_direct(dev, phys + size))
> +	    (!is_mmio && arch_dma_map_phys_direct(dev, phys + size)))
>  		addr = dma_direct_map_phys(dev, phys, size, dir, attrs);

PPC is the only user of arch_dma_map_phys_direct() and it looks like
it should be called on MMIO memory. Seems like another inconsistency
with map_resource. I'd leave it like the above though for this series.

>  	else if (use_dma_iommu(dev))
>  		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
> -	else
> +	else if (is_mmio) {
> +		if (!ops->map_resource)
> +			return DMA_MAPPING_ERROR;

Probably written like:

		if (ops->map_resource)
			addr = ops->map_resource(dev, phys, size, dir, attrs);
		else
			addr = DMA_MAPPING_ERROR;

As I think some of the design here is to run the trace even on the
failure path?

Otherwise looks OK

Reviewed-by: Jason Gunthorpe 

Jason


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Date: Thu, 28 Aug 2025 12:18:06 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 10/16] xen: swiotlb: Open code map_resource callback
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On Tue, Aug 19, 2025 at 08:36:54PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky 
> 
> General dma_direct_map_resource() is going to be removed
> in next patch, so simply open-code it in xen driver.
> 
> Reviewed-by: Juergen Gross 
> Signed-off-by: Leon Romanovsky 
> ---
>  drivers/xen/swiotlb-xen.c | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)

Reviewed-by: Jason Gunthorpe 

Jason


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Subject: Re: [PATCH v2 02/23] x86/traps: Extend struct cpu_user_regs/cpu_info
 with FRED fields
To: Andrew Cooper 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Xen-devel 
References: <20250828150409.901315-1-andrew.cooper3@citrix.com>
 <20250828150409.901315-3-andrew.cooper3@citrix.com>
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On 28.08.2025 17:03, Andrew Cooper wrote:
> The FRED on-stack format is larger than the IDT format, but is by and large
> compatible.  FRED reuses space above cs and ss for extra metadata, some of
> which is purely informational, and some of which causes additional effects in
> ERET{U,S}.
> 
> Follow Linux's choice of naming for fred_{c,s}s structures, to make it very
> clear at the point of use that it's dependent on FRED.
> 
> There is also the event data field and reserved fields, but we cannot include
> these in struct cpu_user_regs without reintroducing OoB structure accesses in
> the non-FRED case.  See commit 6065a05adf15 ("x86/traps: 'Fix' safety of
> read_registers() in #DF path"). for more details.
> 
> Instead, use a new struct fred_info and position it suitably in struct
> cpu_info.  This boundary will be loaded into MSR_FRED_RSP_SL0, and must be
> 64-byte aligned.
> 
> This does add 16 bytes back into struct cpu_info, undoing the saving we made
> by dropping the vm86 data segment selectors.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 



From xen-devel-bounces@lists.xenproject.org Thu Aug 28 15:19:37 2025
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Date: Thu, 28 Aug 2025 09:19:20 -0600
From: Keith Busch 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
Message-ID: 
References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
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On Tue, Aug 19, 2025 at 08:36:59PM +0300, Leon Romanovsky wrote:
> diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
> index 09b99d52fd36..283058bcb5b1 100644
> --- a/include/linux/blk_types.h
> +++ b/include/linux/blk_types.h
> @@ -387,6 +387,7 @@ enum req_flag_bits {
>  	__REQ_FS_PRIVATE,	/* for file system (submitter) use */
>  	__REQ_ATOMIC,		/* for atomic write operations */
>  	__REQ_P2PDMA,		/* contains P2P DMA pages */
> +	__REQ_MMIO,		/* contains MMIO memory */
>  	/*
>  	 * Command specific flags, keep last:
>  	 */
> @@ -420,6 +421,7 @@ enum req_flag_bits {
>  #define REQ_FS_PRIVATE	(__force blk_opf_t)(1ULL << __REQ_FS_PRIVATE)
>  #define REQ_ATOMIC	(__force blk_opf_t)(1ULL << __REQ_ATOMIC)
>  #define REQ_P2PDMA	(__force blk_opf_t)(1ULL << __REQ_P2PDMA)
> +#define REQ_MMIO	(__force blk_opf_t)(1ULL << __REQ_MMIO)

Now that my integrity metadata DMA series is staged, I don't think we
can use REQ flags like this because data and metadata may have different
mapping types. I think we should add a flags field to the dma_iova_state
instead.


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On 28.08.2025 17:03, Andrew Cooper wrote:
> ... disabled by default.  There is a lot of work before FRED can be enabled by
> default.
> 
> One part of FRED, the LKGS (Load Kernel GS) instruction, is enumerated
> separately but is mandatory as FRED disallows the SWAPGS instruction.
> Normally, we'd have to check both CPUID bits, but Xen does not use GS like
> most other software, and can manage without the LKGS instruction.
> 
> FRED formally removes the use of Ring1 and Ring2, meaning we cannot run 32bit
> PV guests.  Therefore, don't enable FRED by default in shim mode.  OTOH, if
> FRED is active, then PV32 needs disabling like with CET.
> 
> No functional change.
> 
> Signed-off-by: Andrew Cooper 

Reviewed-by: Jan Beulich 



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On 8/28/25 05:39, Dmytro Prokopchuk1 wrote:
> Fix an issue in the 'fail:' cleanup path of the 'assign_shared_memory()'
> function where the use of an unsigned long 'i' with the condition
> '--i >= 0' caused an infinite loop.

I'm not requesting any changes to this patch, but as a separate discussion this
could have been caught with -Wtype-limits:

arch/arm/static-shmem.c: In function ‘assign_shared_memory’:
arch/arm/static-shmem.c:188:17: warning: comparison of unsigned expression in ‘>= 0’ is always true [-Wtype-limits]
  188 |     while ( --i >= 0 )
      |                 ^~

It might be nice to add this warning flag into the build by default, but there
may be other issues that would need to be addressed first. Having the flag at
least for the release build would be nice, since the debug build may (or may
not) have justifiable occurrences inside of ASSERTs. Again, I don't mean to
increase the scope of work, I'm just making an observation.

If you're curious try it out, add this to your make command:
EXTRA_CFLAGS_XEN_CORE="-Wtype-limits -Wno-error=type-limits"


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Date: Thu, 28 Aug 2025 16:33:39 +0100
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Subject: Re: [PATCH v2 01/23] x86: FRED enumerations
To: Xen-devel 
Cc: Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 
References: <20250828150409.901315-1-andrew.cooper3@citrix.com>
 <20250828150409.901315-2-andrew.cooper3@citrix.com>
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From: Andrew Cooper 
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In-Reply-To: <20250828150409.901315-2-andrew.cooper3@citrix.com>
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On 28/08/2025 4:03 pm, Andrew Cooper wrote:
> Of note, CR4.FRED is bit 32 and cannot enabled outside of 64bit mode.
>
> Most supported toolchains don't understand the FRED instructions yet.  ERETU
> and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC), while LKGS is
> more complicated and deferred for now.

I've realised this is stale now.  I'll replace with:

Most supported toolchains don't understand the FRED instructions yet. 
ERETU and ERETS are easy to wrap (they encoded as REPZ/REPNE CLAC),
while Xen turns out to have no need for LKGS.

>
> I have intentionally named the FRED MSRs differently to the spec.  In the
> spec, the stack pointer names alias the TSS fields of the same name, despite
> very different semantics.
>
> Signed-off-by: Andrew Cooper 
> Acked-by: Jan Beulich 
> ---
> CC: Jan Beulich 
> CC: Roger Pau Monné 
>
> v2:
>  * Drop CONFIG_HAS_AS_FRED

I should have also noted "Add X86_FEATURE_XEN_FRED" here.

~Andrew


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From: Xen.org security team 
CC: Xen.org security team 
Subject: Xen Security Advisory 471 v2 (CVE-2024-36350,CVE-2024-36357) -
 x86: Transitive Scheduler Attacks
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Date: Thu, 28 Aug 2025 15:36:38 +0000

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-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256

    Xen Security Advisory CVE-2024-36350,CVE-2024-36357 / XSA-471
                              version 2

                   x86: Transitive Scheduler Attacks

UPDATES IN VERSION 2
====================

The fix for this issue uncovered a pre-existing bug with the handling of
timers and broke S3 suspend on certain systems.  The following patch in
xen.git#master resolves the issue:

757abedabbb6 x86/suspend: unconditionally raise a timer softirq on resume

ISSUE DESCRIPTION
=================

Researchers from Microsoft and ETH Zurich have discovered several new
speculative sidechannel attacks which bypass current protections.  They
are detailed in a paper titled "Enter, Exit, Page Fault, Leak: Testing
Isolation Boundaries for Microarchitectural Leaks".

Two issues, which AMD have named Transitive Scheduler Attacks, utilise
timing information from instruction execution.  These are:

  * CVE-2024-36350: TSA-SQ (TSA in the Store Queues)
  * CVE-2024-36357: TSA-L1 (TSA in the L1 data cache)

For more information, see:
  https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf
  https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7029.html
  https://aka.ms/enter-exit-leak

The paper also details other speculative attacks.  See below.

IMPACT
======

An attacker might be able to infer data belonging to other contexts,
including data belonging to other guests.

VULNERABLE SYSTEMS
==================

Systems running all versions of Xen are affected.

Only AMD Fam19h CPUs (Zen3/4 microarchitectures) are believed to be
vulnerable.  Other AMD CPUs, and CPUs from other manufacturers are not
known to be affected.

MITIGATION
==========

There are no mitigations.

RESOLUTION
==========

AMD are producing microcode to address TSA, which adds scrubbing side
effects to the VERW instruction.  This was included in the firmware
fixes for the Entrysign signature vulnerability from ~December 2024, but
are also available in an OS-loadable form on older firmware.  Consult
your dom0 OS vendor and/or hardware vendor for updated microcode.

In addition to the microcode, changes are required to Xen to make use of
VERW scrubbing at suitable points.

Applying the appropriate set of attached patches resolves this issue.

Note that patches for released versions are generally prepared to
apply to the stable branches, and may not apply cleanly to the most
recent release tarball.  Downstreams are encouraged to update to the
tip of the stable branch before applying these patches.

xsa471/xsa471-??.patch           xen-unstable
xsa471/xsa471-4.20-??.patch      Xen 4.20.x
xsa471/xsa471-4.19-??.patch      Xen 4.19.x
xsa471/xsa471-4.18-??.patch      Xen 4.18.x
xsa471/xsa471-4.17-??.patch      Xen 4.17.x

$ sha256sum xsa471*/*
4cc8b54d3cae4864053c4d608061675564cc322c6cd362e33ac59ac4c9371358  xsa471/xsa471-01.patch
9bdfd0ad8d34114e69bb0e264ffdcb176e54211753cc1eed247e73cd3fe752e9  xsa471/xsa471-02.patch
62706c1593cb64bfd053f5ee2e8fa26f5414835c6ef5f694c52a61e18017aa1d  xsa471/xsa471-03.patch
e06162c55de0b3ca79302ea47c8169079b0f2cd65a48d3e0509677452c9887da  xsa471/xsa471-4.17-01.patch
742c59d776c73993c44e72ceada2b83b61fa77a988f5c2c593b6594b4f4078de  xsa471/xsa471-4.17-02.patch
a8ed5e90e405273115d6a06199de3190319ba12aac33bea17495db42b6a9becc  xsa471/xsa471-4.17-03.patch
855c9528d93109a1a673dd8f4feb87a688457908c9dd821d0e1a3326efb19257  xsa471/xsa471-4.17-04.patch
f8dbe5c8dbdf921c7f9b4bc7d8234b9bb291df6a4a8cef604284bf4f36947d4e  xsa471/xsa471-4.17-05.patch
fa2682955663e0966cf285bf79770fe76b387fbf449e1ac64206a6ae4bf79bc4  xsa471/xsa471-4.17-06.patch
dc4695aced6ba65e8b16088aefe817e8e4d965cd94e9e3340bd48d77c1369902  xsa471/xsa471-4.17-07.patch
0393a8711805f40eeb936dcca56f5bea174ff94098ffaee7064cd6801eb55099  xsa471/xsa471-4.17-08.patch
346493cc12d9a0fa4154968bc0c8dca9d87e583a25ae9ecd22b8ae2c7bdeae19  xsa471/xsa471-4.17-09.patch
0d652e9a6bb89782036b39160f2db9c1fd1dfc0e659fb4e351f04eb66ffbdba8  xsa471/xsa471-4.17-10.patch
ff3ae74f6cfccfaee55f007b2410813068928d20a23729ae2766ddcc65d2e82b  xsa471/xsa471-4.17-11.patch
5c6d133f626fdcbc148b596bf3cee1c46260d73fd833aeb6c59cf7c1b315f2b8  xsa471/xsa471-4.17-12.patch
acbdca53d713122545ba210a795c4185e842d4cca71802775adc1a4ce971bf3a  xsa471/xsa471-4.17-13.patch
4a7fa23b7f501cb88100b55fab13b7315a01fc1e4a3eff46b5d0c867fcc03ca8  xsa471/xsa471-4.17-14.patch
164d626a2f446ad7692bd70ab7e109f8b6259aaea34bfb9f51df68def98a2e62  xsa471/xsa471-4.17-15.patch
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$

NOTE CONCERNING OTHER SPECULATIVE ATTACKS
=========================================

The paper describes two further attack:

 * CVE-2024-36348: Rogue execution of SMSW
 * CVE-2045-36349: Rogue read of MSR_TSC_AUX

which are both examples of Rogue System Register Read (sometimes called
Spectre-v3a).  No fix is planned, because these registers do not
typically contain sensitive information.
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From: Dmytro Prokopchuk1 
To: Nicola Vetrini , Jan Beulich
	, Stefano Stabellini 
CC: Doug Goldstein , Andrew Cooper
	, Anthony PERARD ,
	Michal Orzel , Julien Grall ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= ,
	"xen-devel@lists.xenproject.org" 
Subject: Re: [PATCH] misra: consider conversion from UL or (void*) to function
 pointer as safe
Thread-Topic: [PATCH] misra: consider conversion from UL or (void*) to
 function pointer as safe
Thread-Index:
 AQHcETrg9Y9S2hDXvUqVfYmm522krbRswSIAgAAGvACAAhrPAIAEeW2AgAAEDACABOVWAA==
Date: Thu, 28 Aug 2025 15:54:03 +0000
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 <9e5e4ff2c7ba0a90a6ac403e2de9318e18949274.1755628705.git.dmytro_prokopchuk1@epam.com>
 <90fb95a3-4b32-4785-a77c-373e5b9da6ed@suse.com>
 
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Date: Thu, 28 Aug 2025 13:01:10 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Leon Romanovsky ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 11/16] dma-mapping: export new dma_*map_phys()
 interface
Message-ID: <20250828160110.GJ9469@nvidia.com>
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On Tue, Aug 19, 2025 at 08:36:55PM +0300, Leon Romanovsky wrote:
> The old page-based API is preserved in mapping.c to ensure that existing
> code won't be affected by changing EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
> variant for dma_*map_phys().
> 
> Signed-off-by: Leon Romanovsky 
> ---
>  drivers/iommu/dma-iommu.c   | 14 --------
>  include/linux/dma-direct.h  |  2 --
>  include/linux/dma-mapping.h | 13 +++++++
>  include/linux/iommu-dma.h   |  4 ---
>  include/trace/events/dma.h  |  2 --
>  kernel/dma/debug.c          | 43 -----------------------
>  kernel/dma/debug.h          | 21 -----------
>  kernel/dma/direct.c         | 16 ---------
>  kernel/dma/mapping.c        | 69 ++++++++++++++++++++-----------------
>  9 files changed, 50 insertions(+), 134 deletions(-)

Reviewed-by: Jason Gunthorpe 

Jason


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Subject: Re: [PATCH v2 3/5] symbols: arrange to know where functions end
From: Jan Beulich 
To: Jason Andryuk 
Cc: Andrew Cooper , Julien Grall ,
 Stefano Stabellini ,
 Anthony PERARD ,
 Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
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On 28.08.2025 09:28, Jan Beulich wrote:
> On 28.08.2025 03:03, Jason Andryuk wrote:
>> On 2025-04-02 09:58, Jan Beulich wrote:
>>> --- a/xen/tools/symbols.c
>>> +++ b/xen/tools/symbols.c
>>
>>> @@ -318,24 +334,42 @@ static void write_src(void)
>>>   	printf("#else\n");
>>>   	output_label("symbols_offsets");
>>>   	printf("#endif\n");
>>> -	for (i = 0; i < table_cnt; i++) {
>>> +	for (i = 0, ends = 0; i < table_cnt; i++) {
>>>   		printf("\tPTR\t%#llx - SYMBOLS_ORIGIN\n", table[i].addr);
>>> +
>>> +		table[i].addr_idx = i + ends;
>>> +
>>> +		if (!want_symbol_end(i)) {
>>> +			/* If there's another symbol at the same address,
>>> +			 * propagate this symbol's size if the next one has
>>> +			 * no size, or if the next one's size is larger. */
>>
>> Why do we want to shrink the next symbol's size?
> 
> First (see related post-commit-message remarks): In principle section symbols
> could come with a size, too. That would break everything as long as we don't
> strip those.
> 
> The main reason though is that imo smallest granularity is what we want here,
> together with predictability. One symbol with a huge size could cover
> multiple other symbols with smaller sizes. We could omit that part of the
> change here, but then the processing in the hypervisor would need to change,
> to fish out the "best suitable" symbol when dealing with multiple ones at the
> same address. Other changes may then also be needed to the tool, to have such
> symbols come in a well-defined order (to keep the then-new code in the
> hypervisor as simple as possible). Look for "aliased symbol" in
> common/symbols.c to see how simplistic respective code is right now.

Furthermore remember that we can't record sizes, but instead we insert fake
symbols. Obviously there can be only one (at least in the present scheme).
If we used too large a size, chances would increase that the end symbol (in
the sorted table) would have to live past some other symbol, thus becoming
that one's "end".

Jan


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CC: "olekstysh@gmail.com" , Stefano Stabellini
	, Bertrand Marquis , Michal
 Orzel , Volodymyr Babchuk 
Subject: Re: [PATCH v4 01/12] xen/arm: gicv3: refactor obtaining GIC addresses
 for common operations
Thread-Topic: [PATCH v4 01/12] xen/arm: gicv3: refactor obtaining GIC
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From: Leonid Komarianskyi 
To: Julien Grall , "xen-devel@lists.xenproject.org"
	
CC: "olekstysh@gmail.com" , Stefano Stabellini
	, Bertrand Marquis , Michal
 Orzel , Volodymyr Babchuk 
Subject: Re: [PATCH v4 02/12] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Topic: [PATCH v4 02/12] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Index: AQHcF3/Ff+oSmGvjakq9bpLMhjgPlLR3+pEAgABF3AA=
Date: Thu, 28 Aug 2025 16:20:49 +0000
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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v4 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Topic: [PATCH v4 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcF3/KB15KvpnNkEu7nU8vywEQ/bR4HX4AgAAkZIA=
Date: Thu, 28 Aug 2025 16:26:01 +0000
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From: Volodymyr Babchuk 
To: Mykola Kvach 
CC: "xen-devel@lists.xenproject.org" , Mykola
 Kvach , Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Andrew Cooper
	, Anthony PERARD , Jan
 Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Shawn Anastasio ,
	Alistair Francis , Bob Eshleman
	, Connor Davis , Oleksii
 Kurochko 
Subject: Re: [PATCH v11 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
Thread-Topic: [PATCH v11 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
Thread-Index: AQHcGCumBGr3lAlNMUmhrYm2OcIjvw==
Date: Thu, 28 Aug 2025 16:32:31 +0000
Message-ID: <87ecsvz9sx.fsf@epam.com>
References: 
	
In-Reply-To:
 
	(Mykola Kvach's message of "Thu, 28 Aug 2025 17:54:04 +0300")
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Hi Mykola,

Mykola Kvach  writes:

> From: Mykola Kvach 
>
> Add support for the PSCI SYSTEM_SUSPEND function in the vPSCI interface,
> allowing guests to request suspend via the PSCI v1.0 SYSTEM_SUSPEND call
> (both 32-bit and 64-bit variants).
>
> Implementation details:
> - Add SYSTEM_SUSPEND function IDs to PSCI definitions
> - Trap and handle SYSTEM_SUSPEND in vPSCI
> - Allow only non-hardware domains to invoke SYSTEM_SUSPEND; return
>   PSCI_NOT_SUPPORTED for the hardware domain to avoid halting the system
>   in hwdom_shutdown() via domain_shutdown
> - Require all secondary VCPUs of the calling domain to be offline before
>   suspend, as mandated by the PSCI specification
>
> The arch_domain_resume() function is an architecture-specific hook that i=
s
> invoked during domain resume to perform any necessary setup or restoratio=
n
> steps required by the platform.
>
> The new vpsci_vcpu_up_prepare() helper is called on the resume path to se=
t up
> the vCPU context (such as entry point, some system regs and context ID) b=
efore
> resuming a suspended guest. This keeps ARM/vPSCI-specific logic out of co=
mmon
> code and avoids intrusive changes to the generic resume flow.
>
> Usage:
>
> For Linux-based guests, suspend can be initiated with:
>     echo mem > /sys/power/state
> or via:
>     systemctl suspend
>
> Resuming the guest is performed from control domain using:
>       xl resume 
>
> Signed-off-by: Mykola Kvach 

Reviewed-by: Volodymyr Babchuk 

But check a small comment below

> ---
> Changes in V11:
> - introduce arch_domain_resume() and vpsci_vcpu_up_prepare(), which are n=
ow
> called on the resume path to avoid extra modifications to common code.
> The vCPU context is now updated during domain resume.
>
> Changes in V10:
> - small changes to the commit message reflect updates introduced in this
>   version of the patch.
> - Comments are improved, clarified, and expanded, especially regarding PS=
CI
>   requirements and context handling.
> - An ARM-specific helper (domain_resume_nopause_helper)
> - gprintk() and PRIregister are used for logging in vPSCI code.
> - An isb() is added before p2m_save_state
> - The is_64bit_domain check is dropped when masking the upper part of ent=
ry
>   point and cid for SMC32 SYSTEM_SUSPEND PSCI calls
>
> Changes in V9:
> - no functional changes
> - cosmetic chnages after review
> - enhance commit message and add extra comment to the code after review
>
> Changes in V8:
> - GIC and virtual timer context must be saved when the domain suspends
> - rework locking
> - minor changes after code review
>
> Changes in V7:
> - add proper locking
> - minor changes after code review
>
> Changes in V6:
> - skip execution of ctxt_switch_from for vcpu that is in paused domain
> - add implementation of domain_resume without domain_pause
> - add helper function to determine if vcpu is suspended or not
> - ignore upper 32 bits of argument values when the domain is 64-bit
>   and calls the SMC32 SYSTEM_SUSPEND function
> - cosmetic changes after review
>
> Changes in V5:
> - don't use standby mode, restore execution in a provided by guest point
> - move checking that all CPUs, except current one, are offline to after
>   pausing the vCPUs
> - provide ret status from arch_domain_shutdown and handle it in
>   domain_shutdown
> - adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI functio=
ns
>
> Changes in V4:
> Dropped all changes related to watchdog, domain is marked as shutting
> down in domain_shutdown and watchdog timeout handler won't trigger
> because of it.
>
> Previous versions included code to manage Xen watchdog timers during susp=
end,
> but this was removed. When a guest OS starts the Xen watchdog (either via=
 the
> kernel driver or xenwatchdogd), it is responsible for managing that state
> across suspend/resume. On Linux, the Xen kernel driver properly stops the
> watchdog during suspend. However, when xenwatchdogd is used instead, susp=
end
> handling is incomplete, potentially leading to watchdog-triggered resets =
on
> resume. Xen leaves watchdog handling to the guest OS and its services.
>
> Dropped all changes related to VCPU context, because instead domain_shutd=
own
> is used, so we don't need any extra changes for suspending domain.
>
> Changes in V3:
> Dropped all domain flags and related code (which touched common functions=
 like
> vcpu_unblock), keeping only the necessary changes for Xen suspend/resume,=
 i.e.
> suspend/resume is now fully supported only for the hardware domain.
> Proper support for domU suspend/resume will be added in a future patch.
> This patch does not yet include VCPU context reset or domain context
> restoration in VCPU.
> ---
>  xen/arch/arm/domain.c                 |  22 +++++
>  xen/arch/arm/include/asm/domain.h     |   6 ++
>  xen/arch/arm/include/asm/perfc_defn.h |   1 +
>  xen/arch/arm/include/asm/psci.h       |   2 +
>  xen/arch/arm/include/asm/vpsci.h      |   5 +-
>  xen/arch/arm/vpsci.c                  | 114 +++++++++++++++++++++-----
>  xen/arch/ppc/stubs.c                  |   5 ++
>  xen/arch/riscv/stubs.c                |   5 ++
>  xen/arch/x86/domain.c                 |   5 ++
>  xen/common/domain.c                   |   9 ++
>  xen/include/xen/domain.h              |   2 +
>  11 files changed, 156 insertions(+), 20 deletions(-)
>
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index 863ae18157..6fd73eedde 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -12,6 +12,8 @@
>  #include 
>  #include 
> =20
> +#include 
> +
>  #include 
>  #include 
>  #include 
> @@ -27,6 +29,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
> =20
>  #include "vpci.h"
> @@ -880,6 +883,25 @@ void arch_domain_creation_finished(struct domain *d)
>      p2m_domain_creation_finished(d);
>  }
> =20
> +int arch_domain_resume(struct domain *d)
> +{
> +    int rc;
> +    typeof(d->arch.resume_ctx) *ctx =3D &d->arch.resume_ctx;
> +
> +    if ( !d->is_shutting_down || d->shutdown_code !=3D SHUTDOWN_suspend =
)
> +    {
> +        dprintk(XENLOG_WARNING,
> +                "%pd: Invalid domain state for resume: is_shutting_down=
=3D%d, shutdown_code=3D%d\n",
> +                d, d->is_shutting_down, d->shutdown_code);
> +        return -EINVAL;
> +    }

This check probably can go into common domain_resume() function, as
there is nothing arch-specific in here. Probably this can be done during
commit, to save us from v12? If commiters are okay with this.

> +
> +    rc =3D vpsci_vcpu_up_prepare(ctx->wake_cpu , ctx->ep, ctx->cid);
> +    memset(ctx, 0, sizeof(*ctx));
> +
> +    return rc;
> +}
> +
>  static int is_guest_pv32_psr(uint32_t psr)
>  {
>      switch (psr & PSR_MODE_MASK)
> diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm=
/domain.h
> index a3487ca713..68185fc4d6 100644
> --- a/xen/arch/arm/include/asm/domain.h
> +++ b/xen/arch/arm/include/asm/domain.h
> @@ -121,6 +121,12 @@ struct arch_domain
>      void *tee;
>  #endif
> =20
> +    struct resume_info {
> +        register_t ep;
> +        register_t cid;
> +        struct vcpu *wake_cpu;
> +    } resume_ctx;
> +
>  }  __cacheline_aligned;
> =20
>  struct arch_vcpu
> diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/include=
/asm/perfc_defn.h
> index effd25b69e..8dfcac7e3b 100644
> --- a/xen/arch/arm/include/asm/perfc_defn.h
> +++ b/xen/arch/arm/include/asm/perfc_defn.h
> @@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system_r=
eset")
>  PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
>  PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
>  PERFCOUNTER(vpsci_features,            "vpsci: features")
> +PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
> =20
>  PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
> =20
> diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/p=
sci.h
> index 4780972621..48a93e6b79 100644
> --- a/xen/arch/arm/include/asm/psci.h
> +++ b/xen/arch/arm/include/asm/psci.h
> @@ -47,10 +47,12 @@ void call_psci_system_reset(void);
>  #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
>  #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
>  #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
> +#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
> =20
>  #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
>  #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
>  #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
> +#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
> =20
>  /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
>  #define PSCI_0_2_AFFINITY_LEVEL_ON      0
> diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/asm/=
vpsci.h
> index 0cca5e6830..d790ab3715 100644
> --- a/xen/arch/arm/include/asm/vpsci.h
> +++ b/xen/arch/arm/include/asm/vpsci.h
> @@ -23,12 +23,15 @@
>  #include 
> =20
>  /* Number of function implemented by virtual PSCI (only 0.2 or later) */
> -#define VPSCI_NR_FUNCS  12
> +#define VPSCI_NR_FUNCS  14
> =20
>  /* Functions handle PSCI calls from the guests */
>  bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
>  bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid);
> =20
> +int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
> +                          register_t context_id);
> +
>  #endif /* __ASM_VPSCI_H__ */
> =20
>  /*
> diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
> index 7ba9ccd94b..50cf5fd96c 100644
> --- a/xen/arch/arm/vpsci.c
> +++ b/xen/arch/arm/vpsci.c
> @@ -10,30 +10,16 @@
> =20
>  #include 
> =20
> -static int do_common_cpu_on(register_t target_cpu, register_t entry_poin=
t,
> -                            register_t context_id)
> +int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
> +                   register_t context_id)
>  {
> -    struct vcpu *v;
> -    struct domain *d =3D current->domain;
> -    struct vcpu_guest_context *ctxt;
>      int rc;
> +    struct domain *d =3D current->domain;
>      bool is_thumb =3D entry_point & 1;
> -    register_t vcpuid;
> -
> -    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> -
> -    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> -        return PSCI_INVALID_PARAMETERS;
> -
> -    /* THUMB set is not allowed with 64-bit domain */
> -    if ( is_64bit_domain(d) && is_thumb )
> -        return PSCI_INVALID_ADDRESS;
> -
> -    if ( !test_bit(_VPF_down, &v->pause_flags) )
> -        return PSCI_ALREADY_ON;
> +    struct vcpu_guest_context *ctxt;
> =20
>      if ( (ctxt =3D alloc_vcpu_guest_context()) =3D=3D NULL )
> -        return PSCI_DENIED;
> +        return -ENOMEM;
> =20
>      vgic_clear_pending_irqs(v);
> =20
> @@ -76,8 +62,37 @@ static int do_common_cpu_on(register_t target_cpu, reg=
ister_t entry_point,
>      free_vcpu_guest_context(ctxt);
> =20
>      if ( rc < 0 )
> +        return rc;
> +
> +    return 0;
> +}
> +
> +static int do_common_cpu_on(register_t target_cpu, register_t entry_poin=
t,
> +                            register_t context_id)
> +{
> +    struct vcpu *v;
> +    struct domain *d =3D current->domain;
> +    int rc;
> +    bool is_thumb =3D entry_point & 1;
> +    register_t vcpuid;
> +
> +    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> +
> +    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> +        return PSCI_INVALID_PARAMETERS;
> +
> +    /* THUMB set is not allowed with 64-bit domain */
> +    if ( is_64bit_domain(d) && is_thumb )
> +        return PSCI_INVALID_ADDRESS;
> +
> +    if ( !test_bit(_VPF_down, &v->pause_flags) )
> +        return PSCI_ALREADY_ON;
> +
> +    rc =3D vpsci_vcpu_up_prepare(v, entry_point, context_id);
> +    if ( rc )
>          return PSCI_DENIED;
> =20
> +    vgic_clear_pending_irqs(v);
>      vcpu_wake(v);
> =20
>      return PSCI_SUCCESS;
> @@ -197,6 +212,48 @@ static void do_psci_0_2_system_reset(void)
>      domain_shutdown(d,SHUTDOWN_reboot);
>  }
> =20
> +static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t =
cid)
> +{
> +    int32_t rc;
> +    struct vcpu *v;
> +    struct domain *d =3D current->domain;
> +    bool is_thumb =3D epoint & 1;
> +
> +    /* THUMB set is not allowed with 64-bit domain */
> +    if ( is_64bit_domain(d) && is_thumb )
> +        return PSCI_INVALID_ADDRESS;
> +
> +    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> +    if ( is_hardware_domain(d) )
> +        return PSCI_NOT_SUPPORTED;
> +
> +    /* Ensure that all CPUs other than the calling one are offline */
> +    domain_lock(d);
> +    for_each_vcpu ( d, v )
> +    {
> +        if ( v !=3D current && is_vcpu_online(v) )
> +        {
> +            domain_unlock(d);
> +            return PSCI_DENIED;
> +        }
> +    }
> +    domain_unlock(d);
> +
> +    rc =3D domain_shutdown(d, SHUTDOWN_suspend);
> +    if ( rc )
> +        return PSCI_DENIED;
> +
> +    d->arch.resume_ctx.ep =3D epoint;
> +    d->arch.resume_ctx.cid =3D cid;
> +    d->arch.resume_ctx.wake_cpu =3D current;
> +
> +    gprintk(XENLOG_DEBUG,
> +            "SYSTEM_SUSPEND requested, epoint=3D0x%"PRIregister", cid=3D=
0x%"PRIregister,
> +            epoint, cid);
> +
> +    return rc;
> +}
> +
>  static int32_t do_psci_1_0_features(uint32_t psci_func_id)
>  {
>      /* /!\ Ordered by function ID and not name */
> @@ -214,6 +271,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_fun=
c_id)
>      case PSCI_0_2_FN32_SYSTEM_OFF:
>      case PSCI_0_2_FN32_SYSTEM_RESET:
>      case PSCI_1_0_FN32_PSCI_FEATURES:
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
>      case ARM_SMCCC_VERSION_FID:
>          return 0;
>      default:
> @@ -344,6 +403,23 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, u=
int32_t fid)
>          return true;
>      }
> =20
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> +    {
> +        register_t epoint =3D PSCI_ARG(regs, 1);
> +        register_t cid =3D PSCI_ARG(regs, 2);
> +
> +        if ( fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND )
> +        {
> +            epoint &=3D GENMASK(31, 0);
> +            cid &=3D GENMASK(31, 0);
> +        }
> +
> +        perfc_incr(vpsci_system_suspend);
> +        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
> +        return true;
> +    }
> +
>      default:
>          return false;
>      }
> diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c
> index bdaf474c5c..0db0627b5c 100644
> --- a/xen/arch/ppc/stubs.c
> +++ b/xen/arch/ppc/stubs.c
> @@ -224,6 +224,11 @@ void arch_domain_creation_finished(struct domain *d)
>      BUG_ON("unimplemented");
>  }
> =20
> +int arch_domain_resume(struct domain *d)
> +{
> +    return 0;
> +}
> +
>  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
>  {
>      BUG_ON("unimplemented");
> diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c
> index 1a8c86cd8d..52532ae14d 100644
> --- a/xen/arch/riscv/stubs.c
> +++ b/xen/arch/riscv/stubs.c
> @@ -198,6 +198,11 @@ void arch_domain_creation_finished(struct domain *d)
>      BUG_ON("unimplemented");
>  }
> =20
> +int arch_domain_resume(struct domain *d)
> +{
> +    return 0;
> +}
> +
>  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
>  {
>      BUG_ON("unimplemented");
> diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
> index 19fd86ce88..94a06bc697 100644
> --- a/xen/arch/x86/domain.c
> +++ b/xen/arch/x86/domain.c
> @@ -1138,6 +1138,11 @@ void arch_domain_creation_finished(struct domain *=
d)
>          hvm_domain_creation_finished(d);
>  }
> =20
> +int arch_domain_resume(struct domain *d)
> +{
> +    return 0;
> +}
> +
>  #ifdef CONFIG_COMPAT
>  #define xen_vcpu_guest_context vcpu_guest_context
>  #define fpu_ctxt fpu_ctxt.x
> diff --git a/xen/common/domain.c b/xen/common/domain.c
> index 104e917f07..d73a88ced5 100644
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -1352,6 +1352,7 @@ int domain_shutdown(struct domain *d, u8 reason)
>  void domain_resume(struct domain *d)
>  {
>      struct vcpu *v;
> +    int rc;
> =20
>      /*
>       * Some code paths assume that shutdown status does not get reset un=
der
> @@ -1359,6 +1360,14 @@ void domain_resume(struct domain *d)
>       */
>      domain_pause(d);
> =20
> +    rc =3D arch_domain_resume(d);
> +    if ( rc )
> +    {
> +        domain_unpause(d);
> +        printk("%pd: Failed to resume domain (ret %d)\n", d, rc);
> +        return;
> +    }
> +
>      spin_lock(&d->shutdown_lock);
> =20
>      d->is_shutting_down =3D d->is_shut_down =3D 0;
> diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
> index e10baf2615..5f77ffadf1 100644
> --- a/xen/include/xen/domain.h
> +++ b/xen/include/xen/domain.h
> @@ -109,6 +109,8 @@ int arch_domain_soft_reset(struct domain *d);
> =20
>  void arch_domain_creation_finished(struct domain *d);
> =20
> +int arch_domain_resume(struct domain *d);
> +
>  void arch_p2m_set_access_required(struct domain *d, bool access_required=
);
> =20
>  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c);

--=20
WBR, Volodymyr=


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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v4 09/12] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Topic: [PATCH v4 09/12] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Index: AQHcF3/Ont2iCNudZU+HGYrvI6u3EbR4DeIAgAA3ngA=
Date: Thu, 28 Aug 2025 16:38:59 +0000
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From: Oleksii Moisieiev 
To: "xen-devel@lists.xenproject.org" 
CC: Andrew Cooper , Anthony PERARD
	, Bertrand Marquis , Jan
 Beulich , Juergen Gross , Julien Grall
	, Michal Orzel , Oleksii Moisieiev
	, =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini ,
	Volodymyr Babchuk , Grygorii Strashko
	
Subject: [PATCH v6 3/4] xen/arm: scmi-smc: passthrough SCMI SMC to domain,
 single agent
Thread-Topic: [PATCH v6 3/4] xen/arm: scmi-smc: passthrough SCMI SMC to
 domain, single agent
Thread-Index: AQHcGDp07aUQwsobaUO2Bmd+Gq/u2A==
Date: Thu, 28 Aug 2025 16:40:25 +0000
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 <02b79eaa0a611fb43a2146a5f41aec435d3db6c7.1756399156.git.oleksii_moisieiev@epam.com>
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From: Grygorii Strashko 

The commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI over SMC calls
handling layer") introduces simple driver which forwards SCMI over SMC
calls from hwdom/dom0 to EL3 firmware (TF-A) with a single SCMI OSPM agent
support. While it is working gracefully for hwdom/dom0 use case it doesn't
cover "thin Dom0 with guest domain, which serves as Driver domain"
use-case. In this case HW need to be enable in Driver domain and dom0 is
performing only control functions.

The EL3 SCMI firmware (TF-A) with a single SCMI OSPM agent support is
pretty generic case for the default vendors SDK and new platforms.

This patch enables passthrough of SCMI SMC single agent interface to the
one guest domain serving as Driver domain.

Configure Dom0 to enable SCMI passthrough:

 - dom0: add scmi-smc-passthrough to the Xen Command Line

Enabled SCMI passthrough for guest using toolstack in the following way:

 - domD: xl.cfg add "arm_sci" option as below

   arm_sci =3D "type=3Dscmi_smc"

 - domD: xl.cfg enable access to the "arm,scmi-shmem"

iomem =3D [
    "47ff0,1@22001",
]

 - domD: add SCMI nodes to the Driver domain partial device tree as in the
 below example:

passthrough {
   scmi_shm_0: sram@22001000 {
       compatible =3D "arm,scmi-shmem";
       reg =3D <0x0 0x22001000 0x0 0x1000>;
   };

   firmware {
        compatible =3D "simple-bus";
            scmi: scmi {
                compatible =3D "arm,scmi-smc";
                shmem =3D <&scmi_shm_0>;
                ...
            }
    }
}

dom0less case configuration:

- add "xen,sci_type" property for required DomU ("xen,domain") node

   xen,sci_type=3D"scmi_smc"

- add scmi nodes to the Driver domain partial device tree the same way
as above and enable access to the "arm,scmi-shmem" according to
dom0less documentation. For example:

  scmi_shm_0: sram@22001000 {
        compatible =3D "arm,scmi-shmem";
        reg =3D <0x00 0x22001000 0x00 0x1000>;
->        xen,reg =3D <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
->        xen,force-assign-without-iommu;
  };

The SCMI SMC single agent interface can be enabled for one and only one
domain. In general, the configuration is similar to any other HW
passthrough, except explicitly enabling SCMI with "arm_sci" xl.cfg option.

Note that "arm,scmi-smc" and "arm,scmi-shmem" nodes will be removed from
dom0/hwdom DT in case of

Signed-off-by: Grygorii Strashko 
Signed-off-by: Oleksii Moisieiev 
Acked-by: Anthony PERARD  # tools
---

Changes in v6:
- added generated helpers and types go files
- rename cmdline parameter to scmi-smc-passthrough
- fix goto tag in parse_arm_sci_config

Changes in v5:
- rename dom0_scmi_smc_passthrough to scmi_smc_passthrough

Changes in v4:
- xl.cfg doc
- fix comments from Stefano Stabellini
- fix toolstack code as sugested by Anthony PERARD
  - use MATCH_OPTION()
  - move arm_sci struct and cfg params in "arch_arm"
- add SCMI passthrough for dom0less case

 docs/man/xl.cfg.5.pod.in              |  34 ++++++++
 docs/misc/arm/device-tree/booting.txt |  15 ++++
 docs/misc/xen-command-line.pandoc     |   9 +++
 tools/golang/xenlight/helpers.gen.go  |  41 ++++++++++
 tools/golang/xenlight/types.gen.go    |  12 +++
 tools/include/libxl.h                 |   5 ++
 tools/libs/light/libxl_arm.c          |  14 ++++
 tools/libs/light/libxl_types.idl      |  10 +++
 tools/xl/xl_parse.c                   |  36 +++++++++
 xen/arch/arm/dom0less-build.c         |  34 +++++++-
 xen/arch/arm/firmware/Kconfig         |   4 +-
 xen/arch/arm/firmware/scmi-smc.c      | 112 +++++++++++++++++++++++++-
 12 files changed, 321 insertions(+), 5 deletions(-)

diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
index acff45d308..3b18bcc095 100644
--- a/docs/man/xl.cfg.5.pod.in
+++ b/docs/man/xl.cfg.5.pod.in
@@ -3123,6 +3123,40 @@ writes will be ignored.
=20
 This option is only implemented for Arm where the default is enabled.
=20
+=3Ditem B
+
+Set ARM_SCI specific options for the guest. ARM SCI is System
+Control Protocol allows domain to manage various functions that are provid=
ed
+by HW platform firmware.
+
+B is a comma separated list of C settings,
+from the following list:
+
+=3Dover 4
+
+=3Ditem B
+
+Specifies an ARM SCI type for the guest.
+
+=3Dover 4
+
+=3Ditem B
+
+Don't allow guest to use ARM SCI if present on the platform. This is the
+default value.
+
+=3Ditem B
+
+Enables ARM SCMI SMC support for the guest by enabling SCMI over SMC calls
+forwarding from domain to the EL3 firmware (like Trusted Firmware-A) with =
a
+single SCMI OSPM agent support.
+Should be used together with B Xen command line
+option.
+
+=3Dback
+
+=3Dback
+
 =3Dback
=20
 =3Dhead3 x86
diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-t=
ree/booting.txt
index 07acc7ba64..977b428608 100644
--- a/docs/misc/arm/device-tree/booting.txt
+++ b/docs/misc/arm/device-tree/booting.txt
@@ -307,6 +307,21 @@ with the following properties:
     passed through. This option is the default if this property is missing
     and the user does not provide the device partial device tree for the d=
omain.
=20
+- xen,sci_type
+
+    A string property specifying an ARM SCI type for the guest.
+
+    - "none"
+    Don't allow guest to use ARM SCI if present on the platform. This is t=
he
+    default value.
+
+    - "scmi_smc"
+    Enables ARM SCMI SMC support for the guest by enabling SCMI over SMC c=
alls
+    forwarding from domain to the EL3 firmware (like Trusted Firmware-A) w=
ith a
+    single SCMI OSPM agent support.
+    Should be used together with scmi-smc-passthrough Xen command line
+    option.
+
 Under the "xen,domain" compatible node, one or more sub-nodes are present
 for the DomU kernel and ramdisk.
=20
diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line=
.pandoc
index a75b6c9301..0a3d697396 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -1097,6 +1097,15 @@ affinities to prefer but be not limited to the speci=
fied node(s).
=20
 Pin dom0 vcpus to their respective pcpus
=20
+### scmi-smc-passthrough (ARM)
+> `=3D `
+
+The option is available when `CONFIG_SCMI_SMC` is compiled in, and allows =
to
+enable SCMI SMC single agent interface for any, but only one guest domain,
+which serves as Driver domain. The SCMI will be disabled for Dom0/hwdom an=
d
+SCMI nodes removed from Dom0/hwdom device tree.
+(for example, thin Dom0 with Driver domain use-case).
+
 ### dtuart (ARM)
 > `=3D path [:options]`
=20
diff --git a/tools/golang/xenlight/helpers.gen.go b/tools/golang/xenlight/h=
elpers.gen.go
index 667030cbd7..3937653dab 100644
--- a/tools/golang/xenlight/helpers.gen.go
+++ b/tools/golang/xenlight/helpers.gen.go
@@ -938,6 +938,35 @@ return fmt.Errorf("converting field Vcpus: %v", err)
  return nil
  }
=20
+// NewArmSci returns an instance of ArmSci initialized with defaults.
+func NewArmSci() (*ArmSci, error) {
+var (
+x ArmSci
+xc C.libxl_arm_sci)
+
+C.libxl_arm_sci_init(&xc)
+defer C.libxl_arm_sci_dispose(&xc)
+
+if err :=3D x.fromC(&xc); err !=3D nil {
+return nil, err }
+
+return &x, nil}
+
+func (x *ArmSci) fromC(xc *C.libxl_arm_sci) error {
+ x.Type =3D ArmSciType(xc._type)
+
+ return nil}
+
+func (x *ArmSci) toC(xc *C.libxl_arm_sci) (err error){defer func(){
+if err !=3D nil{
+C.libxl_arm_sci_dispose(xc)}
+}()
+
+xc._type =3D C.libxl_arm_sci_type(x.Type)
+
+ return nil
+ }
+
 // NewRdmReserve returns an instance of RdmReserve initialized with defaul=
ts.
 func NewRdmReserve() (*RdmReserve, error) {
 var (
@@ -1113,6 +1142,9 @@ x.Kernel =3D C.GoString(xc.kernel)
 x.Cmdline =3D C.GoString(xc.cmdline)
 x.Ramdisk =3D C.GoString(xc.ramdisk)
 x.DeviceTree =3D C.GoString(xc.device_tree)
+if err :=3D x.DtPassthroughNodes.fromC(&xc.dt_passthrough_nodes);err !=3D =
nil {
+return fmt.Errorf("converting field DtPassthroughNodes: %v", err)
+}
 if err :=3D x.Acpi.fromC(&xc.acpi);err !=3D nil {
 return fmt.Errorf("converting field Acpi: %v", err)
 }
@@ -1163,6 +1195,9 @@ x.ArchArm.GicVersion =3D GicVersion(xc.arch_arm.gic_v=
ersion)
 x.ArchArm.Vuart =3D VuartType(xc.arch_arm.vuart)
 x.ArchArm.SveVl =3D SveType(xc.arch_arm.sve_vl)
 x.ArchArm.NrSpis =3D uint32(xc.arch_arm.nr_spis)
+if err :=3D x.ArchArm.ArmSci.fromC(&xc.arch_arm.arm_sci);err !=3D nil {
+return fmt.Errorf("converting field ArchArm.ArmSci: %v", err)
+}
 if err :=3D x.ArchX86.MsrRelaxed.fromC(&xc.arch_x86.msr_relaxed);err !=3D =
nil {
 return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err)
 }
@@ -1489,6 +1524,9 @@ if x.Ramdisk !=3D "" {
 xc.ramdisk =3D C.CString(x.Ramdisk)}
 if x.DeviceTree !=3D "" {
 xc.device_tree =3D C.CString(x.DeviceTree)}
+if err :=3D x.DtPassthroughNodes.toC(&xc.dt_passthrough_nodes); err !=3D n=
il {
+return fmt.Errorf("converting field DtPassthroughNodes: %v", err)
+}
 if err :=3D x.Acpi.toC(&xc.acpi); err !=3D nil {
 return fmt.Errorf("converting field Acpi: %v", err)
 }
@@ -1699,6 +1737,9 @@ xc.arch_arm.gic_version =3D C.libxl_gic_version(x.Arc=
hArm.GicVersion)
 xc.arch_arm.vuart =3D C.libxl_vuart_type(x.ArchArm.Vuart)
 xc.arch_arm.sve_vl =3D C.libxl_sve_type(x.ArchArm.SveVl)
 xc.arch_arm.nr_spis =3D C.uint32_t(x.ArchArm.NrSpis)
+if err :=3D x.ArchArm.ArmSci.toC(&xc.arch_arm.arm_sci); err !=3D nil {
+return fmt.Errorf("converting field ArchArm.ArmSci: %v", err)
+}
 if err :=3D x.ArchX86.MsrRelaxed.toC(&xc.arch_x86.msr_relaxed); err !=3D n=
il {
 return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err)
 }
diff --git a/tools/golang/xenlight/types.gen.go b/tools/golang/xenlight/typ=
es.gen.go
index e26b3cdfc7..328afe0d94 100644
--- a/tools/golang/xenlight/types.gen.go
+++ b/tools/golang/xenlight/types.gen.go
@@ -520,6 +520,16 @@ SveType1920 SveType =3D 1920
 SveType2048 SveType =3D 2048
 )
=20
+type ArmSciType int
+const(
+ArmSciTypeNone ArmSciType =3D 0
+ArmSciTypeScmiSmc ArmSciType =3D 1
+)
+
+type ArmSci struct {
+Type ArmSciType
+}
+
 type RdmReserve struct {
 Strategy RdmReserveStrategy
 Policy RdmReservePolicy
@@ -582,6 +592,7 @@ Kernel string
 Cmdline string
 Ramdisk string
 DeviceTree string
+DtPassthroughNodes StringList
 Acpi Defbool
 Bootloader string
 BootloaderArgs StringList
@@ -599,6 +610,7 @@ GicVersion GicVersion
 Vuart VuartType
 SveVl SveType
 NrSpis uint32
+ArmSci ArmSci
 }
 ArchX86 struct {
 MsrRelaxed Defbool
diff --git a/tools/include/libxl.h b/tools/include/libxl.h
index 185f74d8a8..bc35e412da 100644
--- a/tools/include/libxl.h
+++ b/tools/include/libxl.h
@@ -313,6 +313,11 @@
  */
 #define LIBXL_HAVE_BUILDINFO_ARCH_NR_SPIS 1
=20
+/*
+ * libxl_domain_build_info has the arch_arm.sci* fields.
+ */
+#define LIBXL_HAVE_BUILDINFO_ARCH_ARM_SCI 1
+
 /*
  * LIBXL_HAVE_SOFT_RESET indicates that libxl supports performing
  * 'soft reset' for domains and there is 'soft_reset' shutdown reason
diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c
index ec258bdc16..e4407d6e3f 100644
--- a/tools/libs/light/libxl_arm.c
+++ b/tools/libs/light/libxl_arm.c
@@ -233,6 +233,20 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
         config->arch.sve_vl =3D d_config->b_info.arch_arm.sve_vl / 128U;
     }
=20
+    switch (d_config->b_info.arch_arm.arm_sci.type) {
+    case LIBXL_ARM_SCI_TYPE_NONE:
+        config->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
+        break;
+    case LIBXL_ARM_SCI_TYPE_SCMI_SMC:
+        config->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC;
+        break;
+    default:
+        LOG(ERROR, "Unknown ARM_SCI type %d",
+            d_config->b_info.arch_arm.arm_sci.type);
+        return ERROR_FAIL;
+    }
+    LOG(DEBUG, " - SCI type=3D%u", config->arch.arm_sci_type);
+
     return 0;
 }
=20
diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_type=
s.idl
index faef3d63a1..c8e3f77947 100644
--- a/tools/libs/light/libxl_types.idl
+++ b/tools/libs/light/libxl_types.idl
@@ -551,6 +551,15 @@ libxl_sve_type =3D Enumeration("sve_type", [
     (2048, "2048")
     ], init_val =3D "LIBXL_SVE_TYPE_DISABLED")
=20
+libxl_arm_sci_type =3D Enumeration("arm_sci_type", [
+    (0, "none"),
+    (1, "scmi_smc")
+    ], init_val =3D "LIBXL_ARM_SCI_TYPE_NONE")
+
+libxl_arm_sci =3D Struct("arm_sci", [
+    ("type", libxl_arm_sci_type),
+    ])
+
 libxl_rdm_reserve =3D Struct("rdm_reserve", [
     ("strategy",    libxl_rdm_reserve_strategy),
     ("policy",      libxl_rdm_reserve_policy),
@@ -726,6 +735,7 @@ libxl_domain_build_info =3D Struct("domain_build_info",=
[
                                ("vuart", libxl_vuart_type),
                                ("sve_vl", libxl_sve_type),
                                ("nr_spis", uint32, {'init_val': 'LIBXL_NR_=
SPIS_DEFAULT'}),
+                               ("arm_sci", libxl_arm_sci),
                               ])),
     ("arch_x86", Struct(None, [("msr_relaxed", libxl_defbool),
                               ])),
diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
index 61660a02da..1cc41f1bff 100644
--- a/tools/xl/xl_parse.c
+++ b/tools/xl/xl_parse.c
@@ -1284,6 +1284,36 @@ out:
     if (rc) exit(EXIT_FAILURE);
 }
=20
+static int parse_arm_sci_config(XLU_Config *cfg, libxl_arm_sci *arm_sci,
+                                const char *str)
+{
+    int ret =3D 0;
+    char *buf2, *ptr;
+    char *oparg;
+
+    if (NULL =3D=3D (buf2 =3D ptr =3D strdup(str)))
+        return ERROR_NOMEM;
+
+    ptr =3D strtok(buf2, ",");
+    while (ptr !=3D NULL)
+    {
+        if (MATCH_OPTION("type", ptr, oparg)) {
+            ret =3D libxl_arm_sci_type_from_string(oparg, &arm_sci->type);
+            if (ret) {
+                fprintf(stderr, "Unknown ARM_SCI type: %s\n", oparg);
+                ret =3D ERROR_INVAL;
+                goto out;
+            }
+        }
+
+        ptr =3D strtok(NULL, ",");
+    }
+
+out:
+    free(buf2);
+    return ret;
+}
+
 void parse_config_data(const char *config_source,
                        const char *config_data,
                        int config_len,
@@ -2996,6 +3026,12 @@ skip_usbdev:
     xlu_cfg_get_defbool(config, "trap_unmapped_accesses",
                         &b_info->trap_unmapped_accesses, 0);
=20
+    if (!xlu_cfg_get_string(config, "arm_sci", &buf, 1)) {
+        if (parse_arm_sci_config(config, &b_info->arch_arm.arm_sci, buf)) =
{
+            exit(EXIT_FAILURE);
+        }
+    }
+
     parse_vkb_list(config, d_config);
=20
     d_config->virtios =3D NULL;
diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 0094cf9e40..7422f4be30 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -279,6 +279,36 @@ int __init arch_handle_passthrough_prop(struct kernel_=
info *kinfo,
     return sci_assign_dt_device(kinfo->bd.d, node);
 }
=20
+int __init domu_dt_sci_parse(struct dt_device_node *node,
+                             struct xen_domctl_createdomain *d_cfg)
+{
+    const char *sci_type =3D NULL;
+    int ret;
+
+    d_cfg->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
+
+    if ( !IS_ENABLED(CONFIG_ARM_SCI) ||
+         !dt_property_read_bool(node, "xen,sci_type") )
+        return 0;
+
+    ret =3D dt_property_read_string(node, "xen,sci_type", &sci_type);
+    if ( ret )
+        return ret;
+
+    if ( !strcmp(sci_type, "none") )
+        d_cfg->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
+    else if ( !strcmp(sci_type, "scmi_smc") )
+        d_cfg->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC;
+    else
+    {
+        printk(XENLOG_ERR "xen,sci_type in not valid (%s) for domain %s\n"=
,
+               sci_type, dt_node_name(node));
+        return -EINVAL;
+    }
+
+    return 0;
+}
+
 int __init arch_parse_dom0less_node(struct dt_device_node *node,
                                     struct boot_domain *bd)
 {
@@ -288,7 +318,9 @@ int __init arch_parse_dom0less_node(struct dt_device_no=
de *node,
=20
     d_cfg->arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
     d_cfg->flags |=3D XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap;
-    d_cfg->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
+
+    if ( domu_dt_sci_parse(node, d_cfg) )
+        panic("Error getting SCI configuration\n");
=20
     if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) )
     {
diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig
index bbf88fbb9a..5c5f0880c4 100644
--- a/xen/arch/arm/firmware/Kconfig
+++ b/xen/arch/arm/firmware/Kconfig
@@ -25,7 +25,9 @@ config SCMI_SMC
 	  doorbell mechanism and Shared Memory for transport ("arm,scmi-smc"
 	  compatible only). The value of "arm,smc-id" DT property from SCMI
 	  firmware node is used to trap and forward corresponding SCMI SMCs
-	  to firmware running at EL3, for calls coming from the hardware domain.
+	  to firmware running at EL3, for calls coming from the hardware domain o=
r
+	  driver domain.
+	  Use with EL3 firmware which supports only single SCMI OSPM agent.
=20
 endchoice
=20
diff --git a/xen/arch/arm/firmware/scmi-smc.c b/xen/arch/arm/firmware/scmi-=
smc.c
index 13d1137592..edc54b11b6 100644
--- a/xen/arch/arm/firmware/scmi-smc.c
+++ b/xen/arch/arm/firmware/scmi-smc.c
@@ -14,6 +14,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
=20
@@ -22,7 +24,11 @@
=20
 #define SCMI_SMC_ID_PROP   "arm,smc-id"
=20
+static bool __ro_after_init opt_scmi_smc_passthrough =3D false;
+boolean_param("scmi-smc-passthrough", opt_scmi_smc_passthrough);
+
 static uint32_t __ro_after_init scmi_smc_id;
+static struct domain __read_mostly *scmi_dom;
=20
 /*
  * Check if provided SMC Function Identifier matches the one known by the =
SCMI
@@ -50,7 +56,7 @@ static bool scmi_handle_smc(struct cpu_user_regs *regs)
         return false;
=20
     /* Only the hardware domain should use SCMI calls */
-    if ( !is_hardware_domain(current->domain) )
+    if ( scmi_dom !=3D current->domain )
     {
         gdprintk(XENLOG_WARNING, "SCMI: Unprivileged access attempt\n");
         return false;
@@ -75,12 +81,45 @@ static bool scmi_handle_smc(struct cpu_user_regs *regs)
     return true;
 }
=20
+static int
+scmi_smc_domain_sanitise_config(struct xen_domctl_createdomain *config)
+{
+    if ( config->arch.arm_sci_type !=3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE &&
+         config->arch.arm_sci_type !=3D XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC=
 )
+        return -EINVAL;
+
+    return 0;
+}
+
 static int scmi_smc_domain_init(struct domain *d,
                                 struct xen_domctl_createdomain *config)
 {
-    if ( !is_hardware_domain(d) )
+    /*
+     * scmi_passthrough is not enabled:
+     * - proceed only for hw_domain
+     * - fail if guest domain has SCMI enabled.
+     */
+    if ( !opt_scmi_smc_passthrough && !is_hardware_domain(d) )
+    {
+        if ( config->arch.arm_sci_type =3D=3D XEN_DOMCTL_CONFIG_ARM_SCI_SC=
MI_SMC )
+            return -EINVAL;
+        else
+            return 0;
+    }
+    /*
+     * scmi_passthrough is enabled:
+     * - ignore hw_domain
+     * - proceed only for domain with SCMI enabled.
+     */
+    if ( opt_scmi_smc_passthrough &&
+         (config->arch.arm_sci_type =3D=3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE =
||
+          is_hardware_domain(d)) )
         return 0;
=20
+    if ( scmi_dom )
+        return -EEXIST;
+
+    scmi_dom =3D d;
     d->arch.sci_enabled =3D true;
     printk(XENLOG_DEBUG "SCMI: %pd init\n", d);
     return 0;
@@ -88,12 +127,77 @@ static int scmi_smc_domain_init(struct domain *d,
=20
 static void scmi_smc_domain_destroy(struct domain *d)
 {
-    if ( !is_hardware_domain(d) )
+    if ( scmi_dom && scmi_dom !=3D d )
         return;
=20
+    scmi_dom =3D NULL;
+    d->arch.sci_enabled =3D false;
     printk(XENLOG_DEBUG "SCMI: %pd destroy\n", d);
 }
=20
+/*
+ * Handle Dom0 SCMI SMC specific DT nodes
+ *
+ * if scmi_smc_passthrough=3Dfalse:
+ * - Copy SCMI nodes into Dom0 device tree.
+ * if scmi_smc_passthrough=3Dtrue:
+ * - skip SCMI nodes from Dom0 DT
+ * - give dom0 control access to SCMI shmem MMIO, so SCMI can be passed
+ *   through to guest.
+ */
+static bool scmi_smc_dt_handle_node(struct domain *d,
+                                    struct dt_device_node *node)
+{
+    static const struct dt_device_match shmem_matches[] __initconst =3D {
+        DT_MATCH_COMPATIBLE("arm,scmi-shmem"),
+        { /* sentinel */ },
+    };
+    static const struct dt_device_match scmi_matches[] __initconst =3D {
+        DT_MATCH_PATH("/firmware/scmi"),
+        { /* sentinel */ },
+    };
+
+    /* skip scmi shmem node for dom0 if scmi not enabled */
+    if ( dt_match_node(shmem_matches, node) && !sci_domain_is_enabled(d) )
+    {
+        dt_dprintk("Skip scmi shmem node\n");
+        return true;
+    }
+
+    /*
+     * skip scmi node for dom0 if scmi not enabled, but give dom0 control
+     * access to SCMI shmem
+     */
+    if ( dt_match_node(scmi_matches, node) && !sci_domain_is_enabled(d) )
+    {
+        struct dt_device_node *shmem_node;
+        const __be32 *prop;
+        u64 paddr, size;
+        int ret;
+
+        /* give dom0 control access to SCMI shmem */
+        prop =3D dt_get_property(node, "shmem", NULL);
+        if ( !prop )
+            return true;
+
+        shmem_node =3D dt_find_node_by_phandle(be32_to_cpu(*prop));
+        if ( !shmem_node )
+            return true;
+
+        ret =3D dt_device_get_address(shmem_node, 0, &paddr, &size);
+        if ( ret )
+            return true;
+
+        ret =3D iomem_permit_access(d, paddr_to_pfn(paddr),
+                                  paddr_to_pfn(paddr + size - 1));
+
+        dt_dprintk("Skip scmi node\n");
+        return true;
+    }
+
+    return false;
+}
+
 static int __init scmi_check_smccc_ver(void)
 {
     if ( smccc_ver < ARM_SMCCC_VERSION_1_1 )
@@ -108,8 +212,10 @@ static int __init scmi_check_smccc_ver(void)
=20
 static const struct sci_mediator_ops scmi_smc_ops =3D {
     .handle_call =3D scmi_handle_smc,
+    .domain_sanitise_config =3D scmi_smc_domain_sanitise_config,
     .domain_init =3D scmi_smc_domain_init,
     .domain_destroy =3D scmi_smc_domain_destroy,
+    .dom0_dt_handle_node =3D scmi_smc_dt_handle_node,
 };
=20
 /* Initialize the SCMI layer based on SMCs and Device-tree */
--=20
2.34.1


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From: Oleksii Moisieiev 
To: "xen-devel@lists.xenproject.org" 
CC: Andrew Cooper , Anthony PERARD
	, Bertrand Marquis , Jan
 Beulich , Juergen Gross , Julien Grall
	, Michal Orzel , Oleksii Moisieiev
	, =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini ,
	Volodymyr Babchuk , Grygorii Strashko
	
Subject: [PATCH v6 2/4] xen/arm: scmi-smc: update to be used under sci
 subsystem
Thread-Topic: [PATCH v6 2/4] xen/arm: scmi-smc: update to be used under sci
 subsystem
Thread-Index: AQHcGDp0dNGz8RLSIkyOshrRMf8UOQ==
Date: Thu, 28 Aug 2025 16:40:25 +0000
Message-ID:
 <8e7e9dcdd643b6681a6127d56b68536b987141af.1756399156.git.oleksii_moisieiev@epam.com>
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From: Grygorii Strashko 

The introduced SCI (System Control Interface) subsystem provides unified
interface to integrate in Xen SCI drivers which adds support for ARM
firmware (EL3, SCP) based software interfaces (like SCMI) that are used in
system management. The SCI subsystem allows to add drivers for different FW
interfaces or have different drivers for the same FW interface (for example=
,
SCMI with different transports).

This patch updates SCMI over SMC calls handling layer, introduced by
commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI over SMC calls handling
layer"), to be SCI driver:
- convert to DT device;
- convert to SCI Xen interface.

There are no functional changes in general, the driver is just adopted
to the SCI interface.

Signed-off-by: Grygorii Strashko 
Reviewed-by: Stefano Stabellini 
---

Changes in v6:
- add R-b tag

 xen/arch/arm/firmware/Kconfig                | 13 ++-
 xen/arch/arm/firmware/scmi-smc.c             | 93 +++++++++++---------
 xen/arch/arm/include/asm/firmware/scmi-smc.h | 41 ---------
 xen/arch/arm/vsmc.c                          |  5 +-
 xen/include/public/arch-arm.h                |  1 +
 5 files changed, 64 insertions(+), 89 deletions(-)
 delete mode 100644 xen/arch/arm/include/asm/firmware/scmi-smc.h

diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig
index fc7918c7fc..bbf88fbb9a 100644
--- a/xen/arch/arm/firmware/Kconfig
+++ b/xen/arch/arm/firmware/Kconfig
@@ -8,9 +8,18 @@ config ARM_SCI
=20
 menu "Firmware Drivers"
=20
+choice
+	prompt "ARM SCI driver type"
+	default SCMI_SMC
+	help
+	Choose which ARM SCI driver to enable.
+
+config ARM_SCI_NONE
+	bool "none"
+
 config SCMI_SMC
 	bool "Forward SCMI over SMC calls from hwdom to EL3 firmware"
-	default y
+	select ARM_SCI
 	help
 	  This option enables basic awareness for SCMI calls using SMC as
 	  doorbell mechanism and Shared Memory for transport ("arm,scmi-smc"
@@ -18,4 +27,6 @@ config SCMI_SMC
 	  firmware node is used to trap and forward corresponding SCMI SMCs
 	  to firmware running at EL3, for calls coming from the hardware domain.
=20
+endchoice
+
 endmenu
diff --git a/xen/arch/arm/firmware/scmi-smc.c b/xen/arch/arm/firmware/scmi-=
smc.c
index 33473c04b1..13d1137592 100644
--- a/xen/arch/arm/firmware/scmi-smc.c
+++ b/xen/arch/arm/firmware/scmi-smc.c
@@ -9,6 +9,7 @@
  * Copyright 2024 NXP
  */
=20
+#include 
 #include 
 #include 
 #include 
@@ -16,12 +17,11 @@
 #include 
 #include 
=20
+#include 
 #include 
-#include 
=20
 #define SCMI_SMC_ID_PROP   "arm,smc-id"
=20
-static bool __ro_after_init scmi_enabled;
 static uint32_t __ro_after_init scmi_smc_id;
=20
 /*
@@ -41,14 +41,11 @@ static bool scmi_is_valid_smc_id(uint32_t fid)
  *
  * Returns true if SMC was handled (regardless of response), false otherwi=
se.
  */
-bool scmi_handle_smc(struct cpu_user_regs *regs)
+static bool scmi_handle_smc(struct cpu_user_regs *regs)
 {
     uint32_t fid =3D (uint32_t)get_user_reg(regs, 0);
     struct arm_smccc_res res;
=20
-    if ( !scmi_enabled )
-        return false;
-
     if ( !scmi_is_valid_smc_id(fid) )
         return false;
=20
@@ -78,49 +75,45 @@ bool scmi_handle_smc(struct cpu_user_regs *regs)
     return true;
 }
=20
-static int __init scmi_check_smccc_ver(void)
+static int scmi_smc_domain_init(struct domain *d,
+                                struct xen_domctl_createdomain *config)
 {
-    if ( smccc_ver < ARM_SMCCC_VERSION_1_1 )
-    {
-        printk(XENLOG_WARNING
-               "SCMI: No SMCCC 1.1 support, SCMI calls forwarding disabled=
\n");
-        return -ENOSYS;
-    }
+    if ( !is_hardware_domain(d) )
+        return 0;
=20
+    d->arch.sci_enabled =3D true;
+    printk(XENLOG_DEBUG "SCMI: %pd init\n", d);
     return 0;
 }
=20
-static int __init scmi_dt_init_smccc(void)
+static void scmi_smc_domain_destroy(struct domain *d)
 {
-    static const struct dt_device_match scmi_ids[] __initconst =3D
-    {
-        /* We only support "arm,scmi-smc" binding for now */
-        DT_MATCH_COMPATIBLE("arm,scmi-smc"),
-        { /* sentinel */ },
-    };
-    const struct dt_device_node *scmi_node;
-    int ret;
+    if ( !is_hardware_domain(d) )
+        return;
=20
-    /* If no SCMI firmware node found, fail silently as it's not mandatory=
 */
-    scmi_node =3D dt_find_matching_node(NULL, scmi_ids);
-    if ( !scmi_node )
-        return -EOPNOTSUPP;
+    printk(XENLOG_DEBUG "SCMI: %pd destroy\n", d);
+}
=20
-    ret =3D dt_property_read_u32(scmi_node, SCMI_SMC_ID_PROP, &scmi_smc_id=
);
-    if ( !ret )
+static int __init scmi_check_smccc_ver(void)
+{
+    if ( smccc_ver < ARM_SMCCC_VERSION_1_1 )
     {
-        printk(XENLOG_ERR "SCMI: No valid \"%s\" property in \"%s\" DT nod=
e\n",
-               SCMI_SMC_ID_PROP, scmi_node->full_name);
-        return -ENOENT;
+        printk(XENLOG_WARNING
+               "SCMI: No SMCCC 1.1 support, SCMI calls forwarding disabled=
\n");
+        return -ENOSYS;
     }
=20
-    scmi_enabled =3D true;
-
     return 0;
 }
=20
+static const struct sci_mediator_ops scmi_smc_ops =3D {
+    .handle_call =3D scmi_handle_smc,
+    .domain_init =3D scmi_smc_domain_init,
+    .domain_destroy =3D scmi_smc_domain_destroy,
+};
+
 /* Initialize the SCMI layer based on SMCs and Device-tree */
-static int __init scmi_init(void)
+static int __init scmi_dom0_init(struct dt_device_node *dev, const void *d=
ata)
 {
     int ret;
=20
@@ -134,22 +127,36 @@ static int __init scmi_init(void)
     if ( ret )
         return ret;
=20
-    ret =3D scmi_dt_init_smccc();
-    if ( ret =3D=3D -EOPNOTSUPP )
-        return ret;
+    ret =3D dt_property_read_u32(dev, SCMI_SMC_ID_PROP, &scmi_smc_id);
+    if ( !ret )
+    {
+        printk(XENLOG_ERR "SCMI: No valid \"%s\" property in \"%s\" DT nod=
e\n",
+               SCMI_SMC_ID_PROP, dt_node_full_name(dev));
+        return -ENOENT;
+    }
+
+    ret =3D sci_register(&scmi_smc_ops);
     if ( ret )
-        goto err;
+    {
+        printk(XENLOG_ERR "SCMI: mediator already registered (ret =3D %d)\=
n",
+               ret);
+        return ret;
+    }
=20
     printk(XENLOG_INFO "Using SCMI with SMC ID: 0x%x\n", scmi_smc_id);
=20
     return 0;
-
- err:
-    printk(XENLOG_ERR "SCMI: Initialization failed (ret =3D %d)\n", ret);
-    return ret;
 }
=20
-__initcall(scmi_init);
+static const struct dt_device_match scmi_smc_match[] __initconst =3D {
+    DT_MATCH_COMPATIBLE("arm,scmi-smc"),
+    { /* sentinel */ },
+};
+
+DT_DEVICE_START(scmi_smc, "SCMI SMC DOM0", DEVICE_FIRMWARE)
+    .dt_match =3D scmi_smc_match,
+    .init =3D scmi_dom0_init,
+DT_DEVICE_END
=20
 /*
  * Local variables:
diff --git a/xen/arch/arm/include/asm/firmware/scmi-smc.h b/xen/arch/arm/in=
clude/asm/firmware/scmi-smc.h
deleted file mode 100644
index 6b1a164a40..0000000000
--- a/xen/arch/arm/include/asm/firmware/scmi-smc.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * xen/arch/arm/include/asm/firmware/scmi-smc.h
- *
- * ARM System Control and Management Interface (SCMI) over SMC
- * Generic handling layer
- *
- * Andrei Cherechesu 
- * Copyright 2024 NXP
- */
-
-#ifndef __ASM_SCMI_SMC_H__
-#define __ASM_SCMI_SMC_H__
-
-#include 
-
-struct cpu_user_regs;
-
-#ifdef CONFIG_SCMI_SMC
-
-bool scmi_handle_smc(struct cpu_user_regs *regs);
-
-#else
-
-static inline bool scmi_handle_smc(struct cpu_user_regs *regs)
-{
-    return false;
-}
-
-#endif /* CONFIG_SCMI_SMC */
-
-#endif /* __ASM_SCMI_H__ */
-
-/*
- * Local variables:
- * mode: C
- * c-file-style: "BSD"
- * c-basic-offset: 4
- * indent-tabs-mode: nil
- * End:
- */
diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c
index 2469738fcc..78d5bdf56f 100644
--- a/xen/arch/arm/vsmc.c
+++ b/xen/arch/arm/vsmc.c
@@ -21,7 +21,6 @@
 #include 
 #include 
 #include 
-#include 
=20
 /* Number of functions currently supported by Hypervisor Service. */
 #define XEN_SMCCC_FUNCTION_COUNT 3
@@ -233,7 +232,7 @@ static bool handle_sip(struct cpu_user_regs *regs)
     if ( platform_smc(regs) )
         return true;
=20
-    return scmi_handle_smc(regs);
+    return sci_handle_call(regs);
 }
=20
 /*
@@ -301,8 +300,6 @@ static bool vsmccc_handle_call(struct cpu_user_regs *re=
gs)
             break;
         case ARM_SMCCC_OWNER_SIP:
             handled =3D handle_sip(regs);
-            if ( !handled )
-                handled =3D sci_handle_call(regs);
             break;
         case ARM_SMCCC_OWNER_TRUSTED_APP ... ARM_SMCCC_OWNER_TRUSTED_APP_E=
ND:
         case ARM_SMCCC_OWNER_TRUSTED_OS ... ARM_SMCCC_OWNER_TRUSTED_OS_END=
:
diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index 55eed9992c..095b1a23e3 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -328,6 +328,7 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
 #define XEN_DOMCTL_CONFIG_TEE_FFA       2
=20
 #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE      0
+#define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC  1
=20
 struct xen_arch_domainconfig {
     /* IN/OUT */
--=20
2.34.1


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From: Oleksii Moisieiev 
To: "xen-devel@lists.xenproject.org" 
CC: Andrew Cooper , Anthony PERARD
	, Bertrand Marquis , Jan
 Beulich , Juergen Gross , Julien Grall
	, Michal Orzel , Oleksii Moisieiev
	, =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini ,
	Volodymyr Babchuk , Grygorii Strashko
	
Subject: [PATCH v6 1/4] xen/arm: add generic SCI subsystem
Thread-Topic: [PATCH v6 1/4] xen/arm: add generic SCI subsystem
Thread-Index: AQHcGDp0HddMWoIUiESW9wlppK7Vcg==
Date: Thu, 28 Aug 2025 16:40:25 +0000
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This patch adds the basic framework for ARM SCI mediator. SCI is System
Control Interface, which is designed to redirect requests from the Domains
to ARM specific Firmware (for example SCMI). This will allow the devices,
passed-through to the different Domains, to access to the System resources
(such as clocks/resets etc) by sending requests to the firmware.

ARM SCI subsystem allows to implement different SCI drivers to handle
specific ARM firmware interfaces (like ARM SCMI) and mediate requests
-between the Domains and the Firmware. Also it allows SCI drivers to perfor=
m
proper action during Domain creation/destruction which is vital for
handling use cases like Domain reboot.

This patch introduces new DEVICE_FIRMWARE device subclass for probing SCI
drivers basing on device tree, SCI drivers register itself with
DT_DEVICE_START/END macro. On init - the SCI drivers should register its
SCI ops with sci_register(). Only one SCI driver can be supported.

At run-time, the following SCI API calls are introduced:

- sci_domain_sanitise_config() called from arch_sanitise_domain_config()
- sci_domain_init() called from arch_domain_create()
- sci_relinquish_resources() called from domain_relinquish_resources()
- sci_domain_destroy() called from arch_domain_destroy()
- sci_handle_call() called from vsmccc_handle_call()
- sci_dt_handle_node()
- sci_dt_finalize() called from handle_node() (Dom0 DT)

Signed-off-by: Oleksii Moisieiev 
Signed-off-by: Grygorii Strashko 
Reviewed-by: Stefano Stabellini 
---

Changes in v6:
- rebase on top of the latest master
- fix return value of sci_dt_finalize() call

Changes in v5:
- update Maintainers file. Set role as a Reviewer
- rebased on the latest master branch
- Introduce arch_handle_passthrough_prop call to handle arm specific nodes

Changes in v4:
- fix SPDX-License
- rename DEVICE_ARM_SCI DT device class to FIRMWARE_DEVICE
- move XEN_DOMCTL_assign_device code in separate patch
- Add documentation for SCI SCMI drivers

 MAINTAINERS                             |   6 +
 xen/arch/arm/device.c                   |   5 +
 xen/arch/arm/dom0less-build.c           |   8 +
 xen/arch/arm/domain.c                   |  12 +-
 xen/arch/arm/domain_build.c             |   8 +
 xen/arch/arm/firmware/Kconfig           |   8 +
 xen/arch/arm/firmware/Makefile          |   1 +
 xen/arch/arm/firmware/sci.c             | 154 ++++++++++++++++++
 xen/arch/arm/include/asm/domain.h       |   5 +
 xen/arch/arm/include/asm/firmware/sci.h | 200 ++++++++++++++++++++++++
 xen/arch/arm/vsmc.c                     |   3 +
 xen/common/device-tree/dom0less-build.c |   4 +
 xen/include/asm-generic/device.h        |   1 +
 xen/include/public/arch-arm.h           |   4 +
 xen/include/xen/dom0less-build.h        |   9 ++
 15 files changed, 427 insertions(+), 1 deletion(-)
 create mode 100644 xen/arch/arm/firmware/sci.c
 create mode 100644 xen/arch/arm/include/asm/firmware/sci.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c4886c1159..31dbba54bb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -509,6 +509,12 @@ R:	George Dunlap 
 S:	Supported
 F:	xen/common/sched/
=20
+SCI MEDIATORS
+R:	Oleksii Moisieiev 
+S:	Supported
+F:	xen/arch/arm/firmware/sci.c
+F:	xen/arch/arm/include/asm/firmware/sci.h
+
 SEABIOS UPSTREAM
 M:	Wei Liu 
 S:	Supported
diff --git a/xen/arch/arm/device.c b/xen/arch/arm/device.c
index 11523750ae..74b54cad34 100644
--- a/xen/arch/arm/device.c
+++ b/xen/arch/arm/device.c
@@ -13,6 +13,7 @@
 #include 
 #include 
=20
+#include 
 #include 
=20
 int map_irq_to_domain(struct domain *d, unsigned int irq,
@@ -303,6 +304,10 @@ int handle_device(struct domain *d, struct dt_device_n=
ode *dev, p2m_type_t p2mt,
                 return res;
             }
         }
+
+        res =3D sci_assign_dt_device(d, dev);
+        if ( res )
+            return res;
     }
=20
     res =3D map_device_irqs_to_domain(d, dev, own_device, irq_ranges);
diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index c8d07213e2..0094cf9e40 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -22,6 +22,7 @@
=20
 #include 
 #include 
+#include 
 #include 
 #include 
=20
@@ -272,6 +273,12 @@ int __init init_vuart(struct domain *d, struct kernel_=
info *kinfo,
     return rc;
 }
=20
+int __init arch_handle_passthrough_prop(struct kernel_info *kinfo,
+                                        struct dt_device_node *node)
+{
+    return sci_assign_dt_device(kinfo->bd.d, node);
+}
+
 int __init arch_parse_dom0less_node(struct dt_device_node *node,
                                     struct boot_domain *bd)
 {
@@ -281,6 +288,7 @@ int __init arch_parse_dom0less_node(struct dt_device_no=
de *node,
=20
     d_cfg->arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
     d_cfg->flags |=3D XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap;
+    d_cfg->arch.arm_sci_type =3D XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
=20
     if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) )
     {
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 310c578909..0f9db7a2d5 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -699,7 +700,7 @@ int arch_sanitise_domain_config(struct xen_domctl_creat=
edomain *config)
         return -EINVAL;
     }
=20
-    return 0;
+    return sci_domain_sanitise_config(config);
 }
=20
 int arch_domain_create(struct domain *d,
@@ -791,6 +792,9 @@ int arch_domain_create(struct domain *d,
     d->arch.sve_vl =3D config->arch.sve_vl;
 #endif
=20
+    if ( (rc =3D sci_domain_init(d, config)) !=3D 0 )
+        goto fail;
+
     return 0;
=20
 fail:
@@ -851,6 +855,7 @@ void arch_domain_destroy(struct domain *d)
     domain_vgic_free(d);
     domain_vuart_free(d);
     free_xenheap_page(d->shared_info);
+    sci_domain_destroy(d);
 #ifdef CONFIG_ACPI
     free_xenheap_pages(d->arch.efi_acpi_table,
                        get_order_from_bytes(d->arch.efi_acpi_len));
@@ -1044,6 +1049,7 @@ enum {
     PROG_p2m_root,
     PROG_p2m,
     PROG_p2m_pool,
+    PROG_sci,
     PROG_done,
 };
=20
@@ -1103,6 +1109,10 @@ int domain_relinquish_resources(struct domain *d)
         ret =3D relinquish_p2m_mapping(d);
         if ( ret )
             return ret;
+    PROGRESS(sci):
+        ret =3D sci_relinquish_resources(d);
+        if ( ret )
+            return ret;
=20
     PROGRESS(p2m_root):
         /*
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index a9e4153e3c..039aa71439 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1640,6 +1641,9 @@ static int __init handle_node(struct domain *d, struc=
t kernel_info *kinfo,
         return 0;
     }
=20
+    if ( sci_dt_handle_node(d, node) )
+        return 0;
+
     /*
      * The vGIC does not support routing hardware PPIs to guest. So
      * we need to skip any node using PPIs.
@@ -1740,6 +1744,10 @@ static int __init handle_node(struct domain *d, stru=
ct kernel_info *kinfo,
         if ( res )
             return res;
=20
+        res =3D sci_dt_finalize(d, kinfo->fdt);
+        if ( res )
+            return res;
+
         /*
          * Create a second memory node to store the ranges covering
          * reserved-memory regions.
diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig
index 817da745fd..fc7918c7fc 100644
--- a/xen/arch/arm/firmware/Kconfig
+++ b/xen/arch/arm/firmware/Kconfig
@@ -1,3 +1,11 @@
+config ARM_SCI
+	bool
+	depends on ARM
+	help
+	  This option enables generic Arm SCI (System Control Interface) mediator=
s
+	  support. It allows domains to control system resources via one of
+	  Arm SCI mediators drivers implemented in XEN, like SCMI.
+
 menu "Firmware Drivers"
=20
 config SCMI_SMC
diff --git a/xen/arch/arm/firmware/Makefile b/xen/arch/arm/firmware/Makefil=
e
index a5e4542666..71bdefc24a 100644
--- a/xen/arch/arm/firmware/Makefile
+++ b/xen/arch/arm/firmware/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_ARM_SCI) +=3D sci.o
 obj-$(CONFIG_SCMI_SMC) +=3D scmi-smc.o
diff --git a/xen/arch/arm/firmware/sci.c b/xen/arch/arm/firmware/sci.c
new file mode 100644
index 0000000000..e1522e10e2
--- /dev/null
+++ b/xen/arch/arm/firmware/sci.c
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Generic part of the SCI (System Control Interface) subsystem.
+ *
+ * Oleksii Moisieiev 
+ * Copyright (c) 2025 EPAM Systems
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+static const struct sci_mediator_ops __read_mostly *cur_mediator;
+
+int sci_register(const struct sci_mediator_ops *ops)
+{
+    if ( cur_mediator )
+        return -EEXIST;
+
+    if ( !ops->domain_init || !ops->domain_destroy || !ops->handle_call )
+        return -EINVAL;
+
+    cur_mediator =3D ops;
+
+    return 0;
+};
+
+bool sci_handle_call(struct cpu_user_regs *args)
+{
+    if ( unlikely(!cur_mediator) )
+        return false;
+
+    return cur_mediator->handle_call(args);
+}
+
+int sci_domain_init(struct domain *d, struct xen_domctl_createdomain *conf=
ig)
+{
+    if ( !cur_mediator )
+        return 0;
+
+    return cur_mediator->domain_init(d, config);
+}
+
+int sci_domain_sanitise_config(struct xen_domctl_createdomain *config)
+{
+    if ( !cur_mediator )
+        return 0;
+
+    if ( !cur_mediator->domain_sanitise_config )
+        return 0;
+
+    return cur_mediator->domain_sanitise_config(config);
+}
+
+void sci_domain_destroy(struct domain *d)
+{
+    if ( !cur_mediator )
+        return;
+
+    cur_mediator->domain_destroy(d);
+}
+
+int sci_relinquish_resources(struct domain *d)
+{
+    if ( !cur_mediator )
+        return 0;
+
+    if ( !cur_mediator->relinquish_resources )
+        return 0;
+
+    return cur_mediator->relinquish_resources(d);
+}
+
+bool sci_dt_handle_node(struct domain *d, struct dt_device_node *node)
+{
+    if ( !cur_mediator )
+        return 0;
+
+    if ( !cur_mediator->dom0_dt_handle_node )
+        return 0;
+
+    return cur_mediator->dom0_dt_handle_node(d, node);
+}
+
+int sci_dt_finalize(struct domain *d, void *fdt)
+{
+    if ( !cur_mediator )
+        return 0;
+
+    if ( !cur_mediator->dom0_dt_finalize )
+        return 0;
+
+    return cur_mediator->dom0_dt_finalize(d, fdt);
+}
+
+int sci_assign_dt_device(struct domain *d, struct dt_device_node *dev)
+{
+    struct dt_phandle_args ac_spec;
+    int index =3D 0;
+    int ret;
+
+    if ( !cur_mediator )
+        return 0;
+
+    if ( !cur_mediator->assign_dt_device )
+        return 0;
+
+    while ( !dt_parse_phandle_with_args(dev, "access-controllers",
+                                        "#access-controller-cells", index,
+                                        &ac_spec) )
+    {
+        printk(XENLOG_DEBUG "sci: assign device %s to %pd\n",
+               dt_node_full_name(dev), d);
+
+        ret =3D cur_mediator->assign_dt_device(d, &ac_spec);
+        if ( ret )
+            return ret;
+
+        index++;
+    }
+
+    return 0;
+}
+
+static int __init sci_init(void)
+{
+    struct dt_device_node *np;
+    unsigned int num_sci =3D 0;
+    int rc;
+
+    dt_for_each_device_node(dt_host, np)
+    {
+        rc =3D device_init(np, DEVICE_FIRMWARE, NULL);
+        if ( !rc && num_sci )
+        {
+            printk(XENLOG_ERR
+                   "SCMI: Only one SCI controller is supported. found seco=
nd %s\n",
+                   np->name);
+            return -EOPNOTSUPP;
+        }
+        else if ( !rc )
+            num_sci++;
+        else if ( rc !=3D -EBADF && rc !=3D -ENODEV )
+            return rc;
+    }
+
+    return 0;
+}
+
+__initcall(sci_init);
diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d=
omain.h
index a3487ca713..af3e168374 100644
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -120,6 +120,11 @@ struct arch_domain
 #ifdef CONFIG_TEE
     void *tee;
 #endif
+#ifdef CONFIG_ARM_SCI
+    bool sci_enabled;
+    /* ARM SCI driver's specific data */
+    void *sci_data;
+#endif
=20
 }  __cacheline_aligned;
=20
diff --git a/xen/arch/arm/include/asm/firmware/sci.h b/xen/arch/arm/include=
/asm/firmware/sci.h
new file mode 100644
index 0000000000..1b9a5c0c07
--- /dev/null
+++ b/xen/arch/arm/include/asm/firmware/sci.h
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Generic ARM SCI (System Control Interface) subsystem.
+ *
+ * Oleksii Moisieiev 
+ * Copyright (c) 2025 EPAM Systems
+ */
+
+#ifndef __ASM_ARM_SCI_H
+#define __ASM_ARM_SCI_H
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_ARM_SCI
+
+struct sci_mediator_ops {
+    /*
+     * Called during domain construction. If it is requested to enable
+     * SCI support, so SCI driver can create own structures for the new do=
main
+     * and inform firmware about new domain (if required).
+     * Mandatory.
+     */
+    int (*domain_init)(struct domain *d,
+                       struct xen_domctl_createdomain *config);
+
+    /*
+     * Called during domain construction. The SCI driver uses
+     * it to sanitize domain SCI configuration parameters.
+     * Optional.
+     */
+    int (*domain_sanitise_config)(struct xen_domctl_createdomain *config);
+
+    /*
+     * Called during domain destruction, releases all resources, that
+     * were allocated for domain.
+     * Mandatory.
+     */
+    void (*domain_destroy)(struct domain *d);
+
+    /*
+     * Called during domain destruction to relinquish resources used
+     * by SCI driver itself and request resources releasing from firmware.
+     * Optional.
+     */
+    int (*relinquish_resources)(struct domain *d);
+
+    /* SMC/HVC Handle callback */
+    bool (*handle_call)(struct cpu_user_regs *regs);
+
+    /*
+     * Dom0 DT nodes handling callback so SCI driver can detect DT nodes i=
t
+     * need to handle and decide if those nodes need to be provided to Dom=
0.
+     * Optional.
+     */
+    bool (*dom0_dt_handle_node)(struct domain *d, struct dt_device_node *n=
ode);
+
+    /*
+     * SCI driver callback called at the end of Dom0 DT generation, so
+     * it can perform steps to modify DT to enable/disable SCI
+     * functionality for Dom0.
+     */
+    int (*dom0_dt_finalize)(struct domain *d, void *fdt);
+
+    /*
+     * SCI driver callback called when DT device is passed through to gues=
t,
+     * so SCI driver can enable device access to the domain if SCI FW prov=
ides
+     * Device specific access control functionality.
+     * Optional.
+     */
+    int (*assign_dt_device)(struct domain *d, struct dt_phandle_args *ac_s=
pec);
+};
+
+
+static inline bool sci_domain_is_enabled(struct domain *d)
+{
+    return d->arch.sci_enabled;
+}
+
+/*
+ * Register SCI subsystem ops.
+ *
+ * Register SCI drivers operation and so enable SCI functionality.
+ * Only one SCI driver is supported.
+ */
+int sci_register(const struct sci_mediator_ops *ops);
+
+/*
+ * Initialize SCI functionality for domain if configured.
+ *
+ * Initialization routine to enable SCI functionality for the domain.
+ * The SCI configuration data and decision about enabling SCI functionalit=
y
+ * for the domain is SCI driver specific.
+ */
+int sci_domain_init(struct domain *d, struct xen_domctl_createdomain *conf=
ig);
+
+/*
+ * Sanitise domain configuration parameters.
+ *
+ */
+int sci_domain_sanitise_config(struct xen_domctl_createdomain *config);
+
+/*
+ * Destroy SCI domain instance.
+ */
+void sci_domain_destroy(struct domain *d);
+
+/*
+ * Free resources assigned to the certain domain.
+ */
+int sci_relinquish_resources(struct domain *d);
+
+/*
+ * SMC/HVC Handle callback.
+ *
+ * SCI driver acts as SMC/HVC server for the registered domains and
+ * does redirection of the domain calls to the SCI firmware,
+ * such as ARM TF-A or similar.
+ */
+bool sci_handle_call(struct cpu_user_regs *regs);
+
+/*
+ * Dom0 DT nodes handling function.
+ *
+ * Allows SCI driver to detect DT nodes it need to handle and decide if
+ * those nodes need to be provided to Dom0.
+ */
+bool sci_dt_handle_node(struct domain *d, struct dt_device_node *node);
+
+/*
+ * Dom0 DT generation finalize.
+ *
+ * Called at the end of Dom0 DT generation, so SCI driver can perform step=
s
+ * to modify DT to enable/disable SCI functionality for Dom0.
+ */
+int sci_dt_finalize(struct domain *d, void *fdt);
+
+/*
+ * Assign DT device to domain.
+ *
+ * Called when DT device is passed through to guest, so SCI driver can ena=
ble
+ * device access to the domain if SCI FW provides "Device specific access
+ * control" functionality.
+ */
+int sci_assign_dt_device(struct domain *d, struct dt_device_node *dev);
+#else
+
+static inline bool sci_domain_is_enabled(struct domain *d)
+{
+    return false;
+}
+
+static inline int sci_domain_init(struct domain *d,
+                                  struct xen_domctl_createdomain *config)
+{
+    return 0;
+}
+
+static inline int
+sci_domain_sanitise_config(struct xen_domctl_createdomain *config)
+{
+    return 0;
+}
+
+static inline void sci_domain_destroy(struct domain *d)
+{}
+
+static inline int sci_relinquish_resources(struct domain *d)
+{
+    return 0;
+}
+
+static inline bool sci_handle_call(struct cpu_user_regs *args)
+{
+    return false;
+}
+
+static inline bool sci_dt_handle_node(struct domain *d,
+                                      struct dt_device_node *node)
+{
+    return false;
+}
+
+static inline int sci_dt_finalize(struct domain *d, void *fdt)
+{
+    return 0;
+}
+
+static inline int sci_assign_dt_device(struct domain *d,
+                                       struct dt_device_node *dev)
+{
+    return 0;
+}
+
+#endif /* CONFIG_ARM_SCI */
+
+#endif /* __ASM_ARM_SCI_H */
diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c
index 6081f14ed0..2469738fcc 100644
--- a/xen/arch/arm/vsmc.c
+++ b/xen/arch/arm/vsmc.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -300,6 +301,8 @@ static bool vsmccc_handle_call(struct cpu_user_regs *re=
gs)
             break;
         case ARM_SMCCC_OWNER_SIP:
             handled =3D handle_sip(regs);
+            if ( !handled )
+                handled =3D sci_handle_call(regs);
             break;
         case ARM_SMCCC_OWNER_TRUSTED_APP ... ARM_SMCCC_OWNER_TRUSTED_APP_E=
ND:
         case ARM_SMCCC_OWNER_TRUSTED_OS ... ARM_SMCCC_OWNER_TRUSTED_OS_END=
:
diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tr=
ee/dom0less-build.c
index badc227031..aaa5e9b22c 100644
--- a/xen/common/device-tree/dom0less-build.c
+++ b/xen/common/device-tree/dom0less-build.c
@@ -228,6 +228,10 @@ static int __init handle_passthrough_prop(struct kerne=
l_info *kinfo,
     if ( res < 0 )
         return res;
=20
+    res =3D arch_handle_passthrough_prop(kinfo, node);
+    if ( res )
+        return res;
+
     /* If xen_force, we allow assignment of devices without IOMMU protecti=
on. */
     if ( xen_force && !dt_device_is_protected(node) )
         return 0;
diff --git a/xen/include/asm-generic/device.h b/xen/include/asm-generic/dev=
ice.h
index 3bd97e33c5..cb13f7faea 100644
--- a/xen/include/asm-generic/device.h
+++ b/xen/include/asm-generic/device.h
@@ -18,6 +18,7 @@ enum device_class
     DEVICE_IOMMU,
     DEVICE_INTERRUPT_CONTROLLER,
     DEVICE_PCI_HOSTBRIDGE,
+    DEVICE_FIRMWARE,
     /* Use for error */
     DEVICE_UNKNOWN,
 };
diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index 24840eeaa6..55eed9992c 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -327,6 +327,8 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
 #define XEN_DOMCTL_CONFIG_TEE_OPTEE     1
 #define XEN_DOMCTL_CONFIG_TEE_FFA       2
=20
+#define XEN_DOMCTL_CONFIG_ARM_SCI_NONE      0
+
 struct xen_arch_domainconfig {
     /* IN/OUT */
     uint8_t gic_version;
@@ -350,6 +352,8 @@ struct xen_arch_domainconfig {
      *
      */
     uint32_t clock_frequency;
+    /* IN */
+    uint8_t arm_sci_type;
 };
 #endif /* __XEN__ || __XEN_TOOLS__ */
=20
diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-bu=
ild.h
index 408859e325..6fdd0552e0 100644
--- a/xen/include/xen/dom0less-build.h
+++ b/xen/include/xen/dom0less-build.h
@@ -62,6 +62,9 @@ void set_domain_type(struct domain *d, struct kernel_info=
 *kinfo);
 int init_intc_phandle(struct kernel_info *kinfo, const char *name,
                       const int node_next, const void *pfdt);
=20
+int arch_handle_passthrough_prop(struct kernel_info *kinfo,
+                                 struct dt_device_node *node);
+
 #else /* !CONFIG_DOM0LESS_BOOT */
=20
 static inline void create_domUs(void) {}
@@ -71,6 +74,12 @@ static inline bool is_dom0less_mode(void)
 }
 static inline void set_xs_domain(struct domain *d) {}
=20
+static inline int arch_handle_passthrough_prop(struct kernel_info *kinfo,
+                                               struct dt_device_node *node=
)
+{
+    return 0;
+}
+
 #endif /* CONFIG_DOM0LESS_BOOT */
=20
 #endif /* __ASM_GENERIC_DOM0LESS_BUILD_H__ */
--=20
2.34.1


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From: Oleksii Moisieiev 
To: "xen-devel@lists.xenproject.org" 
CC: Andrew Cooper , Anthony PERARD
	, Bertrand Marquis , Jan
 Beulich , Juergen Gross , Julien Grall
	, Michal Orzel , Oleksii Moisieiev
	, =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini ,
	Volodymyr Babchuk , Grygorii Strashko
	
Subject: [PATCH v6 4/4] docs: arm: add docs for SCMI over SMC calls forwarding
 driver
Thread-Topic: [PATCH v6 4/4] docs: arm: add docs for SCMI over SMC calls
 forwarding driver
Thread-Index: AQHcGDp0tfvhJciRvkCRbdqW7TfbXw==
Date: Thu, 28 Aug 2025 16:40:26 +0000
Message-ID:
 <17e009a131e54ad68f0a182b1766d333cf1c63f8.1756399156.git.oleksii_moisieiev@epam.com>
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From: Grygorii Strashko 

Add documentation section for Simple Arm SCMI over SMC calls forwarding
driver (EL3).

Signed-off-by: Grygorii Strashko 
Signed-off-by: Oleksii Moisieiev 
---

Changes in v6:
- add link to the scmi bindings used in the doc
- remove mentions about HVC calls from doc
- rename cmdline parameter to scmi-smc-passthrough

Changes in v5:
- rename dom0_scmi_smc_passthrough in documentation

 .../arm/firmware/arm-scmi.rst                 | 180 ++++++++++++++++++
 docs/hypervisor-guide/arm/index.rst           |   9 +
 docs/hypervisor-guide/index.rst               |   1 +
 3 files changed, 190 insertions(+)
 create mode 100644 docs/hypervisor-guide/arm/firmware/arm-scmi.rst
 create mode 100644 docs/hypervisor-guide/arm/index.rst

diff --git a/docs/hypervisor-guide/arm/firmware/arm-scmi.rst b/docs/hypervi=
sor-guide/arm/firmware/arm-scmi.rst
new file mode 100644
index 0000000000..4394c95431
--- /dev/null
+++ b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
@@ -0,0 +1,180 @@
+.. SPDX-License-Identifier: CC-BY-4.0
+
+ARM System Control and Management Interface (SCMI)
+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D
+
+The System Control and Management Interface (SCMI) [1], which is a set of =
operating
+system-independent software interfaces that are used in system management.=
 SCMI currently
+provides interfaces for:
+
+- Discovery and self-description of the interfaces it supports
+- Power domain management
+- Clock management
+- Reset domain management
+- Voltage domain management
+- Sensor management
+- Performance management
+- Power capping and monitoring
+- Pin control protocol.
+
+The SCMI compliant firmware could run:
+
+- as part of EL3 secure world software (like Trusted Firmware-A) with
+  ARM SMC shared-memory transport;
+- on dedicated System Control Processor (SCP) with HW mailbox shared-memor=
y transport
+
+The major purpose of enabling SCMI support in Xen is to enable guest domai=
ns access to the SCMI
+interfaces for performing management actions on passed-through devices (su=
ch as clocks/resets etc)
+without accessing directly to the System control HW (like clock controller=
s) which in most cases
+can't shared/split between domains. Or, at minimum, allow SCMI access for =
dom0/hwdom (or guest
+domain serving as Driver domain).
+
+The below sections describe SCMI support options available for Xen.
+
+| [1] `Arm SCMI `=
_
+| [2] `System Control and Management Interface (SCMI) bindings `_
+
+Simple SCMI over SMC calls forwarding driver (EL3)
+------------------------------------------------------
+
+The EL3 SCMI firmware (TF-A) with a single SCMI OSPM agent support is pret=
ty generic case for
+the default vendors SDK and new platforms with SCMI support. Such EL3 SCMI=
 firmware supports only
+single SCMI OSPM transport (agent) with Shared memory based transport and =
SMC calls as doorbell.
+
+The SCMI over SMC calls forwarding driver solves major problem for this ca=
se by allowing
+SMC calls to be forwarded form guest to the EL3 SCMI firmware.
+
+By default, the SCMI over SMC calls forwarding is enabled for Dom0/hwdom.
+
+::
+
+    +--------------------------+
+    |                          |
+    | EL3 SCMI FW (TF-A)       |
+    ++-------+--^--------------+
+     |shmem  |  | smc-id
+     +----^--+  |
+          |     |
+     +----|-+---+---+----------+
+     |    | |  FWD  |      Xen |
+     |    | +---^---+          |
+     +----|-----|--------------+
+          |     | smc-id
+     +----v-----+--+ +---------+
+     |             | |         |
+     | Dom0/hwdom  | | DomU    |
+     |             | |         |
+     |             | |         |
+     +-------------+ +---------+
+
+
+The SCMI messages are passed directly through SCMI shared-memory (zero-cop=
y) and driver only
+forwards SMC calls.
+
+Compiling
+^^^^^^^^^
+
+To build with the SCMI over SMC calls forwarding enabled support, enable K=
config option
+
+::
+
+    CONFIG_SCMI_SMC
+
+The ``CONFIG_SCMI_SMC`` is enabled by default.
+
+Pass-through SCMI SMC to domain which serves as Driver domain
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+This section describes how to configure the SCMI over SMC calls forwarding=
 driver to handle use
+case "thin Dom0 with guest domain, which serves as Driver domain". In this=
 case HW need to be
+enabled in Driver domain and dom0 is performing only control functions (wi=
thout accessing FW) and so,
+the SCMI need to be enabled in Driver domain.
+
+::
+
+     +--------------------------+
+     |EL3 SCMI FW (TF-A)        |
+     |                          |
+     +-------------^--+-------+-+
+             smc-id|  |shmem0 |
+                   |  +----^--+
+    +-------------++------+|----+
+    |Xen          |  FWD  ||    |
+    |             +--^----+|    |
+    +----------------|-----|----+
+              smc-id |     |
+    +-----------+ +--+-----v-----+
+    |           | |              |
+    | Dom0      | |    Driver    |
+    | Control   | |    domain    |
+    |           | |              |
+    +-----------+ +--------------+
+
+The SCMI can be enabled for one and only one guest domain.
+
+First. configure Dom0 to enable SCMI pass-through using Xen Command Line
+**"scmi-smc-passthrough"** option. This will disable SCMI for Dom0/hwdom a=
nd SCMI nodes will
+be removed from Dom0/hwdom device tree.
+
+**Configure SCMI pass-through for guest domain with toolstack**
+
+* In domain's xl.cfg file add **"arm_sci"** option as below
+
+::
+
+    arm_sci =3D "type=3Dscmi_smc"
+
+* In domain's xl.cfg file enable access to the "arm,scmi-shmem"
+
+::
+
+    iomem =3D [
+        "47ff0,1@22001",
+    ]
+
+.. note:: It's up to the user to select guest IPA for mapping SCMI shared-=
memory.
+
+* Add SCMI nodes to the Driver domain partial device tree as in the below =
example:
+
+.. code::
+
+    passthrough {
+       scmi_shm_0: sram@22001000 {
+           compatible =3D "arm,scmi-shmem";
+           reg =3D <0x0 0x22001000 0x0 0x1000>;
+       };
+
+       firmware {
+            compatible =3D "simple-bus";
+                scmi: scmi {
+                    compatible =3D "arm,scmi-smc";
+                    shmem =3D <&scmi_shm_0>;
+                    ...
+                }
+        }
+    }
+
+Please refer to [2] for details of SCMI DT bindings.
+
+In general, the configuration is similar to any other HW pass-through, exc=
ept explicitly
+enabling SCMI with "arm_sci" xl.cfg option.
+
+**Configure SCMI pass-through for predefined domain (dom0less)**
+
+* add "xen,sci_type" property for required DomU ("xen,domain") node
+
+::
+
+       xen,sci_type=3D"scmi_smc"
+
+* add scmi nodes to the Driver domain partial device tree the same way as =
above and enable access
+  to the "arm,scmi-shmem" according to  dom0less documentation. For exampl=
e:
+
+.. code::
+
+      scmi_shm_0: sram@22001000 {
+            compatible =3D "arm,scmi-shmem";
+            reg =3D <0x00 0x22001000 0x00 0x1000>;
+    ->        xen,reg =3D <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
+    ->        xen,force-assign-without-iommu;
+      };
diff --git a/docs/hypervisor-guide/arm/index.rst b/docs/hypervisor-guide/ar=
m/index.rst
new file mode 100644
index 0000000000..7aae4a0a03
--- /dev/null
+++ b/docs/hypervisor-guide/arm/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: CC-BY-4.0
+
+ARM
+=3D=3D=3D
+
+.. toctree::
+   :maxdepth: 2
+
+   firmware/arm-scmi
diff --git a/docs/hypervisor-guide/index.rst b/docs/hypervisor-guide/index.=
rst
index e4393b0697..520fe01554 100644
--- a/docs/hypervisor-guide/index.rst
+++ b/docs/hypervisor-guide/index.rst
@@ -9,3 +9,4 @@ Hypervisor documentation
    code-coverage
=20
    x86/index
+   arm/index
\ No newline at end of file
--=20
2.34.1


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From: Oleksii Moisieiev 
To: "xen-devel@lists.xenproject.org" 
CC: Andrew Cooper , Anthony PERARD
	, Bertrand Marquis , Jan
 Beulich , Juergen Gross , Julien Grall
	, Michal Orzel , Oleksii Moisieiev
	, =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Stefano Stabellini ,
	Volodymyr Babchuk , Grygorii Strashko
	
Subject: [PATCH v6 0/4] xen/arm: scmi: introduce SCI SCMI SMC single-agent
 support
Thread-Topic: [PATCH v6 0/4] xen/arm: scmi: introduce SCI SCMI SMC
 single-agent support
Thread-Index: AQHcGDpz564/CxWJjkScJHSOCdJ/3w==
Date: Thu, 28 Aug 2025 16:40:24 +0000
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Inroducing V6 patch series  on top of the Xen version 4.20-rc2
which includes implementation of the SCI SCMI SMC single-agent support.

This patch series is the first chunk of the
"xen/arm: scmi: introduce SCI SCMI SMC multi-agent support" which can
be found at [0]

SCMI-multiagent support will be provided as the followup patch series.

[0] https://lore.kernel.org/xen-devel/cover.1753184487.git.oleksii_moisieie=
v@epam.com/

Patch 1 "xen/arm: add generic SCI subsystem"
- rebased and refactored
- introduced DEVICE_ARM_SCI DT device class and used for SCI drivers probin=
g
instead of custom,
  linker sections based implementation.
- added SCI API for Dom0 DT handling, instead of manipulating with ARM arch
dom0 code directly.
- RFC changes in XEN_DOMCTL_assign_device OP processing
- Introduce arch_handle_passthrough_prop call to handle arm specific
nodes

Patch 2 "xen/arm: scmi-smc: update to be used under sci subsystem"
- update driver introduced by commit 3e322bef8bc0 ("xen/arm: firmware: Add =
SCMI
over SMC calls
handling layer") be used under sci subsystem.
- no functional changes in general

Patch 3 "xen/arm: scmi-smc: passthrough SCMI SMC to guest domain
This is new change which allows passthrough SCMI SMC, single agent interfac=
e to
guest domain
cover use case "thin Dom0 with guest domain, which serves as Driver domain"=
.
See patch commit message for full description.

Patch 4 - docs: arm: add docs for SCMI over SMC calls forwarding
driver
- add documentation section for Simple Arm SCMI over SMC calls
forwarding driver.

Code can be found at:
https://github.com/oleksiimoisieiev/xen/tree/scmi_upstrv5

[1] RFC v2:
http://patchwork.kernel.org/project/xen-devel/cover/cover.1644341635.git.ol=
eksii_moisieiev@epam.com/
[2] RFC v3:
https://patchwork.kernel.org/project/xen-devel/patch/20250311111618.1850927=
-1-grygorii_strashko@epam.com
SCMI spec:
https://developer.arm.com/documentation/den0056/e/?lang=3Den

SCMI bindings:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree=
/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree=
/Documentation/devicetree/bindings/access-controllers/access-controllers.ya=
ml

Reference EL3 FW:
RPI5: https://github.com/xen-troops/arm-trusted-firmware/commits/rpi5_dev/
Renesas v4h:
https://github.com/GrygiriiS/arm-trusted-firmware/commits/rcar_gen4_v2.7_v4=
x-scmi_upd/

base-commit: dbe60f244c (Update Xen to 4.21, 2025-02-21)

Changes in v6:
- rebase on top of the latest master
- fix return value of sci_dt_finalize() call
- add R-b tag
- added generated helpers and types go files
- rename cmdline parameter to scmi-smc-passthrough
- fix goto tag in parse_arm_sci_config
- add link to the scmi bindings used in the doc
- remove mentions about HVC calls from doc
- rename cmdline parameter to scmi-smc-passthrough

Changes in v5:
- update Maintainers file. Set role as a Reviewer
- rebased on the latest master branch
- Introduce arch_handle_passthrough_prop call to handle arm specific nodes
- rename dom0_scmi_smc_passthrough to scmi_smc_passthrough
- rename dom0_scmi_smc_passthrough in documentation

Changes in v4:
- fix SPDX-License
- rename DEVICE_ARM_SCI DT device class to FIRMWARE_DEVICE
- move XEN_DOMCTL_assign_device code in separate patch
- Add documentation for SCI SCMI drivers
- xl.cfg doc
- fix comments from Stefano Stabellini
- fix toolstack code as sugested by Anthony PERARD
  - use MATCH_OPTION()
  - move arm_sci struct and cfg params in "arch_arm"
- add SCMI passthrough for dom0less case

Grygorii Strashko (3):
  xen/arm: scmi-smc: update to be used under sci subsystem
  xen/arm: scmi-smc: passthrough SCMI SMC to domain, single agent
  docs: arm: add docs for SCMI over SMC calls forwarding driver

Oleksii Moisieiev (1):
  xen/arm: add generic SCI subsystem

 MAINTAINERS                                   |   6 +
 .../arm/firmware/arm-scmi.rst                 | 180 ++++++++++++++++
 docs/hypervisor-guide/arm/index.rst           |   9 +
 docs/hypervisor-guide/index.rst               |   1 +
 docs/man/xl.cfg.5.pod.in                      |  34 +++
 docs/misc/arm/device-tree/booting.txt         |  15 ++
 docs/misc/xen-command-line.pandoc             |   9 +
 tools/golang/xenlight/helpers.gen.go          |  41 ++++
 tools/golang/xenlight/types.gen.go            |  12 ++
 tools/include/libxl.h                         |   5 +
 tools/libs/light/libxl_arm.c                  |  14 ++
 tools/libs/light/libxl_types.idl              |  10 +
 tools/xl/xl_parse.c                           |  36 ++++
 xen/arch/arm/device.c                         |   5 +
 xen/arch/arm/dom0less-build.c                 |  40 ++++
 xen/arch/arm/domain.c                         |  12 +-
 xen/arch/arm/domain_build.c                   |   8 +
 xen/arch/arm/firmware/Kconfig                 |  25 ++-
 xen/arch/arm/firmware/Makefile                |   1 +
 xen/arch/arm/firmware/sci.c                   | 154 ++++++++++++++
 xen/arch/arm/firmware/scmi-smc.c              | 191 +++++++++++++----
 xen/arch/arm/include/asm/domain.h             |   5 +
 xen/arch/arm/include/asm/firmware/sci.h       | 200 ++++++++++++++++++
 xen/arch/arm/include/asm/firmware/scmi-smc.h  |  41 ----
 xen/arch/arm/vsmc.c                           |   4 +-
 xen/common/device-tree/dom0less-build.c       |   4 +
 xen/include/asm-generic/device.h              |   1 +
 xen/include/public/arch-arm.h                 |   5 +
 xen/include/xen/dom0less-build.h              |   9 +
 29 files changed, 992 insertions(+), 85 deletions(-)
 create mode 100644 docs/hypervisor-guide/arm/firmware/arm-scmi.rst
 create mode 100644 docs/hypervisor-guide/arm/index.rst
 create mode 100644 xen/arch/arm/firmware/sci.c
 create mode 100644 xen/arch/arm/include/asm/firmware/sci.h
 delete mode 100644 xen/arch/arm/include/asm/firmware/scmi-smc.h

--=20
2.34.1


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From: Leonid Komarianskyi 
To: Oleksii Kurochko ,
	"xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Community Manager
	
Subject: Re: [PATCH v3 11/11] CHANGELOG.md: add mention of GICv3.1 eSPI
 support
Thread-Topic: [PATCH v3 11/11] CHANGELOG.md: add mention of GICv3.1 eSPI
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Date: Thu, 28 Aug 2025 16:45:03 +0000
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Date: Thu, 28 Aug 2025 19:54:27 +0300
From: Leon Romanovsky 
To: Keith Busch 
Cc: Marek Szyprowski ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
Message-ID: <20250828165427.GB10073@unreal>
References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
 
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In-Reply-To: 

On Thu, Aug 28, 2025 at 09:19:20AM -0600, Keith Busch wrote:
> On Tue, Aug 19, 2025 at 08:36:59PM +0300, Leon Romanovsky wrote:
> > diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
> > index 09b99d52fd36..283058bcb5b1 100644
> > --- a/include/linux/blk_types.h
> > +++ b/include/linux/blk_types.h
> > @@ -387,6 +387,7 @@ enum req_flag_bits {
> >  	__REQ_FS_PRIVATE,	/* for file system (submitter) use */
> >  	__REQ_ATOMIC,		/* for atomic write operations */
> >  	__REQ_P2PDMA,		/* contains P2P DMA pages */
> > +	__REQ_MMIO,		/* contains MMIO memory */
> >  	/*
> >  	 * Command specific flags, keep last:
> >  	 */
> > @@ -420,6 +421,7 @@ enum req_flag_bits {
> >  #define REQ_FS_PRIVATE	(__force blk_opf_t)(1ULL << __REQ_FS_PRIVATE)
> >  #define REQ_ATOMIC	(__force blk_opf_t)(1ULL << __REQ_ATOMIC)
> >  #define REQ_P2PDMA	(__force blk_opf_t)(1ULL << __REQ_P2PDMA)
> > +#define REQ_MMIO	(__force blk_opf_t)(1ULL << __REQ_MMIO)
> 
> Now that my integrity metadata DMA series is staged, I don't think we
> can use REQ flags like this because data and metadata may have different
> mapping types. I think we should add a flags field to the dma_iova_state
> instead.

Before integrity metadata code was merged, the assumption was that request is
only one type or p2p or host. Is it still holding now?

And we can't store in dma_iova_state() as HMM/RDMA code works in page-based
granularity and one dma_iova_state() can mix different types.

Thanks

> 


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Date: Thu, 28 Aug 2025 11:15:20 -0600
From: Keith Busch 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Jason Gunthorpe ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
Message-ID: 
References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
 
 <20250828165427.GB10073@unreal>
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On Thu, Aug 28, 2025 at 07:54:27PM +0300, Leon Romanovsky wrote:
> On Thu, Aug 28, 2025 at 09:19:20AM -0600, Keith Busch wrote:
> > On Tue, Aug 19, 2025 at 08:36:59PM +0300, Leon Romanovsky wrote:
> > > diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
> > > index 09b99d52fd36..283058bcb5b1 100644
> > > --- a/include/linux/blk_types.h
> > > +++ b/include/linux/blk_types.h
> > > @@ -387,6 +387,7 @@ enum req_flag_bits {
> > >  	__REQ_FS_PRIVATE,	/* for file system (submitter) use */
> > >  	__REQ_ATOMIC,		/* for atomic write operations */
> > >  	__REQ_P2PDMA,		/* contains P2P DMA pages */
> > > +	__REQ_MMIO,		/* contains MMIO memory */
> > >  	/*
> > >  	 * Command specific flags, keep last:
> > >  	 */
> > > @@ -420,6 +421,7 @@ enum req_flag_bits {
> > >  #define REQ_FS_PRIVATE	(__force blk_opf_t)(1ULL << __REQ_FS_PRIVATE)
> > >  #define REQ_ATOMIC	(__force blk_opf_t)(1ULL << __REQ_ATOMIC)
> > >  #define REQ_P2PDMA	(__force blk_opf_t)(1ULL << __REQ_P2PDMA)
> > > +#define REQ_MMIO	(__force blk_opf_t)(1ULL << __REQ_MMIO)
> > 
> > Now that my integrity metadata DMA series is staged, I don't think we
> > can use REQ flags like this because data and metadata may have different
> > mapping types. I think we should add a flags field to the dma_iova_state
> > instead.
> 
> Before integrity metadata code was merged, the assumption was that request is
> only one type or p2p or host. Is it still holding now?

I don't think that was ever the case. Metadata is allocated
independently of the data payload, usually by the kernel in
bio_integrity_prep() just before dispatching the request. The bio may
have a p2p data payload, but the integrity metadata is just a kmalloc
buf in that path.

> And we can't store in dma_iova_state() as HMM/RDMA code works in page-based
> granularity and one dma_iova_state() can mix different types.

I see.


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Subject: Re: [PATCH v2 3/5] symbols: arrange to know where functions end
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On 2025-08-28 12:11, Jan Beulich wrote:
> On 28.08.2025 09:28, Jan Beulich wrote:
>> On 28.08.2025 03:03, Jason Andryuk wrote:
>>> On 2025-04-02 09:58, Jan Beulich wrote:
>>>> --- a/xen/tools/symbols.c
>>>> +++ b/xen/tools/symbols.c
>>>
>>>> @@ -318,24 +334,42 @@ static void write_src(void)
>>>>    	printf("#else\n");
>>>>    	output_label("symbols_offsets");
>>>>    	printf("#endif\n");
>>>> -	for (i = 0; i < table_cnt; i++) {
>>>> +	for (i = 0, ends = 0; i < table_cnt; i++) {
>>>>    		printf("\tPTR\t%#llx - SYMBOLS_ORIGIN\n", table[i].addr);
>>>> +
>>>> +		table[i].addr_idx = i + ends;
>>>> +
>>>> +		if (!want_symbol_end(i)) {
>>>> +			/* If there's another symbol at the same address,
>>>> +			 * propagate this symbol's size if the next one has
>>>> +			 * no size, or if the next one's size is larger. */
>>>
>>> Why do we want to shrink the next symbol's size?
>>
>> First (see related post-commit-message remarks): In principle section symbols
>> could come with a size, too. That would break everything as long as we don't
>> strip those.
>>
>> The main reason though is that imo smallest granularity is what we want here,
>> together with predictability. One symbol with a huge size could cover
>> multiple other symbols with smaller sizes. We could omit that part of the
>> change here, but then the processing in the hypervisor would need to change,
>> to fish out the "best suitable" symbol when dealing with multiple ones at the
>> same address. Other changes may then also be needed to the tool, to have such
>> symbols come in a well-defined order (to keep the then-new code in the
>> hypervisor as simple as possible). Look for "aliased symbol" in
>> common/symbols.c to see how simplistic respective code is right now.
> 
> Furthermore remember that we can't record sizes, but instead we insert fake
> symbols. Obviously there can be only one (at least in the present scheme).
> If we used too large a size, chances would increase that the end symbol (in
> the sorted table) would have to live past some other symbol, thus becoming
> that one's "end".

The scenario I thought about is something like:

a 0x100-0x10f
b 0x100-0x1ff
c 0x200-0x2ff

If you shrink b, you are creating a hole that would otherwise be 
assigned to b.

But I agree avoiding huge sizes covering multiple small variables would 
better be avoided.

Do you have concrete examples to help illustrate the problem?

Regards,
Jason


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Subject: Re: [PATCH v4 08/12] xen/arm: vgic: add resource management for
 extended SPIs
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <9e8a11b024833c1b91b8806e7708bf35b04a8f6e.1756317702.git.leonid_komarianskyi@epam.com>
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From: Oleksandr Tyshchenko 
In-Reply-To: <9e8a11b024833c1b91b8806e7708bf35b04a8f6e.1756317702.git.leonid_komarianskyi@epam.com>
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On 27.08.25 21:24, Leonid Komarianskyi wrote:

Hello Leonid

> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
> requested by the guest. A new field, ext_shared_irqs, is added
> to the VGIC structure to store information about eSPIs, similar
> to how shared_irqs is used for regular SPIs.
> 
> Since the eSPI range starts at INTID 4096 and INTIDs between 1025
> and 4095 are reserved, helper macros are introduced to simplify the
> transformation of indices and to enable easier access to eSPI-specific
> resources. These changes prepare the VGIC for processing eSPIs as
> required by future functionality.
> 
> The initialization and deinitialization paths for vgic have been updated
> to allocate and free these resources appropriately. Additionally,
> updated handling of INTIDs greater than 1024, passed from the toolstack
> during domain creation, and verification logic ensures only valid SPI or
> eSPI INTIDs are used.
> 
> The existing SPI behavior remains unaffected when guests do not request
> eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
> option is disabled.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V4:
> - added has_espi field to simplify determining whether a domain is able
>    to operate with eSPI
> - fixed formatting issues and misspellings
> 
> Changes in V3:
> - fixed formatting for lines with more than 80 symbols
> - introduced helper functions to be able to use stubs in case of
>    CONFIG_GICV3_ESPI disabled, and as a result, reduce the number of
>    #ifdefs
> - fixed checks for nr_spis in domain_vgic_init
> - updated comment about nr_spis adjustments with dom0less mention
> - moved comment with additional explanations before checks
> - used unsigned int for indexes since they cannot be negative
> - removed unnecessary parentheses
> - move vgic_ext_rank_offset to the below ifdef guard, to reduce the
>    number of ifdefs
> 
> Changes in V2:
> - change is_espi_rank to is_valid_espi_rank to verify whether the array
>    element ext_shared_irqs exists. The previous version, is_espi_rank,
>    only checked if the rank index was less than the maximum possible eSPI
>    rank index, but this could potentially result in accessing a
>    non-existing array element. To address this, is_valid_espi_rank was
>    introduced, which ensures that the required eSPI rank exists
> - move gic_number_espis to
>    xen/arm: gicv3: implement handling of GICv3.1 eSPI
> - update vgic_is_valid_irq checks to allow operating with eSPIs
> - remove redundant newline in vgic_allocate_virq
> ---
>   xen/arch/arm/include/asm/vgic.h |  20 +++
>   xen/arch/arm/vgic.c             | 213 +++++++++++++++++++++++++++++++-
>   2 files changed, 230 insertions(+), 3 deletions(-)
> 
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h
> index 3e7cbbb196..fb4cea73eb 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -146,6 +146,12 @@ struct vgic_dist {
>       int nr_spis; /* Number of SPIs */
>       unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
>       struct vgic_irq_rank *shared_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +    struct vgic_irq_rank *ext_shared_irqs;
> +    int nr_espis; /* Number of extended SPIs */

Can nr_espis be negative?

> +    /* To simplify determining whether a domain is able to operate with eSPI */
> +    bool has_espi;

I agree with the Volodymyr's comment provided in separate letter that we 
could avoid adding an extra var.

> +#endif
>       /*
>        * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
>        * struct arch_vcpu.
> @@ -243,6 +249,14 @@ struct vgic_ops {
>   /* Number of ranks of interrupt registers for a domain */
>   #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
>   
> +#ifdef CONFIG_GICV3_ESPI
> +#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
> +#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
> +#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
> +#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
> +#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
> +#endif
> +
>   #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
>   #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
>   
> @@ -302,6 +316,12 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct vcpu *v,
>                                                 unsigned int b,
>                                                 unsigned int n,
>                                                 unsigned int s);
> +#ifdef CONFIG_GICV3_ESPI
> +extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
> +                                                  unsigned int b,
> +                                                  unsigned int n,
> +                                                  unsigned int s);
> +#endif
>   extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int irq);
>   extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
>   extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 2bbf4d99aa..f4b80cb05f 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -27,9 +27,82 @@
>   
>   bool vgic_is_valid_line(struct domain *d, unsigned int virq)
>   {
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( virq >= ESPI_BASE_INTID &&
> +         virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
> +        return true;
> +#endif
> +
>       return virq < vgic_num_irqs(d);
>   }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * Since eSPI indexes start from 4096 and numbers from 1024 to
> + * 4095 are forbidden, we need to check both lower and upper
> + * limits for ranks.
> + */
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
> +{
> +    return rank >= EXT_RANK_MIN &&
> +           EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d);
> +}
> +
> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
> +                                                       unsigned int rank)
> +{
> +    return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)];
> +}
> +
> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int virq)
> +{
> +    return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d),
> +                             d->arch.vgic.allocated_irqs);
> +}
> +
> +static void arch_move_espis(struct vcpu *v)
> +{
> +    const cpumask_t *cpu_mask = cpumask_of(v->processor);
> +    struct domain *d = v->domain;
> +    struct pending_irq *p;
> +    struct vcpu *v_target;
> +    unsigned int i;
> +
> +    for ( i = ESPI_BASE_INTID;
> +          i < EXT_RANK_IDX2NUM(d->arch.vgic.nr_espis); i++ )
> +    {
> +        v_target = vgic_get_target_vcpu(v, i);
> +        p = irq_to_pending(v_target, i);
> +
> +        if ( v_target == v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) )
> +            irq_set_affinity(p->desc, cpu_mask);
> +    }
> +}
> +#else
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
> +{
> +    return false;
> +}
> +
> +/*
> + * This function is stub and will not be called if CONFIG_GICV3_ESPI=n,
> + * because in this case, is_valid_espi_rank will always return false.
> + */
> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
> +                                                       unsigned int rank)
> +{
> +    ASSERT_UNREACHABLE();
> +    return NULL;
> +}
> +
> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int virq)
> +{
> +    return false;
> +}
> +
> +static void arch_move_espis(struct vcpu *v) { }
> +#endif
> +
>   static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>                                                     unsigned int rank)
>   {
> @@ -37,6 +110,8 @@ static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>           return v->arch.vgic.private_irqs;
>       else if ( rank <= DOMAIN_NR_RANKS(v->domain) )
>           return &v->domain->arch.vgic.shared_irqs[rank - 1];
> +    else if ( is_valid_espi_rank(v->domain, rank) )
> +        return vgic_get_espi_rank(v, rank);
>       else
>           return NULL;
>   }
> @@ -117,6 +192,74 @@ int domain_vgic_register(struct domain *d, unsigned int *mmio_count)
>       return 0;
>   }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * The function behavior is the same as for regular SPIs (vgic_rank_offset),
> + * but it operates with extended SPI ranks.
> + */
> +struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int b,
> +                                           unsigned int n, unsigned int s)
> +{
> +    unsigned int rank = REG_RANK_NR(b, (n >> s));
> +
> +    return vgic_get_rank(v, rank + EXT_RANK_MIN);
> +}

So the difference between vgic_rank_offset() and vgic_ext_rank_offset() 
in using EXT_RANK_MIN in the latter. I am wondering, whether it makes 
sense to reuse the existing vgic_rank_offset() by moving #ifdef into it? 
Maybe it would be possible to optimize some code added in "[PATCH v4 
10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers".

e.g. __vgic_v3_distr_common_mmio_read:

Code for the following cases looks very similar to the regular counterparts.
case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):

The difference is in the said helper and the base calculated as
"reg - GICD_XXX", where GICD_XXX is the start of the range for the 
eSPI-based reg (e.g. GICD_IPRIORITYRnE) or regular SPI-based reg 
(e.g.GICD_IPRIORITYR). The GICD_XXX could probably be chosen
based on the "reg" value itself, for example:

rank = vgic_rank_offset(v, 8, reg >= GICD_IPRIORITYRnE ? reg - 
GICD_IPRIORITYRnE : reg - GICD_IPRIORITYR, DABT_WORD);

Please note, I am not requesting for any updates regarding to that, I am 
just thinking out loud.


> +
> +static unsigned int vgic_num_spi_lines(struct domain *d)
> +{
> +    return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
> +}
> +
> +static int init_vgic_espi(struct domain *d)
> +{
> +    unsigned int i, idx;
> +
> +    if ( d->arch.vgic.nr_espis == 0 )
> +        return 0;
> +
> +    d->arch.vgic.ext_shared_irqs =
> +        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
> +    if ( d->arch.vgic.ext_shared_irqs == NULL )
> +        return -ENOMEM;
> +
> +    for ( i = d->arch.vgic.nr_spis, idx = 0;
> +          i < vgic_num_spi_lines(d); i++, idx++ )
> +        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i],
> +                              ESPI_IDX2INTID(idx));
> +
> +    for ( i = 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
> +        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
> +
> +    return 0;
> +}
> +
> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
> +{
> +    irq = ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
> +    return &d->arch.vgic.pending_irqs[irq];
> +}
> +#else
> +static unsigned int init_vgic_espi(struct domain *d
> +{
> +    return 0;
> +}
> +
> +static unsigned int vgic_num_spi_lines(struct domain *d)
> +{
> +    return d->arch.vgic.nr_spis;
> +}
> +
> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
> +{
> +    return NULL;
> +}
> +#endif
> +
> +static unsigned int vgic_num_alloc_irqs(struct domain *d)
> +{
> +    return vgic_num_spi_lines(d) + NR_LOCAL_IRQS;
> +}
> +
>   int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>   {
>       int i;
> @@ -131,6 +274,38 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>        */
>       nr_spis = ROUNDUP(nr_spis, 32);
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    /*
> +     * During domain creation, the dom0less DomUs code or toolstack specifies
> +     * the maximum INTID, which is defined in the domain config subtracted by
> +     * 32 to cover the local IRQs (please see the comment to VGIC_DEF_NR_SPIS).
> +     * To compute the actual number of eSPI that will be usable for,
> +     * add back 32.
> +     */
> +    if ( nr_spis + 32 > ESPI_IDX2INTID(NR_ESPI_IRQS) )
> +        return -EINVAL;
> +
> +    if ( nr_spis + 32 >= ESPI_BASE_INTID )
> +    {
> +        d->arch.vgic.nr_espis = min(nr_spis - ESPI_BASE_INTID + 32, 1024U);
> +        /* Verify if GIC HW can handle provided INTID */
> +        if ( d->arch.vgic.nr_espis > gic_number_espis() )
> +            return -EINVAL;
> +        /*
> +         * Set the maximum available number for regular
> +         * SPI to pass the next check
> +         */
> +        nr_spis = VGIC_DEF_NR_SPIS;
> +        d->arch.vgic.has_espi = true;
> +    }
> +    else
> +    {
> +        /* Domain will use the regular SPI range */
> +        d->arch.vgic.nr_espis = 0;
> +        d->arch.vgic.has_espi = false;
> +    }
> +#endif
> +
>       /* Limit the number of virtual SPIs supported to (1020 - 32) = 988  */
>       if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
>           return -EINVAL;
> @@ -145,7 +320,7 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>           return -ENOMEM;
>   
>       d->arch.vgic.pending_irqs =
> -        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
> +        xzalloc_array(struct pending_irq, vgic_num_spi_lines(d));
>       if ( d->arch.vgic.pending_irqs == NULL )
>           return -ENOMEM;
>   
> @@ -156,12 +331,16 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>       for ( i = 0; i < DOMAIN_NR_RANKS(d); i++ )
>           vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
>   
> +    ret = init_vgic_espi(d);
> +    if ( ret )
> +        return ret;
> +
>       ret = d->arch.vgic.handler->domain_init(d);
>       if ( ret )
>           return ret;
>   
>       d->arch.vgic.allocated_irqs =
> -        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
> +        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_alloc_irqs(d)));
>       if ( !d->arch.vgic.allocated_irqs )
>           return -ENOMEM;
>   
> @@ -195,9 +374,27 @@ void domain_vgic_free(struct domain *d)
>           }
>       }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i = 0; i < d->arch.vgic.nr_espis; i++ )
> +    {
> +        struct pending_irq *p = spi_to_pending(d, ESPI_IDX2INTID(i));
> +
> +        if ( p->desc )
> +        {
> +            ret = release_guest_irq(d, p->irq);
> +            if ( ret )
> +                dprintk(XENLOG_G_WARNING, "d%u: Failed to release virq %u ret = %d\n",


NIT: you can use %pd for printing domain with its ID


> +                        d->domain_id, p->irq, ret);
> +        }
> +    }
> +#endif
> +
>       if ( d->arch.vgic.handler )
>           d->arch.vgic.handler->domain_free(d);
>       xfree(d->arch.vgic.shared_irqs);
> +#ifdef CONFIG_GICV3_ESPI
> +    xfree(d->arch.vgic.ext_shared_irqs);
> +#endif
>       xfree(d->arch.vgic.pending_irqs);
>       xfree(d->arch.vgic.allocated_irqs);
>   }
> @@ -331,6 +528,8 @@ void arch_move_irqs(struct vcpu *v)
>           if ( v_target == v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) )
>               irq_set_affinity(p->desc, cpu_mask);
>       }
> +
> +    arch_move_espis(v);
>   }
>   
>   void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
> @@ -538,6 +737,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq)
>           n = &v->arch.vgic.pending_irqs[irq];
>       else if ( is_lpi(irq) )
>           n = v->domain->arch.vgic.handler->lpi_to_pending(v->domain, irq);
> +    else if ( is_espi(irq) )
> +        n = espi_to_pending(v->domain, irq);
>       else
>           n = &v->domain->arch.vgic.pending_irqs[irq - 32];
>       return n;
> @@ -547,6 +748,9 @@ struct pending_irq *spi_to_pending(struct domain *d, unsigned int irq)
>   {
>       ASSERT(irq >= NR_LOCAL_IRQS);
>   
> +    if ( is_espi(irq) )
> +        return espi_to_pending(d, irq);
> +
>       return &d->arch.vgic.pending_irqs[irq - 32];
>   }
>   
> @@ -668,6 +872,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned int virq)
>       if ( !vgic_is_valid_line(d, virq) )
>           return false;
>   
> +    if ( is_espi(virq) )
> +        return vgic_reserve_espi_virq(d, virq);
> +
>       return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
>   }
>   
> @@ -685,7 +892,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
>       else
>       {
>           first = 32;
> -        end = vgic_num_irqs(d);
> +        end = vgic_num_alloc_irqs(d);
>       }
>   
>       /*



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Message-ID: 
Date: Thu, 28 Aug 2025 21:39:18 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v4 04/12] xen/arm/irq: add handling for IRQs in the eSPI
 range
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 
Content-Language: en-US
From: Oleksandr Tyshchenko 
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On 27.08.25 21:24, Leonid Komarianskyi wrote:


Hello Leonid

> Currently, Xen does not support eSPI interrupts, leading
> to a data abort when such interrupts are defined in the DTS.
> 
> This patch introduces a separate array to initialize up to
> 1024 interrupt descriptors in the eSPI range and adds the
> necessary defines and helper function. These changes lay the
> groundwork for future implementation of full eSPI interrupt
> support. As this GICv3.1 feature is not required by all vendors,
> all changes are guarded by ifdefs, depending on the corresponding
> Kconfig option.
> 
> Signed-off-by: Leonid Komarianskyi 
> Reviewed-by: Volodymyr Babchuk 
> 
> ---
> Changes in V4:
> - removed redundant line with 'default n' in Kconfig, as it is disabled
>    by default, without explicit specification
> - added reviewed-by from Volodymyr Babchuk


only NITs below

Reviewed-by: Oleksandr Tyshchenko 

> 
> Changes in V3:
> - introduced a new define NR_ESPI_IRQS to avoid confusion, like in the
>    case of using NR_IRQS for espi_desc array
> - implemented helper functions espi_to_desc and init_espi_data to make
>    it possible to add stubs with the same name, and as a result, reduce
>    the number of #ifdefs
> - disable CONFIG_GICV3_ESPI default value to n
> 
> Changes in V2:
> - use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
> - remove unnecessary comment for nr_irqs initialization
> ---
>   xen/arch/arm/Kconfig           |  8 ++++++
>   xen/arch/arm/include/asm/irq.h | 26 +++++++++++++++++
>   xen/arch/arm/irq.c             | 52 +++++++++++++++++++++++++++++++++-
>   3 files changed, 85 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index 17df147b25..43b05533b1 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -135,6 +135,14 @@ config GICV3
>   	  Driver for the ARM Generic Interrupt Controller v3.
>   	  If unsure, use the default setting.
>   
> +config GICV3_ESPI
> +	bool "Extended SPI range support"
> +	depends on GICV3 && !NEW_VGIC
> +	help
> +	  Allow Xen and domains to use interrupt numbers from the extended SPI
> +	  range, from 4096 to 5119. This feature is introduced in GICv3.1
> +	  architecture.
> +
>   config HAS_ITS
>           bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORTED
>           depends on GICV3 && !NEW_VGIC && !ARM_32
> diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.h
> index 5bc6475eb4..221dbf23a2 100644
> --- a/xen/arch/arm/include/asm/irq.h
> +++ b/xen/arch/arm/include/asm/irq.h
> @@ -32,6 +32,15 @@ struct arch_irq_desc {
>   #define SPI_MAX_INTID   1019
>   #define LPI_OFFSET      8192
>   
> +#ifdef CONFIG_GICV3_ESPI
> +#define ESPI_BASE_INTID 4096
> +#define ESPI_MAX_INTID  5119
> +#define NR_ESPI_IRQS    1024
> +
> +#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
> +#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
> +#endif
> +
>   /* LPIs are always numbered starting at 8192, so 0 is a good invalid case. */
>   #define INVALID_LPI     0
>   
> @@ -39,7 +48,15 @@ struct arch_irq_desc {
>   #define INVALID_IRQ     1023
>   
>   extern const unsigned int nr_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * This will also cover the eSPI range, as some critical devices
> + * for booting Xen (e.g., serial) may use this type of interrupts.
> + */
> +#define nr_static_irqs (ESPI_MAX_INTID + 1)
> +#else
>   #define nr_static_irqs NR_IRQS
> +#endif
>   
>   struct irq_desc;
>   struct irqaction;
> @@ -55,6 +72,15 @@ static inline bool is_lpi(unsigned int irq)
>       return irq >= LPI_OFFSET;
>   }
>   
> +static inline bool is_espi(unsigned int irq)
> +{
> +#ifdef CONFIG_GICV3_ESPI
> +    return (irq >= ESPI_BASE_INTID && irq <= ESPI_MAX_INTID);
> +#else
> +    return false;
> +#endif
> +}
> +
>   #define domain_pirq_to_irq(d, pirq) (pirq)
>   
>   bool is_assignable_irq(unsigned int irq);
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index b8eccfc924..adb5e49ea3 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -19,7 +19,11 @@
>   #include 
>   #include 
>   
> +#ifdef CONFIG_GICV3_ESPI
> +const unsigned int nr_irqs = ESPI_MAX_INTID + 1;
> +#else
>   const unsigned int nr_irqs = NR_IRQS;
> +#endif
>   
>   static unsigned int local_irqs_type[NR_LOCAL_IRQS];
>   static DEFINE_SPINLOCK(local_irqs_type_lock);
> @@ -46,6 +50,49 @@ void irq_end_none(struct irq_desc *irq)
>   }
>   
>   static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
> +#ifdef CONFIG_GICV3_ESPI
> +static irq_desc_t espi_desc[NR_ESPI_IRQS];

NIT: I would write "TODO: Consider allocating an array dynamically if
there is a need to enable GICV3_ESPI by default". But it is up to you.

> +
> +static struct irq_desc *espi_to_desc(unsigned int irq)
> +{
> +    return &espi_desc[ESPI_INTID2IDX(irq)];
> +}
> +
> +static int __init init_espi_data(void)
> +{
> +    int irq;

NIT: please use unsigned int


> +
> +    for ( irq = ESPI_BASE_INTID; irq <= ESPI_MAX_INTID; irq++ )
> +    {
> +        struct irq_desc *desc = irq_to_desc(irq);
> +        int rc = init_one_irq_desc(desc);
> +
> +        if ( rc )
> +            return rc;
> +
> +        desc->irq = irq;
> +        desc->action  = NULL;
> +    }
> +
> +    return 0;
> +}

[snip]



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Date: Thu, 28 Aug 2025 15:41:15 -0300
From: Jason Gunthorpe 
To: Keith Busch 
Cc: Leon Romanovsky ,
	Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
Message-ID: <20250828184115.GE7333@nvidia.com>
References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
 
 <20250828165427.GB10073@unreal>
 
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On Thu, Aug 28, 2025 at 11:15:20AM -0600, Keith Busch wrote:
> On Thu, Aug 28, 2025 at 07:54:27PM +0300, Leon Romanovsky wrote:
> > On Thu, Aug 28, 2025 at 09:19:20AM -0600, Keith Busch wrote:
> > > On Tue, Aug 19, 2025 at 08:36:59PM +0300, Leon Romanovsky wrote:
> > > > diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
> > > > index 09b99d52fd36..283058bcb5b1 100644
> > > > --- a/include/linux/blk_types.h
> > > > +++ b/include/linux/blk_types.h
> > > > @@ -387,6 +387,7 @@ enum req_flag_bits {
> > > >  	__REQ_FS_PRIVATE,	/* for file system (submitter) use */
> > > >  	__REQ_ATOMIC,		/* for atomic write operations */
> > > >  	__REQ_P2PDMA,		/* contains P2P DMA pages */
> > > > +	__REQ_MMIO,		/* contains MMIO memory */
> > > >  	/*
> > > >  	 * Command specific flags, keep last:
> > > >  	 */
> > > > @@ -420,6 +421,7 @@ enum req_flag_bits {
> > > >  #define REQ_FS_PRIVATE	(__force blk_opf_t)(1ULL << __REQ_FS_PRIVATE)
> > > >  #define REQ_ATOMIC	(__force blk_opf_t)(1ULL << __REQ_ATOMIC)
> > > >  #define REQ_P2PDMA	(__force blk_opf_t)(1ULL << __REQ_P2PDMA)
> > > > +#define REQ_MMIO	(__force blk_opf_t)(1ULL << __REQ_MMIO)
> > > 
> > > Now that my integrity metadata DMA series is staged, I don't think we
> > > can use REQ flags like this because data and metadata may have different
> > > mapping types. I think we should add a flags field to the dma_iova_state
> > > instead.
> > 
> > Before integrity metadata code was merged, the assumption was that request is
> > only one type or p2p or host. Is it still holding now?
> 
> I don't think that was ever the case. Metadata is allocated
> independently of the data payload, usually by the kernel in
> bio_integrity_prep() just before dispatching the request. The bio may
> have a p2p data payload, but the integrity metadata is just a kmalloc
> buf in that path.

Then you should do two dma mapping operations today, that is how the
API was built. You shouldn't mix P2P and non P2P within a single
operation right now..

Jason


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In-Reply-To: 
From: Mykola Kvach 
Date: Thu, 28 Aug 2025 21:59:26 +0300
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Message-ID: 
Subject: Re: [PATCH v10 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Jan Beulich 
Cc: Mykola Kvach , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , Volodymyr Babchuk , 
	Andrew Cooper , Anthony PERARD , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	xen-devel@lists.xenproject.org
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Hi Jan,

I have completely changed the implementation so that the common parts
of the code are almost untouched. Therefore, there is no longer a need
to address the previous issues with comments and other concerns.

Thank you for your review. Please take a look at the new version of
this patch series. I hope there are no issues remaining.

On Thu, Aug 28, 2025 at 10:40=E2=80=AFAM Jan Beulich  wr=
ote:
>
> On 27.08.2025 23:21, Mykola Kvach wrote:
> > --- a/xen/common/domain.c
> > +++ b/xen/common/domain.c
> > @@ -1349,16 +1349,10 @@ int domain_shutdown(struct domain *d, u8 reason=
)
> >      return 0;
> >  }
> >
> > -void domain_resume(struct domain *d)
> > +static void domain_resume_nopause(struct domain *d)
> >  {
> >      struct vcpu *v;
> >
> > -    /*
> > -     * Some code paths assume that shutdown status does not get reset =
under
> > -     * their feet (e.g., some assertions make this assumption).
> > -     */
> > -    domain_pause(d);
> > -
> >      spin_lock(&d->shutdown_lock);
> >
> >      d->is_shutting_down =3D d->is_shut_down =3D 0;
> > @@ -1366,13 +1360,40 @@ void domain_resume(struct domain *d)
> >
> >      for_each_vcpu ( d, v )
> >      {
> > +        /*
> > +         * No need to conditionally clear _VPF_suspended here:
> > +         * - This bit is only set on Arm, and only after a successful =
suspend.
>
> How likely do you think it is that, if e.g. RISC-V or PPC clone Arm's
> code, this comment would then be updated accordingly? IOW I don't think
> a justification like this one should be written in such terms.
>
> > +         * - domain_resume_nopause() may also be called from paths oth=
er than
> > +         *   the suspend/resume flow, such as "soft-reset" actions (e.=
g.,
> > +         *   on_poweroff), as part of the Xenstore control/shutdown pr=
otocol.
> > +         *   These require guest acknowledgement to complete the opera=
tion.
>
> I'm having trouble connecting "require guest acknowledgement" to ...
>
> > +         * So clearing the bit unconditionally is safe.
>
> ... the safety of the unconditional clearing.
>
> > +         */
> > +        clear_bit(_VPF_suspended, &v->pause_flags);
> > +
> >          if ( v->paused_for_shutdown )
> >              vcpu_unpause(v);
> >          v->paused_for_shutdown =3D 0;
> >      }
> >
> >      spin_unlock(&d->shutdown_lock);
> > +}
> >
> > +#ifdef CONFIG_ARM
> > +void domain_resume_nopause_helper(struct domain *d)
>
> This is an odd name to use from code meaning to invoke domain_resume_nopa=
use().
> Why isn't this called domain_resume_nopause(), and ...
>
> > +{
> > +    domain_resume_nopause(d);
>
> ... the static function simply _domain_resume_nopause() (in full accordan=
ce
> to the C standard's naming rules)?
>
> > +}
> > +#endif
> > +
> > +void domain_resume(struct domain *d)
> > +{
> > +    /*
> > +     * Some code paths assume that shutdown status does not get reset =
under
> > +     * their feet (e.g., some assertions make this assumption).
> > +     */
> > +    domain_pause(d);
>
> As you move the comment - no such assumptions exist when the code path
> through domain_resume_nopause_helper() is taken?
>
> Jan

Best regards,
Mykola


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From: Leonid Komarianskyi 
To: Oleksandr Tyshchenko ,
	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v4 08/12] xen/arm: vgic: add resource management for
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Thread-Topic: [PATCH v4 08/12] xen/arm: vgic: add resource management for
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Date: Thu, 28 Aug 2025 13:10:32 -0600
From: Keith Busch 
To: Jason Gunthorpe 
Cc: Leon Romanovsky ,
	Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
Message-ID: 
References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
 
 <20250828165427.GB10073@unreal>
 
 <20250828184115.GE7333@nvidia.com>
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In-Reply-To: <20250828184115.GE7333@nvidia.com>

On Thu, Aug 28, 2025 at 03:41:15PM -0300, Jason Gunthorpe wrote:
> On Thu, Aug 28, 2025 at 11:15:20AM -0600, Keith Busch wrote:
> > 
> > I don't think that was ever the case. Metadata is allocated
> > independently of the data payload, usually by the kernel in
> > bio_integrity_prep() just before dispatching the request. The bio may
> > have a p2p data payload, but the integrity metadata is just a kmalloc
> > buf in that path.
> 
> Then you should do two dma mapping operations today, that is how the
> API was built. You shouldn't mix P2P and non P2P within a single
> operation right now..

Data and metadata are mapped as separate operations. They're just
different parts of one blk-mq request.


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Date: Thu, 28 Aug 2025 16:18:20 -0300
From: Jason Gunthorpe 
To: Keith Busch 
Cc: Leon Romanovsky ,
	Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
Message-ID: <20250828191820.GH7333@nvidia.com>
References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
 
 <20250828165427.GB10073@unreal>
 
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On Thu, Aug 28, 2025 at 01:10:32PM -0600, Keith Busch wrote:
> On Thu, Aug 28, 2025 at 03:41:15PM -0300, Jason Gunthorpe wrote:
> > On Thu, Aug 28, 2025 at 11:15:20AM -0600, Keith Busch wrote:
> > > 
> > > I don't think that was ever the case. Metadata is allocated
> > > independently of the data payload, usually by the kernel in
> > > bio_integrity_prep() just before dispatching the request. The bio may
> > > have a p2p data payload, but the integrity metadata is just a kmalloc
> > > buf in that path.
> > 
> > Then you should do two dma mapping operations today, that is how the
> > API was built. You shouldn't mix P2P and non P2P within a single
> > operation right now..
> 
> Data and metadata are mapped as separate operations. They're just
> different parts of one blk-mq request.

In that case the new bit leon proposes should only be used for the
unmap of the data pages and the metadata unmap should always be
unmapped as CPU?

Jason


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Date: Thu, 28 Aug 2025 14:54:35 -0600
From: Keith Busch 
To: Jason Gunthorpe 
Cc: Leon Romanovsky ,
	Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
Message-ID: 
References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
 
 <20250828165427.GB10073@unreal>
 
 <20250828184115.GE7333@nvidia.com>
 
 <20250828191820.GH7333@nvidia.com>
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In-Reply-To: <20250828191820.GH7333@nvidia.com>

On Thu, Aug 28, 2025 at 04:18:20PM -0300, Jason Gunthorpe wrote:
> On Thu, Aug 28, 2025 at 01:10:32PM -0600, Keith Busch wrote:
> > 
> > Data and metadata are mapped as separate operations. They're just
> > different parts of one blk-mq request.
> 
> In that case the new bit leon proposes should only be used for the
> unmap of the data pages and the metadata unmap should always be
> unmapped as CPU?

The common path uses host allocated memory to attach integrity metadata,
but that isn't the only path. A user can attach their own metadata with
nvme passthrough or the recent io_uring application metadata, and that
could have been allocated from anywhere.

In truth though, I hadn't tried p2p metadata before today, and it looks
like bio_integrity_map_user() is missing the P2P extraction flags to
make that work. Just added this patch below, now I can set p2p or host
memory independently for data and integrity payloads:

---
diff --git a/block/bio-integrity.c b/block/bio-integrity.c
index 6b077ca937f6b..cf45603e378d5 100644
--- a/block/bio-integrity.c
+++ b/block/bio-integrity.c
@@ -265,6 +265,7 @@ int bio_integrity_map_user(struct bio *bio, struct iov_iter *iter)
 	unsigned int align = blk_lim_dma_alignment_and_pad(&q->limits);
 	struct page *stack_pages[UIO_FASTIOV], **pages = stack_pages;
 	struct bio_vec stack_vec[UIO_FASTIOV], *bvec = stack_vec;
+	iov_iter_extraction_t extraction_flags = 0;
 	size_t offset, bytes = iter->count;
 	unsigned int nr_bvecs;
 	int ret, nr_vecs;
@@ -286,7 +287,12 @@ int bio_integrity_map_user(struct bio *bio, struct iov_iter *iter)
 	}
 
 	copy = !iov_iter_is_aligned(iter, align, align);
-	ret = iov_iter_extract_pages(iter, &pages, bytes, nr_vecs, 0, &offset);
+
+	if (blk_queue_pci_p2pdma(q))
+		extraction_flags |= ITER_ALLOW_P2PDMA;
+
+	ret = iov_iter_extract_pages(iter, &pages, bytes, nr_vecs,
+					extraction_flags, &offset);
 	if (unlikely(ret < 0))
 		goto free_bvec;
 
--


From xen-devel-bounces@lists.xenproject.org Thu Aug 28 21:31:59 2025
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Date: Thu, 28 Aug 2025 14:31:42 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [PATCH v6 1/4] xen/arm: add generic SCI subsystem
In-Reply-To: 
Message-ID: 
References:  
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On Thu, 28 Aug 2025, Oleksii Moisieiev wrote:
> This patch adds the basic framework for ARM SCI mediator. SCI is System
> Control Interface, which is designed to redirect requests from the Domains
> to ARM specific Firmware (for example SCMI). This will allow the devices,
> passed-through to the different Domains, to access to the System resources
> (such as clocks/resets etc) by sending requests to the firmware.
> 
> ARM SCI subsystem allows to implement different SCI drivers to handle
> specific ARM firmware interfaces (like ARM SCMI) and mediate requests
> -between the Domains and the Firmware. Also it allows SCI drivers to perform
> proper action during Domain creation/destruction which is vital for
> handling use cases like Domain reboot.
> 
> This patch introduces new DEVICE_FIRMWARE device subclass for probing SCI
> drivers basing on device tree, SCI drivers register itself with
> DT_DEVICE_START/END macro. On init - the SCI drivers should register its
> SCI ops with sci_register(). Only one SCI driver can be supported.
> 
> At run-time, the following SCI API calls are introduced:
> 
> - sci_domain_sanitise_config() called from arch_sanitise_domain_config()
> - sci_domain_init() called from arch_domain_create()
> - sci_relinquish_resources() called from domain_relinquish_resources()
> - sci_domain_destroy() called from arch_domain_destroy()
> - sci_handle_call() called from vsmccc_handle_call()
> - sci_dt_handle_node()
> - sci_dt_finalize() called from handle_node() (Dom0 DT)
> 
> Signed-off-by: Oleksii Moisieiev 
> Signed-off-by: Grygorii Strashko 
> Reviewed-by: Stefano Stabellini 

I just want to say that R-b from me is OK


From xen-devel-bounces@lists.xenproject.org Thu Aug 28 21:33:28 2025
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Date: Thu, 28 Aug 2025 14:33:19 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [PATCH v6 2/4] xen/arm: scmi-smc: update to be used under sci
 subsystem
In-Reply-To: <8e7e9dcdd643b6681a6127d56b68536b987141af.1756399156.git.oleksii_moisieiev@epam.com>
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On Thu, 28 Aug 2025, Oleksii Moisieiev wrote:
> From: Grygorii Strashko 
> 
> The introduced SCI (System Control Interface) subsystem provides unified
> interface to integrate in Xen SCI drivers which adds support for ARM
> firmware (EL3, SCP) based software interfaces (like SCMI) that are used in
> system management. The SCI subsystem allows to add drivers for different FW
> interfaces or have different drivers for the same FW interface (for example,
> SCMI with different transports).
> 
> This patch updates SCMI over SMC calls handling layer, introduced by
> commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI over SMC calls handling
> layer"), to be SCI driver:
> - convert to DT device;
> - convert to SCI Xen interface.
> 
> There are no functional changes in general, the driver is just adopted
> to the SCI interface.
> 
> Signed-off-by: Grygorii Strashko 
> Reviewed-by: Stefano Stabellini 

Also I wanted to write down that the R-b is OK from me


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On 2025-08-28 05:17, Jan Beulich wrote:
> The present copy_page_sse2() is useful in case the destination page isn't
> going to get touched again soon, or if we want to limit churn on the
> caches. Just rename it, to fit the corresponding {clear,scrub}_page_*()
> naming scheme.
> 
> For cases where latency is the most important aspect, or when it is
> expected that sufficiently large parts of a destination page will get
> accessed again soon after the copying, introduce a "hot" alternative.
> Again use alternatives patching to select between a "legacy" and an ERMS
> variant.
> 
> Don't switch any callers just yet - this will be the subject of subsequent
> changes.
> 
> Signed-off-by: Jan Beulich 

Reviewed-by: Jason Andryuk 

> ---
> Of course both pages can be independently hot/cold, and hence more flavors
> may be necessary here.
> 
> To avoid the NOP padding (also in clear_page_hot()) we could use a double
> REP prefix in the replacement code (accounting for the REX one in the code
> being replaced).

Did my tool chain do it automatically?

0000000000000000 <.altinstr_replacement>:
    0:	b9 00 10 00 00       	mov    $0x1000,%ecx
    5:	f3 f3 a4             	repz rep movsb %ds:(%rsi),%es:(%rdi)

Regards,
Jason


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Date: Thu, 28 Aug 2025 14:34:32 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [PATCH v6 3/4] xen/arm: scmi-smc: passthrough SCMI SMC to domain,
 single agent
In-Reply-To: <02b79eaa0a611fb43a2146a5f41aec435d3db6c7.1756399156.git.oleksii_moisieiev@epam.com>
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On Thu, 28 Aug 2025, Oleksii Moisieiev wrote:
> From: Grygorii Strashko 
> 
> The commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI over SMC calls
> handling layer") introduces simple driver which forwards SCMI over SMC
> calls from hwdom/dom0 to EL3 firmware (TF-A) with a single SCMI OSPM agent
> support. While it is working gracefully for hwdom/dom0 use case it doesn't
> cover "thin Dom0 with guest domain, which serves as Driver domain"
> use-case. In this case HW need to be enable in Driver domain and dom0 is
> performing only control functions.
> 
> The EL3 SCMI firmware (TF-A) with a single SCMI OSPM agent support is
> pretty generic case for the default vendors SDK and new platforms.
> 
> This patch enables passthrough of SCMI SMC single agent interface to the
> one guest domain serving as Driver domain.
> 
> Configure Dom0 to enable SCMI passthrough:
> 
>  - dom0: add scmi-smc-passthrough to the Xen Command Line
> 
> Enabled SCMI passthrough for guest using toolstack in the following way:
> 
>  - domD: xl.cfg add "arm_sci" option as below
> 
>    arm_sci = "type=scmi_smc"
> 
>  - domD: xl.cfg enable access to the "arm,scmi-shmem"
> 
> iomem = [
>     "47ff0,1@22001",
> ]
> 
>  - domD: add SCMI nodes to the Driver domain partial device tree as in the
>  below example:
> 
> passthrough {
>    scmi_shm_0: sram@22001000 {
>        compatible = "arm,scmi-shmem";
>        reg = <0x0 0x22001000 0x0 0x1000>;
>    };
> 
>    firmware {
>         compatible = "simple-bus";
>             scmi: scmi {
>                 compatible = "arm,scmi-smc";
>                 shmem = <&scmi_shm_0>;
>                 ...
>             }
>     }
> }
> 
> dom0less case configuration:
> 
> - add "xen,sci_type" property for required DomU ("xen,domain") node
> 
>    xen,sci_type="scmi_smc"
> 
> - add scmi nodes to the Driver domain partial device tree the same way
> as above and enable access to the "arm,scmi-shmem" according to
> dom0less documentation. For example:
> 
>   scmi_shm_0: sram@22001000 {
>         compatible = "arm,scmi-shmem";
>         reg = <0x00 0x22001000 0x00 0x1000>;
> ->        xen,reg = <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
> ->        xen,force-assign-without-iommu;
>   };
> 
> The SCMI SMC single agent interface can be enabled for one and only one
> domain. In general, the configuration is similar to any other HW
> passthrough, except explicitly enabling SCMI with "arm_sci" xl.cfg option.
> 
> Note that "arm,scmi-smc" and "arm,scmi-shmem" nodes will be removed from
> dom0/hwdom DT in case of
> 
> Signed-off-by: Grygorii Strashko 
> Signed-off-by: Oleksii Moisieiev 
> Acked-by: Anthony PERARD  # tools

Reviewed-by: Stefano Stabellini 


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From: Mykola Kvach 
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Subject: Re: [PATCH v5] xen/char: implement suspend/resume calls for SCIF driver
To: Oleksandr Tyshchenko 
Cc: xen-devel@lists.xenproject.org, 
	Volodymyr Babchuk , Stefano Stabellini , 
	Julien Grall , Bertrand Marquis , 
	Michal Orzel , 
	Oleksandr Andrushchenko , Mykola Kvach 
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Hi Oleksandr,

Thank you for your review.

On Tue, Aug 26, 2025 at 6:51=E2=80=AFPM Oleksandr Tyshchenko
 wrote:
>
>
>
> On 07.08.25 08:16, Mykola Kvach wrote:
>
>
> Hello Mykola,
>
> In general patch looks good to me, just one question below ...
>
> > From: Volodymyr Babchuk 
> >
> > Implement suspend and resume callbacks for the SCIF UART driver,
> > enabled when CONFIG_SYSTEM_SUSPEND is set. This allows proper
> > handling of UART state across system suspend/resume cycles.
> >
> > Tested on Renesas R-Car H3 Starter Kit.
> >
> > Signed-off-by: Volodymyr Babchuk 
> > Signed-off-by: Oleksandr Andrushchenko 
> > Signed-off-by: Mykola Kvach 
> > ---
> > In patch v5, there are no changes at all;
> > it was done just to trigger a review.
>
> I think, you could ping on V4.
>
>
> >
> > In patch v4, enhance commit message, no functional changes
> >
> > In patch v2, I just added a CONFIG_SYSTEM_SUSPEND check around
> > the suspend/resume functions in the SCIF driver.
> > ---
> >   xen/drivers/char/scif-uart.c | 40 ++++++++++++++++++++++++++++++++++-=
-
> >   1 file changed, 38 insertions(+), 2 deletions(-)
> >
> > diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.=
c
> > index 757793ca45..888821a3b8 100644
> > --- a/xen/drivers/char/scif-uart.c
> > +++ b/xen/drivers/char/scif-uart.c
> > @@ -139,9 +139,8 @@ static void scif_uart_interrupt(int irq, void *data=
)
> >       }
> >   }
> >
> > -static void __init scif_uart_init_preirq(struct serial_port *port)
> > +static void scif_uart_disable(struct scif_uart *uart)
> >   {
> > -    struct scif_uart *uart =3D port->uart;
> >       const struct port_params *params =3D uart->params;
> >
> >       /*
> > @@ -155,6 +154,14 @@ static void __init scif_uart_init_preirq(struct se=
rial_port *port)
> >
> >       /* Reset TX/RX FIFOs */
> >       scif_writew(uart, SCIF_SCFCR, SCFCR_RFRST | SCFCR_TFRST);
> > +}
> > +
> > +static void scif_uart_init_preirq(struct serial_port *port)
> > +{
> > +    struct scif_uart *uart =3D port->uart;
> > +    const struct port_params *params =3D uart->params;
> > +
> > +    scif_uart_disable(uart);
> >
> >       /* Clear all errors and flags */
> >       scif_readw(uart, params->status_reg);
> > @@ -271,6 +278,31 @@ static void scif_uart_stop_tx(struct serial_port *=
port)
> >       scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) & ~SCS=
CR_TIE);
> >   }
> >
> > +#ifdef CONFIG_SYSTEM_SUSPEND
> > +
> > +static void scif_uart_suspend(struct serial_port *port)
> > +{
> > +    struct scif_uart *uart =3D port->uart;
> > +
> > +    scif_uart_stop_tx(port);
>
>   ... I wonder, whether the call above (that disables Transmit
> interrupt) is really needed as the call below disables all interrupts
> anyway?

I have checked the relevant documentation and did not find any requirement
to clear TIE before disabling the rest of the SCSCR bits, according to the
R-Car Series, 3rd Generation User=E2=80=99s Manual: Hardware, Rev. 0.52.

However, based on how the serial subsystem works, I believe this call is
justified.

Disabling TX IRQs before fully stopping the serial prevents new data
from being added to the FIFO by the IRQ handler during suspend (see
serial_tx_interrupt). This ensures the FIFO is flushed (loop inside
scif_uart_disable) and no further transmissions occur.

If a flush handler were implemented for this driver, we could avoid
calling scif_uart_stop_tx and remove the loop inside scif_uart_disable,
as the flush handler would ensure the FIFO is empty after any invocation
of serial_tx_interrupt.

>
>
> > +    scif_uart_disable(uart);
> > +}
>
> [snip]

Best regards,
Mykola


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Date: Thu, 28 Aug 2025 14:38:20 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Oleksii Moisieiev 
cc: "xen-devel@lists.xenproject.org" , 
    Andrew Cooper , 
    Anthony PERARD , 
    Bertrand Marquis , 
    Jan Beulich , Juergen Gross , 
    Julien Grall , Michal Orzel , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Stefano Stabellini , 
    Volodymyr Babchuk , 
    Grygorii Strashko 
Subject: Re: [PATCH v6 4/4] docs: arm: add docs for SCMI over SMC calls
 forwarding driver
In-Reply-To: <17e009a131e54ad68f0a182b1766d333cf1c63f8.1756399156.git.oleksii_moisieiev@epam.com>
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On Thu, 28 Aug 2025, Oleksii Moisieiev wrote:
> From: Grygorii Strashko 
> 
> Add documentation section for Simple Arm SCMI over SMC calls forwarding
> driver (EL3).
> 
> Signed-off-by: Grygorii Strashko 
> Signed-off-by: Oleksii Moisieiev 

We typically wrap lines at 80. It can be done on commit.

Reviewed-by: Stefano Stabellini 


> ---
> 
> Changes in v6:
> - add link to the scmi bindings used in the doc
> - remove mentions about HVC calls from doc
> - rename cmdline parameter to scmi-smc-passthrough
> 
> Changes in v5:
> - rename dom0_scmi_smc_passthrough in documentation
> 
>  .../arm/firmware/arm-scmi.rst                 | 180 ++++++++++++++++++
>  docs/hypervisor-guide/arm/index.rst           |   9 +
>  docs/hypervisor-guide/index.rst               |   1 +
>  3 files changed, 190 insertions(+)
>  create mode 100644 docs/hypervisor-guide/arm/firmware/arm-scmi.rst
>  create mode 100644 docs/hypervisor-guide/arm/index.rst
> 
> diff --git a/docs/hypervisor-guide/arm/firmware/arm-scmi.rst b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> new file mode 100644
> index 0000000000..4394c95431
> --- /dev/null
> +++ b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> @@ -0,0 +1,180 @@
> +.. SPDX-License-Identifier: CC-BY-4.0
> +
> +ARM System Control and Management Interface (SCMI)
> +==================================================
> +
> +The System Control and Management Interface (SCMI) [1], which is a set of operating
> +system-independent software interfaces that are used in system management. SCMI currently
> +provides interfaces for:
> +
> +- Discovery and self-description of the interfaces it supports
> +- Power domain management
> +- Clock management
> +- Reset domain management
> +- Voltage domain management
> +- Sensor management
> +- Performance management
> +- Power capping and monitoring
> +- Pin control protocol.
> +
> +The SCMI compliant firmware could run:
> +
> +- as part of EL3 secure world software (like Trusted Firmware-A) with
> +  ARM SMC shared-memory transport;
> +- on dedicated System Control Processor (SCP) with HW mailbox shared-memory transport
> +
> +The major purpose of enabling SCMI support in Xen is to enable guest domains access to the SCMI
> +interfaces for performing management actions on passed-through devices (such as clocks/resets etc)
> +without accessing directly to the System control HW (like clock controllers) which in most cases
> +can't shared/split between domains. Or, at minimum, allow SCMI access for dom0/hwdom (or guest
> +domain serving as Driver domain).
> +
> +The below sections describe SCMI support options available for Xen.
> +
> +| [1] `Arm SCMI `_
> +| [2] `System Control and Management Interface (SCMI) bindings `_
> +
> +Simple SCMI over SMC calls forwarding driver (EL3)
> +------------------------------------------------------
> +
> +The EL3 SCMI firmware (TF-A) with a single SCMI OSPM agent support is pretty generic case for
> +the default vendors SDK and new platforms with SCMI support. Such EL3 SCMI firmware supports only
> +single SCMI OSPM transport (agent) with Shared memory based transport and SMC calls as doorbell.
> +
> +The SCMI over SMC calls forwarding driver solves major problem for this case by allowing
> +SMC calls to be forwarded form guest to the EL3 SCMI firmware.
> +
> +By default, the SCMI over SMC calls forwarding is enabled for Dom0/hwdom.
> +
> +::
> +
> +    +--------------------------+
> +    |                          |
> +    | EL3 SCMI FW (TF-A)       |
> +    ++-------+--^--------------+
> +     |shmem  |  | smc-id
> +     +----^--+  |
> +          |     |
> +     +----|-+---+---+----------+
> +     |    | |  FWD  |      Xen |
> +     |    | +---^---+          |
> +     +----|-----|--------------+
> +          |     | smc-id
> +     +----v-----+--+ +---------+
> +     |             | |         |
> +     | Dom0/hwdom  | | DomU    |
> +     |             | |         |
> +     |             | |         |
> +     +-------------+ +---------+
> +
> +
> +The SCMI messages are passed directly through SCMI shared-memory (zero-copy) and driver only
> +forwards SMC calls.
> +
> +Compiling
> +^^^^^^^^^
> +
> +To build with the SCMI over SMC calls forwarding enabled support, enable Kconfig option
> +
> +::
> +
> +    CONFIG_SCMI_SMC
> +
> +The ``CONFIG_SCMI_SMC`` is enabled by default.
> +
> +Pass-through SCMI SMC to domain which serves as Driver domain
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +This section describes how to configure the SCMI over SMC calls forwarding driver to handle use
> +case "thin Dom0 with guest domain, which serves as Driver domain". In this case HW need to be
> +enabled in Driver domain and dom0 is performing only control functions (without accessing FW) and so,
> +the SCMI need to be enabled in Driver domain.
> +
> +::
> +
> +     +--------------------------+
> +     |EL3 SCMI FW (TF-A)        |
> +     |                          |
> +     +-------------^--+-------+-+
> +             smc-id|  |shmem0 |
> +                   |  +----^--+
> +    +-------------++------+|----+
> +    |Xen          |  FWD  ||    |
> +    |             +--^----+|    |
> +    +----------------|-----|----+
> +              smc-id |     |
> +    +-----------+ +--+-----v-----+
> +    |           | |              |
> +    | Dom0      | |    Driver    |
> +    | Control   | |    domain    |
> +    |           | |              |
> +    +-----------+ +--------------+
> +
> +The SCMI can be enabled for one and only one guest domain.
> +
> +First. configure Dom0 to enable SCMI pass-through using Xen Command Line
> +**"scmi-smc-passthrough"** option. This will disable SCMI for Dom0/hwdom and SCMI nodes will
> +be removed from Dom0/hwdom device tree.
> +
> +**Configure SCMI pass-through for guest domain with toolstack**
> +
> +* In domain's xl.cfg file add **"arm_sci"** option as below
> +
> +::
> +
> +    arm_sci = "type=scmi_smc"
> +
> +* In domain's xl.cfg file enable access to the "arm,scmi-shmem"
> +
> +::
> +
> +    iomem = [
> +        "47ff0,1@22001",
> +    ]
> +
> +.. note:: It's up to the user to select guest IPA for mapping SCMI shared-memory.
> +
> +* Add SCMI nodes to the Driver domain partial device tree as in the below example:
> +
> +.. code::
> +
> +    passthrough {
> +       scmi_shm_0: sram@22001000 {
> +           compatible = "arm,scmi-shmem";
> +           reg = <0x0 0x22001000 0x0 0x1000>;
> +       };
> +
> +       firmware {
> +            compatible = "simple-bus";
> +                scmi: scmi {
> +                    compatible = "arm,scmi-smc";
> +                    shmem = <&scmi_shm_0>;
> +                    ...
> +                }
> +        }
> +    }
> +
> +Please refer to [2] for details of SCMI DT bindings.
> +
> +In general, the configuration is similar to any other HW pass-through, except explicitly
> +enabling SCMI with "arm_sci" xl.cfg option.
> +
> +**Configure SCMI pass-through for predefined domain (dom0less)**
> +
> +* add "xen,sci_type" property for required DomU ("xen,domain") node
> +
> +::
> +
> +       xen,sci_type="scmi_smc"
> +
> +* add scmi nodes to the Driver domain partial device tree the same way as above and enable access
> +  to the "arm,scmi-shmem" according to  dom0less documentation. For example:
> +
> +.. code::
> +
> +      scmi_shm_0: sram@22001000 {
> +            compatible = "arm,scmi-shmem";
> +            reg = <0x00 0x22001000 0x00 0x1000>;
> +    ->        xen,reg = <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
> +    ->        xen,force-assign-without-iommu;
> +      };
> diff --git a/docs/hypervisor-guide/arm/index.rst b/docs/hypervisor-guide/arm/index.rst
> new file mode 100644
> index 0000000000..7aae4a0a03
> --- /dev/null
> +++ b/docs/hypervisor-guide/arm/index.rst
> @@ -0,0 +1,9 @@
> +.. SPDX-License-Identifier: CC-BY-4.0
> +
> +ARM
> +===
> +
> +.. toctree::
> +   :maxdepth: 2
> +
> +   firmware/arm-scmi
> diff --git a/docs/hypervisor-guide/index.rst b/docs/hypervisor-guide/index.rst
> index e4393b0697..520fe01554 100644
> --- a/docs/hypervisor-guide/index.rst
> +++ b/docs/hypervisor-guide/index.rst
> @@ -9,3 +9,4 @@ Hypervisor documentation
>     code-coverage
>  
>     x86/index
> +   arm/index
> \ No newline at end of file
> -- 
> 2.34.1
> 


From xen-devel-bounces@lists.xenproject.org Thu Aug 28 23:41:39 2025
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Date: Thu, 28 Aug 2025 16:41:15 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Jan Beulich 
cc: Stefano Stabellini , 
    Oleksii Kurochko , ray.huang@amd.com, 
    Andrew Cooper , 
    =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
    Anthony PERARD , 
    Michal Orzel , Julien Grall , 
    xen-devel@lists.xenproject.org, Penny Zheng 
Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
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On Thu, 28 Aug 2025, Jan Beulich wrote:
> On 28.08.2025 02:52, Stefano Stabellini wrote:
> > On Wed, 27 Aug 2025, Jan Beulich wrote:
> >> On 27.08.2025 02:33, Stefano Stabellini wrote:
> >>> So I ran a test and the appended change, which is based on [1] and
> >>> renaming CONFIG_DOMCTL to CONFIG_SYSCTL, is sufficient to resolve the
> >>> build issue.
> >>>
> >>> For 4.21, I suggest we go with two patches:
> >>> 1) global rename of CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
> >>> 2) stub domctl_lock_acquire/release based on CONFIG_MGMT_HYPERCALLS
> >>>
> >>> Jan, are you OK with this?
> >>
> >> Naming if the option aside, no, I fear I dislike the stubbing. What's
> >> worse though, ...
> >>
> >>> --- a/xen/include/xen/domain.h
> >>> +++ b/xen/include/xen/domain.h
> >>> @@ -148,8 +148,17 @@ void arch_dump_domain_info(struct domain *d);
> >>>  
> >>>  int arch_vcpu_reset(struct vcpu *v);
> >>>  
> >>> +#ifdef CONFIG_SYSCTL
> >>>  bool domctl_lock_acquire(void);
> >>>  void domctl_lock_release(void);
> >>> +#else
> >>> +static inline bool domctl_lock_acquire(void)
> >>> +{
> >>> +    return false;
> >>
> >> ... this will break x86'es HVM_PARAM_IDENT_PT handling. That is, in
> >> principle I would agree that returning false here is appropriate. But
> >> for the specific case there it's wrong.
> > 
> > Uhm, that is a good point actually. And while in principle "false"
> > sounds appropriate, in practice there is no domctl.c to worry about
> > concurrency so "true" is what we want.
> 
> Except that, as said, conceptually "true" is the wrong value to use in
> such a stub.
> 
> >> As said on the call yesterday, until what you call MGMT_HYPERCALLS is
> >> completely done, the option needs to be prompt-less, always-on.
> > 
> > I do not think this is a good idea, because we would be unable to test
> > the configuration. Although we have been accepting code without tests,
> > that is not a good principle. At least with the current approach we can
> > run manual tests if automated tests are not available. If we make it
> > silent, we risk introducing broken code, or code soon-to-become broken.
> > 
> > In my view, we need to make gradual progress toward the goal. In this
> > case, we should move incrementally toward compiling out all the
> > "management" hypercalls. Also the alternative of waiting until all
> > patches are ready before committing them is not feasible. An incremental
> > approach reduces risk, preserves testability, and makes regressions
> > easier to identify.
> 
> If that's your view, then why did you not comment on the SYSCTL series,
> when I asked the prompt to appear last?

I am not trying to be obtuse, but I am not sure what you mean by this.
In any case, I do not recall reading a specific email on this topic. I
try my best to follow other review comments, but I may have overlooked
this one.


> > An extreme example is that I could write:
> > 
> > static inline bool domctl_lock_acquire(void)
> > {
> >     obviously broken
> > }
> > 
> > and no tests would catch it.
> 
> Tests would catch it at the point the prompt is added. Much like it was
> with the SYSCTL series (and why, with the prompt removed, the rest of
> the series can stay in).

In my opinion, this is a no-go. The code must function correctly, and
that is my top priority, certainly above conceptual issues, such as the
return value of domctl_lock_acquire. With your suggestion, there is no
guarantee the code works and there is no way to test it.


> >> Adding
> >> a prompt was necessary to be the last thing on the SYSCTL series, and
> >> it'll need to be last on the follow-on one masking out further
> >> hypercalls. IOW my take is that 34317c508294 and 568f806cba4c will
> >> need reverting (the latter being what caused the regression, and the
> >> former depending on the latter), to allow to cleanly continue that
> >> work after the rename. If we don't do the reverts now (and take either
> >> Penny's patch or what you propose), imo we'll need to do them later.
> >> Else we're risking to introduce new randconfig breakages while the
> >> further conversion work is ongoing.
> > 
> > My suggestion remains to go forward with 2 patches:
> > 0) keep both 568f806cba4c and 34317c508294
> > 1) rename CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
> > 2) this patch with return true from domctl_lock_acquire
> > 
> > I am open to reverting 568f806cba4c but I don't think it would improve
> > things. I definitely don't think we should revert 34317c508294. We need
> > 34317c508294 otherwise this patch doesn't fix the build.
> 
> If "this patch" is the one outlined here, then with the reverts we wouldn't
> need it at all. The reverts alone will fix the build issue, according to my
> understanding.

The reverts you are suggesting do not fix the issue; they only hide it.
The Kconfig option can no longer be disabled, which renders the entire
patch series ineffective. In fact, the #ifdef's could be completely
incorrect, and the code would still build, as in my example:

static inline bool domctl_lock_acquire(void)
{
    obviously broken
}

It looks like we'll need a third opinion to make forward progress.


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Date: Thu, 28 Aug 2025 20:45:42 -0300
From: Jason Gunthorpe 
To: Keith Busch 
Cc: Leon Romanovsky ,
	Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
Message-ID: <20250828234542.GK7333@nvidia.com>
References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
 
 <20250828165427.GB10073@unreal>
 
 <20250828184115.GE7333@nvidia.com>
 
 <20250828191820.GH7333@nvidia.com>
 
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On Thu, Aug 28, 2025 at 02:54:35PM -0600, Keith Busch wrote:

> In truth though, I hadn't tried p2p metadata before today, and it looks
> like bio_integrity_map_user() is missing the P2P extraction flags to
> make that work. Just added this patch below, now I can set p2p or host
> memory independently for data and integrity payloads:

I think it is a bit more than that, you have to make sure all the meta
data is the same, either all p2p or all cpu and then record this
somehow so the DMA mapping knows what kind it is.

Once that is all done then the above should still be OK, the dma unmap
of the data can follow Leon's new flag and the dma unmap of the
integrity can follow however integrity kept track (in the
bio_integrity_payload perhaps?) ??

Jason


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	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 02/15] xen/8250-uart: update definitions
Date: Thu, 28 Aug 2025 16:53:56 -0700
Message-ID: <20250828235409.2835815-3-dmukhin@ford.com>
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In-Reply-To: <20250828235409.2835815-1-dmukhin@ford.com>
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From: Denis Mukhin  

Added missing definitions needed for NS16550 UART emulator.

Newly introduced MSR definitions re-used in the existing ns16550 driver.

Also, corrected FCR DMA definition bit#3 (0x08) as per:
  https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
See "7.7.2 FIFO Control Register (FCR)".

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- reused newly introduced UART_IIR and UART_IER bits in ns16550 driver
- Link to v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-5-dmukhin@ford.com/
---
 xen/drivers/char/ns16550.c  | 16 ++++++------
 xen/include/xen/8250-uart.h | 50 ++++++++++++++++++++++++++++++-------
 2 files changed, 49 insertions(+), 17 deletions(-)

diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index df7fff7f81df..0e80fadbb894 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -388,7 +388,7 @@ static void __init cf_check ns16550_init_preirq(struct serial_port *port)
 
     /* Check this really is a 16550+. Otherwise we have no FIFOs. */
     if ( uart->fifo_size <= 1 &&
-         ((ns_read_reg(uart, UART_IIR) & 0xc0) == 0xc0) &&
+         ((ns_read_reg(uart, UART_IIR) & UART_IIR_FE) == UART_IIR_FE) &&
          ((ns_read_reg(uart, UART_FCR) & UART_FCR_TRG14) == UART_FCR_TRG14) )
         uart->fifo_size = 16;
 }
@@ -728,20 +728,20 @@ static int __init check_existence(struct ns16550 *uart)
      * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
      * 16C754B) allow only to modify them if an EFR bit is set.
      */
-    scratch2 = ns_read_reg(uart, UART_IER) & 0x0f;
-    ns_write_reg(uart,UART_IER, 0x0F);
-    scratch3 = ns_read_reg(uart, UART_IER) & 0x0f;
+    scratch2 = ns_read_reg(uart, UART_IER) & UART_IER_MASK;
+    ns_write_reg(uart, UART_IER, UART_IER_MASK);
+    scratch3 = ns_read_reg(uart, UART_IER) & UART_IER_MASK;
     ns_write_reg(uart, UART_IER, scratch);
-    if ( (scratch2 != 0) || (scratch3 != 0x0F) )
+    if ( (scratch2 != 0) || (scratch3 != UART_IER_MASK) )
         return 0;
 
     /*
      * Check to see if a UART is really there.
      * Use loopback test mode.
      */
-    ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | 0x0A);
-    status = ns_read_reg(uart, UART_MSR) & 0xF0;
-    return (status == 0x90);
+    ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | UART_MCR_RTS | UART_MCR_OUT2);
+    status = ns_read_reg(uart, UART_MSR) & UART_MSR_STATUS;
+    return (status == (UART_MSR_CTS | UART_MSR_DCD));
 }
 
 #ifdef CONFIG_HAS_PCI
diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h
index d13352940c13..bc11cdc376c9 100644
--- a/xen/include/xen/8250-uart.h
+++ b/xen/include/xen/8250-uart.h
@@ -32,6 +32,7 @@
 #define UART_MCR          0x04    /* Modem control        */
 #define UART_LSR          0x05    /* line status          */
 #define UART_MSR          0x06    /* Modem status         */
+#define UART_SCR          0x07    /* Scratch pad          */
 #define UART_USR          0x1f    /* Status register (DW) */
 #define UART_DLL          0x00    /* divisor latch (ls) (DLAB=1) */
 #define UART_DLM          0x01    /* divisor latch (ms) (DLAB=1) */
@@ -42,6 +43,8 @@
 #define UART_IER_ETHREI   0x02    /* tx reg. empty        */
 #define UART_IER_ELSI     0x04    /* rx line status       */
 #define UART_IER_EMSI     0x08    /* MODEM status         */
+#define UART_IER_MASK \
+    (UART_IER_ERDAI | UART_IER_ETHREI | UART_IER_ELSI | UART_IER_EMSI)
 
 /* Interrupt Identification Register */
 #define UART_IIR_NOINT    0x01    /* no interrupt pending */
@@ -51,12 +54,19 @@
 #define UART_IIR_THR      0x02    /*  - tx reg. empty     */
 #define UART_IIR_MSI      0x00    /*  - MODEM status      */
 #define UART_IIR_BSY      0x07    /*  - busy detect (DW) */
+#define UART_IIR_FE       0xc0    /* FIFO enabled (2 bits) */
 
 /* FIFO Control Register */
-#define UART_FCR_ENABLE   0x01    /* enable FIFO          */
-#define UART_FCR_CLRX     0x02    /* clear Rx FIFO        */
-#define UART_FCR_CLTX     0x04    /* clear Tx FIFO        */
-#define UART_FCR_DMA      0x10    /* enter DMA mode       */
+#define UART_FCR_ENABLE     BIT(0, U)   /* enable FIFO          */
+#define UART_FCR_CLRX       BIT(1, U)   /* clear Rx FIFO        */
+#define UART_FCR_CLTX       BIT(2, U)   /* clear Tx FIFO        */
+#define UART_FCR_DMA        BIT(3, U)   /* enter DMA mode       */
+#define UART_FCR_RESERVED0  BIT(4, U)   /* reserved; always 0   */
+#define UART_FCR_RESERVED1  BIT(5, U)   /* reserved; always 0   */
+#define UART_FCR_RTB0       BIT(6, U)   /* receiver trigger bit #0 */
+#define UART_FCR_RTB1       BIT(7, U)   /* receiver trigger bit #1 */
+#define UART_FCR_TRG_MASK   (UART_FCR_RTB0 | UART_FCR_RTB1)
+
 #define UART_FCR_TRG1     0x00    /* Rx FIFO trig lev 1   */
 #define UART_FCR_TRG4     0x40    /* Rx FIFO trig lev 4   */
 #define UART_FCR_TRG8     0x80    /* Rx FIFO trig lev 8   */
@@ -96,11 +106,32 @@
 #define UART_LCR_CONF_MODE_B	0xBF		/* Configuration mode B */
 
 /* Modem Control Register */
-#define UART_MCR_DTR      0x01    /* Data Terminal Ready  */
-#define UART_MCR_RTS      0x02    /* Request to Send      */
-#define UART_MCR_OUT2     0x08    /* OUT2: interrupt mask */
-#define UART_MCR_LOOP     0x10    /* Enable loopback test mode */
-#define UART_MCR_TCRTLR   0x40    /* Access TCR/TLR (TI16C752, EFR[4]=1) */
+#define UART_MCR_DTR            BIT(0, U)   /* Data Terminal Ready  */
+#define UART_MCR_RTS            BIT(1, U)   /* Request to Send      */
+#define UART_MCR_OUT1           BIT(2, U)   /* OUT1: interrupt mask */
+#define UART_MCR_OUT2           BIT(3, U)   /* OUT2: interrupt mask */
+#define UART_MCR_LOOP           BIT(4, U)   /* Enable loopback test mode */
+#define UART_MCR_RESERVED0      BIT(5, U)   /* Reserved #0 */
+#define UART_MCR_TCRTLR         BIT(6, U)   /* Access TCR/TLR (TI16C752, EFR[4]=1) */
+#define UART_MCR_RESERVED1      BIT(7, U)   /* Reserved #1 */
+#define UART_MCR_MASK \
+    (UART_MCR_DTR | UART_MCR_RTS | \
+     UART_MCR_OUT1 | UART_MCR_OUT2 | \
+     UART_MCR_LOOP | UART_MCR_TCRTLR)
+
+/* Modem Status Register */
+#define UART_MSR_DCTS           BIT(0, U)   /* Change in CTS */
+#define UART_MSR_DDSR           BIT(1, U)   /* Change in DSR */
+#define UART_MSR_TERI           BIT(2, U)   /* Change in RI */
+#define UART_MSR_DDCD           BIT(3, U)   /* Change in CTS */
+#define UART_MSR_CTS            BIT(4, U)
+#define UART_MSR_DSR            BIT(5, U)
+#define UART_MSR_RI             BIT(6, U)
+#define UART_MSR_DCD            BIT(7, U)
+#define UART_MSR_CHANGE \
+    (UART_MSR_DCTS | UART_MSR_DDSR | UART_MSR_TERI | UART_MSR_DDCD)
+#define UART_MSR_STATUS \
+    (UART_MSR_CTS | UART_MSR_DSR | UART_MSR_RI | UART_MSR_DCD)
 
 /* Line Status Register */
 #define UART_LSR_DR       0x01    /* Data ready           */
@@ -111,6 +142,7 @@
 #define UART_LSR_THRE     0x20    /* Xmit hold reg empty  */
 #define UART_LSR_TEMT     0x40    /* Xmitter empty        */
 #define UART_LSR_ERR      0x80    /* Error                */
+#define UART_LSR_MASK     (UART_LSR_OE | UART_LSR_BI)
 
 /* These parity settings can be ORed directly into the LCR. */
 #define UART_PARITY_NONE  (0<<3)
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 01/15] emul/vuart: introduce framework for UART emulators
Date: Thu, 28 Aug 2025 16:53:55 -0700
Message-ID: <20250828235409.2835815-2-dmukhin@ford.com>
X-Mailer: git-send-email 2.51.0
In-Reply-To: <20250828235409.2835815-1-dmukhin@ford.com>
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From: Denis Mukhin  

Introduce a driver framework to abstract UART emulators in the hypervisor.

That allows for architecture-independent handling of virtual UARTs in the
console driver and simplifies enabling new UART emulators.

The framework is built under CONFIG_VUART_FRAMEWORK, which will be
automatically enabled once the user enables any UART emulator.

Current implementation supports maximum of one vUART of each kind per domain.

Use new domain_has_vuart() in the console driver code to check whether to
forward console input to the domain using vUART.

Enable console forwarding over vUART for hardware domains with a vUART. That
enables console forwarding to dom0 on x86, since console can be forwarded only
to Xen, dom0 and pvshim on x86 as of now.

Note: existing vUARTs are deliberately *not* hooked to the new framework to
minimize the scope of the patch: vpl011 (i.e. SBSA) emulator and "vuart" (i.e.
minimalistic MMIO-mapped dtuart for hwdoms on Arm) are kept unmodified.

No functional changes for non-x86 architectures.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- addressed feedback
- Link to v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-3-dmukhin@ford.com/
---
 xen/arch/arm/xen.lds.S         |   1 +
 xen/arch/ppc/xen.lds.S         |   1 +
 xen/arch/riscv/xen.lds.S       |   1 +
 xen/arch/x86/xen.lds.S         |   1 +
 xen/common/Kconfig             |   2 +
 xen/common/Makefile            |   1 +
 xen/common/emul/Kconfig        |   6 ++
 xen/common/emul/Makefile       |   1 +
 xen/common/emul/vuart/Kconfig  |   6 ++
 xen/common/emul/vuart/Makefile |   1 +
 xen/common/emul/vuart/vuart.c  | 156 +++++++++++++++++++++++++++++++++
 xen/common/keyhandler.c        |   3 +
 xen/drivers/char/console.c     |   6 +-
 xen/include/xen/serial.h       |   3 +
 xen/include/xen/vuart.h        | 116 ++++++++++++++++++++++++
 xen/include/xen/xen.lds.h      |  10 +++
 16 files changed, 314 insertions(+), 1 deletion(-)
 create mode 100644 xen/common/emul/Kconfig
 create mode 100644 xen/common/emul/Makefile
 create mode 100644 xen/common/emul/vuart/Kconfig
 create mode 100644 xen/common/emul/vuart/Makefile
 create mode 100644 xen/common/emul/vuart/vuart.c
 create mode 100644 xen/include/xen/vuart.h

diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S
index db17ff1efa98..cd05b18770f4 100644
--- a/xen/arch/arm/xen.lds.S
+++ b/xen/arch/arm/xen.lds.S
@@ -58,6 +58,7 @@ SECTIONS
        *(.rodata)
        *(.rodata.*)
        VPCI_ARRAY
+       VUART_ARRAY
        *(.data.rel.ro)
        *(.data.rel.ro.*)
 
diff --git a/xen/arch/ppc/xen.lds.S b/xen/arch/ppc/xen.lds.S
index 1de0b77fc6b9..f9d4e5b0dcd8 100644
--- a/xen/arch/ppc/xen.lds.S
+++ b/xen/arch/ppc/xen.lds.S
@@ -52,6 +52,7 @@ SECTIONS
         *(.rodata)
         *(.rodata.*)
         VPCI_ARRAY
+        VUART_ARRAY
         *(.data.rel.ro)
         *(.data.rel.ro.*)
 
diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S
index edcadff90bfe..59dcaa5fef9a 100644
--- a/xen/arch/riscv/xen.lds.S
+++ b/xen/arch/riscv/xen.lds.S
@@ -47,6 +47,7 @@ SECTIONS
         *(.rodata)
         *(.rodata.*)
         VPCI_ARRAY
+        VUART_ARRAY
         *(.data.rel.ro)
         *(.data.rel.ro.*)
 
diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S
index 966e514f2034..d877b93a6964 100644
--- a/xen/arch/x86/xen.lds.S
+++ b/xen/arch/x86/xen.lds.S
@@ -132,6 +132,7 @@ SECTIONS
        *(.rodata)
        *(.rodata.*)
        VPCI_ARRAY
+       VUART_ARRAY
        *(.data.rel.ro)
        *(.data.rel.ro.*)
 
diff --git a/xen/common/Kconfig b/xen/common/Kconfig
index 76f9ce705f7a..78a32b69e2b2 100644
--- a/xen/common/Kconfig
+++ b/xen/common/Kconfig
@@ -676,4 +676,6 @@ config PM_STATS
 	  Enable collection of performance management statistics to aid in
 	  analyzing and tuning power/performance characteristics of the system
 
+source "common/emul/Kconfig"
+
 endmenu
diff --git a/xen/common/Makefile b/xen/common/Makefile
index c316957fcb36..c0734480ee4b 100644
--- a/xen/common/Makefile
+++ b/xen/common/Makefile
@@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o
 obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/
 obj-$(CONFIG_IOREQ_SERVER) += dm.o
 obj-y += domain.o
+obj-y += emul/
 obj-y += event_2l.o
 obj-y += event_channel.o
 obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o
diff --git a/xen/common/emul/Kconfig b/xen/common/emul/Kconfig
new file mode 100644
index 000000000000..7c6764d1756b
--- /dev/null
+++ b/xen/common/emul/Kconfig
@@ -0,0 +1,6 @@
+menu "Domain Emulation Features"
+	visible if EXPERT
+
+source "common/emul/vuart/Kconfig"
+
+endmenu
diff --git a/xen/common/emul/Makefile b/xen/common/emul/Makefile
new file mode 100644
index 000000000000..ae0b575c3901
--- /dev/null
+++ b/xen/common/emul/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_VUART_FRAMEWORK) += vuart/
diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kconfig
new file mode 100644
index 000000000000..ce1b976b7da7
--- /dev/null
+++ b/xen/common/emul/vuart/Kconfig
@@ -0,0 +1,6 @@
+config VUART_FRAMEWORK
+	bool
+
+menu "UART Emulation"
+
+endmenu
diff --git a/xen/common/emul/vuart/Makefile b/xen/common/emul/vuart/Makefile
new file mode 100644
index 000000000000..97f792dc6641
--- /dev/null
+++ b/xen/common/emul/vuart/Makefile
@@ -0,0 +1 @@
+obj-y += vuart.o
diff --git a/xen/common/emul/vuart/vuart.c b/xen/common/emul/vuart/vuart.c
new file mode 100644
index 000000000000..7b277d00d5c7
--- /dev/null
+++ b/xen/common/emul/vuart/vuart.c
@@ -0,0 +1,156 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UART emulator framework.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define for_each_emulator(e) \
+    for ( e = vuart_array_start; e < vuart_array_end; e++ )
+
+extern const struct vuart_emulator vuart_array_start[];
+extern const struct vuart_emulator vuart_array_end[];
+
+static const struct vuart_emulator *
+vuart_match_by_compatible(struct domain *d, const char *compat)
+{
+    const struct vuart_emulator *emulator;
+
+    if ( d->console.vuart )
+        return NULL;
+
+    for_each_emulator(emulator)
+        if ( emulator->compatible &&
+             !strncmp(emulator->compatible, compat,
+                      strlen(emulator->compatible)) )
+            return emulator;
+
+    return NULL;
+}
+
+static struct vuart *vuart_find_by_console_permission(const struct domain *d)
+{
+    struct vuart *vuart = d->console.vuart;
+
+    ASSERT(d->console.input_allowed);
+
+    if ( !vuart || !vuart->emulator || !vuart->emulator->put_rx ||
+         !(vuart->flags & VUART_CONSOLE_INPUT))
+        return NULL;
+
+    return vuart;
+}
+
+struct vuart *vuart_find_by_io_range(struct domain *d, unsigned long addr,
+                                     unsigned long size)
+{
+    struct vuart *vuart = d->console.vuart;
+
+    if ( !vuart || !vuart->info )
+        return NULL;
+
+    if ( addr >= vuart->info->base_addr &&
+         addr + size - 1 <= vuart->info->base_addr + vuart->info->size - 1 )
+        return vuart;
+
+    return NULL;
+}
+
+int vuart_init(struct domain *d, struct vuart_info *info)
+{
+    const struct vuart_emulator *emulator;
+    struct vuart *vuart;
+    int rc;
+
+    emulator = vuart_match_by_compatible(d, info->compatible);
+    if ( !emulator )
+        return -ENODEV;
+
+    vuart = xzalloc(typeof(*vuart));
+    if ( !vuart )
+        return -ENOMEM;
+
+    vuart->info = xvzalloc(typeof(*info));
+    if ( !vuart->info )
+    {
+        rc = -ENOMEM;
+        goto err_out;
+    }
+    memcpy(vuart->info, info, sizeof(*info));
+
+    vuart->vdev = emulator->alloc(d, vuart->info);
+    if ( IS_ERR(vuart->vdev) )
+    {
+        rc = PTR_ERR(vuart->vdev);
+        goto err_out;
+    }
+
+    vuart->emulator = emulator;
+    vuart->owner = d;
+    vuart->flags |= VUART_CONSOLE_INPUT;
+
+    d->console.input_allowed = true;
+    d->console.vuart = vuart;
+
+    return 0;
+
+ err_out:
+    XVFREE(vuart);
+    return rc;
+}
+
+/*
+ * Release any resources taken by UART emulators.
+ *
+ * NB: no flags are cleared, since currently exit() is called only during
+ * domain destroy.
+ */
+void vuart_deinit(struct domain *d)
+{
+    struct vuart *vuart = d->console.vuart;
+
+    if ( vuart )
+    {
+        vuart->emulator->free(vuart);
+        XVFREE(vuart->info);
+    }
+
+    XVFREE(d->console.vuart);
+}
+
+void vuart_dump_state(const struct domain *d)
+{
+    struct vuart *vuart = d->console.vuart;
+
+    if ( vuart )
+        vuart->emulator->dump_state(vuart);
+}
+
+/*
+ * Put character to the *first* suitable emulated UART's FIFO.
+ */
+int vuart_put_rx(struct domain *d, char c)
+{
+    struct vuart *vuart = vuart_find_by_console_permission(d);
+
+    return vuart ? vuart->emulator->put_rx(vuart, c) : -ENODEV;
+}
+
+bool domain_has_vuart(const struct domain *d)
+{
+    return vuart_find_by_console_permission(d);
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/common/keyhandler.c b/xen/common/keyhandler.c
index cb6df2823b00..156e64d9eb58 100644
--- a/xen/common/keyhandler.c
+++ b/xen/common/keyhandler.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 static unsigned char keypress_key;
@@ -352,6 +353,8 @@ static void cf_check dump_domains(unsigned char key)
                            v->periodic_period / 1000000);
             }
         }
+
+        vuart_dump_state(d);
     }
 
     for_each_domain ( d )
diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c
index 9bd5b4825da6..d5164897a776 100644
--- a/xen/drivers/char/console.c
+++ b/xen/drivers/char/console.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifdef CONFIG_X86
 #include 
@@ -596,11 +597,12 @@ static void __serial_rx(char c)
     if ( !d )
         return;
 
-    if ( is_hardware_domain(d) )
+    if ( is_hardware_domain(d) && !domain_has_vuart(d) )
     {
         /*
          * Deliver input to the hardware domain buffer, unless it is
          * already full.
+         * NB: must be the first check: hardware domain may have emulated UART.
          */
         if ( (serial_rx_prod - serial_rx_cons) != SERIAL_RX_SIZE )
             serial_rx_ring[SERIAL_RX_MASK(serial_rx_prod++)] = c;
@@ -611,6 +613,8 @@ static void __serial_rx(char c)
          */
         send_global_virq(VIRQ_CONSOLE);
     }
+    else if ( domain_has_vuart(d) )
+        rc = vuart_put_rx(d, c);
 #ifdef CONFIG_SBSA_VUART_CONSOLE
     else
         /* Deliver input to the emulated UART. */
diff --git a/xen/include/xen/serial.h b/xen/include/xen/serial.h
index 8e1844555208..d7e81f098359 100644
--- a/xen/include/xen/serial.h
+++ b/xen/include/xen/serial.h
@@ -36,6 +36,9 @@ struct vuart_info {
     unsigned long data_off;     /* Data register offset */
     unsigned long status_off;   /* Status register offset */
     unsigned long status;       /* Ready status value */
+    unsigned int irq;           /* Interrupt */
+    const char *compatible;     /* Compatible string */
+    const char *name;           /* User-friendly name */
 };
 
 struct serial_port {
diff --git a/xen/include/xen/vuart.h b/xen/include/xen/vuart.h
new file mode 100644
index 000000000000..ca025b4179be
--- /dev/null
+++ b/xen/include/xen/vuart.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UART emulator framework.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#ifndef XEN_VUART_H
+#define XEN_VUART_H
+
+#include 
+#include 
+
+struct vuart_emulator;
+
+enum {
+    VUART_CONSOLE_INPUT = 0U << 1, /** Physical console input forwarding. */
+};
+
+
+/*
+ * FIXME: #ifdef is temporary to avoid clash with
+ *   arch/arm/include/asm/domain.h
+ */
+#ifdef CONFIG_VUART_FRAMEWORK
+struct vuart {
+    const struct vuart_emulator *emulator;
+    struct vuart_info *info;
+    struct domain *owner;
+    uint32_t flags;
+    void *vdev;
+};
+#endif
+
+struct vuart_emulator {
+    /* UART compatible string. Cannot be NULL or empty. */
+    const char *compatible;
+
+    /*
+     * Allocate emulated UART state (RX/TX FIFOs, locks, initialize registers,
+     * hook I/O handlers, etc.)
+     * Cannot be NULL.
+     */
+    void *(*alloc)(struct domain *d, const struct vuart_info *info);
+
+    /*
+     * Release resources used to emulate UART state (flush RX/TX FIFOs, unhook
+     * I/O handlers, etc.).
+     * Cannot be NULL.
+     */
+    void (*free)(void *arg);
+
+    /*
+     * Print emulated UART state, including registers, on the console.
+     * Can be NULL.
+     */
+    void (*dump_state)(void *arg);
+
+    /*
+     * Place character to the emulated RX FIFO.
+     * Used to forward physical console input to the guest OS.
+     * Can be NULL.
+     */
+    int (*put_rx)(void *arg, char c);
+};
+
+#define VUART_REGISTER(name, x) \
+    static const struct vuart_emulator name##_entry \
+        __used_section(".data.rel.ro.vuart") = x
+
+struct vuart *vuart_find_by_io_range(struct domain *d,
+                                     unsigned long base_addr,
+                                     unsigned long size);
+
+int vuart_put_rx(struct domain *d, char c);
+
+#ifdef CONFIG_VUART_FRAMEWORK
+
+int vuart_init(struct domain *d, struct vuart_info *info);
+void vuart_deinit(struct domain *d);
+void vuart_dump_state(const struct domain *d);
+bool domain_has_vuart(const struct domain *d);
+
+#else
+
+static inline int vuart_init(struct domain *d, struct vuart_info *info)
+{
+    return 0;
+}
+
+static inline void vuart_deinit(struct domain *d)
+{
+}
+
+static inline void vuart_dump_state(const struct domain *d)
+{
+}
+
+static inline bool domain_has_vuart(const struct domain *d)
+{
+    return false;
+}
+
+#endif /* CONFIG_VUART_FRAMEWORK */
+
+#endif /* XEN_VUART_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
+
diff --git a/xen/include/xen/xen.lds.h b/xen/include/xen/xen.lds.h
index b126dfe88792..2d65f32ddad3 100644
--- a/xen/include/xen/xen.lds.h
+++ b/xen/include/xen/xen.lds.h
@@ -194,4 +194,14 @@
 #define VPCI_ARRAY
 #endif
 
+#ifdef CONFIG_VUART_FRAMEWORK
+#define VUART_ARRAY              \
+       . = ALIGN(POINTER_ALIGN); \
+       vuart_array_start = .;    \
+       *(.data.rel.ro.vuart)     \
+       vuart_array_end = .;
+#else
+#define VUART_ARRAY
+#endif
+
 #endif /* __XEN_LDS_H__ */
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 03/15] emul/ns16x50: implement emulator stub
Date: Thu, 28 Aug 2025 16:53:57 -0700
Message-ID: <20250828235409.2835815-4-dmukhin@ford.com>
X-Mailer: git-send-email 2.51.0
In-Reply-To: <20250828235409.2835815-1-dmukhin@ford.com>
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From: Denis Mukhin  

The change is the first on the way on introducing minimally functional
NS16550-compatible UART emulator.

Define UART state and a set of emulated registers.

Implement alloc/free vUART hooks.

Stub out I/O port handler.

Add initialization of the NS16x50-compatible UART emulator state machine.

Plumb debug logging.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch 
---
 xen/arch/x86/hvm/hvm.c          |  20 ++
 xen/common/emul/vuart/Kconfig   |  18 ++
 xen/common/emul/vuart/Makefile  |   1 +
 xen/common/emul/vuart/ns16x50.c | 362 ++++++++++++++++++++++++++++++++
 xen/include/xen/sched.h         |   4 +
 5 files changed, 405 insertions(+)
 create mode 100644 xen/common/emul/vuart/ns16x50.c

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 23bd7f078a1d..26760cf995df 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -689,6 +690,21 @@ int hvm_domain_initialise(struct domain *d,
     if ( rc != 0 )
         goto fail1;
 
+    if ( IS_ENABLED(CONFIG_VUART_NS16X50) )
+    {
+        struct vuart_info info = {
+            .name       = "COM2",
+            .compatible = "ns16550",
+            .base_addr  = 0x2f8,
+            .size       = 8,
+            .irq        = 3,
+        };
+
+        rc = vuart_init(d, &info);
+        if ( rc )
+            goto out_vioapic_deinit;
+    }
+
     stdvga_init(d);
 
     rtc_init(d);
@@ -712,6 +728,8 @@ int hvm_domain_initialise(struct domain *d,
     return 0;
 
  fail2:
+    vuart_deinit(d);
+ out_vioapic_deinit:
     vioapic_deinit(d);
  fail1:
     if ( is_hardware_domain(d) )
@@ -774,6 +792,8 @@ void hvm_domain_destroy(struct domain *d)
     if ( hvm_funcs.domain_destroy )
         alternative_vcall(hvm_funcs.domain_destroy, d);
 
+    vuart_deinit(d);
+
     vioapic_deinit(d);
 
     XFREE(d->arch.hvm.pl_time);
diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kconfig
index ce1b976b7da7..539e6d5e4fc7 100644
--- a/xen/common/emul/vuart/Kconfig
+++ b/xen/common/emul/vuart/Kconfig
@@ -3,4 +3,22 @@ config VUART_FRAMEWORK
 
 menu "UART Emulation"
 
+config VUART_NS16X50
+	bool "NS16550-compatible UART Emulator" if EXPERT
+	depends on X86 && HVM
+	select VUART_FRAMEWORK
+	help
+	  In-hypervisor NS16x50 UART emulation.
+
+	  Only legacy PC COM2 port is emulated.
+
+	  This is strictly for testing purposes (such as early HVM guest console),
+	  and not appropriate for use in production.
+
+config VUART_NS16X50_DEBUG
+	bool "NS16550-compatible UART Emulator Debugging"
+	depends on VUART_NS16X50 && DEBUG
+	help
+	  Enable development debugging.
+
 endmenu
diff --git a/xen/common/emul/vuart/Makefile b/xen/common/emul/vuart/Makefile
index 97f792dc6641..fe904f6cb65d 100644
--- a/xen/common/emul/vuart/Makefile
+++ b/xen/common/emul/vuart/Makefile
@@ -1 +1,2 @@
 obj-y += vuart.o
+obj-$(CONFIG_VUART_NS16X50) += ns16x50.o
diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
new file mode 100644
index 000000000000..f0479e1022fb
--- /dev/null
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -0,0 +1,362 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * NS16550-compatible UART Emulator.
+ *
+ * See:
+ * - Serial and UART Tutorial:
+ *     https://download.freebsd.org/doc/en/articles/serial-uart/serial-uart_en.pdf
+ * - UART w/ 16 byte FIFO:
+ *     https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
+ * - UART w/ 64 byte FIFO:
+ *     https://www.ti.com/lit/ds/symlink/tl16c750.pdf
+ *
+ * Limitations:
+ * - Only x86;
+ * - Only Xen console as a backend, no inter-domain communication (similar to
+ *   vpl011 on Arm);
+ * - Only 8n1 emulation (8-bit data, no parity, 1 stop bit);
+ * - No baud rate emulation (reports 115200 baud to the guest OS);
+ * - No FIFO-less mode emulation;
+ * - No RX FIFO interrupt moderation (FCR) emulation;
+ * - No integration w/ VM snapshotting (HVM_REGISTER_SAVE_RESTORE() and
+ *   friends);
+ * - No ISA IRQ sharing allowed;
+ * - No MMIO-based UART emulation.
+ */
+
+#define pr_prefix               "ns16x50"
+#define pr_fmt(fmt)             pr_prefix ": " fmt
+
+#ifdef CONFIG_VUART_NS16X50_DEBUG
+#define guest_prefix            "FROM GUEST "
+#define ns16x50_log_level       2
+#else
+#define guest_prefix            ""
+#define ns16x50_log_level       0
+#endif
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define ns16x50_log(n, lvl, vdev, fmt, args...) do { \
+    if ( ns16x50_log_level >= n) \
+        gprintk(lvl, pr_fmt("%s: " fmt), (vdev)->name, ## args); \
+} while (0)
+
+#define ns16x50_err(vdev, fmt, args...) \
+    ns16x50_log(0, KERN_ERR, vdev, fmt, ## args)
+#define ns16x50_warn(vdev, fmt, args...) \
+    ns16x50_log(1, KERN_WARNING, vdev, fmt, ## args)
+#define ns16x50_info(vdev, fmt, args...) \
+    ns16x50_log(2, KERN_INFO, vdev, fmt, ## args)
+#define ns16x50_debug(vdev, fmt, args...) \
+    ns16x50_log(3, KERN_DEBUG, vdev, fmt, ## args)
+
+/*
+ * Number of supported registers in the UART.
+ */
+#define NS16X50_REGS_NUM        (UART_SCR + 1)
+
+/*
+ * Number of emulated registers.
+ *
+ * - Emulated registers [0..NS16X50_REGS_NUM] are R/W registers for DLAB=0.
+ * - DLAB=1, R/W, DLL            = NS16X50_REGS_NUM + 0
+ * - DLAB=1, R/W, DLM            = NS16X50_REGS_NUM + 1
+ * -         R/O, IIR (IIR_THR)  = NS16X50_REGS_NUM + 2
+ */
+#define NS16X50_EMU_REGS_NUM    (NS16X50_REGS_NUM + 3)
+
+/*
+ * Virtual ns16x50 device state.
+ */
+struct vuart_ns16x50 {
+    struct xencons_interface cons;      /* Emulated RX/TX FIFOs */
+    uint8_t regs[NS16X50_EMU_REGS_NUM]; /* Emulated registers */
+    const char *name;                   /* Device name */
+    struct domain *owner;               /* Owner domain */
+    const struct vuart_info *info;      /* UART description */
+    spinlock_t lock;                    /* Protection */
+};
+
+/*
+ * Emulate 8-bit write access to ns16x50 register.
+ */
+static int ns16x50_io_write8(
+    struct vuart_ns16x50 *vdev, uint32_t reg, uint8_t *data)
+{
+    int rc = 0;
+
+    return rc;
+}
+
+/*
+ * Emulate 16-bit write access to ns16x50 register.
+ * NB: some guest OSes use outw() to access UART_DLL.
+ */
+static int ns16x50_io_write16(
+    struct vuart_ns16x50 *vdev, uint32_t reg, uint16_t *data)
+{
+    int rc = -EINVAL;
+
+    return rc;
+}
+
+/*
+ * Emulate write access to ns16x50 register.
+ */
+static int ns16x50_io_write(
+    struct vuart_ns16x50 *vdev, uint8_t reg, uint32_t size, uint32_t *data)
+{
+    int rc;
+
+    switch ( size )
+    {
+    case 1:
+        rc = ns16x50_io_write8(vdev, reg, (uint8_t *)data);
+        break;
+
+    case 2:
+        rc = ns16x50_io_write16(vdev, reg, (uint16_t *)data);
+        break;
+
+    default:
+        rc = -EINVAL;
+        break;
+    }
+
+    return rc;
+}
+
+/*
+ * Emulate 8-bit read access to ns16x50 register.
+ */
+static int ns16x50_io_read8(
+    struct vuart_ns16x50 *vdev, uint32_t reg, uint8_t *data)
+{
+    uint8_t val = 0xff;
+    int rc = 0;
+
+    *data = val;
+
+    return rc;
+}
+
+/*
+ * Emulate 16-bit read access to ns16x50 register.
+ */
+static int ns16x50_io_read16(
+    struct vuart_ns16x50 *vdev, uint32_t reg, uint16_t *data)
+{
+    uint16_t val = 0xffff;
+    int rc = -EINVAL;
+
+    *data = val;
+
+    return rc;
+}
+
+/*
+ * Emulate read access to ns16x50 register.
+ */
+static int ns16x50_io_read(
+    struct vuart_ns16x50 *vdev, uint8_t reg, uint32_t size, uint32_t *data)
+{
+    int rc;
+
+    switch ( size )
+    {
+    case 1:
+        rc = ns16x50_io_read8(vdev, reg, (uint8_t *)data);
+        break;
+
+    case 2:
+        rc = ns16x50_io_read16(vdev, reg, (uint16_t *)data);
+        break;
+
+    default:
+        *data = 0xffffffff;
+        rc = -EINVAL;
+        break;
+    }
+
+    return rc;
+}
+
+/*
+ * Emulate I/O access to ns16x50 register.
+ * Note, emulation always returns X86EMUL_OKAY, once I/O port trap is enabled.
+ */
+static int cf_check ns16x50_io_handle(
+    int dir, unsigned int addr, unsigned int size, uint32_t *data)
+{
+#define op(dir)     (((dir) == IOREQ_WRITE) ? 'W' : 'R')
+    struct domain *d = rcu_lock_current_domain();
+    struct vuart *vuart = vuart_find_by_io_range(d, addr, size);
+    struct vuart_ns16x50 *vdev;
+    const struct domain *owner;
+    const struct vuart_info *info;
+    uint32_t reg;
+    unsigned dlab;
+    int rc;
+
+    if ( !vuart || !vuart->vdev )
+    {
+        printk(KERN_ERR "%c io 0x%04x %d: not initialized\n",
+               op(dir), addr, size);
+
+        ASSERT_UNREACHABLE();
+        goto out;
+    }
+    vdev = vuart->vdev;
+
+    owner = vuart->owner;
+    ASSERT(owner);
+    if ( d != owner )
+    {
+        ns16x50_err(vdev, "%c io 0x%04x %d: does not match current domain %pv\n",
+                    op(dir), addr, size, d);
+
+        ASSERT_UNREACHABLE();
+        goto out;
+    }
+
+    info = vuart->info;
+    ASSERT(info);
+    reg = addr - info->base_addr;
+    if ( !IS_ALIGNED(reg, size) )
+    {
+        ns16x50_err(vdev, "%c 0x%04x %d: unaligned access\n",
+                    op(dir), addr, size);
+        goto out;
+    }
+
+    dlab = 0;
+    if ( reg >= NS16X50_REGS_NUM )
+    {
+        ns16x50_err(vdev, "%c io 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32": not implemented\n",
+                    op(dir), addr, size, dlab, reg, *data);
+        goto out;
+    }
+
+    spin_lock(&vdev->lock);
+
+    if ( dir == IOREQ_WRITE )
+    {
+        ns16x50_debug(vdev, "%c 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32"\n",
+                      op(dir), addr, size, dlab, reg, *data);
+        rc = ns16x50_io_write(vdev, reg, size, data);
+    }
+    else
+    {
+        rc = ns16x50_io_read(vdev, reg, size, data);
+        ns16x50_debug(vdev, "%c 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32"\n",
+                      op(dir), addr, size, dlab, reg, *data);
+    }
+    if ( rc < 0 )
+        ns16x50_err(vdev, "%c 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32": unsupported access\n",
+                    op(dir), addr, size, dlab, reg, *data);
+
+    spin_unlock(&vdev->lock);
+
+out:
+    rcu_unlock_domain(d);
+
+    return X86EMUL_OKAY;
+#undef op
+}
+
+static int ns16x50_init(void *arg)
+{
+    struct vuart_ns16x50 *vdev = arg;
+    const struct vuart_info *info = vdev->info;
+    struct domain *d = vdev->owner;
+
+    ASSERT(vdev);
+
+    register_portio_handler(d, info->base_addr, info->size, ns16x50_io_handle);
+
+    return 0;
+}
+
+static void cf_check ns16x50_deinit(void *arg)
+{
+    struct vuart_ns16x50 *vdev = arg;
+
+    ASSERT(vdev);
+}
+
+static void * cf_check ns16x50_alloc(struct domain *d, const struct vuart_info *info)
+{
+    struct vuart_ns16x50 *vdev;
+    int rc;
+
+    if ( !info )
+        return ERR_PTR(-EINVAL);
+
+    if ( vuart_find_by_io_range(d, info->base_addr, info->size) )
+    {
+        ns16x50_err(info, "already registered\n");
+        return ERR_PTR(-EBUSY);
+    }
+
+    if ( !is_hvm_domain(d) )
+    {
+        ns16x50_err(info, "not an HVM domain\n");
+        return ERR_PTR(-ENOSYS);
+    }
+
+    vdev = xvzalloc(typeof(*vdev));
+    if ( !vdev )
+    {
+        ns16x50_err(info, "failed to allocate memory\n");
+        return ERR_PTR(-ENOMEM);
+    }
+
+    /* Save convenience pointer. */
+    vdev->name = info->name;
+    vdev->owner = d;
+    vdev->info = info;
+
+    rc = ns16x50_init(vdev);
+    if ( rc )
+        return ERR_PTR(rc);
+
+    return vdev;
+}
+
+static void cf_check ns16x50_free(void *arg)
+{
+    struct vuart_ns16x50 *vdev = arg;
+
+    if ( vdev )
+        ns16x50_deinit(vdev);
+
+    XVFREE(vdev);
+}
+
+#define ns16x50_emulator                \
+{                                       \
+    .compatible = "ns16550",            \
+    .alloc      = ns16x50_alloc,        \
+    .free       = ns16x50_free,         \
+    .dump_state = NULL,                 \
+    .put_rx     = NULL,                 \
+}
+
+VUART_REGISTER(ns16x50, ns16x50_emulator);
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
index 02bdc256ce37..613f4596e33d 100644
--- a/xen/include/xen/sched.h
+++ b/xen/include/xen/sched.h
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -660,6 +661,9 @@ struct domain
     struct {
         /* Permission to take ownership of the physical console input. */
         bool input_allowed;
+#ifdef CONFIG_VUART_FRAMEWORK
+        struct vuart *vuart;
+#endif
     } console;
 } __aligned(PAGE_SIZE);
 
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 05/15] emul/ns16x50: implement EIR/IIR registers
Date: Thu, 28 Aug 2025 16:53:59 -0700
Message-ID: <20250828235409.2835815-6-dmukhin@ford.com>
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From: Denis Mukhin  

Add interrupt enable register emulation (EIR) and interrupt identity reason
(IIR) register emulation to the I/O port handler.

Also add routines for asserting/deasserting the virtual ns16x50 interrupt
line as a dependent on IIR code.

Poke ns16x50_irq_check() on every I/O register access because the emulator
does not have clock emulation anyway (e.g. for baud rate emulation).

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 177 +++++++++++++++++++++++++++++++-
 1 file changed, 176 insertions(+), 1 deletion(-)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index f9f307a4ad24..20597cc36b35 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -85,9 +85,131 @@ struct vuart_ns16x50 {
     spinlock_t lock;                    /* Protection */
 };
 
+static bool ns16x50_fifo_rx_empty(const struct vuart_ns16x50 *vdev)
+{
+    const struct xencons_interface *cons = &vdev->cons;
+
+    return cons->in_prod == cons->in_cons;
+}
+
 static inline uint8_t cf_check ns16x50_dlab_get(const struct vuart_ns16x50 *vdev)
 {
-    return 0;
+    return vdev->regs[UART_LCR] & UART_LCR_DLAB ? 1 : 0;
+}
+
+static bool cf_check ns16x50_iir_check_lsi(const struct vuart_ns16x50 *vdev)
+{
+    return vdev->regs[UART_LSR] & UART_LSR_MASK;
+}
+
+static bool cf_check ns16x50_iir_check_rda(const struct vuart_ns16x50 *vdev)
+{
+    return !ns16x50_fifo_rx_empty(vdev);
+}
+
+static bool cf_check ns16x50_iir_check_thr(const struct vuart_ns16x50 *vdev)
+{
+    return vdev->regs[NS16X50_REGS_NUM + UART_IIR] & UART_IIR_THR;
+}
+
+static bool cf_check ns16x50_iir_check_msi(const struct vuart_ns16x50 *vdev)
+{
+    return vdev->regs[UART_MSR] & UART_MSR_CHANGE;
+}
+
+/*
+ * Get the interrupt identity reason.
+ *
+ * IIR is re-calculated once called, because ns16x50 always reports high
+ * priority events first.
+ * regs[NS16X50_REGS_NUM + UART_IIR] is used to store THR reason only.
+ */
+static uint8_t ns16x50_iir_get(const struct vuart_ns16x50 *vdev)
+{
+    /*
+     * Interrupt identity reasons by priority.
+     * NB: high priority are at lower indexes below.
+     */
+    static const struct {
+        bool (*check)(const struct vuart_ns16x50 *vdev);
+        uint8_t ier;
+        uint8_t iir;
+    } iir_by_prio[] = {
+        [0] = { ns16x50_iir_check_lsi, UART_IER_ELSI,   UART_IIR_LSI },
+        [1] = { ns16x50_iir_check_rda, UART_IER_ERDAI,  UART_IIR_RDA },
+        [2] = { ns16x50_iir_check_thr, UART_IER_ETHREI, UART_IIR_THR },
+        [3] = { ns16x50_iir_check_msi, UART_IER_EMSI,   UART_IIR_MSI },
+    };
+    const uint8_t *regs = vdev->regs;
+    uint8_t iir = 0;
+    unsigned int i;
+
+    /*
+     * NB: every interaction w/ ns16x50 registers (except DLAB=1) goes
+     * through that call.
+     */
+    ASSERT(spin_is_locked(&vdev->lock));
+
+    for ( i = 0; i < ARRAY_SIZE(iir_by_prio); i++ )
+    {
+        if ( (regs[UART_IER] & iir_by_prio[i].ier) &&
+             iir_by_prio[i].check(vdev) )
+            break;
+
+    }
+    if ( i == ARRAY_SIZE(iir_by_prio) )
+        iir |= UART_IIR_NOINT;
+    else
+        iir |= iir_by_prio[i].iir;
+
+    if ( regs[UART_FCR] & UART_FCR_ENABLE )
+        iir |= UART_IIR_FE;
+
+    return iir;
+}
+
+static void ns16x50_irq_assert(const struct vuart_ns16x50 *vdev)
+{
+    struct domain *d = vdev->owner;
+    const struct vuart_info *info = vdev->info;
+    int vector;
+
+    if ( has_vpic(d) ) /* HVM */
+        vector = hvm_isa_irq_assert(d, info->irq, vioapic_get_vector);
+    else
+        ASSERT_UNREACHABLE();
+
+    ns16x50_debug(vdev, "IRQ#%d vector %d assert\n", info->irq, vector);
+}
+
+static void ns16x50_irq_deassert(const struct vuart_ns16x50 *vdev)
+{
+    struct domain *d = vdev->owner;
+    const struct vuart_info *info = vdev->info;
+
+    if ( has_vpic(d) ) /* HVM */
+        hvm_isa_irq_deassert(d, info->irq);
+    else
+        ASSERT_UNREACHABLE();
+
+    ns16x50_debug(vdev, "IRQ#%d deassert\n", info->irq);
+}
+
+/*
+ * Assert/deassert virtual ns16x50 interrupt line.
+ */
+static void ns16x50_irq_check(const struct vuart_ns16x50 *vdev)
+{
+    uint8_t iir = ns16x50_iir_get(vdev);
+    const struct vuart_info *info = vdev->info;
+
+    if ( iir & UART_IIR_NOINT )
+        ns16x50_irq_assert(vdev);
+    else
+        ns16x50_irq_deassert(vdev);
+
+    ns16x50_debug(vdev, "IRQ#%d IIR 0x%02x %s\n", info->irq, iir,
+                  (iir & UART_IIR_NOINT) ? "deassert" : "assert");
 }
 
 /*
@@ -102,6 +224,29 @@ static int ns16x50_io_write8(
 
     if ( ns16x50_dlab_get(vdev) && (reg == UART_DLL || reg == UART_DLM) )
         regs[NS16X50_REGS_NUM + reg] = val;
+    else
+    {
+        switch ( reg )
+        {
+        case UART_IER:
+            /*
+             * NB: Make sure THR interrupt is re-triggered once guest OS
+             * re-enabled ETHREI in EIR.
+             */
+            if ( val & regs[UART_IER] & UART_IER_ETHREI )
+                regs[NS16X50_REGS_NUM + UART_IIR] |= UART_IIR_THR;
+
+            regs[UART_IER] = val & UART_IER_MASK;
+
+            break;
+
+        default:
+            rc = -EINVAL;
+            break;
+        }
+
+        ns16x50_irq_check(vdev);
+    }
 
     return rc;
 }
@@ -164,6 +309,29 @@ static int ns16x50_io_read8(
 
     if ( ns16x50_dlab_get(vdev) && (reg == UART_DLL || reg == UART_DLM) )
         val = regs[NS16X50_REGS_NUM + reg];
+    else {
+        switch ( reg )
+        {
+        case UART_IER:
+            val = regs[UART_IER];
+            break;
+
+        case UART_IIR: /* RO */
+            val = ns16x50_iir_get(vdev);
+
+            /* NB: clear IIR scratch location */
+            if ( val & UART_IIR_THR )
+                regs[NS16X50_REGS_NUM + UART_IIR] &= ~UART_IIR_THR;
+
+            break;
+
+        default:
+            rc = -EINVAL;
+            break;
+        }
+
+        ns16x50_irq_check(vdev);
+    }
 
     *data = val;
 
@@ -314,8 +482,15 @@ static int ns16x50_init(void *arg)
     vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & 0xff;
     vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
 
+    /* ns16x50 shall assert UART_IIR_THR whenever transmitter is empty. */
+    vdev->regs[NS16X50_REGS_NUM + UART_IIR] = UART_IIR_THR;
+
     register_portio_handler(d, info->base_addr, info->size, ns16x50_io_handle);
 
+    spin_lock(&vdev->lock);
+    ns16x50_irq_check(vdev);
+    spin_unlock(&vdev->lock);
+
     return 0;
 }
 
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 04/15] emul/ns16x50: implement DLL/DLM registers
Date: Thu, 28 Aug 2025 16:53:58 -0700
Message-ID: <20250828235409.2835815-5-dmukhin@ford.com>
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From: Denis Mukhin  

Add DLL/DLM registers emulation.

DLL/DLM registers report hardcoded 115200 baud rate to the guest OS.

Add stub for ns16x50_dlab_get() helper.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 36 ++++++++++++++++++++++++++++++++-
 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index f0479e1022fb..f9f307a4ad24 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -85,14 +85,24 @@ struct vuart_ns16x50 {
     spinlock_t lock;                    /* Protection */
 };
 
+static inline uint8_t cf_check ns16x50_dlab_get(const struct vuart_ns16x50 *vdev)
+{
+    return 0;
+}
+
 /*
  * Emulate 8-bit write access to ns16x50 register.
  */
 static int ns16x50_io_write8(
     struct vuart_ns16x50 *vdev, uint32_t reg, uint8_t *data)
 {
+    uint8_t *regs = vdev->regs;
+    uint8_t val = *data;
     int rc = 0;
 
+    if ( ns16x50_dlab_get(vdev) && (reg == UART_DLL || reg == UART_DLM) )
+        regs[NS16X50_REGS_NUM + reg] = val;
+
     return rc;
 }
 
@@ -103,8 +113,16 @@ static int ns16x50_io_write8(
 static int ns16x50_io_write16(
     struct vuart_ns16x50 *vdev, uint32_t reg, uint16_t *data)
 {
+    uint16_t val = *data;
     int rc = -EINVAL;
 
+    if ( ns16x50_dlab_get(vdev) && reg == UART_DLL )
+    {
+        vdev->regs[NS16X50_REGS_NUM + UART_DLL] = val & 0xff;
+        vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (val >> 8) & 0xff;
+        rc = 0;
+    }
+
     return rc;
 }
 
@@ -140,9 +158,13 @@ static int ns16x50_io_write(
 static int ns16x50_io_read8(
     struct vuart_ns16x50 *vdev, uint32_t reg, uint8_t *data)
 {
+    uint8_t *regs = vdev->regs;
     uint8_t val = 0xff;
     int rc = 0;
 
+    if ( ns16x50_dlab_get(vdev) && (reg == UART_DLL || reg == UART_DLM) )
+        val = regs[NS16X50_REGS_NUM + reg];
+
     *data = val;
 
     return rc;
@@ -157,6 +179,13 @@ static int ns16x50_io_read16(
     uint16_t val = 0xffff;
     int rc = -EINVAL;
 
+    if ( ns16x50_dlab_get(vdev) && reg == UART_DLL )
+    {
+        val = vdev->regs[NS16X50_REGS_NUM + UART_DLM] << 8 |
+              vdev->regs[NS16X50_REGS_NUM + UART_DLL];
+        rc = 0;
+    }
+
     *data = val;
 
     return rc;
@@ -237,7 +266,7 @@ static int cf_check ns16x50_io_handle(
         goto out;
     }
 
-    dlab = 0;
+    dlab = ns16x50_dlab_get(vdev);
     if ( reg >= NS16X50_REGS_NUM )
     {
         ns16x50_err(vdev, "%c io 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32": not implemented\n",
@@ -274,12 +303,17 @@ out:
 
 static int ns16x50_init(void *arg)
 {
+    const uint16_t divisor = (UART_CLOCK_HZ / 115200) >> 4;
     struct vuart_ns16x50 *vdev = arg;
     const struct vuart_info *info = vdev->info;
     struct domain *d = vdev->owner;
 
     ASSERT(vdev);
 
+    /* NB: report 115200 baud rate. */
+    vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & 0xff;
+    vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
+
     register_portio_handler(d, info->base_addr, info->size, ns16x50_io_handle);
 
     return 0;
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 00/15] x86: introduce NS16550-compatible UART emulator
Date: Thu, 28 Aug 2025 16:53:54 -0700
Message-ID: <20250828235409.2835815-1-dmukhin@ford.com>
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x86 port of Xen lacks vUART facility similar to Arm's vpl011 to support x86
guest OS bring up in the embedded setups.

This patch series introduces initial in-hypervisor emulator for
NS8250/NS16x50-compatible UARTs under CONFIG_VUART_NS16X50.

In parallel domain creation scenario (hyperlaunch), NS16550 emulator helps
early guest firmware and OS bringup debugging, because it eliminates
dependency on the external emulator (qemu) being operational by the time
domains are created.

The emulator also allows to forward the physical console input to the x86
domain which is useful when a system has only one physical UART for early
debugging and this UART is owned by Xen.

By default, CONFIG_VUART_NS16X50 enables emulation of NS16550 at I/O port
0x2f8, IRQ#3 in guest OS (legacy COM2). Legacy COM resources cannot be
selected at built-time or via per-domain xl configuration in this initial
submission.

CONFIG_VUART_NS16X50_DEBUG enables some extra debugging facilities useful
for NS16550 emulator development/debugging (disabled by default).

The NS16550 emulator is disabled in default x86 configuration and goes under
CONFIG_EXPERT in Kconfig.

Limitations
===========
- Only x86;
- Only HVM domains support (build-time), PVH domains are not supported yet;
- Only legacy COM{1,2,3,4} resources via Kconfig, custom I/O ports/IRQs
  are not supported;
- Only Xen console as a backend, no inter-domain communication (similar to
  vpl011 on Arm);
- Only 8n1 emulation (8-bit data, no parity, 1 stop bit);
- No toolstack integration;
- No baud rate emulation (reports 115200 baud to the guest OS);
- No FIFO-less mode emulation;
- No RX FIFO interrupt moderation (FCR) emulation;
- No integration w/ VM snapshotting (HVM_REGISTER_SAVE_RESTORE() and
  friends);
- No ISA IRQ sharing allowed;
- No MMIO-based UART emulation.

Series
======

  Patch 1 introduces the new vUART framework, that is the code originally
  posted here:
    https://lore.kernel.org/xen-devel/20250624035443.344099-16-dmukhin@ford.com/
  Required for emulator.

  Patch 2 adds missing NS16550 definitions, required for emulator.

  Patch 3 introduces the basic emulator skeleton - state machine
  initialization stubs, I/O port handler stub, logging, etc.

  Patches 4-10 incrementally populate the minimal NS16550 register emulation.

  Patch 11 hooks vUART to console driver and enables physical console intput
  forwarding.

  Patch 12 hooks vUART state debugging (disabled by default).

  Pathes 13-15 introduce necessary changes to enable NS16550 on dom0 (and PVH).

Link to CI: https://gitlab.com/xen-project/people/dmukhin/xen/-/pipelines/2009685553
Link to branch: https://gitlab.com/xen-project/people/dmukhin/xen/-/tree/vuart-ns8250-v5?ref_type=heads

Testing
=======

  ```shell
  echo CONFIG_EXPERT=y >> .config
  echo CONFIG_VUART_NS16X50=y >> .config
  make olddefconfig
  ```
  COM2 (0x2f8) resources are used by default.

  To test w/ virtual COM2, the guest kernel parameters should contain
  something like the following:
    earlycon=uart,io,0x2f8,115200n8 console=uart,io,0x2f8,115200n8

  HVM
  ---
  Tested only boot of HVM linux guest with OVMF as the virtual firmware.
  SeaBIOS as a virtual firmware is not tested.

  PVH (dom0)
  ----------
  Xen is able to forward physical console input to the domain with virtual
  NS16550. To switch the console focus press Ctrl+aaa.
  Switch is limited on x86 to dom0 and Xen (fixes pending).
  With COM2, Linux kernel complains nobody cared about IRQ#3. Likely that's
  because guest DSDT needs patching, which is a follow on change, but not
  critical for demonstration; the code is disabled in default config.

Changes since v4:
- Split the series to make it simpler to review.
- Addressed feedback from v4.
- Dropped xl changes, which I will submit separately.
- Link to v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-1-dmukhin@ford.com/

Changes since v3:
- Reduced the blast radius of the series, thanks to reviews, individual
  aspects (like console focus) touched in v3 moved to separate threads.
- Kept the UART emulator framework since I need to redo some of emulator code
  and there's more-or-less agreement on it (where to place, naming, scope).
- Applied the feedback from
    https://lore.kernel.org/xen-devel/20250624035443.344099-1-dmukhin@ford.com/
- Link to v3: https://lore.kernel.org/xen-devel/20250103-vuart-ns8250-v3-v1-0-c5d36b31d66c@ford.com/

Changes since v2:
- renamed emulator s/NS8250/NS16550/g
- reduced the patch series after addressing v2 feedback
- introduced driver framework for UART emulators
- unified guest OS printouts across all available UART emulators
- Link to v2: https://lore.kernel.org/xen-devel/20241205-vuart-ns8250-v1-0-e9aa923127eb@ford.com/

Changes since v1:
- dropped kmalloc/kfree aliases
- fixed ECLAIR jobs (thanks Andrew Cooper)
- addressed console forwarding on arm32 and arm64 (thanks to Luca Fancellu)
- moved NS8250 debugging stubs into its own patch
- added fix for https://gitlab.com/xen-project/xen/-/issues/184
- Link to v1: https://lore.kernel.org/r/20241126-vuart-ns8250-v1-v1-0-87b9a8375b7a@ford.com

Denis Mukhin (15):
  emul/vuart: introduce framework for UART emulators
  xen/8250-uart: update definitions
  emul/ns16x50: implement emulator stub
  emul/ns16x50: implement DLL/DLM registers
  emul/ns16x50: implement EIR/IIR registers
  emul/ns16x50: implement THR/RBR registers
  emul/ns16x50: implement FCR register (write-only)
  emul/ns16x50: implement LCR/LSR registers
  emul/ns16x50: implement MCR/MSR registers
  emul/ns16x50: implement SCR register
  emul/ns16x50: implement put_rx() hook
  emul/ns16550: implement dump_state() hook
  x86/domain: enable per-domain I/O port bitmaps
  xen/domain: allocate d->irq_caps before arch-specific initialization
  emul/ns16x50: implement IRQ emulation via vIOAPIC

 xen/arch/arm/xen.lds.S                   |   1 +
 xen/arch/ppc/xen.lds.S                   |   1 +
 xen/arch/riscv/xen.lds.S                 |   1 +
 xen/arch/x86/Makefile                    |   1 +
 xen/arch/x86/dom0_build.c                | 112 +--
 xen/arch/x86/domain.c                    |   2 +-
 xen/arch/x86/hvm/dom0_build.c            |   7 +
 xen/arch/x86/hvm/hvm.c                   |  55 +-
 xen/arch/x86/hvm/nestedhvm.c             |   8 +-
 xen/arch/x86/hvm/quirks.c                |   3 -
 xen/arch/x86/hvm/svm/nestedsvm.c         |   2 +-
 xen/arch/x86/hvm/vioapic.c               |  10 +
 xen/arch/x86/hvm/vmx/vvmx.c              |   4 +-
 xen/arch/x86/include/asm/hvm/nestedhvm.h |   3 +-
 xen/arch/x86/include/asm/hvm/support.h   |   2 -
 xen/arch/x86/include/asm/iocap.h         |   2 +
 xen/arch/x86/include/asm/irq.h           |   5 +-
 xen/arch/x86/ioport.c                    | 163 ++++
 xen/arch/x86/irq.c                       |  12 +-
 xen/arch/x86/physdev.c                   |   8 +-
 xen/arch/x86/pv/dom0_build.c             |   7 +
 xen/arch/x86/xen.lds.S                   |   1 +
 xen/common/Kconfig                       |   2 +
 xen/common/Makefile                      |   1 +
 xen/common/domain.c                      |   8 +-
 xen/common/emul/Kconfig                  |   6 +
 xen/common/emul/Makefile                 |   1 +
 xen/common/emul/vuart/Kconfig            |  24 +
 xen/common/emul/vuart/Makefile           |   2 +
 xen/common/emul/vuart/ns16x50.c          | 976 +++++++++++++++++++++++
 xen/common/emul/vuart/vuart.c            | 156 ++++
 xen/common/keyhandler.c                  |   3 +
 xen/drivers/char/console.c               |   6 +-
 xen/drivers/char/ns16550.c               |  16 +-
 xen/drivers/passthrough/x86/hvm.c        |  13 +-
 xen/include/xen/8250-uart.h              |  50 +-
 xen/include/xen/sched.h                  |   4 +
 xen/include/xen/serial.h                 |   3 +
 xen/include/xen/vuart.h                  | 116 +++
 xen/include/xen/xen.lds.h                |  10 +
 40 files changed, 1624 insertions(+), 183 deletions(-)
 create mode 100644 xen/arch/x86/ioport.c
 create mode 100644 xen/common/emul/Kconfig
 create mode 100644 xen/common/emul/Makefile
 create mode 100644 xen/common/emul/vuart/Kconfig
 create mode 100644 xen/common/emul/vuart/Makefile
 create mode 100644 xen/common/emul/vuart/ns16x50.c
 create mode 100644 xen/common/emul/vuart/vuart.c
 create mode 100644 xen/include/xen/vuart.h

-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 06/15] emul/ns16x50: implement THR/RBR registers
Date: Thu, 28 Aug 2025 16:54:00 -0700
Message-ID: <20250828235409.2835815-7-dmukhin@ford.com>
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From: Denis Mukhin  

Add RBR/THR registers emulation to the I/O port handlder.

Also, add RX/TX FIFO management code since RBR depends on RX FIFO and
THR depends on TX FIFO.

FIFOs are not emulated as per UART specs for simplicity (not need to emulate
baud rate). Emulator does not emulate NS8250 (no FIFO), NS16550a (16 bytes) or
NS16750 (64 bytes).

FIFOs are emulated by means of using xencons_interface which conveniently
provides primitives for buffer management and later can be used for
inter-domain communication similarly to vpl011.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 135 ++++++++++++++++++++++++++++++++
 1 file changed, 135 insertions(+)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 20597cc36b35..efb2f4c6441c 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -92,6 +92,119 @@ static bool ns16x50_fifo_rx_empty(const struct vuart_ns16x50 *vdev)
     return cons->in_prod == cons->in_cons;
 }
 
+static bool ns16x50_fifo_rx_full(const struct vuart_ns16x50 *vdev)
+{
+    const struct xencons_interface *cons = &vdev->cons;
+
+    return cons->in_prod - cons->in_cons == ARRAY_SIZE(cons->in);
+}
+
+static void ns16x50_fifo_rx_reset(struct vuart_ns16x50 *vdev)
+{
+    struct xencons_interface *cons = &vdev->cons;
+
+    cons->in_cons = cons->in_prod;
+}
+
+static int ns16x50_fifo_rx_getchar(struct vuart_ns16x50 *vdev)
+{
+    struct xencons_interface *cons = &vdev->cons;
+    int rc;
+
+    if ( ns16x50_fifo_rx_empty(vdev) )
+    {
+        ns16x50_debug(vdev, "RX FIFO empty\n");
+        rc = -ENODATA;
+    }
+    else
+    {
+        rc = cons->in[MASK_XENCONS_IDX(cons->in_cons, cons->in)];
+        cons->in_cons++;
+    }
+
+    return rc;
+}
+
+static int ns16x50_fifo_rx_putchar(struct vuart_ns16x50 *vdev, char c)
+{
+    struct xencons_interface *cons = &vdev->cons;
+    int rc;
+
+    /*
+     * FIFO-less 8250/16450 UARTs: newly arrived word overwrites the contents
+     * of the THR.
+     */
+    if ( ns16x50_fifo_rx_full(vdev) )
+    {
+        ns16x50_debug(vdev, "RX FIFO full; resetting\n");
+        ns16x50_fifo_rx_reset(vdev);
+        rc = -ENOSPC;
+    }
+    else
+        rc = 0;
+
+    cons->in[MASK_XENCONS_IDX(cons->in_prod, cons->in)] = c;
+    cons->in_prod++;
+
+    return rc;
+}
+
+static bool ns16x50_fifo_tx_empty(const struct vuart_ns16x50 *vdev)
+{
+    const struct xencons_interface *cons = &vdev->cons;
+
+    return cons->out_prod == cons->out_cons;
+}
+
+static void ns16x50_fifo_tx_reset(struct vuart_ns16x50 *vdev)
+{
+    struct xencons_interface *cons = &vdev->cons;
+
+    cons->out_prod = 0;
+    ASSERT(cons->out_cons == cons->out_prod);
+}
+
+/*
+ * Flush cached output to Xen console.
+ */
+static void ns16x50_fifo_tx_flush(struct vuart_ns16x50 *vdev)
+{
+    struct xencons_interface *cons = &vdev->cons;
+    struct domain *d = vdev->owner;
+
+    if ( ns16x50_fifo_tx_empty(vdev) )
+        return;
+
+    ASSERT(cons->out_prod < ARRAY_SIZE(cons->out));
+    cons->out[cons->out_prod] = '\0';
+    cons->out_prod++;
+
+    guest_printk(d, guest_prefix "%s", cons->out);
+
+    ns16x50_fifo_tx_reset(vdev);
+}
+
+/*
+ * Accumulate guest OS output before sending to Xen console.
+ */
+static void ns16x50_fifo_tx_putchar(struct vuart_ns16x50 *vdev, char ch)
+{
+    struct xencons_interface *cons = &vdev->cons;
+
+    if ( !is_console_printable(ch) )
+        return;
+
+    if ( ch != '\0' )
+    {
+        cons->out[cons->out_prod] = ch;
+        cons->out_prod++;
+    }
+
+    if ( cons->out_prod == ARRAY_SIZE(cons->out) - 1 ||
+         ch == '\n' || ch == '\0' )
+        ns16x50_fifo_tx_flush(vdev);
+}
+
 static inline uint8_t cf_check ns16x50_dlab_get(const struct vuart_ns16x50 *vdev)
 {
     return vdev->regs[UART_LCR] & UART_LCR_DLAB ? 1 : 0;
@@ -228,6 +341,16 @@ static int ns16x50_io_write8(
     {
         switch ( reg )
         {
+        case UART_THR:
+            if ( regs[UART_MCR] & UART_MCR_LOOP )
+                rc = ns16x50_fifo_rx_putchar(vdev, val);
+            else
+                ns16x50_fifo_tx_putchar(vdev, val);
+
+            rc = 0;
+
+            break;
+
         case UART_IER:
             /*
              * NB: Make sure THR interrupt is re-triggered once guest OS
@@ -312,6 +435,14 @@ static int ns16x50_io_read8(
     else {
         switch ( reg )
         {
+        case UART_RBR:
+            rc = ns16x50_fifo_rx_getchar(vdev);
+            if ( rc >= 0 )
+                val = (uint8_t)rc;
+
+            rc = 0;
+            break;
+
         case UART_IER:
             val = regs[UART_IER];
             break;
@@ -499,6 +630,10 @@ static void cf_check ns16x50_deinit(void *arg)
     struct vuart_ns16x50 *vdev = arg;
 
     ASSERT(vdev);
+
+    spin_lock(&vdev->lock);
+    ns16x50_fifo_tx_flush(vdev);
+    spin_unlock(&vdev->lock);
 }
 
 static void * cf_check ns16x50_alloc(struct domain *d, const struct vuart_info *info)
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 07/15] emul/ns16x50: implement FCR register (write-only)
Date: Thu, 28 Aug 2025 16:54:01 -0700
Message-ID: <20250828235409.2835815-8-dmukhin@ford.com>
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From: Denis Mukhin  

Add emulation logic for FCR register.

Note, that does not hooks FIFO interrupt moderation to the FIFO management
code.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index efb2f4c6441c..65ca96dd8bd3 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -363,6 +363,30 @@ static int ns16x50_io_write8(
 
             break;
 
+        case UART_FCR: /* WO */
+            if ( val & UART_FCR_RESERVED0 )
+                ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
+                             UART_FCR_RESERVED0);
+
+            if ( val & UART_FCR_RESERVED1 )
+                ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
+                             UART_FCR_RESERVED1);
+
+            if ( val & UART_FCR_CLRX )
+                ns16x50_fifo_rx_reset(vdev);
+
+            if ( val & UART_FCR_CLTX )
+                ns16x50_fifo_tx_flush(vdev);
+
+            if ( val & UART_FCR_ENABLE )
+                val &= UART_FCR_ENABLE | UART_FCR_DMA | UART_FCR_TRG_MASK;
+            else
+                val = 0;
+
+            regs[UART_FCR] = val;
+
+            break;
+
         default:
             rc = -EINVAL;
             break;
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 08/15] emul/ns16x50: implement LCR/LSR registers
Date: Thu, 28 Aug 2025 16:54:02 -0700
Message-ID: <20250828235409.2835815-9-dmukhin@ford.com>
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From: Denis Mukhin  

Add LCR/LSR registers implementation to the I/O port handler.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 65ca96dd8bd3..687a7ea2fabe 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -347,6 +347,9 @@ static int ns16x50_io_write8(
             else
                 ns16x50_fifo_tx_putchar(vdev, val);
 
+            if ( rc == -ENOSPC )
+                regs[UART_LSR] |= UART_LSR_OE;
+
             rc = 0;
 
             break;
@@ -387,6 +390,11 @@ static int ns16x50_io_write8(
 
             break;
 
+        case UART_LCR:
+            regs[UART_LCR] = val;
+            break;
+
+        case UART_LSR: /* RO */
         default:
             rc = -EINVAL;
             break;
@@ -460,6 +468,9 @@ static int ns16x50_io_read8(
         switch ( reg )
         {
         case UART_RBR:
+            /* NB: do not forget to clear overrun condition */
+            regs[UART_LSR] &= ~UART_LSR_OE;
+
             rc = ns16x50_fifo_rx_getchar(vdev);
             if ( rc >= 0 )
                 val = (uint8_t)rc;
@@ -480,6 +491,21 @@ static int ns16x50_io_read8(
 
             break;
 
+        case UART_LCR:
+            val = regs[UART_LCR];
+            break;
+
+        case UART_LSR:
+            val = regs[UART_LSR] | UART_LSR_THRE | UART_LSR_TEMT;
+            if ( ns16x50_fifo_rx_empty(vdev) )
+                val &= ~UART_LSR_DR;
+            else
+                val |= UART_LSR_DR;
+
+            regs[UART_LSR] = val & ~UART_LSR_MASK;
+
+            break;
+
         default:
             rc = -EINVAL;
             break;
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 09/15] emul/ns16x50: implement MCR/MSR registers
Date: Thu, 28 Aug 2025 16:54:03 -0700
Message-ID: <20250828235409.2835815-10-dmukhin@ford.com>
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From: Denis Mukhin  

Add MCR/MCR registers emulation to the I/O port handler.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 60 +++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 687a7ea2fabe..670c3c6dba9d 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -394,7 +394,58 @@ static int ns16x50_io_write8(
             regs[UART_LCR] = val;
             break;
 
+        case UART_MCR: {
+            uint8_t msr_curr, msr_next, msr_delta;
+
+            msr_curr = regs[UART_MSR];
+            msr_next = 0;
+            msr_delta = 0;
+
+            if ( val & UART_MCR_RESERVED0 )
+                ns16x50_warn(vdev, "MCR: attempt to set reserved bit: %x\n",
+                             UART_MCR_RESERVED0);
+
+            if ( val & UART_MCR_TCRTLR )
+                ns16x50_warn(vdev, "MCR: not supported: %x\n",
+                             UART_MCR_TCRTLR);
+
+            if ( val & UART_MCR_RESERVED1 )
+                ns16x50_warn(vdev, "MCR: attempt to set reserved bit: %x\n",
+                             UART_MCR_RESERVED1);
+
+            /* Set modem status */
+            if ( val & UART_MCR_LOOP )
+            {
+                if ( val & UART_MCR_DTR )
+                    msr_next |= UART_MSR_DSR;
+                if ( val & UART_MCR_RTS )
+                    msr_next |= UART_MSR_CTS;
+                if ( val & UART_MCR_OUT1 )
+                    msr_next |= UART_MSR_RI;
+                if ( val & UART_MCR_OUT2 )
+                    msr_next |= UART_MSR_DCD;
+            }
+            else
+                msr_next |= UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
+
+            /* Calculate changes in modem status */
+            if ( (msr_curr & UART_MSR_CTS) ^ (msr_next & UART_MSR_CTS) )
+                msr_delta |= UART_MSR_DCTS;
+            if ( (msr_curr & UART_MSR_DSR) ^ (msr_next & UART_MSR_DSR) )
+                msr_delta |= UART_MSR_DDSR;
+            if ( (msr_curr & UART_MSR_RI)  & (msr_next & UART_MSR_RI) )
+                msr_delta |= UART_MSR_TERI;
+            if ( (msr_curr & UART_MSR_DCD) ^ (msr_next & UART_MSR_DCD) )
+                msr_delta |= UART_MSR_DDCD;
+
+            regs[UART_MCR] = val & UART_MCR_MASK;
+            regs[UART_MSR] = msr_next | msr_delta;
+
+            break;
+        }
+
         case UART_LSR: /* RO */
+        case UART_MSR: /* RO */
         default:
             rc = -EINVAL;
             break;
@@ -495,6 +546,10 @@ static int ns16x50_io_read8(
             val = regs[UART_LCR];
             break;
 
+        case UART_MCR:
+            val = regs[UART_MCR];
+            break;
+
         case UART_LSR:
             val = regs[UART_LSR] | UART_LSR_THRE | UART_LSR_TEMT;
             if ( ns16x50_fifo_rx_empty(vdev) )
@@ -506,6 +561,11 @@ static int ns16x50_io_read8(
 
             break;
 
+        case UART_MSR:
+            val = regs[UART_MSR];
+            regs[UART_MSR] &= ~UART_MSR_CHANGE;
+            break;
+
         default:
             rc = -EINVAL;
             break;
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 10/15] emul/ns16x50: implement SCR register
Date: Thu, 28 Aug 2025 16:54:04 -0700
Message-ID: <20250828235409.2835815-11-dmukhin@ford.com>
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From: Denis Mukhin  

Add SCR register emulation to the I/O port handler.
Firmware (e.g. OVMF) may use SCR during the guest OS boot.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 670c3c6dba9d..d57695564329 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -444,6 +444,11 @@ static int ns16x50_io_write8(
             break;
         }
 
+        /* NB: Firmware (e.g. OVMF) may rely on SCR presence. */
+        case UART_SCR:
+            regs[UART_SCR] = val;
+            break;
+
         case UART_LSR: /* RO */
         case UART_MSR: /* RO */
         default:
@@ -566,6 +571,10 @@ static int ns16x50_io_read8(
             regs[UART_MSR] &= ~UART_MSR_CHANGE;
             break;
 
+        case UART_SCR:
+            val = regs[UART_SCR];
+            break;
+
         default:
             rc = -EINVAL;
             break;
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 11/15] emul/ns16x50: implement put_rx() hook
Date: Thu, 28 Aug 2025 16:54:05 -0700
Message-ID: <20250828235409.2835815-12-dmukhin@ford.com>
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From: Denis Mukhin  

Implement put_rx() vUART hook for placing a character into the emulated RX
FIFO from console driver.

That implements physical console forwarding to the guest OS over emulated
NS16550.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 48 ++++++++++++++++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index d57695564329..1fb65370d464 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -804,13 +804,59 @@ static void cf_check ns16x50_free(void *arg)
     XVFREE(vdev);
 }
 
+static int cf_check ns16x50_put_rx(void *arg, char ch)
+{
+    struct vuart_ns16x50 *vdev = arg;
+    uint8_t *regs;
+    uint8_t dlab;
+    int rc = -EBUSY;
+
+    spin_lock(&vdev->lock);
+
+    dlab = ns16x50_dlab_get(vdev);
+    regs = vdev->regs;
+
+    if ( dlab )
+        ns16x50_debug(vdev, "THR/RBR access disabled: DLAB=1\n");
+    else if ( regs[UART_MCR] & UART_MCR_LOOP )
+        ns16x50_debug(vdev, "THR/RBR access disabled: loopback mode\n");
+    else
+    {
+        struct vuart *vuart = container_of(arg, struct vuart, vdev);
+        struct domain *d = vuart->owner;
+        uint8_t val = 0;
+
+        rc = ns16x50_fifo_rx_putchar(vdev, ch);
+        if ( rc == -ENOSPC )
+            val |= UART_LSR_OE;
+
+        /* NB: UART_LSR_DR is also set when UART_LSR is accessed. */
+        regs[UART_LSR] |= UART_LSR_DR | val;
+
+        /*
+         * Echo the user input on Xen console iff Xen console input is owned
+         * by ns16x50 domain.
+         * NB: use 'console_timestamps=none' to disable Xen timestamps.
+         */
+        if ( is_console_printable(ch) )
+            guest_printk(d, "%c", ch);
+
+        /* FIXME: check FCR when to fire an interrupt */
+        ns16x50_irq_check(vdev);
+    }
+
+    spin_unlock(&vdev->lock);
+
+    return rc;
+}
+
 #define ns16x50_emulator                \
 {                                       \
     .compatible = "ns16550",            \
     .alloc      = ns16x50_alloc,        \
     .free       = ns16x50_free,         \
     .dump_state = NULL,                 \
-    .put_rx     = NULL,                 \
+    .put_rx     = ns16x50_put_rx,       \
 }
 
 VUART_REGISTER(ns16x50, ns16x50_emulator);
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 12/15] emul/ns16550: implement dump_state() hook
Date: Thu, 28 Aug 2025 16:54:06 -0700
Message-ID: <20250828235409.2835815-13-dmukhin@ford.com>
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From: Denis Mukhin  

Implement dump_state() vUART hook for debugging UART state machine over Xen
console. dump_state() prints state of all emulated registers (including
state-less IIR) and state of RX/TX FIFOs.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
---
 xen/common/emul/vuart/ns16x50.c | 59 ++++++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 1fb65370d464..5c1be854b544 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -636,6 +636,58 @@ static int ns16x50_io_read(
     return rc;
 }
 
+static void cf_check ns16x50_dump_state(void *arg)
+{
+#ifdef CONFIG_VUART_NS16X50_DEBUG
+    struct vuart_ns16x50 *vdev = arg;
+    const struct domain *d = vdev->owner;
+    const struct vuart_info *info = vdev->info;
+    const struct xencons_interface *cons;
+    const uint8_t *regs;
+
+    if ( !vdev )
+        return;
+
+    /* Allow printing state in case of a deadlock. */
+    if ( !spin_trylock(&vdev->lock) )
+        return;
+
+    cons = &vdev->cons;
+    regs = &vdev->regs[0];
+
+    printk("Virtual " pr_prefix " (%s) I/O port 0x%04"PRIx64" IRQ#%d owner %pd\n",
+            vdev->name, info->base_addr, info->irq, d);
+
+    printk("  RX FIFO size %ld in_prod %d in_cons %d used %d\n",
+            ARRAY_SIZE(cons->in), cons->in_prod, cons->in_cons,
+            cons->in_prod - cons->in_cons);
+
+    printk("  TX FIFO size %ld out_prod %d out_cons %d used %d\n",
+            ARRAY_SIZE(cons->out), cons->out_prod, cons->out_cons,
+            cons->out_prod - cons->out_cons);
+
+    printk("  %02"PRIx8" RBR %02"PRIx8" THR %02"PRIx8" DLL %02"PRIx8" DLM %02"PRIx8"\n",
+            UART_RBR,
+            cons->in[MASK_XENCONS_IDX(cons->in_prod, cons)],
+            cons->out[MASK_XENCONS_IDX(cons->out_prod, cons)],
+            regs[NS16X50_REGS_NUM + UART_DLL],
+            regs[NS16X50_REGS_NUM + UART_DLM]);
+
+    printk("  %02"PRIx8" IER %02"PRIx8"\n", UART_IER, regs[UART_IER]);
+
+    printk("  %02"PRIx8" FCR %02"PRIx8" IIR %02"PRIx8"\n",
+            UART_FCR, regs[UART_FCR], ns16x50_iir_get(vdev));
+
+    printk("  %02"PRIx8" LCR %02"PRIx8"\n", UART_LCR, regs[UART_LCR]);
+    printk("  %02"PRIx8" MCR %02"PRIx8"\n", UART_MCR, regs[UART_MCR]);
+    printk("  %02"PRIx8" LSR %02"PRIx8"\n", UART_LSR, regs[UART_LSR]);
+    printk("  %02"PRIx8" MSR %02"PRIx8"\n", UART_MSR, regs[UART_MSR]);
+    printk("  %02"PRIx8" SCR %02"PRIx8"\n", UART_SCR, regs[UART_SCR]);
+
+    spin_unlock(&vdev->lock);
+#endif /* CONFIG_VUART_NS16X50_DEBUG */
+}
+
 /*
  * Emulate I/O access to ns16x50 register.
  * Note, emulation always returns X86EMUL_OKAY, once I/O port trap is enabled.
@@ -712,6 +764,9 @@ static int cf_check ns16x50_io_handle(
 
     spin_unlock(&vdev->lock);
 
+    if ( ns16x50_log_level >= 3 ) 
+        ns16x50_dump_state(vdev);
+
 out:
     rcu_unlock_domain(d);
 
@@ -846,6 +901,8 @@ static int cf_check ns16x50_put_rx(void *arg, char ch)
     }
 
     spin_unlock(&vdev->lock);
+    if ( ns16x50_log_level >= 3 )
+        ns16x50_dump_state(vdev);
 
     return rc;
 }
@@ -855,7 +912,7 @@ static int cf_check ns16x50_put_rx(void *arg, char ch)
     .compatible = "ns16550",            \
     .alloc      = ns16x50_alloc,        \
     .free       = ns16x50_free,         \
-    .dump_state = NULL,                 \
+    .dump_state = ns16x50_dump_state,   \
     .put_rx     = ns16x50_put_rx,       \
 }
 
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 13/15] x86/domain: enable per-domain I/O port bitmaps
Date: Thu, 28 Aug 2025 16:54:07 -0700
Message-ID: <20250828235409.2835815-14-dmukhin@ford.com>
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From: Denis Mukhin  

Current design enables all HVM domains share the same I/O port bitmap.

It is necessary for domains crafting its own I/O port address space depending
on the user configuration.

Ensure NS16550 emulator does not share I/O ports with the physical I/O ports,
which is essential for emulation in PVH hwdom case (dom0).

Not a functional change.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch 
- Link tp v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-4-dmukhin@ford.com/
---
 xen/arch/x86/Makefile                    |   1 +
 xen/arch/x86/dom0_build.c                | 111 +--------------
 xen/arch/x86/hvm/hvm.c                   |  35 +----
 xen/arch/x86/hvm/nestedhvm.c             |   8 +-
 xen/arch/x86/hvm/quirks.c                |   3 -
 xen/arch/x86/hvm/svm/nestedsvm.c         |   2 +-
 xen/arch/x86/hvm/vmx/vvmx.c              |   4 +-
 xen/arch/x86/include/asm/hvm/nestedhvm.h |   3 +-
 xen/arch/x86/include/asm/hvm/support.h   |   2 -
 xen/arch/x86/include/asm/iocap.h         |   2 +
 xen/arch/x86/ioport.c                    | 163 +++++++++++++++++++++++
 xen/arch/x86/pv/dom0_build.c             |   4 +
 xen/common/emul/vuart/ns16x50.c          |  11 ++
 13 files changed, 200 insertions(+), 149 deletions(-)
 create mode 100644 xen/arch/x86/ioport.c

diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
index 9d67ea7cd4a8..5726ecc180eb 100644
--- a/xen/arch/x86/Makefile
+++ b/xen/arch/x86/Makefile
@@ -44,6 +44,7 @@ obj-y += msi.o
 obj-y += msr.o
 obj-$(CONFIG_INDIRECT_THUNK) += indirect-thunk.o
 obj-$(CONFIG_RETURN_THUNK) += indirect-thunk.o
+obj-y += ioport.o
 obj-$(CONFIG_PV) += ioport_emulate.o
 obj-y += irq.o
 obj-$(CONFIG_KEXEC) += machine_kexec.o
diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c
index 0b467fd4a4fc..26202b33345c 100644
--- a/xen/arch/x86/dom0_build.c
+++ b/xen/arch/x86/dom0_build.c
@@ -298,9 +298,6 @@ int __init parse_arch_dom0_param(const char *s, const char *e)
     return 0;
 }
 
-static char __initdata opt_dom0_ioports_disable[200] = "";
-string_param("dom0_ioports_disable", opt_dom0_ioports_disable);
-
 static bool __initdata ro_hpet = true;
 boolean_param("ro-hpet", ro_hpet);
 
@@ -433,122 +430,20 @@ unsigned long __init dom0_compute_nr_pages(
     return nr_pages;
 }
 
-static void __init process_dom0_ioports_disable(struct domain *dom0)
-{
-    unsigned long io_from, io_to;
-    char *t, *s = opt_dom0_ioports_disable;
-    const char *u;
-
-    if ( *s == '\0' )
-        return;
-
-    while ( (t = strsep(&s, ",")) != NULL )
-    {
-        io_from = simple_strtoul(t, &u, 16);
-        if ( u == t )
-        {
-        parse_error:
-            printk("Invalid ioport range <%s> "
-                   "in dom0_ioports_disable, skipping\n", t);
-            continue;
-        }
-
-        if ( *u == '\0' )
-            io_to = io_from;
-        else if ( *u == '-' )
-            io_to = simple_strtoul(u + 1, &u, 16);
-        else
-            goto parse_error;
-
-        if ( (*u != '\0') || (io_to < io_from) || (io_to >= 65536) )
-            goto parse_error;
-
-        printk("Disabling dom0 access to ioport range %04lx-%04lx\n",
-            io_from, io_to);
-
-        if ( ioports_deny_access(dom0, io_from, io_to) != 0 )
-            BUG();
-    }
-}
-
+/* Modify I/O memory access permissions. */
 int __init dom0_setup_permissions(struct domain *d)
 {
     unsigned long mfn;
-    unsigned int i, offs;
-    int rc;
+    unsigned int i;
+    int rc = 0;
 
     if ( pv_shim )
         return 0;
 
-    /* The hardware domain is initially permitted full I/O capabilities. */
-    rc = ioports_permit_access(d, 0, 0xFFFF);
     rc |= iomem_permit_access(d, 0UL,
                               PFN_DOWN(1UL << domain_max_paddr_bits(d)) - 1);
     rc |= irqs_permit_access(d, 1, nr_irqs_gsi - 1);
 
-    /* Modify I/O port access permissions. */
-
-    for ( offs = 0, i = ISOLATE_LSB(i8259A_alias_mask) ?: 2;
-          offs <= i8259A_alias_mask; offs += i )
-    {
-        if ( offs & ~i8259A_alias_mask )
-            continue;
-        /* Master Interrupt Controller (PIC). */
-        rc |= ioports_deny_access(d, 0x20 + offs, 0x21 + offs);
-        /* Slave Interrupt Controller (PIC). */
-        rc |= ioports_deny_access(d, 0xA0 + offs, 0xA1 + offs);
-    }
-
-    /* ELCR of both PICs. */
-    rc |= ioports_deny_access(d, 0x4D0, 0x4D1);
-
-    /* Interval Timer (PIT). */
-    for ( offs = 0, i = ISOLATE_LSB(pit_alias_mask) ?: 4;
-          offs <= pit_alias_mask; offs += i )
-        if ( !(offs & ~pit_alias_mask) )
-            rc |= ioports_deny_access(d, PIT_CH0 + offs, PIT_MODE + offs);
-
-    /* PIT Channel 2 / PC Speaker Control. */
-    rc |= ioports_deny_access(d, 0x61, 0x61);
-
-    /* INIT# and alternative A20M# control. */
-    rc |= ioports_deny_access(d, 0x92, 0x92);
-
-    /* IGNNE# control. */
-    rc |= ioports_deny_access(d, 0xF0, 0xF0);
-
-    /* ACPI PM Timer. */
-    if ( pmtmr_ioport )
-        rc |= ioports_deny_access(d, pmtmr_ioport, pmtmr_ioport + 3);
-
-    /* Reset control. */
-    rc |= ioports_deny_access(d, 0xCF9, 0xCF9);
-
-    /* PCI configuration space (NB. 0xCF8 has special treatment). */
-    rc |= ioports_deny_access(d, 0xCFC, 0xCFF);
-
-#ifdef CONFIG_HVM
-    if ( is_hvm_domain(d) )
-    {
-        /* ISA DMA controller, channels 0-3 (incl possible aliases). */
-        rc |= ioports_deny_access(d, 0x00, 0x1F);
-        /* ISA DMA controller, page registers (incl various reserved ones). */
-        rc |= ioports_deny_access(d, 0x80 + !!hvm_port80_allowed, 0x8F);
-        /* ISA DMA controller, channels 4-7 (incl usual aliases). */
-        rc |= ioports_deny_access(d, 0xC0, 0xDF);
-
-        /* HVM debug console IO port. */
-        rc |= ioports_deny_access(d, XEN_HVM_DEBUGCONS_IOPORT,
-                                  XEN_HVM_DEBUGCONS_IOPORT);
-        if ( amd_acpi_c1e_quirk )
-            rc |= ioports_deny_access(d, acpi_smi_cmd, acpi_smi_cmd);
-    }
-#endif
-    /* Command-line I/O ranges. */
-    process_dom0_ioports_disable(d);
-
-    /* Modify I/O memory access permissions. */
-
     /* Local APIC. */
     if ( mp_lapic_addr != 0 )
     {
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 26760cf995df..12736fc61c11 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -51,6 +51,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -81,14 +82,6 @@ integer_param("hvm_debug", opt_hvm_debug_level);
 
 struct hvm_function_table __ro_after_init hvm_funcs;
 
-/*
- * The I/O permission bitmap is globally shared by all HVM guests except
- * the hardware domain which needs a more permissive one.
- */
-#define HVM_IOBITMAP_SIZE (3 * PAGE_SIZE)
-unsigned long __section(".bss.page_aligned") __aligned(PAGE_SIZE)
-    hvm_io_bitmap[HVM_IOBITMAP_SIZE / BYTES_PER_LONG];
-
 /* Xen command-line option to enable HAP */
 static bool __initdata opt_hap_enabled = true;
 boolean_param("hap", opt_hap_enabled);
@@ -205,15 +198,6 @@ static int __init cf_check hvm_enable(void)
     if ( opt_hvm_fep )
         warning_add(warning_hvm_fep);
 
-    /*
-     * Allow direct access to the PC debug ports 0x80 and 0xed (they are
-     * often used for I/O delays, but the vmexits simply slow things down).
-     */
-    memset(hvm_io_bitmap, ~0, sizeof(hvm_io_bitmap));
-    if ( hvm_port80_allowed )
-        __clear_bit(0x80, hvm_io_bitmap);
-    __clear_bit(0xed, hvm_io_bitmap);
-
     register_cpu_notifier(&cpu_nfb);
 
     return 0;
@@ -645,19 +629,12 @@ int hvm_domain_initialise(struct domain *d,
 
     rwlock_init(&d->arch.hvm.pl_time->pt_migrate);
 
-    /* Set the default IO Bitmap. */
-    if ( is_hardware_domain(d) )
+    rc = ioports_setup_access(d);
+    if ( rc )
     {
-        d->arch.hvm.io_bitmap = _xmalloc(HVM_IOBITMAP_SIZE, PAGE_SIZE);
-        if ( d->arch.hvm.io_bitmap == NULL )
-        {
-            rc = -ENOMEM;
-            goto fail1;
-        }
-        memset(d->arch.hvm.io_bitmap, ~0, HVM_IOBITMAP_SIZE);
+        printk("%pd failed to setup I/O bitmap: %d\n", d, rc);
+        goto fail1;
     }
-    else
-        d->arch.hvm.io_bitmap = hvm_io_bitmap;
 
     register_g2m_portio_handler(d);
     register_vpci_portio_handler(d);
@@ -684,6 +661,8 @@ int hvm_domain_initialise(struct domain *d,
         break;
     }
 
+    BUG_ON(!d->arch.ioport_caps);
+
     vpic_init(d);
 
     rc = vioapic_init(d);
diff --git a/xen/arch/x86/hvm/nestedhvm.c b/xen/arch/x86/hvm/nestedhvm.c
index bddd77d8109b..d4e03123d910 100644
--- a/xen/arch/x86/hvm/nestedhvm.c
+++ b/xen/arch/x86/hvm/nestedhvm.c
@@ -107,7 +107,7 @@ nestedhvm_vmcx_flushtlb(struct p2m_domain *p2m)
  * The users of the bitmap patterns are in SVM/VMX specific code.
  *
  * bitmap        port 0x80  port 0xed
- * hvm_io_bitmap cleared    cleared
+ * hvm.io_bitmap cleared    cleared
  * iomap[0]      cleared    set
  * iomap[1]      set        cleared
  * iomap[2]      set        set
@@ -115,7 +115,7 @@ nestedhvm_vmcx_flushtlb(struct p2m_domain *p2m)
 
 static int __init cf_check nestedhvm_setup(void)
 {
-    /* Same format and size as hvm_io_bitmap (Intel needs only 2 pages). */
+    /* Same format and size as hvm.io_bitmap (Intel needs only 2 pages). */
     unsigned nr = cpu_has_vmx ? 2 : 3;
     unsigned int i, order = get_order_from_pages(nr);
 
@@ -165,7 +165,7 @@ static int __init cf_check nestedhvm_setup(void)
 __initcall(nestedhvm_setup);
 
 unsigned long *
-nestedhvm_vcpu_iomap_get(bool ioport_80, bool ioport_ed)
+nestedhvm_vcpu_iomap_get(struct vcpu *v, bool ioport_80, bool ioport_ed)
 {
     int i;
 
@@ -174,7 +174,7 @@ nestedhvm_vcpu_iomap_get(bool ioport_80, bool ioport_ed)
 
     if (ioport_80 == 0) {
         if (ioport_ed == 0)
-            return hvm_io_bitmap;
+            return v->domain->arch.hvm.io_bitmap;
         i = 0;
     } else {
         if (ioport_ed == 0)
diff --git a/xen/arch/x86/hvm/quirks.c b/xen/arch/x86/hvm/quirks.c
index 9202f5a47fe9..f4d95441fcff 100644
--- a/xen/arch/x86/hvm/quirks.c
+++ b/xen/arch/x86/hvm/quirks.c
@@ -73,9 +73,6 @@ static int __init cf_check check_port80(void)
 
     dmi_check_system(hvm_no_port80_dmi_table);
 
-    if ( !hvm_port80_allowed )
-        __set_bit(0x80, hvm_io_bitmap);
-
     return 0;
 }
 __initcall(check_port80);
diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nestedsvm.c
index dc2b6a42534a..cc8500b61665 100644
--- a/xen/arch/x86/hvm/svm/nestedsvm.c
+++ b/xen/arch/x86/hvm/svm/nestedsvm.c
@@ -381,7 +381,7 @@ static int nsvm_vmrun_permissionmap(struct vcpu *v, bool viopm)
         hvm_unmap_guest_frame(ns_viomap, 0);
     }
 
-    svm->ns_iomap = nestedhvm_vcpu_iomap_get(ioport_80, ioport_ed);
+    svm->ns_iomap = nestedhvm_vcpu_iomap_get(v, ioport_80, ioport_ed);
 
     nv->nv_ioport80 = ioport_80;
     nv->nv_ioportED = ioport_ed;
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index e4f3a5fe4c71..4da3e6e90e6c 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -554,7 +554,7 @@ unsigned long *_shadow_io_bitmap(struct vcpu *v)
     port80 = bitmap[0x80 >> 3] & (1 << (0x80 & 0x7)) ? 1 : 0;
     portED = bitmap[0xed >> 3] & (1 << (0xed & 0x7)) ? 1 : 0;
 
-    return nestedhvm_vcpu_iomap_get(port80, portED);
+    return nestedhvm_vcpu_iomap_get(v, port80, portED);
 }
 
 static void update_msrbitmap(struct vcpu *v, uint32_t shadow_ctrl)
@@ -622,7 +622,7 @@ void nvmx_update_exec_control(struct vcpu *v, u32 host_cntrl)
              * L1 VMM doesn't intercept IO instruction.
              * Use host configuration and reset IO_BITMAP
              */
-            bitmap = hvm_io_bitmap;
+            bitmap = v->domain->arch.hvm.io_bitmap;
         }
         else {
             /* use IO bitmap */
diff --git a/xen/arch/x86/include/asm/hvm/nestedhvm.h b/xen/arch/x86/include/asm/hvm/nestedhvm.h
index ea2c1bc328c7..d691ccb07dd6 100644
--- a/xen/arch/x86/include/asm/hvm/nestedhvm.h
+++ b/xen/arch/x86/include/asm/hvm/nestedhvm.h
@@ -50,7 +50,8 @@ int nestedhvm_hap_nested_page_fault(struct vcpu *v, paddr_t *L2_gpa,
                                     struct npfec npfec);
 
 /* IO permission map */
-unsigned long *nestedhvm_vcpu_iomap_get(bool ioport_80, bool ioport_ed);
+unsigned long *nestedhvm_vcpu_iomap_get(struct vcpu *v,
+                                        bool ioport_80, bool ioport_ed);
 
 /* Misc */
 #define nestedhvm_paging_mode_hap(v) (!!nhvm_vmcx_hap_enabled(v))
diff --git a/xen/arch/x86/include/asm/hvm/support.h b/xen/arch/x86/include/asm/hvm/support.h
index 2a7ba36af06f..7e36d00cc188 100644
--- a/xen/arch/x86/include/asm/hvm/support.h
+++ b/xen/arch/x86/include/asm/hvm/support.h
@@ -41,8 +41,6 @@ extern unsigned int opt_hvm_debug_level;
 #define HVM_DBG_LOG(level, _f, _a...) do {} while (0)
 #endif
 
-extern unsigned long hvm_io_bitmap[];
-
 enum hvm_translation_result {
     HVMTRANS_okay,
     HVMTRANS_bad_linear_to_gfn,
diff --git a/xen/arch/x86/include/asm/iocap.h b/xen/arch/x86/include/asm/iocap.h
index f948b7186e95..1083f6171cf7 100644
--- a/xen/arch/x86/include/asm/iocap.h
+++ b/xen/arch/x86/include/asm/iocap.h
@@ -22,6 +22,8 @@
 #define cache_flush_permitted(d) \
     (has_arch_io_resources(d) || has_arch_pdevs(d))
 
+int ioports_setup_access(struct domain *d);
+
 static inline int ioports_permit_access(struct domain *d, unsigned long s,
                                         unsigned long e)
 {
diff --git a/xen/arch/x86/ioport.c b/xen/arch/x86/ioport.c
new file mode 100644
index 000000000000..dbcd52d37a4f
--- /dev/null
+++ b/xen/arch/x86/ioport.c
@@ -0,0 +1,163 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Guest I/O port address space configuration.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static char __initdata opt_dom0_ioports_disable[200] = "";
+string_param("dom0_ioports_disable", opt_dom0_ioports_disable);
+
+/*
+ * The I/O permission bitmap size.
+ * See: comment in nestedhvm_setup()
+ */
+#define HVM_IOBITMAP_SIZE (3 * PAGE_SIZE)
+
+/* Hide user-defined I/O ports from the guest OS. */
+static void process_dom0_ioports_disable(struct domain *dom0)
+{
+    unsigned long io_from, io_to;
+    char *t, *s = opt_dom0_ioports_disable;
+    const char *u;
+
+    if ( *s == '\0' )
+        return;
+
+    while ( (t = strsep(&s, ",")) != NULL )
+    {
+        io_from = simple_strtoul(t, &u, 16);
+        if ( u == t )
+        {
+        parse_error:
+            printk("Invalid ioport range <%s> "
+                   "in dom0_ioports_disable, skipping\n", t);
+            continue;
+        }
+
+        if ( *u == '\0' )
+            io_to = io_from;
+        else if ( *u == '-' )
+            io_to = simple_strtoul(u + 1, &u, 16);
+        else
+            goto parse_error;
+
+        if ( (*u != '\0') || (io_to < io_from) || (io_to >= 65536) )
+            goto parse_error;
+
+        printk("Disabling dom0 access to ioport range %04lx-%04lx\n",
+            io_from, io_to);
+
+        if ( ioports_deny_access(dom0, io_from, io_to) != 0 )
+            BUG();
+    }
+}
+
+/* Set the default IO Bitmap. */
+int ioports_setup_access(struct domain *d)
+{
+    unsigned int i, offs;
+    int rc;
+
+    if ( pv_shim )
+        return 0;
+
+#ifdef CONFIG_HVM
+    d->arch.hvm.io_bitmap = _xmalloc(HVM_IOBITMAP_SIZE, PAGE_SIZE);
+    if ( d->arch.hvm.io_bitmap == NULL )
+        return -ENOMEM;
+
+    memset(d->arch.hvm.io_bitmap, ~0, HVM_IOBITMAP_SIZE);
+
+    if ( !is_hardware_domain(d) )
+    {
+        /*
+         * Allow direct access to the PC debug ports 0x80 and 0xed (they are
+         * often used for I/O delays, but the vmexits simply slow things down).
+         */
+        if ( hvm_port80_allowed )
+            __clear_bit(0x80, d->arch.hvm.io_bitmap);
+
+        __clear_bit(0xed, d->arch.hvm.io_bitmap);
+
+        return 0;
+    }
+#endif
+
+    /* The hardware domain is initially permitted full I/O capabilities. */
+    rc = ioports_permit_access(d, 0, 0xFFFF);
+
+    /* Modify I/O port access permissions. */
+
+    for ( offs = 0, i = ISOLATE_LSB(i8259A_alias_mask) ?: 2;
+          offs <= i8259A_alias_mask; offs += i )
+    {
+        if ( offs & ~i8259A_alias_mask )
+            continue;
+        /* Master Interrupt Controller (PIC). */
+        rc |= ioports_deny_access(d, 0x20 + offs, 0x21 + offs);
+        /* Slave Interrupt Controller (PIC). */
+        rc |= ioports_deny_access(d, 0xA0 + offs, 0xA1 + offs);
+    }
+
+    /* ELCR of both PICs. */
+    rc |= ioports_deny_access(d, 0x4D0, 0x4D1);
+
+    /* Interval Timer (PIT). */
+    for ( offs = 0, i = ISOLATE_LSB(pit_alias_mask) ?: 4;
+          offs <= pit_alias_mask; offs += i )
+        if ( !(offs & ~pit_alias_mask) )
+            rc |= ioports_deny_access(d, PIT_CH0 + offs, PIT_MODE + offs);
+
+    /* PIT Channel 2 / PC Speaker Control. */
+    rc |= ioports_deny_access(d, 0x61, 0x61);
+
+    /* INIT# and alternative A20M# control. */
+    rc |= ioports_deny_access(d, 0x92, 0x92);
+
+    /* IGNNE# control. */
+    rc |= ioports_deny_access(d, 0xF0, 0xF0);
+
+    /* ACPI PM Timer. */
+    if ( pmtmr_ioport )
+        rc |= ioports_deny_access(d, pmtmr_ioport, pmtmr_ioport + 3);
+
+    /* Reset control. */
+    rc |= ioports_deny_access(d, 0xCF9, 0xCF9);
+
+    /* PCI configuration space (NB. 0xCF8 has special treatment). */
+    rc |= ioports_deny_access(d, 0xCFC, 0xCFF);
+
+#ifdef CONFIG_HVM
+    if ( is_hvm_domain(d) )
+    {
+        /* ISA DMA controller, channels 0-3 (incl possible aliases). */
+        rc |= ioports_deny_access(d, 0x00, 0x1F);
+        /* ISA DMA controller, page registers (incl various reserved ones). */
+        rc |= ioports_deny_access(d, 0x80 + !!hvm_port80_allowed, 0x8F);
+        /* ISA DMA controller, channels 4-7 (incl usual aliases). */
+        rc |= ioports_deny_access(d, 0xC0, 0xDF);
+
+        /* HVM debug console IO port. */
+        rc |= ioports_deny_access(d, XEN_HVM_DEBUGCONS_IOPORT,
+                                  XEN_HVM_DEBUGCONS_IOPORT);
+        if ( amd_acpi_c1e_quirk )
+            rc |= ioports_deny_access(d, acpi_smi_cmd, acpi_smi_cmd);
+    }
+#endif
+
+    /* Command-line I/O ranges. */
+    process_dom0_ioports_disable(d);
+
+    return rc;
+}
diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c
index 21158ce1812e..2b8b4d869ee7 100644
--- a/xen/arch/x86/pv/dom0_build.c
+++ b/xen/arch/x86/pv/dom0_build.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1033,6 +1034,9 @@ static int __init dom0_construct(const struct boot_domain *bd)
     if ( test_bit(XENFEAT_supervisor_mode_kernel, parms.f_required) )
         panic("Dom0 requires supervisor-mode execution\n");
 
+    rc = ioports_setup_access(d);
+    BUG_ON(rc != 0);
+
     rc = dom0_setup_permissions(d);
     BUG_ON(rc != 0);
 
diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 5c1be854b544..8860f25ffdeb 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -780,9 +780,20 @@ static int ns16x50_init(void *arg)
     struct vuart_ns16x50 *vdev = arg;
     const struct vuart_info *info = vdev->info;
     struct domain *d = vdev->owner;
+    int rc;
 
     ASSERT(vdev);
 
+    /* Disallow sharing physical I/O port */
+    rc = ioports_deny_access(d, info->base_addr,
+                             info->base_addr + info->size - 1);
+    if ( rc )
+    {
+        ns16x50_err(info, " virtual I/O port range [0x%04lx"PRIx64"..0x%04lx"PRIx64"]: conflict w/ physical range\n",
+                    info->base_addr, info->base_addr + info->size - 1);
+        return rc;
+    }
+
     /* NB: report 115200 baud rate. */
     vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & 0xff;
     vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
-- 
2.51.0



From xen-devel-bounces@lists.xenproject.org Thu Aug 28 23:54:32 2025
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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 14/15] xen/domain: allocate d->irq_caps before arch-specific initialization
Date: Thu, 28 Aug 2025 16:54:08 -0700
Message-ID: <20250828235409.2835815-15-dmukhin@ford.com>
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In-Reply-To: <20250828235409.2835815-1-dmukhin@ford.com>
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From: Denis Mukhin  

Make sure that NS16550 emulator does not share virtual device IRQ with the
physical one. This is needed for enabling NS16550 emulator for PVH hwdom
(dom0).

To do that, move per-domain interrupt rangeset allocation before arch-specific
code. Add irqs_setup_access() to setup the initial rangeset.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- new patch
- Link to original patch in v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-4-dmukhin@ford.com/
---
 xen/arch/x86/dom0_build.c       | 1 -
 xen/arch/x86/hvm/dom0_build.c   | 7 +++++++
 xen/arch/x86/include/asm/irq.h  | 2 ++
 xen/arch/x86/irq.c              | 8 ++++++++
 xen/arch/x86/pv/dom0_build.c    | 3 +++
 xen/common/domain.c             | 8 ++++++--
 xen/common/emul/vuart/ns16x50.c | 9 +++++++++
 7 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c
index 26202b33345c..9dc87efbf3e8 100644
--- a/xen/arch/x86/dom0_build.c
+++ b/xen/arch/x86/dom0_build.c
@@ -442,7 +442,6 @@ int __init dom0_setup_permissions(struct domain *d)
 
     rc |= iomem_permit_access(d, 0UL,
                               PFN_DOWN(1UL << domain_max_paddr_bits(d)) - 1);
-    rc |= irqs_permit_access(d, 1, nr_irqs_gsi - 1);
 
     /* Local APIC. */
     if ( mp_lapic_addr != 0 )
diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_build.c
index 5551f9044836..245a42dec9aa 100644
--- a/xen/arch/x86/hvm/dom0_build.c
+++ b/xen/arch/x86/hvm/dom0_build.c
@@ -1348,6 +1348,13 @@ int __init dom0_construct_pvh(const struct boot_domain *bd)
          */
         pvh_setup_mmcfg(d);
 
+        rc = irqs_setup_access(d);
+        if ( rc )
+        {
+            printk("%pd unable to setup IRQ rangeset: %d\n", d, rc);
+            return rc;
+        }
+
         /*
          * Setup permissions early so that calls to add MMIO regions to the
          * p2m as part of vPCI setup don't fail due to permission checks.
diff --git a/xen/arch/x86/include/asm/irq.h b/xen/arch/x86/include/asm/irq.h
index 8c81f66434a8..8bffec3bbfee 100644
--- a/xen/arch/x86/include/asm/irq.h
+++ b/xen/arch/x86/include/asm/irq.h
@@ -231,4 +231,6 @@ int allocate_and_map_gsi_pirq(struct domain *d, int index, int *pirq_p);
 int allocate_and_map_msi_pirq(struct domain *d, int index, int *pirq_p,
                               int type, struct msi_info *msi);
 
+int irqs_setup_access(struct domain *d);
+
 #endif /* _ASM_HW_IRQ_H */
diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c
index 556134f85aa0..079277be719d 100644
--- a/xen/arch/x86/irq.c
+++ b/xen/arch/x86/irq.c
@@ -3046,3 +3046,11 @@ int allocate_and_map_msi_pirq(struct domain *d, int index, int *pirq_p,
 
     return ret;
 }
+
+int irqs_setup_access(struct domain *d)
+{
+    if ( is_hardware_domain(d) )
+        return irqs_permit_access(d, 1, nr_irqs_gsi - 1);
+
+    return 0;
+}
diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c
index 2b8b4d869ee7..1a092b802833 100644
--- a/xen/arch/x86/pv/dom0_build.c
+++ b/xen/arch/x86/pv/dom0_build.c
@@ -1037,6 +1037,9 @@ static int __init dom0_construct(const struct boot_domain *bd)
     rc = ioports_setup_access(d);
     BUG_ON(rc != 0);
 
+    rc = irqs_setup_access(d);
+    BUG_ON(rc != 0);
+
     rc = dom0_setup_permissions(d);
     BUG_ON(rc != 0);
 
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 104e917f07e3..eb83e3198f37 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -950,6 +950,11 @@ struct domain *domain_create(domid_t domid,
     radix_tree_init(&d->pirq_tree);
 #endif
 
+    err = -ENOMEM;
+    d->irq_caps = rangeset_new(d, "Interrupts", 0);
+    if ( !d->irq_caps )
+        goto fail;
+
     if ( (err = arch_domain_create(d, config, flags)) != 0 )
         goto fail;
     init_status |= INIT_arch;
@@ -959,8 +964,7 @@ struct domain *domain_create(domid_t domid,
 
     err = -ENOMEM;
     d->iomem_caps = rangeset_new(d, "I/O Memory", RANGESETF_prettyprint_hex);
-    d->irq_caps   = rangeset_new(d, "Interrupts", 0);
-    if ( !d->iomem_caps || !d->irq_caps )
+    if ( !d->iomem_caps )
         goto fail;
 
     if ( (err = xsm_domain_create(XSM_HOOK, d, config->ssidref)) != 0 )
diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index 8860f25ffdeb..aea38304b60c 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -794,6 +794,15 @@ static int ns16x50_init(void *arg)
         return rc;
     }
 
+    /* Disallow sharing physical IRQ */
+    rc = irq_deny_access(d, info->irq);
+    if ( rc )
+    {
+        ns16x50_err(info, "virtual IRQ#%d: conflict w/ physical IRQ: %d\n",
+                    info->irq, rc);
+        return rc;
+    }
+
     /* NB: report 115200 baud rate. */
     vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & 0xff;
     vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v5 15/15] emul/ns16x50: implement IRQ emulation via vIOAPIC
Date: Thu, 28 Aug 2025 16:54:09 -0700
Message-ID: <20250828235409.2835815-16-dmukhin@ford.com>
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In-Reply-To: <20250828235409.2835815-1-dmukhin@ford.com>
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From: Denis Mukhin  

PVH domains use vIOAPIC, not vPIC and NS16550 emulates ISA IRQs which cannot
be asserted on vIOAPIC.

{map,unmap}_domain_emuirq_pirq() infrastructure is modified by adding new
type of interrupt resources 'IRQ_EMU' which means 'emulated device IRQ'
(similarly to IRQ_MSI_EMU).

This is necessary to for IOAPIC emulation code to skip IRQ->PIRQ mapping
(vioapic_hwdom_map_gsi()) when guest OS unmasks vIOAPIC pin corresponding to
virtual device's IRQ.

Also, hvm_gsi_eoi() is modified to trigger assertion in hvm_gsi_deassert()
path for ISA IRQs.

Signed-off-by: Denis Mukhin 
---
Changes since v4:
- dropped xl bits
- cosmetic renames
- fix hvm_gsi_eoi()
- Link to v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-8-dmukhin@ford.com/
---
 xen/arch/x86/domain.c             |  2 +-
 xen/arch/x86/hvm/vioapic.c        | 10 ++++++++++
 xen/arch/x86/include/asm/irq.h    |  3 ++-
 xen/arch/x86/irq.c                |  4 ++--
 xen/arch/x86/physdev.c            |  8 ++++----
 xen/common/emul/vuart/ns16x50.c   | 32 +++++++++++++++++++++++++++++--
 xen/drivers/passthrough/x86/hvm.c | 13 ++++++++-----
 7 files changed, 57 insertions(+), 15 deletions(-)

diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 19fd86ce88d2..0815d0b31827 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1048,7 +1048,7 @@ int arch_domain_soft_reset(struct domain *d)
     write_lock(&d->event_lock);
     for ( i = 0; i < d->nr_pirqs ; i++ )
     {
-        if ( domain_pirq_to_emuirq(d, i) != IRQ_UNBOUND )
+        if ( domain_irq_to_emuirq(d, i) != IRQ_UNBOUND )
         {
             ret = unmap_domain_pirq_emuirq(d, i);
             if ( ret )
diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
index 7c725f9e471f..fd073f6fba4b 100644
--- a/xen/arch/x86/hvm/vioapic.c
+++ b/xen/arch/x86/hvm/vioapic.c
@@ -177,6 +177,16 @@ static int vioapic_hwdom_map_gsi(unsigned int gsi, unsigned int trig,
 
     ASSERT(is_hardware_domain(currd));
 
+    /*
+     * Interrupt is claimed by one of the platform virtual devices (e.g.
+     * NS16550); do nothing.
+     */
+    write_lock(&currd->event_lock);
+    ret = domain_irq_to_emuirq(currd, gsi);
+    write_unlock(&currd->event_lock);
+    if ( ret != IRQ_UNBOUND )
+        return 0;
+
     /* Interrupt has been unmasked, bind it now. */
     ret = mp_register_gsi(gsi, trig, pol);
     if ( ret == -EEXIST )
diff --git a/xen/arch/x86/include/asm/irq.h b/xen/arch/x86/include/asm/irq.h
index 8bffec3bbfee..3b24decb05e4 100644
--- a/xen/arch/x86/include/asm/irq.h
+++ b/xen/arch/x86/include/asm/irq.h
@@ -212,7 +212,7 @@ void cleanup_domain_irq_mapping(struct domain *d);
     __ret ? radix_tree_ptr_to_int(__ret) : 0;                   \
 })
 #define PIRQ_ALLOCATED (-1)
-#define domain_pirq_to_emuirq(d, pirq) pirq_field(d, pirq,              \
+#define domain_irq_to_emuirq(d, pirq) pirq_field(d, pirq,              \
     arch.hvm.emuirq, IRQ_UNBOUND)
 #define domain_emuirq_to_pirq(d, emuirq) ({                             \
     void *__ret = radix_tree_lookup(&(d)->arch.hvm.emuirq_pirq, emuirq);\
@@ -221,6 +221,7 @@ void cleanup_domain_irq_mapping(struct domain *d);
 #define IRQ_UNBOUND (-1)
 #define IRQ_PT      (-2)
 #define IRQ_MSI_EMU (-3)
+#define IRQ_EMU     (-4)
 
 bool cpu_has_pending_apic_eoi(void);
 
diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c
index 079277be719d..7a8093cd3238 100644
--- a/xen/arch/x86/irq.c
+++ b/xen/arch/x86/irq.c
@@ -2790,7 +2790,7 @@ int map_domain_emuirq_pirq(struct domain *d, int pirq, int emuirq)
         return -EINVAL;
     }
 
-    old_emuirq = domain_pirq_to_emuirq(d, pirq);
+    old_emuirq = domain_irq_to_emuirq(d, pirq);
     if ( emuirq != IRQ_PT )
         old_pirq = domain_emuirq_to_pirq(d, emuirq);
 
@@ -2845,7 +2845,7 @@ int unmap_domain_pirq_emuirq(struct domain *d, int pirq)
 
     ASSERT(rw_is_write_locked(&d->event_lock));
 
-    emuirq = domain_pirq_to_emuirq(d, pirq);
+    emuirq = domain_irq_to_emuirq(d, pirq);
     if ( emuirq == IRQ_UNBOUND )
     {
         dprintk(XENLOG_G_ERR, "dom%d: pirq %d not mapped\n",
diff --git a/xen/arch/x86/physdev.c b/xen/arch/x86/physdev.c
index 4dfa1c019105..90a9e7d2f120 100644
--- a/xen/arch/x86/physdev.c
+++ b/xen/arch/x86/physdev.c
@@ -145,7 +145,7 @@ int physdev_unmap_pirq(struct domain *d, int pirq)
     if ( is_hvm_domain(d) && has_pirq(d) )
     {
         write_lock(&d->event_lock);
-        if ( domain_pirq_to_emuirq(d, pirq) != IRQ_UNBOUND )
+        if ( domain_irq_to_emuirq(d, pirq) != IRQ_UNBOUND )
             ret = unmap_domain_pirq_emuirq(d, pirq);
         write_unlock(&d->event_lock);
         if ( d == current->domain || ret )
@@ -191,10 +191,10 @@ ret_t do_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
         if ( is_pv_domain(currd) || domain_pirq_to_irq(currd, eoi.irq) > 0 )
             pirq_guest_eoi(pirq);
         if ( is_hvm_domain(currd) &&
-             domain_pirq_to_emuirq(currd, eoi.irq) > 0 )
+             domain_irq_to_emuirq(currd, eoi.irq) > 0 )
         {
             struct hvm_irq *hvm_irq = hvm_domain_irq(currd);
-            int gsi = domain_pirq_to_emuirq(currd, eoi.irq);
+            int gsi = domain_irq_to_emuirq(currd, eoi.irq);
 
             /* if this is a level irq and count > 0, send another
              * notification */ 
@@ -267,7 +267,7 @@ ret_t do_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
         irq_status_query.flags = 0;
         if ( is_hvm_domain(currd) &&
              domain_pirq_to_irq(currd, irq) <= 0 &&
-             domain_pirq_to_emuirq(currd, irq) == IRQ_UNBOUND )
+             domain_irq_to_emuirq(currd, irq) == IRQ_UNBOUND )
         {
             ret = -EINVAL;
             break;
diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index aea38304b60c..1126b53c30df 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -287,7 +287,9 @@ static void ns16x50_irq_assert(const struct vuart_ns16x50 *vdev)
     const struct vuart_info *info = vdev->info;
     int vector;
 
-    if ( has_vpic(d) ) /* HVM */
+    if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */
+        vector = hvm_ioapic_assert(d, info->irq, false);
+    else if ( has_vpic(d) ) /* HVM */
         vector = hvm_isa_irq_assert(d, info->irq, vioapic_get_vector);
     else
         ASSERT_UNREACHABLE();
@@ -300,7 +302,9 @@ static void ns16x50_irq_deassert(const struct vuart_ns16x50 *vdev)
     struct domain *d = vdev->owner;
     const struct vuart_info *info = vdev->info;
 
-    if ( has_vpic(d) ) /* HVM */
+    if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */
+        hvm_ioapic_deassert(d, info->irq);
+    else if ( has_vpic(d) ) /* HVM */
         hvm_isa_irq_deassert(d, info->irq);
     else
         ASSERT_UNREACHABLE();
@@ -803,6 +807,17 @@ static int ns16x50_init(void *arg)
         return rc;
     }
 
+    /* Claim virtual IRQ */
+    write_lock(&d->event_lock);
+    rc = map_domain_emuirq_pirq(d, info->irq, IRQ_EMU);
+    write_unlock(&d->event_lock);
+    if ( rc )
+    {
+        ns16x50_err(info, "virtual IRQ#%d: cannot claim: %d\n",
+                    info->irq, rc);
+        return rc;
+    }
+
     /* NB: report 115200 baud rate. */
     vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & 0xff;
     vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
@@ -822,9 +837,22 @@ static int ns16x50_init(void *arg)
 static void cf_check ns16x50_deinit(void *arg)
 {
     struct vuart_ns16x50 *vdev = arg;
+    const struct vuart_info *info;
+    struct domain *d;
+    int rc;
 
     ASSERT(vdev);
 
+    d = vdev->owner;
+    info = vdev->info;
+
+    write_lock(&d->event_lock);
+    rc = unmap_domain_pirq_emuirq(d, info->irq);
+    write_unlock(&d->event_lock);
+    if ( rc )
+        ns16x50_err(vdev, "virtual IRQ#%d: cannot unclaim: %d\n",
+                    info->irq, rc);
+
     spin_lock(&vdev->lock);
     ns16x50_fifo_tx_flush(vdev);
     spin_unlock(&vdev->lock);
diff --git a/xen/drivers/passthrough/x86/hvm.c b/xen/drivers/passthrough/x86/hvm.c
index a2ca7e0e570c..11711d20a7ea 100644
--- a/xen/drivers/passthrough/x86/hvm.c
+++ b/xen/drivers/passthrough/x86/hvm.c
@@ -923,13 +923,16 @@ static void __hvm_dpci_eoi(struct domain *d,
 static void hvm_gsi_eoi(struct domain *d, unsigned int gsi)
 {
     struct pirq *pirq = pirq_info(d, gsi);
+    int rc;
+
+    /* Check if GSI is claimed by one of the virtual devices. */
+    rc = domain_irq_to_emuirq(d, gsi);
+    if ( rc != IRQ_UNBOUND )
+        hvm_gsi_deassert(d, gsi);
 
     /* Check if GSI is actually mapped. */
-    if ( !pirq_dpci(pirq) )
-        return;
-
-    hvm_gsi_deassert(d, gsi);
-    hvm_pirq_eoi(pirq);
+    if ( pirq_dpci(pirq) )
+        hvm_pirq_eoi(pirq);
 }
 
 static int cf_check _hvm_dpci_isairq_eoi(
-- 
2.51.0



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Message-ID: <24474024-0542-48e5-a1b8-bb534c7eeb4b@amd.com>
Date: Thu, 28 Aug 2025 20:16:33 -0400
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v8 3/8] xen/cpufreq: implement amd-cppc driver for CPPC in
 passive mode
To: Jan Beulich , Penny Zheng 
CC: , Andrew Cooper ,
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Anthony PERARD
	, Michal Orzel , "Julien
 Grall" , Stefano Stabellini ,
	
References: <20250828100306.1776031-1-Penny.Zheng@amd.com>
 <20250828100306.1776031-4-Penny.Zheng@amd.com>
 
Content-Language: en-US
From: Jason Andryuk 
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On 2025-08-28 07:22, Jan Beulich wrote:
> On 28.08.2025 12:03, Penny Zheng wrote:
>> +static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy,
>> +                                            unsigned int target_freq,
>> +                                            unsigned int relation)
>> +{
>> +    unsigned int cpu = policy->cpu;
>> +    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);
> 
> I fear there's a problem here that I so far overlooked. As it happens, just
> yesterday I made a patch to eliminate cpufreq_drv_data[] global. In the
> course of doing so it became clear that in principle the CPU denoted by
> policy->cpu can be offline. Hence its per-CPU data is also unavailable. See
> cpufreq_add_cpu()'s invocation of .init() and cpufreq_del_cpu()'s invocation
> of .exit(). Is there anything well-hidden (and likely lacking some suitable
> comment) which guarantees that no two CPUs (threads) will be in the same
> domain? If not, I fear you simply can't use per-CPU data here.

Sorry, I'm confused by your use of "domain" here.  Do you mean a 
per_cpu(..., policy->cpu) access racing with a cpu offline?  I'm not 
away of anything preventing that, though I'm not particularly familiar 
with it.

do_pm_op() has:
     if ( op->cpuid >= nr_cpu_ids || !cpu_online(op->cpuid) )
         return -EINVAL;
     pmpt = processor_pminfo[op->cpuid];

and do_get_pm_info() has:
     if ( !op || (op->cpuid >= nr_cpu_ids) || !cpu_online(op->cpuid) )
         return -EINVAL;
     pmpt = processor_pminfo[op->cpuid];

But those are only at entry.

Regards,
Jason

> Since initially I was thinking of using per-CPU data also in my patch, I'm
> reproducing this in raw form below, for your reference. It's generally only
> 4.22 material now, of course. Yet in turn for your driver the new drv_data
> field may want to become a union, with an "acpi" and a "cppc" sub-struct.
> And possibly a "hwp" one: Jason, looks like the HWP driver has a similar
> issue (unless again something guarantees that no two CPUs / threads will
> be in the same domain).
> 
> Jan
> 
> cpufreq: eliminate cpufreq_drv_data[]
> 
> Possibly many slots of it may be unused (all of them when the HWP or CPPC
> drivers are in use), as it's always strictly associated with the CPU
> recorded in a policy (irrespective of that CPU intermediately being taken
> offline). It is shared by all CPUs sharing a policy. We could therefore
> put the respective pointers in struct cpufreq_policy, but even that level
> of indirection is pointless. Embed the driver data structure directly in
> the policy one.
> 
> Signed-off-by: Jan Beulich 
> 
> --- a/xen/arch/x86/acpi/cpufreq/acpi.c
> +++ b/xen/arch/x86/acpi/cpufreq/acpi.c
> @@ -174,17 +174,18 @@ static u32 get_cur_val(const cpumask_t *
>           return 0;
>   
>       policy = per_cpu(cpufreq_cpu_policy, cpu);
> -    if (!policy || !cpufreq_drv_data[policy->cpu])
> +    if ( !policy )
>           return 0;
>   
> -    switch (cpufreq_drv_data[policy->cpu]->arch_cpu_flags) {
> +    switch ( policy->drv_data.arch_cpu_flags )
> +    {
>       case SYSTEM_INTEL_MSR_CAPABLE:
>           cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
>           cmd.addr.msr.reg = MSR_IA32_PERF_STATUS;
>           break;
>       case SYSTEM_IO_CAPABLE:
>           cmd.type = SYSTEM_IO_CAPABLE;
> -        perf = cpufreq_drv_data[policy->cpu]->acpi_data;
> +        perf = policy->drv_data.acpi_data;
>           cmd.addr.io.port = perf->control_register.address;
>           cmd.addr.io.bit_width = perf->control_register.bit_width;
>           break;
> @@ -210,9 +211,8 @@ static unsigned int cf_check get_cur_fre
>       if (!policy)
>           return 0;
>   
> -    data = cpufreq_drv_data[policy->cpu];
> -    if (unlikely(data == NULL ||
> -        data->acpi_data == NULL || data->freq_table == NULL))
> +    data = &policy->drv_data;
> +    if ( !data->acpi_data || !data->freq_table )
>           return 0;
>   
>       return extract_freq(get_cur_val(cpumask_of(cpu)), data);
> @@ -255,7 +255,7 @@ static int cf_check acpi_cpufreq_target(
>       struct cpufreq_policy *policy,
>       unsigned int target_freq, unsigned int relation)
>   {
> -    struct acpi_cpufreq_data *data = cpufreq_drv_data[policy->cpu];
> +    struct acpi_cpufreq_data *data = &policy->drv_data;
>       struct processor_performance *perf;
>       struct cpufreq_freqs freqs;
>       cpumask_t online_policy_cpus;
> @@ -265,10 +265,8 @@ static int cf_check acpi_cpufreq_target(
>       unsigned int j;
>       int result = 0;
>   
> -    if (unlikely(data == NULL ||
> -        data->acpi_data == NULL || data->freq_table == NULL)) {
> +    if ( !data->acpi_data || !data->freq_table )
>           return -ENODEV;
> -    }
>   
>       if (policy->turbo == CPUFREQ_TURBO_DISABLED)
>           if (target_freq > policy->cpuinfo.second_max_freq)
> @@ -334,11 +332,9 @@ static int cf_check acpi_cpufreq_target(
>   
>   static int cf_check acpi_cpufreq_verify(struct cpufreq_policy *policy)
>   {
> -    struct acpi_cpufreq_data *data;
>       struct processor_performance *perf;
>   
> -    if (!policy || !(data = cpufreq_drv_data[policy->cpu]) ||
> -        !processor_pminfo[policy->cpu])
> +    if ( !policy || !processor_pminfo[policy->cpu] )
>           return -EINVAL;
>   
>       perf = &processor_pminfo[policy->cpu]->perf;
> @@ -346,7 +342,7 @@ static int cf_check acpi_cpufreq_verify(
>       cpufreq_verify_within_limits(policy, 0,
>           perf->states[perf->platform_limit].core_frequency * 1000);
>   
> -    return cpufreq_frequency_table_verify(policy, data->freq_table);
> +    return cpufreq_frequency_table_verify(policy, policy->drv_data.freq_table);
>   }
>   
>   static unsigned long
> @@ -382,17 +378,11 @@ static int cf_check acpi_cpufreq_cpu_ini
>       unsigned int i;
>       unsigned int valid_states = 0;
>       unsigned int cpu = policy->cpu;
> -    struct acpi_cpufreq_data *data;
> +    struct acpi_cpufreq_data *data = &policy->drv_data;
>       unsigned int result = 0;
>       struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
>       struct processor_performance *perf;
>   
> -    data = xzalloc(struct acpi_cpufreq_data);
> -    if (!data)
> -        return -ENOMEM;
> -
> -    cpufreq_drv_data[cpu] = data;
> -
>       data->acpi_data = &processor_pminfo[cpu]->perf;
>   
>       perf = data->acpi_data;
> @@ -409,23 +399,18 @@ static int cf_check acpi_cpufreq_cpu_ini
>           if (cpufreq_verbose)
>               printk("xen_pminfo: @acpi_cpufreq_cpu_init,"
>                      "HARDWARE addr space\n");
> -        if (!cpu_has(c, X86_FEATURE_EIST)) {
> -            result = -ENODEV;
> -            goto err_unreg;
> -        }
> +        if ( !cpu_has(c, X86_FEATURE_EIST) )
> +            return -ENODEV;
>           data->arch_cpu_flags = SYSTEM_INTEL_MSR_CAPABLE;
>           break;
>       default:
> -        result = -ENODEV;
> -        goto err_unreg;
> +        return -ENODEV;
>       }
>   
>       data->freq_table = xmalloc_array(struct cpufreq_frequency_table,
>                                       (perf->state_count+1));
> -    if (!data->freq_table) {
> -        result = -ENOMEM;
> -        goto err_unreg;
> -    }
> +    if ( !data->freq_table )
> +        return -ENOMEM;
>   
>       /* detect transition latency */
>       policy->cpuinfo.transition_latency = 0;
> @@ -483,23 +468,14 @@ static int cf_check acpi_cpufreq_cpu_ini
>       return result;
>   
>   err_freqfree:
> -    xfree(data->freq_table);
> -err_unreg:
> -    xfree(data);
> -    cpufreq_drv_data[cpu] = NULL;
> +    XFREE(data->freq_table);
>   
>       return result;
>   }
>   
>   static int cf_check acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy)
>   {
> -    struct acpi_cpufreq_data *data = cpufreq_drv_data[policy->cpu];
> -
> -    if (data) {
> -        cpufreq_drv_data[policy->cpu] = NULL;
> -        xfree(data->freq_table);
> -        xfree(data);
> -    }
> +    XFREE(policy->drv_data.freq_table);
>   
>       return 0;
>   }
> --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c
> +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c
> @@ -35,8 +35,6 @@
>   
>   #include 
>   
> -struct acpi_cpufreq_data *cpufreq_drv_data[NR_CPUS];
> -
>   struct perf_pair {
>       union {
>           struct {
> --- a/xen/arch/x86/acpi/cpufreq/powernow.c
> +++ b/xen/arch/x86/acpi/cpufreq/powernow.c
> @@ -84,16 +84,14 @@ static int cf_check powernow_cpufreq_tar
>       struct cpufreq_policy *policy,
>       unsigned int target_freq, unsigned int relation)
>   {
> -    struct acpi_cpufreq_data *data = cpufreq_drv_data[policy->cpu];
> +    struct acpi_cpufreq_data *data = &policy->drv_data;
>       struct processor_performance *perf;
>       unsigned int next_state; /* Index into freq_table */
>       unsigned int next_perf_state; /* Index into perf table */
>       int result;
>   
> -    if (unlikely(data == NULL ||
> -        data->acpi_data == NULL || data->freq_table == NULL)) {
> +    if ( !data->acpi_data || !data->freq_table )
>           return -ENODEV;
> -    }
>   
>       perf = data->acpi_data;
>       result = cpufreq_frequency_table_target(policy,
> @@ -185,11 +183,9 @@ static void cf_check get_cpu_data(void *
>   
>   static int cf_check powernow_cpufreq_verify(struct cpufreq_policy *policy)
>   {
> -    struct acpi_cpufreq_data *data;
>       struct processor_performance *perf;
>   
> -    if (!policy || !(data = cpufreq_drv_data[policy->cpu]) ||
> -        !processor_pminfo[policy->cpu])
> +    if ( !policy || !processor_pminfo[policy->cpu] )
>           return -EINVAL;
>   
>       perf = &processor_pminfo[policy->cpu]->perf;
> @@ -197,7 +193,7 @@ static int cf_check powernow_cpufreq_ver
>       cpufreq_verify_within_limits(policy, 0,
>           perf->states[perf->platform_limit].core_frequency * 1000);
>   
> -    return cpufreq_frequency_table_verify(policy, data->freq_table);
> +    return cpufreq_frequency_table_verify(policy, policy->drv_data.freq_table);
>   }
>   
>   static int cf_check powernow_cpufreq_cpu_init(struct cpufreq_policy *policy)
> @@ -205,18 +201,12 @@ static int cf_check powernow_cpufreq_cpu
>       unsigned int i;
>       unsigned int valid_states = 0;
>       unsigned int cpu = policy->cpu;
> -    struct acpi_cpufreq_data *data;
> +    struct acpi_cpufreq_data *data = &policy->drv_data;
>       unsigned int result = 0;
>       struct processor_performance *perf;
>       struct amd_cpu_data info;
>       struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
>   
> -    data = xzalloc(struct acpi_cpufreq_data);
> -    if (!data)
> -        return -ENOMEM;
> -
> -    cpufreq_drv_data[cpu] = data;
> -
>       data->acpi_data = &processor_pminfo[cpu]->perf;
>   
>       info.perf = perf = data->acpi_data;
> @@ -228,8 +218,7 @@ static int cf_check powernow_cpufreq_cpu
>           if (cpumask_weight(policy->cpus) != 1) {
>               printk(XENLOG_WARNING "Unsupported sharing type %d (%u CPUs)\n",
>                      policy->shared_type, cpumask_weight(policy->cpus));
> -            result = -ENODEV;
> -            goto err_unreg;
> +            return -ENODEV;
>           }
>       } else {
>           cpumask_copy(policy->cpus, cpumask_of(cpu));
> @@ -238,21 +227,16 @@ static int cf_check powernow_cpufreq_cpu
>       /* capability check */
>       if (perf->state_count <= 1) {
>           printk("No P-States\n");
> -        result = -ENODEV;
> -        goto err_unreg;
> +        return -ENODEV;
>       }
>   
> -    if (perf->control_register.space_id != perf->status_register.space_id) {
> -        result = -ENODEV;
> -        goto err_unreg;
> -    }
> +    if ( perf->control_register.space_id != perf->status_register.space_id )
> +        return -ENODEV;
>   
>       data->freq_table = xmalloc_array(struct cpufreq_frequency_table,
>                                       (perf->state_count+1));
> -    if (!data->freq_table) {
> -        result = -ENOMEM;
> -        goto err_unreg;
> -    }
> +    if ( !data->freq_table )
> +        return -ENOMEM;
>   
>       /* detect transition latency */
>       policy->cpuinfo.transition_latency = 0;
> @@ -298,23 +282,14 @@ static int cf_check powernow_cpufreq_cpu
>       return result;
>   
>   err_freqfree:
> -    xfree(data->freq_table);
> -err_unreg:
> -    xfree(data);
> -    cpufreq_drv_data[cpu] = NULL;
> +    XFREE(data->freq_table);
>   
>       return result;
>   }
>   
>   static int cf_check powernow_cpufreq_cpu_exit(struct cpufreq_policy *policy)
>   {
> -    struct acpi_cpufreq_data *data = cpufreq_drv_data[policy->cpu];
> -
> -    if (data) {
> -        cpufreq_drv_data[policy->cpu] = NULL;
> -        xfree(data->freq_table);
> -        xfree(data);
> -    }
> +    XFREE(policy->drv_data.freq_table);
>   
>       return 0;
>   }
> --- a/xen/include/acpi/cpufreq/cpufreq.h
> +++ b/xen/include/acpi/cpufreq/cpufreq.h
> @@ -37,8 +37,6 @@ struct acpi_cpufreq_data {
>       unsigned int arch_cpu_flags;
>   };
>   
> -extern struct acpi_cpufreq_data *cpufreq_drv_data[NR_CPUS];
> -
>   struct cpufreq_cpuinfo {
>       unsigned int        max_freq;
>       unsigned int        second_max_freq;    /* P1 if Turbo Mode is on */
> @@ -80,6 +78,8 @@ struct cpufreq_policy {
>       int8_t              turbo;  /* tristate flag: 0 for unsupported
>                                    * -1 for disable, 1 for enabled
>                                    * See CPUFREQ_TURBO_* below for defines */
> +
> +    struct acpi_cpufreq_data drv_data;
>   };
>   DECLARE_PER_CPU(struct cpufreq_policy *, cpufreq_cpu_policy);
>   
> 



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From: "Penny, Zheng" 
To: Jan Beulich , "Andryuk, Jason" 
CC: "Huang, Ray" , Andrew Cooper
	, =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Anthony PERARD , "Orzel,
 Michal" , Julien Grall , Stefano
 Stabellini , "xen-devel@lists.xenproject.org"
	
Subject: RE: [PATCH v8 3/8] xen/cpufreq: implement amd-cppc driver for CPPC in
 passive mode
Thread-Topic: [PATCH v8 3/8] xen/cpufreq: implement amd-cppc driver for CPPC
 in passive mode
Thread-Index: AQHcGAMPJXzUCwqDQEuHduiQbQ8QbbR37ByAgAEJOqA=
Date: Fri, 29 Aug 2025 03:30:29 +0000
Message-ID:
 
References: <20250828100306.1776031-1-Penny.Zheng@amd.com>
 <20250828100306.1776031-4-Penny.Zheng@amd.com>
 
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X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5894

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To: Frediano Ziglio 
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	"Daniel P. Smith" ,
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Date: Fri, 29 Aug 2025 06:06:45 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Frediano Ziglio 
Cc: xen-devel@lists.xenproject.org,
	"Daniel P. Smith" ,
	Jan Beulich 
Subject: Re: [PATCH v2] xen/efi: Fix crash with initial empty EFI options

On Tue, Jul 08, 2025 at 02:56:58PM +0100, Frediano Ziglio wrote:
> EFI code path split options from EFI LoadOptions fields in 2
> pieces, first EFI options, second Xen options.
> "get_argv" function is called first to get the number of arguments
> in the LoadOptions, second, after allocating enough space, to
> fill some "argc"/"argv" variable. However the first parsing could
> be different from second as second is able to detect "--" argument
> separator. So it was possible that "argc" was bigger that the "argv"
> array leading to potential buffer overflows, in particular
> a string like "-- a b c" would lead to buffer overflow in "argv"
> resulting in crashes.

I wouldn't call it "buffer overflow" - the argv array is big enough
here. But if there is "--" in cmdline, it has fewer than argc elements
initialized. If there is at least one efi option (IOW, "--" is not the
first one), the sentinel NULL inserted by get_argv() will prevent
reading past the initialized part. But if "--" is the first one, the
NULL is inserted into argv[0], which is skipped by the loop in
efi_start(). Which makes the loop go beyond initialized part of argv
(crash happens even before it goes beyond end of argv allocation).

So, maybe change it to: bigger than the initialized portion of "argv"
array, leading to potential uninitialized pointer dereference, ...?

> Using EFI shell is possible to pass any kind of string in
> LoadOptions.
>=20
> Fixes: bf6501a62e80 ("x86-64: EFI boot code")

Technically, the issue was covered for few months by another issue and
got re-exposed by 926e680aadde ("EFI: suppress bogus loader warning").
While it fixed one issue, it also made it possible to put sentinel NULL
into argv[0] again. But the original EFI code had this issue too, so
IMO the Fixes tag is correct.

While there is convention to put file name as the first option, I don't
see anything in the UEFI spec requiring it. So, Xen should not crash
when it's missing.

> Signed-off-by: Frediano Ziglio 

With commit message adjusted:
Reviewed-by: Marek Marczykowski-G=C3=B3recki 

> ---
> Changes since v1:
> - use argc to make code more clear;
> - fix commit reference;
> - improve commit message.
> ---
>  xen/common/efi/boot.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)
>=20
> diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
> index 9306dc8953..385292ad4e 100644
> --- a/xen/common/efi/boot.c
> +++ b/xen/common/efi/boot.c
> @@ -350,10 +350,11 @@ static unsigned int __init get_argv(unsigned int ar=
gc, CHAR16 **argv,
> =20
>      if ( argc )
>      {
> +        argc =3D 0;
>          cmdline =3D data + *offset;
>          /* EFI_LOAD_OPTION does not supply an image name as first compon=
ent. */
>          if ( *offset )
> -            *argv++ =3D NULL;
> +            argv[argc++] =3D NULL;
>      }
>      else if ( size > sizeof(*cmdline) && !(size % sizeof(*cmdline)) &&
>                (wmemchr(data, 0, size / sizeof(*cmdline)) =3D=3D
> @@ -414,14 +415,14 @@ static unsigned int __init get_argv(unsigned int ar=
gc, CHAR16 **argv,
>                  ++argc;
>              else if ( prev && wstrcmp(prev, L"--") =3D=3D 0 )
>              {
> -                --argv;
> +                --argc;
>                  if ( options )
>                      *options =3D cmdline;
>                  break;
>              }
>              else
>              {
> -                *argv++ =3D prev =3D ptr;
> +                argv[argc++] =3D prev =3D ptr;
>                  *ptr =3D *cmdline;
>                  *++ptr =3D 0;
>              }
> @@ -429,7 +430,7 @@ static unsigned int __init get_argv(unsigned int argc=
, CHAR16 **argv,
>          prev_sep =3D cur_sep;
>      }
>      if ( argv )
> -        *argv =3D NULL;
> +        argv[argc] =3D NULL;
>      return argc;
>  }
> =20
> @@ -1348,8 +1349,8 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE Im=
ageHandle,
>                                    (argc + 1) * sizeof(*argv) +
>                                        loaded_image->LoadOptionsSize,
>                                    (void **)&argv) =3D=3D EFI_SUCCESS )
> -            get_argv(argc, argv, loaded_image->LoadOptions,
> -                     loaded_image->LoadOptionsSize, &offset, &options);
> +            argc =3D get_argv(argc, argv, loaded_image->LoadOptions,
> +                            loaded_image->LoadOptionsSize, &offset, &opt=
ions);
>          else
>              argc =3D 0;
>          for ( i =3D 1; i < argc; ++i )
> --=20
> 2.43.0
>=20

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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MIME-Version: 1.0
Date: Fri, 29 Aug 2025 07:43:30 +0200
From: Nicola Vetrini 
To: Dmytro Prokopchuk1 
Cc: Jan Beulich , Stefano Stabellini
 , Doug Goldstein , Andrew Cooper
 , Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 xen-devel@lists.xenproject.org
Subject: Re: [PATCH] misra: consider conversion from UL or (void*) to function
 pointer as safe
In-Reply-To: <63a8e9f8-61c7-4443-a114-82db08c45f69@epam.com>
References: <9e5e4ff2c7ba0a90a6ac403e2de9318e18949274.1755628705.git.dmytro_prokopchuk1@epam.com>
 <90fb95a3-4b32-4785-a77c-373e5b9da6ed@suse.com>
 
 <6b912698-b871-4819-ac30-14325d0be146@epam.com>
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On 2025-08-28 17:54, Dmytro Prokopchuk1 wrote:
> On 8/25/25 16:08, Nicola Vetrini wrote:
>> On 2025-08-25 14:53, Nicola Vetrini wrote:
>>> On 2025-08-22 18:34, Dmytro Prokopchuk1 wrote:
>>>> On 8/21/25 11:25, Nicola Vetrini wrote:
>>>>> On 2025-08-21 10:01, Jan Beulich wrote:
>>>>>> On 19.08.2025 20:55, Dmytro Prokopchuk1 wrote:
>>>>>>> Rule 11.1 states as following: "Conversions shall not be 
>>>>>>> performed
>>>>>>> between a pointer to a function and any other type."
>>>>>>> 
>>>>>>> The conversion from unsigned long or (void *) to a function 
>>>>>>> pointer
>>>>>>> is safe in Xen because the architectures it supports (e.g., x86 
>>>>>>> and
>>>>>>> ARM) guarantee compatible representations between these types.
>>>>>> 
>>>>>> I think we need to be as precise as possible here. The 
>>>>>> architectures
>>>>>> guarantee nothing, they only offer necessary fundamentals. In the
>>>>>> Windows x86 ABI, for example, you can't convert pointers to/from 
>>>>>> longs
>>>>>> without losing data. What we build upon is what respective ABIs 
>>>>>> say,
>>>>>> possibly in combination of implementation specifics left to 
>>>>>> compilers.
>>>>>> 
>>>>> 
>>>>> +1, a mention of the compilers and targets this deviation relies
>>>>> upon is
>>>>> needed.
>>>> 
>>>> Maybe with this wording:
>>>> 
>>>> This deviation is based on the guarantees provided by the specific 
>>>> ABIs
>>>> (e.g., ARM AAPCS) and compilers (e.g., GCC) supported in Xen. These 
>>>> ABIs
>>> 
>>> s/supported in/supported by/
>>> 
>>>> guarantee compatible representations for 'void *', 'unsigned long' 
>>>> and
>>>> function pointers for the supported target platforms. This behavior 
>>>> is
>>> 
>>> It's not just about the guarantees of the ABIs: it's the behavior of
>>> the compiler for those ABIs that makes this safe or unsafe. If
>>> present, such documentation should be included
>>> 
>> 
>> In any case, provided that the wording can be adjusted:
>> 
>> Reviewed-by: Nicola Vetrini 
> 
> Updated wording:
> 
> This deviation from Rule 11.1 relies on both ABI definitions and 
> compiler
> implementations supported by Xen. The System V x86_64 ABI and the 
> AArch64
> ELF ABI define consistent and compatible representations (i.e., having
> the same size and memory layout) for 'void *', 'unsigned long', and 
> function
> pointers, enabling safe conversions between these types without data 
> loss
> or corruption. Additionally, GCC and Clang, faithfully implement the 
> ABI
> specifications, ensuring that the generated machine code conforms to 
> these
> guarantees. Developers must note that this behavior is not universal 
> and
> depends on platform-specific ABIs and compiler implementations.
> 

LGTM.

> References:
> - System V x86_64 ABI:
> https://gitlab.com/x86-psABIs/x86-64-ABI/-/jobs/artifacts/master/raw/x86-64-ABI/abi.pdf?job=build
> - AArch64 ELF ABI: https://github.com/ARM-software/abi-aa/releases
> - GCC: https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html
> - Clang: https://clang.llvm.org/docs/CrossCompilation.html
> 
> Thanks,
> Dmytro.
>> 
>>>> architecture-specific and may not be portable outside of supported
>>>> environments.
>>>> 
>>>>> 
>>>>>>> --- a/docs/misra/deviations.rst
>>>>>>> +++ b/docs/misra/deviations.rst
>>>>>>> @@ -370,6 +370,16 @@ Deviations related to MISRA C:2012 Rules:
>>>>>>>         to store it.
>>>>>>>       - Tagged as `safe` for ECLAIR.
>>>>>>> 
>>>>>>> +   * - R11.1
>>>>>>> +     - The conversion from unsigned long or (void \*) to a 
>>>>>>> function
>>>>>>> pointer does
>>>>>>> +       not lose any information or violate type safety 
>>>>>>> assumptions
>>>>>>> if unsigned
>>>>>>> +       long or (void \*) type is guaranteed to be the same bit 
>>>>>>> size
>>>>>>> as a
>>>>>>> +       function pointer. This ensures that the function pointer 
>>>>>>> can
>>>>>>> be fully
>>>>>>> +       represented without truncation or corruption. The macro
>>>>>>> BUILD_BUG_ON is
>>>>>>> +       integrated into xen/common/version.c to confirm 
>>>>>>> conversion
>>>>>>> compatibility
>>>>>>> +       across all target platforms.
>>>>>>> +     - Tagged as `safe` for ECLAIR.
>>>>>> 
>>>>>> Why the escaping of * here, when ...
>>>>>> 
>>>>>>> --- a/docs/misra/rules.rst
>>>>>>> +++ b/docs/misra/rules.rst
>>>>>>> @@ -431,7 +431,13 @@ maintainers if you want to suggest a change.
>>>>>>>       - All conversions to integer types are permitted if the
>>>>>>> destination
>>>>>>>         type has enough bits to hold the entire value. 
>>>>>>> Conversions to
>>>>>>> bool
>>>>>>>         and void* are permitted. Conversions from 'void noreturn 
>>>>>>> (*)
>>>>>>> (...)'
>>>>>>> -       to 'void (*)(...)' are permitted.
>>>>>>> +       to 'void (*)(...)' are permitted. Conversions from 
>>>>>>> unsigned
>>>>>>> long or
>>>>>>> +       (void \*) to a function pointer are permitted if the 
>>>>>>> source
>>>>>>> type has
>>>>>>> +       enough bits to restore function pointer without 
>>>>>>> truncation or
>>>>>>> corruption.
>>>>>>> +       Example::
>>>>>>> +
>>>>>>> +           unsigned long func_addr = (unsigned 
>>>>>>> long)&some_function;
>>>>>>> +           void (*restored_func)(void) = (void 
>>>>>>> (*)(void))func_addr;
>>>>>> 
>>>>>> ... context here suggests they work fine un-escaped, and you even 
>>>>>> add
>>>>>> some un-
>>>>>> escaped instances as well. Perhaps I'm simply unaware of some
>>>>>> peculiarity?
>>>>>> 
>>>>> 
>>>>> This is a literal rst block, while the other is not (* acts as a 
>>>>> bullet
>>>>> point in rst iirc)
>>>> 
>>>> This is how "sphinx-build" tool interprets this.
>>>> 1. * inside single quotes '' -> looks normal, e.g. ‘void (*)(…)’
>>>> 2. * without quotes -> warning
>>>> deviations.rst:369: WARNING: Inline emphasis start-string without
>>>> end-string. [docutils]
>>>> 3. \* -> looks normal, e.g. (void *)
>>>> 
>>>> Because that we need such format: \*
>>>> 
>>>> Dmytro.
>>>> 
>>>>> 
>>>>>> Jan
>>>>> 
>> 

-- 
Nicola Vetrini, B.Sc.
Software Engineer
BUGSENG (https://bugseng.com)
LinkedIn: https://www.linkedin.com/in/nicola-vetrini-a42471253


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Subject: Re: [PATCH v8 3/8] xen/cpufreq: implement amd-cppc driver for CPPC in
 passive mode
To: "Penny, Zheng" 
Cc: "Huang, Ray" ,
 Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 "Orzel, Michal" , Julien Grall ,
 Stefano Stabellini ,
 "xen-devel@lists.xenproject.org" ,
 "Andryuk, Jason" 
References: <20250828100306.1776031-1-Penny.Zheng@amd.com>
 <20250828100306.1776031-4-Penny.Zheng@amd.com>
 
 
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From: Jan Beulich 
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On 29.08.2025 05:30, Penny, Zheng wrote:
>> -----Original Message-----
>> From: Jan Beulich 
>> Sent: Thursday, August 28, 2025 7:23 PM
>>
>> On 28.08.2025 12:03, Penny Zheng wrote:
>>> +static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy,
>>> +                                            unsigned int target_freq,
>>> +                                            unsigned int relation) {
>>> +    unsigned int cpu = policy->cpu;
>>> +    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data,
>>> +cpu);
>>
>> I fear there's a problem here that I so far overlooked. As it happens, just
>> yesterday I made a patch to eliminate cpufreq_drv_data[] global. In the course of
>> doing so it became clear that in principle the CPU denoted by
>> policy->cpu can be offline. Hence its per-CPU data is also unavailable.
>> policy->See
>> cpufreq_add_cpu()'s invocation of .init() and cpufreq_del_cpu()'s invocation
>> of .exit(). Is there anything well-hidden (and likely lacking some suitable
>> comment) which guarantees that no two CPUs (threads) will be in the same
>> domain? If not, I fear you simply can't use per-CPU data here.
>>
> 
> Correct me if I understand you wrongly:
> No, my env is always per pcpu per cpufreq domain. So it never occurred to me that cpus, other than the first one in domain, will never call .init(), and of course, no per_cpu(amd_cppc_drv_data) ever gets allocated then.

Well, the question is how domains are organized when using the CPPC driver.
Aiui that's still driven by data passed in by Dom0, so in turn the question
is whether there are any constraints on what ACPI may surface. If there are,
all that may be necessary is adding a check. If there aren't, ...

>> Since initially I was thinking of using per-CPU data also in my patch, I'm
>> reproducing this in raw form below, for your reference. It's generally only
>> 4.22 material now, of course. Yet in turn for your driver the new drv_data field
>> may want to become a union, with an "acpi" and a "cppc" sub-struct.
> 
> How about I embed my new driver data " struct amd_cppc_drv_data * " into cpufreq policy, maybe pointer is enough?
> Later, maybe, all "cppc", "acpi" and "hwp" could constitute an union in policy.

... I'd prefer to go the union approach right away. Whether then to take my
patch as a prereq is tbd; that largely depends on what (if anything) is
needed on the HWP side. If HWP needs fixing, that wants to to come first, as
it would want backporting.

Jan


From xen-devel-bounces@lists.xenproject.org Fri Aug 29 06:18:28 2025
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To: Stefano Stabellini 
CC: "xen-devel@lists.xenproject.org" , Andrew
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	, Bertrand Marquis , Jan
 Beulich , Juergen Gross , Julien Grall
	, Michal Orzel ,
	=?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?= , Volodymyr
 Babchuk , Grygorii Strashko
	
Subject: Re: [PATCH v6 1/4] xen/arm: add generic SCI subsystem
Thread-Topic: [PATCH v6 1/4] xen/arm: add generic SCI subsystem
Thread-Index: AQHcGDp0HddMWoIUiESW9wlppK7VcrR4ldUAgACTHQA=
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In-Reply-To: <24474024-0542-48e5-a1b8-bb534c7eeb4b@amd.com>
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On 29.08.2025 02:16, Jason Andryuk wrote:
> On 2025-08-28 07:22, Jan Beulich wrote:
>> On 28.08.2025 12:03, Penny Zheng wrote:
>>> +static int cf_check amd_cppc_cpufreq_target(struct cpufreq_policy *policy,
>>> +                                            unsigned int target_freq,
>>> +                                            unsigned int relation)
>>> +{
>>> +    unsigned int cpu = policy->cpu;
>>> +    const struct amd_cppc_drv_data *data = per_cpu(amd_cppc_drv_data, cpu);
>>
>> I fear there's a problem here that I so far overlooked. As it happens, just
>> yesterday I made a patch to eliminate cpufreq_drv_data[] global. In the
>> course of doing so it became clear that in principle the CPU denoted by
>> policy->cpu can be offline. Hence its per-CPU data is also unavailable. See
>> cpufreq_add_cpu()'s invocation of .init() and cpufreq_del_cpu()'s invocation
>> of .exit(). Is there anything well-hidden (and likely lacking some suitable
>> comment) which guarantees that no two CPUs (threads) will be in the same
>> domain? If not, I fear you simply can't use per-CPU data here.
> 
> Sorry, I'm confused by your use of "domain" here.

I agree it's confusing, but that's the terminology used in cpufreq.c (see
e.g. "struct cpufreq_dom" or "const struct xen_psd_package *domain_info").

>  Do you mean a 
> per_cpu(..., policy->cpu) access racing with a cpu offline?

Yes (I wouldn't call it "racing" though, as it's not a timing issue).

>  I'm not 
> away of anything preventing that, though I'm not particularly familiar 
> with it.



> do_pm_op() has:
>      if ( op->cpuid >= nr_cpu_ids || !cpu_online(op->cpuid) )
>          return -EINVAL;
>      pmpt = processor_pminfo[op->cpuid];
> 
> and do_get_pm_info() has:
>      if ( !op || (op->cpuid >= nr_cpu_ids) || !cpu_online(op->cpuid) )
>          return -EINVAL;
>      pmpt = processor_pminfo[op->cpuid];
> 
> But those are only at entry.

That's not accessing struct cpufreq_policy, though. Per-CPU accesses
using policy->cpu are the problematic ones, as - from all I can tell -
the CPU named there can have gone offline, with the policy surviving
when some other CPU is also part of the same "domain".

As said in the reply to Penny, main question is whether the data
controlling what a "domain" covers may be constrained in the HWP case,
demanding that no two CPUs (threads) can be in the same "domain". Then
adding merely a sanity check somewhere would suffice.

Jan


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Date: Fri, 29 Aug 2025 09:29:38 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v5] xen/char: implement suspend/resume calls for SCIF
 driver
To: Mykola Kvach 
Cc: xen-devel@lists.xenproject.org,
 Volodymyr Babchuk ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel ,
 Oleksandr Andrushchenko ,
 Mykola Kvach 
References: 
 <60c0b456-bfda-430d-a1e9-f64c9a49ac54@gmail.com>
 
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From: Oleksandr Tyshchenko 
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On 29.08.25 00:36, Mykola Kvach wrote:
> Hi Oleksandr,


Hello Mykola

> 
> Thank you for your review.
> 
> On Tue, Aug 26, 2025 at 6:51 PM Oleksandr Tyshchenko
>  wrote:
>>
>>
>>
>> On 07.08.25 08:16, Mykola Kvach wrote:
>>
>>
>> Hello Mykola,
>>
>> In general patch looks good to me, just one question below ...
>>
>>> From: Volodymyr Babchuk 
>>>
>>> Implement suspend and resume callbacks for the SCIF UART driver,
>>> enabled when CONFIG_SYSTEM_SUSPEND is set. This allows proper
>>> handling of UART state across system suspend/resume cycles.
>>>
>>> Tested on Renesas R-Car H3 Starter Kit.
>>>
>>> Signed-off-by: Volodymyr Babchuk 
>>> Signed-off-by: Oleksandr Andrushchenko 
>>> Signed-off-by: Mykola Kvach 
>>> ---
>>> In patch v5, there are no changes at all;
>>> it was done just to trigger a review.
>>
>> I think, you could ping on V4.
>>
>>
>>>
>>> In patch v4, enhance commit message, no functional changes
>>>
>>> In patch v2, I just added a CONFIG_SYSTEM_SUSPEND check around
>>> the suspend/resume functions in the SCIF driver.
>>> ---
>>>    xen/drivers/char/scif-uart.c | 40 ++++++++++++++++++++++++++++++++++--
>>>    1 file changed, 38 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c
>>> index 757793ca45..888821a3b8 100644
>>> --- a/xen/drivers/char/scif-uart.c
>>> +++ b/xen/drivers/char/scif-uart.c
>>> @@ -139,9 +139,8 @@ static void scif_uart_interrupt(int irq, void *data)
>>>        }
>>>    }
>>>
>>> -static void __init scif_uart_init_preirq(struct serial_port *port)
>>> +static void scif_uart_disable(struct scif_uart *uart)
>>>    {
>>> -    struct scif_uart *uart = port->uart;
>>>        const struct port_params *params = uart->params;
>>>
>>>        /*
>>> @@ -155,6 +154,14 @@ static void __init scif_uart_init_preirq(struct serial_port *port)
>>>
>>>        /* Reset TX/RX FIFOs */
>>>        scif_writew(uart, SCIF_SCFCR, SCFCR_RFRST | SCFCR_TFRST);
>>> +}
>>> +
>>> +static void scif_uart_init_preirq(struct serial_port *port)
>>> +{
>>> +    struct scif_uart *uart = port->uart;
>>> +    const struct port_params *params = uart->params;
>>> +
>>> +    scif_uart_disable(uart);
>>>
>>>        /* Clear all errors and flags */
>>>        scif_readw(uart, params->status_reg);
>>> @@ -271,6 +278,31 @@ static void scif_uart_stop_tx(struct serial_port *port)
>>>        scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) & ~SCSCR_TIE);
>>>    }
>>>
>>> +#ifdef CONFIG_SYSTEM_SUSPEND
>>> +
>>> +static void scif_uart_suspend(struct serial_port *port)
>>> +{
>>> +    struct scif_uart *uart = port->uart;
>>> +
>>> +    scif_uart_stop_tx(port);
>>
>>    ... I wonder, whether the call above (that disables Transmit
>> interrupt) is really needed as the call below disables all interrupts
>> anyway?
> 
> I have checked the relevant documentation and did not find any requirement
> to clear TIE before disabling the rest of the SCSCR bits, according to the
> R-Car Series, 3rd Generation User’s Manual: Hardware, Rev. 0.52.
> 
> However, based on how the serial subsystem works, I believe this call is
> justified.
> 
> Disabling TX IRQs before fully stopping the serial prevents new data
> from being added to the FIFO by the IRQ handler during suspend (see
> serial_tx_interrupt). This ensures the FIFO is flushed (loop inside
> scif_uart_disable) and no further transmissions occur.
> 
> If a flush handler were implemented for this driver, we could avoid
> calling scif_uart_stop_tx and remove the loop inside scif_uart_disable,
> as the flush handler would ensure the FIFO is empty after any invocation
> of serial_tx_interrupt.


thanks for the investigation, the explanation is ok to me.

Reviewed-by: Oleksandr Tyshchenko 

> 
>>
>>
>>> +    scif_uart_disable(uart);
>>> +}
>>
>> [snip]
> 
> Best regards,
> Mykola



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Subject: Re: [PATCH] x86: introduce "hot" and "cold" page copying functions
To: Jason Andryuk 
Cc: Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
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On 28.08.2025 23:33, Jason Andryuk wrote:
> On 2025-08-28 05:17, Jan Beulich wrote:
>> The present copy_page_sse2() is useful in case the destination page isn't
>> going to get touched again soon, or if we want to limit churn on the
>> caches. Just rename it, to fit the corresponding {clear,scrub}_page_*()
>> naming scheme.
>>
>> For cases where latency is the most important aspect, or when it is
>> expected that sufficiently large parts of a destination page will get
>> accessed again soon after the copying, introduce a "hot" alternative.
>> Again use alternatives patching to select between a "legacy" and an ERMS
>> variant.
>>
>> Don't switch any callers just yet - this will be the subject of subsequent
>> changes.
>>
>> Signed-off-by: Jan Beulich 
> 
> Reviewed-by: Jason Andryuk 

Thanks.

>> To avoid the NOP padding (also in clear_page_hot()) we could use a double
>> REP prefix in the replacement code (accounting for the REX one in the code
>> being replaced).
> 
> Did my tool chain do it automatically?
> 
> 0000000000000000 <.altinstr_replacement>:
>     0:	b9 00 10 00 00       	mov    $0x1000,%ecx
>     5:	f3 f3 a4             	repz rep movsb %ds:(%rsi),%es:(%rdi)

Interesting. That looks like a bug to me, when source code merely has

        rep movsb

Did you also check what copy_page_movsq (i.e. "rep movsq") expands to?
What gas version is this? With 2.45 I get

0000000000000000 <.altinstr_replacement>:
   0:	b9 00 10 00 00       	mov    $0x1000,%ecx
   5:	f3 a4                	rep movsb (%rsi),(%rdi)

(the omission of segment indicators when there's no segment override is
indeed a change in 2.45).

Jan


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Subject: Re: [PATCH v2 3/5] symbols: arrange to know where functions end
To: Jason Andryuk 
Cc: Andrew Cooper , Julien Grall ,
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On 28.08.2025 19:16, Jason Andryuk wrote:
> On 2025-08-28 12:11, Jan Beulich wrote:
>> On 28.08.2025 09:28, Jan Beulich wrote:
>>> On 28.08.2025 03:03, Jason Andryuk wrote:
>>>> On 2025-04-02 09:58, Jan Beulich wrote:
>>>>> --- a/xen/tools/symbols.c
>>>>> +++ b/xen/tools/symbols.c
>>>>
>>>>> @@ -318,24 +334,42 @@ static void write_src(void)
>>>>>    	printf("#else\n");
>>>>>    	output_label("symbols_offsets");
>>>>>    	printf("#endif\n");
>>>>> -	for (i = 0; i < table_cnt; i++) {
>>>>> +	for (i = 0, ends = 0; i < table_cnt; i++) {
>>>>>    		printf("\tPTR\t%#llx - SYMBOLS_ORIGIN\n", table[i].addr);
>>>>> +
>>>>> +		table[i].addr_idx = i + ends;
>>>>> +
>>>>> +		if (!want_symbol_end(i)) {
>>>>> +			/* If there's another symbol at the same address,
>>>>> +			 * propagate this symbol's size if the next one has
>>>>> +			 * no size, or if the next one's size is larger. */
>>>>
>>>> Why do we want to shrink the next symbol's size?
>>>
>>> First (see related post-commit-message remarks): In principle section symbols
>>> could come with a size, too. That would break everything as long as we don't
>>> strip those.
>>>
>>> The main reason though is that imo smallest granularity is what we want here,
>>> together with predictability. One symbol with a huge size could cover
>>> multiple other symbols with smaller sizes. We could omit that part of the
>>> change here, but then the processing in the hypervisor would need to change,
>>> to fish out the "best suitable" symbol when dealing with multiple ones at the
>>> same address. Other changes may then also be needed to the tool, to have such
>>> symbols come in a well-defined order (to keep the then-new code in the
>>> hypervisor as simple as possible). Look for "aliased symbol" in
>>> common/symbols.c to see how simplistic respective code is right now.
>>
>> Furthermore remember that we can't record sizes, but instead we insert fake
>> symbols. Obviously there can be only one (at least in the present scheme).
>> If we used too large a size, chances would increase that the end symbol (in
>> the sorted table) would have to live past some other symbol, thus becoming
>> that one's "end".
> 
> The scenario I thought about is something like:
> 
> a 0x100-0x10f
> b 0x100-0x1ff
> c 0x200-0x2ff
> 
> If you shrink b, you are creating a hole that would otherwise be 
> assigned to b.
> 
> But I agree avoiding huge sizes covering multiple small variables would 
> better be avoided.
> 
> Do you have concrete examples to help illustrate the problem?

a 0x100-0x1ff
b 0x100-0x10f
c 0x110-0x11f

If we inserted an "end" label based on a's size, that would effectively be
c's 2nd end symbol (and there may not be two "end" symbols in a row, unless
we want to further complicate the symbol lookup logic).

Jan


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Subject: Re: [PATCH v3 5/5] xen/arm: map static memory on demand
To: Hari Limaye , 
CC: , Penny Zheng , "Stefano
 Stabellini" , Julien Grall ,
	"Bertrand Marquis" , Volodymyr Babchuk
	, Andrew Cooper ,
	Anthony PERARD , Jan Beulich ,
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Wei Chen
	
References: 
 <30cbc79f765c21759d74377e55cc471210fc2575.1756379422.git.hari.limaye@arm.com>
From: "Orzel, Michal" 
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On 28/08/2025 13:12, Hari Limaye wrote:
> From: Penny Zheng 
> 
> In the function `init_staticmem_pages` we need to have mapped static
> memory banks for initialization. Unlike on an MMU system, we cannot map
> the entire RAM on an MPU system as we have a limited number of MPU
> memory regions. To solve this, transiently map the static memory banks
> for initialization.
> 
> Signed-off-by: Penny Zheng 
> Signed-off-by: Wei Chen 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
> Reviewed-by: Michal Orzel 
Given that the freeze date will likely be extended, I'd prefer to take this tag
back and request this patch to be changed due to reasons listed below.

> ---
> Changes from v2:
> - Add Michal's R-b
> ---
>  xen/arch/arm/include/asm/mmu/mm.h |  3 +++
>  xen/arch/arm/include/asm/mpu/mm.h |  4 ++++
>  xen/arch/arm/mpu/setup.c          | 11 +++++++++++
>  xen/include/xen/static-memory.h   |  8 ++++++++
>  4 files changed, 26 insertions(+)
> 
> diff --git a/xen/arch/arm/include/asm/mmu/mm.h b/xen/arch/arm/include/asm/mmu/mm.h
> index 7f4d59137d..645a0ea3cb 100644
> --- a/xen/arch/arm/include/asm/mmu/mm.h
> +++ b/xen/arch/arm/include/asm/mmu/mm.h
> @@ -110,6 +110,9 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr,
>  extern void switch_ttbr(uint64_t ttbr);
>  extern void relocate_and_switch_ttbr(uint64_t ttbr);
>  
> +static inline void map_staticmem_pages_to_xen(paddr_t start, paddr_t end) {}
> +static inline void unmap_staticmem_pages_to_xen(paddr_t start, paddr_t end) {}
> +
>  #endif /* __ARM_MMU_MM_H__ */
>  
>  /*
> diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
> index efb0680e39..4cc769418e 100644
> --- a/xen/arch/arm/include/asm/mpu/mm.h
> +++ b/xen/arch/arm/include/asm/mpu/mm.h
> @@ -123,6 +123,10 @@ void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags);
>   */
>  void unmap_mm_range(paddr_t base);
>  
> +/* {un}map_staticmem_pages_to_xen used while initializing static memory banks */
> +void map_staticmem_pages_to_xen(paddr_t start, paddr_t end);
> +void unmap_staticmem_pages_to_xen(paddr_t start, paddr_t end);
> +
>  /*
>   * Checks whether a given memory range is present in the provided table of
>   * MPU protection regions.
> diff --git a/xen/arch/arm/mpu/setup.c b/xen/arch/arm/mpu/setup.c
> index 163573b932..dbc3107333 100644
> --- a/xen/arch/arm/mpu/setup.c
> +++ b/xen/arch/arm/mpu/setup.c
> @@ -83,6 +83,17 @@ void * __init early_fdt_map(paddr_t fdt_paddr)
>      return fdt_virt;
>  }
>  
> +void __init map_staticmem_pages_to_xen(paddr_t start, paddr_t end)
> +{
> +    if ( !map_mm_range(start, end, PAGE_HYPERVISOR) )
> +        panic("Unable to map staticmem pages to Xen!");
> +}
> +
> +void __init unmap_staticmem_pages_to_xen(paddr_t start, paddr_t end)
> +{
> +    unmap_mm_range(start);
> +}
> +
>  /*
>   * copy_from_paddr - copy data from a physical address
>   * @dst: destination virtual address
> diff --git a/xen/include/xen/static-memory.h b/xen/include/xen/static-memory.h
> index e445aa8057..d99abac113 100644
> --- a/xen/include/xen/static-memory.h
> +++ b/xen/include/xen/static-memory.h
> @@ -18,7 +18,15 @@ static inline void init_staticmem_bank(const struct membank *bank)
>      if ( mfn_x(bank_end) <= mfn_x(bank_start) )
>          return;
>  
> +    /* Map temporarily before initialization */
> +    map_staticmem_pages_to_xen(mfn_to_maddr(bank_start),
> +                               mfn_to_maddr(bank_end));
Static memory is not Arm only feature, it is common and as such should not (and
does not) make calls to Arm only functions. If at all, such helpers should be
made generic so other arches that could enable static memory can re-define them
if needed (as you pointed out, on MMU you don't need to map/unmap this region
temporarily).

~Michal



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From: Lukas Bulwahn 
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To: Juergen Gross ,
	Boris Ostrovsky ,
	Thomas Gleixner ,
	Ingo Molnar ,
	Borislav Petkov ,
	Dave Hansen ,
	x86@kernel.org,
	"H . Peter Anvin" ,
	xen-devel@lists.xenproject.org
Cc: kernel-janitors@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Lukas Bulwahn 
Subject: [PATCH] x86/xen: select HIBERNATE_CALLBACKS more directly
Date: Fri, 29 Aug 2025 09:04:02 +0200
Message-ID: <20250829070402.159390-1-lukas.bulwahn@redhat.com>
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From: Lukas Bulwahn 

The config XEN_SAVE_RESTORE's only purpose is to select
HIBERNATE_CALLBACKS, when config XEN is set. The XEN config definition can
simply select HIBERNATE_CALLBACKS, though, and the definition of
XEN_SAVE_RESTORE can be dropped.

So, remove this indirection through XEN_SAVE_RESTORE and select
HIBERNATE_CALLBACKS directly. Also, drop the XEN_SAVE_RESTORE from the x86
xen config fragment.

No functional change intended with this clean-up.

Signed-off-by: Lukas Bulwahn 
---
 arch/x86/configs/xen.config | 1 -
 arch/x86/xen/Kconfig        | 7 +------
 2 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/x86/configs/xen.config b/arch/x86/configs/xen.config
index d5d091e03bd3..98b6952ba9d2 100644
--- a/arch/x86/configs/xen.config
+++ b/arch/x86/configs/xen.config
@@ -12,7 +12,6 @@ CONFIG_CPU_FREQ=y
 
 # x86 xen specific config options
 CONFIG_XEN_PVH=y
-CONFIG_XEN_SAVE_RESTORE=y
 # CONFIG_XEN_DEBUG_FS is not set
 CONFIG_XEN_MCE_LOG=y
 CONFIG_XEN_ACPI_PROCESSOR=m
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 98d8a50d2aed..aa4040fd9215 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -8,6 +8,7 @@ config XEN
 	depends on PARAVIRT
 	select PARAVIRT_CLOCK
 	select X86_HV_CALLBACK_VECTOR
+	select HIBERNATE_CALLBACKS
 	depends on X86_64 || (X86_32 && X86_PAE)
 	depends on X86_64 || (X86_GENERIC || MPENTIUM4 || MATOM)
 	depends on X86_LOCAL_APIC && X86_TSC
@@ -64,12 +65,6 @@ config XEN_PVHVM_GUEST
 	help
 	  Support running as a Xen PVHVM guest.
 
-config XEN_SAVE_RESTORE
-	bool
-	depends on XEN
-	select HIBERNATE_CALLBACKS
-	default y
-
 config XEN_DEBUG_FS
 	bool "Enable Xen debug and tuning parameters in debugfs"
 	depends on XEN && DEBUG_FS
-- 
2.50.1



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Subject: Re: [PATCH v2] xen/efi: Fix crash with initial empty EFI options
To: =?UTF-8?Q?Marek_Marczykowski-G=C3=B3recki?=
 ,
 Frediano Ziglio 
Cc: xen-devel@lists.xenproject.org,
 "Daniel P. Smith" 
References: <20250708135701.119601-1-frediano.ziglio@cloud.com>
 
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On 29.08.2025 06:06, Marek Marczykowski-Górecki wrote:
> On Tue, Jul 08, 2025 at 02:56:58PM +0100, Frediano Ziglio wrote:
>> EFI code path split options from EFI LoadOptions fields in 2
>> pieces, first EFI options, second Xen options.
>> "get_argv" function is called first to get the number of arguments
>> in the LoadOptions, second, after allocating enough space, to
>> fill some "argc"/"argv" variable. However the first parsing could
>> be different from second as second is able to detect "--" argument
>> separator. So it was possible that "argc" was bigger that the "argv"
>> array leading to potential buffer overflows, in particular
>> a string like "-- a b c" would lead to buffer overflow in "argv"
>> resulting in crashes.
> 
> I wouldn't call it "buffer overflow" - the argv array is big enough
> here. But if there is "--" in cmdline, it has fewer than argc elements
> initialized. If there is at least one efi option (IOW, "--" is not the
> first one), the sentinel NULL inserted by get_argv() will prevent
> reading past the initialized part. But if "--" is the first one, the
> NULL is inserted into argv[0], which is skipped by the loop in
> efi_start(). Which makes the loop go beyond initialized part of argv
> (crash happens even before it goes beyond end of argv allocation).
> 
> So, maybe change it to: bigger than the initialized portion of "argv"
> array, leading to potential uninitialized pointer dereference, ...?
> 
>> Using EFI shell is possible to pass any kind of string in
>> LoadOptions.
>>
>> Fixes: bf6501a62e80 ("x86-64: EFI boot code")
> 
> Technically, the issue was covered for few months by another issue and
> got re-exposed by 926e680aadde ("EFI: suppress bogus loader warning").
> While it fixed one issue, it also made it possible to put sentinel NULL
> into argv[0] again. But the original EFI code had this issue too, so
> IMO the Fixes tag is correct.
> 
> While there is convention to put file name as the first option, I don't
> see anything in the UEFI spec requiring it. So, Xen should not crash
> when it's missing.

Yet if the equivalent of argv[0] is missing from the command line, how
do we even know whether the first token on the command line is an
option (or the -- separator)?

Jan


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Subject: Re: [PATCH v3 5/5] xen/arm: map static memory on demand
Content-Language: en-GB
To: Hari Limaye , xen-devel@lists.xenproject.org
Cc: luca.fancellu@arm.com, Penny Zheng ,
 Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Andrew Cooper ,
 Anthony PERARD , Jan Beulich ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Wei Chen 
References: 
 <30cbc79f765c21759d74377e55cc471210fc2575.1756379422.git.hari.limaye@arm.com>
From: Julien Grall 
In-Reply-To: <30cbc79f765c21759d74377e55cc471210fc2575.1756379422.git.hari.limaye@arm.com>
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Hi Hari,

On 28/08/2025 12:12, Hari Limaye wrote:
> From: Penny Zheng 
> 
> In the function `init_staticmem_pages` we need to have mapped static
> memory banks for initialization. Unlike on an MMU system, we cannot map
> the entire RAM

Even on the MMU system we don't always map the full RAM (for instance on 
arm32). This is why we have infrastructure like map_domain_page() 
(Temporary mapping) and map_domain_page_global() (more permanent).

on an MPU system as we have a limited number of MPU
> memory regions. To solve this, transiently map the static memory banks
> for initialization.

I am guessing you implemented the helper because in 
unmap_staticmem_pages_to_xen(), we are calling scrub_one_page(). This 
will be using map_domain_page() and unmap_domain_page(). I am a bit 
confused why we end up with brand new helpers rather than implementation 
map_domain_page() and unmap_domain_page()?

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH v6 3/4] xen/arm: scmi-smc: passthrough SCMI SMC to domain,
 single agent
To: Oleksii Moisieiev 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Bertrand Marquis , Juergen Gross
 , Julien Grall ,
 Michal Orzel , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Stefano Stabellini ,
 Volodymyr Babchuk ,
 Grygorii Strashko ,
 "xen-devel@lists.xenproject.org" 
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On 28.08.2025 18:40, Oleksii Moisieiev wrote:
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -1097,6 +1097,15 @@ affinities to prefer but be not limited to the specified node(s).
>  
>  Pin dom0 vcpus to their respective pcpus
>  
> +### scmi-smc-passthrough (ARM)
> +> `= `
> +
> +The option is available when `CONFIG_SCMI_SMC` is compiled in, and allows to
> +enable SCMI SMC single agent interface for any, but only one guest domain,
> +which serves as Driver domain. The SCMI will be disabled for Dom0/hwdom and
> +SCMI nodes removed from Dom0/hwdom device tree.
> +(for example, thin Dom0 with Driver domain use-case).
> +
>  ### dtuart (ARM)
>  > `= path [:options]`

On what basis did you pick where to put the new option? It clearly doesn't
fit between dom0_vcpus_pin and dtuart, but wants to go far further down.

Jan


From xen-devel-bounces@lists.xenproject.org Fri Aug 29 07:27:13 2025
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Subject: Re: [PATCH v3 2/5] arm/mpu: Implement setup_mm for MPU systems
Content-Language: en-GB
To: Hari Limaye , xen-devel@lists.xenproject.org
Cc: luca.fancellu@arm.com, Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <2d41ab5c2bd45f788e96a93659595d66c258c8df.1756379422.git.hari.limaye@arm.com>
From: Julien Grall 
In-Reply-To: <2d41ab5c2bd45f788e96a93659595d66c258c8df.1756379422.git.hari.limaye@arm.com>
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Hi,

On 28/08/2025 12:12, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Implement `setup_mm` for MPU systems. This variant doesn't need to set
> up the direct map.

If this is the only difference, then why do we duplicate the rest of the 
code? Why can't we instead setup the directmap helper or make it optional?

In fact, in the future we will want to initially have the directmap 
optional on Arm with MMU, but ultimately will be removed.

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH] xen/x86: move domctl.o out of PV_SHIM_EXCLUSIVE
To: Stefano Stabellini 
Cc: Oleksii Kurochko , ray.huang@amd.com,
 Andrew Cooper ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 xen-devel@lists.xenproject.org, Penny Zheng 
References: <20250815102728.1340505-1-Penny.Zheng@amd.com>
 
 
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From: Jan Beulich 
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On 29.08.2025 01:41, Stefano Stabellini wrote:
> On Thu, 28 Aug 2025, Jan Beulich wrote:
>> On 28.08.2025 02:52, Stefano Stabellini wrote:
>>> On Wed, 27 Aug 2025, Jan Beulich wrote:
>>>> On 27.08.2025 02:33, Stefano Stabellini wrote:
>>>>> --- a/xen/include/xen/domain.h
>>>>> +++ b/xen/include/xen/domain.h
>>>>> @@ -148,8 +148,17 @@ void arch_dump_domain_info(struct domain *d);
>>>>>  
>>>>>  int arch_vcpu_reset(struct vcpu *v);
>>>>>  
>>>>> +#ifdef CONFIG_SYSCTL
>>>>>  bool domctl_lock_acquire(void);
>>>>>  void domctl_lock_release(void);
>>>>> +#else
>>>>> +static inline bool domctl_lock_acquire(void)
>>>>> +{
>>>>> +    return false;
>>>>
>>>> ... this will break x86'es HVM_PARAM_IDENT_PT handling. That is, in
>>>> principle I would agree that returning false here is appropriate. But
>>>> for the specific case there it's wrong.
>>>
>>> Uhm, that is a good point actually. And while in principle "false"
>>> sounds appropriate, in practice there is no domctl.c to worry about
>>> concurrency so "true" is what we want.
>>
>> Except that, as said, conceptually "true" is the wrong value to use in
>> such a stub.
>>
>>>> As said on the call yesterday, until what you call MGMT_HYPERCALLS is
>>>> completely done, the option needs to be prompt-less, always-on.
>>>
>>> I do not think this is a good idea, because we would be unable to test
>>> the configuration. Although we have been accepting code without tests,
>>> that is not a good principle. At least with the current approach we can
>>> run manual tests if automated tests are not available. If we make it
>>> silent, we risk introducing broken code, or code soon-to-become broken.
>>>
>>> In my view, we need to make gradual progress toward the goal. In this
>>> case, we should move incrementally toward compiling out all the
>>> "management" hypercalls. Also the alternative of waiting until all
>>> patches are ready before committing them is not feasible. An incremental
>>> approach reduces risk, preserves testability, and makes regressions
>>> easier to identify.
>>
>> If that's your view, then why did you not comment on the SYSCTL series,
>> when I asked the prompt to appear last?
> 
> I am not trying to be obtuse, but I am not sure what you mean by this.
> In any case, I do not recall reading a specific email on this topic. I
> try my best to follow other review comments, but I may have overlooked
> this one.

Originally Penny introduced the option with prompt, very early in the
series. It became clear very quickly that this way she introduced
randconfig issues, for the case where randconfig could have chosen to
turn the option off. Hence why I asked that the option be introduced
prompt-less, then all #ifdef-ary be added, and then the option would
gain a prompt.

>>> An extreme example is that I could write:
>>>
>>> static inline bool domctl_lock_acquire(void)
>>> {
>>>     obviously broken
>>> }
>>>
>>> and no tests would catch it.
>>
>> Tests would catch it at the point the prompt is added. Much like it was
>> with the SYSCTL series (and why, with the prompt removed, the rest of
>> the series can stay in).
> 
> In my opinion, this is a no-go. The code must function correctly, and
> that is my top priority, certainly above conceptual issues, such as the
> return value of domctl_lock_acquire. With your suggestion, there is no
> guarantee the code works and there is no way to test it.

The code working correctly will be tested at the point the option gains
the prompt.

>>>> Adding
>>>> a prompt was necessary to be the last thing on the SYSCTL series, and
>>>> it'll need to be last on the follow-on one masking out further
>>>> hypercalls. IOW my take is that 34317c508294 and 568f806cba4c will
>>>> need reverting (the latter being what caused the regression, and the
>>>> former depending on the latter), to allow to cleanly continue that
>>>> work after the rename. If we don't do the reverts now (and take either
>>>> Penny's patch or what you propose), imo we'll need to do them later.
>>>> Else we're risking to introduce new randconfig breakages while the
>>>> further conversion work is ongoing.
>>>
>>> My suggestion remains to go forward with 2 patches:
>>> 0) keep both 568f806cba4c and 34317c508294
>>> 1) rename CONFIG_SYSCTL to CONFIG_MGMT_HYPERCALLS
>>> 2) this patch with return true from domctl_lock_acquire
>>>
>>> I am open to reverting 568f806cba4c but I don't think it would improve
>>> things. I definitely don't think we should revert 34317c508294. We need
>>> 34317c508294 otherwise this patch doesn't fix the build.
>>
>> If "this patch" is the one outlined here, then with the reverts we wouldn't
>> need it at all. The reverts alone will fix the build issue, according to my
>> understanding.
> 
> The reverts you are suggesting do not fix the issue; they only hide it.
> The Kconfig option can no longer be disabled, which renders the entire
> patch series ineffective.

Yes, hence why we wouldn't need a revert of the entire series.

Jan


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From: Luca Fancellu 
To: Julien Grall 
CC: Hari Limaye , "xen-devel@lists.xenproject.org"
	, Penny Zheng , Stefano
 Stabellini , Bertrand Marquis
	, Michal Orzel , Volodymyr
 Babchuk , Andrew Cooper
	, Anthony PERARD , Jan
 Beulich , =?iso-8859-1?Q?Roger_Pau_Monn=E9?=
	, Wei Chen 
Subject: Re: [PATCH v3 5/5] xen/arm: map static memory on demand
Thread-Topic: [PATCH v3 5/5] xen/arm: map static memory on demand
Thread-Index: AQHcGLWqZ0Mx4e+sDU+SZKlpnxj7ELR5O3kA
Date: Fri, 29 Aug 2025 07:28:31 +0000
Message-ID: <14107953-172A-4B6C-A25E-7EC747069105@arm.com>
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Hi Julien,

> On 29 Aug 2025, at 08:22, Julien Grall  wrote:
>=20
> Hi Hari,
>=20
> On 28/08/2025 12:12, Hari Limaye wrote:
>> From: Penny Zheng 
>> In the function `init_staticmem_pages` we need to have mapped static
>> memory banks for initialization. Unlike on an MMU system, we cannot map
>> the entire RAM
>=20
> Even on the MMU system we don't always map the full RAM (for instance on =
arm32). This is why we have infrastructure like map_domain_page() (Temporar=
y mapping) and map_domain_page_global() (more permanent).
>=20
> on an MPU system as we have a limited number of MPU
>> memory regions. To solve this, transiently map the static memory banks
>> for initialization.
>=20
> I am guessing you implemented the helper because in unmap_staticmem_pages=
_to_xen(), we are calling scrub_one_page(). This will be using map_domain_p=
age() and unmap_domain_page(). I am a bit confused why we end up with brand=
 new helpers rather than implementation map_domain_page() and unmap_domain_=
page()?

yes I agree, scrub_one_page is already using {un}map_domain_page(), we will=
 investigate about it.

Cheers,
Luca=


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From: Oleksii Moisieiev 
To: Jan Beulich 
CC: Andrew Cooper , Anthony PERARD
	, Bertrand Marquis ,
	Juergen Gross , Julien Grall , Michal Orzel
	, =?utf-8?B?Um9nZXIgUGF1IE1vbm7DqQ==?=
	, Stefano Stabellini ,
	Volodymyr Babchuk , Grygorii Strashko
	, "xen-devel@lists.xenproject.org"
	
Subject: Re: [PATCH v6 3/4] xen/arm: scmi-smc: passthrough SCMI SMC to domain,
 single agent
Thread-Topic: [PATCH v6 3/4] xen/arm: scmi-smc: passthrough SCMI SMC to
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Thread-Index: AQHcGDp07aUQwsobaUO2Bmd+Gq/u2LR5OwuAgAADSoA=
Date: Fri, 29 Aug 2025 07:34:49 +0000
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Date: Fri, 29 Aug 2025 09:41:34 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Mark Syms 
Cc: jgross@suse.com, andrew.cooper3@citrix.com,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH] Clarify the cases where BLKIF_RSP_EOPNOTSUPP can be
 returned.
Message-ID: 
References: <20250828093821.372024-1-mark.syms@cloud.com>
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In-Reply-To: <20250828093821.372024-1-mark.syms@cloud.com>

On Thu, Aug 28, 2025 at 10:38:21AM +0100, Mark Syms wrote:
> Previously this said it would only happen on barrier writes. Except
> the documentation blocks for
>  * feature-flush-cache
>  * feature-discard
> 
> Also say that they can return this error.
> 
> Signed-off-by: Mark Syms 
> ---
>  xen/include/public/io/blkif.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/xen/include/public/io/blkif.h b/xen/include/public/io/blkif.h
> index 8407453324..5e617b0c67 100644
> --- a/xen/include/public/io/blkif.h
> +++ b/xen/include/public/io/blkif.h
> @@ -710,7 +710,7 @@ typedef struct blkif_response blkif_response_t;
>  /*
>   * STATUS RETURN CODES.
>   */
> - /* Operation not supported (only happens on barrier writes). */
> + /* Operation not supported, see feature-barrier, feature-flush-cache, feature-discard. */
>  #define BLKIF_RSP_EOPNOTSUPP  -2

I think there's no need to mention the specific operations. FWIW,
blkback will return BLKIF_RSP_EOPNOTSUPP for any request type it
doesn't understand (see dispatch_other_io()), which covers any
possible request type that's not yet defined:

/* Operation not supported. */
#define BLKIF_RSP_EOPNOTSUPP  -2

Should be fine.

Thanks, Roger.


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Subject: Re: [PATCH v11 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for
 guests
To: Mykola Kvach ,
 Stefano Stabellini ,
 Andrew Cooper , Julien Grall ,
 Anthony PERARD ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
Cc: "xen-devel@lists.xenproject.org" ,
 Mykola Kvach ,
 Bertrand Marquis ,
 Michal Orzel ,
 Shawn Anastasio ,
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 <87ecsvz9sx.fsf@epam.com>
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On 28.08.2025 18:32, Volodymyr Babchuk wrote:
> Mykola Kvach  writes:
>> @@ -880,6 +883,25 @@ void arch_domain_creation_finished(struct domain *d)
>>      p2m_domain_creation_finished(d);
>>  }
>>  
>> +int arch_domain_resume(struct domain *d)
>> +{
>> +    int rc;
>> +    typeof(d->arch.resume_ctx) *ctx = &d->arch.resume_ctx;
>> +
>> +    if ( !d->is_shutting_down || d->shutdown_code != SHUTDOWN_suspend )
>> +    {
>> +        dprintk(XENLOG_WARNING,
>> +                "%pd: Invalid domain state for resume: is_shutting_down=%d, shutdown_code=%d\n",
>> +                d, d->is_shutting_down, d->shutdown_code);
>> +        return -EINVAL;
>> +    }
> 
> This check probably can go into common domain_resume() function, as
> there is nothing arch-specific in here. Probably this can be done during
> commit, to save us from v12? If commiters are okay with this.

Seeing this, I'm learning that ->is_shutting_down can actually go from
true to false. Which I think is a problem (not of this series, but a pre-
existing one, see [1]). Code elsewhere assumes this to not be possible,
see e.g. __domain_crash(), but I'm also unconvinced that e.g. the shutdown
deferral logic is prepared to deal with such a case.

Jan

[1] e105919b0120 ("Add resumedomain domctl to resume a domain after checkpoint")


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Subject: Re: [PATCH v3 3/5] arm/mpu: Implement transient mapping
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To: Hari Limaye , xen-devel@lists.xenproject.org
Cc: luca.fancellu@arm.com, Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <6dc15f5279ea76ac52e89b75d56e3bd2063e91f3.1756379422.git.hari.limaye@arm.com>
From: Julien Grall 
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Hi,

On 28/08/2025 12:12, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Add a scheme to distinguish transient MPU regions, to identify MPU
> regions which will be mapped for a short period of time. This is needed
> for the functions which transiently map and unmap memory ranges on
> demand which will be introduced in a future commit.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
> Reviewed-by: Michal Orzel 
> ---
> Changes from v2:
> - Define offsets programmatically, rather than hard-coding these
> - Add Michal's R-b
> 
> Changes from v1:
> - Improve commit message
> - Mark parameter in read helper as const
> ---
>   xen/arch/arm/arm32/asm-offsets.c         |  3 ++-
>   xen/arch/arm/arm64/asm-offsets.c         |  2 ++
>   xen/arch/arm/include/asm/arm32/mpu.h     |  2 ++
>   xen/arch/arm/include/asm/arm64/mpu.h     |  2 ++
>   xen/arch/arm/include/asm/mpu/mm.h        | 14 +++++++++++++-
>   xen/arch/arm/include/asm/mpu/regions.inc | 17 +++++++++++++----
>   xen/arch/arm/mpu/mm.c                    | 23 ++++++++++++++---------
>   7 files changed, 48 insertions(+), 15 deletions(-)
> 
> diff --git a/xen/arch/arm/arm32/asm-offsets.c b/xen/arch/arm/arm32/asm-offsets.c
> index c203ce269d..f354bf374d 100644
> --- a/xen/arch/arm/arm32/asm-offsets.c
> +++ b/xen/arch/arm/arm32/asm-offsets.c
> @@ -43,7 +43,6 @@ void __dummy__(void)
>      OFFSET(UREGS_SP_und, struct cpu_user_regs, sp_und);
>      OFFSET(UREGS_LR_und, struct cpu_user_regs, lr_und);
>      OFFSET(UREGS_SPSR_und, struct cpu_user_regs, spsr_und);
> -

Spurious change?

>      OFFSET(UREGS_SP_irq, struct cpu_user_regs, sp_irq);
>      OFFSET(UREGS_LR_irq, struct cpu_user_regs, lr_irq);
>      OFFSET(UREGS_SPSR_irq, struct cpu_user_regs, spsr_irq);
> @@ -79,6 +78,8 @@ void __dummy__(void)
>   #ifdef CONFIG_MPU
>      DEFINE(XEN_MPUMAP_MASK_sizeof, sizeof(xen_mpumap_mask));
>      DEFINE(XEN_MPUMAP_sizeof, sizeof(xen_mpumap));
> +   DEFINE(XEN_MPUMAP_ENTRY_SHIFT, ilog2(sizeof(pr_t)));
> +   DEFINE(XEN_MPUMAP_ENTRY_ZERO_OFFSET, sizeof(prbar_t) + sizeof(prlar_t));
>      BLANK();
>   #endif
>   }
> diff --git a/xen/arch/arm/arm64/asm-offsets.c b/xen/arch/arm/arm64/asm-offsets.c
> index 320289b281..38a3894a3b 100644
> --- a/xen/arch/arm/arm64/asm-offsets.c
> +++ b/xen/arch/arm/arm64/asm-offsets.c
> @@ -73,6 +73,8 @@ void __dummy__(void)
>   #ifdef CONFIG_MPU
>      DEFINE(XEN_MPUMAP_MASK_sizeof, sizeof(xen_mpumap_mask));
>      DEFINE(XEN_MPUMAP_sizeof, sizeof(xen_mpumap));
> +   DEFINE(XEN_MPUMAP_ENTRY_SHIFT, ilog2(sizeof(pr_t)));
> +   DEFINE(XEN_MPUMAP_ENTRY_ZERO_OFFSET, sizeof(prbar_t) + sizeof(prlar_t));
>      BLANK();
>   #endif
>   }
> diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/asm/arm32/mpu.h
> index 0a6930b3a0..9906d98809 100644
> --- a/xen/arch/arm/include/asm/arm32/mpu.h
> +++ b/xen/arch/arm/include/asm/arm32/mpu.h
> @@ -39,6 +39,8 @@ typedef union {
>   typedef struct {
>       prbar_t prbar;
>       prlar_t prlar;
> +    bool transient;
 > +    uint8_t pad[7]; /* Pad structure to 16 Bytes */>   } pr_t;
>   
>   #endif /* __ASSEMBLY__ */
> diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/asm/arm64/mpu.h
> index f0ce344e78..1d1843eda0 100644
> --- a/xen/arch/arm/include/asm/arm64/mpu.h
> +++ b/xen/arch/arm/include/asm/arm64/mpu.h
> @@ -38,6 +38,8 @@ typedef union {
>   typedef struct {
>       prbar_t prbar;
>       prlar_t prlar;
> +    bool transient;
> +    uint8_t pad[15]; /* Pad structure to 32 Bytes */
>   } pr_t;
>   
>   #endif /* __ASSEMBLY__ */
> diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
> index e1ded6521d..566d338986 100644
> --- a/xen/arch/arm/include/asm/mpu/mm.h
> +++ b/xen/arch/arm/include/asm/mpu/mm.h
> @@ -55,6 +55,16 @@ static inline void context_sync_mpu(void)
>       isb();
>   }
>   
> +static inline bool region_is_transient(const pr_t *pr)
> +{
> +    return pr->transient;
> +}
> +
> +static inline void region_set_transient(pr_t *pr, bool transient)
> +{
> +    pr->transient = transient;
> +}
> +
>   /*
>    * The following API requires context_sync_mpu() after being used to modify MPU
>    * regions:
> @@ -75,9 +85,11 @@ void write_protection_region(const pr_t *pr_write, uint8_t sel);
>    * @param base      Base address of the range to map (inclusive).
>    * @param limit     Limit address of the range to map (exclusive).
>    * @param flags     Flags for the memory range to map.
> + * @param transient True for a transient mapping, otherwise False.

Why can't this be part of the flags?

>    * @return          0 on success, negative on error.
>    */
> -int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags);
> +int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
> +                      bool transient);
>   
>   /*
>    * Creates a pr_t structure describing a protection region.
> diff --git a/xen/arch/arm/include/asm/mpu/regions.inc b/xen/arch/arm/include/asm/mpu/regions.inc
> index 23fead3b21..09e1dcf03f 100644
> --- a/xen/arch/arm/include/asm/mpu/regions.inc
> +++ b/xen/arch/arm/include/asm/mpu/regions.inc
> @@ -14,19 +14,25 @@
>   #define PRLAR_ELx_EN            0x1
>   
>   #ifdef CONFIG_ARM_64
> -#define XEN_MPUMAP_ENTRY_SHIFT  0x4     /* 16 byte structure */
> -
>   .macro store_pair reg1, reg2, dst
>       stp \reg1, \reg2, [\dst]
>   .endm
>   
> -#else
> -#define XEN_MPUMAP_ENTRY_SHIFT  0x3     /* 8 byte structure */
> +.macro zero_pair dst, offset, tmp1, tmp2
 > +    stp xzr, xzr, [\dst, \offset]> +.endm
>   
> +#else
>   .macro store_pair reg1, reg2, dst
>       strd  \reg1, \reg2, [\dst]
>   .endm
>   
> +.macro zero_pair dst, offset, tmp1, tmp2
> +    mov \tmp1, #0
> +    mov \tmp2, #0
> +    strd \tmp1, \tmp2, [\dst, \offset]
> +.endm
 > +

TBH the addition of zero_pair feels a bit overkill when there is one 
user. Why can't we open-code the use case below and use ``store_pair``?

This would also avoid the "tmp1" and "tmp2" which are not used by arm64.

Cheers,

-- 
Julien Grall



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From: Roger Pau Monne 
To: xen-devel@lists.xenproject.org
Cc: Roger Pau Monne ,
	Jan Beulich ,
	Andrew Cooper 
Subject: [PATCH] x86/pvshim: disable PDX compression in PV shim defconfig
Date: Fri, 29 Aug 2025 09:51:54 +0200
Message-ID: <20250829075154.48787-1-roger.pau@citrix.com>
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There's no need for PDX compression given the memory map provided by Xen
to guests is contiguous, turn off the feature by default in the PV shim
defconfig.

Reported-by: Jan Beulich 
Fixes: c5c45bcbd6a1 ('pdx: introduce a new compression algorithm based on region offsets')
Signed-off-by: Roger Pau Monné 
---
 xen/arch/x86/configs/pvshim_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/xen/arch/x86/configs/pvshim_defconfig b/xen/arch/x86/configs/pvshim_defconfig
index c58c29adb0bf..24f4e4857dde 100644
--- a/xen/arch/x86/configs/pvshim_defconfig
+++ b/xen/arch/x86/configs/pvshim_defconfig
@@ -7,6 +7,7 @@ CONFIG_PV_SHIM_EXCLUSIVE=y
 CONFIG_NR_CPUS=32
 CONFIG_EXPERT=y
 # Disable features not used by the PV shim
+CONFIG_PDX_NONE=y
 # CONFIG_XEN_SHSTK is not set
 # CONFIG_XEN_IBT is not set
 # CONFIG_GRANT_TABLE is not set
-- 
2.51.0



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Subject: Re: [PATCH v3 4/5] arm/mpu: Implement ioremap_attr for MPU
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To: Hari Limaye , xen-devel@lists.xenproject.org
Cc: luca.fancellu@arm.com, Stefano Stabellini ,
 Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <53c6aa61bc0cefce369ffc3a9ff5a7060b5f4b20.1756379422.git.hari.limaye@arm.com>
From: Julien Grall 
In-Reply-To: <53c6aa61bc0cefce369ffc3a9ff5a7060b5f4b20.1756379422.git.hari.limaye@arm.com>
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Hi Hari,

On 28/08/2025 12:12, Hari Limaye wrote:
> From: Luca Fancellu 
> 
> Introduce helpers (un)map_mm_range() in order to allow the transient
> mapping of a range of memory, and use these to implement the function
> `ioremap_attr` for MPU systems.
> 
> Signed-off-by: Luca Fancellu 
> Signed-off-by: Hari Limaye 
> ---
> Changes from v2:
> - Propagate error to caller of is_mm_range_mapped, rather than panic
> 
> Changes from v1:
> - Use transient instead of temporary, and improve wording of comments
>    regarding transient mapping
> - Rename start, end -> base, limit
> ---
>   xen/arch/arm/include/asm/mpu/mm.h |  22 +++++
>   xen/arch/arm/mpu/mm.c             | 157 ++++++++++++++++++++++++++++--
>   2 files changed, 170 insertions(+), 9 deletions(-)
> 
> diff --git a/xen/arch/arm/include/asm/mpu/mm.h b/xen/arch/arm/include/asm/mpu/mm.h
> index 566d338986..efb0680e39 100644
> --- a/xen/arch/arm/include/asm/mpu/mm.h
> +++ b/xen/arch/arm/include/asm/mpu/mm.h
> @@ -101,6 +101,28 @@ int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
>    */
>   pr_t pr_of_addr(paddr_t base, paddr_t limit, unsigned int flags);
>   
> +/*
> + * Maps transiently a range of memory with attributes `flags`; if the range is
> + * already mapped with the same attributes, including an inclusive match, the
> + * existing mapping is returned. This API is intended for mappings that exist
> + * transiently for a short period between calls to this function and
> + * `unmap_mm_range`.
> + *
> + * @param base      Base address of the range to map (inclusive).
> + * @param limit     Limit address of the range to map (exclusive).
> + * @param flags     Flags for the memory range to map.
> + * @return          Pointer to base of region on success, NULL on error.
> + */
 > +void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags);

I think I am missing a couple of things:

  * The current use seems to be ioremap() which tends to be mapping for 
the lifetime of Xen. So I would not describe them as transient.
  * It is unclear to me why we need a different interface and can't use 
exist one. The name also doesn't make very clear that the mapping will 
be "transient" (whatever that means).

> +
> +/*
> + * Unmaps a range of memory if it was previously mapped by map_mm_range,
> + * otherwise it does not remove the mapping.
> + *
> + * @param base     Base address of the range to map (inclusive).
> + */
> +void unmap_mm_range(paddr_t base);
> +
>   /*
>    * Checks whether a given memory range is present in the provided table of
>    * MPU protection regions.
> diff --git a/xen/arch/arm/mpu/mm.c b/xen/arch/arm/mpu/mm.c
> index 33333181d5..337573f9d7 100644
> --- a/xen/arch/arm/mpu/mm.c
> +++ b/xen/arch/arm/mpu/mm.c
> @@ -332,31 +332,39 @@ static int xen_mpumap_update_entry(paddr_t base, paddr_t limit,
>       return 0;
>   }
>   
> -int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
> -                      bool transient)
> +static bool check_mpu_mapping(paddr_t base, paddr_t limit, unsigned int flags)
>   {
> -    int rc;
> -
>       if ( flags_has_rwx(flags) )
>       {
>           printk("Mappings should not be both Writeable and Executable\n");
> -        return -EINVAL;
> +        return false;
>       }
>   
>       if ( base >= limit )
>       {
>           printk("Base address %#"PRIpaddr" must be smaller than limit address %#"PRIpaddr"\n",
>                  base, limit);
> -        return -EINVAL;
> +        return false;
>       }
>   
>       if ( !IS_ALIGNED(base, PAGE_SIZE) || !IS_ALIGNED(limit, PAGE_SIZE) )
>       {
>           printk("base address %#"PRIpaddr", or limit address %#"PRIpaddr" is not page aligned\n",
>                  base, limit);
> -        return -EINVAL;
> +        return false;
>       }
>   
> +    return true;
> +}
> +
> +int xen_mpumap_update(paddr_t base, paddr_t limit, unsigned int flags,
> +                      bool transient)
> +{
> +    int rc;
> +
> +    if ( !check_mpu_mapping(base, limit, flags) )
> +        return -EINVAL;
> +
>       spin_lock(&xen_mpumap_lock);
>   
>       rc = xen_mpumap_update_entry(base, limit, flags, transient);
> @@ -465,10 +473,141 @@ void free_init_memory(void)
>       BUG_ON("unimplemented");
>   }
>   
> +static int is_mm_range_mapped(paddr_t start, paddr_t end, uint8_t *idx)
> +{
> +    ASSERT(spin_is_locked(&xen_mpumap_lock));
> +
> +    /*
> +     * 'idx' will be INVALID_REGION_IDX for rc == MPUMAP_REGION_NOTFOUND and
> +     * it will be a proper region index when rc >= MPUMAP_REGION_FOUND.
> +     */


I feels this comment belongs on top of ``is_mm_range_mapped()`` because 
it describe the behavior of the function.

> +    return mpumap_contains_region(xen_mpumap, max_mpu_regions, start, end, idx);
> +}
> +
> +static bool is_mm_attr_match(pr_t *region, unsigned int attributes)
> +{
> +    bool ret = true;
> +
> +    if ( region->prbar.reg.ro != PAGE_RO_MASK(attributes) )
> +    {
> +        printk(XENLOG_WARNING
> +               "Mismatched Access Permission attributes (%#x0 instead of %#x0)\n",
> +               region->prbar.reg.ro, PAGE_RO_MASK(attributes));
> +        ret = false;
> +    }
> +
> +    if ( region->prbar.reg.xn != PAGE_XN_MASK(attributes) )
> +    {
> +        printk(XENLOG_WARNING
> +               "Mismatched Execute Never attributes (%#x instead of %#x)\n",
> +               region->prbar.reg.xn, PAGE_XN_MASK(attributes));
> +        ret = false;
> +    }
> +
> +    if ( region->prlar.reg.ai != PAGE_AI_MASK(attributes) )
> +    {
> +        printk(XENLOG_WARNING
> +               "Mismatched Memory Attribute Index (%#x instead of %#x)\n",
> +               region->prlar.reg.ai, PAGE_AI_MASK(attributes));
> +        ret = false;
> +    }
> +
> +    return ret;
> +}
> +
> +void *map_mm_range(paddr_t base, paddr_t limit, unsigned int flags)
> +{
> +    paddr_t start_pg = round_pgdown(base);
> +    paddr_t end_pg = round_pgup(limit);
> +    void *ret = NULL;
> +    uint8_t idx;
> +    int rc;
> +
> +    if ( !check_mpu_mapping(start_pg, end_pg, flags) )
> +        return NULL;
> +
> +    spin_lock(&xen_mpumap_lock);
> +
> +    rc = is_mm_range_mapped(start_pg, end_pg, &idx);
> +    if ( rc < 0 ) {

Coding style:

if ( rc < 0 )
{

> +        printk(XENLOG_WARNING
> +               "Cannot handle overlapping MPU memory protection regions\n");
> +        goto out;
> +    }
> +
> +    if ( idx != INVALID_REGION_IDX )
> +    {
> +        /* Already mapped with different attributes */
> +        if ( !is_mm_attr_match(&xen_mpumap[idx], flags) )
> +        {
> +            printk(XENLOG_WARNING
> +                   "Range %#"PRIpaddr"-%#"PRIpaddr" already mapped with different flags\n",
> +                   start_pg, end_pg);
> +            goto out;
> +        }
> +
> +        /* Already mapped with same attributes */
> +        ret = maddr_to_virt(base);
> +        goto out;
> +    }
> +
> +    if ( !xen_mpumap_update_entry(start_pg, end_pg, flags, true) )
> +    {
> +        context_sync_mpu();
> +        ret = maddr_to_virt(base);
> +    }
> +
> + out:
> +    spin_unlock(&xen_mpumap_lock);
> +
> +    return ret;
> +}
> +
> +void unmap_mm_range(paddr_t base)
> +{
> +    uint8_t idx;
> +    int rc;
> +
> +    spin_lock(&xen_mpumap_lock);
> +
> +    /*
> +     * Mappings created via map_mm_range are at least PAGE_SIZE. Find the idx
> +     * of the MPU memory region containing `start` mapped through map_mm_range.
> +     */
> +    rc = is_mm_range_mapped(base, base + PAGE_SIZE, &idx);
> +    if ( rc < 0 ) {

Style:

if ( rc < 0 )
{

> +        printk(XENLOG_WARNING
> +               "Cannot handle overlapping MPU memory protection regions\n");

I think this message is incorrect. AFACT, If is_mm_range_mapped() 
returns a negative value, then it means the region is unmapped.

> +        goto out;
> +    }
> +
> +    if ( idx == INVALID_REGION_IDX )
> +    {
> +        printk(XENLOG_ERR
> +               "Failed to unmap_mm_range MPU memory region at %#"PRIpaddr"\n",
> +               base);
> +        goto out;
> +    }
> +
> +    /* This API is only meant to unmap transient regions */

So the transient flag is more for debugging purpose? But if it really 
happens then...

> +    if ( !region_is_transient(&xen_mpumap[idx]) )
 > +        goto out;

... why do we silently fail? Surely this would indicate an error on the 
system which we want to know in debug build.

> +
> +    /* Disable MPU memory region and clear the associated entry in xen_mpumap */
> +    disable_mpu_region_from_index(idx);
> +    context_sync_mpu();
> +
> + out:
> +    spin_unlock(&xen_mpumap_lock);
> +}
> +
>   void __iomem *ioremap_attr(paddr_t start, size_t len, unsigned int flags)
>   {
> -    BUG_ON("unimplemented");
> -    return NULL;
> +    if ( !map_mm_range(start, start + len, flags) )
> +        return NULL;
> +
> +    /* Mapped or already mapped */
> +    return maddr_to_virt(start);
>   }
>   
>   /*

Cheers,

-- 
Julien Grall



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Subject: Re: [PATCH] x86/pvshim: disable PDX compression in PV shim defconfig
To: Roger Pau Monne 
Cc: Andrew Cooper , xen-devel@lists.xenproject.org
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On 29.08.2025 09:51, Roger Pau Monne wrote:
> There's no need for PDX compression given the memory map provided by Xen
> to guests is contiguous, turn off the feature by default in the PV shim
> defconfig.
> 
> Reported-by: Jan Beulich 
> Fixes: c5c45bcbd6a1 ('pdx: introduce a new compression algorithm based on region offsets')
> Signed-off-by: Roger Pau Monné 

Acked-by: Jan Beulich 

Not sure if a Fixes: tag is really appropriate here. The shim is working as
is, just carrying code which won't ever be used.

Jan


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To: Xen-devel ,
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 "committers@xenproject.org" 
From: Oleksii Kurochko 
Subject: Feature Freeze Extension until September 5, 2025

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Hello Community,

I would like to announce that the Feature Freeze period is extended until
*Friday, September 5, 2025*, as we have a number of patch series that
are very close to being merged.

Have a good day.

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  Oleksii

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    Hello Community,
    
    
    I would like to announce that the Feature Freeze period is extended until
Friday, September 5, 2025, as we have a number of patch series that
are very close to being merged.
    
    
    Have a good day.
    
    
    Best regards,
 Oleksii
    
  


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Subject: Re: [PATCH] Clarify the cases where BLKIF_RSP_EOPNOTSUPP can be returned.
To: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
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On Fri, 29 Aug 2025 at 08:41, Roger Pau Monn=C3=A9  w=
rote:
> I think there's no need to mention the specific operations. FWIW,
> blkback will return BLKIF_RSP_EOPNOTSUPP for any request type it
> doesn't understand (see dispatch_other_io()), which covers any
> possible request type that's not yet defined:
>
> /* Operation not supported. */
> #define BLKIF_RSP_EOPNOTSUPP  -2
>
> Should be fine.

OK, I'll reduce that comment to the minimum then, I was just trying to
be helpful to future us :)


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Date: Fri, 29 Aug 2025 10:56:15 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: Andrew Cooper ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH] x86/pvshim: disable PDX compression in PV shim defconfig
Message-ID: 
References: <20250829075154.48787-1-roger.pau@citrix.com>
 
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On Fri, Aug 29, 2025 at 10:10:59AM +0200, Jan Beulich wrote:
> On 29.08.2025 09:51, Roger Pau Monne wrote:
> > There's no need for PDX compression given the memory map provided by Xen
> > to guests is contiguous, turn off the feature by default in the PV shim
> > defconfig.
> > 
> > Reported-by: Jan Beulich 
> > Fixes: c5c45bcbd6a1 ('pdx: introduce a new compression algorithm based on region offsets')
> > Signed-off-by: Roger Pau Monné 
> 
> Acked-by: Jan Beulich 
> 
> Not sure if a Fixes: tag is really appropriate here. The shim is working as
> is, just carrying code which won't ever be used.

I was borderline also, but I felt it was important to notice that the
change here should ideally had been part of that commit.  Do you have
a recommendation of any other tag I could use for that purpose?

Thanks, Roger.


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	andrew.cooper3@citrix.com,
	xen-devel@lists.xenproject.org
Cc: Mark Syms 
Subject: [PATCH v2] Clarify the cases where BLKIF_RSP_EOPNOTSUPP can be returned.
Date: Fri, 29 Aug 2025 09:56:27 +0100
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Previously this said it would only happen on barrier writes. Except
the documentation blocks for
 * feature-flush-cache
 * feature-discard

Also say that they can return this error.

Signed-off-by: Mark Syms 

---
v2: simplify to remove references to features as requested.
---
 xen/include/public/io/blkif.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/include/public/io/blkif.h b/xen/include/public/io/blkif.h
index 8407453324..e96c9af7c6 100644
--- a/xen/include/public/io/blkif.h
+++ b/xen/include/public/io/blkif.h
@@ -710,7 +710,7 @@ typedef struct blkif_response blkif_response_t;
 /*
  * STATUS RETURN CODES.
  */
- /* Operation not supported (only happens on barrier writes). */
+ /* Operation not supported. */
 #define BLKIF_RSP_EOPNOTSUPP  -2
  /* Operation failed for some unspecified reason (-EIO). */
 #define BLKIF_RSP_ERROR       -1
-- 
2.50.1



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Date: Fri, 29 Aug 2025 11:15:07 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Jan Beulich 
Cc: Frediano Ziglio ,
	xen-devel@lists.xenproject.org,
	"Daniel P. Smith" 
Subject: Re: [PATCH v2] xen/efi: Fix crash with initial empty EFI options
Message-ID: 
References: <20250708135701.119601-1-frediano.ziglio@cloud.com>
 
 
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--FMrMt6kYOwCZ9Zpx
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Date: Fri, 29 Aug 2025 11:15:07 +0200
From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= 
To: Jan Beulich 
Cc: Frediano Ziglio ,
	xen-devel@lists.xenproject.org,
	"Daniel P. Smith" 
Subject: Re: [PATCH v2] xen/efi: Fix crash with initial empty EFI options

On Fri, Aug 29, 2025 at 09:17:31AM +0200, Jan Beulich wrote:
> On 29.08.2025 06:06, Marek Marczykowski-G=C3=B3recki wrote:
> > On Tue, Jul 08, 2025 at 02:56:58PM +0100, Frediano Ziglio wrote:
> >> EFI code path split options from EFI LoadOptions fields in 2
> >> pieces, first EFI options, second Xen options.
> >> "get_argv" function is called first to get the number of arguments
> >> in the LoadOptions, second, after allocating enough space, to
> >> fill some "argc"/"argv" variable. However the first parsing could
> >> be different from second as second is able to detect "--" argument
> >> separator. So it was possible that "argc" was bigger that the "argv"
> >> array leading to potential buffer overflows, in particular
> >> a string like "-- a b c" would lead to buffer overflow in "argv"
> >> resulting in crashes.
> >=20
> > I wouldn't call it "buffer overflow" - the argv array is big enough
> > here. But if there is "--" in cmdline, it has fewer than argc elements
> > initialized. If there is at least one efi option (IOW, "--" is not the
> > first one), the sentinel NULL inserted by get_argv() will prevent
> > reading past the initialized part. But if "--" is the first one, the
> > NULL is inserted into argv[0], which is skipped by the loop in
> > efi_start(). Which makes the loop go beyond initialized part of argv
> > (crash happens even before it goes beyond end of argv allocation).
> >=20
> > So, maybe change it to: bigger than the initialized portion of "argv"
> > array, leading to potential uninitialized pointer dereference, ...?
> >=20
> >> Using EFI shell is possible to pass any kind of string in
> >> LoadOptions.
> >>
> >> Fixes: bf6501a62e80 ("x86-64: EFI boot code")
> >=20
> > Technically, the issue was covered for few months by another issue and
> > got re-exposed by 926e680aadde ("EFI: suppress bogus loader warning").
> > While it fixed one issue, it also made it possible to put sentinel NULL
> > into argv[0] again. But the original EFI code had this issue too, so
> > IMO the Fixes tag is correct.
> >=20
> > While there is convention to put file name as the first option, I don't
> > see anything in the UEFI spec requiring it. So, Xen should not crash
> > when it's missing.
>=20
> Yet if the equivalent of argv[0] is missing from the command line, how
> do we even know whether the first token on the command line is an
> option (or the -- separator)?

I think that assumption of argv[0] presence in LoadOptions was always
buggy... But at this point everybody is adding "placeholder" as the
first argument anyway (which predates EFI code in Xen), so we can very
well continue to require it, at least in this release.

--=20
Best Regards,
Marek Marczykowski-G=C3=B3recki
Invisible Things Lab

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Message-ID: <4b852055-4651-46ad-8f04-3f95fb2fa631@citrix.com>
Date: Fri, 29 Aug 2025 10:34:04 +0100
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Subject: Re: [PATCH] Optimise restore memory allocation
From: Andrew Cooper 
To: Frediano Ziglio ,
 xen-devel@lists.xenproject.org
Cc: Anthony PERARD ,
 Juergen Gross , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?=
 , Oleksii Kurochko 
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In-Reply-To: <3cf8eef1-04e6-44b9-ad41-144de9cbf1d7@citrix.com>
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On 27/08/2025 6:23 pm, Andrew Cooper wrote:
> Subject wants to be at least tools/libxc, and probably "Use superpages
> where possible on migrate/resume"
>
>
> On 27/08/2025 1:33 pm, Frediano Ziglio wrote:
>> Try to allocate larger order pages.
>> With some test memory program stressing TLB (many small random
>> memory accesses) you can get 15% performance improves.
>> On the first memory iteration the sender is currently sending
>> memory in 4mb aligned chunks which allows the receiver to
>> allocate most pages as 2mb superpages instead of single 4kb pages.
> It's critical to say somewhere that this is applicable to HVM guests.
>
> You've eluded to it, but it's important to state clearly that, for HVM
> guests, PAGE_DATA records contain metadata about GFNs in aligned 4M
> blocks.  This is why we don't even need to buffer a second record.
>
> It's also worth stating that 1G superpages are left for later.
>
>
> CC-ing Oleksii as release manager.  This is a fix for a (mis)feature
> which has been known for a decade (since Xen 4.6), and for which two
> series have been posted but not managed to get in.  Unlike those series,
> this is a very surgical fix that gets the majority of the perf win back,
> without the complexity of trying to guess at 1G pages.
>
> Therefore I'd like to request that it be considered for 4.21 at this
> juncture.
>
>> Signed-off-by: Frediano Ziglio 
>> ---
>>  tools/libs/guest/xg_sr_restore.c | 39 ++++++++++++++++++++++++++++----
>>  1 file changed, 35 insertions(+), 4 deletions(-)
>>
>> diff --git a/tools/libs/guest/xg_sr_restore.c b/tools/libs/guest/xg_sr_restore.c
>> index 06231ca826..8dcb1b19c5 100644
>> --- a/tools/libs/guest/xg_sr_restore.c
>> +++ b/tools/libs/guest/xg_sr_restore.c
>> @@ -129,6 +129,8 @@ static int pfn_set_populated(struct xc_sr_context *ctx, xen_pfn_t pfn)
>>      return 0;
>>  }
>>  
>> +#define IS_POWER_OF_2(n) (((n) & ((n) - 1)) == 0)
>> +
>>  /*
>>   * Given a set of pfns, obtain memory from Xen to fill the physmap for the
>>   * unpopulated subset.  If types is NULL, no page type checking is performed
>> @@ -141,6 +143,7 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
>>      xen_pfn_t *mfns = malloc(count * sizeof(*mfns)),
>>          *pfns = malloc(count * sizeof(*pfns));
>>      unsigned int i, nr_pfns = 0;
>> +    bool contiguous = true;
>>      int rc = -1;
>>  
>>      if ( !mfns || !pfns )
>> @@ -159,18 +162,46 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
>>              if ( rc )
>>                  goto err;
>>              pfns[nr_pfns] = mfns[nr_pfns] = original_pfns[i];
>> +            if ( pfns[nr_pfns] != pfns[0] + nr_pfns )
>> +                contiguous = false;
>>              ++nr_pfns;
>>          }
>>      }
>>  
>>      if ( nr_pfns )
>>      {
>> -        rc = xc_domain_populate_physmap_exact(
>> -            xch, ctx->domid, nr_pfns, 0, 0, mfns);
>> +        /* try optimizing using larger order */
>> +        rc = -1;
>> +        /*
>> +         * The "nr_pfns <= (1 << 18)" check is mainly for paranoia, it should
>> +         * never happen, the sender would have to send a really large packet.
>> +         */
>> +        if ( contiguous && nr_pfns <= (1 << 18) &&
> This is an arbitrary limit, and to contradict the prior feedback given
> in private, the domain's MAX_ORDER isn't relevant here.  It's the
> toolstack's choice how to lay out the guest in memory.
>
>> +             IS_POWER_OF_2(nr_pfns) && (pfns[0] & (nr_pfns - 1)) == 0 )
>> +        {
>> +            const unsigned int extent_order = __builtin_ffs(nr_pfns) - 1;
> This (non-)loop isn't great.  You'll e.g. use 4k pages for the second 2M
> page of an HVM guest simply because the VGA hole exists in the first.
>
> I think you probably want something like:
>
> int populate_physmap_4k(ctx, nr, mfns);
> int populate_physmap_2M(ctx, nr, mfns);
>
> as simple wrappers around the raw hypercalls including transforming back
> the mfns[] array, and:
>
> int populate_phymap(...);
>
> with logic of the form:
>
>     while ( nr )
>     {
>         if ( nr < 512 ) /* Can't be a superpage */
>         {
>             populate_physmap_4k(ctx, i, mfns);
>             mfns += i;
>             nr -= i;
>             continue;
>         }
>
>         if ( !ALIGNED_2M(mfn) ) /* Populate up until a point that could be a superpage */
>         {
>             while ( !ALIGNED_2M(mfn + i) )
>                 i++;
>             populate_physmap_4k(ctx, i, mfns);
>             mfns += i;
>             nr -= i;
>         }
>
>         if ( nr >= 512 )
>         {
>             for ( i = 1; i < 512; ++i )
>                 if ( mfns[i] != mfns[0] + i )
>                     break;
>             if ( i == 512 )
>                 populate_physmap_2M(ctx, i, mfns);
>             else
>                 populate_physmap_4k(...);
>
>             mfns += i;
>             nr -= i;
>         }
>     }
>
>
>
> Obviously with error handling, and whatever boundary conditions I've got
> wrong.
>
> 2M is the only size that matters (ignoring 1G which we've excluded for
> now), and this form will reconstruct more superpages for the guest than
> trying to do 4M allocations will.

Actually, I think a simpler option is to alter the first loop, where
you've got contiguous= right now.

Something like:

@@ -158,6 +165,18 @@ int populate_pfns(struct xc_sr_context *ctx, unsigned int count,
             rc = pfn_set_populated(ctx, original_pfns[i]);
             if ( rc )
                 goto err;
+
+            if ( ALIGNED_2M(original_pfns[i]) &&
+                 can_populate_2M(&original_pfns[i], count - i) )
+            {
+                xen_pfn_t mfn = original_pfns[i];
+
+                rc = xc_domain_populate_physmap_exact(xch, ctx->domid, 1, ORDER_2M, 0, &mfn);
+
+                ...
+
+                i += 511;
+                continue;
+            }
+
             pfns[nr_pfns] = mfns[nr_pfns] = original_pfns[i];
             ++nr_pfns;
         }


with error handling of course.  This way we don't potentially fall back
to many separate hypercalls for 4k pages.

~Andrew


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Date: Fri, 29 Aug 2025 12:48:10 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v4 08/12] xen/arm: vgic: add resource management for
 extended SPIs
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 <9e8a11b024833c1b91b8806e7708bf35b04a8f6e.1756317702.git.leonid_komarianskyi@epam.com>
 <01a964ac-a9aa-4301-b3da-5691e18b1b73@gmail.com>
 <801cb42f-3d1e-4173-a5e6-d68c70d89fc7@epam.com>
Content-Language: en-US
From: Oleksandr Tyshchenko 
In-Reply-To: <801cb42f-3d1e-4173-a5e6-d68c70d89fc7@epam.com>
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On 28.08.25 22:09, Leonid Komarianskyi wrote:
> Hello Oleksandr,

Hello Leonid


> 
> Thank you for your comment and suggestions.
> 
> On 28.08.25 20:34, Oleksandr Tyshchenko wrote:
>>
>>
>> On 27.08.25 21:24, Leonid Komarianskyi wrote:
>>
>> Hello Leonid
>>
>>> This change introduces resource management in the VGIC to handle
>>> extended SPIs introduced in GICv3.1. The pending_irqs and
>>> allocated_irqs arrays are resized to support the required
>>> number of eSPIs, based on what is supported by the hardware and
>>> requested by the guest. A new field, ext_shared_irqs, is added
>>> to the VGIC structure to store information about eSPIs, similar
>>> to how shared_irqs is used for regular SPIs.
>>>
>>> Since the eSPI range starts at INTID 4096 and INTIDs between 1025
>>> and 4095 are reserved, helper macros are introduced to simplify the
>>> transformation of indices and to enable easier access to eSPI-specific
>>> resources. These changes prepare the VGIC for processing eSPIs as
>>> required by future functionality.
>>>
>>> The initialization and deinitialization paths for vgic have been updated
>>> to allocate and free these resources appropriately. Additionally,
>>> updated handling of INTIDs greater than 1024, passed from the toolstack
>>> during domain creation, and verification logic ensures only valid SPI or
>>> eSPI INTIDs are used.
>>>
>>> The existing SPI behavior remains unaffected when guests do not request
>>> eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
>>> option is disabled.
>>>
>>> Signed-off-by: Leonid Komarianskyi 
>>>
>>> ---
>>> Changes in V4:
>>> - added has_espi field to simplify determining whether a domain is able
>>>     to operate with eSPI
>>> - fixed formatting issues and misspellings
>>>
>>> Changes in V3:
>>> - fixed formatting for lines with more than 80 symbols
>>> - introduced helper functions to be able to use stubs in case of
>>>     CONFIG_GICV3_ESPI disabled, and as a result, reduce the number of
>>>     #ifdefs
>>> - fixed checks for nr_spis in domain_vgic_init
>>> - updated comment about nr_spis adjustments with dom0less mention
>>> - moved comment with additional explanations before checks
>>> - used unsigned int for indexes since they cannot be negative
>>> - removed unnecessary parentheses
>>> - move vgic_ext_rank_offset to the below ifdef guard, to reduce the
>>>     number of ifdefs
>>>
>>> Changes in V2:
>>> - change is_espi_rank to is_valid_espi_rank to verify whether the array
>>>     element ext_shared_irqs exists. The previous version, is_espi_rank,
>>>     only checked if the rank index was less than the maximum possible eSPI
>>>     rank index, but this could potentially result in accessing a
>>>     non-existing array element. To address this, is_valid_espi_rank was
>>>     introduced, which ensures that the required eSPI rank exists
>>> - move gic_number_espis to
>>>     xen/arm: gicv3: implement handling of GICv3.1 eSPI
>>> - update vgic_is_valid_irq checks to allow operating with eSPIs
>>> - remove redundant newline in vgic_allocate_virq
>>> ---
>>>    xen/arch/arm/include/asm/vgic.h |  20 +++
>>>    xen/arch/arm/vgic.c             | 213 +++++++++++++++++++++++++++++++-
>>>    2 files changed, 230 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/
>>> asm/vgic.h
>>> index 3e7cbbb196..fb4cea73eb 100644
>>> --- a/xen/arch/arm/include/asm/vgic.h
>>> +++ b/xen/arch/arm/include/asm/vgic.h
>>> @@ -146,6 +146,12 @@ struct vgic_dist {
>>>        int nr_spis; /* Number of SPIs */
>>>        unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
>>>        struct vgic_irq_rank *shared_irqs;
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    struct vgic_irq_rank *ext_shared_irqs;
>>> +    int nr_espis; /* Number of extended SPIs */
>>
>> Can nr_espis be negative?
>>
> 
> No, it cannot, so I will change it to unsigned int in V5.
> 
>>> +    /* To simplify determining whether a domain is able to operate
>>> with eSPI */
>>> +    bool has_espi;
>>
>> I agree with the Volodymyr's comment provided in separate letter that we
>> could avoid adding an extra var.
>>
> 
> Sure, as I mentioned to Volodymyr, I will remove it in V5.
> 
>>> +#endif
>>>        /*
>>>         * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
>>>         * struct arch_vcpu.
>>> @@ -243,6 +249,14 @@ struct vgic_ops {
>>>    /* Number of ranks of interrupt registers for a domain */
>>>    #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
>>> +#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
>>> +#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
>>> +#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
>>> +#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
>>> +#endif
>>> +
>>>    #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
>>>    #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
>>> @@ -302,6 +316,12 @@ extern struct vgic_irq_rank
>>> *vgic_rank_offset(struct vcpu *v,
>>>                                                  unsigned int b,
>>>                                                  unsigned int n,
>>>                                                  unsigned int s);
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
>>> +                                                  unsigned int b,
>>> +                                                  unsigned int n,
>>> +                                                  unsigned int s);
>>> +#endif
>>>    extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned
>>> int irq);
>>>    extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned
>>> int n);
>>>    extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned
>>> int n);
>>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
>>> index 2bbf4d99aa..f4b80cb05f 100644
>>> --- a/xen/arch/arm/vgic.c
>>> +++ b/xen/arch/arm/vgic.c
>>> @@ -27,9 +27,82 @@
>>>    bool vgic_is_valid_line(struct domain *d, unsigned int virq)
>>>    {
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    if ( virq >= ESPI_BASE_INTID &&
>>> +         virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
>>> +        return true;
>>> +#endif
>>> +
>>>        return virq < vgic_num_irqs(d);
>>>    }
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +/*
>>> + * Since eSPI indexes start from 4096 and numbers from 1024 to
>>> + * 4095 are forbidden, we need to check both lower and upper
>>> + * limits for ranks.
>>> + */
>>> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int
>>> rank)
>>> +{
>>> +    return rank >= EXT_RANK_MIN &&
>>> +           EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d);
>>> +}
>>> +
>>> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
>>> +                                                       unsigned int
>>> rank)
>>> +{
>>> +    return &v->domain-
>>>> arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)];
>>> +}
>>> +
>>> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned
>>> int virq)
>>> +{
>>> +    return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d),
>>> +                             d->arch.vgic.allocated_irqs);
>>> +}
>>> +
>>> +static void arch_move_espis(struct vcpu *v)
>>> +{
>>> +    const cpumask_t *cpu_mask = cpumask_of(v->processor);
>>> +    struct domain *d = v->domain;
>>> +    struct pending_irq *p;
>>> +    struct vcpu *v_target;
>>> +    unsigned int i;
>>> +
>>> +    for ( i = ESPI_BASE_INTID;
>>> +          i < EXT_RANK_IDX2NUM(d->arch.vgic.nr_espis); i++ )
>>> +    {
>>> +        v_target = vgic_get_target_vcpu(v, i);
>>> +        p = irq_to_pending(v_target, i);
>>> +
>>> +        if ( v_target == v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-
>>>> status) )
>>> +            irq_set_affinity(p->desc, cpu_mask);
>>> +    }
>>> +}
>>> +#else
>>> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int
>>> rank)
>>> +{
>>> +    return false;
>>> +}
>>> +
>>> +/*
>>> + * This function is stub and will not be called if CONFIG_GICV3_ESPI=n,
>>> + * because in this case, is_valid_espi_rank will always return false.
>>> + */
>>> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
>>> +                                                       unsigned int
>>> rank)
>>> +{
>>> +    ASSERT_UNREACHABLE();
>>> +    return NULL;
>>> +}
>>> +
>>> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned
>>> int virq)
>>> +{
>>> +    return false;
>>> +}
>>> +
>>> +static void arch_move_espis(struct vcpu *v) { }
>>> +#endif
>>> +
>>>    static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>>>                                                      unsigned int rank)
>>>    {
>>> @@ -37,6 +110,8 @@ static inline struct vgic_irq_rank
>>> *vgic_get_rank(struct vcpu *v,
>>>            return v->arch.vgic.private_irqs;
>>>        else if ( rank <= DOMAIN_NR_RANKS(v->domain) )
>>>            return &v->domain->arch.vgic.shared_irqs[rank - 1];
>>> +    else if ( is_valid_espi_rank(v->domain, rank) )
>>> +        return vgic_get_espi_rank(v, rank);
>>>        else
>>>            return NULL;
>>>    }
>>> @@ -117,6 +192,74 @@ int domain_vgic_register(struct domain *d,
>>> unsigned int *mmio_count)
>>>        return 0;
>>>    }
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +/*
>>> + * The function behavior is the same as for regular SPIs
>>> (vgic_rank_offset),
>>> + * but it operates with extended SPI ranks.
>>> + */
>>> +struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned
>>> int b,
>>> +                                           unsigned int n, unsigned
>>> int s)
>>> +{
>>> +    unsigned int rank = REG_RANK_NR(b, (n >> s));
>>> +
>>> +    return vgic_get_rank(v, rank + EXT_RANK_MIN);
>>> +}
>>
>> So the difference between vgic_rank_offset() and vgic_ext_rank_offset()
>> in using EXT_RANK_MIN in the latter. I am wondering, whether it makes
>> sense to reuse the existing vgic_rank_offset() by moving #ifdef into it?
>> Maybe it would be possible to optimize some code added in "[PATCH v4
>> 10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers".
>>
>> e.g. __vgic_v3_distr_common_mmio_read:
>>
>> Code for the following cases looks very similar to the regular
>> counterparts.
>> case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
>> case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
>> case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
>> case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
>> case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
>>
>> The difference is in the said helper and the base calculated as
>> "reg - GICD_XXX", where GICD_XXX is the start of the range for the eSPI-
>> based reg (e.g. GICD_IPRIORITYRnE) or regular SPI-based reg
>> (e.g.GICD_IPRIORITYR). The GICD_XXX could probably be chosen
>> based on the "reg" value itself, for example:
>>
>> rank = vgic_rank_offset(v, 8, reg >= GICD_IPRIORITYRnE ? reg -
>> GICD_IPRIORITYRnE : reg - GICD_IPRIORITYR, DABT_WORD);
>>
>> Please note, I am not requesting for any updates regarding to that, I am
>> just thinking out loud.
>>
> 
> First of all, I have to say that I really tried to reuse the existing
> code for regular SPIs whenever possible, but I could not come up with
> something better than introducing a new function for eSPI ranks in this
> case. This is due to several reasons:
> 1) Currently, all eSPI-specific offsets are placed under #ifdef to avoid
> or at least reduce the introduction of dead code or defines that will
> not be used. This was requested by our teammates who are engaged in
> MISRA fixes. Therefore, this is the first reason why eSPI-specific
> elements are placed under the appropriate configuration. Without
> CONFIG_GICV3_ESPI, we cannot use these offsets.
> 
> 2) The proposed solution:
>   > rank = vgic_rank_offset(v, 8, reg >= GICD_IPRIORITYRnE ? reg -
>   > GICD_IPRIORITYRnE : reg - GICD_IPRIORITYR, DABT_WORD);
> 
> will not work, unfortunately, because in this case, vgic_rank_offset
> will always return ranks for regular SPIs.
> 
> Long story short: we will encounter issues determining whether to use
> shared_irqs (for regular SPIs) or ext_shared_irqs (for eSPIs).
> 
> And here are the details about why this will not work:
> 
> In the case of receiving an offset for a regular SPI, e.g., 0x6200
> (GICD_IROUTER range [0x6100-0x7FD8]), we will get rank = 2 for regular SPIs:
> vgic_rank_offset(v, 64, 0x6200-0x6000, DABT_DOUBLE_WORD) ->
> DABT_DOUBLE_WORD = 3
> 
> Thus:
> rank = REG_RANK_NR(64, (0x200 >> 3) ->
> REG_RANK_NR will return in this case:
> 0x200 >> 3 >> 5 = 2
> 
> On the other hand, if we receive an offset for an eSPI, e.g., 0x8200
> (GICD_IROUTERnE range [0x8000-0x9FFC]), we will get the same rank = 2
> when using the proposed solution:
> vgic_rank_offset(v, 64, 0x8200-0x8000, DABT_DOUBLE_WORD) ->
> DABT_DOUBLE_WORD = 3
> 
> rank = REG_RANK_NR(64, (0x200 >> 3) ->
> REG_RANK_NR will return also:
> 0x200 >> 3 >> 5 = 2
> 
> As a result, in both cases, vgic_get_rank(v, 2) will return the rank for
> regular SPIs:
> 
> /* This condition will apply because rank will be less than 32 */
> else if ( rank <= DOMAIN_NR_RANKS(v->domain) )
>       return &v->domain->arch.vgic.shared_irqs[rank - 1];
> 
> Therefore, I decided to create a separate function to properly transform
> ranks into the correct range.
> 
> And, unfortunately, we cannot resolve the second issue with #ifdefs
> inside vgic_rank_offset, because this function will receive the same
> parameters for SPIs/eSPIs and we would not be able to determine whether
> we should return shared_irqs or ext_shared_irqs.

Thanks for such a detailed analysis. I was thinking that somehow we could:
  - reduce the number of #ifdef-s introduced by the current series as a 
whole
  - minimize the changes (optimize code) added in "[PATCH v4 10/12] 
xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers"

Maybe there is no valid concern at all, or I missed somethig. But, what 
worries me a bit is that said patch adds the emulation code for eSPI 
regs that are close for emulation code for regular SPI regs (e.g. please 
refer to VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN) - 
VRANGE64(GICD_IROUTER32, GICD_IROUTER1019) or 
VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN) - 
VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN)), besides the code 
duplication, we would have to keep both regular and entended handlers
in sync when doing possible updates/fixing the bugs.

While I completely agree with the dead code for eSPI-specific 
helpers/functions if we move them out of #ifdef CONFIG_GICV3_ESPI, what 
might be wrong if we at least drop #ifdef CONFIG_GICV3_ESPI for simple 
#define-s (non functional code), such as:

  #ifdef CONFIG_GICV3_ESPI
/* Additional registers for GICv3.1 */
#define GICD_IGROUPRnE               (0x1000)
#define GICD_IGROUPRnEN              (0x107C)
...

or

#ifdef CONFIG_GICV3_ESPI
#define ESPI_BASE_INTID 4096
#define ESPI_MAX_INTID  5119
#define NR_ESPI_IRQS    1024

#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
#endif

> 
>>
>>> +
>>> +static unsigned int vgic_num_spi_lines(struct domain *d)
>>> +{
>>> +    return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
>>> +}
>>> +
>>> +static int init_vgic_espi(struct domain *d)
>>> +{
>>> +    unsigned int i, idx;
>>> +
>>> +    if ( d->arch.vgic.nr_espis == 0 )
>>> +        return 0;
>>> +
>>> +    d->arch.vgic.ext_shared_irqs =
>>> +        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
>>> +    if ( d->arch.vgic.ext_shared_irqs == NULL )
>>> +        return -ENOMEM;
>>> +
>>> +    for ( i = d->arch.vgic.nr_spis, idx = 0;
>>> +          i < vgic_num_spi_lines(d); i++, idx++ )
>>> +        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i],
>>> +                              ESPI_IDX2INTID(idx));
>>> +
>>> +    for ( i = 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
>>> +        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
>>> +
>>> +    return 0;
>>> +}
>>> +
>>> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
>>> +{
>>> +    irq = ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
>>> +    return &d->arch.vgic.pending_irqs[irq];
>>> +}
>>> +#else
>>> +static unsigned int init_vgic_espi(struct domain *d
>>> +{
>>> +    return 0;
>>> +}
>>> +
>>> +static unsigned int vgic_num_spi_lines(struct domain *d)
>>> +{
>>> +    return d->arch.vgic.nr_spis;
>>> +}
>>> +
>>> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
>>> +{
>>> +    return NULL;
>>> +}
>>> +#endif
>>> +
>>> +static unsigned int vgic_num_alloc_irqs(struct domain *d)
>>> +{
>>> +    return vgic_num_spi_lines(d) + NR_LOCAL_IRQS;
>>> +}
>>> +
>>>    int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>>>    {
>>>        int i;
>>> @@ -131,6 +274,38 @@ int domain_vgic_init(struct domain *d, unsigned
>>> int nr_spis)
>>>         */
>>>        nr_spis = ROUNDUP(nr_spis, 32);
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    /*
>>> +     * During domain creation, the dom0less DomUs code or toolstack
>>> specifies
>>> +     * the maximum INTID, which is defined in the domain config
>>> subtracted by
>>> +     * 32 to cover the local IRQs (please see the comment to
>>> VGIC_DEF_NR_SPIS).
>>> +     * To compute the actual number of eSPI that will be usable for,
>>> +     * add back 32.
>>> +     */
>>> +    if ( nr_spis + 32 > ESPI_IDX2INTID(NR_ESPI_IRQS) )
>>> +        return -EINVAL;
>>> +
>>> +    if ( nr_spis + 32 >= ESPI_BASE_INTID )
>>> +    {
>>> +        d->arch.vgic.nr_espis = min(nr_spis - ESPI_BASE_INTID + 32,
>>> 1024U);
>>> +        /* Verify if GIC HW can handle provided INTID */
>>> +        if ( d->arch.vgic.nr_espis > gic_number_espis() )
>>> +            return -EINVAL;
>>> +        /*
>>> +         * Set the maximum available number for regular
>>> +         * SPI to pass the next check
>>> +         */
>>> +        nr_spis = VGIC_DEF_NR_SPIS;
>>> +        d->arch.vgic.has_espi = true;
>>> +    }
>>> +    else
>>> +    {
>>> +        /* Domain will use the regular SPI range */
>>> +        d->arch.vgic.nr_espis = 0;
>>> +        d->arch.vgic.has_espi = false;
>>> +    }
>>> +#endif
>>> +
>>>        /* Limit the number of virtual SPIs supported to (1020 - 32) =
>>> 988  */
>>>        if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
>>>            return -EINVAL;
>>> @@ -145,7 +320,7 @@ int domain_vgic_init(struct domain *d, unsigned
>>> int nr_spis)
>>>            return -ENOMEM;
>>>        d->arch.vgic.pending_irqs =
>>> -        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
>>> +        xzalloc_array(struct pending_irq, vgic_num_spi_lines(d));
>>>        if ( d->arch.vgic.pending_irqs == NULL )
>>>            return -ENOMEM;
>>> @@ -156,12 +331,16 @@ int domain_vgic_init(struct domain *d, unsigned
>>> int nr_spis)
>>>        for ( i = 0; i < DOMAIN_NR_RANKS(d); i++ )
>>>            vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
>>> +    ret = init_vgic_espi(d);
>>> +    if ( ret )
>>> +        return ret;
>>> +
>>>        ret = d->arch.vgic.handler->domain_init(d);
>>>        if ( ret )
>>>            return ret;
>>>        d->arch.vgic.allocated_irqs =
>>> -        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
>>> +        xzalloc_array(unsigned long,
>>> BITS_TO_LONGS(vgic_num_alloc_irqs(d)));
>>>        if ( !d->arch.vgic.allocated_irqs )
>>>            return -ENOMEM;
>>> @@ -195,9 +374,27 @@ void domain_vgic_free(struct domain *d)
>>>            }
>>>        }
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    for ( i = 0; i < d->arch.vgic.nr_espis; i++ )
>>> +    {
>>> +        struct pending_irq *p = spi_to_pending(d, ESPI_IDX2INTID(i));
>>> +
>>> +        if ( p->desc )
>>> +        {
>>> +            ret = release_guest_irq(d, p->irq);
>>> +            if ( ret )
>>> +                dprintk(XENLOG_G_WARNING, "d%u: Failed to release
>>> virq %u ret = %d\n",
>>
>>
>> NIT: you can use %pd for printing domain with its ID
>>
>>
> 
> I will fix it in V5.
> 
>>> +                        d->domain_id, p->irq, ret);
>>> +        }
>>> +    }
>>> +#endif
>>> +
>>>        if ( d->arch.vgic.handler )
>>>            d->arch.vgic.handler->domain_free(d);
>>>        xfree(d->arch.vgic.shared_irqs);
>>> +#ifdef CONFIG_GICV3_ESPI
>>> +    xfree(d->arch.vgic.ext_shared_irqs);
>>> +#endif
>>>        xfree(d->arch.vgic.pending_irqs);
>>>        xfree(d->arch.vgic.allocated_irqs);
>>>    }
>>> @@ -331,6 +528,8 @@ void arch_move_irqs(struct vcpu *v)
>>>            if ( v_target == v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-
>>>> status) )
>>>                irq_set_affinity(p->desc, cpu_mask);
>>>        }
>>> +
>>> +    arch_move_espis(v);
>>>    }
>>>    void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
>>> @@ -538,6 +737,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v,
>>> unsigned int irq)
>>>            n = &v->arch.vgic.pending_irqs[irq];
>>>        else if ( is_lpi(irq) )
>>>            n = v->domain->arch.vgic.handler->lpi_to_pending(v->domain,
>>> irq);
>>> +    else if ( is_espi(irq) )
>>> +        n = espi_to_pending(v->domain, irq);
>>>        else
>>>            n = &v->domain->arch.vgic.pending_irqs[irq - 32];
>>>        return n;
>>> @@ -547,6 +748,9 @@ struct pending_irq *spi_to_pending(struct domain
>>> *d, unsigned int irq)
>>>    {
>>>        ASSERT(irq >= NR_LOCAL_IRQS);
>>> +    if ( is_espi(irq) )
>>> +        return espi_to_pending(d, irq);
>>> +
>>>        return &d->arch.vgic.pending_irqs[irq - 32];
>>>    }
>>> @@ -668,6 +872,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned
>>> int virq)
>>>        if ( !vgic_is_valid_line(d, virq) )
>>>            return false;
>>> +    if ( is_espi(virq) )
>>> +        return vgic_reserve_espi_virq(d, virq);
>>> +
>>>        return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
>>>    }
>>> @@ -685,7 +892,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
>>>        else
>>>        {
>>>            first = 32;
>>> -        end = vgic_num_irqs(d);
>>> +        end = vgic_num_alloc_irqs(d);
>>>        }
>>>        /*
>>
> 
> Best regards,
> Leonid



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RESEND=20PATCH=20v2=200/3]=20Update=20to=20SMBIOS=202.6?=
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First patch clarifies the Xen guest handle definition as being a big
endian UUID. The second does update to SMBIOS 2.6, writing a proper
UUID in the table.

Teddy Astie (3):
  xen: Define xen_domain_handle_t encoding and formatting
  hvmloader: Update to SMBIOS 2.6
  CHANGELOG.md: Add SMBIOS 2.6 update statement

 CHANGELOG.md                            |  2 +
 tools/firmware/hvmloader/smbios.c       | 50 ++++++++++++++++++++-----
 tools/firmware/hvmloader/smbios_types.h |  9 +++++
 xen/include/public/xen.h                |  7 ++++
 4 files changed, 59 insertions(+), 9 deletions(-)

-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RESEND=20PATCH=20v2=201/3]=20xen:=20Define=20xen=5Fdomain=5Fhandle=5Ft=20encoding=20and=20formatting?=
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xen_domain_handle_t is defined as a opaque 16-bytes blob, but is
commonly used by toolstack and guest as a big-endian encoded and
formatted UUID (alike RFC 9562).

Clarify the definition of the type to ensure the guest and toolstack
interprets this value correctly in a way consistent with existing users
(at least with XAPI, xl, libvirt, hvmloader and Linux).

Fixes: 30ce2a9295a5 ("Store an opaque handle (tools uuid) in the domain structure")
Suggested-by: Andrew Cooper 
Signed-off-by: Teddy Astie 
---
v2:
 - introduced
---
 CHANGELOG.md             | 1 +
 xen/include/public/xen.h | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index cd34ea87b8..8c4435c181 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -11,6 +11,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - For x86, GCC 5.1 and Binutils 2.25, or Clang/LLVM 11
    - For ARM32 and ARM64, GCC 5.1 and Binutils 2.25
  - Linux based device model stubdomains are now fully supported.
+ - Clarify guest UUIDs as being big-endian encoded.
 
  - On x86:
    - Restrict the cache flushing done as a result of guest physical memory map
diff --git a/xen/include/public/xen.h b/xen/include/public/xen.h
index 82b9c05a76..a219ef870f 100644
--- a/xen/include/public/xen.h
+++ b/xen/include/public/xen.h
@@ -973,6 +973,13 @@ typedef struct dom0_vga_console_info {
 #define xen_vga_console_info dom0_vga_console_info
 #define xen_vga_console_info_t dom0_vga_console_info_t
 
+/*
+ * The domain handle is chosen by the toolstack, and intended to hold a UUID
+ * conforming to RFC 9562 (i.e. big endian).
+ *
+ * Certain cases (e.g. SMBios) transform it to a Microsoft GUID (little
+ * endian) for presentation to the guest.
+ */
 typedef uint8_t xen_domain_handle_t[16];
 
 __DEFINE_XEN_GUEST_HANDLE(uint8,  uint8_t);
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RESEND=20PATCH=20v2=202/3]=20hvmloader:=20Update=20to=20SMBIOS=202.6?=
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Currently, hvmloader uses SMBIOS 2.4, however, when using OVMF, the
SMBIOS is patched to 2.8, which has clarified the UUID format (as GUID).

In Linux, if the SMBIOS version is >= 2.6, the GUID format is used, else
(undefined as per SMBIOS spec), big endian is used (used by Xen). Therefore,
you have a endian mismatch causing the UUIDs to mismatch in the guest.

$ cat /sys/hypervisor/uuid
e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7
$ cat /sys/devices/virtual/dmi/id/product_uuid
3fe665e8-303d-0b4f-83e0-8fdfc1e30eb7
$ cat /sys/devices/virtual/dmi/id/product_serial
e865e63f-3d30-4f0b-83e0-8fdfc1e30eb7

This patch updates the SMBIOS version from 2.4 to 2.6 and does the appropriate
modifications of the table. This effectively fix this endianness mismatch with
OVMF; while the UUID displayed by Linux is still the same for SeaBIOS.

Fixes: c683914ef913 ("Add code to generate SMBIOS tables to hvmloader.")
(SMBIOS versions before 2.6 has a ill-defined UUID definition)
Signed-off-by: Teddy Astie 
---
v2:
 - rebase onto staging
 - introduce missing SMBIOS 2.5-2.6 fields
 - check for new SMBIOS 2.6 table lengths
 - update UUID conversion comment
 - add Fixes: note
 ---
 tools/firmware/hvmloader/smbios.c       | 50 ++++++++++++++++++++-----
 tools/firmware/hvmloader/smbios_types.h |  9 +++++
 2 files changed, 50 insertions(+), 9 deletions(-)

diff --git a/tools/firmware/hvmloader/smbios.c b/tools/firmware/hvmloader/smbios.c
index 76c7090d16..e445475d78 100644
--- a/tools/firmware/hvmloader/smbios.c
+++ b/tools/firmware/hvmloader/smbios.c
@@ -396,7 +396,7 @@ smbios_entry_point_init(void *start,
     memcpy(ep->anchor_string, "_SM_", 4);
     ep->length = 0x1f;
     ep->smbios_major_version = 2;
-    ep->smbios_minor_version = 4;
+    ep->smbios_minor_version = 6;
     ep->max_structure_size = max_structure_size;
     ep->entry_point_revision = 0;
     memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
@@ -505,7 +505,22 @@ smbios_type_1_init(void *start, const char *xen_version,
     p->version_str = 3;
     p->serial_number_str = 4;
 
-    memcpy(p->uuid, uuid, 16);
+    /*
+     * Xen toolstack uses big endian UUIDs, however GUIDs (which requirement
+     * is clarified by SMBIOS >= 2.6) has the first 3 components appearing as
+     * being little endian and the rest as still being big endian.
+     */
+    /* First component */
+    for ( unsigned int i = 0; i < 4; i++ )
+        p->uuid[i] = uuid[4 - i - 1];
+    /* Second component */
+    p->uuid[4] = uuid[5];
+    p->uuid[5] = uuid[4];
+    /* Third component */
+    p->uuid[6] = uuid[7];
+    p->uuid[7] = uuid[6];
+    /* Rest */
+    memcpy(p->uuid + 8, uuid + 8, 8);
 
     p->wake_up_type = 0x06; /* power switch */
     p->sku_str = 0;
@@ -705,8 +720,8 @@ smbios_type_4_init(
     struct smbios_type_4 *p = start;
     uint32_t eax, ebx, ecx, edx;
 
-    /* Specification says Type 4 table has length of 23h for v2.3+. */
-    BUILD_BUG_ON(sizeof(*p) != 35);
+    /* Specification says Type 4 table has length of 2Ah for v2.6. */
+    BUILD_BUG_ON(sizeof(*p) != 42);
 
     memset(p, 0, sizeof(*p));
 
@@ -716,7 +731,7 @@ smbios_type_4_init(
 
     p->socket_designation_str = 1;
     p->processor_type = 0x03; /* CPU */
-    p->processor_family = 0x01; /* other */
+    p->processor_family = p->processor_family_2 = 0x01; /* other */
     p->manufacturer_str = 2;
 
     cpuid(1, &eax, &ebx, &ecx, &edx);
@@ -736,6 +751,22 @@ smbios_type_4_init(
     p->l2_cache_handle = 0xffff; /* No cache information structure provided. */
     p->l3_cache_handle = 0xffff; /* No cache information structure provided. */
 
+    /*
+     * We have a smbios type 4 table per vCPU (which is per socket),
+     * which means here that we have 1 socket per vCPU.
+     */
+    p->core_count = p->core_enabled = p->thread_count = 1;
+
+    /*
+     * We set 64-bits, execute protection and enhanced virtualization.
+     * We don't set Multi-Core (bit 3) because this individual processor
+     * (as being a single vCPU) is only having one core.
+     *
+     * SMBIOS specification says that these bits don't state anything
+     * regarding the actual availability of such features.
+     */
+    p->processor_characteristics = 0x64;
+
     start += sizeof(*p);
 
     strncpy(buf, "CPU ", sizeof(buf));
@@ -780,8 +811,8 @@ smbios_type_8_init(void *start)
 static void *
 smbios_type_9_init(void *start)
 {
-    /* Specification says Type 9 table has length of 0Dh for v2.1-2.5. */
-    BUILD_BUG_ON(sizeof(struct smbios_type_9) != 13);
+    /* Specification says Type 9 table has length of 11h for v2.6+. */
+    BUILD_BUG_ON(sizeof(struct smbios_type_9) != 17);
 
     /* Only present when passed in. */
     return smbios_pt_copy(start, 9, SMBIOS_HANDLE_TYPE9,
@@ -870,8 +901,8 @@ smbios_type_17_init(void *start, uint32_t memory_size_mb, int instance)
     char buf[16];
     struct smbios_type_17 *p = start;
 
-    /* Specification says Type 17 table has length of 1Bh for v2.3-2.6. */
-    BUILD_BUG_ON(sizeof(*p) != 27);
+    /* Specification says Type 17 table has length of 1Ch for v2.6. */
+    BUILD_BUG_ON(sizeof(*p) != 28);
 
     memset(p, 0, sizeof(*p));
 
@@ -890,6 +921,7 @@ smbios_type_17_init(void *start, uint32_t memory_size_mb, int instance)
     p->bank_locator_str = 0;
     p->memory_type = 0x07; /* RAM */
     p->type_detail = 0;
+    p->attributes = 0;
 
     start += sizeof(*p);
     strcpy(start, "DIMM ");
diff --git a/tools/firmware/hvmloader/smbios_types.h b/tools/firmware/hvmloader/smbios_types.h
index c04b435d31..860617d86a 100644
--- a/tools/firmware/hvmloader/smbios_types.h
+++ b/tools/firmware/hvmloader/smbios_types.h
@@ -147,6 +147,11 @@ struct smbios_type_4 {
     uint8_t serial_number_str;
     uint8_t asset_tag_str;
     uint8_t part_number_str;
+    uint8_t core_count;
+    uint8_t core_enabled;
+    uint8_t thread_count;
+    uint16_t processor_characteristics;
+    uint16_t processor_family_2;
 } __attribute__ ((packed));
 
 /* SMBIOS type 7 - Cache Information */
@@ -185,6 +190,9 @@ struct smbios_type_9 {
     uint16_t slot_id;
     uint8_t slot_characteristics_1;
     uint8_t slot_characteristics_2;
+    uint16_t sgn_base;
+    uint8_t bus_number_base;
+    uint8_t devfn_base;
 } __attribute__ ((packed));
 
 /* SMBIOS type 11 - OEM Strings */
@@ -227,6 +235,7 @@ struct smbios_type_17 {
     uint8_t serial_number_str;
     uint8_t asset_tag_str;
     uint8_t part_number_str;
+    uint8_t attributes;
 } __attribute__ ((packed));
 
 /* SMBIOS type 19 - Memory Array Mapped Address */
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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From: "Teddy Astie" 
Subject: =?utf-8?Q?[RESEND=20PATCH=20v2=203/3]=20CHANGELOG.md:=20Add=20SMBIOS=202.6=20update=20statement?=
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Signed-off-by: Teddy Astie 
---
v2:
 - introduced
---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8c4435c181..80a8273d7e 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -34,6 +34,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
    - Support in hvmloader for new SMBIOS tables: 7 (Cache Info), 8 (Port
      Connector), 9 (System Slots), 26 (Voltage Probe), 27 (Cooling Device),
      and 28 (Temperature Probe).
+   - Updated SMBIOS version to 2.6.
 
  - On Arm:
     - Ability to enable stack protector
-- 
2.50.1



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech



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Date: Fri, 29 Aug 2025 12:07:26 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jiqian Chen 
Cc: xen-devel@lists.xenproject.org, Huang Rui 
Subject: Re: [PATCH v11 1/5] vpci: Use cleanup to free capability resource
 during deassign
Message-ID: 
References: <20250808080337.28609-1-Jiqian.Chen@amd.com>
 <20250808080337.28609-2-Jiqian.Chen@amd.com>
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On Fri, Aug 08, 2025 at 04:03:33PM +0800, Jiqian Chen wrote:
> As cleanup hook of all supported capabilities will be implemented in
> follow-on changes, so to pre-call hook in vpci_deassign_device(), and
> the capability specific clean open-code in there will be removed by
> follow-on corresponding capability changes.
> 
> Since vpci_deassign_device() and vpci_init_capabilities() require
> different cleanup actions, add a boolean parameter to cleanup hook
> to distinguish them.
> 
> Signed-off-by: Jiqian Chen 

I think it's missing:

Requested-by: Jan Beulich 

With the newline below added:

Reviewed-by: Roger Pau Monné 

I can do it on commit.

Thanks, Roger.


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Date: Fri, 29 Aug 2025 12:09:28 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jiqian Chen 
Cc: xen-devel@lists.xenproject.org, Huang Rui ,
	Anthony PERARD 
Subject: Re: [PATCH v11 2/5] vpci: Refactor vpci_remove_register to remove
 matched registers
Message-ID: 
References: <20250808080337.28609-1-Jiqian.Chen@amd.com>
 <20250808080337.28609-3-Jiqian.Chen@amd.com>
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On Fri, Aug 08, 2025 at 04:03:34PM +0800, Jiqian Chen wrote:
> vpci_remove_register() only supports removing a register in a time,
> but the follow-on changes need to remove all registers within a range.
> So, refactor it to support removing all registers in a given region.
> 
> And it is no issue to remove a non exist register, so remove the
> __must_check prefix.
> 
> Note: two test cases don't math the new logic of
> vpci_remove_registers(), then modify them.
> 
> Signed-off-by: Jiqian Chen 

Reviewed-by: Roger Pau Monné 

Thanks, Roger.


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On 29.08.2025 10:56, Roger Pau Monné wrote:
> On Fri, Aug 29, 2025 at 10:10:59AM +0200, Jan Beulich wrote:
>> On 29.08.2025 09:51, Roger Pau Monne wrote:
>>> There's no need for PDX compression given the memory map provided by Xen
>>> to guests is contiguous, turn off the feature by default in the PV shim
>>> defconfig.
>>>
>>> Reported-by: Jan Beulich 
>>> Fixes: c5c45bcbd6a1 ('pdx: introduce a new compression algorithm based on region offsets')
>>> Signed-off-by: Roger Pau Monné 
>>
>> Acked-by: Jan Beulich 
>>
>> Not sure if a Fixes: tag is really appropriate here. The shim is working as
>> is, just carrying code which won't ever be used.
> 
> I was borderline also, but I felt it was important to notice that the
> change here should ideally had been part of that commit.  Do you have
> a recommendation of any other tag I could use for that purpose?

In rare cases I think I've used Amends: (not formally mentioned anywhere,
of course).

Jan


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Date: Fri, 29 Aug 2025 12:29:59 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jiqian Chen 
Cc: xen-devel@lists.xenproject.org, Huang Rui 
Subject: Re: [PATCH v11 4/5] vpci/msi: Implement cleanup function for MSI
Message-ID: 
References: <20250808080337.28609-1-Jiqian.Chen@amd.com>
 <20250808080337.28609-5-Jiqian.Chen@amd.com>
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On Fri, Aug 08, 2025 at 04:03:36PM +0800, Jiqian Chen wrote:
> When MSI initialization fails, vPCI hides the capability, but
> removing handlers and datas won't be performed until the device is
> deassigned. So, implement MSI cleanup hook that will be called to
> cleanup MSI related handlers and free it's associated data when
> initialization fails.
> 
> Since cleanup function of MSI is implemented, delete the open-code
> in vpci_deassign_device().
> 
> Signed-off-by: Jiqian Chen 
> ---
> cc: "Roger Pau Monné" 
> ---
> v10->v11 changes:
> * Add hide paratemer to cleanup_msi().
> * Check hide, if false return directly instead of letting ctrl RO.
> * Delete xfree(pdev->vpci->msi); in vpci_deassign_device().
> * Remove Roger's Reviewed-by since patch change.
> 
> v9->v10 changes:
> No.
> 
> v8->v9 changes:
> * Add Roger's Reviewed-by.
> 
> v7->v8 changes:
> * Add a comment to describe why "-2" in cleanup_msi().
> * Given the code in vpci_remove_registers() an error in the removal of
>   registers would likely imply memory corruption, at which point it's
>   best to fully disable the device. So, Rollback the last two modifications of v7.
> 
> v6->v7 changes:
> * Change the pointer parameter of cleanup_msi() to be const.
> * When vpci_remove_registers() in cleanup_msi() fails, not to return
>   directly, instead try to free msi and re-add ctrl handler.
> * Pass pdev->vpci into vpci_add_register() instead of pdev->vpci->msi in
>   init_msi() since we need that every handler realize that msi is NULL
>   when msi is free but handlers are still in there.
> 
> v5->v6 changes:
> No.
> 
> v4->v5 changes:
> * Change definition "static void cleanup_msi" to "static int cf_check cleanup_msi"
>   since cleanup hook is changed to be int.
> * Add a read-only register for MSI Control Register in the end of cleanup_msi.
> 
> v3->v4 changes:
> * Change function name from fini_msi() to cleanup_msi().
> * Remove unnecessary comment.
> * Change to use XFREE to free vpci->msi.
> 
> v2->v3 changes:
> * Remove all fail path, and use fini_msi() hook instead.
> * Change the method to calculating the size of msi registers.
> 
> v1->v2 changes:
> * Added a new function fini_msi to free all MSI resources instead of using an array
>   to record registered registers.
> 
> Best regards,
> Jiqian Chen.
> ---
>  xen/drivers/vpci/msi.c  | 49 ++++++++++++++++++++++++++++++++++++++++-
>  xen/drivers/vpci/vpci.c |  1 -
>  2 files changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c
> index c3eba4e14870..6ab45b9ba655 100644
> --- a/xen/drivers/vpci/msi.c
> +++ b/xen/drivers/vpci/msi.c
> @@ -193,6 +193,53 @@ static void cf_check mask_write(
>      msi->mask = val;
>  }
>  
> +static int cf_check cleanup_msi(const struct pci_dev *pdev, bool hide)
> +{
> +    int rc;
> +    unsigned int end;
> +    struct vpci *vpci = pdev->vpci;
> +    const unsigned int msi_pos = pdev->msi_pos;
> +    const unsigned int ctrl = msi_control_reg(msi_pos);
> +
> +    if ( !msi_pos || !vpci->msi )
> +        return 0;
> +
> +    if ( vpci->msi->masking )
> +        end = msi_pending_bits_reg(msi_pos, vpci->msi->address64);
> +    else
> +        /*
> +         * "-2" here is to cut the reserved 2 bytes of Message Data when
> +         * there is no masking support.
> +         */
> +        end = msi_mask_bits_reg(msi_pos, vpci->msi->address64) - 2;
> +
> +    rc = vpci_remove_registers(vpci, ctrl, end - ctrl);
> +    if ( rc )
> +    {
> +        printk(XENLOG_ERR "%pd %pp: fail to remove MSI handlers rc=%d\n",
> +               pdev->domain, &pdev->sbdf, rc);
> +        ASSERT_UNREACHABLE();
> +        return rc;
> +    }
> +
> +    XFREE(vpci->msi);
> +
> +    if ( !hide )
> +        return 0;

Kind of the same comment as in the previous patch, for the non-hide
case there's likely no reason to perform the removal of the registers,
as the caller will take care of that.  The function could be
short-circuited earlier as:

if ( !hide )
{
    XFREE(vpci->msi);
    return 0;
}

Thanks, Roger.


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Date: Fri, 29 Aug 2025 12:22:13 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jiqian Chen 
Cc: xen-devel@lists.xenproject.org, Huang Rui 
Subject: Re: [PATCH v11 3/5] vpci/rebar: Implement cleanup function for Rebar
Message-ID: 
References: <20250808080337.28609-1-Jiqian.Chen@amd.com>
 <20250808080337.28609-4-Jiqian.Chen@amd.com>
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In-Reply-To: <20250808080337.28609-4-Jiqian.Chen@amd.com>

On Fri, Aug 08, 2025 at 04:03:35PM +0800, Jiqian Chen wrote:
> When Rebar initialization fails, vPCI hides the capability, but
> removing handlers and datas won't be performed until the device is
> deassigned. So, implement Rebar cleanup hook that will be called to
> cleanup Rebar related handlers and free it's associated data when
> initialization fails.
> 
> Signed-off-by: Jiqian Chen 
> ---
> cc: "Roger Pau Monné" 
> ---
> v10->v11 changes:
> * Add ASSERT_UNREACHABLE() when vpci_remove_registers() fails
> * When hide == true, add handlers to let Rebar ctrl be RO.
> * Remove Roger's Reviewed-by since patch change.
> 
> v9->v10 changes:
> v8->v9 changes:
> No.
> 
> v7->v8 changes:
> * Add Roger's Reviewed-by.
> 
> v6->v7 changes:
> * Change the pointer parameter of cleanup_rebar() to be const.
> * Print error when vpci_remove_registers() fail in cleanup_rebar().
> 
> v5->v6 changes:
> No.
> 
> v4->v5 changes:
> * Change definition "static void cleanup_rebar" to "static int cf_check cleanup_rebar" since cleanup hook is changed to be int.
> 
> v3->v4 changes:
> * Change function name from fini_rebar() to cleanup_rebar().
> * Change the error number to be E2BIG and ENXIO in init_rebar().
> 
> v2->v3 changes:
> * Use fini_rebar() to remove all register instead of in the failure path of init_rebar();
> 
> v1->v2 changes:
> * Called vpci_remove_registers() to remove all possible registered registers instead of using a array to record all registered register.
> 
> Best regards,
> Jiqian Chen.
> ---
>  xen/drivers/vpci/rebar.c | 66 +++++++++++++++++++++++++++++++++-------
>  1 file changed, 55 insertions(+), 11 deletions(-)
> 
> diff --git a/xen/drivers/vpci/rebar.c b/xen/drivers/vpci/rebar.c
> index 3c18792d9bcd..91d5369d75e2 100644
> --- a/xen/drivers/vpci/rebar.c
> +++ b/xen/drivers/vpci/rebar.c
> @@ -49,6 +49,57 @@ static void cf_check rebar_ctrl_write(const struct pci_dev *pdev,
>      bar->guest_addr = bar->addr;
>  }
>  
> +static int cf_check cleanup_rebar(const struct pci_dev *pdev, bool hide)
> +{
> +    int rc;
> +    uint32_t ctrl;
> +    unsigned int nbars;
> +    unsigned int rebar_offset = pci_find_ext_capability(pdev->sbdf,
> +                                                        PCI_EXT_CAP_ID_REBAR);
> +
> +    if ( !rebar_offset || !is_hardware_domain(pdev->domain) )
> +    {
> +        ASSERT_UNREACHABLE();
> +        return 0;
> +    }
> +
> +    ctrl = pci_conf_read32(pdev->sbdf, rebar_offset + PCI_REBAR_CTRL(0));
> +    nbars = MASK_EXTR(ctrl, PCI_REBAR_CTRL_NBAR_MASK);
> +
> +    rc = vpci_remove_registers(pdev->vpci, rebar_offset + PCI_REBAR_CAP(0),
> +                               PCI_REBAR_CTRL(nbars - 1));
> +    if ( rc )
> +    {
> +        printk(XENLOG_ERR "%pd %pp: fail to remove Rebar handlers rc=%d\n",
> +               pdev->domain, &pdev->sbdf, rc);
> +        ASSERT_UNREACHABLE();
> +        return rc;
> +    }
> +
> +    if ( !hide )
> +        return 0;

Now that the handler can differentiate between calls to hide the
capability versus calls from device deassign, do we need to call
vpci_remove_registers() for the non-hiding case?

The non-hiding case is only used from vpci_deassign_device(), and just
after having called all the cleanup hooks that function purges any
remaining registered handlers.  It would be OK to do something like:

static int cf_check cleanup_rebar(const struct pci_dev *pdev, bool hide)
{
    int rc;
    uint32_t ctrl;
    unsigned int nbars;
    unsigned int rebar_offset = pci_find_ext_capability(pdev->sbdf,
                                                        PCI_EXT_CAP_ID_REBAR);

    if ( !rebar_offset || !is_hardware_domain(pdev->domain) )
    {
        ASSERT_UNREACHABLE();
        return 0;
    }

    if ( !hide )
        return 0;

    ... remove handler + mask register ...

Thoughts?

> +
> +    /*
> +     * The driver may not traverse the capability list and think device
> +     * supports Rebar by default. So here let the control register of Rebar
> +     * be Read-Only is to ensure Rebar disabled.
> +     */
> +    for ( unsigned int i = 0; i < nbars; i++ )
> +    {
> +        rc = vpci_add_register(pdev->vpci, vpci_hw_read32, NULL,
> +                               rebar_offset + PCI_REBAR_CTRL(i), 4, NULL);
> +        if ( rc )
> +        {
> +            printk(XENLOG_ERR
> +                   "%pd %pp: fail to add Rebar ctrl handler rc=%d\n",
> +                   pdev->domain, &pdev->sbdf, rc);
> +            return rc;
> +        }
> +    }
> +
> +    return 0;
> +}
> +
>  static int cf_check init_rebar(struct pci_dev *pdev)
>  {
>      uint32_t ctrl;
> @@ -80,7 +131,7 @@ static int cf_check init_rebar(struct pci_dev *pdev)
>          {
>              printk(XENLOG_ERR "%pd %pp: too big BAR number %u in REBAR_CTRL\n",
>                     pdev->domain, &pdev->sbdf, index);
> -            continue;
> +            return -E2BIG;
>          }
>  
>          bar = &pdev->vpci->header.bars[index];
> @@ -88,7 +139,7 @@ static int cf_check init_rebar(struct pci_dev *pdev)
>          {
>              printk(XENLOG_ERR "%pd %pp: BAR%u is not in memory space\n",
>                     pdev->domain, &pdev->sbdf, index);
> -            continue;
> +            return -ENXIO;

I'm unsure we want to return an error here and in the check above,
given this capability is dom0 only, we might want to just skip the BAR
and continue, aiming for the other resizable BARs to be functional?

Thanks, Roger.


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Date: Fri, 29 Aug 2025 12:31:40 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: Andrew Cooper ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH] x86/pvshim: disable PDX compression in PV shim defconfig
Message-ID: 
References: <20250829075154.48787-1-roger.pau@citrix.com>
 
 
 <77299b94-43cd-4d55-891a-8e1209b4b669@suse.com>
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On Fri, Aug 29, 2025 at 12:21:26PM +0200, Jan Beulich wrote:
> On 29.08.2025 10:56, Roger Pau Monné wrote:
> > On Fri, Aug 29, 2025 at 10:10:59AM +0200, Jan Beulich wrote:
> >> On 29.08.2025 09:51, Roger Pau Monne wrote:
> >>> There's no need for PDX compression given the memory map provided by Xen
> >>> to guests is contiguous, turn off the feature by default in the PV shim
> >>> defconfig.
> >>>
> >>> Reported-by: Jan Beulich 
> >>> Fixes: c5c45bcbd6a1 ('pdx: introduce a new compression algorithm based on region offsets')
> >>> Signed-off-by: Roger Pau Monné 
> >>
> >> Acked-by: Jan Beulich 
> >>
> >> Not sure if a Fixes: tag is really appropriate here. The shim is working as
> >> is, just carrying code which won't ever be used.
> > 
> > I was borderline also, but I felt it was important to notice that the
> > change here should ideally had been part of that commit.  Do you have
> > a recommendation of any other tag I could use for that purpose?
> 
> In rare cases I think I've used Amends: (not formally mentioned anywhere,
> of course).

Oh, how would you feel about adding it formally to
sending-patches.pandoc?

It's a rare tag, but I would find it useful in contexts like the
above.

Thanks, Roger.


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Date: Fri, 29 Aug 2025 12:41:48 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jiqian Chen 
Cc: xen-devel@lists.xenproject.org, Huang Rui 
Subject: Re: [PATCH v11 4/5] vpci/msi: Implement cleanup function for MSI
Message-ID: 
References: <20250808080337.28609-1-Jiqian.Chen@amd.com>
 <20250808080337.28609-5-Jiqian.Chen@amd.com>
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On Fri, Aug 08, 2025 at 04:03:36PM +0800, Jiqian Chen wrote:
> When MSI initialization fails, vPCI hides the capability, but
> removing handlers and datas won't be performed until the device is
> deassigned. So, implement MSI cleanup hook that will be called to
> cleanup MSI related handlers and free it's associated data when
> initialization fails.
> 
> Since cleanup function of MSI is implemented, delete the open-code
> in vpci_deassign_device().
> 
> Signed-off-by: Jiqian Chen 
> ---
> cc: "Roger Pau Monné" 
> ---
> v10->v11 changes:
> * Add hide paratemer to cleanup_msi().
> * Check hide, if false return directly instead of letting ctrl RO.
> * Delete xfree(pdev->vpci->msi); in vpci_deassign_device().
> * Remove Roger's Reviewed-by since patch change.
> 
> v9->v10 changes:
> No.
> 
> v8->v9 changes:
> * Add Roger's Reviewed-by.
> 
> v7->v8 changes:
> * Add a comment to describe why "-2" in cleanup_msi().
> * Given the code in vpci_remove_registers() an error in the removal of
>   registers would likely imply memory corruption, at which point it's
>   best to fully disable the device. So, Rollback the last two modifications of v7.
> 
> v6->v7 changes:
> * Change the pointer parameter of cleanup_msi() to be const.
> * When vpci_remove_registers() in cleanup_msi() fails, not to return
>   directly, instead try to free msi and re-add ctrl handler.
> * Pass pdev->vpci into vpci_add_register() instead of pdev->vpci->msi in
>   init_msi() since we need that every handler realize that msi is NULL
>   when msi is free but handlers are still in there.
> 
> v5->v6 changes:
> No.
> 
> v4->v5 changes:
> * Change definition "static void cleanup_msi" to "static int cf_check cleanup_msi"
>   since cleanup hook is changed to be int.
> * Add a read-only register for MSI Control Register in the end of cleanup_msi.
> 
> v3->v4 changes:
> * Change function name from fini_msi() to cleanup_msi().
> * Remove unnecessary comment.
> * Change to use XFREE to free vpci->msi.
> 
> v2->v3 changes:
> * Remove all fail path, and use fini_msi() hook instead.
> * Change the method to calculating the size of msi registers.
> 
> v1->v2 changes:
> * Added a new function fini_msi to free all MSI resources instead of using an array
>   to record registered registers.
> 
> Best regards,
> Jiqian Chen.
> ---
>  xen/drivers/vpci/msi.c  | 49 ++++++++++++++++++++++++++++++++++++++++-
>  xen/drivers/vpci/vpci.c |  1 -
>  2 files changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/drivers/vpci/msi.c b/xen/drivers/vpci/msi.c
> index c3eba4e14870..6ab45b9ba655 100644
> --- a/xen/drivers/vpci/msi.c
> +++ b/xen/drivers/vpci/msi.c
> @@ -193,6 +193,53 @@ static void cf_check mask_write(
>      msi->mask = val;
>  }
>  
> +static int cf_check cleanup_msi(const struct pci_dev *pdev, bool hide)
> +{
> +    int rc;
> +    unsigned int end;
> +    struct vpci *vpci = pdev->vpci;
> +    const unsigned int msi_pos = pdev->msi_pos;
> +    const unsigned int ctrl = msi_control_reg(msi_pos);
> +
> +    if ( !msi_pos || !vpci->msi )
> +        return 0;

I'm afraid the above is not correct, even if vpci->msi == NULL we
still want to hide the capability when requested to do so, that would
be the case if the memory alloc of vpci->msi fails in init_msi().

This should be:

if ( !msi_pos )
{
    ASSERT_UNREACHABLE();
    return 0;
}

if ( !hide )
{
    XFREE(vpci->msi);
    return 0;
}



> +
> +    if ( vpci->msi->masking )

You cannot assume that masking has been correctly set, depending on
where init_msi() fails masking will be uninitialized, same with
address64.

I think the logic would still be correct, because if ->masking and
->address64 is not initialized the register handlers won't be setup
either, but feels fragile.  Ideally cleanup_msi() shouldn't use the
contents of vpci->msi, because they are likely not properly
initialized.

Thanks, Roger.


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In-Reply-To: 
From: Mykola Kvach 
Date: Fri, 29 Aug 2025 14:04:32 +0300
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Message-ID: 
Subject: Re: [PATCH v11 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Jan Beulich 
Cc: Stefano Stabellini , Andrew Cooper , 
	Julien Grall , Anthony PERARD , 
	=?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	"xen-devel@lists.xenproject.org" , Mykola Kvach , 
	Bertrand Marquis , Michal Orzel , 
	Shawn Anastasio , 
	Alistair Francis , Bob Eshleman , 
	Connor Davis , Oleksii Kurochko , 
	Volodymyr Babchuk 
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Hi Jan,

On Fri, Aug 29, 2025 at 10:45=E2=80=AFAM Jan Beulich  wr=
ote:
>
> On 28.08.2025 18:32, Volodymyr Babchuk wrote:
> > Mykola Kvach  writes:
> >> @@ -880,6 +883,25 @@ void arch_domain_creation_finished(struct domain =
*d)
> >>      p2m_domain_creation_finished(d);
> >>  }
> >>
> >> +int arch_domain_resume(struct domain *d)
> >> +{
> >> +    int rc;
> >> +    typeof(d->arch.resume_ctx) *ctx =3D &d->arch.resume_ctx;
> >> +
> >> +    if ( !d->is_shutting_down || d->shutdown_code !=3D SHUTDOWN_suspe=
nd )
> >> +    {
> >> +        dprintk(XENLOG_WARNING,
> >> +                "%pd: Invalid domain state for resume: is_shutting_do=
wn=3D%d, shutdown_code=3D%d\n",
> >> +                d, d->is_shutting_down, d->shutdown_code);
> >> +        return -EINVAL;
> >> +    }
> >
> > This check probably can go into common domain_resume() function, as
> > there is nothing arch-specific in here. Probably this can be done durin=
g
> > commit, to save us from v12? If commiters are okay with this.
>
> Seeing this, I'm learning that ->is_shutting_down can actually go from
> true to false. Which I think is a problem (not of this series, but a pre-
> existing one, see [1]). Code elsewhere assumes this to not be possible,
> see e.g. __domain_crash(), but I'm also unconvinced that e.g. the shutdow=
n
> deferral logic is prepared to deal with such a case.

Should I add an extra patch to this series just for fixing this issue,
or can I do it within the scope of this one?

>
> Jan
>
> [1] e105919b0120 ("Add resumedomain domctl to resume a domain after check=
point")

Best regards,
Mykola


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Date: Fri, 29 Aug 2025 13:06:16 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jiqian Chen 
Cc: xen-devel@lists.xenproject.org, Huang Rui 
Subject: Re: [PATCH v11 5/5] vpci/msix: Implement cleanup function for MSI-X
Message-ID: 
References: <20250808080337.28609-1-Jiqian.Chen@amd.com>
 <20250808080337.28609-6-Jiqian.Chen@amd.com>
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In-Reply-To: <20250808080337.28609-6-Jiqian.Chen@amd.com>

On Fri, Aug 08, 2025 at 04:03:37PM +0800, Jiqian Chen wrote:
> When MSI-X initialization fails, vPCI hides the capability, but
> removing handlers and datas won't be performed until the device is
> deassigned. So, implement MSI-X cleanup hook that will be called
> to cleanup MSI-X related handlers and free it's associated data when
> initialization fails.
> 
> Since cleanup function of MSI-X is implemented, delete the open-code
> in vpci_deassign_device().
> 
> Signed-off-by: Jiqian Chen 
> ---
> cc: "Roger Pau Monné" 
> ---
> v10->v11 changes:
> * Move calling all cleanup hook in vpci_deassign_device() out of this patch.
> * Add hide parameter to cleanup_msix().
> * Check hide, if it is false, return directly instead of letting ctrl RO.
> 
> v9->v10 changes:
> * Call all cleanup hook in vpci_deassign_device() instead of cleanup_msix().
> 
> v8->v9 changes:
> * Modify commit message.
> * Call cleanup_msix() in vpci_deassign_device() to remove the open-code to cleanup msix datas.
> * In cleanup_msix(), move "list_del(&vpci->msix->next);" above for loop of iounmap msix tables.
> 
> v7->v8 changes:
> * Given the code in vpci_remove_registers() an error in the removal of
>   registers would likely imply memory corruption, at which point it's
>   best to fully disable the device. So, Rollback the last two modifications of v7.
> 
> v6->v7 changes:
> * Change the pointer parameter of cleanup_msix() to be const.
> * When vpci_remove_registers() in cleanup_msix() fails, not to return
>   directly, instead try to free msix and re-add ctrl handler.
> * Pass pdev->vpci into vpci_add_register() instead of pdev->vpci->msix in
>   init_msix() since we need that every handler realize that msix is NULL
>   when msix is freed but handlers are still in there.
> 
> v5->v6 changes:
> * Change the logic to add dummy handler when !vpci->msix in cleanup_msix().
> 
> v4->v5 changes:
> * Change definition "static void cleanup_msix" to "static int cf_check cleanup_msix"
>   since cleanup hook is changed to be int.
> * Add a read-only register for MSIX Control Register in the end of cleanup_msix().
> 
> v3->v4 changes:
> * Change function name from fini_msix() to cleanup_msix().
> * Change to use XFREE to free vpci->msix.
> * In cleanup function, change the sequence of check and remove action according to
>   init_msix().
> 
> v2->v3 changes:
> * Remove unnecessary clean operations in fini_msix().
> 
> v1->v2 changes:
> new patch.
> 
> Best regards,
> Jiqian Chen.
> ---
>  xen/drivers/vpci/msix.c | 47 ++++++++++++++++++++++++++++++++++++++++-
>  xen/drivers/vpci/vpci.c |  8 -------
>  2 files changed, 46 insertions(+), 9 deletions(-)
> 
> diff --git a/xen/drivers/vpci/msix.c b/xen/drivers/vpci/msix.c
> index 54a5070733aa..287aafda9157 100644
> --- a/xen/drivers/vpci/msix.c
> +++ b/xen/drivers/vpci/msix.c
> @@ -655,6 +655,51 @@ int vpci_make_msix_hole(const struct pci_dev *pdev)
>      return 0;
>  }
>  
> +static int cf_check cleanup_msix(const struct pci_dev *pdev, bool hide)
> +{
> +    int rc;
> +    struct vpci *vpci = pdev->vpci;
> +    const unsigned int msix_pos = pdev->msix_pos;
> +
> +    if ( !msix_pos )
> +        return 0;

Like with the MSI capability, is it possible to get called and
pdev->msix_pos be 0?

I would also avoid the call to vpci_remove_registers() if !hide, I
think you can change the order of the cleanup, so it's:

if ( vpci->msix )
{
    list_del(&vpci->msix->next);
    for ( unsigned int i = 0; i < ARRAY_SIZE(vpci->msix->table); i++ )
        if ( vpci->msix->table[i] )
            iounmap(vpci->msix->table[i]);

    XFREE(vpci->msix);
}

if ( !hide )
    return 0;

rc = vpci_remove_registers(vpci, msix_control_reg(msix_pos), 2);
...

Thanks, Roger.


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Date: Fri, 29 Aug 2025 14:33:28 +0300
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Subject: Re: [XEN PATCH v1] xen/flask: limit sidtable size
To: Jan Beulich , xen-devel@lists.xenproject.org
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Michal Orzel , Julien Grall ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 "Daniel P. Smith" ,
 Stefano Stabellini 
References: <20250822095123.998313-1-Sergiy_Kibrik@epam.com>
 <1797679c-582f-4b75-a036-ad3bb00bad4d@suse.com>
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25.08.25 15:00, Jan Beulich:
> On 22.08.2025 11:51, Sergiy Kibrik wrote:
>> --- a/xen/common/Kconfig
>> +++ b/xen/common/Kconfig
> 
> I wonder whether we wouldn't better move XSM's controls to a dedicated Kconfig
> file there.

you mean something like Kconfig.xsm in the same common/ directory? Or 
move this Kconfig out into xsm/ directory with the rest of flask code?

> 
>> @@ -418,6 +418,25 @@ config XSM_FLASK_AVC_STATS
>>   
>>   	  If unsure, say Y.
>>   
>> +config XSM_FLASK_SIDTABLE_LIMIT
>> +	def_bool n
> 
> This makes little sense; just "bool" would have the same effect. Yet then
> you can combine that with ...
> 
>> +	prompt "Limit the size of SID table" if EXPERT
> 
> ... this line.
> 
>> +	depends on XSM_FLASK
>> +	---help---
> 
> No triple dashes around "help" anymore, please.
> 
>> +	  Limit the number of security identifiers allocated and operated by Xen.
>> +	  This will limit the number of security contexts and heap memory
>> +	  allocated for SID table entries.
>> +
>> +	  If unsure, say N.
>> +
>> +config XSM_FLASK_MAX_SID
>> +	int "Max SID table size" if XSM_FLASK_SIDTABLE_LIMIT
>> +	default 512
> 
> Hmm, wouldn't the default better be what we had so far? As per the justification
> you aim at a special case (embedded) with this limit.
> 

yes, we can have a default value of UINT_MAX specified here if we'll use 
base-2 exponent as a value. And get rid of second option.


   -Sergiy


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Subject: Re: [XEN PATCH v1] xen/flask: limit sidtable size
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On 29.08.2025 13:33, Sergiy Kibrik wrote:
> 25.08.25 15:00, Jan Beulich:
>> On 22.08.2025 11:51, Sergiy Kibrik wrote:
>>> --- a/xen/common/Kconfig
>>> +++ b/xen/common/Kconfig
>>
>> I wonder whether we wouldn't better move XSM's controls to a dedicated Kconfig
>> file there.
> 
> you mean something like Kconfig.xsm in the same common/ directory? Or 
> move this Kconfig out into xsm/ directory with the rest of flask code?

The latter would be preferable imo.

Jan


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To: Julien Grall , "Orzel, Michal" ,
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Subject: Re: [PATCH] xen/arm: smmuv3: Add cache maintenance for non-coherent
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On 29.08.2025 13:04, Mykola Kvach wrote:
> On Fri, Aug 29, 2025 at 10:45 AM Jan Beulich  wrote:
>> On 28.08.2025 18:32, Volodymyr Babchuk wrote:
>>> Mykola Kvach  writes:
>>>> @@ -880,6 +883,25 @@ void arch_domain_creation_finished(struct domain *d)
>>>>      p2m_domain_creation_finished(d);
>>>>  }
>>>>
>>>> +int arch_domain_resume(struct domain *d)
>>>> +{
>>>> +    int rc;
>>>> +    typeof(d->arch.resume_ctx) *ctx = &d->arch.resume_ctx;
>>>> +
>>>> +    if ( !d->is_shutting_down || d->shutdown_code != SHUTDOWN_suspend )
>>>> +    {
>>>> +        dprintk(XENLOG_WARNING,
>>>> +                "%pd: Invalid domain state for resume: is_shutting_down=%d, shutdown_code=%d\n",
>>>> +                d, d->is_shutting_down, d->shutdown_code);
>>>> +        return -EINVAL;
>>>> +    }
>>>
>>> This check probably can go into common domain_resume() function, as
>>> there is nothing arch-specific in here. Probably this can be done during
>>> commit, to save us from v12? If commiters are okay with this.
>>
>> Seeing this, I'm learning that ->is_shutting_down can actually go from
>> true to false. Which I think is a problem (not of this series, but a pre-
>> existing one, see [1]). Code elsewhere assumes this to not be possible,
>> see e.g. __domain_crash(), but I'm also unconvinced that e.g. the shutdown
>> deferral logic is prepared to deal with such a case.
> 
> Should I add an extra patch to this series just for fixing this issue,
> or can I do it within the scope of this one?

I'm happy to see you fix this (I don't even see how we could easily do so),
but definitely in a separate patch (and possibly even independent of this
series). My remark wasn't meant to get in the way of your work, it was just
something I noticed and thought would be relevant to call out.

Jan


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From: Frediano Ziglio 
To: xen-devel@lists.xenproject.org
Cc: Frediano Ziglio ,
	"Daniel P. Smith" ,
	=?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= ,
	Jan Beulich 
Subject: [PATCH v3] xen/efi: Fix crash with initial empty EFI options
Date: Fri, 29 Aug 2025 13:22:26 +0100
Message-ID: <20250829122227.43023-1-frediano.ziglio@cloud.com>
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EFI code path split options from EFI LoadOptions fields in 2
pieces, first EFI options, second Xen options.
"get_argv" function is called first to get the number of arguments
in the LoadOptions, second, after allocating enough space, to
fill some "argc"/"argv" variable. However the first parsing could
be different from second as second is able to detect "--" argument
separator. So it was possible that "argc" was bigger than the
initialized portion of "argv" array, leading to potential
uninitialized pointer dereference, in particular a string like
"-- a b c" would lead to crashes.
Using EFI shell is possible to pass any kind of string in
LoadOptions.

Fixes: bf6501a62e80 ("x86-64: EFI boot code")
Signed-off-by: Frediano Ziglio 
Reviewed-by: Marek Marczykowski-Górecki 
---
Changes since v2:
- updated commit message
- added Reviewed-by line

Changes since v1:
- use argc to make code more clear;
- fix commit reference;
- improve commit message.
---
 xen/common/efi/boot.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/xen/common/efi/boot.c b/xen/common/efi/boot.c
index b7fdb031d0..e12fa1a7ec 100644
--- a/xen/common/efi/boot.c
+++ b/xen/common/efi/boot.c
@@ -350,10 +350,11 @@ static unsigned int __init get_argv(unsigned int argc, CHAR16 **argv,
 
     if ( argc )
     {
+        argc = 0;
         cmdline = data + *offset;
         /* EFI_LOAD_OPTION does not supply an image name as first component. */
         if ( *offset )
-            *argv++ = NULL;
+            argv[argc++] = NULL;
     }
     else if ( size > sizeof(*cmdline) && !(size % sizeof(*cmdline)) &&
               (wmemchr(data, 0, size / sizeof(*cmdline)) ==
@@ -414,14 +415,14 @@ static unsigned int __init get_argv(unsigned int argc, CHAR16 **argv,
                 ++argc;
             else if ( prev && wstrcmp(prev, L"--") == 0 )
             {
-                --argv;
+                --argc;
                 if ( options )
                     *options = cmdline;
                 break;
             }
             else
             {
-                *argv++ = prev = ptr;
+                argv[argc++] = prev = ptr;
                 *ptr = *cmdline;
                 *++ptr = 0;
             }
@@ -429,7 +430,7 @@ static unsigned int __init get_argv(unsigned int argc, CHAR16 **argv,
         prev_sep = cur_sep;
     }
     if ( argv )
-        *argv = NULL;
+        argv[argc] = NULL;
     return argc;
 }
 
@@ -1355,8 +1356,8 @@ void EFIAPI __init noreturn efi_start(EFI_HANDLE ImageHandle,
                                   (argc + 1) * sizeof(*argv) +
                                       loaded_image->LoadOptionsSize,
                                   (void **)&argv) == EFI_SUCCESS )
-            get_argv(argc, argv, loaded_image->LoadOptions,
-                     loaded_image->LoadOptionsSize, &offset, &options);
+            argc = get_argv(argc, argv, loaded_image->LoadOptions,
+                            loaded_image->LoadOptionsSize, &offset, &options);
         else
             argc = 0;
         for ( i = 1; i < argc; ++i )
-- 
2.43.0



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Subject: Re: [PATCH v11 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: xen-devel@lists.xenproject.org
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On Thu, Aug 28, 2025 at 5:54=E2=80=AFPM Mykola Kvach  wrote:
>
> From: Mykola Kvach 
>
> Add support for the PSCI SYSTEM_SUSPEND function in the vPSCI interface,
> allowing guests to request suspend via the PSCI v1.0 SYSTEM_SUSPEND call
> (both 32-bit and 64-bit variants).
>
> Implementation details:
> - Add SYSTEM_SUSPEND function IDs to PSCI definitions
> - Trap and handle SYSTEM_SUSPEND in vPSCI
> - Allow only non-hardware domains to invoke SYSTEM_SUSPEND; return
>   PSCI_NOT_SUPPORTED for the hardware domain to avoid halting the system
>   in hwdom_shutdown() via domain_shutdown
> - Require all secondary VCPUs of the calling domain to be offline before
>   suspend, as mandated by the PSCI specification
>
> The arch_domain_resume() function is an architecture-specific hook that i=
s
> invoked during domain resume to perform any necessary setup or restoratio=
n
> steps required by the platform.
>
> The new vpsci_vcpu_up_prepare() helper is called on the resume path to se=
t up
> the vCPU context (such as entry point, some system regs and context ID) b=
efore
> resuming a suspended guest. This keeps ARM/vPSCI-specific logic out of co=
mmon
> code and avoids intrusive changes to the generic resume flow.
>
> Usage:
>
> For Linux-based guests, suspend can be initiated with:
>     echo mem > /sys/power/state
> or via:
>     systemctl suspend
>
> Resuming the guest is performed from control domain using:
>       xl resume 
>
> Signed-off-by: Mykola Kvach 
> ---
> Changes in V11:
> - introduce arch_domain_resume() and vpsci_vcpu_up_prepare(), which are n=
ow
> called on the resume path to avoid extra modifications to common code.
> The vCPU context is now updated during domain resume.
>
> Changes in V10:
> - small changes to the commit message reflect updates introduced in this
>   version of the patch.
> - Comments are improved, clarified, and expanded, especially regarding PS=
CI
>   requirements and context handling.
> - An ARM-specific helper (domain_resume_nopause_helper)
> - gprintk() and PRIregister are used for logging in vPSCI code.
> - An isb() is added before p2m_save_state
> - The is_64bit_domain check is dropped when masking the upper part of ent=
ry
>   point and cid for SMC32 SYSTEM_SUSPEND PSCI calls
>
> Changes in V9:
> - no functional changes
> - cosmetic chnages after review
> - enhance commit message and add extra comment to the code after review
>
> Changes in V8:
> - GIC and virtual timer context must be saved when the domain suspends
> - rework locking
> - minor changes after code review
>
> Changes in V7:
> - add proper locking
> - minor changes after code review
>
> Changes in V6:
> - skip execution of ctxt_switch_from for vcpu that is in paused domain
> - add implementation of domain_resume without domain_pause
> - add helper function to determine if vcpu is suspended or not
> - ignore upper 32 bits of argument values when the domain is 64-bit
>   and calls the SMC32 SYSTEM_SUSPEND function
> - cosmetic changes after review
>
> Changes in V5:
> - don't use standby mode, restore execution in a provided by guest point
> - move checking that all CPUs, except current one, are offline to after
>   pausing the vCPUs
> - provide ret status from arch_domain_shutdown and handle it in
>   domain_shutdown
> - adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI functio=
ns
>
> Changes in V4:
> Dropped all changes related to watchdog, domain is marked as shutting
> down in domain_shutdown and watchdog timeout handler won't trigger
> because of it.
>
> Previous versions included code to manage Xen watchdog timers during susp=
end,
> but this was removed. When a guest OS starts the Xen watchdog (either via=
 the
> kernel driver or xenwatchdogd), it is responsible for managing that state
> across suspend/resume. On Linux, the Xen kernel driver properly stops the
> watchdog during suspend. However, when xenwatchdogd is used instead, susp=
end
> handling is incomplete, potentially leading to watchdog-triggered resets =
on
> resume. Xen leaves watchdog handling to the guest OS and its services.
>
> Dropped all changes related to VCPU context, because instead domain_shutd=
own
> is used, so we don't need any extra changes for suspending domain.
>
> Changes in V3:
> Dropped all domain flags and related code (which touched common functions=
 like
> vcpu_unblock), keeping only the necessary changes for Xen suspend/resume,=
 i.e.
> suspend/resume is now fully supported only for the hardware domain.
> Proper support for domU suspend/resume will be added in a future patch.
> This patch does not yet include VCPU context reset or domain context
> restoration in VCPU.
> ---
>  xen/arch/arm/domain.c                 |  22 +++++
>  xen/arch/arm/include/asm/domain.h     |   6 ++
>  xen/arch/arm/include/asm/perfc_defn.h |   1 +
>  xen/arch/arm/include/asm/psci.h       |   2 +
>  xen/arch/arm/include/asm/vpsci.h      |   5 +-
>  xen/arch/arm/vpsci.c                  | 114 +++++++++++++++++++++-----
>  xen/arch/ppc/stubs.c                  |   5 ++
>  xen/arch/riscv/stubs.c                |   5 ++
>  xen/arch/x86/domain.c                 |   5 ++
>  xen/common/domain.c                   |   9 ++
>  xen/include/xen/domain.h              |   2 +
>  11 files changed, 156 insertions(+), 20 deletions(-)
>
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index 863ae18157..6fd73eedde 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -12,6 +12,8 @@
>  #include 
>  #include 
>
> +#include 
> +
>  #include 
>  #include 
>  #include 
> @@ -27,6 +29,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>
>  #include "vpci.h"
> @@ -880,6 +883,25 @@ void arch_domain_creation_finished(struct domain *d)
>      p2m_domain_creation_finished(d);
>  }
>
> +int arch_domain_resume(struct domain *d)
> +{
> +    int rc;
> +    typeof(d->arch.resume_ctx) *ctx =3D &d->arch.resume_ctx;
> +
> +    if ( !d->is_shutting_down || d->shutdown_code !=3D SHUTDOWN_suspend =
)
> +    {
> +        dprintk(XENLOG_WARNING,
> +                "%pd: Invalid domain state for resume: is_shutting_down=
=3D%d, shutdown_code=3D%d\n",
> +                d, d->is_shutting_down, d->shutdown_code);
> +        return -EINVAL;
> +    }
> +
> +    rc =3D vpsci_vcpu_up_prepare(ctx->wake_cpu , ctx->ep, ctx->cid);
> +    memset(ctx, 0, sizeof(*ctx));
> +
> +    return rc;
> +}
> +
>  static int is_guest_pv32_psr(uint32_t psr)
>  {
>      switch (psr & PSR_MODE_MASK)
> diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm=
/domain.h
> index a3487ca713..68185fc4d6 100644
> --- a/xen/arch/arm/include/asm/domain.h
> +++ b/xen/arch/arm/include/asm/domain.h
> @@ -121,6 +121,12 @@ struct arch_domain
>      void *tee;
>  #endif
>
> +    struct resume_info {
> +        register_t ep;
> +        register_t cid;
> +        struct vcpu *wake_cpu;
> +    } resume_ctx;
> +
>  }  __cacheline_aligned;
>
>  struct arch_vcpu
> diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/include=
/asm/perfc_defn.h
> index effd25b69e..8dfcac7e3b 100644
> --- a/xen/arch/arm/include/asm/perfc_defn.h
> +++ b/xen/arch/arm/include/asm/perfc_defn.h
> @@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system_r=
eset")
>  PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
>  PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
>  PERFCOUNTER(vpsci_features,            "vpsci: features")
> +PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
>
>  PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
>
> diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/p=
sci.h
> index 4780972621..48a93e6b79 100644
> --- a/xen/arch/arm/include/asm/psci.h
> +++ b/xen/arch/arm/include/asm/psci.h
> @@ -47,10 +47,12 @@ void call_psci_system_reset(void);
>  #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
>  #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
>  #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
> +#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
>
>  #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
>  #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
>  #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
> +#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
>
>  /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
>  #define PSCI_0_2_AFFINITY_LEVEL_ON      0
> diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/asm/=
vpsci.h
> index 0cca5e6830..d790ab3715 100644
> --- a/xen/arch/arm/include/asm/vpsci.h
> +++ b/xen/arch/arm/include/asm/vpsci.h
> @@ -23,12 +23,15 @@
>  #include 
>
>  /* Number of function implemented by virtual PSCI (only 0.2 or later) */
> -#define VPSCI_NR_FUNCS  12
> +#define VPSCI_NR_FUNCS  14
>
>  /* Functions handle PSCI calls from the guests */
>  bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
>  bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid);
>
> +int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
> +                          register_t context_id);
> +
>  #endif /* __ASM_VPSCI_H__ */
>
>  /*
> diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
> index 7ba9ccd94b..50cf5fd96c 100644
> --- a/xen/arch/arm/vpsci.c
> +++ b/xen/arch/arm/vpsci.c
> @@ -10,30 +10,16 @@
>
>  #include 
>
> -static int do_common_cpu_on(register_t target_cpu, register_t entry_poin=
t,
> -                            register_t context_id)
> +int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
> +                   register_t context_id)
>  {
> -    struct vcpu *v;
> -    struct domain *d =3D current->domain;
> -    struct vcpu_guest_context *ctxt;
>      int rc;
> +    struct domain *d =3D current->domain;

Note to myself:

It is not a good idea to use current here; it should be v instead.
It works for CPU_ON because the requested CPU will be in the same domain
as the caller. However, an interesting situation arises when this is
invoked from "xl resume". If the control domain and the domain being
resumed have different bitness (e.g., 32-bit and 64-bit domains), we
will have problems: we may fill some fields as for one bitness, but
arch_set_info_guest will check the fields for another bitness.

>      bool is_thumb =3D entry_point & 1;
> -    register_t vcpuid;
> -
> -    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> -
> -    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> -        return PSCI_INVALID_PARAMETERS;
> -
> -    /* THUMB set is not allowed with 64-bit domain */
> -    if ( is_64bit_domain(d) && is_thumb )
> -        return PSCI_INVALID_ADDRESS;
> -
> -    if ( !test_bit(_VPF_down, &v->pause_flags) )
> -        return PSCI_ALREADY_ON;
> +    struct vcpu_guest_context *ctxt;
>
>      if ( (ctxt =3D alloc_vcpu_guest_context()) =3D=3D NULL )
> -        return PSCI_DENIED;
> +        return -ENOMEM;
>
>      vgic_clear_pending_irqs(v);

Leftover.
We don't need to call vgic_clear_pending_irqs(v) when resuming a domain,
but this function is called in do_common_cpu_on, so it have to be removed
from this function.

>
> @@ -76,8 +62,37 @@ static int do_common_cpu_on(register_t target_cpu, reg=
ister_t entry_point,
>      free_vcpu_guest_context(ctxt);
>
>      if ( rc < 0 )
> +        return rc;
> +
> +    return 0;
> +}
> +
> +static int do_common_cpu_on(register_t target_cpu, register_t entry_poin=
t,
> +                            register_t context_id)
> +{
> +    struct vcpu *v;
> +    struct domain *d =3D current->domain;
> +    int rc;
> +    bool is_thumb =3D entry_point & 1;
> +    register_t vcpuid;
> +
> +    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> +
> +    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> +        return PSCI_INVALID_PARAMETERS;
> +
> +    /* THUMB set is not allowed with 64-bit domain */
> +    if ( is_64bit_domain(d) && is_thumb )
> +        return PSCI_INVALID_ADDRESS;
> +
> +    if ( !test_bit(_VPF_down, &v->pause_flags) )
> +        return PSCI_ALREADY_ON;
> +
> +    rc =3D vpsci_vcpu_up_prepare(v, entry_point, context_id);
> +    if ( rc )
>          return PSCI_DENIED;
>
> +    vgic_clear_pending_irqs(v);
>      vcpu_wake(v);
>
>      return PSCI_SUCCESS;
> @@ -197,6 +212,48 @@ static void do_psci_0_2_system_reset(void)
>      domain_shutdown(d,SHUTDOWN_reboot);
>  }
>
> +static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t =
cid)
> +{
> +    int32_t rc;
> +    struct vcpu *v;
> +    struct domain *d =3D current->domain;
> +    bool is_thumb =3D epoint & 1;
> +
> +    /* THUMB set is not allowed with 64-bit domain */
> +    if ( is_64bit_domain(d) && is_thumb )
> +        return PSCI_INVALID_ADDRESS;
> +
> +    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> +    if ( is_hardware_domain(d) )
> +        return PSCI_NOT_SUPPORTED;
> +
> +    /* Ensure that all CPUs other than the calling one are offline */
> +    domain_lock(d);
> +    for_each_vcpu ( d, v )
> +    {
> +        if ( v !=3D current && is_vcpu_online(v) )
> +        {
> +            domain_unlock(d);
> +            return PSCI_DENIED;
> +        }
> +    }
> +    domain_unlock(d);
> +
> +    rc =3D domain_shutdown(d, SHUTDOWN_suspend);
> +    if ( rc )
> +        return PSCI_DENIED;
> +
> +    d->arch.resume_ctx.ep =3D epoint;
> +    d->arch.resume_ctx.cid =3D cid;
> +    d->arch.resume_ctx.wake_cpu =3D current;
> +
> +    gprintk(XENLOG_DEBUG,
> +            "SYSTEM_SUSPEND requested, epoint=3D0x%"PRIregister", cid=3D=
0x%"PRIregister,
> +            epoint, cid);
> +
> +    return rc;
> +}
> +
>  static int32_t do_psci_1_0_features(uint32_t psci_func_id)
>  {
>      /* /!\ Ordered by function ID and not name */
> @@ -214,6 +271,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_fun=
c_id)
>      case PSCI_0_2_FN32_SYSTEM_OFF:
>      case PSCI_0_2_FN32_SYSTEM_RESET:
>      case PSCI_1_0_FN32_PSCI_FEATURES:
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
>      case ARM_SMCCC_VERSION_FID:
>          return 0;
>      default:
> @@ -344,6 +403,23 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, u=
int32_t fid)
>          return true;
>      }
>
> +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> +    {
> +        register_t epoint =3D PSCI_ARG(regs, 1);
> +        register_t cid =3D PSCI_ARG(regs, 2);
> +
> +        if ( fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND )
> +        {
> +            epoint &=3D GENMASK(31, 0);
> +            cid &=3D GENMASK(31, 0);
> +        }
> +
> +        perfc_incr(vpsci_system_suspend);
> +        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
> +        return true;
> +    }
> +
>      default:
>          return false;
>      }
> diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c
> index bdaf474c5c..0db0627b5c 100644
> --- a/xen/arch/ppc/stubs.c
> +++ b/xen/arch/ppc/stubs.c
> @@ -224,6 +224,11 @@ void arch_domain_creation_finished(struct domain *d)
>      BUG_ON("unimplemented");
>  }
>
> +int arch_domain_resume(struct domain *d)
> +{
> +    return 0;
> +}
> +
>  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
>  {
>      BUG_ON("unimplemented");
> diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c
> index 1a8c86cd8d..52532ae14d 100644
> --- a/xen/arch/riscv/stubs.c
> +++ b/xen/arch/riscv/stubs.c
> @@ -198,6 +198,11 @@ void arch_domain_creation_finished(struct domain *d)
>      BUG_ON("unimplemented");
>  }
>
> +int arch_domain_resume(struct domain *d)
> +{
> +    return 0;
> +}
> +
>  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
>  {
>      BUG_ON("unimplemented");
> diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
> index 19fd86ce88..94a06bc697 100644
> --- a/xen/arch/x86/domain.c
> +++ b/xen/arch/x86/domain.c
> @@ -1138,6 +1138,11 @@ void arch_domain_creation_finished(struct domain *=
d)
>          hvm_domain_creation_finished(d);
>  }
>
> +int arch_domain_resume(struct domain *d)
> +{
> +    return 0;
> +}
> +
>  #ifdef CONFIG_COMPAT
>  #define xen_vcpu_guest_context vcpu_guest_context
>  #define fpu_ctxt fpu_ctxt.x
> diff --git a/xen/common/domain.c b/xen/common/domain.c
> index 104e917f07..d73a88ced5 100644
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -1352,6 +1352,7 @@ int domain_shutdown(struct domain *d, u8 reason)
>  void domain_resume(struct domain *d)
>  {
>      struct vcpu *v;
> +    int rc;
>
>      /*
>       * Some code paths assume that shutdown status does not get reset un=
der
> @@ -1359,6 +1360,14 @@ void domain_resume(struct domain *d)
>       */
>      domain_pause(d);
>
> +    rc =3D arch_domain_resume(d);
> +    if ( rc )
> +    {
> +        domain_unpause(d);
> +        printk("%pd: Failed to resume domain (ret %d)\n", d, rc);
> +        return;
> +    }
> +
>      spin_lock(&d->shutdown_lock);
>
>      d->is_shutting_down =3D d->is_shut_down =3D 0;
> diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
> index e10baf2615..5f77ffadf1 100644
> --- a/xen/include/xen/domain.h
> +++ b/xen/include/xen/domain.h
> @@ -109,6 +109,8 @@ int arch_domain_soft_reset(struct domain *d);
>
>  void arch_domain_creation_finished(struct domain *d);
>
> +int arch_domain_resume(struct domain *d);
> +
>  void arch_p2m_set_access_required(struct domain *d, bool access_required=
);
>
>  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c);
> --
> 2.48.1
>


From xen-devel-bounces@lists.xenproject.org Fri Aug 29 12:35:35 2025
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Date: Fri, 29 Aug 2025 06:35:16 -0600
From: Keith Busch 
To: Jason Gunthorpe 
Cc: Leon Romanovsky ,
	Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, linux-block@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, linux-nvme@lists.infradead.org,
	linuxppc-dev@lists.ozlabs.org, linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 15/16] block-dma: properly take MMIO path
Message-ID: 
References: 
 <642dbeb7aa94257eaea71ec63c06e3f939270023.1755624249.git.leon@kernel.org>
 
 <20250828165427.GB10073@unreal>
 
 <20250828184115.GE7333@nvidia.com>
 
 <20250828191820.GH7333@nvidia.com>
 
 <20250828234542.GK7333@nvidia.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20250828234542.GK7333@nvidia.com>

On Thu, Aug 28, 2025 at 08:45:42PM -0300, Jason Gunthorpe wrote:
> On Thu, Aug 28, 2025 at 02:54:35PM -0600, Keith Busch wrote:
> 
> > In truth though, I hadn't tried p2p metadata before today, and it looks
> > like bio_integrity_map_user() is missing the P2P extraction flags to
> > make that work. Just added this patch below, now I can set p2p or host
> > memory independently for data and integrity payloads:
> 
> I think it is a bit more than that, you have to make sure all the meta
> data is the same, either all p2p or all cpu and then record this
> somehow so the DMA mapping knows what kind it is.

Sure, I can get all that added in for the real patch.
 
> Once that is all done then the above should still be OK, the dma unmap
> of the data can follow Leon's new flag and the dma unmap of the
> integrity can follow however integrity kept track (in the
> bio_integrity_payload perhaps?) ??

We have available bits in the bio_integrity_payload bip_flags, so that
sounds doable. I think we'll need to rearrange some things so we can
reuse the important code for data and metadata mapping/unmapping, but
doesn't look too bad. I'll get started on that.


From xen-devel-bounces@lists.xenproject.org Fri Aug 29 13:01:24 2025
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Date: Fri, 29 Aug 2025 15:01:14 +0200
From: Anthony PERARD 
To: Jahan Murudi 
Cc: xen-devel@lists.xenproject.org,
	Anthony PERARD 
Subject: Re: [RFC PATCH v3] tools/xentop: Add physical CPU statistics support
Message-ID: 
References: <20250804130643.1046157-1-jahan.murudi.zg@renesas.com>
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On Mon, Aug 04, 2025 at 06:36:43PM +0530, Jahan Murudi wrote:
> diff --git a/tools/xentop/pcpu.c b/tools/xentop/pcpu.c
> new file mode 100644
> index 0000000000..53d6b9c30c
> --- /dev/null
> +++ b/tools/xentop/pcpu.c
> @@ -0,0 +1,152 @@
[..]
> +int update_pcpu_stats(const struct timeval *now, unsigned int delay_sec)
> +{
> +    struct xen_sysctl_cpuinfo info[MAX_PCPUS];
> +    int detected_cpus = 0;
> +    int ret, i;
> +    uint64_t current_time = (uint64_t)now->tv_sec * 1000000ULL + now->tv_usec;
> +
> +    if (!xc_handle) {
> +        xc_handle = xc_interface_open(NULL, NULL, 0);
> +        if (!xc_handle) {
> +            report_pcpu_error("xc_interface_open failed");
> +            return -1;
> +        }
> +    }
> +
> +    ret = xc_getcpuinfo(xc_handle, MAX_PCPUS, info, &detected_cpus);
> +    if (ret < 0) {
> +        report_pcpu_error("xc_getcpuinfo failed");
> +        return -1;
> +    }
> +
> +    /* Allocate/reallocate memory if needed */
> +    if (!pcpu_stats || detected_cpus > allocated_pcpus) {
> +        pcpu_stat_t *new_stats = realloc(pcpu_stats,
> +                        detected_cpus * sizeof(*pcpu_stats));
> +        if (!new_stats) goto alloc_error;

>From here, `pcpu_stats` is an invalid pointer. You need
`pcpu_stats = new_stats` to avoid double free that would happen in
free_pcpu_stats(). And then, no need to do anything different for the
error handling of the other realloc(), that is, no need for any of the
free(new_*) calls.

> +        uint64_t *new_prev_idle = realloc(prev_idle,
> +                        detected_cpus * sizeof(*prev_idle));
> +        if (!new_prev_idle) {
> +            free(new_stats);
> +            goto alloc_error;
> +        }
> +
> +        uint64_t *new_prev_time = realloc(prev_time,
> +                        detected_cpus * sizeof(*prev_time));
> +        if (!new_prev_time) {
> +            free(new_stats);
> +            free(new_prev_idle);
> +            goto alloc_error;
> +        }
> +
> +        pcpu_stats = new_stats;
> +        prev_idle = new_prev_idle;
> +        prev_time = new_prev_time;
> +        allocated_pcpus = detected_cpus;
> +
> +        /* Initialize new entries */
> +        for (i = 0; i < detected_cpus; i++) {
> +            prev_idle[i] = info[i].idletime / 1000; /* ns->us */
> +            prev_time[i] = current_time;
> +            pcpu_stats[i].usage_pct = 0.0;
> +        }
> +        return 0;
> +    }
> +
> +    /* Calculate CPU usage with delay normalization */
> +    for (i = 0; i < detected_cpus; i++) {
> +        uint64_t current_idle = info[i].idletime / 1000;
> +        uint64_t idle_diff = current_idle - prev_idle[i];
> +        uint64_t time_diff = current_time - prev_time[i];

Do we need to calculate `time_diff` for every cpu? It looks like
prev_time[i] is always the same value, which is `current_time` from the
previous call of update_pcpu_stats().

> +
> +        /* Use configured delay when actual interval is too small */

I can't figure out why this would be necessary. Why a value of less
than 100000 would be too small for `time_diff`? Why would we want to use
`delay_sec` here, surely that would mean that we would calculate the
wrong `usage`?

> +        if (time_diff < 100000) {
> +            time_diff = delay_sec * 1000000ULL;
> +        }
> +
> +        if (time_diff > 0) {
> +            double usage = 100.0 * (1.0 - ((double)idle_diff / time_diff));
> +            /* Clamp between 0-100% */
> +            pcpu_stats[i].usage_pct = (usage < 0) ? 0.0 :
> +                                     (usage > 100) ? 100.0 : usage;
> +        } else {
> +            pcpu_stats[i].usage_pct = 0.0;
> +        }
> +
> +        prev_idle[i] = current_idle;
> +        prev_time[i] = current_time;
> +    }
> +
> +    return 0;
> +
> +alloc_error:
> +    free_pcpu_stats();
> +    errno = ENOMEM;
> +    report_pcpu_error("memory allocation failed");
> +    return -1;
> +}
> +
> +void print_pcpu_stats(void)
> +{
> +    if (!pcpu_stats || allocated_pcpus == 0) {
> +        printf("\r\nNo PCPU data available\r\n");
> +        return;
> +    }
> +
> +    printf("\r\nPhysical CPU Usage:\r\n");
> +    printf("+-------+--------+\r\n");
> +    printf("| Core  | Usage  |\r\n");
> +    printf("+-------+--------+\r\n");

I don't think that the right way to print information on the screen in
non-batch mode. It kind of work, but it pushes the bottom bar (with help
on how to activate more stat) out of the screen. And in batch mode,
there's no need for \r.

There's a print() function in xentop.c which seems to take care of batch
vs ncurse mode.

> +
> +    for (int i = 0; i < allocated_pcpus; i++) {
> +        printf("| %-5d | %5.1f%% |\r\n", i, pcpu_stats[i].usage_pct);
> +    }
> +
> +    printf("+-------+--------+\r\n");
> +}
> +
> +void free_pcpu_stats(void)
> +{
> +    if (xc_handle) {
> +        xc_interface_close(xc_handle);
> +        xc_handle = NULL;
> +    }
> +    free(pcpu_stats);
> +    free(prev_idle);
> +    free(prev_time);
> +    pcpu_stats = NULL;
> +    prev_idle = NULL;
> +    prev_time = NULL;
> +    allocated_pcpus = 0;
> +}


Thanks,

-- 
Anthony PERARD


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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=201/9]=20x86/hvm:=20Use=20direct=20structures=20instead=20of=20guest=20handles?=
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Le 28/08/2025 =C3=A0 14:16, Jan Beulich a =C3=A9crit=C2=A0:
> On 21.08.2025 17:25, Teddy Astie wrote:
>> Make these functions work with hypervisor-owned pointer rather than
>> guest handles, so the function parameters don't have to live in guest me=
mory.
> 
> This is odd to read - the function parameters (arguments) didn't live in
> guest memory before either.
> 

I agree, I should reword that so that it's less confusing.

>> No functional changes intended.
>>
>> Signed-off-by: Teddy Astie 
>> ---
>>   xen/arch/x86/hvm/hvm.c | 126 +++++++++++++++++++++++------------------
>>   1 file changed, 70 insertions(+), 56 deletions(-)
>>
>> diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
>> index 56c7de3977..8bf59c63fe 100644
>> --- a/xen/arch/x86/hvm/hvm.c
>> +++ b/xen/arch/x86/hvm/hvm.c
>> @@ -4142,19 +4142,14 @@ static int hvmop_flush_tlb_all(void)
>>       return paging_flush_tlb(NULL) ? 0 : -ERESTART;
>>   }
>>   
>> -static int hvmop_set_evtchn_upcall_vector(
>> -    XEN_GUEST_HANDLE_PARAM(xen_hvm_evtchn_upcall_vector_t) uop)
>> +static int hvmop_set_evtchn_upcall_vector(xen_hvm_evtchn_upcall_vector_=
t op)
> 
> Please can we avoid passing structures by value?
> 

We could, but we would end up having to modify more code to go there i.e 
replacing all op.* with op->* which I tried to avoid here.

> More generally: This one-by-one adjustment is what I'd really like to avo=
id
> with any new interface. It would be far better if ...
> 
>>   {
>> -    xen_hvm_evtchn_upcall_vector_t op;
>>       struct domain *d =3D current->domain;
>>       struct vcpu *v;
>>   
>>       if ( !is_hvm_domain(d) )
>>           return -EINVAL;
>>   
>> -    if ( copy_from_guest(&op, uop, 1) )
>> -        return -EFAULT;
> 
> ... copy_from_guest() could transparantly handle both cases (virtual and
> physical addresses being used). And yes, this would exclude an "everying =
in
> registers" approach.
> 

A part of the goal here is to split the ABI part from the hypercall 
logic; such as it gets possible to have ABI that don't need to refer to 
guest addresses (either virtual or physical); and could help dealing 
with current 32-bits vs 64-bits ABIs. All without duplicating the main 
hypercall logic.

>> @@ -5115,28 +5087,70 @@ long do_hvm_op(unsigned long op, XEN_GUEST_HANDL=
E_PARAM(void) arg)
>>       switch ( op )
>>       {
>>       case HVMOP_set_evtchn_upcall_vector:
>> -        rc =3D hvmop_set_evtchn_upcall_vector(
>> -            guest_handle_cast(arg, xen_hvm_evtchn_upcall_vector_t));
>> +    {
>> +        struct xen_hvm_evtchn_upcall_vector op;
>> +
>> +        if ( copy_from_guest(&op, arg, 1) )
>> +        {
>> +            rc =3D -EFAULT;
>> +            break;
>> +        }
>> +
>> +        rc =3D hvmop_set_evtchn_upcall_vector(op);
>>           break;
>> +    }
>>       
>>       case HVMOP_set_param:
>> -        rc =3D hvmop_set_param(
>> -            guest_handle_cast(arg, xen_hvm_param_t));
>> +    {
>> +        struct xen_hvm_param op;
>> +
>> +        if ( copy_from_guest(&op, arg, 1) )
>> +        {
>> +            rc =3D -EFAULT;
>> +            break;
>> +        }
>> +
>> +        rc =3D hvmop_set_param(op);
>>           break;
>> +    }
>>   
>>       case HVMOP_get_param:
>> -        rc =3D hvmop_get_param(
>> -            guest_handle_cast(arg, xen_hvm_param_t));
>> +    {
>> +        struct xen_hvm_param op;
>> +
>> +        if ( copy_from_guest(&op, arg, 1) )
>> +        {
>> +            rc =3D -EFAULT;
>> +            break;
>> +        }
>> +
>> +        rc =3D hvmop_get_param(&op);
>> +
>> +        if ( !rc && copy_to_guest(arg, &op, 1) )
> 
> Why would the original __copy_to_guest() need to change to copy_to_guest(=
)?
> 

That doesn't need to.

> Jan

Teddy


Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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Date: Fri, 29 Aug 2025 10:16:25 -0300
From: Jason Gunthorpe 
To: Leon Romanovsky 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 00/16] dma-mapping: migrate to physical address-based
 API
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On Tue, Aug 19, 2025 at 08:36:44PM +0300, Leon Romanovsky wrote:

> This series does the core code and modern flows. A followup series
> will give the same treatment to the legacy dma_ops implementation.

I took a quick check over this to see that it is sane.  I think using
phys is an improvement for most of the dma_ops implemenations.

  arch/sparc/kernel/pci_sun4v.c
  arch/sparc/kernel/iommu.c
    Uses __pa to get phys from the page, never touches page

  arch/alpha/kernel/pci_iommu.c
  arch/sparc/mm/io-unit.c
  drivers/parisc/ccio-dma.c
  drivers/parisc/sba_iommu.c
    Does page_addres() and later does __pa on it. Doesn't touch struct page

  arch/x86/kernel/amd_gart_64.c
  drivers/xen/swiotlb-xen.c
  arch/mips/jazz/jazzdma.c
    Immediately does page_to_phys(), never touches struct page

  drivers/vdpa/vdpa_user/vduse_dev.c
    Does page_to_phys() to call iommu_map()

  drivers/xen/grant-dma-ops.c
    Does page_to_pfn() and nothing else

  arch/powerpc/platforms/ps3/system-bus.c
   This is a maze but I think it wants only phys and the virt is only
   used for debug prints.

The above all never touch a KVA and just want a phys_addr_t.

The below are touching the KVA somehow:

  arch/sparc/mm/iommu.c
  arch/arm/mm/dma-mapping.c
    Uses page_address to cache flush, would be happy with phys_to_virt()
    and a PhysHighMem()

  arch/powerpc/kernel/dma-iommu.c
  arch/powerpc/platforms/pseries/vio.c
   Uses iommu_map_page() which wants phys_to_virt(), doesn't touch
   struct page

  arch/powerpc/platforms/pseries/ibmebus.c
    Returns phys_to_virt() as dma_addr_t.

The two PPC ones are weird, I didn't figure out how that was working..

It would be easy to make map_phys patches for about half of these, in
the first grouping. Doing so would also grant those arches
map_resource capability.

Overall I didn't think there was any reduction in maintainability in
these places. Most are improvements eliminating code, and some are
just switching to phys_to_virt() from page_address(), which we could
further guard with DMA_ATTR_MMIO and a check for highmem.

Jason


From xen-devel-bounces@lists.xenproject.org Fri Aug 29 13:17:23 2025
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Date: Fri, 29 Aug 2025 15:17:20 +0200
From: Anthony PERARD 
To: Jason Andryuk 
Cc: xen-devel@lists.xenproject.org,
	Anthony PERARD ,
	Juergen Gross 
Subject: Re: [XEN PATCH 04/11] tools/configure: Introduce deps on json-c lib
 for libxl
Message-ID: 
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-5-anthony@xenproject.org>
 <39b2fc9e-44db-4f42-9586-1dcdac118659@amd.com>
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On Wed, Aug 27, 2025 at 11:01:59AM -0400, Jason Andryuk wrote:
> On 2025-08-08 10:55, Anthony PERARD wrote:
> > From: Anthony PERARD 
> > 
> > To replace yajl.
> > 
> > Introduce YAJL_LIBS variable, to be able to remove "-lyajl" later.
> > 
> > Signed-off-by: Anthony PERARD 
> 
> Should the two configure changes be merged and placed at the end of the
> series?  That avoids a half implemented conversion in between.

It might be half-converted, but it's fully working. Every single patch
introduce changes that can be use right away. I've actually make use of
this possibility. On every single patch, we can run ./testidl, which
will exercise both lib against each other.

./testidl does LibxlObj-to-JSONstring and back and forth. So on the next
commit, we would have JSON generated with json-c, which is then parsed
with YAJL, to finally be generated to JSON with json-c again, then both
JSON output are compared.

I've actually prepared the patch "libxl: Convert libxl__json_parse() to
use json-c' last, then put it in front and check that ./testidl was
still working.

This help me be confident enough that the conversion to json-c was
correct.

So if we squash both config change, every patch until the config change
would only introduce dead code.

Cheers,

-- 
Anthony PERARD


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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=204/9]=20hvm:=20Introduce=20"fixed=20memory=20layout"=20feature?=
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To: "Jan Beulich" 
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Le 28/08/2025 =C3=A0 14:30, Jan Beulich a =C3=A9crit=C2=A0:
> On 21.08.2025 17:25, Teddy Astie wrote:
>> @@ -686,10 +691,31 @@ static int domain_construct_memmap(libxl__gc *gc,
>>       /* We always own at least one lowmem entry. */
>>       unsigned int e820_entries =3D 1;
>>       struct e820entry *e820 =3D NULL;
>> +    uint64_t highmem_start =3D ((uint64_t)1 << 32);
>>       uint64_t highmem_size =3D
>>                       dom->highmem_end ? dom->highmem_end - (1ull << 32)=
 : 0;
>>       uint32_t lowmem_start =3D dom->device_model ? GUEST_LOW_MEM_START_=
DEFAULT : 0;
>>       unsigned page_size =3D XC_DOM_PAGE_SIZE(dom);
>> +    /* Special region starts at the first 1G boundary after the highmem=
 */
>> +    uint64_t special_region_start =3D
>> +        (highmem_start + highmem_size + GB(1) - 1) & ~(GB(1) - 1);
> 
> That is, inaccessible before entering PAE mode?
> 

Yes, I expect this to be only used by newer guests which hopefully 
aren't limited to 4G range (i.e supports PAE or long mode). The issue of 
trying to put that below 4G is that much of the space is already taken 
for the MMIO hole, so that area would quite complicated with more 
special regions.

> The open-coding of ROUNDUP() also isn't nice, but sadly unavoidable as lo=
ng
> the the macro works in terms of unsigned long.
> 
>> @@ -769,6 +805,40 @@ static int domain_construct_memmap(libxl__gc *gc,
>>           e820[nr].type =3D E820_RAM;
>>       }
>>   
>> +    /* Special regions */
>> +    if (libxl_defbool_val(d_config->b_info.arch_x86.fixed_mem_layout))
>> +    {
>> +        e820[nr].type =3D XEN_HVM_MEMMAP_TYPE_SHARED_INFO;
>> +        e820[nr].addr =3D special_region_offset;
>> +        e820[nr].size =3D page_size;
>> +        special_region_offset +=3D e820[nr].size;
>> +        nr++;
>> +
>> +        if ( gnttab_frame_count )
>> +        {
>> +            e820[nr].type =3D XEN_HVM_MEMMAP_TYPE_GRANT_TABLE;
>> +            e820[nr].addr =3D special_region_offset;
>> +            e820[nr].size =3D gnttab_frame_count * page_size;
>> +            special_region_offset +=3D e820[nr].size;
>> +            nr++;
>> +        }
>> +
>> +        if (d_config->b_info.max_grant_version >=3D 2 && gnttab_status_=
frame_count)
>> +        {
>> +            e820[nr].type =3D XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS;
>> +            e820[nr].addr =3D special_region_offset;
>> +            e820[nr].size =3D gnttab_status_frame_count * page_size;
>> +            special_region_offset +=3D e820[nr].size;
>> +            nr++;
>> +        }
>> +
>> +        e820[nr].type =3D XEN_HVM_MEMMAP_TYPE_FOREIGN_REG;
>> +        e820[nr].addr =3D special_region_offset;
>> +        e820[nr].size =3D MB(512);
> 
> Can we really know this is going to be enough for all use cases?
> 

Probably not, but we could make this area larger in the future without 
changing this ABI.

>> --- a/xen/include/public/arch-x86/hvm/start_info.h
>> +++ b/xen/include/public/arch-x86/hvm/start_info.h
>> @@ -99,6 +99,13 @@
>>   #define XEN_HVM_MEMMAP_TYPE_DISABLED  6
>>   #define XEN_HVM_MEMMAP_TYPE_PMEM      7
>>   
>> +/* Xen-specific types (OEM-specific range of the ACPI spec) */
>> +#define XEN_HVM_MEMMAP_TYPE_SHARED_INFO   0xF0000001 /* Shared info pag=
e */
>> +#define XEN_HVM_MEMMAP_TYPE_GRANT_TABLE   0xF0000002 /* Grant table pag=
es */
>> +#define XEN_HVM_MEMMAP_TYPE_GNTTAB_STATUS 0xF0000003 /* Grant table sta=
tus page (v2) */
>> +#define XEN_HVM_MEMMAP_TYPE_FOREIGN_REG   0xF0000004 /* Suitable region=
 for grant mappings */
>> +                                                     /* and foreign map=
pings */
> 
> I question it being legitimate for us to introduce new E820 types.
> 

These E820 types are (at least in ACPI specification) in the OEM-defined 
range which seems appropriate for me to use for Xen-specific mappings.

We could use reserved, but we still need a way to tell the OS what each 
of these "reserved" regions actually means (or it is gonna be ignored).

> Jan
Teddy



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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Date: Fri, 29 Aug 2025 16:42:35 +0300
MIME-Version: 1.0
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Subject: Re: [PATCH v6 1/4] xen/arm: add generic SCI subsystem
To: Oleksii Moisieiev ,
 "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Bertrand Marquis , Jan Beulich
 , Juergen Gross ,
 Julien Grall , Michal Orzel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Volodymyr Babchuk ,
 Grygorii Strashko 
References: 
 
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On 28.08.25 19:40, Oleksii Moisieiev wrote:

Hello Oleksii


> This patch adds the basic framework for ARM SCI mediator. SCI is System
> Control Interface, which is designed to redirect requests from the Domains
> to ARM specific Firmware (for example SCMI). This will allow the devices,
> passed-through to the different Domains, to access to the System resources
> (such as clocks/resets etc) by sending requests to the firmware.
> 
> ARM SCI subsystem allows to implement different SCI drivers to handle
> specific ARM firmware interfaces (like ARM SCMI) and mediate requests
> -between the Domains and the Firmware. Also it allows SCI drivers to perform
> proper action during Domain creation/destruction which is vital for
> handling use cases like Domain reboot.
> 
> This patch introduces new DEVICE_FIRMWARE device subclass for probing SCI
> drivers basing on device tree, SCI drivers register itself with
> DT_DEVICE_START/END macro. On init - the SCI drivers should register its
> SCI ops with sci_register(). Only one SCI driver can be supported.
> 
> At run-time, the following SCI API calls are introduced:
> 
> - sci_domain_sanitise_config() called from arch_sanitise_domain_config()
> - sci_domain_init() called from arch_domain_create()
> - sci_relinquish_resources() called from domain_relinquish_resources()
> - sci_domain_destroy() called from arch_domain_destroy()
> - sci_handle_call() called from vsmccc_handle_call()
> - sci_dt_handle_node()
> - sci_dt_finalize() called from handle_node() (Dom0 DT)
> 
> Signed-off-by: Oleksii Moisieiev 
> Signed-off-by: Grygorii Strashko 
> Reviewed-by: Stefano Stabellini 
> ---
> 
> Changes in v6:
> - rebase on top of the latest master
> - fix return value of sci_dt_finalize() call
> 
> Changes in v5:
> - update Maintainers file. Set role as a Reviewer
> - rebased on the latest master branch
> - Introduce arch_handle_passthrough_prop call to handle arm specific nodes
> 
> Changes in v4:
> - fix SPDX-License
> - rename DEVICE_ARM_SCI DT device class to FIRMWARE_DEVICE
> - move XEN_DOMCTL_assign_device code in separate patch
> - Add documentation for SCI SCMI drivers
> 
>   MAINTAINERS                             |   6 +
>   xen/arch/arm/device.c                   |   5 +
>   xen/arch/arm/dom0less-build.c           |   8 +
>   xen/arch/arm/domain.c                   |  12 +-
>   xen/arch/arm/domain_build.c             |   8 +
>   xen/arch/arm/firmware/Kconfig           |   8 +
>   xen/arch/arm/firmware/Makefile          |   1 +
>   xen/arch/arm/firmware/sci.c             | 154 ++++++++++++++++++
>   xen/arch/arm/include/asm/domain.h       |   5 +
>   xen/arch/arm/include/asm/firmware/sci.h | 200 ++++++++++++++++++++++++
>   xen/arch/arm/vsmc.c                     |   3 +
>   xen/common/device-tree/dom0less-build.c |   4 +
>   xen/include/asm-generic/device.h        |   1 +
>   xen/include/public/arch-arm.h           |   4 +
>   xen/include/xen/dom0less-build.h        |   9 ++
>   15 files changed, 427 insertions(+), 1 deletion(-)
>   create mode 100644 xen/arch/arm/firmware/sci.c
>   create mode 100644 xen/arch/arm/include/asm/firmware/sci.h

[snip]

> diff --git a/xen/arch/arm/include/asm/firmware/sci.h b/xen/arch/arm/include/asm/firmware/sci.h
> new file mode 100644
> index 0000000000..1b9a5c0c07
> --- /dev/null
> +++ b/xen/arch/arm/include/asm/firmware/sci.h
> @@ -0,0 +1,200 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Generic ARM SCI (System Control Interface) subsystem.
> + *
> + * Oleksii Moisieiev 
> + * Copyright (c) 2025 EPAM Systems
> + */
> +
> +#ifndef __ASM_ARM_SCI_H
> +#define __ASM_ARM_SCI_H
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 

NIT: Looks like the headers are not alphabetically sorted

[snip]

>   
> diff --git a/xen/include/xen/dom0less-build.h b/xen/include/xen/dom0less-build.h
> index 408859e325..6fdd0552e0 100644
> --- a/xen/include/xen/dom0less-build.h
> +++ b/xen/include/xen/dom0less-build.h
> @@ -62,6 +62,9 @@ void set_domain_type(struct domain *d, struct kernel_info *kinfo);
>   int init_intc_phandle(struct kernel_info *kinfo, const char *name,
>                         const int node_next, const void *pfdt);
>   
> +int arch_handle_passthrough_prop(struct kernel_info *kinfo,
> +                                 struct dt_device_node *node);
> +
>   #else /* !CONFIG_DOM0LESS_BOOT */
>   
>   static inline void create_domUs(void) {}
> @@ -71,6 +74,12 @@ static inline bool is_dom0less_mode(void)
>   }
>   static inline void set_xs_domain(struct domain *d) {}
>   
> +static inline int arch_handle_passthrough_prop(struct kernel_info *kinfo,
> +                                               struct dt_device_node *node)
> +{
> +    return 0;
> +}
> +
>   #endif /* CONFIG_DOM0LESS_BOOT */
>   
>   #endif /* __ASM_GENERIC_DOM0LESS_BUILD_H__ */


If I build current patch with # CONFIG_DOM0LESS_BOOT is not set
I got the following error:

CC      arch/arm/domain_build.o
   CC      arch/arm/guestcopy.o
In file included from arch/arm/domain_build.c:5:
./include/xen/dom0less-build.h:78:55: error: 'struct dt_device_node' 
declared inside parameter list will not be visible outside of this 
definition or declaration [-Werror]
    78 |                                                struct 
dt_device_node *node)
       | 
^~~~~~~~~~~~~~
./include/xen/dom0less-build.h:77:55: error: 'struct kernel_info' 
declared inside parameter list will not be visible outside of this 
definition or declaration [-Werror]
    77 | static inline int arch_handle_passthrough_prop(struct 
kernel_info *kinfo,
       |                                                       ^~~~~~~~~~~




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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=208/9]=20hvm:=20Introduce=20XEN=5FHVM=5FMEMMAP=5FTYPE=5FHOTPLUG=5FZONE?=
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To: "Jan Beulich" 
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Le 28/08/2025 =C3=A0 14:40, Jan Beulich a =C3=A9crit=C2=A0:
> On 21.08.2025 17:25, Teddy Astie wrote:
>> Allow specifying in memory map a region which can be hotplugged.
>>
>> This will be used by a future memory hotplug feature.
> 
> Why could this not be done the ACPI way, with the regions properly specif=
ied
> in SRAT?
> 

I am not sure whether or not ACPI mandates a specific way of doing 
memory hotplug when SRAT is advertised. But if doesn't, SRAT sounds like 
a better alternative.

> Jan
> 



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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Date: Fri, 29 Aug 2025 15:56:03 +0200
From: Anthony PERARD 
To: Jason Andryuk 
Cc: xen-devel@lists.xenproject.org,
	Anthony PERARD ,
	Juergen Gross 
Subject: Re: [XEN PATCH 06/11] libxl: convert libxl__json_object_to_yajl_gen
 to libxl__json_object_to_libjsonc_object
Message-ID: 
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-7-anthony@xenproject.org>
 <10a60455-a4d2-4c58-8a80-d8b264d27efd@amd.com>
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On Wed, Aug 27, 2025 at 11:37:07AM -0400, Jason Andryuk wrote:
> On 2025-08-08 10:55, Anthony PERARD wrote:
> > +    case JSON_NUMBER:
> > +        *jso_out = json_object_new_string(obj->u.string);
> 
> Is JSON_NUMBER calling json_object_new_string() correct?  It looks like the
> yajl code falls back to a string, so that is okay but surprising.

Yeah, I think that's correct.
:-( maybe not. Even if we have these too comments:

    In libxl_internal.h, enum libxl__json_node_type:
        /* number is store in string, it's too big to be a long long or a double */
        JSON_NUMBER  = (1 << 4),

    In json_callback_number():
        /* If the conversion fail, we just store the original string. */

With yajl, we call yajl_gen_number(), which probably write 2^128 as:

    340282366920938463463374607431768211456

but this new json-c generator would write instead:

    "340282366920938463463374607431768211456"

I guess we might be able to replicate the same behavior by using
json_object_set_serializer() or json_object_new_double_s() (which use
the former). But I don't know if it is worth the effort. I hope we won't
have int bigger than 64 bits.

And there's probably no tests for JSON_NUMBERs. So I guess first step
would be to write a test that have numbers that can't be converted to
`long long` and see what happens.

Thanks,

-- 
Anthony PERARD


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	"xen-devel@lists.xenproject.org" 
CC: Stefano Stabellini , Julien Grall
	, Bertrand Marquis , Michal Orzel
	, Volodymyr Babchuk 
Subject: Re: [PATCH v4 08/12] xen/arm: vgic: add resource management for
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Thread-Topic: [PATCH v4 08/12] xen/arm: vgic: add resource management for
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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=205/9]=20docs/x86:=20Introduce=20FastABI?=
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To: "Jan Beulich" 
Cc: "Andrew Cooper" , "Anthony PERARD" , "Michal Orzel" , "Julien Grall" , "=?utf-8?Q?Roger=20Pau=20Monn=C3=A9?=" , "Stefano Stabellini" , xen-devel@lists.xenproject.org
References:  <64800d22220f31bf052713ce61ecedeaa8a36b6f.1755785258.git.teddy.astie@vates.tech> <2fcdb264-15a3-47f7-915d-83d1c1e06765@suse.com>
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Le 28/08/2025 =C3=A0 14:35, Jan Beulich a =C3=A9crit=C2=A0:
> On 21.08.2025 17:25, Teddy Astie wrote:
>> FastABI is a alternative ABI designed with performance and coco-enabled
>> guest in mind. It is register-oriented instead of refering to C structur=
es
>> in the guest memory (through a virtual memory pointer).
>>
>> It only focuses on kernel-side hypercalls, it doesn't aim to provide too=
lstack
>> operations.
> 
> And even there it excludes certain pretty relevant ones, like many of the
> gnttabop sub-ops. As alluded to by a reply to an earlier patch, I don't
> think having an ABI for just a subset of the hypercalls is going to help.
> 

Many hypercalls are missing in current RFC, including the grant 
map/unmap ones. But a part of the idea is to still having some 
hypercalls out of scope (mainly legacy and toolstack-specific ones) to 
reduce the complexity.

> Jan
> 



Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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Subject: [PATCH] i386/xen: Advertise XEN_HVM_CPUID_EXT_DEST_ID for Xen
 guests where supported
From: David Woodhouse 
To: qemu-devel@nongnu.org
Cc: Paolo Bonzini , Marcelo Tosatti
 ,  kvm@vger.kernel.org, xen-devel
 , Roger Pau =?ISO-8859-1?Q?Monn=E9?=
 , =?ISO-8859-1?Q?J=FCrgen?= Gross 
Date: Fri, 29 Aug 2025 15:04:55 +0100
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From: David Woodhouse 

The 15-bit MSI enlightenment which allows for up to 32768 vCPUs without a
virtual IOMMU is documented at http://david.woodhou.se/ExtDestId.pdf and
has been supported for native KVM guests since QEMU v6.0.

Although Xen itself has only defined the CPUID bit and not yet implemented
it because of complexity in the interface between QEMU and Xen for MSI
handling, there's no reason why it can't work when QEMU/KVM is hosting Xen
guests. Advertise it accordingly.

Tested with a standard Linux guest (which has supported this under Xen
since v5.17) and QEMU command line including -M q35 -smp 4,maxcpus=3D288
 -device host-x86_64-cpu,socket-id=3D0,core-id=3D257,thread-id=3D0
 -cpu host,+xen-vapic

We need +xen-vapic to test it properly, or the guest turns every MSI and
I/O APIC interrupt into an event channel. Testing shows that both line
interrupts and MSIs can be set affine to the fifth CPU and are delivered
correctly.

Signed-off-by: David Woodhouse 
---
 target/i386/kvm/kvm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 369626f8c8..1401d7a903 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -2221,6 +2221,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
=20
             if (cs->kvm_state->xen_version >=3D XEN_VERSION(4, 17)) {
                 c->eax |=3D XEN_HVM_CPUID_UPCALL_VECTOR;
+                c->eax |=3D XEN_HVM_CPUID_EXT_DEST_ID;
             }
         }
=20
--=20
2.49.0



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From: "Teddy Astie" 
Subject: =?utf-8?Q?Re:=20[RFC=20PATCH=20v3=203/3]=20x86/hvm:=20Introduce=20Xen-wide=20ASID=20allocator?=
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Le 28/08/2025 =C3=A0 15:05, Jan Beulich a =C3=A9crit=C2=A0:
> On 26.06.2025 16:01, Teddy Astie wrote:
>> From: Vaishali Thakkar  (formely vates.tech)
>>
>> Currently ASID generation and management is done per-PCPU. This
>> scheme is incompatible with SEV technologies as SEV VMs need to
>> have a fixed ASID associated with all vcpus of the VM throughout
>> it's lifetime.
>>
>> This commit introduces a Xen-wide allocator which initializes
>> the asids at the start of xen and allows to have a fixed asids
>> throughout the lifecycle of all domains. Having a fixed asid
>> for non-SEV domains also presents us with the opportunity to
>> further take use of AMD instructions like TLBSYNC and INVLPGB
>> for broadcasting the TLB invalidations.
>>
>> Introduce vcpu->needs_tlb_flush attribute to schedule a guest TLB
>> flush for the next VMRUN/VMENTER. This will be later be done using
>> either TLB_CONTROL field (AMD) or INVEPT (Intel). This flush method
>> is used in place of the current ASID swapping logic.
>>
>> Signed-off-by: Teddy Astie 
>> Signed-off-by: Vaishali Thakkar  (formely vat=
es.tech)
> 
> Not sure whether you may legitimately alter pre-existing S-o-b. In
> any event the two S-o-b looks to be in the wrong order; like most
> other tags they want to be sorted chronologically.
> 

Yes, I misordered it, will fix it for the next version.

>> ---
>> CC: Oleksii Kurochko 
>>
>> Should the ASID/VPID/VMID management logic code being shared accross
>> x86/ARM/RISC-V ?
> 
> If all present and future architectures agree on how exactly they want
> to use these IDs. Which I'm unsure of. RISC-V is now vaguely following
> the original x86 model.
> 
>> Is it possible to have multiples vCPUs of a same domain simultaneously
>> scheduled on top of a single pCPU ? If so, it would need a special
>> consideration for this corner case, such as we don't miss a TLB flush
>> in such cases.
> 
> No, how would two entities be able to run on a single pCPU at any single
> point in time?
> 

It was more concerning regarding having 2 vCPUs of the same domain (thus 
sharing the same ASID) running consecutively, e.g having on the same core
   dom1.vcpu1 -> dom1.vcpu2

without a appropriate TLB flush; because the address space may not be 
consistent between 2 vCPUs.

I found a approach to fix it by tracking per domain which vCPU last ran 
on each pCPU so that in case of mismatch, we need to TLB flush. Along 
with explictely flush the TLB when the vCPU is migrated, because in the 
case too the TLB can be inconsistent for the ASID.

>> I get various stability when testing shadow paging in these patches, uns=
ure
>> what's the exact root case. HAP works perfectly fine though.
>>
>> TODO:
>> - Intel: Don't assign the VPID at each VMENTER, though we need
>>    to rethink how we manage VMCS with nested virtualization / altp2m
>>    for changing this behavior.
>> - AMD: Consider hot-plug of CPU with ERRATA_170. (is it possible ?)
>> - Consider cases where we don't have enough ASIDs (e.g Xen as nested gue=
st)
>> - Nested virtualization ASID management
> 
> For these last two points - maybe we really need a mixed model?
> 

Mixed model would not allow future support for broadcast TLB 
invalidation (even for hypervisor use) with e.g AMD INVLPGB or (future) 
Intel Remote Action Request.

>> ---
>>   xen/arch/x86/flushtlb.c                |  31 +++---
>>   xen/arch/x86/hvm/asid.c                | 148 +++++++++----------------
>>   xen/arch/x86/hvm/emulate.c             |   2 +-
>>   xen/arch/x86/hvm/hvm.c                 |  14 ++-
>>   xen/arch/x86/hvm/nestedhvm.c           |   6 +-
>>   xen/arch/x86/hvm/svm/asid.c            |  77 ++++++++-----
>>   xen/arch/x86/hvm/svm/nestedsvm.c       |   1 -
>>   xen/arch/x86/hvm/svm/svm.c             |  36 +++---
>>   xen/arch/x86/hvm/svm/svm.h             |   4 -
>>   xen/arch/x86/hvm/vmx/vmcs.c            |   5 +-
>>   xen/arch/x86/hvm/vmx/vmx.c             |  68 ++++++------
>>   xen/arch/x86/hvm/vmx/vvmx.c            |   5 +-
>>   xen/arch/x86/include/asm/flushtlb.h    |   7 --
>>   xen/arch/x86/include/asm/hvm/asid.h    |  25 ++---
>>   xen/arch/x86/include/asm/hvm/domain.h  |   1 +
>>   xen/arch/x86/include/asm/hvm/hvm.h     |  15 +--
>>   xen/arch/x86/include/asm/hvm/svm/svm.h |   5 +
>>   xen/arch/x86/include/asm/hvm/vcpu.h    |  10 +-
>>   xen/arch/x86/include/asm/hvm/vmx/vmx.h |   4 +-
>>   xen/arch/x86/mm/hap/hap.c              |   6 +-
>>   xen/arch/x86/mm/p2m.c                  |   7 +-
>>   xen/arch/x86/mm/paging.c               |   2 +-
>>   xen/arch/x86/mm/shadow/hvm.c           |   1 +
>>   xen/arch/x86/mm/shadow/multi.c         |  12 +-
>>   xen/include/xen/sched.h                |   2 +
>>   25 files changed, 227 insertions(+), 267 deletions(-)
> 
> I think I said this to Vaishali already: This really wants splitting up s=
ome,
> to become halfway reviewable.
> 

Indeed, I am looking for a approach for splitting the change without 
breaking things in-between patches.

> Jan
> 

Teddy


Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech




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Date: Fri, 29 Aug 2025 16:24:21 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jan Beulich 
Cc: "xen-devel@lists.xenproject.org" ,
	Andrew Cooper ,
	Julien Grall ,
	Stefano Stabellini ,
	Anthony PERARD ,
	Michal Orzel 
Subject: Re: [PATCH v2 1/5] symbols: add minimal self-test
Message-ID: 
References: 
 <879646dd-b55e-4b42-b637-d3b14570b880@suse.com>
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On Wed, Apr 02, 2025 at 03:57:57PM +0200, Jan Beulich wrote:
> ... before making changes to the involved logic.
> 
> Signed-off-by: Jan Beulich 
> ---
> While Andrew validly suggests cf_check isn't a requirement for selecting
> which function(s) to use (with the non-upstream gcc patch that we're
> using in CI), that's only because of how the non-upstream patch works.
> Going function-pointer -> unsigned long -> function-pointer without it
> being diagnosed that the cf_check is missing is a shortcoming there, and
> might conceivably be fixed at some point. (Imo any address-taking on a
> function should require it to be cf_check.) Hence I'd like to stick to
> using cf_check functions only for passing to test_lookup().
> 
> With this FAST_SYMBOL_LOOKUP may make sense to permit enabling even
> when LIVEPATCH=n. Thoughts? (In this case "symbols: centralize and re-
> arrange $(all_symbols) calculation" would want pulling ahead.)
> 
> --- a/xen/common/symbols.c
> +++ b/xen/common/symbols.c
> @@ -260,6 +260,41 @@ unsigned long symbols_lookup_by_name(con
>      return 0;
>  }
>  
> +#ifdef CONFIG_SELF_TESTS
> +
> +static void __init test_lookup(unsigned long addr, const char *expected)
> +{
> +    char buf[KSYM_NAME_LEN + 1];
> +    const char *name, *symname;
> +    unsigned long size, offs;
> +
> +    name = symbols_lookup(addr, &size, &offs, buf);
> +    if ( !name )
> +        panic("%s: address not found\n", expected);
> +    if ( offs )
> +        panic("%s: non-zero offset (%#lx) unexpected\n", expected, offs);

If there's a non-zero offset returned, could you also print the
returned name? (so use %s+%#lx) there's a change the returned name
doesn't match what we expect if there's a non-zero offset.

The rest LGTM:

Acked-by: Roger Pau Monné 

Thanks, Roger.


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Date: Fri, 29 Aug 2025 17:42:30 +0300
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Subject: Re: [PATCH v6 2/4] xen/arm: scmi-smc: update to be used under sci
 subsystem
To: Oleksii Moisieiev ,
 "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Bertrand Marquis , Jan Beulich
 , Juergen Gross ,
 Julien Grall , Michal Orzel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Volodymyr Babchuk ,
 Grygorii Strashko 
References: 
 <8e7e9dcdd643b6681a6127d56b68536b987141af.1756399156.git.oleksii_moisieiev@epam.com>
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From: Oleksandr Tyshchenko 
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On 28.08.25 19:40, Oleksii Moisieiev wrote:


Hello Oleksii

the patch lgtm, just some comments

> From: Grygorii Strashko 
> 
> The introduced SCI (System Control Interface) subsystem provides unified
> interface to integrate in Xen SCI drivers which adds support for ARM
> firmware (EL3, SCP) based software interfaces (like SCMI) that are used in
> system management. The SCI subsystem allows to add drivers for different FW
> interfaces or have different drivers for the same FW interface (for example,
> SCMI with different transports).
> 
> This patch updates SCMI over SMC calls handling layer, introduced by
> commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI over SMC calls handling
> layer"), to be SCI driver:
> - convert to DT device;
> - convert to SCI Xen interface.
> 
> There are no functional changes in general, the driver is just adopted
> to the SCI interface.
> 
> Signed-off-by: Grygorii Strashko 
> Reviewed-by: Stefano Stabellini 
> ---
> 
> Changes in v6:
> - add R-b tag
> 
>   xen/arch/arm/firmware/Kconfig                | 13 ++-
>   xen/arch/arm/firmware/scmi-smc.c             | 93 +++++++++++---------
>   xen/arch/arm/include/asm/firmware/scmi-smc.h | 41 ---------
>   xen/arch/arm/vsmc.c                          |  5 +-
>   xen/include/public/arch-arm.h                |  1 +
>   5 files changed, 64 insertions(+), 89 deletions(-)
>   delete mode 100644 xen/arch/arm/include/asm/firmware/scmi-smc.h
> 
> diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig
> index fc7918c7fc..bbf88fbb9a 100644
> --- a/xen/arch/arm/firmware/Kconfig
> +++ b/xen/arch/arm/firmware/Kconfig
> @@ -8,9 +8,18 @@ config ARM_SCI
>   
>   menu "Firmware Drivers"
>   
> +choice
> +	prompt "ARM SCI driver type"
> +	default SCMI_SMC
> +	help
> +	Choose which ARM SCI driver to enable.
> +
> +config ARM_SCI_NONE
> +	bool "none"
> +
>   config SCMI_SMC
>   	bool "Forward SCMI over SMC calls from hwdom to EL3 firmware"
> -	default y
> +	select ARM_SCI
>   	help
>   	  This option enables basic awareness for SCMI calls using SMC as
>   	  doorbell mechanism and Shared Memory for transport ("arm,scmi-smc"
> @@ -18,4 +27,6 @@ config SCMI_SMC
>   	  firmware node is used to trap and forward corresponding SCMI SMCs
>   	  to firmware running at EL3, for calls coming from the hardware domain.
>   
> +endchoice
> +
>   endmenu
> diff --git a/xen/arch/arm/firmware/scmi-smc.c b/xen/arch/arm/firmware/scmi-smc.c
> index 33473c04b1..13d1137592 100644
> --- a/xen/arch/arm/firmware/scmi-smc.c
> +++ b/xen/arch/arm/firmware/scmi-smc.c
> @@ -9,6 +9,7 @@
>    * Copyright 2024 NXP
>    */
>   
> +#include 

NIT: Should be included after "xen" headers
(could probably be updated on commit)

>   #include 
>   #include 
>   #include 
> @@ -16,12 +17,11 @@
>   #include 
>   #include 
>   
> +#include 
>   #include 
> -#include 
>   
>   #define SCMI_SMC_ID_PROP   "arm,smc-id"
>   
> -static bool __ro_after_init scmi_enabled;
>   static uint32_t __ro_after_init scmi_smc_id;
>   
>   /*
> @@ -41,14 +41,11 @@ static bool scmi_is_valid_smc_id(uint32_t fid)
>    *
>    * Returns true if SMC was handled (regardless of response), false otherwise.
>    */
> -bool scmi_handle_smc(struct cpu_user_regs *regs)
> +static bool scmi_handle_smc(struct cpu_user_regs *regs)
>   {
>       uint32_t fid = (uint32_t)get_user_reg(regs, 0);
>       struct arm_smccc_res res;
>   
> -    if ( !scmi_enabled )
> -        return false;
> -
>       if ( !scmi_is_valid_smc_id(fid) )
>           return false;
>   
> @@ -78,49 +75,45 @@ bool scmi_handle_smc(struct cpu_user_regs *regs)
>       return true;
>   }
>   
> -static int __init scmi_check_smccc_ver(void)
> +static int scmi_smc_domain_init(struct domain *d,
> +                                struct xen_domctl_createdomain *config)
>   {
> -    if ( smccc_ver < ARM_SMCCC_VERSION_1_1 )
> -    {
> -        printk(XENLOG_WARNING
> -               "SCMI: No SMCCC 1.1 support, SCMI calls forwarding disabled\n");
> -        return -ENOSYS;
> -    }
> +    if ( !is_hardware_domain(d) )
> +        return 0;
>   
> +    d->arch.sci_enabled = true;
> +    printk(XENLOG_DEBUG "SCMI: %pd init\n", d);
>       return 0;
>   }
>   
> -static int __init scmi_dt_init_smccc(void)
> +static void scmi_smc_domain_destroy(struct domain *d)
>   {
> -    static const struct dt_device_match scmi_ids[] __initconst =
> -    {
> -        /* We only support "arm,scmi-smc" binding for now */
> -        DT_MATCH_COMPATIBLE("arm,scmi-smc"),
> -        { /* sentinel */ },
> -    };
> -    const struct dt_device_node *scmi_node;
> -    int ret;
> +    if ( !is_hardware_domain(d) )
> +        return;
>   
> -    /* If no SCMI firmware node found, fail silently as it's not mandatory */
> -    scmi_node = dt_find_matching_node(NULL, scmi_ids);
> -    if ( !scmi_node )
> -        return -EOPNOTSUPP;
> +    printk(XENLOG_DEBUG "SCMI: %pd destroy\n", d);
> +}
>   
> -    ret = dt_property_read_u32(scmi_node, SCMI_SMC_ID_PROP, &scmi_smc_id);
> -    if ( !ret )
> +static int __init scmi_check_smccc_ver(void)
> +{
> +    if ( smccc_ver < ARM_SMCCC_VERSION_1_1 )
>       {
> -        printk(XENLOG_ERR "SCMI: No valid \"%s\" property in \"%s\" DT node\n",
> -               SCMI_SMC_ID_PROP, scmi_node->full_name);
> -        return -ENOENT;
> +        printk(XENLOG_WARNING
> +               "SCMI: No SMCCC 1.1 support, SCMI calls forwarding disabled\n");
> +        return -ENOSYS;
>       }
>   
> -    scmi_enabled = true;
> -
>       return 0;
>   }
>   
> +static const struct sci_mediator_ops scmi_smc_ops = {
> +    .handle_call = scmi_handle_smc,
> +    .domain_init = scmi_smc_domain_init,
> +    .domain_destroy = scmi_smc_domain_destroy,
> +};
> +
>   /* Initialize the SCMI layer based on SMCs and Device-tree */
> -static int __init scmi_init(void)
> +static int __init scmi_dom0_init(struct dt_device_node *dev, const void *data)
>   {
>       int ret;
>   
> @@ -134,22 +127,36 @@ static int __init scmi_init(void)
>       if ( ret )
>           return ret;
>   
> -    ret = scmi_dt_init_smccc();
> -    if ( ret == -EOPNOTSUPP )
> -        return ret;
> +    ret = dt_property_read_u32(dev, SCMI_SMC_ID_PROP, &scmi_smc_id);
> +    if ( !ret )
> +    {
> +        printk(XENLOG_ERR "SCMI: No valid \"%s\" property in \"%s\" DT node\n",
> +               SCMI_SMC_ID_PROP, dt_node_full_name(dev));
> +        return -ENOENT;
> +    }

I know that you are just moving the code, but I wonder whether it makes 
sense to validate that retrieved value at least corresponds to SiP 
Service Calls (for the future hardening)?


> +
> +    ret = sci_register(&scmi_smc_ops);
>       if ( ret )
> -        goto err;
> +    {
> +        printk(XENLOG_ERR "SCMI: mediator already registered (ret = %d)\n",
> +               ret);
> +        return ret;
> +    }
>   
>       printk(XENLOG_INFO "Using SCMI with SMC ID: 0x%x\n", scmi_smc_id);
>   
>       return 0;
> -
> - err:
> -    printk(XENLOG_ERR "SCMI: Initialization failed (ret = %d)\n", ret);
> -    return ret;
>   }
>   
> -__initcall(scmi_init);
> +static const struct dt_device_match scmi_smc_match[] __initconst = {
> +    DT_MATCH_COMPATIBLE("arm,scmi-smc"),
> +    { /* sentinel */ },
> +};
> +
> +DT_DEVICE_START(scmi_smc, "SCMI SMC DOM0", DEVICE_FIRMWARE)
> +    .dt_match = scmi_smc_match,
> +    .init = scmi_dom0_init,
> +DT_DEVICE_END
>   
>   /*
>    * Local variables:
> diff --git a/xen/arch/arm/include/asm/firmware/scmi-smc.h b/xen/arch/arm/include/asm/firmware/scmi-smc.h
> deleted file mode 100644
> index 6b1a164a40..0000000000
> --- a/xen/arch/arm/include/asm/firmware/scmi-smc.h
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-only */
> -/*
> - * xen/arch/arm/include/asm/firmware/scmi-smc.h
> - *
> - * ARM System Control and Management Interface (SCMI) over SMC
> - * Generic handling layer
> - *
> - * Andrei Cherechesu 
> - * Copyright 2024 NXP
> - */
> -
> -#ifndef __ASM_SCMI_SMC_H__
> -#define __ASM_SCMI_SMC_H__
> -
> -#include 
> -
> -struct cpu_user_regs;
> -
> -#ifdef CONFIG_SCMI_SMC
> -
> -bool scmi_handle_smc(struct cpu_user_regs *regs);
> -
> -#else
> -
> -static inline bool scmi_handle_smc(struct cpu_user_regs *regs)
> -{
> -    return false;
> -}
> -
> -#endif /* CONFIG_SCMI_SMC */
> -
> -#endif /* __ASM_SCMI_H__ */
> -
> -/*
> - * Local variables:
> - * mode: C
> - * c-file-style: "BSD"
> - * c-basic-offset: 4
> - * indent-tabs-mode: nil
> - * End:
> - */
> diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c
> index 2469738fcc..78d5bdf56f 100644
> --- a/xen/arch/arm/vsmc.c
> +++ b/xen/arch/arm/vsmc.c
> @@ -21,7 +21,6 @@
>   #include 
>   #include 
>   #include 
> -#include 
>   
>   /* Number of functions currently supported by Hypervisor Service. */
>   #define XEN_SMCCC_FUNCTION_COUNT 3
> @@ -233,7 +232,7 @@ static bool handle_sip(struct cpu_user_regs *regs)
>       if ( platform_smc(regs) )
>           return true;
>   
> -    return scmi_handle_smc(regs);
> +    return sci_handle_call(regs);
>   }
>   
>   /*
> @@ -301,8 +300,6 @@ static bool vsmccc_handle_call(struct cpu_user_regs *regs)
>               break;
>           case ARM_SMCCC_OWNER_SIP:
>               handled = handle_sip(regs);
> -            if ( !handled )
> -                handled = sci_handle_call(regs);

These two lines where added by [PATCH v6 1/4] xen/arm: add generic SCI 
subsystem, but here they are removed. This is not a request for an extra 
work right now, but ideally the series should be splitted without an 
extra temporarily changes.

>               break;
>           case ARM_SMCCC_OWNER_TRUSTED_APP ... ARM_SMCCC_OWNER_TRUSTED_APP_END:
>           case ARM_SMCCC_OWNER_TRUSTED_OS ... ARM_SMCCC_OWNER_TRUSTED_OS_END:
> diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
> index 55eed9992c..095b1a23e3 100644
> --- a/xen/include/public/arch-arm.h
> +++ b/xen/include/public/arch-arm.h
> @@ -328,6 +328,7 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
>   #define XEN_DOMCTL_CONFIG_TEE_FFA       2
>   
>   #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE      0
> +#define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC  1
>   
>   struct xen_arch_domainconfig {
>       /* IN/OUT */



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Date: Fri, 29 Aug 2025 17:02:22 +0200
From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jason Andryuk 
Cc: Jan Beulich ,
	"xen-devel@lists.xenproject.org" ,
	Andrew Cooper ,
	Julien Grall ,
	Stefano Stabellini ,
	Anthony PERARD ,
	Michal Orzel ,
	Bertrand Marquis ,
	Volodymyr Babchuk 
Subject: Re: [PATCH v2 4/5] symbols: centralize and re-arrange $(all_symbols)
 calculation
Message-ID: 
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 <5a77bb51-22d1-4956-8e45-c2412c413766@suse.com>
 
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On Wed, Aug 27, 2025 at 09:05:59PM -0400, Jason Andryuk wrote:
> On 2025-04-02 09:59, Jan Beulich wrote:
> > For one there's no need for each architecture to have the same logic.
> > Move to the root Makefile, also to calculate just once.
> > 
> > And then re-arrange to permit FAST_SYMBOL_LOOKUP to be independent of
> > LIVEPATCH, which may be useful in (at least) debugging.
> > 
> > Signed-off-by: Jan Beulich 
> 
> Reviewed-by: Jason Andryuk 

Reviewed-by: Roger Pau Monné 

Thanks.


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From: Roger Pau =?utf-8?B?TW9ubsOp?= 
To: Jason Andryuk 
Cc: Jan Beulich ,
	"xen-devel@lists.xenproject.org" ,
	Andrew Cooper ,
	Julien Grall ,
	Stefano Stabellini ,
	Anthony PERARD ,
	Michal Orzel 
Subject: Re: [PATCH v2 5/5] symbols: prefer symbols which have a type
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On Wed, Aug 27, 2025 at 09:07:50PM -0400, Jason Andryuk wrote:
> On 2025-04-02 10:00, Jan Beulich wrote:
> > ... and thus typically also a size. Using global vs local is undesirable
> > in certain situations, e.g. when a "real" symbol is local and at the
> > same address as a section start/end one (which are all global).
> > 
> > Note that for xen.efi the checking for "Function" is only forward-
> > looking at this point: The function-ness of symbols (much like their
> > size) is lost when linking PE/COFF binaries from ELF objects with GNU ld
> > up to at least 2.44.
> > 
> > Signed-off-by: Jan Beulich 
> 
> Reviewed-by: Jason Andryuk 

Reviewed-by: Roger Pau Monné 

Thanks, Roger.


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Date: Fri, 29 Aug 2025 17:32:54 +0200
From: Anthony PERARD 
To: Andrew Cooper 
Cc: Jason Andryuk , xen-devel@lists.xenproject.org,
	Anthony PERARD ,
	Juergen Gross 
Subject: Re: [XEN PATCH 07/11] libxl: libxl__object_to_json() to json-c
Message-ID: 
References: <20250808145602.41716-1-anthony@xenproject.org>
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On Wed, Aug 27, 2025 at 06:59:14PM +0100, Andrew Cooper wrote:
> On 27/08/2025 6:51 pm, Jason Andryuk wrote:
> > On 2025-08-08 10:55, Anthony PERARD wrote:
> >> From: Anthony PERARD 
> >>
> >> - libxl changes:
> >>
> >> While doing so, we rename all "*_gen_json" function to "*_gen_jso" as
> >> they have different prototype. All the function pointer are been cast
> >> to (libxl__gen_json_callback) by "gentypes.py" when generating
> >> "*_to_json()" functions.
> >>
> >> We also introduce a few more "*_gen_jso" functions for "int" and
> >> "bool" because we can't use json_object_*() functions from json-c
> >> directly like it's done with yajl.
> >>
> >> To make the generation of _libxl_types*json.[ch] with both YAJL and
> >> json-c we add "--libjsonc" to gentypes.py so it can generate
> >> functions/types for both.
> >>
> >> Also introducing "jsonc_json_gen_fn" in the IDL, to be able to point
> >> to a different function when using json-c.
> >>
> >> Also, don't export any of the new *_gen_jso() function, at the cost of
> >> having "_hidden" macro in semi-public headers.
> >>
> >> - xl changes:
> >>
> >> Also, rework the implementation of printf_info() in `xl` to avoid
> >> using libxl_domain_config_gen_json() which isn't available without
> >> YAJL. The implementation using "json_object" call
> >> libxl_domain_config_to_json() which generate a plain string of JSON,
> >> which we parse to add it to our own json; this avoid a dependency on
> >> the json library used by libxl.
> >>
> >> Signed-off-by: Anthony PERARD 
> >
> >> @@ -358,6 +535,36 @@ int libxl__mac_parse_json(libxl__gc *gc, const
> >> libxl__json_object *o,
> >>       return libxl__parse_mac(libxl__json_object_get_string(o), *p);
> >>   }
> >>   +#ifdef HAVE_LIBJSONC
> >> +int libxl_hwcap_gen_jso(json_object **jso_r, libxl_hwcap *p)
> >> +{
> >> +    json_object *jso;
> >> +    int i;
> >> +    int rc = ERROR_FAIL;
> >> +
> >> +    jso = json_object_new_array();
> >> +    if (!jso) goto out;
> >> +
> >> +    for(i=0; i<4; i++) {
> >
> > typedef uint32_t libxl_hwcap[8];
> >
> > I see this is the same as the yajl implementation, but should this be 8?

Yeah, looks like it should be ARRAY_SIZE(p). But that would want fixing
in a different patch. And since no one complained about missing bits in
this json conversion, I guess it's not used.

We would need to also fix libxl__hwcap_parse_json(), to parse up to 8
items, and be able to deal with missing 4 of them.

> >
> > The remainder looks good:
> >
> > Reviewed-by: Jason Andryuk 
> 
> A tangent, but physinfo.hw_cap (which libxl_hwcap wraps) is as good as
> stack rubble.  It's not exactly random data, but it is a view of an
> internal Xen structure which has been reformatted multiple times before
> we even realised it was exported, then continued being reformatting it
> because it's a gross laying violation that noone could possibly be using
> anyway.

It's display in `xl info`, surely it's useful for someone :-), a long
long time ago since it seems to be inherited from `xm info`.

> It needs purging from libxl and the sysctl interface, and if that makes
> JSON easier, then lets get it done.

It would be more work, not less. Removing things from libxl's api is
annoying. But I guess we can look at removing that later.

Cheers,


-- 
Anthony PERARD


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Subject: [PATCH v5 03/12] xen/arm: vgic: implement helper functions for virq
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Thread-Topic: [PATCH v5 03/12] xen/arm: vgic: implement helper functions for
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Introduced two new helper functions for vGIC: vgic_is_valid_line and
vgic_is_spi. The functions are similar to the newly introduced
gic_is_valid_line and gic_is_spi, but they verify whether a vIRQ
is available for a specific domain, while GIC-specific functions
validate INTIDs for the real GIC hardware. For example, the GIC may
support all 992 SPI lines, but the domain may use only some part of them
(e.g., 640), depending on the highest IRQ number defined in the domain
configuration. Therefore, for vGIC-related code and checks, the
appropriate functions should be used. Also, updated the appropriate
checks to use these new helper functions.

The purpose of introducing new helper functions for vGIC is essentially
the same as for GIC: to avoid potential confusion with GIC-related
checks and to consolidate similar code into separate functions, which
can be more easily extended by additional conditions, e.g., when
implementing extended SPI interrupts.

Only the validation change in vgic_inject_irq may affect existing
functionality, as it currently checks whether the vIRQ is less than or
equal to vgic_num_irqs. Since IRQ indexes start from 0 (where 32 is the
first SPI), the check should behave consistently with similar logic in
other places and should check if the vIRQ number is less than
vgic_num_irqs. The remaining changes, which replace open-coded checks
with the use of these new helper functions, do not introduce any
functional changes, as the helper functions follow the current vIRQ
index verification logic.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Oleksandr Tyshchenko 
Reviewed-by: Volodymyr Babchuk 
Acked-by: Julien Grall 

---
Changes in V5:
- added reviewed-by from Oleksandr Tyshchenko and from Volodymyr Babchuk
- added acked-by from Julien Grall

Changes in V4:
- removed redundant parentheses

Changes in V3:
- renamed vgic_is_valid_irq to vgic_is_valid_line and vgic_is_shared_irq
  to vgic_is_spi
- added vgic_is_valid_line implementation for new-vgic, because
  vgic_is_valid_line is called from generic code. It is necessary to fix
  the build for new-vgic.
- updated commit message

Changes in V2:
- introduced this patch
---
 xen/arch/arm/gic.c              |  3 +--
 xen/arch/arm/include/asm/vgic.h |  7 +++++++
 xen/arch/arm/irq.c              |  4 ++--
 xen/arch/arm/vgic.c             | 10 ++++++++--
 xen/arch/arm/vgic/vgic.c        |  5 +++++
 5 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 4bb11960ee..9469c9d08c 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -134,8 +134,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned i=
nt virq,
=20
     ASSERT(spin_is_locked(&desc->lock));
     /* Caller has already checked that the IRQ is an SPI */
-    ASSERT(virq >=3D 32);
-    ASSERT(virq < vgic_num_irqs(d));
+    ASSERT(vgic_is_spi(d, virq));
     ASSERT(!is_lpi(virq));
=20
     ret =3D vgic_connect_hw_irq(d, NULL, virq, desc, true);
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 35c0c6a8b0..3e7cbbb196 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -335,6 +335,13 @@ extern void vgic_check_inflight_irqs_pending(struct vc=
pu *v,
 /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
 #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
=20
+extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
+
+static inline bool vgic_is_spi(struct domain *d, unsigned int virq)
+{
+    return virq >=3D NR_LOCAL_IRQS && vgic_is_valid_line(d, virq);
+}
+
 /*
  * Allocate a guest VIRQ
  *  - spi =3D=3D 0 =3D> allocate a PPI. It will be the same on every vCPU
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 7dd5a2a453..b8eccfc924 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -442,7 +442,7 @@ int route_irq_to_guest(struct domain *d, unsigned int v=
irq,
     unsigned long flags;
     int retval =3D 0;
=20
-    if ( virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_valid_line(d, virq) )
     {
         printk(XENLOG_G_ERR
                "the vIRQ number %u is too high for domain %u (max =3D %u)\=
n",
@@ -560,7 +560,7 @@ int release_guest_irq(struct domain *d, unsigned int vi=
rq)
     int ret;
=20
     /* Only SPIs are supported */
-    if ( virq < NR_LOCAL_IRQS || virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_spi(d, virq) )
         return -EINVAL;
=20
     desc =3D vgic_get_hw_irq_desc(d, NULL, virq);
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index c563ba93af..2bbf4d99aa 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -24,6 +24,12 @@
 #include 
 #include 
=20
+
+bool vgic_is_valid_line(struct domain *d, unsigned int virq)
+{
+    return virq < vgic_num_irqs(d);
+}
+
 static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
                                                   unsigned int rank)
 {
@@ -582,7 +588,7 @@ void vgic_inject_irq(struct domain *d, struct vcpu *v, =
unsigned int virq,
     if ( !v )
     {
         /* The IRQ needs to be an SPI if no vCPU is specified. */
-        ASSERT(virq >=3D 32 && virq <=3D vgic_num_irqs(d));
+        ASSERT(vgic_is_spi(d, virq));
=20
         v =3D vgic_get_target_vcpu(d->vcpu[0], virq);
     };
@@ -659,7 +665,7 @@ bool vgic_emulate(struct cpu_user_regs *regs, union hsr=
 hsr)
=20
 bool vgic_reserve_virq(struct domain *d, unsigned int virq)
 {
-    if ( virq >=3D vgic_num_irqs(d) )
+    if ( !vgic_is_valid_line(d, virq) )
         return false;
=20
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index 6cabd0496d..b2c0e1873a 100644
--- a/xen/arch/arm/vgic/vgic.c
+++ b/xen/arch/arm/vgic/vgic.c
@@ -718,6 +718,11 @@ bool vgic_reserve_virq(struct domain *d, unsigned int =
virq)
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
 }
=20
+bool vgic_is_valid_line(struct domain *d, unsigned int virq)
+{
+    return virq < vgic_num_irqs(d);
+}
+
 int vgic_allocate_virq(struct domain *d, bool spi)
 {
     int first, end;
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk ,
	Julien Grall 
Subject: [PATCH v5 02/12] xen/arm: gic: implement helper functions for INTID
 checks
Thread-Topic: [PATCH v5 02/12] xen/arm: gic: implement helper functions for
 INTID checks
Thread-Index: AQHcGP7XgADFYzc0NU2aQr9cJjulKw==
Date: Fri, 29 Aug 2025 16:06:13 +0000
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Introduced two new helper functions: gic_is_valid_line and
gic_is_spi. The first function helps determine whether an IRQ
number is less than the number of lines supported by hardware. The
second function additionally checks if the IRQ number falls within the
SPI range. Also, updated the appropriate checks to use these new helper
functions.

The current checks for the real GIC are very similar to those for the
vGIC but serve a different purpose. For GIC-related code, the interrupt
numbers should be validated based on whether the hardware can operate
with such interrupts. On the other hand, for the vGIC, the indexes must
also be verified to ensure they are available for a specific domain. The
first reason for introducing these helper functions is to avoid
potential confusion with vGIC-related checks. The second reason is to
consolidate similar code into separate functions, which can be more
easily extended by additional conditions, e.g., when implementing
extended SPI interrupts.

The changes, which replace open-coded checks with the use of the new
helper functions, do not introduce any functional changes, as the helper
functions follow the current IRQ index verification logic.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 
Acked-by: Julien Grall 

---
Changes in V5:
- fixed a minor nit: moved the existing comment to the line above to fix
  formatting that exceeded 80 characters
- added acked-by from Julien Grall

Changes in V4:
- removed redundant parentheses
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- renamed gic_is_valid_irq to gic_is_valid_line and gic_is_shared_irq to
  gic_is_spi
- updated commit message

Changes in V2:
- introduced this patch

Changes for V4:

Changes in V4:
- removed redundant parentheses
- added reviewed-by from Volodymyr Babchuk
---
 xen/arch/arm/gic.c             | 3 ++-
 xen/arch/arm/include/asm/gic.h | 9 +++++++++
 xen/arch/arm/irq.c             | 2 +-
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index e80fe0ca24..4bb11960ee 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -111,7 +111,8 @@ static void gic_set_irq_priority(struct irq_desc *desc,=
 unsigned int priority)
 void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority)
 {
     ASSERT(priority <=3D 0xff);     /* Only 8 bits of priority */
-    ASSERT(desc->irq < gic_number_lines());/* Can't route interrupts that =
don't exist */
+    /* Can't route interrupts that don't exist */
+    ASSERT(gic_is_valid_line(desc->irq));
     ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
     ASSERT(spin_is_locked(&desc->lock));
=20
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.=
h
index 541f0eeb80..3fcee42675 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -306,6 +306,15 @@ extern void gic_dump_vgic_info(struct vcpu *v);
=20
 /* Number of interrupt lines */
 extern unsigned int gic_number_lines(void);
+static inline bool gic_is_valid_line(unsigned int irq)
+{
+    return irq < gic_number_lines();
+}
+
+static inline bool gic_is_spi(unsigned int irq)
+{
+    return irq >=3D NR_LOCAL_IRQS && gic_is_valid_line(irq);
+}
=20
 /* IRQ translation function for the device tree */
 int gic_irq_xlate(const u32 *intspec, unsigned int intsize,
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index 03fbb90c6c..7dd5a2a453 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -415,7 +415,7 @@ err:
 bool is_assignable_irq(unsigned int irq)
 {
     /* For now, we can only route SPIs to the guest */
-    return (irq >=3D NR_LOCAL_IRQS) && (irq < gic_number_lines());
+    return gic_is_spi(irq);
 }
=20
 /*
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Anthony PERARD ,
	Oleksii Kurochko , Community Manager
	
Subject: [PATCH v5 00/12] Introduce eSPI support
Thread-Topic: [PATCH v5 00/12] Introduce eSPI support
Thread-Index: AQHcGP7UQBYvhtVNRUaCLipIubV2Ig==
Date: Fri, 29 Aug 2025 16:06:07 +0000
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Hello everyone!

This is V5 of the patch series to introduce eSPI support, which contains
fixes and improvements based on the comments received in V4.

The main changes in this version compared to V4 are related to removing
unnecessary #ifdefs that previously prevented the use of certain defines
and macros, leading to an overuse of #ifdefs. After refactoring, it is
now possible to reuse the existing code for vGIC eSPI emulation, which
improves readability and simplifies future changes. As some patches that
had already been reviewed were modified, I would ask Volodymyr and
Oleksandr to take a look at the updated versions of:

[4/12] xen/arm/irq: add handling for IRQs in the eSPI range
[5/12] xen/arm: gicv3: implement handling of GICv3.1 eSPI

The changes made in these patches allowed me to significantly simplify
the following patch:

[10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers

For the other patches, I have addressed comments and added reviewed-by
or acked-by tags accordingly, based on the received comments.

Summarized description:
This patch series adds support for the extended shared peripheral
interrupt (eSPI) range (INTIDs 4096-5119 [2](ranges of INTIDs)) for Xen
and guest domains. The implementation uses a generic approach to handle
eSPIs, similar to regular SPIs, while maintaining compatibility with the
existing SPI range. Functionality remains unchanged for setups that do
not require eSPIs.

The series includes:
1) General refactoring of common IRQ operations with GIC registers to
improve code readability, simplify further maintenance and prepare the
key functions for eSPI implementation.
2) Introducing a new Kconfig option (default n) to enable or disable
eSPI support. Disabling this option prevents unnecessary resource
allocation for setups that do not require eSPIs.
3) Adding additional resources to store required information and operate
with up to 1024 interrupts from eSPI range.
4) Adjusting assertions and checks to pass verification for INTIDs in
the eSPI range.
5) Configuration of eSPI-specific registers during GIC initialization
for systems with GICv3.1+ hardware.
6) Enables eSPI MMIO emulation for vGIC, allowing guest domains to
access and operate within the eSPI's INTIDs.
7) Updating documentation and CHANGELOG to reflect the changes made for eSP=
I
support.

Also, to simplify reviewing, please find below link to unsquashed patches, =
that
are on top of every patch, that is changed in the series, compared to V4:
https://github.com/LKomaryanskiy/xen/commits/espi-support-master-upstream-v=
5-unsquashed/


Changes in V5:
- individual changes in patches

Link on V4:
- https://lists.xenproject.org/archives/html/xen-devel/2025-08/msg01767.htm=
l

Changes in V4:
- added a patch for documentation
- individual changes in patches

Link on V3:
- https://lists.xenproject.org/archives/html/xen-devel/2025-08/msg01628.htm=
l

Changes in V3:
- added a patch to update CHANGELOG.md
- individual changes in patches

Link on V2:
- https://lists.xenproject.org/archives/html/xen-devel/2025-08/msg00372.htm=
l

Changes in V2:
- added 2 more patches to implement helper
  functions for gic/vgic:
  xen/arm: gic: implement helper functions for INTID checks
  xen/arm: vgic: implement helper functions for virq checks
- removed 2 patches:
  xen/arm/irq: allow assignment/releasing of eSPI interrupts
  xen/arm: gic/irq: permit routing of eSPI interrupts to Xen and domains
  since their functionality can be moved to appropriate patches after
  introducing patches with helper functions
- individual changes in patches

Link on V1:
- https://lists.xenproject.org/archives/html/xen-devel/2025-07/msg01809.htm=
l

Leonid Komarianskyi (12):
  xen/arm: gicv3: refactor obtaining GIC addresses for common operations
  xen/arm: gic: implement helper functions for INTID checks
  xen/arm: vgic: implement helper functions for virq checks
  xen/arm/irq: add handling for IRQs in the eSPI range
  xen/arm: gicv3: implement handling of GICv3.1 eSPI
  xen/arm/irq: allow eSPI processing in the gic_interrupt function
  xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow eSPI processing
  xen/arm: vgic: add resource management for extended SPIs
  xen/arm: domain_build/dom0less-build: adjust domains config to support
    eSPIs
  xen/arm: vgic-v3: add emulation of GICv3.1 eSPI registers
  doc/man: update description for nr_spis with eSPI
  CHANGELOG.md: add mention of GICv3.1 eSPI support

 CHANGELOG.md                           |   2 +
 docs/man/xl.cfg.5.pod.in               |  13 +-
 xen/arch/arm/Kconfig                   |   8 +
 xen/arch/arm/dom0less-build.c          |   2 +-
 xen/arch/arm/domain_build.c            |   2 +-
 xen/arch/arm/gic-v3.c                  | 195 +++++++++++++++++----
 xen/arch/arm/gic.c                     |   8 +-
 xen/arch/arm/include/asm/gic.h         |  31 ++++
 xen/arch/arm/include/asm/gic_v3_defs.h |  40 ++++-
 xen/arch/arm/include/asm/irq.h         |  25 +++
 xen/arch/arm/include/asm/vgic.h        |  42 +++++
 xen/arch/arm/irq.c                     |  62 ++++++-
 xen/arch/arm/vgic-v3.c                 | 198 +++++++++++++++++----
 xen/arch/arm/vgic.c                    | 232 ++++++++++++++++++++++++-
 xen/arch/arm/vgic/vgic.c               |   5 +
 15 files changed, 778 insertions(+), 87 deletions(-)

--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v5 04/12] xen/arm/irq: add handling for IRQs in the eSPI range
Thread-Topic: [PATCH v5 04/12] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcGP7bBiDA5fxWR0+DupelLQbe9w==
Date: Fri, 29 Aug 2025 16:06:19 +0000
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Currently, Xen does not support eSPI interrupts, leading
to a data abort when such interrupts are defined in the DTS.

This patch introduces a separate array to initialize up to
1024 interrupt descriptors in the eSPI range and adds the
necessary defines and helper function. These changes lay the
groundwork for future implementation of full eSPI interrupt
support. As this GICv3.1 feature is not required by all vendors,
all changes are guarded by ifdefs, depending on the corresponding
Kconfig option.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V5:
- no functional changes introduced by this version compared with V4, only
  minor fixes and removal of ifdefs for macroses
- added TODO comment, suggested by Oleksandr Tyshchenko
- changed int to unsigned int for irqs
- removed ifdefs for eSPI-specific defines and macros to reduce the
  number of ifdefs and code duplication in further changes
- removed reviewed-by as moving defines from ifdefs requires additional
  confirmation from reviewers

Changes in V4:
- removed redundant line with 'default n' in Kconfig, as it is disabled
  by default, without explicit specification
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- introduced a new define NR_ESPI_IRQS to avoid confusion, like in the
  case of using NR_IRQS for espi_desc array
- implemented helper functions espi_to_desc and init_espi_data to make
  it possible to add stubs with the same name, and as a result, reduce
  the number of #ifdefs
- disable CONFIG_GICV3_ESPI default value to n

Changes in V2:
- use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
- remove unnecessary comment for nr_irqs initialization
---
 xen/arch/arm/Kconfig           |  8 +++++
 xen/arch/arm/include/asm/irq.h | 24 +++++++++++++++
 xen/arch/arm/irq.c             | 56 +++++++++++++++++++++++++++++++++-
 3 files changed, 87 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 17df147b25..43b05533b1 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -135,6 +135,14 @@ config GICV3
 	  Driver for the ARM Generic Interrupt Controller v3.
 	  If unsure, use the default setting.
=20
+config GICV3_ESPI
+	bool "Extended SPI range support"
+	depends on GICV3 && !NEW_VGIC
+	help
+	  Allow Xen and domains to use interrupt numbers from the extended SPI
+	  range, from 4096 to 5119. This feature is introduced in GICv3.1
+	  architecture.
+
 config HAS_ITS
         bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORT=
ED
         depends on GICV3 && !NEW_VGIC && !ARM_32
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.=
h
index 5bc6475eb4..4443799648 100644
--- a/xen/arch/arm/include/asm/irq.h
+++ b/xen/arch/arm/include/asm/irq.h
@@ -32,6 +32,13 @@ struct arch_irq_desc {
 #define SPI_MAX_INTID   1019
 #define LPI_OFFSET      8192
=20
+#define ESPI_BASE_INTID 4096
+#define ESPI_MAX_INTID  5119
+#define NR_ESPI_IRQS    1024
+
+#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
+#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
+
 /* LPIs are always numbered starting at 8192, so 0 is a good invalid case.=
 */
 #define INVALID_LPI     0
=20
@@ -39,7 +46,15 @@ struct arch_irq_desc {
 #define INVALID_IRQ     1023
=20
 extern const unsigned int nr_irqs;
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * This will also cover the eSPI range, as some critical devices
+ * for booting Xen (e.g., serial) may use this type of interrupts.
+ */
+#define nr_static_irqs (ESPI_MAX_INTID + 1)
+#else
 #define nr_static_irqs NR_IRQS
+#endif
=20
 struct irq_desc;
 struct irqaction;
@@ -55,6 +70,15 @@ static inline bool is_lpi(unsigned int irq)
     return irq >=3D LPI_OFFSET;
 }
=20
+static inline bool is_espi(unsigned int irq)
+{
+#ifdef CONFIG_GICV3_ESPI
+    return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID);
+#else
+    return false;
+#endif
+}
+
 #define domain_pirq_to_irq(d, pirq) (pirq)
=20
 bool is_assignable_irq(unsigned int irq);
diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
index b8eccfc924..61c915c3f9 100644
--- a/xen/arch/arm/irq.c
+++ b/xen/arch/arm/irq.c
@@ -19,7 +19,11 @@
 #include 
 #include 
=20
+#ifdef CONFIG_GICV3_ESPI
+const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1;
+#else
 const unsigned int nr_irqs =3D NR_IRQS;
+#endif
=20
 static unsigned int local_irqs_type[NR_LOCAL_IRQS];
 static DEFINE_SPINLOCK(local_irqs_type_lock);
@@ -46,6 +50,53 @@ void irq_end_none(struct irq_desc *irq)
 }
=20
 static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * TODO: Consider allocating an array dynamically if
+ * there is a need to enable GICV3_ESPI by default.
+ */
+static irq_desc_t espi_desc[NR_ESPI_IRQS];
+
+static struct irq_desc *espi_to_desc(unsigned int irq)
+{
+    return &espi_desc[ESPI_INTID2IDX(irq)];
+}
+
+static int __init init_espi_data(void)
+{
+    unsigned int irq;
+
+    for ( irq =3D ESPI_BASE_INTID; irq <=3D ESPI_MAX_INTID; irq++ )
+    {
+        struct irq_desc *desc =3D irq_to_desc(irq);
+        int rc =3D init_one_irq_desc(desc);
+
+        if ( rc )
+            return rc;
+
+        desc->irq =3D irq;
+        desc->action  =3D NULL;
+    }
+
+    return 0;
+}
+#else
+/*
+ * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn,
+ * because in this case, is_espi will always return false.
+ */
+static struct irq_desc *espi_to_desc(unsigned int irq)
+{
+    ASSERT_UNREACHABLE();
+    return NULL;
+}
+
+static int __init init_espi_data(void)
+{
+    return 0;
+}
+#endif
+
 static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc);
=20
 struct irq_desc *__irq_to_desc(unsigned int irq)
@@ -53,6 +104,9 @@ struct irq_desc *__irq_to_desc(unsigned int irq)
     if ( irq < NR_LOCAL_IRQS )
         return &this_cpu(local_irq_desc)[irq];
=20
+    if ( is_espi(irq) )
+        return espi_to_desc(irq);
+
     return &irq_desc[irq-NR_LOCAL_IRQS];
 }
=20
@@ -79,7 +133,7 @@ static int __init init_irq_data(void)
         desc->action  =3D NULL;
     }
=20
-    return 0;
+    return init_espi_data();
 }
=20
 static int init_local_irq_data(unsigned int cpu)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk ,
	Julien Grall 
Subject: [PATCH v5 01/12] xen/arm: gicv3: refactor obtaining GIC addresses for
 common operations
Thread-Topic: [PATCH v5 01/12] xen/arm: gicv3: refactor obtaining GIC
 addresses for common operations
Thread-Index: AQHcGP7VA43rYFd/50W5xNx+fBJnNg==
Date: Fri, 29 Aug 2025 16:06:10 +0000
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 <7da58b5a27d61f75eaebb749a7ab4c72655a12cb.1756481577.git.leonid_komarianskyi@epam.com>
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Currently, many common functions perform the same operations to calculate
GIC register addresses. This patch consolidates the similar code into
a separate helper function to improve maintainability and reduce duplicatio=
n.
This refactoring also simplifies the implementation of eSPI support in futu=
re
changes.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 
Acked-by: Julien Grall 

---
Changes in V5:
- fixed a minor nit: changed %d to %u in the warning message because the
  IRQ number cannot be less than zero
- added acked-by from Julien Grall

Changes in V4:
- no changes

Changes in V3:
- changed panic() in get_addr_by_offset() to printing warning and
  ASSERT_UNREACHABLE()
- added verification of return pointer from get_addr_by_offset() in the
  callers
- moved invocation of get_addr_by_offset() from spinlock guards, since
  it is not necessarry
- added RB from Volodymyr Babchuk

Changes in V2:
- no changes
---
 xen/arch/arm/gic-v3.c          | 114 +++++++++++++++++++++++----------
 xen/arch/arm/include/asm/irq.h |   1 +
 2 files changed, 81 insertions(+), 34 deletions(-)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index cd3e1acf79..29b7f68cba 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -445,17 +445,67 @@ static void gicv3_dump_state(const struct vcpu *v)
     }
 }
=20
+static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
+{
+    switch ( irqd->irq )
+    {
+    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+        case GICD_ICENABLER:
+        case GICD_ISPENDR:
+        case GICD_ICPENDR:
+        case GICD_ISACTIVER:
+        case GICD_ICACTIVER:
+            return (GICD_RDIST_SGI_BASE + offset);
+        case GICD_ICFGR:
+            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
+        case GICD_IPRIORITYR:
+            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
+        default:
+            break;
+        }
+    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+        case GICD_ICENABLER:
+        case GICD_ISPENDR:
+        case GICD_ICPENDR:
+        case GICD_ISACTIVER:
+        case GICD_ICACTIVER:
+            return (GICD + offset + (irqd->irq / 32) * 4);
+        case GICD_ICFGR:
+            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
+        case GICD_IROUTER:
+            return (GICD + GICD_IROUTER + irqd->irq * 8);
+        case GICD_IPRIORITYR:
+            return (GICD + GICD_IPRIORITYR + irqd->irq);
+        default:
+            break;
+        }
+    default:
+        break;
+    }
+
+    /* Something went wrong, we shouldn't be able to reach here */
+    printk(XENLOG_WARNING "GICv3: WARNING: Invalid offset 0x%x for IRQ#%u"=
,
+           offset, irqd->irq);
+    ASSERT_UNREACHABLE();
+
+    return NULL;
+}
+
 static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_fo=
r_rwp)
 {
     u32 mask =3D 1U << (irqd->irq % 32);
-    void __iomem *base;
+    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
=20
-    if ( irqd->irq < NR_GIC_LOCAL_IRQS )
-        base =3D GICD_RDIST_SGI_BASE;
-    else
-        base =3D GICD;
+    if ( addr =3D=3D NULL )
+        return;
=20
-    writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
+    writel_relaxed(mask, addr);
=20
     if ( wait_for_rwp )
         gicv3_wait_for_rwp(irqd->irq);
@@ -463,15 +513,12 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u32=
 offset, bool wait_for_rwp)
=20
 static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset)
 {
-    void __iomem *base;
-    unsigned int irq =3D irqd->irq;
+    void __iomem *addr =3D get_addr_by_offset(irqd, offset);
=20
-    if ( irq >=3D NR_GIC_LOCAL_IRQS)
-        base =3D GICD + (irq / 32) * 4;
-    else
-        base =3D GICD_RDIST_SGI_BASE;
+    if ( addr =3D=3D NULL )
+        return false;
=20
-    return !!(readl(base + offset) & (1U << (irq % 32)));
+    return !!(readl(addr) & (1U << (irqd->irq % 32)));
 }
=20
 static void gicv3_unmask_irq(struct irq_desc *irqd)
@@ -558,30 +605,28 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cp=
u)
 static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type)
 {
     uint32_t cfg, actual, edgebit;
-    void __iomem *base;
-    unsigned int irq =3D desc->irq;
+    void __iomem *addr;
=20
     /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
-    ASSERT(irq >=3D NR_GIC_SGI);
+    ASSERT(desc->irq >=3D NR_GIC_SGI);
=20
-    spin_lock(&gicv3.lock);
+    addr =3D get_addr_by_offset(desc, GICD_ICFGR);
+    if ( addr =3D=3D NULL )
+        return;
=20
-    if ( irq >=3D NR_GIC_LOCAL_IRQS)
-        base =3D GICD + GICD_ICFGR + (irq / 16) * 4;
-    else
-        base =3D GICD_RDIST_SGI_BASE + GICR_ICFGR1;
+    spin_lock(&gicv3.lock);
=20
-    cfg =3D readl_relaxed(base);
+    cfg =3D readl_relaxed(addr);
=20
-    edgebit =3D 2u << (2 * (irq % 16));
+    edgebit =3D 2u << (2 * (desc->irq % 16));
     if ( type & IRQ_TYPE_LEVEL_MASK )
         cfg &=3D ~edgebit;
     else if ( type & IRQ_TYPE_EDGE_BOTH )
         cfg |=3D edgebit;
=20
-    writel_relaxed(cfg, base);
+    writel_relaxed(cfg, addr);
=20
-    actual =3D readl_relaxed(base);
+    actual =3D readl_relaxed(addr);
     if ( ( cfg & edgebit ) ^ ( actual & edgebit ) )
     {
         printk(XENLOG_WARNING "GICv3: WARNING: "
@@ -600,16 +645,13 @@ static void gicv3_set_irq_type(struct irq_desc *desc,=
 unsigned int type)
 static void gicv3_set_irq_priority(struct irq_desc *desc,
                                    unsigned int priority)
 {
-    unsigned int irq =3D desc->irq;
+    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IPRIORITYR);
=20
-    spin_lock(&gicv3.lock);
-
-    /* Set priority */
-    if ( irq < NR_GIC_LOCAL_IRQS )
-        writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + =
irq);
-    else
-        writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
+    if ( addr =3D=3D NULL )
+        return;
=20
+    spin_lock(&gicv3.lock);
+    writeb_relaxed(priority, addr);
     spin_unlock(&gicv3.lock);
 }
=20
@@ -1273,6 +1315,10 @@ static void gicv3_irq_set_affinity(struct irq_desc *=
desc, const cpumask_t *mask)
 {
     unsigned int cpu;
     uint64_t affinity;
+    void __iomem *addr =3D get_addr_by_offset(desc, GICD_IROUTER);
+
+    if ( addr =3D=3D NULL )
+        return;
=20
     ASSERT(!cpumask_empty(mask));
=20
@@ -1284,7 +1330,7 @@ static void gicv3_irq_set_affinity(struct irq_desc *d=
esc, const cpumask_t *mask)
     affinity &=3D ~GICD_IROUTER_SPI_MODE_ANY;
=20
     if ( desc->irq >=3D NR_GIC_LOCAL_IRQS )
-        writeq_relaxed_non_atomic(affinity, (GICD + GICD_IROUTER + desc->i=
rq * 8));
+        writeq_relaxed_non_atomic(affinity, addr);
=20
     spin_unlock(&gicv3.lock);
 }
diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.=
h
index fce7e42a33..5bc6475eb4 100644
--- a/xen/arch/arm/include/asm/irq.h
+++ b/xen/arch/arm/include/asm/irq.h
@@ -29,6 +29,7 @@ struct arch_irq_desc {
  */
 #define NR_IRQS		1024
=20
+#define SPI_MAX_INTID   1019
 #define LPI_OFFSET      8192
=20
 /* LPIs are always numbered starting at 8192, so 0 is a good invalid case.=
 */
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v5 05/12] xen/arm: gicv3: implement handling of GICv3.1 eSPI
Thread-Topic: [PATCH v5 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcGP7dC7+WoEN69k6endDrwJ322g==
Date: Fri, 29 Aug 2025 16:06:22 +0000
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Introduced appropriate register definitions, helper macros,
and initialization of required GICv3.1 distributor registers
to support eSPI. This type of interrupt is handled in the
same way as regular SPI interrupts, with the following
differences:

1) eSPIs can have up to 1024 interrupts, starting from the
beginning of the range, whereas regular SPIs use INTIDs from
32 to 1019, totaling 988 interrupts;
2) eSPIs start at INTID 4096, necessitating additional interrupt
index conversion during register operations.

In case if appropriate config is disabled, or GIC HW doesn't
support eSPI, the existing functionality will remain the same.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V5:
- fixed minor nits, no functional changes: changed u32 to uint32_t and
  added a comment noting that the configuration for eSPIs is the same as
  for regular SPIs
- removed ifdefs for eSPI-specific offsets to reduce the number of
  ifdefs and code duplication in further changes
- removed reviewed-by as moving offset from ifdefs requires additional
  confirmation from reviewers

Changes in V4:
- added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
  for vGIC emulation
- added a log banner with eSPI information, similar to the one for
  regular SPI
- added newline after ifdef and before gic_is_valid_line
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- add __init attribute to gicv3_dist_espi_common_init
- change open-codded eSPI register initialization to the appropriate
  gen-mask macro
- fixed formatting for lines with more than 80 symbols
- introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
  CONFIG_GICV3_ESPI disabled
- renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
  (name was taken from GIC specification) to avoid confusion
- changed type for i variable to unsigned int since it cannot be
  negative

Changes in V2:
- move gic_number_espis function from
  [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
  to use it in the newly introduced gic_is_valid_espi
- add gic_is_valid_espi which checks if IRQ number is in supported
  by HW eSPI range
- update gic_is_valid_irq conditions to allow operations with eSPIs
---
 xen/arch/arm/gic-v3.c                  | 83 ++++++++++++++++++++++++++
 xen/arch/arm/include/asm/gic.h         | 22 +++++++
 xen/arch/arm/include/asm/gic_v3_defs.h | 38 ++++++++++++
 3 files changed, 143 insertions(+)

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 29b7f68cba..4a7ce12f26 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_des=
c *irqd, u32 offset)
         default:
             break;
         }
+#ifdef CONFIG_GICV3_ESPI
+    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
+    {
+        uint32_t irq_index =3D ESPI_INTID2IDX(irqd->irq);
+
+        switch ( offset )
+        {
+        case GICD_ISENABLER:
+            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
+        case GICD_ICENABLER:
+            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
+        case GICD_ISPENDR:
+            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
+        case GICD_ICPENDR:
+            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
+        case GICD_ISACTIVER:
+            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
+        case GICD_ICACTIVER:
+            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
+        case GICD_ICFGR:
+            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
+        case GICD_IROUTER:
+            return (GICD + GICD_IROUTERnE + irq_index * 8);
+        case GICD_IPRIORITYR:
+            return (GICD + GICD_IPRIORITYRnE + irq_index);
+        default:
+            break;
+        }
+    }
+#endif
     default:
         break;
     }
@@ -655,6 +685,55 @@ static void gicv3_set_irq_priority(struct irq_desc *de=
sc,
     spin_unlock(&gicv3.lock);
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+unsigned int gic_number_espis(void)
+{
+    return gic_hw_ops->info->nr_espi;
+}
+
+static void __init gicv3_dist_espi_common_init(uint32_t type)
+{
+    unsigned int espi_nr, i;
+
+    espi_nr =3D min(1024U, GICD_TYPER_ESPIS_NUM(type));
+    gicv3_info.nr_espi =3D espi_nr;
+    /* The GIC HW doesn't support eSPI, so we can leave from here */
+    if ( gicv3_info.nr_espi =3D=3D 0 )
+        return;
+
+    printk("GICv3: %d eSPI lines\n", gicv3_info.nr_espi);
+
+    /* The configuration for eSPIs is similar to that for regular SPIs */
+    for ( i =3D 0; i < espi_nr; i +=3D 16 )
+        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
+
+    for ( i =3D 0; i < espi_nr; i +=3D 4 )
+        writel_relaxed(GIC_PRI_IRQ_ALL,
+                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
+
+    for ( i =3D 0; i < espi_nr; i +=3D 32 )
+    {
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i / 32) =
* 4);
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i / 32) =
* 4);
+    }
+
+    for ( i =3D 0; i < espi_nr; i +=3D 32 )
+        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) * =
4);
+}
+
+static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
+{
+    unsigned int i;
+
+    for ( i =3D 0; i < gicv3_info.nr_espi; i++ )
+        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * 8)=
;
+}
+#else
+static void __init gicv3_dist_espi_common_init(uint32_t type) { }
+
+static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
+#endif
+
 static void __init gicv3_dist_init(void)
 {
     uint32_t type;
@@ -700,6 +779,8 @@ static void __init gicv3_dist_init(void)
     for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i +=3D 32 )
         writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4)=
;
=20
+    gicv3_dist_espi_common_init(type);
+
     gicv3_dist_wait_for_rwp();
=20
     /* Turn on the distributor */
@@ -713,6 +794,8 @@ static void __init gicv3_dist_init(void)
=20
     for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
         writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8);
+
+    gicv3_dist_espi_init_aff(affinity);
 }
=20
 static int gicv3_enable_redist(void)
diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.=
h
index 3fcee42675..1e747dcd99 100644
--- a/xen/arch/arm/include/asm/gic.h
+++ b/xen/arch/arm/include/asm/gic.h
@@ -306,8 +306,26 @@ extern void gic_dump_vgic_info(struct vcpu *v);
=20
 /* Number of interrupt lines */
 extern unsigned int gic_number_lines(void);
+#ifdef CONFIG_GICV3_ESPI
+extern unsigned int gic_number_espis(void);
+
+static inline bool gic_is_valid_espi(unsigned int irq)
+{
+    return (irq >=3D ESPI_BASE_INTID &&
+            irq < ESPI_IDX2INTID(gic_number_espis()));
+}
+#else
+static inline bool gic_is_valid_espi(unsigned int irq)
+{
+    return false;
+}
+#endif
+
 static inline bool gic_is_valid_line(unsigned int irq)
 {
+    if ( gic_is_valid_espi(irq) )
+        return true;
+
     return irq < gic_number_lines();
 }
=20
@@ -325,6 +343,10 @@ struct gic_info {
     enum gic_version hw_version;
     /* Number of GIC lines supported */
     unsigned int nr_lines;
+#ifdef CONFIG_GICV3_ESPI
+    /* Number of GIC eSPI supported */
+    unsigned int nr_espi;
+#endif
     /* Number of LR registers */
     uint8_t nr_lrs;
     /* Maintenance irq number */
diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/=
asm/gic_v3_defs.h
index 2af093e774..3370b4cd52 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -37,6 +37,44 @@
 #define GICD_IROUTER1019             (0x7FD8)
 #define GICD_PIDR2                   (0xFFE8)
=20
+/* Additional registers for GICv3.1 */
+#define GICD_IGROUPRnE               (0x1000)
+#define GICD_IGROUPRnEN              (0x107C)
+#define GICD_ISENABLERnE             (0x1200)
+#define GICD_ISENABLERnEN            (0x127C)
+#define GICD_ICENABLERnE             (0x1400)
+#define GICD_ICENABLERnEN            (0x147C)
+#define GICD_ISPENDRnE               (0x1600)
+#define GICD_ISPENDRnEN              (0x167C)
+#define GICD_ICPENDRnE               (0x1800)
+#define GICD_ICPENDRnEN              (0x187C)
+#define GICD_ISACTIVERnE             (0x1A00)
+#define GICD_ISACTIVERnEN            (0x1A7C)
+#define GICD_ICACTIVERnE             (0x1C00)
+#define GICD_ICACTIVERnEN            (0x1C7C)
+#define GICD_IPRIORITYRnE            (0x2000)
+#define GICD_IPRIORITYRnEN           (0x23FC)
+#define GICD_ICFGRnE                 (0x3000)
+#define GICD_ICFGRnEN                (0x30FC)
+#define GICD_IGRPMODRnE              (0x3400)
+#define GICD_IGRPMODRnEN             (0x347C)
+#define GICD_NSACRnE                 (0x3600)
+#define GICD_NSACRnEN                (0x36FC)
+#define GICD_IROUTERnE               (0x8000)
+#define GICD_IROUTERnEN              (0x9FFC)
+
+#ifdef CONFIG_GICV3_ESPI
+#define GICD_TYPER_ESPI_SHIFT        8
+#define GICD_TYPER_ESPI_RANGE_SHIFT  27
+#define GICD_TYPER_ESPI_RANGE_MASK   (0x1F)
+#define GICD_TYPER_ESPI              (1U << GICD_TYPER_ESPI_SHIFT)
+#define GICD_TYPER_ESPI_RANGE(espi_range) ((((espi_range) & \
+        GICD_TYPER_ESPI_RANGE_MASK) + 1) * 32)
+#define GICD_TYPER_ESPIS_NUM(typer)    \
+        (((typer) & GICD_TYPER_ESPI) ? \
+        GICD_TYPER_ESPI_RANGE((typer) >> GICD_TYPER_ESPI_RANGE_SHIFT) : 0)
+#endif
+
 /* Common between GICD_PIDR2 and GICR_PIDR2 */
 #define GIC_PIDR2_ARCH_MASK         (0xf0)
 #define GIC_PIDR2_ARCH_GICv3        (0x30)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk 
Subject: [PATCH v5 06/12] xen/arm/irq: allow eSPI processing in the
 gic_interrupt function
Thread-Topic: [PATCH v5 06/12] xen/arm/irq: allow eSPI processing in the
 gic_interrupt function
Thread-Index: AQHcGP7eN+yGlYwKSkircjBNqV5JFQ==
Date: Fri, 29 Aug 2025 16:06:24 +0000
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The gic_interrupt function is the main handler for processing IRQs.
Currently, due to restrictive checks, it does not process interrupt
numbers greater than 1019. This patch updates the condition to allow
the handling of interrupts from the eSPI range.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 

---
Changes in V5:
- no changes

Changes in V4:
- fixed commit message
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- no changes

Changes in V2:
- no changes
---
 xen/arch/arm/gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 9469c9d08c..260ee64cca 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -342,7 +342,7 @@ void gic_interrupt(struct cpu_user_regs *regs, int is_f=
iq)
         /* Reading IRQ will ACK it */
         irq =3D gic_hw_ops->read_irq();
=20
-        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) )
+        if ( likely(irq >=3D GIC_SGI_STATIC_MAX && irq < 1020) || is_espi(=
irq) )
         {
             isb();
             do_IRQ(regs, irq, is_fiq);
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk 
Subject: [PATCH v5 07/12] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow
 eSPI processing
Thread-Topic: [PATCH v5 07/12] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to
 allow eSPI processing
Thread-Index: AQHcGP7fr2aNz8WgzkeaOcGbW6a0ZQ==
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To properly deactivate guest interrupts and allow them to be retriggered
after the initial trigger, the LR needs to be updated. The current
implementation ignores interrupts outside the range specified by the mask
0x3FF, which only covers IRQ numbers up to 1023. To enable processing of
eSPI interrupts, this patch updates the mask to 0x13FF.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 

---
Changes in V5:
- no changes

Changes in V4:
- added reviewed-by from Volodymyr Babchuk

Changes in V3:
- no changes

Changes in V2:
- remove unnecessary CONFIG_GICV3_ESPI ifdef guard
---
 xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/=
asm/gic_v3_defs.h
index 3370b4cd52..e70c1a5675 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -211,7 +211,7 @@
 #define ICH_LR_VIRTUAL_SHIFT         0
 #define ICH_LR_CPUID_MASK            0x7
 #define ICH_LR_CPUID_SHIFT           10
-#define ICH_LR_PHYSICAL_MASK         0x3ff
+#define ICH_LR_PHYSICAL_MASK         0x13ff
 #define ICH_LR_PHYSICAL_SHIFT        32
 #define ICH_LR_STATE_MASK            0x3
 #define ICH_LR_STATE_SHIFT           62
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v5 08/12] xen/arm: vgic: add resource management for extended
 SPIs
Thread-Topic: [PATCH v5 08/12] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcGP7gzxYtqJZFyUiPTlrb5XV2MQ==
Date: Fri, 29 Aug 2025 16:06:28 +0000
Message-ID:
 <4b13dea924eabf1370d3f31030f3eef48371de06.1756481577.git.leonid_komarianskyi@epam.com>
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This change introduces resource management in the VGIC to handle
extended SPIs introduced in GICv3.1. The pending_irqs and
allocated_irqs arrays are resized to support the required
number of eSPIs, based on what is supported by the hardware and
requested by the guest. A new field, ext_shared_irqs, is added
to the VGIC structure to store information about eSPIs, similar
to how shared_irqs is used for regular SPIs.

Since the eSPI range starts at INTID 4096 and INTIDs between 1025
and 4095 are reserved, helper macros are introduced to simplify the
transformation of indices and to enable easier access to eSPI-specific
resources. These changes prepare the VGIC for processing eSPIs as
required by future functionality.

The initialization and deinitialization paths for vgic have been updated
to allocate and free these resources appropriately. Additionally,
updated handling of INTIDs greater than 1024, passed from the toolstack
during domain creation, and verification logic ensures only valid SPI or
eSPI INTIDs are used.

The existing SPI behavior remains unaffected when guests do not request
eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
option is disabled.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V5:
- removed the has_espi field because it can be determined by checking
  whether domain->arch.vgic.nr_espis is zero or not
- since vgic_ext_rank_offset is not used in this patch, it has been
  moved to the appropriate patch in the patch series, which implements
  vgic eSPI registers emulation and requires this function
- removed ifdefs for eSPI-specific macros to reduce the number of ifdefs
  and code duplication in further changes
- fixed minor nit: used %pd for printing domain with its ID

Changes in V4:
- added has_espi field to simplify determining whether a domain is able
  to operate with eSPI
- fixed formatting issues and misspellings

Changes in V3:
- fixed formatting for lines with more than 80 symbols
- introduced helper functions to be able to use stubs in case of
  CONFIG_GICV3_ESPI disabled, and as a result, reduce the number of
  #ifdefs
- fixed checks for nr_spis in domain_vgic_init
- updated comment about nr_spis adjustments with dom0less mention
- moved comment with additional explanations before checks
- used unsigned int for indexes since they cannot be negative
- removed unnecessary parentheses
- move vgic_ext_rank_offset to the below ifdef guard, to reduce the
  number of ifdefs

Changes in V2:
- change is_espi_rank to is_valid_espi_rank to verify whether the array
  element ext_shared_irqs exists. The previous version, is_espi_rank,
  only checked if the rank index was less than the maximum possible eSPI
  rank index, but this could potentially result in accessing a
  non-existing array element. To address this, is_valid_espi_rank was
  introduced, which ensures that the required eSPI rank exists
- move gic_number_espis to
  xen/arm: gicv3: implement handling of GICv3.1 eSPI
- update vgic_is_valid_irq checks to allow operating with eSPIs
- remove redundant newline in vgic_allocate_virq
---
 xen/arch/arm/include/asm/vgic.h |  12 ++
 xen/arch/arm/vgic.c             | 199 +++++++++++++++++++++++++++++++-
 2 files changed, 208 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 3e7cbbb196..912d5b7694 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -146,6 +146,10 @@ struct vgic_dist {
     int nr_spis; /* Number of SPIs */
     unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
     struct vgic_irq_rank *shared_irqs;
+#ifdef CONFIG_GICV3_ESPI
+    struct vgic_irq_rank *ext_shared_irqs;
+    int nr_espis; /* Number of extended SPIs */
+#endif
     /*
      * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
      * struct arch_vcpu.
@@ -243,6 +247,14 @@ struct vgic_ops {
 /* Number of ranks of interrupt registers for a domain */
 #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
=20
+#ifdef CONFIG_GICV3_ESPI
+#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
+#endif
+#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
+#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
+#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
+#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
+
 #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
 #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
=20
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 2bbf4d99aa..c9b9528c66 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -27,9 +27,82 @@
=20
 bool vgic_is_valid_line(struct domain *d, unsigned int virq)
 {
+#ifdef CONFIG_GICV3_ESPI
+    if ( virq >=3D ESPI_BASE_INTID &&
+         virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
+        return true;
+#endif
+
     return virq < vgic_num_irqs(d);
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+/*
+ * Since eSPI indexes start from 4096 and numbers from 1024 to
+ * 4095 are forbidden, we need to check both lower and upper
+ * limits for ranks.
+ */
+static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
+{
+    return rank >=3D EXT_RANK_MIN &&
+           EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d);
+}
+
+static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
+                                                       unsigned int rank)
+{
+    return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)];
+}
+
+static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int v=
irq)
+{
+    return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d),
+                             d->arch.vgic.allocated_irqs);
+}
+
+static void arch_move_espis(struct vcpu *v)
+{
+    const cpumask_t *cpu_mask =3D cpumask_of(v->processor);
+    struct domain *d =3D v->domain;
+    struct pending_irq *p;
+    struct vcpu *v_target;
+    unsigned int i;
+
+    for ( i =3D ESPI_BASE_INTID;
+          i < EXT_RANK_IDX2NUM(d->arch.vgic.nr_espis); i++ )
+    {
+        v_target =3D vgic_get_target_vcpu(v, i);
+        p =3D irq_to_pending(v_target, i);
+
+        if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->s=
tatus) )
+            irq_set_affinity(p->desc, cpu_mask);
+    }
+}
+#else
+static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
+{
+    return false;
+}
+
+/*
+ * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn,
+ * because in this case, is_valid_espi_rank will always return false.
+ */
+static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
+                                                       unsigned int rank)
+{
+    ASSERT_UNREACHABLE();
+    return NULL;
+}
+
+static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int v=
irq)
+{
+    return false;
+}
+
+static void arch_move_espis(struct vcpu *v) { }
+#endif
+
 static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
                                                   unsigned int rank)
 {
@@ -37,6 +110,8 @@ static inline struct vgic_irq_rank *vgic_get_rank(struct=
 vcpu *v,
         return v->arch.vgic.private_irqs;
     else if ( rank <=3D DOMAIN_NR_RANKS(v->domain) )
         return &v->domain->arch.vgic.shared_irqs[rank - 1];
+    else if ( is_valid_espi_rank(v->domain, rank) )
+        return vgic_get_espi_rank(v, rank);
     else
         return NULL;
 }
@@ -117,6 +192,62 @@ int domain_vgic_register(struct domain *d, unsigned in=
t *mmio_count)
     return 0;
 }
=20
+#ifdef CONFIG_GICV3_ESPI
+static unsigned int vgic_num_spi_lines(struct domain *d)
+{
+    return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
+}
+
+static int init_vgic_espi(struct domain *d)
+{
+    unsigned int i, idx;
+
+    if ( d->arch.vgic.nr_espis =3D=3D 0 )
+        return 0;
+
+    d->arch.vgic.ext_shared_irqs =3D
+        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
+    if ( d->arch.vgic.ext_shared_irqs =3D=3D NULL )
+        return -ENOMEM;
+
+    for ( i =3D d->arch.vgic.nr_spis, idx =3D 0;
+          i < vgic_num_spi_lines(d); i++, idx++ )
+        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i],
+                              ESPI_IDX2INTID(idx));
+
+    for ( i =3D 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
+        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
+
+    return 0;
+}
+
+struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
+{
+    irq =3D ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
+    return &d->arch.vgic.pending_irqs[irq];
+}
+#else
+static unsigned int init_vgic_espi(struct domain *d)
+{
+    return 0;
+}
+
+static unsigned int vgic_num_spi_lines(struct domain *d)
+{
+    return d->arch.vgic.nr_spis;
+}
+
+struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
+{
+    return NULL;
+}
+#endif
+
+static unsigned int vgic_num_alloc_irqs(struct domain *d)
+{
+    return vgic_num_spi_lines(d) + NR_LOCAL_IRQS;
+}
+
 int domain_vgic_init(struct domain *d, unsigned int nr_spis)
 {
     int i;
@@ -131,6 +262,36 @@ int domain_vgic_init(struct domain *d, unsigned int nr=
_spis)
      */
     nr_spis =3D ROUNDUP(nr_spis, 32);
=20
+#ifdef CONFIG_GICV3_ESPI
+    /*
+     * During domain creation, the dom0less DomUs code or toolstack specif=
ies
+     * the maximum INTID, which is defined in the domain config subtracted=
 by
+     * 32 to cover the local IRQs (please see the comment to VGIC_DEF_NR_S=
PIS).
+     * To compute the actual number of eSPI that will be usable for,
+     * add back 32.
+     */
+    if ( nr_spis + 32 > ESPI_IDX2INTID(NR_ESPI_IRQS) )
+        return -EINVAL;
+
+    if ( nr_spis + 32 >=3D ESPI_BASE_INTID )
+    {
+        d->arch.vgic.nr_espis =3D min(nr_spis - ESPI_BASE_INTID + 32, 1024=
U);
+        /* Verify if GIC HW can handle provided INTID */
+        if ( d->arch.vgic.nr_espis > gic_number_espis() )
+            return -EINVAL;
+        /*
+         * Set the maximum available number for regular
+         * SPI to pass the next check
+         */
+        nr_spis =3D VGIC_DEF_NR_SPIS;
+    }
+    else
+    {
+        /* Domain will use the regular SPI range */
+        d->arch.vgic.nr_espis =3D 0;
+    }
+#endif
+
     /* Limit the number of virtual SPIs supported to (1020 - 32) =3D 988  =
*/
     if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
         return -EINVAL;
@@ -145,7 +306,7 @@ int domain_vgic_init(struct domain *d, unsigned int nr_=
spis)
         return -ENOMEM;
=20
     d->arch.vgic.pending_irqs =3D
-        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
+        xzalloc_array(struct pending_irq, vgic_num_spi_lines(d));
     if ( d->arch.vgic.pending_irqs =3D=3D NULL )
         return -ENOMEM;
=20
@@ -156,12 +317,16 @@ int domain_vgic_init(struct domain *d, unsigned int n=
r_spis)
     for ( i =3D 0; i < DOMAIN_NR_RANKS(d); i++ )
         vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
=20
+    ret =3D init_vgic_espi(d);
+    if ( ret )
+        return ret;
+
     ret =3D d->arch.vgic.handler->domain_init(d);
     if ( ret )
         return ret;
=20
     d->arch.vgic.allocated_irqs =3D
-        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
+        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_alloc_irqs(d))=
);
     if ( !d->arch.vgic.allocated_irqs )
         return -ENOMEM;
=20
@@ -195,9 +360,27 @@ void domain_vgic_free(struct domain *d)
         }
     }
=20
+#ifdef CONFIG_GICV3_ESPI
+    for ( i =3D 0; i < d->arch.vgic.nr_espis; i++ )
+    {
+        struct pending_irq *p =3D spi_to_pending(d, ESPI_IDX2INTID(i));
+
+        if ( p->desc )
+        {
+            ret =3D release_guest_irq(d, p->irq);
+            if ( ret )
+                dprintk(XENLOG_G_WARNING, "%pd: Failed to release virq %u =
ret =3D %d\n",
+                        d, p->irq, ret);
+        }
+    }
+#endif
+
     if ( d->arch.vgic.handler )
         d->arch.vgic.handler->domain_free(d);
     xfree(d->arch.vgic.shared_irqs);
+#ifdef CONFIG_GICV3_ESPI
+    xfree(d->arch.vgic.ext_shared_irqs);
+#endif
     xfree(d->arch.vgic.pending_irqs);
     xfree(d->arch.vgic.allocated_irqs);
 }
@@ -331,6 +514,8 @@ void arch_move_irqs(struct vcpu *v)
         if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->s=
tatus) )
             irq_set_affinity(p->desc, cpu_mask);
     }
+
+    arch_move_espis(v);
 }
=20
 void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
@@ -538,6 +723,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v, unsi=
gned int irq)
         n =3D &v->arch.vgic.pending_irqs[irq];
     else if ( is_lpi(irq) )
         n =3D v->domain->arch.vgic.handler->lpi_to_pending(v->domain, irq)=
;
+    else if ( is_espi(irq) )
+        n =3D espi_to_pending(v->domain, irq);
     else
         n =3D &v->domain->arch.vgic.pending_irqs[irq - 32];
     return n;
@@ -547,6 +734,9 @@ struct pending_irq *spi_to_pending(struct domain *d, un=
signed int irq)
 {
     ASSERT(irq >=3D NR_LOCAL_IRQS);
=20
+    if ( is_espi(irq) )
+        return espi_to_pending(d, irq);
+
     return &d->arch.vgic.pending_irqs[irq - 32];
 }
=20
@@ -668,6 +858,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned int v=
irq)
     if ( !vgic_is_valid_line(d, virq) )
         return false;
=20
+    if ( is_espi(virq) )
+        return vgic_reserve_espi_virq(d, virq);
+
     return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
 }
=20
@@ -685,7 +878,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
     else
     {
         first =3D 32;
-        end =3D vgic_num_irqs(d);
+        end =3D vgic_num_alloc_irqs(d);
     }
=20
     /*
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	, Volodymyr Babchuk ,
	Oleksandr Tyshchenko 
Subject: [PATCH v5 09/12] xen/arm: domain_build/dom0less-build: adjust domains
 config to support eSPIs
Thread-Topic: [PATCH v5 09/12] xen/arm: domain_build/dom0less-build: adjust
 domains config to support eSPIs
Thread-Index: AQHcGP7ji/JPLIO80UCW93TQMdVywQ==
Date: Fri, 29 Aug 2025 16:06:33 +0000
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The Dom0 and DomUs logic for the dom0less configuration in create_dom0() an=
d
arch_create_domUs() has been updated to account for extended SPIs when
supported by the hardware and enabled with CONFIG_GICV3_ESPI. These changes
ensure the proper calculation of the maximum number of SPIs and eSPIs avail=
able
to Dom0 and DomUs in dom0less setups.

When eSPIs are supported by the hardware and CONFIG_GICV3_ESPI is enabled, =
the
maximum number of eSPI interrupts is calculated using the ESPI_BASE_INTID
offset (4096) and is limited to 1024, with 32 IRQs subtracted. To ensure
compatibility with non-Dom0 domains, this adjustment is applied by the
toolstack during domain creation, while for Dom0 or DomUs in Dom0, it is
handled directly during VGIC initialization. If eSPIs are not supported, th=
e
calculation defaults to using the standard SPI range, with a maximum value =
of
992 interrupt lines, as it works currently.

Signed-off-by: Leonid Komarianskyi 
Reviewed-by: Volodymyr Babchuk 
Reviewed-by: Oleksandr Tyshchenko 

---
Changes in V5:
- fixed minor nits, no functional changes: updated the comment to make
  it clearer and corrected a misspelling
- added reviewed-by from Volodymyr Babchuk and from Oleksandr Tyshchenko

Changes in V4:
- consolidated the eSPI and SPI logic into a new inline function,
  vgic_def_nr_spis. Without eSPI support (either due to config being
  disabled or hardware not supporting it), it will return the regular SPI
  range, as it works currently. There are no functional changes compared
  with the previous patch version
- removed VGIC_DEF_MAX_SPI macro, to reduce the number of ifdefs

Changes in V3:
- renamed macro VGIC_DEF_NR_ESPIS to more appropriate VGIC_DEF_MAX_SPI
- added eSPI initialization for dom0less setups
- fixed comment with mentions about dom0less builds
- fixed formatting for lines with more than 80 symbols
- updated commit message

Changes in V2:
- no changes
---
 xen/arch/arm/dom0less-build.c   |  2 +-
 xen/arch/arm/domain_build.c     |  2 +-
 xen/arch/arm/include/asm/vgic.h | 19 +++++++++++++++++++
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
index 69b9ea22ce..02d5559102 100644
--- a/xen/arch/arm/dom0less-build.c
+++ b/xen/arch/arm/dom0less-build.c
@@ -285,7 +285,7 @@ void __init arch_create_domUs(struct dt_device_node *no=
de,
     {
         int vpl011_virq =3D GUEST_VPL011_SPI;
=20
-        d_cfg->arch.nr_spis =3D VGIC_DEF_NR_SPIS;
+        d_cfg->arch.nr_spis =3D vgic_def_nr_spis();
=20
         /*
          * The VPL011 virq is GUEST_VPL011_SPI, unless direct-map is
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index d91a71acfd..39eea0be00 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2054,7 +2054,7 @@ void __init create_dom0(void)
=20
     /* The vGIC for DOM0 is exactly emulating the hardware GIC */
     dom0_cfg.arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE;
-    dom0_cfg.arch.nr_spis =3D VGIC_DEF_NR_SPIS;
+    dom0_cfg.arch.nr_spis =3D vgic_def_nr_spis();
     dom0_cfg.arch.tee_type =3D tee_get_type();
     dom0_cfg.max_vcpus =3D dom0_max_vcpus();
=20
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 912d5b7694..3aa22114ba 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -347,6 +347,25 @@ extern void vgic_check_inflight_irqs_pending(struct vc=
pu *v,
 /* Default number of vGIC SPIs. 32 are substracted to cover local IRQs. */
 #define VGIC_DEF_NR_SPIS (min(gic_number_lines(), VGIC_MAX_IRQS) - 32)
=20
+static inline unsigned int vgic_def_nr_spis(void)
+{
+#ifdef CONFIG_GICV3_ESPI
+    /*
+     * Check if the hardware supports extended SPIs (even if the appropria=
te
+     * config is set). If not, the common SPI range will be used. Otherwis=
e
+     * return the maximum eSPI INTID, supported by HW GIC, subtracted by 3=
2.
+     * For Dom0 and started at boot time DomUs we will add back this value
+     * during VGIC initialization. This ensures consistent handling for Do=
m0
+     * and other domains. For the regular SPI range interrupts in this cas=
e,
+     * the maximum value of VGIC_DEF_NR_SPIS will be used.
+     */
+    if ( gic_number_espis() > 0 )
+        return ESPI_BASE_INTID + min(gic_number_espis(), 1024U) - 32;
+#endif
+
+    return VGIC_DEF_NR_SPIS;
+}
+
 extern bool vgic_is_valid_line(struct domain *d, unsigned int virq);
=20
 static inline bool vgic_is_spi(struct domain *d, unsigned int virq)
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Stefano Stabellini ,
	Julien Grall , Bertrand Marquis ,
	Michal Orzel , Volodymyr Babchuk
	
Subject: [PATCH v5 10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v5 10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Index: AQHcGP7lSnKp01vKiUyg8GCh+goOAw==
Date: Fri, 29 Aug 2025 16:06:36 +0000
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 <6fda233a1a2f0362062ff9a6e80ee223d33815cf.1756481577.git.leonid_komarianskyi@epam.com>
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Implemented support for GICv3.1 extended SPI registers for vGICv3,
allowing the emulation of eSPI-specific behavior for guest domains.
The implementation includes read and write emulation for eSPI-related
registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
following a similar approach to the handling of regular SPIs.

The eSPI registers, previously located in reserved address ranges,
are now adjusted to support MMIO read and write operations correctly
when CONFIG_GICV3_ESPI is enabled.

The availability of eSPIs and the number of emulated extended SPIs
for guest domains is reported by setting the appropriate bits in the
GICD_TYPER register, based on the number of eSPIs requested by the
domain and supported by the hardware. In cases where the configuration
option is disabled, the hardware does not support eSPIs, or the domain
does not request such interrupts, the functionality remains unchanged.

Signed-off-by: Leonid Komarianskyi 

---
Changes in V5:
- since eSPI-specific defines and macros are now available even when the
  appropriate config is disabled, this allows us to remove many
  #ifdef guards and reuse the existing code for regular SPIs for eSPIs as
  well, as eSPIs are processed similarly. This improves code readability
  and consolidates the register ranges for SPIs and eSPIs in a single
  place, simplifying future changes or fixes for SPIs and their
  counterparts from the extended range
- moved vgic_ext_rank_offset() from
  [08/12] xen/arm: vgic: add resource management for extended SPIs
  as the function was unused before this patch
- added stub implementation of vgic_ext_rank_offset() when CONFIG_GICV3_ESP=
I=3Dn
- removed unnecessary defines for reserved ranges, which were introduced in
  V4 to reduce the number of #ifdefs. The issue is now resolved by
  allowing the use of SPI-specific offsets and reworking the logic

Changes in V4:
- added missing RAZ and write ignore eSPI-specific registers ranges:
  GICD_NSACRnE and GICD_IGRPMODRnE
- changed previously reserved range to cover GICD_NSACRnE and
  GICD_IGRPMODRnE
- introduced GICD_RESERVED_RANGE_START/END defines to remove
  hardcoded values and reduce the number of ifdefs
- fixed reserved ranges with eSPI option enabled: added missing range
  0x0F30-0x0F7C
- updated the logic for domains that do not support eSPI, but Xen is
  compiled with the eSPI option. Now, prior to other MMIO checks, we
  verify whether eSPI is available for the domain or not. If not, it
  behaves as it does currently - RAZ and WI
- fixed print for GICD_ICACTIVERnE
- fixed new lines formatting for switch-case

Changes in V3:
- changed vgic_store_irouter parameters - instead of offset virq is
  used, to remove the additional bool espi parameter and simplify
  checks. Also, adjusted parameters for regular SPI. Since the offset
  parameter was used only for calculating virq number and then reused for
  finding rank offset, it will not affect functionality.
- fixed formatting for goto lables - added newlines after condition
- fixed logs for GICD_ISACTIVERnE and GICD_ICACTIVERnE handlers
- removed #ifdefs in 2 places where they were adjacent and could be merged

Changes in V2:
- add missing rank index conversion for pending and inflight irqs
---
 xen/arch/arm/include/asm/vgic.h |   4 +
 xen/arch/arm/vgic-v3.c          | 198 ++++++++++++++++++++++++++------
 xen/arch/arm/vgic.c             |  23 ++++
 3 files changed, 192 insertions(+), 33 deletions(-)

diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgi=
c.h
index 3aa22114ba..103bc3c74b 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -314,6 +314,10 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct v=
cpu *v,
                                               unsigned int b,
                                               unsigned int n,
                                               unsigned int s);
+extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
+                                                  unsigned int b,
+                                                  unsigned int n,
+                                                  unsigned int s);
 extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int ir=
q);
 extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
 extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n);
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 4369c55177..b5d766c98f 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -111,13 +111,10 @@ static uint64_t vgic_fetch_irouter(struct vgic_irq_ra=
nk *rank,
  * Note the offset will be aligned to the appropriate boundary.
  */
 static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *ran=
k,
-                               unsigned int offset, uint64_t irouter)
+                               unsigned int virq, uint64_t irouter)
 {
     struct vcpu *new_vcpu, *old_vcpu;
-    unsigned int virq;
-
-    /* There is 1 vIRQ per IROUTER */
-    virq =3D offset / NR_BYTES_PER_IROUTER;
+    unsigned int offset;
=20
     /*
      * The IROUTER0-31, used for SGIs/PPIs, are reserved and should
@@ -685,13 +682,20 @@ static int __vgic_v3_distr_common_mmio_read(const cha=
r *name, struct vcpu *v,
     {
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
         /* We do not implement security extensions for guests, read zero *=
/
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
         goto read_as_zero;
=20
     case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_WORD);
+        if ( reg >=3D GICD_ISENABLERnE )
+            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE,
+                                        DABT_WORD);
+        else
+            rank =3D vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_WOR=
D);
         if ( rank =3D=3D NULL ) goto read_as_zero;
         vgic_lock_rank(v, rank, flags);
         *r =3D vreg_reg32_extract(rank->ienable, info);
@@ -699,8 +703,13 @@ static int __vgic_v3_distr_common_mmio_read(const char=
 *name, struct vcpu *v,
         return 1;
=20
     case VRANGE32(GICD_ICENABLER, GICD_ICENABLERN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_WORD);
+        if ( reg >=3D GICD_ICENABLERnE )
+            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE,
+                                        DABT_WORD);
+        else
+            rank =3D vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_WOR=
D);
         if ( rank =3D=3D NULL ) goto read_as_zero;
         vgic_lock_rank(v, rank, flags);
         *r =3D vreg_reg32_extract(rank->ienable, info);
@@ -710,20 +719,29 @@ static int __vgic_v3_distr_common_mmio_read(const cha=
r *name, struct vcpu *v,
     /* Read the pending status of an IRQ via GICD/GICR is not supported */
     case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
     case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
         goto read_as_zero;
=20
     /* Read the active status of an IRQ via GICD/GICR is not supported */
     case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
     case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
         goto read_as_zero;
=20
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
     {
         uint32_t ipriorityr;
         uint8_t rank_index;
=20
         if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD ) goto b=
ad_width;
-        rank =3D vgic_rank_offset(v, 8, reg - GICD_IPRIORITYR, DABT_WORD);
+        if ( reg >=3D GICD_IPRIORITYRnE )
+            rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE,
+                                        DABT_WORD);
+        else
+            rank =3D vgic_rank_offset(v, 8, reg - GICD_IPRIORITYR, DABT_WO=
RD);
         if ( rank =3D=3D NULL ) goto read_as_zero;
         rank_index =3D REG_RANK_INDEX(8, reg - GICD_IPRIORITYR, DABT_WORD)=
;
=20
@@ -737,11 +755,15 @@ static int __vgic_v3_distr_common_mmio_read(const cha=
r *name, struct vcpu *v,
     }
=20
     case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
     {
         uint32_t icfgr;
=20
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD);
+        if ( reg >=3D GICD_ICFGRnE )
+            rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_W=
ORD);
+        else
+            rank =3D vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD);
         if ( rank =3D=3D NULL ) goto read_as_zero;
         vgic_lock_rank(v, rank, flags);
         icfgr =3D rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WORD=
)];
@@ -782,46 +804,81 @@ static int __vgic_v3_distr_common_mmio_write(const ch=
ar *name, struct vcpu *v,
     {
     case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
         /* We do not implement security extensions for guests, write ignor=
e */
         goto write_ignore_32;
=20
     case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_WORD);
+        if ( reg >=3D GICD_ISENABLERnE )
+            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE,
+                                        DABT_WORD);
+        else
+            rank =3D vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_WOR=
D);
         if ( rank =3D=3D NULL ) goto write_ignore;
         vgic_lock_rank(v, rank, flags);
         tr =3D rank->ienable;
         vreg_reg32_setbits(&rank->ienable, r, info);
-        vgic_enable_irqs(v, (rank->ienable) & (~tr), rank->index);
+        if ( reg >=3D GICD_ISENABLERnE )
+            vgic_enable_irqs(v, (rank->ienable) & (~tr),
+                             EXT_RANK_IDX2NUM(rank->index));
+        else
+            vgic_enable_irqs(v, (rank->ienable) & (~tr), rank->index);
         vgic_unlock_rank(v, rank, flags);
         return 1;
=20
     case VRANGE32(GICD_ICENABLER, GICD_ICENABLERN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_WORD);
+        if ( reg >=3D GICD_ICENABLERnE )
+            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE,
+                                        DABT_WORD);
+        else
+            rank =3D vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_WOR=
D);
         if ( rank =3D=3D NULL ) goto write_ignore;
         vgic_lock_rank(v, rank, flags);
         tr =3D rank->ienable;
         vreg_reg32_clearbits(&rank->ienable, r, info);
-        vgic_disable_irqs(v, (~rank->ienable) & tr, rank->index);
+        if ( reg >=3D GICD_ICENABLERnE )
+            vgic_disable_irqs(v, (~rank->ienable) & tr,
+                              EXT_RANK_IDX2NUM(rank->index));
+        else
+            vgic_disable_irqs(v, (~rank->ienable) & tr, rank->index);
         vgic_unlock_rank(v, rank, flags);
         return 1;
=20
     case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 1, reg - GICD_ISPENDR, DABT_WORD);
+        if ( reg >=3D GICD_ISPENDRnE )
+            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISPENDRnE, DABT=
_WORD);
+        else
+            rank =3D vgic_rank_offset(v, 1, reg - GICD_ISPENDR, DABT_WORD)=
;
         if ( rank =3D=3D NULL ) goto write_ignore;
=20
-        vgic_set_irqs_pending(v, r, rank->index);
+        if ( reg >=3D GICD_ISPENDRnE )
+            vgic_set_irqs_pending(v, r, EXT_RANK_IDX2NUM(rank->index));
+        else
+            vgic_set_irqs_pending(v, r, rank->index);
=20
         return 1;
=20
     case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 1, reg - GICD_ICPENDR, DABT_WORD);
+        if ( reg >=3D GICD_ICPENDRnE )
+            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICPENDRnE, DABT=
_WORD);
+        else
+            rank =3D vgic_rank_offset(v, 1, reg - GICD_ICPENDR, DABT_WORD)=
;
         if ( rank =3D=3D NULL ) goto write_ignore;
=20
-        vgic_check_inflight_irqs_pending(v, rank->index, r);
+        if ( reg >=3D GICD_ICPENDRnE )
+            vgic_check_inflight_irqs_pending(v,
+                                             EXT_RANK_IDX2NUM(rank->index)=
, r);
+        else
+            vgic_check_inflight_irqs_pending(v, rank->index, r);
=20
         goto write_ignore;
=20
@@ -838,16 +895,38 @@ static int __vgic_v3_distr_common_mmio_write(const ch=
ar *name, struct vcpu *v,
                v, name, r, reg - GICD_ICACTIVER);
         goto write_ignore_32;
=20
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+        if ( dabt.size !=3D DABT_WORD )
+            goto bad_width;
+        printk(XENLOG_G_ERR
+               "%pv: %s: unhandled word write %#"PRIregister" to ISACTIVER=
%dE\n",
+               v, name, r, reg - GICD_ISACTIVERnE);
+        return 0;
+
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+        printk(XENLOG_G_ERR
+               "%pv: %s: unhandled word write %#"PRIregister" to ICACTIVER=
%dE\n",
+               v, name, r, reg - GICD_ICACTIVERnE);
+        goto write_ignore_32;
+
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
     {
-        uint32_t *ipriorityr, priority;
+        uint32_t *ipriorityr, priority, offset;
=20
         if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD ) goto b=
ad_width;
-        rank =3D vgic_rank_offset(v, 8, reg - GICD_IPRIORITYR, DABT_WORD);
+        if ( reg >=3D GICD_IPRIORITYRnE ) {
+            offset =3D reg - GICD_IPRIORITYRnE;
+            rank =3D vgic_ext_rank_offset(v, 8, offset, DABT_WORD);
+        }
+        else
+        {
+            offset =3D reg - GICD_IPRIORITYR;
+            rank =3D vgic_rank_offset(v, 8, offset, DABT_WORD);
+        }
         if ( rank =3D=3D NULL ) goto write_ignore;
         vgic_lock_rank(v, rank, flags);
-        ipriorityr =3D &rank->ipriorityr[REG_RANK_INDEX(8, reg - GICD_IPRI=
ORITYR,
-                                                      DABT_WORD)];
+        ipriorityr =3D &rank->ipriorityr[REG_RANK_INDEX(8, offset, DABT_WO=
RD)];
         priority =3D ACCESS_ONCE(*ipriorityr);
         vreg_reg32_update(&priority, r, info);
         ACCESS_ONCE(*ipriorityr) =3D priority;
@@ -859,10 +938,14 @@ static int __vgic_v3_distr_common_mmio_write(const ch=
ar *name, struct vcpu *v,
         goto write_ignore_32;
=20
     case VRANGE32(GICD_ICFGR + 4, GICD_ICFGRN): /* PPI + SPIs */
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
         /* ICFGR1 for PPI's, which is implementation defined
            if ICFGR1 is programmable or not. We chose to program */
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD);
+        if ( reg >=3D GICD_ICFGRnE )
+            rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT_W=
ORD);
+        else
+            rank =3D vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD);
         if ( rank =3D=3D NULL ) goto write_ignore;
         vgic_lock_rank(v, rank, flags);
         vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR,
@@ -1129,6 +1212,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
             typer |=3D GICD_TYPE_LPIS;
=20
         typer |=3D (v->domain->arch.vgic.intid_bits - 1) << GICD_TYPE_ID_B=
ITS_SHIFT;
+#ifdef CONFIG_GICV3_ESPI
+        if ( v->domain->arch.vgic.nr_espis > 0 )
+        {
+            /* Set eSPI support bit for the domain */
+            typer |=3D GICD_TYPER_ESPI;
+            /* Set ESPI range bits */
+            typer |=3D (DIV_ROUND_UP(v->domain->arch.vgic.nr_espis, 32) - =
1)
+                       << GICD_TYPER_ESPI_RANGE_SHIFT;
+        }
+#endif
=20
         *r =3D vreg_reg32_extract(typer, info);
=20
@@ -1194,6 +1287,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, m=
mio_info_t *info,
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
     case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
         /*
          * Above all register are common with GICR and GICD
          * Manage in common
@@ -1201,6 +1304,7 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mm=
io_info_t *info,
         return __vgic_v3_distr_common_mmio_read("vGICD", v, info, gicd_reg=
, r);
=20
     case VRANGE32(GICD_NSACR, GICD_NSACRN):
+    case VRANGE32(GICD_NSACRnE, GICD_NSACRnEN):
         /* We do not implement security extensions for guests, read zero *=
/
         goto read_as_zero_32;
=20
@@ -1216,16 +1320,21 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, =
mmio_info_t *info,
         /* Replaced with GICR_ISPENDR0. So ignore write */
         goto read_as_zero_32;
=20
-    case VRANGE32(0x0F30, 0x60FC):
+    case VRANGE32(0x0F30, 0x0FFC):
         goto read_reserved;
=20
     case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
+    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
     {
         uint64_t irouter;
=20
         if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
-                                DABT_DOUBLE_WORD);
+        if ( gicd_reg >=3D GICD_IROUTERnE )
+            rank =3D vgic_ext_rank_offset(v, 64, gicd_reg - GICD_IROUTERnE=
,
+                                        DABT_DOUBLE_WORD);
+        else
+            rank =3D vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
+                                    DABT_DOUBLE_WORD);
         if ( rank =3D=3D NULL ) goto read_as_zero;
         vgic_lock_rank(v, rank, flags);
         irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTER);
@@ -1235,8 +1344,8 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, mm=
io_info_t *info,
=20
         return 1;
     }
-
-    case VRANGE32(0x7FE0, 0xBFFC):
+    case VRANGE32(0x3700, 0x60FC):
+    case VRANGE32(0xA004, 0xBFFC):
         goto read_reserved;
=20
     case VRANGE32(0xC000, 0xFFCC):
@@ -1382,12 +1491,23 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v,=
 mmio_info_t *info,
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
     case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
     case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
+    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
+    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
+    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
+    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
+    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
+    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
+    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
+    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
+    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
+    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
         /* Above registers are common with GICR and GICD
          * Manage in common */
         return __vgic_v3_distr_common_mmio_write("vGICD", v, info,
                                                  gicd_reg, r);
=20
     case VRANGE32(GICD_NSACR, GICD_NSACRN):
+    case VRANGE32(GICD_NSACRnE, GICD_NSACRnEN):
         /* We do not implement security extensions for guests, write ignor=
e */
         goto write_ignore_32;
=20
@@ -1405,26 +1525,38 @@ static int vgic_v3_distr_mmio_write(struct vcpu *v,=
 mmio_info_t *info,
         if ( dabt.size !=3D DABT_WORD ) goto bad_width;
         return 0;
=20
-    case VRANGE32(0x0F30, 0x60FC):
+    case VRANGE32(0x0F30, 0x0FFC):
         goto write_reserved;
=20
     case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
+    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
     {
         uint64_t irouter;
+        unsigned int offset, virq;
=20
         if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
-        rank =3D vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
-                                DABT_DOUBLE_WORD);
+        if ( gicd_reg >=3D GICD_IROUTERnE ) {
+            offset =3D gicd_reg - GICD_IROUTERnE;
+            rank =3D vgic_ext_rank_offset(v, 64, offset, DABT_DOUBLE_WORD)=
;
+        } else {
+            offset =3D gicd_reg - GICD_IROUTER;
+            rank =3D vgic_rank_offset(v, 64, offset, DABT_DOUBLE_WORD);
+        }
         if ( rank =3D=3D NULL ) goto write_ignore;
         vgic_lock_rank(v, rank, flags);
-        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTER);
+        irouter =3D vgic_fetch_irouter(rank, offset);
         vreg_reg64_update(&irouter, r, info);
-        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTER, irout=
er);
+        if ( gicd_reg >=3D GICD_IROUTERnE )
+            virq =3D ESPI_IDX2INTID(offset / NR_BYTES_PER_IROUTER);
+        else
+            virq =3D offset / NR_BYTES_PER_IROUTER;
+        vgic_store_irouter(v->domain, rank, virq, irouter);
         vgic_unlock_rank(v, rank, flags);
         return 1;
     }
=20
-    case VRANGE32(0x7FE0, 0xBFFC):
+    case VRANGE32(0x3700, 0x60FC):
+    case VRANGE32(0xA004, 0xBFFC):
         goto write_reserved;
=20
     case VRANGE32(0xC000, 0xFFCC):
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index c9b9528c66..27ffdf316c 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -193,6 +193,18 @@ int domain_vgic_register(struct domain *d, unsigned in=
t *mmio_count)
 }
=20
 #ifdef CONFIG_GICV3_ESPI
+/*
+ * The function behavior is the same as for regular SPIs (vgic_rank_offset=
),
+ * but it operates with extended SPI ranks.
+ */
+struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int b,
+                                           unsigned int n, unsigned int s)
+{
+    unsigned int rank =3D REG_RANK_NR(b, (n >> s));
+
+    return vgic_get_rank(v, rank + EXT_RANK_MIN);
+}
+
 static unsigned int vgic_num_spi_lines(struct domain *d)
 {
     return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
@@ -241,6 +253,17 @@ struct pending_irq *espi_to_pending(struct domain *d, =
unsigned int irq)
 {
     return NULL;
 }
+
+/*
+ * It is expected that, in the case of CONFIG_GICV3_ESPI=3Dn, the function=
 will
+ * return NULL. In this scenario, mmio_read/mmio_write will be treated as
+ * RAZ/WI, as expected.
+ */
+struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int b,
+                                           unsigned int n, unsigned int s)
+{
+    return NULL;
+}
 #endif
=20
 static unsigned int vgic_num_alloc_irqs(struct domain *d)
--=20
2.34.1


From xen-devel-bounces@lists.xenproject.org Fri Aug 29 16:10:51 2025
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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Oleksii Kurochko
	, Community Manager
	
Subject: [PATCH v5 12/12] CHANGELOG.md: add mention of GICv3.1 eSPI support
Thread-Topic: [PATCH v5 12/12] CHANGELOG.md: add mention of GICv3.1 eSPI
 support
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Date: Fri, 29 Aug 2025 16:06:46 +0000
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The GICv3.1 eSPI (Extended Shared Peripheral Interrupts) range is
already supported with CONFIG_GICV3_ESPI enabled, so this feature should
be mentioned in CHANGELOG.md.

Signed-off-by: Leonid Komarianskyi 
Acked-by: Oleksii Kurochko

---
Changes in V5:
- extended changelog update with a brief explanation of what eSPI is
- added acked-by from Oleksii Kurochko, which was received for V3:
  https://lore.kernel.org/xen-devel/bce5e07c-eee7-481b-a833-4d5d8bbce78f@gm=
ail.com/

Changes in V4:
- no changes

Changes in V3:
- introduced this patch
---
 CHANGELOG.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5f31ca08fe..31b4ded444 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -29,6 +29,8 @@ The format is based on [Keep a Changelog](https://keepach=
angelog.com/en/1.0.0/)
=20
  - On Arm:
     - Ability to enable stack protector
+    - GICv3.1 eSPI (Extended Shared Peripheral Interrupts) support for Xen
+      and guest domains.
=20
 ### Removed
  - On x86:
--=20
2.34.1


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From: Leonid Komarianskyi 
To: "xen-devel@lists.xenproject.org" 
CC: "olekstysh@gmail.com" , Leonid Komarianskyi
	, Anthony PERARD 
Subject: [PATCH v5 11/12] doc/man: update description for nr_spis with eSPI
Thread-Topic: [PATCH v5 11/12] doc/man: update description for nr_spis with
 eSPI
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Date: Fri, 29 Aug 2025 16:06:38 +0000
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Since eSPI support has been introduced, update the documentation with
the appropriate description.

Signed-off-by: Leonid Komarianskyi 

---
The discussion is ongoing and can be addressed in V5.
Clarification is needed from the maintainers.
Link:
- https://lore.kernel.org/xen-devel/87y0r4z717.fsf@epam.com/

Changes in V5:
- no changes

Changes in V4:
- introduced this patch
---
 docs/man/xl.cfg.5.pod.in | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
index 5362fb0e9a..292ab10331 100644
--- a/docs/man/xl.cfg.5.pod.in
+++ b/docs/man/xl.cfg.5.pod.in
@@ -3072,11 +3072,14 @@ interval of colors (such as "0-4").
 =3Ditem B
=20
 An optional integer parameter specifying the number of SPIs (Shared
-Peripheral Interrupts) to allocate for the domain. Max is 960 SPIs. If
-the `nr_spis` parameter is not specified, the value calculated by the tool=
stack
-will be used for the domain. Otherwise, the value specified by the `nr_spi=
s`
-parameter will be used. The number of SPIs should match the highest interr=
upt
-ID that will be assigned to the domain.
+Peripheral Interrupts) to allocate for the domain. Max is 960 for regular =
SPIs
+or 5088 for eSPIs (Extended SPIs). The eSPIs includes an additional 1024 S=
PIs
+from the eSPI range (4096 to 5119) if the hardware supports extended SPIs
+(GICv3.1+) and CONFIG_GICV3_ESPI is enabled. If the `nr_spis` parameter is=
 not
+specified, the value calculated by the toolstack will be used for the doma=
in.
+Otherwise, the value specified by the `nr_spis` parameter will be used. Th=
e
+number of SPIs should match the highest interrupt ID that will be assigned=
 to
+the domain.
=20
 =3Ditem B
=20
--=20
2.34.1


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To: Oleksii Moisieiev ,
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Cc: Andrew Cooper ,
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 , Juergen Gross ,
 Julien Grall , Michal Orzel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Volodymyr Babchuk ,
 Grygorii Strashko 
References: 
 <02b79eaa0a611fb43a2146a5f41aec435d3db6c7.1756399156.git.oleksii_moisieiev@epam.com>
Content-Language: en-US
From: Oleksandr Tyshchenko 
In-Reply-To: <02b79eaa0a611fb43a2146a5f41aec435d3db6c7.1756399156.git.oleksii_moisieiev@epam.com>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit



On 28.08.25 19:40, Oleksii Moisieiev wrote:

Hello Oleksii

the patch lgtm, just some comments

> From: Grygorii Strashko 
> 
> The commit 3e322bef8bc0 ("xen/arm: firmware: Add SCMI over SMC calls
> handling layer") introduces simple driver which forwards SCMI over SMC
> calls from hwdom/dom0 to EL3 firmware (TF-A) with a single SCMI OSPM agent
> support. While it is working gracefully for hwdom/dom0 use case it doesn't
> cover "thin Dom0 with guest domain, which serves as Driver domain"
> use-case. In this case HW need to be enable in Driver domain and dom0 is
> performing only control functions.
> 
> The EL3 SCMI firmware (TF-A) with a single SCMI OSPM agent support is
> pretty generic case for the default vendors SDK and new platforms.
> 
> This patch enables passthrough of SCMI SMC single agent interface to the
> one guest domain serving as Driver domain.
> 
> Configure Dom0 to enable SCMI passthrough:
> 
>   - dom0: add scmi-smc-passthrough to the Xen Command Line
> 
> Enabled SCMI passthrough for guest using toolstack in the following way:
> 
>   - domD: xl.cfg add "arm_sci" option as below
> 
>     arm_sci = "type=scmi_smc"
> 
>   - domD: xl.cfg enable access to the "arm,scmi-shmem"
> 
> iomem = [
>      "47ff0,1@22001",
> ]
> 
>   - domD: add SCMI nodes to the Driver domain partial device tree as in the
>   below example:
> 
> passthrough {
>     scmi_shm_0: sram@22001000 {
>         compatible = "arm,scmi-shmem";
>         reg = <0x0 0x22001000 0x0 0x1000>;
>     };
> 
>     firmware {
>          compatible = "simple-bus";
>              scmi: scmi {
>                  compatible = "arm,scmi-smc";
>                  shmem = <&scmi_shm_0>;
>                  ...
>              }
>      }
> }
> 
> dom0less case configuration:
> 
> - add "xen,sci_type" property for required DomU ("xen,domain") node
> 
>     xen,sci_type="scmi_smc"
> 
> - add scmi nodes to the Driver domain partial device tree the same way
> as above and enable access to the "arm,scmi-shmem" according to
> dom0less documentation. For example:
> 
>    scmi_shm_0: sram@22001000 {
>          compatible = "arm,scmi-shmem";
>          reg = <0x00 0x22001000 0x00 0x1000>;
> ->        xen,reg = <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
> ->        xen,force-assign-without-iommu;
>    };
> 
> The SCMI SMC single agent interface can be enabled for one and only one
> domain. In general, the configuration is similar to any other HW
> passthrough, except explicitly enabling SCMI with "arm_sci" xl.cfg option.
> 
> Note that "arm,scmi-smc" and "arm,scmi-shmem" nodes will be removed from
> dom0/hwdom DT in case of

?

> 
> Signed-off-by: Grygorii Strashko 
> Signed-off-by: Oleksii Moisieiev 
> Acked-by: Anthony PERARD  # tools
> ---
> 
> Changes in v6:
> - added generated helpers and types go files
> - rename cmdline parameter to scmi-smc-passthrough
> - fix goto tag in parse_arm_sci_config
> 
> Changes in v5:
> - rename dom0_scmi_smc_passthrough to scmi_smc_passthrough
> 
> Changes in v4:
> - xl.cfg doc
> - fix comments from Stefano Stabellini
> - fix toolstack code as sugested by Anthony PERARD
>    - use MATCH_OPTION()
>    - move arm_sci struct and cfg params in "arch_arm"
> - add SCMI passthrough for dom0less case
> 
>   docs/man/xl.cfg.5.pod.in              |  34 ++++++++
>   docs/misc/arm/device-tree/booting.txt |  15 ++++
>   docs/misc/xen-command-line.pandoc     |   9 +++
>   tools/golang/xenlight/helpers.gen.go  |  41 ++++++++++
>   tools/golang/xenlight/types.gen.go    |  12 +++
>   tools/include/libxl.h                 |   5 ++
>   tools/libs/light/libxl_arm.c          |  14 ++++
>   tools/libs/light/libxl_types.idl      |  10 +++
>   tools/xl/xl_parse.c                   |  36 +++++++++
>   xen/arch/arm/dom0less-build.c         |  34 +++++++-
>   xen/arch/arm/firmware/Kconfig         |   4 +-
>   xen/arch/arm/firmware/scmi-smc.c      | 112 +++++++++++++++++++++++++-
>   12 files changed, 321 insertions(+), 5 deletions(-)
> 

[snip]

> diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c
> index 0094cf9e40..7422f4be30 100644
> --- a/xen/arch/arm/dom0less-build.c
> +++ b/xen/arch/arm/dom0less-build.c
> @@ -279,6 +279,36 @@ int __init arch_handle_passthrough_prop(struct kernel_info *kinfo,
>       return sci_assign_dt_device(kinfo->bd.d, node);
>   }
>   
> +int __init domu_dt_sci_parse(struct dt_device_node *node,
> +                             struct xen_domctl_createdomain *d_cfg)
> +{
> +    const char *sci_type = NULL;

NIT: I think "= NULL" can be omitted.

> +    int ret;
> +
> +    d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
> +
> +    if ( !IS_ENABLED(CONFIG_ARM_SCI) ||
> +         !dt_property_read_bool(node, "xen,sci_type") )
> +        return 0;
> +
> +    ret = dt_property_read_string(node, "xen,sci_type", &sci_type);
> +    if ( ret )
> +        return ret;
> +
> +    if ( !strcmp(sci_type, "none") )
> +        d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
> +    else if ( !strcmp(sci_type, "scmi_smc") )
> +        d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC;
> +    else
> +    {
> +        printk(XENLOG_ERR "xen,sci_type in not valid (%s) for domain %s\n",
> +               sci_type, dt_node_name(node));
> +        return -EINVAL;
> +    }
> +
> +    return 0;
> +}
> +
>   int __init arch_parse_dom0less_node(struct dt_device_node *node,
>                                       struct boot_domain *bd)
>   {
> @@ -288,7 +318,9 @@ int __init arch_parse_dom0less_node(struct dt_device_node *node,
>   
>       d_cfg->arch.gic_version = XEN_DOMCTL_CONFIG_GIC_NATIVE;
>       d_cfg->flags |= XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap;
> -    d_cfg->arch.arm_sci_type = XEN_DOMCTL_CONFIG_ARM_SCI_NONE;
> +
> +    if ( domu_dt_sci_parse(node, d_cfg) )
> +        panic("Error getting SCI configuration\n");
>   
>       if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) )
>       {
> diff --git a/xen/arch/arm/firmware/Kconfig b/xen/arch/arm/firmware/Kconfig
> index bbf88fbb9a..5c5f0880c4 100644
> --- a/xen/arch/arm/firmware/Kconfig
> +++ b/xen/arch/arm/firmware/Kconfig
> @@ -25,7 +25,9 @@ config SCMI_SMC
>   	  doorbell mechanism and Shared Memory for transport ("arm,scmi-smc"
>   	  compatible only). The value of "arm,smc-id" DT property from SCMI
>   	  firmware node is used to trap and forward corresponding SCMI SMCs
> -	  to firmware running at EL3, for calls coming from the hardware domain.
> +	  to firmware running at EL3, for calls coming from the hardware domain or
> +	  driver domain.
> +	  Use with EL3 firmware which supports only single SCMI OSPM agent.
>   
>   endchoice
>   
> diff --git a/xen/arch/arm/firmware/scmi-smc.c b/xen/arch/arm/firmware/scmi-smc.c
> index 13d1137592..edc54b11b6 100644
> --- a/xen/arch/arm/firmware/scmi-smc.c
> +++ b/xen/arch/arm/firmware/scmi-smc.c
> @@ -14,6 +14,8 @@
>   #include 
>   #include 
>   #include 
> +#include 
> +#include 
>   #include 
>   #include 
>   
> @@ -22,7 +24,11 @@
>   
>   #define SCMI_SMC_ID_PROP   "arm,smc-id"
>   
> +static bool __ro_after_init opt_scmi_smc_passthrough = false;

NIT: I think "= false" can be omitted.


> +boolean_param("scmi-smc-passthrough", opt_scmi_smc_passthrough);
> +
>   static uint32_t __ro_after_init scmi_smc_id;
> +static struct domain __read_mostly *scmi_dom;
>   
>   /*
>    * Check if provided SMC Function Identifier matches the one known by the SCMI
> @@ -50,7 +56,7 @@ static bool scmi_handle_smc(struct cpu_user_regs *regs)
>           return false;
>   
>       /* Only the hardware domain should use SCMI calls */
> -    if ( !is_hardware_domain(current->domain) )
> +    if ( scmi_dom != current->domain )
>       {
>           gdprintk(XENLOG_WARNING, "SCMI: Unprivileged access attempt\n");
>           return false;
> @@ -75,12 +81,45 @@ static bool scmi_handle_smc(struct cpu_user_regs *regs)
>       return true;
>   }
>   
> +static int
> +scmi_smc_domain_sanitise_config(struct xen_domctl_createdomain *config)
> +{
> +    if ( config->arch.arm_sci_type != XEN_DOMCTL_CONFIG_ARM_SCI_NONE &&
> +         config->arch.arm_sci_type != XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC )
> +        return -EINVAL;
> +
> +    return 0;
> +}
> +
>   static int scmi_smc_domain_init(struct domain *d,
>                                   struct xen_domctl_createdomain *config)
>   {
> -    if ( !is_hardware_domain(d) )
> +    /*
> +     * scmi_passthrough is not enabled:
> +     * - proceed only for hw_domain
> +     * - fail if guest domain has SCMI enabled.
> +     */
> +    if ( !opt_scmi_smc_passthrough && !is_hardware_domain(d) )
> +    {
> +        if ( config->arch.arm_sci_type == XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC )
> +            return -EINVAL;
> +        else
> +            return 0;
> +    }
> +    /*
> +     * scmi_passthrough is enabled:
> +     * - ignore hw_domain
> +     * - proceed only for domain with SCMI enabled.
> +     */
> +    if ( opt_scmi_smc_passthrough &&
> +         (config->arch.arm_sci_type == XEN_DOMCTL_CONFIG_ARM_SCI_NONE ||
> +          is_hardware_domain(d)) )
>           return 0;
>   
> +    if ( scmi_dom )
> +        return -EEXIST;
> +
> +    scmi_dom = d;
>       d->arch.sci_enabled = true;
>       printk(XENLOG_DEBUG "SCMI: %pd init\n", d);
>       return 0;
> @@ -88,12 +127,77 @@ static int scmi_smc_domain_init(struct domain *d,
>   
>   static void scmi_smc_domain_destroy(struct domain *d)
>   {
> -    if ( !is_hardware_domain(d) )
> +    if ( scmi_dom && scmi_dom != d )
>           return;
>   
> +    scmi_dom = NULL;
> +    d->arch.sci_enabled = false;
>       printk(XENLOG_DEBUG "SCMI: %pd destroy\n", d);
>   }
>   
> +/*
> + * Handle Dom0 SCMI SMC specific DT nodes
> + *
> + * if scmi_smc_passthrough=false:
> + * - Copy SCMI nodes into Dom0 device tree.
> + * if scmi_smc_passthrough=true:
> + * - skip SCMI nodes from Dom0 DT
> + * - give dom0 control access to SCMI shmem MMIO, so SCMI can be passed
> + *   through to guest.
> + */
> +static bool scmi_smc_dt_handle_node(struct domain *d,
> +                                    struct dt_device_node *node)
> +{
> +    static const struct dt_device_match shmem_matches[] __initconst = {
> +        DT_MATCH_COMPATIBLE("arm,scmi-shmem"),
> +        { /* sentinel */ },
> +    };
> +    static const struct dt_device_match scmi_matches[] __initconst = {
> +        DT_MATCH_PATH("/firmware/scmi"),
> +        { /* sentinel */ },
> +    };
> +
> +    /* skip scmi shmem node for dom0 if scmi not enabled */
> +    if ( dt_match_node(shmem_matches, node) && !sci_domain_is_enabled(d) )
> +    {
> +        dt_dprintk("Skip scmi shmem node\n");
> +        return true;
> +    }
> +
> +    /*
> +     * skip scmi node for dom0 if scmi not enabled, but give dom0 control
> +     * access to SCMI shmem
> +     */
> +    if ( dt_match_node(scmi_matches, node) && !sci_domain_is_enabled(d) )
> +    {
> +        struct dt_device_node *shmem_node;
> +        const __be32 *prop;
> +        u64 paddr, size;

NIT: uint64_t please for the new code

> +        int ret;
> +
> +        /* give dom0 control access to SCMI shmem */
> +        prop = dt_get_property(node, "shmem", NULL);
> +        if ( !prop )
> +            return true;
> +
> +        shmem_node = dt_find_node_by_phandle(be32_to_cpu(*prop));
> +        if ( !shmem_node )
> +            return true;
> +
> +        ret = dt_device_get_address(shmem_node, 0, &paddr, &size);
> +        if ( ret )
> +            return true;
> +
> +        ret = iomem_permit_access(d, paddr_to_pfn(paddr),
> +                                  paddr_to_pfn(paddr + size - 1));

Shouldn't we at least warn if the access to SCMI shmem is not permitted 
for Dom0? Or this is not going to be an issue at all?


> +
> +        dt_dprintk("Skip scmi node\n");
> +        return true;
> +    }
> +
> +    return false;
> +}
> +
>   static int __init scmi_check_smccc_ver(void)
>   {
>       if ( smccc_ver < ARM_SMCCC_VERSION_1_1 )
> @@ -108,8 +212,10 @@ static int __init scmi_check_smccc_ver(void)
>   
>   static const struct sci_mediator_ops scmi_smc_ops = {
>       .handle_call = scmi_handle_smc,
> +    .domain_sanitise_config = scmi_smc_domain_sanitise_config,
>       .domain_init = scmi_smc_domain_init,
>       .domain_destroy = scmi_smc_domain_destroy,
> +    .dom0_dt_handle_node = scmi_smc_dt_handle_node,
>   };
>   
>   /* Initialize the SCMI layer based on SMCs and Device-tree */



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 0/2] x86/apic: Drop vestigial pieces (Intel VFM cleanup)
Date: Fri, 29 Aug 2025 17:17:08 +0100
Message-Id: <20250829161710.1056772-1-andrew.cooper3@citrix.com>
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Found while doing the Intel VFM cleanup.  This diffstat seems preforable to
simply dropping the x86_ prefixes on the field name.

Andrew Cooper (2):
  x86/apic: Get rid of get_physical_broadcast()
  x86/apic: Drop sync_Arb_IDs()

 xen/arch/x86/apic.c             | 40 ---------------------------------
 xen/arch/x86/include/asm/apic.h |  3 ---
 xen/arch/x86/io_apic.c          | 18 +++++++--------
 3 files changed, 9 insertions(+), 52 deletions(-)

-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 2/2] x86/apic: Drop sync_Arb_IDs()
Date: Fri, 29 Aug 2025 17:17:10 +0100
Message-Id: <20250829161710.1056772-3-andrew.cooper3@citrix.com>
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It is not obvious at first glance, but this is dead logic.

On Intel, xAPIC (which is what modern_apic() is really checking for) predates
64bit support, while the Family 0xf check on AMD is the K8 processor.

Simply drop the logic, rather than trying to adjust vendor/family logic.

Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

  add/remove: 0/1 grow/shrink: 0/1 up/down: 0/-166 (-166)
  Function                                     old     new   delta
  setup_IO_APIC                               2992    2987      -5
  sync_Arb_IDs                                 161       -    -161
---
 xen/arch/x86/apic.c             | 32 --------------------------------
 xen/arch/x86/include/asm/apic.h |  1 -
 xen/arch/x86/io_apic.c          |  2 +-
 3 files changed, 1 insertion(+), 34 deletions(-)

diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 70636b0bb585..774771860002 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -91,23 +91,6 @@ static enum apic_mode apic_boot_mode = APIC_MODE_INVALID;
 bool __read_mostly x2apic_enabled;
 bool __read_mostly directed_eoi_enabled;
 
-static int modern_apic(void)
-{
-    unsigned int lvr, version;
-    /* AMD systems use old APIC versions, so check the CPU */
-    if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-        boot_cpu_data.x86 >= 0xf)
-        return 1;
-
-    /* Hygon systems use modern APIC */
-    if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
-        return 1;
-
-    lvr = apic_read(APIC_LVR);
-    version = GET_APIC_VERSION(lvr);
-    return version >= 0x14;
-}
-
 /*
  * 'what should we do if we get a hw irq event on an illegal vector'.
  * each architecture has to answer this themselves.
@@ -396,21 +379,6 @@ int __init verify_local_APIC(void)
     return 1;
 }
 
-void __init sync_Arb_IDs(void)
-{
-    /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
-       And not needed on AMD */
-    if (modern_apic())
-        return;
-    /*
-     * Wait for idle.
-     */
-    apic_wait_icr_idle();
-
-    apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
-    apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);
-}
-
 /*
  * An initial setup of the virtual wire mode.
  */
diff --git a/xen/arch/x86/include/asm/apic.h b/xen/arch/x86/include/asm/apic.h
index d22854953689..918f1cee3567 100644
--- a/xen/arch/x86/include/asm/apic.h
+++ b/xen/arch/x86/include/asm/apic.h
@@ -166,7 +166,6 @@ extern void disconnect_bsp_APIC (int virt_wire_setup);
 extern void disable_local_APIC (void);
 extern int verify_local_APIC (void);
 extern void cache_APIC_registers (void);
-extern void sync_Arb_IDs (void);
 extern void init_bsp_APIC (void);
 extern void setup_local_APIC(bool bsp);
 extern void init_apic_mappings (void);
diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index 42a9b653d397..17e6827f4bb3 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -2163,7 +2163,7 @@ void __init setup_IO_APIC(void)
      */
     if (!acpi_ioapic)
         setup_ioapic_ids_from_mpc();
-    sync_Arb_IDs();
+
     setup_IO_APIC_irqs();
     init_IO_APIC_traps();
     check_timer();
-- 
2.39.5



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From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH 1/2] x86/apic: Get rid of get_physical_broadcast()
Date: Fri, 29 Aug 2025 17:17:09 +0100
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This is a port of Linux commit 517234446c1a ("x86/apic: Get rid of
get_physical_broadcast()") to Xen.  Thomas Gleixner notes:

  There is no point for this function. The only case where this is used is
  when there is no XAPIC available, which means the broadcast address is 0xF.

In Linux, users of get_physical_broadcast() have already been hidden behind
CONFIG_X86_32 suggesting we can drop all of this, but that's a task for some
other time.

In Xen as with Linux, setup_ioapic_ids_from_mpc() and io_apic_get_unique_id()
are only called in pre-xAPIC cases, so can use a broadcast ID of 0xf.  The
only other user is __print_IO_APIC() for diagnostics, which can simply drop
the check.

No functional change.

Link: https://lore.kernel.org/r/20240212154639.057209154@linutronix.de
Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 

  add/remove: 0/1 grow/shrink: 0/3 up/down: 0/-165 (-165)
  Function                                     old     new   delta
  __print_IO_APIC                              980     975      -5
  setup_IO_APIC                               3018    2992     -26
  io_apic_get_unique_id                        719     686     -33
  get_physical_broadcast                       101       -    -101
---
 xen/arch/x86/apic.c             |  8 --------
 xen/arch/x86/include/asm/apic.h |  2 --
 xen/arch/x86/io_apic.c          | 16 ++++++++--------
 3 files changed, 8 insertions(+), 18 deletions(-)

diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index e3a2b84f1aae..70636b0bb585 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -133,14 +133,6 @@ static bool __read_mostly using_apic_timer;
 
 static bool __read_mostly enabled_via_apicbase;
 
-int get_physical_broadcast(void)
-{
-    if (modern_apic())
-        return 0xff;
-    else
-        return 0xf;
-}
-
 int get_maxlvt(void)
 {
     unsigned int v = apic_read(APIC_LVR);
diff --git a/xen/arch/x86/include/asm/apic.h b/xen/arch/x86/include/asm/apic.h
index d8eda6df6d86..d22854953689 100644
--- a/xen/arch/x86/include/asm/apic.h
+++ b/xen/arch/x86/include/asm/apic.h
@@ -153,8 +153,6 @@ static inline u32 get_apic_id(void)
 
 void apic_wait_icr_idle(void);
 
-int get_physical_broadcast(void);
-
 static inline void ack_APIC_irq(void)
 {
 	/* Docs say use 0 for future compatibility */
diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c
index 1816e1c0b9f4..42a9b653d397 100644
--- a/xen/arch/x86/io_apic.c
+++ b/xen/arch/x86/io_apic.c
@@ -1217,8 +1217,6 @@ static void /*__init*/ __print_IO_APIC(bool boot)
 	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
 	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
-	if (reg_00.bits.ID >= get_physical_broadcast())
-            UNEXPECTED_IO_APIC();
 	if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
             UNEXPECTED_IO_APIC();
 
@@ -1475,6 +1473,7 @@ static void __init setup_ioapic_ids_from_mpc(void)
     int i;
     unsigned char old_id;
     unsigned long flags;
+    const uint32_t broadcast_id = 0xf;
 
     /*
      * Don't check I/O APIC IDs for xAPIC systems. They have
@@ -1504,7 +1503,7 @@ static void __init setup_ioapic_ids_from_mpc(void)
 		
         old_id = mp_ioapics[apic].mpc_apicid;
 
-        if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
+        if (mp_ioapics[apic].mpc_apicid >= broadcast_id) {
             printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
                    apic, mp_ioapics[apic].mpc_apicid);
             printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
@@ -1521,10 +1520,10 @@ static void __init setup_ioapic_ids_from_mpc(void)
         {
             printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
                    apic, mp_ioapics[apic].mpc_apicid);
-            for (i = 0; i < get_physical_broadcast(); i++)
+            for (i = 0; i < broadcast_id; i++)
                 if (!physid_isset(i, phys_id_present_map))
                     break;
-            if (i >= get_physical_broadcast())
+            if (i >= broadcast_id)
                 panic("Max APIC ID exceeded\n");
             printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
                    i);
@@ -2223,6 +2222,7 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
     static physid_mask_t __initdata apic_id_map = PHYSID_MASK_NONE;
     unsigned long flags;
     int i = 0;
+    const uint32_t broadcast_id = 0xf;
 
     /*
      * The P4 platform supports up to 256 APIC IDs on two separate APIC 
@@ -2240,7 +2240,7 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
     reg_00.raw = io_apic_read(ioapic, 0);
     spin_unlock_irqrestore(&ioapic_lock, flags);
 
-    if (apic_id >= get_physical_broadcast()) {
+    if (apic_id >= broadcast_id) {
         printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
                "%d\n", ioapic, apic_id, reg_00.bits.ID);
         apic_id = reg_00.bits.ID;
@@ -2253,12 +2253,12 @@ int __init io_apic_get_unique_id (int ioapic, int apic_id)
     if ( physid_isset(apic_id, apic_id_map) )
     {
 
-        for (i = 0; i < get_physical_broadcast(); i++) {
+        for (i = 0; i < broadcast_id; i++) {
             if ( !physid_isset(i, apic_id_map) )
                 break;
         }
 
-        if (i == get_physical_broadcast())
+        if (i == broadcast_id)
             panic("Max apic_id exceeded\n");
 
         printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
-- 
2.39.5



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Hi everyone,

Don't forget that our September community call is scheduled for Thursday
September 4 @ 15:00 UTC.

I'll send out a proposed agenda at the beginning of the week, but I wanted
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I'm looking forward to seeing you on Thursday!

Have a great weekend,

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    Hi everyone,

    Don't forget that our September community=C2=A0call is scheduled for=
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    I'll send o=
ut a proposed agenda at the beginning=C2=A0of the week, but I wanted to sen=
d out a friendly reminder before the weekend.

    I=
9;m looking forward to seeing you on Thursday!

    Hav=
e a great weekend,

    Cody Zuschlag
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--0000000000001edbf0063d837c47--


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Date: Fri, 29 Aug 2025 11:44:57 -0700
From: Elliott Mitchell 
To: Julien Grall 
Cc: Jan Beulich ,
        Demi Marie Obenour ,
        xen-users@lists.xenproject.org, xen-devel@lists.xenproject.org,
        Stefano Stabellini ,
        Bertrand Marquis ,
        Michal Orzel ,
        Volodymyr Babchuk ,
        Paul Leiber 
Subject: Re: Consider changing CONFIG_ACPI default on ARM?
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On Sat, Aug 23, 2025 at 08:59:13AM +0100, Julien Grall wrote:
> 
> On 22/08/2025 21:09, Elliott Mitchell wrote:
> > There may be many more using it.  Perhaps this
> > should even be done on the 4.20 branch given how long this has been
> > working?
> 
> I am guessing you mean 4.21 which will be released in a couple of months
> time, correct?
> 
> We have been discussing among the committers on whether we are ok to enable
> ACPI despite the fact it is still not feature complete (see above). The
> discussion is not fully finalized but if we were to enable CONFIG_ACPI=y by
> default then I think we would need the following:
> 
>  * Select device-tree by default rather than ACPI

This appears to be the case.  `arm_smmu_device_probe()` only calls
`arm_smmu_device_acpi_probe()` if the SMMUv3 is absent from the
device-tree.  The file appears laced with assumptions about device-tree
support being enabled so I think this is the present state.

>  * Go through SUPPORT.MD and check what features we marked as SUPPORTED.md
> but doesn't work on ACPI.
> 
> Maybe you can help with that?

The only things which stood out to me was SMMUv1/SMMUv2/SMMUv3.  Since
SMMUv3 is marked experimental anyway, this doesn't seem to be a problem.

Note, I haven't been looking too closely at things so my look isn't all
that much better than than an Ouija board.

Mostly it seems multiple people have found rebuilding Debian's packages
and enabling ACPI was the best way of getting Debian/Xen on a RP4.  The
lack of bugs seems to suggest ACPI works quite well.  The downsides are
limits in what ACPI supports and needing to rebuild.


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Date: Fri, 29 Aug 2025 12:27:13 -0700
From: Stefano Stabellini 
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Subject: Re: [PATCH v5 01/15] emul/vuart: introduce framework for UART
 emulators
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On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> From: Denis Mukhin  
> 
> Introduce a driver framework to abstract UART emulators in the hypervisor.
> 
> That allows for architecture-independent handling of virtual UARTs in the
> console driver and simplifies enabling new UART emulators.
> 
> The framework is built under CONFIG_VUART_FRAMEWORK, which will be
> automatically enabled once the user enables any UART emulator.
> 
> Current implementation supports maximum of one vUART of each kind per domain.
> 
> Use new domain_has_vuart() in the console driver code to check whether to
> forward console input to the domain using vUART.
> 
> Enable console forwarding over vUART for hardware domains with a vUART. That
> enables console forwarding to dom0 on x86, since console can be forwarded only
> to Xen, dom0 and pvshim on x86 as of now.
> 
> Note: existing vUARTs are deliberately *not* hooked to the new framework to
> minimize the scope of the patch: vpl011 (i.e. SBSA) emulator and "vuart" (i.e.
> minimalistic MMIO-mapped dtuart for hwdoms on Arm) are kept unmodified.
> 
> No functional changes for non-x86 architectures.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v4:
> - addressed feedback
> - Link to v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-3-dmukhin@ford.com/
> ---
>  xen/arch/arm/xen.lds.S         |   1 +
>  xen/arch/ppc/xen.lds.S         |   1 +
>  xen/arch/riscv/xen.lds.S       |   1 +
>  xen/arch/x86/xen.lds.S         |   1 +
>  xen/common/Kconfig             |   2 +
>  xen/common/Makefile            |   1 +
>  xen/common/emul/Kconfig        |   6 ++
>  xen/common/emul/Makefile       |   1 +
>  xen/common/emul/vuart/Kconfig  |   6 ++
>  xen/common/emul/vuart/Makefile |   1 +
>  xen/common/emul/vuart/vuart.c  | 156 +++++++++++++++++++++++++++++++++
>  xen/common/keyhandler.c        |   3 +
>  xen/drivers/char/console.c     |   6 +-
>  xen/include/xen/serial.h       |   3 +
>  xen/include/xen/vuart.h        | 116 ++++++++++++++++++++++++
>  xen/include/xen/xen.lds.h      |  10 +++
>  16 files changed, 314 insertions(+), 1 deletion(-)
>  create mode 100644 xen/common/emul/Kconfig
>  create mode 100644 xen/common/emul/Makefile
>  create mode 100644 xen/common/emul/vuart/Kconfig
>  create mode 100644 xen/common/emul/vuart/Makefile
>  create mode 100644 xen/common/emul/vuart/vuart.c
>  create mode 100644 xen/include/xen/vuart.h
> 
> diff --git a/xen/arch/arm/xen.lds.S b/xen/arch/arm/xen.lds.S
> index db17ff1efa98..cd05b18770f4 100644
> --- a/xen/arch/arm/xen.lds.S
> +++ b/xen/arch/arm/xen.lds.S
> @@ -58,6 +58,7 @@ SECTIONS
>         *(.rodata)
>         *(.rodata.*)
>         VPCI_ARRAY
> +       VUART_ARRAY
>         *(.data.rel.ro)
>         *(.data.rel.ro.*)
>  
> diff --git a/xen/arch/ppc/xen.lds.S b/xen/arch/ppc/xen.lds.S
> index 1de0b77fc6b9..f9d4e5b0dcd8 100644
> --- a/xen/arch/ppc/xen.lds.S
> +++ b/xen/arch/ppc/xen.lds.S
> @@ -52,6 +52,7 @@ SECTIONS
>          *(.rodata)
>          *(.rodata.*)
>          VPCI_ARRAY
> +        VUART_ARRAY
>          *(.data.rel.ro)
>          *(.data.rel.ro.*)
>  
> diff --git a/xen/arch/riscv/xen.lds.S b/xen/arch/riscv/xen.lds.S
> index edcadff90bfe..59dcaa5fef9a 100644
> --- a/xen/arch/riscv/xen.lds.S
> +++ b/xen/arch/riscv/xen.lds.S
> @@ -47,6 +47,7 @@ SECTIONS
>          *(.rodata)
>          *(.rodata.*)
>          VPCI_ARRAY
> +        VUART_ARRAY
>          *(.data.rel.ro)
>          *(.data.rel.ro.*)
>  
> diff --git a/xen/arch/x86/xen.lds.S b/xen/arch/x86/xen.lds.S
> index 966e514f2034..d877b93a6964 100644
> --- a/xen/arch/x86/xen.lds.S
> +++ b/xen/arch/x86/xen.lds.S
> @@ -132,6 +132,7 @@ SECTIONS
>         *(.rodata)
>         *(.rodata.*)
>         VPCI_ARRAY
> +       VUART_ARRAY
>         *(.data.rel.ro)
>         *(.data.rel.ro.*)
>  
> diff --git a/xen/common/Kconfig b/xen/common/Kconfig
> index 76f9ce705f7a..78a32b69e2b2 100644
> --- a/xen/common/Kconfig
> +++ b/xen/common/Kconfig
> @@ -676,4 +676,6 @@ config PM_STATS
>  	  Enable collection of performance management statistics to aid in
>  	  analyzing and tuning power/performance characteristics of the system
>  
> +source "common/emul/Kconfig"
> +
>  endmenu
> diff --git a/xen/common/Makefile b/xen/common/Makefile
> index c316957fcb36..c0734480ee4b 100644
> --- a/xen/common/Makefile
> +++ b/xen/common/Makefile
> @@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o
>  obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/
>  obj-$(CONFIG_IOREQ_SERVER) += dm.o
>  obj-y += domain.o
> +obj-y += emul/
>  obj-y += event_2l.o
>  obj-y += event_channel.o
>  obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o
> diff --git a/xen/common/emul/Kconfig b/xen/common/emul/Kconfig
> new file mode 100644
> index 000000000000..7c6764d1756b
> --- /dev/null
> +++ b/xen/common/emul/Kconfig
> @@ -0,0 +1,6 @@
> +menu "Domain Emulation Features"
> +	visible if EXPERT
> +
> +source "common/emul/vuart/Kconfig"
> +
> +endmenu
> diff --git a/xen/common/emul/Makefile b/xen/common/emul/Makefile
> new file mode 100644
> index 000000000000..ae0b575c3901
> --- /dev/null
> +++ b/xen/common/emul/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_VUART_FRAMEWORK) += vuart/
> diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kconfig
> new file mode 100644
> index 000000000000..ce1b976b7da7
> --- /dev/null
> +++ b/xen/common/emul/vuart/Kconfig
> @@ -0,0 +1,6 @@
> +config VUART_FRAMEWORK
> +	bool
> +
> +menu "UART Emulation"
> +
> +endmenu
> diff --git a/xen/common/emul/vuart/Makefile b/xen/common/emul/vuart/Makefile
> new file mode 100644
> index 000000000000..97f792dc6641
> --- /dev/null
> +++ b/xen/common/emul/vuart/Makefile
> @@ -0,0 +1 @@
> +obj-y += vuart.o
> diff --git a/xen/common/emul/vuart/vuart.c b/xen/common/emul/vuart/vuart.c
> new file mode 100644
> index 000000000000..7b277d00d5c7
> --- /dev/null
> +++ b/xen/common/emul/vuart/vuart.c
> @@ -0,0 +1,156 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UART emulator framework.
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define for_each_emulator(e) \
> +    for ( e = vuart_array_start; e < vuart_array_end; e++ )
> +
> +extern const struct vuart_emulator vuart_array_start[];
> +extern const struct vuart_emulator vuart_array_end[];
> +
> +static const struct vuart_emulator *
> +vuart_match_by_compatible(struct domain *d, const char *compat)
> +{
> +    const struct vuart_emulator *emulator;
> +
> +    if ( d->console.vuart )
> +        return NULL;
> +
> +    for_each_emulator(emulator)
> +        if ( emulator->compatible &&
> +             !strncmp(emulator->compatible, compat,
> +                      strlen(emulator->compatible)) )

strncmp will continue until the given count even if compat is shorter


> +            return emulator;
> +
> +    return NULL;
> +}
> +
> +static struct vuart *vuart_find_by_console_permission(const struct domain *d)
> +{
> +    struct vuart *vuart = d->console.vuart;
> +
> +    ASSERT(d->console.input_allowed);

This ASSERT looks suspicious as we haven't even checked that vuart!=NULL
yet. I would remove it


> +    if ( !vuart || !vuart->emulator || !vuart->emulator->put_rx ||
> +         !(vuart->flags & VUART_CONSOLE_INPUT))
> +        return NULL;
> +
> +    return vuart;
> +}
> +
> +struct vuart *vuart_find_by_io_range(struct domain *d, unsigned long addr,
> +                                     unsigned long size)
> +{
> +    struct vuart *vuart = d->console.vuart;
> +
> +    if ( !vuart || !vuart->info )
> +        return NULL;

You might as well call vuart_find_by_console_permission that has all the
checks already

> +
> +    if ( addr >= vuart->info->base_addr &&
> +         addr + size - 1 <= vuart->info->base_addr + vuart->info->size - 1 )
> +        return vuart;
> +
> +    return NULL;
> +}
> +
> +int vuart_init(struct domain *d, struct vuart_info *info)
> +{
> +    const struct vuart_emulator *emulator;
> +    struct vuart *vuart;
> +    int rc;
> +
> +    emulator = vuart_match_by_compatible(d, info->compatible);
> +    if ( !emulator )
> +        return -ENODEV;
> +
> +    vuart = xzalloc(typeof(*vuart));
> +    if ( !vuart )
> +        return -ENOMEM;
> +
> +    vuart->info = xvzalloc(typeof(*info));
> +    if ( !vuart->info )
> +    {
> +        rc = -ENOMEM;
> +        goto err_out;
> +    }
> +    memcpy(vuart->info, info, sizeof(*info));

one thing to note is that the fields (strings) compatible and name are
copied by address, I am not if it is OK but FYI


> +    vuart->vdev = emulator->alloc(d, vuart->info);
> +    if ( IS_ERR(vuart->vdev) )
> +    {
> +        rc = PTR_ERR(vuart->vdev);
> +        goto err_out;

this path leads to vuart->info not being freed


> +    }
> +
> +    vuart->emulator = emulator;
> +    vuart->owner = d;
> +    vuart->flags |= VUART_CONSOLE_INPUT;
> +
> +    d->console.input_allowed = true;
> +    d->console.vuart = vuart;
> +
> +    return 0;
> +
> + err_out:
> +    XVFREE(vuart);
> +    return rc;
> +}
> +
> +/*
> + * Release any resources taken by UART emulators.
> + *
> + * NB: no flags are cleared, since currently exit() is called only during
> + * domain destroy.
> + */
> +void vuart_deinit(struct domain *d)
> +{
> +    struct vuart *vuart = d->console.vuart;
> +
> +    if ( vuart )
> +    {
> +        vuart->emulator->free(vuart);

should we pass vuart or vuart->vdev here? The emulator state is supposed
to be vuart->vdev?

> +        XVFREE(vuart->info);
> +    }
> +
> +    XVFREE(d->console.vuart);
> +}
> +
> +void vuart_dump_state(const struct domain *d)
> +{
> +    struct vuart *vuart = d->console.vuart;
> +
> +    if ( vuart )
> +        vuart->emulator->dump_state(vuart);

also here vuart->vdev?


> +}
> +
> +/*
> + * Put character to the *first* suitable emulated UART's FIFO.
> + */
> +int vuart_put_rx(struct domain *d, char c)
> +{
> +    struct vuart *vuart = vuart_find_by_console_permission(d);
> +
> +    return vuart ? vuart->emulator->put_rx(vuart, c) : -ENODEV;

and here?


> +}
> +
> +bool domain_has_vuart(const struct domain *d)
> +{
> +    return vuart_find_by_console_permission(d);
> +}
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/common/keyhandler.c b/xen/common/keyhandler.c
> index cb6df2823b00..156e64d9eb58 100644
> --- a/xen/common/keyhandler.c
> +++ b/xen/common/keyhandler.c
> @@ -22,6 +22,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  
>  static unsigned char keypress_key;
> @@ -352,6 +353,8 @@ static void cf_check dump_domains(unsigned char key)
>                             v->periodic_period / 1000000);
>              }
>          }
> +
> +        vuart_dump_state(d);
>      }
>  
>      for_each_domain ( d )
> diff --git a/xen/drivers/char/console.c b/xen/drivers/char/console.c
> index 9bd5b4825da6..d5164897a776 100644
> --- a/xen/drivers/char/console.c
> +++ b/xen/drivers/char/console.c
> @@ -33,6 +33,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #ifdef CONFIG_X86
>  #include 
> @@ -596,11 +597,12 @@ static void __serial_rx(char c)
>      if ( !d )
>          return;
>  
> -    if ( is_hardware_domain(d) )
> +    if ( is_hardware_domain(d) && !domain_has_vuart(d) )
>      {
>          /*
>           * Deliver input to the hardware domain buffer, unless it is
>           * already full.
> +         * NB: must be the first check: hardware domain may have emulated UART.
>           */
>          if ( (serial_rx_prod - serial_rx_cons) != SERIAL_RX_SIZE )
>              serial_rx_ring[SERIAL_RX_MASK(serial_rx_prod++)] = c;
> @@ -611,6 +613,8 @@ static void __serial_rx(char c)
>           */
>          send_global_virq(VIRQ_CONSOLE);
>      }
> +    else if ( domain_has_vuart(d) )
> +        rc = vuart_put_rx(d, c);
>  #ifdef CONFIG_SBSA_VUART_CONSOLE
>      else
>          /* Deliver input to the emulated UART. */
> diff --git a/xen/include/xen/serial.h b/xen/include/xen/serial.h
> index 8e1844555208..d7e81f098359 100644
> --- a/xen/include/xen/serial.h
> +++ b/xen/include/xen/serial.h
> @@ -36,6 +36,9 @@ struct vuart_info {
>      unsigned long data_off;     /* Data register offset */
>      unsigned long status_off;   /* Status register offset */
>      unsigned long status;       /* Ready status value */
> +    unsigned int irq;           /* Interrupt */
> +    const char *compatible;     /* Compatible string */
> +    const char *name;           /* User-friendly name */
>  };
>  
>  struct serial_port {
> diff --git a/xen/include/xen/vuart.h b/xen/include/xen/vuart.h
> new file mode 100644
> index 000000000000..ca025b4179be
> --- /dev/null
> +++ b/xen/include/xen/vuart.h
> @@ -0,0 +1,116 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * UART emulator framework.
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#ifndef XEN_VUART_H
> +#define XEN_VUART_H
> +
> +#include 
> +#include 
> +
> +struct vuart_emulator;
> +
> +enum {
> +    VUART_CONSOLE_INPUT = 0U << 1, /** Physical console input forwarding. */

code style: single *
This flag is zero, is that intended?


> +};
> +
> +
> +/*
> + * FIXME: #ifdef is temporary to avoid clash with
> + *   arch/arm/include/asm/domain.h
> + */
> +#ifdef CONFIG_VUART_FRAMEWORK
> +struct vuart {
> +    const struct vuart_emulator *emulator;
> +    struct vuart_info *info;
> +    struct domain *owner;
> +    uint32_t flags;
> +    void *vdev;
> +};
> +#endif
> +
> +struct vuart_emulator {
> +    /* UART compatible string. Cannot be NULL or empty. */
> +    const char *compatible;
> +
> +    /*
> +     * Allocate emulated UART state (RX/TX FIFOs, locks, initialize registers,
> +     * hook I/O handlers, etc.)
> +     * Cannot be NULL.
> +     */
> +    void *(*alloc)(struct domain *d, const struct vuart_info *info);
> +
> +    /*
> +     * Release resources used to emulate UART state (flush RX/TX FIFOs, unhook
> +     * I/O handlers, etc.).
> +     * Cannot be NULL.
> +     */
> +    void (*free)(void *arg);
> +
> +    /*
> +     * Print emulated UART state, including registers, on the console.
> +     * Can be NULL.
> +     */
> +    void (*dump_state)(void *arg);
> +
> +    /*
> +     * Place character to the emulated RX FIFO.
> +     * Used to forward physical console input to the guest OS.
> +     * Can be NULL.
> +     */
> +    int (*put_rx)(void *arg, char c);
> +};
> +
> +#define VUART_REGISTER(name, x) \
> +    static const struct vuart_emulator name##_entry \
> +        __used_section(".data.rel.ro.vuart") = x
> +
> +struct vuart *vuart_find_by_io_range(struct domain *d,
> +                                     unsigned long base_addr,
> +                                     unsigned long size);
> +
> +int vuart_put_rx(struct domain *d, char c);
> +
> +#ifdef CONFIG_VUART_FRAMEWORK
> +
> +int vuart_init(struct domain *d, struct vuart_info *info);
> +void vuart_deinit(struct domain *d);
> +void vuart_dump_state(const struct domain *d);
> +bool domain_has_vuart(const struct domain *d);
> +
> +#else
> +
> +static inline int vuart_init(struct domain *d, struct vuart_info *info)
> +{
> +    return 0;
> +}
> +
> +static inline void vuart_deinit(struct domain *d)
> +{
> +}
> +
> +static inline void vuart_dump_state(const struct domain *d)
> +{
> +}
> +
> +static inline bool domain_has_vuart(const struct domain *d)
> +{
> +    return false;
> +}
> +
> +#endif /* CONFIG_VUART_FRAMEWORK */
> +
> +#endif /* XEN_VUART_H */
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> +
> diff --git a/xen/include/xen/xen.lds.h b/xen/include/xen/xen.lds.h
> index b126dfe88792..2d65f32ddad3 100644
> --- a/xen/include/xen/xen.lds.h
> +++ b/xen/include/xen/xen.lds.h
> @@ -194,4 +194,14 @@
>  #define VPCI_ARRAY
>  #endif
>  
> +#ifdef CONFIG_VUART_FRAMEWORK
> +#define VUART_ARRAY              \
> +       . = ALIGN(POINTER_ALIGN); \
> +       vuart_array_start = .;    \
> +       *(.data.rel.ro.vuart)     \
> +       vuart_array_end = .;
> +#else
> +#define VUART_ARRAY
> +#endif
> +
>  #endif /* __XEN_LDS_H__ */
> -- 
> 2.51.0
> 


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        Fri, 29 Aug 2025 12:29:43 -0700 (PDT)
From: Andrew Cooper 
To: Xen-devel 
Cc: Andrew Cooper ,
	Jan Beulich ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= 
Subject: [PATCH] x86/gen-cpuid: Fix debugging for cycle detection
Date: Fri, 29 Aug 2025 20:29:39 +0100
Message-Id: <20250829192939.1090358-1-andrew.cooper3@citrix.com>
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Jan reports the following exception when using the cycle debugging:

  Feature IBRSB, seen [IBRSB, STIBP, INTEL_PSFD, EIBRS, IPRED_CTRL, RRSBA_CTRL, RRSBA, BHI_CTRL], to_process [SSBD]
  Traceback (most recent call last):
    File "/local/xen.git/xen/../xen/tools/gen-cpuid.py", line 594, in 
      sys.exit(main())
               ^^^^^^
    File "/local/xen.git/xen/../xen/tools/gen-cpuid.py", line 588, in main
      crunch_numbers(state)
    File "/local/xen.git/xen/../xen/tools/gen-cpuid.py", line 366, in crunch_numbers
      (state.names[feat], repl(seen), repl(to_process)))
                                      ^^^^^^^^^^^^^^^^
    File "/local/xen.git/xen/../xen/tools/gen-cpuid.py", line 364, in repl
      return "[" + ", ".join((state.names[x] for x in l)) + "]"
                   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
    File "/local/xen.git/xen/../xen/tools/gen-cpuid.py", line 364, in 
      return "[" + ", ".join((state.names[x] for x in l)) + "]"
                              ~~~~~~~~~~~^^^
  KeyError: 534
  make[2]: *** [/local/xen.git/xen/include/xen/lib/x86/Makefile:9: cpuid-autogen.h] Error 1

This is caused by commit ce8c930851a5 ("x86/cpu-policy: MSR_ARCH_CAPS feature
names") being rather lazy and marking dependenices on unknown features.

Introduce a helper to pick the known features in a range, and use it for
ARCH_CAPS.

Additionally, remove trailing whitepsace from the debug print.

Reported-by: Jan Beulich 
Fixes: ce8c930851a5 ("x86/cpu-policy: MSR_ARCH_CAPS feature names")
Signed-off-by: Andrew Cooper 
---
CC: Jan Beulich 
CC: Roger Pau Monné 
---
 xen/tools/gen-cpuid.py | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 6f96d1368e9e..403369aedcd9 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -168,6 +168,10 @@ def crunch_numbers(state):
     state.hvm_shadow_max = state.pv_max         | state.raw['S'] | state.raw['s']
     state.hvm_hap_max =    state.hvm_shadow_max | state.raw['H'] | state.raw['h']
 
+    def feat_range(start, last):
+        """ Select all known features in the given range """
+        return [ x for x in state.names.keys() if start <= x <= last ]
+
     #
     # Feature dependency information.
     #
@@ -338,7 +342,7 @@ def crunch_numbers(state):
         PSFD: [EPSF],
 
         # The ARCH_CAPS CPUID bit enumerates the availability of the whole register.
-        ARCH_CAPS: list(range(RDCL_NO, RDCL_NO + 64)),
+        ARCH_CAPS: feat_range(RDCL_NO, RDCL_NO + 63),
 
         # The behaviour described by RRSBA depend on eIBRS being active.
         EIBRS: [RRSBA],
@@ -362,7 +366,7 @@ def crunch_numbers(state):
             # To debug, uncomment the following lines:
             # def repl(l):
             #     return "[" + ", ".join((state.names[x] for x in l)) + "]"
-            # sys.stderr.write("Feature %s, seen %s, to_process %s \n" % \
+            # sys.stderr.write("Feature %s, seen %s, to_process %s\n" % \
             #     (state.names[feat], repl(seen), repl(to_process)))
 
             f = to_process.pop(0)

base-commit: e7c689a249ca6b8d14a077bb0f3311eaeda2ca19
-- 
2.39.5



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Date: Fri, 29 Aug 2025 12:32:46 -0700 (PDT)
From: Stefano Stabellini 
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To: dmukhin@xen.org
cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, 
    dmukhin@ford.com
Subject: Re: [PATCH v5 02/15] xen/8250-uart: update definitions
In-Reply-To: <20250828235409.2835815-3-dmukhin@ford.com>
Message-ID: 
References: <20250828235409.2835815-1-dmukhin@ford.com> <20250828235409.2835815-3-dmukhin@ford.com>
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On Thu, 27 Aug 2025, dmukhin@xen.org wrote:
> From: Denis Mukhin  
> 
> Added missing definitions needed for NS16550 UART emulator.
> 
> Newly introduced MSR definitions re-used in the existing ns16550 driver.
> 
> Also, corrected FCR DMA definition bit#3 (0x08) as per:
>   https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
> See "7.7.2 FIFO Control Register (FCR)".
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v4:
> - reused newly introduced UART_IIR and UART_IER bits in ns16550 driver
> - Link to v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-5-dmukhin@ford.com/
> ---
>  xen/drivers/char/ns16550.c  | 16 ++++++------
>  xen/include/xen/8250-uart.h | 50 ++++++++++++++++++++++++++++++-------
>  2 files changed, 49 insertions(+), 17 deletions(-)
> 
> diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
> index df7fff7f81df..0e80fadbb894 100644
> --- a/xen/drivers/char/ns16550.c
> +++ b/xen/drivers/char/ns16550.c
> @@ -388,7 +388,7 @@ static void __init cf_check ns16550_init_preirq(struct serial_port *port)
>  
>      /* Check this really is a 16550+. Otherwise we have no FIFOs. */
>      if ( uart->fifo_size <= 1 &&
> -         ((ns_read_reg(uart, UART_IIR) & 0xc0) == 0xc0) &&
> +         ((ns_read_reg(uart, UART_IIR) & UART_IIR_FE) == UART_IIR_FE) &&
>           ((ns_read_reg(uart, UART_FCR) & UART_FCR_TRG14) == UART_FCR_TRG14) )
>          uart->fifo_size = 16;
>  }
> @@ -728,20 +728,20 @@ static int __init check_existence(struct ns16550 *uart)
>       * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
>       * 16C754B) allow only to modify them if an EFR bit is set.
>       */
> -    scratch2 = ns_read_reg(uart, UART_IER) & 0x0f;
> -    ns_write_reg(uart,UART_IER, 0x0F);
> -    scratch3 = ns_read_reg(uart, UART_IER) & 0x0f;
> +    scratch2 = ns_read_reg(uart, UART_IER) & UART_IER_MASK;
> +    ns_write_reg(uart, UART_IER, UART_IER_MASK);
> +    scratch3 = ns_read_reg(uart, UART_IER) & UART_IER_MASK;
>      ns_write_reg(uart, UART_IER, scratch);
> -    if ( (scratch2 != 0) || (scratch3 != 0x0F) )
> +    if ( (scratch2 != 0) || (scratch3 != UART_IER_MASK) )
>          return 0;
>  
>      /*
>       * Check to see if a UART is really there.
>       * Use loopback test mode.
>       */
> -    ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | 0x0A);
> -    status = ns_read_reg(uart, UART_MSR) & 0xF0;
> -    return (status == 0x90);
> +    ns_write_reg(uart, UART_MCR, UART_MCR_LOOP | UART_MCR_RTS | UART_MCR_OUT2);
> +    status = ns_read_reg(uart, UART_MSR) & UART_MSR_STATUS;
> +    return (status == (UART_MSR_CTS | UART_MSR_DCD));
>  }
>  
>  #ifdef CONFIG_HAS_PCI
> diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h
> index d13352940c13..bc11cdc376c9 100644
> --- a/xen/include/xen/8250-uart.h
> +++ b/xen/include/xen/8250-uart.h
> @@ -32,6 +32,7 @@
>  #define UART_MCR          0x04    /* Modem control        */
>  #define UART_LSR          0x05    /* line status          */
>  #define UART_MSR          0x06    /* Modem status         */
> +#define UART_SCR          0x07    /* Scratch pad          */
>  #define UART_USR          0x1f    /* Status register (DW) */
>  #define UART_DLL          0x00    /* divisor latch (ls) (DLAB=1) */
>  #define UART_DLM          0x01    /* divisor latch (ms) (DLAB=1) */
> @@ -42,6 +43,8 @@
>  #define UART_IER_ETHREI   0x02    /* tx reg. empty        */
>  #define UART_IER_ELSI     0x04    /* rx line status       */
>  #define UART_IER_EMSI     0x08    /* MODEM status         */
> +#define UART_IER_MASK \
> +    (UART_IER_ERDAI | UART_IER_ETHREI | UART_IER_ELSI | UART_IER_EMSI)
>  
>  /* Interrupt Identification Register */
>  #define UART_IIR_NOINT    0x01    /* no interrupt pending */
> @@ -51,12 +54,19 @@
>  #define UART_IIR_THR      0x02    /*  - tx reg. empty     */
>  #define UART_IIR_MSI      0x00    /*  - MODEM status      */
>  #define UART_IIR_BSY      0x07    /*  - busy detect (DW) */
> +#define UART_IIR_FE       0xc0    /* FIFO enabled (2 bits) */
>  
>  /* FIFO Control Register */
> -#define UART_FCR_ENABLE   0x01    /* enable FIFO          */
> -#define UART_FCR_CLRX     0x02    /* clear Rx FIFO        */
> -#define UART_FCR_CLTX     0x04    /* clear Tx FIFO        */
> -#define UART_FCR_DMA      0x10    /* enter DMA mode       */
> +#define UART_FCR_ENABLE     BIT(0, U)   /* enable FIFO          */
> +#define UART_FCR_CLRX       BIT(1, U)   /* clear Rx FIFO        */
> +#define UART_FCR_CLTX       BIT(2, U)   /* clear Tx FIFO        */
> +#define UART_FCR_DMA        BIT(3, U)   /* enter DMA mode       */
> +#define UART_FCR_RESERVED0  BIT(4, U)   /* reserved; always 0   */
> +#define UART_FCR_RESERVED1  BIT(5, U)   /* reserved; always 0   */
> +#define UART_FCR_RTB0       BIT(6, U)   /* receiver trigger bit #0 */
> +#define UART_FCR_RTB1       BIT(7, U)   /* receiver trigger bit #1 */
> +#define UART_FCR_TRG_MASK   (UART_FCR_RTB0 | UART_FCR_RTB1)
> +
>  #define UART_FCR_TRG1     0x00    /* Rx FIFO trig lev 1   */
>  #define UART_FCR_TRG4     0x40    /* Rx FIFO trig lev 4   */
>  #define UART_FCR_TRG8     0x80    /* Rx FIFO trig lev 8   */
> @@ -96,11 +106,32 @@
>  #define UART_LCR_CONF_MODE_B	0xBF		/* Configuration mode B */
>  
>  /* Modem Control Register */
> -#define UART_MCR_DTR      0x01    /* Data Terminal Ready  */
> -#define UART_MCR_RTS      0x02    /* Request to Send      */
> -#define UART_MCR_OUT2     0x08    /* OUT2: interrupt mask */
> -#define UART_MCR_LOOP     0x10    /* Enable loopback test mode */
> -#define UART_MCR_TCRTLR   0x40    /* Access TCR/TLR (TI16C752, EFR[4]=1) */
> +#define UART_MCR_DTR            BIT(0, U)   /* Data Terminal Ready  */
> +#define UART_MCR_RTS            BIT(1, U)   /* Request to Send      */
> +#define UART_MCR_OUT1           BIT(2, U)   /* OUT1: interrupt mask */

is OUT1 an interrupt mask actually?


> +#define UART_MCR_OUT2           BIT(3, U)   /* OUT2: interrupt mask */
> +#define UART_MCR_LOOP           BIT(4, U)   /* Enable loopback test mode */
> +#define UART_MCR_RESERVED0      BIT(5, U)   /* Reserved #0 */
> +#define UART_MCR_TCRTLR         BIT(6, U)   /* Access TCR/TLR (TI16C752, EFR[4]=1) */
> +#define UART_MCR_RESERVED1      BIT(7, U)   /* Reserved #1 */
> +#define UART_MCR_MASK \
> +    (UART_MCR_DTR | UART_MCR_RTS | \
> +     UART_MCR_OUT1 | UART_MCR_OUT2 | \
> +     UART_MCR_LOOP | UART_MCR_TCRTLR)
> +
> +/* Modem Status Register */
> +#define UART_MSR_DCTS           BIT(0, U)   /* Change in CTS */
> +#define UART_MSR_DDSR           BIT(1, U)   /* Change in DSR */
> +#define UART_MSR_TERI           BIT(2, U)   /* Change in RI */
> +#define UART_MSR_DDCD           BIT(3, U)   /* Change in CTS */

Changes in DCD, can be done on commit


> +#define UART_MSR_CTS            BIT(4, U)
> +#define UART_MSR_DSR            BIT(5, U)
> +#define UART_MSR_RI             BIT(6, U)
> +#define UART_MSR_DCD            BIT(7, U)
> +#define UART_MSR_CHANGE \
> +    (UART_MSR_DCTS | UART_MSR_DDSR | UART_MSR_TERI | UART_MSR_DDCD)
> +#define UART_MSR_STATUS \
> +    (UART_MSR_CTS | UART_MSR_DSR | UART_MSR_RI | UART_MSR_DCD)
>  
>  /* Line Status Register */
>  #define UART_LSR_DR       0x01    /* Data ready           */
> @@ -111,6 +142,7 @@
>  #define UART_LSR_THRE     0x20    /* Xmit hold reg empty  */
>  #define UART_LSR_TEMT     0x40    /* Xmitter empty        */
>  #define UART_LSR_ERR      0x80    /* Error                */
> +#define UART_LSR_MASK     (UART_LSR_OE | UART_LSR_BI)
>  
>  /* These parity settings can be ORed directly into the LCR. */
>  #define UART_PARITY_NONE  (0<<3)
> -- 
> 2.51.0
> 


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v5 04/12] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Topic: [PATCH v5 04/12] xen/arm/irq: add handling for IRQs in the eSPI
 range
Thread-Index: AQHcGP7cvDFEqdT0B0atuMEMYN3Piw==
Date: Fri, 29 Aug 2025 19:45:58 +0000
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References: 
	
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Hi Leonid,

Leonid Komarianskyi  writes:

> Currently, Xen does not support eSPI interrupts, leading
> to a data abort when such interrupts are defined in the DTS.
>
> This patch introduces a separate array to initialize up to
> 1024 interrupt descriptors in the eSPI range and adds the
> necessary defines and helper function. These changes lay the
> groundwork for future implementation of full eSPI interrupt
> support. As this GICv3.1 feature is not required by all vendors,
> all changes are guarded by ifdefs, depending on the corresponding
> Kconfig option.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V5:
> - no functional changes introduced by this version compared with V4, only
>   minor fixes and removal of ifdefs for macroses
> - added TODO comment, suggested by Oleksandr Tyshchenko
> - changed int to unsigned int for irqs
> - removed ifdefs for eSPI-specific defines and macros to reduce the
>   number of ifdefs and code duplication in further changes
> - removed reviewed-by as moving defines from ifdefs requires additional
>   confirmation from reviewers
>
> Changes in V4:
> - removed redundant line with 'default n' in Kconfig, as it is disabled
>   by default, without explicit specification
> - added reviewed-by from Volodymyr Babchuk
>
> Changes in V3:
> - introduced a new define NR_ESPI_IRQS to avoid confusion, like in the
>   case of using NR_IRQS for espi_desc array
> - implemented helper functions espi_to_desc and init_espi_data to make
>   it possible to add stubs with the same name, and as a result, reduce
>   the number of #ifdefs
> - disable CONFIG_GICV3_ESPI default value to n
>
> Changes in V2:
> - use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
> - remove unnecessary comment for nr_irqs initialization
> ---
>  xen/arch/arm/Kconfig           |  8 +++++
>  xen/arch/arm/include/asm/irq.h | 24 +++++++++++++++
>  xen/arch/arm/irq.c             | 56 +++++++++++++++++++++++++++++++++-
>  3 files changed, 87 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index 17df147b25..43b05533b1 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -135,6 +135,14 @@ config GICV3
>  	  Driver for the ARM Generic Interrupt Controller v3.
>  	  If unsure, use the default setting.
> =20
> +config GICV3_ESPI
> +	bool "Extended SPI range support"
> +	depends on GICV3 && !NEW_VGIC
> +	help
> +	  Allow Xen and domains to use interrupt numbers from the extended SPI
> +	  range, from 4096 to 5119. This feature is introduced in GICv3.1
> +	  architecture.
> +
>  config HAS_ITS
>          bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPO=
RTED
>          depends on GICV3 && !NEW_VGIC && !ARM_32
> diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/ir=
q.h
> index 5bc6475eb4..4443799648 100644
> --- a/xen/arch/arm/include/asm/irq.h
> +++ b/xen/arch/arm/include/asm/irq.h
> @@ -32,6 +32,13 @@ struct arch_irq_desc {
>  #define SPI_MAX_INTID   1019
>  #define LPI_OFFSET      8192
> =20
> +#define ESPI_BASE_INTID 4096
> +#define ESPI_MAX_INTID  5119
> +#define NR_ESPI_IRQS    1024
> +
> +#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
> +#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
> +
>  /* LPIs are always numbered starting at 8192, so 0 is a good invalid cas=
e. */
>  #define INVALID_LPI     0
> =20
> @@ -39,7 +46,15 @@ struct arch_irq_desc {
>  #define INVALID_IRQ     1023
> =20
>  extern const unsigned int nr_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * This will also cover the eSPI range, as some critical devices
> + * for booting Xen (e.g., serial) may use this type of interrupts.
> + */
> +#define nr_static_irqs (ESPI_MAX_INTID + 1)
> +#else
>  #define nr_static_irqs NR_IRQS
> +#endif
> =20
>  struct irq_desc;
>  struct irqaction;
> @@ -55,6 +70,15 @@ static inline bool is_lpi(unsigned int irq)
>      return irq >=3D LPI_OFFSET;
>  }
> =20
> +static inline bool is_espi(unsigned int irq)
> +{
> +#ifdef CONFIG_GICV3_ESPI

Taking into account that with CONFIG_GICV3_ESPI=3Dn we should never have
"irq" in eSPI range, do you really need this #ifdef? I think that
ASSERT_UNREACHABLE in espi_to_desc() is sufficient guard.

Also, IRQ line number belongs to eSPI range regardless of CONFIG_GICV3_ESPI=
,
value, so in my opinion is_espi() should always return correct value for
a given "irq".

> +    return (irq >=3D ESPI_BASE_INTID && irq <=3D ESPI_MAX_INTID);

Also, you don't need parentheses here.

> +#else
> +    return false;
> +#endif
> +}
> +
>  #define domain_pirq_to_irq(d, pirq) (pirq)
> =20
>  bool is_assignable_irq(unsigned int irq);
> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
> index b8eccfc924..61c915c3f9 100644
> --- a/xen/arch/arm/irq.c
> +++ b/xen/arch/arm/irq.c
> @@ -19,7 +19,11 @@
>  #include 
>  #include 
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +const unsigned int nr_irqs =3D ESPI_MAX_INTID + 1;
> +#else
>  const unsigned int nr_irqs =3D NR_IRQS;
> +#endif
> =20
>  static unsigned int local_irqs_type[NR_LOCAL_IRQS];
>  static DEFINE_SPINLOCK(local_irqs_type_lock);
> @@ -46,6 +50,53 @@ void irq_end_none(struct irq_desc *irq)
>  }
> =20
>  static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * TODO: Consider allocating an array dynamically if
> + * there is a need to enable GICV3_ESPI by default.
> + */
> +static irq_desc_t espi_desc[NR_ESPI_IRQS];
> +
> +static struct irq_desc *espi_to_desc(unsigned int irq)
> +{
> +    return &espi_desc[ESPI_INTID2IDX(irq)];
> +}
> +
> +static int __init init_espi_data(void)
> +{
> +    unsigned int irq;
> +
> +    for ( irq =3D ESPI_BASE_INTID; irq <=3D ESPI_MAX_INTID; irq++ )
> +    {
> +        struct irq_desc *desc =3D irq_to_desc(irq);
> +        int rc =3D init_one_irq_desc(desc);
> +
> +        if ( rc )
> +            return rc;
> +
> +        desc->irq =3D irq;
> +        desc->action  =3D NULL;
> +    }
> +
> +    return 0;
> +}
> +#else
> +/*
> + * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn=
,
> + * because in this case, is_espi will always return false.
> + */
> +static struct irq_desc *espi_to_desc(unsigned int irq)
> +{
> +    ASSERT_UNREACHABLE();
> +    return NULL;
> +}
> +
> +static int __init init_espi_data(void)
> +{
> +    return 0;
> +}
> +#endif
> +
>  static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc);
> =20
>  struct irq_desc *__irq_to_desc(unsigned int irq)
> @@ -53,6 +104,9 @@ struct irq_desc *__irq_to_desc(unsigned int irq)
>      if ( irq < NR_LOCAL_IRQS )
>          return &this_cpu(local_irq_desc)[irq];
> =20
> +    if ( is_espi(irq) )
> +        return espi_to_desc(irq);
> +
>      return &irq_desc[irq-NR_LOCAL_IRQS];
>  }
> =20
> @@ -79,7 +133,7 @@ static int __init init_irq_data(void)
>          desc->action  =3D NULL;
>      }
> =20
> -    return 0;
> +    return init_espi_data();
>  }
> =20
>  static int init_local_irq_data(unsigned int cpu)

--=20
WBR, Volodymyr=


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v5 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Topic: [PATCH v5 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
Thread-Index: AQHcGP7eXuLLXrvHTUaZmxhTVnJkUA==
Date: Fri, 29 Aug 2025 19:55:59 +0000
Message-ID: <87iki5yka9.fsf@epam.com>
References: 
	
In-Reply-To:
 
	(Leonid Komarianskyi's message of "Fri, 29 Aug 2025 16:06:22 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> Introduced appropriate register definitions, helper macros,
> and initialization of required GICv3.1 distributor registers
> to support eSPI. This type of interrupt is handled in the
> same way as regular SPI interrupts, with the following
> differences:
>
> 1) eSPIs can have up to 1024 interrupts, starting from the
> beginning of the range, whereas regular SPIs use INTIDs from
> 32 to 1019, totaling 988 interrupts;
> 2) eSPIs start at INTID 4096, necessitating additional interrupt
> index conversion during register operations.
>
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V5:
> - fixed minor nits, no functional changes: changed u32 to uint32_t and
>   added a comment noting that the configuration for eSPIs is the same as
>   for regular SPIs
> - removed ifdefs for eSPI-specific offsets to reduce the number of
>   ifdefs and code duplication in further changes
> - removed reviewed-by as moving offset from ifdefs requires additional
>   confirmation from reviewers
>
> Changes in V4:
> - added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
>   for vGIC emulation
> - added a log banner with eSPI information, similar to the one for
>   regular SPI
> - added newline after ifdef and before gic_is_valid_line
> - added reviewed-by from Volodymyr Babchuk
>
> Changes in V3:
> - add __init attribute to gicv3_dist_espi_common_init
> - change open-codded eSPI register initialization to the appropriate
>   gen-mask macro
> - fixed formatting for lines with more than 80 symbols
> - introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
>   CONFIG_GICV3_ESPI disabled
> - renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
>   (name was taken from GIC specification) to avoid confusion
> - changed type for i variable to unsigned int since it cannot be
>   negative
>
> Changes in V2:
> - move gic_number_espis function from
>   [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
>   to use it in the newly introduced gic_is_valid_espi
> - add gic_is_valid_espi which checks if IRQ number is in supported
>   by HW eSPI range
> - update gic_is_valid_irq conditions to allow operations with eSPIs
> ---
>  xen/arch/arm/gic-v3.c                  | 83 ++++++++++++++++++++++++++
>  xen/arch/arm/include/asm/gic.h         | 22 +++++++
>  xen/arch/arm/include/asm/gic_v3_defs.h | 38 ++++++++++++
>  3 files changed, 143 insertions(+)
>
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 29b7f68cba..4a7ce12f26 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_d=
esc *irqd, u32 offset)
>          default:
>              break;
>          }
> +#ifdef CONFIG_GICV3_ESPI
> +    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
> +    {
> +        uint32_t irq_index =3D ESPI_INTID2IDX(irqd->irq);
> +
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ICENABLER:
> +            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ISPENDR:
> +            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ICPENDR:
> +            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ISACTIVER:
> +            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICACTIVER:
> +            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTERnE + irq_index * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYRnE + irq_index);
> +        default:
> +            break;
> +        }
> +    }
> +#endif
>      default:
>          break;
>      }
> @@ -655,6 +685,55 @@ static void gicv3_set_irq_priority(struct irq_desc *=
desc,
>      spin_unlock(&gicv3.lock);
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +unsigned int gic_number_espis(void)
> +{
> +    return gic_hw_ops->info->nr_espi;
> +}
> +
> +static void __init gicv3_dist_espi_common_init(uint32_t type)
> +{
> +    unsigned int espi_nr, i;
> +
> +    espi_nr =3D min(1024U, GICD_TYPER_ESPIS_NUM(type));
> +    gicv3_info.nr_espi =3D espi_nr;
> +    /* The GIC HW doesn't support eSPI, so we can leave from here */
> +    if ( gicv3_info.nr_espi =3D=3D 0 )
> +        return;
> +
> +    printk("GICv3: %d eSPI lines\n", gicv3_info.nr_espi);
> +
> +    /* The configuration for eSPIs is similar to that for regular SPIs *=
/
> +    for ( i =3D 0; i < espi_nr; i +=3D 16 )
> +        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 4 )
> +        writel_relaxed(GIC_PRI_IRQ_ALL,
> +                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 32 )
> +    {
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i / 32=
) * 4);
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i / 32=
) * 4);
> +    }
> +
> +    for ( i =3D 0; i < espi_nr; i +=3D 32 )
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) =
* 4);
> +}
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
> +{
> +    unsigned int i;
> +
> +    for ( i =3D 0; i < gicv3_info.nr_espi; i++ )
> +        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * =
8);
> +}
> +#else
> +static void __init gicv3_dist_espi_common_init(uint32_t type) { }
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
> +#endif
> +
>  static void __init gicv3_dist_init(void)
>  {
>      uint32_t type;
> @@ -700,6 +779,8 @@ static void __init gicv3_dist_init(void)
>      for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i +=3D 32 )
>          writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * =
4);
> =20
> +    gicv3_dist_espi_common_init(type);
> +
>      gicv3_dist_wait_for_rwp();
> =20
>      /* Turn on the distributor */
> @@ -713,6 +794,8 @@ static void __init gicv3_dist_init(void)
> =20
>      for ( i =3D NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
>          writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8)=
;
> +
> +    gicv3_dist_espi_init_aff(affinity);
>  }
> =20
>  static int gicv3_enable_redist(void)
> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gi=
c.h
> index 3fcee42675..1e747dcd99 100644
> --- a/xen/arch/arm/include/asm/gic.h
> +++ b/xen/arch/arm/include/asm/gic.h
> @@ -306,8 +306,26 @@ extern void gic_dump_vgic_info(struct vcpu *v);
> =20
>  /* Number of interrupt lines */
>  extern unsigned int gic_number_lines(void);
> +#ifdef CONFIG_GICV3_ESPI
> +extern unsigned int gic_number_espis(void);
> +
> +static inline bool gic_is_valid_espi(unsigned int irq)
> +{
> +    return (irq >=3D ESPI_BASE_INTID &&
> +            irq < ESPI_IDX2INTID(gic_number_espis()));

You don't need external () here.

> +}
> +#else
> +static inline bool gic_is_valid_espi(unsigned int irq)
> +{
> +    return false;
> +}
> +#endif
> +
>  static inline bool gic_is_valid_line(unsigned int irq)
>  {
> +    if ( gic_is_valid_espi(irq) )
> +        return true;
> +
>      return irq < gic_number_lines();
>  }

As you are going to rework this patch anyways, my I ask to rewrite this
function in the following way?

static inline bool gic_is_valid_line(unsigned int irq)
{
     return irq < gic_number_lines() || gic_is_valid_espi(irq);
}

My justification is that (irq < gic_number_lines()) case is more likely,
so it is better to evaluate it first, only then check for eSPIs.

I am sorry, I should asked it earlier, but only after removing #ifdef I
saw that this part could be more optimal.

> =20
> @@ -325,6 +343,10 @@ struct gic_info {
>      enum gic_version hw_version;
>      /* Number of GIC lines supported */
>      unsigned int nr_lines;
> +#ifdef CONFIG_GICV3_ESPI
> +    /* Number of GIC eSPI supported */
> +    unsigned int nr_espi;
> +#endif
>      /* Number of LR registers */
>      uint8_t nr_lrs;
>      /* Maintenance irq number */
> diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/includ=
e/asm/gic_v3_defs.h
> index 2af093e774..3370b4cd52 100644
> --- a/xen/arch/arm/include/asm/gic_v3_defs.h
> +++ b/xen/arch/arm/include/asm/gic_v3_defs.h
> @@ -37,6 +37,44 @@
>  #define GICD_IROUTER1019             (0x7FD8)
>  #define GICD_PIDR2                   (0xFFE8)
> =20
> +/* Additional registers for GICv3.1 */
> +#define GICD_IGROUPRnE               (0x1000)
> +#define GICD_IGROUPRnEN              (0x107C)
> +#define GICD_ISENABLERnE             (0x1200)
> +#define GICD_ISENABLERnEN            (0x127C)
> +#define GICD_ICENABLERnE             (0x1400)
> +#define GICD_ICENABLERnEN            (0x147C)
> +#define GICD_ISPENDRnE               (0x1600)
> +#define GICD_ISPENDRnEN              (0x167C)
> +#define GICD_ICPENDRnE               (0x1800)
> +#define GICD_ICPENDRnEN              (0x187C)
> +#define GICD_ISACTIVERnE             (0x1A00)
> +#define GICD_ISACTIVERnEN            (0x1A7C)
> +#define GICD_ICACTIVERnE             (0x1C00)
> +#define GICD_ICACTIVERnEN            (0x1C7C)
> +#define GICD_IPRIORITYRnE            (0x2000)
> +#define GICD_IPRIORITYRnEN           (0x23FC)
> +#define GICD_ICFGRnE                 (0x3000)
> +#define GICD_ICFGRnEN                (0x30FC)
> +#define GICD_IGRPMODRnE              (0x3400)
> +#define GICD_IGRPMODRnEN             (0x347C)
> +#define GICD_NSACRnE                 (0x3600)
> +#define GICD_NSACRnEN                (0x36FC)
> +#define GICD_IROUTERnE               (0x8000)
> +#define GICD_IROUTERnEN              (0x9FFC)
> +
> +#ifdef CONFIG_GICV3_ESPI
> +#define GICD_TYPER_ESPI_SHIFT        8
> +#define GICD_TYPER_ESPI_RANGE_SHIFT  27
> +#define GICD_TYPER_ESPI_RANGE_MASK   (0x1F)
> +#define GICD_TYPER_ESPI              (1U << GICD_TYPER_ESPI_SHIFT)
> +#define GICD_TYPER_ESPI_RANGE(espi_range) ((((espi_range) & \
> +        GICD_TYPER_ESPI_RANGE_MASK) + 1) * 32)
> +#define GICD_TYPER_ESPIS_NUM(typer)    \
> +        (((typer) & GICD_TYPER_ESPI) ? \
> +        GICD_TYPER_ESPI_RANGE((typer) >> GICD_TYPER_ESPI_RANGE_SHIFT) : =
0)
> +#endif
> +
>  /* Common between GICD_PIDR2 and GICR_PIDR2 */
>  #define GIC_PIDR2_ARCH_MASK         (0xf0)
>  #define GIC_PIDR2_ARCH_GICv3        (0x30)

--=20
WBR, Volodymyr=


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From: Stefano Stabellini 
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To: dmukhin@xen.org
cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, 
    dmukhin@ford.com
Subject: Re: [PATCH v5 03/15] emul/ns16x50: implement emulator stub
In-Reply-To: <20250828235409.2835815-4-dmukhin@ford.com>
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On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> From: Denis Mukhin  
> 
> The change is the first on the way on introducing minimally functional
> NS16550-compatible UART emulator.
> 
> Define UART state and a set of emulated registers.
> 
> Implement alloc/free vUART hooks.
> 
> Stub out I/O port handler.
> 
> Add initialization of the NS16x50-compatible UART emulator state machine.
> 
> Plumb debug logging.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v4:
> - new patch 
> ---
>  xen/arch/x86/hvm/hvm.c          |  20 ++
>  xen/common/emul/vuart/Kconfig   |  18 ++
>  xen/common/emul/vuart/Makefile  |   1 +
>  xen/common/emul/vuart/ns16x50.c | 362 ++++++++++++++++++++++++++++++++
>  xen/include/xen/sched.h         |   4 +
>  5 files changed, 405 insertions(+)
>  create mode 100644 xen/common/emul/vuart/ns16x50.c
> 
> diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
> index 23bd7f078a1d..26760cf995df 100644
> --- a/xen/arch/x86/hvm/hvm.c
> +++ b/xen/arch/x86/hvm/hvm.c
> @@ -28,6 +28,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -689,6 +690,21 @@ int hvm_domain_initialise(struct domain *d,
>      if ( rc != 0 )
>          goto fail1;
>  
> +    if ( IS_ENABLED(CONFIG_VUART_NS16X50) )

maybe only for the hardware domain?
or only input_allowed = true only for the hardware domain?

> +    {
> +        struct vuart_info info = {
> +            .name       = "COM2",
> +            .compatible = "ns16550",
> +            .base_addr  = 0x2f8,
> +            .size       = 8,
> +            .irq        = 3,
> +        };
> +
> +        rc = vuart_init(d, &info);
> +        if ( rc )
> +            goto out_vioapic_deinit;
> +    }
> +
>      stdvga_init(d);
>  
>      rtc_init(d);
> @@ -712,6 +728,8 @@ int hvm_domain_initialise(struct domain *d,
>      return 0;
>  
>   fail2:
> +    vuart_deinit(d);
> + out_vioapic_deinit:
>      vioapic_deinit(d);
>   fail1:
>      if ( is_hardware_domain(d) )
> @@ -774,6 +792,8 @@ void hvm_domain_destroy(struct domain *d)
>      if ( hvm_funcs.domain_destroy )
>          alternative_vcall(hvm_funcs.domain_destroy, d);
>  
> +    vuart_deinit(d);
> +
>      vioapic_deinit(d);
>  
>      XFREE(d->arch.hvm.pl_time);
> diff --git a/xen/common/emul/vuart/Kconfig b/xen/common/emul/vuart/Kconfig
> index ce1b976b7da7..539e6d5e4fc7 100644
> --- a/xen/common/emul/vuart/Kconfig
> +++ b/xen/common/emul/vuart/Kconfig
> @@ -3,4 +3,22 @@ config VUART_FRAMEWORK
>  
>  menu "UART Emulation"
>  
> +config VUART_NS16X50
> +	bool "NS16550-compatible UART Emulator" if EXPERT
> +	depends on X86 && HVM
> +	select VUART_FRAMEWORK

default n

> +	help
> +	  In-hypervisor NS16x50 UART emulation.
> +
> +	  Only legacy PC COM2 port is emulated.
> +
> +	  This is strictly for testing purposes (such as early HVM guest console),
> +	  and not appropriate for use in production.
> +
> +config VUART_NS16X50_DEBUG
> +	bool "NS16550-compatible UART Emulator Debugging"
> +	depends on VUART_NS16X50 && DEBUG
> +	help
> +	  Enable development debugging.
> +
>  endmenu
> diff --git a/xen/common/emul/vuart/Makefile b/xen/common/emul/vuart/Makefile
> index 97f792dc6641..fe904f6cb65d 100644
> --- a/xen/common/emul/vuart/Makefile
> +++ b/xen/common/emul/vuart/Makefile
> @@ -1 +1,2 @@
>  obj-y += vuart.o
> +obj-$(CONFIG_VUART_NS16X50) += ns16x50.o
> diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> new file mode 100644
> index 000000000000..f0479e1022fb
> --- /dev/null
> +++ b/xen/common/emul/vuart/ns16x50.c
> @@ -0,0 +1,362 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * NS16550-compatible UART Emulator.
> + *
> + * See:
> + * - Serial and UART Tutorial:
> + *     https://download.freebsd.org/doc/en/articles/serial-uart/serial-uart_en.pdf
> + * - UART w/ 16 byte FIFO:
> + *     https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
> + * - UART w/ 64 byte FIFO:
> + *     https://www.ti.com/lit/ds/symlink/tl16c750.pdf
> + *
> + * Limitations:
> + * - Only x86;
> + * - Only Xen console as a backend, no inter-domain communication (similar to
> + *   vpl011 on Arm);
> + * - Only 8n1 emulation (8-bit data, no parity, 1 stop bit);
> + * - No baud rate emulation (reports 115200 baud to the guest OS);
> + * - No FIFO-less mode emulation;
> + * - No RX FIFO interrupt moderation (FCR) emulation;
> + * - No integration w/ VM snapshotting (HVM_REGISTER_SAVE_RESTORE() and
> + *   friends);
> + * - No ISA IRQ sharing allowed;
> + * - No MMIO-based UART emulation.
> + */
> +
> +#define pr_prefix               "ns16x50"
> +#define pr_fmt(fmt)             pr_prefix ": " fmt
> +
> +#ifdef CONFIG_VUART_NS16X50_DEBUG
> +#define guest_prefix            "FROM GUEST "
> +#define ns16x50_log_level       2
> +#else
> +#define guest_prefix            ""
> +#define ns16x50_log_level       0
> +#endif
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#define ns16x50_log(n, lvl, vdev, fmt, args...) do { \
> +    if ( ns16x50_log_level >= n) \
> +        gprintk(lvl, pr_fmt("%s: " fmt), (vdev)->name, ## args); \
> +} while (0)
> +
> +#define ns16x50_err(vdev, fmt, args...) \
> +    ns16x50_log(0, KERN_ERR, vdev, fmt, ## args)
> +#define ns16x50_warn(vdev, fmt, args...) \
> +    ns16x50_log(1, KERN_WARNING, vdev, fmt, ## args)
> +#define ns16x50_info(vdev, fmt, args...) \
> +    ns16x50_log(2, KERN_INFO, vdev, fmt, ## args)
> +#define ns16x50_debug(vdev, fmt, args...) \
> +    ns16x50_log(3, KERN_DEBUG, vdev, fmt, ## args)
> +
> +/*
> + * Number of supported registers in the UART.
> + */
> +#define NS16X50_REGS_NUM        (UART_SCR + 1)
> +
> +/*
> + * Number of emulated registers.
> + *
> + * - Emulated registers [0..NS16X50_REGS_NUM] are R/W registers for DLAB=0.
> + * - DLAB=1, R/W, DLL            = NS16X50_REGS_NUM + 0
> + * - DLAB=1, R/W, DLM            = NS16X50_REGS_NUM + 1
> + * -         R/O, IIR (IIR_THR)  = NS16X50_REGS_NUM + 2
> + */
> +#define NS16X50_EMU_REGS_NUM    (NS16X50_REGS_NUM + 3)
> +
> +/*
> + * Virtual ns16x50 device state.
> + */
> +struct vuart_ns16x50 {
> +    struct xencons_interface cons;      /* Emulated RX/TX FIFOs */
> +    uint8_t regs[NS16X50_EMU_REGS_NUM]; /* Emulated registers */
> +    const char *name;                   /* Device name */
> +    struct domain *owner;               /* Owner domain */
> +    const struct vuart_info *info;      /* UART description */
> +    spinlock_t lock;                    /* Protection */
> +};
> +
> +/*
> + * Emulate 8-bit write access to ns16x50 register.
> + */
> +static int ns16x50_io_write8(
> +    struct vuart_ns16x50 *vdev, uint32_t reg, uint8_t *data)
> +{
> +    int rc = 0;
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate 16-bit write access to ns16x50 register.
> + * NB: some guest OSes use outw() to access UART_DLL.
> + */
> +static int ns16x50_io_write16(
> +    struct vuart_ns16x50 *vdev, uint32_t reg, uint16_t *data)
> +{
> +    int rc = -EINVAL;
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate write access to ns16x50 register.
> + */
> +static int ns16x50_io_write(
> +    struct vuart_ns16x50 *vdev, uint8_t reg, uint32_t size, uint32_t *data)
> +{
> +    int rc;
> +
> +    switch ( size )
> +    {
> +    case 1:
> +        rc = ns16x50_io_write8(vdev, reg, (uint8_t *)data);
> +        break;
> +
> +    case 2:
> +        rc = ns16x50_io_write16(vdev, reg, (uint16_t *)data);
> +        break;
> +
> +    default:
> +        rc = -EINVAL;
> +        break;
> +    }
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate 8-bit read access to ns16x50 register.
> + */
> +static int ns16x50_io_read8(
> +    struct vuart_ns16x50 *vdev, uint32_t reg, uint8_t *data)
> +{
> +    uint8_t val = 0xff;
> +    int rc = 0;
> +
> +    *data = val;
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate 16-bit read access to ns16x50 register.
> + */
> +static int ns16x50_io_read16(
> +    struct vuart_ns16x50 *vdev, uint32_t reg, uint16_t *data)
> +{
> +    uint16_t val = 0xffff;
> +    int rc = -EINVAL;
> +
> +    *data = val;
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate read access to ns16x50 register.
> + */
> +static int ns16x50_io_read(
> +    struct vuart_ns16x50 *vdev, uint8_t reg, uint32_t size, uint32_t *data)
> +{
> +    int rc;
> +
> +    switch ( size )
> +    {
> +    case 1:
> +        rc = ns16x50_io_read8(vdev, reg, (uint8_t *)data);
> +        break;
> +
> +    case 2:
> +        rc = ns16x50_io_read16(vdev, reg, (uint16_t *)data);
> +        break;
> +
> +    default:
> +        *data = 0xffffffff;
> +        rc = -EINVAL;
> +        break;
> +    }
> +
> +    return rc;
> +}
> +
> +/*
> + * Emulate I/O access to ns16x50 register.
> + * Note, emulation always returns X86EMUL_OKAY, once I/O port trap is enabled.
> + */
> +static int cf_check ns16x50_io_handle(
> +    int dir, unsigned int addr, unsigned int size, uint32_t *data)
> +{
> +#define op(dir)     (((dir) == IOREQ_WRITE) ? 'W' : 'R')
> +    struct domain *d = rcu_lock_current_domain();
> +    struct vuart *vuart = vuart_find_by_io_range(d, addr, size);
> +    struct vuart_ns16x50 *vdev;
> +    const struct domain *owner;
> +    const struct vuart_info *info;
> +    uint32_t reg;
> +    unsigned dlab;
> +    int rc;
> +
> +    if ( !vuart || !vuart->vdev )
> +    {
> +        printk(KERN_ERR "%c io 0x%04x %d: not initialized\n",

XENLOG_ERR


> +               op(dir), addr, size);
> +
> +        ASSERT_UNREACHABLE();
> +        goto out;
> +    }
> +    vdev = vuart->vdev;
> +
> +    owner = vuart->owner;
> +    ASSERT(owner);
> +    if ( d != owner )
> +    {
> +        ns16x50_err(vdev, "%c io 0x%04x %d: does not match current domain %pv\n",
> +                    op(dir), addr, size, d);
> +
> +        ASSERT_UNREACHABLE();
> +        goto out;
> +    }
> +
> +    info = vuart->info;
> +    ASSERT(info);
> +    reg = addr - info->base_addr;
> +    if ( !IS_ALIGNED(reg, size) )
> +    {
> +        ns16x50_err(vdev, "%c 0x%04x %d: unaligned access\n",
> +                    op(dir), addr, size);


For this one we could consider returning X86EMUL_UNHANDLEABLE but I am not sure
as it would crash the guest.

> +        goto out;
> +    }
> +
> +    dlab = 0;
> +    if ( reg >= NS16X50_REGS_NUM )
> +    {
> +        ns16x50_err(vdev, "%c io 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32": not implemented\n",
> +                    op(dir), addr, size, dlab, reg, *data);
> +        goto out;
> +    }
> +
> +    spin_lock(&vdev->lock);
> +
> +    if ( dir == IOREQ_WRITE )
> +    {
> +        ns16x50_debug(vdev, "%c 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32"\n",
> +                      op(dir), addr, size, dlab, reg, *data);
> +        rc = ns16x50_io_write(vdev, reg, size, data);
> +    }
> +    else
> +    {
> +        rc = ns16x50_io_read(vdev, reg, size, data);
> +        ns16x50_debug(vdev, "%c 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32"\n",
> +                      op(dir), addr, size, dlab, reg, *data);
> +    }
> +    if ( rc < 0 )
> +        ns16x50_err(vdev, "%c 0x%04x %d: DLAB=%d %02"PRIx32" 0x%08"PRIx32": unsupported access\n",
> +                    op(dir), addr, size, dlab, reg, *data);
> +
> +    spin_unlock(&vdev->lock);
> +
> +out:
> +    rcu_unlock_domain(d);
> +
> +    return X86EMUL_OKAY;
> +#undef op
> +}
> +
> +static int ns16x50_init(void *arg)
> +{
> +    struct vuart_ns16x50 *vdev = arg;
> +    const struct vuart_info *info = vdev->info;
> +    struct domain *d = vdev->owner;
> +
> +    ASSERT(vdev);
> +
> +    register_portio_handler(d, info->base_addr, info->size, ns16x50_io_handle);
> +
> +    return 0;
> +}
> +
> +static void cf_check ns16x50_deinit(void *arg)
> +{
> +    struct vuart_ns16x50 *vdev = arg;
> +
> +    ASSERT(vdev);

it should unregister the handlers


> +}
> +
> +static void * cf_check ns16x50_alloc(struct domain *d, const struct vuart_info *info)
> +{
> +    struct vuart_ns16x50 *vdev;
> +    int rc;
> +
> +    if ( !info )
> +        return ERR_PTR(-EINVAL);
> +
> +    if ( vuart_find_by_io_range(d, info->base_addr, info->size) )
> +    {
> +        ns16x50_err(info, "already registered\n");
> +        return ERR_PTR(-EBUSY);
> +    }
> +
> +    if ( !is_hvm_domain(d) )
> +    {
> +        ns16x50_err(info, "not an HVM domain\n");
> +        return ERR_PTR(-ENOSYS);
> +    }
> +
> +    vdev = xvzalloc(typeof(*vdev));
> +    if ( !vdev )
> +    {
> +        ns16x50_err(info, "failed to allocate memory\n");
> +        return ERR_PTR(-ENOMEM);
> +    }
> +
> +    /* Save convenience pointer. */
> +    vdev->name = info->name;
> +    vdev->owner = d;
> +    vdev->info = info;

the spinlock should be initialized 


> +    rc = ns16x50_init(vdev);
> +    if ( rc )
> +        return ERR_PTR(rc);
> +
> +    return vdev;
> +}
> +
> +static void cf_check ns16x50_free(void *arg)
> +{
> +    struct vuart_ns16x50 *vdev = arg;
> +
> +    if ( vdev )
> +        ns16x50_deinit(vdev);
> +
> +    XVFREE(vdev);

XVFREE should only be called if ( vdev )


> +}
> +
> +#define ns16x50_emulator                \
> +{                                       \
> +    .compatible = "ns16550",            \
> +    .alloc      = ns16x50_alloc,        \
> +    .free       = ns16x50_free,         \
> +    .dump_state = NULL,                 \
> +    .put_rx     = NULL,                 \
> +}
> +
> +VUART_REGISTER(ns16x50, ns16x50_emulator);
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/include/xen/sched.h b/xen/include/xen/sched.h
> index 02bdc256ce37..613f4596e33d 100644
> --- a/xen/include/xen/sched.h
> +++ b/xen/include/xen/sched.h
> @@ -23,6 +23,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -660,6 +661,9 @@ struct domain
>      struct {
>          /* Permission to take ownership of the physical console input. */
>          bool input_allowed;
> +#ifdef CONFIG_VUART_FRAMEWORK
> +        struct vuart *vuart;
> +#endif

this should be in patch #1, as patch #1 does:

d->console.vuart = vuart;


>      } console;
>  } __aligned(PAGE_SIZE);
>  
> -- 
> 2.51.0
> 


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v5 10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Topic: [PATCH v5 10/12] xen/arm: vgic-v3: add emulation of GICv3.1 eSPI
 registers
Thread-Index: AQHcGP7mpeV242hLM02UQE7oK85XeQ==
Date: Fri, 29 Aug 2025 20:12:12 +0000
Message-ID: <87cy8dyjj8.fsf@epam.com>
References: 
	<6fda233a1a2f0362062ff9a6e80ee223d33815cf.1756481577.git.leonid_komarianskyi@epam.com>
In-Reply-To:
 <6fda233a1a2f0362062ff9a6e80ee223d33815cf.1756481577.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Fri, 29 Aug 2025 16:06:36 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> Implemented support for GICv3.1 extended SPI registers for vGICv3,
> allowing the emulation of eSPI-specific behavior for guest domains.
> The implementation includes read and write emulation for eSPI-related
> registers (e.g., GICD_ISENABLERnE, GICD_IROUTERnE, and others),
> following a similar approach to the handling of regular SPIs.
>
> The eSPI registers, previously located in reserved address ranges,
> are now adjusted to support MMIO read and write operations correctly
> when CONFIG_GICV3_ESPI is enabled.
>
> The availability of eSPIs and the number of emulated extended SPIs
> for guest domains is reported by setting the appropriate bits in the
> GICD_TYPER register, based on the number of eSPIs requested by the
> domain and supported by the hardware. In cases where the configuration
> option is disabled, the hardware does not support eSPIs, or the domain
> does not request such interrupts, the functionality remains unchanged.
>
> Signed-off-by: Leonid Komarianskyi 

I have a couple of comments about coding style, but apart from that it
looks really good. With these issues fixed:

Reviewed-by: Volodymyr Babchuk 

>
> ---
> Changes in V5:
> - since eSPI-specific defines and macros are now available even when the
>   appropriate config is disabled, this allows us to remove many
>   #ifdef guards and reuse the existing code for regular SPIs for eSPIs as
>   well, as eSPIs are processed similarly. This improves code readability
>   and consolidates the register ranges for SPIs and eSPIs in a single
>   place, simplifying future changes or fixes for SPIs and their
>   counterparts from the extended range
> - moved vgic_ext_rank_offset() from
>   [08/12] xen/arm: vgic: add resource management for extended SPIs
>   as the function was unused before this patch
> - added stub implementation of vgic_ext_rank_offset() when CONFIG_GICV3_E=
SPI=3Dn
> - removed unnecessary defines for reserved ranges, which were introduced =
in
>   V4 to reduce the number of #ifdefs. The issue is now resolved by
>   allowing the use of SPI-specific offsets and reworking the logic
>
> Changes in V4:
> - added missing RAZ and write ignore eSPI-specific registers ranges:
>   GICD_NSACRnE and GICD_IGRPMODRnE
> - changed previously reserved range to cover GICD_NSACRnE and
>   GICD_IGRPMODRnE
> - introduced GICD_RESERVED_RANGE_START/END defines to remove
>   hardcoded values and reduce the number of ifdefs
> - fixed reserved ranges with eSPI option enabled: added missing range
>   0x0F30-0x0F7C
> - updated the logic for domains that do not support eSPI, but Xen is
>   compiled with the eSPI option. Now, prior to other MMIO checks, we
>   verify whether eSPI is available for the domain or not. If not, it
>   behaves as it does currently - RAZ and WI
> - fixed print for GICD_ICACTIVERnE
> - fixed new lines formatting for switch-case
>
> Changes in V3:
> - changed vgic_store_irouter parameters - instead of offset virq is
>   used, to remove the additional bool espi parameter and simplify
>   checks. Also, adjusted parameters for regular SPI. Since the offset
>   parameter was used only for calculating virq number and then reused for
>   finding rank offset, it will not affect functionality.
> - fixed formatting for goto lables - added newlines after condition
> - fixed logs for GICD_ISACTIVERnE and GICD_ICACTIVERnE handlers
> - removed #ifdefs in 2 places where they were adjacent and could be merge=
d
>
> Changes in V2:
> - add missing rank index conversion for pending and inflight irqs
> ---
>  xen/arch/arm/include/asm/vgic.h |   4 +
>  xen/arch/arm/vgic-v3.c          | 198 ++++++++++++++++++++++++++------
>  xen/arch/arm/vgic.c             |  23 ++++
>  3 files changed, 192 insertions(+), 33 deletions(-)
>
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 3aa22114ba..103bc3c74b 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -314,6 +314,10 @@ extern struct vgic_irq_rank *vgic_rank_offset(struct=
 vcpu *v,
>                                                unsigned int b,
>                                                unsigned int n,
>                                                unsigned int s);
> +extern struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v,
> +                                                  unsigned int b,
> +                                                  unsigned int n,
> +                                                  unsigned int s);
>  extern struct vgic_irq_rank *vgic_rank_irq(struct vcpu *v, unsigned int =
irq);
>  extern void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n=
);
>  extern void vgic_enable_irqs(struct vcpu *v, uint32_t r, unsigned int n)=
;
> diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
> index 4369c55177..b5d766c98f 100644
> --- a/xen/arch/arm/vgic-v3.c
> +++ b/xen/arch/arm/vgic-v3.c
> @@ -111,13 +111,10 @@ static uint64_t vgic_fetch_irouter(struct vgic_irq_=
rank *rank,
>   * Note the offset will be aligned to the appropriate boundary.
>   */
>  static void vgic_store_irouter(struct domain *d, struct vgic_irq_rank *r=
ank,
> -                               unsigned int offset, uint64_t irouter)
> +                               unsigned int virq, uint64_t irouter)
>  {
>      struct vcpu *new_vcpu, *old_vcpu;
> -    unsigned int virq;
> -
> -    /* There is 1 vIRQ per IROUTER */
> -    virq =3D offset / NR_BYTES_PER_IROUTER;
> +    unsigned int offset;
> =20
>      /*
>       * The IROUTER0-31, used for SGIs/PPIs, are reserved and should
> @@ -685,13 +682,20 @@ static int __vgic_v3_distr_common_mmio_read(const c=
har *name, struct vcpu *v,
>      {
>      case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>      case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
>          /* We do not implement security extensions for guests, read zero=
 */
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
>          goto read_as_zero;
> =20
>      case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN):
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_WORD)=
;
> +        if ( reg >=3D GICD_ISENABLERnE )
> +            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE,
> +                                        DABT_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_W=
ORD);
>          if ( rank =3D=3D NULL ) goto read_as_zero;
>          vgic_lock_rank(v, rank, flags);
>          *r =3D vreg_reg32_extract(rank->ienable, info);
> @@ -699,8 +703,13 @@ static int __vgic_v3_distr_common_mmio_read(const ch=
ar *name, struct vcpu *v,
>          return 1;
> =20
>      case VRANGE32(GICD_ICENABLER, GICD_ICENABLERN):
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_WORD)=
;
> +        if ( reg >=3D GICD_ICENABLERnE )
> +            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE,
> +                                        DABT_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_W=
ORD);
>          if ( rank =3D=3D NULL ) goto read_as_zero;
>          vgic_lock_rank(v, rank, flags);
>          *r =3D vreg_reg32_extract(rank->ienable, info);
> @@ -710,20 +719,29 @@ static int __vgic_v3_distr_common_mmio_read(const c=
har *name, struct vcpu *v,
>      /* Read the pending status of an IRQ via GICD/GICR is not supported =
*/
>      case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
>      case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
>          goto read_as_zero;
> =20
>      /* Read the active status of an IRQ via GICD/GICR is not supported *=
/
>      case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
>      case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
>          goto read_as_zero;
> =20
>      case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
>      {
>          uint32_t ipriorityr;
>          uint8_t rank_index;
> =20
>          if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD ) goto=
 bad_width;
> -        rank =3D vgic_rank_offset(v, 8, reg - GICD_IPRIORITYR, DABT_WORD=
);
> +        if ( reg >=3D GICD_IPRIORITYRnE )
> +            rank =3D vgic_ext_rank_offset(v, 8, reg - GICD_IPRIORITYRnE,
> +                                        DABT_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 8, reg - GICD_IPRIORITYR, DABT_=
WORD);
>          if ( rank =3D=3D NULL ) goto read_as_zero;
>          rank_index =3D REG_RANK_INDEX(8, reg - GICD_IPRIORITYR, DABT_WOR=
D);
> =20
> @@ -737,11 +755,15 @@ static int __vgic_v3_distr_common_mmio_read(const c=
har *name, struct vcpu *v,
>      }
> =20
>      case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
>      {
>          uint32_t icfgr;
> =20
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD);
> +        if ( reg >=3D GICD_ICFGRnE )
> +            rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT=
_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD)=
;
>          if ( rank =3D=3D NULL ) goto read_as_zero;
>          vgic_lock_rank(v, rank, flags);
>          icfgr =3D rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR, DABT_WO=
RD)];
> @@ -782,46 +804,81 @@ static int __vgic_v3_distr_common_mmio_write(const =
char *name, struct vcpu *v,
>      {
>      case VRANGE32(GICD_IGROUPR, GICD_IGROUPRN):
>      case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
>          /* We do not implement security extensions for guests, write ign=
ore */
>          goto write_ignore_32;
> =20
>      case VRANGE32(GICD_ISENABLER, GICD_ISENABLERN):
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_WORD)=
;
> +        if ( reg >=3D GICD_ISENABLERnE )
> +            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISENABLERnE,
> +                                        DABT_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 1, reg - GICD_ISENABLER, DABT_W=
ORD);
>          if ( rank =3D=3D NULL ) goto write_ignore;
>          vgic_lock_rank(v, rank, flags);
>          tr =3D rank->ienable;
>          vreg_reg32_setbits(&rank->ienable, r, info);
> -        vgic_enable_irqs(v, (rank->ienable) & (~tr), rank->index);
> +        if ( reg >=3D GICD_ISENABLERnE )
> +            vgic_enable_irqs(v, (rank->ienable) & (~tr),
> +                             EXT_RANK_IDX2NUM(rank->index));
> +        else
> +            vgic_enable_irqs(v, (rank->ienable) & (~tr), rank->index);
>          vgic_unlock_rank(v, rank, flags);
>          return 1;
> =20
>      case VRANGE32(GICD_ICENABLER, GICD_ICENABLERN):
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_WORD)=
;
> +        if ( reg >=3D GICD_ICENABLERnE )
> +            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICENABLERnE,
> +                                        DABT_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 1, reg - GICD_ICENABLER, DABT_W=
ORD);
>          if ( rank =3D=3D NULL ) goto write_ignore;
>          vgic_lock_rank(v, rank, flags);
>          tr =3D rank->ienable;
>          vreg_reg32_clearbits(&rank->ienable, r, info);
> -        vgic_disable_irqs(v, (~rank->ienable) & tr, rank->index);
> +        if ( reg >=3D GICD_ICENABLERnE )
> +            vgic_disable_irqs(v, (~rank->ienable) & tr,
> +                              EXT_RANK_IDX2NUM(rank->index));
> +        else
> +            vgic_disable_irqs(v, (~rank->ienable) & tr, rank->index);
>          vgic_unlock_rank(v, rank, flags);
>          return 1;
> =20
>      case VRANGE32(GICD_ISPENDR, GICD_ISPENDRN):
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 1, reg - GICD_ISPENDR, DABT_WORD);
> +        if ( reg >=3D GICD_ISPENDRnE )
> +            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ISPENDRnE, DA=
BT_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 1, reg - GICD_ISPENDR, DABT_WOR=
D);
>          if ( rank =3D=3D NULL ) goto write_ignore;
> =20
> -        vgic_set_irqs_pending(v, r, rank->index);
> +        if ( reg >=3D GICD_ISPENDRnE )
> +            vgic_set_irqs_pending(v, r, EXT_RANK_IDX2NUM(rank->index));
> +        else
> +            vgic_set_irqs_pending(v, r, rank->index);
> =20
>          return 1;
> =20
>      case VRANGE32(GICD_ICPENDR, GICD_ICPENDRN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 1, reg - GICD_ICPENDR, DABT_WORD);
> +        if ( reg >=3D GICD_ICPENDRnE )
> +            rank =3D vgic_ext_rank_offset(v, 1, reg - GICD_ICPENDRnE, DA=
BT_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 1, reg - GICD_ICPENDR, DABT_WOR=
D);
>          if ( rank =3D=3D NULL ) goto write_ignore;
> =20
> -        vgic_check_inflight_irqs_pending(v, rank->index, r);
> +        if ( reg >=3D GICD_ICPENDRnE )
> +            vgic_check_inflight_irqs_pending(v,
> +                                             EXT_RANK_IDX2NUM(rank->inde=
x), r);
> +        else
> +            vgic_check_inflight_irqs_pending(v, rank->index, r);
> =20
>          goto write_ignore;
> =20
> @@ -838,16 +895,38 @@ static int __vgic_v3_distr_common_mmio_write(const =
char *name, struct vcpu *v,
>                 v, name, r, reg - GICD_ICACTIVER);
>          goto write_ignore_32;
> =20
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +        if ( dabt.size !=3D DABT_WORD )
> +            goto bad_width;
> +        printk(XENLOG_G_ERR
> +               "%pv: %s: unhandled word write %#"PRIregister" to ISACTIV=
ER%dE\n",
> +               v, name, r, reg - GICD_ISACTIVERnE);
> +        return 0;
> +
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +        printk(XENLOG_G_ERR
> +               "%pv: %s: unhandled word write %#"PRIregister" to ICACTIV=
ER%dE\n",
> +               v, name, r, reg - GICD_ICACTIVERnE);
> +        goto write_ignore_32;
> +
>      case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
>      {
> -        uint32_t *ipriorityr, priority;
> +        uint32_t *ipriorityr, priority, offset;
> =20
>          if ( dabt.size !=3D DABT_BYTE && dabt.size !=3D DABT_WORD ) goto=
 bad_width;
> -        rank =3D vgic_rank_offset(v, 8, reg - GICD_IPRIORITYR, DABT_WORD=
);
> +        if ( reg >=3D GICD_IPRIORITYRnE ) {

Brace should go on new line

> +            offset =3D reg - GICD_IPRIORITYRnE;
> +            rank =3D vgic_ext_rank_offset(v, 8, offset, DABT_WORD);
> +        }
> +        else
> +        {
> +            offset =3D reg - GICD_IPRIORITYR;
> +            rank =3D vgic_rank_offset(v, 8, offset, DABT_WORD);
> +        }
>          if ( rank =3D=3D NULL ) goto write_ignore;
>          vgic_lock_rank(v, rank, flags);
> -        ipriorityr =3D &rank->ipriorityr[REG_RANK_INDEX(8, reg - GICD_IP=
RIORITYR,
> -                                                      DABT_WORD)];
> +        ipriorityr =3D &rank->ipriorityr[REG_RANK_INDEX(8, offset, DABT_=
WORD)];
>          priority =3D ACCESS_ONCE(*ipriorityr);
>          vreg_reg32_update(&priority, r, info);
>          ACCESS_ONCE(*ipriorityr) =3D priority;
> @@ -859,10 +938,14 @@ static int __vgic_v3_distr_common_mmio_write(const =
char *name, struct vcpu *v,
>          goto write_ignore_32;
> =20
>      case VRANGE32(GICD_ICFGR + 4, GICD_ICFGRN): /* PPI + SPIs */
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
>          /* ICFGR1 for PPI's, which is implementation defined
>             if ICFGR1 is programmable or not. We chose to program */
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD);
> +        if ( reg >=3D GICD_ICFGRnE )
> +            rank =3D vgic_ext_rank_offset(v, 2, reg - GICD_ICFGRnE, DABT=
_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 2, reg - GICD_ICFGR, DABT_WORD)=
;
>          if ( rank =3D=3D NULL ) goto write_ignore;
>          vgic_lock_rank(v, rank, flags);
>          vreg_reg32_update(&rank->icfg[REG_RANK_INDEX(2, reg - GICD_ICFGR=
,
> @@ -1129,6 +1212,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v,=
 mmio_info_t *info,
>              typer |=3D GICD_TYPE_LPIS;
> =20
>          typer |=3D (v->domain->arch.vgic.intid_bits - 1) << GICD_TYPE_ID=
_BITS_SHIFT;
> +#ifdef CONFIG_GICV3_ESPI
> +        if ( v->domain->arch.vgic.nr_espis > 0 )
> +        {
> +            /* Set eSPI support bit for the domain */
> +            typer |=3D GICD_TYPER_ESPI;
> +            /* Set ESPI range bits */
> +            typer |=3D (DIV_ROUND_UP(v->domain->arch.vgic.nr_espis, 32) =
- 1)
> +                       << GICD_TYPER_ESPI_RANGE_SHIFT;
> +        }
> +#endif
> =20
>          *r =3D vreg_reg32_extract(typer, info);
> =20
> @@ -1194,6 +1287,16 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v,=
 mmio_info_t *info,
>      case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
>      case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
>      case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
>          /*
>           * Above all register are common with GICR and GICD
>           * Manage in common
> @@ -1201,6 +1304,7 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, =
mmio_info_t *info,
>          return __vgic_v3_distr_common_mmio_read("vGICD", v, info, gicd_r=
eg, r);
> =20
>      case VRANGE32(GICD_NSACR, GICD_NSACRN):
> +    case VRANGE32(GICD_NSACRnE, GICD_NSACRnEN):
>          /* We do not implement security extensions for guests, read zero=
 */
>          goto read_as_zero_32;
> =20
> @@ -1216,16 +1320,21 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v=
, mmio_info_t *info,
>          /* Replaced with GICR_ISPENDR0. So ignore write */
>          goto read_as_zero_32;
> =20
> -    case VRANGE32(0x0F30, 0x60FC):
> +    case VRANGE32(0x0F30, 0x0FFC):
>          goto read_reserved;
> =20
>      case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
> +    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
>      {
>          uint64_t irouter;
> =20
>          if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
> -                                DABT_DOUBLE_WORD);
> +        if ( gicd_reg >=3D GICD_IROUTERnE )
> +            rank =3D vgic_ext_rank_offset(v, 64, gicd_reg - GICD_IROUTER=
nE,
> +                                        DABT_DOUBLE_WORD);
> +        else
> +            rank =3D vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
> +                                    DABT_DOUBLE_WORD);
>          if ( rank =3D=3D NULL ) goto read_as_zero;
>          vgic_lock_rank(v, rank, flags);
>          irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTER);
> @@ -1235,8 +1344,8 @@ static int vgic_v3_distr_mmio_read(struct vcpu *v, =
mmio_info_t *info,
> =20
>          return 1;
>      }
> -
> -    case VRANGE32(0x7FE0, 0xBFFC):
> +    case VRANGE32(0x3700, 0x60FC):
> +    case VRANGE32(0xA004, 0xBFFC):
>          goto read_reserved;
> =20
>      case VRANGE32(0xC000, 0xFFCC):
> @@ -1382,12 +1491,23 @@ static int vgic_v3_distr_mmio_write(struct vcpu *=
v, mmio_info_t *info,
>      case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
>      case VRANGE32(GICD_ICFGR, GICD_ICFGRN):
>      case VRANGE32(GICD_IGRPMODR, GICD_IGRPMODRN):
> +    case VRANGE32(GICD_IGROUPRnE, GICD_IGROUPRnEN):
> +    case VRANGE32(GICD_ISENABLERnE, GICD_ISENABLERnEN):
> +    case VRANGE32(GICD_ICENABLERnE, GICD_ICENABLERnEN):
> +    case VRANGE32(GICD_ISPENDRnE, GICD_ISPENDRnEN):
> +    case VRANGE32(GICD_ICPENDRnE, GICD_ICPENDRnEN):
> +    case VRANGE32(GICD_ISACTIVERnE, GICD_ISACTIVERnEN):
> +    case VRANGE32(GICD_ICACTIVERnE, GICD_ICACTIVERnEN):
> +    case VRANGE32(GICD_IPRIORITYRnE, GICD_IPRIORITYRnEN):
> +    case VRANGE32(GICD_ICFGRnE, GICD_ICFGRnEN):
> +    case VRANGE32(GICD_IGRPMODRnE, GICD_IGRPMODRnEN):
>          /* Above registers are common with GICR and GICD
>           * Manage in common */
>          return __vgic_v3_distr_common_mmio_write("vGICD", v, info,
>                                                   gicd_reg, r);
> =20
>      case VRANGE32(GICD_NSACR, GICD_NSACRN):
> +    case VRANGE32(GICD_NSACRnE, GICD_NSACRnEN):
>          /* We do not implement security extensions for guests, write ign=
ore */
>          goto write_ignore_32;
> =20
> @@ -1405,26 +1525,38 @@ static int vgic_v3_distr_mmio_write(struct vcpu *=
v, mmio_info_t *info,
>          if ( dabt.size !=3D DABT_WORD ) goto bad_width;
>          return 0;
> =20
> -    case VRANGE32(0x0F30, 0x60FC):
> +    case VRANGE32(0x0F30, 0x0FFC):
>          goto write_reserved;
> =20
>      case VRANGE64(GICD_IROUTER32, GICD_IROUTER1019):
> +    case VRANGE64(GICD_IROUTERnE, GICD_IROUTERnEN):
>      {
>          uint64_t irouter;
> +        unsigned int offset, virq;
> =20
>          if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
> -        rank =3D vgic_rank_offset(v, 64, gicd_reg - GICD_IROUTER,
> -                                DABT_DOUBLE_WORD);
> +        if ( gicd_reg >=3D GICD_IROUTERnE ) {

Braces should go into separate line

> +            offset =3D gicd_reg - GICD_IROUTERnE;
> +            rank =3D vgic_ext_rank_offset(v, 64, offset, DABT_DOUBLE_WOR=
D);
> +        } else {

... so "else" also should be on a separate line

> +            offset =3D gicd_reg - GICD_IROUTER;
> +            rank =3D vgic_rank_offset(v, 64, offset, DABT_DOUBLE_WORD);
> +        }
>          if ( rank =3D=3D NULL ) goto write_ignore;
>          vgic_lock_rank(v, rank, flags);
> -        irouter =3D vgic_fetch_irouter(rank, gicd_reg - GICD_IROUTER);
> +        irouter =3D vgic_fetch_irouter(rank, offset);
>          vreg_reg64_update(&irouter, r, info);
> -        vgic_store_irouter(v->domain, rank, gicd_reg - GICD_IROUTER, iro=
uter);
> +        if ( gicd_reg >=3D GICD_IROUTERnE )
> +            virq =3D ESPI_IDX2INTID(offset / NR_BYTES_PER_IROUTER);
> +        else
> +            virq =3D offset / NR_BYTES_PER_IROUTER;
> +        vgic_store_irouter(v->domain, rank, virq, irouter);
>          vgic_unlock_rank(v, rank, flags);
>          return 1;
>      }
> =20
> -    case VRANGE32(0x7FE0, 0xBFFC):
> +    case VRANGE32(0x3700, 0x60FC):
> +    case VRANGE32(0xA004, 0xBFFC):
>          goto write_reserved;
> =20
>      case VRANGE32(0xC000, 0xFFCC):
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index c9b9528c66..27ffdf316c 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -193,6 +193,18 @@ int domain_vgic_register(struct domain *d, unsigned =
int *mmio_count)
>  }
> =20
>  #ifdef CONFIG_GICV3_ESPI
> +/*
> + * The function behavior is the same as for regular SPIs (vgic_rank_offs=
et),
> + * but it operates with extended SPI ranks.
> + */
> +struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int =
b,
> +                                           unsigned int n, unsigned int =
s)
> +{
> +    unsigned int rank =3D REG_RANK_NR(b, (n >> s));
> +
> +    return vgic_get_rank(v, rank + EXT_RANK_MIN);
> +}
> +
>  static unsigned int vgic_num_spi_lines(struct domain *d)
>  {
>      return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
> @@ -241,6 +253,17 @@ struct pending_irq *espi_to_pending(struct domain *d=
, unsigned int irq)
>  {
>      return NULL;
>  }
> +
> +/*
> + * It is expected that, in the case of CONFIG_GICV3_ESPI=3Dn, the functi=
on will
> + * return NULL. In this scenario, mmio_read/mmio_write will be treated a=
s
> + * RAZ/WI, as expected.
> + */
> +struct vgic_irq_rank *vgic_ext_rank_offset(struct vcpu *v, unsigned int =
b,
> +                                           unsigned int n, unsigned int =
s)
> +{
> +    return NULL;
> +}
>  #endif
> =20
>  static unsigned int vgic_num_alloc_irqs(struct domain *d)

--=20
WBR, Volodymyr=


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	 h8omc+T5rDiVNCk2ZTtSYWLEncEcpHc5LKDA3Fu4e+9+N+X9k+cwrKjBlom/XP1MQx
	 q8ZAV0h/bZQvA==
Date: Fri, 29 Aug 2025 13:14:03 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: dmukhin@xen.org
cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, 
    dmukhin@ford.com
Subject: Re: [PATCH v5 05/15] emul/ns16x50: implement EIR/IIR registers
In-Reply-To: <20250828235409.2835815-6-dmukhin@ford.com>
Message-ID: 
References: <20250828235409.2835815-1-dmukhin@ford.com> <20250828235409.2835815-6-dmukhin@ford.com>
User-Agent: Alpine 2.22 (DEB 394 2020-01-19)
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On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> From: Denis Mukhin  
> 
> Add interrupt enable register emulation (EIR) and interrupt identity reason

EIR->IER

> (IIR) register emulation to the I/O port handler.
> 
> Also add routines for asserting/deasserting the virtual ns16x50 interrupt
> line as a dependent on IIR code.
> 
> Poke ns16x50_irq_check() on every I/O register access because the emulator
> does not have clock emulation anyway (e.g. for baud rate emulation).
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v4:
> - new patch
> ---
>  xen/common/emul/vuart/ns16x50.c | 177 +++++++++++++++++++++++++++++++-
>  1 file changed, 176 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> index f9f307a4ad24..20597cc36b35 100644
> --- a/xen/common/emul/vuart/ns16x50.c
> +++ b/xen/common/emul/vuart/ns16x50.c
> @@ -85,9 +85,131 @@ struct vuart_ns16x50 {
>      spinlock_t lock;                    /* Protection */
>  };
>  
> +static bool ns16x50_fifo_rx_empty(const struct vuart_ns16x50 *vdev)
> +{
> +    const struct xencons_interface *cons = &vdev->cons;
> +
> +    return cons->in_prod == cons->in_cons;
> +}

there is no ring so far so I would not add ns16x50_fifo_rx_empty for now


>  static inline uint8_t cf_check ns16x50_dlab_get(const struct vuart_ns16x50 *vdev)
>  {
> -    return 0;
> +    return vdev->regs[UART_LCR] & UART_LCR_DLAB ? 1 : 0;
> +}
> +
> +static bool cf_check ns16x50_iir_check_lsi(const struct vuart_ns16x50 *vdev)
> +{
> +    return vdev->regs[UART_LSR] & UART_LSR_MASK;
> +}
> +
> +static bool cf_check ns16x50_iir_check_rda(const struct vuart_ns16x50 *vdev)
> +{
> +    return !ns16x50_fifo_rx_empty(vdev);
> +}
> +
> +static bool cf_check ns16x50_iir_check_thr(const struct vuart_ns16x50 *vdev)
> +{
> +    return vdev->regs[NS16X50_REGS_NUM + UART_IIR] & UART_IIR_THR;
> +}
> +
> +static bool cf_check ns16x50_iir_check_msi(const struct vuart_ns16x50 *vdev)
> +{
> +    return vdev->regs[UART_MSR] & UART_MSR_CHANGE;
> +}
> +
> +/*
> + * Get the interrupt identity reason.
> + *
> + * IIR is re-calculated once called, because ns16x50 always reports high
> + * priority events first.
> + * regs[NS16X50_REGS_NUM + UART_IIR] is used to store THR reason only.
> + */
> +static uint8_t ns16x50_iir_get(const struct vuart_ns16x50 *vdev)
> +{
> +    /*
> +     * Interrupt identity reasons by priority.
> +     * NB: high priority are at lower indexes below.
> +     */
> +    static const struct {
> +        bool (*check)(const struct vuart_ns16x50 *vdev);
> +        uint8_t ier;
> +        uint8_t iir;
> +    } iir_by_prio[] = {
> +        [0] = { ns16x50_iir_check_lsi, UART_IER_ELSI,   UART_IIR_LSI },
> +        [1] = { ns16x50_iir_check_rda, UART_IER_ERDAI,  UART_IIR_RDA },
> +        [2] = { ns16x50_iir_check_thr, UART_IER_ETHREI, UART_IIR_THR },
> +        [3] = { ns16x50_iir_check_msi, UART_IER_EMSI,   UART_IIR_MSI },
> +    };
> +    const uint8_t *regs = vdev->regs;
> +    uint8_t iir = 0;
> +    unsigned int i;
> +
> +    /*
> +     * NB: every interaction w/ ns16x50 registers (except DLAB=1) goes
> +     * through that call.
> +     */
> +    ASSERT(spin_is_locked(&vdev->lock));
> +
> +    for ( i = 0; i < ARRAY_SIZE(iir_by_prio); i++ )
> +    {
> +        if ( (regs[UART_IER] & iir_by_prio[i].ier) &&
> +             iir_by_prio[i].check(vdev) )
> +            break;
> +
> +    }
> +    if ( i == ARRAY_SIZE(iir_by_prio) )
> +        iir |= UART_IIR_NOINT;
> +    else
> +        iir |= iir_by_prio[i].iir;
> +
> +    if ( regs[UART_FCR] & UART_FCR_ENABLE )
> +        iir |= UART_IIR_FE;
> +
> +    return iir;
> +}
> +
> +static void ns16x50_irq_assert(const struct vuart_ns16x50 *vdev)
> +{
> +    struct domain *d = vdev->owner;
> +    const struct vuart_info *info = vdev->info;
> +    int vector;
> +
> +    if ( has_vpic(d) ) /* HVM */
> +        vector = hvm_isa_irq_assert(d, info->irq, vioapic_get_vector);
> +    else
> +        ASSERT_UNREACHABLE();
> +
> +    ns16x50_debug(vdev, "IRQ#%d vector %d assert\n", info->irq, vector);
> +}
> +
> +static void ns16x50_irq_deassert(const struct vuart_ns16x50 *vdev)
> +{
> +    struct domain *d = vdev->owner;
> +    const struct vuart_info *info = vdev->info;
> +
> +    if ( has_vpic(d) ) /* HVM */
> +        hvm_isa_irq_deassert(d, info->irq);
> +    else
> +        ASSERT_UNREACHABLE();
> +
> +    ns16x50_debug(vdev, "IRQ#%d deassert\n", info->irq);
> +}
> +
> +/*
> + * Assert/deassert virtual ns16x50 interrupt line.
> + */
> +static void ns16x50_irq_check(const struct vuart_ns16x50 *vdev)
> +{
> +    uint8_t iir = ns16x50_iir_get(vdev);
> +    const struct vuart_info *info = vdev->info;
> +
> +    if ( iir & UART_IIR_NOINT )
> +        ns16x50_irq_assert(vdev);

It is a bit strange that if "NOINT" is set, we raise the interrupt


> +    else
> +        ns16x50_irq_deassert(vdev);
> +
> +    ns16x50_debug(vdev, "IRQ#%d IIR 0x%02x %s\n", info->irq, iir,
> +                  (iir & UART_IIR_NOINT) ? "deassert" : "assert");
>  }
>  
>  /*
> @@ -102,6 +224,29 @@ static int ns16x50_io_write8(
>  
>      if ( ns16x50_dlab_get(vdev) && (reg == UART_DLL || reg == UART_DLM) )
>          regs[NS16X50_REGS_NUM + reg] = val;
> +    else
> +    {
> +        switch ( reg )
> +        {
> +        case UART_IER:
> +            /*
> +             * NB: Make sure THR interrupt is re-triggered once guest OS
> +             * re-enabled ETHREI in EIR.

EIR->IER


> +             */
> +            if ( val & regs[UART_IER] & UART_IER_ETHREI )
> +                regs[NS16X50_REGS_NUM + UART_IIR] |= UART_IIR_THR;

I am confused by this. Shouldn't it be :

if ( (val & UART_IER_ETHREI) && !(regs[UART_IER] & UART_IER_ETHREI) )

Meaning set UART_IIR_THR if ETHREI goes 0->1 ?


> +            regs[UART_IER] = val & UART_IER_MASK;
> +
> +            break;
> +
> +        default:
> +            rc = -EINVAL;
> +            break;
> +        }
> +
> +        ns16x50_irq_check(vdev);
> +    }
>  
>      return rc;
>  }
> @@ -164,6 +309,29 @@ static int ns16x50_io_read8(
>  
>      if ( ns16x50_dlab_get(vdev) && (reg == UART_DLL || reg == UART_DLM) )
>          val = regs[NS16X50_REGS_NUM + reg];
> +    else {
> +        switch ( reg )
> +        {
> +        case UART_IER:
> +            val = regs[UART_IER];
> +            break;
> +
> +        case UART_IIR: /* RO */
> +            val = ns16x50_iir_get(vdev);
> +
> +            /* NB: clear IIR scratch location */
> +            if ( val & UART_IIR_THR )
> +                regs[NS16X50_REGS_NUM + UART_IIR] &= ~UART_IIR_THR;

Maybe add an in-code comment why it is a good idea to clear THR here


> +
> +            break;
> +
> +        default:
> +            rc = -EINVAL;
> +            break;
> +        }
> +
> +        ns16x50_irq_check(vdev);
> +    }
>  
>      *data = val;
>  
> @@ -314,8 +482,15 @@ static int ns16x50_init(void *arg)
>      vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & 0xff;
>      vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
>  
> +    /* ns16x50 shall assert UART_IIR_THR whenever transmitter is empty. */
> +    vdev->regs[NS16X50_REGS_NUM + UART_IIR] = UART_IIR_THR;
> +
>      register_portio_handler(d, info->base_addr, info->size, ns16x50_io_handle);
>  
> +    spin_lock(&vdev->lock);
> +    ns16x50_irq_check(vdev);
> +    spin_unlock(&vdev->lock);
> +
>      return 0;
>  }
>  
> -- 
> 2.51.0
> 


From xen-devel-bounces@lists.xenproject.org Fri Aug 29 20:28:56 2025
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Date: Fri, 29 Aug 2025 13:28:41 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: dmukhin@xen.org
cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, 
    dmukhin@ford.com
Subject: Re: [PATCH v5 06/15] emul/ns16x50: implement THR/RBR registers
In-Reply-To: <20250828235409.2835815-7-dmukhin@ford.com>
Message-ID: 
References: <20250828235409.2835815-1-dmukhin@ford.com> <20250828235409.2835815-7-dmukhin@ford.com>
User-Agent: Alpine 2.22 (DEB 394 2020-01-19)
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On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> From: Denis Mukhin  
> 
> Add RBR/THR registers emulation to the I/O port handlder.
> 
> Also, add RX/TX FIFO management code since RBR depends on RX FIFO and
> THR depends on TX FIFO.
> 
> FIFOs are not emulated as per UART specs for simplicity (not need to emulate
> baud rate). Emulator does not emulate NS8250 (no FIFO), NS16550a (16 bytes) or
> NS16750 (64 bytes).
> 
> FIFOs are emulated by means of using xencons_interface which conveniently
> provides primitives for buffer management and later can be used for
> inter-domain communication similarly to vpl011.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v4:
> - new patch
> ---
>  xen/common/emul/vuart/ns16x50.c | 135 ++++++++++++++++++++++++++++++++
>  1 file changed, 135 insertions(+)
> 
> diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> index 20597cc36b35..efb2f4c6441c 100644
> --- a/xen/common/emul/vuart/ns16x50.c
> +++ b/xen/common/emul/vuart/ns16x50.c
> @@ -92,6 +92,119 @@ static bool ns16x50_fifo_rx_empty(const struct vuart_ns16x50 *vdev)
>      return cons->in_prod == cons->in_cons;
>  }
>  
> +static bool ns16x50_fifo_rx_full(const struct vuart_ns16x50 *vdev)
> +{
> +    const struct xencons_interface *cons = &vdev->cons;
> +
> +    return cons->in_prod - cons->in_cons == ARRAY_SIZE(cons->in);
> +}
> +
> +static void ns16x50_fifo_rx_reset(struct vuart_ns16x50 *vdev)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +
> +    cons->in_cons = cons->in_prod;
> +}
> +
> +static int ns16x50_fifo_rx_getchar(struct vuart_ns16x50 *vdev)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +    int rc;
> +
> +    if ( ns16x50_fifo_rx_empty(vdev) )
> +    {
> +        ns16x50_debug(vdev, "RX FIFO empty\n");
> +        rc = -ENODATA;
> +    }
> +    else
> +    {
> +        rc = cons->in[MASK_XENCONS_IDX(cons->in_cons, cons->in)];
> +        cons->in_cons++;
> +    }
> +
> +    return rc;

The signed integer to char conversion here is not great from a MISRA
perspective. I think it would be better to keep rc as success/failure
return value and take the read char as a pointer parameter.


> +}
> +
> +static int ns16x50_fifo_rx_putchar(struct vuart_ns16x50 *vdev, char c)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +    int rc;
> +
> +    /*
> +     * FIFO-less 8250/16450 UARTs: newly arrived word overwrites the contents
> +     * of the THR.
> +     */
> +    if ( ns16x50_fifo_rx_full(vdev) )
> +    {
> +        ns16x50_debug(vdev, "RX FIFO full; resetting\n");
> +        ns16x50_fifo_rx_reset(vdev);
> +        rc = -ENOSPC;
> +    }
> +    else
> +        rc = 0;
> +
> +    cons->in[MASK_XENCONS_IDX(cons->in_prod, cons->in)] = c;
> +    cons->in_prod++;
> +
> +    return rc;
> +}
> +
> +static bool ns16x50_fifo_tx_empty(const struct vuart_ns16x50 *vdev)
> +{
> +    const struct xencons_interface *cons = &vdev->cons;
> +
> +    return cons->out_prod == cons->out_cons;
> +}
> +
> +static void ns16x50_fifo_tx_reset(struct vuart_ns16x50 *vdev)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +
> +    cons->out_prod = 0;
> +    ASSERT(cons->out_cons == cons->out_prod);

I am not sure about this.. why resetting the out_prod index? In theory
it could keep increasing until wrap around and still go forward thanks
to the mask


> +}
> +
> +/*
> + * Flush cached output to Xen console.
> + */
> +static void ns16x50_fifo_tx_flush(struct vuart_ns16x50 *vdev)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +    struct domain *d = vdev->owner;
> +
> +    if ( ns16x50_fifo_tx_empty(vdev) )
> +        return;
> +
> + UART_IIR_THR   ASSERT(cons->out_prod < ARRAY_SIZE(cons->out));
> +    cons->out[cons->out_prod] = '\0';

should use MASK_XENCONS_IDX to access the array


> +    cons->out_prod++;
> +
> +    guest_printk(d, guest_prefix "%s", cons->out);
> +
> +    ns16x50_fifo_tx_reset(vdev);

set UART_IIR_THR and call ns16x50_irq_check ?


> +}
> +
> +/*
> + * Accumulate guest OS output before sending to Xen console.
> + */
> +static void ns16x50_fifo_tx_putchar(struct vuart_ns16x50 *vdev, char ch)
> +{
> +    struct xencons_interface *cons = &vdev->cons;
> +
> +    if ( !is_console_printable(ch) )
> +        return;
> +
> +    if ( ch != '\0' )
> +    {
> +        cons->out[cons->out_prod] = ch;

should use MASK_XENCONS_IDX to access the array


> +        cons->out_prod++;
> +    }
> +
> +    if ( cons->out_prod == ARRAY_SIZE(cons->out) - 1 ||
> +         ch == '\n' || ch == '\0' )
> +        ns16x50_fifo_tx_flush(vdev);
> +}
> +
>  static inline uint8_t cf_check ns16x50_dlab_get(const struct vuart_ns16x50 *vdev)
>  {
>      return vdev->regs[UART_LCR] & UART_LCR_DLAB ? 1 : 0;
> @@ -228,6 +341,16 @@ static int ns16x50_io_write8(
>      {
>          switch ( reg )
>          {
> +        case UART_THR:
> +            if ( regs[UART_MCR] & UART_MCR_LOOP )
> +                rc = ns16x50_fifo_rx_putchar(vdev, val);
> +            else
> +                ns16x50_fifo_tx_putchar(vdev, val);

should UART_IIR_THR be cleared here?


> +            rc = 0;
> +
> +            break;
> +
>          case UART_IER:
>              /*
>               * NB: Make sure THR interrupt is re-triggered once guest OS
> @@ -312,6 +435,14 @@ static int ns16x50_io_read8(
>      else {
>          switch ( reg )
>          {
> +        case UART_RBR:
> +            rc = ns16x50_fifo_rx_getchar(vdev);
> +            if ( rc >= 0 )
> +                val = (uint8_t)rc;

Empty fifo check?


> +            rc = 0;
> +            break;
> +
>          case UART_IER:
>              val = regs[UART_IER];
>              break;
> @@ -499,6 +630,10 @@ static void cf_check ns16x50_deinit(void *arg)
>      struct vuart_ns16x50 *vdev = arg;
>  
>      ASSERT(vdev);
> +
> +    spin_lock(&vdev->lock);
> +    ns16x50_fifo_tx_flush(vdev);
> +    spin_unlock(&vdev->lock);
>  }
>  
>  static void * cf_check ns16x50_alloc(struct domain *d, const struct vuart_info *info)
> -- 
> 2.51.0
> 


From xen-devel-bounces@lists.xenproject.org Fri Aug 29 20:34:51 2025
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Date: Fri, 29 Aug 2025 13:34:39 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: Stefano Stabellini 
cc: dmukhin@xen.org, xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, dmukhin@ford.com
Subject: Re: [PATCH v5 06/15] emul/ns16x50: implement THR/RBR registers
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Message-ID: 
References: <20250828235409.2835815-1-dmukhin@ford.com> <20250828235409.2835815-7-dmukhin@ford.com> 
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On Fri, 29 Aug 2025, Stefano Stabellini wrote:
> On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> > From: Denis Mukhin  
> > 
> > Add RBR/THR registers emulation to the I/O port handlder.
> > 
> > Also, add RX/TX FIFO management code since RBR depends on RX FIFO and
> > THR depends on TX FIFO.
> > 
> > FIFOs are not emulated as per UART specs for simplicity (not need to emulate
> > baud rate). Emulator does not emulate NS8250 (no FIFO), NS16550a (16 bytes) or
> > NS16750 (64 bytes).
> > 
> > FIFOs are emulated by means of using xencons_interface which conveniently
> > provides primitives for buffer management and later can be used for
> > inter-domain communication similarly to vpl011.
> > 
> > Signed-off-by: Denis Mukhin 
> > ---
> > Changes since v4:
> > - new patch
> > ---
> >  xen/common/emul/vuart/ns16x50.c | 135 ++++++++++++++++++++++++++++++++
> >  1 file changed, 135 insertions(+)
> > 
> > diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> > index 20597cc36b35..efb2f4c6441c 100644
> > --- a/xen/common/emul/vuart/ns16x50.c
> > +++ b/xen/common/emul/vuart/ns16x50.c
> > @@ -92,6 +92,119 @@ static bool ns16x50_fifo_rx_empty(const struct vuart_ns16x50 *vdev)
> >      return cons->in_prod == cons->in_cons;
> >  }
> >  
> > +static bool ns16x50_fifo_rx_full(const struct vuart_ns16x50 *vdev)
> > +{
> > +    const struct xencons_interface *cons = &vdev->cons;
> > +
> > +    return cons->in_prod - cons->in_cons == ARRAY_SIZE(cons->in);
> > +}
> > +
> > +static void ns16x50_fifo_rx_reset(struct vuart_ns16x50 *vdev)
> > +{
> > +    struct xencons_interface *cons = &vdev->cons;
> > +
> > +    cons->in_cons = cons->in_prod;
> > +}
> > +
> > +static int ns16x50_fifo_rx_getchar(struct vuart_ns16x50 *vdev)
> > +{
> > +    struct xencons_interface *cons = &vdev->cons;
> > +    int rc;
> > +
> > +    if ( ns16x50_fifo_rx_empty(vdev) )
> > +    {
> > +        ns16x50_debug(vdev, "RX FIFO empty\n");
> > +        rc = -ENODATA;
> > +    }
> > +    else
> > +    {
> > +        rc = cons->in[MASK_XENCONS_IDX(cons->in_cons, cons->in)];
> > +        cons->in_cons++;
> > +    }
> > +
> > +    return rc;
> 
> The signed integer to char conversion here is not great from a MISRA
> perspective. I think it would be better to keep rc as success/failure
> return value and take the read char as a pointer parameter.
> 
> 
> > +}
> > +
> > +static int ns16x50_fifo_rx_putchar(struct vuart_ns16x50 *vdev, char c)
> > +{
> > +    struct xencons_interface *cons = &vdev->cons;
> > +    int rc;
> > +
> > +    /*
> > +     * FIFO-less 8250/16450 UARTs: newly arrived word overwrites the contents
> > +     * of the THR.
> > +     */
> > +    if ( ns16x50_fifo_rx_full(vdev) )
> > +    {
> > +        ns16x50_debug(vdev, "RX FIFO full; resetting\n");
> > +        ns16x50_fifo_rx_reset(vdev);
> > +        rc = -ENOSPC;
> > +    }
> > +    else
> > +        rc = 0;
> > +
> > +    cons->in[MASK_XENCONS_IDX(cons->in_prod, cons->in)] = c;
> > +    cons->in_prod++;
> > +
> > +    return rc;
> > +}
> > +
> > +static bool ns16x50_fifo_tx_empty(const struct vuart_ns16x50 *vdev)
> > +{
> > +    const struct xencons_interface *cons = &vdev->cons;
> > +
> > +    return cons->out_prod == cons->out_cons;
> > +}
> > +
> > +static void ns16x50_fifo_tx_reset(struct vuart_ns16x50 *vdev)
> > +{
> > +    struct xencons_interface *cons = &vdev->cons;
> > +
> > +    cons->out_prod = 0;
> > +    ASSERT(cons->out_cons == cons->out_prod);
> 
> I am not sure about this.. why resetting the out_prod index? In theory
> it could keep increasing until wrap around and still go forward thanks
> to the mask

I get it now .. it is because it is called from ns16x50_fifo_tx_flush
right after printing to the real console.

I think it is better to simply do:

  cons->out_cons = cons->out_prod;

which effectively clears out the whole buffer. It is dangerous to do:

  cons->out_prod = 0;

without also doing:

  cons->out_cons = 0;

Also, if ns16x50_fifo_tx_flush is the only caller of
ns16x50_fifo_tx_reset, I would open code the implementation directly
inside ns16x50_fifo_tx_flush to make it more obvious.


> > +}
> > +
> > +/*
> > + * Flush cached output to Xen console.
> > + */
> > +static void ns16x50_fifo_tx_flush(struct vuart_ns16x50 *vdev)
> > +{
> > +    struct xencons_interface *cons = &vdev->cons;
> > +    struct domain *d = vdev->owner;
> > +
> > +    if ( ns16x50_fifo_tx_empty(vdev) )
> > +        return;
> > +
> > + UART_IIR_THR   ASSERT(cons->out_prod < ARRAY_SIZE(cons->out));
> > +    cons->out[cons->out_prod] = '\0';
> 
> should use MASK_XENCONS_IDX to access the array
> 
> 
> > +    cons->out_prod++;
> > +
> > +    guest_printk(d, guest_prefix "%s", cons->out);
> > +
> > +    ns16x50_fifo_tx_reset(vdev);
> 
> set UART_IIR_THR and call ns16x50_irq_check ?
> 
> 
> > +}



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Date: Fri, 29 Aug 2025 13:38:02 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: dmukhin@xen.org
cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, 
    dmukhin@ford.com
Subject: Re: [PATCH v5 07/15] emul/ns16x50: implement FCR register
 (write-only)
In-Reply-To: <20250828235409.2835815-8-dmukhin@ford.com>
Message-ID: 
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On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> From: Denis Mukhin  
> 
> Add emulation logic for FCR register.
> 
> Note, that does not hooks FIFO interrupt moderation to the FIFO management
> code.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v4:
> - new patch
> ---
>  xen/common/emul/vuart/ns16x50.c | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> index efb2f4c6441c..65ca96dd8bd3 100644
> --- a/xen/common/emul/vuart/ns16x50.c
> +++ b/xen/common/emul/vuart/ns16x50.c
> @@ -363,6 +363,30 @@ static int ns16x50_io_write8(
>  
>              break;
>  
> +        case UART_FCR: /* WO */
> +            if ( val & UART_FCR_RESERVED0 )
> +                ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
> +                             UART_FCR_RESERVED0);
> +
> +            if ( val & UART_FCR_RESERVED1 )
> +                ns16x50_warn(vdev, "FCR: attempt to set reserved bit: %x\n",
> +                             UART_FCR_RESERVED1);
> +
> +            if ( val & UART_FCR_CLRX )
> +                ns16x50_fifo_rx_reset(vdev);
> +
> +            if ( val & UART_FCR_CLTX )
> +                ns16x50_fifo_tx_flush(vdev);

Should UART_FCR_CLTX actually emit data or only clear the buffer?

set UART_IIR_THR ?


> +
> +            if ( val & UART_FCR_ENABLE )
> +                val &= UART_FCR_ENABLE | UART_FCR_DMA | UART_FCR_TRG_MASK;
> +            else
> +                val = 0;
> +
> +            regs[UART_FCR] = val;


ns16x50_irq_check ?


> +            break;
> +
>          default:
>              rc = -EINVAL;
>              break;
> -- 
> 2.51.0
> 


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From: Volodymyr Babchuk 
To: Leonid Komarianskyi 
CC: "xen-devel@lists.xenproject.org" ,
	"olekstysh@gmail.com" , Stefano Stabellini
	, Julien Grall , Bertrand Marquis
	, Michal Orzel 
Subject: Re: [PATCH v5 08/12] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Topic: [PATCH v5 08/12] xen/arm: vgic: add resource management for
 extended SPIs
Thread-Index: AQHcGP7hrcU5X1RXvUyGwHbXwaiTdQ==
Date: Fri, 29 Aug 2025 20:45:01 +0000
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References: 
	<4b13dea924eabf1370d3f31030f3eef48371de06.1756481577.git.leonid_komarianskyi@epam.com>
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 <4b13dea924eabf1370d3f31030f3eef48371de06.1756481577.git.leonid_komarianskyi@epam.com>
	(Leonid Komarianskyi's message of "Fri, 29 Aug 2025 16:06:28 +0000")
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Hi Leonid,

Leonid Komarianskyi  writes:

> This change introduces resource management in the VGIC to handle
> extended SPIs introduced in GICv3.1. The pending_irqs and
> allocated_irqs arrays are resized to support the required
> number of eSPIs, based on what is supported by the hardware and
> requested by the guest. A new field, ext_shared_irqs, is added
> to the VGIC structure to store information about eSPIs, similar
> to how shared_irqs is used for regular SPIs.
>
> Since the eSPI range starts at INTID 4096 and INTIDs between 1025
> and 4095 are reserved, helper macros are introduced to simplify the
> transformation of indices and to enable easier access to eSPI-specific
> resources. These changes prepare the VGIC for processing eSPIs as
> required by future functionality.
>
> The initialization and deinitialization paths for vgic have been updated
> to allocate and free these resources appropriately. Additionally,
> updated handling of INTIDs greater than 1024, passed from the toolstack
> during domain creation, and verification logic ensures only valid SPI or
> eSPI INTIDs are used.
>
> The existing SPI behavior remains unaffected when guests do not request
> eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
> option is disabled.
>
> Signed-off-by: Leonid Komarianskyi 
>
> ---
> Changes in V5:
> - removed the has_espi field because it can be determined by checking
>   whether domain->arch.vgic.nr_espis is zero or not
> - since vgic_ext_rank_offset is not used in this patch, it has been
>   moved to the appropriate patch in the patch series, which implements
>   vgic eSPI registers emulation and requires this function
> - removed ifdefs for eSPI-specific macros to reduce the number of ifdefs
>   and code duplication in further changes
> - fixed minor nit: used %pd for printing domain with its ID
>
> Changes in V4:
> - added has_espi field to simplify determining whether a domain is able
>   to operate with eSPI
> - fixed formatting issues and misspellings
>
> Changes in V3:
> - fixed formatting for lines with more than 80 symbols
> - introduced helper functions to be able to use stubs in case of
>   CONFIG_GICV3_ESPI disabled, and as a result, reduce the number of
>   #ifdefs
> - fixed checks for nr_spis in domain_vgic_init
> - updated comment about nr_spis adjustments with dom0less mention
> - moved comment with additional explanations before checks
> - used unsigned int for indexes since they cannot be negative
> - removed unnecessary parentheses
> - move vgic_ext_rank_offset to the below ifdef guard, to reduce the
>   number of ifdefs
>
> Changes in V2:
> - change is_espi_rank to is_valid_espi_rank to verify whether the array
>   element ext_shared_irqs exists. The previous version, is_espi_rank,
>   only checked if the rank index was less than the maximum possible eSPI
>   rank index, but this could potentially result in accessing a
>   non-existing array element. To address this, is_valid_espi_rank was
>   introduced, which ensures that the required eSPI rank exists
> - move gic_number_espis to
>   xen/arm: gicv3: implement handling of GICv3.1 eSPI
> - update vgic_is_valid_irq checks to allow operating with eSPIs
> - remove redundant newline in vgic_allocate_virq
> ---
>  xen/arch/arm/include/asm/vgic.h |  12 ++
>  xen/arch/arm/vgic.c             | 199 +++++++++++++++++++++++++++++++-
>  2 files changed, 208 insertions(+), 3 deletions(-)
>
> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/v=
gic.h
> index 3e7cbbb196..912d5b7694 100644
> --- a/xen/arch/arm/include/asm/vgic.h
> +++ b/xen/arch/arm/include/asm/vgic.h
> @@ -146,6 +146,10 @@ struct vgic_dist {
>      int nr_spis; /* Number of SPIs */
>      unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
>      struct vgic_irq_rank *shared_irqs;
> +#ifdef CONFIG_GICV3_ESPI
> +    struct vgic_irq_rank *ext_shared_irqs;
> +    int nr_espis; /* Number of extended SPIs */
> +#endif
>      /*
>       * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
>       * struct arch_vcpu.
> @@ -243,6 +247,14 @@ struct vgic_ops {
>  /* Number of ranks of interrupt registers for a domain */
>  #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
> +#endif
> +#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
> +#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
> +#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
> +#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
> +
>  #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
>  #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
> =20
> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
> index 2bbf4d99aa..c9b9528c66 100644
> --- a/xen/arch/arm/vgic.c
> +++ b/xen/arch/arm/vgic.c
> @@ -27,9 +27,82 @@
> =20
>  bool vgic_is_valid_line(struct domain *d, unsigned int virq)
>  {
> +#ifdef CONFIG_GICV3_ESPI
> +    if ( virq >=3D ESPI_BASE_INTID &&
> +         virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
> +        return true;
> +#endif
> +
>      return virq < vgic_num_irqs(d);
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +/*
> + * Since eSPI indexes start from 4096 and numbers from 1024 to
> + * 4095 are forbidden, we need to check both lower and upper
> + * limits for ranks.
> + */
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int ran=
k)
> +{
> +    return rank >=3D EXT_RANK_MIN &&
> +           EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d);
> +}
> +
> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
> +                                                       unsigned int rank=
)
> +{
> +    return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)]=
;
> +}
> +
> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int=
 virq)
> +{
> +    return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d),
> +                             d->arch.vgic.allocated_irqs);
> +}
> +
> +static void arch_move_espis(struct vcpu *v)

I don't need you need a copy of arch_move_irqs(). Se below for more info.

> +{
> +    const cpumask_t *cpu_mask =3D cpumask_of(v->processor);
> +    struct domain *d =3D v->domain;
> +    struct pending_irq *p;
> +    struct vcpu *v_target;
> +    unsigned int i;
> +
> +    for ( i =3D ESPI_BASE_INTID;
> +          i < EXT_RANK_IDX2NUM(d->arch.vgic.nr_espis); i++ )
> +    {
> +        v_target =3D vgic_get_target_vcpu(v, i);
> +        p =3D irq_to_pending(v_target, i);
> +
> +        if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-=
>status) )
> +            irq_set_affinity(p->desc, cpu_mask);
> +    }
> +}
> +#else
> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int ran=
k)
> +{
> +    return false;
> +}
> +
> +/*
> + * This function is stub and will not be called if CONFIG_GICV3_ESPI=3Dn=
,
> + * because in this case, is_valid_espi_rank will always return false.
> + */
> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
> +                                                       unsigned int rank=
)
> +{
> +    ASSERT_UNREACHABLE();
> +    return NULL;
> +}
> +
> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int=
 virq)
> +{
> +    return false;
> +}
> +
> +static void arch_move_espis(struct vcpu *v) { }
> +#endif
> +
>  static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>                                                    unsigned int rank)
>  {
> @@ -37,6 +110,8 @@ static inline struct vgic_irq_rank *vgic_get_rank(stru=
ct vcpu *v,
>          return v->arch.vgic.private_irqs;
>      else if ( rank <=3D DOMAIN_NR_RANKS(v->domain) )
>          return &v->domain->arch.vgic.shared_irqs[rank - 1];
> +    else if ( is_valid_espi_rank(v->domain, rank) )
> +        return vgic_get_espi_rank(v, rank);
>      else
>          return NULL;
>  }
> @@ -117,6 +192,62 @@ int domain_vgic_register(struct domain *d, unsigned =
int *mmio_count)
>      return 0;
>  }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +static unsigned int vgic_num_spi_lines(struct domain *d)
> +{
> +    return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
> +}
> +
> +static int init_vgic_espi(struct domain *d)
> +{
> +    unsigned int i, idx;
> +
> +    if ( d->arch.vgic.nr_espis =3D=3D 0 )
> +        return 0;
> +
> +    d->arch.vgic.ext_shared_irqs =3D
> +        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
> +    if ( d->arch.vgic.ext_shared_irqs =3D=3D NULL )
> +        return -ENOMEM;
> +
> +    for ( i =3D d->arch.vgic.nr_spis, idx =3D 0;
> +          i < vgic_num_spi_lines(d); i++, idx++ )
> +        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i],
> +                              ESPI_IDX2INTID(idx));
> +
> +    for ( i =3D 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
> +        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
> +
> +    return 0;
> +}
> +
> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)

I know that I should made this observation in previous version, but I
didn't, sorry for that. Anyways, I don't think that this is a good idea
to introduce this function and vgic_reserve_espi_virq(), as well as
arch_move_espis(), actually, because in each case this is a code
duplication, which is not good.

I think that instead you need to introduce a pair of helpers that will
map any (e)SPI number to pending_irq[]/allocate_irqs index and back.

somethink like

static inline unsigned virq_to_index(int virq)
{
   if (is_espi(virq))
       return ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
   return virq;
}

See below for examples.

> +{
> +    irq =3D ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
> +    return &d->arch.vgic.pending_irqs[irq];
> +}
> +#else
> +static unsigned int init_vgic_espi(struct domain *d)
> +{
> +    return 0;
> +}
> +
> +static unsigned int vgic_num_spi_lines(struct domain *d)
> +{
> +    return d->arch.vgic.nr_spis;
> +}
> +
> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
> +{
> +    return NULL;
> +}
> +#endif
> +
> +static unsigned int vgic_num_alloc_irqs(struct domain *d)
> +{
> +    return vgic_num_spi_lines(d) + NR_LOCAL_IRQS;
> +}
> +
>  int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>  {
>      int i;
> @@ -131,6 +262,36 @@ int domain_vgic_init(struct domain *d, unsigned int =
nr_spis)
>       */
>      nr_spis =3D ROUNDUP(nr_spis, 32);
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    /*
> +     * During domain creation, the dom0less DomUs code or toolstack spec=
ifies
> +     * the maximum INTID, which is defined in the domain config subtract=
ed by
> +     * 32 to cover the local IRQs (please see the comment to VGIC_DEF_NR=
_SPIS).
> +     * To compute the actual number of eSPI that will be usable for,
> +     * add back 32.
> +     */
> +    if ( nr_spis + 32 > ESPI_IDX2INTID(NR_ESPI_IRQS) )
> +        return -EINVAL;
> +
> +    if ( nr_spis + 32 >=3D ESPI_BASE_INTID )
> +    {
> +        d->arch.vgic.nr_espis =3D min(nr_spis - ESPI_BASE_INTID + 32, 10=
24U);
> +        /* Verify if GIC HW can handle provided INTID */
> +        if ( d->arch.vgic.nr_espis > gic_number_espis() )
> +            return -EINVAL;
> +        /*
> +         * Set the maximum available number for regular
> +         * SPI to pass the next check
> +         */
> +        nr_spis =3D VGIC_DEF_NR_SPIS;
> +    }
> +    else
> +    {
> +        /* Domain will use the regular SPI range */
> +        d->arch.vgic.nr_espis =3D 0;
> +    }
> +#endif
> +
>      /* Limit the number of virtual SPIs supported to (1020 - 32) =3D 988=
  */
>      if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
>          return -EINVAL;
> @@ -145,7 +306,7 @@ int domain_vgic_init(struct domain *d, unsigned int n=
r_spis)
>          return -ENOMEM;
> =20
>      d->arch.vgic.pending_irqs =3D
> -        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
> +        xzalloc_array(struct pending_irq, vgic_num_spi_lines(d));
>      if ( d->arch.vgic.pending_irqs =3D=3D NULL )
>          return -ENOMEM;
> =20
> @@ -156,12 +317,16 @@ int domain_vgic_init(struct domain *d, unsigned int=
 nr_spis)
>      for ( i =3D 0; i < DOMAIN_NR_RANKS(d); i++ )
>          vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
> =20
> +    ret =3D init_vgic_espi(d);
> +    if ( ret )
> +        return ret;
> +
>      ret =3D d->arch.vgic.handler->domain_init(d);
>      if ( ret )
>          return ret;
> =20
>      d->arch.vgic.allocated_irqs =3D
> -        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
> +        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_alloc_irqs(d=
)));
>      if ( !d->arch.vgic.allocated_irqs )
>          return -ENOMEM;
> =20
> @@ -195,9 +360,27 @@ void domain_vgic_free(struct domain *d)
>          }
>      }
> =20
> +#ifdef CONFIG_GICV3_ESPI
> +    for ( i =3D 0; i < d->arch.vgic.nr_espis; i++ )
> +    {
> +        struct pending_irq *p =3D spi_to_pending(d, ESPI_IDX2INTID(i));
> +
> +        if ( p->desc )
> +        {
> +            ret =3D release_guest_irq(d, p->irq);
> +            if ( ret )
> +                dprintk(XENLOG_G_WARNING, "%pd: Failed to release virq %=
u ret =3D %d\n",
> +                        d, p->irq, ret);
> +        }
> +    }
> +#endif
> +
>      if ( d->arch.vgic.handler )
>          d->arch.vgic.handler->domain_free(d);
>      xfree(d->arch.vgic.shared_irqs);
> +#ifdef CONFIG_GICV3_ESPI
> +    xfree(d->arch.vgic.ext_shared_irqs);
> +#endif
>      xfree(d->arch.vgic.pending_irqs);
>      xfree(d->arch.vgic.allocated_irqs);
>  }
> @@ -331,6 +514,8 @@ void arch_move_irqs(struct vcpu *v)
>          if ( v_target =3D=3D v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p-=
>status) )
>              irq_set_affinity(p->desc, cpu_mask);
>      }
> +
> +    arch_move_espis(v);
>  }
> =20
>  void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
> @@ -538,6 +723,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v, un=
signed int irq)
>          n =3D &v->arch.vgic.pending_irqs[irq];
>      else if ( is_lpi(irq) )
>          n =3D v->domain->arch.vgic.handler->lpi_to_pending(v->domain, ir=
q);
> +    else if ( is_espi(irq) )
> +        n =3D espi_to_pending(v->domain, irq);
>      else
>          n =3D &v->domain->arch.vgic.pending_irqs[irq - 32];
>      return n;
> @@ -547,6 +734,9 @@ struct pending_irq *spi_to_pending(struct domain *d, =
unsigned int irq)
>  {
>      ASSERT(irq >=3D NR_LOCAL_IRQS);
> =20
> +    if ( is_espi(irq) )
> +        return espi_to_pending(d, irq);
> +

here you can just do

idx =3D virq_to_idx(virq);

>      return &d->arch.vgic.pending_irqs[irq - 32];

and

return &d->arch.vgic.pending_irqs[idx];

instead

>  }
> =20
> @@ -668,6 +858,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned int=
 virq)
>      if ( !vgic_is_valid_line(d, virq) )
>          return false;
> =20
> +    if ( is_espi(virq) )
> +        return vgic_reserve_espi_virq(d, virq);
> +

here you can just do

idx =3D virq_to_idx(virq)

>      return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);

and then just

return !test_and_set_bit(idx, d->arch.vgic.allocated_irqs);


>  }
> =20
> @@ -685,7 +878,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
>      else
>      {
>          first =3D 32;
> -        end =3D vgic_num_irqs(d);
> +        end =3D vgic_num_alloc_irqs(d);
>      }

I thinj you need to recalculate "virq" value at the end of this
function. You'll return index in bitfield, but this is not the same is
IRQ number in case of eSPIs. The helpers I mentioned before can help here.

> =20
>      /*

Lastly, I think that it is very wasteful to allocate pending_irqs as
continuous array, because it will consist mostly of unused entries,
especially with eSPIs enable. Probably, better approach will be to use radi=
x
tree. As a bonus, you can use IRQ line number as a key, and get rid of
all these is_espi() checks and mappings between IRQ number and index in
the array.  But this is a much more drastic change, and I don't think that =
it
should be done in this patch series...

--=20
WBR, Volodymyr=


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Date: Fri, 29 Aug 2025 21:58:57 +0100
MIME-Version: 1.0
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Subject: Re: [PATCH] x86/gen-cpuid: correct cycle detection
To: Jan Beulich ,
 "xen-devel@lists.xenproject.org" 
Cc: =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= 
References: <73d725a9-4163-4dd8-a9ac-b1c234005ced@suse.com>
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In-Reply-To: <73d725a9-4163-4dd8-a9ac-b1c234005ced@suse.com>
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On 16/07/2025 7:59 am, Jan Beulich wrote:
> With the processing done linearly (rather than recursively), checking
> whether any of the features was previously seen is wrong: That would
> e.g. trigger for this simple set of dependencies
>
>     X: [A, B]
>     A: [C]
>     B: [C]
>
> (observed in reality when making AMX-AVX512 dependent upon both
> AMX-TILE and AVX512F, causing XSAVE to see AMX-AVX512 twice in its list
> of dependents). But checking the whole accumulated set also isn't
> necessary - just checking the feature we're processing dependents of is
> sufficient. We may detect a cycle later that way, but we still will
> detect it. What we need to avoid is adding a feature again when we've
> already seen it.
>
> As a result, seeding "seen[]" with "feat" isn't necessary anymore.
>
> Fixes: fe4408d180f4 ("xen/x86: Generate deep dependencies of features")
> Signed-off-by: Jan Beulich 
> ---
> Doing AMX-AVX512's dependencies like mentioned above still isn't quite
> right; we really need AVX512F || AVX10, which can't be expressed right
> now.
>
> This contextually collides with patch 2 of "x86/cpu-policy: minor
> adjustments", posted almost 2 years ago and still pending (afair) any
> kind of feedback.
>
> I'd like to note that the commented out code in the loop (sitting
> between the two hunks beklow) doesn't really work for ARCH_CAPS: The
> first unused bit (between XAPIC_STATUS and OVRCLK_STATUS) triggers
>
> Traceback (most recent call last):
>   File ".../xen/../xen/tools/gen-cpuid.py", line 608, in 
>     sys.exit(main())
>   File ".../xen/../xen/tools/gen-cpuid.py", line 602, in main
>     crunch_numbers(state)
>   File ".../xen/../xen/tools/gen-cpuid.py", line 382, in crunch_numbers
>     (state.names[feat], repl(seen)))
>   File ".../xen/../xen/tools/gen-cpuid.py", line 378, in repl
>     return "[" + ", ".join((state.names[x] for x in l)) + "]"
>   File ".../xen/../xen/tools/gen-cpuid.py", line 378, in 
>     return "[" + ", ".join((state.names[x] for x in l)) + "]"
> KeyError: 534
>
> (line numbers slightly shifted due to other debugging code I had added).
> My Python clearly isn't good enough to try to guess how to fix that.

I've posted a fix for this.


>
> --- a/xen/tools/gen-cpuid.py
> +++ b/xen/tools/gen-cpuid.py
> @@ -350,7 +350,7 @@ def crunch_numbers(state):
>  
>      for feat in deep_features:
>  
> -        seen = [feat]
> +        seen = []
>          to_process = list(deps[feat])
>  
>          while len(to_process):
> @@ -363,14 +363,14 @@ def crunch_numbers(state):
>  
>              f = to_process.pop(0)
>  
> -            if f in seen:
> -                raise Fail("ERROR: Cycle found with %s when processing %s"
> -                           % (state.names[f], state.names[feat]))
> +            if f == feat:
> +                raise Fail("ERROR: Cycle found with %s" % (state.names[f], ))

Despite f and feat being the same now, I think this wants to keep the
other part of the sentence.  i.e. "Cycle found when processing %s".

It's a little awkward that there's no sensible way to reverse engineer
the cycle and print it, but it's also been far too long since I last did
graph theory.

>  
> -            seen.append(f)
> -            to_process = list(set(to_process + deps.get(f, [])))
> +            if not (f in seen):
> +                seen.append(f)
> +                to_process = list(set(to_process + deps.get(f, [])))

    if f not in seen:

But this will be a simpler patch if you do:

    if f in seen:
        continue

and don't change the indentation of of seen.append()

After this fix goes in, and now because the order is less relevant, I
probably ought to rewrite this to use sets rather than lists.  I have a
suspicion it can be done better than one-at-a-time; all that matters if
we don't see a repeat feature in deps.  We don't need to check the
feature bits outside of deps because they're (by definition) leaf values.

~Andrew


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Date: Fri, 29 Aug 2025 14:43:18 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: dmukhin@xen.org
cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, 
    dmukhin@ford.com
Subject: Re: [PATCH v5 13/15] x86/domain: enable per-domain I/O port
 bitmaps
In-Reply-To: <20250828235409.2835815-14-dmukhin@ford.com>
Message-ID: 
References: <20250828235409.2835815-1-dmukhin@ford.com> <20250828235409.2835815-14-dmukhin@ford.com>
User-Agent: Alpine 2.22 (DEB 394 2020-01-19)
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Content-Type: text/plain; charset=US-ASCII

On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> From: Denis Mukhin  
> 
> Current design enables all HVM domains share the same I/O port bitmap.
> 
> It is necessary for domains crafting its own I/O port address space depending
> on the user configuration.
> 
> Ensure NS16550 emulator does not share I/O ports with the physical I/O ports,
> which is essential for emulation in PVH hwdom case (dom0).
> 
> Not a functional change.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v4:
> - new patch 
> - Link tp v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-4-dmukhin@ford.com/
> ---
>  xen/arch/x86/Makefile                    |   1 +
>  xen/arch/x86/dom0_build.c                | 111 +--------------
>  xen/arch/x86/hvm/hvm.c                   |  35 +----
>  xen/arch/x86/hvm/nestedhvm.c             |   8 +-
>  xen/arch/x86/hvm/quirks.c                |   3 -
>  xen/arch/x86/hvm/svm/nestedsvm.c         |   2 +-
>  xen/arch/x86/hvm/vmx/vvmx.c              |   4 +-
>  xen/arch/x86/include/asm/hvm/nestedhvm.h |   3 +-
>  xen/arch/x86/include/asm/hvm/support.h   |   2 -
>  xen/arch/x86/include/asm/iocap.h         |   2 +
>  xen/arch/x86/ioport.c                    | 163 +++++++++++++++++++++++
>  xen/arch/x86/pv/dom0_build.c             |   4 +
>  xen/common/emul/vuart/ns16x50.c          |  11 ++
>  13 files changed, 200 insertions(+), 149 deletions(-)
>  create mode 100644 xen/arch/x86/ioport.c
> 
> diff --git a/xen/arch/x86/Makefile b/xen/arch/x86/Makefile
> index 9d67ea7cd4a8..5726ecc180eb 100644
> --- a/xen/arch/x86/Makefile
> +++ b/xen/arch/x86/Makefile
> @@ -44,6 +44,7 @@ obj-y += msi.o
>  obj-y += msr.o
>  obj-$(CONFIG_INDIRECT_THUNK) += indirect-thunk.o
>  obj-$(CONFIG_RETURN_THUNK) += indirect-thunk.o
> +obj-y += ioport.o
>  obj-$(CONFIG_PV) += ioport_emulate.o
>  obj-y += irq.o
>  obj-$(CONFIG_KEXEC) += machine_kexec.o
> diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c
> index 0b467fd4a4fc..26202b33345c 100644
> --- a/xen/arch/x86/dom0_build.c
> +++ b/xen/arch/x86/dom0_build.c
> @@ -298,9 +298,6 @@ int __init parse_arch_dom0_param(const char *s, const char *e)
>      return 0;
>  }
>  
> -static char __initdata opt_dom0_ioports_disable[200] = "";
> -string_param("dom0_ioports_disable", opt_dom0_ioports_disable);
> -
>  static bool __initdata ro_hpet = true;
>  boolean_param("ro-hpet", ro_hpet);
>  
> @@ -433,122 +430,20 @@ unsigned long __init dom0_compute_nr_pages(
>      return nr_pages;
>  }
>  
> -static void __init process_dom0_ioports_disable(struct domain *dom0)
> -{
> -    unsigned long io_from, io_to;
> -    char *t, *s = opt_dom0_ioports_disable;
> -    const char *u;
> -
> -    if ( *s == '\0' )
> -        return;
> -
> -    while ( (t = strsep(&s, ",")) != NULL )
> -    {
> -        io_from = simple_strtoul(t, &u, 16);
> -        if ( u == t )
> -        {
> -        parse_error:
> -            printk("Invalid ioport range <%s> "
> -                   "in dom0_ioports_disable, skipping\n", t);
> -            continue;
> -        }
> -
> -        if ( *u == '\0' )
> -            io_to = io_from;
> -        else if ( *u == '-' )
> -            io_to = simple_strtoul(u + 1, &u, 16);
> -        else
> -            goto parse_error;
> -
> -        if ( (*u != '\0') || (io_to < io_from) || (io_to >= 65536) )
> -            goto parse_error;
> -
> -        printk("Disabling dom0 access to ioport range %04lx-%04lx\n",
> -            io_from, io_to);
> -
> -        if ( ioports_deny_access(dom0, io_from, io_to) != 0 )
> -            BUG();
> -    }
> -}
> -
> +/* Modify I/O memory access permissions. */
>  int __init dom0_setup_permissions(struct domain *d)
>  {
>      unsigned long mfn;
> -    unsigned int i, offs;
> -    int rc;
> +    unsigned int i;
> +    int rc = 0;
>  
>      if ( pv_shim )
>          return 0;
>  
> -    /* The hardware domain is initially permitted full I/O capabilities. */
> -    rc = ioports_permit_access(d, 0, 0xFFFF);
>      rc |= iomem_permit_access(d, 0UL,
>                                PFN_DOWN(1UL << domain_max_paddr_bits(d)) - 1);
>      rc |= irqs_permit_access(d, 1, nr_irqs_gsi - 1);
>  
> -    /* Modify I/O port access permissions. */
> -
> -    for ( offs = 0, i = ISOLATE_LSB(i8259A_alias_mask) ?: 2;
> -          offs <= i8259A_alias_mask; offs += i )
> -    {
> -        if ( offs & ~i8259A_alias_mask )
> -            continue;
> -        /* Master Interrupt Controller (PIC). */
> -        rc |= ioports_deny_access(d, 0x20 + offs, 0x21 + offs);
> -        /* Slave Interrupt Controller (PIC). */
> -        rc |= ioports_deny_access(d, 0xA0 + offs, 0xA1 + offs);
> -    }
> -
> -    /* ELCR of both PICs. */
> -    rc |= ioports_deny_access(d, 0x4D0, 0x4D1);
> -
> -    /* Interval Timer (PIT). */
> -    for ( offs = 0, i = ISOLATE_LSB(pit_alias_mask) ?: 4;
> -          offs <= pit_alias_mask; offs += i )
> -        if ( !(offs & ~pit_alias_mask) )
> -            rc |= ioports_deny_access(d, PIT_CH0 + offs, PIT_MODE + offs);
> -
> -    /* PIT Channel 2 / PC Speaker Control. */
> -    rc |= ioports_deny_access(d, 0x61, 0x61);
> -
> -    /* INIT# and alternative A20M# control. */
> -    rc |= ioports_deny_access(d, 0x92, 0x92);
> -
> -    /* IGNNE# control. */
> -    rc |= ioports_deny_access(d, 0xF0, 0xF0);
> -
> -    /* ACPI PM Timer. */
> -    if ( pmtmr_ioport )
> -        rc |= ioports_deny_access(d, pmtmr_ioport, pmtmr_ioport + 3);
> -
> -    /* Reset control. */
> -    rc |= ioports_deny_access(d, 0xCF9, 0xCF9);
> -
> -    /* PCI configuration space (NB. 0xCF8 has special treatment). */
> -    rc |= ioports_deny_access(d, 0xCFC, 0xCFF);
> -
> -#ifdef CONFIG_HVM
> -    if ( is_hvm_domain(d) )
> -    {
> -        /* ISA DMA controller, channels 0-3 (incl possible aliases). */
> -        rc |= ioports_deny_access(d, 0x00, 0x1F);
> -        /* ISA DMA controller, page registers (incl various reserved ones). */
> -        rc |= ioports_deny_access(d, 0x80 + !!hvm_port80_allowed, 0x8F);
> -        /* ISA DMA controller, channels 4-7 (incl usual aliases). */
> -        rc |= ioports_deny_access(d, 0xC0, 0xDF);
> -
> -        /* HVM debug console IO port. */
> -        rc |= ioports_deny_access(d, XEN_HVM_DEBUGCONS_IOPORT,
> -                                  XEN_HVM_DEBUGCONS_IOPORT);
> -        if ( amd_acpi_c1e_quirk )
> -            rc |= ioports_deny_access(d, acpi_smi_cmd, acpi_smi_cmd);
> -    }
> -#endif
> -    /* Command-line I/O ranges. */
> -    process_dom0_ioports_disable(d);
> -
> -    /* Modify I/O memory access permissions. */
> -
>      /* Local APIC. */
>      if ( mp_lapic_addr != 0 )
>      {
> diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
> index 26760cf995df..12736fc61c11 100644
> --- a/xen/arch/x86/hvm/hvm.c
> +++ b/xen/arch/x86/hvm/hvm.c
> @@ -51,6 +51,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -81,14 +82,6 @@ integer_param("hvm_debug", opt_hvm_debug_level);
>  
>  struct hvm_function_table __ro_after_init hvm_funcs;
>  
> -/*
> - * The I/O permission bitmap is globally shared by all HVM guests except
> - * the hardware domain which needs a more permissive one.
> - */
> -#define HVM_IOBITMAP_SIZE (3 * PAGE_SIZE)
> -unsigned long __section(".bss.page_aligned") __aligned(PAGE_SIZE)
> -    hvm_io_bitmap[HVM_IOBITMAP_SIZE / BYTES_PER_LONG];
> -
>  /* Xen command-line option to enable HAP */
>  static bool __initdata opt_hap_enabled = true;
>  boolean_param("hap", opt_hap_enabled);
> @@ -205,15 +198,6 @@ static int __init cf_check hvm_enable(void)
>      if ( opt_hvm_fep )
>          warning_add(warning_hvm_fep);
>  
> -    /*
> -     * Allow direct access to the PC debug ports 0x80 and 0xed (they are
> -     * often used for I/O delays, but the vmexits simply slow things down).
> -     */
> -    memset(hvm_io_bitmap, ~0, sizeof(hvm_io_bitmap));
> -    if ( hvm_port80_allowed )
> -        __clear_bit(0x80, hvm_io_bitmap);
> -    __clear_bit(0xed, hvm_io_bitmap);
> -
>      register_cpu_notifier(&cpu_nfb);
>  
>      return 0;
> @@ -645,19 +629,12 @@ int hvm_domain_initialise(struct domain *d,
>  
>      rwlock_init(&d->arch.hvm.pl_time->pt_migrate);
>  
> -    /* Set the default IO Bitmap. */
> -    if ( is_hardware_domain(d) )
> +    rc = ioports_setup_access(d);
> +    if ( rc )
>      {
> -        d->arch.hvm.io_bitmap = _xmalloc(HVM_IOBITMAP_SIZE, PAGE_SIZE);
> -        if ( d->arch.hvm.io_bitmap == NULL )
> -        {
> -            rc = -ENOMEM;
> -            goto fail1;
> -        }
> -        memset(d->arch.hvm.io_bitmap, ~0, HVM_IOBITMAP_SIZE);
> +        printk("%pd failed to setup I/O bitmap: %d\n", d, rc);
> +        goto fail1;
>      }
> -    else
> -        d->arch.hvm.io_bitmap = hvm_io_bitmap;
>  
>      register_g2m_portio_handler(d);
>      register_vpci_portio_handler(d);
> @@ -684,6 +661,8 @@ int hvm_domain_initialise(struct domain *d,
>          break;
>      }
>  
> +    BUG_ON(!d->arch.ioport_caps);
> +
>      vpic_init(d);
>  
>      rc = vioapic_init(d);
> diff --git a/xen/arch/x86/hvm/nestedhvm.c b/xen/arch/x86/hvm/nestedhvm.c
> index bddd77d8109b..d4e03123d910 100644
> --- a/xen/arch/x86/hvm/nestedhvm.c
> +++ b/xen/arch/x86/hvm/nestedhvm.c
> @@ -107,7 +107,7 @@ nestedhvm_vmcx_flushtlb(struct p2m_domain *p2m)
>   * The users of the bitmap patterns are in SVM/VMX specific code.
>   *
>   * bitmap        port 0x80  port 0xed
> - * hvm_io_bitmap cleared    cleared
> + * hvm.io_bitmap cleared    cleared
>   * iomap[0]      cleared    set
>   * iomap[1]      set        cleared
>   * iomap[2]      set        set
> @@ -115,7 +115,7 @@ nestedhvm_vmcx_flushtlb(struct p2m_domain *p2m)
>  
>  static int __init cf_check nestedhvm_setup(void)
>  {
> -    /* Same format and size as hvm_io_bitmap (Intel needs only 2 pages). */
> +    /* Same format and size as hvm.io_bitmap (Intel needs only 2 pages). */
>      unsigned nr = cpu_has_vmx ? 2 : 3;
>      unsigned int i, order = get_order_from_pages(nr);
>  
> @@ -165,7 +165,7 @@ static int __init cf_check nestedhvm_setup(void)
>  __initcall(nestedhvm_setup);
>  
>  unsigned long *
> -nestedhvm_vcpu_iomap_get(bool ioport_80, bool ioport_ed)
> +nestedhvm_vcpu_iomap_get(struct vcpu *v, bool ioport_80, bool ioport_ed)
>  {
>      int i;
>  
> @@ -174,7 +174,7 @@ nestedhvm_vcpu_iomap_get(bool ioport_80, bool ioport_ed)
>  
>      if (ioport_80 == 0) {
>          if (ioport_ed == 0)
> -            return hvm_io_bitmap;
> +            return v->domain->arch.hvm.io_bitmap;
>          i = 0;
>      } else {
>          if (ioport_ed == 0)
> diff --git a/xen/arch/x86/hvm/quirks.c b/xen/arch/x86/hvm/quirks.c
> index 9202f5a47fe9..f4d95441fcff 100644
> --- a/xen/arch/x86/hvm/quirks.c
> +++ b/xen/arch/x86/hvm/quirks.c
> @@ -73,9 +73,6 @@ static int __init cf_check check_port80(void)
>  
>      dmi_check_system(hvm_no_port80_dmi_table);
>  
> -    if ( !hvm_port80_allowed )
> -        __set_bit(0x80, hvm_io_bitmap);
> -
>      return 0;
>  }
>  __initcall(check_port80);
> diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nestedsvm.c
> index dc2b6a42534a..cc8500b61665 100644
> --- a/xen/arch/x86/hvm/svm/nestedsvm.c
> +++ b/xen/arch/x86/hvm/svm/nestedsvm.c
> @@ -381,7 +381,7 @@ static int nsvm_vmrun_permissionmap(struct vcpu *v, bool viopm)
>          hvm_unmap_guest_frame(ns_viomap, 0);
>      }
>  
> -    svm->ns_iomap = nestedhvm_vcpu_iomap_get(ioport_80, ioport_ed);
> +    svm->ns_iomap = nestedhvm_vcpu_iomap_get(v, ioport_80, ioport_ed);
>  
>      nv->nv_ioport80 = ioport_80;
>      nv->nv_ioportED = ioport_ed;
> diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
> index e4f3a5fe4c71..4da3e6e90e6c 100644
> --- a/xen/arch/x86/hvm/vmx/vvmx.c
> +++ b/xen/arch/x86/hvm/vmx/vvmx.c
> @@ -554,7 +554,7 @@ unsigned long *_shadow_io_bitmap(struct vcpu *v)
>      port80 = bitmap[0x80 >> 3] & (1 << (0x80 & 0x7)) ? 1 : 0;
>      portED = bitmap[0xed >> 3] & (1 << (0xed & 0x7)) ? 1 : 0;
>  
> -    return nestedhvm_vcpu_iomap_get(port80, portED);
> +    return nestedhvm_vcpu_iomap_get(v, port80, portED);
>  }
>  
>  static void update_msrbitmap(struct vcpu *v, uint32_t shadow_ctrl)
> @@ -622,7 +622,7 @@ void nvmx_update_exec_control(struct vcpu *v, u32 host_cntrl)
>               * L1 VMM doesn't intercept IO instruction.
>               * Use host configuration and reset IO_BITMAP
>               */
> -            bitmap = hvm_io_bitmap;
> +            bitmap = v->domain->arch.hvm.io_bitmap;
>          }
>          else {
>              /* use IO bitmap */
> diff --git a/xen/arch/x86/include/asm/hvm/nestedhvm.h b/xen/arch/x86/include/asm/hvm/nestedhvm.h
> index ea2c1bc328c7..d691ccb07dd6 100644
> --- a/xen/arch/x86/include/asm/hvm/nestedhvm.h
> +++ b/xen/arch/x86/include/asm/hvm/nestedhvm.h
> @@ -50,7 +50,8 @@ int nestedhvm_hap_nested_page_fault(struct vcpu *v, paddr_t *L2_gpa,
>                                      struct npfec npfec);
>  
>  /* IO permission map */
> -unsigned long *nestedhvm_vcpu_iomap_get(bool ioport_80, bool ioport_ed);
> +unsigned long *nestedhvm_vcpu_iomap_get(struct vcpu *v,
> +                                        bool ioport_80, bool ioport_ed);
>  
>  /* Misc */
>  #define nestedhvm_paging_mode_hap(v) (!!nhvm_vmcx_hap_enabled(v))
> diff --git a/xen/arch/x86/include/asm/hvm/support.h b/xen/arch/x86/include/asm/hvm/support.h
> index 2a7ba36af06f..7e36d00cc188 100644
> --- a/xen/arch/x86/include/asm/hvm/support.h
> +++ b/xen/arch/x86/include/asm/hvm/support.h
> @@ -41,8 +41,6 @@ extern unsigned int opt_hvm_debug_level;
>  #define HVM_DBG_LOG(level, _f, _a...) do {} while (0)
>  #endif
>  
> -extern unsigned long hvm_io_bitmap[];
> -
>  enum hvm_translation_result {
>      HVMTRANS_okay,
>      HVMTRANS_bad_linear_to_gfn,
> diff --git a/xen/arch/x86/include/asm/iocap.h b/xen/arch/x86/include/asm/iocap.h
> index f948b7186e95..1083f6171cf7 100644
> --- a/xen/arch/x86/include/asm/iocap.h
> +++ b/xen/arch/x86/include/asm/iocap.h
> @@ -22,6 +22,8 @@
>  #define cache_flush_permitted(d) \
>      (has_arch_io_resources(d) || has_arch_pdevs(d))
>  
> +int ioports_setup_access(struct domain *d);
> +
>  static inline int ioports_permit_access(struct domain *d, unsigned long s,
>                                          unsigned long e)
>  {
> diff --git a/xen/arch/x86/ioport.c b/xen/arch/x86/ioport.c
> new file mode 100644
> index 000000000000..dbcd52d37a4f
> --- /dev/null
> +++ b/xen/arch/x86/ioport.c
> @@ -0,0 +1,163 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Guest I/O port address space configuration.
> + *
> + * Copyright 2025 Ford Motor Company
> + */
> +
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +static char __initdata opt_dom0_ioports_disable[200] = "";
> +string_param("dom0_ioports_disable", opt_dom0_ioports_disable);
> +
> +/*
> + * The I/O permission bitmap size.
> + * See: comment in nestedhvm_setup()
> + */
> +#define HVM_IOBITMAP_SIZE (3 * PAGE_SIZE)
> +
> +/* Hide user-defined I/O ports from the guest OS. */
> +static void process_dom0_ioports_disable(struct domain *dom0)
> +{
> +    unsigned long io_from, io_to;
> +    char *t, *s = opt_dom0_ioports_disable;
> +    const char *u;
> +
> +    if ( *s == '\0' )
> +        return;
> +
> +    while ( (t = strsep(&s, ",")) != NULL )
> +    {
> +        io_from = simple_strtoul(t, &u, 16);
> +        if ( u == t )
> +        {
> +        parse_error:
> +            printk("Invalid ioport range <%s> "
> +                   "in dom0_ioports_disable, skipping\n", t);
> +            continue;
> +        }
> +
> +        if ( *u == '\0' )
> +            io_to = io_from;
> +        else if ( *u == '-' )
> +            io_to = simple_strtoul(u + 1, &u, 16);
> +        else
> +            goto parse_error;
> +
> +        if ( (*u != '\0') || (io_to < io_from) || (io_to >= 65536) )
> +            goto parse_error;
> +
> +        printk("Disabling dom0 access to ioport range %04lx-%04lx\n",
> +            io_from, io_to);
> +
> +        if ( ioports_deny_access(dom0, io_from, io_to) != 0 )
> +            BUG();
> +    }
> +}
> +
> +/* Set the default IO Bitmap. */
> +int ioports_setup_access(struct domain *d)
> +{
> +    unsigned int i, offs;
> +    int rc;
> +
> +    if ( pv_shim )
> +        return 0;
> +
> +#ifdef CONFIG_HVM
> +    d->arch.hvm.io_bitmap = _xmalloc(HVM_IOBITMAP_SIZE, PAGE_SIZE);
> +    if ( d->arch.hvm.io_bitmap == NULL )
> +        return -ENOMEM;
> +
> +    memset(d->arch.hvm.io_bitmap, ~0, HVM_IOBITMAP_SIZE);
> +
> +    if ( !is_hardware_domain(d) )
> +    {
> +        /*
> +         * Allow direct access to the PC debug ports 0x80 and 0xed (they are
> +         * often used for I/O delays, but the vmexits simply slow things down).
> +         */
> +        if ( hvm_port80_allowed )
> +            __clear_bit(0x80, d->arch.hvm.io_bitmap);
> +
> +        __clear_bit(0xed, d->arch.hvm.io_bitmap);
> +
> +        return 0;
> +    }
> +#endif
> +
> +    /* The hardware domain is initially permitted full I/O capabilities. */
> +    rc = ioports_permit_access(d, 0, 0xFFFF);
> +
> +    /* Modify I/O port access permissions. */
> +
> +    for ( offs = 0, i = ISOLATE_LSB(i8259A_alias_mask) ?: 2;
> +          offs <= i8259A_alias_mask; offs += i )
> +    {
> +        if ( offs & ~i8259A_alias_mask )
> +            continue;
> +        /* Master Interrupt Controller (PIC). */
> +        rc |= ioports_deny_access(d, 0x20 + offs, 0x21 + offs);
> +        /* Slave Interrupt Controller (PIC). */
> +        rc |= ioports_deny_access(d, 0xA0 + offs, 0xA1 + offs);
> +    }
> +
> +    /* ELCR of both PICs. */
> +    rc |= ioports_deny_access(d, 0x4D0, 0x4D1);
> +
> +    /* Interval Timer (PIT). */
> +    for ( offs = 0, i = ISOLATE_LSB(pit_alias_mask) ?: 4;
> +          offs <= pit_alias_mask; offs += i )
> +        if ( !(offs & ~pit_alias_mask) )
> +            rc |= ioports_deny_access(d, PIT_CH0 + offs, PIT_MODE + offs);
> +
> +    /* PIT Channel 2 / PC Speaker Control. */
> +    rc |= ioports_deny_access(d, 0x61, 0x61);
> +
> +    /* INIT# and alternative A20M# control. */
> +    rc |= ioports_deny_access(d, 0x92, 0x92);
> +
> +    /* IGNNE# control. */
> +    rc |= ioports_deny_access(d, 0xF0, 0xF0);
> +
> +    /* ACPI PM Timer. */
> +    if ( pmtmr_ioport )
> +        rc |= ioports_deny_access(d, pmtmr_ioport, pmtmr_ioport + 3);
> +
> +    /* Reset control. */
> +    rc |= ioports_deny_access(d, 0xCF9, 0xCF9);
> +
> +    /* PCI configuration space (NB. 0xCF8 has special treatment). */
> +    rc |= ioports_deny_access(d, 0xCFC, 0xCFF);
> +
> +#ifdef CONFIG_HVM
> +    if ( is_hvm_domain(d) )
> +    {
> +        /* ISA DMA controller, channels 0-3 (incl possible aliases). */
> +        rc |= ioports_deny_access(d, 0x00, 0x1F);
> +        /* ISA DMA controller, page registers (incl various reserved ones). */
> +        rc |= ioports_deny_access(d, 0x80 + !!hvm_port80_allowed, 0x8F);
> +        /* ISA DMA controller, channels 4-7 (incl usual aliases). */
> +        rc |= ioports_deny_access(d, 0xC0, 0xDF);
> +
> +        /* HVM debug console IO port. */
> +        rc |= ioports_deny_access(d, XEN_HVM_DEBUGCONS_IOPORT,
> +                                  XEN_HVM_DEBUGCONS_IOPORT);
> +        if ( amd_acpi_c1e_quirk )
> +            rc |= ioports_deny_access(d, acpi_smi_cmd, acpi_smi_cmd);
> +    }
> +#endif
> +
> +    /* Command-line I/O ranges. */
> +    process_dom0_ioports_disable(d);
> +
> +    return rc;
> +}
> diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c
> index 21158ce1812e..2b8b4d869ee7 100644
> --- a/xen/arch/x86/pv/dom0_build.c
> +++ b/xen/arch/x86/pv/dom0_build.c
> @@ -17,6 +17,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -1033,6 +1034,9 @@ static int __init dom0_construct(const struct boot_domain *bd)
>      if ( test_bit(XENFEAT_supervisor_mode_kernel, parms.f_required) )
>          panic("Dom0 requires supervisor-mode execution\n");
>  
> +    rc = ioports_setup_access(d);
> +    BUG_ON(rc != 0);
> +
>      rc = dom0_setup_permissions(d);
>      BUG_ON(rc != 0);
>  
> diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> index 5c1be854b544..8860f25ffdeb 100644
> --- a/xen/common/emul/vuart/ns16x50.c
> +++ b/xen/common/emul/vuart/ns16x50.c
> @@ -780,9 +780,20 @@ static int ns16x50_init(void *arg)
>      struct vuart_ns16x50 *vdev = arg;
>      const struct vuart_info *info = vdev->info;
>      struct domain *d = vdev->owner;
> +    int rc;
>  
>      ASSERT(vdev);
>  
> +    /* Disallow sharing physical I/O port */
> +    rc = ioports_deny_access(d, info->base_addr,
> +                             info->base_addr + info->size - 1);

I would be tempted to move ioports_deny_access to hvm_domain_initialise
before vuart_init


> +    if ( rc )
> +    {
> +        ns16x50_err(info, " virtual I/O port range [0x%04lx"PRIx64"..0x%04lx"PRIx64"]: conflict w/ physical range\n",
> +                    info->base_addr, info->base_addr + info->size - 1);

0x%04lx"PRIx64 seems wrong


> +        return rc;
> +    }
> +
>      /* NB: report 115200 baud rate. */
>      vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & 0xff;
>      vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
> -- 
> 2.51.0
> 


From xen-devel-bounces@lists.xenproject.org Fri Aug 29 21:46:39 2025
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Date: Fri, 29 Aug 2025 14:46:29 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: dmukhin@xen.org
cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, 
    dmukhin@ford.com
Subject: Re: [PATCH v5 14/15] xen/domain: allocate d->irq_caps before
 arch-specific initialization
In-Reply-To: <20250828235409.2835815-15-dmukhin@ford.com>
Message-ID: 
References: <20250828235409.2835815-1-dmukhin@ford.com> <20250828235409.2835815-15-dmukhin@ford.com>
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On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> From: Denis Mukhin  
> 
> Make sure that NS16550 emulator does not share virtual device IRQ with the
> physical one. This is needed for enabling NS16550 emulator for PVH hwdom
> (dom0).
> 
> To do that, move per-domain interrupt rangeset allocation before arch-specific
> code. Add irqs_setup_access() to setup the initial rangeset.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v4:
> - new patch
> - Link to original patch in v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-4-dmukhin@ford.com/
> ---
>  xen/arch/x86/dom0_build.c       | 1 -
>  xen/arch/x86/hvm/dom0_build.c   | 7 +++++++
>  xen/arch/x86/include/asm/irq.h  | 2 ++
>  xen/arch/x86/irq.c              | 8 ++++++++
>  xen/arch/x86/pv/dom0_build.c    | 3 +++
>  xen/common/domain.c             | 8 ++++++--
>  xen/common/emul/vuart/ns16x50.c | 9 +++++++++
>  7 files changed, 35 insertions(+), 3 deletions(-)
> 
> diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c
> index 26202b33345c..9dc87efbf3e8 100644
> --- a/xen/arch/x86/dom0_build.c
> +++ b/xen/arch/x86/dom0_build.c
> @@ -442,7 +442,6 @@ int __init dom0_setup_permissions(struct domain *d)
>  
>      rc |= iomem_permit_access(d, 0UL,
>                                PFN_DOWN(1UL << domain_max_paddr_bits(d)) - 1);
> -    rc |= irqs_permit_access(d, 1, nr_irqs_gsi - 1);
>  
>      /* Local APIC. */
>      if ( mp_lapic_addr != 0 )
> diff --git a/xen/arch/x86/hvm/dom0_build.c b/xen/arch/x86/hvm/dom0_build.c
> index 5551f9044836..245a42dec9aa 100644
> --- a/xen/arch/x86/hvm/dom0_build.c
> +++ b/xen/arch/x86/hvm/dom0_build.c
> @@ -1348,6 +1348,13 @@ int __init dom0_construct_pvh(const struct boot_domain *bd)
>           */
>          pvh_setup_mmcfg(d);
>  
> +        rc = irqs_setup_access(d);
> +        if ( rc )
> +        {
> +            printk("%pd unable to setup IRQ rangeset: %d\n", d, rc);
> +            return rc;
> +        }
> +
>          /*
>           * Setup permissions early so that calls to add MMIO regions to the
>           * p2m as part of vPCI setup don't fail due to permission checks.
> diff --git a/xen/arch/x86/include/asm/irq.h b/xen/arch/x86/include/asm/irq.h
> index 8c81f66434a8..8bffec3bbfee 100644
> --- a/xen/arch/x86/include/asm/irq.h
> +++ b/xen/arch/x86/include/asm/irq.h
> @@ -231,4 +231,6 @@ int allocate_and_map_gsi_pirq(struct domain *d, int index, int *pirq_p);
>  int allocate_and_map_msi_pirq(struct domain *d, int index, int *pirq_p,
>                                int type, struct msi_info *msi);
>  
> +int irqs_setup_access(struct domain *d);
> +
>  #endif /* _ASM_HW_IRQ_H */
> diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c
> index 556134f85aa0..079277be719d 100644
> --- a/xen/arch/x86/irq.c
> +++ b/xen/arch/x86/irq.c
> @@ -3046,3 +3046,11 @@ int allocate_and_map_msi_pirq(struct domain *d, int index, int *pirq_p,
>  
>      return ret;
>  }
> +
> +int irqs_setup_access(struct domain *d)
> +{
> +    if ( is_hardware_domain(d) )
> +        return irqs_permit_access(d, 1, nr_irqs_gsi - 1);
> +
> +    return 0;
> +}
> diff --git a/xen/arch/x86/pv/dom0_build.c b/xen/arch/x86/pv/dom0_build.c
> index 2b8b4d869ee7..1a092b802833 100644
> --- a/xen/arch/x86/pv/dom0_build.c
> +++ b/xen/arch/x86/pv/dom0_build.c
> @@ -1037,6 +1037,9 @@ static int __init dom0_construct(const struct boot_domain *bd)
>      rc = ioports_setup_access(d);
>      BUG_ON(rc != 0);
>  
> +    rc = irqs_setup_access(d);
> +    BUG_ON(rc != 0);
> +
>      rc = dom0_setup_permissions(d);
>      BUG_ON(rc != 0);
>  
> diff --git a/xen/common/domain.c b/xen/common/domain.c
> index 104e917f07e3..eb83e3198f37 100644
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -950,6 +950,11 @@ struct domain *domain_create(domid_t domid,
>      radix_tree_init(&d->pirq_tree);
>  #endif
>  
> +    err = -ENOMEM;
> +    d->irq_caps = rangeset_new(d, "Interrupts", 0);
> +    if ( !d->irq_caps )
> +        goto fail;
> +
>      if ( (err = arch_domain_create(d, config, flags)) != 0 )
>          goto fail;
>      init_status |= INIT_arch;
> @@ -959,8 +964,7 @@ struct domain *domain_create(domid_t domid,
>  
>      err = -ENOMEM;
>      d->iomem_caps = rangeset_new(d, "I/O Memory", RANGESETF_prettyprint_hex);
> -    d->irq_caps   = rangeset_new(d, "Interrupts", 0);
> -    if ( !d->iomem_caps || !d->irq_caps )
> +    if ( !d->iomem_caps )
>          goto fail;
>  
>      if ( (err = xsm_domain_create(XSM_HOOK, d, config->ssidref)) != 0 )
> diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> index 8860f25ffdeb..aea38304b60c 100644
> --- a/xen/common/emul/vuart/ns16x50.c
> +++ b/xen/common/emul/vuart/ns16x50.c
> @@ -794,6 +794,15 @@ static int ns16x50_init(void *arg)
>          return rc;
>      }
>  
> +    /* Disallow sharing physical IRQ */
> +    rc = irq_deny_access(d, info->irq);
> +    if ( rc )
> +    {
> +        ns16x50_err(info, "virtual IRQ#%d: conflict w/ physical IRQ: %d\n",
> +                    info->irq, rc);
> +        return rc;
> +    }

Also this one I wonder if it could be in hvm_domain_initialise, it would
make more sense to keep the irq_deny_access there, compared to here
which is supposed to be a generic emulator


>      /* NB: report 115200 baud rate. */
>      vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & 0xff;
>      vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
> -- 
> 2.51.0
> 


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Date: Fri, 29 Aug 2025 15:06:27 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: dmkhn@proton.me
cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, 
    dmukhin@ford.com
Subject: Re: [PATCH v11] xen/console: introduce domain_console struct
In-Reply-To: <20250807005649.551704-1-dmukhin@ford.com>
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References: <20250807005649.551704-1-dmukhin@ford.com>
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On Thu, 7 Aug 2025, dmkhn@proton.me wrote:
> From: Denis Mukhin  
> 
> Introduce domain_console for grouping data structures used for integrating
> domain's diagnostic console with Xen's console driver.
> 
> Group all pbuf-related data structures under domain_console. Rename the moved
> fields to plain .buf, .idx and .lock names, since all uses of the fields are
> touched.
> 
> Ensure accesses to domain_console pointer are valid in console_switch_input().
> 
> Bump the domain console buffer allocation size to 256. No extra symbol for the
> value since it is used only once during data structure declaration. All size
> checks use ARRAY_SIZE().
> 
> Allocate domain_console from the heap so that the parent domain struct size
> stays below PAGE_SIZE boundary to account for more console-related fields
> added in the future.
> 
> Finally, update the domain_console allocation and initialization code. Make
> sure domain_console is not allocated for system domains.
> 
> No functional change.
> 
> Signed-off-by: Denis Mukhin 

Reviewed-by: Stefano Stabellini 


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Date: Fri, 29 Aug 2025 15:21:13 -0700 (PDT)
From: Stefano Stabellini 
X-X-Sender: sstabellini@ubuntu-linux-20-04-desktop
To: dmukhin@xen.org
cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com, 
    anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org, 
    michal.orzel@amd.com, roger.pau@citrix.com, sstabellini@kernel.org, 
    dmukhin@ford.com
Subject: Re: [PATCH v5 15/15] emul/ns16x50: implement IRQ emulation via
 vIOAPIC
In-Reply-To: <20250828235409.2835815-16-dmukhin@ford.com>
Message-ID: 
References: <20250828235409.2835815-1-dmukhin@ford.com> <20250828235409.2835815-16-dmukhin@ford.com>
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On Thu, 28 Aug 2025, dmukhin@xen.org wrote:
> From: Denis Mukhin  
> 
> PVH domains use vIOAPIC, not vPIC and NS16550 emulates ISA IRQs which cannot
> be asserted on vIOAPIC.

One option is to enable the vPIT for PVH domains when the NS16550
emulator is enabled. Would that resolve the problem? That would be a
simpler solution compared to adding IRQ_EMU because the IRQ_* logic is
already quite complex.

Alternatively...


> {map,unmap}_domain_emuirq_pirq() infrastructure is modified by adding new
> type of interrupt resources 'IRQ_EMU' which means 'emulated device IRQ'
> (similarly to IRQ_MSI_EMU).
> 
> This is necessary to for IOAPIC emulation code to skip IRQ->PIRQ mapping
> (vioapic_hwdom_map_gsi()) when guest OS unmasks vIOAPIC pin corresponding to
> virtual device's IRQ.
> 
> Also, hvm_gsi_eoi() is modified to trigger assertion in hvm_gsi_deassert()
> path for ISA IRQs.
> 
> Signed-off-by: Denis Mukhin 
> ---
> Changes since v4:
> - dropped xl bits
> - cosmetic renames
> - fix hvm_gsi_eoi()
> - Link to v4: https://lore.kernel.org/xen-devel/20250731192130.3948419-8-dmukhin@ford.com/
> ---
>  xen/arch/x86/domain.c             |  2 +-
>  xen/arch/x86/hvm/vioapic.c        | 10 ++++++++++
>  xen/arch/x86/include/asm/irq.h    |  3 ++-
>  xen/arch/x86/irq.c                |  4 ++--
>  xen/arch/x86/physdev.c            |  8 ++++----
>  xen/common/emul/vuart/ns16x50.c   | 32 +++++++++++++++++++++++++++++--
>  xen/drivers/passthrough/x86/hvm.c | 13 ++++++++-----
>  7 files changed, 57 insertions(+), 15 deletions(-)
> 
> diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
> index 19fd86ce88d2..0815d0b31827 100644
> --- a/xen/arch/x86/domain.c
> +++ b/xen/arch/x86/domain.c
> @@ -1048,7 +1048,7 @@ int arch_domain_soft_reset(struct domain *d)
>      write_lock(&d->event_lock);
>      for ( i = 0; i < d->nr_pirqs ; i++ )
>      {
> -        if ( domain_pirq_to_emuirq(d, i) != IRQ_UNBOUND )
> +        if ( domain_irq_to_emuirq(d, i) != IRQ_UNBOUND )
>          {
>              ret = unmap_domain_pirq_emuirq(d, i);
>              if ( ret )
> diff --git a/xen/arch/x86/hvm/vioapic.c b/xen/arch/x86/hvm/vioapic.c
> index 7c725f9e471f..fd073f6fba4b 100644
> --- a/xen/arch/x86/hvm/vioapic.c
> +++ b/xen/arch/x86/hvm/vioapic.c
> @@ -177,6 +177,16 @@ static int vioapic_hwdom_map_gsi(unsigned int gsi, unsigned int trig,
>  
>      ASSERT(is_hardware_domain(currd));
>  
> +    /*
> +     * Interrupt is claimed by one of the platform virtual devices (e.g.
> +     * NS16550); do nothing.
> +     */
> +    write_lock(&currd->event_lock);
> +    ret = domain_irq_to_emuirq(currd, gsi);
> +    write_unlock(&currd->event_lock);
> +    if ( ret != IRQ_UNBOUND )
> +        return 0;

..alternatively, we could have an add-hoc check here? Not very nice but
at least it would be very simple.

In other words, adding vPIT is preferable in my opinion but as a second
option I would consider an ad-hoc check. I would try to avoid adding
IRQ_EMU -- that should be the last resort in my view.


>      /* Interrupt has been unmasked, bind it now. */
>      ret = mp_register_gsi(gsi, trig, pol);
>      if ( ret == -EEXIST )
> diff --git a/xen/arch/x86/include/asm/irq.h b/xen/arch/x86/include/asm/irq.h
> index 8bffec3bbfee..3b24decb05e4 100644
> --- a/xen/arch/x86/include/asm/irq.h
> +++ b/xen/arch/x86/include/asm/irq.h
> @@ -212,7 +212,7 @@ void cleanup_domain_irq_mapping(struct domain *d);
>      __ret ? radix_tree_ptr_to_int(__ret) : 0;                   \
>  })
>  #define PIRQ_ALLOCATED (-1)
> -#define domain_pirq_to_emuirq(d, pirq) pirq_field(d, pirq,              \
> +#define domain_irq_to_emuirq(d, pirq) pirq_field(d, pirq,              \
>      arch.hvm.emuirq, IRQ_UNBOUND)
>  #define domain_emuirq_to_pirq(d, emuirq) ({                             \
>      void *__ret = radix_tree_lookup(&(d)->arch.hvm.emuirq_pirq, emuirq);\
> @@ -221,6 +221,7 @@ void cleanup_domain_irq_mapping(struct domain *d);
>  #define IRQ_UNBOUND (-1)
>  #define IRQ_PT      (-2)
>  #define IRQ_MSI_EMU (-3)
> +#define IRQ_EMU     (-4)
>  
>  bool cpu_has_pending_apic_eoi(void);
>  
> diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c
> index 079277be719d..7a8093cd3238 100644
> --- a/xen/arch/x86/irq.c
> +++ b/xen/arch/x86/irq.c
> @@ -2790,7 +2790,7 @@ int map_domain_emuirq_pirq(struct domain *d, int pirq, int emuirq)
>          return -EINVAL;
>      }
>  
> -    old_emuirq = domain_pirq_to_emuirq(d, pirq);
> +    old_emuirq = domain_irq_to_emuirq(d, pirq);
>      if ( emuirq != IRQ_PT )
>          old_pirq = domain_emuirq_to_pirq(d, emuirq);
>  
> @@ -2845,7 +2845,7 @@ int unmap_domain_pirq_emuirq(struct domain *d, int pirq)
>  
>      ASSERT(rw_is_write_locked(&d->event_lock));
>  
> -    emuirq = domain_pirq_to_emuirq(d, pirq);
> +    emuirq = domain_irq_to_emuirq(d, pirq);
>      if ( emuirq == IRQ_UNBOUND )
>      {
>          dprintk(XENLOG_G_ERR, "dom%d: pirq %d not mapped\n",
> diff --git a/xen/arch/x86/physdev.c b/xen/arch/x86/physdev.c
> index 4dfa1c019105..90a9e7d2f120 100644
> --- a/xen/arch/x86/physdev.c
> +++ b/xen/arch/x86/physdev.c
> @@ -145,7 +145,7 @@ int physdev_unmap_pirq(struct domain *d, int pirq)
>      if ( is_hvm_domain(d) && has_pirq(d) )
>      {
>          write_lock(&d->event_lock);
> -        if ( domain_pirq_to_emuirq(d, pirq) != IRQ_UNBOUND )
> +        if ( domain_irq_to_emuirq(d, pirq) != IRQ_UNBOUND )
>              ret = unmap_domain_pirq_emuirq(d, pirq);
>          write_unlock(&d->event_lock);
>          if ( d == current->domain || ret )
> @@ -191,10 +191,10 @@ ret_t do_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
>          if ( is_pv_domain(currd) || domain_pirq_to_irq(currd, eoi.irq) > 0 )
>              pirq_guest_eoi(pirq);
>          if ( is_hvm_domain(currd) &&
> -             domain_pirq_to_emuirq(currd, eoi.irq) > 0 )
> +             domain_irq_to_emuirq(currd, eoi.irq) > 0 )
>          {
>              struct hvm_irq *hvm_irq = hvm_domain_irq(currd);
> -            int gsi = domain_pirq_to_emuirq(currd, eoi.irq);
> +            int gsi = domain_irq_to_emuirq(currd, eoi.irq);
>  
>              /* if this is a level irq and count > 0, send another
>               * notification */ 
> @@ -267,7 +267,7 @@ ret_t do_physdev_op(int cmd, XEN_GUEST_HANDLE_PARAM(void) arg)
>          irq_status_query.flags = 0;
>          if ( is_hvm_domain(currd) &&
>               domain_pirq_to_irq(currd, irq) <= 0 &&
> -             domain_pirq_to_emuirq(currd, irq) == IRQ_UNBOUND )
> +             domain_irq_to_emuirq(currd, irq) == IRQ_UNBOUND )
>          {
>              ret = -EINVAL;
>              break;
> diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> index aea38304b60c..1126b53c30df 100644
> --- a/xen/common/emul/vuart/ns16x50.c
> +++ b/xen/common/emul/vuart/ns16x50.c
> @@ -287,7 +287,9 @@ static void ns16x50_irq_assert(const struct vuart_ns16x50 *vdev)
>      const struct vuart_info *info = vdev->info;
>      int vector;
>  
> -    if ( has_vpic(d) ) /* HVM */
> +    if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */
> +        vector = hvm_ioapic_assert(d, info->irq, false);
> +    else if ( has_vpic(d) ) /* HVM */
>          vector = hvm_isa_irq_assert(d, info->irq, vioapic_get_vector);
>      else
>          ASSERT_UNREACHABLE();
> @@ -300,7 +302,9 @@ static void ns16x50_irq_deassert(const struct vuart_ns16x50 *vdev)
>      struct domain *d = vdev->owner;
>      const struct vuart_info *info = vdev->info;
>  
> -    if ( has_vpic(d) ) /* HVM */
> +    if ( has_vioapic(d) && !has_vpic(d) ) /* PVH */
> +        hvm_ioapic_deassert(d, info->irq);
> +    else if ( has_vpic(d) ) /* HVM */
>          hvm_isa_irq_deassert(d, info->irq);
>      else
>          ASSERT_UNREACHABLE();
> @@ -803,6 +807,17 @@ static int ns16x50_init(void *arg)
>          return rc;
>      }
>  
> +    /* Claim virtual IRQ */
> +    write_lock(&d->event_lock);
> +    rc = map_domain_emuirq_pirq(d, info->irq, IRQ_EMU);
> +    write_unlock(&d->event_lock);
> +    if ( rc )
> +    {
> +        ns16x50_err(info, "virtual IRQ#%d: cannot claim: %d\n",
> +                    info->irq, rc);
> +        return rc;
> +    }
> +
>      /* NB: report 115200 baud rate. */
>      vdev->regs[NS16X50_REGS_NUM + UART_DLL] = divisor & 0xff;
>      vdev->regs[NS16X50_REGS_NUM + UART_DLM] = (divisor >> 8) & 0xff;
> @@ -822,9 +837,22 @@ static int ns16x50_init(void *arg)
>  static void cf_check ns16x50_deinit(void *arg)
>  {
>      struct vuart_ns16x50 *vdev = arg;
> +    const struct vuart_info *info;
> +    struct domain *d;
> +    int rc;
>  
>      ASSERT(vdev);
>  
> +    d = vdev->owner;
> +    info = vdev->info;
> +
> +    write_lock(&d->event_lock);
> +    rc = unmap_domain_pirq_emuirq(d, info->irq);
> +    write_unlock(&d->event_lock);
> +    if ( rc )
> +        ns16x50_err(vdev, "virtual IRQ#%d: cannot unclaim: %d\n",
> +                    info->irq, rc);
> +
>      spin_lock(&vdev->lock);
>      ns16x50_fifo_tx_flush(vdev);
>      spin_unlock(&vdev->lock);
> diff --git a/xen/drivers/passthrough/x86/hvm.c b/xen/drivers/passthrough/x86/hvm.c
> index a2ca7e0e570c..11711d20a7ea 100644
> --- a/xen/drivers/passthrough/x86/hvm.c
> +++ b/xen/drivers/passthrough/x86/hvm.c
> @@ -923,13 +923,16 @@ static void __hvm_dpci_eoi(struct domain *d,
>  static void hvm_gsi_eoi(struct domain *d, unsigned int gsi)
>  {
>      struct pirq *pirq = pirq_info(d, gsi);
> +    int rc;
> +
> +    /* Check if GSI is claimed by one of the virtual devices. */
> +    rc = domain_irq_to_emuirq(d, gsi);
> +    if ( rc != IRQ_UNBOUND )
> +        hvm_gsi_deassert(d, gsi);
>  
>      /* Check if GSI is actually mapped. */
> -    if ( !pirq_dpci(pirq) )
> -        return;
> -
> -    hvm_gsi_deassert(d, gsi);
> -    hvm_pirq_eoi(pirq);
> +    if ( pirq_dpci(pirq) )
> +        hvm_pirq_eoi(pirq);
>  }
>  
>  static int cf_check _hvm_dpci_isairq_eoi(
> -- 
> 2.51.0
> 


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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v17 0/4] xen/domain: domain ID allocation
Date: Fri, 29 Aug 2025 16:21:28 -0700
Message-ID: <20250829232132.3460081-1-dmukhin@ford.com>
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Patch 1 introduces new domid_{alloc,free} calls.
Patch 2 is a prep change for domain ID allocator test.
Patch 3 introduces some basic testing for domain ID allocator.
Patch 4 adjusts create_dom0() messages (use %pd).

Link to v16: https://lore.kernel.org/xen-devel/20250812223024.2364749-1-dmukhin@ford.com/
Link to CI: https://gitlab.com/xen-project/people/dmukhin/xen/-/pipelines/2012378054

Denis Mukhin (4):
  xen/domain: unify domain ID allocation
  tools/include: move xc_bitops.h to xen-tools/bitops.h
  tools/tests: introduce unit tests for domain ID allocator
  xen/domain: update create_dom0() messages

 .../xen-tools/bitops.h}                       | 16 +++-
 tools/libs/ctrl/xc_misc.c                     | 13 +--
 tools/libs/guest/xg_dom_elfloader.c           |  1 -
 tools/libs/guest/xg_dom_hvmloader.c           |  1 -
 tools/libs/guest/xg_private.h                 |  2 +-
 tools/libs/guest/xg_sr_common.h               |  2 -
 tools/tests/Makefile                          |  1 +
 tools/tests/domid/.gitignore                  |  2 +
 tools/tests/domid/Makefile                    | 88 +++++++++++++++++
 tools/tests/domid/harness.h                   | 54 +++++++++++
 tools/tests/domid/test-domid.c                | 95 +++++++++++++++++++
 xen/arch/arm/domain_build.c                   | 13 ++-
 xen/arch/x86/setup.c                          | 11 ++-
 xen/common/Makefile                           |  1 +
 xen/common/device-tree/dom0less-build.c       | 15 +--
 xen/common/domain.c                           |  2 +
 xen/common/domctl.c                           | 43 ++-------
 xen/common/domid.c                            | 95 +++++++++++++++++++
 xen/include/xen/domain.h                      |  3 +
 xen/lib/find-next-bit.c                       |  5 +
 20 files changed, 397 insertions(+), 66 deletions(-)
 rename tools/{libs/ctrl/xc_bitops.h => include/xen-tools/bitops.h} (84%)
 create mode 100644 tools/tests/domid/.gitignore
 create mode 100644 tools/tests/domid/Makefile
 create mode 100644 tools/tests/domid/harness.h
 create mode 100644 tools/tests/domid/test-domid.c
 create mode 100644 xen/common/domid.c

-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com,
	Alejandro Vallejo ,
	Julien Grall 
Subject: [PATCH v17 4/4] xen/domain: update create_dom0() messages
Date: Fri, 29 Aug 2025 16:21:32 -0700
Message-ID: <20250829232132.3460081-5-dmukhin@ford.com>
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From: Denis Mukhin  

Use %pd for domain identification in error/panic messages in create_dom0().

No functional change.

Signed-off-by: Denis Mukhin 
Reviewed-by: Alejandro Vallejo 
Acked-by: Jan Beulich 
Reviewed-by: Julien Grall 
---
Changes since v16:
- n/a
---
 xen/arch/arm/domain_build.c | 6 +++---
 xen/arch/x86/setup.c        | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index aca35b8961d6..670f634b8b0d 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2084,14 +2084,14 @@ void __init create_dom0(void)
         panic("Error creating domain 0 (rc = %ld)\n", PTR_ERR(dom0));
 
     if ( llc_coloring_enabled && (rc = dom0_set_llc_colors(dom0)) )
-        panic("Error initializing LLC coloring for domain 0 (rc = %d)\n", rc);
+        panic("Error initializing LLC coloring for %pd (rc = %d)\n", dom0, rc);
 
     if ( vcpu_create(dom0, 0) == NULL )
-        panic("Error creating domain 0 vcpu0\n");
+        panic("Error creating %pdv0\n", dom0);
 
     rc = construct_dom0(dom0);
     if ( rc )
-        panic("Could not set up DOM0 guest OS (rc = %d)\n", rc);
+        panic("Could not set up %pd guest OS (rc = %d)\n", dom0, rc);
 
     set_xs_domain(dom0);
 }
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 78e24b78c5a6..da1fe8fdb6dd 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1075,7 +1075,7 @@ static struct domain *__init create_dom0(struct boot_info *bi)
 
         if ( (strlen(acpi_param) == 0) && acpi_disabled )
         {
-            printk("ACPI is disabled, notifying Domain 0 (acpi=off)\n");
+            printk("ACPI is disabled, notifying %pd (acpi=off)\n", d);
             safe_strcpy(acpi_param, "off");
         }
 
@@ -1090,7 +1090,7 @@ static struct domain *__init create_dom0(struct boot_info *bi)
 
     bd->d = d;
     if ( construct_dom0(bd) != 0 )
-        panic("Could not construct domain 0\n");
+        panic("Could not construct %pd\n", d);
 
     bd->cmdline = NULL;
     xfree(cmdline);
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com,
	Julien Grall ,
	Alejandro Vallejo 
Subject: [PATCH v17 1/4] xen/domain: unify domain ID allocation
Date: Fri, 29 Aug 2025 16:21:29 -0700
Message-ID: <20250829232132.3460081-2-dmukhin@ford.com>
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From: Denis Mukhin  

Currently, there are two different domain ID allocation implementations:

  1) Sequential IDs allocation in dom0less Arm code based on max_init_domid;

  2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
     max_init_domid (both Arm and x86).

The domain ID allocation covers dom0 or late hwdom, predefined domains,
post-boot domains, excluding Xen system domains (domid >=
DOMID_FIRST_RESERVED).

It makes sense to have a common helper code for such task across architectures
(Arm and x86) and between dom0less / toolstack domU allocation.

Note, fixing dependency on max_init_domid is out of scope of this patch.

Wrap the domain ID allocation as an arch-independent function domid_alloc() in
new common/domid.c based on the bitmap.

Allocation algorithm:
- If an explicit domain ID is provided, verify its availability and use it if
  ID is not used;
- If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1],
  starting from the last used ID.
  Implementation guarantees that two consecutive calls will never return the
  same ID. ID#0 is reserved for the first boot domain (currently, dom0) and
  excluded from the allocation range.

Remove is_free_domid() helper as it is not needed now.

No functional change intended.

Signed-off-by: Denis Mukhin 
Reviewed-by: Julien Grall 
Reviewed-by: Alejandro Vallejo 
---
Changes since v16:
- n/a
- kept existing R-bs
---
 xen/arch/arm/domain_build.c             |  7 +-
 xen/arch/x86/setup.c                    |  7 +-
 xen/common/Makefile                     |  1 +
 xen/common/device-tree/dom0less-build.c | 15 ++--
 xen/common/domain.c                     |  2 +
 xen/common/domctl.c                     | 43 ++---------
 xen/common/domid.c                      | 95 +++++++++++++++++++++++++
 xen/include/xen/domain.h                |  3 +
 8 files changed, 126 insertions(+), 47 deletions(-)
 create mode 100644 xen/common/domid.c

diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index a9e4153e3cf9..aca35b8961d6 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -2050,6 +2050,7 @@ void __init create_dom0(void)
         .grant_opts = XEN_DOMCTL_GRANT_version(opt_gnttab_max_version),
     };
     unsigned int flags = CDF_privileged | CDF_hardware;
+    domid_t domid;
     int rc;
 
     /* The vGIC for DOM0 is exactly emulating the hardware GIC */
@@ -2074,7 +2075,11 @@ void __init create_dom0(void)
     if ( !llc_coloring_enabled )
         flags |= CDF_directmap;
 
-    dom0 = domain_create(0, &dom0_cfg, flags);
+    domid = domid_alloc(0);
+    if ( domid == DOMID_INVALID )
+        panic("Error allocating domain ID 0\n");
+
+    dom0 = domain_create(domid, &dom0_cfg, flags);
     if ( IS_ERR(dom0) )
         panic("Error creating domain 0 (rc = %ld)\n", PTR_ERR(dom0));
 
diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c
index 6c81841426a4..78e24b78c5a6 100644
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -1038,8 +1038,11 @@ static struct domain *__init create_dom0(struct boot_info *bi)
     if ( iommu_enabled )
         dom0_cfg.flags |= XEN_DOMCTL_CDF_iommu;
 
-    /* Create initial domain.  Not d0 for pvshim. */
-    bd->domid = get_initial_domain_id();
+    /* Allocate initial domain ID.  Not d0 for pvshim. */
+    bd->domid = domid_alloc(get_initial_domain_id());
+    if ( bd->domid == DOMID_INVALID )
+        panic("Error allocating domain ID %u\n", get_initial_domain_id());
+
     d = domain_create(bd->domid, &dom0_cfg,
                       pv_shim ? 0 : CDF_privileged | CDF_hardware);
     if ( IS_ERR(d) )
diff --git a/xen/common/Makefile b/xen/common/Makefile
index c316957fcb36..0c7d0f5d46e1 100644
--- a/xen/common/Makefile
+++ b/xen/common/Makefile
@@ -11,6 +11,7 @@ obj-$(filter-out $(CONFIG_X86),$(CONFIG_ACPI)) += device.o
 obj-$(CONFIG_DEVICE_TREE_PARSE) += device-tree/
 obj-$(CONFIG_IOREQ_SERVER) += dm.o
 obj-y += domain.o
+obj-y += domid.o
 obj-y += event_2l.o
 obj-y += event_channel.o
 obj-$(CONFIG_EVTCHN_FIFO) += event_fifo.o
diff --git a/xen/common/device-tree/dom0less-build.c b/xen/common/device-tree/dom0less-build.c
index badc227031eb..8ef5ae9c0912 100644
--- a/xen/common/device-tree/dom0less-build.c
+++ b/xen/common/device-tree/dom0less-build.c
@@ -834,6 +834,7 @@ void __init create_domUs(void)
     {
         struct kernel_info ki = KERNEL_INFO_INIT;
         int rc = parse_dom0less_node(node, &ki.bd);
+        domid_t domid;
 
         if ( rc == -ENOENT )
             continue;
@@ -843,13 +844,13 @@ void __init create_domUs(void)
         if ( (max_init_domid + 1) >= DOMID_FIRST_RESERVED )
             panic("No more domain IDs available\n");
 
-        /*
-         * The variable max_init_domid is initialized with zero, so here it's
-         * very important to use the pre-increment operator to call
-         * domain_create() with a domid > 0. (domid == 0 is reserved for Dom0)
-         */
-        ki.bd.d = domain_create(++max_init_domid,
-                                &ki.bd.create_cfg, ki.bd.create_flags);
+        domid = domid_alloc(DOMID_INVALID);
+        if ( domid == DOMID_INVALID )
+            panic("Error allocating ID for domain %s\n", dt_node_name(node));
+
+        max_init_domid = max(max_init_domid, domid);
+
+        ki.bd.d = domain_create(domid, &ki.bd.create_cfg, ki.bd.create_flags);
         if ( IS_ERR(ki.bd.d) )
             panic("Error creating domain %s (rc = %ld)\n",
                   dt_node_name(node), PTR_ERR(ki.bd.d));
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 104e917f07e3..775c33928585 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -692,6 +692,8 @@ static void _domain_destroy(struct domain *d)
 
     lock_profile_deregister_struct(LOCKPROF_TYPE_PERDOM, d);
 
+    domid_free(d->domain_id);
+
     free_domain_struct(d);
 }
 
diff --git a/xen/common/domctl.c b/xen/common/domctl.c
index f2a7caaf853c..71e712c1f316 100644
--- a/xen/common/domctl.c
+++ b/xen/common/domctl.c
@@ -51,20 +51,6 @@ static int xenctl_bitmap_to_nodemask(nodemask_t *nodemask,
                                    MAX_NUMNODES);
 }
 
-static inline int is_free_domid(domid_t dom)
-{
-    struct domain *d;
-
-    if ( dom >= DOMID_FIRST_RESERVED )
-        return 0;
-
-    if ( (d = rcu_lock_domain_by_id(dom)) == NULL )
-        return 1;
-
-    rcu_unlock_domain(d);
-    return 0;
-}
-
 void getdomaininfo(struct domain *d, struct xen_domctl_getdomaininfo *info)
 {
     struct vcpu *v;
@@ -423,36 +409,19 @@ long do_domctl(XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl)
 
     case XEN_DOMCTL_createdomain:
     {
-        domid_t        dom;
-        static domid_t rover = 0;
+        /* NB: ID#0 is reserved, find the first suitable ID instead. */
+        domid_t domid = domid_alloc(op->domain ?: DOMID_INVALID);
 
-        dom = op->domain;
-        if ( (dom > 0) && (dom < DOMID_FIRST_RESERVED) )
+        if ( domid == DOMID_INVALID )
         {
             ret = -EEXIST;
-            if ( !is_free_domid(dom) )
-                break;
-        }
-        else
-        {
-            for ( dom = rover + 1; dom != rover; dom++ )
-            {
-                if ( dom == DOMID_FIRST_RESERVED )
-                    dom = 1;
-                if ( is_free_domid(dom) )
-                    break;
-            }
-
-            ret = -ENOMEM;
-            if ( dom == rover )
-                break;
-
-            rover = dom;
+            break;
         }
 
-        d = domain_create(dom, &op->u.createdomain, false);
+        d = domain_create(domid, &op->u.createdomain, false);
         if ( IS_ERR(d) )
         {
+            domid_free(domid);
             ret = PTR_ERR(d);
             d = NULL;
             break;
diff --git a/xen/common/domid.c b/xen/common/domid.c
new file mode 100644
index 000000000000..2387ddb08300
--- /dev/null
+++ b/xen/common/domid.c
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Domain ID allocator.
+ *
+ * Covers dom0 or late hwdom, predefined domains, post-boot domains.
+ * Excludes system domains (ID >= DOMID_FIRST_RESERVED).
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include 
+
+static DEFINE_SPINLOCK(domid_lock);
+static DECLARE_BITMAP(domid_bitmap, DOMID_FIRST_RESERVED);
+
+/*
+ * Allocate domain ID.
+ *
+ * @param domid Domain ID hint:
+ * - If an explicit domain ID is provided, verify its availability and use it
+ *   if ID is not used;
+ * - If DOMID_INVALID is provided, search [1..DOMID_FIRST_RESERVED-1] range,
+ *   starting from the last used ID. Implementation guarantees that two
+ *   consecutive calls will never return the same ID. ID#0 is reserved for
+ *   the first boot domain (currently, dom0) and excluded from the allocation
+ *   range.
+ * @return Valid domain ID in case of successful allocation,
+ *         DOMID_INVALID - otherwise.
+ */
+domid_t domid_alloc(domid_t domid)
+{
+    static domid_t domid_last;
+
+    spin_lock(&domid_lock);
+
+    /* Exact match. */
+    if ( domid < DOMID_FIRST_RESERVED )
+    {
+        if ( __test_and_set_bit(domid, domid_bitmap) )
+            domid = DOMID_INVALID;
+    }
+    /*
+     * Exhaustive search.
+     *
+     * Domain ID#0 is reserved for the first boot domain (e.g. control domain)
+     * and excluded from allocation.
+     */
+    else
+    {
+        domid_t bound = DOMID_FIRST_RESERVED;
+
+        domid = find_next_zero_bit(domid_bitmap, bound, domid_last + 1);
+        if ( domid >= bound && domid_last != 0 )
+        {
+            bound = domid_last + 1;
+            domid = find_next_zero_bit(domid_bitmap, bound, 1);
+        }
+
+        ASSERT(domid <= DOMID_FIRST_RESERVED);
+        if ( domid < bound )
+        {
+            __set_bit(domid, domid_bitmap);
+            domid_last = domid;
+        }
+        else
+            domid = DOMID_INVALID;
+    }
+
+    spin_unlock(&domid_lock);
+
+    return domid;
+}
+
+void domid_free(domid_t domid)
+{
+    int rc;
+
+    ASSERT(domid <= DOMID_FIRST_RESERVED);
+
+    spin_lock(&domid_lock);
+    rc = __test_and_clear_bit(domid, domid_bitmap);
+    spin_unlock(&domid_lock);
+
+    ASSERT(rc);
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * tab-width: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615fd..8aab05ae93c8 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -38,6 +38,9 @@ void arch_get_domain_info(const struct domain *d,
 
 domid_t get_initial_domain_id(void);
 
+domid_t domid_alloc(domid_t domid);
+void domid_free(domid_t domid);
+
 /* CDF_* constant. Internal flags for domain creation. */
 /* Is this a privileged domain? */
 #define CDF_privileged           (1U << 0)
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v17 2/4] tools/include: move xc_bitops.h to xen-tools/bitops.h
Date: Fri, 29 Aug 2025 16:21:30 -0700
Message-ID: <20250829232132.3460081-3-dmukhin@ford.com>
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From: Denis Mukhin  

Move xc_bitops.h to common tools location to be shared between
the toolstack and unit test code.

Adjust the guard in xen-tools/bitops.h

Correct the #include directives and comments referring to the old
xc_bitops.h in the toolstack code.

Signed-off-by: Denis Mukhin 
Acked-by: Anthony PERARD 
---
Changes since v16:
- dropped unneeded includes
- added Anthony's A-b
---
 .../ctrl/xc_bitops.h => include/xen-tools/bitops.h} |  6 +++---
 tools/libs/ctrl/xc_misc.c                           | 13 +++++++------
 tools/libs/guest/xg_dom_elfloader.c                 |  1 -
 tools/libs/guest/xg_dom_hvmloader.c                 |  1 -
 tools/libs/guest/xg_private.h                       |  2 +-
 tools/libs/guest/xg_sr_common.h                     |  2 --
 6 files changed, 11 insertions(+), 14 deletions(-)
 rename tools/{libs/ctrl/xc_bitops.h => include/xen-tools/bitops.h} (95%)

diff --git a/tools/libs/ctrl/xc_bitops.h b/tools/include/xen-tools/bitops.h
similarity index 95%
rename from tools/libs/ctrl/xc_bitops.h
rename to tools/include/xen-tools/bitops.h
index 4a776dc3a57f..681482f6759f 100644
--- a/tools/libs/ctrl/xc_bitops.h
+++ b/tools/include/xen-tools/bitops.h
@@ -1,5 +1,5 @@
-#ifndef XC_BITOPS_H
-#define XC_BITOPS_H 1
+#ifndef __XEN_TOOLS_BITOPS_H__
+#define __XEN_TOOLS_BITOPS_H__
 
 /* bitmap operations for single threaded access */
 
@@ -81,4 +81,4 @@ static inline void bitmap_or(void *_dst, const void *_other,
         dst[i] |= other[i];
 }
 
-#endif  /* XC_BITOPS_H */
+#endif  /* __XEN_TOOLS_BITOPS_H__ */
diff --git a/tools/libs/ctrl/xc_misc.c b/tools/libs/ctrl/xc_misc.c
index 33e87bac2868..10ddf85667a9 100644
--- a/tools/libs/ctrl/xc_misc.c
+++ b/tools/libs/ctrl/xc_misc.c
@@ -17,8 +17,8 @@
  * License along with this library; If not, see .
  */
 
-#include "xc_bitops.h"
 #include "xc_private.h"
+#include 
 #include 
 
 int xc_get_max_cpus(xc_interface *xch)
@@ -94,11 +94,12 @@ xc_cpumap_t xc_cpumap_alloc(xc_interface *xch)
 }
 
 /*
- * xc_bitops.h has macros that do this as well - however they assume that
- * the bitmask is word aligned but xc_cpumap_t is only guaranteed to be
- * byte aligned and so we need byte versions for architectures which do
- * not support misaligned accesses (which is basically everyone
- * but x86, although even on x86 it can be inefficient).
+ *  has macros that do this as well - however they
+ * assume that the bitmask is word aligned but xc_cpumap_t is only
+ * guaranteed to be byte aligned and so we need byte versions for
+ * architectures which do not support misaligned accesses (which is
+ * basically everyone but x86, although even on x86 it can be
+ * inefficient).
  *
  * NOTE: The xc_bitops macros now use byte alignment.
  * TODO: Clean up the users of this interface.
diff --git a/tools/libs/guest/xg_dom_elfloader.c b/tools/libs/guest/xg_dom_elfloader.c
index f17930d98bf7..a55b5e8c3caf 100644
--- a/tools/libs/guest/xg_dom_elfloader.c
+++ b/tools/libs/guest/xg_dom_elfloader.c
@@ -26,7 +26,6 @@
 #include 
 
 #include "xg_private.h"
-#include "xc_bitops.h"
 
 #define XEN_VER "xen-3.0"
 
diff --git a/tools/libs/guest/xg_dom_hvmloader.c b/tools/libs/guest/xg_dom_hvmloader.c
index 39e1e5f579a7..a98c7fe5d877 100644
--- a/tools/libs/guest/xg_dom_hvmloader.c
+++ b/tools/libs/guest/xg_dom_hvmloader.c
@@ -25,7 +25,6 @@
 #include 
 
 #include "xg_private.h"
-#include "xc_bitops.h"
 
 /* ------------------------------------------------------------------------ */
 /* parse elf binary                                                         */
diff --git a/tools/libs/guest/xg_private.h b/tools/libs/guest/xg_private.h
index d73947094f2e..285229cf82a3 100644
--- a/tools/libs/guest/xg_private.h
+++ b/tools/libs/guest/xg_private.h
@@ -28,9 +28,9 @@
 #include 
 
 #include "xc_private.h"
-#include "xc_bitops.h"
 #include "xenguest.h"
 
+#include 
 #include 
 #include 
 #include 
diff --git a/tools/libs/guest/xg_sr_common.h b/tools/libs/guest/xg_sr_common.h
index 2f058ee3a6ff..0e419c3a96a0 100644
--- a/tools/libs/guest/xg_sr_common.h
+++ b/tools/libs/guest/xg_sr_common.h
@@ -5,8 +5,6 @@
 
 #include "xg_private.h"
 #include "xg_save_restore.h"
-#include "xc_bitops.h"
-
 #include "xg_sr_stream_format.h"
 
 /* String representation of Domain Header types. */
-- 
2.51.0



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From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com,
	anthony.perard@vates.tech,
	jbeulich@suse.com,
	julien@xen.org,
	michal.orzel@amd.com,
	roger.pau@citrix.com,
	sstabellini@kernel.org,
	dmukhin@ford.com
Subject: [PATCH v17 3/4] tools/tests: introduce unit tests for domain ID allocator
Date: Fri, 29 Aug 2025 16:21:31 -0700
Message-ID: <20250829232132.3460081-4-dmukhin@ford.com>
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From: Denis Mukhin  

Introduce some basic infrastructure for doing domain ID allocation unit tests,
and add a few tests that ensure correctness of the domain ID allocator.

Use  and xen/lib/find-next-bit.c in test hardness code.

Adjust find-next-bit.c to be compiled with __XEN_TOOLS__.

Signed-off-by: Denis Mukhin 
---
Changes since v16:
- used exit() in the test suite's verify()
- various fixes in the test Makefile
---
 tools/include/xen-tools/bitops.h | 10 ++++
 tools/tests/Makefile             |  1 +
 tools/tests/domid/.gitignore     |  2 +
 tools/tests/domid/Makefile       | 88 +++++++++++++++++++++++++++++
 tools/tests/domid/harness.h      | 54 ++++++++++++++++++
 tools/tests/domid/test-domid.c   | 95 ++++++++++++++++++++++++++++++++
 xen/lib/find-next-bit.c          |  5 ++
 7 files changed, 255 insertions(+)
 create mode 100644 tools/tests/domid/.gitignore
 create mode 100644 tools/tests/domid/Makefile
 create mode 100644 tools/tests/domid/harness.h
 create mode 100644 tools/tests/domid/test-domid.c

diff --git a/tools/include/xen-tools/bitops.h b/tools/include/xen-tools/bitops.h
index 681482f6759f..3b98fba6d74c 100644
--- a/tools/include/xen-tools/bitops.h
+++ b/tools/include/xen-tools/bitops.h
@@ -12,6 +12,16 @@
 #define BITS_PER_LONG 32
 #endif
 
+#define ffsl(x)       __builtin_ffsl(x)
+
+#define BIT_WORD(nr)  ((nr) / BITS_PER_LONG)
+
+#define BITS_TO_LONGS(bits) \
+    (((bits) + BITS_PER_LONG - 1) / BITS_PER_LONG)
+
+#define DECLARE_BITMAP(name, bits) \
+    unsigned long name[BITS_TO_LONGS(bits)]
+
 #define BITMAP_ENTRY(_nr,_bmap) ((_bmap))[(_nr) / 8]
 #define BITMAP_SHIFT(_nr) ((_nr) % 8)
 
diff --git a/tools/tests/Makefile b/tools/tests/Makefile
index 97ba2a13894d..ac5737364623 100644
--- a/tools/tests/Makefile
+++ b/tools/tests/Makefile
@@ -2,6 +2,7 @@ XEN_ROOT = $(CURDIR)/../..
 include $(XEN_ROOT)/tools/Rules.mk
 
 SUBDIRS-y :=
+SUBDIRS-y += domid
 SUBDIRS-y += resource
 SUBDIRS-$(CONFIG_X86) += cpu-policy
 SUBDIRS-$(CONFIG_X86) += tsx
diff --git a/tools/tests/domid/.gitignore b/tools/tests/domid/.gitignore
new file mode 100644
index 000000000000..37d773103be4
--- /dev/null
+++ b/tools/tests/domid/.gitignore
@@ -0,0 +1,2 @@
+generated
+test-domid
diff --git a/tools/tests/domid/Makefile b/tools/tests/domid/Makefile
new file mode 100644
index 000000000000..22f1f15d11db
--- /dev/null
+++ b/tools/tests/domid/Makefile
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Unit tests for domain ID allocator.
+#
+# Copyright 2025 Ford Motor Company
+
+XEN_ROOT=$(CURDIR)/../../..
+include $(XEN_ROOT)/tools/Rules.mk
+
+TESTS := test-domid
+
+define list-c-headers
+$(shell sed -n -E \
+    's/^[ \t]*# *include[ \t]*[<"]([^">]+)[">].*/\1/p' $(1) 2>/dev/null)
+endef
+
+# NB: $1 cannot be a list
+define emit-harness-nested-rule
+$(1): $(CURDIR)/harness.h
+	mkdir -p $$(@D);
+	ln -sf $$< $$@;
+
+endef
+
+define emit-harness-rules
+$(foreach x,$(2),$(call emit-harness-nested-rule,$(CURDIR)/generated/$(x)))
+$(1:.c=.o): $(addprefix $(CURDIR)/generated/,$(2))
+endef
+
+define emit-harness-deps
+$(if $(strip $(2)),$(call emit-harness-rules,$1,$2),)
+endef
+
+define vpath-with-harness-deps
+vpath $(1) $(2)
+$(call emit-harness-deps,$(1),$(call list-c-headers,$(2)$(1)))
+endef
+
+.PHONY: all
+all: $(TESTS)
+
+.PHONY: run
+run: $(TESTS)
+	set -e; $(foreach t,$(TESTS),./$(t);)
+
+.PHONY: clean
+clean:
+	$(RM) -r generated
+	$(RM) -- *.o $(TESTS) $(DEPS_RM)
+
+.PHONY: distclean
+distclean: clean
+	$(RM) -- *~
+
+.PHONY: install
+install: all
+	$(INSTALL_DIR) $(DESTDIR)$(LIBEXEC)/tests
+	$(INSTALL_PROG) test-domid $(DESTDIR)$(LIBEXEC)/tests
+
+.PHONY: uninstall
+uninstall:
+	$(RM) -- $(DESTDIR)$(LIBEXEC)/tests/test-domid
+
+CFLAGS += -D__XEN_TOOLS__
+# find-next-bit.c
+CFLAGS += '-DEXPORT_SYMBOL(x)=' \
+          -Dfind_first_bit \
+          -Dfind_first_zero_bit \
+          -Dfind_next_bit \
+          -Dfind_next_bit_le \
+          -Dfind_next_zero_bit_le
+CFLAGS += $(APPEND_CFLAGS)
+CFLAGS += $(CFLAGS_xeninclude)
+CFLAGS += -I./generated/
+
+LDFLAGS += $(APPEND_LDFLAGS)
+
+vpath find-next-bit.c $(XEN_ROOT)/xen/lib/
+
+# Point to the hypervisor code and generate test harness dependencies
+# on the fly, making it possible to compile parts of the hypervisor
+# within a mocked environment.
+$(eval $(call vpath-with-harness-deps,domid.c,$(XEN_ROOT)/xen/common/))
+
+test-domid: domid.o find-next-bit.o test-domid.o
+	$(CC) $^ -o $@ $(LDFLAGS)
+
+-include $(DEPS_INCLUDE)
diff --git a/tools/tests/domid/harness.h b/tools/tests/domid/harness.h
new file mode 100644
index 000000000000..17eb22a9a854
--- /dev/null
+++ b/tools/tests/domid/harness.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Unit test harness for domain ID allocator.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#ifndef _TEST_HARNESS_
+#define _TEST_HARNESS_
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+typedef bool spinlock_t;
+typedef uint16_t domid_t;
+
+extern domid_t domid_alloc(domid_t domid);
+extern void domid_free(domid_t domid);
+
+extern unsigned long find_next_zero_bit(const unsigned long *addr,
+                                        unsigned long size,
+                                        unsigned long offset);
+
+#define __test_and_set_bit(nr, addr)    test_and_set_bit(nr, addr)
+#define __test_and_clear_bit(nr, addr)  test_and_clear_bit(nr, addr)
+#define __set_bit(nr, addr)             set_bit(nr, addr)
+
+#define BUG_ON(x)                       assert(!(x))
+#define ASSERT(x)                       assert(x)
+
+#define DEFINE_SPINLOCK(l)              spinlock_t l
+#define spin_lock(l)                    (assert(!*(l)), *(l) = true)
+#define spin_unlock(l)                  (assert(*(l)), *(l) = false)
+
+#define printk                          printf
+
+#define DOMID_FIRST_RESERVED            (100)
+#define DOMID_INVALID                   (101)
+
+#endif /* _TEST_HARNESS_ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/tools/tests/domid/test-domid.c b/tools/tests/domid/test-domid.c
new file mode 100644
index 000000000000..5915c4699a5c
--- /dev/null
+++ b/tools/tests/domid/test-domid.c
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Unit tests for domain ID allocator.
+ *
+ * Copyright 2025 Ford Motor Company
+ */
+
+#include 
+
+#include "harness.h"
+
+#define verify(exp, fmt, args...) \
+while (!(exp)) { \
+    printf(fmt, ## args); \
+    exit(EX_SOFTWARE); \
+}
+
+/*
+ * Fail on the first error, since tests are dependent on each other.
+ */
+int main(int argc, char **argv)
+{
+    domid_t expected, allocated;
+
+    /* Test ID cannot be allocated twice. */
+    for ( expected = 0; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated = domid_alloc(expected);
+        verify(allocated == expected,
+               "TEST 1: expected %u allocated %u\n", expected, allocated);
+    }
+    for ( expected = 0; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated = domid_alloc(expected);
+        verify(allocated == DOMID_INVALID,
+               "TEST 2: expected %u allocated %u\n", DOMID_INVALID, allocated);
+    }
+
+    /* Ensure all IDs, including ID#0 are not allocated. */
+    for ( expected = 0; expected < DOMID_FIRST_RESERVED; expected++ )
+        domid_free(expected);
+
+    /*
+     * Test that that two consecutive calls of domid_alloc(DOMID_INVALID)
+     * will never return the same ID.
+     * NB: ID#0 is reserved and shall not be allocated by
+     * domid_alloc(DOMID_INVALID).
+     */
+    for ( expected = 1; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated = domid_alloc(DOMID_INVALID);
+        verify(allocated == expected,
+               "TEST 3: expected %u allocated %u\n", expected, allocated);
+    }
+    for ( expected = 1; expected < DOMID_FIRST_RESERVED; expected++ )
+    {
+        allocated = domid_alloc(DOMID_INVALID);
+        verify(allocated == DOMID_INVALID,
+               "TEST 4: expected %u allocated %u\n", DOMID_INVALID, allocated);
+    }
+
+    /* Re-allocate first ID from [1..DOMID_FIRST_RESERVED/2]. */
+    for ( expected = 1; expected < DOMID_FIRST_RESERVED / 2; expected++ )
+        domid_free(expected);
+    for ( expected = 1; expected < DOMID_FIRST_RESERVED / 2; expected++ )
+    {
+        allocated = domid_alloc(DOMID_INVALID);
+        verify(allocated == expected,
+               "TEST 5: expected %u allocated %u\n", expected, allocated);
+    }
+
+    /* Re-allocate last ID from [1..DOMID_FIRST_RESERVED - 1]. */
+    expected = DOMID_FIRST_RESERVED - 1;
+    domid_free(DOMID_FIRST_RESERVED - 1);
+    allocated = domid_alloc(DOMID_INVALID);
+    verify(allocated == expected,
+           "TEST 6: expected %u allocated %u\n", expected, allocated);
+
+    /* Allocate an invalid ID. */
+    expected = DOMID_INVALID;
+    allocated = domid_alloc(DOMID_FIRST_RESERVED);
+    verify(allocated == expected,
+           "TEST 7: expected %u allocated %u\n", expected, allocated);
+
+    return 0;
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/lib/find-next-bit.c b/xen/lib/find-next-bit.c
index 9b8d7814f20c..539c7f2022b0 100644
--- a/xen/lib/find-next-bit.c
+++ b/xen/lib/find-next-bit.c
@@ -8,8 +8,13 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
+
+#ifdef __XEN_TOOLS__
+#include 
+#else
 #include 
 #include 
+#endif
 
 #define __ffs(x) (ffsl(x) - 1)
 #define ffz(x) __ffs(~(x))
-- 
2.51.0



From xen-devel-bounces@lists.xenproject.org Fri Aug 29 23:32:39 2025
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From: dmukhin@xen.org
Date: Fri, 29 Aug 2025 16:32:27 -0700
To: Julien Grall 
Cc: dmkhn@proton.me, xen-devel@lists.xenproject.org,
	andrew.cooper3@citrix.com, anthony.perard@vates.tech,
	jbeulich@suse.com, michal.orzel@amd.com, roger.pau@citrix.com,
	sstabellini@kernel.org, dmukhin@ford.com,
	Julien Grall ,
	Alejandro Vallejo 
Subject: Re: [PATCH v16 1/4] xen/domain: unify domain ID allocation
Message-ID: 
References: <20250812223024.2364749-1-dmukhin@ford.com>
 <20250812223024.2364749-2-dmukhin@ford.com>
 
 <304cffd8-498d-447f-a8b0-cda694393ec8@xen.org>
MIME-Version: 1.0
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In-Reply-To: <304cffd8-498d-447f-a8b0-cda694393ec8@xen.org>

On Wed, Aug 20, 2025 at 10:33:16PM +0100, Julien Grall wrote:
> Hi Denis,
> 
> On 12/08/2025 23:30, dmkhn@proton.me wrote:
> > From: Denis Mukhin 
> >
> > Currently, there are two different domain ID allocation implementations:
> >
> >    1) Sequential IDs allocation in dom0less Arm code based on max_init_domid;
> >
> >    2) Sequential IDs allocation in XEN_DOMCTL_createdomain; does not use
> >       max_init_domid (both Arm and x86).
> >
> > The domain ID allocation covers dom0 or late hwdom, predefined domains,
> > post-boot domains, excluding Xen system domains (domid >=
> > DOMID_FIRST_RESERVED).
> >
> > It makes sense to have a common helper code for such task across architectures
> > (Arm and x86) and between dom0less / toolstack domU allocation.
> >
> > Note, fixing dependency on max_init_domid is out of scope of this patch.
> >
> > Wrap the domain ID allocation as an arch-independent function domid_alloc() in
> > new common/domid.c based on the bitmap.
> >
> > Allocation algorithm:
> > - If an explicit domain ID is provided, verify its availability and use it if
> >    ID is not used;
> > - If DOMID_INVALID is provided, search the range [1..DOMID_FIRST_RESERVED-1],
> >    starting from the last used ID.
> >    Implementation guarantees that two consecutive calls will never return the
> >    same ID. ID#0 is reserved for the first boot domain (currently, dom0) and
> >    excluded from the allocation range.
> >
> > Remove is_free_domid() helper as it is not needed now.
> >
> > No functional change intended.
> >
> > Signed-off-by: Denis Mukhin 
> > Reviewed-by: Julien Grall 
>  > Reviewed-by: Alejandro Vallejo 
>  > ---> Changes since v15:
> > - fixup for check after the first pass in the bitarray in domid_alloc()
> 
> This was a good catch from Jan. Has a unit-test been added for this issue?

So I looked into how to plumb the test.
The boundary conditions tests are there for IDs: 0, DOMID_FIRST_RESERVED-1,
DOMID_FIRST_RESERVED.

But to actually check that 

        domid_t bound = DOMID_FIRST_RESERVED;

        domid = find_next_zero_bit(domid_bitmap, bound, domid_last + 1);
        if ( domid >= bound ...

I need to write a test harness for bit manipulation and it is a project on its
own to make hypervisor's bitops compiled for the host...

> 
> Anyway, my reviewed-by holds.
> 
> Cheers,
> 
> --
> Julien Grall
> 


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From: Mykola Kvach 
Date: Sat, 30 Aug 2025 13:09:54 +0300
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Subject: Re: [PATCH v11 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
To: Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" , Mykola Kvach , 
	Stefano Stabellini , Julien Grall , 
	Bertrand Marquis , Michal Orzel , 
	Andrew Cooper , Anthony PERARD , 
	Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , 
	Shawn Anastasio , 
	Alistair Francis , Bob Eshleman , 
	Connor Davis , Oleksii Kurochko 
Content-Type: text/plain; charset="UTF-8"
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Hi Volodymyr,

On Thu, Aug 28, 2025 at 7:32=E2=80=AFPM Volodymyr Babchuk
 wrote:
>
>
> Hi Mykola,
>
> Mykola Kvach  writes:
>
> > From: Mykola Kvach 
> >
> > Add support for the PSCI SYSTEM_SUSPEND function in the vPSCI interface=
,
> > allowing guests to request suspend via the PSCI v1.0 SYSTEM_SUSPEND cal=
l
> > (both 32-bit and 64-bit variants).
> >
> > Implementation details:
> > - Add SYSTEM_SUSPEND function IDs to PSCI definitions
> > - Trap and handle SYSTEM_SUSPEND in vPSCI
> > - Allow only non-hardware domains to invoke SYSTEM_SUSPEND; return
> >   PSCI_NOT_SUPPORTED for the hardware domain to avoid halting the syste=
m
> >   in hwdom_shutdown() via domain_shutdown
> > - Require all secondary VCPUs of the calling domain to be offline befor=
e
> >   suspend, as mandated by the PSCI specification
> >
> > The arch_domain_resume() function is an architecture-specific hook that=
 is
> > invoked during domain resume to perform any necessary setup or restorat=
ion
> > steps required by the platform.
> >
> > The new vpsci_vcpu_up_prepare() helper is called on the resume path to =
set up
> > the vCPU context (such as entry point, some system regs and context ID)=
 before
> > resuming a suspended guest. This keeps ARM/vPSCI-specific logic out of =
common
> > code and avoids intrusive changes to the generic resume flow.
> >
> > Usage:
> >
> > For Linux-based guests, suspend can be initiated with:
> >     echo mem > /sys/power/state
> > or via:
> >     systemctl suspend
> >
> > Resuming the guest is performed from control domain using:
> >       xl resume 
> >
> > Signed-off-by: Mykola Kvach 
>
> Reviewed-by: Volodymyr Babchuk 
>
> But check a small comment below
>
> > ---
> > Changes in V11:
> > - introduce arch_domain_resume() and vpsci_vcpu_up_prepare(), which are=
 now
> > called on the resume path to avoid extra modifications to common code.
> > The vCPU context is now updated during domain resume.
> >
> > Changes in V10:
> > - small changes to the commit message reflect updates introduced in thi=
s
> >   version of the patch.
> > - Comments are improved, clarified, and expanded, especially regarding =
PSCI
> >   requirements and context handling.
> > - An ARM-specific helper (domain_resume_nopause_helper)
> > - gprintk() and PRIregister are used for logging in vPSCI code.
> > - An isb() is added before p2m_save_state
> > - The is_64bit_domain check is dropped when masking the upper part of e=
ntry
> >   point and cid for SMC32 SYSTEM_SUSPEND PSCI calls
> >
> > Changes in V9:
> > - no functional changes
> > - cosmetic chnages after review
> > - enhance commit message and add extra comment to the code after review
> >
> > Changes in V8:
> > - GIC and virtual timer context must be saved when the domain suspends
> > - rework locking
> > - minor changes after code review
> >
> > Changes in V7:
> > - add proper locking
> > - minor changes after code review
> >
> > Changes in V6:
> > - skip execution of ctxt_switch_from for vcpu that is in paused domain
> > - add implementation of domain_resume without domain_pause
> > - add helper function to determine if vcpu is suspended or not
> > - ignore upper 32 bits of argument values when the domain is 64-bit
> >   and calls the SMC32 SYSTEM_SUSPEND function
> > - cosmetic changes after review
> >
> > Changes in V5:
> > - don't use standby mode, restore execution in a provided by guest poin=
t
> > - move checking that all CPUs, except current one, are offline to after
> >   pausing the vCPUs
> > - provide ret status from arch_domain_shutdown and handle it in
> >   domain_shutdown
> > - adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI funct=
ions
> >
> > Changes in V4:
> > Dropped all changes related to watchdog, domain is marked as shutting
> > down in domain_shutdown and watchdog timeout handler won't trigger
> > because of it.
> >
> > Previous versions included code to manage Xen watchdog timers during su=
spend,
> > but this was removed. When a guest OS starts the Xen watchdog (either v=
ia the
> > kernel driver or xenwatchdogd), it is responsible for managing that sta=
te
> > across suspend/resume. On Linux, the Xen kernel driver properly stops t=
he
> > watchdog during suspend. However, when xenwatchdogd is used instead, su=
spend
> > handling is incomplete, potentially leading to watchdog-triggered reset=
s on
> > resume. Xen leaves watchdog handling to the guest OS and its services.
> >
> > Dropped all changes related to VCPU context, because instead domain_shu=
tdown
> > is used, so we don't need any extra changes for suspending domain.
> >
> > Changes in V3:
> > Dropped all domain flags and related code (which touched common functio=
ns like
> > vcpu_unblock), keeping only the necessary changes for Xen suspend/resum=
e, i.e.
> > suspend/resume is now fully supported only for the hardware domain.
> > Proper support for domU suspend/resume will be added in a future patch.
> > This patch does not yet include VCPU context reset or domain context
> > restoration in VCPU.
> > ---
> >  xen/arch/arm/domain.c                 |  22 +++++
> >  xen/arch/arm/include/asm/domain.h     |   6 ++
> >  xen/arch/arm/include/asm/perfc_defn.h |   1 +
> >  xen/arch/arm/include/asm/psci.h       |   2 +
> >  xen/arch/arm/include/asm/vpsci.h      |   5 +-
> >  xen/arch/arm/vpsci.c                  | 114 +++++++++++++++++++++-----
> >  xen/arch/ppc/stubs.c                  |   5 ++
> >  xen/arch/riscv/stubs.c                |   5 ++
> >  xen/arch/x86/domain.c                 |   5 ++
> >  xen/common/domain.c                   |   9 ++
> >  xen/include/xen/domain.h              |   2 +
> >  11 files changed, 156 insertions(+), 20 deletions(-)
> >
> > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> > index 863ae18157..6fd73eedde 100644
> > --- a/xen/arch/arm/domain.c
> > +++ b/xen/arch/arm/domain.c
> > @@ -12,6 +12,8 @@
> >  #include 
> >  #include 
> >
> > +#include 
> > +
> >  #include 
> >  #include 
> >  #include 
> > @@ -27,6 +29,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >
> >  #include "vpci.h"
> > @@ -880,6 +883,25 @@ void arch_domain_creation_finished(struct domain *=
d)
> >      p2m_domain_creation_finished(d);
> >  }
> >
> > +int arch_domain_resume(struct domain *d)
> > +{
> > +    int rc;
> > +    typeof(d->arch.resume_ctx) *ctx =3D &d->arch.resume_ctx;
> > +
> > +    if ( !d->is_shutting_down || d->shutdown_code !=3D SHUTDOWN_suspen=
d )
> > +    {
> > +        dprintk(XENLOG_WARNING,
> > +                "%pd: Invalid domain state for resume: is_shutting_dow=
n=3D%d, shutdown_code=3D%d\n",
> > +                d, d->is_shutting_down, d->shutdown_code);
> > +        return -EINVAL;
> > +    }
>
> This check probably can go into common domain_resume() function, as
> there is nothing arch-specific in here. Probably this can be done during
> commit, to save us from v12? If commiters are okay with this.

It is more complicated than I expected, because this function is also used
for the "soft-reset" action (see domain_soft_reset). Currently, it may only
be called in the x86 case, but as I understand it, almost for any event an
action can be rewritten:
https://xenbits.xen.org/docs/unstable/man/xl.cfg.5.html#Event-Actions.

It also appears that domain_resume() is used to clean up state after
domain_shutdown(). So, if I simply add a condition to check for a specific
shutdown_code, it could break the "soft-reset" functionality.

This needs a deeper investigation. I propose to leave this check inside
arch_domain_resume() for now.

>
> > +
> > +    rc =3D vpsci_vcpu_up_prepare(ctx->wake_cpu , ctx->ep, ctx->cid);
> > +    memset(ctx, 0, sizeof(*ctx));
> > +
> > +    return rc;
> > +}
> > +
> >  static int is_guest_pv32_psr(uint32_t psr)
> >  {
> >      switch (psr & PSR_MODE_MASK)
> > diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/a=
sm/domain.h
> > index a3487ca713..68185fc4d6 100644
> > --- a/xen/arch/arm/include/asm/domain.h
> > +++ b/xen/arch/arm/include/asm/domain.h
> > @@ -121,6 +121,12 @@ struct arch_domain
> >      void *tee;
> >  #endif
> >
> > +    struct resume_info {
> > +        register_t ep;
> > +        register_t cid;
> > +        struct vcpu *wake_cpu;
> > +    } resume_ctx;
> > +
> >  }  __cacheline_aligned;
> >
> >  struct arch_vcpu
> > diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/inclu=
de/asm/perfc_defn.h
> > index effd25b69e..8dfcac7e3b 100644
> > --- a/xen/arch/arm/include/asm/perfc_defn.h
> > +++ b/xen/arch/arm/include/asm/perfc_defn.h
> > @@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system=
_reset")
> >  PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
> >  PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
> >  PERFCOUNTER(vpsci_features,            "vpsci: features")
> > +PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
> >
> >  PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
> >
> > diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm=
/psci.h
> > index 4780972621..48a93e6b79 100644
> > --- a/xen/arch/arm/include/asm/psci.h
> > +++ b/xen/arch/arm/include/asm/psci.h
> > @@ -47,10 +47,12 @@ void call_psci_system_reset(void);
> >  #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
> >  #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
> >  #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
> > +#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
> >
> >  #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
> >  #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
> >  #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
> > +#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
> >
> >  /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
> >  #define PSCI_0_2_AFFINITY_LEVEL_ON      0
> > diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/as=
m/vpsci.h
> > index 0cca5e6830..d790ab3715 100644
> > --- a/xen/arch/arm/include/asm/vpsci.h
> > +++ b/xen/arch/arm/include/asm/vpsci.h
> > @@ -23,12 +23,15 @@
> >  #include 
> >
> >  /* Number of function implemented by virtual PSCI (only 0.2 or later) =
*/
> > -#define VPSCI_NR_FUNCS  12
> > +#define VPSCI_NR_FUNCS  14
> >
> >  /* Functions handle PSCI calls from the guests */
> >  bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
> >  bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid);
> >
> > +int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
> > +                          register_t context_id);
> > +
> >  #endif /* __ASM_VPSCI_H__ */
> >
> >  /*
> > diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
> > index 7ba9ccd94b..50cf5fd96c 100644
> > --- a/xen/arch/arm/vpsci.c
> > +++ b/xen/arch/arm/vpsci.c
> > @@ -10,30 +10,16 @@
> >
> >  #include 
> >
> > -static int do_common_cpu_on(register_t target_cpu, register_t entry_po=
int,
> > -                            register_t context_id)
> > +int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
> > +                   register_t context_id)
> >  {
> > -    struct vcpu *v;
> > -    struct domain *d =3D current->domain;
> > -    struct vcpu_guest_context *ctxt;
> >      int rc;
> > +    struct domain *d =3D current->domain;
> >      bool is_thumb =3D entry_point & 1;
> > -    register_t vcpuid;
> > -
> > -    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> > -
> > -    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> > -        return PSCI_INVALID_PARAMETERS;
> > -
> > -    /* THUMB set is not allowed with 64-bit domain */
> > -    if ( is_64bit_domain(d) && is_thumb )
> > -        return PSCI_INVALID_ADDRESS;
> > -
> > -    if ( !test_bit(_VPF_down, &v->pause_flags) )
> > -        return PSCI_ALREADY_ON;
> > +    struct vcpu_guest_context *ctxt;
> >
> >      if ( (ctxt =3D alloc_vcpu_guest_context()) =3D=3D NULL )
> > -        return PSCI_DENIED;
> > +        return -ENOMEM;
> >
> >      vgic_clear_pending_irqs(v);
> >
> > @@ -76,8 +62,37 @@ static int do_common_cpu_on(register_t target_cpu, r=
egister_t entry_point,
> >      free_vcpu_guest_context(ctxt);
> >
> >      if ( rc < 0 )
> > +        return rc;
> > +
> > +    return 0;
> > +}
> > +
> > +static int do_common_cpu_on(register_t target_cpu, register_t entry_po=
int,
> > +                            register_t context_id)
> > +{
> > +    struct vcpu *v;
> > +    struct domain *d =3D current->domain;
> > +    int rc;
> > +    bool is_thumb =3D entry_point & 1;
> > +    register_t vcpuid;
> > +
> > +    vcpuid =3D vaffinity_to_vcpuid(target_cpu);
> > +
> > +    if ( (v =3D domain_vcpu(d, vcpuid)) =3D=3D NULL )
> > +        return PSCI_INVALID_PARAMETERS;
> > +
> > +    /* THUMB set is not allowed with 64-bit domain */
> > +    if ( is_64bit_domain(d) && is_thumb )
> > +        return PSCI_INVALID_ADDRESS;
> > +
> > +    if ( !test_bit(_VPF_down, &v->pause_flags) )
> > +        return PSCI_ALREADY_ON;
> > +
> > +    rc =3D vpsci_vcpu_up_prepare(v, entry_point, context_id);
> > +    if ( rc )
> >          return PSCI_DENIED;
> >
> > +    vgic_clear_pending_irqs(v);
> >      vcpu_wake(v);
> >
> >      return PSCI_SUCCESS;
> > @@ -197,6 +212,48 @@ static void do_psci_0_2_system_reset(void)
> >      domain_shutdown(d,SHUTDOWN_reboot);
> >  }
> >
> > +static int32_t do_psci_1_0_system_suspend(register_t epoint, register_=
t cid)
> > +{
> > +    int32_t rc;
> > +    struct vcpu *v;
> > +    struct domain *d =3D current->domain;
> > +    bool is_thumb =3D epoint & 1;
> > +
> > +    /* THUMB set is not allowed with 64-bit domain */
> > +    if ( is_64bit_domain(d) && is_thumb )
> > +        return PSCI_INVALID_ADDRESS;
> > +
> > +    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
> > +    if ( is_hardware_domain(d) )
> > +        return PSCI_NOT_SUPPORTED;
> > +
> > +    /* Ensure that all CPUs other than the calling one are offline */
> > +    domain_lock(d);
> > +    for_each_vcpu ( d, v )
> > +    {
> > +        if ( v !=3D current && is_vcpu_online(v) )
> > +        {
> > +            domain_unlock(d);
> > +            return PSCI_DENIED;
> > +        }
> > +    }
> > +    domain_unlock(d);
> > +
> > +    rc =3D domain_shutdown(d, SHUTDOWN_suspend);
> > +    if ( rc )
> > +        return PSCI_DENIED;
> > +
> > +    d->arch.resume_ctx.ep =3D epoint;
> > +    d->arch.resume_ctx.cid =3D cid;
> > +    d->arch.resume_ctx.wake_cpu =3D current;
> > +
> > +    gprintk(XENLOG_DEBUG,
> > +            "SYSTEM_SUSPEND requested, epoint=3D0x%"PRIregister", cid=
=3D0x%"PRIregister,
> > +            epoint, cid);
> > +
> > +    return rc;
> > +}
> > +
> >  static int32_t do_psci_1_0_features(uint32_t psci_func_id)
> >  {
> >      /* /!\ Ordered by function ID and not name */
> > @@ -214,6 +271,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_f=
unc_id)
> >      case PSCI_0_2_FN32_SYSTEM_OFF:
> >      case PSCI_0_2_FN32_SYSTEM_RESET:
> >      case PSCI_1_0_FN32_PSCI_FEATURES:
> > +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> > +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> >      case ARM_SMCCC_VERSION_FID:
> >          return 0;
> >      default:
> > @@ -344,6 +403,23 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs,=
 uint32_t fid)
> >          return true;
> >      }
> >
> > +    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
> > +    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
> > +    {
> > +        register_t epoint =3D PSCI_ARG(regs, 1);
> > +        register_t cid =3D PSCI_ARG(regs, 2);
> > +
> > +        if ( fid =3D=3D PSCI_1_0_FN32_SYSTEM_SUSPEND )
> > +        {
> > +            epoint &=3D GENMASK(31, 0);
> > +            cid &=3D GENMASK(31, 0);
> > +        }
> > +
> > +        perfc_incr(vpsci_system_suspend);
> > +        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid))=
;
> > +        return true;
> > +    }
> > +
> >      default:
> >          return false;
> >      }
> > diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c
> > index bdaf474c5c..0db0627b5c 100644
> > --- a/xen/arch/ppc/stubs.c
> > +++ b/xen/arch/ppc/stubs.c
> > @@ -224,6 +224,11 @@ void arch_domain_creation_finished(struct domain *=
d)
> >      BUG_ON("unimplemented");
> >  }
> >
> > +int arch_domain_resume(struct domain *d)
> > +{
> > +    return 0;
> > +}
> > +
> >  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
> >  {
> >      BUG_ON("unimplemented");
> > diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c
> > index 1a8c86cd8d..52532ae14d 100644
> > --- a/xen/arch/riscv/stubs.c
> > +++ b/xen/arch/riscv/stubs.c
> > @@ -198,6 +198,11 @@ void arch_domain_creation_finished(struct domain *=
d)
> >      BUG_ON("unimplemented");
> >  }
> >
> > +int arch_domain_resume(struct domain *d)
> > +{
> > +    return 0;
> > +}
> > +
> >  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
> >  {
> >      BUG_ON("unimplemented");
> > diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
> > index 19fd86ce88..94a06bc697 100644
> > --- a/xen/arch/x86/domain.c
> > +++ b/xen/arch/x86/domain.c
> > @@ -1138,6 +1138,11 @@ void arch_domain_creation_finished(struct domain=
 *d)
> >          hvm_domain_creation_finished(d);
> >  }
> >
> > +int arch_domain_resume(struct domain *d)
> > +{
> > +    return 0;
> > +}
> > +
> >  #ifdef CONFIG_COMPAT
> >  #define xen_vcpu_guest_context vcpu_guest_context
> >  #define fpu_ctxt fpu_ctxt.x
> > diff --git a/xen/common/domain.c b/xen/common/domain.c
> > index 104e917f07..d73a88ced5 100644
> > --- a/xen/common/domain.c
> > +++ b/xen/common/domain.c
> > @@ -1352,6 +1352,7 @@ int domain_shutdown(struct domain *d, u8 reason)
> >  void domain_resume(struct domain *d)
> >  {
> >      struct vcpu *v;
> > +    int rc;
> >
> >      /*
> >       * Some code paths assume that shutdown status does not get reset =
under
> > @@ -1359,6 +1360,14 @@ void domain_resume(struct domain *d)
> >       */
> >      domain_pause(d);
> >
> > +    rc =3D arch_domain_resume(d);
> > +    if ( rc )
> > +    {
> > +        domain_unpause(d);
> > +        printk("%pd: Failed to resume domain (ret %d)\n", d, rc);
> > +        return;
> > +    }
> > +
> >      spin_lock(&d->shutdown_lock);
> >
> >      d->is_shutting_down =3D d->is_shut_down =3D 0;
> > diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
> > index e10baf2615..5f77ffadf1 100644
> > --- a/xen/include/xen/domain.h
> > +++ b/xen/include/xen/domain.h
> > @@ -109,6 +109,8 @@ int arch_domain_soft_reset(struct domain *d);
> >
> >  void arch_domain_creation_finished(struct domain *d);
> >
> > +int arch_domain_resume(struct domain *d);
> > +
> >  void arch_p2m_set_access_required(struct domain *d, bool access_requir=
ed);
> >
> >  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c);
>
> --
> WBR, Volodymyr

Best regards,
Mykola


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Date: Sat, 30 Aug 2025 16:03:51 +0300
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Subject: Re: [PATCH v6 4/4] docs: arm: add docs for SCMI over SMC calls
 forwarding driver
To: Oleksii Moisieiev ,
 "xen-devel@lists.xenproject.org" 
Cc: Andrew Cooper ,
 Anthony PERARD ,
 Bertrand Marquis , Jan Beulich
 , Juergen Gross ,
 Julien Grall , Michal Orzel ,
 =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= ,
 Stefano Stabellini ,
 Volodymyr Babchuk ,
 Grygorii Strashko 
References: 
 <17e009a131e54ad68f0a182b1766d333cf1c63f8.1756399156.git.oleksii_moisieiev@epam.com>
Content-Language: en-US
From: Oleksandr Tyshchenko 
In-Reply-To: <17e009a131e54ad68f0a182b1766d333cf1c63f8.1756399156.git.oleksii_moisieiev@epam.com>
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On 28.08.25 19:40, Oleksii Moisieiev wrote:

Hello Oleksii

the patch lgtm, just some NITs

> From: Grygorii Strashko 
> 
> Add documentation section for Simple Arm SCMI over SMC calls forwarding
> driver (EL3).
> 
> Signed-off-by: Grygorii Strashko 
> Signed-off-by: Oleksii Moisieiev 
> ---
> 
> Changes in v6:
> - add link to the scmi bindings used in the doc
> - remove mentions about HVC calls from doc
> - rename cmdline parameter to scmi-smc-passthrough
> 
> Changes in v5:
> - rename dom0_scmi_smc_passthrough in documentation
> 
>   .../arm/firmware/arm-scmi.rst                 | 180 ++++++++++++++++++
>   docs/hypervisor-guide/arm/index.rst           |   9 +
>   docs/hypervisor-guide/index.rst               |   1 +
>   3 files changed, 190 insertions(+)
>   create mode 100644 docs/hypervisor-guide/arm/firmware/arm-scmi.rst
>   create mode 100644 docs/hypervisor-guide/arm/index.rst
> 
> diff --git a/docs/hypervisor-guide/arm/firmware/arm-scmi.rst b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> new file mode 100644
> index 0000000000..4394c95431
> --- /dev/null
> +++ b/docs/hypervisor-guide/arm/firmware/arm-scmi.rst
> @@ -0,0 +1,180 @@
> +.. SPDX-License-Identifier: CC-BY-4.0
> +
> +ARM System Control and Management Interface (SCMI)
> +==================================================
> +
> +The System Control and Management Interface (SCMI) [1], which is a set of operating
> +system-independent software interfaces that are used in system management. SCMI currently
> +provides interfaces for:
> +
> +- Discovery and self-description of the interfaces it supports
> +- Power domain management
> +- Clock management
> +- Reset domain management
> +- Voltage domain management
> +- Sensor management
> +- Performance management
> +- Power capping and monitoring
> +- Pin control protocol.
> +
> +The SCMI compliant firmware could run:
> +
> +- as part of EL3 secure world software (like Trusted Firmware-A) with
> +  ARM SMC shared-memory transport;
> +- on dedicated System Control Processor (SCP) with HW mailbox shared-memory transport
> +
> +The major purpose of enabling SCMI support in Xen is to enable guest domains access to the SCMI
> +interfaces for performing management actions on passed-through devices (such as clocks/resets etc)
> +without accessing directly to the System control HW (like clock controllers) which in most cases
> +can't shared/split between domains. Or, at minimum, allow SCMI access for dom0/hwdom (or guest

NIT: can't be shared

> +domain serving as Driver domain).
> +
> +The below sections describe SCMI support options available for Xen.
> +
> +| [1] `Arm SCMI `_
> +| [2] `System Control and Management Interface (SCMI) bindings `_
> +
> +Simple SCMI over SMC calls forwarding driver (EL3)
> +------------------------------------------------------
> +
> +The EL3 SCMI firmware (TF-A) with a single SCMI OSPM agent support is pretty generic case for
> +the default vendors SDK and new platforms with SCMI support. Such EL3 SCMI firmware supports only
> +single SCMI OSPM transport (agent) with Shared memory based transport and SMC calls as doorbell.
> +
> +The SCMI over SMC calls forwarding driver solves major problem for this case by allowing
> +SMC calls to be forwarded form guest to the EL3 SCMI firmware.


NIT: s/form/from

> +
> +By default, the SCMI over SMC calls forwarding is enabled for Dom0/hwdom.
> +
> +::
> +
> +    +--------------------------+
> +    |                          |
> +    | EL3 SCMI FW (TF-A)       |
> +    ++-------+--^--------------+
> +     |shmem  |  | smc-id
> +     +----^--+  |
> +          |     |
> +     +----|-+---+---+----------+
> +     |    | |  FWD  |      Xen |
> +     |    | +---^---+          |
> +     +----|-----|--------------+
> +          |     | smc-id
> +     +----v-----+--+ +---------+
> +     |             | |         |
> +     | Dom0/hwdom  | | DomU    |
> +     |             | |         |
> +     |             | |         |
> +     +-------------+ +---------+
> +
> +
> +The SCMI messages are passed directly through SCMI shared-memory (zero-copy) and driver only
> +forwards SMC calls.
> +
> +Compiling
> +^^^^^^^^^
> +
> +To build with the SCMI over SMC calls forwarding enabled support, enable Kconfig option
> +
> +::
> +
> +    CONFIG_SCMI_SMC

NIT: I think, if we mention Kconfig option, then s/CONFIG_SCMI_SMC/SCMI_SMC

> +
> +The ``CONFIG_SCMI_SMC`` is enabled by default.
> +
> +Pass-through SCMI SMC to domain which serves as Driver domain
> +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> +
> +This section describes how to configure the SCMI over SMC calls forwarding driver to handle use
> +case "thin Dom0 with guest domain, which serves as Driver domain". In this case HW need to be
> +enabled in Driver domain and dom0 is performing only control functions (without accessing FW) and so,
> +the SCMI need to be enabled in Driver domain.
> +
> +::
> +
> +     +--------------------------+
> +     |EL3 SCMI FW (TF-A)        |
> +     |                          |
> +     +-------------^--+-------+-+
> +             smc-id|  |shmem0 |
> +                   |  +----^--+
> +    +-------------++------+|----+
> +    |Xen          |  FWD  ||    |
> +    |             +--^----+|    |
> +    +----------------|-----|----+
> +              smc-id |     |
> +    +-----------+ +--+-----v-----+
> +    |           | |              |
> +    | Dom0      | |    Driver    |
> +    | Control   | |    domain    |
> +    |           | |              |
> +    +-----------+ +--------------+
> +
> +The SCMI can be enabled for one and only one guest domain.
> +
> +First. configure Dom0 to enable SCMI pass-through using Xen Command Line

NIT: First,

> +**"scmi-smc-passthrough"** option. This will disable SCMI for Dom0/hwdom and SCMI nodes will
> +be removed from Dom0/hwdom device tree.
> +
> +**Configure SCMI pass-through for guest domain with toolstack**
> +
> +* In domain's xl.cfg file add **"arm_sci"** option as below
> +
> +::
> +
> +    arm_sci = "type=scmi_smc"
> +
> +* In domain's xl.cfg file enable access to the "arm,scmi-shmem"
> +
> +::
> +
> +    iomem = [
> +        "47ff0,1@22001",
> +    ]
> +
> +.. note:: It's up to the user to select guest IPA for mapping SCMI shared-memory.
> +
> +* Add SCMI nodes to the Driver domain partial device tree as in the below example:
> +
> +.. code::
> +
> +    passthrough {
> +       scmi_shm_0: sram@22001000 {
> +           compatible = "arm,scmi-shmem";
> +           reg = <0x0 0x22001000 0x0 0x1000>;
> +       };
> +
> +       firmware {
> +            compatible = "simple-bus";
> +                scmi: scmi {
> +                    compatible = "arm,scmi-smc";
> +                    shmem = <&scmi_shm_0>;
> +                    ...
> +                }
> +        }
> +    }
> +
> +Please refer to [2] for details of SCMI DT bindings.
> +
> +In general, the configuration is similar to any other HW pass-through, except explicitly
> +enabling SCMI with "arm_sci" xl.cfg option.
> +
> +**Configure SCMI pass-through for predefined domain (dom0less)**
> +
> +* add "xen,sci_type" property for required DomU ("xen,domain") node
> +
> +::
> +
> +       xen,sci_type="scmi_smc"
> +
> +* add scmi nodes to the Driver domain partial device tree the same way as above and enable access
> +  to the "arm,scmi-shmem" according to  dom0less documentation. For example:
> +
> +.. code::
> +
> +      scmi_shm_0: sram@22001000 {
> +            compatible = "arm,scmi-shmem";
> +            reg = <0x00 0x22001000 0x00 0x1000>;
> +    ->        xen,reg = <0x0 0x47ff0000 0x0 0x1000 0x0 0x22001000>;
> +    ->        xen,force-assign-without-iommu;
> +      };

[snip]



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29.08.25 14:44, Jan Beulich:
> On 29.08.2025 13:33, Sergiy Kibrik wrote:
>> 25.08.25 15:00, Jan Beulich:
>>> On 22.08.2025 11:51, Sergiy Kibrik wrote:
>>>> --- a/xen/common/Kconfig
>>>> +++ b/xen/common/Kconfig
>>>
>>> I wonder whether we wouldn't better move XSM's controls to a dedicated Kconfig
>>> file there.
>>
>> you mean something like Kconfig.xsm in the same common/ directory? Or
>> move this Kconfig out into xsm/ directory with the rest of flask code?
> 
> The latter would be preferable imo.

then it probably will have to be moved outside Common Features menu and 
into the main configuration menu, while having 6-7 items. Is it ok to 
keep such small submenu for that?

  -Sergiy


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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Andrew Cooper ,
	Anthony PERARD ,
	Michal Orzel ,
	Jan Beulich ,
	Julien Grall ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Stefano Stabellini 
Subject: [PATCH v12 3/4] SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
Date: Sun, 31 Aug 2025 01:10:30 +0300
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From: Mykola Kvach 

Add a new entry under the "Virtual Hardware, QEMU" section documenting
support for the optional PSCI SYSTEM_SUSPEND function exposed to guests.

This function is available via the virtual PSCI (vPSCI) interface and
allows guest domains (domUs) to initiate system suspend operations.

The feature is currently marked as "Tech Preview".

Signed-off-by: Mykola Kvach 
---
Changes in V10:
- Status of vPSCI SYSTEM_SUSPEND changed from "Experimental" to
  "Tech Preview"

Changes in v6:
- Dropped the generic guest PSCI support entry (merged in a separate patch)
- This patch now documents only the SYSTEM_SUSPEND optional function
- Reworded commit message to match the final form after rebase

Changes in v5:
- Dropped ARM/PSCI entry: this refers to internal use of PSCI SMC calls,
  which is not relevant for SUPPORT.md
- Added a dedicated entry for PSCI SYSTEM_SUSPEND instead of generic guest
  PSCI info; guest PSCI support was documented in a separate patch
---
 SUPPORT.md | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/SUPPORT.md b/SUPPORT.md
index 6a82a92189..0ce0903cb1 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -962,8 +962,9 @@ Emulated PSCI interface exposed to guests. We support all mandatory
 functions of PSCI 1.1. See below for the list of optional PSCI call
 implemented and their status.
 
-   Status, Mandatory: Supported
-   Status, MIGRATE_INFO_TYPE: Supported
+    Status, Mandatory: Supported
+    Status, MIGRATE_INFO_TYPE: Supported
+    Status, SYSTEM_SUSPEND: Tech Preview
 
 ## Virtual Hardware, QEMU
 
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Anthony PERARD ,
	Juergen Gross 
Subject: [PATCH v12 2/4] tools/xl: Allow compilation of 'xl resume' command on Arm
Date: Sun, 31 Aug 2025 01:10:29 +0300
Message-ID: <6e7bc11b7d1b96e48c8211ca3d2e48c702d0b675.1756586648.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

The "xl resume" command was previously excluded from Arm builds because
system suspend/resume (e.g., SYSTEM_SUSPEND via vPSCI) was not
implemented. On x86, this command is used for resume.

This change enables compilation of `xl resume` on Arm regardless of the
underlying implementation status, making the tool available for testing
and future feature support. The relevant libxl infrastructure and handler
functions are already present and usable.

Note: This does not imply full system suspend/resume support on Arm.
      The `xl suspend` command still does not work on Arm platforms.

Signed-off-by: Mykola Kvach 
Acked-by: Anthony PERARD 
---
Changes in v7:
- dropped renaming of LIBXL_HAVE_NO_SUSPEND_RESUME macro

Changes in v6:
- Renamed macro from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND
  to better reflect the scope of this change
- Applied cosmetic changes based on review feedback
---
 tools/include/libxl.h     |  1 -
 tools/xl/xl.h             |  4 ++--
 tools/xl/xl_cmdtable.c    |  4 ++--
 tools/xl/xl_migrate.c     |  2 +-
 tools/xl/xl_saverestore.c |  2 +-
 tools/xl/xl_vmcontrol.c   | 12 ++++++------
 6 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/tools/include/libxl.h b/tools/include/libxl.h
index 185f74d8a8..b204fc5e2e 100644
--- a/tools/include/libxl.h
+++ b/tools/include/libxl.h
@@ -1140,7 +1140,6 @@ typedef struct libxl__ctx libxl_ctx;
  * restoring or migrating a domain. In this case the related functions
  * should be expected to return failure. That is:
  *  - libxl_domain_suspend
- *  - libxl_domain_resume
  *  - libxl_domain_remus_start
  */
 #if defined(__arm__) || defined(__aarch64__)
diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index 45745f0dbb..9233b73f85 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -65,7 +65,7 @@ static const char migrate_permission_to_go[]=
     "domain is yours, you are cleared to unpause";
 static const char migrate_report[]=
     "my copy unpause results are as follows";
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
   /* followed by one byte:
    *     0: everything went well, domain is running
@@ -130,8 +130,8 @@ int main_migrate_receive(int argc, char **argv);
 int main_save(int argc, char **argv);
 int main_migrate(int argc, char **argv);
 int main_suspend(int argc, char **argv);
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 int main_resume(int argc, char **argv);
-#endif
 int main_dump_core(int argc, char **argv);
 int main_pause(int argc, char **argv);
 int main_unpause(int argc, char **argv);
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 06a0039718..bcb2d233cc 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -198,12 +198,12 @@ const struct cmd_spec cmd_table[] = {
       "Suspend a domain to RAM",
       "",
     },
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "resume",
       &main_resume, 0, 1,
       "Resume a domain from RAM",
       "",
     },
-#endif
     { "dump-core",
       &main_dump_core, 0, 1,
       "Core dump a domain",
@@ -548,7 +548,7 @@ const struct cmd_spec cmd_table[] = {
       "                        checkpoint must be disabled.\n"
       "-p                      Use COLO userspace proxy."
     },
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
     { "devd",
       &main_devd, 0, 1,
       "Daemon that listens for devices and launches backends",
diff --git a/tools/xl/xl_migrate.c b/tools/xl/xl_migrate.c
index b8594f44a5..4b4a379aa1 100644
--- a/tools/xl/xl_migrate.c
+++ b/tools/xl/xl_migrate.c
@@ -767,7 +767,7 @@ int main_remus(int argc, char **argv)
     close(send_fd);
     return EXIT_FAILURE;
 }
-#endif
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 /*
diff --git a/tools/xl/xl_saverestore.c b/tools/xl/xl_saverestore.c
index 953d791d1a..747094ec7b 100644
--- a/tools/xl/xl_saverestore.c
+++ b/tools/xl/xl_saverestore.c
@@ -270,7 +270,7 @@ int main_save(int argc, char **argv)
     return EXIT_SUCCESS;
 }
 
-#endif /* LIBXL_HAVE_NO_SUSPEND_RESUME */
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
 
 
 
diff --git a/tools/xl/xl_vmcontrol.c b/tools/xl/xl_vmcontrol.c
index c813732838..93766f631b 100644
--- a/tools/xl/xl_vmcontrol.c
+++ b/tools/xl/xl_vmcontrol.c
@@ -38,11 +38,6 @@ static void suspend_domain(uint32_t domid)
     libxl_domain_suspend_only(ctx, domid, NULL);
 }
 
-static void resume_domain(uint32_t domid)
-{
-    libxl_domain_resume(ctx, domid, 1, NULL);
-}
-
 int main_suspend(int argc, char **argv)
 {
     int opt;
@@ -55,6 +50,12 @@ int main_suspend(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
+#endif /* !LIBXL_HAVE_NO_SUSPEND_RESUME */
+
+static void resume_domain(uint32_t domid)
+{
+    libxl_domain_resume(ctx, domid, 1, NULL);
+}
 
 int main_resume(int argc, char **argv)
 {
@@ -68,7 +69,6 @@ int main_resume(int argc, char **argv)
 
     return EXIT_SUCCESS;
 }
-#endif
 
 static void pause_domain(uint32_t domid)
 {
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Shawn Anastasio ,
	Alistair Francis ,
	Bob Eshleman ,
	Connor Davis ,
	Oleksii Kurochko ,
	Juergen Gross ,
	Community Manager 
Subject: [PATCH v12 0/4] Enable guest suspend/resume support on ARM via vPSCI
Date: Sun, 31 Aug 2025 01:10:27 +0300
Message-ID: 
X-Mailer: git-send-email 2.48.1
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From: Mykola Kvach 

This patch series introduces the initial support for guest suspend
and resume on ARM platforms using the PSCI SYSTEM_SUSPEND interface. The main
goal is to allow ARM guests to request suspension using PSCI and be resumed
by the control domain (e.g., via "xl resume").

### Background

The PSCI SYSTEM_SUSPEND call is part of the PSCI v1.0+ specification and is
used by guests to enter the deepest possible power state. On Xen/ARM, we
emulate this interface in the virtual PSCI (vPSCI) layer for guests.

This series includes:

1. A new vPSCI implementation of the PSCI SYSTEM_SUSPEND function for guests
2. Documentation updates to SUPPORT.md to reflect PSCI and vPSCI support status
3. Enabling "xl resume" command compilation for ARM, which was previously disabled

### Usage

For Linux-based guests:
  - Suspend can be triggered using: "echo mem > /sys/power/state" or "systemctl suspend"
  - Resume can be performed from control domain using: "xl resume "

For more information, refer to the official Linux kernel documentation on power management.

Note that currently, SYSTEM_SUSPEND is supported only for guest domains (not for
the hardware domain).
---

This is the first part of previous patch series and originally consist only
with necessary changes needed for guest domain suspend.

The second part can be found here:
    https://patchew.org/Xen/cover.1754943874.git.mykola._5Fkvach@epam.com/
---

Changes in v12:
- Use the input vCPU from vpsci_vcpu_up_prepare function argument instead of current.
- Add a check for the wake_cpu pointer on resume.
- Call arch_domain_resume() under shutdown_lock.
- Drop redundant vgic_clear_pending_irqs() call from vpsci_vcpu_up_prepare().

Changes in V11:
- introduce arch_domain_resume() and vpsci_vcpu_up_prepare(), which are now
called on the resume path to avoid extra modifications to common code.
The vCPU context is now updated during domain resume.

Changes in V10:
- An ARM-specific helper (domain_resume_nopause_helper)
- An isb() is added before p2m_save_state
- The is_64bit_domain check is dropped when masking the upper part of entry
  point and cid for SMC32 SYSTEM_SUSPEND PSCI calls
- Status of vPSCI SYSTEM_SUSPEND changed from "Experimental" to "Tech Preview"

Changes in V9:
- no functional changes
- enhance commit message and add extra comment to the code after review

Changes in V8:
- GIC and virtual timer context saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Main changes in V6:
- Skip execution of ctxt_switch_from for VCPUs in paused domains.
- Implement domain_resume_nopause
- Add a helper to determine if a VCPU is in suspended domain.
- Ignore upper 32 bits of arguments for 64-bit domains calling SMC32 SYSTEM_SUSPEND.
- Macro renamed from LIBXL_HAVE_NO_SUSPEND_RESUME to LIBXL_HAVE_NO_SUSPEND for clarity.
- Documentation now focuses only on the SYSTEM_SUSPEND function, with improved wording and structure.
- Changelog and commit messages refined for clarity and to remove redundant explanations.

Main change in V5:
  - Reverted the logic related to suspending domains. Instead of the standby
    mode introduced in v4, domains now resume execution at the point provided
    during suspend

The rest of the minor changes are described in the changelog of each commit.

Previous versions of this patch series:
  V1: https://lists.xenproject.org/archives/html/xen-devel/2018-11/msg01093.html
  V2: https://marc.info/?l=xen-devel&m=166514782207736&w=2
  V3: https://lists.xenproject.org/archives/html/xen-devel/2025-03/msg00168.html

Mykola Kvach (4):
  xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
  tools/xl: Allow compilation of 'xl resume' command on Arm
  SUPPORT.md: Document PSCI SYSTEM_SUSPEND support for guests
  CHANGELOG: Document guest suspend/resume to RAM support on Arm

 CHANGELOG.md                          |   2 +
 SUPPORT.md                            |   5 +-
 tools/include/libxl.h                 |   1 -
 tools/xl/xl.h                         |   4 +-
 tools/xl/xl_cmdtable.c                |   4 +-
 tools/xl/xl_migrate.c                 |   2 +-
 tools/xl/xl_saverestore.c             |   2 +-
 tools/xl/xl_vmcontrol.c               |  12 +--
 xen/arch/arm/domain.c                 |  37 ++++++++
 xen/arch/arm/include/asm/domain.h     |   6 ++
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   5 +-
 xen/arch/arm/vpsci.c                  | 116 +++++++++++++++++++++-----
 xen/arch/ppc/stubs.c                  |   5 ++
 xen/arch/riscv/stubs.c                |   5 ++
 xen/arch/x86/domain.c                 |   5 ++
 xen/common/domain.c                   |   9 ++
 xen/include/xen/domain.h              |   2 +
 19 files changed, 188 insertions(+), 37 deletions(-)

-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Oleksii Kurochko ,
	Community Manager 
Subject: [PATCH v12 4/4] CHANGELOG: Document guest suspend/resume to RAM support on Arm
Date: Sun, 31 Aug 2025 01:10:31 +0300
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From: Mykola Kvach 

Mention the newly added support for guest suspend and resume to/from
RAM via vPSCI on Arm platforms.

This support is limited to non-hardware domain guests.

Signed-off-by: Mykola Kvach 
Acked-by: Oleksii Kurochko 
---
Chnages in v6:
- removed reduntand explanation that thi support added for
  both arm32 and arm64.

Changes in v5:
- adjustments to the commit title and message
- expanded the changelog entry to include more context about
  suspend/resume support introduced in this patch series
---
 CHANGELOG.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index cd34ea87b8..7a75bd37cb 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -36,6 +36,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
 
  - On Arm:
     - Ability to enable stack protector
+    - Support for guest suspend and resume to/from RAM via vPSCI.
+      Applies only to non-hardware domain guests.
 
 ### Removed
  - On x86:
-- 
2.48.1



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From: Mykola Kvach 
To: xen-devel@lists.xenproject.org
Cc: Mykola Kvach ,
	Stefano Stabellini ,
	Julien Grall ,
	Bertrand Marquis ,
	Michal Orzel ,
	Volodymyr Babchuk ,
	Andrew Cooper ,
	Anthony PERARD ,
	Jan Beulich ,
	=?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= ,
	Shawn Anastasio ,
	Alistair Francis ,
	Bob Eshleman ,
	Connor Davis ,
	Oleksii Kurochko 
Subject: [PATCH v12 1/4] xen/arm: Implement PSCI SYSTEM_SUSPEND call for guests
Date: Sun, 31 Aug 2025 01:10:28 +0300
Message-ID: <244e5c2bcebad9563595ac7564ffa105d5f568d3.1756586648.git.mykola_kvach@epam.com>
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From: Mykola Kvach 

Add support for the PSCI SYSTEM_SUSPEND function in the vPSCI interface,
allowing guests to request suspend via the PSCI v1.0 SYSTEM_SUSPEND call
(both 32-bit and 64-bit variants).

Implementation details:
- Add SYSTEM_SUSPEND function IDs to PSCI definitions
- Trap and handle SYSTEM_SUSPEND in vPSCI
- Allow only non-hardware domains to invoke SYSTEM_SUSPEND; return
  PSCI_NOT_SUPPORTED for the hardware domain to avoid halting the system
  in hwdom_shutdown() via domain_shutdown
- Require all secondary VCPUs of the calling domain to be offline before
  suspend, as mandated by the PSCI specification

The arch_domain_resume() function is an architecture-specific hook that is
invoked during domain resume to perform any necessary setup or restoration
steps required by the platform.

The new vpsci_vcpu_up_prepare() helper is called on the resume path to set up
the vCPU context (such as entry point, some system regs and context ID) before
resuming a suspended guest. This keeps ARM/vPSCI-specific logic out of common
code and avoids intrusive changes to the generic resume flow.

Usage:

For Linux-based guests, suspend can be initiated with:
    echo mem > /sys/power/state
or via:
    systemctl suspend

Resuming the guest is performed from control domain using:
      xl resume 

Signed-off-by: Mykola Kvach 
---
Changes in v12:
- Use the input vCPU from vpsci_vcpu_up_prepare function argument instead of current.
- Add a check for the wake_cpu pointer on resume.
- Call arch_domain_resume() under shutdown_lock.
- Drop redundant vgic_clear_pending_irqs() call from vpsci_vcpu_up_prepare().
- Cosmetic fixes.

Changes in V11:
- introduce arch_domain_resume() and vpsci_vcpu_up_prepare(), which are now
called on the resume path to avoid extra modifications to common code.
The vCPU context is now updated during domain resume.

Changes in V10:
- small changes to the commit message reflect updates introduced in this
  version of the patch.
- Comments are improved, clarified, and expanded, especially regarding PSCI
  requirements and context handling.
- An ARM-specific helper (domain_resume_nopause_helper)
- gprintk() and PRIregister are used for logging in vPSCI code.
- An isb() is added before p2m_save_state
- The is_64bit_domain check is dropped when masking the upper part of entry
  point and cid for SMC32 SYSTEM_SUSPEND PSCI calls

Changes in V9:
- no functional changes
- cosmetic chnages after review
- enhance commit message and add extra comment to the code after review

Changes in V8:
- GIC and virtual timer context must be saved when the domain suspends
- rework locking
- minor changes after code review

Changes in V7:
- add proper locking
- minor changes after code review

Changes in V6:
- skip execution of ctxt_switch_from for vcpu that is in paused domain
- add implementation of domain_resume without domain_pause
- add helper function to determine if vcpu is suspended or not
- ignore upper 32 bits of argument values when the domain is 64-bit
  and calls the SMC32 SYSTEM_SUSPEND function
- cosmetic changes after review

Changes in V5:
- don't use standby mode, restore execution in a provided by guest point
- move checking that all CPUs, except current one, are offline to after
  pausing the vCPUs
- provide ret status from arch_domain_shutdown and handle it in
  domain_shutdown
- adjust VPSCI_NR_FUNCS to reflect the number of newly added PSCI functions

Changes in V4:
Dropped all changes related to watchdog, domain is marked as shutting
down in domain_shutdown and watchdog timeout handler won't trigger
because of it.

Previous versions included code to manage Xen watchdog timers during suspend,
but this was removed. When a guest OS starts the Xen watchdog (either via the
kernel driver or xenwatchdogd), it is responsible for managing that state
across suspend/resume. On Linux, the Xen kernel driver properly stops the
watchdog during suspend. However, when xenwatchdogd is used instead, suspend
handling is incomplete, potentially leading to watchdog-triggered resets on
resume. Xen leaves watchdog handling to the guest OS and its services.

Dropped all changes related to VCPU context, because instead domain_shutdown
is used, so we don't need any extra changes for suspending domain.

Changes in V3:
Dropped all domain flags and related code (which touched common functions like
vcpu_unblock), keeping only the necessary changes for Xen suspend/resume, i.e.
suspend/resume is now fully supported only for the hardware domain.
Proper support for domU suspend/resume will be added in a future patch.
This patch does not yet include VCPU context reset or domain context
restoration in VCPU.
---
 xen/arch/arm/domain.c                 |  37 ++++++++
 xen/arch/arm/include/asm/domain.h     |   6 ++
 xen/arch/arm/include/asm/perfc_defn.h |   1 +
 xen/arch/arm/include/asm/psci.h       |   2 +
 xen/arch/arm/include/asm/vpsci.h      |   5 +-
 xen/arch/arm/vpsci.c                  | 116 +++++++++++++++++++++-----
 xen/arch/ppc/stubs.c                  |   5 ++
 xen/arch/riscv/stubs.c                |   5 ++
 xen/arch/x86/domain.c                 |   5 ++
 xen/common/domain.c                   |   9 ++
 xen/include/xen/domain.h              |   2 +
 11 files changed, 171 insertions(+), 22 deletions(-)

diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 863ae18157..7d7358abe5 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -12,6 +12,8 @@
 #include 
 #include 
 
+#include 
+
 #include 
 #include 
 #include 
@@ -27,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "vpci.h"
@@ -880,6 +883,40 @@ void arch_domain_creation_finished(struct domain *d)
     p2m_domain_creation_finished(d);
 }
 
+int arch_domain_resume(struct domain *d)
+{
+    int rc;
+    typeof(d->arch.resume_ctx) *ctx = &d->arch.resume_ctx;
+
+    if ( !d->is_shutting_down || d->shutdown_code != SHUTDOWN_suspend )
+    {
+        dprintk(XENLOG_WARNING,
+                "%pd: Invalid domain state for resume: is_shutting_down=%d, shutdown_code=%d\n",
+                d, d->is_shutting_down, d->shutdown_code);
+        return -EINVAL;
+    }
+
+    /*
+     * It is still possible to call domain_shutdown() with a suspend reason
+     * via some hypercalls, such as SCHEDOP_shutdown or SCHEDOP_remote_shutdown.
+     * In these cases, the resume context will be empty.
+     * This is not expected to cause any issues, so we just warn about the
+     * situation and return without error, allowing the existing logic to
+     * proceed as expected.
+     */
+    if ( !ctx->wake_cpu )
+    {
+        dprintk(XENLOG_WARNING, "%pd: Invalid wake CPU pointer for resume\n",
+                d);
+        return 0;
+    }
+
+    rc = vpsci_vcpu_up_prepare(ctx->wake_cpu , ctx->ep, ctx->cid);
+    memset(ctx, 0, sizeof(*ctx));
+
+    return rc;
+}
+
 static int is_guest_pv32_psr(uint32_t psr)
 {
     switch (psr & PSR_MODE_MASK)
diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
index a3487ca713..68185fc4d6 100644
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -121,6 +121,12 @@ struct arch_domain
     void *tee;
 #endif
 
+    struct resume_info {
+        register_t ep;
+        register_t cid;
+        struct vcpu *wake_cpu;
+    } resume_ctx;
+
 }  __cacheline_aligned;
 
 struct arch_vcpu
diff --git a/xen/arch/arm/include/asm/perfc_defn.h b/xen/arch/arm/include/asm/perfc_defn.h
index effd25b69e..8dfcac7e3b 100644
--- a/xen/arch/arm/include/asm/perfc_defn.h
+++ b/xen/arch/arm/include/asm/perfc_defn.h
@@ -33,6 +33,7 @@ PERFCOUNTER(vpsci_system_reset,        "vpsci: system_reset")
 PERFCOUNTER(vpsci_cpu_suspend,         "vpsci: cpu_suspend")
 PERFCOUNTER(vpsci_cpu_affinity_info,   "vpsci: cpu_affinity_info")
 PERFCOUNTER(vpsci_features,            "vpsci: features")
+PERFCOUNTER(vpsci_system_suspend,      "vpsci: system_suspend")
 
 PERFCOUNTER(vcpu_kick,                 "vcpu: notify other vcpu")
 
diff --git a/xen/arch/arm/include/asm/psci.h b/xen/arch/arm/include/asm/psci.h
index 4780972621..48a93e6b79 100644
--- a/xen/arch/arm/include/asm/psci.h
+++ b/xen/arch/arm/include/asm/psci.h
@@ -47,10 +47,12 @@ void call_psci_system_reset(void);
 #define PSCI_0_2_FN32_SYSTEM_OFF          PSCI_0_2_FN32(8)
 #define PSCI_0_2_FN32_SYSTEM_RESET        PSCI_0_2_FN32(9)
 #define PSCI_1_0_FN32_PSCI_FEATURES       PSCI_0_2_FN32(10)
+#define PSCI_1_0_FN32_SYSTEM_SUSPEND      PSCI_0_2_FN32(14)
 
 #define PSCI_0_2_FN64_CPU_SUSPEND         PSCI_0_2_FN64(1)
 #define PSCI_0_2_FN64_CPU_ON              PSCI_0_2_FN64(3)
 #define PSCI_0_2_FN64_AFFINITY_INFO       PSCI_0_2_FN64(4)
+#define PSCI_1_0_FN64_SYSTEM_SUSPEND      PSCI_0_2_FN64(14)
 
 /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
 #define PSCI_0_2_AFFINITY_LEVEL_ON      0
diff --git a/xen/arch/arm/include/asm/vpsci.h b/xen/arch/arm/include/asm/vpsci.h
index 0cca5e6830..d790ab3715 100644
--- a/xen/arch/arm/include/asm/vpsci.h
+++ b/xen/arch/arm/include/asm/vpsci.h
@@ -23,12 +23,15 @@
 #include 
 
 /* Number of function implemented by virtual PSCI (only 0.2 or later) */
-#define VPSCI_NR_FUNCS  12
+#define VPSCI_NR_FUNCS  14
 
 /* Functions handle PSCI calls from the guests */
 bool do_vpsci_0_1_call(struct cpu_user_regs *regs, uint32_t fid);
 bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid);
 
+int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
+                          register_t context_id);
+
 #endif /* __ASM_VPSCI_H__ */
 
 /*
diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index 7ba9ccd94b..22c3a5f544 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -10,32 +10,16 @@
 
 #include 
 
-static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
-                            register_t context_id)
+int vpsci_vcpu_up_prepare(struct vcpu *v, register_t entry_point,
+                   register_t context_id)
 {
-    struct vcpu *v;
-    struct domain *d = current->domain;
-    struct vcpu_guest_context *ctxt;
     int rc;
+    struct domain *d = v->domain;
     bool is_thumb = entry_point & 1;
-    register_t vcpuid;
-
-    vcpuid = vaffinity_to_vcpuid(target_cpu);
-
-    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
-        return PSCI_INVALID_PARAMETERS;
-
-    /* THUMB set is not allowed with 64-bit domain */
-    if ( is_64bit_domain(d) && is_thumb )
-        return PSCI_INVALID_ADDRESS;
-
-    if ( !test_bit(_VPF_down, &v->pause_flags) )
-        return PSCI_ALREADY_ON;
+    struct vcpu_guest_context *ctxt;
 
     if ( (ctxt = alloc_vcpu_guest_context()) == NULL )
-        return PSCI_DENIED;
-
-    vgic_clear_pending_irqs(v);
+        return -ENOMEM;
 
     memset(ctxt, 0, sizeof(*ctxt));
     ctxt->user_regs.pc64 = (u64) entry_point;
@@ -76,8 +60,37 @@ static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
     free_vcpu_guest_context(ctxt);
 
     if ( rc < 0 )
+        return rc;
+
+    return 0;
+}
+
+static int do_common_cpu_on(register_t target_cpu, register_t entry_point,
+                            register_t context_id)
+{
+    struct vcpu *v;
+    struct domain *d = current->domain;
+    int rc;
+    bool is_thumb = entry_point & 1;
+    register_t vcpuid;
+
+    vcpuid = vaffinity_to_vcpuid(target_cpu);
+
+    if ( (v = domain_vcpu(d, vcpuid)) == NULL )
+        return PSCI_INVALID_PARAMETERS;
+
+    /* THUMB set is not allowed with 64-bit domain */
+    if ( is_64bit_domain(d) && is_thumb )
+        return PSCI_INVALID_ADDRESS;
+
+    if ( !test_bit(_VPF_down, &v->pause_flags) )
+        return PSCI_ALREADY_ON;
+
+    rc = vpsci_vcpu_up_prepare(v, entry_point, context_id);
+    if ( rc )
         return PSCI_DENIED;
 
+    vgic_clear_pending_irqs(v);
     vcpu_wake(v);
 
     return PSCI_SUCCESS;
@@ -197,6 +210,48 @@ static void do_psci_0_2_system_reset(void)
     domain_shutdown(d,SHUTDOWN_reboot);
 }
 
+static int32_t do_psci_1_0_system_suspend(register_t epoint, register_t cid)
+{
+    int32_t rc;
+    struct vcpu *v;
+    struct domain *d = current->domain;
+    bool is_thumb = epoint & 1;
+
+    /* THUMB set is not allowed with 64-bit domain */
+    if ( is_64bit_domain(d) && is_thumb )
+        return PSCI_INVALID_ADDRESS;
+
+    /* SYSTEM_SUSPEND is not supported for the hardware domain yet */
+    if ( is_hardware_domain(d) )
+        return PSCI_NOT_SUPPORTED;
+
+    /* Ensure that all CPUs other than the calling one are offline */
+    domain_lock(d);
+    for_each_vcpu ( d, v )
+    {
+        if ( v != current && is_vcpu_online(v) )
+        {
+            domain_unlock(d);
+            return PSCI_DENIED;
+        }
+    }
+    domain_unlock(d);
+
+    rc = domain_shutdown(d, SHUTDOWN_suspend);
+    if ( rc )
+        return PSCI_DENIED;
+
+    d->arch.resume_ctx.ep = epoint;
+    d->arch.resume_ctx.cid = cid;
+    d->arch.resume_ctx.wake_cpu = current;
+
+    gprintk(XENLOG_DEBUG,
+            "SYSTEM_SUSPEND requested, epoint=0x%"PRIregister", cid=0x%"PRIregister"\n",
+            epoint, cid);
+
+    return rc;
+}
+
 static int32_t do_psci_1_0_features(uint32_t psci_func_id)
 {
     /* /!\ Ordered by function ID and not name */
@@ -214,6 +269,8 @@ static int32_t do_psci_1_0_features(uint32_t psci_func_id)
     case PSCI_0_2_FN32_SYSTEM_OFF:
     case PSCI_0_2_FN32_SYSTEM_RESET:
     case PSCI_1_0_FN32_PSCI_FEATURES:
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
     case ARM_SMCCC_VERSION_FID:
         return 0;
     default:
@@ -344,6 +401,23 @@ bool do_vpsci_0_2_call(struct cpu_user_regs *regs, uint32_t fid)
         return true;
     }
 
+    case PSCI_1_0_FN32_SYSTEM_SUSPEND:
+    case PSCI_1_0_FN64_SYSTEM_SUSPEND:
+    {
+        register_t epoint = PSCI_ARG(regs, 1);
+        register_t cid = PSCI_ARG(regs, 2);
+
+        if ( fid == PSCI_1_0_FN32_SYSTEM_SUSPEND )
+        {
+            epoint &= GENMASK(31, 0);
+            cid &= GENMASK(31, 0);
+        }
+
+        perfc_incr(vpsci_system_suspend);
+        PSCI_SET_RESULT(regs, do_psci_1_0_system_suspend(epoint, cid));
+        return true;
+    }
+
     default:
         return false;
     }
diff --git a/xen/arch/ppc/stubs.c b/xen/arch/ppc/stubs.c
index bdaf474c5c..0db0627b5c 100644
--- a/xen/arch/ppc/stubs.c
+++ b/xen/arch/ppc/stubs.c
@@ -224,6 +224,11 @@ void arch_domain_creation_finished(struct domain *d)
     BUG_ON("unimplemented");
 }
 
+int arch_domain_resume(struct domain *d)
+{
+    return 0;
+}
+
 int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
 {
     BUG_ON("unimplemented");
diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c
index 1a8c86cd8d..52532ae14d 100644
--- a/xen/arch/riscv/stubs.c
+++ b/xen/arch/riscv/stubs.c
@@ -198,6 +198,11 @@ void arch_domain_creation_finished(struct domain *d)
     BUG_ON("unimplemented");
 }
 
+int arch_domain_resume(struct domain *d)
+{
+    return 0;
+}
+
 int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
 {
     BUG_ON("unimplemented");
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 19fd86ce88..94a06bc697 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -1138,6 +1138,11 @@ void arch_domain_creation_finished(struct domain *d)
         hvm_domain_creation_finished(d);
 }
 
+int arch_domain_resume(struct domain *d)
+{
+    return 0;
+}
+
 #ifdef CONFIG_COMPAT
 #define xen_vcpu_guest_context vcpu_guest_context
 #define fpu_ctxt fpu_ctxt.x
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 104e917f07..667017c5e1 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -1352,6 +1352,7 @@ int domain_shutdown(struct domain *d, u8 reason)
 void domain_resume(struct domain *d)
 {
     struct vcpu *v;
+    int rc;
 
     /*
      * Some code paths assume that shutdown status does not get reset under
@@ -1361,6 +1362,13 @@ void domain_resume(struct domain *d)
 
     spin_lock(&d->shutdown_lock);
 
+    rc = arch_domain_resume(d);
+    if ( rc )
+    {
+        printk("%pd: Failed to resume domain (ret %d)\n", d, rc);
+        goto fail;
+    }
+
     d->is_shutting_down = d->is_shut_down = 0;
     d->shutdown_code = SHUTDOWN_CODE_INVALID;
 
@@ -1371,6 +1379,7 @@ void domain_resume(struct domain *d)
         v->paused_for_shutdown = 0;
     }
 
+ fail:
     spin_unlock(&d->shutdown_lock);
 
     domain_unpause(d);
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index e10baf2615..5f77ffadf1 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -109,6 +109,8 @@ int arch_domain_soft_reset(struct domain *d);
 
 void arch_domain_creation_finished(struct domain *d);
 
+int arch_domain_resume(struct domain *d);
+
 void arch_p2m_set_access_required(struct domain *d, bool access_required);
 
 int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c);
-- 
2.48.1



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Date: Sun, 31 Aug 2025 15:42:02 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v5 01/12] xen/arm: gicv3: refactor obtaining GIC addresses
 for common operations
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk ,
 Julien Grall 
References: 
 <7da58b5a27d61f75eaebb749a7ab4c72655a12cb.1756481577.git.leonid_komarianskyi@epam.com>
Content-Language: en-US
From: Oleksandr Tyshchenko 
In-Reply-To: <7da58b5a27d61f75eaebb749a7ab4c72655a12cb.1756481577.git.leonid_komarianskyi@epam.com>
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On 29.08.25 19:06, Leonid Komarianskyi wrote:

Hello Leonid


> Currently, many common functions perform the same operations to calculate
> GIC register addresses. This patch consolidates the similar code into
> a separate helper function to improve maintainability and reduce duplication.
> This refactoring also simplifies the implementation of eSPI support in future
> changes.
> 
> Signed-off-by: Leonid Komarianskyi 
> Reviewed-by: Volodymyr Babchuk 
> Acked-by: Julien Grall 

Reviewed-by: Oleksandr Tyshchenko 

with one NIT ...

> 
> ---
> Changes in V5:
> - fixed a minor nit: changed %d to %u in the warning message because the
>    IRQ number cannot be less than zero
> - added acked-by from Julien Grall
> 
> Changes in V4:
> - no changes
> 
> Changes in V3:
> - changed panic() in get_addr_by_offset() to printing warning and
>    ASSERT_UNREACHABLE()
> - added verification of return pointer from get_addr_by_offset() in the
>    callers
> - moved invocation of get_addr_by_offset() from spinlock guards, since
>    it is not necessarry
> - added RB from Volodymyr Babchuk
> 
> Changes in V2:
> - no changes
> ---
>   xen/arch/arm/gic-v3.c          | 114 +++++++++++++++++++++++----------
>   xen/arch/arm/include/asm/irq.h |   1 +
>   2 files changed, 81 insertions(+), 34 deletions(-)
> 
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index cd3e1acf79..29b7f68cba 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -445,17 +445,67 @@ static void gicv3_dump_state(const struct vcpu *v)
>       }
>   }
>   
> +static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)

  ... please use uint32_t for new code

(could probably updated on commit)


> +{
> +    switch ( irqd->irq )
> +    {
> +    case 0 ... (NR_GIC_LOCAL_IRQS - 1):
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD_RDIST_SGI_BASE + offset);
> +        case GICD_ICFGR:
> +            return (GICD_RDIST_SGI_BASE + GICR_ICFGR1);
> +        case GICD_IPRIORITYR:
> +            return (GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irqd->irq);
> +        default:
> +            break;
> +        }
> +    case NR_GIC_LOCAL_IRQS ... SPI_MAX_INTID:
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +        case GICD_ICENABLER:
> +        case GICD_ISPENDR:
> +        case GICD_ICPENDR:
> +        case GICD_ISACTIVER:
> +        case GICD_ICACTIVER:
> +            return (GICD + offset + (irqd->irq / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGR + (irqd->irq / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTER + irqd->irq * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYR + irqd->irq);
> +        default:
> +            break;
> +        }
> +    default:
> +        break;
> +    }
> +
> +    /* Something went wrong, we shouldn't be able to reach here */
> +    printk(XENLOG_WARNING "GICv3: WARNING: Invalid offset 0x%x for IRQ#%u",
> +           offset, irqd->irq);
> +    ASSERT_UNREACHABLE();
> +
> +    return NULL;
> +}
> +
>   static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_for_rwp)
>   {
>       u32 mask = 1U << (irqd->irq % 32);
> -    void __iomem *base;
> +    void __iomem *addr = get_addr_by_offset(irqd, offset);
>   
> -    if ( irqd->irq < NR_GIC_LOCAL_IRQS )
> -        base = GICD_RDIST_SGI_BASE;
> -    else
> -        base = GICD;
> +    if ( addr == NULL )
> +        return;
>   
> -    writel_relaxed(mask, base + offset + (irqd->irq / 32) * 4);
> +    writel_relaxed(mask, addr);
>   
>       if ( wait_for_rwp )
>           gicv3_wait_for_rwp(irqd->irq);
> @@ -463,15 +513,12 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_for_rwp)
>   
>   static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset)
>   {
> -    void __iomem *base;
> -    unsigned int irq = irqd->irq;
> +    void __iomem *addr = get_addr_by_offset(irqd, offset);
>   
> -    if ( irq >= NR_GIC_LOCAL_IRQS)
> -        base = GICD + (irq / 32) * 4;
> -    else
> -        base = GICD_RDIST_SGI_BASE;
> +    if ( addr == NULL )
> +        return false;
>   
> -    return !!(readl(base + offset) & (1U << (irq % 32)));
> +    return !!(readl(addr) & (1U << (irqd->irq % 32)));
>   }
>   
>   static void gicv3_unmask_irq(struct irq_desc *irqd)
> @@ -558,30 +605,28 @@ static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
>   static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type)
>   {
>       uint32_t cfg, actual, edgebit;
> -    void __iomem *base;
> -    unsigned int irq = desc->irq;
> +    void __iomem *addr;
>   
>       /* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
> -    ASSERT(irq >= NR_GIC_SGI);
> +    ASSERT(desc->irq >= NR_GIC_SGI);
>   
> -    spin_lock(&gicv3.lock);
> +    addr = get_addr_by_offset(desc, GICD_ICFGR);
> +    if ( addr == NULL )
> +        return;
>   
> -    if ( irq >= NR_GIC_LOCAL_IRQS)
> -        base = GICD + GICD_ICFGR + (irq / 16) * 4;
> -    else
> -        base = GICD_RDIST_SGI_BASE + GICR_ICFGR1;
> +    spin_lock(&gicv3.lock);
>   
> -    cfg = readl_relaxed(base);
> +    cfg = readl_relaxed(addr);
>   
> -    edgebit = 2u << (2 * (irq % 16));
> +    edgebit = 2u << (2 * (desc->irq % 16));
>       if ( type & IRQ_TYPE_LEVEL_MASK )
>           cfg &= ~edgebit;
>       else if ( type & IRQ_TYPE_EDGE_BOTH )
>           cfg |= edgebit;
>   
> -    writel_relaxed(cfg, base);
> +    writel_relaxed(cfg, addr);
>   
> -    actual = readl_relaxed(base);
> +    actual = readl_relaxed(addr);
>       if ( ( cfg & edgebit ) ^ ( actual & edgebit ) )
>       {
>           printk(XENLOG_WARNING "GICv3: WARNING: "
> @@ -600,16 +645,13 @@ static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type)
>   static void gicv3_set_irq_priority(struct irq_desc *desc,
>                                      unsigned int priority)
>   {
> -    unsigned int irq = desc->irq;
> +    void __iomem *addr = get_addr_by_offset(desc, GICD_IPRIORITYR);
>   
> -    spin_lock(&gicv3.lock);
> -
> -    /* Set priority */
> -    if ( irq < NR_GIC_LOCAL_IRQS )
> -        writeb_relaxed(priority, GICD_RDIST_SGI_BASE + GICR_IPRIORITYR0 + irq);
> -    else
> -        writeb_relaxed(priority, GICD + GICD_IPRIORITYR + irq);
> +    if ( addr == NULL )
> +        return;
>   
> +    spin_lock(&gicv3.lock);
> +    writeb_relaxed(priority, addr);
>       spin_unlock(&gicv3.lock);
>   }
>   
> @@ -1273,6 +1315,10 @@ static void gicv3_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
>   {
>       unsigned int cpu;
>       uint64_t affinity;
> +    void __iomem *addr = get_addr_by_offset(desc, GICD_IROUTER);
> +
> +    if ( addr == NULL )
> +        return;
>   
>       ASSERT(!cpumask_empty(mask));
>   
> @@ -1284,7 +1330,7 @@ static void gicv3_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
>       affinity &= ~GICD_IROUTER_SPI_MODE_ANY;
>   
>       if ( desc->irq >= NR_GIC_LOCAL_IRQS )
> -        writeq_relaxed_non_atomic(affinity, (GICD + GICD_IROUTER + desc->irq * 8));
> +        writeq_relaxed_non_atomic(affinity, addr);
>   
>       spin_unlock(&gicv3.lock);
>   }
> diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.h
> index fce7e42a33..5bc6475eb4 100644
> --- a/xen/arch/arm/include/asm/irq.h
> +++ b/xen/arch/arm/include/asm/irq.h
> @@ -29,6 +29,7 @@ struct arch_irq_desc {
>    */
>   #define NR_IRQS		1024
>   
> +#define SPI_MAX_INTID   1019
>   #define LPI_OFFSET      8192
>   
>   /* LPIs are always numbered starting at 8192, so 0 is a good invalid case. */



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Date: Sun, 31 Aug 2025 16:12:50 +0300
From: Leon Romanovsky 
To: Jason Gunthorpe 
Cc: Marek Szyprowski ,
	Abdiel Janulgue ,
	Alexander Potapenko ,
	Alex Gaynor ,
	Andrew Morton ,
	Christoph Hellwig , Danilo Krummrich ,
	iommu@lists.linux.dev, Jason Wang ,
	Jens Axboe , Joerg Roedel ,
	Jonathan Corbet , Juergen Gross ,
	kasan-dev@googlegroups.com, Keith Busch ,
	linux-block@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-nvme@lists.infradead.org, linuxppc-dev@lists.ozlabs.org,
	linux-trace-kernel@vger.kernel.org,
	Madhavan Srinivasan ,
	Masami Hiramatsu ,
	Michael Ellerman ,
	"Michael S. Tsirkin" ,
	Miguel Ojeda ,
	Robin Murphy , rust-for-linux@vger.kernel.org,
	Sagi Grimberg ,
	Stefano Stabellini ,
	Steven Rostedt ,
	virtualization@lists.linux.dev, Will Deacon ,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v4 09/16] dma-mapping: handle MMIO flow in
 dma_map|unmap_page
Message-ID: <20250831131250.GC10073@unreal>
References: 
 
 <20250828151730.GH9469@nvidia.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <20250828151730.GH9469@nvidia.com>

On Thu, Aug 28, 2025 at 12:17:30PM -0300, Jason Gunthorpe wrote:
> On Tue, Aug 19, 2025 at 08:36:53PM +0300, Leon Romanovsky wrote:
> > From: Leon Romanovsky 
> > 
> > Extend base DMA page API to handle MMIO flow and follow
> > existing dma_map_resource() implementation to rely on dma_map_direct()
> > only to take DMA direct path.
> 
> I would reword this a little bit too
> 
> dma-mapping: implement DMA_ATTR_MMIO for dma_(un)map_page_attrs()
> 
> Make dma_map_page_attrs() and dma_map_page_attrs() respect
> DMA_ATTR_MMIO.
> 
> DMA_ATR_MMIO makes the functions behave the same as dma_(un)map_resource():
>  - No swiotlb is possible
>  - Legacy dma_ops arches use ops->map_resource()
>  - No kmsan
>  - No arch_dma_map_phys_direct()
> 
> The prior patches have made the internl funtions called here support
> DMA_ATTR_MMIO.
> 
> This is also preparation for turning dma_map_resource() into an inline
> calling dma_map_phys(DMA_ATTR_MMIO) to consolidate the flows.
> 
> > @@ -166,14 +167,25 @@ dma_addr_t dma_map_page_attrs(struct device *dev, struct page *page,
> >  		return DMA_MAPPING_ERROR;
> >  
> >  	if (dma_map_direct(dev, ops) ||
> > -	    arch_dma_map_phys_direct(dev, phys + size))
> > +	    (!is_mmio && arch_dma_map_phys_direct(dev, phys + size)))
> >  		addr = dma_direct_map_phys(dev, phys, size, dir, attrs);
> 
> PPC is the only user of arch_dma_map_phys_direct() and it looks like
> it should be called on MMIO memory. Seems like another inconsistency
> with map_resource. I'd leave it like the above though for this series.
> 
> >  	else if (use_dma_iommu(dev))
> >  		addr = iommu_dma_map_phys(dev, phys, size, dir, attrs);
> > -	else
> > +	else if (is_mmio) {
> > +		if (!ops->map_resource)
> > +			return DMA_MAPPING_ERROR;
> 
> Probably written like:
> 
> 		if (ops->map_resource)
> 			addr = ops->map_resource(dev, phys, size, dir, attrs);
> 		else
> 			addr = DMA_MAPPING_ERROR;

I'm big fan of "if (!ops->map_resource)" coding style and prefer to keep it.

> 
> As I think some of the design here is to run the trace even on the
> failure path?

Yes, this is how it worked before.

> 
> Otherwise looks OK
> 
> Reviewed-by: Jason Gunthorpe 
> 
> Jason


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Date: Sun, 31 Aug 2025 17:08:47 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v5 04/12] xen/arm/irq: add handling for IRQs in the eSPI
 range
To: Leonid Komarianskyi 
Cc: Volodymyr Babchuk ,
 "xen-devel@lists.xenproject.org" ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel 
References: 
 
 <87tt1pykqz.fsf@epam.com>
Content-Language: en-US
From: Oleksandr Tyshchenko 
In-Reply-To: <87tt1pykqz.fsf@epam.com>
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On 29.08.25 22:45, Volodymyr Babchuk wrote:
> 
> Hi Leonid,

Hello Leonid

> 
> Leonid Komarianskyi  writes:
> 
>> Currently, Xen does not support eSPI interrupts, leading
>> to a data abort when such interrupts are defined in the DTS.
>>
>> This patch introduces a separate array to initialize up to
>> 1024 interrupt descriptors in the eSPI range and adds the
>> necessary defines and helper function. These changes lay the
>> groundwork for future implementation of full eSPI interrupt
>> support. As this GICv3.1 feature is not required by all vendors,
>> all changes are guarded by ifdefs, depending on the corresponding
>> Kconfig option.
>>
>> Signed-off-by: Leonid Komarianskyi 
>>
>> ---
>> Changes in V5:
>> - no functional changes introduced by this version compared with V4, only
>>    minor fixes and removal of ifdefs for macroses
>> - added TODO comment, suggested by Oleksandr Tyshchenko
>> - changed int to unsigned int for irqs
>> - removed ifdefs for eSPI-specific defines and macros to reduce the
>>    number of ifdefs and code duplication in further changes
>> - removed reviewed-by as moving defines from ifdefs requires additional
>>    confirmation from reviewers


Reviewed-by: Oleksandr Tyshchenko 

with the following addressed ...


>>
>> Changes in V4:
>> - removed redundant line with 'default n' in Kconfig, as it is disabled
>>    by default, without explicit specification
>> - added reviewed-by from Volodymyr Babchuk
>>
>> Changes in V3:
>> - introduced a new define NR_ESPI_IRQS to avoid confusion, like in the
>>    case of using NR_IRQS for espi_desc array
>> - implemented helper functions espi_to_desc and init_espi_data to make
>>    it possible to add stubs with the same name, and as a result, reduce
>>    the number of #ifdefs
>> - disable CONFIG_GICV3_ESPI default value to n
>>
>> Changes in V2:
>> - use (ESPI_MAX_INTID + 1) instead of (ESPI_BASE_INTID + NR_IRQS)
>> - remove unnecessary comment for nr_irqs initialization
>> ---
>>   xen/arch/arm/Kconfig           |  8 +++++
>>   xen/arch/arm/include/asm/irq.h | 24 +++++++++++++++
>>   xen/arch/arm/irq.c             | 56 +++++++++++++++++++++++++++++++++-
>>   3 files changed, 87 insertions(+), 1 deletion(-)
>>
>> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
>> index 17df147b25..43b05533b1 100644
>> --- a/xen/arch/arm/Kconfig
>> +++ b/xen/arch/arm/Kconfig
>> @@ -135,6 +135,14 @@ config GICV3
>>   	  Driver for the ARM Generic Interrupt Controller v3.
>>   	  If unsure, use the default setting.
>>   
>> +config GICV3_ESPI
>> +	bool "Extended SPI range support"
>> +	depends on GICV3 && !NEW_VGIC
>> +	help
>> +	  Allow Xen and domains to use interrupt numbers from the extended SPI
>> +	  range, from 4096 to 5119. This feature is introduced in GICv3.1
>> +	  architecture.
>> +
>>   config HAS_ITS
>>           bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORTED
>>           depends on GICV3 && !NEW_VGIC && !ARM_32
>> diff --git a/xen/arch/arm/include/asm/irq.h b/xen/arch/arm/include/asm/irq.h
>> index 5bc6475eb4..4443799648 100644
>> --- a/xen/arch/arm/include/asm/irq.h
>> +++ b/xen/arch/arm/include/asm/irq.h
>> @@ -32,6 +32,13 @@ struct arch_irq_desc {
>>   #define SPI_MAX_INTID   1019
>>   #define LPI_OFFSET      8192
>>   
>> +#define ESPI_BASE_INTID 4096
>> +#define ESPI_MAX_INTID  5119
>> +#define NR_ESPI_IRQS    1024
>> +
>> +#define ESPI_INTID2IDX(intid) ((intid) - ESPI_BASE_INTID)
>> +#define ESPI_IDX2INTID(idx)   ((idx) + ESPI_BASE_INTID)
>> +
>>   /* LPIs are always numbered starting at 8192, so 0 is a good invalid case. */
>>   #define INVALID_LPI     0
>>   
>> @@ -39,7 +46,15 @@ struct arch_irq_desc {
>>   #define INVALID_IRQ     1023
>>   
>>   extern const unsigned int nr_irqs;
>> +#ifdef CONFIG_GICV3_ESPI
>> +/*
>> + * This will also cover the eSPI range, as some critical devices
>> + * for booting Xen (e.g., serial) may use this type of interrupts.
>> + */
>> +#define nr_static_irqs (ESPI_MAX_INTID + 1)
>> +#else
>>   #define nr_static_irqs NR_IRQS
>> +#endif
>>   
>>   struct irq_desc;
>>   struct irqaction;
>> @@ -55,6 +70,15 @@ static inline bool is_lpi(unsigned int irq)
>>       return irq >= LPI_OFFSET;
>>   }
>>   
>> +static inline bool is_espi(unsigned int irq)
>> +{
>> +#ifdef CONFIG_GICV3_ESPI
> 
> Taking into account that with CONFIG_GICV3_ESPI=n we should never have
> "irq" in eSPI range, do you really need this #ifdef? I think that
> ASSERT_UNREACHABLE in espi_to_desc() is sufficient guard.
> 
> Also, IRQ line number belongs to eSPI range regardless of CONFIG_GICV3_ESPI,
> value, so in my opinion is_espi() should always return correct value for
> a given "irq".

  ... I agree with Volodymyr's suggestion for is_espi() to always return 
correct value for a given "irq".


> 
>> +    return (irq >= ESPI_BASE_INTID && irq <= ESPI_MAX_INTID);
> 
> Also, you don't need parentheses here.
> 
>> +#else
>> +    return false;
>> +#endif
>> +}
>> +
>>   #define domain_pirq_to_irq(d, pirq) (pirq)
>>   
>>   bool is_assignable_irq(unsigned int irq);
>> diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c
>> index b8eccfc924..61c915c3f9 100644
>> --- a/xen/arch/arm/irq.c
>> +++ b/xen/arch/arm/irq.c
>> @@ -19,7 +19,11 @@
>>   #include 
>>   #include 
>>   
>> +#ifdef CONFIG_GICV3_ESPI
>> +const unsigned int nr_irqs = ESPI_MAX_INTID + 1;
>> +#else
>>   const unsigned int nr_irqs = NR_IRQS;
>> +#endif
>>   
>>   static unsigned int local_irqs_type[NR_LOCAL_IRQS];
>>   static DEFINE_SPINLOCK(local_irqs_type_lock);
>> @@ -46,6 +50,53 @@ void irq_end_none(struct irq_desc *irq)
>>   }
>>   
>>   static irq_desc_t irq_desc[NR_IRQS - NR_LOCAL_IRQS];
>> +#ifdef CONFIG_GICV3_ESPI
>> +/*
>> + * TODO: Consider allocating an array dynamically if
>> + * there is a need to enable GICV3_ESPI by default.
>> + */
>> +static irq_desc_t espi_desc[NR_ESPI_IRQS];
>> +
>> +static struct irq_desc *espi_to_desc(unsigned int irq)
>> +{
>> +    return &espi_desc[ESPI_INTID2IDX(irq)];
>> +}
>> +
>> +static int __init init_espi_data(void)
>> +{
>> +    unsigned int irq;
>> +
>> +    for ( irq = ESPI_BASE_INTID; irq <= ESPI_MAX_INTID; irq++ )
>> +    {
>> +        struct irq_desc *desc = irq_to_desc(irq);
>> +        int rc = init_one_irq_desc(desc);
>> +
>> +        if ( rc )
>> +            return rc;
>> +
>> +        desc->irq = irq;
>> +        desc->action  = NULL;
>> +    }
>> +
>> +    return 0;
>> +}
>> +#else
>> +/*
>> + * This function is stub and will not be called if CONFIG_GICV3_ESPI=n,
>> + * because in this case, is_espi will always return false.

  This comment should also be updated.

>> + */
>> +static struct irq_desc *espi_to_desc(unsigned int irq)
>> +{
>> +    ASSERT_UNREACHABLE();
>> +    return NULL;
>> +}
>> +
>> +static int __init init_espi_data(void)
>> +{
>> +    return 0;
>> +}
>> +#endif
>> +
>>   static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc);
>>   
>>   struct irq_desc *__irq_to_desc(unsigned int irq)
>> @@ -53,6 +104,9 @@ struct irq_desc *__irq_to_desc(unsigned int irq)
>>       if ( irq < NR_LOCAL_IRQS )
>>           return &this_cpu(local_irq_desc)[irq];
>>   
>> +    if ( is_espi(irq) )
>> +        return espi_to_desc(irq);
>> +
>>       return &irq_desc[irq-NR_LOCAL_IRQS];
>>   }
>>   
>> @@ -79,7 +133,7 @@ static int __init init_irq_data(void)
>>           desc->action  = NULL;
>>       }
>>   
>> -    return 0;
>> +    return init_espi_data();
>>   }
>>   
>>   static int init_local_irq_data(unsigned int cpu)
> 



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Subject: Re: [PATCH] x86: introduce "hot" and "cold" page copying functions
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On 2025-08-29 02:29, Jan Beulich wrote:
> On 28.08.2025 23:33, Jason Andryuk wrote:
>> On 2025-08-28 05:17, Jan Beulich wrote:
>>> The present copy_page_sse2() is useful in case the destination page isn't
>>> going to get touched again soon, or if we want to limit churn on the
>>> caches. Just rename it, to fit the corresponding {clear,scrub}_page_*()
>>> naming scheme.
>>>
>>> For cases where latency is the most important aspect, or when it is
>>> expected that sufficiently large parts of a destination page will get
>>> accessed again soon after the copying, introduce a "hot" alternative.
>>> Again use alternatives patching to select between a "legacy" and an ERMS
>>> variant.
>>>
>>> Don't switch any callers just yet - this will be the subject of subsequent
>>> changes.
>>>
>>> Signed-off-by: Jan Beulich 
>>
>> Reviewed-by: Jason Andryuk 
> 
> Thanks.
> 
>>> To avoid the NOP padding (also in clear_page_hot()) we could use a double
>>> REP prefix in the replacement code (accounting for the REX one in the code
>>> being replaced).
>>
>> Did my tool chain do it automatically?
>>
>> 0000000000000000 <.altinstr_replacement>:
>>      0:	b9 00 10 00 00       	mov    $0x1000,%ecx
>>      5:	f3 f3 a4             	repz rep movsb %ds:(%rsi),%es:(%rdi)
> 
> Interesting. That looks like a bug to me, when source code merely has
> 
>          rep movsb
> 
> Did you also check what copy_page_movsq (i.e. "rep movsq") expands to?
> What gas version is this? With 2.45 I get
> 
> 0000000000000000 <.altinstr_replacement>:
>     0:	b9 00 10 00 00       	mov    $0x1000,%ecx
>     5:	f3 a4                	rep movsb (%rsi),(%rdi)
> 
> (the omission of segment indicators when there's no segment override is
> indeed a change in 2.45).

Oh, sorry, I forgot I had the extra rep in when I looked at the 
disassembly.  It is as you show.

Sorry for the noise.

-Jason


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On 2025-08-29 09:17, Anthony PERARD wrote:
> On Wed, Aug 27, 2025 at 11:01:59AM -0400, Jason Andryuk wrote:
>> On 2025-08-08 10:55, Anthony PERARD wrote:
>>> From: Anthony PERARD 
>>>
>>> To replace yajl.
>>>
>>> Introduce YAJL_LIBS variable, to be able to remove "-lyajl" later.
>>>
>>> Signed-off-by: Anthony PERARD 
>>
>> Should the two configure changes be merged and placed at the end of the
>> series?  That avoids a half implemented conversion in between.
> 
> It might be half-converted, but it's fully working. Every single patch
> introduce changes that can be use right away. I've actually make use of
> this possibility. On every single patch, we can run ./testidl, which
> will exercise both lib against each other.
> 
> ./testidl does LibxlObj-to-JSONstring and back and forth. So on the next
> commit, we would have JSON generated with json-c, which is then parsed
> with YAJL, to finally be generated to JSON with json-c again, then both
> JSON output are compared.
> 
> I've actually prepared the patch "libxl: Convert libxl__json_parse() to
> use json-c' last, then put it in front and check that ./testidl was
> still working.
> 
> This help me be confident enough that the conversion to json-c was
> correct.
> 
> So if we squash both config change, every patch until the config change
> would only introduce dead code.

Oh, I didn't realize that.  Yes, your approach sounds great.

Thanks,
Jason


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On 2025-08-29 02:59, Jan Beulich wrote:
> On 28.08.2025 19:16, Jason Andryuk wrote:
>> On 2025-08-28 12:11, Jan Beulich wrote:
>>> On 28.08.2025 09:28, Jan Beulich wrote:
>>>> On 28.08.2025 03:03, Jason Andryuk wrote:
>>>>> On 2025-04-02 09:58, Jan Beulich wrote:
>>>>>> --- a/xen/tools/symbols.c
>>>>>> +++ b/xen/tools/symbols.c
>>>>>
>>>>>> @@ -318,24 +334,42 @@ static void write_src(void)
>>>>>>     	printf("#else\n");
>>>>>>     	output_label("symbols_offsets");
>>>>>>     	printf("#endif\n");
>>>>>> -	for (i = 0; i < table_cnt; i++) {
>>>>>> +	for (i = 0, ends = 0; i < table_cnt; i++) {
>>>>>>     		printf("\tPTR\t%#llx - SYMBOLS_ORIGIN\n", table[i].addr);
>>>>>> +
>>>>>> +		table[i].addr_idx = i + ends;
>>>>>> +
>>>>>> +		if (!want_symbol_end(i)) {
>>>>>> +			/* If there's another symbol at the same address,
>>>>>> +			 * propagate this symbol's size if the next one has
>>>>>> +			 * no size, or if the next one's size is larger. */
>>>>>
>>>>> Why do we want to shrink the next symbol's size?
>>>>
>>>> First (see related post-commit-message remarks): In principle section symbols
>>>> could come with a size, too. That would break everything as long as we don't
>>>> strip those.
>>>>
>>>> The main reason though is that imo smallest granularity is what we want here,
>>>> together with predictability. One symbol with a huge size could cover
>>>> multiple other symbols with smaller sizes. We could omit that part of the
>>>> change here, but then the processing in the hypervisor would need to change,
>>>> to fish out the "best suitable" symbol when dealing with multiple ones at the
>>>> same address. Other changes may then also be needed to the tool, to have such
>>>> symbols come in a well-defined order (to keep the then-new code in the
>>>> hypervisor as simple as possible). Look for "aliased symbol" in
>>>> common/symbols.c to see how simplistic respective code is right now.
>>>
>>> Furthermore remember that we can't record sizes, but instead we insert fake
>>> symbols. Obviously there can be only one (at least in the present scheme).
>>> If we used too large a size, chances would increase that the end symbol (in
>>> the sorted table) would have to live past some other symbol, thus becoming
>>> that one's "end".
>>
>> The scenario I thought about is something like:
>>
>> a 0x100-0x10f
>> b 0x100-0x1ff
>> c 0x200-0x2ff
>>
>> If you shrink b, you are creating a hole that would otherwise be
>> assigned to b.
>>
>> But I agree avoiding huge sizes covering multiple small variables would
>> better be avoided.
>>
>> Do you have concrete examples to help illustrate the problem?
> 
> a 0x100-0x1ff
> b 0x100-0x10f
> c 0x110-0x11f
> 
> If we inserted an "end" label based on a's size, that would effectively be
> c's 2nd end symbol (and there may not be two "end" symbols in a row, unless
> we want to further complicate the symbol lookup logic).

Ok.

Reviewed-by: Jason Andryuk 

Thanks,
Jason


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Date: Sun, 31 Aug 2025 10:51:53 -0400
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Subject: Re: [XEN PATCH 06/11] libxl: convert libxl__json_object_to_yajl_gen
 to libxl__json_object_to_libjsonc_object
To: Anthony PERARD 
CC: , Anthony PERARD
	, Juergen Gross 
References: <20250808145602.41716-1-anthony@xenproject.org>
 <20250808145602.41716-7-anthony@xenproject.org>
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On 2025-08-29 09:56, Anthony PERARD wrote:
> On Wed, Aug 27, 2025 at 11:37:07AM -0400, Jason Andryuk wrote:
>> On 2025-08-08 10:55, Anthony PERARD wrote:
>>> +    case JSON_NUMBER:
>>> +        *jso_out = json_object_new_string(obj->u.string);
>>
>> Is JSON_NUMBER calling json_object_new_string() correct?  It looks like the
>> yajl code falls back to a string, so that is okay but surprising.
> 
> Yeah, I think that's correct.
> :-( maybe not. Even if we have these too comments:
> 
>      In libxl_internal.h, enum libxl__json_node_type:
>          /* number is store in string, it's too big to be a long long or a double */
>          JSON_NUMBER  = (1 << 4),
> 
>      In json_callback_number():
>          /* If the conversion fail, we just store the original string. */
> 
> With yajl, we call yajl_gen_number(), which probably write 2^128 as:
> 
>      340282366920938463463374607431768211456
> 
> but this new json-c generator would write instead:
> 
>      "340282366920938463463374607431768211456"
> 
> I guess we might be able to replicate the same behavior by using
> json_object_set_serializer() or json_object_new_double_s() (which use
> the former). But I don't know if it is worth the effort. I hope we won't
> have int bigger than 64 bits.

I didn't check, but I thought uint64_t is the biggest size libxl uses.

Regards,
Jason


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Date: Sun, 31 Aug 2025 17:56:39 +0300
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH v5 05/12] xen/arm: gicv3: implement handling of GICv3.1
 eSPI
To: Leonid Komarianskyi ,
 "xen-devel@lists.xenproject.org" 
Cc: Stefano Stabellini , Julien Grall
 , Bertrand Marquis ,
 Michal Orzel ,
 Volodymyr Babchuk 
References: 
 
Content-Language: en-US
From: Oleksandr Tyshchenko 
In-Reply-To: 
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On 29.08.25 19:06, Leonid Komarianskyi wrote:

Hello Leonid


> Introduced appropriate register definitions, helper macros,
> and initialization of required GICv3.1 distributor registers
> to support eSPI. This type of interrupt is handled in the
> same way as regular SPI interrupts, with the following
> differences:
> 
> 1) eSPIs can have up to 1024 interrupts, starting from the
> beginning of the range, whereas regular SPIs use INTIDs from
> 32 to 1019, totaling 988 interrupts;
> 2) eSPIs start at INTID 4096, necessitating additional interrupt
> index conversion during register operations.
> 
> In case if appropriate config is disabled, or GIC HW doesn't
> support eSPI, the existing functionality will remain the same.
> 
> Signed-off-by: Leonid Komarianskyi 
> 
> ---
> Changes in V5:
> - fixed minor nits, no functional changes: changed u32 to uint32_t and
>    added a comment noting that the configuration for eSPIs is the same as
>    for regular SPIs
> - removed ifdefs for eSPI-specific offsets to reduce the number of
>    ifdefs and code duplication in further changes
> - removed reviewed-by as moving offset from ifdefs requires additional
>    confirmation from reviewers


Reviewed-by: Oleksandr Tyshchenko 

> 
> Changes in V4:
> - added offsets for GICD_IGRPMODRnE and GICD_NSACRnE that are required
>    for vGIC emulation
> - added a log banner with eSPI information, similar to the one for
>    regular SPI
> - added newline after ifdef and before gic_is_valid_line
> - added reviewed-by from Volodymyr Babchuk
> 
> Changes in V3:
> - add __init attribute to gicv3_dist_espi_common_init
> - change open-codded eSPI register initialization to the appropriate
>    gen-mask macro
> - fixed formatting for lines with more than 80 symbols
> - introduced gicv3_dist_espi_init_aff to be able to use stubs in case of
>    CONFIG_GICV3_ESPI disabled
> - renamed parameter in the GICD_TYPER_ESPI_RANGE macro to espi_range
>    (name was taken from GIC specification) to avoid confusion
> - changed type for i variable to unsigned int since it cannot be
>    negative
> 
> Changes in V2:
> - move gic_number_espis function from
>    [PATCH 08/10] xen/arm: vgic: add resource management for extended SPIs
>    to use it in the newly introduced gic_is_valid_espi
> - add gic_is_valid_espi which checks if IRQ number is in supported
>    by HW eSPI range
> - update gic_is_valid_irq conditions to allow operations with eSPIs
> ---
>   xen/arch/arm/gic-v3.c                  | 83 ++++++++++++++++++++++++++
>   xen/arch/arm/include/asm/gic.h         | 22 +++++++
>   xen/arch/arm/include/asm/gic_v3_defs.h | 38 ++++++++++++
>   3 files changed, 143 insertions(+)
> 
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 29b7f68cba..4a7ce12f26 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -485,6 +485,36 @@ static void __iomem *get_addr_by_offset(struct irq_desc *irqd, u32 offset)
>           default:
>               break;
>           }
> +#ifdef CONFIG_GICV3_ESPI
> +    case ESPI_BASE_INTID ... ESPI_MAX_INTID:
> +    {
> +        uint32_t irq_index = ESPI_INTID2IDX(irqd->irq);
> +
> +        switch ( offset )
> +        {
> +        case GICD_ISENABLER:
> +            return (GICD + GICD_ISENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ICENABLER:
> +            return (GICD + GICD_ICENABLERnE + (irq_index / 32) * 4);
> +        case GICD_ISPENDR:
> +            return (GICD + GICD_ISPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ICPENDR:
> +            return (GICD + GICD_ICPENDRnE + (irq_index / 32) * 4);
> +        case GICD_ISACTIVER:
> +            return (GICD + GICD_ISACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICACTIVER:
> +            return (GICD + GICD_ICACTIVERnE + (irq_index / 32) * 4);
> +        case GICD_ICFGR:
> +            return (GICD + GICD_ICFGRnE + (irq_index / 16) * 4);
> +        case GICD_IROUTER:
> +            return (GICD + GICD_IROUTERnE + irq_index * 8);
> +        case GICD_IPRIORITYR:
> +            return (GICD + GICD_IPRIORITYRnE + irq_index);
> +        default:
> +            break;
> +        }
> +    }
> +#endif
>       default:
>           break;
>       }
> @@ -655,6 +685,55 @@ static void gicv3_set_irq_priority(struct irq_desc *desc,
>       spin_unlock(&gicv3.lock);
>   }
>   
> +#ifdef CONFIG_GICV3_ESPI
> +unsigned int gic_number_espis(void)
> +{
> +    return gic_hw_ops->info->nr_espi;
> +}
> +
> +static void __init gicv3_dist_espi_common_init(uint32_t type)
> +{
> +    unsigned int espi_nr, i;
> +
> +    espi_nr = min(1024U, GICD_TYPER_ESPIS_NUM(type));
> +    gicv3_info.nr_espi = espi_nr;
> +    /* The GIC HW doesn't support eSPI, so we can leave from here */
> +    if ( gicv3_info.nr_espi == 0 )
> +        return;
> +
> +    printk("GICv3: %d eSPI lines\n", gicv3_info.nr_espi);
> +
> +    /* The configuration for eSPIs is similar to that for regular SPIs */
> +    for ( i = 0; i < espi_nr; i += 16 )
> +        writel_relaxed(0, GICD + GICD_ICFGRnE + (i / 16) * 4);
> +
> +    for ( i = 0; i < espi_nr; i += 4 )
> +        writel_relaxed(GIC_PRI_IRQ_ALL,
> +                       GICD + GICD_IPRIORITYRnE + (i / 4) * 4);
> +
> +    for ( i = 0; i < espi_nr; i += 32 )
> +    {
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICENABLERnE + (i / 32) * 4);
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_ICACTIVERnE + (i / 32) * 4);
> +    }
> +
> +    for ( i = 0; i < espi_nr; i += 32 )
> +        writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPRnE + (i / 32) * 4);
> +}
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity)
> +{
> +    unsigned int i;
> +
> +    for ( i = 0; i < gicv3_info.nr_espi; i++ )
> +        writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTERnE + i * 8);
> +}
> +#else
> +static void __init gicv3_dist_espi_common_init(uint32_t type) { }
> +
> +static void __init gicv3_dist_espi_init_aff(uint64_t affinity) { }
> +#endif
> +
>   static void __init gicv3_dist_init(void)
>   {
>       uint32_t type;
> @@ -700,6 +779,8 @@ static void __init gicv3_dist_init(void)
>       for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
>           writel_relaxed(GENMASK(31, 0), GICD + GICD_IGROUPR + (i / 32) * 4);
>   
> +    gicv3_dist_espi_common_init(type);
> +
>       gicv3_dist_wait_for_rwp();
>   
>       /* Turn on the distributor */
> @@ -713,6 +794,8 @@ static void __init gicv3_dist_init(void)
>   
>       for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i++ )
>           writeq_relaxed_non_atomic(affinity, GICD + GICD_IROUTER + i * 8);
> +
> +    gicv3_dist_espi_init_aff(affinity);
>   }
>   
>   static int gicv3_enable_redist(void)
> diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h
> index 3fcee42675..1e747dcd99 100644
> --- a/xen/arch/arm/include/asm/gic.h
> +++ b/xen/arch/arm/include/asm/gic.h
> @@ -306,8 +306,26 @@ extern void gic_dump_vgic_info(struct vcpu *v);
>   
>   /* Number of interrupt lines */
>   extern unsigned int gic_number_lines(void);
> +#ifdef CONFIG_GICV3_ESPI
> +extern unsigned int gic_number_espis(void);
> +
> +static inline bool gic_is_valid_espi(unsigned int irq)
> +{
> +    return (irq >= ESPI_BASE_INTID &&
> +            irq < ESPI_IDX2INTID(gic_number_espis()));
> +}
> +#else
> +static inline bool gic_is_valid_espi(unsigned int irq)
> +{
> +    return false;
> +}
> +#endif
> +
>   static inline bool gic_is_valid_line(unsigned int irq)
>   {
> +    if ( gic_is_valid_espi(irq) )
> +        return true;
> +
>       return irq < gic_number_lines();
>   }
>   
> @@ -325,6 +343,10 @@ struct gic_info {
>       enum gic_version hw_version;
>       /* Number of GIC lines supported */
>       unsigned int nr_lines;
> +#ifdef CONFIG_GICV3_ESPI
> +    /* Number of GIC eSPI supported */
> +    unsigned int nr_espi;
> +#endif
>       /* Number of LR registers */
>       uint8_t nr_lrs;
>       /* Maintenance irq number */
> diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h
> index 2af093e774..3370b4cd52 100644
> --- a/xen/arch/arm/include/asm/gic_v3_defs.h
> +++ b/xen/arch/arm/include/asm/gic_v3_defs.h
> @@ -37,6 +37,44 @@
>   #define GICD_IROUTER1019             (0x7FD8)
>   #define GICD_PIDR2                   (0xFFE8)
>   
> +/* Additional registers for GICv3.1 */
> +#define GICD_IGROUPRnE               (0x1000)
> +#define GICD_IGROUPRnEN              (0x107C)
> +#define GICD_ISENABLERnE             (0x1200)
> +#define GICD_ISENABLERnEN            (0x127C)
> +#define GICD_ICENABLERnE             (0x1400)
> +#define GICD_ICENABLERnEN            (0x147C)
> +#define GICD_ISPENDRnE               (0x1600)
> +#define GICD_ISPENDRnEN              (0x167C)
> +#define GICD_ICPENDRnE               (0x1800)
> +#define GICD_ICPENDRnEN              (0x187C)
> +#define GICD_ISACTIVERnE             (0x1A00)
> +#define GICD_ISACTIVERnEN            (0x1A7C)
> +#define GICD_ICACTIVERnE             (0x1C00)
> +#define GICD_ICACTIVERnEN            (0x1C7C)
> +#define GICD_IPRIORITYRnE            (0x2000)
> +#define GICD_IPRIORITYRnEN           (0x23FC)
> +#define GICD_ICFGRnE                 (0x3000)
> +#define GICD_ICFGRnEN                (0x30FC)
> +#define GICD_IGRPMODRnE              (0x3400)
> +#define GICD_IGRPMODRnEN             (0x347C)
> +#define GICD_NSACRnE                 (0x3600)
> +#define GICD_NSACRnEN                (0x36FC)
> +#define GICD_IROUTERnE               (0x8000)
> +#define GICD_IROUTERnEN              (0x9FFC)
> +
> +#ifdef CONFIG_GICV3_ESPI
> +#define GICD_TYPER_ESPI_SHIFT        8
> +#define GICD_TYPER_ESPI_RANGE_SHIFT  27
> +#define GICD_TYPER_ESPI_RANGE_MASK   (0x1F)
> +#define GICD_TYPER_ESPI              (1U << GICD_TYPER_ESPI_SHIFT)
> +#define GICD_TYPER_ESPI_RANGE(espi_range) ((((espi_range) & \
> +        GICD_TYPER_ESPI_RANGE_MASK) + 1) * 32)
> +#define GICD_TYPER_ESPIS_NUM(typer)    \
> +        (((typer) & GICD_TYPER_ESPI) ? \
> +        GICD_TYPER_ESPI_RANGE((typer) >> GICD_TYPER_ESPI_RANGE_SHIFT) : 0)
> +#endif
> +
>   /* Common between GICD_PIDR2 and GICR_PIDR2 */
>   #define GIC_PIDR2_ARCH_MASK         (0xf0)
>   #define GIC_PIDR2_ARCH_GICv3        (0x30)



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Date: Sun, 31 Aug 2025 18:58:33 +0300
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Subject: Re: [PATCH v5 08/12] xen/arm: vgic: add resource management for
 extended SPIs
To: Leonid Komarianskyi ,
 Volodymyr Babchuk 
Cc: "xen-devel@lists.xenproject.org" ,
 Stefano Stabellini , Julien Grall ,
 Bertrand Marquis ,
 Michal Orzel 
References: 
 <4b13dea924eabf1370d3f31030f3eef48371de06.1756481577.git.leonid_komarianskyi@epam.com>
 <87y0r1x3g2.fsf@epam.com>
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From: Oleksandr Tyshchenko 
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On 29.08.25 23:45, Volodymyr Babchuk wrote:

Hello Leonid, Volodymyr

> 
> Hi Leonid,
> 
> Leonid Komarianskyi  writes:
> 
>> This change introduces resource management in the VGIC to handle
>> extended SPIs introduced in GICv3.1. The pending_irqs and
>> allocated_irqs arrays are resized to support the required
>> number of eSPIs, based on what is supported by the hardware and
>> requested by the guest. A new field, ext_shared_irqs, is added
>> to the VGIC structure to store information about eSPIs, similar
>> to how shared_irqs is used for regular SPIs.
>>
>> Since the eSPI range starts at INTID 4096 and INTIDs between 1025
>> and 4095 are reserved, helper macros are introduced to simplify the
>> transformation of indices and to enable easier access to eSPI-specific
>> resources. These changes prepare the VGIC for processing eSPIs as
>> required by future functionality.
>>
>> The initialization and deinitialization paths for vgic have been updated
>> to allocate and free these resources appropriately. Additionally,
>> updated handling of INTIDs greater than 1024, passed from the toolstack
>> during domain creation, and verification logic ensures only valid SPI or
>> eSPI INTIDs are used.
>>
>> The existing SPI behavior remains unaffected when guests do not request
>> eSPIs, GIC hardware does not support them, or the CONFIG_GICV3_ESPI
>> option is disabled.
>>
>> Signed-off-by: Leonid Komarianskyi 
>>
>> ---
>> Changes in V5:
>> - removed the has_espi field because it can be determined by checking
>>    whether domain->arch.vgic.nr_espis is zero or not
>> - since vgic_ext_rank_offset is not used in this patch, it has been
>>    moved to the appropriate patch in the patch series, which implements
>>    vgic eSPI registers emulation and requires this function
>> - removed ifdefs for eSPI-specific macros to reduce the number of ifdefs
>>    and code duplication in further changes
>> - fixed minor nit: used %pd for printing domain with its ID

@Leonid, thanks for optimizing the series, now it looks much better (the 
number of #ifdef-s is reduced, code is reused).


>>
>> Changes in V4:
>> - added has_espi field to simplify determining whether a domain is able
>>    to operate with eSPI
>> - fixed formatting issues and misspellings
>>
>> Changes in V3:
>> - fixed formatting for lines with more than 80 symbols
>> - introduced helper functions to be able to use stubs in case of
>>    CONFIG_GICV3_ESPI disabled, and as a result, reduce the number of
>>    #ifdefs
>> - fixed checks for nr_spis in domain_vgic_init
>> - updated comment about nr_spis adjustments with dom0less mention
>> - moved comment with additional explanations before checks
>> - used unsigned int for indexes since they cannot be negative
>> - removed unnecessary parentheses
>> - move vgic_ext_rank_offset to the below ifdef guard, to reduce the
>>    number of ifdefs
>>
>> Changes in V2:
>> - change is_espi_rank to is_valid_espi_rank to verify whether the array
>>    element ext_shared_irqs exists. The previous version, is_espi_rank,
>>    only checked if the rank index was less than the maximum possible eSPI
>>    rank index, but this could potentially result in accessing a
>>    non-existing array element. To address this, is_valid_espi_rank was
>>    introduced, which ensures that the required eSPI rank exists
>> - move gic_number_espis to
>>    xen/arm: gicv3: implement handling of GICv3.1 eSPI
>> - update vgic_is_valid_irq checks to allow operating with eSPIs
>> - remove redundant newline in vgic_allocate_virq
>> ---
>>   xen/arch/arm/include/asm/vgic.h |  12 ++
>>   xen/arch/arm/vgic.c             | 199 +++++++++++++++++++++++++++++++-
>>   2 files changed, 208 insertions(+), 3 deletions(-)
>>
>> diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h
>> index 3e7cbbb196..912d5b7694 100644
>> --- a/xen/arch/arm/include/asm/vgic.h
>> +++ b/xen/arch/arm/include/asm/vgic.h
>> @@ -146,6 +146,10 @@ struct vgic_dist {
>>       int nr_spis; /* Number of SPIs */
>>       unsigned long *allocated_irqs; /* bitmap of IRQs allocated */
>>       struct vgic_irq_rank *shared_irqs;
>> +#ifdef CONFIG_GICV3_ESPI
>> +    struct vgic_irq_rank *ext_shared_irqs;
>> +    int nr_espis; /* Number of extended SPIs */

It seems you have agreed (V4) that nr_espis could not be negative.

>> +#endif
>>       /*
>>        * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in
>>        * struct arch_vcpu.
>> @@ -243,6 +247,14 @@ struct vgic_ops {
>>   /* Number of ranks of interrupt registers for a domain */
>>   #define DOMAIN_NR_RANKS(d) (((d)->arch.vgic.nr_spis+31)/32)
>>   
>> +#ifdef CONFIG_GICV3_ESPI
>> +#define DOMAIN_NR_EXT_RANKS(d) (((d)->arch.vgic.nr_espis+31)/32)
>> +#endif
>> +#define EXT_RANK_MIN (ESPI_BASE_INTID/32)
>> +#define EXT_RANK_MAX ((ESPI_MAX_INTID+31)/32)
>> +#define EXT_RANK_NUM2IDX(num) ((num)-EXT_RANK_MIN)
>> +#define EXT_RANK_IDX2NUM(idx) ((idx)+EXT_RANK_MIN)
>> +
>>   #define vgic_lock(v)   spin_lock_irq(&(v)->domain->arch.vgic.lock)
>>   #define vgic_unlock(v) spin_unlock_irq(&(v)->domain->arch.vgic.lock)
>>   
>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
>> index 2bbf4d99aa..c9b9528c66 100644
>> --- a/xen/arch/arm/vgic.c
>> +++ b/xen/arch/arm/vgic.c
>> @@ -27,9 +27,82 @@
>>   
>>   bool vgic_is_valid_line(struct domain *d, unsigned int virq)
>>   {
>> +#ifdef CONFIG_GICV3_ESPI
>> +    if ( virq >= ESPI_BASE_INTID &&
>> +         virq < ESPI_IDX2INTID(d->arch.vgic.nr_espis) )
>> +        return true;
>> +#endif
>> +
>>       return virq < vgic_num_irqs(d);
>>   }
>>   
>> +#ifdef CONFIG_GICV3_ESPI
>> +/*
>> + * Since eSPI indexes start from 4096 and numbers from 1024 to
>> + * 4095 are forbidden, we need to check both lower and upper
>> + * limits for ranks.
>> + */
>> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
>> +{
>> +    return rank >= EXT_RANK_MIN &&
>> +           EXT_RANK_NUM2IDX(rank) < DOMAIN_NR_EXT_RANKS(d);
>> +}
>> +
>> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
>> +                                                       unsigned int rank)
>> +{
>> +    return &v->domain->arch.vgic.ext_shared_irqs[EXT_RANK_NUM2IDX(rank)];
>> +}
>> +
>> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int virq)
>> +{
>> +    return !test_and_set_bit(ESPI_INTID2IDX(virq) + vgic_num_irqs(d),
>> +                             d->arch.vgic.allocated_irqs);
>> +}
>> +
>> +static void arch_move_espis(struct vcpu *v)
> 
> I don't need you need a copy of arch_move_irqs(). Se below for more info.
> 
>> +{
>> +    const cpumask_t *cpu_mask = cpumask_of(v->processor);
>> +    struct domain *d = v->domain;
>> +    struct pending_irq *p;
>> +    struct vcpu *v_target;
>> +    unsigned int i;
>> +
>> +    for ( i = ESPI_BASE_INTID;
>> +          i < EXT_RANK_IDX2NUM(d->arch.vgic.nr_espis); i++ )
>> +    {
>> +        v_target = vgic_get_target_vcpu(v, i);
>> +        p = irq_to_pending(v_target, i);
>> +
>> +        if ( v_target == v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) )
>> +            irq_set_affinity(p->desc, cpu_mask);
>> +    }
>> +}
>> +#else
>> +static inline bool is_valid_espi_rank(struct domain *d, unsigned int rank)
>> +{
>> +    return false;
>> +}
>> +
>> +/*
>> + * This function is stub and will not be called if CONFIG_GICV3_ESPI=n,
>> + * because in this case, is_valid_espi_rank will always return false.
>> + */
>> +static inline struct vgic_irq_rank *vgic_get_espi_rank(struct vcpu *v,
>> +                                                       unsigned int rank)
>> +{
>> +    ASSERT_UNREACHABLE();
>> +    return NULL;
>> +}
>> +
>> +static inline bool vgic_reserve_espi_virq(struct domain *d, unsigned int virq)
>> +{
>> +    return false;
>> +}
>> +
>> +static void arch_move_espis(struct vcpu *v) { }
>> +#endif
>> +
>>   static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>>                                                     unsigned int rank)
>>   {
>> @@ -37,6 +110,8 @@ static inline struct vgic_irq_rank *vgic_get_rank(struct vcpu *v,
>>           return v->arch.vgic.private_irqs;
>>       else if ( rank <= DOMAIN_NR_RANKS(v->domain) )
>>           return &v->domain->arch.vgic.shared_irqs[rank - 1];
>> +    else if ( is_valid_espi_rank(v->domain, rank) )
>> +        return vgic_get_espi_rank(v, rank);
>>       else
>>           return NULL;
>>   }
>> @@ -117,6 +192,62 @@ int domain_vgic_register(struct domain *d, unsigned int *mmio_count)
>>       return 0;
>>   }
>>   
>> +#ifdef CONFIG_GICV3_ESPI
>> +static unsigned int vgic_num_spi_lines(struct domain *d)
>> +{
>> +    return d->arch.vgic.nr_spis + d->arch.vgic.nr_espis;
>> +}
>> +
>> +static int init_vgic_espi(struct domain *d)
>> +{
>> +    unsigned int i, idx;
>> +
>> +    if ( d->arch.vgic.nr_espis == 0 )
>> +        return 0;
>> +
>> +    d->arch.vgic.ext_shared_irqs =
>> +        xzalloc_array(struct vgic_irq_rank, DOMAIN_NR_EXT_RANKS(d));
>> +    if ( d->arch.vgic.ext_shared_irqs == NULL )
>> +        return -ENOMEM;
>> +
>> +    for ( i = d->arch.vgic.nr_spis, idx = 0;
>> +          i < vgic_num_spi_lines(d); i++, idx++ )
>> +        vgic_init_pending_irq(&d->arch.vgic.pending_irqs[i],
>> +                              ESPI_IDX2INTID(idx));
>> +
>> +    for ( i = 0; i < DOMAIN_NR_EXT_RANKS(d); i++ )
>> +        vgic_rank_init(&d->arch.vgic.ext_shared_irqs[i], i, 0);
>> +
>> +    return 0;
>> +}
>> +
>> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
> 
> I know that I should made this observation in previous version, but I
> didn't, sorry for that. Anyways, I don't think that this is a good idea
> to introduce this function and vgic_reserve_espi_virq(), as well as
> arch_move_espis(), actually, because in each case this is a code
> duplication, which is not good.
> 
> I think that instead you need to introduce a pair of helpers that will
> map any (e)SPI number to pending_irq[]/allocate_irqs index and back.
> 
> somethink like
> 
> static inline unsigned virq_to_index(int virq)
> {
>     if (is_espi(virq))
>         return ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
>     return virq;
> }
> 
> See below for examples.
> 
>> +{
>> +    irq = ESPI_INTID2IDX(irq) + d->arch.vgic.nr_spis;
>> +    return &d->arch.vgic.pending_irqs[irq];
>> +}
>> +#else
>> +static unsigned int init_vgic_espi(struct domain *d)
>> +{
>> +    return 0;
>> +}
>> +
>> +static unsigned int vgic_num_spi_lines(struct domain *d)
>> +{
>> +    return d->arch.vgic.nr_spis;
>> +}
>> +
>> +struct pending_irq *espi_to_pending(struct domain *d, unsigned int irq)
>> +{
>> +    return NULL;
>> +}
>> +#endif
>> +
>> +static unsigned int vgic_num_alloc_irqs(struct domain *d)
>> +{
>> +    return vgic_num_spi_lines(d) + NR_LOCAL_IRQS;
>> +}

I do not know where it would be better to put a comment related to 
non-visible in the patch context route_irq_to_guest(), but put it here.

I am afraid, the vgic_num_irqs(d) printed in the following error message 
is not entirely correct with your changes:

route_irq_to_guest():

...

     if ( !vgic_is_valid_line(d, virq) )
     {
         printk(XENLOG_G_ERR
                "the vIRQ number %u is too high for domain %u (max = %u)\n",
                irq, d->domain_id, vgic_num_irqs(d));
         return -EINVAL;
     }


>> +
>>   int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>>   {
>>       int i;
>> @@ -131,6 +262,36 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>>        */
>>       nr_spis = ROUNDUP(nr_spis, 32);
>>   
>> +#ifdef CONFIG_GICV3_ESPI
>> +    /*
>> +     * During domain creation, the dom0less DomUs code or toolstack specifies
>> +     * the maximum INTID, which is defined in the domain config subtracted by
>> +     * 32 to cover the local IRQs (please see the comment to VGIC_DEF_NR_SPIS).
>> +     * To compute the actual number of eSPI that will be usable for,
>> +     * add back 32.
>> +     */
>> +    if ( nr_spis + 32 > ESPI_IDX2INTID(NR_ESPI_IRQS) )
>> +        return -EINVAL;
>> +
>> +    if ( nr_spis + 32 >= ESPI_BASE_INTID )
>> +    {
>> +        d->arch.vgic.nr_espis = min(nr_spis - ESPI_BASE_INTID + 32, 1024U);
>> +        /* Verify if GIC HW can handle provided INTID */
>> +        if ( d->arch.vgic.nr_espis > gic_number_espis() )
>> +            return -EINVAL;
>> +        /*
>> +         * Set the maximum available number for regular
>> +         * SPI to pass the next check
>> +         */
>> +        nr_spis = VGIC_DEF_NR_SPIS;
>> +    }
>> +    else
>> +    {
>> +        /* Domain will use the regular SPI range */
>> +        d->arch.vgic.nr_espis = 0;
>> +    }
>> +#endif
>> +
>>       /* Limit the number of virtual SPIs supported to (1020 - 32) = 988  */
>>       if ( nr_spis > (1020 - NR_LOCAL_IRQS) )
>>           return -EINVAL;
>> @@ -145,7 +306,7 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>>           return -ENOMEM;
>>   
>>       d->arch.vgic.pending_irqs =
>> -        xzalloc_array(struct pending_irq, d->arch.vgic.nr_spis);
>> +        xzalloc_array(struct pending_irq, vgic_num_spi_lines(d));
>>       if ( d->arch.vgic.pending_irqs == NULL )
>>           return -ENOMEM;
>>   
>> @@ -156,12 +317,16 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
>>       for ( i = 0; i < DOMAIN_NR_RANKS(d); i++ )
>>           vgic_rank_init(&d->arch.vgic.shared_irqs[i], i + 1, 0);
>>   
>> +    ret = init_vgic_espi(d);
>> +    if ( ret )
>> +        return ret;
>> +
>>       ret = d->arch.vgic.handler->domain_init(d);
>>       if ( ret )
>>           return ret;
>>   
>>       d->arch.vgic.allocated_irqs =
>> -        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d)));
>> +        xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_alloc_irqs(d)));
>>       if ( !d->arch.vgic.allocated_irqs )
>>           return -ENOMEM;
>>   
>> @@ -195,9 +360,27 @@ void domain_vgic_free(struct domain *d)
>>           }
>>       }
>>   
>> +#ifdef CONFIG_GICV3_ESPI
>> +    for ( i = 0; i < d->arch.vgic.nr_espis; i++ )
>> +    {
>> +        struct pending_irq *p = spi_to_pending(d, ESPI_IDX2INTID(i));
>> +
>> +        if ( p->desc )
>> +        {
>> +            ret = release_guest_irq(d, p->irq);
>> +            if ( ret )
>> +                dprintk(XENLOG_G_WARNING, "%pd: Failed to release virq %u ret = %d\n",
>> +                        d, p->irq, ret);
>> +        }
>> +    }
>> +#endif
>> +
>>       if ( d->arch.vgic.handler )
>>           d->arch.vgic.handler->domain_free(d);
>>       xfree(d->arch.vgic.shared_irqs);
>> +#ifdef CONFIG_GICV3_ESPI
>> +    xfree(d->arch.vgic.ext_shared_irqs);
>> +#endif
>>       xfree(d->arch.vgic.pending_irqs);
>>       xfree(d->arch.vgic.allocated_irqs);
>>   }
>> @@ -331,6 +514,8 @@ void arch_move_irqs(struct vcpu *v)
>>           if ( v_target == v && !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) )
>>               irq_set_affinity(p->desc, cpu_mask);
>>       }
>> +
>> +    arch_move_espis(v);
>>   }
>>   
>>   void vgic_disable_irqs(struct vcpu *v, uint32_t r, unsigned int n)
>> @@ -538,6 +723,8 @@ struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq)
>>           n = &v->arch.vgic.pending_irqs[irq];
>>       else if ( is_lpi(irq) )
>>           n = v->domain->arch.vgic.handler->lpi_to_pending(v->domain, irq);
>> +    else if ( is_espi(irq) )
>> +        n = espi_to_pending(v->domain, irq);
>>       else
>>           n = &v->domain->arch.vgic.pending_irqs[irq - 32];
>>       return n;
>> @@ -547,6 +734,9 @@ struct pending_irq *spi_to_pending(struct domain *d, unsigned int irq)
>>   {
>>       ASSERT(irq >= NR_LOCAL_IRQS);
>>   
>> +    if ( is_espi(irq) )
>> +        return espi_to_pending(d, irq);
>> +
> 
> here you can just do
> 
> idx = virq_to_idx(virq);
> 
>>       return &d->arch.vgic.pending_irqs[irq - 32];
> 
> and
> 
> return &d->arch.vgic.pending_irqs[idx];
> 
> instead
> 
>>   }
>>   
>> @@ -668,6 +858,9 @@ bool vgic_reserve_virq(struct domain *d, unsigned int virq)
>>       if ( !vgic_is_valid_line(d, virq) )
>>           return false;
>>   
>> +    if ( is_espi(virq) )
>> +        return vgic_reserve_espi_virq(d, virq);
>> +
> 
> here you can just do
> 
> idx = virq_to_idx(virq)
> 
>>       return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs);
> 
> and then just
> 
> return !test_and_set_bit(idx, d->arch.vgic.allocated_irqs);
> 
> 
>>   }
>>   
>> @@ -685,7 +878,7 @@ int vgic_allocate_virq(struct domain *d, bool spi)
>>       else
>>       {
>>           first = 32;
>> -        end = vgic_num_irqs(d);
>> +        end = vgic_num_alloc_irqs(d);
>>       }
> 
> I thinj you need to recalculate "virq" value at the end of this
> function. You'll return index in bitfield, but this is not the same is
> IRQ number in case of eSPIs.

+1

  The helpers I mentioned before can help here.
> 
>>   
>>       /*
> 
> Lastly, I think that it is very wasteful to allocate pending_irqs as
> continuous array, because it will consist mostly of unused entries,
> especially with eSPIs enable. Probably, better approach will be to use radix
> tree. As a bonus, you can use IRQ line number as a key, and get rid of
> all these is_espi() checks and mappings between IRQ number and index in
> the array.  But this is a much more drastic change, and I don't think that it
> should be done in this patch series...
>